1993_Zilog_Digital_Signal_Processors_Data_Book 1993 Zilog Digital Signal Processors Data Book

User Manual: 1993_Zilog_Digital_Signal_Processors_Data_Book

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Digital Signal

Processors
Includes Specifications
for the following parts:

•
•
•
•
•

Z86C95
Z89COO
Z89120/920
Z89121/921
Z89320/321

Databook
DC 8299-03

DSP DATABOOK
TABLE OF CONTENTS
TITLE

PAGE

INTRODUCTION .................................................................................................................................1-1
Z86C95 Z8® DIGITAL SIGNAL PROCESSOR ........................................................................ 1-1
Z89COO 16-BIT DIGITAL SIGNAL PROCESSOR .................................................................. 2-1
Z89COO DSP ApPLICATION NOTE .........................................................................................3-1
"UNDERSTANDING

Q15 Two's

COMPLEMENT FRACTIONAL MULTIPLICATION"

Z89120, Z89920 (ROM LESS) 16-BIT MIXED SIGNAL PROCESSOR .......................... 4-1
Z89121, Z89921 (ROM LESS) 16-BIT MIXED SIGNAL PROCESSOR .......................... 5-1
Z89320 16-BIT MIXED SIGNAL PROCESSOR ......................................................................6-1
Z89321 16-BIT MIXED SIGNAL PROCESSOR ......................................................................7-1
SUPPORT PRODUCT INFORMATION ...........................................................................................8-1
SUPERINTEGRATION™ PRODUCTS GUIDE ..............................................................................S-1
LITERATURE GUIDE AND THIRD PARTY SUPPORT .............................................................. L-1
ZILOG'S SALES OFFICES, REPRESENTATIVES AND DISTRIBUTORS ................................ Z-1

Introduction

20!l7Rgg2U
16,.Blt Mixed Signal

1

--~---

a

INTRODUCTION
Zilog's Focus on Application Specific Products Helps You
Maintain Your Technological Edge
Zilog's DSP products are suitable for a broad range of applications, from general-purpose use
through speech synthesis and mass storage. Whichever device you choose, you'll find a
comprehensive feature set and easy-to-use development tools to speed your design time to
production.
Z86C95 CMOS Z8® Digital Signal Processor
The Z86C95 is a ROMless Z8 microcontrollerwith an embedded 16-bit DSP. This device is well
suited for servo control in mass storage applications, digital filtering in motor controllers and
non-interruptable power supplies. The slave DSP executes most instructions in a single clock
cycle, including 16-bit by 16-bit multiplication and accumulation. The Z86C95 has 16 digital
I/O lines, an 8-channel, 8-bit A-to-D converter with 2 ~s conversion time, an 8-bit D-to-A
converter with programmable gain, a PWM, UART, and SPI, three 16-bit timers with capture
and compare registers, a hardwired 16-bit by 16-bit multiplier and a 32-bitl16-bit divider for the
Z8. Support tools include demonstration boards, assemblers/linkers, and a real time trace
emulation system.
Z89COO 16-Bit Digital Signal Processor
With a high-performance single-cycle multiply/accumulate instruction and zero software
overhead pointer architecture, the Z89COO is an excellent choice for many DSP designs.
Flexible general-purpose I/O features, including a 16-bit address and data bus and a 16-bit
I/O bus, make it easy to configure even slow peripherals into the system. A comprehensive set
of development support tools makes it even easier to work with the Z89COO. This device offers
broad functionality in an affordable package for consumer and industrial product designs alike.
Z89120, Z89920 (ROMless) 16-Bit Mixed Signal Processor
Multiple-chip capability in a single-chip solution is the hallmark of the Z89120. Combining
16-bit DSP functions with an integrated 8-bit microcontroller and AID, D/A converters, it is an
optimal choice for communications applications including audio, fax, voice mail, modems and
data transmission, as the Z89120 can handle several of these functions without additional
hardware. Its very low power consumption and small footprint make it ideal for portable use,
or in applications requiring long-term continuous operation, such as security systems and other
supervisory instrumentation. The Z89920 is the ROM less version of the Z89120 device.
Z89121, Z89921 (ROMless) 16-Bit Mixed Signal Processor
The Z89121 system processor offers exceptional flexibility for applications like voice mail and
personal communications, which involve substantial 1/0 and storage requirements. Two Codec
ports allow extensive analog interfacing, and expanded DSP program memory space-plus a
32-Mbit DRAM interface-accommodates digital speech generation and storage. The Z8912's
compact design provides maximum space-efficiency for remote messaging and paging
applications. The Z89921 is the ROMless version of the Z89121 device.

1-1

Z89320 16-Bit Digital'Signal Processor
The Z89320 provides the computational power of the Z89COO at a cost effective price. This
device incorporates 512 bytes of RAM and 4K words of program ROM. Two general purpose
user inputs and two user outputs provide convenient peripheral monitoring or control. A
dedicated 16-bit 1/0 bus assists in transferring information to and from external peripherals. The
compact instruction set is standard to all Zilog DSP products and provides ease-of-use
programming. Applications include high-volume multimedia, digital audio, speech processing,
and system control.
Z8932116-Bit Digital Signal Processor
Building on the Z89320 feature set, the Z89321 integrates a dual codec interface to assist in
the transfer of analog signals to the processor. A standard 8-bit codec can be used to
communicate with the interface. An upgrade to the Z89321 will provide an expansion to the
interface capabilities to include 16-bit linear and 16-bit stereo codecs. This integration path
provides additional cost advantages to customers that use codecs for transfer of data.

1-2

Z86C95 Z8~ Digital
Signal Processor

Application Note

1

20, Z89920 (ROMless)
Mixed Signal Processor

Z89121!1 Z89921 (ROMless)
16.. Bit Mixed Signal Processor

II

CP2iUD,

PRELIMINARY PRODUCT SPECIFICATION

ZS6e95

CMOS Z8® DIGITAL
SIGNAL PROCESSOR

FEATURES
•

Complete Microcontroller, 16 I/O Lines, and up to
64 Kbytes of Addressable External Space Each for
Program and Data Memory

•

Embedded Reduced Instruction Set DSP (Digital Signal
Processor) for Digital Servo Control, with
16 x 16-Bit Multiply and Accumulate in One Clock
Cycle

•

On-Chip Oscillator that Accepts Crystal or External
Clock Drive

•

Full-Duplex UART

•

16-Bit Counter/Timers with Capture and Compare
Registers

•

Register Pointer for Short, Fast Instructions to Any One
of the 16 Working Register Groups

•

S-Channel, S-Bit AID Converter with Track and Hold
and Minimum Single Conversion Time of 2 lIS
•

Serial Peripheral Interface

•

S-Bit D/A Converter with Programmable Gain Stage
and a Maximum Settling Time of 3 lIS

•

Multiplexed and Demultiplexed Address/Data Bus

•

Single Channel 40/S0 kHz Pulse Width Modulator

•

Single +5V Power Supply, All I/O Pins TTL Compatible

•

256-Byte Register File, Including 236 General-Purpose
Registers, Four I/O Port Registers and 16 Status and
Control Registers

•

1.2 Micron CMOS Technology

•

Clock Speeds 20 and 24 MHz

•

16 x 16-Bit Hardwired Multiply and 32-Bit by 16-Bit
Divide, Exclusive of DSP

•

Three Low-Power Standby Modes; STOP, HALT, and
PAUSE

•

Four External Vectored Priority Interrupts for I/O,
Counter/Timers and UART

•

Flash EPROM WritEf Support

GENERAL DESCRIPTION
The ZS6C95 MCU (Microcontroller Unit) introduces a new
level of sophistication to Superintegration™. The ZS6C95
is a member of the ZSII single-chip microcontroller family
incorporating a CMOS ROM less ZS microcontrollerwith an
embedded DSP processor for digital servo control. The
DSP slave processor can perform 16 x 16-bit multiplicates
and accumulates in one clock cycle. Additionally, the
ZS6C95 is further enhanced with a hardwired 16 x 16-bit
multiplier and 32-bit/16-bit divider, three 16-bit counter
timers with capture and compare registers, a half flash Sbit AID converter with a 2 lIS conversion time, an S-bit DAC
with 1/4 programmable gain stage, UART, serial peri ph-

eral interface, and a PWM output channel (Figure 1). It is
fabricated using 1.2 micron CMOS technology and offered
in an SO-pin QFP, S4-pin PLCC package, or a 100-pin
VQFP (Figures 2, 3, and 4).
The ZS6C95 provides up to 16 output address lines. This
permits an address space of up to 64 Kbytes of data and
program memory each. Eight address outputs (AD?-ADO)
are provided by a multiplexed, S-bit, Address/Data bus.
The remaining eight bits are provided through output
address bits A 15-AS.

1-1

Z86C95

PRELIMINARY

Z8~DSP

GENERAL DESCRIPTION (Continued)
There are 256 registers located on chip and organized as
236 general-purpose registers, 16 control and status registers, and four I/O port registers. The register file can be
divided into 16 groups of 16 working registers each.
Configuration of the registers in this manner allows the use
of short format instructions; in addition, any of the individual registers can be accessed directly. The Z86C95
contains 256 words of DSP Program RAM configured from
the Z8 side as 512 bytes of RAM and 128 words of DSP
data RAM.

Output Input

Vcc

GND

~

~

Notes:
All Signals with a preceding front slash, "t', are active Low, e.g.,
B/NJ (WORD is active Low); IBNJ (BYTE is active Low, only).
Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power
Ground

XTAL lAS IDS RlNJ IRESET !WAIT

Machine Timing and
Instruction Control

ALU
Flags

Register
Pointer
Register File
256 x a-Bit

Digital Signal Processor

*In multiplexed mode A7-AO reflects
the DSP address bus for emulation

I/O

(Bit Programmable)

AddresslData

a Channel
Analog In

Figure 1. Functional Block Diagram

1-2

Analog
Out

PWM

Z86C95

PRELIMINARY

ZS'"DSP

PIN DESCRIPTION

6463"6261 6059585756 5554535251 50494847464544434241
P2(0)
P2(1)
P2(2)
P2(3)
P2(4)
P2(5)
P2(6)
P2(7)
VSS
ANGND

Avec
VAHI
VALO
ANA(O)
ANA(1)
ANA(2)

~

A3

~

~

67
68
69
70
71

38
37
36
35
34
33
ZS6C95
SO·Pin QFP
32
31
30
29
28
27
26
25
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

A2
A1

~

72

73
74
75
76
77

78
79
80
1

AD
ADO
VSS

AD1
AD2

AD3
AD4

AD5
AD6

AD7
R/W

IDS
lAS

Figure 2. SO-Pin QFP Pin Assignments

1·3
---

--~--~-~--~----

Z86C95

PRELIMINARY

*2il..£lG

Z8~DSP

PIN DESCRIPTION (Continued)
Table 1. SO-Pin QFP Pin Identification
No.

Symbol

Function

Direction

1-5
6
7
8
9

ANA(3)-ANA(7)
VD LO
DAC
VD H1
VDD

Input to A/D
low Ref Volt, DAC
D/A Converter Output
High Ref Volt, DAC
Digital Power Supply

Input
Input
Output
Input
Input

10-12
13-16
17
18
19

P3(7)-P3(5)
P3(3)-P3(0)
XTAl1
XTAl2
PWM

Port 3, Pins 7,6,5
Port 3, Pins 3,2,1,0
Crystal, OSC ClK
Crystal, OSC ClK
Pulse Width Modulator

Output
Input
Input
Output
Output

20
21
22
23
24

/RESET
SClK
SYNC
lACK
P3(4)

Reset
System Clock
Synchronize Pin
Interrupt Acknowledge
Port 3, Pin 4

Input
Output
Output
Output
Output

25
26
27
28-34
35

/AS
/DS
R//W
AD7-AD1
Vss

Address Strobe
Data Strobe
Read/Write
MUX ADD/DATA, Pins 7-1
Digital Ground

Output
Output
Output
Input/Output
Input

36
37-52
53
54
55

ADO
AO-A15
Vss
VDD
DO

MUX ADD/DATA, Pin 0
External Address
Digital Ground
Digital Power Supply
SPI Data Out

Input/Output
Output
Input
Input
Output

56
57
58
59
60

DI
SK
SLAVESEl
DSP_RW
DSP_SYNC

SPI Data In
SPI Clock
Slave Select
DSP Emulation R/W Pin
DSP Emulation Sync Pin

Input
Input/Output
Input
Output
Output

61-62
63
64
65-72
73

C02-CO 1
DSP_SSN
/WAIT
P2(0)-P2(7)
Vss

Compare Outputs for Timer 2
DSP Emulation Single Step Pin
Wait
Port 2, Pins 0-7
Digital Ground

Output
Input
Input
Input, Output
Input

74
75
76

ANGND
AVec
VAH1
VALO
ANA(0)-ANA(2)

Analog Ground
Analog Power Supply
High Ref Volt, AID
low Ref Volt, AID
Input to AID

Input
Input
Input
Input
Input

77
78-80

1-4

~2i1..(]l;

Z86C95
Z8 Z
«z «z ::;;:
~ 0
0
.....
co .,., ....
N
z z -' :E c.:> C!l en
!2
N c..
N
N
N
N
N
« « « ~ ~ :?c :2
:2 «
« en
c.. '"
c.. c.. c.. c.. c.. '"
> c..
C")

N

C")

t-

~

~I
Z en
Cl

c.:>

84
ANA4
ANA5
ANA6
ANA7
VOLO
OAC
VOHI
VOO
P37
P36
P35
P33
P32
P31
P30
XTAL1
XTAL2

75
74

Z86C95
84-Pin PlCC

PWM

IRESET
SCLK
SYNC

32

33

54
53

42 43
:.<:

~ c.:>
s;

....
~

en en

::!:

~

~

.....
Cl
«

co

Cl

«

.,., ....
Cl Cl
«

«

0
Ei en Cl
~ ::;;: ~ ~
Cl
« «'" « gz «
C")

Cl

~

C01
CO2
DSP_SYNC
OSP_RW
SLAVESEL
SK
01
00
VOO
VSS
A15
A14
A13
A12
A11
A10
A9
AS
A7
A6
A5

:::::

en

Cl

Figure 3. 84-Pin PLCC Pin Assignments

1-5

--~-~-

~---

------~~

~2j1..CG

Z86C95

PRELIMINARY

Z8~DSP

PIN DESCRIPTION (Continued)
Table 2. 84-Pin PLCC Pin Identification

1-6

No.

Symbol

Function

Direction

1
2
3
4
5

P27
Vss
AN GNO
AVec
VA H1

Port 2 Pin 7
Digital Ground
Analog Ground
Analog Power Supply
High Ref Volt, AID

Input/Output
Input
Input
Input
Input

6
7-10
12-15
16
17

VALO
ANAO·ANA3
ANA4-ANA7
VD LO
DAC

Low Ref Volt, A/D
Input to A/D, Pins 0-3
Input to AD, Pins 5-7
Low Ref Volt, DAC
D/A Converter Output

Input
Input
Input
Input
Output

18
19
20-22
23-26
27

VD H1
Voo
P37-P35
P33-P30
XTAL1

High Ref Volt, DAC
Digital Power Supply
Port 3, Pins 7-5
Port 3, Pins 3-0
Crystal, OSC CLK

Input
Input
Output
Input
Input

28
29
30
31
32

XTAL2
PWM
/RESET
SCLK
SYNC

Crystal, OSC CLK
Pulse Width Modulator
Reset
System Clock
Z8 Emulation Sync Pin

Output
Output
Input
Output
Output

33
34
35
36
37

N/C
lACK
P34
/AS
/DS

No Connection
Interrupt Acknowledge
Port 3, Pin 4
Address Strobe
Data Strobe

Output
Output
Output
Output

38
39-45
46
47
48-51

R//W
AD7-AD1
Vss
ADO
AO-A3

Read/Write
MUX ADD/DATA, Pins 7-1
Digital Ground
MUX ADO/DATA Pin 0
External Address

Output
Input/Output
Input
Input/Output
Output

52
53
54-64
65
66

DSP-A8
A4
A5-A15
Vss
Voo

MSB of DSP PC
External Address
External Address
Digital Ground
Digital Power Supply

Output
Output
Output
Input
Input

67
68
69
70
71

DO
DI
SK
SLAVESEL
DSP_RW

SPI Data Out
SPI Data In
SPI Clock
Slave Select
DSP Emulation R/W Pin

Output
Input
Input/Output
Input
Output

72
73-74
75
76
77
78-84

DSP_SYNC
C02-CO 1
DSP_SSN
N/C
/WAIT
P20-P26

DSP Emulation SYNC Pin
Compare Outputs for Timer 2
DSP Emulation Single Step Pin
No Connection
Wait
Port 2, Pins 0-6

Output
Output
Output
Input
Input/Output

Z86C95

PRELIMINARY

A4
A5

50

40

45

Z8~DSP

35

30

25

A6
A7
A8
A9

20

55

A10
A11
A12
A13

XTAL1

60

15

A14
A15

VSS
VDD
NC
DO

Z86C95
100-Pln VQFP

65

10

D1

SK
SLAVESEL
DSP_RW
DSP_SYNC

5

70

C02
C01

DSP_SSN
/WAIT

NC
SYNC
SCLK
NC
RESET
PWM
XTAL2
P30
P31
P32
P33
P35
P36
P37

VDD
VDHI
DAC
VDLO
ANA?
ANA6
ANA5
ANA4

75

80

85

90

95

NC
NC

Figure 4. 100-Pin VQFP Pin Assignments

1-7

*2iUlG

Z86C95
Z8"'DSP

PRELIMINARY

PIN DESCRIPTION (Continued)
Table 3. 100-Pin VQFP Pin Identification

1-8

No.

Symbol

Function

Direction

1-2
3-6
7
8
9
10
11-13
14-17
18
19

N/C
ANA4-ANA7
VDlO
DAC
VDHI
VDD
P37-P35
P33-P30
XTAl1
XTAl2

No Connection
Input to AD, Pins 5-7
low Ref Volt, DAC
D/A Converter Output
High Ref Volt, DAC
Digital Power Supply
Port 3, Pins 7-5
Port 3, Pins 3-0
Crystal, OSC ClK
Crystal, OSC ClK

Input
Input
Output
Input
Input
Output
Input
Input
Output

20
21
22
23
24
25-28
29
30
31
32

PWM
/RESET
N/C
SClK
SYNC
N/C
lACK
P34
/AS
/DS

Pulse Width Modulator
Reset
No Connection
System Clock
Synchronize Pin
No Connection
Interrupt Acknowledge
Port 3, Pin 4
Address Strobe
Data Strobe

33
34-40
41
42
43-46
47
48-50
51-62
63
64

R//W
AD7-AD1
VSS
ADO
AO-A3
DSP-A8
N/C
A5-A15
VSS
VDD

Read/Write
MUX ADD/OATA, Pins 7-1
Digital Ground
MUX ADO/OATA Pin 0
External Address
MSB of DSP PC
No Connection
External Address
Digital Ground
Digital Power Supply

65
66
67
68
69
70
71
72-73
74
75

N/C
DO
01
SK
SLAVESEl
DSP_RW
DSP_SYNC
C02-C01
DSP_SSN
/WAIT

No Connection
SPI Data Out
SPI Data In
SPI Clock
Slave Select
DSP Emulation R/W Pin
DSP Emulation SYNC Pin
Compare Outputs for Timer 2
DSP Emulation Single Step Pin
Wait

76-77
78-85
86
87-89
90
91
92
93
94-97
98-100

N/C
P20-P27
VSS
N/C
ANGND
AVCC
VAHI
VAlO
ANAO-ANA3
N/C

No Connection
Port 2, Pins 0-6
Digital Ground
No Connection
Analog Ground
Analog Power Supply
High Ref Volt, NO
low Ref Volt, NO
Input to NO, Pins 0-3
No Connection

Output
Input
Output
Output
Output
Output
Output
Output
Output
Input/Output
Input
Input/Output
Output
Output
Output
Input
Input
Output
Input
Input/Output
Input
Output
Output
Output
Output
Input
Input/Output
Input
Input
Input
Input
Input
Input

Z86C95

PRELIMINARY

Z8~DSP

PIN FUNCTIONS

::;

Address
A15-AO

A7-AO
(DSP Emulator
Support)

~

A15
A14
A13
A12
A11
A10
A9
AS
A7
A6
A5

""u'"
~ ~ ~
- Ie g;

'"~

AN7
AN6

c

AN5
AN4
AN3

Analog
Inputs
To NO

AN2
AN1
ANO

M
A3
A2
A1
AO

VDHI

Z86e95

DAC Output
PWM Output

ADO
AD1
AD2

SLAVESEL

AD3

SK

SPI Slave Select
SPI Clock

AD4
ADS
AD6
AD7

.., .... on
N
<>- ~ ~ ~ ~ ~

:i0

Port 2
(Btt Programmable 110)

~

N

~

.., ....

on
~~ ~

Port 3

co .....
~ ~

0

~ ~

/WAIT

Asynchronous
WAIT States

NO
Ref Voltage

Figure 5. Pin Functions

IDS (output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of IDS. For
WRITE operations, the falling edge of IDS indicates that
output data is valid. Data Strobe will tri-state in reset.

lAS (output, active LOw). Address Strobe is pulsed once at
the beginning of each machine cycle. Memory address
transfers are valid at the trailing edge of lAS. Under
program control, lAS can be placed in the highimpedance state along with Port 1, Data Strobe, and Readl
/Write.

1-9

PRELIMINARY

ZS6C95
ZS"'DSP

PIN FUNCTIONS (Continued)
/RESET (input, active Low). To avoid asynchronous and
noisy reset problems, the Z86C95 is equipped with a reset
filter of four external clocks (4TpC). If the external/RESET
signal is less than 4TpC in duration, no reset occurs.

SK (input, output). SPI clock.

On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC/2. When
/RESET is deactivated, program execution begins at location OOOCH. Reset time must be held Low for 50 ms or until
VDD is stable, whichever is longer.

00 (output, active High). SPI serial data output.

XTAL 1, XTAL2 Crystal 1, CrystaI2(time-based input and
output, respectively). These pins connect a parallelresonant crystal, ceramic resonator, LC, or any external
single-phase clock to the on-chip oscillator and buffer.

RI!W (output, read High/write Low). The Read/Write signal
is low when the MCU is writing to the external program or
data memory. Will tri-state in reset.

01 (input, active High). SPI serial data input in both master
and slave mode.

!WAIT (input, active Low). Introduces asynchronous wait
states into the external memory fetch cycle. When this
input goes Low during an external memory access, the Z8
freezes the fetch cycle until this pin goes High. This pin is
sampled after /DS goes Low; should be pulled up if not
used.
VAH1 (input). Reference voltage (High) for the AID converter.
VALO (input). Reference voltage (Low) for the AID converter.
ANVcc (input). Analog power supply for AID and D/A.
ANGND (input). Analog ground for AID and D/A.

A15-A8 (output). Demultiplexed high byte of Z8 external
address bus. Auto Latch when in reset.
A7-AO (output). Demultiplexed low byte of Z8 external
address bus or internal DSP address bus.
A07-AOO (input, output). Multiplexed Z8 address/data
bus. Auto Latch when in reset.
AN7-ANO (analog input). Analog inputs to the A/D con-

VO H1 (input). Reference voltage (High) for D/A converter.
VOLO (input). Reference voltage (Low) for D/A converter.
SSTEP (input, active High). DSP single-step control pin.
The DSP processor will execute a NOP instruction and
hold the program counter value when this pin is High.
/SSTEP is synchronized with the system clock; should be
pulled Low if not used.

verter.

OAC (output). Analog output of the D/A converter.
PWM (output). Pulse Width Modulator output. Open-Drain.
C01 (output). Compare output1 for timer T2.
C02 (output). Compare output2 for timer T2.
SLAVESEL (input, active Low). SPI Slave Select is used
in Slave mode to mark the beginning and end of a transaction.

1-10

SCLK System Clock (output). The internal system clock is
available at this pin.
lACK Interrupt Acknowledge (output, active High). This
output, when High, indicates that the Z86C95 is in an
interrupt cycle.
ISYNC (output, active Low). This signal indicates the last
clock cycle of the currently executing instruction.

Z86C95
lr'DSP

PRELIMINARY
Port 2 (P27-P20). Port 2 is an a-bit, bit programmable,
bidirectional, CMOS compatible port. Each of these eight
I/O lines can be independently programmed as an input or
output or globally as an open-drain output. Port 2 is always
available for I/O operation. When used as an I/O port, Port
2 may be placed under handshake control. In this configu-

ration, Port 3 lines P31 (Port 3, bit 1) and P36 are used as
the handshake controls lines/DAV2 and RDY2. The handshake signal assignment for Port 3 lines P31 and P36 is
dictated by the direction (input or output) assigned to P27
(Figure 6).

Port 2 (I/O)
Z86C95

MCU

t---~~ }

Handshake Controls
IDAV2 and RDY2
(P31 and P36)

Open-Drain

OEN

Out

.--I.~ 2.3 Hysteresis
In

r
I

iI

I
I
I

I
I
I

I
I

I

R .. 500 K.Q

Auto Latch

I

~------------------------~

Figure 6. Port 2 Configuration

1-11

Z86C95

PRELIMINARY

Z8~DSP

PIN FUNCTIONS (Continued)
Port 3 (P37-P30). Port3 is an a-bit, CMOS compatible fourfixed input and four-fixed output port. These a I/O lines
have four-fixed (P33-P30) input and four-fixed (P37-P34)

output ports (Table 3). Port 3 P30 and P37, when used as
serial I/O, are programmed as serial in and serial out,
respectively (Figure 7).

Z86C95
MCU

..
.

-

Port 3
(110 or Control)

_

Figure 7. Port 3 Configuration

Port 3 is configured under software control to provide the
following control functions: Handshakes for Ports 2 (lOAV
and ROY); four external interrupt request signals (IR03IROO); timer input and output signals (TIN and ToUT)' and
Data Memory Select (10M).

Port 3 lines P37 and P30, can be programmed as serial
I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate is controlled by the Counter/
TimerO.

Table 4. Port 3 Pin Assignments

1-12

Pin#

110

CTC1

Int.

P30
P31
P32
P33

In
In
In
In

TIN

IR03
IR02
IROO
IR01

P34
P35
P36
P37

Out
Out
Out
Out

P2HS

UART

Ext.

Serial In
D/R

/OM
ToUT

R/O
Serial Out

Z86C95

PRELIMINARY
The Z86C95 automatically adds a start bit and two stop bits
to transmitted data (Figure 8). Odd parity is also available
as an option. Eight data bits are always transmitted,
regardless of parity selection. If parity is enabled, the
eighth bit is the odd parity bit. An interrupt request (IRQ4)
is generated on all transmitted characters.
Received data must have a start bit, eight data bits and at
least one stop bit. If parity is On, bit 7 of the received data

Transmitted Data (No Parity)

I

T

Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs that are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level
rather, than a floating node, reduces excessive supply
current flow in the input buffer.

1~lwl~I~I~lool~I~loolfil

L

L

Start Bit

Start Bit

Eight Data Bits

Eight Data Bits

Two Stop BHs

One Stop Bit

Transmitted Data (With Parity)

Received Data (With Parity)

L

_ _

I,

is replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.

Received Data (No Parity)

ISP 1SP 107 106 1051 04 1031 021 01 1DO 1ST 1

~

Z8~DSP

Start Bit
Seven Data Bits

Start Bit
Seven Data Bits

Odd Parity

Parity Error Flag

Two Stop Bits

One Stop Bit

Figure 8. Serial Data Formats

1-13

PRELIMINARY

Z86C95

ZS"DSP

ADDRESS SPACE
Program Memory. The Z86C95 can address up to 64
Kbytes of external program memory (Figure 9). Program
execution begins at external location OOOCH after a reset.

the type instruction being executed. An LDC opcode
references program (lDM inactive) memory, and an LDE
instruction references DATA (lDM active Low) memory.
Data Memory will tri-state in reset.

Data Memory (lDM). The Z86C95 can address up to 64
Register Memory Map. The Z86C95 register memory

Kbytes of external data memory (Figure 9). External data
memory may be included with, or separated from, the
external program memory space. IDM, an optional I/O
function, that can be programmed to appear on P34 (Port
3, bit 4), is used to distinguish between data and program
memory space. The state of the IDM signal is controlled by

space is split into five register files; the original Z8 Register
File, Expanded Register File A (ERF-A), Expanded Register File B (ERF-B), Expanded Register File C (ERF-C) and
Expanded Register File D (ERF-D) (Figure 10).

FFFF

Program
Memory

Location of
First Byte of
Instruction
Executed
After RESET

Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)

---C
B
A
9
8

~--------

IRQ1

-

IRQO

-

-

IRQ5

-

IRQ4

~
5

~

3
2
1
0

Data
Memory

-

IRQ3
IRQ2

Figure 9. Program and Data Memory Configuration

1-14

Z86C95

PRELIMINARY

ZSG'DSP

Z8 Standard Control Registers
Register"

FF
FO

~

FF

SPL

FE

SPH

FD

RP

FC

FLAGS

FB

IMR

FA

IRQ

F9

IPR

F8

P01M

F7
F6

P3M

Reset Condition

u u u u u u u u
u u u u u u u u
0 0 0 0 0 0
U U U U U U
0 U U U U U
0 0 0 0 0 0

PREO

F4

TO

F3

PRE1

F2

T1

F1

TMR

FO

SIO

U U U U U U U 0
U U U U U U U U
U U U U U U 0 0
U U U U U U U U
o 0 0 0 0 0 0 0

ERFC

U U U U U U U U

------------------------,

~I

Register File"

U U

0 0
U U U U U U U U
0 1 0 0 1 1 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1

P2M

F5

0 0
U U

Note.:
U = Unknown

•• A1IAddresses in Hexadecimal

B~h'

~ERFA
'2l

",VI

FF
Z8IDSP Interface
BankF

P

00

W
02

I

iJJ!P

OF

L

1

P2

2

ERFB

4

01 Reserved
00 Reserved

ERFD

A

Be

0

I

~-----------------Figure 10. Register File

1-15

Z86C95
Z8<1>DSP

PRELIMINARY
ADDRESS SPACE (Continued)
Register File. The Register File consists of four I/O port
registers, 236 General-Purpose Registers and 16 control
and status registers. The instructions can access registers
directly or indirectly through an S-bit address field. The
ZS6C95 also allows short 4-bit register addressing using
the Register Pointer (Figures 11, 12). In the 4-bit mode, the
Register File is divided into 16 working register groups,
each occupying 16 contiguous locations. The Register
Pointer addresses the starting location of the active working-register group.
Expanded Register File. The register memory has been
further expanded into four additional register files known
as Expanded Register Files A thorough D. Each of these
register files contain 15 banks of 16 registers per bank.
ERF-A stores data for the DSP processor in nine banks of
its register space as well as system control registers and
peripheral device registers in the remaining six banks.
ERF-B contains the remaining four banks of DSP data
memory (total DSP data memory is 20S bytes [accessible
by the ZS]) as well as ten banks of DSP program memory.
ERF-C contains fourteen banks of DSP program memory,
and ERF-D contains eight banks of DSP program memory
making a total of 512 bytes. Bank F is common to all four
Expanded Register Files. Register (SH) in bank F is the ZSI
DSP control register. This register allows a quick means of
switching between register files while in the DSP. To do
this, bits 5 and 6 of the ZS/DSP control register are used as
follows: 06/5 - 00 for ERF-A, 06/5 - 01 for ERF-B, 06/5 - 10
for ERF-C,D6/5 - 11 for ERF-D. On power-up, bits 5 and 6
are reset to 0 thereby enabling access to ERF-A. Bits 7-4
of the register pointer, RP, selectthe working register bank
of the register file while bits 3-0 of the register pointer, RP,
selects the working register bank of the Expanded Register File. Once an expanded register bank is selected it is
effectively overlayed onto Bank 0 of the ZS's working
register file. When an expanded register bank is selected,
access to the ZS's ports is turned off.

R253 RP

Expanded Register Bank
Z8 Working Register Group

Figure 11. Register Pointer Register

I

I

r7

r6

r5

r4

I

r3 r2

r1

rO

1-16

R253
(Register Pointer)

The upper nibble of the register file address
provided by the register pointer specifies

the active working-register group.

--

FF

}
FO

--

--

R15toRO

i

··
··

·
Specified Working
Register Group

..... 1-

2F

The lower nibble
of the register
file address
provided by the
instruction points
to the specified

register.
20

IF

Register Group 1

Stack. The ZS6C95 has a 16-bit Stack Pointer (FEH-FFH)
used for external stack that resides anywhere in the data
memory. An S-bit Stack Pointer (FFH) is used for the
internal stack that resides within the 236 general-purpose
registers (04H-EFH). The High byte of the Stack Pointer
(SPI-Bits 15-S) can be used as a general-purpose register
when using internal stack only.

I

10
OF

Register Group 0

----------------110

~

Ports

00

Figure 12. Register Pointer

R15toRO
R15to R4
R3to RO

Z86C95

PRELIMINARY
Z8~IDSP

Z8~DSP

MEMORY INTERFACE

There are three types of memory spaces residing in the Z81
DSP interface:
1. DSP Program Memory. The size of this memory is 512
bytes. This memory space is mapped into ERF-B, C,
and 0 of the Z8. It occupies bank 1 through bank A in
ERF-B, bank 1 through bank E in ERF-C, and bank 1
through bank 8 in ERF-D. (Figures 13 and 14).

out of 256 are shared between the Z8 and the DSP. Out
of this 208 bytes, 144 bytes are mapped to Bank 1
through Bank 9 of ERF-A. The remaining bytes
are mapped into Bank B through Bank E of ERF-B.
3. Z8JDSP Interface Registers. The register mapping of
the various registers which are part of the Z8/DSP
interface are shown in Figure 15.

2. DSP Data Memory. There are two data memory banks
each 64 x 16 in size called DSP RAMO and DSP RAM 1.
This translates to 256 bytes. However, only 208 bytes

BankF

Z8IDSP INTF REG

BankF

Z8IDSP INTF REG

BankE

MUUDIV, TIMER

BankE

DSPDATAMEM

BankD

TIMER REG

BankD

DSP DATAMEM

Banke

AID, D/A, SPI, PWM

Banke

DSPDATAMEM

BankB

Not Used

BankB

DSPDATAMEM

Bank A

Not Used

Bank A

DSPPGMMEM

Bank 9

DSPDATAMEM

Bank 9

DSPPGMMEM

Bank 8

DSPDATAMEM

Bank 8

DSPPGMMEM

Bank 7

DSPDATAMEM

Bank 7

DSPPGMMEM

BankS

DSPDATAMEM

BankS

DSPPGMMEM

BankS

DSPDATAMEM

BankS

DSPPGMMEM

Bank 4

DSPDATAMEM

Bank 4

DSPPGMMEM

Bank 3

DSPDATAMEM

Bank 3

DSPPGMMEM

Bank 2

DSP DATA MEM

Bank 1

DSPDATAMEM

64 Bytes

160. Bytes
144 Bytes

Expanded Register
File A (ERFA)

Bank 2
Bank 1

DSP PGMMEM
DSPPGMMEM

Expanded Register
File B (ERF B)

Figure 13. DSP Program and Data Memory

1-17

Z86C95

PRELIMINARY

Z8~DSP

Z8/DSP MEMORY INTERFACE (Continued)

Bank F

Z8/DSP INTF REG

Bank F

Z8/DSP INTF REG

Bank E

DSP PGM MEM

Bank E

Not Used

BankD

DSP PGM MEM

BankD

Not Used

BankC

DSP PGM MEM

BankC

Not Used

Bank B

DSP PGM MEM

Bank B

Not Used

Bank A

DSPPGM MEM

Bank A

Not Used

Bank 9

DSPPGM MEM

Bank 9

Not Used

Bank 8

DSP PGM MEM

Bank 8

DSP PGM MEM

Bank?

DSP PGM MEM

Bank?

DSP PGM MEM

BankS

DSPPGM MEM

BankS

DSP PGM MEM

BankS

DSPPGM MEM

BankS

DSP PGM MEM

Bank 4

DSPPGM MEM

Bank 4

DSP PGM MEM

Bank 3

DSPPGM MEM

Bank 3

DSP PGM MEM

Bank 2

DSPPGM MEM

Bank 2

DSP PGM MEM

Bank 1

DSP PGM MEM

Bank 1

DSP PGM MEM

1-

224 Bytes

r- 128 Bytes

Expanded Register
File C (ERF C)

Expanded Register
File D (ERF D)

Figure 14. DSP Program and Data Memory

1-18

1-

Z86C95
Z8"'DSP

PRELIMINARY
ERF (A) ERF (B) Bank F

3 and so on are all split between RAMO for the first 8 bytes
and RAM1 for the last 8 bytes. Also, notice that the higher
order bits (15 through 8 of the DSP word) are mapped to
an even number byte of the Z8 and the lower order bits of
the DSP (7 through 0) are mapped to the odd numbered
bytes of the Z8. The size of DSP RAM 1 and RAMO is 64 16bit words each. These occupy hex addresses
00 through 3F. The following is the bank mapping of Z8
ERF-A and ERF-B to the DSP RAM1 and RAMO.

9H

Register Pointer 0 (RO)

lH

Register Pointer 1 (Rl)

2H

Register Pointer 2 (R2)

3H

Register Pointer 3 (R3)

4H

DSP Status Register High Byte

DSP RAM1/RAMO

5H

DSP Status Register Low Byte

00- 03

6H

Psuedo Program Counter (LSB)

7H

Psuedo Instruction Register

04 - 07
08 - OB
OC -OF
10 - 13

8H

Z8/DSP Control Register

14 - 17

AH

Psuedo Program Counter (MSB)

18 - 1B
1C - 1F

CH

Shadow Latch (LSB)

20- 23

DH

Shadow Latch (MSB)

24 - 27
28 - 2B
2C - 2F

30 - 33
34- 3F

Z8 Bank
Bank 1 of
Bank 2 of
Bank 3 of
Bank 4 of
Bank 5 of

ERF-A
ERF-A
ERF-A
ERF-A
ERF-A

Bank 6
Bank 7
Bank 8
Bank 9

ERF-A
ERF-A
ERF-A
ERF-A

of
of
of
of

Bank B of ERF-B
Bank C of ERF-B
Bank 0 of ERF-B
Bank E of ERF-B
Not mapped to Z8

Figure 15. Z8IDSP Interface Register Mapping

The details of the data memory mapping between the Z8
and the DSP are shown in Figures 16 and 17. For example,
Bank 1 of ERF-A is split between DSP RAM1 and RAMO.
Bytes 15 through 8 are mapped to DSP RAM1 and bytes
7 through 0 are mapped to DSP RAMO. Similarly. Banks 2,

1-19

Z86C95

PRELIMINARY

~DSP

Z8/DSP MEMORY INTERFACE (Continued)
Access to a working bank in ERF-A is achieved by selecting the appropriate lower four bits, 3-0 of the Register
Pointer, RP located within the Z8's Standard Register
Bank. Bits 5and 6 of the Z8/DSP control register are used
to access the remaining register files as follows: D6/5 - 00
for ERF-A, D6/5 - 01 for ERF-B,D6/5 - 10 for ERF-C,D6/511 for ERF-D. Notice that bank F in ERF-B or C or D is the
same as that of ERF-A. This provides common access to
the Z8/DSP control register which allows movement from

ERF (A) Bank 1
Not Mapped to Z8

Not Mapped to Z8
34
33

34
33

ERF (B)
ERF (B)
ERF (B)
ERF (B)

ERF (B) Bank E
ERF (B) Bank D
ERF (B) Bank C
ERF (B) Bank B

ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)

Bank 9
Bank 8
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1

24
23

ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)
ERF (A)

Bank E
Bank D
Bank C
Bank B

Bank 9
Bank 8
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1

00

00
DSP
Address

DSP Data RAM 0
(64x16)

DSP
Address

DSP Data RAM 1
(64x16)

Figure 16. Data Memory Mapping of ZS and DSP

1-20

The interface registers (except the Z8/DSP control register) program memory and data memory of the DSP can not
be accessed while the DSP is executing from the internal
program memory.

3F

3F

24
23

any register file to any other file. In other words, all the
registers in bank F can be accessed from any of the four
ERFs.

ERF (A) Bank 1

03

14

15

03

6

7

02

12

13

02

4

5

01

10

11

01

2

3

00

8

9

00

0

1

DSP
Address

DSP Data RAM 1

DSP
Address

DSP Data RAM 0

Figure 17. Close-Up of ERF (A)
Bank 1 Byte Addressing

Z86C95

PRELIMINARY

Z8~DSP

Z8IDSP Interface. The block diagram of the Z8/DSP
interface logic and shared RAM between the Z8 and DSP
is shown in Figures 18 and 19.

PGM MEM 512 Bytes

"'-

...-

I I
DATA/8

1Io

~}

Pseudo IR

!8~ LMapping Logic

II

I

~
~

n

EXT (15-0) (

'V

--y

Pseudo PC

I--

I

--"

.>

ERF Bus+ CTL

~

CTL

7

.

-"

SSt

CT L ----

_JO.

ADDR!9

PD(15-0)

J1
A

J

Reset
DSP
(see DSP core)

CK12

State
Machine

Reg + RAM RIW
Zero, OV, Link

Figure 18. Block Diagram of Z8IDSP Interface

1-21

Z86C95
ZS"'DSP

PRELIMINARY

Z8/DSP MEMORY INTERFACE (Continued)

Control

f4-

64 Words
RAM

64 Words
RAM

-

Reg Pt 0,1

-

1-Level
Stack

16-Bit Bus

~

®

@
16 x16
Multiplier

®
~

-CP
-~

24-Bit Bus

I

SR

cb

(B)

\

ALU

I

I

~
ACC

r

Status

J--

I
Figure 19. DSP Core

1-22

PCSAR
IMM

Reg pt 2,3

I

Program
Memory
Interface

J

PRELIMINARY

Access to DSP Processor
There are three ways to instruct the OSP to execute
instructions.

ERF (A) (B) Bank F, Register 6

1. Through the internal program memory (512 Bytes):
Pause Mode

The program memory can be loaded by the Z8 (series
of load immediate instructions). After loading the program memory, the Pseudo-PC can be loaded with the
start address for program execution. Loading of the
pseudo-PC will start the OSP. The OSP keeps executing until STOP OSP instruction which puts the OSP in
the low power mode. As shown in the OSP instruction
set, branching is allowed within the program memory
space (512 bytes). The instruction execution time in
this mode is one state time in the pipeline mode except
for Branch and Load Immediate to the register pointers. This takes three and two state times, respectively,
in the pipeline mode.

2. Another way to start the OSP execution from the
internal program memory is to load the Shadow latch
register with the start address and set bit 3 of the Z81
OSP control register to 1. When the NO converter
finishes conversion, it generates an interrupt to the
OSP which then loads the pseudo-PC from the shadow
latch and start the execution from that location. Notice
that this enables a very fast LOOP execution by
avoiding a Z8 interrupt wait time delay.
3. Through loading the Psuedo-IR with the appropriate
instruction:
The OSP instruction (8 bits) is loaded as a Load
Immediate data value into the Pseudo-IR. The OSP
then wakes up from the power-down mode, executes
the instruction and goes back to the power down
mode. Since a Load Immediate operation takes six
clocks, the instruction execution time in this mode is
six clocks. Notice, that branching in this mode can be
done by examining the Status register of the OSP
which is mapped to the Z8 space (Figure 20).

OSPStatus
O=ldle, 1=Busy
Reset OSP
Automatic OSP Execution
Enables Z66C95 to execute
from Intemal Program Memory
Access to ERF A, B. C, 0
OO=A 01=B
100C 11=0
' - - - - - - - - - - - - Not Implemented

Figure 20. Z8IDSP Control Register

Bits 7 not implemented.
Bits 5, 6 Access to ERF NB/C/O.
Bit 4 enables the Z8 to execute from internal memory (256
bytes) when set to 1, this bit is automatically reset to 0 on
power-up.
Bit 3 enables automatic OSP execution when the NO
completes conversion (when set to 1).
Bit 2 allows reset of the OSP.
Bit 1 indicates the status of the OSP. When bit 1 is set to 1
it indicates the OSP is busy executing from internal program memory. Bit 1 is reset to 0 on power-up.
Bit 0 enables PAUSE mode when set to 1. Bit 0 is reset to

oon power-up (see power-down mode).

1-23

PRELIMINARY

Z86C95
Z8$DSP

FUNCTIONAL DESCRIPTION
Z8 Multiply/Divide Unit
This section describes the basic features, implementation
details and the interface between the ZS and the multiply/
divide unit (Figure 21).
Basic features:
•

16 x 16-Bit Multiply with 32-Bit Product

•

32 x 16-Bit Divide with 16-Bit Quotient
and 16-Bit Remainder

•

Unsigned Integer Data Format

•

Simple Interface to ZS

Interface to za. The following is a brief description of the
register mapping in the multiply/divide unit and its interface to ZS.
The multiply/divide unit is interfaced like a peripheral. The
only addressing mode available with the peripheral interface is register addressing. In other words. all the operands are in the respective registers before a multiplication/
division can start.

CTL

Z8

CTL

CTL

CTL

Control

Figure 21.

1-24

za MultiplylDivide Unit Block Diagram

PRELIMINARY
Register Mapping. The registers used in the multiply/
divide unit are mapped onto the expanded register file A
in Bank E. The exact register locations used are as shown
below.
Register

Address

REGO
REG1
REG2
REG3

(E) OOH
(E) 01H
(E) 02H
(E)03H

REG4
REG5
REG6
REG7
REG8

(E)
(E)
(E)
(E)
(E)

04H
05H
06H
14H
15H

Register Allocation. The following is the register allocation during multiplication.
Allocation

Register

Multiplier high byte
Multiplier low byte
Multiplicand high byte
Multiplicand low byte

REG2
REG3
REG4
REG5

Result high byte of high word
Result low byte of high word
Result high byte of low word
Result low byte of low word
Control register

REGO
REG1
REG2
REG3
REG6

Z86C95
Z8"DSP

The following is the register allocation during division.
Allocation

Register

High byte of high word of dividend
Low byte of high word of dividend
High byte of low word of dividend
Low byte of low word of dividend
High byte of divisor

REGO
REG1
REG2
REG3
REG4

Low byte of divisor
High byte of remainder
Low byte of remainder
High byte of quotient
Low byte of quotient
Control register

REG5
REGO
REG1
REG2
REG3
REG6

Control Register. The MOCON control register is used to
interface with the multiply/divide unit (Figures 22 and 23).
Specific functions of various bits in the control register are
shown.
DONE Bit (07). This bit is a handshake bit between the
math unit and the external world. On power up, this bit is
set to 1 to indicate that the math unit has completed
the previous operation and is ready to perform the next
operation.

Before starting a new multiply/divide operation this bit
should be reset to 0 by the processor/programmer. This
will indicate that all the data registers have been loaded
and the math unit can now begin a multiply/divide operation. During the process of multiplication or division, this bit
is write-protected. Once the math unit completes its operation itwill set this bit to indicate the completion of operation.
The processor/programmer can then read the result.

1-25

PRELIMINARY

Z86C95

~DSP

FUNCTIONAL DESCRIPTION (Continued)
ERF(A) Bank E, Register 6

1~lool~I~lool~I~lool

--~

TL

DlvidebyO
(0 = No Error
1 = Error)

Division Overflow
(0 = No Overflow
1 = Overflow)
L..-_ _ _ _ Reserved
.....- - - - - - - Divide SL (D5)jMultiply SL (00)
00= NOP
01 =DIV
10=MUL
11 =NCP
' - - - - - - - - - - - Done

Figure 22. MultiplylDivide Control Register
(MOCON)
General-Purpose Register
General-Purpose Register
Compare Register 1 Low Byte
Compare Register 1 High Byte
Not Used
Not used
Not Used
Not Used
Not Used
MUUDIV Control Register
MUUDIV Register 5
MUUDIV Register 4
MUUDIV Register 3

MULSL Multiply Select (06). If this bit is set to 1, it will
indicate a multiply operation directive. Like the DONE bit,
this bit is also write-protected during math unit operation
and is reset to zero by the math unit upon starting of
multiply/divide operation.
OIVSL Division Select (05). Similar to 06, 05 will start a
division operation.

04-02 Reserved .
OIVOVF Division Overflow (01). This bit indicated an
overflow during the division process. Division overflow
occurs when the high word of the dividend is greater than
or equal to the divisor. This bit is read only. When set to 1,
it indicates overflow error.
OIVZR Division by Zero (DO). When set to 1 this indicates
an error of division by O. This bit is read only.
Example:
Upon reset, the statusofthe MDGON register is 100uuuOOb
(07 to DO).
u = Undefined
x = Irrelevant
b = Binary
If multiplication operation is desired, the MDGON register
should be set to 010xxxxxb.
If the MDGON register is READ during multiplication, it
would have a value of OOOuuuOOb.
On completion of multiplication, the result of the MDGON
register will be 100uuuOOb.
If division operation is desired, the MOGON register should
be set to 001xxxxxb.
During division operation, the register would contain
OOOuu??b (? - value depends on the DIVIDEND, DIVISOR).
Upon completion of division operation, the MDGON register would contain 1OOuuu??b.

MUUDIV Register 2
MUUDIV Register 1
MUUDIV Register 0

Figure 23. ERF (A) Bank E

1-26

Note that once the multiplication/division operation starts,
all data registers (REG5 thorough REGO) are writeprotected and so are the writable bits of the MDGON
register. The write protection is released once the math
unit operation is complete. However, the registers can be
read any time.

PRELIMINARY
A multiplication sequence would look like:

1. Load multiplier and multiplicand.
2. Load MDCON register to start multiply operation.
3.

Wait for the DONE bit of the MDCON register to be
set to 1 and then read results.

Note that while the multiply/divide operation is in progress,
the programmer can use the ZS to do other things. Also,
since the multiplication/division takes fixed numbers of
cycles, the results can be read before the DONE bit is set.
During a division operation, the error flag bits are set at the
beginning of the division operation which means the flag
bits can be checked by the ZS while the division operation
is being done.
REG7 and REGS can be used as scratch pad registers or
as external data memory address pointers during an LDE
instruction. REGO thorough REG5 and REG7 and REGS, if
not used for multiplication or division, can be used as
general-purpose registers.
Performance of Multiplication. The actual multiplication
takes 17 clock cycles. It is expected that the chip would run
at a 10 MHz internal clock frequency (external clock

Z86C95

Z8~DSP

divided-by-two). This would result in an actual multiplication time (16 x 16-bit)of 1.7 1lS.lfwe include the time taken
to load and read the registers:
number of clock cycles to load 5 registers = 30
number of clock cycles to read 4 registers = 24
then, the total number of clock cycles is 71. This results in
a net multiplication time of 7.1 1lS. Note that this would be
the worst case. This assumes that all of the operands are
loaded from the external world as opposed to some of the
operands being already in place as a result of a previous
operation whose destination register is one of the math
unit registers.
Performance of Division. The actual division needs 20
clock cycles. This translates to 2.0 IJ.S for the actual
division at 10 MHz (internal clock speed). If the time to load
operands and read results is included:
number of clock cycles to load operands = 42
number of clock cycles to read results = 24
The total clock cycles to perform a division is S6 cycles.
This translates to S.6 IlS at 10 MHz.

1-27

Z86C95
Z8$DSP

PRELIMINARY

FUNCTIONAL DESCRIPTION (Continued)
CounterlTimers
This section describes the enhanced features olthe counter/
timers (CTC) on the Z86C95 (Figure 24). It contains the
register mapping of CTC registers and the bit functions of
the newly added Timer2 control register.
In a standard Z8, there are two 8-bit programmable counter/
timers (TO and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the TO prescaler
is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt
request, IR04 (TO) or IR05 (T1), is generated.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. Also, the counters
can be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, can be read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and can be either the
internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register
configures the external timer input (P31) as an external
clock, a trigger input that can be retriggerable or nonretriggerable, or as a gate input for the internal clock. The
counter/timers can be cascaded by connecting the TO
output to the input of T1. Either TO or T1 can be outputted
through P36.

The following are the enhancements made to the counter/
timer block on the Z86C95:
TO counter length is extended to 16 bits. For example, TO
now has a 6-bit prescaler and 16-bit down counter.
T1 counter length is extended to 16 bits. For example, T1
now has a 6-bit prescaler and 16-bit down counter.
A new counter/timer T2 is added. T2 has a 4-bit prescaler
and a 16-bit down counter with three capture registers and
two compare registers.
These three counters are cascadable as shown in Table 5.
The result is that T2 may be extendable to 32 bits and T1
extendable to 24 bits. Bits 1 and 0 (CAS1 AND CASO) of the
T2 Prescaler Register (PRE2) determine the counter length.
Table 5. Z86C95 Counter Length Configurations

TO

CAS1

CASO

o
o

o
1

1

8
8

o

1
1

T1

T2

8

8

16

16
24
16

32
16
16
24

The controlling clock input to T2 can be programmed to
XTAU2 or XT AU8 which results in a resolution of 100 ns at
external XTAL clock speed of 20 MHz.

IR04

XTAUB
P36

TOUT

XTAU8
or
External
IROS

XTAU8
or
XTAU2
T21RO

P32 - - - I

Figure 24. CounterfTimer Block Diagram

1-28

IROO

Z86C95

PRELIMINARY

Z8~DSP

Capture and Compare
There are three capture registers associated with T2 HIGH
BYTE and T2 LOW BYTE registers and two compare
registers on timer T2 (Figure 25). At the falling edge of the
appropriate Port 3 input, the current value of Timer 2 (T2)
is "captured" into a read only register. For example, the
negative going transition on P33 will enable the latching of
the current T2 value (16-bits) into the Capture Register 1

(CAP1). The register mapping and the appropriate inputs
are shown below (Table 6). Note that the negative transition on P33, P32, and P30 is capable of generating an
interrupt. Also, the negative transition on Port 3 will always
latch the current T2 value into the capture register. There
in no need for a control bit to enable/disable the latching.

ERF (A), Bank D
(D)OFH

Compare Register 2 Low Byte

(D)OEH

Compare Register 2 High Byte

(D)ODH

Capture Register 3 Low Byte

(D)OCH

Capture Register 3 High Byte

(D)OBH

Capture Register 2 Low Byte

(D)OAH

Capture Register 2 High Byte

(D)09H

Capture Register 1 Low Byte

(D)08H

Capture Register 1 High Byte

(D)07H

limer2 Low Byte

(D)06H

limer2 High Byte

(D)05H

Capture/Compare Control Register

(D)04H

limera High Byte

(D)03H

limer2 Prescaler

(D)02H

limer1 High Byte

(D)01H

limer2 Mode Register

Figure 25. Capture and Compare Registers

Table 6. Capture Register Mapping
Capture Register

CAP 1
CAP2
CAP3

Port 3

Input

Addr. High

Addr. Low

P33
P32
P30

Falling
Falling
Falling

(0) 8
(0) A
(O)C

(0) 9
(0) B
(0) 0

1-29

Z86C95
Z8"'DSP

PRELIMINARY

FUNCTIONAL DESCRIPTION (Continued)
Compare Registers. Whenever the current value of T2
equals the contents of the compare register, some action
is taken depending on the contents of the T2 Compare

C01 Output (D 1,DO). Controls the value outputted on CO 1
according to the following table:
Table 7. Compare Output Status

Control Register (COMCON). Also, a successful comparison can generate an interrupt (if enabled) and also set
a bit in the control register that can be polled at a later date
.
(Figure 26).
COM2 Compare 2 (D7). This bit is set to 1 when the
contents of Compare Register 2 (COM2) match the current
value of T2. This bit will have to be cleared by the interrupt
polling routine.

Bit 5 Bit 4
Bit 1 Bit 0

o
o
1
1

0
1

0
1

Output on Compare Output
NOP (C01/C02 retain previous value)
Reset to "0"
Set to "1"
Toggle status

Table 8. Compare Register Mapping
Interrupt Enable 2 (D6). This bit, when set to 1, will enable
the interrupt for COM2.
C02 Output (D5,D4). Controls the value outputted on C02
according to Table 7.
COM1 Compare 1 (D3). This bit is set to 1 when the
contents of Compare Register 1 (COM 1) match the current
value of T2. This bit will have to be cleared by the interrupt
polling routine (Table 8).
Interrupt Enable 1 (D2). This bit when set to 1 enables the
interrupt for COM1. When either D6 or D2 is set and the
corresponding compare register contents match the current value of T2, an interrupt is generated on IRQ5, which
is configured as an OR of T1IRQ, COM1, or COM2
interrupts.

ERF (A) Bank D, Register 5

17161514131211101

I

11.....-_

Configure Compare R~gister 1

Compare Register
COM1
COM2

Addr. High
(E) C
(D) E

Addr. Low
(E) D
(D) F

Observations:
Except for the programmable down counter length and
clock input, T2 is identical to TO.
TO and T1 retain all their features except that now they are
extendable interims of the down counter length.
The output of T2, under program control, can go to an
output pin (P35). Also, the interrupt generated by T2 can
be ORed with the interrupt request generated by P32. Note
that the service routine then has to poll the T2 flag bit and
also clear it (bit 7 of T2 Timer Mode Register).
On power up, TO and T1 are configured in the 8-bit down
counter length mode (to be compatible with Z86C91) and
T2 is in the 32-bit mode with its output disabled (no
interrupt is generated and T2 output DOES NOT go to port
P35).

Configure Compare Register 2

Figure 26. T2 Compare Control Register (COM CON)

1-30

The UART uses TO for generating the bit clock. This means,
while using UART TO should be in 8-bit mode. So, while
using the UART there are only two independent timer/
counters.

Z86C95

PRELIMINARY
The counters are configured in the following manner:
TO in a-bit mode
TO in 16-bit mode

TO Low byte
TO High byte, TO Low byte

T1 in a-bit mode
T1 in 16-bit mode

T1 Low byte
T1 High byte, T1 Low byte

T1 in 24-bit mode

TO High byte, T1 High byte
T1 Low byte

T2 in 16-bit mode
T2 in 24-bit mode

T2 High byte, T2 Low byte
TO High byte, T2 High byte
T2 Low byte

T2 in 32-bit mode

TO High byte, T1 High byte,
T2 High byte, T2 Low byte

Note that the T2 interrupt is logically ORed with P32 to
generate IROO.
The T2 Timer Mode register is shown in Figure 27. Upon
reaching end of count, bit 7 of this register is set to 1. This
bit IS NOT reset in hardware and it has to be cleared by the
interrupt service routine.

Z8~DSP

The register map of the new eTe registers is shown in
Figure 12. TO High byte, T1 High byte are at the same
relative locations as their respective Low bytes, but in a
different register bank.
The T2 prescaler register is shown in Figure 2a. Bit 1 and
Bit 0 of this register controls the various cascade modes of
the counters as shown in Table 1.

ERF (A) Bank D, Register 3

1~1~1~1~lool~I~lool

II

=~~h
00
01
10
11

TO
8
16
8
8

T1
8
16
24
16

T2
32
16
16
24

Reserved
Prescaler Modulo
(Renge: 1 - 16 Decimal
01 -00 Hex)

Figure 28. 12 Prescaler Register (PRE2)

ERF (A) Bank D, Register 1

o

No Function
1 LoedT2

o

Disable T2 Count
1 Enable T2 Count

Count Mode
T2 Single Pass
1 T2ModuioN

o

Interrupt Enabled
Disable
1 Enable

o

T2out (P36)

o

Disable
1 Enable

Reserved (Must be 0)
T2 CLOCK Source

o

XTAL18
1 XTAlJ2

T2 End Of Count
NotEOC
1 EOC

o

Figure 27. 12 Timer Mode Register (12)

1-31

PRELIMINARY

Z86C95
ZS"'DSP

Analog to Digital Converter (ADC)
and the other three will be in sequence following with
wraparound from Channel 7 to Channel O.

The ADC is an 8-bit half flash converter which uses two
reference resistor ladders for its upper 4 bits (MSBs) and
lower 4 bits (LSBs) conversion. Two reference voltage
pins, VAH1(High) and VALO (Low), are provided for external
reference voltage supplies. During the sampling period
from one of the eight channel inputs, the converter is also
being auto-zeroed before starting the conversion. The
conversion time is dependent on the external clock
frequency and the selection of the prescaler value for the
internal ADC clock source. The minimum conversion time
is 2.0 ~. (See Figure 29, ADC Architecture.)

The start commands are implemented in such a way as to
begin a conversion at any time, if a conversion is in
progress and a new start command is received, then the
conversion in progress will be aborted and a new conversion will be initiated. This allows the programmed values to
be changed without affecting a conversion-in-progress.
The new values will take effect only after a new start
command is received.

The ADC is controlled by the Z8 and its six registers (two
Control and four Result) are mapped into the Extended
Register File. The first Result register is also readable by
the DSP. The DSP can access the ADC control register 0,
and this allows the DSPto change Input Channel selections.

The clock prescaler can be programmed to derive a
minimum 2 ~ conversion time for XTAL clock inputs from
4 MHz to 20 MHz. For example, with a 20 MHzXTALclock
the prescaler should be programmed for divide by 40
which then gives a 2 ~ conversion rate.

A conversion can be initiated in one of four ways: by writing
to the Command register, from a rising or falling edge on
Port 32 pin orTimerO equal O. These four are programmably
selectable. There are four modes of operation that can be
selected: one channel converted four times with the results
written to each Result register, one channel continuously
converted and one Result channel updated for each
conversion, four channels converted once each and the
four results written to the Result registers, and four channels repeatedly converted and the Result registers kept
updated. The channel to be converted is programmable
and if one of the four-channel modes is selected then the
programmed channel will be the first channel converted

The ADC can generate an Interrupt after either the first or
fourth conversion is complete depending on the programmable selection.

1-32

The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain constant over the specified electrical range. The errors of the
converter will increase and the conversion time may also
take slightly longer due to smaller input signals.

Z86C95
ZSil>DSP

PRELIMINARY
EXT

TMRO

~~
Start
Converter

l

...

¢:

AID
Prescaler

AID
Controller
Register

I

~
['r-

I

Integrated
Logic

...
VREF

4xB
Result
Register

I
B
Channel
Multiplexer

~

r---v

Sample
and
Hold

I

>

,

~

Internal
Bus

Flash
AID
Converter

1

1
-

AGND

r

Dual

Scan

AID
Channel
Register

A.

...

Channel Select

Figure 29. ADC Architecture

1·33

Z86C95
Z8$DSP

PRELIMINARY

FUNCTIONAL DESCRIPTION (Continued)
Modes (bits 4, 3).

ERF(A) Bank C, Register 8

~CSELO

~

CSELI
CSEL2
SCAN

QUAD

~---------------- 01
DO
02

Figure 30. ADC Control Register 0

Prescaler Values (bits 7, 6, 5).
D1

DO

Prescaler
(XTAL divided by)

0
0
0
0

0
0
0
1

0
0
1
0

8
12816
24

0
1
1
1
1

1
0
0
1
1

1
0
1
0
1

32
40
48
56
64

D2

Note:
The ADC is being characterized as of this date. The errors of the
converter are estimated to increase to 2LSBs (Integral non-linearity), 1
LSB (Differential non-linearity) and 10mV (Zero error at 25°C) if the
voltage swing on the reference ladder is decreased to -3V .

• 33 MHz Device only.

1-34

QUAD

SCAN

0

0

0
1
1

1
0
1

Convert selected channel 4 times
then stop
Convert selected channel then stop
Convert 4 channels then stop
Convert 4 channels continuously

Channel Select (6its 2, 1, 0).
CSEL2

CSEL1

CSELO

Channel

0
0
0
0

0
0
1
1

0
1
0
1

0
1
2
3

0
0
1
1

0
1
0
1

4
5
6
7

~2j(.m

Z86C95

PRELIMINARY

Z8~DSP

ADIE (bit 2). This is the ADC Interrupt Enable. A 0 disables
setting the ADC Interrupt. A 1 enables setting the ADC
Interrupt.

ERF (A) Bank C, Register 9

ADSTO
ADsn
ADIE
ADIT
ADCINT
Reserved
ADE

START (bits 1, 0).
ADST1

ADSTO

o

o

Mode
Conversion starts when this
register is written.
Conversion starts on a rising
edge at Port 3-2.
Conversion starts on a falling
edge at Port 3-2.
Conversion starts when TimerO
times out.

o
o

Figure 31. ADC Control Register 1

ADE (bit 7). AO disables any NO conversions or accessing
any ADC registers except writing to ADE bit. A 1 Enables all
ADC accesses.
Reserved (bits 6, 5). Reserved for future use.
ADCINT (bit 4). This is the ADC Interrupt bit and is read
only by the Z8, the ADCINT will be reset any time this
register is written.
ADIT (bit 3). This bit selects when to set the ADC Interrupt
if ADIE=1. A 0 sets the Interrupt after the first AID conversion is complete. A 1 sets the Interrupt after the fourth NO
conversion is complete.

These are the four ADC result registers, Reg-A holds the
first result and Reg-D the fourth result. These registers are
RNV by the Z8 (Writable for test purposes) and Reg-A is
Read Onlybythe DSP and is mapped to Reg 1 for the DSP.
Figure 32 shows the timing diagram for the ADC.

ERF (A) Bank C, Registers A,B,C,D

Iwlool~I~loolool~lool

I

Data

Figure 32. Result Registers

1-35

."

~I

c:

.~

0

~

z

-I

2

1
SCLI<

3

4

6

5

7

8

9

10

11

27

26

28

29

30

32

Z

l>
r
I

I

I

,

I
I

I

,

I

I

m

en

I

,

I

,

I

I

,

I

I

I

I

I

I

I

I

,
,

I
I

I

AID Resutt

,
,

I

I

I

I

,

,iI
I.

0
:0
=ij

:::!
0

Z

00

:::J

~

""t>

c:::

CD

::0

.9:

!....!....J, I
, ,

."
r-

I

I

I

s:

,

DSPINT

DSPWrileto 2
ADCCTLREG0

,

I

I

I

I

, ,

, ,
CHANMUX

I

a

C

I

P32

Input Sample

31

(5

,
,

I

I

I

~
I

I

):,.
I
I

,

::0

-.:::

Notes:

1. SCLK = 12 MHz (XTAL = 24 MHz)
2. ADC ClL REG(/) = 85
ADC ClL REG1 = 85

Figure 33. ADC Timing Diagram

~N

8""

~~

-aU!

Z86C95

PRELIMINARY

Z8~DSP

Reg F
Reg E

PWM Data

Reg D
RegC

AD Result 4
AD Result 3

Reg B

AD Result 2

Reg A

AD Result 1

~

Reg 9
Reg 8

AD Control 1
AD Control 0

Reg 7

DAC Data

Reg 6

DAC Control

.

registers can be
- These
accessed from DSP

Reg 5
Reg 4
Reg 3
Reg 2

SPI Control

Reg 1 SPI TXRXDATA
Reg 0
SPI Compare

Figure 34. ERF(A) Bank C

Figure 35 shows· the input circuit of the ADC. When
conversion starts the analog input voltage from one of the
eight channel inputs is connected to the MSB and LSB
flash converter inputs as shown in the Input Impedance
CKT diagram. Effectively, shunting 31 parallel internal
resistance of the analog switches and simultaneously
charging 31 parallel 0.5 pF capacitors, which is equivalent
to seeing a 400 Ohms input impedance in parallel with a

16 pF capacitor. Other input stray capacitance adds
about 10 pF to the input load. For input source resistances
up to 2 kOhms can be used under normal operating
condition without any degradation of the input settling
time. For larger input source resistance, longer conversion cycle time may be required to compensate the input
settling time problem.

~

MOSSwitch

on Resistance

2 - 5 kn

VRef_~
C.5pF

C Parasitic

1
-

vRef_~
C.5pF

31 CMOS Digital
Comparators

~

VRef_~
C.5pF

Figure 35. Input Impedance of ADC

1-37

'~'.--~---

------

Z86C95

PRELIMINARY

Z8~DSP

Digital to Analog Converter (DAC)
The DAC (Digital to Analog Converter) is an 8-bit resistor
string, with a programmable O.25X and O.5X gain output
buffer. The DAC output voltage is settled after the internal
digital data is latched. Two pins are provided externally for

the DAC reference voltage supplies, VD H1 and VD LO , these
should not exceed the supply voltages. The DAC output is
latch-up protected and can drive output loads
(Figure 36).

VDHI
AVCC
8

CTRL
Reg

Analog

Enable

Data
Bus

8-Bit Resistor
Ladder DAC
8

TARGET
Reg

8

VDLO

GO

G1

Figure 36. DAC Block Diagram
The DAC is controlled by the Z8. Its two registers (Control
1 and Data 1) are mapped into the ERF (Figures 37 and 38).
The Data 1 register is writable by the DSP.
The DAC can be enabled or disabled by programming the
Control 1 register or it can be programmed to output an
analog voltage when the Data 1 register is loaded. The
Control 1 register is used to program for the Gain factor of
the DAC output.

The DAC Data Register is initialized to 80H on power-up
(Figure 38). Also the DAC gain control pivots about a midpoint rather than ground. (Figure 38). When the gain
control is at i.0X or O.5X or O.25X the DAC output remains
constant when the DAC data register equals 80H (Figure
39).
ERF (A) Bank C, Register 7

ERF (A) Bank C, Register 6

Figure 38. DAC Data Register

DACGain
001 X
o 1 1/2X
1 01 N/A
1 1 1/4 X
DAC Enable
o Disable
1 Enable
Reserved (Must be 0)
Settling Time
(Nonnally set to 1)
'--- ABiPC -Address Bus or DSP Program Counter
Address BusAO toA7 output 06=0 05=0.
To change to the DSP PC output to PinsA7-AO
write 05=1 06=0. Then write 05=1 06=1
PWM Clock Select
o XTAL 1 Divided-by-2
1 Buffered XTALt

Figure 37. DAC Control Register
1-38

Z86C95

PRELIMINARY

ZS"'DSP

DAC Output in Volts

3.SV
VDHI

-----------------------------

3.S

3.0S
2% accuracy

2.6

1.7

1.26
VDLO .8
---------~----------r

ir

o

80H

FFH

DAC Data Register Value

Figure 39. Gain Control on DAC

1-39

PRELIMINARY

Z86C95

Z8~DSP

FUNCTIONAL DESCRIPTION (Continued)
Serial Peripheral Interface
Serial Peripheral Interface (SPI). The Z86C95 incorporates a serial peripheral interface for communication with
other microcontrollers and peripherals. The SPI includes
features such as Master/Slave selection and Compare
mode. The SPI consists of four registers; SPI Control
Register (SCON), SPI Compare Register (SCOMP), SPI
Receive/Buffer Register (RxBUF), and SPI Shift Register
(Figures 40, 41, and 42). SCON is located in bank C of the
Expanded Register Group at Address 02. This register is
a read/write register that controls; Master/Slave selection,
interrupts, clock source and phase selection, and error
flag. Bit 0 enables/disables the SPI with the default being
SPI disabled. A 1 in this location enables the SPI, and a 0
disables the SPI.

Bits 1 and 2 of the SCON register in Master Mode selects
the clock rate. The user may choose whether internal clock
is divide by 2,4,8, or 16. In Slave Mode, Bit 1 of this register
flags the user if an overrun of the RxBUF Register has
occurred.
The RxCharOverrun flag can only be reset by writing a 0 to
this bit. In slave mode, bit 2 of the Control Register can
disable the data-out I/O function. If a 1 is written to this bit,
the data-out pin is tri-stated. If a 0 is written to this bit, the
SPI will shift out one bit for each bit received. Bit 3 of the
SCON Register enables the interrupt of the SPI, with the
default being disabled. Bit 4 signals that a receive character is available in the RxBUF Register. If the associated

1-40

IROO is enabled, an interrupt is generated. Bit 5 controls
the clock phase of the SPI. A 1 in Bit 5 allows for receiving
data on the clock's falling edge and transmitting data on
the clock's rising edge. A 0 allows receiving data on the
clock's rising edge and transmitting on the clock's falling
edge.
The SPI clock source is defined in bit 6 for Master mode.
A 1 uses TimerO output for the SPI clock, and a 0 uses TCLK
for clocking the SPI. In Slave mode, bit 6 will enable or
disable the address compare feature. Finally, bit 7 determines whether the SPI is used as a Master or a Slave. A 1
puts the SPI into Master mode and a 0 puts the SPI into
Slave mode.
SPI Operation. The SPI can be used in one of two modes;
either as system slave, or a system master. In the slave
mode, data transfer starts when the slave select
(SLAVESEL) pin goes active. Data is transferred into the
slave's SPI Shift Register, through the 01 pin, which has the
same address as the RxBUF Register. After a byte of data
has been received by the SPI Shift Register a Receive
Character Available (RCNIROO) interrupt and flag is generated. The next byte of data may be received at this time,
but the RxBUF Register must be cleared, or a Receive
Character Overrun (RxCharOverrun) flag is set in the
SCON Register and the data in the RxBUF Register is
overwritten.

Z86C95
Z8<1>DSP

PRELIMINARY
ERF (A) Bank C, Register 1

ERF (A) Bank C, Register 2

Iwloolool~loolml~lool
r- -r- -r- -

,SPI Enable
Receive Character Overrun (Slave)
Clock Frequency (Master)
o 0 Divlde-by-2
o 1 Dlvlde-by-4
1 0 Dlvide-by-8
1 1 Divide-by-16

Figure 41. SPI TXRXDATA Register

ERF (A) Bank C, Register 0

DOP (Slave)
o Enable DO as Output
1 Trl-state 00
Interrupt Enable
1 Enable 0 Disable

Figure 42. SPI Compare Register

Received Character Available
CLKP
o is Transmit on Falling
Receive Data on Rising Edge
1 Is Transmit on Rising
Receive Data on Failing Edge
SPI Clock Source Select (Master)
o Is Intemal Clock
1 Is Counter Timer 0 = 0
Address Compare Enable (Slave)
o is Disable 1 is Enable
1 Master 0 Slave

Figure 40. SPI Control Register (SCON)

1-41

PRELIMINARY

Z86C95

ZS"'DSP

Serial Peripheral Interface (Continued)
When the communication between the master and slave is
complete, the SS goes inactive. Unless disconnected, for
every bitthat is transferred into the slave through the 01 pin,
a bit is transferred out through the DO pin on the opposite
clock edge. During slave operation, the SPI clock pin (SK)
is an input (Figure 43). In master mode, the CPU must first
activate a SS through one of it's I/O ports. Next, data is
transferred through the master's DO pin one bit per master
clock cycle. Loading data into the shift register initiates the
transfer. In master mode, the master's clock drives the
slave's clock. At the conclusion of a transfer, a Receive
Character Available (RCA/I ROQ) interrupt and flag is generated. Before data is transferred through the DO pin, the
SPI Enable bit in the SCON Register must be enabled.
SPI Compare. When the SPI Compare Enable bit, 06 of the
SCON Register is set to 1, the SPI Compare feature is
enabled. The compare feature is only valid for slave mode.
A compare transaction begins when the SS line goes
active. Data is received as if it were a normal transaction,
but there is no data transmitted to avoid bus contention
with other slave devices. When the compare byte is received, IROQ is not generated. Instead, the data is compared with the contents of the SCOMP Register. If the data
does not match, DO will remain inactive and the slave will
ignore all data until the SS signal is reset.

SPI Clock. The SPI clock can be driven from three sources;
with TimerQ, a division of the internal system clock, or an
external master when in slave mode. Bit 06 of the SCON
Register controls what source drives the SPI clock. Divided-by-2, 4, 8, or 16 can be chosen as the scaler with bits
02, 01 in master mode.
'
Receive Character Available and Overrun. When a complete data stream is received an interrupt is generated and
the RxCharAvail bit in the SCON Register is set. Bit 4 in the
SCON Register is for enabling or disabling the RxCharAvail
interrupt. The RxCharAvail bit is available for interrupt
polling purposes and is reset when the RxBUF Register
is read. RxCharAvail is generated in both master and slave
modes. While in slave mode, if the RxBUF is not read
before the next data stream is received and loaded into
the RxBUF Register, Receive Character Overrun
(RxCharOverrun) occurs. Since there is no need for clock
control in slave mode, bit 01 in the SPI Control Register is
used to log any RxCharOverrun.

5K

55

DO

01

Figure 43. SPI Timing

1-42

Z86C95
Z8«>DSP

PRELIMINARY

Interrupts
The Z86C95 has six different interrupts from ten different
sources (Table 9). The interrupts are maskable and prioritized. The eight sources are divided as follow: four sources
are claimed by Port 3 lines P33-P30, one is Serial Out, one
is Serial In, and two in the counter/timers. The Interrupt
Mask Register globally or individually enables or disables
the six interrupt requests. When more than one interrupt is
pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority
register. All Z86C95 interrupts are vectored through locations in the program memory. When an interrupt machine
cycle is activated an interrupt request is granted. Thus, this
disables all of the subsequent interrupts, save the Program
Counter and Status Flags, and then branches to the
program memory vector location reserved for that interrupt. This memory location and the next byte contain the
16-bit address of the interrupt service routine for that
particular interrupt request.

service. Software initiated interrupts are supported by
setting the appropriate bit in the Interrupt Request Register
(IRQ).
Internal interrupt requests are sampled on the falling edge
of the last cycle of every instruction, and the interrupt
request must be valid 5TpC before the falling edge of the
last clock cycle of the currently executing instruction.
When the device samples a valid interrupt request, the
next 48 (external) clock cycles are used to prioritize the
interrupt, and push the two PC bytes and the FLAG register
on the stack. The following nine cycles are used to fetch the
interrupt vector from external memory. The first byte of the
interrupt service routine is fetched beginning on the 58th
TpC cycle following the internal sample point, which corresponds to the 63rd TpC cycle following the external
interrupts on the Z86C95.

To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is
polled to determine which of the interrupt requests need

Table 9. Z86C95 Interrupts
Name

Source

Vector

Comments

IRQO
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5

P3.2, SPI, A/D Start
P3.3, AID Finish
P3.2, TIN
P3.0, Serial In
TO, Serial Out
T1

0,1
2,3
4,5
6,7
8,9
10,11

Falling Edge Triggered
Falling Edge Triggered
Falling Edge Triggered
Falling Edge Triggered
Internal
Internal

1-43

Z86C95
Z8<8lDSP

PRELIMINARY

FUNCTIONAL DESCRIPTION (Continued)

Clock
The Z86C95 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, LC, ceramic
resonator, or any suitable external clock source (XTAL 1 =
input, XTAL2 = Output). The crystal should be AT cut, 1
MHz to 24 MHz max, and series resistance (RS) is less than

.----..---l XTAL 1

or equal to 100 Ohms. The crystal should be connected
across XTAL 1 and XTAL2 using the crystal vendor's recommended capacitors (10pF < CL < 100 pF) from each
pin Vss pin (Figure 44).

.---~---l XTAL1

D

---II)O----l XTAL 1

L

....--"---1 XTAL2

Ceramic Resonator
or Crystal

XTAL2

....--'----1 XTAL2

Extemal Clock

LC CLOCK

• VSS pin, not system ground

Figure 44. Oscillator Configuration

Power Down Modes
HALT. Will turn off the internal CPU clock but not the XTAL
oscillation. The counter/timers and the external interrupt
IRQO, IRQ1, IRQ2, and IRQ3 remains active. The devices
may be recovered by interrupts, either externally or internally generated. An interrupt request must be executed
(enabled) to exit HALT mode. After the interrupt service
routine, the program continues from the instruction after
the HALT.
STOP. This instruction turns off the internal clock and
external crystal oscillation and reduces the standby current to 10 j.tA or less. The STOP mode is terminated by a
/RESET, which causes the processor to restart the applica.tion program at address OOOCH.
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending
execution in mid-instruction. To do this, the user must
execute a NOP (opcode=OFFH) immediately before the
appropriate sleep instruction. I.e.:

1-44

FF
6F

NOP
STOP

FF
7F

NOP
HALT

; clear the pipeline
; enter STOP mode
or
; clear the pipeline
; enter HALT mode

PAUSE. This is similar to the STOP mode, except in the
recovery method, and the fact that the program counter
simply continues from where it paused instead of resetting
to OOOCH. PAUSE mode is entered by setting bit 0 of DSP
control register to 1 and executing a HALT instruction. All
the internal clocks are stopped during the PAUSE mode
thus resulting in very low power. To recover from the
PAUSE mode, the Z86C95 needs to see a negative going
transition on Port 32. This generates an interrupt and
operation can resume by simply doing an IRET in the
interrupt execution routine, The recovery time from PAUSE
mode is equal to the XTAL oscillator stabilization time + 1.3
ms (XTAL frequency of 20 MHz).

Z86C95

PRELIMINARY

Z8~DSP

Pulse Width Modulator (PWM)
This block provides a Pulse Width Modulated output at a
constant period based on the input clock.
The PWM provides an output waveform whose period is
either the internal system clock or the buffered XTAL input
divided by 256. The duty cycle of this waveform is
programmable by a register in the Extended Register File
of the Z8 and can have values from 0 to 99.6% (Reg = 0 to
255). A programmed value of Owill disable the counter and
place the PWM in a low power mode. Any non-zero value
programmed in this register will enable the PWM divider
and generate the selected output waveform.
The clock source for the PWM is programmable providing
the user access to a higher frequency clock versus using
the internal clock. The clock source is selected using Bit 7
of the OAC control register (ERF(A) Bank C, Register 6).
07=1 selects a buffered XTAL 1 clock, 07=0 selects XTAL
divided-by-2 (Figure 37).

Data Register (ERF (A) Bank C, Register E)

Iwl~I~I~lool~I~lool

I

Data

Figure 45. Pulse Width Modulation
Register Assignment
The PWM register is used to program the duty cycle of the
PWM. If the programmed value is 0, then the PWM is
disabled and the PWM output is OFF. For any non-zero
value the PWM output is a periodic waveform which is High
for (value/256)X100% of the period.

1-45

PRELIMINARY

Z86C95
Z8$DSP

DIGITAL SIGNAL PROCESSOR
The DSP slave processor is a 16-bit fixed point, two's
complement high-speed digital signal processor. The
basic concept behind the DSP megacell is to simplify the
architecture and instructions as much as possible, providing a user-friendly programming environment for various
DSP algorithms (Figure 47). Additionally, a convenient
mapping architecture was designed to allow the ZS to map
the DSP memory into the shared expanded register file
architecture of the ZS.

additional machine cycle is required to modify the PC
content. For instance, consider the example of a simple
branch instruction, "BRA NZ, 13S.At t= Tn", the pre-fetched
content of the pseudo instruction register, "BRA NZ, 13S",
starts to decode and execute while the pseudo PC is
automatically increased to "10S". Since the instruction is to
change the PC to "13S" if the condition is NZ, the next
fetched instruction would be treated as a NOP.

Indirect Addressing Mode
The ZS6C9S's DSP has two sets of high-speed on-chip
RAM for data storage. The RAM data specified by two
different RAM address registers or instruction address
field are read out in one machine cycle. Multiplication,
addition and register loading can be accomplished in one
clock cycle. The instructions are one cycle pipelined,
which are transparent to the users.

Architectural Overview
The ZS6C9S's DSP employs a 16-bit fixed point, two's
complement number system (Figure SO). The binary point
is assumed to be placed right next to the sign bit. DSP
algorithms are accomplished by single-cycle multiply/
accumulate instructions, two on-chip RAM banks, dedicated arithmetic logic unit, user-definable I/O for signal
processing and other functions. (See DSP Commands
Section below.)

Cycles Per Instruction
Most instructions are one machine cycle instructions which
are executed in 1 cycle time. Load register pointer immediate and Branch instructions need two machine cycles to
execute. Besides these execution machine cycles, one
more cycle is required if the PC (program counter) is
selected as the destination of a data transfer instruction.
This happens when register indirect branch is executed.
An a 1 *b 1 +ACC~ACC calculation is done in one machine
clock cycle modifying the RAM pointer contents. Both a1
and b1 can be RAM contents located in two independent
addresses. Since each instruction is fetched into the
instruction register one cycle earlier and the pre-fetched
instruction is decoded at the next machine cycle, one

1-46

Register INDIRECT addressing is the method of addressing within the ZS6C9S's DSP. This is accomplished by
means of four register pointers, two for each bank. These
pointers are RO and R1 for DSP RAM(O) and R2 and R3 for
DSP RAM(1). The register pointers are located within the
ZS/DSP interface register bank (Bank F in both ERF (A) and
ERF (B)). For example, "LDI RO, 14" will load "14" into the
register pointer RO. If followed by an instruction "LD (RO)"
for example the contents of the register in DSP RAMO
whose address is "14" will be loaded into the accumUlator
(Figures 4S and 49).

Arithmetic Logic Unit
Upon loading the DSP data RAM the ZS6C9S's DSP can
multiply two 16-bit integers and accumulate a 24-bit result
in one clock cycle. For example, an "MPYA (RO), (R1)" will
load the contents of the DSP RAM(O) registers pointed to
by RO and R1 respectively into the multiplier, multiply the
RAM(O) registers and add the result to the accumulator.
The result of the multiplication is available at the next
machine cycle.

DSP Single Step Timing
The occurrence of pre-selected DSP_PC stop address
and DSP_SYNC needs to be detected. DSP_SSN is pulled
high which stops the DSP until DSP_SSN is pulled low at
which time the DSP will execute until the nexttime DSP_SSN
is high. DSP_SSN should not be pulled high for second or
third bytes of multi-byte instructions, only for first byte of
multi-byte instructions or for single byte instructions (Figure 46).

Z86C95

PRELIMINARY

Z8~DSP

SCLK

DSP_PC
PinsA7-AO

: STOP:
I Addrl
I
I

U
I
I

I
I
I
I

I
I
I
I
I
I

I
I

-11-

SSN t50

LHJ

Ie

I)

I
I
I
I
I
I

I
I
I
I
I
I

I
I

-11-

SSN tsec

Figure 46. DSP Single Step Timing

1-47

Z86C95
zaczDSP

PRELIMINARY

DIGITAL SIGNAL PROCESSOR (Continued)

I

~

Data
RAM1
64x16

Data
RAMO
64x16

I

R2
R3
Z8

I
DSP

I

~

----01

AID

RO
R1

---

DAC

I
Program
RAM
512x8

Figure 47. Block Diagram of DSP

ERF (A) (B) Bank F, Register 6

1

ERF (A) (B) Bank F, Register 5

loolool~I~lool~I~lool
r-

r-

~L

loolool~I~lool~I~lool
OVerftowProtectlon
Multiply Output Shifted by 3
Not Used
LlnkBH

Zero Bit
1 -_ _ _ _ _ _ _ OVerftowBit
NegativeBt

Figure 48. DSP Status Register 1

1-48

~

Ram Pointer
000
001
01 0
01 1
1 00
1 01
1 1 0
111
Not Used

Figure 49. DSP Status Register 0

Loop Size
64
2
4
8
16
32
64
64

Z86C95
Z8<1lDSP

PRELIMINARY
Z8
16 Banks (working
register groups) of 16
registers per bank

Banks 1-E are
mapped into
DSP PGM Memory

ERFA
Bank E• Z8's Hardwired MultlplylDlvlde Registers
Bank D • Capture, Compare and Timer Registers

anksl.DSP

~

Program Memory

\

I'-

Banks B·E
:::L, ~ DSP RAM Data
Memory
Bank 101
ERF(A)

Bank F• Z8IDSP Interlace Register Bank

64x 16-BH
Bank E 01 ERF (B)

64 x 16-Blt
Bank E01 ERF (B)

ERFB

Bank B of ERF (B)

Bank B 01 ERF (B)

Bank 3 of ERF (A)
Bank 2 of ERF (A)

Bank 3 of ERF (A)
Bank 2 of ERF (A)

!

E
C
A

8

I

B
B

9

DSPRAM(l)
52 Registers 01
16-BHWords

I

!iI
0

iI
1

DSPRAM(O)
52 Registers of
16-BHWords

Figure 50. Z86C95 Memory Architecture

1-49

PRELIMINARY

Z86C95

Z8$DSP

ABSOLUTE MAXIMUM RATINGS
Symbol
Voo
TSTG
TA

Description

Min

Max

Supply Voltage'
Storage Temp
Oper Ambient Temp

-0.3
-65

+7.0
+150

t

t

Unit

V

C
C

• Voltages on all pins with respect to GND.
t See Ordering Information

Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended period may affect device reliability .

STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted (Figure 51).

V Commutation

Figure 51. Test Load Diagram

1-50

~2iu:a;

Z86C95
Z8DSP

P R ELIMINARY

DC ELECTRICAL CHARACTERISTICS

Vee =3.3V ±10%
Sym Parameter

VeH
Vel
VIH
Vll

Max Input Voltage
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage

VOH
VOH
VOL
VRH
VRI

Output High Voltage
Output High Voltage
Output Low Voltage
Reset Input High Voltage
Reset Input Low Voltage

III
IOl
IIR
lee

Input Leakage
Output Leakage
Reset Input Current
Supply Current

1CC1

HALT mode
PAUSE and STOP mode
Auto Latch Low Current

lee2
IAll

TA =DOC to +70°C
Min
Max

Typical
at 25°C

V
V
V
V
V

liN < 250 J.lI\
Driven by External Clock Generator
Driven by External Clock Generator

0.4
Vee
0.2 Vee

V
V
V
V
V

IOH =-1.0 rnA
IOH = -100 J.lI\
IOl =+1.0 rnA

J.lI\
J.lI\
J.lI\

Test at OV, Vee
Test at OV, Vee
VRl = OV
@24MHz[l]
HALT mode VIN=OV, Vee @ 24 MHz [1]
STOP mode VIN=OV, Vee [1]

2.0
Vee -l00mV
0.8 Vee
-0.3
-2
-2

-10

Condillons

Vee
0.1 Vee
Vee
0.2 Vee

7
0.8 Vee
-0.3
0.6 Vee
-0.3

Units

2
2
-120
50

40

rnA

15
20
10

10
6
5

rnA

J.lI\
J.lI\

Note:

[1] All inputs driven to av, Vee and outputs floating.

1-51

.2il.CE

Z86C95

PRELIMINARY

~DSP

DC ELECTRICAL CHARACTERISTICS

Vee

=5.0V ±10%

Sym Parameter

VeH
Vel
VIH
Vll

Max Input Voltage
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage

VOH
VOH
VOL
VfUi
VR1

Output High Voltage
Output High Voltage
Output Low Voltage
Reset Input High Voltage
Reset Input Low Voltage

III
IOl
I'R
lee

Input Leakage
Output Leakage
Reset Input Current
Supply Current

lee1

HALT mode

lee2
IAll

PAUSE and STOP mode
Auto Latch Low Current

TA = DOC to +7O°C
Min
Max

3.8
-0.3
2.0
-0.3

3.8
-0.03
-2
-2

-10

Units

Conditions

7
Vee
0.8
Vee
0.8

V
V
V
V
V

liN <250 IlA
Driven by External Clock Generator
Driven by External Clock Generator

0.4
Vee
0.8

V
V
V
V
V

IOH=-2.0 mA
IOH =-100 IlA
IOl =+2.0 mA

IlA
IlA
IlA

2.4
Vee-100 mV

Note:
[1] All inputs driven to av. Vee and outputs floating.

1-52

Typical
at 25°C

2
2
-120
82
120

50
70

rnA
mA

Test at OV. Vee
Test at OV. Vee
VRl = OV
@24MHz[1)
@33MHz[1)

20
30

13
20

mA
mA

HALT mode VI~OV. Vee @24MHz[1)
HALT mode VI~OV. Vee @33MHz[1)

20
10

6.
5

IlA
IlA

STOP mode VI~OV. Vee [1)

---------

ZS6C95
ZSil>DSP

PRELIMINARY
AC CHARACTERISTICS

External I/O or Memory Read/Write Timing Diagram

RJW,/DM

K

}

~

~

f--®--

12

Pori 0

}

K

AB-A15

~

18

Pori 1

}

00-071N

AO-A7

rg"

,~
lAS

/DS
(Readl

Porl1

~

3

I

8

hr~

}

~

.AO-A7

AO-A7

...

..

0

~

-"

17

~

}

lK

DO -07 OUT

~

AO-A7

--®-7

/DS
(WrHal

"

I

Figure 52. Extemal 110 or Memory Reacl/Wrlte Timing

1-53

~ZJl.CIG

Z86C95
za«'DSP

PRELIMINARY

AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table

No

Sym

Parameter

1
2
3
5

TdA(AS)
TdAS(A)
TdAS(DI)
TwAS
TdAZ(DSR)

Address Valid To lAS Rise Delay
IAS Rise To Address Hold Time
lAS Rise Data In Req'd Valid Delay
lAS Low Width
Address Float To IDS Fall (Read)

6
7
8
9
10

TwDSR
TwDSW
TdDSR(DI)
ThDSR(DI)
TdDS(A)

11
12
13
14
15

TA =O°C to +70°C
33 MHz··
24 MHz
Min
Max
Min
Max

13
20

130

85
0
40

ns
ns
ns
ns
ns

30
26
30
34
34

ns
ns
ns
ns
ns

90
28
0

IDS (Read) Low Width
IDS (Write) Low Width
IDS Fall (Read) To Data Req'd Valid Delay
IDS Rise (Read) to Data In Hold Time
IDS Rise To Address Active Delay

65
40

100
65

0
25

TdDS(AS)
TdR!W(AS)
TdDS(RIW)
TdDO(DSW)
ThDSW(DO)

IDS Rise To lAS Delay
R!W To Valid lAS Rise Delay
IDS Rise To R!W Not Valid Delay
Data Out To IDS Fall (Write) Delay
IDS Rise (Write) To Data Out Hold Time

16
12
12
12
12

16
17
18
19
20

TdA(DI)
TdAS(DSR)
TdDM(AS)
TdDS(DM)
ThDS(A)

lAS Rise To IDS Fall (Read) Delay
IDM Valid To lAS Rise Delay
IDS Rise To IDM Valid Delay
IDS Rise To Address Valid Hold Time

21
22
23
24

TdXT(SCR)
TdXT(SCF)
TdXT(DSRF)
TdXT(DSRR)

25
26
27
28
29

TdXT(DSWF)
TdXT(DSWF)
TsW(XT)
ThW(XT)
TwW

34"
34"

ns
ns
ns
ns
ns

XTAL Falling to SCLK Rising
XTAL Falling to SCLK Falling
XTAL Falling tolDS Read Falling
XTAL Falling to IDS Read Rising

20"
23"
29"
29"

ns
ns
ns
ns

XTAL Falling to IDS Write Falling
XTAL Falling to IDS Write Rising
Wait Set-up Time
Wail Hold Time
Wait Width (One Wait Time)

29"
29"
10'
15"
25"

ns
ns
ns
ns
ns

Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC .
• Preliminary value, to be characterized (24 MHz).
•• Preliminary engineering value, to be characterized.

1-54

30

Address Valid To Data Req'd Valid Delay

Units

ns
ns
ns
ns
ns

22
25

20
0

4

Typical
Vcc ·5.0V
@25°C

110
20
10

160
40
22

Z86C95

PRELIMINARY

~DSP

XlAl1

selK

----__+oi

DSR

r-®

I-@

----II

Dsw--------.L-I_ _ _

Figure 53. XTAUSCLK to DSR and DSW Timing

1-55

---~~~---~-

~.~.---

--~-----

~-----~

Z86C95
ZSilODSP

PRELIMINARY

AC CHARACTERISTICS (Continued)

Clock

TIN

~----~6r-----~

IRQN

Figure 55. Additional Timing

AC CHARACTERISTICS
Additional Timing Table

No

Symbol

Parameter

1
2
3
4

TpC
TrC,TlC
TwC
TwTinL

Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width

5
6
7
8a

TwTinH
TpTin
TrTin,TfTin
TwlL

8b
9

TwlL
TwlH

TA =DOC to +7O°C
24 MHz
33 MHz
Min
Min
Max
Max
42

30

11
75

10
75

Timer Input High Width
Timer Input Period
Timer Input Rise & Fall Times
Interrupt Request Input Low Times

3TpC
8TpC
100
70

3TpC
8TpC
100
70

Interrupt Request Input Low Times
Interrupt Request Input High Times

5TpC
3TpC

5TpC
3TpC

Notes:
[1] Clock timing references use 3.BV for a logic 1 and O.BV for a logic O.
[2] Timing references use 2.0V for a logic 1 and O.BV for a logic O.
[3] Interrupt references request through Port 3.
[4] Interrupt request through Port 3 (P33-P31).
[5] Interrupt request through Port 30.

1-56

1000
10

1000
5

Units

Notes

ns
ns
ns
ns

[1]
[1]
[1]
[2]
[2]

ns
ns

[2]
[2]
[2,4]

[2,5]
[2,3]

Z86C95
zrosp

PRELIMINARY

AC CHARACTERISTICS
Handshake Timing Diagrams

Data In

Data In Valid

~-~r- --;e~ ~;a~;~I~ - - - - - - -

- - - - - - - - --

~~r---------------------------IDAV

(Input)

RDY
(Output)

Delayed RDY
~-----\~i--'- -- -

I

- -- - --'

Figure 56. Input Handshake Timing

1I---------------1r---------------------·
Data Out

Data Out valid

Next Data Out valid

1--------------1r---------------------·
IDAV

(Output)

RDY
(Input)

Figure 57. Output Handshake Timing

1-57

~2il..CD3

Z86C95

Z8$DSP

PRELIMINARY

AC CHARACTERISTICS
Handshake Timing Table

TA = DOC to +70°C
No

Symbol

Parameter

Min

1
2
3

TsDl(DAV)
ThDl(DAV)
TwDAV

Data In Setup Time to /DAV
RDY to Data In Hold Time
/DAVWidth

0
0
40

4
5

TdDAVlf(RDYf)
TdDAVlr(RDYr)
TdRDYOr(DAVlf)

/DAV to RDY Delay
DAV Rise to RDY Wait Time
RDY Rise to DAV Delay

9

TdDO(DAV)
TdDAVOf{RDYlf}
TdRDYlf(DAVOr)

Data Out to DAV Delay
/DAV to RDY Delay
RDY to /DAV Rise Delay

10
11

TwRDY
TdRDYlr(DAVOf)

RDYWidth
RDY Rise to DAV Wait Time

6

7
8

1-58

Units

Data
Direction

ns
ns
ns

In
In
In

70
40

ns
ns
ns

In
In
In

TpC

70

ns
ns
ns

Out
Out
Out

40

ns
ns

Out
Out

Max

0
0
40

~------

.2il.ClG

Z86C95

PRE L IMINAR Y

Z8~DSP

AID Converter Electrical Characteristics

Vee =3.3V ±10%
Parameter

Minimum

Resolution
Integral non-linearity ~
Differential non-linearity
Zero Error at 25°C

Typical
8
0.5
0.5

Maximum

Units

1
1
5.0

Bits
LSB
LSB
mV
Volts
mW
MHz
Volts

Supply Range
Power dissipation, no load
Clock frequency
Input voltage range

VALO

3.3
40
24
VAH,

Conversion time
Input capacitance on ANA
VAH, range
VALO range
VAH, -VALO

25
VALO + 2.5
AN GNO
2.S

2
40
AVee
AVcc -2.5
AVec

J.l.S
pF
Volts
Volts
Volts

Typical

Maximum

Units

8
0.25
0.25
1.5
10

1
0.5
3.0
20

2.7

3.0
20

Notes:
Voltage 2.7 -3.3V
TempO-86°C

D/A Converter Electrical Characteristics
Vee =3.3V ±10%
Parameter

Minimum

Resolution
Integral non-linearity
Differential non-linearity
Setting time, 1/2 LSB
Zero Error at 2SoC
Full Scale error at 2SoC
Supply Range
Power dissipation, no load
Ref Input resistance
Output noise voltage
VD H, range at 3V
VDLO range at 3V
VD H, -VDLO' at 3V
Capacitive output load, CL
Resistive output load, RL
Output slew rate

1.S

0.25
3.0
10
4K
SO
1.8

0.2
1.3

0.5
1.6

50K
1.0

3.0

2.7
2K

O.S
3.3

Bits
LSB
LSB
J.l.S
mV

10K

LSB
Volts
mW
Ohms

2.1

Volts

0.8
1.9
20

Volts
Volts
pF
Ohms
V/J.l.S

~Vp-p

Notes:
Voltage 2.7-3.3V
Temp a-86°C

1·59

~2il..tE

Z86C95
-ZS®DSP

p R E L I MIN A R Y

AC CHARACTERISTICS (Continued)
AID Converter Electrical Characteristics

Vee
Parameter

Minimum

Resolution
Integral non-linearity
Differential non-I inearity
Zero Error at 25°C
Supply Range
Power dissipation, no load
Clock frequency
Input voltage range
Conversion time
Input capacitance on ANA
VAH1 range
VALO range
VAH1 -VALO

=5.0V ±10%
Typical

8
0.5
0.5
4.5

5.0
35

Maximum

1
1
5.0

Units

Bits
LSB
LSB
mV
Volts
mW

VALO

5.5
75
33
VAH1

25
VALO + 2.5
ANGND
2.5

2
40
AVec
AV
2.5
cc

A'0-

J.lS
pF
Volts
Volts
Volts

Typical

Maximum

Units

8
0.25
0.25
1.5
10

1
0.5
3.0
20

MHz

Volts

Notes:
Voltage 4.S-S.SV
Temp 0-86°C

D/A Converter Electrical Characteristics

Vee
Parameter

Minimum

Resolution
Integral non-linearity
Differential non-linearity
Setting time, 1/2 LSB
Zero Error at 25°C
Full Scale error at 25°C
Supply Range
Power dissipation, no load
Ref Input resistance
Output noise voltage
VD H1 range at 3V
VDLO range at 5V
VDH1-VD LO ' at 5V
Capacitive output load, CL
Resistive output load, RL
Output slew rate
Notes:
Voltage 4.S-S.SV
Temp 0-86°C

1-60

=5.0V ±10%

10K

LSB
Volts
mW
Ohms

2.6

3.5

Volts

0.8
0.9

1.7
2.7
30

Volts
Volts
pF
Ohms
V/J.lS

4.5
2K

20K
1.0

0.25
5.0
10
4K
50

3.0

0.5
5.5

Bits
LSB
LSB
J.lS
mV

~Vp-p

Z86C95

PRELIMINARY

Z8~DSP

EXPANDED REGISTER FILE CONTROL REGISTERS
T2TMR (D) 01

TOH (D) 04

1~lool~I~lool~I~lool

I

o

No Function
1 LoadT2

o

Disable T2 Count
1 Enable T2 Count

Count Mode
T2 Single Pass
1 T2Moduio N

TO High Byte Initial Value
(When Written)
TO High Byte Currenl Value
(When Read)

o

Interrupt Enabled
Disable
1 Enable

o

T20ut (P35)
o Disable
1 Enable

Figure 61. Counter Timer 0 Register High Byte
(OH 04: ReadlWrite)

T2H (D) 06

Resarved (Must be 0)

1~1~1~1~lool~I~lool

I

T2 CLOCK Source
o XTAUB
1 XTAL12

T2 High Byte Initial Value
(WhenWrillen)
T2 High Byte Currenl Value
(When Read)

T2 End 01 Count
o NotEOC
1 EOC

Figure 62. Counter Timer 2 Register High Byte
(OH 06: ReadlWrlte)
Figure 58. Timer 2 Mode Register
(OH 01: ReadlWrite)
T2L (D) crl

T1H (0)02

1~1~1~1~lool~I~lool

1~1~1~1~lool~I~lool

I

T1 High Byte Initial Value
(When Wrltten)
T1 High Byte Current Value
(When Read)

Figure 59. Counter Timer 1 Register High Byte
(OH 02: ReadlWrite)

I

T2 Low Byte Initial Value
(When Written)
T2 Low Byte Current Value
(When Read)

Figure 63. Counter Timer 2 Register Low Byte
(OH 07: ReadlWrite)

PRE2 (D) 03

1~1~1~1~lool~I~lool
II

=~-T1

T2

00

8

8

32

01
10
11

TO

16
8
8

16
24
16

16
16
24

Reserved
Prescaler Modulo
(Range: 1 • 16 Decimal
01·OOHex)

Figure 60. Prescaler 2 Register High Byte
(OH 03: Write Only)

1-61

Z86C95

PRELIMINARY

Z8~DSP

Z8 CONTROL REGISTER DIAGRAMS
R243 PREI

R240S10

Imloolool~lool~I~lool

I

Count Mode
o Tl Single Pass
1 Tl ModuloN

Serial Data (DO = LSB)

Clock Source
1 Tllntemal
o T1 External Timing Input
(TIN) Mode

Figure 64. Serial VO Register
(FOH: ReadlWrite)

Presealer Modulo
(Range: 1-64 Decimal
01-()0 HEX)
R241 TMR

Figure 67. Prescaler 1 Register
(F3H: Write Only)

0 No Function
1 Load TO
0 Disable TO Count
1 Enable TO Count
0 No Function
1 LoadTl

o

R244 TO

Imloolool~lool~I~lool

Disable Tl Count
1 Enable T1 Count

I

TIN
00
01
10

Modes
Extemal Clock Input
Gate Input
Trigger Input
(Non-retrlggerable)
11 Trigger Input
(Retrlggerable)

TO Low Byte Initial Value
(When Written)
TO Low Byte Current Value
(When Read)

Figure 68. CounterlTimer 0 Register
(F4H: ReadlWrite)

TOUT Modes
00 Not Used
01 TO Out
10 T1 Out
11 Intemal Clock Out
R245 PREO

Figure 65. Timer Mode Register
(F1H: ReadlWrite)
Count Mode
o TO Single Pass
1 TO Modulo N
ReselVed (Must be 0)
R242Tl

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

Imloolool~lool~I~lool

I

Tl

Low Byte Initial Value
(When Written)

T1

Low Byte Current Value
(When Read)

Figure 66. CounterlTimer 1 Register
(F2H: ReadIWrite)

Figure 69. Pres caler 0 Register
(F5H: Write Only)

R246 P2M
1071061051041031021011 Dol

I

P20 - P27 1/0 Definition
o Defines Bit as Output
1 Defines Bit as Input

Figure 70. Port 2 Mode Register
(F6H: Write Only)

1-62

Z86C95
Z8«>DSP

PRELIMINARY
R247 P3M

o Port 2 Pull-Ups Open Drain
1 Port 2 Pull-Ups Active
o P31, P321nputs
1 Reserved
0 P32= Input
1 P32 = IOAVOIADYO
00 P33 = Input
01
10 } P33 = Input
11

P35 = Output
P35 = RDYOIIDAVO
P34 = Output
P34-IOM

Reserved

0 P31 = Input (TIN)
1 P31 = IOAV2lADY2

P36 = Output (TOUT)
P36 = RDY2IIOAV2

0
1

P37 = Output
P37 • Serial OUT

P30= Input
P30 = Serial IN

0 Parity OFF
1 Parity ON

Figure 71. Port 3 Mode Register
(F7H: Write Only)

A2491PR

Interrupt Group Priority
000 Reserved
001 C>A>B
010 A>B>C
011 A>C>B
100 B>C>A
101 C>B>A
110 B>A>C
111 Reserved
IRQt, IRQ4 Priority (Group C)
IROI >IRQ4
1 IR04>IROI
IRoo, IR02 Priority (Group B)
o IR02>IRoo
1 IRoo> IR02
IR03, IR05 Priority (Group A)
o IR05 > IR03
1 IR03> IR05

o

Reserved

Figure 72. Interrupt Priority Register
(F9H: Write Only)

1-63

4'2JI..CE

Z86C95
Z8<11>DSP

PRELIMINARY

~

Z8 CONTROL REGISTER DIAGRAMS (Continued)
R250IRQ

R253 RP

1~1~1~1~lool~I~lool

1~1~1~1~lool~I~lool

1' - - - - -

IRQO = P32 Input, SPI, AID Start
IRQ1 = P33lnput, AID Finish
IROO = P31 Input
IROO = P30 Input, UART Input
1RQ4 = TO, UART Output
IRQ5=T1
L -_ _ _ _ _ _ _ _ Reserved

Figure 73. Interrupt Request Register
(FAH: ReadlWrite)

I

& . . . . . 1-

Expanded Register File
Working Register Pointer

Figure 76. Register Pointer
(FDH: ReadlWrite)

R254SPH

1~1~1~1~lool~I~lool
1

R2511MR

Stack Pointer Upper
Byte (SP8 - SPI5)

Figure 77. Stack Pointer High
(FEH: ReadlWrlte)

1 Enables IRQO-IRQ5
(00= IRoo)
Reserved (Must be 0)
1 Enables Interrupts
R255SPL

Figure 74. Interrupt Mask Register
(FBH: ReadlWrlte)
Stack Pointer Lower
Byte (SPO - SP7)

R252 FLAGS

Figure 78. Stack Pointer Low
(FFH: ReadlWrite)
User Rag F1
User Rag F2
Half Carry Rag
Decimal Adjust Rag
Overflow Rag
Sign Flag
Zero Rag
Carry Rag

Figure 75. Flag Register
(FCH: ReadlWrlte)

1-64

Z86C95
zrosp

PRELIMINARY

INSTRUCTION SET NOTATION
Addressing Modes. The following notation is used to

Flags. Control register (R252) contains the following six

describe the addressing modes and instruction operations as shown in the instruction summary.

flags:

Symbol

Meaning

IRR

Indirect register pair or indirect workingregister pair address
Indirect working-register pair only
Indexed ·address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect
working-register address
Indirect working-register address only
Register pair or working register pair
address

Irr

X
DA
RA

1M

R
r
IR
Ir

RR

Symbol

Meaning

C

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

Z

S
V
D
H

Affected flags are indicated by:

o
1

x

Clear to zero
Set to one
Set to clear according to operation
Unaffected
Undefined

Symbols. The following symbols are used in describing
the instruction set.
Symbol

Meaning

dst
src
cc

Destination location or contents
Source location or contents
Condition code
Indirect address prefix
Stack Pointer
Program Counter
Flag register (Control Register 252)
Register Pointer (R253)
Interrupt mask register (R251)

@

SP
PC
FLAGS
RP
IMR

1-65

~2il..CJG

Z86C95
Z8@DSP

PRELIMINARY

CONDITION CODES
Value

Mnemonic

Meaning

Flags Set

1000
0111
1111
0110
1110

C
NC
Z
NZ

Always True
Carry
No Carry
Zero
Not Zero

C= 1
C=O
Z=1
Z=O

1101
0101
0100
1100
0110

PL
MI
OV
NOV
EQ

Plus
Minus
Overflow
No Overflow
Equal

S=O
S=1
V=1
V=O
Z=1

1110
1001
0001
1010
0010

NE
GE
LT
GT
LE

Not Equal
Greater Than or Equal
Less than
Greater Than
Less Than or Equal

Z=O
(S XORV) = 0
(S XORV) = 1
[Z OR (S XORV)] = 0
[Z OR (S XOR V)] = 1

1111
0111
1011
0011
0000

UGE
ULT
UGT
ULE
F

Unsigned Greater Than or Equal
Unsigned Less Than
Unsigned Greater Than
Unsigned Less Than or Equal
Never True (Always False)

C=O
C= 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1

1-66

Z86C95

PRELIMINARY

ZS"'DSP

INSTRUCTION FORMATS
OPC

dst

CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC

One-Byte Instructions

OR 11

1'1 0

OPC

lOR 1111 0

dst

I
I

CLR, CPL, DA, DEC,
DECW, INC, INCW,
dstlsrc I POP, PUSH, RL, RLC,
RR, RRC, SRA, SWAP

I MODE

OPC

src

OR

dst

OR

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM,XOR

JP, CALL (Indirect)
dst

I MODE

OPC

dst
OPC

ORI 1110

I

dst

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM,XOR

VALUE

SRP

VALUE
MODE
ADC, ADD, AND, CP,
OR, SBC, SUB, TCM,
TM,XOR
LD, LDE, LDEI,
LDC,LDCI

MODE
dstlsrc

I

OPC

LD

src

OR

dst

OR

I
I

OPC

LD

x

ADDRESS

OR 1111 0

I

LD

I

cc

src

OPC

JP

DAU
LD

I L
dstiCC

OPC
DJNZ, JR

OPC

CALL

DAU
DAL

FFH
6FH

DAL

STOP/HALT
7FH

Three-Byte Instructions

Two-Byte Instructions

INSTRUCTION SUMMARY
Note: Assignment of a value is indicated by the symbol
" f- ". For example:
dst f- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The

notation "addr (n)" is used to refer to bit (n) of a given
operand location. For example:
dst (7)
refers to bit 7 of the destination operand.

1-67

1-68

~2il..!E
Instruction
and Operation

Address
Mode
dst src

NOP
OR dst, src
dstf--dst OR src

t

POP dst
dstf--@SP;
SPf--SP + 1

R
IR

PUSH src
SPf--SP -1;
@SPf--src

Flags
Opcode
Affected
Byte (Hex) C Z S V 0 H

Instruction
and Operation

FF

STOP

4[ ]

R
IR

-

**0

50
51

- - - - - -

70
71

- - - - - -

- - - - -

RCF
Cf--O

CF

0

RET
PCf--@SP;
SPf--SP + 2

AF

- - - - - -

RLdst

~
RLC dst

l&-I

7

ot-J

RR dst

L:fu4t5P
RRCdst

l-@H7

otJ

SBC dst, src
dstf--dstf--srcf--C

R
IR

90
91

****--

R
IR

10
11

****-

R
IR

EO
E1

****--

R
IR

CO
C1

****- -

t

3[ ]

**** *

DF

1

DO
D1

***0

~
SRP src
RPf--src

-

Address
Mode
dst src

Flags
Opcode
Affected
Byte (Hex) C Z S V 0 H
6F

- - - -

SUB dst, src
dstf--dstf--src

t

2[ ]

SWAPdst

R
IR

FO
F1

****1 *
X
**X - -

TCM dst, src
(NOT dst)
AND src

t

6[ ]

-

**0

-

TM dst, src
dstAND src

t

7[ ]

-

**0

- -

XOR dst, src
dstf--dst
XOR src

t

S[ ]

-

**0

- -

17

55

01
-

t These instructions have an identical set of addressing modes, which
are encoded for brevity. The first opcode nibble is found in the instruction
set table above. The second nibble is expressed symbolically by a '[ ]'
in this table, and its value is found in the following table to the left of the
applicable addressing mode pair.
For example, the opcode of an ADC instruction using the addressing
modes r (destination) and Ir (source) is 13.

Address Mode
dst
src

Lower
Opcode Nibble
[2]

SCF
Cf--1
SRA dst

Z86C95
Z8'"DSP

P R E L 1M I N A R Y

R
IR

1m

31

1

-

- - - - -

-

-

-

- -

-

Ir

[3]

R

R

[4]

R

IR

[5]

R

1M

[6]

IR

1M

[7]

-

1-69

Z86C95

PRELIMINARY

Z8~DSP

OPCODEMAP
Lower Nibble (Hex)

o
o

2

3

4

5

6

2

3

4

5

6

7

8

9

65

65

105

105

10.5

10.5

65

6.5

ADD

LD

C

D

E

65

12.10.0

65

B

A

F

65

65

DEC

DEC

ADD

ADD

ADD

ADD

ADD

R1
6.5

IR1
6.5

r1. r2
65

r1,lr2
6.5

R2, R1
10.5

IR2, R1
10.5

R1,IM
10.5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC

R1
6.5

IR1
65

r1, r2
65

r1,lr2
6.5

R2, R1
105

IR2, R1
10.5

R1,IM
10.5

IR1,IM
10.5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB

R1
80

IR1
61

r1, r2
6.5

r1,lr2
65

R2, R1
10.5

IR2, R1
10.5

R1,IM
10.5

IR1,IM
10.5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR1
85

1M
85

r1, r2
65

r1,lr2
65

R2, R1
105

IR2, R1
10.5

R1,IM
105

IA1,IM
105

DA

DA

OR

OR

OR

OR

OR

OR

R1
10.5

IR1
10.5

r1, r2
6.5

r1,lr2
6.5

R2, R1
10.5

IA2, R1
105

R1,IM
10.5

IR1,IM
10.5

POP

POP

AND

AND

AND

AND

AND

AND

R1
65

IR1
65

r1, r2
6.5

r1,lr2
65

R2, R1
105

IR2, R1
105

R1,IM
10.5

IR1,IM
105

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

r-e:o
STOP

IR1,IM
10.5

'7:0

IR1,IM r1, R2
10.5

12/10.5 12/10.0

LD

DJNZ

JR

LD

JP

INC

r2, R1

r1, RA

ee, RA

r1,IM

ee, DA

r1

I-I-I-I-I--

i

R1
IR1
10/12.1 12/14.1

r1, r2
6.5

r1,lr2
6.5

R2, R1
10.5

IR2, R1
10.5

R1,IM
10.5

.!! 7

PUSH PUSH

TM

TM

TM

TM

TM

TM

r1, r2
12.0

r1,lr2
180

R2, R1

IR2, R1

R1,IM

IR1,IM

LDE

LDEI

DI

e.

......
Z
~

R2
105

8

Q,
Q,

IR2
10.5

DECW DECW

HALT

~

RR1
6.5

IR1
65

r1 Irr2
12.0

Ir1 Irr2
180

~

RL

RL

LDE

LDEI

EI

R1
10.5

IR1
105

r2 Irr1
6.5

Ir2 Irr1
6.5

INCW

INCW

CP

CP

CP

CP

RR1
65

IR1
65

r1, r2
65

r1,lr2
6.5

R2, R1
10.5

IR2, R1
105

CLR

CLR

XOR

XOR

XOR

XOR

R1
6.5

IR1
65

r1, r2
12.0

r1,lr2
18.0

R2, R1

IR2, R1

C

RRC

RRC

LDC

LDCI

R1
65

IR1
6.5

D

SRA

SRA

A1
6.5

IR1
6.5

RR

RR

R1
85

IR1
85

:::l

9

A

B

E

F

r1,lrr2 Ir1,lrr2
12.0
18.0

LDC

R1

IR1

105

10.5

10.5

CP

CP

'14.0
RET

R1,IM IR1,IM
10.5
105

XOR

r-w-o
IRET

XOR

R1,IM IR1,IM
10.5

r-ss
RCF

LD
20.0

CALL

LD

IRR1
10.5

105

DA
10.5

r2,x,R1
10.5

LD

LD

LD

LD

LD

r1,IR2
6.5

R2, R1

IR2, R1
105

R1,IM

IR1,IM

LD

LD

Ir1, r2

R2,IR1

r---s:s
SCF

r1,x,R2
105

200

CALL'

LDCI

r1,lrr2 Ir1,lrr2
6.5

SWAP SWAP

105

r-ss
CCF

r-so
NOP
Y

y

2

3

3

2

Bytes per Instruction
Legend:
Execution
Cycles

Pipeline
Cycles

=
=

R S-blt Address
r 4-bit Address
R1 or r1
R2 or r2

Mnemonic

=Dst Address
=Sre Address

Sequence:
Opeode, First Operand,
Second Operand

First
Operand

Second
Operand

Note: Blank areas not defined.
'2-byte instruction appears as
a 3-byte instruction

1-70

y

- --

Z86C95

PRELIMINARY

Z8~DSP

DSP COMMANDS
7

432

0

1110101; Isl811111

Addressing:
(Ri) is specified by both the bank bit (Bit 3) and bit 2 as
follows.

LD (Ri),ADC
Instruction: 1 Byte
Cycle:
1 Cycle

B

S

o

o

o

Operation:
The contents of the ADC register are copied to the register
specified by the register pointer.
ADC -7 (Ri)

1

o

1
1

1

RO
R1
R2
R3

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).
R2 and R3 are register pointers associated with DSP Data
Memory RAM(1)

Flag change: No
The ADC register is a Read - Only register as far as the DSP
is concerned. It may be used to transfer the current AID
conversion result into DSP memory space.

7

4, 3

2

111010111s181

1

0

p

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).
R2 and R3 are register pointers associated with DSP Data
Memory RAM(1).

ST (Ri)

P field (modification field for register pointers):

Instruction: 1 Byte
Cycle:
1 Cycle

o
Operation:
The contents ofthe accumulator are stored into the register
specified by the register pointer.
Accumulator -7 (Ri)
Flag change: No
Addressing:
(Ri) is specified by both the bank bit (bit 3) and bit 2 as
follows:

B

S

o

o

o

1

1

o

1

1

o

o
1

1

o

1

1

NOP
+1
-1 Loop
ILLEGAL

Example:
The instruction ST (R2-) will store the accumulator into the
register whose address is specified by R2 and then it will
decrement R2.
Quick reference:
Accumulator -7 (Ri)
Ri + 1 or Ri - 1 or Ri -7 Ri

RO
R1
R2
R3

1-71

Z86C95
Z8®DSP

PRELIMINARY

DSP COMMANDS (Continued)
7

432

1

0

11101010101011111

Accumulator

~

DAC

Flag change: No
The DAC register is a write-only register as far as the DSP
is concerned. It may be used to transfer the DSP results
into the D/A converter register.

STDAC
Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
The contents of the accumulator are copied to the DAC
register.

7

432

11101110ls181

1 0
p

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).
R2 and R3 are register pointers associated with DSP Data
Memory RAM(1).

ADD (Ri)
P field (modification field for register pointers):

Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
The contents of the register specified by the register
pointer are added to the accumu lator. Ri register is modified
according to the P field after execution.
Accumulator ~ Accumulator + (Ri)

Flag change: Yes (OV). (L). (Z). (N)
Addressing:
(Ri) is specified by both the bank bit (bit 3) and bit 2 as
follows:

B

S

o
o

o

1
1

1-72

1

o
1

RO
R1
R2
R3

o
o
1
1

o
1

o

NOP
+1
-1 Loop
+1 Loop

Example:
The instruction ADD (RO+) will add the accumulator with
the register whose address is specified by RO and then it
will increment RO.
Quick reference:
Accumulator ~ Accumulator + (Ri)
Ri + 1 or Ri - 1 or Ri ~ Ri

Z86C95
Z8<1>DSP

PRELIMINARY
7

432

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).

1 0

11 1011 11 IB Is I

P

1

R2 and R3 are register pointers associated with DSP Data
Memory RAM(1).

SUB (Ri)

P field (modification field for register pointers):

Instruction: 1 Byte
Cycle:
1 Cycle

o
o

Operation:

1
1

The contents of the register specified by the register
pointer are subtracted from the accumulator. Ri register is
modified according to the P field after execution.
Accumulator

~

o

NOP
+1
-1 Loop
+1 Loop

1

o
1

Example:

Accumulator - (Ri)

Flag change: Yes (OV), (L), (Z), (N)

The instruction SUB (RO+) will subtract the register whose
address is specified by RO form the accumulator and then
it will increment RO.

Addressing:

Quick referen.ce:

(Ri) is specified by both the bank bit (bit 3) and bit 2 as
follows:

B

S

o
o

o

RO
R1
R2
R3

1

o

1
1

1

7

5

4

Addressing:

320

11 11 I0 IRll Rd

P

I

(Ri) is specified by bit 4 and (Rj) by bit 3 as follows:
If bit 4 = 0, RO is selected else R1 is selected.
If bit 3 = 0, R2 is selected else R3 is selected.

MLD (Ri),(Rj)

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).

Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
The contents of the RAM registers whose address is
specified by the register pointers Ri and Rj are copied to
the multiplier temporary registers X and Y respectively. Ri
specifies the addresssfor DSP DataRAM(O) and Rj specifies
the address for DSP Data RAM(1). Ri,Rj are modified
according to the modification field P after accumulator is
cleared.

Quick reference:

X ~ (Ri)
Y ~ (Rj)
Accumulator

~

Accumulator ~ Accumulator - (Ri)
Ri + 1 or Ri - 1 or Ri ~ Ri

0

Flag change: No

R2 and R3 are register pointers associated with DSP Data
Memory RAM(1).
P field (modification field for register pointers):

P(2:0)

Ri

Rj

000
001
010
011

NOP
NOP
+1
+1

+1
-1 Loop
NOP
+1

100
101
110
111

+1
-1 Loop
-1 Loop
-1 Loop

-1 Loop
NOP
+1
-1 Loop

1-73

-

-

-~~---~-

..

-----------~~~-

Z86C95

PRELIMINARY

ZS'"DSP

DSP COMMANDS (Continued)
765

10 101

4
Rj

3

2

1
Ri

0

I

MPYA (Rj),(Ri)

Operation:
The multi pier output is added to the accumulator. Then, the
contents of the RAM registers whose address is specified
by register pointers Ri and Rj are copied to the multiplier
temporary registers X and Y respectively. Ri specifies the
address for DSP Data RAM(O) and Rj specifies the address
for DSP Data RAM(1). Ri,Rj are modified according to the
modification field P after the copy execution.

X~(Ri)

Y ~ (Rj)

R2 and R3 are register pointers associated with DSP Data
Memory RAM (1).
Modification field for register pointers:
Bit 1IBit 4

Bi to/Bit 3

RilRj

0
1
0
1

NOP
+1
-1 Loop
+1 Loop

Accumlator + P

765

10 11 1

4

321

Rj

Ri

0

MPYS (Rj),(Ri)
Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
The multi pier output is subtracted from the accumulator.
Then, the contents of the RAM registers whose address is
specified by register pointers Ri and Rj are copied to the
multiplier temporary registers X and Y respectively. Ri
specifies the address for DSP Data RAM(O) and Rj specifies
the address for DSP Data RAM(1). Ri,Rj are modified
according to the modification field P after the copy
execution.
Quick reference:
X~(Ri)

Y ~ (Rj)
Accumulator ~ Accumlator - P
Ri + 1 or Ri - 1 or Ri ~ Ri
Rj + 1 or Rj - 1 or Rj ~ Rj

1-74

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).

0
0
1
1

Quick reference:

~

Addressing:
(Ri) is specified by bits 2-0 and (Rj) by bit 5-3 as follows:
If bit 2 = 0, RO is selected else R1 is selected.
If bit 5 = 0, R2 is selected else R3 is selected.

Instruction: 1 Byte
Cycle:
1 Cycle

Accumulator

Flag change: Yes (OV), (L), (2), (N)

Flag change: Yes (OV), (L), (2), (N)
Addressing:
(Ri) is specified by bits 2-0 and (Rj) by bit 5-3 as follows:
If bit 2 = 0, RO is selected else R1 is selected.
If bit 5 = 0, R2 is selected else R3 is selected.
RO and R1 are register pointers associated with DSP Data
Memory RAM(O).
R2 and R3 are register pointers associated with DSP Data
Memory RAM (1).
Modification field for register pointers:
Bit 1/Bit 4
0
0
1
1

Bit alB it 3

RilRj

0
1
0
1

NOP
+1
-1 Loop
+1 Loop

Z86C95
ZSIllDSP

PRELIMINARY
7

6

5

4

3

2

1

0

1111111cond I opcode

I

MODcond,OP

Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
The contents of the accumulator are modified ifthe condition
is met. Otherwise a NOP is executed. The exact nature of
the accumulator modification is specified by the OPCODE
field.

Opcode

Mnemonic

000
001
010
011

ROR
ROL
SHR
SHL

Rotate Right
Rotate Left
Arithmetic Right Shift
Arithmetic Left Shift

(OV)
(OV)
(OV)
(OV)

(Z)
(Z)
(Z)
(Z)

(N)
(N)
(N)
(N)

100
101
110
111

INC
DEC
NEG
ABS

IncrementA
Decrement A
Negate A
Absolute A

(OV)
(OV)
(OV)
(OV)

(Z)
(Z)
(Z)
(Z)

(N)
(N)
(N)
(N)

Condition Field:

Bit 4

Bit 3

o
o

0

1

0

1

1

1

ILLEGAL
Always True (MOD. always. OP)
IF OV = 1 (MOD. OV = 1. OP)
IF N = 1 (MOD. N = 1. OP)

Operation

Flags

If the condition is met then
000
(L) -+ a15. a15 -+ a14 ...... a1 -+ aO. aO -+ (L)
001
(L) t- a15. a15 t- a14 ...... a1 t- aO. aO t- (L)
010
Accumulator/2 -+ Accumulator
011
Accumulator*2 -+ Accumulator
100 Accumulator+ 1 -+ Accumulator
101
Accumulator-1 -+ Accumulator
110 -Accumulator -+ Accumulator
111
IAccumulatorl -+ Accumulator

Flag change: Yes (OV). (L). (Z). (N)

1-75

Z86C95
ZSIllDSP

PRELIMINARY

DSP COMMANDS (Continued)
7

4

3

2

1

0

11101010lalsl pi

RO and R1 are register pointers associated with DSP Data
Memory RAM(O).
R2 and R3 are register pOinters associated with DSP Data
Memory RAM(1).

LD (RI)

P field (modification field for register pointers):

Instruction: 1 Byte
Cycle:
1 Cycle

o
o

Operation:
The contents of the register specified by the register
pointer are copied to the. accumulator.
(Ri) -+ Accumulator

Flag change: No
Addressing:
(Ri) is specified by both the bank bit (bit 3) and bit 2 as
follows:
B

s

o
o

o
1

o

1
1

1

Quick reference:

RO
R1
R2
R3

Addressing:
(Ri) is specified by bits (1 :0) as follows.

Instruction: 2 Bytes
Cycle:
2 Cycles
Operation:
The register pOinters (RO, R1, R2, R3) are loaded with the
immediate value specified

1-76

1

Example:
The instruction LD (RO+) will load the accumulator with the
register whose address is specified by RO and then it will
increment RO.

Immediate Data

No

+1
-1 Loop
ILLEGAL

o

1
1

LOIRi

Flag change:

NOP

1

(Ri) -+ Accumulator
Ri + 1 or Ri - 1 or Ri -+ Ri

76543210
1111111010101 Ri I

I

o

Bit 1

Bit 0

o
o
1

o
1
o

1

1

Quick reference:
Ri

f-

Immediate data

RO
R1
R2
R3

Z86C95

PRELIMINARY
7

6

5

4

321

0

11 11 10 10 11 1cond 1

11

Branch Address MSB

Z8~DSP

Quick reference:
If condition
Else,

= True,

then

Pseudo PC = Branch address
Pseudo PC = Pseudo PC + 1

Branch Address LSB

BRA cond,addr
Instruction: 3 Bytes
Cycle:
3 Cycles
Operation:
The condition is tested and the branch is taken if the
condition is true. The branch address has to be within the
internal program memory space (512 bytes).
Flag change: No
Branch conditions are specified as follows:

Bit 1

Bit 0

o
o

o

Branch on NOT ZERO
Branch on OVERFLOW
Branch ALWAYS
Branch on LINK bit SET

1

o

1
1

1

7

6

5

4 3

2 1 0

11101010101111111
DSPSTOP

Instruction: 1 Byte
Cycle:
1 Cycle
Operation:
This instruction will stop the DSP.
Flag change: No

1-77

Z86C95

Z8$DSP

PRELIMINARY

PACKAGE INFORMATION
~-----------HD------------~

_----D-------.,

L

i

!
I

.- _._._._._.+i _._._._._._.
!
I
!

E

HE

!

0-12-

b

MILLIMETER
MIN
MAX
0.10
0.30
2.60
2.80
0.45 _
0.30

c:
HD
D
HE
E
II!I
L

0.13
0.20
23.80
24.40
20.10
19.90
17.80
18.40
13.90
14.10
0.80 TYP
0.70
L20

SYMBDL
NOTES,
I.. CONTROLLING DIMENSIONS , MILLIMETER
2. MAX COPLANARITY , JlI.!)'lm
.004"

AI
A2

I

80-Pin QFP Package Diagram

1-78

INCH
MAX
MIN
.004
.012
.102
.110
.012
.018
.005
.008
.937
.961
.783
.791
.701
.724
.547
.55:1
.031 TYP
.028
.047

I

Z86C95
Z8"'DSP

PRELIMINARY

D
D\
4~'

'"

U

I'

,.

1

"


I

"-----:-----ill
i
I
I

32

:1:1-

53

NIlTES·
L CDNTR[]I..LING DIHENSICNS • INCH

I!. LEADS ARE COPLANAR W!THIN
3. DIMENSIl!N • ...H!L
INCH

~04

SYMB[]I..
IN.

A
A\

DIE
DIIEI
D2

•

MILLIMETER

MIN

MAX

4.57
4.32
2.6'1
2.92
30.35
30.10
29.41
2921
28.58
27.9.
127 TYP

INCII
MIN

MAX

.170

.ISO
JI5
1.195
1.158
Ll25
TYP

J~

US5
I.lSO
1.100
~50

84-Pin PLCC Package Diagram

1-79

Z86C95

PRELIMINARY

~DSP

PACKAGE INFORMATION (Continued)
A

SYMBDL

A2

AI

-----I" L

III

1.60
1.35
0.20
0.05
1.30
1.50
0.15
0.26
0.10
D.20
16.15
15.85
14.10
13.90
16.15
15.85
14.10
13.90
0.50 TYP

L
LE

0.35
0.90

A
AI
A2
b

c
HD
D
HE

E

100

~JL

LE

r--=

c

100-Pln VQFP Package Diagram

1-80

MILLIMETER
MAX
MIN

I
I

0.6!!
1.10

INCH
MIN

MAX

.053
.002
.051
.006
.004
.624
.547
.624

.063
.008

.059
.010
.008
.636
.555
.636
.547
.555
.020 TYP

.014 j

.D26

i

.043

.035

I. CONTROlLING DIMENSIONS , 14M
2. MAX C!lPLANARITY , JDtz
.004'

PRELIMINARY

Z86C95

Z8~DSP

ORDERING INFORMATION
Z86C95
84-pin PLCC
Z86C9524VSC

24 MHz
80-pin QFP
Z86C9524FSC

100-pin VQFP
Z86C9524ASC

84-pin PLCC
Z86C9533VSC

33 MHz
80-pin QFP
Z86C9533FSC

10o-pin VQFP
Z86C9533ASC

For fast results, contact your local Zilog sales office for assistance in ordering the part desired.

Package
V = Plastic Chip Carrier
Longer Lead Time
F = Plastic Quad Flat Pack
A = Very Small QFP
Temperature
S = 0° C to +70° C
Speed
24 = 24 MHz
33 = 33 MHz
Environmental
C = Plastic Standard
Example:
Z86C9523ASC

~

is a Z86C95, 33 MHz, VQFP, DoC to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix

1-81

Introduction

lSBC95 l8® Digital
Signal Processor

II

Z89COO 16·llt Digital I!I
Signal Processor KIll

l89COO DSP
plication Note

Z89120, l89920 (ROMless)
16..Bit Mixed Signal Processor

Z89121, Z89921 (ROMless)
16..Bit Mixed Signal Processor

PRELIMINARY PRODUCT SPECIFICATION

Z89COO
16-81T DIGITAL
SIGNAL PROCESSOR
FEATURES
•

16-Bit Single Cycle Instructions

•

16-Bit I/O Port

•

Zero Overhead Hardware Looping

•

4K Words of On-Chip Masked ROM

•

16-Bit Data

•

Three Vectored Interrupts

•

Ready Control for Slow Peripherals

•

64K Words of External Program Address Space

•

Single Cycle Multiply/Accumulate (100 ns)

•

Two Conditional Branch Inputs/Two User Outputs

•

Six-Level Stack

•

24-Bit ALU, Accumulator and Shifter

•

512 Words of On-Chip RAM

•

IBM PC Development Tools

•

Static Single-Cycle Operation

GENERAL DESCRIPTION
The Z89COO is a second generation, 16-bit, fractional,
two's complement CMOS Digital Signal Processor (DSP).
Most instructions, including multiply and accumulate,
are accomplished in a si(1gle clock cycle. The processor
contains 1 Kbyte of on-chip data RAM (two blocks of
256 16-bit words), 4K words of program ROM and 64K
words of program memory addressing capability. Also,
the processor features a 24-bit ALU, a 16 x 16 multiplier, a
24-bitAccumulator and a shifter. Additionally, the processor
contains a six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of three pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be
simultaneously addressed and loaded to the multiplier for
a true single cycle multiply.

Development tools for the IBM PC include a relocatable
assembler, a linker loader, and an ANSI-C compiler. Also,
the development tools include a simulator/debugger, a
cross assembler for the TMS320 family assembly code
and a hardware emulator.
To assist the user in understanding the Z89COO DSP Q15
two's complement fractional multiplication, an application
note has been included in this product specification as an
appendix.
Notes:

Power connections follow conventional descriptions below:

Connection
There is a 16-bit address and a 16-bit data bus for external
program memory and data, and a 16-bit I/O bus for
transferring data. Additionally, there are two general
purpose user inputs and two user outputs. Operation with
slow peripherals is accomplished with a ready input pin.
The clock may be stopped to conserve power.

'r,

All Signals with a preceding front slash,
are active Low, e.g.,
BIN/ (WORD is active Low); IBN! (BYTE is active Low, only).

Circuit

Device

Power
Ground

2-1
~~
~~--~~---

C)

I\)

N

m
z
m

::u

External Program ROM
P015-POO
16

>
rC

PA15-PAO

m

1...-..,....-.....14

TT

IROMEN

256 Word
RAM

256 Word

RAM

o

1

"11

z
00

~

s·

c

EXT15-EXTO

CiJ

:-"
C
:::J

!l

0"
!!!..
m
:::J

g

16x16
Multiplier
24-bit0

en
:!!
0

-I

cO"

"11

~

5

4K
Word
ROM

Register
Pointer
4-6

~

'tI

16
Register
Pointer
0-2

~)

~

16-bit
1/0
Port

IROVE
ERIIW,/EI
EA2-EAO

c

S

I'"
:tl

..."
r-

:s::
~

~

INT2-INTO

C

».
:tl

~

IRESET

-..;:

iil
3

Status
(5)

User
Port

~

UI1-UIO
U01-UOO

I"l>

""=I
C

e

~

........

U>

is
z:

8N
rna>

!:ll;!i;
oC>
:DO

PRELIMINARY

9
VSS

10

POO

11

P01

12

P02

13

P03

14

P04

15

P05

16

P06

17

P07

18

P08

19

P09

20

P010

21

P011

22

P012 '

23

P013

24

P014

25

P015

26

8

7

6

5

4

3

2

Z89COO
16-BIT DIGITAL SIGNAL PROCESSOR

1 68 67 66 65 64 63 62 61

•

Z89COO

Figure 2. 68-Pin PLCC Pin Assignments

2-3

~2iUE

PRELIMINARY

Z89COO
l6·Brr DlGrrAL SIGNAL PROCESSOR

Table 1. 58-Pin PlCC Pin Identification
No.

Symbol

Function

Direction

1-9
10
11-26
27-38

EXT15-EXT7
Vss
PD15-PDO
PAll-PAO

External data bus
Ground
Program data bus
Program address bus

Input/Output
Input
Input
Output

39
40-43
44-46
47

Voo
PA15-PA12
EA2-EAO
lEI

Power Supply
Program address bus
External address bus
RNJ for external bus

Input
Output
Output
Output

48
49
50
51

ER/NJ
IRDYE
IRES
ClK

External bus direction
Data ready
Reset
Clock

Output
Input
Input
Input

52
53
54-55
56-58

IROMEN
HALT
Ull-UIO
INT2-INTl

Enable ROM
Stop execution
User inputs
Interrupts

Input
Input
Input
Input

59-60
61-64
65
66-68

U01-UOO
EXT3-EXTO
Vss
EXT6-EXT4

User outputs
External data bus
Ground
External data bus

Output
Input/Output
Input
Input/Output

PIN FUNCTIONS
ClK Clock (input). External clock. The clock may be
stopped to reduce power.
EXT15-EXTO External Data Bus (input/output). Data bus
for user defined outside registers such as an ADC or DAC.
The pins are normally in output mode except when the
outside registers are specified as source registers in the
instructions. All the control signals exist to allow a read or
a write through this bus.

ERlIW External Bus Direction (output, active low). Data
direction signal for EXT-Bus. Data is available from the
CPU on EXT15-EXTOwhen this signal is low. EXT-Bus is in
input mode (high-impedance) when this signal is High.
EA2-EAO External Address( output). User-defined register
addressoutpul. One of eight user-defined external registers
is selected by the processor with these address pins for
read or write operations. Since the addresses are part of
the processor memory map, the processor is simply
executing internal reads and writes.

2-4

lEI Enable Input (output). Write timing signal for EXT-Bus.
Data is read by the external peripheral on the rising edge
of lEI. Data is read by the processor on the rising edge of
ClK, not lEI.
HALT Halt State (input). Stop Execution Control. The CPU
continuously executes NOPs and the program counter
remains at the same value when this pin is held High. This
signal must be synchronized with ClK.
INT2-INTO Three Interrupts(rising edge triggered). Interrupt
request 2-0. Interrupts are generated on the rising edge of
the input signal. Interrupt vectors for the interrupt service
starting address are stored in the program memory locations
OFFDH for INTO, OFFEH for INTl and OFFFH for INT2.
Priority is: 2 = lowest, 0 = highest.
PA15-PAO Program memory address bus (output). For up
to 64K x 16 external program memory. These lines are tristated during Reset low.

PRELIMINARY
PD15-PDO Program Memory Data Input (input). Instructions or data are read from the address specified by PD15PD~, through these pins and are executed or stored.

IRES Reset(input, active Low). Asynchronous reset signal.
A Low level on this pin generates an internal reset signal.
The IRES signal must be kept Low for at least one clock
cycle. The CPU pushes the contents of the PC onto the
stack and then fetches a new Program Counter (PC) value
from program memory address OFFCH after the Reset
signal is released. RES Lowtri-states the PA and PD bases.
/ROMEN ROM Enable(input). An active Low signal enables
the internal ROM. Program execution begins at OOOOH
from the ROM. An active High input disables the ROM and
external fetches occur from address OOOOH.

Z89COO
16·8rr DIGITAL SIGNAL PROCESSOR

/RDVE Data Ready (input). User-supplied Data Ready
signal for data to and from external data bus. This pin
stretches the lEI and ER/NJ lines and maintains data on the
address bus and data bus. The ready signal is sampled
from the rising edge of the clock with appropriate setup
and hold times. The normal write cycle will continue from
the next rising clock only if ready is active.
UI1-UIO Two Input Pins (input). General purpose input
pins. These input pins are directly tested by the conditional
branch instructions. These are asynchronous input signals
that have no special clock synchronization requirements.
U01-UOO Two Output Pins (output). General purpose
output pins. These pins reflect the inverted value of status
register bits S5 and S6. These bits may be used to output
data by writing to the status register.

ADDRESS SPACE
Program Memory. Programs of up to 4K words can be
masked into internal ROM. Four locations are dedicated to
the vector address for the three interrupts (OFFDH-OFFFH)
and the starting address following a Reset (OFFCH). Internal
ROM is mapped from OOOOH to OFFFH, and the highest
location for program is OFFBH. If the /ROMEN pin is held
High, the internal ROM is inactive and the processor
executes external fetches from OOOOH to FFFFH. In this
case, locations FFFC-FFFF are used for vector addresses.
Internal Data RAM. The Z89COO has an internal 512 x
16-bit word data RAM organized as two banks of 256 x
16-bit words each, referred to as RAMO and RAM1. Each
data RAM bank is addressed by three pointers, referred to
asPn:O(n = 0-2) for RAMO and Pn:1 (n = 0-2)forRAM1. The
RAM addresses for RAMO and RAM1 are arranged from
0-255 and 256-511, respectively. The address pointers,
which may be written to or read from, are 8-bit registers

connected to the lower byte of the internal 16-bit D-Bus
and are used to perform no overhead looping. Three
addressing modes are available to access the Data RAM:
register indirect, direct addressing, and short form direct.
These modes are discussed in detail later. The contents of
the RAM can be read or written in one machine cycle per
word without disturbing any internal registers or status
other than the RAM address pointer used for each RAM.
The contents of each RAM can be loaded simultaneously
into the X and Y inputs of the multiplier.

Registers. The Z89COO has 12 internal registers and up to
an additional eight external registers. The external registers
are user definable for peripherals such as AID or D/A or to
DMA or other addressing peripherals. External registers
are accessed in one machine cycle the same as internal
registers.

2-5
---- --------

-- - - - - - - - - -

PRELIMINARY

Z89COO

1&-B1T DIGITAL SIGNAL PRocEssoR

FUNCTIONAL DESCRIPTION
General. The ZB9COO is a high-performance Digital Signal
Processor with a modified Harvard-type architecture with
separate program and data memory. The design has been
optimized for processing power and minimizing silidon
space.
Instruction Timing. Many instructions are executed in one
machine cycle. Long immediate instructions and Jump or
Call instructions are executed in two machine cycles.
When the program memory is referenced in internal RAM
indirect mode, it takes three machine cycles. In addition,
one more machine cycle is required if the PC is selected as
the destination of a data transfer instruction. This only
happens in the case of a register indirect branch instruction.
An Acc + P => Acc; a(i) • bO) ~ P calculation and
modification of the RAM pointers, is done in one machine
cycle. Both operands, a(i) and bO), can be located in two
independent RAM (0 and 1) addresses.

Multiply/Accumulate. The multiplier can perform a 16-bit
x 16-bit multiply or multiply accumulate in one machine
cycle using the Accumulator and/or both the X and Y
inputs. The multiplier produces a 32-bit result, however,
only the 24 most significant bits are saved for the next
instruction or accumulation. The multiplier provides a flow
through operation whenever the X or Y register is updated,
an automatic multiply operation is performed and the P
register is updated. For operations on very small numbers
where the least significant bits are important, the data
should first be scaled by eight bits (or the multiplier and
multiplicand by four bits each) to avoid truncation errors.
Note that all inputs to the multiplier should be fractional
two's complement 16-bit binary numbers. This puts them
in the range [-1 to 0.9999695], and the result is in 24-bits
so that the range is [-1 to 0.9999999]. In addition, if BOOOH
is loaded into both X and Y registers, the resulting
multiplication is considered an illegal operation as an
overflow would result. Positive one cannot be represented
in fractional notation, and the multiplier will actually yield
the result 8000H x BOOOH =8000H (-1 x -1 =-1).

2-6

ALU. The 24-bit ALU has two input ports, one of which is
connected to the output of the 24-bit Accumulator. The
other input is connected to the 24-bit P-Bus, the upper
16 bits of which are connected to the 16-bit D-Bus. A shifter
between the P-Bus and the ALU input port can shift the
data by three bits right, one bit right, one bit left or no shift.
Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The CALL instruction pushes PC+2 onto the stack. The
RET instruction pops the contents of the stack to the PC.
User Inputs. The ZB9COO has two inputs, UIO and U11,
which may be used by jump and call instructions. The jump
or call tests one of these pins and if appropriate, jumps to
a new location. Otherwise, the instruction behaves like a
NOP. These inputs are also connected to the status register
bits S10 and S11 which may be read by the appropriate
instruction (Figure 3).
User Outputs. The status register bits S5 and S6 connect
through an inverter to UOO and U01 pins and may be
written to by the appropriate instruction.
Interrupts. The ZB9COO has three positive edge triggered
interrupt inputs. An interrupt is acknowledged at the end of
any instruction execution. It takes two machine cycles to
enter an interrupt instruction sequence. The PC is pushed
onto the stack. A RET instruction transfers the contents
of the stack to the PC and decrements the stack pointer
by one word. The priority of the interrupts is 0 = highest,
2 = lowest.
Registers. The ZB9COO has 12 physical internal registers
and up to eight user-defined external registers. The EA2EAO determines the address of the external registers. The
/EI, /RDYE, and ER//W signals are used to read or write
from the external registers.

PRELIMINARY

Z89COO
l6-BIT DIGITAL SIGNAL PROCESSOR

REGISTERS
There are 12 internal registers which are defined below:
Register

P

Register Definition

X
Y
A

Output of Multiplier, 24-bit, Read Only
X Multiplier Input, 16-bit
Y Multiplier Input, 16-bit
Accumulator, 24-bit

SR
Pn:b
PC

Status Register, 16-bit
Six Ram Address Pointers, 8-bit Each
Program Counter, 16-bit

Pn:b are the pointer registers for accessing data RAM.
(n = 0,1,2 refer to the pointer number) (b = 0,1 refers to
RAM bank 0 or 1). They can be directly read from or written
to, and can point to locations in data RAM or indirectly to
Program Memory.

=

EXT(n) are external registers (n 0 to 7). There are eight
16-bit registers here for accessing External data,
peripherals, or memory. Note that the actual register RAM
does not exist on the chip, but would exist as part of the
external device such as an AOC result latch.
BUS is a read-only register which, when accessed, returns
the contents of the O-Bus.

The following are virtual registers as physical RAM does
not exist on the chip.
Register

EXTn
BUS
On:b

Register Definition

External registers, 16-bit
O-Bus
Eight Oata Pointers

P holds the result of multiplications and is read only.

X and Yare two 16-bit input registers for the multiplier.
These registers can be utilized as temporary registers
when the multiplier is not being used. The contents of the
P register will change if X or Y is changed.

Dn:b refer to possible locations in RAM that can be used
as a pointer to locations in program memory. The
programmer decides which location to choose from two
bits in the status register and two bits in the operand. Thus,
only the lower 16 possible locations in RAM can be
specified. At anyone time there are eight usable pointers,
four per bank, and the four pointers are in consecutive
locations in RAM. For example, if S3/84 = 01 in the status
register, then 00:0/01 :0/02:0/03:0 refer to locations
4/5/6/7 in RAM bank O. Note that when the data pointers are
being written to, a number is actually being loaded to Oata
RAM, so they can be used as a limited method for writing
to RAM.

A is a 24-bit Accumulator. The output of the ALU is sent to
this register. When 16-bit data is transferred into this
register, it goes into the 16 MSB's and the least significant
eight bits are set to zero. Only the upper 16 bits are
transferred to the destination register when the Accumulator
is selected as a source register in transfer instructions.

2-7

~2iUJG

Z89COO

PRELIMINARY

16·BIT DIGITAL SIGNAL PROCESSOR

REGISTERS (Continued)
RPL

Ram Pointer
000
001
010
011
100
101
110
111

Loop Size
256
2
4
8
16
32
64
128

'Short Form Direct' bitS}
Read
and
Write

User Output 0-1
Interrupt Enable
Overflow protection

MPY output shifted right
by 3 bit with sign extension
User Input 0-1
Carry
Read Only
Zero
Overflow
Negative

Figure 3. Status Register

SR is the status register (Figure 3) which contains the ALU
status and certain control bits as shown in the following
table.
Status
Register Bit

Function

S15(N)
S14 (OV)
S13 (Z)
S12 (L)
Sll (UI1)
S10 (UIO)

ALU Negative
ALU Overflow
ALU Zero
Carry
User Input 1
User InputO

S9 (SH3)
S8(OP)
S7 (IE)
S6 (U01)
S5 (UOO)
S4-3
S2-0 (RPL)

MPY Output Shifted Right by Three Bits
Overflow Protection
Interrupt Enable
User Output 1
User Output 0
"Short Form Direct" Bits
RAM Pointer Loop Size

2-8

RPL Description
S2

S1

SO

Loop Size

0
0
0
0

0
0
1
1

0
1
0
1

256
2
4
8

0
0
1
1

0
1
0
1

16
32
64
128

The status register may always be read in its entirety.
S15-S10 are set/reset by the hardware and can only be
read by software. S9-S0 can be written by software.

Z89COO
l6-BIT DIGITAL SIGNAL PROCESSOR

PRELIMINARY
S15-S12 are set/reset by the ALU after an operation.
S11-S10 are set/reset by the user inputs. S6-S0 are control
bits described elsewhere. S7 enables interrupts. S8, if 0
(reset), allows the hardware to overflow. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiply instruction
is used, the shifter shifts the result three bits right with sign
extension.

PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.

RAM ADDRESSING
The address of the RAM is specified in one of three ways (Figure 4):

RAMl

RAMO

q

RAM Pointers

PO:O
Pl:0
P2:0

%FF

37

I

I==~=:

%FF

----

OP1:0 ...........=-_
%37 1-..",;;%0;;;;32;;;,,;,,1_

PO:l

256 x 16-Bn

256 X 16-BII

I

RAM Poinlers

t-

r-

Pl:l
P2:1

%0321

%04

--

%00 ....._ __

84/83=01

%00
'"--

Data Pointers

Imemal ROM
%1000

00:0

---4Kx

01:0
02:0

16-Bil

03:0

---

@OP1:0

%0321

%0000

%1234

--

I+-

m

00:1
01:1
02:1
03:1

The following Instructions load
% 1234 into lhe Accumulator.

000:1

--

LDA,OOP1:0
LDA,ODO:l

Figure 4. RAM, ROM, and Pointer Architecture

1. Register Indirect
Pn:b n = 0-2, b = 0-1
The most commonly used method is a register indirect
addressing method, where the RAM address is
specified by one of the three RAM address pOinters (n)
for each bank (b). Each source/destination field in
Figures 5 and 8 may be used by an indirect instruction
to specify a register pointer and its modification after
execution of the instruction.

b

I osl

n1
03

T

I 02 1

I

01

nO

II
DO

~

RAM Pointer Register
Operation
RAM Bank

Figure 5. Indirect Register

2-9

Z89COO

PRELIMINARY

16·Brr DIGITAL SIG'NAL PROCESSOR

RAM ADDRESSING (Continued)
The register pointer is specified by the first and second bits
in the source/destination field and the modification is
specified by the third and fourth bits according to the
following table:

D3·DO

Meaning

OOxx
01xx
10xx
11xx

NOP
+1
-1/LOOP
+1/LOOP

No Operation
Simple Increment
Decrement Modulo the Loop Count
Increment Modulo the Loop Count

xxOO
xx01
xx10
xx11

PO:O or PO: 1
P1:0 or P1:1
P2:0 or P2:1

See
See
See
See

Note a.
Note a.
Note a.
Short Form Direct

Note:
a. If bit 8 is zero, PO:O to P2:0 are selected; if bit 8 is one, PO:1 to P2: 1
are selected.

When Loop mode is selected, the pointer to which the loop
is referring will cycle up or down, depending on whether a
-LOOP or +LOOP is specified. The size of the loop is
obtained from the least significant three bits of the Status
Register. The increment or decrement of the register is
accomplished modulo the loop size. As an example, if the
loop size is specified as 32 by entering the value 101 into
bits 2-0 of the Status Register (S2-S0) and an increment
+LOOP is specified in the address field of the instruction,
i.e., the RPi field is 11xx, then the register specified by RPi
will increment, but only the least significant five bits will be
affected. This means the actual value of the pointer will
cycle round in a length 32 loop, and the lowest or highest
value of the loop, depending on whether the loop is up or
down, is set by the three most significant bits. This allows
repeated access to a set of data in RAM without software
intervention. To clarify, if the pointer value is 10101001 and
if the LOOP = 32, the pointer increments up to 10111111,
then drops down to 10100000 and starts again. The upper
three bits remaining unchanged. Note that the original
value of the pointer is not retained.

2. Direct Register
The second method is a direct addressing method.
The address of the RAM is directly specified by
the address field of the instruction. Because this
addressing method consumes nine bits (0-511) of the
instruction field, some instructions cannot use this
mode (Figure 6).
Figures 8 to 13 show the different register instruction
formats along with the two tables below Figure 8.
b

n3

n2

T

n1

nO

' - - - - - RAM Address
RAM Bank

Figure 7. Short Form Direct Address
3. Short Form Direct
Dn:b n = 0-3, b = 0-1
The last method is called Short Form DirectAddressing,
where one out of 32 addresses in internal RAM can be
specified. The 32 addresses are the 1610wer addresses
in RAM Bank 0 and the 16 lower addresses in RAM
Bank 1. Bit 8 of the instruction field determines RAM
Bank 0 or 1. The 16 addresses are determined by a
4-bit code comprised of bits S3 and S4 of the status
register and the third and fourth bits of the Source/
Destination field. Because this mode can specify a
direct address in a shor~ form, all of the instructions
using the register indirect mode can use this mode
(Figure 7). This method can access only the lower 16
addresses in the both RAM banks and as such has
limited use. The main purpose is to specify a data
register, located in the RAM bank, which can then be
used to point to a program memory location. This
facilitates down-loading look-up tables, etc. from
program memory to RAM.

RAM Address
Opcode

Figure 6. Direct Internal RAM Address Format

2-10

Z89COO

PRELIMINARY

16-Brr DIGITAL SIGNAL PROCESSOR

INSTRUCTION FORMAT

T

'-----

Source field
Destination field
L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ RAM Bank selection
L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Opcode
L -_ _ _ _ _ _ _ _ _

Note:
Source/Destination fields can specify either register or
RAM addresses in RAM pointer indirect mode.

Figure 8. General Instruction Format

A. Registers
Source/Destination

B. Register Pointers Field
Register

Source/Destination

0000
0001
0010
0011

BUS**
X
Y
A

OOxx
01xx
10xx
l1xx

0100
0101
0110
0111

SR
STACK
PC
P**

xxOO
xxOl
xxl0
xxll

1000
1001
1010
1011

EXTO
EXTl
EXT2
EXT3

1100
1101
1110
1111

EXT4
EXT5
EXT6
EXT?

Meaning
NOP
+1
-l/LOOP
+l/LOOP
PO:O or PO: 1*
Pl:0 or Pl:l*
P2:0 or P2:1*
Short Form Direct
Mode

Notes:
• If RAM Bank bit is 0, then Pn:O are selected.
If RAM Bank bit is 1, then Pn:l are selected.
•• Read only.

Short Immediate Data
Reg. Pointer

000
001
a10
011
100
101
110
111

PO:O
Pl:0
P2:0
NA
PO:l
P1:1
P2:1
NA

Opcode

00011

Figure 9. Short Immediate Data Load Format

2-11

Z89COO

PRELIMINARY

l6-BIT DIGITAL SIGNAL PROCESSOR

INSTRUCTION FORMAT (Continued)
1st Word

General Instruction Format

2nd Word

Immediate Oata

Figure 10. Immediate Data Load Format

101510141013 0121011 1010 1 09 108 1 07 106
-r-

05 104 1 03 102 1 01 100

I
ACC Modification Codes
o0 0 0 ROR Rotate right
o0 0 1 ROL Rotate left
o0 1 0 SHR Shift right
o0 1 1 SHL Shift left
01 00 INC Increment(LSB)
o1 0 1 OEC Oecrement (LSB)
o1 1 0 NEG Negate
o1 11 ABS Absolute
Condition Codes
0000 TRUE
0001 ••••
0010U01=0
0011 U01=0
0100 C=O
0101 Z=O
0110 OV=O
0111 N=O
1 xxx····
0000 TRUE
0001 ••••
0010 UOO=l
0011 U01=1
0100 C=l
0101 Z=1
0110 OV=l
0111 N=l
1 xxx .•.•

o= Negative Condition
1 = Positive Condition

Opcode
1001000

Figure 11. Accumulator Modification Format

2-12

Z89COO

PRELIMINARY

16-Brr DIGITAL SIGNAL PROCESSOR

1st Word

xxxx
Condition Codes
0000 TRUE
00 01 ---0010 UOO=O
00 11 U01=0
0100 C=O
0101 Z=O
0110 OV=O
0111 N=O

lxxx ----

0000 TRUE
0001 ---00 10 UOO=l
00 11 U01=1
0100 C=l
0101 Z=1
01100V=1
0111 N=l

1xxx ----

Condition
0= Negative
Condition
1 = Positive Condition
Opcode
0100110
Branch
0100100 Call
2nd Word

Branch Address

Figure 12. Branching Format

....._ - - xxl0
xx 11
xlxO
xlx1
lxxO
lxx1

Reset Cflag
Set Cflag
Reset IE Flag
(Interrupt enable)
Set IE Flag
Reset OP Flag
(Overflow protection)
Set OP Flag

~------------------xxxx

Opcode
1001010 Mod

Figure 13. Flag Modification Format

2-13

PRELIMINARY

Z89COO
16·Brr DIGITAL SIGNAL PROCESSOR

ADDRESSING MODES
This section discusses the syntax of the addressing modes
supported by the DSP assembler. The symbolic name is

used in the discussion of instruction syntax in the instruction
descriptions.

Symbolic Name

Syntax

Description



Pn:b

Pointer Register


(Points to RAM)

Dn:b

Data Register



X,Y,PC,SR,P
EXTn,A,BUS

Hardware Registers


(Points to Program Memory)

@A

Accumulator Memory Indirect





Direct Address Expression



#

Long (16-bit) Immediate Value



#

Short (8-bit) Immediate Value


(Points to RAM)

@Pn:b
@Pn:b+
@Pn:b-LOOP
@Pn:b+LOOP

Pointer Register Indirect
Pointer Register Indirect with Increment
Pointer Register Indirect with Loop Decrement
Pointer register Indirect with Loop Increment


(Points to Program Memory)

@@Pn:b
@Dn:b
@@Pn:b-LOOP
@@Pn:b+LOOP
@@Pn:b+

Pointer Register Memory Indirect
Data Register Memory Indirect
Pointer Register Memory Indirect with Loop Decrement
Pointer Register Memory Indirect with Loop Increment
POinter Register Memory Indirect with Increment

There are eight distinct addressing modes for transfer of
data (Figure 4 and the table above).

,  These two modes are used for simple
loads to and from registers within the chip such as loading
to the Accumulator, or loading from a pointer register. The
names of the registers need only be specified in the
operand field. (Destinatiqn first then source)

 This mode is used for indirect accesses to the
data RAM. The address of the RAM location is stored in the

2-14

pointer. The "@" symbol indicates "indirect" and precedes
the pointer, so @P1 :1 tells the processor to read or write to
a location in RAM1, which is specified by the value in the
pointer.

 This mode is also used for accesses to the data
RAM but only the lower 16 addresses in either bank. The
4-bit address comes from the status register and the
operand field of the data pointer. Note that data registers
are typically used not for addressing RAM, but loading
data from program memory space.

Z89COO

PRELIMINARY
 This mode is used for indirect, indirect accesses
to the program memory. The address of the memory is
located in a RAM location, which is specified by the value
in a pointer. So @@Pl:l tells the processor to read (write
is not possible) from a location in memory, which is
specified by a value in RAM, and the location of the RAM
is in turn specified by the value in the pointer. Note that the
data pointer can also be used for a memory access in this
manner, but only one "@" precedes the pointer. In both
cases the memory address stored in RAM is incremented
by one each time the addressing mode is used to allow
easy transfer of sequential data from program memory.

l6·BIT DIGITAL SIGNAL PROCESSOR

 The direct mode allows read or write to data RAM
from the Accumulator by specifying the absolute address
of the RAM in the operand of the instruction. A number
between 0 and 255 indicates a location in RAMO, and a
number between 256 and 511 indicates a location in
RAM1.
 This indicates a long immediate load. A 16-bit
word can be copied directly from the operand into the
specified register or memory.
 This can only be used for immediate transfer of
8-bit data in the operand to the specified RAM pointer.

 Similarto the previous mode, the address for the
program memory read is stored in the Accumulator. @A in
the second operand field loads the number in memory
specified by the address in A.

CONDITION CODES
The following table defines the condition codes supported
by the DSP assembler. If the instruction description
refers to the  (condition code) symbol in one of its

addressing modes, the instruction will only execute if the
condition is true.

Name

Description

Name

Description

C
EQ
F
IE
MI
NC
NE
NIE
NOV
NUO

Carry
Equal (same as Z)
False
Interrupts Enabled
Minus
No Carry
Not Equal (same as NZ)
Not Interrupts Enabled
Not Overflow
Not User Zero

NUl
NZ
OV
PL
UO
Ul
UGE

Not User One
Not zero
Overflow
Plus (Positive)
User Zero
User One
Unsigned Greater Than or
Equal (Same as NC)
Unsigned Less Than (Same as C)
Zero

ULT
Z

2·15

~2iu::a:;

Z89COO

PRELIMINARY

16-Brr DIGITAL SIGNAL PROCESSOR

INSTRUCTION DESCRIPTIONS
Inst.

Description

Synopsis

Operands

ABS

Absolute Value

ABS[,)

,A
A

ADD

Addition

ADD,

A,
A,
A,
A,
A,
A,
A,

1
1
2
1
1
1
1

1
1
2
3
1
1
1

ADD A,PO:O
ADD A,DO:O
ADD A,#% 1234
ADD A,@@PO:O
ADDA,%F2
ADD A,@P1:1
ADD A,X

AND

Bitwise AND

AND,

A,
A,
A,
A,
A,
A,
A,

1
1
2
1
1
1
1

1
1
2
3
1
1
1

AND A,P2:0
ANDA,DO:1
AND A,#% 1234
AND A,@@P1:0
AND A,%2C
AND A,@P1:2+LOOP
AND A,EXT3

CALL

Subroutine call

CALL [,)
, 2 2 2 2 CALL Z,sub2 CALL sub1 CCF Clear carry flag CCF None CCF ClEF Clear Carry Flag ClEF None ClEF COPF Clear OP flag COPF None COPF CP Comparison CP, A, A, A, A, A, A, A DEC Decrement DEC [,] A, A DEC NZ,A DEC A INC Increment INC [,) ,A A INC PL,A INCA JP Jump JP [,]
, 2-16 Words Cycles Examples ABS NC,A ABSA 1 1 1 1 1 1 2 2 2 1 1 3 1 1 1 2 2 2 CP A,PO:O CP A,D3:1 CP A,@@PO:1 CP A,%FF CP A,@P2:1+ CP A,STACK CP A,#%FFCF JP NIE,Label JP Label ~2iUlG Z89COO PRE L I MIN A R Y Inst. Description Synopsis Operands LD Load destination with source LD, A, A, A, A, A, A, ,A , , , , , , , , , , , , 16·Brr DIGITAL SIGNAL PROCESSOR Words Cycles Examples 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 LDA,X LD A,DO:O LD A,PO:1 LDA,@P1:1 LDA,@DO:O LD A,124 LD 124,A LD DO:O,EXT7 LD P1:1 ,#%FA LD P1:1 ,EXT1 LD@P1:1,#1234 LD@P1:1+,X LD Y,PO:O LD SR,DO:O LD PC,#%1234 LDX,@A LD Y,@DO:O LD A,@PO:D-LOOP LD X,EXT6 Nota: If X or Yregister is the destination, an automatic multiply operation is performed. Nota: The Pregister is Read Only and cannot be destination. Nota: LD EXTN' EXTN is not allowed. Nota: LD A, @A is not allowed. MLD Multiply MLD[,] , ,, , ,, MLD A,@PO:D+LOOP MLD A,@P1:0,OFF MLD @P1:1,@P2:0 MLD @PO:1,@P1:0,ON Note: If src1 is it must be a bank 1 register. Src2's for src1 cannot be X. Note: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. MPYA Multiply and add MPYA [,] , ,, , ,, MPYAA,@PO:O MPYA A,@P1:0,OFF MPYA @P1:1,@P2:0 MPYA@PO:1,@P1:0,ON Note: If src1 is it must be abank 1 register. Src2's must be a bank 0 register. Note: for src1 cannot be Xor A. Note: For the operands , the defaults to OFF. For the operands , the defaults to ON. 2-17 Z89COO PRE L I MINARY *2il.ClG 16·Brr DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS (Continued) Insl. Description MPYS Multiply and subtract Synopsis Operands Words Cycles Examples MPYS A,@PO:O MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS@PO:1,@P1:0,ON MPYS,L] , ,, , ,, Nole: If src1 is it must be a bank 1 register. Src2's must be a bank 0 register. Nole: for src1 cannot be Xor A. Nole: Forthe operands , the defaults to OFF. Forthe operands , the defaults to ON. NEG Negate NEG ,A , A A NEG MI,A NEGA NOP No operation NOP None NOP OR Bitwise OR OR , A, A, A, A, A, A, A, POP Pop value from stack POP PUSH Push value onto stack PUSH RET Return from subroutine RET None RL Rotate Left RL ,A ,A A RL NZ,A RLA RR Rotate Right RR ,A ,A A RR G,A RR A 2-18 1 1 2 1 1 1 1 1 1 2 3 1 1 1 OR A,PO:1 ORA,OO:l ORA,#%2G21 OR A,@@P2:1+ ORA, %2G OR A,@P1:D-LOOP ORA,EXT6 POP Po:o POP 00:1 POP@PO:O POP A 1 1 1 1 2 1 1 1 1 1 1 2 3 3 PUSH PO:O PUSH 00:1 PUSH@PO:O PUSH BUS PUSH #12345 PUSH@A PUSH@@PO:O 2 RET ~2iu:a; Z89COO PRE L IMINAR y 16-Brr DIGITAL SIGNAL PROCESSOR Insl. Description Synopsis Operands SCF Set Cflag SCF None SCF SIEF Set IE flag SIEF None SIEF SLL Shift left logical SLL [.!A A SLL NZ,A SLL A SOPF Set OP flag SOPF None SOPF SRA Shift right arithmetic SRA,A ,A A SRANZ,A SRAA SUB Subtract SUB, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 SUB A,P1:1 SUBA,DO:1 SUB A,#%2C2C SUBA,@DO:1 SUB A,%15 SUB A,@P2:0-LOOP SUBA,STACK XOR Bitwise exclusive OR XOR , A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 XORA,P2:0 XORA,DO:1 XOR A,'13933 XOR A,OOP2:1+ XOR A,%2F XORA,@P2:0 XORA,BUS Bank Switch Enumerations. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether a bank switch is set on or off. To more clearly represent this, two keywords are used (ON and OFF) Words Cycles Examples which state the direction olthe switch. These keywords are referred to in the instruction descriptions through the symbol. 2-19 ~~-~--~----~----- ~----- PRELIMINARY Z89COO 16-Brr DIGITAL SIGNAL PROCESSOR ABSOLUTE MAXIMUM RATINGS Symbol Vcc TSTG TA Description Min Max Supply Voltage(*) Storage Temp. Oper. Ambient Temp. -0.5 -65° 7.0 +150° t Units V C C Notes: • Voltages on all pins with respect to ground. t Sea Ordering Information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability . STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load Diagram, Figure 14). 2.1 KO From Output o - - -......----1>---ICi----+ Under Test Figure 14. Test Load Diagram DC ELECTRICAL CHARACTERISTICS (Vcc = 5V ± 5%, TA = aoe to +7aoe unless otherwise specified) Symbol Parameter Condition Icc Supply Current Icc, Halt Mode Vee = 5.25V fclock = 10 MHz Vee = 5.25V fclock = 0 MHz (stopped) VIH VIL IlL Input High Level Input Low Level Input Leakage VOH VOL Output High Voltage Output Low Voltage IFL Output Floating Leakage Current 2-20 Min. Max. Units 60 mA 5 mA 0.9Vcc IOH= -100 llA 10L = 0.5mA V V 0.1 Vee 1 llA 0.5 V V 5 llA Vee- 0.2 ------------- - ft'2iu::a; Z89COO PRELIMINARY i6·BIT DIGITAL SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS (Vee =5V ± 5%, TA = to +70 unless otherwise specified) ooe No. oe Symbol Parameter 1 2 3 4 5 TCY PWW Tr Tf TEAD Clock Cycle Time Clock Pulse Width Clock Rise Time Clock Fall Time EA,ER/NJ Delay from CK 6 7 8 9 10 TXVD TXWH TXRS TXRH TIEDR 11 12 13 14 15 16 17 18 19 20 Min. Max. Units 100 45 2 2 9 1000 ns ns ns ns ns EXT Data Output Valid from ClK EXT Data Output Hold from ClK EXT Data Input Setup Time EXT Data Input Hold from ClK lEI Delay Time from Rising ClK Edge 5 6 15 5 3 27 22 TIEDF TINS TINl TPAD TPDS lEI Delay Time from Falling ClK Edge Interrupt Setup Time Interrupt Hold Time PA Delay from ClK PD Input Setup Time 0 5 15 5 20 23 TPDH TCTlS TCTlH RDYS RDYH PD Input Hold Time Halt Setup Time Halt Hold Time Ready Setup Time Ready Hold Time 20 5 20 10 7 4 4 33 15 15 22 28 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-21 PRELIMINARY AC TIMING DIAGRAM I+------{ )-----'*"10-. CD eLK ® tEl ERlIW EXTI5-EXTO EA2-EAO Output valid Data Out valid Address Out tRDYE Figure 15. Write To External Device Timing 2-22 Z89COO 16·BIT DIGITAL SIGNAL PROCESSOR Z89COO PRELIMINARY i + - - - - - - - { )-----i+-~ 16-BIT DIGITAL SIGNAL PROCESSOR CD elK @ lEI ERIN! EXT15-EXTO EA2-EAO Valid Data In Valid Address Out IROVE Figure 16_ Read From External Device Timing 2-23 PRELIMINARY AC TIMING DIAGRAM elK lEI ERlfW EXT15-EXTO EA2-EAO EXT Bus: Output valid Data Out valid Address Out /ROVE Figure 17. Write To External.Devlce Timing (/RDVE used to hold data one clock cycle)* Note: ·IRDYE Is checked during rising edge of clock. 2·24 Z89COO 16-BIr DIGITAL SIGNAL PRocESSOR PRELIMINARY Z89COO 16·Brr DIGITAL SIGNAL PROCESSOR elK lEI ERlIW EXT15-EXTO EA2-EAO IROVE Figure 18. Read From External Device Timing (/ROVE used to hold data one clock cycle)' Note: '/ROVE Is checked during rising edge of clock. 2-25 Z89COO PRELIMINARY 16-BIT DIGITAL SIGNAL PRoCESSOR AC TIMING DIAGRAM ....--{i15s)--~ IJto---~ ClK PAl5-PAO P01S·POO HALT Figure 19. Memory Port Timing 0' _ _......1 1 ...._ _----Ir""1-----.1..._ __ I· CD I-- ~ en lti &l ,... C\I ~ I:; 0... 0... 0... 0... 0... e 0 0 z > Z < 0 (!l VREF+ • ANIN VREF- ANGND lAS IRESET R/W PWM P10 P47 P11 P46 P53 P45 P44 P43 Z89120 INC INC C;; 0... ~ ~ ~ 0 0 > It) (') 0... ~ o~ a:: a::en fuo... a:: 0 0 (') [;; ~ 0... 0... a:: ~ ~ ~ C\I Figure 2. Z89120 68-Pin PLCC Pin Assignments 4-4 *2iUJG Z891201Z89920 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR Table 1. Z89120 68-Pin PLCC Pin Identification Pin# Symbol Function Direction Pin# Symbol Function DSPO P36 P13 P37 DSP User Output Port 3, bit 7 Port 1, bit 3 Port 3, bit 7 ° Direction 1 2 3 4 IR/Rl VDD P04 P50 ROM/ROMless Power Supply Port 0, bit 4 Port 5, bit Control Input Input/Output Input/Output 35 36 37 38 5 6 7 8 P57 P03 P02 POl Port 5, Port 0, Port 0, Port 0, Input/Output Input/Output Input/Output Input/Output 39 40 41 42 P40 P12 P06 P41 Port 4, Port 1, Port 0, Port 4, 9 10 11 12 POO XTAl2 XTAL1 P22 Input/Output Port 0, bit Crystal Oscillator Clock Output Crystal Oscillator Clock Input Port 2, bit 2 Input/Output 43 44 45 46 P42 NC P43 P44 Port 4, bit 2 Not Connected Port 4, bit 3 Port 4, bit 4 Input/Output 13 14 15 16 P56 P23 P55 P54 Port 5, Port 2, Port 5, Port 5, bit 6 bit 3 bit 5 bit 4 Input/Output Input/Output Input/Output Input/Output 47 48 49 50 P45 P53 P46 Pll Port 4, Port 5, Port 4, Port 1, Input/Output Input/Output Input/Output Input/Output 17 18 19 20 GND P17 P05 P24 Ground Port 1, bit 7 Port 0, bit 5 Port 2, bit 4 Input/Output Input/Output Input/Output 51 52 53 54 P47 Pl0 PWM Port 4, bit 7 Port 1, bit 0 Pulse Width Modulator Read/Write Input/Output Input/Output Output Output 21 22 23 24 P16 P25 P15 P26 Port Port Port Port Input/Output Input/Output Input/Output Input/Output 55 56 57 58 Input Output ANGND VREF• Reset Address Strobe Analog Ground Analog Voltage Ref. 25 26 27 28 29 P27 NC P31 P32 P33 Port 2, bit 7 Not Connected Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Input/Output 59 60 61 62 63 AN'N VREF+ ANVDD GND P07 Analog Input Analog Voltage Ref. Analog Power Supply Ground Port 0, bit 7 Input Input 30 31 32 33 34 P34 VDO P35 P14 DSP1 Port 3, bit 4 Power Supply Port 3, bit 5 Port 1, bit 4 DSP User Output 1 64 65 66 67 68 P20 P21 P52 P51 Port 2, bit 0 Port 2, bit 1 Port 5, bit 2 Port 5, bit 1 Data Strobe Input/Output Input/Output Input/Output Input/Output Output ° 1, 2, 1, 2, bit 7 bit 3 bit 2 bit 1 ° bit 6 bit 5 bit 5 bit 6 Input Input Input Output Output Input/Output Output R//W IRESET lAS IDS bit 0 bit 2 bit 6 bit 1 bit 5 bit 3 bit 6 bit 1 Output Output Input/Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output 4-5 --------- ~2ilLlG Z891201Z89920 16·BIT MIXED SIGNAL PROCESSOR PRELIMINARY PIN DESCRIPTION (Continued) 0 0 0 en u:; f?l C\i (\/ t; 0z > 8 0 ~ 8 C!i z n. n. n. n. n. n. n. > z Q n. n. n. n. n. (!l < "LO 0 LO XTAL2 XTAL1 P22 P56 P23 P55 P54 GND P17 P05 P24 P16 P25 P15 P26 P27 SCLK 0 0 () VREF+ ANIN VREF· ANGND • lAS IRESET RJW PWM P10 P47 P11 P46 P53 P45 P44 P43 ISYNC Z89920 C;; (\/ C') ~ ;;I; 0 n. n. n. n. 0 LO C') > n. "'a::" ena:: 0 0 CD n. en n. 0 C') C') a:: "C') ~ n. n. (\/ a:: ~ ~ ~ n. n. n. Figure 3. Z89920 68-Pin PLCC Pin Assignments 4·6 -----------_. - ~2.il.JJG Z891201Z89920 PRELIMINARY 16·BIT MIXED SIGNAL PROCESSOR Table 2. Z89920 S8-Pin PLCC Pin Identification Pin# Symbol Function Direction Pin# Symbol Function DSPO P36 P13 P37 DSP User Output 0 Port 3, bit 7 Port 1, bit 3 Port 3, bit 7 Output Output Input/Output Output Input/Output Input/Output Input/Output Input/Output Direction 1 2 3 4 NC VDD P04 P50 Not Connected Power Supply Port 0, bit 4 Port 5, bit 0 Input/Output Input/Output 35 36 37 38 5 6 7 8 P57 P03 P02 POi Port 5, bit 7 Port 0, -bit 3 Port 0, bit 2 Port 0, bit 1 Input/Output Input/Output Input/Output Input/Output 39 40 41 42 P40 P12 P06 P41 Port 4, Port 1, Port 0, Port 4, 9 10 11 12 POO XTAL2 XTAL1 P22 Port 0, bit 0 Input/Output Crystal Oscillator Clock Output Crystal Oscillator Clock Input Port 2, bit 2 Input/Output 43 44 45 46 P42 ISYNC P43 P44 Port 4, bit 2 Synchronize Pin Port 4, bit 3 Port 4, bit 4 Input/Output Output Input/Output Input/Output 13 14 15 16 P56 P23 P55 P54 Port 5, Port 2, Port 5, Port 5, bit 6 bit 3 bit 5 bit 4 Input/Output Input/Output Input/Output Input/Output 47 48 49 50 P45 P53 P46 P11 Port 4, Port 5, Port 4, Port 1, Input/Output Input/Output Input/Output Input/Output 17 18 19 20 GND P17 P05 P24 Ground Port 1, bit 7 Port 0, bit 5 Port 2, bit 4 Input/Output Input/Output Input/Output 51 52 53 54 P47 P10 PWM Port 4, bit 7 Port 1, bit 0 Pulse Width Modulator Read/Write Input/Output Input/Output Output Output 21 22 23 24 P16 P25 P15 P26 Port 1, Port 2, Port 1, Port 2, Input/Output Input/Output Input/Output Input/Output 55 56 57 58 Input Output ANGND VREFo Reset Address Strobe Analog Ground Analog Voltage Ref. 25 26 27 28 29 P27 SCLK P31 P32 P33 Port 2, Obit? System Clock Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Input/Output Output Input Input Input 59 60 61 62 63 AN'N VREF+ ANVDD GND PO? Analog Input Analog Voltage Refo Analog Power Supply Ground Port 0, bit 7 Input Input 30 31 32 33 34 P34 VDD P35 Pi4 DSPi Port 3, bit 4 Power Supply Port 3, bit 5 Port 1, bit 4 DSP User Output 1 Output 64 65 66 67 68 P20 P21 P52 P5i Port 2, bit 0 Port 2, bit 1 Port 5, bit 2 Port 5, bit 1 Data Strobe Input/Output Input/Output Input/Output Input/Output Output bit 6 bit 5 bit 5 bit 6 Output Input/Output Output R//W IRESET lAS IDS bit 0 bit 2 bit 6 bit 1 bit 5 bit 3 bit 6 bit 1 Input Input/Output 4-7 PRELIMINARY Z8912OJZ89920 16-BIT r.mo SIGNAL PROCESSOR PIN FUNCTIONS !RESET (input, active Low). Initializes the MCU. Reset is accomplished either through Power-On Reset (POR), WDT reset, SMR or external reset. During POR and WDT reset, the internally generated reset is driving the reset pin Low for the POR time. Any devices driving the reset line must be open drain to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. A /RESET signal resets both the Z8 and the DSP. FortheZ8: After the POR time,IRESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z8 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. Program execution begins at location OOOCH (Hexadecimal), 5-10 TpC cycles after the IRESET is released. For Power-On Reset, the typical reset time is 5 ms. The Z8 does not reset WDT, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. For the DSP: A low level on the IRESET pin generates an internal reset signal. The IRESET signal must be kept low for at least one clock cycle. The CPU will push the contents of the PC onto the stack and then fetch a new Program Counter (PC) value from program memory address OFFCH after the reset signal is released. IRIRL ROM/ROMless (input, active Low). This pin, when connected to VcC' disables the internal Z8 ROM only and forces the device to function as a Z89920 ROM less. (Note that when pulled Low to GND, the Z89120 functions normally as the ROM version). The DSP can not be configured as ROM less. This is available only on the Z89120. IDS Data Strobe (output, active Low). Data Strobe is activated once for each external memory transfer. For read operations, data must be available prior to the trailing edge of IDS. For write operations, the falling edge of IDS indicates that output data is valid. XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network or an external single-phase clock to the on-chip oscillator input. XTAL2 CrystaI2(time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, or LC network to the on-chip oscillator output. DSPO (output). DSPO is a general purpose output pin connected to bit 6 of the Analog Control Register (DSP EXT4). This bit has no special significance and may be used to output data by writing to bit 6 of the ACR. DSP1 (output). DSP1 is a general purpose output pin connected to bit 7 of the Analog Control Register (DSP EXT4). This bit has no special significance and may be used to output data by writing to bit 7 of the ACR. SCLK System Clock (output). SCLK outputs the internal system clock. This pin is only available on the Z89920. /SYNC Synchronize (output). This signal indicates the last clock cycle of the currently executing Z8 instruction. This pin is only available on theL:89920. PWM Pulse Width Modulator (output). The PWM is a 10-bit resolution D/A converter. This output is a digital signal with CMOS output levels. AN'N (input). Analog input for the AID converter. Signal range is AN GNO to AN voo ' RI/W Read/Write (output, write Low). The R//W signal defines the signal flow when the Z8 is reading or writing to external program or data memory. The Z8 is reading when this pin is High and writing when this pin is Low. ANVcc . Analog power supply for the AID and DIA converters. lAS Address Strobe (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port OIPort 1 for all external programs. Memory address transfers are valid at the trailing edge of lAS. Under program control, lAS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. VREF+ (input). Reference voltage (High) for the AID ANGND • Analog ground for the AID converter. converter. VREF_ (input). Reference voltage (Low) for the AID converter. vcc. Digital power supply for the Z89120/920. GND. Digital ground for the Z89120/920. 4-8 PRELIMINARY Port 0 (P07-POO). Port 0 is an 8-bit, bidirectional, CMOS compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and the output drivers are push-pull. Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control/DAVO and RDVO. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble. The Auto Latch on Port 0 puts valid CMOS levels on all CMOS inputs which are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Z891201Z89920 16-BIT MIXED SIGNAL PROCESSOR For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they are configured by writing to the Port 0 mode register. In ROM less mode, after a hardware reset, Port 0 is configured as address lines A 15-A8. and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode. (In ROM mode. Port 0 is defined as input after reset.) Port 0 is set in the high-impedance mode if selected as an address output state along with Port 1 and the control signals /AS, /DS, and R//W (Figure 4). .IL._....A. } PortO (VOorA1S-AB) ""--,, Handshake Controls IDAVO and RDYO (P32 and P35) OEN --.--1 ~I-------f~l)----a Out 1 . S _ 2.3V Hysteresis In 1 1 1L.. 1 Auto Latch R .. _ 500Kn _ _ _ _ _ _ _ _ _ _1 I Figure 4. Port 0 Configuration 4-9 Z891201Z89920 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS compatible port (Figure 5). It has multiplexed Address (A7AO) and Data (07-00) ports. These eight I/O lines are programmed as inputs or outputs, or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitttriggered and the output drivers are push-pull. Port 1 may be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and /DAV1 (Ready and Data Available). Memory locations greater than 24575 (in ROM mode) are referenced through Port 1. To interface extemal memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines. Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS and R/fW, allowing the Z89120/920 to share common resources in multiprocessor and DMA applications. Port 1 (1/0 or AD? - ADO) .... Handshake Controls IDAV2 and RDY1 (P33 and P34) OEN Out 1.5..... 2.3V HysteresiS In --------CE~---.--------------------_1--~ I ...I I R=SOOKO I - - - - - - - - - - - - ______ 1 Figure 5. Port 1 Configuration 4-10 Auto Latch Z89120JZ89920 PRELIMINARY Port 2 (P27·P20). Port 2 is an 8-bit, bidirectional, CMOS compatible I/O port. These eight I/O lines are independently configured under software control as an input or output. Port 2 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs may be globally programmed as either push-pull or open-drain. Port 2 may be placed under handshake control. configuration, Port 3 lines P31 and P36 are used handshake controls lines /DAV2 and RDY2. The shake signal assignment for Port 3 lines P31 and In this as the handP36 is 16·8rr MIXED SIGNAL PROCESSOR dictated by the direction (input or output) assigned to bit 7, Port 2 (Figure 6). Port 26 can be configured in DSP software to activate DSP INTO. The Auto Latch on Port 2 puts valid CMOS levels on all CMOS inputs which are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Port 2 (1/0) Handshake Controls IDAV2 and RDY2 (P31 and P36) OEN Out 1.~ In 2.3V Hysteresis ---------<~~--~~----------------------.-~ .., I I R=500Kn I Auto Latch I L ____________ .J Figure 6. Port 2 Configuration 4-11 Z89l201Z89920 PRELIMINARY l6·BIT MIXED SIGNAL PROCESSOR PIN FUNCTIONS (Continued) Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible port with three fixed inputs (P33-P31) and four fixed outputs (P37-P34). It is configured under software control for input! output, counter/timers, interrupt, and port handshakes. Pins P31, P32, and P33 are standard CMOS inputs; outputs are push-pull. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). Port3, pin 3 is a falling edge interrupt input. P31 and P32 are programmable as rising, falling or both edge-triggered interrupts (IRQ register bits 6 and 7). P33 is the comparator reference voltage input. Access to Counter/Timer1 is made through P31 (T'N) and P36 (Tour)' Handshake lines for Ports 0, 1, and 2 are available on P31 through P36. Port 3 also provides the following control functions: handshake for Ports 0, 1, and 2 (IDAV and ROY); three external interrupt request signals (IRQ3-IRQ1); timer input and output signals (T'N and Tour); Data Memory Select (10M); (Figure 7 and Table 3). Comparator Inputs. Port 3, Pins P31 and P32 each have a comparator front end. The comparator reference voltage, pin P33, is common to both comparators. In analog mode, the P31 and P32 are the positive inputs to the comparators and P33 is the reference voltage supplied to both comparators. In digital mode, pin P33 can be used as a P33 register input or IRQ1 source. Table 3. Port 3 Pin Assignments Pin VO CTC1 AN IN Int. POHS P31 P32 P33 IN IN IN Tin AN1 AN2 REF IRQ2 IRQO IRQ1 D/R P34 P35 P36 P37 OUT OUT OUT OUT Notes: HS = Handshake Signals D=DAV R=RDY 4-12 P1HS P2HS D/R D/R R/D /DM R/D Tout EXT R/D Z891201Z89920 PRELIMINARY 16·Brr MIXED SIGNAL PROCESSDR , ~ Z891201920 MCU ~ . > . . ) --'" Port 3 (1/0 or Control) --"" R247=P3M t = Analog 0= Digi1al IRQ2, Tin, P3t Data Latch P3t (ANt) I I I I I 1 P32(AN2) IRQO, P32 Data Latch I I I I v P33(REF) - -......... • IRQt, P33 Data Latch D From Stop Moda Recovery Source - - - - - -..... Figure 7. Port 3 Configuration 4-13 Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR PRELIMINARY PIN FUNCTIONS (Continued) Port 4 (P47·P40). Port 4 is an 8·bit, bidirectional, CMOS compatible I/O port (Figure 8). These eight I/O lines are configured under software control as an input or output, independently. Port 4 is always available for I/O operation. The input buffers are Schmitt·triggered. Bits programmed as outputs may be globally programmed as either pushpull or open-drain. - Port 4 is a bit programmable general purpose I/O port. The control and data registers for Port 4 are mapped into the expanded register file (Bank F) of the Z8. Auto Latch. The Auto Latch on Port 4 puts valid CMOS levels on all CMOS inputs which are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. .... , Port 4 ~ (I/O) Z89120/920 MCU ~ - ) OEN Out 1.5+--+ 2.3V Hysteresis In r------------ .... I I I I I R=500KO I .... _____________ .J Figure 8. Port 4 Configuration 4-14 Auto Latch Z891201Z89920 16-Brr MIxED SIGNAL PROCESSOR PRELIMINARY Port 5 (P57-P50). Port 5 is an a-bit, bidirectional, CMOS compatible 110 port (Figure 9). These eight 110 lines are configured under software control as an input or output, independently. Port 5 is always available for 110 operation. The input buffers are Schmitt-triggered. Bits programmed as outputs may be globally programmed as either pushpull or open-drain. -,. Port 5 is a bit programmable general purpose 110 port. The control and data registers for Port 5 are mapped into the expanded register file (Bank F) of the za. Auto Latch. The Auto Latch on Port 5 puts valid CMOS levels on all CMOS inputs which are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. --"' , PortS Z891201920 )0 (I/O) MCU ~ - J OEN Out 1.~ 2.3V Hysteresis In ------------ ..... I I Auto Latch I I.... _____________ R=500Ka .JI Figure 9. Port 5 Configuration 4-15 Z891201ZS9920 PRELIMINARY Z8~ 16-BIT MIXED SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION The Z8 CCP core incorporates special functions to enhance the Z8's performance in control applications. 65535 Extemal ROM and RAM 24575 Pipelined Instructions. The Z8 instructions (see page 4-70) are comprised of two parts, an instruction fetch and execute part. The instructions typically take between six and ten cycles to fetch and five cycles to execute. Five cycles of the next instruction fetch may be overlapped with five cycles of the current instruction execution. This improves performance over sequential methods. Additionally, the register-based archetecture allows any registers to be picked as the source and destination in an instruction saving intermediate move. Reset. The device is reset in one of the following conditions: • • • • Power-On Reset Watch-Dog Timer STOP-Mode Recovery Source External Reset Program Memory. The Z8 addresses up to 24 Kbytes of internal program memory and 40 Kbytes external memory (Figure 10). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors which correspond to the five user interrupts and one DSP interrupt. Byte 12 to byte 24575 consists of on-chip mask-programmed ROM. At addresses 24576 and greater, the Z8 executes external program memory. In ROMless mode, the Z8 will execute from external program memory beginning at byte 12 and continuing through byte 65535. 4-16 On-Chip ROM (In ROM Mode) Location of First Byte of Instrucli'on ~ .....- Execut AiterRES - ----- 11 IRQ5 10 IRQ5 9 IRQ4 8 IRQ4 7 Interrupt Vee!or 6 (LowerByte) IRQ3 t"'. IRQ2 4 "" IRQ2 ~~ Interru IRQ3 5 Vee! (UpperByte) 3 2 IRQ1 1 IRQO 0 IRoo IRQ1 Figure 10. Program Memory Map Z89120/Z89920 PRELIMINARY ROM Protect. The 24 Kbytes of internal program memory for the Z8 is mask programmable. A ROM Protect feature prevents "dumping" of the ROM contents of Program Memory by inhibiting execution of LOC, LOCI, LDE, and LDEI instructions. The ROM Protect option is mask· programmable, to be selected by the customer at the time when the ROM code is submitted. Data Memory (/OM). In ROM mode, the Z8 can address up to 40 Kbytes of external data memory beginning at location 24576 (Figure 11). In ROMless mode, the Z8 can address the full 64 Kbytes of external data memory beginning at location 12. External data memory may be included with, or separated from, the external program memory space. 10M, an optional 1/0 function that can be programmed to appear on Port 34, is used to distinguish between data and program memory space (Table 3). The state of the 10M signal is controlled by the type of instruction being ex· ecuted. An LOC opcode references PROGRAM (IDM inactive) memory, and an LDE instruction references data (10M active Low) memory. 16·BIT MIXED SIGNAL PRocESSOR 65535 r-------....., Extemal Data Memory 24756 1--------1 Not Addressable (In ROM Mode) 0 ....._ _ _ _ _..... Figure 11. Data Memory Map 4-17 ---_. --~~~~ Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR PRELIMINARY Z8 FUNCTIONAL DESCRIPTION (Continued) Register File. The standard Z8~ register file consists of four I/O port registers, 236 general-purpose registers, and 15 control and status registers (R3-RO, R239-R4, and R255-R241, respectively). The instructions access registers directly or indirectly through an 8-bit address field. This allows a short, 4-bit register address using the Register Pointer (Figure 12). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group (Figure 13). R253 RP Expanded Register Bank Working Register Group Default setting after RESET = 00000000 Figure 12. Register Pointer Register Note: Register Group E (Registers EO-EF) is only accessed through a working register and indirect addressing modes. r7 r6 r5 r4 r3 r2 rl rO R253 (Register Pointer) The upper nibble of the register file address provided by the register pOinter specifies the active working·register group. FF ~--------------------~ } R15 to RO ~ ~--------------------~ I Specified Working Register Group 2F The lower nibble of the register file address ~I- provided by the instruction pOints to the specified register. 20 1F Register Group 1 10 OF Register Group 0 ~----------------I/O Ports 00 Figure 13. Register Pointer 4-18 ~ R15toRO R15 to R4 R3to RO PRELIMINARY RAM Protect. The upper portion of the Z8's RAM address spaces 80FH to EFH (excluding the control registers) are protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user activates from the internal ROM code to turn off/on the RAM Protect by loading a bit D6 in the IMR register to either a 0 or a 1, respectively. A 1 in D6 indicates RAM Protect enabled. Stack. The Z8's external data memory or the internal register file is used for the stack. The 16-bit Stack Pointer (R255-R254) is used for the external stack which can reside only from 24576 to 65535 in ROM mode or 0 to 65535 in ROM less mode. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 236 general-purpose registers (R239-R4). SPH can be used as a general-purpose register when using internal stack only. Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR Expanded Register File. The register file on the Z8 has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices along with I/O ports into the register address area. The Z8 register address space has now been implemented as 16 banks of 16 registers groups per bank (Figure 14). These register banks are known as the ERF (Expanded Register File). Bits 7-4 of register RP (Register Pointer) select the working register group. Bits 3-0 of register RP select the Expanded Register bank (Figure 14). System configuration registers, Ports 4 and 5 mode registers, data registers and a DSP control register reside in Bank F of the Expanded Register File. Bank B of the Expanded Register File consists of the Mailbox Interface in which the Z8 and the DSP communicate. The rest of the Expanded Register is not physically implemented and is open for future expansion. 4-19 Z891201Z89920 PRELIMINARY 16-8fT MIxED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) Z8 STANDARD CONTROL REGISTERS REGISTER BANK (0) RESET CONDITION REGISTER GROUP 1S(F) REGISTER POINTER t ·· R~ ~,A_le ~~ r-___Z8 __ ____ ---------- FFH F~~---------------+~_ u u u u u u u u u u u u u u u u FFH SPl FEH SPH FDH RP 0 0 0 0 0 0 0 0 FCH FlAGS U U U U U U U U FSH IMR 0 U U U U U U U FAH IRQ 0 0 0 0 0 0 0 0 U F9H IPR U U U U U U U FSH P01M 0 1 0 0 1 1 0 1 F7H P3M 0 0 0 0 0 0 0 0 F6H P2M 1 1 1 1 1 1 1 1 FSH PREO U U U U U U U 0 %F4 TO U U U U U U U U F3H PRE1 U U U U U U 0 0 F2H T1 U U U U U U U U F1H TMR 0 0 0 0 0 0 0 0 FOH R_ 1 0 1 .... - --;..;;...-.....;.;.;;.;..;.;.;;.. il 7FH ~ A r ~ h 4 1J OFH 1re ______________ 0 ~--------------~ OOH~ ~~ \ '\ Z8 EXPANDED REGISTER BANK (F) · · REGISTER GROUP 0 (0) (F)OFH WDTMR (F)OEH R_ RESET CONDITION u u u 0 1 (F)ODH Raaarved (F)OCH DSPCON U U U U U U U U (F)OBH SMR 0 0 1 0 0 0 U 0 (F)OAH R...rved (F)09H R_ (F)06H R_ (F) 07H R_ (F)06H P4SM U U U 0 U U U 0 (F) 05H P5M 1 1 1 1 1 1 1 1 (F) 04H P5 U U U U U U U U (F) 03H P4M 1 1 1 1 1 1 1 1 (F) 02H P4 U U U U U U U U (F)01H Rooerved (F)OOH PCON 0 0 0 0 0 0 U U Z8 EXPANDED REGISTER BANK (B) za.oSP Mailbox 1"I""ace I Z8 STANDARD REGISTER BANK (0) REGISTER GROUP 0 RESET CONDITION (O)03H P3 1 1 1 1 U U U U (O)02H P2 U U U U U U U U (0) 01 H R...rved U U U U U U U U (O)OOH PO U U U U U U U U U. Unknown t = For RQMI... . . - , RESET Condition 10110110 • WII no! be I8S8I wIIh 8 STOP Mode Recovery Figure 14. Expanded Register File Architecture 4-20 Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR PRELIMINARY Interrupts. The Z8 has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 15). The six sources are divided as follows; three sources are claimed by Port 3 lines P33-P31, two in counter/timers, and one by the DSP (Table 4). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. IROO IR02 IR01, 3, 4, 5 IRO Register (D6, D7) 6 Global Interrupt Enable Interrupt Request Vector Select Figure 15. Interrupt Block Diagram Table 4. Interrupt Types, Sources, and Vectors Name Source Vector Location IROO IR01 IR02 /DAVO, P32, AN2 /DAV1, P33 /DAV2, P31, TIN' AN2 DSP TO T1 0, 1 2,3 4,5 External (P32), Programmable Rise or Fall Edge Triggered External (P33), Fall Edge Triggered External (P31), Programmable Rise or Fall Edge Triggered 6, 7 Internal (DSP activated) Internal Internal IR03 IR04 IR05 8,9 10, 11 Comments 4·21 ---------- -------- Z891201Z89920 IS-BIT MIXED SIGNAL PROCESSOR PRELIMINARY Z8 FUNCTIONAL DESCRIPTION (Continued) Table 5. IRQ Register When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. Thus, this disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request Register is polled to determine which of the interrupt requests need service. An interrupt resulting from ANI is mapped into IR02, and an interrupt from AN2 is mapped into IROO. Interrupts IR02 and IROO may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Interrupt Edge IRQ 07 o o 1 1 06 P31 P32 1 o F F R R F 1 RtF RtF o Notes: F = Falling Edge R = Rising Edge Clock. The Z89120t920 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL 1 =Input, XTAL2 =Output). The crystal should beAT cut, 20.48 MHz max., with a series resistance (RS) less than or equal to 100 Ohms. The system clock (SCLK) is one half the crystal frequency. The crystal is connected across XTAL 1 and XTAL2 using capacitors from each pin to ground (Figure 16). Programming bits for the Interrupt Edge Select is located in the IRO Register (R250), bits 07 and 06 . The configuration is shown in Table 5 . ....-.....---1 XTAL1 ,..........---1 XTAL 1 _ .....__ XTALI L ....-.....---1 XTAL2 ....-.....---1 XTAL2 XTAL2 C2~ Ceramic Resonator or Crystal LC Figure 16. Oscillator Configuration 4-22 F External Clock Z891201Z89920 PRELIMINARY CounterlTimers. TherR are two 8-bit programmable counter/timers (T1-TO), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the TO prescaler is driven by the internal clock only (Figure 17). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each pres caler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of the count, a timer interrupt request, IR04 (TO) or IR05 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can 16-Brr MIXED SIGNAL PROCESSOR also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided byfour, or an external signal input through Port 31. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers can be cascaded by connecting the TO output to the input of T1. 07-06 DSPCON Internal Data Bus ToT2, T3 PREO Initial Value Register TO Initial Value Register 6-Bit Down Counter 8-bit Down Counter TO Current Value Register IRQ4 TOUT P36 6-Bit Down Counter Internal Clock Gated Clock Triggered Clock IRQS T1 Initial Value Register Current Value Register TIN P31 Internal Data Bus Figure 17. CounterlTimer Block Diagram 4-23 PRELIMINARY Z8912OJZ89920 16-BIT MIxED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) Port Configuration Register (PCON). The PCON register configures the port individually; comparator output on Port 3, and open-drain on Port 0 and Port 1. The PCON register is located in the Expanded Register File at Bank F, location DOH (Figure 18). Port 4 and 5 Configuration Register (P45CON). The P45CON register configures Port 4 and Port 5, individually, to open-drain or push-pull active. This register is located in the Expanded Register File at Bank F, location 06H (Figure 19). Comparator Output Port 3 (00). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P35, and a 0 releases the port to its standard 1/0 configuration. Port 4 Open-Drain (00). Port 4 can be configured as an open-drain by resetting this bit (00 O) or configured as push-pull active by setting this bit (00 = 1). The default value is 1. Port 0 Open-Drain (01). Port 0 can be configured as an open-drain by resetting this bit (01 = O) or configured as push-pull active by setting this bit (01 = 1). The default value is 1. Port 5 Open-Drain (04). Port 5 can be configured as an open-drain by resetting this bit (04 = 0) or configured as push-pull active by setting this bit (04 = 1). The default value is 1. Port 1 Open-Drain (02). Port 1 can be configured as an open-drain by resetting this bit (02 = 0) or configured as push-pull active by setting this bit (02 = 1). The default value is 1. = P45M (FH) 06H Port 4 Configuration BIt o Open Drain 1 Push-pull PCON(F)OOH Reserved Comperator Output Port 3 o P34, P35 Standard Output' 1 P34, P35 Comparator Output Port 5 Configuration Bh Open Drain 1 Push-pull o Reserved oPort 0 Open-Drain 1 Port 0 Push-Pull Active" o Port 1 Open-Drain 1 Port 1 Push-Pull Active" Reserved • Defauh setting after Reset Figure 18. Port Configuration Register (PCON) / 4-24 Figure 19. Port 4 and 5 Configuration Register (F) 06H [Write Only] PRELIMINARY Power-On Reset (PaR). A timer circuit clocked by a dedicated on-board RC oscillator is used forthe Power-On Reset (PaR) timer function. The paR time allows Vee and the oscillator circuit to stabilize before instruction execution begins. The paR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status. 2. STOP-Mode Recovery (if 05 of SMR = 1). 3. WOT timeout. The paR time is a nominal 5 ms. Bit 5 of the STOP mode Register determines whether the paR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC/ LC oscillators). Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR STOP-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of STOP-Mode Recovery (Figure 20). All bits are write only, except bit 7 which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, or the SMR register, specify the source of the STOP-Mode Recovery signal. Bits 0 and 1 determine the timeout period of the WOT. The SMR is located in Bank F of the Expanded Register group at address OBH. SMR (F) 08 SCLKlTCLK Divide by 16 o HALT. HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IROO, IR01, IR02, and IR03 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. OFF· 1 ON RESERVED Stop Mode Recovery Source 000 POR Only· 001 Reserved 010 P31 011 P32 100 101 110 111 P33 P27 P2NORO·3 P2NORO·7 Stop Delay STOP. This instruction turns off the internal clock and external crystal oscillation. It reduces the standby current to 10 IlA (typical) or less. The STOP mode is terminated by a reset only, either by WOTtimeout, paR, SMR, or external reset. This causes the processor to restart the application program at address OOOCH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a Nap (opcode=FFH) immediately before the appropriate sleep instruction, i.e., FF Nap 6F STOP FF Nap 7F HALT o OFF 1 ON· Stop Recovery Level Low· 1 High o Stop Flag POR· 1 Stop Recovery o • Default setting after Figure 20. STOP-Mode Recovery Register (SMR) ; clear the pipeline ; enter STOP mode or ; clear the pipeline ; enter HALT mode 4-25 PRELIMINARY Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) SCLKlTCLK Divide-By-16 Select (00). 00 of the SMR controls a divide-by-16prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). STOP-Mode Recovery Source (04-02). These three bits of the SMR specify the wake-up source of the STOP recovery (Figure 21 and Table 6). SMA 040302 0 0 ~ SMA D4 03 02 SMA 04 03 02 010 100 o 1 1 voo P31 P32 SMA 04 03 02 101 SMA D4 03 02 1 1 0 SMA 040302 1 1 1 P27 ToPOR ~~~~----~---r-------------------------------------i--------~~ Stop Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 P33 From Pads DigitaVAnalog Mode Select (P3M) Figure 21. STOP-Mode Recovery Source Table 6. STOP-Mode Recovery Source SMR:432 D4 D3 D2 o o o o o o 1 1 1 o o o o 1 1 4-26 o 1 1 o 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 STOP-Mode Recovery Delay Select (05). This bit, if High, disables the 5 ms /RESET delay after STOP-Mode Recovery. The default configuration of this bit is one. If the "fast" wake up is selected, the STOP-Mode Recovery source is kept active for at least 5 TpC. STOP-Mode Recovery Edge Select (06). A 1 in this bit position indicates that a high level on anyone of the recovery sources wakes the Z89120 from STOP mode. A indicates low level recovery. The default is 0 on POR (Figure 20). o Cold or Warm Start (07). This bit is set by the device upon entering STOP mode. It is active High, and is 0 (cold) on POR/WDT /RESET. This bit is read only. It is used to distinguish between cold or warm start. Z891201Z89920 PRELIMINARY DSP Control Register (OSPCON). The OSPCON register controls various aspects of the Z8 and the OSP. It can configure the internal system clock (SCLK) or the za, /RESET and HALT of the OSP, and control the interrupt interface between the za and the OSP (Figure 22). 16-Brr MIXED SIGNAL PROCESSOR Z8 IRQ3 (00). This bit, when read, indicates the status of za IRQ3. za IRQ3 is set by the OSP by writing to OSP Expanded Register 4. By writing a 1 to this bit, Z8 IRQ3 is IRESET. DSP INT2 (01). This bit is linked to OSP INT2. Writing a 1 to this bit sets OSP INT2. Reading this bit indicates the status of OSP INT2. DSPCON (FH) OCH Write Read o No Effect 0 Z8 IRa3 Reset t Clear Z8 IRa3 1 Z8 IRa3 Set Write Read No Effect 0 DSP INT2 Reset 1 Set DSP 1NT2 1 DSP INT2 Set o Reserved DSP RESET (05). Setting this bit to 1 will reset the OSP. If the OSP was in HALT mode, this bit is automatically preset to 1. Writing a 0 has no effect. This bit is write only. DSP Run o HaltDSP 1 Run DSP L -_ _ _ _ _ _ _ DSP Reset (Write Only) o No Effect 1 ResetDSP L -_ _ _ _ _ _ _ _ _ DSP RUN (04). This bit defines the HALT mode olthe OSP. If this bit is set to 0, then the OSP clock is turned off to minimize power consumption. After this bit is set to 1, then the OSP will continue code execution from where it was halted. After a hardware reset, this bit is set to O. Z8 SLCK (08-07). These bits define the SCLK frequency of the za. The oscillator can be either divided by a, 4, or 2. After IRESET, both of these are defaulted to 00. Z8 SCLK 00 2.5 MHz (OSC+8) 01 5 MHz (OSC+4) 1. 10 MHz (OSC+2) Watch-Dog Timer Mode Register (WOT). The WOT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WOT is initially enabled byexecuting the WOT instruction and refreshed on subsequent executions of the WOT instruction. The WOT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL 1 pin. The POR clock source is selected with bit 4 of the WOT register (Figure 23). The WOT affects the Z (zero), S (sign), and V (overflow) flags. Figure 22. DSP Control Register (F) OCH [ReadlWrite] WDTMR (F)OF Iwloolool~lool~I~lool -- I I -'" ,~~~ 00 5ms 01' 10 11 15ms 25 ms 100ms External Clock 256TpC 512TpC 1024TpC 4096TpC WDT During HALT OFF 1 ON' L-_ _ _ _ WDT During STOP o o OFF 1 ON' L-_ _ _ _ _ XTAL1/INT RC Select for WDT o On-Board RC ' 1 XTAL L-_ _ _ _ _ _ _ _ Reserved , Default setting after RESET Figure 23. Watch-Dog Timer Mode Register 4-27 Z891201Z89920 PRELIMINARY 1&oBIT MIXED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) WOT During HALT (02). This bit determines whether or WOT Time Select (00,01). Selects the WOT time period (Figure 24). It is configured as shown in Table 7. not the WOT is active during HALT mode. A 1 indicates active during HALT. The default is 1. Table 7. WOT Time Select 01 DO 0 0 1 1 0 1 0 1 Timeout of Internal RC OSC WOT During STOP (03). This bit determines whether or Timeout of XTALciock 5msmin 15 ms min 25 ms min 100ms min not the WOT is active during STOP mode. Since XTAL clock is stopped during STOP mode, the on-board RC has to be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1. 256TpC 512TpC 1024 TpC 4096TpC Clock Source for WOT (04). This bit determines which oscillator source is used to clock the internal POR and WOT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WOT clock source is driven from the external pin, XTAL 1. The default configuration of this bit is 0 which selects the RC oscillator. Notes: TpC = XTAL clock cycle The default on reset is 15 ms. See Figures 54 to 57 for details. 1----.fOcl;;ea;r-~i8C;;~;Eir_:=:1 18 Clock RESET 4 Clock .._F;.;;IR;;;er;......,l.. r-_ _--1cLK Generator RESET Internal RESET WDT Select (WDTMR) CKSource Select (WDTMR) XTAL -----+-----t--{:;=~~~~~:rI - - - - - - I I -....... ----.....,j........ 5mSPOR CLR WDT/POR Counter Chain VDD 2VREF. From Stop Mode Recovery Source 12 ns GIHch FiRer WDT------..I Stop Delay _ _ _ _ _ _ _ _ _ _---1 Select (SMR) Figure 24. Resets and WOT 4-28 PRELIMINARY Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR DSP FUNCTIONAL DESCRIPTION General. The DSP is a high-performance second generation CMOS Digital Signal Processor with a modified Harvardtype architecture with separate program and data ports. The design has been optimized for processing power and saving silicon space. Program Memory. Programs of up to 4K words can be masked into internal DSP ROM. Four locations are dedicated to the vector address for the three interrupts (OFFDHOFFFH) and the starting address following a reset (OFFCH). Internal Data RAM. The DSP has an internal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each, referred to as RAMO and RAM1. Each data RAM bank is addressed by three address register pointers, referred to as PO:0-P2:0 for RAMO and PO:1-P2:1 for RAM1. Three addressing modes are available to access the data RAM: register indirect, direct, and short-form direct addressing. These modes are discussed in detail in Functional Description. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The DSP has twelve internal registers and seven extended registers. The extended registers are for the NO and D/A converters, and the mailbox and interrupt interfacing between DSP to the za. Extended registers are accessed in one machine cycle, the same as internal registers. Instruction Timing. Many instructions are executed in one machine cycle. Long immediate instructions and Branch or Call instructions are executed in two machine cycles. When the program memory is referenced in internal RAM indirect mode, it takes three machine cycles. In addition, one more machine cycle is required if the PC is selected as the destination of a data transfer instruction.This only happens in the case of a register indirect branch instruction. For example, an a(i) * b(j) + Acc --. Acc calculation is done in one machine cycle, modifying the RAM pointer contents. Both operands, a(i) and b(j), can be located in two independent RAM (0 and 1) addresses. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply or multiply accumulate in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers where the least significant bits are important, the data should first be scaled by eight bits to avoid truncation errors. ALU. The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16 bits of which are connected to the 16-bit D-Bus. A shifter between the P-Bus and the ALU input port can shift the data by three bits right, during a multiply/accumulator operation or no shift. Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction pops the contents of the stack to the PC. Interrupts. The DSP has three positive edge triggered interrupt inputs. An interrupt is acknowledged at the end of any instruction execution. It takes two machine cycles to enter an interrupt instruction sequence. The PC is pushed onto the stack. A RET instruction transfers the contents of the stack to the PC and decrements the stack pointer by one word. The priority of the interrupts is 0 = highest, 2 = lowest. 4-29 Z891201Z89920 PRELIMINARY 16-BIT MIXED SIGNAL PROCESSOR DSP Registers There are 15 internal and extended 16-bit registers which are defined in Table 8. Table 8. DSP Registers Register Attribute BUS X y A Read Read/Write Read/Write Read/Write Data-Bus X Multiplier Input, 16-Bit Y Multiplier Input, 16-Bit Accumulator, 24-Bit SR SP PC P Read/Write Read/Write Read/Write Read Status Register Stack Pointer Program Counter Output of MAC, 24-Bit EXTO Read Write Read Write Z8 Z8 Z8 Z8 ERF Bank ERF Bank ERF Bank ERF Bank Read Write Read Write Z8 Z8 Z8 Z8 ERF Bank B, ERF Bank B, ERF Bank B, ERF Bank B, EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 4-30 Read/Write Read Write Read/Write Register Definition B, B, B, B, Register 00-01 (from Z8) Register 08-09 (to Z8) Register 02-03 (from Z8) Register OA-OB (to Z8) Register Register Register Register 04-05 (from Z8) OC-OD (to Z8) 06-07 (from Z8) OE-OF (to Z8) DSP Interrupt Control Register AID Converter D/A Converter Analog Control Register Z891201Z89920 16-B1r MIxED SIGNAL PRocEssOR PRELIMINARY Two registers, Bus and P are read only. If either of these registers are designated as the destination of a data transfer instruction, the contents will be unaffected. BUS is a read-only register which, when accessed, returns the contents of the D-Bus. X and Yare two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. The P register is affected by changing X or Y. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSB's and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. SR is the DSP status register (Figure 25) which contains the ALU status and certain control bits as shown in Table 9. 000 001 010 011 100 101 110 1 11 Loop Size 256 2 4 8 16 32 64 128 General purpose register bank PO output (general purpose) P1 output (general purpose) Interrupt Enable Overflow protection MPY output shifted by three bits Reserved Carry Zero Overflow Negative Figure 25. DSP Status Register 4-31 PRELIMINARY Z89120JZ89920 16-Brr MIxED SIGNAL PROCESSOR DSP FUNCTIONAL DESCRIPTION (Continued) Table 9. DSP Status Register Bits Sialus Regisler Bil S15 S14 S13 S12 (N) (OV) (Z) (C) ALU Negative ALU Overflow ALU Zero Carry S11 S10 S9 sa (U01) (UOO) (SH3) (OP) User Pin 1 Input (DSP1) User Pin 0 Input (DSPO) MPY Output Shined by 3 Bits Overflow Protection S7 S6 S5 S4-S3 S2-S0 (IE) (P1) (PO) (RBi) (RPL) Interrupt Enable User Output (General Purpose) User Output (General Purpose) General Purpose Register Ban RAM Pointer Loop Size 4-32 Function PC is the program counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. P is the output register for the 24-bit multiplier. S2 S1 SO Loop Size 0 0 0 0 0 0 1 1 0 1 0 1 256 2 4 8 0 0 1 1 0 1 0 1 16 32 64 128 EXT3-EXTO (Extended Registers 0-3) are the Mailbox Registers in which the DSP and the Z8 communicate (Figure 26). These four 16 bit registers correspond to the eight outgoing and eight incoming 8-bit registers in Bank B of the Z8's Expanded Register File. EXT4 (DSP Interrupt Control Register (lCR» controls the interrupts in the DSP as well as the interrupts in common between the DSP and the Z8. It is accessible by the DSP only, except for the bit F and bit 9. EXT5 (D/A and ND Data Register) is used by both D/A and A/D converters. The D/A converter will be loaded by writing to this register, while the A/D converter will be addressed by reading from this register. The Register EXT5 is accessible by the DSP only. EXT6 (Analog Control Register) controls the D/A and ND converters. It is a read/write register accessible by the DSPonly. ZB91201Z89920 16-BIT MIxED SIGNAL PRocEssOR PRELIMINARY Mail Box Registers - Outgoing Registers !"- (B)OO, (B)01 (B)02, (B)03 EXTO .... EXT1 " EXT2 A ... (B)04, (B)05 (B)OS, (B)07 J\o. . EXT3 Incoming Registers (B)08, (B)09 (B)OA, (B)OB EXTO AEXT1 .... til :::J ID '.19 III 0 ~ EXT2 (B)OC, (B)OO (B)OE, (B)OF ~ 0 EXT3 DSP Interrupt Control Register (A)OO 07,01 til :::J ID .... K EXT4 Il.. .. CIJ 0 r 1 D/A and AID Data Registers EXT5 A . Analog Control Register ...... .... EXTS K J\o. .. .. r - Figure 26. Z8-0SP Interface 4-33 Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY DSP-Z8 Mailbox To receive information from the DSP, the 28 uses eight incoming registers which are mapped in the 28 Extended Register File (Bank B, 08 to OF). The DSP treats these as four 16-bit registers that correspond to the eight incoming 28 reg isters. Both the outgoing registers and the incoming registers share the same DSP address (EXT3-EXTO). Note: The 28 can read and write to ERF Bank B ROO-R07, Registers 08-0F are read only from the 28. Table 10. Outgoing Registers (Read Only from DSP) Field (Z8 Side) Z8 Position Z8 AHributes DSP Position DSP AHributes Label Outgoing Outgoing Outgoing Outgoing [0] [1] [2] [3] 76543210 76543210 76543210 76543210 R(W R(W R(W R(W FEDCBA98 765434210 FEDCBA98 765434210 R R R R DSPextO_hi DSPextOJo DSPext1_hi DSPextUo Outgoing Outgoing Outgoing Outgoing [4] [5] [6] [7] 76543210 76543210 76543210 76543210 R(W R(W R(W R(W FEDCBA98 765434210 FEDCBA98 765434210 R R R R DSPext2_hi (15-8) DSPext2Jo (7-0) DSPext3_hi (15-8) DSPext3Jo (7-0) (15-8) (7-0) (15-8) (7-0) Table 10. Incoming Registers (Write Only from DSP) Field (Z8 Side) Z8 Position Z8 AHributes DSP Position DSP AHributes Label Incoming Incoming Incoming Incoming [0] [1] [2] [3] 76543210 76543210 76543210 76543210 R R R R FEDCBA98 76543210 FEDCBA98 76543210 W W W W DSPextO_hi DSPextO_lo DSPext1_hi DSPextUo (15-8) (7-0) (15-8) (7-0) Incoming Incoming Incoming Incoming [4] [5] [6] [7] 76543210 76543210 76543210 76543210 R R R R FEDCBA98 76543210 FEDCBA98 76543210 W W W W DSPext2_hi DSPext2Jo DSPext3_hi DSPext3Jo (15-8) (7-0) (15-8) (7-0) 4-34 Z891201Z89920 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR DSP Interrupts The DSP processor has three interrupt sources (INT2, INT1, INTO) (Figure 27). These sOtJrces have different priority levels (Figure 28). The highest priority, the next lower and the lowest priority level are assigned to INT2, INT1, and INTO, respectively. The DSP does not allow ZS_INT AID INT D/AINT IPR2 --- Interrupt Priority Logie -- interrupt nesting (interrupting service routines that are currently being executed). When two interrupt requests occur simultaneously, the DSP starts servicing the interrupt with the highest priority level (Figure 29). INT2 Interrupt Request Logic Interrupt Mask Logic INTO '1 IPRl INT2 INTl INTl INTO CLEAR_INTO CLEAR_INTl IPRO CLEAR_INT2 FBDSP -- FeedBack ZS_INT MPX ENABLE INT Figure 27. DSP Interrupts 1] INTO 1 INTl INT2 DSP Execution 1] INT2 I 1 INTO " II INT1 II INT2 Figure 28. DSP Interrupt Priority Structure 4-35 -------_.,----- Z891201Z89920 l6·Brr MIXED SIGNAL PROCESSOR PRELIMINARY DSP Interrupts (Continued) IR02 of the DSP The DSP can clear IR02 bit by writing 1 to this location. Resets the IR02 of the DSP. I " ZS can read and write IR02 bit. The bit is set by the ZS and can be cleared only by the DSP. IR03 of the ZS 4--------------- /I /I / / / / / / / " ZS can reset the IR03 bit I by writing 1 to this location. / .---------------~ I I \ : \ I \ I I I \ DSP can read and write IR03 bit. The bit is set by the DSP and can be cleared only by the ZS. \ . . - - - - - - - - - - - - ............ __ I I I L - - I ~ L-~ ~1L.._D_E_LA_Y_L_IN_E_(_3T)_...Jr- Figure 29. Interprocessor Interrupts Structure Interrupt Control Register {lCR). The ICR is mapped into EXT4 of the DSP (Figure 30). The bits are defined as follows. DSP_IR02 (Z8 Interrupt). This bit can be read by both Z8 and DSP and can be set only by writing to the Z8 expanded Register File (Bank F, ROC, bit 0). This bit asserts IRQ2 of the DSP and can be cleared by writing to the CieaURQ2 bit. DSP_IR01 (AID Interrupt). This bit can be read by the DSP only and is set when valid data is present at the AID output register (conversion done). This bit asserts IRQ1 of the DSP and can be cleared by writing to the CieaURQ1 bit. DSP_I ROO (D/A Interrupt). This bit can be read by DSP only and is set by Timer3. This bit assists IRQO of the DSP and can be cleared by writing to the CleaURQO bit. DSP_MasklntX. These bits can be accessed by the DSP only. Writing a 1 to these locations allows the INT to be serviced, while writing a 0 masks the corresponding INT off. 4-36 Z8_IR03. This bit can be read from both Z8 and DSP and can be set by DSP only. Addressing this location accesses bit D3 of the Z8 IRQ register, hence this bit is not implemented in the ICR. During the interrupt service routine executed on the Z8 side, the user has to reset the Z8JRQ3 bit by writing a 0 to bit D9. The hardware of the Z89120 automatically resets Z8JRQ3 bit three instructions of the Z8 after 0 is written to its location in register bank OF. This delay provides the timing synchronization between the Z8 and the DSP sides during interrupts. In summary, the interrupt service routine of the Z8 for IRQ3 should be finished by: SRP OF OC,#%FD AND POP RP IRET DSP Enable_INT. Writing a 1 to this location enables global interrupts of the DSP while writing 0 disables them. A system reset globally disables all interrupts. DSP_IPRX. This 3-bit group defines the Interrupt Priority according to Table 12. Z891201Z89920 PRELIMINARY c 16-Brr MIxED SIGNAL PRoCESSOR Reserved CleerlROO o No Effect 1 CleerlROO CleerlR01 o No Effect 1 CleerlR01 CleerlR02 o No Effect 1 CleerlR02 DSP Interrupt Priori1y 000 IROO> IR01 > IR02 001 IROO> IRQ2 > IR01 010 IR01 > IROO > IR02 011 IR01 > IRQ2 > IROO 100 IRQ2 > IROO > IR01 101 IRQ2 > IR01 > IROO 110 Reserved 111 Reserved DSP In1erupt Enable o Disable 1 Enable ZBIR03 SetZBIR03 Reset ZB IR03 DSP InterruptO Mask o Diseble INTO 1 Enable INTO DSP Interrupt1 Mask o Disable INT1 1 Enable INT1 DSP Interrupt2 Mask o Disable INT2 1 Enable INT2 DSP InterruptO Slatus (DSP IROO) (Read Only) o INTOReset 1 INTO Set DSP Interrupt1 Slatus (DSP IR01) o INT1 Reset 1 INT1 Set DSP Interrupt2 Slatus (DSP IRQ2) o 1NT2 Reset 1 INT2Set Figure 30. EXT4 DSP Interrupt Control Register (lCR) Definition Table 12. DSP Interrupt Priority High Priority intO Interrupt Medium Priority int1 Interrupt Low Priority Int2 Interrupt DSP_IPR2, 1, 0 IROO IROO IR01 IR02 IR02 IR01 000 001 IR01 IR01 IROO IR02 IR02 IROO 010 01 1 IR02 IR02 IROO IR01 IR01 IROO 100 1 01 4-37 --~~----.~--~--------- Z891201Z89920 PRELIMINARY 16·Brr MIXED SIGNAL PROCESSOR DSP Interrupts (Continued) Clear_IRQX.These bits can be accessed by the DSP only. Writing a 1 to these locations resets the corresponding DSPJRQX bits to o. CleaURQX are virtual bits and are not implemented. The Z8 can supply the DSP with data through eight outgoing registers mapped into both the Z8 Extended Register File (Bank B, Registers 00 to 07) and the external register interface of the DSP. These registers are RNI and can be used as general purpose registers of the Z8. The DSP can only read information from these registers. Since the DSP uses a 16·bit data format and the Z8 uses an a-bit data format, eight outgoing registers of the Z8 correspond to four DSP registers. The DSP can only read information from the outgoing registers. DSP Analog Data Registers The D/A conversion is DSP driven by sending 10-bit data to the EXT5 of the DSP. The six remaining bits of EXT5 are not used (Figure 31). The AID supplies 8-bit data to the DSP through register EXT5 of the DSP. From the 16 bits of EXT5, only bits 2 through 9 are used by the AID (Figure 32). Bits 0 and 1 are padded with zeroes. 10·BII Data for O/A (WrlteOnly) Reserved Figure 31. EXT5 Register DIA Mode Definition I --c:.. IFIeioiciBIAI91al7161s1413121110 Reserved a·BIt Data From AID Converter (Read Only) Reserved Figure 32. EXT5 Register AID Mode Definition 4-38 Z891201Z89920 PRELIMINARY 16-BIT r.txED SIGNAL PRocESSOR Analog Control Register (ACR) The Analog Control Register is mapped to register EXT6 of the DSP (Figure 33). This read/write register is accessible by the DSP only. . Table 13. D/A Data Accuracy Sampling Rate 64kHz 16 kHz 10 kHz 4kHz The 16-bit field of EXT6 defines modes of both the AID and the D/A. The High Byte configures the D/A. while the Low Byte controls the NO mode. D/A Accuracy 8 Bits 10 Bits 10 Bits 10 Bits DSP IRQO. Defines the source of DSP IROO interrupt. D/A Converter Effective Sempllng Rate. This field defines the effective sampling rate of the D/A output (Figure 33). It changes the period of Timer3. which generates the interrupt for updating the output sample and in turn affects the maximum possible accuracy of the D/A (Table 13). 115114113112111 110 DSPO. DSPO is a general purpose output pin connected to bit 6. This bit has no special significance and may be used to output data by writing to bit 6. DSP1.DSP1 is a general purpose output pin connected to bit 7. This bit has no special significance and may be used to output data by writing to bit 7. II II I 9 81 7 6 514 31 2 11 I 0 1 L- AID Converter Sampling Rate 000 8 001 16 010 32 011 64 100 128 1 0 1 Reeerved 1 1 0 Reeerved 1 1 1 Reeerved StartAID Conversion Walt for llmer2lime-out 1 Start Immediately o Conversion Done o AID Conversion Not Done 1 AID Conversion Done Enable AID Disable 1 Enable o DSPO DSPI D/AConverterSampling Rate o00 Reserved 001 4kHz 010 16kHz 011 10kHz 100 64kHz 10 1 Reserved 110 Reserved 111 Reserved Reserved DSP IRoo Source o limer3 1 P26(ZB) Figure 33. EXT6 Analog Control Register (ACR) 4-39 Z891201Z89920 PRELIMINARY 16·BIT MIxED SIGNAL PROCESSOR ANALOG CONTROL REGISTER (Continued) Enable AID. Writing a 0 to this location disables the NO converter, a 1 will enable it. A hardware reset forces this bit to be o. Start AID Conversion. Writing a 1 to this location immediately starts one conversion cycle. If this bit is reset to 0 the input data is converted upon successive Timer2 time-outs. A hardware reset forces this bit to be 1. Conversion Done. This read only flag indicates that the .NO conversion is complete. Upon reading EXT5 (A/D data), the Conversion Done flag is cleared. AID Converter Sampling Rate. This field defines the sampling rate of the NO. It changes the period of Timer2 interrupt (Figure 33). DSPTimers Timer2 is a free running counter that divides the XTAL frequency to support different sampling rates for the A/D converter. The sampling rate is defined by the Analog Control Register. Upon reaching the end of a count, the timer generates an interrupt request to the DSP. The contents of the RAM can be read or written in one machine cycle per word without disturbing any internal registers or status other than the RAM address pointer used for each RAM. The address of the RAM is specified in one of three ways: Analogous to Timer2, Timer3 generates the different sampling rates for the D/A converter. Timer3 also generates an interrupt request to the DSP upon reaching its final count value (Figure 34). Note: that the crystal speed in this example is 20.48 MHz, which is the maximum tested speed, but lower speeds may be used. DSP RAM. The DSP has two 256 word x 16-bit internal RAMs (RAMO and RAM1) with three address pointer registers for each RAM Bank, PO:0-P2:0 and PO: 1-P2: 1. The RAM addresses for RAMO and RAM1 are arranged from 255-0 and 256-511, respectively. The address pointers, which may be written or read, are 8-bit registers connected to the lower byte of the internal 16-bit, D-Bus and are used to perform no overhead hardware looping. TIMER2 128, 64, 32, 16, 8 kHz TIMER3 64,16,10,4 kHz Figure 34. Timer2 and Timer3 4·40 1. Register Indirect (Figures 35 and 38) Pn:b n = 0-2, b = 0-1: The most commonly used method is a register indirect addressing method, where the RAM address is specified by one of the three RAM address pointers (n) for each bank (b). Each source/destination field in Figures 35 and 39 may be used by an indirect instruction to specify a register pointer and its modification after execution of the instruction (Figures 35 and 39). The register pointer is specified by the first and second bits in the source/destination field and the modification is specified by the third and fourth bits according to Table 14. b n1 nO I I I I I I 08 03 02 01 DO Figure 35. DSP Register Indirect Fields Z89120/Z89920 16-BIT r.mD SIGNAL PRoCESSOR PRELIMINARY Table 14. Register Indirect Fields SID Field Modification OOxx 01xx 10xx 11xx NOP +1 -1/LOOP +1/LOOP xxOO xx01 xx10 PO:O or PO: 1* P1:0 or P1:1* P2:0 or P2:1* Meaning No Operation Simple increment Decrement modulo the loop count Increment modulo the loop count See Note a. See Note a. See Note a. Notes: a. If bit S Is zero, PO:O-2:0 are selected; if bit S is one, PO:1-2:1 are selected. • PO:0-P2:0 and PO:1-P2:1 refer to the DSP pointer registers and not to the I/O ports in the ZS. When LOOP mode is selected, the size of the loop is obtained from the least-mast-significant three bits of the Status Register. The increment or decrement of the register is accomplished modulo the loop size. As an example, if the loop size is specified as 32 by entering the value 101 into bits 2-0 of the Status Register (S2-S0) and an increment + 1/LOOP is specified in the address field of the instruction, i.e., the RPi field is 11xx, then the register specified by RPi will increment, but only the least significant five bits will be affected. 2. Register Direct (Figure 36): The second method is a direct addressing method. The address of the RAM is specified by the address field of the instruction directly. Because this addressing method consumes nine bits (0-511) of the instruction field, some instructions cannot use this mode. RAM Address Opcode Figure 36. DSP Internal RAM Address Format 4-41 Z891201Z89920 PRELIMINARY 16-Brr MIxED SIGNAL PROCESSOR DSP Timers (Continued) 3. Short Form Direct (Figure 37) Dn:b n =0-3, b =0-1 : The last method is called Short Form Direct Addressing, where one-out-of 32 addresses in internal RAM can be specified. The 32 addresses are the 16 Low addresses in RAM Bank o and the 16 Low addresses in RAM Bank 1. Bit 8 of the instruction field determines RAM Bank 0 or 1. The 16 addresses are determined by a 4-bit code comprised of bits S3 and S4 of the status register and the third and fourth bits of the Source/Destination field. Because this mode can specify a direct address in a short form, all the instructions where the register indirect mode is used can use this mode. Short Immediate Data Reg. Pointer 000 001 010 011 100 101 110 111 po:o P1:0 P2:0 NA PO:1 P1:1 P2:1 NA Opcode 00011 Figure 37. Short Form Direct Address INSTRUCTION FORMAT Source field Destination field RAM Bank selection Opcode Note: Source/Destination fields can speciry either register or RAM address in RAM pOinter indirect mode. Figure 38. General Instruction Format 4-42 Z89l201Z89920 PRELIMINARY Table 15. Registers Fields Source/Destination Table 16. Register Pointers Fields Register Source/Destination BUS** X 0000 0001 0010 0011 y 0100 0101 0110 0111 S ST PC P** 1000 1001 1010 1011 EXTO EXT 1 EXT2 EXT3 1100 1101 1110 1111 EXT4 EXT5 EXT6 l6·Brr MIXED SIGNAL PROCESSOR A Meaning OOxx 01xx 10xx 11xx NOP +1 -1/LOOP +1/LOOP xxOO xx01 xx10 PO:O or PO: 1* P1:0 or P1:1* P2:0 or P2:1* Notes: If RAM Bank bit is 0 then PO:0-P2:0 are selected. If RAM Bank bit is 1 then PO:1-P2:1 are selected. Also note, PO:0-P2:0 and PO:1-P2:1 refer to the DSP pointer registers and not to the I/O ports in the ZB . •• Read only. S4, S3 = bits 4, 3 of Status Register D3, D2 bits 4, 3 of Source/Destination Field • = Reserved Short Immediate Data 000 Reg. Pointer PO:O 001 010 011 100 101 110 111 P1:0 P2:0 NA PO:1 P1:1 P2:1 NA Opcode 00011 Figure 39. Short Immediate Data Load Format 4·43 ----- .. - - . - - - - ------ -- Z891201Z89920 16·Brr MIXED SIGNAL PROCESSOR PRELIMINARY INSTRUCTION FORMAT (Continued) lsI Word Genera/Instruction Fonnat 2nd Word Immediate Data Figure 40. Immediate Data Load Format 101510141013 012101110101091 DB 1071 D6 05104103102101100 1 -r- ACC Modification Codes o0 0 0 ROR Rotate right 0001 ROL Rotateleft 0010 SHR Shift right 0011 SHL Shiftleft o10 0 INC Increment (LSB) o10 1 DEC Decremant (LSB) o11 0 NEG Negate o1 1 1 ABS Absolute Condition Codes 0000 TRUE 0001 -DOlO UOO=O 0011 U01=O 0100 C=O 0101 Z=O 01100V=O 0111 N=O 1 xxx •••• 0000 TRUE 0001 •••• 0010 UOO=1 0011 U01=1 0100 C=1 0101 Z=1 01100V=1 0111 N=1 1 xxx •••• o= Negative Condition 1 = Positive Condition Opcode 1001000 Figure 41. Accumulator Modification Format 4·44 Z891201Z89920 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR 1st Word xxxx Condition Cod.. 0000 TRUE 0001 -0010 UOO=O 0011 U01=O 0100 C=O 0101 Z=O 01100V=O 0111 N=O 1 xxx ---0000 TRUE 0001 ---0010 UOO=I 0011 UOl=1 0100C=1 0101 Z=1 01100V=1 0111 N=1 1 xxx ---Cond~on 0= Negative Condition 1 = Positive Condition Opoode 0100110 Branch 0100100 Call 2nd Word Branch Addrass Figure 42. Branching Format ' - - - - xxl0 xx 11 xlxO xl xl lxxO lxxl L..._ _ _ _ _ _ _ _ _ _ Reset C flag SlIt Cflag Reset IE Flag (Interrupt enable) Set IEAag Reset OP Aag (Overllow protection) Set OPAag xxxx Opoode 1001010 Mod Figure 43. Flag Modification Format 4-45 PRELIMINARY Z89l201Z89920 l6-Brr MIXED SIGNAL PROCESSOR PULSE WIDTH MODULATOR (PWM) Digital to Analog Converter The analog signal is generated by a 10-bit resolution oversampling pulse distribution modulator (OPOM). The OPOM output is a digital signal with 0 to Vee output levels. The effective sampling rate is directly programmable by the OSP processor and indirectly by the Z8C~ ~N ~~r--Ci>l-f>- VAEF _ _______________________ -.; The IISIng edge of 1he 'SIaJI conv" occurs upon Invo~ng 1he SIaJI COIMIISIOII bot mEXT6 or upon limer2TIIIIIKlut.. The failing odgo ocan 24 CI.K's after 1he lint COINIISIOIISIaJ1ed. The oolllbon of1he startconv. SlIJIBIIs 1he COIMIIliIon bme of1he NO 2,4 ~N _ VAEF ~..., r;:'..., converter _h camoI be shorter1hen (24+1). mAL =2.4ps L ~~f---1--1>--1-i> ~ ~ I Ide bme reserved for Mum CIIanneI Conversion Figure 46. ADC Timing Diagram ~ 2048MHl12 itf '-e<> ;&';;; ~~ i§!§ :u C> Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY AID CONVERTER (ADC) (Continued) Figure 47 shows the input circuit of the ADC. When conversion starts, the analog input voltage from the input is connected to the MSB and LSB flash converter inputs as shown in the Input Impedance circuit diagram. Shunting 31 parallel internal resistances of the analog switches and simultaneously charging 31 parallel 0.5 pF capacitors (only the first, 0.5 pF caps matter) is equivalent to a 400 Ohm input impedance in parallel with a 16 pF capacitor. Other input stray capacitance adds about 10 pF to the input load. Input source resistances of up to 2 kOhms can be used under normal operating conditions without any degradation of the input settling time. For larger input source resistance, longer conversion cycle times may be required to compensate for the input settling time problem. VAEF is set using the VAEF+ pin. The operation of the flash converter is divided into two parts. The first section converts the four MSBs and the second similar section converts the four LSBs. Before a conversion starts all the switches across the comparators are shut, thus forcing input and output to Vcc+2. The input switches are also closed, forcing the 0.5 pF sample capacitors to track the input voltage on one side while the other side is held at Vcc+2. When the switch inputs (Si) open the charge is stored on the sample capacitor. A linear resistor ladder divides the reference voltage into 32 equal steps. When the Si's open, they are connected to the stepped reference voltages at the same time the switch comparators (Sc's) are opened, allowing the input to the comparator to change. The new input to the comparator will be the sum of the original voltage across the sample cap and the reference Voltage. This voltage is compared to Vcc+2 on the threshold of the comparator. For any given input voltage, the 31 comparators will divide between all "on" above the input voltage and all "off" below it. The parallel output then is converted by logic into a binary value. VRef+ Sc Sc ~~ .5pF .5 pF Sc Sc ~r-Q;:L I I I I I I .5pF : Sc r I VRef- : Sc ~r-Q;:L Si .5pF .5pF C * G21 PMOS T NMOS VIN~VOUT G1 C Transfer gate on resistance =2-5 kr.!. Figure 47. Input Impedance of ADC 4-50 31 Comparators PRELIMINARY Once the determination has been made as to which point in the resistor divider the signal came closest to, the second part of the conversion takes place. In this case, the LSB part of the signal is across the resistor in the ladder 1st ladder Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR adjacentto the comparison point. A second resistor ladder and comparators similar to the first are connected across the resistor (see Figure 48). A second conversion similar to the first takes place to complete the LSB portion. 2nd ladder VRel+ Initial compare point VRel- Figure 48. Input Impedance of ADC 4-51 Z891201Z89920 16·8rr MIXED SIGNAL PROCESSOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Symbol Vee TSTG TA Description Min Max Supply Voltage (*) -0.3 Storage Temp -65° Oper Ambient Temp +7.0 +150° t Units V C C Notes: Voltage on all pins with respect to GND. t See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 49). +5V 2.1 kO From Output Under Test o----t---+--IIO--....... 150pF I Figure 49. Test Load Diagram CAPACITANCE TA = 25°C. Vee = GND = OV. f = 1.0 MHz. unmeasured pins returned to GND. Parameter Max Input capacitance Output capacitance I/O capacitance 12 pF 12 pF 12 pF 4-52 ~2iu::a; Z89l201Z89920 l6-Brr MIXED SIGNAL PROCESSOR P R ELIMINARY DC ELECTRICAL CHARACTERISTICS Sym Icc Icc1 Icc2 TA = ooe to +700 e Min Max Vee Note [1] Parameter Supply Current HALT Mode Current STOP Mode Current 5.0V 5.0V 5.0V Typical @25°e 40 6 6 65 10 20 Units mA mA IlA Notes: [1]5 OV±O 5V DC ELECTRICAL CHARACTERISTICS Sym Parameter Max Input Voltage VeH Clock Input High Voltage Vel Clock Input Low Voltage VIH Input High Voltage Vil Input Low Voltage VOH Output High Voltge VOl1 Output Low Voltage Vee Note (1) TA =DOC to +70°C Min Max Typical @25°C Units 1.3 2.5 V V V V liN 250 J.IA liN 250 J.IA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Conditions 3.3V 5.0V 3.3V 5.0V 0.7 Vee 0.7 Vee 7 7 Vee+0.3 Vee+0.3 3.3V 5.0V 3.3V 5.0V GND-o.3 GND-o.3 0.7 Vee 0.7 Vee 0.2 Vee 0.2 Vee Vee+0.3 Vee+0.3 0.7 1.5 1.3 2.5 V V V V 3.3V 5.0V 3.3V 5.0V GND-o.3 GND-o.3 Vee-004 Vee-004 0.2 Vee 0.2 Vee 0.7 1.5 3.1 4.8 V V V V IOH =-2.0 rnA IOH =-2.0 rnA 1.2 1.2 0.2 0.1 0.3 0.3 V V V V IOl =+4.0 rnA IOl =+4.0 rnA IOl = +6 rnA, 3 Pin Max IOl =+12 rnA, 3 Pin Max 0.8 Vee 0.8 Vee GND-o.3 GND-o.3 Vee Vee 0.2 Vee 0.2 Vee 1.5 2.1 1.1 1.7 V V -1 -1 25 25 1 1 10 10 <1 <1 mV mV J.IA J.IA 1 1 -45 -55 <1 <1 -20 -30 J.IA J.IA J.IA J.IA 3.3V 5.0V 3.3V 5.0V V012 Output Low Voltage VPJi Reset Input High Voltage VRI Reset Input Low Voltage VOFFSET III Comparator Input Offset Voltage Input Leakage 3.3V 5.0V 3.3V 5.0V IOl Output Leakage IIR Reset Input Current 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 0.6 004 -1 -1 VIN = OV, Vee VIN = OV, Vee VIN = OV, Vee VIN = OV, Vee 4-53 Z891201Z89920 16-Brr MIxED SIGNAL PROCESSOR PRELIMINARY AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram RlfW ) J( --®-- HD- PortO, 10M )f- ).~ 16 f.®.Port 1 3 ). 07- DO IN A7-AO - ~ ~ )<- lAS H>= kD- IDS (Read) Portl ls' 8 ----® A7-AO " ~ ) 07-00 OUT ~ --®- ,..... ~ Figure 50. External 110 or Memory ReadlWrite Timing 4-54 ~ I 7 IDS .1 '6' --®--(Write) -A>B 010 A>B>C all A>C>B 100 B>C>A 101 C>B>A 110 B>A>C 111 Reserved IR01, IR04 Priority (Group C) a IROI >IRQ4 1 IRQ4> IROI IRoo, IRQ2 Priority (Group B) a IR02 > IROO 1 IROO> IR02 IR03, IR05 Priority (Group A) o IR05 > IR03 1 IR03 > IR05 Reserved Figure 88. Interrupt Priority Register (F9H:Write Only) 4-66 Z891201Z89920 PRELIMINARY R25Q IRO 16·Brr MIXED SIGNAL PROCESSOR R253 RP Iwloolool~lool~lmIDOI IROQ IR01 IR02 IR03 IR04 IR05 P32 Input P33 Input P31 Input DSP TO T1 I 1 0 . . - 1- Expanded Register File Bank Working Register Group Figure 92. Register Pointer (FDH:ReadlWrite) Inter Edge P31 ~ P32~ =00 P31 ~ P32t =01 P31t P32~ =10 P31 U P32th 11 R254 SPH Figure 89. Interrupt Request Register (FAH:ReadlWrite) Iwloolool~lool~lmIDOI I Stack Pointer Upper Byte (SPS· SP15) R2511MR Figure 93. Stack Pointer High (FEH:ReadlWrite) 1 Enables IRQO·IR05 = IRQO) (DO 1 Enables RAM Protect 1 Enables Interrupts R255 SPL Iwloolool~lool~lmIDOI Figure 90. Interrupt Mask Register (FBH:ReadlWrite) I Stack Pointer Lower Byte (SPO • SP7) Figure 94. Stack Pointer Low (FFH:ReadlWrite) R252 FLAGS User Flag F1 User Flag F2 Half carry Flag Decimal Adjust Rag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 91. Flag Register (FCH:ReadlWrlte) 4·67 Z8912OJZ89920 PRELIMINARY 16-Brr MIxED SIGNAL PROCESSOR Z81NSTRUCTION SET NOTATION Addressing Modes. The following notation is used to describe the addressing modes and instruction operations as shown in the instruction summary, Symbol Meaning IRR Indirect register pair or indirect workingregister pair address Indirect working-register pair only Indexed address Direct address Relative address Immediate Register or working-register address Working-register address only Indirect-register or indirect working-register address Indirect working-register address only Register pair or working register pair address Irr X DA RA 1M R r IR Ir RR Symbols. The following symbols are used in describing the instruction set. Symbol Meaning dst src cc Destination location or contents Source location or contents Condition code Indirect address prefix Stack Pointer Program Counter Flag register (Control Register 252) Register Pointer (R253) Interrupt mask register (R251) @ SP PC FLAGS RP IMR 4-68 Flags. Control register (R252) contains the following six flags: Symbol Meaning C Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Z S V D H Affected flags are indicated by: o 1 x Clear to zero Set to one Set to clear according to operation Unaffected Undefined .2il.JJG PRELIMINARY Z891201Z89920 16-Brr MIXED SIGNAL PRocEssOR CONDITION CODES Value Mnemonic Meaning Flags Set 1000 0111 1111 0110 1110 C NC Z NZ Always True Carry No Carry Zero Not Zero C=1 C=O Z=1 Z=O 1101 0101 0100 1100 0110 PL MI OV NOV EQ Plus Minus Overflow No Overflow Equal 8=0 8=1 V=1 V=O Z=1 1110 1001 0001 1010 0010 NE GE LT GT LE Not Equal Greater Than or Equal Less than Greater Than Less Than or Equal Z=O (8 XOR V) = 0 (8 XOR V) = 1 [Z OR (8 XOR V)] = 0 [Z OR (8 XOR V)] = 1 1111 0111 1011 0011 0000 UGE ULT UGT ULE Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Never True C=O C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 4-69 Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY INSTRUCTION FORMATS OPC dst CCF. DI. EI. IRET. NOP. RCF. RET. SCF OPC One-Byte Instructions ORl1110 OPC I lOR 1111 0 I dst CLR. CPL. DA. DEC. DECW. INC. INCW. dsvsrel POP. PUSH. RL. RLC. RR. RRC. SRA. SWAP I OPC MODE sre OR dst OR ADC. ADD. AND. CPo LD. OR. SBC. SUB. TCM. TM.XOR JP. CALL (Indirect) dst I MODE OPC dst OPC ORI 1110 I dst ADC. ADD. AND. CPo LD. OR. SBC. SUB. TCM. TM.XOR VALUE SRP VALUE J OPC MODE ADC. ADD. AND. CPo OR. SBC. SUB. TCM. TM.XOR LD. LDE. LDEI. LDC. LDCI LD sre OR dst OR MODE dsVsre I I OPC LD x ADDRESS OR 1111 0 I LD I co sre OPC JP DAU LD I L dsVCC OPC opc DJNZ. JR CALL DAU DAL FFH 6FH DAL STOP/HALT 7FH Two-Byte Instructions Three-Byte Instructions INSTRUCTION SUMMARY Note: Assignment of a value is indicated by the symbol " f- ". For example: dst f- dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. The 4-70 notation "addr (n)" is used to refer to bit (n) of a given operand location. For example: dst (7) refers to bit 7 of the destination operand. -- ----~~~ ftl2lUE -- Z891201Z89920 16-Brr MIxED SIGNAL PROCESSOR PRELIMINA R Y INSTRUCTION SUMMARY (Continued) Instruction and Operallon Address Moda dst sre Flags Affacted Opcoda Byte (Hax) C Z S V D H ADC dst, src dstf--dst + src + C t 1[1 ADD dst, src dstf--dst +src t O[ I AND dst, src dstf--dst AND src t 5[ I CALLdst SPf--SP-2 @SPf--PC, PCf--dst DA IRR CCF Cf--NOT C ****0 * ****0 * - **0 INC dst dstf--dst + 1 D6 D4 - - - - - - EF *- - IRET FLAGSf--@SP; SPf--SP + 1 PCf--@SP; SPf--SP + 2; IMR(7)f--1 - CLR dst dstf--O R IR BO B1 - - COMdst dst f--NOT dst R IR 60 61 - CPdst, src dst-src t A[ I DAdst dstf--DA dst R IR 40 41 DECdst dstf--dst -1 R IR 00 01 - DECWdst dstf--dst-1 RR IR 80 81 - 8F - - - - rA r=O-F ---- DI IMR(7)f--O DJNZdst rf--r-1 Ifr;loO PCf--PC + dst Range: +127, -128 RA Instruction and Oparallon - **0 ****- ***X- - INCWdst dstf--dst + 1 Address Moda dst sre Opcode Flags Affectad Byta (Hax) C Z S V D H - R IR rE r=O-F 20 21 RR IR AD A1 - BF EI IMR(7)f--1 9F ---- - - HALT 7F ----- - cB c=O-F - - - - - - - X r Ir r R IR 1M 1M R rC r8 r9 r=O-F C7 07 E3 F3 E4 E5 E6 E7 F5 Irr C2 - - - - Irr C3 ------ JR ce, dst if cc is true, PCf--PC +dst Range: +127, -128 RA LD dst, src dstf--src r r R 1m R r X r Ir R R R IR IR LDCI dst, src dstf--src rf--r+1; rrf--rr + 1 IRR Ir - - - - - - DA LDC dst, src *** ****** cD c=O-F 30 JP cc, dst if cc is true PCf--dst ***- ***-- ***- - --- - - 4-71 ~2il..CJG Z891201Z89920 16·Brr MIXeD SIGNAL PRoceSSOR P R fLIM/NARY INSTRUCTION SUMMARY (Continued) Address ModI! dsl src Instruction and Operallon NOP Opcode Flags Affected Byte (Hex) C Z S V D H FF - - - * *" 0 - STOP OR ds!, src dst(-dst OR src t 4[ J - POP dst dst(-@SP; SP(-SP + 1 R IR 50 51 - - - - - - - - 70 71 - RCF C(-O CF 0 - - RET PC(-@SP; SP(-SP + 2 AF R IR of.J RlC dst l&47 o~ RR dst 4Il y7 o~ RRC dst 49:H7 o~ SBC dst, src dst(-dst(-srcf-C SRA dst ~ 4-72 - - - - - - - - - - - 2[ J SWAP dst R IR FO F1 ****1 * X **X TCM ds!, src (NOT dst) AND src t 6[ J - **0 TM dst, src dst AND src t 7[ J - **0 5[ J - X X X B[ J - - - - - 2:3 oI XOR dst, src dst(-dst XOR src t - - **0 R IR 90 91 ****- - R IR 10 11 ****- - R IR EO E1 ****-- t These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a'[ ]' in this table, and its value is found in the following table to the left of the applicable addressing mode pair. R IR CO C1 - For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13. t 3[ J **** * DF 1 SCF C(-1 SRP src RP(-src - - 6F t WDT Rl dst ~7 - Opcode Flags Affected Byte (Hex) C Z S V D H SUB dst, src dSI(-dsl(-src 17 PUSH src SP(-SP -1; @SP(-src Address Mode dst src Instruction and Operation R IR DO D1 1m 31 ****- - - - - - Lower Opcode Nibble [2] - ***0 - Address Mode dst src Ir [3] R R [4] R IR [5] R 1M [6] IR 1M [7] Z891201ZB9920 PRELIMINARY 16-BIT IotxED SIGNAL PRocEssoR OPCODEMAP Lower Nibble (Hex) o o 2 3 4 5 6 A a C o E F 6.5 DEC R1 6.5 RLC R1 6.5 INC R1 8.0 JP IRR1 8.5 OA R1 10.5 pop 6.5 Dec IR1 6.5 RLC IR1 6.5 INC IR1 61 SRP 1M 8.5 OA IR1 10.& 3 4 5 6.5 ADD 11,12 65 AOC '1, ,2 65 sua '1, ,2 6.5 sac 6.5 ADD 10.5 ADD R2, R1 105 AOC R2, R1 105 sua R2,R1 105 sac R2, R1 10.5 OR R2,R1 10.5 AND R2, R1 10.5 TCM R2, R1 105 TM R2, R1 10.5 ADD IR2, R1 10.5 AOC IR2, R1 105 sua IR2, R1 10.5 sac IR2, R1 10.5 OR IR2, R1 10.5 AND IR2, R1 10.5 TCM IR2, R1 10.5 TM IR2, R1 '1, ,2 6.5 OR '1, ,2 6.5 AND '1, ,2 6.5 TCM pop R1 IR1 6.5 6.5 COM COM R1 IR1 '1,12 10/12.1 12/14.1 6.5 PUSH PUSH TM R2 IR2 '1,12 10.5 10.5 12.0 OECW OECW LOE RR1 IR1 ,1 Irr2 6.5 6.5 120 RL RL LOE R1 IR1 ,21rr1 10.5 105 ·65 INCW INCW CP RR1 IR1 '1, ,2 6.5 6.5 65 CLR XOR CLR ,1,,2 R1 IR1 6.5 6.5 12.0 LOC RRC RRC R1 IR1 '1,1'12 6.5 12.0 6.5 SRA LOC SRA ,1,lrr2 R1 IR1 6.5 6.5 RR RR IR1 R1 8.5 8.5 SWAP SWAP IR1 R1 '1,1'2 6.5 AOC '1,1'2 6.5 sua '1,1'2 6.5 sac '1,1'2 6.5 OR '1,1'2 6.5 AND '1,1'2 6.5 TCM '1,1'2 6.5 TM '1,1'2 18.0 LOEI 1,1 Irr2 180 LOEI 112 Irr1 65 CP '1,1'2 6.5 XOR 7 6 2 8 10.5 10.5 6.5 ADD ADD LD R1,IM IR1,IM '1, R2 10.5 10.5 AOC AOC R1,IM IR1,IM 105 10.5 sua sua R1,IM IR1,IM 105 105 sac sac R1,IM IR1,IM 10.5 10.5 OR OR R1,IM IR1,IM 10.5 10.5 AND AND R1,IM IR1,IM 10.5 105 TCM TCM R1,IM IR1,IM 10.5 10.5 TM TM R1,IM IR1,IM 9 6.5 LD 12, R1 A a C 12/10.5 12/100 6.5 LO OJNZ JR ,1,RA ee, RA ,1,IM o E 12.100 JP ee, DA 6.5 INC ,1 F I--I--I--I--- r-so WOT r-so STOP ~ HALT ~ 01 r--s:1 EI 105 CP R2, R1 10.5 XOR R2, R1 105 CP IR2, R1 10.5 XOR IR2, R1 740 105 105 CP CP R1,IM IR1,IM 10.5 10.5 XOR XOR R1,IM IR1,IM 105 LO ,1.x,R2 20.0 10.5 CALL LO ,2,x,R1 DA 10.5 10.5 LO LO R1,IM IR1,IM '1,1'2 18.0 LOCI 1,1,lrr2 18.0 20.0 LOCI CALL· 1,1,lrr2 IRR1 6.5 105 105 LO LO LO ,1,IR2 R2, R1 IR2, R1 10.5 6.5 LO LO 1,1 ,2 R21R1 RET r-;so IRET rs:s RCF f--s:5 SCF rs:s r--s.o CCF NOP y y y 2 3 2 y 3 Bytes per Instruction Legend: Execution Cycles Pipeline Cycles Mnemonic First Operand Second Operand R =8-bit Address r 4-blt Address R1 or r1 = Ost Address R2 or r2 =Src Address = Sequence: Opcode, First Operand, Second Operand Nota: Blank areas not defined. ·2-byte instruction appears as a 3-byte Instruction 4-73 Z89l201Z89920 l6·Brr MIXED SIGNAL PROCESSOR PRELIMINARY DSP INSTRUCTION SET NOTATION Register Names. The following lists the register names and their descriptions. Name Description C Carry Equal (same as Z) False Interrupts Enabled Minus No Carry Not Equal (same as NZ) Not Interrupts Enabled Not Overflow Not User Zero Not User One Not zero Overflow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero Name Description EQ A Accumulator Bus Dummy Register Data Register where n is the register number (0 ... 3) and b is the bank in which is resides (0 .. 1). Extended Registers where n is the register number (0 .. 7). Multiplier Product Register Pointer Registers where n is the register number (0 ... 2) and b is the bank into which it points (0 ... 1). Multiplier Input Register X Multiplier Input Register Y Program Counter Register Status Reg ister IE MI NC NE NIE BUS Dn:b EXTn P Pn:b X Y PC SR F NOV NUO NUl NZ OV PL UO U1 UGE ULT Z Condition Codes. The following defines the condition codes supported by the DSP assembler. In the instruction descriptions, condition codes are referred to via the symbol. If the instruction description refers to a condition code in one of its addressing modes, the instruction will only execute if the condition is true. 4·74 Bank Switch Enumerations. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether a bank switch is set on or off. To more clearly represent this two keywords are used (ON and OFF) which state the direction of the switch. These keywords are refered to in the instruction descriptions through the symbol. PRELIMINARY Addressing Modes. This section discusses the syntax of the addressing modes supported by the DSP assembler. Symbolic Name Z891201Z89920 16·Brr MIXED SIGNAL PRocESSOR The symbolic name is used in the discussion of instruction syntax in the instruction descriptions. Syntax Description Pn:b Pointer Register (Points to RAM) Dn:b Data Register X,Y,PC,SR,P EXTn,A,BUS Hardware Registers (Points to Program Memory) @A Accumulator Memory Indirect Direct Address Expression # Word (16-bit) Immediate Value # Short (a-bit) Immediate Value (Points to RAM) @Pn:b @Pn:b-LOOP @Pn:b+LOOP Pointer Register Indirect Pointer Register Indirect with Loop Decrement Pointer register Indirect with Loop Increment (Points to Program Memory) @@Pn:d @Dn:b @@Pn:b-LOOP @@Pn:b+LOOP @@Pn:b+ Pointer Register Memory Indirect Data Register Memory Indirect Pointer Register Memory Indirect with Loop Decrement Pointer Register Memory Indirect with Loop Increment Pointer Register Memory Indirect with Increment 4-75 ~2iu:a; Z891201Z89920 PRELIMINARY 16·Brr MIXED SIGNAL PROCESSOR DSP INSTRUCTION DESCRIPTIONS Inst. Description Synopsis Operands ABS Absolute Value ABS[,ksrc> ,A A ADD Addition ADD, A, A, A, A, A, A, A, 1 1 1 2 1 1 1 1 2 3 1 1 1 A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 AND A,#128 AND A,DO:1 AND A,@@PO:D+LOOP AND A,@P2:1+ 2 2 2 2 CALL sub1 CALL Z,sub2 AND Bitwise AND AND, Words Cycles Examples ABS NC,A ABSA 1 ADD A,#128 ADD A,DO:1 ADD A,@@LOOP ADD A,@P2:1+ ADD A,X AND A,X CALL Subroutine call CALL [,kaddress> , CCF Clear carry flag CCF None CCF ClEF Clear Carry Flag ClEF None ClEF COPF Clear OP flag COPF None COPF CP Comparison CP, A, A, A, A, A, A, DEC Decrement DEC [.l A, A DEC NZ,A DECA INC Increment INC [.J ,A A INC NZ,A INCA JP Jump JP [.l
, 4·76 1 1 3 1 1 1 2 2 2 2 CP A,PO:O CP A,D3:1 CP A,#512 CPA,@@PO:1 CP A,LABEL CPA,@DO:D CP A,X JP NIE,Label JP Label Z891201Z89920 16·Brr MIXED SIGNAL PRocESSOR PRE L I MIN A R Y Inst. Description Synopsis Operands LO Load destination with source LO, A, A, A, A, A, A, ,A , , , , , , , , , , , , Words Cycles Examples 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 LOA,X LOA,OO:O LO A,PO:1 LOA,@@P1:1 LO A,MEMAOOR LO MEMAOOR,A LO 00:1 ,A LO P1:0'128 LOP1:1,X LO@PO:O+LOOP,'1234 LO@P1:1+,X LO X,PO:O LO Y,PO:O LO SR,I%1023 LO PC,(A) LOX,@@PO:O LD Y,@P1:D-LOOP LOSR,X Note: When is , cannot be P. Note: When is and is , cannot be EXTn if is EXTn, cannot be X if is X, cannot be SR if is SR. Note: When is cannot be A. MLO Multiply MLO,[,] , ,, , ,, MLOA@PO:O MLO A@P1:0,OFF MLO @P1:1,@P2:0 MLO @PO:1,@P1:0,ON Note: If src1 is it must be abank 1 register. Src2's for src1 cannot be X. Note: For the operands , the defaults to OFF. For the operands , the defaults to ON. MPYA Multiply and add MPYA ,[,] , ,, , ,, MPYAA@PO:O MPYA A,@P1:0,OFF MPYA@P1:1,@P2:0 MPYA@PO:1 ,@P1:0,ON Note: If src1 is it must be abank 1 register. Src2's must be abank 0 register. Note: for src1 cannot be X. Note: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. 4-77 .2iLCJG Z891201Z89920 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY DSP INSTRUCTION DESCRIPTIONS (Continued) Inst. Description MPYS Multiply and subtract Synopsis Operands Words Cycles Examples MPYS A,@PO:O MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS@PO:1,@P1:0,ON MPYSL1 , ,, , ,, Nole: If src1 is it must bea bank 1register. Src2's must be a bank 0 register. Note: for src1 cannot be X. Note: For the operands , the defaults to OFF. For the operands , the defaults to ON. NEG Negate NEG ,A , A A NEG NZ,A NEGA NOP No operation NOP None NOP OR Bitwise OR OR , A, A, A, A, A, A, A, POP Pop value from stack POP PUSH Push value onto stack PUSH RET Return from subroutine RET None RL Rotate Left RL ,A ,A A RL NZ,A RLA RR Rotate Right RR ,A ,A A RR NZ,A RR A 4-78 1 1 2 1 1 1 1 1 1 2 3 1 1 1 OR A,#128 ORA,DO:1 OR A,OOPO:O+LOOP ORA,@P2:1+ ORA,X POP PO:O POP 00:1 POP@PO:O POPA POP BUS 1 1 1 1 2 1 1 1 1 1 1 2 3 3 PUSH PO:O PUSH 00:1 PUSH@PO:O PUSH A PUSH BUS PUSH #12345 PUSH@A PUSHOOPO:O 2 RET -------- - - - - - - ----- ~2iu:a; Z891201Z89920 16-B/r MIxED SIGNAL PRocEssoR P R ELIMINARY Inst. Description Synopsis Operands SCF Set Cflag SCF None SCF SIEF Set IE flag SIEF None SIEF SLL Shift left logical SLL [,]A A SLL NZ,A SLL A SOPF Set OP flag SOPF None SOPF SRA Shift right arithmetic SRA,A ,A A SRANZ,A SRAA SUB Subtract SUB, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 A, A, A. A. A, A, A, 1 1 2 1 1 1 1 XOR Bitwise exclusive OR XOR , BankSwHch Enumerations. The third (optional) operand of the MLD. MPVA and MPVS instructions represents whether a bank switch is set on or off. To more clearly represent this two keywords are used (ON and OFF) which Words Cycles 1 1 2 3 1 1 1 1 1 2 3 1 1 1 Examples SUBA,'128 SUBA,DO:1 SUB A,@@PO:!l+LOOP SUB A,@P2:1+ SUBA,X XORA,'128 XORA,DO:1 XOR A,@@PO:O+LOOP XORA,@P2:1+ XORA,X state the direction of the switch. These keywords are referred to in the instruction descriptions through the symbol. 4-79 Z891201Z89920 PRELIMINARY 16-Brr MIXED SiGNAL PROCESSOR PACKAGE INFORMATION D 45' '", , 1 01 1 61 "2, ~ 71 ---sJ¥ "314J.f \ "2,~ 1 OFH ooK 0 * RESET CONDITION REGISTER GROUP 0 (0) u u u (F) OFH WOTMR (F) OEH Reserved (F)OOH Reserved (F)OCH OSPCON 0 0 U 1 U U U U (F)OBH SMA 0 0 1 0 0 0 U 0 (F)OAH Reserved (F)09H Reserved (F) 08H Reserved (F)07H Reserved (F) 06H P45CON U U U U 0 1 1 , U P5M , U (F) 05H 1 1 1 1 (F) O4H P5 U U U U U U U U (F)OSH P4M 1 1 1 1 1 1 1 1 (F)02H P4 U U U U U U U U (F)OlH Reserved (F)ooH peON 0 0 0 0 0 0 U U 0 0 1 Z8 EXPANDED REGISTER BANK (B) za-osp Mailbox Interface J (AO .. A1S) ZS EXPANDED REGISTER BA!NK (A) ze STANDARD REGISTER BANK REGISTER GROUP 0 * * * * (0) RESET CONDITION (A)OOH ARAM_Data u u u u u u u (A)OlH ARAM_Control 0 0 0 0 0 0 0 (0) 03H PS 1 1 1 1 U U U U (A)02H MOST SB U U U U U U U U (0) O2H P2 U U U U U U U U (A)03H MIDDLE_SB U U U U U U U U (O)OlH p, U U U U U U U U (A)04H LEAST S8 U U U U U U U U (O)ooH PO U U U U U U U U (A)05H Refresh_Count 0 0 0 0 0 0 0 0 U = Unknown t * = For ROMless mode, RESET Condition 10110110 Will not be Reset with a Stop-Mode Recovery Figure 14. Expanded Register File Architecture 5-20 u 0 Z891211Z89921 PRELIMINARY Interrupts. The Z8 has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 15). The six sources are divided as follows; three sources are claimed by Port 3 lines P33-P31, two by 16·811 MIXED SIGNAL PROCESSOR counter/timers, and one by the DSP (Table 4). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. IROO IR02 IR01, 3, 4, 5 Interrupt Edge Select IRO Register (D6, D7) 6 Interrupt Request Vector Select Figure 15. Interrupt Block Diagram Table 4. Interrupt Types, Sources, and Vectors Name Source IROO IR01 IR02 /DAVO, P32 /DAV1, P33 /DAV2, P31, TIN IR03 IR04 IR05 IR03 TO TI Vector Location 0, 1 2,3 4,5 6, 7 8,9 10, 11 Comments External (P32), Programmable Rise or Fall Edge Triggered External (P33), Fall Edge Triggered External (P31), Programmable Rise or Fall Edge Triggered Internal (DSP activated), Fall Edge Triggered Internal Internal 5-21 ~2iUJG Z891211Z89921 PRELIMINARY 16-81T MIXED SIGNAL PROCESSOR ZS FUNCTIONAL DESCRIPTION (Continued) When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. This disables all subsequent interrupts, pushes the Program Counter and Status Flags to the stack, and then branches to the program memory vector location reserved for that interru pt. All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the i6-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request Register is polled to determine which of the interrupt requests needs service. An interrupt resulting from ANi is mapped into IR02, and an interrupt from AN2 is mapped into IROO. Interrupts IR02 and IROO may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Table 5. IRQ Register IRQ interrupt Edge D7 D6 P31 o o 1 1 o F F R 1 1 R/F o C2~ The crystal is connected across XTAL 1 and XTAL2 using capacitors from each pin to ground. ...--..--1 XTAL 1 -otlD-oooI XTAL1 ...-~--1 XTAL2 LC Figure 16. Oscillator Configuration 5·22 XTAL2 C2~ Ceramic Resonator or Crystal F R/F Clock. The Z89121/921 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL 1 =Input, XTAL2 =Output). The crystal should be AT cut, 20.48 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The system clock (SCLK) is one half the crystal frequency (Figure 16). L r-~--I XTAL2 R Notes: F = Falling Edge R =Rising Edge Programming bits for the Interrupt Edge Select is located in the IRO Register (R250), bits D7 and D6. The configuration is shown in Table 5. r--..--I XTAL 1 P32 F External Clock Z891211Z89921 16-Brr MIxED SIGNAL PROCESSOR PRELIMINARY CounterlTimers. There are two 8-bit programmable counter/timers (TO-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the TO prescaler is driven by the internal clock only (Figure 17). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of the count, a timer interrupt request, IR04 (TO) or IR05 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided-by-four, or an external signal input through Port 31. The Timer Mode register configures the external timer inplJt (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers can be cascaded by connecting the TO output to the input ofT1. DSPClock Internal Data Bus Initial Value Initial Value 6-BIt Down Counter Down Counter CUrrent Value IRQ4 Clock TOUT P36 Internal Clock Gated Clock Triggered Clock 6-Blt Down 8-BIt Down PRE1 Initial Value T1 Initial Value IROS T1 TIN P31 Internal Data Bus Figure 17. CounterlTlmer Block Diagram 5-23 ~~-~--~-------.-".--- .. - .---~-~--- ------". ~-. Z891211Z89921 PRELIMINARY 16·BIT MIXED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) Port Configuration Register (PCON). The PCON register configures each port individually; comparator output on Port 3, and open-drain on Port 0 and Port 1. The PCON register is located in the Expanded Register File at bank F, location OOH (Table 6). Comparator Output Port 3 (00). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P35, and a 0 releases the Port to its standard I/O configuration. Port 0 Open-Drain (01). Port 0 can be configured as an open-drain by resetting this bit (01 = 0) or configured as push-pull active by setting this bit (01 = 1). The default value is 1. Port 1 Open-Drain (02). Port 1 can be configured as an open-drain by resetting this bit (02 = 0) or configured as push-pull active by setting this bit (02 = 1). The default value is 1. Table 6. Port Configuration Register (PCON) (F) OOH Register PCON (F)%OO Position Attrib. Value Description 76543-------2-- R ------1- R -------0 R 0 1 0 1 0 1 Reserved Port 1 Open-drain Port 1 Push-pull Active" Port 0 Open-drain Port 0 Push-pull Active" P34, P35 Standard Output" P34, P35 Comparator Output Note: • Default setting after Reset Port 4 and 5 Configuration Register (P45CON). The P45CON register configures Port 4 and Port 5, individually, to open-drain or push-pull active. This register is located in the Expanded Register File at Bank F, location 06H (Table 7). Port 5 Open-Drain (04). Port 5 can be configured as an open-drain by resetting this bit (04 = 0) or configured as push-pull active by setting this bit (04 = 1). The default value is 1. Port 4 Open-Drain (00). Port 4 can be configured as an open-drain by resetting this bit (00 = 0) or configured as push-pull active by setting this bit (00 = 1). The default value is 1. Table 7. Port 4 and 5 Configuration Register (F) OSH [Write Only] Register P45CON {F)%06 Position Attrib. Value 765-321---4---- w o -------0 w o 1 1 Note: • Default setting after Reset 5-24 Description Reserved Port 5 Open-drain Port 5 Push-pull Active" Port 4 Open-drain Port 4 Push-pull Active" Z891211Z89921 16-8rr MIXED SIGNAL PROCESSOR PRELIMINARY Power-On Reset (PaR). A timer circuit clocked by a dedicated on-board RC oscillator is used forthe Power-On Reset (PaR) timer function. The paR time allows Vee and the oscillator circuit to stabilize before instruction execution begins. The paR timer circuit is a·one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status. 2. STOP-Mode Recovery (if D5 of SMR = 1). 3. WDT time-out. The paR time is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the paR timer is bypassed after STOP-Mode Recovery (typical for external clock, RC/LC oscillators). HALT. HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IROO, IR01, IR02, and IR03 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. a reset only, either by WDT time-out, paR, SMR recovery or external reset. This causes the processor to restart the application program at address OOOCH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in midinstruction. To do this, the user must execute a Nap (opcode = FFH) immediately before the appropriate Sleep instruction, Le.; FF Nap .; clear the pipeline 6F STOP ; enter STOP mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT mode STOP-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of STOP-Mode Recovery (Table 8). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a Low level or a High level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, or the SMR register, specify the source of the STOP-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the WDT. The SMR is located in Bank F of the Expanded Register Group at address OBH. STOP. This instruction turns off the internal clock and external crystal oscillation. It reduces the standby current to 10 ~ (typical) or less. the STOP mode is terminated by Table 8. Stop-Mode Recovery Register (SMR) (F) OBH Register SMR(F)%OB Position Attrlb. Value Description 7------- R o paR" Stop Recovery Low Stop Recovery Level" High Stop Recovery Level Stop Delay On" Stop Delay Off STOP-Mode Recovery Source paR Only" Reserved P31 P32 P33 P27 P2 NOR 0-3 P2NOR 0-7 Reserved SCLK/TCLK Not Divide-by-16t SCLK/TCLK Divide-by-16 1 -6------ W --5----- W ---432-- W o 1 o 1 000 001 010 011 100 101 110 111 ------1-------0 W o 1 Notes: • Default setting after Reset t Reset after STOP-Mode Recovery 5-25 PRELIMINARY SCLKlTCLK divlde-by-16 Select (00). 00 of the SMR controls a divide-by-16 prescaler of SCLK[TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). Z891211Z89921 16-Brr MIXED SIGNAL PROCESSOR STOP-Mode Recovery Source (02, 03, and 04). These three bits of the SMR specify the wake-up source of the STOP recovery (Figure 18 and Table 9). SMR 040302 0 0 ~ voo SMR 04 03 02 SMR 04 03 02 010 100 o 1 1 P31 P32 P33 SMR D4 03 02 101 SMR D4 03 02 1 1 0 SMR D4 03 D2 1 1 1 P27 Stop Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 P33 From Pads DigitaVAnalog Mode Select (P3M) Figure 18. STOP-Mode Recovery Source Table 9. STOP-Mode Recovery Source SMR:432 D4 D3 D2 o o o o o o 1 1 o o 1 1 o 1 o 1 o 1 o 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through"P23 Logical NOR of P20 through P27 STOP-Mode Recovery Delay Select (05). This bit, if High, disables the 5 ms /RESET delay after STOP-Mode Recovery. The default configuration of this bit is one. If the "fast" wake up is selected, the Stop-Mode Recovery source is kept active for at least five TpC. STOP-Mode Recovery Edge Select (06). A 1 in this bit position indicates that a High level on anyone of the recovery sources wakes the Z89121/921 from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR (Table 9). 5-26 Cold or Warm Start (07). This bit is set by the device upon entering STOP mode. It is active High, and is 0 (cold) on PORIWOT /RESET. This bit is read only. It is used to distinguish between cold or warm start. DSP Control Register (OSPCON). The OSPCON register controls various aspects of the Z8 and the OSP. It can configure the internal system clock (SCLK) or the Z8, RESET, and HALT of the OSP, and control the interrupt interface between the Z8 and the OSP (Table 10). Z81RQ3 (00). This bit, which causes the Z8 interrupt, can be set by the OSP by writing bit 9 of ICR. Z8 has to set th is bit after serving the IR03 interrupt. The OSP can poll the status of IR03 by reading ICR bit 9. DSP INT2 (01). This bit is linked to OSP interrupt (INT2). It can be set by the Z8. After serving INT2, the OSP has to write a 1to an appropriate bit in ICR (EXT4) to clear the IRO. Reading this bit reflects the status of INT2 of the OSP. Z891211Z89921 16-Bn' MIxED SIGNAL PRocEssoR PRELIMINARY Table 10. DSP Control Register (F) OCH [ReadlWrlte] Field DSPCON(F)OCH Position Attrlb. Value Label Z8_SCLK 76------ R/W 00 01 lx DSP_Reset --5----- R W 2.5 MHz (OSC/8) 5 MHz (OSC/4) 10 MHz (OSC/2) Return '0' No effect Reset DSP HalLDSP Run_DSP DSP_Run ---4---- Reserved ----32-- IntFeedback 0 1 0 1 xx R/W ------1- R 'W -------0 1 0 R W DSP RUN (D4). This bit defines the HALT mode ofthe DSP. If this bit is set to 0, then the DSP clock is turned off to minimize power consumption. After this bit is set to 1, then the DSP will continue code execution from where it was halted. After a hardware reset, this bit is reset to 1. DSP RESET (D5). Setting this bit to 1 will reset the DSP. If the DSP was in HALT mode, this bit is automatically preset to 1. Writing a 0 has no effect. 1 0 Return '0' No effect FB_OSP_INT2 Set DSP_INT2 No effect FB.-Z8_IRQ3 Clear IRQ3 No effect Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WOT instruction. The WOT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL 1 pin. The paR clock source is selected with bit 4 of the WDT register (Table 11). The WDT affects the Z (Zero), S (Sign), and V (Overflow) flags. Z8 SLCK (06-07). These bits define the SCLK frequency of the Z8. The oscillator can be either divided-by-8, 4, or 2. After a reset, both of these are defaulted to 00. Table 11. Watch-Dog Timer Mode Register (F) OF Register WDTMR (F)%OF Position Attrlb Value ---4---- R/W ----3--- R/W -----2-- R/W 0 1 0 1 0 1 ------10 R/W 765----- 00 01 10 11 Description Reserved On-Board RC for WOT* XTAL forWDT WOT Off Ouring STOP WDT On During STOp· WDT Off During HALT WDT On During HALT· Int RC Osc Ext. Clock 256TpC 5ms 512 TpC· 15ms 1024 TpC 25ms lOOms 4096TpC Note: • Default setting after Reset 5-27 Z891211Z89921 PRELIMINARY 16·Brr MIxED SIGNAL PROCESSOR Z8 FUNCTIONAL DESCRIPTION (Continued) /RESET 4 Clock Filter Clear ........;;;;;;.... r-----ICLK 18 Clock RESET Generator RESET Internal RESET WDTSelect (WDTMR) CKSource Select (WDTMR) ------t-----+-C::~~~~~~ -----;f-......, XTAL - - - -............-1 CLR WDT/POR Counter Chain VDD 2V REF. From Stop Mode Recovery Source 12 ns Glitch Filter WDT------..I Stop Delay _ _ _ _ _ _ _ _ _ _ _-' Select (SMR) Figure 19. Resets and WOT WOTTimeSelect(OO, 01). SelectstheWOTtime period. It is configured as shown in Table 12. WOT Ouring HALT (02). This bit determines whether or not the WOT is active during HALT mode. A 1 indicates active during HALT. The default is 1. Table 12. WOT Time Select 01 00 0 0 1 1 0 1 0 1 Time-out of Internal RC OSC 5 ms 15 ms 25 ms 100 ms Notes: TpC ; XTAL clock cycle The default on reset is 15 ms. 5-28 min min min min Time-out of XTALciock 256TpC 512TpC 1024 TpC 4096TpC WOT Ouring STOP (03). This bit determines whether or not the WOT is active during STOP mode. Since XTAL clock is stopped during STOP mode, the on-board RC has to be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1. Clock Source for WOT (04). This bit determines which oscillator source is used to clock the internal POR and WOT counter chain. If the bit is ai, the internal RC oscillator is bypassed and the POR and WOT clock source is driven from the external pin, XTAL 1. The default configuration of this bit is 0 which selects the RC oscillator. Z891211ZB9921 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY DSP FUNCTIONAL DESCRIPTION The DSP coprocessor is characterized by an efficient hardware architecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply accumulate of two 16-bit operands. Most instructions are executed in one clock cycle. Four DSP registers (EXT3-EXTO) are shared through a quasi dual port mapping with the expanded register file of the Communication between the and the DSP occurs through these mailbox registers and interprocessor interrupt mechanism. za. za Outgoing Registers - (B)OO, (B)01 (B)02, (B)03 A r-- EXTO EXT1 I.. I.. EXT2 (B)04, (B)05 (B)06, (B)07 EXT3 Incoming Registers (B)08, (B)09 (B)OA, (B)OB EXTO A EXT1 40 ns. The user has to load a 23-bit address into the Least, Middle, and Most Significant Byte Registers and then write the 8-bit data to the Data Register. The data will be automatically separated into higher nibble and lower nibble and stored into two subsequent locations in the DRAM (2'Address for higher nibble and 2'Address+ 1 for lower nibble). Writing data to the Data Register with the Auto-incremental Bit (bit 0) of the DRAM Control Register equal to 0 increases the address in the Least Significant DRAM register (AH)04H by 1. Label Data See Text Data Data Data Data Most, Middle, and Least Significant Byte Registers. The 23-bit logical address of DRAM is stored in these three registers. Upon writing to these registers, the read cycle from DRAM is executed so that the new data is available in the data register. Refresh Count Register. The /RAS-only refresh cycle is transparent to the user and is supported by hardware logic. This register specifies how many rows of memory matrix, starting from the beginning of the DRAM (logical address OOOOOOH), should be refreshed. The number of the rows in DRAM to be refreshed is defined by the value in Refresh Count Register plus one and then multiplied by eight. 5-41 Z891211Z89921 PRELIMINARY 16·B!T MIXED SIGNAL PROCESSOR The basic timing diagram of the DRAM interface is shown in Figure 28. llil. IRAS ICAS RIW 1 1 1 1 1 1 1 1 : : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 :: : 1 1 1 1 1 1 : :: : : : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address 1 14------I.MI Read Cycle ~ 1 .1...1 1 Write Cycle Followed By Read Cycle 1l1li ~ Refresh Cycle 1 .1 AH • Address Hi (During !RAS) ALO • Address Lo (During ICAS) Bit 0 =0 AL 1 • Address Lo (During ICAS) Bit 0 = 1 RE • Refresh Address Figure 28. Timing Diagram for DRAM Interface 5-42 II1II l+-+I I Read Cycle ~ 1 ~ Z89121/Z89921 16-B1r MxED SIGNAL PRocEssoR PRELIMINARY DRAM Control Register The register defines DRAM access time, DRAM memory size, refresh operation, etc. (Figure 29). After Power-On Reset, the DRAM Control Register is set to %00, which defines 1 Mbit DRAM configuration with permanently active DRAM refreshing. Table 25_ DRAM Control Register Position Attrib. Value Description Access_Time 7------- ANI ARAM_size -6------ RNI Reserved --54---- RNI 0 1 0 1 %DD Refresh_start ----32-- RNI Refresh_clear ------1- R W 400ns 200 ns 1 Mbit 4 Mbit number These two bits can be used as User defined flags. Permanently Upon TO Upon TO Refresh off Return '0' Refresh clear No effect Increment ON Increment OFF Register Autoincrement -------0 RNI 00 01 10 11 1 0 0 1 Access_time. This bit defines the speed of DRAM Controller. The read/write cycle width can be changed to support slower DRAMs. When set to 1, the width of ICAS signal is set to 200 ns. Reset the Access_time bit to 0 set the width of ICAS signal to 400 ns. Blt6 ICAS DRAM_size. DRAM interface supports four different sizes of ARAM: 1 Mbit x 1, 1 Mbit x 4, 4 Mbit x 1 and 4 Mbit x 4. These require either 11- or 10-bit address bus. For 1 Mbit x 1 or 1 Mbit x 4 DRAM, the ADDR10 is used to generate select (/CAS) signal. Auto Increment. This bit specifies the Auto Increment of the LBS byte of the DRAM address. The Auto Increment function does not affect any flag of ZB. o 1 1st/CAS 1st ICAS 3rd/CAS 3rd/CAS 2nd ICAS 2nd ICAS Addr10 4th ICAS Z891211Z89921 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR DRAM Interface ~ ICAS I Data Transmitting Register Data Receiving Register + , ~ ~ I I I ff L I ~, ~~ I IL L ,-L I ,. DataMPX I DO D1 D2 D3 SelectMPX I ~ .. " " I I/CAS MPxl ~~~~ ~ ICAS u ,,. ,,. SEll SELO Al0 ",.,,. , " 'u, ",. ,., " Address MPX ~~~~~~~~~~ A9 AS A7 A6 A5 Figure 29. Block Diagram of the DRAM Interface 5-44 Least Significant Byte Register '- j ,,. ,,. Middle Significant Byte Register Most Significant Byte Register A4 A3 A2 A1 AO I Z89l2llZ8992l l6·Brr MIXED SIGNAL PRocESSOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Symbol Description Min. Max. Units Vee TSTG TA Supply Voltage (*) Storage Temp Oper Ambient Temp -0.3 -65° +7.0 +150° V C C t Notes: * Voltage on all pins with respect to GND. t See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS +SV The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive currant flows into the referenced pin (Figure 30). 2.1 kn From Output _ _ _....._ Under Test ...._-I~_.. Figure 30. Test Load Diagram CAPACITANCE TA = 25°C. Vee =GND =OV, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Max Input capacitance Output capacitance 110 capacitance 12 pF 12 pF 12 pF DC ELECTRICAL CHARACTERISTICS Symbol Icc ICCt 1CC2 l.,w Parameter Vee Nola [1J Supply Current HAlT Mode Current STOP Mode Current Output Current, -5V SUpply 5.0V 5.0V 5.OV TA • DOC 10 +7DoC Min Mu Typical 65 10 20 @25°C Units 40 rnA rnA 6 6 -20 -15 ~ rnA Hole: IllS.eN :l:O.5V 5-45 ------------ --- -------- -~-- ~2iUJG Z891211Z89921 P R ELIM/NARY 16·BIT MIXED SIGNAL PROCESSOR DC ELECTRICAL CHARACTERISTICS Sym Parameter TA = DOC to +70°C Note [3] Min Max Vee Max Input Voltage 3.3V 5.0V Clock Input High Voltage 3.3V 5.0V 0.7 Vee 0.7 Vee 7 7 Vee+O·3 Vee+O·3 Clock Input Low Voltage 3.3V 5.0V Input High Voltage 3.3V 5.0V GND-D.3 GND-D.3 0.7 Vee 0.7 Vee 0.2 Vee 0.2 Vee Vee+O·3 Vee+O·3 Vil Input Low Voltage VOH Output High Voltage GND-D.3 0.2 Vee GND-D.3 0.2 Vee Vee -0.4 Vee -0.4 VOl1 Output Low Voltage VOI.2 Output Low Voltage VI'Ii Reset Input High Voltage 3.3V 5.0V Reset Input Low Voltage 3.3V 5.0V VeH Vel VIH VRI 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V III Comparator Input Offset Voltage Input Leakage 3.3V 5.0V 3.3V 5.0V IOl Output Leakage 3.3V 5.0V 3.3V 5.0V VOFFSET I'R 5-46 Reset Input Current TA =-4DoC to +105°C Min Max 0.7 Vee 0.7 Vee 7 7 Vee+0.3 Vee+O·3 GND-D.3 GND-D.3 0.7 Vee 0.7 Vee Units Conditions 2.5 V V V V liN 250 uA liN 250 uA Driven by External Clock Generator Driven by External Clock Generator 0.2 Vee 0.2 Vee Vee+O·3 Vee+0.3 0.7 1.5 1.3 2.5 V V V V Driven by External Clock Generator Driven by External Clock Generator GND-D.3 0.2 Vee GND-D.3 0.2 Vee Vee -o.4 Vee -0.4 0.7 1.5 3.1 4.8 V V V V IOH=-2.0 mA IOH=-2.0 rnA 0.6 0.4 1.2 1.2 0.2 0.1 0.3 0.3 V V V V IOl =+4.0 mA IOl =+4.0 mA IOl = +6 rnA, 3 Pin Max IOl =+12 mA, 3 Pin Max 0.8 Vee 0.8 Vee GND-o.3 GND-o.3 Vee Vee 0.2 Vee 0.2 Vee 1.5 2.1 1.1 1.7 V V 25 25 2 2 10 10 <1 <1 mV mV ~ ~ 2 2 -60 -70 <1 ~ ~ ~ ~ 0.6 0.4 1.2 1.2 0.8 Vee 0.8 Vee GND-o.3 GND-o.3 Vee Vee 0.2 Vee 0.2 Vee -1 -1 25 25 1 1 -1 -1 -1 1 -1 -1 1 -1 -45 -55 Typical @25°C 1.3 <1 -20 -30 VIN = OV, Vee VIN = OV, Vee VIN = OV, Vee VIN = OV, Vee Z89l2l1Z8992l l6-Brr MIXED SIGNAL PROCESSOR PRELIMINARY AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram RlfW )] ( -®- -®Port 0, 10M )] )] 16 -@+ Port 1 3 ) A7-AO 07-00 IN - -0-- -®lAS } ~ ~ IDS (Read) 6 ~ --® .1 ~ 18 8 kD I ~ Port1 A7-AO )r ~ IDS (Write) 07-00 OUT , ~ ~ 7 t Figure 31. External UO or Memory ReadlWrlte Timing 5-47 .2il..tE Z89l2l1Z8992l l6-BIT MIXED SIGNAL PROCESSOR PRELIMINA R Y AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table Vee Nole (4) TA =DOC to +70°C No Symbol Parameter Units Notes 1 2 TdA(AS} TdAS(A} Address Valid to lAS Rise Delay lAS Rise to Address Float Delay 5.0 5.0 20 25 ns ns [2,3] [2,3] 3 4 TdAS(DR} TwAS lAS Rise to Read Data Req'd Valid lAS Low Width 5.0 5.0 30 ns ns [1,2,3] [2,3] 5 6 TdAZ(DS} TwDSR Address Float to IDS Fall IDS (Read) Low Width 5.0 5.0 0 105 ns ns [1,2,3] 7 8 TwDSW TdDSR(DR) IDS (Write) Low Width IDS Fall to Read Data Req'd Valid 5.0 5.0 65 ns ns [1,2,3] [1,2,3] 9 10 ThDR(DS) TdDS(A) Read Data to IDS Rise Hold Time IDS Rise to Address Active Delay 5.0 5.0 0 40 ns ns [2,3] [2,3] 11 12 TdDS(AS} TdR/W(AS) IDS Rise to lAS Fall Delay R//W Valid to lAS Rise Delay 5.0 5.0 25 20 ns ns [2,3] [2,3] 13 14 TdDS(R/W) TdDW(DSW) IDS Rise to RI/W Not Valid Write Data Valid to IDS Fall (Write) Delay 5.0 5.0 25 20 ns ns [2,3J [2,3] 15 16 TdDS(DW) TdA(DR) IDS Rise to Write Data Not Valid Delay 5.0 5.0 25 Address Valid to Read Data Req'd Valid ns ns [2,3] [1,2,3] 17 18 19 TdAS(DS) TdDl(DS) TdDM(AS) lAS Rise to IDS Fall Delay Data Input Setup to IDS Rise /OM Valid to lAS Fall Delay 5.0 5.0 5.0 35 50 20 ns ns ns [2,3] [1,2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4]S.OV ±O.SV Standard Test Load All timing references use 0.9 Vcc for a logic 1 and 0.1 Vcc for a logic O. 5-48 Min Max 150 55 180 PRELIMINARY Z891211Z89921 16-Brr MIXED SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram Clock TIN IRON Clock Setup 11 Slop Mode Recovery Source --------~~-.~~=~®-10r---------~]<~---Figure 32. Additional Timing 5-49 ~2iUlG Z891211Z89921 PRE L IMINARY 16-Srr MIXED SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS Additional Timing Table vee Note [5] TA = DOC to +7DoC Min Max No Symbol Parameter 1 2 TpC TrC,TfC Input Clock Period Clock Input Rise & Fall Times 5.0V 5.0V 48.83 3 4 TwC TwTinL Input Clock Width Timer Input Low Width 5.0V 5.0V 16 70 5 6 TwTinH TpTin Timer Input High Width Timer Input Period 5.0V 5.0V 3TpC 8TpC 7 8A TrTin, TfTin TwlL Timer Input Rise & Fall Timer Int. Request Low Time 5.0V 5.0V 70 88 9 TwlL TwlH Int. Request Low Time Int. Request Input High Time 5.0V 5.0V 3TpC 3TpC 10 Twsm STOP-Mode Recovery Width Spec 5.0V ns 11 Tost Oscillator Startup Time 5.0V 12 5TpC 5TpC 12 Twdt Watch-Dog Timer 5.0V 5.0V 5.0V 5.0V 5 15 25 100 ms ms ms ms Notes: [lJ Timing Reference uses 0.9 Vee for a logic 1 and 0.1 Vee for a logic O. [2J Interrupt request via Port 3 (P31-P33). [3] SMR-OS = O. [4] Reg. WOT. [S] S.OV ±O.SV 5-50 6 Units Noles ns ns [1] [1] ns ns [1] [1] [1] 100 ns ns [1] [1,2] [1] [1] [1] [3] 01 = 0, DO = 0 [4] 01=0,00=1[4] 01 = 1, DO = 0 [4] 01 = 1, DO = 1 [4] Z891211Z89921 16-Bn' MIxED SIGNAL PRocessoR PRELIMINARY AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In IDAV (Input) _----\~ ........................................................... ------\~ ........................................................... Data InValid Next Data In Valid Delayed DAV I'---IL......................... ~~ ................./ .. ROY (Output) Figure 33. Input Handshake Timing Data Out - - II---------------\~ -------------Data Out Valid Next Data Out Valid ____-J~----------------------------------------------------~~-_------------ IDAV (Output) " Delayed DAV ROY (Input) figure 34. Output Handshake nmlng 5·51 ~2il.CE Z891211Z89921 P R ELIMINARY 16-8rr MIXED SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS Handshake Timing Table vee Note (1) TA=DOC to +70°C Max Min No Symbol Parameter 1 2 TsDI(DAV) ThDI(DAV) Data In Setup Time Data In Hold Time 5.0V 5.0V 0 115 3 4 TwDAV TdDAVI(RDY) Data Available Width DAV Fall to RDY Fall Delay 5.0V 5.0V 110 5 TdDAVld(RDY) TdDO(DAV) DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay 5.0V 5.0V TcLDAVO(RDY) TcLDAVO(RDY) Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay TdRDYO(DAV) TwRDY TdRDYOd(DAV) RDY Fall to DAV Rise Delay RDYWidth RDY Rise to DAV Fall Delay 6 7 8 9 10 11 Note: [1]5.0V±0.5V 5-52 Units ns Data Direction ns IN IN ns ns IN IN 0 ns ns IN IN 5.0V 5.0V 25 0 ns ns OUT OUT 5.0V 5.0V 5.0V 115 80 ns ns 80 ns OUT OUT OUT 115 80 PRELIMINARY Z891211Z89921 16-8rr MIXED SIGNAL PRocESSOR Z8 EXPANDED REGISTER FILE REGISTERS Expanded Register Bank B Register Position AHrlb. Outgoing Reg. to DSP EXTO (High Byte) (B)%OO 76543210 R{W DSP EXTO. Bits D15-D8 Outgoing Reg. to DSP EXTO (Low Byte) (B)%01 76543210 R{W DSP EXTO. Bits D7-DO Outgoing Reg. to DSP EXT1 (High Byte) (B)%02 76543210 R{W DSP EXT1. Bits D15-D8 Outgoing Reg. to DSP EXT1 (Low Byte) (B)%03 76543210 R{W DSP EXT1. Bits 07-00 Outgoing Reg. to DSP EXT2 (High Byte) (B)%04 76543210 R{W DSP EXT2. Bits D15-D8 Outgoing Reg. to DSP EXT2 (Low Byte) (B)%05 76543210 R{W DSP EXT2. Bits D7-DO Outgoing Reg. to DSPEXT3 (High Byte) (B)%06 76543210 R{W DSP EXT3. Bits D15-D8 Outgoing Reg. to DSPEXT3 (Low Byte) (B)%07 76543210 R{W DSP EXT3. Bits D7-DO Value Description 5-53 PRELIMINARY Z891211Z89921 16-Brr MIxED SIGNAL PROCESSOR Z8 EXPANDED REGISTER FILE REGISTERS Expanded Register Bank B (Continued) 5-54 Register Position Attrib. Incoming Reg. to DSP EXTO (High Byte) (B)%08 76543210 R Value Description DSP EXTO, Bits D15-D8 Incoming Reg. to DSP EXTO (Low Byte) (B)%09 76543210 R DSP EXTO, Bits D7-DO Incoming Reg. to DSP EXT1 (High Byte) (B)%OA 76543210 R DSP EXT1, Bits D15-D8 Incoming Reg. to DSP EXT1 (Low Byte) (B)%OB 76543210 R DSP EXT1, Bits D7-DO Incoming Reg. to DSP EXT2 (High Byte) (B)%OC 76543210 R DSP EXT2, Bits D15-D8 Incoming Reg. to DSP EXT2 (Low Byte) (B)%OD 76543210 R DSP EXT2, Bits D7-DO Incoming Reg. to DSP EXT3 (High Byte) (B)%OE 76543210 R DSP EXT3, Bits D15-D8 Incoming Reg. to DSP EXT3 (Low Byte) (B)%OF 76543210 R DSP EXT3, Bits D7-DO ---------- -------- ft)2Ju::a; PRELIMINARY Z891211Z89921 1&.arr MIxED SIGNAL PRocessoR Expanded Register Bank F Register Position Attrlb. Value Description 76543-------2-- R ------1- R -------0 R 0 1 0 1 0 1 Reserved Port 1 Open-drain Port 1 Push-pull Active* Port 0 Open-drain Port 0 Push-pull Active* P34, P35 Standard Output" P34, P35 Comparator Output DSPCON (F)OCH ZB_SCLK 76------ R(W DSP_Reset --5----- PCON (F)%OO R W DSP_Run ---4---- Reserved ----32-- IntFeedback ------1- R(W 0 1 0 1 2.5 MHz (OSC/B) 5 MHz (OSC/4) 10 MHZ (OSC/2) Return '0' No effect ResetDSP HalLDSP Run_DSP xx W 1 0 Return '0' No effect FB_DSP_INT2 Set DSP-'NT2 No effect FB..,ZB_IR03 Clear IR03 No effect %NN Port 4 Data Register %FF W Returns %FF 0 Defines P4X as Output 1 Defines P4X as Input %NN Port 5 Data Register %FF Returns %FF 0 Defines P5X pin as Output 1 Defines P5X pin as Input R W -------0 00 01 1x 1 0 R P4 (F)%02 76543210 RNJ P4M (F)%03 76543210 R P5 (F)%04 76543210 R(W P5M (F)%05 76543210 R W P45CON (F)%06 765-321---4---- W -------0 r W 0 1 0 1 Reserved Port 5 Open-drain Port 5 Push-pull Active" Port 4 Open-drain Port 4 Push-pull Active" NoIe: • Default setting after Reset 5-55 ft)2iUJG Z891211Z89921 16-BIT MIXED SIGNAL PROCESSOR PRELIMINAR Y Z8 EXPANDED REGISTER FILE REGISTERS Expanded Register Bank F (Continued) Register Position Attrib. Value Description 7------- R -6------ W --5----- W 0 1 0 1 0 1 ---432-- W POR" Stop Recovery Low Stop Recovery Level" High Stop Recovery Level Stop Delay On" Stop Delay Off STOP-Mode Recovery Source POR Only" Reserved P31 P32 P33 P27 P2 NOR 0-3 P2 NOR 0-7 Reserved SCLK/TCLK Not Divide-by-16t SCLK/TCLK Divide-by-16 SMR (F)%OB 000 001 010 011 100 101 110 111 ------1-------0 W 0 1 765-------4---- RNI ----3--- RNI -----2-- RNI 0 1 0 1 0 1 ------10 RNI WDTMR (F)%OF 00 01" 10 11 Notes: • Default setting after Reset t Reset after STOP-Mode Recovery 5-56 Reserved On-Board RC for WDT" XTAL forWDT WDT Off During STOP WDT On During STOP" WDT Off During HALT WDT On During HALT" Int RC Osc Ext Clock 5ms 256TpC 512TpC 15 ms 1024 TpC 25ms 100ms 4096TpC ~2il..!lG Z891211Z89921 PRELIMINARY 16-BIT MIXED SIGNAL PROCESSOR Z8 CONTROL REGISTERS Register Position %FO 76543210 Attrib. Value Description Reserved TMR %F1 76------ RW 00 01 10 11 --54---- RW ----3--- R/W -----2-- R/W ------1- R/W -------0 R/W 00 01 10 11 0 1 0 1 0 1 0 1 ToUT Modes Not Used TO Out T10ut Internal Clock Out P36 TIN Modes External Clock Input Gate Input Trigger Input (Non-Retriggerable) Trigger Input (Retriggerable) Disable T1 Count Enable T1 Count No Effect Load T1 Disable TO Count Enable TO Count No Effect Load TO T1 %F2 76543210 R W %NN %NN T1 Current Value T1 Initial Value PRE1 %F3 765432-------1- W W 0 1 W 0 1 Prescaler Modulo (1-64 Dec) T1 Clock Source External Timing Input (TIN) Mode Internal Clock T1 Count Mode Single Pass Modulo-n %NN %NN TO Current Value TO Initial Value W 0 1 Prescaler Modulo (1-64 Dec) Reserved TO Count Mode Single Pass Modulo-n W 0 1 Defines P2X pin as Output Defines P2X pin as Input -------0 TO %F4 76543210 R W PREO %F5 765432-------1-------0 W P2M %F6 76543210 5-57 ~2iu:a; PRE L IMINAR Y Z891211Z89921 16-S1T MiXED SIGNAL PROCESSOR Z8 CONTROL REGISTERS (Continued) Register Position Attrib. Value Description --5----- W W ---43--- W -----2-- W ------1- W -------0 R/W 0 0 1 00 01 10 11 0 1 0 1 0 1 Reserved P30 = Input; P37 =Output P31 = Input (TIN); P36 =Output (TOUT)" P31 =/DAV2/RDY2; P36 =RDY2/1DAV2 P33 =Input; P34 =Output' P33 =Input; P34 =/DM P33 = Input; P34 =/DM P33 =/DAV1/RDY1; P34 =RDY1//DAVl P32 = Input; P35 =Output' P32 =/DAVO/RDYO; P35 =RDYO//DAVO P31, P32 Digital Mode P31, P32 Analog Mode Port 2 Open-drain' Port 2 Push-pull Active 76------ W P3M %F7 7-------6------ P01M %F8 00 01 1x --5----- W 0 1 ---43--- W 00 01 10 11 -----2-- W 0 1 ------10 W 00 01 1x Note: • Defaull setting after Reset. 5-58 ToUT Modes P04-P07 Mode Output Input' A15-A12 External Memory Timing Normal' Extended P10-P17 Mode Byte Output Byte Input' AD7-ADO High-Z AD7 -ADO, /AS, /DS/ R/W, A11-A8 A15-A12, If selected Stack Selection External Internal' POO-P03 Mode Output Input' All-A8 ~2iUJG P R E L I MIN A R Y Register Position Attrib. IPR %F9 76-------5----- W Value 0 1 -----1-- W 0 1 -----2-- W 0 1 ---43--0 W 000 001 010 011 100 101 110 111 IRO %FA 76------ RNI 00 01 10 11 ZS91211ZS9921 16-Brr MIXED SIGNAL PROCESSOR Description Reserved IR03, IR05 Priority (Group A) IR05> IR03 IR03> IR05 IROO, IR02 Priority (Group B) IR02> IROO IROO> IR02 IR01, IR04 Priority (Group C) IROl > IR04 IR04> IROl Interrupt Group Priority Reserved C>A>B A>B>C A>C>B B>C>A C>B>A B>A>C Reserved Inter Edge (R = Rising edge; F = Falling edge) P31 = F; P32 = F P31 = F; P32 = R P31 = R; P32 = F P31 = RF; P32 = RF IR05 = Tl IR04=TO IR03 = DSP IR02 = P31 Input IROl = P33 Input IROO = P32 Input --543210 RNI 7------- RNI -6------ RW --543210 RNI Flags %FC 7-------6-------5-------4-------3-------2-------1-------0 ANI ANI RNI RNI RNI ANI ANI ANI RP %FD 7654-------3210 ANI ANI %NO %ON Working Aegister Group Expanded Aegister File Bank SPH %FE 76543210 ANI %NN Stack Pointer Upper Byte SPL %FF 76543210 RNI %NN Stack Pointer Lower Byte IMR %FB 0 1 0 1 0 1 Disables Interrupts Enables Interrupts Disables RAM Protect Enables RAM Protect Disables IA05-IROO (DO = IAOO) Enables IR05-IROO Carry Flag Zero Flag Sign Flag Overflow Flag Decimal Adjust Flag Half Carry Flag User Flag F2 User Flag Fl 5·59 Z891211Z89921 PRELIMINARY 16-Brr MIXED SIGNAL PROCESSOR Z81NSTRUCTION SET NOTATION Addressing Modes. The following notation is used to Flags. Control register (R252) contains the following six describe the addressing modes and instruction operations as shown in the instruction summary. flags: Symbol Meaning IRR Indirect register pair or indirect workingregister pair address Indirect working-register pair only Indexed address Direct address Relative address Immediate Register or working-register address Working-register address only Indirect-register or indirect working-register address Indirect working-register address only Register pair or working register pair address Irr X DA RA 1M R r IR Ir RR Symbols. The following symbols are used in describing the instruction set. Symbol Meaning dst src cc Destination location or contents Source location or contents Condition code Indirect address prefix Stack Pointer Program Counter Flag register (Control Register 252) Register Pointer (R253) Interrupt mask register (R251) @ SP PC FLAGS RP IMR 5-60 Symbol Meaning C Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Z S V D H Affected flags are indicated by: o 1 x Clear to zero Set to one Set to clear according to operation Unaffected Undefined 4'2Ju:a; PRELIMINARY Z891211Z89921 16-Brr MIXED SIGNAL PRocEssoR CONDITION CODES Value Mnemonic Meaning Flags Set 1000 0111 1111 0110 1110 C NC Z NZ Always True Carry No Carry Zero Not Zero C=1 C=O Z=1 Z=O 1101 0101 0100 1100 0110 PL MI OV NOV EQ Plus Minus Overflow No Overflow Equal S=O S=1 V=1 V=O Z=1 1110 1001 0001 1010 0010 NE GE LT GT LE Not Equal Greater Than or Equal Less than Greater Than Less Than or Equal Z=o 1111 0111 1011 0011 0000 UGE ULT UGT ULE Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Never True C=O C=1 (C = 0 AND Z = 0) = 1 (C OR Z) 1 (SXORV) = 0 (SXORV) = 1 [Z OR (S XOR V») = 0 [Z OR (S XOR V») = 1 = 5-61 Z891211Z89921 PRELIMINARY 16·Brr MIXED SIGNAL PROCESSOR INSTRUCTION FORMATS OPC dst CCF, 01, EI, IRET, NOP, RCF, RET, SCF OPC One-Byte Instructions r---r---, OR I 1 1 1 0 L..._=;;';"_..I. CPL, DA, DEC, I dst/sre I CLR, DECW, INC, INCW, POP, PUSH, RL, RLC, . I MODE OPC . RR, RRC, SRA, SWAP I OPC I - - -d-s-t ---lOR I 1 1 1 0 I sre OR dst OR ADC, ADD, AND, cp, LD, OR, SBC, SUB, TCM, TM,XOR JP, CALL (Indirect) dst I MODE OPC dst OPC ORI 1110 1 dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM,XOR VALUE SRP VALUE I MODE ADC, ADD, AND, CP, OR, SBC, SUB, TCM, TM,XOR LD, LDE, LDEI, LDC,LDCI OPC LD sre OR dst OR MODE dstlsrc I I OPC LD x ADDRESS ..-_..,.._--, LD '--.....;=;.;........ oRllll0 I OPC JP DAU I OPC dst I co src LD DAL VALUE dst/CC OPC I OPC DJNZ,JR DAL RA FFH 6FH CALL DAU STOPIHALT 7FH Two-Byte Instructions Three-Byte Instructions INSTRUCTION SUMMARY Note: Assignment of a value is indicated by the symbol " ~ ". For example: dst ~ dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. The 5-62 notation "addr (n)" is used to refer to bit (n) of a given operand location. For example: dst (7) refers to bit 7 of the destination operand. ~2il!JG Z891211Z89921 16-Brr MIXED SIGNAL PROCESSOR PREL/MINAR y INSTRUCTION SUMMARY (Continued) Address Mode dst src Flags Affected Opcode Byte (Hex) C Z S V D H Instruction and Operation ADC dst, src dstf-dst + src + C t H] ****0 * INC dst dstf-dst + 1 ADD dst, src dstf-dst + src t O[ ] ****o * AND dst, src dstf-dst AND src t 5[ ] - CALL dst SPf-SP-2 @SPf-PC, PCf-dst DA IRR D6 D4 - - EF *- - - - - Instruction and Operation CCF Cf-NOT C INCWdst dstf-dst + 1 **0 - - - - CLR dst dstf-O R IR BO B1 - - - - COMdst dstf-NOT dst R IR 60 61 - **0 CP dst, src dst- src t A[ ] **** DAdsl dslf-OAdst R IR 40 41 ***X OEC dsl dslf-dsl-1 R IR 00 01 - *** DECWdsl dslf-dsl-1 RR IR 80 81 - *** 8F -- - - - - rA r=O-F -- - - - - 01 IMR(7)t-O DJNZdsl rH-1 if r;l!O PCf-PC +dsl Range: +127, -128 RA Address Mode dst src Opcode Flags Affected Byte (Hex) C Z S V D H - ***- - R IR rE r=O-F 20 21 RR IR AO A1 - *** BF ****** cD c=O-F 30 - - - - - - cB c=O-F - - - - - - - IRET FLAGSf-@SP; SPf-SP+ 1 PCf-@SP; SPf-SP +2; IMR(7)f-1 JP ce, dst if cc is true PCf-dst DA JR ce, dst if cc is true, PCf-PC +dst Range: +127, -128 RA LO dst, src dslf-src r r R 1m R r X r Ir R R R IR IR X r Ir r R IR 1M 1M R rC r8 r9 r=O-F C7 07 E3 F3 E4 E5 E6 E7 F5 Irr C2 Irr C3 IRR LOC dsl, src -- EI IMR(7)f-1 9F - - - - HALT 7F -- ---- LDCI dsl, src dstf-src rf-r+1; rrf-rr+ 1 Ir - - - - - 5-63 Z891211Z89921 l&oBIT MiXED SIGNAl. PROCESSOR PRELIMINARY INSTRUCTION SUMMARY (Continued) Instruction and Operation Address Mode dst src NOP Opcode Flags Affected Byte (Hex) C Z S V D H Instruction and Operation FF STOP - - - - Address Mode dst src Opcode Flags Affected Byte (Hex) C Z S V D H 5F - - - - OR dst, src dstf-dst OR src t 4[ ] SUB dst, src dstf-dstf-src t 2[ ] POP dst dstf-@SP; SPf-SP +1 R 50 51 SWAP dst IR R IR F1 TeM dst, src (NOT dst) AND src t 51] TM dst, src dstAND src t 7[ R IR PUSH src SPf-SP -1; @SPf-src 17 6°1 70 71 RCF Cf-O CF RET AF 0----- WDT PCf-@SP; SPf-SP +2 Rl dst ~ RlC dst ~ RR dst Lm c::rt:::IJJ RRC dst slIe dsl, src XOR dst, src 5[ ] - XXX S[ ] -**0 ****- - dstf-dst XOR src R IR 10 ****- - R IR EO El ****- - t These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a'[ ]' in this table, and its value is found in the following lable to the left althe applicable addressing mode pair. R CO IR C1 ****- - t 3[ j **** * DF 1 - 11 R DO D1 IR 5-64 -**0 90 91 SCF Cf-l SRP src RPf-src t 1 R IR dstf-dstf-srcf-C SRAdst FO 1m 31 ***0 For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13. Address Mode dst src Lower Opcode Nibble [2J Ir [3] R R [4] R IR [5] R 1M [6] IR 1M [7] Z89121JZ89921 16-B1T MIXED SIGNAL PRocEssoR PRELIMINARY OPCODEMAP Lower Nibble (Hex) o o 2 3 4 5 B 7 8 9 6.5 6.5 10.5 10.5 10.5 10.5 6.5 6.5 ADD ADD a C D E 12/10.5 12/100 65 12.10.0 6.5 DJNZ LD JP INC ee,DA rl A F 6.5 6.5 DEC DEC ADD ADD ADD ADD Rl 6.5 IRl 6.5 '1, r2 6.5 rl,lr2 6.5 R2, Rl 10.5 IR2, Rl 10.5 RLC RLC ADC ADC ADC ADC Rl 6.5 IRl 6.5 rl, r2 6.5 R2, Rl 10.5 IR2, Rl 10.5 Rl,lM IR1,IM 10.5 105 f--- INC INC sua rl,lr2 6.5 Rl 80 IRl 6.1 rl, r2 65 R2, Rl 10.5 IR2, Rl 10.5 RUM IR1.IM 105 105 f--- JP SRP sac rl,Ir2 6.5 Rl,IM IR1,IM 105 10.5 f--- sua sac sua sac LD Rl,IM IR1,IM rl, R2 10.5 105 ADC sua sua sac sac LD r2, Rl JR rl,RA ee, RA rl,IM f--- ADC sua sac IRRl 85 1M 85 rl, r2 65 rl,Ir2 6.5 R2, Rl 105 IR2, Rl 105 DA DA OR OR OR OR IRl 10.5 rl, r2 6.5 rl,lr2 6.5 5 Rl 10.5 pop POP AND AND AND AND AND AND Rl 6.5 IRl 6.5 rl, r2 65 rl,lr2 6.5 R2, Rl 10.5 IR2, Rl 105 Rl,IM 105 IR1,IM 105 COM COM TCM TCM TCM TCM TCM TCM r-soSTOP IRl Rl 10/12.1 12/14.1 rl, r2 6.5 rl,lr2 6.5 RUM 10.5 IR1, 1M 10.5 PUSH PUSH TM '7'0 TM rl, r2 12.0 rl,lr2 18.0 LDE LDEI .. j 7 'M R2 10.5 Z l 3 4 B e. 2 8 Q. :::I 9 A a C D E F IR2 10.5 DECW DECW RRl 6.5 IRl 65 RL RL Rl 10.5 IRl 105. OR R2, Rl IR2, Rl 105 10.5 TM TM EI LDEI r21rrl 6.5 Ir21rrl 65 10.5 10.5 CP CP CP CP R2, Rl IR2, Rl 105 105 rl, r2 6.5 rl,Ir2 6.5 CLR CLR XOR XOR XOR XOR Rl 65 IRl 6.5 '1. r2 12.0 rl,lr2 180 R2, Rl IR2, Rl RRC RRC LDC LDCI Rl 6.5 IRl 65 SRA SRA Rl 6.5 IRl 65 RR rl,Irr2 Irl,Irr2 18.0 12.0 LDC LDCI rl,lrr2 Irl,lrr2 65 LD IRl 10.5 10.5 CP CP ~ RET Rl,IM IR1,IM 105 10.5 XOR '16:0 IRET XOR Rl,IM IR1,IM 10.5 ~ LD RCF "s"5" 20.0 20.0 rl,x,R2 105 CALL· CALL LD IRRl 10.5 105 DA 105 r2,x,Rl 105 LD LD LD LD rl,IR2 R2, Rl IR2, Rl 105 65 SWAP SWAP Rl "s'1 "s'1 LDE IRl 65 IRl 85 HALT IR1,IM DI RRl 6.5 Rl 8.5 TM R2, Rl IR2, Rl Rl,IM rl Irr2 Irl Irr2 12.0 18.0 INCW INCW RR rs:o WDT Rl,IM IR1,IM 10.5 10.5 R2, Rl IR2, Rl 10.5 10.5 TM OR SCF ~ CCF Rl,IM IR1,IM I--siJ LD Irl r2 R21Rl y y 'Y 2 3 2 -V 3 Bytes per Instruction Execution Cycles Pipeline Cycles Mnemonic First Operand - NOP LD Second Operand Y Legend: R = 8-bit Address r = 4-blt Address R1 or r1 = Dst Address R2 or r2 = Src Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas not defined. ·2-byte Instruction appears as a 3-byte instruction 5-65 ---_._--------_._--.-.- --.--.~ .-.-.----. Z891211Z89921 16-Brr MIXED SIGNAL PROCESSOR PRELIMINARY PACKAGE INFORMATION A ~-------D--------~ I~--------DI--------~ NOT[SI L CllNTRlLLING DIMENSIONS , INCH a. LEADS ME ClPLANM WITHIN .oM IN. 3. DIHENSIIIN , .JIlL. INCH $YMBIL A AI DIE DIIEI D2 • Hn.LlIt£TER MIH 4.32 84-lead PlCC Package Diagram 5-66 MAX 4.:57 2.92 2M 30.35 3OJO I!9.2t 2'-41 27.9• 28.58 1.27 TYP INCH HIN MAX .170 .ISO JIS JOII 1.195 US5 LISe U50 UOO LI25 .050 TYP PRELIMINARY Z891211Z89921 16-81T MIXED SIGNAL PRocESSOR ORDERING INFORMATION Z89121 Z89921 20 MHz 84-Pin PLCC Z8912120VSC 20 MHz 84-Pin PLCC Z8992120VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Speed 20 = 20.48MHz Package V = Plastic Leaded Chip Carrier (PLCC) Temperature S = O°C to + 70°C Environment C = Plastic Standard Example: Z 89121 20 V S C ~ is a Z89121, 20.48 MHz, PLCC, O°C to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix 5-67 Z89320 16·Bit Mixed Signal Processor 189321 16.. Blt Mixed Signal Processor Support Product Information Superintegratlon™ Products Guide literature Guide and Third Party Support Inog Sales Offices Representatives &Distributors .2;1 la, PRELIMINARY PRODUCT SPECIFICATION Z89320 16-81T DIGITAL SIGNAL PROCESSOR FEATURES • 16-Bit Single Cycle Instructions • 16-Bit I/O Port • Zero Overhead Hardware Looping • 4K Words of On-Chip Masked ROM • 16-Bit Data • Three Vectored Interrupts • Ready Control for Slow Peripherals • Two Conditional Branch Inputs/Two User Outputs • Single Cycle Multiply/Accumulate (100 ns) • 24-bit ALU, Accumulator and Shifter • Six-Level Stack • IBM'" PC Development Tools • 512 Words of On-Chip RAM • Cost Effective 40-pin DIP Package GENERAL DESCRIPTION The Z89320 is a second generation, 16-bit, fractional, two's complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains 1 Kbyte of on-chip data RAM (two blocks of 256 16-bit words), 4K words of program ROM. Also, the processor features a 24~bit ALU, a 16 x 16 multiplier, a 24-bitAccumulator and a shifter. Additionally, the processor contains a six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of three pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true single cycle mUltiply. The device includes a 16-bit I/O bus for transferring data or for mapping peripherals into the processor address space. Additionally, there are two general purpose user inputs and two user outputs. Operation with slow peripherals is accomplished with a ready input pin. Development tools for the IBM PC include a relocatable assembler, a linker loader, and an ANSI-C compiler. Also, the development tools include a simulator/debugger, a cross assembler for the TMS320 family assembly code and a hardware emUlator. Notes: All Signals with a preceding front slash, 'f, are active Low, e.g., BIN/ (WORD is active Low); IB/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Power Ground GND Device Vee 6-1 ~2iUJG PRELIMINARY Z89320 16-Brr DIGITAL SIGNAL PROCESSOR GENERAL DESCRIPTION (Continued) Register Pointer 0-2 256 Word RAM 256 Word RAM o 1 Register Pointer 4-6 EXTO-15 RDVE, ERI/W, S-Bus EI EAO-2 16x16 Multiplier 24-bit® INTO-2 IRESET UIO-1 UOO-1 Figure 1. Functional Block Diagram 6-2 Z89320 PRELIMINARY 16·Brr DIGITAl SIGNAL PROCESSOR PIN DESCRIPTION EXT12 VSS EXT13 EXT2 EXT14 EXT1 VSS EXT15 EXTO VSS EXT3 NC EXT4 U01 VSS UOO EXT5 INTO EXT6 HALT EXT7 CK EXT8 EI EXT9 VDD VSS EA2 EXT10 EA1 EXT11 EAO INT2 IRES INT1 IRDYE UI1 ERlIW UIO VDD Figure 2. 40-Pin DIP Pin Assignments 6-3 ~2iUJG PRELIMINARY Z89320 16-Brr DlGrrAL SIGNAL PROCESSOR PIN DESCRIPTION (Continued) Table 1. 40-Pin DIP Pin Identification No. Symbol Function Direction 1-3 4 5 6-7 EXT12-EXT14 Vss External data bus Ground External data bus External data bus Input/Output Input Input/Output Input/Output Ground External data bus Ground External data bus Input Input/Output Input Input/Output Interrupt Interrupt User input User input Power Supply Input Input Input Input Input RNJ for external bus Data ready RESET External address bus Power Supply Data strobe for external bus CLOCK STOP execution Interrupt User output No Connection Ground External data bus Ground Output Input Input Output Input Output Input Input Input Output 8 9-13 14 15-16 Vss 17 18 19 20 21 INT2 INT1 UI1 UIO 22 23 24 25-27 28 29 30 31 32 33-34 35 36 37-39 40 6-4 EXT15 EXT3-EXT4 EXT5-EXT9 Vss EXT10-EXT11 Voo ER/NJ IRDYE IRES EAO-EA2 Voo EI CK HALT INTO UOO-U01 NC Vss EXTO-EXT2 Vss Input Input/Output Input Z89320 PRELIMINARY 0 z g :) 0 !:i !zo -z :l 6 5 4 3 0 0 2 c ~ iii ~ ~ 1&-BIT DIGITAL SIGNAL PROCESSOR _ US 1 44 43 42 41 40 VSS 7 39 EAO EXTO 8 3B IRES EXT1 9 37 IROVE EXT2 10 36 ERlIW VSS 11 35 VOO 34 NC Z89320 N/C 12 EXT12 13 33 UIO EXT13 14 32 UI1 EXT14 15 31 INT1 VSS 16 30 INT2 EXT15 17 29 EXT11 PLCC 18 19 20 21 22 23 24 25 26 27 28 Figure 3. 44-Pln PLCC Pin Assignments (Standard Mode) 6-5 ~~~~-~ -------- - ~-~ ~----~ .------~---- -----~~~-------~~- ~~ ~-- ~2ilJJ[; PRELIMINARY Z89320 16-Brr DIGITAl SIGNAL PROCESSOR PIN DESCRIPTION (Continued) Table 2. 44-Pin PlCC Pin Identification No. Symbol Function Direction 1 2 3 4-5 HALT NC INTO UOO-U01 STOP execution No Connection Interrupt User output Input Input Output 6 7 8-10 11 NC Vss No Connection Ground External data bus Ground Input Input/Output Input No Connection External data bus Ground External data bus Input/Output Input Input/Output 12 13-15 16 17 Vss NC EXT12-EXT14 Vss EXT15 18-19 20 21-23 24 Vss EXT3-EXT4 25-26 27 28-29 30 Vss External data bus Ground External data bus No Connection Input/Output Input Input/Output EXT10-EXT11 INT2 External Data Bus Ground External data bus Interrupt Input/Output Input Input/Output Input 31 32 33 34 INT1 Ul1 UIO NC Interrupt User input User input No Connection Input Input Input 35 36 37 38 VDD Power Supply RNI/ for external bus Data ready RESET Input Output Input Input External address bus Power Supply Data strobe for external bus CLOCK Output Input Output Input 39-41 42 43 44 6-6 EXTO-EXT2 EXT5-EXT7 NC EXT8-EXT9 ER/NI/ IRDYE IRES EAO-EA2 VDD EI CK PRELIMINARY Z89320 l6·BIT DIGITAL SIGNAL PROCESSOR PIN FUNCTIONS CK Clock (input). External clock. EXT15-EXTO External Data Bus (input/output). Data bus for user defined outside registers such as an ADC or DAC. The pins are normally in output mode except when the outside registers are specified as source registers in the instructions. All the control signals exist to allow a read or a write through this bus. ERlIW External Bus Direction (output). Data direction signal for EXT-Bus. Data is available from the CPU on EXT15-EXTO when this signal is Low. EXT-Bus is in input mode (high-impedance) when this signal is High. EA2-EAO ExternaIAddress(output). User-defined register address output. One of eight user-defined external registers is selected by the processor with these address pins for read or write operations. Since the addresses are part of the processor memory map, the processor is simply executing internal reads and writes. EI Enable Input(output). Read/Write timing signal for EXTBus. User defined register or the processor can put data on the EXT-Bus during a Low state. Data is read by the external peripheral on the rising edge of EI. Data is read by the processor on the rising edge of CK not EI. HALT Halt State (input). Stop Execution Control. The CPU continuously executes Naps and the program counter remains at the same value when this pin is held High. This signal must be synchronized with CK. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. INT2-INTO Three Interrupts (input, active Low). Interrupt request 2-0. Interrupts are generated on the rising edge of the input signal. Interrupt vectors for the interrupt service starting address are stored in the program memory locations OFFFH for INTO, OFFEH for INT1, and OFFDH for INT2. Priority is : INT2 = lowest, INTO = highest. IRES Reset(input, active Low). Asynchronous reset signal. A Low level on this pin generates an internal reset signal. The IRES signal must be kept Low for at least one clock cycle. The CPU fetches a new Program Counter (PC) value from program memory address OFFCH after the reset signal is released. IROVE Data Ready (input). User-supplied Data Ready signal for data to and from external data bus. This pin stretches the EI and ER//W lines and maintains data on the address bus and data bus. The ready signal is sampled at the rising edge of the clock with appropriate setup and hold times. The normal write cycle will continue from the next rising clock only if ready is active (High state). UI1-UIO Two Input Pins (input). General purpose input pins. These input pins are directly tested by the conditional branch instructions. These are asynchronous input signals that have no special clock synchronization requirements. U01-UOO Two Output Pins (output). General purpose output pins. Theirvalue is determined by the status register bits S5 and S6. If a one is loaded into S5 or S6, a Lowoutput appears at the respective pin. If a zero is used, a High output appears. ADDRESS SPACE Program Memory. Programs of up to 4K words can be masked into internal ROM. Four locations are dedicated to the vector address for the three interrupts (OFFDH-OFFFH) and the starting address following a Reset (OFFCH). Internal ROM is mapped from OOOOH to OFFFH, and the highest location for program is OFFBH. Internal Data RAM. The Z89320 has an internal 512 x 16bit word data RAM organized as two banks of 256 x 16-bit words each, referred to as RAMO and RAM1. Each data RAM bank is addressed by three pointers, referred to as Pn:O (n = 0-2) for RAMO and Pn:l (n = 0-2) for RAM1. The RAM addresses for RAMO and RAM1 are arranged from 0-255 and 256-511 respectively. The address pointers, which may be written to or read from, are 8-bit registers connected to the lower byte of the internal 16-bit D-Bus. and are used to perform no overhead looping. Three addressing modes are available to access the Data RAM: register indirect, direct addressing, and short form direct. These modes are discussed in detail later. The contents of the RAM can be read or written in one machine cycle per word without disturbing any internal registers or status other than the RAM address pointer used for each RAM. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The Z89320 has 12 internal registers and up to an additional eight external registers. The external registers are user definable for peripherals such as ND or D/A or to DMA or other addressing peripherals. External registers are accessed in one machine cycle the same as internal registers. 6-7 PRELIMINARY Z89320 16-Brr DIGITAL SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION General. The 289320 is a high-performance Digital Signal Processor with a modified Harvard-type architecture with separate program and data memory. The design has been optimized for processing power and minimizing silicon space. Instruction Timing. Many instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. When the program memory is referenced in internal RAM indirect mode, it takes three machine cycles. In addition, one more machine cycle is required if the PC is selected as the destination of a data transfer instruction. This only happens in the case of a register indirect branch instruction. An Acc + P => Acc; a(i) * b(j) ~ P calculation and modification of the RAM pointers, is done in one machine cycle. Both operands, a(i) and b(j), can be located in two independent RAM (0 and 1) addresses. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply or multiply accumulate in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers where the least significant bits are important, the data should first be scaled by eight bits (or the multiplier and multiplicand by four bits each) to avoid truncation errors. Note that all inputs to the multiplier should be fractional two's complement 16-bit binary numbers. This puts them in the range [-1 to 0.9999695]. and the result is in 24 bits so that the range is [-1 to 0.9999999]. In addition, if 8000H is loaded into both X and Y registers, the resulting multiplication is considered an illegal operation as an overflow would result. Positive one cannot be represented in fractional notation, and the multiplier will actually yield the result 8000H x 8000H = 8000H (-1 x -1 = -1). 6-8 ALU. The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16 bits of which are connected to the 16-bit D-Bus. A shifter between the P-Bus and the ALU input port can shift the data by three bits right, one bit right, one bit left or no shift. Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction pops the contents of the stack to the PC. User Inputs. The 289320 has two inputs, UIO and U11, which may be used by Jump and Call instructions. The Jump or Call tests one of these pins and if appropriate, jumps to a new location. Otherwise, the instruction behaves like a NOP. These inputs are also connected to the status register bits S10 and S11 which may be read by the appropriate instruction (Figure 4). User Outputs. The status register bits S5 and S6 are connected to UOO and U01 pins and may be written to by the appropriate instruction. The status bits are inverted prior to being output to the external pin. Interrupts. The 289320 has three positive edge-triggered interrupt inputs. An interrupt is acknowledged at the end of any instruction execution. It takes two machine cycles to enter an interrupt instruction sequence. The PC is pushed onto the stack. A RET instruction transfers the contents of the stack to the PC and decrements the stack pointer by one word. The priority of the interrupts is INTO = highest, INT2 = lowest. Registers. The 289320 has 12 physical internal registers and up to eight user-defined external registers. The EA2-EAO determines the address of the external registers. The /EI, /RDYE, and ER//W Signals are used to read or write from the external registers. Z89320 16-BIr DIGITAL SIGNAL PRocEssoR PRELIMINARY REGISTERS There are 12 internal reg!sters which are defined below: Register Register Definition P Output of Multiplier, 24-bit X X Multiplier Input, 16-bit Y Y Multiplier Input, 16-bit A Accumulator, 24-bit SR Pn:b PC Status Register, 16-bit Six Ram Address Pointers, a-bit each Program Counter, 16-bit A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSB's and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. Pn:b are the pointer registers for accessing data RAM, (n = 0,1,2 refers to the pointer number) (b = 0,1 refers to RAM Bank 0 or 1). They can be directly read from or written to, and can point to locations in data RAM or Program Memory. EXTn are external registers (n The following are virtual registers as physical RAM does not exist on the chip. Register Register Definition EXTn External registers, 16-bit O-Bus Eight Oata Pointers BUS On:b = 0 to 7). There are eight 16-bit registers here for mapping external devices into the address space of the processor. Note that the actual register RAM does not exist on the chip, but would exist as part of the external device such as an AOC result latch. bus is a read-only register which, when accessed, returns the contents of the O-Bus. Dn:b refer to possible locations in RAM that can be used P holds the result of multiplications and is read-only. X and Yare two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. Since the multiplier provides a flow through process, any data placed in the X or Y register automatically invokes a multiplication. as a pointer to locations in program memory. The programmer decides which location to choose from two bits in the status register and two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At anyone time there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in RAM. For example, if S3/S4 = 01 in the status register, then 00:0/01 :0/02:0/03:0 refer to locations 4/5/6/7 in RAM Bank O. Note that when the data pointers are being written to, a number is actually being loaded to Oata RAM, so they can be used as a limited method for writing to RAM. 6-9 _ ... _ - - - - - - - - - - -.--~ ---.---- .. . . ~ - -. _ '.~~. .. ..... Z89320 PRELIMINARY 16-BIr DIGITAL SIGNAL PRocEssoR REGISTERS (Continued) Ram Pointer Loop Size 000 001 010 011 100 101 110 111 256 2 4 8 16 32 84 128 'Short Form Direct' bits User Output ()"1 Interrupt Enable Overflow protacUon MPY output shifted by three bits User Input 0-1 (Reed Only) Carry Zero Overflow Negative Figure 4. Status Register SR is the status register (Figure 4) which contains the ALU status and certain control bits as shown in the following table. Table 3. Status Register Bit Functions Status Register Bit Function S15 (N) S14 (OV) S13 (Z) S12 (L) S11 (UI1) S10 (UIO) ALU Negative ALU Overflow ALU Zero Carry User Input 1 User Input 0 S9 (SH3) S8 (OP) S7 (IE) S6 (U01) S5 (UOO) S4-S3 S2-S0 (RPL) MPY Output Shifted by three bits Overflow Protection Interrupt Enable User Output 1 User Output 0 "Short Form Direct" bits RAM Pointer Loop Size 6-10 Table 4. RPL Description S2 S1 SO Loop Size o o o o 0 0 1 1 0 1 0 1 256 2 4 8 0 0 1 1 0 1 0 1 16 32 64 128 The status register may always be read in its entirety. S15S10 are set/reset by the hardware and can only be read by software. S9-S0 can be written by software. Z89320 PRELIMINARY 815-812 are set/reset by the ALU after an operation. 811810 are set/reset by the user inputs. 86-80 are control bits described elsewhere. 87 enables interrupts. 88, if 0 (reset), allows the hardware to overflow. If 88 is set, the hardware clamps at maximum positive or negative values instead of overflowing. 16-BIT DIGITAL SIGNAL PRoceSSOR If 89 is set and the MPYA or MPY8 instruction is used, then the shifter to the ALU shifts the result three bits right. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. RAM ADDRESSING The address of the RAM is specified in one of three ways (Figure 5): RAMI RAMO RAM Pointers %FF 1-_......._ %FF ---- PO:O Pl:0 P2:0 9:~. %37 RAM Pointers PO:l 256 x 16-Bit 256 x 16-Bit 1-_'*..000.;,32;;,,;1_ - r- Pl:l P2:1 %0321 %04 -- 84/S3=01 %00 L..-_ __ %00 '--- Oata Pointers IntemalROM %OFFF @@Pl:0 %0321 %0000 ---4K x 16-Bit --%1234 --- ~ 00 :Om*,0321 01 :0 00:1 02 :0 02:1 03:0 03:1 @00:1 01:1 Both 01 theFoliowing Instructions Load %1234 into the Accumulator. LOA,@@Pl:0 LOA,@OO:1 Figure 5. RAM, ROM, and Pointer Architecture Register Indirect b Pn:b n =0-2, b = 0-1 The most commonly used method is a register indirect addressing method, where the RAM address is specified by one of the three RAM address pointers (n) for each bank (b). Each source/destination field in Figures 6 and 9 may be used by an indirect instruction to specify a register pointer and its modification after execution olthe instruction. nl T nO L RAM Pointer Register ' - - - - - - - Operation ~--------RAMBMk Figure 6. Indirect Register 6-11 ~~~~ -- ~----~------ Z89320 PRELIMINARY 16-Brr DIGITAL SIGNAL PROCESSOR RAM ADDRESSING (Continued) The register pointer is specified by the first and second bits in the source/destination field and the modification is specified by the third and fourth bits according to the following table: 03·00 Meaning OOxx 01xx 10xx llxx NOP +1 -l/LOOP +l/LOOP No Operation Simple Increment Decrement Modulo the Loop Count Increment Modulo the Loop Count xxOO xxOl xxl0 xxll PO:O or PO:l Pl:0 or Pl:l P2:0or P2:1 See See See See Note a. Note a. Note a. Short Form Direct Notes: a. If bit 8 is zero, PO:O to P2:0 are selected; if bit 8 is one, PO:1 to P2:1 are selected. Direct Register The second method is a direct addressing method. The address of the RAM is directly specified by the address field of the instruction. Because this addressing method consumes nine bits (0-511) of the instruction field, some instructions cannot use this mode (Figure 7). When LOOP mode is selected, the pointer to which the loop is referring will cycle up or down, depending on whether a -LOOP or +LOOP is specified. The size of the loop is obtained from the least significant three bits of the Status Register. The increment or decrement of the register is accomplished modulo the loop size. As an example, if the loop size is specified as 32 by entering the value 101 into bits 2-0 ofthe Status Register (S2-S0) and an increment +LOOP is specified in the address field of the instruction, i.e., the RPi field is l1xx, then the register specified by RPi will increment, but only the least significant five bits will be affected. This means the actual value of the pointer will cycle round in a length 32 loop, and the lowest or highest value of the loop, depending on whether the loop is up or down, is set by the three most significant bits. This allows repeated access to a set of data in RAM without software intervention. To clarify, if the pointer value is 10101001 and if the loop = 32, the pointer increments up to 10111111, then drops down to 10100000 and starts again. The upper three bits remaining unchanged. Note that the original value of the pointer is not retained. Figures 9 to 14 show the different register instruction formats along with the two tables below Figure 9. RAM Address Opcode Figure 7. Direct Internal RAM Address Format Short Form Direct Dn:b n = 0-3, b = 0-1 The last method is called Short Form Direct Addressing, where one out of 32 addresses in internal RAM can be specified. The 32 addresses are the 16 lower addresses in RAM Bank 0 and the 16 lower addresses in RAM Bank 1. Bit 8 of the instruction field determines RAM Bank 0 or 1. The 16 addresses are determined by a4-bit code comprised of bits S3 and S4 of the status register and the third and fourth bits of the Source/Destination field. Because this mode can specify a direct address in a short form, all of the instructions using the register indirect mode can use this mode (Figure 8). This method can access only the lower 16 addresses in the both RAM banks and as such has limited use. The main purpose is to specify a data register, located in the RAM bank, which can then be used to point to a program memory location. This facilitates down-loading look-up tables etc. from program memory to RAM. n3 n2 nl nO L-_ _ _ _ RAM Address RAM Bank Figure 8, Short Form Direct Address 6-12 Z89320 PRELIMINARY 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION FORMAT 1 Source field Destination field RAM Bank selection Opcode Note: Source/Destination fields can speci!y eHher register or RAM address in RAM pointer indirect mode. Figure 9. General Instruction Format TableS. Registers Source/Destination Table 6. Register Pointers Field Source/Destination Meaning A OOxx 01xx 10xx 11xx NOP +1 -1/LOOP +1/LOOP 0100 0101 0110 0111 SR STACK PC P"" xxOO xx01 xx10 xx11 PO:O or PO:1" P1:0 or P1:1" P2:0 or P2: 1" Short Form Direct Mode""" 1000 1001 1010 1011 EXTO EXT 1 EXT2 EXT3 1100 1101 1110 1111 EXT4 EXT5 EXT6 EXT? 0000 0001 0010 0011 Register BUS"" X Y Notes: if RAM Bank bit is 0, then Pn:O are selected. If RAM Bank bit is 1, then Pn:l are selected. •• Read only. When the short form direct mode is selected, 00000-01111 or 10000-11111 are used as RAM addresses. Short Immediate Data 000 001 010 011 100 101 Reg. Pointer PO:O P1:0 P2:0 NA PO:1 P1:1 110 P2:1 111 NA Opcode 00011 Figure 10. Short Immediate Data Load Format 6-13 Z89320 PRELIMINARY 16·Brr DlGrrAL SIGNAL PROCESSOR INSTRUCTION FORMAT (Continued) 1st Word General Instruction Format 2nd Word Immediate Data Figure 11. Immediate Data Load Format 101510141013 0121011 1010 1 09 108 1 07 106 -r- 05 104 1 03 102 1 01 IDO 1 ACC Modification Codes o0 0 0 ROR Rotate right o0 0 1 ROL Rotate left o0 1 0 SHR Shift right o0 1 1 SHL Shift left 01 00 INC Increment (LSB) o1 0 1 DEC Decrement (LSB) o1 1 0 NEG Negate o1 1 1 ABS Absolute Condition Codes 0000 TRUE 0001 --.0010U01=0 0011 U01=0 0100C=0 0101 Z=O 01100V=0 0111 N=O 1 xxx ---0000 TRUE 0001 -- -0010 UOO=1 0011 U01=1 0100 C=1 0101 Z=1 0110 OV=1 0111 N=1 1 xxx ---- o= Negative Condition 1 = Positive Condition Opcode 1001000 Figure 12. Accumulator Modification Format 6-14 Z89320 PRELIMINARY 16-BIT DIGITAL SIGNAL PROCESSOR 1st Word xxxx Condition Codes 0000 TRUE 0001 ---0010 UOO=O 0011 U01=0 0100C=0 0101 Z=O 01100V=0 0111 N=O 1xxx ---DO 0 0 TRUE 0001 ---0010 UOO=l 0011 U01=1 0100 C=l 0101 Z=1 0110 OV=l 0111 N=l 1xxx ---Condition 0= Negative Condition 1 = Positive Condition Opcode 0100110 Branch 0100100 Call 2nd Word Branch Address Figure 13. Branching Format ' - - - - - xxl0 Reset Cflag xxll Set Cflag x1xO Reset IE Flag (Interrupt enable) x1xl Set IE Flag lxxO ResetOPAag (OVerflow protection) lxxl Set OP Flag ~---------- xxxx Opcode 1001010 Mod Figure 14. Flag Modification Format 6-15 PRELIMINARY Z89320 16-Brr DIGITAL SIGNAL PROCESSOR ADDRESSING MODES This section discusses the syntax of the addressing modes supported by the DSP assembler. The symbolic name is used in the discussion of instruction syntax in the instruction descriptions. Table 7. Addressing Modes Symbolic Name Syntax Description Pn:b Pointer Register Dn:b Data Register X,Y,PC,SR,P EXTn,A,BUS Hardware Registers (Points to Program Memory) @A Accumulator Memory Indirect Direct Address Expression # Long (16-bit) Immediate Value # Short (a-bit) Immediate Value (Points to RAM) @Pn:b @Pn:b+ @Pn:b-LOOP @Pn:b+LOOP Pointer Register Indirect Pointer Register Indirect with Increment Pointer Register Indirect with Loop Decrement Pointer register Indirect with Loop Increment (Points to Program Memory) @@Pn:b @Dn:b @@Pn:b-LOOP @@Pn:b+LOOP @@Pn:b+ Pointer Register Memory Indirect Data Register Memory Indirect Pointer Register Memory Indirect with Loop Decrement Pointer Register Memory Indirect with Loop Increment Pointer Register Memory Indirect with Increment (Points to RAM) ' There are eight distinct addressing modes for transfer of data (Figure 5 and Table 7). , . These two modes are used for simple loads to and from registers within the chip such as loading to the Accumulator, or loading from a pointer register. The names of the registers need only be specified in the operand field. (Destination first then s?urce.) . This mode is used for indirect accesses to the data RAM. The address of the RAM location is stored in the 6-16 pointer. The "@" symbol indicates "indirect" and precedes the pointer, so@P1:1 tells the processor to read or write to a location in RAM1 , which is specified by the value in the pointer. . This mode is also used for accesses to the data RAM but only the lower 16 addresses in either bank. The '4-bit address comes from the status register and the operand field of the data pointer. Note that data registers are typically used not for addressing RAM, but loading data from program memory space. Z89320 PRELIMINARY . This mode is used for indirect, indirect accesses to the program memory. The addressofthe memory is located in a RAM location, which iS,specified by the value in a pointer. So@@Pl:l tells the processor to read (write is not possible) from a location in memory, which is specified by a value in RAM, and the location of the RAM is in turn specified by the value in the pointer. Note that the data pointer can also be used for a memory access in this manner, but only one "@" precedes the pointer. In both cases the memory address stored in RAM is incremented by one each timethe addressing mode is used to allow easy transfer of sequential data from program memory. 16-Brr DlGrrAL SIGNAL PROCESSOR . The direct mode allows read or write to data RAM from the Accumulator by specifying the absolute address of the RAM in the operand of the instruction. A number between 0 and 255 indicates a location in RAMO, and a number between 256 and 511 indicates a location in RAM1. . This indicates a long immediate load. A 16-bit word can be copied directly from the operand into the specified register or memory. . This can only be used for immediate transfer of 8-bit data in the operand to the specified RAM pointer. . Similar to the previous mode, the address for the program memory read is stored in the Accumulator. @A in the second operand field loads the number in memory specified by the address in A. CONDITION CODES The following defines the condition codes supported by the DSP assembler. If the instruction description refers to the (condition code) symbol in one of its addressing modes, the instruction will only execute if the condition is true. Table 8. Condition Codes Name Description Name Description C EQ F IE MI NC NE NIE NOV NUO Carry Equal (same as Z) False Interrupts Enabled Minus No Carry Not Equal (same as NZ) Not Interrupts Enabled Not Overflow Not User Zero NUl NZ OV PL UO Ul UGE Not User One Not zero Overflow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero ULT Z 6-17 ttlZll.£ll3 Z89320 16-Brr DIGITAL SIGNAL PROCESSOR PRELIMINARY INSTRUCTION DESCRIPTIONS Inst. Descrlpllon Synopsis Operands ABS Absolute Value ABS[,) ,A A ADD Addition ADD, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 ADDA,PO:O ADDA,DO:O ADDA,'%1234 ADD A,OOPO:O ADDA,%F2 ADDA,@P1:1 ADDA,X AND Bitwise AND AND, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 ANDA,P2:0 ANDA,DO:1 AND A,'% 1234 AND A,OOP1:0 ANDA,%2C AND A,@P1:2+LOOP ANDA,EXT3 CALL Subroutine call CALL [,)
, 2 2 2 2 CALLZ,sub2 CALLsub1 CCF Clear carry flag CCF None CCF ClEF Clear Carry Flag ClEF None ClEF COPF Clear OPfiag COPF None COPF CP Comparison CP, A, A, A, A, A, A, A 1 1 1 1 1 1 2 1 1 DEC Decrement DEC (,) A, A INC Increment INC [,) ,A A JP Jump JP[ ,)
, 6-18 Words Cycles Examples ABSNC,A ABSA 1 1 3 1 1 1 2 CPA,PO:O CPA,D3:1 CPA,@@PO:1 CPA,%FF CPA,@P2:1+ CPA,STACK CPA,'%FFCF DEC NZ,A DECA INC PL,A INCA 2 2 2 2 JP NIE,Label JP Label ~2jLJ:]l; Z89320 PRE L I MIN A R Y Insl. Description Synopsis Operands LD Load destination with source LD, A, A, A, A, A, A, ,A , , , , , , , , , , , , 16-Brr DIGITAL SIGNAL PROCESSOR Words Cycles Examples 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 LD A,X LD A,DO:O LD A,PO:1 LD A,@P1:1 LD A,@DO:O LD A,124 LD 124,A LD DO:O,EXTl LD P1:1 ,#%FA LD P1:1 ,EXT1 LD@P1:1 ,#1234 LD@P1:1+,X LD Y,PO:O LD SR,DO:O LD PC,#%1234 LDX,@A LD Y,@DO:O LD A,@PO:D-LOOP LD X,EXT6 Note: When is , cannot be P. Note: When is and is , cannot be EXTn if is EXTn, cannot be Xif is X, cannot be SR if is SR. Note: When is cannot be A. MLD Multiply MLD,[', ,, , ,, MLD A,@PO:D+LOOP MLD A,@P1:0,OFF MLD @P1:1,@P2:0 MLD @PO:1,@P1:0,ON Note: If src1 is it must be abank 1 register. Src2's for src1 cannot be X. Note: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. MPYA Multiply and add MPYA ,[,, ,, , ,, MPYAA,@PO:O MPYA A,@P1:0,OFF MPYA@P1:1,@P2:0 MPYA@PO:1,@P1:0,ON Note: If src1 is it must be abank 1 register. Src2's must be abank 0 register. Note: for src1 cannot be X. Note: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. 6-19 ~2iu::a; Z89320 PRELIMINA R Y 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS (Continued) Insl. Description MPYS Multiply and subtract Synopsis Operands Words Cycles Examples MPYS A,@PO:O MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS@PO:1,@P1:0,ON MPYS,[,] , ,, , ,, Note: If src1 is it must be abank 1register. Src2's must be a bank 0 register. Note: for src1 cannot be X. Note: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. NEG Negate NEG ,A , A A NEG MI,A NEG A NOP No operation NOP None NOP OR Bitwise OR OR , A, A, A, A, A, A, A, POP Pop value from stack POP PUSH Push value onto stack PUSH <3ccind> RET Return from subroutine RET None RL Rotate Left RL ,A ,A A RL NZ,A RLA RR Rotate Right RR ,A ,A A RR C,A RR A 6-20 1 1 2 1 1 1 1 1 1 2 3 1 1 1 OR A,PO:1 ORA,OO:l OR A.I%2C21 OR A,OOP2:1+ ORA, %2C OR A,@P1:O--LOOP ORA,EXT6 POP PO:O POP 00:1 POP@PO:O POPA 1 1 1 1 2 1 1 1 1 1 1 2 3 3 PUSH PO:O PUSH 00:1 PUSH@PO:O PUSH BUS PUSH #12345 PUSH@A PUSHOOPO:O 2 RET ~2iu::a; Z89320 16·BIT DIGITAL SIGNAL PROCESSOR PRE L I MIN A R Y Insl. Descrlpllon Synopsis Operands SCF Set Cflag SCF None SCF SIEF Set IE flag SIEF None SIEF SLL Shift left logical SLL [,lA A SLL NZ,A SLL A SOPF Set OP flag SOPF None SOPF SRA Shift right arithmetic SRA,A ,A A SRANZ,A SRAA SUB Subtract SUB, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 XOR Bitwise exclusive OR XOR , A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 XORA,P2:0 1 XORA,DO:1 2 XOR A,#13933 3 XOR A,@@P2:1+ 1 . XORA,%2F 1 XORA,@P2:0 1 XORA,BUS Bank Switch Enumerations. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether a bank switch is set on or off. To more clearly represent this two keywords are used (ON and OFF) which Words Cycles Examples SUB A,P1:1 SUBA,DO:1 SUB A,I%2C2C SUBA,@DO:1 SUBA,%15 SUB A,@P2:O-LOOP SUBA,STACK state the direction of the switch. These keywords are referred to in the instruction descriptions through the symbol. 6·21 -------:--.----~--- -----:---::- ---- -------~-~-.------ Z89320 PRELIMINARY ~6·BIT DIGITAL SIGNAL PROCESSOR ABSOLUTE MAXIMUM RATINGS Symbol Description Min. Max. Units vcc Supply Voltage (*) Storage Temp Oper Ambient Temp -0.3 -65° +7.0 +150° V C t C TSTG TA Notes: • Voltage on all pins with respect to GND. t See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability . STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Figure 15). 2.1 KO FromO~p~ ~-----'--~~--~---i Under Test Figure 15. Test Load Diagram DC ELECTRICAL CHARACTERISTICS (Voo= 5V ±5%, TA = O°C to +70°C unless otherwise specified) Symbol Parameter Condition 100 Supply Current loe DC Power Consumption Voo= 5.25V fclock = 10 MHz Voo= 5.25V V1H V1L IL Input High Level Input Low Level Input Leakage VOH VOL IFL Output High Voltage Output Low Voltage Output Floating Leakage Current 6-22 Min. Max. Units 60 mA 5 mA 0.9 Voo 0.1 Voo 1 IOH= -100 IlA IOL = 0.5 mA Voo-O.2 0.5 5 V V IlA V V IlA Z89320 16-Brr DIGiTAL SIGNAL PRocESSOR PRELIMINARY AC ELECTRICAL CHARACTERISTICS (Voo = 5V ±5%, TA = O°C to +70°C unless otherwise specified) Symbol Parameter Min. Max. Units TCY PWW Tr Tf Clock Cycle Time Clock Pulse Width Clock Rise Time Clock Fall Time 100 45 2 2 1000 ns ns ns ns TEAD TXVD TXWH TXRS EA,ERlNI Delay from CK EXT Data Output Valid from CK EXT Data Output Hold from CK EXT Data Input Setup Time 15 5 15 15 25 25 ns ns ns ns 0 0 10 0 15 5 ns ns ns ns TXRH TIED RDYS RDYH EXT Data Input Hold from CK lEI Delay Time from CK Ready Setup Time , Ready Hold Time 4 4 'AC TIMING DIAGRAM TXWH 1 + - - - - - TOV - - - - - 1 + - - . 1 OK TIED lEI ERlIW EXT (15:0) EA(2:0) Valid Da1aOut Valid Address Out TEAD IRDVE RDVS Figure 16. Write To External Device Timing 6-23 PRELIMINARY AC TIMING DIAGRAM (Continued) TXRH 1+------ TCY ----~I+__.j TXRS CK TIED lEI ERlIW Valid Data In EXT (15:0) EA(2:0) Valid Address Out I..I.A,",,~"+,-""'" IROYE Figure 17. Read From External Device Timing 6·24 Z89320 16·BIT DIGITAL SIGNAL PROCESSOR Z89320 16·Brr DIGITAL SIGNAL PROCESSOR PRELIMINARY PACKAGE INFORMATION 20 EI SYMBOL AI A2 I II C D [ [I • .A L • QI S HILLlMtTER MIN MAX 0.51 0.81 3.l!S 3.43 0.38 0.S3 1.02 1.52 0:23 S2.07 IS.C!4 13.5. 2.54 15.49 INCH HIN .020 .128 .015 .040 0.39 .00' S2.58 IS.75 14.22 2.Q50 HAX .032 .135 .021 .060 .01'S 2.070 .620 .560 .100 ryp .600 .S3S rvp 3.18 16.51 3.81 .610 .12S 1.52 1.52 t.91 2.2' .060 .060 CDNTROLLING DIM£NSI[]NS .650 J50 .075 .090 I tNCH 40-Lead DIP Package Diagram 6-25 Z89320 16-Brr DlGrrAL SIGNAL PROCESSOR PRELIMINARY PACKAGE INFORMATION (Continued) D DI 45' ""\ , 7 I 40 39 i I 1-'-'-'+'-'-'17 i 11 EI E UJ I I 28 SYMBIlL IIITE:50 L CDNTROLLING DIMENSIDN5 , INCH 2. LEADS ARE CIlPLANAR WITHIN .004 IN. 3. DIMENSION , ...JIlL INCH A Al DIE DIIEI Di! -- MILLIMETm MAX MIN 4.57 427 2.67 2.92 17.40 17.6' 16.51 16.66 15J14 16.00 Li!7 TYP 44-Pln PLCC Package Diagram 6-26 INCH MIN MAX .168 .180 .105 .115 .685 .695 .656 .650 .600 .630 .050 TVP PRELIMINARY Z89320 16·BIT DIGITAL SIGNAL PROCESSOR ORDERING INFORMATION Z89320 10 MHz 40·pin DIP Z8932010PSC 10 MHz 44-pin PLCC Z8932010VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package P = Plastic DIP V = Plastic Chip Carrier Temperature S = O°C to +70°C Speed 10 = 10 MHz Environmental C = Plastic Standard Example: Z 89320 10 P S C ~ is a Z89320, 10 MHz, DIP, O°C to +70°C, Plastic Standard Flow. Environmental Flow Temperature Package Speed Product Number Zilog Prefix 6-27 4:)2;1« 0, l89320 16..Bit Mixed Signal Processor l89321 16·Blt Mixed Signal Processor II Support Product , Information Superintegratlon™ Products Guide II 'Literature Guide and Third Party Support ZUog Sales Offices Representatives & Distributors II ~2iua!, ADVANCE INFORMATION SPECIFICATION Z89321 16-81T DIGITAL SIGNAL PROCESSOR FEATURES • 16-Bit Single Cycle Instructions • Zero Overhead Hardware Looping • 16-Bit Data • Ready Control for Slow Peripherals • Single Cycle Multiply/Accumulate (100 ns) • Six-Level Stack • 512 Words of On-Chip RAM • Programmable Timer • • • • • • • • 16-Bit I/O Port 4K Words of On-Chip Masked ROM Three Vectored Interrupts Two Conditional Branch Inputs/Two User Outputs 24-Bit ALU, Accumulator and Shifter IBM«> PC Development Tools Cost Effective 44-Pin PLCC Package CODEC Interface GENERAL DESCRIPTION The Z89321 is a second generation, 16-bit, fractional, two's complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains 1 Kbyte of on-chip data RAM (two blocks of 256 16-bit words), 4K words of program ROM. Also, the processor features a 24-bit ALU, a 16 x 16 multiplier, a 24-bitAccumulator and a shifter. Additionally, the processor contains a six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of three pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true single cycle multiply. inputs and two user outputs. Operation with slow peripherals . is accomplished with a ready input pin. Development tools for the IBM PC include a relocatable assembler, a linker loader, and an ANSI-C compiler. Also, the development tools include a simulator/debugger, a cross assemblor for the TMS320 family assembly code and a hardware emulator. Notes: All Signals with a preceding front slash, "t, are active Low, e.g., BINI (WORD is active Low); IBNI (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection The device includes a 16-bit I/O bus for transferring data or for mapping peripherals into the prOcessor address space. Additionally, there are two general purpose user Circuit Device Power Ground 7-1 ADVANCE INFORMATION Z89321 16·Brr DlGrrAL SIGNAL PROCESSOR GENERAL DESCRIPTION (Continued) Register Pointer 0-2 256 Word RAM 256 Word RAM o 1 EXTO-t5 - - -, ,, RDVE, ERJrw, lEI S-Bus EAO-2 : ,, ----1 ,, ,,, IINTO-2 - - - -: IRESET t-------I User Port Status (5) UIO-l UOO-t ,,, , ----,,, ,,, r----------------------------------------~ ;~~~~St~~;i~>g~ ~~'b~~"7n:~~:.e 16-bit I/O Port, ,..._..L'_...., DIN DENAO CODEC DCLK DOUT DENAI Interface ~ Data Rate 2.048/1.7066 MHz _ _ _ _ _..... 10.24 MHz 5.12/2.56/1.28/0.64 MHz Timer Output Figure 1. Functional Block Diagram 7-2 Z89321 ADVANCE INFORMATION 16-BIT DiGITAL SIGNAL PROCESSOR PIN DESCRIPTION DCLK EXTO EXTl • EXT2 VSS DENAl EXT12 Z89321 PLCC EXT13 EXT14 VSS EXT15 EAO 38 37 IRES IROVE 36 35 VDD 34 TO 33 UIO 32 31 30 INTl 29 18 19 20 21 22 23 24 25 26 27 28 ERJ/W Ull INT2 EXTll § ~ ~ ~ ~ ~ c~ ~ ~ ~ ~ Figure 2. 44-Pin PLCC Pin Assignments 7-3 ft)aI..£E ADVANCE INFORMATION Z89321 16-B1T DIGITAL SIGNAL PRocessoR PIN DESCRIPTION (Continued) Table 1. 44·Pin PLCC Pin Identification 7-4 No. Symbol Function Direction 1 2 3 4-5 6 HALT Dour IINTO UOO-U01 DIN Stop execution Data Out Interrupt User output Data In Input Output Input Output Input 7 8-10 11 12 13-15 DCLK EXTO-EXT2 Vss DENA1 EXT12-EXT14 CO DEC Lock External data bus Ground Enable 1 External data bus Output Input/Output Input Output Input/Output 16 17 18-19 20 21-23 Vss EXT15 EXT3-EXT4 Vss EXT5-EXT7 Ground External data bus External data bus Ground External data bus Input Input/Output Input/Output Input Input/Output 24 25-26 27 28-29 30 DENAO EXT8-EXT9 Vss EXT10-EXT11 IINT2 Enable 0 External Data Bus Ground External data bus Interrupt Output Input/Output Input Input/Output Input 31 32 33 34 35 IINT1 UI1 UIO TO Veo Interrupt User input User input Timer Output Power Supply Input Input Input Output Input 36 37 38 39-41 42 43 44 ERINI /ROVE /RES EAO-EA2 Voo lEI CK RNI for external bus Data ready Reset External address bus Power Supply Data strobe for external bus Clock Output Input Input Output Input Output Input Z89321 ADVANCE INFORMATION 16·BIT DIGITAL SIGNAL PROCESSOR CODEC INTERFACE CONTROLLER External DSP registers EXT5 and EXT6 are used by External Codec Interface. The accessibility of these devices is driven by the Codec{fimer Control register (EXT?). Two different Codecs can be addressed by the Codec/ Timer Control register (EXT?). The data can be loaded to CodecO or Codec1 by writing to EXT5 or EXT6 correspondingly. In order to receive the data from the Codecs the DSP should read EXT5 and EXT6. 1. Codec Data Registers - EXT5 and EXT6 The DSP writes data to Codecs using the lower eight bits of the EXT5 and EXT6 registers. The eight remaining upper bits of EXT5 and EXT6 are reserved, as shown in Table 2. 2. CodecITimer Control Register The DSP can define the status of the Codecs and the frequency of the Timer output by writing data to a Codec/ Timer Control Register (Table 3). Table 2. Codec Data Registers - EXT5 and EXT6 Field Reserved Position AHrib. fedcba9B-------- Value Label %NN %NN Return '0' No effect Data from Codec Data to Codec R W --------76543210 R W Table 3. CodeclTimer Control Register Field Reserved Position fedcba9B76------ AHrib. Value Return '0' No effect R W Codec_enable ----------54---- R/W 00 01 10 11 Disabled CO enable Reserved Enabled R/W o Divided-by-6 Divided-by-5 1 Sampling -------------2-- R/W o 1 Timer_rate --------------10 Label R/W 00 01 10 11 Codec_enable. This field enables the Codecs. The options are disable both Codecs, enable both Codecs, or enable CodecO only. Codec1 can not be enabled alone. Div5/6. This bit defines the speed of codecs. If the bit is set to a '1' the Codec clock frequency is set to 2.048 MHz and the sampling rate equals to 8 KHz. If the bit is resetto '0' the codec clock frequency is equal to 1.7066 MHz, while the sampling rate is setto 6.66 KHz. Upon a paR the bit is reset to '0'. Normal Slow Divided-by-2 Divided-by-4 Divided-by-8 Divided-by-16 Sampling. This field defines the sampling rate of the Codecs. The sampling rate can be selected from 8 KHz ('0') and 6.66 ('1'). The clock frequency of the Codecs is not controlled by this field. Upon paR the bit is set to a '0'. Timer-rate. This field defines the frequency of the embedded Timer. Upon paR the field is reset to a '00'. 7-5 Z89321 ADVANCE INFORMATION 16-BIT DIGITAL SIGNAL PROCESSOR CODEC INTERFACE CONTROLLER (Continued) 3. The Codec Interface Timings Codec interface provides the customer with all necessary signals to connect two independent Codec chips. The supported effective data rate for each Codec is 8/6.66 Kbytes/sec. The Clock frequency is fixed to 2.048/1.7066 MHz. Figure 4 timing diagrams describe the functionality of Codec interface. Figure 3 shows the connection of Z89321 to popular TI (TCM29C18) and Motorola's (MC145503) codecs. No additional components are necessary. TCM29C18 -5V vee - [ PWRO+ GSX PWRO- ANALOG IN Analog Out +5V IPDN r--f ~ -{ GND +5V VCC h II GND ANGND DClKR fTSX PCMIN PCMOUT FSRfTSRE FSXfTSXE GND ClK Analog In Y P-- DINIP33 r D---- DENAOIP34 DClKlP35 DOUTIP36 MC145503 GND Analo In GND Analo +5V +5V -5V VAG VDD RXO ROD +Tx RCE Txl ROC -Tx TOC MulA TOO IPDI TOE VSS VlS +5V DOUT DENA DClK DIN GND Figure 3. Connection of TCM29C18 and MC145503 To Z89321 7-6 Z8932l ADVANCE INFORMATION Clock l6·BIT DIGITAL SIGNAL PROCESSOR JlQl1JlOllJJJJJ. 1 Enable 1 11 I I ~ I " ' - - - 1- Clock OENAO OENA1 OATA_VALIO' - I I I I I II I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I : -: : : : : : : I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I ~ I I I I I _I_~==========================~__ -+~ Figure. 4 CODEC Interface Tming Diagram • Data Valid is an internal signal generated by the CO DEC interface. When the CODEC is enabled, this signal is applied to interrupt 0 and user input O. In this way, the DSP can determine when data is valid either by an interrupt on INTO or by polling UIO. Under these conditions, INTO and UIO are disabled. 7·7 ADVANCE INFORMATION Z89321 16-Brr DIGITAL SIGNAL PROCESSOR PIN FUNCTIONS CK Clock (input). External clock. EXT1S-EXTO External Data Bus (input/output). Data bus for user defined outside registers such as an ADC or DAC. The pins are normally in. output mode except when the outside registers are specified as source registers in the instructions. All the control signals exist to allow a read or a write through this bus. ERlIW External Bus Direction (output). Data direction signal for EXT-Bus. Data is available from the CPU on EXT15-EXTO when this signal is Low. EXT-Bus is in input mode (high-impedance) when this signal is High. EA2-EAO ExternaIAddress(output). User-defined register address output. One of eight user-defined external registers is selected by the processor 'with these address pins for read or write operations. Since the addresses are part of the processor memory map, the processor is simply executing internal reads and writes. lEI Enable Input(output). Read/Write timing signal for EXTBus. User defined register or the processor can put data on the EXT-Bus during a Low state. Data is read by the external peripheral on the rising edge of /EI. Data is read by the processor on the rising edge of CK not /EI. HALT Halt State (input). Stop Execution Control. The CPU continuously executes Naps and the program counter remains at the same value when this pin is held High. This signal must be synchronized with CK. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. IINT2-IINTO Three Interrupts (inpul, active Low). Interrupt request 2-0. Interrupts are generated on the rising edge of the input signal. Interrupt vectors for the interrupt service starting address are stored in the program memory locations OFFFH for /INTO, OFFEH for /INT1, and OFFDH for /INT2. Priority is: INT2 ;; lowest, INTO;; highest. IRES Reset(input, active Low). Asynchronous reset signal. A Low level on this pin generates an internal reset signal. The /RES signal must be kept Low for at least one clock cycle. The CPU pushes the contents of the PC onto the stack and then fetches a new Program Counter (PC) value from program memory address OFFCH after the reset signal is released. IROVE Data Ready (input). User-supplied Data Ready signal for data to and from external data bus. This pin stretches the /EI and ER//W lines and maintains data on the address bus and data bus. The ready signal is sampled from the rising edge of the clock with appropriate setup and hold times. The normal write cycle will continue frorn the next rising clock only if ready is active. UI1-UIO Two Input Pins (input). General purpose input pins. These input pins are directly tested by the conditional branch instructions. These are asynchronous input signals that have no special clock synchronization requirements. U01-UOO Two Output Pins (output). General purpose output pins. These pins reflect the value of two bits in the status register S5 and S6. These bits have no special significance and may be used to output data by writing to the status register. ADDRESS SPACE Program Memory. Programs of up to 4K words can be masked into internal ROM. Four locations are dedicated to the vector address for the three interrupts (OFFDH-OFFFH) and the starting address following a Reset (OFFCH). Internal ROM is mapped from OOOOH to OFFFH, and the highest location for program is OFFBH. Internal Data RAM. The Z89321 has an internal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each, referred to as RAMO and RAM 1. Each data RAM bank is addressed by three pointers, referred to as Pn:O (n ;; 0-2) for RAMO and Pn: 1 (n ;; 0-2) for RAM1. The RAM addresses for RAMO and RAM1 are arranged from 0-255 and 256-511 respectively. The address pointers, which may be written to or read from, are 8-bit registers connected to the lower byte of the internal 16-bit D-Bus 7-8 and are used to perform no overhead looping. Three addressing modes are available to access the Data RAM: register indirect, direct addressing, and short form direct. These modes are discussed in detail later. The contents of the RAM can be read or written in one machine cycle per word without disturbing any internal registers or status other than the RAM address pointer used for each RAM. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The Z89321 has 12 internal registers and up to an additional eight external registers. The external registers are user definable for peripherals such as A/D or D/A or to DMA or other addressing peripherals, External registers are accessed In one machine cycle the same as Internal registers. ADVANCE INFORMATION Z89321 16-Brr DIGITAL SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION General. The Z89321 is a high-performance Digital Signal Processor with a modified Harvard-type architecture with separate program and data memory. The design has been optimized for processing power and minimizing silicon space. Instruction Timing. Many instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. When the program memory is referenced in internal RAM indirect mode, it takes three machine cycles. In addition, one more machine cycle is required if the PC is selected as the destination of a data transfer instruction. This only happens in the case of a register indirect branch instruction. An Acc + P => Acc; a(i) • b(j) -) P calculation and modification of the RAM pointers, is done in one machine cycle. Both operands, a(i) and b(j), can be located in two independent RAM (0 and 1) addresses. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply or multiply accumulate in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers where the least significant bits are important, the data should first be scaled by eight bits (or the multiplier and multiplicand by four bits each) to avoid truncation errors. Note that all inputs to the multiplier should be fractional two's complement 16-bit binary numbers. This puts them in the range [-1 to 0.99996951, and the result is in 24 bits so that the range is [-1 to 0.9999999]. In addition, if 8000H is loaded into both X and Y registers, the resulting multiplication is considered an illegal operation as an overflow would result. Positive one cannot be represented in fractional notation, and the multiplier will actually yield the result 8000H x 8000H = 8000H (-1 x -1 = -1). ALU. The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16 bits of which are connected to the 16-bit O-Bus. A shifter between the P-Bus and the ALU input port can shift the data by three bits right, one bit right, one bit left or no shift. Hardware Stack. A six-level hardware stack is connected to the O-Bus to hold subroutine return addresses or data. The Call instruction pushes PC+2 onto the stack. The RET instruction pops the contents of the stack to the PC. User Inputs. The Z89321 has two inputs, UIO and Ul1, which may be used by Jump and Call instructions. The Jump or Call tests one of these pins and if appropriate, jumps to a new location. Otherwise, the instruction behaves like a NOP. These inputs are also connected to the status register bits 810 and 811 which may be read by the appropriate instruction (Figure 5). User Outputs. The status register bits 85 and S6 connect directly to UOO and U01 pins and may be written to by the appropriate instruction. Interrupts. The Z89321 has three positive edge-triggered interrupt inputs. An interrupt is acknowledged at the end of any instruction execution. It takes two machine cycles to enter an interrupt instruction sequence. The PC is pushed onto the stack. A RET instruction transfers the contents of the stack to the PC and decrements the stack pointer by one word. The priority of the interrupts is INTO = highest, INT2 = lowest. Registers. The Z89321 has 12 physical internal registers and up to eight user-defined external registers. The EA2-EAO determines the address of the external registers. The /EI,/ROYE, and ER/IW signals are used to read or write from the external registers. 7-9 ADVANCE INFORMATION Z8932l l6-BIT DIGITAL SIGNAL PROCESSOR REGISTERS There are 12 internal registers which are defined below: Register P X y A SR Pn:b PC Register Definition Output of Multiplier, 24-bit X Multiplier Input, 16-bit Y Multiplier Input, 16-bit Accumulator, 24-bit Status Register, 16-bit Six Ram Address Pointers, 8-bit each Program Counter, 16-bit The following are virtual registers as physical RAM does not exist on the chip. Register Register Definition EXTn BUS On:b External Registers, 16-bit O-Bus Eight Oata Pointers EXTn are external registers (n = 0 to 7). There are eight 16-bit registers here for mapping external devices into the address space of the processor. Note that the actual register RAM does not exist on the chip, but would exist as . part of the external device such as an AOC result latch. BUS is a read-only register which, when accessed, returns the contents of the O-Bus. Dn:b refer to possible locations in RAM that can be used as a pointer to locations in program memory. The programmer decides which location to choose from two bits in the status register and two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At anyone time there are eight usable pointers, four per bank, and the four pOinters are in consecutive locations in RAM. For example, if S3/S4 =01 in the status register, then 00:0/01 :0/02:0/03:0 refer to locations 4/5/6/7 in RAM Bank O. Note that when the data pointers are being written to, a number is actually being loaded to Oata RAM, so they can be used as a limited method for writing to RAM. SR is the status register (Figure 5) which contains the ALU P holds the result of multjplications and is read-only. X and Yare two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. status and certain control bits (Table 4). The status re"gister may always be read in its entirety. S15-S 10 are set/reset by the hardware and can only be read by software. S9-S0 can be written by software (Table 5). Pn:b are the pointer registers for accessing data RAM, S 15-S 12 are set/reset by the ALU after an operation. S 11S10 are set/reset by the user inputs. S6-S0 are control bits described elsewhere. S7 enables interrupts. S8, if 0 (reset), allows the hardware to overflow. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. If S9 is 0, the shifter shifts data one bit left or right. If S9 is set and a shift is called for on a multiply instruction, then the shifter shifts the result three bits right instead of one bit right. (n = 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM BankOor 1). They can be directly read from or written to, and can point to locations in data RAM or Program Memory. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSB's and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. 7-10 Z89321 ADVANCE INFORMA nON N OV Z CUll SH3 OP 16·BIT DIGITAL SIGNAL PROCESSOR RPL Ram Pointer Loop Size a aa aa 1 a1a 256 2 4 8 all 1 aa 1 a1 11 a 111 16 32 64 128 'Short Form Direct' bits User Output a-I Interrupt Enable Overflow protection MPY output shifted by three bits User Input a-I (Read Only) Carry Zero Overflow Negative Figure 5. Status Register Table 4. Status Register Bit Functions Status Register Bit Function 815 (N) 814 (OV) 813 (Z) 812 (L) 811 (U11) 810 (UIO) ALU Negative ALU Overflow ALU Zero Carry User Input 1 User Input 0 89 (8H3) 88 (OP) 87 (IE) S6 (U01) S5 (UOO) S4-S3 S2-S0 (RPL) MPY Output Shifted by three bits Overflow Protection Interrupt Enable User Output 1 User Output 0 "Short Form Direct" bits RAM Pointer Loop Size Table 5. RPL Description S2 S1 SO Loop Size o o o o 0 0 1 1 0 1 0 1 256 2 4 8 0 0 1 1 0 1 0 1 16 32 64 128 7-11 - - - -.-----~--- - .------- Z89321 AD VA NeE IN FOR MATI 0 N 16-BIT DIGITAl SIGNAL PROCESSOR RAM ADDRESSING The address of the RAM is specified in one of three ways (Figure 6): RAM Pointers PO:O Pl:0 P2:0 q RAMO %FF ...--;.;;.;;;;.;;;...- %FF I @Pl:0 t---===-- %37 1-_"..;,;%;.;.03;;2;,;.1_ RAM Pointers -256 x 16-Bit --- 256 x 16-Bit V037 I RAMl -- - PO:l Pl:l P2:1 %04~-------------' %0321 -- S4 IS3 = 01 %00'--_ _ __ %00 - Data Pointers Internal ROM %OFFF DO --- :omV00321 01 :0 4K x 16-Bit -- @@Pl:0 %0321 %0000 %1234 --- 4- @00:1 00:1 01:1 02 :0 02:1 03 :0 03:1 Both of the Following Instructions Load %1234 into the Accumulator. LOA,@@Pl:0 LOA,@OO:l Figure 6. RAM, ROM, and Pointer Architecture Register Indirect Pn:b n = 0-2, b = 0-1 The most commonly used method is a register indirect addressing method, where the RAM address is specified by one of the three RAM address pointers (n) for each bank (b). Each source/destination field in Figures 7 and 10 may be used by an indirect instruction to specify a register pointer and its modification after execution ofthe instruction. ~ L....._ _ _ _ _ _ RAM Pointer Register Operation RAM Bank Figure 7. Indirect Register 7-12 Z8932l ADVANCE INFORMATION The register pointer is specified by the first and second bits in the source/destination field and the modification is specified by the third and fourth bits according to the following table: 03·00 Meaning OOxx 01xx 10xx llxx NOP +1 -l/LOOP +l/LOOP No Operation Simple Increment Decrement Modulo the Loop Count Increment Modulo the Loop Count xxOO xxOl xxl0 xxll PO:O or PO:l Pl:0 or Pl:l P2:0 or P2:1 See See See See Note a. Note a. Note a. Short Form Direct Notes: a. If bit 8 is zero, PO:O to P2:0 are selected; if bit 8 is one, PO:1 to P2:1 are selected. Direct Register The second method is a direct addressing method. The address of the RAM is directly specified by the address field of the instruction. Because this addressing method consumes nine bits (0-511) of the instruction field, some instructions cannot use this mode (Figure 8). l6-BIT DIGITAL SIGNAL PROCESSOR When LOOP mode is selected, the pointer to which the loop is referring will cycle up or down, depending on whether a -LOOP or +LOOP is specified. The size of the loop is obtained from the least significant three bits of the Status Register. The increment or decrementofthe register is accomplished modulo the loop size. As an example, if the loop size is specified as 32 by entering the value 101 into bits 2-00fthe Status Register (S2-S0) and an increment +LOOP is specified in the address field of the instruction, i.e., the RPi field is 11 xx, then the register specified by RPi will increment, but only the least significant five bits will be affected. This means the actual value of the pointer will . cycle round in a length 32 loop, and the lowest or highest value of the loop, depending on whether the loop is up or down, is set by the three most significant bits. This allows repeated access to a set of data in RAM without software intervention. To clarify, ifthe pointer value is 10101001 and if the loop = 32, the pointer increments up to 10111111, then drops down to 10100000 and starts again. The upper three bits remain unchanged. Note that the original value of the pointer is not retained. Figures 10 to 15 show the different register instruction formats along with the two tables below Figure 9. RAM Address Opcode Figure 8. Direct Internal RAM Address Format Short Form Direct Dn:b n =0-3, b =0-1 The last method is called Short Form Direct Addressing, where one out of 32 addresses in internal RAM can be specified. The 32 addresses are the 16 lower addresses in RAM Bank 0 and the 16 lower addresses in RAM Bank 1. Bit 8 of the instruction field determines RAM Bank 0 or 1. The 16 addresses are determined by a 4-bit code comprised of bits S3 and S4 of the status register and the third and fourth bits of the Source/Destination field. Because this mode can specify a direct address in a short form, all of the instructions using the register indirect mode can use this mode (Figure 9). This method can access only the lower 16 addresses in the both RAM banks and as such has limited use. The main purpose is to specify a data register, located in the RAM bank, which can then be used to pOint to a program memory location. This facilitates down-loading look-up tables etc. from program memory to RAM. b n3 n2 n1 nO 1081841831031021 T RAM Address RAM Bank Figure 9. Short Form Direct Address 7-13 =~-~-~-=--~------~---- -- ~~------------------- Z89321 ADVANCE INFORMATION 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION FORMAT T Source field Destination field RAM Bank selection Opcode Note: SourceJDesUnatlon fields can specify either register or RAM address in RAM pointer Indirect mode. Figure 10. General Instruction Format TableS. Registers Source/Destination Table 7. Register Pointers Field Register Source/Destination Meaning NOP +1 -1/LOOP +1/LOOP PO:O or PO:1" P1 :0 or P1: 1" P2:0 or P2: 1" 0000 0001 0010 0011 BUS"" X A OOxx 01xx 10xx 11 xx 0100 0101 0110 0111 SR STACK PC P"" xxOO xx01 xx10 xx11 Y 1000 1001 1010 1011 EXTO EXT1 EXT2 EXT3 1100 1101 1110 1111 EXT4 EXT5 EXT6 EXT? Short Form Direct Mode Notes: If RAM Bank bit is 0, then Pn:O are selected. If RAM Bank bit is 1, then Pn:1 are selected. ** Read only. When the short form direct mode is selected, 00000-01111 or 10000-11111 are used as RAM addresses. L-______ Short Immediate Data 000 001 010 011 100 1 01 11 0 111 Reg. Pointer PO:O Pl:0 P2:0 NA PO:l Pl:1 P2:1 NA Opcode 00011 Figure 11. Short Immediate Data Load Format 7-14 Z89321 16·Brr DIGITAL SIGNAL PROCESSOR ADVANCE INFORMATION 1st Word General Instruction Format 2nd Word Immediate Oata Figure 12. Immediate Data Load Format 10151014101301210111010109108107106 -r- 05104103102101100 j ACC Modification Codes o0 0 0 ROR Rotate right o0 0 1 ROL Rotate left 00 1 0 SHR Shift right 00 1 1 SHL Shift left o1 0 0 INC Increment (LSB) o1 0 1 DEC Decrement (LSB) o1 1 0 NEG Negate o1 1 1 ABS Absolute Condition Codes 0000 TRUE 0001··001 0 U01=0 0011 U01=0 0100C=0 0101 Z=O 01100V=0 0111N=0 1 xxx ...• 0000 TRUE 0001 •••• 0010 UOO=1 0011 U01=1 0100 C=1 0101 Z=1 0110 OV=1 0111 N=1 1 xx x •••• o= Negative Condition 1 = POSitive Condttlon Opcode 1001000 Figure 13. Accumulator Modification Format 7-15 Z89321 ADVANCE INFORMATION l6·BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION FORMAT (Continued) 1st Word xxxx Condition Codes 0000 TRUE 0001 --0010 UOO=O 0011 U01=O 0100 CoO 0101 ZoO 01100V=0 0111 N=O 1xxx - --- 0000 TRUE 0001 ---0010 UOO=I 0011 U01=1 0100 C=1 0101 Z=1 0110 OV=1 0111 N=1 1 xxx ---Condition 0= Negative Condition 1 = Positive Condition Opcode 0100110 Branch 0100100Call 2nd Word Branch Address Figure 14. Branching Format L..._ _ _ xxI 0 Reset Cflag xx 11 Set Cflag xlxO Reset IE Flag (Interrupt enable) x 1 xl Set IE Flag 1xxO Reset OP Flag (Overflow protection) 1 xx 1 Set OP Flag L..._ _ _ _ _ _ _ _ _ xxxx Opcode 1001010Mod Figure 15. Flag Modification Format 7-16 Z89321 ADVANCE INFORMATION 16-81T DIGITAL SIGNAL PRocESSOR ADDRESSING MODES This section discusses the syntax ofthe addressing modes supported by the DSP assembler. The symbolic name is used in the discussion of instruction syntax in the instruction descriptions. Table 8. Addressing Modes Symbolic Name Syntax Description Pn:b Pointer Register (Points to RAM) Dn:b Data Register X,Y,PC,SR,P EXTn,A,BUS Hardware Registers (Points to Program Memory) @A Accumulator Memory Indirect Direct Address Expression # Long (16-bit) Immediate Value # Short (a-bit) Immediate Value (POints to RAM) @Pn:b @Pn:b+ @Pn:b-LOOP @Pn:b+LOOP Pointer Register Indirect Pointer Register Indirect with Increment Pointer Register Indirect with Loop Decrement Pointer register Indirect with Loop Increment _ (Points to Program Memory) @@Pn:b @Dn:b @@Pn:b-LOOP @@Pn:b+LOOP @@Pn:b+ Pointer Register Memory Indirect Data Register Memory Indirect Pointer Register Memory Indirect with Loop Decrement Pointer Register Memory Indirect with Loop Increment Pointer Register Memory Indirect with Increment There are eight distinct addressing modes for transfer of data (Figure 6 and Table 8). , These two modes are used for simple loads to and from registers within the chip such as loading to the Accumulator, or loading from a pointer register. The names of the registers need only be specified in the operand field. (Destination first then source.) This mode is used for indirect accesses to the data RAM. The address ofthe RAM location is stored in the pointer. The "@" symbol indicates "indirect" and precedes the pointer, so@P1:1 tells the processor to read or write to a location in RAM 1, which is specified by the value in the pointer. This mode is also used for accesses to the data RAM but only the lower 16 addresses in either bank. The 4-bit address comes from the status register and the operand field of the data pointer. Note that data registers are typically used not for addressing RAM, but loading data from program memory space. 7-17 ~~-.-~~~~.~~~~~~~~-~ ----- ----------- - --~--- ~2iUJG Z89321 ADVANCE INFORMATION This mode is used for indirect, indirect accesses to the program memory. The address olthe memory is located in a RAM location, which is specified by the value in a pointer. So@@Pl:l tells the processor io read (write is not possible) from a location in memory, which is specified by a value in RAM, and the location of the RAM is in turn specified by the value in the pointer. Note that the data pointer can also be used for a memory access in this manner, but only one "@" precedes the pointer. In both cases the memory address stored in RAM is incremented by one each time the addressing mode is used to allow easy transfer of sequential data from program memory. l6·BIT DIGITAL SIGNAL PROCESSOR The direct mode allows read or write to data RAM from the Accumulator by specifying the absolute address of the RAM in the operand of the instruction. A number between 0 and 255 indicates a location in RAMO, and a number between 256 and 511 indicates a location in RAM1. This indicates a long immediate load. A 16-bit word can be copied directly from the operand into the specified register or memory. This can only be used for immediate transfer of 8-bit data in the operand to the specified RAM pointer. Similartothe previous mode, the address forthe program memory read is stored in the Accumulator. @A in the second operand field loads the number in memory specified by the address in A. CONDITION CODES The following defines the condition codes supported by the DSP assembler. If the instruction description refers to the (condition code) symbol in one of its addressing modes, the instruction will only execute if the condition is true. Name Description Name Description C EQ F IE MI NC NE NIE NOV NUO Carry Equal (same as Z) False Interrupts Enabled Minus No Carry Not Equal (same as NZ) Not Interrupts Enabled Not Overflow Not User Zero NUl NZ OV PL UO Ul UGE Not User One Not zero Overflow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero 7-18 ULT Z .2iu:D; Z89321 ADVANCE INFORMATION 16-Brr DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS Insl. Description Synopsis Operands ABS Absolute Value ABS[,] ,A A ADD Addition ADD, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 ADD A,#128 ADD A,DO:1 ADD A,@@LOOP ADD A,@P2:1+ ADDA,X AND Bitwise AND AND, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 AND A,#128 AND A,DO:1 AND A,@@PO:O+LOOP AND A,@P2:1+ , 2 2 2 2 CALL Subroutine call CALL [,l
Words Cycles Examples ABS NC,A ABSA ANDA,X CALL sub1 CALL Z,sub2 CCF Clear carry flag CCF None CCF ClEF Clear Carry Flag ClEF None ClEF COPF Clear OP flag COPF None COPF CP Comparison CP, A, A, A, A, A, A, DEC Decrement DEC [,] A, A DEC NZ,A DECA INC Increment INC [,l ,A A INC NZ,A INCA JP Jump JP [,]
, 1 1 3 1 1 1 2 2 2 2 CP A,PO:O CP A,D3:1 CP A,#512 CPA,@@PO:1 CP A,LABEL CPA,@DO:O CPA,X JP NIE,Label JP Label 7-19 Z89321 ADVANCE INFORMATION 16-BIT DIGITAL SIGNAL PROCESSOR INSTRUCTION DESCRIPTIONS (Continued) Insl. Descrlpllon Synopsis Operands LD Load destination with source LD, A, A, A, A, A, A, ,A , , , , , , , , ,<3ccind> , , , Words Cycles Examples 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 LDA,X LDA,DO:O LDA,PO:1 LDA,@@P1:1 LD A,MEMADDR LD MEMADDR,A LD DO:1.A LD P1:0#128 LDP1:1,X LD@PO:O+LOOP,'1234 LD@P1:1+,X LD X,PO:O LDY,PO:O LD SR,'%1023 LD PC,(A) LDX,@@PO:O LD Y,@P1:Q-LOOP LDSR,X Nole: When is , cannot be P. Nole: When is and is , cannot be EXTn if is EXTn, cannot be Xif is X, cannot be SR if is SR. Nole: When is <3ccind> cannot be A. MLD Multiply MLD,[,] , ,, , ,, MLDA@PO:O MLD A@P1:0,OFF MLD @P1:1 ,@P2:0 MLD @PO:1,@P1:0,ON Nole: If src1 is it must be a bank 1 register. Src2's for src1 cannot be X. Nole: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. MPYA Multiply and add MPYA ,[.] , ,, , ,, MPYAA@PO:O MPYA A,@P1:0,OFF MPYA @P1:1 ,@P2:0 MPYA@PO:1,@P1:0,ON Nole: If src1 is it must be abank 1 register. Src2's must be a bank 0 register. Nole: for src1 cannot be X. Nole: Forthe operands , the defaults to OFF. For the operands , the defaults to ON. 7-20 --~ 4'2i1.ClG Insl. Description MPYS Multiply and subtract Z89321 16-81T DIGITAL SIGNAL PRocEssoR ADVANCE INFORMATION Synopsis Operands Words Cycles MPYS,I.] , ,, , ,, Examples MPYS A,@PO:O MPYS A,@P1 :O,OFF MPYS @P1:1,@P2:0 MPYS@PO:1,@P1:0,ON Nola: If src1 is it must be abank 1register. Src2's must be abank 0 register. Nola: for src1 cannot be X. Nola: For the operands , the defaults to OFF. Forthe operands, the defaults to ON. NEG Negate NEG ,A ,A A NEG NZ,A NEG A NOP No operation NOP None NOP OR Bitwise OR OR , A, A, A, A, A, A, A, POP Pop value from stack POP PUSH Push value onto stack PUSH RET Return from subroutine RET None 1 1 2 1 1 1 1 1 1 2 3 1 1 1 ORA,1128 ORA,OO:l OR A,@@PO:Il+LOOP ORA,@P2:1+ ORA,X POP PO:O POP 00:1 POP@PO:O POPA POP BUS 1 1 1 1 2 1 1 1 1 1 1 2 3 3 2 PUSH PO:O PUSH 00:1 PUSH@PO:O PUSH A PUSH BUS PUSH 112345 PUSH@A PUSH@@PO:O RET RL Rotate Left RL,A ,A A RLNZ,A RLA RR Rotate Right RR,A ,A A RR NZ,A RR A 7-21 ~~~.~----------------- ----------- ~2il.JJG Z89321 16·Brr DIGITAL SIGNAL PROCESSOR ADVANCE INFORMATION INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis Operands SCF Set Cflag SCF None SCF Words Cycles Examples SIEF Set IE flag SIEF None SIEF SLL Shift left logical SLL [,]A A SLL NZ,A SLL A SOPF Set OP flag SOPF None SOPF SRA Shift right arithmetic SRA,A ,A A SRANZ,A SRAA SUB Subtract SUB, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 A, A, A, A, A, A, A, 1 1 2 1 1 1 1 XOR Bitwise exclusive OR XOR , Bank Switch Enumerations. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether a bank switch is set on or off. To more clearly represent this two keywords are used (ON and OFF) which 7·22 1 1 2 3 1 1 1 1 1 2 3 1 SUB A,#128 SUB A,DO:l SUB A,@@PO:D+LOOP SUB A,@P2:1+ SUB A,X XORA,#128 XOR A,DO:l XOR A,@@PO:D+LOOP XOR A,@P2:1+ XORA, X 1 1 state the direction of the switch. These keywords are referred to in the instruction descriptions via the symbol. Z89321 ADVANCE INFORMATION 16·BIT DIGITAL SIGNAL PROCESSOR ABSOLUTE MAXIMUM RATINGS Symbol Description Min. Max. Units Vee TSTG TA Supply Voltage (*) Storage Temp Oper Ambient Temp -0.3 -65 0 +7.0 +150 0 V C t C Notes: • Voltage on all pins with respect to GND. t See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability . STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Figure 16). 2.1 KG From Output 0 - - - - . . - _ _ 4........-10--...... Under Test Figure 16. Test Load Diagram DC ELECTRICAL CHARACTERISTICS = -40 o e to + 105°e unless otherwise specified) (V00= 5V ± 10%, TA Symbol Parameter Condition 100 Supply Current loe DC Power Consumption Voo= 5.25V fclock = 10 MHz Voo= 5.25V V1H V1L IL Input High Level Input Low Level Input Leakage VOH VOL IFL Output High Voltage Output Low Voltage Output Floating Leakage Current Min. Max. Units 60 mA 5 mA 0.1 Voo 1 V V !lA 0.5 5 V V !lA 0.9 Voo IOH= -100!lA IOL = 0.5 mA Voo-0.2 7-23 ADVANCE INFORMATION Z89321 16·Brr DiGITAL SIGNAL PROCESSOR AC ELECTRICAL CHARACTERISTICS (Voo = 5V ±10%, TA = -40°C to +105°C unless otherwise specified) Symbol Parameter TCY PWW Tr Tf Clock Clock Clock Clock TEAD TXVD TXWH TXRS TXRH TIED RDYS RDYH EA(2:0) Min. Max. Units 100 45 2 2 1000 ns ns ns ns EA,ER/fW Delay from CK EXT Data Output Valid from CK EXT Data Output Hold from CK EXT Data Input Setup Time 15 5 15 15 25 25 ns ns ns ns EXT Data Input Hold from CK lEI Delay Time from CK Ready Setup Time Ready Hold Time 0 0 10 0 15 ns ns ns ns Cycle Time Pulse Width Rise Time Fall Time Valid Address Out IROYE Figure 17. Write To External Device Timing 7·24 4 4 5 ADVANCE INFORMA T/ON Z89321 16-BIT DIGITAL SIGNAL PROCESSOR TXRH ~---------TCY----------~~~ TXRS CK TIED lEI ERlIW EXT (15:0) EA(2:0) EXT Bus: Input Valid Data In Valid Address Out IRDYE Figure 18. Read From External Device Timing 7-25 -- ---~---~----------- ADVANCE INFORMATION . Z89321 16-BIT DIGITAL SIGNAL PROCESSOR PACKAGE INFORMATION D Dl- ~ 6 1 40 39 i 1 I r-'-'-+'-'-'I I 11 i 18 EI E ill ea SYHBIlL N[JTES' • 1, C[JNTR[JLLING DIMENSI[JNS • INCH 2, LEADS ARE C[JPLANAR "'ITHIN ,004 IN. 3. DIMENSION • .JIlL INCH A AI DIE DI/£I D2 II MILLIMETE'R MAX MIN 4.57 4.27 2.67 2.92 17.40 17." 16.51 16.66 15.24 16.00 1.27 TYP 44-Lead PLCC Package Diagram 7-26 INCH MAX MIN .168 .180 .IDS .IIS .685 .695 .656 .650 ,600 .630 ,050 TYP ADVANCE INFORMATION Z89321 16-BIT DIGITAL SIGNAL PROCESSOR ORDERING INFORMATION Z89321 10 MHz 44-pin PLCC Z8932110VSC Z8932110VEC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package V =Plastic PLCC Temperature S =O°C to +70°C E = -40°C to +105°C Speed 10 = 10 MHz Environmental ~ C = Plastic Standard Example: Z 89321 10 V S C L§ is a Z89321, 10 MHz, DIP, O°C to +70°C, Plastic Standard Flow. Environmental Flow lemperature Package Speed Product Number Zilog Prefix 7-27 .2;1 CD, 189320 16..Blt Mixed P;I Signal Processor iii 12 Signal Processor 18932116..Bit Mixed Support Product Information Superintegration™ Products Guide Literature Guide and Third Party Support ZUog Sales Offices Representatives &Distributors II!' aw DSP DATABOOK SUPPORT PRoDUCTS Z86C9500ZCO EVALUATION BOARD PRODUCT SPECIFICATION SUPPORTED DEVICE: Z86C9S KIT CONTENTS DESCRIPTION The ZS6C9500ZCO Evaluation Board contains an assembled circuit board, software and documentation for use in evaluating the ZS6C95 ZSiI/DSP microcontroller. The board comes equipped with a monitor program which provides access to all the ZS6C95 registers and on-board memory and assists in using the ZS6C95. SPECIFICATIONS Power Requirements +3 ~ f!JllJy~~" IiC32 ~ U9 U9 iLIC.. .. !IIO -~~ --r-Lo-iLo--1-!!II :_ KI , I __---=_~ ...... :-a -1£" .... §!:@ PIlI JNTEAFAC£ OTI-OIB PIN OUT POHER ON RESET r ~ _ _ ~I 11-91~1 ~191 ~19I ~l ~191 ~19 9 ~ 9~ ]IDI flit f::tlrrilltriririto-:J'iririr PI J .. Z89C99 Evaluation Board , Schematic 2 0"2 .' I ~ ~~ ;;&Ii!' 2= il~ DSP DATABOOK SUPPORT PRODUCTS Z89COOOOZEM IN CIRCUIT EMULATOR· COO PRODUCT SPECIFICATION SUPPORTED DEVICE: Z89COO DESCRIPTION Z89COO EMULATOR The Z89COOOOZEM is a member of Zilog's ICEBOXm product family of in-circuit emulators. The ICEBOX -COO provides emulation for Zilog's Z89COO DSP core. This includes all the essential DSP timing and I/O circuitry which simplifies user emulation of the prototype hardware/ software product. The ICEBOX can be connected to a serial port COM 1 through COM 4 of the host computer (IBM~ 386,486, or compatible). ZS Emulation Base Board The ICEBOX provides basic support of a emulator (program execution, single step, jump, halt, breakpoint, download/upload program code, etc.). In addition, 64 K x 16 program memory in steps of 4K, 8K, 16K, 32K, and 64K (software selectable), 64K breakpoint support, maximum internal clock frequency of up to 16 MHz. The host software runs under both MS Windows 3.0 and 3.1, it creates the Graphical User Interface (GUI) for the COO ICEBOX. The software trace and symbolic debugging features give a big advantage for user code debugging. SPECIFICATIONS ZS9COO Emulation Daughter Board Z89COO DSP ICE Chip Five 64K X 4 Static RAM 80/60 Pin Target Connectors 100-Pin HP-16500 Interface Board Connector Cables 12", 68-Pin PLCC Emulation Cable 15", Power Cable with Banana Plugs 60", DP25 RS-232C Cable Software (IBM PC platform) ICEBOXm GUI Host Package Documentation Emulation Specification Maximum Emulation Speed: CMOS Z86C9120PSC 8K X 8 EPROM (Programmed with Debug Monitor) 32K X 8 Static RAM RS-232C Interface Three 64K X 4 Static RAM 16 MHz Z8 ICEBOXm User Manual ICEBOX GUI User Manual Registration Card N Power Requirements +5 Vdc@ 1.5A Dimensions Width: Length: ORDERING INFORMATION Part No: Z86COOOOZEM 6.0 in. (15.2 cm) 8.8 in. (22.4 cm) Serial Interface RS-232C @ 19200 baud 8-7 DSP DATABOOK SUPPORT PRODUCTS Z89COOOOZAS Z89COO ASSEMBLER, LINKER AND LIBRARIAN PRODUCT SPECIFICATION SUPPORTED DEVICE: Z89COO DESCRIPTION The l89COa Macro Assembler The l89Caa Librarian The Z89CDD Macro Assembler (Z89ASM) generates relocatable object code modules in IEEE 695 OMF format. The assembler also handles macros and conditional assembly, eliminating the need for a macro preprocessor. The Z89CDD Librarian (Z89L1B) is the librarian facility. The librarian can be used to place the re-Iocatable object files in a library. In this way, the user can collect user-defined modules which allows commonly used routines to be easily included in programs. The l89COa Linker The Z89CDD Linker (Z89L1NK) links object modules produced by the assembler. The linker produces two files: • • an absolute object file in Motorola S-record format, and an optional comprehensive linkmap file. Linking offers the benefits of: • • • smaller, faster-assembling modules, use of local and global variables, and ease of relocating to a specified address. Linking lets the user develop commonly-used routines separately, test them, and link them to programs under development. The PLC Z89CDD Macro Assembler/Linker/Librarian requires an IBM$ PC or true compatible with: • • • DOS 3.2 or higher, a hard drive, and a floppy drive. The real-mode version requires at least 64DK of RAM. The protected-mode version requires: • • an 80386 or 80486 CPU and 2 Mbytes of RAM with at least 1 Mbyte of extended memory free. KIT CONTENTS Software (IBM PC platform; Assembler, linker, librarian Documentation Macro Assembler/linker/librarian User's Guide. Registration Card. ORDERING INFORMATION Part No: 8-8 Z89CDOOOZAS DSP DATABOOK SUPPORTPRoouClS l89CDDDDlCC l89CDD C CROSS COMPILER PRODUCT SPECIFICATION SUPPORTED DEVICE: Z89COO DESCRIPTION KIT CONTENTS The Z89COOOOZCC produces assembly language code which can be assembled and linked with Z89COOOOZAS. After linking, the code can then be simulated and debugged using the Z89COOOOZDB or Z89COOOOZSM. Software (IBM PC platform) The Z89COOOOZCC requires an IBMiI> PC or true compatible with: C Cross Compiler Documentation ANSI C Cross Compiler User's Manual Registration Card ORDERING INFORMATION • • • DOS 3.2 or higher a hard drive, and a floppy drive. Part No: Z89COOOOZCC The real-mode version re_quires at least 640K of RAM. The protected-mode version requires: • • an 80386 or 80486 CPU and 2 Mbytes of RAM with at least 1 Mbyte of extended memory free. 8-9 ------------------ -------------------- ---- --------~ DSP DATABOOK SUPPORT PRODUCTS Z89COOOOZEM IN CIRCUIT EMULATOR -COO PRODUCT SPECIFICATION SUPPORTED DEVICE: Z89COO DESCRIPTION KIT CONTENTS The Z89COOOOZEM is a member of Zilog's ICEBOX product family of in-circuit emulators. The ICEBOX -COO provides emulation for Zilog's Z89COO DSP core. This includes all the essential DSP timing and I/O circuitry which simplifies user emulation of the prototype hardware/ software product. The ICEBOX can be connected to a serial port COM 1 through COM 4 of the host computer (IBM" 386,486, or compatible). N The ICEBOX provides basic support of a emulator (program execution, single step, jump, halt, breakpoint, download/upload program code, etc.). In addition, 64 K x 16 program memory in steps of 4K, 8K, 16K, 32K, and 64K (software selectable), 64K breakpoint support, maximum internal clock frequency of up to 16 MHz. The host software runs under both MS Windows 3.0 and 3.1, it creates the Graphical User Interface (GUI) for the COO ICEBOX. The software trace and symbolic debugging features give a big advantage for user code debugging. Z89COO Emulator Z8 Emulation Base Board CMOS Z86C9120PSC 8K X 8 EPROM (Programmed with Debug Monitor) 32K X 8 Static RAM RS-232C Interface Three 64K X 4 Static RAM Z89COO Emulation Daughter Board Z89COO DSP ICE Chip Five 64K x 4 Static RAM 80/60 Pin Target Connectors 100-Pin HP-16500 Interface Board Connector Cables 12", 68-Pin PLCC Emulation Cable 15", Power Cable with Banana Plugs 60', DP25 RS-232C Cable Software (IBM PC platform) ICEBOXN GUI Host Package SPECIFICATIONS Documentation Emulation Specification ~.4ax!mum Emu!ation Speed: 16 MHz Z8 ICEBOX User Manual ICEBOX GUI User Manual Registration Card N N Power Requirements +5 Vdc@ 1.5A Dimensions Width: 6.0 in. (15.2 cm) Length: 8.8 in. (22.4 cm) Serial Interface RS-232C@ 19200 baud 8-10 ORDERING INFORMATION Part No: Z89COOOOZEM DSP DATABOOK SUPPORT PRooUCTS Z89COOOOZHP LOGIC ANALYZER ADAPTER BOARD PRODUCT SPECIFICATION SUPPORTED DEVICES: L7X, C67/121, C65/120, COO DESCRIPTION KIT CONTENTS The ICEBOX/H-P Logic Analyzer Adapter Board provides the owner of a Hewlett-Packard Logic Analyzer (model #16500A) with real-time trace capabilities for the Zilog ICEBOX Emulator. The adapter board interfaces to the H-P Logic Analyzer probes and ICEBOX interface connector. At the touch of a button, the captured code can be disassembled, providing a complete listing of program flow in native assembly language on the analyzer screen. This simple and low-cost setup transforms the logic analyzer into a powerful tool for software debugging. ICEBOX/H-P Logic Analyzer Adapter Board 10, 18-Pin DIP RC Network ICs 100-Pin ICEBOX Interface Connector 5, H-P 165XX Logic Analyzer Connectors SPECIFICATIONS Dimensions Width: Length: 4.9 in. (12.4 cm) 5.4 in. (13.7 cm) Cables 2", 100-Pin Cable Software (IBM-PC Platform) Z89COO Disassembler Software Z8~ Disassembler Software (future support) Documentation H-P Adapter Board User Guide ORDERING INFORMATION Part No: Z89COOOOZHP 8-11 DSP DATABOOK SUPPORT PRODUCTS Z89COOOOZSD Z89COO SIMULATOR!DEBUGGER PRODUCT SPECIFICATION DEVICE SUPPORTED: Z89COO DESCRIPTION The Z89COO Simulator is designed to work with the PLC Z89COO development tools to simulate code written with those tools. The simulator interacts with the user through a userdefined, windowed interface. The user has complete control over what each window looks like, where it is located on the screen, when it is displayed, and what information the window contains. Thus, the simulator display may be tailored to a specific application. The debugger is designed to work with the PLC Z89COO and Z8'" development tools to debug code written with these tools. The debugger supports several DSP and Z8 devices and must be used in conjunction with the appropriate simulator and assemblers for a particular device. The debugger interacts with the user through a userdefined, windowed interface. The user has complete control over what each window looks like, where it is located on the screen, when it is displayed, and what information the window contains. Thus, the debugger display may be tailored to a specific application. The Simulator (Z89SIM) and Debugger (Z89BUG) requires an IBM'" PC or true compatible with: • • • DOS 3.2 or higher, a hard drive, and a floppy drive. The real-mode version requires at least 640K of RAM. The protected-mode version requires: • • an 80386 or 80486 CPU and 2 Mbytes of RAM with at least 1 Mbyte of extended memory free. KIT CONTENTS Software (IBM PC platform) Simulator Documentation Z89COO Simulator User's Guide Z89COO Debugger User's Guide Registration Card Features include: • • • • • • • • 8-12 Source code window All registers are displayed, and can be modified. Single step or operate at full speed. Break points can be set. Disassembler with line assembler. RAM and ROM windows. Clock/time count Mouse option for user interface ORDERING INFORMATION Part No: Z89COOOOZSD DSP DATABOOK SUPPORT PRODUCTS Z8912000ZEM IN CIRCUIT EMULATOR ·120 PRODUCT SPECIFICATION SUPPORTED DEVICES: Z89120, Z89920 KIT CONTENTS DESCRIPTION The Z89C6500ZEM is a member of Zilog's ICEBOX'" product family of in circuit emulators. The emulator provides emulation support for Zilog's Z89120 and Z89920 microcontroliers. This includes ali the essential MCU timing and 1/0 circuitry which simplifies user emulation of the prototype hardware andlor software. Data entering and program debugging are performed by the monitor ROM and the Host Package which communicates via a RS-232C serial interface with a fixed 19200 baud rate. The user program can be downloaded directly from the host computer via the RS-232C connector and may then be executed using various debugging commands in the monitor. The ICEBOX can be connected to a serial port COM1 or COM2 of the host computer (IBM~ XT, AT, 286, 386 or 486 compatible). SPECIFICATIONS Emulation Specification Maximum Emulation Speed: Power Requirements +5 Vdc@ 1.4 A Operating Temperature 0° to 50°C Dimensions Width: 6.25 in. Length: 9.50 in. Height: 2.50 in. Serial Interface RS-232 @ 19200 baud 20.48 MHz Z89C65 Emulator Z8m Emulation Base Board CMOS Z86C91120PSC 8K X 8 EPROM (Programmed with Debug Monitor) EPM5128 EPLD 32K X 8 Static RAM Three 64 X 4 Static RAM RS-232C Interface Reset Switch Z89C65 Emulation Daughter Board Z86C5020GSE ICE Chip CD2400 Two EPM5128 EPLD Two EPM5192 EPLD 32K X 8 Static RAM, 16Kx8 Static RFA - 2 each Six HP-16500A Logic Analysis System Interface Connectors 80/60 Pin Target Connectors Cables 12', 68-Pin PLCC Emulation Cable 15', Power Cable with Banana Plugs 60", DP25 RS-232C Cable Software (IBM PC platform) Z8~/Z80~/Z8000~ Cross Assembler MOBJ Link!Loader Host Package Includes Windows and non-Windows software for emulation Documentation Z8 ICEBOX User Manual Z89120 User Manual Supplement Z8 Cross Assembler User's Guide MOBJ Link/Loader User Guide Registration Card ORDERING INFORMATION Part No: Z8912000ZEM 8-13 Z89320 16.. Blt Mixed Signal Processor Z89321 16..Blt Mixed Signal Processor Support Product Information Superintegration™ I! Products Guide ~ Literature Guide and Third Party Support ZUog Sales Offices Representatives & Distributors E Block Diagram 256 BYTES 1512 WORD RAM RAM 8-BIT 10-BIT ND ~ , DIA ESCC zoo CPU MMUI osc Part # Z89COO Z89120 Z89920 Z84C15 Z80182 Z80180 Z85230 DescripHon 16-Bit Digital Signal Processor Zilog Modem/Fax Controller (ZMFC) ZHog Modem/Fax Controller (ZMFC) IPCIEIPC Controller Zilog Intelligent Peripheral (ZIP' High-performance zao- CPU with peripherals Enhanced Serial Com. Controller Process/Speed CMOS 10,15 MHz CMOS 20 MHz CMOS 20 MHz CMOS 6,10,16 MHz CMOS 16, 20 MHz 6, a, 10, 16", 20' 'ZaSloo only CMOS a, 10,16, 20 MHz Features 16-bit Mac 75 ns 2da1a RAMs (256 words each) 4Kword ROM 64Kx16 Ext. ROM 16-bit I/O Port 74 instructions Most single cycle Two conditional branch inputs, two user outputs library of software macros available zero overhead pointers ZS· controlier with 24 KbYte ROM 16-bit DSP with 4Kword ROM B-bitND lD-bit D/A (PWM) library of software macros available 47 vO pins Two comparators Independent za· and DSP Operations Power-Down Mode ZS w/64K external memOlY DSP w/4K word ROM a-bitND lD-bitD/A library of macros 47 pins Two comparators Independent lB- and DSP Operations Power-Down Mode ZOO- CPU, SIO, CTC WDT, CGC The zao Family in one device Power-On Reset Two chip selects 32-bit CRC WSG EVmode' 3 and 5 Volt Version Complete Static Version ofZ1oo-plus ESCC (2 channels of Z85230) 16550 MIMIC 24 Parallel VO Emulation Modes' Enhanced zao· CPU MMU1Mbyte 2DMAs 2 UARTs with BRGs ClSerial VO Port Oscillator Z8S1aO includes; Pwr dwn, Prgmble EM I, divlde-by-one clock option Full dual-channel SCC plus deeper FIFOs: 4 bytes on Tx S bytes on Rx DPLL counter per channel Software compatible toSCC Package 68-pin PLCC 6D-pinVOFP 68-pin PLCC 68-pin PLCC loa-pin OFP laO-pin VOFP loa-pin OFP loa-pin VOFP 64-pin DIP 6S-pin PLCC aD-pin OFP 4D-pin DIP 44-pin PLCC Other ApplicaHons 16-bit General-Purpose DSP TMS 32010/20/25 applications Multimedia-Audio Voicemail Speech Storage and Transmission Modems FAXes, Sonabouys Multimedia-Audio Voicemail Speech Storage and Transmission Modems FAXes, Sonabouys Intelligent peripheral controllers Modems General-Purpose Embedded Control Modem, Fax, Data Communications Embedded Control General-Purpose datacom. High performance SCC software compatible upgrade va , (J) ro Block Diagram II UAR;r ___ Is II Z86C911Z8691 Description ROMlessl8~ l8~ 8KOTP Process/Speed CMOS 16 MHz (C91) NMOS 12 MHz (91) Features I I Z89C~O I Z86E21 Part # DlvT MLiLi1 UART CPU DSP DAC PWM ADC SPI P2 I P3 I A15-0 MULTIDIVluART 512 RAM 14K ROM OSP 16-81T MAC DATA RAM 1/0 1/0 CPU IOSC 256 RAM ICLOCK POlp11p21p3 I Z86C93 I Z86C95 Z86018 16-Bit Digital Signal Processor I Enhanced l8e I Enhanced l8~ with DSP lilog Datapath Controller (lDPC) CMOS 12, 16 MHz CMOS 10, 15 MHz I CMOS 20, 25 MHz I CMOS 24 MHz CMOS 40 MHz Full duplex UART 2 Standby Modes (STOP and HALT) 2xSbit Counter/Timer 8KOTP ROM 256 Byte RAM Full-duplex UART 2 Standby Modes (STOP and HAL 2 Counter/Timers ROM Protect option RAM Protect option Low EMI option 16-bit Mac 75 ns 2 data RAMs (256 words each) 4Kwold ROM 64Kxl1l Ext. ROM 16-bitl/O Port 74 inslructions Most single cycle Two conditional branch inpuls, two user outputs Library of software macl'Os available zero overhead pointers 16x16 Multiply 1.7 ~ 32x16 Divide 2.0 ~ Full duplex UART 2 Standby Modes (STOP and HALT) 3 16-bit Counter/Timers Pin compatible to l86C91 (PDIP) 4o-pin DIP 44-pin PLCC 44-pin QFP 4o-pin DIP 44-pin PLCC 44-pin QFP 68-pin PLCC 6o-pin VQFP 4o-pin DIP 44-pin PLCC 44-pin QFP 48-pin VQFP Software Debug Z8~ protoiyping Z8~ production runs Card Reader Disk Drives Tape Drives Servo Control Motor Control Disk Drives Tape Drives Modems n 8 channel 8-bit ADC, 8-bit DAC 16-bit Multiply/Divide Full duplex UART SPI (Serial Peripheral Interface) 3 Standby Modes (STOP/HALT/PAUSE) Pulse Width Modulator 3x16-bit timer 16-bit DSP slave processor 83 ns Mult./Accum Full track read Automatic data transfer (Point & Go~) S8-bit Reed Solomon ECC 'on the fly' Full AT/IDE bus interface 64 KB SRAM buffer 1 MB DRAM buffer Split data field support 1OO-pin VQFP package JTAG boundary scan option Up to 8 KB buffer RAM reselVed for MCU I Package I Application -I Disk Drives Modems I Tape Drives 18O-Pin QFP 84-pin PLCC l00-pin VQFP I Disk Drives Tape Drives Servo Control Motor Control l00-pin VQFP 100-pin QFP I Hard Disk Drives Block Diagram II ROM UART : """' ..... 1 III 4KROM II Z8 24K* OSP 4K ROM ROM NO O/A 31'/47 DIGITAL I/O Part # CP I c.> DSP Z8 24KROM' 6KROM RAM PORT GODEC INTF. RAM PWM REFRESH 27'143 DIGITAL VO Z8 DSP 32KROM 6KROM RAM PORT CODEC INTF. RAM PWM REFRESH 43 DIGITAL 110 DSP Z8 32KROM 8KROM RAM PORT CODEC INTF.I RAM REFRESH CODEC INTF.I 27'/43 DIGITAL VO DSP Z8 24KROM' 8KROM RAM PORT COOEC INTF. RAM CODEC INTF. REFRESH 27'/43 DIGITAL 110 Z08600/Z08611 Z86C30/E30 Z86C40/E40 Z89C65!C66 Z89C67/C68 Z89C69 Z89167/168 Description Za-NMOS (CCPj 8600= 2K ROM 8611 =4KROM ZS- Consumer Controller Processor (CCPj with4KROM C30= 28-pin C40=40-pin E30/E40 = OTP version Telephone Answering Controller with DSP LPC voice synthesis and DTMF detection, Extemal RAM /RAM Interface (COO) Telephone Answering Controller with digital voice encode and decode OTMF detection and full memory control interface. Ext. ROM/RAM InHc. (C68) Telephone Answering Controller with digital voice encode and decode DTMF detection and full memory control interface Enhanced telephone answering controller with digital yoice encode and decode DTMF detection and full memory controller intlc. ext. ROM/RAM inHc. (16S) Enhanced telephone answering controller with digital voice encode and decode DTMF detection and full memory controller interface Process/Speed NMOSS,12 MHz CMOS 12 MHz CMOS 20 MHz CMOS 20 MHz CMOS 20 MHz CMOS 24 MHz CMOS 24 MHz Features 2K/4KROM 12S Bytes RAM 22/32 VO lines On-chip oscillalDr 2 Counter/Timers 6vectored, priority interrupts UART (Z8611) 4K ROM, 236 RAM 2 Standby Modes 2 Counter/Timers ROM Protect RAM Protect 4 Ports (86C40/E40) 3 Ports (86C30/E30) Brown-Out Protection 2 Analog ComparalDrs LowEMI Watch-Dog TImer Auto Power-On Reset Low Power option Za- Controller 24K ROM (C65) 16-bit DSP 4KWordROM 8-bit NO with AGC DTMF macro available LPC macro available lO-bitPWM D/A Other DSP software options available 47 I/O Pins (C65) ZS- Controller 24K ROM (C67) 16-bitDSP 6KWordROM DTMF macro available LPC macro available lO-bit PWM D/A Other DSP srw opt avail. ARAM/DRAM/ROM Controller & Interface Dual Codec Interface 43 I/O (C67) ' =Note Z89C68 is ROMless (18) with 271/0 pins ZS- Controller 32KROM 16-bitDSP 6KWord ROM DTMF macro available LPC macro available lo-bit PWM D/A Other DSP software options available ARAM/DRAM/ROM Controller & Interface Dual Codec Interface 43VO ZS- Controller 24K ROM (167) 16-bit DSP SKWord ROM DTMF Macro available LPC Macro available lO-bit PWM D/A Other DSP software options available ARAM/DRAM/ROM Dual Codec Interface 43 VO (167) '= Note Z89168IS ROMless (Z8) with 27 I/O pins ZS- Controller 32KROM 16-bit DSP SKWord ROM DTMF Macro available LPC MaQ'o available lO-bit PWM D/A Other DSP software options available ARAM/DRAM/ROM Dual Codec Interface 43VO ' =Nlie Z89C66ls ROMI... (ZS) with 31 I/O pins. Package 28-pin DIP 4O-pin DIP 44-pin PLCC 28-pin DIP 4o-pin DIP 44-pin PLCC, QFP 68-pin PLCC 84-pin PLCC 84-pin PLCC S4-pin PLCC 8o-pin QFP Application Low cost tape board TAD Window Control Wiper Control Sunroof Control Security Systems TAD Fully featured cassette answering machines with Yoice prompts and DTMF signaling Digital OGM available 'Voice Processing, DSP applications in tapeless TAD and other high-perfomnance voice processors Voice Processing, DSP applications in tapeless TAD and other high-performance voice processors Voice Processing, DSP applications in tapeless TAD and other high-performance Yoice processors I IZ89169 I 84-pin PLCC SO-pin QFP Voice Processing, DSP applications in tapeless TAD and other high-performance voice processors en ./:. Block Diagram SKROM 6KROM 4KCHAR ROM 3KCHAR ROM IU_CHARROM COMMAND IlHERPRETER - , ...... , --_. ,- Part # ~-- -, Z86C27/127/97 J' ..... , --_. r - -- -, Z86227 ANALOG SYNC/DATA 8lrPL SLICER - '-- Z861l!8 1K/6K ROM Z8 GPU WDr P2 124 RAM P3 Z86L06/L29 Z86L70mm (Q193) I Z86C40/E40 I Description ZS'" Digital Television Controller MCU with logic functions needed for Television Controller, VCRs and Cable Standard DTC features with reduced ROM, RAM, PWM outputs for greater economy Line 21 Controller (L21cn) for Closed Caption Television 18-pin ZS'" Consumer' Controller Processor (CCP,,) low-voltage and low-current battery operation lK-6K ROM Process/Speed CMOS4 MHz CMOS4 MHz CMOS 12 MHz Low Voltage CMOS SMHz Low Voltage CMOS SMHz CMOS 12 MHz ZS/OTC Architecture SK ROM, 256-byte RAM 160x7-bitvideo RAM On-Screen Display (OSD) video controller Programmable color, size, position attributes 13 PWMs for D/A conversion 12S-character set 4Kx6-bit char. Gen. ROM Watch-Dog Tirner (WDT) Brown-Out Protection 5 Ports/36 pins 2 Standby Modes I Low EMI Mode Z8/0TC Architecture 6K ROM, 256-byte RAM 120x7-bit video RAM OSD on board Programmable color, size, pOSition attributes 7PWMs 9&-character set 3Kx6-bit character generator ROM Watch-Dog Timer (WDT) Brown-Out Protection 3 Ports/20 pins 2 Standby Modes Low EMI Mode Conforrns to FCC Line 21 format Parallel or serial modes Stand-, lone operation On-board data sync anc slicer On-board character ger'erator - Color - Blinking -Italic - Underline ZS'" Architecture lK ROM & 6K ROM Watch-Dog Timer 2 Analog Comparators with output option 2 Standby Modes 2 Counter/Timers Auto Power-On Reset 2 volt operation RC OSC option Low Noise option Brown-Out Protection High current drivers (2, 4) ZS'" Architecture 2K1SKl16K ROM Watch-Dog Timer 2 Analog Comparators with output option 2 Standby Modes 2 Enhanced Counter/ Timers, Auto Pulse Reception/Generation Auto Power-On Reset 2 volt operation RC OSC option Brown-Out Protection High current drivers (4) I52-pin 64-pin DIP active (127) 4o-pin DIP 18-pin )IP lS-pin DIP 18-pin SOIC 2o-pin DIP (L71), 14O-Pin DIP 18-pin DIP, SOIC (L70) 40,44-pin DIP, PLCC, QFP (L72) Low-end Television Cable/Satellite Receiver TVs, VC Rs, Decoders I.A. Controller Portabte battery operations I.A. Controller Portable battery operations Features Package Application Low-end Television Cable/Satellite Receiver ZS'" (CCP,,) low-voltage parts that have more ROM, RAM and special Counter/Timers for automated output drive capabilities ZS'" Consumer Controller Processor (CCP") with 4K ROM (C40) E40 = OTP version 4K ROM, 236 RAM 2 Standby Modes 2 Counter/Timers ROM Protect RAM Protect 4 Ports Brown-Out Protection 2 Analog Comparators LowEMI Watch-Dog Timer Auto Power-On Reset Low Power option I Window Control Wiper Control Sunroof Control Security Systerns TAD I Z86C61/62 I ZS'" MCU with Expanded I/O's and 16K ROM CMOS 16, 20 MHz 16K ROM Full duplex UART 2 Standby Modes (STOP and HALT) 2 Counter/Timers ROM Protect option RAM Protect option Pin compatible to ZS6C21 C61 =4Ports C62 = 7 Ports 14O-Pin DIP (C61) 44-pin PLCC,QFP (C61) 6S-pin PLCC (C62) I Cable Television Rernote Control Security Block Diagram Part # Description Processl Speedl Clock Data Rate Features 1[:] c:J IlB030/Z8DC3D I Z8530/Z85C3D I Serial Com. Controller full-duplex channels Enhanced OMA support 10x19 status FIFO 14-bit byte counter NRZJNRZlJFM en cit I 1 DwfMfu DMA BIU ~ I-- WOT 510 ~ CTC - - -- CTC -6VO zoo CPU SCC12 (85C3012) Z180 85230 16550 ESCC MIMIC (2CH) 5180 lB5230/Z8D23D Z85233* Z16C35 Z84C15 Z8D181 Z8D182 Enhanced Serial Com. Controller Integraled Serial Com. Controller Intelligent Peripheral Controller Smart Access Controller CMOS: 10, 16 MHz 2.5, 4.0 Mbls Full dual-channet SCC plus 4 OMA controllers and abus interface unit NMOS: 4, 6, SMHZ CMOS: 10, 16 CMOS: S,10 20 MHz 16 MHz 2.5,4.0,5.0 Mbls 2,2.5,4 Mbis I Two independent I'IU sec Full dual-channel SCC plus deeper FIFOs: 4 bytes on Tx Sbyteson Ax OPll counter per channel Software compatible InSCC "One channel of Z85230 Package 4O-pin DIP 44-pin CEROIP 44-pin PlCC 4O-pin DIP !6Il-PinPlGG 44-pin PlCC "44-pin OFP (85233) ApplicaHon General-Purpose datacom. General-Purpose datacom. High performance SCC software High performance datacom. SGC upgrades G ~" ~ TSA " OMA I OMA Z16C3D Z16C33 Zilog Intelligent Peripheral UnivelSal Serial Controller Mono-channel UnivelSal Serial Controller CMOS 6,10,16 MHz 10,12.5 CMOS 16,20 MHz CMOS: 20 MHz CPU Bus 10 Mbls 20Mbls CMOS: 10 MHz CPU Bus 10 Mbls ZSo- CPU, SIO, CTC Complete Zl80w WOT,CGC plusSCCI2 The Z80 Family in one device 16 va lines Power-on Reset Emulation Mode' Two chip selecls 32-bitCRC WSG EVmode' 3 and 5 Volt Version Complete Static version of Zl80 plus ESCC (2 channels of 85230) 16550 MIMIC 24 Parallel va Emulation Mode' Two dual-channel 32-byte receive & transmit FIFOs 16-bit bus 8.M': lS.2 Mbls 2 BRGs per channel Flexible 8/16-bR bus interface Single-channel (half of USCj plus (half DfUSC) Time Slot plus two OMA Assigner functions controllers forlSON Array chained and linked-list modes with ring buffer support erc !lOQ-pin QFP 10Q-pin VOFP Intelligent peripheral controllers Modems !l00-Pin OFP Intelligent peripheral controllers PrintelS, Faxes, Modems, Tenninals !l00-Pin OFP 1OO-pin VOFP I 68-pin PlCC General-Purpose Embedded Control Modem, Fax, Data CommunicaHons I 68-pln PlCC General-Purpose high;md datacom. Ethemet HOlC X.25 Frame Relay General-Purpose higlHnd datacom. Ethemet HOlC X.25 Frame Relay I Z16C32 I Integrated UnivelSal Serial Controller I CMOS:20 MHz CPU Bus 16Mbls 20 Mbls l68-pin PlCC General-Purpose high;md datacom. Ethernet HOlC X25 Frame Relay I AppleTalk" ARegistered Trademark of Apple Computer, Inc en m Block Diagram I a4C01" CPU OSC PWRDOWN eTC SIO -Pia CTC CGC SID WDT ~I zao CPU ~ SID I 2DMA 401/0 WDT OOC CTC WDT zao CPU eTC Z80CPU Z80 CPU I Z84011/C11 2 UART 2C/T 16-BIT Z80 CPU osc II 4DMA Z8OIZ-BUS UART INTERFACE 85230116550 ESCC MIMIC (2 CH) CISer MMU 3C/T OSC CACHE WSG I Z80180/S180 \ Z80280 \ Z80181 MMU Z180 Part # Z84C50 Z84C90 Z84013/C13 Description 180/84C01 with 2KSRAM KillerI/O (3 180 peripherals) Intelligent Peripheral Intelligent Peripheral Controller Contmller Parallel I/O Controller High-performance lao- CPU with peripherals l'B-bit l~ code compatible CPU with peripherals ISmart Access Controller Speed MHz 10 8,10,12.5 6,10 6,10 6,8,10,16",20" "18S180 only \10,12 \10,12.5 Features 180· CPU SID, PIO, CTC plus 81/0 lines lao- CPU, SID, CTC l~ CPU, SID, CTC WDT, CGC, WSG, WDT, CGC Power-On Reset The zao Family in 2chip selects one device EVmode' POYoer-On Reset Two chip selects 32-hit CRC WSG EVmcde' 180· CPU, CTC, Enhanced lao CPU MMU 1 Mbyte 2DMAs 2 UARTs with BRGs C/Seriall/O Port Oscillator 18S1S0 includes; Pwr dwn, Prgmble EMI, divide-by-one clock option 2 Kbytes SRAM WSG Oscillator Pin compatible with ZS4COO DIP & PLCC EV mode' "84COI is avai lable as a separate part Z84015/C15 6,10,16 WDT 40 I/O lines bit programmable Power-On Reset EVmode' Application 14o-Pin DIP 44-pin PLCC 44-pin aFP I Embedded Controllers S4-pin PLCC IGeneral-purpose peripheral that can be used with ISO and other CPU's S4-pin PLCC 10o-pin OFP 100-pin VaFP l00-pin OFP 64-pin DIP 68-pin PLCC SO-pin aFP Intelligent datacom controllers Intellioent peripheral coni rollers Modems Intelligent parallelI/O controllers Industrial display terminals Embedded Control I 68-pin PLCC Embedded Control Terminals Printers l' S180 \ Z80182 \16,20 Complete 1180 16-bit code compatible ISO- CPU plus SCC/2 Three stage pipeline CTC MMU 16 Mbyte 161/0 lines CACHE 256 byte Emulation Mode' Inst. & Data Peripherals 4 DMAs, UART. 3 lB-bit CIT, WSG ISOtz-BUS· interface I Package 241/0 CTC OO-pin OFP Intelligent peripheral controllers Printers Faxes Modem~, Term'inals 1 Complete Static Version of Zlao~ plus ESCC (2 channels of 185230) 18550 MIMIC 24 Parallel 110 Emulation Modes' l' OO-pin aFP 1~O-pin VaFP I General-Purpose Embedded Control Modem, Fax, Data Communications Allows use of existing development systems I Z85C80 Z8036 Z8536 Z32HOO Z5380 Z53C80 Description Counter!fimer & parallel I/O Unit (CIO) Hyperstone Enhanced Fast Instruction Set Computer (EFISC) Embedded (RISC) Processor Small Computer System Intertace (SCSI) Serial Communication Controller and Small Computer System Intertace Processl Speed NMOS 4,6 MHz CMOS 25 MHz CMOS Z5380: 1.5 MB/s Z53CBO: 3.0 MB/s CMOS SCC -10,16 MHz SCSI - 3.0 MB/s Features Three 16-bit Counter/Timers, Three I/O ports with bit catching, paitem matching interrupts and handshake I/O 32-bitMPU 4 Gbytes address space 19 global and 64 local registers of 32 bits each 128 bytes instruction cache 1.211 CMOS 42 mm'die ANSI X3.131-1986 Direct SCSI bus intertace On-board 4B mA drivers Normal or Block mode DMA transfers Bus intertace, target and initiator Full dual-channel SCC plus SCSI sharing databus and read/Wrile functions 4D-pin PDIP 44-pin PLCC 144-pin PGA 132-pin QFP Z5380: General-Purpose Counter!fimers and VO system designs Embedded high-pertormance industrial controller Workstations Bus host adapters, formatters, host pOiis l Package I Application I 4D-pin DIP 44-pin PLCC Z53C80: 48-pin DIP 44-pin PLCC I 68-pin PLCC I AppleTalke networking SCSI disk drives 2Software and hardware compatible With discrete devices U> ..:... IS9320 16.. 811 Mixed Signal Processor 10932116.. 811 Mixed ~ Signal Processor . . II!' Support Product Information iii Superintegration™ Products Guide Literature Guide and Third Party Support ZUog Sales Offices Representatives & Distributors II LITERATURE GUIDE Z8®/SUPER8™ MICROCONTROLLER FAMILY Databooks Part No ZS Microcontrollers Databook (Includes the following documents) DC-S275-o4 ZB CMOS Mlcrocontrol/ers Z86COO/C10/C20 MCU OTP Product Specification Z86C06 Z8 CCpN Preliminary Product Specification Z86C08 8-Bit MCU Product Specification Z86E08 Z8 OTP MCU Product Specification Z86C09/19 Z8 CCP Product Specification Z86E19 Z8 OTP MCU Advance Information Specification Z86C11 Z8 MCU Product Specification Z86C12 Z8 ICE Product Specification Z86C21 Z8 MCU Product Specification Z86E21/Z86E22 OTP Product Specification Z86C30 Z8 CCP Product Specification Z86E30 Z8 OTP CCP Product Specification Z86C40 Z8 CCP Product Specification Z86E40 Z8 OTP CCP Product Specification Z86C27/9l Z8 DTCN Product Specification Z86127 Low-Cost Digital Television Controller Adv. Info. Spec. Z86C50 Z8 CCP ICE Advance Information Specification Z86C61 Z8 MCU Advance Information Specification Z86C62 Z8 MCU Advance Information Specification Z86C89/C90 CMOS Z8 CCP Product Specification Z86C91 Z8 ROM less MCU Product Specification Z86C93 Z8 ROM less MCU Preliminary Product Specification Z86C94 Z8 ROM less MCU Product Specification Z86C96 Z8 ROM less MCU Advance Information Specification Z88COO CMOS Super8 MCU Advance Information Specification ZB NMOS Mlcrocontrol/ers Z8600 Z8 MCU Product Specification Z8601/03/11/13 Z8 MCU Product Specification Z8602 8-Bit Keyboard Controller Preliminary Product Spec. Z8604 8-Bit MCU Product Specification Z8612 Z8 ICE Product Specification Z8671 Z8 MCU With BASIC/Debug Interpreter Product Spec. Z8681/82 Z8 MCU ROM less Product Specification Z8691 Z8 MCU ROM less Product Specification Z8800/01/20/22 Super8 ROMless/ROM Product Specification Unit Cost 5.00 Peripheral Products Z86128 Closed-Captioned Controller Adv. Info. Specification Z765A Floppy Disk Controller Product Specification Z5380 SCSI Product Specification Z53CBO SCSI Advance Information Specification ZB Application Notes and Technical Articles Zilog Family On-Chip Oscillator Design Z86E21 Z8 Low Cost Thermal Printer Z8 Applications for I/O Port Expansions Z86C09/19 Low Cost Z8 MCU Emulator Z8602 Controls A101/102 PC/Keyboard The Z8 MCU Dual Analog Comparator The Z8 MCU In Telephone Answering Systems Z8 Subroutine Library AComparison of MCU Units Z86xx Interrupt Request Registers Z8 Family Framing AProgrammer's Guide to the Z8 MCU Memory Space and Register Organization SuperB Application Notes and Technical Articles Getting Started with the Zilog SuperB Polled Async Serial Operations with the Super8 Using the Super81nterrupt Driven Communications Using the SuperB Serial Port with DMA Generating Sine Waves with Super8 Generating DTMF Tones with SuperB ASimple Serial Parallel Converter Using the SuperB Additional Information Z8 Support Products Zilog Quality and Reliability Report Literature List Package Information Ordering Information L-1 LITERATURE GUIDE Z8®/SUPER8"" MICROCONTROLLER FAMILY (Continued) Databooks By Market Niche Part No Digital Signal Processor Databook (includes the following documents) Z86C95 Z8$ Digital Signal Processor Preliminary Product Specification Z89COO 16-8it Digital Signal Processor Preliminary Product Specification Z89COO DSP Application Note "Understanding Q15 Two's Complement Fractional Multiplication' Z89120, Z89920 (ROMless) 16-Bit Mixed Signal Processor Preliminary Product Specification Z89121, Z89921 (ROMless) 16-Bit Mixed Signal Processor Preliminary Product Specification Z89320 16-Bit Digital Signal Processor Preliminary Product Specification . Z8932116-Bit Digital Signal Processor Advance Information Specification DC-8299-02 3.00 Telephone Answering Device Databook (includes the following documents) DC-8300-02 Z89C65, Z89C66 (ROMless) Dual Processor TAM. Controller Preliminary Product Specification Z89C67, Z89C68/C69 (ROM less) Dual Processor Tapeless TAM. Controller Preliminary Product Specification Z89C65 Software Development Guide Z89C67/C69 Software Development Guide 3.00 Infrared Remote (IR) Control Databook (includes the following documents) Z86L06 Low Voltage CMOS Consumer Controller Processor Preliminary Product Specification Z86L29 6K Infrared (IR) Remote (ZIRCj Controller Advance Information Specification Z86L70/L71/L72, Z86E72 Zilog IR (ZIRCj CCpN Controller Family Preliminary Product Specification DC-8301-03 3.00 ZS Microcontrollers (includes the following documents) Z86C07 CMOS Z8 8-Bit Microcontroller Product Specification Z86C08 CMOS Z8 8-Bit Microcontroller Product Specification Z86E08 CMOS Z8 8-Bit OTP Microcontroller Product Specification Z86C11 CMOS Z8 Microcontroller Product Specification Z86C12 CMOS Z8ln-Circuit Microcontroller Emulator Product Specification Z86C21 8K ROM Z8 CMOS Microcontroller Product Specification Z85E2i CMOS ZS SK DTP Microconiroiier Produci Specificaiion Z86C61/62/96 CMOS Z8 Microcontroller Product Specification Z86C63/64 32K ROM Z8 CMOS Microcontroller Product Specification Z86C91 CMOS Z8 ROM less Microcontroller Product Specification Z86C93 CMOS Z8 Multiply/Divide Microcontroller Product Specification DC-8305-01 3.00 ZS Mlcrocontrollers (includes the following documents) Z86C04 CMOS Z8 8-Bit Low Cost 1KROM Microcontroller Product Specification Z86E04 CMOS Z8 OTP 8-Bit Low Cost Microcontroller Product Specification DC-6018-01 3.00 Mass Storage (includes the following documents) Z86C21 8K ROM Z8 CMOS Microcontroller Product Specification Z86E21 CMOS Z8 8K OTP Microcontroller Product Specification Z86C91 CMOS Z8 ROM less Microcontroller Product Specification Z86C93 CMOS Z8 Multiply/Divide Microcontroller Product Specification Z86C95 Z8 Digital Signal Processor Product Specification Z89COO 16-Bit Digital Signal Processor Product Specification Z89COO DSP Application Note - 'Understanding Q15 Two's Complement Fractional Multiplication" DC-8303-00 3.00 L-2 Unit Cost ~2iUD, LITERATURE GUIDE Z8@/SUPER8'" MICROCONTROLLER FAMILY (Continued) Databooks By Market Niche Part No Digital Television Controllers (includes the following documents) Z86C27/97 CMOS Z8~ Digital Signal Processor Product Specification Z86C61/62/96 CMOS Z8 Microcontroller Product Specification Z86C63/64 32K ROM CMOS 28 Microcontroller Product Specification Z86127 Low Cost Digital Television Controller Product Specification Z86128 Line 21 Closed-Caption Controller (L21Cj Digital Television Controller Product Specification Z86227 4D-Pio.1ow Cost (4LDTCj Digital Television Controller Product Specification DC-8308-00 3.00 Keyboard/Mouse/Polntlng Devices Databook (includes the following documents) Z8602 NMOS Z8~ 8-Bit Keyboard Controller Product Specification Z8614 NMOS Z8~ 8-Bit Keyboard Controller Product Specification Z8615 NMOS Z8~ 8-Btl Keyboard Controller Product Specification Z86E23 Z8~ 8-Bit Keyboard Controller with 8K OTP Product Specification Z86C04 CMOS Z8~ 8-Bit Microcontroller Product Specification Z86C08 CMOS Z8~ 8-Bit Microcontroller Product Specification Z88C17 CMOS Z8~ B-Bit Microcontroller Product Specification DC-8304-00 3.00 PC Audio Databook (includes the following documents) Z86321 Digital Audio Processor Preliminary Product Specification Z89320 16-Bit Digital Signal Processor Preliminary Product Specification Z89321/37116-Bit Digital Signal Processor Preliminary Product Specification Z8933116-Bit PC ISA Bus Interface Advance Information Specification Z89341/42/43 Wave Synthesis Chip Set Advance Information SpeCification Z5380 Small Computer System Interface Product Specification DC-8317-oo 3.00 PCMCIA/SCSllnterface Controllers (includes the following documents) Z5380 Small Computer System Interface Product Specification Z53C80 Small Computer System Interface Product Specification Z85C80 SCSCI'" Serial Communications and Small Computer Interface Product Specification Z86017 PCMCIA Interface Preliminary Product Specification Z86015 PCMCIA Interface with DMA Support Advance Product Specification Z86020 CardBuS/PCllnterface Advance Product Specification DC 8313-00 3.00 DC-8318-oo 3.00 Low End MCU Databook (includes the following documents) Z86C04 Z8~ Unit Cost L-3 ~2iUD, LITERATURE GUIDE Z8®/SUPER8'" MICROCONTROllER FAMilY (Continued) ZS Product Specifications, Technical Manuals and Users Guides Part No Z86E23 CMOS Z8 OTP Microcontroller Preliminary Product Specification Z8614 NMOS Z8 8-Bit MCU Keyboard Controller Preliminary Product Specification Z8 OTP CMOS One-Time-Programmable Microcontrollers Addendum Z8 Microcontrollers Technical Manual Z86018 Preliminary User's Manual Digital TV Controller User's Manual Z89COO 16-Bit Digital Signal Processor User's Manual/DSP Software Manual PLC Z89COO Cross Development Tools Brochure Z86C95 16-Bit Digital Signal Processor User Manual Z86017 PCMCIA Adaptor Chip User's Manual Z89C65/C67/C69 Software Manual DC-2598-00 DC-2576-00 DC-2614-M DC-8291-02 DC-8296-00 DC-8284-01 DC-8294-02 DC-5538-01 DC-8595-00 DC-8298-01 DC-831 0-00 ZS Application Notes Part No Z8602 Controls A101/102 PC/Keyboard The Z8 MCU Dual Analog Comparator Z8 Applications for I/O Port Expansions Z86E21 Z8 Low Cost Thermal Printer Zilog Family On-Chip Oscillator Design Using the Zilog Z86C06 SPI Bus Interfacing Leos to the Z8 X-10 Compatible Infrared (IR) Remote Control Z86C17 In-Mouse Applications Z86C40/E40 MCU Applications Evaluation Board Z86C08/C17 Controls AScrolling LED Message Display Z86C95 Hard Disk Controller Flash EPROM Interface Timekeeping with Z8; DTMF Tone Generation; Serial Communication Using the CCP Software UART DC-2601-01 DC-2516-01 DC-2539-01 DC-2541-01 DC-2496-01 DC-2584-01 DC-2592-01 DC-2591-01 DC-3001-01 DC-2604-01 DC-2605-01 DC-2639-01 DC-2645-01 L-4 Unit Cost N/C N/C N/C 5.00 N/C 3.00 3.00 N/C 3.00 3.00 3.00 Unit Cost N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C LITERATURE GUIDE Z80®1Z8000® CLASSIC FAMILY OF PRODUCTS Databooks By Market Niche Part No High-Speed Serial Communication Controllers Z16C30 CMOS Universal Serial Controller (USCj Preliminary Product Specification Z16C32 Integrated Universal Serial Controller (IUSCj Preliminary Product Specification Application Notes and Support Products Zilog's SuperintegrationNProducts Guide Literature Guide and Third Party Support DC-8314-00 3.00 Serial Communication Controllers Z8030/Z8530 Z-Busil> SCC Serial Communication Controller Product Specification Z80C30/Z85C30 CMOS Z-Busil> SCC Serial Communication Controller Product Specification Z80230 Z-Busil> ESCCNEnhanced Serial Communication Controller Preliminary Product Specification Z85230 ESCCTMEnhanced Serial Communication Controller Product Specification Z85233 EMSCCN Enhanced Mono Serial Communication Controller Product Specification Z85C80 SCSCIN Serial Communications and Small Computer Interface Product Specification Z16C35/Z85C35 CMOS ISCC Integrated Serial Communications Controller Product Specification Application Notes and Support Products Zilog's Superintegration Products Guide Literature Guide and Third Party Support DC-8316-00 3.00 Unit Cost N N Z801Z1801Z280 Product Specifications, Technical Manuals and Users Guides Part No Z80 Family Technical Manual Z80180 Z180 MPU Microprocessor Unit Technical Manual Z280 MPU Microprocessor Unit Technical Manual Z8018o/Z8S18o Z180 Microprocessor Product Specification Z80182 Zilog Intelligent Peripheral (ZIPj Z380 Preliminary Product Specification Z38o User's Manual Z80 Family Programmer's Reference Guide DC-8306-00 DC-8276-o4 DC-8224-o3 DC-2609-o3 DC-2616-o3 DC-6oo3-03 DC-8297-0o DC-0012-o4 Z801Z1801Z280 Application Notes Part No Z18o/SCCN Serial Communications Controller Interface at 10 MHz Z80 Using the 84C11/C13/C15 in place olthe 84011/013/015 AFast Z80 Embedded Controller DC-2521-o2 DC-2499-o2 DC-2578-o1 N N Unit Cost 3.00 3.00 3.00 N/C N/C N/C 3.00 N/C Unit Cost N/C N/C N/C L-5 LITERATURE GUIDE Z80@1Z8000@ CLASSIC FAMILY OF PRODUCTS (Continued) Z8000 Product Specifications, Technical Manuals and Users Guides Part No Z8000 CPU Central Processing Unit Technical Manual SCC Serial Communication Controller User's Manual Z8036 Z-CI0/Z8536 CIO Counter/Timer and ParaliellnpuVOutput Technical Manual Z8038 Z8000 HIO FIFO InpUVOutput Interface Technical Manual Z8000 CPU Central Processing Unit Programmer's Pocket Guide . Z85233 EMSCC Enhanced Mono Serial Communication Controller Preliminary Product Specification Z85C80 SCSCI'" Serial Communication and Small Computer Interface Preliminary Product Specification Z16C30 USC Universal Serial Controller Preliminary Technical Manual Z16C321USC Integrated Universal Serial Controller Technical Manual Z16C351SCC Integrated Serial Communication Controller Technical Manual Z16C35 ISCC Integrated Serial Communication Controller Addendum Z53C80 Small Computer System Interface (SCSI) Product Specification Z80230 Z-BUS~ ESCC Enhanced Serial Communication Controller Preliminary Product Specification DC-2010-06 DC-8293-02 DC-2091-02 DC-2051-01 DC-0122-03 DC-2590-00 DC-2534-02 DC-8280-02 DC-8292-03 DC-8286-01 DC-8286-01A DC-2575-01 DC-2603-D1 Z8000 Application Notes Part No Z16C30 Using the USC in Military Applications Datacom IUSC/MUSC Time Slot Assigner Datacom Evaluation Board Using The Zilog Family With The 80186 CPU Boost Your System Performance Using the Zilog ESCC Controller Z16C30 USC - Design aSerial Board for Multiple Protocols Using aSCSI Port for Generalized 1/0 DC-2536-01 DC-2497-02 DC-2560-03 DC-2555-02 DC-2554-01 DC-2608-01 L-6 Unit Cost 3.00 3.00 3.00 3.00 3.00 N/C N/C 3.00 3.00 3.00 N/C N/C N/C UnHCost N/C N/C N/C N/C N/C N/C ~2.iU:D, LITERATURE GUIDE MILITARY COMPONENTS FAMILY Military Specifications Part No Z8681 ROM less Microcomputer Military Product Specification Z8001/8002 Military Z8000 CPU Central Processing Unit Military Product Specification 28581 Military CGC Clock Generator and Controller Military Product Specification 28030 Military Z8000 Z-SCC Serial Communications Controller Military Product Specification 28530 Military SCC Serial Communications Controller Military Product Specification 28036 Military 28000 2-C10 CounterfTimer Controller and Parallel I/O Military Electrical Specification 28038/8538 Military FlO FIFO Input/Output Interface Unit Military Product Specification Z8536 Military CIO CounterfTimer Controller and Parallel I/O Military Electrical Specification Z8400 Military 280 CPU Central Processing Unit Military Electrical Specification Z8420 Military PIO Parallel Input/Output Controller Military Product Specification Z8430 Military CTC CounterfTimer Circuit Military Electrical Specification Z8440/1/2/4 Z80 SIO Serial Input/Output Controller Military Product Specification Z80C30/85C30 Military CMOS SCC Serial Communications Controller Military Product Specification Z84COO CMOS Z80 CPU Central Processing Unit Military Product Specification 284C20 CMOS 280 PIO Parallel Input/Output Military Product Specification Z84C30 CMOS Z80 CTC Counter/Timer Circuit Military Product Specification Z84C40/1/2/4 CMOS Z80 SIO Serial Input/Output Military Product Specification Z16C30 CMOS USC Universal Serial Controller Military Preliminary Product Specification Z80180 Z180 MPU Microprocessor Unit Military Product Specification Z84C90 CMOS KIO Serial/Parallel/Counter Timer Preliminary Military Product Specification Z85230 ESCC Enhanced Serial Communication Controller Military Product Specification DC-2392-02 DC-2342-03 DC-2346-01 DC-2388-02 DC-2397-02 DC-2389-01 DC-2463-02 DC-2396-01 DC-2351-02 DC-2384-02 DC-2385-01 DC-2386-02 DC-2478-02 DC-2441-02 DC-2384-02 DC-2481-01 DC-2482-01 DC-2531-01 DC-2538-01 DC-2502-00 DC-2595-00 Unit Cost N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C L-7 LITERATURE GUIDE GENERAL LITERATURE Catalogs, Handbooks, Product Flyers and Users Guides Part No Superintegration Shortform Catalog 1994 Superintegration Products Guide ZIA™3.3-5.5V Matched Chip Set for AT Hard Disk Drives Datasheet ZIA ZIAOOZCD Disk Drive Development Kit Datasheet Zilog Hard Disk Controllers - Z86C93/C95 Datasheet Zilog Infrared (IR) Controllers - ZIRcm Datasheet Zilog Intelligent Peripheral Controller - ZIpTMZ80182 Datasheet Zilog Digital Signal Processing - Z89320 Datasheet Zilog Keyboard Controllers Datasheet Z380m - Next Generation Z8()$!Z180'" Datasheet Fault Tolerant Z8" Microcontroller Datasheet 32K ROM Z8" Microcontrollers Datasheet Zilog Datacommunications Brochure Zilog Digital Signal Processing Brochure Zilog PCMCIA Adaptor Chip Z86017 Datasheet Zilog TelevisionNideo Controllers Datasheet Zilog TAD Controllers - Z89C65/C67/C69 Datasheet Zilog ASSPs - Partnering With You Product Flyer Quality and Reliability Report The Handling and Storage of Surface Mount Devices User's Guide Universal Object File Utilities User's Guide Zilog 1991 Annual Report Zilog 1992 Annual Report Zilog 1993 First Quarter Financial Report Zilog 1993 Second Quarter Financial Report Microcontro!!er Quick Reference Folder DC-5472-12 DC-5499-07 DC-5556-01 DC-5593-01 DC-5560-01 DC-5558-01 DC-5525-01 DC-5547-01 DC-5600-01 DC-5580-02 DC-5603-01 DC-5601-01 DC-5519-00 DC-5536-02 DC-5585-01 DC-5567-01 DC-5561-01 DC-5553-01 DC-2475-11 DC-5500-02 DC-8236-04 DC-1991-AR DC-1992-AR DC-1993-Q1 DC-1993-Q2 DC-5508-01 L-8 Unit Cost N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 3.00 N/C N/C N/C N/C N/C ZlLOG PRODUCTS THIRD PARTY SUPPORT Z8® HARDWARE AND SOFTWARE SUPPORT ZS Support Company Allen Ashley Avocet Systems Assembler X X Operating System Phone Number DOS, CP/M (818) 793-5748 DOS (800) 448-8500 DOS (519) 888-6911 DOS (415) 726-3000 DOS (213) 306-7412 DOS (609) 466-1751 Macintosh (513) 271-9100 DOS (716) 461-9187 X DOS (386+) (817) 599-8363 X DOS (804) 873-1947 DOS UNIX (800) 448-7733 DOS CP/M-80 ISIS-II (303) 327-4888 DOS UNIX CP/M VAX VMS (719) 345-8683 Simulator X X X Laboratory Microsystems Micro Computer Control Micro Dialects X X X X X MPE Production Language Corp. X Pseudo Corp. X X Software Development Systems Forth X Byte Craft Cybernetic Micro C Compiler X Western Wares X 2500AD Software X X Assembler Compiler X SuperS® Support C Company Allen Ashley X 2500AD Software X X Micro Computer Control Pseudo Corp. Simulator X X X X Forth Operating System Phone Number Macintosh (818) 793-5748 DOS (609) 466-1751 DOS (804) 873-1947 DOS (719) 345-8683 L-9 ZI.OG PRoDuCTS THIRD PARTY SUPPORT Z8® HARDWARE AND SOFTWARE SUPPORT Emulators Development System Creative Technology iSystems JK Board V.3.B Microlime Orion Instruments Signum Systems Wytec = A-/1,y1,~'7 W 1,7 1,71,7 1,7 C 0 0 0 0 0 E E • • • • • • • •• •• •• •• •• • • • • • • •• • •• •• •• •• •• • • • • • • • • • • • • • •• • •• •• • •• •• •• • • • • • •• • • • • A A B B B A A Emulate with Z86COBOOZDP Adaptor B = Emulate with ZB612 Board C = Emulate with Z86COBOOZDP and ZB612 Board or ZB6COBOOZEM o = Emulate with Z8612 Board E = Emulate with ZB6C90 Board Development System / ' Data 110, Inc. Logical Devices, Inc.' Needham, Inc. Smart Access, Inc. • •• •• • •• • •• • Single and Gang Programming Available L-10 ""71,71,)'1,71,7 W ZlLOG PRoDUCTS THIRD PARTY SUPPORT Z8® HARDWARE AND SOFTWARE SUPPORT Company Allen Ashley 395 Sierra Madre Villa Pasadena, CA 91107-2902 (818) 793-5748 Product Assembler Disassembler Simulator Company Logical Devices, Inc. 1201 NW 65th Place Fort Lauderdale, FL 33309 (800) 331-7766 Product OTP Programmer (Z86E21, Z86E22) Avocet Systems 120 Union Street Rockport, ME 04856 (800) 448-8500 Assembler. Micro Computer Control P.O. Box 275/17 Model Ave. Hopewell, NJ 08525 (609) 466-1751 Assembler C Compiler Simulator Byte Craft Limited 421 King Street North Waterloo, Ontario Canada N2J4E4 (519) 888-6911 C Compiler Micro Dialects P.O. Box 30014 Cincinnati, OH 45230 (513) 271-9100 Assembler Creative Technology 5144 Peachtree Road Suite 301 Atlanta, GA 30341 (404) 455-8255 Emulator CybernetiC Micro Systems P.O. Box3000 San Gregorio, CA 94074 (415) 726-3000 Dantrol 1910 Rena Ln. Dalton, GA 30720 (404) 226-3714 Data I/O, Inc. 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (206) 867-6829 Assembler Emulator OTP Programmer (Z86E21) MPE 2604 Elmwood Ave. Rochester, NY 14618 (716) 461-9187 Needham Electronics 4539 Orange Grove Ave. Sacramento, CA 95841 (916) 924-8037 Forth Complier OTP Programming Orion Instruments 180 Independence Dr. Menlo Park, CA 94025 (415) 327-8800 iSystems GmbH Einsteinstr. 5 W8050 Dachau, Germany (49) 8131-25085 Emulator Production Languages Corp. P.O. Box 109 Weatherford, TX 76086-0109 (817) 599-8363 J K Engineering 37 Kallang Pudding Rd. Blk. B Tong Lee Bldg. #08-03 Singapore 1334 011-65-7448418 Emulator Pseudo Corp. 716 Thimble Shoals Blvd. Ste. E Newport News, VA 23606 (804) 873-1947 Laboratory Microsystems 12555 West Jefferson Blvd. Los Angeles, CA 90060· (213) 306-7412 Emulator MicroTime 10F No. 1180 Chen-De Rd. 11148 Taipei, Taiwan, R O.C. 11-886-2-881-1791 Signum Systems 171 E. Thousand Oaks Blvd. Thousand Oaks, CA 91360 (805) 371-4608 Emulator Assembler Simulator C Compiler Assembler Disassembler Simulator Emulator Forth Compiler L-11 --~~--~---------------------------------- ZlLOG PRoouCTS THIRD PARTY SUPPORT Z8® HARDWARE AND SOFTWARE SUPPORT Company Product Smart Access, Inc. 124 Robin Road Altamonte Springs, FL 32701 (407) 331-4724 OTP Programmer (Z86E21, Z86E22) Software Development Systems 4248 Belle Aire Lane Downers Grove, IL 60515 (800) 448-7733 Software Science 3750 Round Bottom Road Cincinnati, OH 45244 (513) 561-2060 L-12 Assembler Z8~ Prototyping System Company Western Wares P.O. BoxC Norwood, CO 81423 (303) 327-4898 Wytec 185C East Lake Street Ste. 140 Bloomingdale, IL 60108 (708) 894-1440 2500AD Software, Inc. 109 Brookdale Ave. P.O. Box 480 Buena Vista, CO 81211 (719) 345-8683 Product Assembler Emulator Assembler CCompiler Simulator LITERATURE GUIDE ORDERING INFORMATION MINIMUM ORDER REQUIREMENTS Complete the attached literature order form. Be sure to enclose the proper payment or supply a purchase order. Please reference specific order requirements. Orders under$300.00 must be prepaid by check, money order or credit card. Canadian and foreign orders must be accompanied by acashier's check in U.S. dollars, drawn on acorrespondent U.S. bank only. Orders over $300.00 may be submitted with a Purchase Order. SHIPMENT Orders will be shipped after your check is cashed or credit is checked via the most economical method. Please allow four weeks for delivery. RETURNS ARE NOT ACCEPTED. PLEASE PRINT OR TYPE NAME PHONE ( COMPANY o Check ADDRESS STATE PART NUMBER lZIP DOCUMENT TITLE MaUTo: Credij Card or Purchase Order II ~2iUJ[; Expiration Date 210 E. HACIENDA AVE. MIS Cl·0 CAMPBELL, CA 95008·6600 Signature Phone: (408)370·8016 Fax: (408)37()'8056 o Money Order Credit Card 0 VISA 0 MlC 0 P.O. (over $300.00) I CITY ) Method of Payment (Check One) COUNTRY UNIT COST QTY. TOTAL $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ SUBTOTAL ADD APPLICABLE SALES TAX (CA ONLY) ADD 10% SHIPPING AND HANDLING TOTAL .2;1« 0, 16..Bit Processor Zilog Sales Offices Representatives & Distributors lilt IIiI ZILOG DOMESTIC SALES OFFICES AND TECHNICAL CENTERS INTERNATIONAL SALES OFFICES CALIFORNIA Agoura ........................................................... 818-707-2160 Campbell ........................................................ 408-370-8120 Irvine ............................................................... 714-453-9701 San Diego ....................................................... 619-658-0391 CANADA Toronto ........................................................... 905-673-0634 COLORADO Boulder ........................................................... 303-494-2905 GERMANY Munich ............................................................ 49-8967-2045 S6mmerda .................................................... 49-3634-23906 FLORIDA Clearwater ...................................................... 813-725-8400 GEORGIA Duluth ............................................................ .404-931-4022 ILLINOIS Schaumburg ................................................... 708-517-8080 MINNESOTA Minneapolis .................................................... 612-944-0737 NEW HAMPSHIRE Nashua ........................................................... 603-888-8590 OHIO Independence ................................................ 216-447-1480 CHINA Shenzhen .................................................... 86-755-2236089 JAPAN Tokyo ........................................................... 81-3-3587-0528 HONG KONG Kowloon ........................................................... 852-7238979 KOREA Seoul ............................................................. 82-2-577-3272 SINGAPORE Singapore .......................................................... 65-2357155 TAIWAN Taipei ........................................................... 886-2-741-3125 UNITED KINGDOM Maidenhead .................................................. 44-628-392-00 OREGON Portland .......................................................... 503-274-6250 PENNSYLVANIA Horsham ......................................................... 215-784-0805 TEXAS Austin .............................................................. 512-343-8976 Dallas .............................................................. 214-987-9987 © 1993 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subjectto change without notice. DevicessoldbyZilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. DC 8299-03 Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Z-1 SALES REPRESENTATIVES AND DISTRIBUTORS u.s., CANADIAN & PUERTO RICAN REPRESENTATIVES ALABAMA MASSACHUSETTS Huntsville North Reading Electronic Sales, Inc ................................ (205) 533-1735 Advanced Technical Sales ...................... (508) 664-0888 ARIZONA MICHIGAN Scottsdale Farmington Hills Thom Luke Sales, Inc .............................. (602) 451-5400 Rathsburg Associates, Inc ...................... (313) 489-1500 COLORADO Englewood Thorson Rocky Mountain ......................... (303) 773-6300 CONNECTICUT Wallingford Advanced Technical Sales ...................... (508) 664-0888 FLORIDA Altamonte Springs Semtronic Associates, Inc ....................... (407) 831-8233 Clearwater Semtronic Associates, Inc ....................... (813) 461-4675 Fort Lauderdale Semtronic Associates, Inc ....................... (305) 731-2484 MINNESOTA Minneapolis Professional Sales for Industry ................ (612) 944-8545 MISSOURI Bridgeton Advanced Technical Sales ...................... (314) 291-5003 NEW JERSEY Cherry Hill Tritek ........................................................ (609) 667-0200 NEW MEXICO Albuquerque Quatra & Associates ................................ (505) 296-6781 NEW YORK GEORGIA fJorcross Electronic Sales, Inc ................................ (404) 448-6554 Fairport L-Mar Associates, inc .............................. (7i6j 425-9iOO NORTH CAROLINA ILLINOIS Hoffman Estates Cary Electronic Sales, Inc ................................ (919) 467-8486 Victory Sales, Inc ..................................... (708) 490-0300 OHIO IOWA Cedar Rapids Advanced Technical Sales ...................... (319) 393-8280 Centerville Q-Mark, Inc .............................................. (513) 438-1129 Independence Rathburg Associates, Inc ........................ (216) 447-8825 KANSAS Olathe Advanced Technical Sales ...................... (913) 782-8702 OKLAHOMA Tulsa Nova Marketing, Inc ................................. (918) 660-5105 MARYLAND Pasadena Electronic Engineering & Sales ............... (410) 255-9686 Z-2 SALES REPRESENTATIVES AND DISTRIBUTORS u.s., CANADIAN & PUERTO RICAN REPRESENTATIVES TEXAS Austin Nova Marketing, Inc ................................. (512) 343-2321 Dallas Nova Marketing, Inc ................................. (214) 265-4630 Houston Nova Marketing, Inc ................................. (713) 988-6082 UTAH Salt Lake City Thorson Rocky Mountain ......................... (801) 942-1683 WISCONSIN Brookfield Victory Sales, Inc ..................................... (414) 789-5770 CANADA British Columbia BBD Electronics, Inc ................................ (604) Ontario BBD Electronics, Inc ................................ (905) Ottawa BBD Electronics, Inc ................................ (613) Quebec BBD Electronics, Inc ................................ (514) 465-4907 821-7800 764-1752 697-0801 PUERTO RICO SanJuan Semtronic Associates, Inc ....................... (809) 766-0700 Z-3 SALES REPRESENTATIVES AND DISTRIBUTORS u.s. AND CANADIAN DISTRIBUTORS NATIONWIDE Newark Electronics ................................. 1-800-367-3573 ALABAMA Inside Alabama .......................................... 800-572-7236 Outside Alabama ....................................... 800-633-2918 Huntsville Arro",! Electronics ............... : ..................... (205l837-6955 Hamilton Hallmark Electronics ................. (205 837-8700 ARIZONA Inside Arizona ............................................ 800-352-8489 Outside Arizona ......................................... 800-528-8471 Phoenix Hamilton Hallmark Electronics ................. (602) 437-1200 Tempe Anthem Electronics .................................. (602) 966-6600 Arrow Electron ics ..................................... (602) 431-0030 CALIFORNIA Calabasas Arrow Electronics ..................................... (818) 880-9686 Chatsworth Anthem Electronics .................................. (818) 700-1000 Costa Mesa Hamilton Hallmark Electronics ................. (714) 641-4100 Hayward Arrow Electronics ..................................... (510) 487-8416 Irvine Anthem Electronics .................................. (714l768-4444 Arrow Electronics ..................................... (714 587-0404 Rocklin Anth~m Electronics ............ : ..................... (916l624-9744 Hamilton Hallmark Electronics ................. (916 961-0922 San Diego Anthem Electronics .................................. ~619l453-9005 Arro",! Electronics ............... : ..................... 619 565-4800 Hamilton Hallmark Electronics ................. 619 277-6136 San Jose Anthem Electronics .................................. (408l453-1200 Arrow Electronics ..................................... (408 441-9700 Sunnyvale Hamilton Hallmark Electronics ................. (408) 743-3300 Woodland Hills Hamilton Hallmark Electronics ................. (818) 594-0404 COLORADO Colorado Springs Hamilton Hallmark Electronics ................. (719) 637-0055 Englewood Anthem Electronics .................................. ~303l790-4500 Arrow Electronics ............... : ..................... 303 799-0258 Hamilton Hallmark Electronics ................. 303 790-1662 Z-4 CONNECTICUT Cheshire Hamilton Hallmark Electronics ................. (203) 271-2844 Wallingford Arrow Electronics ..................................... (203) 265-7741 Waterbury Anthem Electronics .................................. (203) 596-3200 FLORIDA Deerfield Beach Arrow Electronics ..................................... (305) 429-8200 Lake Mary Arrow Electronics ..................................... (407) 333-9300 Largo Hamilton Hallmark Electronics ................. (813) 541-7440 (800) 282-9350 Fort Lauderdale Hamilton Hallmark Electronics ................. (305) 484-5482 Winter Park Hamilton Hallmark Electronics ................. (407) 657-3300 GEORGIA Duluth Arro",! Electron ics ............... : ..................... ~404l497 -1300 Hamilton Hallmark Electronics ................. 404 623-5475 404 623-4400 iLliNOiS Bensonville Hamilton Hallmark Electronics ................. (708) 860-7780 Itasca Arrow Electronics ..................................... (708) 250-0500 Schaumburg Anthem Electronics .................................. (708) 884-0200 INDIANA Indianapolis Arrow Electronics ............... : ..................... (317~ 299-2071 Hamilton Hallmark Electronics ................. (317 872-8875 (800 829-0146 IOWA Cedar Rapids Arrow Electronics ..................................... (319) 395-7230 KANSAS Lenexa Arro",! Electronics ............... : ..................... ~913l541-9542 Hamilton Hallmark Electronics ................. 913 888-4747 800 332-4375 SALES REPRESENTATIVES AND DISTRIBUTORS U.S. AND CANADIAN DISTRIBUTORS KENTUCKY Lexington Hamilton Hallmark Electronics ................. (800) 235-6039 (800) 525-0069 MARYLAND Columbia Anthem Electronics .................................. ~3011995-6640 Arro,,! Electronics ...............; ..................... 301 596-7800 Hamilton Hallmark Electronics ................. 410 988-9800 MASSACHUSETTS Peabody Hamilton Hallmark Electronics ................. (508) 532-9808 Wilmington Anthem Electronics .................................. (508) 657-5170 Arrow Electronics ..................................... (508) 658-0900 MICHIGAN Livonia Arrow Electronics ..................................... (313) 462-2290 Nori Hamilton Hallmark Electronics ................. (313) 347-4271 Plymouth Hamilton Hallmark Electronics ................. (313) 416-5800 (800) 767-9654 MINNESOTA Bloomington Hamilton Hallmark Electronics ................. (612) 881-2600 Eden Prairie Anthem Electronics .................................. (612) 944-5454 Arrow Electronics ..................................... (612) 941-5280 MISSOURI Earth City Hamilton Hallmark Electronics ................. (314) 291-5350 St Louis Arrow Electronics ..................................... (314) 567-6888 NEVADA Sparks Arrow Electronics ..................................... (702) 331-5000 NEW JERSEY Cherry Hili Hamilton Hallmark Electronics ................. (609) 424-0110 Marlton Arrow Electronics ..................................... (609) 596-8000 Plnebrook Anthem Electronics .................................. (201) 227-7960 Arrow Electronics ..................................... (201) 227-7880 Parsippany Hamilton Hallmark Electronics ................. (201) 515-1601 NEW YORK Commack Anthem Electronics .................................. (516) 864-6600 Hauppauge Arro,,! Electronics ...............; ..................... (516) 231-1000 Hamilton Hallmark Electromcs ................. (516) 434-7470 Melville Arrow Electronics ..................................... (516) 391-1300 Rochester Arro,,! Electronics ...............; ..................... (716) 427-0300 Hamilton Hallmark Electromcs ................. (716) 475-9130 Ronkonkoma Hamilton Hallmark Electronics ................. (516) 737-0600 NORTH CAROLINA Raleigh Arrow Electronics ..................................... (919) 876-3132 Hamilton Hallmark Electronics ................. (919) 872-0712 OHIO Centerville Arrow Electronics ..................................... (513) 435-5563 Dayton Hamilton Hallmark Electronics ................. (513) 439-6735 (800) 423-4688 Solon , Arro,,! Electronics ............... ;..................... (216) 248-3990 Hamilton Hallmark Electronics ................. (216) 498-1100 Worthington Hamilton Hallmark Electronics ................. (614) 888-3313 ZoS SALES REPRESENTATIVES AND DISTRIBUTORS U.S. AND CANADIAN DISTRIBUTORS OKLAHOMA WISCONSIN Tulsa Brookfield Arrow Electronics ..................................... (918) 252-7537 Hamilton Hallmark Electronics ................. (918) 254-6110 Arrow Electronics ..................................... (414) 792-0150 New Berlin Hamilton Hallmark Electronics ................. (414) 797-7844 OREGON Beaverton ALMAC/Arrow Electronics .: ..................... (503) 629-8090 Hamilton Hallmark Electronics ................. (503) 526-6200 CANADA Alberta Future Electron!cs .................................... (403) 250-5550 Future Electronics .................................... (403) 438-2858 PENNSYLVANIA Horsham British Columbia Anthem Electronics .................................. (215) 443-5150 Arrow Electroni~s ..................................... (604) 421-2333 Future Electronics .................................... (604) 294-1166 Pittsburgh Arrow Electron ics ..................................... (412) 963-6807 Manitoba TEXAS Future Electronics .................................... (204) 786-7711 Austin Arro",! Electronics ............... : ..................... (512) 835-4180 Hamilton Hallmark Electronics ................. (512) 258-8848 Carrollton Arrow Electronics ..................................... (214) 380-6464 Dallas Hamilton Hallmark Electronics ................. (214) 553-4300 Houston Arro",! Electronics ............... : ..................... (713) 530-4700 Hamilton Hallmark Electronics ................. (713) 781-6100 Richardson Anthem Electronics .................................. (214) 238-7100 San Antonio Hamilton Hallmark Electronics ................. (21 0) 828-2246 UTAH Salt Lake City Anthem Electronics .................................. ~801 ~ 973-8555 Arro",! Electronics ............... : ..................... 801 973-6913 Hamilton Hallmark Electronics ................. 801 266-2022 WASHINGTON Bellevue ALMAC/Arrow Electronics ....................... (206) 643-9992 Bothell Anthem Electronics .................................. (206) 483-1700 Redmond Hamilton Hallmark Electronics ................. (206) 881-6697 Spokane ALMAC/Arrow Electronics ....................... (509) 924-9500 Z-6 Ontario Arrow Electron!cs ..................................... !6131226-6903 Arrow Electronics ..................................... 905 670-7769 Future Electronics .................................... 905 612-9200 Future Electronics .................................... 613 820-8313 Quebec Arrow Electronics ..................................... (514) 421-7411 Future Electronics .................................... (514) 694-7710 Burnaby Hamilton Hallmark Electronics ....... ;......... (604) 420-4101 Mississauga Hamilton Hallmark Electronics ................. (416) 564-6060 Nepean Hamilton Hallmark Electronics ................. (613) 226-1700 Ville St. Laurent Hamilton Hallmark Electronics ................. (514) 335-1000 SALES REPRESENTATIVES AND DISTRIBUTORS CENTRAL AND SOUTH AMERICA ASIA-PACIFIC MEXICO Semiconductores Profesionales ............................................. 525-524-6123 Proyeccion Electronica .............................. 525-264-7482 AUSTRALIA R&D Electronics ........................................ 61-3-558-0444 GEC Electronics Division ......................... 61-2-638-1888 ARGENTINA Buenos Aires YEL SRL .............................................. 011-541-440-1532 CHINA Lestina International Ltd ........................... 86-1-849-8888 Rm.20469 China Electronics Appliance Corp ....... 86-755-335-4214 TLG Electronics, Ltd .................................. 852-388-7613 BRAZIL 5aoPau/o Digibyte ........................................... 011-55-11-581-4100 Nish icom .......................................... 011-55-11-535-1755 HONG KONG Lestina International Ltd ............................ 852-735-1736 Electrocon Products Ltd ............................ 852-481-6022 INDIA Banga/ore Zenith Technologies Pvt. Ltd ................... 91-812-586782 Bombay Zenith Technologies Pvt. Ltd ................... 91-22-4947457 JAPAN Teksel Co., Ltd ........................................ 81-44-812-7430 Internix Incorporated .............................. 81-3-3369-1101 Kanematsu Electronic Components Corp .................................. 81-3-3779-7811 KOREA ENC-Korea ................................................. 822-579-3330 MALAYSIA Eltee Electronics Ltd .................................. 60-3-7038498 NEW ZEALAND GEC Distributors Ltd .................................. 64-25-971057 PHILIPPINES Alexan Commercial ...................................... 63-2-402223 SINGAPORE Eltee Electronics Ltd ..................................... 65-2830888 TAIWAN (ROC) Acer Sertek, Inc ...................................... 886-2-501-0055 Orchard Electronics Co .......................... 886-2-504-7083 Weikeng Ind. Co. Ltd .............................. 886-2-659-0303 THAILAND Eltee Electronics Ltd ................................. 66-2-530-1739 Z-7 --'- - - -----~----"--- ---.------~'. - ------ ---~ - .,-----=---'.------._ ... SALES REPRESENTATIVES AND DISTRIBUTORS EUROPE AUSTRIA Vienna EBV Elektronik GMBH ............................ 43-222-8941774 BELGIUM Antwerp D & D Electronics PVBA .......................... 01 0-323-82779 Zaventem EBV Elektronik ...................................... 01 0-322-7209936 DENMARK Brondby Ditz Schweitzer AS ............................... 01 0-4542-453044 Lynge Delco A/S ............................................ 011-45-35-821200 ENGLAND Berkshire Future Electronics ....................................... 0753-687000 Gothic Crellon ............................................. 0734-787848 Macro Marketing ......................................... 0628-604383 Lanc:astershlre Complementary Technologies Ltd ........... 44-942-274731 FINLAND Espoo OY SW Instruments AB ...................... 011-358-0-522-122 FRANCE Cedex A2M .................................................... 010-331-46232425 Massy Reptronic SA ...................................... 010-331-60139300 Z-8 GERMANY Berlin EBV Elektronik GMBH ................................. 030-3421041 Electronic 2000 ........................................... 030-2110761 Burgwedel EBV Elektronik GMBH ................................. 051-3980870 Dortmund Future Electronics ....................................... 02305-42051 Duesseldorf Electronic 2000 ........................................... 021-1920030 Erfurt Thesys ......................................................... 036-1476000 Frankfurt EBV Elektronik GMBH ................................... 069-785037 Electronic 2000 ............................................. 069-973840 Future Electronics ......................................... 6126-54020 Hamburg Electronic 2000 ......................................... 040-64557021 Leonberg EBV Elektronik GMBH ................................. 071-5230090 Muenchen Electronic 2000 ............................................. 089-451101 EBV Elektronik GMBH ................................... 089-460960 Future Electronics ....................................... 089-9571950 Nuernberg Electronic 2000 ........................................... 911-9951610 , Neuss EBV Elektronik GMBH ............................... 021-31530072 Stuttgart Electronic 2000 ............................................. 071-563560 Future Electronics ......................................... 711-830830 SALES REPRESENTATIVES AND DISTRIBUTORS ISRAEL ROT .................................................... 010-972-35483737 ITALY Milano De Mica S.PA ......................................... 39-295-343600 NETHERLANDS Tekelec ................................................. 01 0-3179-310100 NORWAY Hefro .................................................... 010-47-22676800 PORTUGAL Ibertronics ................................................. 35-1-471-6587 SPAIN Madrid Unitronics SA ........................................... 34-1-5428493 SWEDEN NC Nordcomp Sweden AB .................. 010-46-87646710 SWITZERLAND Dletlkon EBV Elektronik GMBH ............................... .41-1-7401090 Regensdorf Moor elektronik AG .................................... 41-1-8433111 Lausanne EBV Elektronik GMBH ............................ ..41-21-3112804 Z-9 Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 408-370-8000 I I - I

Source Exif Data:
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:25 10:21:08-08:00
Modify Date                     : 2013:08:25 18:18:54-07:00
Metadata Date                   : 2013:08:25 18:18:54-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:d9bb5640-4320-f443-9a58-db9b7f6ee620
Instance ID                     : uuid:514f0177-e228-3f41-8fbf-68628e593fae
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 398
EXIF Metadata provided by EXIF.tools

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