1994_Crystal_Semiconductor_Audio_Databook 1994 Crystal Semiconductor Audio Databook
User Manual: 1994_Crystal_Semiconductor_Audio_Databook
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MODEL
INDEX
CS5349 .................... 3-101
CDB5349 ................. 3-122
CS5389 .................... 3-135
CS5390 .................... 3-155
CDB5389/90 ............ 3-173
CS5412 ...................... 9-13
CS5501/3 ................... 9-14
CS5504 ...................... 9-15
CS5505/6/7/8 ............. 9-16
CS5509 ...................... 9-17
CS5516/20 ................. 9-18
CS6152 ...................... 10-6
CS61535A .................. 10-7
CS61574A .................. 10-8
CS61600 .................... 10-9
CXT6176/8192 ......... 10-10
CS6400 ..................... 10-11
CS6401 .................... 10-12
CS6453 .................... 10-13
CS80600 .................. 10-14
CS83C92 ................. 10-15
CS8401A/2A ................ 6-3
CS8411/12 ................. 6-35
CS8425 ...................... 6-69
CS8870 .................... 10-16
CS8905 ...................... 5-45
CS9203 ...................... 5-61
CDBGMR4 ................. 5-86
CDBCAPTURE .......... 7-25
CWDRGNTT ............ 4-266
CWMNLG ................. 4-265
DIAGNOSTICS ........ 4-264
DRIVERS ................. 4-263
CS1232 ....... :................. 7-3
CS2180A/B ................. 10-5
CS3310 ... ;................... 7-11
CDB3310 .................... 7-24
CS4131 ........................ .4-5
CS4215 ...................... .4-29
CDB4215 .................... 4-67
CS4216 ...................... .4-77
CDB4216 ................. .4-115
CS4225 .....................4-135
CDB4225 ................. .4-163
CS4231 .................... .4-165
CDB4231 ................. .4-212
CS4248 .................... .4-225
CS4303 ......................... 2-3
CDB4303 ....................2-19
CS4328 .......................2-31
CDB4328 .................... 2-50
CS4330 .......................2-61
CS4920 ......................... 5-3
CDB4920 .................... 5-43
CS501214/6 ................... 9-5
CS5030/1 ...................... 9-6
C5101A/02A ................. 9-7
CS5126 ......................... 9-8
CS5317 ......................... 9-9
CS5321 ....................... 9-10
CS5322/23 .................. 9-11
CS5324 ....................... 9-12
CS5326/7/8/9 ................ 3-5
CDB5326/7/8/9 ...........3-24
CS5336/8/9 ................. 3-39
CDB5336/8/9 .............. 3-60
CS5345 ....................... 3-73
CDB5345 .................... 3-90
ADB7.0
---------------------Crystal Semiconductor Corporation
Digital Audio Products
Data Book
January 1994
This publication neither states nor implies any warranty of any kind, including, but not limited to, implied warrants of merchantability or
fitness for a particular application. Crystal assumes no responsibility for the use of any circuitry other than the circuitry in a Crystal product.
No circuit patent licenses are implied.
The information in this publication is believed tn be accurate in all respects at the time of publication but is subject to change without
notice. Crystal assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use
of information included herein. Additionally, Crystal assumes no responsibility for the functioning of undescribed features or parameters.
© Copyright 1994 Crystal Semiconductor COrporation
LIFE SUPPORT AND NUCLEAR POLICY
CRYSTAL SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITIEN CONSENT OF CRYSTAL
SEMICONDUCTOR.
Life Support Systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with
instructions provided can be reasonably expected to result in personal injury or death. Users contemplating applications of Crystal Semiconductor products in Life Support Systems are requested to contact Crystal Semiconductor factory headquarters to establish suitable terms and
conditions for these applications. Crystal Semiconductor's warranty is limited to replacement of defective components and does not cover
injury to persons or property or other consequential damages.
Examples of devices considered to be life support devices are neonatal oxygen analyzers, nerve stimulators (whether used for anesthesia,
pain relief, or other purposes), autotransfusion devices, blood pumps, defibrillators, arrhythmia detectors and alarms, pacemakers, hemodialysis systems, peritoneal dialysis systems, neonatal ventilator incubators, ventilators for both adults and infants, anesthesia ventilators, and
infusion pumps, as well as other devices designated as "critical" by the FDA. The above are examples only and are not intended to be
conclusive or exclusive of any other life support device.
Examples of nuclear facility applications are applications in (a) a nuclear reactor, or (b) any device designed or used in connection with the
handling, processing, packaging, preparation, utilization, fabricating, alloying, storing, or disposal of fissionable material or waste products
thereof.
----------------------
Products in this book may be covered by one or more of the following patents. Additional patents are
pending.
~
4,709,225;
5,055,846;
5,087,914;
5,187,390;
5,257,026.
4,849,662;
4,918,454;
5,061,925;
5,196,850;
4,804,863;
4,941,156;
5,111,451;
5,198,782;
4,748,418;
4,988,954;
5,117,200;
5,208,597;
4,746,899;
5,068,660;
5,121,080;
5,212,659;
4,805,198;
5,079,550;
5,140,279;
5,220,483;
4,851,841;
5,039,989;
5,150,386;
5,245,344;
4,943,807;
5,012,244;
5,157,395;
5,247,210;
Germany:
3,642,070; 3,736,735; 3,737,279; 3,733,682; 3,933,552; 4,002,871; 4,127,096; 4,202,180.
Great Britain:
2,184,621; 2,198,306; 2,198,305; 2,195,848; 2,223,879; 2,232,547.
France:
2,591,753; 2,604,839; 2,606,565.
Japan:
1,684,670; 1,736,807; 1,747,991.
2
4,939,516;
5,088,107;
5,172,115;
5,248,970;
-------"---------..,... ---
AUDIO DATA BOOK CONTENTS
-.'
..
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
•~
DIGITAL AUDIO INTERFACES
AES/EBU & SPDlF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
I
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
I
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & ,Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
-
I
~
3
----------- ----------l.
2.
3.
4.
4
CONTENTS
GENERAL INFORMATION
- Contents
- Company Information and Part Numbering Convention
- Quality and Reliability Information .
1-2
1-3
1-5
DIGIT AL-TO-ANALOG CONVERTERS
- Introduction, Contents and User's Guide
- CS4303 107 dB, D/A Converter for Digital Audio
- CDB4303 Evaluation Board for CS4303
- CS4328 18-Bit, Stereo D/A Converter for Digital Audio
- CDB4328 Evaluation Board for CS4328
- CS4330 8 Pin Stereo D/A Converter for Digital Audio
2-2
2-3
2-19
2-31
2-50
2-61
ANALOG-TO-DIGITAL CONVERTERS
- Introduction, Contents and User's Guide
- CS5326/7/8/9 16 & 18 Bit, Stereo AID Converters for Digital Audio
- CDB532617/8/9 Evaluation Board for CS532617/8/9
- CS5336/8/9 16 Bit, Stereo AID Converter for Digital Audio
- CDB5336/8/9 Evaluation Board for CS5336/8/9
- CS5345 Low Power, Stereo AID Converter for Digital Audio .
- CDB5345 Evaluation Board for CS5345
- CS5349 Single Supply, Stereo AID Converter for Digital Audio
- CDB5349 Evaluation Board for CS5349
- CS5389 18 Bit, Stereo AID Converter for Digital Audio
- CS5390 20 Bit, Stereo AID Converter for Digital Audio
- CDB5389/90 Evaluation Board for the CS5389/90
3-2
3-5
3-24
3-39
3-60
3-73
3-90
3-101
3-122
3-135
3-155
3-173
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CODEC
- Introduction, Contents and User's Guide
- CS4131 Multimedia Digital Audio Controller
- CS4215 16 Bit Multimedia Audio Codec
- CDB4215 Evaluation Board for CS4215
- CS4216 16 Bit Stereo Audio Codec
- CDB4216 Evaluation Board for CS4216
- CS4225 Digital Audio Conversion System
- CDB4225 Evaluation Board for CS4225
- CS4231 Parallel Interface, Multimedia Audio Codec
- CDB4231 Evaluation Board for CS4231 and CS4248
- CS4248 Parallel Interface, Multimedia Audio Codec
- CS4231 and CS4248 Device Drivers
- Multimedia Audio Codec Diagnostic Software .
- First Byte's Monologue for Windows
- Talk~To Voice Recognition from Dragon Systems
4-2
4-5
4-29
4-67
4-77
4-115
4-135
4-163
4-165
4-212
4-225
4-263
4-264
4-265
4-266
-____-_
.. .....
. ..,-._..
....
5.
6.
7.
8.
DIGITAL SIGNAL PROCESSORS
- Introduction, Contents and User's Guide
- CS4920 Broadcast Audio Decoder - DAC
- CDB4920 Evaluation Board for CS4920
- CS8905 Programmable Music Processor
- CS9203 Advanced Music Synthesizer .
- Wave Table MIDI Synthesizer Solutions
- CDBGMR4 Evaluation Board for CS8905 & CS9203
DIGITAL AUDIO INTERFACES
- Introduction, Contents and User's Guide
- CS8401A12A Digital Audio Interface Transmitter
- CS8411112 Digital Audio Interface Receiver
- CS8425 Audio Local Area Network Transceiver (A-LAN)
SUPPORT FUNCTION PRODUCTS
- Introduction, Contents and User's Guide
- CS1232 Micromonitor
- CS3310 Stereo Digital Volume Control
- CDB3310 Evaluation Board for the CS3310
- CDBCAPTURE Data Capture System for AID Converter Analysis
APPLICATION NOTES
- Contents .
- Printed Circuit Board Layout Guidelines
- AID Converter Input Protection Techniques
- Delta-Sigma AID Conversion Technique Overview
- CS5326 to DSP56000 Interface .
- CS5326 Low Frequency Operation .
- CS5328 ADC AES paper by C. Sanchez
- CS5326 ADC AES paper by D. WeIland et al
- Clock Jitter AES paper by S. Harris
- CS4328 DAC AES paper by N. Sooch et al
- AESIEBU Transmitters and Receivers AES paper by D. Knapp
- AESIEBU & SIPDIF Digital Audio Communication Standards Overview
- CS4303 DAC AES paper by S. Green et al
- Delta-Sigma AID & D/A Converters AES paper by S. Harris
- CS4225 AID & D/A AES paper by S. Harris et al .
- SCMS AES paper by C. Sanchez
- Single Chip Stereo Audio Codec AES paper by S. McDonald et al
- A Single Chip Stereo Volume Control AES paper by L. Harris et al
- A MIDI Tutorial .
- Design Techniques for CD-Quality Audio SVPC paper by Ron Knapp
CONTENTS
5-2
5-3
5-40
5-41
5-57
5-77
5-82
6-2
6-3
6-35
6-69
7-2
7-3
7-11
7-24
7-25
8-2
8-3
8-7
8-11
8-21
8-23
8-25
8-43
8-55
8-67
8-79
8-93
8-101
8-121
8-137
8-153
8-189
8-203
8-213
8-237
5
..-_-_
_-___
...... .. ...-..
."
9.
6
DATA ACQUISITION PRODUCTS
- Introduction, Contents and User's Guide
- CS5012N4/6 16, 14, & 12-Bit, Self-Calibrating AID Converters
- CS5030/l 12-Bit, 500 kHz, Sampling AID Converters
- CS5101N2A 16-Bit, 100 kHzI20 kHz AID Converters
- CS5126 16-Bit, Stereo AID Converter for Digital Audio
- CS5317 16-Bit, 20 kHz OversamplingAID Converter.
- CS5321 High Dynamic Range Delta-Sigma Modulator
- CS5322/3 24-Bit Variable Bandwidth AID Converter
- CS5324 120 dB, 500 Hz Oversampling AID Converter
- CS5412 12-Bit, 1MHz Self-Calibrating AID Converter
- CS550113 Low-Cost, 16 & 20-Bit Measurement AID Converter
- CS5504 Low Power, 20-Bit AID Converter
- CS5505/6/7/8 Very Low Power, 16-Bit lind 20-Bit AID Converters
- CS5509 Single Supply, 16-Bit AID Converter
- CS5516120 16-Bitl20-Bit Bridge Transucer AID Converters
CONTENTS
9-2
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
10. COMMUNICATIONS PRODUCTS
- Introduction, Contents and User's Guide
- CS2180AIB T1 FramerlTransceiver
- CS6152 Tl (1.544MHz) Analog Interface
- CS61535A T1 (1.544 MHz) & PCM-30 (2.048 MHz) Line Interface
- CS61574A T1 (1.544 MHz) & PCM-30 (2.048 MHz ) Line Interface
- CS61600 T1 (1.544 MHz) & PCM-30 (2.048 MHz) Jitter Attenuator
- CXT6176/8192 6.176 MHz and 8.192 MHz Crystals
- CS6400 Echo-Cancelling Codec
- CS6401 Programmable Echo Canceller.
- CS6453 Modem and Audio Analog Front End
- CS80600 4.5 MHz to 8.5 MHz Jitter Attenuator
- CS83C92 Coaxial Transceiver Interface
- CS8870 DTMF Receiver
10-2
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
11. APPENDICES
- Contents
- Definition of Product Category Levels
- Definition of Product Preview, Preliminary, and Final Data Sheets
- Radiation Performance
- Reliability Methods
- Package Outlines
11-2
11-3
11-4
11-4
11-5
11-12
12. SALES OFFICES
- Contents
- Sales Offices .
12-2
12-3
-_--_
___-_
. .. ...-..
....
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
1
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
1-1
I
._.-.
_.-_..__.._-_
...
,~--
GENERALJNFORMATIQN
CONTENTS
1-2
Company Information and Part Numbering Convention
1-3
Quality and Reliability Information
1-5
.._-_
...-..
_..-_...,-__
COMPANY INFORMATION
COMPANY INFORMATION
Crystal's proprietary SMART Analog™ design technique, incorporating analog and digital circuitry in
monolithic CMOS devices, represents a powerful new technology in the semiconductor industry. This
innovative approach to design eliminates many of the sources of inconsistent performance in traditional
analog circuitry.
Maximum system performance is built-in from initial research on end-user requirements through product definition. Product quality and reliability is designed into the device architecture and is further
assured through rigorous standards for fabrication, assembly and testing. Crystal's part numbering
scheme is as follows:
II
CSLXXXX - TPNNH/R
V
L
DEVICE REVISION: DOES NOT APPEAR HERE ON PACKAGE MARK.
REVISION IS COVERED IN DATE CODE STAMP.
USED ONLY FOR ORDERINGrrRACKING.
SPECIAL HANDLING ,ALPHA ONLY
A·COMMERCIAL HIGH·REL
B-MILITARY 883B REV. C PROCESSING
ELECTRICAL OR SPEED SPECIFICATION. (OPTIONAL) UP TO 2
NUMERIC DIGITS. NO ALPHA CHARACTERS. SEE DATA SHEET
PACKAGE CODE ·REQUIRED ,ALPHA CHARACTER ONLY,NO NUMERICS
P = PLASTIC DIP
S= 0.3' SOIC
E= CERAMIC LCC
C = CERAMIC SIDEBRAZE
D = CERDIP
J= J·LEAD CERAMIC CHIP CARRIER
L = PLASTIC LEADED CHIP CARRIER,J LEAD
G= GULLWING CERAMIC CHIP CARRIER
U= UNPACKAGED DIE
0= PLASTIC QUAD FLATPACK
TEMPERATURE SPECIFICATION· REQUIRED,ALPHA CHARACTER ONLY
SIGNAL CONDITIONING/COMMUNICATION:
C= 0 'C 1070 'C
1= ""o'C 1085 'C
M = ·55 'C 10 125 'C
TEMPERATURE/ACCURACY· REQUIRED,ALPHA CHARACTER ONLY
DATA ACQUISITION:
TEMPERATURE
ACCURACY
GOOD
o
'C
1070 'C
""0 'C to 85 'C
·55 'C to 125 'C
J
BETTER
A
K
B
S
T
BEST
L
C
U
UP TO FOUR ALPHANUMERIC DIGITS COMPRISE REMAINDER OF BASIC PART NUMBER
CRYSTAL PRODUCT LINE (PROPRIETARY PARTS; SECOND·SOURCE PARTS HAVE EXCEPTIONS):
3 = DATA ACQ. SUPPORT CIRCUITS
42=CODECS
43 = D/A CONVERTERS
5 = AID CONVERTERS
6 = TELECOMMUNICATIONS
7 = SIGNAL CONDITIONING
8 = DATACOMMUNICATIONS
CRYSTAL SEMICONDUCTOR
'CS' = ALL CRYSTAL PRODUCTS;EXCEPT FOR
'CXT" = QUARTZ CRYSTALS
"CDB' = EVALUATION BOARD
'CX' = CUSTOM PRODUCTS
REV5
1-3
COMPANYINFQRMATION
In addition to the part number, all Crystal parts. have a second line of marking, which can be decoded as
follows:
(FAT)LLRYYWW(HF)
~ L
L FOUNDRY DESIGNATOR· SECOND DIE (DUAL DIE PKGS ONLY)
UL
". L.
I?EVICEREVISION LEVEL· SECOND DIE (DUAL DIE PKGS ONLY)
ASSEMBLY DATE CODE
DEVICE REVISION LEVEL
.
LOT IDENTIFICATION
TEST SITE DESIGNATOR }
ASSEMBLY SITE DESIGNATOR
NOT USED ON SMALL PACKAGES
FOUNDRY DESIGNATOR
LOT CODE IDENTIFIER • TWO DIGIT ALPHA CHARACTER.
IDENTIFIER SEQUENCE WILL BEGIN WITH
AA,AB,AC, ETC. EACH LOT WILL RECEIVE
A UNIQUE IDENTIFIER REGARDLESS OF
DEVICE OR START DATE. SEQUENCE
BEGINS AGAIN WITH AA WHEN
HAS
BEEN UTILIZED.
z:z.
COMPANY BACKGROUNP
Crystal Semiconductor Corporation was founded in 1984 with the goal of supplying the industry with
high-performance, mixed analog/digital CMOS circuits. In 1991, Crystal became a wholly owned subsidiary of Cirrus Logic.
To meet its objectives, Crystal recruited' a staff of renowned CMOS analog design engineers, a scarce
resource in the industry, and teamed them, with designers trained in system architecture development.
By coupling this design staff with highly qualified application and test engineers and seasoned. management, Crystal has achieved several industry firsts. Systems designers now benefit from the performance
and cost savings of Crystal breakthroughs such as self-calibrating ADCs, monolithic T1 interfaces and
the industry's first implementations of "delta sigma" oversampling A-to-D converters.
Headquartered in Austin, Texas, Crystal sells its products worldwide through a network of manufacturer's representatives. Crystal's entire marketing and sales organization is committed to providing quality products and reliable, rapid service.
.
1-4
----------------------
QUALITY AND RELIABILITY INFORMATION
QUALITY AND RELIABILITY INFORMATION
Crystal Semiconductor is committed at every
level of the company to the highest possible
standards of quality and reliability in its products. This commitment is evident in all phases of
operations: initial product definition, design, fabrication, assembly, test, qualification and customer service. Product quality and reliability are
active concerns of each Crystal employee. Quality is ingrained in every operation throughout the
product life cycle. Some of the key operations
are discussed below.
In Product Definition
To ensure maximum system performance,
Crystal works with users to identify and quantify
the parameters, including quality and reliability
issues, that best serve customer needs. Quality
and reliability become part of the design goals,
along with electrical performance and cost.
In Design
Conservative CMOS design rules are the basis
for all current Crystal products. In addition, extensive use is made of proven standard cells to
drastically reduce the possibility of design errors.
Each pin in every SMART Analog product is designed to meet ESD levels of at least 2500V
when tested per MIL STD 883C, Method 3015.
Each pin is also designed to withstand more than
200mA of DC latch current.
Crystal SMART Analog design architectures
provide quality and reliability comparable to
leading digital devices and memories. This is far
superior to traditional analog ICs and hybrids.
On-chip digital error correction provides stable
performance over time and temperature by taking advantage of digital controls that are insensitive to parametric analog problems such as leakages and shifts in threshold voltage. Using Crystal devices, designers have fewer error sources to
Q&R1
consider. The result is a less complicated, more
reliable system.
In Fabrication and Assembly
Crystal ensures reliable delivery of quality parts
by accessing established foundries in multiple
locations worldwide. Each fabrication facility is
qualified by Crystal. Assembly is performed
both domestically and offshore under carefully
documented and well-controlled conditions.
Wafer fabrication and assembly processes
undergo in-line quality inspections. Wafers are
inspected optically to guidelines based on MIL
STD 883C, Method 2010. Each die is electrically tested using proprietary test circuits that
verify key parameters. Following assembly,
packages are subjected to a variety of mechanical inspections to verify integrity and insure high
quality. (For example, x-ray inspection to 3.0
percent LTPD is one of the standard production
tests.)
In Test
In a break from traditional analog components,
Crystal's SMART Analog products include basic
test capabilities designed into each chip. Crystal's in-process quality assurance program uses
this designed-in testability to monitor and track
the performance and quality of these complex
circuits. Finished packaged components are
tested 100· percent electrically, over temperature
where critical parameters are involved. With
these extensive quality programs, Crystal guarantees outgoing electrical quality levels on all
data sheet specifications to a 0.065 percent AQL
level over the full specified temperature range.
Throughout the assembly and test phases, traceability to the original wafer lot is carefully maintained.
1-5
_.-_..---.-.
__.._-_.
....-
QUALITY AND RELIABILITY INFORMATION
In Product Qualification
Before any Crystal product is released to production and shipped in volume, it must undergo
a thorough qualification program. Crystal has
separate qualification criteria to address both
long-term reliability and infant mortality so that
the sources of failure are identified and eliminated. Crystal uses military specifications as the
guidelines for reliability tests, methods and procedures. (See Qualification Criteria Table)
To ensure reliability of the design and processes,
full qualification requires that three nonconsecutive lots are used during the qualification
program. Fabrication and assembly facilities are
audited every six months and routinely monitored. Any major design or process changes are
re-qualified.
These steps guarantee that Crystal products
maintain the high standards of reliability designed-in from the start.
In Customer Service
Compliance with purchasing requirements is
ensured through the use of Crystal's
computerized system "Compass" (Crystal Online Marketing, Production, and Sales System).
This processing system ensures that all orders
are entered correctly, scheduled properly, produced according to· schedule, and shipped with
zero discrepancies.
All systems and procedures at Crystal
Semiconductor are aimed at continuously
improving the quality and reliability of our products and services to meet the needs of our customers.
Crystal's philosophy on quality is to anticipate
problems and develop systems and controls to
alleviate possible problems~ It is a well .stated
fact by Juran and Deming, two of the nation's
foremost experts on quality, that 85% of all
1-6
quality problems are system related and 15% are
worker related. Therefore, Crystal devotes its
major quality efforts toward preventing system
related quality problems.
Crystal has a very aggressive audit program in
place. Monthly internal· audits are performed to
insure compliance to the extensive documentation of instructions and criteria for testing and
inspection. Semi-annual vendor audits are performed on the assembly and fabrication foundries. Vendor audits insure the adequacy and
compliance of specifications, product flow,
training, process controls and cleanliness. All
internal and external audits have provisions for
ratings and a system for corrective action
requirements. These frequent audits by assembly,
fabrication and quality engineers maximize
system quality compliance.
As an added measure of continued high quality
from assembly and fabrication foundries, thorough incoming inspections are performed. Wafer
level optical inspection is based upon guidelines
of MIL STD 883C, METHOD 2010. Test die are
electrically tested to verify compliance to key
process parameters based upon design rulespecifications. These electrical parameters include
threshold voltages, breakdown voltages, material
resistance, and contact resistance. Assembly
packaging inspection includes external visual,
marking permanency, solderability, x-ray, hermeticity, die shear, wirepull and internal visual.
Preventive measures are very much in force in
the final test area. Equipment calibration and
preventive maintenance procedures are strictly
adhered to. Handling procedures for Electrostatic
Discharge are in place throughout the test areas.
Non-conforming material is segregated until disposition by a material review board. There are
controlled procedures for releasing new test programs and new test equipment to the production
environment. In sUmmary, Crystal Semiconductor is committed to· meet the quality requirements of its customers.
Q&R1
-_ _-_
.. ...-.
-. ..--_._.
__
QUALITY AND RELIABILITY INFORMATION
Qualification Criteria Table
Production Production
Level III
Level II
Level I
2500
--
--
JE[)Ec: 17
Vcc+1V
+SO
Vcc+SO%
+100
SOO
9S%
100%
100%
4000
300
Vcc+SO%
DPM
100%
100%
1S00
1S00
nla
100%
100%
2000
±200
mA
MIL 100S
MIL 100S
1/1674
t.il I,L,100!; ,
SOO
SOO
300
1000
300
100
DPM
FITS
FITS
1k1S%
1k13%
1441S%
144/3%
1k1S%
1k13%
1k13%
1k13%
1k13%
,MethO,d, '
Quality Performance
Outgoing Quality (elec.lvis-mechlship.)
Fault Coverage (Digital)
Datasheet Test Coverage (Digital)
Datasheet Test Coverage (Analog)
ESD - Human Body Model
ESD - Machine Model
Latchup - Power Supply 1
Latchup - 1/0 1
Reliability performance
Infant Mortality (48hrs@125°C or equivf
Early Life (168hrs@125°C or 1yr. equiv.,s
Operating Life (1000hrs@125°C or 10yr, equiv.)3
: Crystal Spec.
nla
Datasheet
Datasheet
MIL 3015
MIL3015
JEDEC 17
Moisture performance
Moisture Resistance - THB (plastic pkgs)
Autoclave (plastic pkgs)
JEDEC 22B
: , J,EDEC 22,B, ,
SOO/S%
96/S%
Mechanical performance
Temp Cycle (plastic pkgs)
Thermal Shock (plastic pkgs)
Temp Cycle wI Hermeticity (hermetic pkgs)
Thermal Shock wI Hermeticity (hermetic pkgs)
Soak &VPR (surface mount plastiC pkgs)
Xray
Dimensions
Solderability
Lead Integrity & Lead Pull
Mark Permanency
MIL 1010
MIL1011
MIL 1010/14
MIL 1011/14
: Crystal Spec.
: Crystal Spec.
MIL 2016
MIL 2003
MIL 2004
k/i IL2()1S,
SOO/S%
200/S%
500/S%
200/S%
3/S%
SOO/S%
3/3%
2.S0%
2.50%
2.50%
2.50%
2.S0%
2.S0%
2.S0%
2.S0%
2.50%
2.S0%
0.6S%
0.6S%
0.65%
0.65%
0.65%
Product Integrity
Design Rule and LVS Checks
Design for Reliability & Packaging
Product Characterization
Test guardbands
: Crystal Spec.
: Crystal Spec.
: Crystal Spec.
:Crystal$pec,
yes
yes
limited
some
yes
yes
full
100%
yes
yes
statistical
100%
Construction Analysis
Wafer cross section & topo
SEM metallization
Package
Notes: 1.
2.
3.
4.
5.
Q&R1
SOO/S%
1k15%
-
World
Class
3/1%
%
%
%
V
V
V
hrsl"loLTPD per lot5
hrsl"loLTPD per lot5
#cyI"IoLTPD per
#cy/%LTPD per
#Cy/%LTPD per
#cyI"IoLTPD per
#cyI"IoLTPD per
%AQL per lot5
%AQL per lot5
%AQL per lot5
%AQL per lot5
%AQL per lot5
lot5
lot5
lot5
lot5
lot5
. Crystal Spec.
MIL2018
:CrystaISp~c, ,L-~~_ _~2-_ _~:!.-....J
at High Temperatures (exc. Lev.lV)
Point Estimate
S5°C, 0.7eV, 60%UCL
#acceptln
LTPD and AGL criteria in table above apply to each lot tested.
CUM LTPD and AQL numbers are also required for Level II:
Individual Lot
Cum Lot ReQuirement
S% LTPD
3% LTPD
3% LTPD
1% LTPD
1.0% AQL
2.S% AQL
1-7'
.._
_-_...-.
.-_
--_._.
_
....
• Notes.
1-8
-.._-_.
...-.
_.....
..__
...
~-
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGIT AL-TO-ANALOG CONVERTERS
2
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
2-1
....-.............
-.
............
...........
DIGITAL-TO-ANALOG CONVERTERS },
CS4328 Digital to Analog Converter
The CS4328 is the industry's first complete stereo
,. digital-to-aIialog outplit system,This I8-bit stereo'
DiA·· coriverter uses Crystal's' well established
oversampling converter techniques.
The CS4328 includes the major system elements
of 8X interpolation filter, (i4X delta-sigmamodulator, I-bit D/A converter arid a 124 dB signal-tonoise ratio analog anti-imaging filter, all in one
packaged, tested, solution. The device features
patented delta-sigma architectures to maintain excellent distortion performance, even at low signal
levels. The output anti-imaging filters are the frrst
to be based on a mixed linear/switched capacitor
architecture. This approach is particularly insensitive to clock jitter and allows the benefit of scaling the bandwidth proportionally to the system ,
master clock. The CS4328 is therefore adjustable
for both audio and voice band applications. The
flexible digital interface makes with CD player
circuitry, DAT recorders and DSP's.
.
CS4303 Digital to Analog Converter
The CS4303 is an all digitall.C. containing an 8X
interpolation. filter· and overall .64X, oversampling
'delta-sigma modulator. Addition Of an external
analog reconstruction filter yields 107 dB dynamic
range with superb low level linearity.
CS4330·Digital to AnBIog converter
Packaged in an 8 pin SOle, the CS4330 is the
world's smallest stereo audio DAC. This 16-bit
complete digital-to-analog output system contains
interpolation filters, 128X oversampling deltasigma modulators, I-bit D/A converters, and analog filtering. De"emphasis is al,so included for CD
applications.
CONTENTS
CS4303 107 dB, D/A Converter for Digital Audio
CDB4303 Evaluation Board for CS4303 .
CS4328 18-Bit, Stereo D/A Converter for Digital Audio
CDB4328 Evaluation Board for CS4328 .
CS4330 16-bit, 8 Pin, Stereo D/A Converter for Digital Audio
2-2
2-3
2-19
2-31
2-50
2-61
.. .
.. """
............
.............
~
""""".
CS4303
Semiconductor Corporation
107 dB, DIA Converter for Digital Audio
Features
General Description
The CS4303 is a high performance delta-sigma D/A
converter for digital audio systems which require wide
• Stereo Delta-Sigma DIA converter
8x Interpolation Filter
64x Delta-Sigma DAC
dynamic range. The CS4303 includes 8x interpolation
and a 64x oversampled delta-sigma modulator that
outputs a 1-bit signal to an extemal analog low pass
filter. The 1's density of the 1-bit signal is proportional
to the digital input.
• Single +5V Operation
• Adjustable System sampling Rates
including 32 kHz, 44.1 kHz and 48 kHz
• 107 dB Dynamic Range Over the
Audio Bandwidth
The CS4303 has a configurable input serial port that
provides four interface formats. The master clock rate
can be either 256 or 384 times the input word rate,
supporting various audio environments.
• ±O.0002 dB Passband Ripple
• Flexible Serial Input Port
Supports Multiple Input Formats
16 or 18 Bit Input Words
Ordering Information:
Model
Temp. Range
CS4303-KS
CS4303-KP
r---~
VOl
Package Type
28-pin plastic SOIC
28-pin plastic DIP
0° to 70°C
0° to 70°C
22
AGND2
AGNDl
DGNDl
VA3
DOR+
~~~~----L-----.J~DOR_
DOL+
DOL-
DZF
MUTE
RST TSTl
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
TST2
XTI XTO CKS SCKO
DGND2
VD2
I This
document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation
(All Rights Reserved)
AUG '93
DS81PP2
2-3
...........
- .._
-..._-..
....
.",
.~' ~
ANALOG CHARACTERISTiCS (T..x =25~c:vD1; VAf, VA2, VA3,VD2 = +S.'OV ; Full-scale Output
SiheWB.Ve, 991 Hz;'·lnput Word Rate = 48 kHz; BICK '= 3.072 MHz; Logic "" = VD; Logic "0" = DGNDJ'
"
Parameter'
'~ ;'.
.
Symbol
Min
Typ
Max
107
THD+N
-
-
Units··
,
Dynamic Performance
,-
Dynamic Range
(NQie 1)
Total Harmonic Distortion + Noise
(digital fullscale input)
Interchannel,lsolation
100
115
dB
dB
dB
Power supplies
RST = High:
Power Supply Current
-
VD1
VA1, VA2, VA3
VD2
VD1
VA1, VA2, VA3
VD2
RST = Low:
-
(RST = High)
Power Dissipation
--
27
4
2
5
0.1
1
rnA
,
-
mA
mA
mA
mA
mA
300
mW
-
165
Note 1. Assumes ideal conversion of 1-bit data to an analog signal
DIGITAL FILTER CHARACTERISTICS (TA = 25°C; VD1, VA1, VA2,
VA3, VD2 = +5V± 5%; In-
put Word Rate = 48 kHz)
Parameter·
Min
Max
Units
-
21.8
23.5
kHz
kHz
-
kHz
90
-
-
33/1WR
-
s
-
-
0
deg
±O.0002 dB corner
to -3 dB corner
Pass Band
,
Symbol
,~.
Typ •
0
0
"
Stop Band
-
26.2
.....
Pass Band Ripple;
-
"
Stop Band Attenuafion
'-
(IWR = Input Word Rate)
Group Delay
Deviation from Linear'Phase
ABSOLUTE MAXIMUM RATINGS (AGND1, AGND2, AGND3,
, .,
±O.0002
dB
-
dB
,
DGND1, DGND2 = OV; All Volt-
ages With Respect to Ground)
,
Parameter
DC Power Supplies:
Positive Digital
Positive Analog
IVA-VDI
(VA1,VA2,VA3,VD2)
Symbol
Min
Max
Units
VD
VA
-0.3
-0.3
-
6.0
6.0
0.4
V
V
V
±10
mA
-0.3
VD + 0.3
".'
,',
Input Current
liN
Digital Input Voltage
Ambient,Operating Temperature"
.,
, ,-10"" '
70
V
"
°C,
Specifications are subject to change without notice.
2-4
DS81PP2
----------------------
CS4303
DIGITAL CHARACTERISTICS (TA = 25°C; VD1, VA1,
VA2, VA3, VD2 = 5V ± 5%; Input Word
Rate = 48 kHz)
Parameter
Symbol
Min
Typ
High-level
Low-level
VIH
VIL
VD - 1.0
High-level 10 = -2OI1A
Low-level 10 = +2011A
VOH
VOL
4.4
-
-
liN
-
±1.0
Digital Input Voltage
Digital Output Voltage
Input Leakage Current
SWITCHING CHARACTERISTICS (TA= 25°C;
-
Max
Units
1.0
V
V
0.1
V
V
-
!LA
VA1, VA2, VA3, VD1, VD2 = 5V±5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Symbol
Min
Typ
Max
Units
Master Clock Frequency using Internal Oscillator:
(384 x Fs) XTIIXTO
CKS=H
(256 x Fs)
CKS=L
10.7
7.1
-
19.2
13.9
MHz
MHz
0.384
0.256
-
19.2
13.9
MHz
MHz
21
-
-
ns
XTIIXTO Pulse Width High
21
-
-
ns
BICK Pulse Width Low
tbickl
30
-
ns
BICK Pulse Width High
tbickh
30
tbickw
80
-
(Note 2)
tblrd
35
-
ns
Parameter
Master Clock Frequency using External Clock:
CKS=H
CKS=L
(384 x Fs) XTIIXTO
(256 x Fs)
-
XTIIXTO Pulse Width Low
BICK Period
ns
ns
BICK rising to LRCK edge setup time
(Note 2)
tblrs
35
-
-
ns
SDATAI valid to BICK rising setup time
(Note 2)
tsbs
35
-
-
ns
BICK rising to SDATAI hold time
(Note 2)
tbsh
35
-
-
ns
BICK rising to LRCK edge delay
RST Minimum Pulse Width Low
Note:
2 periods of XTIIXTO
2. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling."
LRCK
LRCK
lbickl lbickh
BICK
lbickl lbickh
BICK
tsbs
SDATAI
Serial Data Input Timing (Modes 0, 1 and 3)
DS81PP2
SDATAI
MSB
MSB-l
Serial Data Input Timing (Mode 2)
2-5
.'
_.-_..__.._-_
....
.. -.-.
-~-
CS4303··
+
10j.LF~
Audio
Data
Processor
I 15 pF::r
I_ _ _-- _ _ J
External Clock
Mode
Select
DGND2 2
Figure 1. CS4303 Typical Connection Diagram
GENERAL DESCRIPTION·
The CS4303 is a stereo digital-to-analog system
designed for digital audio. The system accepts
data at standard audio frequencies, such as
48 kHz, 44.1 kHz, and 32 kHz. The architecture
includes an 8x oversampling filter followed by a
64x oversampled one-bit delta-sigma modulator
and I-bit DAC as shown in Figure 2. The I-bit
data is passed through an external analog lowpass filter to produce the audio signal.
18 Bit
Digital Input
Is
8x Interpolation
Filter
18 Bit
8 Is
The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of
laser trimmed resistive DAC architectures by using an inherently linear I-bit DAC. The
advantages of a I-bit DAC include: ideal differential linearity, no distortion mechanisms due to
resistor matching errors and no linearity drift
over time and temperature due to variations in
resistor values.
1 Bit
5th-order
Delta-Sigma
Modulator
64 Is
Figure 2. CS4303 Architecture
2-6
DS81PP2
---------------------(dB)
CS4303
'
tIII:IIllIJ]
,
,
,
,
,
rii111
'
,
111
~
,
,
~
~~~~--~~-+~--~~~~--~~~~--~~~--~+-~------+
24 Fs
2Fs
4Fs
6Fs
8Fs
~
16Fs
f (kHz)
Figure 3. CS4303 Interpolation Filter Input
~~r-JL-~--------------------------------~~--~~~Iw-~~~-------.
~
M
~
16Fs
f (kHz)
Figure 4. CS4303 Interpolation Filter Output
Digital Interpolation Filter
The digital interpolation filter increases the sample rate by a factor of 8 and eliminates images of
the baseband audio signal which exist at multiples of the input sample rate, Fs (Figure 3). This
allows for the selection of a less complex analog
filter based on out-of-band noise attenuation requirements rather than anti-image filtering.
Following the interpolation filter, the resulting
frequency spectrum (Figure 4) has images of the
input signal at multiples of eight times the input
sample rate, 8Fs. These images are removed by
the analog filter required to filter the I-bit data.
o,---------------------------~
-20
-40
iii'
~
-60
~
-80
-'2
-100
i
Delta-Sigma Modulator
The interpolation filter is followed by a fifth-order delta-sigma modulator which converts the
8Fs multi-bit interpolation filter output into I-bit
data at 64 times Fs. The frequency spectrum of
the I-bit delta- sigma modulator output is shown
in Figure 5 for an Fs of 48 kHz.
One-Bit DAC
The CS4303 incorporates a differential output to
maximize the output level and minimize the
amount of gain required in the analog filter.
Figure 6 shows each output as well as the differentially summed output for an arbitrary I-bit
data stream.
DO+
-120
00-
-140
-160
(00+) - (DO-)
-180
-200
60
80
100
120
140
160
180
Figure s. 1-bit Modulator Output (Fs
DS81PP2
200
Figure 6. CS4303 Differential Outputs
Frequency (kHz)
=48 kHz)
2-7
.._-_
_.-_..--_._.
__
...-.
:CS4303
Return-to-zero coding is utilized where each occurence of a 1 is 75% high and returns low for
25% of the bit period as shown in Figure 7. This
technique ensures that.the energy within each 1
includes the' effects of finite rise and fall times
regardless of the previous or next state and mini"
mizes distortion.
u
L
Figure 7. Return to Zero Encoding
SYSTEM DESIGN
System Clock Input
The master clock (XTIIXTO) input to the DAC
is used to operate the digital interpolation filter
and the delta-sigma modulator. The master clock
can be either a crystal placed across the XTI and
XTO pins, or an external clock input to the XTI
pin with the XTO pin left floating. .
The frequency of XTIIXTO is determined by the
desired Input Word Rate, IWR, and the setting of
the Clock Select pin, CKS. IWR is the frequency
at which words for each charinel are input to the
DAC and is equal to the LRCK frequency. Setting CKS low selects an XTIIXTO frequency of
256x IWR while setting CKS high selects
384x IWR. Table 1 illustrates various audio
word rates and corresponding frequencies used
in the DAC.
The remaining system clocks, LRCK and BICK,
must be synchronously derived from XTIIXTO.
If the CS4303 internal oscillator is used, the circuit must be configured and XTO buffered as
shown in Figure 1. XTIIXTO can be divided to
produce LRCK and BICK using a synchronous
counter such as 74HC590. Notice that the value
of the capacitor on XTO is 10 pF and the XTI
capacitor is 15 pF, which allows for 5 pF of gate
and stray capacitance.
2-8
LRCK
(kHz)
CKS
..
XTIIXTO
(MHz)
32
low
8.192
44.1
low
11.2896
44.1
high
16.9344
48
low
12.288
Table 1. Common Clock Frequencies
Serial Data Interface
Data is input to the CS4303 via three serial input
pins; SDATAI is the serial data input,BICK is
the serial data clock and LRCK defmes the channel and delineation of data. The DAC supports
four serial data formats which are selected :via
the digital input format pins DIPO. and DIPI. The
different formats control the relationship of
LRCK to SDATAI and the edge of BICK used to
latch data. Table 2 lists the four formats, along
with the associated figure number. Format 0 is
compatible with existing 16-bit D/A converters
and digital filters. Format 1 is an 18-bit version
of format O. Format 2 is similar to Crystal ADCs
and manyDSP serial ports. Format 3 is compatible with the I2S serial data protocol. Formats 2
and 3 support 18-bit input or 16-bit followed by
two zeros. In all four serial input formats, the
serial data is MSB~frrst and 2's-complement format.
Formats 0, 2 and 3 will operate with 16-bit data
and 16 BICK pulses as well. See Figure 11 for
DIF1
DIFO
Format
Figure
0
0
0
8
0
1
1
8
1
0
2
9
1
1
3'
10
Table 2. Digital Input Formats
DS81PP2
_.-_..--__....._-_
..._.-.
LRCK~(l
CS4303
rl
Right Channel
Left Channel
~------------~~I
SUl1ll1t
~~~~I 11 101 11 ; 711J151141131 12 in1101 91s171s15141312111 0V; ;11J1s1141 13 b2111110191s171sIsl4131211 10VI;
BICK
~~:~~I 1110 I 1 1 ; ; J1711SI15114113b211111019IsI7IsI5141312111 0V; ~1711SI1511411311211111019IsI7IeI514131211 10VI;
Figure 8. Digital Input Formats 0 & 1
LRCK
~
Left Channel
I
~L-_ _ _ _ _ _R_ig_h_tC_ha_n_n_e_1--------1
BICK
1SBi! 11 A15114113112in110191s171elsl4131211 101
SDATAI
SDATAI
1SBi!
11 J1711SI1SI14113112j"j1019IsI7Isl sI4131211 I0VI; ~ 1A1711S11S114113112in110191s171elsl4131211 10V; ~
~
Figure 9. Digital Input Format 2
LRCK
IL______L_e_ft_C_h_a_n_n_e_1- - - - - - I I / J
Right Channel
BICK
SDATAI
'---'---.L-LL:..L.:..c:..:c~.:..L.:JL.:...L::..L...JL.:...L::..L.:..l--'-1...:::CL.:.J.--=...L----"rZ-'--( 1111S114113112111110191s171sl s141312111 0I
SDATAI
III 111711S11S114113112111110191s171sls141312111 oV I;; 1111711SI1511411311211111019IsI7IslsI4131211IoV;
1SBi!
1SBi!
;
Z
Figure 10. Digital Input Format 3
LRCK~
Left Channel
---'r
R_ig-'--h_t_C_h_a_n_ne_I_ _ _
L -_ _ _
_2
BICK
SDATAI T7---rT-:-r::Tc::-r-:T"C"r-::-r-::-r::T::lrc::T-:-r::T::l--'-'-~-r:-T-,---,-:--:-r--r:T-cT:-r-::-r-T-::-r:-r-r-T--":-"--'-H
IIl-II-
BICK
SDATAI T7---rT-:-rTc:-r:-r:-:cr-::-r-"---TClrT-,,:-,,--,-,--r-,,----r-,----,,-,-,-,,--,-.,-,,--,---,,---,-H
Mode 0
SDATAI --,--,-,---.,,----r-r-,----,---,r-r-,---,----,,--,----,---,------,----,---,--,---,----,--.--,---,---,---.--,---,---,---.--,---,-,--,-rl
Mode 3
IIII-
Figure 11. Digital Input Formats 0, 2 and 3 with 16 BICK Periods
DS81PP2
2-9
---------------------16-bit timing. However, the use of
BICK = 64x IWR is recommended to minimize
the possibility of performance degradation resulting from BICK coupling on the supply voltages.
C$4303
RST is an active low signal that resets the digital
filter and delta-sigma modulator and synchronizes LRCK with internal control signals. The
CS4303 DOL+\- and DOR+\- outputs are forced
to zero during reset.
A two stage MUTE operation can be implemented by forcing SDATAI to 0 using an AND
gate as shown in Figure 12. The first mute occurs following 33 LRCK cycles when the 0
input data propagates to the output of the DAC.
Following a total of 4096 LRCK cycles with 0
input data the output of the CS4303 will mute.
Upon release of the MUTE command and non-'
zero input data, the CS4303 output mute will
immediately release. However, 33 LRCK cycles
are required for input data to propagate to the
output.
Power-Up Considerations
Analog Output and Filtering
Upon initial application of power to the DAC,
the digital filter registers will be indeterminate,
RST should be low during power-up to prevent
this erroneous information from being. output
from the DAC. Bringing RST high will initialize
these registers.
The primary function of the analog filter is to
attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. The selection of the filter transfer function is based on
the optimization of out-of-band noise attenuation, passband amplitude and phase
requirements. The computer simulated frequency
spectrum of the I-bit delta-sigma modulator output is shown in Figure 5 for an Fs of 48 kHz.
Figures l3-15 show the results of computer
simulations demonstrating the attenuation of outof-band noise with 3, 5 and 7 pole Butterworth
filters. The filter corner frequencies were selected to achieve a maximum attenuation of
0.2 dB at 20kHz.
Reset
Muting
The Mute functions of the CS4303 involve the
recognition of 0 input data for 4096 conse,cutive
LRCK cycles. If the MUTE pin is HIGH, the
DATA outputs will be forced to 0 following
4096 LRCK cycles with 0 input data. If left
LOW, the MUTE circuit will ignore 0 input data.
The DZF, Data Zero Flag, pin will go HIGH following 0 input data for 4096 consecutive LRCK
cycles regardless of the Mute pin status. The
DZF output, can be used to control an external
muting circuit.
",- 8 kHz Fundamental
120 kHz Bandwidth
- -,-- , - - , - -,- - -:OynamlcRange=52,87dB
,20
-40
- .,. _.,
-60
- -.- -
.,. - .,
-
.,.
- - ,.
,
,
,
- -,-
- -, -
- ,. - -
-
-
-
iii" ·80
:; -100
'0
:ijl.120
c
'"
~ -140
-160
_!.
-
-
.' -
_!...
.'.
.'
-
I.
__
-180
·200
Figure 12. Muting Implementation
0
28
48
72
96
120
Frequency (kHz)
Figure 13. Simulated Noise Attenuation
3rd Order Filter
2~10
DS81PP2
----------------------
CS4303
O,-~--~--~--~------------------.
o,--,c--~--~--~------------------,
-20
-40
_ (":" 8_ kl:!z F~n~ame_n~~1 _
120 kHz Bandwidth
.. Dynamic Ra~ge = 77.55 dB
-20
-
-,
-40
-,-
-
-, -
-
;-
-
.,.
-
-
-
i"
-
.,.
-
-, -
-
-60
-60
-80
iii -80
" -100
:; -100
~
~
-,-
-
~
-120
!
'"
:!1! -140
-160
-180
-,-
-
120 kHz Bandwidth
- Dynamic Range = 99.3 dB
-, -
-
., -
-;-
i"
-
-,-
-
-,
-
-
- -,- - ., - -
;-
-
..
- -
-
- - , - - - - - -" - - - - - - - - - ,
,
,
,
,
J
I
- - - - - - - - - - - - - - - - - - - - - - - - ,
"
-200 -t--4r-----t----j---t----t---j----t---j----t-----i
24
48
72
96
120
o
120
96
i"
-140
-180
48
72
Frequency (kHz)
-
-120
-160
24
-, -
-
I
"C
~
_ ~!l ~~~ t:u~d'!me~al_
-
Frequency (kHz)
Figure 15. Simulated Noise Attenuation
Seventh Order Filter
Figure 14. Simulated Noise Attenuation
Fifth Order Filter
Measuring System Performance
The suggested filter of Figures 16-19 is as-pole
Butterworth modified to realize a 6-pole response. Implementing a pole as a passive RC in
the input of the analog circuit along with a high
slew rate op-amp will eliminate slew rate related
distortion. This architecture provides matched
loading for the differential outputs and a noisefree pole for additional out-of-band noise
attenuation.
The effects of out-of-band noise must be considered when making THD+N and dynamic range
measurements. The dynamic range specifications of Figures 13-15 are identical over a 20kHz
bandwidth but differ by 46 dB over the 120kHz
bandwidth. The proper use of a measurement
bandlimiting filter is critical for evaluating the
in-band performance of systems with low-order
analog filters. The measurement bandwidth must
be properly limited to prevent out-of-band energy from dominating the measurements.
680pF
2.1k
1.21 k
1.21 k
5.62k
2.1k
2.1k
1050 .OO22J!F
r---------1
2.1k
.0033J!F
Analog
Out
2.1k
1050
2.1k
1.21 k
1050
1.21 k
I·
OO22 J!F
5.62k
680pF
Figure 16.. Suggested 6-Pole Analog Filter
DS81PP2
2-11
----------------------
CS4303
1-2: •••.•.•.•.•. !•.•.•.•.•. . }.•.•.•.•.•.:..\ :• •.•. . . .
i: • • • • .• • • •. :• • • • .• • • \ • • .•
100
10k
1k
100k
Frequency (Hz)
Figure 17. Simulated Analog Filter Frequency Response
o
-~--,-------,------;----..
,
,
iii'
~
,
- - - - - - - - - - - -
-4
-
,
- - - -
-- -
,
- ,- -
- - - - -, -
-- --- -
-
- -
-
- - - - - - - -
--
- - - - - - -
- - - - - - - ,- - - - - - - -, - - - - - -
-
-
- -
1
-' -8
'S
%
0-12
- - - - - - - , - - - - - - - -, - - - - - ,
- ,-
,
,
- - - - - - - - - - - - - - - - - - - - - - ,
,I
-- -
-16
,
I
- - - - - - - - ,
100
-- -
-
- -
-
- - -,- -
-
- - -
I
- - - - - - - - - - - ,
-
- - - - - - - - - - - - - - - - t
1K
I
10K
100K
Frequency (Hz)
Figure 18. Simulated Analog Filter Frequency Response
Expanded Scale
40
,
,
,
- - - - - - - - - - - - - - -
,
I
,
,
- - - - - - ,- - - - - - - ,- - -
10
o
,
,
- - - , - - - "- - - -, - - - , - - -
- - - ,
5
- - ,- - - - - - - , ,
I
15
I
- -
- - - - - - - - - - - - - - - I
25
I
,
35
I
45
Frequency (kHz)
Figure 19. Simulated Analog Filter Group Delay
2-12
DS81PP2
---------------------System Performance Measurements
The following collection of CS4303 measurement plots (IWR = 48 kHz) were taken from a
CDB4303 evaluation board with an Audio Precision Dual Domain System One. All FFT plots
are 16,384 point. Several of the plots are influenced by inadequate dithering of the test signal.
Figure 20 shows the unmuted noise. This data
was taken by feeding the CS4303 all zero's. This
plot shows the noise shaping characteristics of
the delta-sigma modulator combined with the
analog filter.
Figure 21 shows the A-weighted THD+N vs signal amplitude for a dithered 1kHz input signal.
The small variations in THD + N at around
-70 dB are caused by inadequate dithering of the
test signal. The System One was set to 18-bit triangular dither.
Figures 22 and 23 show the fade-to-noise
linearity. The input test signal is a dithered
500 Hz sine wave which gradually fades from
-60 dB level to -120 dB. During the fading, the
output level from the CS4303 is measured and
compared to the ideal level. Notice the very
close tracking of the output level to the ideal,
even at low level inputs of -90 dB. The gradual
shift of the plot away from zero at signal levels
< -100 dB is caused by the background noise
starting to dominate the measurement. Figure 22
shows the result with 18-bit dithered data. The
1 dB shift at -95 dB is due to inadequate dither.
Figure 23 shows the result with 16-bit dithered
data.
CS4303
data pattern is taken from track 21 of the CD-l
test disk. Notice the increasing staircase envelope, with no decreasing elements. Notice also
the clear resolution of the LSB. For this test, one
LSB is a 16-bit LSB.
The following tests were done by filtering the
analog output of the CS4303 with the System
One analyzer 1 kHz notch filter to reduce the
peak signal level. The resulting signal was then
amplified and applied to the DSP module, avoiding distortion in the System One NO converter.
Figure 26 shows a 16K FFT Plot with a 1 kHz,
input. Notice the low order harmonic distortion at < -100 dB.
o dB
Figure 27 shows a 16K FFT Plot with a 1 kHz,
-10 dB input. Notice the almost complete absence of distortion, with a small residual 2nd
harmonic below -120 dB.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your
Figure 24 shows a 16K FFT plot result, with a
1 kHz -100 dB 17-bit dithered input. Notice
the lack of distortion components.
Figure 25 shows the monotonicity test result
plot. The input data to the CS4303 is +1 LSB,
-1 LSB four times, then +2 LSB, -2 LSB four
times and so on, until + 10 LSB, -10 LSB. This
DS81PP2
2-13
--------~------------CRYSTAL noiseunm
AMP1(dBr)
CS4303
vs FREQ(kHz)
0
Ap
CRYSTALd-a-lin
10
BANDPASS(dBr)
vs GENAMP(dBFS)
Ap
-20
-40
4
-60
-80
0
-100
-2
-120
-4
-140
-6
-160
-8
-180
~ 9.82
19.6
29.4
39.2
49.0
58.8
68.6
78.4
88.2
98.0
Figure 20. Unmuted Noise
THD+N(dBr)
vs GENAMP(dBFS)
CRYSTAL THDAMP1
-80 '---~-----'------'---------""CA"p
-85
-10
-140
-130
-120
-110
-100
-90.0
-80.0
-70.0
-60.0
Figure 22. Fade to Noise Dithered IS-bit Linearity
CRYSTALdalin16
BANDPASS(dBr) vs GENAMP(dBFS)
10 ,----~r---------------------A~p
8
6
-90
4
-95
-100
o
-2
-4
-110
-6
-115
-120 '-----~---~---~---~--_~_ __"
-100 -90
-80
-70
-60
-50
-40
-30
-20
-10
0
Figure 21. 1 kHz A-weighted THD + N vs Level
2-14
-8
-10 .'---~-------~--------~----~-~
-140
-130
-120
-110
-100 -90.0
-80.0
-70.0 -60.0
Figure 23. Fade to Noise Dithered 16-bit Linearity
DS81PP2
----------------------
CS4303
AMPl (dBr) vs FREQ(Hz)
CRYSTAL lKl00fft
o r-~~~~----------------~~~-A~p'
-20
I
,
CRYSTAL 1KODBFFT
o
-20
"""
I,',',
-40
-40
-60
-60
-80
FREQ(Hz)
vs AMPl (dBr)
, ' , ' ",
-
I
-
,
I
1',1,
- - - - -
-
I
I,
Ap '
"',
- - - - - -
-, - ,-, -, ,-, ,-, -
-100
-100
-:- :-:-: ::·'1'-
, I , ' '"
-,- '-1-' .. ' .. -
-120
,
-140 ~-,-,,-,,-,- -
I
I
I
-120
'"
!-,-,-,-:-:,:,-
-140
-160
100
20
lk
10k
20k
Figure 26. 1kHz 0 dB FFT
Figure 24. 1 kHz -100 dB FFT
CRYSTALmonoton
1000
AMPl (uV) vs TIME(ms)
,------------~---~-_;_--__n-____;;_::_,
800
AMP1 (dBr) vs FREQ(Hz)
CRYSTAL lkmlOfft
or---~~--~-~~-~-----~A~p
-20
600
400
-60
200
o
~"'IIUtrUIIUIiU
-200
-80
-100
-400
-120
-,- ,-,-, ", ,-, -
-600
-140
-800
-1000 0L --5~r-l0C:-~15---'-20'-------2~5--3:-0-~.L...r-.LlJ~4-5---'50
Figure 25. Monotonicity Test (16-bit Data)
DS81PP2
Figure 27. 1 kHz -10 dB FFT
2-15
-
.._-_
.-_
_
..---._.
__
...-.
" CS4303·.
PIN DESCRIPTIONS
Crystal Oscillator Output
XTO
Crystal Ground
DGND2
Left Output Data +
DOL+
Left Output Data -
DOL-
Left Analog Power 1
VA1
Left Analog Ground
AGND3
Left Analog Power 2
VA2
1-
28
XTI
Crystal or Clock Input
2
27
VD2
Crystal Power
26
DOR+
Right Output Data +
25
DOR-
Right Output Data -
: CS4303
5
24
AGND1
Right Analog Ground 1
6'
23
VA3
Right Analog Power
7
22
AGND2
Right Analog Ground 2
Data Zero Flag
Left/Right Clock Input
Clock Select
CKS
8
21
DZF
9
20
LRCK
10
19
BICK
Serial Bit Clock Input
Serial Data Input
Mute
MUTE
Reset
RST
Test 1
TST1
11
18
SDATAI
Test 2
TST2
12
17
SCKO
256 Fs Clock Output
Digital Input Format 1
DIF1
13
16
DGND1
Digital Ground
Digital Input Format 2
DIFO
14
15
VD1
Digital Power
Power Supply Connections
VAl, VA2, VA3 - Analog Power, PINS 5, 7, 23.
Positive analog supplies. Nominally +5 volts.
AGND1, AGND2, AGND3 - Analog Grounds, PINS 6, 22, 24.
Analog ground reference.
VD1 - Digital Power, PIN 15.
Positive supply for the digital section. Nominally +5 volts.
DGND1 - Digital Ground, PIN 16.
Ground for the digital section.
VD2 - Crystal Power, PIN 27.
Positive supply for the crystal oscillator. Nominally +5 volts.
DGND2 - Crystal Ground, PIN 2.
Crystal ground reference.
2-16
D.S81PP2
----------------------
CS4303
Digital Inputs
XTI - Crystal or Clock Input, PIN 28.
A crystal oscillator can be connected between this pin and XTO, or an external CMOS clock
can be input on XTI. The frequency must be either 256x or 384x the input word rate based on
the clock select pin, CKS.
MUTE - Mute Input, PIN 9.
This input determines if the CS4303 will recognize an input string of 4096 zeros to initiate a
muted output. If left low, the CS4303 will not mute.
DZF - Data Zero Flag, PIN 21.
This pin will go High following 0 input data for 4096 consecutive LRCK cycles regardless of
the Mute pin status.
SCKO - Serial Clock Output, PIN 17
Clock output of 256x the input word rate regardless of the CKS pin status.
LRCK - LeftlRight Clock, PIN 20.
This input determines which channel is currently active on the Serial Data Input pin, SDATAI.
The format of LRCK is controlled by DIFO and DIFl.
BICK - Serial Bit Input Clock, PIN 19.
Clocks the individual bits of the serial data in from the SDATAI pin. The polarity with respect
to the serial data is controlled by DIFO and DIFl.
SDATAI - Serial Input, PIN 18.
Two's complement MSB-first serial data of either 16 or 18 bits is input on this pin. The data is
clocked into the CS4303 via the BICK clock and the channel is determined by the LRCK
clock. The format for the previous two clocks is determined by the Digital Input Format pins,
DIFOandDIFl.
DIFO, DIFI - Digital Input Format, PINS 14, 13.
These two pins select one of four formats for the incoming serial data stream. These pins set
the format of the BICK and LRCK clocks with respect to SDATAI. The formats are listed in
Table 2.
CKS - Clock Speed Select, PIN 8.
Selects the clock frequency input on the XTI pin. CKS low selects 256x the input word rate
(LRCK frequency) while CKS high selects 384x.
RST - Reset, PIN 10.
When reset is low, the filters and modulators are held in reset.
DS81PP2
_
..--__.._-_
...-..
.-_
CS4303
TST1, TST2 - Test Inputs, PINS 11, 12.
Allows access to the CS4303 test modes, which are reserved for factory use. Must be tied to
DGND.
Digital Outputs
XTO - Crystal Oscillator Output, PIN 1.
When a crystal oscillator is used, it is tied between this pin and XTI. When an external clock is
input, this pin· should be left floating.
DOL+, DOL- - Digital Left Channel Output, PINS 3, 4.
Differential digital output data for the left channel.
DOR+, DOR- - Digital Right Channel Output, PINS 26, 25.
Differential digital output data for the right channel.
2-18
DS81PP2
.... .. ......
I CDB43031
~..,~
•~-1IIIIr _ _
. . ..
."."
Semiconductor Corporation
EvaluatianBaard far CS4303
Features
General Description
The CDB4303 evaluation board is an excellent means
for quickly evaluating of the C84303 18-bit, stereo D/A
converter. The board is configured to accept digital
audio data via coax or optical interlaces. Analog outputs are provided via RCA connectors for both
channels. Evaluation requires an analog signal analyzer, a digital signal source, and a power supply.
• Demonstrates techniques used to
achieve 104 dB Dynamic Range and
fullscale THD+N > 101 dB.
• CS8412 Receives AES/EBU, S/PDIF,
& EIAJ-340 Compatible Digital Audio
The CDB4303 includes optocouplers, clock jitter attenuator, off-chip 1-bit latch, analog filtering and a
C88412 digital audio receiver I.C. The C88412 provides the system timing necessary to operate the
C84303 and will accept AE8/EBU, 8/PDIF, and EIAJ340 compatible audio data.
• Digital and Analog Patch Areas
• Requires only a digital signal source
and power supplies for a complete
Digital-to-Analog-Converter system
ORDERING INFORMATION:
CDB4303
Block Diagram
256 x Fs
Clock
Opto
Couplers
Clock
Jitter
Right
Line
Out
Left
Line
Out
R+
AE8~EBU3 ~
'."
&PDIF~.
CS8412
CS4303
RL+
L-
Optical
Input
! !
OV
+5V
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4457581
! ! !
-12V
OV
+12V
Copyright © Crystal Semiconductor Corporation 1992
(All Rights Reserved)
MAY '93
D881OB2
2-19
--
-.
..- .....-.......
~
'. OD84303
...",.,.,." .•• ••'iitti.
CS4303 AudioDAC
<•
A description. of the CS4303 including the func,
tiottsof CKS, MUTE, DIFO and DIF! are
'discussed in the CS4303 data sheet. The recom'
mended jumper positions for the evaluation
board are listed in Table 2. A power,up and user
activated ryS~t circuit is provided by D 11, R7,
'.'
.
C6, U4 and SW2.
The CDB4303 is an example application of the
CS4303 which includes optocouplers, a Phase
Lock Loop / VCXO and external latches. These
techniques allow for maximum isolation and
control of potential error mechanisms.
VD+
.011
BAT85
C2
RST
""B
TSTl TST2
25
VAl
C3 0:1 J.1F"
VA2
C4 0.1 J.1F. '.
VA3
C5 0.1 J.1F
VD2
DOfI~
DOR-
VOl
24
22
6
16
2
MCLK
28
26
AGNDl
DOR+
.,I'.!
AGND3
DGNDl
U1
DGND2
CS4303
is.
:::I
0
0
%
0
XTI
{:.
DOL-
'"~
FSYNC
en
u
E
e
SCLK'
20
19
DOR+
AGND2
4
DOL-
LRCK
BICK
IL
SDATA
18
SDATAI
DOL+
J2
3
DOL+
J5
Figure 1. CS4303 DAC Connections
2-20
DS81DB2
_
..---'._.
__.._-_
...-.
.--
CDB4303
VD+
T
Error Information
SWl
L,; -, 1
C7
0.1 IlF
2
Channel Status
U4A
74HC14
VD+
RPl
10kn
C30
16
:r
7
22
VD+
SEL VA+
l~O.lIlF =6
MO
, J8
Ml
CO/EO
M2
5
5
11
4
3
3
13
2
Ca/El
M3
Cb/E2
FILT
, J9
C12
~
U2
Cc/FO
0.047IlF
CS8412
Cd/F1
VERF
f-'-------"'27'-1Ce/F2
U3
MCLK
19
MCLK
11
FSYNC
74HC04
J12
13"-lCSLRIFCK
...- - - - - - - - - "
FSYNC
[5
..,.
'"
en
'U
JP2
12
SCLK
26
SDATA
SCLK
0
I-
10 RXN
SDATA
Scholl
67129600
Optical /V"
Input /V"
5
Figure 2. CS8412 Digital Audio Receiver Connections
CS8412 Digital Audio Receiver
The system receives and decodes standard
AES/EBU and S/PDIF data formats using a
CSS412 Digital Audio Receiver as shown in Figure 2. The data input circuit can be configured to
accept either professional or consumer modes via
coax .or optical means. The outputs of the
CSS412 include a serial bit clock, serial data, a
word clock and a 256Fs master clock
DS81DB2
The operation of the CSS412 is covered in detail
in the CSS412 data sheet and includes a description of the AESIEBU and SIPDIF hardware and
data formats. Refer to Table 2 for the CDB4303
jumper options for the CSS412. The circuit is
factory configured for AESIEBU and can be
modified for SIPDIF by substituting a 75 ohm
resistor for RS.
2-21
_.-_..--_
__.._-_
...-..
The LEDs, D4-DS and DlO, perform two functions. When S I is in the Channel Status position,
the LEDs display the channel status information
for the channel selected by J12. The channel
status information is explained in the CSS412
data sheet.
When S 1 is in the Error Information position,
the LEDs D4-D6, display encoded error information that can be decoded by consulting the
CSS412 data sheet. Encoded sample frequency
information is displayed on LEDs D7,DS and
D I 0 provided a proper clock is being applied to
the FCK pin of the CSS412 .. When an LED is
lit, this indicates a "I" on the corresponding pin
located on the CSS412. When an LED is off,
this indicates a "0" on the corresponding pin.
Neither the L or R option of J12 should be selected if the FCK pin is being driven by a clock
signal.
Optocouplers
Optocouplers provide effective isolation between
the analog circuitry and digital circuit noise, Figure 3. Hewlett-Packard HCPL-7101 optocouplers
were chosen since they have built in CMOS input buffers and operate at 40MHz. The high
output slew rate of the optQcouplers yields minimum corruption of the signal edges and low
jitter on the clock. The input side of the optocoupIers is well decoupled, since the LED's create
significant current spikes. The output side of the
optocouplers is referenced to analog ground and
the data optocouplers are powered with a separate +5V power regulator, V16. A large physical
gap between the pins of each side of the optocoupler package was maintained on the circuit
board to ensure maximum digital to analog isolation.
I-Bit Latch
The external CMOS latch, Figure 3, used to time
the data is a 74ACll074 from Texas Instruments. This dual D-type flip-flop was chosen
2-22
CDB4303
because of its center power and ground connections, which reduce internal inductances and the
possibility of the supplies being modulated by
the output signal. The device also has a high output drive capability which allows minimizing the
input impedance of the analog filter for noise
considerations.
The power supplies to the latch are the voltage
references for the I-bit data. Each latch is powered from a separate +5V regulator, V14 and
VIS, to decrease interaction between channels
and minimize noise. Extreme care was taken to
optimize the supply decoupling with high frequency capacitors positioned very close to the
supply and ground pins.
Proper latch supply decoupling is also important
to minimize distortion. The one's density of the
data produces variations in the latch power supply loading. Modulation of the latch supply
voltage by the I-bit data is effectively multiplying the signal by itself, which produces 2nd
harmonic distortion.
There are significant advantages in the use of a
dual flip-flop. Due to the differential nature of
the DAC output, it is possible to minimize thermal gradients within the latch and improve
distortion performance. This can be accomplished by using a separate dual latch for each
channel.
The latch clock rising edge is timed so that the
set-up and hold time requirements for the data
inputs are met with a generous margin.
Clock Jitter Attenuator / VCXO
Clock jitter can originate from .the original
AESIEBV signal, the VCO in the CSS412, and
from the optocouplers. To reduce the clock jitter
as much as possible prior to the latch, a Phase
Lock Loop (PLL) is used as a jitter attenuator.
Figure 4 shows the schematic of the latch clock
generator/jitter attenuator. The PLL consists of a
DS81DB2
----------------------
CDB4303
lATCH CLOCK
VA4+
v
14
lClR
lClK
13 10
+
lPRE 11
VCC
10 f-=2_+-_ _ _ _ __
R-
Ul0
u:
8'
c:
«
(ij
DOR+
R+
VD+
Jll
0
I-
VA4+
14
13
lClR
lClK
lPRE
11
VCC
L-
10 2
10
Jll
u:
Ol
0
(ij
Ull
9 2D
VD+
VA4+
C16
8
2ClK
20 S
4
l+
«"
0
I-
VA2+
us - U9 =
HCPl-710l
Ul0 - Ull= 74ACll074
Figure 3. OptocoupJers and Latch Circuitry
phase detector, a voltage controlled crystal oscillator and a loop filter.
The phase detector was implemented using an
74ACll086 exclusive or gate. This phase detector introduces a 90 degree phase shift, which
results in the correct timing of the output clock
for the latch. The phase detector is also inherently free from hysteresis, which improves jitter
performance.
The requirement for a low jitter clock led to the
choice of a voltage controlled crystal oscillator
DS81DB2
(VCXO). The VCXO has a limited frequency
range and a substitution is required for changes
in sample rate. The CDB4303 includes a 11.2896
MHz VCXO for a 44.1 kHz sample rate and
and a 12.288 MHz VCXO for a 48 kHz sample
rate. The VC7025 VCXO can be obtained from
RALTRON (phone number 305-593-6033).
Power for the phase detector and VCXO must be
very clean in order to avoid output clock jitter.
An independent +5V regulator, U16, for the
VCXO and phase detector ensures a minimum
amount of coupling between the VCXO/phase
2-23
-------=::.
:.,==~;
CDB4303
VD+
'"
~
Cfl
MCLK
U
2
E
e
R2
680n
u.
j
U13C
U5 = HCPL -7101
U13 74AC11086
U12 = VC7025
=
LATCH CLOCK
Figure 4. Clock Jitter Attenuator I VCXO
detector and the remaining circuitry via the supply. The layout of the PLL is such that the loop
filter is close to the VCXO. This minimizes the
possibility of induced noise into the control pin
on the VCXO.
frequency and group delay plots is included in
the CS4303 data sheet.
Power Supply Circuitry
Figure 6 shows the evaluation board power supply block diagram. Power is supplied to the
evaluation board by five binding posts. The 5 V
analog power supply inputs are derived from
12 V using the voltage regulators U14 - U17.
The +5 V digital supply for the converter and the
Analog FilleT
The circuit of Figure 5 is a 5-pole Butterworth
modified to realize a 6-pole response. A complete discussion of the circuit including
680pF
1.21k
1.21k
2.1k
R18(33)
R(L·)
R13(29)
R16(31)
R22 (37)
5.62k
2
6
2.1k
1050
R28 (43)
2.2nF
3
U18(22)
C34 (38)
6
3
S.3nF
U19(23)
3
2.
R+
(L+)
2.1k
1050
R26(41)
U20(24)
C50 (56)
VOUTR
(VOUTL)
~18nF
C39(55)
f.
1.21k
1.21k
5.62k
R14(30)
R17(32)
R19(34)
fr
C36 (53)
Right channel show~. Parenthetical identifiers designate
left channel components and signals.
U18-U25 = Burr·Brown OPA627
Figure 5. 6-Pole Analog Filter
2-24
DS81DB2
..--_
_.-_..--_._.
__
...-.
CDB4303
+12V~~--~--~--~--~----~--~--~------~------~------~~----~~-+VA+
AGND~~--~--~--~--~----~--~--~
-12V
VA4+
~----4-------4---_-----4-----4--_
:&O.II'F
D2
Dl
=D3 =P6KE 13A From Motorola
=P6KE-6VBP from Thomson
~.47I'F
U14 - U17 =7BL05
VD+
+5V
+
Dl
Ll
DGND
C26
1 1O l'F
VD2+
VA1+:
VA2+:
VA3+:
VA4+:
To Right Channel Data Latch
To Left Channel Data Latch
To Clock Jitter Attenuator
To Data Octocouplers
471lH
Figure 6. Power Supply
discrete logic on the board is provided by the
+5 V and DGND binding posts. D1, D2, and
D3 are transient suppressors which also provide
protection from incorrectly connected power
supply leads. The evaluation board intentionally
isolates the analog and digital ground planes.
The digital and analog grounds should not be
joined at the power supply.
Evaluation using the CDB5326/7/S/9 or
CDB5336/S/9 as a signal source
An analog input of ± 3.68 V will produce a full
scale digital output from the CS5336nt9 and the
CS5326nt8/9. A full scale digital input to the
CS4303 will produce a full scale output of
± 2.8V resulting in an overall loss of approximately 2.3 dB from input to output.
Evaluation of the CDB4303
The DAC system can be evaluated by connection to any digital audio source via either the
AESIEBU or SIPDIF interface. This includes a
CDB532617/8/9, CDB5336/8/9 or CDB5389
Analog-to-Digital-Converter evaluation board as
well as a CD or DAT digital output.
Interconnection requires the power supply connections and a shielded twisted pair cable (or
optical cable) connecting the digital outputs from
the ADC evaluation board to the digital inputs
on the CDB4303. It is recommended that the
power connections for each board are brought
directly from the power supply and not in a
"daisy-chain" manner from board to board.
The CDB4303 jumpers should be set to the factory default setting of Table 2. The VCXO must
be selected for the appropriate system sample
frequency.
References:
OS81082
"An I8-Bit Delta-Sigma D/A Processor System
Achieving Full-scale THD+N > lOOdB" by
Steven Green and Steven Harris presented at the
93rd Audio Engineering Society Convention.
Preprints are available from the AES and Crystal
Semiconductor.
2-25
___-_
--.. -........_.-.
-......
CONNECTOR
CDB4303
INPUT/OUTPUT
SIGNAL PRESENT
+12 Volts from powe(supply for analog section
+12
input
-12
input
AGND
input
analog ground connection from powersupply
+5
input
+5 Volts from power supply for digital section
DGND
input
digital ground connection from power supply
OUTL
output
left channel analog output
OUTR
output
right channel analog output
OPTICAL INPUT
. input
digital audio interface optical input
DIGITAL INPUT
input
' .
"12 Volts from poiNer supply for analog section
digital audio interface coax input
Table 1. System Connections
,
JUMPER
J12
JP2
J8,J9
J5
L
R
8ee 088412 data sheet for details
COAX
activates the coax input
OPTI
activates the optical input
selects digital audio input source
C88412 mode select,
MO
"Low
M1
"Low
M2
"Low
,M3.
"Low
8ee' C88412 data sHeet for details
",
.'
J2
FUNCTION SELECTED '
POSITION
'selects channel forC88412
channel status information
l.
J2,J5
"
";'
PURPOSE
DIFO
"Low
DlF1
"High
C84303 mode select
C84303 clock select
MUTE
8ee C84303 data sheet for details
"Low
selects 256Fs master clock
High
' •s.elects 384Fs master clock
CK8
"High
Low
Mute function is active
disables Mute function
" Default setting frOI)1 factory
Table 2_ Jumper Selectable Options
2-26
DS81DB2
iCD
...
C
~
[]
..
IT
~ f.:
~~
U§COM
nl=i.'
~
~
~
~
.
MTI
14
D~MfI
~
04. '
UI
0.,.
'rr"" ~n
'" ~~==
B
g.OO ~ .~B~a;>..' ,~w ,
.0 DC'.
c , '0
"
CI C33
m
~ ~ ~!!
LOW
U4
.n
RI
III
-
""
cr;;t
- .
UI' '"
0 0
~...
...
00
Cl1
p~
cootle
0Q~u C4~
oU7
.7el
".
-cJ.
-cJ.
"
~u 55 ::TATUS ,__• ~ CO ~,
L"O 0 " DilgCl, 0" On,. . . CI' CM
.3yi
to
::Ie .'"
R2'-~
041'"
,so.,.:.O02.
OCli
;0
ut
LIICII
ca
en
Ul1
c"
g~ , ·"02'"'
C1C. c:t)
n
.
Lo
',u
U2"",".. ".
ffiOa
..
DIG!T:L . ; ' .
INPUT
&,'C..
II
C
mCD
<:r::)C"
0
1I
-cJ.
Ul
INPUT
D
..,
"
C42
~ =DC.
.-'--
-I
,
~mn
CDB4JOJ
...
n .. v.v.
/
[]
OUTR
[.1:-"
';;..:. '"
e71
~.53
e32
OUTL
U2ht
f:
RJ1PU22
ct'tj~
"~e
CL:)
Evaluation Board
...
tl1Bm
'",c.'!. •••
~2J
' ' ' - c : :~
J-
In. ~U
-cJ.
CIS
""C15
::I
,,,:C:;-,,p
[g
~ [-0
@ @ @ ~==
ell
.30'
.
[]
,,;
""
.....
i"I~. :
DJ
~w ~~I'''''~
CDCl.
OPTICAL
(.>
!=
tI.l
_
02
€)w
.~ cfi ~~
'"
:-'I
.
-{C}-
a./f2
COl"
"
[OJ'' G'''0~"O
"ODQIDG
C,.
g
,=,....
en
[., 0
UlS ell
C:C
~u
coo
g
!!!
o
c
OJ
~
Co)
~
I
-__-_
.... ._..
-.-..,..,-...-
CDB4303,
•
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
• ••••••••••••••
•••••••••••••••
•••••••••••••••
•••••••••••••••
.....
..........
•••••••••••••••
,
••••••••••••••
••••••••••••••
•••••••••••••••
••••••••••••••
••••••••••••••••
.'.:..........
••••••••••••••••
••••••••••••
••••••••••••
••••••••••••
•
Figure 8. CDB4303 Rev. B. Component Side
2-28
DS81DB2
----------- -----------
CDB4303
•
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
••••••••••••
•••••••••••
...........
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
• ••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••
••••••••••••
:::::::::::: 4t
Figure 9. CDB4303 Rev. B. Solder Side
OS81082
2-29
-_.._-_.
;
;.,,,=~
=;"
CDB4303 :.
• Notes •
.)
2-30
D581D.82
.
... ........
...
~~
CS4328
~-.~.
~~
~
Semiconductor Corporation
~
1B-Bit, Stereo DIA Converter for Digital Audio
General Description
Features
• Complete Stereo DAC System
8x Interpolation Filter
64x Delta-Sigma DAC
Analog Post Filter
• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
• 120 dB Signal-to-Noise Ratio
The CS4328 is a complete stereo digital-Io-analog output system. In addition to the traditional D/A function,
the CS4328 includes an 8x digital interpolation filter followed by a 64x oversampled delta-sigma modulator.
The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample
rate between 1 kHz and 50 kHz while maintaining linear phase response simply by changing the master
clock frequency.
The CS4328 also includes an extremely flexible serial
port utilizing two select pins to support four different
interlace modes.
• Low Clock Jitter Sensitivity
• Completely Filtered Line-Level Outputs The master clock can be either 256 or 384 times the
input word rate, supporting various audio environLinear Phase Filtering
ments.
Zero Phase Error Between Channels
No External Components Needed
• Flexible Serial Interface for Either 16
or 18 bit Input Data
DIFO
DIF1
VD+
ORDERING INFORMATION:
CS4328-KP
0 to 70°C
28-pin Plastic
CS4328-KS
0 to 70°C
28-pin Plastic
-40 to +85 °c
28-pin Plastic
CS4328-BP
CS4328-BS
-40 to +85 °C
28-pin Plastic
CDB4328
CS4328 Evaluation Board
DGND
AGND1
VA-
LRCK
DIP
SOIC
DIP
SOIC
VA+
1----------,---'+0 -VREF
'----,---_ _ _ _..J
BICK
SDATAI
AOUTL
TST
RST
AOUTR
AGND2
AGND3
CALO
CMPI
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
XTI XTO CKS ACKO
ACKI
CALI
CMPO
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
OCT '93
DS62F3
2-31
-
--------.._-------"""
_. --ANALOG CHARACTERISTICS (TA = 25°C for K grade, TA=-4(}to +85 eCfor B grade; VA¥,VD+
= 5V; VA- = -5V; Logic "1" = VD+; Logic "0" = DGND;FullcSccile Output Sinewave. 991. Hz; Input Word Rate =
48 kHz; Input Data = 18 Bits; BICK = 3.072 MHz; RL = 10kQ; MeasurementB8ndwidth IS 10 Hz to 20 kHz, unweighted; unless otherwise specified.)
CS4328-K
Parameter"
Specified Temperature Range
Symbol
Min
TA
0
Resolution
Typ
CS4328-B
Max
Min
+70
. -40
Typ
Max
Units
+85
ec
-
16
-
-
Bits
-
-
120
-
-
dB
-
-
-93
-77
-37
-90
-73
-33
-
-88
-75
-35
-85
-70
-30
dB
dB
dB
-
±0.5
-
-
±0.5
-
deg
0
to
23.5
0
to
23.5
kHz
to
21.6
kHz
16
-
120
Dynamic Performance
Signal-to-Noise Ratio
(A-weighted)
(Note 1)
SNR
(A-Weighted) THD+N
Total Harmonic Distortion + Noise
o dB Output,
-20 dB Output,
-60 dB Output,
(Note 2)
Deviation From Linear Phase
Passband:
to -3 dB corner
(Notes 3, 4)
to 0.00025 dB comer
(Notes 3, 4)
0
to
21.6
0
-
-0.05
+0.1
+0.2
-0.05
-
0.00025
-
90
-
tgd
-
331IWR
-
-100
-110
-
-
-
0.1
VOUT
VA+
VA-
IA+
IA-
VD+
ID+
Frequency Response 10 Hz to 20 kHz
(Note 2)
Passband Ripple
(Note 4)
StopBand
(Note 3)
StopBand Attenuation
(Note 2)
Group Delay (IWR
=Input Word Rate)
Interchannel Isolation
-
(1 kHz)
26.4
'.
+0.1 .. ,+0.2.
dB
0.00025
dB
26.4
-
kHz.
-
-
90
-
-
331IWR
-
s
-95
-105
-
dB
-
-
0.1
-
dB
-
-
±5
%
-
ppm/oC
dB
dcAccuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Offset Error (after calibration)
-
±5
150
-
-
3.8
-
. 150
± 1
-
-
±1
mV
4.0
4.2
3.8
4.0
4.2
Vpp
40
-40
-
40
-40
50
55
-55
60
mA
mA
mA
650
850
mW
50
-
dB
Analog Output
Full Scale Output Voltage
Power Supplies
Power Supply Current:
-
Power Dissipation
Power Supply Rejection Ratio
Notes:
(1 kHz)
-
50
55
-55
60
650
850
50
-
1. Idle channel, digital input all zeros.
2. Combined digital and analog filter characteristics.
3. The passband and stopband edges scale with frequency. For input word rates, IWR, other than
48 kHz, the 0.00025 dB passband edge is 0.45x1WR and the stopband edge is 0.55xIWR ..
4. Digital filter characteristics.
* Definitions are at the end of this data sheet.
2-32
PSRR
-
Specifications are subject to change without notice.
DS62F3
----------------------
CS4328
DIGITAL CHARACTERISTICS
= 25°C; VA+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)
(TA
Parameter
Symbol
Min
High-Level Input Voltage
VIH
70%VD+
Low-Level Input Voltage
VIL
-
High-Level Output Voltage at 10 = -2OIlA
VOH
4.4
Low-Level Output Voltage at 10 = 20llA
VOL
-
Input Leakage Current
(Note 5)
lin
Typ
Max
Units
-
-
V
-
30%VD+
V
-
-
V
-
0.1
V
1.0
IlA
Note: 5. TST, DIFO & DIF1 have internal pull-down devices, nominally 90kn.
ABSOLUTE MAXIMUM RATINGS (AGND1-3,
DGND = OV, all voltages with respect to ground.)
Symbol
Min
Max
Units
Positive Digital
VD+
-0.3
6.0
V
Positive Analog
VA+
VA-
-0.3
6.0
-6.0
V
Parameter
DC Power Supplies:
Negative Analog
0.3
0.4
V
lin
±10
mA
VIND
-0.3
(VD+)+O.4
V
TA
-55
125
°C
Tstg
-65
150
°C
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
V
-
IVA+ - VD+I
WARNING: Operation at or beyond these limits may result in permanent damage to the device
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND1, AGND2, AGND3, DGND = OV; all voltages with respect to ground)
Parameter
DC Power Supplies:
Typ
Max
Units
5.0
5.25
V
VA+
4.75
5.25
V
VA-
-4.75
5.0
-5.0
-5.25
V
-
-
0.4
V
VD+
Positive Analog
Negative Analog
IVA+ - VD+I
DS62F3
Min
4.75
Symbol
Positive Digital
I
2-33
----------------------
CS4328
SWITCHING CHARACTERISTICS
(TA = 25°C; VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = OV, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
Min
XTIIXTO
10.7
7.1
Typ
Master Clock Frequency using Internal.Osciliator:
CKS=H
CKS=L
·
Master Clock Frequency using External Clock:
CKS=H
CKS=L
XTIIXTO
·
·
-
0.384
0.256
·
·
Max
Units
19.2
13.9
MHz
MHz
19.2
13.9
MHz
MHz
-
ns
ns
ns
·
·
21
SICK Pulse Width Low
tbickl
30
SICK Pulse Width High
tbickh
30
·
·
·
tbickw
80
-
·
·
·
·
·
·
·
·
·
·
·
·
XTIIXTO Pulse Width Low
XTIIXTO Pulse Width High
SICK Period
21
SICK '~sing to LRCK edge delay
(Note 6)
tblrd
35
SICK rising to LRCK edge setup time
(Note 6)
tblrs
35
SDATAI valid to SICK rising setup time
(Note 6)
tsbs
35
SICK rising to SDATAI hold time
(Note 6)
tbsh
35
LRCK
ns
ns
ns
ns
ns
2 periods of XTIIXTO
RST Minimum Pulse, Width Low
Note:
ns
6. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling."
I
I
LRCK
-------1r-----; Iblrs
Iblrd
l-..j
I
I
Ib' kl Ibickh
Iblrd
I~
BICK
V
I
-----'/r-----; Iblrs
l-..j
I
I
tb' kl Ibickh
I~
BICK
ISbs~lbSh
SDATAI
Serial Input Timing (Modes 0, 1, &3)
2-34
~~---,~
MSB
1'-M-S-B.-1-C
Serial Input Timing (Mode 2)
DS62F3
.-_
_
..--_._.
__.._-_
...-.
+5V Digital
CS4328
+5V
Analog
>---~~-----,
+
10 IlF I
+
I
0.1
l,.F...L...1..:.6_ _ _ _ _ _ _ _ _--'-_~_1_Il_F~ ~ 10 IlF
VD+
VA+
1 - - - 1 -_ _ _~2~0~ LRCK
Audio
Data
Processor
f--_ _ _---'.1.::..9~
18
L.---.----J------=~
SICK
NC
23
NC
15
5
-5V
Analog
0.1 IlF:&
SDATAI
optional crystal oscillator
- - - -I
7
1
VA-
~
10 IlF
VREF-r2~8~-_-_,
CS4328
D/A CONVERTER
0.1 IlF:&
2 510
XTO
AOUTL
f-=~V'v-~>----'
~ 10nF
V NPO
AOUTR f-'2=.:6~/\/\~~>----.
10 nF
V NPO
XTI
·510
;::i:
ACKO
ACKI
~~~~~====~~1l1JCKS
Mode
Select
13
f------=~
CMPO
CMPI
DIFO
L _ _ _J-----'1=2~ DIF1
9
f--------"-~
6
CALO
CALI
RST
TST DGND
AGND3
AGND2
AGND1
Figure 1. Typical Connection Diagram
DS62F3
2-35
--------------_._-----
CS4328
GENERAL DESCRIPTION
The CS4328 is a complete stereo digital-to-analog system designed for digital audio. The
system accepts data at standard audio frequencies, such as 48 kHz, 44.1 kHz, and 32 kHz; and
produces line-level outputs.
The architecture includes an 8x oversampling filter followed by a 64x oversampled one-bit
delta-sigma modulator. The output from the one
bit modulator controls the polarity of a reference
voltage which is then passed through an ultralinear analog low-pass filter. The result is
line-level outputs with no need for further filtering.
LRCK
(kHz)
CKS
XTIIXTO
(MHz)
ACKO
(MHz)
32
low
8.192
4.096
32
high
12.288
4.096
44.1
44.1
low
11.2896
5.6448
high
16.9344
5.6448
48
low
12.288
6.144
48
high
18.432
6.144
Table 1. Common Clock Frequencies
Very few external components are required to
support the DAC. Normal power supply decoupiing components and voltage reference bypass
capacitors are all that's required.
The remaining system clocks, LRCK and BICK,
must be synchronously derived from XTJJXTO.
If the CS4328 internal oscillator is used, the circuit must be configured and XTO buffered as
shown in Figure 1. XTJJXTO can be divided to
produce LRCK and BICK using a synchronous
counter such as 74HC590. Notice that the value
of the capacitor on XTO is 10 pF and the XTI
capacitor is 15 pF, which allows for 5 pF of gate
and stray capacitance.
System Clock Input
It is also possible to divide ACKO, 128x IWR,
SYSTEM DESIGN
The master clock (XTJJXTO) input to the DAC
is used to operate the digital interpolation filter
and the delta-sigma modulator. The master clock
can be either a crystal placed across the XTI and
XTO pins, or an external clock input to the XTI
pin with the XTO pin left floating.
The frequency of XTJJXTO is determined by the
desired Input Word Rate, IWR, and the setting of
the Clock Select pin, CKS. IWR is the frequency
at which words for each channel are input to the
DAC and is equal to LRCK frequency. Setting
CKS low selects an XTI/XTO frequency of
256x IWR while setting CKS high selects
384x IWR. The ACKO pin will always be
128x IWR and is used by the analog low-pass
smoothing filter. Table 1 illustrates various audio
word rates and corresponding frequencies used
in the DAC.
2-36
to derive BICK and LRCK. However, external
circuitry must be used to apply a "kick-start"
pulse to LRCK in.order to activate ACKO. The
sequence for the cancellation of RESET, beginning of calibration and activation of ACKO is
shown in Figure 2 with the required transitions
indicated by arrows. A momentary loss of
XTJJXTO or power will require a "kick-start"
pulse to resume operation.
Serial Data Interface .
Data is input to the CS4328 via three serial input
pins; SDATAl is the serial data input, BICK is
the serial data clock and LRCK defines the channel and delineation of data. The DAC supports
four serial data formats which are selected via
the digital input format pins DIFO and DIFl. The
different formats control the relationship of
LRCK to SDATAl and the edge of BICK used to
DS62F3
----------------------
CS4328
))
RST
~ons~
minimum
LRCK
"Kickstart"
«
I minimum ~l'--)_ _ _ _ _ __
----l
J
(
UlJlsL
XTIIXTO
2LnJ
4~'-"
ACKO
Figure 2. RESET Cancellation Timing
latch data. Table 2 lists the four formats, along
with the associated figure number. Format 0 is
compatible with existing 16-bit D/A converters
and digital filters. Format I is an 18-bit version
of format O. Format 2 is similar to Crystal ADCs
and many DSP serial ports. Format 3 is compatible with the I2S serial data protocol. Formats 2
and 3 support 18-bit input or 16-bit followed by
two zeros. In all four serial input modes, the serial data is MSB-first and 2's-complement
format.
Formats 0, 2 and 3 will operate with 16-bit data
and 16 BICK pulses as well. See Figure 6 for
16-bit timing. However, the use of
BICK = 64x IWR is recommended to minimize
the possibility of performance degradation resulting from BICK coupling into VREF-.
DIF1
DIFO
Mode
Figure
a
a
a
a
3
1
1
3
1
a
2
4
1
1
3
5
Table 2. Digital Input Formats
DS62F3
Reset and Offset Calibration
RST is an active low signal that resets the digital
filter and the delta-sigma modulator, synchronizes LRCK with internal control signals and
starts an offset calibration cycle upon exiting reset. When RST goes low, CALO goes high and
stays high until the end of an offset calibration
cycle. An offset calibration cycle takes 1024
IWR cycles to complete. CALO must be connected to CALI and CMPO must be connected
to CMPI for offset calibration. During an offset
calibration the analog output is forced to zero.
Power-Up Considerations
Upon initial application of power to the DAC,
offset calibration and digital filter registers will
be indeterminate. RST should be low during
power-up to activate an internal mute and prevent this erroneous information from being
output from the DAC. Bringing RST high will
begin a calibration cycle and initialize these registers.
Muting
There are two types of mutes that can be implemented with the CS4328. The first is a -50 dB
2-37
----------- ----------LRCK~<'
BICK
CS4328
rl
Right Channel
Left Channel
~------------~I
~1-''1JU
7
~~~~~I jlj oj II ; II J15j14jl*j11jlOj9jSj7jSj5j4j3j2jlj or; ; II J15j14j13j12jl1jlOj9jsj7jSj5j4j3j2j1j ov/;
~~~~~I jlj ojll ; ; J17jlSj15j14j13j12j11jlOj9jSj7jSj5j4j3j2jlj oV; ~17jlSj15j14j13j12HlOj9jsj7jSj5j4j3j2j1j or I;
Figure 3. Digital Input Formats 0 & 1
LRCK
~
BICK
lJ1JUUUUulrlruuuUUlJ~
Left Channel
I
~L
ri:: I
r
R~ig~h~t~C~ha~n~n~e~1- - - - - I u
______
III
~~
yfE1/
SDATAI
I I J15j14j13j12jllj10j9jSj7jSj5j413j2]1jOj
SDATAI
I I J17jlS]15j14j13j12HlOj9jSj7jS]5]4j3]2]1] 0VI:: :: I J17]16j15j14]13j12HlOj9jS]7jSj5j4j3j2jl] or : M
~
lSBil
lSBit
L4
J15j14j13]12HlOj9jSj7jSj5j4]3j2jljOj
Figure 4. Digital Input Format 2
-IL______~Le~f~tC~h~a~n~n~e~1- - - - - I
LRCK
Right Channel
BICK
SDATAI
~L-LL.:..L-'-'--'-LCL-'-'-L..L'-'------'--'--LJ--'--'---1--'----"-~--'-I ; I 1]15j14j13j12 H 10 j 9j sj 7j sj 5j 4] 3j 2jl ]0j
SDATAI
II I 1]17j16j15j14j13j12HlOj9jsj7]S]5j4j3j2]1]OV I;; Ilj17jlsj15j14j13j12j11jlOj9]sj7]sj5j4j3j2jlj or;
lS Bit
lS Bit
Z
Figure 5. Digital Input Format 3
LRCK
~
Left Channel
~____R~ig~ht_C~h_a~n_n~e~1_ _ _--1~
II-
SDATAI
-,-,--,----,--,-"-,-,--,--,,--,,-,---,-,--,,-,,-,---,--,-,,-,-,-,,-,---,,-,---,,,rI I-
l-
Mode 2
I-
BICK
SDATAI ,,--,----,-,--,,---,-,-,---,--,-,-,-,-----;-,-,-,-,----,----,---,-,--,,--.-,--,------;,--,-,-,--,------;,--,-.-1
Mode 0
•
SDATAI
,--,--,--,,-,--,,---,-,-,---,--,-,-,-,-----;-,-,-,-,----,----,---,-,--,,---,,--,------;-,--,-,-,-----;~---,i
Mode 3
IlII-
* LRCK must be inverted.
Figure 6. Digital Input Formats 0, 2 and 3 with 16 BICK Periods
2-38
DS62F3
----------------------
CS4328
CS4328
21
,-------------1CALO
CALI
Figure 7. -50dB Muting
mute which can be activated by forcing the
CALI pin high. Figure 7 shows how to implement a -50 dB mute using an OR gate. The
propagation of the gate will be the only delay in
moving the CS4328 to a muted state.
CS4328
MUTE
DATA
Figure 8. -120 dB Muting
The second mute option is a two stage operation
which involves forcing SDATAI to 0 using an
AND gate as shown in Figure 8. The first mute
occurs following 33 LRCK cycles when the 0
input data propagates to the output of the DAC.
The rms noise present at the output will typically
be 93 dB below fullscale. Following a total of
4096 LRCK cycles with 0 input data the output
of the CS4328 will mute and lower the output
rms noise to a minimum of 120 dB below
fullscale. Upon release of the MUTE command
and non-zero input data the CS4328 output mute
will immediately release. However, 33 LRCK
cycles are required for input data to propagate to
the output of the CS4328.
Grounding and Power Supply Decoupling
As with any high resolution converter, the
CS4328 requires careful attention to power supply and grounding arrangements to optimize
performance. Figure 1 shows the recommended
power arrangements with VA+ connected to a
clean +5 volt supply and VA- connected to a
DS62F3
clean -5 volt supply. VD+, which powers the
digital interpolation filter and delta-sigma modulator, may be powered from the system +5 volt
logic supply. Decoupling capacitors should be
located as near to the CS4328 as possible.
The printed circuit board layout should have
separate analog and digital regions with individual ground planes. The CS4328 should straddle
the ground plane break as shown on the
CDB4328 Evaluation board. Optional jumpers
for connecting these planes should be included
near the DAC, where power is brought on to the
board and near the regulators. All signals, especially clocks, should be kept away from the
VREF- pin to avoid unwanted coupling into the
CS4328. The VREF- decoupling capacitors, particularly the 0.1 !!p, must be positioned to
minimize the electrical path from VREF- to
Pin 1 AGND and to minimize the path between
VREF- and the capacitors. Extensive use of
ground plane fill on both the analog and digital
sections of the circuit board will yield large reductions in radiated noise effects. An application
note "Layout and Design Rules for Data Converters" is printed in the Application Note
section of this book.
Analog Output and Filtering
Full scale analog output for each channel is typically 4V peak-to-peak. The analog outputs can
drive load impedances as low as 6000 and are
short-circuit protected to 20mA.
The CS4328 analog filter is a 5th order
switched-capacitor filter followed by a secondorder
continuous-time
filter.
The
switched-capacitor filter is clock dependent and
will scale with the IWR frequency. The continuous-time filter is fixed and not related to IWR. A
low-pass filter consisting of a 510 resistor and a
.01 f..LF NPO capacitor is recommended on the
analog outputs.
2-39
-
---------------------Performance Plots
The following collection of CS4328 measurement plots (IWR = 48 kHz) were taken with an
Audio Precision Dual Domain System One. All
FFT plots are 16,384 point.
Figure 9 shows the frequency response with a
48 kHz input word rate. The response is very flat
out to half the input word rate.
Figure 10 shows the muted noise with all zeros
data into the CS4328. This plot is dominated by
the noise floor of the System One.
Figure 11 shows the unmuted noise. This data
was taken by feeding the CS4328 continuous zeros, but pulling CALI low. This unmutes the
output stage of the CS4328. This plot shows the
noise shaping characteristics of the delta-sigma
modulator combined with the analog filter.
Figure 12 shows the A-weighted THD+N vs signal amplitude for a dithered 1kHz input signal.
Notice that there is no increase in distortion as
the signal level decreases. This indicates very
good low-level linearity, one of the key benefits
of the delta-sigma technique.
Figure 13 shows the fade-to-noise linearity test
result using track 20 of the CBS CD-I. The input test signal is a dithered 500 Hz sine wave
which gradulllly fades from -60 dB level to -120
dB. During the fading, the output level from the
CS4328 is measured and compared to the ideal
level. Notice the very close tracking of the output level to the ideal, even at low level inputs of
-90 dB. The gradual shift of the plot away from
zero at signal levels < -100 dB is caused by the
background noise starting to dominate the measurement.
CS4328·
Figure 15 shows a 16K FFT plot result, with a
1 kHz -90 dB dithered input. Notice the complete lack of distortion components and tones.
Figure 16 shows a bandlimited, 10 Hz to
22 kHz, time domain plot of the CS4328 output
with a 1 kHz, -90 dB dithered input. Notice the
clear residual sine wave shape, in .the presence of
noise.
Figure 17 shows the monotonicity test result
plot. The input data to the CS4328 is +1 LSB,-1
LSB four times, then +2 LSB, -2 LSB four times
and so on, until +10 LSB, -10 LSB. This data
pattern is taken from track 21 of the CD-l test
disk. Notice the increasing staircase envelope,
with no decreasing elements. Notice also the
clear resolution of the LSB. For this test, one
LSB is a 16-bit LSB.
The following tests were done by filtering the
analog output of the CS4328 with the System
One analyzer 1 kHz notch filter to reduce the
peak signal level. The resulting signal was then
amplified and applied to the DSP module, avoiding distortion in the System One AID converter.
Figure 18 shows a 16K FFT Plot with a 1 kHz,
o dB input. Notice the low order harmonic distortion at < -100 dB.
Figure 19 shows a 16K FFT Plot with a 1 kHz,
-10 dB input. Notice the almost complete absence of distortion, with a small residual 2nd
harmonic at -110 dB.
Figure 14 shows the impulse response, taken
from the single positive full scale value on track
17 of the CD-l test disk. Notice the high degree
of symmetry, indicating good phase linearity.
2-40
DS62F3
----------- ----------CRYSTAL
2.0
FRQRSP48
CS4328
AMPL(dBr) vs GENFRQ(Hz)
Ap
CRYSTAL THDAM18A
-80
THD+N(dBr)
vs GENAMP(dBFS)
,
Ap
-82
1.5
-84
1.0
-86
0.5 .
-88
-90
0.0
-92
-0.5
-94
-1.0
f-...---~-'------:---'----c----~-----:-/
-96
-1.5
-98
-2.0
10
lk
100
10k
30k
-100
-100
Figure 9. Frequency Response (48 kHz word rate)
CRYSTAL NOISE
AMP1(dBr) & AMP1(dBr)
vs FREQ(kHz)
Ap
-90
-80
-70
-60
-50
-40
-30
-20
o
-10
Figure 12. THD+N vs 18-bit Input Signal Level
BANDPASS(dBr)
CRYSTAL TR20R
10
vs LEVEL(dBr)
Ap
-20
-40
-60
-80
-2
-100
-4
-120
-6
-140
-160
0.02
,.1
9.82
19.6
29.4
39.2
-8
v"').
49.0
58.8
68.6
78.4
88.2
98.0
-10
-120
Figure 10. Muted Idle Channel Noise
CRYSTAL NOISEUNM
0
AMP1(dBr)
vs
-110
-100
-90
-80
-70
-60
Figure 13. Fade-to-Noise Linearity
FREQ(kHz)
Ap
CRYSTAL
2.000
IMPULSE
AMP1(V)
vs TIME(usec)
Ap
-20
1.583
-40
1.167
- -
-60
-80
0.750
-100
0.333
-120
-0.083
-140
-160
0.02 9.82
19.6
29.4
39.2
49.0
58.8
68.6
78.4
Figure 11. Unmuted Idle Noise
DS62F3
88.2
98.0
-0.500
0.0
95.8
192
287
383
479
575
670
766
862
Figure 14. Impulse Response
2-41
---------------------CRYSTAL M90DBIK
CS4328
AMP1(dBr)
vs FREO(kHz)
CRYSTAL
O,----~~~--~~~~-~~~~____;;__,
, , "'"
MONOTON
AMP1(uV)
.\(8
TIME(ms!>Pl
600r-----~------~------~------~----~
Ap
640
-20
480
-40
.,. ,.,.,.,
·'·,·'-,1-,
.,. ,-,·,i,i,-
320
160
-60
o
-80
,
~,
_
- '_ '. '.' ! '
~I
_
_
'_
'.
'_ I
~
-160
-100
-320
-480
-120
-640
~oo
lk
10k
L..__~____~____--~------~------~~
o
20k
Figure 15. 1 kHz, ·90 dB Input FFT Plot
10
5
15
20
25
30
35
40
45
50
Figure 17. Monotonicity Test (16·bit data)
CRYSTAL M90TIME
AMP1(uV)
YS TIME(msec)
250 r-----------~------------~--------~,
CRYSTAL lkOdBFFT
AMP1(dBr)
vs
FREO(Hz)
Or-~~~--~~~~-~~~~____;~
Ap
, ' , ""
Ap
200
-,- ,-'-,T,T,·
-20
-40
-,-,-,.,
-,- ,·,-,i,i,"
-60
-,- ,-,.,
"
;,-
"
-60
-' - '-' -' '"
"
- I- ,- I-I',',
---
"
-100
-'- '-'-'
'-'-
• '. ' . ' . ' L'L'.
.'. '.'.'!'!.' .
-120
-200
-250
L..____
0.0
~
__________
0.50
1.00
~
____________
2.00
1.50
~
___
2.50
3.00
Figure 16. 1 kHz, -90 dB Input Time Domain Plot
CRYSTAL
Figure 18. 1 kHz, 0 dB Input FFT Plot
lKM10DB
AMP1(dBr)
vs FREO(Hz)
O,-_ _ _ _-_-_~-_-~~~~
, '
, ' "'"
Ap
, '
-20 -I-,·.·,r, . . , -,- ,-'·,'",r,·
,
-40
I
1', ""
.'.,.'., '.,'.,-
.,. ,-,-, 't,'·
I
'
,',','
I
'
"""
I
I , ' .',,
1'1 ""
-,- ,-'·,.,1,·
-60
-,.,.,., ;,,-,-
.,. ,·,·,',i,-
-80
. ' . '.'.' !.'!,.'-
-
-100
-120
,
-'- '- '-'
I _
I.
I.,
~
I
~
I
I
I
I
I I ,
~,
'_
'. '.'
~
I
I
,
_
I, '.'.'
. ' . ' . ' . ' L'L'_
-
, I I' ,',I
!.' _
"',"
_,_ I.'_.l.!.,.
10k
20k
Figure 19. 1 kHz, ·10 dB Input FFT Plot
2·42
DS62F3
.._-_
_.-_..--__
...-..
CS4328
r S;itched I
Audio
Data
I
Cap
i(:ontinuou51
Time
I
1--+1
L~F_I
L~e~1
Analog
Output
Analo Filter
Figure 20. CS4328 Architecture
THEORY OF OPERATION
The CS4328 architecture can be considered in
five blocks: Interpolation, sample/hold, deltasigma modulation, D/A conversion, and analog
filtering.
Audio data is input to the CS4328 digital interpolation filter which removes images of the
input signal that are present at multiples of the
input sample frequency, Fs (Figure 21). Following the interpolation stage, the resulting
frequency spectrum has images of the input signal at multiples of eight times the input sample
frequency, 8x Fs (Figure 22). Eliminating the
images between Fs and 8x Fs greatly relaxes the
requirements of the analog filtering, allowing the
suppression of images while leaving the audio
band of interest unaltered.
(dB)
ffiTIill
24 Fs
2Fs
f (kHz)
Figure 21. Input Data Spectrum
tiples. The sinxlx zeros completely attenuate
signals at 8x Fs and largely suppress the remaining energy of the images (Figure 23). The 8x
interpolation followed by the 8x sample-and-
(dB)
flL-"""----i...Ln-+-'----....I.Cr~~
16Fs
8Fs
24
Figure 23. Spectrum After SIB
f (kHz)
hold results in data at a rate of 64x Fs.
The delta-sigma modulator takes in the 64x Fs
data (3.072 MHz for 48kHz sampled systems)
and performs fifth-order noise shaping. In the
digital modulator of the CS4328, 18-bit audio
data is modulated to a I-bit, 64x Fs signal. The
5th-order noise shaper allows 1-bit quantization
to support 18-bit audio processing by suppressing quantization noise in the bandwidth of
(dB)
24
f(kHz)
Figure 24. Modulator Output Spectrum
8Fs
16Fs f (kHz)
Figure 22. 8X Interpolated Data Spectrum
interest. Figure 24 shows the frequency spectrum of the modulator output.
The CS4328 interpolation stage is followed by a
sample-and-hold function where the data points
from the interpolator are held for eight (64x Fs)
clock cycles. The resulting frequency response
is a sinxlx characteristic with zeros at 8x Fs mul.DS62F3
The CS4328's digital modulator is followed by a
D-to-A converter that translates the I-bit signal
into a series of charge packets. The magnitude
of the charge in each packet is determined by
sampling of a voltage reference onto a switched
2-43
----------------------
'CS4328:
capacitor, where the polarity of each packet is
controlle4 by the I-bit signal. The result is a
I-bit DIA conversion process' that is very insensitive to clock jitter. This is a major
improvement over previous generations of I ,Bit
D/A converters where the magnitude of charge in
the D/A process is, determined by switching a
current referenae for a period of time defined by
periods of the master clock.
The final stage of the CS4328 is made up of a
5th order switched-capacitor low pass filter and
a 2nd order continuous time fllter. The switchedcapacitor filter eliminates out-of-band energy resulting from the noise shaping process
(Figure 25). The switched-capacitor stage scales
with the master clock signal being applied to the
(dB)
1\
CS4328. The final stage is a 2nd order continuous time filter that eliminates high frequency
energy that appears at multiples of the 64x Fs
sample rate (Figure 26).
Figures 27-30 are computer simulations of the
combined response of the CS4328 digital and
analogfllters with an input word rate of 48 kHz.
Figure 27 shows the individual and combined
phase response of the CS4328 fllters. Notice the
digital fllter equalization of the analog fllter to
produce a linear phase response.
Figures 28-30 are plots of the CS4328 magnitude response.
,)
20,---------~----------~-------
~~.--~c:>r:J~~~~~1
24
\
64Fs' f (kHz)
Figure 25. Spectrum Mter Switched-Capacitor Filier
16- -' - - - - - - - - - - - - - - - - - - - - - - - - -
/
!.
.
:I
12- - - - - -- - - - -- - - - - -Analog-Fiite;' - / -
~
8 - - - - - - - - - - - -- - - - - - - - :.,; /- - - -
w.
,4 - - - - - - - - - - '- - - - - - - - ...---: - - - - - - _ ~ -Total Phase
-
:!:!. 0 -
- - - - - - - - - - - - - -
-4 - - - - - - - - - - - - - - - - --:- -~ -.......:: - - - - - -
a. -8 _ _ _ _ _ _ _ _ _ _ _ _' _ _ _ _ _ _ _ _ _ -_ "'-_ _ _ _
~
Digital Filter - "-12 - - - - - - - - - - - - - - - - - - - - - - - .- - - .-
(dB)D
-1,6,,~
I
f (kHz)'
24
Figure 26.
Spectru~ After
- - - - - - - - - - - - - - - - - - - - - - - - - -
-20 -'---'-__-'------'__--L-_ _
o
2
4
6
~~
_ _~~_ _~_
8
10 12 14
Frequency (kHz)
16
18
20
Continuous Time Filter
Figure 27. Deviation From Linear Phase
Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Before Building Your
For Our Free Review Service
Call Applications Engineering.
DS62F3
----------------------
CS4328
.
10
0
-10
10 -20
~ -30
CD
1J -40
:Ec: -50
-60
:2 -70
-80
-90
-100
-110
-120
-130
'"
'"
24
32
16
Input Frequency (kHz)
8
0
40
48
Figure 28. Combined Digital and Analog
Filter Frequency Response
0
-1
10
-2
CD
1J
-3
:g
-4
~
:::>
Cl
'"
:2
-5
-6
-7
-8
-9
-10
20
21
22
23
Input Frequency (kHz)
24
25
Figure 29. Combined Digital and Analog
Filter Frequency Response
0
-10
-20
10
-30
CD
1J
-40
~
.-2c:
-50
'"
-60
Cl
:2
-70
-80
-90
-100
-110
22
23
24
25
27
26
Input Frequency (kHz)
28
29
30
Figure 30. Combined Digital and Analog
Filter Transition Band
DS62F3
2-45
'
~i
----------------------
CS4328
PIN DESCRIPTIONS
ANALOG GROUND
ANALOG LEFT CHANNEL OUTPUT
ANALOG POWER
ANALOG GROUND
NEGATIVE ANALOG POWER
COMPARATOR OUTPUT
NO CONNECT
COMPARATOR INPUT
RESET
TEST
CLOCK SELECT
DIGITAL INPUT FORMAT 1
DIGITAL INPUT FORMAT 0
CRYSTAL OR CLOCK INPUT
AGND1
AOUTL
VA+
AGND2
VACMPO
NC
CMPI
RST
TST
CKS
DIF1
DIFO
XTI
VREF- VOLTAGE REFERENCE OUTPUT
CALI
CALIBRATION INPUT
AOUTR ANALOG RIGHT CHANNEL OUTPUT
AGND3 ANALOG GROUND
ANALOG CLOCK INPUT
ACKI
NC
NO CONNECT
ACKO ANALOG CLOCK OUTPUT
CALO CALIBRATION OUTPUT
LRCK LEFT/RIGHT CLOCK INPUT
BICK SERIAL BIT CLOCK INPUT
SDATAI SERIAL DATA INPUT
DGND DIGITAL GROUND
VD+
DIGITAL POWER
XTO . CRYSTAL OSCILLATOR OUTPUT
Power Supply Connections
VA+ - Positive Analog Power, PIN 3.
Positive analog supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 5.
Negative analog supply. Nominally -5 volts.
AGND1, AGND2, AGND3 - Analog Grounds, PINS 1, 4, 25.
Analog ground reference.
VD+ - Positive Digital Power, PIN 16.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, PIN 17.
Digital ground for the digital section.
Analog Outputs
VREF - - Voltage Reference Output, PIN 28.
Nominally -3.68 volts. Normally connected to a O.lJ.lF ceramic capacitor in parallel with a
1OJ.lF or larger electrolytic capacitor. Note the negative output polarity.
AOUTL - Analog Left Channel Output, PIN 2.
Analog output for the left channel. Typically 4V peak-to-peak for a full-scale input signal.
AOUTR - Analog Right Channel Output, PIN 26.
Analog output for the right channel. Typically 4V peak-to-peak for a full-scale input signal.
2-46
DS62F3
----------------------
CS4328
Digital Inputs
XTI· Crystal or Clock Input, PIN 14.
A crystal oscillator can be connected between this pin and XTO, or an external CMOS clock
can be input on XTI. The frequency must be either 256x or 384x the input word rate based on
the clock select pin, CKS.
ACKI· Analog Clock Input, PIN 24.
This is the master clock input for the analog section of the chip and must be 128x the input
word rate. ACKI is typically connected to the Analog Clock Ouput pin, ACKO.
CALI· Calibration Input, PIN 27.
Input to the analog section that is used during offset calibration. Normally connected to the
Calibration Output pin, CALO.
CMPI . Comparator Input, PIN 8
Input to the digital section that is used during offset calibration. Normally connected to the
Comparator Output pin, CMPO.
LRCK· LeftlRight Clock, PIN 20.
This input determines which channel is currently being input on the Serial Data Input pin,
SDATAI. The format of LRCK is controlled by DIFO and DIFl.
BICK· Serial Bit Input Clock, PINI9.
Clocks the individual bits of the serial data in from the SDATAI pin. The edge used to latch
SDATAI is controlled by DIFO and DIFl.
SDATAI . Serial Data Input, PIN 18.
Two's complement MSB-first serial data of either 16 or 18 bits is input on this pin. The data is
clocked into the CS4328 via the BICK clock and the channel is determined by the LRCK
clock. The format for the previous two clocks is determined by the Digital Input Format pins,
DIFO and DIFI
DIFO,DIFI . Digital Input Format, PINS 13, 12
These two pins select one of four formats for the incoming serial data stream. These pins set
the format of the BICK and LRCK clocks with respect to SDATAI. The formats are listed in
Table 2.
CKS . Clock Speed Select, PIN 11.
Selects the clock frequency input on the XTI pin. CKS low selects 256x the input word rate
(LRCK frequency) while CKS high selects 384x.
RST . Reset and Calibrate, PIN 9.
When reset is low the filters and modulators are held in reset. When reset goes high, an offset
calibration is initiated.
DS62F3
2·47
.._-_
_.-_..--_._.
__
...-.
CS4328
Digital Outputs
XTO • Crystal Oscillator Output, PIN 15.
When a crystal oscillator is used, it is tied between this pin and XTI. When an external clock is
input, this pin should be left floating.
ACKO· Analog Clock Output, PIN 22.
This output is 128x the input word rate (LRCK frequency). Normally connected to the Analog
Clock Input pin, ACKI.
CALO • Calibration Output, PIN 21.
Used during offset calibration. Must be connected to the Calibration Input pin, CALI.
CMPO • Comparator Output, PIN 6.
Used during offset calibration. Must be connected to the Comparator Input pin, CMPI.
Miscellaneous
NC • No Connection, PINS 7, 23.
These two pins are bonded out to test outputs. They must not be connected to any external
component or any length of PC trace.
TST •Test Input, PIN 10.
Allows access to the CS4328 test modes, which are reserved for factory use. Must be tied to
DGND.
2-48
DS62F3
--------~-------------
CS4328
PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise - The ratio of the rms value of the signal to the rms sum of all
other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including
distortion components. Expressed in decibels.
Signal-to-Noise Ratio - The ratio of the full scale rms value of the signal to the rms sum of all other
spectral components over the specified bandwidth with an input cif all zeros.
Frequency Response - A measure of the amplitude response variation from 10 Hz to 20 kHz relative
to the amplitude response at 1 kHz. Units In decibels.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with all zeros to the input under test and a full-scale
signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels.
Gain Error - The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift - The change in gain value with temperature. Units in ppm/°e.
Offset Error - The deviation of the mid-serue transition (111...111 to 000 ... 000) from the ideal
(AGND). Units in mY.·
DS62F3
2-49
_:
..........
.
...,""'...",-...
.
"'""'" ....,
Semiconductor Corporation
CS4328 Evaluation Board
Features
. General Description
• Demonstrates recommended layout
and grounding arrangements
• CS4328 Supports multiple input formats
The CDB4328 evaluation board allows fast evaluation
of the CS4328 18-bit, stereo D/A converter. The board
provides an analog output interface via' BNC connectors for both channels. Evaluation requires an analog
signal analyzer, a digital signal source, and a power
supply.
• CS8412 Receives AES/EBU, S/PDIF,
& EIAJ-340 Compatible Digital Audio
Also included is a CS8412 digital audio receiver I.C.,
which will accept AESIEBU, S/PDIF, and EIAJ-340
compatible audio data. The CS8412 can provide the
system timing necessary to operate the CS4328.
• Digital and Analog Patch Areas
The evaluation board may also be configured to accept
external timing signals for operation: in a: user application during system development.
• Operation with on-board CS8412 or
externally supplied system timing
ORDERING INFORMATION: CDB4328
Block Diagram
Digital Audio Input
Digital
Patch
Area
Error Infol
Channel
Status
-15V GND
GND
+5V
Analog
Patch
Area
CS8412
Digital
Audio
Receiver
6
+15V
Power Supply
Regulation and Conditioning
Timing
Signal
Selector
CS4328
AOUTR
DIA Converter
AOUTL
Offset
Calibration
Network
UR SCLK SDATA MCLK
AUG '93
DS62DB2
Crystal Semiconductor Corporation
P.O. Box 17847,Austin, TX 78760
2-50
(512) 445 7222 Fax: (512) 445 7581
_.-_..---._.
__.._-...-.
CDB4328
Power Supply Circuitry
Offset Calibration & Reset Circuitry
Figure 1 shows the evaluation board power supply circuitry. Power is supplied to the evaluation
board by five binding posts. The ±5 V analog
power supply inputs of the converter are derived
from ± 15 V using the voltage regulators U5 and
U6. The +5 V digital supply for the converter
and the discrete logic on the board is provided
by the +5 V and DGND binding posts. D1, D2,
and D3 are transient suppressors which also provide protection from incorrectly connected
power supply leads. C l-CB provide general
power supply filtering for the analog supplies.
As shown in Figure 2, C20-C24 provide localized decoupling for the converter VA+ and VApins. Note that C22 is connected between VAand VA+ and not VA- and AGND. The evaluation board uses both an analog and a digital
ground plane which are connected at J1. This
ground plane arrangement isolates the board's
digital logic from the analog circuitry.
Figure 1, shows the offset calibration circuit provided on the evaluation board. Upon power-up,
this circuit provides a pulse on the Digital to
Analog Converter's RST pin initiating an offset
calibration cycle. Pressing and releasing S2 also
initiates an offset calibration cycle.
Serial Data Interface
Figure I shows that there are two options for inputing serial data into the CS432B. Serial data
can be provided via the SDATA BNC connector
on the evaluation board. BNC connectors for
SCLK, the serial data input clock, and uR, the
clock that defines the channel and delineates the
data, are also provided on the evaluation board.
This information can also be provided by the onboard CSB412. JP3 selects the source of
SDATA, SCLK, and uR that will be provided to
the converter. JP3 selections are shown in Table 1.
US
+15V
1---.------
lot----11--_t------'--'-'19~BICK
U3, Pin 8 >-11----f-_~-'-'---L--'-'18~SDATAI
U3, Pin 11 >--11----j--+-_-'--'-14~XTI
ACKI VA+ AGND1 1
C22
U3, Pin 3
U3, Pin 6
U1
CS4328
UR SCLK SDATAMCLK
15 XTO
From
Reset
9 RST
Circuit
VD+
Figure 2. CS4328 DAC Connections
The CS4328 supports four serial data input formats. The selection of which is made via the
digital input format pins DIFO and DIFL The
different formats control the relationship of LiR
to SDATA and the edge of SCLK used to latch
the data. Consult the CS4328 data sheet for an
explanation of the different formats.
Position
Input Option Selected
EXTCLK
SDATA,SCLK, VR provided
by an external source.
8412
SDATA,SCLK, VR provided
by the CS8412
Table 1. JP3 Selectable Options
2-52
System Timing
The master clock input to the CS4328 can be
provided by several sources. JP3 selects the
source of the master clock that is to be supplied
to the XTI pin of the converter. When EXT
CLK is selected, the master clock is provided by
one of two sources. The 12.288 MHz clock signal provided by U8 can be used as the master
clock for both the CS4328 and the external system that provides the serial data to the board.
The other option is for a master clock that is
synchronized to the external serial data coming
into the board, be used as the master clock for
the CS4328 as well. However, if an external
DS62DB2
_.--..--__.._-_
...
._.-.
master clock is to be used, U8 must be removed
from it's socket to prevent the two clock signals
from interfering with one another. When 8412 is
selected by JP3, the master clock for the CS4328
is provided by the MCK output of the CS8412.
The CKS pin of the CS4328 can be pulled either
high or low via JP2. This determines whether
the master clock frequency has to be 384X or
256X the input word rate. Consult the CS4328
data sheet for the common master clock frequencies table.
Analog Outputs
The analog outputs are available at 2 BNC connectors labeled AOUTL and AOUTR. R5 and
C 18 remove the remaining very high frequency
components from the left channel output signal
while R6 and C19 do so for the right channel
output signal.
Digital Audio Standard Interface
Included on the evaluation board is a CS8412
Digital Audio Interface Receiver. This device
can receive and decode data according to the
AES/EBU, S/PDIF, and EIAJ-340 interface
standard. Figure 3 shows the schematic for the
CS8412. The input is coupled to the device
through a transformer that is included on the
board. The input to the device can be configured to accept either professional or consumer
input modes. Consult the CS8412 data sheet
for an explanation of the two input modes.
The LEDs, D4-D8, perform two functions.
When S 1 is in the Channel Status position, the
LEDs display the channel status information for
the channel selected by JPl. When SI is in the
Error Information position, the LEDs D4-D6,
display encoded error information that can be
decoded by consulting the CS8412 data sheet.
Encoded sample frequency information is displayed on LEDs D7-D9 provided a proper clock
is being applied to the FCK pin of JPl. When
an LED is lit, this indicates a "1" on the corre0862082
CDB4328
sponding pin located on the CS8412. When an
LED is off, this indicates a "0" on the corresponding pin. Neither the L or R option should
be selected if the FCK pin of JPl is being driven
by a clock signal.
Serial Output Interface
The SDATA, SCLK, LIR, and MCLK BNC
connectors can also be used to provide a serial
output interface for the CS8412. With JP3 in the
8412 position, the outputs from the CS8412 can
be brought off the board to an external evalution system. This data can be configured in one
of seven selectable formats. These formats are
outlined in the CS8412 data sheet.
CDB5336171819 Interface to CDB4328
Many users find it informative to evaluate a
combined ADC and DAC system connected together yielding analog input and analog output.
This can be accomplished by interconnecting a
CDB532617/8/9 or CDB533617/8/9 to a
CDB4328 evaluation board. The following information contains several techniques to
accomplish this goal. There are two general
points which need to be mentioned. An analog
input of ± 3.68 V will produce a full scale digital
output from the CS533617/8/9 and the
CS532617/8/9. A full scale digital input to the
CS4328' will produce a full scale output of ± 2 V
resulting in an overall loss of approximately
5.2 dB from input to output. Also it is recommended that the power connections for each
board are brought directly .from the power supply and not in a "daisy-chain" manner from
board to board.
Connecting the CDB4328 to the CDB5336n /8/9
can be accomplished using one of two methods:
2-53
R9
10n
o
U7
D,E,F
+5VAnalog
~
~
c
~
c
OJ
01:0
~-
CO
Figure 3. CS8412 Digital Audio Receiver Couuections
---------------------CDB4328 to CDB5336/71819 - Method 1
This method uses the AESIEBU Digital Audio
Interface which is supported by the CS8402
AES/EBU Transmitter and the CS8412
AESIEBU Receiver. The data and clock information is transmitted from the CDB5336n 18/9
to the CDB4328 via this interface.
CDB4328 Configuration for Method 1
The CS84I2 is configured to output data in Format 0 (MO ,M 1 ,M2 and M3 low) and the
CDB4328 must be set to receive data in the corresponding Format 2 (DIPI high and DIPO low).
Modify the jumpers located near pins 12 and 13
of the CS4328. Please note that Format 0 for
the CS8412 corresponds to the Format 2 for the
CS4328. JP2 sets the clock to sample frequency
ratio (CKS) on the CS4328 and is set low for a
ratio of 256.
JP3 selects the source of SDATA, SCLK and
LlR that will be provided to the converter and
should be in the 8412 position to allow the
CDB4328 to access the multiple clocks generated from the CS8412 and disable the oscillator
U8.
CDB5336/718!9 Configuration for Method 1
P4 selects an option to invert the SCLK for the
CS8402 and the parallel interface. The positions
of P4 are labeled and the jumpers should be in
the appropriate position for the ADC being
used. P7 should be set to "internal" to allow the
use of the master clock on the CDB5336n/8/9.
CMODE is set low for a master clock to sample
rate ratio of 256.
CDB5336/718!9 and CDB4328 Interconnection
for Method 1
Interconnection requires the power supply connections and a shielded twisted pair cable
connecting the digital outputs from the
DS62DB2
CDB4328
CDB5336n/8/9 to the digital inputs on the
CDB4328.
CDB4328 to CDB5336/718!9 - Method 2
Method 2 of interfacing the CDB5336n/8/9 and
the CDB4328 requires a direct interface through
the EXTCLKIN, SCLK, SDATA, and LIR BNC
connectors. This technique also requires minor
modifications to the CDB5336n/8/9.
CDB4328 Configuration for Method 2
The CS4328 is set to accept data in format 3
(DIFO and DIF1 high). JP2 sets the clock to
sample frequency ratio (CKS)· on the CS4328
(pin 11) is set low for a ratio of 256.
JP3 selects the source of SDATA, SCLK and
LIR that will be provided to the converter and
should be removed to access the multiple clocks
from the CDB5336n18/9 and disable the oscillator U8.
A left channel input will appear as a right channel output in this configuration. To correct this
the LIR clock must be inverted prior to the
CS4328 LIR input. This can be implemented by
modifying the CDB4328 as follows: Cut the
trace at the LlR BNC connecter on the
CDB4328. Cut the trace at V7 pin 9. Place a
jumper between V7 pin 9 and the LIR BNC.
Place a jumper between V7 pin 8 and VI pin 20.
CDB5336/718!9 Configuration for Method 2
The CS5336/7/8/9 data output contains 16 bits of
audio data as well as 3 tag bits and a left/right
indicator. These additional bits need to be removed before transmission to the CDB4328.
This can be done by making use of the FSYNC
pulse which frames the audio data bits. This has
been implemented on the CDB5336n18/9 and
can be utilized with a minor modification: cut
2-55
-
_.-_..--_._.
__.._-_
...-.
the trace at the SDATA BNC connector and
place a jumper between the SDATA BNC and
U8 pin 11. CMODE is set LOW for a master
clock of 256 times the sample rate. P7 must
have both the internal and external jumpers installed. This will route the master clock to the
EXTCLKIN BNC for connection to the
CDB4328 MCLK.
If a CS5336/8 is installed an additional modification is required to invert the SCLK prior to
transmission to the CDB4328. This can be implemented as follows: cut the trace at the SCLK
BNC and install a jumper between U7 pin 4 and
the SCLK BNC.
CDB5336/71819 and CDB4328 Interconnection
for Method 2
Shielded coaxial cables with BNC connectors
should be used to make the following connections: LIR to uR, SCLK to SCLK, SDATA to
SDATA, EXTCKINto MCLK.
CDB4328 Interfacing to the CDB5326171819
CDB4328
should be removed to acCess the multiple clocks
from the CDB5326/7/8/9. Remove the
12.288 MHz oscillator (U8).
CDB5326f718/9 Configuration
Remove the clock source- jumper (P2) .. Remove
the 6.144 MHz oscillator (U2) and replace with
the 12.288 MHz oscillator from the CDB4328.
Install a divide by 2 function on the
CDB532617/8/9 digital patch area. Use a
74HC74 with the D input connected to the Q
output. Connect the oscillator output to the
74HC74 clock input. Connect the Q output to
Ul pin 23.
Position P2 to connect the oscillator output to
the EXTCLKIN.
CDB5326f71819 and CDB4328 Interconnection
Shielded coaxial cables with BNC connectors
should be used to make the following connections: LlR to LlR, SCLK to SCLK, SDATA to
SDATA, EXTCLKIN to MCLK.
A method of interfacing the CDB5326n /8/9 and
the CDB4328 requires a direct interface through
the EXTCLKIN, SCLK, SDATA, and LIR BNC
connectors. This technique requires modifications to the CDB5326n /8/9 to derive the proper
clock frequencies. This is done by utilizing a
12.288 MHz clock and supplying a clock to the
CDB53261718/9 at 6.144 MHz.
CDB4328 Configuration
The CS4328 must be set to receive data in format 2 (DIPI high and DIPOlow). Modify the
jumpers located near pins 12 and 13 of the
CS4328. JP2 sets the clock to sample frequency
ratio (CKS) on the CS4328 and is set low for a
256 ratio.
JP3 selects the source of SDATA, SCLKand
LIR that will be provided to the converter and
2-56
DS62DB2
----------------------
CDB4328
Figure 4. Top Ground Plane Layer (NOT TO SCALE)
DS62DB2
2-57
CDB4328
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2-58
DS62DB2
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Semiconductor Corporation
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.._-_
.-_
_
..--_._.
__
...-.
CDB4328
-Notes-
2-60
DS62DB2
......
.............
.,,-- .,.
..,..,~.
CS4330
.~
Semiconductor Corporation
8 Pin Stereo DIA Converter for Digital Audio
General Description
Features
The CS4330 is a complete, stereo digital-to-analog output system in a small a pin package. It includes
interpolation, D/A conversion and output analog filtering. The CS4330 is based on delta-sigma modulation
where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample
rate between 1 kHz and 50 kHz while maintaining linear phase response simply by changing the master
clock frequency.
• Complete Stereo DAC System
Interpolation, DIA, Output Analog
Filtering
• 96 dB Dynamic Range
• 0.003% THD + N
• On-Chip Digital De-emphasis
• Low Clock Jitter Sensitivity
• Single +3 to +5V power Supplies
• Completely Filtered Line Level Outputs
Linear Phase Filtering
The CS4330 contains on-chip digital de-emphasis and
operates from a single +3V to +5V power supply, and
it consumes only 50 mW of power with a 3V power
supply. These features make it ideal for portable CD
players and other portable playback systems.
ORDERING INFORMATION
CS4330-KP
CS4330-KS
DEM
AGND
0 to 70°C
0 to 70°C
a-pin Plastic DIP
a-pin Plastic SOIC
VA+
LRCK
SDATAI
AOUTL
AOUTR
MCLK
Preliminary Product Information I This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this porduct without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS136PP1
2-61
-_ _-_
.. ...
.. -.-.
-. ..--_
__
• Notes.
2·62
_.-_..--_._
__.._-_
...-...
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-OIGITAL CONVERTERS
3
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
3-1
.- ........_.
....--_._
..........
. .....
ANALOG-TO-DIGITALCONVERTERS,
.
CS5326n1S19 and CS5336/8/9
Audio AID Converters
Delta-Sigma
CS5349 Single Supply, Stereo AID Converter
for Digital Audio.
This new class of device features 64X oversamc
pIing, using a Delta-Sigma architecture with resolutions of 16 or l8-bits. Output word rates can be
from 1 klli;, to 50 kHz. These stereo parts have 2
sample and holds, dual Delta-Sigma modulators,
two anti-aliasing and decimation ftlters, and a
voltage reference, all in· a 28-pin package. Performance measurements include 95 dB dynamic
range in stereo mode, up to 100 dB in mono
mode, along with 0.0015% THD.
The CS5349 is a complete, 16-bitanalog-to-digital
converter for stereo digital audio systems that require a single +5V supply. Similar to.the CS5339,
the CS5349 features 64X oversampling Delta
Sigma conversion with on-chip sample and hold,
filtering and voltage reference in a 28-pin package.
CS5345 Low Power AID Converter
The CS5389 is Crystal's newest audio AID converter irimed at the professional audio market.
Dual differential inputs, with special modulator
design, yield a dynamic range of 107 dB. Excellent noise rejection and low idle tones yield a superbly performing AID Converter.
CS53S9 & CS5390 Professional Audio Analog
to Digital Converters
The CS5345 is a single chip, 16-bit, stereo AID
converter requiring only lOOmW of power from a
single +5V supply. The part features two analog
delta-sigma modulators, two digital decimation fil- .
ters and a voltage reference in an SOlC package.
The CS5390 is pin compatible with the CS5389,
and offers increased dynamic range and 20-bit
output data words.
Audio AID Converter Comparison Table
Device
Number of Bits
Dynamic Range (dB)
CS5326 CS5327 CS5328 CS5329 CS5336 CS5338 CS5339 CS5349 CS5389
CS5390
16
16
18
18
16
16
16
16
18
20
95
95
100'
100'
95
95
95
90
107
110
-
-
-
-
./
./
./
./
-
-
Filter Passband (kHz)
0-22
0-20
0-22
0-20
0-20
0-22
0-22
0-22
0-22
0-22
Filter Transition Band (kHz)
22-26
20-24
22-26
20-24
20-26
22-28
22-28
22-28
22-28
22-28
Stop Band Attenuation (dB)
-86
-86
-89
-86
-80
-80
-80
-80
-80
-98
Overrange Tag Bits
-
-
-
-
./
./
./
./
Left/Right Tag Bits
-
-
-
-'
./
./
./
./
-
./
./
./
./
./
t
t
.!.
.!.
.!.
SOIC Package
Master Clocking Mode
-
-
-
-
t
t
t
t
Master Clock Frequency (XFs
128
128
128
128
Power Supply Voltages (V)
±5
±5
±5
±5
SCLK active edge
Operation < 30 kHz
without TEST Mode
Power Consumption mW
• In Mono Mode
3-2
'
256/384 256/384 256/384 256/384 2561384
±5
-
-
-
-
./
450
450
450
450
400
±5
./
400 '
±5
+5
±5
./
.!.
256/384
±5
./
./
./
./
400
325
550
550
All frequencies are with 'an output word rate of 48 kHz
_-_.
....._._.
_.-_..-__
...-
ANALOG-TO-DIGITAL CONVERTERS
CONTENTS
CS532617/8/9 16 & 18 Bit, Stereo AID Converters for Digital Audio
CDB532617/8/9 Evaluation Board for CS532617/8/9
CS5336/8/9 16 Bit, Stereo AID Converter for Digital Audio
CDB5336/8/9 Evaluation Board for CS5336/8/9 .
CS5345 Low Power, Stereo AID Converter for Digital Audio
CDB5345 Evaluation Board for CS5345 .
CS5349 Single Supply, Stereo AID Converter for Digital Audio
CDB5349 Evaluation Board for CS5349 .
CS5389 18 Bit, Stereo AID Converter for Digital Audio
CS5390 20 Bit, Stereo AID Converter for Digital Audio
CDB5389/90 Evaluation Board for the CS5389/90 .
3-5
3-24
3-39
3-60
3-73
3-90
3-101
3-122
3-135
3-155
3-173
3-3
.._-_
_
....,-__
...
.-_
....._...
ANALOG-TO-DIGITAL CONVERTERS
• Notes.
.... ...
. ....,-.....
~
CS5326
CS5328
~~"""
..,
..,
Semiconductor Corporation
~~
CS5327
CS5329
16 & 18-Bit, Stereo AID Converters for Digital Audio
Features
General Description
• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
The CS5326, CS5327, CS5328 & CS5329 are complete
analog-to-digital converters for stereo digital audio systems.
They perform sampling,
analog-to-digital
conversion and anti-aliasing filtering, generating 16 or
18-bit values for both left and right inputs in serial form.
The output word rate can be up to 50 kHz per channel.
• Adjustable System Sampling Rates
30 kHz to 50 kHz
• Low Noise and Distortion
95 dB dynamic range, 16-Bit
97 dB dynamic range, 18-Bit
100 dB dynamic range, 19-Bit Mono
0.0015% THD
• Internal 64X Oversampling
• Linear Phase Digital Anti-Alias Filtering
0.001 dB Passband Ripple
86dB Stopband Rejection
APD
The CS5326 & CS5327 are 16-bit ADCs, achieving
95 dB dynamic range. The CS5328 & CS5329 are 18-bit
ADCs with 97 dB dynamic range in stereo mode and
100 dB dynamic range in mono mode.
The CS5326 & CS5328 have digital filters which are
compatible with CD requirements. The CS5327 &
CS5329 have filters which guarantee no aliasing. The
filters have linear phase, 0.001 dB passband ripple, and
>86 dB stopband rejection.
The ADC's are housed in a 0.6" wide 28-pin plastic DIP.
• Low Power Dissipation: 450 mW
Power-Down Mode for Portable
Applications
ClKIN
The ADCs use delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
ORDERING INFORMATION:
ACAl AClKA
SClK
DClKA
Page 3-23
UR
VREF
SDATA
AINl
3-Stage
Digital Decimation
Filter
ZEROl
,11
TSTI
TST2
3-Stage
Digital Decimation
Filter
AINR
ZEROR
TS1"3
'8
AGND
,21
-
-
- - - - - - - - - -
VA+
5
VA-
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
-
NC
NC
- - - -
Vl+
lGND
DCAl DPD
VD1+ VD2+ DGND
MAR '92
DS35F1
3-5
________ c·
---------------
CS5326,CS5327,CS5328,CS5329
ANALOG CHARACTERISTICS (TA= 25°C; VA+, Vl+,VD1+,VD2+ = 5V; VA- = -5V; Full-Scale Input Sinewave, 4kH~; ClKIN = 6.144MH~; SClK = 3.072 MH~; Source Impedance =
with 10 nF to AGND;
Measurement Bandwidth is 10 H~ to 20 kHz; Digital Inputs: logic 1 = VD+, logic 0 = DGND; .
unless otherwise specified.)
son
Symbol
Parameter"
Resolution
min
SpeCification
typ
max
Units
CS5326, CS5327
CS5328, CS5329
16
18
CS5326, CS5327
CS5328, CS5329
CS5328, CS5329
92.7
94.7
95.7
97.1
100.1
dB
dB
dB
90.7
92.5
92.7
94.5
97
dB
dB
dB
0.003
0.0015
0.001
%
%
0.0001
Degrees
106
dB
Bits
Bits
Dynamic Performance
Dynamic Range
Mono
(Note 1)
Signal-to(Noise + Distortion)
Mono
(Note 1)
Total Harmonic Distortion
Vin= ± FS
Vin = -20dB
CS5326, CS5327
CS5328, CS5329
CS5328, CS5329
S/(N+D)
THD
Interchannel Phase Deviation
100
Interchannel Isolation (de to 20 kHz)
dcAccuracy
Interchannel Gain Mismatch
0.01
± 1
Gain Error
Gain Drift
Bipolar Offset Error
(After Calibration)
0.05
± 5
± 5
± 20
%
ppml° C
50
CS5326, CS5327
CS5328, CS5329
dB
± 15
± 60
LSB (16-bit)
LSB (18-bit)
Analog Input
Input Voltage Range
( ± Full Scale)
Input Impedance
± 3.68
Volts
ZIN
65
ko
VIN
± 3.50
Power Supplies
Power Supply Current
with APD,DPD low
(Normal Operation) ,
(VA+) + (VL+)
VA(VD1+) + (VD2+)
IA+
IAID+
25
25
40
35
35
55
rnA
rnA
rnA
Power Supply Current
with APD,DPD high
(Power-Down Mode)
(VA+) + (VL+)
VA(VD1+) + (VD2+)
IA+
IAID+
10
10
5
15
15
7
uA
uA
rnA
Power Consumption
(APD, DPD Low)
(APD, DPD High)
PDN
PDS
450
25
625
35
mW
mW
Power Supply Rejection Ratio (de to 26 kHz)
(26 kHz to 3.046 MHz)
Notes:
PSRR
54
dB
100
dB
1. Mono means connecting AINl & AINR together and adding together the output words from each channel.
* Refer to Parameter Definitions at the end of this data sheet.
Specifications are subject to change without notice.
3-6
DS35F1
.-_
._.-.
_
..--__.._-_
...
CS5326,CS5327,CS5328,CS5329
DIGITAL FILTER CHARACTERISTICS
(TA = 25 ° C; VA+, Vl+ ,VD1+,VD2+= 5V ± 5%; VA- = -5V
Parameter
Symbol
Passband
(-3 dB)
(-3 dB)
(-0.001 dB)
(-0.001 dB)
CS5326,
CS5327,
CS5326,
CS5327,
± 5%; ClKIN = 6.144MHz
Min
CS5328
CS5329
CS5328
CS5329
0
0
0
0
CS5326, CS5328
CS5327, CS5329
26
24
Typ
Passband Ripple
Stopband
(Note 2)
Stopband Attenuation
Units
23.5
21.6
21.8
20.0
kHz
kHz
kHz
kHz
0.001
dB
kHz
kHz
3046
3052
86
Group Delay
dB
4274/ClKIN
tgd
Group Delay Variation vs. Frequency
Notes:
Max
s
0.0
Ltgd
us
2. The analog modulator samples the input at 3.072MHz for a ClKIN of 6.144MHz. There IS no rejection
of input signals which are multiples of the sampling frequency (that is: there is no rejection for
n x 3.072MHz ±21.8kHz for the CS5326 & CS5328, or n x 3.072MHz ±20.0kHz for the
CS5327 & CS5329 ,where n = 0,1,2,3 ... ).
DIGITAL CHARACTERISTICS
(TA = 25°C; VA+, Vl+ ,VD1+,VD2+= 5V±5%; VA- = -5V±5%)
Parameter
Symbol
Min
(VD+) - 1.0
Typ
Max
Units
-
-
V
High-level Input Voltage (ClKIN)
VIH
low-level Input Voltage (ClKIN)
Vil
-
-
1.0
V
High-level Input Voltage (except ClKIN)
VIH
70%VD+
-
V
30% VD+
V
-
V
low-level Input Voltage (except ClKIN)
Vil
-
High-level Output Voltage at 10 = -20uA
VOH
4.4
low-level Output Voltage at 10 = 20uA
VOL
-
-
Input leakage Current
lin
-
1.0
0.1
V
-
uA
RECOMMENDED OPERATING CONDITIONS
(AGND, lGND , DGND =
av·, all voltages with respect to ground)
Parameter
DC Power Supplies:
Analog Input Voltage
Positive Digital
Positive logic
Positive Analog
Negative Analog
{Note 3)
Symbol
Min
Typ
Max
Units
VD1+,VD2+
Vl+
VA+
VA-
4.75
4.75
4.75
-4.75
5.0
5.0
5.0
-5.0
5.25
VA+
5.25
-5.25
V
V
V
V
3.68
V
6.4
MHz
f ClK 12
f ClK
Hz
f ClK 1128
f ClK 1128
Hz
VAIN
ClKIN Frequency
f ClK
SClK Frequency
f SClK
UR Frequency
Notes:
DS35F1
fUR
-3.68
3.84
3. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive
full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These
values are subject to the gain error tolerance specification.
3-7
_.--..--_._.
_-.._-_
...-.
CS5326,CS5327,CS5328,CS5329
SWITCHING CHARACTERISTICS
(TA = 25°C; VA+, Vl+, VD1+ , VD2+
CL =20pF)
= 5V ±5%;
Parameter
VA-
= -5V ± 5%;
Inputs: logic 0
= OV, logic 1 = VD+;
Symbol
Min
Typ
Max
Units
ClKIN Period
tclkw
155
ns
tclkl
50
ClKIN High
tclkh
50
-
ns
ClKIN Rising to AClKA edge (Note 4)
tclka
40
100
ns
AClKA Falling to UR Edge (Note 4)
taclr
-140
-
260
ClKIN low
140
ns
tclr
-10
-10
170
30
ns
-
ns
45
ns
ns
-
elKIN Rising to UR Edge
ns
(Note 4)
SClK Pulse Width low
tsclkl
60
SClK Pulse Width High
tsclkh
60
SClK Period
tsclkw
155
SClK Rising to SDATA Valid
tdss
-
-
tlrdss
-
-
50
ns
AClKA to ClKIN phase correct
AClKA to ClKIN phase unknown
-
UR edge to MSB Valid
ns
ns
SClK Rising to UR edge
tsclklr
-40
-
40
DPD, APD pulse width
tpd
150
-
-
ns
ClKIN Falling to APD Falling
tapdclk
-30
-
30
ns
Notes:
4. It is recommended th~t UR be generated by dividing AClKA by 64. If ClKIN is used to ge(1erate UR,
a longer ClKIN to UR delay may be tolerated if the phase of AClKA is determined through the use of
the APD pin. When high, the APD pin resets the divide-by-two circuit that generates AClKA from
ClKIN (that is, AClKA is reset to "0"). APD should be brought low on a falling edge of ClKIN.
This falling edge should be chosen such that UR edges nominally occur at AClKA falling edges.
ABSOLUTE MAXIMUM RATINGS (AGND, lGND,
Parameter
DC Power Supplies:
Symbol
Positive Analog
Negative Analog
Positive logic
Positive Digital
Input Current, Any Pin Except Supplies
Analog Input Voltage (AIN and ZERO pins)
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
DGND = OV, all voltages with respect to ground.)
VA+
VAVl+
VD1+,VD2+
I in
V1NA
Min
-0.3
Max
Units
+0.3
-0.3
+6.0
-6.0
(VA+)+0.3
V
V
-0.3
+6.0
(VA-)-0.3
± 10
V
V
mA
(VA+ )+0.3
V
V
'c
'c
V1ND
-0.3
(VD+) + 0.3
TA
-55
+125
Tstg
-65
+150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3·8
DS35F1
----------------------
CS5326,CS5327,CS5328,CS5329
SCU<
UR.
SOATA
Serial Data Timing
ClKlN
I--
t elr
-------------------~~--------
UR
Channel Selection Timing Using UR Derived From CLKlNI128
ClKIN
AClKA
OCLKA
__________________-.~.-~t~~lr______
LJR
__________~x~______
Channel Selection Timing Using UR Derived from ACLKAl64
APO,OPO
Power Down Timing
CLKlN
I
____________~-+_.t-ta~elk
APO
AClKA
\~--_ _-----11
ACLKA Phase Determination using APD
DS35F1
3-9
-_--_._.
___-_
. .. ......
....
··CS5326, CS5327, CS5328, CS5329
sample-and-hold amplifiers or a voltage reference.
GENERAL DESCRIPTION
The CS5326, CS5327, CS5328 and CS5329 are
16 & 18-bit, 2-channel NO converters designed
specifically for stereo digital audio applications.
The devices use two one-bit delta-sigma modulators which simultaneously sample the analog
input signals at a 64x sampling rate. A threestage digital filter then constructs pairs of 16-bit
or 18-bit values. This technique yields nearly
ideal conversion performance independent of input frequency and amplitude. The converters do
not require difficult-to-design or expensive antialias filters, and do not require external
,-----.__-""-j
VA+
VREF
An on-chip voltage reference provides for an input signal range of ± 3.68 volts. Any zero offset
can be internally calibrated out during a powerup self-calibration cycle. Output data is available
in serial form, coded as 2's complement 16 or
18-bit numbers. Typical power consumption of
only 450 mW can be further reduced by use of
the power-down mode.
For more information on delta-sigma modulation
and the particular implementation inside these
VL+
VD1+
VD2+
APD
DPD
ACAL
DCAL
>--I
r-- Filter Deli'! Time
x UR clocks)
(85.33 ms
@
48kHz)
(-100 UR periods)
(-2 ms @ 48 kHzf
.----_ _ _ 1
DPD
DCAl
~\L:____________-+_________N_or_ma_l~op~e~.m_tio__
n
~
Figure 3. lnitiaiCalibration Cycle Timing
3-12
DS35F1
---------------------During the offset calibration cycle, the digital
section of the part measures and stores the value
of the calibration input of each channel in registers. The calibration input value is subtracted
from all future outputs. The calibration input may
be obtained from either the analog input pins
(AINL and AINR) or the zero pins (ZEROL and
ZEROR) depending on the state of the ACAL
pin. With ACAL low, the analog input pin voltages are measured, and with ACAL high, the zero
pin voltages are measured.
As shown in Figure 3, the DCAL outpu0s high
during calibration, which takes 4096 UR clock
cycles. If DCAL is connected to the ACAL input,
the calibration routine will measure the voltage
on ZEROR and ZEROL. These should be connected directly to ground or through a network
matched to that present on the analog input pins.
Internal offsets of each channel will thus be
measured. and subsequently subtracted.
Alternatively, ACAL may be permanently connected low and DCAL utilized to ground the
user's front end. In this case, the calibration routine will measure and store not only the internal
offsets but also any offsets present on the front
end.
During calibration, the digital output of both
channels is forced to a 2's complement zero. Subtraction of the calibration input from conversions
after calibration substantially reduces any
power-on click that might otherwise be experienced. A short delay of approximately 100 output
words will occur following calibration for the
digital filter to begin accurately tracking audio
band signals. The transition is simply the natural
filter response and is, of course, graceful.
Power-up Considerations
Upon initial application of power to the supply
pins, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
DS35F1
CS5326,CS5327,CS5328,CS5329
potentially large values of data in these registers
with the correct values.
The modulators settle very quickly (a matter of
microseconds) after the analog section is powered
on, either through the application of power, or by
exiting the power-down mode. The voltage reference, however, can take a much longer time to
reach a final value due to the presence of large
external capacitance on the VREF pin; allow approximately 5 ms/J.lF. The calibration period is
long enough to allow the reference to settle for
capacitor values of up to 10 J.lF. If a larger capacitor is used, additional time between APD
going low and DPD going low should be allowed
for VREF settling before a calibration cycle is initiated.
Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows powering
the part from single ± 5 volt supplies. Analog
ground and digital ground should be connected
together near to where the supplies are brought
onto the printed circuit board. Decoupling capacitors should be as near to the ADC as possible,
with the low value ceramic capacitor being the
nearest. The VREF decoupling capacitors, particularly the 0.1 J.lF, must be positioned to
minimize the electrical path from VREF to Pin 1
AGND and to minimize the path between VREF
and the capacitors.
The printed circuit board layout should have
separate analog and digital regions and ground
planes, with the ADC straddling the boundary.
An evaluation board is available which demonstrates the optimum layout and power supply
arrangements, as well as allowing fast evaluation
of the A DC.
To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
3-13
.._-_
.-_
.._.-.
_
..--_
__
....
CS5326, CS5327, CS532SiCS5329
performed on the output data. The resulting spectrum is a measure of the 'performance of the
ADC.
.
Multiple ADC's
In systems where multiple ADC's are used, cafe
must be taken to ensure that the ACLKA phases
are synchronized if simultaneous sampling is desired. In the absence of this synchronization, the
sam~ling. difference could be one CLKIN cycle
(typIcally 162 ns). If this difference is unacceptable, the. parts may be synchronized to within
several. nanoseconds by using the circuit shown
in Figure 4. This circuit ensures that when the
ADC's come out of power-down mode, ACtKA
will have the same phase between all ADC's. The
APD signal is used to reset the internal divideby-t~o flip~flopwhich generates ACLKA. The
circuit also ensures that uR and SCLK occur at
the correct time.
Figure 5 shows the spectral. purity of the CS5326
with a 1 kHz, -10 dB input. Notice the low noise
floor, the absence of any harmonic distortion,'and
the Dynamic Range value of 94.63 dB.
Figure 6 shows .the CS5326 high frequency performance. The input signal is a -10 dB, 9 kHz
sine wave. Notice the small 2nd harmonic at 112 dB.
Figure 7 shows the low-level performance of the
CS5326. Notice the lack of any distortion. components. Traditional R-2R ladder based ADC's
can have problems with this test, since differential non-linearities around the zero point become
very significant. Figure 8 shows the same very
low input amplitude performance, but at.9kHz input frequency.
PERFORMANCE
FFT Tests
For FFT based tests, a very pure sine wave is
presented to the ADC, and an FFT analysis is
U4
CCK
QA
6.144 MHz
CLK
CS5326171819
74HC04
+2
15
+128
14
SCLK
sbATA
16
74HC590A
R~QG
UR
CCLR
10
23
APD
ACLKA
DPD
DCLKA
ClKIN
U1
CLKIN
CS5326171819
U3
0
U3
Q
74HC74
0
Q
74HC74
POWER DOWN
TO OTHER
CS5326's
··
Figure 4. Connections filr Synchronization of Multiple CS5326nis/9 ADC's.
3-14
DS35F1
----------------------
CS5326,CS5327,CS5328,CS5329
Figure 9 shows the CS5327 FFf plot with an input signal of 1 kHz at -10 dB. This is very
similar to the CS5326 plot, but notice the reduction in the noise floor between 22 kHz and
24 kHz. This is caused by the digital filter attenuating the noise in its transition band.
Figure 10 shows a plot of Signal to (Noise + Distortion) versus input amplitude relative to full
o,---------------~--~~~--~~-.
.10
-10
-20
~~!~~~I:e~L~6~~-P
·20
-30
-40
Signal
-50
Amplitude -60
Relative to -70
Full Scale -80
(dB)
-90
Signal
Amplitude
Relative to
Full Scale
(dB)
-50
-60
-70
-80
-90
-too
- - -
~10
lllli-.IiIIIi
• • • • • • •-_''•' .....,...
'
4
8
12
16
Input Frequency (kHz)
de
20
-1 ~ -,---------o""u-=tp"'u.,-;tW~o::c::rd:;-;R"'a::::te~:4o;;8cck'"'"Hz'--'
-20
Full Scale: 7.3 V pop
s/(N+D): 15.95 dB
-30
DynamiC Range: 95.95 dB
-40
(de to 20 kHz)
Signal
-50
Amplitude -60
Relative to -70
Full Scale -80
(dB)
-90
-100
-110
1II1i11••IIII.lIIIiIIII.IIIIIIII• •iiI.'*II'''~
-120
-130-,1
de
4
8
12
16
Input Frequency (kHz)
20
24
Figure 7. CS5326 FFT Plot with -80 dB, 1 kHz Input
-1 ~ -,-------------,O=-u.,-tp-ut:7W
""o-rd""R=-a-c
te-:48-=-:k""HC"z-----'
Full Scale: 7.3 V pop
s/(N+D): 84.78 dB
-30
DynamiC Range: 94.78 dB
-40
(de to 20 kHz)
Signal
-50
Amplitude -60
Relative to -70
Full Scale -80
(dB)
-90
-20
.,
~1III• • •~"• •~iI Il.-• •'-.
-120
-t30-l"
de
24
Figure 5. CS5326 FFT Plot with -10 dB, 1 kHz Input
4
8
t2
16
Input Frequency (kHz)
20
24
Figure 6. CS5326 FFT Plot with -10 dB, 9 kHz Input
0.------------------,
_to
-20
Signal
Amplitude
Relative to
Full Scale
(dB)
Output Word Rate: 48 kHz
Full Scale: 7.3 V pop
s/(N+D): 15.35 dB
Dynamic Range: 95.35 dB
(de to 20 kHz)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120 ....... L.ri,-"
-130
4
de
8
12
16
Input Frequency (kHz)
20
24
Figure 8. CS5326 FFT Plot with -80 dB, 9 kHz Input
iii'
100,----.----~----r_--_.--____,
:g.
+ 1 kHz
" 80
.~
.~
o
,10kHz
,20kHz
60
+
ill
·0
~
40
.9 20
-100
-110
-120
-130
~
.2'
.J.. -
de
w
4
8
12
16
Input Frequency (kHz)
Figure 9. CS5327 FFT Plot with
DS35F1
Output Word Rate: 48 kHz
Full Scale: 7.3 V pop
s/(N+D): 85.07 dB
Dynamic Range: 95.07 dB
(de to 20 kHz)
!~
Dynamic Range: 94.96 dB
(de to 20 kHz)
-100
-110
-120
-130
o-,----------------~~~--:-~~~~-.
Oulpul Word Rate: 48 kHz
~10
20
~.t0~~~--~c---~----~--~
24
dB, 1 kHz Input
Input Signal Level (dB)
Figure 10. CS5326, CS5327 Signal to Noise+Distortion
Ratio vs. Input Level
3-15
----------------------
CS5326, CS5327, CS5328, CS5329
o.---------~~~~~~--~~~
o.---------~--~--~~--~~_;
-10
-20
_ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _
30°
--4
Output Word Rate: 48 kHz
Full Scale: 7.3 V p-p
s/(N+D}: 87.00 dB
- - - - - - - -
Dynamic Range: 97.00 dB
- - - - - - - -
-30
-60
-70
-80
-90
(dB)
-100
-110
-120
-130
... -
- -
-
- - - - -
.... - -
-- --
8
12
16
Input Frequency (kHz)
de
- -
.......
20
Signal
Amplttude
Relative to
Full Scale
-50
(dB)
-90
_ _ _ _ _ _ _ _ _ _ Output Word Rate: 48 kHz
_ _ _ _ _ _ _ _ _ Full Scale: 7.3 V pop
s/(N+D}: 90.08 dB
- - - - - - - - -
-40
- - - - - - - - -
:~~~.l.t~.~-~-IIiI-"-II-_"-IIIi-Ii-"-~-lii-.-.-lllil-li-"-"-~-..=.jde
B
4
20
12
16
Input Frequency (kHz) '.
24
Figure 12. CS5329 FFT Plot with ·10 dB, 1 kHz Input
100 ; - - - - - - - - - - - - - - - - - - - - - - - ,
:E.
I
(de to 20 kHz}
(dcto20kHz)
-100
-110
iii"
Dynamic Range: 100.08 dB
Dynamic Range: 97.09 .dB
-80
O.-------------~~~~~~~,
-30
- - - - - - -
- - - - - - - - -
-60
-70
24
Figure 11. CS5328 FFT Plot with ·10 dB, 1 kHz Input
-10
-20
_ _ _ _ _ _ _ _ _ _ Output Word Rate: 48 kHz
_________ Full Scale: 7.3 V p-p
s/(N+D): 87.09 dB
-40
(de to 20 kHz}
-50
Signal
Amplitude
Relative to
Full Scale
-10
-20
Signal
Amplitude
Relativeto
Full Scale
-50
-60
(dB)
-90
;;;
-100
-110
-120
-130
9
.~
eo
'-.------1- - - - - - - - --
60
c
-70
+
!R 40
-80
'0
.to - - - - - - - - - - - - - - - - - -............
de
.\
8
12
16
Input Frequency (kHz)
20
I
20
24
-
- -
I
-
,
I
I
- - - - - - - - - - - -
-
O+---;----r--~----~~
-40
·20
·100
-so
-so
Input Signal Level (dB)
Figure 13. CS5328 in Mono Mode FFT Plot with
·10 dB, 1 kHz Input
Figure 14. CS5328 Signal to Noise+Distortion Ratio vs.
Input Level
scale. For an ideal ADC, this plot would be a
straight line at 45° for all input frequencies between dc and half the output word rate. The
measured data from a CS5326 shows both the
excellent high frequency performance as well as
the maintenance of good performance with low
input levels.
Figure 13 shows the CS5328 operated in 19-bit
mono mode, with the two inputs joined together,
and the output words added. Notice the 3 dB improvement over Figure 11.
Figure 11 shows theI8-bit CS5328 FFf plot. Notice the 2 dB improvement in dynamic range over
the CS5326.
Figure 12 shows thel8-bit CS5329 FFf plot. Notice the filter cut-off at 22 kHz, and the 2 dB
improvement in dynamic range over the CS5327.
3·16
Figure 14 shows a plot of Signal to Noise + Distortion versus Input Level for the 18-bit CS5328.
Notice the improvement in values over Figure 10.
DNLTests
A Differential Non-Linearity test is also shown.
Here, the converter is presented with a linear
ramp signal. The resulting output codes are
counted to yield a number which is proportional
to the codewidth. A plot of codewidth versus
code graphically illustrates the uniformity of the
DS35F1
._.-.
_.-_....____.._-_
...
CS5326, CS5327, CS5328, CS5329
+1
+1/2
iD
en
d.
....J
Z
Cl -112
-1
65,535
32,768
Codes
Figure 15. CS5326 Differential Non-Linearity Plot
codewidths. Figure 15 shows the excellent Differential Non-Linearity of the CS5326. This plot
displays the worst case positive and negative errors in each of 512 groups of 128 codes.
Codewidths typically are within ± 0.2 LSB's of
ideal. A delta-sigma modulator based ADC has
no inherent mechanism for generating DNL errors. The residual small deviations shown in
Figure 10 are a result of noise. Nevertheiess, the
performance shown is extremely good, and is superior to typical R-2R ladder based designs.
Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Digital Filter
Figures 16 through 21 show the performance of
the digital filter included in the ADC. All the
plots assume an output word rate of 48 kHz, with
a CLKIN frequency of 6,144 MHz. The filter frequency response will scale precisely with
changes in CLKIN frequency. The passband ripple is flat to ± 0.001 dB maximum. Stopband
rejection is greater than 86 dB.
Figures 16,18 &20 show the CS5326 and
CS5328 filter characteristics. Figure 20 is an expanded view of the transition band.
Figures 17,19 & 21 show the CS5327 and
CS5329 filter characteristics. Figure 21 is an expanded view of the transition band. Notice how
the filter enters the stopband at exactly 24 kHz,
which is half the output word rate, thereby guaranteeing no aliasing.
DS35F1
3-17
.._-_.
_.--..--_._.
_...-
CS5326, CS5327, CS5328, CS5329
10,---~----~--~--~----~--~
10,---~----~--,_--~----~--~
o +---__----~"""
0+---__----__- - ,
-10
-10
-20
-20
iii'
-30
:!:!. -40
iii'
.gJ ;50
~ -60
.gJ -50
.~ -60
g> -70
::;; -80
-90
-100
-110
g> -70
::;; -80
-90
-100
-110
-120
-130
-120
-130
-30
t-----;I;------;I;~___;;t;_--_;j;;_--'-'___;I;:~____;I...
;
-40
:!:!.
-
"-,-
-,-
t----j;------;t:;----;:;jf---;:;I;:;----~-'---',l..
Input Frequency (kHz)
Input Frequency (kHz)
Figure 16. CS5326 /8 Digital Filter Stopband Rejection
Figure 17. CS532719 Digital Filter Stopband Rejection
0.0010 ,---~----~--~--~----~--~
0.0010 ,------.----,.----,_-----,----,----,
iii'
iii'
0.0005
0.0005
:!:!.
:!:!.
~
"E
.gJ
.-E 0.0000
c:
g>
0.0000
g>
::;;
::;;
-0.0005
-0.0005
-0.0010 t----t------,t----:;t"----;1;;----;;I;c--'---;d
-0.0010 -j;----t------,t----;t,-----:;I;,------,±----;;j
Input Frequency (kHz)
Input Frequency (kHz)
Figure 18. CS5326!8 Digital Filter Passband Ripple
Figure 19. CS532719 Digital Filter Passband Ripple
o,---__~~--.-----.------.----,
~
-10
-20
-20
g>
::;;
-,- -
-;-
-,-
,-
:!:!.
Q)
'C
:J
-40
~ -50
g> -60
-50
-60
~
::;;
-70
-70
-80
-80
-90
-90
-1 00 ±---~±_----=:t;_-----=I=_~__;;l="'---'----;;I..
Input Frequency (kHz)
Figure 20. CS532618 Digital Filter Transition Band
3-18
:
iii' -30
-30
~ -40
'E
0
-10
-100
Input Frequency (kHz)
Figure 21. CS532719 Digital Filter Transition Band
DS35F1
.-_
_
..--_._.
__.._-_
...-.
CS5326,CS5327,CS5328,CS5329
PIN DESCRIPTIONS
ANALOG GROUND AGND
LEFT CHANNEL ANALOG INPUT
AINl
LEFT CHANNEL ZERO INPUT ZEROl
POSITIVE ANALOG POWER
VA+
NEGATIVE ANALOG POWER
VAANALOG POWER DOWN INPUT
APD
ANALOG CALIBRATE INPUT ACAl
NO CONNECT
NC
DIGITAL CALIBRATE OUTPUT DCAl
DIGITAL POWER DOWN INPUT
DPD
TEST TST1
TEST TST2
TEST TST3
LEFT/RIGHT SELECT INPUT
LlR
VREF
AINR
ZEROR
Vl+
lGND
ClKIN
AClKA
NC
DClKA
DGND
VD2+
VD1+
SDATA
SClK
VOLTAGE REFERENCE OUTPUT
RIGHT CHANNEL ANALOG INPUT
RIGHT CHANNEL ZERO INPUT
ANALOG SECTION LOGIC POWER
ANALOG SECTION LOGIC GROUND
MASTER CLOCK INPUT
ANALOG SECTION CLOCK OUTPUT
NO CONNECT
DIGITAL SECTION CLOCK INPUT
DIGITAL GROUND
DIGITAL SECTION POSITIVE POWER
DIGITAL SECTION POSITIVE POWER
SERIAL DATA OUTPUT
SERIAL DATA CLOCK INPUT
Power Supply Connections
VA+ - Positive Analog Power, PIN 4.
Positive analog supply. Nominally +5 volts.
VL+ - Positive Logic Power, PIN 25.
Positive logic supply for the analog section. Nominally +5 volts.
VA- - Negative Analog Power, PIN 5.
Negative analog supply. Nominally -5 volts.
AGND - Analog Ground, PIN 1.
Analog ground reference.
LGND - Logic Ground, PIN 24
Ground for the logic portions of the analog section.
VDl+, VD2+ - Positive Digital Power, PINS 17, 18.
Positive supply for the digital section. Nominally +5 volts.
DGND - DigitalGround, PIN 19.
Digital ground for the digital section.
Analog Inputs
AINL, AINR - Left and Right Channel Analog Inputs, PINS 2, 27
Analog input connections for the left and right input channels. Nominally ±3.68 volts full scale.
DS35F1
3-19
--
----------- ..----------
CS5326,CS5327,CS5328,CS5329
ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26.
Analog zero level inputs for the left and right channels. The levels present on these pins can be
used as zero during the offset calibration cycle. Normally connected to AGND, optionally through
networks matched to the analog input networks ..
Analog Outputs
VREF - Voltage Reference Output, PIN 28.
Nominally "3.68 volts. Normally connected to a O.lJlF ceramic capacitor in parallel with a lOJlF
or larger electrolytic capacitor. Note the negative output polarity.
Digital Inputs
CLKIN - Master Input Clock, PIN 23.
This clock is internally divided by 2 to set the modulators sample rate. Sampling rates, output
rates, and digital filter characteristics scale to CLKIN frequency. CLKIN frequency of 6.144 MHz
corresponds to an output word rate of 48 kHz per channel.
DCLKA - Digital Section Input Clock, PIN 20.
This clock is used to clock the modulator output data into the· digital section. Must be connected
to ACLKA.
SCLK - Serial Output Data Clock, PIN 15.
Data bits are output on the rising edge of SCLK.
LIR - LeftlRight Select, PIN 14.
Select the left or right channel for output on SDATA. !!Ie rising edge of UR starts th~ MSB of
the left channel data. Thereafter, CLKIN, SCLK and UR should run synchronously. UR must be
equal to CLKIN/118. Although the outputs of each channel are transmitted at different times, the
two words in a UR cycle represent simultaneously sampled analog inputs.
APD - Analog Power Down, PIN 6.
Analog section power-down command. When high the analog circuitry is in power-down mode. It
also causes the analog section to reset the clock output (ACLKA). APD is normally connected to
DPD when using the power down feature.
DPD - Digital Power Down, PIN 10
Digital section power-down command. Bringing DPD high puts the digital section into
power-down mode. Upon returning low, the ADC starts an offset calibration cycle. This takes
4096 uR periods (85.33 ms with a 6.144 MHz clock). DCAL is high during the calibrate cycle
and goes low upon completion. DPD is normally connected to APD. A calibration cycle should
always be initiated after applying power to the supply pins.
3-20
DS35F1
----------- -----------
CS5326,CS5327,CS5328,CS5329
ACAL - Analog Calibrate, PIN 7.
Analog section calibration command. When high, causes the left and right channel modulator
inputs to be internally connected to ZEROL and ZEROR inputs respectively. May be connected to
DCAL.
Digital Outputs
ACLKA - Analog Section Output Clock, PIN 22.
This clock is CLKIN/2. It is used by the digital section to clock in the modulator output data.
ACLKA must be connected to DCLKA. The phase of ACLKA may be reset by using APD.
SDATA - Serial Data Output, PIN 16.
Data bits are presented MSB first, in 2's complement format.
DCAL - Digital Calibrate Output, PIN 9.
This pin ris~ immediately upon entering the power-down state (DPD brought high). It returns
low 4096 LIR periods after leaving the power down state (DPD brought low), indicating the end
of the offset calibration cycle (which = 85.33 ms with a 6.144 MHz CLKIN). May be connected
to ACAL.
(See Figure 3)
Miscellaneous
NC - No Connection, PINS 8,21.
These two pins are bonded out to test outputs. They must not be connected to any external
component or any length of PC trace.
TSTl, TST2, TST3 -Test Inputs, PINS 11, 12, 13.
Allows access to the ADC test modes, which are reserved for factory use. Must be tied to DGND.
DS35F1
3-21
......
_-_
-.-_..--__
...-..
CS5326, CS5327, CS5328, C$5329
PARAMETER DEFINITIONS
Resolution - The total number of possible output codes is equal to 2N , where N·::: the number of bits
in the output word for each channel.
Signal-to-Noise plus Distortion Ratio - The ratio of the rms value of the signal to the rms sum of all
other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), i,ncluding
distortion components. Expressed in decibels.
Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value
of the signal. Units in percent.
Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels.
Interchannel Phase Deviation - The difference between the left and right channel sampling times.
Int~rchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal
applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The
decibels.
gain difference between
left and right channels. Units in
Gain Error -The deviation of the gain value from the typical number given in the analog
specifications table.
Gain Drift - The change in gain value with temperature. Units in ppm/°e.
Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000 ... 000) from the ideal
(112 LSB below AGND). Units in LSBs.
Differential Non-Linearity - The deviation of a code's width from the ideal width. Units in LSB's.
3-22
DS35F1
.._-_
.-_..--_._.
_
__
...-.
CS5326,CS5327,CS5328,CS5329
(All reprinted in the back of this data book)
REFERENCES
1) "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio" by D.R. WeIland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
2) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on
Oversampling Delta Sigma ADC's" by Steven Harris. Paper presented at the 87th Convention of the
Audio Engineering Society, October 1989.
3) " An 18-Bit Dual-Channel Oversampling Delta-Sigma AID Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
Ordering Guide
Model
CS5326-KP
CS5327-KP
CS5328-KP
CS5329-KP
CDB5326
CDB5327
CDB5328
CDB5329
DS35F1
Resolution
16-bits
16-bits
18-bits
18-bits
CS5326
CS5327
CS5328
CS5329
Filter Enters Stopband
26 kHz
24 kHz
26 kHz
24 kHz
Evaluation
Evaluation
Evaluation
Evaluation
Temperature
DOC to 7D °C
DOC to 7D °C
DOC to 7D °C
DOC to 7D °C
Package
28-pin Plastic
28-pin Plastic
28-pin Plastic
28-pin Plastic
DIP
DIP
DIP
DIP
Board
Board
Board
Board
3-23
.'
..............
.......
__ .......
~
CDB5326 CDB5327
CDB5328 CDB5329
~~
Semiconductor Corporation
Evaluation Board for CS5326, CS5327, CS5328 and CS5329
Features
General Description
• Demonstrates recommended layout
and grounding arrangements
• CS8402 Generates AES/EBU, S/PDIF
& CP-340 Compatible Digital Audio
• Buffered Serial Output Interface
• Digital and Analog Patch Areas
• On-board or externally supplied system
timing
-15V GND +15V
The CDB5326 and CDB5327 evaluation boards allow
fast evaluation of the CS5326 and CS5327 16-bit, stereo AID converters. The CDB5328 and CDB5329
evaluation boards allow fast evaluation of the CS5328
and CS5329 18-bit, stereo AID converters. The boards
generate all converter timing signals and provide a serial output interface. Evaluation requires a digital signal
processor, a low-distortion signal source, and a power
supply.
The evaluation boards may also be configured to accept external timing signals for operation in a user
application during system development.
ORDERING INFORMATION:
CDB5326, CDB5327, CDB5328, CDB5329
GND +5V
~UR
SCLK
CS5326,
CS5327,
CS5328,
SERIAL
INPUT/OUTPUT
, - - - - + ( 0 SDATA
OR
CS5329
AID CONVERTER
EXTCLKIN
CS8402
1<------------1-+-+------>1 DIGITAL AUDIO
LINE DRIVER
DIGITAL
AUDIO
DATA
,-~~~--------------~~-~--1
--_
--_
--_
-_
-1
- - SERIAL TO
PARALLEL
1--_
_
_-_
_
_- _ > 1 PARALLEL '---+ OUTPUT
I
L _ _ _s------------,~m~\IEFi~·E~
DATA
Not Provided on
the evaluaiton board.
MAR '93
DS35DB5
3-24
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
_.-_..--_._.
__.._-_
...-.
DS35DB5
CDB5326,7,8,9
3-25
---------------------..
: J.
,"
CDB5326,7,8,9
Power Supply Circuitry
Analog Input Buffer and Protection Circuitry
The schematic diagram in Figure 2 shows the
evaluation board power supply circuitry. Power is
supplied to the evaluation board by five binding
posts. The ±5 Volt analog power supply inputs of
the converter are derived from ±l5 Volts using
the voltage regulators U3 and US. The +5 Volt
digital supply for the converter and the discrete
logic on the board is provided by the +5V and
DGND binding posts with isolation provided by
Ll, L2 and L3. Dl, D2 and D3 are transient suppressors which also provide protection from
incorrectly connected power supply leads. Cl-C6
provide general power supply filtering for the
analog supplies. C13, C14, CI6 and C17 provide
localized decoupling for the converter VA+ and
VA- pins as shown in Figure 2. Note that C16 is
connected between VA- and VA+ and not VAand AGND. Rll and CIS provide isolation for
the analog logic power supply pin, VL+. The
evaluation board uses both an analog and a digital ground plane which are connected at a single
point. This ground plane arrangement isolates
digital logic nois,e from the analog circuitry.
As shown in Figure 2, the analog input signals
are connected to the board via the BNC connectors labeled AINL and AINR. The input buffer
and protection circuit is comprised of UlO, Rl2Rl5, Philips BAT-85 schottky diodes D5-D8, and
the 5.6V zener diodes D9-DlO. The Crystal Application Note "ADC Input Buffer and Protection
Techniques" discusses this circuit and component
selection criteria. Jumpers have been included to
allow the input buffers to be easily bypassed and
terminated.
RC filters, Rl6/Cl8 and Rl8/Cl9, provide antialias filtering and the optimum source
impedance for the ADC analog inputs. The
ZEROR and ZEROL inputs of the ADC are tied
to analog ground through identical filters to duplicate the output impedance of the analog
buffers for use during offset calibration.
+15V
+15V (01-'--~------"---+_ U2-6
U9-3
U8-9
ACLKA
Jl4-3
SCLK
SCLK
Figure 6. Offset Calibration Circuit
U7-10
f-Cl,,-S. - . - - - - - - - ' - '
Reset/Offset Calibration Circuit
U1
, CSS326,
, CSS327,
,CSS328,
,
OR
, CS5329
UR
uR
SDATA
1-'1-,-4-<~-~---------.D - :U R
__ ,D RDY
Figure 10. Suggested Serial to Parallel Interface
(Not provided on the evaluation board)
3-34
DS35DB5
I
!
Q)
ai
....:
cD
o
.IV
OIl
oAQG
QG
+5V
-15V
o
-\Sf
<\Sf
+I5V
N
ACID
C")
in
m
o
C
QOJ
J6
c:::::::J C7
c=Jca
QG
n
C6
J1
o
OUTPUT
n
.H~ D
01lD aP
SW1
tm :I2t
,
....
!I=
.....
~O fr
B U
C27
bt
=-t
t.. ,
"=
1~ Ii.
;'0
SW2
o
PCB5J26 REV.E
llaiJ -c::::::JR19
-c::::::J-
JI2
JIJ
SCUgwS~
0-
U7
. . .-
-----
~
tll=ltI
R12
RI5
6
_
l/R
0
..
!
..
r.;i
~
OUT
-r::=:J-c:::J-
o
r:I hnD
"I-itl
-
orr
g
U D?
=-
S!!!
I
u
...;
.....
~
i
0"
.
.
-~!:!~~
0
IXI
C25
U9
" .
SDATA
CI5
<
[DCJ
OUT
SDATA
O~. OU8
-_
C4
C~"CJ.n
LD
0
TICJI C29IT IT"::0 ~~
R7
~
e
J5
~
•
~
_ _ _--,C19
2J
L1 lJ
U2
iii! B!
§ ~<
LIR
D~
0
c=J DUc5 c=J
R5
IJIGITAL
Q02
JJ
AQGOVOOCIr9
Ol2
R6
001
J4
..
. .
0
SCLK
EXT CLKff
Evaluation Board
o
It)
ID
C
It)
M
~
-____-_
.. ...-.
. --_._.
....
CDB5326,7,8,9
Figure 12. CDB5326/718/9Rev. E. Component Side
3·36
DS35DB5
_.-_..--_._.
-_.._-_
...-.
CDB5326,7,8,9
Figure 13. CDB5326171819 Rev. E. Solder Side
DS35DB5
3-37
.._-_
_.-_..---,._.
__
...-.
CDB5326;7.8,9.
• Notes •
3-38
DS35DB5
..............
......
.........
CS5336 CS5338 CS5339
.., ~--
Semiconductor Corporation
16-Bit, Stereo AID Converters for Digital Audio
Features
General Description
• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference
The CS5336, CS5338 & CS5339 are complete analogto-digital converters for stereo digital audio systems.
They perform sampling, analog-to-digital conversion and
anti-aliasing filtering, generating 16-bit values for both
left and right inputs in serial form. The output word rate
can be up to 50 kHz per channel.
• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
• Low Noise and Distortion
>90 dB St(N+D)
The ADCs use delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
• Internal 64X Oversampling
The CS5336 & CS5338 have an SCLK which clocks out
data on rising edges. The CS5339 has an SCLK which
clocks out data on falling edges.
• Linear Phase Digital Anti-Alias Filtering
0.01 dB Passband Ripple
80dB Stopband Rejection
The CS5336 has a filter passband of dc to 22kHz. The
CS5338 & CS5339 have a filter passband of dc to 24
kHz. The filters have linear phase, 0.01 dB passband
ripple, and >80 dB stopband rejection.
• Low Power Dissipation: 400 mW
Power-Down Mode for Portable
Applications
The ADC's are housed in a 0.6" wide 28-pin plastic DIP,
and also in a 0.3" wide 28-pin SOIC surface mount
package. Extended temperature range versions of the
CS5336 are also available.
• Evaluation Board Available
ORDERING INFORMATION:
IClKA
APD
OClKD
ACAl
IClKD
FSYNC SClK
See Page 3-59
UR
VREF
SDATA
CMODE
SMODE
AINl
ZEROl
Digital Decimation
Filter
TST
AINR
Digital Decimation
Filter
ZEROR
,.-----,
AGND
l'
VA+
VA-
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Vl+
lGND
DCAl DPD
VD+
,8
NC
DGND
AUG '93
DS23F1
3-39
...._
_-_...-.
._
--_.-.
_
....
CS5336, CS5338, CS5339
(Logic 0 = GND; LOgic 1 = VD+; K grade: TA = 25°C; Band T
grades: TA == TMIN to TMAX; VA+, VL+,VD+ = 5V; VA- = -5V; Full~Scale Input Sinewave, 1kHz; Output word
rate = 48 kHz;SCLK = 3.072 MHz; Source Impedance = 501.1 with 10 nF to AGND; Measurement Bandwidth is
10 Hz to 20 kHz; unless otherwise specified.)
ANALOG CHARACTERISTICS
CS5336-B
CS5336,8,9-K
CS5336-T
Symbol Min Typ Max Min Typ Max Min Typ Max Units
Parameter
Specified Temperature Range
TA
Resolution
0
to
70
-40
to
+85
-55
to
+125
°C
16
-
-
16
-
-
16
-
-
Bits
-
90
93.5
-
84
92
dB
85
89
82
86
-
95
-
94
dB
Dynamic Performance
Dynamic Range
92.7 95.7
Signal-to-(Noise + Distortion); THD+N
S/(N+D) 90.7 92.7
-
Signal to Peak Noise
Total Harmonic Distortion
THO
Interchannel Isolation
.0025.001
-
Interchannel Phase Deviation
(dc to 20 kHz)
96
.0001
100 106
-
-
.0001
83
96
-
.05
-
.01
0.1
-
±3
±6
%
70
-
ppmf'C
±16 ±65
-
20
-
.0001
90
106
-
-
.01
.005 .001
.013 .005
dB
dB
%
°
dB
dc Accuracy
-
Interchannel Gain Mismatch
(includes Vref tolerance)
Gain Error
Gain Drift
(includes Vref drift, Note 1)
Bipolar Offset Error
(Note 2)
Offset Drift
(Note1)
0.01 0.05
±1
±5
-
±2
±5
25
-
-
70
-
±5
±15
15
- -
±10 ±30
20
-
LSB
-
ppm/oC
Analog Input
Input Voltage Range
(±Full Scale)
Input Impedance
VIN
±3.5 ±3.68
-
- -
65
-
-
25
-25
30
35
-35
45
10
-10
10
50
-50
400
ZIN
-
65
-
25
-25
30
35
-35
45
10
-10
10
50
-50
400
±-3.5±3.68
-
65
-
kg
-
25
-25
30
35
-35
50
mA
mA
rnA
10
-10
10
50
-50
400
ItA
ItA
ItA
400 600
0.15 2.5
mW
mW
±3.5 ±3.68
V
Power Supplies
Power Supply Current
with APD, DPD low
(Normal Operation)
(VA+)+(VL+)
VAVD+
IA+
IA10+
Power Supply Current
with APD, DPD high
(Power-Down Mode)
(VA+)+(VL+)
VAVD+
IA+
IA10+
(APD, DPD Low)
(APD, DPD High)
PDN
PDS
Power Consumption
Power Supply
Rejection Ratio
Notes:
(dc to 26 kHz)
(26 kHz to 3.046 MHz)
PSRR
-
-
-
- - -
400 575
0.15 2.5
400 575
0.15 2.5
54
100
54
100
-
-
-
- -
54
100
-
dB
dB
1. This parameter is guaranteed by design and/or characterization.
2. After calibration with DCAL connected to ACAL, and ZEROL & ZEROR terminated to AGND with an
impedance matched to the AINR & AINL source impedance. Executing a calibration with ACAL tied
low (See Power Down and Offset Calibration section) will yield an offset error of typically less than
±5LSB.
Specifications are subject to change without notice.
3-40
DS23F1
----------------------
CS5336, CS5338, CS5339
DIGITAL FILTER CHARACTERISTICS
= 25 ° C·, VA+ , VL+ ,VD+ = 5V +- 5%', VA- = -5V +- 5%', Output word
(TA
Parameter
Passband
(-3 dB)
(-3 dB)
(-0.Q1 dB)
(-0.01 dB)
Symbol
Min
CS5336
CS5338, CS5339
CS5336
CS5338. CS5339
Passband Ripple
Stopband
CS5336
CS5338, CS5339
(Note 3)
Stopband Atlenuation
Units
22
24
20
22
kHz
kHz
kHz
kHz
dB
kHz
kHz
0
0
0
0
to
to
to
to
-
-
± 0.01
26
28
to
to
3046
3044
80
Group Delay (OWR = Output Word Rate)
-
tgd
Group Delay Variation vs. Frequency
Notes:
rate of 48 kHz)
Max
Typ
L>.
t gd
18/0WR
-
-
dB
0.0
us
s
3. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (that is: there is
no rejection for n x 3.072MHz ±22kHz for the CS5338 & CS5339, or n x 3.072MHz ±20.0kHz for the
CS5336, where n = 0,1,2,3 ... ).
DIGITAL CHARACTERISTICS
TA
= 25 °C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Parameter
VIH
70%VD+
-
V
Low-Level Input Voltage
VIL
-
30% VD+
V
High-Level Output Voltage at 10 = -20uA
VOH
4.4
-
-
V
Low-Level Output Voltage at 10 = 20uA
VOL
0.1
V
Input Leakage Current
-
-
lin
1.0
-
uA
ABSOLUTE MAXIMUM RATINGS (AGND,
Parameter
DC Power Supplies:
Symbol
Positive Analog
Negative Analog
VA+
VA-
Positive Logic
Positive Digital
VL+
VD+
Input Current, Any Pin Except Supplies
Analog Input Voltage (AIN and ZERO pins)
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
LGND, DGND = OV, all voltages with respect to GND)
I in
V1NA
Min
-0.3
+0.3
-0.3
Max
+6.0
-6.0
(VA+) +0.3
-0.3
+6.0
(VA-)-0.3
Units
V
V
V
V
± 10
mA
(VA+ )+0.3
V
V
V1ND
-0.3
(VD+) + 0.3
TA
-55
+125
°C
Tstg
-65
+150
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS23F1
3-41
----------------------
CS5336,CS5338,CS5339
SWITCHING CHARACTERISTICS
(TA = 25°C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = OV, Logic 1 =VD+; CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
t clkw1
78
3906
ns
t clkl1
3.1
t clkh1
31
-
ns
40
ns
2604
ns
-
ns
t i01
5
ICLKD Period (CMODE high)
tclkw2
52
-
ICLKD Low (CMODE high)
t clkl2
20
-
t clkh2
20
ICLKD Period (CMODE low)
(Note 6)
ICLKD Low (CMODE low)
I.CLKD High (CMODE low)
ICLKD rising to OCLKD rising (CMODE low)
t i02
5
ICLKD rising to UR edge (CMODE low, MASTER mode)
t ilr1
5
ICLKD rising to FSYNC edge (CMODE low, MASTER mode)
t ifs1
5
ICLKD rising to SCLK edge (CMODE low, MASTER mode)
t isclk1
5
ICLKD falling to UR edge (CMODE high, MASTER mode)
t i1r2
5
t ifs2
5
-
t isclk2
5
ICLKD High (CMODE high)
ICLKD rising or falling to OCLKD rising (CMODE high, Note 4)
ICLKD falling to FSYNC edge (CMODE high, MASTER mode)
ICLKD falling to SCLK edge (CMODE high, MASTER mode)
ns
ns
45
ns
50
ns
50
ns
50
ns
50
ns
50
ns
-
50
ns
ns
0
-
50
SCLK duty cycle (MASTER mode)
40
50
60
%
SCLK rising to UR (MASTER mode, Note 5)
tmslr
-20
20
ns
SCLK rising to FSYNC (MASTER mode, Note 5)
t msfs
-20
20
ns
SCLK Period (SLAVE mode)
t sclkw
155
-
ns
t sclkl
60
-
ns
t sclkh
60
-
50
ns
4096
-
1/0WR
SCLK rising to SDATA valid (MASTER mode, Note 5)
tsdo
SCLK Pulse Width Low (SLAVE mode)
SCLK Pulse Width High (SLAVE mode)
SCLK rising to SDATA valid (SLAVE mode, Note 5)
t Irdss
-
t slr1
30
t slr2
30
t sfs1
30
t dss
UR edge to MSB valid (SLAVE mode)
Falling SCLK to UR edge delay (SLAVE mode, Note 5)
UR edge to falling SCLK setup time (SLAVE mode, Note 5)
Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5)
Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5)
t sfs2
30
DPD pulse width
todw
2 xtclkw
DPD rising to DCAL rising
t pcr
DPD falling to DCAL falling (OWR
Notes:
3-42
4.
5.
6.
=Output Word Rate)
-
t oel
-
-
ns
50
ns
50
ns
-
ns
ns
ns
ns
ns
ICLKD rising or falling depends on DPD to LlR timing (see Figure 2).
SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339.
Specifies minimum output word rate (OWR) of 1 kHz.
DS23F1
.-_
..--_._.
__.._-_
...-.
CS5336, CS5338, CS5339
ICLKD
IClKD
=:i
OCLKD
(CMODElow)
I--
I clkw1
~~ \'---~/
~---liol
UR oUlpul
(MASTER mode)
FSYNC oUlpul
(MASTER mode)
SCLKoulpul
(MASTER mode)
~ __ilr_1
_ _ _ _ _ _ _ _ __
~--I~ifS~I~----------------
-
,
~-----------------
URoulpul
(MASTER mode)
---d
~mslr
\
{
X
(MASTER mode)
--,
SClKoutput
(MASTER mode)
---~I~
l ilr2
lifs2
-----------~~~-,---------
ICLKD to Outputs Propagation Delays (CMODE high)
"'pdw
'pet
ro-----...-.--------+
:=J i'= Isdo
1
~
C
i'=
C
DPD
I msfs
SCLK to SDATA, UR & FSYNC - MASTER Mode
DCAl
t
------
Power Down & Calibration Timing
1
1
SDATA
---~:l------~~'L------_ _____--+1~
FSYNC output
1
FSYNC outpul
(MASTER mode)
UR inpul
(SLAVE mode)
(MASTER mode)
: \'-----~!
isclk2
SDATA
SCLKinpul
(SLAVE mode)
UR output
liselkl
ICLKD to OUtputs Propagation Delays (CMODE low)
SCLKoulpul
(MASTER mode)
OClKD
(CMODE high)
~
rlselkw
----
---~/~---------~I
---~-:::..,F Ilrdss
____%
MS8
~_-..J-"---,~ Idss
X MS8-1 ~
SCLK to UR & SDATA - SLAVE mode, FSYNC high
SCLKinpul
(SLAVE mode)
FSYNC inpul
(SLAVE mode)
SDATA
FSYNC to SCLK - SLAVE Mode, FSYNC Controlled.
DS23F1
3-43
.
'
'"
----------.------------
,
..
CS5336, C$5338, CS53.39
RECOMMENDED OPERATING CONDITIONS
(AGND , LGND , DGND =
ov·, all voltages with respect to ground)
Parameter
DC Power Supplies:
Analog Input Voltage
Notes:
Symbol
Min
Typ
Max
Units
VD+
VL+
VA+
VA-
4.75
4.75
4.75
-4.75
5.0
5.0
5.0
-5.0
VA+
VA+
5.25
-5.25
V
V
V
V
VAIN
-3.68
-
3.68
V
Positive Digital
Positive Logic
Positive Analog
Negative Analog
(Note 7)
7. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive
full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These
values are subject to the gain error tolerance specification. Additional tag bits are output to indicate
the amount of overdrive.
I' +5VAnalog
-~
t
I
- __---
as
:::;
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
22
23
24
25
26
27
28
29
30
Input Frequency (kHz)
Figure 16. CS5338/9 Digital Filter Transition Band
DS23F1
Input Frequency (kHz)
Figure 17. CS5336 Digital Filter Transition Band
3-53
.._-_
.-_
_
..---.-...-.
CS5336,CS5338,CS5339
_:-
PIN DESCRIPTIONS
ANALOG GROUND AGND
LEFT CHANNEL ANALOG INPUT
AINl
LEFT CHANNEL ZERO INPUT ZEROl
POSITIVE ANALOG POWER
VA+
NEGATIVE ANALOG POWER
VAANALOG POWER DOWN INPUT
APD
ANALOG CALIBRATE INPUT ACAl
NO CONNECT
NC
DIGITAL CALIBRATE OUTPUT DCAl
DIGITAL POWER DOWN INPUT
DPD
TEST
TST
SELECT CLOCK MODE CMODE
SELECT SERIAL 1/0 MODE SMODE
LEFT/RIGHT SELECT
LiR"
VREF
AINR
ZEROR
Vl+
lGND
IClKA
NC
OClKD
IClKD
DGND
VD+
FSYNC
SDATA
SClK
VOLTAGE REFERENCE OUTPUT
RIGHT CHANNEL ANALOG INPUT
RIGHT CHANNEL ZERO INPUT
ANALOG SECTION LOGIC POWER
ANALOG SECTION LOGIC GROUND
ANALOG SECTION CLOCK INPUT
NO CONNECT
DIGITAL SECTION OUTPUT CLOCK
DIGITAL SECTION CLOCK INPUT
DIGITAL GROUND
DIGITAL SECTION POSITIVE POWER
FRAME SYNC SIGNAL
SERIAL DATA OUTPUT
SERIAL DATA CLOCK
Power Supply Connections
VA+ - Positive Analog Power, PIN 4.
Positive analog supply. Nominally +5 volts.
VL+ - Positive Logic Power, PIN 25.
Positive logic supply for the analog section. Nominally +5 volts.
VA- - Negative Analog Power, PIN 5.
Negative analog supply. Nominally -5 volts.
AGND - Analog Ground, PIN 1.
Analog ground reference.
LGND - Logic Ground, PIN 24
Ground for the logic portions of the analog section.
VD+ - Positive Digital Power, PIN 18.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, PIN 19.
Digital ground for the digital section.
Analog Inputs
AINL, AINR - Left and Right Channel Analog Inputs, PINS 2, 27
Analog input connections for the left and right input channels. Nominally ±3.68 volts full
scale.
3-54
DS23F1
----------------------
CS5336, CS5338, CS5339
ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26.
Analog zero level inputs for the left and right channels. The levels present on these pins
can be used as zero during the offset calibration cycle. Normally connected to AGND,
optionally through networks matched to the analog input networks.
Analog Outputs
VREF - Voltage Reference Output, PIN 28.
Nominally -3.68 volts. Normally connected to a O.IIlF ceramic capacitor in parallel with a
10IlF or larger electrolytic capacitor. Note the negative output polarity.
Digital Inputs
ICLKA - Analog Section Input Clock, PIN 23.
This clock is internally divided by 2 to set the modulators' sample rate. Sampling rates,
output rates, and digital filter characteristics scale to ICLKA frequency. ICLKA frequency
is 128 X the output word rate. For example, 6.144 MHz ICLKA corresponds to an output
word rate of 48 kHz per channel. Normally connected to OCLKD.
ICLKD - Digital Section Input Clock, PIN 20.
This is the clock which runs the digital filter. ICLKD frequency is determined by the
required output word rate and by the CMODE pin. If CMODE is low, ICLKD frequency
should be 256 X the desired output word rate. If CMODE is high, ICLKD should be
384 X the desired output word rate. For example, with CMODE low, ICLKD should be
12.288 MHz for an output word rate of 48 kHz. This clock also generates OCLKD,
which is always 128 X the output word rate.
APD - Analog Power Down, PIN 6.
Analog section power-down command. When high, the analog circuitry is in power-down
mode. APD is normally connected to DPD when using the power down feature. If power
down is not used, then connect APD to AGND.
DPD - Digital Power Down, PIN 10
Digital section power-down command. Bringing DPD high puts the digital section into
power-down mode. Upon returning low, the ADC starts an offset calibration cycle. This
takes 4096 uR periods (85.33 ms with a 12.288 MHz ICLKD). DCAL is high during the
calibrate cycle and goes low upon completion. DPD is normally connected to APD when
using the power down feature. A calibration cycle should always be initiated after
applying power to the supply pins.
ACAL - Analog Calibrate, PIN 7.
Analog section calibration command. When high, causes the left and right channel
. modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively.
May be connected to DCAL.
DS23F1
3-55
--------------_.~-----
CS5336,CS5338,CS5339
CMODE - Clock Mode Select, PIN 12.
CMODE should be tied low to select an ICLKD frequency of 256 X the output word rate.
CMODE should be tied high to select an ICLKD frequency of 384 X the output word
rate.
SMODE - Serial Interface Mode Select, PIN 13.
SMODE should be tied high to select serial interface master mode, where SCLK, FSYNC
and uR are all outputs, generated by internal dividers operating from ICLKD. SMODE
should be tied low to select serial interface slave mode, where SCLK, FSYNC and uR
are all inputs. In slave mode, uR, FSYNC and SCLK need to be derived from ICLKD
using external dividers.
Digital Outputs
SDATA - Serial Data Output, PIN 16.
Audio data bits are presented MSB fIrst, in 2's complement format. Additional tag bits,
which indicate input overload and left/right channel data, are output immediately
following each audio data word.
DCAL - Digital Calibrate Output, PIN 9.
DCAL rises immediately upon entering the power-down state (DPD brought high). It
returns low 4096 LtR periods after leaving the power down state (DPD brought low),
indicating the end of the offset calibration cycle (which == 85.33 ms with a 12.288 MHz
ICLKD). Maybe connected to ACAL.
OCLKD - Digital Section Output Clock, PIN 21.
OCLKD is always 128 X the output word rate. Normally connected to ICLKA.
Digital Inputs or Outputs
SCLK - Serial Data Clock, PIN 15.
Data is clocked out on the rising edge of SCLK for the CS5336 and CS5338. Data is
clocked out on the falling edge of SCLK for the CS5339.
In master mQde (SMODE high), SCLK is a continuous o:utput clock at 64 X the output
word rate.
In'slave mode (SMODE low), SCLK is an input, which requires a continuously supplied
clock at any frequency from 32 X to 128 X the output word rate (64 X is preferred).
When FSYNC is high, SCLK clocks out serial data, except for the MSB which appears
on SDATA when uR changes.
3-56
DS23F1
----------------------
CS5336, CS5338, CS5339
LIR - LeftlRight Select, PIN 14.
In master mode (SMODE high), uR is an output whose frequency is at the output word
rate. LlR edges occur 1 SCLK cycle before FSYNC rises. When uR is high, left channel
data is on SDATA, except for the first SCLK cycle. When uR is low, right channel data
is on SDATA, except for the first SCLK cycle. The MSB data bit appears on SDATA one
SCLK cycle after uR changes.
In slave mode (SMODE low), LtR is an input which selects the left or right channel for
output on SDATA. The rising edge of uR starts the MSB of the left channel data. uR
frequency must be equal to the output word rate.
Although the outputs of each channel are transmitted at different times, the two words in
an LtR cycle represent simultaneously sampled analog inputs.
FSYNC - Frame Synchronization Signal, PIN 17.
In master mode (SMODE high), FSYNC is an output which goes high coincident with the
start of the first SDATA bit (MSB) and falls low immediately after the last SDATA audio
data bit (LSB).
In slave mode (SMODE low), FSYNC is an input which controls the clocking out of the
data bits on SDATA. FSYNC is normally tied high, which causes the data bits to be
clocked out immediately following LtR transitions. If it is desired to delay the data bits
from the uR edge, then FSYNC must be low during the delay period. Bringing FSYNC
high will then enable the clocking out of the SDATA bits. Note that the MSB will be
clocked out based on the uR edge, independent of the state of FSYNC.
Miscellaneous
NC - No Connection, PINS 8, 22.
These two pins are bonded out to test outputs. They must not be connected to any external
component or any length of PC trace.
TST -Test Input, PIN 11.
Allows access to the ADC test modes, which are reserved for factory use. Must be tied to
DGND.
DS23F1
3-57
."
-____-_
.. ......
....
. '---".-.
CS5336.C$5338.CS5339
PARAMETER DEFINITIONS
Resolution - The total number of possible output codes is equal to 2N , where N
in the output word for each channel.
= the number of bits
Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels.
Signal-to-(Noise plus Distortion) Ratio - The ratio of the'rms value of the signal to the rms sum of all
other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including
.
distortion components. Expressed in decibels.'
Total Harmonic Distortion - The ratio· of the rms sum of all harmonics' up to 20 kHz to the rms value
of the signal. Units in percent.
Interchannel Phase Deviation - The difference between the left and right channel sampling times.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal
applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The
decibels.
gain difference between
left and right channels. Units in
Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude
value.
Gain Drift - The change in gain value with temperature. Units in ppmfOC.
Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000 ... 000) from the ideal
(l/2 LSB below AGND). Units in LSBs.
.
3-58
DS23F1
.-_
_
..--_._.
__.._-_
...-.
CS5336, CS5338, CS5339
REFERENCES
1) "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio" by D.R. WeIland, B.P. Del Signore, EJ. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
2) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on
Oversampling Delta Sigma ADC's" by Steven Harris. Paper presented at the 87th Convention of the
Audio Engineering Society, October 1989.
3) " An 18-Bit Dual-Channel o.versampling Delta-Sigma AID Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
Ordering Guide
Model
CS5336-KP
CS5336-BP
CS5338-KP
CS5339-KP
CS5336-KS
CS5336-BS
CS5338-KS
CS5339-KS
CS5336-TC
CDB5336
CDB5338
CDB5339
DS23F1
Resolution
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
Passband
22 kHz
22 kHz
24 kHz
24 kHz
22 kHz
22 kHz
24 kHz
24 kHz
22 kHz
SCLK
active
active
active
,j. active
i active
i active
i active
,j. active
i active
i
i
i
Temperature
O°C to 70°C
-40 to +85 °C
O°C to 70°C
O°C to 70°C
O°C to 70°C
-40 to +85 °C
O°C to 70°C
O°C to 70°C
-55 to +125 °C
Package
28-pin Plastic DIP
28-pin Plastic DIP
28-pin Plastic DIP
28-pin Plastic DIP
28-pin SOIC
28-pin SOIC
28-pin SOIC
28-pin SOIC
28-pin Sidebrazed Ceramic DIP
CS5336 Evaluation Board
CS5338 Evaluation Board
CS5339 Evaluation Board
3-59
....
.
......... ....
CDB5336
CDB5338 CDB5339
.".,,~
•~.w _ _
. . ..
Semiconductor Corporation
Evaluation Board for CS5336, CS5338 & CS5339
Features
General Description
• Demonstrates recommended layout
and grounding arrangements
• CS8402 Generates AES/EBU, S/PDIF
& CP-340 Compatible Digital Audio
The CDB5336, CDB5338 & CDB5339 evaluation
boards allow fast evaluation of the CS5336, CS5338
and CS5339 16-bit, stereoAJD converters .. The boards
generate all converter timing· signals and provide both
parallel and serial output interfaces. Evaluation requires a digital signal processor, a low-distortion· signal
source, and a power supply.
• Buffered Serial Output Interface
Also included is a CS8402 digital audio transmitterI,C.,
which can generate AES/EBU, S/PDIF & EIAJ CP-340
compatible audio data.
• 16-Bit Parallel Output Interface
The evaluation boards may also be configured to accept external timing signals for operation in a user
application during system development.
• Digital and Analog Patch Areas
ORDERING INFORMATION:
• On-board or externally supplied system
timing
-15V GND +15V
GND +5V
CDB5336, CDB5338, CDB5339
EXTCLKIN
FSYNC
r--------+(O
SCLK
SERIAL
OUTPUT
DATA
CS5336,
CS5338,
r-----+{O SDATA
OR
CS5339
AID CONVERTER
SERIAL TO
PARALLEL
OUTPUT
DATA
PARALLEL
CONVERTER
CS8402
DIGITAL AUDIO
'--_-+I LINE DRIVER
AUG '93
DS23DB5
3-60
1----.....
DIGITAL
AUDIO
DATA
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
----------- -----------
CDB5336,8,9
Power Supply Circuitry
The schematic diagram in Figure 1 shows the
evaluation board power supply circuitry. Power
is supplied to the evaluation board by five binding posts. The ±5 Volt analog power supply
inputs of the converter are derived from ±I5
Volts using the voltage regulators UIO and UU.
The +5 Volt digital supply for the converter and
the discrete logic on the board is provided by the
+5V and DGND binding posts. D1, D2 and D4
are transient suppressors which also provide protection from incorrectly connected power supply
leads. C25-C28, C30 and C31 provide general
power supply filtering for the analog supplies.
As shown in Figure 2, ClO-CI3 provide localized decoupling for the converter VA+ and VApins. Note that C13 is connected between VAand VA+ and not VA- and AGND. Space for a
ferrite bead inductor, Ll, has been provided so
that the board may be modified to power the
converter's VD+ input directly from the VA+
supply. Note that the trace connecting the VD+
power to the VD+ of the converter must be bro-
ken before Ll may be installed. R5 and C7 lowpass filter the analog logic power supply pin,
VL+. The evaluation board uses both an analog
and a digital ground plane which are connected
at a single point by J1. This ground plane arrangement isolates the board's digital logic from
the analog circuitry.
Offset Calibration & Reset Circuit
Figure 1, shows the optional offset calibration
circuit provided on the evaluation board. Upon
power-up, this circuit provides a pulse on the
Analog-to-Digital Converter's DPD pin initiating
an offset calibration cycle. Releasing SWI also
initiates an offset calibration cycle. P6 (see Figure 2) selects the signal source used during
offset calibration. In the "AIN" position, the
AINL and AINR inputs are selected during calibration, while in the "ZERO" position, the
ZEROL and ZEROR inputs are selected.
= =
02 04 1N6276A 1.5KE
01 = P6KE-6V8P from Thomson
RST
VO+
+5V
03
1N4148
10
OGNO (c»---It--____-~
SW1-j
CAL
U7D
Cal
(OPO CS5336)
lL_ _'"
Figure 1. Power Supply and Reset Circuitry
DS23DB5
3-61
.-_
_
..,--_._.
_-..--_
...-.
CDB5336,8,9
Cl~+
28
VD+
VD+ )-_+_+_---<~____----'1=_j8 VD+
TI5
L1
~
R5
VA+
NC
NC
A'PD
DPD
VL+
25
ACAL
VL+
DCAL
IC7VA+
..-_-+~
6
10
_0:=
c
Cal
Cal
,0.luF
51i1
)-__
8
VREF
___4-'-i VA+
U1
CMODE
PI!
7
~
9
,AIN
_0: ZER0=:1VD+
12
:::r
°
R7
CS5336
1 AGND
CS5338
SMODE
CS5339
TST
13
Pins 1,13
U9
11
UR
VA-
- 14
UR
VALGND
SDATA
DGND
UR
SDATA
16
SDATA
SCLK
15
R1
From
Buffers
Fig 3
27
SCLK
AINR
FSYNC
R2
2
AINL
ZEROL
ICLKD
ZEROR
OCLKD
21
SCLK
FSYNC
17
FSYNC
20
ICLKD
ICLKA
23
P7
,-
ICLKA
R3'
51 {l
: EXT
,INT
NC
U3
• Optional
8
Oscillator
MCK
8402
VD+
12.288 MHz
14
0.1 uF
EXT
CLKIN
Figure 2 ADC Connections
3-62
DS23DB5
----------- -----------
CDB5336,8,9
Analog Inputs
tance. Also remove U13 op-amp, to remove the
lkn load impedance.
As shown in Figure 2, the analog input signals
are connected to the CS5336 via an RC network.
R 1 and C 1 provide anti aliasing and optimum
source impedance for the right analog input
channel while R2 and C2 do so for the left channel. The ZEROR and ZEROL inputs are tied to
the analog ground plane on the board as shipped
from the factory, but space is provided for an optional RC section on each. These RC sections
may be added to model the output impedance of
the analog signal source to minimize offset error
during calibration.
Timing Generator
P7 selects the master clock source supplied to
the ICLKD pin of the converter. As shipped
from the factory, P7 is set to the "INT" position
to select the 12.288 MHz clock signal provided
by U3. An external master clock signal may be
connected to the EXTCLKIN connector and selected by placing P7 in the "EXT" position. Note
that R6, tied between EXTCLKIN and GND, is
available for impedance matching an external
clock source. The board is shipped with SMODE
high, which selects MASTER timing mode. In
this mode, SCLK, LlR and FSYNC are all outputs, generated by the converter from ICLKD.
Figure 3 shows the optional input buffer circuit.
This can be used as an example input buffer circuit for your application. If the ADC is driven
from a son source impedance signal generator,
the input buffer amplifiers may be bypassed.
Place P8 and P9 jumpers in the OUT position,
and short circuit Rl and R2. This ensures that
the ADC is driven from a son source resis-
Serial Output Interface
The serial output interface is provided by the
SDATA, SCLK, FSYNC and LlR BNC
connectors on the evaluation board. These out-
VA+
R22
0.1 uF
AINL
\~-+--_2---j _
8
3 U13A
~ C32
>"-_ _ _...::IN-'----'-~-o- -~ R1,Fig2
OUT
C33
~ 0.1
uF
I
6:
P8
VA1kD
AINR
IN
r--
R2,Fig2
P9
Figure 3. Input Buffer Circuit
DS23DB5
3·63
~,
~'
_.-_..__.._-_
...-.
---.~.
CDB5336,8,9
VD+
OClKD
P4
~ - - - - - - - - - - - - - - - ' DIPSW 8
SW2
19
VD+
VD+
MCK
SCK
3
-·2
PRO
14
2
15
3
4
13
4
5
12
C7tC3
GND
P3
15
CBl
C1tFCO
CBl
C6JC2
CS8402
U2
9 V
V
10
C
11
U
C9tC15
EM1tCa
C
EMOtC9
U
6
11
13
a
9
14
7
10
24
CRElFCl
Rla 20kO
RST
MO
12
16
16
RST
R19
Ml
R20
M2
SDATA
FSYNC
a
CS5336
{FSYNC
SDATA
TXN
~.
7
902
74HCOB
2
lieu
SCHOTT 67125450
PULSE PE65612
13
RESET2
12
D2
74HC74
U12B
ClK
a 02 SET2
11
UR CS5336
FSYNC CS5336
+5V
Figure 4. CS8402 Digital Audio Line Driver Connections
puts are buffered, as shown in Figure 5, in order
to isolate the converter from the digital signal
processor. If slave mode is selected by pulling
SMODE low, then U9 (74HC243) will change to
the opposite direction, and act as an input buffer.
U9 is provided to protect against inadvertent external driving of SCLK, uR and FSYNC while
in MASTER mode. U9 is not necessary in your
application circuit.
3-64
Jumper P4 allows the board to be configured for
either the CS5336/38, or the CS5339, which
have opposite polarities of SCLK.
Parallel Output Interface
Figure 6 depicts the parallel output interface on
the evaluation board. 16-bit words are assembled
from the serial data output of the converter. Each
bit of serial data is clocked out of the converter
DS23DB5
----------------------
CDB5336,8,9
VD+
RB
A-to-B
Enable
13
SMODE
11
SCLK
10
B1
FSYNC
B2
-
9 B3
UR
SDATA
SDATA I -.........J---+ SDATA
6
_r,
VD+
B-to-A
Enable
VCC
GND
U9
74HC243
A1
A2
4
5
A4
B4
B
R9
20kD
A3
R10
20kD
74HC08
:~: ~_
ff"m,
"---_-------,-'-0
,P4
'5337139
'
CS8402
: ,;"'
Pin 11
U4, U5
595'5
Figure 5. Serial Output Interface
on the rising edge of SCLK and shifted into the
I6-bit shift register formed by U4 and US on
SCLK's falling edge. After all data bits for the
selected channel have been shifted into U4 and
US the data is latched onto PI by a delayed version of FSYNC.
PS selects the channel whose output data will be
converted to parallel form and presented on PI.
With PS in the "B" (both) position, parallel data
from one channel will be presented first with
data from the other channel presented subsequently. In the "L" (left) position, only left
channel conversions will be presented, while in
the "R" (right) position only right channel conversions are presented.
Two interface mechanisms are provided for reading the data from this port. With the fIrst, the
edges of LlR may be used to clock the parallel
data into the digital signal processor. (Set jumper
P2 into the LlR position.) Alternatively, a handshake protocol implemented with DACK and
DRDY may be used to transfer data to the signal
DS23DB5
processor. (Set jumper P2 to the DRDY position.) The fall of DRDY informs the digital
signal processor that a new data word is available. The processor then reads the port and
acknowledges the transfer by asserting DACK.
Note that DRDY will not be asserted again unless DACK is momentarily brought high
although new data will continue to be latched
onto the port.
Digital Audio Standard Interface
Included on the evaluation board is a CS8402
Digital Audio Line Driver. This device can implement AESIEBU, S/PDIF and EIA] CP-340
interface standards. Figure 4 shows the schematic for the CS8402. P3 allows the C, U and V
bits to be driven from external logic using the
CBL output for block synchronization. SW2 provides 8 DIP switches to select various modes
and bits for the CS8402. Table 3 lists the settings
for the professional mode which is the default
setting for the evaluation board from the factory.
The third switch selects between professional
3-65
-_
.. _------------------
CDB5336,8,9
x0 - - - - - ,
VR
PIN14
U1
VD+
~w
8,
l'
'
R'
, - - 6
FSYNC
PIN17
U1
IClKD
PIN20
U1
iT
5
VD+
°H~7__~~\/,\/\,~~~
U7C
OG~6~~+AI\A,~~~
2
D
0
°F~5~~~\/,\/\,~~~
R15
VD+
47kO
5
0Er4~~~\/,\/\,~~~
U4
74HC595 0 Df"3~~-I-'\/\/\'+'-'=--.Lf-'
~__~10~SRClR
6
U12A Q I -________~-t------i2--1> latch ClK
3
ClK
VD+
OCf"2~~-I-'\/\A,~~f-'
0 8 r1__--'-~\/,\/\,~"-'-~
5-----'=-t-',W'\r-I--=---W_
r l_____1'-.!1-1> Shift ClK
0 A f-'1..::c
DIN
OE
14
13
PRE
4
R11
47kO
VD+
P4
13
9
VD+
OEO
7
H f'---,-+-,'\/\/'\r+-=-,f-/
OG~6~~~\/,\I\'~~~
OF 5
0Er4~_4'-+-',\AI'\r+-=-~
74HC595
0D~3~--,5"--+''\/\I'\r+-=--,-+"
L -_ _~1~OSRClR
OC~2~--,6"--+',\AI'\r+~-,-+"
2
r -____________________. . ,_______1_
--c> latch ClK
'--_____1:..:1-1> Shift ClK
DIN
14
SDATA>----------'
3
2
ClR
ClK
U6A
74HC74
D
PRE
3
US
08>-,-1__-'-I-1\/\,/\,..j-=--4-/
0 A 1-'1-=-5--='-I-I\I\I\,r+-~~
13
5
ClR
0
8
4
11
47kO
R11
VD+
Figure 6. Parallel Output Interface
3-66
DS23DB5
_.-_..--_._.
__.._-_
...-.
CONNECTOR
CDB5336,8,9
INPUT/OUTPUT
SIGNAL PRESENT
+15
input
+ IS Volts from power supply
-IS
input
-IS Volts from power supply
AGND
input
analog ground connection from power supply
+5
input
+5V for ADC VD+ and discrete logic
DGND
input
digital ground connection from power supply
AINl
input
left channel analog input
AINR
input
right channel analog input
EXTClKIN
UR
input
external master clock input
outputlinput
left fright channel signal
output
serial output data
SClK
output/input
serial output clock
FSYNC
output/input
data framing signal
output
CS8402 digital output via transformer
SDATA
DIGITAL OUTPUT
P3
output/input
CS8402 C,U,V inputs; CBl output
PI
output
parallel output data
Table 1. System Connections
JUMPER
PURPOSE
P6
select!> offset calibration
input source
POSITION
AIN
'ZERO
P7
P5
P2
P8, P9
P4
FUNCTION SELECTED
AINl and AINR selected during
offset calibration
ZEROl and ZEROR selected during
offset calibration
selects master clock source
for CS5326 ClKIN
'INT
ClKIN provided by U3
EXT
ClKIN provided by EXTClKIN BNC
selects channel for serial to
parallel conversion
'l
left channel data presented on PI
R
right channel data presented on PI
B
left then right channel data
alternately presented on PI
the
DRDY selected to signal
arrival of
new data for the selected channel
selects llR or DRDY as the
output status signal presented
on PI
'DRDY
UR
UR selected
selects optional input buffers
'IN
Buffer amplifier in circuit
OUT
Buffer amplifier bypassed
selects device type
5337/39
Correct SClK for CS5337 & CS5339
5336/38
Correct SClK for CS5336 & CS5338
, Default setting from factory
Table 2. Jumper Selectable Options
OS23DB5
3-67
----------------------
CDB5336,8,9
Switch#
O::Closed,1=Open
3
PRO=O
1
.....
···········1·
5, 2
default
default
00 - Not Indicated c Default to 48 kHz
01 - 48 kHz
10 - 44.1 kHz·
11 - 32 kHz
1
1 - Non-Audio
...... C~~(?9,C10,C11 - Channel Mode (1 of~?it~)
1
0
I···
.....
~"""
.......
0000 - Not indicated - Default to 2-channel
0100 - Stereophonic
EM1 EMO
1
1
0
0
C1 - Audio
o - Normal Audio
C9
default
~
1
0
1
0
1
0
I·
8,.............
7 ..
C6,C7 - Sample Frequency
.............. ................................................................................................
C1
........ 1
6
Disabled
Internally Generated (channel status bytes 14-17 and byte 22)
C6,C7
1
1
0
0
default
...........
Local Sample
Address Counter & Reliability
Flags
..................................................................
.. .................................................
0
1
1
4
Professional Mode, CO=1 (default)
CRE
default
.............
Comment
1
0
1
0
..........
C2,C3,C4
- Emphasis
..... .. "".........
..............
~
000 - Not Indicated - default to none
100 - No emphasis
110 -50/15 f.1s
111 - CCITT J.t?
Table 3. CS8402 Switch Definitions - Professional Mode,
and consumer modes; however, the CS8402 output to the transformer must be modified, as
shown below Table 4, to be compatible with the
consumer interface. Table 4 lists the switch settings for consumer mode .. If the C input of
connector P3 is used, the input bits are logically
OR'ed with the appropriate DIP switch bits. In
Tables 3 and 4, the· 'C' bits listed in the comment section are taken from the Digital Audio
Interface specifications. As an example, switch 6
in the professional mode (Table 3) controls C9
which is the inverse of channel status bit 9 (also
listed as byte 1, bit 1 in the CS84b2 data sheet).
Channel status bit 9 is one of four bits indicating
channel mode. Therefore, using DIP switch 6,
only two of the available channel modes may be
selected. The C input port on connector P3 may
be used to select other channel modes. See the
3-68
CS8401 & CS8402 part data sheet for more information on the operation of the CS8402.
.DS23DB!i
.._-_
.-_
_
..--_._.
__
...-.
CDB5336,8,9
Switch#
O=Closed, 1=Open
3
PRO=1
1,4
+
I·
2
Consumer Mode, CO=O (Note 1)
FC1, FCO
0
0
1
1
C24,C25,C26,C27 - Sample Frequency (encoded 2 of 4 bits)
.................
0
1
0
1
..........
..
1
0
5
,
6
······1
I···
..........
Note:
i·········· ......
......
"",,,,,
o - Copy Inhibited/Copyright Asserted
1 - Copy Permitted/Copyright Not Asserted
- Generation.........................
Status...
C15
........ .....
C15
~
. .........
~
........
o - Definition
1
0
8, 7
..............
C3,C4,C5 - Emphasis (1 of 3 bits)
C2 - Copy/Copyright
................................
1
0
I
~.
~.
000 - None
100 - 50/15 J.ls
C2
.....
........
0000 - 44.1 kHz
0100 - 48 kHz
1100 - 32 kHz
0000 - 44.1 kHz, CD Mode
C3
......
Comment
1-
is based on category code.
See CS8402 Data Sheet, Appendix A
C8,C9
C8-C14 -.............................
Category...Code
(2 of 7 bits)
......................
...........
1
1
0
0
0000000 - General
0100000 - PCM encoder/decoder
1000000 - Compact Disk - CD
1100000 - Digital Audio Tape - DAT
1
0
1
0
1. The evaluation board is shipped from the factory in the Professional mode. Changing switch 3 to
open places the CS8402 in Consumer mode; however, the hardware is not set up for consumer
mode. To modify the hardware for Consumer mode, change R19 to 3740 and add R20 at 90.90.
Then, as shown in the figure below, cut the trace connecting TXN to the transformer, and connect
the transformer side to the ground hole provided. For a full explanation of the consumer hardware
.
interface, see the CS8402 data sheet, Appendix B.
Table 4. CS8402 Switch Definitions· Consumer Mode
~
TX~
~~T_X_N~
:'
___
20
R\l19\1'-_---'----R20
2
3
Ilrn
~
SCHOTT 67125450
PULSE PE65612
DS23DB5
3-69
.._-_
.-_
_
..--_._.
_-"
..-.
CDB5336,8,9
Figure 7. Top Ground Plane Layer (NOT TO SCALE)
3-70
DS23DB5
---------------------•
DS23DB5
•.......
.....................•
•••••••••••••••••••••
• ~
...............................
~~~~~~~~~~~~~n
•
••••••••••••••••••••••••
••
••
•
•
•
•
•
•
•
•
•
•
CDB5336~8,9
~~
••••••••••••••••••••••••
••••••••••••••••••••••••
••••••••••••••••
••
•••••••••••••••••
•••••••••••••• ••
..............
.... ,,
(
~
•
•
·1.· .-_._-..
•
••••
••••
........... ...
'--
•••••••
·······:::::::::11:
•••••••
•••••••
·······iiiii;!iilli
•••••••
•••••••
•••••••••••••
•
•••••••••••••
••••••••••••• ••
•••••••••••••
Figure 8. Bottom Trace Layer (NOT TO SCALE)
•
3-71
II)
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as
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~~
CS5345
.."
Semiconductor Corporation
Low Power, Stereo AID Converter for Digital Audio
Features
General Description
•
Single +5 V Power Supply
•
•
91 dB Dynamic Range
Linear Phase Digital Anti-Alias Filtering
0.05dB Passband Ripple
73.5dB Stopband Rejection
•
•
The CS5345 is a complete stereo analog-to-digital,converter which performs anti-alias filtering, sampling and
analog-to-digital conversion generating 16-bit values for
both left and right inputs in serial form. The output
word rate can be up to 50 kHz per channel.
The CS5345 operates from a single +5V supply and
requires only 100 mW for normal operation, making it
ideal for battery-powered applications.
Low Power Dissipation: 100 mW
Power-Down Mode for Portable
Applications
The ADC uses delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The linear-phase digital filter has a passband of dc to
22 kHz, 0.05 dB passband ripple and >73.5 dB stopband rejection.
Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference
•
Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
•
•
Internal 64X Oversampling
Evaluation Board Available
The device is available in a 0.3" wide 28-pin SOIC surface mount package.
ORDERING INFORMATION:
Model
CS5345-KS
CDB5345
Temp. Range
0° to 70°C
Package Type
28-pin plastic SOIC
Evaluation Board
SDATA
CMODE
SMODE
VCOM
AINL+
AINL-
Digital Decimation
Filter
AINR+
AINR-
AGND
23
VA+
Preliminary Product Information
15
VD+
PO
VS+
DGND
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS112PP1
3-73
-_._-------------------
CS5345
ANALOG CHARACTERISTICS (TA = 25°C; VA+, VS+,
VD+ = 5V; Full-Scale Input Sinewave,
1kHz; Output word rate = 48 kHz; SCLK = 3.072 MHz; Source Impedance = 1500 with 1500 pF across AIN+,
AIN-; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified, Logic O=OV, Logic 1=VD+.)
Parameter
Symbol
Resolution
Min
Typ
Max
Units
16
-
-
Bits
-
91
88
-
dB
dB
Dynamic Performance
Dynamic Range
A-weighted
'.
Total Harmonic Distortion+Noise
-86
"68
-28
-
dB
dB
dB
0.0001
-
Degree
100
-
dB
0.05
-.
dB
Gain Error
-
±2
±5
%
Gain Drift
-
60
-
ppml°C
-
±5
±30
LSB
Total Harmonic Distortion
OdB THD+N
-20dB
-60dB
-
OdB
THD
. Interchannel Phase Deviation
Interchannel Isolation
(dc to 20 kHz)
.0018
%
dcAccuracy
Interchannel Gain Mismatch
Bipolar Offset Error
(After Calibration)
Analog Input
Differential Input Voltage Range
(Full Scale) (Note 1)
VIN
3.46
3.75
4.06
Vpp
Input Impedance
ZIN
-
85
-
k.Q
-
10.5
9.5
16
14
rnA
rnA
50
50
-
-
~
~
mW
mW
Power Supplies
Power Supply Current
Normal Operation
VA+
(VD+) + (VS+)
IA+
ID+
Power Supply Current
Power-Down Mode
VA+
(VD+) + (VS+)
IA+
ID+
Power Dissipation
Notes:
100
150
0.5
Power Down
1. The peak-to-peak input voltage range for each input is equal to {(VA+)-VREF}xO.625. The nominal
value for (VA+) - VREF is 3 Volts. The differential peak-to-peak input voltage is equal to twice the
individual voltage range. (See Figure 5)
-
* Refer to Parameter Definitions at the end of this data sheet.
Specifications are subject to change without notice.
3-74
DS112PP1
----------------------
CS5345
DIGITAL FILTER CHARACTERISTICS
(TA = 25°C; VA+, VS+, VD+ = 5V ± 5%; Output word rate (Fs) of 48 kHz)
Symbol
Parameter
Passband
(-0.05 dB)
(-2.8 dB)
(-6.5 dB)
Min
Typ
Max
Units
-
o to 18
o to 22
o to 24
-
kHz
kHz
kHz
-
±a.05
dB
3040
kHz
-
dB
-
-
Passband Ripple
Stopband
32
Stopband Attenuation
(Note 2)
Group Delay (OWR = Output Word Rate)
(Note 3)
73.5
-
8/0WR
Symbol
Min
Typ
High-Level Input Voltage
VIH
70% VD+
-
-
V
Low-Level Input Voltage
VIL
-
-
30% VD+
V
= -20 ItA
Low-Level Output Voltage at 10 = 20 I1A
VOH
4.4
-
V
VOL
-
-
0.1
V
1.0
-
I1A
tgd
Group Delay Variation vs. Frequency
Notes:
s
-
0.0
8tgd
I1S
2. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency ( n x 3.072MHz ±18kHz
where n = 0,1,2,3 ... ).
3. Group delay for OWR = 48kHz, tgd = 8148kHz = 16711S
DIGITAL CHARACTERISTICS
(TA = 25°C; VA+, VS+, VD+ = 5V ± 5%)
Parameter
High-Level Output Voltage at 10
Input Leakage Current
lin
ABSOLUTE MAXIMUM RATINGS .(AGND,
Parameter
DC Power Supplies:
Positive Analog
Positive Digital
Units
DGND = OV, all voltages with respect to ground.)
Symbol
Min
Typ
Max
Units
VA+
VD+
-0.3
-0.3
-
+6.0
+6.0
V
V
±10
mA
(VA+)+0.3
V
lin
-
Analog Input Voltage
VINA
-0.3
Digital Input Voltage
Input Current, Any Pin ExceptSupplies
Max
VIND
-0.3
Ambient Temperature (power applied)
TA
-55
Storage Temperature
Tstg
-65
(VD+)+0.3
V
+125
°C
+150
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS112PP1
3-75
----------------------
CS5345:
SWITCHING CHARACTERISTICS
(TA = 25°C; VA+, VS+, VD+
= 5V ± 5%;
Inputs: Logic 0
= OV, Logic 1 = VA+, VS+, VD+;
Parameter
CL
= 20 pF)
Symbol
Min
Typ
Max
MCLK Period (CMODE low)
t clkw1
78.13
ns
t clkl1
31.25
-
ns
MCLK High (CMODE low)
. t clkh1
31.25
-
781.3
MCLK Low (CMODE low)
-
ns
520.8
ns
-
-
ns
-
75
%
-
ns
ns
ns
-
70
ns
-
70
ns
-
ns
MCLK Period (CMODE high)
t clkw2
52.0
MCLK Low (CMODE high)
t clkl2
20.83
MCLK High (CMODE high)
t clkh2
20.83
UR duty cycle
25
SCLK Period
t sclkw
312.5
SCLK Pulse Width Low
t sclkl
100
SCLK Pulse Width High
t sclkh
100
t dss
t Irdss
-
-
SCLK falling to SDATA valid
UR edge to MSB valid
Units
ns
PD pulse width
t odw
150
PD falling to SDATA valid
t oct
-
8224/0WR
Rising SCLK to UR edge delay
t slr1
30
+70
ns
UR edge to rising SCLK setup time
s
tslr2
30
tis
-70
-
Symbol
Min
Typ
Max
Units
5.25
5.25
5.25
V
V
-
SCLK Falling to FSYNC delay
ns
ns
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = OV; all voltages with respect to ground)
Parameter
DC Power Supplies:
Positive Analog
Positive Digital
. Positive Substrate
Differential Analog Input Voltage
Analog Input Bias Voltage
Notes:
3-76
(Note 5)
VA+
VD+
VS+
4.75
4.75
4.75
5.0
5.0
5.0
(Notes 1&6)
VIN
-
3.75
0.5VA+
Vpp
V
5. VD+ must be within 0.3V of VA+.
6. The output codes will clip at full scale with differential input signals >3.75 Vpp.
DS112PP1
--.------~-------------
CS5345
tpdw
tpet
I,
.1.
.1
tclkh
I-
DPD
tclkl
'I'
tclkw
-
I
I
J1JL
-->f
JI--,--I_
,I
SDATA
i'-
MCLK Definition
-l.----C
Power Down & SDATA Valid
SCLK
I
VR
~
~
SDATA
~
I
tsctkw
~tlrdss
l
MSB
JE,='~
X MSB-1
SCLK to LIR & SDATA-Mode 1 (SMODE High), FSYNC Ignored
Mode 2 - FSYNC High (SMODE Low)
SCLK
I
I
I
-I I-tfs
-----,r-----~------4-----------~s~s--------~--------
VA
-------'-,\1.-_______
','T-',
FSYNC
_____="-'-, ~tlrdss
SDATA
="
I- tdss
______---'l______M_S_B______---'~ MSB-1
C:J
LSB+1
X
LSB
SCLK to L1R, SDATA & FSYNC - Mode 2 - FSYNC Controlled (SMODE Low)
DS112PP1
3-77
y~
.CS5345·
'.'''"
FerriteSead
+5V
Analog
- --
10!J:F
~+
O.1I1F
1
T
O.1I1F
O.1I1F
, - -.
T
~O.1
+lJo I1F
I1F
~
~23
~
4.711F
l ;
~
14
VA+
VD+
_~O.1I1F
r
VREF
_~
PD
VCOM
SMODE
1500 pF
150n
..
=}
6
~
7
150n
150n
Power Down &
Cal. Control
8
CS5345
25
CMODE
150n
~
24
T
Analog
Input
Circuits
iOn
VS+
4
=?
5
Mode
Select
.19
Audio Data
Processor
AINL+ ."
AINL-
T
13
SDATA
AINR+
MCLK
AINR-
SCLK
1500 pF
UR
FSYNC
(
9
TST01
AGND
DGND
1
16
TST
117
TST02
•..
.10
.12
Timing
Logic
.11
Clock
&
18
~
~
l
I
TSTO pins should beleft
floating, with no trace
1
Figure 1. Typical Connection Diagram
'DS112~P1
.-_
_
..--_._.
__.._-_
...-.
CS5345
GENERAL DESCRIPTION
SYSTEM DESIGN
The CS5345 is a 16-bit, 2-channel NO converter
designed for stereo digital audio applications that
require a single +5V supply. The device uses two
one-bit delta-sigma modulators which simultaneously sample the analog input signals at a 64 X
sampling rate. The resulting serial bit streams are
digitally filtered, yielding pairs of 16-bit values.
This technique yields nearly ideal conversion
performance independent of input frequency and
amplitude. The converters do not require difficult-to-design or expensive anti-alias filters and
do not require external sample-and-hold amplifiers or a voltage reference.
Very few external components are required to
support the ADC. Normal power supply decoupIing components, voltage reference bypass
capacitors and a resistor and capacitor on each
input for anti-aliasing are all that's required, as
shown in Figure 1.
An on-chip voltage reference provides for a differential input signal range of 3.75 Vpp. Offsets
are internally calibrated out during a power-up
self-calibration cycle. Output data is available in
serial form, coded as 2's complement 16-bit
numbers. Typical power consumption is
100 rnW. This can be further reduced to .05 mW
using the power-down mode.
For more information on delta-sigma modulation
and the particular implementation inside this
ADC, see the references at the end of this data
sheet.
UR
(kHz)
CMODE
MCLK
(MHz)
SCLK
(MHz)
32
low
8.192
2.048
32
high
12.288
2.048
44.1
low
11.2896
2.8224
44.1
high
16.9344
2.8224
48
low
12.288
3.072
48
high
18.432
3.072
Master Clock Input
The master input clock (MCLK) into the ADC
runs the digital filter and it is used to generate
the delta-sigma modulator sampling clock.
CMODE high will set the required MCLK frequency to 384 X the output word rate (OWR),
while CMODE low will set the required MCLK
frequency to 256 X OWR. Table 1 shows some
common clock frequencies.
Serial Data Interface
The serial data interface has 2 possible modes of
operation. LIR, SCLK and FSYNC are inputs in
both interface modes. LIR must be derived from
MCLK and be equal to the OWR. SCLK should
also be derived from MCLK and be equal to the
delta-sigma modulator sample rate (64 X OWR)
to eliminate the possibility of interference tones
in the output data. An SCLK frequency of 32 X
OWR is possible but may cause interference
tones. Data bits are clocked out via the SDATA
pin using SCLK, LIR and FSYNC inputs. The
serial nature of the output data results in the left
and right data words being read at different
times. However, the words within a LIR cycle
represent simultaneously sampled analog inputs.
Mode 1 (SMODE high) is shown in Figure 2.
The falling edge of SCLK causes the ADC to
output each data bit. Notice the one SCLK cycle
delay between LIR edges and the data MSB.
FSYNC is ignored and should be tied either
High or Low in this mode. Mode 1 is compatible
with I2S.
Table 1. Common Clock Frequencies
DS112PP1
3-79
_.-_..--_._.
__.._-_.
...-
CS5345
~--------------~
I131
LJR
I
1
fW
SClK
SDATA
0
~L-~__________~_______ _
I"
Left Audio Data
I"
'I
,I
Right Audio Data
Figure 2. Data Output Timing - Mode 1 (FSYNC High or Low)
~------------~~
I
UR
~30
~
31
2
I~-------------~
SCLK
FSYNC
SDATA
15
.1
Left Audio Data
Right Audio Data
Figure 3. Data Output Timing - Mode 2 - FSYNC High
Mode 2-FSYNC High (SMODE low) is shown
in Figure 3. The falling edge of SCLK caus~s
the ADC to output each data bit with the exception of the MSB which is clocked out by the LIR
edge.
In Mode 2-FSYNC Controlled, as shown in Figure 4, only the MSB is clocked out after the LIR
edge with FSYNC low, SCLK is ignored. When
it is desired to output data, bringing FSYNC
high will.enable SCLK to clock out data. This
feature is particularly useful to position the data
bits in time onto a common serial bus.
3-80
Analog Connections
Figure 1 shows the analog input connections.
The analog inputs are presented differentially to
the modulators via the AINR+, AINR- and
AINL+, AINL- pins. Each analog input will accept a maximum of 1.88 Vpp centered at +2.5 V.
The + and - input signals are 180 out of phase
resulting in a differential input voltage of
3.75 Vpp. Figure 5 shows the input signal levels
for full scale.
0
The CS5345 samples the analog inputs at
3.072 MHz for a 12.288 MHz MCLK (CMODE
low). The digital filter rejects all noise between
DS112PP1
----------- -----------
CS5345
~--------------~
I
UR
c-----------------I
~
SCLK
FSYNC
SDATA
,I
Right Audio Data
Left Audio Data
• Rising FSYNC enables
SCLK to clock out SDATA
..
Falling FSYNC stops SCLK from
clocking out SDATA
Figure 4. Data Output Timing- Mode 2 - FSYNC Controlled
32 kHz and (3.072 MHz-32 kHz). However, the
filter will not reject frequencies right around
3.072 MHz (and multiples of 3.072 MHz). Most
audio signals do not have significant energy at
3.072 MHz. Nevertheless, a 150 n resistor in series with each analog input and a 1500 pF
capacitor across the inputs will attenuate any
noise energy at 3.072 MHz, in addition to providing the optimum source impedance for the
modulators. The use of capacitors which have a
large voltage coefficient (such as general purpose
ceramics) must be avoided since these will degrade signal linearity. NPO, COG and polyester
film capacitors are acceptable. If active circuitry
precedes the ADC, it is recommended that the
above RC filter is placed between the active circuitry and the AINR and AINL pins. The above
example frequencies scale linearly with output
word rate.
Figure 6 is a suggested active input buffer circuit
which provides a differential signal and level
shifts up to +2.5 V. This circuit has been implemented on the CDB5345 evaluation board which
is available from Crystal Semiconductor.
DS112PP1
The on-chip voltage reference ((VA+) - 3.0 V) is
connected to VREF (pin 24). A 4.7 J.lF electrolytic capacitor in parallel with a 0.1 J.LF ceramic
capacitor attached between VREF and VA+
eliminates the effects of high frequency noise.
Notice that VREF is decoupled to VA+ not
AGND. This requirement is a result of the
modulator sampling between VREF and VA+.
No load current may be taken from the VREF
output pin.
An additional on-chip voltage reference
{(VA+) - 2.5 V)}is connected to VCOM
(pin 25). This output may be used to bias the
analog input circuitry if a high impedance, lowbias current buffer is used.
Power-Down and Offset Calibration
The ADC has a power-down mode wherein typical consumption drops to 0.5 mW. PD is the
power down pin for the device. When high, it
places the analog and digital circuitry in the
power-down mode. Bringing this pin low will release the power-down mode and initiate a
calibration sequence.
3-81
.._-_.
_.-_..--_._.
__
...-
CS5345
CS5345
calibration, the digital output of both channels is
forced to a 2's complement zero.
+3.44 V
+2.S0V
Power-up Considerations
--'------1AIN+
+1.S6V
+3.44 V
+2.S0V
+1.56 V
-
---
--
--
Upon initial application of power· to the supply
pins, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
potentially large values of data in these registers
with the correct values.
--
~
---
AIN·
-
+2.5 V
Full Scale Input level: (AIN+)· (AIN·): 3.75 Vpp
VCOM
Figure 5. Full Scale Input Voltage
The delta-sigma modulator +/- inputs are internally disconnected from the AIN pins and
shorted together during calibration. The digital
section of the device measures and stores a value
corresponding to the DC offset of each channel
in the calibration registers. This calibration value
is then subtracted from all future conversions
during normal operation. 8224 LIR cycles are required for a calibration sequence. A short delay
of approximately 18 output words will occur following calibration for the digital filter to begin
accurately tracking audio band signals. During
The modulators settle very quickly (a matter of
microseconds) after the analog section is powered, either through the application of power or
by . exiting the power-down mode. The voltage
reference takes a longer time to reach a final
value due to the presence of large external capacitance on the VREF pin. The calibration
period is optimized to allow the reference to settle for capacitor values of up to 4.7 11F. The use
of larger capacitors can cause erroneous calibration or make the device inoperable and is not
recommended.
~-------'-~AINL·
10 k
. LEFT
ANALOG
INPUT
10 k
10k
>-----1 r-+~V\l""""""_
10 uF
>---BAINL+
r+------.,--:-:------7 AINR-
10 k
RIGHT
ANALOG
INPUT
>---""*""7 AINR +
Figure 6. Example Input Buffer Circuit
3-82
DS112PP1
------------.---------Grounding and Power Supply Decoupling ."
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the
recommended power arrangements with VA+
connected to a clean +5 V supply. VS+ and VD+
should be powered from VA+ via a ferrite bead
to minimize noise coupling. To further minimize
noise coupling into the ADC, no additional devices should be powered from VD+. Analog
ground and digital ground should pe connected
together near to where the supplies are brought
onto the printed circuit board. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor
being the nearest.
The printed circuit. board layout should have
separate analog and digital regions and ground
planes, with the ADC straddling the boundary.
All signals, especially clocks, should be kept
away from the VREF pin in order to avoid unwanted coupling into the modulators. The
Crystal Semiconductor application note "Layout
and Design Rules for Data Converters" is available Crystal Semiconductor data books and
should be considered required reading. An evaluation board is available which demonstrates the
optimum layout and power supply arrangements,
, 'CS5345
as well as allowing fast evaluation of the
CS5345.
To minimize digital noise, connect the ADC
digital outputs only to CMOS inputs.
Syn~hronization
In systems where multiple ADC's are required,
care must be taken to insure that the ADC internal clocks are synchronized between converters
to insure simultaneous sampling.
Synchronous sampling is achieved by connecting
all PD pins to a single control signal and supplying the same LIR and MCLK to all converters.
1.0 -,----,-----;------,,-----,-----:----,
0.8
0.6
iii' 0.4
~
III 0.2
-g -0.0
§'-0.2
~-0.4
-0.6
-0,8
-1.0 +------i----j-----i-----i-------i'-----j
o
-90
0100
-110 -t-----r------.----,-----,------'-;--'---I
o
8.
162432
40
48
Input Frequency (kHz)
Figure 7. CS5345 Digital Filter Stopband Rejection
DS112PP1
8
12
16
Input Frequency (kHz)
20
24
1,-----~--~~----~~----,
o-t------,----,.--"
-10
-20
!g -30
-; -40
-g -50
'2 -60
~ -70
~ -80
4
Figure 8. CS5345 Digital Filter Passband Ripple
10'---~--~----~--~--~---'
~
of Multiple CS5345
O+-----~----~~
-1
iii' -2
~
~
-3
-4
~
-6
~ -5
::2
-7
-8
-9
_10-t------,------,------,-L-----I
8
16
24
32
o
Input Frequency (kHz)
Figure 9. CS5345 Digital Filter Transition Band
3-83
.....
...-..
_.-..,.,,_._
___-_
CS5345
PERFORMANCE
CRYSTAL
1KMIODB
0r-~~~----~
,
-20
Digital Filter
Figures 7, 8, and 9 sbo\\, 'the performance bf the
digital filter inCluded' in the ADC. All the plots
assume an output word rate of 48 kHz. The filter
frequency response will scale precisely with
changes in output word rate. The passband ripple
CRYSTAL
FRQRESP
.FLVL2(dBFS) YO FREQ(Hz)
1.0 ,---'--~-'---'------'.:.~----,A"""'p
0.5
•• - -
~
0.0
I -
-
1-
'T
-
-
••
-
-
1-
-
1-
-
,
-
••
-0.5
_.' - - I
-1.0
_ . . - -, - -
-
-
,-
-
..
-
••
-
-
1-
1-
-
r
-
...
-
-, -
-
'-
-
:.
/.;
-
,
-
-
1-
-
..
-
-
_,
..
-
-
•• -
'-
-
-
,-
-
-,
-
• • • • , • • ,• . • . • • • , . • '• • • • • , . • ,.
-.
·2.5
-3.0
. • • • , • • ' • • • • •' • • , • . '• • • - .' •. " • •
-3.5
-
-4.0
_I
-
L-~
20.0
_, -
-
,-
__
-
T
-
.'
-
~_~
4.02k
_, _
-
__
'.
_
12.Dk
8.o1k
,
-
_I
~_-'-'
.. :, .'.'.'.',','
..
, ' ,',',1
,
~
,
',', ' ,"
' , ' , ' ~,~
,' " .
-
, , """
,
.,
- ,- •- , -, ;-, ;-, - . i -, -' ,. ,-.
, " , ',',
' , ' , ',',
'
'. '.'
',',
,-,' -,,-',-., i' ,',
, ; ,'.
~
.
I , " ',I,
• '.'.'.' ~'~' •• : • '. '. '.' ,'~ •• ~ .' '. '. '.. ' :'~' ••
, , ',',',
, , ' ,','.
, ' , ',',',
.:. :.:.:
~:~:.
~:~
. • : .:.:. :.:::::.......
-, ' ,-'
' " , ' ,'.'
- - -,-"- '- ,- -I,',- --
_ : .:. :.:.:
~.
-140
Ap
.'. '.'.':':' ..
",",
. , _., '-, ' -, ' _, . . .' ,
- -' ,
- ', , ',',"
, ' , ' i ',',
_ _ ,_
~
..
_
± 0.05 dB
One Dual Domain tester. The CS5345 was in a
CDB5345 evaluation board, running at 48 kHz
word rate and interfaced to the System One via
the digital audio interface using a CS8402 transmitter.
_ _..........cL..J
16.0k
2O.ok
CRYSTAL
Figure 10. Frequency Response
is flat to
-120
FREQ(H~
AMP1 (dBFS) VB
__~--__--__~_~
, ,'.','
Figure 12. 1 kHz ·60 dB
,
-1.5
·2.0
-100
, , """
-
.. - -,- _ ..
• • • , • • ,• •
.eo
"',"
.'.'.'.'~;~'
THDNAMP
f'LVL2(dBFS) YO
AMPL(dBr)
-40r------------------~--------A~p
-50
maximum.
•••• :••••
J
•••• : ••••
,
J
• • • • :• • • •
,
.eo . . . . , ... - ; ... ',' ... ; ... ',' .. ' .
CRYSTAL
NOISE
IIMPI (dBFS) VB
FREQ(H>I
O,--~_~--_~~-~-_~_."...,
, ,',','
-20
.'.'.'.'~'~'
..
I , I.',',
,
' , ' ,',',
Ap
~
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-1002O'=--"7
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100
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-100
-70
,',',
, ' , ' ,',',
Figure 11. Noise Floor
Figure 13. mD+N vs Input Level at 1kHz
Figure 10 shows the CS5345 frequency response.
Figure 11 shows the noise floor with zero input
signal level. A 16 K point FFT was used.
Performance Measurements
All the following performance measurements
were taken using an Audio Precision System
3-84
Figure 12' shows a 1 kHz, -60 dB input signal
FFT plot. Notice the lack of harmonic distortion
DS112PP1
.._-_
_.-_..--_._.
__
...-.
CRYSTAL
THDNFRQ
CS5345
va
FLVL2(dBFS)
FREQ(Hz)
-60 ,.----~,-,~,,~,~,,---,~,-,~,~,,-,- - - ,-,~,'~'~"----:;---JAp
,
't
I,' ,',I
',',
- '- '- '_, c' c' __ _
-70
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-60
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,- ,-, -, .-, .-, - - , -, - '-, -, ,-, :' - - ; - ,- ,- '-, ',', - -
, I I,',',
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-100
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-110
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- ,- .- '-, .-,.-, - - • - ,- .- ,-,:,:, - - ; -
,- '-,' ,', - -
Figure 14. THD+N vs Frequency at -ldB
Schematic &Layout Review Service
components. This is a direct result of the perfect
differential non-linearity of the delta-sigma architecture
CRYSTAL
ADLIN
FLVL2(dBFS)
va AMPL(dB~
10 ,.------------------A~p
8
- - - -, - - - - , - - -
6
-
4
r
-
-
-
Figure 15 shows the linearity of the CS5345.
The input signal is at 500 Hz and is varied from
o dB (full scale) to -120 dB. At each input level,
the output level is measured and compared to
the perfect value. Any deviation is plotted as a
deviation away from 0 dB. Notice the close conformance to perfect linearity, until the noise
starts to influence the readings at about -100 dB.
Confirm Optimum
Schematic &Layout
Before Building Your
,- - - - , - - - - ,- - - -.-
-
-
-
T
-
-
-
-.-
-
-
-
- - - -, - - - - , - - - - '- - - - , - - - - ,- - - -
:~'----'----:---'----'--2
- - - -, - - - - , - - - -, - - - - , - - - -, - - - -
-4
- -, - - - - , - - - -' - - - - , -
- - '- - - -
-8
- - - -, - - - - , - - - -' - - - - , - - - -, - - - -
-8
- - - -, - - - - , - - - -, - - - - , - - - - ,- - -
-10
-1~
-100
-80
o
Figure 15. Output Level Error vs Input Level
Figure 13 shows the THD+N versus input level
at 1 kHz. This plot indicates an unweighted dynamic range of 88 dB.
Figure 14 shows THD+N versus frequency at
-1 dB input.
DS112PP1
3-85
.._-_
.-_
........
_
..-__
...-..
CS~345
PIN DESCRIPTIONS
+ RIGHT
- RIGHT
+ LEFT
- LEFT
NO CONNECT
NC
NO CONNECT
NC
NO CONNECT
NC
CHANNEL ANALOG INPUT AINR+
CHANNEL ANALOG INPUT AINR·
CHANNEL ANALOG INPUT AINL+
CHANNEL ANALOG INPUT AINL·
PO
POWER DOWN INPUT
SELECT CLOCK MODE CMODE
MASTER CLOCK INPUT MCLK
LEFTIRIGHT SELECT
LIR
. SERIAL DATA CLOCK SCLK
SILI6~~I~~·~:J.~A~~T~~~· ~D~~~
NC
NO CONNECT
NC
NO CONNECT
NC
NO CONNECT
VCOM VOLTAGE COMMON OUTPUT
VREF VOLTAGE REFERENCE OUTPUT
VA+
POSITIVE ANALOG POWER
AGND ANALOG GROUND
TST02 TEST OUTPUT
TST01 TEST OUTPUT
SMODE SELECT SERIAL 1/0 MODE
FSYNC FRAME SYNC SIGNAL
TST
TEST
DGND DIGITAL GROUND
VD+
POSITIVE DIGITAL POWER
Power Supply Connections
VA+· Analog Power, PIN 23
'Positive supply for the analog section. Nolninally +5 volts.
VS+· Digital Power, PIN 14
Positive supply for .the, silicon .substrate. Nominally +5 volts.
VD+ • Digital Power,' PINtS
Positive supply for the digital section. Nominally +5 volts.
AGND • Analog Ground, PIN 22
Analog ground reference.
DGND • Digital Ground, PIN 16
Digital ground for the digital section.
Analog Inputs
±AINL, ±AINR· Differential Left and Right Channel Analog Inputs, PINS 6, 7, 4, S
Analog input connections for the left and right input channels. A nominal. differential input
voltage of 3.75 Vpp will produce a full scale digital output.
Analog Outputs
VREF • Voltage Reference Output, Pin 24
Internal voltage reference output. Nominally (VA+) - 3.0 V. Must be bypassed to VA+ with a
0.1 JlF ceramic capacitor in parallel with a 4.7 JlF electrolytic capacitor.
3·86
DS112PP1
----------- -----------
CS5345
VCOM - Voltage Common Output, PIN 2S
Nominally (VA+) - 2.5 volts. May be used to bias the analog input circuitry if an additional
buffer is used.
Digital Inputs
MCLK - Master Input Clock, PIN 10
Sampling rates, output rates and digital filter characteristics scale to MCLK frequency. MCLK
frequency is either 256 or 384 X the output word rate (see CMODE). For example, a
12.288 MHz MCLK corresponds to an output word rate of 48 kHz per channel with CMODE
low.
SCLK - Serial Data Clock, PIN 12
SCLK is an input clock at any frequency from 32 X to 128 X the output word rate (64 X is
preferred). Data is clocked out on the falling edge of SCLK. See the descriptions of Data
Output Mode 1 and Mode 2.
LIR - LeftlRight Select, PIN 11
LIR is an input which selects the left or right channel for output on SDATA. The LIR frequency
must be at the output word rate. Although the outputs of each channel are transmitted at
different times, the two words in an LIR cycle represent simultaneously sampled analog inputs.
Left channel data is on SDATA when LIR is low in Mode 1 (SMODE high). Right channel data
is on SDATA when LIR is high. The MSB data bit appears on SDATA one SCLK cycle after
LIR changes.
Left channel data is on SDATA when LIR is high in Mode 2 (SMODE low). Right channel data
is on SDATA when LlR is low. The rising edge of LIR clocks out the MSB of the left channel
data. The falling edge of LIR clocks out the MSB of the right channel data.
PD - Analog Power Down, PIN 8
Device power-down command. The analog and digital circuitry are in power-down mode when
PD is logic high.
CMODE - Clock Mode Select, PIN 9
CMODE should be tied low to select an MCLK frequency of 256 X the output word rate.
CMODE should be tied high to select an MCLK frequency of 384 X the output word rate.
SMODE - Serial Interface Mode Select, PIN 19
SMODE must be tied high to select serial interface Mode 1. SMODE must be tied low to select
serial interface Mode 2. In all interface modes, LIR, FSYNC and SCLK should be derived
from MCLK using external dividers.
DS112PP1
3-87
.._-_
.-_
_
..--_._.
__
...-.
CS5345
FSYNC - Frame Synchronization Signal, PIN 18
In Mode 1 (SMODE high), FSYNC is ignored but must be connected to VD+ or DGND.
In Mode 2 (SMODE low), FSYNC is an input which controls the output of data on SDATA.
FSYNC is normally tied high, which causes the data bits to be clocked out immediately
following LIR transitions. If it is desired to delay the data bits from the LIR edge, then FSYNC
must be low during the delay period. Bringing FSYNC high will enable SCLK to clock out of
the SDATA bits. Note that the MSB will be clocked out based on the LIR edge, independent of
the state of FSYNC.
Digital Outputs
SDATA - Serial Data Output, PIN 13
Audio data bits are presented MSB first, in 2's complement format.
Miscellaneous
NC - No Connection, PINS 1,2,3,26,27,28
No internal connection.
TSTOl, TSt02 -Test Pins, PIN 20, 21
These pins are factory test outputs and must not be connected to any external component or
length of PC trace.
tST - test Input, PIN 17
Allows access to the CS5345 test modes. Must be connected to digital ground for normal
operation.
PARAMETER DEFINITIONS
Resolution - The total number of possible output codes is equal to 2N , where N
in the output word for each channel.
= the number of bits
Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels.
Total Harmonic Distortion+Noise - The ratio of the rms sum of all spectral components over the
specified bandwidth (typically 10 Hz to 20 kHz), excluding signal, to the rms value of the
signal.
Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz tq the rms value
of the signal.
Interchannel Phase Deviation - The difference between the left and right channel sampling times.
3-88
DS112PP1
.._-_
_.-_..--_._.
__
...-.
CS5345
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal
applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The
decibels.
gain difference between
left and right channels. Units in
Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude
value.
Gain Drift - The change in gain value with temperature. Units in ppml°C.
Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000... 000) from the
ideal . Units in LSBs.
REFERENCES· All reprinted in this data book.
1) "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio" by D.R. WeIland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
2) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on
Oversampling Delta Sigma ADC's" by Steven Harris. Paper presented at the 87th Convention of the
Audio Engineering Society, October 1989.
3) " An 18-Bit Dual-Channel Oversampling Delta-Sigma AID Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
DS112PP1
3·89
-
. .............
__ .....
.....
~
I CDB5345I
~
."
~..,
."
Semiconductor Corporation
·EvaluationBoard for CS5345
Features
General Description
• Demonstrates recommended layout
and grol-lnding arrangements
• CS8402 Generates AES/EBU, SPDIF
& EIAJ-340 Compatible Digital Audio
• Demonstrates CS8402 Generation of
System Clocks
• Buffered Serial Output Interlace
The COB5345 evaluation;board allows fast evaluation
of the e85345 16-bit, stereo AID converter. The board
generates all converter timing signals and provides serial output interfaces. Evaluation requires a digital
signal processor, a low-distortion signal source, and a
power supply.
Also included is a e88402 digital audio transmitter I.e.,
which .can generate AE8/EBU, 8POIF & EIAJ-340
compatible audio data via standard phono and optical
connectors.
The evaluation boards may also be configured to accept external timing signals for operation in a user
application during system development.
• Digital and· Analog Patch Areas
ORDERING INFORMATION: CDB5345
GND
MCLK
0
'!
AINR
riOt-- Input
~9 '
Buff/e"",r_ _-.I
0
CS5345
UR
SERIAL
OUTPUT
DATA
SCLK
SDATA
AID CONVERTER
AINL
riOt-- Input
~9'
Buf:;;:le"",_ _-.I
CS8402
I o - - - - - - - - - - I c + - - - - - I DIGITAL AUDIO
INTERFACE
Optical
Output
AUG '93
081120B1
3-90
Crystal Semiconductor Corporation
Copyright © Crystal Semiconductor Corporation 1993
,
(All Rights Reserved)
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 758("
....
....~....
I\)
c
ar
....
=••
AINR-
'1=
'"..........=.,
AINR+
Input Buffer
AINL-
Serial Output
Interface
CS5345
AID Converter
AINL+
-
UR
MCLK
i
i
SCLK
I
SDATA
I
PD
CS1232
CS8402
Power Monitorl
Reset Circuit
~
RST
Digital Audio
Interface
Power
Conditioning
o
c
m
U1
Co)
....~
t;
Figure 1. CDB5345 Overview
I
_.-_..--_._.
__.._-_
...-.
CDB5345
L4
.---/'iT'---[::> VD2+
L2
Ll
VA1+
+5V
r---~-~~--~-----_L~VA+
C9
0.1 mF
,--...,
GND
r---~~~~~--
AGND
~
DGND
Figure 2. Power Conditioning
PowerSuppryCUCuU7y
power supply leads. C7 and C9 provide general
power supply filtering for the analog supply.'
Cl3 and CI7 provide localized decoupling for
the converter VA+ pin, Figure 4. The evaluation
board uses both an analog and a digital ground
plane which are connected at a single point. This
ground plane arrangement isolates the board's
digital logic from the analog circuitry.
The schematic diagram in Figure 2 shows the
evaluation board power supply circuitry. Power
and ground for the evaluation board are made
via the two binding posts. The +5 Volt ~alog
power supply (VA+) powers .the analog input
buffers, Figure 5. The ADC analog supply,
VAl+, is derived from VA+ via the ferrite bead,
L1, to minimize noise coupling.
The ADC substrate bias voltage, VS+, and digital supply voltage, VD+, are derived from VAI+
through the ferrite bead L3, Figure 4. Notice the
lowpass filter, RI8 and CI8 I C19, between VS+
and VD+. VD+ is not used to power any other
The +5 Volt digital supply for the discrete logic
is derived from the VA+ through the ferrite bead,
L2. Z3 is a transient suppresser which also provides protection from incorrectly connected
R9
VD1+
RST
LI R L~-----7--lST
U2
CS1232
, - - - - - - 3 - - lTOL
.----0SW2
-I-
5
RST 1------1
PD
PBRST
2
~----~TD
GND
4
Figure 3. Power MonitorlReset Circnit
3-92
OS112081
_.-_..--_._.
__..--_
...-.
CDB5345
digital logic on the evaluation board, which is
necessary to minimize digital noise on VA1+.
ing output from the evaluation board on powerup and initiates a CS5345 calibration sequence
when the supply voltages have stabilized. This
also ensures that the CS5345 calibration data
will be replaced if a momentary loss of power
occurs. A CS5345 calibration sequence can also
be initiated manually with SW2. The CS 1232
also implements a system watchdog timer and
monitors the LIR clock.
Power monitor & Reset Circuit
The power monitor / clock monitor / reset function has been implemented using the Crystal
Semiconductor CS1232 Micromonitor, Figure 3.
The power-monitor threshold for the CS1232 has
been configured to issue a reset command to the
CS5345 PD and the CS8402 RST pins when the
supply voltage ,VD1+, is below 4.62Y. The command will remain asserted for approximately
250 ms after the supply voltage exceeds the
threshold. This prevents erroneous data from be-
Analog Inputs
As shown in Figure 4, the analog input signals
are connected to the CS5345 via an RC network.
R1-R4 and Cl-C4 provide antialiasing and optiVD+
R18
10W
L3
VA1+
C17
+
Io.1m
C4
C13
mFTi mF
10
16V
0.1
C10
0.1 mF
C16 +
10mF
16V
C5
0.1 mF
23
VA+
L-_""*-__
24--j VREF
L -_ _ _ _ _ _ _ _ _ _ _ _2~5
AINL+
AINL-
VCOM
R1
/\,_ _ _-.-_ _ _6--jAINL+
C1
1500pF
14
VS+
U1
CS5345
18
FSYNC 1_ _ _ _ _ _ _ _ _ _---'
TST01 20
TST02 21
PD~PD
SDATA 13
7 AINLV\r----e>-----'--I
SCLK~SCLK
5 AINR+
v'v-------1I>-----'--I
UR
C2
1500pF
AINR-
19
SMODE 1-------.
22 AGND
DGND
1~UR
9
CMODEf------.
5 AINRv'v---__.>-------1
150
SDATA
MCLK~MCLK
150
R3
AINR+
15
VD+~----------~
TST
Figure 4. ADC Connections
OS112081
3-93
----------------..
~-----
CDB5345
mum source impedance for the analog input
channels.
the standardized implementation of SIPDIF with
both coax and optical outputs.
Figure 5 shows the input buffer circuit. This circuit converts single-ended inputs to differential
and elevates the center point of the differential
singles to approximately +2.5 V.
The CS8402 is configured to operate in Mode 1
which allows the CS8402 to generate LIR and
SCLK from MCLK. This not only simplifies the
design but also lowers the number of components on the evaluation board. See the CS8401 /
CS8402 data sheet for more information on the
operation of the CS8402.
CS5345 Configuration
The CS5345 is configured for Mode 2-FSYNC
high. MCLK is set for 256 X OWR by CMODE
low. Refer to the CS5345 data sheet for a complete description of the CS5345 operation.
Digital Audio Standard Interface and Clock
Generation
Serial Outputlnterjace
The serial output interface is provided by the
SDATA, SCLK, and LIR BNC connectors on the
evaluation board. These outputs are buffered, as
shown in Figure 8, in order to isolate the converter from the digital signal processor.
The CS8402 Digital Audio Interface Transmitter
is included on the evaluation board. This device
can implement either AESIEBU, S/PDIF or
EIAJ-340 interface standards. The CDB5345
digital audio interface circuit, Figures 6 and 7, is
'-----t-------~
R10
r
.-------~v'~~~~------~~------~~~\
10K
+
U6 = MC33079
C8
AINR-
R6
v--------~~VA1+
C3 10k
O ,mF
.
Figure 5. Input ButTer Circuit
3-94
05112081
_-_...-..
_.--..-___.......
CDB5345
VD+
GND
GND
CBL
9
V
10
11
21
~
~
u..
..:
o
(f)
RST 1-1.::...S- - C ) RST
20
TXP
TXP
TXN 17
TRNPT/FCl r2~4________________- ,
C7 I C3 I---'---__._-C:> VD1+
PRO 2
Cl/FCO 3
C
U
CS/C2r4~~--------------.
MO
Ml
M2
(f)
U8
CS8402A
22
23
~
()
!;(
5
C9/C15 12
EMO/C9 14
GND
EM1 IC8 13
:.
U7
OSCILLATOR
.--+-------.---<--1 VD2+
MCLK
MCLK n----1--"---l>
+ C22
10mF
16V
Figure 6. CS8402 Digital Audio Interface Connections
TXP
C>--.-----,
,, ,'.
,,
,,
,,
, I
,,
C14
O.lmF
NPO
,..--_1---------
J7
OPTl
SHU-HK313103
"
R32
1 11:~ 4
37V4'V-----------:X:7.FMR-SCHOTT
U4
VDl +
Figure 7. Digital Audio Output Circuit
08112081
3-95
_-_...-.
_.-_..__....-.-.
~
CDB5345
J23
2
U9D
LRCKO
tv~
3
4
5
6
7
SCLK
LCLK
8
10
VD1+
74HC04
SDATA
SDATA
-VD1+
SCLK
-SCLK
0---'
MCLK
L>--~--'
--
74HC243
LRCK~-~--------+-.
UR
MCLK
Figure 8. Serial Output Interface
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+5 ANALOG
input
+5 Volts from analog power supply
AGND
input
analog ground connection from power supply
AINL
input
left channel analog input
AINR
input
right channel analog input
MCLK
output
master clock output
UR
output
left/right channel signal
SDATA
output
serial output data
SCLK
output
serial output clock
DIGITAL OUTPUT
output
CS8402 digital output via transformer
OPTICAL OUTPUT
output
CS8402 Digital output via optical
Table 1. Systems Connections
3·96
05112081
~
~
~ ~
+5~ ~ND
[CDCI
D ----]ZJ
C7CJ)
.--_ _ _ _ _ _---,1 VA1+
gJ
10:'
~
m
!
~
a
~
£
I'. I
ACJ
JI
AINR
~
R7
~w: fio·
2 .. . ItLn
g~l~
UI·
OJ m OJ
CII
..----r----'l t1
D
CIl
CIS
m
L2
~
RIO
gC51
RIB
)C4
rn~
~
D
CRYST AL
Semiconductor Corporation
SMART Anolo
....."
=I~
..:
,
.
Jl7
JJ
.
:0
UII
~
. .
RESET
J2
Evaluation Boord
C20~
i'·'I:
oSClK
.
~
g~
....
.
SI2
PCB5345 REV B
•.
I
~
UI2
R1 R2
o
ue'-----'
sa
wg~
ggD
«(
~.
SPCD
~
CDB5345
C=========:j
VD1+
DGND.
-c:::J-
NWn U
AINL
L/R
~IO
g ~:7 1.'~ ~:
CS
R5
-c=J-
~
-c:::J-c:::J-
HI .. RJI
R32
C14cr::::J
RZZ
-c:::::J-
OPTICALQ
OUTPUT
Ir::ll
~
OPT!
H
J7
.
DIGITAL
OUTPUT
Ir::ll
MCLK
.
~
. SILKSCREEN- TOP
I
o
c
m
U1
Co)
~
.._-_
_.-_..--_._.
__
...-.
CDB5345
Component Side Layer (NOT TO SCALE)
3-98
OS112081
----------------------
CDB5345
Solder Side Layer (NOT TO SCALE)
D8112D81
3-99
._.-.
._.-_..-.,--_.._-_
...
CDB5345
• Notes.
3-100
DS112D81
......... ......
.......
~
""'"
.",.",
~.,~~
CS5349
Semiconductor Corporation
Single Supply, Stereo AID Converter for Digital Audio
Features
General Description
•
•
The CS5349 is a complete analog-to-digital converter
which operates from a single +5V supply. It performs
sampling, analog-to-digital conversion and anti-aliasing
filtering, generating 16-bit values for both left and right
inputs in serial form. The output word rate can be up to
50 kHz per channel.
•
•
•
•
•
•
Single +5 V Power Supply
Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference
Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
90 dB Dynamic Range
Internal 64X Oversampling
Linear Phase Digital Anti-Alias Filtering
0.01 dB Passband Ripple
80dB Stopband Rejection
Low Power Dissipation: 300 mW
Power-Down Mode for Portable
Applications
Evaluation Board Available
VREFIN
IClKA
APD
The ADC uses delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5349 has an SCLK which clocks out data on
falling edges and a filter passband of dc to 24 kHz.
The filter has linear phase, 0.01 dB passband ripple,
and >80 dB stopband rejection.
The device is available housed in a 0.6" wide 28-pin
plastic DIP, and also in a 0.3" wide 28-pin sOle surface mount package.
ORDERING INFORMATION:
ACAl
OClKD
IClKD FSYNC
SClK
Page 3-121
UR
VREFOUT
SDATA
CMODE
'------.,.----~__<.J SMODE
AINl+
AINl-
:11
TST
AINR+
AINR-
'8
NC
,22
AGND
NC
19
VA+
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
lGND
Vl+
DCAl
DPD
VD+
DGND
APR '92
DS73F1
3~101
~==~":'=;
....
.,_ .....
, CS~349
'>
ANALOG CHARACTERISTICS (TA = 25°C for K grade, TA = ,-40"C to t85 °C for'B grade;VA+,
Vl+,VD+ = 5V;Full-Si:ale Input Sinewave, 1kHz; Output word rate 48 kHz; SClK == 3.072 MHz; Source 1m"
pedance = 1000 With 500 pF across AIN+, AIN-; VREFIN connected to VREFOUT; DCAl COIinected to ACAl;
Master Mode; Measurement Bandwidth is 10 Hz to 20 kHz; unless otherwise specified.)
='
Parameter"
CS5349-K
Symbol
Specified Temperature Range
Min
TA
Typ
Max
Ot070
-
-
88
90
85
87
-
86
S/(N+D)
84
THD
-
0.001
0.005
0.0001
100
-
-
-
0.05
-
Dynamic Performance
. 16
Units
°C
-
-
Bits
90
-
dB
87
0.001
0.005
%
0.0001
-
Degrees
.'
Dynamic Range
Signal-tp-(Noise+Distortion) THD+N
Yin
=-10 dB, 1kHz
Interchannel Phase Deviation
Interchannel Isolation
CS5349-B
Typ
Max
-40 to +85
16
Resolution
Total Harmonic Distortion
Min
(dc to 20 kHz)
"
dB
100
-
dB
-
0.05
-
dB
±2
dcAccuracy
Interchannel Gain Mismatch
(After Calibration)
-
(ACAL Low)
-
Gain Error
Gain Drift
Bipolar Offset Error
Offset Calibration Range
±2
±5
±5
%
50
.-
-
50
ppm/oC
±3
±10
±3
±10
LSB
±100
-
-
-
±100
-
mV
Analog Input
Differential Input Voltage Range
(Full Scale) (Note 1)
VIN
3.8
4.0
-
3.8
4.0
-
Vpp
Input Impedance
ZIN
-
50
-
-
50
-
kQ
Power Supplies
Power Supply Current
with APD, DPD low
(Normal Operation)
(VA.t)+(VL+)
VD+
IA+
ID+
-
30,
35
40
45
-
30
35
40
45
mA
mA
Power Supply Current
with APD, DPD high
(Power-Down Mode)
(VA+)+(VL+)
VD+
IA+
ID+
-
10
100
-
-
10
100
-
jlA
jlA
(APD, DPD Low)
(APD, DPD High)
PDN
PDS
-
325
0.5
425
-
325
0.5
425
mW
mW
Power Dissipation
Power Supply Rejection Ratio
(dc to 26 kHz)
(Note 2)
(26 kHz to 3.046 MHz)
Notes:
PSRR
-
50
90
-
-
50
90
-
dB
dB
1. Input voltage range is equal to ±{(VA+)-VREFIN}xO.8. (See Figure in Analog Connection Section)
• Refer to Parameter Definitions at the end of this data sheet.
Specifications are subject to change without notice.
3-102
DS73F1
----------- -----------
CS5349
DIGITAL FILTER CHARACTERISTICS
(TA = 25 D C', VA+ , VL+ ,VD+ = 5V -+ 5%', Output word rate of 48 kHz)
Parameter
Symbol
Min
Typ
Max
Units
0
0
to
to
24
22
kHz
kHz
Passband Ripple
-
-
±0.Q1
dB
Stopband
28
to
3044
kHz
80
-
-
-
dB
18/0WR
-
0.0
us
Passband
(-3 dB)
(-0.01 dB)
Stopband Attenuation
(Note 2)
Group Delay (OWR = Output Word Rate)
tgd
Group Delay Variation vs. Frequency
Notes:
6tgd
s
2. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (that is: there is
no rejection for n x 3.072MHz ±22kHz wheren = 0,1,2,3 ... ).
DIGITAL CHARACTERISTICS
TA = 25 DC; VA+, VL+ ,VD+ = 5V ± 5%
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
VIH
70%VD+
-
-
V
Low-Level Input Voltage
VIL
-
30% VD+
V
High-Level Output Voltage at 10 = -20uA
VOH
4.4
-
-
V
Low-Level Output Voltage at 10 = 20uA
VOL
-
-
0.1
V
Input Leakage Current
lin
1.0
-
uA
ABSOLUTE MAXIMUM RATINGS (AGND,
LGND, DGND = OV, all voltages with respect io
ground)
Parameter
DC Power Supplies:
Positive Analog
Positive Logic
Positive Digital
Input Current, Any Pin Except Supplies
Analog Input Voltage
(AIN and VREFIN pins)
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Symbol
Min
Typ
Max
Units
VA+
VL+
VD+
-0.3
-0.3
-0.3
-
V
V
V
lin
-
-
+6.0
(VA+)+0.3
+6.0
±10
mA
VINA
-0.3
-
(VA+)+0.3
V
VIND
-0.3
-
(VD+)+0.3
V
TA
-55
-
+125
DC
Tstg
-65
-
+150
DC
-
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS73F1
3-103
_-_
.. ...
.. _.-.
-.-_
..--_
__
CS5349
SWITCHING CHARACTERISTICS
(TA
=25°C;
VA+, VL+, VD+
=5V ± 5%;
Inputs: Logic 0
=OV; Logic 1 =VA+, VD+;
CL
=20 pF)
Symbol
Min
Typ
Max
Unit
ICLKD Period (CMODE low)
t clkwl
78
·
3906
ns
ICLKD Low (CMODE low)
t clkll
31
t clkhl
·
·
·
·
·
·
ns
31
Parameter
ICLKD High (CMODE low)
t iol
5
ICLKD Period (CMODE high)
ICLKD rising to OCLKD rising (CMODE low)
t clkw2
52
ICLKD Low (CMODE high)
t clkl2
20
ICLKD High (CMODE high)
t ifs2
5
t isclk2
5
·
·
·
·
·
·
·
·
·
t sdo
0
SCLK duty cycle (MASTER mode)
40
SCLK falling to UR (MASTER mode)
t mslr
·20
·
SCLK falling to FSYNC (MASTER mode)
t msfs
·20
SCLK Period (SLAVE mode)
t sclkw
155
SCLK Pulse Width Low (SLAVE mode)
t sclkl
60
·
·
·
SCLK Pulse Width High (SLAVE mode)
t clkh2
20
ICLKD rising or falling to OCLKD rising (CMODE high, Note 3)
t i02
5
ICLKD rising to UR edge (CMODE low, MASTER mode)
t ilrl
5
ICLKD rising to FSYNC edge (CMODE low, MASTER mode)
t ilsl
5
ICLKD rising to SCLK edge (CMODE low, MASTER mode)
t isclkl
5
ICLKD falling to UR edge (CMODE high, MASTER mode)
t ilr2
5
ICLKD falling to FSYNC edge (CMODE high, MASTER mode)
ICLKD falling to SCLK edge (CMODE high, MASTER mode)
SCLK falling to SDATA valid (MASTER mode)
t sclkh
60
SCLK falling to SDATA valid (SLAVE mode)
t dss
UR edge to MSB valid (SLAVE mode)
t Irdss
·
·
Rising SCLK to UR edge delay (SLAVE mode)
t slrl
30
UR edge to rising SCLK setup time (SLAVE mode)
t slr2
30
Rising SCLK to rising FSYNC delay (SLAVE mode)
t sfsl
30
Rising FSYNC to rising SCLK setup time (SLAVE mode)
t sfs2
30
DPD pulse width
tpdw
21clkw
DPD rising to DCAL rising
t pcr
·
DPD falling to DCAL falling (OWR = Output Word Rate)
t pef
Notes:
3-104
3.
ICLKD rising or falling depends on DPD to
UR timing
ns
40
ns
2604
ns
·
·
ns
45
ns
ns
50
ns
50
ns
50
ns
50
ns
50
ns
50
ns
·
50
ns
50
60
%
20
ns
20
ns
·
·
ns
·
·
·
·
·
·
·
·
·
4096
ns
·
ns
50
ns
50
ns
·
·
ns
·
ns
·
·
ns
ns
50
ns
ns
1/0WR
(see Figure 2).
DS73F1
,
.._-_
_.-_..---._.
__
...-.
CS5349
IClkh2 IClkl2
Iclkh Iclkl
I'
'I'
I'
'I
IClKD
IClKD
~
OCLKD
(CMODElow)
_
UR oUlpul
:::::::j
Iclkw1
1
OClKD
(CMODE high)
/..- li01
(MASTER mOde)~Ik----------
lilr1
--t\y
=n
(MASTER mode) ----:::::;f---l~----------lifs1
SCLK oUlpul
(MASTER mode)
i'=:------------
_
,
_
(
/
SCLK oUlpul \
(MASTER mode)
1m sir
X
(MASTER mode)
SClKoutput
(MASTER mode)
------~~'L~----"I
---~'L
t ils2
jo---t-is-cl-k2----
ICLKD to Outputs Propagation Delays (CMODE high)
r
~
tpdw
1
::j
SDATA
t ilr2
-------1-,1
FSYNC output
--01
ICLKD to OUtputs Propagation Delays (CMODE low)
URoutpul
(MASTER mode)
__------1,
JL--
UR output
(MASTER mode)
lisclk1
--J 1:=
1
/..- ti02
~~~~---------
FSYNC oUlpul
tclkw2
-J-{,--------1h\L-
tpcl
1:= Isdo
C
1:=
C
1
-J
DPD
I msfs
FSYNC oUlpul
(MASTER mode)
DCAl
\
SCLK to SDATA, LIR & FSYNC - MASTER Mode
Power Down & Calibration Timing
SCLK inpul
(SLAVE mode)
1
UR input
(SLAVE mode)
_ _ _=---.i~Fllrdss
____X
SDATA
-.,
r
I sclkw
_--~/~------~~~
MSB
----I
r.=
Idss
~
SCLK to L/R & SDATA - SLAVE mode, FSYNC high
t s fs1
SCLKinpul
(SLAVE
mode)
r+ '
sfs21
~~
1
FSYNC inpul
(SLAVE mode)
SDATA
MSB
~
FSYNC to SCLK - SLAVE Mode, FSYNC Controlled.
DS73F1
3-105
-
----------------------
CS5349
RECOMMENDED OPERATING CONDITIONS
(AGND, LGND, DGND = OV; all voltages with respect to ground)
Parameter
DC Power Supplies:
Positive Digital
Positive Logic
Positive Analog
Differential Analog Input Voltage
Symbol
Min
Typ
Max
Units
(Note 5)
VD+
VL+
VA+
4.75
4.75
4.75
5.0
5.0
5.0
5.25
VA+
5.25
V
V
V
(Note 6)
VAIN
3.8
4.0
-
Vpp
VBIAS
-
0.5VA+
-
V
Analog Input Bias Voltage
Notes:
5. VD+ must be within 0.3V of VA+.
6. The output codes will clip at full scale with input signals >4Vpp, but <8Vpp. Input signals >8Vpp will
cause indeterminate output codes. These voltages are subject to the gain error tolerance specification.
Additional tag bits are output to indicate a near to clipping and overdrive condition.
I-~--
I
t
Ferrite Bead
...---......- -......--<.. +5V Digital
O.IIlF
V V
=:s=
+=:S=IIlF
VA+
18
24
VL+
VD+
VREFOUT
Power Down
& Calibrate
Control
APD
DPD
3
,.l
t
O.1IlF
4
26
O.IIlF
=r:::
5H1
ACAL
VREFIN
DCAL
SMODE
CMODE
CS5349
AID CONVERTER
681lF
A*
B*
C*
0*
>-1
>-1
>-1
>-1
AINL+
+
loon
+
loon
+
100n
+
loon
2 AINL·
500pF
NP028
AINR+
SDATA
UR
E F G H
ICLKD
OCLKD
ICLKA
* For best performance, A and B (and C and D)
should be differentially driven. For single ended
use, either A or B (&C or D) can be grounded.
Timing
SCLK
FSYNC
27 AINR·
500pF
NPO
14
NC
NC
Logic
17
& Clock
20
21
23
8
22
t
EITHER connect VD+
to +5V digital logic supply
(do not use ferrite bead)
OR derive VD+ from VA+
via ferrite bead. In this
case, do not drive any
other logic from VD+.
An example ferrite bead
is Permag VK200-2.5/52
Figure 1. Typical Connection Diagram
3·106
DS73F1
......
_-_..._.-.
.-_
_
..-__
CS5349
GENERAL DESCRIPTION
SYSTEM DESIGN
The CS5349 is a 16-bit, 2-channel AID converter
designed specifically for stereo digital audio applications that require a single +5V supply. The
device uses two one-bit delta-sigma modulators
which simultaneously sample the analog input
signals at a 64 X sampling rate. The resulting
serial bit streams are digitally filtered, yielding
pairs of 16-bit values. This technique yields
nearly ideal conversion performance independent
of input frequency and amplitude. The converters do not require difficult-to-design or
expensive anti-alias filters, and do not require
external sample-and-hold amplifiers or a voltage
reference.
Very few external components are required to
support the ADC. Normal power supply decoupling components, voltage reference bypass
capacitors and a resistor and capacitor on each
input for anti-aliasing are all that's required, as
shown in Figure 1.
An on-chip voltage reference provides for a differential input signal range of 4Vpp. Any zero
offset is internally calibrated out during a powerup self-calibration cycle. Output data is available
in serial form, coded as 2's complement 16-bit
numbers. Typical power consumption of only
300 mW can be further reduced by use of the
power-down mode.
For more information on delta-sigma modulation
and the particular implementation inside this
ADC, see the references at the end of this data
sheet.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter, and is used to generate the
modulator sampling clock. ICLKD frequency is
determined by the desired Output Word Rate
(OWR) and the setting of the CMODE pin.
CMODE high will set the required ICLKD frequency to 384 X OWR, while CMODE low will
set the required ICLKD frequency to 256 X
OWR. Table 1 shows some common clock frequencies. The digital output clock (OCLKD) is
always equal to 128 X OWR, which is always
2 X the input sample rate. OCLKD should be
connected to ICLKA, which controls the input
sample rate.
The phase alignment between ICLKD and
OCLKD is determined as follows: when
o
1
234
5
6
7
ICLKD
Input
OCLKDI
UR
CMODE
(kHz)
ICLKD
(MHz)
ICLKA
(MHz)
SCLK
(MHz)
DPD
Input
UR
Input
32
low
8.192
4.096
2.048
32
high
12.288
4.096
2.048
OCLKD
Output
44.1
low
11.2896
5.6448
2.8224
Input
44.1
high
16.9344
5.6448
2.8224
48
low
12.288
6.144
3.072
48
high
18.432
6.144
3.072
Table 1. Common Clock Frequencies
UR
••• 1
---
1
I
2
OCLKD 2
Output
• DPD low is recognized on the next ICLKD rising edge
(#0) _
•• UB. rising before ICLKD rising #2 causes OCLKD -1
.~. UR rising after ICLKD rising #2 causes OCLKD - 2
Figure 2. ICLKD to OCLKD Timing with CMODE
high (384 X OWR)
DS73F1
3-107
..--"""'
_.--..__.....
..._.-.
.."
-
UR
Output
C$5349··
~~--~---.----~
.
J
16 17 18 19
20 21
I
~31
~
I
0
1
2
3
I~--------~~
~
SCLK
Output
FSYNC
Output
SDATA
Output
15
Left Audio Data
Tag Bits
Left Data Tag
Right Audio Data
Tag Bits
Right Data Tag
Figure 3. Data Output Timing - MASTER mode
;-----------------c~
~
.
I II
LJR
Input
~ 30 31
0
1
2 ~-----------------i
SCLK
Input
FSYNC
Input (high)
SDATA
Output
.1.
Left Audio Data
Tag Bits
Left Data Tag
Right Audio Data
.1
Tag Bits
Right Data Tag
Figure 4. Data Output Timing - SLAVE Mode, F8YNC high
CMODE is low, ICLKD is divided by 2 to generate OCLKD. The phase relationship between
ICLKDand OCLKD is always the same, and is
shown in the Switching Characteristics Timing
Diagrams. When CMODE is high, OCLKD is
ICLKDdivided by 3. There are two possible
phase relationships between ICLKD· and
OCLKD, which depend on the start-up timing
between DPD and LlR, shown in Figure 2.
Serial Data Interface
The serial data output interface has 3 possible
modes of operation: MASTER mode, SLAVE
mode with FSYNC high, .and SLAVE mode with
FSYNC controlled. In MASTER mode, the NO
3-108
converter is driven from a master clock (ICLKD)
and outputs all other clocks, derived from
ICL~ (see Figure 3). Notice the one SCLK cycle delay between LIR edges and FSYNC rising
edges. FSYNC brackets the 16 data bits for each
channel.
In SLAVE mode,LIR and SCLK are inputs.LIR
must be externally derived from ICLKD, and
should.be equal to the Output Word Rate. SCLK
should be equal to the input sample rate, which
is equal to OCLKDI2. Other SCLK frequencies
are possible, but may degrade dynamic range because of interference effects. Data bits are
clocked out via the SDATA pin using the SCLK
DS73F1
----------- -----------
CS5349
---------i~
~
"rq-o--~ ~------------~I
UR
Input
.
~
SCLK
Input
FSYNC
Input
I
SDATA
Output
0
1
,I,
Left Audio Data
1++°1
,I,
Tag Bits
,I,
Left Data
Tag
Right Audio Data
• Rising FSYNC enables
SCLK to clock out SDATA
••
Tag Bits
Right Data
Tag
Falling FSYNC stops SCLK from
clocking out SDATA
Figure 5 Data Output Timing-SLAVE Mode, FSYNC coutrolled
and LIR inputs. The falling edge of SCLK
causes the ADC to output each bit, except the
MSB, which is clocked out by the LlR edge. As
shown in Figure 4, when FSYNC is high, serial
da~ bits are clocked immediately following the
LlR edge.
In SLAVE mode with FSYNC controlled, as
shown in Figure 5, when FSYNC is low, only
the MSB is clocked out after the LlR edge. With
FSYNC low, SCLK is ignored. When it is desired to start clocking out data, bring FSYNC
Input Level
T2 T1 TO
1.375xFS
1
1
1
1.250 x FS to 1.375 x FS
1
1
0
1.125 x FS to 1.250 x FS
1
0
1
1.000 x FS to 1.125 x FS
1
0
0
-1.006dB to O.OOOdB
0
1
1
-3.060dB to -1.006dB
0
1
0
-6.000dB to -3.060dB
0
0
1
< -6.000dB
0
0
0
FS = Full Scale (OdB) Input
high which enables SCLK to start clocking out
data. Bringing FSYNC low will stop the data being clocked out. This feature is particularly
useful to position in time the data bits onto a
common serial bus.
The serial nature of the output data results in the
left and right data words being read at different
times. However, the words within an LiR cycle
represent simultaneously sampled analog inputs.
In all modes, additional bits are output after the
data bits: 3 tag bits and a left/right indicator. The
tag bits indicate a near-to-clipping input condition for the data word to which the tag bits are
attached. Table 2 shows the relationship between
input level and the tag bit values. The serial bit
immediately following the tag bits is 0 for the
left channel, and 1 for the right channel. The remaining bits before the next LiR edge will be 1's
for the left channel and O's for the right channel.
Normally, the tag bits are separated from the
audio data by the digital signal processor. However, if the tag bits are interpreted as audio data,
their position below the LSB would result as a
very small dc offset.
Table 2. Tag Bit Definition
DS73F1
3-109
...
"
CS5349
Analog Connections
The CS5349 samples the analog inputs at
3.072 MHz for a 12.288 MHz ICLKD (CMODE
low). The digital filter rejects all noise between
28 kHz and (3.072 MHz-28 kHz). However, the
filter will not reject frequencies right ar()und
3.072 MHz (and multiples of 3.072 MHz). Most
audio signals do not have significant energy at
3.072 MHz. Nevertheless, a 100 Q resistor in series with the analog input, and a 500 pF NPO or
COG capacitor across the inputs will attenuate
any noise energy at 3.072 MHz, in addition to
providing the optimum source impedance for the
modulators. The use of capacitors which have a
large voltage coefficient (such as general purpose
ceramics) should be avoided since these will degrade signal linearity. If active circuitry precedes
the ADC, it is recommended that the above RC
filter is placed between the active circuitry and
the ~INR and AINL pins. The above example
frequencies scale linearly with output word rate.
Figure 1 shows the analog input connections.
The analog inputs are presented differentially to
the modulators via the AINR+, AINR- and
AINL+, AINL- pins. Each analog input will accept a maximum of 2 Vpp centered at +2.5 V.
The + and - input signals are 180 out of phase
resulting in an effective input voltage of 4 Vpp.
Figure 6 shows the input signal levels for full
scale.
0
+3.SV
CSS349
-~--
+2.SV
--
+1.SV
+3.S V
---
+2.SV
--
+1.SV
-
.
-
-
-
-
"---
AIN+
-~---
--
AIN--
-
VREFOUT
VREFIN
+2.SV
Full Scale Input level: (AIN+) - (AIN-): 2 Vp or4 vpp
As an altemativeto Figure 1 input arrangements,
Figure 7 shows an active input buffer circuit
which produces a differential output and level
Figure 6. Full Scale Input Voltage
,------------'-----~
H
10 k
10 k
AINL
*
3 U14
+
5 U14
>-----<1>4 G
7
4 LT1013B
~--~+.
LT1013A
n---------~~F
10 k
10 k
AINR
3 U13
--~+
*
Must be driven from
a 10)1'1 impedance,
dc coupled, source
referenced to
°v.
10k
TT
+
47UF
O.l uF
Figure 7. Example Input ButTer Circuit
DS73F1
_.-_..--__...._-_
..._.-.
CS5349
shifts up to +2.5 V. This circuit must be driven
from a source which is referred to OV dc. If this
circuit is used, then the level shifting and AC
coupling components shown in Figure 1 are not
required.
During the offset calibration cycle, the digital
section of the part measures and stores the value
of the calibration input of each channel in registers. The calibration input value is subtracted
from all future outputs. The calibration input
comes from either the analog input signals or by
the value obtained from shorting the differential
inputs together. This input is determined by the
state of the ACAL pin. With ACAL low, the calibration input is obtained from the analog inputs.
With ACAL in a high state, the differential inputs are disconnected from the device input pins
and shorted internally to provide the calibration
input value.
The on-chip voltage reference output (2.5 V) is
brought out to the VREFOUT pin, and normally
connected to VREFlN. External reference voltages between 1.5 V and 3.0 V may be used. A
10 ~F electrolytic capacitor in parallel with a
0.1 ~F ceramic capacitor attached between VREFIN and VA+ eliminates the effects of high
frequency noise. No load current may be taken
from the VREFOUT output pin.
As shown in Figure 8, the DCAL output is high
during calibration, which takes 4096 LIR clock
cycles. If DCAL is connected to the ACAL input, the calibration routine will measure the
voltage resulting from the shorted inputs. Internal offsets of each channel will thus be measured
and subsequently subtracted.
Power-Down and Offset Calibration
The ADC has a power-down mode wherein typical consumption drops to 0.5 mW. In addition,
exiting the power-down state initiates an offset
calibration procedure.
APD and DPD are the analog and digital powerdown pins. When high, they place the analog
and digital sections in the power-down mode.
Bringing these pins low takes the part out of
power-down mode. DPD going low initiates a
calibration cycle. If not using the power down
feature, APD should be tied to AGND. When using the power down feature, DPD and APD may
be tied together if the capacitor on VREF is not
greater than 10 ~F, as stated in the "Power-Up
Considerations" section.
r-DPD
Alternatively, ACAL may be permanently connected low and DCAL utilized to control a
multiplexer which grounds the user's front end.
In this case, the calibration routine will measure
and store not only the internal offsets but also
any offsets present in the front end input circuitry.
During calibration, the digital output of both
channels is forced to a 2's complement zero.
Subtraction of the calibration input from conversions after calibration substantially reduces any
Cal Period
I
(4096
I
(85.33 ms @ 48kHz)
x UR clocks)
--1
I
I
I
Filter Delay_Time
(-40 UR periods)
(-833 us
@
48 kHz)
I~~\,---"
_ _ _ _~l------_
\
Normal Operation
~
I
~~------~~,---l_ _ _ __ _
DCAl
Figure 8. Initial Calibration Cycle Timing
DS73F1
3-111
--------- .... _---------power-on click that might otherwise be experienced. A short delay of approximately 40 output
words will occur following calibration for the
digital filter to begin accurately tracking audio
band signals.
Power-up Considerations
Upon initial application of power to the supply
pins, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
potentially large values of data in· these registers
with the correct values.
The modulators settle very quickly (a matter of
microseconds) after the analog section is powered on, either through the application of power,
or by exiting the power-down mode. The voltage
reference can take a much longer time to reach a
final value due to the presence of large external
capacitance on the VREF pin; allow approximately 5 ms/lJ,F. The calibration period is long
enough to allow the reference to settle for capacitor values of up to 10 IJ,F. If a larger
capacitor is used, additional time between APD
going low and DPD going low should be allowed for VREF settling before a calibration
cycle is initiated.
CS5349
onto the printed circuit board. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor
being the nearest.
The printed circuit board layout should have
separate analog and digital regions and ground
planes, with the ADC straddling the boundary.
All signals, especially clocks, should be kept
away from the VREF pin in order to avoid unwanted coupling into the modulators. An
evaluation board is available which demonstrates
the optimum layout and power supply arrangements, as well as allowing fast evaluation of the
ADC.
To minimize digital noise, connect the ADC
digital outputs only to CMOS inputs.
Synchronization of Multiple CS5349
In systems where multiple ADC's are required,
care must be taken to insure that the ADC internal clocks are synchronized between converters
to insure simultaneous sampling. In the absence
of this synchronization, the sampling difference
could be one ICLKD period which is typically
81.4 nsec for a 48 kHz sample rate.
SLAVE MODE
Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the
recommended power arrangements, with VA+
and VL+ connected to a clean +5 V supply.
VD+, which powers the digital filter, may be run
from the system +5V logic supply, provided that
it is not excessively noisy « ± 50 mV pk-to-pk).
Alternatively, VD+ may be powered from VA+
via a ferrite bead. In this case, no additional devices should be powered from VD+. Analog
ground and digital ground should be connected
together near to where the supplies are brought
3-112
Synchronous sampling in the slave mode is
achieved by connecting all DPD and APD pins
to a single control signal and supplying the same
ICLKD and LtR to all converters.
MASTER MODE
The internal counters of the CS5349 are reset
during DPD/APD high and will start simultaneously by insuring that the release of DPD/APD
for all converters is internally latched on the
same rising edge of ICLKD. This can be
achieved by connecting all DPDIAPD pins to
the same control signal and insuring that the
DS73F1
---------------------DPD/APD falling edge occurs outside a ±30 ns
window either side of an ICLKD rising edge.
CS5349
m
:!:!.
~
~
::;:
Digital Filter
Figures 10 through 12 show the performance of
the digital filter included in the ADC. All the
plots assume an output word rate of 48 kHz. The
filter frequency response will scale precisely
with changes in output word rate. The passband
ripple is flat to ± 0.01 dB maximum. Stopband
rejection is greater than 80 dB. Figure 12 is an
expanded view of the transition band.
I
~
g'
PERFORMANCE
10,---------------------------,
0+----,---;----....- - - - - - - - - - -10
-20
- - - - - - - - - - - - - - - - - - - - -30
-40 - - - ,- - - -,- - - -,.
-50
-60
,
,
,
-70 - - - ,- - - - ,- - - - , -80
-90
,
,
,
-100 - - - - - - - - - - - - '
"
-110
-120
-130 ±-----r----:t::----:::t:-----::I::"-------;140::------;l48"
Input Frequency (kHz)
Figure 10. CS5349 Digital Filter Stopband Rejection
0.020.,------------------------------,
m
:!:!.
~
0.010
- - - ,- - - -,- - - -, - - - -, - - - , - - -
c:
f
-0.010
-0.020+----t------t-----t-----t------t--L..--j
4
12
16
20
24
Input Frequency (kHz)
Figure 11. CS5349 Digital Filter Passband Ripple
0
m
:!:!.
(J)
_
-10
.' __
.'
__
..!
__
L
__
-20
"C
:2c:
-30
-
g' -40
::;:
I
,
"
- - - - - - - - - I
I
,
,
I
,
,
I
I
I
23
24
- - - - - - - - - - -
-50
-- -- -I
"
- ,
- -
-
- - - ,
- - - -
-60
-70
-80
- - - - - - -
-90
-100
22
-
,
I
,
26
27
- - - - - - - -
25
28
29
30
Input Frequency (kHz)
Figure 12. CS5349 Digital Filter Transition Band
DS73F1
3-113
....._.-.--..--_.._-_.
CS5349
-~
Performance Measurements
All the following performance measurements
were taken using an Audio Precision System
One Dual Domain tester. The CS5349 was in a
CDB5349 evaluation board, running at 48 kHz
word rate and interfaced to the System One Via
the AESIEBU input using a CS8402 AESIEBU
transmitter.
F~TLVL(dBFS) & FLTLVL(dBFS)
CRYSTAL FRQRESP
1
'. , I,' ,.,1
, "
,
I
I,
',.,'
I
,
I
'
t,I,I
vs FREQ(Hz)
Ap
1'1,',1,
.5
I
I',
""
0
-.5
-
-1
I
_ ,_,
-,-,-,
~
, ..
I
'r- - -, - ,. .. r-'...,' ..
T'T'.-
-
-1-
l'
I _
...... ' , ' .. ' -
I '
I'
_.
T
_, _
,_ I ...
,1,1,
-
T
_'_,_',
"
_
I
'...,tot __
'..
_
I
-1.5
-2
I
1',1,1,1
, ' I I.',',
I
,
.1
-2.5
Figure 13 shows the frequency response, which
is essentially flat.
I'
.1.1
,f
,
'
••
,1,
-3
-3.5
""""
-4
Figure 14 shows 'the noise floor with zero input
signal level. A 16 K point FFT was used.
'
20
I,'
100
1k
10k
30k
Figure 13. Frequency Response
Figure 15 shows a 1 kHz, -10 dB input signal
FFT plot. Notice the low 2nd harmonic at
-110 dB.
Figure 18 shows THD+N versus frequency, at
-10 dB input. This indicates a value of 90 dB,
with minor degradati!-,n at high frequency.
Figure 16 shows a 1 kHz, -80 dB input signal
FFT plot. Notice the lack of harmonic distortion
components. This is a direct result of the perfect
differential non-linearity, which is one of the
benefits of the delta-sigma technique.
Figure 19 shows the linearity of the CS5349.
The input signal is at 500 Hz and is varied from
o dB (full scale) to -120 dB. At each input
level, the output level is measured and compared
to the perfect value. Any deviation is plotted as
a deviation away from 0 dB. Notice the close
conformance to perfect linearity, until the noise
starts to influence the readings at about -100 dB.
Figure 17 shows the THD+N versus input level
at 1 kHz. This plot indicates a dynamic range of
90 dB, with a small increase in distortion with a
full scale' input.
Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
3-114
DS73F1
.._-_
_.-_..--_._.
__
...-.
CRYSTAL NOISE
0
CS5349
AMP1(dBFS)
vs FREQ(Hz)
,lip
CRYSTAL THDNAMP
-60
FlTlVl(dBFS)
vs
AMPl(dBr)
,lip
""
-20
-, -, '-",'-
,-,,-,
-40
,- ',i,
-,
-70
"-"
-,-
-80
-,-
-,-
,-
-60
-90
,1,1
-80
,
-100
,.,'
~
,
,I,.
1,1,
.!'.'.'
-100
"_,1
J
-110
-120
-140
10
100
1k
10k
20k
-120
-120
Figure 14 Noise Floor
CRYSTAL 1KM10DB
vs
FREQ(Hz)
, "",
,- ,-,
,
-60.0
-20.0
-40.0
-,
-,
FlTlVl(dBFS)
CRYSTAL THDNFRQ
-60
0.0
,-,I
"
vs
FREQ(Hz)
,lip
,I,',
,lip
-20
-40
-80.0
Figure 17. THD+N vs Input level at 1 kHz
AMP1(dBFS)
o
-100
-70
~
~
-80
,,
-'
,
-, ,-
~
'-
,
,- ,-
,
~
,,
-60
'-
-80
,
-100
c
"
"
~
:
,,
"
~
-90
,
",
J
",
-,
-120
-' _1'-
-100
~
~
~
~
,,
-110
,,
,-
,
,,
-120
-140
10
1k
100
10k
20k
Figure 15. 1 kHz, -10 dB input FFT
CRYSTAL 1KM80DB
AMP1 (dBFS)
o
vs
10k
1k
100
50
20k
Figure 18. THD+N vs Frequency at -10 dB
FREQ(Hz)
'"
FlTlVl(dBFS)
CRYSTAL ADLIN
10
vs
AMPl(dBr)
,lip
,lip
-20
6
-40
,-
-60
,- -,
, -, ,
4
2
,-
,
-80
,
-100
c
:
,
,,
'~
-'
-2
-4
'-
~
-
-
_1-
-6.
-120
-8.
-140
10
1k
Figure 16. 1 kHz, -80 dB input FFT
DS73F1
10k
20k
-10
-120
-100
-80.0
-60.0
-40.0
-20.0
0.0
Figure 19. Output level Error vs. Input level at 500 Hz
3-115
.-_
..--_._.
__.._-_
...-.
CS5349
PIN DESCRIPTIONS
+ LEFT CHANNEL ANALOG INPUT AINL+
- LEFT CHANNEL ANALOG INPUT AINLVOLTAGE REFERENCE INPUT VREFIN
POSITIVE ANALOG POWER
VA+
ANALOG GROUND AGND
ANALOG POWER DOWN INPUT
APD
ANALOG CALIBRATE INPUT ACAL
NO CONNECT
NC
DIGITAL CALIBRATE OUTPUT DCAL
DIGITAL POWER DOWN INPUT
DPD
TEST
TST
SELECT CLOCK MODE CMODE
SELECT SERIAL 1/0 MODESMODE
LiR"
LEFTIRIGHT SELECT
AINR+ + RIGHT CHANNEL ANALOG INPUT
AINR- - RIGHT CHANNEL ANALOG INPUT
VREFOUT VOLTAGE REFERENCE OUTPUT
LGND ANALOG SECTION LOGIC GROUND
VL+
ANALOG SECTION LOGIC POWER
ICLKA ANALOG SECTION CLOCK INPUT
NC
NO CONNECT
OCLKD DIGITAL SECTION OUTPUT CLOCK
ICLKD DIGITAL SECTION CLOCK INPUT
DGND DIGITAL GROUND
VD+
DIGITAL SECTION POSITIVE POWER
FSYNC FRAME SYNC SIGNAL
SDATA SERIAL DATA OUTPUT
SCLK SERIAL DATA CLOCK
Power Supply Connections
VA+ - Positive Analog Power, PIN 4.
Positive analog supply. Nominally +5 volts.
VL+ - Positive Logic Power, PIN 24.
Positive logic supply for the analog section. Nominally +5 volts.
AGND - Analog Ground, PIN 5.
Analog ground reference.
LGND - Logic Ground, PIN 25
Ground for the logic portions of the analog section.
VD+ - Positive Digital Power, PIN 18.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, PIN 19.
Digital ground for the digital section.
Analog Inputs
±AINL, ±AINR - Differential Left and Right Channel Analog Inputs, PINS 1,2,27,28
Analog input connections for the left and right input channels. Nominally 4Vpp full scale.
VREFIN - Voltage Reference Input, Pin 3
Normally tied to VREFOUT for 4Vpp differential input levels.
3-116
DS73F1
.._-_
.-_
_
..--_._.
__
...-.
CS5349
Analog Outputs
VREFOUT - Voltage Reference Output, PIN 26.
Nominally +2.5 volts. Must be bypassed to VA+ with a 0.1 !1F ceramic capacitor in parallel
with a 10 IlF electrolytic capacitor. Normally connected to VREFIN.
Digital Inputs
ICLKA - Analog Section Input Clock, PIN 23.
This clock is internally divided by 2 to set the modulators' sample rate. Sampling rates, output
rates, and digital filter characteristics scale to ICLKA frequency. ICLKA frequency is 128 X the
output word rate. For example, a 6.144 MHz ICLKA corresponds to an output word rate of 48
kHz per channel. Normally connected to OCLKD.
ICLKD - Digital Section Input Clock, PIN 20.
This is the clock which runs the digital filter. ICLKD frequency is determined by the required
output word rate and by the CMODE pin. If CMODE is low, ICLKD frequency should be
256 X the desired output word rate. If CMODE is high, ICLKD should be 384 X the desired
output word rate. For example, with CMODE low, ICLKD should be 12.288 MHz for an output
word rate of 48 kHz. This clock also generates OCLKD, which is always 128 X the output
word rate.
APD - Analog Power Down, PIN 6.
Analog section power-down command. When high, the analog circuitry is in power-down
mode. APD is normally connected to DPD when using the power down feature. If power down
is not used, then connect APD to AGND.
DPD - Digital Power Down, PIN 10
Digital section power-down command. Bringing DPD high puts the digital section into
power-d~n mode. Upon returning low, the ADC starts an offset calibration cycle. This takes
4096 LIR periods (85.33 IDS with a 12.288 MHz ICLKD). DCAL is high during the calibrate
cycle and goes low upon completion. DPD is normally connected to APD when· using the
power down feature. A calibration cycle should always be initiated after applying power to the
supply pins.
ACAL - Analog Calibrate, PIN 7.
Analog section calibration command. When high, causes the left and right channel modulator
differential inputs to be shorted together. May be connected to DCAL.
CMODE - Clock Mode Select, PIN 12.
CMODE should be tied low to select an ICLKD frequency of 256 X the output word rate.
CMODE should be tied high to select an ICLKD frequency of 384 X the output word rate.
DS73F1
3-117
___,,_J-__
----.-----------
CS5349
SMODE - Serial Interface Mode Select, PIN 13.
S~ODE should be tied high to select serial interface master mode, where SCLK, FSYNC and
LIR are all outputs, generated by internal dividers operating from ICLKD. ~MODE should be
tied low tosel~t serial interface slave mode, where SCLK, FSYNC and LIR are all inputs. In
slave mode, LIR, FSYNC and SCLK need to be derived from ICLKD using external dividers.
Digital Outputs
SDATA - Serial Data Output, PIN 16.
Audio data bits are presented MSB first, in 2's complement format. Additional tag bits, which
indicate input overload and left/right channel data, are output immediately following each audio
data word.
DCAL - Digital Calibrate Output, PIN 9.
DCAL rises l!nmediately upon entering the power-down state (DPD brought high). It returns
low 4096 LlRperiods after leaving the power down state (DPD brought low), indicating the
end of the offset calibration cycle (which = 85.33 ms with a 12.288 MHz ICLKD). May be
connected to ACAL.
OCLKD - Digital Section Output Clock, PIN 21.
OCLKD is always 128 X the output word rate. Normally connected to ICLKA.
Digital Inputs or Outputs
SCLK - Serial Data Clock, PIN 15.
Data is clocked out on the falling edge of SCLK
In master mode (SMODE high), SCLK is a continuous output clock at 64 X the output word
rate.
In slave mode (SMODE low), SCLK is an input, which requires a clock at any frequency from
32 X to 128 X the output word rate. (64 X is preferred). When FSTIiC is high, SCLK clocks
out serial data, except for the MSB Which appears on SDATA when LIR changes.
LIR - LeftlRight Select, PIN 14.
In,.!llaster mode (SMODE high), LIR is an output whose freI LINE DRIVER f----4I.
MAY'91
DS73DB1
3-122
PARALLEL
OUTPUT
DATA
DIGITAL
AUDIO
DATA
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
_.-_..--_._.
__.._-_
...-.
CDB5349
Power Supply Circuitry
The schematic diagram in Figure I shows the
evaluation board power supply circuitry. Power
is supplied to the evaluation board by four binding posts. The +5 Volt analog power supply
input for the converter is provided by the +5V
and AGND binding posts. The +5 Volt digital
supply for the converter and the discrete logic on
the board is provided by the +5V and DGND
binding posts. DI and D2 are transient suppressers which also provide protection from
incorrectly connected power supply leads. C30
provides general power supply filtering for the
analog supply. As shown in Figure 2, CIO and
Cl2 provide localized decoupling for the converter VA+ pin. Space for a ferrite bead inductor,
L1, has been provided so that the board may be
modified to power the converter's VD+ input directly from the VA+ supply. Note that the trace
connecting VD+ to LI must be broken before LI
may be installed. R5 and C7 low-pass filter the
analog logic power supply pin, VL+. The evaluation board uses both an analog and a digital
ground plane which are connected at a single
point by n. This ground plane arrangement isolates the board's digital logic from the analog
circuitry.
Offset Calibration & Reset Circuit
Figure 1, shows the optional offset calibration
circuit provided on the evaluation board. Upon
power-up, this circuit provides a pulse on the
Analog to Digital Converter's DPD pin initiating
an offset calibration cycle. Releasing SWI also
initiates an offset calibration cycle. P6 (see Figure 2) selects the signal source used during
offset calibration. In the "AIN" position, the
AINL and AINR inputs are selected during calibration. In the "ZERO" position, the AINL and
AINR inputs are disconnected and the differential inputs shorted for calibration.
Analog Inputs
As shown in Figure 2, the analog input signals
are connected to the CS5349 via an RC network.
+5V
Analog
AGND
U7E
VD+
AGND
DGND
D3
D1 = P6KE-6V8P from Thomson
+5V
Digital
R26
10k
1 N4148
VD+
~_ _-----4l--_1:....:1-1 II- >o-1:..c:O-----~~--~--~~-*~~VD+
VREF
8
NC
P10
NC
APD 1-'6'----;0-<:>,-,
10 '
DPD I--~I---< Cal
L1
7
v-_...-::-:---=--.., VL+
ACAL
DCAL 1--..------'
VA+
VD+
12
>---~_...------._------1VA+
T
a
CMODE
R7
13
25
11
U1
CS5349
LGND
TST f--Q-----< UR
SDATA
16
AINR+
SDATA 1-----<>--_ SDATA
SCLK
27
AINR-
SCLK
15
SCLK
FSYNC
R3
FSYNC f.'1c:.7__~__-< FSYNC
AINL+
2 AINL-
D
ICLKD
OClKD
21
f.'2::.:0'--...--.ICLKD
IClKA
23
P7
IClKA
, EXT
,...----'D
___ INT
NC
VD+
U3
• Optional
8 12.288 MHz
Oscillator
C14
uF
=:I.Q.1
MCK
8402
VD+
14
Module
o
0.1 uF
EXT
ClKIN
Figure 2. ADC Connections
3-124
DS73DB1
----------------------
CDB5349
R1-R4 and C1-C4 provide anti aliasing and optimum source impedance for the analog input
channels.
high, which selects MASTER timing mode. In
this mode, SCLK, uR and FSYNC are all outputs, generated by the converter from ICLKD.
Figure 3 shows the input buffer circuit. This circuit converts the single ended inputs to
differential, and also elevates the center point of
the differential singles to approximately
+2.5 VThis can be used as an example input
buffer circuit for your application.
Digital Audio Standard Interface
Timing Generator
P7 selects the master clock source supplied to
the ICLKD pin of the converter. As shipped
from the factory, P7 is set to the "INT" position
to select the 12.288 MHz clock signal provided
by U3. An external master clock signal may be
connected to the EXTCLKIN connector and selected by placing P7 in the "EXT" position. Note
that R6, tied between EXTCLKIN and GND, is
available for impedance matching an external
clock source. The board is shipped with SMODE
Included on the evaluation board is a CS8402
Digital Audio Line Driver. This device can implement AES/EBU, S/PDlF and EIAJ-340
interface standards. Figure 4 shows the schematic for the CS8402. P3 allows the C, U and V
bits to be driven from external logic. SW2 provides 8 DIP switches to select various modes
and bits for the CS8402. An output transformer
is included. A position for R20 is included to allow use in the consumer output mode. See the
CS8401 & CS8402 part data sheet for more information on the operation of the CS8402.
Serial Output Interface
The serial output interface is provided by the
SDATA, SCLK, FSYNC and LlR BNC connec,----------------7 A
10k
AINR
~---------+ SDATA
4
~
VD+
B-to-A
Enable
VCC
B1
GND
U9
74HC243
A1
9 B3
A2
6
A4
-
3
B2
4
5
B4
A3
R10
20 k
74HC08
595'5
Figure 5. Serial Output Interface
on the rising edge of SCLK and shifted into the
16-bit shift register formed by U4 and U5 on
SCLK's falling edge, After all data bits for the
selected channel have been shifted into U4 and
U5 the data is latched onto PI by a delayed version of FSYNC,
P5 selects the channel whose output data will be
converted to parallel form and presented on Pl.
With P5 in the "B" (both) position, parallel data
from one channel will be presented first with
data from the other channel presented subsequently. In the "L" (left) position, only left
channel conversions will be presented, while in
the "R" (right) position only right channel conversions are presented.
processor. (Set jumper P2 to the DRDY position.) The fall of DRDY informs the digital
signal processor that a new data word is available. The processor then reads the port and
acknowledges the transfer by asserting DACK.
Note that DRDY will not be asserted again unless DACK is momentarily brought high
although new data will continue to be latched
onto the port.
Two interface mechanisms are provided for reading the data from this port. With the fIrst, the
edges of LlR may be used to clock the parallel
data into the digital signal processor. (Set jumper
P2 into the LlR position.) Alternatively, a handshake protocol implemented with DACK and
DRDY may be used to transfer data to the signal
DS73DB1
3-127
CDB5349
x0 - - - - ,
UR
PIN14
Ul
VD+
~w
VD+
B·
l'
•
R'
, - - 6
FSYNC
PIN17
Ul
5
QH 7
U7C
D
Q
a
3
QG 6
QF 5
R15
VD+
2
U12A
IClKD
PIN20
Ul
JT
QE 4
U4
74HC595 Q D 3
47k
5
10 SRClR
12
Latch ClK
11 ShiftClK
6
ClKI
DIN
14
VD+
QC 2
Qs 1
Q A 15
OE
13
PRE
4
Rll
47k
VD+
U7, p12
VD+
9
13
OEQ
H
7
QG 6
US
QF 5
QE 4
74HC595 QD 3
Qc 2
10 SRClR
12
Qs 1
latch ClK
11 ShiftClK
Q A .15
DIN
14
SDAT
3
2
ClR
ClK
U6A
74HC74
D
PRE
5
Q
ClR
8
4
47k
Rll
VD+
Figure 6. Parallel Output Interface
3-128
DS73DB1
---------------------CONNECTOR
CDB5349
INPUT/OUTPUT
+5 ANALOG
input
SIGNAL PRESENT
+5 Volts from analog power supply
AGND
input
analog ground connection from power supply
+5 DIGITAL
input
+5V digital supply for ADC VD+ and discrete logic
DGND
input
digital ground connection from power supply
AINL
input
left channel analog input
AINR
input
right channel analog input
EXTCLKIN
input
external master clock input
UR
SDATA
output/input
left fright channel signal
output
serial output data
SCLK
output/input
serial output clock
FSYNC
output/input
data framing signal
output
CS8402 digital output via transformer
DIGITAL OUTPUT
P3
output/input
CS8402 C,U,V inputs; CBL output
P1
output
parallel output data
-
Table 1. Systems Connections
JUMPER
P6
P7
P5
P2
P4
POSITION
PURPOSE
FUNCTION SELECTED
selects signal offset or
AIN
offset cal to signal input
shorted inputs for calibration
ZERO
offset cal to shorted inputs
selects master clock source
forCS5349
'INT
CLKIN provided by U2
EXT
CLKIN provided by EXTCLKIN BNC
selects channel for serial to
parallel conversion
'L
left channel data presented on P5
R
right channel data presented on P5
B
left then right channel data
alternately presented on P5
selects LlR or DRDY as the
output status signal presented
on P1
selects device type
*DRDY
-
LlR
DRDY selected to signal the arrival of
new data for the selected channel
-
LlR selected
5349
Correct SCLK for CS5349
5346
Correct SCLK for CS5346
* Default setting from factory
Table 2. Jumper Selectable Options
DS73DB1
3-12Q
----------------------
CDB5349
Switch#
O=Closed; 1=Open
3
PRO=O
1
CRE
default
0
1
......
............
2,5 .............
default
4
6
default
Local Sample Address Counter & Reliability Flags
Disabled
Internally Generated
C6,C7 - Sample Frequency
1
1
0
0
00 - Not Indicated - Default to 48 kHz
01 - 48 kHz
10 - 44.1 kHz
11 - 32 kHz
1
0
1
0
C1
.........
.....
of 4
bits)
C8,C9,C10,C11 - Channel Mode (1.....
......... .......
0000 - Not indicated - Default to 2-channel
0100 - Stereophonic
,
1
0
.....
",~
EM1, EMO
.. .....
... "
1
1
0
0
C1 - Audio
1 - Non-Audio
C9
.......
...............
o - Normal Audio
1
0
default
8,7
Professional Mode CO=1 (default)
C6,C7
default
.....
Comment
1
0
1
0
........... ...
~.
",.
'""
"."
"
"."
...
...........
... C2,c:~,c:~~~rnph~~is (?of 3 bits)
000 - Not Indicated - default to none
100 - No emphasis
110 - 50/15 J.!s
111 - CCITT J.17
Table 3. Switch Definitions - Professional Mode
3-130
DS73DB1
_.-_..--_._.
__.._-_
...-.
CDB5349
Switch#
O=Closedj 1=Open
3
PRO=1
1,4
............. .........
FC1,FCO
C24,C25,C26,C27
- Sample
Frequency
. .......... ....... ................ "..
.. .... ............ ...... . ,.
0000 - 44.1 kHz
0100 - 48 kHz
1100 - 32 kHz
0000 - 44.1 kHz, CD Mode
"
0
1
0
1
0
0
1
t
2
Coinment
Consumer Mode C1 =0 (Note 1)
C3
.....
5
I·······
....... .... :, ...........
C2
- Copy/Copyright
.............
...... .....
... ...
.....
. . . . . ....
1 - Copy Permitted/Copyright Not Asserted
C15 - Generation Status
C15
Note:
···v····
"
..............
~
'"
..................
o - Definition is based on category code.
1-
C?8,C?~
1
1
0
0
....................
".,.,
o - Copy Inhibited/Copyright Asserted
1
0
8,7
.............
,
000 - None
100- 50/15 I1s
1
0
6
"
C3,C4,C5
-.....................................................................
Emphasis (1 of 3 bits)
.
C2
.......... ..... ,...
,,'
"
....... ..........
1
0
I
,
See CS8402 Data Sheet, App. A
C8-C14 - CategorY
Code (2 of 7
. ....•.................................
........................ .............
1
0
1
0
. .....
0000000 - General
0100000 - PCM encoder/decoder
1000000 - Compact Disk - CD
1100000 - Digital Audio Tape - DAT
1. The evaluation bO!lrd is shipped from the factory in the Professional mode. Changing switch 3 to
open places the CS8402 in ConsiJmer mode; however, the hardware is not set up for consumer
mode. To modify the hardware for Consumer mode, change R19 to 374(1 and add .R20 at 90.9n .
. Then, as shown in the figure below, cut the trace connecting TXN to the transformer, and connect
the transformer side to the ground hole provided. For a full explanation, see the CS8402 data
sheet, Appendix B.
Table 4. Switch Definitions - Consumer Mode
R19
"
TXP 20
374
CS8402
U2
TXN
IIt-<>u
Q-~---::2:-' ~
SCHOTT 67125450
PULSE PE65612
DS73DB1
3-131
-
--------...-------------
CDB5349
Top Ground Plane Layer (NOT TO SCALE)
3-132
DS73DB1
.-------_
..-_
__......._.-
•
CDB5349
•
•
••
•
•••
••
••
•
•
•
••
••
••
••
•••
••
•
••
••
••
•
•
•
?>
<
w
~
l1J
."
m
ru
UJ
u
.ll
•••••••••
• •••••••••••••
•••••••••••••••
••••••••••••••
••
••••••••••••••
••••••••••••••
•••••••••••••••••
••••••••••••••
•••••••••••••• •
•••••••••••••••
•••••••••••••• ••
••••••••••••••
••••••••••••••
•
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••••
••••••••••••••
•
•
Bottom Trace Layer (NOT TO SCALE)
DS73DB1
3-133
~
o
r-:::=
·m
Q
o
'-5.
GNOln
I.I! --,
DGHD
-
-
b:3f~PI+
.
5V:3
,
~RlillJ
'
, ca.
y
DACK
I
II
0'
0,
~
P21
IAI4
IIImY'
LIlI"
I
CD
Be
C21ii;;
~
'"
ii
02
03
O.
lIS
DO
07
08
09
010
011
80 dB stopband rejection.
• Internal 64X Oversampling
• Linear Phase Digital Anti-Alias Filtering
The CS5389 is targeted for the most demanding
professional audio systems requiring wide dynamic
range and low noise and distortion.
• Low Power Dissipation: 550 mW
Power-Down Mode
ORDERING INFORMATION:
Model
Temp. Range Package Type
CS5389-KP
0° to 70°C
28-pin Plastic DIP
• Evaluation Board Available
IClKA
APD
ACAl
FSYNC
OClKD
SClK
UR
VREF+
VREF-
SDATA
CMODE
SMODE
AINlAINl+
Digital Decimation
Filter
AINR-
Digital Decimation
Filter
AINR+
AGND
VA+
VA-
Preliminary Product Information I
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Vl+
lGND
DCAl
DPD
VD+
DGND
This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS87PP2
3-135
----------------------
CS5389
(TA = 25°C; VA+, VL+,VD+ = 5V; VA- = -5V; Fullcscale Input Sinewave, 1kHz; Output word rate = 48 kHz; SCLK = 3:072 MHz; Source Impedance = 390. with 6.8 nF across.
AIN+, AIN-; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Logic 0 OV,
Logic 1 = VD+;
ANALOG CHARACTERISTICS
=
Min
CS5389-K
Typ
Max
Units
18
-
-
Bits
102
104
107
-
dB
dB
-
-100
-84
-44
-82
-42
dB
dB
dB
0.0001
106
120
-
dB
-
0.05
-
dB
±1
±5
%
50
150
ppm/oC
±5
±20
LSB
±50
-
mV
VIN
14.0
14.72
Vpp
ZIN
-
115
-
37.5
37.5
35.0
55
55
50
mA
mA
mA
100
100
100
-
j.lA
(.LA
(.LA
550
1.5
800
mW
mW
Symbol
Parameter
Resolution
Dynamic Performance
Dynamic Range
-
(A-weighted)
Total Harmonic Distortion + Noise
o dB
THD+N
-
-20 dB
-60 dB
Interchannel Phase Deviation
Interchannel Isolation
°
dcAccuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Bipolar Offset Error (After Calibration)
Offset Calibration Range
Analog Input
Full-scale Differential Input Voltage (Note 1)
Input Impedance
Common-Mode Rejection
CMRR
25
kn
dB
Power Supplies
Power Supply Current
with APD, DPD low
(Normal Operation)
(VA+)+(VL+)
VAVD+
IA+
IA10+
Power Supply Current
with APD, DPD high
(Power-Down Mode)
(VA+)+(VL+)
VAVD+
IA+
IA10+
(APD, DPD Low)
(APD, DPD High)
PDN
PDS
Power Consumption
Power Supply
Rejection Ratio
(dc to 28 kHz)
(28 kHz to 3 ..046 MHz)
PSRR
-
-
65
100
-
-
dB
dB
1. Specified for a fully differential input ±{(AINR+)-(AINR-)}.The ADC accepts input voltages up to the
analog supplies (VA+, VA-). Full-scale outputs will be produced for differential inputs beyond VIN.
This value is subject to the gain error tolerance specification
• Refer to Parameter Definitions at the end of this data sheet.
Notes:
Specifications are subject to change without notice
3-136
DS87PP2
--------.",-- -----------
CS5389
DIGITAL FILTER CHARACTERISTICS
(TA = 25°C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%; Output word rate of 48 kHz)
Parameter
Symbol
(-3d B)
(-0.01 dB)
Passband
Passband Ripple
Stopband
Stopband Attenuation
(Note 2)
Group Delay (OWR = Output Word Rate)
Group Delay Variation vs Frequency
Noles:
Min
Typ
Max
Units
0
0
-
24
22
kHz
kHz
-
-
±O.01
dB
28
-
3044
kHz
dB
18/0WR
-
-
0.0
J.ls
80
tgd
~tgd
-
s
2. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are (n x 3.072MHz) ±22kHz, where n = 0,1,2,3 ...
DIGITAL CHARACTERISTICS
(TA = 25°C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)
Symbol
Min
High-Level Input Voltage
VIH
70%VD+
Low-Level Input Voltage
VIL
-
High-Level Output Voltage at 10 = -20 J.lA
VOH
4.4
Low-Level Output Voltage at 10 = 20 J.lA
VOL
-
-
0.1
V
1.0
-
J.lA
Parameter
Input Leakage Current
lin
ABSOLUTE MAXIMUM RATINGS (AGND,
Parameter
DC Power Supplies:
Input Current
Positive Analog
Negative Analog
Positive Logic
Positive Digital
IVA+ - VD+I
IVA+ - VL+I
IVD+ - VL+I
Any Pin Except Supplies
Peak Analog Input Voltage (AINL+/- and AINR +/- pins)
Digital Input Voltage
Ambient Operating Temperature (Power Applied)
Storage Temperature
Typ
Max
Units
-
-
V
-
30%VD+
V
-
V
DGND = OV, All voltages with respect to ground.)
Symbol
Min
Typ
VA+
VAVL+
VD+
-0.3
+0.3
-0.3
-0.3
-
lin
-
VIN
(VA-)-O.4
VIND
-0.3
TA
-55
Tstg
-65
-
Max
Units
+6.0
-6.0
+6.0
+6.0
0.4
0.4
0.4
V
V
V
V
V
V
V
±10
rnA
(VA+)+0.4
V
(VD+)+0.4
V
+125
°C
+150
°C
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS87PP2
3-137
-
_.-_..--_._.
__.._-_
...-.
CS5389
SWITCHING CHARACTERISTICS
=
(TA 25°C; VA+. VL+. VD+
CL 20 pF)
=
= 5V ±5%;
VA-
= -5V ± 5%;
Parameter
Inputs: Logic 0
= OV. Logic 1 = VD+;
Symbol
Min
Typ
Max
Unit
ICLKD Period (CMODE low)
I clkw1
78
ns
I clkl1
31
I clkh1
31
-
ns
ICLKO High (CMODE low)
I i01
5
40
ns
ICLKD Period (CMODE high)
Iclkw2
52
-
3906
ICLKD Low (CMODE low)
ICLKD Low (CMODE high)
I clkl2
20
ICLKD High (CMODE high)
I clkh2
20
ICLKD rising or falling 10 OCLKD rising (CMODE high. Nole 3)
I i02
5
ICLKD rising 10 UR edge (CMODE low. MASTER mode)
I ilr1
5
ICLKD rising 10 FSYNC edge (CMODE low. MASTER mode)
I ifs1
5
ICLKD rising 10 SCLK edge (CMODE low. MASTER mode)
I isclk1
5
ICLKD falling 10 UR edge (CMODE high. MASTER mode)
I ilr2
5
ICLKD falling 10 FSYNC edge (CMODE high. MASTER mode)
I ifs2
5
ICLKD rising 10 OCLKD rising (CMODE low)
ICLKD falling 10 SCLK edge (CMODE high. MASTER mode)
SCLK falling to SDATA valid (MASTER mode)
-
ns
50
ns
50
60
%
-20
20
ns
20
ns
.-
ns
50
ns
50
ns
-
ns
Imsfs
-20
155
SCLK Pulse Widlh Low (SLAVE mode)
I sclkl
60
-
SCLK Pulse Widlh High (SLAVE mode)
I sclkh
60
Rising SCLK 10 rising FSYNC delay (SLAVE mode)
I sfs1
30
Rising FSYNC 10 rising SCLK selup lime (SLAVE mode)
I sfs2
30
OPD pulse widlh
lodw
2 x Iclkw
-
I pcr
-
-
SCLK falling 10 SDATA valid (SLAVE mode)
I dss
UR edge 10 MSB valid (SLAVE mode)
Ilrdss
-
RiSing SCLK 10 UR edge delay (SLAVE mode)
I slr1
30
UR edge 10 rising SCLK selup lime (SLAVE mode)
I slr2 ..
30
3-138
ns
50
40
I sclkw
=OUlpul Word Rale)
ns
50
5
SCLK Period (SLAVE mode)
3.
45
0
SCLK falling 10 FSYNC (MASTER mode)
DPD falling 10 DCAL falling (OWR
ns
I sdo
-
Notes:
ns
-
I isclk2
t mslr
DPD rising 10 DCAL rising
2604 .
-
SCLK duty cycle (MASTER mode)
SCLK falling to UR (MASTER mode)
ns
locf
4096
ns
50
ns
50
ns
50
ns
50
ns
50
ns
ns
ns
ns
ns
ns
ns
1/0WR
-
ICLKDrising or falling depends on DPD to UR timing (see Figure 2).
DS87PP2
---------------------telkh
I'
CS5389
telkl
'I'
'I
JlJUIJ
ICLKD
->I
OCLKD
(CMODElow)
~
--ry
UR output
(MASTER mode) ~~
F tilrt
~
--LJ
UR output
(MASTER mode)
:
,
X
I
ilr2
------+,W
1A
I
F t ilS2
-------L,W
IA
F
t iselk2
ICLKD to Outputs Propagation Delays (CMODE high)
r
~
.
\L-__~/
I
------=-.:i-'F"'Ot-- - - - -
--01
.~
--oJ ~-
1
-------v
---.A-------t----o--
tpdw
1
(MASTER mode)
I
(MASTER mode)
~
U R output
~
tisclk1
ICLKD to Outputs Propagation Delays (CMODE low)
~
I
/.-- t i02
SCLK output
--, F
SCLKoutput
(MASTER mode)
OCLKD
(CMODE
high)
FSYNC output
(MASTER mode) ~--;-_ _ _ _ _ _ _ __
t ilst
SCLK output
(MASTER mode)
telkw2
(MASTER mode)
~
FSYNC output
ICLKD
I--
tcikw
:J i'=
----,......,IC
DPD
J i'=
-------.C
DCAL
tsdo
SDATA
t msls
FSYNC output
(MASTER mode)
SCLK to SDATA, LIR & FSYNC - MASTER Mode
t slrt
tslr2
U
---.J
----
Power Down & Calibration Timing
tselkl tsclkh
I' 'I' 'In
n:
SCLKinput
(SLAVE mode)
\
I
I'
U
~
'I'n 'I
U
/
rtselkw
--=
URinput
(SLAVE mode)
(
---..-J
-J
SDATA
rr=
tlrdss
--.I
r,::::: tdss
SCLK to L/R & SDATA - SLAVE mode, FSYNC high
tslst
SCLKinput
(SLAVE
mode)
FSYNC input
1--+ t SIs21
2!1~
1,-----\-------
(SLAVE mode)
SDATA
MSB
~
FSYNC to SCLK - SLAVE Mode, FSYNC Controlled.
DS87PP2
3-139
_-_
.. ...-.
-.-..--_._.
__
CS53S9
RECOMMENDED OPERATING CONDITIONS
ov, all voltages with respect to ground.)
(AGND, DGND =
Parameter
DC Power Supplies:
Symbol
Min
Typ
Max
VD+
VL+
VA+
VA-
4.75
4.75
4.75
-4.75
5.0
5.0
5.0
-5.0
5.25
5.25
5.25
-5.25
0.4
Positive Digital
Positive Logic
Positive Analog
Negative Analog
IVA+ - VD+I
t
-5V Analog
Y
+5V Analog
~.1
I -
-
-
-
Units
V
V
V
V
V
Ferrite Bead
-~ -
UF 1
-
- - . - - - - - - - + - - - < +5V Digital
0.1 uF
0.1 uF
~
:::r::::
1 uF
17
VA+
VL+
VD+
APD
VREF+
+
2
Power Down
& Calibrate
Control
DPD
100 uF
ACAL
VREF-
DCAL
SMODE
Left Analog Input +
CMODE
3
AINL+
6.8 nF
CS5389
AID CONVERTER
4
SDATA
AINLLeft Analog Input -
UR
SCLK
Right Analog Input +
Logic
26
FSYNC
AINR+
& Clock
ICLKD
6.8nF
OCLKD
25
AINR-
ICLKA
Right Analog Input TST01
TST02
VA- LGND
DGND
AGND
8
TSTO pins should be left
floating, with no trace
21
t
Ferrite bead may
be used if VD+ is
derived from VA+.
If used, do not drive
any other logic
fromVD+.
An example ferrite
bead is Permag
VK200-2.5/52
Figure 1. Typical Connection Diagram
3·140
DS87PP2
.._-_.
_.-_..--_.-.
__
...-
CS5389
GENERAL DESCRIPTION
SYSTEM DESIGN
The CS5389 is an 18-bit, stereo NO converter designed specifically for stereo digital audio
applications. The device uses two one-bit deltasigma modulators which simultaneously sample
the analog input signals at a 64 X sampling rate.
The resulting serial bit streams are digitally filtered, yielding pairs of 18-bit values. This
technique yields nearly ideal conversion performance independent of input frequency and
amplitude. The converter does not require difficult-to-design or expensive anti-alias filters and it
does not require external sample-and-hold amplifiers or voltage references.
Very few external components are required to
support the ADC. Normal power supply decoupiing components, voltage reference bypass
capacitors and a single resistor and capacitor on
each input for anti-aliasing are all that's required,
as shown in Figure 1.
On-chip voltage references provide for a differential input signal range of ± 14.72 volts. Any offset
is internally calibrated out during a power-up selfcalibration cycle. Output data is available in serial
form, coded as 2's complement 18-bit numbers.
Typical power consumption of only 550 mW can
be further reduced by use of the power-down
mode.
For .more information on delta-sigma modulation
techniques see the references at the end of this
data sheet.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter and is used to generate the
modulator sampling clock. The required ICLKD
frequency is determined by the desired Output
Word Rate (OWR) and the setting of the CMODE
pin. CMODE high will set the ICLKD frequency
to 384 X OWR, while CMODE low will set the
ICLKD frequency to 256 X OWR. Table 1 shows
some common clock frequencies. The digital output clock (OCLKD) is always equal to 128 X
OWR. OCLKD should be connected to ICLKA,
which controls the input sample rate.
The phase alignment between ICLKD and
OCLKD is determined as follows: when CMODE
is low, ICLKD is divided by 2 to generate
OCLKD. The phase relationship between ICLKD
and OCLKD is always the same and is shown in
the Switching Characteristics Timing Diagrams.
When CMODE is high, OCLKD is ICLKD di-
OCLKDI
UR
CMODE
(kHz)
ICLKD
ICLKA
SCLK
(MHz)
(MHz)
(MHz)
32
low
8.192
4.096
2.048
32
high
12.288
4.096
2.048
44.1
low
11.2896
5.6448
2.8224
44.1
high
16.9344
5.6448
2.8224
48
low
12.288
6.144
3.072
48
high
18.432
6.144
3.072
Table 1. Common Clock Frequencies
DS87PP2
3-141
----------------------
CS5389
vided by 3. There are two possible phase relationships between 1CLKD and OCLKD, which
depend on the start-up timing between DPD and
uR, shown in Figure 2.
o
2
3
4
5
6
7
ICLKD
Input
DPD
Input
~L-_---'-------'----_ __
LJR
**
Input
OCLKD
Output
LJR
SCLK is ignored with FSYNC low and only the
MSB is clocked out after the uR edge in SLAVE
mode / FSYNC controlled as shown in Figure 5.
Bringing FSYNC high will enable SCLK to clock
data out. This feature is particularly useful to multiplex multiple channels.
2
Input
OCLKD
effects. FSYNC may be high or used to control',
SDATA. With FSYNC high, data bits are clocked
out via the SDATA pin using the SCLK and uR
inputs. The falling edge of SCLK causes the ADC
to output each bit, except the MSB, which is
clocked out by the uR edge, as shown in Figure4.
2
Output
• DP.Q low is recognized on the next ICLKD rising edge (#0)
•• Ufrrising before ICLKD rising #2 causes OCLKD-1
••• UR rising after ICLKD rising #2 causes OCLKD - 2
Figure 2. ICLKD to OCLKD TiIiling with CMODE
high (384XOWR)
Serial Data Interface
MASTER mode and SLAVE mode are the 2 primary modes of operation for the serial data output
interface.
Master Mode
SCLK, uR and FSYNC are outputs derived from
1CLKD in Master mode, Figure 3. Notice the one
SCLK cycle delay between uR edges, SDATA
and FSYNC. FSYNC brackets the 16 most significant data bits.
Certain serial modes align well with various interface requirements. A CS5389 in MASTER mode,
with an inverted LtR signal, generates 12S
(Philips) compatible timing. A CS5389 (with an
inverted SCLK) in SLAVE mode emulates a
CS5326 style interface and also links to a
DSP56000 in network mode.
The serial nature of the output data results in the
left and right data words being read at different
times. However, the words within an uR cycle
represent simultaneously sampled analog inputs.
Analog Connections
Figure 1 shows the analog input connections. The
analog inputs are presented differentially to the
modulators via the AINR+, AINR- and AINL+,
AINL- pins. Each analog input will accept a
maximum of 7.36 Vpp. The + and - input signals
are 1800 out of phase resulting in a differential
input voltage of 14.72 Vpp. Figure 6 shows the
input signal levels for full scale.
Slave Mode
uR,
FSYNC and SCLK become inputs in
SLAVE mode.. uR must be externally derived
from 1CLKD and be equal to the Output Word
Rate. SCLK should be equal to 64 X OWR
though other frequencies are possible but may degrade system performance due to interference
3-142
The analog modulator samples the input at
3.072 MHz (64 x Fs) for an output word rate of
48 kHz. The digital filter will reject signals between 22 kHz and 3.072 MHz - 22 kHz.
However, there is no rejection for input signals
which are ( n x 3.072 MHz) +/- 22 kHz, where
n =0,1,2, ... A 39 n resistor in series with the anaDS87PP2
.-_
_
..-_
__....._-_
..._.-.
CS5389
LJR
Output
SCLK
Output
.'
FSYNC
Output
SDATA
Output
Left Audio Data
Right Audio Data
Figure 3. Data Output Timing· MASTER mode
LJR
Input
1
2
3
4
:-----------'1
15
16 17 18 19
20
SCLK
Input
~
I~
~-----+-----I I
FSYNC
Input
II
I
SDATA
Output
!--~~~+------~
I'
Left Audio Data
Right Audio Data
"I
I
Figure 4. Data Output Timing· SLAVE Mode, FSYNC high
~---~
I
n"
LJR
Input
~
SCLK
Input
J
FSYNC
Input
SDATA
Output
I~
~I II
II
171I
I
I'
0
2
I
15 16
17
~
~
I
I
~
I~ I~'----i ___________~I~
18 19 20
0
mUVUUI I
J1l
I
II I
I
II
~
1--
3
Left Audio Data
0
III
II 171I
~
~
"I
15 16 17 18 19 20
~
III~
~-~II
II
II
~~L-~+_----_~~
11' -----R-i9h-t-Au-d-io-Da-ta----"1
1
I
- Rising FSYNC enables SCLK to clock out SDATA
-- Falling FSYNC stops SCLK from clocking out SDATA
Figure 5. Data Output Timing. SLAVE Mode, FSYNC controlled
DS87PP2
3·143
.-_
..--_._.
__.._-_
...-.
3.6BV
OV
-3.66V
3.6BV
OV
-3.6BV
CS5389
CS53B9
=~
APD and DPD are the analog and digital powerdown pins. When high, they place the analog and
digital sections in the power-down mode wherein
typical power consumption drops to 1.5 mW.
AIN+
-~--
--
--
--
-
AIN-
-
Full Scale Input level= (AIN+) - (AIN-)= 14.72 Vpp
Figure 6. Full Scale Input Voltage
log input and a 6.8 nF NPO or COG capacitor between the inputs will attenuate any noise energy
at 3.072 MHz, in addition to providing the optimum source impedance for the modulators. The
use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be
avoided since these can degrade signal linearity. If
active circuitry precedes the ADC, it is recommended that the above RC ftlter is placed between
the active circuitry and the AINR and AINL pins.
The above example frequencies scale linearly with
output word rate.
The on-chip voltage references are available at the
VREF+ and VREF- pins for the purpose of decoupling only. The circuit traces attached to these
pins must be minimal in length and no load current may be taken from VREF+ or VREF-. The
recommended decoupling scheme, Figure 1, is a
100 p.F electrolytic capacitor across VREF+ and
VREF- and two 0.22 p.F ceramic capacitors connected from VREF+ to GND and VREF- to
GND.
r
Power-Down and Offset Calibration
Cal Period
Bringing DPD low exits power-down and initiates
an offset calibration cycle. During the calibration
cycle, the digital section measures the offset of
each channel and stores a corresponding value in
the calibration registers. This value is subtracted
from future conversions to produce an offset free
conversion. The calibration inputs are obtained
from the analog input pins (ACAL low) or AGND
(ACAL high).
The offsets generated by the input circuitry are included when calibration is performed using the
analog input pins (ACAL low). DCAL should be
used to control a multiplexer which grounds the
user's front-end in this mode. The DCAL output
will remain high for 4096 uR clock cycles during
calibration as shown in Figure 7.
A delay of approximately 50 output words will
occur following calibration for the digital ftlter to
begin accurately tracking audio band signals.
Power-up Considerations
~pon
initial application of power to the supply
pms, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
potentially large values of data in these registers
with the correct values.
~
(4096 x UR clocks)
(B5.33 ms @ 4BkHz)
DPD
~
I
I
I
:
Filter Delay Time
(-50 UR periods)
(-1 ms @ 4B kHz)
Normal Operation
~,..----...,.-----~
DCAl
L -_ _ _ _ _ __
Figure 7. Initial Calibration Cycle Timing
3-144
DS87PP2
---------------------The modulators settle in a matter of microseconds
after the analog section is powered, either through
the application of power or by exiting the powerdown mode. The voltage reference will take a
much longer time to reach a final value due to the
presence of external capacitance on the VREF+
and VREF- pins. A time delay of approximately
10 ms/IJF is required between APD going low and
DPD going low to allow for VREF settling. The
typical connection diagram of Figure 1 requires a
1 second delay.
APD should be tied to AGND if the analog power
down feature is not required. When using the analog power down feature, DPD and APD may be
tied together if the capacitor across VREF+ and
VREF- is not greater than 10 1lF. Figure 17 shows
that a slight increase in distortion will result for
signals below 1 kHz and within 6 dB of fullscale
due to less than optimum VREF decoupling. Figure 17 demonstrates this effect at a -4 dB input
level.
Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the
recommended power arrangements, with VA+,
VA- and VL+ connected to a clean ± 5 V supply.
VD+, which powers the digital filter, may be run
from the system +5V logic supply, provided that
it is not excessively noisy « ± 50 mV pk-to-pk).
Alternatively, VD+ may be powered from VA+
via a ferrite bead. In this case, no additional devices should be powered from VD+. Analog
ground and digital ground should be connected
together near to where the supplies are brought
onto the printed circuit board. Decoupling capacitors should be as near to the ADC as possible,
with the low value ceramic capacitor being the
nearest.
DS87PP2
CS5389
The printed circuit board layout should have separate analog and digital regions and ground planes,
with the ADC straddling the boundary. All signals, especially clocks, should be kept away from
the VREF+ and VREF- pins in order to avoid unwanted coupling into the modulators. The VREF+
and VREF- decoupling capacitors, particularly the
0.22 IJF, must be positioned to minimize the electrical path from VREF+ and VREF- to Pin 1,
AGND. The CDB5389 evaluation board is available which demonstrates the optimum layout and
power supply arrangements, as well as allowing
fast evaluation of the ADC.
To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
Synchronization of Multiple CSS389
In systems where multiple ADC's are required,
care must be taken to insure that the ADC internal
clocks are synchronized between converters to insure simultaneous sampling. In the absence of
this synchronization, the sampling difference
could be one ICLKD period which is typically
81.4 nsec for a 48 kHz sample rate.
SLAVE MODE
Synchronous sampling in the slave mode is
achieved by connecting all DPD pins to a single
control signal and supplying the same ICLKD and
I.JR to all converters.
MASTER MODE
The internal counters of the CS5389 are reset during DPDIAPD high and will start simultaneously
by insuring that the release of DPD for all converters is internally latched on the same rising
edge of ICLKD. This can be achieved by connecting all DPD pins to the same control signal
and insuring that the DPD falling edge occurs
outside a ±30 ns window either side of an ICLKD
rising edge.
3-145
_.-_..--_._.
__.._-_
...-.
,CS5389
PERFORMANCE
0.020~-~--~-~--~-~--~
iil
~
Digital Filter
-40
:2 -50
-60
-70
-80
-90
-100
-110
-120 - - - - - - - - - - - - - - - - - - - - - - - - -130 -t---t-----c1f=6---::2tc"4---::c2---::41::-0--:l48
~:::l
I
,
,
,
~
-20
- -
., -
- .,
~
-30
- -
,-
- -, - - -, - - -, - -
'"
-40
- - - - - - - - - - - - - - -
an input which selects the left or right chan~l for output
on SDATA. The rising edge of LIR starts the MSB of the left channel data. LIR frequency
must be equal to the output word rate.
A~ough the outputs of each channel are transmitted at different times, the two words in an
LIR cycle represent simultaneously sampled analog inputs.
DS87PP2
3-151
--------~-------------
CS5389
FSYNC - Frame Synchronization Signal, PIN 16.
In master mode (SMODE high), FSYNC is an output which goes high coincident with the start
of the fIrst SDATA bit (MSB) and falls low immediately after the sixteenth SDATA audio data
bit.
In slave mode (SMODE low), FSYNC is an input which controls the clocking out of the data
bits on SDATA. FSYNC is normally tied high, which causes the data bits to be clocked out
immediately following LlR transitions. If it is desired to delay the data bits from the uR edge,
then FSYNC must be low during the delay period. Bringing FSYNC high will then en~le the
clocking out of the SDATA bits. Note that the MSB will be clocked out based on the LIR edge,
independent of the state of FSYNC.
Miscellaneous
TST01, TST02 - Test Output, PINS 8,21.
These two pins are bonded out for factory test outputs. They must not be connected to any
external component or any length of PC trace.
3-152
DS87PP2
.-_
_
..--_._.
__.._-_
...-.
CS5389
PARAMETER DEFINITIONS
Resolution - The total number of possible output codes is equal to 2N , where N = the number of bits
in the output word for each channel.
Dynamic Range - Full scale (rms) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth, and with an input signal60dB below full-scale.
Total Harmonic Distortion plus Noise - The ratio of the rms sum of all spectral components over the
specified bandwidth (typically 10 Hz to 20 kHz), excluding signal, to the rms value of the signal.
Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value
of the signal.
Interchannel Phase Deviation - The difference between the left and right channel sampling times.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels.
Gain Error - The deviation of the gain value from the typical number given in the analog specifications table.
Gain Drift - The change in gain value with temperature. Units in ppm/DC.
Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000... 000) from the
ideal.
(112 LSB below AGND). Units in LSBs.
DS87PP2
3-153
--------.,,-- -----------
CS5389
REFERENCES - All, except 1), are reprinted in this data book.
1) "A Fifth~Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range" by I. Fujimori,
K. Hamashita and EJ. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio" by D.R. WeIland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
3) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on
Oversampling Delta Sigma ADC's" by Steven Harris. Paper presented at the 87th Convention of the
Audio Engineering Society, October 1989.
4) " An 18-Bit Dual-Channel Oversampling Delta-Sigma AID Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
3-154
DS87PP2
..,..........
......
.....
~~~.
..,..,
CS5390
~-
Semiconductor Corporation
20-Bit, Stereo AID Converter for Digital Audio
Features
General Description
The CS5390 is a complete analog-to-digital converter for
stereo digital audio systems. It performs sampling, analog-to-digital
conversion
and
anti-alias
filtering,
generating 20-bit values for both left and right inputs in
serial form. The output word rate can be up to 50 kHz
per channel.
• 110 dB Dynamic Range (A-Weighted)
•
THD + N better than -100dB
• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
The CS5390 uses 5th-order, delta-sigma modulation
with 64X oversampling followed by digital filtering and
decimation, which removes the need for an external antialias filter. The ADC uses a differential architecture
which provides excellent noise rejection.
• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
The CS5390 has a filter passband of dc to 21.7kHz. The
filters have linear phase, 0.005 dB passband ripple, and
>100 dB stopband rejection.
• Internal 64X Oversampling
• Linear Phase Digital Anti-Alias Filtering
>1OOdB StopBand Attenuation
0.005dB Passband Ripple
• Low Power Dissipation: 550 mW
Power-Down Mode
The CS5390 is targeted for the highest performance
professional audio systems requiring wide dynamic
range, negligible distortion and low noise. Pin compatibility with the CS5389 allows a simple upgrade path
without hardware changes.
• Pin Compatible with CS5389
ORDERING INFORMATION:
• Evaluation Board Available
IClKA
APD
ACAl
Model
Temp. Range
Package Type
CS5390-KP
0° to 70°C
28-pin Plastic DIP
OClKD
IClKD
FSYNC
VREF+
VREF-
SClK
UR
SDATA
Serial Output Interlace
CMODE
SMODE
AINlAINl+
Digital Decimation
Filter
AINR-
Digital Decimation
Filter
AINR+
AGND
VA+
VA-
Vl+
lGND
DCAl
DPD
VD+
DGND
Preliminary Product Information I This document contains
information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
OCT '93
DS105PP2
3-155
_:
_-_
.. ....-...,.
-.-_
...........
__
CS5390
=
ANALOG CHARACTERISTICS
(TA = 25°C; VA+, VL+,VD+ = 5V; VA- -5V; Full-scale Input Sinewave, 1kHz; Output word rate = 48 kHz; SCLK = 3.072 MHz; Source. Impedance = 39n with 6.8 nF across
AIN+, AIN-; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Logic 0 OV,
Logic 1 = VD+;
=
Parameter
Min
CS5390-K
Typ
Max
Units
20
-
-
Bits
TBD
107
110
-
dB
dB
-
-100
-87
-47
0.0001
-
°
106
120
-
dB
-
0.05
-
dB
±1
±5
%
50
150
ppml?C
±5
±20
LSB
±50
-
mV
VIN
14.0
14.72
-
Vpp
ZIN
CMRR
-
115
-
dB
-
37.5
37.5
35.0
55
55
TBD
rnA
rnA
rnA
-
100
100
100
-
I1A
I1A
I1A
550
1.5
TBD
mW
mW
Symbol
Resolution
Dynamic Performance
Dynamic Range
-
(A-weighted)
Total Harmonic Distortion + Noise
OdB
-20 dB
-60 dB
THD+N
-
Interchannel Phase Deviation
Interchannel Isolation
-
TBD
TBD
dB
dB
dB
dcAccuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Bipolar Offset Error (After Calibration)
Offset Calibration Range
Analog Input
Full-scale Differential Input Voltage (Note 1)
Input Impedance
Common-Mode Rejection
25
-
kn
Power Supplies
Power Supply Current
with APD, DPD low
(Normal Operation)
(VA+)+(VL+)
VAVD+
IA+
IAID+
Power Supply Current
with APD, DPD high
(Power-Down Mode)
(VA+)+(VL+)
VAVD+
IA+
IAID+
(APD, DPD Low)
(APD, DPD High)
PDN
PDS
Power Consumption
Power Supply
Rejection Ratio
(dc to 29 kHz)
(29 kHz to 3.046 MHz)
PSRR
-
65
90
-
dB
dB
Notes:
1. Specified for a fully differential input ±{(AINR+)-(AINR-)}.The ADC accepts input voltages up to the
analog supplies (VA+,YA-). Full-scale outputs will be produced for differential inputs beyond VIN.
This value is subject to the gain error tolerance specification
• Refer to Parameter Definitions at the end of this data sheet.
Specifications are subject to change without notice.
3-156
DS105PP2
----------- -----------
CS5390
DIGITAL FILTER CHARACTERISTICS
= 25°C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%; Output word rate of 48 kHz)
(TA
Parameter
Symbol
(-0.005 dB)
Passband
Passband Ripple
Stopband
Stopband Attenuation
Group Delay Variation vs Frequency
Notes:
Typ
Max
Units
kHz
0
-
21.7
-
-
±0.005
dB
29
-
3043
kHz
dB
J.ls
tgd
-
18/0WR
-
Atgd
-
-
0.0
100
(Note 2)
Group Delay (OWR = Output Word Rate)
Min
s
2. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are (n x 3.072MHz) ±21.7kHz, where n = 0,1,2,3 ...
DIGITAL CHARACTERISTICS
= 25°C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)
(TA
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
VIH
70%VD+
V
VIL
-
30%VD+
V
High-Level Output Voltage at 10 = -20 J.lA
VOH
4.4
-
-
Low-Level Input Voltage
-
V
Low-Level Output Voltage at 10 = 20 J.lA
VOL
-
-
0.1
V
1.0
-
J.lA
Parameter
Input Leakage Current
lin
ABSOLUTE MAXIMUM RATINGS (AGND,
Parameter
DC Power Supplies:
Input Current
Positive Analog
Negative Analog
Positive Logic
Positive Digital
IVA+ - VD+I
IVA+ - VL+I
IVD+ - VL+I
Any Pin Except Supplies
Peak Analog Input Voltage (AINL+I- and AINR +1- pins)
Digital Input Voltage
Ambient Operating Temperature (Power Applied)
Storage Temperature
DGND = OV, All voltages with respect to ground.)
Symbol
Min
Typ
VA+
VAVL+
VD+
-0.3
+0.3
-0.3
-0.3
-
VIN
(VA-)-O.4
VIND
-0.3
-
TA
-55
Tstg
-65
-
lin
-
Max
Units
+6.0
-6.0
+6.0
+6.0
0.4
0.4
0.4
V
V
V
V
V
V
V
±10
mA
(VA+)+O.4
V
{VD+)+O.4
V
-
+125
°C
-
+150
°C
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS105PP2
3-157
----------------------
CS5390
SWITCHING CHARACTERISTICS
(TA = 25°C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V
CL = 20 pF)
± 5%; Inputs: Logic 0 = OV, Logic 1 = VD+;
Symbol
Min
Typ
Max
Unit
ICLKD Period (CMODE low)
Parameter
I clkw1
78
390.6
ns
ICLKD Low (CMODE low)
I clkl1
31
I clkh1
31
-
ns
ICLKD High (CMODE low)
I i01
5
40
ns
ICLKD Period (CMODE high)
Iclkw2
52
260.4
ns
ICLKD Low (CMODE high)
I clkl2
20
I clkh2
20
-
ns
ICLKD High (CMODE high)
ICLKD rising or falling 10 OCLKD rising (CMODE high, Nole 3)
I i02
5
45
ns
ICLKD rising 10 UR edge (CMODE low, MASTER mode)
lilr1
5
50
ns
ICLKD rising 10 FSYNC edge (CMODE low, MASTER mode)
I ifs1
5
50
ns
ICLKD rising 10 SCLK edge (CMODE low, MASTER mode)
t isclk1
5
50
ns
ICLKD falling 10 UR edge (CMODE high, MASTER mode)
I ilr2
5
50
ns
ICLKD falling 10 FSYNC edge (CMODE high, MASTER mode)
I ifs2
5
50
ns
I isclk2
5
-
50
ns
I sdo
0
-
50
hs
40
50
60
%
I mslr
-20
20
ns
20
ns
-
ns
50
ns
50
ns
-
ns
ICLKD rising 10 OCLKD rising (CMODE low)
ICLKD falling 10 SCLK edge (CMODE high, MASTER mode)
SCLK falling to SDATA valid (MASTER mode)
SCLK duly cycle (MASTER mode)
UR edge to MSB valid (SLAVE mOde)
Ilrdss
-
Rising SCLK 10 UR edge delay (SLAVE mode)
I slr1
30
UR edge 10 rising SCLK selup lime (SLAVE mode)
I slr2
30
-
Rising SCLK 10 rising FSYNC delay (SLAVE mode)
I sfs1
30
-
Rising FSYNC to rising SCLK selup lime (SLAVE mode)
I sfs2
30
DPD pulse widlh
lodw
2 x Iclkw
DPD rising 10 DCAL rising
I pcr
-
-
SCLK falling 10 UR (MASTER mode)
SCLK falling 10 FSYNC (MASTER mode)
I msfs
-20
SCLK Period (SLAVE mode)
I sclkw
155
SCLK Pulse Widlh Low (SLAVE mode)
I sclkl
60
SCLK Pulse Widlh High (SLAVE mode)
I sclkh
60
SCLK falling 10 SDATA valid (SLAVE mode)
DPD falling 10 DCAL falling (OWR
Notes:
3-158
3.
=Oulpul Word Rale)
ICLKD rising or falling depends on DPD to
I dss
locf
4096
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/0WR
UR timing (see Figure 2).
DS105PP2
---------------------tclkh
I'
CS5390
telkl
'I'
telkh2 telkl2
~
I--
ICLKD
~
URoutput
~
(MASTER mode) ~~
F t ilrt
SCLK output
(MASTER mode)
UR output
FSYNC output
----::::;I--l~-;---------
t i/s1
-----t-w
(MASTER mode)
SCLK output
-----L.A
(MASTER mode)
~ tisclk1
---:
OCLKD
(CMODE high)
~
I \
I.- t i02
I/
.
'------~
:
%
(MASTER mode) -------.=:fI--1Fc:t-i,r2-----
---r-y
FSYNC output
(MASTER mode)
ICLKD
telkw
---01
OCLKD
(CMODElow)
I'
'I
ICLKD to Outputs Propagation Delays (CMODE low)
------~W
I
fi..
I
fi..
---01
F
I F t i/S2
--------'--,'11
tiselk2
ICLKD to Outputs Propagation Delays (CMODE high)
r
SCLKoutput
~ , .
~
(MASTER mode)
~
~
-J t=
U R output
(MASTER mode)
I
------v
~'---------r-----;'----
I
:J t= tsdo
C
-----.---1
SDATA
t=
- - - --.JC
DPD
t ms/s
FSYNC output
(MASTER mode)
SCLK to SDATA, LIR & FSYNC - MASTER Mode
SCLKinput
(SLAVE mode)
tslr1 tslr2
I
'I
'II:
I'
---.J
U
Power Down & Calibration Timing
tselkl tselkh
'I'
'I
I'
'II 'II /
U
U
~
I
rtsclkw
==
UR input
(
(SLAVE mode) ~
-J r,= tlrdss
SDATA
DCAL
~
r,=: tdss
SCLK to LlR & SDATA - SLAVE mode, FSYNC high
ts/s1
SCLKinput
(SLAVE
mode)
FSYNC input
(SLAVE mode)
SDATA
r+
tS/s21
~~
1-----+-----.
MSB
~
FSYNC to SCLK - SLAVE Mode, FSYNC Controlled.
DS105PP2
3-159
----------------------
CS5390
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = OV, all voltages with respect to ground.)
Parameter
DC Power Supplies:
Symbol
Min
Typ
Max
VD+
VL+
VA+
VA-
4.75
4.75
4.75
-4.75
5.0
5.0
5.0
-5.0
5.25
5.25
5.25
-5.25
0.4
Positive Digital
Positive Logic
Positive Analog
Negative Analog
IVA+ - VD+I
t
-5V Analog
Y
+5V Analog
~.1
I -
Ferrite Bead
-~ -
UF 1
-
-
-
-.-----.----.---<
-
0.1 uF
0.1 uF
~
Units
V
V
V
V
V
+5V Digital
1 uF
17
28
+
VD+
APD
VREF+
2
Power Down
& Calibrate
Control
DPD
100 uF
ACAL
VREF-
DCAL
SMODE
Left Analog Input +
CMODE
3
AINL+
6.8 nF
CS5390
AID CONVERTER
4
SDATA
AINLLeft Analog Input -
LIR
SCLK
Right Analog Input +
Logic
26
FSYNC
AINR+
& Clock
ICLKD
6.8 nF
OCLKD
25
AINR-
ICLKA
Right Analog Input TST01
TST02
VA- LGND
DGND
AGND
8
21
t
Ferrite bead may
be used if VD+ is
derived from VA+.
If used, do not drive
any other logic
fromVD+.
An example ferrite
bead is Permag
VK200-2.5/52
Figure 1. Typical Connection Diagram
3-160
DS105PP2
_.-_..__.._-_.
...
._.~---
CS5390
GENERAL DESCRIPTION
SYSTEM DESIGN
The CS5390 is a 20-bit, stereo ND converter designed specifically for stereo digital audio
applications. The device uses two one-bit deltasigma modulators which simultaneously sample
the analog input signals at a 64 X sampling rate.
The resulting serial bit streams are digitally filtered, yielding pairs of 20-bit values. This
technique yields nearly ideal conversion performance independent of input frequency and
amplitude. The converter does not require difficult-to-design or expensive anti-alias filters and it
does not require external sample-and-hold amplifiers or voltage references.
Very few external components are required to
support the ADC. Normal power supply decoupIing components, voltage reference bypass
capacitors and a single resistor and capacitor on
each input for anti-aliasing are all that's required,
as shown in Figure 1.
On-chip voltage references provide for a differential input signal range of 14.72 Vpp. Any offset is
internally calibrated out during a power-up selfcalibration cycle. Output data is· available in serial
form, coded as 2's complement 20-bit numbers.
Typical power consumption of only 550 mW can
be further reduced by use of the power-down
mode.
The CS5390 is pin compatible with the CS5389,
and it offers wider dynamic range and twenty bit
resolution. The pin compatibility of the CS5390
provides a simple upgrade path to systems currently using the CS5389.
For more information on delta-sigma modulation
techniques see the references at the end of this
data sheet.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter and is used to generate the
modulator sampling clock. The required ICLKD
frequency is determined by the desired Output
Word Rate (OWR) and the setting of the CMODE
pin. CMODE high will set the ICLKD frequency
to 384 X OWR, while CMODE low will set the
ICLKD frequency to 256 X OWR. Table 1 shows
some common clock frequencies. The digital output clock (OCLKD) is always equal to 128 X
OWR. OCLKD should be connected to ICLKA,
which controls the input sample rate.
The phase alignment between ICLKD and
OCLKD is determined as follows: when CMODE
is low, ICLKD is divided by 2 to generate
OCLKD. The phase relationship between ICLKD
and OCLKD is always the same and is shown in
the Switching Characteristics Timing Diagrams.
When CMODE is high, OCLKD is ICLKD divided by 3. There are two possible phase
OCLKDI
-
UR
CMODE
(kHz)
ICLKD
ICLKA
SCLK
(MHz)
(MHz)
(MHz)
32
low
8.192
4.096
2.048
32
high
12.288
4.096
2.048
44.1
low
11.2896
5.6448
2.8224
44.1
high
16.9344
5.6448
2.8224
48
low
12.288
6.144
3.072
48
high
18.432
6.144
3.072
Table 1. Common Clock Frequencies
DS105PP2
3-161
_.:
.-_
_
..--_._.
__.._-_
...-.
CS5390
relationships between ICLKD and OCLKD,
which depend on the start-up timing between
DPD and uR, shown in Figure 2.
Serial Data Interface
o
ICLKD
..•
Input
DPD
Input
1
~
UR
Input
OCLKD
2
a
4
567
I
:
Output
UR
2
Input
OCLKD
2
Output
• DP.Q low is recognized on the next ICLKD rising edge (#0)
•• UB. rising before ICLKD rising #2 causes OCLKD-1
••• UR rising after ICLKD rising #2 causes OCLKD - 2
Figure 2. ICLKD to OCLKD Timing with CMODE
high (384XOWR)
MASTER mode and SLAVE mode are the 2 primary modes of operation for the serial data output
interface.
Master Mode
SCLK, UR and FSYNC are outputs derived from
ICLKD in Master mode, Figure 3. Notice the one
SCLK cycle delay between uR edges, SDATA
and FSYNC. FSYNC brackets the 16 most significant data bits.
Slave Mode
uR,
FSYNC and SCLK become inputs in
SLAVE mode. LtR must be externally derived
from ICLKD and be equal to the .Output Word
Rate. SCLK should be equal to 64 X OWR
though other frequencies are possible but may degrade system performance due to interference
effects. FSYNC may be high or used to control
SDATA. With FSYNC high, data bits are clocked
3-162
out via the SDATA pin using the SCLK and uR
inputs. The falling edge of SCLK causes the ADC
to output each bit, except the MSB, which is
clocked out by the LIR edge; as shown in Figure4.
SCLK is ignored with FSYNC low and only the
MSB is clocked out after the uR edge in SLAVE
mode / FSYNC controlled as shown in Figure 5.
Bringing FSYNC high will enable SCLK to clock
data out. This feature is particularly useful to multiplex multiple channels.
Certain serial modes align well with various interface requirements. A CS5390 in MASTER mode,
with an inverted LtR signal, generates I2S
(Philips) compatible timing. A CS5390 (with an
inverted SCLK) in SLAVE mode emulates a
CS5326 style interface and also links to a
DSP56000 in network mode .
The serial nature of the output data results in the
left and right data words being read at different
times. However, the words within an LIR cycle
represent simultaneously sampled analog inputs.
Analog Connections
Figure 1 shows the analog input connections. The
analog inputs are presented differentially to the
modulators via the AINR+, AINR- and AINu,
AINL- pins. Each analog input will accept a
maximum of 7.36 Vpp. The + and - input sigrials
are 1800 out of phase resulting in a differential
input voltage of 14.72 Vpp. Figure 6 shows the
input signal levels for full scale.
The analog modulator samples the input at
3.072 MHz (64 x Fs) for an output word rate of
48 kHz. The digital filter will reject signals between 21.7 kHz and 3.072 MHz - 21.7 kHz.
However, there is no rejection for input signals
which are ( n x 3.072 MHz) +/- 21.7 kHz, where
n =0,1,2, ... A 39 n resistor in series with the analog input and a 6.8 riP NPO or COG capacitor
between the inputs will attenuate any noise energy
DS10SPP2
----------- -----------
CS5390
LJR
Output
o
1
2
3
16 17 18 19
20 21
SCLK
Output
-
FSYNC
Output
SDATA
Output
Left Audio Data
Right Audio Data
Figure 3. Data Output Timing· MASTER mode
LJR
Input
I
I~
~~~~~~~1i%
17
18 19 20 21
22
SCLK
Input
~
~~~~~~~I~
FSYNC
II
Input
I
SDATA
Output
~~~~-+~~---~
Left Audio Data
·1
Right Audio Data
Figure 4. Data Output Timing· SLAVE Mode, FSYNC high
~
~
~
UR
Input
17 18 19 20 21 22
SCLK
Input
•
17 18 19 20 21
2.
~
~
~~
~
FSYNC
Input
1
SDATA
Output
~
Left Audio Data
22
Ii
11
~:
II
~ I
3
2
1
1
Right Audio Data
.1
I-:~
I
• Rising FSYNC enables SCLK to clock out SDATA
•• Falling FSYNC stops SCLK from clocking out SDATA
Figure 5. Data Output Timing· SLAVE Mode, FSYNC controlled
DS105PP2
3-163
_._-_.-.-------------3.BBV
OV
-3.BBV
3.6BV
CS5390
CS5390
=~
AIN+
OV~~
AIN-
-3.BBV
Full Scale Input level= (AIN+) - (AIN-)= 14.72 Vpp
Figure 6. Full Scale Input Voltage
at 3.072 MHz, in addition to providing the optimum source impedance for the modulators. The
use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be
avoided since these can degrade signal linearity. If
active circuitry precedes the ADC, it is recommended that the above RC filter is placed between
the active circuitry and the AINR and AINL pins.
The above example frequencies scale linearly with
output word rate.
The on-chip voltage references are available at the
VREF+ and VREF- pins for the purpose of decoupling only. The circuit traces attached to these
pins must be minimal in length and no load current may be taken from VREF+ or VREF-. The
recommended decoupling scheme, Figure 1, is a
100 IlF electrolytic capacitor across VREF+ and
VREF- and two 0.22 !!F ceramic capacitors connected from VREF+ to GND and VREF- to
GND.
Power-Down and Offset Calibration
APD and DPD are the analog and digital powerdown pins. When high, they place the analog and
r--
Cal Period
digital sections in the power-down mode wherein
typical power consumption drops to 1.5 mW.
Bringing DPD low exits power-down and initiates
an offset calibration cycle. During the calibration
cycle, the digital section measures the offset of
each channel and stores a corresponding value in
the calibration registers. This value is subtracted
from future conversions to produce an offset free
conversion. The calibration inputs are obtained
from the analog input pins (ACAL low) or AGND
(ACAL high).
The offsets generated by the input circuitry are included when calibration is performed using the
analog input pins (ACAL low). DCAL should be
used to control a multiplexer which grounds the
user's front-end in this mode. The DCAL output
will remain high for 4096 uR clock cycles during
calibration as shown in Figure 7.
A delay of approximately 50 output words will
occur following calibration for the digital ftlter to
begin accurately tracking audio band signals.
Power-up Considerations
Upon initial application of power to the supply
pins, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
potentially large values of data in these registers
with the correct values.
The modulators settle in a matter of microseconds
after the analog section is powered, either through
the application of power or by exiting the power--->I
r-- Filter Delay Time
(4096 x UR clocks)
(B5.33 ms @ 4BkHz)
DPD
(-50 UR periods)
(-1 ms @ 48 kHz)
Normal Operation
DCAl
Figure 7. Initial Calibration Cycle Timing
3-164
DS10SPP2
.._-_
.-_
_
..--_._.
__
...-.
down mode. The voltage reference will take a
much longer time to reach a final value due to the
presence of external capacitance on the VREF+
and VREF- pins. A time delay of approximately
10 ms/lJP is required between APD going low and
DPD going low to allow for VREF settling. The
typical connection diagram of Figure 1 requires a
1 second delay.
APD should be tied to AGND if the analog power
down feature is not required. When using the analog power down feature, DPD and APD may be
tied together if the capacitor across VREF+ and
VREF- is not greater than 10 IJP.
Grounding and Power Supply Decoupling
CS5390
AGND. The CDB5390 evaluation board is available which demonstrates the optimum layout and
power supply arrangements, as well as allowing
fast evaluation of the ADC.
To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
Additional printed circuit board design and circuit
design hints are included in the application note,
"Layout and Design Rules for Data Converters"
and the Audio Engineering Society paper "How to
Achieve Optimum Performance from Delta-Sigma
AID & D/A Converters" which are included in the
Crystal Semiconductor data book application section.
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the
recommended power arrangements, with VA+,
VA- and VL+ connected to a clean ± 5 V supply.
VD+, which powers the digital filter, may be run
from the system +5V logic supply, provided that
it is not excessively noisy « ± 50 mV pk-to-pk).
Alternatively, VD+ may be powered from VA+
via a ferrite bead. In this case, no additional devices should be powered from VD+. Analog
ground and digital ground should be connected
together near to where the supplies are brought
onto the printed circuit board. Decoupling capacitors should be as near to the ADC as possible,
with the low value ceramic capacitor being the
nearest.
MASTER MODE
The printed circuit board layout should have separate analog and digital regions and ground planes,
with the ADC straddling the boundary. All signals, especially clocks, should be kept away from
the VREF+ and VREF- pins in order to avoid unwanted coupling into the modulators. The VREF+
and VREF- decoupling capacitors, particularly the
0.22 IJP, must be positioned to minimize the electrical path from VREF+ and VREF- to Pin 1,
The internal counters of the CS5390 are reset during DPD/APD high and will start simultaneously
by insuring that the release of DPD for all converters is internally latched on the same rising
edge of ICLKD. This can be achieved by connecting all DPD pins to the same control signal
and insuring that the DPD falling edge occurs
outside a ±30 ns window either side of an ICLKD
rising edge.
DS105PP2
Synchronization of Multiple CS5390
In systems where multiple ADC's are required,
care must be taken to insure that the ADC internal
clocks are synchronized between converters to insure simultaneous sampling. In the absence of
this synchronization, the sampling difference
could be one ICLKD period which is typically
81.4 nsec for a 48 kHz sample rate.
SlAVE MODE
Synchronous sampling in the slave mode is
achieved by connecting all DPD pins to a single
control signal and supplying the same ICLKD and
I.JR to all converters.
3-165
--------
~==-=;=;"
CS5390··
PERFORMANCE
Digital Filter
0.020
Figures 8 - 10 show the performance of the digital
filter included in the ADC. All plots are normalized to the output word rate, Fs. Assuming a iii'
sample rate of 48 kHz, the 0.5 frequency point on :!:!.
Q)
the plot refers to 24 kHz. The filter frequency re- ]
sponse scales precisely with the output word rate. ·c
0.010
,--~--~---,--~--~----,
,,
,
_______ .1 _______ ..J ________ L _______ I.. _______ .l. ______ _
1
I
I
1
1
1
1
1
1
1
1
1
1
0.000
Cl
100dB" by
Steven R. Green, Steven Harris and Brent Wilson. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
7) " How to Achieve Optimum Performance from Delta-Sigma NO and D/A Converters" by Steven
Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
DS105PP2
.,.,.............
...., .......
.........
ICDB5389 CDB5390 I
Semiconductor Corporation
Evaluation Board for CS5389/ CS5390
Features
General Description
• Demonstrates recommended layout
and grounding arrangements
• CS8402 Generates AES/EBU, S/PDIF
& EIAJ CP-340 Compatible Digital
Audio
• Buffered Serial Output Interface
• On-board or externally supplied system
timing
GND+5V
Also included is a CS8402 digital audio interface transmitter which generates AESIEBU, S/PDIF & EIAJ
CP-340 compatible audio data. The digital audio data
is available via XLR, RCA phono and optical connectors
The evaluation board may also be configured to accept
external timing signals for operation in a user application during system development.
• Digital and Analog Patch Areas
-15V GND +15V
The CDB5389/CDB5390 evaluation board allows fast
evaluation of the CS5389 18-bit or CS5390 20-bit, stereo AID converter. The board generates all converter
timing signals and provides a serial output interface.
Evaluation requires a digital signal processor, a lowdistortion signal source and a power supply.
CDB5389
CDB5390
ORDERING INFORMATION:
ICLKD
FSYNC
0
AINR
CS5389
OR
'!
0
UR
SCLK
SERIAL
OUTPUT
DATA
SDATA
CS5390
AID CONVERTER
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
CS8402
DIGITAL AUDIO
INTERFACE
TRANSMITTER
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
Optical
Output
AUG '93
DS87DB1
3-173
• .,:,
...
~
~
AINR-
Input Buffer
SDATA1
AINR+
and
Protection
CS5389
OR
AINL-
Circuits
Serial to Parallel
Timing Generator
CS5390
AID Converter
,..,
.......1:i'·,,
=.,
.....
SCLK1
AINL+
en
0
~
en
()
r
0
()
r
" "
0
UR
FSYNC
--
SCLK
DPD
Reset
Circuit
RST
CS8402
Power
Digital Audio
Supply
Interface
o:cC
OJ
UI-
Co)
CD
CO
oC
OJ'
UI
~
~
c
~.
Co)
8
Figure 1. CDB5389/CDB5390 Overview
C
II
VA+
> u;;-:.
~
1
, , ,
R12
-:-
I
r"'",r;o:
I- - -
'1M
,...~g
IC5J
51il
:J
r :1
~ ~
Cl~
....
'- VD1+
=d
,.=
J924 lC53
VA17
7
VD+
0
U
z
>I§
en
u.
--'
VV
27
VREFSDATA
--'
U
U
en
~
~
0
~
~
~
en
en
U
en
0
:;c
~
V
0
.....
'"
=d
.....
15
10
TSTO ~ins must
be left loating
21
3
AINL+
4
AINL-
26
AINR+
25
AINRVD+
I
8
>
TSTOl
ICLKA
TST02
Ul
AINL+
OCLKD
CS5389
AINL-
FSYNC
VR
OR
AINR+
SCLK
CS5390
;>
16
~"
13
14
10k :
CMODE
12
DEB
A2
DEA
A3
0---;---1 DPD
~6
.10k
74HC243
APD
U13
ICLKD : 19
ACAL
DCAL
Al14
U11
B2
B3
AID CONVERTER
f0111
Aol3
10 Bl
AINR-
SMODE
DPD
22
20
•
.
6
1
~I/-
5V~
74HC04
LGND
AGND
DGND
8
14
~VD2+
U71JlJ11 ~
• Undesignated Capacitors are 0.1 uF
Cf
....
Ul
~
~C33
II
aJ
Oscillator
12.288 MHz
U1
I~
...L
Figure 2_ CS5389/CS5390 Connections
I
--------
£;=~;=z.
CDB5389/CDB5390
.----.-----------< VD+
+5V
'~--
__--~----~--~--~VD+
~----Shift CLK
QA,:!L t DIN
41koil-)
. CS
: LCLK
~
1
LCLK
~
"-
16 VCCDOUT
TO.luF 8
-J=10
12
11
y
47kO
l
2
PRE
5
D U14 Q~
74HC74
r>CLK
CLR
1
SDATAI "-
Q ~
X
:D17 (MSS)
,D 16
,D 15
QH 7
QG 6
QF 5
QE 4
GND
U12
74HC595 QD 3
QC 2
SRCLR
Latch CLK QS 1
QA 15
ShiftCLK
DIN
OE
13
1:1
113
DOUT OEQ 7
VCC
H
QG 6
QF 5
GND
U13
QE 4
74HC595 QD 3
r
1
V+
v~+
P3
,- - : X
1:1
VD+
SCLKI
X
~
16
TO.l~F8
-J=-'
10 SRCLR
12
Latch CLK
11 r>Shift CLK
DIN
14J
J-
r 'D7
:D6
:D5
:D4
:D3
:D2
,D 1
,D (LSS)
QC 2
QS 1
QA 15
1-fi
1uF ::L-
'D 14
'D 13
:D 12
:D11
:D 10
:D9
:D8
VD+
°
'D RDY
DACK~
47kO
ff
=
74HC14
P2
UR >-----70- P R
__ DRDY
Figure 7. Serial to Parallel Converter
(Not Included with CDB5389/CDB5390)
3-182
DS87DB1
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~
~
-____-
.. .....-..
..--....
CDB5389/CDB5390
::::::::::::
••••••••••••
.
•••••••••••••••
••••••••••••••••
•••••••••••••••
•••••••••••••••
•••••••••••••••
•••••••••••••••
•••••••••••••••
••••••••••••••••
•••••••••••••••
•••••••••••••••
••••••••••••••
•••••••••••••••
Component Side Layer
3-184
DS87DB1
----------------------
CDB5389/CDB5390
::::::::::.:
•••••••••••
-
•••••••••• ••••
•••••••••••••••
•••••••••• ••••
••••••••••
••••
••••••••••
••••
••••••••••
••••
•••••••••• ••••
•••••••••• ••••
•••••••••• ••••
••••••••••
••••
•••••••••
••••
••••••••• ••••
Solder Side Layer
DS87DB1
3·185
---_ .._,
..--------_-------
COB5389/COB5390
• Notes •
3-186
DS87DB1
--------.._------------
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
4
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
4·1
_-_.
.-_
......-._.
_
..-__
...-
AID and D/A CODECS
CS4131 PC-ISA bus to CS4215 Interface
CS4231 PC ISA Bus Multimedia Audio Codec
The CS4131 is an interface device which connects
to an PC-IS A bus on one side, and connects to the
CS4215 audio codec on the other. Registers inside
the CS4131 are clocked out serially to control the
CS4215.
The CS4231 is a single chip with 2 16-bit AID
converters, 2 16-bit D/A converters, adjustable input gain, and adjustable output level. Also included is ADPCM compression and decompression, MPC compatible mixer, timer register for
audio/visual synchronization and 16 samples deep
FWOs for record and playback. The device requires only a +5V supply, and has a low power
standby mode. Both digital audio and control information is communicated over a parallel bus
which meets the PC-ISA bus standard.
CS4215 Serial Interface AudioCodec
The CS4215 is a single 44 pin PLCC package
containing 2 16-bit AID converters, 2 16-bit D/A
converters, adjustable input gain, and adjustable
output level. Also included is a microphone preamplifier, stereo headphone driver, crystal oscillators and a mono monitoring output. The device
requires only a +5V supply, and has a low power
standby mode. Both digital audio and control information is communicated over a serial bus.
CS4216 Serial Interface Audio Codec
The CS4216 isa single 44 pin PLCC package
containing 2 16-bit AID converters, 2 16-bitD/A
converters, adjustable input gain, and adjustable
output level. The device requires only a +5V supply, and has a low power standby mode. Both
digital audio and control information is communicated over a serial bus.
CS4225 Two ADC, Four DAC Codec
Intended for automotive and surround sound applications, the CS4225 includes two 16-bit ADCs
and four 16-bit DACs. The analog inputs have
level adjustment and the analog outputs include an
output level attenuator. The device has mimy
clocking modes, including using the on-chip PLL
for locking onto an audio sample rate clock. The
CS4225 runs from +5V and has a low power
standby mode.
4-2
CS4248 PC ISA Bus Multimedia Audio Codec
The CS4248 is a single chip with 2 16-bit AID
converters, 2 16-bit D/A converters, adjustable input gain, and adjustable output level. The device
requires only a +5V supply, and has a low power
standby mode. Both digital audio and control information is communicated over a parallel bus
which meets the PC-ISA bus standard.
Software
To support the multimedia codec family, a wide
range of software is available. Windows and NT
drivers are available for the CS4231 and CS4248
multimedia codecs. A comprehensive diagnostics
package assists in the debug of boards. In addition, voice recognition and text~to-speech synthesis software demonstrates some of the capabilities
of an audio equipped Pc.
...-..
_.-_..--_
__.._-_
AID and D/A CODECS
CONTENTS
CS4131 Multimedia Digital Audio Controller
CS4215 16 Bit Multimedia Audio Codec
CDB4215 Evaluation Board for CS4215
CS4216 16 Bit Stereo Audio Codec .
CDB4216 Evaluation Board for CS4216
CS4225 Digital Audio Conversion System
CDB4225 Evaluation Board for CS4225 .
CS4231 Parallel Interface, Multimedia Audio Codec
CDB4231148 Evaluation Board for CS4231 and CS4248
CS4248 Parallel Interface, Multimedia Audio Codec
CS4231 and CS4248 Device Drivers .
Multimedia Audio Codec Diagnostic Software
First Byte's Monologue for Windows
Talk~To Voice Recognition from Dragon Systems
4-5
4-29
4-67
4-77
4-115
4-135
4-163
4-165
4-212
4-225
4-263
4-264
4-265
4-266
4-3
.._-_
__
.........
.-_..--_.'
...,
AID andD/A CODE,CS
• Notes •
4-4
.....
..
.
.. ...
•~IIIIIIIr _
~~
_
. . ..
CS4131
..,
..,
Semiconductor Corporation
~~
Multimedia Digital Audio Controller
Features
General Description
• Direct Interface of CS4215 to ISA Bus
• Support for stereo digital audio up to
48 kHz sample rate at 16 bit resolution.
• 16 bit DMA transfers of 8 or 16-bit audio
data to and from host PC.
The CS4131 is a monolithic integrated circuit that provides a digital audio interface between the Crystal
eS4215 audio Codec and a personal computer. The
eS4131 implements all timer and control functions necessary to record and play back sampled digital audio at
sample rates up to 48 kHz. The device is housed in a
68 pin PLCC or 64 pin TQFP.
• Full 10 bit lID address decode for more
flexible lID space usage and EISA bus
compatibility .
• 68 Pin PLCC
ORDERING INFORMATION:
CS4131-CL
0 to 70°C
CS4131-CQ
0 to 70 0 e
DATA
--l
I
r---+i
I
10
ADDRESS
-
I
16
I
~
ISABUS
INTERFACE
I
I
CONTROL
~
I
IRQ
~
I
I
DRQ
DAK
DAC
-
I
CONTROL
-
OOD~
I
DMA
~
~
CS4215
Audio
Codec
INTERFACE
~GIi'--------' '-------'~
2
68-pin PLCC
64-pin TQFP
ADC
I
___
_.J
Preliminary Product Information IThis ~ocument contains infor~ation for a. new. product. Crystal
.
Semiconductor reserves the nght to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1992
(All Rights Reserved)
DEC '92
DS104PP4
4-5
_-_
..- ...-.
•. --_._.
......
-".,
CS4131
DIGITAL CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Low Level Output Voltage
@IOLmax
High Level Output Voltage
@IOHmin
High Level Output Current
@VOHmax
Low Level Output Current
Min
VOL
VOH
Max
Unit
+0.4
V
V
+2.4
10H
2
4
8
12
mA
mA
mA
mA
driver
driver
driver
driver
2
4
8
12
mA
mA
mA
mA
driver
driver
driver
driver
@ VOL max
-2
-4
-8
-12
mA
mA
mA
+2
+4
+8
+12
mA
+10
IlA
mA
10L
-10
mA
mA
mA
Output tristate current
10Z
Power Consumption
Po
150
mW
Low Level Input Voltage (TTL level buffer)
VILTTL
+0.8
V
High Level Input Voltage (TTL level buffer)
VIHTTL
TTL Inputs
V
+2.0
-33
-496
!lA
!lA
!lA
496
IlA
Low Level Input Current
IlL
-1
High Level Input Current
IIH
+1
Input Pull-Up Current
IlL
Input Pull-Down Current
IIH
33
Schmitt Negative Threshold
Vt-
0.8
Schmitt Positive Threshold
Vt+
Schmitt Hysteresis
Vh
V
2.4
0.4
V
V
CMOS Inputs
Low Level Input Voltage (CMOS level buffer)
VILCMOS
High Level Input Voltage (CMOS level buffer)
VIHCMOS
0.3*VDD
V
V
0.7*VDD
IlL
-1
!lA
High Level Input Current
IIH
+1
IlA
Input PUll-Up Current
IlL
-33
-496
IlA
496
IlA
Low Level Input Current
Input Pull-Down Current
IIH
33
Schmitt Negative Threshold
Vt-
0.2*VDD
Schmitt Positive Threshold
Vt+
Schmitt Hysteresis
Vh
4·6
V
0.8*VDD
1.0
V
V
DS104PP4
.-_
..--_._.
__.._-_
...-.
CS4131
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Supply Voltage
DC Input Voltage
DC Input Current
Min
Max
Units
VDD
-0.3
+7.0
V
VIN
-0.3
VDD+0.3
V
liN
-10
+10
mA
Tstg
-55
+125
°C
300
°C
TA = 25°C
Storage Temperature
Lead Temperature
Symbol
10 seconds
Tlead
RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage
Ambient Temperature
DS104PP4
(TA
_
I
"
= 25°C)
Symbol
Min
Max
Units
VDD
+4.5
+5.5
V
TA
0
+70
°C
4-7
_
..---.-.
__.._-_
...-.
.-_
CS4131
SWITCHING CHARACTERISTICS (TA = 25°C; VDD = 4.75V to 5.25 V), outputs loaded with
10pF, ISA data lines with 15pF; Input Levels: Logic 0 = OV, Logic 1 = VDD
Parameter
Symbol
Min
Max
Unit
Writes to CS4215; 8-bit 10 slave mode
Address, AEN setup to IOWC inactive
t1
7
ns
Address, AEN hold from IOWC inactive
t2
12
ns
Data setup to IOWC inactive
t3
3
ns
t4
16
ns
t4A
96
ns
t5
6
35
ns
t6
4
24
ns
t6A
48
Data hold from IOWC inactive
IOWC active time
Reads from CS4215; 8-bit 10 slave mode
(Note 1)
Data valid from IORC active
Data hold from IORC inactive
IORC active time
Writes to CS4215; 16-bit DMA slave mode
ns
(Note 2)
DRO inactive from DACK active (8-bit mono and stereo,
16-bit mono)
t7
34
ns
DRO inactive from IOWC or IORC active (16-bit stereo)
t8
41
ns
Data setup to IOWC inactive
t9
3
ns
Data hold from IOWC inactive
t10
17
ns
lowe inactive time
t11
90
ns
lowe active time
t12
96
ns
IORC active time
t13
48
ns
Data valid from IORC active
t14
6
34
ns
25
ns
Reads from CS4215; 16-bit DMA slave mode
(Note 2)
Data hold from IORC inactive
t15
3
IORC Inactive Time
t16
90
t17
5
t18
500
t19
10
ns
CS4131 Reset
Internal registers reset from RESDRV active
RESDRV pulse width (Required by CS4215)
Control Bit Outputs
New control bit output values from IOWC inactive
Notes:
4-8
26
ns
ns
(Note 3)
32
ns
1. These specifications assume an ISA compliant controller which provides an address setup and
hold to IORC .
2. These specifications assume an ISA compliant controller which provides a DACK setup and hold
relative to IOWC for writes to the CS4215, and relative to IORC for reads from the CS4215.
3. These .Q.utputs cover the signals that are reflections of control bit registers. These include
SERD/C, PDN, and AUDRST.
DS104PP4
----------------------
CS4131
SWITCHING CHARACTERISTICS ( Continued)
Parameter
Symbol
Min
"Threshold" OMA operation to INTOUT active
t20
INTCLRBIT active write to INTOUT inactive
t21
10WC active to OBUFENx active
10WC inactive to DBUFENx inactive
Max
Unit
2 BCLK + 4
3 BCLK + 24
ns
1 BCLK + 5
2 BCLK + 29
ns
t22
5
29
ns
Interrupt Output
External Buffer Control
(Note 4)
t23
10
65
ns
10RC active to OBUFOIR active (programmed 1/0 mode)
t24
4
22
ns
IORC active to DBUFENO active
(programmed 1/0 mode)
t25
11
64
ns
10RC inactive to DBUFENx inactive
(both programmed 1/0 and DMA mode)
t26
5
28
ns
10RC inactive to DBUFDIR inactive (programmed 110 mode)
t27
11
65
ns
DACKO or DACK1 active to OBUFDIR active (DMA mode)
t28
4
22
ns
DACKO or DACK1 inactive to DBUFDIR inactive (DMA mode)
t29
5
30
ns
10RC active to OBUFENx active (DMA mode)
t30
5
29
ns
Serial Bus Interface; CS4215 Master Mode
SCLK Period
t31
125
ns
SCLK high time
t32
50
ns
SCLK low time
t33
50
ns
FSYNC setup to SCLK falling
t34
3
ns
FSYNC hold from SCLK falling
t35
17
ns
SDIN setup to SCLK falling
t36
3
ns
SOIN hold from SCLK falling
t37
14
ns
SCLK rising to SOOUT
5
t39
3
ns
TSOUT hold from SCLK falling
t40
14
ns
Notes:
46
ns
t38
TSOUT setup to SCLK falling
4. DBUFENx refers to DBUFENO or DBUFEN1
DS104PP4
4·9
_.-_..---._.
__.._-_
...-.
CS4131
SWITCHING CHARACTERISTICS ( Continued)
Parameter
Symbol
Min·
Max
Unit
SCLK period. Is BCLK divided by eight
t41
800
1200
ns
SCLK high time
Serial Bus Interface; CS4215 Slave Mode
t42
300
700
ns
SCLK low time
t43
300
700
ns
SCLK rising to FSYNC
t44
7
40
ns
SDIN setup to SCLK falling
t45
3
ns
SDIN hold from SCLK falling
t46
14
ns
SCLK rising to SDOUT
ns
t47
5
TSOUT setup to SCLK falling
t48
3
ns
TSOUT hold from SCLK falling
t49
14
ns
4-10
46
DS104PP4
.._-_
_.-_..--_._.
__
...-.
CS4131
leA
14A
-~
--
~
lowe
~
IORC
12
~
A(9:0)
AEN
I
A(9:0)
AEN
VALID
~ 15
0(7:0)
13
\
0(7:0)
I VALID
_I
VALID
I
~ Ie
II
VALID
14
a. Write Timing
Figure 1. CS4131 in 8-bit 110 Slave Mode
b. Read Timing
DRQOor
DRQ1
DACKOor
DACK1
IOWCor
IORC
Figure 2. DMA Deassertion
AEN
J
v-
112
~
111
VALID
19
IORC
D(15:0)
110
a. Write Timing
Figure 3. CS4131 in 16-bit DMA Slave Mode
RESDRV
IOWC
internal
registers
Control
Initial Value
BitOulput _ _ _ _ _ _~
Figure 4. CS4131 Reset Timing
DS104PP4
v-
J
II
IOWC
D(15:0)
AEN
b. Read Timing
IOWC
New Value
INTOUT
L -_ __
Figure 5. Control Bit Output Timing
Figure 6. CS4131 Interrupt
Output Timing
4-11
CS4131
IOWC
IORC
DACKOor
DACK1
DBUFDIR
DBUFENO.
DBUFEN1
Figure 7. CS4131 External ButTer Control Timing
SCLK
SCLK
FSYNC
FSYNC
SDIN
SDIN
SDOUT
SDOUT
TSOUT
TSOUT
a. CS4215 in Master Mode
b. CS4215 in Slave Mode
Figure 8. Serial Bus Interface Timing
4-12
DS104PP4
----------------------
CS4131
+5V
r 'r'r'r r
+5V
~
4
~
17
T
I
T
34
51
59
68
22K
ClKIN~
A9
A8
A7
A6
A5
ClKOUT~
TSIN~
FSYNC
SDIN
SDOUT
SClK
13
10
11
12
8
15
14
7
1
44
43
13
PD~
35
D/C
41
TSOUT
12
RESET
FSYNC
SDOUT
SDIN
SClK
PDN SERD/C
TSOUT
--AUDRST
A4
A3
A2
A1
AO
INTOUT
AEN
22K
22K
-
~
CS4215
lOW
lOR
l
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SAO
INT(n)
22
27
AEN
lOW
lOR
-
63
64
D15 ~ 74AlS.--..
~ 245 .--..
D14
D.--..
D13 ~D
A.--..
D12 ~A
D11
46
D10
B'--"
D9 ~
D8 ~
~
=
J7
39
38
37
36
33
32
31
30
29
28
CS4131
~~ ~.--..
BoardAnalog Board Digital
Ground
Ground
~A
.--..
D15
D14
D13
D12
D11
D10
D9
D8
ISA
BUS
65 ~DIR
DBEN1 r-----'-'-~~
,----
+5V
10K
-:
f
22K
~
<;
2:22K
~
24
IOJUMP1
23
IOJUMPO
3
TEST
DGND1,2
---.
DGND8
D7 ~-. 74AlS~
D6 ~:--. 245 ~
D5 ~'--. D
D ~
A~
D4 ~-.A
54
T
T
D3 ~-'A
A~
D2 ~-.
~
D1 ~-.A
B ~
DO ~-.
~
DBUFDIR +"-'DIR
DBENO ~G
61
BClK
2
RESDRV
- - 20
DACK1
16
DRQ1
- 21
DACKO
19
DRQO
D7
D6
D5
D4
D3
D2
D1
DO
ClK
RESET
DACK(n)
DRQ(n)
DACK(n)
DRQ(n)
11 1 9 118126135144152160
-.L
Figure 9. Typical Connection
DS104PP4
4-13
___-_
.. ...-.
-.-_
..--_._.
FUNCTIONAL DESCRIPTION
Overview
The CS4131 provides an interface between the
CS4215 and the 16-bit ISA bus. The CS4131 resides on the ISA bus found in the class of
desktop computers known as "PC-compatibles",
or PC's. It can act as both an 110 and DMA
slave.
As an 8-bit 110 slave, the CS4131 decodes its
own 16-byte 110 range, from among four possible base addresses, that can be selected via two
external pins. The CS4131 is used as an 110
slave primarily to set up its mode of operation.
The CS4131 also acts.as a 16-bit DMA slave. It
is physically connected to one or two DMA
channels. It can use either channel for both input
and output, or use one channel for input and the
other for output. The CS4131 can tristate one or
both DMA request lines to free up the channels
it is not using. It is used asa DMA slave for
sample transfers to and from the CS4215 Codec.
The CS4131 provides one interrupt request
(IRQ) line to notify the software driver when the
audio data ring buffer needs servicing.
The CS4131 can sink 12 rnA on each data bus
pin. For use in systems that require stronger
drive on the ISAdata lines, two pins are provided to control an external 74ALS245 buffer.
In a local bus implementation, no buffers are
typically required.
Component Requirements
External pullups or pulldowns may be connected
to the two IOJUMP pins if the system designer
requires a base 110 location other than the default 240H. The global tristate input is pulled-up
internally.
4·14
CS4131
An external pullup is required on SDOUT, and
external pulldowns are required on SCLK and
FSYNC. Series termination resistors may be
added depending on layout proximity of the
CS4131 and CS4215. For close spacing, they
will not be necessary.
Two 74ALS245 data buffers may be added if the
12 rnA drive provided by the CS4131 is insufficient for system requirements. The "A" side of
the buffers shoulli connect to the CS4131 data
bus and the '''B'' side of the buffers should connect to the PC data bus.
Connecting to the CS4215
The CS4131 connects to the CS4215 serial interface lines. The CS4131 requires that the CS4215
operate in master mode while recording or playing back samples. It also requires that FSYNC
and TSIN be tied together on the CS4215, and
the CS4215 be programmed in 128 bits per
frame mode (see Control Time Slot 3 in the
CS4215 data sheet). The CS4131 always receives FSYNC from the CS4215, except during
Control Mode.
Transfer of Data
Write Operation
For writes to the CS4215, the CS4131 takes parallel data from the data bus and shifts it out to
the Codec one bit at a time. Before shifting the
data out, the CS4131 appends control bits to the
data packet, and orders the data correctly according to mono/stereo and 8/16-bit conditions.
When fresh data is needed for another packet,
the CS4131 issues a DMA request, receives new
data, and repeats the shift out operation.
DS104PP4
_.-_..--__.._-_.
...
._.Read Operation
For reads of the CS4215, the CS4131 receives a
packet from the CS4215, strips off the relevant
bytes according to mono/stereo and 8/16-bit conditions, and loads them into 8-bit registers. It
then issues a DMA request, and the ensuing
DMA read operation transfers the data from the
CS4131 registers to main memory.
Control Mode Operation
For control mode operations, the CS4131 drives
Die LO to the CS4215, and takes over driving
'the SCLK and FSYNC lines. The control packet
is formed in the CS4131 by means of 110 writes,
and then shifted out under CS4131 control after
an 110 write to the CS4131 results in an FSYNC.
CS4131
mined by logic levels of the two 110 jumper pins
as follows:
IOJUMPI
o
o
1
1
CS4131 Registers
IOJUMPO Base Address
240H
o
1
050H
o
260H
1
250H
Note: in an EISA-based system, the CS4131 can
receive a slot-specific AEN, resulting in a base
address of X240 for example, when IOJUMPO
and 1 are both 0, and AENX is connected to the
CS4131.
Register Set
Table 1 shows the CS4131 register set.
The CS4131 acts as an 8-bit slave for programmed 110 operations, and as a 16-bit DMA
slave. It is capable of meeting timing for extended ISA "TYPE A" DMA, or for the standard
ISA DMA timings.
The TIMES LOT registers are used to load and
unload the serial shift register.
Reset
Figure 10 shows the TIMES LOT and shift register data path.
The ISA reset signal, RESDRV, resets all registers in the CS4131. The control register bits are
all reset low. See descriptions of the control registers for bit interpretations.
I/O Slave Operations
The CS4131 operates as an 8-bit 110 slave meeting standard ISA timing. It occupies a 16-byte
address range, with its base address set by the
two IOJUMP input pins.
Internal Decode
The CS4131 register set occupies 16 contiguous
110 addresses, beginning at a base address deter-
DS104PP4
Timeslot Registers
The data written to the TIMES LOT registers is
used to load the shift register that in tum, supplies
the CS4215. The data read from the TIMES LOT
registers originates from the CS4215, and is held
in the registers until it can be written to main
system memory (DRAM). To read what was just
written to the TIMES LOT registers, the programmer must put the CS4215 into loopback
mode, assert FSYNC, and wait at least 70 Ils for
the shift loopback operation to complete. The
TIMES LOT registers can be read back at that
point.
TIMES LOT registers 1 through 4 can be written
either via programmed 110 writes or DMA operations. Which registers are written to or read
4-15
.._-_
.-_
_
..--_.-.
__
...-.
CS4131
SDINd1
t
INPUT
REG.
-------.
-------.
REG.
-------.
-------.
~
~
Timeslot 6
INPUT
REG.
INPUT
REG.
~
INPUT
REG.
~
64-Bit
Shift
REG.
-------.
Register
Er
-------.
INPUT
REG.
Timeslot 1
EXTRA
MONO-8
INPUT
REG.
OUTPUT
REG.
BUF
~ i~;I->
REG.
BUF
~
{;} r---
OUTPUT
~
REG.
BUF
Timeslot4
-------.
~
OUTPUT
REG.
BUF
Timeslot 3
OUTPUT
-------.
~
REG.
I-----------
Timeslot 2
Timeslot 2
f--
BUF
Timeslot 5
Timeslot 3
INPUT
~
l~
OUTPUT
-------.
Timeslot 4
f--
OUTPUT
REG.
Timeslot 6
Timeslot 5
-'"
BUF
Timeslot 7
Timeslot 7
INPUT
REG.
{;}
REG.
Timeslot 8
Timeslot 8
INPUT
OUTPUT
MUX~
~
OUTPUT
I----REG.
Timeslot 1
t
-1~~r
~.
BUF
BUF
§- r---
SDOUT
BUF
~
1;Jr
BUF
EXTRA
MONO-8
INPUT
REG.
~~ f----.
BUF
Figure 10 Register Data Path.
4-16
DS104PP4
_.-_..--_._.
__.._-_
...-.
--
CS4131
--------------
-------------- -
Register Name
Offset Address
Function
TIMESLOT1
0000
Byte 1 of packet
TIMESLOT2
0001
Byte 2 of packet
TIMESLOT3
0010
Byte 3 of packet
TIMESLOT4
0011
Byte 4 of packet
TIMESLOT5
0100
Byte 5 of packet
TIMESLOT6
0101
Byte 6 of packet
TIMESLOT7
0110
Byte 7 of packet
TIMESLOT8
0111
Byte 8 of packet
CONTROL REGISTER A
1000
Control register - CS4131 configuration bits.
CONTROL REGISTER B
1001
Control register - CS4131 configuration bits.
DIE REVISION
1010
Holds revision level of the CS4131.
First revision holds the signature AOH.
FRAME COUNT READ
1011
Holds current value of internal frame bit counter.
Read-only register used for chip test.
STATUS POLL
1100
Holds bits that can be read by software to
determine packet transfer and interrupt flag status.
DMA COUNTER LSB READ
1101
Holds current value of LSB of DMA.
Read only register used for chip test.
DMA COUNTER MSB READ
1110
Holds current value of MSB of DMA.
Read only register used for chip test.
DMA COUNTER LOAD
1111
Upper byte of word that is used to initialize the
DMA counter.
Table 1. Register Set Table
Bit
Name
Function
0
DMAOEN
When high, enables DMA from DRAM to CS4131 (Writes to CS4215).
1
DMAIEN
When high, enables DMA from CS4131 to DRAM (Reads of the CS4215).
2
ID/C
Directly controls SERD/C pin on CS4215. When low, puts the CS4215 in control
mode.
3
ICMD
When high, allows the CS4131 to drive the bidirectional SCLK and FSYNC lines that
connect the CS4131 and CS4215.
4
STEREO
When high, tells the CS4131 that it should assume that the CS4215 is operating
in stereo modes.
5
WIDTH16
When high, tells the CS4131 that it should assume that the CS4215 is operating
with 16-bit samples.
6
IPDN
Directly controls PDN pin on the CS4215. When high, puts CS4215 into a powered
down, "sleep" state. Systems that depend on the CMOUT signal of the
CS4215 to always be active should never set this bit high.
7
FSYNCBIT
When ICMD is active, a write of high to this bit will cause a single FYSNC
bit to be output to the CS4215. This initiates a control packet transmission.
Note that no succeeding write of 0 is required.
Table 2. Control Register A Bit Definitions
DS104PP4
4-17
.._-_
.-_
_
..--__
...-..
CS4131
Control Register B
Bit
Name
Function
0
DMACNT8EL
When high, DMA writes to C84131 increment the DMA cycle counter.
When low, DMA reads from C84131 increment the counter.
1
DMAMODO
Defines DMA pin usage (see DMA mode table), pg. 14
2
DMAMOD1
Defines DMA pin usage (see DMA mode table), pg. 14
3
INTCLRBIT
A write of high to this bit will clear the INT line driven by C84131.
Not that no succeeding write of 0 is required.
4
DMACNTR8T
When high, resets the DMA cycle counter.
5
8ERBU8EN
When low, enables the C84131 to drive serial bus lines. When high,
C84131 tristates its drivers for these lines.
6
AUDR8T
When high, resets the C84215 and also puts the 084131 into serialloopback mode.
7
CLR8REN
WhE1n high, disables shift operations in the 64cbit shift register.
Table 3. Control Register B Bit Definitions
Status Poll Register
Bit
Name
Function
0
RCVD_T80UT 8et high when T80UT received at completion of packet transfer. Reset by
read from Timeslot 1.
1
8ENT_PKT
Packet sent out to C84215. 8et high at beginning of packet transfer. Reset by
write to Timeslot 1.
6
INTOVF
Interrupt overflow. Goes active when a DMA counter terminal count is reached
before a pending interrupt for a previous DMA counter terminal count was serviced.
Reset by a write of high to INTCLRBIT in Control Register B
7
INTFLG
Interrupt request activated by C84131 when DMA terminal count is reached.
Reflects state of INTOUT pin. Reset by a write of high to INTCLRBIT in
Control Register B.
Table 4. Status Poll Register Bit Definitions
from during DMA is determined by the CS4131
byte packing algorithm, described later.
TIMESLOT registers 5 through 8 are only writ. ten to via programmed 110. They do not receive
DMA service because they are usually static during sample playback and record operations.
Keeping these register values stored in the
CS4131 also reduces ISA bus bandwidth requirements.
TIMES LOT registers 5 through 8 can be written
to while DMA activity is in progress. These reg4-18
isters may be written to asynchronously, but
should be synchronized with the loading of the
main shift register as follows:
1) Wait for the RCVD_TSOUT (in Status Poll
Register) to go low.
2) Wait for RCVb_TSOUT to go high.
3) Write to time slot Register 5-8 immediately.
l)MA Counter LSB Read
This register holds the current value of the LSB
of the 16-bitDMA counter. This register is used
DS104PP4
----------- ----------for chip test purposes to increase the fault coverage of the test. It is not needed by the software
drivers, although it may be used for diagnostics
if deemed necessary.
DMA Counter MSB Read
This register holds the current value of the MSB
of the 16-bit DMA counter. This register is used
for chip test purposes to increase the fault coverage of the test. It is not needed by the software
drivers, although it may be used for diagnostics
if deemed necessary.
DMA Counter Load Register
The DMA Counter Load register sets the initial
count value for the DMA cycle counter. The
DMA cycle counter is a 16-bit counter. Its lower
eight bits are initialized to zero. The Counter
Load Register only initializes the upper eight
bits. The DMA counter is an up counter, incrementing its value on each DMA transfer. The
DMACNTSEL bit in Control Register B sets the
counter to increment on reads or writes.
The load value programmed in the register is inverted before loading into the DMA counter. For
example, if the load value programmed was
01R, the counter will be initialized to FEOOR.
The counter will count 512 DMA operations before an interrupt is generated by the count value
reaching FFFFH.
The number of DMA operations before interrupt
generation = ((load register value+1) * 256).
Writes to CS4215 Codec
ISA Bus Operation
When DMA is enabled for writes to the CS4215
(via the DMAIEN bit in Control Register A), the
CS4131 issues a DMA request (DRQ) as soon as
the current contents of the TIMES LOT registers
DS104PP4
CS4131
are loaded into the shift register in preparation
for a packet output. Once this load occurs, the
TIMESLOT registers are free to be loaded with
data for the next packet output. (The DMA channel used is determined by the programming of
the DMAMOD bits in Control Register B.) The
DMA acknowledge (DACK) will return from the
system board DMA controller. While DACK is
active, the DMA controller will execute one or
two write cycles to the CS4131. The two cycle
case occurs when the CS4131 indicates 16-bit
stereo mode. Note that the DMA controller
should always be programmed in demand mode.
At the beginning of the last cycle that the
CS4131 requires, it will deassert its DRQ signal.
The data is now in the TIMES LOT register,
ready to be loaded into the shift register when
the next packet is needed by the CS4131.
Note that the DMA latency required for no sample underruns is approximately equal to the
sample period. For example, a 44k Sample/sec
rate has a latency requirement of about 22).!s,
while a 8 k sample/sec rate has a latency requirement of about 125 ).!S.
Serial Bus Operation
The activation of FSYNC by the CS4215 begins
this operation. The CS4131 responds to the
FSYNC sampled on the falling edge of SCLK
by driving data out on its SDOUT pin on the
next rising edge of SCLK. This continues for
each SCLK, until the clock after TSOUT is sampled on a falling edge of SCLK.
Reads of the CS4215 Codec
ISA Bus Operation
When DMA is enabled for reads of the Codec
(via the DMAIEN bit in Control Register A), the
CS4131 issues a DMA request (DRQ) as soon as
a packet is loaded into the TIMES LOT registers.
The DMA channel used is determined by the
4-19
. '
.._-_
_.-_..--_._.
__
...-.
programming of the DMAMOD bits in Control
Register B. The DMA acknowledge (DACK)
will return from the system board DMA controller. While DACK is active, the DMA controller
will execute one or two read, cycles from the
CS4131. The two cycle case occurs when the
CS4131 indicates 16-bit stereo mode. Note that
the DMAcontroller should always be programmed in demand mode. At the beginning of
the last cycle that the CS4131 requires, it will
deassert its DRQ signal. The DMA cycle will
complete with the sample data completely transferred from the CS4215 to the CS4131 to
DRAM.
Note that the DMA latency required for no sample overruns is approximately equal to the
sample period. For example, a 44k Sample/s rate
has a latency requirement of about 221ls.
Serial Bus Operation
The activation of FSYNC by the CS4215 begins
this operation. The CS4131 responds to FSYNC
sampled on the falling edge of SCLK by loading
data from SDIN into the shift register on the
next rising edge of SCLK. This continues for
each SCLK, until the clock after TSOUT is sampled on a falling edge of SCLK
Byte Ordering and Packing
8-bit Mono Reads
One DMA read operation serves for two samples. A DMA request only occurs after every
second sample. The ensuing DMA read contains
the first sample data on D(7:0) and the second
sample data on D(15:8). Therefore, the first sample received in time goes into the lower memory
location.
4-20
CS4131
8-bit Stereo Reads
A DMA request is issued for each sample. The
left channel data is driven onD(7:0) and the
right channel data on D(15:8). Therefore, the left
channel data goes into the lower memory location.
16-bit Mono Reads
A DMA request is issued for each sample. The
most significant byte of the sample is driven on
D(15:8) and the least significant byte on D(7:0).
Therefore, the least significant byte goes into the
lower memory location. This conforms to the little-endian standard of Intel x86 processors.
16-bit Stereo Reads
Two DMA reads of the CS4131 are required to
load a single packet. These two reads are accomplished with a single DMA request, using the
demand transfer mode of the DMA controller.
The first DMA read will have the left channel
most significant byte on D(15:8), and left channel least significant byte on D(7:0). The second
DMA read will have the right channel most significant byte on D(15:8), and right channel least
significant byte on D(7:0). The resulting filled
memory will look like this:
Memory
Offset
o
1
2
3
Contents
Left channel LSB
Left channel MSB
Right channel LSB
RightchannelMSB
8-bit Mono Writes
One DMA write operation serves for two samples. A DMA request only occurs after every
second sample. The CS4131 will use,the data on
DS104PP4
----------- -----------
CS4131
DMAMOD1
DMAMODO
0
0
DMA Channel Usage
Neither channel used. Both DRQO and DRQ1 tristated. INTOUT
is tristated, too.
0
1
DMA channel 0 is used for both reads from and writes to the CS4215.
INTOUT enabled.
1
0
DMA channel 1 is used for both reads form and writes to the CS4215.
INTOUT enabled.
1
1
DMA channel 0 is used for reads from the CS4215. DMA channel 1
is used for writes to the CS4215. INTOUT enabled.
.'
Table 5. DMA Mode Table
D(7 :0) for its first packet, and the data on
D(l5:8) for its second packet.
During pause of play (suspended DMA), the
CS4131 will still send alternating samples from
TIMESLOTI register and the extra storage register. To avoid an output of Fsl2, set the
WIDTH16 bit in Control Register A. When
DMA resumes, this bit can be reset.
8-bit Stereo Writes
A DMA request is issued for each sample. The
CS4131 will use the data on D(7 :0) as left channel data, and the data on D(l5:8) as right
channel data.
16-bit Mono Writes
A DMA request is issued for each sample. The
CS4131 will use the data on D(7 :0) as the least
significant byte of the sample data, and the data
on D(l5:8) as the most significant byte of the
sample data.
16-bit Stereo Writes
Two DMA writes from the CS4131 are required
to unload a single packet. These two writes are
accomplished with a single DMA request, using
the demand transfer mode of the DMA controller. The first DMA write will expect the left
channel most significant byte on D(l5:8), and
DS104PP4
left channel least significant byte on D(7:0). The
second DMA write will expect the right channel
most significant byte on D(l5:8), and right channel least significant byte on D(7:0) The required
memory map is shown below:
Memory
Contents
Offset
o
Left channel LSB
1
Left Channel MSB
2
Right channel LSB
3
Right channel MSB
DMA and Interrupt Issues
DMA Mode Selection
The CS4131 provides the flexibility of softwareselectable DMA channels. Note that the CS4131
must utilize 16-bit DMA channels, which are
typically channels 5, 6, and 7 in ISA systems.
The channel usage is set by the DMAMOD bits
of Control Register B, as shown in Table 5.
DMA Counter
The DMA counter is used to count the number
of either DMA writes to the CS4215 or DMA
reads from the CS4215, depending upon the setting of the DMACNTSEL bit found in Control
Register B. When the counter reaches its terminal value of FFFFH, the INTOUT output of the
CS4131 is activated. This interrupt can signal the
4-21
----------------------software driver that the sample ring buffer in
DRAM needs to be serviced. The counter is set
to its initial value via the DMA Counter Load
Register. This register sets the upper eight bits of
the counter to the inverse of the value that is
programmed into it. The lower eight bits of the
counter are always initialized to FEOOH. The
counter will count 512 DMA operations before
an interrupt is generated by the count value
reaching FFFFH.
The number of DMA operations before interrupt
generation = ((load register value+ 1) * 256).
After the counter reaches FFFFH, it rolls over
and begins counting again at the value programmed by the DMA Counter Load Register.
CS4131
will prevent contention with the CS4215 on
thes.e lines.
The CS4131 enables these lines synchronously
to the new SCLK that will be driven. In other
words, when these lines are enabled, there will
be no spikes or runt pulses on SCLK, and
FSYNC will be initially driven to a clean low.
The CS4131 also disables these lines synchronously to SCLK, ensuring that there are no clock
spikes or runt pulses.
The synchronization carries a time penalty, so allow 2 Ils after the I/O write that modifies ICMD
before assuming that the action of the write
(SCLKlFSYNC enable or disable) is complete.
SCLK frequency
Interrupt Output
Generation
The INTOUT signal is generated when the DMA
counter reaches FFFFH. it remains active until
cleared via the I/O write described below. The
state of INTOUT is mirrored in the INTFLG bit
in the Status Poll Register.
Clearing
The INTOUT signal is cleared by writing a high
to the INTCLRBIT found in Control Register B.
If left active in the register, this high will not
prevent a succeeding INTOUT from being asserted. Therefore, there is no need to write a low
to INTCLRBIT after the first write of a high.
The SCLK generated by the CS4131 for control
mode operations is· formed by a divide-by-eight
of the ISA BCLK input. Therefore, it will operate at a nominal frequency of 1 MHz.
FSYNC generation
FSYNC is generated for the CS4215 control
mode by writing a high to the FSYNCBIT found
in Control Register A. Note that no succeeding
write of a low is required.
Under normal operation, a second FSYNC cannot be generated until the TSOUT from the first
one is received. This can cause a problem with
the CS4215, as it does not return TSOUT from
the first FSYNC it receives when it goes into
control mode. To work around this problem, observe the following procedure.
CS4215 Control Mode
1) Generate initial FSYNC with FSYNCBIT.
Enabling of SCLK and FSYNC
The CS4131 will drive SCLK and FSYNC when
the ICMD bit found in Control Register A is
high. It is recommended that this bit only be set
high when IDle in the same register is low. This
4-22
2) Wait a minimum of 100 Ils.
3) Allow a second FSYNC to be sent by pulsing
the CLRSREN bit found in Control Register B
high, then low.
DS104PP4
.._-_
_.-_..--_._.
__
...-.
4) Send a second FSYNC by writing to Control
Register A with FSYNCBIT high.
5) Read Status Poll Register until RCVD
TSOUT is active.
Now the CS4215 should be returning TSOUT to
each FSYNC and FSYNC can be asserted using
a polling procedure instead of using software
timers:
1) Read and write to offset 0 to clear Status Poll
Register bits.
CS4131
control lines for two external 74ALS245 type
buffers. The 74ALS245's should have their "A"
sides connected to the CS4131, and their "B"
sides connected to the ISA data bus. The
CS4131 DBUFENO output should be connected
to the EN input of the 74ALS245 that connects
to the low order byte of the ISA data bus, and
the DBUFENI output should be connected to the
EN input of the 74ALS245 that connects to the
high order byte of the ISA data bus. The CS4131
DBUFDIR output should be connected to the
DlR input of both 74ALS245's.
2) Generate FSYNC.
3) Read Status Poll Register to determine if
TSOUT has been received by the CS4131. If so,
read and write to offset 0 to clear Status Poll
Register bits.
CS4215 Reset
The CS4215 is reset by two conditions:
1) ISA Bus reset initiated by RESDRV, This
also resets all CS4131 logic.
2) XAUDRST bit found in Control Register B
is high. Note that this bit also puts the CS4131
into serialloopback mode. XAUDRST does not
reset CS4131 logic - it only puts it into loopback mode.
Selective Tristate of Serial Lines
The CS4131 serial lines that interface to the
CS4215 are tristated by the CS4131 when the
SERBUSEN bit found in Control Register B is
driven inactive (high). Note that these lines are
not tristated upon power up reset.
The Loopback Mode
The CS4131 loopback mode is a useful tool for
diagnostics. When XAUDRST is active, the shift
register output is looped around to its input. After a full frame send, the data written to the
TIMES LOT registers can be read back at the
same addresses. When in loopback mode,
FSYNC must be generated via the FSYNCBIT
for a loopback operation. An internal-only version of TSOUT is generated by the CS4131, so
the RCVD TSOUT bit may be used to determine
when the frame shift operation is complete. Alternatively, a wait after sending FSYNC of about
100 f..ls may be used.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
External Buffer Control
The CS4131 data bus lines can sink up to
12 rnA per pin. For system applications where
greater drive is required, the CS4131 provides
DS104PP4
4-23
------_--------..,-----
CS4t31
PIN DESCRIPTIONS
GNO
RESORV
TEST
NTOUT
OBUFENO
OBUFOIR
AUDRST
PON
GNO
SDOUT
SOIN
SCLK
FSYNC
TSOU.!
SERO/C
ORQ1
VCC
GNO -----j=1
ORQO
OACK1
OACKO
INTOUT
IOJUMPtr
IOJUMPf
RSV01
GNO
AEN
AO
A1
A2
A3
A4
AS
VCC
VCC
RSV05
RSV04
OBUFEN1
IORC
IOWC
RSV02
BCLK
GNO
VCC
CS4131
68-Pin
PLCC
Top View
07
06
05
04,
03
02
p.---GNO
VCC
01
DO
08
09
010
011
GNO
012
013
014
015
A9
A8
A7
A6
GNO
"
4-24
OS104PP4
.-_
_
..--_._.
__.._-_
...-.
CS4131
PIN DESCRIPTIONS
TEST
NTOUT
OUBFENO
OUBFOIR
AUORST
PON
GNO
SOOUT
SOIN
SCLK
FSYNC
TSOUT
SERO/C
ORQ1
VCC
GNO
ORQO
OACK1
OACKO
INTOUT
IOJUMPO
IOJUMP1
GNO
AEN
AO
A1
A2
A3
A4
A5
VCC
GNO
4
CS4131
6
64-Pin
TQFP
----r-I8
RESORV
GNO
VCC
OUBFEN1
IORC
IOWC
BCLK
GNO
VCC
07
06
05
04
03
02
GNO
vce
Top View
10
12
14
16
18
20
22
24
26
_1~
28
30
32
01
00
OS
09
010
011
GNO
012
013
014
015
A9
AS
A7
A6
Serial Interface Pins
FSYNC - Frame Sync, Pin 13(L), 3(Q)
Frame Synchronization Signal. 4mA CMOS 110.
SDOUT - Serial Data Output, Pin 10(L), 20(Q)
Serial data out to CS4215. 4mA CMOS Output.
SDIN - Serial Data In, Pin l1(L), l(Q)
Serial data in from CS4215. CMOS Input, Weak: Pull Up.
SCLK - Serial Clock, Pin 12(L), 2(Q)
Serial Clock Signal. 4mA CMOS 110.
OS104PP4
4-25
----
--------~..
---------
CS4131
PDN - Power Down, Pin 8(L), 18(Q)
4mA CMOS Output.
SERD/C - Serial Data/Control, Pin 15(L), 5(Q)
Serial data/control word indicator. 4mA CMOS Output.
TSOUT - Timeslot Out, Pin 14(L), 4(Q)
End of frame indicator from CS4215. CMOS Input, Weak: Pull Down.
AUDRST - Pin 7(L), 61(Q)
Reset for CS4215. 4mA CMOS Output
[SA Bus Control
DRQI - DMA Channell Request, Pin 16(L), 6(Q)
12mA TTL Output.
DRQO - DMA Channel 0 Request, Pin 19(L), 9(Q)
12mA TTL Output.
DACKI- DMA Channell Acknowledge, Pin 20(L), 10(Q)
Schmitt TTL Input.
DACKO - DMA Channel 0 Acknowledge, Pin 21(L), ll(Q)
Schmitt TTL Input
INTOUT - Interrupt Out, Pin 22(L), 12(Q)
12mA TTL Output.
10RC - Pin 64(L), 52(Q)
ISA I/O read signal used for CPU-driven I/O and DMA operations. Schmitt TTL Input.
IOWC - Pin 63(L), 51(Q)
ISA I/O write signal used for CPU-driven I/O and DMA operations. Schmitt TTL Input.
AEN - Pin 27(L), 16(Q)
Address can be decoded from address bus when low. TTL Input.
[SA Clock and Reset
BCLK - Bus Clock, Pin 61(L), 50(Q)
Schmitt TTL Input.
RESDRV - ISA Bus Reset Signal, Pin 2(L), 56(Q)
Schmitt TTL Input.
4-26
DS104PP4
----------- -----------
CS4131
A4 - A9 - Address Lines Used for Decode Register Block, Pins [32,33,36 - 39(L)] [21,22,
25-28(Q)]
TTL Inputs.
AO - A3 - Address Lines Used for Register Selection, Pins [28 - 31(L)] [17-20(Q)]
TTL Inputs.
DO - D15 - Parallel Data Bus Bits, Pins [49, 50, 53-58, 48 - 45, 43 - 40(L)] [38,39,42-47,37-34,
32-29(Q)]
12mA TTL 110.
IOJUMPI - 110 Jumper 1, Pin 24(L), 14(Q)
Jumper to determine 110 base address. CMOS Input, Weak Pull Up.
IOJUMPO - 110 Jumper 0, Pin 23(L), 13(Q)
Jumper to determine I/O base address. CMOS Input, Weak Pull Up.
External Buffer Control
DBUFENO - Data Buffer Enable 0 Pin 5(L), 59(Q)
Enable for external '245 type data buffer that may connect low order byte of ISA and CS4131
data buses. 8mA TTL Output.
DBUFENI - Data Buffer Enable 1, Pin 65(L), 53(Q)
Enable for external '245 type data buffer that may connect high order byte of ISA and CS4131
data buses. 8mA TTL Output.
DBUFDIR - Data Buffer Direction, Pin 6(L), 60(Q)
Direction control for both '245 type data buffers that may connect ISA and CS4131 data buses.
8mA TTL Output.
Power and Ground Pins
vee - Digital Power Supply, Pins [17, 34, 51, 59, 68(L)] [7,23,40,48, 54(Q)]
GND - Digital Ground, Pins [1, 9, 18, 26, 35, 44, 52, 60(L)] [55, 63, 8, 15, 24, 33, 41, 49(Q)]
Miscellaneous
TEST - Pin 3(L), 57(Q)
Tristates all outputs except NTOUT for test purposes. CMOS input, Weak Pull Up.
NTOUT - NAND Tree Output, Pin 4(L), 58(Q)
2mA CMOS Output.
DS104PP4
4-27
--------.,,_. -----------
CS4131
RSVDl, 2, 4, 5 - Pins 25,62,66, 67(L)
Reserved
4-28
DS104PP4
... __ ....
I - ' . . . .~~~.
. . . .1-'1-' •
CS4215
....
Semiconductor Corporation
16-Bit Multimedia Audio Codec
Features
General Description
• Sample Frequencies from 4 kHz to 50 kHz IIJIwave
16-bit Linear, 8-bit Linear, Il-Law, or A-Law
• Audio
Data Coding
• Programmable Gain for Analog Inputs
Attenuation for Analog
• Programmable
Outputs
• On-chip Oscillators
• +5V Power Supply
• Microphone and Line Level Analog Inputs
• Headphone, Speaker, and Line Outputs
• On-chip Anti-Aliasing/Smoothing Filters
• Serial Digital Interface
The CS4215 is an Mwave™
audio codec.
The CS4215 is a single-chip, stereo, CMOS multimedia
codec that
supports
CD-quality
music,
FM radio-quality music, telephone-quality speech, and
modems. The analog-to-digital and digital-to-analog
converters are 64xoversampled delta-sigma converters
with on-chip filters which adapt to the sample frequency selected.
The +5V only power requirement makes the CS4215
ideal for use in workstations and personal computers.
Integration of microphone and line level inputs, input
and output gain setting, along with headphone and
monitor speaker driver, results in a very small footprint.
Ordering Information:
CS4215-KL
O°C to 70°C
CS4215-KQ
O°C to 70°C
CDB4215
Evaluation Board
CMOUT
LlNl
unsigned
LlNR
~-Iaw
MINl
44-pin PLCC
100-pin TQFP
SDOUT
SClK
FSYNC
MINR
TSIN
SDIN
TSOUT
ClKIN
ClKOUT
XTl11N
XTL10UT
VREF
MOUT1
8
MOUT2
XTL21N
XTL20UT
PlOD
LOUTR
LOUTL
HEADC
HEADR
HEADL
Control
PI01
DIG
RESET
PDN
VA1
VA2
VD1
VD2
AGND1
AGND2 DGND1 DGND2
This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and
previous versions, see Appendix A.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 44fr7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS76F2
4-29
-_.._-_.
~==~;=:,
CS4215
ANALOG CHARACTERISTICS( TA = 25°C; VA1, VA2, VD1, VD2' = +5V;
Input Levels: Logic 0 = OV, Logic 1 = VD1, VD2; FufiSoalelnput Sine wave, No Gain, No Attenuation 1 kHz;
Conversion Rate = 48 kHz; No Gain, No Attenuation, SCLK = 3.072 MHz; Measurement Bandwidth is 10Hz to'
20 kHz; Slave mode; Unless otherwise specified.)
Parameter *
Symbol
Min
Typ
Max
Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
-
-
±D.9
LSB
Instantaneous Dynamic Range ,
Line Inputs
Mic Inputs
lOR
80
72
84
78
-
dB
,dB
Total Harmonic Distortion
Line Inputs
Mic Inputs
THO
-
-
0.012
0.032
%
%
80
60
-
dB
dB
-
0.5
0.5
dB
dB
+0.2
dB
23.5
44
dB
dB
1.5
-
dB
16
ADC Resolution
ADC Differential Nonlinearity
Line to Line Inputs
Line to Mio Inputs
Interchannel Isolation
Interchannel Gain Mismatch
Line Inputs
Mic Inputs
Frequency Response (Note 1)
(0 to 0.45 Fs)
-0.5
Line Inputs
Mic Inputs
-0.2
19.8
Programmable Input Gain
-
Gain Step Size
-
Bits
-
0.75
dB
Offset Error
with HPF = 0
(No Gain)
line Inputs (AC Coupled)
Line Inputs (DC Coupled)
Mic Inputs
-
±150
±10
±400
±400
±150
LSB
Offset Error
with HPF = 1 (Notes 1,2)
(No Gain)
Line Inputs (AC Coupled)
Line Inputs (DC Coupled)
Mic Inputs
-
0
0
0
±5
±5
±5
0.250
2.50
2.50
0.28
2.8
2.8
0.310
3.10
3.10
Vpp
Vpp
-
100
ppm/°C
20
-
-
-
-
15
pF
1.9
2.1
2.3
V
Absolute Gain Step Error
Full Scale Input Voltage:
(MLB=O) Mic Inputs
(MLB=1) Mic Inputs
Line Inputs
Gain Drift
Input Resistance
(Note 3)
Input Capacitance'
CMOUT Output Voltage
(Maximum output current = 400 ~A)
(Note 4)
LSB
Vpp
kil
Notes: 1. ThiS specification is guaranteed by characterization, not production testing.
2. Very low frequency signals will be slightly distorted when using the HPF.
3. Input resistance is for the input selected. Non-selected inputs have a very high (>1 Mil) input
resistance.
4. DC c:;urrent only. If dynamic loading exists, then CMOUTmust be buffered or the performance of
ADC's imd DAC's may be degraded.
* Parameter definitions are given aUhe end of this data sheet. '
Mwave™ is a trademark of the IBM Corporation.
4-30
Specifications are subject to change without notice.
DS76F2
.._--.-_
..--_.-.
...-.
-_
CS4215
ANALOG CHARACTERISTICS
(Continued)
Symbol
Parameter •
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution
DAC Differential Nonlinearity
-
±O.9
LSB
-
dB
-
0.025
0.2
0.32
%
%
%
80
40
-
dB
dB
0.5
0.5
dB
dB
-
95
80
85
THD
-
-
(Note 5)
(Note 6)
(Note 6)
Interchannel Isolation
Line Out
Headphone Out
(Note 5)
(Note 6)
Line Out
Headphone
Programmable Attenuation
Bits
-
IDR
Line Out
Headphone Out
Speaker Out
Frequency Response (Note 1)
-
TDR
Total Harmonic Distortion
(OLB = 1)
Interchannel Gain Mismatch
-
(All Outputs)
Total Dynamic Range
Instantaneous Dynamic Range (OLB = 1)
16
-
(0 to 0.45 Fs)
-0.5
(All Outputs)
0.2
-
dB
-
+0.2
dB
-94.7
dB
1.5
-
dB
-
0.75
dB
Offset Voltage
Line Out
-
10
-
mV
Full Scale Output Voltage
Line Output
with OLB = 0
Headphone Output
Speaker Output-Differential
(NoteS)
(Note 6)
(Note 6)
2.55
3.6
7.3
2.8
4.0
8.0
3.08
4.4
8.8
Vpp
Vpp
Vpp
Full Scale Output Voltage
Line Output (Note 5)
with OLB = 1
Headphone Output (Note 6)
Speaker Output-Differential (Note 6)
1.8
1.8
3.6
2.0
2.0
4.0
2.2
2.2
4.4
Vpp
Vpp
Vpp
-
100
-
ppm/oC
-
1
Degree
-60
-
dB
-
110
0.5
140
2
mA
40
-
dB
Attenuation Step Size
Absolute Attenuation Step Error
Gain Drift
Deviation from Linear Phase
Out of BaRd Energy
(22 kHz to 100 kHz)
Line Out
Power Supply
Power Supply Current
Power Supply Rejection
Notes;
DS76F2
(Note 7)
Operating
Power Down
(1 kHz)
rnA
5. 10 kn, 100 pF load. Headphone and Speaker outputs disabled.
6.48 n, 100 pF load. For the headphone outputs, THD with 10kn, 100pF load is 0.02%.
7. Typically, 50% of the power supply current is supplied to the analog power pins (VA1, VA2)
and 50% is supplied to the digital power pins (VD1, VD2). Values given are for unloaded outputs.
4-31
.._-_
.----_._.
-.--_
...-.
CS4215
AID Decimation Filter Characteristics
Parameter
Symbol
(Fs is conversion freq.)
Passband
Min
Typ
Max
Units
0
O.4SFs
Hz
O.SSFs
-
74
-
-
-O.S
+0.2
dB
±O.1
dB
O.SSFs
Hz
dB
16/Fs
-
-
0.0
Ils
Min
Typ
Max
Units
0
O.4SFs·
Hz
O.4SFs
-
O.SSFs
.-
74
-
Group Delay
-
Group Delay Variation vs. Frequency
-
Frequency Response
-
Passband Ripple
0.4SFs
Transition Band
~
Stop Band
Stop Band Rejection
Group Delay
Group Delay Variation vs. Frequency
Hz
s
D/A Interpolation Filter Characteristics
Symbol
Parameter
Passband
(Fs is conversion freq.)
-O.S
Frequency Response
+0.2
dB
±0.1
dB
O.SSFs
Hz
Hz
dB
16/Fs
-
-
0.1/Fs
s
-
Passband Ripple
Transition Band
Stop Band ..
~
Stop Band Rejection
DIGITAL CHARACTERISTICS (TA = 2S0C; VA1,
Parameter
s
VA2, VD1, VD2 = SV)
Symbol
Min
Max
Units
High-level Input Voltage
VIH
(VD1,VD2)-1.0
(VD1,VD2)+0.3
V
Low-level Input Voltage
VIL
-0.3
1.0
V
High-level Output Voltage at 10 = -2.0 rnA
VOH
(VD1,VD2)-0.2
-
V
Low-level Output Voltage at 10 =2.0 rnA
VOL
-
0.1
V
10
J.I.A
10
IlA
Input Leakage Current
Output Leakage Current
4-32
(Digital Inputs)
(High-Z Digital Outputs)
DS76F2
----------- -----------
CS4215
SWITCHING CHARACTERISTICS (TA = 25°C; VA1,
outputs loaded with 30 pF; Input levels: logic 0
Parameter
SClK period
VA2, VD1, VD2 = +5V,
= OV, logic 1 = VD1, VD2)
Symbol
Min
Typ
Master Mode, XClK = 1 (Note 8)
Slave Mode (XClK = 0)
tsckw
tsckw
-
1/(Fs*bpf)
80
= 0 (Note 9)
= 0 (Note 9)
tsckh
25
-
tsckl
25
ts1
15
th1
10
-
SClK high time
Slave Mode, XClK
SClK low time
Slave Mode, XClK
Input Setup Time
Input Hold Time
Input Transition Time
-
10% to 90% points
Output delay
tpd1
-
SClK to TSOUT
tpd2
-
Output to Hi-Z state
Timeslot 8, bit 0
thz
-
Output to non-Hi-Z
Timeslot 1, bit 7
tnz
15
Input Clock Frequency
Crystals
ClKIN (Note 10)
1.024
Input Clock (ClKIN) low time
30
Input Clock (ClKIN) high time
30
Sample rate
Notes:
(Note 11)
-
-
Units
-
s
ns
-
ns
ns
ns
ns
10
ns
28
ns
30
ns
12
ns
-
ns
27
13.5
MHz
MHz
-
ns
-
ns
4
-
50
kHz
500
-
-
ns
Fs
RESET low time
-
Max
8. In Master mode with BSEl1 ,0 set to 64 or 128 bits per frame (bpf), the SClK duty cycle is 50%.
When BSEl1 ,0 is set to 256 bpf, SClK will have the same duty cycle as ClKOUT.
See Internal Clock Generation section.
9. In Slave mode, FSYNC and SClK must be derived from the master clock running the codec
(ClKIN, XTAl1, XTAl2).
10. Sample rate specifications must not be exceeded.
11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage
reference to settle.
FSYNC in
TSIN
TSOUT
FSYNC oul
---+---f----1,
I sckh 1+---.----.1
SClK
X
----'
SDIN
,-----'-"-''-'----,1,-
SDOUT
1'--~.:..:...="-'----1 ~_--''--_J,,
__
___
~X
TS 8, BilO
I
d
TS 8, Bil 0
1 hz
DS76F2
4-33
_
i
"
_-_...-..
.-_
_
..-_
__.......
OS4215
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = OV, all voltages with
Parameter
Power Supplies:
Input Current
Symbol
Min
Max
Units
Digital VD1,VD2
Analog VA1,VA2
-0.3
-0.3
6.0
6.0
V
V
-
±10.0
mA
-0.3
(VA1, VA2)+0.3
V
-0.3
(VD1, VD2)+0.3
V
-55
+125
°C
-65
+150
°C
(Except Supply Pins)
Analog Input Voltage
Digital Input Voltage
(Power Applied)
Ambient Temperature
Storage Temperature
Warning:
respect to OV.)
Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = OV, all voltages with re-
spect to OV.)
Parameter
Power Supplies:
Operating Ambient Temperature
Note:
4-34
8.
Symbol
Min
Typ
Max
Units
Digital (Note 8) VD1,VD2
Analog (Note 8) VA1,VA2
4.75
4.75
5.0
5.0
5.25
5.25
V
V
0
25
70
°C
TA
IVD - VA I must be less than 0.5 Volts (one diode drop).
DS76F2
.._-_
.-_
_
..--_.-.
-_
...-.
CS4215
Ferrite Bead
+5V Analog
+5V Digital
Supply
1 uF
~
~O.IUF
3
0.47 uF
Microphone
Input Right
150
>-1
15
VOl
8
VD2
24
VA2
Supply
+
0.1 uF
~
~'UF
23
VAl
MOUTI
MINR
;,,32Q
-
MOUT2
NPO
12Q 112W
~
Headphone
HEADR
Jack
;,,48Q
HEADL
30 12Q 1/2W
HEADC
0.47 uF
Microphone
Input Left
150
>-1
17
MINL
LOUTR
0.01 uF
NPO
~
LOUTL
19
To Optional
CMOUT
CS4215
VREF
Input Buffers
0.47 uF
+
r
~
XTL2IN
'OUF
16.9344 MHz
16
)--------1
UNR
XTL20UT
18
) .-------'-"-1 UNL
XTLIIN
See Line Level
Inputs Section
+5v
24.576 MHz
XTL10UT
20k
Refer to the Analog Inputs
section for terminating
unused line and mic inputs.
SDiN
4
CLKIN
All other unused inputs
should be tied to GND. All NC
pins should be left floating.
CLKOUT
5
12
RESET
PDN
SDOUT
VOl
TSOUT
TSIN
47k
36
---+---';PIOO
+-_ _..,,3!...7-.; PIOI
D/C
SCLK
FSYNC
13
44
41
Controller
40
35
43
42
20k
22
Note: AGND and DGND pins must be on the same ground plane.
Figure 1. Recommended Connection Diagram
DS76F2
4-35
I
.-_
_
..--_._.
__.._-_
...-.
FUNCTIONAL DESCRIPTION
Overview
The CS4215 has two channels of 16-bit analogto-digital conversion and two channels of 16-bit
digital-to-analog conversion. Both the. A,DCs and
the DACs are delta-sigma converters. The ADC
inputs have adjustable input gain, while the
DAC outputs have adjustable output attenuation.
Special features include a separate microphone
input with a 20 dB programmable gain block, an
optional 8-bit ~-law or A-law encoder/decoder,
pins for two crystals to set alternative sample
rates, direct headphone drive and mono speaker
drive.
Control for the functions available on the
CS4215, as well as the audio data, are communicated to the device over a serial interface.
Separate pins for input and output data are provided, allowing concurrent writing to and
reading frqm the device. Data must be continually written for proper operation. Multiple
CS4215 devices may be attached to the same
data lines.
CS4215
Unused analog inputs that are not selected have
a very high input impedance, so they may be
tied to AGND directly. Unused analog inputs
that are selected should be tied to AGND
through a 0.1 uF capacitor. This prevents any
DC current flow.
Line Level Inputs
LINL and LINR are the line level input pins.
These pins are internally biased to the CMOUT
voltage. Figure 2 shows a dual op-amp buffer
which combines level shifting with a gain of 0.5
to attenuate the standard line level of 2 Vrms to
LlNR
(pin 16)
Example
Op-Amps
CMOUT
(pin 19)
LlNL
(pin 18)
Analog Inputs
Figure 1, the recommended connection diagram,
shows examples of the external analog circuitry
recommended around the CS4215. An internal
multiplexer selects between line level inputs and
microphone level inputs.
Input filters using a 150 n resistor and a .01 ~F
NPO capacitor to ground are required to isolate
the input op-amps from, and provide a charge reserve for, the switched-capacitor input of the
codec. The RC values may be safely changed
by a factor of two.
The HPF bit in Control Time Slot 2 provides a
high pass filter that will reduce DC offset on the
analog inputs. Using the high pass filter will
cause slight distortions at very low frequencies.
4-36
Op-amps are run
from VA1, VA2 and
AGND.
Figure 2. DC Coupled Input.
0.47 uF
Line In
Right
~ I~
~
150
UNR
(pin 16)
0.01 uF
NPO
ITo-01
7
Line In
Left
NPo
o---i~
uF
LlNL
(pin 18)
0.47 uF
Figure 3. AC Coupled Input.
DS76F2
----------------------
CS4215
R6
2.2 k
+
10uF ~ C6
R4
..-_22_._1_k_H:::C:...:.4_~
VA+
560 pF
.......---, NPO
~
C8
~0.1
8
C48
uF
R56
Microphone
InpulRighl
~
0.4; uF 150...l NPO
MINR
.'
(pin 15)
U2
C47 :& 0.Q1 uF
:;J;
CMOUT
+
C7
MINL
(Mono)
C45
7
C1
1 uF
560 pF
R57
0.47~O
Microphone
Inpul Left
(pin 17)
C4S:& 0.01 uF
NPO
2.2 k
22.1 k
R3
R1
+
10uF ~ C3
Figure 4. Optional Microphone Input Buffer
1 Vrms . The CMOUT reference level is used to
level shift the signal. This level shifting allows
the line inputs to be DC coupled into the
CS421S. Minimum ADC offset results when the
line inputs are DC coupled (see Analog Characteristics Table).
Figure 3 shows an AC coupled input circuit for
signals centered around 0 Volts. The anti-aliasing RC filter presents a low impedance at high
frequencies and should be driven by a low impedance source.
Microphone Level Inputs
Internal amplifiers with a programmable 20 dB
gain block are provided for the microphone level
inputs, MINR and MINL. Figure 4 shows a single-ended input microphone pre-amplifier stage
with a gain of 23 dB. AC coupling is mandatory
for these inputs since any DC offset on the input
will be amplified by the codec.
DS76F2
The 20 dB gain block may be disabled using the
MLB bit in Control Time Slot 1. When disabled, the inputs become line level with full
scale inputs of 1 Vrms.
Adjustable Input Gain
The signals from the microphone or the line inputs are routed to a programmable gain circuit
which provides up to 22.S dB of gain in I.S dB
steps. Level changes only take effect on zero
crossings to minimize audible artifacts, often referred to as "zipper noise". The requested level
change is forced if no zero crossing is found after Sl1 frames (10.6 ms at a 48 kHz frame rate).
A separate zero crossing detector exists for each
channel.
Analog Outputs
The analog outputs of the DACs are routed via
an attenuator to a pair of line outputs, a pair of
4-37
------------- -----------
CS4215
headphone outputs and a mono monitor speaker
output.
phone output lines are short-circuit protected.
These outputs may be muted.
Output Level Attenuator
Speaker Output
The DAC outputs are routed through an attenuator, which provides 0 dB to 94.5 dB of
attenuation, adjustable in 1.5 dB steps. Level
changes are implemented using both analog and
digital attenuation techniques. Level changes
only take effect on zero crossings to minimize
audible artifacts. The requested level change is
forced if an analog zero crossing does not occur
within 511 frames (10.6 ms at a 48 kHz frame
rate). A separate zero crossing detector exists for
each channel.
Moun and MOUT2 differentially drive a small
loudspeaker, whose impedance should be greater
than 32 n. The signal is a summed version of
the right and left line output, tapped off prior to
the mute function, but after the attenuator. The
speaker output may be independently muted.
With OLB = 0, the speaker output also contains
a 3 dB gain over the line outputs. When
OLB = 1, the speaker outputs are driven at the
same level as the line outputs.
Line Outputs
LOUTR and LOUTL output an analog signal,
centered around the CMOUT voltage. The minimum recommended load impedance is 8 ill.
Figure 1 shows the recommended 1.0 I!F DC
blocking capacitor with a 40 kn resistor to
ground. When driving impedances greater than
10 ill, this provides a high pass corner of
20 Hz. These outputs may be muted.
Headphone Outputs
HEADR and HEADL output an analog signal,
centered around' the HEADC voltage. The default headphone output level (OLB = 0) contains
an optional 3 dB gain over the line outputs
which provides reasonable listening levels, even
with small amplitude digital sources. These outputs have increased current -drive capability and
can drive a load impedance as low as 48 n. External 12 n series resistors reduce output level
variations with different impedance headphones.
The common return line from driving headphones should be connected to HEADC, which
is biased to the CMOUT voltage. This removes
the need for AC coupling, and also controls
where the return currents flow. All three head4·38
Some small speakers distort heavily when presented with low frequency energy. A high-pass
filter helps eliminate the low frequency energy
and can be implemented by AC coupling both
speaker terminals with a resistor to ground, on
the speaker side of the DC blocking capacitors.
The values selected would depend on the
speaker chosen, but typical values would be
22 I!F for the capacitors, with the positive side
connected to the codec, and 50 kn resistors.
This circuit is contained on the CDB4215 evaluation board as shown in the end of this data
sheet.
Input Monitor Function
To allow monitoring of the input audio signal,
the output of the ADCs can be routed through a
monitor path attenuator, then digitally mixed into
the input data for the DACs (see the front page
block diagram). Changes in the input gain or
output level settings directly affect the monitor
level. If full ~cale data from the ADCs is added
to full scale digital data from the serial interface,
clipping will occur.
Calibration
Both output offset voltage and input offset error
are minimized by an internal calibration cycle.
DS76F2
----------------------
CS4215
FSYNC
SCLK
CLKOUT
~ 8'5CLKOUT~
PIO Read
11 CLKOUT's
PIOWrite
Data Mode -Read and Write
TSIN~
~
SCLKSiSUL
HplORead
1 SCLK
Control Mode - Read Only
Notes:
1. DATA MODE READ - The data is sent out via SDOUT on the next frame.
2. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.
3. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.
They are independent of SCLK.
4. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.
Figure 5. PIO Pin Timing
At least one calibration cycle must be invoked
after power up. A calibration cycle will occur
immediately after leaving the reset state. A calibration cycle will also occur immediately after
going from control mode to data mode (DIe going high). When powering up the CS4215, or
exiting the power down state, a minimum of
50 ms must occur, to allow the voltage reference
to settle, before initiating a calibration cycle.
This is achieved by holding RESET low or staying in control mode for 50 ms after power up or
exiting power down mode. The input offset error
will be calibrated for whichever input channel is
selected (microphone or line, using the IS bit).
Therefore, the IS bit should remain steady while
the codec is calibrating, although the other bits
input to the codec are ignored. Calibration takes
194 FSYNC cycles and SDOUT data bits will be
zero dudng this period. The AID Invalid bit, AD!
(bit 7 in data time slot 6), will be high during
DS76F2
calibration and will go low when calibration is
finished.
Parallel Input/Output
Two pins are provided for parallel input/output.
These pins are open drain outputs and require
external pull-up resistors. Writing a zero turns on
the output transistor, pulling the pin to ground;
writing a one turns off the output transistor,
which allows an external resistor to pull the pin
high. When used as an input, a one must be written to the pin, thereby allowing an external
device to pull it low or leave it high. These pins
can be read in control mode and their state is
recorded in Control Register 5. These pins can
be written to and read back in data mode using
Data Register 7. Figure 5 shows the Parallel Input/Output timing.
4-39
.._-_
_..-_.._-_._.
__
...-.
Clock Generation
The master clock operating the CS4215 may be
generated using the on-chip crystal oscillators, or
by using an external clock source. In all data
modes SCLK and FSYNC must be synchronous
to the selected master clock.
If the master clock source stops, the digital fil-
ters will power down after 5 Ils to prevent
overheating. If FSYNC stops, the digital filters
will power down after approximately 1 FSYNC
period. The CS4215 will not enter the total
power down state.
Internal Clock Generation
Two external crystals may be attached to the
XTLlIN, XTLlOUT, XTL2IN and XTL20UT
pins. Use of an external crystal requires additional 40 pF loading capacitors to digital ground
(see Figure 1). XTALl oscillator is intended for
use at 24.576 MHz and XTAL2 oscillator is intended for use at 16.9344 MHz, although other
frequencies may be used. The gain of the internal inverter is slightly higher for XTALl,
ensuring proper operation at >24 MHz frequencies. The crystals should be parallel resonant,
fundamental mode and designed for 20 pF loading (equivalent to a 40 pF capacitor on each leg).
If XTALl or XTAL2 is not selected as the master clock, that particular crystal oscillator is
powered down to minimize interference. If a
crystal is not needed, the XTL-IN pin should be
grounded. An example crystal supplier is CAL
Crystal, telephone number (714) 991-1580.
FSYNC and SCLK must be synchronous to the
master clock. When using the codec in slave
mode with one of the crystals as master clock,
the controller must derive FSYNC and SCLK
from the crystals, i.e. via CLKOUT. Note that
CLKOUT will sto~ in a low condition within
two periods after D/C goes low.
4-40
CS4215
An internally generated clock which is 256 times
the sample rate (FSYNC rate) is output
(CLKOUT) for potential use with an external
AESIEBU transmitter, or another CS42l5. No
glitch occurs on CLKOUT when selecting alternate clock sources. CLKOUT will stop in a low
condition within two periods after Die goes low,
assuming one of the crystal oscillators is selected, or either CLKIN or SCLK is the master
clock source and is continuous. The duty cycle
of CLKOUT is 50% if the master clock is one of
the crystal oscillators and the DFR bits are 0, I,
2, 6 or 7. If the DFR bits are 3 or 5, the duty
cycle is 33% (high time). If the DFR bits are 4
then CLKOUT has the timing shown in Figure
6. If the master clock is SCLK or CLKIN, the
duty cycle of CLKOUT will be the same as the
master clock source.
1/(128 x FSYNC)
1/(128 x FSYNC)
Figure 6. CLKOUT duty cycle using theon-chip
crystal oscillator when DFR = 4
(typically FSYNC = 37.8 kHz)
External Clock
An external clock input pin (CLKIN) is provided
for potential use with an external AESIEBU receiver, or an already existing system clock.
When MCK2 = 0, the input clock must be exactly 256 times the sample rate, and FSYNC and
SCLK must be synchronous to CLKIN. When
MCK2 = 1 the DFR bits allow various divide
ratios off the CLKIN frequency.
Alternatively, an external high frequency clock
may be driven into XTLlIN or XTL2IN. The
correct clock source must be selected using the
MCK bits. Manipulating DFR bits will allow
various divide ratios fr9m the clock. to be seDS76F2
.._-_
._.-.
_.-_..--__
...
CS4215
lected. SCLK and FSYNC must be synchronous
to the external clock.
or 256 bits per frame, thereby allowing for 1, 2
or 4 CS4215s connected to the same bus.
As a third alternative, SCLK may be programmed to be the master clock input. In this
case, it must be 256 times Fs.
In a typical multi-part scenario, one CS4215 (the
Serial Interface
The serial interface of the CS4215 transfers digital audio data and control data into and o&t of
the device. Multiple CS4215 devices may share
the same data lines. DSP's supported include the
Motorola 56001 in network mode and a subset
of the 'CHI' bus from AT&TlIntel.
Serial Interface Signals
master) would generate FSYNC and SCLK,
while the other CS4215s (the slaves) would receive FSYNC and SCLK. The CLKOUT of the
master would be connected to the CLKIN of
each slave device as shown in Figure 7. Then,
the master device would be programmed for the
desired sample frequency (assuming one of the
crystals is selected as the clock source), the number of bits per frame, and for SCLK and FSYNC
to be outputs. The slave devices would be programmed to use CLKIN as the clock source, the
same number of bits per frame, and for SCLK
and FSYNC to be inputs. Since CLKOUT is al-
Figure 7 shows an example of two CS4215 devices connected to a common controller. The
Serial Data Out (SDOUT) and Serial Data In
(SDIN) lines are time division multiplexed between the CS4215s.
The serial interface clock, SCLK, is used for
transmitting and receiving data. SCLK can be
generated by one of the CS4215s, or it can be
input from an external SCLK source. When generated by an external source, SCLK must be
synchronous to the master clock. Data is transmitted on the rising edge of SCLK and is
received on the falling edge of SCLK. The
SCLK frequency is always equal to the bit rate.
CS4215
SClK
SDiN
SDOUT
Controller
SClK
XTlllN
SDIN
XTll0UT
~
f-I
SDOUT
FSYNC
L
TSIN
,-
TSOUT
D/C
A
FSYNC
XTl21N
XTL20UT
Die
~
f-I
Master
PDN
ClKOU
RESET
r--
CS4215
t-----'
'--t-----'
~
SClK
ClKIN
SDIN
r--
SDOUT
The Frame Synchronizing signal (FSYNC) is
used to indicate the start of a frame. It may be
output from one of the CS4215s, or it may be
generated from an external controller. If FSYNC
is generated externally, it must be high for at
least 1 SCLK period, and it must fall at least
2 SCLKs before the start of a new frame (see
Figure 8). It must also be synchronous to the
master clock. The frequency of FSYNC is equal
to the system sample rate (see Figure 8). Each
CS4215 requires 64 SCLKs to transfer all the
data. The SCLK frequency can be set to 64, 128,
DS76F2
FSYNC
'------'
TSIN
,--
TSOUT
DIG
B
Slave
PDN
RESET
•
•
•
•
Figure 7. Multiple CS421S's
4-41
-
-____-_
.. ...-..
-. ..---
CS4215"
FSYNC
TSINA
TSn
I·
TSOUTA
TSINB
n
DEVICE A
DEVICEB
--------------~~------------
----------------------~
1/Frame Rate or 1/System Sample Rate
T1
TSOUTB
TSn
Time slot numbers
Figure 8. Serial Interface Timing for 2 CS4215's
TSOUT
n
--------------------~
~----
Figure 9. Frame Sync and Bit Offset Timing
n:,~~ri16465666768,1281
SCLK
FSYNC
TSINA
TSOUTA,
TSIN B
TSOUT B
SDIN
SDOUT
~
~
~
.
J ~~~ ~~
~
~'"
In
_ _ _ _ _ _--!~
I
~
~
-rT7CT-::--,----:-:--:--!fi
Control to A ~
r-----i~
--1
~
fi
~~
Control to B
fi
~
fi
0
~
~
fi
~~
~
in
~
~~1Jl
?afi
--------!fi
-~I Control Mode
DIC
2345,646566
1J1JUlJ1flJ1JUUlrull1JU1J
U U U u
, -__~,,~~~~~
'
Control to A
Control from A
L--
?afi
'?ic-------~
~
,
0==
~
~
Control from B
~
~~_ _ _ _ _-,I '
r-
Figure 10. Control Mode Timing for 2 CS4215's
4-42
DS76F2
---------------------ways 256 times the sample frequency and scales
with the selected sample frequency on the master, the slave devices will automatically scale
with changes in the master codec's sample frequency.
CS4215s are time division multiplexed onto the
bus using the Time Slot Out (TSOUT) and Time
Slot In (TSIN) signals. TSOUT is an output signal that is high for one SCLK bit time, and
indicates that the CS4215 is about to release the
bus. TSIN is an input signal that informs the
CS4215 that the next time slot is available for it
to use. The first device in the chain uses FSYNC
as its TSIN signal. All subsequent devices use
the TSOUT of the previous device as its TSIN
input. TSIN must be high for at least 1 SCLK
period and fall at least 2 SCLKs before start of a
new frame.
Serial Interface Operation
The serial interface format has a variable number
of time slots, depending on the number of
CS4215s attached to the bus. All time slots have
8 bits. Each CS4215 requires 8 time slots (64
bits) to communicate all data (see Figure 9).
CONTROL MODE
The Control Mode is used to set up the CS4215
for subsequent operation in Data Mode by loading the internal control registers. Control mode is
asserted by bringing DIe low. If DIe is low during power up, then the CS4215 will enter control
mode immediately. The SCLK and FSYNC pins
are tri-stated, and the CS4215 will receive SCLK
and FSYNC from an external source. If the
CS4215 is in master mode (SCLK and FSYNC
are outputs) and DIe is brought low, then SCLK
& FSYNC will continue to be driven for a minimum of 4 and a maximum of 12 SCLKs, if the
ITS bit = o. If ITS is 1, SCLK and FSYNC will
three-state immediately after Die goes low. If
Die is brought low when the codec is programmed as master with ITS=O, the codec will
DS76F2
CS4215
timeout and release FSYNC and SCLK within
lOOlls. The values in the control registers ·for
control of the serial ports are ignored in control
mode. The data received on SDIN is stored into
the control registers which have addresses
matching their time slots. The data in the registers is transmitted on SDOUT with the time slot
equal to the register number (see Figure 10).
The steps involved when going from data mode
to control mode and back are shown in the flow
chart in Figure 11.
Control Formats
The CS4215 control registers have the functions
and time slot assignments shown in Table 1. The
register address is the time slot number when
Die is O. Reserved bits should be written as 0
and could be read back as 0 or 1. When comparing data read back, reserved bits should be
masked. The SDOUT pin goes into a
high-impedance state prior to Time Slot 1 and
after Time Slot 8. The data listed below the register is its reset state.
The parallel port register is used to read and
write the two open-drain input/output pins. The
outputs are all set to 1 on RESET. PIO bits are
read only in control mode. Note that, since PIO
signals are open drain signals, an external device
Time slot
1
2
3
4
5
6
7
8
Description
Status
Data Format
Serial Port Control
Test
Parallel Port
RESERVED
Revision
RESERVED
Table 1. Control Registers
4·43
--------------_._-----
CS421S
may drive them low even when they have been
programmed as highs. Therefore, the value read
back may differ from the value written. In the
data mode, (D/C::::1), this register can be read
and written to through the serial port as part of
the Input Settings Registers. In control mode,
(D/C=O) these bits can only be read.
4·44
DS76F2
----------------------
CS4215
Wait at least 12 SCLK
periods for FSYNC and
SCLK to three-state
Y
Codec programmed for
Master mode & ITS=O?
1 This is a software design choice,
not a run-time conditional branch.
Poll for CLB=O? 1
N
n=5
Read back and verify control information.
Mask off reserved bits
N
CLB=O?
n = O? /-'-'N_ _----'
~--~~====~--------~Y
two more frames of valid
control information 2
Y
Is codec
programmed for
Master mode?
2 This will cause the codec to
ignore any further bus activity.
The SDOUT pin will be held in
the high impedance state after
transmitting 1 frame with CLB=1
Transmit/receive data with attenuated outputs
and muted speaker for 194 FSYNC cycles
while codec executes offset calibration
Figure 11. Control Mode Flow Chart
DS76F2
4-45
- ... --------------------
CS4215
Control Time Slot 1, Status Register
07
06
05
04
03
02
Register
o
o
1
MLB
OLB
CLB
Reset (R)
o
o
o
0
BIT
RSRV
ClB
NAME
Reserved Bits
Control latch Bit
1
OlB
Output level Bit
0
Microphone level
DO
RSRV
.X
X
FUNCTION
Must be written as O.
R Ensures proper transition between control and
data mode.
R Line full scale outputs are 2.8 Vpp (1 Vrms)
Headphone full scale output is 4.0 Vpp.
Speaker full scale output is 8.0 Vpp.
Line and Headphone full scale outputs are
2.0 VPP. Speaker full scale output is 4.0 Vpp.
R 20 dB Fixed Gain Enabled
Full scale microphone inputs are 0.288 Vpp.
20 dB Fixed Gain Disabled
Full scale inputs are 2.88 VPP.
VALUE
1
MlB
01
0
1
Control Time Slot 2, Data Format Register
03
02
01
DO
HPF I RSRV I DFR2
DFR1
DFROI
ST
DF1
DFO
X
0
0
0
0
07
Register
Reset (R)
BIT
DF1-0
0
NAME
Data Format
Selection
ST
Stereo Bit
DFR2-0
Data Conversion
Frequency Selection
06
4-46
Reserved Bit
High Pass Filter
04
0
VALUE
00
0
01
1
10
2
11
3
0
1
000
001
010
01 1
100
1 01
110
111
RSRV
HPF
05
0
1
0
1
2
3
4
5
6
7
R
R
R
R
FUNCTION
16-bit 2's-complement linear.
8-bit ~-law.
8-bit A-law.
8-bit unsigned linear.
Mono Mode.
Stereo Mode.
XTAl1(kHz)
XTAL2 (kHz)
elKIN H
21 :276 M!::!z; 16.~a44 M!::!z
3072
8
5.5125
1536
16
11.025
896
27.42857
18.9
768
32
22.05
448
NA
37.8
384
NA
44.1
33.075
512
48
2560
9.6
6.615
Must be written as 0
Disabled.
Enabled. A Digital High Pass Filter is used to force
the ADC DC offset to zero.
DS76F2
----------------------
CS4215
Control Time Slot 3, Serial Port Control Register
07
Register
ITS
Reset (R)
o
BIT
XEN
NAME
Transmitter Enable
XCLK
Transmit Clock
06
I MCK2
o
05
04
o
o
VALUE
0
1
0
R
R
1
BSEL1-0
MCK2-0
ITS
Select Bit Rate
Clock Source Select
00
01
10
11
000
0
1
2
3
0
001
01 0
01 1
1 00
1
2
3
4
Immediate ThreeState
03
02
01
MCK1 MCKO IBSEl1 BSElO I XClK
0
R
R
R
1
o
00
I XEN I
o
FUNCTION
Enable the serial data output.
Oisable (high-impedance state) serial data output.
Receive SCLK and FSYNC from external source
SLAVE Mode
Generate SCLK and FSYNC
MASTER Mode
64 bits per frame.
128 bits per frame.
256 bits per frame.
Reserved.
SCLK is master clock, 256 bits per frame.
BSEL must equal 2, and XCLK must equal O.
XTAL 1, 24.576 MHz, is clock source.
XTAL2, 16.9344 MHz, is clock source.
CLKIN is clock source, and must be 256xFs.
CLKIN is clock source, OFR2-0 select sample
frequency.
SCLK and..fSYNC three-state up to 12 clocks
after O/C goes low.
SCLK and..fSYNC three-state immediately
after O/C goes low.
Control Time Slot 4, Test Register
07
06
05
Register
Reset (R)
BIT
OAO
NAME
Loopback Mode
ENL
Enable Loopback
Testing
Test bits
TEST
DS76F2
04
03
TEST
o
o
o
VALUE
0
1
0
1
0
o
02
01
00
ENl
DAD
000
FUNCTION
R Digital-Digital Loopback.
Digital-Analog-Digital Loopback.
R Disable.
Enable.
The TEST bits must be written as zero, otherwise
special factory test modes may be invoked.
4·47
-
.._-_
.-_
_
..--_._.
__
...-.
CS4215
Control Time Slot 5, Parallel Port Register
07
06
05
04
0302
01
00
Register lC-:-po.::lo:....:1_"-pl:..;:o:..::o_IL-_ _ _ _ _ _
, ""RS=R""V"---_ _ _ _ _------'
X
Reset (R)
BIT
RSRV
P101-0
NAME
Reserved Bits
Parallel 110 Bits
X
VALUE
11
3
X
X
X
X
FUNCTION
Must be written as o.
R See the Parallel InpuVOutput Section.
Control Time Slot 6, Reserved Register
07
06
05
Reset (R)
03
04
Register I
02
01
00
X
X
X
RSRV
X
X
NAME
Reserved Bits
X
X
X
FUNCTION
Must be written as O.
VALUE
Control Time Slot 7, Version Register
07
Register I
Reset (R)
BIT
VER3-0
NAME
Oevice Version
Number
RSRV
Reserved Bits
06
05
04
X
X
03
I VER3
RSRV
X
VALUE
0000
0
0001
1
0010
2
X
0
02
01
00
VER2
VER1
VERol
0
0
FUNCTION
"C". See Appendix A.
"0". See Appendix A.
R "E". This Oata Sheet
Must be written as
o.
Control Time Slot 8, Reserved Register
Register
Reset (R)
NAME
Reserved Bits
4-48
07
06
05
04
X
X
X
X
I
03
02
01
00
X
X
X
RSRV
VALUE
X
FUNCTION
Must be written as O.
DS76F2
---------------------.
CS4215
128 1
SCLK
2
3
4 2 64 65 66 67 68 69 %.
128 1
2
3
4
~n n n n n I
U U U U1~nununununun~
u u u u u
n n n n
~
~
~
F~~~~J ~~~~ 1'---_
~
n
TSOUTA,
~
TSIN B _ _ _ _ _ _---;~
~
~
~
~--------
I
~
~I-Sl-~
i11
i11
i11
TSOUT B
---------;i11i11
SDIN
-r~~------;~I
Data to A
~
P
OIX
~
~
c=J(
Data to B
SDOUT
-
D/C
,---------'~
Data from A ~
L -_ _ _ _----'~
~p
~
Data from B
~
~
~
~
iii
Data from A
.~_ _ _ __ _
~--------
j'-----------.;i11
Data Mode
Data to A
i11
~
Figure 12. Data Mode Timing for 2 CS421S's
DATA MODE
Time slot
1
The data mode is used during conversions to
pass digital data between the CS4215 and external devices. The frame sync rate is equal to the
value of the conversion frequency set by the
DFR2-DFRO bits of the Data Format register.
Each frame has either 64, 128, or 256 bit times
depending on the BSEL bits in the Serial Control
register. Control of gain, attenuation, input selection and output muting are embedded in the data
stream.
Description
Left Audio MS8 bits
Left Audio LS8 bits
Right Audio MS8 bits
Right Audio LS8 bits
Output Setting
Output Setting
Input Setting
Input Setting
2
3
4
5
6
7
8
Table 2. Data Registers
Data Formats
+ffi.-------~------~
All time slots contain 8 bits. The MSB of the
data is transmitted/received first. The CS4215
data registers have the functions and time slot
assignments shown in Table 2. The register address is the time slot number when Die is 1. The
SDOUT pin goes into a high-impedance state
prior to time slot 1 and after Time Slot 8 (see
Figure 12).
w
:::>
~
Cl 0
- - - - - - - - - - -
~
-FS
The CS4215 supports four audio data formats:
16-bit 2's-complement linear, 8-bit unsigned linear, 8-bit A-Law, and 8-bit I!-Law. Figure 13
illustrates the transfer characteristic for 16-bit
and 8-bit linear formats. Note that a digital code
DS76F2
8-bit
unsigned:
0
65
2.i ~~~p: -32768
-16384
t28
0
DIGITAL CODE
191
255
16384
32767
Figure 13. Linear Data Formats
4-49
_.-_..--_._.
__.._-_
...-.
C$4215
+FS~--------------------------~
(12) bits for the DACs and compressed from the
upper 13 (12) bits to 8 bits for the ADCs.
Data Time Slot 1 &2, Left Channel Audio Data
~
....
~
0
~
- - - - - -
~-~-~-~--~--~-~- -
- - - - --
-FS+-------.--------.:.-t---------.-----------l
A-Law: 2Ah
u-Law:
OOh
15h
3Fh
95h
BFh
55h1D5h
7FhIFFh
AAh
Time slot 1 and 2 contain audio data for the left
channel. In mono modes, only the left channel
data is used, however both the right and left
output DACs are driven. In 8-bit modes, only
time slot 1 is used for the data.
Data Time Slot 3&4, Right Channel Audio Data
BOh
DIGITAL CODE
Figure 14. Companded Data Formats
of 128 (80 Hex) is considered analog zero for
the 8-bit unsigned format.
A non-linear coding scheme is used for the companded formats as shown in Figure 14. This
scheme is compatible with CCITT G.711. Companding uses more precision at lower amplitudes
at the expense of less precision at higher amplitudes. Jl-Law is equivalent to 13 bits at low
signal levels and A-Law is equivalent to 12 bits.
This low-level dynamic range is obtained at the
expense of large-signal dynamic range which,
for both Jl-Law and A-Law, is equivalent to
6 bits. The CS4215 internally operates at 16 bits.
The companded data is expanded to the upper 13
Time slot 3 and 4 contains audio data for the
right channel. In mono modes, the right ADC
outputs zero and the right DAC uses the left
digital data. In 8-bit modes, only time slot 3 is
used for the data.
Figure 15 summarizes all the time slot bit allocations for the 4 data modes and for control mode.
Reset
RESET going low causes all the internal control
registers to be set to the states shown with each
register description. RESET must be brought low
and. high at least once after power up. RESET
returning high causes the CS4215 to execute an
offset calibration cycle. RESET or Die returning
high should occur at least 50 ms after the power
supply has stabilized to allow the voltage reference to settle.
Data Time Slot 5, Output Setting
Register
07
06
05
04
03
02
01
DO
IL-'H-"E"____L-'L~E"____L_':L~O~5_~L~O:::!.4_~L!::':O~3_~LO!::':2~__"'LO~1_=LO~O~
Reset (R)
BIT
L05-0
LE
HE
4-50
0
NAME
Left Channel Output
Attenuation Settine
Line Output Enable
Headphone Output
Enable
0
FUNCTION
VALUE
111111 63 R 1.5dB attenuation steps. L05 is the MSB.
0- no attenuation. 111111 - -94.5dB
R Analog line outputs off (muted).
0
1
Analog line outputs on.
0
R Headphone output off (muted).
Headphone output on.
1
DS76F2
----------------------
CS4215
Data Time Slot 6, Output Setting
07
Register
06
Reset (R)
BIT
R05-0
05
04
03
02
D1
DO
--,-A=D:..:.I----,-----,S=-:E=--L.:..:R=O=S----,Rc-=-O=-4-,------,R:..:.O=-3=-----=R:..:.O=2=-----=,-,-R=O-=-1_-,-,R=O=O-,
LI
0
SE
NAME
Right Channel
Output Attenuation
Settina
Speaker Enable
ADI
AID Data Invalid
FUNCTION
VALUE
111111 63 R 1.5dB attenuation steps. ROS is the MSB.
0= no attenuation. 111111 = -94.SdB
Not used in mono modes.
0
R Speaker off (muted).
1
Speaker on.
AID data valid.
0
1
R AID data invalid. Busy in calibration.
Data Time Slot 7, Input Setting
07
Register
06
0
Reset (R)
BIT
LG3-0
05
04
03
02
D1
DO
-'-P::..::IO:...;1_-'-P::..::IO:...::o----'--1-=O--'-V-'-'R----'--_I=-=S'--"--=L=G=-3_-=L=G=2_-=LG=-=-1_-=LG=O=-,
LI
IS
NAME
Left Channel Input
Gain Settina
Input Select
OVR
Overrange
0
1
0
P101-0
Parallel 110
11
0
VALUE
0000
3
0
0
0
0
FUNCTION
R 1.SdB gain steps. LG3 is the MSB.
0= no aain 1111 = 22.SdB aain.
R Line level inputs (UNL, UNR).
Microphone level inputs (MINL MINR).
R When read as 1, this bit indicates that an input overrange condition has occurred. The bit remains set
until cleared by writing 0 into the register. Writing
a 1 enables the overrange detection. The bit will
remain 0 until an over-range occurs. Serial port .
clear has priority over internal settinas.
R Parallel input/output bits.
Data Time Slot 8, Input Setting
D7
D6
05
D4
Register 1 MA3
MA2
MA1
MAO
Reset (R)
BIT
RG3-0
MA3-0
DS76F2
1
NAME
Right Channel Input
Gain Setting
Monitor Path
Attenuation
D3
02
D1
DO
I RG3
RG2
RG1
RGO
0
0
0
0
VALUE
0000
1111
I
FUNCTION
R 1.SdB gain steps. RG3 is the MSB.
0- no aain 1111 - 22.5dB gain.
15 R 6dB attenuation steps. MA3 is the MSB.
0- no attenuation, 1111 - mute.
4-51
""
~
.-,
'.---,b.
=••
7
6
RO
I PIO
RO
I PIO
RO
I PIO
RO
I PIO
8
i!!
ci
en
f)
-'"
Ut.
c
~.
~
Figure 1 5. Time SlotiRegister Overview
_.-_..--_._.
__.._-_
...-.
CS4215
CS4215
AI~
S DIN
Decode
DAD
DD
Digital-Digital
I
SDO UT
Loopback
I
I
AI~
Encode
fc?i
D/A
I
I
I
I
AID
LOUT
ROUT
(Still Operate)
DigitalAnalogDigital
Loopback
I
Monitor=!!!!
(Full Mute)
I
II
Attenuation
Gain
I
I
1
LIN
RIN
(Disconnected)
CS4215
1------+1
SDIN
LOUT
ROUT
(DAC data = 0)
o is different for
each data
format
r -_ _~~~~~::::~~~::~~----~~-t-ADA
/+------1
SDOUT
LIN
RIN
Figure 16. DD, DAD & ADA Loopback Paths
Power Down Mode
LOOPBACK TEST MODES
Bringing the PDN pin high puts the CS4215 into
the power down mode. In this mode HEADC
and CMOUT will not supply current. Power
down will change all the control registers to the
reset state shown under each Control Time Slot
register. In the power down mode, the TSOUT
pin will follow the TSIN state with less than
10 ns delay.
The CS4215 contains three loopback modes that
may be used to test the codec. Two of the loopback test modes are designed to allow the host to
perform a self-test on the CS4215. The third
mode allows laboratory testing using external
equipment.
Host Self-Test Loopback Modes
After returning to normal operation from power
down, an offset calibration cycle must be executed. Either bringing RESET low then high, or
updating the control registers, will cause an offset calibration cycle. In either case, a delay of
50 ms must occur after PDN goes low before
executing the offset calibration. This allows the
internal voltage reference time to settle.
Since the CS4215 is a mixed-signal device, it is
equipped with an internal register that will enable the host to perform a two-tiered test on
power-up or as needed. The loopback test is enabled by setting the Enable Loopback bit, ENL,
in control register 4. The first tier of loopback is
a digital-digital loopback, DD, which is selected
by clearing the DAD bit in control register 4
DS76F2
4-53
_-_
.....-._.
_.-_..-_-,
...-.
CS4215
(see Figure 16). DD loopback checks the interface between the host and the CS4215 by taking
the data on SDIN and looping it back ontQ
SDOUT, with the data on SDOUT being one
frame delayed from the data on SDIN. The host
can verify that the data received is exactly the
same as the data sent, thereby indicating the interface between the two devices and the digital
interface on the CS4215are operating properly.
The output DAC's are functional in DD loopback. Now that the interface has been verified,
the rest of the CS4215 can be tested using the
second tier of loopback.
The second tier of loopback is a digital-analogdigital loopback, DAD, which is selected by
setting the DAD bit in control register 4. DAD
loopback checks the analog section of the
CS4215 by connecting the right and left analog
outputs, after the output attenuator, to the analog
inputs of the gain stage. This allows testing of
most of the CS4215 from the host by sending a
known digital signal to the DACs and monitoring the digital signal from the ADCs. During
DAD loopback, the monitor attenuator must be
set at maximum (full mute), and the analog outputs may be individually muted. The analog
inputs are disconnected internally. The flow of
test data for both DD and DAD loopback modes
is illustrated in the top portion of Figure 16.
Analog-to-Analog Loopback Mode
A third loopback mode is achieved by setting the
monitor attenuator to zero attenuation and sending theDACs digital zero via SDIN. This
loopback is termed analog~digital-analog, ADA,
since the selected analog input will now appear
on the enabled analog outputs. Since this test is
controlled by external stimulus and the host is
not involved (except to send the DACs zeros), it
is generally considered a laboratory test as opposed to a self test. The bottom portion of
Figure 16 illustrates the ADA signal flow
through the CS4215. Note that this test requires
the host send analog zeros to the DAC. Each
data format has a different code for zero. See
Figures 13 and 14.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
+5V
Supply
CS4215
Figure 17. Optional Power Supply Arrangement
4-54
DS76F2
.._-_
.-_
..--_._.
__
...-.
CS4215
~1/8"
Digital
Ground
Plane
Ground
Connection
1r
.- r-.
Note that the CS4215
is oriented with its
digital pins towards the
digital end of the board.
Analog
Grbuitd
Plahe
I~S42151
+5V
Ferrite
Bead
~I
I~
Codec
digital
signals
CPU & Digital
Logic
Codec
analog
signals &
Components
Figure 18. Suggested Layout Guideline
POWER SUPPLY AND GROUNDING
When using separate supplies, the digital power
should be connected to the CS4215 via a ferrite
bead, positioned closer than 1" to the device (see
Figure 1). The codec VAl, VA2 pins should be
derived from the cleanest power source available. If only one supply is available, use the
suggested arrangement in Figure 17. VAl supplies analog power to the ADCs and DACs while
VA2 supplies power to the output power drivers
(headphones and speaker). The large currents
necessary for VA2 are not flowing through the
2.0 Q resistor, and therefore do not corrupt the
VAl converter supply.
The CS4215 along with associated analog circuitry, should be positioned near to the edge of
the circuit board, and have its own, separate,
ground plane. On the CS4215, the analog and
digital grounds are internally connected; therefore, the four ground pins must be externally
connected with zero impedance between ground
pins. The best solution is to place the entire chip
DS76F2
on a solid ground plane as shown in Figure 18.
Preferably, it should also have its own power
plane. A single connection between the CS4215
ground and the board ground should be positioned as shown in Figure 18.
Figure 19 illustrates the optimum ground and decoupling layout for the CS4215 assuming a
surface-mount socket and leaded decoupling capacitors. Surface-moun! sockets are useful since
the pad locations are exactly the same as the actual chip; therefore, given that space for the
socket is left on the board, the socket can be optional for production. Figure 19 depicts the top
layer containing signal traces and assumes the
bottom or inter-layer contains a solid analog
ground plane. The important points with regards
to this diagram are that the ground plane is
SOLID under the codec and connects all codec
ground pins with thick traces providing the absolute lowest impedance between ground pins. The
decoupling capacitors are placed as close as possible to the device which, in this case, is the
socket boundary. The lowest value capacitor is
4-55
.-_
_
..--_
__.._-_
...-..
CS4215
r----------~---------.
I
I
00000000000
10
10
10
10
10
+
~. :;b
Digital
Supply
.. Analog
Supply
;~<~-.
~I
0
cil
I 061";'(;.
:
- - -;-
00000000000
u;-~
q----------
I
~
+
Figure 19. CS4215 Decoupling Layout Guideline
00000000000
o
lL
"
Analog
Supply
+
10uF
Figure 20. CS4215 Surface Mount Decoupling Layout
4-56
DS7SF2
---------------------placed closest to the codec. Vias are placed near
the AGND and DGND pins, under the IC, and
should be attached to the solid analog ground
plane on another layer. The negative side of the
decoupling capacitors should also attach to the
same solid ground plane. Traces bringing the
power to the codec should be wide thereby keeping the impedance low.
CS4215
10
0+-~-~-~~"'-, - -,- - -,- -, - -,- --10 - - - - - - - - - - - - - - - - - - - - - - - - I
"
' "
I
m -20
~
(J)
-30
"C
-40
Ol
-50
:Ec:
'"
:::;:
-60
-70
- - -, - - ,- - -
-80
-90
Although not shown in the figures, the trace layers (top layer in the figures) should have ground
plane fill in-between the traces to minimize coupling into the analog section. See the CDB4215
evaluation board data sheet for an example layout.
- - '. - - - - '. - -
-100 -t---t----j-----j----j---T-"--t---LL--t-'---'--'r--'---'--t--'------I
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (Fs)
Figure 21. ADC Frequency Response
If using all surface-mount components, the de-
coupling capacitors should still be placed on the
layer with the codec and in the positions shown
in Figure 20. The vias shown are assumed to attach to the appropriate power and analog ground
layers. Traces bringing power to the codec
should be as wide as possible to keep the impedance low. For the same reason, vias should be
large for power and ground runs.
-0.
![ -0.1
(J)
~ -0.
.§,
-0.
'"
:::;: -0.4
-0.
-0.6
- -,- - " - - ,- - -' - - , - - '- - -' - -
If using through-hole sockets, effort should be
-0.7
made to find a socket with the minimum height
which will minimize the socket impedance.
When using a through-hole socket, the vias under the codec in Figure 19 are not needed since
the pins serve the same function.
-0.81-t-___I_---t--1----j---t-___I_---t--1----t'-----J
0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 22. ADC Passband Ripple
o~------~~------------------,
-10
ADC and DAC Filter Response Plots
Figures 21 through 27 show the overall frequency response, passband ripple and transition
band for the CS4215 ADCs and DACs. Figure 27 shows the DACs' deviation from linear
phase. Fs is the selected sample frequency. Since
the sample frequency is programmable, the filters will adjust to the selected sample frequency.
Fs is also the FSYNC frequency.
c
- - ,- - " - - ,- - -,-
-20
m
~ -30
(J)
~
'§,
-40
-50
~
-60
-
.,.
-
.,
-
-
,.
-
-
-;
-
- .,. -
.,.
-;
- - ,. - .,. - .. - .,. - -
-
,.
-
.,.
-70
·80
- - - - - - - '. - .' - - .: - - '. - - -
-90
- - '. - .' - - '. - .' - -
J
-
i
-
.,-
-
-
-
-100-t-___I_---t--t-----t---t---t---t--T-"--t----j
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 23. ADC Transition Band
DS76F2·
4-57
----------------------
CS421S.
0.2-r<:--~-~-;-------'A""-'-"~~-r<:--;;:----'
10
0.1
-10
10 -20
~
-0.1
-30
]i'"
-0.2
~
:E'"
"C
-4
§, -50
co
::;: -60
~
-0.4
-70
-0.5
-80
-0.6
-90
-0.7
-100
0.0
- '.
§, -0.3
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (Fs)
-0.81+-~r-_t_--_r_______j--_t_---t---r-_r---r----j
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 25. DAC Passband Ripple
Figure 24. DAC Frequency Response
2 . &r--------~-~-~--~
-1
-,-
-100H---r--+--~--r-~---r--r-~---r-4
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 26. DAC Transition Band
4-58
-2 . ~--_r_______j--_t_--_r_______j,-_t_--_r___--r__r~
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 27. DAC Deviation from Linear Phase
DS76F2
.._-_
_-_..--_._.
__
...-.
•
CS4215
PIN DESCRIPTIONS
...
I-
3:
~
~
0
0
XTL10UT
1
2
VD2
4
DGND2
6
XTL21N
8
XTL20UT
10
0
~
0
~
..J
0
z
52
...
0
>
..J
r--
In
'" '" '"'"
I-
C
z z
Cl
C
C
~
0
is c
III
III
~
..J
0
III
r-- In
Oi '"
co co co '"
co
0
z
>
III
IL
I~
0
III
l-
co '"r--
z
in
I-
r--co
r--r--
CS4215
1OO-PIN
TQFP
(Q)
Top View
RESET
14
PDN
16
MINR
18
LlNR
20
MINL
22
LlNL
24
25
co
C\I
C;;
'"'" '" '"r-- '"'"
l-
W
II:
~
0
0==
In
lL
>
... ...
C
Z
Cl
c(
N
> ~
c(
:;
N
C
Z
Cl
c(
'"v
~
~.
0
In
v
75
74
PI01
72
PlOD
70
D/C
66
LOUTR
64
LOUTL
60
HEADL
56
HEADC
52
51
HEADR
III'
0
In
1=
~
0
== ==
Note: All unlabeled pins are No Connects
DS76F2
4-59
.._-_
_.-_..--_._.
__
...-.
CS421 5 "
SDIN
DGND1
SDOUT
CL~E~~ ~~~:~~~
XTL11N ~
~
XTL1OUT
./_______ TSIN
~r-'-'
~-LLLl..LLl...l...\+-l..LLl-LLL.Ll..LI---,
VD2 \ \
DGND2 ----.. \
6 4 2? 44 42 40
7
~:
NC --...//
MINR
"2;
31
20
CMOUT
NC
VREF
AGND1
~/ /
----- LOUTR
22
<'- LOUTL
'-
Top View
~~~~~18
NC
~ PI01
_______ D/C
NC
(L)
13
14
15
NC
~ PI~O
CS4215
44-PIN
PLCC
RESET /
----
39 /
XTL21N
XTL20UT ________
PDN ------
/;=
\\=
HEADL
24~2~'~::E
~~ MOUT2
NC
AGND2
VA2
VA1
Power Supply
VAl, VA2 - Analog Power Input, Pins 23(L), 24(L), 37(Q), 39 (Q)
+5 V analog supply.
AGNDI, AGND2 - Analog Ground, Pins 22(L), 25(L), 35(Q), 41(Q)
Analog ground. Must be connected to DGNDl, DGND2 with zero impedance.
VDl, VD2 - Digital Power Input, Pins 3(L), 8(L), 91(Q), 4(Q)
+ 5 V digital supply.
DGNDI, DGND2 - Digital Ground, Pin 2(L), 9(L), 89(Q), 6(Q)
Digital ground. Must be connected to AGNDl, AGND2 with zero impedance.
4-60
DS76F2
----------------------
CS4215
Analog Inputs
LINL, LINR - Left and Right Channel Line Level Inpnts, Pins 18(L), 16(L), 24(Q), 20(Q)
Line level input connections for the right and left channels.
MINL, MINR - Left and Right Channel Microphone Inpnts, Pins 17(L), 15(L), 22(Q), 18(Q)
Microphone level input connections for the right and left channels.
Analog Outputs
LOUTR, LOUTL - Line Level Outputs, Pins 33(L), 32(L), 66(Q), 64(Q)
One pair of line level outputs are provided. The output level for right and left outputs can be
independently varied. These outputs can be muted.
HEADR, HEADL - Headphone Outputs, Pins 29(L), 31(L), 52(Q), 60(Q)
HEADR and HEADL are intended to drive a pair of headphones. Additional current drive,
along with an optional +3 dB of gain, ensures reasonable listening levels. These outputs can be
muted.
HEADC - Common Return for Headphone Outputs, Pin 30(L), 56(Q)
HEADC is the return path for large currents when driving headphones from the HEADR and
HEADL outputs. This pin is nominally at 2.1 V.
CMOUT - Common Mode Output, Pin 19(L), 31(Q)
Common mode voltage output. This signal may be used for level shifting the analog inputs. The
load on CMOUT must be DC only, with an impedance of not less than lOll. CMOUT should
be bypassed with a 0.47 IlF to AGND. CMOUT is nominally at +2. IV.
MOUTl, MOUT2 - Mono Speaker Outputs, Pins 28(L), 27(L), 45(Q), 43(Q)
Mono external loudspeaker differential output connections. The loudspeaker output is a mix of
left and right line outputs. Independent muting of the speaker is provided. MOUTI and
MOUT2 output voltage is nominally at 2.1 V with no signal.
VREF - Voltage Reference Output, Pin 21(L), 33(Q)
The on-chip generated ADCIDAC reference voltage is brought out to this pin for decoupling
purposes. This output must be bypassed with a 10 IlF capacitor in parallel with a 0.1 flF
capacitor to the adjacent AGNDI pin. No other external load may be connected to this output.
Digital Interface Signals
SDIN - Serial Data Input, Pin 1(L), 87(Q)
Audio data for the DACs and control information for all functions is presented to the CS4215
on this pin.
SDOUT - Serial Data Output, Pin 44(L), 85(Q)
Audio data from the ADCs and status information concerning all functions is written out by the
CS4215 onto this pin.
DS76F2
4-61
_.-_..--_._.
__.._-_
...-.
CS4215
SCLK - Serial Port Clock, Pin 43(L), 83(Q)
SCLK rising causes the data Qn SDOUT to, be updated. SCLK falling latches the data Qn SDIN
into the CS4215. The SCLK signal can be generated Qff-chip, and input into, theCS4215.
Alternatively, the CS4215 can generate and Qutput SCLK in data mQde.
FSYNC - Frame Sync Signal, Pin 42(L), 81(Q)
The Frame SynchrQnizing Signal is sampled by SCLK, with a rising edge indicating a new
frame is abQut to, start. FSYNC frequency is always the system sample rate. Each frame may
have 64, 128 Qr 256 data bits, allQwing fQr 1, 2 Qr 4 CS4215s cQnnected to, the same bus.
FSYNC may be input to, the CS4215, Qr may be generated and Qutput by the 'CS4215 in data
mQde. When FSYNC is an input, it must be high fQr at least 1 SCLK periQd. FSYNC can stay
high fQr the rest Qf the frame, but must return IQW at least 2 SCLKs befQre the next frame
starts.
TSIN - Time Slot Input:, Pin40(L), 77(Q)
TSIN high fQr at least 1 SCLK cycle indicates to, the CS4215 that the next time slQt is allQcated
fQr it to, use. TSIN is nQrmally cQnnected to, the TSOUT pin Qf the previQus device in the chain.
TSIN shQuld be cQnnected to, FSYNC fQr the 1st (or Qnly) CS4215 in the chain.
TSOUT - Time Slot Output, Pin 41(L), 79(Q)
TSOUT gQes high fQr 1 SCLK cycle, indicating that the CS4215 is abQut to, release the data
bus. NQrmally cQnnected to, the TSIN pin Qn the next device in the chain.
D/C - Data/Control Select Input, Pin 35(L), 70(Q)
When D/C is IQw, the infQrmatiQn Qn SDIN and SDOUT is cQntrol infQrmatiQn. When D/C is
high, the infQrmation Qn SDIN and SDOUT is data infQrmatiQn.
PDN - Power Down Input, Pin 13(L), 16(Q)
When high, the PDN pin puts the CS4215 into, the PQwer dQwn mQde. In this mQde HEADC
and CMOUT will nQt supply current. PQwer dQwn causes all the cQntrol registers to, change to,
the default reset state. In the PQwer dQwn mQde, the TSOUT pin remains active, and fQllQWS
TSIN delayed by less than 10 ns.
RESET - Active Low Reset Input, Pin 12(L), 14(Q)
UpQn reset, the values Qf the cQntrQI infQrmatiQn (when D/C
values given in the Reset DescriptiQn sectiQn Qf this data sheet.
= 0)
will be initialized to, the
Clock and Crystal Pins
XTLlIN, XTLlOUT, XTL2IN, XTL20UT - Crystals 1 and 2 Inputs and Outputs, Pins 6(L),
7(L), 10(L), 11(L), 97(Q), 2(Q), 8(Q), 10(Q)
Input and Qutput cQnnectiQns fQr crystals 1 and 2. One Qf these Qscillators may provide the
master clQck to, run the CS4215.
CLKIN - External Clock Input, Pin 4(L), 93(Q)
4-62
DS76F2
.-_
_
..--_._.
__.._-_
...-.
CS4215
External clock input optionally used to clock the CS4215. The CLKIN frequency must be
256 times the maximum sample rate (FSYNC frequency).
CLKOUT - Master Clock Output, Pin 5(L), 95(Q)
Master clock output, whose frequency is always 256 times the system sample rate (FSYNC
frequency). CLKOUT is active only in data mode and is low during control mode.
Miscellaneous Pins
PIOO, PIOI - Parallel Input/Output, Pins 36(L), 37(L), 72(Q), 74(Q)
These pins are provided as general purpose digital parallel input/output and have open drain
outputs. An external pull-up resistor is required. They can be read in control mode, and read
and written to in data mode.
Note: All unlabeled pins are No Connects which should be left floating.
DS76F2
4-63
__
--------------_._----PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal codewidth. Units in LSB.
Total Dynamic Range
The rms value of a full scale signal to the lowest obtainable noise floor. It is measured by
comparing a full scale signal to the lowest noise floor possible in the codec (ie. attenuation bits
for the DACs at full attenuation.) Units in dB.
Instantaneous Dynamic Range
The dynamic range available at any instant in time. It is measured using S/(N+D) with a 1 kHz,
-60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small
input signal reduces to harmonic distortion components of the noise to insignificance. Units in
dB.
Total Harmonic Distortion
THD is the ratio of the rms value of a signal's first five harmonic components to the rms value
of the signals fundamental component. THD is calculated for the ADCs using an input signal
which is 3dB below typical full-scale, and is referenced to typical full-scale. A digital full-scale
output is used to calculate THD for the DACs.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
o dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Frequency Response
Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB.
Step Size
Typical delta between two adjacent gain or attenuation values. Units in dB.
Absolute Step Error
The deviation of a gain or attenuation step from a straight line passing through the
no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB.
4-64
DS76F2
----------------------
CS4215
Out-of-Band Energy
The ratio of the fIllS sum of the energy from 0.46xFs to 2.lxFs compared to the rms full-scale
signal value. Tested with 48kHz Fs giving an out-of-band energy range of 22kHz to 100kHz.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input at
CMOUT. For the DACs, the deviation of the output from CMOUT with mid-scale input code.
Units in volts.
DS76F2
4-65
-<
.---------_ ....
---------
CS4215
APPENDIX A
This data sheet describes. version 2 of the CS4215. Therefore, this appendix is included to describe the
differences between versions 0,1 and version 2. This information is only useful for users that still have
version 0 and version 1 devices since version 2 devices will supplant the earlier versions. The version
number can be found in control mode, time slot 7. The version can also be identified by the revision
letter stamped on the top of the actual chip. The revision letter immediately precedes the data code on
the second line of the package marking (See General Information section of the Crystal Data Book).
Version 0 corresponds to chip revision C, version 1 corresponds to chip revision D, and version 2 corresponds to chip revision E. Future chip revisions (ie. F, G, H) may still be version 2 since the version
number only changes if there is a register change to the part that will affect driver software.
The Functional Differences Between Version O(Rev. C) and Version l(Rev. D)
1. FSYNC on version 0 must be ONLY one SCLK period high, whereas on version 1 FSYNC must be
AT LEAST one SCLK period high.
2. When driving an external CMOS clock into one of the XTL-IN pins, version 0 devices must have a
series resistor of at least lkO between the CS4215 and the clock source. The resistor is needed because the codec will put XTL-IN to ground (on version 0 only) when that crystal is not selected, as is
the case on power-up. In version 1 the XTL-IN pins are floated when not selected; therefore, the series resistor is not needed on version 1. Version 1 will work properly if the resistor is included.
3. The OLB and ITS bits do not exist on version O. Writing these bits as zero makes both versions
function identically; therefore, version 1 is backwards compatible with version O.
4. When entering control mode, CLKOUT stops 4 to 12 clocks later and may start up briefly when
switching master clock sources on version O. On version 1 CLKOUT stops within two clocks and
doesn't start up until data mode is entered.
5. In version 0 the headphone and speaker outputs are not short-circuit protected, whereas in version 1
they are short-circuited protected.
The functional differences between Version l(Rev. D) and Version 2(Rev. E)
1. The MLB, HPF, and MCK2 bits in control mode do not exist in version 0 or version 1. Writing
these bits as zero makes all versions functionally identical; therefore, version 2 is backwards compatible with previous versions.
2. The NO invalid bit, ADI, in data mode does not exist in version 0 or version 1.
3. The 8-bit unsigned data format (DFt,0=3) does not exist in version 0 or version 1.
4. SDOUT contained random data during calibration in versions 0 and 1. SDOUT outputs zeros during
calibration in version 2.
4-66
DS76F2
.... ...
..........
.. ...
."."
~
~
~~
CDB4215
~
Semiconductor Corporation
CS4215 Evaluation Board
Features
General Description
• Easy DSP Hook-Up
• Correct Grounding and Layout
• Microphone Pre-Amplifier
The CDB4215 evaluation board allows easy evaluation
of the CS4215 audio multimedia codec. Analog inputs
provided include two 1/4" microphone jacks and two
BNC line inputs. Analog outputs provided are two BNC
line outputs, one stereo 1/4" headphone jack and one
pair of speaker terminals.
Digital interfacing is facilitated by two buffered ribbon
cable headers. One contains the serial port and the
other contains the codec control pins.
• Line Input Buffer
• Digital Patch Area
ORDERING INFORMATION: CDB4215
+5VA
Microphone
Jacks
DGND +5VD
AGND
LL~=t1
@)
Line Inputs
A=- 6 dB
00
00
00
00
00
Digital
1/0
CS4215
Buffers
Speaker
Terminals
Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Control
Pin
Header
Serial
Port
Header
c::::::J
Headphone
Jack
ClKIN
c::::::J
.? PIO
Indicators
Copyright © Crystal Semiconductor Corporation 1992
(All Rights Reserved)
Digital
Patch
Area
JUL '93
DS76DB3
4-67
_I
-----------,----------GENERAL INFORMATION
TheCDB4215 is designed to provide an easy
platform for evaluating the performance of the
CS4215 Multimedia Audio Codec. The board
provides a buffered serial interface for easy connectioh to the serial port of a DSP or other serial
device. A single +5 V power supply is all that is
required to power the evaluation board.
The line input buffers are designed to accept
standard CD-level inputs of 2 VRMS and BNCto-phono adapters are included ,to support
various test setups. The microphone inputs consist of two 1/4" mono jacks that are designed to
accept standard single-ended dynamic or condenser microphones.
The line outputs are supplied via BNC jacks
with two more BNC-to-phono ada¥ters. The
headphone output is supplied via a 14" stereo
jack and will drive headphones of 48 n or
greater. This includes most "walkman" style
headphones. Speaker terminals are provided and
can be connected to speakers with an impedance
of 32 n or greater.
The film plots of the board are included to provide an example of the optimum layout,
grounding, and decoupling arrangement for the
CS4215.
POWER SUPPLY CIRCUITRY
Figure 1 illustrates a portion of the CDB4215
schematic and includes the CS4215 codec along
with power supply circuitry. Power is supplied to
the board via two sets of binding posts, 'one for
digital and one for analog. The analog supply
must be +5 Volts and supplies power for the entire codec (both digital and analog power supply
pins) along with the analog input buffers for the
line and microphone inputs. The digital supply is
also +5 Volts and supplies power to the digital
4-68
COB4215,
header buffer circuitry. Space for a ferrite bead
inductor, L1, has been provided so that the board
may be modified to power the codec from 'the
digital supply. Selection of L1 will depend on
the characteristics of the noise on the digital supply used.
ANALOG INPUTS
The analog inputs consist of a pair of 1/4" jacks
for two microphones, and a pair of BNC's for
line level inputs. BNC-to-phono adapters are included to allow testing of the line inputs using
coax or standard audio cables.
The line-level inputs go through a buffer, Figure 2, with a gain of 0.5 which allows input
signals of up to 2 VRMS. '
The two microphone inputs are single-ended and
are designed to work with both condenser and
dynamic mics. The microphone input buffer circuit, shown in Figure 3, has a gain of 23 dB
thereby defining a full-scale input voltage to the
mic jacks of 19.5 mVpp.
ANALOG OUTPUTS
The CDB4215 includes three analog outr.ut
paths: a pair of line output BNC's, a stereo 14"
headphone jack, and a pair of mono speaker terminals.
The CS4215 drives the line outputs into an R-C
filter and then to a pair of BNC's. As with the
line inputs, BNC-to-phono adapters are provided
for flexibility. The line outputs can drive an impedance of 10 ill or more, which is the typical
input impedance of most audio gear.
The stereo headphone output can drive headphones with an impedance of 48 n or greater.
This includes most "walkman" style headphones.
DS761?B3
----------- -----------
CDB4215
Ferrite Bead
+5VD
R28
2!l
~Ll
VD
+ 1 uF
D2
P6KE
VA
+ 1 uF
0.1 uF
0.1 uF
+5VA
0.1 uF
47 uF +
C31
C33
Dl
DGND
3
23
8
Microphone
Input Buffer
See Figure 3
Line Input
Buffer
See Figure 2
{
15
MINR
VA2
MOUTl
R52
50 k
19 CMOUT
17
{
24
VAl
VDl VD2
16 UNR
18
MOUTl
MINL
UNL
CS4215
MOUT2
+
22 uF
U1
MOUT2
2916 1/2W
HEADR
R21
XTL21N
HEADL
31
fl.2.o
30
16 1I2W
1\
Headphones
~VV~'
HEADC
16.9344 MHz
C29
1 uF
XTL20UT
LOUTR
XTL1IN
0.0022 uF
NPO
R25
XTL10UT
32 600
24.576 MHz
~
C2:
LOUTR
~
7
.n ~~~;
C28
+ 1 U~F
LOUTL
LOUTL
39 k
R27
See Fig 5
4 CLKIN
VREF
21
+
1'10 uF
C20
AGNDl AGND2
DGND2
22
Figure 1. CS4215 & Power Supplies
DS76DB3
4-69
_.-_..--_
-_.._-_...-..
CDB4215
VA
10 k
R19
LlNR 047 uF
20 k
.
t-J17
CS4215
16
R12
LlNR
5k
U3
LT1013
CMOUT
+ 1 uF
R17
~35
LlNL
(Mono) 0.47 uF
t-J37
18
20 k
LlNL
C9
R13
10 k
R18
Figure 2. Line Input Buffer
10uF
AS
R4
1.5k
22.1 k
C4
560 pF
NPO
+
~C6
VA+
C8
8
~0.1 uF
C48
R56
CS4215
MINR
150
MINR
U2
MC33178
C47
NPO
~ 0.Q1
0.47 uF
uF
.------------.------------------~19~CMOUT
+
C7 ~ 1uF
MINL
(Mono)
7
MINL
150
. -_ _
C--I1 560 pF
C45
R57
C46
NPO
0.47 uF
~0.01 uF
NPO
1.5k
R3
+
10uF ~ C3
22.1k
R1
Figure 3. Microphone Input Buffe~
4-70
DS76DB3
--- ------------------Speaker terminals are provided and are labeled
MOUTl and MOUT2. Speakers connected to the
terminals must have an impedance of 32 n or
greater. DC blocking capacitors are included to
form a high-pass filter with the speaker impedance. This filter blocks very low frequency
signals which can heavily distort some inexpensive speakers.
CDB4215
mode. In control mode the codec is always a
slave and FSYNC and SCLK must be driven
from the DSP. Since the evaluation board buffers
all the signals between the codec and the DSP,
the board must "know" which of the two modes
is being used. Jumper P3 selects the particular
mode.
Codec Master Data Mode
SERIAL INTERFACE
The CDB4215 is primarily designed to evaluate
the CS4215 is single chip mode, i.e. only one
codec on the serial bus. This is the default state
for the CDB4215 and is defined by having the
P4 jumper in the "lCHIP" position, see Figure 4,
which connects FSYNC to TSIN. This connection defines the board codec's time slots as the
first 64 bits of the frame. The only signals that
need to be connected to the DSP are the five signals on header 115. The serial interface is
illustrated in Figure 4.
If the goal is to connect multiple CDB4215s on
the same serial port, jumper P4 must be in the
"MULTI" position which disconnects TSIN from
FSYNC. The MULTI position also connects an
unbuffered SDOUT to header 114. This header
pin, SDOUTUB, must be used in lieu of
SDOUT since SDOUT is buffered and does not
go high impedance during other codec's time
slots. Using the multi-chip scenario, the TSIN
header pin must be connected to the previous
codec's TSOUT line and the first codec's TSIN
must be connected, via the header, to FSYNC.
Note that when P4 is in the lCHIP mode, the
SDOUTUB pin on header 114 is not connected
to the SDOUT pin on the CS4215 and is floating.
There are two scenario's that must be addressed
when connecting the CDB4215 to a DSP: one is
when the codec is the master in data mode and
the other is when the codec is a slave in data
DS76DB3
When the codec is to be programmed as a master in data mode, the direction of FSYNC and
SCLK have to be changed between control mode
and data mode. In this case the P3 jumper must
be set for "MIS" which uses the Die signal to
control the direction of the buffers (U7) for
SCLK and FSYNC. When P3 is set to MIS, the
buffers drive the Jl5 header in data mode and
receives FSYNC and SCLK from the header in
control mode.
Codec Slave Data Mode
When the codec is to be programmed as a slave
in data mode, FSYNC and SCLK are always inputs to the codec. In this mode P3 must be set to
"SLAVE" which configures the FSYNC and
SCLK buffers to always receive FSYNC and
SCLK from the Jl5 header.
As stated in the CS4215 data sheet, when the
codec is programmed in slave mode, XCLK = 0
in control mode, SCLK and FSYNC are inputs
and must be derived from the same clock used
as the master clock for the codec. Although
SCLK and FSYNC must be frequency locked to
the master clock, there is no phase requirement.
CONTROL PINS
All control pins, located on header Jl4, are defined as pins that are not essential to the DSP
serial port when used in lCHIP mode.
4-71
-
---
--------.....
-.------~
CDB4215
VD
T
P3
I
~ _9~M/S
. 1
C41 TO
----L .1 uF
I
~
141
1
±:6~'SLAVE
U7
=
43
=
R411 k
11 OEB OEA 3
74HCT243
SCLK f-'4"-2{)-j-~-~_MlA.L------'-1-'-10 BO
AO r=----
Lrr
~VV.
FSYNC
Y!2-
DIG
SDOUT
SDIN
TSIN
TSOUT
+-
9 Bl
'SB2
R441k
B3
18
44
3
1
16
40
/1
~
15
A3
:-~f~-~~-~~-:
7-J-
8
6
r
""
K
r-v
12
PDN f-'1=-30-_=+--<
,
~
, SDIN
L-~~~~---~IJVv~~
~~--+-~------~~~
5
14
13
I
P41 :,lCHIP
'MULTI
, TSIN
,--'---~----r-r-----VV~~
9 - - -8'
~
R47
;;,. 20 k
,-----,-h
8
USC
go
J14
-===R50
CLKOUT
50
R9
20 k
\\ 10
USB 4
R42
\.L 1------,,6'0' \\ 1-"'5---------+-f---i'I!\!\r--'
\.L
100
7
9
,.."f..
~i ~;.
RESET
100
C15 ~'::::- R8
1 uF
1='
PIOO
--L
1
Ploa
R55
800
~,r'r'
800 j;R54
~~
D3
237 k
-vvv
02
PI01~, r'r'
R30
36
237 k
I~T'\J\J'---I
. PIOl
: PIOl
: RESET
L----r-r--~----.~_ ~ SDOUTUB
O'~~~~h'4
12
,
TSOUT
,PDN
PIOO
~
U4
74HTCS41
RESET
, SCLK
_ ' FSYNC
11
V
=
2
JlJ
8
9
5
CLKOUT
TO.l uF
RPl
100 Ohm Dip
16 - - - 1 __ J!5
2
, DIe
.---------~~--~~+-~--~~~ SDOUT
"J
41
~C49
RP2
___ ?Qk_SJP____ 1
40 k -::;;J;0.1 uFL'::::====::J
R49 120
35
VD
Al
A2~
GND
r~40
Ul
CS4215
_
r-=37 _ - , - - _ - - - - - - - - - - - - - _ * _ - - - - - - - - ' 1
c...
-F-
D4
03
R53
02,03 = MPSA14
Figure 4. Digital Interface
4-72
DS76DB3
.._-_
.-_
._.-.
_
..--__
...
CDB4215
PDN and RESET
CLOCKS
Power down, PDN, controls the PDN pin on the
codec. The line has an on-board pull-down resistor thereby defining the default state as powered.
This pin only needs to be controlled if the power
down feature is used.
The CDB4215 can accommodate all clocking
modes supported by the CS4215. A CLKIN
BNC, as shown in Figure 5 allows the CLKIN
pin on the CS4215 to be used as the master
clock source. The two crystals listed in the
CS4215 data sheet are also provided and support
all the audio and multimedia standard sample
frequencies. The master clock is selected via a
CS4215 internal register from control mode.
RESET controls the RESET pin on the codec
and is pulled up on the board. This defines the
default state as not reset. This pin only needs to
be controlled if the reset feature on the codec is
needed. Since the codec does require a reset at
power up, a power-up reset circuit is included on
the board. A reset switch is also included to reset
the device without having to remove the power
supply. The power-up reset plus switch are logically OR'ed with the RESET pin on header 114.
The CLKOUT BNC is a buffered version of the
CLKOUT pin on the CS4215. CLKOUT is always 256 times the programmed sample
frequency in data mode. CLKOUT is held low in
control mode.
PIO Lines
LAYOUT ISSUES
The parallel input/output, PIO, lines are pulled
up on the evaluation board. If they are to be
used as inputs, they should be driven by opencollector gates since inadvertently setting the
PIO bits low in software will force the external
lines low. The PIO lines are available on header
114.
Figure 6 contains the silk screen, Figure 7 contains the top-side copper layer, and Figure 8
contains the bottom-side copper layer of the
CDB4215 evaluation board. These plots are included to provide an example of how to layout a
PCB for the codec. Two of the more important
aspects are the position of the ground plane split,
which is next to the part - NOT UNDER IT, and
the ground plane fill between traces on both layers, which minimizes coupling of radiated
energy.
The PIO lines also go through a high-impedance
buffer and drive LED's on the evaluation board.
When the LED is on, the corresponding bit is 1
or high. The LED's provide a visual indication
that may be used to verify that the software is
writing the bits correctly.
VD
CS4215
R16
10 k
elKIN
4
Figure 5. eLKIN
DS76DB3
4-73
(')
~
,..
It)
N
Qnn
~il
..B~
~ ~ rn:;:~ 0
G
+5VD
oo:r
In
C
o
DGND
OfCD
JJ
R55 R54
U4
IMI
QC40
'Ie
I
~
so'"
C29
1SIIIO
ISOUl
PI00
PII1I
RESET
PID
O~O
PI
R44
lCHlP
Il\A.II
____
RI6
d
R5JrfWR9
C4l
U5
R42
~
R24
A
I~'
'\::::) CJI
b.A.lL-JR28
AGiiD
"l'CIJ ~
20VCJ
\I V
1
:OR29
JI2
Y 'CJ Y \i
[;Dc,
PO'
1
R:
RI4TlRIJ
R50
R57
~~
~D:"
RJ RB
CRYSTAL .
Semiconduclor corpor. OIIOn)
SMART Ana~g
~
JJ
+5VA
~~.s
~e
!
~
JI
-o~~1 i
90
....
Jl:;:
~
a:mo
e
\CS
UNL
....~
RI2cIJc:::IJ
WINR
Ilw7lj
R51
J5
CDB4215
Evaluation Board
CI6
01'D
UI
FSYN(:
SOlIIJl
~~
~
11
TUS
I
R20R21
'""='"=""
R25 RlJ
i
tJ,oo"
U~WOUT2
n
TS.
r
D
§.
RJO
PON
R26
!'" C28
:-0
n
GND
R47
JI4
rr5i
JIO
~
G
HEADPHONES
Q"Q).
.J15
'. i
LOUTL
J6
::! •
I ,.
SDOUl
50111
SCLK
FSTNC
....'=.,"
LOUTR
Jl
OGNJl.
.....
11=
.....
Ic:Jl
WINL
(MONO)
XI
X2
UNR
JI
GJ
~
----------- -----------
CDB4215
-.
...... ..
•••••••••
•••••••••••
•••••••••••
•••••••••••
••••••••
••••••••'
•••••••
•••••••
•••••••
•••••••
••••••••
•• ••••••
•••••••
••••••••
•••• •
..••••••
••
••
•••
••
••
Figure 7. CDB4215 Compont Side Layout (Not to Scale)
DS76DB3
4-75
--------
;.==~:=:"
--.
CDB4215
• ••••••••
••••••••• ••
••
••••••••
••
•••• ••••• ••
••••••••
••
•••••••••
••
••••••
••••••••
•••• ••
•••• •••.•
•
i •
... .....
••••••••
••••••••
:
••••••••
•••
••
Figure 8. CDB4215 Solder Side Layout (Not to Scale)
4-76
DS76DB3
...
__ ....
.........
. . . . . • •1I8f1l8f ~.
~
CS4216
~
Semiconductor Corporation
16-8it Stereo Audio Codec
Features
General Description
• CMOS Stereo Audio Input/Output System
Delta-Sigma AID Converters
Delta-Sigma D/A Converters
Input Anti-Aliasing and Output
Smoothing Filters
Programmable Input Gain and
Output Attenuation
• Sample Frequencies of 4 kHz to 50 kHz
• CD Quality Noise and Distortion
< 0.01 %THD
IIgwave
The CS4216 is an Mwave™
audio codec.
The CS4216 Stereo Audio Codec is a monolithic
CMOS device for computer multimedia, automotive,
and portable audio applications. It performs AID and
D/A conversion, filtering, and level setting, creating 4
audio inputs and 2 audio outputs for a digital computer
system. The digital interfaces of left and right channels
are multiplexed into a single serial data bus with word
rates up to 50 kHz per channel. Up to 4 CS4216 devices can be attached to a single hardware bus.
Both the ADCs and the DACs use delta-sigma modulation with 64X oversampling. The ADCs include a digital
decimation filter which eliminates the need for external
anti-aliasing filters. The DACs include output smoothing
filters on-chip.
• Internal 64X Oversampling
• Low Power Dissipation: 80 mA
1 mA Power-Down Mode
Ordering Information:
CS4216-KL
0° to 70°C
0° to 70°C
CS4216-KQ
CDB4216
Evaluation Board
44-pin PLCC
44-pin TQFP
RESET
....I
0:0
PDN
wo:
LOUT
~I-
OZ
0..0
()
ROUT
SMODE3
DOl
MF5:D02I1NT
MF2:D03/F2ICDIN
MFl :D04/Fl/CDOUT
Dll
MF6:DI2IFl
MF3:DI3/F3/CClK
MF4:DI4IMAlCCS
SMODE2
SMODEl
SDIN
SDOUT
SClK
REFGND
REFBYP
REFBUF
SSYNC
LlNl
LlN2
MF7:SFS1/F2
MFB:SFS2/F3
RINl
RIN2
ClKIN
VD
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
VA
DGND
AGND
Copyright © Crystal Semicondutor Corporation 1993
(All Rights Reserved)
Oct '93
DS83F2
4-77
.
'
}J
__
"""'_
.."""''''''''_
--II-.
-......
.. -...
'CS4216
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND = OV, all voltages with re-
spect to OV.)
Parameter
Digital
Analog
Power Supplies:
Operating Ambient Temperature
Symbol
Min
Typ
Max
Unit$
VD
VA
4.75
4.75
5.0
5.0
5.25
5.25
V
V
TA
0
25
"70
°C
ANALOG CHARACTERlsTICs( TA = 25°C;
VA, VD = +5V; Input levels: logic 0 = OV,
logic 1 = VD; 1 kHz Input Sine Wave; ClKIN = 24.576 MHz; SM1; Conversion Rate = 48 kHz; SClK
12.288 MHz; Measurement Bandwidth is 10Hz to 20 kHz; Unless otherwise specified.)
Parameter *
Symbol
Min
Typ
=
Max
Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
-
-
Instantaneous Dynamic Range
IDR
80
85
-
dB
Total Harmonic Distortion
THD
-
-
0.01
%
-
80
-
dB
-
±D.5
dB
-0.5
-
+0.2
dB
21
22.5
24
dB
-
1.5
-
dB
-
0.75
dB
100
-
ppm/°C
±10
±150
±100
±400
lSB
lSB
2.5
2.8
3.1
Vpp
20
-
-
kQ
15
pF
ADC Resolution
16
ADC Differential Nonlinearity
(Note 1)
Interchannel Isolation
Interchannel Gain Mismatch
Frequency Response
(Note 1)
Programmable Input Gain Span
Gain Step Size
Absolute Gain Step Error
Gain Drift
Offset Error
DC Coupled Inputs
AC Coupled Inputs
Full Scale Input Voltage
Input Resistance
(Notes 1,2)
Input Capacitance
Notes:
(Note 1)
-
-
Bits
±D.9
lSB
1. This specification is guaranteed by characterization, not production testing.
2. Input resistance is for the input selected. Non-selected inputs have a very high (>1 MQ) input resistance.
* Parameter definitions are given at the end of this data sheet.
Mwave™ is a trademark of the ·IBM Corporation.
Specifications are subject to change without nOtice.
'4.78
DS83F2
----------------------
CS4216
ANALOG CHARACTERISTICS
(Continued)
Symbol
Parameter •
Min
Typ
Max
Units
-
Bits
±O.9
LSB
dB
dB
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
-
-
TDR
-
93
IDR
80
83
-
THD
-
0.02
%
80
-
dB
±O.5
dB
+0.2
dB
16
DAC Resolution
(Note 1)
DAC Differential Nonlinearity
Total Dynamic Range
Instantaneous Dynamic Range
Total Harmonic Distortion
(Note 4)
Interchannel Isolation
(Note 4)
-
(Note 1)
-0.5
-
Interchannel Gain Mismatch
Frequency Response
Programmable Output Attenuation Span
(Note 3)
-45
-46.5
-
dB
Attenuation Step Size
(Note 3)
-
1.5
-
dB
Absolute Attenuation Step Error
(Note 3)
-
-
0.75
dB
Gain Drift
REFBUF Output Voltage
(Note 5)
Maximum output current= 400 !1A
Offset Voltage
-
100
-
ppm/°C
1.9
2.2
2.5
V
-
10
-
mV
Full Scale Output Voltage
(Note 4)
2.5
2.8
3.1
Vpp
Deviation from Linear Phase
(Note 1)
-
-
1
Degree
-60
-
dB
80
-
100
1
rnA
rnA
40
-
dB
Out of Band Energy
(22 kHz to 100 kHz)
Power Supply
Power Supply Current
Power Supply Rejection
Notes:
(Note 6)
Operating
Power Down
(1 kHz)
-
3. Tested in SM3, Slave sub-mode, 128 BPF.
4. 10 kil, 100 pF load.
5. REFBUF load current must be DC. To drive dynamic loads, REFBUF must be buffered.
AC variations in REFBUF current may degrade ADC and DAC performance.
6. Typically current: VA = 30mA, VD = 50mA. Power supply current does not include output loading .
• Parameter definitions are given at the end of this data sheet.
DS83F2
4-79
----------------------
CS4216
SWITCHING CHARACTERISTICS (TA = 25°C; VA, VO = +5V, outputs loaded with 30 pF;
Input
levels: logic 0 = OV, logic 1 = VO)
Parameter
SM1:
SM2, SM3, SM4:
Input clock (ClKIN) frequency
Symbol
Min
Typ
Max
Units
ClKIN
ClKIN
2.048
1.024
24.576
12.288
25.6
12.8
MHz
MHz
tckl
15
tckh
15
-
ns
Fs
4
50
kHz
-
ns
-
ns
50
ns
-
s
ns
28
ns
12
ns
Sample Rate
(Note 1)
01 pins setup time to SClK edge
(Note 1)
ts2
10
01 pins hold time from SClK edge
(Note 1)
th2
8
tpd2
30
-
-
-
1/(Fs*bpf)
ClKIN low time
ClKIN high time
DO pins delay from SClK edge
SClK and SSYNC output delay
from ClKIN rising
Master Mode (Note 1)
tpd3
SClK period
Master Mode (Note 7)
Slave Mode
tsckw
SClK high time
Slave Mode
tsckh
30
SClK low time
Slave Mode
tsckl
30
75
SOIN, SSYNC setup time to SClK edge
Slave Mode
ts1
15
SOIN, SSYNC hold time from SClK edge
Slave Mode
th1
10
tpd1
-
SOOUT delay from SClK edge
Output to Hi-Z state
bit 64 (Note 1)
thz
Output to non-Hi-Z
bit 1 (Note 1)
tnz
RESET pulse width low
15
500
CCS low to CClK rising
SM4 (Note 1)
tcslcc
25
COIN setup to CClK falling
SM4 (Note 1)
tdiscc
15
CClK low to COIN invalid (hold time)
SM4 (Note 1)
tccdih
10
CClK high time
SM4 (Note 1) . tcclhh
25
CClK low time
SM4 (Note 1)
tcclhl
25
CClK Period
SM4 (Note 1)
tcclkw
75
CClK rising to COOUT data valid
SM4 (Note 1)
tccdov
CClK rising to COOUT Hi-Z
SM4 (Note 1)
tccdot
-
CClK falling to CCS high
SM4 (Note 1)
tcccsh
0
Notes:
4-80
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
30
ns
30
ns
-
ns
7. When the CS4216 is in master mode (SSYNC and SClK outputs), the SClK duty cycle is 50%.
The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
DS83F2
--------.._----.--------
CS4216
'Word Sync
Frame Sync
SSYNC
[SM1, SM2\
SCLK
[SM1,SM2\
SCLK
[SM3,SM4\
SSYNC
[SM3,SM4\
SDIN
Bil33
(BiI1)
[SM1,SM2,SM3\
(SM4)
[SM1,SM2,SM3\
SDOUT
MF4:CCS
Bil63
(BiI31)
Bil33
(BiI1)
(SM4)
Bil63
(BiI31)
'Oplional
J
Serial Audio Port Timing
MF1:CDOUT--r---------------------------------------------------
MF3:CCLK
MF2:CDIN
2
5
4
3
7
6
8
9
11
10
J
MF4:CCS
7
MF1:CDOUT
MF3:CCLK
MF2:CDIN
22
23
24
25
26
27
28
29
30
31
32
Serial Mode 4. Control Data Serial Port Timing
DS83F2
4-81
----------------------
CS4216
1ii1
~
~
~
~
~
~
~---+--~
Dlx
~
~---+--~
------------~~------~
~
DOx
~
------------~~------~
SClK*
* SClK is inverted for SM1 and SM2
ClKIN
SClK
SCLK & SSYNC Output Timing
(Master Mode)
DIGITAL CHARACTERISTICS (TA = 25°C; VA,
VD = 5V)
Parameter
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage at 10 = -2.0 rnA
Low-level Output Voltage at 10= +2.0 rnA
Output Leakage Current
Output Capacitance
Input Capacitance
4-82
I~r--------
SSYNC
(Master Mode)
DIlDO Timing
Input Leakage Current
--------,~
Symbol
Min
Typ
Max
Units
VIH
VD-1.0
-
-
V
1.0
V
-
V
0.1
V
10
JlA
10
JlA
15
pF
15
pF
VIL
-
VOH
VD-0.3
VOL
-
(Digital Inputs)
(High-Z Digital Outputs)
COUT
CIN
DS83F2
.._-_
_.-_..--_._.
__
...-.
CS4216
AID Decimation Filter Characteristics
Parameter
Symbol
(Fs is conversion freq.)
Passband
Min
Typ
Max
0
0.45Fs
Hz
+0.2
dB
-
-
±O.2
dB
0.45Fs
-
0.55Fs
?: 0.55Fs
-
-
Hz
Hz
dB
0.0
I1s
Units
-0.5
Frequency Response
Passband Ripple
Transition Band
Stop Band
Stop Band Rejection
80
Group Delay
Group Delay Variation vs. Frequency
-
16/Fs
Min
Typ
Max
Units
s
D/A Interpolation Filter Characteristics
Symbol
Parameter
Passband
(Fs is conversion freq.)
Frequency Response
0
-
0.45Fs
Hz
-0.5
-
+0.2
dB
-
±O.1
dB
0.55Fs
Hz
Hz
74
-
Group Delay
-
16/Fs
-
Group Delay Variation vs. Frequency
-
-
0.1/Fs
Passband Ripple
Transition Band
0.45Fs
?: 0.55Fs
Stop Band
Stop Band Rejection
ABSOLUTE MAXIMUM RATINGS (AGND,
dB
115
s
DGND = OV, all voltages with respect to OV.)
Symbol
Min
Typ
Max
Units
VD
VA
-0.3
-0.3
6.0
6.0
V
V
-
-
±10.0
mA
Analog Input Voltage
-0.3
-
VA+0.3
V
Digital· Input Voltage
-0.3
-
VD+0.3
V
+125
°C
+150
°C
Parameter
Power Supplies:
Input Current
Ambient Temperature
Storage Temperature
Warning:
DS83F2
Digital
Analog
(Except Supply Pins)
(Power Applied)
-55
-65
Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
4-83
.._-_.
_.-_..-__....
..._.+5V
Supply
CS4216
Ferrite Bead
/ - - - - - - T - - -~'-_.______=__.__-_>-211J.0Vv___.__-_>--____,
___________
24
r-----=~--------~-
'>--________--=2"'-16
+5V
Analog
If a separate +5V
Analog supply is used, remove
the 2.0 ohm resistor
VA
VD
Line In 2
Right
<
'·°1 ·R''''
15
RIN2
I>40 k
ROUT
Audio
Output
~0.OO22ILF
'V
See Analog Inputs section
for suggested input ciruits.
NPO
16
Line In 2
left
>'1'
I
lOUT
40k
Audio
Loft
Output
~O.0022ILF
)>-________----'2::.::8'--1 LlN2
'V
NPO
21
REFBYP
10ILF
22
CS4216
Line In 1
REFGND
)>-________----'2::.::5'-.1 RIN1
Right
ClKIN
To Optional
Input Buffers
.4_ _ _ _ _ _~---=2::.::0'-1 REFBUF
3
PDN
I
Controller
~0.47ILF
Line In 1
)>-_________2_7_1 LlN1
SSYNC
left
MF1 :D041F1/CDOUT
Parallel Bits
or
Sub-Mode
Settings
or
Control Port
MF2:D03IF2ICDIN
MF3:DI3IF3ICClK
MF4:DI4IMA/CCS
MF5:D02lINT
SMODE1
MF7:SFS1
Mode
Setting
MF8:SFS2
MF6:DI2IF1
Note: AGND and DGND pins MUST be on the same ground plane
Refer to the Analog Inputs
section for terminating
unused line inputs.
All other unused inputs
should be tied to GND. All NC
pins should be left floating.
Figure 1. Typical Connection Diagram
4-84
DS83F2
----------------------
CS4216
OVERVIEW
56 pF
The CS4216 contains two analog-to-digital converters, two digital-to-analog converters,
adjustable input gain, and adjustable output level
control. Since the converters contain all the required filters in digital or sampled analog form,
the filters' frequency responses track the sample
rate of the CS4216. Only a single-pole RC filter
is required on the analog inputs and outputs. The
RC filter acts as a charge reserve for the
switched-capacitor input and buffers op-amps
from a switched-capacitor load. Communication
with the CS4216 is via a serial port, with separate pins for data into the device, and data from
the device. The filters and converters operate
over a sample rate range of 4 kHz to 50 kHz.
Une In
RINx
Right
(PLCC pin 25 or 26)
Example
Op·Amps
REFBUF
are
MC34072
or
LT1013
LlNx
Line In
(PLCC pin 27 or 28)
Left
Op-amps are run
from VA+5V and
AGND.
Figure 2. DC Coupled Input.
FUNCTIONAL SPECIFICATIONS
Analog Inputs and Outputs
0.47 uF
Line In
Figure 1 illustrates the suggested connection diagram to obtain full performance from the
CS4216. The line level inputs, LIN1 or LIN2
and RIN1 or R1N2, are selected by an internal
input multiplexer. This multiplexer is a source
selector and is not designed for switching between inputs at the sample rate.
Right
o----i ~ (PLCCR~~X25
ow
~01 uF
,------I~
ry
Line In
Left
~
or 26)
NPO
~.~:tNPO
0.01 uF
I
~
150
LlNx
(PLCC pin 27 or 28)
0.47uF
Unused analog inputs that are not selected have
a very high input impedance, so they may be
tied to AGND directly. Unused analog inputs
that are selected should be tied to AGND
through a 0.1 J.LF capacitor. This prevents any
DC current flow.
The analog inputs are single-ended and internally biased to the REFBUF voltage (nominally
2.2 V). The REFBUF output pin can be used to
level shift an input signal centered around
o Volts as shown in Figure 2. The input buffers
shown have a gain of 0.5, yielding a full scale
input sensitivity of 2 Vrms with the CS4216 proDS83F2
Figure 3. AC Coupled Input
grammable gain set to O. If the source impedance is very low, then the inputs can be AC
coupled with a series 0.47 J.LF capacitor, eliminating the need for external op-amps (see Figure
3). However, the use of AC coupling capacitors
will increase DC offset at OdB gain (see Analog
Characteristics Table).
The analog outputs are also single-ended and
centered around the REFBUF pin. AC coupling
capacitors of >1 J.LF are recommended.
4·85
_.-_..--_._.
__.._-_.
...Offset Calibration
Both input and output offset voltages are minimized by internal calibration. Offset calibratio~
occurs after exiting a reset or power down condItion. During calibration, which takes 194 frames,
output data from the ADCs will be all zeros, and
will be flagged as invalid. Also, the DAC outputs will be muted. After power down mode or
power up, RESET should be held low for a
minimum of 50 ms to allow the voltage reference to settle.
Input Gain and Output Level Setting
Input gain is adjustable from 0 dB to +22.5 dB
in 1.5 dB steps. In serial modes SMI and SM2,
the output level attenuation is adjustable from
o dB to -22.5 dB. In serial modes SM3 and
SM4, the output level attenuation is adjustable
from 0 dB to -46.5 dB. Both input and output
gain adjustments are internally made o.n .ze~o
crossings of the analog signal, to mInImIZe
"zipper" noise. The gain change automatically
takes effect if a zero crossing does not occur
within 512 frames.
Muting and the ADC Valid Counter
The mute function allows the output channels to
be silenced. It is the controlling processor's responsibility to reduce the signal level to a low
value before muting, to avoid an audible click.
The outputs should be muted before changing
the sample frequency.
The serial data stream contains a "Valid Data"
indicator for the AID converters which is false
until enough clocks have passed since reset, or
low-power (power down mode) operation to
have valid AID data from the filters, i.e., until
calibration time plus the full latency of the digital filters has passed.
4·86
CS4216
SSYNC
II
SCLK
(5M3)
Start of,
Frame
i
01 pins
DO pins
latched
update
Figure 4. Digital Input/Output Timing
Parallel DigitalJnputlOutput Pins
Parallel digital inputs are general purpose pins
whose value is reflected in. the serial datll:0utput
stream to the processor. Parallel digital outputs
provide a way to control external devices using
bits in the serial data input stream. All parallel
digit~ pins, with the exception of DIl and D~I,
are multifunction and are defined by the senal
mode selected. Serial modes 1 and 2 define all
multifunction pins as general purpose digital inputs and outputs .. In Serial mode 3 only t~o
digital inputs and two digital outputs are aVaIlable. In serial mode 4 only one digital input and
digital output exists. Figure 4 shows w~en the
DI pins are latched, and when the DO pms are
updated in SM3 and SM4.
Reset and Power Down Modes
Reset places the CS4216 into a known state and
must be held low for at least 50 ms after powerup or a hard power down. Reset must also occur
when the codec is in master mode and a change
in sample frequency is desired. In res 7t, the digital outputs are driven low. Reset sets all control
data register bits to zero.
Hard power down mode may be initiated by
bringing the PDN pin low. All analog outp~ts
will be driven to the REFBUF voltage whIch
will then decay to zero. All digital outputs will
be driven low and then will go to a high impedance state. Minimum power consumption will
occur if CLKIN is held low. After leaving the
power down state, RESET should be held low
for 50 ms to allow the analog voltage reference
to settle before calibration is started.
DS83F2
_.-_..--__.._-_
...
._.-.
CS4216
Alternatively, soft power down may be initiated,
in slave mode, by reducing the SCLK frequency
below the minimum CLKINI12. In soft power
down the analog outputs are muted and the serial
data from the codec will indicate invalid data
and the appropriate error code. The parallel bit
110 is still functional in soft power down mode.
This is, in effect, a low power mode with only
the parallel bit 110 unit functioning.
audio data which reduces the number of bits on
the audio port from 64 to 32 per codec.
The serial port protocol is based on frames consisting of 1, 2, or 4 sub-frames. The frame rate is
the system sample rate. Each sub-frame is used
by one CS4216 device. Up to 4 CS4216s may be
attached to the same serial control lines. SFS 1
and SFS2 are tied low or high to indicate to each
CS4216 which sub-frame is allocated for it to
use.
Audio Serial Interface
Serial Data Format
In serial modes 1, 2, and 3, the audio serial port
uses 4 pins: SDOUT, SDIN, SCLK and SSYNC.
SDIN carries the D/A converters' input data and
control bits. Input data is ignored for frames not
allocated to the selected CS4216. SDOUT carries the AID converters' output data and status
bits. SDOUT goes to a high-impedance state
during frames not allocated to the selected
CS4216. SCLK clocks data in to and out of the
CS4216. The rising edge of SCLK clocks data
out on SDOUT. The falling edge latches data on
SDIN into the port (SCLK polarity is inverted in
Serial Modes 1&2). SSYNC indicates the start of
a frame and/or sub-frame. SCLK and SSYNC
must be synchronous to the master clock.
Serial mode 4 is similar to serial mode 3 with
the exception of the control information. In serial
mode 4 the control information is entered
through a separate asynchronous control port.
Therefore, the audio serial port only contains
SMODE PINS
3
2
1
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
Serial
Mode
SCLK Bit
Center
SM1
SM2
SM3
SM4
In serial modes 1, 2, and 3, a sub-frame is
64 bits in length and consists of two 16-bit audio
values and two 16-bit control fields. In serial
mode 4 a sub-frame is 32 bits in length and only
contains the two 16-bit audio values; the control
data is loaded through a separate port. The audio
data is MSB first, 2's complement format. The
sub-frame bit assignments for serial modes 1, 2,
and 3, are numbered 1 through 64 and are shown
in Figures 5 and 6. Control data bits all reset to
zero.
CS4216 SERIAL INTERFACE MODES
The CS4216 has 4 serial port modes, selected by
the SMODEl, SMODE2 and SMODE3 pins. In
all modes, CLKIN, SCLK and SSYNC must be
derived from the same clock source. SM1 is an
easy interface to ASICs that use a change in the
SCLK-to-CLKIN ratio to determine the sample
Sub-frame
Width
Bits per
Frame (BPF)
SCLK&
SSYNC
Rising
64 bits
256
Slave
ClKIN
Rising
64 bits
256
Slave
SClK
Falling
64 bits
Factory Test mode
32 bitst
Falling
Master
Frequency
64/128/256 MasterlSlave
= 512xFs
= 256xFs
ClKINlSClK = 256xFs
32164/128t
ClKIN
MasterlSlave
= 256xFs
tContains audio data only. Control information is entered through a separate serial port.
Table 1. Serial Port Modes
DS83F2
4-87
.._-_
._.-.
_.-_..--__
...
CS4216
Sub-frame Bits 33 to 48
Right DAC audio data MSB ftrst, 2's complement coded.
INPUT DATA BIT DEFINITIONS
Sub-frame bits 1 to 16
Left DAC Audio Data, MSB ftrst, 2's complement coded.
Sub-frame Bits 49 to 50
Must be zero.
Sub-frame Bits 17 to 24
1
17
18
19
20
0
o
0
0
21
2223
Sub-frame Bits 51 to 60
24
~
I Expi MUTE IISL IISRI
EXP
Expand bit
Reserved. Must be set to zero.
MUTE Mute O/A Outputs
o - Normal Outputs
1 - Mute Outputs
ISL
t 1 0
Select Left Input Mux
1 - Select L1N2
Select Right Input Mux
1 - Select RIN2
Sub-frame Bits 25 to 32
25
26
27
LG2
LGi
28
29
LGO 1RG3
~
~
$
~
~
~
~
0 1 LA3 LA2 LA1 LAO 1RA3 RA2 RA1 RAol
RA4-RAO Sets right output attenuation
·SM3,4
tSM1,2
RA4 is the MSB.
RA3 is the MSB.
00000 = no attenuation
0000 = no attenuation
1111 = -22.5 dB
11111 = -46.5 dB
RAO represents 1.5 dB.
o - Select RIN1
1 LG3
~
LA4-LAO Sets left output attenuation
·SM3,4
tSM1,2
LA3 is the MSB.
LA4 is the MSB.
00000 = no attenuation
0000 = no attenuation
.11111 = -46.5 dB
1111 = -22.5 dB
LAO represents 1.5 dB.
o - Select L1N1
ISR
~
·1 LA4 LA3 LA2 LA1 LAO 1RA4 RA3 RA2 RA1 RAol
30
31
32
RG2
RG1
RGOI
Sub-frame Bits 61 to 64
LG3-LGO Sets left input gain.
LG3 is the MSB. LGO represents 1.5 dB.
0000 = no gain.
1111 = +22.5 dB gain
61
1001
62
63
64
002
003
0041
001-004
RG3-RGO Sets right input gain.
RG3 is the MSB.RGO represents 1.5 dB.
0000 = no gain
Set the logic level on the 4 digital output
pins. In SM3 003 and 004 are not
available. In SM4 002, 003, & 004
are not available.
Sub-frame
It,
~'.----------------
WoroA--------------~.,.~-------------- WoroB--------------~.,
101 I I I I I I I I J I I I I t~I~1 I I INI~I&lI~lgjl I 1&llgJl I I~iij I I I I I I I I I I I I I I~I I ilOl~f21 I@®@ I IgiIDI I 1C'b!
~
DAe· Left Word
DAe • Right Word
~
SM1 and,SM2
DAe· Right Word
DAe· Left Word
SM3
Figure 5. Serial Data Input Format - SM!, SM2, and SM3.
4-88
DS83F2
.-_
_
..--_._.
__.._-_
...-.
CS4216
Sub-frame Bits 25 to 32
OUTPUT DATA BIT DEFINITIONS
Sub-frame Bits 1 to 16
25
I ER3
Left ADC Audio Data, MSB first, 2's comple-
Sub-frame Bits 17 to 24
18
19
20
RESERVED
ADV
22
21
I a
23
27
ER1
28
24
I ADV I LCL I RCLI
ADC Valid data bit.
a - Invalid ADC data
1 - Valid ADC data
Indicates ADC has completed initialization
after power-up, low power mode,
or mute.
30
31
32
Ver2
Ver1
vera I
Subjrame Bits 33 to 48
Right ADC Audio Data, MSB first, 2's complement coded.
LCL
Left ADC clipping indicator
0- Normal
1- Clipping
RCL
Right ADC clipping indicator
0- Normal
1- Clipping
RESERVED bits can be a or 1
Sub-frame Bits 49 to 60
These bits are reserved, and can be 0 or 1.
Sub-frame Bits 61 to 64
61
62
63
64
I DI1
DI2
DI3
DI41
D11-D14
These bits follow the state of the Digital
Input pins. In SM3 DI3 and DI4 are used
and unavailable. In SM4 D12, D13, & DI4
are not available as input bits.
Sub-frame
~,'--------
29
ERa I Ver3
ER3-ERO Error Word
0000 - Normal - No errors.
0001 - Input Sub-frame Bit 21 is set.
Control data will not be loaded
0010 - Sync Pulse is incorrect.
Causes the analog output to mute.
0011 - SCLK is outside the allowable
range. Analog output mutes.
Ver3-VerO
CS4216 Version Number
0000 = "A" (see Appendix A)
0001 = "B", "C", ... (This data sheet)
ment coded.
17
26
ER2
"
Word A - - - - - - - _ 1 1 1 - - - - - - - - - - Word B - - - - - - - - + . '
la 1 1 1 1 1 1 1 1 1 1 1 1 1 liil~ 11 1;;J~i(jiilil 1 liijgj 1 1~18 1 1 1 1 1 1 1 1 1 1 1 1 1 lij 1 1 lill@ lillll@ 1 1$1;;;1 1 I~
,
'
ADC - Left Word
ADC - Right Word
8Ml
'"'"
and 8M2
ADC - Left Word
ADC - Right Word
8M3
Figure 6. 8erial Data Output Format - 8Mt, 8M2, and 8M3.
DS83F2
4-89
-
,~
'"
--------------_._----frequency... SM2 is similar to SMI except that
CLKIN is not used and SCLK becomes the master cloc,k and is fixed at 256xFs. SM3 was
designed !lS an easy interface to general purpose
DSPs and provides extra features such as one
more bit of attenuation, a master mode, and variable frame sizes. SM4 is similar to SM3 but
splits the audio data from the control data
thereby reducing the audio serial bus bandwidth
by half. The contr()l data is transmitted through a
control serial port in SM4.
Table 1 lists the serial port modes available,
along with some of the differences between
modes. The first three columns in Table 1 select
the serial mode. The "SCLK Bit Center" column
indicates whether SCLK is rising or falling in
the center of a bit period. The "Sub-frame
Width" column indicates how many bits are in
an individual codec's sub-frame. SM4 differs
from all other modes by separating the control
data from the audio data. In both SMI and SM2,
there are 256 bits per frame which allows up to
four codecs to occupy the same bus. In SM3 and
SM4, the number of bits per frame is programmable. In SMI and SM2, SCLK and SSYNC
must be generated externally; whereas, in SM3
and SM4 the CS4216 can optionally generate
those signals. In all modes, SCLK and SSYNC
must .be synchronous to the master clock. The
last column in Table 1 lists the master frequency
used by the codec. In SM1, the master frequency, input on CLKIN, is 512 times the
highest sample frequency available. In SM2, the
master frequency is fixed at 256 times the sample frequency and, in this mode, SCLK is the
master· clock. In SM3, the master frequency is
256 times the highest frequency available and is
input on CLKIN or SCLK, based on the submode used. In SM4, the master frequency is also
256 times the highest frequency available and is
input on CLKIN.
CS4216
SERIAL MODE 1, SMI
Serial Mode 1 is a slave mode selected by setting SMODE3 = SMODE2 = SMODEI = O.
SCLK and SYNC must be synchronous the mas"
ter clock. SMI uses a two bit wide (minimum)
frame sync with an optional word sync. In this
mode, SSYNC low for one SCLK period followed by SSYNC high for a minimum of two
SCLK periods indicates the beginning of a
frame. The first bit of the frame starts with the
rising edge of SSYNc. An optional word sync,
being one SCLK period high, may be used to
indicate the start of a new 32-bit word. Figures 5
and 6 contain the serial data format for SMI ~ In
this serial mode, the ratio of two clocks are used
to select sample frequency~ These are the master
clock CLKIN and the serial clock SCLK.
CLKIN should be set to 512xFsmax, where
Fsmax is the maximum required sample rate.
SCLK must be externally set to a value of
CLKININ, such that SCLK equals 256 times the
desired sample rate. The codec uses the ratio between CLKIN and SCLK to set the internal
sample frequency and causes the CS4216 to go
into soft power down mode if the SCLK frequency drops to •..-,.- FRAME (n+2)
128 SCLK Periods
Sub-frame 1
WardA
DATA
Word B
Sub·frame 1
Sub·frame2
WardA
WardB
Word A
Word B
Sub-frame 2
Word A
Sub-frame 1
Word B
WardA
WardB
-'nL_________----'nL_____
MF8:
SFS2
o
o
MF7: Sub·
SFS1 frame
0
1
2
SSYNC JlL-._ _ _ _ _ _ _ _
Figure 11. SM3-Slave - 128 BPF; MF1:Fl, MF2:F2 = 01
'<-'.---~------
FRAMEn - - - - - - - - - - - -....'.0--- FRAME(n+1)
256 SCLK Periods
Sub-frame 1
DATA
Word A
Word B
Sub-frame 2
WardA
WordB
Sub-frame 3
Word A
Word B
Sub·frame 4
WardA
Sub-frame 1
WordB
WardA
Word B
----.JnL _ _ _ __
SSYNcJlL-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Figure 12. SM3-Slave - 256 BPF; MF1:Fl, MF2:F2 =10
DS83F2
MF8:
SFS2
o
o
MF7: Sub·
SFS1 frame
o
1
o
1
2
3
4
-
----------------------
CS4216
channel. The Applications of SM4 section contains more information on low-cost
implementations of this sub-mode.
MF5:INT is 'reset by reading the control serial
port.
Master Sub-Mode (SM4)
SMODEI = 1 selects Master sub-mode with a
frame width of 64 bits. This sub-mode allows up
to two codecs to occupy the same bus. SMODE2
is now used to select the particular time slot. If
SMODE2 = 0 the codec selects time slot 1,
which is the first 32 bits. If SMODE2 = 1 the
codec selects time slot 2, which is the second
32 bits.
Master sub"mode configures SSYNC and SCLK
as outputs from the CS4216. During power
down, SSYNC and SCLK are driven high impedance, and during reset they both are driven
low. There are two SM4 Master sub-modes. One
allows 32 bits per frame and the other allows 64
bits per frame. As shown in Table 6, the
SMODE1and SMODE2 pins select the particular ·Master sub-mode (as well as the Slave
sub-mode). When SMODE1 is set to zero,
SMODE2 selects either Master sub-mode with
32-bit frames, or Slave sub-mode.
In Master sub-mode, multifunction pins MF6:F1,
MF7:F2, and MF8:F3 select the sample frequency as shown in Table 7. This table indicates
how to obtain standard audio sample frequencies
given one of two CLKIN frequencies:
12.288 MHz or 11.2896 MHz. Other CLKIN frequencies may be used with the corresponding
sample frequencies being CLKININ. The codec
must be reset when changing sample frequencies
to allow a new calibration to occur.
SMODE1,SMODE2 = 00 selects Master submode where a frame = sub-frame = 32 bits. This
sub-mode allows only one codec on the audio
serial bus, with the first 16 bits being the left
channel and the second 16 bits being the right
Slave Sub-Mode (SM4)
SMODE1
SMODE2
0
0
1
1
0
1
0
1
SM4, Sub-Mode
In SM4, Slave sub-mode is selected by setting
SMODE1,SMODE2 = 01. This mode configures
SSYNC and SCLK as inputs to the CS4216.
These two signals must be externally derived
from CLKIN. Since the CS4216 has no control
over the phase relationship of SSYNC and
Master, 32 BPF
Slave, 128/64/32 BPF
Master, 64 BPF, TS1
Master, 64 BPF, TS2
Table 6. SM4 Sub-Modes.
- - - - - - - - Sub·Frame
(master)
SSYNC
------~nr-------------------------~n~------------
(slave)
SCLK
SDOUT
ACC· Riglt W",d
ADC· Left Word
",,,,
'" '"
-'
SDIN
DAC· Right Word
DAC·LeftWO
HC597
n_
~y+__--------~l---1yr_---L//~~ 11
A
LOAD
CS4216
SM4
SCLK
32BPF
' - - - - - - - - . p LCLK
4O
MF1:CDOUT t--..::.____..._-----.I AIN
DIN
Af--- 0
B f--- ADV
C I - - - Dll
Df--- RCL
24+ bit DSP Data Bus
~--------------,
E I--- LCL
F I---ERRO
f
HC595
Gf---ERRl
Hf--- 0
OE
R-E-S-E-T ~=2______________~
MF6:F1
34
VtL----------'
MF7:F2 f+=3:...:.1_ _ _ _ _ _- j
~~----------~
MF8:F314-3-'-0-------1
HC574
Figure 17. SM4· Enhanced DSP Interface
4-100
DS83F2
.-_
._.-.
_
..--__.._-_
...
CS4216
nously (every audio frame) with respect to the
interrupt occurrence.
(analog ground) and the board digital ground
should be positioned as shown in Figure 18.
The third section is only needed if sample frequencies need to be changed. This section is
comprised of an HC574 octal latch that can be
replaced by general purpose port pins if available. This section controls the sample frequency
selection bits: MF6:Fl, MF7:F2, MF8:F3 and
the RESET pin. The codec must be reset when
changing sample frequencies.
Figure 19 illustrates the optimum ground and decoupling layout for the CS4216 assuming a
surface-mount socket and leaded decoupling capacitors. Surface-mount sockets are useful since
the pad locations are identical to the chip pads;
therefore, assuming space for the socket is left
on the board, the socket can be optional for production. Figure 19 depicts the top layer,
containing signal traces, and assumes the bottom
or inter-layer contains a fairly solid ground
plane. The important points are that there is solid
ground plane under the codec on the same layer
as the codec and it connects all ground pins with
thick traces providing the absolute lowest impedance between ground pins. The decoupling
capacitors are placed as close as possible to the
device which, in this case, is the socket boundary. The lowest value capacitor is placed closest
to the codec. Vias are placed near the AGND
and DGND pins, under the IC, and should attach
to the solid ground plane on another layer. The
negative side of the decoupling capacitors should
also attach to the same solid ground plane.
Traces and vias bringing power to the codec
should be large, which minimizes the impedance.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Power Supply and Grounding
The CS4216, along with associated analog circuitry, should be positioned in an isolated section
of the circuit board, and have its own, separate,
ground plane. On the CS4216, the analog and
digital grounds are internally connected; therefore, the AGND and DGND pins must be
externally connected with no impedance between
them. The best solution is to place the entire
chip on a solid ground plane as shown in Figure 18. Preferably, it should also have its own
power plane. The +5V supply must be connected
to the CS4216 via a ferrite bead, positioned
closer than 1" to the device. The VA supply can
be derived from VD, as shown in Figure 1. Alternatively, a separate +5V analog supply may be
used for VA, in which case, the 2.0 n resistor
between VA and VD should be removed. A single connection between the CS4216 ground
Although not shown in the figures, the trace layers (top layer in the figures) should have ground
plane fill in-between the traces to minimize coupling into the analog section. See the CDB4216
evaluation board as an example.
If using all surface-mount components, the de-
coupling capacitors should be placed on the
same layer as the codec and in the positions
shown in Figure 20. The vias shown are assumed to attach to the appropriate power and
ground layers. Traces and vias bringing power to
the codec should be as large as possible to minimize the impedance.
If using a through-hole socket, effort should be
made to find a socket with minimum height,
DS83F2
4-101
-
--------..-----_._-----
CS4216
which will minimize the socket impedance.
When using a through hole socket, the vias under the codec in Figure 19 are not needed since
the pins serve the same function.
ADC andDAC Filter Response Plots
Figures 21 - 26 shows the overall frequency response, passband ripple and transition band for
the CS4216 ADCs and DACs. Figure 27 shows
the DACs' deviation from linear phase.
Fs is defined as the selected sample frequency
and is also the SSYNC frequency. Since the
sample frequency is programmable, the filters
will adjust to the selected sample frequency.
~1/8"
Analog
Digital
Ground
Plane
Ground"
Plane
Ground
conneCtion
Note that the CS4216
is oriented with its
digital pins towards the
digital end of the board .
. I·C84216 1
+5V
Ferrite
Bead
I~
CPU & Digital
Logic
Codec
digital
signals
Codec
analog
signals &
Components
Figure 18. CS4216 Board Layout Guideline
4-102
DS83F2
----------------------
CS4216
1---------------'
:
00000000000
:
I
I
I
I
I
I
1
+
I_
Analog
Supply
,.+~ljICiIflI.!I
Digital
Supply"
IlL:J
1,,-:
o
I
I
00000000000
I
L ________________ I
Figure 19. CS4216 Decoupling Layout Guideline
,- - - - - - - - - - - - - - - - -I
:
00000000000
I
I
I
I
I
I
I
~• • • •I>AnaIOg
Supply
~
I
Digital
Supply
C• •I
I~
1°
IL
~:
00000000000
L _______________
:
~
Figure 20. CS4216 Surface Mount Decoupling Layout
DS83F2
4-103
----------------------
CS4216
O. & r - - - - - - - - - - - - - - - - ,
-10
iii" -20
o.
~
-0.
~
-0 •
:Eo
:Eo -30
'"
~
iii"
-40
Cl
as
::;;
§, -50
as
::;; -60
-0.
-70
-0.
-80
- ,-
','
-,-
-90
-100+---t--t--t--t---j--'-jl...i...j-+,....L..l't-'-lL..lj-.l....Jl.-j
M ~ ~ ~ M M M ~ M M In
-1.2t---t---t--t---t---t---j---t---j--f--1
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Input Frequency (Fs)
Figure 21. CS4216 ADC Frequency Response
Figure 22. CS4216ADC Passband Ripple
,
-10
-20
-10
:Eo -30
iii" -20
iii"
:E'c"
~
::;;
-50
.-
:Eo -30
-40
"C
"
'"
"C
OJ
-,
'"c
,.-
-40
-50
~
::;; -60
.'
-70
-8
.'
-80
-9
,.-
-90
-1 OOH-~r---+--+--t---+--+--t---+---f-L0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
-100
0.0
0.1
0.2
Input Frequency (Fs)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (Fs)
Figure 23. CS4216 ADC Transition Band
Figure 24. CS4216 DAC Frequency Response
-10
~
-20
iii"
-0.1
:Eo -30
~ -0.2
'"
!
§, -0.3
as
§, -50
as
::;; -0.4
-40
::;; -60
-0.5
-7
-0.6
-8
-0.7
-90
-0.8+---t---t--t-----r--r----t---t----cr----f---I
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 25. CS4216 DAC Passband Ripple
4-104
','
"
"
.'
!
-100'+---I,---t---r----I--t---j--r-------r--j----i
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 26. CS4216 DAC Transition Band
DS83F2
----------------------
CS4216
2.
2.
1.
m
CD
1.
o.
~
CD
'"
:s. o.
CD
-
m -0.
.c:
Il-
-1.
-1.
-2.
-2.5+---t--t----t---t---j--t---t---t----t----i
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 27. CS4216 DAC Deviation from Linear Phase
DS83F2
4-105
_-_
-.-..--__......._.-.
CS4216
PIN DESCRIPTIONS
SSYNC
RESET
SCLK
CL~~
~:~~UT
OG:~~
~::~~~UT
NC~
44
NC~\
NC~
~
42
40
0
3
NC_______:
NC- 6
PON~
34
11 12
1/001
44-PIN
:/-MF4:014IMAlCCS
______ MF3:013IF3ICCLK
-MFS:012IF1
'---011
(Q)
Top View
14
/;=MF5:002llNT
CS4216
7
~
-!I
36
TQFP
NCJ.:
ROUT
10
LOUT
38
16
18
:~~~
"'-SMOOE2
~MF7:SFS1/F2
20
22
'tMF8:SFS2IF3
~~~=~OE1
REFB~~~
~RIN2
REFBYP
REFGNO
RIN1
VA
AGNO
SM
1
2
3
4-SL
4-MA
4·106
MF1
004
MF2
003
004
F1
003
F2
COIN
COIN
COOUT
COOUT
MF3
013
013
F3
CCLK
CCLK
MF4
014
MF5
002
MFS
012
MF7
SFS1
014
MA
002
002
INT
INT
012
012
SFS1
MF8
SFS2
SFS2
SFS1
SFS1
F2
SFS2
SFS2
F3
CCS
CCS
F1
F1
OS83F2
.-_
_
..--_._.
-_.._-_
...-.
CS4216
SSVNC
~~~~~
~:~UT
DG=~~ ~:~~~~~UT
NC~
NC~\
NC~
6
4
2 ? 44
~
9
NC __________ :~
NC- 12
PDN -------NC.---/
ROUT
. LOUT:;
=1
/ /D01
:/-MF4:DI4/MAlCCS
..----MF3:DI3IF3ICCLK
-MF6:DI2IF1
(L)
:!
15
/;=MF5:D02lINT
42
CS4216
44-PIN
PLCC
"---
Top View
31
16
17 18
28
~~~~~
~~~=~DE1
REFB~~--:/://
~RIN2
REFBVP
REFGND
SM
1
MF1
004
MF2
003
DI1
:::-SMODE2
\'\-MF7:SFS1IF2
'tMF8:SFS2IF3
RIN1
VA
AGND
2
004
003
MF3
013
013
MF4
014
014
MF5
002
MF6
012
MF7
SFS1
MF8
SFS2
002
012
SFS1
SFS2
3
F1
F2
F3
MA
002
012
SFS1
SFS2
4-SL
COOUT
COIN
CCLK
CCS
INT
F1
SFS1
SFS2
4-MA
COOUT
COIN
CCLK
CCS
INT
F1
F2
F3
Power Supply
VD • Digital +5V Supply, PIN 4(L), 42(Q).
+5V digital supply.
VA· Analog +5V Supply, PIN 24(L), 18(Q).
+5V analog supply.
DGND • Digital Ground, PIN 5(L), 43(Q).
Digital ground. Must be connected to AGND with zero impedance.
DS83F2
4-107
----------------------
CS4216
AGND - Analog Ground, PIN 23(L), 17(Q).
Analog ground. Must be connected to DGND with zero impedance.
Analog Inputs
RINI - Right Input #1, PIN 25(L), 19(Q).
Right analog input #1. Full scale input, with no gain, is 1 Vrms, centered at REFBUF.
RIN2 - Right Input ~, pIN 26(L), 20(Q).
Right analog input #2. Full scale input, with no gain, is 1 Vrms, centered at REFBUF.
LINI - Left Input #1, PIN 27(L), 21(Q).
Left analog input #1. Full scale input, with no gain, is 1 Vrms, centered at REFBUF.
LIN2 - Left Input #2, PIN 28(L), 22(Q).
Left analog input #2. Full scale input, with no gain, is 1 Vrms, centered at REFBUF.
Analog Outputs
ROUT - Right Channel Output, PIN 15(L), 9(Q).
Right channel analog output. Maximum signal is 1 Vrms centered at REFBUF.
LOUT - Left Channel Output, PIN 16(L), 10(Q).
Left channel analog output. Maximum signal is 1 Vrms centered at REFBUF.
REFBYP - Analog Reference Decoupling, PIN 21(L), 15(Q).
A 10 IlF and 0.1 JlF capacitor must be attached between REFBYP and REFGND.
REFGND - Analog Reference Ground Connection, PIN 22(L), 16(Q).
Connect to AGND.
REFBUF - Buffered Reference Out, PIN 20(L), 14(Q).
A nominal +2.2 V output for setting the bias level for external analog circuits.
Serial Digital Audio Interface Signals
SDIN - Serial Port Data In, PIN 42(L), 36(Q).
Digital audio data to the DACs and level control information is received by the CS4216 via
SDIN.
SDOUT - Serial Port Data Out, PIN 43(L), 37(Q).
Digital audio data from the ADCs and status information is output from the CS4216 via
SDOUT.
SCLK - Serial Port Bit Clock, PIN 44(L), 38(Q).
SCLK controls the digital audio data on SDOUT and latches the data on SDIN.
4-108
DS83F2
----------------------
CS4216
SSYNC - Serial Port Sync Signal, PIN l(L), 39(Q).
Indicates the start of a digital audio frame in SM3 and SM4, and also the start of a word in
SM! & SM2.
SMODEI - Serial Mode Select, PIN 29(L), 23(Q).
One of three pins that select the serial mode and function of the multifunction pins.
SMODE2 - Serial Mode Select, PIN 32(L), 26(Q).
One of three pins that select the serial mode and function of the multifunction pins.
SMODE3 - Serial Mode Select, PIN 41(L), 35(Q).
One of three pins that select the serial mode and function of the multifunction pins. This pin
has an internal pull-down making this revision backwards compatible with a previous version
(Revision A or Version3-VersionO bits = 0000).
Multifunction Digital Pins
MFl:D04 - Parallel Digital Bit Output #4 in SMl/SM2, PIN 40(L), 34(Q).
In serial modes 1 and 2 this pin reflects the value of the D04 bit in the sub-frame.
MFl:Fl - Format bit 1 in SM3, PIN 40(L), 34(Q).
In serial mode 3 this pin is a format bit and is used as one of three sample frequency select pins
when in master mode, or as one of two bits-per-frame select pins when in slave mode.
MFl:CDOUT - Control Data Output in SM4, PIN 40(L), 34(Q).
In serial mode 4 this pin is the data output for the control port which contains status
information.
MF2:D03 - Parallel Digital Bit Output #3 in SMl/SM2, PIN 39(L), 33(Q).
In serial modes 1 and 2 this pin reflects the value of the D03 bit in the sub-frame.
MF2:F2 - Format bit 2 in SM3, PIN 39(L), 33(Q).
In serial mode 3 this pin is a format bit and is used as one of three sample frequency select pins
when in master mode, or as one of two bits-per-frame select pins when in slave mode.
MF2:CDIN - Control Data Input in SM4, PIN 39(L), 33(Q).
In serial mode 4 this pin is the control port data input which contains data such as gain and
attenuation settings as well as input select, mute, and digital output bits.
MF3:DI3 - Parallel Digital Bit Input #3 in SMlISM2ISM3 (Slave), PIN 35(L), 29(Q).
In serial modes 1 and 2 this pin value is reflected in the 013 bit in the sub-frame.
MF3:F3 - Format bit 3 in SM3 (Master), PIN 35(L), 29(Q).
In serial mode 3 this pin is a format bit and is used as one of three sample frequency select pins
when in master mode. In slave mode, the pin reverts to being a general purpose input.
MF3:CCLK - Control Data Clock in SM4, PIN 35(L), 29(Q).
In serial mode 4 this pin is the control port serial bit clock which latches data from CDIN on
the falling edge, and outputs data onto CDOUT on the rising edge.
DS83F2
4-109
----------------------
CS4216
MF4:DI4 - Parallel Digital Bit Input #4 in SMlISM2, PIN 36(L), 30(Q).
In serial modes 1 and 2 this pin value is reflected in the DI4 bit in the sub-frame.
MF4:MA - Master Sub-Mode in SM3, PIN 36(L), 30(Q).
In serial mode 3 this pin selects either master or slave mode. When MF4:MA== 1, the codec is
in master mode and outputs SSYNC andSCLK. When MF4:MA= 0, the codec is in slave
mode and receives SSYNC and SCLK from an external source that must be frequency locked
to CLKIN.
MF4:CCS - Control Data Chip Select in SM4, PIN 36(L), 30(Q).
In serial mode 4 this pin is the control port chip select signal. When low, the control port data is
clocked in CDIN and status data is output on CDOUT. When CCS goes high, control data is
latched internally. This data remains active until new data is clocked in. The control port may
also be asynchronous to the audio data port.
MF5:D02 - Parallel Digital Bit Output #2 in SMl/SM2ISM3, PIN 38(L), 32(Q).
In serial modes 1, 2, and 3 this pin reflects the value of the D02 bit in. the sub-frame.
MF5:INT - Interrupt in SM4, PIN 38(L), 32(Q).
In serial mode 4 this pin is an active low interrupt signal that is maskable using the MSK bit in
the control port serial data stream. INT is an open-collector output and requires and external
pull-up resistor. Assuming the mask bit is not set, and interrupt is triggered by a change in ADV
or DIl, or a rising edge on LCL or RCL, or a exiting an SCLK out of range condition
(Error = 3)
MF6:DI2 - Parallel Digital Bit Input #2 in SMlISM2/SM3, PIN 34(L), 28(Q).
In serial modes 1,2, and 3 this pin value is reflected in the DI2 bit of the sub-frame.
MF6:Fl - Format Bit 1 in SM4, PIN 34(L), 28(Q).
In serial mode 4 this pin is a format bit and is used as one of three sample frequency select pins
when in master mode. In slave mode, MF6:Fl helps determine the number of sub-frames within
a frame.
MF7:SFSI - Sub-Frame Select 1 in SMlISM2/SM3/SM4-SL, PIN 31(L), 25(Q).
In serial modes 1, 2, and 3, MF7:SFSI helps select the sub-frame that this particular CS4216 is
allocated. In slave sub-mode of serial mode 4, this pin is one of two pins used as a sub-frame
select when MF6:Fl = 1 (128-bit frames). When MF6:Fl = 0, this pin is used to select the
frame sizes of 32 or 64 bits.
MF7:F2 - Format Bit 2 in SM4-MA, PIN 31(L), 25(Q).
In master sub-mode of serial mode 4, this pin is used as one of three· sample frequency select
pins.
MF8:SFS2 - Sub-Frame Select 2 in SMlISM2ISM3/SM4-SL, PIN 30(L), 24(Q).
In serial modes 1,2,3, and slave sub-mode of 4, MF8:SFS2 helps select the sub-frame that this
particular CS4216 is allocated.
MF8:F3 - Format Bit 3 in SM4-MA, PIN 30(L), 24(Q).
In master sub-mode of serial mode 4, this pin is a format bit and is one of three sample
frequency select pins.
4-110
DS83F2
----------------------
CS4216
Miscellaneous
RESET - Reset Input, PIN 2.(L), 40(Q).
Resets the CS4216 into a known state, and must be initiated after power-up or power-down
mode. Releasing RESET caused the CS4216 to initiate a calibration sequence. RESET should
also be initiated when changing sample frequencies in any master sub-mode.
CLKIN - Master Clock, PIN 3(L), 41(Q).
CLKIN is the master clock that operates the internal logic. In serial mode I,
CLKIN = 512xhFs, where hFs is the highest sample frequency needed. Different sample
frequencies are obtained by changing the ratio of SCLK to CLKIN. In serial mode 2, CLKIN is
not used and must be tied low. In serial modes 3 and 4, CLKIN is 256xhFs, where different
sample frequencies are obtained by either changing the ratio of SCLK to CLKIN in slave mode,
or changing the format pin values (F2-FO) in master mode.
PDN - Power Down, PIN 13(L), 7(Q).
This pin, when low, causes the CS4216 to go into a power down state. RESET should be held
low for 50 ms when exiting the power down state to allow time for the voltage reference to
settle.
DIl - Parallel Digital Bit Input #1, PIN 33(L), 27(Q).
This pin value is reflected in the DII bit in the sub-frame.
DOl - Parallel Digital Bit Output #1, PIN 37(L), 31(Q).
This pin reflects the value of the DOl bit in the sub-frame.
NC - No Connection,
PINS 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 19(L)
PINS 44, 1, 2, 3, 4, 5, 6, 8, 11, 12, 13(Q).
These pins should be left floating with no trace attached to allow backwards compatibility with
future revisions. They should not be used as a convenient path for signal traces.
DS83F2
4-111
_.
-----------------------
CS4216
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, arid in the output words from the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal codewidth. Units in LSB.
Total Dynamic Range
TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is
measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e.
attenuation bits for the DACs at full attenuation). Uqits in dB.
Instantaneous Dynamic Range
IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the harmonic distortion components to insignificance when
compared to the noise. Units in dB.
Total Harmonic Distortion
THD is the ratio of the rms value of a signal's first five harmonic components to the rms value
of the signals fundamental component. THD is calculated using an input signal which is 3dB
below typical full-scale, and is referenced to typical full-scale.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel, with 1 kHz
o dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Frequency Response
Worst case variation in output signal level versus frequency over the passband. Tested over the
frequency band of 10 Hz to 20 kHz, with the sample frequency of 48 kHz. Units in dB.
Step Size
Typical delta between two adjacent gain or attenuation values. Units in dB.
Absolute Gain!Attenuation Step Error
The deviation of a gain or attenuation step from a straight line passing through the
no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB.
Offset Error
For the ADCs, the deviation of the output code from the mid-scale with the selected input at
REFBUF. For the DACs, the deviation of the output from REFBUF with mid-scale input code.
Units in LSB's for the ADCs and volts for the DACs.
4-112
DS83F2·
----------------------
CS4216
Out of Band Energy
The ratio of the fIllS sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale
signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz.
-
DS83F2
4-113
._.-.
_.-_.....__.._-_
...
·CS4216
APPENDIX A
This data sheet describes version 1 of the CS4216. Therefore, this appendix is included to describe the
differences between version 0 and version 1. This infonnation is only useful for users that still have
version 0 since version 1 devices will supplant the earlier version. The version number is contained in
the serial data line, bits 29 - 32 on SDOUT in SM1-SM3 and, bits 17 - 20 on CDOUT in SM4. The
version number can also be identified by the revision letter stamped on the top of the actual chip. The
revision letter immediately precedes the data code on the second line of the package marking (See
General Information section of the Crystal Data Book). Version 0 corresponds to chip revision A, and
version 1 corresponds to chip revisions B, and C. The functionally and perfonnance of revisions B
and C are identical. Likewise, future chip revisions (i.e. D, E, F, ... ) may still be version 1 since the
version number only changes if there is a software change to the part.
Functional Differences Between Version 0 (Rev. A) and Version 1 (Revs. B, C)
1. In version 0, serial mode 4 (SM4) does not exist; the SMODE3 pin is a no connect. In version 1 the
SMODE3 pin contains an internal pull-down resistor making this version backwards compatible with
version 0 sockets.
2. SSYNC on version 0 must be ONLY one SCLK period high in SM3 or 2 SCLK periods high in
SMI and SM2 to indicate the start of a frame. Also, on version 0 in SMI or SM2, SSYNC must be
EXACTLY one SCLK period high, at the beginning of each word. In version 1, SSYNC can be high
for an arbitrary number of SCLKs beyond the one in SM3 or two in SMI and SM2. Also in SMI and
SM2, the one-SCLK-wideSSYNCs at each word are not needed. In version 1, SM3 and SM4, the
codec only looks for a low-to-high edge of SSYNC to start a frame; in SMI and SM2 a low-to-high
edge of SSYNC, being high for two SCLK periods, starts a frame.
4-114
DS83F2
..... -........
~~
~
~~~.
CDB4216
~.
~~
~
Semiconductor Corporation
CS4216 Evaluation Board
Features
General Description
The CDB4216 evaluation board allows easy evaluation
of the CS4216 audio multimedia codec. Analog inputs
provided include two BNC line inputs for LlN1 and
RIN1, and two 1/4" microphone jacks on the LlN2 and
RIN2 lines. Analog outputs are available on two BNCs.
• Easy DSP Hook-Up
• Analog-in To Analog-out Loopback
Mode
Digital interfacing is facilitated using one to three of the
buffered ribbon cable headers. All four serial modes of
the CS4216 are supported using a simple DIP switch
which is decoded to select the proper mode and submode.
• Correct Grounding and Layout
• Microphone Pre-amplifier
• Line Input Buffer
• Digital and Analog Patch Areas
ORDERING INFORMATION: CDB4216
LlN2
Digital
I/O Port
00
00
00
00
00
00
.RIN2
"
00
Control
Port
Audio
Port
Microphone
Jacks
CS4216
00
00
00
Digital
I/O
Buffers
&
MUX
00
00
00
00
00
00
00
LlN1
Line Inputs
RIN1
LOUT
ROUT
Line Outputs
(+5V)
(+5V)
ClKIN
VD DGND
AGND
VA
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
JUN '93
CS83DB4
4-115
_.-_..__..--_
....-.
---.~.
GENERAL DESCRIPTION
The CDB4216 was designed to provide an easy
platfonn for evaluating the performance of the
CS4216 Stereo Audio Codec. Since the evalu. ation board contains a proper layout and is
.perfonnance tested, the user can concentrate on
engineering the rest of the system thereby reducing the development time. The layout should
also be used as a guideline for obtaining the best
possible performance from the CS4216. Lastly,
the board can be used as a benchmark and debugging tool for ·user developed PCBs.
The evaluation board· supports all serial modes
and includes decode circuitry to ease the selection of the serial mode and sub-mode of interest.
All serial interfaces are buffered for easy connection to the serial port of a DSP or other serial
device. The board can also be placed in a loop
back mode where the digital data is looped back
allowing an analog in to analog out testing vehicle without an external processor. A single +5V
supply is all that is needed to power the board.
Analog inputs consist of a pair of line input
buffers (LIN1, RIN1) designed to accept a maximum audio signal of 2VRMS and BNC-to-phono
adapters are included to support various test configurations. The second pair of inputs contain a
example microphone input buffer supported by
two 1/4" mono jacks that are designed to accept
standard single-ended dynamic or condenser microphones.
The line outputs are· supplied via BNC connectors with two more BNC-to-phono adapters.
The film plots of the evaluation board are included to provide an example of the optimum
layout, grounding, and decoupling arrangement
for the CS4216.
CDB4216
SELECTING A SERIAL MODE
The CS4216 supports four serial modes and
many sub-modes. Selecting the most appropriate
mode for a given application can be time consuming. The CDB4216 contains a DIP switch
that simplifies this selection. Since the CS4216
contains many multifunction pins, the DIP
switch lets the user select the configuration and
two PLDs decode the proper multifunction pin
values. Since these PLDs are only used to simplify the configuration of the device, they would
not be needed in an end application which would
hard wire the configuration pins. Table 4 describes the multifunction pin values for a given
DIP switch setting. The PAL equations for DIP
switch decoding are given in Figures 8 and 9.
Serial Port Format
Table 1 lists the DIP switches used to select the
serial mode. SPF2 and SPF1 select one the four
serial modes of the CS4216. MA selects master
(MA = 1) or slave and is only useful in serial
modes 3 and 4. The majority of users select
either serial mode 3, SM3, or serial mode 4,
SM4. Serial modes· 1 and 2, SM1 and SM2, are
primarily designed for ASICs and are less flexible. In master sub-mode, the CS4216 outputs
SSYNC and SCLK. In slave sub-mode, SSYNC
and SCLK must be externally generated and
must be synchronous to CLKIN.
SPF2
SPF1
MA
0
0
1
1
1
1
0
1
0
0
1
1
x
x
0
1
0
1
Serial Mode
SM1
SM2
SM3
SM3
SM4
SM4
Slave
Slave
Slave
Master
Slave
Master
Table 1. DIP Switch, Serial Modes
4-116
DS83DB4
----------------------
CDB4216
Bits per Frame Selection
The next decision is selecting the number of bits
per frame which defines how many codecs can
sit on the same serial bus. Each codec occupies a
sub-frame and 1 to 4 sub-frames make up a
frame. A sub-frame is 64 bits in SMl, SM2, and
SM3; and 32 bits in SM4. Table 2 lists the possible selections. If the evaluation board serial port
is shared with other devices, SDOUTUB must
be used instead of SDOUT since SDOUTUB,
driven directly from the chip, must only drive
the time slot assigned to it. See the Audio Port
Header section for more information.
BPF
1
SM1
SM2
SL
MA
SL
SM4
MA
0
0
0
1
1
0
256
256
256
256
64
128
256
256'
64
128
128
128
32
64
128
128
32
64
64
64
2
, SCLK
1
1
IS
SM3
TS2
TS1
4
0
0
0
1
1
0
1
1
Available Sub-frames
1
2
1
2
3
4
1
2
2
2
1
1
1
1
Table 3. DIP Switch, Time Slots
master clock.
Table 2. DIP Switch, Bits per Frame
Time Slot Selection
If the number of bits per frame selected allows
for more than one codec sub-frame, then the actual time slot or sub-frame used by the eval
board must be selected. This is done with the
TS2 and TS 1 DIP switches. If the number of bits
per frame allows only one codec on the serial
bus, then TS2 and TS 1 are ignored. Table 3 list
the decoding for TS2 and TS 1. Time slot 1 is the
first sub-frame after SSYNC goes high, time
slot 2 is the next sub-frame, and so on.
Sample Frequency Selection - Master Mode
The last decision is selecting the sample frequency in master sub-mode. If configured for
slave sub-mode, the sample frequency is the ratio of SCLK to CLKIN as described in the
CS4216 Data Sheet. In master mode, three pins
are used to select the sample frequency divide.
DS83DB4
The DIP switches labeled DIVl, DIV2, and
DIV3 select the sample frequency and are
equivalent to Fl, F2, and F3, respectively. The
actual FI-F3 pins on the CS4216 are different
between SM3 and SM4 as shown in Table 4 at
the end of the data sheet. Table 3 and Table 9 of
the CS4216 Data Sheet describe the sample frequencies obtained using the on-board oscillator
of 11.2896 MHz. As an example, if all DIV
switches are off, the sample frequency is
44.1 kHz. With only DIV2 on, the sample frequency is 22.05 kHz.
DIP SWITCH MAPPING TO MULTI-FUNCTION PINS
The two PALs on the evaluation board decode
the DIP switches to configure the codec into a
particular mode. These PALs are not necessary
in a design since only one mode is usually used
and can be hard wired. Figure 9 and Figure 10
list the PAL equations used for decoding.
Table 4 shows the CS4216 multi-function pin
settings for each possible DIP switch configuration. Refer to the CS4216 data sheet to
determine pin settings for sample frequencies.
Once a suitable mode has been chosen using the
evaluation board, this table will show the hard
wire configuration for each multi-function pin.
Example Mode Settings
Following are two examples of how to set a serial mode with the DIP switches and then
determine the multi-function pin settings for the
codec. These modes were chosen for illustration
4-117
_
..-__....._-_
...-.-.
.-_
CDB4216
only, not to suggest that they are better than
other modes.
A commonly used mode is SM3, Master, 64
BPF, 44.1kHz sampling rate, and bit-long
SSYNc. To configure the codec in this mode,
set SPF2=MA=l and all other DIP switches to
zero. From Table 4, the SMODE3, SMODE2,
and SMODEI pins are set to .010, respectively.
The DIVl, DIV2, and DIV3 DIP switches will
set the sampling frequency by directly mapping
to the MF1, MF2, and MF3 pins as 000. The
MA DIP switch sets the MF4 pin high for master
mode. multi-function pins MF5 and MF6 become the general purpose 1/0 pins D02 and
DI2, respectively. In this particular mode, MF7
determines the high time for the SSYNC signal.
The MF7 pin is set low by the TS 1 switch to
generate the bit-long SSYNC. In all other applicable cases, the TS 1 switch is used for time-slot
configuration. 64 BPF is selected by setting the
MF8 pin low with the BPFI switch.
SM4 is a powerful mode which reduces data
transfer bandwidth to facilitate easier use with
low cost DSPs. As an example, consider SM4,
Slave, 64 BPF, Time-slot 2, and a 22.05kHz
sampling
rate.
Set
SPF2=SPFl=DIVl=TSl=BPFl=l and all other
DIP switches to zero. Table 4 shows that the
SMODE3, SMODE2, and SMODEI pins will be
OIP SWITCHES
SMOOE' SMOOE' SMOOE
SPF2' SPF1' MA
2
1-°_
:_o_:~
3
°
~
°
. --
q: : :
LOOPBACK MODE
The CDB4216 may be configured in a simple
loop back mode that only requires a power
source to operate. No controller of any type is
necessary. This mode allows a quick and simple
verification of codec operation by sampling the
LINl and RINl inputs, then looping the digital
data back to the LOUT and ROUT line outputs.
Set SPF2=SPFl=MA=1 and shunt SDOUT to
SDIN on stake header 115. This mode uses. SM4
with all control settings set to zero, so no gain or
attenuation is available.
CS4216 Multifunction Pins
~--~----~----~--------------~--~----~
° ' °_
0'
=: =0=
'1 '0
0'
1
'
~ 0--': :~<_':::i
0 _~ ~1~ ::..:- ~
1 ' 1 '0
l'
1
'
: 1: : :: ): :: :
1: : ; :
:0::
___ :_ J _ .: _1.. __ 1__ ; ~PF:=q :___0_.
l ' BPF>O' TS1
, 1 '1
I- 0_ ,_1 _'
set to 110, respectively. The multi-function pins
MFI-4 will become the control port interface.
MF5 serves as the interrupt pin INT. BPF2 and
BPFI will set the codec to 64 -BPF by mapping
directly to the MF6 and MF7 pins as 01, respectively. The second time-slot is chosen with TS 1
setting the MF8 pin high. Since the part is in
slave mode, the sampling rate must be set by the
ratio between CLKIN and SCLK. Assuming
that CLKIN has a frequency of 11.2896MHz,
this ratio must be eight to give a sampling rate
of 22.05kHz (refer to the CS42l6 data sheet). In
all slave modes, SSYNC and SCLK must be
synchronous to the master clock.
MF1
,
MF2 ,
004
'
003 '
MF3 ,
:< : : :
COOUT'
~o:O!Jr:
COOUT:
coeur;
MF5 ,
MF6 ,
MF7 , MFa
013 ' 014 ' 002'
012 ' TS1 ' TS2
=oii =:Qj4=: = OQ?
~Ig::: := T§.:1 ::::: -.!S~
_BPr=1_ ; _ 1?1;3 _ ; !oIIf.,:,O. ~ _ I)()~ _: __ DI2_.: Tl?1. _: _ :rl?~ _
OJY2_ _01.'{3 -,_MA=L' _OQ? -.:.. J?I?... '_ TS1 --'- BP~
COIN ' CCLK' CCS ' INT 'BPF2=0' BPF1 ' TS1
:C:O!N: : :C~~~ :: ¢~S: : : iN!: ::~p)=?~<: ~S:1: ::: :r~~
COIN : CCLK : CCS : INT : 0lV1 : 0lV2 : 0lV3
·COiN- ; -CCLK ~ . CCS- -, . INT· -, - 01\11· -, 01\12 -, - -olva-
:= :I° _ :QoI := Q9L:
i.- Q!VL -'-°
I;l~F~ _ ,
MF4 ,
==
:
:
Table 4. CS4216 Pin Decode
4-118
DS83DB4
_.-_..--_._.
_-.._-_
...-.
CDB4216
VD
(+5V)
-
DGND
R26
VA
2(2
r-----~--~\I\I\~--~----~----~~--_,----
0
VA
(+5V)
D4
P6KE
'-----------------<~-O
AGND
4
VD REFBYP
Microphone
Input Buffer
See Figure 3
28
26
20
Line Input
Buffer
See Figure 2
See Figure 7,8
27
25
lOUT
16
RIN2
REFBUF
LlN1
RIN1
CS4216
U1
ROUT
15
1 uF
3
41
32
See Figure 5
C32
LlN2
29
31
30
ClKIN
RESET
SMODE3
MF4
SMODE2
MF3
SMODE1
MF6
2
See Figure 6
36
35
See Figure 5
34
MF7
MF8
DGND
REFGND
AGND
23
Figure 1. CS4216 and Power Supplies
DS83DB4
4-119
----------.-----_
... ---POWER SUPPLY CIRCUITRY
Figure 1 illustrates a portion of the CDB4216
schematic and includes the CS4216 along with
power supply decoupling and circuitry. The
evaluation board supports various power supply
arrangements. The factory configuration powers
the analog portion of the CS4216, along with input buffers, from the VA binding post, which
needs a clean +5 Volts. The digital portion of the
CS4216 is factory configured to obtain power
through a 2Q resistor -from the VA supply. The
digital buffers and PLDs obtain power from the
VD binding post, which also needs +5 Volts. Although binding posts exist for both digital and
analog grounds, only one needs to be connected
if a single supply is used for both VA and YD.
Note that the CS4216 is entirely on the analog
ground plane, close to the ground plane split as
required by the CS4216 Data Sheet. Also note
that the two ground planes are connected near
the two ground binding posts.
CDB4216
The microphone inputs are connected to the
CS4216's LIN2 and RIN2 pins. The two microphone inputs are single-ended and are designed
to work with both condenser and dynamic microphones. The microphone input buffer, shown
in Figure 3, has a gain of 23 dB thereby defining
a full-scale input voltage to the microphone
jacks of 71 mVRMS. Another 22 dB of programmable gain is available on the CS4216 to
amplify smaller microphone signals.
An analog patch area with analog power and
ground, included on the CDB4216, provides
space to develop other input buffer circuits.
Space for headers are included, 119 and 120, to
comiect to the LIN2 and RIN2 inputs. To use
these headers, the microphone traces must be
cut.
ANALOG OUTPUTS
Space for a ferrite bead, Ll, is provided so that
the board may be modified to power the codec
from the digital supply. Selection of L1 will depend on the noise characteristics of the digital
supply used.
The CS4216 drives the line outputs into an R-C
filter and then to a pair of BNCs labeled LOUT
and ROUT. As with the line inputs, BNC-tophono adapters are provided for flexibility. The
line outputs can drive an impedance of 10 ill or
more, which is the typical input impedance of
most audio gear.
ANALOG INPUTS
AUDIO PORT HEADER
The analog inputs consist of a pair of line level
inputs and a pair of 1/4" mono jacks for two microphones. BNC-to-phono adapters are included
to allow testing of the line inputs using coax or
standard audio cables.
The CDB4216 is primarily designed to evaluate
the CS4216 in single chip mode, i.e. only one
codec on the serial bus. This is the factory default state of the CDB4216.
The line-level inputs are connected to the
CS4216's LINI and RINI pins. As shown in
Figure 2, the line-level inputs go through a buffer set to a gain of 0.5 which allows input signals
of up to 2 VRMS. When placed in serial mode 4
with loop back, the LINI and RINI inputs are
used for analog inputs.
4-120
The audio port header 115 provides all buffered
signals necessary to connect to the serial port of
a DSP or other controller (see Figure 4). SDOUTUB can provide an unbuffered version of
SDOUT which can be used when connecting
multiple codecs on the same bus. The default
configuration does not connect SDOUTUB
which may be connected to the SDOUT of the
CS4216 through 117 jumper.
DS83DB4
----------------------
CDB4216
R20
R21
1k
13 k
C23
10UF~
C16
VA
CS4216
RIN2
RIN2
20
C37
J19
~ _- ~LMIC ~0.1 uF
R25
1-
LlN2
(Mono)
150
C24+
10UF~
C15 1000 pF
NPO
R23
1k
REFBUF
LlN2
C18
0.47uF
~0.01 uF
NPO
13 k
Figure 2. Microphone Input Buffer
10.~F
LlN1
CS4216
27
C13
C12
R11
0.47uF~
tr
C11
RIN1
(Mono)
LlN1
~ 0.01 uF
LT1013
3
20 k
1 uF R15
+
2
R13
NPO 20
REFBUF
C37
~ 0.1 uF
R17
25 RIN1
C14
~ 0.01 uF
NPO
Figure 3. Line Input Buffer
DS83DB4
4-121
----------------------
CDB4216
The eval board supports both master and slave
sub-modes. In master sub-mode, SSYNC and
SCLK are output (and buffered) from the
CS4216. In slave sub-mode, SSYNC and SCLK
must be provided externally and must be synchronous to the master clock CLKIN.
CONTROL PORT HEADER
The Control Port Header 114 contains the control
port pins, available only in SM4, and the PDN
and RESET pins.
are available on this header. Since CDOUT is
buffered and always driven, it cannot be used on
a shared serial port. Although the INT pin on the
codec is open drain, the default factory configuration for the eval board is an on-board pull-up
resistor and a buffer. Therefore, the !NT header
pin cannot share an interrupt pin on a processor
since it is buffered and will always be driven. By
cutting a trace in the 118 jumper, the unbuffered
!NT signal, labeled U, can be supplied to the
header. When using the control port, the LB
switch must be off or the control serial port will
be blocked.
Serial mode 4, SM4, splits the serial data to the
codec into two separate serial ports, the audio
port and the control port. The control port pins
U6
74HC243
SSYNC
SSYNC
SCLK
R44
10
OEA
S
9
44
SCLK
OEB
B3
A3
1
CFSIN
13
6
5
R10
10
CS4216
SDOUT
SDIN
DI1
MFl
, SDOUTUB
, SDOUT
43
, SDIN
: SCLK
_' SSYNC
42
33
40
R49
L-_-'.lo:..3.!.1:1/1-/V-~4,---"~_ _'--h' DI2
L - - - - - W v - c - - - - - - , h : DI1
MF2
MF5
PDN
39
>T~-----~Jvv'r_---~n,D04
~~~~--~V'v~----~ :D03
F--!VV'v'--"S'-'--_ _---'-n
38
' D02
13
806
DOl
37
U7
A9
237k
Figure 4. Serial Port Headers
4-122
DS83DB4
C
en
~
c
'''.i'·.1:
DJ
....
VO
VO
C3~
SW3'
0.1"r
19
18
17
16
SMOOEl
MF8
MF7
SMOOE2
SMOOE3
CFSIN
R34
10k
:9 _8 7_ ~ _5 _4 3_
1
- - -
? _:
y
13
20
1
2
U9
3
PALCE16VSZ 4
' \ ' \ ' \ '\ '\
- -
- - - -
'\
-
-
C40E
O.lU~
' -
24
24
1
2
3
4
5
5
6
7
8
9
15
14
13
12
10l
= SWX
Ul0
20
14
13
'Tl-
R53
27k
R54
27k
....--=
y
~~~
R37 R36-s
R33
47k
47k
47k
~:
2 3 4 5 6 7 8 9 10
16 - - - - - : R35 ,_
_
_ _ _ ' 47k '_
1
1
R48
,- - '6
5
.4
, ::: '3
1~
14
:R49
,100
3
121
, RESET
, PON
,
:,'"......,....
: INT
,CCS
'0 , CCLK
, CDIN
~
MFla
MF2
MF4
MF3
MF6
,1!
VO
'''IT,
~~
MFlb~ : COOUT
21
19
18
17
16
I--°SWY~
0--
R47
27k
PALCE22Vl0Z
6
7
8
9
- - - -
" Tr
\
~~~~Cij~~~<~~m
12 CO 0 0 0 I- I- III m ::!: en en ...J 1
' -b-!)- g I)-b -(\- g 0 -6-5 I>" ::L-
2 3_ ~ _5 6
R4S:
10k,
1
:1
014
",013
012
011
<
~ 27k
o
c
OJ
t....
en
...i'"
Figure 5. DIP Switch Decode + Digital Header
~
I
.._-_
_-_..__
...-.
•
,..w _ _ . _ .
CDB4216
PDN and RESET
PDN is buffered and controls the PDN pin on
the CS4216. PDN contains an on-board pull-up
resistor defining the default state as powered.
This pin only needs to be controlled when the
power down feature is used.
RESET is also buffered and controls the RESET
pin on the codec (see Figure 6). RESET has a
pull-up resistor on the board defining the default
state as not reset or active. This pin only needs
to be controlled when the reset feature on the
codec is needed. Since the codec requires a reset
at power up, a power-up reset circuit is included
on the board. A reset switch is also included to
allow resetting the device without having to remove the power supply. The power-up reset plus
switch are logically ORed with the RESET pin
on header 114.
VD
In SMI and SM2 all four digital inputs and outputs are available. In SM3, only the first two
inputs and outputs are functional. In SM4 only
DOl and DIl are functional. See the CS4216
Data Sheet for more details.
CLOCKS
The CDB4216 provides an on-board default
clock oscillator of 11.2896 MHz (see Figure 7).
This allows all 44.1 kHz and derivative sample
frequencies in SM3 and SM4. If using SM1, a
master clock with a frequency that is 512 times
the highest sample rate must be supplied. A
CLKIN BNC allows the eval board to be driven
from an external source. To select the CLKIN
frequency, the 11 jumper must be placed in the
EXT position. When the 11 jumper is in the !NT
position, the on-board oscillator is used as the
master clock. Both clock sources are buffered to
guarantee a clean signal and proper clock levels
to the codec.
, CS4216
RESET
f---<_~l\l\f,--(
Dl
lN4148
R2
R4
47,5k
100
RESET
---I-
SW1~
+ Cl
1:'1 uF
Figure 6. Reset Circuit
If sample frequencies other than the ones provided are needed, the oscillator can be replaced
with the proper frequency oscillator. The board
accepts crystals and provides the socket YI (refer to Figure 8). When using a crystal, U8 must
contain an HCU04 unbuffered CMOS inverter.
The U8 socket is designed to accept either the
HCU04 or a crystal oscillator, and can alternate
between the two.
DIGITAL I/O HEADER
LAYOUT ISSUES
The Digital I/O Header, 113 shown in Figure 4,
contains the four digital inputs, DIl-DI4, and the
four digital outputs, D01-D04. Note that all
digital I/O except DII and DOl are multifunction pins and may not be available in a particular
mode. Since DOl is always a digital output, an
LED is connected to DOl providing a visual indication that software is writing this bit correctly.
When the LED is on, DO I is high.
Figure 11 contains the silk screen, Figure 12
contains the component-side copper layer, and
Figure 13 contains the solder-side copper layer
of the CDB4216 evaluation board. These plots
are included to provide an example of how to
correctly layout a PCB for the codec.
Grounding and Power
Notice in Figure 12 and Figure 13 how the
ground plane split is positioned. The split is
4-124
DS83DB4
_.-_..--__.._-_
...
._.-.
CDB4216
CS4216
R8
3
elKIN
10
Figure 7. Default Clock Circuit
next to the part - NOT UNDER IT. The AGND
and DGND pins are connected to the ground
plane fill inside the codec pad layout on the
component-side layer. This is recommended because AGND and DGND are connected on the
codec die and must have a zero impedance between them.
Notice how each ground connection has at least
four points in thermal relief. The main board
grounds at the terminal connections have eight
points in thermal relief. This helps minimize the
impedance to the main ground terminal from any
particular ground pin, reducing the chance of
noise coupling.
Another important design consideration is the
ground plane fill between traces on both layers,
which minimizes coupling of radiated energy.
Ground fill on the digital side of the board helps
reduce the amount of noisy digital energy radiated to the sensitive analog side and to a host
system. Ground fill on the analog side helps reduce the amount of radiated digital energy that is
coupled into the analog circuitry. All ground
plane fills must be connected to their respective
grounds - floating ground fill is worse than no
fill.
All power and ground traces are as thick as the
surface mount pads they connect. Thick traces
C44
l C43
33 pF ~ _---'R1J\.5/15,-_ ~ 33 pF
VD
O~:F~
10M
)0-.::.8---c::::> CLKIN-J 1
US
74HCU04
Figure 8. Optional Clock Circuit
DS83DB4
4-125
-_--_
-_.._-_.......
.
....
CDB4216
minimize impedance, thereby reducing the
chance of noise coupling.
Decoupling
Notice how the decoupling capacitors are placed
as close as possible to the codec. The O.IJlF capacitors are placed closer than the lOJlF or IJlF
capacitors. This reduces lead inductance at high
frequencies and allows the smaller valued capacitors to attenuate unwanted signals more
effectively.
Sockets
The CDB4216 was designed to accommodate
either the 44-pin PLCC package or the 44-pin
TQFP package. Each evaluation board is
shipped with a PLCC codec loaded into a surface mount socket. Notice how the socket pads
match the footprint of the PLCC package. Using
this socket in a design allows for testing with the
socket mounted, and the option to surface mount
the codec directly for cost reduction during
board production.
4-126
DS83DB4
.._-_
_.-_..--_._.
__
...-.
CDB4216
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
CDB4216
PATTERN
4216S_B
REVISION
4.0B
C. Sanchez, M. Jordan
AUTHOR
COMPANY
Crystal Semiconductor
DATE
5/28/93
.i:
CHIP _4216s_b PALCE16V8
;---------------------------------- PIN Declarations --------------/SPF2
COMBINATORIAL; INPUT
PIN
1
COMBINATORIAL; INPUT
2
PIN
/SPFI
COMBINATORIAL; INPUT
PIN
IMA
3
COMBINATORIAL; INPUT
4
IBPF2
PIN
COMBINATORIAL; INPUT
PIN
5
IBPFI
COMBINATORIAL; INPUT
6
ITS2
PIN
COMBINATORIAL; INPUT
PIN
7
ITS 1
COMBINATORIAL; INPUT
PIN
8
IDIV3
COMBINATORIAL; INPUT
9
IDIV2
PIN
PIN
10
GND
PIN
11
NC
COMBINATORIAL; OUTPUT
PIN
12
/CFSIN
13
NC
PIN
PIN
14
NC
PIN
15
SMODE3
COMBINATORIAL OUTPUT
PIN
16
SMODE2
COMBINATORIAL OUTPUT
PIN
17
MF7
COMBINATORIAL OUTPUT
COMBINATORIAL OUTPUT
PIN
18
MF8
19
SMODEI
COMBINATORIAL OUTPUT
PIN
VCC
PIN
20
;----------------------------------- Boolean Equation Segment -----EQUATIONS
/CFSIN = SPF2
SMODE3
* MA
=SPF2 * SPFI
SMODE2 = SPF2 * /SPFI
+ SPF2 * SPFI
+ SPF2 * SPFI
+ SPF2 * SPFI
+ SPF2 * SPFI
+ SPF2 * SPFI
SMODEI
* IMA
* MA * BPFI * TSI
* MA * BPFI * TS2
* MA * BPF2' TSI
* MA * BPF2 * TS2
=/SPF2 * SPFI
+ SPF2
+ SPF2
* SPFI • MA * BPFI
* SPFI * MA * BPF2
MF8 = /SPF2 • TS2
+ SPF2 * /SPFI * MA * BPF2
+ SPF2 • /SPFI • MA * BPFI
+ SPF2 * /SPFI * /MA * BPF2 * TS2
+ SPF2' SPFI *IMA *IBPF2' BPFI • TSI
Figure 9. PALCE16V8H PAL Equations.
DS83DB4
4-127
_.-_..__..--_
...-.
~--.-.
+ SPF2 • SPFI * IMA * IBPF2 * BPFI
+ SPF2 • SPFI * IMA • BPF2 * TS2
+ SPF2 * SPFI • MA * DIV3
MF7
=ISPF2 • TS 1
+ SPF2
+ SPF2
+ SPF2
+ SPF2
+ SPF2
+ SPF2
+ SPF2
CDB4216.
* TS2
* ISPFI * IMA * IBPF2 * BPFI • TSI
* ISPFI * IMA * IBPF2 * BPFI * TS2
* ISPFI * IMA * BPF2 * TSI
* ISPFI * MA' TSI
* SPFI * IMA * IBPF2 * BPFI
* SPFI * IMA * BPF2 * TSI
* SPFI * MA * DIV2
Figure 9. Continued.
4·128
DS83DB4
---------- .. _----------
CDB4216
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
CDB4216
PATTERN
42 I 6L_B
REVISION
2.0B
AUTHOR
C. Sanchez
COMPANY
Crystal Semiconductor
DATE
4/27/93
-
CHIP _4216U PALCE22VIOZ
;---------------------------------- PIN Declarations --------------ISPF2
COMBINATORIAL; INPUT
PIN
1
COMBINATORIAL; INPUT
2
ISPFI
PIN
COMBINATORIAL; INPUT
3
IMA
PIN
COMBINATORIAL; INPUT
PIN
4
/BPF2
COMBINATORIAL; INPUT
IBPFI
PIN
5
COMBINATORIAL; INPUT
6
IDIV3
PIN
COMBINATORIAL; INPUT
7
IDIV2
PIN
COMBINATORIAL; INPUT
PIN
8
IDIVI
COMBINATORIAL; INPUT
9
DI4
PIN
COMBINATORIAL; INPUT
10
DI3
PIN
PIN
II
DI2
COMBINATORIAL; INPUT
PIN
12
GND
COMBINATORIAL; INPUT
PIN
13
CDIN
COMBINATORIAL; INPUT
PIN
14
CCLK
PIN
15
NC
PIN
16
MF6
COMBINATORIAL; OUTPUT
PIN
17
MF3
COMBINATORIAL; OUTPUT
PIN
COMBINATORIAL; OUTPUT
18
MF4
PIN
19
MF2
COMBINATORIAL; OUTPUT
PIN
20
COMBINATORIAL; INPUT
ICCS
PIN
21
MFI
COMBINATORIAL; OUTPUT
PIN
22
NC
PIN
23
NC
PIN
24
VCC
;----------------------------------- Boolean Equation Segment -----EQUATIONS
MFI = SPF2 */SPFI • MA * DIVI
+ SPF2 • ISPFI • IMA
MF1.TRST
* BPF2
=SPF2 • ISPFI
MF2 = SPF2 • ISPFI • MA • DIV2
+ SPF2 • ISPFI • IMA * BPFI
+ SPF2 * SPFI * CDIN
MF2.TRST = SPF2
MF3 = ISPF2 • DI3 + SPF2 * ISPFI * IMA • DI3
+ SPF2 * ISPFI * MA * DIV3
+ SPF2 • SPFI • CCLK
MF4 = ISPF2
* DI4
Figure 10. PALCE22VI0Z PAL Equations.
DS83DB4
4-129
.._-_.
..-_
_
.._-_._.
...-
CDB4216
_-'
+ SPF2 * ISPFl
+ SPF2
MF6
* MA
* SPFl * ICCS
=ISPF2 • DI2 + ISPFl * DI2
+ SPF2
+ SPF2
* SPFl * MA * DIYl
* SPFl * IMA • BPF2
Figure 10. Continued.
4-130
DS83DB4
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Evaluation Boord
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CDB4216
••••••
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•
••••••
Figure 12. CDB4216 Component-side Layer.
4-132
DS83DB4
_.-_..--_._.
-_.._-_
...-.
CDB4216
-
••••••••
••••••••
••••••••
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.......
Figure 13. CDB4216 Solder-side Layer.
DS83DB4
4-133
--------.,.... -..,..,--------
CDB4216
• Notes.
4-134
"
~
DS83DB4
.....
...
.... .....
~
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~~
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~
•
CS4225
Semiconductor Corporation
Digital Audio Conversion System
Features
Description
The CS4225 is a single-chip, stereo analog-to-digital
and quad digital-to-analog converter using delta-sigma
conversion techniques. Applications include CD-quality
music, FM radio quality music, telephone-quality
speech. Four D/A converters make the CS4225 ideal
for surround sound and automotive applications.
• Stereo 16-bit AID Converters
• Quad 16-bit DfA Converters
• Sample Rates From 4kHz to 50kHz
• > 100 dB DAC Signal-to-Noise Ratio
The CS4225 is supplied in a 44-pin plastic package
with J-Ieads (PLCC) or as a die.
• Variable Bandwidth Auxiliary 12-bit AID
• Programmable Input Gain & Output
Attenuation
• +5V Power Supply
• On-chip Anti-aliasing and Output Smooth- Ordering Information
ing Filters
CS4225-KL
CS4225-BL
CS4225-YU
CDB4225
• Error Correction and De-Emphasis
SCUCCLKlIFO
AD2/CDIN/CKFl
PLCC, 0 °C to +70 °C
PLCC, -40°C to +85 °C
die, -40°C to +85 °C operation
Evaluation Board
SDNCDOUT/CKFO AD3/CSlIFl VREF CMOUT
VD+ VA+
DEM
HIS
RST-PDN
f----___ooQ AOUTl
LRCK
f----___o~
AOUT2
f-------O~
AOUT3
SCLK
SDINl
SDIN2
AOUT4
2
SDOUTl
SDOUT2
ISO/ADO,
ISl/ADl
AIN1L
AIN1R
DIF/HOLD
AIN2L
AIN2R
AINAUX
AIN3L
AIN3R
AGND2
OVL
CLKOUT
XTI XTO
FILT
CL
CR DATAUX LRCKAUX SCLKAUX AGNDl DGND
Preliminary Product Information I This .document contains infor~ation for a. new. product.
Crystal
.
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semicoruluctor Corporation 1993
(All Rights Reserved)
NOV '93
DS86PP8
4-135
~'.:.'
~'
-_ _-_
-.'.--_._.
......_...-.
CS4225
ANALOG CHARACTERISTICS( TA = 25°C; VA+, VD+ = +5V; Ful! Scale Input Sinewave, 1 kHz;
Word Clock = 48 kHz (PLL in use); Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown
in "Recommended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.)
Parameter *
Symbol
Min
Typ
Max
Units
-
-
Bits
Bits
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution
Audio channels
Auxiliary channel
16
12
-
-
±O.9
LSB
Audio channels(A weighted):
82
85
-
dB
-
-85
-82
dB
Interchannel Isolation
-
85
-
dB
Interchannel Gain Mismatch
-
.1
dB
ADC Differential Nonlinearity
Dynamic Range
Total Harmonic Distortion + Noise (A weighted)
THD+N
Programmable Input Gain
-0.2
-
Gain Step
1.3
1.5
1.7
dB
-
10
-
LSB
2.66
2.8
2.94
Vpp
-
100
-
-
-
ppml°C
10
15
pF
1.9
2.1
2.3
V
Frequency Response
Audio channels(O to 0.454 Fs):
Offset Error
Full Scale Input Voltage (Auxiliary and Audio channels):
Gain Drift
Input Resistance
(Note 1)
Input Capacitance
CMOUT Output Voltage
-3.0
+0.2
dB
46.7
dB
k!l
Notes: 1. Input resistance is for the input selected. Non-selected inputs have a very high (>1 MQ) input
resistance. The input resistance will vary with gain value selected, but will always be greater
than the min. value specified.
* Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice.
4·136
DS86PP8
_.-_..--_._.
__.._-_
...-.
CS4225
ANALOG CHARACTERISTICS
(Continued)·
Parameter *
Symbol
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution
16
-
-
Bits
-
-
±O.9
LSB
100
-
-
dB
-
-
0.01
%
85
88
-
dB
-
85
-
dB
-
-
0.2
dB
(0 to 0.476 Fs)
-3.0
dB
0.2
-
+0.2
(All Outputs)
-117
dB
0.88
1.0
1.12
dB
-
10
-
mV
2.66
2.8
2.94
Vpp
Gain Drift
-
100
-
ppm/oC
Deviation from Linear Phase
-
-
5
Degrees
-
dB
DAC Differential Nonlinearity
Total Dynamic Range
Total Harmonic Distortion
(DAC muted,A weighted)
(Note 2)
Instantaneous Dynamic Range
(DAC not muted, Note 2, A weighted)
Interchannel Isolation
(Note 2)
Interchannel Gain Mismatch
Frequency Response
Programmable Attenuation
Attenuation Step
Offset Voltage
Full Scale Output Voltage
(Note 2)
THD
Out of Band Energy
(Fs/2 to 2Fs)
-
-60
Analog Output Load
Resistance:
Capacitance:
8
-
-
100
kQ
pF
Operating
Power Down
-
120
1
TBD
TBD
mA
mA
(1 kHz)
-
40
-
dB
Power Supply
Power Supply Current
Power Supply Rejection
Notes:
2. 10 kQ, 100 pF load.
DS86PP8
4-137
.-------..,-- .
_._---.-..,.
CS4225
16-Bit Audio AID Decimation Filter Characteristics
(See graphs towards the
end 01 this data sheet)
Parameter
Passband ( to -3 dB corner)
Symbol
(Fs is conversion Ireq.)
Passband Ripple
Transition Band
Min
Typ
Max
Units
0
-
0.454Fs
Hz
-
-
±O.1
dB
0.40Fs
-
0.60Fs
0.60Fs
-
Hz
Hz
75
-
-
dB
GroupDelay
-
10/Fs
-
s
Group Delay Variation vs. Frequency
-
-
0.0
Its
~
Stop Band
Stop Band Rejection
D/A Interpolation Filter Characteristics (See graphs toward the end
Parameter
Passband (to -3 dB corner)
Symbol
(Fs is conversion freq.)
Passband Ripple
Transition Band
Stop Band
Typ
Max
Units
0
-
0.476Fs
Hz
-
-
±O.1
dB
0.442Fs
-
0.567Fs
-
Hz
Hz
dB
12/Fs
-
s
-
TBD
its
~0.567Fs
Stop Band Rejection
50
Stop Band Rejection
with Ext. 2Fs RC filter
57
Group Delay
Group Delay Variation vs. Frequency
4-138
01 this data sheet)
Min
-
dB
DS86PP8
.._-_
.-_
-_.-.
_
..--__
...
CS4225
SWITCHING CHARACTERISTICS (TA = 25°C; VA+,
Parameter
VD+ = +5V, outputs loaded with 30pF)
Symbol
Min
Typ
Max
Units
SCLK period
tsckw
80
ns
SCLK high time
tsckh
25
tsckl
25
10
ns
26000
26000
kHz
kHz
-
ns
-
ns
Input Clock (XTI) low time
30
-
Input Clock (XTI) high time
30
-
SCLK low time
Input Transition Time
10% to 90% points
-
Crystals
XTI
32
32
Input Clock Frequency
LRCK, LRCKAUX
SCLK,SCLKAUX
CLKOUT duty cycle
Audio ADC's & DAC's sample rate
RST-PDN low time
-
500
-
ps
-
50
3.200
kHz
MHz
45
50
55
%
4
-
50
kHz
Fs
500
(Note 5)
MSB output from LRCK edge (Format 1 and 3)
tlrpd
-
SDOUT output from SCLK edge
tdpd
-
tdh
-
LRCK to SCLK delay (slave mode)
tlrckd
35
LRCK to SCLK setup (slave mode)
tlrcks
35
LRCK to SCLK alignment (master mode)
tmslr
-20
SDIN setup time before SCLK edge
tds
SDIN hold time after SCLK edge
Note:
ns
32
2.048
Input clock jitter tolerance
PLL clock recovery frequency
ns
-
ns
50
ns
50
ns
35
ns
35
ns
-
ns
-
ns
20
ns
5. After Powering up the CS4225, RST-PDN should be held low for 50 ms to allow the voltage
reference to settle.
LRCK
---v
LRCKAUX~
(input)
t Irckd
I1
SCLK*=
SCLKAUX*
(output)
1
C
f.- tmslr
L~~~UX-----~~_ _
(output)
I/L-
1' - - - ; , - - - - - - , - - - - - : - - - - I.
SCLK*
SCLKAUX*
(input) -"L_ _- '
'-----'IL---' ' - - -
I'
1 tsckw
DJ~~~ ---'----'~:
: ~~--~Idl~','=dS~·tl·=t=dh==I~.~'I'ltdPd
tlr
SDOUT1
SDOUT2
1
X~.--M-S-S-
~'~M-SS---1-
I
*Active edge of SCLK, SCLKAUX depends on selected format.
Audio Ports Master Mode Timing
DS86PP8
Audio Ports Slave Mode and Data 110 timing
4-139
-
_-_
.. ...-..
-.-_
..--_
__
CS4225
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA;= 25°C VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30pF)
Parameter
Symbol
Min
Max
Units
1
MHz
SPI Mode (H/S=O)
CCLK Clock Frequency
fsck
0
CS High Time Between Transmissions
tcsh
1.0
J.ls
CS Falling to SCK Edge
tcss
20
ns
tscl
500
ns
CCLK High Time
tsch
500
ns
CDIN to CCLK Rising Setup Time
tdsu
250
ns
tdh
50
CCLK Low Time
CCLK Rising to DATA Hold Time
CCLK Falling to COOUT stable
COIN (Note 9)
ns
tpd
250
ns
Rise Time of CDOUT
tr1
25
ns
Fall Time of CDOUT
tf1
25
ns
Rise Time of CCLK and COIN
tr2
100
Fall Time of CCLK and COIN
tf2
100
ns
ns
Notes:
9. Oata must be held for sufficient time to bridge the transition time of CCLK.
CS
CCLK
CDIN
CDOUT
4-140
DS86PP8
----------- -----------
CS4225
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA
= 25°C; VD+, VA+ = 5V±10%;lnputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF)
Parameter
Symbol
Min
Max
Units
fscl
0
100
kHz
Bus Free Time Between Transmissions
tbuf
4.7
!is
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
!is
Clock Low Time
tlow
4.7
!is
Clock High Time
thigh
4.0
!is
Setup Time for Repeated Start Condition
tsust
4.7
!is
thdd
0
!is
tsud
250
12 C® Mode (HIS = floating)
Note 10
SCL Clock Frequency
SDA Hold Time from SCL Falling
Note 11
SDA Setup Time to SCL Rising
ns
Rise Time of Both SDA and SCL Lines
tr
1
!is
Fall Time of Both SDA and SCL Lines
tf
300
ns
Setup Time for Stop Condition
tsusp
4.7
!is
Notes: 10. Use of the 12C® bus interface requires a license from Philips.
12C® is a registered trademark of Philips Semiconductors.
11. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
SDA
SCL
!Iow
DS86PP8
!hdd
!sud
!sus!
4-141
•
1
.'
I",
_-_...-..
_.-_..-_.......
.,,_
CS4225
ABSOLUTE MAXIMUM RATINGS (AGND,DGND = OV, all voltages with respect to OV.)
Parameter
Power Supplies:
Symbol
Min
Typ
Max
Units
VD
VA
-0.3
-0.3
-
6.0
6.0
V
V
±10,0
mA
(VA+)+0.3
V
Digital
Analog
Input Current
-
(Except Supply Pins)
Analog Input Voltage
-0.3
-0.3
Digital Input Voltage
Ambient Temperature
-55
(Power Applied)
-65
Storage Temperature
Warning:
(VD+)+0.3
V
+125
°C
+150
°C
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = OV, all voltages with
respect to OV.)
Parameter
Symbol
Min
Typ
Max
Units
Digital
Analog
VD
VA
4.6
4.6
5.0
5.0
5.4
5.4
V
V
CS4225-KL
CS4225-BL
CS4225-YU
TA
0
-40
-40
25
25
25
70
+85
+85
°C
°C
°C
Symbol
Min
Typ
Max
Units
High-level Input Voltage
VIH
(VD+)-1.0
V
VIL
-0.3
1.0
V
High-level Output Voltage at 10 = -2.0 mA
VOH
(VD+)-0.3
Low-level Output Voltage at 10 = 2.0 mA
VOL
-
-
(VD+)+0.3
Low-level Input Voltage
Power Supplies:
Operating Ambient Temperature
DIGITAL CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V)
Parameter
Input Leakage Current
Output Leakage Current
4-142
(Digital Inputs)
(High-Z Digital Outputs)
-
V
0.1
V
10
!LA
10
!LA
DS86PP8
----------------------
CS4225
Ferrite Bead
-<
+5V
Supply
26
3
To Optional
Input Buffers
+5V Analog (optional)
If a separate +5V analog supply
is available, attach here and
remove the 2.00 resistor
VA
_-----.---=2=-13 CMOUT VD
AOUTl
27
~ 0.47~F
)>-_ _-11
19
0.00221l F --r>1.8 .. F
NPO
V - ,.
AIN1L
AOUT2
1.01lF
)>-_ _-11
18
~
6000
28
1.01lF
)>-_ _-11
16
AOUT3
AIN2L
29
)>-_ _-11
v-·,.
17
AIN2R
AOUT4
1.01lF
)>-_ _-11
15
AIN3L
1.01lF
)
14
>-------11
CS4225
30
47k
~
600
0.0022 IlF --r> 1 8 .. F
NPO
1.01lF
••
~
6000
0.00221lF --r > 1.8 "F
NPO
V ,.
AIN1R
47k
47 k
~
6000
0.00221lF --r > 1.8 "F
NPO
V ,.
47 k
VREF~2~4-~---,
AIN3R
1.01lF
21
,--------1CR
22
CL
O.OlIlF
NPO --r --r 0.01 IlF
V V NPO
'"
I
1500
20
/l1----'\I\~...._=_i
4
Digital
Audio
Source
Mode
Setting
and
Hardware
Controls
SCUCCLKlIFO
SDAlCDOUT/CKFO
AD3ICSIlFl
AD2ICDINICKFl
7
9
10
8
MicroController
AINAUX
DATAUX
LRCKAUX
SCLKAUX
DIFIHOLD
RST-PDN
HIS
DEM
SDINl
SDIN2
SDOUTl
SDOUT2
43
42
1
44
Audio
41
LRCK
40
SCLK
36
CLKOUT
11
OVL
DSP
XTI
External
Clock:
Input
All unused inputs
should be tied to OV.
All NC pins should
be left floating.
Figure 1 - Recommended Connection Diagram
DS86PP8
4-143
----------------------
CS422S'
FUNCTIONAL DESCRIPTION
56pF
Overview
The CS4225 has 2 channels of I6-bit analog-todigital conversion and 4 channels of I6-bit
digital-to-analog conversion. An auxiliary I2-bit
ADC is also provided. The ADCs and the DACs
are delta-sigma type converters. The ADC inputs
have adjustable input gain, while the DAC outputs have adjustable output attenuation.
Digital audio data for the DACs and from the
ADCs is communicated over a serial port. Separate pins for input and output data are provided,
allowing concurrent writing to and reading from
the device. Control for the functions available on
the CS4225 are communicated over a serial microcontroller style interface, or may be set via
dedicated mode pins. Figure 1 shows the recommended connection diagram for the CS4225.
Analog Inputs
Line Level Inputs
A~IR,A~IL,A~2R,AJN2L,A~3R,AIN3L
and AJNAUX are the line level input pins (See
Figure 1). These pins are internally biased to the
CMOUT voltage (nominally 2.1 V). A IflF DC
blocking capacitor allows signals centered
around OV to be input. Figure 2 shows an optional dual op amp buffer which combines level
shifting with a gain of 0.5 to attenuate the, standard line level of 2Vrms to IVrms . The CMOUT
reference level is used to bias the op amps to
approximately one half the supply voltage.
Series DC blocking capacitors eliminate the con- '
tribution of signal offset to the NO converters.
The CS4225 offset calibration scheme yields
minimum DC offset values assuming that the inputs are AC coupled (DC blocking capacitor
present). If a DC blocking capacitor is not used,
a greater DC offset will occur. This offset could
be as high as ± 70 codes, with no gain.
4-144
10 k
Line In
Right
AINxR
Example
Op-Amps
CMOUT
Line In
Left
AINxL
Op-amps are run
from VA+ (+5V)
andAGND.
56 pF
Figure 2 - Optional Line Input Buffer
The input pair for the I6-bit ADCs is selected by
ISO and lSI, which are accessible in the Input
Selection Byte in software mode or dedicated
pins in the hardware mode. Antialiasing filters
follow the input mux, providing antialiasing for
the input channels. These fllters consist of internal resistors and external capacitors attached to
the CR and CL pins. The CR and CL capacitors
must be low voltage coefficient type, such as
NPO.
The analog signal is input to the I2-bit ADC via
the A~AUX pin. An anti aliasing fllter of I50n
with O.OIflF to ground is required (See Figure 1)
along with a series DC blocking capacitor. The
A~AUX signal is normally routed to the I2-bit
ADC. This signal may also be routed to the Left
I6-bit ADC (replacing the selected left input),
under control of the AIM bit in the I2-bit ADC
Mode Byte. In this mode, the input antialiasing
filters and gain adjustment operates on the
AINAUX signal.
Adjustable Input Gain
The signals from the line inputs are routed to a
programmable gain circuit which provides up to
DS86PP8
.-_
._.-.
_
..--__.._-_
...
46.5dB of gain in l.5dB steps. The gain is adjustable only by software control. Level changes
only take effect on zero crossings to minimize
audible artifacts. If there is no zero crossing,
then the requested level change will occur after a
time-out of 511 frames (lO.6ms at 48kHz frame
rate). There is a separate zero crossing detector
for each channel.
Analog Outputs
Line Level Outputs
AOUTl, AOUT2, AOUT3 and AOUT4 output a
1Vrms level for full scale, centered around
+2.1 V. Figure 1 shows the recommended 1.01lF
dc blocking capacitor with a 40kQ resistor to
ground. When driving impedances greater than
10ill, this provides a high pass corner of 20Hz.
These outputs may be muted.
Output Level AUenuator
The DAC outputs are each routed through an attenuator, which is adjustable in IdB steps.
Output attenuation is available via software control only. Level changes are implemented such
that the noise is attenuated by the same amount
as the signal (equivalent to using an analog attenuator after the signal source), until the
residual output noise is equal to the noise floor
in the mute state. Level changes only take effect
on zero crossings to minimize audible artifacts.
If there is no zero crossing, then the requested
level change will occur after a time-out of 511
frames (1O.6ms at 48kHz frame rate). There is a
separate zero crossing detector for each channel.
Each output can be independently muted via
mute control bits. In addition, the CS4225 has an
optional mute on consecutive zeros feature,
where each. DAC output will mute if it receives
512 consecutive zeros. A single non-zero value
will unmute the DAC output.
DS86PP8
CS4225
ADC and DAC Coding
The CS4225 converters use 2's complement coding. Table 1 shows the ADC and· DAC transfer
functions.
16-bit ADC/DAC
12-bitADC
2's
Input
Complement Voltage"
Code
Input!
Output
Voltage"
2's
Complement
Code
+1.400000
7FFF
7FF
+1.40000
+1.399957
7FFE
7FE
+139864
+0.000064
0001
001
+0.00204
+0.000021
0000
000
+0.00068
-0.000021
FFFF
FFF
-0.00068
-0.000064
FFFE
FFE
-0.00204
-1.399957
8001
801
-1.39864
-1.400000
8000
800
-1.40000
"Nominal voltage relative to CMOUT (Typ 2.1V), no
gain or attenuation. Actual measured voltage will be
modified by the gain error and offset error specifications.
Table 1 - ADCIDAC Input and Output Coding Table
Calibration
Both output offset voltage and input offset error
are minimized by an internal calibration cycle.
At least one calibration cycle must be invoked
after power up. A calibration will occur any time
the part comes out of reset, including the powerup reset. For the most accurate calibration, some
time must be allowed between powering up the
CS4225, or exiting the power-down state, and
initiating a calibration cycle, to allow the voltage
reference to settle. This is achieved by holding
RSTIPDN low for at least 50ms after power up
or exiting power-down mode. Input offset error
will be calibrated for all inputs and outputs.
A calibration takes 192 frames to complete,
based on the frequency of the VCO of the inter4-145
-
.._-_
_.-_..--_._.
__
...-.
nal PLL. The calibration that occurs following a
reset will proceed at a rate determined by the
free running veo in software mode (which will
be at a Fs of about 40kHz), or the selected clock
input in hardware mode.
The CS4225 can be calibrated whenever desired.
A control bit, CAL, in the Control Byte, is provided to initiate a calibration. The sequence is:
1) Set CAL to 1, the CS4225 sets CALD to 1
and begins to calibrate.
2) Wait for CALD to go to O. CALD will go to 0
when the calibration is done.
3) Set CAL to 0 for normal operation.
CS4225
Alternatively, the on-chip PLL may be used to
generate the required high frequency clock. The
PLL input clock is either 1 Fs, 32 Fs or 64 Fs
and may be input from the Auxiliary Port, (either
LRCKAUX or SCLKAUX), the DSP port,
(either LRCK or SCLK) , or from XTIIXTO. In
this last case, a 1 Fs clock may be input into
XTI, or a 1 Fs crystal attached across XTIIXTO.
The gain of the internal inverter is adjusted for
the low crystal frequency. Using a clock at 64 Fs
will result in less PLL clock jitter than a clock at
1 Fs. The PLL will lock onto a new 1 Fs clock
within 5,000 Fs periods. If the PLL input clock
is removed, the VCO will drift to the low frequency end of its frequency range.
Clock Generation
The master clock to operate the CS4225 may be
generated by using the on-chip crystal oscillator,
by using the on-chip PLL, or by using an external clock source. If the active clock source stops
for 5Jls, the CS4225 will enter a power down
state to prevent overheating. In all modes it is
desirable to have SCLK & LRCK synchronous
to the selected master clock.
Clock Source
The CS4225 requires a high frequency (256 Fs)
clock to run the internal logic. The Clock Source
bits, CSOI1l2, in the Clock Mode Byte determine
the source of the clock. A high frequency .crystal
can be attached to XTI and XTO, or a high frequency clock can be input into XTI. In both
these cases, the internal PLL is disabled, with the
VCO shut off. The externally supplied high frequency clock can be 256 Fs, 384 Fs or 512 Fs.
The CIOIl bits in the Clock Mode Byte must be
set accordingly. When using the on-chip crystal
oscillator, external loading capacitors are required (see Figure 1). lIigh frequency crystals
(> 8 MHz) should be parallel resonant, fundamental mode and designed for 20pF loading
(equivalent to 40pF to ground on each leg). An
example crystal supplier is CAL crystal
(714) 991-1580.
4-146
In software mode, bits CS2/110 in the Clock
Mode Byte establish the clock source and frequency. In Hardware mode, either LRCKAUX is
the clock reference, at 1 Fs, or the clock may be
input to XTI.
Master Clock Output
CLKOUT is a master clock output provided to
allow synchronization of external components.
Available CLKOUT frequencies of 1 Fs, 256 Fs,
384 Fs, and 512 Fs, are selectable by the coon
bits of the Clock Mode Byte. When switching
between clock sources, CLKOUT will always remain low or high for> IOns.
Synchronization
In normal operation, the DSP port and. Auxiliary
port operate synchronously to the CS4225 clock
source. It is advisable to mute the DACs when
changing from one synchronization source to another· to avoid the output of undesirable audio
signals as the CS4225 resynchronizes. If data
which is not synchronous to the clock source is
input to the CS4225, then samples will be
dropped or repeated, which will cause audible
artifacts. Under such conditions,· the CS4225
may not meet all data sheet performance specifications.
DSS6PPS·
---------------------FORMATO:
FORMAT 1:
CS4225
LRCK
I
SCLK
~::
SDIN
_ _-LrMSBI.-".M=SB= : : : :L.=[Lss::,,-sB"-L1_ _ _[MSB[LeM""S=B : : : :,-"[LSaJ:"-SB:::...L_ _ _L-'-[MSB], , S=B
LRCK
~
SCLK
~-:_~-:_~-:_~-:_IL
~
LRCK
FORMAT 3:
Right
L I_ _ _
Jl-_ -~~ : : Jl-_ -~--U-U-
I
Left
_I,-"M"",S","BI~-,------,I : : [LSB]
So'lN
FORMAT 2:
1
Left
III
: : [LSB]
1MSBI
I
Left
I
Right
Right
I
_- : _- : : JL
SCLK
JLf--:-:::0: _- _- _- _- _- JlF- __-: I
LRCK
~_-_-_-_-_L~~-_-_-_-_-~_-_-_-_R!g~i_-_-_-_-_-~
SCLK
~-:_~-:_~-:_~-:_IL
I MSBI
SDIN
Figure 3 - Audio DSP and Auxiliary Port Data Input Formats.
LRCK
FORMATO
FORMAT 1
I
I
Left
SCLK
~::ST_-_~::ST_-_~
B _- _- _- _-c..:[LSBJ=SB::....L_ _--.J[MSBJc.:;M:=SB::.J _- _- _- JL.:LsBlL=SB::....L_ _--.J[MSBJ-'.:M:=SB::.J
_ _.L;[MSBJ=S=.J
I
I
LRCK
~
SCLK
~-:_IL-:_r1ILn._:-:_IL-:_1L
LRCK
SCLK
SDOUT
FORMAT 3
'---
SDOUT
Left
Right
I : : [LSBJ
SDOUT
FORMAT 2
I
Right
~
Left
1
Right
I
~-_ -_LJ~-_-_-_-_-_~-_-_-_-_-_S~-_-_-_-_-_JL
c..:[LSBJ=SB"-'-_ _-'[MSBJ~M~SB:'J. -_ -___ -_ JLsBlL.:L:::::SB::....L_ _ _--L[MSB].:.:.:M=SB:..L -_ -_ -_ -_ -_
~
: : : _~e~: : : : :~ : : :Righ( : : : : :~
LRCK
~:
SCLK
~-:_IL-:_r1ILn._:-:_IL-:_1L
SDOUT
Figure 4 - Audio DSP Port Data Output Formats.
DS86PP8
4-147
.._-_
...-..
.-_
_
..--_
__
LRCK
CS4225
~~----------------------------------------------------------~
Jlj-
SDIN1
~- - _ 1 LSB 1 MSB 1- __- 1 LSB 1 MSB 1- _- _- 1 LSB 1 MSB 1- _- _- 1 LSB 1 MSB
SDOUT1
~_ILf1j-~,
1Lf1j-
nsu-
SCLK
~_
~ D~C#1~ DAC#2~ DAC#3~
~- _- _-I LSB 1 MSBI- __-I LSB 1 MSBI_ -,
~ Left ADC---J.- Right ADC
.1.
.1.
0
~_ ~
DAC#4--J
[MSij_ -,
.1.
0
.1.
[MSF
.1
AUX ADC 4 0'5 AUX ADC 4 0'5
12-Bits
12-Bits
Figure 5 " One data line mode (Format 4)
Digital Interfaces
There are 3 digital interface ports: the audio DSP
port, the auxiliary digital audio p~rt and the control port. In hardware mode (HIS pin high) the
control port is disabled, and various modes can
be set via pins. In hardware mode, control of the
input gain, output level and some modes are not
possible.
Audio DSP Serial Interface Signals
The serial interface clock, SCLK, is used for
transmitting and receiving audio data. SCLK can
be generated by the CS4225 (master mode) or it
can be input from an external SCLK source
(slave mode). The number of SCLK cycles in
one system sample period is programmable to be
32, 48, or 64. When SCLK is an input, 32
SCLK's per system sample period is not recommended, due to potential interference effects; 64
SCLK's per sample period should be used instead.
The LeftlRight clock (LRCK) is used to indicate
left and right data, also the start of a new sample
period. It may be output from the CS4225, or it
may be generated from an external controller.
The frequency of LRCK is equal to the system
sample rate, Fs.
SDINI and SDIN2 are the data input pins, each
of which drives a pair of DACs. SDINI left data
is for DAC #1, SDINI right data is for DAC #2,
SDIN2 left data is for DAC #3, and SDIN2 right
4-148
data is for DAC #4. SDOUTl carries the data
from the 2 16-bit ADCs. SDOUT2 carries the
data from the 12-bit ADC. The audio DSP port
may also be configured so that all 4 DAC's data
is input on SDIN1, and all 3 ADC's data is output on SDOUT 1.
Audio DSP Serial Interface Formats
The audio DSP port supports 5 alternate formats,
shown in Figures 3, 4, and 5. These formats are
chosen through the DSP Port Mode Byte in software mode. In hardware mode, four formats are
available as selected by the DIF and IFO pins.
The 12-bit ADC data format is similar to the 16bit data format. The 12-bit data is positioned to
the most significant end of a 16-bit field, with
the lower 4 bits set to zero. The resulting 16-bit
value is output on SDOUT2 in both the left and
right channel positions. The format will be the
same as the selected SDOUTl format.
Figure 5 shows the timing for format 4, where
all 4 DAC data words are presented on SDIN1,
and the 3 ADC data words are presented on
SDOUTI.
Format 5 is a combination mode. The data output is as in Format 1, on the SDOUTI and
SDOUT2pins. The data input is as in Format 4
on SDINI. In both format 4 and 5, LRCK duty
cycle is 50% if it is an output.
DS86PP8
----------------------
CS4225
CS ~L.~__________________~!l~,
CCLK
~fVI.1l:t
CHIP
ADDRESS
COIN
_____________________r-
MAP
CHIP
ADDRESr-S---.--_ _ _ _ _ _ _ __
DATA
J OH[ADt[ADO\RiNr-~ 0, ~Rh.AL_________
byte 1-
;1
-byte n
CDOUT--------------------4~
High Z
MAP =Memory Address Pointer
Figure 6 - Control Port Timing, SPI mode
Auxiliary Audio Port Signals
Control Port Signals
The auxiliary port provides an alternate way to
input digital audio signals into the CS4225, and
allows the CS4225 to synchronize the system to
an external digital audio source. This port consists of clock, data and left/right clock pins
named, SCLKAUX, DATAAUX and
LRCKAUX. These signals are fed through to the
SCLK, SDOUTl and LRCK pins. There is a two
frame delay from DATAAUX to SDOUTl.
When the auxiliary port is used, the frequency of
LRCKAUX must equal to the system sample
rate, Fs, but no particular phase relationship is
required.
The control port has 2 modes: SPI and I2C®,
with the CS4225 as a slave device. The SPI
mode is selected by setting the His pin low.
I2C® mode is selected by floating the HIS pin.
If the HIS pin is floated, add a O.l/-!F capacitor
to ground on the HIS pin to minimize noise
pickup.
Auxiliary Audio Port Formats
Input data on DATAAUX is clocked into the part
by SCLKAUX using the format selected in the
Auxiliary Port Mode Byte. In hardware mode,
the auxiliary port format is the same as the DSP
port format and is determined by the DIF pin.
The auxiliary audio port supports the same 4 formats as the audio DSP port in 2 data line mode.
LRCKAUX is used to indicate left and right data
samples, and the start of a new sample period.
SCLKAUX and LRCKAUX may be output from
the CS4225, or they may be generated from an
external source, as set by the AMS control bit in
Software mode or IFI in Hardware mode.
DS86PP8
SPI Mode
In SPI mode, CS is the CS4225 chip select signal, CCLK is the control port bit clock, (input
into the CS4225 from the microcontroUer),
CDIN is the input data line from the microcontroller, CDOUT is the output data line to the
microcontroller, and ADO and ADI form the
chip address.
The pins ADO, ADI must be tied to one of 4
possible chip addresses. To write to a particular
CS4225, the ADO, ADI bits must match the state
of the ADO, ADI pins for that chip. This allows
up to 4 CS4225 devices to co-exist on one control port bus.
Figure 6 shows the operation of the control port
in SPI mode. To write to a register, bring CS
low. The first 5 bits on CDIN must be zero. The
next 2 bits form the chip address. The eighth bit
is a read/write indicator (RIW), which should be
4-149
.._-_
_.-_.. .......
...-..
..,.-,_
CS4225
..-- Note 1
SDA
SCL
fI-001
..-- Note 2
II~f~lf~
RiW ACK DATA ACK DATA ACK If:
~
I II
-f!\ rlr.., rll"
I
ADDR
AD3-0 II
I~U U
1-8
f
n n ,-If" n
U U U
1-8
U U
II
11_
,-II~
U
n
III
U lJ
Start
Stop
Note 1: The first 3 address bits for the CS4225 must be 001.
Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 7 - Control Port Timing, I 2C® Mode
low to write. The next 8 bits form the Memory
Address Pointer (MAP), which is set to the address of the register that is to be updated. The
next 8 bits are the data which'will be placed into
register designated by the MAP. During writes,
the CDOUT output stays in the Hi-Z state. It
may be externally pulled high or low with a
47kQ resistor_
The CS4225 has a MAP auto increment capability, enabled by the INCR bit in the MAP register.
If INCR is a zero, then the MAP will stay constant for successive reads or writes. If INCR is
set to a l, then MAP will auto increment after
each byte is read or written, allowing block
reads or writes of successive registers.
To read a register, the MAP has to be set to the
correct address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The auto MAP increment bit (INCR)
may b~et or not, as desired. To begin a read,
bring CS low, send out the chip address and set
the read/write bit (R/W) high. The next falling
edge of CCLK will clock out the MSB of the
addressed r~gister (CDOUT will leave the high
impedance state). If the MAP auto increment bit
is set to l, the data for successive registers will
appear consecutively.
clock, SCL, with the clock to data relationship as
shown in Figure 7. There is no CS pin. Pins
ADO, ADl, AD2, AD3 form the chip address.
The upper 3 bits of the 7 bit address. field must
be 001. To communicate with a CS4225, the
LSBs of the chip address field, which is the first
byte sent to the CS4225, should match the settings of the ADO, ADl, AD2, AD3 pins. The
eighth bit of the address bit is the R/W bit (high
for a read, low for a write). If the operation is a
write, the next byte is the Memory Address
Pointer. which selects the register to be read or
written. If the operation is a read, the contents of
the register pointed to by the Memory Address
Pointer will be output. Setting the auto increment bit in MAP, allows successive reads or
writes of consecutive registers. Each byte is
separated by an acknowledge bit. Use of the I2C
bus®com~atibie interface requires a license from
Philips. I C bus® is a regis.tered trademark of
Philips Semiconductors.
Control Port Bit Definitions
All registers Can be written and read back, except the status report byte, which is read only.
See the following bit definition tables for bit assignment information.
In I2C® mode, SDA is a bidirectional data line.
Data is clocked into and out of the part by the
4-150
DS86PP8
----------------------
CS4225
Auxiliary Port Mode Byte (7)
Memory Address Pointer (MAP)
87
IINCR
86
85
o
10
84
83
82
81
80
0 I MAP3 MAP2 MAP1 MAPol
87
I 0
86
85
o
0
84
83
82
81
80
lAMS IACK1 ACKO IADF1 ADFOI
ADF1 - ADFO
Sets Digital Interface Format
o - Format 0 - 12S
1 - Format 1
2 - Format 2
3 - Format 3
ACK1 - ACKO Sets number of bit clocks per Fs period
0-64
1 - 48 - gated 64Fs
2 - 32 - gated 64Fs
3 - 32 - continuous
AMS
AUX Master ISlave control bit
o - port is master (SCLKAUX and
LRCKAUX are outputs).
1 - port is slave (SCLKAUX and
LRCKAUX are inputs).
MAP3-MAPO
Register Function
o - Reserved
1 - Output Attenuator 1
2 - Output Attenuator 2
3 - Output Attenuator 3
4 - Output Attenuator 4
5 - Input Gain 1
6 - Input Gain 2
7 - Auxiliary Port Mode
8 - DSP Port Mode
9 - Clock Mode
10 - Control Byte
11 - Status Report Byte
12 - Input Channel Select
13 - Aux Control Byte
14 - Reserved
15 - Reserved
Auto Increment Control Bit
o - No auto increment
1 - Auto increment on
INCR
DSP Port Mode Byte (8)
87
0
I
Output Attenuator Data Byte (1, 2, 3, 4)
87
86
85
84
83
82
81
80
o I ATT6 ATT5· ATT4 ATT3 ATT2 ATT1 ATTOI
ATT6 to
ATTO
Sets Attenuator Level
o - No attenuation
127 - 127 dB attenuation
ATTO represents 1.00 dB
Input Gain Setting Data Byte (5, 6)
87
0
I
GN4 to
GNO
86
85
0
0
DS86PP8
84
I GN4
83
82
GN3 GN2
Sets Input Gain
0- No gain
31 - 46.5 dB gain
GNO represents 1.5 dB
81
80
GN1
GNOI
86
o
85
84
83
82
81
80
I DMS I DCK1 DCKOI DDF2 DDF1 DDFOI
DDF2 - DDFO Sets Digital Interface Format
o - Format 0 - 12S
1 - Format 1
2 - Format 2
3 - Format 3
4 - One data pin in, One data pin out
mode (Format 4).
5 - Output is Format 1 on SDOUT1
and SDOUT2, input is Format 4
on SDIN1.
DCK1 - DCKO Set number of bit clocks per Fs period
0-64
1 - 48 - gated 64 Fs
2 - 32 - gated 64 Fs
3 - 32 - continuous
DSP Master ISlave control bit
DMS
o - port is master (SLCK and LRCK
are outputs).
1 - port is slave (SLCK and LRCK
are inputs).
4-151
-------_.
..-... -----------
CS4225
Clock Mode Byte (9)
I
B7
B6
0
Ico1
B5
Status Report Byte (11)
B4
COO I CI1
B3
B2
CIO I CS2
B1
BO
CS1
csol
CS 1 - CSO Sets the source of the master clock
which runs the CS4225.
o - Crystal Oscillator or XTI (PLL Disabled)
1 - PLL driven by LRCKAUX at 1 Fs
2 - PLL driven by LRCK at 1 Fs
3 - PLL driven by XTIIXTO (XTI at 1 Fs)
4 - PLL driven by SCLK at 32 Fs
5 - PLL driven by SCLK at 64 Fs
6 - PLL driven by SCLKAUX at 32 Fs
7 - PLL driven by SCLKAUX at 64 Fs
CI1 - CIO
Determines frequency of XTI
when PLL is disabled.
0- 256 Fs
1 - 384 Fs
2 -512 Fs
3 - Reserved
C01-COO Determines CLKOUT frequency
0-256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs
B7
B6
B6
B5
B4
.B3
B2
B1
B4
B3
B2
B1
BO
ILocKlcALD I 01
16 - bit ADC overload bits.
00 - Normal ADC input levels
01 - -6 dB level
10 - -3 dB level
11 - Clipping
Indicates one of the ADC's has been
overdriven. These bits are "sticky".
They will stay set until read, when they
will return to 00 if the overload is no
longer present.
12-bit ADC overload bit
o - normal input
1 - clipped input
This bit is also "sticky"
Control port data check bit
0- Multiple of 8 clocks received
last word (SPI Mode)
1 - Error, not multiple of 8 clocks received.
PLL lock indicator
o - PLL not locked. If PLL is selected,
DAC outputs will mute
1 - PLL locked
o - Calibration done
1 - Calibration in progress
OVL1 to
OVLO
OV12
ACK
LOCK
Control Byte (10)
B7
B5
lovu OVLolov12 lACK I 0
BO
IMUTclcALI DEMCIDEMI MUT4 MUT3 MUT2 MUT11
MUT4 to
MUT1
DEM
DEMC
CAL
MUTC
4-152
Mute Control Bits
o - Normal Output Level
1 - Selected DAC output muted
Selects De-Emphasis
o - Normal Flat DAC frequency response
1 - CD De-Emphasis Selected
Selects De-Emphasis Control Source
o - De-emphasis is controlled by DEM
pin. DEM bit is ignored.
1 - De-emphasis is controlled by DEM bit.
DEM pin is ignored.
o - Normal Operation
1 - Initiate Calibration
Controls mute on consecutive zeros
function
0- 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros.
Input Selection Byte (12)
B7
I
0
B6
B5
B4
B3
B2
B1
0
0
0
0
0
IS1
IS1 - ISO
Select input channel
o - Select AIN1
1 - Select AIN2
2 - Select AIN3
3 - Select Auxiliary Digital Input Port
Aux Control Byte (13)
B7
B6
I AIM 1 0
AIM
B5
B4
B3
B2
B1
BO
0
0
0
0
0
01
Auxiliary Input Mode Control Bit
0- AINAUX signal is routed to 12-bit ADC
1 - AINAUX routed to AINL of 16-bit ADC
DS86PP8
-____-_
.. ...-.
-. ..--_._.
CS4225
Reset
De-Emphasis
RST-PDN going low causes all the internal control registers, used in software mode, to be set to
the states indicated in Table 1. The reset states
are different for hardware mode, see the section
on Hardware Mode. RST -PDN must be brought
low and high at least once after power up. RSTPDN returning high causes the CS4225 to
execute an offset calibration cycle. RST-PDN returning high should occur at least SOms after the
power supply has stabilized.
Figure 8 shows the de-emphasis curve. De-emphasis may be enabled under hardware control,
using the DEM pin, or by software control using
the DEM bit. In software mode, either hardware
or software control of de-emphasis may be selected.
Power Down Mode
Placing the RST-PDN pin into a high impedance
state (floating) puts the CS4225 into the power
down mode. This may be done by driving the
RST-PDN pin with a three-state buffer, and setting the buffer to the hi-z state. In power-down
mode CMOUT and VREF will not supply curATT6 ~ATTO
GN4 ~ GNO
ADF1, ADFO
ACK1,ACKO
AMS
DDF2 ~ DDFO
DCK1, DCK1
DMS
MAP
CAL
= 127
=0
=0
=0
= 1
=0
=0
= 1
=0
=0
CS2, CS1,CSO
C11, CIO
C01, COO
MUT4 ~MUT1
DEM
DEMC
MUTC
IS1, ISO
AIM
=3
=0
=0
= 1111
=0
=0
=0
=0
=0
Table 1 - Reset State (Software Mode)
rent. If the master clock source stops, the
CS4225 will power down after 5f..Ls. Power down
will change all the control registers to the reset
state shown in Table 1.
The de-emphasis corner frequencies are as
shown in Figure 8 for a sample rate of 44. 1kHz.
Selection of de-emphasis at other sample rates
will cause the filter to be applied, but with corner frequencies scaled proportionally to the
sample rate.
Hold Function (Software Mode only)
If the digital audio source has an invalid data
output pin, then the CS4225 may be configured
to cause the last valid analog output level to be
held constant. (This sounds much better than a
potentially random output level.) HOLD is sampled on the active edge of SCLK. If HOLD is
driven high any time during the stereo sample
period, both pairs of DAC's hold their current
output level, and reject the data currently being
input. SDIN input data is ignored while the
HOLD pin is high. For normal operation, the
HOLD pin must be low.
Gain
dB
(0.072 Fs)
T1=50us'
OdB
(0.241 Fs)
T2 = 15us'
After returning to normal operation from power
down, an offset calibration cycle must be executed. To leave the power-down state, pull
RST-PDN low for at least 50ms to allow the internal voltage reference time to settle, then high
to initiate an offset calibration cycle.
-10dB
- - - - - - - - - - - - - - - -'>,------
F1
F2
Frequency
• with Fs = 44.1 kHz
Figure 8 - De-emphasis Curve.
DS86PP8
4-153
.-_
_
..--_._.
__.._-_
...-.
CS422S
Hardware Mode
Hardware mode is selected by connecting the
His pin to YD. In hardware mode, only certain
functions are available:
- de-emphasis,
- digital interface formats 0, I and 2, and DSP
format 4,
- auxiliary audio port master/slave selection,
- CLKOUT and XTI frequencies are restricted,
- use of PLL is tied to master/slave selection,
- the PLL locks to LRCKAUX only,
- will mute on consecutive zeros.
In addition, the input gain is set to OdB (no
gain), and the attenuator is set to OdB (no attenuation). The DAC mute bits are set to 0 (not
muted). The DSP port and Auxiliary port serial
clocks are set to 64 bits per Fs period.
In hardware mode, the DSP port is always in
slave mode. The IFI pin selects the Auxiliary
port to. be master or slave (low for master, high
for" slave). When the Auxiliary port is a master,
XTI is the clock source and the PLL is off.
CKFO and CKFI pins define both XTI and
CLKOUT frequencies as follows:
CKFI
CKFO
XTI
CLKOUT
o
o
o
256 Fs
384 Fs
512 Fs
512 Fs
256 Fs
256 Fs
256 Fs
512 Fs
1
1
1
o
Functions .o.nbc available in software mode include:
- input gain adjust & output level adjust,
- digital interface format 3, DSP format 5,
- more clocking flexibility,
- DAC muting,
- setting of number of bit clocks per Fs period,
- tum off mute upon consecutive zeros function,
- 12-bit ADC clipping indicator,
- PLL lock flag,
- routing the AINAUX signal to a 16-bit ADC,
- hold last sample on error.
Power Supply and Grounding
The CS4225, along with associated analog circuitry, should be positioned near to the edge of
your circuit board, and have its own, separate,
ground plane (see Figure 9). Preferably, it should
also have its own power plane. The +5V supply
must be connected to the CS4225 via a ferrite
bead, positioned closer than 1" to the device. A
single connection between the CS4225 ground
and the board ground should be positioned as
shown in Figure 9. Figure 10 shows the recommended decoupling capacitor layout. Also see
Crystal's layout Applications Note, and the
CDB4225 evaluation board data sheet for recommended layout of the decoupling components.
The CS4225 will mute the analog outputs if the
supply drops below approximately 4 volts.
ADC and DAC Filter Response Plots
When the Auxiliary port is a slave, LRCKAUX
is the clock source at 1 Fs, the PLL is enabled.
CKFI and CKFO determine CLKOUT as follows:
CKFI
CKFO
CLKOUT
o
o
o
256 Fs
384 Fs
512 Fs
1 Fs
1
o
1
4-154
Figures 11 through 18 show the overall frequency response, passband ripple and transition
band for the CS4225 ADC's and DAC's. Figure
17 shows the DAC's deviation from linear phase.
The 12-bit ADC output is fully decimated to Fs,
but is not filtered. Figure 18 shows the noise
floor of the output, along with a low frequency
full scale signal. External digital filtering is necessary to achieve the desired trade off between
measurement bandwidth and dynamic range.
DS86PP8
--------
~==~ 1=;'
CS4225
21/8"
Digital
Ground
Plane
11
Note that the CS4225
is oriented with its
digital pins towards the
digital end of the board .
AnalOg
Gi'Oflifd
+5V
Ferrite
fisrle·
Bead
.f
Ground Connection
r...1~S42251
-
I-I
.
.1' .
.I
1
I
CPU & Digital
Logic
Codec
digital
signals
Codec
analog
signals &
components
Figure 9. Suggested Layout Guideline
Digital
Supply
Digital
Supply
0.1
°
( 0
(~ 5
1c:::::J
1c:::::J
I c:::::J
I c:::::J
I c:::::J
I c:::::J
1c:::::J
1c:::::J
c:::::J
1c:::::J
I c:::::J
1c:::::J
1c:::::J
I c:::::J
I c:::::J
I c:::::J
I c:::::J
1c:::::J
1c:::::J
c:::::J
1c:::::J
I c:::::J
~-
DOD 5IT 00- - -.
:__D_DjJ] ~ 0
Figure 10. Recommended Decoupling Capacitor Layout
DS86PP8
4-155
.._-_
.-.....
_
..-__
..._.-.
CS4225
-1
-1
-'
-2
-2
iii' -3
:g. -4
iii'
:g.
,-
CD
"C
CD
"C
~
c:
~
:::E
'-
:Ec:
'"
tU
:::E
,-
-,
-'
0.0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
Input Frequency (Fs)
0.8
0.9
1.0
0.0
0.2
0.2
0.1
0.1
-0.0
-0.0
-0.1
-0.1
~
-0.2
~
"
-0.3
"0
,E -0.3
"0
C
-
~ -0.4
1.0
-0.2
~ -0.4
-0.5
-0.5
-0.6
-0.6
-0.7
-0.7
-0.8
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 12. 16~bit ADC Passband Ripple.
Figure 15. DAC Passband Ripple.
0
0
-10
-10
-20
-20
-30
-
-30
iii'
iii' -40
:2- -40
:2-
"0
"
.-2c -50
-50
.
-60
Cl
::;;
::;; -70
-60
-70
':
-80
-90
0.9
C
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
5l'
0.8
::;;
-0.8
"0
0.3 0.4 0.5 0.6 0.7
Input Frequency (Fs)
"
::;;
:E"c
0.2
Figure 14. DAC Frequency Response.
Figure 11. 16-bU ADC Filter Response.
::>
.t<
0.1
"
-100
-80
-90
-100
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (Fs)
Figure 13. 16-bit ADC Transition Band.
4-156
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 16. DAC Transition Band.
DS86PP8
----------------------
CS4225
2.5
2.0
1.5
1.0
""
~
0.5
~
-0.0
""'
1!
Q.
-0.5
C>
\
-,-
-1.0
-1.5
-
-2.0
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 17. DAC Phase Response.
0.00
-15.00
-30.00
-45.00
iii" -60.00
~
"
"
~
-75.00
C>
-90.00
:ll1 -105.00
-120.00
-135.00
-150.00 +-'-+---+--+--+--+---+--+--+--+-----1
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 18. 12-bit ADC Noise with a Low Frequency
Full Scale Sine wave input sigual.
DS86PP8
4-157
.._-_
_.-_..---._.
__
...-.
CS4225
PIN DESCRIPTIONS
SDOUT1
DGND
SDOUT2
£f~~~
~:HI{S~~
~~~6 ~
SCl
CCCDllK
N
AD2
SDA CDOUT
AD3
CS
AD1
ADO
IF0
CKF1
4
""\\
CKFO ~ \
IF1
OVl ---.......
IS1 ISO ------/
AIN3R
~
AD1
ADO
-/>
AIN3l -2;
2
~
? 44
42
; ; - DIF
40
/
31
; : : ClKOUT
...---- XTO
XTI
"---- RST-PDN
"'\'----- FllT
9
-
~;:W
14
15
:II::~ ~-5~'---r-r-r
~18
HOLD
r- DEM
39
\\=:
AGND2
24""TTT"TT~2~6
&rrr-----'2~
\= :~~~:
20
""TTT"TT2TTTTTT2
AIN1 R ---------/'
AIN1l
AINAUX
CR
Cl
" ------- AOUT2
AOUT1
VA
..
AGND1
VREF
CMOUT
Power Supply
VA - Analog Power Input
+5 V analog supply.
AGNDl, AGND2 - Analog Ground
Analog grounds.
VD - Digital Power Input
+ 5 V digital supply.
DGND - Digital Ground
Digital ground.
Analog Inputs
AINIL, AINIR - Left and Right Channel Mux Input 1
Analog signal input connections for the right and left channels for multiplexer input 1.
4-158
DS86PP8
-_
.. _------------------
CS4225
AIN2L, AIN2R • Left and Right Channel Mux Input 2
Analog signal input connections for the right and left channels for multiplexer input 2.
AIN3L, AIN3R • Left and Right Channel Mux Input 3
Analog signal input connections for the right and left channels for multiplexer input 3.
AINAUX • Auxiliary Line Level Input
Analog signal input for the 12-bit ND converter. In software mode, setting the AIM bit causes
AINAUX to replace the left analog input at the multiplexer input.
Analog Outputs
AOUT1, AOUT2, AOUT3, AOUT4 • Audio Outputs
The analog outputs from the 4 DIA converters. Each output can be independently controlled for
output amplitude.
CMOUT • Common Mode Output
This common mode voltage output may be used for level shifting when DC coupling is desired.
The load on CMOUT must be DC only, with an impedance of not less than 25kQ. CMOUT
should be bypassed with a 0.47JlF to AGND.
VREF • Voltage Reference Output, Pin 21
The on-chip generated ADCIDAC reference voltage is brought out to this pin for decoupling
purposes. This output must be bypassed with a lO/lF capacitor in parallel with a O.I/lF
capacitor to the adjacent AGND pin. No other external load may be connected to this output.
Digital Interface Signals
SDINI • Serial Data Input 1
Digital audio data for the DACs 1 and 2 is presented to the CS4225 on this pin.
SDIN2 • Serial Data Input 2
Digital audio data for the DACs 3 and 4 is presented to the CS4225 on this pin.
SDOUT!· Serial Data Output 1
Digital audio data from the 16-bit audio ADCs is output from this pin. When selected,
DATAAUX is output on SDOUTI.
.
SDOUT2 • Serial Data Output 2
Digital audio data from the 12-bit audio ADC is output from this pin.
SCLK • DSP Serial Port Clock 110
SCLK clocks digital audio data into the DACs via SDIN1I2, and clocks data out of the ADCs
on SDOUT1I2. Active clock edge depends on the selected format.
DS86PP8
4·159
_J
--------..,------.-------
CS4225
LRCK - Left/Right Select Signal I/O
The LeftlRight select signal. This signal has a frequency equal to the sample rate. The
relationship of LRCK to the left and right channel data depends on the selected format.
RST -PDN - Reset and Power-Down Input
The CS4225 must be reset after power up by bringing this pin low, then high. To select power
down mode, float this pin, or drive this pin with a three-state buffer, and place the buffer in the
Hii-Z state. Low-to-highrise time should be less than 1O/JS.
DEM - De-emphasis Control
When high, DEM causes the standard Compact Disk de-emphasis frequency response for Fs =
44. 1kHz to be applied to the DACs. If HIS is high, this pin is active. If HIS is low, then this pin
is enabled by setting the DEMC control bit to 0, and disabled by setting the DEMC control bit
to 1.
HOLDIDIF - Digital Interface Format Select Pin 11I0LD Control
In software mode, when HOLD is high any time during the sample period, SDINI and SDIN2
data is ignored, and the previous "good" sample is presented to the DACs.
In hardware mode, DIF becomes a selection pin which selects audio data lIO formats 0, 1 and 2
(when IFO is low) using a 3-leve1 selection. Low selects format o. High selects format 1.
Floating selects format 2. Float DIF by tying a 0.01J.IF capacitor from DIF to ground. In
hardware mode, both the auxiliary audio data port and the audio DSP port are set to the same
audio format.
SCUCCLKlIFO - Serial Control Interface Clock I DSP Interface Mode Select.
In software control mode, SCUCCLK is the serial control interface clock, and is used to clock
control bits into and out of the CS4225.
In hardware control mode, when IFO is low, the data for DACs 1 and 2 is input on SDINl, and
for DACs 3 and 4 is input on SDIN2. The data from the audio ADCs is presented on SDOUTl
and the data from the l2-bit auxiliary ADC is presented on SDOUT2. In hardware control
mode, when IFO is high, the data for all 4 DACs is input on the SDINI pin, and the data from
the audio ADCs l!1ld the 12-bit auxiliary ADC is output on the SDOUTI pin. This mode allows
a DSP which has only 1 serial input and 1 serial output port to access all the DACs and ADCs.
AD3/CSIlFl - Control Port Chip Select I Interface Control
In I2C® software control mode, AD3 is a chip address bit. In SPI software control mode, CS is
used to enable the control port interface on the CS4225.
In hardware control mode, IFl low sets the auxiliary digital audio input port to be master and
IFI high sets the auxiliary digital audio input port to be slave. In slave mode, the PLL is used
to generate the internal 256 Fs clock from LRCKAUX, and to generate CLKOUT.
AD2ICDIN/CKFl - Serial Control Data In I Interface Control
In I2C® mode, AD2 is a chip address bit. In SPI software control mode, CDIN is the input data
line for the control port interface.
In hardware control mode, CKFO and CKFI controls the clock frequency of CLKOUT.
4-160
DS86PP8
----------- -----------
CS4225
SDAlCDOUT/CKFO - Serial Control Data Out I Clock Select
In I2C® mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the
output data from the control port interface on the CS4225.
In hardware control mode, CKFO and CKFI controls the clock frequency of CLKOUT.
DATAUX - Auxiliary Data Input
DATAUX is the auxiliary audio data input line, usually connected to an external digital audio
source.
LRCKAUX - Auxiliary Word Clock Input or Output
In auxiliary slave mode, LRCKAUX is a word clock (at Fs) from an external digital audio
source. LRCKAUX can be used as the clock reference for the internal PLL. In auxiliary master
mode, LRCKAUX is a word clock output (at Fs) to clock an external digital audio source.
SCLKAUX - Auxiliary Bit Clock Input or Output
In auxiliary slave mode, SCLKAUX is the serial data bit clock from an external digital audio
source, used to clock in data on DATAAUX. SCLKAUX can be used as the clock reference for
the internal PLL. In auxiliary master mode, SCLKAUX is a serial data bit clock output.
ADO/ISO, ADlJISl - Input Select Control Pins
In software mode, these pins are part of the chip address.
In hardware mode, ISO and IS 1 select the audio input source from between 4 pairs of signals
(AINI, AIN2 and AIN3) and DATAUX.
HIS - Hardware or Software Control
Setting HIS high puts the CS4225 into hardware control mode, where many functions are
controlled by dedicated pins. When HIS is low, many chip functions are controlled via the
control port in SPI mode. When HIS is open circuit, then software mode I2C® protocol is
selected for the control port. When floating HIS, a lOOpF capacitor should be connected from
the HIS pin to ground, to reduce the possibility of external interference influencing the pin.
OVL - Overload Indicator
If either of the 2 16-bit audio ADCs, or the 12-bit ADC, is clipped, then this pin goes high.
Clock and Crystal Pins
XTI, XTO - Crystal connections
Input and output connections for the crystal which may be used to operate the CS4225.
Alternatively, a clock may be input into XTI.
CLKOUT - Master Clock Output
CLKOUT allows external circuits to be synchronized to the CS4225. Alternate output
frequencies are selectable by the control port or via hardware pins.
DS86PP8
4-161
.'
----------------
-.r _ _ - __
" CS422,5
Miscellaneous Pins
FILT - PLL Loop Filter Pin
A 0.22 ~ capacitor should be connected from FILT to AGND.
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal codewidth; expressed in LSBs.
Total Dynamic Range
The ratio between the DAC full scale output and the noise floor with the DAC muted. Units are
in dB.
'
Total Harmonic Distortion + Noise (THD+N)
THD+N is the ratio of the rms value of the input signal to the rms sum of all other spectral
components within: the measurement bandwidth (10Hz to 20kHz). THD+N is expressed in dB.
Total Harmonic Distortion (THD) "
"
THD is the ratio of the test signal amplitude to the 'rms sum of all the in-band harmonics of the
~~
,
Instantaneous Dynamic Range
The S/(N+D) with a 1kHz, -60dB input signal, with 60dB added to compensate for the small
input signal. Use of a small input signal reduces the harmonic distortion components of the
noise to insignificance. Units are in dB.
Interchannel isolation
The amount of 1kHz signal present on the output of the grounded i,nput channel with 1kHz,
OdB signal present on the other channel. Units are in dB. '
,
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in dB.
Frequency Response
Worst case variation in output signal level versus frequency over 10Hz to 20kHz. Units in dB.
Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input
grounded. For the DAC's, the deviation of the output from zero with mid-scale input code.
Units are in volts.
4-162
DS86PP8
...............
....
.
.
.
~
I CDB4225I
.,~
~-- .~
Semiconductor Corporation
CDB4225 Evaluation Board
General Description
Features
• CS4225 - Quad DAC, Stereo ADC
• CS8425 Digital Audio Transceiver
• Input Data from Either Audio Processor or
via Optical IEC-958 Compatible Digital
Audio Transceiver
• Output Data to Serial Interface Port or via
Digital Audio Transceiver
• Serial Control Port for Software Control of
both CS4225 and CS8425. Supports 12 C
and SPI
• Board is Also Hardware Controllable
The CDB4225 is useful for evaluating the performance
of both the CS4225 and the CS8425. Audio data can
be input to and output from the CS4225 via a serial
port which connects to an audio data processor. Alternatively, the CS8425 can serve as the audio data
interface, supporting the "consumer" interface over fiber optics.
The board can be configured and controlled by either a
peripheral serial control port, or by stand alone hardware interface. The peripheral control options are SPI
and 12C. PC software which supports the board's SPI
interface is available, and can be used to set the internal control registers of the CS4225 and CS8425.
ORDERING INFORMATION
CDB4225
DSP
RBEROPTfC
CONTROL
PORT
HDW
AIN2L
CS4225
AUDIO DATA
CS8425
DIGITAL
QUADDAC
AIN2R
AUDIO
STEREOA/O
TRANSCENER
HOW
AIN1 L
-if--Jv'V'v---'-I
AINAUX
-iLAJ\A~
CONTROL
1~~DACOUT1
CAC OUT2
CAC OUT3
DACOUT4
Preliminary Product Information IThis ,document contains infor~ation for a. new. product. Crystal
.
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
AUG '93
DS86DB1
4-163
-
_.-_..--__.._-_
...
.-..-.
• Notes •
4-164
..
....
.
.. ...
~~
~
• ." .... ~.
~
~~
CS4231
~
Semiconductor Corporation
Parallel Interface, Multimedia Audio Codec
Features
General Description
• ADPCM Compression/Decompression
I!gwave
• Free Windows ™ Software Drivers
The eS4231 provides 16-bit audio for computer multimedia systems. The CS4231 includes stereo audio
converters and complete on chip filtering for record and
playback of 16-bit audio data, plus analog mixing and
programmable gain and attenuation are included to
provide a complete audio subsystem. Free high-performance Windows software drivers are available that
support all the CS4231 features including full duplex
transfers. The eS4231 is a pin compatible upgrade to
the eS4248 and AD1848 (PLee Version).
• MPC Compatible Mixer
• Dual DMA Count Registers for Full
Duplex Operation
• DMA Transfers with On-chip FIFOs.
• Timer for AudioNisual Synchronization
• 16 rnA Bus Drive Capability
TABLE OF CONTENTS:
ORDERING INFORMATION:
CS4231-KL
0 to 700 e
CS4231-KQ
0 to 700 e
• Digital 3.3/5V Operation
• Pin Compatible with CS4248/AD1848
VD3
The eS4231 is an Mwave™
audio codec.
68-pin PLCC
100-pin TQFP
VAl VA2
LFILT RFILT
VD4
page 4-210
LMIC
RMIC
Io-------+------o(
XCTLl
ROUT
XCTLO
L---{--;-;;c;>~----1
PDWN
~~~~----------~~~--~--~--~~--~~~--~
DGNDl
DGND2
DGND3I4I7IB
Preliminary Product Information
XTAL11
XTAL10
XTAL21
XTAL20
MIN
AGNDl
LAUX2
RAUX2
AGND2
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV'93
DS111PP4
4-165
-
._.-.
_.-_..--__.._-_
....
CS4231
ANALOG CHARACTERISTICS( TA = 25°C;
VA1, VA2, VD1-VD4 = +5V;
Input Levels: Logic 0 = OV, Logic 1= VD1-VD4; 1 kHz Input Sine wave; Conversion Rate = 48 kHz; Measurement Bandwidth is 10 Hz to 20 kHz, 16-bit linear coding.)
Parameter'
Symbol
Min
Typ
Max
Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution
(Note 1)
16
-
-
Bits
ADC Differential Nonlinearity
(Note 1)
-
-
±0.5
LSB
-
dB
dB
Instantaneous Dynamic Range
Total Harmonic Distortion
Line Inputs
(Note 2) Mic Inputs
IDR
80
72
85
77
Line Inputs
Mic Inputs
THD
0.02
0.025
0.003
0.01
Signal-to-Intermodulation Distortion
-
%
%
-
90
-
dB
Line to Line Inputs
Line to Mic Inputs
Line-to-AUX1
Line-to-AUX2
-
80
80
90
90
-
dB
dB
dB
dB
Interchannel Gain Mismatch
Line Inputs
Mic Inputs
-
-
0.5
0.5
dB
dB
Programmable Input Gain Span
Line Inputs
21.5
22.5
-
dB
1.3
1.5
1.7
dB
-
10
100
LSB
--
Interchannel Isolation
Gain Step Size
ADC Offset Error
o dB gain
Gain Error
Full Scale Input Voltage:
(MGE=1) MIC Inputs
(MGE=O) MIC Inputs
LINE, AUX1, AUX2, MIN Inputs
-
-
5
%
0.266
2.66
2.66
0.29
2.9
2.9
0.31
3.1
3.1
Vpp
Vpp
Vpp
-
100
-
ppm/oC
Input Resistance
(Note 1)
20
-
-
kQ
Input Capacitance
(Note 1)
-
-
15
pF
Gain Drift
Notes:
1. This specification is guaranteed by characterization, not production testing.
2. MGE = 1 and a 10111" capacitor on the VREF pin.
* Parameter definitions are given at the end of this data sheet.
Mwave is a registered trademark of IBM Corporation.
Windows is a registered trademark of Microsoft Corporation.
Specifications are subject to change without notice.
4-166
DS111PP4
----------------------
CS4231
ANALOG CHARACTERISTICS
(Continued)
Symbol
Parameter •
Min
Typ
Max
Units
-
Bits
±O.5
lSB
dB
dB
Analog Output Characteristics - Minimum Attenuation (0 dB); Unless Otherwise Specified.
DAC Resolution
16
(Note 1)
DAC Differential Nonlinearity
Dynamic Range
TDR
IDR
80
95
85
THD
0.02
0.01
-
-
85
-
dB
95
-
dB
0.1
0.5
dB
2.0
2.15
2.3
V
-
100
-
IlA
93
94.5
-
dB
o dB to -81 dB
-82.5 dB to -94.5 dB
1.3
1.0
1.5
1.5
1.7
2
dB
dB
-
1
10
mV
(Notes 4, 5)
OUT, MOUT
1.85
2.66
2.0
2.9
2.25
3.2
Vpp
Vpp
-
100
-
ppm/°C
-
-
1
Degree
-
k.Q
- Total
- Instantaneous
Total Harmonic Distortion
All Outputs
(Note 4)
Signal-to-Intermodulation Distortion
Interchannel Isolation
Line Out
Interchannel Gain Mismatch
(Note 4)
Line Out
Voltage Reference Output
Voltage Reference Output Current
(Note 3)
DAC Programmable Attenuation Span
DAC Attenuation Step Size
DAC Offset Voltage
Full Scale Output Voltage
OlB =0
OlB = 1
Gain Drift
Deviation from Linear Phase
-
(Note 1)
External load Impedance
10
Mute Attenuation (0 dB)
80
Total Out-of-Band Energy
(Note 1)
-
0.6xFs to 3 MHz
Audible Out-of-Band Energy (Fs = 8kHz) 0.6xFs to 22 kHz
-
%
dB
-45
dB
-60
dB
65
60
120
1
1
rnA
rnA
rnA
rnA
rnA
-
dB
Power Supply
Power Supply
Current
Power Supply Rejection
Notes:
1kHz
Digital, Operating
Analog, Operating
Total
Digital, Power Down
Analog, Power Down
-
(Note 1)
40
55
43
98
-
3. DC current only. If dynamic loading exists, then the voltage reference output must be buffered
or the performance of ADCs and DACs will be degraded.
4. 10 kQ, 100 pF load.
5. All mixer and output gain tables assume the output level bit, OlB, in indirect register 16 (116) is set,
wherein the input and output full scale values are equal. When OlB=O, the output value is 3 dB
below the input value, given no gain or attenuation.
DS111PP4
4-167
----------,------------
CS4231
AUXILIARY INPUT MIXERS (TA = 25°C; VA1, VA2,
VD1-VD4 =+5V;
Input Levels: Logic 0 = OV, Logic 1 = VD1-VD4; 1 kHz Input Sine Wave)
Symbol
Parameter
Mixer Gain Range Span
LINE, AUX1, AUX2
MIN
Step Size
LINE, AUX1, AUX2
MIN
Note:
(Note 6)
Min
Typ
Max
Units
45
42
46.5
45
-
dB
dB
1.3
2.3
1.5
3.0
1.7
3.4
dB
dB
6. All mixer gain values assume OLB=1. If OLB=O, the analog output will be 3 dB below listed settings.
ABSOLUTE MAXIMUM RATINGS (AGND,
DGND = OV, all voltages with respect to OV.)
Parameter
Symbol
Digital VD1-VD4
Analog VA1,VA2
Power Supplies:
Input Current Per Pin
(Except Supply Pins)
Output Current Per Pin
(Except Supply Pins)
Min
Max
Units
-0.3
-0.3
6.0
6.0
V
V
-10
10
mA
-50
50
mA
Analog Input Voltage
-0.3
VA+0.3
V
Digital Input Voltage
-0.3
VD+0.3
V
Ambient Temperature
-55
+125
°C
-65
+150
°C
(Power Applied)
Storage Temperature
Warning:
Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND,
DGND = OV, all voltages with respect
to OV.)
Parameter
Power Supplies:
Operating Ambient Temperature
Symbol
Digital VD1-VD4
Analog, VA1,VA2,
TA
Min
Typ
Max
Units
4.75
4.75
5.0
5.0
5.25
5.25
V
V
0
25
70
°C
DS111PP4
----------------------
CS4231
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
0
-
0.40xFs
Hz
-O.S
-
+ 0.2
dB
-
-
±O.1
dB
Transition Band
0.40xFs
-
0.60xFs
Hz
Stop Band
0.60xFs
-
-
Hz
74
-
-
dB
-
-
30/Fs
s
0.0
0.1/Fs
iJ.s
iJ.s
Passband
Frequency Response
Passband Ripple
(O-O.4xFs)
Stop Band Rejection
Group Delay
Group Delay Variation vs. Frequency
ADCs
DACs
-
DIGITAL CHARACTERISTICS (TA = 2S0C; VA1, VA2, VD1-VD4
AGND1, AGND2, DGND1-DGND4, DGND7, DGNDB = OV.)
Parameter
High-level Input Voltage
Digital Inputs
XTAL1IIXTAL21, PDWN
Low-level Input Voltage
High-level Output Voltage:
0<7:0>
All Others
Low-level Output Voltage:
0<7:0>
All Others
Input Leakage Current
Output Leakage Current
10 = -16.0 mA
10 = -1.0 mA
10 = 16.0 mA
10 = 4.0 mA
= SV;
Symbol
Min
Max
Units
VIH
2.0
VD-1.0
VD+ 0.3
VD+ 0.3
V
V
VIL
-0.3
O.B
V
VOH
2.4
2.4
VD
VD
V
V
VOL
-
0.4
0.4
V
V
(Digital Inputs)
-
-10
10
iJ.A
(High-Z Digital Outputs)
-
-10
10
iJ.A
TIMING PARAMETERS
Parameter
Description
Min
Max
Units
90
twDSU
(write cycle)
22
-
ns
Data valid to WR rising edge
tRDDV
RD falling edge to data valid
(read cycle)
-
60
ns
-
ns
tSTW
WR or RD strobe width
ns
tcSSU
CS setup to WR or RD falling edge
10
tCSHD
CS hold from WR or RD rising edge
0
tADSU
ADDR <> setup to RD or WR falling edge
22
-
ns
tADHD
ADDR <> hold from WR or RD rising edge
10
-
ns
DS111PP4
ns
4-169
----------------------
CS4231
TIMING PARAMETERS (continued)
Parameter
f---
Description
Min
Max
Units
tSUOK1
DAK inactive to WR or RD falling edge (DMA cycle
completion immediately followed by a PIO cycle)
60
-
ns
tSUOK2
DAK active from WR or RD rising edge (PIO cycle
completion immediately followed by DMA cycle)
0
-
ns
tOKSUa
tOKSUb
DAl< setup to WR falling
DAK setup to RD falling edge (DMA cycles)
edge
25
25
-
ns
ns
tOH02
Data hold from WR rising edge
15
-
ns
tORHO
DRO hold from WR or RD falling edge (assumes no
more DMA cycles needed)
0
25
ns
tBWON
Time between rising edge of WR or RD to next falling
edge of WR or AD
80
-
ns
tOH01
Data hold from RD rising edge
0
20
ns
tOKHOa
tOKHOb
DAK hold from WR rising edge
OAK hold from RD rising edge
25
25
-
ns
ns
tOBOL
DBEN or DBDIR active from WR or RD falling edge
40
ns
tPOWN
PDWN pulse width low
-
ns
-----
-
-
CORO
200
~
I,..
t DRHD
1-
CDAK
~
t DKSUa
-->
t DBDL
-->
t DBDL
_t DKHDb
DBEN
DBDIR
tSTW
RD
I-
- t RDDV
D<7:0>
t DHD1
~
8-Bit Mono DMA Read/Capture Cycle
4-170
DS111PP4
.-_
_
..-_
__....._-_
..._.-.
CS4231
~
PDRQ
'..,
I.
1
PDAK
1 DKSUb
1+-1 DKHDa
1 DBDL
-----
DBEN
DBDIR
t DRHD
(high)
ISTW
WR
-
---------+~
1 WDSU
1 DHD2
D<7:0>
8-Bit Mono DMA Write/PIayback Cycle
\~-----
~
COROIPORQ
RO/WR
_____--« LE~~~W
0<7:0>
)>-____-«
RIG~~IGH
)>-_______
8-Bit Stereo or 16-Bit Mono DMA Cycle
CDRQI ~
PDRQ
\'----
COAKI
POAK
~~ -----;\~--~{
-« .
0<7:0> _ _ _
LOW
BYTE
\
(
.
HIGH
BYTE
LEFT SAMPLE
/
LOW
BYTE
I
\
(
HIGH
BYTE
)--
RIGHT SAMPLE
16-Bit Stereo DMA Cycle
DS111PP4
4-171
_-_
- .. .
.-_
--_.-.
.. ...
CS4231
~-
I/O Read Cycle
CDRO/PDRO
.:........ ; .
':.
,,','
.; ...
"',
:
:
.............',:' ......
',',','
':
.
CDAKlPDAK
CS
DB EN
DBDIR
(high)
WR
D<7:0>
A<1:0>
I/O Write Cycle
4-172
DS111PP4
----------------------
CS4231
>- I
+5V Analog (preferred)
If a separate +5V analog
supply is available, attach here
and remove the 2.00 resistor
V'-~"",~~,,-...Li
36
4f~F
47
22
17
18
~
Microphone
Inputs
~
35
0.1 ~F
0.1 ~F
~
~
19
VA2VA1 V04
29
28
L._~~~~~~~~-<
0.1 ~F 1 ~F
:::);;:
15
V03
MOUT
21
24.576MHz
Ferrite ~~ad
2.00
.-._---:::-1
:::);;:
7
V01
V02
ROUT
LOUT
XTAL21
41
1~~
POWN
III
40~
1 ~F
XTAL20
XTAL11
+5V
Supply
47kQ
ISA
BUS
23
XTAL10
LMIC
CS
59
18
Address
Decode
RMIC
AEN
0.33~F
>----1
Line
Inputs ) 0.33~F
0.33
I
30
LLiNE
27
RLiNE
~F
>----1
I
0.33~F I
0.33~F I
0.33~F I
) 0.33~F
Auxilary )
Inputs
)
)
LAUX1
CS4231
RAUX1
(PLCC)
Pinout
LAUX2
RAUX2
MIN
0.33~F
26
This trace
must be
very short
A1
AO
WR
RO
~
1000 pF
NPO
31
~
1000 pF
NPO
32
RFILT
LFILT
VREF
0.47~F
33
~ 10~F ~ 0.1
~F
VREFI
SA 19:2
9
10
61
60
SAl
SAO
IOWC
IORC
XCTLO
XCTL1
07
06
05
D4
D3
D2
01
DO
OBOIR
OBEN
PORQ
CORQ
POAK
COAK
IRQ
07
06
05
04
03
02
01
DO
DRQ
DRQ
OAK
OAK
IRQ
12
13
11
57
-b
Board Analog
Ground
l
Board Digital
Ground
Figure 1. Recommended Connection Diagram
(See Figures 16 & 17 for Layout Recommendations)
DS111PP4
4-173
----------.----------GENERAL DESCRIPTION
The CS4231 is a monolithic integrated circuit
that provides audio in personal computers or
other parallel interface environments. The functions include stereo Analog-to-Digital and
Digital-to-Analog converters (ADCs and DACs),
analog mixing, anti-aliasing and reconstruction
filters, line and microphone level inputs, optional
A-Law / Il-Law coding, simultaneous capture
and playback (at the same sample rates) and a
parallel bus interface. Five analog inputs are provided and three can be multiplexed to the ADC.
The line input, two auxiliary inputs and a mono
input can be mixed with the output of the DAC
with full volume control. Several data modes are
supported including 8- and 16-bit linear as well
as 8-bit companded, 4-bit ADPCM compressed,
and 16-bit big Endian. The CS4231 is packaged
in a 68-pin PLCC or a IOO-pin TQFP.
Enhanced. Functions (MODE 2)
The CS4231's initial state is labeled MODE
and forces the CS4231 to appear as a CS4248.
Enhanced functionality is provided by a second
mode on the CS4231. To switch from MODE 1
to MODE 2, the MODE2 bit should be set to
one in the MODE and ID register (112). When
MODE 2 is selected, the bit IA4 in the Index
Address register (RO) will be decoded as a valid
index pointer providing 16 additional registers
and increased functionality over the CS4248.
To reverse the procedure, clear the MODE2 bit
and the CS4231 will resUme operation in
MODE 1. Since previous code should write a
zero to bit IA4 of the Index Address register
(RO), the CS4231 is backwards compatible with
the CS4248 and the AD1848.
CS4231
output mixer. This fourth input to the mixer
completes the recommended mixer configuration
for MPC Level-2 compliance. The LINE mix
register provides 32 volume adjustments in 1.5
dB steps. In addition, there is a one bit mute
control.
The additional MODE 2 functions are:
1.
2.
3.
4.
5.
6.
Full-Duplex DMA support
A programmable timer
Mono output with mute control
Mono input with mixer volume control
ADPCM and Big Endian audio data formats
Independent selection of capture and
playback audio data formats
ANALOG HARDWARE DESCRIPTION
The analog hardware consist of an MPC
Level 2-compatible mixer (four stereo mix
sources), three line-level stereo inputs, a stereo
microphone input, a mono input, a mono output,
and a stereo line output. This section describes
the analog hardware needed to interface with
these pins.
Analog Inputs
The analog inputs consist of four stereo analog
inputs, and one mono input. As shown on this
data sheet cover, the input to the ADCs comes
from a multiplexer that selects between two analog line-level inputs (LINE, AUXl), a
microphone level input (MIC), and the output
from the MPC-compatible mixer. The LINE and
AUXI lines also feed the MPC mixer and include individual volume controls. Unused analog
inputs should be connected together and then
connected through a capacitor to analog ground.
Mixer Attenuation Control on Line Input
Line-Level Inputs plus MPC Mixer
The CS4231 adds mixer attenuation control for
the LINE inputs which are then summed into the
4-174
The analog input interface is designed to accommodate four stereo inputs and one mono input.
DS111PP4
----------------------
CS4231
Three of these sources are multiplexed to the
ADC. These inputs are: a stereo line-level input
(LINE), a stereo microphone input (MIC), and a
stereo auxiliary line-level input (AUXI). The
LINE and AUXI inputs have a separate path,
with volume control, to the output analog mixer
which has the additional inputs of a stereo
AUX2 channel, a mono input channel, and the
output of the DACs. All audio inputs should be
capacitively coupled to the CS4231.
Since some analog inputs can be as large as
2 VRMS, the circuit shown in Figure 2 can be
used to attenuate the analog input to 1 VRMS
which is the maximum voltage allowed for the
line-level inputs on the CS423 1.
5.6
kQ
Mono Input with Attenuation and Mute
The mono input, MIN, is useful for mixing the
output of the "beeper" (timer chip), provided in
all PCs, with the rest of the audio signals. The
attenuation control allows 16 levels in -3dB
steps. In addition, a mute control is provided.
The attenuator is a single channel block with the
resulting signal sent to the output mixer where it
is mixed with the left and right outputs. Figure 4
illustrates a typical input circuit for the Mono In.
Although this input is described for a low-quality beeper, the input is of the same high-quality
as all other analog inputs and may be used for
other purposes. At power-up, the MIN line is unmuted (as is the mono out line) allowing the
initial beeps heard, when the computer is initializing, to pass through.
+5VA
(Low Noise)
Figure 2. Line Inputs
Microphone Level Inputs
The microphone level inputs, LMlC and RMIC,
include a selectable + 20dB gain stage for interfacing to an external microphone. The 20dB gain
block can be turned off to provide another stereo
line-level input. Figure 3 illustrates a singleended microphone input buffer circuit that will
support lower gain mics.
1.5kQ
4.7kQ
Figure 4. Mono Input
Analog Outputs
The analog output section of the CS4231 provides a stereo line-level output. The other output
types (headphone and speaker) can be implemented with external circuitry. LOUT and
ROUT outputs should be capacitively coupled to
external circuitry. Figure 1 shows the simplicity
of the analog output interface.
Mono Output with Mute Control
LMIC
V\r--~I--_-=3"'12 VREF
Figure 3. Left or Mono Microphone Input
DS111PP4
The mono output, MOUT, is a sum of the left
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
channel can be used to drive the PC-internal
mono speaker using an appropriate drive circuit.
This approach allows the traditional PC-sounds
4-175
.. ...-.
-. ..--_._.
~-
-~-
CS4231
~-
to be integrated with the rest of the audio system. Figure 5 illustrates a typical speaker driver
circuit. The mute control is independent of the
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The
power-up default has MIN and MOUT enabled
to provide a pass~through for the beeps heard at
power-up.
DIGITAL HARDWARE DESCRIPTION
The digital hardware consist of the data bus, address bus, and control signals needed for the
parallel bus, as well as an interrupt and DMA
signals.
+5V
Parallel Data Interface
MOUT
9
~ ~.022J.1F
RESDRV
MC34119
~.022J.1F
Figure 5. Mono Output
Miscellaneous Analog Signals
The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capacitors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to
the ADCs. By placing these filters at the input to
the ADCs, low~pass filters at each analog input
pin is avoided.
The VREFI pin is used to lower the noise of the
internal voltage reference. A lO~F and O.lf..lF capacitor to analog ground should be connected
with a short wide trace to this pin. No other connection should be made, as any coupling onto
this pin will degrade the analog performance of
the codec. Likewise, digital signals should be
kept away from VREFI for similar reasons.
The VREF pin is typically 2.1 V and provides a
common mode signal for single-supply external
circuits. VREF only supports DC loads and
should be buffered if AC loading is needed. For
4-176
typical use, a 0.47 f..lF capacitor should be connected to VREF. High-gain microphone circuits
can be improved by increasing the capacitance to
10 f..lF.
The 8-bit parallel port of the CS4231 provides
an interface which is compatible with most computer peripheral busses. This parallel interface is
designed to operate on the Industry Standard Architecture (IS A) bus, but the CS4231 will easily
interface with other buses such as EISA and microchannel. Two types of accesses can occur via
the parallel interface: Programmed 110 (PIO) access, and DMA access.
There is no provision for the CS4231 to "hold
off' or extend a cycle occurring on the parallel
interface. Therefore, the internal architecture of
the CS4231 accepts asynchronous parallel bus
cycles without interfering with the flow of data
to or from theADC and DAC sections.
FIFOs
The CS4231 contains 16-sample FIFOs in both
the playback and capture paths. The FIFOs are
transparent and have no programming associated
with them.
When playback is enabled, the playback FIFO
continually requests data until the FIFO is full,
and then makes requests as positions inside the
FIFO are emptied, thereby keeping the playback
FIFO as full as possible. Thus when the system
cannot respond within a sample period, the FIFO
DS111PP4
---------------------is emptied, avoiding a momentary loss of audio
data. If the FIFO runs out of data, the last valid
sample can be continuously output to the DACs
(if DACZ in 116 is set) which will eliminate
pops from occurring.
When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
every sample period. Thus when the system cannot respond within a sample period, the capture
FIFO starts filling thereby avoiding a loss of
data in the audio data stream.
CS4231
between the CS423 1 and the bus. The CS4231 is
responsible for asserting a request signal whenever the CS4231 's internal buffers need
updating. The logic interfaced with the CS4231
responds with an acknowledge signal and strobes
data to and from the CS4231, 8 bits at a time.
The CS4231 keeps the request pin active until
the appropriate number of 8-bit cycles have occurred to transfer one audio sample. Notice that
different audio data types will require a different
number of 8-bit transfers.
DMA Interface
High Cu"ent Data Bus Drivers
The CS4231 provides 16 rnA drivers eliminating
the need for off chip drivers in many cases. If a
full 24 rnA drive is required, the appropriate direction and driver select lines are provided. The
current drivers are provided for the data bus,
DMA request line, and the interrupt request line.
PIO Registers Interface
The first type of parallel bus access is programmed I/O (PIO) to the four control registers.
The control registers allow access to status,
audio data, and all indirect registers via the index registers. The RD and WR signals are used
to define the read and write cycles respectively.
The PIO register cycle is defined by the assertion of the CS4231 CS signal while the DMA
acknowledge signals, CDAK and PDAK, are inactive. For read cycles, the CS4231 will drive
data on the DATA lines while the host asserts the
RD strobe. Writ~ cycles require the host to assert
data on. the DATA lines and strobe the WR signal. The CS4231 will latch data into the PIO
register on the rising edge of the WR strobe. The
CS4231 CS signal should remain active until after completion of the read or write cycle. 110
cycles are the only type of cycle which can access the internal control and status registers.
The second type of parallel bus cycle on the
CS4231 is a DMA transfer. DMA cycles are distinguished from PIO register cycles by the
assertion by the CS4231 of a CDRQ (or PDRQ)
followed by an acknowledgment by the host by
the assertion of CDAK (or PDAK). While the
acknowledgment is received from the host, the
CS4231 assumes that any cycles occurring are
DMA cycles and ignores the addresses on the
address lines and the CS line.
The CS4231 may assert the DMA request signal
at any time. Once asserted, the DMA request
will remain asserted until a DMA cycle occurs to
the CS4231. Once the falling edge of the final
WR or RD strobe of a full sample of a DMA
cycle occurs, the DMA request signal is negated
immediately. DMA transfers may be terminated
by resetting the PEN andlor CEN bits in the interface Configuration register (19), depending on
the DMA that is in progress (playback, capture,
or both). Termination of DMA transfers may
only happen between sample transfers on the
bus. If PDRQ andlor CDRQ goes active while
resetting PEN andlor CEN, the request must be
acknowledged (PDAK andlor CDAK) and a final sample transfer completed. The CS4231
supports up to two DMA channels.
The audio data interface typically uses DMA request/grant pins to transfer the digital audio data
DS111PP4
4·177
.._-_
_.-_..--_._.
__
...-.
CS4231
Dual DMA Channel Mode
Miscellaneous Signals
In dual DMA channel mode, playback and capture DMA requests and acknowledges occur on
independent DMA channels. In this mode, capture and playback are enabled and set for DMA
transfers. In addition, the dual DMA mode must
be set (SDC = 0). The Playback- and CaptureEnables (PEN, CEN, 19) can be changed without
a Mode Change Enable (MCE, RO). This allows
for proper full duplex control where applications
are independently using playback and capture.
The power supply providing analog power
should be as clean as possible to minimize coupling into the analog section and degrading
analog performance. The VD 1 and VD2 pins are
isolated from the rest of the digital power pins
and provide digital power for the asynchronous
parallel bus. These two pins can be connected
directly to the digital power supply. VD3 and
VD4 digital power supply pins provide power to
the internal digital section of the codec and
should be optimally quieter than VDl and VD2.
This can be achieved by using a ferrite bead as
shown in the typical connection diagram in Figure 1. Grounding is covered in the Grounding
and Layout section.
Single DMA Channel (SDC) Mode
When two DMA channels are not available, the
SDC mode forces all DMA transfers (capture or
playback) to occur on a single DMA channel
(playback channel). The trade-off is that the
CS4231 will no longer be able to perform simultaneous DMA capture and playback.
To enable the SDC mode, set the SDC bit in the
Interface Configuration register (19). With the
SDC bit asserted, the internal workings of the
CS4231 remain exactly the same as dual mode,
except for the manner in which DMA request
and acknowledges are handled.
The playback of audio· data' will occur on the
playback channel exactly as dual channel operation. However, the capture audio channel· is now
diverted to the playback channel. This means
that the capture DMA request occurs on the
PDRQ pin and the PDAK pin is used to acknowledge the capture request. (In MODE 2, the
capture data format is always set in register 128.)
Note, simultaneous capture and playback cannot
occur in SDC mode. If both playback and capture are enabled, the default will be playback.
In SDC mode, the CDRQ pin· is logic low (inactive). The CDAK pin is ignored by the CS4231.
SDC does not have any affect when using Pia
accesses.
4-178
An interrupt pin, IRQ, is provided to allow for
host notification by the CS4231. Since the interrupt is mainly a software function, it is described
in more detail under the software section.
Crystals / Clocks
Four pins have been allocated to allow the interfacing of two crystal oscillators to the CS4231:
XTALlI, XTALlO, XTAL21, XTAL20. The
crystals should be designed as fundamental
mode, parallel resonant, with a load capacitor of
between 10 and 20 pF. The capacitors shown in
Figure 1, connected to each of the crystal pins,
should be twice the load capacitance specified to
the crystal manufacturer. The XTALI oscillator
is designed with slightly more gain· to handle
higher frequencies, but any crystal with the
above· specifications should suffice. The standard
.crystals for audio are:
XTAL1:
24.576 MHz
Fundamental Mode
Parallel Resonant, CL = 20 pF
XTAL2:
16.9344 MHz
Fundamental Mode
Parallel Resonant, CL =20 pF
DS111PP4
_.-_..--__.._-_
...
._.-.
These crystal frequencies support the standard
sample frequencies listed in Table 7.
External CMOS clocks may be connected the
crystal inputs (XTALlI, XTAL21) in lieu of the
crystals. When using external CMOS clocks, the
XTAL out pins should be left floating. Extreme
care should be used when laying out a board using external clocks since coupling between
clocks can degrade analog performance.
CS4231
SOFTWARE DESCRIPTION
The CS4231 must be in Mode Change Enable
Mode (MCE=l) before any changes to the Interface Configuration register (19) or the Data
Format registers (IS, 12S) are allowed. The exceptions are CEN and PEN which can be
changed "on-the-fly" via programmed 110 writes
to these bits. All outstanding DMA transfers
must be completed before new values of CEN or
PEN are recognized.
Power Down - PDWN
Procedures
The PDWN signal places the CS4231 into maximum power conservation mode. When PDWN
goes low, any reads of the codec's parallel interface return SO hex, all analog outputs are muted,
and the voltage reference then slowly decays to
ground. The PDWN signal should be held low
while power is applied to the codec. Once the
power supplies have settled, PDWN should be
brought high which starts an initialization procedure and causes a full calibration cycle to occur.
While the codec is initializing, any reads from
the parallel interface will return SO hex and
writes will be ignored. When initialization is
completed, the registers will contain their reset
value as stated in the register section of the data
sheet.
Power-Down and Initialization
To put the CS4231 into a power-down mode, the
PDWN pin is pulled low. In this state the host
interface reads SOh indicating that it is unable to
respond and all analog circuits are turned off.
DBENIDBDIR
To let the CS4231 go through its reset initialization the PDWN pin should be set high. This
rising edge starts the initialization process in
which a full calibration occurs. While the
CS4231 is initializing, SO hex is returned from
all reads by the host computer. All writes during
initialization of the CS4231 will be ignored. At
the end of the initialization, all registers are set
to known reset values as documented in the register definition section.
If needed, the DBEN and DBDIR pins can con-
Auto Calibration
trol an external data buffer to the CS4231. The
CS4231 contains 16 rnA bus drivers so the external data buffer is only needed when driving a
full 24 rnA bus. DBEN enables the external drivers and DBDIR controls the direction of the data
flow. Both signals are normally high, where
DBDIR high points the transceiver towards the
codec and low points the transceiver towards the
data bus. See Figure 1 for a typical connection
diagram.
DS111PP4
The CS4231 has the ability to calibrate the
ADCs and DACs. Auto-calibration occurs whenever the CS4231 returns from Mode Change
Enable (MCE) AND the ACAL bit in the Interface Configuration register (19) has been set.
The completion of calibration can be determined
by polling the Auto-Calibrate In-Progress bit in
the Error Status and Initialization register (AC!,
Ill). This bit will be high while the calibration is
in progress and low once completed. The autocalibration sequence will take at least 16S
4-179
-
_
..--__.._-_
...
.-_
.-.-.
sample periods. Transfers enabled during calibrate will not begin until the calibration cycle
has completed.
The auto-calibrate procedure is as follows:
1) Place the CS4231 in Mode Change Enable
using the MCE bit of the Index Address
register (RO).
2) Set the ACAL bit in the Interface Configuration register (19).
3) Return from Mode Change Enable by resetting the MCE bit of the Index Address
register (RO).
4) Wait until SOh NOT returned
5) Wait until ACI (Ill) cleared to proceed
Changing Sampling Rate
The internal states of the CS4231 are synchronized by the selected sampling frequency defined
in the Data Format registers (IS, 12S). The
changing of either the clock source or the clock
frequency divide requires a special sequence for
proper CS4231 operation:
1) Place the CS4231 in Mode Change Enable
using the MCE bit of the Index Address
register (RO).
2) During a single write cycle, change the
Clock Frequency Divide Select (CFS)
and/or Clock Source Select (CSL) bits of
the Fs & Playback Data Format register
(IS) to the desired value. (The data format
may also be changed.)
3) The CS4231 resynchronizes its internal
states to the new clock. During this time
the CS4231 will be unable to respond at its
parallel interface. Writes to the CS4231
will not be recognized and reads will always return the value SO hex.
4) The host now polls the CS4231 's Index Address register (RO) until the value SO hex is
no longer returned.
5) Once the CS4231 is no longer responding
to reads with a value of SO hex, normal op4-180
CS4231
eration can resume and the CS4231 can be
removed from MCE.
The CSL and CFS bits cannot be changed
unless the MCE bit has been set. Attempts
to change the Data Format registers (IS,
12S) or Interface Configuration register (19,
except CEN and PEN) without MCE set,
will not be recognized.
Audio Data Formats
In MODE 1 operation, all data formats of the
CS4231 are in "little endian" format. This format
defines the byte ordering of a multibyte word as
having the least significant byte occupying the
lowest memory address. Likewise, the most significant byte of a little endian word occupies the
highest memory address.
The sample frequency is always selected in the
Fs and Playback Data Format register (IS). In
MODE 1· the same register, IS, determines the
audio data format for both playback and capture;
however, in MODE 2, IS only selects the playback data format and the capture data format is
independently selectable in the Capture Data
Format register (12S).
The CS4231 always orders the left channel data
before the right channel. Note that these definitions apply regardless of the specific format of
the data. For example, S-bit linear data streams
look exactly like S-bit companded data streams.
Also, the left sample always comes first in the
data stream regardless of whether the sample is
16-bit or S-bit in size.
There are four data formats supported by the
CS4231 during MODE 1 operation: 16-bit
signed (little endian), S-bit unsigned, S-bit companded Il-Law, and S-bit companded A-Law.
See Figures 6 through 9.
Additional data formats are supported in
MODE 2 operation: 4-bit ADPCM, and 16-bit
DS111PP4
.._-_
_.-_..--_._.
__
...-.
CS4231
32-bilWord
24
31
16
23
Time
o
8 7
15
Figure 6. 8·bit Mono, Unsigned Audio Data
32-bitWord
31
24
23
16
Time
o
8 7
15
Figure 7. 8·bit Stereo, Unsigued Audio Data
31
24 23
16
15
8 7
o
Figure 8. 16·bit Mono, Signed Little Endian Audio Data
31
24 23
16
15
8 7
o
Figure 9. 16·bit Stereo, Signed Little Endian Audio Data
DS111PP4
4-181
.._-_
.-_
._.-.
_
..--__
...
CS4231
32-bitWord
----------------~-----------------
31
28 27
24 23
20 19
16 15
4 3
8 7
12 11
o
Figure 10. 4-bit Mono, ADPCM Audio Data
32-bitWord
------------------~-------------------
31
28 27
24 23
20 19
16 15
4 3
87
12 11
o
Figure 11. 4-bit Stereo, ADPCM Audio Data
-
32-bitWord
23
16
31
24
Time
o
7
15
8
Figure 12. 16-bit Mono, Signed Big Endian Audio Data
32-bit Word
Time
-------------' ~-------------
23
16
31
24 7
o
15
8
Figure 13. 16-bit Stereo, Signed Big Endian Audio Data
4-182
DS111PP4
.-_
._._
..--__.._-_.
...
CS4231
signed big endian. See Figures 10 through 13.
With the addition of the big endian and ADPCM
audio data formats, the CS4231 is compliant
with the IMA recommendations for digital audio
data formats (and sample frequencies).
8-bit Companded
The 16-bit signed format (also called 16-bit 2's
complement) is the standard method of representing 16-bit digital audio. This format gives
96 dB theoretical dynamic range and is the
standard for compact disk audio players. This
format uses the value -32768 (8000h) to represent minimum analog amplitude while
32767 (7FFFh) represents maximum analog amplitude.
The 8-bit companded formats (A-Law and ILLaw) come from the telephone industry. IL-Law
is the standard for the United States/Japan while
A-Law is used in Europe. Companded audio allows either 64 dB or 72 dB of dynamic range
using only 8-bits per sample. This is accomplished using a non-linear companding transfer
function which assigns more digitalization codes
to lower amplitude analog signals with the sacrifice of precision on higher amplitude signals.
The IL-Law and A-Law formats of the CS4231
conform to the CCITT G.711 specifications. Figure 15 illustrates the transfer function for both
A- and IL-Law. Please refer to the standards mentioned above for an exact definition.
8-bit Unsigned
ADPCM CompressionlDecompression
The 8-bit unsigned format is commonly. used in
the personal computer industry. This format delivers a theoretical dynamic range of 48 dB. This
format uses the value 0 (OOh) to represent minimum analog amplitude while 255 (FFh)
represents maximum analog amplitude. The 16bit signed and 8-bit unsigned transfer functions
are shown in Figure 14.
In MODE 2, the CS4231 also contains Adaptive
Differential Pulse Code Modulation (ADPCM)
for improved performance and compression ratios over IL-Law or A-Law. The ADPCM format
is compliant with the IMA standard and provides
a 4-to-l compression ratio (i.e. 4 bits are saved
for each 16-bit sample captured). For more information on the specifics of the format, contact the
IMA at (202) 408-1000. See Figures 10 and 11.
16-bit Signed
+FS
+FS
w
W
::J
:::0
~
-'
'CI"
>
(J) 0
9
z«
«
0
-'
0
'z"
'"
B-bit
unsigned:
16-bit -32768
2'scomp:
65
128
191
-16384
0
16384
A-Law: 2Ah
DIGITAL CODE
Figure 14. Linear Transfer Functions
DS111PP4
32767
u-Law: DOh
15h
3Fh
55h1D5h
7FhlFFh
95h
BFh
AAh
BOh
DIGITAL CODE
Figure 15. Companded Transfer Functions
4-183
-
.._-_
_.-_..---._.
__
...-.
When using the ADPCM data format, the DMA
Base register count is not on a per sample basis.
CS4231
by four, minus one. The same number is used
whether the data format is stereo or mono
ADPCM. Symbolically:
DMA Registers
DMA Base registef16
The DMA registers allow easier integration of
the CS4231 in ISA systems. Peculiarities of the
ISA DMA controller require an external count
mechanism to notify the host CPU of a full
DMA buffer via interrupt. The programmable
DMA Base registers provide this service.
=Nbl4 - 1
Where Nb is the number of BYTES transferred
between interrupts and the "DMA Base registef16" consists of the concatenation of the upper
and lower DMA Base registers.
Playback DMA Registers
The act of writing a value to the Upper Base
register cause both Base registers to load the
Current Count register. DMA transfers are enabled by setting the PEN/CEN bit while
PPIO/CPIO is clear. (PPIO/CPIO can only be
changed while the MCE bit is set.) Once transfers are enabled, each sample that is transferred
by a DMA cycle will decrement the Current
Count register (with the exception of the
ADPCM format) until zero is reached. The next
sample after zero generates an interrupt and reloads the Current Count registers with the values
in the Base registers.
For all data formats except ADPCM, the DMA
Base registers must be loaded with the number
of samples, minus one, to be transferred between
"DMA Interrupts". Stereo data contains twice as
many samples as mono data; however, 8-bit data
and 16-bit data contain the same number of samples. Symbolically:
DMA Base registef16
=Ns - 1
Where Ns is the number of samples transferred
between interrupts and the "DMA Base registef16" consists of the concatenation of the upper
and lower DMA Base registers.
For the ADPCM data format, the contents of the
DMA Base registers is calculated differently
from any other data format. The Base registers
must be loaded with the number of BYTES to be
transferred between "DMA interrupts", divided
4-184
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
MODE 2. In MODE 1, these registers (I14/15)
are used for both playback and capture; therefore, full-duplex DMA operation is not possible.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (124) is set
causing the !NT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (124).
Capture DMA Registers
The Capture DMA Base registers (130/31) provide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex operation capture and playback can occur
simultaneously. These registers are provided in
MODE 2 operation only.
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (124) is set
causing the !NT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Capture Interrupt bit, CI (124).
Digital Loopback
Digital Loopback is enabled via the LBE bit in
the Loopback Control register (I13). This loopDS111PP4
---------------------back routes the digital data from the ADCs to
the DACs. This loopback can be digitally attenuated via additional bits in the Loopback Control
register (113). Loopback is then summed with
DAC data supplied at the digital bus interface.
When loopback is enabled, it will "freerun" synchronous with the sample rate. The digital
loopback is shown in the CS4231 Block Diagram on the front cover. This loopback can be
used to mix the incoming microphone data with
data from the DACs. Since the CS4231 allows
selection of different data formats between capture and playback, if the capture channel is set to
mono and the playback channel set to stereo, the
mono input (mic) data will be mixed into both
channels of the output mixer.
If the sum of the loopback and bus data are
greater than full scale, CS4231 will send the appropriate full scale value to the DACs (clipping).
Timer Registers
The Timer registers are provided for synchronization, watch dog and other functions where a
high resolution time reference is required. This
counter is 16 bits and the exact time base, listed
in the register description, is determined by the
crystal selected.
The Timer register is set by loading the high and
low registers to the appropriate values and setting the Timer Enable bit, TE, in the Alternate
Feature Enable register (116). This value will be
loaded into an internal Current Count register
and will decrement at approximately a 10 ~sec
rate. When the value of the Current Count register reaches zero, an interrupt will be posted to
the host and the Timer Interrupt bit, TI, is set in
the Alternate Feature Status register (124). On
the next timer clock the value of the Timer registers will be loaded into the internal Current
Count register and the process will begin again.
The interrupt is cleared by any write to the
Status register (R2) or by writing a "0" to the
DS111PP4
CS4231
Timer Interrupt bit, TI, in the Alternate Feature
Status register (124).
The !NT bit of the Status register (R2) always
reflects the status of the CS4231 internal interrupt state. A roll-over from any Current Count
register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status register (R2), or by clearing the appropriate bit or bits
(PI, CI, TI) in the Alternate Feature Status register (124). The IRQ pin of the CS4231 mayor
may not go active on an interrupt event.
The Interrupt Enable (lEN) bit in the Pin Control
register (110) determines whether the interrupt
pin responds to the interrupt event in the
CS4231. When the lEN bit.is low, the interrupt
is masked and the IRQ pin of the CS4231 is
forced low. However, the !NT bit in the Status
register (R2) always responds to the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the CS4231 in an
appropriate amount of time. The amount of time
for such data transfers depends on the frequency
selected within the CS4231.
Should an overrun condition occur during data
capture, the last whole sample (before the overrun condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transferring the sample.
Should an underrun condition occur in a playback case the last valid sample will be output
(assuming DACZ = 0) to the digital mixer. This
will mask short duration error conditions. When
the next complete sample arrives from the host
computer the data stream will resume on the
next sample clock.
4-185
----------------------
CS4231
CS4231 REGISTER MAPPING
Addr.
Register Name
RO
0
R1
1
Index Address register
Indexed Data register
R2
2
Status register
R3
3
PIO Data register
Table 1. Direct Registers
The two address pins of the CS4231 allow access to four8-bit registers. Two of these registers
provide indirect accessing to more CS4231 registers via an index register. The other two
registers provide status information and allow
audio data to· be transferred to and from the
CS4231 without using DMA cycles or indexing.
Physical Mapping
The PIa registers are I/O mapped via four locations. Two address pins provide access to all of
the CS4231 's registers. The four direct registers
are shown in Table 1. The first two direct registers are used to access 32 indirect registers
shown in Table 2. As indicated by the arrows,
the Index Address register (RO) points to the indirect register that is accessed through the
Indexed Data register (R1).
This section describes all the direct and indirect
registers. Table 3 details a summary of each bit
in each register with Tables 4 through 10 illustrating the majority of decoding needed when
programming the CS4231 and are included for
reference; Tables 4 through 8 indicate gain settings at internal nodes. If OLB= 1 then the
output will reflect the gain setting. If OLB= 0,
the output will be attenuated by 3 dB as indicated in the specifications. The CS4231 powers
up into the reset state which is defined as
MODE 1. MODE 1 is backwards compatible
with the CS4248 and only allows access to the
first 16 indirect registers. Setting the MODE2 bit
in the MODE and ID register (112) enables
4-186
r
Index
~
Register Name
10
Left ADC Input Control
11
Right ADC Input Control
12
Left Aux #1 Input Control
13
Right Aux #1 Input Control
14
Left Aux #2 Input Control
15
Right Aux #2 Input Control
16
Left DAC Output Control
17
Right DAC Output Control
18
Fs & Playback Data Format
19
Interface Configuration
110
Pin Control
111
Error Status and Initialization
112
MODE and ID (MODE2 bit)
113
Loopback Control
114
Playback Upper Base Count
115
Playback Lower Base Count
116
Alternate Feature Enable I
117
Alternate Feature Enable II
118
Left Line Input Control
119
Right Line Input Control
120
Timer Low Byte
121
Timer High Byte
122
RESERVED
123
RESERVED
124
Alternate Feature Status
125
Version I Chip ID
126
Mono Input & Output Control
127
RESERVED
128
Capture Data Format
129
RESERVED
130
Capture Upper Base Count
131
Capture Lower Base Count
Table 2. Indirect Registers
DS111PP4
_.-_..--__.._-_
...
._.-.
CS4231
MODE 2 which allows access to indirect registers 16 through 31 and enables all the features of
the CS4231.
03
02
01
DO
IINIT I MCE I TAD 11A4 I IA3
IA2
IA1
lAO
06
05
04
IA3-IAO
Index Address: These bits define the
address of the CS4231 register accessed by the Indexed Data register
(R1). These bits are read/write.
1A4
Allows access to indirect registers 16
- 31. Only available in MODE 2. In
MODE 1,this bit is reserved.
MCE
TRD
Mode Change Enable: This bit must
be set whenever the current mode
of the CS4231 is changed. The Data
Format (18, 128) and Interface Configuration (19) registers CANNOT be
changed unless this bit is set. The
exceptions are CEN and PEN which
can be changed "on-the-fly". The
DAC output is muted when MCE is
set.
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the status
register is set. Independent for playback and capture interrupts.
o - Transfers
Enabled (PDRQ and
CDRQ occur uninhibited)
1 - Transfers Disabled (PDRQ and
CDRQ only occur if INT bit is 0)
INIT
CS4231 Initialization: This bit is read
as 1 when the CS4231 is in a state
in which it cannot respond to parallel
interface cycles. This bit is read-only.
Immediately after RESET (and once the CS4231
has left the INIT state), the state of
this register is: 010XOOOO
During initialization and power down, this register CANNOT be written and always reads
10000000 (80h)
OS111PP4
07
06
05
04
03
02
01
DO
I 107
106
105
104
103
102
101
100
Indexed Oata register: These bits are
the indirect register referenced by
the Indexed Address register (RO).
107-100
Index Address Register (RO)
07
Indexed Data Register (Rl)
During initialization and power down, this register can NOT be written and is always read
10000000 (80h)
I/O Data Registers
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During initialization and power down, this register CANNOT be written and is always read
10000000 (80h)
Capture I/O Data Register (R3, Read Only)
07
06
05
I C07
C06
CD5
C07-COO
04
03
CD4 CD3
02
01
C02
CD1
DO
COO I
Capture Oata Port. This is the control
register where capture data is read
during programmed I/O data transfers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once this has occurred, and a read of the status
has occurred, the state machine and Status register (R2) will. point to the first byte of the new
sample.
4-187
.....
_-_..._.-.
.-_
_
..-__
Direct Registers:
A1 AO
RO 0 0
R1 0 1
R2 1 0
R3 1 1
R3 1 1
(RO-R3)
07
INIT I
107
CUll
C07
P07
CS4231
06
05
MCE .. I TRO I
106
105
CUR I CROY I
C06
COS
P06
POS
Indirect Registers: (10-131)
IA4-IAO
07
06
0
lSS1
lSSO
1
RSS1
RSSO
2
LX1M
3
RX1M
4
LX2M
5
RX2M
6
lOM
7
ROM
FMT1t
FMTO
811
PPIO
9§
CPIO
10
XCTl1
XCTlO
11
COR
PUR
12
1
MOOE2
13
lBAS
lBA4
14 *
PUB7
PUB6
15 *
PlB7
PlB6
16
OlB
TE
17
18
llM
19
RlM
20
Tl7
Tl6
21
TU7
rU6
22
23
24
TI
25
V2
V1
26
MIM
MOM
27
28 §
FMT1
FMTO
29
' 30
CUB7
CUB6
31
ClB7
ClB6
04
lA4t
104
SER
C04
P04
05
lMGE
RMGE
04
LDAS
ROAS
LX1G4
RX1G4
LX2G4
RX2G4
lOA4
ROA4
C/l
S/M
-
-
ACI
ORS
-
I
03
IA3
103
PUll
C03
P03
02
IA2
102
PUR
CO2
P02
03
LAG3
RAG3
LX1G3
RX1G3
lX2G3
RX2G3
lOA3
ROA3
CSF2
ACAl
OEN
ORR1
103
lBA1
PUB3
PlB3
02
LAG2
RAG2
LX1G2
RX1G2
lX2G2
RX2G2
lOA2
ROA2
CSF1
SOC
I
I
-
01
IA1
101
I PROY
C01
P01
01
LAG 1
RAG1
LX1G1
RX1G1
LX2G1
RX2G1
lOA1
ROA1
CSFO
CEN
lEN
ORL1
101
00
LAGO
RAGO
lX1GO
RX1GO
lX2GO
RX2GO
lOAD
ROAD
C2Sl
PEN
-
-
-
llG3
RlG3
Tl3
TU3
llG2
RlG2
Tl2
TU2
llG1
RlG1
Tl1
TU1
ORlO
100
lBE
PUBO
PlBO
OACZ
HPF
llGO
RlGO
TlO
TUO
-
-
-
-
-
PI
CU
-
-
-
-
-
MIA3
CO
CI02
MIA2
PO
CI01
MIA1
C/l
S/M
-
-
-
PU
ClOD
MIAO
-
-
CUB3
ClB3
CUB2
ClB2
CUB1
ClS1
CUBO
ClBO
-
-
lBA3
PUBS
PlBS
lBA2
PUB4
PlB4
-
-
-
TlS
TUS
llG4
RlG4
Tl4
TU4
CI
VO
-
-
-
CUBS
ClBS
CUB4
ClB4
ORRO
102
lBAO I
PUB2
PUB1
PlB2
PlB1
I
00
lAO
100
INT
COO
POD
-
-
-
I
1
-
t
IA4 and FMT2 bits are only available in MODE 2 (IA = 12, bit 6 = 1)
Since IA4 is only available in MODE 2, registers 16-31 are only available in MODE 2
• When in MODE I, the playback base registers ( upper and lower) are used for both playback and capture.
§ MCE must be set before changing any bits in these registers (except CEN and PEN).
Table 3. Register Bit Summary
4-188
OS111PP4
----------------------
CS4231
NOTE: Output level relative to input level assuming OLB=l.
AG3 AG2 AG1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
2
3
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
AGO
0
1
0
1
Level
0.0 dB
1.5 dB
3.0 dB
4.5 dB
0
1
0
1
18.0
19.5
21.0
22.5
dB
dB
dB
dB
Thble 4. ADC Input Gain
0
1
2
3
A5
0
0
0
0
A4
0
0
0
0
A3
0
0
0
0
A2
0
0
0
0
A1
0
0
1
1
AO
0
1
0
1
60
61
62
63
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Level
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-90.0
-91.5
-93.0
-94.5
dB
dB
dB
dB
G3
0
0
0
0
0
0
0
0
9
10
11
12
G4
0
0
0
0
0
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
1
1
1
1
1
G2
0
0
0
0
1
1
1
1
0
0
0
0
1
G1
0
0
1
1
0
0
1
1
0
0
1
1
0
GO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Level
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
-24.0
-25.5
-27.0
-28.5
-30.0
-31.5
-33.0
-34.5
dB
dB
dB
dB
dB
dB
dB
dB
Thble 5. AUX1 & AUX2 & LINE Mixer Gain
Thble 6. DAC & Loopback Attenuation
MIA3 MIA2 MIA1 MIAO
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
2
3
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Level
0.0 dB
-3.0 dB
-6.0 dB
-9.0 dB
-36.0
-39.0
-42.0
-45.0
dB
dB
dB
dB
0
1
2
3
4
5
6
7
SS1 SSO
0
0
0
1
1
0
1
1
ADC Input Multiplexer
Line
Auxiliary 1
Microphone
Line Output Loopback
Table 9. ADC Input Selector
DS111PP4
XTAL1
XTAL2
24.576 MHz 16.9344MHz
8.0 kHz
5.51 kHz
16.0 kHz
11.025 kHz
27.42 kHz
18.9 kHz
32.0 kHz
22.05 kHz
N/A
37.8 kHz
N/A
44.1 kHz
48.0 kHz
33.075 kHz
9.6 kHz
6.62 kHz
Table 8. Sample Frequency Select
Thble 7. Mono Mixer Attenuation
0
1
2
3
CFS2 CFS1 CFSO
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
1
0
1
2
3
5
6
FMT1 FMTO C/L
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
1
1
0
Audio Data Format
Linear, 8-bit unsigned
Il-Law, 8-bit
Linear, 16-bit, 2's C, LEnd.
A-Law, 8-bit
ADPCM, 4-bit IMA
Linear, 16-bit, 2'sC, BEnd.
Table 10. Audio Data Format
4-189
-____-_
.. ...-.
-. ..--_._.
CS4231
During initialization and power down, this register can NOT be written and is always read
10000000 (80h)
PUR
o- Right Channel Data
Playback I/O Data Register (R3, Write Only)
I
07
P07
06
P06
PD7-PDO
1 - Left Channel or Mono Data
05
04
03
02
01
00
P05 P04 P03 PD2 PD1 PD~
Playback Data Port. This is the control
register where playback data is
written during programmed 10 data
transfers.
I
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset when the current sample is sent to the DACs.
PUlL
06
05
04
03
02
01
1 - Upper Byte needed or any a-bit
mode
SER
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indicates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
be determined. However, the Alternate Feature Status register (124)
can indicate the exact source of the
error.
CRDY
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the hpst. This
bit would be used for direct programmed 1/0 data transfers.
00
ICUlL I CUR ICRDY I SER I PUlL I PUR IPRDY liNT I
INT
Interrupt Status: This indicates the
status of the internal interrupt logic
of the CS4231. This bit is cleared by
any write of any value to this register. The lEN bit of the Pin Control
register (110) determines whether
the state of this bit is reflected on
the IRQ pin of the CS4231.
Read States
o - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
o - Interrupt inactive
1 - Interrupt active
PRDY
CUR
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when direct programmed 1/0 data transfers
are desired.
o - Data still valid.
Do not overwrite.
1 - Data stale. Ready for next host
data write value.
Playback UpperlLower l;3yte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel.
o - Lower Byte needed
Status Register (R2, Read Only)
07
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel.
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel.
o - Right Channel Data
1 - Left Channel or Mono Data
CUlL
Capture UpperlLower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel.
o - Lower byte ready
1 - Upper byte or any a-bit ready
4-190
OS111PP4
----------------------
CS4231
Note on PRDY/CRDY: These two bits are designed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
Right ADC Input Control (ll)
07
06
04
03
02
01
00
RAG3-RAGO
Right ADC Gain. The least significant
bit represents + 1.5 dB, with
0000 = 0 dB. See Table 4.
RMGE
Right Mic Gain Enable: This bit
enables the 20 dB gain stage of the
right mic input signal, RMIC.
RSS1-RSSO
Right ADC Input Select. These bits
select the input source for the right
ADC channel.
Indirect Mapped Registers
These registers are accessed by placing the appropriate index in the Index Address register
(RO) and then accessing the Indexed Data register (R1). A detailed description of each indirect
register is given below. All reserved bits should
be written zero and may be 0 or 1 when read.
Note that indirect registers 16-31 are only available when the MODE2 bit in MODE and ID
register (112) is set.
05
IRSS1 RSSO I RMGE I res I RAG3 RAG2 RAG1RAGq
o - Right Line:
RLiNE
1 - Right Auxiliary 1: RAUX1
2 - Right Microphone: RMIC
3 - Right Line Out Loopback
This register's initial state after reset is: OOOxOOOO
Left Auxiliary #1 Input Control (12)
07
07
06
05
04
03
02
01
04
03
02
01
00
00
ILSS1 LSSO I LMGE I res I LAG3 LAG2 LAG1 LAGOI
LAG3-LAGO
Left ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 4.
LMGE
Left Mic Gain Enable: This bit enables
the 20 dB gain stage of the left mic
input signal, LMIC.
LSS1-LSSO
06 05
I LX1Mlres reslLX1G4 LX1G3 LX1G2 LX1G1 LX1GOI
Left ADC Input Control (10)
Left ADC Input Source Select. These
bits select the input source for the
left ADC channel.
LX1 G4-LX1 GO Left Auxiliary #1, LAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 5.
LX1 M
Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to
the mixer, is muted.
This register's initial state after reset is: 1xx01000.
Right Auxiliary #1 Input Control (13)
07
06 05
04
03
02
01
00
IRX1Mlres reslRX1G4 RX1G3 RX1G2 RX1G1 RX1GOI
o - Left Line: LLiNE
1 - Left Auxiliary 1: LAUX1
2 - Left Microphone: LMIC
3 - Left Line Output Loopback
This register's initial state after reset is: OOOxOOOO
RX1G4-RX1GO Right Auxiliary #1, RAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 5.
RX1M
Right Auxiliary #1 Mute. When set to
1, the right Auxiliary #1 input,
RAUX1, to the mixer, is muted.
This register's initial state after reset is: 1xx01000.
OS111PP4
4-191
-
.-_
..--_._.
__.._-_
...-.
CS4231
Left Auxiliary #2 Input Control (14)
07
06 05
04
03
02
Right DAC Output Control (17)
01
00
07
06
05
04
03
02
01
00
! LX2M! res res!LX2G4 LX2G3 LX2G2 LX2G1 LX2GO!
! RDM ! res! RDAS RDA4 RDA3 RDA2 RDA 1 RDAO!
LX2G4-LX2GO Left Auxiliary #2, LAUX2, Mix Gain.
The least significant bit represents
1.S dB, with 01000 = 0 dB. See Table S.
RDAS-RDAO
Right DAC Attenuator. The least significant bit represents -1.S dB, with
000000 = 0 dB. See Table 6.
RDM
Right DAC Mute. When set to 1, the
right DAC output to the mixer will be
muted.
LX2M
Left Auxiliary #2 Mute. When set to 1,
the left Auxiliary #2 input, LAUX2, to
the mixer, is muted.
This register's initial state after reset is: 1xOOOOOO.
This register's initial state after reset is: 1xx01000.
Fs and Playback Data Format (18)
Right Auxiliary #2 Input Control (15)
07
06 05
04
03
02
07
01
00
06
05
04
03
02
01
00
! FMT1! FMTO ! C/L! SIM ! CSF2 CFS1 CFSO !C2SL!
!RX2M! res res! RX2G4RX2G3 RX2G2 RX2G1 RX2GO!
C2SL
Clock 2 Source Select: This bit selects
the clock source used for the audio
sample rates for both capture and
playback.
CAUTION: See note below about
changing these bits
RX2G4-RX2GO Right Auxiliary #2, RAUX2, Mix Gain.
The least significant bit represents
1.S dB, with 01000 = 0 dB. See Table S.
RX2M
Right Auxiliary #2 Mute. When set to
1, the right Auxiliary #2 input,
RAUX2, to the mixer, is muted.
0- XTAL1
1 - XTAL2
Typically 24.S76 MHz
Typically 16.9344 MHz
This register's initial state after reset is: 1xx01 000.
CFS2-CFSO
Left DAC Output Control (16)
07
06
05
04
03
02
01
00
! LOM ! res! LDAS LDA4 LDA3 LOA2 LOA 1 LOAO!
LDAS-LDAO
Left DAC Attenuator. The least significant bit represents -1.S dB, with
000000 = 0 dB. See Table 6.
LDM
Left DAC Mute. When set to 1, the
left DAC output to the mixer will be
muted.
Clock Frequency Divide Select: These
bits select the audio sample frequency for both capture and
playback. The actual audio sample
frequency depends on which clock
source (C2SL) is selected and its frequency. Frequencies listed as N/A
are not available because their sample frequency violates the maximum
specifications; however, the decodes
are available and may be used with
crystals that do not violate the sample frequency specifications.
CAUTION: See note below about
changing bits
This register's initial state after reset is: 1xOOOOOO.
4-192
OS111PP4
.._-_
_
..--__
...
.-_
.-.-.
XTAl1
24.576 MHz
8.0 kHz
16.0 kHz
27.42 kHz
32.0 kHz
N/A
N/A
48.0 kHz
9.6 kHz
Divide
0-3072
1 - 1536
2 - 896
3 -768
4 - 448
5 - 384
6 - 512
7 - 2560
siiiil
CS4231
XTAl2
16.9344 MHz
5.51 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.62 kHz
Stereo/Mono Select: This bit determines how the audio data streams
are formatted. Selecting stereo will
result in alternating samples representing left and right audio channels.
Mono playback plays the same
audio sample on both channels.
Mono capture only captures data
from the left channel. In MODE 1,
this bit is used for both playback and
capture. In MODE 2, this bit is only
used for playback, and the capture
format is independently selected via
128.
Interface Configuration (19)
07
PEN
FMT1t FMTO ell
07
06 05
0
0
0
0
0
1
0
1
0
t
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
Linear, 8-bit unsigned
~-law,
8-bit companded
Linear, 16-bit two's
complement, Little Endian
A-law, 8-bit companded
RESERVED
ADPCM, 4-bit, IMA compatible
Linear, 16-bit two's
complement, Big Endian
RESERVED
05
04
03
02
01
00
Playback Enable. This bit enables
playback. The CS4231 will generate
PDRa and respond to PDAK signals
when this bit is enabled and
PPIO=O. If PPIO=1, PEN enables
PIO playback mode. PEN may be
set and reset without setting the
MCE bit.
o - Playback Disabled
(PDRa and
PIO inactive)
1 - Playback Enabled
CEN
0- Mono
1 - Stereo
The C/l, FMT1, and FMTO bits set the audio data
format as shown below. In MODE 1, FMT1, which is
forced low, FMTO, and ciL are used for both playback and capture. In MODE 2, these bits are only
used for playback, and the capture format is independently selected via register 128.
06
I CPIO I PPIO I res I res I ACAl I SDC I CEN I PEN I
Capture Enabled. This bit enables the
capture of data. The CS4231 will
generate CDRa and respond to
CDAK signals when CEN is enabled
and CPIO=O. If CPIO=1, CEN enables PIO capture mode. CEN may
be set and reset without setting the
MCE bit.
o - Capture disabled (CDRa and
PIO inactive)
1 - Capture enabled
SDC
Single DMA Channel: This bit will force
BOTH capture and playback DMA requests to occur on the Playback
DMA channel. The Capture DMA
CDRa pin will be zero. This bit
forces the CS4231 to use one DMA
channel. Should both capture and
playback be enabled in this mode,
only the playback will occur. See the
DMA section for further explanation.
o - Dual
DMA channel mode
1 - Single DMA channel mode
FMT1 is not available in MODE 1 (forced to 0).
This register's initial state after reset is: 0000000.
OS111PP4
4-193
-
_.-_..--_._.
__.._-_
...-.
ACAL
CS4231
This registers initial state after reset is: OOxxOxOx
o - No auto calibration
Error Status and Initialization (Ill, Read Only)
1 - Auto calibration enabled
PPIO
XCTL1-XCTLO XCTL Control: These bits are reflected
on the XCTL 1,0 pins of the CS4231.
Auto-Calibrate Enable: This bit determines whether the CS4231 performs
a calibration whenever the Mode
Change Enable (MCE) bit changes
from 1 to o. If the ACAL bit is not
set, previous calibration values are
used, and no calibration takes place.
o - TTL logic low on XCTL 1,0 pins
1 - TTL logic high on XCTL 1,0 pins
07
Playback PIO Enable: This bit determines whether the playback data is
transferred via DMA or PIO.
06
05
04
03
02
01
00
I COR PUR I ACII DRS IORR1 ORRO I ORL 1 ORLO I
ORL 1-0RLO
o - DMA transfers
Overrange Left Detect: These bits
determine the overrange on the left
ADC channel. These bits are updated on a sample by sample basis.
1 - PIO transfers
CPIO
0- Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
,Capture PIO Enable: This bit determines whether the capture data is
transferred via DMA or PIO.
o - DMA transfers
1 - PIO transfers
DRR1-0RRO
Note: This register, except bits CEN and PEN, can
only be written while in Mode Change Enable. See
section on MCE for more details.
0- Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
This register's initial state after reset is: 00xx1000
Pin Control (110)
07
06'
05
I XCTL 1 I XCTLO I res
lEN
04
03
02
01
00
I res IDEN I res I lEN I res
1 -Interrupt enabled
DEN
DRS
. Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will reflect the value of the INT bit of the
Status register (R2). The interrupt
pin is active high.
o - Interrupt disabled
Dither Enable: When set, triangular
pdf dither is added before truncating
the ADC 16-bit value to a-bit, unsigned data. Dither is only active in
the a-bit unsigned mode.
Overrange Right Detect: These bits
determine the overrange on the
Right ADC channel.
. DRQ Status: This bit indicates the
current'status of the PDRQ and
CDRQ pins of the CS4231.
o - CDRQ AND
PDRQ are presently
inactive
1 - CDRQ OR PDRQ are presently
active
ACI
Auto-calibrate In-Progress: This bit
indicates the state of calibration.
o - Calibration not in progress
1 - Calibration is in progress
o - Dither enabled
1 - Dither disabled
4-194
OS111PP4
----------------------
CS4231
Playback underrun: This bit is set
when playback data has not arrived
from the host in time to be played.
As a result, if OACZ = 0, the last
valid sample will be sent to the
OACs. This bit is set when an error
occurs and will not clear until the
Status register (R2) is read.
PUR
Capture overrun: This bit is set when
the capture data has not been read
by the host before the next sample
arrives. The old sample will not be
overwritten and the new sample will
be ignored. This bit is set when an
error condition occurs and will not
clear until the Status register(R2) is
read.
COR
Loopback Control (Il3)
07
06
ILBA5 LBA4
05
04
03
02
01
00
LBA3 LBA2 LBA1 LBAO I res I LBE I
Loopback Enable: When set to 1, the
AOC data is digitally mixed with data
sent to the OACs.
LBE
o - Loopback disabled
1 - Loopback enabled
LBA5-LBAO
Loopback Attenuation: These bits
determine the attenuation of the loopback from AOC to OAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 6.
This register's initial state after reset is: OOOOOOxO
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This
enables a polling host CPU to detect an error
condition while checking other status bits.
This register's initial state after reset is: 00000000
Playback Upper Base (Il4)
07
06
PUB?-PUBO
MODE and ID (Il2)
07
I
05
04
03
02
01
00
1 I MOOE21 res
06
res
103
102
101
100
103-100
Codec 10: These four bits indicate the
10 and initial revisions of the codec.
Further revisions are expanded in indirect register 25. These bits are
read only.
0001 - Revision "B". See Appendix
101 0 - Revision "C" on. See register
25 and the Appendix.
MOOE2
MODE 2: Enables the expanded mode
of the CS4231. Must be set to enable access to indirect registers
16-31 and their associated features.
0- MODE 1: CS4248 "look-alike".
1 - MODE 2: Expanded features.
This register's initial state after reset is: 10xx1010
05
04
03
02
01
00
IpUB? PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUBO I
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SOC, this
register is used for both the Playback and Capture Base registers.
This register's initial state after reset is: 0000000
Playback Lower Base (IlS)
07
06
05
04
03
02
01
00
IPLB? PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLBOI
PLB?-PLBO
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SOC, this register is
used for both the Playback and Capture Base registers.
This register's initial state after reset is: 00000000
OS111PP4
4-195
---.-------------------
CS4231
Alternate Feature Enable I (Il6)
Right Line Input Control (Il9)
07
06
05
04
03
02
01
I OLB
TE
res
res
res
res
res I DACzl
DACZ
00
OLB
06
05
04
RLM
Right Line Mute. When set to 1, the
Right Line input, RLlNE, to the
mixer, is muted.
This register's initial state after reset is: 1xx01000.
Timer Lower Byte (120)
07
06
05
04
03
02
01
00
I TL7
TL6
TL5
TL4
TL3
TL2
TL1
TLO I
TL7-TLO
Lower Timer Bits: This is the low order
byte of the 16-bit timer.
This register's initial state after reset is: 00000000.
This register's initial state after reset is: OOxxxxxO
Timer Upper Byte (121)
Alternate Feature Enable II (Il7)
I TU7
07
07
06
05
04
03
02
01
I res
res
res
res
res
res
res I HPF I
06
05
04
03
02
01
TU6
TU5
TU4
TU3
TU2
TU1
TU7-TUO
C2SL = 1 - divide XTAL2 by 168
(16.9344 MHz - 9.92 j.ls)
This register's initial state after reset is: xxxxxxxO.
Left Line Input Control (Il8)
04
Upper Timer Bits: This is the high
order byte of the 16-bit timer. The
time base is determined by the clock
source selected.
C2SL = 0 - 'divide XTAL 1 by 245
(24.576 MHz - 9.969 j.ls)
0- disabled
1 - enabled
05
00
TUO I
00
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset of O.
06
00
1 - Go to center scale
o - Hold previous valid sample
1 - Full scale of 2.8 Vpp (0 dB)
07
01
Right Line, RLlNE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 =0 dB. See Table 5.
o - Full scale of 2 Vpp (-3 dB)
ILLM I res
02
RLG4-RLGO
Output Level Bit: Sets the analog output level. When clear, analog line
outputs are attenuated 3dB.
HPF
03
res IRLG4 RLG3 RLG2 RLG1 RLGol
DAC Zero: This bit will force the output of the playback channel to AC
zero when an underrun error occurs
Timer Enable: This bit, when set, will
enable the timer to run and interrupt
the host at the specified frequency
in the timer registers.
TE
07
I RLM I res
03
02
01
00
res I LLG4 LLG3 LLG2 LLG1 LLGO I
LLG4-LLGO
Left Line, LLlNE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 5.
LLM
Left Line Mute. When set to 1, the left
Line input, LLlNE, to the mixer, is
muted.
This register's initial state after reset is: 00000000
RESERVED (122)
07
06
05
04
03
02
01
00
I res
res
res
res
res
res
res
res
This register's initial state after reset is: xxxxxxxx
RESERVED (123)
07
06
05
04
03
02
01
00
I res
res
res
res
res
res
res
res
This register's initial state after reset is: xxxxxxxx
This register's initial state after reset is: 1xx01000.
4-196
OS111PP4
----------------------
CS4231
Alternate Feature Status (124)
07
I
res
06
I
TI
I
05
CI
I
04
PI
03
Version / ID (125)
02
I CU I CO I
01
00
PO
PU
PU
Playback Underrun: This bit, when set,
indicates that the DAC has run out
of data and a sample has been
missed.
PO
Playback Overrun: This bit, when set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
CO
CU
Capture Overrun: This bit, when set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case the bit is set
and the new sample is discarded.
Capture Underrun: This bit indicates
that the host has read more data out
. of the FIFO than it contained. In this
condition, the bit is set and the last
valid byte is read by the host.
PI
Playback Interrupt: This bit indicates
that an interrupt is pending from the
playback DMA count registers.
CI
Capture Interrupt: This bit indicates
that an interrupt is pending from the
record DMA count registers.
TI
Timer Interrupt: This bit indicates that
an interrupt is pending from the
timer count registers
The PI, CI, and TI bits are reset by writing a "0" to
the particular interrupt bit or by writing any value to
the Status register (R2).
This register's initial state after reset is: xOOOOOOO
07
I V2
06
05
04
03
V1
VO
res
res
V2-VO
02
01
00
CID2 CID1 CIDO
I
Version number. As enhancements are
made to the CS4231, the version
number is changed so software can
distinguish between the different versions.
100 - Revision C, D, & E. This Data
Sheet
CID2-CIDO
Chip Identification. Distinguishes
between this chip and future chips
that support this register set.
000 - CS4231
This register's initial state after reset is: OOOxxOOO
Mono Input & Output Control (126)
07
06
05
I MIM IMOM I res
04
res
03
I MIA3
02
01
00
MIA2 MIA1 MIAO
I
MIA3-MIAO
Mono Input Attenuation. MIAO is the
least significant bit and represents
3 dB attenuation, with 0000 = 0 dB.
See Table 7.
MOM
Mono Output Mute. The MOM bit will
mute the mono mix output, MOUT.
This mute is independent of the line
output mute.
0- no mute
1 - mute
MIM
Mono Input Mute. This bit controls the
mute function on the mono input,
MIN. The mono input provides mix
for the "beeper" function in most personal computers.
0- no mute
1 - muted
This register's initial state after reset is: 00xx0011.
OS111PP4
4·197
CS4231
RESERVED (127)
Capture Lower Base (131)
07
06
05
04
03
02
01
00
I res
res
res
res
res
res
res
res
This register's initial state after reset is: xxxxxxxx
06
05
04
03
02
01
00
I FMT1 I FMTO I C/l I SIM I res
res
res
res
StereolMono Select: This bit determines how the capture audio data
stream is formatted. Selecting stereo
will result with alternating samples
representing left and right audio
channels. Selecting mono only captures data from the left audio
channel.
S/M
0- Mono
1 - Stereo
The ciL, FMT1, and FMTO bits.set the capture data
format in MODE 2. See Table 10 or register 18 for
the bit settings and data formats. The capture data
format can be different thatthe playback data format; however, the sample frequency must be the
same and is set in 18. MCE must be set to modify
this register.
This register's initial state after reset is: OOOOxxxx
RESERVED (129)
07
06
05
04
03
02
01
00
I res
res
res
res
res
res
res
res
This register's initial state after reset is: xxxxxxxx
06
05
04
03
02
01
04
03
02
01
00
lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 1S-bit
Capture Base register. Reads from
this register returns the same value
which was written.
This register's initial state after reset is: 00000000
GROUNDING AND LAYOUT
Figure 16 is a suggested layout for the CS4231.
Similar to other Crystal codecs, it is recommended that the device be located on a separate
analog ground plane. With the CS4231 's parallel
data interface, however, optimum performance is
achieved by extending the digital· ground plane
across pins 65 through. 68 and pins 1 through 8.
Pins 2 and 8 are grounds for the data bus and
should be electrically connected to the digital
ground plane which will minimize the effects of
the bus interface due to transient currents during
bus switching. Figure 17 shows the recommended positioning of the decoupling capacitors.
The capacitors must be on the same layer as, and
close to, the CS4231. The vias shown go
through to the ground plane layer. Vias, power
supply traces, and VREF traces should be as
large as possible to minimize the impedance.
00
ICUB7 CUBS CUB5 CUB4 CUB3 CUB2 CUB1 CUBol
CUB7-CUBO
05
Schematic &Layout Review Service
Capture Upper Base (130)
07
06
ClB7 -ClBO
Capture Data Format (128)
07
07
IClB7 ClBS ClB5 ClB4 ClB3 ClB2 ClB1 ClBOI
Confirm Optimum
Schematic & Layout
Capture Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 1S-bit
Capture Base register. Reads from
this this register returns the same
value that was written.
This register's initial state after reset is: 0000000
4-198
OS111PP4
_.-_..--_-....._-...._.-.
CS4231
,,1/8'
11
Digital
Ground
Plane
Analog
_:
Pins
Ground
Connection
. : AnilciVi
+5V
Ferrite
Bead
I.
Ground'
pilrlll;
•1.
CPU & Digital
Logic
.1•
Codee
digital
signals
.1
Codee
analog signals
&
Components
Figure 16. Suggested Layout Guideline
r - - - - - - - - - - - - - - - - - - --I
i
C)
OOOOOOO!OOOOOOOOO
10
1 0
IL
::l.
BUS VO
'3. 1
;1
~
-
'".;
0
BUS VO
~9
0
0
0
0
CD
0
0
0
i
0
0
1'3.
~ ~.~
. .••
~'i~'VA
,O!
"0'
'0\0
~
~'"~';:g
0
0
0
::'0
0
C)
OJ
'0
1'3.
o
I;
C)
o
0000000000
b<::-_/:_'' ---",Q - O=-.-----::g'" - - - - -
~
1
1
1
~
0.1 I!F
VO
VO
Figure 17. Recommended Decoupling Capacitor PositiodS
DS111PP4
4-199
-----------.----------COMPATIBILITY WITH AD1848
The CS4231 is compatible with the AD1848 rev.
J silicon and the CS4248 in terms of the applications circuit. The AD1848 rev K requires 0.1 IlF
capacitors (not 1000 pF) on pins 26 and 31. The
CS4231 requires 1000 pF NPO-type capacitors
on filter pins 26 and 31 (not 0.1 IlF). To achieve
compatibility with the CS4231:
1. Correct spacing of pads will ensure that
either 0.1 IlF capacitors (for the AD 1848
rev K) or 1000 pF NPO capacitors (for
the CS4248) may be installed.
2. The CS4231 does not require the input
anti-aliasing filters included as an input
RIC for the AD1848 (5.1kQ and 560 pF).
The additional RIC's can be used with
the CS4231 if desired, with no degradation in performance.
CS4231
8. The AD1848 does not contain the selectable dither (DEN, nO)
9. The AD1848 is not available in a 100-pin
TQFP package.
ADCIDAC FILTER RESPONSE PLOTS
Figures 18 through 23 show the overall frequency response, passband ripple, and transition
band for the CS4231 ADCs and DACs. Figure 24 shows the DACs' deviation from linear
phase. Since the CS4231 scales filter response
based on sample frequency selected, all frequency response plots x-axis' are shown from 0
to 1 where 1 is equivalent to Fs. Therefore, for
any given sample frequency, multiply the x-axis
values by the sample frequency selected to get
the actual frequency.
3. Although optimum performance is
achieved using the ground plane shown
in Figure 16, any ground plane scheme
that achieves acceptable performance
with the AD1848 should work with the
CS4231.
4. The AD1848 needs extra power and
ground pins. The power pins (VDD) are
pins 24, 45, and 54. The ground pins
(GNDD) are pins 25 and 44. The CS4231
PLCC package does not use these pins
and the appropriate power/ground connections can be made.
5. The Mono InIMono Out pins do not exist
on the AD1848.
6. The ADl848 does not contain 16 rnA bus
drivers. Therefore, buffers must be used.
7. MODE 2 and all associated features do
not exist on the AD1848.
4-200
DS111PP4
----------------------
CS4231
10
o
'\
-10
\
-20
\
~ -30
\
~ -40
\
:E!
~-50
::. -60
-70
~I\ /\
1\
'IV V If"\I III II
-80
-90
1/\ "
II
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
I
0.7
I II I
0.8
0.9
1.0
-r.....
.......
Input Frequency (xFs)
Figure 18. ADC Filter Response.
0.2
0.1
1/
1'\
\
-0.0
-0.1
m
~-0.2
~
I\.
I
\. ./
o
1/\
"'\
"
-10
-20
~-30
m
:!'!.-40
"'-
" '\
-50
g> -60
~
-0.5
:;; -70
-0.6
-80
-0.7
-90
-O.B
0.00 0.05
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (xFs)
Figure 19. ADC Passband Ripple.
DS111PP4
1\
\
1
1.
V \I
\l
b
,
V
U
-100
0040 0.43 0046 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (xFs)
Figure 20. ADC Transition Band.
4-201
---------------------10
0.2
o
0.1
'\
-10
iO -20
-30
{l -40
::J
'2
g>
-50
-60
-0.0
~
\
~
:::i:
CS4231
-60
:::i: -70
-80
-90
-0.7
-0.8
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (xFs)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (xFs)
-
Figure 22. DAC Passband Ripple.
2.5
t-..
2.0
..........
1.5
" \.,
I
Ui'
1.0
(J)
1
~ 0.5
(J)
:!:!. 0.0
1\
(J)
gj -0.5
\
.s:::
\ 1'\ J-,.
" \I
V
-100
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (xFs)
Figure 23. DAC Transition Band.
4·202
f\
~-0.3
Figure 21. DAC Filter Response.
~ -50
'c
\.
g>-0.4
0.0 0.1
~ -40
\. /
v",
::;; -0.5
-100
iO -30
./
,
~-0.2
\
\
-80
-90
-20
\
iii'-0.1
-70
-10
1/
I\.
a. -1.0
-1.5
-2.0
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (xFs)
Figure 24. DAC Phase Response.
DS111PP4
.._-_
_.-_..--_._.
__
...-.
CS4231
PIN DESCRIPTIONS
RFILT
CCCCC>CCCC
g~~3:
00>0>
C')C\I..-OO> 0> 0> 0> 0..C\lC\IC')C')
C')
C')
WOOW
!:i
Z--Z
-:E:E~a:...I::1
DS111PP4
~Ze:
z ...
O ... NMCJCo::rIt)CO .....
0
AO
CDAK
CDRQ
PDAK
PDRQ
VD3
DGND3
XTAL11
XTAL10
VD4
DGND4
XTAL21
XTAL20
PDWN
...C
N
C
ZN
... CJC
c(C>
u::
...I
LO
C')
LL.
W
a:
>
vvvvvvvvvv
u:: c<~S~><~
z»z~~oo~~
W
a:
>
CJ
c(
CJ~~...Ia:c(c(
c(
a: a:
4-203
---------------------VD1
DGND1
D3
D2
D1
DO
VD2
DGND2
A1
AO
CDAK
CDRQ
PDAK
PDRQ
VD3
DGND3
XTAL11
XTAL10 ------;=1
VD4---~
DGND4
XTAL21
XTAL20
PDWN
* NC (Voo)
* NC (GNDD)
RFILT
RLINE
RMIC
LMIC
LLINE
LFILT
VREF
VREFI
AGND1
CS4231
CS4231
68-pin
PLCC
(L)
Top View
* see Power Supply section
D4
D5
D6
D7
DGND8
DBEN
DBDIR
WR
RD
CS
XCTL1
IRQ
XCTLO
TEST
* NC (Voo)
DGND7
p---NC
NC
NC
NC
NC
MOUT
MIN
* NC (Voo)
* NC (GNDD)
RAUX2
RAUX1
ROUT
LOUT
LAUX1
LAUX2
AGND2
VA2
VA1
Parallel Bus Interface Pins
CDRQ - Capture Data Request, Output, Pin 12 (L), Pin 7 (Q).
The assertion of this signal indicates that the codec has a captured audio sample ready for
transfer. This signal will remain asserted until all the bytes from the capture buffer have been
transferred.
CDAK - Capture Data Acknowledge, Input, Pin 11 (L), Pin 6 (Q).
The assertion of this active low signal indicates that the RD cycle occurring is a DMA read
from the capture buffer.
PDRQ - Playback Data Request, Output, Pin 14 (L), Pin 9 (Q).
The assertion of this signal indicates that the codec is ready for more. playback data. The signal
will remain asserted until the bytes needed for a playback sample have been transferred.
4-204
DS111PP4
----------------------
CS4231
PDAK - Playback Data Acknowledge, Input, Pin 13 (L), Pin 8 (Q).
The assertion of this active low signal indicates that the WR cycle occurring is a DMA write to
the playback buffer.
A< 1:0> - Address Bus, Input, Pin 9, 10 (L), Pin 100, 1 (Q).
These address pins are read by the codec interface logic during an I/O cycle access. The state of
these address lines determines which register (RO-R3) is accessed.
RD - Read Strobe, Input, Pin 60 (L), Pin 75 (Q).
This signal defines a read cycle to the codec. The cycle may be an I/O cycle read, or the cycle
could be a read from the codec's DMA sample registers.
WR - Write Strobe, Input, Pin 61 (L), Pin 76 (Q).
This signal indicates a write cycle to the codec. The cycle may be an I/O cycle write, or the
cycle could be a write to the codec's DMA sample registers.
CS - Chip Select, Input, Pin 59 (L), Pin 74 (Q).
The codec will not respond to any I/O cycle accesses unless this signal is active. This signal is
ignored during DMA transfers.
D< 7:0> - Data Bus, Input/Output, Pin 65-68, 3-6 (L), Pin 84-87, 90-93 (Q).
These signals are used to transfer data to and from the CS4248.
DBEN - Data Bus Enable, Output, Pin 63 (L), Pin 78 (Q).
This pin indicates that the bus drivers attached to the CS4248 should be enabled. This signal is
normally high.
DBDIR - Data Bus Direction, Output, Pin 62 (L), Pin 77 (Q).
This pin indicates the direction of the data bus transceiver. High points to the CS4231, low
points to the host bus. This signal is normally high.
IRQ - Host Interrupt Pin, Output, Pin 57 (L), Pin 72 (Q).
This signal is used to notify the host of events which need servicing.
Analog Inputs
LLINE - Left Line Input, Pin 30 (L), Pin 31 (Q).
Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. The
LINE inputs may be selected for AID conversion via the input multiplexer (10). A
programmable gain block (118) also allows routing to the mixer.
RLINE - Right Line Input, Pin 27 (L), Pin 28 (Q).
Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. The
LINE inputs may be selected for AID conversion via the input multiplexer (11). A
programmable gain block (119) also allows routing to the mixer.
DS111PP4
4-205
-
.-_
..--_._.
_-.._-_
...-.
CS4231
LMIC - Left Mic Input, Pin 29 (L), Pin 30 (Q).
Microphone input for the Left MIC channel, centered around VREF. This signal can be either
1 VRMS (LMGE = 0) or 0.1 VRMS (LMGE = 1). The MIC inputs may be selected for NO
conversion via the input multiplexer (10).
RMIC - Right Mic Input, Pin 28 (L), Pin 29 (Q).
Microphone input for the Right MIC channel, centered around VREF. This signal can be either
1 VRMS (RMGE = 0) or 0.1 VRMS (RMGE = 1). The MIC inputs may be selected for NO
conversion via the input multiplexer (11).
LAUXI - Left Auxiliary #1 Input, Pin 39 (L), Pin 45 (Q)~
Nominally 1 VRMS max analog input for the Left AUXI channel, centered around VREF. The
AUXI inputs may be selected for AID conversion via the input multiplexer (10). A
programmable gain block (12) also allows routing to the output mixer.
RAUXI - Right Auxiliary #1 Input, Pin 42 (L), Pin 48 (Q).
Nominally 1 VRMS max analog input for the Right AUXI channel, centered around VREF.
The AUXI inputs may be selected for NO conversion via the input multiplexer (11). A
programmable gain block (13) also allows routing to the output mixer.
LAUX2 - Left Auxiliary #2 Input, Pin 38 (L), Pin 44 (Q).
Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A
programmable gain block (14) allows routing of the AUX2 channels into the output mixer.
RAUX2 - Right Auxiliary #2 Input, Pin 43 (L), Pin 49 (Q).
Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A
programmable gain block (15) allows routing of the AUX2 channels into the output mixer.
MIN - Mono Input, Pin 46 (L), Pin 56 (Q).
Nominally 1 VRMS max analog input, centered around VREF, that goes through a
programmable gain stage (126) into both channels of the mixer. This is a general purpose mono
analog input that is normally used to mix the typical "beeper" signal on most computers into the
audio system.
Analog Outputs
LOUT - Left Line Level Output, Pin 40 (L), Pin 46 (Q).
Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around
VREF when aLB = 1 (116). When aLB = 0, the output is attenuated 3 dB and is a maximum
of 0.707 VRMS.
ROUT - Right Line Level Output, Pin 41 (L), Pin 47 (Q).
Analog output from the mixer for the right channel. Nominally 1 VRMS max centered around
VREF when aLB = 1 (116). When aLB = 0, the output is attenuated 3 dB and is a maximum
of 0.707 VRMS.
4-206
DS111PP4
_.-_..--_._.
__.._-_
...-.
CS4231
MOUT - Mono Output, Pin 47 (L), Pin 57 (Q).
When OLB=1 (116), MOUT is nominally 1 VRMS max analog output, centered around VREF.
When OLB=O, the maximum output voltage is 3 dB lower, 0.707 VRMS. This output is a
summed analog output from both the left and right output channels of the mixer. MOUT
typically is connected to a speaker driver that drives the internal speaker in most computers.
Independantly mutable via MOM in 126.
Miscellaneous
XTALlI - Crystal #1 Input, Pin 17 (L), Pin 12 (Q).
This pin will accept either a crystal with the other pin attached to XTALl 0 or an external
CMOS clock. XTALI must have a crystal or clock source attached for proper operation. The
standard crystal frequency is 24.576 MHz although other frequencies can be used. The crystal
should be designed for fundamental mode, parallel resonance operation.
XTALlO - Crystal #1 Output, Pin 18 (L), Pin 13 (Q).
This pin is used for a crystal placed between this pin and XTALlI.
XTAL2I - Crystal #2 Input, Pin 21 (L), Pin 16 (Q).
If a second crystal is used, is should be placed between this pin and XTAL20. The standard
crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal should
be designed for fundamental mode, parallel resonance operation.
XTAL20 - Crystal #2 Output, Pin 22 (L), Pin 17 (Q).
This pin is used for a crystal placed between this pin and XTAL2I.
PDWN - Power Down, Input, Pin 23 (L), Pin 18 (Q).
Places CS4231 in lowest power consumption mode. All sections of the CS4231, except the
digital bus interface which reads 80h, are shut down and consuming minimal power. The
CS4231 is in power down mode when this pin is logic low.
XCTLO, XCTLl - External Control, Output, Pin 56, 58 (L), Pin 71, 73 (Q).
These signals are controlled by the register bits XCTLO and XCTLl in register 110. They can
be used to control external logic via TTL levels.
VREF - Voltage Reference, Output, Pin 32 (L), Pin 35 (Q).
All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This
pin may be used to level shift external circuitry, although any AC loads should be buffered.
High internal-gain microphone inputs can be slightly improved by placing a 10IlF capacitor on
VREF.
VREFI - Voltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q).
Voltage reference used internal to the CS4231 must have a 0.1 Ilf + 10 IlF capacitor with short
fat traces to attach to this pin. No other connections should be made to this pin.
DS111PP4
4-207
-
-_
--------... _----------
CS4231
LFILT - Left Channel Antialias Filter Input, Pin 31 (L), Pin 33 (Q).
This pin needs 1000 pF NPOcapacitor attached and tied to analog ground.
RFILT - Right Channel Antialias Filter Input, Pin 26 (L), Pin 25 (Q).
This pin needs 1000 pF NPO capacitor attached and tied to analog ground.
TEST - Test, Pin 55 (L), Pin 70 (Q).
This pin must be tied to ground for proper operation.
Power Supplies
VAl, VA2 - Analog Supply Voltage, Pin 35, 36 (L), Pin 41, 42 (Q).
Supply to the analog section of the codec.
AGND1, AGND2 - Analog Ground, Pin 34, 37 (L), Pin 40, 43 (Q).
Ground reference to the analog section of the codec. Intemally, these pins are connected to the
substrate as are DGND3/417/8; therefore, optimum layout is achieved with the AGND pins on
the same ground plane as DGND3/417/8 (see Figure 17). However, other ground arrangements
should yield adequate results.
VD1, VD2 - Digital Supply Voltage, Pin 1, 7 (L), Pin 88, 98 (Q).
Digital supply for the parallel data bus section of the codec.
VD3, VD4 - Digital Supply Voltage, Pin 15, 19 (L), Pin 10, 14 (Q).
Digital supply for the internal digital section of the codec (except for the parallel data bus).
DGND1, DGND2 - Digital Ground, Pin 2, 8 (L), Pin 89, 99 (Q).
Digital ground reference for the parallel data bus section of the codec. These pins are isolated
from the other digital grounds and should be connected to the digital ground section of the
board (see Figure 17).
DGND3, DGND4, DGND7, DGND8 - Digital Ground, Pin 16,20,53, 64(L), Pin 11, 15,69, 79(Q)
Digital ground reference for the internal digital section of the codec (except the parallel data
bus). These pins are connected to the substrate of the die as are the AGND pins. Optimum
layout is achieved by placing DGND3/417/8 on the analog ground plane with the AGND pins as
shown in Figure 17. However, other ground arrangements should yield adequate results.
* NC (VDD) - No Connect, Pins 24, 45, 54 (L)
These pins are no connects for the CS4231. When compatibility with the AD1848 is desired,
these pins should be connected to the digital power supply. For other compatibility issues, see
the Compatibility with AD1848 section of the data sheet.
* NC (GNDD) - No Connect, Pins 25, 44 (L)
These pins are no connects for the CS4231. When compatibility with the AD1848 is desired,
these pins should be connected to digital ground. For other compatibility issues, see the
Compatibility with AD1848 section of the data sheet.
4-208
DS111PP4
----------------------
CS4231
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.
Total Dynamic Range
TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is
measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e.
attenuation bits for the DACs at full attenuation). Units in dB.
Instantaneous Dynamic Range
IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the harmonic distortion components to insignificance when
compared to the noise. Units in dB.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the
test signal.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
o dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input
code.
DS111PP4
4-209
-----------------.,----
CS4231
TABLE OF CONTENTS:
CS4231 GENERAL DESCRIPTION ................................................................. .4-174
Enhanced Functions (MODE 2) .................................................................. 4-174
Mixer Attenuation Control on Line Input.. ........................................ .4-174
ANALOG HARDWARE DESCRIPTION ......................................................... .4-174
Analog Inputs ..............................................................................................4-174
Line-Level Inputs plus MPC Mixer .................................................. .4-174
Microphone Level Inputs .......... ,..... ,................................................... 4~175
Mono Input with Attenuation and Mute ........................... ~ ................ .4-175
Analog Outputs ...................... ,.......... ~ ......................................................... .4-175
Mono Output with Mute Control.. ..................................................... .4-175
Miscellaneous Analog Signals .................................................................... .4-176
DIGITAL HARDWARE DESCRIPTION ......................................................... ..4-176
Parallel Data Interface .................................................................................4-176
FIFOs .......................................................................................................... .4-176
High Current Data Bus drivers ...................................................................4-177
PIO Registers Interface .............................................................................. .4-177
DMA Interface ............................................................................................ .4-177
Dual DMA Channel Mode .......................................................................... 4-178
Single DMA Channel (SDC) Mode .................................................... 4-178
Miscellaneous Signals ................................................................................ .4-178
Crystals/Clocks ................................................................................... .4-178
Power Down - PDWN ....................................................................... .4-179
DBENIDBDIR ................................................................................... .4-179
SOFTWARE DESCRIPTION ............................................................................ .4-179
Procedures .................................................................................................. .4-179
Power-Down and Initialization .......................................................... .4-179
Auto Calibration ................................................................................. .4-179
Changing Sampling Rate ................................................................... .4-180
Audio Data Formats ....................................................................................4-180
16-bit Signed ...................................................................................... .4-183
8-bit Unsigned .................................................................................... .4-183
8-bit Companded ........................ ;.~ ..................................................... .4-183
ADPCM Compression/Decompression ..............................................4-183
DMA Registers ........................................................................................... .4-184
Playback DMA Registers ................................................................... .4-184
Capture DMA Registers ..................................................................... .4-184
Digital Loopback ........................................................................................ .4-184
Timer Registers ........................................................................................... .4-185
Interrupts ..................................................................................................... .4-185
Error Conditions ......................................................................................... .4-185
4-210
DS111PP4
----------------------
CS4231
CS4231 REGISTER MAPPING ........................................................................ .4-186
Physical Mapping ....................................................................................... .4-186
Index Address Register (RO) .............................................................. .4-187
Index Data Register (Rl) ................................................................... .4-187
Capture 110 Data Register (R3, Read Only) .................................... ..4-187
Playback 110 Data Register (R3, Write Only) .................................... 4-190
Status Register (R2, Read Only) ....................................................... .4-190
Indirect Mapped Registers .......................................................................... .4-191
Left ADC Input Control (10) .............................................................. .4-191
Right ADC Input Control (11) .......................................................... ..4-191
Left Auxiliary #1 Input Control (12) .................................................. .4-191
Right Auxiliary #1 Input Control (I3) .............................................. ..4-191
Left Auxiliary #2 Input Control (14) .................................................. .4-192
Right Auxiliary #2 Input Control (15) .............................................. ..4-192
Left DAC Output Control (16) .......................................................... ..4-192
Right DAC Output Control (17) ........................................................ .4-192
Fs and Playback Data Format (18) ...................................................... 4-192
Interface Configuration (19) ............................................................... .4-193
Pin Control (110) ................................................................................ .4-194
Error Status and Initialization (Ill, Read Only) ............................... .4-194
MODE and ID (112) .......................................................................... .4-195
Loopback Control (113) ..................................................................... .4-195
Playback Upper Base (114) ................................................................ .4-195
Playback Lower Base (115) .............................................................. ..4-195
Alternate Feature Enable I (116) ........................................................ .4-196
Alternate Feature Enable II (117) ....................................................... .4-196
Left Line Input Control (118) ............................................................ .4-196
Right Line Input Control (119) .......................................................... .4-196
Timer Lower Byte (120) ..................................................................... .4-196
Timer Upper Byte (121) ...................................................................... 4-196
Alternate Feature Status (124) ............................................................ .4-197
Version! Chip ID (125) ....................................................................... .4-197
Mono Input & Output Control (126) ................................................ ..4-197
Capture Data Format (128) ................................................................. .4-198
Capture Upper Base (I30) .................................................................. .4-198
Capture Lower Base (I31) ................................................................ ..4-198
GROUNDING AND LAyOUT .......................................................................... .4-198
COMPATffiILITY WITH AD1848 .................................................................... .4-200
ADCIDAC FILTER RESPONSE PLOTS .......................................................... .4-200
PIN DESCRIPTIONS ......................................................................................... .4-203
PARAMETER DEFINITIONS ........................................................................... .4-209
DS111PP4
4-211
....... ..........
~
".,,,.,~
..,
Semiconductor Corporation
1 CDB4231 14248 .1
~..,~~
.CS4231/4248 Evaluation Board
Features
General Description
The COB4231/4248 evaluation board supports all the
features of the CS4231 and CS4248. The CS4231 is
an enhanced version, and is backwards compatible
with the CS4248. The OMA, IRQ, and base address
are all selectable via: on-board jumpers. Four stereo
jacks provide MIC in, AUX1 in, LINE in, and
Line/Headphone out· In addition, on-board headers
provide an internal analog CD-ROM interface via the
AUX2 inputs, and support for the mono in and mono
out capabilities of the CS4231.
• PC ISA Plug-In Card
• Mono In / Mono Out Support
• Microphone Pre-Amplifier
• Line Out / Headphone Circuit
Software that runs under Microsoft Windows™ 3.1 is
also provided along with an extensive diagnostics program.
• Microsoft Windows™ 3.1 Software
Support
ORDERING INFORMATION: COB4231, COB4248
CDROM IN (Aux2)
Base Address
A= 1/2
CS4231/
CS4248
Digital
Patch
Line In
A=4
INT
00
00
00
00
00
00
00
00
00
00
A= 1/2
DMA
DMA
PLAY CAPTURE
00
00
Mic In
Aux1 In
A= 1/2
00
00
A=2
Line/Headphone Out
Area
PC Bus
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
NOV '93
OS11lOB4
4·212
---------------------GENERAL INFORMATION
The CDB423114248 is designed to provide an
easy platform for evaluating the performance of
the CS4231 or CS4248 Parallel Interface, Multimedia Audio Codec in a PC environment.
Software that operates under the Microsoft Windows™ environment is also included with
applets that control all the CS4231 or CS4248
features. This software also provides full Windows™ 3.1 compatibility with extensions to
utilize the more powerful CS4231 features in
custom code.
Four stereo jacks, externally accessible, allow
connection to Microphone inputs, Auxiliary 1 inputs, Line inputs, and Line/Headphone outputs.
Headers allow internal connections to a CDROM analog output (using the codec's
Auxiliary 2 inputs), and speaker pass-through
and control via the SPEAKER IN (Mono In) and
SPEAKER OUT (Mono Out) headers.
Additional headers on the board allow the setting
of the Base Address, DMA channel, and IRQ for
the CS4231. The factory default for the
CDB4231 is base address 530h, DMA playback
channel 3, DMA capture channel 0 and IRQ 7.
The CDB4248 is the same with the exception of
the DMA capture header which is not used and
has both shorting jumpers removed.
CDB4231/4248
a gain of 4 dB providing a maximum full scale
of 91 mV (with the 20 dB boost inside the codec
enabled). For microphones with larger signals,
the 20 dB gain block inside the codec can be
disabled in software (the "Boost" button in the
input applet). The microphone circuit is designed
for single-ended microphones which are the
most common type available. The J35 header,
close to the mic input jack allows selection of a
stereo microphone when the jumper is in the'S'
position, or mono input where the jumper is in
the 'M' position. In the mono position, a mono
mic input would go to both the left and right mic
input pins on the codec.
The second input jack is Ax1 I, Auxiliary 1 In,
(Figure 1) which has an input impedance of approximately 10 kn with a maximum full scale
into the Ax1 I jack of 2 VRMS.
The third stereo input jack is Line I, Line In,
(Figure 4) which also has a maximum full scale
of 2 VRMS and provides a typical audio input
impedance of 47 kn.
The software must be configured to match the
settings on the evaluation board headers for
proper operation.
An internal header, labeled COROM IN (AUX2),
(Figure 4) may be used by any internal device
for analog mixing into the codec's output mixer
via the Auxiliary 2 inputs, AUX2. Since the
AUX2 inputs don't have a path to the ADCs,
when nothing is plugged into the Line I jack, the
analog contained on the COROM IN header is
summed into the Line inputs of the codec as
well as the AUX2 inputs. When a plug is inserted into the Line I jack, the COROM IN header
is disconnected from the Line inputs (but is still
connected to the AUX2 inputs).
STEREO ANALOG INPUTS
STEREO ANALOG OUTPUTS
Three of the four external 1/8" stereo jacks are
for analog inputs. The stereo Mic I, Microphone
Input, (Figure 2) contains an op-amp buffer with
The CDB4231/4248 contains one stereo analog
output labeled Ln/Hp 0, Line/Headphone Out,
Windows is a registered trademark of Microsoft Corporation
OS111084
4-213
-
-----------.--.--------(Figure 5) with a maximum full-scale output of
2 VRMS. This output provides a high-quality line
out for use with external power amps or other
equipment containing line-level inputs. It is also
designed to drive headphones directly with exceptional quality.
MONO INPUT AND OUTPUT
The CS4231 contains a MIN (mono in) pin and
a MOUT (mono out) pin that are typically
placed in between the internal PC speaker and
the beeper chip. The CDB4231 comes with a cable that should be connected between the PC
beeper chip and the SPEAKER IN header (Figure 1) on the CDB4231 board. The cable wire,
pin 1, should be placed on pin 1 of the
SPEAKER IN header and pin 1 of the beeper
header. If the PC beeps do not mix into the
codec, try reversing the beeper header connector.
This connects the beeper to the MIN pin on the
CS4231 and allows traditional PC beeps to be
mixed into the audio path.
The SPEAKER OUT header (Figure 3) should be
connected to the PC speaker. The MOUT pin on
the CS4231 is a mix of both left and right channels and has an independent software mute. The
quality of this circuit is limited to the quality of
the speaker used. Much higher fidelity can be
achieved by using a higher quality speaker.
Since the CS4248 does not have MIN and
MOUT pins, the CDB4248 board does not pt:ovide a cable, and the SPEAKER IN and SPEAKER
OUT headers are non-functional.
BASE ADDRESS
The base address is set using header J18 (Figure 6) and must match the software selected base
address. The CDB423114248 evaluation board
uses 8 I/O addresses. The first four are used to
read the board ID of 04. Writes to the first four
4·214
CDB4231/4248
addresses are ignored. The board ID is output
from the ID31 PLD and indicates that the board
is Windows Sound System, WSS, compatible
(see limitations listed in the SOFTWARE COMPATIBIllTY section).
The second four addresses are used by the
codec. The default for the evaluation board and
the software is 530h - no jumpers. The following
table lists the available base addresses (along
with the associated codec address), with a "1"
defined as no shorting jumper and a "0" defined
as a shorting jumper installed:
Xl XQ.
1
1
0
0
1
0
1
0
Base
Codec
Address Address
534h
530h
604h
608h
E80h
E84h
F44h
F40h
(default)
INTERRUPT
Although the hardware supports a wide selection
of interrupts, software may have limitations in
the available options. See the SOFTWARE COMPATIBIllTY section for more information.
The interrupt is set using header J2, also labeled
INT, (Figure 7) and must also match the software
selected interrupt. The default for the evaluation
board and the software is 7.
DMA SELECTION
Although the hardware supports a wide selection
of DMA channels for playback and capture, software may have limitations in the available
options. See the SOFTWARE COMPATIBIllTY
section for more information.
The CDB4231 contains two headers for DMA
selection: one determines the playback channel
and the other, if used, determines the capture
OS111084
.-_
_
..--_._.
__.._-_
...-.
channel for full duplex operation. Two shorting
jumpers are needed for the selected DMA channel, one for the DRQ and one for the DACK.
Header 120, labeled OMA PLAY, (Figure 7) is the
primary DMA channel used for both playback
and capture on the CS4248 or CS4231 in SDC
mode, as well as playback on the CS4231 in
full-duplex operation.
Half Duplex - Single DMA Channel
The default configuration for the CDB4231 is
full duplex. When the evaluation board is configured for half duplex, both jumpers on the OMA
CAPTURE header 11, (Figure 7) SHOULD BE
REMOVED. Otherwise, contention with other
system resources may occur.
The CS4248 does not contain the second set of
DMA base registers; therefore, it must be operated in half duplex mode. Since only one DMA
channel is needed at any particular time, the
CS4248 is usually operated in Single DMA
Channel, SDC, mode.
If only one DMA channel is available, the
CS4231 can be programmed for SDC mode
wherein the playback channel, selected on the
OMA PLAY header is used for both playback and
capture. The default setting for the evaluation
board for the OMA PLAY header DRQ3IDACK3.
Full Duplex - Two DMA Channels
Full duplex is only supported on the CS4231
(MODE 2 operation) which contains independent
capture and playback DMA Base registers.
The 11 header, labeled OMA CAPTURE, (Figure 7) is used to support simultaneous capture in
the CS4231 full-duplex mode. The default for
08111084
CDB4231/4248
the CDB4231 evaluation board OMA CAPTURE
header, 11, is DRQOIDACKO.
To support full-duplex operation, a unique DMA
channel from each header must be selected.
SOFTWARE COMPATIBILITY
The CDB423114248 comes with two sets of software: diagnostics and Windows 3.1 drivers. The
diagnostics will support all hardware jumper settings. The Windows software will support all
hardware settings when configured for generic
hardware. When the included Windows software
(or any software) is configured or designed for
100% Windows Sound System compatibility,
limitations in the hardware selections exist.
The CDB4231/4248 evaluation board includes a
board ID PLD, ID31, that indicates to software
that the board is Windows Sound System, WSS,
compatible. This read-only register is located at
the first four addresses (the second four are for
the codec). This ID will read back Ox04 from the
lower six bits. Although the evaluation board is
WSS compatible from the codec register perspective, the auto-select hardware of the WSS
board is not included. The DMA and IRQ settings must be configured via on-board jumpers.
The four base addresses supported by the evaluation board are the same as specified for WSS
hardware.
Windows software, such as the included drivers
and applets, that check for a WSS board will
read the board ID and assume that the auto-select register needs to be loaded. The auto-select
register only allows certain combinations which
4-215
-
----------- ----------must be adhered to when using the evaluation
board with this software.
Therefore, to run 100% compatible Windows
Sound System, WSS, software, the IRQ and
DMA selection must be made from the following:
INT:
7
10
(default)
CDB4231/4248
switch that forces the software to use the DMA
and IRQ settings in the SYSTEM.INI file and
assume no Auto-Select register exists. With this
switch on, all combinations of DMA and IRQ,
supported by the hardware, are allowed. To use
this option, the SYSTEM.lNI file must contain:
[CSBusAud]
GenericHardware=On
; either On or Off
; Off is default
11
Half Duplex: DMA PLAY:
o
1
3 (CDB4248 default)
DMA CAPTURE:
No jumpers (CDB4248 default)
Full Duplex: PLAY CAPTURE
o
1
1
0
3
0 (CDB4231 default)
Note in full duplex, only the three combinations
listed are allowed with the last combination being the default for the CDB4231. If the software
does not support full duplex, remove the jumpers
on the DMA CAPTURE header, 11 (Figure 7).
The Crystal Windows software provided with the
evaluation board can be configured for 100%
WSS compatible hardware and will load the
Auto-Select register with the proper DMA and
IRQ settings. In 100% WSS mode, the Crystal
software will not allow improper settings for the
DMAandIRQ.
Some hardware, including the CDB4231/4248,
allow selection of DMA and IRQ via on-board
jumpers. These jumpers allow a wider selection
of configuration options since it is not limited by
the Auto-Select register options listed above.
The Crystal Windows 3.1 software (version 1.04
and greater) supports a "generic hardware"
4-216
This switch is added to the SYSTEM.INI file by
the installation software when the "Generic
Hardware" option is selected from the Windows
Sound System screen.
WSS SOFTWARE COMPATIBILITY
The CS4231/4248 is compatible with Microsoft
Windows Sound System software (version 2.0)
with respect to wave audio data support. Since
the evaluation board does not contain a synthesizer, the MIDI portion of WSS will not
function. When installing the Microsoft software,
select Custom Installation and set the base address, IRQ, and DMA channel consistent with
the evaluation board jumper settings. Since the
board does not contain the extra hardware
needed for software configuration of the IRQ
and DMA channel, the Auto Installation mode of
the Microsoft WSS software is not supported.
The Microsoft WSS hardware and software drivers do not use all the analog inputs. The only
hardware supported by the Microsoft WSS hardware and software are a mono microphone input
(set jumper on J35 to M), and the stereo Line
input jack, Line I.
SCHEMATICS
The following pages contain the full schematics
for the CDB4231/4248, as well as the PLD
equations.
DS111DB4
....
+,y
.........~
L _ _ _ _ _ _ _ .J
C
NOT INSTALLED
ED
""
" I"
';'14
=••
---1£9
X7R
X711:
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SA1
'AQ
"VA
I""'
'"
1',
67 !)~
v~
'!'eND
D.l UF
DB'
AGNOI
I ~4 I
SPEAKER IN
1
2.7 NF
J3
..... CND
H~V
m
=
OJI
I.
_
GNQ
DBD
~
X7'
~
H20
IllUl<"
~NPO
R(O
OOW
XCTLO
AGND
"""
""'"
Q>
NP:SA14
NT
L4
Ax! !
'"
CBI
j~
lur
CORD
i!1'Jjj(
PODRO
'''f
CS4231A
"'"
'"
U~
'".....
=.;
C41
,4..71(
+7K
JB
'"
DB'
JJ
'.".....
J7
OND
LOUT
Lt.Ilc!
"
R~IC:
ca,
~~
1UF
R6Q
17
LLlN[
I I
r:;:::-;:::::;- .,117
lAUX2
LAUX2
~J2I
RLiNE
RAUX2
RAUX 2.
X1Al2If-'I'CLI------------------,
e"
.1 Xu1rR
XTAl20rI2~'-------------
-:C7~,-r---===-----------==-~·
T~
""'T
TANT
XTALlIt-'1'7~_______-----,
C73
c"
p~ "oN;~~
f""IIO
NPO
1000
J::5prY3.JPFJJPrYJ3PF
@l
CUi
NPO
"GND
ACND
ACfII)
I
!
I
o
-
-L
XrL2-LP
~c,-s
NPD
CU
NPO
-.L
XTL2-lP
Nf'()
I
AGND
- GND
;t
.......
AeNO
-L C4-J
o
c
OJ
t
Co)
.....
lo
I\)
t
Figure 1. CS4231 & Auxl In
I
.._-_
.-_
_
..--_._.
__
...-.
C084231/4248
C37
10 UF
TANT
J
Mic I
VREF
AGND
c~o
10 UF
TANT
AGND
J
R37
AGND
Figure 2. Microphone In
+5V
C76
TANT
~.~ ~F
TO.1
X7R
UF
~ND
J15
+
R20
'v---4.---....!....j us
MOUT
.22 UF
+
10K
SPEAKER OUT
1;63
TANT
TANT
~n
RESORV
AGND
AGND
ACNO
Figure 3. Mono Speaker Out
4-218
05111084
_.-_..--__....._-_
..._.-.
CDB4231 14248
R5
I~---'--r--,j
t+---------IO
RAUX2
Line I
AGND R32 SGND
AGND
j'------,--r--Ti 1 . - - - - - - 0 LAUX2
+5VA
C61
0.1 UF
X7R
AGND
,---_--=C-=-85=-1
47 PF
NPO
AGND
~RLINE
VREF
AGND
~
UF
X7R
LLINE
Figure 4. Line In & CDROM In (Aux2)
05111084
4-219
-
_.-_..--_._.
__.._-_
...-.
R55
C71
ROUT
6Ba
en
L.2 NF
NPO
~
T
3.3
CDB42'31 14248
R55
TANT
UF
~
AGND
AGND
R53
LOUT
C7D
~
2.2 NF
.
NPOJ
tif
+12V
AGND
C58
0.1 UF
X7R
8
U5C
4 NE5532
-12V
Figure 5. LineJHeadpbone Out
4-220
OS111084
C
1/1
+oV
....
....
....
....
=,.
'."hi.....
+5V
CoO
C
til
P1C
olio
,
u
I'"
«
~
63
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
M[MR
I'IIEMW
08
09
D10
011
D12
D13
014
015
R27
6-5
66
67
68
69
7Q
71
I
-----+----'\ J
I> TOVA
C1
,
TANT
n
~
III'
I"
II
,,"
81NT
11
c'c
111 ""
W~ 1![llC:"'
"
';"1111,
[lie
AGND
DMA CAPTURE
J20
I I I
nRnn
31
II
8
1111
u
85
"do
~
INT
IDI<_~
67
89
~
CDI~~ ~
P!l!lll.1--
~
",01 L
4
.
8PDRa
~
-PDK
U11
t '1A1m f1}-------s:::: IlTOR
lA2
lY2
BID...,
B l~~
:~~ Ht-- ~~JRQ
1~
2A1
17
2M-
15 ~~~
--<
7
1
+5 V
+------->m C ~ 10.1
211
BPDRQ
2Y4:3
BAI
0 MA PLA Y
e69
X'R
Uf
GND
74ALS24+
ISA-ATBUS
GND
GND
o
c
m
t;
...
i:
Co)
~
....
....
....
C
ID
....
I\)
~
CD
Figure 7. Analog Power & Buffer
----------------------
CDB4231/4248
;PALASM Design Description
; CDB4231 Rev. D
;---------------------------------- Declaration Segment -----------TITLE
Address Decode for CS4231 and Read ID
PATTERN AD31.PDS
REVISION 2.0
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
10/15/93
CHIP
_AD31
PAL20VB
,"---------------------------------- PIN Declarations --------------PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
2
3
4
5
6
7
B
9
10
11
AEN
A2
A3
A4
A5
A6
A7
AB
A9
AI0
All
13
XO
Xl
/DBENP
/IOR
AO
BAO
/RDID
RESDRV
/CCS
/CRES
/DBEN
14
15
16
17
IB
19
20
21
22
23
Eight addresses in all.
The first four addresses are used by the
board PLD ID31 - address select RDID.
The second four addresses are used by the
CS4231/424B.
Base Address: Xl,XO
1
1
o
o
(header JIB)
1
530-537,
o
604-60B,
1
ESO-ES7,
o
F40-F47,
codec
codec
codec
codec
534
60B
ES4
F44
I - Address selector Xl,XO:
.
I
-
;' 0 - Data Bus Enable Prime for 245 chip
; I - Qualifies Read ID enable
; I - from bus
o - Buffered AO (PLD just used for buffer)
o - Read ID register enable
I - Global Reset
o - Chip Select for Codec
o - Inverted RESDRV - to codec PWDN pin
I - Data Bus Enable from codec
;----------------------------------- Boolean Equation Segment -----EQUATIONS
/BAO
/AO
RDID
+
+
+
/All*A10*/A9* AB*/A7*/A6* A5* A4*/A3*/A2*/AEN*IOR* Xl* XO
/All*A10* A9*/AB*/A7*/A6*/A5*/A4*/A3* A2*/AEN*IOR* Xl*/XO
All*A10* A9*/AB* A7*/A6*/A5*/A4*/A3*/A2*/AEN*IOR*/Xl* XO
All*A10* A9* AS*/A7* A6*/A5*/A4*/A3*/A2*/AEN*IOR*/Xl*/XO
+
+
+
/All*A10*/A9* AS*/A7*/A6* A5* A4*/A3* A2*/AEN* Xl* XO
/All*A10* A9*/AB*/A7*/A6*/A5*/A4* A3*/A2*/AEN* Xl*/XO
All*A10* A9*/AB* A7*/A6*/A5*/A4*/A3* A2*/AEN*/Xl* XO
All*A10* A9* AB*/A7* A6*/A5*/A4*/A3* A2*/AEN*/Xl*/XO
CCS
DBENP
CRES
530-533
604-607
EBO-ES3
F40-F43
534-537
60B-60B
EB4-EB7
F44-F47
DBEN
+ /All*A10*/A9* AB*/A7*/A6* A5* A4*/A3*
/AEN* Xl* XO ; 530-537
+ / All *AI0* A9* /AB* /A7 * /A6* /A5* / A4 * /A3 * A2 * /AEN* Xl * /XO ;604-607
+ /All*A10* A9*/AB*/A7*/A6*/A5*/A4* A3*/A2*/AEN* Xl*/XO ; 60S-60B
+
All*A10* A9*/AB* A7*/A6*/A5*/A4*/A3*
/AEN*/Xl* XO ; ESO-EB7
+
All*A10* A9* AS*/A7* A6*/A5*/A4*/A3*
/AEN*/Xl*/XO; F40-F47
RESDRV
PLDAD31
OS111084
4-223
1111
----------------------
. CDB423114248
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
Read ID + relay enable
PATTERN ID31.PDS
REVISION 2.0
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
10/28/93
CHIP
ID31
PAL22V10
;---------------------------------- PIN Declarations --------------I - from Codec XCTL1 pin, Software Mute
PIN 1
MUTE
I
buffered /IOR from 244
PIN 2
/BIOR
I
inverted RESDRV from the AD31 PLD
/CRES
PIN 3
I
codec chip select, used for ACCESS
PIN 4
/CCS
I
Read
ID chip select, from the AD31 PLD
PIN 5
/RDID
INT
PIN 6
PIN 7
NC
PIN 8
NC
PIN 9
NC
PIN 10
NC
PIN 11.
NC
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
SBHE
DO
D1
D2
D3
D4
D5
D6
D7
ACCESS
/RLYEN
13
14
15
16
17
18
19
20
21
22
23
I
o - Data Bus, Enabled for /RDID
o
Places Read on the data bus
o
o
o
o
o
, 0
; 0 -
True after first read of the codec
; 0 - Relay Enable
i----------------------------------- Boolean Equation Segment ------
EQUATIONS
DO = GND
DO . TRST = RDID
D1 = GND
D1 . TRST = RDID
D2 = VCC
D2 . TRST '" RDID
D3 = GND
D3 . TRST = RDID
D4 = GND
D4 . TRST = RDID
D5 = GND
D5 . TRST = RDID
D6 = /INT
D6 . TRST = RDID.
D7 = SBHE
D7 . TRST
RDID
ACCESS
ACCESS * /CRES
* BIOR * /CRES
+ CCS
RLYEN
ACCESS * /MUTE
PLD ID31
4-224
OS111084
. .... .........
....
~
~~~.
CS4248
.,~~~
Semiconductor Corporation
Parallellnteriace, Multimedia Audio Codec
General Description
Features
ltgwave
• Integrated parallel interface to ISA and
EISA buses
• Stereo Digital Audio at sample rates from
4 kHz to 50 kHz with 16-bit resolution.
• DMA Transfers with on-chip FIFOs
• Free Window™ Software Drivers
• Linear, ~-Iaw, and A-law coding
V02
V03
V04
The CS4248 is a mixed signal integrated circuit that
provides 16-bit audio for computer multimedia systems.
The CS4248 includes stereo audio converters and
complete on chip filtering for record and playback of
16-bit audio data. The CS4248 combines conversion,
analog mixing, and programmable gain and attenuation
to provide a complete audio subsystem in a single 68pin PLCC or 100-pin TQFP package. The CS4248
includes an 8-bit parallel interface to the industry
standard ISA bus.
ORDERING INFORMATION:
Model
Temp. Range
0 to 70° C
CS4248-KL
CS4248-KQ
0 to 70° C
• Pin compatible with the AD1848 (PLCC)
VOl
The CS4248 is an Mwave™
audio codec.
VREF
VREFI
LFILT RFILT
Package Type
68 pin PLCC
100 pin TQFP
VAl VA2
LMIC
RMIC
FIFOs
I-----~
I-----~
LLiNE
RLINE
I--~--~
LAUXl
RAUXl
h+---~
RO
WR
Parallel
Bus
Interface
:r----1~--~LO~
FIFOs
I->{/:H----.....----~
L-r:-:;::--,~_---'\
ROUT
LAUX2
RAUX2
OGNOl OGN02
OGN03l4l7J8
XTAL11
XTAL10
XTAL21
XTAL20
AGNOl
AGN02
Preliminary Product Information IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV '93
DS106PP3
4-225
....
'----_._-.-----_
---,.,--
CS4248
ANALOG CHARACTERISTICS( TA = 25°C; VA1, VA2,
VD1-VD4 = +5V;
Input Levels: Logic 0 = OV, Logic 1 = VD1-VD4; 1kHz Input Sine wave; Conversion Rate = 48 kHz; Measurement Bandwidth is 10 Hz to 20 kHz, 16-bit linear coding.)
Parameter *
Symbol
Typ
Min
Max
'Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution
(Note 1)
16
ADC Differential Nonlinearity
(Note 1)
-
Instantaneous Dynamic Range
Signal-to-Intermodulation Distortion
Interchannel Isolation
Programmable Input Gain Span
-
77
-
dB
dB
0.02
0.025
0.003
0.01
%
%
-
90
-
-
80
80
90
90
-
-
dB
dB
dB
dB
Line Inputs
Mic Inputs
-
-
0.5
0.5
dB
dB
Line Inputs
21.5
22.5
-
dB
1.3
1.5
1.7
dB
-
10
100
LSB
-
5
%
0.266
2.66
2.66
0.29
2.9
2.9
0.31
3.1
3.1
Vpp
Vpp
Vpp
-
100
ppm/DC
-
15
pF
Line Inputs
Mic Inputs
THO
,:
Gain Step Size
ADC ,Offset Error
o dB gain
Gain Error
Full Scale Input Voltage:
(MGE=1) MIC Inputs
(MGE=O) MIC Inputs
LINE, AUX1, AUX2 Inputs
Gain Drift
-
Input Resistance
(Note 1)
20
Input Capacitance
(Note 1)
-
Notes:
Bits
LSB
85
lOR
Line to Line Inputs
Line to Mic Inputs
Line-to-AUX1
Line-to-AUX2
Interchannel Gain Mismatch
±O.5
80
72
Line Inputs
(Note 2) Mic Inputs
Total Harmonic Distortion
-
dB
kn
1. This specification is guaranteed by characterization, not production testing.
2. MGE = 1 and a 10JlF capacitor on the VREF pin .
• Parameter definitions are given at the end of this data sheet.
Mwave is a registered trademark of IBM Corporation.
Windows is a registered trademark of Microsoft Corporation.
Specifications are subject to change without notice.
4-226
DS106PP3
----------- -----------
CS4248
ANALOG CHARACTERISTICS
(Continued)
Parameter·
Symbol
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation (0 dB); Unless Otherwise Specified.
DAC Resolution
DAC Differential Nonlinearity
Dynamic Range
(Note 1)
- Total
- Instantaneous
Total Harmonic Distortion
Bits
±O.5
LSB
-
dB
dB
All Outputs
TDR
IDR
80
95
85
(Note 4)
THD
0.02
0.01
-
%
-
85
dB
95
-
dB
0.1
0.5
dB
2.0
2.15
2.3
V
Signal-to-Intermodulation Distortion
Interchannel Isolation
-
-
-
16
Line Out
Interchannel Gain Mismatch
(Note 4)
Line Out
Voltage Reference Output
Voltage Reference Output Current
-
100
94.5
-
IJ.A
93
o dB to -81 dB
-82.5 dB to -94.5 dB
1.3
1.0
1.5
1.5
1.7
2
dB
dB
-
1
10
mV
(Notes 4, 5)
1.85
2.0
2.25
Vpp
-
100
-
ppm/DC
-
1
Degree
-
kQ
(Note 3)
DAC Programmable Attenuation Span
DAC Attenuation Step Size
DAC Offset Voltage
Full Scale Output Voltage
Gain Drift
Deviation from Linear Phase
(Note 1)
External Load Impedance
10
Mute Attenuation (0 dB)
80
Total Out-of-Band Energy
(Note 1)
0.6xFs to 3 MHz
Audible Out-of-Band Energy (Fs = 8kHz) 0.6xFs to 22 kHz
-
dB
dB
-45
dB
-60
dB
65
60
120
1
1
mA
mA
mA
mA
mA
-
dB
Power Supply
Power Supply
Current
Power Supply Rejection
Notes:
1kHz
Digital, Operating
Analog, Operating
Total
Digital, Power Down
Analog, Power Down
-
(Note 1)
40
55
43
98
-
3. DC current only. If dynamic loading exists, then the voltage reference output must be buffered
or the performance of ADCs and DACs will be degraded.
4. 10 kQ, 100 pF load.
5. The output level full-scale value is 3 dB below the input full-scale value. This attenuation is not taken
into account in the mixer gain tables which show gain intemal to the mixer.
DS106PP3
4-227
.._-_
_.-_..--_._.
__
...-.
CS4248
AUXILIARY INPUT MIXERS (TA = 25°C; VA1, VA2, VD1-VD4 = +5V;
Input Levels: Logic 0 = OV, Logic 1 = VD1-VD4; 1 kHz Input Sine Wave)
Symbol
Parameter
Mixer Gain Range Span
AUX1, AUX2
Step Size
AUX1, AUX2
Note:
(Note 6)
Min
Typ
Max
Units
45
46.5
-
dB
1.3
1.5
1.7
dB
6. An addition 3 dB attenuation must be included when comparing the output value to the input value
since the analog output full-scale value is 3 dB lower than the analog input full-scale value.
ABSOLUTE MAXIMUM RATINGS (AGND,
DGND = OV, all voltages with respect to OV.)
Parameter
Power Supplies:
Symbol
Digital VD1-VD4
Analog VA1,VA2
Min
Max
Units
-0.3
-0.3
6.0
6.0
V
V
Input Current Per Pin
(Except Supply Pins)
-10
10
rnA
Output Current Per Pin
(Except Supply Pins)
-50
50
mA
Analog Input Voltage
-0.3
VA+0.3
V
Digital Input Voltage
-0.3
VD+0.3
V
-55
+125
°C
-65
+150
°C
Ambient Temperature
(Power Applied)
Storage Temperature
Warning:
Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND,
DGND
= OV, all voltages with respect
to OV.)
Parameter
Power Supplies:
Operating Ambient Temperature
4-228
Symbol
Digital VD1-VD4
Analog VA1,VA2
TA
Min
Typ
Max
Units
4.75
4.75
5.0
5.0
5.25
5.25
V
V
0
25
70
°C
DS106PP3
......
_-_...-.-.
.-_
_
..-_
_-
CS4248
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Passband
Frequency Response
Passband Ripple
Typ
Max
0
-
0.40xFs
Hz
-0.5
-
+ 0.2
dB
±0.1
dB
0.60xFs
Hz
-
Hz
-
dB
-
30/Fs
s
-
0.0
~s
0.1/Fs
~s
-
(0-0.4xFs)
Transition Band
0.40xFs
Stop Band
0.60xFs
74
Stop Band Rejection
-
Group Delay
ADCs
DACs
Group Delay Variation vs. Frequency
-
Units
DIGITAL CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1-VD4 = 5V;
AGND1, AGND2, DGND1-DGND4, DGND7, DGND8 = OV.)
Parameter
High-level Input Voltage
Digital Inputs
XTAL11IXTAL21, PDWN
Low-level Input Voltage
Symbol
Min
Max
Units
VIH
2.0
VD-1.0
VD+ 0.3
VD+ 0.3
V
V
VIL
-0.3
0.8
V
High-level Output Voltage:
D<7:0>
All Others
10 = -16.0 mA
10 = -1.0 mA
VOH
2.4
2.4
VD
VD
V
V
Low-level Output Voltage:
D<7:0>
All Others
10 = 16.0 mA
10 = 4.0 mA
VOL
-
0.4
0.4
V
V
-10
10
~A
-10
10
~
Input Leakage Current
Output Leakage Current
(Digital Inputs)
(High-Z Digital Outputs)
-
TIMING PARAMETERS
Parameter
tSTW
twDSU
tRDDV
tCSSU
Description
WR or RD strobe width
Data valid to WR rising edge
(write cycle)
RD falling edge to data valid
(read cycle)
CS setup to WR or RD falling edge
Min
Max
Units
90
-
ns
22
-
60
ns
10
tCSHD
CS hold from WR or RD rising edge
tADSU
ADDR <> setup to RD or WR falling edge
22
tADHD
ADDR <> hold from WR or RD rising edge
10
DS106PP3
0
-
ns
ns
ns
ns
ns
4-229
-
.._-_
_.-_..-__.....
..._.-.
CS4248
TIMING PARAMETERS (continued)
Parameter
Description
Min
Max
Units
tSUDKl
OAK inactive to WR or RD falling edge (DMA cycle
completion immediately followed by a PIO cycle)
60
-
ns
tSUDK2
OAK active from WR or RD rising edge (PIO cycle
completion immediately followed by DMA cycle)
0
-
ns
tDKSUa
tDKSUb
OAK setup to RD falling edge (DMA cycles)
OAK setup to WR falling edge
25
25
ns
ns
ns
tDHD2
Data hold from WR rising edge
15
-
tDRHD
ORO hold from WR or RD falling edge (assumes no
more DMA cycles needed)
0
25
ns
tBWDN
Time between rising edge of VIIR or RD to next falling
edge of WR or RD
80
-
ns
tDHDl
Data hold from RD rising edge
0
20
ns
tDKHDa
tDKHDb
OAK hold from WR rising edge
OAK hold from RD rising edge
25
25
-
ns
ns
tDBDL
DBEN or DBDIR active from WR or RD falling edge
40
ns
tPDWN
PDWN pulse width low
-
ns
CDRQ
200
~
'III
t DRHD
L
CDAK
DBEN
DBDIR
~
t DKSUa
-
-
t DBDL
-'''''"''''~
t DBDL
tsTW
RD
I+- t RDDV
->
~ t DHD1
D<7:0>
8-Bit Mono DMA Read/Capture Cycle
4-230
DS106PP3
.-._.-.
_
..--__.._-_
...
CS4248
-.I
PDRQ
',..
t DRHD
t DKSUb
PDAK
--.
~t DKHDa
t DBDL
-
DBEN
DBDIR
(high)
tSTW
WR
r---
-------..1+0
t WDSU
t DHD2
~
D<7:0>
8-Bit Mono DMA WriteJPJayback Cycle
CDROIPDRQ
---CDAKlPDAK
~
\
D<7:0>
_____--«
-t
{
\
RD/WR
LE~~~W
\
/
tSWDN
)>-___---«
/
RIG~~'GH
)1-_______
8-Bit Stereo or 16-Bit Mono DMA Cycle
CDRQ/ ~
\'----
PDRQ
~~:~~~------~~~~~_ _ _ _ _ _ _ _~~~_ _ _ _ _ _ _ _~~~lliL_ _ _ _ _ _~r
D<7:0> -------<
LOW
BYTE
1--_ _--«
.
HIGH
BYTE
/
\
>-----<\
LEFT SAMPLE
/
\'---~!
~~ ))---~\ ~~~
r-
RIGHT SAMPLE
16-Bit Stereo DMA Cycle
DS106PP3
4-231
...-..
_.-_....,--__.._-_
CDROIPDRO
.
CS4248
:'. : .
. '..
:
.
..
~.'.
.
:',
,,'
.
CDAKlPDAK
DBEN
DBDIR
RD
D<7:0>
A<1:0>
I/O Read Cycle
CDROIPDRO
.:
",
..:'.
".
.
"
..
:
..
'
:.....
,',
.
:
'.:"::',
"
CDAKlPDAK
CS
DBEN
DBDIR
(high)
WR
D<7:0>
A<1:0>
I/O Write Cycle
4·232
DS106PP3
.._-_
.-._.-.
_
..--__
...
+5V Analog (preferred)
If a separate +5V analog
supply is available, attach here
and remove the 2.00 resistor
CS4248
>- I
Ferrite Bead
2.0n
+5V
Supply
~MfL--_-~~JJ
36
35
VA2VA1
19
V04
15
V03
7
V01
-
V02
ROUT
41~
1!lF .&47kn
LOUT
1-_--'2'-'1--1 XTAL21
40~
1!lF ~47kn
rt_-'-----1I-_-=2==2'--j XTAL20
POWN
1-_---'1'-'.7--1 XTAL11
ISA
BUS
23
1-_-,1",8'--j XTAL1 0
Microphone
Inputs
.~
033 F
29
LMIC
CS
SA 19:2
Address
Oecode
~,28 RMIC
AEN
0.33!lF
Line
Inputs
30
LLiNE
27
RLiNE
Auxilary
Inputs
LAUX1
CS4248
RAUX1
( PLCC)
Pinout
LAUX2
RAUX2
,--_--'2=6'--1 RFILT
1000pF
NPO
This trace
must be
very short
,-----_--'3"-'1--1 LFILT
1000 pF
NPO
32
VREF
VREFI
A1 ~9"--_ _ _ _ _---1
10
AO
61
WR
60
RO
56
XCTLO
58
XCTL1
07
06
05
04
03
02
01
00
OBOIR
OBEN
SAl
SAO
IOWC
IORC
07
06
05
04
03
02
01
00
PORO
ORO
CORQ
ORQ
POAK 1+-'1"'3'--_ _ _ _ _-1 OAK
COAK
IRQ
11
57
OAK
IRO
l
Board Analog
Ground
Board Oigital
Ground
Figure 1. Recommended Connection Diagram
(See also Figures 9 & 10 for Layout Recommendations)
DS106PP3
4-233
---------------------GENERAL DESCRIPTION
The CS4248 is a monolithic integrated circuit
that provides audio in personal computers or
other parallel interface environments. The functions include stereo Analog-to-Digital and
Digital-to-Analog Converters (ADC and DAC),
analog mixing, anti-aliasing and reconstruction
filters, line and microphone level inputs, selectable A-law I Il-law coding, and a parallel bus
interface. Three stereo analog inputs, LINE,
MIC, and AUXl, are provided and can be multiplexed to the ADC. AUXI can be mixed with
the output of the DAC along with an additional
auxiliary input (AUX2). The only external filtering required is two capacitors. Several data
modes are supported including 8-, and 16-bit linear as well as 8-bit companded. The CS4248 is
packaged in a 68-pin PLCC or a lOO-pin TQFP.
A number of innovative design techniques are
used to minimize audible noise from external
sources, data handling errors and during normal
operating changes such as v.olume control. In the
event that a data error does occur, the CS4248
provides smooth error masking and eliminates
pops and clicks.
FUNCTIONAL DESCRIPTION
Parallel Data Interface
The 8-bit parallel port of the CS4248 provides
an interface which is compatible with most computer peripheral busses. The model for this
interface is the Industry Standard Architecture
(ISA) bus, but the CS4248 will easily interface
to other buses such as EISA and micro channel.
Two types of accesses can occur via the parallel
interface; Programmed I/O (PIO) access, and
DMAaccess.
There is no provision for the CS4248 to "hold
off' or extend a cycle occurring on the parallel
interface. Therefore, the internal architecture of
4-234
CS4248 '
the CS4248 accepts asynchronous parallel bus
cycles without interfering with the flow of data
to or from the ADC and DAC sections.
Control Registers Interface
The fIrst I/O cycle access is to the control registers of the CS4248. Timing diagrams are given
to show the timing of control register cycles. The
RD and WR signals are used to defIne the read
and write cycles respectively. The control register cycle is defined by the assertion of the
CS4248 CS signal while the DMA acknowledge
signals, CDAK and PDAK, are inactive. For
read cycles, the CS4248 will drive data on the
DATA lines while the host asserts the RD strobe.
Write cycles require the host to assert data on
the DATA lines and strobe the WR signal. The
CS4248 will latch data into the control register
on the rising edge of the WR strobe. The
CS4248 CS signal should remain active until after completion of the read or write cycle. PIO
cycles (non-DMA) are the only type which access the Control Registers.
The data interface typically uses DMA request/grant pins to transfer the digital audio data
between the CS4248 and the bus. The CS4248 is
responsible for asserting a request signal whenever the CS4248 's internal buffers need
updating. The logic interfaced with the CS4248
responds with an acknowledge signal and strobes
data to and from the CS4248, 8 bits at a time.
The CS4248 keeps the request pin active until
the appropriate number of 8-bit cycles have occurred to transfer one audio sample. Notice that
different audio data types will require a different
number of 8-bit transfers. ,
DMA Interfaces
The second type of parallel bus cycle on the
CS4248 is a DMA transfer. DMA cycles are distinguished from control register cycles by the
assertion by the CS4248 of a CDRQ (or PDRQ)
DS106PP3
_-_
......-._.
-.-_
..- _...-.
followed by an acknowledgment by the host by
the assertion of CDAK (or PDAK). While the
acknowledgment is received from the host, the
CS4248 assumes that any cycles occurring are
DMA cycles and ignores the addresses on the
address lines and the CS line.
The CS4248 may assert the DMA request signal
at any time. Once asserted,. the DMA request
will remain asserted until a DMA cycle occurs to
the CS4248. Once the falling edge of the final
WR or RD strobe of a full sample of a DMA
cycle occurs, the DMA request signal is deasserted immediately. DMA transfers may be
terminated by resetting the PEN and/or CEN bits
in the Interface Configuration Register, depending on the DMA that is in progress (Playback,
Capture, or Both). Termination of DMA transfers
may only happen between sample transfers on
the bus. If PDRQ and/or CDRQ goes active
while resetting PEN and/or CEN, the request
must be acknowledged (PDAK and/or CDAK)
and a final sample transfer completed. The
CS4248 supports one or two DMA channels.
Dual Channel DMA Mode
In dual-channel mode, playback and capture
DMA requests and acknowledges occur on independent DMA channels. In this mode, capture
and playback are enabled and set for DMA transfers. In addition, the SDC bit must be set to
zero. The playback and capture enables can be
changed without a mode change enable. This allows proper control where applicatiotls are
independently using playback and capture. Simultaneous capture and playback is not
plausible.
CS4248
forces all DMA transfers (capture or playback) to
occur on a single DMA channel (the playback
channel).
To enable the SDC mode, set the SDC bit (Index 9) to one in the Interface Configuration
register. With the SDC bit asserted, the internal
workings of the CS4248 remain exactly the same
as dual mode, except for the manner in which
DMA request and acknowledges are handled.
The playback of audio data will occur on the
playback channel exactly as dual channel operation. However, the capture audio channel is now
diverted to the playback channel. This means
that the capture DMA request occurs on the
PDRQ pin and the PDAK pin is used to acknowledge the capture request.· Simultaneous DMA
capture and playback is not plausible. If both
playback and capture are enabled, the default
will be playback.
In SDC mode, the CDRQ pin is logic low (inactive). The CDAK pin is ignored by the CS4248.
SDC does not have any affect when using Programmed 110 mode.
Interrupt
Interrupts are generated under control of the
Current Count register. The Current Count register is not accessible by the host, but is loaded
when a write occurs to the upper byte of the
Base Count Register. Note that the Base Count
registers should be loaded with the buffer size
minus one. The Current Count Register decrements on every sample period. Once the Current
Count register reaches zero, an interrupt is generated on the next sample.
Single Channel DMA (SDC) Mode
SDC mode is designed to allow the CS4248 to
be used in a computer where two dedicated
DMA channels for audio are not available. SDC
DS106PP3
The INT bit of this Status Register always reflects the status of the CS4248 internal interrupt
state. A roll-over from Current Count register
sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status register.
4-235
.-_
_
..--_._.
__.._-_
...-.
The Interrupt Enable (lEN) bit in the Pin Control
register determines whether the interrupt pin responds to the interrupt event in the CS4248.
When the lEN bit has the interrupt disabled, the
IRQ pin of the CS4248 is forced low and does
not change. However, the INT bit of the status
register always responds to the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the CS4248 in an
appropriate amount of time. The amount of time
for such data transfers depends on the frequency
selected within the CS4248.
Should an overrun condition occur during data
capture, the last whole sample (before the overrun condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transferring the sample.
Should an underrun condition occur in a playback case the last valid sample will be output to
the digital mixer. This will mask short duration
error conditions. When the next complete sample arrives from the host computer the data
stream will resume on the next sample clock.
Noise Management
The CS4248 includes circuitry for noise manage"
ment resulting from power up and down
transients. No aUdible clicks and pops occur due
to power up and down transients or when entering power down mode.
Analog Input Interface
The analog input interface is designed to accommodate four stereo input sources. Three of these
sources are multiplexed to the ADC These inputs are: the stereo line level input, the
microphone input, and an auxiliary line level in4-236
CS4248
put (AUXl). AUXI and AUX2 can be analog
mixed with the DAC outputs. All audio inputs
should be capacitively coupled to the CS4248.
Microphone Level Inputs
The CS4248 includes an selectable +20 dB gain
stage for interfacing to an external microphone.
Figure 2 shows an example microphone input
buffer circuit.
Analog Output Interface
The analog output section of the CS4248 provides a stereo line level output. The other output
types (headphone· and speaker) are implemented
with external circuitry. Left and Right outputs
should be capacitively coupled to external circuitry.
Miscellaneous· Signals
Four pins have been allocated to allow the interfacing of two crystal oscillator circuits to the
CS4248. These pins are XTALlI, XTALlO,
XTAL2I, AND XTAL20.
A PDWN signal places the CS4248 into maximum power conservation mode. A 2.1 V
reference pin is provided to maintain an audio
reference level for single supply input and output
audio signals; however, this reference is not
maintained in power-down mode.
The DBEN and DBDIR pins are used to control
an external data buffer to the CS4248. The
CS4248 is capable of driving a 16 rnA bus load.
Data bus loading requirements greater than
16 rnA will require an external buffer. DBEN enables the external drivers and DBDIR controls
the direction of the data flow.
DS106PP3
----------------------
CS4248
standing DMA transfers must be completed before new values of CEN or PEN are recognized.
CONTROL REGISTER DEFINITION
The two address pins of the CS4248 allow access to four 8-bit registers. Two of these registers
allow indirect accessing to more CS4248 registers via an index and data register. The other two
registers provide status information and allow direct access to the CS4248's digital audio data
without the need to perform DMA cycles.
Digital Loopback
Digital Loopback is enabled via the LBE bit in
the Loopback Control register and can be used
to monitor the record path during a capture sequence. This loopback routes the digital data
from the ADCs to the DACs. This loopback can
be digitally attenuated via additional bits in the
Loopback Control register. Loopback is then
summed with DAC data supplied at the digital
bus interface. When loopback is enabled, it will
"freerun" synchronous with the sample rate. The
digital loopback is shown in the CS4248 block
diagram on the front page of this data sheet.
Changing Transfer Modes
The CS4248 must be in Mode Change Enable
Mode (MCE=l) before any changes to the Interface Configuration register or the Data Format
register are allowed. The exceptions are CEN
and PEN which can be changed "on-the-fly" via
programmed liD writes to these bits. All outR6
R4
22.1 k
C4
'-VA-+---I 560 pF
NPO
C8
~0.1 uF
>-C--
1
MINR
C48
0.33 uF
_ _>-----1 ~
RMIC
(pin 28)
U2
----------.----------<
VREF
C45
MINL
(Mono)
A =20 dB
C1
.------1
2.2 k
LMIC
(pin 29)
560pF
NPO
22.1 k
+
10uF ~ C3
Figure 2. Optional Microphone Input Buffer.
DS106PP3
4-237
-- .. _-----------------If the sum of the loopback and bus data are
greater than full scale, CS4248 will send a + or full scale value to the DACs whichever is appropriate. (Clipping)
CS4248
Auto Calibration
The CS4248 has the ability to calibrate the
ADCs and DACs. Auto~calibration is initiated
when MCE goes from 1 to 0 with the ACAL bit
in the Interface Configuration register set.
INITIALIZATION AND PROCEDURES
Reset and Power down
Reset and power down modes are controlled by
the PDWN pin. To put the CS4248 into a power
down mode, the PDWN pin is pulled low. In this
state the host interface is inactive and all digital
and analog circuits are turned off..
To let the CS4248 go through its reset initialization the PDWN pin should be set high. This
rising edge starts the initialization process. While
the CS4248 is initializing, all reads by the host
computer will receive a 80 hex. All writes during initialization of the CS4248 will be ignored.
At the end of the initialization, all registers are
set to known values as documented in the register definition section.
The completion of calibration can··be determined
by polling the Auto-calibrate In-Progress (ACI)
bit in the Test and Initialization register. This bit
will be high while the calibration is in progress
and low once completed. The calibration sequence will take at least 128 sample periods.
Transfers enabled during calibration will not begin until calibration has completed..
The calibration procedure is as follows:
1) Place the CS4248 in Mode Change Enable
using the MCE bit of the Index register.
2) Set the ACAL bit in the Interface
Configuration register.
3) Return from Mode Change Enable by
resetting the MCE bit of the Index register.
4) Poll the ACI bit in the Test and Initialization
register for a one (active) then poll for a zero
(complete).
4-238
DS106PP3
_.--..-___......_-_
..._.-.
Changing Sampling Rate
The internal states of the CS4248 are synchronized by the selected sampling frequency defined
in the Data Format register. If only one crystal is
provided in hardware, it must be XTALI. The
changing of the clock source requires a special
sequence for proper CS4248 operation.
1) Mute the outputs of the CS4248 and place it
in Mode Change Enable using the MCE bit
of the Index register.
2) During a single write cycle, change the Clock
Frequency Divide Select (CFS) and/or Clock
Source Select (CSL) bits of the Data Format
register to the desired values.
3) The CS4248 resynchronizes its internal states
to the new clock. During this time the CS4248
will be unable to respond at its parallel interface. Writes to the CS4248 will not be
recognized and reads will always return the
value 80 hex.
CS4248
The CSL and CFS[2 ..0] bits cannot be changed
unless the MCE bit has been set. Attempts to
change the Data Format register or Interface
Configuration register without MCE set, will not
be recognized.
DATA STREAM DEFINITION
The CS4248 is designed for data formats which
are in "little endian" format. This format defines
the byte ordering of a multibyte word as having
the least significant byte occupying the lowest
memory address. Likewise, the most significant
byte of a little endian word occupies the highest
memory address.
The CS4248 always orders the left channel data
before the right channel. Note that these definitions apply regardless of the specific format of
the data. For example, 8-bit linear data streams
look exactly like 8-bit companded data streams.
Also, the left sample always comes first in the
data stream regardless of whether the sample is
16-bit or 8-bit in size. See Figures 3 through 6.
4) The host now polls the CS4248's Index
register until the value 80 hex is no longer
returned.
5) Once the CS4248 is no longer responding to
reads with a value of 80 hex, normal operation
can resume and the CS4248 can be removed
from MCE.
6) If ACAL is set, proceed with Auto Calibration
steps previously mentioned.
DS106PP3
4-239
--------..-------------
CS4248
----
32-bitWord
Time
Figure 3. 8-bit Mono, Data Stream Definition.
--
32-bit Word
Time
Figure 4. 8-bit Stereo, Data Stream Definition.
Figure 5. 16·bit Mono, Data Stream Definition.
31
16 15
o
Figure 6. 16-bit Stereo, Data Stream Definition.
4·240
DS106PP3
----------------------
CS4248
Data Format Definition
There are four data formats supported by the
CS4248: 16-bit signed, 8-bit unsigned, 8-bit
companded J.l-Law, and 8-bit companded A-Law.
16-bit Signed
The 16-bit signed format (also called 16-bit
two's-complement) is the standard method of
representing 16-bit digital audio. This format
gives 96 dB theoretical dynamic range and is the
standard for compact disk audio players. This
format uses the value -32768 (8000h) to represent minimum analog amplitude while
32767 (7FFFh) represents maximum analog amplitude.
8-bit Unsigned
The 8-bit unsigned format is commonly used in
the personal computer industry. This format delivers a theoretical dynamic range of 48 dB. This
format uses the value 0 (OOh) to represent minimum analog amplitude while 255 (FFh)
represents maximum analog amplitude. 16-bit
signed and 8-bit unsigned formats are shown in
Figure 7. When using NO converters of higher
resolution (16-bits) to generate 8-bit values, truncating can produce correlated noise artifacts
+~~------------.-----------~
which can be disturbing to the listener. Once the
data is truncated to 8 bits, it is impossible to remove these artifacts. The CS4248 contains an
optional dither bit in indirect register 10. When
the dither bit is set, a triangular pdf dither is
added to the internal 16-bit ADC before truncating to the 8-bit value. Dither is only used for the
ADCs when the 8-bit unsigned data format is selected. This dither removes the correlation
between the noise and the signal with a slight
increase in the noise floor.
8-bit Companded
The 8-bit companded formats (A-law and J.l-Iaw)
corne from the telephone industry. J.l-Iaw is the
standard for the United States/Japan while A-law
is used in Europe. Companded audio allows
either 64 dB or 72 dB of dynamic range using
only 8 bits per sample. This is accomplished using a non-linear companding which assigns more
digital codes to lower amplitude analog signals
with the sacrifice of precision on higher amplitude signals. The J.l-Iaw and A-law formats of
the CS4248 conform to the CCITT G.711 specifications. Figure 8 is a diagram of approximately
how both A- and J.l-Iaw behave. Please refer to
the standard mentioned above for an exact definition.
+FS ,..----------------;-------------------,
w
:l
~
- - - - - --.-:--.;--~--~----~-...,-:--- - - - - - -
0
~
8-bit
-FS
unsigned:
2'i~~p:
0
65
128
191
255
-32768
-16384
0
16384
32767
DIGrrAL CODE
Figure 7. 16-bit Signed, 8-bit Unsigned Formats.
DS106PP3
-FS
A-Law: 2Ah
15h
u-Law:
3Fh
OOh
55h1D5h
7FhlFFh
DIGrrAL CODE
95h
AAh
BFh
80h
Figure 8. 8-bit A-Law, J.l-Law Formats.
4-241
Ell·
----------------------
CS4248
CS4248 REGISTER MAPPING
Addr.
0
1
.2
3
Register Name
Index Address Register
Indexed Data Register
Status Register
PIO Data Register
r
Table 1. Direct Registers
Physical Mapping
The control registers are mapped via partial indireet mapping. Two address bits are defined to
access all of the CS4248's registers. The four direct registers are shown in Table 1. The first two
direct registers are used to access 16 indirect
registers as shown in Table 2. Table 3 details a
summary of each bit in each register. The detailed register descriptions are described in this
section. Tables 4 through 6 illustrate all the programmable gain block decodes and is included
here for reference. These gain tables will be refien:ed to under the description for the particular
r eglster.
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ir
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Data Format
Interface Configuration
Pin Control
Test and Initialization
Misc. Information
Loopback Control
Upper Base Count
Lower Base Count
Table 2. Indirect Registers
Index Register
07
06
05
INIT I MCE I TRD
IA3-IAO
04
03
I res I IA3
02
01
DO
IA2
IA1
lAO
Index Address: These bits define the
address of the CS4248 register accessed by the Indexed Data Register.
These bits are readlwrite.
res
Reserved for future expansion. Always
write zero to this bit.
MCE
Mode Change Enable: This bit must be
set whenever the current mode of the
CS4248 is changed. The Data Format
and Interface Configuration registers
CANNOT be changed unless this bit is
set. The exceptions are CEN and PEN
which can be changed "on-the-fly".
No audio activity will occur when this
bit is set.
4-242
TRD
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the status
register is set.
o - Transfers Enabled (PDRQ and
CDRQ occur uninhibited)
1 - Transfers Disabled (PDRQ and
CDRQ only occur if INT bit is 0)
INIT
CS4248 Initialization: This bit is read as
1 when the CS4248 is in a state which
it cannot respond to parallel interface
cycles. This bit is read-only.
Immediately after RESET (and once the CS4248
has left the INIT state), the state of this register is:
010XOOOO (40h)
OS106PP3
.-_
_
..--_._.
__.._-_
...-.
CS4248
During CS4248 initialization, this register CANNOT be written and is always read
10000000 (80h)
has occurred, the state machine and status register will point to the first byte of the new sample.
Until a new sample is received, reads from this
register will return the most significant byte of
the sample.
Indexed Data Register
07
107
06
106
ID7-IDO
05
105
04
104
03
103
02
102
01
101
DO
100
Indexed Register Data: These bits are
the data the CS4248 register referenced by the Indexed Data register.
During CS4248 initialization, this register can
NOT be written and is always read
10000000 (80h)
Playback Data Register (Write Only)
During CS4248 initialization, this register can
NOT be written and is always read
10000000 (80h)
I
07
PD7
06
PD6
PD7-PDO
05
PD5
04
PD4
03
PD3
02
PD2
01
P01
DO
PDO
Playback Data Port. This is the control
register where playback data is written
during programmed I/O data transfers.
I/O Data Register
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During CS4248 initialization, this register CANNOT be written and is always read
10000000 (80h)
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte· writes to this port are
ignored. The state machine is reset when the current sample is sent to the DACs.
Capture Data Register (Read Only)
I
07 06
05
C07 CD6 CD5
CD7-CDO
04
CD4
03
02
CD3 CD2
01
CD1
DO
CDO
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data transfers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register. Once
all relevant bytes have been read, the state machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once this has occurred, and a read of the status
OS106PP3
4-243
.-_
_
..--_._.
__.._-_
....-.
CS4248
CRDY
I CUlL I CUR I CRDY I SER I PUlL I PUR I PRDY liNT I
Capture Data Ready. The Capture
Data register contains data ready for
reading by the host. This bit would be
used for direct programmed I/O data
transfers. (This bit is a Read-Only)
INT
o - Data is stale.
Status Register
07
06
05
04
03
02
01
00
Interrupt Status: This indicates the
status of the internal interrupt logic of
the CS4248. This bit is cleared by any
write of any value to this register. The
lEN bit of the Pin Control register determines whether the state of this bit is
reflected on the IRQ pin of the CS4248.
Read States
Do not reread the
information.
1 - Data is fresh. Ready for next host
data read.
CUR
o - Interrupt pin
inactive
1 - Interrupt pin active
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Right channel or Left
channel. (This bit is Read-Only)
o - Right Channel Data
1 - Left Channel Data or mono
CUll
PRDY
Playback Data Register Ready. The
Playback Data register is ready for
more data. This bit would be used when
direct programmed I/O data transfers
are desired. (This bit is Read-Only)
o - Data still valid. Do not overwrite.
1." Data stale. Ready for next host
data write value.
PUR
Playback RightlLeft Sample: This bit
indicates whether data needed is for
the Right channel or Left channel.
(This bit is Read-Only)
o - Right Channel
Data
1 - Left Channel Data or Mono selected
PUll
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte of
the channel. (This bit is Read-Only)
o - Lower byte ready
1 - Upper byte ready or any 8-bit mode
The PRDY and CRDY bits are designed to be
read as one when action is required by the host.
For example, when PRDY is set to one the device is ready for more data, or when the CRDY
is set to one data is available to the host. The
definition of the CRDY and PRDY bits are
therefore consistent in this regard.
Playback UpperlLower Byte: This bit
indicates whether the playback data
needed is for the upper or lower byte of
the channel. (This bit is Read-Only)
o - Lower Byte Needed
1 - Upper Byte Needed or any
8-bit mode
SER
4-244
Sample Error: This bit indicates
that a sample was not serviced in time
and therefore an error has occurred.
The bit indicates an overrun for capture
and underrun for playback. If both the
capture and playback are enabled, the
source which set this bit can not be
determined. (This bit is Read-Only)
OS106PP3
.._-_
.-_
._.-.
_
..--_...
CS4248
Indirect Mapped Registers
o - Right
These registers are accessed by placing the ap-.
propriate index in the Index register and then
accessing the Index Data register. A detailed description of each of the registers is given below.
All reserved bits should be written zero and may
be 0 or I when read back
Line
1 - Right Auxiliary 1
2 - Right Microphone
3 - Right Line Out Loopback
This register's initial state after reset is: OOOxOOOO
Left Auxiliary #1 Input Control (Index 2)
07 06 05
Input Control Registers
07
06
LSSO
LlG3-LlGO
05
I LMGE I
04
res
03
I LlG3
02
LlG2
01
00
LlG1 LlGO I
Left input gain select. The least
significant bit of this gain select
represents 1.5 dB. See Table 4.
LSS1-LSSO
03
02
00
LX1GO
LX1 M
Left Auxiliary #1 Mute. This bit, when
set to 1, will mute the left channel of
the Auxiliary #1 input source.
This register'S initial state after reset is: 1xx01 000.
Left Input Mic Gain Enable: This bit
will enable the 20 dB gain of the left
mic input signal.
LMGE
04
LX1 G4-LX1 GO Left Auxiliary #1 Mix Gain Select. The
least significant bit of this gain select
represents 1.5 dB. See Table 5.
Left Input Control (Index 0)
I LSS1
01
ILX1Mlresresi LX1G4 LX1G3 LX1G2 LX1G1
Left input source select. These bits
select the input source for the left gain
stage going to the left ADC.
o - Left
Line
1 - Left Auxiliary 1
2 - Left Microphone
3 - Left Line Output Loopback
Right Auxiliary #1 Input Control (Index 3)
07 06 05
04
03
02
01
00
IRX1MI res res I RX1G4 RX1G3 RX1G2 RX1G1 RX1GO
RX1G4-RX1GO Right Auxiliary #1 Mix Gain Select.
The least significant bit of this gain
select represents 1.5 dB.
See Table 5.
RX1 M
This register's initial state after reset is: OOOxOOOO
Right Auxiliary #1 Mute. This bit, when
set to 1, will mute the right channel of
the Auxiliary #1 input source.
This register's initial state after reset is: 1xx01 000.
Right Input Control (Index 1)
07
I RSS1
06
05
04
03
02
RSSO I RMGE I res I RIG3 RIG2
01
00
RIG1 RIGO I
Left Auxiliary #2 Input Control (Index 4)
07 06 05
RIG3-RIGO
RMGE
RSS1-RSSO
OS106PP3
Right input gain select. The least
significant bit of this gain select
represents 1.5 dB. See Table 4.
Right Input Mic Gain Enable: This bit
will enable the 20 dB gain of the right
mic input signal.
Right input source select. These bits
select the input source for the right
channel gain stage going to the right
ADC.
I
04
03
02
01
00
I LX2M res res I LX2G4 LX2G3 LX2G2 LX2G 1 LX2GO
LX2G4-LX2GO Left Auxiliary #2 Mix Gain Select. The
least significant bit of this gain select
represents 1.5 dB. See Table 5.
LX2M
Left Auxiliary #2 Mute. This bit, when
set to 1, will mute the left channel of
the Auxiliary #2 input source.
This register's initial state after reset is: 1xx01 000.
4-245
.-_
_
..--_._.
__.._-_
...-.
CS4248
RightAuxiliary #2 Input Control (Index 5)
07 06 05
04
03
02
01
Data Format Register (Index 8)
DO
IRX2Mlres reslRX2G4 RX2G3 RX2G2 RX2G1 RX2GO
RX2G4-RX2GO Right Auxiliary #2 Mix Gain Select.
,
The least significant bit of this gain
select represents 1.5 dB.
See Table 5.
.1
07
06
res
FMT I
CSL
Right Auxiliary #2 Mute. This bit, when
set to 1, will mute the right channel of
the Auxiliary #2 input source.
RX2M
05 04
cit I S~
03
I CSF2
02
CFS1
01
00
CFSO I CSL I
Clock Source Select: These bits select
the clock source used for the audio
sample rates.
CAUTION: See note at end of this
section about changing these bits
0- XTAL11
24.576 MHz
1 - XTAL2I
16.9344 MHz
Note: When only one crystal or clock source
is provided in hardware,it must be XTAL 1.
This register's initial state after reset is: 1xx01 000.
Output Control Registers
CFS2-CFSO
Left Output Control (Index 6)
07
06
05
04
03
02
I LOM I res I LOA5 LOA4 LOA3 LOA2
LOA5-LOAO
01
00
LOA 1 LOAO I
Left Output Attenuate Select. The
least significant bit of this attenuate
select represents -1.5 dB. Full
attenuation is at least -94.5 dB.
See Table 6.
LOM
Left Output Mute. This bit, when set to
1, will mute the left DAC channel
output.
This register's initial state after reset is: 1xOOOOOO.
~
0-3072
1 - 1536
2 - 896
3 -768
4 - 448
5 - 384
6 - 512
7 - 2560
S/M
Right Output Control (Index 7)
07
06
05
I ROM I res I ROA5
ROA5-ROAO
ROM
04
03
02
01
DO
ROA4 ROA3 ROA2 ROA 1 ROAO I
Right Output Attenuate Select. The
least significant bit of this attenuate
select represents -1.5 dB. Full
attenuation must be at least -94.5 dB.
See Table 6.
Clock Frequency Divide Select: These
bits select the audio sample rate
frequency. The actual audio sample
rate depends on which Clock Source
is selected and it's frequency.
CAUTION: See note below
about changing bits
XTAL1
XTAL2
24.576 MHz
16.9344 MHz
8.0 kHz
5.51 kHz
16.0 kHz
11.025 kHz
27.42 kHz
18.9 kHz
32.0 kHz
22.05 kHz
N/A
37.8 kHz
44.1 kHz
N/A
48.0 kHz
33.075 kHz
9.6 kHz
6.62 kHz
Stereo/Mono Select: This bit
determines how the audio data streams
are formatted. Selecting stereo will
result with alternating samples
representing left and right audio
channels. Mono playback plays the
same audio sample on both channels.
Mono capture only captures data from
the left audio channel.
0- Mono
1 - Stereo
Right Output Mute. This bit, when set
to 1, will mute the right DAC output.
This register's initial state after reset is: 1xOOOOOO.
4-246
OS106PP3
_.-_..--_._.
__.._-_
...-.
C/L
o - linear
FMT
CS4248
Companded llinear Select: This bit
selects between a linear digital
representation of the audio signal or a
non-linear, companded format. The
type of companded format is defined
by the FMT bit.
1 - Companded
soc
Format Select: This bit defines the
exact format of the digital audio based
on the state of the C/L bit.
Single DMA Channel: This bit will force
BOTH capture and playback DMA
requests to occur on the Playback DMA
channel. The Capture DMA CDRQ pin
will be zero. This bit will allow the
CS4248 to be used with only one DMA
channel. Should both capture and
playback be enabled in this mode, only
the playback will occur. See the DMA
section for further explanation.
o - Dual
DMA channel mode
1- Single DMA channel mode
linear
Companded
o - 8 bit, unsigned
o - ~-Law
ACAL
1 - A-law
1 - 16-bit, signed
This register's initial state after reset is: xOOOOOOO.
Note: The Contents of this register CANNOT be
changed except when the CS4248 is in Mode
Change Enable (MCE) is 1. If MCE is not one,
writes to this register will be ignored.
o - No auto calibration
Interface Configuration Register (Index 9)
I
07
CPIO
06
05
04
03
02
01
Playback Enable. This bit enables
playback. The CS4248 will generate
PDRQ and respond to PDAK signals
when this bit is enabled and PPIO=O.
If PPIO=1, this bit enables PIO playback mode. PEN may be set and
reset without setting the MCE bit.
o - Playback Disabled
(PDRQ and
PIO inactive)
1 - Playback Enabled
CEN
PPIO
Playback PIO Enable: This bit
determines whether the playback data
is transferred via DMA or PIO.
o - DMA transfers only
1 - PIO transfers only
CPIO
Capture PIO Enable: This bit
determines whether the capture data
is transferred via DMA or PIO.
o - DMA transfers only
1 - PIO transfers only
Capture Enabled. This bit enables
the capture of data. The CS4248 will
generate CDRQ and respond to
CDAK signals when this bit is enabled
and CPIO=O. If CPIO=1, this bit
enables PIO capture mode. CEN may
be changed without setting the MCE
bit.
o - Capture Disabled
1 - Auto calibration allowed
DO
I PPIO I res I res I ACAL I SDC I CEN I PEN
PEN
Auto calibrate Enable: This bit
determines whether the CS4248
performs an auto calibrate whenever
returning from the Mode Change Enable
(MCE) bit being asserted. If the ACAL
bit is not set, previous calibration
values are used, and no calibration
cycle takes place. Therefore, ACAL is
normally set.
Note: This register, except bits CEN and PEN, can
only be written while in Mode Change Enable. See
section on MCE for more details.
This register's initial state after reset is: 00xx1000
(CDRQ and PIO
inactive)
1 - Capture Enabled
OS106PP3
4-247
----------------------
CS4248
ORR1-0RRO
Pin Control Register (Index 10)
D2
01
XCTL 1 I XCTLO I res I res I DEN I res
lEN
07
06
05
04
03
00
I res
Interrupt Enable: This bit enables
interrupts to occur on the interrupt pin.
The Interrupt pin will reflect the value
of the INT bit in the status register.
The interrupt pin is active high.
iEN
o -Interrupt Disabled
0- Greater than -1.5 dB underrange
1 - Between -1.5 dB and 0 dB
underrange
2 - Between 0 dB and 1.5 dB overrange
3 - Greater than 1.5 dB overrange
DRS
1 - Interrupt Enabled
Dither Enable: When this bit is set,
triangular pdf dither is added before
truncating the ADC l6-bit data to
8-bit unsigned data. Dither is only
active in the 8-bit unsigned data
format.
DEN
inactive
1 - CDRQ OR PDRQ are presently
active
1 - Dither Enabled
XCTL Control: These bits are
reflected on the XCTL 1,0 pins of the
CS4248
XCTL1,
XCTLO
o - TIL Logic Low on XCTL1,0 pins
not in progress
1 - Auto calibration is in progress
PUR
Playback underrun: This bit is set when
playback data has not arrived from the
host in time to be played. As a result
the last valid sample will be sent to the
DAC. This bit is sticky and will set in
in an error condition. This bit is
cleared by a Status register read.
COR
Capture overrun: This bit is set when
the capture data has not been read by
the host before the next sample arrives.
The sample being read will not be
overwritten by the new sample. The.
new sample will be ignored. This bit is
sticky and will stay set in an error
condition. This bit is cleared by a
Status register read.
This registers initial state after reset is: OOxxOxOx
Test and Initialization Register (Index 11)
07
06
05
04
03
ORL 1-0RLO
02
01
00
ORRO I ORL1 ORLO I
Overrange Left Detect: These bits
determine the overrange on the left
input channel. (Read Only) These bits
hold the peak value and are reset to "0"
by a read of this register
0- Greater than -1.5 dB underrange
1 - Between -1 .5 dB and 0 dB
underrange
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater 1.5 dB overrange
Auto calibrate In-Progress: This bit
indicates the state of aUlo calibration
(Read-Only)
o - Auto calibration
1 - TTL Logic High on XCTL 1,0 pins
I COR PUR I ACII DRS I ORR1
DRQ Status: This bit indicates the
current status of the PDRQ and CDRQ
pins ofthe CS4248.
o - CDRQ AND PDRQ are presently
ACI
o - Dither Disabled
Overrange Right Detect: These bits
.determine the overrange on the right
input channel. (Read Only) These bits
hold the peak value and are reset to
"0" by a read .ef this register
The SER bit in the Status register is simply a
logical OR of the COR and PUR bits. This enables a polling host CPU to detect an error
condition while checking other status bits.
This register's initial state after reset is: 00000000
4-248
OS106PP3
-____-_
.. ...-.
-. ..--,._.
CS4248
Misc. Information Register (Index 12)
07
06
05
04
res
res
res
103-100
I
03
02
01
00
103
102
101
100
CS4248 10: These four bits define
the version of the CS4248.
These bits are Read-Only
103-100 = 0001 Chip version "B"
103-100 = 1010 Chip version "C" and later.
This register's initial state after reset is: 1xxx0001 or
1xxx1 01 0 based on chip version.
Loopback Control Register (Index 13)
07
ILBA5
06
05
LBA4
LBA3
LBE
04
03
02
LBA2 LBA 1 LBAO
01
00
The Base Count register contains the number of
samples which occur before an interrupt is generated on the INT pin. The act of writing a value
to the Upper Base register cause both Base registers to load the current count register. Once
transfers are enabled, each sample will decrement the current count registers until zero is
reached. The next sample after zero generates an
interrupt and reloads the count registers with the
values in the Base registers. The interrupt is
cleared by a write to the Status register.
The count register is only decremented when
either the PEN or CEN bit is enabled AND a
sample occurs.
I res I LBE I
Loopback Enable: This bit will enable
the loopback mode of the CS4248 from
the AOC's output to the OACs. When
enabled, the data from the AOC's are
digitally mixed with other data being
delivered to the OACs.
Upper Base Register (Index 14)
07
06
05
04
03
02
01
00
UB?
UB6
UB5
UB4
UB3
UB2
UB1
UBO
UB7-UBO
Upper Base Bits: This byte is the
upper byte of the base count register.
It represents the 8 most significant bits
of the 16-bit base register. Reads from
this register return the same value
which was written. The current count
registers cannot be read. The base
register should be loaded with the buffer
size minus 1.
o - Loopback disabled
1 - Loopback enabled
LBA5-LBAO
Loopback Attenuation: These bits
determine the attenuation of the
loopback from AOC to OAC. Each
attenuation step is -1.5 dB.
See Table 7.
This register's initial state after reset is: OOOOOOxO
DMA Count Registers
This register's initial state after reset is: 0000000
Lower Base Register (Index 15)
07
06
05
04
03
02
01
00
LB?
LB6
LB5
LB4
LB3
LB2
LB1
LBO
LB7-LBO
The DMA Count registers allow easier integration of the CS4248 in ISA systems. Peculiarities
of the ISA DMA controller require an external
count mechanism to notify the host CPU of a
full DMA buffer via interrupt. The programmable DMA Count registers provides this service.
This register should be loaded with the buffer
size minus one.
OS106PP3
Lower Base Bits: This byte is the
lower byte of the base count register.
It represents the 8 least significant bits
of the 16-bit base register. Reads from
this register return the same value
which was written. The current count
registers cannot be read. The Base
register should be loaded with the
buffer size minus one.
This register's initial state after reset is: 00000000
4-249
----------.-----------
CS4248
Direct Registers:
A1
0
0
1
1
1
0
1
2
3
3
AO
0
1
0
1
1
07
INIT
107
CUlL
C07
P07
I
06
MCE
106
CUR
C06
P06
I
I
05
TRO
105
CROY
C05
P05
04
I
I
104
SER
C04
P04
I
I
03
IA3
103
PUlL
C03
P03
02
IA2
102
PUR
CO2
P02
03
LlG3
RIG3
LX1G3
RX1G3
LX2G3
RX2G3
LOA3
ROA3
CSF2
ACAL
OEN
ORR1
103
LBA1
UB3
LB3
02
LlG2
RIG2
LX1G2
RX1G2
LX2G2
RX2G2
LOA2
ROA2
CSF1
SOC
I
01
IA1
101
PROY
C01
P01
I
00
lAO
100
INT
COO
POO
Indirect Registers:
IA3·IAO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
07
LSS1
RSS1
LX1M
RX1M
LX2M
RX2M
LOM
ROM
06
LSSO
RSSO
05
LMGE
RMGE
-
-
-
FMT
PPIO
XCTLO
PUR
CPIO
XCTL1
COR
1
LBA5
UB7
LB7
-
-
LOA5
ROA5
C/L
04
LX1G4
RX1G4
LX2G4
RX2G4
LOA4
ROA4
S/M
-
-
ACI
ORS
-
-
-
-
LBA4
UB6
LB6
LBA3
UB5
LB5
LBA2
UB4
LB4
I
I
ORRO
102
LBAO
UB2
LB2
01
LlG1
RIG1
LX1G1
RX1G1
LX2G1
RX2G1
LOA1
ROA1
CSFO
CEN
lEN
ORL1
101
-
UB1
LB1
00
LlGO
RIGO
LX1GO
RX1GO
LX2GO
RX2GO
LOAO
ROAO
CSL
PEN
-
ORLO
100
LBE
UBO
LBO
Table 3. Register Bit Summary
4-250
OS106PP3
.._-_
_.-_..---._.
__
...-.
CS4248
0
1
2
3
IG3
0
0
0
0
IG2
0
0
0
0
IG1
0
0
1
1
IGO
0
1
0
1
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Level
0.0 dB
1.5 dB
3.0 dB
4.5 dB
18.0
19.5
21.0
22.5
dB
dB
dB
dB
0
1
2
3
60
61
62
63
OA5 OA4 OA3 OA2 OA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
Table 4. ADC Input Gain
0
1
2
3
4
5
6
7
8
9
10
11
12
XxG4 XxG3 XxG2 XxG1 XxGO
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
OAD
0
1
0
1
0
1
0
1
Level
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-90.0
-91.5
-93.0
-94.5
dB
dB
dB
dB
Table 6. DAC Output Attenuation
Level
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
0
1
2
3
60
61
62
63
LBA5 LBA4 LBA3 LBA2 LBA 1 LBAO
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Level
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-90.0
-91.5
-93.0
-94.5
dB
dB
dB
dB
Table 7. Loopback Attenuation
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-24.0
-25.5
-27.0
-28.5
-30.0
-31.5
-33.0
-34.5
dB
dB
dB
dB
dB
dB
dB
dB
Table 5. AUXl, AUX2 Output Mix Gain
DS106PP3
4-251
III;
_.-_..--_._.
__.._-_
...-.
CS4248
Codee
digital
signals
CPU & Digital
Logie
Codee
analog signals
&
Components
Figure 9. Suggested Layout Guideline
r------------------l
1
1
0
0
0
1
1
1
BUS VD
1
1
113.
I~~:
~
o
'0
VA
I;;
1
1
- - - -
. . _-----=
O'!='-.~_
O.1IlF
VD
e;!--------=Q- - - - - ;1"·
1
O.1IlF
VD
Figure 10. Recommended Decoupling Capacitor Positions
4-252
DS106PP3
---------- .. ----------POWER SUPPLY AND GROUNDING
Figure 9 is the suggested layout for the CS4248.
Similar to other Crystal codecs, it is recommended that the device be located on a separate
analog ground plane. With the CS4248's parallel
data interface, however, optimum performance is
achieved by extending the digital ground plane
across pins 65 through 68 and pins 1 through 8.
Pins 2 and 8 are grounds for the data bus and are
electrically connected to the digital ground
plane. This minimizes the effect of the bus interface due to transient currents during bus
switching. Figure 10 shows the recommended
positioning of the decoupling capacitors. The capacitors must be on the same layer as, and close
to, the CS4248. The vias shown go through to
the ground plane layer. See Crystal's layout application note for more information.
COMPATIBILITY WITH AD1848
The CS4248 is compatible with the AD1848 rev.
J silicon in terms of the applications circuit. The
AD1848 rev. K requires 1.0 /IF capacitors (not
1000pF) on pins 26 and 31. The CS4248 requires 1000 pF NPO-type capacitors on filter
pins 26 and 31 (not 1.0 /IF). To achieve compatibility with the CS4248:
1. Correct spacing of pads will ensure that
either 1.0 J..lF capacitors (for the AD1848
rev. K) or 1000 pF NPO capacitors (for
the CS4248) may be installed.
2. The CS4248 does not require the input
anti-aliasing filters included as an input
RIC for the AD1848 (5.1kQ and 560 pF).
The additional RIC's can be used with the
CS4248 if desired, with no degradation in
performance.
3. Crystal recommends the ground plane as
shown in Figure 9. Any ground plane
DS106PP3
CS4248
scheme that achieves acceptable performance with the AD 1848 should work with
the CS4248.
4. The AD1848 needs extra power and
ground pins. The power pins (VDD) are
pins 24, 45, and 54. The ground pins·
(GNDD) are pins 25 and 44. The CS4248
PLCC package does not use these pins
ard the appropriate power/ground connections can be made.
5. The AD1848 does not contain the selectable dither (DEN, 110).
6. The AD1848 is not avai;able in a 100-pin
TQFP package.
As far as software is concerned, the CS4248 is
compatible with the AD 1848 rev. K in terms of
the mix gain on the AUXI and AUX2 inputs,
and the position of the output mute block. The
CS4248 is also software compatible with the
MCE and auto-calibration functionality of the
AD1848 rev. K.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
For Our Free Review Service
Call Applications Engineering.
ADC and DAC Filter Response Plots
Figures 11 through 16 show the overall frequency response, pass-band ripple and transition
band for the CS4248 ADCs and DACs. Figure
17 shows the DACs' deviation from linear phase.
4-253
.-_
..--_
__.._-_
...-..
CS424S··
10
0
-10
-20
-30
Iii' -40
:E.
'" -50
.,'" -60
:::;
~
:2
-70
-80
-90
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (Fs)
Figure 11. 16-bit ADC Filter Response.
0.2
0
0.1
-10
-0.0
-20
-0.1
-30
~
-0.2
Iii' -40
"
-0.3
"0
.~
:E.
'"
."c:"
"0
- .-
iij' -0.4
:::;
-0.5
-0.6
-50
-60
iij'
:::; -70
-80
-0.7
-90
-'-+--+--+--+--r----t--+--+....L+----i
-0.8
+.
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 12. 16-bit ADC Passband Ripple.
4-254
-100 +-~r---+--+---t--r---+--+-"-+--"-t---j
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (Fs)
Figure 13. 16-bit ADC Transition Band.
DS106PP3
----------------------
CS4248
0.2 - = - - - - - - - 0 " " " " " " - - - - = : - - - - - = - - - - - - ,
10
0
0.1
-10
-0.0
-20
-0.1
-30
iii' -0.2
iii' -40
:r2Q>
:r2-
.~
~
-0.3
~
·0.5
:e5 -0.4
-50
."
-60
al'
:;; -70
-80
-0.6
-90
-0.7
-0.8 +--+-----;--+--+---+---+--+---I--L...t---j
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-100
0.1
0.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (Fs)
Input Frequency (Fs)
Figure 15. DAC Passband Ripple.
Figure 14. DAC Frequency Response
0
2.5
·10
2.0
-20
1.5
1.0
-30
iii' -40
Ui"
Q>
0.5
'"
Q>
0.0
Q>
-0.5
~
:r2~
-,-
-50
:r2-
~
5 -60
os
:;; -70
'"
1!
0..
-1.5
-90
-2.0
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (Fs)
Figure 16. DAC Transition Band.
DS106PP3
)
_I_
., -
-
-1.0
-80
-100
-
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 17. DAC Phase Response.
4-255
.'
----------------------
CS4248
PIN DESCRIPTION
C
z,..
C,..NMCJC'O:!' II) CO ....
CCCCC>CCCC
ZIWC1a:
CJIJlIJl;=
CCC
00>00
00>0>
C')N,..Oo>oo .... COII)"0>0>0> 00 ooc:oc:oc:oc:o
0> 00 .... CO
................
~Zg:
0
AO
CDAK
CDRQ
PDAK
PDRQ
VD3
DGND3
XTAL11
XTAL10
VD4
DGND4
XTAL21
XTAL20
PDWN
6
7
8
9
10
11
12
13
14
15
16
17
18
RFILT
25
75
74
73
72
71
70
69
RD
CS
XCTL1
IRQ
XCTLO
TEST
DGND7
CS4248
100-pin
TaFP
(a)
Top View
000>0..NNC')C')
C')
C')
II)
C')
00
C')
WOOW
I...I
i!
...I
u..
"''''NNN'''I-I-'''~
i! Cc(c(C><><:;):;)><
W z»z:;):;)oo:;):;)
a: CJ
CJc(c(...Ia: c(c(
> c(
c(...I...I
a: a:
Z--Z
-:E:E-
~a:...I:::I
4-256
,..
N
C
ZN
,..CJC
c(C>
W
a:
>
0 .... NC') "
" - Address Bus, Input, Pin 9, 10 (L), Pin 100, 1 (Q).
These address pins are read by the codec interface logic during an I/O cycle access. The state of
these address lines determines which register is accessed.
RD - Read Strobe, Input, Pin 60 (L), Pin 75 (Q).
This signal defines a read cycle to the codec. The cycle may be an I/O cycle read, or the cycle
could be a read from the codec's DMA sample registers.
WR - Write Strobe, Input, Pin 61 (L), Pin 76 (Q).
This signal indicates a write cycle to the codec. The cycle may be an I/O cycle write, or the
cycle could be a write to the codec's DMA sample registers.
CS - Chip Select, Input, Pin 59 (L), Pin 74 (Q).
The codec will not respond to any I/O cycle accesses unless this signal is active. This signal is
ignored during DMA transfers.
D< 7:0> - Data Bus, Input/Output, Pin 65-68, 3-6 (L), Pin 84-87, 90-93 (Q).
These signals are used to transfer data to and from the CS4248.
DBEN - Data Bus Enable, Output, Pin 63 (L), Pin 78 (Q).
This pin indicates that the bus drivers attached to the CS4248 should be enabled. This signal is
normally high.
DBDIR - Data Bus Direction, Output, Pin 62 (L), Pin 77 (Q).
This pin indicates the direction of the data bus transceiver. High points to the CS4248, low
points to the host bus. This signal is normally high.
IRQ - Host Interrupt Pin, Output, Pin 57 (L), Pin 72 (Q).
This signal is used to notify the host of events which need servicing.
Analog Inputs
LLINE - Left Line Input, Pin 30 (L), Pin 31 (Q).
Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. The
LINE inputs may be selected for AID conversion via the input multiplexer (10).
RLINE - Right Line Input, Pin 27 (L), Pin 28 (Q).
Nominally 1 VRMS max analog input for the Right LINE channel; centered around VREF. The
LINE inputs may be selected for AID conversion via the input multiplexer (11).
4-258
DS106PP3
----------- -----------
CS4248
LMIC - Left Mic Input, Pin 29 (L), Pin 30 (Q).
Microphone input for the Left MIC channel, centered around VREF. This signal can be either
1 VRMS (LMGE = 0) or 0.1 VRMS (LMGE = 1). The MIC inputs may be selected for AID
conversion via the input multiplexer (10).
RMIC - Right Mic Input, Pin 28 (L), Pin 29 (Q).
Microphone input for the Right MIC channel, centered around VREF. This signal can be either
1 VRMS (RMGE = 0) or 0.1 VRMS (RMGE = 1). The MIC inputs may be selected for AID
conversion via the input multiplexer (11).
LAUXI - Left Auxiliary #1 Input, Pin 39 (L), Pin 45 (Q).
Nominally 1 VRMS max analog input for the Left AUXI channel, centered around VREF. The
AUXI inputs may be selected for AID conversion via the input multiplexer (10). A
programmable gain block (12) also allows routing to the output mixer.
RAUXI - Right Auxiliary #1 Input, Pin 42 (L), Pin 48 (Q).
Nominally 1 VRMS max analog input for the Right AUXI channel, centered around VREF.
The AUXI inputs may be selected for AID conversion via the input multiplexer (11). A
programmable gain block (13) also allows routing to the output mixer.
LAUX2 - Left Auxiliary #2 Input, Pin 38 (L), Pin 44 (Q).
Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A
programmable gain block (14) allows routing of the AUX2 channels into the output mixer.
RAUX2 - Right Auxiliary #2 Input, Pin 43 (L), Pin 49 (Q).
Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A
programmable gain block (15) allows routing of the AUX2 channels into the output mixer.
Analog Outputs
LOUT - Left Line Level Output, Pin 40 (L), Pin 46 (Q).
Analog output from the mixer for the left channel.
around VREF.
Nominally 0.707 VRMS max centered
ROUT - Right Line Level Output, Pin 41 (L), Pin 47 (Q).
Analog output from the mixer for the right channel. Nominally 0.707 VRMS max centered
around VREF.
Miscellaneous
XTALlI - Crystal #1 Input, Pin 17 (L), Pin 12 (Q).
This pin will accept either a crystal with the other pin attached to XTALI0 or an external
CMOS clock. XTALl must have a crystal or clock source attached for proper operation. The
standard crystal frequency is 24.576 MHz although other frequencies can be used. The crystal
should be designed for fundamental mode, parallel resonance operation.
DS106PP3
4-259
.._
_-_...-.
--_._.
.-_
_
....
CS4248
XTAL10 - Crystal #1 Output, Pin 18 (L), Pin 13 (Q).
This pin is used for a crystal placed between this pin and XTALlI.
XTAL2I - Crystal #2 Input, Pin 21 (L), Pin 16 (Q).
If a second crystal is used, is should be placed between this pin and XTAL20. The standard
crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal should
be designed for fundamental mode, parallel resonance operation ..
XTAL20 - Crystal #2 Output, Pin 22 (L), Pin 17 (Q).
This pin is used for a crystal placed between this pin and XTAL2I.
PDWN - Power Down Signal, Input, Pin 23 (L), Pin 18 (Q).
Places CS4248 in lowest power consumption mode. All sections of the CS4248, except the bus
interface logic which reads 80h, are shut down and consuming minimal power. The CS4248 is
in power down mode when this pin is logic low.
XCTLO, XCTL1 - External Control, Output, Pin 56, 58 (L), Pin 71, 73 (Q).
These signals are controlled by register bits inside the CS4248. They can be used to control
external logic via TTL levels.
VREF - Voltage Reference, Output, Pin 32 (L), Pin 35 (Q).
All analog inputs and outputs are centered around VREfl which is nominally 2.1 Volts. This
pin may be used to level shift external circuitry, although any AC loads should be buffered.
High internal-gain microphone inputs can be slightly improved by placing a IOIlF capacitor on
VREF.
VREFI - Voltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q).
Voltage reference used internal to the CS4248 must have a 0.1 ~ + 10 ~ capacitor with short
fat traces to attach to this pin. No other connections should be made to this pin.
LFILT - Left Channel Antialias Filter Input, Pin 31 (L), Pin 33 (Q).
This pin needs 1000 pF NPO capacitor attached and tied to analog ground.
RFILT - Right Channel Antialias Filter Input, Pin 26 (L), Pin 25 (Q).
This pin needs 1000 pF NPO capacitor attached and tied to analog ground.
TEST -Test, Pin 55 (L), Pin 70 (Q).
This pin must be tied to ground for proper operation.
Power Supplies
VAl, VA2 • Analog Supply Voltage, Pin 35, 36 (L), Pin 41, 42 (Q).
Supply to the analog section of the codec.
4-260
DS106PP3
----------------------
CS4248
AGNDl, AGND2 - Analog Ground, Pin 34, 37 (L), Pin 40, 43 (Q).
Ground reference to the analog section of the codec. Internally, these pins are connected to the
substrate as are DGND3/417/8; therefore, optimum layout is achieved with the AGND pins on
the same ground plane as DGND3/417/8 (see Figure 10). However, other ground arrangements
should yield adequate results.
VDl, VD2 - Digital Supply Voltage, Pin 1, 7 (L), Pin 88, 98 (Q).
Digital supply for the parallel data bus section of the codec.
VD3, VD4 - Digital Supply Voltage, Pin 15, 19 (L), Pin 10, 14 (Q).
Digital supply for the itlternal digital section of the codec (except for the parallel data bus).
DGNDl, DGND2 - Digital Ground, Pin 2, 8 (L), Pin 89, 99 (Q).
Digital ground reference for the parallel data bus section of the codec. These pins are isolated
from the other digital grounds and should be connected to the digital ground section of the
board (see Figure 10).
DGND3, DGND4, DGND7, DGND8 - Digital Ground, Pin 16,20,53, 64(L), Pin 11, 15, 69, 79(Q)
Digital ground reference for the internal digital section of the codec (except the parallel data
bus). These pins are connected to the substrate of the die as are the AGND pins; therefore,
optimum layout is achieved by placing DGND3/417/8 on the analog ground plane with the
AGND pins as shown in Figure 10. However, other ground arrangements should yield
adequate results.
* NC (VDD) - No Connect, Pins 24, 45, 54 (L)
These pins are no connects for the CS4248. When compatibility with the AD1848 is desired,
these pins should be connected to the digital power supply. For other compatibility issues, see
the Compatibility with AD1848 section of the data sheet.
* NC (GNDD) - No Connect, Pins 25, 44 (L)
These pins are no connects for the CS4248. When compatibility with the AD1848 is desired,
these pins should be connected to digital ground. For other compatibility issues, see the
Compatibility with AD1848 section of the data sheet.
DS106PP3
4-261
--------.,-- -----------
CS4248
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.
Total Dynamic Range
TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is
measured by comparing a full scale signal to the lowest noise floor possible in the codec (Le.
attenuation bits for the DACs at full attenuation). Units in dB.
Instantaneous Dynamic Range
IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the h~onic distortion components to insignificance when
compared to the noise. Units in dB.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the
test signal.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
o dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input
code.
4-262
DS106PP3
...,..............
.., ... . .
.........
IDRIVERS I
~
."
Semiconductor Corporation
CS4231 and CS4248 Device Drivers
General Description
Features
• Support wave audio capture, playback
under Windows 3.1 & NT
• Highly optimized code for maximum
throughput, minimum CPU utilization
• Input & Output volume/mixing control
• Support ADPCM compression &
decompression
Crystal offers complete wave driver support for
the Microsoft Windows 3.1 & NT environments.
CS4231 drivers supports full duplex operation -i.e. simultaneous capture and playback. Full
duplex permits voice recognition to control
multimedia playback. Control panel applets are
provided supporting all features of the CS4248
and CS4231 devices. Functions include: 1) Input
control panel used to select audio source and
individually set the gain level, turn dither on/off,
and visually monitor recording levels with a VU
meter; 2) Output control panel used to control
volume, mixer levels and loopback monitoring; 3)
Recorder applet used to capture and playback
.WAV files, at various sample frequencies, with
compression & de-compression (ADPCM, ULaw
& ALaw). The recorder is an OLE server.
• Full Duplex audio capture & playback
• Complete with installation routines,
documentation, etc.
All source code was developed in-house. Object
code is provided without licensing fees directly
by Crystal. Sample copies are available.
ORDERING INFORMATION
Contact Crystal Semiconductor
Product Preview
document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723
NOV. '93
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
DS132PP1
4-263
.........
....
......
.... __ ...
~
~.
I DIAGNOSTICS I
~~
Semiconductor Corporation
Multimedia Audio .CodecDiagnosticSoftware
General Description
Features
• Development and manufacturing .test
support forthe CS4248 & CS4231
• Control over every feature & function automated board test features
• Measure Codec performance without
need of an external signal source·
• Record and playback .WAVfiles in the
DOS environment
• Real-time FFT, time and frequencyresponse plots
The diagnostics program for the CS4231 and CS4248
assists inevety phase of PC audio ·sub-system design.
From initial board bring-up and functional testing to factory test and field service, the diagnostics provide
in-depth information to the engineer regarding audio
performance and function.
Detailed reporting capabilities aid in both burn-in and
board debug. The diagnostics support communication
through input and output files, as well as DOS exit
codes, allowing it to be spawned by another program
and return meaningful results. A system-level diagnostics/factory test system could thus use the program
while retaining its' own user interface routines.
The diagnostics run under DOS,and are controlled by
a command line interface optimized for minimum keystrokes. Sample 'C' source code is available detailing
how to call the routines from inside a host program.
All source code was developed in-house by Crystal.
Object code is provided to OEMs without charge.
Sample copies are available.
ORDERING INFORMATION
Contact Crystal Semiconductor
Product Preview
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723
document contains information for a new product. Crystal.
IThis
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV. '.93
DS131PP1
4-264
............
..............
I CWMNLG I
..,..,~
."",.
Semiconductor Corporation
First Byte's Monologue for Windows
General Description
Features
• Monologue Text-To-Speech synthesis
software from First Byte.
• Industry leading text-to-speech
• Allows Windows applications to speak
• Permits efficient proof-reading of text
and numerical data
Monologue increases productivity in the business environment, allowing users to add speech capabilities to
any Windows (or ~OS) application. Any pronounceable
combination of letters and numbers will be spoken
clearly. No voice recording or speech training is necessary. Customizable speech parameters permit control
of volume, pitch and speed. An exception dictionary allows the user to save preffered pronounciations of
words and abbreviations.
Crystal Semiconductor has a strategic relationship with
First Byte to allow OEMs to integrate speech capabilities into their products. Crystal licenses the products
directly to OEMs.
Sample copies are available free of charge; license
fees for production are volume dependent.
• Multilingual: French, German, Spanish
and American available now; Italian,
British and Japanese in development
• Transfer data through clipboard or
direct DLUDDE link
ORDERING INFORMATION
Contact Crystal Semiconductor
Monologue
16-bit
Product Preview
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1993
(All Rights ReseNsd)
NOV. '93
OS133PP1
4-265
. '
..
....
_
.. .....
.. .. .
~~
~
..,..,~.
~~
i CWDRGNTT I
"",
Semiconductor Corporation
Talk-.:; To Voice Recognition from Dragon Systems
Features
General Description
Talk~To
• World's foremost voice recognition
• Supports popular Windows apps.
• Hands free command & control in the
Windows 3.1 environment
• Reduces typing for data entry
• Speaker independent - also supports
regional dialects through training
• Supports 64 active commands; context
sensitive for unlimited recognition
Product Preview
Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
is a powerful and flexible voice recognition
package for the Microsoft Windows 3.1 envirbnment.
Voice recognition enhances productivity by allowing users to enter simple voice commands, instead of
complicated keystrokes or multiple mouse movements,
to choose menu and control options. Voice recognition
redefines the human/computer interface, making it truly
intuitive. Talk~To is highly speaker independent, yet
may be quickly trained to support an individual's
speaking style, thus handling regional or foreign accents.
Crystal Semiconductor has a strategic relationship with
Dragon Systems to allow OEMs to integrate voice recognition capabilities into their products. Crystal licenses
the products directly to OEMs.
Sample copies are available free of charge;· license
fees for production are volume dependent.
ORDERING INFORMATION:
Contact Crystal Semiconductor
document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV. '93
DS130PP1
4-266
----------------------
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
5
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
5-1
___-_
.. ....
.-.-.---........
....
CS4920 Multi-Standard Audio DecoderlDAC
The CS4920 combines a 16.5MIPS DSP with a
stereo 16-bit Digital to Analog converter. In addition, a decompressed linear PCM coded digital
output is available in industry standard SIPDIF
format. An on-chip PLL allows very flexible
clocking. DSP code for MPEG Layers 1 and 2,
and Dolby AC2 decompression algorithms is provided. Targetted at TV set top audio decoder applications, this device is useful in any application
where low-cost audio decompression is required.
DIGITAL SIGNAL PROCESSORS·
CS8905 and CS9203 Audio Wave Table Synthesizers
The CS9203 is a wave table synthesizer which
uses a set of sampled real sounds, stored in a
ROM, to construct very realistic musical sounds.
When teamed with a 8051 type microcontroller, a
General Midi compliant synthesizer may be easily
realized. Crystal can supply the CS9203, the wave
table ROM information and code for the microcontroller.
The CS8905 is a programmable effects DSP
which may be used to add various sound effects to
the output of the CS9203 wave table synthesizer.
CONTENTS
CS4920 Broadcast Audio Decoder - DAC
CDB4920 Evaluation Board for CS4920
CS8905 Programmable Music Processor
CS9203 Advanced Music Synthesizer
Wave Table MIDI Synthesizer Solutions
CDBGMR4 Evaluation Board for CS8905 & CS9203
5-2
5-3
5-43
5-45
5-61
5-81
5-86
....
..,..,
..
.
...
__
...
.
.... .....
~
CS4920
~~
Semiconductor Corporation
Multi-Standard Audio Decoder - DAC
Features
General Description
• General Purpose Digital Signal
Processor Optimized for Audio
24 Bit Fixed Point
48 Bit Accumulator
16.9 MIPS @ 44.1 kHz Sample Rate
• On-Chip Functional Blocks Include:
-CD Quality DfA Converter
-Programmable PLL Clock Multiplier
-AESfEBU - SfPDIF Compatible
Digital AudioTransmitter
-Audio Serial Input Port
-Serial Control Port
The CS4920 is a complete audio subsystem on a chip.
This device contains a general purpose DSP, a CD
quality stereo Digital-to-Analog Converter, a programmable PLL clock multiplier, an AES-EBU - S/PDIF
compatible digital audio transmitter, an audio serial input port, and a serial control port. The CS4920 is
based on a programmable DSP core and is intended
to support a wide variety of digital signal processing
applications which include decoding compressed digital
audio. Serial audio data broadcast on networks such
as cable TV, direct broadcast satellite TV, or the telephone system can be decompressed and converted to
standard analog or digital signals.
Both industry standard and proprietary DSP algorithms
can be supported. Software which performs industry
standard MPEG layers 1 and 2 and Dolby AC-2 is
available. A complete set of software development
tools are available. These include an assembler, simulator, and debugger.
• Applications Include:
-Audio Decompression
-MPEG Layers 1 and 2
-Dolby AC-2
• Standard 44 pin PLCC Package
ORDERING INFORMATION:
CS4920-CL 44-pin PLCC
CDB4920 Evaluation Board
VD1-VD4
I
I
I
SCK/SCl SDAlCDOUT CDIN CS REO
I
I
I
I
1 1
Serial Control Port (SPI or 12C)
RESET
Serial
Audio
Port
-
DSP
Y
r----
DBDA ~
DBClK 1---0.
-
Stereo
DAC
,--------.
FSYNC r--->
SClK f------o
SDATA i------o
VA+
---+
---+
AES/EBU - S/PDIF
Transmitter
r
VREF
AOUTL
AOUTR
TX
Pll
+
Clock Manager
BOOT 1----+
I
1 J
j
DGND1- DGND4
T
T
T
T
~
FlT ClKIN EXTCKAlTClK ClKOUT
j
AGND
Preliminary Product Information I This .document contains inforr~ation for a. new. product.
Crystal
.
Semiconductor reserves the rrght to modify thiS product Without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
OCT '93
DS113PPO
5-3
-
.._-_
.....
.-_
_
..__
..._.-.
,.,
CS4920
ANALOG CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V; Full-Scale Output Sinewave, 1 kHz;
Word Clock 48 kHz (PLL in use); Logic 0 GND, Logic 1 VD+; Measurement Bandwidth is 20 Hz to 20
kHz; Local components as shown in ''Typical Connection Diagram"; SPI mode, 12S audio data; unless otherwise
specified.)
=
=
=
Parameter'
Symbol
Min
Typ
Max
-
16
-
Bits
±0.9
LSB
0.01
%
-
dB
Units
Dynamic Performance
THO
-
-
Instantaneous Dynamic Range
(DAC not muted, Note 1, A weighted)
-
85
88
Interchannel Isolation
-
-
85
-
dB
-
0.2
dB
-3.0
-
+0.2
dB
2.66
2.88
3.1
Vpp
-
100
-
ppm/oC
-
5
Deg
-60
-
dB
8
-
-
kil
pF
DAC Resolution
DAC Differential Nonlinearity
(Note 1)
Total Harmonic Distortion
(Note 1)
Interchannel Gain Mismatch
Frequency Response
(10 to 0.476 Fs)
Full Scale Output Voltage
(Note 1)
Gain Drift
Deviation from Linear Phase
Out of Band Energy
(Fs/2 to 2Fs)
Analog Output Load
Resistance:
Capacitance:
-
100
Power Supply
Power Supply Rejection
-
VA+
VD+
Note:
-
(1 kHz)
Power Supply Consumption
40
-
dB
40
TBD
mA
80
TBD
rnA
1. 10 kil, 100pF load.
D/A Interpolation Filter Characteristics (See graphs toward the end of this data sheet)
Parameter
Passband (to -3 dB corner)
Symbol
(Fs is conversion freq.)
Min
Typ
Max
Units
0
-
0.476Fs
Hz
-
Passband Ripple
Transition Band
0.442Fs
Stop Band
~
0.567Fs
Stop Band Rejection
50
Stop Band Rejection
with Ext. 2Fs RC filter
57
Group Delay
Group Delay Variation vs. Frequency
-
-
±O.1
dB
0.567Fs
Hz
-
dB
121Fs
-
s
-
TBD
I1s
Hz
dB
• Refer to Parameter Definitions at the end of this data sheet.
Specifications are subject to change without notice.
5-4
DS113PPO
___-_
.. ...-.
-.-..--_._.
ABSOLUTE MAXIMUM RATINGS (AGND,
CS4920
DGND = OV, all voltages with respect to ground.)
Parameter
Symbol
Min
Max
Positive Digital
VD+
-0.3
6.0
V
Positive Analog
VA+
-0.3
6.0
V
0.4
V
lin
-
±10
rnA
Digital Input Voltage
VIND
-0.3
(VD+)+O.4
V
Ambient Operating Temperature (power applied)
TAmax
-55
125
°C
Tstg
-65
150
°C
DC Power Supplies:
IIVA+I - IVD+II
Input Current, Any Pin Except Supplies
Storage Temperature
Units
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
-
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = OV; all voltages with respect to ground.)
Symbol
Min
Typ
Max
Positive Digital
VD+
4.50
5.0
5.50
V
Positive Analog
VA+
4.50
5.0
5.50
V
-
-
0.4
V
70
°C
Max
Units
Parameter
DC Power Supplies:
IIVA+I - IVD+II
Ambient Operating Temperature
TA
0
Units
DIGITAL CHARACTERISTICS
(TA = 25°C; VA+, VD+ = 5V ± 10%; measurements performed under static conditions.)
Parameter
High-Level Input Voltage
Symbol
Min
Typ
-
VIH
2.0
Low-Level Input Voltage
VIL
-
High-Level Output Voltage at 10 = -2.0mA
VOH
2.4
Low-Level Output Voltage at 10 = 2.0mA
VOL
-
lin
-
Input Leakage Current
DS113PPO
V
0.8
V
-
V
0.4
V
1.0
itA.
5-5
----------------------
CS4920
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(TA = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = GND, Logic 1 = VD+; CL = 20 pF)
Parameter
Symbol
SCLK Frequency
SCLK Pulse Width Low
SCLK Pulse Width High
Min
Typ
Max
Units
-
-
12.5
MHz
-
ns
tsckl
25
tsckh
25
SCLK rising to FSYNC edge delay
(Note 2)
tsfds
20
SCLK rising to FSYNC edge setup
(Note 2)
tsfs
20
SDATA valid to SCLK rising setup
(Note 2)
tsss
20
SCLK rising to SDATA hold time
(Note 2)
tssh
20
Notes:
ns
ns
ns
ns
ns
2. The table above assumes data is output on the falling edge and latched on the rising edge.
The SCLK edge is selectable in setting the EDG bit in the ASICN register. The diagram is for EDG = 1.
FSYNC
SCLK
SDATA
Serial Audio Port Timing
5-6
.DS113PPO
___-_
.. ...
._.-.
-.-..---
CS4920
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA
=25°C; VA+, VD+ =5V; Inputs: Logic 0 = DGND, Logic 1 =VD+, CL =20pF)
Symbol
Min
Max
Units
SCKlSCL Clock Frequency
fscl
0
350
kHz
CS High Time Between Transmissions
tcsh
1.0
ILs
CS Falling to SCKlSCL Edge
tcss
20
ns
SCKlSCL Low Time
tscl
1.1
ILs
SCKlSCL High Time
tsch
1.1
ILs
tdsu
250
ns
tdh
0
ILs
tscdv
300
Parameter
SPI Mode (CS = 0)
CDIN and CDOUT to SCKlSCL Rising Setup Time
SCKlSCL Rising to CDIN Hold Time
(Note 3)
SCKlSCL Falling to CDOUT Invalid
tr
1
ILs
Fall Time of Both CDIN and SCKlSCL Lines
tf
300
ns
Notes:
-
ns
Rise Time of Both CDIN and SCKlSCL Lines
3. Data must be held for sufficient time to bridge the 300ns transition time of SCKlSCL.
CS
SCKlSCL
CDIN
CDOUT
tdsu
tdh
SPI Control Port Timing
DS113PPO
5-7
----------------------
CS4920
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA
= 25 °C; VA+, VD+ = 5V;
Inputs: Logic 0
= DGND,
Logic 1 = VD+, CL
Parameter
= 20pF)
Symbol
Min
Max
Units
fscl
0
100
kHz
Bus Free Time Between Transmissions
tbut
4.7
lIs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
lIs
Clock Low Time
tlow
4.7
lIs
Clock High Time
thigh
4.0
lIs
Setup Time for Repeated Start Condition
tsust
4.7
lIs
thdd
0
lIs
tsud
250
12C® Mode
Note 4
SCKlSCL Clock Frequency
SDA Hold Time from SCKlSCL Falling
Note 5
SDA Setup Time to SCKlSCL Rising
ns
Rise Time of Both SDA and SCKlSCL Lines
tr
1
lIS
Fall Time of Both SDAand SCKlSCL Lines
If
300
ns
Setup Time for Stop Condition
Note:
Note:
tsusp
4.7
lIs
4. Use of the 12C bus®compatible interface requires a license from Philips. 12C bus® is a registered
trademark of Philips Semiconductors.
5. Data must be held for sufficient time to bridge the 300 ns transition time of SCKlSCL.
Repeated
Start
'J
I I
SDA
SCKlSCL
tsud
! sus!
12 C® Control Port Timing
5-8
DS113PPO
_.-_..--__.._-_
...
._.-.
CS4920
rect broadcast satellite TV, or the telephone system can be decompressed and converted to
.standard analog and digital signals. A wide variety of standard and proprietary decompression
algorithms can be supported. An assembler, a
simulator, and a debugger are available. CS4920
DSP code is available which performs industry
standard MPEG layers 1 and 2 and Dolby AC-2.
THEORY OF OPERATION
Introduction
The CS4920 is a complete audio subsystem on a
chip. It consists of a general-purpose Digital Signal
Processor (DSP), and a number of supplementary
analog and digital blocks. These supplementary
blocks include a programmable PLL clock multiplier, a serial audio input port, a CD quality stereo
Digital-to-Analog Converter (DAC), an AESIEBU
- SIPDIF compatible digital audio transmitter, and
a serial control port. Figure 1 shows a typical connection diagram for the CS4920 in which a micro
controller is used for loading the program code.
The DSP has a 24-bit fixed point data path, 4K
words of program RAM, and 2K words of data
RAM. The execution unit has a 48-bit accumulator, and no input data registers. Typical ALU
instructions read operands from memory and
store results back to memory. Modulo and bit reverse addressing are supported. For a sample rate
of 44.1 kHz, the DSP can provide 16.9 MIPS.
The CS4920 is based on a programmable DSP
core. A typical application is the decoding of a
compressed digital audio signal. Serial audio
data broadcast on networks such as cable TV, di-
The CS4920 includes a flexible clock manager.
This section allows clock inputs on CLKIN to
range from 7 kHz to 30 MHz, while producing
Ferrite Bead
+5V
SUPPLY
lEFT
AUDIO
CS4920
AOUTR
I--'VVIr-~---'-i
VREF 1 - - - - - - ,
27 MHz
>---,--------~
TX
ClKIN
I-----~
1k
FlT >-~\III\~-
AlTClK
EXTCK
DGND1 .. DGND4
AGND
~O.047 ~F
Figure 1. Typical Connection Diagram
DS113PPO
5-9
-
_.-_..--_.-.
__.._-_
...-.
CS4920
the necessary DSP and DAC clocks through a
programmable PLL.
The digital audio data is input through the serial
audio port: Various formats are possible with the
availability of three signal inputs and an internal
control register.
For analog reproduction of the digital input, a
stereo DAC using delta-sigma architecture is
built-in. Switched-capacitor filters perform most
of the reconstruction process. Only a simple external passive filter is needed to complete
reconstruction.
PERIPHERALS
Five on-chip peripherals make the audio decoder
ideal for decoding broadcast digital audio signals. It has a PLL clock manager, a CD quality
DAC, a digital audio transmitter, a three pin serial ¥.ort for inputting audio data, and an
SPIll C® port for serial control information.
Each peripheral has I/O mapped data, control,
and status registers. Many can also generate interrupts. A serial debug peripheral is provided to
allow easy debugging of code.
Clock Manager
In addition to the analog output, an AESIEBU SIPDIF compatible output is provided. This allows the designer the flexibility of transmitting
the audio data in a standard digital format to an
external system.
The clock manager consists primarily of a programmable clock multiplier circuit that takes a
CLKIN input of any frequency from 7 kHz to 30
MHz and produces all the internal clocks required to run the DSP and the audio peripherals.
To facilitate the downloading of DSP code to the
CS4920:i a serial control port, communicating in
either I C® or SPI format, is used. This port
may also be used in real time to issue control
commands to the DSP.
The clock manager generates a clock at a frequency of 128Fs (128 times the audio sample
rate) or 192Fs. This clock is generated by the
first PLL in the block diagram (Figure 2). It divides the CLKIN input frequency by M and
multiplies it by N to produce the 128Fs (192Fs)
clock. M is a 12 bit divider and N is 10 bit multiplier. The frequency range of the PLL is
FlT
AlTClK EXTCK
ClKOUT
U
X
3.-
SRCB
~
Instruction
7
MARO
MAR1
MAR2
MAR3
MAR4
MARS
MAR6
MAR7
~~
4
Buffer
7
}
Address Bus (11 Bits)
Register
7.
~
4
IncremenV
Decrement
112
Buffer
l
Buffer
Buffer
I
I
• The buffers each have high·impedance
states to control information flow.
12
SRCA
Figure 14. Data Address Unit
5-26
DS113PPO
.._-_
_.-_..--_._.
__
...-.
CS4920
circular buffers of size 2N that start at 2N block
boundaries can be created. When reverse carry is
specified, the carry is injected at the Nth bit and
propagated to the LSB. This provides reverse
C?!TY addressing to block sizes of 2N starting at
2N block boundaries.
decrement. Bit reverse addressing is very useful
for addressing the results of an FFT.
The result from the execution unit can be written
to an AR, an MAR, an I/O register, the ACC, or
any location in data memory. If an AR is the
destination, the low twelve bits of the result are
written into the 12 bit AR. If an MAR is specified as the destination, the four LSB's of the
result are written into the 4 bit MAR. If the result is written to data memory, the memory
address can be generated exactly the same as the
A operand address. The destination address can
be post modified exactly the same as the A operand address. The modified address is written
back to the AR at the end of the second half of
the instruction cycle.
All addressing options are specified in the instruction word and can be performed on the A
operand address and the destination address.
Program Address Unit
The Program Address Unit (PAU) generates the
13 bit address for the program memory. It generates two addresses per instruction cycle. If the
current instruction requires a source B address,
the address generated during the first half is the
B operand address. The address generated during
the second half is the next instruction address.
Every address register (AR) has a corresponding
modulo address register (MAR). The MAR can
specify circular buffers or reverse carry address
blocks. The value in the MAR specifies how
many bits the carry is allowed to propagate
through. When normal carry is specified, the
carry propagates from the LSB to the Nth bit,
where N is the value in the MAR. This means
~
I STACK POINTER I
-->
-->
-->
INTERRUPT
CONTROLLER
1
LC
STACKLC1
STACKLC2
STACKLC3
STACKLC4
STACKLC5
STACKLC6
STACKLC7
,( 10
I
NMI
INTO
INn
INT2
INT3
I
~
PC
STACKPC1
STACKPC2
STACKPC3
STACKPC4
STACKPC5
STACKPC6
STACKPC7
,( 13
IINCREMENTI
DECREMENT
ZERO
Program memory consists of 4k words of RAM
and 512 words of ROM. The ROM stores the
boot and debug programs. The 13th address bit
selects between RAM and ROM. The ROM
space should not be accessed by the user.
I
I
I
I
MPARO
MPAR1
4
PARO
PAR1
I
I
13
13
I
PROGRAM
ADDRESS
BUS
?
I
YI
*
SRCB
I CONTROL I I INSTRUCTION I
REGISTER
REGISTER
Figure 15. Program Address Unit
DS113PPO
5-27
...-..
.-_
_
..--_
__.._-_
CS4920
As shown in Figure 15, the PAU consists of two
13 bit Program Address Registers (PAR's), two 4
bit Modulo Program Address Registers
(MPAR's), the 13 bit Program Counter (PC), a
10 bit Loop Counter (LC), and seven stack locations each for the PC and LC. There is also a
stack pointer which points to the current PC and
the current LC.
During the first half of an instruction, the B operand can be read from a program address
register (PAR) or from program memory. During
the second half of an instruction, the next instruction is prefetched. If the B operand comes
from program memory, the address can come
from the PC+ 1 (immediate addressing) or a PAR
(indirect addressing).
The next instruction address normally comes
from the PC. After reading the instruction, the
PC is incremented. During a jump instruction
(JMP) , the jump address comes from ACC or
immediate short data. This address is loaded into
the PC during the first half of the jump instruction. The next instruction is read from the new
address in the PC.
If indirect addressing is specified, the contents of
the specified PAR can be post modified. The
value can be incremented or decremented. There
is no reverse carry option. Although post modify
can be specified in the instruction word, whether
it is incremented or decremented is determined
by the DEC bit in the control register. When
DEC is high, the contents of the specified PAR
is decremented.
When a jump-to-subroutine (IMPS) instruction is
executed, the PC is incremented, the stack
pointer is incremented, and the jump address is
written to the new Pc. When a return-from-subroutine (RET) is executed, the stack pointer is
decremented and the next instruction is read
from the old Pc. Incrementing the stack pointer
pushes the PC and LC to the stack and decrementing the stack pointer pops the PC and LC
from the stack.
The load instruction (LD) and the repeat (REP)
can load LC from the SRCB bus during the first
half of an instruction cycle. Loading this register
causes the next instruction to be repeated by the
value in LC+ 1. Every time the next instruction is
executed, LC is decremented. Since the PC does
not have to be incremented, LC is decremented
by the increment/decrement unit during the time
which the PC is normally incremented. Instructions with immediate data cannot be repeated.
Looping can be accomplished by repeating a
jump to subroutine instruction. Nested loops are
possible since both the PC and LC are pushed
onto the stack during a jump-to-subroutine. This
type of looping has two instructions of overhead,
the jump to subroutine and return instructions.
5·28
Each PAR has an associated Modulo Program
Address Register (MPAR). The MPAR's create
circular buffers of length 2N that start at 2N
block boundaries, where N is the value in the
MPAR. This allows carries and borrows in the
post modify increment/decrement unit to propagate from the LSB to the Nth bit only.
The PC, LC, PAR's, MPAR's, the control register, the top stack location and program memory
pointed to by a PAR can be loaded from immediate data (13 bits) or from the accumulator in
the Execution Unit. The LD (load) instruction
loads them during the first half of an instruction
cycle.
The PC, LC, PAR's, MPAR's, the control register, the top stack location and program memory
pointed to by a PAR can be read by a move program (MVP) instruction.
Interrupts
There are five· interrupt lines from the on-chip
peripherals. They are interrupts 0 through 3 and
a non-maskable interrupt. Interrupts 0 through 2
are used for outputting audio data, inputting
DS113PPO
---------------------audio data, and transferring control information
respectively. Interrupt 3 is used for reporting error conditions and updating channel status
information in the digital audio transmitter. The
non-maskable interrupt is used by the debugger.
Interrupts 0 through 3 can be enabled by setting
the interrupt enable (lEN) bit in the control register. They can be individually disabled by
clearing the corresponding mask bit (MSKO-3)
in the control register. The non-maskable interrupt is disabled by clearing the non-maskable
interrupt enable (NMIEN) bit in the control register.
When an interrupt occurs, an interrupt vector
generates the address of the next instruction.
This interrupt vector address is unique for each
interrupt. Interrupt 0 through 2 have two possible interrupt vector addresses.
Interrupt 0 occurs at twice the audio sample rate.
The ftrst time it occurs, the interrupt vector address is 0002H and right audio data should be
written to the DAC and the digital audio transmitter. The second time it occurs, the interrupt
vector address is 0003H and left audio data
should be written to the DAC and transmitter.
Refer to ftgure 12.
The audio data serial input port double buffers
one input word. This word can contain up to 24
bits. The frame sync (FSYNC) input can differentiate between left and right data when stereo
audio data is being input. When a new word is
loaded into the double buffer, interrupt 1 occurs.
The state of FSYNC determines whether the interrupt vector address is 0004H or OOOSH.
Typically, if left data has been loaded the address
is 0004H and if right data has been loaded, the
address is OOOSH.
Interrupt 2 occurs when data is transferred
through the serial control port. When data is
transferred from an external micro controller to
the DSP, the interrupt vector address is 0006H.
DS113PPO
CS4920
When data is transferred from the DSP to an external micro controller, the address is 0007H.
Interrupt 3 is a wired OR of various conditions
in the peripherals. The Long Interrupt Register
(LINT) reports all conditions that generate interrupt 3. It also contains mask bits to individually
enable each condition to generate an interrupt.
The interrupt vector address is always 0008H.
The debugger uses the non-maskable interrupt to
suspend operation in the processor. When this interrupt occurs, control switches to the monitor
program in ROM. The interrupt vector address is
lOO2H.
The interrupts are priority encoded to prevent
problems when multiple interrupts occur simultaneously. The non-maskable interrupt has a higher
priority than the maskable interrupts. Of the
maskable interrupts, line 0 has the highest priority and line 3 has the lowest priority.
An interrupt is detected by the program controller at the end of the instruction cycle during
which the interrupt occurred. Since the next instruction has already been fetched, it is executed
before the instruction at the interrupt vector location is executed. There is a one to two
instruction cycle delay from the time the interrupt occurs until the instruction at the interrupt
vector location is executed.
Interrupts can be long or short. A short interrupt
occurs if the instruction at the interrupt vector
location is anything but a JMPS( jump to subroutine). After this instruction is executed,
program control switches back to normal. The
instruction at the interrupt vector location cannot
have immediate data.
A long interrupt occurs if the instruction at the
interrupt vector address is a JMPS (jump-to-subroutine). When the jump occurs, the lEN
(interrupt enable) bit in the control register is
cleared. This disables interrupts. The lEN bit is
5-29
-
-____-_
.. ...-.
-. ..--_._.
set when an RET! (return from interrupt) instruction is executed. The lEN bit can also be set and
cleared by writing to the control register.
There is a hardware stack in the PAU which is 7
locations deep for both the program counter (PC)
and the loop counter (LC). This allows 7 levels
of subroutines and interrupts without a software
stack for these counters. There is also one
shadow status register which operates as a one
deep hardware stack for the status register. Multiple levels of interrupts can be supported by
implementing a software stack for the status register and by using short interrupts.
When a long interrupt occurs, the contents of the
status register and the shadow status register
swap. If a software stack is required, the contents of the shadow status register must be stored
and interrupts enabled. Near the end of the interrupt service routine, interrupts must be disabled
and the shadow status register restored. A RET!
(return from interrupt) instruction swaps the contents of the status register and the shadow status
register and enables interrupts. The status and
shadow status registers do not swap when a short
interrupt occurs.
If multiple levels of interrupts are not required or
if the interrupt service routine does not affect the
status register, the shadow status register does
not have to be saved on the software stack. In
this case, the contents of the status register and
shadow status register are swapped when the interrupt occurs and again when the RET! is
executed. Short interrupts do not swap the contents of the status and shadow status registers.
CS4920
Instruction Set
The instruction set allows flexible addressing of
two source operands and the destination. In one
instruction the main ALU operation is performed
and up to three memory address pointers can be
updated ..
The assembly code syntax is:
OPCODE SRCA, SRCB, DEST
For typical arithmetic and logical instructions
SRCA is a location in data memory, an address
register, or an 110 register. SRCB is a location in
program memory, a program address register, or
the accumulator. DEST is a location in data
memory, an address register, an 110 register, or
the accumulator.
Addressing modes can be register direct or register indirect for SRCA, SRCB, and DEST. SRCA
and DEST memory locations can also be addressed directly. SRCB can also be immediate
data.
The following examples of an ADD instruction
illustrate possible addressing modes.
add *AR2+, *PARO, *AR3+
/*SRCA=AR2 indirect with post increment;
SRCB=PARO indirect; DEST=AR3 indirect with
post increment*/
add *AR2, *PAROm, *AR3
/*SRCA=AR2 indirect; SRCB=PARO indirect
with post modify; DEST=AR3 indirect*/
add *AR2-, PAROr, *AR3/*SRCA=AR2 indirect with post decrement;
SRCB=PARO register direct; DEST=AR3 indirect with post decrement*/
add *AR2b+, OxI23456, *AR3b+
/*SRCA=AR2 indirect with bit reverse post in-
5·30
DS113PPO
----------------------
CS4920
crement; SRCB=immediate; DEST=AR3 indirect
with bit reverse post increment*/
add Ox19, ACC, ACC
/*SRCA=direct address, ARO is the page register; SRCB=ACC; DEST=ACC*/
add *AR2b-, ACC, *AR3b/*SRCA=AR2 indirect with bit reverse post decrement; SRCB=accumulator; DEST=AR3
indirect with bit reverse post decrement* /
Any combination of addressing modes for
SRCA, SRCB, and DEST are permitted.
Figure 16 illustrates the processor programming
model. It shows all registers and memory, and
the bus attached to each.
add *AR2b-, ACC , *AR3b+
/*SRCA=AR2 indirect with bit reverse post decrement; SRCB=ACC; DEST=AR3 indirect with
bit reverse post increment*/
All registers and memory locations on bus A can
be used as the SRCA operand or as the destination. The MPAR's, the PAR's, the accumulator,
and program memory space can be used as the
SRCB operand.
add AR2, ACC, AR3
/*SRCA=AR2 register direct; SRCB=ACC;
DEST=AR3 register direct*/
The LD (load) instruction can write the contents
of the accumulator or immediate short (13 bits)
data to a PAR, an MPAR, the control register(CR), the program counter (PC), the loop
counter (LC), and the last PC and REP pushed
onto the stack (PC-1 and LC-1). It can also write
the contents of the accumulator or immediate
short data to program memory pointed to by a
add MAR2, ACC, MAR3
/*SRCA=MAR2 register direct; SRCB=ACC;
DEST=MAR3 register direct*/
add Ox19, ACC, Ox27
/*SRCA=direct address, ARO is the page register; SRCB=ACC; DEST=direct address, AR1 is
the page register*/
STACK POINTER
I
I
BOOT &
Monitor
ROM
I I CONTROL
I
REGISTER
LC
STACKLC1
STACKLC2
STACKLC3
STACKLC4
STACKLC5
STACKLC6
STACKLC7
1
PC
STACKPC1
STACKPC2STACKPC3
STACKPC4
STACKPC5
STACKPCS
STACKPC7
I
MPARO
MPAR1
I
PARO
PAR1
Program
RAM
4KX24
1
I ACCUMULATORJ
1
1
SRCB
MARO
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
r
ARO
AR1
AR2
AR3
AR4
AR5
AR6
AR7
r
Da1a
RAM
2KX24
r
I SHADOW
STATUS REG I
REG
r
I/O
REGISTERS
r
SRCA
Figure 16. Programming Model
DS113PPO
5-31
CS4920
PAR. The specified PAR can be post modified or
not post modified.
The MVP (move program) instruction can move
immediate long data, the accumulator, a PAR, an
MPAR, the CR, the PC, the LC, the PC-I, and
the LC-I to any destination described in the
ADD example above. It can also move program
memory pointed to by an PAR to any destination
described above and any of the stack pointer locations (STACKPC[O-7] and STACKLC[O-7]).
The specified PAR can be post modified or not
post modified.
The contents of the stack pointer can be accessed
by reading bits 5 through 7 of the Status Register. Bits 5 through 7 of the Shadow Status
Register are always low.
Boot Procedure
Program and data RAM must be loaded from external memory after power up or when a new
program needs to be loaded. During the loading
procedure (boot), data is transferred through the
serial control port to program and data memory.
This procedure is controlled by a program stored
internally in ROM.
Following a power up or reset, the fast mode bit
(FSTB) is cleared. This places the CS4920 into a
'fast mode'. While the serial control port (SCP)
still conforms to the data format determined by
CS on power up, the port can be operated at
much higher bit rates to facilitate faster downloading of the DSP code. Once the code has
been loaded the software can set the FSTB for
normal communication in either SPI or I2C®.
Since the. CS4920 is always a slave this fast
mode will not affect the operation of other devices sharing the same communication bus.
The boot procedure is initiated by a low to high
transition of the reset (RESET) pin with the
BOOT pin tied high. This initializes the program
counter to location IOOOH, the first location in
5-32
ROM. After the ROM program transfers data
from the control port to memory, it issues a software reset. This is done by writing a one to the
RS (reset) bit in the control register. The software reset clears all registers including the
program counter, which transfers control to the
new program in RAM.
A hardware reset (RESET pin toggled low) has
the same affect as a software reset. During the
boot procedure, all interrupts, except the debug
interrupt, are disabled.
The serial control port will boot from a micro
controller. When booting, it can communicate in
an I2C® or SPI format. If the CS (chip select)
pin is high when boot is initiated, the port will
communicate in SPI format. If the CS pin is low
when boot is initiated, the port will communicate
in I 2C®.
Nodes in an I2C® network have unique network
addresses. A message in an 12C® network consists of the address of the node receiving the
message followed by the message data. When
the control port is configured for I2C® format, it
normally compares the address to an address
stored in an internal register. During the boot
procedure, the control port is programmed to ignore the address.
The boot program in internal ROM expects data
transferred through the control port to have the
proper file format. The first two bytes contain
the starting address for the following block of
data. The starting address is 13 bits with the 13th
bit specifying program or data memory. Therefore, the upper 3 bits of these two bytes are
discarded internally. The second two bytes contain the length of the block of data. Successive
bytes are concatenated into 24 bit words. These
words are sequentially loaded into program and
data memory beginning at the starting address.
Any number of blocks of data can be loaded.
Two bytes containing FF and 3 bytes containing
DS113PPO
_.-_..--_._.
__.._-_
...-.
CS4920
a check sum must follow the last block of data.
This check sum is generated by summing all the
previous data, address, and length bytes and
truncating to 24 bits. This check sum is compared to the value calculated internally. If they
do not match, the REQ (request) pin is pulled
low and the processor does not issue the software reset. It stays in a loop until boot is
initiated again.
SRCA operand or destination for most ALU operations. The control register is connected to the
SRCB bus. It is loaded by the LD (load) instruction and can be read by the MVP instruction.
The contents of each register are described below.
I/O Address Space
IJO address space consists of peripheral input
Control and Status Registers
The Status Register is connected to the SRCA
bus. Since it is IJO mapped, it can be used as the
Status Register
Bit
23-8
7-5
Name
(undefined)
STPTR
4
3
2
1
0
N
Z
V
U
C
and output registers, peripheral control registers,
and the Status and Shadow Status Registers.
These registers can be used as the SRCA operand or as the destination. The assembly language
Function
Stack pointer
Points to the current program and repeat counters
Negative
Zero
Overflow
Unnormalized
Carry
Control Register
Bit
23-10
9
Name
(undefined)
NMIEN
8
PWDN
7
6
lEN
TRACE
5
RS
4
DEC
0-3
MSKO-3
DS113PPO
Function
(must be programmed low)
Non-maskable interrupt enable. When low, non-maskable interrupts
cannot occur. NMIEN is high after a reset.
Power down. Writing a one puts the chip into a power down mode.
The reset pin must be toggled to clear it. In power down mode, the
processor stops functioning.
Interrupt enable. When high, interrupt lines 0 through 3 can occur.
Trace mode enable. When high, the processor will enter single step
mode.
Software reset. Writing a one resets the chip. All registers are
cleared.
Increment/decrement. When set, the program address registers are
decremented when post modify is specified. When clear, they are incremented.
Interrupt mask bits 0 through 3. When low, the corresponding
interrupt line cannot interrupt the processor.
5-33.
-
.._-_
.-_
_
..---._.
__
...-.
OAC
CS4920
~==::===~========~~~~_
~I~~-'r-~--r.=~-
ASICN
SCPIN
SCPOUT
SCPCN
CMO
eM1
X~~~
XMTCS
XMTCN
________~________~~________~____________
p'-,-----,,-'---,---,--.....,,=-,-..,..,"""rru;;;-
LINT
STATUS
SHADOW
DBIN
OBOUT
OBPST
Figure 17. I/O Register Bit Map
syntax has a keyword for each register in 110
space. The following table summarizes these
keywords and their respective register addresses.
Keyword
DAC
ASI
ASICN
Register
Addresses
00000
00010
00011
SCPIN
00100
SCPOUT
00100
SCPCN
00101
CMO
00110
CMl
00111
XMT
XMTCS
01000
01001
XMTCN
LINT
01010
01011
5-34
Keyword
Register
Addresses
STATUS
10000
SHADOW 10001
DBIN
01100
Description
DBOUT
01100
DAC output register
Serial input register
Serial input control
register
Serial control input
register, read only
Serial control output
register, write only
Serial control port
control register
Clock manager control
register 0
Clock manager control
register 1
Audio transmit register
Transmit channel status
register
Transmit control register
Long interrupt register
DBPST
01101
Description
Status register
Shadow status register
Debug input register,
read only
Debug output register,
write only
Debug port status
register
Table 1. Register Summary
Figure 17 shows all 110 register bit assignments.
These registers are described in the section
which follows. Note that the Control Register
described earlier is not included in Figure 17.
This is because the Control Register is not an
110 mapped Register.
Debugger
The debugger consists of software and a cable
which connects PC compatible parallel port to
the debug port pins (DBCLK, DBDA), and an
on-chip serial debug port and debug ROM. The
computer can load programs, set breakpoints,
DS113PPO
-____-_
.. ...-.
-. ..--_._.
CS4920
read and write registers and memory, and single
step programs.
The debug ROM contains the interrupt service
routine which interprets commands sent from the
computer. Examples of these commands are
"read register", "write register", or "set break
point". The main program or the boot program is
interrupted when the computer sends a command
to the debug port. This causes program control
to switch to the debug program.
This program polls the debug port for additional
commands and performs the appropriate action.
When a "run" command is issued, the program
executes a RETI (return from interrupt) and program control switches back to the main program.
Breakpoints are set by replacing the instruction
at the breakpoint location with a TRAP instruction. The TRAP instruction generates a debug
interrupt when it is executed. Once the breakpoint has been set and the processors registers
have been properly initialized, the user can issue
a "run" command. The main program runs until
the TRAP instruction is executed. Program control then switches back to the debug program.
>1/8"
Ground
Connection
Digital
Ground
The debug port and the TRAP instruction can
generate a debug interrupt. This interrupt is a
unique signal which can interrupt the processor
independent of the state of the lEN control bit.
This interrupt can be enabled or disabled by setting or clearing the NMIEN (non-maskable
interrupt enable) control register bit. The default
state is enabled. NMIEN is cleared when a debug interrupt occurs and it is set when an RTI
instruction is executed. Writing to the control
register can also change the state of NMIEN.
The high 32 words of data memory are used by
the debug program.
POWER SUPPLY AND GROUNDING
When using separate supplies, the digital power
should be connected to the CS4920 via a ferrite
bead, positioned closer than 1" to the device (see
Figure 18). The CS4920 VA+ pin should be derived from the cleanest power source available.
If only one supply is available, use the suggested
arrangement in Figure 1.
The CS4920 should be positioned such that the
analog pins (pins 29 - 39) are over the analog
Ii
Analog,
Ground
piane
Plane
I.
Note that the CS4920
is oriented with its
digital pins towards the
digital end of the board.
.1
Digital
Interface
Analog
Signals &
Components
Figure 18. CS4920 Suggested Layout
DS113PPO
5·35
-
.._-_
_.-_..-_-....
..._.-.
CS4920
DGND·AGND
SPUT
.-:---
+
+
DGND
1.0uF
(on bottom layer')
o
AGND
(on bottom layer)
= vias oonnectlng lOp
and bottom planas
_
=top layer
D
= bottom layer
note:
vias A and B provide the nllC8llSlUY retum path to AGND for the capacitors
oonnactad to VREF by m81111S of the solid AGND plane on the bottom layer.
Figure 19. CS4920 Surface Mount Decoupling Layout
ground plane, while the rest of the pins layover
the digital ground plane as illustrated in Figures
18 and 19. The analog and digital grounds on
the CS4920 are not connected internally; this
should be accomplished externally through a
point-to-point connection across the ground split
as shown in Figure 18. A separate power plane
for the chip is preferable.
Figure 19 illustrates the optimum ground and decoupling layout for the CS4920 assuming a
surface-mount socket and surface mount capacitors. Surface-mount sockets are useful since the
pad locations are exactly the same as the actual
chip; therefore, given that space for the socket is
5-36
left on the board, the socket can be optional for
production. Figure 19 depicts mostly the top
layer containing signal traces and assumes the
bottom or inter-layer contains a solid ground
plane (analog or digital), except where the digital
supply needs to run to the power pins. The important points with regards to this diagram are
that the ground plane is SOLID under the
CS4920 and connects all ground pins with thick
traces providing the absolute lowest impedance
between ground pins. The decoupling capacitors
are placed as close as possible to the device
which, in this case, is the socket boundary. The
lowest value capacitor is placed closest to the
chip. Vias are placed near the AGND and DGND
DS113PPO
_.-_..--_._.
__.._-_
...-.
pins, under the IC, and should be attached to the
solid ground plane (analog or digital) on another
layer. The negative side of the decoupling capacitors should also attach to the same solid
ground plane. Traces bringing the power to the
CS4920 should be wide thereby keeping the impedance low.
If using through-hole sockets, effort should be
made to find a socket with the minimum height
which will minimize the socket impedance.
When using a through-hole socket, the vias under the chip in Figure 19 are not needed since
the pins serve the same function.
CS4920
,
-10
I
I ,
- -, - - -, - - ,- - -, - -
,
~
- - .- - -
-20
Iii'
-3
~ -40
III
~ -50
-60
'§,
'"
:::!: -70
-80
- - - - - - - - - - - - - "
'"
- - - - - - - - - - - - - I
-9
~
I
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I
I
-
~
-
I
-
- -
-1001+---t---t--t-----t----t---t---t---j-----j-----'i
M
~
M
~
M
M
M
M
~
M
1n
Inpu1 Frequency (Fs)
Figure 20. DAC Frequency Response.
o,-~--~~~-~~-~~-~-,
- - -, - - - -
-10
-"
- - -"
- - -
- -
-
-
-
-
-20
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
-30
~
-40
-g"
-50
."<=
~ -60
-
-
I
-
-
,
-
-
,-
-
::;;
-80
_ ,_
-90
For Our Free Review Service
Call Applications Engineering.
-,
~
-
,-
-
-
-,
I
,
I
,
,
I
I
I
-
-
J -
-,
- - - - - - - - - - - - - - - ,
,
,
-70
_
_, _
_
!..
_
_, _
,
I
-
+
-
-
_
2
_
_ ,_
-
-
~
-
-
_, _
-
_
-100 +---t--t--t----t---j-----j----t----t---t---1
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 21. DAC Transition Band.
0.2 - , - - - - - - - - - - - - - - - - - , - - . . , - - - - - - ,
0.1
-0.0
·0.1
DAC Filter Response Plots
Figures 20 through 23 show the overall frequency response, passband ripple and transition
band for the CS4920 DACs. Figure 23 shows the
DACs' deviation from linear phase. Fs is the selected sample frequency. Since the sample
frequency is programmable, the filters will adjust
to the selected sample frequency. Fs is also the
FSYNC frequency.
DS113PPO
~
-0.2
"
~ -0.3
~ -0.4
-
-,-
-
"j
-
-,-
::;;
-
-,
-
-
- - -
-0.5
,-
,
-
"
-
-,-
- -
,
-0.6
-0.7
I
,
I
,
I
-
-;
- - -,
- - -,
,
,
-
-,-
-
-
-
-
- - - - - - ,
,
,
- - - - - - I
- - - - - - - - - - - - - - - - - - - - - -
-- ,
-0.8 +----t--t--t----t---j-----j---t----t--f---1
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 22. DAC Passband Ripple.
5-37
-
---------_._-.
-----_._-
CS4920
2.5
2.0
1.5
-
""'"e
-0.0
~
-0.5
:E.
~
,
,
,
,
~
;
1.0
;
,
,
0.5
CD
n.
-1.5
-2.0
\
-,-
-1.0
-
,
-
,
•
-,
,
-,-
-
-2.5 +----1r--+--t--t---t---t--t--t--j----j
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Figure 23. DAC Phase Response.
'.:.
5-38
DS113PPO
_.-_..-___.....--_
..._.-.
CS4920
PIN DESCRIPTIONS
CDIN
SCKlSCl
NC
NC -----NC ~
NC
NC
VD2
DGND2
DBClK
DBDA
SDATA
SClK
:::w
CS
VD4
DGND4
RESET
BOOT
AOUTR
AOUTl
NC
VREF
NC
VA+
------- AGND
NC
31~ FlT
NC
EXTCK
AlTClK
ClKIN
DGND3
VD3
ClKOUT
FSVNC
~~~~
Power Supplies
VDl, VD2, VD3, VD4 - Positive Digital Power Supply, PINS 7, 17, 25, 43.
The +5V supply is connected to these pins to power the various digital subcircuits on the chip.
See decoupling section in this data sheet for decoupling recommendations.
DGNDl, DGND2, DGND3, DGND4 - Digital Ground, PINS 6, 18, 26, 42.
Digital power supply ground.
VA+ - Positive Analog Power Supply, PIN 34.
The analog +5V supply for the analog-to-digital converter and the PLL. Analog performance is
highly dependent on the quality of this supply. See decoupling section in this data sheet for
decoupling recommendations.
AGND - Analog Ground, PIN 33.
Analog power supply ground.
DS113PPO
5-39
.._-_
_.-_..--_.-.
__
...-.
CS4920
Digital-to-Analog Converter
AOUTL, AOUTR - Analog Outputs, Left and Right Channels, PINS 38, 39.
These DAC outputs are centered about the voltage at VREF. An external filter is required to
diminish out-of-band noise.
VREF - DAC Voltage Reference, PIN 36.
This reference should be decoupled with lOJ.LF and a O.lJ.LF capacitors to ground using
minimum trace lengths. The O.1J.LF capacitor should be closest to the pin.
Serial Audio Port
FSYNC - Frame Synchronization Clock Input, PIN 23,
FSYNC transitions delineate left and right audio data, or the start of a data frame, as
determined by the PUL bit in the ASICN. The edge definition (left, right, or active) is
determined by the POL bit.
SCLK - Serial Clock Input, PIN 22.
SCLK is used to clock the serial audio data on SDATA into the device. The EDG bit in the
ASICN determines the active edge. The DEL bit can be used to delay data by one SCLK after
an FSYNC transition.
SDATA - Serial Audio Data Input, PIN 21.
Audio data input to SDATA is clocked into the device by SCLK. There are several options for
the relationships between SDATA, SCLK, and FSYNC.
Digital Audio Transmitter
TX - Transmit, PIN 5,
Biphase mark encoded data is output at logic levels from the TX pin. This output typically
connects to the input of an RS-422 or optical transmitter. The port can support either AESIEBU
or SIPDIF formats.
Clock Manager
CLKOUT - Clock Output, PIN 24.
CLKOUT can be used to synchronize peripheral devices such as a micro controller or an audio
source. The clock frequency is determined by a divide by Q and a divide by 2 of the DSP
clock. Q is a 10 bit register..
ALTCLK - Clock Input, PIN 28.
When EXTCK is high, ALTCLK is an input for an externally generated 128Fs or 192Fs clock.
EXTCK - External Clock Select, PIN 29.
Setting EXTCK high allows ALTCLK to be used as an input for an external VCO. Setting
EXTCK low disables ALTCLK.
5-40
DS113PPO
.-._.-.
_
..--__.._-_
...
CS4920
FLT - PLL Filter, PIN 31,
An RC low-pass filter (1.0 ill, 0.047IlF) connected to this pin sets the control voltage for the
on-chip VCO.
CLKIN - Clock Input, PIN 27.
A clock input to the CLKIN is used to synchronize the PLL's. The permissible frequency range
is from 7 kHz to 30 MHz. It is typical to have SCLK for the audio data and CLKIN to be
derived from the same clock source to avoid asynchronous noise between the audio source and
the DSP.
Control
DBCLK, DBDA - Debug Clock, Debug Data 110, PINS 19, 20.
These pins are used for serial port debug. DBCLK clocks the data into or out of the debug port.
DBDA is a bi-directional data I/O. Software and a cable are available to interface the debug
port to a PC.
RESET - PIN 41.
The CS4920 enters a reset state while RESET is low. When in reset condition, all internal
registers are set to 0, the digital audio transmitter, serial control port, and ALTCLK pin are
disabled, and the stereo DAC is muted. The DAC is recalibrated and normal operation is
resumed, one internal clock cycle after the rising edge of RESET.
BOOT - PIN 40.
Boot enable pin. Pin must be set high to initiate the download of a program. While boot is high,
RESET must be toggled low. This starts the internal boot program.
Serial Control Port
REQ - Request Output, PIN 3.
This pin is driven low when the DSP needs servicing from an external device. A write to the
SCPOUT will cause the REQ to go low.
CS - Chip Select Input, PIN 44.
In SPI format, CS of the device the master wants to communicate with must be driven low.
This pin also serves as the communication format select during a reset or power up. When CS
is low during a reset or power up the SCP will be configured in I2C® mode. When high, it is
configured in SPI mode. The mode is selectable in software by setting the MO bit in the
SCPCN.
SCK/SCL - Serial Clock Input, PIN 2.
SCKlSCL clocks data into or out of the serial control port. This is always driven by an external
device because the CS4920 is always the slave.
CDOUT/SDA - Control Data Output I Serial Data 110, PIN 4.
In SPI mode, CDOUT is a data output for the serial control data. In I2C interface mode, SDA is
a bi-directional data I/O.
DS113PPO
5-41
-
------------~---------
CS4920
CDIN - Control Data Input, PIN 1.
In SPI mode, CDIN is the data input for the serial control port. It has no function in I2C®
mode.
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs.
Differential Nonlinearity
The worst case deviation from the ideal codewidth; expressed in LSBs.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the
test signal.
Instantaneous Dynamic Range
The Signal-to-(Noise + Distortion) ratio (S/(N+D» with a 1 kHz, -60dB from full scale DAC
input signal, with 60dB added to compensate for the small signal. Use of a small signal reduces
the harmonic distortion components of the noise to insignificant levels. Units are in dB.
Interchannel Isolation
The amount of 1kHz signal present on the output of the grounded input channel with 1 kHz,
OdB signal present on the other channel. Units are in dB.
Interchannel Gain Mismatch
The difference in output voltages for each channel with a full scale digital input. Units are in
dB.
Frequency Response
Worst case variation in output sigriallevel versus frequency over 10 Hz to 20 kHz. Units in dB.
Out of Band Energy
The ratio of the rms sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale
signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz.
5-42
DS113PPO
...........
............
..,-~
CDB4920
.~
.."
Semiconductor Corporation
CS4920 Evaluation Board
Features
General Description
The CDB4920 evaluation board provides an effective
means to evaluate the CS4920 broadcast audio decoder. Compressed audio data can be input via one of
two ribbon cable headers. The audio data is received
either single-ended or according to the RS-422 standard. The decompressed data is output as analog and
digital signals.
• Demonstrates recommended layout
and grounding arrangements
• Interfaces to parallel port of PC for
easy programming and evaluation
• On-board or externally supplied system
timing
• Accepts digital audio data transmitted
either single-ended or RS-422
• Digital and Analog Patch Areas
Serial Audio Input Headers
00
00
00
00
00
Control
Port
Header
Debug
Port
Header
ClKIN
00
00
00
00
00
00
00
00
00
00
00
00
00
A ribbon cable header is provided to access the serial
control port of the CS4920. Control can be accomplished by an external device, communicating in either
12C or SPI format, such as a personal computer or micro controller. Software is available that uses the SPI
format to download programs and issue control commands via the parallel port of an IBM compatible PC.
An additional ribbon cable header is provided to access the CS4920's debug port.
ORDERING INFO: CDB4920
+5VD DGND AGND +5VA
~~F
~--~
Digital
1/0
Buffers
Analog RCA
Audio
Phono
Outputs
Analog
Patch
Area
CS4920
RCA
Digital
Phono
Audio
7" Outputs
TOSLINK
7"
I--~I---~.
Digital
Patch
Area
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS113DB1
5-43
-
-..,-- ---_._--------~---
• Notes.
5-44
...........
..............
~
."
~~~.
CS8905
Semiconductor Corporation
Programmable Music Processor
General Description
Features
• Polyphonic up to 16 notes
• Multi-timbral up to 16 simultaneous
timbres
• Oscillator frequencies to 48 MHz
(46.875 kHz sampling rate)
• Stereo 16 bit digital audio output
• On-chip 256x15 Algorithm RAM, and
256x19 Parameter RAM
• Built-in sine and ramp data
• Addresses up to 1Mx12 sample ROM
directly, 64Mx12 using paging
• Single +5V supply CMOS, 50 mW
typical power dissipation
The CS8905 is a high performance programmable signal processor which is specially designed for music
and sound generation applications such as music synthesis and digital effects processing. This device
features 19-bit internal data paths, a 19-bit two's complement adder, a 12 x 12 two's complement multiplier,
two 24-bit accumulators and a 32-bit output shift register. As a music synthesizer, the CS8905 is capable of
generating 16 notes of polyphony with a high quality
16-bit stereo digital audio output at a 44.1 kHz sampling rate. For wave table synthesis applications, up to
64 Msamples of external sample memory may be addressed, and the CS8905 can generate linear
envelope segments under external microprocessor
control. The micro-programmable architecture of the
CS8905 also makes this device well suited for use as
a digital effects processing engine.
ORDERING INFORMATION
• 68 pin PLCC package
CS8905-CL 68-pin PLCC
slot
WAOWA19
wooWDll
wcs
00-
WOE
07
WWE
Preliminary Product Information
AOcs
A2.!!Q
INT
ALG
Xl CKOUT
X2
CLBO DABD WSSO
WA
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV '93
DS116PP4
5-45
-
---------'
------'
---------
CS8905
ABSOLUTE MAXIMUM RATINGS (All yoltages with respect to OV, GND=OV)
Parameter
Ambient Temperature
(Power Applied)
Symbol
Min
Typ
TA
-40
-
-65
-0.5
VCC
-0.5
-
-
-
Symbol
Min
VCC
4.75
TA
Storage Temperature
Voltage on any Pin
Supply Voltage
Max
Units
+85
°C
+150
°C
VCC+0.5
V
6.5
V
10
mA
Typ
Max
Units
V
0
-
5.25
70
°C
Symbol
Min
Typ
,Max
Units
VIL
-0.5
-
0.8
V
High-Level Input Voltage
VIH
2.0
-
Vcc+0.5
V
Low-Level Output Voltage at IOL=3.2 mA
VOL
-
0.45
V
High-Level Output Voltage at IOH=-0.8 mA
VOH
2.4
-
-
V
ICC
-
10
25
mA
Maximum 10L per I/O Pin
RECOMMENDED OPERATION CONDITIONS
Parameter
Supply Voltage
Operating Ambient Temperature
D.C. CHARACTERISTICS (TA=25°C, Vcc=5V±5%)
Parameter
Low-Level Input
Voltag~
Power Supply Current at
Oscillator Frequency=45.1584 MHz
Notes:
5-46
(Note 1)
1. Digital Inputs at Logic "1" = Vcc; Logic "0" = DGND, Power Supply Current does not include output
loading
DS116PP4
----------- -----------
CS8905
A.C. CHARACTERISTICS (TA=25°C, Vcc=5V±5%, Oigitallnputs at Logic "1 "=Vcc; Logic "O"=OGNO,
load capacitance=80pF for all outputs except X2)
Parameter
Symbol
Min
Typ
Max
Units
1/tclcl
0
45.1584
48
MHz
tcswr
50
twrcs
20
AO-A2, 00-07 Valid to Rising WR
tadwr
20
AO-A2, 00-07 Valid After Rising WR
twrad
10
-
ns
WR High to CS High
twr
50
-
-
ns
-
ns
50
ns
Oscillator Frequency
CS Low to WR Low
WR Pulse Width
CS Low to RD Low
tcsrd
50
RO High to CS High
trdcs
20
RD Active to Valid Oata Out
trdld
-
Data Out Hold From RO
trdhd
10
AO-A2 Valid to Valid Oata Out
tad
-
AO-A2 Hold From RD
trda
10
Recover From Control Write
WAOO-19 Valid From WWF or WPHI Micro-Instruction
twadmi
-
WDO-11 Valid Before WXY Micro-Instruction
tmiwd
10
WOE High From RSP ClearB Micro-Instruction
twoemi
WOO-11 Out Valid (Y Register) From WOE High
twoewd
-
tclbd
WWE Low From WOE High
twoewe
WWE High to WOO-11 High Z
twewd
WWE High to WOE Low
twewoe
tcswr
WR
-
trecover 32xtclcl+ 10
CLBD Period
cs
-
I'
..I
twr
32xtclcl
tclcl
2 x tclcl
tclcl
tclcl
ns
ns
ns
ns
-
ns
50
ns
-
ns
ns
10
ns
-
-
ns
10
ns
-
ns
ns
ns
ns
. twrcs
I
I
I
I
'i'
I
tadwr
I twrad
'I'
"
AO-A2
00-07
Microprocessor Write to CS890S
DS116PP4
5-47
-
_.--..--_.-.
__.._-_
...-.
CS8905
n
tcsrd
trdcs
CS
RD
DO-D7
Microprocessor Read from CS8905
2 xtclcl
r----1
I
Microinstruction
I
WXY
I
WADO
WAD19
twadmi
WCS
-J tmiwd
WDO
WDll
Sample Memory Read
2 x tclcl
r---1
Microinstruction
I
1
2
I
~twoemi
2
l=RSP ,
2=RSP ,
I
WOE
I,
WDO
WDll
WWE
1
twoe)Nd
1
___h_i9_h_Z__7:__~~~________~~__--4~~__+I~h=i9~hZ=-_________
I,
twoewe
'I
-------11
twewd;..---.l
1-,~~~_tt~ww~eernWW~(o~e~~~~~~~
__
Sample Memory Write
5-48
DS116PP4
----------- -----------
CS8905
2048. The sample period, or synthesis frame, is
divided into 16 time slots, which are referred to
as synthesis slots. A sound generation algorithm
for the CS8905 consists of 32 microinstructions,
and one algorithm is executed during each synthesis slot.
FUNCTIONAL DESCRIPTION
The CS8905 is a specialized high speed programmable signal processor for music and sound
generation applications. The CS8905 signal processing unit includes a 19-bit two's complement
adder, a 12 x 12 two's complement multiplier,
two 24-bit accumulators and a 32-bit output shift
register. The devices' internal data paths are 19
bits wide. Typical connections for a CS8905based MIDI music synthesizer are indicated in
Figure 1.
An on-chip 256 x 15 Algorithm RAM (A-RAM)
holds eight different synthesis algorithms [4 algorithms in slow mode]. A 256 x 19 Parameter
RAM (P-RAM) provides 16 words of parameter
data storage for each synthesis slot. The sound
generation functions of the CS8905 are controlled by an external microprocessor which has
access to the Algorithm RAM and the Parameter
RAM. The Parameter RAM block for each synthesis slot provides a means for the external
microprocessor to control the parameters of the
synthesis algorithm used by the slot, and this
The CS8905 operates at one of two possible
sampling rates. In the normal operating mode,
the sampling rate is equal to the crystal oscillator
frequency divided by 1024. In the "slow" mode,
the sampling rate is the oscillator rate divided by
+ 5V
...
'\.
Supply
110
MIDI
In
)----.
MicroController
....
.....
......
......
21
28
26
32
127
144
161
AO-A2
WAO-WA19
DO-D7
WDO-WD11
-
CS
WCS
CS8905
-
--
RD
WOE
36
Sample
Memory
....
.....
56
60
WR
--
RESET
WSBD
34
~
-
CLBD
Crystal
or Clock
Source
---..
X1
DABD
X2
GND
1
I
38
39
DAC
r---.
Stereo
Analog
Audio
Out
37
35
1 1
18
52
V
Figure 1. Typical Connection Diagriun
DS116PP4
5-49
-
----------------------
CS8905
memory block also provides working memory
for the synthesis algorithm. The external microprocessor may write to either the A-RAM or the
P-RAM during operation.
For music synthesis applications, each time slot
is independent of the other slots, and each time
slot may be used to generate one sound or note.
During each slot time, one synthesis algorithm is
executed and the output sample data from that
algorithm is written to the left and right channel
24-bit accumulators. The signal processing unit
controls the level and balance of the output from
the slot by scaling the sample output to the accumulators under the control of the output mix
parameters specified in the P-RAM block for
that slot. The accumulators are specially designed to prevent digital overflow. At the end of
each frame, the contents of the accumulators are
transferred to the 32-bit output shift register and
the accumulators are cleared. The shift register
clocks the resulting sample data out serially to
the external Digital-to-Analog Converter (DAC).
For other signal processing applications, such as
generation of digital reverberation and chorus effects for musical applications, the 16 time slots
available during each sample period may be used
to run subroutines of a larger algorithm. In this
case, parameters may be passed between time
slots through the A register of the adder circuit,
through the multiplier, or through external RAM.
The CS890S can directly address up to 1 M x 12
of external memory. For high quality sampling
algorithm implementations, paging techniques
may be utilized to allow the CS890S to address
up to 64 Msamples of external sample memory.
Sine wave and ramp data is built into the chip.
The CS890S is capable of generating linear envelope segments with a specified slope to allow
creation of piecewise linear amplitude envelopes
under external microprocessor control.
Microprocessor Interface
An external microprocessor controls the CS890S
synthesis functions by accessing the CS890S
Control Register, Interrupt Register, Algorithm
RAM (A-RAM), and Parameter RAM (P-RAM).
The Microprocessor electrical interface is a
standard bus interface, comprised of the address
lines AO-A2, the data lines DO-D7, the Chip Select signal CS, the Write signal WR, and the
Read signal RD.
If the external microprocessor timing and the
CS890S timing are asynchronous, then an external write synchronization circuit, such as that
shown in Figure 2, should be employed to synchronize the WR signal from the external
WR
74HC74
~
+5V
CKOUT
Q1
74HC32
SWR
(toCS8905)
~
02
SWR
~
Figure 2. Write Synchronization Circuit
5-50
DS116PP4
_.-_..---_......_-_
..._.-.
microprocessor with the CS8905 tlllung. This
circuit assumes that data from the microprocessor is valid on the leading edge of WR, and that
the CKOUT period is shorter than the pulse
width of WR. If the external microprocessor
timing and the CS8905 timing are derived from
the same oscillator source, then the write synchronization circuit is not necessary.
The 256 x 15 Algorithm Ram (A-RAM) is organized as either 8 blocks of 32 words, or 4
blocks of 64 words in slow mode. Each word
contains one micro-instruction, and each block
of 32 instructions [64 in slow mode] makes up
one algorithm. The last two locations in each
block are reserved for microprocessor access and
algorithm changes. Thus an algorithm consists of
30 micro-instructions [62 iIi slow mode] for
sound generation. Internally, the CS8905 operates on a Master Clock, with a frequency equal
to the crystal oscillator frequency divided by
two. Each micro-instruction is executed in one
cycle of the Master Clock.
The 256 x 19 bit Parameter RAM (P-RAM) is
organized as 16 blocks of 16 words each. There
is one 16 word x 19 bit block of P-RAM associated with each synthesis slot. The 16 word block
of P-RAM associated with a particular synthesis
slot is used to specify the synthesis algorithm
number and the associated parameter data to be
used for that synthesis slot. The P-RAM also
functions as working RAM for the synthesis algorithm computations. The parameter types,
parameter data formats and parameter addresses
required for that slot depend on the specific synthesis algorithm being utilized for the slot.
However, parameter location 15 in each 16-parameter block utilizes a common format which
specifies the algorithm to be used for the slot.
Location 15 also contains the Idle bit (I) which
is used to force the associated synthesis slot to
an idle mode, and the Interrupt Mask bit (M)
which is used to enable/disable the generation of
interrupts from that synthesis slot. Details of the
DS116PP4
CS8905
CS8905 micro-instructions and associated parameter data formats are not covered in this
document.
The Control Register is a 4-bit write-only register which is comprised of the foiIowing control
bits:
SSR
0 - Set Sampling Rate = Crystal
Oscillator Frequency/1024.
1 - Set Sampling Rate = Crystal
Oscillator Frequency/2048
(SSR = 1 selects the slow mode).
IDL
0 - Normal Operation.
1 - All slots are forced to idle mode,
independent of the P-RAM
contents.
SEL
0- Select Access to P-RAM.
1 - Select Access to A-RAM.
WR
0-
Request a Read from P-RAM
orA-RAM.
1 - Request a Write to P-RAM
orA-RAM.
The Control Register is accessed by first performing a Write operation to the CS8905 with
address line A2=1 (Address lines Al and AO are
"don't care" conditions). Note that a change of
the Control Register IDL bit from 0 to 1 may
take up to 1.5 Jls [3 Jls in slow mode] to take
effect.
To write to the CS8905 P-RAM or A-RAM, the
following steps must be taken:
1. Write the desired address to the CS8905
2. Write the data to the CS8905
3. Write to the CS8905 Control Register, settingWR=1
4. Allow 1.5 Jls [3 Jls in slow mode] for the
write cycle to be completed.
5-51
-
----------------------
CS8905
To read from the CS8905 P-RAM or A-RAM,
the following steps must be taken:
1. Write the desired address to the CS8905
2. Write to the CS8905 Control Register, setting WR=O
The Interrupt Register is an 8-bit read-only register which indicates the slot number and the
parameter address which caused the interrupt.
The parameter address identifies one parameter
location within the I6-parameter P-RAM block
associated with a slot. The Interrupt Register is
accessed by reading from the CS890S at address
A2AIAO = 000. Reading the Interrupt Register
will not reset the interrupt cause. After initially
reading the Interrupt register, the microprocessor
should change the slot parameters to remove the
interrupt cause, then perform a dummy read of
the Interrupt Register (read the register and discard the result) to clear any possible interrupts
which may be pending from the same cause.
Most musical synthesis applications do not need
to utilize the interrupt features of the CS8905.
3. Allow 1.5 Ils [3 IlS in slow mode] for the
read cycle to be completed.
4. Read the data from the CS8905
The desired address is written to the CS8905 by
performing a write cycle with A2AIAO=OOO.
The address formats for P-RAM, A-RAM (SSR
bit=O), and A-RAM (SSR bit=I) are each different. These formats are given in Table 1.
The data formats for reading or writing fromlto
the 19 bit P-RAM and the IS-bit A-RAM are
given in Table 2.
Type of Address
(ReadlWritten)
A2
Address
A1
AO
07
Address Data Format
04
06
05
P-RAM Address
0
0
0
V3
V2
V1
VO
03
02
DO
01
MAD3 MAD2 MA01
MADO
A-RAM with SSR=O
0
0
0
AL2
AL1
ALO
PC4
PC3
PC2
PC1
PCO
A-RAM with SSR=1
0
0
0
AL2
AL1
PC5
PC4
PC3
PC2
PC1
PCO
Notes:
1.
2.
3.
4.
VO-V3 = SyntheSIS Slot Number
MADO-MAD3 = Address of specific parameter within the 16 word block associated with the specified slot
ALO-AL2 = Algorithm number
PCO-PC5 = Address of specified micro instruction within the 32 word block [64 word block in slow mode]
associated with the specified algorithm number.
Table 1. Data Format for writing Address Information to tbe CS890S
Type of Data
(ReadlWritten)
P-RAM data
A-RAM data
Notes:
Address
A1
AO
Data Format
06
05
04
03
02
01
DO
0
0
0
0
1
1
1
0
1
87
815
86
814
85
813
84
812
83
811
X
X
X
X
X
82
810
818
81
89
817
80
88
816
0
0
0
1
1
0
17
16
114
15
113
14
112
13
111
12
110
11
19
10
18
A2
07
X
1.80-818 = P-RAM parameter data (19 bit word)
2. 10-114 = A-RAM micro instruction data (15 bit word)
Table 2. Data Format for reading/writing P-RAM or A-RAM data to CS890S
5-52
OS116PP4
---------------------Sample Memory Interface
The CS8905 provides a 20 bit address bus and
12 bit wide data bus for access to external memory. The memory interface signals are output
under micro-instruction control. Therefore, the
timing requirements for external memory access
are algorithm dependent.
The 20 bit address bus is made up of 8 bits of
waveform address information from the WF register, and 12 bits of phase information from the
PHI register. The upper 8 bits of the address
bus, WA12-WA19, represent the 8 least significant bits of the 9 bit WF register. The lower 12
bits of the address bus, WAO-WAll, represent
the 12 most significant bits of the 19 bit PHI
register.
The 19 bit PHI register can be subdivided into
an integer part and a fractional part. The relative
sizes of the integer and fractional parts of the
phase will depend on the memory size and memory addressing techniques used in an application.
The integer part of the phase is that part of the
PHI register which is used to address external
memory (12 bits maximum). The fractional part
of the phase is that part of the PHI information
which does not address external memory (7 bits
minimum). The size of the fractional part of the
phase affects the playback frequency accuracy in
wave table synthesis applications.
The CS8905 is capable of directly addressing a
maximum of 1 Msample of external memory. In
this case the fractional part of the phase is 7 bits.
This provides sufficient frequency resolution for
samples which will be replayed without pitch
transposition. However, for implementations
which will shift the pitch of stored samples during playback, a minimum of 9 bits of fractional
phase information is recommended. This limits
the memory size for direct addressing to 256
Ksamples. For larger transposable sample memo-
DS116PP4
CS8905
ries, a paged address system should be implemented. Transposable sample memory sizes of
up to 64 Msamples can be implemented with excellent frequency accuracy using paging. Paging
requires only one additional micro-instruction
per memory access compared to direct addressing.
Figure 3 depicts a 32K x 8 RAM sampling
memory which is directly addressed by the
CS8905. In this case, the five lower address
lines WAO-WA4 are not used to address sample
memory, and the fractional part of the phase is
increased to 12 bits.
Figure 4 shows a 1M x 12 bit sample memory
which is organized as 4 pages of 256 Ksamples
per page. Each page is divided into 512 waves
of 512 samples/wave. The address lines WA12
and WA13 are used to select one of the four
pages. In this case the wave number (WF register data) is output and captured from address
lines WA2-WAlO by the 74HC174 latches on the
falling edge of WCS. The sample address within
the page (the integer part of the phase) is then
taken from address lines WA3-WAll. The fractional part of the phase has 10 bit resolution,
allowing good frequency accuracy. Note that in
this example, 12 bit samples are stored in two
8-bit wide ROMs. The smaller 4Mbit ROM
holds the 4 lower data bits for two consecutive
samples in each of its' 8-bit memory locations.
The correct nibble is selected using the
74HC157 based on the state of address line
WA3. Address lines WA14-WA19 could be utilized as additional page address bits to expand
this addressing mechanism to a maximum of 256
pages (64 Msamples) while maintaining 10 bits
of resolution in the fractional part of the phase.
When 8-bit sample memories are utilized, the
unused data bus pins on the CS8905 should be
pulled down to ground through 10 kOhm resistors.
5-53
-
----------------------
CS8905
For high quality sampling algorithms which employ paged addressing, an external buffer circuit
may be added to the memory interface circuitry
to allow.the CS890S to perform linear interpolation between sample values read from memory.
The buffer. is used to selectively gate the lower
lines of the CS890S address bus onto the data
bus. This allows the synthesis algorithm to read
the most significant bits of the fractional phase
information via the data bus for use as a weighting constant in the interpolation calculations.
and the stereo output data stream DABD. The
digital audio output format for the CS890S is
shown in Figure S. Note that the most significant
bit (msb) of the sample is output from the
CS890S 112 bit time (112 clock cycle of the
CLBD bit clock) after the rising or falling edge
of WSBD. This timing format may be converted
to a more common format, wherein the msb is
output one full bit time after the edge of CLBD,
using either of the two circuits shown in Figure 6.
DAC Interface
The digital audio output from the CS890S has a
positive DC offset of S% of the full scale value.
Some low cost DACs generate a considerable
amount of electrical noise when transitioning
The CS890S DAC interface consists of a
left/right clock signal WSBD, a bit clock CLBD
CS8905
--¥.-
CLBD
DABD
W5BD
~
WWE
WOE
A2
WCS
A1
WA19
AD
WA18
WA17
WA16
~ D7
WA15
~ D6
WA14
D5
WA13
D4
WA12
D3
WAH
D2
WA10
~ D1
~
WA9
DO
WAS
~
INT
WA7
WA6
WA5
-.M X1
WA4
WA3
WA2
--.-M. X2
WA1
WAD
CKOUT
WW
.
D DWWWWWWWWWW
11DDDDDDDDDD
109876543210
RES
- 4 cs
~
RD
WR
t}==
T-
~
~.
44 44
1 23
o
~
~~
7
6
5
2
3
63
58
62
!ill
57
~
256 Kbil ROM
~
WEI
DE
CE
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AD
07
06
05
04
03
02
01
00
-
-
~
l ~~U3~
~:
--,l---
Figure 3. Direct Addressing of 32Kx8 Sample Memory
5-54
DS116PP4
,=,...,
'1=
....,
'"
......~
Q)
"'II
~
.....
="
CLBD
DABD
CS8905
W5BD
WWE
WOE
WCS
WA19
WA18
WA17
WA16
WA15
WA14
WA13
WAll
WA12
WA10
WA9
WAS
WA7
~~
WA4
~:
WA1
WAD
CKOUT
'g 'g WWWWWWWWW
11'gDDDDDDDDD
109876543210
. . . ~ ~ • • • • • ...
-
CE
DE
~~il~
CE
DE
A19NPP
AlB
A17
A16
A15
A14
A13
A12
A1a
A19NPP
A17
AlB
A15
A14
WAS
D6
05
06 RA12
02
01
Q2
01
g;
as RA16
~ RA
~~~
An
All
~o
Al0
AI3
G
J\IB
AS
A7
07
~
4B
4A
38
4Y
05
SA
3Y
02
01
2B
2A
lB
lA
A6
A:3
A2
A1
AS
06
g~
AO
I
WD3
2Y
1Y
74HC157
~
CO
Figure 4. IMx12 Sample Memory Using Paging
~
I
g
-_.._-_.
;.,==~;=~
CS8905
from zero (an input code of all zeros) to minus
one (an input code of all ones). The S% DC offset can dramatically reduce the signal to noise
level for small signals when using this type of
DAC. If the .digital output from the CS890S is
input to another digital processing device, the
offset may be removed by subtracting the value
ODOO Hexadecimal from each sample received
from the CS890S.
Power Connections and Decoupling
All power and ground pins on the CS8905 device should be connected to the appropriate low
impedance supply planes using the shortest trace
lengths possible.
The ground reference for the DAC should be
connected directly to the CS890S aND at 'pin
35, and this should be the only connection between analog ground and digital, ground,
Recommended decoupling consists of four 0.1
uF ceramic decoupling capacitors between Vee
and aND, one at each of the four sides of the
IC. These capacitors should be placed as close to
the IC as possible. In addition, place one 10 uF
Tantalum capacitor from Vee to aND near the
crystal oscillator circuit.
Oscillator Circuit
Power-up Reset
The CS8905 timing may be generated using the
internal oscillator (external crystal circuit) or using an external oscillator. Trace lengths should
be kept to a minimum, and the board layout
should include ground plane beneath the oscillator circuit components.
The RESET signal initializes the CS8905. The
initialization includes the following:
1. Initialize internal master clock phasing
2. Select high sampling rate (sets SSR=O in
the Control Register)
3. Set the general idle bit IDL=l in the Control Register
4. Force the micro-instruction counter to 31
S. Force the slot number to 0
If an external oscillator circuit is utilized, shield
the input trace from the oscillator to the CS8905
Xl input and keep the trace. lengths to a minimum. The external clock supplied to the Xl pin
should be CMOS level. Pin X2 should be left
open.
IMSB
I
left sample
LSB MSB
DABD
I I
I II I I I I I I I I I I I I
WSBD
~L____~______________________________~
right sample
I I I I I I I I I
CLBD
1.-.1 tclbd
Figure 5. eS8905 Digital Audio Output Format
5-56
DS116PP4
_.-_..--_._.
__.._-_
...-.
CS8905
The RESET input must be held low until the oscillator circuit has stabilized. The CS8905
internal oscillator is enabled during RESET,
other functions of the device are held in an idle
mode while RESET is low.
Schematic &Layout Review Service
-
Confirm Optimum
Schematic & Layout
For Our Free Review Service
Call Applications Engineering.
ClBD
from CS8905
470
ClBD'
(to DAC)
W.
lOOp'
Solution 1
+5V
~
DABD
from CS8905
D P Q
,-----
ClBD
from CS8905
I>
74HC74
DABD'
(to DAC)
C
Jv
74HC04
ClBD'
(to DAC)
Solution 2
Figure 6. Digital Audio Output Format Conversion
DS116PP4
5-57
_.-_..---.-.
__.._-_
...-.
CS8905
PIN DESCRIPTIONS
GNO
WA16
WA1S
WWE
WA17
WA1S
WA19
WAO
WA1
vee
WA2
00
01
02
03
04
05
GNO
06
07
es
AO
A1
A2
INT
WR
vee
-----.!:m
SYNe
ALGZ
FSH
RESET
eKOUT
X1
WA10
WA11
WA9
WA12
WAS
WA14
WA7
vee
WOE
WA6
WA13
WAS
wes
WA4
W07
WA3
p---GNO
W06
woo
WOS
W01
W04
W02
W03
vee
woo
W09
W010
W011
WSBO
eLBO
OABO
X2
GNO
Pins
GND - Ground. PINS 1, 18, 35, and 52.
Ground, all ground pins on the device must be connected to a low impedance ground.
VCC - +5V supply. PINS 10,27,44, and 61.
+5V supply, all vee pins on the device must be connected to a low impedance +5V supply.
nO-D7 - Data I/O. PINS 12, 13, 14, 15, 16, 17, 19, and 20.
These bi-directional data lines are used to transfer data between an external microprocessor and
the eS8905.
5-5S
OS116PP4
.._-_
._.-.
_.-_..--__
...
CS8905
AO-A2 - Address Select Input from Microprocessor. PINS 22, 23, and 24.
These pins allow an external microprocessor to select the CS8905 control register or specify
data registers for read/write operations.
CS - Chip Select Input. PIN 21.
This is the CS8905 chip select input from an external microprocessor. Active low.
RD - Read Strobe Input from Microprocessor. PIN 28.
This signal is the read strobe from an external microprocessor. Active low.
WR - Write Strobe Input from Microprocessor. PIN 26.
This signal is the write strobe from an external microprocessor. Active low.
INT - Interrupt Request Output to Microprocessor. PIN 25.
This output will be driven low by the CS8905 to interrupt an external microprocessor.
III
Xl - Xtal or External Clock Input. PIN 34.
This is the input pin for the internal oscillator circuit. A crystal or external clock frequency of
48 MHz maximum may be connected. If an external oscillator is used, it should be CMOS
logic level.
X2 - Xtal Output Connection. PIN 36.
This pin is the internal oscillator circuit output. If an external oscillator is used, this pin should
be left open.
CKOUT - Output Clock. PIN 33.
This output clock has a frequency equal to the CS8905 oscillator frequency divided by four.
RESET - Chip Reset Input. PIN 32.
This active low input is used to reset and initialize the CS8905. This signal should be held low
for at least 10 ms after power up.
DABD - Serial Data Out to External DAC. PIN 37.
This signal is the stereo 16-bit digital audio data output from the CS8905 to an external DAC.
CLBD - Clock Output to External DAC. PIN 38.
This output is the bit clock for the DABD signal.
WSBD - LeftJRight Channel Select Output to External DAC. PIN 39.
This is the left/right word clock for the DABD signal.
WAO-WA19 - External Sampling Wave Memory Address Output. PINS 8, 9, 11, 53, 55, 57, 59,
62, 64, 66, 68, 67, 65, 58, 63, 3, 2, 5, 6, and 7
These address lines are used to address an external sample memory.
DS116PP4
5-59
-_-__-_
.. ...-.
-. ..--_._.
CS8905
WDO-WDll - External Sampling Wave M€!mory Data Output. PINS 50,48,46,45,47,49,51,
54, 43, 42, 41, and 40.
These data lines are used to pass sample data frornlto external sample memory.
WCS - External Sampling Wave Memory Chip Select Output. PIN 56.
This is an active low chip select signal for external sample memory.
WOE - External Sampling Wave Memory Output Enable. PIN 60.
This signal is an active low output enable strobe pin for external sample memory.
WWE - External Sampling Wave Memory Write Output. PIN 4.
This signal is an active low write strobe for external RAM sample memory.
SYNC - Synchronize Input. PIN 29.
This active low signal is used for synchronization between several CS8905 devices. This signal
should be tied to Vee under normal operating conditions.
ALGZ - Zero Algorithm Input. PIN 30.
This active low signal will force execution of algorithm zero. This signal should be tied to
Vee under normal operating conditions.
FSH - Fast Shift Input. PIN 31.
This active low input signal forces the serial data DABD to be shifted out at the master clock
rate rather than the CLBD rate. This signal should be tied to Vee under normal operating
conditions.
5-60
DS116PP4
......... ....
~
..,..,~.
..,
~~~~
CS9203
Semiconductor Corporation
Advanced Music Synthesizer
Features
General Description
• Polyphonic up to 32 notes
• Multi-timbral up to 32 simultaneous
timbres
• 15 built-in synthesis algorithms
• On-chip high speed adder,
multiplier, and 24 bit accumulators
with overflow protection
The CS9203 is a high performance signal processor
which is specially designed for high-quality music synthesis applications. Fifteen built-in music synthesis
algorithms make the CS9203 extremely flexible, and
the advanced features associated with it's PCM sampling algorithms, such as linear interpolation between
samples, linear segment envelope generator, and 12
dB variable Q filtering, make the CS9203 a superb
wave table synthesis engine. Dual stereo digital audio
outputs are provided to allow the addition of an external effects processor, such as the CS8905. The 32
note polyphony and 32 part multi-timbral capabilities of
the CS9203 make it an ideal choice for General MIDI
(GM) synthesis applications, including musical instruments, MIDI sound modules, Karaoke machines, and
high quality Personal Computer sound cards.
• Built-in sine wave data
• Addresses up to 8Mx12 external
samRling memory (ROM, SRAM, or
DRAM)
• Two stereo 16 - 20 bit digital audio
outputs (four audio outputs)
• Independent pan and volume mix
assignable for each voice
• +5V supply CMOS, 50 mW power
• 68 pin PLCC package
ORDERING INFORMATION
CS9203-CL 58-pin PLCC
GNO VCC
X1
X2
CKOUT
XCLK
RESET
INT
:
•
b~~~Greg.
INTERRUPT reg.
TIMING generator
PARAMETER
RAM (P-RAM)
5t2'19
SLOT
(0 to 31)
Parameter select
(0 to 15)
19 bits internal bus
SIGNAL
PROCESSING
UNIT
WAO- WOO- RAS CAS WOE WWE CLBO
WA16 W011
WSBO
OABO
OAFO
Preliminary Product Information IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV '93
DS117PP4
5-61
-
-_ _-_
.. ...-.
-.. ..--_._.
__
CS9203
ABSOLUTE MAXIMUM RATINGS (All voltages with respect to OV, GND=OV)
Parameter
Ambient Temperature
Symbol
Min
Typ
Max
Unit
-
-40
-
+85
°C
+150
°C
-0.5
Vcc+0.5
V
VCC
-0.5
-
-
-
Symbol
(Power Applied)
Storage Temperature
Voltage on any Pin
Supply Voltage
-65
6.5
V
-
10
rnA
Min
Typ
Max
Units
VCC
4.75
V
0
-
5.25
TA
70
°C
Symbol
Min
Typ
Max
Unit
VIL
-0.5
-
0.8
V
High-Level Input Voltage
VIH
2.0
V
VOL
-
High-Level Output Voltage at IOH=-0.8 mA
VOH
2.4
-
VCC+0.5
Low-Level Output Voltage at IOL=3.2 rnA
ICC
-
10
Maximum 10L Per 110 Pin
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Ambient Temperature
D.C. CHARACTERISTICS (TA=25°C, Vcc=5V ±5%)
Parameter
Low-Level Input Voltage
Power Supply Current
Notes:
5-62
(Note 1)
crystal frequency=50.000MHz
0.45
V
-
V
25
mA
1. Digital Inputs at Logic "1" = Vcc; Logic "0" = DGND, Power Supply Current does not include output
loading
DS117PP4
----------------------
CS9203
SWITCHING CHARACTERISTICS (TA=25°C, Vcc=5V ±5%, Digital Inputs at Logic "1" = Vcc;
Logic "0" = DGND, load capacitance=80pF for all outputs except X2)
Parameter
Symbol
Min
Typ
Max
Unit
MHz
Oscillator Frequency
l/tclcl
0
48.0
50
CS Low to WR Low
tcswr
50
-
ns
WR High to CS High
twrcs
20
-
-
ns
AO-A 1, 00-07 Valid before
RisingWR
tadwr
20
-
-
ns
AO-A 1, 00-07 Valid after
Rising WR
twrad
0
-
-
ns
WR Pulse Width
twr
50
CS Low to RD Low
tcsrd
50
RD High to CS High
trdcs
20
RD Active to Valid Data Out
trdld
-
Data Out Hold from RD
trdhd
10
AO-A 1 Valid to Valid Data Out
tad
-
AO-A 1 Hold from RD
trda
10
Recover from Control Write
trecover 34xtclcl+ 10
CLSD Period
tclbd
-
34xtclcl
WA Valid before RAS or CAS H to L
tswa
tclcl-5
-
thwa
tclcl-5
tazwoel
tdwoeh
0
40
tdh
0
-
WA Valid after RAS or CAS H to L
WD Floating to WOE Low
Valid Data in to Rising WOE
Data in Hold after Rising WOE
50
ns
ns
ns
ns
-
ns
50
ns
-
ns
ns
ns
ns
ns
ns
ns
X2
WAO-WAll
valid
I
I'
RAS!
CAS
tswa
':r------
1 - - - -
I'
lhwa
WOE
.1.
•r1 azwoel
I
(CAS case only)
Sample Memory Address Timing
DS117PP4
5-63
-
------------ --...----'-'-
CS9203
CASt
RAS/
WOE
tdwoeh
,tdh
;<-'---------.jo',~'1
valid data
WD
Sample Memory Data Bus Timing, Sample Memory Read
trdcs
n
tcsrd
CS
'I
1
1
1
I'
r-----------I!
RO
!
1
I,
trdld
trdhd
~
'I
00-07
trda
~
1
AO-A1
Microprocessor Read Cycle
tcswr
twrcs
twr
CS
WR
I,
tadwr
,I,
twrad
,I
AO-A1
00-07
Microprocessor Write Cycle '
5-64
DS117PP4
.._-_
.-_
_
..--_._.
__
...-.
CS9203
FUNCTIONAL DESCRIPTION
The CS9203 is a specialized high performance
signal processor for music synthesis applications.
The CS9203 signal processing unit includes a
high speed adder, a multiplier, and specialized
circuitry for phase computation, interpolation between samples, and amplitude envelope
generation. The devices' internal data paths are
19 bits wide, and four 24-bit accumulators are
used to generate the output samples for the four
digital output channels of the device (two stereo
output channels). The CS9203 has fifteen different built-in ROM-coded synthesis algorithms
which can be used to generate a wide variety of
sounds. A sixteenth algorithm is included for
DRAM refresh in applications which store PCM
sound samples in Dynamic RAM
MIDI
In
>--
MicroController
....
...
63
65
The sample memory interface allows PCM sample-based synthesis algorithms to access sound
samples stored off-chip in DRAM, SRAM, or
ROM. Sine wave data is contained on-chip. An
on-chip Parameter RAM (P-RAM) block provides RAM workspace for the synthesis
algorithms. The CS9203 synthesis functions are
controlled by an external microprocessor. Typical connections for a wavetable synthesis
application are indicated in Figure 1.
The CS9203 operates on a synthesis frame timing basis. A stereo digital audio sample is output
at the end of each synthesis frame. Thus the
output sampling rate is the same as the synthesis
frame rate. The synthesis frame is divided into a
number of time slots, which are referred to as
synthesis slots. One of the CS9203's 15 synthe-
AO,A1
WAO-WA16
DO - 07
WDO-WD11
CS
RAS
CS9203
-
RD
-
CAS
--
64
-
11
--
WR
WOE
WSBD
66
67
~
.........
Sample
Memory
25
24
22
RESET
CLBD
Crystal
or Clock
Source
...
X1
DABD
X2
GND
2°1
35 1
16
15
DAC
r---
Stereo
Analog
Audio
Out
21
19
4915°1681
7
Figure 1. Typical Connection Diagram
DS117PP4
5·65
-
--------------
---~-.---sis algorithms is executed during each synthesis
slot, and in general,each synthesis slot generates
one note or voice. The number of synthesis slots
in the synthesis frame can be set to any even
number from 16 to 32. The length of a synthesis slot is 68 clock cycles (tclcl x 68), and the
length of the frame is then (tclcl x 68 x N),
where N is the number of synthesis slots per
frame (N can be considered to be the number of
notes of polyphony). The frame rate, or sampling rate, is the inverse of the frame length:
Output Sampling Rate = lI(tclcl x 68 x N) =
Crystal Oscillator frequency/(68 x N) where N is
the number of synthesis slots per frame.
The 512 x 19 bit Parameter RAM (P-RAM) is
organized as 32 blocks of 16 words each. There
is one 16 word x 19 bit block of Parameter
RAM associated with each synthesis slot. The
16 word block of P-RAM associated with a particular slot holds all of the parameter data for
that slot. The last word in the P-RAM block
specifies which of the 16 built-in algorithms will
be utilized for the synthesis slot. The specific
data and format for the remaining 15 words of
P-RAM in the block are algorithm dependent.
During each slot time, one algorithm is executed
and the output sample from that algorithm is sent
to the four 24-bit accumulators. The signal
processing unit controls the level and balance of
the output from the slot by scaling the sample
output to the accumulators under the control of
the mix parameters located in the P-RAM block
for that slot. The accumulators are specially designed to prevent digital overflow. At the end of
each frame, the contents of the accumulators are
transferred to the four 20-bit output shift registers and the accumulators are cleared. The shift
registers clock the resulting sample data out serially to the external Digital-to-Analog
Converter(s).
Seven of the CS9203 synthesis algorithms utilize
external PCM sound samples for lligh quality ,
sound generation. Algorithm number 1, the
5-66
CS9203
High Quality Sampling algorithm, employs linear interpolation for frequency shifting, followed
by a 12 dB variable-Q low-pass filter for tiinbre
adjustment and elimination of noise which may
be naturally created when transposing a samples'
pitch during playback. The low-pass filter implementation has a variable cutoff frequency which
may be controlled using a built-in envelope generator. A second envelope generator is utilized
to control the final output amplitude for the resulting sound.
Other useful PCM sample-based algorithms include a 3X sampling algorithm for drums, a 2X
sampling algorithm with 12 dB fixed-Q variablecutoff low-pass filter, a 2X sampling algorithm
with I2dB variable-Q variable-cutoff low-pass
filter, a IX sampling plus white noise algorithm
with 12 dB variable-Q variable-cutoff low-pass
filter, a IX sampling algorithm with 24 dB variable-Q variable-cutoff low-pass filter, and an
algorithm which combines a IX pcm sampling
operator with an algorithmic synthesis technique.
The 3X sampling algorithm allows a single voice
of polyphony (a single synthesis slot) to generate
three simultaneous drum sounds. Separate envelope generators are used to control the output
amplitude for each of the three sounds. The 2X
sampling algorithm with 12 dB fixed-Q variablecutoff low-pass filter is useful for generating
"partials"-based sounds without the severe polyphony sacrifice normally associated with these
techniques.
The remaining eight algorithms in the CS9203
employ algorithmic synthesis techniques which
utilize the on-chip sine data rather than external
PCM samples.
All of the PCM sample-based algorithms in the
CS9203 support looped playback of samples.
The sample memory address space is organized
as 64 pages of 512 waves per page, where a
wave is defined to be a block of 256 consecutive
samples. A single sampled sound may occupy a
maximum of one full page of sample memory
DS117PP4
---------------------(128K samples). Three pointers are used to define the location of a sampled sound in memory.
These pointers specify the Current Wave address,
the End Wave address, and the Loop Wave address. Sample memory access during sound
playback begins at the initial Current Wave address, and the current wave pointer is
incremented during playback until the End Wave
address is reached. The CS9203 supports two
different loop modes for sound playback. In the
more general case, when the current wave
pointer value reaches the End Wave, it is automatically reloaded with the Loop Wave address.
This mode of playback allows the lengths of the
attack (non-looped) portion and the looped portion of the sampled sound to be optimized for
the characteristics of that sound. In the "loop
last wave" mode of operation, playback will always loop on the End Wave. One-shot sounds
are implemented by including a blank wave at
the end of the sound, and then utilizing the loop
on last wave playback mode for the one-shot
sound.
The pitch, or playback frequency, for playback
of sampled sounds is specified by the 18 bit
DPHI parameter. The upper 6 bits of the DPHI
parameter are referred to as the upper phase bits,
and these bits make up the six least significant
bits of the sample memory address. The lower
12 bits of the DPHI parameter make up the fractional part of the phase. The frequency scaling
on playback is equal to DPHII4096. A DPHI
value of 4096 (upper phase = 1, fractional part =
0) would play the samples from memory at the
CS9203 output word rate. The fractional part of
the phase is also used as the weighting constant
for linear interpolation between samples when
utilizing algorithm 1. A DPHI value of 2048
(upper phase = 0, fractional part = 2048) would
play the samples from memory at one half the
CS9203 word rate. In this case, every second
value output from the algorithm would be an interpolated value to fill in the "missing point"
midway between adjacent samples in memory.
DS117PP4
CS9203
Envelope generation in the CS9203 is of the linear segment type, allowing the creation of any
piecewise linear envelope shape under external
microprocessor control. The microprocessor
specifies a rate of change and the amplitude endpoint for each segment, and the envelope
generator will generate an interrupt to the microprocessor when the endpoint level has been
reached.
Microprocessor Interface
The electrical interface between the microprocessor and the CS9203 is a standard bus interface,
comprised of the address lines AO and AI, the
data lines DO-D7, the Chip Select signal CS, the
Write signal WR, and the Read signal RD. The
external microprocessor controls the CS9203
synthesis functions by accessing the CS9203
Configuration Register, Interrupt Register, and
Parameter RAM (P-RAM).
The Configuration Register is an 8-bit write-only
control register which js comprised of the following control bits:
RUN
o1-
OFST
o1-
IE
o1-
SFMT
o1-
All slots are forced to idle
mode, independent of the
P-RAM contents
(power-up default state).
Synthesis slot processing
is enabled as indicated by
contents of the P-RAM.
The digital audio output data
on DABD has no DC offset (powerup default).
The digital audio output data on
DABD includes a
5%positive DC offset.
Envelope generator interrupts masked off (power-up default).
Envelope generator
interrupts enabled.
Selects digital audio output
format with idling on LSB (power-up
default). See Figure 6.
Select!' digital audio output
format with idling on MSB.
See Figure 6.
5-67
-
-___
.._-_.
-. ..---.-.
...SO - S3
CS9203
Slot Count Sequence - These 4 bits are
used to select the number of synthesis slots to be used as follows:
S2. S1 sQ No Slots
1
X
X
X
16
o 0 0 0
18 (default)
o 0 0 1
20
o 0 1 0
22
.sa.
o
o
o
o
o
0
1
1
0
1
0
24
26
1
1
1
0
1
1
1
0
1
28
30
32
The Control Register is accessed by first performing a Write operation to the CS9203 at
Address A1AO = 11 with data bit D6 =1 in order
to set the CS9203 into the configuration mode.
After setting the device to configuration mode,
the configuration register data is written to address A1AO=OO.
The Interrqpt Register is an 8-bit read-only register which indicates the slot number and the
envelope generator address within that slot
which has caused the interrupt. The Interrupt
Register is accessed.by reading from the CS9203
at address A1AO =00.
The CS9203 Parameter RAM (P-RAM) is used
to specify the synthesis algorithm and associated
parameter data to be used for each synthesis slot.
The P-RAM also functions as working RAM for
the synthesis algori¢m computations. There are
16 words of P-RAM associated with each synthesis slot. The P-RAM. word size is 19 bits.
The full address for a given P-RAM location is
made up of a Page bit (P)and an 8-bit P-RAM
address. The Page bit. value is zero for parameters associated with slots 0 - IS, and one for
slots 16-32. The 8-bit P-RAM address is comprised of a 4-bit Slot address and a 4-bit
Parameter address (the 4-bit Parameter address
identifies one parameter location in the 16-parameter block associated with the specified Slot).
The parameter types, parameter data formats,
and parameter addresses required for each slot
5-68
depend on the specific synthesis algorithm being
utilized for that slot. However, parameter location 15 in each 16-parameter block utilizes a
common format which specifies the algorithm to
be used fOf that slot, the output mix to be used,
the phase angle constant (used by some algorithms), and the busy/idle status of the slot.
Details of the sixteen synthesis algorithms and
associated parameter data formats are not covered in this document. The P-RAM write
sequence and P-RAM read sequence operations
are indicated in Table 1 and Table 2.
Sample Memory Interface
The CS9203 can address up to 8 Msamples of
external peM sample memory. The 23-bit sample memory address is comprised of a 6-bit Page
Address (PAGEO-PAGE5), a 9-bit Current Wave
Address (CWO-CW8), and an 8-bit Upper Phase
Address (PHI11-PHI18). This addressing technique organizes the sample memory into 64
pages, with each page containing 512 waves of
256 samples each. The Page Address bits
(PAGEO-PAGE5), Current Wave Address bits
(CWO-CW8), and Upper Phase Address bits
(PHI11-PHI18) are output on the CS9203 Wave
Address pins (WAO-WAll) in a time division
multiplexed manner, using the RAS and CAS
output signals as address strobes. Table 3 indicates the address bits which are available on the
Wave Address signal pins (WAO-WAll) at RAS
time, CAS time, and following the CAS strobe
(CAS+ 1 time). This memory addressing tec~
nique allows direct connection of large Dynannc
RAMs with enable control inputs (x4 configurations). Large ROM memory configurations
require external latches to capture a small subset
of the address information on the Wave Address
lines (WA9-WAll) during the RAS and CAS
strobes. A typical external sampling memory
read sequence is shown in Figure 2. Note that
the cycle on which the RAS and CAS strobes
occur is algorithm dependent.
DS117PP4
----------- -----------
CS9203
Operation
Address
A1 AO
Step 1. Select P-RAM Address Inside Page (CS=WR=O)
0
0
Step 2. Write Low data 6yte (CS=WR=O)
0
1
Step 3. Write Mid Data 6yte (CS=WR=O)
1
0
Step 4. Write H!9h.Data 6its, Select Page P and
Request Write (CS=WR=O)
1
1
Notes: 1.
2.
3.
4.
Data
07 06 05 04 03 02 01
DO
P-RAM Address (8bits)
67
61
60
615 614 613 612 611 610 69
68
P
66 65
0
X
64 63
X
62
X 618 617 616
Allow 68 crystal clock cycles (1.36 f.ls @50MHz) between step 4 and subsequent step 1 or
read operations.
Steps 2 and 3 can be omitted when writing repetitive data.
Steps 1, 2 and 3 can occur in any order.
The page P selected on step 4 remains valid for subsequent reads.
-
Table 1. P-RAM Write Sequence
Operation
Address
A1 AO
Data
07 D6 05 D4 03 02 01
X
X
61
60
615 614 613 612 811 610 89
68
1
1
P
1
Step 2. Dummy Read (CS=RD=O)
0
1
X
X
Step 3. Select P-RAM Address in Page and
Request Read (CS=WR=O)
0
0
Step 4. Read Low Data 6yte (CS=RD=O)
0
1
67
Step 5. Read Mid Data 6yte (CS=RD=O)
1
0
Step 6. Read High Data6yte (CS=RD=O)
1
1
X
X
X
X
X
X
X
X
DO
X
X
Step 1. Select P-RAM Page (CS=WR=O)
P-RAM Address (86its)
X
66
X
65
X
64 63
X
62
X 618 617 616
Notes: 1. Steps 1 and 2 can be omitted if the page bit P is already loaded (from a previous read or
write).
2. Step 1 loads the page bit P and sets the configuration mode, this requires a dummy read on
step 2.
3. At least 68 crystal clock cycles (1.36 f.ls @50MHz) are required between step 3 and the
subsequent step.
4. Steps 4 to 6 can occur in any order.
5. Steps 4 to 6 are optional.
Table 2. P·RAM Read Sequence
DS117PP4
5-69
_
..--__.._-_
...-..
.-_
CS9203
Time
WA11
(RAS)
WWE PAGE2 PAGE1 PAGED PHI18
WA10
WAg
WA6
WA5
WA4
WA3
WA2
WA1
WAO
PHI17
PHI16
PHI15
PHI14
PHI13
PHI12
PHI11
(CAS)
PAGE5 PAGE4 PAGE3 CWF8 CWF7 CWF6 CWF5 CWF4 .CWF3 CWF2
CWF1
CWFD
(CAS+1)
CWF3
PHI12
PHI11
CWF2
CWF1
WAS
CWFD
WA7
PHI18
PHI17
PHI16
PHI15
PHI14
PHI13
Table 3. Sample Memory Address Multiplexing on WAO • WAll
X2
RAS
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
CAS
WOE
row
col
min 12 cycles (240 ns)
WA16-12
--~(~------------------~)~--------~(~----
WD
-------------------4(~____~)~---------------Figure 2. Typical External Memory Read Sequence
5-70
DS117PP4
---------------------Figure 3 shows direct connection of three 4 Mbit
(lMx4) DRAM chips to form a 1Mx12 sample
memory. Note that one synthesis slot can be assigned to algorithm number 16 to generate RAS
before CAS refresh for Dynamic RAMs. The
CAS before RAS refresh timing generated using
algorithm 16 is shown in Figure 4. Note that
algorithm 16 utilizes one of the synthesis slots,
but this algorithm does not generate a voice.
Thus, the polyphony of the CS9203 is reduced
by one note when using Algorithm 16 to generate DRAM refresh.
CS9203
CS8905. Two different serial DAC data formats
are supported by the WSBD signal, as indicated
in Figure 6. The serial DAC format is selected
using the SFMT bit in the CS9203 Configuration
Register. The number of data bits transmitted in
the serial data output depends on the state of the
SFMT bit, and on the number of synthesis slots
being utilized as follows:
SEMI
o
o
o
1
DRAMs without enable control pins (xl configurations) require the use of an external
Flip-flop to capture the early write information
(WWE) on the WAll line at RAS time.
DRAMs with static column mode access should
not be used with the CS9203 because the addresses are not stable during the full CAS cycle.
Figure 5 shows the address latch circuitry required to address 8 Msamples of ROM memory.
One 3-bit latch is clocked at RAS time to capture address lines WA17-WA19, the second 3-bit
latch is clocked at CAS time to capture WA20WA22. A 1Msample ROM implementation
would require only the first 3-bit latch, a 128K
sample ROM could be addressed directly by the
CS9203.
DAC interface
The CS9203 DAC interface consists of a
left/right clock signal WSBD, a bit clock CLBD
and the stereo output data stream DABD or
DAFD. The left/right clock signal WSBD and bit
clock CLBD are common to both the main stereo serial data output DABD and the secondary
stereo serial data output DAFD. The DAFD output is commonly used as a stereo effects send to
an external effects processor, such as the
DS117PP4
Number of
bits output
16
18
S/Qts.
16
18
20-32
X
20
16
The number of bit clock (CLBD) cycles per
frame is equal to two times the number of synthesis slots being used (two CLBD clock cycles
per synthesis slot). When the number of synthesis slots used is larger than the number of output
data bits, then the output data stream is padded
with zeros as indicated in Figure 6. The most
significant bit (MSB) of the left channel data is
output during the slot time, and the MSB of
the right channel is output during the slot 8 time.
The slot count sequence used in the CS9203 is
represented in Figure 7. If 16 slots are utilized,
the slot count sequence is straightforward (0,1, ...
15). If the slot count is greater than 16, then
slots are added symmetrically after slot 7 and after slot 15. For example, if the number of slots
is 20 (the number of slots is always an even
number), then the slot count sequence will be (0,
1, ... 7, 16, 17,8,9, ... 15,24,25). In this case,
slot numbers 18 - 23 and slot numbers 26 - 31
are not used. This allows the zero padding to be
symmetrical with respect to the left channel and
right channel data.
°
The ground reference for the DAC should be
connected directly to the CS9203 GND at pin
19, and this should be the only connection between analog ground and digital ground.
5-71
III
,..,
il.,.=
....",
~
CS9203
RESET
CS
RO
WR
f
i
~
I
=:
§
S.
~
....NI><
~
CIl
A1
AO
07
06
05
04
03
02
01
00
-
INT
X1
i
i
X2
W011
CLBO ~
WSBO ~
OABO ~
OAFO r--1L
WWE
WOE
RAS
CAS
WA16
WA15
WA14
WA13
WA12
WA11
WA10
WA9
WAB
WA7
WA6
WAS
WA4
WA3
WA2
WA1
WAO
23
22
25
24
.....
="
~
~
~
~
~
~
~
51
52
53
54
55
56
57
5B
59
60
-
j
RAS
CAS
~ W
22 -G
23
5
.1B
17
16
15
14
12
11
10
9
A9
AB
A7
A6
AS
A4
A3
A2
A1
AO
4 RAS
CAS
23
"--'3
22 '.!'i
G
5
A9
'T8 AB
'16 A7
'15 A6
AS
'14 A4
A3
r-:rr
0Q4 ~
003 ~
002 r£001 r!4C4001DJ
r--w
r--w
r--g
004 ~
003 24
~
A1
002 r=-001 r!r-:- AO
4C40010J
'1f
A2
4 RAS
Qt.S
3 W
22 G.
~
.---E-
A9
~ AB
c--1Z.
A7
A6
AS
A4
A3
e--11- A2
c-!Q. A1
~ AO
~
~
~
~
0Q4 f-=003 ~
002 ~
001 cL
4C40010J
CKOUl ~
XCLK ~
WOO
o
~
N
......cen.....
'tI
'tI
""
o
W
---------------------RAS
~L
CS9203
__________________________
~
CAS
WWE
WD
------~(L___________~_li_d________~)r--------------------------------------
\~---------------------
WOE
Figure 4. Algorithm 15, External RAM Write, CAS Before RAS Refresh
Oscillator Circuit
CLKOUT and XCLK Clock Outputs
The CS9203 timing may be generated using the
built-in crystal oscillator (external crystal circuit)
or an external oscillator. Connections for a typical 3rd overtone series-resonant crystal oscillator
circuit are shown in Figure 8. Trace lengths
should be kept to a minimum, and the board layout should include ground plane beneath the
oscillator circuit components.
The frequency of the CKOUT output is the crystal oscillator frequency divided by four. The
CKOUT output is disabled while the RESET input is low.
If an external oscillator circuit in utilized, shield
the input trace connecting the oscillator output to
the Xl input at pin 66, and keep the trace
lengths to a minimum. The ground for the oscillator circuit should be a direct connection to the
CS9203 GND at pin 68.
DS117PP4
The XCLK output is a gated clock output which
provides either 1024 or 2048 output clock pulses
per synthesis frame. The period of the XCLK
output pulses are the same as those of the
CS9203 crystal oscillator. If the number of synthesis slots in use is less than 32, then the XCLK
signal will output 64 pulses per synthesis frame
for the first 16 synthesis frames executed, and
then remain inactive for the balance of the
frames. If the number of slots is equal to 32,
then the XCLK signal will output 64 pulses dur5-73
III
,...
~
~
VCC
VCC
ClR
ClK
74HC04
CS9203
:=l
~
a
!"
>-
=-=-
a
CHECKSUM F7H
Exclusive status ---.J
I
I
I I
Dream MMA code'---------.J
Device i d - - - - - - - - - - - - - - '
Model id
COMMAND - OOH - DOWN-LOAD OF INSTRUMENT SOUND
Down-loaded sound is selected on track by sending Control channel # 0 value 64 decimal, then program change O.
-
COMMAND - 12 - GS COMPATIBILITY MODE
In this case
= addressMSB I address I addressLSBI
AddressGS Data (HlParameterDescriDtionDefault value (Hl
4001 3000-07REVERB TYPEOO : Room104
01 : Room2
02: Room3
03: Hall1
04: Hall2
05: Plate
06: Delay
07 : Panninq Delav
note : Reverb type can also be set with Control # 80
4001 3800-7FREVERB LEVEL40
40 01 3800-07CHORUS TYPEOO : Chorus 102
01 : Chorus 2
02: Chorus 3
03: Chorus 4
04 : Feedback Chorus
05: Flanger
06 : Short Delay
07 : Short delCiY with feed-back
note: Chorus type can also be set with Control # 81
DS127DB1
5-101
_.-_..--_.-.
__.._-_
...-.
CDBGMR4
AddressGS DatalHlParameterDescriDtionDefault value lHl
Part numbering :
Part 1 (default MIDI channel = 1)n=1
, ,
Part 9 (default MIDI channel = 9)n=9
Part 10 (default MIDI channel = 10)n=0
Part 11 (default MIDI channel = 11)n=A
,
,
Part 16 (default MIDI channel = 16)n=F
Part OFFn=10
40 1n 0200-10Rx CHANNELOO(1) OF(16) 10(OFF)same as the Part#
40 1n 1S00-02Rhythm assignOO (sound part)OO for n<>O
01, 02 (rhythm part)01 for n=O (part 10)
40 1n 4000-7F (12)SCALE TUNE-64 +63 (cent)40, 40, .. ,,40 (12 values)
note: 40 1n 40 followed by 12 values (one value for each semi-tone, starting with C)
;
40 1n 1AOO-7FVelocity depth (velocity slope)40
40 1n 1BOO-7FVelocity offset40
40 2x 0300-7FMOD WHEEL RATE (common to all tracks)3C
40 2n 0400-11 MOD WHEEL DEPTHOA
5-102
05127081
----------------------
CDBGMR4
RPN - Registered Parameter Number
RPN
#0 = pitch bend sensitivity
#1 = fine tuning
#2 = coarse tuning
NRPN - Non Registered Parameter Number
NRPN
MSB
01H
01H
01H
01H
01H
01H
01H
01H
1BH
1AH
1CH
1DH
1EH
OS127081
LSB
OBH:Vibrate rate (-50,0,+50) [0 = 40H]
09H:Vibrate depth (-50,0,+50)
OAH:Vibrate delay (-50,0,+50)
20H:TVF cutoff frequency (-50,0,+16)
21 H:TVF resonance (-50,0,+50)
63H:Environment attack time (-50,0,+50)
64H:Environment decay time (-50,0,+50)
66H:Environment release time (-50,0,+50)
rrH:Pitch coarse of drum instrument note rr (-64,0,+63 semitones)
rrH:Level of drum instrument note rr (0,+ 127)
rrH:Pan of drum instrument (-64,0,+63)
rrH:Reverb send level of drum instrument (0,+127)
rrH:Chorus send level of drum instrument (0,+127)
-
5-103
---------------------PC INTERFACE SPECIFICS
I/O base address can be jumper selected to 300H,
310H, 320H, 330H (default setting is 330H).
Interrupt can be jumper selected to 2/9, 3, 4, 5, 7
(default setting IRQ2/9).
After power-up or software reset, the board is in
stand-alone mode:
Channels 1-9: instruments
Channel 10: drums
Channels 11-16: instruments
MIDI IN connected to synthesis and
MIDI OUT
PC interrupt disconnected
No data transmitted to PC
In stand-alone mode, the only MPU-401
command processed are:
3FH:
set UART mode
This command is acknowledged
by the data OFEH on data port
CDBGMR4
Hardware handshake
Address base + 1
read: status
bit 7: DSR· (0 data pending)
bit 6: ORR· (0 = ready to accept
data or command)
=
write:
command
command will be accepted only; if
ORR· = o.
command write sets ORR· to 1.
ORR· will return to zero after
completion by the board.
Address base + 0
read: data (valid when OSR· = 0)
data read will set DSR* to 1
write:
data (ready for write when ORR·
returns to zero when the board
finishes processing the data.
In UART mode:
Interrupt (as selected by jumper) is
connected to PC
Data received from MIDI IN is
transmitted to PC
Data received from the PC is transmitted
to synthesis and MIDI OUT
The only command recognized in UART mode is:
OFFH: reset (resume stand-alone mode)
this command is not acknowledged
Interrupts are generated only in UART mode, when
a character is pending (board to PC).
5-104
OS127081
----------------------
CDBGMR4
CRYSTAL SOFTWARE LICENSE AGREEMENT
Crystal Semiconductor Corp. reference designs contain copyrighted software and wavetable sample data. Under
this license agreement Crystal grants to you the right to use one copy of the software and wavetable data
("Licensed Software"), for the purpose of evaluating Crystal Semiconductor Corp. products. You may not:
1. modify, translate, reverse engineer, decompile, disassemble, create derivative works based on the
Licensed Software, or copy the Licensed Software; or
2. rent, distribute, lend, or otherwise disclose, transfer or grant any rights in the Licensed Software in
any form to any third party, or
3. disclose to any third party, or use for any purpose other than evaluation of the Licensed Software,
any information that you learn or derive conceming the Licensed Software as a result of your use or
possession of the Licensed Software; or
4. remove any proprietary notices, labels, or marks on or in the original or any copy of the
Licensed Software.
THE LICENSED SOFTWARE IS PROVIDED TO YOU "AS IS." CRYSTAL MAKES NO WARRANTY OR REPRESENTATION, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE
LICENSED SOFTWARE, INCLUDING ITS QUALITY, PERFORMANCE, MERCHANTABILITY, NON INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL CRYSTAL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL,
OR OTHER DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR COVER, LOSS
OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR ANY
OTHER PECUNIARY LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE THE LICENSED SOFTWARE, EVEN IF CRYSTAL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
TRADEMARKS & COPYRIGHTS
SMART ANALOG™ is a registered trademark of Crystal Semiconductor Corp.
TM.
TM
• •
TM
• •
MS DOS ,Microsoft ,Microsoft Windows ,Microsoft Windows 3.1
marks of Microsoft Corp.
TM
TM.
,and MSCDEX
are registered trade-
Sound Blaster™ is a copyright of Creative Labs, Inc.
AdLibTM is a registered trademark of AdLib, Inc.
TM
TM
TM
IBM ,XT ,and AT
TM
are registered trademarks of International Business Machines Corp.
TM
Roland ,SoundCanvas ,SCC-1
TM
,LAPC-1
TM
,and MT-32
TM
are trademarks of Roland Corp.
The General MIDI logo is a servicemark of the MIDI Manufacturers Association.
Trademarks and Copyrights not specifically mentioned remain the property of their specific holders.
05127081
5-105
-
----------------------
CDBGMR4
- Notes-
5-106
DS127DB1
.._-_
_
...
.-_..__
._.-.
~--
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
6
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
6-1
_-_
.. .
.-_---_._.
.-•.__ .> ••.CS8401A, CS8402A AESIEBU &
Transmitters
DIGITAL AUDIO INTERFACES
SlPnlF
CS8425 A-LAN - Audio Local Area Network
Transceiver
The CS8401A & CS8402A accept digital audio in
many standard formats and generate an AESIEBU
or SIPDIF compatible data stream. The CS8401A
is software programmable for mode and for channel status and user data. The CS8402A is pin programmable.
The CS8425 is an SIPDIF transceiver with onchip low jitter PLL. A ring of CS8425 devices
forms an Audio Local Area Network, where user
data bits may be used for system messages between nodes. Intended for automotive applications, the device finds use wherever audio and
some additional low bandwidth information needs
to be communicated between multiple devices.
CS8411, CS8412 AES/EBU and SlPnlF Receivers
The CS8411 and CS8412 digital audio receivers
accept AESIEBU or SIPDIF signals and gen~rate
digital audio in many standard formats. A lowjitter PLL recovers a clean clock for system use.
The CS8411 is software readable for channel
status and user data. The CS8412 is pin programmable
CONTENTS
CS8401N2A Digital Audio Interface Transmitter
CS841 1/12 Digital Audio Interface Receiver
CS8425 Audio Local Area Network Transceiver (A-LAN)
6-2
6-3
6-35
6-69
......
..........
..,-- .........
~~~.
CS8401 A CS8402A
Semiconductor Corporation
Digital Audio Interface Transmitter
General Description
Features
• Supports: AES/EBU, IEC 958,
S/PDIF, & EIAJ CP-340
Professional and Consumer Formats
The CS8401/2A are monolithic CMOS devices which
encode and transmit audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface
standards. The CS8401/2A accept audio and digital
data, which is then multiplexed, encoded and driven
onto a cable. The audio serial port is double buffered
and capable of supporting a wide variety of formats.
• Host Mode and Stand Alone Modes
• Generates CRC Codes and Parity Bits
The CS8401A has a configurable internal buffer memory, loaded via a parallel port, which may be used to
buffer channel status, auxiliary data, and/or user data.
• On-Chip RS422 Line Driver
• Configurable Buffer Memory (CS8401A)
• Transparent Mode Allows Direct
Connection of CS8402A and CS8412
or CS8401 A and CS8411 A
The CS8402A multiplexes the channel, user, and validity data directly from serial input pins with dedicated
input pins for the most important channel status bits.
• Monolithic Digital Audio Interface
Transmitter
ORDERING INFORMATION:
TABLE OF CONTENTS:
page 6-32
page 6-33
MCK
CS8401A
15
6
7
SCK
FSYNC
SDATA
8
CS
RDIWR
14
16
J
:1
A4. AD
5
Audio
Serial Port
Configurable
Buffer
Memory
D7·DO
8
M2
CS8402A
123
SCK
6
FSYNC
7
SDATA
8
C
10
U
11
V
9
T
M1
~
rL
r
15
Prescaler
I
+
MUX
~
RS422 Driver
U
MO
122 121
MCK
RST
15
1
Registers
~ TXN
16
Audio
Serial Port
L
TXP
~ TXP
U
MUX
RS422 Driver
-IT..
r+
7
TXN
[l24
Dedicated Channel
Status Bits
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX:. (512) 445-7581
CBl
TRNPT
NOV '93
DS60F1
6-3
... -.-.
_.-_.. .._-_
.....
~-.-,_
CS8401 A .CS8402A
ABSOLUTE MAXIMUM RATINGS (GND = OV, all voltages with respect to ground.)
Parameter
Symbol
DC Power Supply
Input Current, Any Pin Except Supply
Units
6.0
V
-
±10
rnA
VIND
-0.3
VD+
V
TA
-55
125
°C
T stg
-65
150
°C
Ambient Operating Temperature (power applied)
Storage Temperature
Max
lin
Note 1
Digital Input Voltage
Notes:
Min
VD+
1. Transient currents of up to 100 rnA will not cause SCR latch-up.
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = OV; all voltages with respect to ground)
Parameter
DC Voltage.
Supply Current
Symbol
Min
Typ
Max
VD+
4.5
5.0
5.5
V
1.5
5
rnA
Note 2
IDD
Ambient Operating Temperature: CS8401/2A-CP or -CS Note 3
TA
Power Consumption
Notes:
25
0
70
°C
85
°C
'25
mW
Max
Units
-40
CS8401/2A-IP or -IS
Note 2
7.5
PD
Units
2. Drivers open (unloaded). The majority of power is used in the load connected to the drivers.
3. The '-CP' and '-CS' parts are specified to operate over 0 to 70°C but are tested at 25 °C only.
The '-IP' and '-IS' parts are tested over the full -40 to 85°C temperature range.
DIGITAL CHARACTERISTICS
(TA
= 25°C for suffixes 'CP' & 'CS', TA = -40 to 85 OC for 'IP' & 'IS'; VD+ = 5V ± 10%)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-level Ou.tput Voltage
(10 = 2001lA)
Low-Level Output Voltage
(10 =3.2mA)
Min
VIH
2.0
VDD+0.3
V
VIL
-0.3
+0.8
V
VOH
VDD-1.0
V
0.4
VOL
Input Leakage Current
1.0
lin
Master Ciock Frequency:
CS8401A
Note 4
CS8402A
Note 4
Master Clock Duty Cycle
CS8401/2A
Notes:
Typ
Symbol
MCK
40
V
10
IlA
22
MHz
7.1
MHz
60
%
4. MCK for the CS8401 must be 128, 192,256, or 384x the input word rate based on MO and M1 in control
register 2. MCK for the CS8402A must be 128x the input word rate, except in Transparent Mode where MCK is
256x the input word rate.
Specifications are subject to change without notice.
6-4
DS60F1
----------- -----------
CS8401A CS8402A
DIGITAL CHARACTERISTICS - RS422 DRIVERS
(TXP, TXN pins only; VD+
= 5V ±10%)
Parameter
Symbol
Output High Voltage
IOH = -30 rnA
VOH
Output Low Voltage
IOL =30 rnA
VOL
Min
Typ
Max
VD+- 0.7 VD+ - 0.4
0.4
Units
V
0.7
V
Max
Units
SWITCHING CHARACTERISTICS - CS8401A PARALLEL PORT
(TA = 25°C for suffixes '-CP' and '-CS'; TA = -40 to 85°C for suffixes '-IP' and '-IS')
Parameter
Symbol
Min
tadcss
13.5
ns
CS high to ADDRESS invalid
tcsadh
0
ns
RDIWR valid to CS low
trwcss
10
ns
CS low to RDIWR invalid
tcsrwi
35
ns
lesl
35
ns
ADDRESS valid to CS low
CS low
Typ
DATA valid to CS rising
RDIWR low (writing)
tdcssw
32
ns
CS high to DATA invalid
RDIWR low (writing)
tcsdhw
0
ns
CS falling to DATA valid
RDIWR high (reading)
tcsddr
CS rising to DATA Hi-Z
RDIWR high (reading)
lesdhr
35
5
-
ns
ns
A4-AO
r--- ladess
cs
1 + - - - - lesl
I rwess
---->(
-+---- lesrwi ---~
RDIWR
Wrilin g
<
D7-DO
RDIWR
Reading
<
D7-DO
CS8401A Parallel Port Timing
DS60F1
6-5
.._-_.
_.-_..--_._.
_"""' ...-
CS8401 A CS8402A
SWITCHING CHARACTERISTICS - SERIAL PORTS·
(TA = 25°C for suffixes '-CP' and '-CS'; TA = -40 to 85°C for suffixes '-IP' and '-IS';
Inputs: Logic 0 = GND, logic 1 = VD+; CL = 20 pF)
Symbol
Parameter
SCKFrequency
Master Mode
Notes 5,6
Min
Typ
Max
Units
12.5
MHz
IWRx64
tsckf
Hz
Slave Mode
Note 6
SCK Pulse Width Low
Slave Mode
Note 6
tsckl
25
ns
SCK Pulse Width High
Slave Mode
Note 6
tsckh
25
ns
tsfds
20
ns
ns
SCK rising to FSYNC edge delay
Notes 6,7
SCK rising to FSYNC edge setup
Notes 6,7
Isfs
20
SDATA valid to SCK rising"setup
Note 7
tsss
20
ns
SCK rising to SDATA hold time
Note 7
tssh
20
ns
Notes,7,S
tess
0
ns
Notes 7, S
tscs
50
ns
C, U, V valid to SCK rising setup CS8402A
non-CD Mode
SCK rising to C, U, V hold time
CSS402A
non-CD mode
U valid to SBC rising setup
CSS402A, CD mode
NoteS
tuss
0
ns
SBC rising to U hold time
CSS402A, CD mode
Note S
tsuh
SO
ns
RST Pulse Width
CS8402A
150
ns
Notes:
5. The input word rate, IWR, refers to the frequency at which stereo audio input samples are input to
the. part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always
32 SCK periods in one audio sample.
6. Master mode is defined as SCK and FSYNC being outputs. In Slave mode they are inputs. In the
CS8401A, control reg. 3 bit 1, MSTR, selects master. In the CS8402A, only format 0 is master.
7. The table above assumes data is output on the falling edge and latched on the rising edge. In both
parts the edge is selectable. The table is defined for the CSS401A with control reg. 3 bit 0, SCED, set to
one, and for the CS8402A in formats 4 through 7. For the other formats, the table and figure edges
must be reversed (ie. "rising" to "falling" and vice versa).
S. The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions.
This is true for all modes except FSFO & 1 both equal 1 in the CSS401A, and format 4 in the CSS402A.
In these modes SBC is delayed one full SCK period.
FSYNC
________+-~LJ~~t~
tsfds
tsckl
tsckh
SCK
SDATA
Serial Input Timing - Slave Mode
6-6
DS60F1
---------_ .. _----------
CS8401A CS8402A
FSYNC
tslds
SCK
SDATA
CS8402A
non-CD mode \
C,U,V
tess i'---->I<--~tseh
-----,I
1,---------------
U
CD mode
~
t uss i'---->I<--~t suh
SSC
-
Serial Input Timing - Master Mode & C, U, V Port
l
~
- - - -
,
Audio
Data
Processor
Audio
Data
Processor
-
- -
External
Clock
- - >- - - - - - - - - - - - <
-i
I
-t§)L
5
5 k!l
7
6
8
MCK
19
FSYNC
SCK
GND
SDATA
15
--
14
-
16
VD+
18
_T
0.1 uF
-b
-
INT
CS8401A
CS
--
or
RDIWR
Microcontroller
AO-A4
DO-D7
TXP
~
TXN
~
Transmitter
Circuit
See Appendix B
Figure 1. CS8401A Typical Connection Diagram
DS60F1
6-7
-____-_
.. ...-.
-. ..--_._.
CS8401 A CS8402A
I
External
Clock
: -------------------t
,
7
Audio
Data
Processor
6
8
-:---I
Microcontroller
or
unused
15
10
11
9
16
I
-t§~
5
MCK
FSYNC
VD+
GND
SDATA
C
M2
M1
CS8402A
MO
U
TXP
V
~
22
~
.=..:-~
-
RST
TXN
Channel
Status Bits
Control
18
24"'
TRNPT ----<
-...=-
SCK
CBl
~ 0.1 uF
19
8 Dedicated C.S. Bits
J..L.
Serial Port
Mode Select
Transmitter
Circuit
See Appendix B
Figure 2. CS8402A Professional & Consumer Modes Typical Connection Diagram
~
External
Clock
---------------------i
"t
Audio
Data
Processor
I
7
6
8
9
Decoder
Subcode
Port
Reset
Control
Channel
Status Bits
Control
10
11
15
16
FSYNC
I
-t§~
5
MCK
SCK
19
SBF
-...=-
U
M2
CS8402A
M1
MO
SBC
-
~23
22
21
TXP
~
TXN
~
RST
8 Dedicated C.S. Bits
0.1 uF
VD+
18
GND f---<
SDATA
V
=h
Serial Port
Mode Select
Transmitter
Circuit
See Appendix B
Figure 3. Consumer CD Submode Typical Connection Diagram
6-8
DS60F1
.._-_
.-_
_
..--_._.
__
...-.
CS8401A CS8402A
GENERAL DESCRIPTION
CS8401A DESCRIPTION
The CS8401Al2A are monolithic CMOS circuits
that encode and transmit audio and digital data
according to the AESIEBU, IEC 958 (SIPDIF) ,
and EIAJ CP-340 interface standards. Both chips
accept audio and control data separately; multiplex and biphase-mark encode the data
internally; and drive it, directly or through a
transformer, to a transmission line. The CS8401A
is fully software programmable through a parallel port and contains buffer memory for control
data, while the CS8402A has dedicated pins for
the most important control bits and a serial input
port for the C, U, and V bits.
The CS8401A accepts 16- to 24-bit audio samples
through a configurable serial port, and channel status,
user, and auxiliary data through an 8-bit parallel port.
The parallel port allows access to 32 bytes of internal
memory which is used to store control information
and buffer channel status, user, and auxiliary data.
This data is multiplexed with the audio data from the
serial port, the parity bit is generated, and the bit
stream is biphase-mark: encoded and driven through
an RS422 line driver. A block diagram of the
CS8401A is shown in Figure 4. In accordance with
the professional definition of channel status, the
CRCC code (C.S. byte 23) can be internally generated.
Familiarity with the AES/EBU and IEC 958
specifications are assumed throughout this data
sheet. Many terms such as channel status, user
data, auxiliary data, professional mode, etc. are
not defined. The Application Note, Overview of
AESIEBU Digital Audio Interface Data Structures, provides an overview of the AESIEBU and
IEC 958 specifications and is included for clarity; however, it is not meant to be a complete
reference, and the complete standards should be
obtained from the Audio Engineering Society or
ANSI for the AESIEBU document, and the International Electrotechnical Commission for the
IEC document.
Line Drivers
The RS422 line drivers for both the CS8401A
and CS8402A are low skew, low impedance, differential outputs capable of driving 110 Q
transmission lines with a 4 volt peak-to-peak signal when configured as shown in Appendix A.
To prevent possible short circuits, both drivers
are set to ground when no master clock (MCK)
is provided. They can also be disabled by resetting the device (RST = low). Appendix A
contains more information on the line drivers. A
0.1 IlF capacitor, with short leads, should be
placed as close as possible to the VD+ and GND
pins.
DS60F1
Parallel Port
The parallel port accesses one status register, three
control registers, and 28 bytes of dual port buffer
memory. The address bus, and RDIWR line must be
valid when CS goes low. If RDIWR is low, the
value on the data bus will be written into the buffer
memory at the specified address. If RDIWR is high,
the value in the buffer memory, at the specified address, is placed on the data bus. The detailed timing
for reading and writing the CS8401A can be found
in the Digital Switching Characteristics table. The
memory space is allocated as shown in Figure 5.
There are three defined buffer memory modes selectable by two bits in control register 2.
Status and Control Registers
Upon power up the CS8401A control registers
contain all zeros. Therefore, the part is initially
in reset and is muted. One's must be written to
control register 2, bits RST and MUTE, before
the part will transmit data. The remaining regis-
ters are not initialized on power-up and may
contain random data.
The first register, shown in Figure 6, is the status
register in which only three bits are valid. The lower
three bits contain flags indicating the position of the
transmit pointer in the buffer memory. These flags
6-9
-
___-_
.. ...-.
-.-_
..--_._.
SOATA
8
SCK
6
FSYNC
7
00-07
A4-AO
CS
ROIWR
CS8401A
Serial
Port
Logic
21-24,1-4
9-13
14
16
Biphase
Mark
Encoder
TXP
TXN
Control
and Flags
4 X 8
INT
Buffer
Memory
28 X 8
Figure 4. CS8401A Block Diagram
may be used to avoid contention between the
transmit pointer reading the data and the user updating the buffer memory. Besides indicating the
byte location being transmitted, the flags indicate
the block of memory the part is currently addressing, thereby telling the user which block is
free to be written to. Each flag has a corresponding mask bit (control register 1) which, when set,
allows a transition on the flag to generate a pulse
on the interrupt pin. Flag 0 and flag I cause interrupts on both edges whereas flag 2 causes an
interrupt only on the rising edge. Timing and
further explanation of the flags can be found in
the buffer memory section.
The two most significant bits of control register 1,
BKST and TRNPf, are used for Transparent Mode
operation of the CS8401A Transparent Mode is used
for those applications· where it is useful to maintain
frame alignment between the received and transmitted
audio data signals. In Transparent Mode
(TRNPT = I ") the MCK, FSYNC, SCK and
SDATA inputs of the CS8401A can be connected to
their corresponding outputs of the CS8411. In Transparent Mode, FSYNC synchronizes the transmitter
and the receiver. The data delay through the CS8401A
II
6-10
is set so that three frame delays occur from the
input of the CS8411 to the output of the
CS8401A In Transparent Mode, 32 SCK's are
required per subframe.
Channel status block alignment between the
CS8411 and the CS840lA is accomplished. by
setting BKST high at the occurrence of the Flag
2 rising edge of the CS8411. If FSYNC is a
left/right signal, BKST is sampled once per
frame; if FSYNC is a word clock, BKST is sampled once per subframe. A low to high transition
of BKST (based on two successive internal samples) resets the channel status block boundary to
the beginning.
Control register 2, shown in Figure 8, contains
various system level functions. The two most
significant bits, M I and MO, select the frequency
at the MCK pin as shown in Table 1. As an example, if the audio sample frequency is 44.1 kHz
and MO and Ml are both zero, MCK would then
be 128x the audio sample rate or 5.6448 MHz. The
next bit (5) in control register 2, V, indicates the validity of the current audio sample. According to the
DS60F1
.._-_
.-_
_
..--_._.
__
...-.
CS8401A
digital audio specifications, V = 0 signifies the
audio signal is suitable for conversion to analog.
B I and BO select one of three modes for the
buffer memory. The different modes are shown
in Figure 5 and the bit combinations in Table 2.
More information on the different modes can be
found in the BlffJer Memory section. Bit 2, CRCE, is
the channel status CRee enable and should only be
used in professional mode. When CRCE is high, the
76543210
1><1><1><1><1><1 FLAG21 FLAG11 FLAGOI
X:oo
FLAG2: High for first four bytes of channel status
FLAG 1: Memory mode dependent· See figure 11
FLAGO: High for last two bytes of user data.
Figure 6. Status Register
76543210
1BKST 1TRNPT I>--_ _--=[MSBJ.:.::S=B _- _- _- _- _- _-[ISBlLCL-'--SB---'---_ _ _.L. C[MSBJ-'-'-S---'B _- _- _- _- _- _- [LSBJ
FORMAT 6:
FSYNC (in)
SCK(in)
~
/.-----16 Bits---.l
Left
/.-----16 Bits----./
Right
I
~-_-_-_I_-_-_-_-_-_-SLr_-_-_-_-_-I_-_-_-_-_-_-JL
SDATA (in) c.=:[LSB]=SB=-->--_ _---!-'-'-[MSBf.:.::S=B _- _- _- _- _- _- [LSB]LCL-'--SB---c-_ _ _7--'[MSBJ-'-'-S---'B _- _- _- _- _- _-[LSB]
FORMAT 7:
FSYNC (in)
SCK(in)
~
/.-----18 Bits ---.I
Left
/.-----18 Bits--.!
Right
I
~-_-_-_I_-_-_-_-_-_-SLr_-_-_-_--I_-_-_-_-_-_-JL
SDATA (in) c:.:[MSB]=S=B'-------_ _L::[ISBJ=SB::.J _- _- _- _- _- _-[MSB]'--M"'-SB---'---_ _ _-'-'[ISBJ'-"-SB~ _- _- _- _- _- _-[MSB]
Arrows indicate where C, U, and V bits are latched
Figure 16. CS8402A Audio Serial Port Fonnats
DS60F1
6-21
--------..,-- -----------
CS8402A
C, U, V Serial Port
RST and CBL (TRNPT is low)
The serial input pins for channel status (C), user
(D), and validity (V) are sampled during the first
bit period after the active edge of FSYNC for all
formats except Format 4, which is sampled during the second bit period (coincident with the
MSB). In Figure 16, the arrows on SCK indicate
when the C, D, and V bits are sampled. The C,
D, and V bits are transmitted with the audio
sample entered before the FSYNC edge that
sampled it. The V bit, as defined in the audio
standards, is set to zero to indicate the audio data
is suitable for conversion to analog. Therefore,
when the audio data is errorred, or the data is
not audio, the V bit should be set high. The
channel status serial input pin (C) is not available in consumer mode when the CD subcode
port is enabled (FC1 = FCD = high). Any channel status data entered through the channel status
serial input (C) is logically OR'ed with the data
entered through the dedicated pins or internally
generated.
When RST goes low, the differential line drivers
are set to ground and the block counters are reset
to the beginning of the first block. In order to
properly synchronize the CS84D2A to the audio
serial port, the transmit timing counters, which
include CBL, are not enabled after RST goes
high until eight and one half SCK periods after
the active edge (first edge after reset is exited) of
FSYNC. When FSYNC is configured as a
left/right signal (all defined formats except 2),
the counters and CBL are not enabled until the
right sample is being entered (during which the
previous left sample is being transmitted). This
guarantees that channel A is left and channel B is
right as per the digital audio interface specs.
(
TRNPThighJ
CBl
.
TRNPTlow
SDATA
FSYNC
As shown in Figure 17, CBL, channel block start
output, can assist in serially inputting the C, D
and V bits as CBL goes high one bit period before the first bit of the preamble of the first
sub-frame of the channel status block is trans-
)
:~
left 0
Right 0
f
(
(
left 1
(
2
~19ht 128(
left 128
1
(
)
~
~)
.
(
(
(
• ..
.. C bits from Cpin ..
2!
I
Right 0
left 0
)~
•
m"",,,,,, II\I!. ~cuv"'~CUV<>,~C"~'
• ~C"V"01\\\\!~cU"'"
~C"V'" ~C"V'"
111111111111 LI\IIIIIIIIII t(llllllllllllllr
\\\\\\\\\~ 2L\\\\\\\\\\\\~ \\\\\\\
C,U,V
TRNPTlow
.
CUV191R
CUVOl
t
CUVOR
t
C bits OR'ed wI
PRO pin
--'-----------'
CUV1l
Q..bit OR'ed wI
C1 pin
j
CUV128l
CUV191R
CUVOl
tBitOofC.S. - - - - - _
Block Byte 16
TXP
TXN
-
-
"j
left 0 - Audio Data
14-1_------------- Sub-frame ------------~
Figure 17. CBL and Transmitter Timing
6-22
DS60F1
.._-_.
.-_
_
..--_._.
__
...mitted. This sub-frame contains channel status
byte 0, bit O. CBL returns low one bit period before the start of the frame that contains bit 0 of
channel status byte 16. CBL is the exact inverse
of flag I in mode 0 on the CS8401 (see Figure 11). CBL is not available when the CD
subcode port is enabled.
Figure 17 illustrates timing for stereo ~ata in~ut
on the audio port. Notice how CBL rIses whIle
the right channel data (Right 0) is input, but the
previous left channel data (Left 0) is being transmitted as the first sub-frame of the channel
status block (starting with preamble Z). The C,
U, and V input ports only need to be valid for a
short period after FSYNC changes. A sub-frame
includes one audio sample while a frame includes a stereo pair. A channel status (C.S.)
block contains 24 bytes of channel status and
384 audio samples (or 192 stereo pairs, or
frames, of samples).
Figure 17 shows the CUV ports as having left
and right bits (e.g. CUVOL, CUVOR). Since the
C.S. block is defined as 192 bits, or one bit per
frame, there are actually 2 C.S. blocks, one for
channel A (left) and one for channel B (right).
When inputting stereo audio data, both blocks
normally contain the same information, so COL
and COR from the input port pin are both channel status bit 0 of byte 0, which is defined as
professional/consumer. These first two bits from
the port, COL and COR, are logically OR'ed with
the inverse of PRO, since PRO is a dedicated
channel status pin defmed as C.S. bit O. Also, if
in professional mode, C 1, C6, C7 and C9 are
dedicated C.S. pins. The inverse of C1 is logically OR'ed with channel status inp~ort bits
CIL and C1R. In similar fashion, C6, C7 and C9
are OR'ed with their respective input bits. Also,
the C bits in CUV128L and CUV128R are both
channel status block bit 128, which is bit 0 of
channel status byte 16.
CS8402A
Transparent Mode
In certain applications it is desirable to receive
digital audio data with the CS8412 and retransmit it with the CS8402A. In this case, channel
status, user and validity information must pass
through unaltered. For studio environments, AES
recommends that signal timing synchronization
be maintained throughout the studio. Frame synchronization of digital audio signals input to and
output from a piece of equipment must be within
±5%.
The transparent mode of the CS8402A is selected by setting TRNPT, pin 24, high. In this
mode, the CBL pin becomes an input, allowing
direct connection of the outputs of the CS8412
to the inputs of the CS8402A as shown in Figure 18. The transmitter and receiver are
synchronized by the FSYNC signal. CBL specifies the start of a new channel status block
boundary, allowing the transmit block structure
to be slaved to the block structure of the receiver. In the transparent mode, C, U, and V are
now transmitted with the current audio sample as
shown in Figure 17 (TRNPT high), and the dedicated channel status pins are ignored. When in
the transparent mode, the propagation delay of
data through the CS8402A is set so that the total
propagation delay from the receive inputs of the
CS8412 to the transmit outputs of the CS8402A
is three frames.
v+
MCK
CBL
TRNPT
C
311
RXP
U
TXP
v
RXN
FSYNC
TXN
II~
_ $C)<_
SP~Tt.
CS8412
CS8402A
Data
Figure 18. Transparent Mode Interface
DS60F1
6-23
_-_.
--..
~==~;=::.
CS8402A
When FSYNC is a word clock (Format 2), CBL
is sampled when left C,U,V are sampled. When
FSYNC is Left/Right, CBL is sampled when left
C,U,V are sampled, The channel status block
boundary is reset when CBL transitions from
low to high (based on two successive samples of
CBL). MCK for the CS8402A is normally expected to be 128 times the sample frequency, in
the transparent mode MCK must be 256 Fs.
Professional Mode
Setting PRO low places the CS8402A in professional mode as shown in Figure 19. In
professional mode, channel status bit 0 is transmitted as a one and bits 1, 2, 3, 4, 6, 7, and 9
can be controlled via dedicated pins. The pins
are actually the inverse of the identified bit. For
example, tying the Cl pin low places a one in
channel status bit 1. As shown in the Application
Note, Overview of AESIEBU Digital Audio Interface Data Structures, C 1 indicates
audio/non-audio; C6 and C7 determine the sample frequency; and C9 allows the encoded
channel mode to be stereophonic. EMI and EMO
determine emphasis and encode C2, C3, C4 as
M2
SDATA
8
S CK
6
FSY NC
M1
The channel status data cyclic redundancy check
character (C.S. byte 23) is always generated in-·
dependently for channels A and B and is
transmitted at the end of the channel status
block.
Data should not be input through the channel status
port, C, during the CRCC byte time frame, since inputs on C are logically OR'ed with internally
generated data.
Consumer Mode
Setting PRO high places the CS8402A in consumer
mode which redefines the pins as shown in Figure 20. In consumer mode, channel status bit 0 is
transmitted as a zero and channel status bits 2, 3, 8,
9, 15, 24, and 25 are controlled via dedicated pins.
The pins are actually the inverse of the bit so if pm
MO
.J.23 .J.22 121
Audio
Serial
Port
logic
7
C
~
U
~
V
~
Aux
I
~f---Validity
24
2
-'-
114 t3 13
EMO EM1
Mux ~
~
Biphase
Mark
Encoder
Driver
TXP
TXN
17
CRC
IPreamble
I Parity
.,.
PRO
f----rf----
U Bits
Registers
TRN PT
~
shown in Table 4. The dedicated channel status
pins are read at the appropriate time and are
logically OR'ed with datamput on the channel
status port, C. In Transparent Mode, these dedicated channel status pins are ignored; and
channel status bits are input at the C pin.
C1
14
C6
t
C7
f---f---f--
I Timing I,
15
112
C9
CBl
16
RST
5
MCK
Figure 19. CS8402A Block Diagram - Professional Mode
6-24
DS60F1
.....
_-_..._.-.
.-_
_
..-_
-_
CS8402A
C2 is tied high, channel status bit 2 will be transmitted as a zero. Also, FCO and FCI are encoded
versions of channel status bits 24 and 25, which
define the sample frequency. When FCO and
FC 1 are both high, the part is placed in a CD
submode which activates the CD subcode port.
This submode is described in detail in the next
section. Table 5 describes the encoding of C24
and C25 through the FCI and FCO pins. According to AES/EBU standards, C2 is copy
prohibit/permit, C3 specifies pre-emphasis, C8
and C9 define the category code, and C15 identifies the generation status of the transmitted
material (i.e.. first generation, second generation).
Consumer - CD Submode
The consumer CD submode is invoked by placing the pari in consumer mode (PRO = high) and
setting both FC 1 and FCO high. This mode redefines some of the pins for a CD subcode port as
shown in Figure 21. The CD subcode port pins,
SBF and SBC, replace the C and CBL pins respectively. The user data input, U, becomes the CD
subcode input. Figure 22 describes the timing for
the CD subcode port. When SBF is low, SBC becomes active, clocking in the subcode bits. SBF
goes high for one SCK period, one half SCK period after the active edge of FSYNC for all formats
(except format 4, which will be one and a half
SCK periods after the active edge of FSYNC).
SBF high for more than 16 SBC periods indicates
the start of a subcode block. The first, third, and
fourth Q bits after the start of a subcode block become channel status bits 5, 2, and 3 respectively.
Channel status bits are set by the dedicated pins;
the category code is forced to CD.
Comments
EM1
EMD
C2
C3
C4
FC1
FCD
C24
C25
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
48.0 kHz
1
0
1
0
0
1
0
1
1
32.0 kHz
1
1
0
0
0
1
1
0
0
44.1 kHz, CD Mode
Table 4. Emphasis Encoding
M2
S DATA
8
SCK
6
FSYNC
7
C
U
V
Ml
Table 5. Sample Frequency Encoding
MO
p3 +22 +21
Serial
Port
Logic
H
1
10
9
Registers
I
Audio
f--~
Aux
f--
CBits
~
I
U Bits
Validity
DS60F1
2
PRO
13
t4
Mux
~
Biphase
Mark
Encoder
---.
Driver
t
/
1
I Preamble
I
,
Parity
f-f-f--
15
-
I
Timing
TXN
16
RST
f----
13 114 12
FCO FCI C2 C?3 C8 C9 C15
I
TXP
17
I
I
T
44.1 kHz
5
CBL MCK
Figure 20. CS8402A Block Diagram Consumer Mode
6-25
-
-_ _-_
.. ...-.
. ..--_._.
__
CS8402A
.."
M2
M1
MO
23 122 121
SCK
6
FS YNC
7
SBF
U
SBC
V
rj
8
S DATA
Serial
Port
Logic
Subcode
Port
10
11
15
~
9
Register
Aux
rl
I
~
I
I
f-rf-
Audio
U Bits
r--
Validity
f-
f
2
3
24
PRO FCO FC1
4
1
H~;~:, ~
Driver
TXP
TXN
17
16
I Timing I,
r-
I Preamble
I
Biphase
Mark
Encoder
~ Mux ---
CBits
RST
f-
Parity
f
5
13114 t2
MCK
C2 C3 C8 C9 C15
Figure 21. CS8402A Block Diagram - Consumer Mode, CD Submode
SBF
II
II
1L(t-Jl-~
II
u
111111111
I11111111
! 11111111
111111111
m??m
111111111
SBC
11111111
' 11111111
' 11111111
11111111
II~ till
11111111
,-----------------------------SBF
u
l
, Data latched on rising edge
~----
P
Q
R
S
T
u
V
w
Figure 22. CD Subcode Port Timing
6-26
DS60F1
--------~-------------
CS8402A
PIN DESCRIPTIONS
CS8402A
CS BIT 7 1 CS BIT 3
PROFESSIONAL MODE
CS BIT 1 1 FREQ. CTRL. 0
CS BIT 6 1 CS BIT 2
MASTER CLOCK
SERIAL DATA CLOCK
FRAME SYNC
SERIAL INPUT DATA
VALIDITY INPUT
CS SERIAL IN 1 SC FRAME CLOCK
USER DATA INPUT
CS BIT 91 CS BIT 15
C7/C3
PRO
C1/FCO
C6/C2
MCK
SCK
FSYNC
SDATA
V
C/SBF
U
C9/C15
TRNPT/FC1TRANSPARENT/FREQ.CTRL1
M2
SERIAL PORT MODE SELECT 2
M1
SERIAL PORT MODE SELECT 1
MO
SERIAL PORT MODE SELECT 0
TXP
TRANSMIT POSITIVE
VD+
POWER
GND
GROUND
TXN
TRANSMIT NEGATIVE
RST
MASTER RESET
CBUSBC CS BLOCK OUT / SC BIT CLOCK
EMO/C9
EMPHASIS 0 1 CS BIT 9
EM1/C8
EMPHASIS 1 1 CS BIT 8
Power Supply Connections
-
VD+ - Positive Digital Power, PIN 19.
Positive supply for the digital section. Nominally +5 volts.
GND - Ground, PIN 18.
Ground for the digital section.
Audio Input Interface
SCK - Serial Clock, PIN 6.
Serial clock for SDATA pin which can be configured (via the MO, Ml, and M2 pins) as an
input or output, and can sample data on the rising or falling edge. As an output, SCK will
contain 32 clocks for every audio sample. As an input, it does not need to be continuous and
can be up to 15 MHz.
FSYNC - Frame Sync, PIN 7.
Delineates the serial data and may indicate the particular channel, left or right, and may be an
input or output. The format is based on MO, Ml, and M2 pins.
SDATA - Serial Data, PIN 8.
Audio data serial input pin.
MO, Ml, M2 - Serial Port Mode Select, PINS 21, 22, 23.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.
Control Pins
RST - Master Reset, PIN 16.
When low, all internal counters are reset and the line drivers are disabled, pulling low.
DS60F1
6-27
_.-_..--__.._-...
.-.-.
CS8402A
v - Validity, PIN 9.
Validity bit serial input port. This bit is defined according to the digital audio standards wherein
V = 0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio
signal is not suitable for conversion to analog, i.e. invalid. V is sampled once per subframe
U - User Bit, PIN 11.
User bit serial input port is sampled once per subframe.
PRO - ProfessionaUConsumer Select, PIN 2_._
Selects between professional mode (PRO low) and consumer mode (PRO high). This pin
defines the functionality of the next seven pins. PRO must be low for Transparent Mode, but
will have no effect on the channel status bits.
C9/C15 - Channel Status Bit!ll Channel Status Bit 15, PIN 12.
In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of b~_)). In consumer
mode, CIS is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in
Transparent Mode.
EMO/C9 - Emphasis 0 I Channel Status Bit 9, PIN 14.
!!!"professional mode, EMO and EMI encode channel status bits 2....], and 4. In consumer mode,
C9 is the inverse of channel status bit 9 (bit 1 or byte 1). EMO/C9 are ignored in Transparent
Mode.
EMlIC8 - Emphasis 11 Channel Status Bit 8, PIN 13.
!!!"professional mode, EMO and EMI encode channel status bits 2.....], and 4. In consumer mode,
C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EMlIC8 are ignored in Transparent
Mode.
C7IC3 - Channel Status Bit 7.LChannel Status Bit 3, PIN 1.
In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the
inverse of channel status bit 3. C7/C3 are ignored in Transparent Mode.
C6/C2 - Channel Status Bit 6.LChannel Status Bit 2, PIN 4.
In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the
inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode.
Cl/FCO - Channel Status Bit 11 Frequency Control 0, PIN 3.
In professional mode, Cl is the inverse of channel status bit 1. In consumer mode, FCO and
FCI are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When FCO
and FCI are both high, CD mode is selected. CIIFCO are ignored in Transparent Mode.
6-28
DS60F1
----------------------
CS8402A
TRNPTIFC1 - Transparent Mode I Frequency Control 1, PIN 24.
In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting
TRNPT high, allows the CS8402A to be connected directly to a CS8412.In transparent mode,
CBL is an input & MCK must be at 256 Fs.
In consumer mode, FCO and FCI are encoded versions of channel status bits 24 and 25. When
FCO and FC 1 are both high, CD mode is selected.
C/SBF - Channel Status Serial Input I Subcode Frame Clock, PIN 10.
In professional and consumer modes this pin is the channel status serial input port. In CD mode
this pin inputs the CD subcode frame clock.
CBUSBC - Channel Status Block Output I Subcode Bit Clock, PIN 15.
In professional and consumer modes, the channel status block output is high for the first 16
bytes of channel status. In CD mode, this pin outputs the subcode bit clock.
Transmitter Interface
MCK - Master Clock, PIN 5.
Clock input at 128x Fs the sample frequency which defines the transmit timing. In transparent
mode, MCK must be 256x Fs.
TXP, TXN - Differential Line Drivers, PINS 20, 17.
RS422 compatible line drivers. Drivers are pulled to low when part is in reset state.
DS60F1
6-29
-
._.-.
.-_
_
..--__.._-_
...
CS8401 A CS8402A
Appendix A: RS422 Driver Information
The RS422 drivers on the CS8401A and CS8402A
are designed to drive both the professional and consumer interfaces. The AESIEBU specification for
professionalJbroadcast use calls for a 1100 source
impedance and a balanced drive capability. Since the
transmitter impedance is very low, a 1100 resistor
should be placed in series with one of the transmit
pins. (A 1100 resistor in parallel with the transformer would, with the receiver impedance of 1100,
provide a 550 load to the part which is too low.)
The specifications call for a balanced output drive of
2-7 volts peak-to-peak into a 1100 load with no cable attached. Using the circuit in Figure AI, the
output of the transformer is short-circuit protected,
has the proper source impedance, and provides a
5 volt peak-to-peak signal into a 1100 load. Lastly,
the two output pins should be attached to an XLR
connector with male pins and a female shell, and
with pin 1 of the connector grounded.
CS8401/2A
1100
TXP
'--------'
TXN,
OF
1 XLR
~~~--"
Figure AI. Professional Output Circuit
In the case of consumer use, the specifications
call for an unbalanced drive circuit with an output impedance of 750 and a output drive level
of 0.5 volts peak-to-peak ±20% when measured
across a 750 load using no cable. The circuit
CS8401/2A
TXP
TXN
3740
fi\7cA
~ono
Figure A2. Consumer Output Circuit
6-30
CS8401/2A
TXP~-----------4
TTL or
TXN
CMOS Gate
Figure A3. TTL/CMOS Output Circuit
shown in Figure A2 only uses the TXP pin and
provides the proper output impedance and drive
level using standard 1% resistors. The connector
for consumer would be an RCA phono socket.
This circuit is also short circuit protected.
The TXP pin may be used to drive TTL or
CMOS gates as shown in Figure A3. This circuit
may be used for optical connectors for digital
audio since they are usually TTL compatible.
This circuit is also useful when driving multiple
digital audio outputs since RS422 line drivers
have TTL interfaces.
The transformer should be capable of operating
from 1.5 to 7 MHz, which is the audio data rate
of 25 kHz to 55 kHz after biphase-mark encoding. Transformers provide isolation from ground
loops, 60 Hz noise, and common mode noise
and interference. One of the important considerations when choosing transformers is minimizing
shunt capacitance between primary and secondary windings. The higher the shunt capacitance,
the lower the isolation between primary and secondary, and the more coupling of high frequency
energy. This energy appears in the form of common mode noise on the receive side ground and
has the potential to degrade analog performance.
Therefore, for best performance, shielded transformers optimized for minimum shunt
capacitance should be used. The following are a
few typical transformers:
Pulse Engineering
Telecom Products Group
7250 Convoy Ct.
San Diego, CA 92111
DS60F1
.-_
_
..--_._.
__.._-_.
...-
CS8401A CS8402A
(619) 268-2400
Part Number: PE65612
All internal timing is derived from MCK. On the
CS8402A, MCK is always 128xFs. On the
CS8401A, the external MCK is programmable
and is initially divided to 128xFs before being
used by the part. The internal clock IMCK used
in the following discussion is always 128xFs regardless of the external MCK pin.
Schott Corporation
1000 Parkers Lane Rd.
Wayzata, MN 55391
(612) 475-1173
FAX (612) 475-1786
Part Number:
67125450 - compatible with Pulse
67128990 - lower cost
67129000 - surface mount
67129600 - single shield
After RST, the CS8401A and CS8402A synchronize the internal timing to the audio data port,
more specifically FSYNC, to guarantee that
channel A is left channel data and channel B is
right channel data as per the AESIEBU specification. If FSYNC moves with respect to IMCK,
the transmitter could lose synchronization, which
causes an internal reset.
Scientific Conversions Inc.
42 Truman Drive
Novato, CA. 94947
(415) 8922323
Part Number:
SC916-01 - single shield
SC916-02 - surface mount
Appendix B: MCK and FSYNC Relationship
FSYNC should be derived either directly or indirectly from MCK. The indirect case could be a
DSP, providing FSYNC through its serial port,
using the same master oscillator that generates
MCK. In either case, FSYNC's relationship to
MCK is fixed and does not move. Since this appendix provides information on what would
happen if FSYNC did move with respect to
MCK, it does not apply to the majority of users.
Figure B 1 shows the structure of the serial port
input, to the transmitter output. The audio data is
serially shifted into Rl. PLD is an internal signal
that parallel loads R1 into the R2 buffer, and, at
the same time, the C, U, and V bits are latched.
On the CS8401A, the C, U, and V bits are held
in RAM, whereas on the CS8402A, they are
latched from external pins. The PLD signal rises
on the first SCK edge that can latch data. This is
coincident with the latching of the MSB of audio
data in MSB-first, left-justified modes. PLD
stays high for one SCK period. In the CS8402A
section, the arrows on SCK in Figure 16 indicate
when PLD goes high. Also, SBC in the
CS8402A CD submode is an external version of
PLD gated by the SBF input.
sDATA====:t----~RT1~-SNh~if~t(~in~)nRe=g~is~te=r-----------,
SCK
t
CS8402A C,U,V POrl
CS8401A Internal
Memory
~--'
~
,-_..- PLD (load signal)
R2 - Audio Buffer
11
IMCK __-1~__________~R~3_-~Sh~ift~(~o~ut~)_Re~g~is_te_r________~
2
Internal Reset
Driver
TXP
TXN
Figure Bl. Serial Port-to-Transmitter Block Diagram
DS60F1
6-31
-
----------------------
CS8401A CS8402A
;'---S.5_
SCK
FSYNC
J:
i:
SDATA_u:__________~______Le_ft_O________________~I~:_______R~ig~H~.tO________
CSS402A C,U, V JI_CUV191R
m-CUVOL
PLDJl~______~______________________~n~
____~_______
IMCK
LDS __________~~n~
__________________________~__~~
TXXNP_Le_ft_1_91__~lv~lu~lc+IP~I~_,~i_________R~ig_ht_19_1____________~lv~l~ul~c~lp~I--~,~I_Le__
ftO
T
',HnL: 'Preamb.
',1~1_R,: Preamb.
-----------------------r-------_
CSS401A Flags _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L - _
_
_
CSS402ACBL
Figure B2. Serial Ports-to.Transmitter Timing (slave mode)
When the part is finished transmitting the preamble of a sub-frame, the internal signal LDS rises
to parallel-load R2 into R3 for transmission. After RST, the part synchronizes the audio port to
IMCK as shown in Figure B2. Since PLD is
based on. FSYNC and LDS is based on IMCK, if
FSYNC moves with respect to IMCK until PLD
and LDS occur at the same time, the data would
not be properly loaded into R3. If LDS and PLD
overlap, an internal reset is initiated causing the
timing to return to the initial state shown in Figure B2.
Ordering Guide
Model
Temperature Range
Package
CS8401A-CP
CS8401A-IP
CS8401A-CS
CS8401A-IS
o to 70°C'
-40 to 85 °C
o to 70°C'
-40 to 85 °C
24-Pin
24-Pin
24-Pin
24-Pin
Plastic
Plastic
Plastic
Plastic
.3" DIP
.3" DIP
SOIC
SOIC
CS8402A-CP
CS8402A-IP
CS8402A-CS
CS8402A-IS
o to 70 °C*
-40 to 85°C
o to 70°C'
-40 to 85 °C
24-Pin
24-Pin
24-Pin
24-Pin
Plastic
Plastic
Plastic
Plastic
.3" DIP
.3" DIP
SOIC
SOIC
* Although the '-CP' and '-CS' suffixed parts are guaranteed to operate over 0 to 70°C, they are
tested at 25°C only. If testing over temperature is desired, the '-IP' and '-IS' suffixed parts are
tested over their specified temperature range.'
.
6-32
DS60F1
----------------------
CS8401A CS8402A
TABLE OF CONTENTS:
CS8401l2A GENERAL DESCRIPTION
Line Drivers ..................................................................... 6-9
CS8401A DESCRIPTION ..................................................... 6-9
Parallel Port ...................................................................... 6-9
Status and Control Registers ........................................... 6-9
Serial Port ....................................................................... 6-12
Buffer Memory ................................................................ 6-13
Buffer Mode 0 ........................................................... 6-15
Buffer Mode 1 ........................................................... 6-15
Buffer Mode 2 ........................................................... 6-16
Buffer-Read and Interrupt Timing ................................... 6-17
CS8401A PIN DESCRIPTIONS ........................................... 6-18
-
CS8402A DESCRIPTION ..................................................... 6-20
Audio Serial Port ............................................................. 6-20
C, U, V Serial Port ........................................................... 6-22
RST and CBL .................................................................. 6-22
Transparent Mode ............................................................ 6-23
Professional Mode ........................................................... 6-24
Consumer Mode ............................................................... 6-24
Consumer - CD Submode ................................................ 6-25
CS8402A PIN DESCRIPTIONS ........................................... 6-27
APPENDIX A - RS422 Driver Information .......................... 6-30
APPENDIX B - MCK and FSYNC Relationship ................. 6-31
ORDERING GUIDE ............................................................. 6-32
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
For Our Free Review Service
Call Applications Engineering.
DS60F1
6-33
-____-_
.. ...-.
-. ..--_._.
CS8401A CS8402A
.Notes.
6-34
DS60F1
.... ...
.....,.,-_
.......
~
~~
CS8411 CS8412I
.."
~~
Semiconductor Corporation
Digital Audio Interface Receiver
General Description:
Features
• Monolithic CMOS Receiver
• Low-Jitter, On-Chip Clock Recovery
256xFs Output Clock Provided
The CS8411/12 are monolithic CMOS devices which receive and decode audio data according to the
AES/EBU, IEC 958, SIPDIF, & EIAJ CP-340 interface
standards. The CS8411/12 receive data from a transmission line, recover the clock and synchronization
signals, and de-multiplex the audio and digital data. Differential or single ended inputs can be decoded.
• Supports: AES/EBU, IEC 958,
S/PDIF, & EIAJ CP-340
Professional and Consumer Formats
The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
• Extensive Error Reporting
Repeat Last Sample on Error Option
The CS8412 de-multiplexes the channel, user, and validity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
• On-Chip RS422 Line Receiver
• Configurable Buffer Memory (CS8411)
VD+
DGND
VA+
FllT
AGND
page 6-67
page 6-68
ORDERING INFORMATION:
TABLE OF CONTENTS:
MCK
26
12
11
CS8411
13
RXP
4
RXN
SDATA
SCK
FSYNC
A4/FCK
A3-AO
8
D7· DO
VD+
DGND
VA+
FllT
AGND
ERF
MCK
24
CS
23
RDIWR
26
12
11
SDATA
SCK
FSYNC
14
28
C
U
VERF
INT
M3 M2 M1 MO
CS8412
RXP
RXN
CS121
FCK
SEl
COl Cal Cbl Cel
EO E1 E2 FO
Cd!
F1
Cel
F2
ERF
CBl
Preliminary Product Intormationl ThiS .document contains infon~ation for a. new. product. C~stal
.
Semiconductor reserves the nght to modify thiS product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
NOV '93
DS61PP4
6-35
-
--------...... -----------
CS8411 CS8412
ABSOLUTE MAXIMUM RATINGS (GND = OV, all voltages with
Parameter
respect to ground)
Symbol
Power Supply Voltage
Min
Max
Units
6.0
VD+, VA+
V
.'
Input Current, Any Pin Except Supply
Note 1
±10
lin
rnA
Input Voltage, Any Pin except RXP, RXN
VIN
-0.3
VD+ + 0.3
V
Input Voltage, RXP and RXN
VIN
-12
12
V
Ambient Operating Temperature (power applied)
TA
-55
125
°C
Tstg
-65
150
°C
Storage Temperature
Notes:
1. Transient currents of up to 100 rnA will not cause SCR latch-up.
WARNING:
Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = OV; all voltages with respect to ground)
Parameter
Power Supply Voltage
Supply Current
VA+
VD+
Ambient Operating Temperature: CS8411/12-CP or -CS Note 2
Symbol
Min
Typ
Max
VD+,VA+
4.5
5.0
5.5
V
20
35
10
mA
mA
IA
ID
TA
Power Consumption
25
70
°C
85
°C
248
mW
-40
CS8411/12-IP or -IS
Notes:
7
0
135
PD
..
Units
2. The '-CP' and '-CS' parts are specified to operate over 0 to 70°C but are tested at 25 °C only.
The '-IP' and '-IS' parts are tested over the full-40 to 85°C temperature range.
DIGITAL CHARACTERISTICS
(TA = 25°C for suffixes '-CP' & '-CS', TA = -40 to 85°C for '-IP' & '-IS'; VD+, VA+ = 5V ± 10%)
Symbol
Min
except RXP, RXN
VIH
2.0
except RXP, RXN
VIL
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
(10 = 200!!A)
VOH
Low-Level Output Voltage
(10
=-3.2mA)
VOL
Input Leakage CUrrent
CS8411/12-CP or -CS
CS8411 /12-1 P or -IS
Master Clock Frequency
Note 3
MCK Clock Jitter
0.4
25
30
MCK
6.4
tj
V
V
1.0
FS
FS
Units
V
VD+ - 1.0
MCK Duty Cycle (high time/cycle time)
Notes:
Max
+0.8
lin
Input Sample Frequency (Note 3)
Typ
256xFS
V
10
!!A
55
50
kHz
kHz
14.08
MHz
200
ps RMS
50
%
3. Fs is defined as the incoming audio sample frequency per channel.
Specifications are subject to change without notice.
6-36
DS61PP4
--------..- .. _----------
CS8411
CS8412
DIGITAL CHARACTERISTICS - RS422 RECEIVERS
(RXP, RXN pins only; VD+, VA+ = 5V
± 10%)
Parameter
Input Resistance
Symbol
Note 4
(-7V < VCM < 7V)
Differential Input Voltage, RXP to RXN (-7V < VCM < 7V) Note 4,5
Input Hysteresis
Notes:
Min
ZIN
Typ
Max
kQ
50
mV
200
VTH
VHYST
Units
10
mV
4. VCM - Input Common Mode Range
5. When the receiver inputs are configured for single ended operation (e.g. consumer configuration) the signal
amplitude must exceed 400mVp-p for the differential voltage on RXP to RXN to exceed 200mV. This represents
SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT
(TA = 25°C for suffixes '-CP' and '-CS'; TA = -40 to 85°C for suffixes '-IP' and '-IS';
VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; CL = 20 pF)
Parameter
Symbol
Min
ADDRESS valid to CS low
tadcss
13.5
CS high to ADDRESS invalid
Typ
Max
Units
ns
tcsadh
0
ns
RDIWR valid to CS low
trwcss
10
ns
CS low to RDIWR invalid
tcsrwi
35
ns
tcsl
35
ns
ns
CSlow
DATA valid to CS rising
RDIWR low (writing)
tdcssw
32
CS high to DATA invalid
RDIWR low (writing)
tcsdhw
0
CS falling to DATA valid
RDIWR high (reading)
tcsddr
CS rising to DATA Hi-Z
RDIWR high (reading)
tcsdhr
ns
35
5
ns
ns
A4-AO
tadcss
cs
1 < - - - - tesl - - - - > I
n ......
- - o j . I - - - - t esrwi - - - - 0 1
ROIWR
Writing
<
07-DO
ROIWR
Reading
<
07-00
CS8411 Parallel Port Timing
DS61PP4
6-37
-
_.-_......__-_
...-.
-~-.-.
CS8411 CS8412
SWITCHING CHARACTERISTICS - SERIAL 'PORTS
(TA = 25°C for suffixes '-CP' and '-CS'; TA = -40 to 85°C for suffixes '-IP' and '-IS';
VD+, VA+ = 5V + 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; CL = 20 pF)
Parameter
SCK Frequency
Symbol
Master Mode
Notes 5,6
Slave Mode
Min
Typ
Max
OWRx32
fsck
OWRx32
Note 6
Units
Hz
TBD
Hz
20
ns
SCK falling to FSYNC delay
Master Mode
Notes 6,7
tsfdm
-20
SCK Pulse Width low
Slave Mode
Note 6
tsckl
40
ns
SCK Pulse Width High
Slave Mode
Note 6
tsckh
40
ns
SCK rising to FSYNC edge delay Slave Mode
Notes 6,7
tsfds
20
ns
FSYNC edge to SCK rising setup Slave Mode
Notes 6,7
tfss
20
ns
Note 7
tssv
SCK falling (rising) to SDATA valid
C, U, CBl valid to FSYNC edge
CSB412
MCK to FSYNC edge delay
FSYNC from RXN/RXP
Notes:
Note 7
20ns
tcuvf
1lfsck
s
tmfd
15
ns
5. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.
(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods
in one audio sample. In Slave mode 32 SCK periods must be provided in most serial port formats.
6. In master mode SCK and FSYNC are outputs. In Slave mode they are inputs. In the CSB411, coritrol
reg. 2 bit 1, MSTR, selects master. In the CSB412, formats 1 & 3 are slaves.
7. The table above assumes data is output on the falling edge and latched on the rising edge. With both
parts the edge is selectable. The table is defined 10J the CSB411 with control reg. 2 bit 0, SCED, set
to one, and for the CSB412 in formats 2, 3, 5 - 7. For the other formats, the table and figure edges
must be reversed (i.e.. "rising" to "failing" and vice versa).
FSYNC
MCK~
tmfd
SCK
FSYNC
FSYNC Generated From Received Data
SDATA
C,U
Mode 1
FSYNC
FSYNC
SCK
SCK
tssv
SDATA
SDATA
Mode 3
Serial Output Timing - Slave Mode
6-38
Serial Output Timing - Master Mode & C, U Port
DS61PP4
----------------------
-CS8411
CS8412
+5Vdigital
+5Vanalog
0.1 uF
=f
VA+
AGND
21
9
VD+
25
ERF
-
14
-
24
-
23
CS
1kn
r~
RDIWR
FlLT
Audio
Data
Processor
26
INT
RXN
5kn
11
12
FSYNC
SCK
SDATA
CS8411
~
19
MCK
RXP
10
(See Appendix A)
-
7
122
V
Receiver
Circuit
±0.1UF
.!.
Audio
Data
Processor
AO-A4
DO- D7
DGND
0.047 uF
...
..
or
Microcontroller
-
~
1
Figure 1. CS8411 Typical Connection Diagram
+5V digital
+5Vanalog
0.1 uF
Receiver
Circuit
(See Appendix A)
=f=
V
21
9
10
13
Channel Status
and/or
Error/Frequency
Reporting
16
25
~0.1UF
-
122
7
VA+
AGND
VD+
MCK
RXP
RXN
VERF
SCK
SDATA
28
12
26
FSYNC
11
CS12/FCK
C
SEL
U
ERF
CBL
FILT
Audio
Data
Processor
L.
CS8412
6 C/ E-F bits
20
19
1
14
Microcontroller
or
Logic
15
DGND
1kn
8
0.047UF
-
~
Figure 2. CS8412 Typical Connection Diagram
DS61PP4
6-39
_..
_.-_..--_-...._-_
.....
GENERAL DESCRIPTION
The CS8411112 are monolithic CMOS circuits
that receive and decode audio and digital data according to the AESIEBU, IEC 958, SIPDIF, and
EIAJ CP-340 interface standards. Both chips contain RS422 line receivers and Phase-Locked
Loops (PLL) that recover the clock andsynchronization signals, and de-multiplex the audio and
digital data. The CS8411 contains a configurable
internal buffer memory, read via a parallel port,
which can buffer channel status, user, and optionally auxiliary data. The CS8412 de-multiplexes
the channel status, user, and validity information
directly to serial output pins with dedicated pins
for the most important channel status bits. Both
chips also contain extensive error reporting as
well as incoming sample frequency indication for
auto-set applications.
Familiarity with the AESIEBU and IEC 958
specifications are assumed throughout this document. The App Note, Overview of Digital Audio
Interface Data Structures, contains information on
digital audio specifications; however, it is not
meant to be a complete reference. To guarantee
compliance, the proper standards documents
should be obtained. The AES/EBU standard
AES3-1985, should be obtained from the Audi~
Engineering Society or ANSI (ANSI document #
ANSI S4.40-1985); the IEC 958 standard from
the International Electrotechnical Commission'
and the EIAJ CP-340 standard from the Japanes~
Electronics Bureau.
Line Receiver
The RS422 line receiver can decode differential
as well as single ended inputs. The receiver consists of a differential input Schmitt trigger with
5.0mV of hysteresis. The hysteresis prevents noisy
SIgnals from corrupting the phase detector. Appendix A contains more information on how to
configure the line receivers for differential and
single ended signals.
6-40
CS8411
Clocks and Jitter Attenuation
The primary function of these chips is to recover
audio data and low jitter clocks from a digital
audio transmission line. The clocks that can be
generated are MCK (256xFs), SCK (64xFS), and
FSYNC (FS or 2xFS). MCK is the output of the
voltage controlled oscillator which is a component of the PLL. The PLL consists of phase and
frequency detectors, a second-order loop filter,
and a voltage controlled oscillator. All components of the PLL are on chip with the exception
of a resistor and capacitor used in the loop filter.
This filter is connected between the FILT pin and
AGND. The closed-loop transfer function, which
specifies the PLL's jitter attenuation characteristics, is shown in Figure 3. The loop will
begin to attenuate jitter at approximately 25 kHz
with another pole at 80 kHz, and will have 50 dB
of attenuation by IMHz. Since most data jitter introduced by the transmission line is high in
frequency, it will be strongly attenuated.
Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the
incoming data stream and to prevent false lock
conditions. When the PLL is not locked to the incoming data stream, the frequency detectors pull
the VCO frequency within the lock range of the
PLL. When no digital audio data is present, the
VCO frequency is pulled to its minimum value.
As a master, SCK is always MCK divided by
four, producing a frequency of 64xFs. In the
CS841l, FSYNC can be programmed to be a divided version of MCK or it can be generated
directly from the incoming data stream. In the
CS8412, FSYNC is always generated from the incoming data stream. When FSYNC is generated
from the data, its edges are extracted at times
when intersymbol interference is at a minimum.
This provides a sample frequency clock that is as
spectrally pure as the digital audio source clock
for moderate length transmission lines. For long
transmission lines, the CS8411 can be pro-
DS61PP4
---------------------OdB
CS8411
---,-~~~--~---,-~--~------.- ,- ,-"r
-
-
-
- ,-
-
"
-, m -
-
-
-
-, -
- ,-
,,,
25dB
"o
~
~"
«
- - -, - - ,-
50dS
;-
.~
-,
- - - -"- - - - -
75dB
-- --
"
-" - - - - - - - - - " - - - - - - - - - - - - "
100dB -'-----'---'-'T---'---------'---'--'T-----'--'----'-'+I-----'--'----'-'+I-----'---'---'--"il
1kHz
10kHz
1OOkHz
Jitter Frequency
1MHz
10MHz
Figure 3. Jitter Attenuator Characteristics
grammed to generate FSYNC from MCK instead
of from the incoming data.
CS8411 DESCRIPTION
The CS8411 is more flexible than the CS8412 but
requires a microcontroller or DSP to load internal
registers. The CS8412 does not have internal registers so it may be used in a stand-alone mode
where no microprocessor or DSP is available.
The CS8411 accepts data from a transmission line
coded according to the digital audio interface
standards. The LC. recovers clock and data, and
separates the audio data from control information.
The audio data is output through a configurable
serial port and the control information is stored in
internal dual-port RAM. Extensive error reporting
is available via internal registers with the option
of repeating the last sample when an error occurs.
A block diagram of the CS8411 is shown in Figure4
Parallel Port
The parallel port accesses two status registers,
two interrupt enable registers, two control registers, and 28 bytes of dual-port buffer memory.
The status registers and interrupt enable registers
DS61PP4
occupy the same address space. A bit in control
register 1 selects the two registers, either status or
interrupt enable, that occupy addresses 0 and 1 in
the memory map. The address bus and the
RDIWR line should be valid when CS goes low.
If RDIWR is low, the value on the data bus will
be written into the buffer memory at the specified
address. If RDIWR is high, the value in the buffer
memory, at the specified address, is placed on the
data bus. Detailed timing for the parallel port can
be found in the Switching Characteristics - Parallel Port table.
The memory space on the CS8411 is allocated as
shown in Figure 5. There are three defined buffer
modes selectable by two bits in control register 1.
Further information on the buffer modes can be
found in the Control Registers section.
Status and IEnable Registers
The status and interrupt enable registers occupy
the same address space. The IERISR bit in control
register 1 selects whether the status registers
(IERISR = 0) or the IEnable registers (IERISR =
1) occupy addresses 0 and 1. Upon power-up, the
control and IEnable registers contain all zeros;
therefore, the status registers are visible and all
interrupts are disabled. The IERISR bit must be
set to make the IEnable registers visible.
6-41
-
_-_
.. ...
.-_--._.-.
-..
__
VA+
22
'CS8411
FILT AGND
20
21
MCK
19
I Bi-phase I
Decoder
RXP
RXN
~n
Clock & Data
Recovery
I
I
H
Audio
Serial
Port
De-Multiplexor :
I
1I
VD+
DGND
crc
check
~
SCK
~
SDATA
1
user
Buffer
Memory
C.S.
28X8
slipped
parity
validity
crc
coding
no lock
confidence
Frequency
Comparator
~
aUx
~
I
FSYNC
Control
Registers
2X8
IConfidence
Flag
~
IEnable
&
Status
4X8
I
!
113
}4
~
~
~
~
INT
ERF
CS
RDIWR
8
A4/ AO- DOFCK A3
D7
Figure 4_ CS8411 Block Diagram
Status register I (SRI), shown in Figure 6, reports all the conditions that can generate a pulse
of four SCLK cycles on the interrupt pin (INT).
The three least significant bits, FLAG2-FLAGO,
are used to monitor the ram buffer. These bits
continually change and indicate the position of
the buffer pointer which points to the buffer
memory location currently being written. Each
flag has a corresponding interrupt enable bit in
IEnable register I which, when set, allows a transition on the flag to generate a pulse on the
interrupt pin. FLAGO and FLAG I cause interrupts on both. edges whereas FLAG2 causes an
interrupt on the rising edge only. Further information, including timing, on the flags can be found
in the Buffer Memory section.
6-42
The next five bits; ERF, SLIP, CCHG,
CRCE/CRCI, and CSDIF/CRC2, are latches
which are set when their corresponding conditions occur, and are reset when SRI is read.
Interrupt pulses are generated the first time that
.condition occurs. If the status register is not read,
further instances of that same condition will not
generate another interrupt. ERF is the error flag
bit and is set when the ERF pin goes high. It is an
OR'ing of the errors listed in status register 2,
bits 0 through 4, AND'ed with their associated interrupt enable bits in IEnable register 2.
SLIP is only valid when the audio port is in slave
mode (FSYNC and SCK are inputs to the
CS8411). This flag is set when an audio sample is
dropped or reread because the audio data output
from the part is at a different frequency than the
DS61PP4
----------- -----------
CS8411
data received from the transmission line. CCHG
is set when any bit in channel status bytes 0
through 3, stored in the buffer, changes from one
block to the next. In buffer modes 0 and 1, only
one channel of channel status data is buffered, so
CCHG is only affected by that channel.
(CS2/CS 1 in CRI selects which channel is buffered.) In buffer mode 2 both channels are
buffered, so both channels affect CCHG. This bit
is updated after each byte (0 to 3) is written to the
buffer. The two most significant bits in SRI,
CRCE/CRCI and CSDIF/CRC2, are dual function flags. In buffer modes 0 and 1, they are
CRCE and CSDIF, and in buffer mode 2, they are
0
2
Status 1 II Enable 1
-------Status 2/1Enable 2
------_
~0~1 ~g~er J.- __
Control
3
2
4
5
User Data
6
7
8
9
A
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
LettC. S.
Data
C.S.
Data
Lett
C.S.
Data
B
C
A
0
0
R
D
E
F
E
10
S
S
11
12
Last
20 Bytes
Channel
Status
Data
U
N
D
E
F
I
N
E
IEnable register 1, which occupies the same address space as status register 1, contains interrupt
enable bits for all conditions in status register 1. A
"1" in a bit location enables the same bit location
in status register 1 to generate an interrupt pulse.
A "0" masks that particular status bit from causing an interrupt.
Status register 2 (SR2) reports all the conditions
that can affect the error flag bit in SRI and the
error pin (ERF), and can specify the received
clock frequency. As previously mentioned, the
first five bits of SR2 are AND'ed with their interrupt enable bits (in IER2) and then OR'ed to
create ERF. The V, PARITY, CODE, LOCK, and
0
1st Four
Bytes of
Right
C. S. Data
13
CRCI and CRC2. In buffer modes 0 and 1, the
channel selected by the CS2/CS 1 bit is stored in
RAM and CRCE indicates that a CRC error occurred in that channel. CSDIF is set if there is any
difference between the channel status bits of each
channel. In buffer mode 2 channel status from
both channels is buffered, with CRC 1 indicating a
CRC error in channel 1 and CRC2 indicating a
CRC error in channel 2. CRCE, CRCl, and
CRC2 are updated at the block boundary. Block
boundary violations also cause CRCl,2 or CRCE
to be set.
x:oo
r::c;;,,=,;r;o;~.,,---"--,--"----r--".--r---''--,--'--,--''---J
SRI
~~~~4---~---+---4----~--+-~
14
Auxiliary
Data
15
16
IERI _
INTERRUPT ENABLE BITS FOR ABOVE -,----->1
SRI:
CSDIF: CS differenl between sub-frames. Buf. modes 0 & I.
CRC2: CRC Error - sub-frame 2. Buffer mode 2 only.
CRCE: CRC Error - selected sub-frame. Buffer modes 0 & I.
CRCI: CRC Error- sub-frame 1. Buffer mode 2 only.
CCNG: Channel Status changed
SLIP: Slipped an audio sample
ERF: Error Flag. ORing of all errors in SR2.
FLAG2: High for first four bytes of channel status
FLAGI: Memory mode dependent - See Figure II
FLAGO: High for last two bytes of user data.
Right
C.S.
Data
17
18
19
lA
lB
lC
10
lE
IERI:
Enables the corresponding bij in SR I.
A "I' enables the interrupt. A '0" masks the interrupt.
lF
o
2
3
Memory Mode
Figure 5. CS8411 Buffer Memory Map
DS61PP4
Figure 6, StatusJIEnable Register 1
6-43
-
_.-_..--_._.
__.._-_
...-.
CONF bits are latches which are set when their
corresponding conditions occur, and are reset
when SR2 is read. The ERF pin is asserted each
time the error occurs assuming the interrupt enable bit in IER2 is set for that particular error.
When the ERF pin is asserted, the ERF bit in SRI
is set. If the ERF bit was not set prior to the ERF
pin assertion, an interrupt will be generated (assUlning bit 3 in IER1 is set). Although the ERF
pin is asserted for each occurrence of an enabled
error condition, the ERF bit will only cause an
interrupt once if SRI is not read.
V is the validity status bit which is set any time
the received Validity bit is high. PARITY is set
when a parity error is detected. CODE is set when
a biphase coding error is detected. LOCK is asserted when the receiver PLL is not locked and
occurs when there is no input on RXPIRXN, or if
the received frequency is out of the receiver lock
range (25 kHz to 55 kHz). Lock is achieved after
receiving three frame preambles followed by one
block preamble, and is lost after four consecutive
frame preambles are not received. CONF is the
confidence flag which is asserted when the received data eye opening is less than half a bit
period. This indicates the transmission link is
poor and does not meet specifications.
CS8411
The upper three bits in SR2, FREQ2-FREQO, can
report the receiver frequency when the receiver is
locked. These bits are only valid when FCEN in
control register 1 is set, and a 6.144 MHz clock is
applied to the FCK pin. When FCEN is set, the
A4IFCK pin is used as FCK and A4 is internally
set to zero; therefore, only the lower half of the
buffer can be accessed. Table 2 lists the frequency
ranges reported. The FREQ bits are updated three
times per block and the clock on the FCK pin
must be valid for two thirds of a block for the
FREQ bits to be accurate. The vast majority of
audio systems must meet the 400 ppm tolerance
listed in the table. The 4% tolerance is provided
for unique situations where the approximate frequency needs to be known, even though that
frequency is outside the normal audio specifications.
IEnable register 2 has corresponding interrupt enable bits for the first five bits in SR2. A "1"
enables the condition in SR2 to cause ERF to go
high, while a "0" masks that condition. Bit 5 is
unused and bits 6 and 7, the two most significant
bits, are factory test bits and must be set to zero
when writing to. this register. The CS8411 sets
these bits to zero on power-up.
Control Registers
The CS8411 contains two control registers. Control register 1 (CR1), at address 2, selects system
level features, while control register 2 (CR2) , at
address 3, configures the audio serial port.
SR2:
FREQ2: The 3 FREO bits indicate incoming sample freq.
FRE01:
FREOO:
(must have 6.144 MHz clock on FCK pin
and FCEN must be "1")
CONF: Confidence error
LOCK: Out-of-Lock error
CODE: Coding violation
PARITY: Parity error
V: Validity bit high
IER2:
TEST1,0: (0 on power-up) Must stay at "0".
INT. ENABLES: Enables the corresponding bit in SR2.
A "1" enables the interrupt. A "0" masks the interrupt.
Figure 7. StatusIIEnable Register 2
6-44
In control register 1, when RST is low, all outputs
are reset except MCK (FSYNC and SCLK are
high impedance). After the user sets RST high,
the CS8411 comes fully out of reset when the
block boundary is found. The serial port, in master mode, will begin to operate as soon as RST
goes high. BO and B 1 select one of three buffer
modes listed in Table 1 and illustrated in Figure 5.
In all modes four bytes of user data are stored. In
mode 0, one entire block of channel status is
stored. In mode 1 eight bytes of channel status
DS61PP4
----------- -----------
CS8411
and sixteen bytes of auxiliary data are stored. In
mode 2, eight bytes of channel status from each
sub-frame are stored. The buffer modes are discussed in more detail in the Buffer Memory
section. The next bit, CS2/CS 1, selects the particular sub-frame of channel status to buffer in
modes 0 and 1, and has no effect in mode 2.
When CS2/CS 1 is low, sub-frame 1 is buffered,
and when CS2/CS 1 is high, sub-frame 2 is buffered. IERISR selects which set of registers, either
IEnable or status, occupy addresses 0 and 1.
When IERISR is low, the status registers occupy
the first two addresses, and when IERISR is high,
the IEnable registers occupy those addresses.
FCEN enables the internal frequency counter. A
6.144 MHz clock must be connected to the FCK
pin as a reference. The value of the FREQ bits in
SR2 are not valid until two thirds of a block of
data is received. Since FCK and A4, the most significant address bit, occupy the same pin, A4 is
internally set to zero when FCEN is high. Since
A4 is forced to zero, the upper half of the buffer
is not accessible while using the frequency compare feature. FPLL determines how FSYNC is
derived. When FPLL is low, FSYNC is derived
X:02
7
6
5
4
3
CR1 I FPLLIFCENIIERISR ICS2ICS1 I B1
2
1
0
BO IXIRSTI
FPLL: 0 - FSYNC from RXP/RXN, 1 - FSYNC from PLL
FCEN: enables freq. comparator (FCK must be 6.144 MHz).
IERISR: [X:00,01] 0 - status, 1 - interrupt enable registers.
.CS2ICS1: ch. status to buffer; 0 - sub-frame 1,1 - sub-frame 2.
B1: with BO, selects the buffer memory mode.
BO: with B1, selects the buffer memory mode.
RST: Resets internal counters. Set to "1' for normal operation.
Figure 8. Control Register 1
from the incoming data, and when FPLL is high,
it is derived from the internal phase-locked loop.
Control Register 2 configures the serial port
which consists of three pins: SCK, SDATA, and
FSYNC. SDATA is always an output, but SCK
and FSYNC can be configured as inputs or outputs. FSYNC and SDATA can have a variety of
relationships to each other, and the polarity of
SCK can be controlled. The large variety of audio
data formats provides an easy interface to most
DSPs and other audio processors. SDATA is normally just audio data, but special modes are
provided that output received biphase data, or received NRZ data with zeros substituted for
preamble. Another special mode allows an asynchronous SCK input to read audio data from the
serial port without slipping samples. In this mode
FSYNC and SDATA are outputs synchronized to
the SCK input. Since SCK is asynchronous to the
received clock, the number of SCK cycles between FSYNC edges will vary.
X:03
7
6
5
4
3
2
1
0
CR2 I ROER I SDF2 1 SDF1 I SDFO I FSF1 I FSFO I MSTR I SCED I
ROER: Repeat previous value on error (audio data)
SDF2: with SDFO & SDF1, select serial data format.
SDF1: with SDFO & SDF2, select serial data format.
SDFO: with SDF1 & SDF2, select serial data format.
FSF1: with FSFO, select FSYNC format.
FSFO: with FSF1, select FSYNC formal.
MSTR: When set, SCK and FSYNC are outputs.
SCED: When set, falling edge of SCK outputs data.
When clear, rising edge of SCK outputs data.
Figure 9. Control Register 2
FREQ2 FREQ1 FREQO
Sample Frequency
0
0
0
Out of Range
0
0
1
4BkHz±4%
1
0
44.1 kHz ± 4%
B1
BO
Mode
Buffer Memory Contents
0
0
0
0
Channel Status
0
1
1
32 kHz±4%
0
1
1
Auxiliary Data
1
0
0
48 kHz ± 400 ppm
1
0
2
3
Independent Channel Status
1
0
1
44.1 kHz ± 400 ppm
Reserved
1
1
0
44.056 kHz ± 400 ppm
1
1
1
32 kHz ± 400 ppm
1
1
Table 1. Buffer Memory Modes
DS61PP4
Table 2. Incoming Sample Frequency Bits
6-45
-
-____-_
.. ......
. --_._.
....
CS8411
1) or inputs (MSTR = 0). When FSYNC and
SCK are inputs (slave mode) the audio data can
be read twice or missed if the device controlling
FSYNC and SCK is on a different time-base than
the CS8411. If the audio data is read twice or
missed, the SLIP bit in SRI is set. SCEDselects
the SCK edge to output data on. SCED high
causes data to be output on the falling edge, and
SCED low causes data to be output on the rising
edge.
ROER, when set, causes the last audio sample to
be reread if the error pin, ERF, is active. When
out of lock, the CS8411 will output zeros if
ROER is set and output random data if ROER is
not set. The conditions that activate ERF are
those reported in SR2 and enabled in IER2. Figure 10 illustrates the modes selectable by
SDF2-SDFO and FSFI-FSFO. MSTR, which in
most applications will be set to one, determines
whether FSYNC and SCK are outputs (MSTR =
FSF MSTR
10 (bit)
00
0 FSYNC Input
_ - - - - 32 Bits -----~,,~,- - - - 32 Bits - - - - - - 0 , 0 ,
,
,
,
::~:::::::::::::::~::-::-:::::-:::~:
::~:::::::::::::::~:::::::::::::::~:
01
0
FSYNC Input
10
0
FSYNC Input
11
a
FSYNC Input IL~
00
1
FSYNC Output ~ 16 Clocks
,I.
16 Clocks
d
01
1
FSYNCOutput ~ 16 Clocks
oJ.
16 Clocks
==-+il-_____---'
10
1
FSYNC Output --JF'===~3i22CC:klo;;;jCks~=====~'I~'=====-:3~2~C~IO~C~ks~==~'r--
11
1
FSYNC Output
SDF
210 (bit)
000
Name
MSB First - 32
001
MSBLast
011
LSB Last - 16
LSB Last - 18
101
LSB Last- 20
111
SPECIAL MODES:
SDF
210 MSTR Name
100 0 Async SCK
~
r---
i
______________~
'--____---.-Jr--L--
I~'=~==~32~C~I~OC~ks~===~+;==:::====-i!Cl;~;-====~ol_~_ _ _
IMSBI
~ 16 Bits ----.j
IMSBI
ILSBI
~ 18 Bits------+l
IMSBI
I LSBI
20 Bits
MSBI
I Ls:1
=::TLSB1
=rLSBl
IMSBI
~ 16 Bits
IMSBI
I--- 24 Bits, Incl. Aux~
I LSBI
~18Bits~
~
IMSBI
I'
=n=sa:1
----.j
j4---
ILS~I
20 Bits
I MSBI
I--- 24 Bits, Incl. Aux ~
IMSBI
I LSB I
- I ' 24 Bits, Incl. Aux
MSBI
I MSBI
,',
1 LSBIMSBI
IMSBI
I LsslMSBI
I LSB I
24 Bits, Incl. Aux
tMSBC
"
ILSBIMSBI
--~";;;;===::::1~6[!B!ijit~S===~;;'-'~0'~';;~==]1~6~Bn~s~===~~"~:=
1100
MSBFirst-24
010
a
MSBFirst-16
010'
1
NRZ Data
100'
1
Bi-Phase Data _ _--'---_ _ _.:;:Bc--i-P=--:hC-"a=-se::.:M"'-a:::.r"-k=D_a=ta=-_ _---'-_ _--=B:..ci--'-P;c::ha::::s-=-e-".M;=:ar""k.:;:D.=at=a_ _ _-'-_ _
1 LSBIMSBI
--~"==~==~J3~2]B~its~===~~~",t==;=~~3~2~Bi~ts~==~~~"~~=
I AUX I LSB
MSB I VUCP 1
I AUX I LSB
MSB I VUCP 1
IAU:x
• Error Hags are not accurate in these modes
Figure 10. CS8411 Serial Port SDATA and FSYNC Timing
6-46
DS61PP4
.._-_
_.-_..--_._.
__
...-.
Audio Serial Port
The audio serial port outputs the audio data portion from the received data and consists of three
pins: SCK, SDATA, and FSYNC. SCK clocks the
data out on the SDATA line. The edge that SCK
uses to output data is programmable from CR2.
FSYNC delineates the audio samples and may indicate the particular channel, left or right.
Figure 10 illustrates the multitude of formats that
SDATA and FSYNC can take.
NORMAL MODES
SCK and FSYNC can be inputs (MSTR = 0) or
outputs (MSTR = 1), and are usually programmed as outputs. As outputs, SCK contains 32
periods for each sample and FSYNC has four formats. The first two output formats of FSYNC
(shown in Figure 10) delineate each word and the
identification of the particular channel must be
kept track of externally. This may be done using
the rising edge of FLAG2 to indicate the next
data word is left channel data. The last two output
formats of FSYNC also delineate each channel
with the polarity of FSYNC indicating the particular channel. The last format has FSYNC
change one SCK cycle before the frame containing the data and may be used to generate an I2S
compatible interface.
When SCK is programmed as an input, 32 SCK
cycles per sample must be provided. (There are
two formats in the Special Modes section where
SCK can have 16 or 24 clocks per sample.) The
four modes where FSYNC is an input are similar
to the FSYNC output modes. The first two require a transition of FSYNC to start the sample
frame, whereas the last two are identical to the
corresponding FSYNC output modes. If the circuit generating SCK and FSYNC is not locked to
th~ master clock of the CS8411, the serial port
w~ll eventually be reread or a sample will be
mlssed. When this occurs, the SLIP bit in SRI
will be set.
DS61PP4
CS8411
SDATA can take on five formats in the normal
serial port modes. The first format (see Figure 10), MSB First, has the MSB aligned with the
start of a sample frame. Twenty-four audio bits
are output including the auxiliary bits. This mode
is compatible with many DSPs. If the auxiliary
bits are used for something other than audio data,
they must be masked off. The second format
MSB Last, outputs data LSB first with the MSB
aligned to the end of the sample frame. This format is conducive to serial arithmetic. Both of the
above formats output all audio bits from the received data. The last three formats are LSB Last
formats that output the most significant 16, 18,
and 20 bits respectively, with the LSB aligned to
the end of the sample frame. These formats are
used by many interpolation filters.
SPECIAL MODES
Five special modes are included for unique applications. In these modes, the master bit, MSTR,
must be defmed as shown in Figure 10. In the
first mode, Asynchronous SCK, FSYNC (which
is an output in this mode) is aligned to the incoming SCK. This mode is useful when the SCK is
locked to an external event and cannot be derived
from MCK. Since SCK is asynchronous, the
number of SCK cycles per sample frame will
vary. The data output will be MSB first, 24 bits,
and aligned to the beginning of a sample frame.
The second and third special modes are unique in
that they contain 24 and 16 SCK cycles respectively per sample frame, whereas all normal
modes contain 32 SCK cycles. In these two
modes, the data is MSB first and fills the entire
frame. The fourth special mode outputs NRZ data
including the V, U, C, and P bits and the preamble
replaced with zeros. SCK is an output with
32 SCK cycles per sample frame. The fifth mode
outputs the biphase data recovered from the transmission line with 64 SCK cycles output per
sample frame, with data changing on the rising
edge.
6-47
-
.-------.,.......
-.------Normally, data recovered by the CS8411 is delayed by two frames in propagating through the
part, but in the fourth and fifth special modes, the
data is delayed only a few bit periods before being output. However, error codes, and the C, U
and V bits follow the normal a pathway with a
two frame delay (so that the error code would be
output with the offending data in the other
modes). As a result, in special modes four and
five, the error codes are nearly two frames behind
the data output on SDATA.
Buffer Memory
ill all buffer modes, the status, mask, and control
registers are located at addresses 0-3, and the user
data is buffered at locations 4 through 7. The parallel port can access any location in the user data
buffer at any time; however, care should be taken
not to read a location when that location is being
updated internally. This internal writing is done
through a second port of the buffer and is done in
a cyclic manner. As data is received, the bits are
assembled in an internal 8-bit shift register which,
when full, is loaded into the buffer memory. The
first bit received is stored in DO and, after D7 is
received, the byte is written into the proper buffer
memory location.
The user data is received one bit per sub-frame.
At the channel status block boundary, the internal
pointer for writing user data is initialized to 04H
(Hex). After receiving eight user bits, the byte is
written to the address indicated by the user
pointer which is then incremented to point to the
next address. After receiving all four bytes of user
data, 32 audio samples, the user pointer is set to
04H again and the cycle repeats. FLAGO, in SRI
can be used to monitor the user data buffer. When
the last byte of the user buffer, location 07H, is
written, FLAGO is set low and when the second
byte, location 05H, is written, FLAGO is set high.
If the corresponding bit in the interrupt enable
register (IERI, bit 0) is set, a transition of FLAGO
will generate a low pulse on the interrupt pin. The
level of FLAGO indicates which two bytes the
6-48
CS8411
part will write next, thereby indicating which two
bytes are free to be read.
FLAG I is buffer mode dependent and is discussed in the individual buffer mode sections. A
transition of FLAG 1 will generate an interrupt if
the appropriate interrupt enable bit is set.
FLAG2 is set high after channel status byte 23,
the last byte of the block, is written and set low
after channel status byte 3 is written to the buffer
memory. FLAG2 is unique in that only the rising
edge can cause an interrupt if the appropriate interrupt enable bit in IERI is set.
Figure 11 illustrates the flag timing for an entire
channel status block which includes 24 bytes of
channel status data per channel and 384 audio
samples. The lower portion of Figure 11 expands
the first byte of channel status showing eight
pairs of data, with a pair defined as a frame. This
is further expanded showing the first sub-frame
(AO) to contain 32 bits defined as per the digital
audio standards. When receiving stereo, channel A is left and channel B is right.
For all three buffer modes, the three most significant bits in SRI, shown in Figure 6, can be used
to monitor the channel status data. In buffer
mode 2, bits 7 and 6 change definition and are described in that section. Channel status data, as
described in the standards, is independent for
each channel. Each channel contains its own
block of channel status data, and in most systems,
both channels will contain the same channel
status data. Buffer modes 0 and 1 operate on one
block of channel status with the particular block
selected by the CS2/CSI bit in CRl. CSDIF, bit 7
in SRI, indicates when the channel status data for
each channel is not the same even though only
one channel is being buffered. CRCE, bit 6 in
SRI, indicates a CRC error occurred in the buffered channel. CCRG, bit 5 in SRI, is set when
any bit in the buffered channel status bytes 0 to 3,
change from one block to the next.
DS61PP4
----------- -----------
CS8411
FLAGI in status register 1, SRI, can be used to
monitor the channel status buffer. In mode 0,
FLAG 1 is set low after channel status byte 23
(the last byte) is written, and is set high when
channel status byte 15, location 17H is written. If
the corresponding interrupt enable bit in IERI is
set, a transition of FLAG 1 will generate a pulse
on the interrupt pin. Figure 12 illustrates the
memory write sequence for buffer mode 0 along
with flag timing. The arrows on the flag timing
indicate when an interrupt will occur if the appropriate interrupt enable bit is set. FLAGO can
cause an interrupt on either edge, which is only
shown in the expanded portion of the figure for
clarity.
BUFFER MODE 0
The user data buffer previously described is identical for all modes. Buffer mode 0 allocates the
rest of the buffer to channel status data. This
mode stores an entire block of channel status in
24 memory locations from address 08H to IPH.
Channel status (CS) data is different from user
data in that channel status data is independent for
each channel. A block of CS data is defined as
one bit per frame, not one bit per sub-frame;
therefore, there are two blocks of channel status.
The CS2/CS 1 bit in CRI selects which channel is
stored in the buffer. In a typical system sending
stereo data, the channel status data for each channel would be identical.
-
Block
(384 Audio Samples)
Flag2
~----------------------~~
~
Flag 10 ,
Mode
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Flag 1
Modes 1 &2:
Flag 0
23' 0
1 2 3
AO
I
I
BO
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 '0
Channel Status Byte
I
A1
I
B1
I
A21
B2
I-_-_-_-i-_-_-_I
A71
1
B71
Expa=nded)==---=-==~
~
•
bit,O
34
78
I Preamble I Aux Data I LSB
Sub-frame
--------------------~
2728293031
MSB I V I u I C I P I
Audio Data
validity~~J
userData~
Channel Status Data
Parity Bit
Figure 11. CS8411 Status Register Flag Timing
DS61PP4
6-49
----------------------
CS8411
Block
(384 Audio Samples)
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r___
FLAG2~
FLAG1
le-___----'-__________-:------'f
t-
FLAGO
o 1 2 3, 4 5 6 7 S 9 10 11 12 13 14 15 16 17 1S 19 20 21 22 23: 0
c.s. Byte
C.S.Address :os--OB: OC------------------~---·1F: o s -
~d)
I
,
FLAGO t
C.S. Addr. 1 F:
User Addr. 07,
'
04
f
t
f
t
os
05
09:
07'
OA
05
OB
07
06
04
06
(Addresses are in Hex)
Figure 12. CS8411 Buffer Memory Write Sequence - MODE 0
Block
(384 Audio Samples)
~----~------~------~------~----~r---
FLAG2~
FLAG 1
FLAGO
C.S. Byte
,0
1
2
~ 4 5
6
~ S 9 10
11:
12 13 14 15 16 17 1S 19 20 21 22 2~ 0
C.S. Address' OS-OB, O C - - Of; OC - - Of; O C - - Of; O C - - O~ O C - - O~ OS-
L-----______Q(E§:X~P~a~n~d~e:d~)____~(AddreSses are in Hex)
"I
FLAG1
t
f
t
f
t
f
t
FLAGOt
09,
OS,
OA,
OB,
C.S. Addr. OF:
05,
07,
05,
User Addr. 07'
06
07,
04
06
04
Aux. Addr. 1 F' 10 -13,14-17: 1S-1 B,1C-1 F: 10--+13,14-17: 1S-1 B,1C-1F:
Figure 13. CS8411 Buffer Memory Write Sequence - MODE 1
6-50
DS61PP4
-_
--------.. _----------
CS8411
BUFFER MODE 1
In buffer mode 1, eight bytes are allocated for
channel status data and sixteen bytes for auxiliary
data as shown in Figure 5. The user data buffer is
the same for all modes. The channel status buffer,
locations 08H to OFH, is divided into two sections. The first four locations always contain the
first four bytes of channel status, identical to
mode 0, and are written once per channel status
block. The second four locations, addresses OCH
to OFH, provide a cyclic buffer for the last
20 bytes of channel status data. The channel
status buffer is divided in this fashion because the
first four bytes are the most important ones;
whereas, the last 20 bytes are often not used (except for byte 23, CRC).
FLAG 1 and FLAG2 can be used to monitor this
buffer as shown in Figure 13. FLAG 1 is set high
when CS byte 1, location 09H, is written and is
toggled when every other byte is written. FLAG2
is set high after CS byte 23 is written and set low
after CS byte 3, location OBH, is written .. FLAG2
determines whether the channel status pointer is
writing to the first four-byte section of the channel status buffer or the second four-byte section,
while FLAG 1 indicates which two bytes of the
section are free to update.
The auxiliary data buffer, locations 10H to IFH,
is written to in a cyclic manner similar to the
other buffers. Four auxiliary data bits are received
per audio sample (sub-frame) and, since the auxiliary data is four times larger than the user data,
the auxiliary data buffer on the CS8411 is four
times larger allowing FLAGO to be used to monitor both.
BUFFER MODE 2
In buffer mode 2, two 8-byte buffers are available
to independently buffer each channel of channel
status data. Both buffers are identical to the channel status buffer in mode 1 and are written to
simultaneously, with locations 08H to OFH containing CS data for channel A and locations 10H
to 17H containing CS data for channel B. Both
Block
(384 Audio Samples)
FLAG1
FLAGO
C.S.Byte
0123'4567'891011'12131415'161718192021222301
Left C.S. Ad. : 0 8 - 0 B : O C - OF: O C - OF: O C - OF: O C - OF: O C - OF: 08RightC.S.Ad.: 1 0 - 1 3 : 1 4 - 1 7 : 1 4 - 1 7 : 1 4 - 1 7 : 1 4 - 1 7 : 1 4 - 1 4 : 10-
~ded)
I
FLAG1
f
t
t
+
t
FLAGO
Left C.S. Ad. :
Right C.S. Ad. '
User Address'
!
04
08,
10:
05'
09,
11:
06
07'
04
t
i
t
OA,
12:
05'
OB,
13:
07'
06
(Addresses are in Hex)
Figure 14. CS8411 Buffer Memory Write Sequence - MODE 2
DS61PP4
6-51
-
.._-_
.-_
_
..--_._.
__
...-.
CS8411
CS buffers can be monitored using FLAG 1 and
FLAG2 as described in the BUFFER MODE 1
section.
SCK is 64 times the incoming sample frequency,
and is the same SCK output in master mode. The
FSYNC shown is valid for all master modes except the I2S compatible mode. The interrupt pulse
is shown to be 4 SCK periods wide and goes low
5 SCK periods after the RAM is written. Using
the above information, the entire data buffer may
be read starting with the next byte to be updated
by the internal pointer.
The two most significant bits in SRI change definition for buffer mode 2. These two bits, when
set, indicate CRC errors for their respective channels. A CRC error occurs when the internal
calculated CRC for channel status bytes 0
through 22 does not match channel status byte 23.
CCHG, bit 5 in SRI, is set when any bit in the
first four channel status bytes of either channel
changes from one block to the next. Since channel status doesn't change very often, this bit may
be monitored rather than checking all the bits in
the first four bytes. These bits are illustrated in
Figure 6.
ERF Pin Timing
ERF signals that an error occurred while receiving the audio sample that is currently being read
from the serial port. ERF changes with the active
edge of FSYNC and is high during the errorred
sample. ERF is affected by the error conditions
reported in SR2: CONF, LOCK, CODE, PARITY,
and V. Any of these conditions may be masked
off using the corresponding bits in IER2. The
ERF pin will go high for each error that occurs.
The ERF bit in SRI is different from the ERF pin
in that it only causes an interrupt the first time an
error occurs until SRI is read. More information
on the ERF pin and bit is contained at the end of
the Status and [Enable Registers section.
Buffer Updates and Interrupt Timing
As mentioned previously in the buffer mode sections, conflicts between externally reading the
buffer RAM and the CS8411 internally writing to
it may be averted by using the flag levels to avoid
the section currently being addressed by the part.
However, if the interrupt line, along with the
flags, is utilized, the actual byte that was just updated can be determined. In this way, the entire
buffer can be read without concern for internal
updates. Figure 15 shows the detailed timing for
the interrupt line, flags, and the RAM write line.
riilflJUlJlJUU1f
r~lliUlJ1~
i
~
~
~
SCK
r--:--:--::-:-:--,------;--------;-'~
FSYNC
--.J
IWRITE
Jl
Left 191
: 1
~
I
Right 1911:
I
I
Left 0
:
p
:~:'~I~---~----~---,
I
L ._ _ _ _
INT
(FLAGO,1)
INT
(FLAG2)
~
~
_ _ _ _
r.~~
'--------'
~~------,
~~
FSF1,O=10
MSTR
1
SCED
1
=
=
Figure 15. RAMlBuffer-Write and Interrupt Timing
6-52
DS61PP4
_.-_..--__.._-_
...
._.-.
CS8411
PIN DESCRIPTIONS:
CS8411
DATA BUS BIT 2
DATA BUS BIT 3
DATA BUS BIT 4
DATA BUS BIT 5
DATA BUS BIT 6
DATA BUS BIT 7
DIGITAL POWER
DIGITAL GROUND
RECEIVE POSITIVE
RECEIVE NEGATIVE
FRAME SYNC
SERIAL DATA CLOCK
ADD BUS BIT 4 / FCLOCK
INTERRUPT
02
03
04
05
06
07
VO+
OGNO
RXP
RXN
FSYNC
SCK
A4IFCK
INT
01
00
SOATA
ERF
CS
ROIWR
VA+
AGNO
FILT
MCK
AO
A1
A2
A3
DATA BUS BIT 1
DATA BUS BIT 0
SERIAL OUTPUT DATA
ERROR FLAG
CHIP SELECT
READIWRITE SELECT
ANALOG POWER
ANALOG GROUND
FILTER
MASTER CLOCK
ADDRESS BUS BIT 0
ADDRESS BUS BIT 1
ADDRESS BUS BIT 2
ADDRESS BUS BIT 3
-
Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive supply for the digital section. Nominally +5 volts.
VA+ - Positive Analog Power, PIN 22.
Positive supply for the analog section. Nominally +5 volts. This supply should be as
quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock.
DGND - Digital Ground, PIN 8.
Ground for the digital section. DGND should be connected to same ground as AGND.
AGND - Analog Ground, PIN 21.
Ground for the analog section. AGND should be connected to same ground as DGND.
Audio Output Interface
SCK - Serial Clock, PIN 12.
Serial clock for SDATA pin which can be configured (via control register 2) as an input
or output, and can sample data on the rising or falling edge. As an input, SCK must
contain 32 clocks for every audio sample in all normal audio serial port formats.
OS61PP4
6-53
.-_
_
..--_._.
__.._-_
...-.
CS8411
FSYNC - Frame Sync, PIN 11.
Delineates the serial data and may indicate the particular channel, left or right. Also,
FSYNC may be configured as an input or output. The format is based on bits in control
register 2.
SDATA - Serial Data, PIN 26.
Audio data serial output pin.
ERF - Error Flag, PIN 25.
Signals that an error has occurred while receiving the audio sample currently being read
from the serial port. The errors that cause ERF t() go high are enumerated in status
register 2 and enabled by setting the corresponding bit in IEnable register 2.
A4IFCK - Address Bus Bit 4IFrequency Clock, PIN 13.
This pin has a dual function and is controlled by the FCEN bit in control register 1. A4
is the address bus pin as defined below. When used as FCK, an internal frequency
comparator compares a 6.144 MHz clock input on this pin to the received clock
frequency and stores the value in status register 1 as three FREQ bits. These bits
indicate the incoming frequency as well as the tolerance. When defined as FCK, A4 is
internally set to O.
Parallel Interface
CS - Chip Select, PIN 24.
This input is active low and allows access to the 32 bytes of internal memory. The
address bus and RDIWR must be valid while CS is low.
RDIWR - Read/Write, PIN 23.
If RDIWR is low when CS goes active (low), the data on the data bus is written to
internal memory. If RDIWR is high when CS goes active, the data in the internal
memory is placed on the data bus.
A4-AO - Address Bus, PINS 13,15-18.
Parallel port address bus that selects the internal memory location to be read from or
written to. Note that A4 is the dual function pin A4IFCK as described above.
DO-D7 - Data Bus, PINS 27-28, 1-6.
Parallel port data bus used to check status, read or write control words, or read internal
buffer memory.
6-54
DS61PP4
----------------------
CS8411
INT· Interrupt, PIN 14.
Open drain output that can signal the state of the internal buffer memory as well as
error information. A 5kQ resistor to VD+ is typically used to support logic gates. All
bits affecting INT are maskable to allow total control over the interrupt mechanism.
Receiver Interface
RXP, RXN • Differential Line Receivers, PINS 9, 10.
RS422 compatible line receivers. Described in detail in Appendix A.
Phase Locked Loop
MCK - Master Clock, PIN 19.
Low jitter clock output of 256 times the received sample frequency.
FILT - Filter, PIN 20.
An external lkQ resistor and O.047J..LF capacitor are required from the FILT pin to
analog ground.
DS61PP4
6·55
-
----------------------
OS8412
The line receiver and jitter performance are described in the sections directly preceding the
CS8411 sections in the beginning of this data
sheet.
CS8412 DESCRIPTION
The CS8412 does not need a microprocessor to
handle the non-audio data (although a micro may
be used with the C and U serial ports). Instead,
dedicated pins are available for the most important channel status bits. The CS8412 is a
monolithic CMOS circuit that receives and decodes digital audio data which was encoded
according to the digital audio interface standards.
It contains an RS422 line receiver and clock and
data recovery utilizing an on-chip phase-locked
loop. The audio data is output through a configurable serial port that supports 14 formats. The
channel status and user data have their own serial
pins and the validity flag is OR'ed with the ERF
flag to provide a single pin, VERF, indicating that
the audio output may not be valid. This pin may
be used by interpolation filters that provide error
correction. A block diagram of the CS8412 is illustrated in Figure 16.
RXP
RXN
VA+
FILT
AGND
~~
120
21
t
When M3 is low, the normal serial port formats
shown in Figure 17 are selected using M2, Ml,
and MO. These formats are also listed in Table 3,
wherein the first word past the format number
(Out-In) indicates whether FSYNC and SCK are
M3
.I
"I
I
Recovery
l
Timing
17
J
I De-Multiplexer
M2
M1
18
24
Audio
Serial
Port
•
BI-phase
Decoder
and
Frame
Svnc
1
~
I
~
~
check
1
Check
,
I~~e~:~:r
~
+J
~
Channel
Status
Latc
Error
Encoder
}
La
j;"
16
I
6~
COl
EO
Cal
E1
4+
3t
Cbl
E2
CcI
FO
23
~
FSYNC
~
SCK
~
SDATA
1
C
R
e
14--.
9
28--.
i
J
t
e
r
S
u
VERF
'----
15
25
CBL
ERF
}-
Multiplexer
5+
MO
s
•
~.
SEL
= 0)
-
~
CSl21 13
FCK
NORMAL MODES (M3
19
Clock & Data
Confidence I
Flao
VD+ ~
DGND
The audio serial port is used primarily to output
audio data and consists of three pins: SCK,
FSYNC, and SDATA. These pins are configured
via four control pins: MO, MI, M2, and M3. M3
selects between eight normal serial formats (M3 =
0), and six special forma~ (M3 = 1).
MCK
10
I
Audio Serial Port
2t
Cd!
F1
27+
Cel
F2
Figure 16. CS8412 Block Diagram
6-56
DS61PP4
----------- -----------
CS8412
outputs from the CS8412 or are inputs. The next
word (LIR-WSYNC) indicates whether FSYNC
indicates the particular channel or just delineates
each word. If an error occurs (ERF = 1) while
using one of these formats, the previous valid
audio data for that channel will be output. As long
as ERF is high, that same data word will be output. If the CS8412 is not locked, it will output all
zeroes. In some modes FSYNC and SCK are outputs and in others they are inputs. In Table 3,
LSBJ is short for LSB justified where the LSB is
justified to the end of the audio frame and the
MSB varies with word length. As outputs the
CS8412 generates 32 SCK periods per audio
sample (64 per stereo sample) and, as inputs, 32
SCK periods must be provided per audio sample.
When FSYNC and SCK are inputs, one stereo
sample is double buffered. For those modes
which output 24 bits of audio data, the auxiliary
bits will be included. If the auxiliary bits are not
used for audio data, they must be masked off.
SPECIAL MODES (M3
= 1)
When M3 is high, the special audio modes described in Table 4 are selected via M2, MI, and
MO. In formats 8, 9, and 10, SCK, FSYNC, and
SDATA are the same as in formats 0, 1, and 2 respectively; however, the recovered data is output
as is even if ERF is high, indicating an error. (In
modes 0-2 the previous valid sample is output.)
Similarly, when out of lock, the CS8412 will still
output all the recovered data, which should be zeros if there is no input to the RXP, RXN pins.
Format 11 is similar to format 0 except that SCK
is an input and FSYNC is an output. In this mode
FSYNC and SDATA are synchronized to the incoming SCK, and the number of SCK periods
between FSYNC edges will vary since SCK is
not synchronous to received data stream. This
mode may be useful when writing data to storage.
Format 12 is similar to format 7 except that
SDATA is the entire data word received from the
transmission line including the C, U, V, and P
bits, with zeros in place of the preamble. In format 13 SDATA contains the entire biphase
encoded data from the transmission line including
the preamble, and SCK is twice the normal frequency. The normal two frame delay of data from
input to output is reduced to only a few bit periods in formats 12 and 13. However, the C, U, V
bits and error codes follow their normal pathways
and therefore follow the output data by nearly
two frames. Figure 18 illustrates formats 12 and
13. Format 14 is reserved and not presently used,
and format 15 causes the CS8412 to go into a reset state. While in reset all outputs will be
inactive except MCK. The CS8412 comes out of
reset at the first block boundary after leaving the
reset state.
C, U, VERF, ERF, and CBL Serial Outputs
The C and U bits and CBL are output one SCK
period prior to the active edge of FSYNC in all
serial port formats except 2 and 3 (l 2S modes).
The active edge of FSYNC may be used to latch
C, U, and CBL externally. In formats 2 and 3,
M2
M1
MO
Format
o - Out, UR, 16-24 Bits
0
0
0
8 - Format 0 - No repeat on error
1
1 - In, UR, 16-24 Bits
0
0
1
9 - Format 1 - No repeat on error
0
2 - Out, UR, 12 S Compatible
0
1
0
10 - Format 2 - No repeat on error
1
3 - In, UR, 12 S Compatible
0
1
1
11 - Format 0 - Async. SCK input
0
4 - Out, WSYNC, 16-24 Bits
1
0
0
12 - Received NRZ Data
0
1
5 - Out, UR, 16 Bits LSBJ
1
0
1
13 - Received Bi-phase Data
1
0
6 - Out, UR, 18 Bits LSBJ
1
1
0
14 - Reserved
1
1
7 - Out, UR, MSB Last
1
1
1
15 - CS8412 Reset
M2
M1
MO
0
0
0
0
0
0
1
0
1
1
0
1
1
1
Format
Table 3. Normal Audio Port Modes (M3=O)
DS61PP4
Table 4. Special Audio Port Modes (M3=1)
6-57
-
----------------------
CS8412
FMT
No. M2 M1 MO
o
FSYNC (out) ~
000
FSYNC (in)
IMSBI
~
IMSBI
1MSBI
1
o
1 0
SCK(out)~- _- _-
SDATA (out) _ _--L[MS8J=S=-=B'-L
FSYNC (in)
3
o
1
1
_ILSBJ
IMSBI
4
100
0
1
_ILSBJ
[MSB]
Right
~ ~ ~ ~ L.ClLsBl--,,-S=--B'---_ _-'[MS8J_M_SB-->- ~ ~ ~ ~ lLsBl'-=L=SB::...L-_ _-----'[MSB]-'-'-M~SB::J
I
Left
Right
:01_ -_ -~~- _- _- _-01_ -_ -~--U-LJ
~ ~ ~ ~ c..:lLsBl=S=-B'---_ _-'[MS8J-:.:.M=S=-cB ~ ~ ~ ~ '-=[LSa]=SB::....L-_ _---'[MSB-:.:.M=S=B]
SCK(out)~- ~ __
1MSBI
FSYNC (out)~
1
1 _- _-
FSYNC(Out)~~:::: :L~~:::: :~~: ~ ~ :~ighj:: ~ ~ ~~
SDATA (out)
5
1
_-01_ -_ -~LrLrL: _- _- :01_ -_ -~--U-LJ
SCK(in) ~- _- _
SDATA (out) _ _---L[MS8J=S=BO-L
I
Right
1 _- _-
[MSB]
IL- -,__ ILJUL- -,__ IL- -,__ ~
FSYNC (outfIL_ _ _ _L_e_ft_ _ _---'
2
1 _- _- _[LSBJ
1
Left
SCK(in) ~- -, __
SDATA (out)
IL- -,_ JLJLfL- ~ __ IL- ~_ JL
1_- : _[LSBJ
1
I
Right
SCK(out) ~- ~ __
SDATA(out)
001
Left
1
1 _- _-
IL- ~ __ ~- ~ __ IL- ~ __ ~
.ILSBJ
IMSB 1
Left
SCK(out)~~ ~ ~ S~-
1
1 : _-
_ILSBJ
Right
[MSBJ
I
_- _- _- _- -_~- _- _- _- _- _- _S~- _- -_- _- _-_~
SDATA (out) L::[iSBJ=SB=-.L-_ _--'[MSB]-'-'-'M=SB=--c- _- _- _- _- _- _[LSBJL::L=SB=--'-_ _ _---'-[MSBJ.:.:.:M=-:SB::.J.- _- _- _- __- _~
1---16 Bits - - - - \
FSYNC (out) ~
6
1
1
0
Left
SCK(out) ~~ ~ ~ S~-
1---16 Bits----\
'--_ _ _ _R~ig~h_t_ _ _~1
_- _- _- _- _- _-~- _- _- _- _- _- _-S~- _- _- _- _- _-_~
SDATA(Out)c=lLsBl=SB=--.L-_ _--c[MSBJ-=M=SB=--c- _- _- _- _- _- JL.C
LsL
=S.::..8]
B c----_------'-----7[MSBJ=M=SB=--c- _- _- _- _- _-_~
1---18 Bits----\
FSYNC (out) ~
7
1
1
1
SCK(out)~~
Left
: : S~-
1---18 Bits----\
'--_ _ _~R~igh~t_ _ _ _~1
_- _- _- _- -_-~- _- _-- _- _-S~- _- _- _- _-
-_~
SDATA (out)L::[MSB]=S=B~_ _---'-lLsBl-=::LS=B:.L- _- _- _- _- _- _TMsB1'--'-'M=S=B-'--_ _ _c..:lLsBl=S=--.LB- _- _- _- _- _- _~
Figure 17. CS8412 Audio Serial Port Formats
6-58
DS61PP4
..--_
.-_--._..
....
.....
__
No.
12
CS8412
FSYNC (out)
SCK(out)
SDATA (out)
13
Right
,~--------~------~I
FSYNC (out)
SCK(out)
SDATA(out)
Figure 18. Special Audio Port Fonnats 12 and 13
dicates a serious error occurred on the transmission line. There are three errors that cause ERF to
go high: a parity error or biphase coding violation
during that sample, or an out of lock PLL receiver. Timing for the above pins is illustrated in
Figure 19.
the C and U bits and CBL are updated with the
active edge of FSYNC. The validity + error flag
(VERF) and the error flag (ERF) are always updated at the active edge of FSYNC. This timing is
illustrated in Figure 19.
The C output contains the channel status bits with
CBL rising indicating the start of a new channel
status block. CBL is high for the first four bytes
of channel status (32 frames or 64 samples) and
low for the last 20 bytes of channel status
(160 frames or 320 samples). The U output contains the User Channel data. The V bit is OR'ed
with the ERF flag and output on the VERF pin.
This indicates that the audio sample may be in
error and can be used by interpolation filters to
interpolate through the error. ERF being high in-
Multifunction Pins
There are Seven multifunction pins which contain
either error and received frequency information,
or channel status information, selectable by SEL.
ERROR AND FREQUENCY REPORTING
When SEL is low, error and received frequency
information are selected. The error information is
encoded on pins E2, E1, and EO, and is decoded
ifii
ifii
~
~
~
~
CBL
CO,
Ca-Ce
SDATA Right
FSYNC
ERF,
VERF
C,U
19~
I
:I
Left 0
Right 0
~
I
Ii
~Lelt1
Right 31
!
I
Lelt32
~
~
:!
!
I~
I~
Iw
'
\
:I
~
~
~
~
~
~
~
~
~
w
I~
~
I
I-J
I
~
~
IIW !
~
Right 191
: ! LeltO
'
\
:!
~
Figure 19. CBL Timing
DS61PP4
6-59
-
----------------------
CS8412
as shown in Table 5. When an error occurs, the
corresponding error code is latched. Clearing is
then accomplished by bringing SEL high for
more than eight MCK cycles. The errors have a
priority associated with their error code, with validity having the lowest priority and no lock
having the highest priority. Since only one code
can be displayed, the error with the highest priority that· occurred since the last clearing will be
selected.
The validity flag indicates that the validity bit for
a previous sample was high since the last clearing
of the error codes. The confidence flag occurs
when the received data eye opening is less than
half a bit period. This indicates that the quality of
the transmission link is poor and does not meet
the digital audio interface standards. The slipped
sample error can only occur when FSYNC and
SCK of the audio serial port are inputs. In this
case, if FSYNC is asynchronous to the received
data rate, periodically a stereo sample will be
dropped or reread depending on whether the read
rate is slower or faster than the received data rate.
When this occurs, the slipped sample error code
will appear on the 'E' pins. The CRC error is updated at the beginning of a channel status block,
and is only valid when the professional format of
channel status data is received. This error is indicated when the CS8412 calculated CRC value
does not match the CRC byte of the channel
status block or when a block boundary changes
(as in removing samples while editing). The par-
ity error occurs when the incoming sub-frame
does not have even parity as specified by the
standards. The biphase coding error indicates a
biphase coding violation occurred. The no lock
error indicates that the PLL is not locked onto the
incoming data stream. Lock is achieved after receiving three frame preambles then one block
preamble, and is lost after not receiving four consecutive frame preambles.
The received frequency information is encoded
on pins F2, Fl, and Fa, and is decoded as shown
in Table 6. The on-chip frequency comparator
compares the received clock frequency to an externally supplied 6.144 MHz clock which is input
on the FCK pin. The 'F' pins are updated three
times during a channel status block including
prior to the rising edge of CBL. CBL may be used
to externally latch the 'F' pins. The clock on FCK
must be valid for two thirds of a block for the 'F'
pins to be accurate.
CHANNEL STATUS REPORTING
When SEL is high, channel status is displayed on
CO, and Ca-Ce for the channel selected by CSI2.
If CS12 is low, channel status for sub-frame 1 is
displayed, and if CS12 is high, channel status for
sub-frame 2 is displayed. The contents of Ca-Ce
depend upon the CO professional/consumer bit.
The information reported is shown in Table 7.
E2
E1
EO
Error
F2
F1
FO
Sample Frequency
0
0
0
No Error
0
0
0
Out of Range
0
0
1
Validity Bit HiQh
0
0
1
48kHz±4%
0
1
0
Confidence Flag
0
1
0
44.1kHz±4%
0
1
1
Slipped Sample
0
1
1
32kHz±4%
1
0
0
CRC Error (PRO only)
1
0
0
48kHz ± 400 ppm
1
0
1
Parity Error
1
0
1
44.1 kHz ± 400 ppm
1
1
0
Bi-Phase Coding Error
1
1
0
44.056kHz ± 400 ppm
1
1
1
No Lock
1
1
1
32kHz ± 400 ppm
Table 5_ Error Decoding
6-60
Table 6. Sample Frequency Decoding
DS61PP4
_.-_..--_.-.
__.._-_
...-.
CS8412
Professional Channel Status (CO
= 0)
When CO is low, the received channel status
block is encoded according to the professionallbroadcast format. The Ca through Ce pins
are defined for some of the more important professional bits. As listed in Table 7, Ca is the
inverse of channel status bit 1. Therefore, if the
incoming channel status bit 1 is 1, Ca, defined as
CI, will be O. CI indicates whether audio
(CI = 1) or non-audio (CI = 0) data is being received. Cb and Cc, defined as EMO and EMI
respectively, indicate emphasis and are encoded
versions of channel status bits 2, 3, and 4. The decoding is listed in Table 8. Cd, defined as C9, is
the inverse of channel status bit 9, which gives
some indication of channel mode. (Bit 9 is also
defined as bit 1 of byte 1.) When Ce, defined as
CRCE, is low, the CS8412 calculated CRC value
does not match the received CRC value. This signal may be used to qualify Ca through Cd. If Ca
through Ce are being displayed, Ce going low can
indicate not to update the display.
Consumer Channel Status (CO = 1)
When CO is high, the received channel status
block is encoded according to the consumer format. In this case Ca through Ce are defined
differently as shown in Table 7. Ca is the inverse
of channel status bit 1, CI, indicating audio (Cl =
1) or non-audio (CI = 0). Cb is defined as the
inverse of channel status bit 2, C2, which indicates copy inhibit/copyright information. Cc,
defined as C3, is the emphasis bit of channel
status, with C3 low indicating the data has had
pre-emphasis added.
The audio standards, in consumer mode, describe
bit 15, L, as the generation status which indicates
whether the audio data is an original work or a
copy (1st generation or higher). The definition of
the L bit is reversed for three category codes: two
broadcast codes, and laser-optical (CD's). Therefore, to interpret the L bit properly, the category
code must be decoded. The CS8412 does this decoding internally and provides the ORIG signal
that, when low, indicates that the audio data is
original over all category codes.
SCMS
The consumer audio standards also mention a serial copy management system, SCMS, for dealing
with copy protection of copyrighted works.
SCMS is designed to allow unlimited duplication
of the original work, but no duplication of any
copies of the original. This system utilizes the
channel status bit 2, Copy, and channel status
bit 15, L or generation status, along with the category codes. If the Copy bit is 0, copyright
protection is asserted over the material. Then, the
L bit is used to determine if the material is an
original or a duplication. (As mentioned in the
previous paragraph, the definition of the L bit can
be reversed based on the category codes.) There
are two category codes that get special attention:
general and AID converters without C or L bit information. For these two categories the SCMS
standard requires that equipment interfacing to
these categories set the C bit to 0 (copyright protection asserted) and the L bit to 1 (original). To
support this feature, Ce, in the consumer mode, is
defined as IGCAT (ignorant category) which is
low for the "general" (0000000) and "AID converter without copyright information" (OllOOxx)
categories.
Pin
Professional
Consumer
CO
o (low)
1 (high)
Ca
C1
C1
EM1
EMO
C2
C3
Cb
EMO
C2
0
0
1
1
1
Cc
EM1
C3
0
1
1
1
0
C4
Cd
C9
ORIG
1
0
1
0
0
Ce
CRCE
IGCAT
1
1
0
0
0
Table 7. Channel Status Pins
DS61PP4
Table 8. Emphasis Encoding
6-61
-
-------------..,--------
CS8412
PIN DESCRIPTIONS:
CS8412
CHANNEL STATUS OUTPUT
C
CS d I FREQ REPORT 1
CdlF1
CS c I FREQ REPORT 0
Cc/FO
CS b I ERROR CONDITION 2
CblE2
CS a I ERROR CONDITION 1
Ca/E1
CS 0 I ERROR CONDITION 0
CO/EO
DIGITAL POWER
VD+
DGND
DIGITAL GROUND
RXP
RECEIVE POSITIVE
RECEIVE NEGATIVE
RXN
FRAME SYNC
FSYNC
SERIAL DATA CLOCK
SCK
CHANNEL SELECT I FCLOCK CS121FCK
U
USER DATA OUTPUT
VERF
CelF2
SDATA
ERF
M1
MO
VA+
AGND
FllT
MCK
M2
M3
SEl
CBl
VALIDITY + ERROR FLAG
CS e I FREQ REPORT 2
SERIAL OUTPUT DATA
ERROR FLAG
SERIAL PORT MODE SELECT 1
SERIAL PORT MODE SELECT 2
ANALOG POWER
ANALOG GROUND
FilTER
MASTER CLOCK
SERIAL PORT MODE SELECT 2
SERIAL PORT MODE SELECT 3
FREQ/CS SELECT
CS BLOCK START
Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive supply for the digital section. Nominally +5 volts.
VA+ - Positive Analog Power, PIN 22.
Positive supply for the analog section. Nominally +5 volts.
DGND - Digital Ground, PIN 8.
Ground for the digital section. DGND should be connected to same ground as AGND.
AGND - Analog Ground, PIN 21.
Ground for the analog section. AGND should be connected to same ground as DGND.
Audio Output Interface
SCK - Serial Clock, PIN 12.
Serial clock for SDATA pin which can be configured (via the MO, MI; M2, and M3
pins) as an input or output, and can sample data on the rising or falling edge. As an
output, SCK will generate 32 clocks for every audio sample. As an input, 32 SCK
periods per audio sample must be provided in all normal modes.
FSYNC - Frame Sync, PIN 11.
Delineates· the serial data and may indicate the particular channel, left or right, and may
be an input or output. The fonnat is based on MO, MI, M2, and M3 pins.
6-62
DS61PP4
----------- -----------
CS8412
SDATA - Serial Data, PIN 26.
Audio data serial output pin.
MO, Ml, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3
selects between eight normal modes (M3 = 0), and six special modes (M3 = 1).
Control Pins
VERF - Validity + Error Flag, PIN 28.
A logical OR'ing of the validity bit from the received data and the error flag. May be
used by interpolation filters to interpolate through errors.
U - User Bit, PIN 14.
Received user bit serial output port. FSYNC may be used to latch this bit externally.
C - Channel Status Output, PIN 1.
Received channel status bit serial output port. FSYNC may be used to latch this bit
externally.
CBL - Channel Status Block Start, PIN 15.
The channel status block output is high for the first four bytes of channel status and low
for the last 16 bytes.
SEL - Select, PIN 16.
Control pin that selects either channel status information (SEL = 1) or error and
frequency information (SEL = 0) to be displayed on six of the following pins.
CO, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.
These pins are dual function with the 'C' bits selected when SEL is high. Channel status
information is displayed for the channel selected by CSI2. CO, which is channel status
bit 0, defines professional (CO = 0) or consumer (CO = 1) mode and further controls the
definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
CS12 - Channel Select, PIN 13.
This pin is also dual function and is selected by bringing SEL high. CS 12 selects
sub-frame 1 (when low) or sub-frame 2 (when high) to be displayed by channel status
pins CO and Ca through Ceo
FCK - Frequency Clock, PIN 13.
Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the
received clock frequency with the value displayed on F2 through FO. Nominal input
value is 6.144 MHz.
DS61PP4
6-63
-
.-_
..--_._.
__.._-_
...-.
CS8412
EO, E1, E2 - Error Condition, PINS 4-6.
Encoded error information that is enabled by bringing SEL low. The error codes are
prioritized and latched so that the error code displayed is the highest level of error since
the last clearing of the error pins. Clearing is accomplished by bring SEL high for more
than 8 MCK cycles.
FO, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27.
Encoded sample frequency information that is enabled by bringing SEL low. A proper
clock on FCK must be input for at least two thirds of a channel status block for these
pins to be valid. They are updated three times per block, starting at the block boundary.
ERF - Error Flag, PIN 25.
Signals that an error has occurred while receiving the audio sample currently being read
from the serial port. Three errors cause ERF to go high: a parity or biphase coding
violation during the current sample, or an out of lock PLL receiver.
Receiver Interface
RXP, RXN - Differential Line Receivers, PINS 9, 10.
RS422 compatible line receivers.
Phase Locked Loop
MCK - Master Clock, PIN 19.
Low jitter clock output of 256 times the received sample frequency.
FILT - Filter, PIN 20.
An external lkn resistor and O.047/lF capacitor is required from FILT pin to analog
ground.
6-64
DS61PP4
_.-_..---__.._-_
...
._.-.
APPENDIX A: RS422 Receiver Information
The RS422 receivers on the CS8411 and
CS8412 are designed to receive both the professional and consumer interfaces, and meet all
specifications listed in the digital audio standards. Figure Al illustrates the internal schematic
of the receiver portion of both chips. The receiver has a differential input. A Schmitt trigger
is incorporated to add hysteresis which prevents
noisy signals from corrupting the phase detector.
CS8411
flowing down the shield of the cable that could
result when boxes with different ground potentials are connected. Generally, it is good practice
to ground the shield to the chassis of the transmitting unit, and connect the shield through a
capacitor to chassis ground at the receiver. However, in some cases it is advantagous to have the
ground of two boxes held to the same potential,
and the cable shield might be depended upon to
make that electrical connection. Generally, it
r-----------
I
8kl1
9
I RXP
16kl1
10
I RXN
I
I
16 kl1
Professional Interface
The digital audio specifications for professional
use call for a balanced receiver, using XLR connectors, with lIOn ± 20% impedance. (The
XLR connector on the receiver should have female pins with a male shell.) Since the receiver
has a very high impedance, a lIOn resistor
should be placed across the receiver terminals to
match the line impedance, as shown in Figure A2, and, since the part has internal biasing,
no external biasing network is needed. If some
isolation is desired without the use of transformers, a O.OIIlF capacitor should be placed on the
input of each pin (RXP and RXN) as shown in
Figure A3. However, if transformers are not
used, high frequency energy could be coupled
between transmitter and receiver causing degradation in analog performance.
Grounding the shield of the cable is a tricky issue. In the configuration of systems, it is
important to avoid ground loops and DC current
DS61PP4
8kl1
+
ff
4kl1
L ____
4kl1
-_--=- ____ _
l1li
Figure AI. RS422 Receiver Internal Circuit
XLR
CS8411/12
* See Text
T~i~~~ ~~~II"--_-IRXP
Pair
'----~--I
RXN
1
Figure A2. Professional Input Circuit
XLR
Although transformers are not required by AES
they are strongly recommended. The EBU requires transformers. Figures A2 and A3 show an
optional DC blocking capacitor on the transmission line. A 0.1 to 0.47/lf ceramic capacitor may
be' used to block any DC voltage that is accidentally connected to the digital audio receiver. The
use of this capacitor is an issue of robustness as
the digital audio transmission line does not have
a DC voltage component.
CS8412
1100
Twis~ed
!:
• See Text 0.0: "F
~I110 II
Pair
0.Q1 uF
T"112
RXP
RXN
1
Figure A3. Transformerless Professional Circuit
CS8411/12
RCA Phono
O.01~
75Q
Coax
O.01~
uF -::r
Figure A4. Consumer Input Circuit
6-65
----------------------
CS8411 CS8412
may be a good idea to provide the option of
grounding or capacitively coupling to ground
with a "ground-lift" circuit.
Consumer Interface
In the case of the consumer interface, the standards call for an unbalanced circuit having a
receiver impedance of 750 ±5%. The connector
for the consumer interface is an RCA phono plug
(fixed socket described in Table IV of IEC 26811). The receiver circuit for the consumer
interface is shown in Figure A4.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
TTUCMOS Levels
The following are a few typical transformers:
The circuit shown in Figure A5 may be used
when external RS422· receivers or TTUCMOS
logic drive the CS8411/12 receiver section.
Pulse Engineering
Telecom Products Group
7250 Convoy ct.
San Diego, CA 92111
(619) 268-2400
Part Number: PE65612
nUCMOS
_~~_~~1UF
CS8411112
~ 1 - - - - - - ; RXP
0.01
uFT
RXN
Figure AS. TIUCMOS Interface
Transformers
The transformer used in the professional interface should be· capable of operation from 1.5 to
7 MHz, which is the audio data rate of 25 kHz
to 55 kHz after biphase-mark encoding. Transformers provide isolation from ground loop,
60 Hz noise, and common mode noise and interference. One of the important considerations
when choosing transformers is minimizing shunt
capacitance between primary and secondary
windings. The higher the shunt capacitance, the
lower the isolation between primary and secondary and the more coupling that can occur for
high frequency energy. This energy appears in
the form of common mode noise on the receive
side ground and has the potential to degrade analog performance. Therefore, shielded
transformers optimized for minimum primary to
secondary capacitance may be desirable.
6-66
Schott Corporation
1000 Parkers Lane Rd.
Wayzata, MN 55391
(615) 889-8800
Part Number: 67125450
67128990 -lower cost
67129000 - surface mount
67129600 - single shield
Scientific Conversions Inc.
42 Truman Dr.
Novato, CA94947
(415) 892-2323
Part Number: SC916-01 - single shield
SC916-01A - improved version
SC937-01 - low profile
SC937-02 - surface mount
DS61PP4
----------------------
CS8411
CS8412
ORDERING GUIDE
Model
Temperature Range
Package
CS8411-CP
CS8411-IP
CS8411-CS
CS8411-IS
o to 70 °C*
-40 to 85°C
o to 70 °C*
-40 to 85°C
28-Pin
28-Pin
28-Pin
28-Pin
Plastic .6" DIP
Plastic .6" DIP
Plastic SOIC
Plastic SOIC
CS8412-CP
CS8412-IP
CS8412-CS
CS8412-IS
o to 70 °C*
-40 to 85°C
o to 70 °C*
-40 to 85°C
28-Pin
28-Pin
28-Pin
28-Pin
Plastic .6" DIP
Plastic .6" DIP
Plastic SOIC
Plastic SOIC
* Although the '-CP' and '-CS' suffixed parts are guaranteed to operate over 0 to 70°C, they are tested
at 25°C only. If testing over temperature is desired, the ' -IP' and '-IS' suffixed parts are
tested over their specified temperature range.
DS61PP4
6-67
-
----------------------
CS8411 CS8412
TABLE OF CONTENTS:
CS8411/12 GENERAL DESCRIPTION ........................... 6-40
Line Receivers ............................................................. 6-40
Clocks and Jitter Attentuation ..................................... 6-40
CS8411 DESCRIPTION .................................................... 6-41
Parallel Port .................................................................. 6-41
Status and Interrupt Enable Registers ......................... 6-41
Control Registers ......................................................... 6-47
Audio Serial Port ......................................................... 6-47
Normal Modes ....................................................... 6-47
Special Modes ........................................................ 6-47
Buffer Memory ............................................................ 6-48
Buffer Mode 0 ....................................................... 6-49
Buffer Mode 1 ....................................................... 6-51
Buffer Mode 2 ....................................................... 6-51
Buffer Updates and Interrupt Timing ...................... ~ ... 6-52
ERF Pin Timing ........................................................... 6-52
CS8411 PIN DESCRIPTIONS .......................................... 6-53
CS8412 DESCRIPTION .................................................... 6-56
Audio Serial Port ......................................................... 6-56
Normal Modes ....................................................... 6-56
Special Modes ........................................................ 6-57
C, U, VERF, ERF, and CBL Serial Outputs ................ 6-57
Multifunction Pins ....................................................... 6-59
Error and Frequency Reporting ............................. 6-59
Channel Status Reporting ...................................... 6-60
Professional Channel Status (CO==0) ................ 6-61
Consumer Channel Status (CO==I) ................... 6-61
SCMS ......................................................... 6-61
CS8412 PIN DESCRIPTIONS .......................................... 6-62
APPENDIX A: RS422 Receiver Information ................... 6-65
ORDERING GUIDE ......................................................... 6-67
TABLE OF CONTENTS ................................................... 6-68
6·68
DS61PP4
.. ......
..............
......
~
~.
CS8425
~-
Semiconductor Corporation
A-LAN - Audio Local Area Network Transceiver
General Description
Features
• Monolithic Digital Audio Transceiver for
Point-to-Point Transmission of Audio Data
• Supports D2B OPTICAL
• User Channel Used for Communication of
System Messages Between Nodes
• Sonfigurable Interface Port Supports SPI,
I C BUs®, Parallel Interface, or the
CS8425 Operates as Stand-alone Unit
• Supports Large Number of Nodes per
Network
• Also Applicable as General Purpose
IEC-958 Digital Audio Transceiver
FLT
XTO
XTI
RMCK
The A-LAN chip is a monolithic CMOS circuit that implements the physical layer of an Audio Local Area
Network. The A-LAN allows numerous pieces of audio
equipment such as CD players, digital equalizers, digital tape decks, DACs, amps, etc. to be connected in a
ring topology, sharing audio data from a designated
source. Control and configuration messages are
passed between nodes via a unique application of the
user channel.
Audio data is transmitted using the format specified by
IEC-958, and can be generated by anyone of multiple
nodes on the A-LAN. External drivers and receivers
are required for interface to the transmission media.
ORDERING INFORMATION
CS8425-CL, OOC to 70°C
CS8425-IL, -40°C to 85°C
44-pin PLCC
44-pin PLCC
RFSY RCBL RBCK RSDAO VERF
M1=O
M2=O
RXo----I
Receive
Buffers
7*16'8
AGND
Control &
Status
Registers
16'8
RESET
I
Interrupt
Control f - - - - - - - - - < > INT
DGND
Transmit
buffer
16'8
~
TX,
~
I
I
Receive
Common
Channel
~
I
Transmit
Common
~
.-------1
r--
1
TMCK
RUBIT
1
,-----------1
LL-M_U_X_ r - - - - t - - - 1 ,-_____
Transmit
Timing
REPRESENTS
PARALLEL
INTERFACE
TUBIT
~I=C=ha=n=ne=I~[-ITV
Transmit Audio Port
'--,-----,----,---------,-----,---,--1--<-1 TEMPH
1 1 1 1 1 1
TFSY
TCBL
TBCK
TSDA1
TSDA2
TSDAO
Preliminary Product Information I This .document contains info~ation for a. new. product. C~stal
,
Semiconductor reserves the nght to modify thiS product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1992
(All Rights Reserved)
AUG '93
DS93PP3
6-69
-_
..--_
-. ..--_._.
__
...-.
CS8425
ABSOLUTE MAXIMUM RATINGS
Parameter
PoWer Supply Voltage
Symbol
Min
VA+,VD+
0
Note 1
Input Current, Any Pin Except Supply
Max
.Units
6.0
V
±10
mA
VD+ + 0.3
V
liN
-0.3
Ambient Operating Temperature (power applied)
VIN
TA ..
-55
125
°c
Storage Temperature
Tstg
-65
150
°C
Input Voltage, All Pins
Notes:
1. Transient Currents of up to 100mA will not cause SCR latch-up.
WARNING: Operating the part beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = OV; all voltages with respect to ground.)
Parameter
Power Supply Voltage
Supply Current
Ambient Operating Temperature
Power Consumption
Notes:
Symbol
Min
Typ
Max
VD+, VA
4.5
5.0
5.5
V
20
12
35
18
mA
mA
70
85
°C
292
mW
Max
Units
VA+
VD+
IA
ID
CS8425-CL
CS8425-IL
TA
0
-40
Note 2
160
Units
2. Power consumption is measured with inputs at VD+ or GND, and outputs floating.
DIGITAL CHARACTERISTICS
(TA = 25°C for '-CL' suffix; TA = -40°C - 85°C for '-IL' suffix; VD+, VA+ = 5V±10%)
Parameter
High-Level Input Voltage
(Except XTI)
Symbol
Min
VIH
2.0
Low-Level Input Voltage
(Except XII)
VIL
High-Level Input Voltage
XTI
VIH
Low-Level Input Voltage
XTI
High-Level Output Voltage
(10 = 200~)
(Except XTO)
VOH
Low-Level Output Voltage
(10 = -3.2mA)
(Except XTO)
VOL
Input Leakage Current
(Except XTI & M1)
Received Serial Data Sample Frequency
0.8
.9VD+
.1VD+
Note 3
V
10
!LA
30
50
kHz
21.120
MHz
30
fOSC
9.60
RESET Low Time
tRST
200
6-70
0.4
6.4
Crystal Oscillator Frequency
3.
V
V
1.0
tj
Slave Modes
Master Mode
V
V
VD+-1.0
lin
FS
RMCK Clock Jitter
Notes:
V
VIL
Master Clock Frequency, RMCK, TMCK*
RMCK Duty Cycle
Typ
200
pSRMS
50
50
%
%
21.12
MHz
ns
RMCK is 33% duty cycle in master mode when the crystal is divided by 1.5. Otherwise, RMCK is 50%
duty cycle.
OS93PP3
_.-_..--__......_-_
..._.-.
CS8425
SWITCHING CHARACTERISTICS - SERIAL AUDIO DATA PORTS
(TA = 25°C for '-CL' suffix; TA = -40°C - 85°C for '-IL' suffix; VD+, VA+ = 5V±10%;
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF)
Symbol
Parameter
Bit Clock Frequency, TBCK, RBCK
Note 4
Min
fbck
Typ
Max
Units
64FS
15
MHz
TBCK Pulse Width Low
ttbckl
30
ns
TBCK Pulse Width High
ttbckh
30
ns
TBCK Edge to TFSY Edge Delay
Note 5
ttctfd
20
ns
TBCK Edge to TFSY Edge Setup
Note 5
ttctfs
20
ns
TSDAO/1/2, TCBL, TV Valid to TBCK Edge Setup Note 5, 6
tdvs
20
ns
TSDAO/1/2, TCBL, TV Valid to TBCK Edge Hold
Note 5,6
tdvh
20
Note 5
trcrf
-20
20
ns
Note 5
20
ns
RBCK Edge to RFSY & VERF Edge
RBCK Edge to RCBL Rising
ns
trcrcbr
-20
Note 5,7
trdrcs
20
ns
RSDAO & TSDA2 Valid to RBCK Edge Hold
Note 5,7
trdrch
20
ns
RCBIT, RLBIT, RUBIT, RSFO & RSF1
Setup to RFSY Edge Setup
Note 5, 8
tcsrfs
200
ns
RSDAO & TSDA2 Valid to RBCK Edge Setup
Notes:
4. There can be 16,24, or 32 TBCK cycles per sample. Typ value assumes 32 TBCK cycles per sample.
5. The "Edge" of TBCK, RBCK, TFSY & RFSY refers to the active edge of these signals which is
determined by the selected serial data format.
6. TCBIT and TLBIT are available as dedicated pins in the stand-alone configuration.
7. TSDA2 is a receive data output in receive format 5 only.
8. RUBIT will transition a bit period before RCBIT, RLBIT, RSFO, and RSF1.
RX
TFSY
I
V
U
C
P
I Y PREAMBLE
ttells
RCBL
RFSY.
TBCK
VERF--------~------------~Wl
RBCK
TSDAO/1/2,
RSDAO
TV,
TCBL*
TUBIT** "",",~""""""",,,",i=JIL..:---,---1IL--,-----'
• TCBl is sampled along with TV in Format 1,
and half as mueh in all other formats
**TUBIT sampled here in General Purpose modes only
TSDA2,
RSDAO
RUBIT
RCBIT, RLBIT,
RSFO.RSF1
Transmit Port Timing
DS93PP3
----------JIL--------~----
Receive Port Timing
6'71
.._-_
_
...-.
.-_..__
~--.-.
CS8425
SWITCHING CHARACTERISTICS
~
PARALLEL PORT
(TA = 2SoC for '-CL' suffix; TA = -40°C - 8SoC for '-IL' suffix; VD+, VA+
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF)
Parameter
= SV±10%;
Symbol
Min
tale
40
ns
Address Valid to ALE Falling Setup
tadrs
20
ns
ALE Falling to Address Hold
tadrh
20
ns
ALE Falling to RD Falling
talrd
40
ns
trd
80
ns
RD Falling to ADO-7 Driven
trdd
0
RD Falling to ADO-7 Valid
trddv
RD Rising to ADO-7 Hold
trddh
RD Rising to ADO-7 Hi-Z
trdz
ALE Falling to WR Falling
talwr
40
ns
twr
80
ns
tdwrs
80
ns
ALE High
RD Low
WRLow
ADO-7 Valid to WR Rising Setup
~
ALE
ale
al'rd
Max
Units
ns
80
ns
20
ns
ns
S
lalwr
~
I rd
RD
WR
ADO-7
I drz
1adrs ladr~
ADDREssl
I'
6-72
"I
I_ I rddv ~
r
~
~~h
DATA
Iwr
ladrs ladr~
.. ---1 ADDRESS~
U
I wrdh
Idwrs
DATA
DS93PP3
----------------------
CS8425
SWITCHING CHARACTERISTICS - SERIAL PERIPHERAL PORTS
(TA = 25°C for '-CL' suffix; TA = -40°C - 85°C for '-IL' suffix; VD+, VA+
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF)
Parameter
= 5V±10%;
Symbol
Min
Max
Units
100
kHz
SPI Mode ([2C/SPI = 1)
SCK Clock Frequency
fsck
0
CS High Time Between Transmissions
tcsh
1.0
~s
tess
20
ns
SCK Low Time
tscl
1.1
~s
SCK High Time
tsch
1.1
~s
SDI and SDO to SCK Rising Setup Time
tdsu
250
ns
tdh
50
ns
tscdv
300
CS Falling to SCK Edge
SCK Rising to DATA Hold Time
SDI (Note 9)
SCK Falling to DATA Invalid
SDO
ns
Rise Time of Both SDI and SCK Lines
tr
1
~s
Fall Time of Both SDI and SCK Lines
tf
300
ns
Notes:
9. Data must be held for sufficient time to bridge the transition time of SCK.
H
CS\
r-
'0'
SCK-'If\r\flJUVlJVlJ J1f/lJVVlfVU\fU
ADDRESS
MAP
DATA
ADDRESS
SDI ~SEVEN9~~'f--'J"'-RlW----'\---------byte 1 -
~
-byte n
SDO ----..'--_ _ _ _ _ _-----'
DS93PP3
6·73
-
-____-_
.. .......
. --_
....
CS8425
SWITCHING CHARACTERISTICS - SERIAL PERIPHERAL PORTS
(TA = 2SoC for '-CL' suffix; TA = -40°C - 8SoC for '-IL' suffix; VD+, VA+
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF)
Symbol
Parameter
12 C Mode (1 2 C/SPI
= SV±10%;
Min
Max
Units
100
kHz
= 0)
SCL Clock Frequency
fscl
0
Bus Free Time Between Transmissions
tbuf
4.7
!is
!is
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low Time
tlow
4.7
!is
Clock High Time
thigh
4.0
!is
tsust
4.7
!is
thdd
0
!is
tsud
2S0
ns
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
Note 9
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
tr
1
Fall Time of Both SDA and SCL Lines
tf
300
Setup Time for Stop Condition
Notes:
4.7
tsusp
!is
ns
!is
9. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Repealed
Start
~I
I I
SDA
SCL
I low
~
l
SDA
SCL
-" -
I I I
I
0
Ihdd
Note 1
I
sud
I
susl
~
I
r
Note 2
if
" if
if
ADDR] R/W \ACKA DATA JACKA DATA JACK
IAS-O ff
1-8 if
1-8 if
't
I I
I I
TJJUfflJVVff\J\JfflJ\J[:
Start
Stop
Note 1: The first address bit for the CS842S must be a zero.
Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP.
6-74
DS93PP3
---------------------FUNCTIONAL DESCRIPTION
Introduction
The CS8425 is a monolithic, CMOS, digital
audio data transceiver which implements the
physical layer of an Audio-Local Area Network,
A-LAN. The CS8425 can also be applied as a
general-purpose transceiver. In A-LAN applications, several CS8425s can be connected in a
ring or multi-ring topology of point-to-point
IEC-958 links. The digital audio data is transmitted and received through TTL compatible
buffers. The transmission media can be optical,
co-ax or twisted pair cable.
Audio data can be generated from anyone of
multiple nodes on the ring, and passed from
node to node. The U (user) channel is time division multiplexed into nine channels and used for
message passing of control information between
nodes. Message passing is not required of all
nodes.
The CS8425 can be set to operate as a master,
slave, slave processor, or as a stand-alone unit.
An A-LAN must have one master node to establish the network timing, and set the frame and
block structures. The remaining nodes slave their
timing to the master. A master or a slave processor can source, alter, or pass along audio data. A
slave node passes audio data unaltered, operating
as a monitor for an audio data destination such
as an amplifier. As a stand-alone unit, the
CS8425 can be set to be a master, slave or slaveprocessor, but has limited message passing
capabilities.
CS8425
determined through internal registers. There are
also stand-alone configurations in which the
CS8425 is controlled by dedicated pins.
In addition, there are two operational modes for
the CS8425 in which it functions as a generalpurpose stand-alone transceiver. In one mode,
transmit timing is independent of receive timing;
in the other mode, transmit timing is slaved to
the receive timing. Message passing is not supported in the general-purpose modes.
Ring Topology
The orientation of nodes performing different
functions on the ring should be considered in a
ring design. An important consideration in ring
topology is the functionality of the master. Since
the master generates the ring timing, its ability to
pass audio data from its receive input to transmit
output is compromised. The optimal configuration would have a master followed by slave
processors which are then followed by slave
nodes. Such a configuration would allow any of
the slave processors or the master to serve as an
audio data source, and not require the master to
pass audio data through.
For the example shown in Figure 1, the CD
player is the master. The signal processor could
AMP &
TAPE
SPEAKER
AMP &
SPEAKER
AMP &
' - - _ , - - - - - ' SIGNAL
SPEAKER
The CS8425 supports several different interface
configurations for controlling the device. There are
three peripheral configurations: Intel compatible
parallel port, 12C serial port, and SPI serial port. In
the peripheral configurations, device operation is
AMP &
SPEAKER
TELEPHONE
Figure 1 - Example of Audio LAN Topology
Supply of the CS8425 for use in a D2B application does not convey any license whatsoever; nor imply
a right under any patent.
DS93PP3
6-75
-
-----------_ ..---------
CS8425
be a digital graphic equalizer which regenerates
audio data. If the Digital Tape player becomes
the audio data source, that node could reconfigure as the master and the CD player would
become a slave. Alternatively the tape player
could slave its timing to the master. CD player,
and input its audio data on to the ring.
Figure 2 shows a block diagram of a node that
could be used as a master or a slave processor.
The example shown operates in conjunction with
a microcontroller. A slave node would have only
Digital
Audio
Digital
to
Analog
To
Next
Node
IEC-958
CS8425
A-LAN
IEC-958
From
Previous
Node
Figure 3 - PLL Filter
The recovered clock is derived from the incoming data stream by an on-chip PLL. An external
loop filter of lill and .047J.IF to ground is required as shown in Figure 3. When no signal is
applied to RX, the VCO will be pulled to its
minimum frequency.
In peripheral configurations, numerous clock dividers are available to provide a variety of
possible frequencies at the RMCK output. These
dividers are controlled by FRO and FRl of Control Register 0 as shown in Table 1. The
frequencies at RMCK and TMCK can be 128,
DGND
AGNDH_--'
O.1uF 1.0uF
Figure 2 - Block Diagram of Typical Node
the DAC functionality.
Clocks
The clock frequency for the entire ring is always
established by the master. The master's clock
source can be either the on chip crystal oscillator
or an external clock input to the TMCK pin. If a
384Fs crystal is used, RMCK and TMCK can be
connected together. In the slave or slave processor modes, the transmit clock is always derived
from the recovered clock, and TMCK is ignored.
Figure 4 - Internal Clock Routing and Divide Circuitry
6-76
DS93PP3
---------------------192, 256, or 384 times the audio sample rate.
Alternatively, the TMCK input can be connected
directly to the XTO pin. FRO and FRl affect the
clock dividers immediately after being set.
Changing dividers may cause momentary
glitches on RMCK and TX.
FROFRl
o
o
1
1
0
1
o
Frequency
384Fs
256Fs
192Fs
128Fs
Table 1 - Master Clock Settings for Peripheral
Configurations
Figure 4 shows the internal clock routing and divide structure. In stand-alone configurations, the
clock dividers are set for RMCK of 256Fs, and
TMCK is divided by two. The divide by 1.5 circuits will produce a 33% duty cycle. The
internal transmit clock must always be 128Fs
(this clock can be 33% duty cycle).
Serial Port Formats
The serial ports are for I/O of audio data. Each
port consists of a frame sync, a bit clock and
data signals. There are six serial port formats
which select the relationship of the clock, data
and frame sync signals input to and output from
the CS8425. These formats are selected by setting TFO, TFI and TF2 for the transmit side and
RFO, RFl and RF2 for the receive side. In standalone modes, the formats are selected via
dedicated pins. In the peripheral modes, the formats are selected via the Serial Port Control
register.
TRANSMIT SERIAL PORT
The six input formats are shown in Figure 5. The
frame sync input, TFSY, separates the audio data
words, and can specify left and right samples.
The selected format determines the edge on
which the bit clock, TBCK, latches data into the
DS93PP3
CS8425
part. In peripheral configurations, data may be
input through three pins, TSDAO, TSDAl, and
TSDA2. In formats 0 through 4, stereo audio
data is read through one pin, as specified by the
Source Switch Control, SSC, register. In standalone configurations, data is always read through
TSDAO. In format 5, 16 bit stereo data is read
through one pin, and 16 bit mono data is read
through TSDA1. These three 16 bit channels are
multiplexed into the two 24 bit channels of the
SPDIF as shown in Figure 6.
The number of TBCKs between TFSY edges can
be 16, 24, or 32. The device counts these clock
cycles and configures itself accordingly. Any time
the number of clocks changes between samples, an
incorrect audio sample may be transmitted, but
the chip will adapt to the new clock count.
Eighteen or twenty bit data can be input in Formats 0, 1, and 2, using either 24 or 32 TBCKs
(24 bits of audio data are input in the 24 and 32
TBCK modes). The trailing bits should be input
as zeros.
A frame of audio data is input to a shift register as
shown in Figure 7. An internally generated "latch"
signal transfers the audio data to a temporary register. Then an internal "load" signal loads the data
into another shift register from which data is
clocked to the biphase encoder and transmitted.
Load (determined by internal transmit timing) and
latch (determined by TFSY) must not be coincident. Timing is shown in Figure 8.
The validity bit can be entered on a per sample basis
through pin Tv. TV is sampled after either edge of
TFSY in all formats except format 1 where it is
sampled after the rising edge only. In all formats
except format 2, TV is sampled 1;2 TBCK samples
after the edge of TFSY. In fonnat 2, TV is sampled
11;2 TBCK samples after the TFSY edge. TV for a
channel is sampled along with the audio data being input through the serial port at the same time.
6-77
-
---------------------TF
211/0
FORMATO:
000
CS8425
I
TBCK 1LfLfUL· •. IL; .•. n.nJL .•. IL; .•. IL
TFSY
~
1MSB 1
TSDA
FORMAT 1:
001
I· .... @Bl
1LfLfUL' •.
1MSB 1
TSDA
'010
..
TFSY
I
TBCK
~ ....
011
TFSY
~S
1MSB 1
~
I· .. TlSB]
.•. n.nJL .•.
1MSB 1
%
1
Left
TSDA _ _~[MSBJ~M=SB~'"
FORMAT 3:
Right
1
[MSB]
TFSY ~ ...... ·L~ft.·.· . . . ~.·.·.· .Rig~i.· . . . . . ~
TBCK
FORMAT 2:
Left
~
I·' .
~
.•. JL
[MSBJ
%
~I_ __
Right
:.Jl ~ ~~ .... :.Jl ~
~~
%L.:L=S=-B-'----_ _-----1.[MSBJ""M=SB:.L·· . . %L.:L=S=-B-'----_ _~[MSB]-"'M=:SB::..J
I
·····I.·.·.···JL
Right
Left
~
TSDA c.:[LSBJ=SB::....L_ _-.L[MSBJ.ccM-=cSB::..J.·.· ...... [LSBJ
L_S_B-'-_ _ _-![MSBJ_M_S-'B .
k--18Bits
FORMAT 4:
1 00 TFSY
_~
---I
1
Left
TBCK ~... '
k--18Bits---l
·:F.·.·.·.·.·.'JL.· ·.·.·.·.I.·.·.·.·.·.JL
TSDA c.:[LSBJ=S=-B-'----_ _. .l[MSBJ..::.M::::SB::.J ......... %c.:L=S-=-B...L.._ _ _...JIMsBl-"M=S.=-JB
k - - 1 6 Bits
101
FORMATS:
TFSY
~
TBCK
~. . .
---I
[LSBJ
........ ~
k - - 16 Bits
1
Left
---I
I
Right
·.·.···.~.·.····I.·.·.·.JL
SB- ' . · . . .
TSDAO L.@Bl_S_B-'----_ _--c[MSBJ_M-=c
TSDA1
I
Right
k--16Bits
@BlLL_S_B~_ _ _...JIMsBl-"M=S.=-JB _.
. . ..
~
[MSBJ ...... ~
---I
k--16Bits
---I
Figure 5 - Input Formats for Transmit Data
Mono
! PRE! LSB
Left
BIT? !LSB
Mono
MSB
!VUCP! PRE! BITS
Right
MSB ! LSB
MSB!VUCP!
Figure 6 - Data Channel Configuration for Three Channel Operation
6-78
DS93PP3
----------------------
CS8425
TSDA
TBCK
samples). Once block timing is established,
TCBL can remain in either logic state.
RECEIVE SERIAL PORT
LATCH
LOAD
CLOCK
Figure 7 - Transmit Input Registers
The channel status block timing can be altered
without affecting the frame and subframe timing. TCBL is sampled, along with TV, just after
the rising edge of TFSY in all formats (falling
edge in format 2). Input format 1 does not specify which channel is left or right. The first
channel input after a low to high transition
of TCBL is the left channel. In format 1, the
CS8425 will not exit reset until a change on
TCBL is detected. Block timing is established by
a low to high transition of TCBL (on successive
TFSY
The receive serial port consists of a frame sync,
RFSY, a bit clock, RBCK, and data outputs. The
desired format is selected by setting RFO, RFl,
and RF2. In stand-alone configurations the
RFO/1I2 are dedicated pins; in the peripheral
mode, RFOIlI2 are control register bits. The relationships between RFSY, RBCK and output data
are shown in Figure 9. Formats 0 - 4 are stereo
formats with stereo data output on pin RSDAO.
Format 5 is a three channel format with stereo
data output on pin RSDAO, and mono data output on pin TSDA2. All 24 bits of audio data are
output in formats 0, 1, and 2.
The receive port has 24 bit shift registers for reversing the order of the received audio data.
Consequently, there is one subframe of delay
_J
TSDA
I MSB
Left 1
I MSB
Right 1
I MSB
Left 2
I MSB
Right 2
I
TV:t
t
t
t
t
Sampled
TCBL -------+'------------~~+=~--==~----~----------~~~--------------{L-_-_-_-_-_Sampled
:
(Format 1) -------
. ======i
=3'
~TCH
.
-------------------------------------~-
LOAD
TX
Right 191
I PRE I
Right 0
Left 0
IPREI
- - - - - -
Format2 _
TFSY
...____________________________________________________~ ___
~ ____________________________________________ ,
TS~;rmal 0
I
TV
:
MSB
Left 1
I MSB
t
! ___ _
Right 1
t
t
H
C
T
~
n
LOAD
TX
FSY
Window
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Sampled
:
TCBL ____"~---------------------------------------~~~rm~at~1~o~nILY-----.----~...- - - - - - - - Sampled
:
_ _ _ _ _ _ _ __ _
----~---------------------------------------------------!lL---
C I P I Preamble
Right 191
Device will auto-reset internal timin
Figure 8 - Detailed Transmitter Timing Information
DS93PP3
6-79
-
---------------------RF
FORMAT 0: ~~~
C58425
II+-'- - - 32 Clocks
"I'
RFSY - - . J r - - - - - L - e f t - - - - - : I
RBCK
1lIlILJL;-
001
RFSY
~_ ~- ~_
1--16 Clocks ---.j...-16 Clocks
Left
1
RBCK I
n
LJ
n
LJ
,-' ,-' n
L..
'_"
'_ -'
I
fL- ~_ JL
--.j
I
i-I---R-ig-h-t'I
,-' n
L..
"I
1_- _- .[LSBJ
1 MSBI
~
n
RSDAO
fL-
-,-,-IM=S=-BLI_-'----..--JI _- _- _@Bl
RSDAO
FORMAT 1:
~_
32 Clocks
Right
'_ -'
n
LJ
,-" ,- - n
L..
'_"
'_ -'
,-" n
L..
1+-1'- - - 3 2 Clocks ------1"""1'--- 32 Clocks
FORMAT 2:
125
010
FORMAT 3:
011
I'---___-=:Le""ft'----_ _ _--'I
RBCK
--uL.["L-_-_-_JL: :~-_-_-_JL:
Right
LI_ __
:,~
_ _~[MSED_M_SB~ _- _- _- _- c..:[lSB]:::S=-B.L..-_ _----L[MSED.:..cM=cSB=..J _- _- _- _- L-'[lS8]""S=B-'---_ _---'[MSBJ.-'-'M""S::.JB
II+-,- - - 32 Clocks
"I'
RFSY - - . J ' - - - - - L e - f t - - - - - : I
RBCK
J1S:"-_ -_
-_S~
-_ -_ -_ -_ -_
-~-
32 Clocks
Right
______ __
S~
"I
I
-_ -_ -_ -_
-_-~
RSDAO [lSB]c..:L:.=S=B-'---_ _---L.:[MSBl:::S:::B:..J. -_ -_ -_ -_ -_ -.t..:[LSB]=::S:::B--'---_ _----'-[MSa].:::M::::SB=-.i -_ -_ -_ -_ -_
1---18
100
I
RFSY ---.J
RBCK
n
--1
'--
1---18
Bits -------..!
- - - 2 4 Clocks
110-'
FORMAT 4:
L
"I
RFSY
RSDAO
'_ J
---'-'.:1M,-=-S=:.JB1,---,1 _____- _- _- _TLsBlc..::L=sB::...L._L.::1M=s=BLI----,I ___________TLsBlc..:L=SB=-.L.-----.J[MSa]c.:.:M=SB::..J
----I
Left
,-----,---,
n
_..---J
__ ..---J _____
~
~
Bits-------..!
~24 Clocks
1
1
L- __
-[LSB]
----I
I
Right
,-----,---,
n
..---J
__
_____
~
~
~
L
B -_ -_- ~
RSDAO L..:[lSB]::.::S.::.B-L-_ _ _ _--'[MSBl. :;.M:. =B
S:: : . J. -_-_ -L[lSB]=-:S""B-L-_ _ _ _ _-+[MSa]..::.M:.::.S::...L
1---16 Bits
- - - 2 4 Clocks
10-1'
FORMAT 5:
101
-----.J
1---16 Bits
----I
RFSY
~
RBCK
JL_I::I:::~
Left
~24 Clocks
1
1
----I
[LSBJ
1---16 Bits
__ ~::I:::~
-----.J
Figure 9 • Receive Serial Port Data Fonnats
6·80
I
Right
RSDAO L.[LSB]_S_B-L-_ _ _ _7'[MSB]""S'-'-B-'.-_ -_-L[lSB]_S_B-+-_ _ _ _ _-'-[MSB]-"M:..=;S=c.L
B -_ -_
TSDA2
-----.J
-~
[MSB] -_-_-
~
I--- 16 Bits -----.J
DS93PP3
.-_
._.-.
_
..--__.._-_
...
CS8425
through the receive serial port. In all formats,
RFSY changes one bit period after the start of a
preamble on RX ..
In slave mode, received audio data is always retransmitted. The transmitted data signal is
delayed 2.5 biphase bit periods relative to the received audio data as shown in Figure 10.
A slave processor node can retransmit audio data
if the received audio data is sent back to the
transmit port. The timing for a slave processor
with the receive serial port driving the transmit
serial port is shown in Figure 11. The frame and
block structure of the IEC-958 data is delayed
2.5 biphase bit periods and the audio data is delayed an additional two frames. The bit clock
and frame sync can be internally looped back by
RX
Left 1
Right 1
[PRE [
setting the Source Switch Control register appropriately.
In some cases, it may be required to pass data
through a master. This can be done by first establishing ring timing, then switching the
transmit serial port inputs from external signals
to the receive serial port outputs. One audio
sample may be corrupted when the switch is
made. Configuring a master to pass through received data is risky and generally not
recommended. The ring clock source is no
longer controlled, and should ring timing be interrupted for any reason, the ring will not resync
without reconfiguration of the master.
The RCBL output identifies block boundaries of
the received data. RCBL transitions high three
RBCK cycles before the RFSY edge that identiLeft 2
[PRE [
Right 2
[PRE [
[PRE [
RFSY
:[
Format 0 ~L_ _ _ _ _---c-'
RSDAO
TX SLAVE
:
I
:
Right 0
: IPRE I
Left 1
~
Left 1
[
Right 1
Right 1
: [PRE [
- - - - -
-
- - - - - - -
Left 2
[PRE [
-
-
r==
Left 2
[PRE [
Right 2
- - - - - - - - - - - - - - - - - - - - - -
Left 1
[PRE [
--
[V[U[C[p!
RFSY-:l~__________________________________~__________~~
RSDAO
C
Right 0
: [
TXSLAVE[U[c[PHa~bl~
Left 1
[v[u[C[p[
Figure 10 • Slave Mode Receive to Transmit Timing
RX
[ ~R~[
Left 1
[ PRE[
Right 1
[ PRE[
Left 2
[ PRE[
Right 2
RFSY=TFSY~
~
Format 0
RSDAO=TSDAO
TX
i
[ PRE[
Right 0
:[ PRE[
Left 191
Left 1
[ PRE[
Right 1
Right 191
[ PRE[
Left 2
Left 0
[ PRE[
I
Right 0
[ PRE[
Figure 11 • Slave Processor Timing with Receive Serial Port Driving Transmit Serial Port
DS93PP3
6·81
-
_.-_..--_._.
__.._-_
...-.
fies the first audio sample of a block. RCBL remains high for 32 frames, and is then low for
160 frames. RCBL remains low when the receiver is not locked.
CS8425
essors: parallel interface, 12C and SPI. Figure 12
shows a block diagram and the different peripheral interfaces.
PARALLEL INTERFACE
The pin VERF can output the received validity
bit and identify etrored audio samples. In standalone configurations, VERF is high if the
receiver is not in lock, a parity or line coding
error is detected, or the received validity bit is
high. In peripheral configurations, the Status
Register EnablelMask register determines which
conditions affect VERF. Transitions on VERF
occur coincident with the edges of RFSY that
identify the start of the errored audio sample.
When the device is in the master or slave processor modes and it is. configured to retransmit
received audio data, VERF can be connected to
TV to properly retransmit the validity bit.
Device Configurations
The CS8425 can be set to interface as a peripheral, operate as a stand-alone unit, or function as
a general-purpose transceiver. The configuration
is set by the mode pins, Ml and M2 as shown in
Table 2.
Ml M2
o
o
1
1
float
float
0
1
0
1
0
1
Mode Configurations
Peripheral - Parallel Port
1
2
Peripheral - 12C/SPI Bus
3
Stand-alone - Master
Stand-alone - SlavelSlave Pro
4
General-Purpose 0, GPO
5
6
General-Purpose 1, GPI
Table 2 - Operating Modes
Selecting mode 1 (pins M11M2 =010) configures
the part for parallel interface. The parallel port
consists of an eight bit multiplexed address/data
bus, ADO-AD7, an address latch enable, ALE, a
read signal, RD, and a write signal, WR. An address present on ADO - AD7 will be latched into
the part on the falling edge of ALE. The addressed register is read by setting RD low. The
bus will be tristated shortly after RD goes high.
A register is written by setting WR low.
SERIAL INTERFACES
Mode 2 (pins M11M2 = 011) configures the part
for serial interface. Either 12C or SPI interface is
selected by the I 2C/SPI pin. When transmitting
data to the transceiver in either serial interface
format, the first byte after the slave address is
written to the memory address pointer, MAP.
Successive bytes are written to the address in
MAP. If CR1.3, INC, is set, the MAP will automatically increment after each memory access,
thus allowing blocks of data to be efficiently accessed. If a read operation is specified,
successive bytes are read from the address in
MAP. Unless the proper address resides in MAP,
a write operation must precede a read.
Pc Interface
The 12C interface is selected by setting the
FC/SPI pin low. This interface consists of a se-
Peripheral Configurations
As a peripheral, internal buffer memory allows
the device to send and receive messages, and 16
control and status registers allow flexible management of the device and the network. Modes 1
and 2 allow selection of three different CS8425
configurations for interface with peripheral proc6-82
rial clock, SCL, serial data, SDA, and five node
address pins, lAO - 1A3, IA5. IA4 is set to zero,
and the MSB of the address is internally set to
zero. The CS8425 is configured as a slave, and
has· an eight bit memory address pointer, MAP,
which must be loaded prior to memory access.
DS93PP3
---------------------FlT
XTO
XTI
RMCK
I
I
I
Ii
Clock Manager
Clock
RX >-- Data H
Recovery
AGND
RESET
DGND
TMCK
I
"I-----"-U
ST
1 4- -4- - - t TD ---4I·1
Timing Diagram-Strobe Input
-:-::------------------'~~----------Timing Diagram-Power Down
RST
~~--tRPu-k---.I
V OH
RST
----------------------------------~
VOL
Timing Diagram-Power Up
7-6
DS18F1
---------------_
-.r _ _ _ __
CS1232
POWER SUPPLY MONITOR
WATCHDOG TIMER
The CS 1232 will detect out-of-tolerance power
supplies for processor-based systems as well as
warn of an impending power failure. The TOL
digital input pin defines the threshold level for
Vee; when the Vee level drops below the TOL
defined level, the CS 1232 asserts the signals
RST and RST. The threshold level is set to typically 4.37 V if TOL is connected to Vee, and is
set to typically 4.62 V if TOL is connected to
GND. The processor is allowed to continue until
the last possible moment that Vee is valid. Upon
return of power, RST and RST are active for 250
ms (minimum) to allow stabilization.
When RST and RST become inactive (normal
CPU operation), the watchdog timer starts timing
out, using the time set by TD. RST and RST are
forced active when ST is not stimulated for this
predetermined time. TD sets the time to be: 150
ms if TD is connected to ground, 600 ms is TD
is not connected, or 1.2 seconds with TD connected to Vee. RST and RST are driven active
for 250 ms (minimum) if no high-ta-Iow transition occurs on the ST input pin before time out.
Microprocessor address signals, data signals,
control signals, and output port bits can be used
for the ST input pin. These signals cause the
watchdog timer to be reset prior to time out indicating normal function of the microprocessor
(see Figure 2).
PUSHBUTTON RESET CONTROL
PBRST is normally connected to a reset pushbutton (see Figure 1). This active low signal is
debounced and timed to generate signals of
250 ms (minimum) for RST and RST. The delay
begins when PBRST is released from from the
low state. PBRST has an internal 100 kn pull-up
resistor.
+SVDC
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your
III
For Our Free Review Service
Call Applications Engineering.
+SVDC
ALE
MREQ
RST
--
8051
uP
Figure 1. Pushbutton Reset
DS18F1
Decoder
Z80
RST
Address Bus
Figure 2. Watchdog Timer
7-7
---------------------PUSH BUTTON RESET INPUT PBRST
TIME DELAY SET
TO
SELECTS Vee DETECT LEVEL
TOl
GROUND
GNO
NO CONNECTION
NC
PUSH BUTTON RESET INPUT PBRST
NO CONNECT
TIME DELAY SET
NO CONNECT
SELECTS Vee DETECT LEVEL
NO CONNECT
GROUND
7-8
CS1232
0
8
2
3
4
7
6
5
Vee
ST
RST
RST
+5 VOLT POWER
STROBE INPUT
RESET OUTPUT (Active Low, Open Drain)
RESET OUTPUT (Active High)
NC NO CONNECT
Vee +5 VOLT POWER
NC NO CONNECTION
ST
STROBE INPUT
NC NO CONNECT
RST RESET OUTPUT (Active Low, Open Drain)
NC NO CONNECT
RST RESET OUTPUT (Active High)
OS18F1
----------------------
CS1232
DIE INFORMATION
Crystal Semiconductor Procedure 42AA00007
outlines the General Requirements for Die Sales.
The document includes information on wafer
fabrication, manufacturing flow, screening/inspection procedures, packing, shipping, and
change notification.
Assembly Information
6. The CSI232-YU requires no particular bonding sequence.
1. Die size: 0.061" by 0.069" (± 0.002").
2. The die is suited for die attach through either
eutectic or adhesive means. When eutectic die attach is used, Crystal Semiconductor recommends
either a 99.9% Au or 98% Aul2% Si preform of
the appropriate size. The backside of the die
should be electrically connected to Vcc.
3. Die thickness shall be 0.0175" ±0.0035". If
tighter tolerances are required, contact the factory.
7. Each pin of the CS1232 has ESD and latch-up
protection circuitry.
8. Technical constraints limit the viability of accurate performance measurements of precision
analog IC's at wafer probe. Although high yield
to the limits listed in the specification tables is
anticipated, no guarantee is given for unpackaged die product.
4. The maximum number of die per waffle pack
carrier is 100.
5. The cavity dimensions for each die within the
waffle pack are 0.080" by 0.080" (Waffle Pack
Type H20-080).
CS1232-YU Bonding Diagram
8.
7 •
• 1
• 2
6 •
• 3
• 4 •••••
1 - PBRST
2 - TD
3 - TOL
4 - GND
DS18F1
5 •
5 - RST
6 - RST
7 - ST
8 - VCC
7-9
----------------------
CS1232
eNotese
7·10
DS18F1
...-.. ......
..........
..
."
~~
~~
CS331 0
~
Semiconductor Corporation
Stereo Digital Volume Control
General Description
Features
The CS3310 is a complete stereo digital volume control
designed specifically for audio systems. It features a
16-bit serial interface that controls two independent, low
distortion audio channels.
• Complete Digital Volume Control
2 Independent Channels
Serial Control
0.5 dB Step Size
The CS3310 includes an array of well-matched resistors
and a low noise active output stage that is capable of
driving a 600 Q load. A total adjustable range of 127 dB,
in 0.5 dB steps, is achieved through 95.5 dB of attenuation and 31.5 dB of gain.
• Wide Adjustable Range
-95.5 dB Attenuation
+31.5 dB Gain
The simple 3-wire interface provides daisy-chaining of
multiple CS3310's for multi-channel audio systems.
• Low Distortion & Noise
0.001 % THD+N
116 dB Dynamic Range
The device operates from ±5V supplies and has an input/output voltage range of ±3.75V.
• Noise Free Level Transitions
ORDERING INFORMATION:
Model
Temp. Range
CS3310-KP
0° to 70° C
CS3310-KS
0° to 70° C
• Channel-to-Channel Crosstalk
Better Than 110 dB
AINL 01",,6--.------i
Package Type
16-pin plastic DIP
16-pin plastic SOIC
-
14
AOUTL
8
-MUTE
ZCEN
2
AGNDL o-1"'S--<>--_ _- l
10
3
AGNDR
7
Serial to
Parallel
6
cs
SDATAI
SDATAO
SCLK
Register
11
AOUTR
AINR 0-=9-0-----1
12
VA+
Preliminary Product Information
VA·
VD+
DGND
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993·
(All Rights Reserved)
NOV '93
DS82PP2
7-11
-_ _-_
.. ...-.
-. ..---.,-.
__
CS331 0
ANALOG CHARACTERISTICS
(TA = 25 °C, VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; RL = 2kf.!; CL '" 20 pF;
10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Units
0.5
10
-
dB
CIN
-
THD+N
-
0.001
.0025
%
DC Characteristics
Step Size
Gain Error (31.5 dB Gain)
Gain Matching Between Channels
RIN
Input Resistance
Input Capacitance
±0.05
±0.05
10
dB
dB
kf.!
pF
AC Characteristics
Total Harmonic Distortion plus Noise
(Vin = 2V rms, 1 kHz)
Dynamic Range
InpuVOutput Voltage Range
Output Noise
(Note 1)
Digital Feedthrough (Peak Component)
Interchannel Isolation
(1kHz)
110
116
-
dB
(VA-)+1.25
-
(VA+)-1.25
V
-
4.2
8.4
IlVrms
-80
-
dB
-100
-110
-
-
0.25
0.75
mV
-
-
100
pF
dB
Output Buffer
Offset Voltage
(Note 1)
VOS
Load Capacitance
Short Circuit Current
Unity Gain Bandwidth, Small Signal
(Note 2)
-
20
2
-
-
MHz
-
5.0
8.0
mA
5.0
8.0
rnA
350
800
IlA
52.0
84.0
mW
80
-
dB
mA
Power Supplies
Supply Current (No Load, AIN = OV)
IA+
IAID+
Power Consumption
Power Supply Rejection Ratio (250 Hz)
PD
PSRR
-
-
-
NOTE: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings> 1.
2. This parameter is guaranteed by design and/or characterization.
7-12
DS82PP2
----------------------
CS3310
DIGITAL CHARACTERISTICS
(TA
= 25 DC, VA+ , VD+ = 5V ± 5%, VA- = -5V ± 5% )
Parameter
Symbol
Min
Typ
Max
Units
VIH
2.0
VD+0.3
V
+0.8
V
-
V
-
-
0.4
V
1.0
10
JiA
Symbol
Min
Typ
Max
Units
SCLK
0
4.2
MHz
Pulse Width High
tph
80
tpl
80
Pulse Width Low
-
2.0
-
ns
Pulse Width Low
-
SDATAI Set Up Time
tSDVS
20
-
SDATAI Hold Time
tSDH
20
tCSVS
30
tLTH
35
-
-
CS Low to Output Active
tCSH
SCLK Falling to Data Valid
tSSD
-
-
High-Level Input Voltage
VIL
-0.3
High-Level Output Voltage
(10 = 200jlA)
VOH
VD-1.0
Low-Level Output Voltage
(10 = 3.2mA)
VOL
Low-Level Input Voltage
Input Leakage Current
lin
SWITCHING CHARACTERISTICS
(TA
= 25 DC; VA+,
VD+
= +5V ± 5%; VA- = -5V ± 5%; CL = 20 pF)
Parameter
Serial Clock
Serial Clock
MUTE
ns
ms
Input Timing
CS Valid to SCLK Rising
SCLK Falling to CS High
ns
ns
ns
ns
Output Timing
CS High to SDATAO Inactive
CS
tCSDH
----1 _______________________~~
~
~tCSVS
SCLK
H
...l...l..U..L.;--1---'
1
1
1
----+I---/.
-J
~
~tSDH -I
1
SDATAO
n
tSDVS
1
//IIIlIJ//(
MSB
L -_ _ _ _ _ _
- - tCSH
ns
60
ns
100
ns
r----------
~
~
~ 1+4 tLTH
1
~
SDATAI
35
~
VrTi-TO//TrrO/TTTiO/rrn/
///TTTll
1
~
q~Ur+rr~llTTT7/
///TTTiO/rrTT// / /TTTTO/
1
~
~tCSDH
X~--+:--~I
~
~
~I
tSSD
I
Figure 1. Serial Port Timing Diagram
DS82PP2
7-13
.._-_.-_..--_._.
_...-.
CS331 0
RECOMMENDED OPERATING CONDITIONS
(DGND = OV; all voltages with respect to ground)
Parameter
Symbol
Min
Typ
Positive Digital
VD+
4.75
Positive Analog
VA+
4.75
Negative Analog
VA-
-4.75
TA
0
Max
Units
5.0
VA+
V
5.0
V
-5.0
5.25
-5.25
25
70
°C
DC Power Supplies:
Ambient Operating Temperature:
ABSOLUTE MAXIMUM RATINGS (AGND,
DGND
V
=OV, all voltages with respect to ground.)
Symbol
Min
Max
Units
Positive Digital
VD+
-0.3
(VA+)+ 0.3
V
Positive Analog
VA+
-0.3
6.0
V
Negative Analog
VA-
0.3
-6.0
V
lin
-
±10
mA
VIND
-0.3
(VA+) + 0.3
V
TA
-55
+125
°C
TSTG
-65
+150
°C
Parameter
DC Power Supplies:
Input Current, Any Pin Except Supply
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
10.a
+SVANALOG
ZCEN
VD+
0.11!F
2
-
13
-SVANALOG
VA-
CS
SDATAI
CONTROLLER
SCLK
CS331 0
MUTE
AINL
AOUTL
AUDIO
SOURCE
14
11
AUDIO OUTPUTS
AOUTR
AINR
DGND
TO ANOTHER CS3310
OR CONTROLLER
7
SDATAO
AGNDL
AGNDR
Figure 2. Recommended Connection Diagram
7-14
DS82PP2
----------------------
CS331 0
GENERAL DESCRIPTION
Serial Data Interface
The CS3310 is a stereo, digital volume control
designed for audio systems. The levels of the left
and right analog input channels are set by a 16bit serial data word; the first 8 bits address the
right channel and the remaining 8 bits address
the left channel. Resistor values are decoded to
0.5 dB resolution by an internal multiplexer for a
total attenuation range of -95.5 dB. An output
amplifier stage provides a programmable gain of
up to 31.5 dB in 0.5 dB steps. This results in an
overall 8-bit adjustable range of 127 dB.
The CS3310 has a simple, three wire interface
that consists of three input pins: SDATAI, serial
data input; SCLK, serial data clock and CS, the
chip select input. SDATAO, serial data output,
enables the user to read the current volume setting or provide daisy-chaining of multiple
CS331O's.
The CS3310 operates from ±5V suppiies and accepts inputs up to ±3.75Y. Once in operation, the
CS3310 can be brought to a muted state with the
mute pin, MUTE, or by writing all zeros to the
volume control registers. The device contains a
simple three wire serial interface which accepts
16-bit data. This interface also supports daisychaining capability.
Tne 16-bit serial data is formatted MSB first and
clocked into SDATAI by the rising edge of
SCLK with CS low as shown in Figure 3. The
data is latched by the rising edge of CS and the
analog output levels of both left and right channels are set. The existing data in the volume
control data register is clocked out SDATAO on
the falling edge of SCLK. This data can be used
to read current gain/attenuation levels or to daisy
chain multiple CS331O's. See Figure 1 for
proper setup and hold times for CS, SDATAI,
SCLK, and SDATAO. SCLK and SDATAI
should be active only during volume setting operations to achieve optimum dynamic range
SYSTEM DESIGN
Very few external components are required to
support the CS331O. Normal power supply decoupling components are all that is required, as
shown in Figure 2.
CS - - - - - - - ,
SCLK
SDATAI \ \ \ \ \ \ I R71 RsIR51 R41 R31 R21R11ROI L71 Lsi L51 L41 L31 L21 L11 Lol \ \ \ \ \ \
SDATAO
--~~ R71 R61 R51 R41 R31 R21 R11 Rol L71 L61 L51 L41 L31 L21 L11 LO ~I---LO = Left Channel Least Significant Bit
RO = Right Channel Least Significant Bit
L7 = Left Channel Most Significant Bit
R7 = Right Channel Most Significant Bit
SDATAI is latched internally on the rising edge of SCLK
SDA TAO transitions after the falling edge of SCLK
SDATAO bits reflect the data previously loaded into the CS3310
Figure 3. Serial Port Timing
DS82PP2
7-15
-
-_ _-_
..
.
.- ..--_._.
-_ ...-
CS331 0
Daisy-chaining
Digitally controlled, multi-channel audio systems
often. result in complex address decoding which
complicates PCB layout. This is greatly simplified with the daisy-chaining capability of the
CS331O.
Controller
AOUTL 1-'-1:::...4i----'--~
c:-
AOUTR 11,+---+-+
In single device operation, volume control data
is loaded into the 16-bit shift register by holding
the CS pin low for sixteen SCLK pulses and
then latched on the rising edge of CS. The previous contents of the shift-register are shifted
through the register and out SDATAO during the
process.
CS3310
AOUTL 1-'-14,,--_+
Multi-channel operation can be implemented as
shown in Figure 4 by connecting the SDATAO
of device #1 to the SDATAI pin of device #2. In
this manner multiple CS33lOs can be loaded
from a single serial data line without complex
addressing schemes. Volume control data is
loaded by holding CS low for 16 x N SCLK
pulses, where N is the number of devices in the
chain. The 16 bits clocked into device #1 on
SCLK pulses 1-16 are clocked into device #2 on
SCLK pulses 17-32. The CS33 lOs are simultaneously updated on the rising edge of CS
following 16 x N SCLK pulses.
Changing the Analog Output Level
Care has been taken to ensure that there are no
audible artifacts in the analog output signal during volume control changes. The gain/attenuation
changes of the CS3310 occur at zero crossings to
eliminate glitches during level transitions. The
zero crossing for the left channel is the voltage
potential at the AGNDL pin; the voltage potential at the AGNDR pin defines the right channel
zero crossing.
A volume control change occurs after chip select
latches the data in the volume control data register and two zero crossings are detected. If two
zero crossings are not detected within lOOms of
7-16
SDATAO
7
AOUTR 1-'-11'---_+
Figure 4. Daisy Chaining Diagram
the change
plemented.
enables or
function as
in CS, the new volume setting is imThe zero crossing enable pin, ZCEN,
disables the zero crossing detection
well as the lOOms timeout circuit.
Input Code
(Left or Right Channel)
Gain or
Attenuation (dB)
11111111
11111110
+31.5
+31.0
•
•
11000000
0
•
•
00000010
00000001
00000000
•
•
-95.0
-95.5
Software Mute
Figure 5. Input Code Definition
DS82PP2
---------------------Analog Inputs and Outputs
The maximum input level is limited by the common-mode voltage capabilities of the internal
op-amp. Signals approaching the analog supply
voltages may be applied to the AIN pins if the
internal attenuator limits the output signal to
within 1.25 volts of the analog supply rails.
The outputs are capable of driving 600 ohm
loads to within 1.25 volts of the analog supply
rails and are short circuit protected to 20 rnA.
As with any adjustable gain stage the affects of a
DC offset at the input must be considered. Capacitively coupling the analog inputs may be
required to prevent "clicks and pops" which occur with gain changes if an appreciable offset is
present.
Mute
Muting can be achieved by either hardware or
software control. Hardware muting is accomplished via the MUTE input and software muting
by loading all zeroes into the volume control
register.
MUTE disconnects the internal buffer amplifiers
from the output pins and terminates AOUTL and
AOUTR with 10ka resistors to ground. The
mute is activated with a zero crossing detection
or a lOOms timeout to eliminate any audible
"clicks" or "pops". MUTE also initiates an internal offset calibration.
A software mute is implemented by loading all
zeroes into the volume control register. The internal amplifier is set to unity gain with the
amplifier input connected to the maximum attenuation point of the resistive divider, AGND.
A "soft mute" can be accomplished by sequentially ramping down from the current volume
DS82PP2
CS331 0
control setting to the maximum attenuation code
of all zeroes.
Power-Up Considerations
Upon initial application of power, the MUTE pin
of the CS3310 should be set low to initiate a
power-up sequence. This sequence sets the serial
shift register and the volume control register to
zero and performs an offset calibration. The device should remain muted until the supply
voltages have settled to ensure an accurate calibration.
The offset calibration minimizes internally generated offsets and ignores offsets applied to the
AIN pins. External clocks are not required for
calibration.
Although the device is tolerant to power supply
variation, the device will enter a hardware mute
state if the power supply voltage drops below
approximately ±3.5 volts. A power-up sequence
will be initiated if the power supply voltage returns to greater than ±3.5 volts.
Grounding and Power Supply Decoupling
As with any high performance device which
contains both analog and digital circuitry, careful
attention to power supply and grounding arrangements must be observed to optimize
performance. Figure 2 shows the recommended
power arrangements with VA+ connected to a
clean +5 volt supply and VA- connected to a
clean -5 volt supply. VD+ powers the digital interface circuitry and should be powered from
VA+ as shown to minimize latch-up possibilities.
Decoupling capacitors should be located as near
to the CS3310 as possible, see Figure 6.
The printed circuit board layout should have
separate analog and digital regions with individual ground planes. The CS3310 should straddle
the ground plane break with pins 1-8 residing in
7-17
-
.._-_
_.-_..--_._.
__
...-.
CS3310
1i
? 1/8"
Analog
Ground
Plane
Digital
Ground
Plane
~I
CPU & Digital
Logic
Analog Signals
and Circuits
Figure 6. Recommended 2-Layer PCB Layout
the digital region and pins 9-16 residing in the
analog region as shown in Figure 6. Care
should be taken to ensure that there is minimal
resistance in the analog ground leads to the device to prevent any change in the defined
attenuation settings. Extensive use of ground
plane fill on both the analog and digital sections
7-18
of the circuit bbard will yield large reductions in
radiated noise effects. An applications note
"Layout and Design Rules for Data Converters"
is printed in the Application section of the Crystal data book and contains many guidelines for
the optimum layout of mixed signal devices.
DS82PP2
----------------------
CS331 0
AMPL (dBr) vs FREQ (Hz)
THD+N% vs AMPL (Vrms)
1.0
Ap
Ap
0.5
1
0.0
"'\
-0.5
.0 1
-1.0
.001r-....
-1.5
-2.0 10
100
1k
10k
100k 200
.-
.000 1
0.1
Figure 9. THD+N vs AMP
Figure 7. Frequency Response
Full scale Input
Figure 7 displays the CS3310 frequency response with a 3.75 Vp output.
Figure 8 shows the frequency response with a
.375 Vp output.
AMPL (dBr) vs FREQ (Hz)
1.0
--
The lower trace is the THD+N of the Audio Precision System One generator output connected
directly to the analyzer input. The System One
panel settings are identical to the previous test.
This indicates that the THD+N contribution of
the Audio Precision actually degrades the measured performance of the CS3310 below 2.7 Vrms
signal levels.
Ap
AMPL (dBr) vs FREQ (Hz)
0.5
Ap
-20
0.0
"""
-0.5
-40
-60
-80
-1.0
-100
-1.5
-2.0
-120
-140
10
100
1k
10k
lOOk 200k
I
I
\...
-160
Figure 8. Frequency Response
·20 dB Input
Figure 9 is the Total Harmonic Distortion +
Noise vs amplitude at 1 kHz. The upper trace is
the THD+N vs amplitude of the CS331O.
DS82PP2
-180
20.00 2.08k 4.11k6.15k 8.19k 10.2k 12.3k 14.3k 16.4k 18.4k 20.5k 22.5
Figure 10. 20 kHz Crosstalk
Figure 10 is a 16k FFT plot demonstrating the
crosstalk performance of the CS3310 at 20 kHz.
Both channels were set to unity gain. The right
channel input is grounded with the left channel
driven to 2.65 Vrms output at 20 kHz. The FFT
plot is of the right channel output. This indicates
channel to channel crosstalk of -130 dB at 20
kHz.
7-19
-
.._-_
.-_
_
..--_._.
__
...-.
CS331 0
0.1000
Ap
0.0100
600n=
/
0.001 0
0.000 1
20
100
Ap
0.0100
""'+
1"-
....,"" ~
lk
0.1000
10k
20k
2.8VRMS
0.001 0
2VRMS
~
1 VRM
0.000 1
20
II
100
lk
10k
20k
Figure 11. THD+N vs. Frequency
LOAD = 600 ohm, 2 kohm, open ckt
Figure 12. THD+N vs. Frequency
Output levels of 1, 2 and 2.8 Vrms
Figure 11 is a series of plots which display the
unity-gain THD+N vs Frequency for 600 ohm,
2 kohm and infinite load conditions. The output
was set to 2 Vrms. The Audio Precision System
One was bandlimited to 22 kHz.
Figure 12 is a series of plots which display the
unity-gain THD+N vs Frequency for 1, 2 and
2.8 Vrms output levels. The output load was
open circuit. The Audio Precision System One
was bandlimited to 22 kHz.
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your
For Our Free Review Service
Call Applications Engineering.
7-20
DS82PP2
----------------------
CS331 0
PIN DESCRIPTIONS
Zero Crossing Enable
ZCEN
Chip Select
CS
AINL
Left Channel Input
AGNDL
Left Analog Ground
Serial Data Input
SDATAI
AOUTL
Left Channel Output
Positive Digital Power
VD+
VA-
Negative Analog Power
Digital Ground
DGND
VA+
Positive Analog Power
Serial Clock Input
SCLK
AOUTR
Right Channel Output
Serial Data Output SDATAO
AGNDR
Right Analog Ground
AINR
Right Channel Input
Mute
MUTE
Power Supply Connections
VA+ - Positive Analog Power, Pin 12.
Positive analog supply. Nominally +5 volts.
VA- - Negative Analog Power, Pin 13.
Negative analog supply. Nominally -5 volts.
AGNDL - Left Channel Analog Ground, Pin 15.
Analog ground reference for the left channel.
AGNDR - Right Channel Analog Ground, Pin 10.
Analog ground reference for the right channel.
VD+ - Positive Digital Power, Pin 4.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, Pin 5.
Digital ground for the digital section.
Analog Inputs and Outputs
AINL, AINR - Left and Right Chaunel Analog Inputs, Pins 16, 9.
Analog input connections for the left and right channels. Nominally ±3.75 volts for a full scale
input.
AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11.
Analog outputs for the left and right channels. Nominally ±3.75 volts for a full scale output.
DS82PP2
7-21
___-_
.. ...
._.-.
-..-_
..---
CS331 0
Digital Pins
SDATAI - Serial Data Input, Pin 3.
Serial input data that sets the analog output level of the left and right channels. The data is
formatted in a 16-bit word. The first eight bits clocked into this pin control the analog output
level for the right channel, and the second eight bits clocked into the device control the analog
output level for the left channel. The data is clocked into the CS3310 by the rising edge of
SCLK.
'
SDATAO - Serial Data Output, Pin 7.
Serial output data that provides daisy-chaining of multiple CS331O's. This serial output will
output the previous sixteen bits of volume control data that were clocked into the SDATAI pin.
SCLK - Serial Input Clock, Pin 6.
Serial clock that clocks in the individual bits of serial data from the SDATAI pin. This clock is
also used to clock out the individual bits from the SDATAO pin. The SDATAI data is latched
on the rising edge, and SDATAO data is clocked out on the falling edge.
CS - Chip Select, Pin 2.
When high, the SDATAO output is held in a high impedance state. A falling transition defines
the start of the 16-bit volume control word into the device. The 16-bit input data is latched into
the control register on the rising edge of CS.
MUTE - Mute, Pin 8.
Forces both the left and right analog output channels to ground. An offset calibration is
initiated following the low transition of MUTE. Calibration requires a minimum mute period
of2ms.
ZCEN - Zero Crossing Enable, Pin 1.
This pin enables or disables the zero crossing detection and timeout function used during
analog output level transitions. A high level on this pin enables the zero crossing detection
function. A low level on this pin disables the zero crossing detection.
7-22
DS82PP2
----------------------
CS331 0
PARAMETER DEFINITIONS
Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth with the input grounded. Units in decibels.
Total Harmonic Distortion plus Noise - The ratio of the rms value of the signal to the rms sum of all
other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels.
DS82PP2
7-23
.
......,..........
......
.
.....,
."
CDB3310
."."
Semiconductor Corporation
Evaluation Board for CS331 0
Features
General Description
• Demonstrates recommended layout
and grounding arrangements
The CDB3310 evaluation board allows fast evaluation
of the CS3310 stereo digital volume control. The board
generates all control signals. Evaluation requires a lowdistortion signal source and a power supply.
• On-board or externally supplied system
control
The evaluation board may be configured to accept external timing signals for operation in a user application
during system development. The CDB3310 also provides a PC compatible control port for user software
development.
• Buffered PC Control Interface
Analog inputs and outputs are standard RCA phono
plugs.
• Digital and Analog Patch Areas
ORDERING INFORMATION:
+5V
Analog
Patch
Area
GND
CDB3310
-5V
Power Supply
Conditioning
AINR __---~
Digital
Patch
Area
AOUTR
CS331 0
AINL
AOUTL
PC
Control
Port
Microcontroller
CS
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
SDATAI SDATAO SCLK
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS82DB1
7-24
..... .. .......
~~
~~~
ICOBCAPTUREI
~-~~
Semiconductor Corporation
Data Capture and Interface Board for a PC
General Description
Features
• Measurement Tool used for the
evaluation of Crystal Semiconductor
Analog to Digital Converters.
• Easy interface to a PC Compatible
computer.
• LabWindows@ evaluation software for
data analysis.
• Includes time domain, FFT and noise
distribution histograms.
• Can be used to evaluate the ADC in
your equipment.
The CAPTURE interface board is a development tool
that interfaces a Crystal Semiconductor analog to digital converter to a PC compatible computer. Digital data
is collected in a high speed digital FIFO, then transferred to the PC over a serial COM port. Evaluation
software is included to analyze the data and demonstrate the analog to digital converter's performance.
The CAPTURE interface board is designed to be easily
interfaced to Crystal Semiconductor Evaluation boards.
Application software is loaded via the PC's serial COM
port. The software adjusts the CAPTURE interface
board for the appropriate signat. timing and polarity,
coding format and number of bits, thus allowing the
same hardware to be used with a variety ot Crystal
Semiconductor ADCs.
Evaluation software is included with the CAPTURE interface board. The software is developed with
LabWindows, a software development system for instrument control, data acquisition, and analysis
applications. The evaluation software permits time domain, frequency domain and histogram analysis.
Ordering Information: CDBCAPTURE
Power
Supply \
·.oe~
Signal
Source
o0°
00
+5 V Power
Supply
.0. ·
=I~
I
I
00
.00
@JO@.
Crystal
Evaluation
Board
.co
.COul
Serial
Cable
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Evaluation
Software
••
==>
~
~
I .co ml
CDBCAPTURE
RS232 Cable
IBM Compatible PC
(AT or Better)
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
JULY '93
DS124F1
7-25
_
-_.,_....._-..
,_...............
....
.COBCAPTURE
OVERVIEW
The CAPTURE interface board captures a block
of AID converter output data, which is then
transferred to the PC. The CAPTURE board
buffers the high speed digital data in a FIFO and
transfers the data to the PC via the COM port.
Figure 1 is a functional block diagram which
illustrates the data acquisition process.
The setup for the CAPTURE board is simple. A
serial cable is connected from the evaluation
board to the CAPTURE board. An RS232 cable
is connected from the CAPTURE board to a PC
COM port. A +5V power supply is required.
Upon reset, the microcontroller (uC) on the
CAPTURE board begins executing boot code
from its internal EPROM. The boot code
monitors the uC's serial port for application
software from the PC and stores the application
software in SRAM. The application software is
specific for the type of A/D converter being
used. When the transfer is complete, the uC
executes program code out of the SRAM and
turns on the LED.
With the uC running the application software,
the data collection process can begin. The
collection process is started by a command sent
from the PC to the CAPTURE board. When the
collection command is received, the CAPTURE
board synchronizes itself to the FRAME signal
and begins capturing data from the ADC. The
serial cable signals are optically isolated for
optimum noise isolation and the data is stored in
a serial FIFO. The writing to the FIFO is
controlled by the IlC and Counter/Control
circuit.
When the data sample set has been collected and
stored in the serial FIFO, the uC reads the data
out of the FIFO and converts the format to 2's
complement if required. The data in 2's
complement format is then transferred to the PC
via the RS232 cable connected the PC's COMM
port.
The evaluation software developed with
LabWindows performs post processing of the
digitized signal (source code included). Time
plots, FFT analysis and noise analysis are
included. The software operates upon sample
sets as large as 8192. For more sophisticated
analysis, the LabWindows development system
can be purchased from National Instruments
(512-794-0100).
CS5012A
CS5014
CS5016
CS5030
CS5031
CS5101A
CS5102A
CS5126
CS5317
CS5322
CS5326
CS5327
CS5328
CS5329
CS5336
CS5338
CS5339
CS5345
CS5349
CS5389
CS5501
CS5503
CS5505
CS5506
CS5507
CS5508
Crystal Parts Supported by Capture Board
*Future products will be added with software updates
Packaging List:
SDATA
CDBCAPTURE Interface Board
Serial Cable
EIA232 Cable (RS232)
3.5" 1.44 MB Software. Diskette
R
r----1 S
SCLK
RS232
CABLE
2
FRAME
3
2
5VDC
GND
Serial
Cable
+5VDC
GND
Figure 1. Functional Block Diagram
7-26
DS124F1
.._-_
.-_
_
..--_
__
...-..
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDlF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
8
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
8-1
----------------------
APPLICATION NOTES/PAPERS
This section contains a collection of Audio Engineering Society (AES) papers, application notes and
other papers, all authored by Crystal engineers. Much useful information is presented here. If you are
considering using a Crystal Semiconductor audio product, please read the relevant papers presented
below.
CONTENTS
Printed Circuit Board Layout Guidelines
NO Converter Input Protection Techniques
Delta-Sigma NO Conversion Technique Overview
CS5326 to DSP56000 Interface
CS5326 Low Frequency Operation
CS5328 ADC AES paper by C. Sanchez
CS5326 ADC AES paper by D. WeIland et al
Clock Jitter AES paper by S. Harris .
CS4328 DAC AES paper by N. Sooch et al .
AESIEBU Transmitters and Receivers AES paper by D. Knapp
AESIEBU & SIPDIF Digital Audio Communication Standards Overview
CS4303 DAC AES paper by S. Green et al .
Using Delta-Sigma NO & D/A Converters AES paper by S. Harris
CS4225 NO & D/A AES paper by S. Harris et al
SCMS AES paper by C. Sanchez .
Single Chip Stereo Audio Codec AES paper by S. McDonald et al
A Single Chip Stereo Volume Control AES paper by L. Harris et al
A MIDI Tutorial
Design Techniques for CD-Quality Audio SVPC paper by Ron Knapp .
8-2
8-3
8-7
8-11
8-21
8-23
8-25
8-43
8-55
8-67
8-79
8-93
8-101
8-121
8-137
8-153
8-189
8-203
8-213
8-237
..
..
...
..........
..,
.....
~~
~~
~~
Semiconductor Corporation
All ADC's/DAC's
Application Note
Layout and Design Rules for Data Converters
by
Ron Knapp & Steven Harris
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445 7581
NOV '93
AN18REV4
8-3
-. ..--_._.
__ ...._ _ .iIt_ _
~
•
L~youtDesign
Rules
Here is a list of guidelines for optimum printed circuit board layout for Crystal ADC's, DAC's,
and codecs. Use these pages as a checklist during and after layout by checking the boxes
when each line item is OK. Remember, Crystal offers a free schematic and layout review
service. Try hard to use this service ~ building your first prototype board. Comments
or additional items are very welcome.
D
1)
Partition the board with all analog components grouped together in one area and all
digital components in the other. Common power supply related components should be
centrally located.
D
2)
Have separate analog and digital ground planes on the same layer, with the digital
components over the digital ground plane, and the analog components, including the analog
power regulators, over the analog ground plane. The split between planes should be >1/8" .
D
3)
Mixed signal components, including the data converters, should bridge the partition in the
ground plane with only analog pins in the analog area, and only digital pins in the digital
area. Rotating the data converter can often make this task easier.
For our serial codecs, the device should be placed over the analog ground plane, positioned
next to the ground plane split. The digital pins should be next to the split, with the digital
traces crossing directly over into the digital region of the board. The analog ground pins
and digital ground pins should be connected with zero impedence (same ground plane). See
the CS4215 and CS4216, CDB4215 and CDB4216 data sheets for examples.
8-4
D
4)
Analog and digital ground planes should only be connected at one point (in most cases).
Have vias available in the board to allow altemative connection points.
D
5)
The analog to digital ground plane connection should be near to the power supply, or near
to the power supply connections to the board, or near to the data converter. In the case of
multiple converters, leave jumper options at each converter.
D
D
D
6)
Analog power and analog signal traces should be over the analog ground plane.
7)
Digital power and digital signal traces should be over the digital ground plane.
8)
Keep digital signal traces, especially the clock, as far away from analog input and voltage
reference pins as possible.
D
9)
Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the
shortest connection to pins with wide traces to reduce impedance (for example, between
pins 1 and 28 at the top end of the IC package in the case of the VREF decoupling capacitors
for the CS5326 family, the CS5336 family and the CS4328).
D
10) If both large electrolytic and small ceramic capacitors are recommended, make the small
ceramic capacitor closest to the IC pins. For multi-layer pc boards, make the connections
to the converter and to the capacitors on the same layer (this avoids the additional
irnpedence of vias).
AN18REV4
---------------------o
o
o
o
o
o
o
o
o
o
o
o
Layout Design Rules
11) All filtering capacitors in the signal path should be NPOICOG dielectric. BXlX7R
dielectric is OK for DC voltages where voltage coefficient is not a factor.
12) All resistors in the signal path or on the voltage reference should be metal film. Carbon
resistors are OK for DC voltages and the power supply path where voltage coefficient,
temperature coefficient or noise are not a factor. Avoid wire wound resistors and
potentiometers.
13) Avoid multiple crystal oscillators or asynchronous clocks. Best results are obtained when
all circuits are synchronous to the NO or DIA sampling clock.
14) When using converters with DSP IC's, operate everything from one crystal using
dividers if necessary.
15) In systems requiring multiple crystals for selectable sampling frequencies, enable only one
at a time. Shut off all other oscillators by removing power. Make sure other oscillators
are off either with an active crowbar on Vcc or ~ high impedance switch. Often
the leakage from a transistor or FET which is not completely off is sufficient for the
oscillator to produce a low level output frequency.
16) When using DC-DC switching regulators, synchronize the switching frequency to the NO
if possible. This applies to CMOS chopper amplifiers as well.
17) Avoid connecting the clock source oscillator to the converter sampling clock input through
analog multiplexers, PAL's, gate arrays, opto-couplers or circuits which can cause jitter.
18) Locate the crystal or oscillator close to the converter. Avoid overshoot and undershoot on
the master clock for the converter. This is particularly important for the CS5326 family,
where the master clock (CLKIN) goes directly into the analog modulator die.
19) Use buffers for digital signals directly to or from the converter to connectors which
go off the board.
20) In the case of piggy-back boards, or boards which plug into a slot adjacent to other
boards, consider the circuits which will be above or below the converter as sources
of interference. A mu-metal screen may be required.
21) For delta sigma converters, make sure that potential interfering clocks are not in
sensitive frequency regions. Sensitive regions are defined as ± passband either
side of multiples of the input sample rate. Two examples are : a) for a CS5336
operating at 48 kHz word rate, the frequencies to avoid are (N X 3.072MHz) ±24 kHz.
b) for a CS5501 with a 4 MHz crystal, the frequencies to avoid are
(N X 16 kHz) ± 10 Hz. Frequencies which are synchronous to the input sample rate
will not cause problems, since they will be converted to dc, and calibrated out.
22) For boards with more than 2 layers, do not overlap analog related and digital related
planes. Do not have a plane which crosses the split between the analog ground plane
region and the digital ground plane region.
AN18REV4
8-5
-
---------------------o
o
o
o
o
o
o
o
Layout Design Rules
23) For CS5326, CS5336 & CS5349 families, supply VD+ to the device via a separate
trace connected to where the +5V digital supply enters the board. Connect no other logic
to this trace. Alternatively, provide a 10 JlH inductor in series with VD+, near to the ADC.
24) For boards with both NDconverters and DIA converters, provide a means for testing each
function separately. Possible methods include providing a header to allow access to the
digital data paths, and allowing for easy attachment of a CS8402 and CS8412 AESIEBU
transmitter and receiver parts.
25) Terminate unused op-amps in dual and quad packs by grounding the + input and
connecting the - input to the output.
26) Digital control lines which must cross into the analog region should be as short as
possible and should be mostly static. For example, digital gain and analog mux control
lines.
27) Regions between analog signal traces should be ftIled with copper, which should be
electrically attached to the analog ground plane, Regions between digital signal traces
should be fIlled with copper, which should be electrically attached to the digital ground plane.
These regions should llQt be left floating, which only make the interference worse. Using
ground plane fill has been shown to reduce digital to analog coupling by up to 30 dB.
28) The pins of DIP or SOlC packages should not have ground plane in between adjacent pins.
29) In systems using a delta-sigma converter, then avoid the use of clocks (particularly the serial
bit clock) at half the frequency of the input sample rate. If this frequency interferes with
the voltage reference, then tones can occur.
30) Do not surround the analog region with digital components. Do not surround the digital
region with the analog region
Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Vnllr' Rruo,rri
8-6
AN18REV4
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,.,.........,.,
~~..,.
ADC Input Buffer and
Protection Techniques
Semiconductor Corporation
Application Note
ADC Input Buffer and Protection Techniques
by
Steven Green
Figure 1. ADC Input Protection ±15V Op-Amp
Introduction
SCR Latch-up
The design of input buffer and protection circuits
for analog-to-digital-converters (ADC) is critical
to an optimized and reliable data acquisition system. The Crystal Semiconductor application note
"ADC Input Buffers" covered this area well and
the system designer should review this information. Since the publication of "ADC Input
Buffers" there have been many requests for additional information and circuits relating to ADC
input protection. This application note describes
suitable buffer/protection circuits for the CS5336
family of converters. The techniques described
are equally applicable to the other families of
Crystal analog-to-digital converters.
SCR latch-up has been defined as "the creation
of a low impedance path between the power supply rails by the triggering of parasitic, fourlayer bipolar structures (SCR's) inherent in
CMOS input and output circuitry." This is a selfsustaining condition and once latched, a
CMOS device will remain so regardless of the
110 pin voltages until the power supply voltages
are removed. The excessive power dissipation
during latch-up may also damage the device.
Latch-up is most often caused by forcing current
into the inputs or outputs of a CMOS device
by applying voltages greater than the power supply rails. When powered, Crystal Semiconductor
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
FEB '92
AN20REV2
8-7
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..--_
.-_
_
..--_._.
__
...-.
ADC's are extremely immune to latch-up
because of the amount of current required to
initiate a latch. Problems can arise when input
voltages greater than the instantaneous power
supply voltages are applied during power-up. A
less common but equally damaging SCR condition can occur when power-supply voltages
exceed the absolute maximum specified value.
There are several protection techniques available
to the designer each with their own advantages
and disadvantages.
Protection Techniques
The goal of input protection is to guarantee that
the ADC input voltage never exceeds the supply
voltages of the converter. This is accomplished
with an op-amp buffer between the "outside"
world and the ADC input, then limiting the ADC
input voltage excursions to the range bounded by
the converter power supply voltages.
Method I
There are many high. quality op-amps available
to the design engineer for use as input buffers
and the majority of these have been designed
to operate from power supplies greater than ±5Y.
The use of the required multiple supplies presents potential problems. It is possible for the
ADC analog input to experience voltages greater
than the ADC supplies either during signal amplitude excursions, transient power-on conditions
or op-amp failure. Several methods are available
to clamp the ADC input voltage and are discussed in detail in references 1-7. Figure 1
shows a diode-clamped input buffer circuit utilizing multiple supplies. The type of diode
selected for CRI-CR4 is crucial and must be
evaluated using the following criteria:
1) Forward-biased voltage characteristics.
Schottky diodes are preferred due to their low
forward-biased voltage characteristics.
2) Reverse-bias leakage current. The effects of
8-8
Input Buffer/Protection Techniques
voltage dependent leakage currents are proportional to circuit impedences and can cause
distortion. Leakage currents will also vary with
temperature and must be evaluated over the intended temperature operating range.
3) Reverse-bias capacitance. Voltage dependent
junction capacitance can cause distortion and
must be insignificant in comparison to the circuit
component values.
Figure 2 is a comparison %THD plot of the circuit of Figure 1 with and without IN5818
Schottky diodes installed for CRI-CR4. Note
the increase in %THD resulting from diode capacitance. Figure 3 is a comparison %THD plot
of the circuit of Figure 1 with and without
Philips BAT-85 Schottky diodes. Note the lack
of distortion produced by the addition of suitable
protection components. Hewlett-Packard 50822810 diodes give similar results.
Notes for Method 1
The values of Rl and R2 were selected to optimize the source impedance for the CS5336 and
utilize the current limiting characteristics of the
op-amp.
Clamping circuits with diodes in the feedback
loop of the op-amp work well for signal clamping but are not effective for power-on transient
or op-amp failure conditions. These circuits are
not recommended for protection.
ADe Power Supply Overvoltage
Standard 3-terminal regulators are designed to
either source (78L05) or sink (79L05) current
but not both. It is possible to raise the ADC supply voltage above the regulation voltage through
the Schottky diodes during error conditions. The
5.6V zener diodes CR5 and CR6 are included to
prevent the supply voltages from exceeding the
maximum specified value and damaging the converter.
AN20REV2
.._-_
_.-_..--_._.
__
...-.
THD+N(%)
vs
Input Buffer/Protection Techniques
THD+N(%)
FREQ(Hz)
1
Ap
0.1
0.1
0.010
0.010
0.001
0.001
0.0005
0.0005
20
100
1k
10k 20k
Figure 2. % THD Effects of IN5818 Schottky Diodes
with NE5532 Op-amp
Method II
The goals of input protection can also be
achieved by powering the input buffer from the
same supplies as the converter as shown in Figure 4. This circuit requires fewer components
than the circuit of Figure I and the use of com-
vs
FREQ(Hz)
1
20
Ap
1k
100
10k 20k
Figure 3. %THD Effects of BAT-85 Schottky Diodes
with NE5532 Op-amp
mon power supplies guarantees that the op-amp
output will not exceed the ADC supply voltages.
However, the required analog voltage to achieve
full scale digital output for the CS5336 is typically ±3.68 V and the majority of op-amps do
not have this output capability with ±5V supplies.
51
n
-
+15V
2k
Left
Analog
Input
Right
Analog
Input
-15V
• must be capable of ±3.7 V output
with ±5 V supplies
Figure 4. ADC Input Protection ±5V Op-Amp
AN20REV2
8-9
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_
__
...-.
THD+N(%)
vs
Input Buffer/Protection Techniques
FREQ(Hz)
1
THD+N(%)
,lip
vs FREQ(Hz)
1
,lip
0.1
0.1
0.010 ~
0.010
~
0.001 ~
0.0005 F
20
0.001
0.0005
100
lk
10k 20k
20
100
lk
10k
20k
Figure 5. % THD Effects of Power Supply Variation
for MC33078 at ±15V and ±5V
Figure 6. % THD Effects of Power Supply Variation
for MC33078 at ±15V and ±4.75V
The, Motorola MC33078/9 is a viable contender
for this application. Figure 5 shows the %THD
vs Frequency of the MC33078 with ±15 and
±5V supplies operating at 3.68 Vp. Note the lack
of performance degradation resulting from the
reduced supplies.
data acquisition system will not be limited by the
input buffer and protection circuits.
The power supply voltages could be as low as
4.75V due to the 5 % tolerance of the
78L05179L05. Figure 6 shows the increased
%THD of the MC33078 at this supply voltage.
Due to the transient nature of audio signals, digital audio systems are generally operated at
average levels 10 to 20 dB below full scale. This
is to allow sufficient headroom to handle high
amplitude transient signals. The increase in distortion at full scale due to regulator tolerances
could be considered insignificant. If required,
2% regulators will avoid this increase in distortion.
Conclusion
Two circuits have been described which utilize
effective protection techniques. Use of either of
these circuits or the techniques described will insure that the performance and reliability of a
8-10
References
1. Johnston, Jerome: ADC Input Buffers,
Crystal Semiconductor Corp.
2. Fredriksen, Thomas M.: Intuitive IC Op
Amps, National Semiconductor Technology Series 1984
3. Pease, Robert: Bounding, clamping
techniques improve circuit performance, EDN
Nov. 10, 1983
4. Pease, Robert: Active-component problems
yield painstaking probing, EDN Aug. 3, 1989
5. HewlettlPackard Components: Application
Bulletin 14, Waveform Clipping With Schottky
Diodes.
6. HewlettIPackard Components: Application
Bulletin 15, Waveform Clipping With Schottky
Diodes.
7. HewlettlPackard Components: Application
Note 942, Schottky Diodes for High Volume,
Low Cost Applications
8. Application Note MSAN-107: Understanding
and Eliminating Latch-up in CMOS
Applications, MITEL August 1982
AN20REV2
. .........__ ...
.......
~
.",
..,..,~
Delta-Sigma Techniques
~~
Semiconductor Corporation
Application Note
Delta Sigma AID Conversion Technique Overview
a. Analog Input Spectrum
~.
5kHz
2.5MHz
f -3dB
fs
b. Modulator Digital Output Spectrum
Shaped
Quantization
2.5MHz
5kHz
-
c. Digital Filter Response
No Noise Rejection
at Integer Multiples
of Oversampling Rate
2.5MHz
5kHz
d. Digital Filter Output Spectrum
(Before Decimation)
Spectrum of Interest
5kHz
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 TWX: 910-874-1352
2.5MHz
JAN '89
AN10REV1
8-11
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Delta-Sigma techniques
.".,,-
SECTION A
OVERVIEW,' DELTA-SIGMA MODUlATION
Although developed over two decades ago, deltasigma modulation has only recently achieved
commercial implementation. The technique utilizes oversampling and digital filtering to achieve
high performance in both AID conversion and filtering at low cost. The advent of commercial
delta-sigma converters is due in most part to recent advances in mixed analog-digital VLSI
technology. Precision analog circuitry can now be
integrated on the same chip with powerful digital
filters.
Figure A1. Delta-Sigma ADC
In a delta-sigma ADC, the same digital fIlter used
in the AID conversion process can perform
system-level filtering with performance unachievable in analog form. Therefore, the first
commercial delta-sigma converters have been
targeted at applications demanding high-performance filtering (high-end modems, digital audio,
geophysical exploration, etc).
This application note uses the CS5317 voice
band AID converter for examples. See the end of
this application note for implementation details
for the CS5317, CS5501, CS5326 AID converters.
embedded in an analog negative feedback loop
with high open loop gain. The modulator loop
oversamples and processes the analog input at a
rate much higher than the bandwidth of interest.
The modulator's output provides small packages
of information (that is, I-bit) at a very high rate
and in a format that the digital filter can process
to extract higher resolution (such as 16-bits) at a
lower rate.
The delta-sigma converter's basic operation can
be analyzed in either the time domain, or (more
conventionally) in the frequency domain.
Time-Domain Analysis
The basic operation of a delta-sigma modulator
can be understood more intuitively by demonstration. A simple, first-order modulator (that is, a
conventional voltage-to-frequency converter) is
shown in Figure A2. (Note: a modulator's order
indicates the number of orders of analog filtering
- or integration - in the loop). Full-scale inputs
are ± I V and three nodes are labeled VI, V2, and
V3. The output of the comparator, node V3, is the
output of the loop and is also converted by the
I-bit DAC into plus or minus full-scale (+ I V or
-IV).
At the differential amplifier, the -I- 1V or -1 V is
subtracted from the analog input voltage. The result, the voltage at node VI, is input to the
integrator. The integrator acts as an analog accumulator; ie. the input voltage at node V 1 is added
to the voltage on node V2 which becomes the
new voltage on node V2. Node V2 is then com-
Digital
Output
Fundamentals
Differential
Amplifier
Integrator
- - - - - +1v
A delta-sigma ADC consists of two basic blocks:
an analog modulator and a digital fIlter (see Figure AI). The fundamental principle behind the
modulator is that of a single-bit AID converter
8-12
?
,
Comparator
DAC'
__ :1 v___
~
Figure A2. 1st_order Delta-Sigma Modulator
AN10REV1
----------------------
Delta-Sigma Techniques
pared to ground. If it is greater than ground, node
V3 becomes +IV; if it is less than ground, V3
becomes -1 V. Each operation occurs once during
each clock cycle.
In the example shown in Table AI, all nodes are
initially set to zero, and the analog input voltage
is assumed to be 0.6V Since all nodes are identical in clock cycles two and seven, the period
defined by cycles two to six will repeat if the
analog input remains unchanged. The average
value of modulator outputs (at node V3) during
that period, 0.6, yields a numerical representation
of the analog input.
Clock
Period
V1
V2
V3
0
1
2
3
4
5
6
7
8
0
0.6
-0.4
-0.4
1.6
-0.4
-0.4
-0.4
-0.4
0
0.6
0.2
-0.2
1.4
1.0
0.6
0.2
-0.2
0
Period
Avg
1 +--f-1
-1
0.6
1
11 _ _
1
-1
Table AI. Modulator Walk-Through
With conventional voltage-to-frequency converters a digital counter is used to extract the
information in the VFC's I-bit output. Pulses are
counted over a specified period, effectively creating a digital averaging (or integrating) filter. The
final count represents the average analog input
value during the integrating period.
Advanced delta-sigma converters use higher-order modulators and more powerful digital filters.
For example, the CS5317 uses a second-order
modulator. The pattern of transitions in its I-bit
output provides more useful information regarding higher resolution at higher frequencies.
AN10REV1
However, a more sophisticated digital filter than
a counter is needed to interpret that information.
A digital FIR filter is basically a rolling,
weighted average of consecutive samples (see
Appendix B). An averaging filter weights all
samples equally. By applying a more sophisticated weighting function to the I-bit signal, a
digital FIR filter can assemble an N-bit output
(with 2N possible values) without having to wait
for 2N samples.
The Charge-Balance Name
Delta-sigma ADC's are also known by other
names - sigma delta and charge-balance are two
examples. The Charge-Balance name derives
from the fact that the modulator tries to balance
the analog input with the DAC's output in the
negative feedback loop. The charge injected onto
the integrator's capacitor from sampling the analog input (see Figure A2) is therefore balanced by
the charge injected by the DAC's output. Modulators have been implemented in both
switched-capacitor and continuous-time form.
Frequency-Domain Analysis
Since filtering plays a key role in a delta-sigma
ADC, it is easier to understand the converter's
operation by analyzing it in the frequency domain.
Overview
An AID converter's resolution determines its dynamic range (or signal-to-noise ratio).
Conversely, one can improve a converter's signal-to-noise ratio and thereby increase its
effective resolution. The fundamental concept
behind delta-sigma converters is to perform a
simple, low-resolution AID conversion and reduce the resulting "quantization noise" (without
affecting the frequency band of interest) using
analog and digital filtering.
8-13
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_.-_..--_.-.
__.._-_
...-.
Quantization Noise
The comparator in the delta-sigma modulator
loop plays the role of a I-bit AID converter. Any
AID converter· can represent a continuous analog
input by one of only a finite number of codes,
giving rise to an uncertainty, or quantization error, of up to ± 112 LSB. For a consecutive
sequence· of samples in a waveform, these quantization effects can be modeled as a random noise
source under conditions commonly encountered
in signal processing· applications. (These conditions hold true for delta-sigma modulators). The
rms value of the noise source relative to a fullscale input can be shown to equal - (6.02 N +
1.76) dB, for an N-bit resolution converter. Since
this error "signal" is totally random (or uncorrelated with the input) it can be assumed to be
white, with its energy spread uniformly over the
band from dc to one-half the sampling rate.
As a I-bit ADC, the comparator in a delta-sigma
modulator ·offers (an almost comical) 7.78 dB
signal-to-noise ratio. However, the input signal is
grossly oversampled (2.5 MHz in the CS5317),
thus spreading the quantization noise over a wide
bandwidth (1.25 MHz). The noise density in the
bandwidth of interest (5 kHz) is therefore reduced.
Delta-Sigma Techniques
Dout = Q(n) - H(t) Dout
Q(n)
Dout = I + H(t)
The quantization noise at the output is reduced
by the open-loop gain of the integrator. At low
frequency, the integrator is designed for high
open-loop gain, so that quantization noise is reduced. As shown in Figure A4b, the integrator
effectively pushes the quantization noise out of
the bandwidth of interest and into higher frequencies. Digital lowpass filtering then removes the
quantization noise at the higher frequencies without affecting the low-frequency spectrum of
interest.
The spectral characteristics of the analog loop filtering dictates the delta-sigma converter's
resolutionlbandwidth ratio. Higher-order integrators improve noise shaping and allow for higher
resolutions at wider bandwidths. The CS5317
uses a second-order modulator for superior noise
shaping.
Q(n)
v;"~
"In
~DO"
Figure A3. Analog Modulator Model
Noise Shaping
Digital Filtering
Analog filtering is used in the modulator loop to
further reduce noise density in the frequency
band of interest by shaping the quantization noise
spectrum. The spectrum of the input signal,
meanwhile, remains unaltered. Figure A3 shows a
modulator loop with analog and digital circuit
differences ignored. The comparator is simply
shown as a (quantization) noise source, and the
analog filtering, which is simply an integrator, assumes the filter response H(t). If the analog input
equals zero, then
The spectral characteristics of the back-end digital filtering also affects the delta-sigma
converter's resolutionlbandwidth ratio. Faster
roll-off and greater stopband rejection reduces residual quantization noise. Section B offers a
detailed explanation of the theory behind digital
filtering.
Anti-Alias Requirements
As shown in Figure A4, the input and digital flltering spectrum of any ADC repeats around
integer multiples of its sampling rate. A delta8-14
AN10REV1
----------------------
Delta-Sigma Techniques
sigma ADC thus does not provide noise rejection
in the region around integer multiples of the sampling rate (± S kHz around 2.S MHz, S MHz, 7.S
MHz ... ). If noise exists in the system in these
narrow bands, analog filtering is needed to remove it at the converter's input otherwise it will
alias and pass unfiltered to the converter's output.
Since delta-sigma ADC's are grossly oversampled, anti-alias filtering requirements are often
trivial. For instance, the CSS317 provides a factor
of SOO of oversampling (2.S MHZ/S kHz). A s.ingle-pole, passive RC filter at the CSS317's input
is therefore sufficient in most applications.
Decimation
a. Analog Input Spectrum
~
5kHz
2.5MHz
f -3dB
fs
b. Modulator Digital Output Spectrum
Shaped
Quantization
Spectrum Repeats at
Oversampling Rate
Even though the delta-sigma ADC oversamples
and processes analog samples at a frequency well
above the bandwidth of interest, it will generally
offer its high-resolution output at a much-lower
system sampling rate. Any reduction in sampling
rate is termed decimation. The output can be further decimated at the system level by selectively
reading a fraction of the available samples (for
instance, every tenth sample). Independent of the
decimation ratio, the converter's noise performance (and effective resolution) remains
unchanged.
Conversion Accuracy/Performance
5kHz
2.5MHz
c. Digital Filter Response
No Noise Rejection
at Integer Multiples
of Oversampling Rate
5kHz
2.5MHz
d. Digital Filter Output Spectrum
Like integrating ADC's and V/F converters, a
delta-sigma ADC does not contain any source of
nonmonotonicity and thereby offers "theoretically
perfect" DNL with no missing codes. The ADC
in the modulator is simply a comparator, and the
DAC is the positive and negative voltage references. No precision ratio matching is needed as
in other medium- or high-speed AID conversion
techniques such as successive-approximation.
Useful resolution is limited only by residual
quantization noise which, in tum, is determined
by coarse analog and high-performance digital
filtering.
(Before Decimation)
Spectrum of Interest
5kHz
2.5MHz
Linearity error is limited only by imperfections in
the input sample/hold. The CSS317 achieves
typical nonlinearity of just ± 0.003 % through the
use of high-quality on-chip silicon dioxide capacitors with low capacitor voltage coefficient.
Figure A4. Delta-Sigma Spectral Analysis
(Using frequencies taken from the CS5317 AID
Converter)
AN10REV1
8-15
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...-.
Delta-Sigma Techniques
SECTIONB
Sampled-Data Theory
OVERVIEW.' DIGITAL FILTERING
A fundamental phenomenon. in sampled-data systems is an effect called "aliasing." Basically, once
an analog signal is sampled, its frequency components are no longer uniquely distinguishable.
Figure Bla shows a special case called "dc aliasing." If a signal is sampled precisely at its
fundamental frequency, it will always be sampled
at the same point on the waveform. It thus becomes indistinguishable from a dc input.
Likewise, a signal at twice the sampling frequency (or any integer multiple of fs) would
appear as dc as well. Figure BIb illustrates a
more general case of aliasing. Again, two signals
at different frequencies become indistinguishable
once sampled.
A conventional analog filter implements a mathematical equation using reactive components
(capacitors and inductors). A digital filter can implement the same filter equation using two
fundamental arithmetic operations: multiplication
and addition (or accumulation). A digital filter
considers a consecutive sequence of digitized
samples a "waveform." It analyzes the relationship between samples, processes the data, and
outputs an adjusted waveform.
Digital filters offer ideal stability, repeatability,
and potentially perfect performance (linear phase,
etc.). Digital filters also remain impervious to environmental conditions, thus providing superior
reliability over time and temperature. The major
difference compared to analog filters, though, is
that digital filters operate on a signal in sampled
form.
The effect of aliasing in the frequency domain is
illustrated in Figure B2. The baseband spectrum
(dc to one-half the sampling rate) also "appears"
around integer multiples of the sampling rate,
and vice-versa. In signal processing applications,
Volts
Time
L.
Is
f = f s (sampling frequency)
a. Continuous-Time Input Spectrum
a. de Aliasing
Is 12
Is
b. Sampled-Data Spectrum
f= (N + 1)fslN
b. General Aliasing
Figure Bl. Aliasing in Sampled-Data Systems
8-16
Figure B2. Sampled-Data Spectrum
AN10REV1
---------------------anti-alias filtering is used to bandlimit the analog
signal before it is sampled. This removes out-ofband components which could be mistaken for
important information in the band of interes(
Aliasing is critical in digital filtering. A digital
filter is incapable of distinguishing signals in its
passband from signals aliasing from around its
sampling frequency. Its passband spectrum therefore repeats around integer multiples of the
sampling frequency. Take for instance the case of
dc aliasing shown in Figure Bla. A digital lowpass filter would treat the signal at fs as a dc
input and pass it with no attenuation. Similarly, if
the filter would attenuate the lower-frequency
signal in Figure Bib by 10 dB, the higher-frequency signal would receive the same 10 dB of
attenuation. The higher-frequency signals in both
cases could be selectively filtered only by analog
anti-alias filtering before the signal is sampled.
Delta-Sigma Techniques
be achieved by increasing integration time. The
trade-off is bandwidth.
-20
10
:s
~"c:
g'
::;;
-60
- - - -
-80
- - - -
-100 '----'---_L----'--_-'---------'--------,-'---------'-------,-L---'-=_:'
o
2f,/N
4f,/N
Sf,/N
8f,/N
10f,IN
Frequency (Hz)
Sampling rates are usually set high enough that
analog anti-alias requirements become trivial (or
perhaps eliminated). Higher oversampling ratios
offer greater bandwidth to roll off between the
passband and sampling frequency. Noise in the
digital domain can be analyzed just as it is in the
analog domain. Limiting a system's bandwidth
will reduce noise and improve dynamic range.
Digital Filtering
The most popular digital filtering technique is averaging. A sequence of digital samples are simply
collected and averaged to produce an output. This
reduces noise by limiting the effective noise
bandwidth. Averaging yields a (sin x)/x (or sinc)
filter response as shown in Figure B3. The zeroes
of infinite rejection (at fsIN, 2fslN, 3fsIN, etc.)
can be strategically placed by selecting fs and the
number of samples averaged, N, to average over
an integral number of periods of critical frequencies (50 Hz, 60 Hz, etc.). Of course, this same
principle lies at the heart of integrating ADC's,
but the averaging is done in analog form. In both
cases greater dynamic range (or resolution) can
AN10REV1
Figure B3. Averaging Filter Response
FIR Filters
Averaging is an elementary example of FIR, or
Finite Impulse Response, digital filtering. Finite
Impulse Response indicates that the filter considers only a finite number of inputs to calculate
each output. The number of samples determines
the impulse response duration. For example, a
filter which averages ten samples has an impulse
response duration of ten. Longer durations indicate more information is considered for each
calculation, resulting in a more powerful filter response.
A digital filter's impulse response is what determines its filter function. It is basically a
weighting function applied to the sequence of
samples being considered. The averaging filter is
an elementary example of an FIR filter because it
uses equal weighting (weight = lIN where N =
# samples). More sophisticated impulse responses
extract the information contained in the relation8-17
-
----------- -----------
Delta-Sigma Techniques
ship between samples. Averaging filters ignore
this information.
Figure B4 illustrates how an FIR filter actually
implements the impulse response. The two basic
operations are multiplication (indicated by 0)
and addition - or accumulation - (indicated by L).
Filter coefficients ao to ~ represent the impulse
response. The three unit delay elements insure
that each output is calculated using the current
input sample and the three previous samples. The
filter's input, x(n), and output, yen), are digital
words of any length. (For the CS5317, x(n) is
I-bit and yen) is 16-bits). Each digital output requires one complete convolution. For the
4th -order filter shown in Figure B4, one convolution consists of four multiplications and the
accumulation of the four products.
FIR filters are often described in terms of taps.
This terminology hails back to analog transversal
filters, which were basically analog implementations of the filter in Figure B4. The analog delay
elements were termed taps. The number of taps
indicated the filter's impulse duration. The longer
the duration, the more powerful the filter.
Decimation
Digital filters often operate with input· sampling
rates well above the bandwidth of interest. This
serves to minimize analog anti-alias filtering requirements. The filter's output rate, however, is
generally dropped to a more manageable system
sampling rate. Any reduction in sampling rate is
termed decimation.
To illustrate the decimation process lets return to
averaging. A filter which collects ten samples and
then averages them to produce one output decimates by ten. That is, for an input rate of fs, the
output rate is fsl10. Alternatively, one could use a
"rolling average." For each input sample received, an output would be calculated using that
sample and the nine previous samples. The sampling rate would therefore remain at fs with no
decimation.
The 4th-order FIR filter in Figure B5 exhibits the
same filter response as that in Figure B4, but
decimates by a factor of four. In this case, only
one multiplication is performed per input cycle.
Without any delay elements, the accumulator
needs four input cycles to complete one convolution. Output samples are therefore produced at
fsf4. Decimation clearly relaxes computational
complexity.
Decimation does not affect overall signal-to-noise
or dynamic range. For this reason, one can decimate the CS5317's 20 kHz output (by selectively
reading a fraction of the available samples) without affecting the converter's noise. However, a
digital signal is normally not decimated if additional filtering is to be used to increase dynamic
range (and resolution). All noise energy in a sam-
x(n} >-------~
Circulating
Address
Generator
[:>
x(n)
N-t
Unit Delay Elements
y(n} = A
:>::
at Coefficient
ROM
a2
y(n)
a i x(n-i}
i=O
Figure B4. 4th_order FIR Filter
8-18
>--_f,,-8_~
aO
Figure B5. 4th -order FIR Filter with 4X Decimation
AN10REV1
.-_
_
..--_._.
__.._-_
...-.
pled signal lies between dc and one-half the sampling rate. Lower sampling rates therefore exhibit
larger noise densities in the bandwidth of interest
for a given amount of noise energy due to aliasing.
FIR Characteristics
The only source of inaccuracy in digital filters is
rounding errors due to finite word lengths in the
computations. If properly designed, a digital filter
will not induce linearity, offset, or gain errors.
Aside from their simplicity, FIR filters' most
popular characteristic is their ability to implement
perfectly linear phase filters. The effect of every
input sample on the output is always seen a fixed
number of cycles later. This processing delay
from input to output is termed the filter's group
delay, and can be shown to equal one-half the
impulse response duration.
Unfortunately, FIR filters can only implement zeroes, no poles. Roll-off is therefore limited. Of
course, this limitation can be overcome by cascading FIR filters to produce an extraordinarily
long impulse duration. (Fortunately stability is
not an issue with FIR filters). The trade-off,
though, is an extraordinarily long group delay.
Delta-Sigma Techniques
computational complexity. Therefore, IIR filters
generally operate with lower sampling rates.
The CS5317 Voice-band AID Converter
Implementation
The CSS317 uses oversampling, decimation, and
FIR filtering to implement its digital filter. The
CSS317 samples its analog input at 2.S MHz (for
a full-rated S MHz master clock). This high oversampling ratio of SOO: I (2.5 MHz sampling/S
kHz bandwidth) reduces external analog anti-alias
requirements.
The FIR filter decimates the sampling rate from
2.5 MHz to 20 kHz to reduce computational complexity. The filter features an impulse response
duration of 384 x 2.S MHz and a decimation ratio
of 128 (2.S MHz:20 kHz). Since the filter does
not decimate by 384 as shown in Figure BS, multiple convolutions must be in process
concurrently. To achieve this, the CSS317 uses
three accumulators working from a single 384word coefficient memory. The three convolutions
are spaced to begin and end 128 samples apart.
Thus, a new 16-bit output sample becomes available every 128 input samples (for a decimation
ratio of 128) whereas each 16-bit output is calculated using 384 input samples (for an impulse
response duration of 384).
IIR Filters
Infinite Impulse Response filters, on the other
hand, can implement zeroes and poles to achieve
high roll-off. Unlike FIR filters, which use previous inputs to calculate an output, IIR filters
also utilize historical output information to calculate each new output. In this manner, IIR filters
can implement mathematical filter equations with
variables in the denominator (that is, poles).
The only drawback to IIR filters is their computational complexity. Since their computations use
historical information on their past outputs, each
output must be calculated. That is, unlike FIR filters an IIR filter cannot decimate to reduce
AN10REV1
The CS5501 dc Measurement AID Converter
Implementation
The CSSSOI uses oversampling, decimation, and
both FIR and IIR filtering to implement its 6-pole
Gaussian filter. The CSSSOI samples its analog
input at 16kHz (for a full-rated 4.096MHz master
clock). This high oversampling ratio of 1600: 1
(16kHz sampling/10Hz bandwidth) reduces and
most often eliminates external analog anti-alias
requirements.
The FIR filter is used to decimate the sampling
rate from 16kHz to 4kHz to reduce computational complexity in the subsequent IIR filter. The
8-19
-
---------------------FIR filter response is not especially critical. Its
only goal is to reject energy within ±10Hz bands
around integer multiples of 4kHz, the llR filter's
sampling rate.
The IIR filter is needed to implement the poles in
the 6th -order Gaussian filter and achieve high
roll-off of 120dB/decade. Its baseband filter characteristics are shown on page 4. Note that the
filter's entire frequency response can be scaled
by adjusting the master clock. The converter's
sampling rate simply scales accordingly. With its
cut-off frequency set at 10Hz (4.096MHz master
clock) for maximized settling, the CS5501 offers
55dB rejection at 60Hz. With a 5Hz cut-off,
though, 60Hz rejection increases to greater than
90dB. Master clocks as low as 40.96kHz are acceptable, yielding cut-off frequencies as low as
O.1Hz.
Delta-Sigma Techniques
of a half-band filter for FlR3. Data is truncated to
16 bits at the output, and this operation is the majornoise contributor in the system.
FIR I , FIR2, and FlR3 also combine to provide
antialiasing filtering. All analog input frequencies
from 26kHz to 3046kHz are attenuated by at
least 86dB. Phase response is precisely linear.
The CS5326 Digital Audio AID Converter
Implementation
Linear-phase finite-impulse-response (FIR) filters
are used for decimation. The I-bit, 3.072 MHz
outputs of the modulators are decimated in steps
of 8, 4, and 2 to yield 16-bit, 48kHz results.
The decimation strategy includes two stages,
FlRI and FIR2, whose primary responsibility is
attenuation of quantization noise prior to decimation and aliasing. Modulator out-of-band
quantization noise spectral density is very high.
FIRI and FIR2 use 17 and 18-bit coefficients to
attenuate this noise, and out-of-band input signals, into the converter noise floor. Filter orders
are 27 and 30, respectively.
A third stage, FIR3, performs passband shaping
and out-of-band signal attenuation. Passband frequency response errors introduced by the
modulator, FIRI, and FIR2 are corrected by
FlR3. Overall filter passband ripple is thus reduced to ±o.OOldB from dc to 22kHz. The
passband compensation function prevents the use
AN10REV1
. ..,"'"......
.
....
"'" ....,
" ' " __ • •JII8fJII8f ~ •
CS5326 Interface
Semiconductor Corporation
Application Note
CS5326 to DSP56000 Interface
By Clif Sanchez
This application note describes the interface
needed to connect the CS5326 to the Motorola
DSP56000 Digital Signal Processor.
Since the CS5326 is a stereo delta-sigma
oversampled analog-to-digital converter, it
requires three clocks: a master clock to sample
the analog input, a serial clock to shift out data,
and a left/right clock to select the channel. The
74HC590 synchronous counter from TI, along
with a couple of inverters, provide all the clocks
thi!:!. the CS5326 requires. The output previous to
LIR , QF, is used as a frame sync for the
DSP56000 and connects to SC2 which is
configured as FSr. For the DSP56000, the FSL
bit must be set equal to zero.
ClKIN
ClKIN
74HC590
[> CCK
°A
OF
------. [>
CS5326
SCLK
+2
+64
-[::>o---£-SYNC
,----
RCK
°G
.
..
+ 128
SClK
SDATA
UR
r
SCQ
SC2
SCK
SRD
or
SC1
DSP56000/1
Figure 1. CS5326 to DSP56000 Connection Diagram
AN13REV2
8-21
.-_
.-.-.
_
..---_.._-_
...
CS5326 Interface
:
If the DSP56000 serial port is in the synchronous
mode, then the serial port transmit and receive
sections used the same serial clock. This releases
two pins, SCO and SCI, and one can be
configured as an input flag indicating the
channel, left or right. They are latched in the
DSP56000 at the same time as the MSB (see
Figure 2) and can be used to synchronize
left/right pairs.
If a synchronous counter is not available, a
similar circuit can be constructed from a ripple
counter and latch as shown in Figure 3. Since the
D flip-flops provide inverted outputs, the output
inverters are not needed. But the 74HC4040
ripple counter's clock must be inverted to give it
enough time, one full clock in~tead of one half
clock, to settle before the flip-flops latch the data.
ClKIN
>-__1 - - - - - - - - - - - _ ClKlN
SCLK
FSYNC
UR
Figure 3. Alternate to 74HC590
SClK
SDATA
SC2
~
(FSYNC)
SCQ
UR
~
SCQ
...
11
Figure 2. CS5326 to DSP56000 Timing Diagram
8·22
AN13REV2
....__
.. .....
................
~
.".,,~
CS5326nl8/9
Semiconductor Corporation
Application Note
CS5326/7/8/9 Low Frequency Operation
By Clif Sanchez
+5V
PD L 2
74HC74
T4
D S a
TST2,TST3
6
3
R
MClK
APD,DPD
5
a
1
+5V
L
ClKIN
~74HC1~
--
CLR'
74HC161
O~
1
14
a
0
1 R
~
EnT EnP 9
10 1 7 1
~D
11
R=Reset=Clear
S=Set=Preset
+5V
S
74HC74 8
R
13
This circuit places the CS5326/7/8/9 in test mode
6 and provides clocks with the proper frequencies
and relative phases to operate the converter at
speeds lower than specification.
In normal operation (i.e., not in a test mode), the
CS5326n18/9 utilizes a phase lock loop circuit to
implement a 3X clock frequency multiplier, the
output of which paces the digital filterl
decimators. The limited range of the PLL results
in a lower bound to the speed of operation. The
ACLKA output is normally connected to the
DCLKA input, and it is this clock signal that is
the input to the 3X frequency multiplier.
In test mode 6, the 3X multiplier is disabled, and
the clock required for the digital filterldecimators
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
UR
12
+~'L
l
EnT EnP
Pg'
TST1
r-
1°17L15
0x= 00 0r0 1
1 RCO
14 or 13
---c R
ax
+5V
U2
2
I>
l
ClK1
EnT EnP ~ =
10 1 71
74HC161
~
), 10
O2
U3
2
U1 L';-T
2
R
SClK
-,
a
DClKA
PO-P3 inputs on 161/3'5 tied low
is instead received directly on the DCLKA pin.
The lower bound on the speed of operation is
dramatically reduced (still non-zero due to
internal dynamic logic), but the DCLKA signal
frequency must be appropriately generated. The
requisite frequency is 1.5X the frequency of the
CLKlN signal. This ratio mimics the combination
of the divide-by-two between CLKIN and
ACLKAlDCLKA and the multiply-by-three
between ACLKAlDCLKA and the filter/decimators' clock that occurs in normal operation.
The master clock signal MCLK is used to drive a
divide-by-two counter to generate DCLKA and a
divide-by-three counter to generate CLKIN, and
to synchronize the PD (Power-Down) signal. The
latter is used to appropriately reset the phase of
MAR '90
AN14REV3
8-23
-
_.-_..--__...._-_
....
-._.'-.
CS5326nl8/9 Low Frequency Operation·
the counters. as well, as that of the delta-sigma
modulators in the CS5326n1S/9 (this is done
through the use of theAPD signal). In addition,
when PD falls, the complementary output of the
synchronizing flip-flop places the converter in
test mode 6 through the use of the TST2 and
TST3 pins. Note that the CS5326n1S/9 should
not be placed in test mode 6 in the absence of
active clocks. In addition to powering down the
analog section, APD is used to synchronize the
start of ACLKA. DPD initiates an offset
calibration and can be controlled separately from
APD. Since APD powers down the reference,
DPD should only occur at the same time or (at
any time) after APD is released. In test mode 6,
the serial data output during calibration is not
all zeros.
An additional_divider is used to generate the
SCLK and LIR signals which are derived from
CLKIN. The SCLK signal may be an inversion
of either QO or Ql. Using Ql, though, results in
an SCLK frequency that can slightly raise the
noise floor of the CS5326nlS/9 through
interference effects with the modulators. If
receive circuitry speed permits, QO should be
used to clock out the serial output data.
The resulting phases of the various clocks
generated by this circuitry is such that rising
SCLK edges and all LIR edges occur at falling
edges of DCLKA, as can be seen by referring to
the timing diagram. Furthermore, I-bit data
transfers between the modulators and the
filter/decimators are correctly timed. In normal
mode, this transfer is synchronized by the
ACLKA signal. In test mode 6, though, ACLKA
is not used (and should be left open), and the
correct timing is attained by setting the modulator
phase with APD, as described above. As a check,
it can be observed that falling edges of ACLKA
occur at rising edges of DCLKA.
I--Jl--JL 6fs
~
MClK
PD
APD,DPD
~L
____________________________________________
~I
___________
------~--------------------------------------------il-----------
.-------------------------------------------~~-----------
TST2,3 -------'
I
LJ
LJ
~~
~
~
---------------'IIL-----"IIL--------.J!L.1
I 12fs
ClR3 _ _--"
ClKIN
AClKA
(on CS5326n18l9")--------~--------'
ClK1 __________--.JII~
(~~=l~ a
SClK
.
UR
~
________'IIL__________'II'--____j~2fS
~
L-----------'I-J
~ --------~ I
L _________________________
(Ox= 0,)
8-24
~
~
rL---J/3fs
DClKA
Notes:
,---~
~fs
~
~
fs
fs/2
--------- fs
64
-----------------------------------------------------I-J
1. Qx = Qo is recommended for SCLK to avoid adverse analog interference effects caused
byj"s/2 signals.
2. lJR is a square wave with edges coincident with SCLK rising edges.
3. fs is analog sampling frequency.
AN14REV3
.._-_
._.-.
_.-_..--__
...
Sanchez CS5328 AES Paper
An IS-Bit Dual Channel Oversampling Delta-Sigma AID Converter,
with 19-Bit Mono Application Example
Clifton W. Sanchez,
Applications Engineer
Crystal Semiconductor, Corp.
Austin, Texas
U.S.A.
This paper was presented at the 87th Audio Engineering Society Convention,
New York, October 1989
ABSTRACT
The architecture and performance of a stereo I8-bit delta-sigma analog-todigital converter are discussed. This 28-pin device contains dual delta-sigma
modulators and dual digital filters/decimators. Special emphasis is placed on
applications examples using the AID converter in various common audio environments including AES/EBU integrated circuits and digital signal
processors. In addition, an example application is discussed in which the dual
channel 18-bit part is configured as a single 19-bit AID converter yielding a
dynamic range of 100 dB.
o INTRODUCTION
The benefits of using digital to store and process audio information are well documented[I]; however, the number of bits required to reproduce the analog signal to an acceptable level is still in flux.
Consumer products are standardizing on the I6-bit leve1[2] while professional equipment manufacturers are asking for more[3,4],
Sec. 1 describes the architecture of the CS5328, a stereo I8-bit delta-sigma analog-to-digital (AID)
converter. Sec. 2 illustrates the performance of the AID converter under a variety of test conditions.
Also discussed is a I9-bit monaural example in which both input channels are tied together and the
output words are summed, achieving a dynamic range of 100 dB over the.0-20 kHz audio band.
Sec. 3 describes interfaces to common audio environments such as AESIEBU integrated circuits and
the Philips I2S bus, while Sec. 4 discusses DSP interfaces. Sec. 5 discusses a method of attaching the
channel indication, left or right, as a tag to the end of the serial data stream.
1 ARCHITECTURE
The architecture of the CS5328, as seen in Figure 1, consists of two one-bit delta-sigma modulators[5] that oversample the analog input at a frequency that is 64 times the output word rate. Each
delta-sigma modulator is followed by a 3-stage FIR filter. Dividing the filtering function into three
8-25
-_.
__ ._.-------------
Sanchez CS5328 AES Paper
stages allows for an overall reduction in the number of required taps and incremental decimation to
arrive at the output word rate. The output of each channel is latched and multiplexed on the SDXfA
pin under control of the r.JR (left/right) signal. r.JR also starts the convolution for the FIR filters.
The digital filter response is illustrated in Figure 2 for a 48 kHz output word rate and has a stopband
rejection of greater than 86 dB. Since the filter is digital, the frequency response will scale with clock
frequency allowing the use of other sample frequencies. Table 1 lists the master clock frequency,
passband edge, -3 dB point, and stopband edge for typical digital audio frequencies. An expanded
view of the passband showing less than 0.001 dB passband ripple appears in Figure 3 while the
transition band is expanded in Figure 4.
2 PERFORMANCE
To test the AID converter, the analog input of a CDB5328 evaluation board[6] is driven with a signal
generator having distortion lower than the AID converter's noise floor. Any distortion produced from
such a setup is assumed to be from the AID converter[7]. For the FFT tests produced in this paper,
the analog input is either a Krohn-Hite Model 4400A or a Briiel & Kjrer Type 1051. The data is
collected for 1024 consecutive samples. The FFT expects the sample set to be periodic; therefore, if the
samples at each end of the sample set do not align exactly, the FFT will produce distortion products that
don't exist in the analog input. If the AID converter were synchronized to the analog input, the end points
could be aligned, but to align to the 18-bit level is very difficult. Since the analog input is not synchronized to the AID converter, the time-domain samples are windowed to avoid discontinuities at the end
points. Wmdowing drives the end points to zero making the first point and last point is the sample set
equal. The window is a minimum 5-tenn which widens the fundamental and harmonics, but doesn't affect
the specifications being tested such as SIN+D and dynamic range[8]. Since the noise is uncorrelated,
sample sets of points can be averaged to produce a plot in which the noise shape and low level harmonics
are distinguishable. The noise spreads itself equally among the frequency bins while the fundamental,
harmonics, and tones present, if any, remain unchanged. The data for this paper was gathered with a
personal computer which also calculates the FFT[9].
2.1 CS5328 Results
A plot of 100 sample sets averaged, using the previously mentioned setup with an analog input at full
scale, appears in Figure 5.· A full-scale input is not the optimum test for digital audio since any
excursions above full scale cause clipping and large distortions. Digital audio equipment usually
defines -10 dB asa maximum signal level to guardband against clipping. A signal 10 dB below full
scale would be a better test of an AID converter for this environment. As can be seen from Figure 6,
a -10 dB signal shows slightly better performance than the full scale signal and the harmonics are
practically below the noise floor. In Figure 7 the input signal is 80 dB down from full scale and is
considered a more difficult test of AID converter performance[lO]. On-chip dither minimizes tones
that are normally associated with delta-sigma AID converters. Figure 8 plots input signal level versus
signal-to-(noise+distortion) for a 1, 10, and 20 kHz input signal. This plot illustrates the CS5328's
lack of significant distortion for low signal levels over the entire audio band.
8-26
----------- -----------
Sanchez CS5328 AES Paper
2.2 19-Bit Monaural Mode
The hardware illustrated in Figure 9 ties the two analog inputs together and adds the two 18-bit
outputs, generating a 19-bit number. Utilizing the CDB5328 evaluation board, the serial data for eacE
channel is shifted into the serial-to-parallel converter during the first 18 serial clocks after LIR
changes state and is then latched on the parallel output. The serial-to-parallel converter has a separate
shift register and latch so the parallel output is valid until the next parallel latch update. On the
evaluation board, the left channel data is latched 14 serial clocks before uR falls and the adder
circuitry latches the left channel on the falling edge of uR. The right channel is latched on the
evaluation board 14 serial clocks before uR rises. The two 18-bit numbers propagate through the
adder during the latter 14 serial clocks of the uR low time and the 19-bit result is latched when LlR
rises.
The FFT plot in Figure 10 shows an improvement of approximately 3 dB using summed channels
over the single channel approach. The extra bit generates a 6 dB improvement since the signal level
is doubled, but the noise from the second channel invokes a 3 dB penalty. Figure 11 illustrates a
19-bit FFT with the analog input down 60 dB. Notice the dynamic range for the 19-bit mono mode
is 100 dB over the 0-20 kHz audio bandwidth.
3 TIMING IN AUDIO ENVIRONMENTS
In a typical audio environment such as CD, DAT, or digital audio workstations, the traditional analog
front end consists of an 11th-order Chebyshev anti-aliasing filter[ll], followed by a sample-and-hold
(SIH), and completed by an ND converter for each channel as shown in Figure l2a. The timing
section is required to synchronize the SIH, ND converter, output multiplexer, and digital signal
processing system. If oversampling is utilized, the diagram would look more like Figure 12b in
which oversampling by two decreases the anti-alias filter requirements to a 7th-order Butterworth[l1]. This anti-aliasing filter provides better group delay characteristics than the traditional
approach. In 2X oversampling the ND converter and SIH must be capable of operating twice as fast
as the traditional approach, and the timing section has to accommodate the decimation filter between
the ND converter and the system. Figure 12c shows the analog front end using the CS5328 that
oversamples the analog input by 64 generating a sample frequency, Fs, of 64xOWR (output word
rate). The CS5328 requires frequencies of l28xOWR for the master clock, 2xOWR for the serial
data clock, and OWR for the uR signal indicating the channel: left or right. The anti-aliasing filter
requirements are minimized to a single pole passive filter and the group delay characteristics for this
approach provide a flat delay over the entire passband. The high frequency clocks required are
usually available for other system functions and can be derived from a 74HC590 synchronous
counter.
3.1 Philips
Ps Bus
The "inter-IC sound" bus is a digital audio interface as defined by Philips[12]. The I2S interface uses
word select, WS, (inverted uR) to indicate both the channel and start of data. The data is output on
the falling edge of SCK one SCK cycle after WS changes state. In the configuration illustrated in
Figure 13, the 74HC590 counter is considered the master since it provides the word select and serial
8-27
-
_.-_..--__.._-_
...
._.-.
Sanchez CS5328 AES Paper
data clocks. The data output by the CS5328 must be delayed one SCLK cycle and is considered 32
bits in length with the receiving device ignoring unused bits as defined by the interface specifications.
3.2 Sony Digital Interface
Both the CX23033 and CXD121l from Sony Corp. are digital transmitting chips designed to send
data in a format similar to the AESIEBU specifications[l3]. The CS5328 interface for these chips
would be straightforward if the NO converter was only 16 bits because both interface ICs provide a
16-bit MSB-frrst format. Figure 14 illustrates the circuitry needed to connect the CS5326, a 16- bit
NO converter, to the Sony chips. Since the CS5238 outputs 18 bits, the 24-bit format of both
interface chips must be used, and that format only accepts data LSB first. If the interface chips
allowed the specification of the MSBILSB-first option separate from the 16-bitl24-bit option, the
interface would be greatly simplified. Another feature of the interface chips is that the data must be
right justified in the channel, whereas the data output from the CS5328 is left justified. Using the
16-bit format as an example, the 16 bits preceding LRCK (UR) changing state are latched for
right-justified data, whereas the 16 bits following LRCK changing state are latched for left-justified
data. Figure 15 illustrates a method of converting from MSB-frrst to LSB-frrst using tlrree cascaded
74HC299 shift registers oscillating between channels. When the right channel is shifting into the shift
registers from the NO converter, the left channel is shifting olit of the shift registers to the digital
interface chip and vice versa. LRCK for the CXD121l has the same polarity as the CS5328, high for
the left channel and low for the right channel, whereas LRCK in the CX23033 has the opposite
polarity. Figure 16 illustrates the flow of serial data for each channel. While the CS5328 is clocking
left-channel data into the 24-bit shift register via pin 'X, the shift register is clocking the previous
right-channel data out of the QH' pin and tlrrough a multiplexer into the interface chip. In Figure 16b
the shift register's shifting direction is reversed and still contains the left-channel data. When the
CS5328 starts shifting right-channel data into the shift register via pin 'H', the left-channel data
contained in the shift register is clocked out of the Q~ pin and through the multiplexer into the
interface chip. The multiplexer is needed to select the appropriate output of the 24-bit shift register to
input to the interface chip, whereas the two inputs to the shift register may be tied directly together.
The shift register clocks are disabled for eight serial clock cycles since only 24 bits of the 32 bit-periods in a channel are stored. Since the CS5328 outputs zeros after the 18 data bits, the shift register
stores six zeros. In the timing diagram shown in Figure 17, the 'z's reflect the stored zeros. All
combinational logic can be programmed into a PAL for compactness. To configure the interface chips
for the 24-bit format, MSBF is set to zero for the CXDI211, whereas the CX23033 is used in
operation mode lor, if a microcontroller is present, mode 3 with control register bits D7 and D6
both set to one.
4 INTERFACING TO DIGITAL SIGNAL PROCESSORS
Digital signal processors are used extensively in digital audio environments[14]. Although the digital
signal processors, DSPs, discussed below are not an exhaustive set of DSPs capable of handling
greater than 16 bits, they do illustrate the circuitry needed to interface to common serial ports.
8-28
.._-_
._.-.
_.-_..--__
...
Sanchez CS5328 AES Paper
4.1 Motorola DSP56000
The interface for the DSP56000 is straightforward as shown in Figure 18 with the timing diagram
appearing in Figure 19. The counter needed for the various timing signals on the CS5328 provides
other divided outputs that can be used by the DSP56000. The counter output previous to LlR,
FSYNC, is twice the frequency of uR and can be used to indicate the beginning of a word. This
output will rise concurrently with uR changing state; however, FSYNC will fall after the 16th data
bit is output. This is not a concern since the DSP56000 only uses FSYNC to start a serial data
transmission and stops transmission when the specified number of bits are received. The DSP56000's
serial port is configured to receive 24 bits (WL1,WLO = 1,1), normal operation (MOD = 0), continuous clock (GCK = 0), and word-length frame sync (FSLl = 0). If the transmit and receive ports are
synchronous (SYN = 1), uR can be used as a serial port flag indicating the channel. Section 5 has
more information on the serial port flag.
4.2 Texas Instruments TMS320C30
The TMS320C30 has an interface similar to the DSP56000, with the exception of serial port flags.
Figure 20 shows the interface diagram and Figure 21 illustrates the timing. If uR must be known to
the DSP, one of the alternate methods described in Section 5 must be employed. The interface diverges from previous TI DSPs but has become more flexible in the process. For the serial port, the
variable data rate mode with 24 or 32 bits is utilized. In this scenario, FSR goes active concurrently
with the MSB of the data. (In fixed data rate mode, FSR goes active one CLKR cycle before data.)
The DSP also inputs the programmed number of bits after FSR indicates the start of serial data
transmission. The polarity of CLKR and FSR are programmable, thereby eliminating one inverter
from the previous DSP interface.
4.3 AT&T DSP32IDSP32C
The DSP32 incorporates the data skewing technique utilized in the Philips I2S interface although
there is no provision for stereo. The delay is one ICK (serial data clock) cycle on the ILD pin. ILD is
a word sync as opposed to an WS signal which indicates the channel: left or right. The DSP32
accepts 32 bits, whereas the DSP32C can accept 24 or 32 bits, and both latch data on the rising edge
of ICK. As with the two previous DSPs, ILD is only used to start serial data transmission. Figure 22
shows the connection diagram while Figure 23 illustrates the timing.
5 CHANNEL INDICATION
Many systems do similar processing to both left and right channels; therefore, the DSP may not need
to know which channel it is currently operating on. The channel indication, uR, may be connected
to the ND converter and digital out or DIA converter, thereby synchronizing the input and output,
without connecting to the DSP. However, if the processing is different for each channel, the DSP
must know which channel it is operating on. As this function is only needed at initialization, an
interrupt line could be utilized, with the interrupt being disabled after synchronization is achieved.
This method requires a dedicated interrupt line which is usually in short supply. Another common
8-29
----------- -----------
Sanchez CS5328 AES Paper
method is to map UR to a memory location allowing the DSP to read that location while in the serial
port service routine, thereby determining the channel. This method requires address decode logic and
a high impedance latch to connect uR to the data bus. A third method connects r.JR to a general
purpose input pin on the DSP if any exist.
If the serial port transmitting and receiving sections are synchronous on the DSP56000 from Motorola, two pins are liberated and can be configured as serial port flags. One of these flags can be
utilized to capture ther.JR signal. As shown in Figure 19, the SCOflag is latched concurrently with
the MSB of the serial data. This flag can be tested on initialization to determine the channel.
Since all the DSP serial ports mentioned require a minimum of 24 bits, and the CS5328 is only 18
bits, 6 trailing bits are unused. If uR is appended to the serial data, the DSP could read the lower
bits which identify the channel. The DSP could subsequently mask the lower bits or ignore them
since they appear as a DC offset at a minimum of the 19-bit level. The circuit in Figure 24 appends
r.JR to the serial data stream by ORing r.JR with the zeros output after the 18-bit serial word. The
alternate circuit provides a single-chip-package implementation that multiplexes between SDATA and
r.JR. Since the CS5328 outputs 18 bits, a flip-flop is needed to delay the rising edge of the QF
(which rises after the 16th bit) until the 19th bit. A benefit produced by this configuration is that a
larger-divide output of the 74HC590 can delay the r.JR "tag" information until later bit times making
the DC offset less· significant. Figure 24 shows two configurations for adding the r.JR tag to the data.
In the "bit-19 tag" configuration, the uR tag immediately follows the data, whereas in the "bit-21
tag" configuration the tag doesn't appear until the 21st-bit position. Figure 25 illustrates timing for
the "bit-21 tag" configuration. Notice that the left channel data is followed by two zeros, then twelve
ones; therefore, the first "one" of the channel tag is in the 21st-bit position. If the DSP's serial port is
configured for 32 bits, a "bit-25 tag" could be generated by using the QE output of the 74HC590
counter as the clock input to the flip-flop.
6 CONCLUSION
The architecture and performance of the CS5328 18-bit dual channel delta-sigma AID converter were
discussed along with detailed interface and timing diagrams to AESIEBU chips, the 12S bus, and a
number of DSPs. A method of adding a channel identifier to the serial data stream was also explored.
Low input signal levels were shown not to degrade performance, and an example application using
both 18-bit channels to generate a single 19-bit part was shown to improve the dynamic range to
100 dB over the audio band.
8·30
----------- -----------
Sanchez CS5328 AES Paper
REFERENCES
[1] T.G. Stockham, Jr., "The Promise of Digital Audio," Collected Papers from the AES Premiere
Conference, pp. 12-21, New York, June 1982
[2] R. Iwashita, "Digital Audio Engineering in Consumer Audio Products in Japan," Present and
Future of Digital Audio, The Proceedings of the AES 3rd International Conference, pp. 24-31,
Tokyo, June 1985
[3] M. Richards, "Improvements in Oversampling Analogue to Digital Converters," AES preprint
N2588 (D-8) presented at the 84th convention, Paris, March 1988
[4] Roger Lagadec, "R-DAT and Professional Audio", AES preprint N2558 (A- 10) presented at
the 83rd convention, New York, October 1987
[5] D.R. WeIland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, and K.
Takasuka, "A Stereo 16-Bit Delta-Sigma NO Converter for Digital Audio," J. Audio Eng. Soc.,
Vol. 37 No.6, pp. 476-486 (1989 June)
[6] "CDB5328 Evaluation Board Data Sheet," Crystal Semiconductor Corp.
[7] S. Harris, "Dynamic Techniques Test High-Resolution ADCs on PCs", Electronic Design, Vol.
35 No. 20, September 1987, pp.109-112
[8] A.H. Nuttall, "Some Windows with Very Good Sidelobe Behavior," IEEE Trans. Acoustics,
Speech, Signal Proc., February 1981, Vol. ASSP-29 No.1, pp. 84-91
[9] G.D. Bergland and M.T. Dolan, "Fast Fourier Transform Algorithms," Programs for Digital
Signal Processing Committee; IEEE Acoustics, Speech, and Signal Processing Society; Sec. 1.2
[10] N.H.C. Gilchrist, The Subjective Effect and Measurement of A.D.C.ID.A.C. Transfer Characteristic Discontinuity," AES preprint N2394 (E-2) presented at the 81st Convention, Los Angeles,
November 1986
[11] S. Kakiuchi, H. Iizuka, M. Chijiiwa, T. Ohtsuka, "Application of Oversampling NO and D/A
Conversion Techniques to R-DAT," AES Preprint N2520 (A-9) presented at the 83rd Convention,
New York, October 1987
[12] Phillips I2S Bus Specification, Philips Components and Materials Division, February 1986
[13] Audio Engineering Society, Inc. (author), "AES Recommended Practice for Digital Audio
Engineering - Serial Transmission Format for Linearly Represented Digital Audio Data," AES31985 (ANSI S4.40-1985)
[14] M. Snelgrove, "Digital Signal Processing in Audio," 6.A, Presented at the AES 7th International Conference, Toronto, May 1989
8-31
•
----------- -----------
Sanchez CS5328 AES Paper
3.096 MHz
96kHz
384 kHz
48 kHz
AINl
AINR
Figure 1. CS5328 Block Diagram
10
0
,
,-
,
,-
-10
-20
-30
-40
-50
~
""
-60
-70
-80
-90
-, -
-100
-, -
-110
-'
" -
" -
-
J
_
,
-120
0
4
8
12
16
20
24
28
32
36
40
44
Frequency (kHz)
Figure 2. Frequency Response
Output
Word Rate
elKIN
Frequency
Passband
Edge
-3 dB
Point
32 kHz
4.096 MHz
14.5 kHz
15.6 kHz
17.3 kHz
44.1 kHz
5.6448 MHz
20.0 kHz
21.6 kHz
23.9 kHz
48 kHz
6.144 MHz
21.8 kHz
23.5 kHz
26.0 kHz
Table 1. Audio Output Word Rates
8-32
Stopband
Edge
48
--- -------------------
Sanchez CS5328 AES Paper
0.0010 - , - - - - , - - - - - - - - - - - - - - - - - ,
-10
0.0008
!g
0.0006
-20
0.0004
-30
0.0002
-40
~
0.0000
-50
-0.0002
-60
-0.0004
-70
-0.0006
-80
-0.0008
-90
-100 -j------t---t------tc----t---t-----t---t'-'-"----j
22.50 23.00 23.50 24.00 24.50 25.00 25.50 26.00 26.50
-0.0010 -j--t---t--t---t------t-+--t-----t----t---t-----'t----j
10
12
14
16
18
20
22
24
Frequency (kHz)
Frequency (kHz)
Figure 4. CS5328 Transition Band
Figure 3. CS5328 Passband Ripple
-10
-10
Dynamic Range
-20
-30
-40
-50
24kHz BW:
22kHz BW:
20kHz BW:
-30
-40
95.3 dB
96.2 dB
96.9 dB
-50
-60
~
Dynamic Range
-20
93.7 dB
22 kHz BW:
94.5 dB
2Q kHz BW;
95.2 dB
SID: 101.4 dB
24kHz BW:
-60
-70
~
-80
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
Frequency (kHz)
Frequency (kHz)
Figure 5. CS5328, Full Scale Analog Input
Figure 6. CS5328, -tOdB Analog Input
100
-10
-30
-40
-50
24kHz BW:
22kHz BW:
95.5 dB
20 kHz BW:
97.1 dB
BO
1 kHz
10kHz
96.4 dB
c
.70
20kHz
.1.
~
""en
-60
~
+
90
Dynamic Range
-20
-70
-80
-90
60
50
40
30
-100
-110
20
-120
~
10
-130
-140
0
-100
Frequency (kHz)
Figure 7. CS5328, -80 dB Analog Input
'"
-90
-80
-70
-60
-50
-40
-30
-20
-10
o
Signal Level
Figure 8. Signal-to-Noise vs. Signal Level
8-33
----------- -----------
Sanchez CS5328 AES Paper
P-JVV\r--+--t AINL
A
o
CDB5328
AIN
_ _~ 19 bits
o
E
R
D-"WI.--.....---I AINR
Right Channel
Figure 9. 19-Bit Hardware Configuration
-10
-10
-20
-30
,
-40
,
-50
c
Dynamic Range
24kHz BW:
22 kHz BW:
20 kHz BW:
SID:
98.6 dB
99.5 dB
100.2 dB
97.9 dB
-30
-40
98.6 dB
99.5 dB
100.2 dB
-
-60
-70
!1l
-70
-60
-80
-90
-90
-100
-100
·110
-110
-120
-120
-130
-130
-140
-140
Frequency (kHz)
Figure 10. 19-Bit FFT, -10dB Analog Input
8-34
24kHz BW:
22 kHzBW:
20kHz BW:
-50
-60
!1l
Dynamic Range
-20
Frequency (kHz)
Figure 11. 19-Bit FFT, -60dB Analog Input
,-
----------- -----------
Sanchez CS5328 AES Paper
Anti-Alias Filter
Timing
11th-Order
Chebyshev
96kHz
Digital
Processing
System
11th-Order
Chebyshev
a. Traditional Approach
Timing
Anti-Alias Filter
7th-Order
Butterworth
Digital
Processing
System
7th-Order
Butterworth
-
b. 2x Oversampling
Anti-Alias Filter
::r::
AINl
AINR
SClK
LlR
ClKIN
Digital
Processing
System
SDATA~____9_6_kH_Z______~
CS5328
c. 64x Oversampling
Figure 12. Analog Front End
8-35
.. _.-.
_.-_..--_
__..--_
....
Sanchez CS5328 AES Paper
Transmitter
Controller = Master
ClKIN
ClKIN
,.
74HC590
----
j>CCK
CS5328
~
'---- j>RCK %
+2
SClK
SDATA
,------
+ 128:
UR
- ,
,-
'--- D Q -
~
WS
SCK
SD
Receiver
SCK
WS
~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
so
32nd bit (lSB) of
right channel word
J:
32 bit left channel
.....f - - - - - - - - 18 data, 14 zeros - - - - - -.........-'
Figure 13. Philips 12S Bus
8-36
32 bit right channel
----------- ----------ClKIN
Sanchez CS5328 AES Paper
n
CS5326
74HC590
L-., ClKIN
-------0;\ T 2
f---
'------
CCK
L--o- RCK
-
-----t::
SClK
-
OF ~
°G
.... 128
BCK
SDATA
CX230331
CXD1211
UR
Ln
lRCK
°
UR
EXTAl
DATA I DATA.DATS
~r--------------------------~I~I-----'L-______________________~
SCK
DATA
.-____~I,~J------------------------------,
~
lRCK
Figure 14. Sony Digital Interface, 16-bit Format
ClKIN DI}_--------------------------------_---------------------.
CS5328
74HC590
QA :2
~EXTAl
'------ ClKIN
'--------IBCK
CX23033/
CXD1211
r------g~~~~~~ ----------<~lRCK
,---------. DATA I DATA,DATB
MUX
5R
D~l~~:~
~
DQ
~R~
Q
Q
:
- - - - - - - - - -
-n
T74HC299
T74HC299
I 74HC299
~~A' S2S1~t=J~A' S2S1~t=J~A' S2S1~t:
D
Qr---__l-t--I--__l~t_I---'I
Q~--~l----_--l--~
Figure 15. Sony Digital Interface, 24-Bit Format
8-37
III
_-_
.. ...
._.-.
-.-_
..--__
Sanchez CS5328 AES Paper
CS5328
SDATA
•
Left Data - MSB First
- - - - - - - - - - - - -. - - - - - - - -
~
....
,..
-- -- --
, - - - - -1
A
-
~
24-Bit Shift Register
-
-
-
-
~
-
-
I
~
-' - - - - - - -'
~
H
"
Shift Direction
•
°A'
°H'
{
- - - - - - - - - ,
- - - - - - - - - - - - - ____
,
, -
CX230331
CXD1211
Right Data - LSB First
"
~
L
~"
R
L.
MUX
Right Data - LSB First Ih.
JV
DATA
a. First Chaimel
CS5328
SDATA
Right Data-MSB First
'-::::::: :::::: -::: ~~~~~
',- - - - , A
"
24-Bit Shift Register
H
Shift Direction
CX230331
CXD1211
Left Data-LSB First
L
R
Left Data-LSB First
I
DATA
MUX
b. Second Channel
Figure 16. Sony Interface Serial Data Flow
8-38
--- ------------------UR
Sanchez CS5328 AES Paper
~
LEFr CHANNEL: N
SDATA
SCLK
BCK
DATA
LRCK
UR
LEFr CHANNEL: N+I
RIGHT CHANNEL: N
SDATA
JsJ4JaJ2J1JoJZJZJzJzJzJz
SCLK
BCK
RIGHT CHANNEL: N
LEFr CHANNEL: N
DATA
LRCK
Figure 17. Sony Digital Interface Timing Diagram, 24-bit Format
CLKIN
-
CLKIN
74HC590
------~
>CCK
0
CS5328
:2
SCLK
SCLK
A
OF
>RCK
%
~SYNC
,---
+128
r
SCQ
SDATA
UR
SC2
SCK
SRD
or
SC1
DSP5600011
Figure 18. DSP56000 Connection Diagram
8-39
-.---------- ---
_ _ _ _i'- ___ _
Sanchez CS5328 AES Paper
SCK
SRD
SC2
(FSYNC)
I',
---.l
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
sea
UR
I:
~
sea
~~!-------------------------------------,I~I----------~
Figure 19. DSP56000 Timing Diagram
ClKIN
ClKIN
CS5328
74HC590
..-- >CCK
--
SClK
:2
0
SClK
A
OF
>RCK
%
.;-64
- - SDATA
.;-128
UR
FSR
ClKR
DR
TMS320C30
Figure 20. TMS320C30 Connection Diagram
ClKR
DR
FSR
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Figure 21. TMS320C30 Timing Diagram
8-40
----------- -----------
Sanchez CS5328 AES Paper
CLKIN
CLKIN
CS5328
74HC590
:2
0
r-
CCK
SCLK
A
... 64
OF ~ >RCK
-
SDATA
... 128
%
UR
-- °
-
D
t-------
-
~
ILD ICK
DI
DSP32
Figure 22. DSP32 Connection Diagram
-
ICK
ILD
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
DI
Figure 23. DSP32 Timing Diagram
8-41
------------"----------
Sanchez CS5328 AES Paper
ClKIN D - . - - - - - - - - - - - - - - - - - - - - - - - - - - I C l K I N
74HC590
r=-"=~Q~Al'~~2~-------__l
CS5328
; ; o - - - - - - - - - - - - . j SClK
CCK Ocf"~",,"8_ _--.
QD ~16
RCK
a
SDATA
r-----t~~
~64
UR
F
QG ~128
bil-191ag
bit-21 tag
""'~
'+5
.... FSYNC
,
UR
Alternate Circuit
Figure 24. Channel Tag
FSYNC
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
FSYNC
UR
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _
~
a. Left Channel
IL______________________________________~
b. Right Channel
Figure 25. Channel Tag Timing Diagram (bit-21 tag)
8-42
.
'
DSP_DATA ' , ,
----------------------
Weiland AES Paper
A Stereo 16-Bit Delta-Sigma AID Converter for
Digital Audio
D. R. Weiland, B.P. Del Signore, E. J. Swanson
Crystal Semiconductor Corp., Austin, TX 78744, U.S.A.
AND
T. Tanaka, K. Hamashita, S. Hara and K. Takasuka
Asahi Kasei Microsystems, Inc., Tokyo, Japan
A two channel 16-bit AID converter employing oversampling techniques has been
developed. The device contains two fourth order delta-sigma modulators with I-bit
outputs, each followed by a digital finite impulse response filter/decimator. The analog inputs are sampled at 3.072 MHz and the digital words are output at 48 kHz.
o. INTRODUCTION
The emergence of digital audio has increased
the demand for high performance NO converters.
Delta-sigma conversion has been gaining recognition as having advantages over more classical
audio band conversion techniques. In particular, it
obviates the need for sample and hold amplifiers,
eases the design of anti-aliasing filters, and is free
of differential non-linearity errors that distort low
level signals.
This paper discusses the development of a two
channel 16-bit audio band delta-sigma converter
featuring a high degree of integration and suitable
for use in stereo digital audio applications. Section
I gives an overview of the concepts pertaining to
delta-sigma conversion. The device architecture
and a functional partitioning strategy are presented
in Section 2 Sections 3 and 4 discuss design of
the two major functional blocks, and measured results are presented in Section 5.
1. DELTA-SIGMA CONVERSION
1.1 Quantization Noise
Analog to digital conversion is a process that
necessarily introduces errors into a signal due to
quantization. The difference between the output of
an otherwise perfect converter (or "quantizer")
and that which might be expected of a converter
with unlimited resolution can be modeled as an
additive noise signal. The level of this "quantization noise" is reduced in converters of higher
resolution with finer quantization levels, but nonetheless must remain non-zero. If the analog input
is sufficiently large and/or if the input is sufficiently random, the spectrum of the quantization
noise can be approximated as white [1] with its
energy equally distributed between dc and fsl2,
where fs is the sampling and conversion rate (it is
assumed the signal is sampled before it is converted). The effective resolution of a converter can
be increased by filtering the output and thereby
reducing the level of the quantization noise. A
commensurate reduction in the available signal
bandwidth must be accepted as a consequence of
the filtering, but may prove acceptable if the conversion rate is high. The sampling and conversion
of a signal at a rate much higher than the signal
frequency is a technique termed "oversampling".
The "oversampling ratio" is the ratio of the actual
sampling rate to the Nyquist rate (i.e., twice the
highest signal frequency of interest).
This process is illustrated in Figure 1, where
an analog sinusoid of frequency fo is converted to
a digital, quantized sinusoid at a rate fs by a linear
Reprinted from Journal of the Audio Engineering Society, Vol. 37, No.6, June
8-43
-
_.-_..--_._.
__.._-_
...-.
Weiland AES Paper
pulse-code modulation (PCM) converter. The input spectrum is shown in Figure lA, and Figure
lB shows the effects of the quantization process
with the addition of white noise (this and following spectra repeat at multiples of fs, of course, due
to the discrete time nature of the sampled signal).
Processing by a digital filter with a baseband cutoff
frequency of fb as illustrated in Figure lD yields the
output spectrum in Figure IE. The baseband cutoff
frequency fb is presumed to be equal to the highest
signal frequency of interest. The remaining quantization noise voltage level will be lower than the
original level by a factor of sqrt(fsl2fb) (the quantization noise energy is lowered directly by the
oversampling ratio fsl2fb).
The utility of this technique when applied to
audio signals with a baseband frequency of
Is
1
fb = 20kHz is questionable. To obtain the equivalent of l6-bit performance from, say, a l2-bit
converter, the l2-bit quantization noise would
have to be lowered by 24=16. This would in tum
require an oversampling ratio of fsf2fb = 256, or
f s=lOMHz.
Delta-sigma conversion is a technique that
employs oversampling to obtain high resolution
(low quantization noise) digital signals from low
resolution (high quantization noise) quantizers. As
will be shown below, the delta-sigma converter
contrasts with the previous example in that the
quantization noise at the output of the low resolution quantizer is not white, but rather frequency
"shaped", such that noise in the baseband (ffb) noise. The power of digital filtering
can then be applied to the resultant spectrum to
pass the signal (and the residual baseband quantization noise) while rejecting the out-of-band
quantization noise.
AID
Converter
Analog
a. PCM Converter
t
I
10
b. Input Spectrum
='_'
t
Digital
Is/2
I
H(I)
Analog Filter
10
Is/2
0_' ',,,,rum
U
I
10 Ib
Is/2
e. Filter Output Spectrum
Figure 1. Increasing Resolution with Filtering
8-44
The converter consists of a modulator and a
digital filter. As can be seen in Figure 2, embedded in the modulator is the low resolution N-bit
quantizer, around which frequency dependent
feedback is applied by means of aN-bit DAC and
an analog filter. The analog filter has a frequency
response of H(f). The analog input is summed into
N-Bit
DAC
u
Digital
Output
(To Digital Filter)
Figure 2. Delta-sigma modulator
.-_
_
..--_._.
__.._-_
...-.
Weiland AES Paper
The modulator output signal y is a function of
the analog input x and quantization noise q, as follows:
y
= (x-y) H(f)g + q
Y [1 + H(f)g] = xH(f)g +q
H(f)gx
q
Y 1 + H(f)g + 1 + H(f)g
=
If the loop gain H(f)g »1, then
Digital
Output
(To Digital Filter)
q
y ::x
I
1
H(f)g q
Quantizer
Figure 3. Linearized delta-sigma modulator
the modulator loop at a point where, for frequencies with high loop gain, the output of the DAC
will be substantially equal to the input. To the extent that the DAC faithfully reproduces the
quantizer digital output, this signal, too, must be
substantially representative of the analog input
again, for frequencies with high loop gain.
1.2 Loop Analysis
The presence of the non-linear quantizer renders exact analysis of the loop difficult. A typical
and useful approach is to linearize the quantizer
by replacing it with a gain stage and a quantization noise source [2]. Again, the latter is only a
contrivance to account for the difference between
the quantized output and the amplified input. This
is illustrated in Figure 3. The DAC has been replaced by a unity gain stage, as its function is
irrelevant for analyzing the effects of quantization
noise. Note, though, that non-idealities in the
DAC can be the chief limitation to the modulator's performance [3].
The actual value of the gain g and the rms
value of the quantization noise signal q need not
be known to obtain an understanding of how the
modulator shapes the quantization noise. It must
be assumed, hnwever, that successive values of
the quantization error are uncorrelated - i.e., the
quantization noise spectrum is white. The validity
of this assumption is borne out empirically.
That is, the output will be the sum of the input
and the quantization noise spectrally shaped by
the inverse of the analog filter frequency response.
A glance at the approximate expression for y
may lend hope to the prospect of reducing quantization noise by increasing the value of H at all
frequencies. However, the effective value of g
would change to compensate such a maneuver.
Reducing q by introducing a higher resolution
quantizer would indeed offer improved performance. But the most effective method of achieving
lower baseband quantization noise (for a given
oversampling rate) is the selection of filter function H(f) that possesses high in-band gain and
high out-of-band attenuation, thereby shaping the
quantization noise spectrum advantageously. Note
that the poles of the filter are zeros of the noise
transfer function.
1.3 Integrator
A simple integrator has the desired spectral
qualities for a filter. A cascade of two integrators
would appear more attractive, and indeed such a
"second order" filter more effectively shifts quantization noise to out-of-band frequencies than the
"first order" filter. Extension to higher order filters is problematic, though, due to stability
considerations. A second-order design requires
the placement of a single zero in the filter response to obtain a well-behaved modulator.
8-45
-
.---------- ----------Higher- order filters can also have zeros included
as an aid to stability, but even so they are conditionally stable due to the high phase shift at
baseband frequencies. Conditionally stable loops
can become unstable if a frequency independent
gain parameter in the loop is reduced. The effective quantizer gain g is such a parameter and is
subject to change under varying operating conditions. As such, stability of modulators with third
and higher order filters is at risk. Nevertheless, the
attractiveness of higher order filters has led to a
number of solutions to the stability problem
[4],[5]. The device discussed in this paper utilizes
a fourth-order filter. Stability will be discussed below.
Weiland AES Paper
I
Signal
Quantization Noise
I
Is
Ib
Is
1s/2
a. Modulator Output
llr\flr-tr
Is'
~2fb~
215'
~
315'
~
~
15/2
~
~
~
b. Filter Response
Another approach that leads to performance
similar to higher-order modulators without the attendant stability question has been reported [6].
This architecture has cascaded lower order modulators, with successive modulators measuring the
residual in-band quantization noise of previous
modulators. The various modulator outputs are
digitally processed to lower overall in-band noise.
However, accurately matched components and
high gain integrators are necessary to achieve the
desired performance.
Is
Ib
c. Filter Output
Is'
1.4 Filtering and Decimation
Once the quantization noise has been appropriately shaped, it remains the task of the digital
filter to remove the out-of-band quantization
noise. A straightforward approach of synthesizing
a low pass filter with sufficient stop-band attenuation and acceptable pass-band response would
prove inefficient. Instead, a strategy of staged filtering and decimation can be adopted to ease the
computational burden [7]. Decimation is the process of sampling a discrete time signal at a rate
lower than its own. The advantage of decimation
is that signal processing after decimation can proceed at the lower rate. As a sampling process,
though, decimation is subject to the ill effects of
aliasing.
8-46
klr\f\f\f
t
k:::
Ib
d. Decimated Filter Output
1s/2
~
Is'/2
Figure 4. Filter Strategy
In this application, each stage of filtering need
only reject signals that will be aliased into the
baseband by the immediately subsequent decimation process, since later filter stages will reject
signals aliased elsewhere. Figure 4 illustrates this
approach. A signal with a spectrum characteristic
of a modulator output signal is input to a filter at
a rate fs. The output of this filter is to be deci-
----------- ----------mated to a new rate fs', where fs = Nfs', before
being processed further. Aliasing will occur
throughout the spectrum, but only components
within ±fb of integer multiples of fs' will get aliased into the baseband. A filter designed to have
rejection only in these frequency "pockets" requires much less computation than one with
rejection across the entire stop-band. As the sampling rate gets lower, of course, the pockets
become proportionately wider and the filters become more complex. However, they can proceed
with their computations at a more leisurely pace.
The final filter stage, operating at the slowest
rate, can be a true low pass filter, eliminating the
accumulated out-of-band quantization noise. In
addition, it can "tweak" the frequency response of
the pass-band if previous filter stages, the modulator, or even analog processing prior to the
modulator have warped the response.
The need to reject the out-of-band quantization noise also represents a benefit. Namely,
signals outside the baseband up to half the modulator sampling frequency do not get aliased by the
modulator and are rejected by the digital filter. Indeed, spurious input signals approaching the
sampling frequency do not get aliased into the
baseband unless they are within ±fb of fs, and are
likewise rejected. This characteristic can greatly
relax analog anti-aliasing requirements and, for
some applications, stands as one of the leading
benefits of delta-sigma conversion.
2. ARCHITECTURE
2.1 Overall Architecture
The device described in this paper contains
two delta-sigma converters suitable for stereo
digital audio applications. It is packaged in a 28
pin dual-in-line package with a standard 0.600
inch wide footprint. The cavity of the package is
occupied by two silicon dice. One die contains the
two modulators, a voltage reference (the value of
which determines full scale signal level), clocking
circuitry, and a small amount of digital house-
Weiland AES Paper
keeping circuitry. The second die contains the
digital filter/decimators.
2.2 Reasons for Two Die
Partitioning of the system in such a fashion
was motivated by the following considerations:
1) The complexity of the digital filter necessarily creates a large amount of electrical noise
during normal operation. Placing this circuitry on
a silicon substrate separate from the modulators
eases the task of preventing this noise from interfering with the modulators' analog signal
processing.
2) The great majority of the silicon area is occupied by the digital filter/decimators, and the
manufacturing cost is dominated by this circuitry.
Shrinking of the geometries comprising this circuitry as the product matures can lead to cost
reductions without affecting performance. Shrinking of analog circuitry is risky and difficult;
hence, the advantage of removing this circuitry
from the more cost-sensitive digital die.
3) With separate die, different processes can
be used to fabricate the analog and digital portions
on the converters.
Regarding the last item, the digital die is
manufactured using a standard 5V, 2 micron double-metal digital CMOS process. A lOY process
was chosen for the analog die to allow more headroom for the analog signals. CMOS was chosen to
support the switched capacitor design discussed in
the next section. The selected process has 3 micron line widths, double polys iii con layers for
capacitors, and a single metal layer.
2.3 Shared Functions
To a large extent, the two channels function
independently. However, some circuit blocks are
shared. On the analog die, all clocking is common
between the two channels to facilitate simultaneous sampling of the left and right channel signals.
Additionally, a single voltage reference circuit is
utilized by both channels. The voltage reference
8-47
-
___-_
.. ...-.
.-_--_.-.
....
employs both lateral and vertical bipolar npn transistors (both of which are useful parasitics in this
process) in a bandgap configuration. Its output is
connected to a pin so that it can be capacitively
bypassed to reduce crosstalk between the two
channels. This capacitor and two simple RC antialias filters are all the external elements required
of the device other than standard power supply
decoupling elements.
The two digital filter/decimators also have
common clocking. The various filter coefficients
are stored in a single ROM which is accessed by
both right and left channels.
3. MODULATOR
3.1 Major Characteristics
The major characteristics that need be determined in the design of a delta-sigma modulator
are filter technology, oversampling ratio, quantizer
resolution, and filter order.
3.2 Discrete Time Implementation
Although continuous time filters can be employed in the implementation of a delta-sigma
modulator (sampling occurs at the quantizer only),
three considerations dictated the choice of sampled data filters for use in the product. First is the
ease with which sampled data filters can be integrated in comparison to continuous time filters.
Second is that continuous time filters are sensitive
to timing errors in the feedback of the modulator's
DAC signal [3], whereas sampled data filters are
not. Third, with proper design care sampled data
circuits can provide greater isolation between
channels in a stereo application since signal currents are transient. They can be made quite small
at the sampling instances and are of no consequence at other times (both technologies are
subject to capacitive crosstalk). Thus, sampled
data switched capacitor technoiogy was chosen for
the design of the modulator.
3.3 Oversampling Ratio
8·48
Weiland AES Paper
The overs amp ling ratio is limited by the
achievable settling time of analog components as
well as the maximum computation rate of the
digital filter. It is also preferable that the oversampIing ratio be a factor of 2N to ease applications.
With a standard baseband of 24kHz, the oversampIing ratio of 64 was chosen for a sampling rate
of 3.072MHz. In a switched capacitor network
each cycle is divided into two phases. With design
margin, all modulator circuit blocks were designed
to settle in lOOns to 0.1%.
3.4 1·bit Quantizer
As was mentioned in Section 1, higher resolution quantizers embedded in the modulator loop
yield lower levels of in-band quantization noise.
However, a I-bit quantizer (i.e., a comparator) is
simple to implement and minimizes the number of
connections between the modulators and their
digital filters. More importantly, a very attractive
attribute of the use of a I-bit quantizer is that errors in the I-bit feedback DAC are not sources of
distortion andlor excess noise, but only gain and
offset errors [8]. Therefore, no precision components are necessary. Further, a one bit output
simplifies the design of the first (and highest
speed) digital filter stage.
3.5 Modulator Filter Order
The selection of a I-bit quantizer operating at
an oversampling rate of 64 requires at least a third
order modulator filter to obtain I6-bit performance at the digital filter output. The addition of
other noise sources (e.g., quantization effects in
the digital filter) eliminated the candidacy of a
third order filter. A fourth order modulator filter
comprised of four cascaded integrators would provide sufficient rejection. of baseband quantization
noise. However, the modulator's baseband quantization noise can be rendered insignificant by
optimization of a fourth order filter, as follows.
In Section 1 it was noted that the poles of the
modulator filter are the zeros of the quantization
noise transfer function. A filter with four cascaded
----------------------
Weiland AES Paper
integrators results in a noise transfer function with
four zeros at dc. Lee and Sodini [9] found that
spreading these zeros by application of local feedback around the integrators was effective in
lowering the total baseband quantization noise
output by the modulator. Optimal placement of all
four zeros (two conjugate pairs) results in an lldB
improvement in baseband quantization noise rejection. Optimal placement of a single conjugate
pair with two zeros left at dc results in a 10dB
improvement.
Implementation of the two-conjugate-pair filter requires feedback to the input summing
junction. This requirement has associated undesirable consequences (PSRR degradation, for
example) and the two pair configuration offers little additional noise shaping improvement above
the single pair. So, the single conjugate pair configuration was adopted.
3.6 Modulator Design
Figure 5 is a block diagram of the modulator.
Coefficient b is fed back around the third and
fourth integrators to form the conjugate pair of
poles in the filter transfer function. The analog input is represented by x, and the single bit digital
output is y (which is inverted and summed with x
in analog form). The feedforward coefficients aj
through 34 are necessary (although not sufficient)
for stable operation. The value of one coefficient
is arbitrary. The value of the other three coefficients determine the location of filter zeros, but
the effect of these on modulator operation is not
easily predictable. Higher ratios of aj to 34 lead to
more stable, noisier operation.
3.7 Stability Considerations
As was mentioned in Section 1, low values of
the "effective gain" of the quantizer (in this case
comparator) g can lead to instability. Since the
output levels of the comparator are fixed, and
since in an unstable mode the integrator output
levels can be expected to grow, any linearization
criterion for evaluating g should lead to an ever
-
b
y
Figure 5. Modulator Block Diagram
8-49
-_--_._.
_-_
.. ......,.
. _..,
.....
Weiland AES Paper
decreasing value. Similarly, it would not be unreasonable to expect that large values of the input
would lead to small effective values of g, initiating instability.
Simulation and laboratory experience has
shown that the modulators do indeed exhibit this
behavior. Fortunately, stable regions of operation
also exist. The strategy adopted in the design of
these modulators is to allow normal operation
only well within the stable state space. Circuitry is
provided to detect excessively high integrator levels as an indication of unstable operation. If such
levels are detected, the integrators are reset to a
stable condition. In practice, the reset circuitry is
never utilized except at power-up (whereupon the
modulator filter mayor may not be in a stable
state) or during periods when the input is excessively high. "Excessively high" means much
higher than full scale, in which case the converter's digital output would be clipped and
occasional modulator resets would be of no consequence. As the input returns to a level near full
scale, the latest reset event leaves the modulator in
a stable state.
Figure 6 shows. a typical spectrum of a simulated modulator including a sinusoid input signal
(very close to dc on the linear frequency scale)
plus the quantization noise from dc to fsl2. An
expansion of the low frequency portion of this
figure is shown in Figure 7. Here, the effect of
the conjugate pair of quantization noise zeros is
evident, as well as that of the pair at dc.
4. FILTERIDECIMATOR
4.1 Overall Architecture
Linear-phase finite-impulse-response (FIR)
filters are used for decimation. The 1-bit,
3.072MHz outputs of the modulators are decimated in steps of 8, 4, and 2 to yield 16-bit,
48kHz results. A functional block diagram of the
digital die appears in Figure 8. Timing, control,
and coefficient ROMs (FIR2 and FlR3) are shared
by the two channels. Left and right channel data
paths operate independently. FIR2 and FlR3 use a
per-channel multiplier/accumulator.
3.8 Measured Spectra
IdB)
10
-5
-20
-35
-50
-65
-60
i
-95
-110
-125
-140
1.0
IN)
16384.0
Figure 6. Simulated modulator output spectrum
8-50
Figure 7. Expanded simulated modulator output
spectrum
_.-_..--_
__.._-_
...-..
Weiland AES Paper
input signals - into the converter noise floor. Filter orders are 27 and 30, respectively. Data is
processed with 18-bit fixed point arithmetic.
96kHz
384kHz
Figure 8. Filter/decimator block diagram
4.3 Passband Shaping
FIR3 performs passband shaping and out-ofband signal attenuation. Passband frequency
response errors introduced by the modulator,
FIR 1, and FIR2 are corrected by FIR3. Overall
filter passband ripple is thus reduced to ±o.OOldB
from dc to 22kHz. The passband compensation
function prevents the use of a half-band filter for
FIR3. The filter has 124 non-zero, I8-bit coefficients. Again, data is processed with I8-bit fixed
point arithmetic. Data is truncated to 16 bits at the
output, and this operation is the major noise contributor in the system.
4.2 Decimation
The decimation strategy includes two stages,
FIRI and FIR2, whose primary responsibility is
attenuation of quantization noise prior to decimation and aliasing. As Figure 6 shows, modulator
out-of-band quantization noise spectral density is
very high. FIRI and FIR2 use 17 and 18-bit coefficients to attenuate this noise - and out-of-band
4.4 Antialiasing Filtering
As indicated in Section 1, FIR 1, FIR2, and
FIR3 also combine to provide antialiasing filtering. All analog input frequencies from 26kHz to
3046kHz are attenuated by at least 86dB. The
magnitude response of the complete modulator/decimator from dc to 48kHz is shown in
Figures 9 and 10. Phase response is precisely linear.
Output
Logic
Serial
Data
Clock
III
0.0010,----,-----,---------.----;----,-----,
10,-----.----,---,---,--,-----,
O+--~-~--....,-
CD
0.0005
,
,
,
- -, - - - - , - - - - , - - -
~
Q)
"0
:E
c:
0.0000
16'
~
-0.0005
-0.0010 ±-----t---:t----:;1:::----:-r.:------;±----L---::l
Input Frequency (kHz)
Figure 9. Filter passband ripple
- - -,- - - -" - --
-10 - - - -" - - - - - - - - - - - - I
- - -,
- - - - -20
CD -30
~ -40
{l -50
~ w60 - - - - - - - - - - - - - - - - - - - - - - 16' -70
~ -80
,
,
,
-90 - - - - - - - - - - - - - -100
,
-110 - - - -, - - - - , - - - --120 - - - -, - - - -, - - - -,-130 ±---------;1t::S------=2r:4 -----::t::--'---'----:t:---"---:I
I
,
I
I
,
I
,
,
,
,
Input Frequency (kHz)
Figure 10. Filter frequency response
8-51
----------- -----------
Weiland AES Paper
Averages: 10
S/(N+D): 92.9dB
OdB"--------------------------,
PrgM: HFFTO.8
Date: 8/31/88
Avgs: 1888
dB
Pal't: 5326.
-18
-28
·20dB
-38
·40dB
Signal
-48
~~~::~ed7o·S0dB
-68
Full Scale
-78
-5B
·80dB
-BB
-18B
-11.8
-12H
·120dB
24
de 5
48
9S
Input Frequency (kHz)
Figure 11. Partial 16K point FFT of modulator output
5. RESULTS
5.1 Modulator Output
Testing of the key specification parameters
was performed with the aid of Fast Fourier Transform (FFT) routines. Figure 11, for instance,
shows the low frequency portion of an FFT performed on a modulator's single bit output. The
quantization noise shaping is evident in this plot.
Absent, however, is the null due to the conjugate
pair noise shaping zeros that is visible in Figure 6.
The quantization noise of the modulator is masked
iil
o
100,-----~----~----~----~----~
80
12
~ 60
+
1 kHz
o
10 kHz
020 kHz
+
OT-----~-----r-----r----_r----
-80
-60
-40
-20
Input Signal Level (dB)
Figure 13. Signal-to-noise ratio versus signal level
8-52
de
24.B kHz
Figure 12. 1000 averaged FFTs of AID converter
by the device's more classical noise mechanisms.
Quantization noise can only be seen rising out of
the thermal noise floor at frequencies above the
audio band.
5.2 Digital Filter Output
Figure 12 shows a plot of the result of an average of one thousand FFT's performed on the
16-bit words output by the digital filter. Averaging
of numerous FFT's serves only to cosmetically
smooth the noise floor and does not change the
ratio of the signal to noise level. The width of the
fundamental is due to the application of a low
side-lobe window to the data stream [10].
In addition to the noise floor and the fundamental, dc and harmonic distortion components
are visible. Close inspection reveals a lIf noise
comer in the area of 300Hz and a bump in the
noise floor in the area of 23kHz. The latter is
caused by the rising modulator quantization noise
in concert with the falling digital filter characteristic.
o
-100
··································1
-98
·100dB
:s.
c
S/N+D: 93.22 dB
SID: 9B.24 dB
S/PN: 181. 6 dB
o
Figure 13 is a plot of measured signal-to-noise
plus distortion ratio versus signal level for 1kHz
and 10kHz input frequencies. High-level performance appears slightly better for the 10kHz signal
because all but the second-harmonic distortion
components fall outside the baseband.
.._-_
_.-_..--_._.
-_
...-.
5.3 Specifications
Table 1 lists the key specifications and their
measured values.
64X
92 dB
94 dB
<0.001 dB
>86 dB
5 LSB
-103 dB at
20kHz
Channel-to-channe1 gain mismatch 0.04 dB
Gain temperature coefficient
80 ppmfOC
PSRR
50 dB
450mW
Power dissipation
Oversampling ratio
Signal-to-noise plus distortion
Dynamic range
Filter passband ripple
Filter stop-band rejection
Calibration error
Channel-to-channel crosstalk
Weiland AES Paper
[7] RE. Crochiere and L.R. Rabiner, "Interpolation and Decimation of Digital Signals -- A
Tutorial Review," Proc. IEEE, March 1981, vol.
69 no. 3, pp. 300-331.
[8] M.W. Hauser and RW. Brodersen, "Circuit
and Technology Considerations for MOS DeltaSigma AID Converter," ISCAS Digest, 1986.
[9] w.L. Lee and C.G. Sodini, "A Topology
for Higher Order Interpolative Coders," ISCAS
Digest, 1987, pp. 459-462.
[10] A.H. Nuttal, "Some Windows with Very
Good Sidelobe Behavior," IEEE Trans. Acoustics,
Speech, Signal Proc., February 1981, vol. ASSP29 no. 1, pp. 84-91.
REFERENCES
[1] A. Gersho, "Quantization," IEEE Commun.
Society Mag., September 1977, vol. 15 no. 5, pp.
20-29.
[2] S.H. Ardalan and lJ. Paulos, "An Analysis
of Non-Linear Behavior in Delta-Sigma Modulators," IEEE Trans. Circuits and Systems, June
1987, vol. CAS-34, pp. 593-603.
-
[3] R W. Adams, "Design and Implementation
of an Audio 18-Bit AID Converter Using Oversampling Techniques," 1. Audio Eng. Soc., March
1986, vol. 34 no. 3., pp. 153-166.
[4] R W. Adams, "Companded Predictive
Delta Modulation: A Low-Cost Conversion Technique for Digital Recording," 1. Audio Eng. Soc.,
September 1984, vol. 32 no. 9, pp. 659-672.
[5] Gould Electronics Technical Notes,
0141A0860.
[6] Y. Matsuya et.al., "A 16-bit Oversampling
AID Conversion Technology Using Triple-Integration Noise Shaping," IEEE 1. Solid State Circuits,
December 1987, vol. SC-22 no. 6, pp. 921-929.
8-53
_.-_..--_._.
__.._-_
...-.
Weiland AES Paper
eNotese
8-54
----------------------
Harris Jitter AES Paper
The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,
and on Oversampling Delta Sigma ADC's.
Steven Harris
Crystal Semiconductor Corporation
4210 South Industrial Drive
Austin, Texas, 78744, USA
An earlier version of this paper was presented at the 87th Audio Engineering Society Convention,
New York, October 1989. This paper is reproduced from the July 1990 issue of the Journal
of the Audio Engineering Society.
Abstract
Sampling clock jitter is inevitable in a digital studio environment. This paper discusses the audio effects of clock jitter on an Analog-to-Digital Converter (ADC). The clock jitter sensitivity of a
conventional Nyquist sampling ADC is compared and contrasted to that of a 3 MHz 64X oversampIing delta sigma ADC.
o INTRODUCTION
The increasing density of digital equipment in studios has prompted much discussion on synchronization of multiple items of digital audio equipment. The distribution of a master clock, for example via
the AESIEBU interface, will inevitably add jitter to the clock. Each item of digital audio equipment
that contains an analog-to-digital converter (ADC), or a digital-to-analog converter (DAC), will require a stable sampling clock, which is frequency locked to the distributed master clock. This paper
investigates the amount and nature of jitter that an ADC can tolerate.
Included in the paper are a theoretical analysis of the effect of clock jitter on the sampling process, the
results of a computer simulation, and measured results taken from actual ADC's with deliberately jittered clocks. Different types and amplitudes of jitter are investigated. In addition, the jitter sensitivity
of a 76.8 kHz sampling ADC is compared and contrasted to that of a 3 MHz oversampling delta sigma
ADC.
Journal Audio Engineering Society - July 1990
8-55
-
-------,-,--------------
Harris Jitter AES Paper
1 Clock Jitter Theory
The effects on ADC performance of jittering the sampling clock bear a strong resemblance to classical
FM modulation. The input frequency is equivalent to the carrier frequency, and the clock jitter frequency (or spectrum) is equivalent to the modulation frequency. For simplicity of initial analysis,
consider an ADC with a sine wave input signal, and a sampling clock time modulated Gittered) by a
low frequency sine function. If a record of data is taken from the ADC and analyzed using Fourier
analysis, then the effect of the clock jitter is to reduce the height of the input sine component, and to
introduce sideband frequency components. The sideband frequencies are equally spaced either side of
the input component, at a distance equal to multiples of the jitter frequency. The amplitude of the sidebands varies with the amount of clock jitter. However clock jitter is not precisely FM modulation;
there are some important behavioral differences. The equation for sinusoidal sampling clock time jitter
is:
vet) = A cos[<.Oj(t + J sin <.Ojt)]
(1)
where A is the ADC input signal amplitude, <.OJ is the input signal frequency, J is the peak amplitude of
the jitter, and <.OJ is the jitter frequency. Notice that if <.OJ is increased then the contribution of the jitter
term also increases. This agrees with the intuitive reasoning that if the slew rate of the input signal increases, then the amplitude error caused by clock jitter will increase. Notice also that the units of J is
time, in seconds.
Equation (1) may be re-written as:
vet)
=A cos[ <.Ojt + J<.Oj sin <.Ojt)]
Substituting P
= J <.OJ
gives:
vet) = A cos[ <.Ojt + P sin <.Ojt)]
(2)
Equation (2) is the classical FM modulation equation, where P is the modulation index. Analysis of
the height of sidebands in terms of P is well documented using Bessel functions [1], where Jo(P) is the
relative amplitude of the input frequency component, and Jl (P) is the relative amplitude of the first
pair of sidebands. Since we are only concerned with small amounts of clock jitter, and therefore small
P, only the first pair of sidebands are significant.
As an example of using these formulae, let's set the input frequencr to 10900 Hz, and the clock jitter
peak amplitude to 1 ns. Therefore, since P = J (OJ, P = 6.848 xlO- radians. Unfortunately, commonly
available tables of Bessel functions have JO(P) and 11 (P) values for P = 0, and then for P = 0.1, and
are therefore useless for determining sideband heights for very small p. However, as a result of previous work at Crystal Semiconductor concerning testing Tl line interface parts for very low jitter
specifications [2], a useful relationship between P and Jl (P)lJo(P) was noticed:
(only for very small P)
8-56
(3)
Journal Audio Engineering Society - July 1990
_.-_..--_._.
__.._-_
...-.
Harris Jitter AES Paper
This relationship is also confirmed by approximations for Bessel coefficients given in [3].
Using (3) gives us a Jl (P)/Jo(P) ratio of 3.424 x 10-5 , which is -89.3 dB. Quantization noise for a 16bit, Nyquist sampling ADC is -122 dB peak with respect to a 0 dB full scale input. Assuming the
ADC is normally run at -10 dB input level for full amplitude music, then the sidebands have to be 112 dB down to guarantee non-audibility. Therefore for our example, the sidebands may be audible
(ignoring masking effects of the ear).
How much clock jitter will cause a sideband to rise above the quantization noise floor, and therefore
be potentially audible? Using the above equations, and for an input frequency of 10900 Hz, assuming
a 16-bit ADC, the answer is 232 ps peak clock jitter. This result aligns well with previously published
estimates [4].
2 Clock Jitter Simulations
In order to facilitate the understanding of the effects of clock jitter, a simulation program was written,
shown in Figure 1. Line 160 through line 210 form the main program loop, which increments the
time sample count, G, by one for each pass. Line 170 calculates the jitter amplitude for each sample.
Line 180 simulates a pure cosine input signal, jittered by an amount of time, J. Notice the use of double precision arithmetic. Lines 185 and 200 quantize the output values to X bits. The output of the
program is a set of numbers which are written to a file.
To confirm the accuracy of the simulation compared to theory, the program was run with the same input conditions as used in the theory example. The resulting file of numbers was then processed by a
standard FFT analysis and display program in routine use at Crystal Semiconductor for testing all
types of ADCs [5]. Figure 2 shows the resulting spectrum. The two sidebands are 89.66 dB down
from the input frequency amplitude, which agrees closely with the theoretical result.
Modifying line 170 allows changing the nature of the clock jitter. Changing line 180 allows investigation of different ADC input signals.
3 Measured Results
A CS5101 sampling successive approximation ADC was used to verify the theoretical and simulation
results. Figure 3 shows the test set-up. A 6.144 MHz clock was used to allow later substitution of an
alternate delta-sigma ADC. Using a 6.144 MHz clock determines the sample rate of76.8 kHz. Figure 4 shows the Phase Lock Loop (PLL) circuit used to inject clock jitter. The set-up was verified to
introduce no additional distortion compared to a jitter free crystal based clock source. Clock jitter is
added by injecting the desired jitter modulation signal into the Voltage Controlled Oscillator (VCO) of
the PLL.
Journal Audio Engineering Society - July 1990
8-57
-
-----------_ ..---------
Harris Jitter AES Paper
Using the same conditions as used for the theoretical and simulation example, the sidebands were
shown to be 89.74 dB down from the input frequency component, shown in Figure 5. This validates
the theory and simulation results. The clock jitter was checked by ctisplaying a divided down version
of the jittered clock on a delayed time base oscilloscope. Figure 6 shows a rising edge of the divided
clock, corrupted by 1 ns peak jitter. This measurement was taken at the same time as the Figure 5 test
result plot.
Correlation between clock jitter amplitude and side-band height has previously been verified at Crystal
Semiconductor by compared the jitter readings of an HP 3785A jitter test unit with the same clock jittering an ADC sampling clock [2].
4 Oversampling ADC Clock Jitter Sensitivity
Oversampling delta-sigma ADC's have several advantages over more traditional Nyquist sampling
successive approximation ADC's and are also becoming more available [6] . The CS5326 from Crystal
Semiconductor has an oversampling ratio of 64, sampling the input at 3 MHz. The output of the delta
sigma modulator is a 3 MHz serial bit stream which is then digitally filtered (dc to 22 kHz) and decimated to produce 16-bit numbers at a 48 kHz word rate. How sensitive is such an ADC to clock jitter?
As a proportion of clock period, a given amount of jitter is more significant to a 3 MHz sampling
clock, compared to a 50 kHz sampling clock. However the amount of amplitude error resulting from
the clock jitter is the same in both cases, since the slew rate of the input signal is the same. Also, for
noise induced jitter, the extra noise induced by the jitter will be spread out between dc and 1.5 MHz,
and then low pass filtered by the 22 kHz cut-off digital filter. Thus it is reasonable to speculate that an
oversampling delta-sigma ADC will be no more sensitive to clock jitter than a Nyquist sampling ADC.
To prove this hypothesis, a theoretical simulation was performed, along with measured results.
Figure 7 shows the results of the CS5326 oversampled ADC simulation program. The input conditions
were the same as previously used, that is an input frequency of 10900 Hz, 1 ns peak sinusoidal
980 Hz jitter, and -10 dB input amplitude. The difference in amplitude between the fundamental and
the jitter induced sidebands is 89 dB, which is the same result as obtained in the Nyquist sampling
case. The lack of low frequency noise in Figure 7 is because the simulation did not include the final
truncation to 16-bits after the filter.
Figure 8 shows the measured results from the CS5326 oversampled ADC. The test conditions were the
same as above, and the test set-up was the same as shown in Figure 3, using a CDB5326 evaluation
board. The plot shows that the difference in amplitude between the fundamental and the jitter induced
sidebands is 89.5 dB, which agrees well with the oversampled ADC simulation results, and with the
previously given non-oversampled ADC test results.
The above results confirm that an oversampled delta-sigma ADC has the same sensitivity to clock jitter as a Nyquist sample rate ADC.
8-58
Journal Audio Engineering Society· July 1990
.-_
_
..--_._.
__.._-_
...-.
Harris Jitter AES Paper
5. Non Sinusoidal Jitter
In practical hardware, clock jitter will not be sinusoidal. It is likely to consist of noise components and
some periodic components. To investigate the effects of white noise jitter, the simulation program
given in Figure 1 was modified, replacing the sine jitter equation with a random number generator
equation (Figure 9).
A number of simulations were run which show that white noise clock jitter results in an overall elevation of the noise floor of the ADC system. This will degrade the available dynamic range. For
example, 2 ns peak white noise clock jitter will degrade a perfect 16-bit ADC from a dynamic range
of 98 dB to 91 dB (Figures 10 &11). To reduce clock jitter effects to less than 0.5 dB impact on dynamic range, the peak jitter amplitude has to be less than 400 ps (Figure 12).
For oversampling ADC's, we speculated that the effects of clock jitter noise would be treated like
quantization noise, that is spread out between DC and half the input sample rate, and then filtered by
the audio bandwidth digital filter. Figure 13 shows the results of a delta sigma ADC simulation, with
2 ns peak white noise clock jitter. Compared to Figure 11, this confirms that the delta sigma ADC is
much less sensitive to white noise clock jitter. As with Figure 7, Figure 13 does not include 16-bit
quantization noise.
6. Conclusions
A combination of theoretical analysis, computer simulations and practical measurements has allowed
the confident prediction of the audible effects of sampling clock jitter. As the resolution, and therefore
dynamic range, of ADC's and DAC's increase beyond 16-bits, sampling clock jitter will become more
significant. The analysis techniques presented allow maximum allowable levels of clock jitter to be determined.
It has been demonstrated that delta-sigma oversampling ADC's are no more or less susceptible to the
effects of clock jitter than Nyquist sampling architectures. It has also been shown that delta-sigma
oversampling ADC's are less sensitive to random noise clock jitter than Nyquist sampling ADC's.
7. Acknowledgments
My sincere thanks go to Greg Stearman, Bruce Del Signore, Dan Caldwell, John Lamay and Eric
Swanson at Crystal Semiconductor for their theoretical and practical help in preparing this paper.
Journal Audio Engineering Society - July 1990
8·59
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___-_
.. ...
.-_..,-.........
.....
Harris Jitter AESPaper
8. References
[1] H. Taub & D.L. Schilling, "Principles of Communication Systems,." McGraw-Hill, pp 113-131.
[2] Lamay J.L. & Caldwell D.C., "A Telecommunications Line Interface Test System Architecture",
Proceedings of the IEEE International Test Conference, 1989, pp 216-221.
[3] Pipes, L.A., "Applied Mathematics for Engineers and Physicists", McGraw-Hill Book Company,
New York, 1958.
[4] Lidbetter, P.S., "Basic Concepts and Problems of Synchronization of Digital Audio Systems", Presented at AES 84th Convention, Paris, March 1988
[5] Harris S., " Dynamic Techniques Test High-Resolution ADCs on PCs", Electronic Design, September 3, 1987.
[6] Welland D.R. et al, "A Stereo 16-Bit Delta-Sigma AID Converter for Digital. Audio", 1. Audio Eng.
Soc., Vol. 37, No.6, June 1989.
8-60
Journal Audio Engineering Society - July 1990
---------------------10 REM
ADC SIMULATION PROGRAM "JITSINE"
Harris Jitter AES Paper
Steven Harris
8/3/89
95 INPUT "Number of samples in output file ?",SIZE
96 REM Set X = to # of bits in ADC
97 LET X = 16
100 PRINT "JITSINE generates ";SIZE;" numbers quantized to ";X;" bits"
102 PRINT "Random phase offset added to simulate asynchronous sampling"
103 PRINT "Sine wave jitter is added to the sampling clock"
110 REM The numbers are dumped in a file as 5 digit decimal values
112 INPUT "File name to write numbers? ",F$
113 OPEN "0",#1,F$
116 Offset=RN D
1170ffsetj=RND
135 LET PI#=3.141592654
143 INPUT "Sample Frequency ?",FS#
145 INPUT "Input Signal Frequency?", FIN#
146 INPUT "Input Signal Amplitude relative to full scale (=1) ", INAMP#
147 INPUT "Jitter Frequency ?",FJ#
149 INPUT "Peak amplitude of clock jitter in seconds ?",JPA#
160 FOR G = 1 TO SIZE
168 REM Form jitter amplitude for this time sample
170 LET J# = JPA#*SIN(Offsetj + «G-1)*2*PI#*FJ#/FS#))
172 REM Form unquantized clock jittered cosine value for this sample
180 LET A# =INAMP#*COS(2*PI#*FIN#*«(G-1 )/FS#)+J#)+Offset)
182 REM Scale to X bits
185 LET A# = A#* « (2I\X)/2)-1 )
198 REM Quantize levels (round to nearest integer)
200 LET S = CINT(A#)
205 REM PRINT "#="G;"Value=";A#;"Quantized value=";S
207 PRINT #1, USING "######";S
210 NEXT G
220 CLOSE #1
-
Figure 1. BASIC program which simulates a perfect N-bit ADC with sinusoidal clock jitter
Journal Audio Engineering Society - July 1990
8-61
.._-_
_.-_..--_._.
__
...-.
Harris Jitter AES Pa.per
,
0.00
-10.00
Sample Rate: 76.8 kHz
Input Frequency: 10.9 kHz
Jitter Frequency: 980 Hz
Jitter Peak Amplitude: 1 ns
-20.00
iil -30.00
~
0;
-40.00
--'
-50.00
'&
-60.00
a;
.5
Jitter Component Amplftude
Compared to. Input : 89.66 dB
-,
-70.00
-80.00
J
-90.00
,
-100.00
-110.00
7. 8 11.52 15.36 19.2023.04 26.68 30.72 34.56 38.40
Frequency (kHz)
Figure 2. Nyquist Sampliug ADC Simulation with 1 ns Peak Sine Clock Jitter
Signal Source
Khron-Hfte 4400A
X1k
OdB
10900 Hz SET
10900 Hz (-10dB)
Main
Output
50.11
Jitter Source
Khron-Hite 4400A
X 100
40 dB
980 Hz SET
Main
Output
50.11
I 980 Hz, Jitter
4046 PLL
Boand
AINL
Jittered
Clock out
In
+5
Clock In
6.144 MHz
I---
GND
CDB5101/CDB5326
Extemal
Clock
In
+5
t
ADCBoard
GND
-15
f----o
IBM
PC
Computer
GND +15
r
6.144 MHz
+5
Clock
GND
Osc
I Power
+5 GND
Supply
#2
1-15
GND +151
powe~~UPPIY
Figure 3. Jitter Experiments Test Set-up
Journal Audio Engineering Society - July 1990
_
..--__.._-_
...
.-._.-.
Harris Jitter AES Paper
+5
Vee
6.144 MHz
OSC
0.1 uF
+5
OUT
0.1 uF
'-------cSr
Vee
14 SIGNAL
IN
Jittered
VCO OUT f"-<~--.......j'@ I
CD74HC40464A
6 C1 A
¢
SOpF
7 Cl.
Clock Out
(ext. clock of
eval board)
DET 3 f-"15"--'1N'v---,
VCO IN f-'9,--_~
11 Rl
lkn
7.2kn
12 R2 DEMOD OUT
INHIBIT
I
Khron-Hite 4400A
Oscillator (Jitter Source)
~
lkn
l0nF
3.3 uF
Figure 4. Phase Locked Loop Jitter Generator Schematic
0.00
-10.00
Sample Rate: 76.S kHz
Input Frequency: 10.9 kHz
Jitter Frequency: 9S0 Hz
Jitter Peak Amplitude: 1 ns
-20.00
iii' -30.00
~
a; -40.00
Jitter Component Amplitude
Compared to Input: S9.74 dB
it; -50.00
-'
:E
c..
-'
E
-90.00
-100.00
-
"C
-70.00
-SO.OO
~
(])
~ -60.00
-"
>
«
c
Frequency (kHz)
Figure 5. Measured Nyquist Sampling ADC (CS5101)
with 1 ns Peak Sine Clock Jitter
Journal Audio Engineering Society - July 1990
Time 2 ns/div
Figure 6. ADC Sampling Clock Jitter Measured at the
Output of the Clock Jitter Generator Shown in Figure 4
8-63
----------------------
Harris Jitter AES Paper
0.00
Sample Rate: 3.072 MHz
Output Word Rate: 48.0 kHz
Input Frequency: 10.9 kHz
Jitter Frequency: 980 Hz
Jitter Peak Amplitude: 1ns
Jitter Component Amplitude
Compared to Input: 89.0 dB
-10.00
-20.00
10
-30.00
:s
-40.00
it;
-50.00
'5
-60.00
a;
...J
c.
.5
-
-70.00
- .-
.-
-80.00
-90.00
-100.00
-110.00
-120.00
-130.00
.l-__-:-_--.l~aJjlJilll~~Il...IUA)llIlllDj
0.0
4.0
8.0 FreqUe~~$ (kHz) 16.0
20.0
24.0
Figure 7. Simulated 64x Oversampling Delta Sigma ADC with 1 ns Peak Sine Clock Jitter
0.00
-10.00
-20.00
-30.00
10
:s
-40.00
Sample Rate: 3.072 MHz
Output Word Rate: 48.0 kHz
Input Frequency: 10.9 kHz
Jitter Frequency: 980 Hz
Jitter Peak Amplitude: 1 ns
I
g!. -50.00
~ -60.00
=>
c.
.5 .-70.00
-80.00
-90.00
'-
-100.00
Frequency (kHz)
Figure 8. Measured 64x Oversampling Delta·Sigma ADC (CS5326) with 1 ns Peak Sine Clock Jitter
8·64
Journal Audio Engineering Society - July 1990
_.-------..--_._.
__ ...10 REM
ADC SIMULATION PROGRAM
Harris Jitter AES Paper
"JITNOISE"
Steven Harris 8/3/89
95 INPUT "Number of samples in output file ?",SIZE
96 REM Set X = to # of bits in ADC
97 LET X = 16
100 PRINT "JITNOISE generates ";SIZE;" numbers quantized to ";X;" bits"
102 PRINT "Random phase offset added to simulate asynchronous sampling"
103 PRINT "White noise jitter is added to the sampling clock"
110 REM The numbers are dumped in a file as 5 digit decimal values
112 INPUT "File name to write numbers? ",F$
113 OPEN "O",#1,F$
116 Offset=RND
117 Offsetj=RND
135 LET PI#=3.141592654
143 INPUT "Sample Frequency ?",FS#
145 INPUT "Input Frequency?", FIN#
146 INPUT "Input signal amplitude relative to full scale (=1) ?", INAMP#
149 INPUT "Peak amplitude of clock jitter in seconds ?",JPA#
160 FOR G = 1 TO SIZE
169 LET NOISE=RND
170 LET J# = JPA#*(NOISE*2-1)
172 REM Form perfect clock jittered sine
180 LET A# = INAMP#*COS(2*PI#*FIN#*(((G-1)/FS#)+J#)+Offset)
182 REM Scale to X bits
185 LET A# = A#*(((2AX)/2)-1)
198 REM Quantize levels (round to nearest integer)
200 LET S = CINT(A#)
205 REM PRINT "#="G;"Value=";A#;"Quantized value=";S
207 PRINT #1, USING "######";S
210 NEXT G
220 CLOSE #1
230 GOTO 95
Figure 9. BASIC program which simulates a perfect N-bit ADC with noise jittered clock
Journal Audio Engineering Society - July 1990
8-65
-_.._--.
;.==~;=:.
Harris Jitter AES Paper
0.00
0.00
-10.00
Sample Rale: 48 kHz
Input Frequency: 10.9 kHz
No Clock Jitter
-20.00
Iii"
:s
~
-'
-30.00
SignaVNoise: 87.88 dB
Dynamic Range: 97.88 dB
-40.00
,-
-50.00
5
c. -60.00
.5
-70.00
-10.00
-30.00
Iii"
:s
!i
-40.00
5
-60.00
SignaVNoise: 81.26 dB
Dynamic Range: 91.26 dB
~ -SO.OO
,g-
-70.00
'-
-80.00
Sample Rate: 48 kHz
Input Frequency: 10.9 kHz
White Noise Jitter. :2 ns pk
-20.00
-80.00
-90.00
-90.00
'-
-100.00
-100.00
-110.00
-120.00
-130.00 -jillI1iI.l1.l.l"'.LlllIIIIU..jIIIIHRlI~IlI.JJ&I..-uUJ_IIllUII~
O.
8. 0
12.00
16.00
Frequency (kHz)
Figure 10. Nyquist Sampling ADC Simulation with No
Clock Jitter
1
Frequency (kHz)
Figure 11. Nyquist Sampling ADC Simulation with 2 ns
Peak White Noise Clock Jitter
0.00
0.00
-10.00
-20.00
Iii"
-30.00
~
-40.00
:s
SignaVNoise: 87.27 dB
Dynamic Range: 97.27 dB
"
5
-' -SO.OO
-20.00
Iii"
-30.00
5
-40.00
:s
.5
-70.00
-60.00.
-80.00
-90.00
-90.00
-100.00
-100.00
-110.00
-110.00
-J.UUIIIl14lJU1.....
W.~IlJI~IlIIW~lJ.IlWj
8.00
12.00
16.00
-130.00
O.
Frequency (kHz)
Figure 12. Nyquist Sampling ADC Simulation with
400 ps Peak White Noise Clock Jitter
8-66
Dynamic Range: 98 dB
-50.00
5c. -60.00
c. -60.00
.5
-70.00
-120.00
Sample Rate: 3.072 MHz
Oulput Word Rate: 48 kHz
Input Frequency: 10.9 kHz
Whfte Noise Jitter
Jitter Peak Amplitude: 2 ns
-10.00
Sample Rate: 48 kHz
Input Frequency: 10.9 kHz
White Noise Jitter. 400 ps pk
-120.00
-130.00
0.00
4.00
8.00 FreqU~~c~O(kHz) 16.00
20.00
24.00
Figure 13. Simulated 64x Oversampling Delta.Sigma
ADC with 2 ns Peak White Noise Clock Jitter
Journal Audio Engineering Society· July 1990
--------.--------------
Sooch CS4328 AES Paper
1S-BIT STEREO D/A CONVERTER WITH INTEGRATED DIGITAL AND
ANALOG FILTERS.
Nav S. Sooch, Jeffrey W. Scott
Crystal Semiconductor, Austin, Texas
T. Tanaka, T. Sugimoto, C. Kubomura
Asahi Kasei Microsystems, Tokyo, Japan
ABSTRACT
This paper describes an integrated digital audio Digital-to-Analog output
system. The circuit consists of an 8x digital interpolation filter followed by a
64x oversampled Delta-Sigma modulator. The modulator output controls the
reference voltage input to an ultra-linear analog low pass filter. The total
DIA system provides a linear phase response.
INTRODUCTION
Delta-sigma modulation has become the conversion technology of choice for audio-band data converters. Analog-to-Digital converters using the delta-sigma conversion principle have been available
for many years. The several advantages of delta-sigma modulation already demonstrated for AID
converters also apply to DIA converters. The benefits of delta-sigma modulators over conventional
laser trimmed converters include:
1.
No differential linearity error.
2.
No distortion mechanisms due to component mismatch.
3.
No laser trimming.
4.
No linearity error drift over time and temperature.
Previous delta-sigma audio D/A converter implementations have either not integrated the analog fIlter
or required several external fIlter components [1],[2]. These implementations require component
value changes for large variations in conversion rate. This paper presents an 18-bit stereo D/A
converter employing delta-sigma modulation that integrates digital and analog fIlters that track the
conversion rate. No external components are required.
The block diagram of the complete system is shown in figure 1. An 8x interpolation filter removes
out-of-band images. The output of the interpolator is held for eight, 64fs cycles and fed into a 5th
order delta-sigma modulator. An analog fIlter removes high frequency quantization noise in the
modulator output and presents a signal suitable for playback. The interpolation filter and modulator
This paper was presented at the 91st AES convention, October 1991, New York, Pre-print #3113(y-1)
8-67
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Sooch CS4328 AES Paper
are implemented on a 1.6 ~ double metal CMOS chip. The analog ftlter is implemented in a 3 f.Lm
CMOS chip. Both chips are packaged in one 28-pin DIP.
INTERPOLATION FILTER
The purpose of the digital interpolation ftlter is to remove images of the baseband audio signal that
exist in the sampled data signal. Figure 2a shows the spectrum of the sampled data signal that is
input to the D/A converter. The spectrum (chosen here to have near uniform frequency content) has
images of the baseband audio signal that repeat at the input sample rate (fs) of the D/A converter.
Although the frequency content of the images is above the human hearing range (20kHz), inevitable
nonlinearities downstream from the D/A converter require removal of these images. Intermodulation
of the signals above the audio band by these nonlinearities can result in audible by-products. Figure
2f is the desired signal that should be output by the DIA converter.
The interpolation ftlter is implemented in three consecutive interpolate by 2 stages as shown in
Figure 3. This three stage FIR architecture meets two design goals. The first goal is adequate image
rejection. The second design goal is to implement two channels of interpolation ftlters with a single
hardware multiplier that operates at a maximum clock rate of 256fs (12.288MHz for sampling rate of
48kHz).
The first stage of interpolation is a 125 tap half-band FIR ftlter (i.e. every other coefficient except for
the center coefficient is zero) [3]. The half-band topology is well suited for 2x interpolation and
decimation filters since it provides rejection above one fourth the filter's sample rate reference. The
spectrum at the output of the first stage is shown in figure 2b. Note that the first image is removed
by this stage of ftltering. The first stage is the most difficult of the three interpolation stages since it
requires the steepest roll-off characteristics.
The second interpolate by two stage is a 24 tap FIR ftlter. The third interpolate stage is a 4 tap FIR
filter. The spectra at the output of the second and third stages are shown in figure 2c and 2d,
respectively. Note that the complete interpolation ftlter provides less attenuation for higher frequencies than for frequencies just outside the audio band. This is done with the knowledge that the
analog ftlter will easily attenuate signals at higher frequencies but will have difficulty filtering signals
just above the audio band.
Eighteen bit wide data paths with 19-bit coefficients are used throughout the interpolation ftlter. The
SIN for a full scale sinewave (noise due to truncation) of the interpolation ftlter is over 107dB in the
audio band.
DELTA-SIGMA MODULATOR
The fifth-order delta-sigma modulator shown in figure 4 is used to convert the output of the interpolation ftlter into a I-bit stream. The signal is converted to a I-bit stream so that an inherently linear
I-bit D/A converter can be used. The modulator-is sampled at 64fs. The output of the interpolation
filter is held for eight consecutive modulator clock cycles yielding a sinc ftlter characteristic. The
8-68
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Sooch CS4328 AES Paper
spectrum of the signal at the input to the modulator is shown in figure 2e. The fifth order modulator
was chosen to keep all inband quantization noise peaks well below -130dB, and is similar to
other high order modulator topologies [4]. The spectrum at the output of the modulator is shown in
figure 5 for a modulator sample rate of 3.072MHz. This figure is a simulation of the modulator
alone and does not include any effects of the digital or analog filters. The SIN of the modulator in
the 20kHz audio band is I20dB.
I-BIT D/A
The many advantages of I-bit DIA conversion can only be enjoyed if the DIA converter has only two
distinct output levels. Errors in the two output levels caused by noise, interference, or dependence
on previous states can substantially degrade the SIN ratio of the DIA converter. Many delta-sigma
DIA converters perform the I-bit conversion by holding an output voltage level for a finite duration
of time defined by periods of a master clock source[l]. This waveform is then filtered by a continuous-time analog filter. The resulting output is highly dependent on purity of the clock signal used to
gate the output voltage level. Jitter in the clock source directly translates to errors in the I-bit D/A
output.
The requirement for a low jitter clock can be essentially eliminated by the use of a switched capacitor structure. A switched capacitor filter processes packets of charge. The I-bit DIA converter is
implemented by charging a capacitor to a voltage reference and choosing the appropriate polarity of
the charge by one of two switching arrangements. As long as the voltage reference value settles on
the capacitor, the magnitude of the charge packet will be independent of the clock jitter.
ANALOG FILTER
The block diagram of the analog filter is shown in figure 6. The first switched-capacitor filter has
fourth-order Butterworth response with a -3dB frequency of 25kHz. The topology of the fourth-order switched capacitor filter is shown in figure 7. The multiple feedback loop topology is chosen
over the traditional cascaded biquad configuration for its high noise rejection of integrators 2, 3, and
4. The sampling rate of the switched capacitor filter is 64fs, identical to that of the delta-sigma
modulator.
Switched capacitor filters have generally been used in telecommunications circuits for their precise
frequency response characteristics and their unique ability to scale frequency response directly with
the clock rate. Switched-capacitor structures used as I-bit DIA post filters offer the further benefit of
easing the delicate transition from discrete-time to continuous-time processing. With the exception of
the final stage, signal processing in a switched-capacitor filter is performed entirely in the sampleddata domain where nonlinear opamp settling behavior cannot distort signals of interest.
Consequently, the strong high frequency energy of the I-bit pattern is substantially reduced before it
has the opportunity to excite any dynamic nonlinearities in subsequent continuous-time filtering.
The use of switched-capacitor filters in audio applications has been quite limited because of their
traditionally inadequate dynamic range. The economics of integration have historically restricted
switched capacitors to values that realize relatively high effective impedances. The result is a high
8-69
Ell
_..--..__---.._-_
...
.-.-.
Sooch CS4328 AES Paper..
thermal noise floor in the frequency range of interest. In this design; dynamic range is extended to
97dB (A-weighted) by appropriate selection of loop topology, opamp topology and capacitor values.
The distortion mechanisms traditionally associated with switched-capacitor structures have further
limited their use in high performance applications. Distortion in switched capacitor filters is primarily caused by nonlinear charge injection during sampling, opamp dc nonlinearities and slewing of the
final stage output waveform between settled output levels [5]. In this design charge injection is kept
independent of input signal levels by appropriate switch phasing, and dc opamp nonlinearity is made
negligible by sufficient open loop gain.
The third distortion mechanism, arising from opamp output slew limiting, is generally the most
difficult to control. Since the output of the switched capacitor filter is being treated as a continuoustime waveform, the exact nature of the transition from one settled value to the next is critical in
achieving a low distortion waveform. Nonlinear behavior in this transition must be avoided.
To ease the transition between the switched-capacitor domain and the continuous-time domain the
switched-capacitor to continuous-time buffer of figure 8 is used. This buffer samples the output of
the switched capacitor filter after it is settled and provides a continuous-time waveform free from
distortion artifacts. The switching. arrangement ensures that the charge transfer from Cl to C2 is
done passively and not with the assistance of the amplifier. The amplifier only supplies the charge to
the output load capacitance, which at low frequencies is minimal. This buffer has a single pole
response with a -3dB frequency of 50kHz.
A continuous-time filter is used to remove the remaining images at multiples of the switched capacitor sample rate (64fs). The continuous-time filter has a second order butterworth response with a
-3dB frequency of 80kHz. The output stage of the continuous-time filter is capable of driving a
6000 load with less than 0.0015% THD at 10kHz.
MAGNITUDE AND PHASE RESPONSE
Although the magnitude response of the analog filter is fairly flat due to the Butterworth response, it
is not sufficient for digital audio qUality. To achieve greater flatness the response of the analog filters
is compensated in the digital interpolation filter. FIR2, the second stage of interpolation, performs
the magnitude compensation. The total calculated magnitude response of the DIA system is shown
in figure 9.
Since the nonlinear phase response of the analog filter is also a concern, the phase response of the
analog filter is also equalized in the digital interpolation filter. Again, FIR2 is used for phase equalization. Figure 10 plots the deviation from linear phase for the analog filter, digital filter and the
combined D/A system. Total deviation from linear phase is kept to less than 0.7 0 in the audio band.
Since the frequency response of the analog filter is dominated by the switched capacitor filter, the
magnitude and phase equalization will be valid at any sample rate of the DIA converter.
8-70
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Sooch CS4328 AES Paper
OFFSET CALffiRATION
In any integrated analog filter significant dc offsets can be generated. In this design offset calibration
is perfonned to lower the effective offset to approximately 20 Ilv. A comparator measures the analog
output of the filter with respect to ground and a successive approximation search is used to find the
offset at the input to the delta-sigma modulator. Since the comparator does not band limit at 20kHz,
its decisions are impacted by the entire out-of-band quantization noise left at the output of the analog
filter. To achieve repeatable and accurate calibration the output of the comparator is averaged for
1024 cycles before a successive approximation decision is made.
The actual implementation of the comparator is shown in figure 11. The output stage of the continuous-time filter is disconnected from the chip output and is used as a comparator. This eliminates the
need to design a zero offset comparator and also isolates the chip output from any audible clicks that
may be generated by the successive approximation search.
Audio systems are susceptible to pops and clicks generated by active circuitry during power-up and
power-down transients. This design incorporates a low power supply detect circuit which holds the
output shorted to ground (i.e., same as calibration mode) until the supplies are sufficiently high to
allow the remainder of the analog filter to operate correctly. Hysteresis in the low supply detect
circuit prevents rapid toggling of the switches near the trip point. As a result, tum-off and tum-on
_power transients are inaudible even for loud listening levels.
MEASURED RESULTS
The D/A has been characterized using a CBS Test Disk 1 and an Audio Precision System One. The
measured magnitude response of the complete D/A system is shown in figure 12. The slight peaking
near 20kHz of O.ldB is due to a systematic mismatch of capacitors in the switched-capacitor filter.
Unweighted THD+N (0-22kHz) versus input sinewave level is shown in figure 13. A considerable
portion of the output noise is concentrated near the upper end of the audio range. Dynamic range
from 0-20kHz is 93.8dB and A-Weighted dynamic range is 97dB. Figure 14 is a plot of the output
spectrum of a -90dB dithered sinewave at 1kHz. Because of the ideal differential nonlinearity of the
I-bit D/A, the noise floor is quite smooth. A key test of D/A converters is the fade-to-noise linearity
test shown in figure 15. A monotonically decreasing sinewave is fed into the D/A converter. The
energy of the output sinewave is compared with the energy of the input. Deviations from 0dB are a
result of differential nonlinearity or noise. The D/A exhibits excellent perfonnance down to -95dB
where the residual output noise starts to dominate the measurement. Figure 16 is a plot of the idle
channel output spectrum from 0 to 100kHz showing the relatively low level of out-of-band quantization noise. The total energy from 0-lookHz is 78dB below full scale. Table 1 is a summary of the
system perfonnance specifications.
8-71
-
----------- -..---------
Sooch CS.4328 AES Paper
CONCLUSION
An 18-bit D/A converter using delta-sigma modulation has been presented. The design integrates an
8x interpolation filter with a fIfth order delta-sigma modulator. On a separate chip an analog filter
wiing a combination of switched-capacitor and continuous-time filters is implemented.
Switched-capacitor filters have the ability to change bandwidths without changing component values.
One bit DIA converters implemented with switched-capacitors offer excellent clock jitter tolerance.
The design difficulties associated with high quality switched-capacitor filters have been mastered. In
the future even higher dynamic range switched-capacitor filters can be expected.
REFERENCES
[1] Y.MATSUYA, et.al., "A 17-bit oversampling D-to-A Conversion Technology Using Multistage
Noise Shaping," IEEE J. Solid-State Circuits, vol.24, noA, pp.969-975, August, 1989.
[2] P.J.NAUS, et.al., "A CMOS Stereo 16-bit D/A Converter for Digital Audio," IEEE 1. Solid-State
Circuits, vol.SC-22, no.3, pp.390-395, June 1987.
[3] P.P.VAIDYANATHN and T.Q.NGUYEN, "A 'Trick' for the Design of FIR Half-band Filters,"
IEEE Trans. Circuits Sys., vol.CAS-34, pp.297-300, March 1987.
[4] W.L.LEE and C.G. SODINI, "A Topology for Higher Order Interpolative Coders," ISCAS Digest,
1987, ppA59-462.
[5] K.LEE and RG.MEYER, "Low-Distortion Switched-Capacitor Filter Design Techniques," IEEE
J. Solid-State Circuits, vol.SC-20 no.6, pp.1 103-11 13, December 1985.
TABLE 1
Dynamic range
A-weighted
(18-bit mode)
SITHD 1kHz
Interchannel Isolation 1kHz
Power Consumption
Digital
Analog
Deviation from flat magnitude
Total DIA System
Deviation From Linear Phase
Total DIA System
Digital Filter Stop Band Attenuation
Digital Filter Pass Band Ripple
8·72
97dB
92dB
-l1OdB
150mW
420mW
O.ldB
< 0.7 0
90dB
O.OOldB
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._.-.
_.-_..--__
...
18 Bit
Digital Input
fs
----->
Sooch CS4328 AES Paper
18 Bit
8 fs
8x Interpolation
Filter
5th-order
Delta-Sigma
Modulator
1 Bit 64 fs 1 Bit
I--D/A
I-
Analog
Low-Pass
Filter
r-----.
Analog
Output
-
Figure 1. 18 Bit D/A Converter Architecture
a
o·
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b
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o
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Frequency
31s
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Figure 2.
8-73
--- -------------------
Sooch CS4328 AES Paper
FIR1
18 Bit
Digital Input
Is
---->
2x Interpolation
Filter
125 Taps
FIR3
FIR2
- 2 Is
2x Interpolation
Filter
24 Taps
4 Is
I---
2x Interpolation
Filter
8 Is
4 Taps
Figure 3. Interpolation Filter Architecture
b1
18 Bit
Input
+
1 Bit Output
Figure 4. Digital Delta·Sigma Modulator
8·74
Interpolator
Output
b2
----------- -----------
Sooch CS4328 AES Paper
0
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Frequency (kHz)
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Figure Sa. Modulator Output Spectrum
o,-o-----------------------------------~
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6
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12
14
8
Frequency (kHz)
16
18
20
Figure 5b. Expanded Modular Output Spectrum
8-75
----------- ----------1 Bit Input From
Delta·Sigma
-----0
Modulator
Sooch CS4328 AES Paper
4th·order
Switched·
Switched·
Capacitor to
Capacitor
Continuous
Filter
Time Buffer
·3 dB @ 25 kHz
2nd·order
I----
Continuous
Analog
Output
Time Filter
·3dB @ 50 kHz
·3dB @ 80 kHz
Figure 6. Analog Filter Architecture
Analog
In.
log
+
+
+
BIS
AlS
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+
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Vo(s)
.
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ABCD
Vin(s)
Figure 7. Switched Capacitor Filter Topology
Output
Figure 8. Switched-Capacitor to Continuous Time Buffer
8-76
Output
----------- -----------
Sooch CS4328 AES Paper
15~--------------------------------------~
o -r----, - - - - - - - - - - - - - - - - - - - - - - - - - -
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o
15
30
45
60
75
90
105 120 135 150
Frequency (kHz)
Figure 9. Total D/A System Magnitude Response
20~--------------------------------------~
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o
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Frequency (kHz)
Figure 10. Deviation From Linear Phase
8-77
-____-_
.. ...
._.-.
-. ..---
Sooch CS4328 AESPaper
CRYSTAL FRQRSP48
AMPL(dBr) vs GENFRQ(Hz)
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Figure 12. Frequency Response (48 kHz word rate)
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Figure 14. 1 kHz, -90dB Input FFT Plot
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98.0
----------- -----------
Knapp AES-EBU Paper
A Family of AES-EBU Interface Devices
David J. Knapp
Design Engineer
Crystal Semiconductor Corp., Austin,Texas
U.S.A.
ABSTRACT
This paper describes a family of digital audio transmitters and receivers
which conform to the AES-EBU interface standard. Different versions are
used to control the interface to various levels of complexity. Few external
components are required to create a complete transmission link. The paper
introduces the AES-EBU standard and illustrates the chip architectures.
o INTRODUCTION
"The AES-EBU digital audio interface has been slow to gain market acceptance, partly because of
interface complexity, specification ambiguities, lack of commercial IC's, and the effort required for
discrete implementations." [1] To alleviate these problems and promote widespread use of the interface, Crystal Semiconductor has defined a family of integrated circuits that will facilitate the
implementation of the AES-EBU standard. These IC's are general purpose, providing compatibility
as the specifications mature, support the similar consumer-style interface, and consist of two versions
of transmitters and receivers. Since the transmitters are commercially available today and the receivers are still in development, this paper will primarily discuss the transmitters, following a brief
overview of the interface specifications.
Ell
1 AES-EBU SPECIFICATIONS
The AES-EBU interface, described in AES3-1985 [2], is a means for serially communicating digital
audio data through a single transmission line. It provides 2 channels for audio data, a method for
communicating control information, and some error detection capabilities. This control information
is transmitted 1 bit per sample and accumulates in a block structure. Data is biphase encoded, which
enables the receiver to extract a clock from the data, with coding violations identifying sample and
block boundaries. The electrical specifications for the AES-EBU interface are compatible with RS422 [3].
The structure of the serial word, called a subframe, is illustrated in Figure 1. The subframe consists
of 4 bits of preamble, 4 bits of auxiliary data, 20 bits of audio data, a parity bit, and 3 bits called
validity, user, and channel status. The preamble contains biphase coding violations and identifies the
start of a subframe. The audio sample word length can vary up to 24 bits. If the word length is
greater than 20 bits, the sample occupies both the audio and auxiliary data fields. If it is 20 bits or
less, the auxiliary field can be used for other applications such as a voice channel. The parity bit
generates even parity and can be used to detect an odd number of transmission errors. If an even
number of bit errors occurred, the received parity will remain even and the errors will not be identiThis paper was presented at the 89th AES Convention, Los Angeles, September 1990, Preprint #2962
8-79
.._-_
._.-.
_.-_..--__
...
Knapp
AES~EBU
Paper
fied. The validity bit indicates if the audio sample is secure and error free. In some applications it
identifies samples that have been interpolated due to errors. The user and channel status bits are sent
once per sample and when accumulated over a number of samples can be used to transmit blocks of
.data. The user bit channel is undefined and is available to the user for any purpose. The channel
status channel is defined and conveys important information about the audio data and transmission
link. Each of the two audio channels has its own channel status channel with a block structure that
repeats every 192 samples.
As shown in Figure 2, two subframes, one each from channels 1 and 2, create a frame and 192
frames generate a block. The preambles that identify the start of a subframe are unique for each
channel with another third pattern identifying the beginning of channel status block. The 192 channel status bits in a block can be arranged. as 24 bytes and are defined according to the AES-EBU
standard as shown in Figure 3. Bytes 0 to 3 contain specific bits of information about the data and
the link, bytes 4 and 5 are presently undefined, bytes 6 to 13 can be used for networking, bytes 14 to
17 function as a recording index counter by counting the number of transmitted blocks, bytes 18 to
21 record the time the signal was source encoded, byte 22 identifies which bytes of the block are
valid, and byte 23 is a cyclic redundancy check character generated from the previous 23 channel
status bytes (provides some error detection).
The primary difference between theAES-EBU interface and the consumer interface is the definition
of the channel status bits. The defmition for the consumer interface is illustrated in Figure 4. Bytes
o to 3 contain specific bits of information about the data and the link, and bytes 4 to 23 can be used
for music program. production. More information on these bytes is available in the EIAJ CP-340
document [4].
The channel coding used in the AES-EBU and the consumer interface is biphase mark. As shown in
the example given in Figure 5, this means there is a transition at every data cell boundary and
another transition in the middle of the data cell when transmitting a one. There is no transition in the
middle of a data cell when transmitting a zero. Recovering a clock from data encoded this way is
simpler than other coding schemes due to the frequent transitions. Biphase coding also has no dc
content, which allows ac coupling, and is immune to polarity inversions. Synchronization is
achieved by producing biphase coding violations in the preambles. A violation occurs when there is
no transition at a data cell boundary and the patterns used to identify subframe, frame, and block
boundaries are shown in Figure 6.
The electrical specifications of the AES-EBU interface require encoded data to be transmitted as a
differential signal on a shielded twisted pair cable. The signal voltage can be 3 to 10 volts peak to
peak when measured across a 110 ohm resistor. The consumer interface allows electrical or optical
communication. As an electrical link, data is transmitted as a single ended signal on a coaxial cable
with a signal amplitude of .5 volts +/- 20%, when measured across a 75 ohm load.
8-80
----------- -----------
Knapp AES-EBU Paper
2 THE AES-EBU CHIP FAMILY
Our AES-EBU Ie'S are general purpose, support both the AES-EBU and consumer interfaces, and
consist of two transmitters and two receivers. Having the line drivers on the transmitters and the line
receivers and clock recovery circuits on the receivers, they provide a complete transmission link with
minimal external components. Providing control of and access to all the user and channel status bits,
these devices will remain compatible with the specifications as the standard matures. The two transmitter and receiver versions are appropriate for different applications. Both versions have serial ports
for audio data. The first version, which consists of the CS8401 transmitter and the CS8411 receiver,
has a buffer memory with a parallel port for storing control information and most of the non-audio
subframe data, and should be driven by a processor. The second version, which consists of the
CS8402 transmitter and the CS8412 receiver, will operate without a processor. This version is controlled by dedicated pins, and can accept and provide the non-audio data on a sample basis through
serial input and output pins. Both transmitters, whose pinouts are shown in Figures 13 and 14, are
available in 24 pin DIP's and SOle's. The receivers will be available in similar 28 pin packages.
Figure 7 illustrates the basic differences between the two transmitters.
Both transmitters, having RS422 differential line drivers, are compatible with the AES-EBU interface. To make these parts compatible with the consumer interface for an electrical link, the
non-inverting driver output can be attenuated by an external resistive divider. This will provide the
necessary single ended signal with the appropriate amplitude.
3 THE CS8401 TRANSMITTER
As shown in Figure 8, the CS8401 has control registers, a status register, and a 28 byte buffer
memory, which are all accessible through an 8 bit parallel port. The buffer memory holds channel
status, user, and auxiliary data, and can be monitored by the status register and the interrupt pin. The
device supports both the AES-EBU and the consumer interfaces by setting the channel status buffer
according to the appropriate standard. When complying with the AES-EBU specification, the
CS8401 can automatically generate the local sample address, the reliability flag, and the CRC character. The parity bit is always generated and audio data is entered through a serial port configured by
a control register.
The buffer memory can operate in three modes. The address maps for these modes are shown in
Figure 9 and are selectable by a control register. In all modes, 4 bytes of user data are buffered.
This data is read cyclicly and shifted out one bit per audio sample, allowing user data to be different
in channels 1 and 2. Consequently, this buffer must be reloaded every 32 samples. In buffer mode
0, in addition to the user data buffer, one entire block of channel status data is buffered. This block
will be transmitted in both channel 1 and channel 2. Since an entire block is stored, only the data
that changes from one block to the next needs to be updated.
In buffer mode 1, eight bytes are allocated for channel status data and 16 bytes for auxiliary data.
The channel status buffer is divided into two sections. The first four locations always contain the
first four bytes of channel status, identical to mode 0, and are read once per channel status block.
The second four locations provide a cyclic buffer for the last 20 bytes of channel status data. Similar
to mode 0, transmitted channel status data will be the same for channel 1 and channel 2. The
8-81
•
I
----------- -----------
Knapp AES-EBU Paper
auxiliary data buffer is read in a cyclic manner similar to the user data buffer; however, four auxiliary
data bits are transmitted per audio sample. Since the auxiliary buffer must be read four times as
often as the user data buffer and is four times as large, they both need to be updated at the same rate.
In buffer mode 2, two 8-byte buffers are available for buffering both channel 1 and channel 2
channel status data independently. Both buffers are identical to the channel status buffer in mode 1,
except that each channel can have unique channel status data. All modes use the status register and
the interrupt pin to monitor the buffers. They can identify when the buffers are half full and empty.
When operating a digital audio interface according to the AES-EBU standard, the CS8401 can automatically generate channel status bytes 14 to 17, the local sample address, byte 22, the reliability
flag, and byte 23, the CRC character, by setting the appropriate bits in a control register. The local
sample address can be generated by a 32 bit counter incremented at every block boundary, the
reliability flag can be transmitted with bits 5 and 7 set indicating that bytes 6 to 13 and bytes 18 to
21 are unreliable, and the CRC character can be generated independently for channel I and channel 2.
The serial port is used to enter audio data and consists of three pins: SCK, SDATA, and FSYNC.
The serial port is double buffered with SCK clocking in data from SDATA, and FSYNC delineating
audio samples and may define the particular channel, 1 or 2. A large number of input formats is
supported to provide zero glue-logic interfaces to many DSP's, encoder chips, and standard audio
interfaces. This port is configured by 7 bits in a control register allowing SCK and FSYNC to inputs
or outputs, and allowing SDATA to sampled on the rising or falling edge of SCK and be entered
MSB first, MSB last, or LSB last. In most modes audio data of 16 to 24 bits may be accepted.
4 THE CS8402 TRANSMITTER
The CS8402, since it is controlled by dedicated pins, can operate without the assistance of a microprocessor or DSP. The device accepts audio samples, through a serial port similar to the CS8401, in
a limited number of formats. Several pins are dedicated to the most critical channel status bits, and
all channel status, user, and validity bits can be serially input through serial port pins. The parity bit
is always generated, and data is biphase mark encoded and driven through an RS422 line driver. The
CS8402 can operate as an AES-EBU or consumer interface transmitter. As an AES-EBU interface
device, the dedicated channel status input pins are defined according to that standard, the CRC
characters are generated, and the local sample address and the reliability flag can be generated. As a
consumer device, the dedicated channel status input pins are defined according to the consumer
standard. When transmitting data from a compact disk, a CD subcode port can accept CD subcode
data, extract channel status information from it, and transmit it as user data. Figures 10, 11, and 12
are block diagrams of Professional (AES-EBU) Mode, Consumer Mode, and CD Mode, respectively.
The audio serial port, consisting of SCK, SDATA, and FSYNC, is configured by three format control
pins, and is double buffered. Like the CS8401, SCK clocks in SDATA while FSYNC delineates
audio samples and may indicate the particular channel, 1 or 2. The format control pins select one of
seven different formats for the serial port, which allow zero glue-logic interfaces to many data converters, DSP's, and standard audio interfaces.
8-82
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Knapp AES-EBU Paper
Channel status, user, and validity bits can be entered through three serial port pins, which are sampled by FSYNC on a per sample basis. Any channel status data entered serially is logically OR'ed
with data entered though the dedicated pins or internally generated.
Although channel status can always be entered serially, Professional, Consumer, and CD Modes offer
different ways in which it can be generated. In Professional Mode, audio/non-audio mode, emphasis,
sampling frequency, and some channel modes can be controlled by dedicated pins, CRC characters
are inserted independently for both channels, and the local sample address and reliability flag byte
can be generated. As in the CS8401, when this option is enabled, bits 5 and 7 of the reliability flag
are set. In Consumer Mode and CD Mode, the copy bit, emphasis, some category codes, the generation status, and the sampling frequency can be controlled by dedicated pins. In CD Mode only, the
copy bit, emphasis, and the 2 channe1l4 channel bit are extracted from the CD subcode entered as
user data.
5 THE CS8411 AND CS8412 RECEIVERS
The CS8411 and CS8412 are receivers being developed to complement the CS8401 and CS8402,
respectively. The CS8411 has a buffer memory and parallel port for control by a processor. The
CS8412 is controlled by dedicated pins and operates as a stand alone device. Both parts will require
only external capacitors for the clock recovery, and will be able to lock to audio sample rates of
25kHz to 55kHz. They will have schmitt trigger line receivers and will detect and report various
errors conditions and information about the link, such as recovered clock frequency.
6 SUMMARY
To eliminate some of the practical problems of implementing an AES-EBU digital audio interface,
Crystal Semiconductor has defined integrated circuits which will permit economical and timely designs. Each version, consisting of a transmitter chip and a receiver chip, is targeted for a different
application. The first version, with a parallel port and internal buffer memory, is aimed at systems
requiring control of many aspects of the interface. The second version, while still able to implement
the entire interface, is more suitable for systems requiring minimal control. Presently, the transmitters are available and the receivers are defined and being developed.
7 ACKNOWLEDGMENT
The author would like to thank Clif Sanchez and the rest of the applications department at Crystal
Semiconductor for their help in defining these products and preparing this document. Mike Callahan
and Jeff Scott, also of Crystal, provided valuable assistance in circuit design.
8-83
_.--..--__.._-_
...
._.-.
Knapp AES-EBU Paper
REFERENCES
[1] R.C. Cabot,"Measuring AES-EBU Digital Audio Interfaces,"J. Audio Eng Soc.,
Vo1.38,No.6,pp.461-468,1990 June
[2] Audio Engineering Society,Inc(author),"AES Recommended Practice for Digital Audio Engineering - Serial Transmission Format for Linearly Represented Digital Audio Data,"AES3-1985(ANSI
S4.40-1985)
[3] EIA Standard RS422A,"Electrical Characteristics of Balanced Voltage Digital Interface Circuits,"Electronic Industries Assoc.,Washington,DC,1978 Dec.
[4] Electronic Industries Assoc. of Japan(author),"Digital Audio Interface," CP-340,September,1987
o
Sync.
preamble
7 8
L
S
B
3 4
L
S
Aux
B
2728
Audio Data
31
M
S V U C P
B
Validity flag
User data
Channel status
Panty bit
~
r
Figure 1. Subframe Format
I M I Channel 1 I w I Channel 2 I B I Channel 1 I w I Channel 2 I M I Channel 1 I w I Channel 2 I M I
Sub-frame
Frame 191
.I.
Sub-frame
Frame 0
1 4 - - - Start of block
Figure 2. Frame Format
8·84
Frame 1
----------- -----------
Knapp AES-EBU Paper
Byte/bit _
'"
1
~
a=1
2 :
_ :
3
0
_
3
2
I
b
I
4
c
I
1
h
d
I
6
I
g
7
e
i
I
i
4 _
5 _
5
Reserved but undelined at present
'"
Alphanumeric channel origin data
7 ::
;8 _
9
_
'"
;1~::
12 _
13 -
L-______________________________________
Alphanumeric channel destination data
L-____________________________________~
'"
1:16 ::
_
~
17 _
'"
i
Local sample address code
(32-bit binary)
L-______________________________________
~-
'"
~a:
b:
c:
d:
e:
~
Time 01 day code
1: : :
20_
21_
'"
~
(32-bit binary)
L-_______________________________________
L I_ _ _ _ _ _ _ _ _ _ _ _ _ _
~R~e~lia=b~ili~ty~I~la~gs~____________~
C~yc_l_ic_r_ed_u_n_d_a_nc~y~c_h_e_c_k_ch_a_r_ac_t_er______~
L I_ _ _ _ _ _ _ _ _ _
Use of channel status block.
Audio/Non-audio mode.
Audio signal emphasis.
Locking of source sampling frequency.
Sampling frequency.
f:
g:
h:
j:
Channel mode.
User bits management.
Use of auxiliary sample bits.
Source word length and source encoding history.
Future multichannel function description.
Figure 3. AES·EBU Channel Status Data Format
8-85
---------------------Bytelbit _
Knapp AES-EBU Paper
0
2
3
c
d
t
~~I
l
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
a:
b:
c:
d:
e:
f:
--------
a=O
b
4
5
6
7
e
o
o
h
k
Music Program Production Use
(See EIAJ CP-340)
Use of channel status block
Audio/Non-audio mode
Copy permitted
Pre-emphasis
2 ChanneV 4 Channel
Category code
g:
h:
i:
j:
k:
Generation status
Source number
Channel number
Sampling frequency
Clock accuracy
Figure 4. Consumer Channel Status Data Format
8-86
g
----------- -----------
Knapp AES-EBU Paper
jjjjjjjjjjjjj
Clock (2 times bit rate)
Source coding
Channel coding (biphase ma
Figure 5. Channel Coding
DATA BIT TIMES
I
I
I
FORM B
J
FORMM
FORMW
I
I
I
I
I
I
I
I
1
2
I
4
3
Lfl
I
I
I
fI
I
-1
I
I
I
OR
I
ilJ
I
I
I
I
I
I
I
I
2
OR
I
I
I
I
I
I
I
I
4
3
IU
J
OR
I
I
I
I
L
I
u:
I
I
W
I
I
I
I
I
Figure 6. Preamble forms. Three types sample preamble 'used are B) chan~el 1, subframe, and block
synchronizing; M) channell, otherwise; W) channel 2.
8-87
-
123
SCK
6
FSYNC
7
SDATA
8
10
C
U
11
V
9
~5
122 121
Audio
Serial Port
I
L
Registers
,I RS422 Driver ~
MUX
U r;+
~16
TXP
TXN
15
Dedicated Channel
Status Bits
CBL
Figure 7. General Description
SDATA
8
,---
SCK
6
FSYNC
7
Serial
Port
Logic
DO-D7
A4-AO
CS
RDIW
T
~
'----
21-24,1-4
9-13
14
16
M
Interrupt
Control
r
T
Read
Address
Generator
f4-
f-
'" !
Control
and Flags --<
4 X 8
Buffer
Memory
28 X 8
Jd
Reliability
Flag Byte
Local
~ Sample
Address
Counter
I
Audio
Aux
~~
~
~f--
Mux ~
Biphase
Mark
Encoder
CRC
~
U Bits
rl
Validity
~
I Preamble
f--
I
~
I Timing I
, ~IJ
Parity
5
MCK
Figure 8. CS8401 Block Diagram
8-88
g
TXP
Driver
TXM
17
----------- -----------
Knapp AES-EBU Paper
0
2
3
4
5
6
7
8
A
D
D
R
E
S
5
9
A
B
C
D
E
F
10
11
12
13
14
15
Status register 0
Control Register 1
Control Register 2
Control Register 3
User Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
LeltC.S.
Data
C.S.
Data
Lelt
C.S.
Data
Last
20 Bytes
Channel
Status
Data
I
N
E
D
1st Four
Bytes of
Right
C. S. Data
Auxiliary
Data
16
17
U
N
D
E
F
Right
C.S.
Data
18
19
lA
lB
lC
10
lE
lF
0
2
-
3
Memory Mode
Figure 9. CS8401 Buffer Memory Modes
8-89
----------- -----------.
Knapp AES-EBU Paper
M2
M1
MO
+23 +22 +21
8
SOATA
Audio
Serial
SCK
FSYNC
C
U
6
Port
7
logic
+
~
~
~f--
Regis1ers
v ~
CRE
Aux
~~
Validity
Sample
r--
Address
Counter
2
14
13
4
3
EM1
C1
lXP
Driver
Encoder
lXM
17
1
I
Preamble
I
Parity
,
f-f-f-
I
C6
C7
15
CBl
C9
L
Timing
12
-PRO__ EMO
Mark
U Bi1s
Local
-
m
Biphase
Mux --
CRC
f-.
Reliabili1y
Flag
f--f--
16
RST
I'
5
MCK
Figure 10. CS8402 Block Diagram-Professional Mode
M2
M1
MO
p3 .22 p1
SOATA
SCK
FSYNC
C
U
V
8
Audio
Serial
6
Port
7
Logic
B
Aux
i
10
.I
Registers
-I
I
C Bi1s
UBits
Validi1y
/
+5V
T
2
PRO
13
FCO
24
FC1
4
C2
1
C3
13
C8
14
C9
I
Preamble
I
Parity
,
f-f-
r
rrr-
f---
Mark
lXM
17
~
I Timing I,
i-'
15
CBl
Figure 11. CS8402 Block Diagram-Consumer Mode
8-90
lXP
Driver
Encoder
12
C15
@
Biphase
Mux
5
MCK
16
RST
----------- -----------
Knapp AES-EBU Paper
M2
Ml
MO
p3 p2 .21
8
SOATA
FSYNC
C
U
SBC
Audio
Serial
SCK
6
Port
7
Logic
10
11
Aux
.I
Subcode ~
Port
:J
1
15
'I
V
~
9
Register
I
2
T
PRO
3
24
FCO FCI
t tL
1
C2
U Bits
Validity
/
+5V
C Bits
C3
ca
C9
br~
r
~
b
I
Preamble
~
I
Parity
l--
t
12
Biphase
Mux
r--
Mark
Encoder
IS;
Driver
TXP
TXM
17
~
Timing
16
RST
5
MCK
C15
Figure 12. CS8402 Block Diagram-Consumer Mode, CD Submode
DATA BUS BIT 4
DATA BUS BIT S
DATA BUS BIT 6
DATA BUS BIT 7
MASTER CLOCK
SERIAL DATA CLOCK
FRAME SYNC
SERIAL INPUT DATA
ADDRESS BUS BIT 4
ADDRESS BUS BIT 3
ADDRESS BUS BIT 2
ADDRESS BUS BIT 1
04
05
06
07
MCK
SCK
FSYNC
SDATA
A4
A3
A2
A1
03
02
01
DO
TXP
VD+
GND
TXN
RDIWR
INT
CS
AO
DATA BUS BIT 3
DATA BUS BIT 2
DATA BUS BIT 1
DATA BUS BIT 0
TRANSMIT POSITIVE
POWER
GROUND
TRANSMIT NEGATIVE
READIWRITE SELECT
INTERRUPT
CHIP SELECT
ADDRESS BUS BIT 0
-
Figure 13. CS8401 Pinout
CS BIT 7 I CS BIT 3
PROFESSIONAL MODE
CS BIT 1 I FREQ. CTRL. 0
CS BIT 6 I CS BIT 2
MASTER CLOCK
SERIAL DATA CLOCK
FRAME SYNC
SERIAL INPUT DATA
VALIDITY INPUT
CS SERIAL IN I SC FRAME CLOCK
USER DATA INPUT
CS BIT9/CS BIT1S
C7/C3
PRO
C1/FCO
C6/C2
MCK
SCK
FSYNC
SDATA
V
C/sBF
U
C9/C15
TSTIFC1
M2
M1
MO
SAMPLE ADDR. I FREQ. CTRL 1
SERIAL PORT MODE SELECT 2
SERIAL PORT MODE SELECT 1
SERIAL PORT MODE SELECT 0
TXP
TRANSMIT POSITIVE
POWER
VD+
GND
GROUND
TRANSMIT NEGATIVE
TXN
RST
MASTER RESET
CBLlSBC CS BLOCK OUT I SC BIT CLOCK
EMO/C9
EMPHASIS 0 I CS BIT 9
EM1/CS
EMPHASIS 1 I CS BIT 8
Figure 14. CS8402 Pinout
8-91
- ... -_......--------_-------
Knapp
-Notes-
8·92
AES~EBU
Paper
....................
~
~~~.
~
~
~~
AES/EBU Interface
Semiconductor Corporation
Application Note
Overview of Digital Audio Interface Data Structures
CHf Sanchez & Roger Taylor
The following information is provided for convenience, but by no means constitutes the entire
specification. Also included is information from
the IEC 958 and the new AES3-199x and TC84
documents. The AES3-199x and TC84 documents
have not received approval as of the printing of
this data sheet. To guarantee conformance, a copy
of the actual specification should be obtained from
the Audio Engineering Society or ANSI (ANSI
S4.40-1985) for the AES3 document, and the International Electrotechnical Commission for the
IEC 958 document.
The AESIEBU interface is a means for serially communicating digital audio data through a single
transmission line. It provides two channels for audio
data, a method for communicating control information, and some error detection capabilities. The
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
control information is transmitted as one bit per
sample and accumulates in a block structure. The
data is biphase encoded, which enables the receiver to extract a clock from the data. Coding
violations, defmed as preambles, are used to identify sample and block boundaries.
Frames Sub-frames and Blocks
An audio sample is placed in a structure known as
a sub-frame. The sub-frame, shown in Figure 1,
consists of 4 bits of preamble, 4 bits of auxiliary
data, 20 bits of audio data, 3 bits called validity,
user, and channel status, and a parity bit. The preamble contains biphase coding violations and
identifies the start of a sub-frame. The audio sample word length can vary up to 24 bits and is
transmitted LSB first. If the word length is greater
than 20 bits, the sample occupies both the audio
MAR '92
AN22REV1
8-93
-
---------------------bit
I~
34
AESIEBU Interface
Sub-frame - - - - - - - - - - - - - · · - - > j 0 l
2728293031
Audio Data
MSB
78
I Preamble I Aux Data ILSB
Iviulcipi
V.lld~ ~
1
User Data
1)
Channel Status Data
Parity Bit
Figure 1. Sub-frame Format
k Frn~
'"
--~--~--
----t~---Frn~' ~
Frame 0
Start of Channel Status Block
Figure 2. FrameIBlock Format
and auxiliary data fields. If it is 20 bits or less,
the auxiliary field can be used for other applications such as voice. The parity bit generates even
parity and can detect an odd number of transmission errors in the sub-frame. The validity bit,
when low, indicates the audio sample is fit for
conversion to analog. The user and channel
status bits are sent once per sample and, when
accumulated over a number of samples, define a
block of data. The user bit channel is undefmed
and available to the user for any purpose. The
channel status bit conveys, over an entire block,
important information about the audio data and
transmission link. Each of the two audio channels has its own channel status data with a block
structure that repeats every 192 samples.
As shown in Figure 2, two consecutive subframes are defined as a frame, containing
channels A and B, and 192 frames define a
block. The preambles that identify the start of a
sub-frame are different for each of the two channels with another unique one identifying the
beginning of a channel status block.
Modulation and Preambles
The data is transmitted with biphase-mark encoding to minimize the DC component and to
allow clock recovery from the data. As illustrated in Figure 3, the 1's in the data have
transitions in the center, and the O's do not, after
biphase-mark encoding. Also, the biphase-mark
data switches polarity at every data bit boundary.
Since the value of the data bit is determined by
whether their is a transition in the center of the
bit, the actual polarity of the signal is irrelevant.
Each sub-frame starts with a preamble. This allows a receiver to lock on to the data within one
sub-frame. There are three defined preambles:
Clock
(2 times bit rate)
~~~~~~~~~~~~~
'1'0'0'0'1'1'
Data
~::~
'~I'
I
nil.
,
,
I
nn
Biphase-Mark
II
Data.JU
LJ U U L
:1 0:1 1:0 0:1 1:0 1 :0 1 :
Figure 3. Biphase-Mark Encoding
8-94
AN22REV1
----------------------
AES/EBU Interface
Channel
Biphase Patterns
X 11100010 or 00011101
y 11100100 or 00011011
Z 11101000 or 00010111
'1 1 '10'00'1 0'
Ch.A
Preamble X
Ch. B
Ch. A & C.S. Block Start
~I
'1 1 '1 0'01 '0 0'
Preamble Y
~-:-t-r
-.J
-I
,LJ LJ
Table 1. Preambles
one for each channel and one to indicate the beginning of a channel status block (which is also
channel A). To distinguish the preambles from
arbitrary data patterns, the preambles contain
two biphase-mark violations. Biphase-mark data
is required to transition at every bit period, but
each preamble violates that requirement twice. In
Figure 3 each bit boundary, indicated by the
dashed lines, contains a transition in the biphase
Preamble Z
Figure 4. Preamble Forms
data. Each preamble shown in Figure 4 has two
bit boundaries with no transition, which enables
the receiver to recognize the data as a preamble.
Table 1 lists the preamble biphase-mark data patblock
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
---.
o
2
PRO=1
J
Audio I
Channel Mode
AUX Use
Reference
I
4
3
Emphasis
I
1
6
5
Fs
I Lock
User Bit Management
Word Length
Reserved
Reserved
Reserved
1
1
Reserved
7
I~t
7
15
23
31
39
47
55
-
Alphanumeric channel origin data
87
Alphanumeric channel destination data
119
Local sample address code
(32-bit binary)
151
Time of day code
(32-bit binary)
L-______~R~e~se~rv~e~d~________~______~R~e~l=ia~bi~lit~y~fl=ag~s~____-"1183
L-______________.-:C=.,y~c:::.lic:..:.:re:.:d=un:.::d:.:a:::n=cy~=ch~e:.:c.:.:k..::c.:.:ha=r=act=er~________---......J1191
Figure 5. Professional Channel Status Block Structure
AN22REV1
8-95
___-_.
.. ...
.-_--_
....-.
.....
AES/EBU .Interface
terns and what each designates. Since biphasemark encoding is not polarity conscious, both
phases are shown in the table. Preambles "X"
and "Y" indicate a sub-frame containing channels A and B respectively. Preamble "Z" replaces
preamble "X" once every 192 frames to indicate
the start of a channel status block.
There are two channel status blocks, one for
channel A and one for channel B. Since there are
192 frames in a block, each channel has a channel status block 192 bits long. These
192 channel status bits in a block can be arranged as 24 bytes. The blocks have one of two
formats, professional or consumer. The first bit
of the channel status block defines the format
with 0 indicating consumer and 1 indicating professional.
Channel Status Block - Professional Format
Setting the fIrst bit of channel status high designates the professional or broadcast format. The
channel status block structure for the professional format is illustrated in Figure 5 and shows
bit 0 of byte 0, PRO, to contain a one. Tables 2
and 3 list the bits in each byte and their meaning. The areas designated "reserved" in the
fIgures and tables, are currently not specified and
must be set to 0 when transmitting. Most of the
professional format data was obtained from the
AES3-1985 document, and information from
AES3-199x. Since the AES specification is currently being updated, the accuracy of this data is
not guaranteed.
BYTE 1
BYTE 0
bit
0
PRO = 1
-----~o-----,-c:~o~n~s-u-m~e-r-u-s-e--m~c~h-a-n-ne~l~s~ta~t~us~bl~oc~k~1
. . . . . . . . . . . .-
Professional use of channel status block
1
bit
Audio
--0--- ··········~;;~~~I~~~i;;
Man. override disabled
000 1 Two-channels.
...................................................... ...................................................-............ .
,
Non-Audio
None. Rec. manual override disabled
o
50/15
I
X X X
~S.
"
o 0 1 O~i~~I~~~li~~~I:l\t1li~.()~~rri~~~i~EI:~I~~
o 0 1
Primary/Secondary (Ch. A is primary).
Manual override disabled
bits 2 3 4
Encoded audio signal emphasis
o 0 0 ······E;:;;ph~~i~~~ii~di~~i~d:R;;~i~~;
defaults to no emphasis with manual
override enabled
o 0
bits 0 1 2 3 Channel Mode
_____________.___________ _
OOOOM~de not i~di~~i~d:R~~~i;;;;~ default
to 2-channel mode. Manual override
enabled
o
......
Rec. manual override disabled
CCITT J.17 . Rec. man. override
disabled
..........
.............
All other states of bits 2-4 are reserved
0 0 Stereophonic. (Ch. A is left)
Manual override disabled.
o 1 0 1 ..............
Reserved
for user defined applications
-........................................................................................................................
o
1
0 ..... f'I~~~"'~~f()r...~s~~..~~fi.~~~liPpli~El:ti()~~ ...
1 Vector tobyte 3. Reserved
X X X X All other states of bits 0-3 are reserved.
bits 4 5 6 7 User bits management
o 0 0 0 Default, no user info indIcated
o 0 0
Fs: Sample Frequ~.~.~y................. __
bits 6 7
oON~i·i~di~~i~d:-R~ceiver default to 48 kHz
li~~lT1lin~lil()~~~ri~~()rEl~t()~~t~~li~I~~
o 148kHz. Man. override or auto disabled .......
1 0
192 bit block structure
Preamble 'Z' starts block
o 0 1 0 Reserved
o 0 1 1 User defined application
X X X X All other states of bits 4-7 are reserved.
~.l ~.~.~.: ~E1~:()~~~ri~~.()r.E1~t() ~.i~li?I~~
....
...
...
32 kHz. Man. override or auto disabled
1••••
Table 2. ProCessional Channel Status bytes 0-1
8-96
AN22REV1
----------------------
AES/EBU Interface
BYTE 2
BYTES 6 - 9
AUX: Use of auxiliary sample bits
Alphanumeric channel origin data
000
Not defined. Maximum audio word length
is 20 bits
7-bit ISO 646 (ASCII) data with odd parity bit. First character in message is byte 6. LSB's are transmitted first.
o
0 1
Used for main audio. Maximum audio
word length is 24 bits
0 1 0
Single coordination signal. Max. audio
word length is 20 bits
0 1 1
User defined application
X X X
All other states of bits 0-2 are reserved
345
Source word length
Max. audio based on bits 0-2 above
bits 0 1 2
..
...
bits
BYTES 10 -13
Alphanumeric channel destination data
7-bit ISO 646 (ASCII) data with odd parity bit. First character in message is byte 10. LSB's are transmitted first.
BYTES 14-17
Local sample
address code (32-bit binary)
--_
- - - - _ . - - _ . _ . _..._...._._-
Max audio 24 bits Max audio 20 bits
..
0
o
Not Indicated
Not Indicated (default)
o
0 1
23 bits
19 bits
0 1 0
22 bits
18 bits
0 1 1
21 bits
17 bits
Time-of-day sample address code (32-bit binary)
1 0 0
20 bits
16 bits
Value is of first sample of current block. LSBs are transmitted first.
1 0 1
24 bits
20 bits
XXX
All other states of bits 3-5 are reserved
bits 6 7
.......
XX
0
BYTES 18 - 21
BYTE 22
------:r··-----bits 0 1 2 3
............. [Reserved
X X X X Reserved
bit
BYTE 3
bit
0 1
................•
Digital audio reference signal
per AES11-1990
Unreliable
5
Channel status bytes 6 to 13
1
Unreliable
Channel status bytes 14 to 17
0 1
Grade 1 reference signal
1
1 0
Grade 2 reference signal
1 1
Reserved
bit
T-
...
- ._.-_._--"."_.--.
Channel status bytes 18 to 21
....
····I:~~:I~~:le
r Reserved
--··--T····-··---··-XXXXXXX Reserved
-.---~
Reliable
7
0
..
Unreliable
......
1
BYTES
0-7
......- - - - - - -
I Reliable
6
0
XXXXXX
bits
bit
. ...
2-7
Reliable
1
Not reference signal (default)
0 0
·If"'' ""'~ byI".~
0
BYTE 4
bits
4
0
Vectored targe_t_b-'-y_te________ _
bits 0-7
-xXXXXXXTR-;;;;;rved--
bits
.. _ - - - - - -
Value is of first sample of current block. LSBs are transmitted first.
......
BYTE 23
CRCC:
Cyclic redundancy
check character
...........................
.................................... .
CRCC for channel status data block that uses bytes 0 to
22 inclusive. Generating polynomial is
G(x) = XB + X4 + X3 + X2 + 1
with an initial state of all ones.
Table 3. Professional Channel Status Bytes 2-23
AN22REV1
8-97
-
----------- -----------
AES/EBU Interface
Channel Status Block - Consumer Format
Setting the first bit of channel status low designates the consumer format. The channel status
block structure for the consumer format is illustrated in Figure 6 with the bit descriptions in
Tables 4 and 5. All areas listed as "reserved"
must be transmitted as a O. The data for this format was obtained from the EIAJ CP-340 and the
IEC 958 with some information from TC84
which is a proposed amendment to IEC 958 and
has not received approval yet. As with the professional format, since this format is currently
changing, the accuracy of the data listed cannot
be guaranteed.
In the consumer format, bit 0 must be O. If bit 1
is set to 1 defining the data as non-audio, then
byte/bit
t _~I
;1
-2 -3 -~
--------------------
o
PRO 0
bits 3-5 are redefined (see Table 4, byte 0).
Bits 6 and 7 of byte 0 define the mode, and only
one mode is presently defined, mode = 00. This
mode defines the next three bytes as listed in
Figure 6. Most of byte 1 defines the category
code. The first 3 to 5 bits define the general
category. Under the laser-optical category is
compact disk (cat. code 1000000). This format
defines some of the U channel bits and the CD
subcode port. More information can be obtained
from the CP-340 or IEC 958 documents.
Currently the standards committees are trying to
define a minimum implementation as well as
levels of implementation of channel status data.
A scheme for providing copy protection is also
currently being developed. It includes knowing
6
4
5
7
Emphasis
Mode
I
Category Code
I L
Source Num.
Channel Num.
Reserved
Fs
I Clock Acc.
2
3
I Audio I Copy I
1
1
block
bit
I t
7
15
23
31
4
39
5
6
Reserved
7
8
9
10 - 11
12 ----+
13
14
15
16
17
18
19
20
21 -----.
22 -----.
23
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~191
---~
8-98
Figure 6. Consumer Channel Status Block Structure
AN22REV1
.-_
._.-.
_
..--__.._-_
...
AES/EBU Interface
BYTE 1
BYTE 0
Category Code
bits 0 1 2 3 4 5 6 ........................
0
o
0 0 0 0 0 General
0 0 1 Experimental
XXX Reserved
0 0 0 1 X X X Solid state memory.
Broadcast recep. of digital audio
0 0 1 X X X X ................................................................................................................
~~-:---e:;-~~
0 0
None - 2 channel audio
o
0
50/15 IJS - 2 channel audio
o
o
Reserved - 2 channel audio
Reserved - 2 channel audio
X X 1
Reserved - 4 channel audio
o
bits 3 4 5
0 X X X X Digital/digital converters
0
1 0 0 X X AID converters w/o copyright
1 X X AID converters w/ copyright
(using Copy.and~~it~)
recep...............................
of digital audio
0 1 1 1 X X X Broadcast
.......
bits______________
3 4 5
Pre-emphasis
-. ..if_______
bit 1 is 0 (dig.
audio)
....
'---=--_
_c-j
o
0
0 0 X X X X Laser-optical
.......
0 1 X X X X Musical Instruments, mics, etc.
.............................
OX X X XIIt11ignetict~p~?rdi~~
1 X X X X Reserved
bit
7
f····················································,..................................................................
000
XXX
bits 6 7
o
0
XX
Digital data
All other states of bits 3-5 are reserved
L: Generation Status.
Only category codes: 001 XXXX,
0111XXX,
100XXXX
if bit 1 is 1 (non-audio)
o
Original/Commercially pre-recorded data
~?i~~i~~!i~~.~!1~!~~~~!~ti?~~~~i~~Elr.
Mode
Mode
0 (defines......................
bytes 1-3)
......
.....................
......
All other category codes
. ........... .
All other states of bits 6-7 are reserved
o
No indication or1~t~~~Elr1iti~~~r~i9~~r
Original/Commercially pre-recorded data
BYTE 1 - Category Code 001
bits 3 4 5 6~~~1i~~.~~!_!~~~!!~~~f_~i~!!1iI1i~_~i~_
o 0 0 0 Japan
o
0 1
United States
o 0 0 Europe
000
The subgroups under the category code groups listed
above are described in tables below. Those not listed
are
reserved.
The Copy and L bits form a copy protection scheme for
original works. Further explanations can be found in the
proposed amendment (TCB4) to IEC-95B.
Electronic software delivery
X X X X All other states are reserved
BYTE 1 - Category Code 010
bits 3 4 5 6 .........................................................
Digital/digital conv.
& signal processing
_...............................-......._.....................................
BYTE 1 - Category Code 100
bits
3 4 5 6 Laser Optical
..-...-.........................................._..........-......................................._-
o
........................_.. _._ .....
0 0 0 CD - compatible with IEC-90B
1 0 0 0 CD - not compo with IEC-90B
(magneto-optical). ...
........
o0
o0
o
0 0 PCM encoder/decoder
1 0 Digital
sound...........
sampler
........
.
......
0 0 .........................................................................
Digital signal mixer
1 1 0 0 Sample-rate converter
....
X X X X All other states are reserved
X X X X All other states are reserved
Table 4. Consumer Channel Status Bytes 0 and 1
AN22REV1
8-99
-
.._-_
.-_
_
..--_._.
_...-.
AES/EBUlnterface
BYTE 1 - Category Code 101
BYTE 1 - Category Code 110
bits
3 4 ....5- ......6- --Musical
Instruments,
mics, etc.
.... _-_ ... _._ ..... _
...
....-..........---..-.....
. ........._--_........... . ..............•..........__ ..
o 0 0 0 .................................................
Synthesizer
bits 3 4 5 6 Magnetic tape or disk
-.~~-
o0
0 0 DAT
1 0 0 0 Microphone
1 0 0 O[)iQitfllfl~~i()~()~~~y100 dB
Steven R. Green, Steven Harris and Brent Wilson
Crystal Semiconductor Corporation
PO Box 17847
Austin, TX 78760, USA
A recently released low distortion and high dynamic range Delta-Sigma DAC achieves a dynamic
range of 107 dB and full-scale Total Harmonic Distortion + Noise (THD+N) of 101 dB. This level
of performance can be achieved with an understanding of I-bit technology and thoughtful system
design. The development of a DAC system employing this device will be discussed including the
use of optocouplers, clock jitter attenuator, off-chip I-bit latch and analog filtering.
1.0 Introdnction
The performance capabilities of integrated audio Digital-to-Analog-Converters (DAC) continues to
advance. Achieving these capabilities in a system requires attention to details that only a few years
ago were inconsequential. To put this into perspective it is interesting to compare the noise requirements of analog and digital systems. The dynamic range of analog systems can often exceed
110 dB with output capabilities of 20 dBV or greater, equating to a system noise floor of approximately 30 flY. Integrated DACs generally have a maximum analog output of 6 dBV which
requires a noise floor of 10 flY to achieve a 106 dB dynamic range. Not only is this less than
one-third of the total noise allowable for a 110 dB analog system but must also be accomplished in
the presence of MHz region sampling clocks.
The CS4303, Figure 1, is an example of a high performance DAC capable of a 107 dB dynamic
range. The goal was to develop a complete DAC system incorporating a CS84I2 AES/SPDIF
Digital Audio receiver which would realize the performance capabilities of the CS4303. This paper
will present critical design considerations and the DAC system architecture including jitter attenuation, optocoupling and analog filtering. The primary purpose of using delta-sigma modulation
techniques is to avoid the limitations of laser trimmed resistive DAC architectures [1] by using an
This paper was presented at the 93rd AES Convention, San Francisco, October 1992, Preprint #3416
8-101
-
----------- -----------
Green CS4303 AES paper
inherently linear I-bit DAC [2]. The advantages of a I-bit DAC include:
1. Ideal differential linearity
2. No distortion mechanisms due to resistor matching errors
3. No linearity drift over time and temperature due to variations in resistor values.
2.0 I-Bit Conversion and the CS4303
The CS4303 DAC includes a digital interpolation filter, a delta-sigma modulator and a I-bit DAC
as shown in Figure 2. An understanding of the operation and capabilities of each stage is crucial to
an optimum design and define the system performance goals.
2.1 Digital Interpolation Filter
Audio data is input to the digital interpolation filter which increases the sample rate by a factor of
8 and eliminates images of the baseband audio signal which exist at multiples of the input sample
rate, Fs (Figure 3a). This allows for the selection of a less complex analog filter based on out-ofband noise attenuation requirements rather than anti-image filtering. Following the interpolation
filter, the resulting frequency spectrum (Figure 3b) has images of the input signal at multiples of
eight times the input sample rate, 8Fs. These images are removed by the analog filter required to
filter the I-bit data.
The dynamic range of an interpolation filter is limited by a finite number of data bits which is the
source of truncation and quantization noise. The CS4303 interpolation filter data paths are 18-bit
with 19-bit filter coefficients which equates to a dynamic range of better than 107 dB over the
audio bandwidth. The interpolation filter has a -3 dB point of 0.4896Fs (23.5kHz for Fs equal to
48kHz) with a maximum passband ripple of +/- 0.0002 dB. It achieves this amplitude response
while maintaining perfectly linear phase throughout the passband. Any deviation of the system
from flat amplitude and linear phase response will originate in the analog filter.
2.2 Delta-Sigma Modulator
The interpolation filter is followed by a fifth-order delta-sigma modulator which converts the 8Fs
multi-bit interpolation filter output into I-bit data at 64 times Fs (64Fs). The ratio of the number of
ones to the number of zeroes in the output is referred to as the one's density. The one's density
will track the input code between the extremes of 70% for positive and 30% for negative full-scale
with a mid-scale of 50%. The frequency spectrum of the I-bit delta-sigma modulator output is
shown in Figure 4 for an Fs of 48 kHz. Note that the inband noise peaks are well below -130 dB
and yield a 120 dB dynamic range over the 20kHz audio bandwidth.
2.3 I-Bit DAC
This is the point where the signal returns to the analog domain, albeit in the MHz range. There are
several important considerations since the ultimate performance of a delta-sigma DAC is dependent on the purity of the I-bit data. The signal from the I-bit DAC is filtered by an external analog
8-102
----------- -----------
Green CS4303 AES paper
filter to produce the audio output and any errors that are introduced into the I-bit signal due to
noise from the voltage references or clock jitter will degrade the performance.
The delta-sigma modulator I-bit output and the master clock control the switching between two
reference voltages. Since these reference voltages are directly connected to the output of the DAC,
any noise or interference on the references will be directly applied to the analog filter. Harris [3]
discusses the effects of voltage reference noise for converters.
There is also an interesting relationship between variations in the amplitude of the reference voltages due to the I-bit data. If the reference voltages are allowed to be modulated by the I-bit data
due to loading on the output or insufficient power supplies, second harmonic distortion and possibly tones will be generated. It is therefore critical that the reference voltages be stable and free
from noise to achieve optimum performance.
To minimize distortion it is critical that the energy within each pulse be independent of a previous
or next state. In Figure 5a, notice that the energy within the bit-period is affected by finite rise and
fall time while in Figure 5b, the energy is not affected by either. To prevent this type of error the
CS4303 utilizes return-to-zero coding where each occurrence of a I is 75% high and returns low
for 25% of the bit period as shown in Figure 5c. This technique ensures that the energy within
each I includes the effects offinite rise and fall times regardless of the previous or next state.
There is an additional situation that can add uncertainty to the energy contained in each occurrence
of a 1. Each data bit is output from the I-bit DAC for a period of time which is defined by the
master clock. Variations in this timing due to clock jitter will lead to variations in the energy
within pulses and directly translate to errors in the integrated signal. Harris [4] investigated the
affects of clock jitter for analog-to-digital-converters and these effects are also applicable to digital-to-analog-converters. The CS4303 incorporates a differential output to maximize the output
level and minimize the amount of gain required in the analog filter. Figure 7 shows each output as
well as the differentially summed output for an arbitrary I-bit data stream.
3.0 System Design
To obtain maximum performance from the CS4303, exceptionally clean references for the analog
signal and a very low jitter clock are mandatory. Since the output stage on the CS4303 is on the
same die as the interpolation filter and other logic, corruption of the output stage supplies and
degradation of the clock edges is likely. To avoid these effects, optocouplers are used to create a
completely isolated set of one's density data. This data is re-timed using a CMOS latch, clocked
by a very low jitter clock. The power supplies to the latch are independent and very clean. Figure
7 shows the block diagram of the entire DIA processor board.
3.1 CS8412 Digital Audio Receiver
The system receives and decodes standard AESIEBU and SIPDIF data formats using a CS84I2
Digital Audio Receiver. The output from the CS84I2 is a serial bit clock, serial data, a word clock
and a 256Fs master clock. The operation of this device is covered in detail in Reference [5].
8-103
-
--- -------------------
Green CS4303 AES paper
3.2 Optocouplers
Optocouplers provide effective isolation between the analog circuitry and digital circuit noise.
Hewlett-Packard HCPL-7101 optocouplers were chosen since they have built in CMOS input buffers and operate at 40MHz. The high output slew rate yields minimum corruption of the signal
edges and low jitter on the clock. The input side of the optocouplers is well decoupled, since the
LED's create significant current spikes. The output side of the optocouplers is referenced to analog
ground, and has it own +5V power regulator. A large physical gap between the pins of each side of
the optocoupler package was maintained on the circuit board, with no traces or ground plane
reducing the physical spacing. This ensures maximum digital to analog isolation.
3.3 I-Bit Latch
The external CMOS latch used to time the data is a 74ACl1074 from Texas Instruments. This dual
D-type flip-flop was chosen because of its center power and ground connections, which reduce
internal inductances and the possibility of the supplies being modulated by the output signal. The
device also has a high output drive capability, which is important since we wish to minimize the
input impedance of the analog filter for noise considerations.
The supplies to the latch are the voltage references for the I-bit data. Extreme care must be taken
to optimize the supply decoupling with low value high frequency capacitors positioned very close
to the supply and ground pins. High value capacitors significantly reduce low frequency noise in
the latch output data. The capacitors not only act as decoupling for the latch but also serve as a
power supply noise filter.
Good latch supply decoupling is also important to minimize 2nd harmonic distortion. As the one's
density of the data varies, then the loading on the latch supply varies. If the supply is inadequately
decoupled then the supply voltage will change in sympathy with the signal. This is effectively
multiplying the signal by itself, yielding 2nd harmonic distortion.
There are significant advantages in the use of a dual flip-flop. Due to the differential nature of the
DAC output, it is possible to minimize thermal gradients within the latch and improve distortion
performance. This can be accomplished by using a separate dual latch for each channel.
The latch clock rising edge is timed so that the set-up and hold time requirements for the data
inputs are met with a generous margin.
3.4 Clock Jitter Attenuator /VCXO
Clock jitter can originate from the original AESIEBU signal, the VCO in the CS8412, and from
the optocouplers. To reduce the clock jitter as much as possible prior to the latch, a Phase Lock
Loop (PLL) is used as a jitter attenuator. Figure 8 shows the schematic of the latch clock generator/jitter attenuator. The PLL consists of a phase detector, a voltage controlled oscillator and a
loop filter.
8-104
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Green CS4303 AES paper
The phase detector was implemented using an 74AC11086 exclusive or gate. This phase detector
introduces a 90 degree phase shift, which results in the correct timing of the output clock for the
latch. The phase detector is also inherently free from hysteresis improving jitter performance.
The requirement for a low jitter clock led to the choice of a voltage controlled crystal oscillator
(VCXO). Devices made by Raltron have been shown to have low intrinsic jitter. This allows the
use of a low frequency loop filter, since the PLL is not required to reduce inherent jitter in the
oscillator.
The loop filter is a single pole RC network. The design procedure is as follows:
1) A phase margin of 60 degrees is chosen. This yields a critically damped response.
2) The PLL open loop gain is calculated, by multiplying the phase detector gain and the VCXO
gain. G = Kd. Ko = Vcc/n . 2n (615) =6150 rad/sec. This is the unity gain frequency.
3) Using an RC time constant equal to the inverse of the unity gain frequency will yield a 45
degree phase margin. A 60 degree phase margin is 15 degrees greater than 45 degrees. The slope
of the single pole RC filter is 45 degrees/decade. Therefore, the corner frequency of the loop filter
needs to be increased by a factor of 15/45 decades. This yields a corner frequency of 2.38 kHz.
4) A 0.1 IJF capacitor was chosen because capacitors behave most ideally at that value. This leads
to choosing a 681 ohm resistor.
Power for the phase detector and VCXO must be very clean in order to avoid output clock jitter.
Independent +5V regulators for the VCXO and phase detector ensure no coupling between the
VCXO and phase detector output transitions via the supply. The layout of the PLL should be such
that the loop filter is close to the VCXO. This minimizes the possibility of induced noise into the
control pin on the VCXO.
3.5 Analog Filter
The selection of the analog filter transfer function is based on the optimization of out-of-band
noise attenuation, passband amplitude and phase requirements. The filter must be implemented not
only to minimize noise and distortion but also to properly load the DAC and- to accept the high
frequency I-bit data avoiding slew rate limitations. The primary function of the analog filter is to
attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The computer simulated frequency spectrum of the I-bit delta-sigma modulator output is shown in Figure 4
for an Fs of 48 kHz. Note that the out-of-band noise begins to increase beyond 20 kHz and it is
the attenuation of this out- of-band noise which must be considered. Due to the sharp increase in
noise near the passband, a compromise must be made between the goals of linear phase, a flat
passband and the attenuation of out-of-band noise.
A Butterworth function has the desired maximally flat passband response, out-of-band attenuation
and acceptable phase characteristics. Figures 9-11 show the results of computer simulations dem8-105
-
----------- -----------
Green CS4303 AES paper
onstrating the out-of-band noise attenuation of 3, 5 and 7 pole Butterworth filters where the filter
corner frequencies were selected to achieve a maximum attenuation of .2 dB at 20kHz.
The circuit of Figure 12 is a 5-pole Butterworth modified to realize a 6-pole response. The real
pole of .the standard Butterworth configuration has been altered and complemented with an additional real pole. These poles have been positioned for the frequency response of Figure 13-14 and
the group delay of Figure 15. The out-of-band noise attenuation is demonstrated in the system
performance plot of Figure 16. Notice that the noise peaks remain well below 100 dB. Implementing a pole as a passive RC in the input of the analog circuit along with the 40 V/Jls slew rate of
the Burr-Brown OP-627 op-amp, eliminates slew rate related distortion. The architecture of Figure
12 also provides matched loading for the latch outputs, as well as adding the noise-free pole for
additional out-of-band noise attenuation.
4.0 System Performance Measurements
Figures 9-11 raise an interesting question concerning Dynamic Range and THD+N specifications.
The specifications for each plot over a 20kHz bandwidth are identical, but the dynamic range
differs. by 46 dB over the 120kHz bandwidth. Therefore, the filter used to band-limit the measurement will greatly affect the results. As an example, the 22kHz band-limiting filter of the Audio
Precision System One is insufficient to compare the in-band performance between either a 3, 5 or
7 pole system. The dynamic range and THD+N specifications for the CS4303 DAC system were
obtained by digitizing the output with a CS5327 ADC and performing an FFT on the data. This
allows the measurement bandwidth to be set precisely at 20kHz and remove out-of-band influences.
The following collection of CS4303 measurement plots (IWR = 48 kHz) were taken with an Audio
Precision Dual Domain System One. All FFT plots are 16,384 point. Several of the plots are
influenced by inadequate dithering of the test signal. Lipshitz [9] discusses these effects.
Figure 16 shows the unmuted noise. This data was taken by feeding the CS4303 all zero's. This
plot shows the noise shaping characteristics of the delta-sigma modulator combined with the analog filter.
Figure 17 shows the system frequency response with a 48 kHz input word rate. The 0.2 dB rise at
18 kHz is the result of component tolerances.
Figure 18 shows the A-weighted THD+N vs signal amplitude for a dithered 1kHz input signal.
The small variations in THD + N at around -70 dB are caused by inadequate dithering of the test
signal. The System One was set to 18-bit triangular dither.
Figures 19 and 20 show the fade-to-noise linearity. The input test signal is a dithered 500 Hz sine
wave which gradually fades from -60 dB level to -120 dB. During the fading, the output level
from the CS4303 is measured and compared to the ideal level. Notice the very close tracking of
the output level to the ideal, even at low level inputs of -90 dB. The gradual shift of the plot away
from zero at signal levels < -100 dB is caused by the background noise starting to dominate the
8-106
--- -------------------
Green CS4303 AES paper
measurement. Figure 19 shows the result with 18-bit dithered data. The 1 dB shift at -95 dB is due
to inadequate dither. Figure 20 shows the result with 16-bit dithered data.
Figure 21 shows a 16K FFT plot result, with a 1 kHz -100 dB 17-bit dithered input. Notice the
lack of distortion components.
Figure 22 shows the monotonicity test result plot. The input data to the CS4303 is + 1 LSB,
-1 LSB four times, then +2 LSB, -2 LSB four times and so on, until +10 LSB, -10 LSB. This data
pattern is taken from track 21 of the CD-1 test disk. Notice the increasing staircase envelope, with
no decreasing elements. Notice also the clear resolution of the LSB. For this test, one LSB is a
16-bit LSB.
The following tests were done by filtering the analog output of the CS4303 with the System One
analyzer 1 kHz notch filter to reduce the peak signal level. The resulting signal was then amplified
and applied to the DSP module, avoiding distortion in the System One AID converter.
Figure 23 shows a 16K FFT Plot with a 1 kHz, 0 dB input. Notice the low order harmonic
distortion at < -100 dB.
Figure 24 shows a 16K FFT Plot with a 1 kHz, -10 dB input. Notice the almost complete absence of distortion, with a small residual 2nd harmonic below -120 dB.
5.0 Conclusion
An 18-bit delta-sigma DAC system achieving 104 dB dynamic range and a full-scale THD+N of
101 dB has been discussed. Many subtle implementation details have also been revealed. Measurements and listening tests confirm state-of-the-art performance.
6.0 Acknowledgments
Many thanks to Eric Swanson and Jeff Scott of Crystal Semiconductor for their invaluable insights, suggestions and encouragement. Jamie Dugan for his patience through the many edits and
revisions.
7.0 References
[1] J.E. Johnston, "Self-Calibrating AID Converter Chips Overcome Laser Trim Technology Limitations", Hybrid Circuit Technology, July 1990
[2] N.S. Sooch, J.W. Scott, T. Tanaka, T. Sugimoto, C. Kubomura, "18-Bit D/A Converter with Integrated Digital and Analog Filters",91st AES Convention, October 1991, New York,
Pre-print#3113(y-1)
8-107
-
----------- -.----------
Green CS4303 AES paper
[3] S. Harris "How to Achieve Optimum Performance from Delta-Sigma AID & D/A Converters",
92nd AES Convention, October 1992, San Francisco·
[4] S. Harris "The Effects of Sampling Clock Jitter on Nyquist Sampling Analog- to-Digital Converters, and on Oversampling Delta-Sigma ADCs" J.Audio Eng. Soc., Vol. 38 No. 7/8, 1990
July/August
[5] CS8411\12 Data sheet, CrystalSerniconductor Corporation
[6] Reference Data for Radio Engineers (Fourth Edition), International Telephone and Telegraph
Corporation
[7] A.B. Williams, "Electronic Filter Design Handbook", McGraw-Hill
[8] C.S. Lindquist, "Active Network Design with Signal Filtering Applications", Steward & Sons
[9] S.P. Lipshitz, et al, "Quantization and Dither: A Theoretical Survey" J. Audio Eng. Soc., Vol.
40 No.5, 1992 May
8-108
----------- -----------
Green CS4303 AES paper
LRCK SICK DIF1 DIFO
SDATAI
22
DVDO
AGND2
AGND1
XGND
VA+R
DOR+
DORDOL+
DOLAGNDL
VA+L1
VA+L2
DZF
MUTE
RST TST1 TST2
XTI XTO CKS SCKO XDGND XVD+
Figure 1. CS4303 Block Diagram
1 B"It
18 Bit
18 Bit
8x Interpolation
Digital Input
f8
8 f8
5th-order
64 f8
1 Bit
Delta-Sigma
~
Filter
D/A
Modulator
r-------
Figure 2. CS4303 Architecture
(dB)
=
.
.
.
-
~
~
.
.
fa
~
.
~~~--~~~--+-~~--~~~--+-~~--~~~--fa~~~~--------'
24 Fs
2Fs
4Fs
6Fs
8Fs
~
16Fs
f (kHz)
Figure 3a. Interpolation Filter Input Spectrum
0
~
fafa
fa
(dB) nL..--I.______________.....I..-+---I._ _ _.......-+-......._ _--.
24
8Fs
~
~~
16Fs
f (kHz)
Figure 3b. Interpolation Filter Output Spectrum
8-109
----------- -----------
Green CS4303 AES paper
0.--------------------------------------.
~20
---------------------------------------
-40
iii'
-60
-!l::I
-80
~
:s -100
g'
::::i -120
-140
-160
-180
-200
o
20
40
60
80 100 120 140
Frequency (kHz)
160
180
Figure 4. 48 kHz Delta-Sigma Modulator Output Spectrum
Bit Period
A~I
u
Figure 5. Bit Period Energy Effects.
8-110
l
l
200
----------- -----------
Green CS4303 AES paper
~
00+
00-
~
(00+) - (00-)
~
(
Figure 6. CS4303 Differential Output
256 x Fs
Clock
A!I:U~
Optical
Fiber
Socket
Opto
Couplers
Clock
Jitter
Right
Line
Out
R+
RCS8412
CS4303
Left
Line
Out
L+
L-
1 1
ov
+5V
1 ov1 !
-12V
+12V
Figure 7. CS4303 Evaluation Board Block Diagram
8-111
-
----------- -----------
Green CS4303 AES paper
+5V
Clock
Input
74HC86
De-jittered
Clock
Figure 8. Clock Jitter AttenuatorlPLL Schematic
o~~------------------------------------.
/,- 8 kHz Fundamental 120 kHz Bandwidth
-20
- - - ,- - - -, - - - -, - - - ; - - - : Dynamic Range = 52.87 dB
-40
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
I
,
I
I
I
,
I
,
,
,
,
,
-60
iii'
'C
.......
~
:::J
~
-80
-100
-120
CI
~ -140
-160
-
-,
-180
,
-
-
-,
-
-
-
;-
-
-
-
1-
-
-
-,-
-
-
-,
,
I
,
I
I
I
I
,
,
I
-
-
- - - - - - - - - - - - - - - - - - - -
-
..
-,
,
-
-
-
,-
,
-
- - - - I
-
-
-
-
-200+---T-~T---r-~r-~--~---+---r---r--4
o
28
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Figure 9. Filtered Modulator Output Spectrum
3rd Order -3 dB @ 33.28 kHz (Simulated)
8-112
120
--- -------------------
Green CS4303 AES paper
0.--,------------------------------------,
.;- 8 kHz Fundamental 120 kHz Bandwidth
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8-113
...-..
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_....
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...
Green CS4303 AES paper
680pF
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8-114
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Green CS4303 AES paper
------'----------'-----,
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8-115
----------------------
Green CS4303 AES paper
..
CRYSTAL noiseunm
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8-116
I
1Ok
30k
--- -------------------
Green CS4303 AES paper
CRYSTAL THDAMP1
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8-117
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Green CS4303 AESpaper
CRYSTALdalin16
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----------- -----------
Green CS4303 AES paper
CRYSTALmonoton
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8-119
_-_...-..
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Green CS4303 AES paper
AMP1 (dBr) vs FREQ(Hz)
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8·120
10k
20k
----------- -----------
Harris AID & 01A AES paper
How to Achieve Optimum Performauce from Delta-Sigma AID & D/A Converters
Steven Harris
Crystal Semiconductor Corporation
POBox 17847
Austin, Texas 78760, USA
Modem delta-sigma NO & DIA converters are capable of very high levels of performance.
Realizing the full potential from this class of converters requires attention to many details. This
paper discusses these details which include clock jitter and interference effects, ground plane
techniques, minimizing power supply coupling and reducing tone effects. The paper concludes with
a checklist of rules, which, if followed, will ensure optimal converter operation.
1.0 Delta-Sigma Converters - Fundamentals
Delta-sigma analog-to-digital and digital-to-analog converters (ADCs and DACs) offer the digital
audio equipment designer many benefits, including freedom from complex analog anti-aliasing and
reconstruction filters, perfect differential non linearity, high integration and low cost. A study of the
theory of operation of such converters reveals some particular sensitivities, which, if not taken into
account during equipment design, can lead to degraded performance. In order to understand these
degrading mechanisms, several fundamental concepts need to be reviewed. These are oversampling,
noise shaping, aliasing and the multiplicative nature of the voltage reference input of a converter.
1.1 Oversampling
To digitize and subsequently reconstruct a signal, it must be sampled with a sampling frequency
(Fs) of at least twice the maximum signal frequency (Fb). Sampling at exactly 2Fb is known as
Nyquist rate sampling. Oversampling is when Fs is greater than 2Fb.
When a large signal is digitized, the signal to quantization noise ratio is approximately 6 times .the
number of bits in the digitizer. The quantization noise is white and is equally spread between dc and
Fsl2. Delta-sigma converters internally quantize the signal with a resolution of I-bit, yielding a
signal to noise ratio of approximately 6dB. Using an Fb of 24kHz, and a 64X oversampling ratio,
the input sample rate is very high at 3.072MHz; therefore, the quantization noise is spread out
between dc and 1.536MHz. Subsequent digital filtering removes the noise between 24kHz and
This paper was presented at the 93rd AES Convention, San Francisco, October 1992, Preprint #3417
and also appeared in the October 1993 issue ofthe JAES, Volume 41, Number 10.
8-121
III
----------- -----------
Harris AID & D/A AES paper
1.536MHz. This greatly improves the signal to noise ratio in the frequency band of interest, dc to
24kHz. However, even 64 times oversampling is insufficient to yield an acceptable signal to noise
ratio, so noise shaping is used to further lower the noise.
1.2 Noise Shaping
The quantizer in a delta sigma converter has a noise floor which is shaped such that most of the
quantization noise is out of the frequency band of interest (dc to 24 kHz), yielding very low noise in
the audio band. Such quantizers are known as delta-sigma modulators, and may be realized in
analog form for an ADC, and in digital form for a DAC. WeIland [1] and Sooch [2] papers contain
excellent analyses of delta-sigma conversion for both ADCs and DACs.
1.3 Aliasing
Aliasing occurs when a high frequency signal is translated to a lower frequency by sampling the
signal at a frequency less than 2Fb. For example, if a 47kHz signal is presented to a Nyquist rate
converter sampling at 48kHz, then a 1kHz digital signal will be the result. With delta-sigma
converters, the input sample rate is very high. With an input sample rate of 3.072MHz, aliasing
occurs at frequencies greater than 1.536 MHz. For example, a 3.062MHz input into the converter
will appear at 10kHz in the output spectrum. Thus, delta-sigma converters require particular
attention to interfering frequencies in the MHz range, of which there are many in today's digital
equipment.
1.4 Voltage Reference Input to an ADCIDAC
=
The transfer function of a 16-bit ADC is N 32767xVinlVref, where Vin is the input voltage, N is
the output word and Vref is the dc voltage reference. For a 16-bit DAC, the transfer function is
Vout NxVref/32767, where Nis the input word, Vout is the output voltage and Vref is the dc
voltage reference. Notice in both cases, the voltage reference, Vref, has a multiplicative relationship
with the output. In theory, the voltage reference is only a dc voltage, with no AC component. In
reality, the voltage reference will have some noise, and it may also have some discrete frequencies
present caused by interference. These AC components are multiplied by the input signal, yielding
sum and difference frequency components in the output, since signal multiplication causes
amplitude modulation.
=
In the case of a delta sigma converter, there is significant energy in the shaped quantization noise at
high frequencies, which when amplitude modulated by high frequency interference on the
reference, results in an elevation of the noise floor of the converter in the audio band (Figure 1).
Thus a single interfering high frequency, if inadequately decoupled from the voltage reference, has
the somewhat surprising result of an elevated noise floor in the audio band.
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2.0 Converter Artifacts
This paper studies 2 kinds of converter artifacts: noise and discrete frequencies. Noise effects
elevate the noise floor of the converter from its expected level. Discrete frequencies are particularly
troublesome, since the ear is remarkably good at detecting single frequencies out of the noise floor
[3].
The common measurement tool for measuring these artifacts is the spectrum analyzer, often using a
Fast Fourier Transform (FFT) technique. An FFT performed on the output of a converter allows the
noise floor to be measured and tones to be revealed. High resolution FFTs, for example 16K points,
are required to yield sufficiently low noise content of each frequency bin to allow barely audible
tones to be measured. The Audio Precision System One is an example of measuring equipment
using this technique [Reference 4].
3.0 Clock Jitter Effects
Wide dynamic range audio converters are sensitive to clock jitter. Harris [Reference 5] explored the
effects of clock jitter. In summary, if the clock edges running the converter vary in time about their
nominal position in a random fashion, then the noise floor of the converter will elevate. If the clock
jitter is periodic in nature, then PM modulation occurs, and sideband tones will appear equally
spaced either side of the signal frequency. Clock jitter greater than 50 ps rms can be unacceptable in
some high quality audio converters. The best way to avoid these effects is to use a crystal oscillator
to generate the sampling clock. Typical jitter from such an oscillator is under lOps rms. The
oscillator should have a clean power supply, and should be positioned close to the ADC and/or
DAC. The rest of the audio system should then be locked to this oscillator. This architecture will
make sure that clock jitter at the converter is minimized.
An example of this is the separation of a CD transport from the DAC function. Several
manufacturers use a crystal oscillator in the DAC box which runs the DAC. An AESIEBU signal
derived from this clock is then transmitted to the transport unit. The transport electronics are
operated from the recovered 256xFs clock from an AESIEBU receiver chip. The CD transport
audio data is transmitted back to the DAC box, using the same clock, for conversion to audio. New
AESIEBU devices [Reference 6] allow whole networks to be run synchronously, with the timing
master being resident in the converter unit, thus minimizing clock jitter effects on the converter.
4.0 Power Supply Rejection of Delta Sigma Converters
One mechanism by which high frequencies can interfere with the operation of a delta-sigma
converter is via the power supply. Figure 2b shows what happens when a high frequency near to the
input sample rate is deliberately injected into the supply. The injected high frequency is not a pure
sine wave; harmonics are present. Therefore the shape of the resulting interference is not a tone, but
a collection of tones. Notice how the higher harmonic interference has the same shape as the lower
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frequency, but is more spread out. This is because the harmonics of the interference are
proportionally further removed in frequency away from multiples of the input sample rate. This
yields a characteristic cluster of tones. System clocks are square waves, often yielding clusters of
tones which contain odd harmonics.
If the interfering frequency is changed and the ability of the converter to reject the frequency is
measured, then Figure 3 is the result. Notice the approximately 50dB of power supply rejection in
the audio band, then the very steep improvement coincident with the transition band of the output
filter of the converter. Between 24 kHz and 3.072MHz - 24kHz, the power supply rejection is very
good, in fact it is difficult to measure reliably because of the effectiveness of the digital filter. At
exactly 3.072MHz - 24kHz, the power supply rejection becomes much worse, in fact only around
20dB. The window of poor rejection lasts until 3.072MHz + 24kHz. Similar 48kHz wide windows
of poor rejection occur around multiples of the input sample rate. If the sample rate of the converter
is changed, then the power supply rejection against frequency plot scales with the change in
frequency. Thus in systems which switch between 32kHz, 44. 1kHz and 48kHz operation, there are
a number of sensitive frequency regions.
There are many board level coupling mechanisms that will be discussed later, but careful attention
to the choice of system clock frequencies can result in more robust system performance by avoiding
the sensitive frequency regions.
5.0 Synchronous Clock Effects
An effect peculiar to delta-sigma converters becomes apparent after close study of the output
spectrum of a delta-sigma modulator. Figure 4 shows the output spectrum of a delta-sigma
modulator with an input voltage which yields exactly 50% ones density output. Notice the shaped
quantization noise, with a tone at exactly half the input sample rate (IFsl2). This is present because
of the high number of occurrences of 010101 sequences, which have a fundamental frequency of
IFsl2.
In a real system, the modulator input circuitry and any external circuitry will have voltage offsets.
In a digital modulator, the digital data may not be centered on the mid-scale code. Figure 5 shows
the output spectrum in the presence of a small dc offset. Notice a frequency component at a small
displacement frequency (Fd). This frequency is caused by occasional occurrences of 00 and 11
amongst the occurrences of 010101. The frequency with which the pairs of zeros or pairs of ones
occur is Fd, and is proportional to the dc offset. This tone, slightly displaced from IFsl2 is, in itself,
not a problem, since it will be filtered out along with the quantization noise.
However, if a signal of exactly IFsl2 is coupled onto the voltage reference, then, because of the
multiplicative nature of the voltage reference, sum and difference frequencies occur. The difference
between IFs and IFs/2 - Fd is Fd, which could lie in the audio band. The IFsl2 frequency may well
be present ina system, since IFsl2 is an integer divide ratio from the master sampling clock. Thus,
the combination of dc offset, and IFsl2 coupling onto the reference, yields an audible tone. Figure 6
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shows such a tone, with SOmV input dc offset and 2mV of IFs/2 deliberately injected onto the
voltage reference. The resulting tone is clearly evident.
The behavior of such tones with varying dc offset can be seen in Figure 7. Notice the linear
behavior. The serial bit clock for a 2-channel16-bit converter naturally calculates out to be IFs/2 for
some converters (16 right bits + 16 left bits =32 bits per word period =IFs/2 for a 64 X
oversampled converter). A robust system design will avoid the use of clocks with a frequency of
IFs/2, typically using IFs for the serial bit clock instead.
6.0 Coupling Mechanisms
In a real system, various mechanisms exist which can couple interfering energy into the ADC or
DAC. These coupling mechanisms can be classified into direct, capacitive, magnetic and radio
frequency. A short study of the characteristics of each mechanism will allow us to design systems
which minimize unwanted coupling.
6.1 Direct Coupling
The most common form of direct coupling is the mixing of ground return currents through a
common ground connection. It is particularly damaging if digital currents find their way into analog
signal paths.
The usual way of preventing direct coupling is to use entirely separate connections for digital
ground and analog ground. The two grounds are then connected together at one place. Common
choices for the connection point are next to the power connector on the printed circuit board, at the
power supply and at the converter. Experienced designers allow for all three possibilities, the best
place being determined by performance measurements.
6.2 Capacitive Coupling
Stray capacitance between circuit elements and connections will couple unwanted signals into
sensitive nodes. Figure 8 shows a model of this mechanism, along with a frequency response plot.
From this model we can deduce several guidelines to reduce this effect. Firstly, minimize the size of
the stray capacitance by reducing the area of the plates. This normally involves minimizing the
length of sensitive PCB traces. Also the spacing between the plates of the stray capacitor must be as
large as possible, leading to physical separation between digital and analog circuits. A floating
metal region between circuit elements can greatly increase coupling, and should be avoided. From
the frequency response plot, it follows that low frequency noise sources cause less interference than
high frequency. Therefore slowing down fast digital signal edges can often result in reduced
interference. Lowering the impedance of the sensitive traces to ground reduces the magnitude of the
coupled voltage.
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6.3 Magnetic Coupling
Magnetic coupling is a current related effect, as shown in Figure 9. The induced noise voltage is
dependent on the rate of change of the current, the mutual inductance and the orientation of the
transmitter with respect to the receiver. The mutual inductance is dependent on the spacing between
the transmitter and the receiving loop, and on the loop area. Therefore to minimize the coupling,
physical separation should be large, current rise times should be slow, loop area should be small
and the relative orientation should be perpendicular. Figure 10 shows the small loop area that
occurs when a ground plane is used for the return connection.
6.4 Radio Frequency Interference and Electric Field Effects
Digital audio equipment often has to operate in an environment where there is much RF energy, for
example in a broadcast studio or in satellite TV stations. The goal of the equipment designer is to
reduce the susceptibility to RF pickUp. This is accomplished largely by using the correct power
supply, input and reference decoupling components, and by minimizing the decoupling capacitors'
total loop area. The use of both surface mount packages for the converter les and surface mount
decoupling components is highly recommended. Also, there should be no large areas of copper
plane either floating or attached to the reference or input of the converter. An additional low
impedance path at high frequency between the analog and digital ground pins of the converter can
often reduce the effects of RF fields. This may be achieved by a wire link or a small value
capacitor.
7.0 Ground Planes
Ground planes in the digital region minimize ground return current loop area, since the return
current will follow under the associated trace at high frequencies (Reference [5]). Figure 11 shows
how the radiated magnetic field is reduced. The return current magnetic field cancels the primary
current magnetic field for distances much greater than the board thickness.
Ground plane fill in the analog region acts as a magnetic field shield by causing the field to be
absorbed, since the ground plane fill acts as a shorted turn (Figure 12). The secondary current
induced in the ground fill generates a magnetic field. This field induces a voltage in the conductor
of interest that tends to cancel the voltage induced by the primary current.
Measuring the coupling between adjacent traces with and without ground plane fill revealed that up
to 30dB reduction of coupling is possible. Thus using ground plane fill is a very effective technique
for reducing digital to analog interference. Remember to fill in the digital regions to reduce the
transmission of noise, in addition to filling in the analog regions to reduce the reception of noise.
These two effects add in dB, and are therefore very effective when used together.
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8.0 Distortion Mechanisms
Modem delta-sigma converters achieve distortion figures of better than 0.001 %. It is quite easy to
degrade the converter performance by using non-optimal external circuits. The most common cause
of excessive large signal distortion is the use of incorrect filter capacitors. Any capacitor which is
between the signal path and ground should be a low voltage coefficient type, for example NPO or
COG. Normal ceramic decoupling types, for example X7R, are not suitable, and will result in
severe harmonic distortion at full scale.
Another potential effect is illustrated in Figure 13. Here the use of a non inverting amplifier
configuration has caused excess distortion. The distortion is caused by common mode stress of the
input stage as the input voltage varies. The use of an inverting configuration removes this effect,
since both input terminals of the op-amp stay at zero volts.
9.0 A Checklist of Layout and Design Rules
Extensive experience of system designs has led to a list of fecommended design techniques. If these
are studied and followed, then optimum ADC and DAC performance is assured.
a) Partition the board with all the analog components grouped together in one area and all the
digital components in the other. Do not surround the digital area with the analog area or vice versa.
Position components to minimize the return current path and loop area. Do not allow high current
returns to mix with sensitive signal paths.
b) Have separate analog and digital ground planes on the same layer, with the digital components
over the digital plane, and analog components, including the analog power regulators, over the
analog plane. The split between the planes should be 118 inch.
c) Mixed signal components, including the data converters, should bridge the partition in the ground
plane with only analog pins in the analog area, and only digital pins in the digital area. Rotating the
converter package can often make this much easier.
d) Analog and digital grounds should only be connected at one point. The best alternative points are
at the power supply, where the supplies enter the board and at the converter. Provide facilities for
alternative connection points.
e) Analog power and signal traces should be over the analog ground plane. Digital power and signal
traces should be over the digital ground plane. No traces should cross the gap between the two
planes.
f) Keep digital signal traces away from the analog supply, voltage reference and analog pins of the
converter.
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g) Bypassing capacitors should be close to the converter IC pins, and positioned for the shortest
possible signal connections. For example, the voltage reference decoupling capacitor should be
surface mount, and there should be only a very short trace from the reference pin to the capacitor.
The OV end of the capacitor should be directly attached to the analog ground plane.
h) If both large and small decoupling capacitors are recommended, then the small one should be
nearest to the IC. For multi-layer boards, make the connections to the IC and the capacitor on the
same layer.
i) For boards with more than 2 layers, do not overlap analog and digital ground planes. Do not have
a plane which crosses the split between the analog and digital ground planes.
j) Avoid multiple crystal oscillators or asynchronous clocks. When using converters with DSPs or
microcontrollers, operate everything from one oscillator using dividers.
k) In systems requiring multiple crystals for selecting alternative sampling rates, enable only one
oscillator at a time. Shut off unused oscillators by removing power.
1) When using switching power supplies, DC to DC converters or chopper stabilized amplifiers,
lock the switching frequency to the ADC and/or DAC sampling frequency.
m) Do not connect the sampling clock to the converter via a PAL, analog multiplexer, opto-coupler,
gate array or other circuits which can cause clock jitter.
n) Locate the crystal oscillator for the sampling clock close to the converter. A void overshoot and
undershoot on the sampling clock, which can inject transients into the converter.
0) Do not drive signals off the circuit board directly from converter digital signals. Excessive
current transients can occur when driving capacitative cables. Always use a buffer, which will
prevent the current transients interfering with the converter.
p) When converters are used in a particularly hostile environment, for example inside a personal
computer, then a metal screen on both sides of the board will reduce radiated interference effects.
The screen should enclose the entire converter and associated analog components.
q) Make sure that any potentially interfering clocks are not in the sensitive frequency regions
exhibited by delta-sigma converters.
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r) Make sure that the digital supply decoupling for the converter is such that the loop area is
minimized. A small ferrite bead close to the converter, and before the decoupling capacitor, will
prevent the digital current loop area extending beyond the immediate vicinity of the converter,
Reference [6].
s) Do not have clocks in the equipment at 112 the input sample rate of the converter. If an IFsJ2
frequency clock couples into the voltage reference, then tones can occur. Odd order sub-multiples
of IFs12 are also potentially dangerous, since clocks will have odd harmonics. For example, IFs/6
clocks will have a strong component at IFs12.
t) Empty regions between printed circuit board traces should be filled with copper. The filled
regions should be electrically attached to the appropriate ground plane (digital in the digital region,
analog in the analog region). This technique reduces the electromagnetic radiation from the digital
section, and reduces the sensitivity of the analog traces to radiated effects.
10.0 Debugging Checks
Three simple tests can help to identify the source of excess noise in an ADCIDAC system.
1) If the noise floor is modulated by dc input amplitude, then the excess noise originates in the
voltage reference.
2) If the noise floor is modulated by the input frequency, then there is excessive clock jitter.
3) If the noise floor is not modulated by amplitude or frequency, then the excess noise is present in
the input signal. Noise at high frequencies can be aliased into the audio band.
11.0 Conclusions
A number of sensitivities of delta-sigma converters have been explored. Various coupling
mechanisms which could excite those sensitivities have been listed. Finally, a list of guidelines is
enumerated, which, if followed, will help ensure the best possible performance from delta-sigma
converters.
12.0 Acknowledgments
My sincere thanks go to Jeff Scott, Ron Knapp, Eric Swanson and Harold Bogard for their
contributions to this paper.
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13.0 References
[1] D. R. WeIland, B. P. Del Signore, E. J. Swanson, T. Tanaka, K. Hamashita, S. Hara, and K.
Takasuka, "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio", JABS, Vol 37, No.6,
June 1989.
[2] N. S. Sooch, J. W. Scott, T. Tanaka, T. Sugimoto, C. Kubomura, " 18-Bit Stereo D/A Converter
with Integrated Digital and Analog Filters", 91st ABS Convention, October 1991, New York,
Pre-print #3113(y-l)
[3] L. D. Fielder, "Human Auditory Capabilities and Their Consequences in Digital Audio
Converter Design", ABS 7th International Conference, May 1989, Paper # 4.A
[4] R. C. Cabot, "Testing Digital Audio Devices in the Digital Domain", AES 86th Convention,
Hamburg, March 1989, Preprint 2800 (V-I).
[5] S. Harris, " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital
Converters, and on Oversampling Delta Sigma ADC's", JABS, July 1990.
[6] DJ. Knapp, H. Hetzel, "Audio Local Area Network Chip for Cars", AES 92nd Convention,
Vienna, March 1992.
[7] P. Brokaw, J. Barrow, " Grounding for low and High Frequency Circuits", Analog Dialogue
23-3, 1989.
[8] T. A. Jerse, Signal Analysis Division, "Circuit Decoupling for EMI Control" , Electronics
Engineer, May 1992.
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-v
Converter
- AV
Output
Demodulated
o
641s
Freq
/
Noise
2
Oversampled
Digital
I
Signal
1 kHz
Out-ol-Band
Freq
Noise
1 kHz
Freq
Figure 1. How High Frequency Interference on Vref can Elevate
the Noise Floor
0
0
-10
-20
-30
Il- -40
al
:g. -50
-11
•
CS5336: DC AIN
2mv fs/2 Coupled onto Vref
g10
(I)
9
5-8
~7
U.6
(1)5
54
1-3
2
1
o
-100 -75
-50
-25
0
25
DC Input (mv)
50
75 100
Figure 7. How a IFsl2 Induced Tone Behaves with Varying dc Offset
Applied to the Input
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Harris AID & D/AAES papel'
Conductor
Potential
Noise
Source VN
r~R
-
T
Model
C
Conductor
/
Cc VN
C+Cc
-/1I
I
I
__
1_
R(C+Cc )
Freq
co
Frequency Response
Figure 8. Capacitive Coupling Mechanism
M
=Mutual Inductance
=f (d, A)
d = distance
A
= receptor loop area
Figure 9. Inductive Coupling Mechanism
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Board
L
Analog Ground
Plane
High Frequency Loop Area Cross Section
Figure 10. How A Ground Plane Reduces the Loop Area
Signal
Current
01
./
./
./
./
Board
~bigital Ground
Plane
Radiated
Magnetic
Fields
Figure 11. How a Ground Plane Reduces Magnetic Radiation
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""----GrOUnd Plane
Figure 12. How Grouud Plane Fill Acts as a Magnetic
Shield
OdB
S/(N+D): 72.13 dB
: : : ::
OdB
: _ _ ::
S/(N+D): 90.29 dB
::::-:::J:::: ..~
-130dB
-130dB
24kHz
7
de
de
24kHz
7
2k
7 k H Z. >
F & r ADC
20Vpp
OP27
2k
2kVlr-_&_
7kHz >-'vv
20Vpp
2k
Figure 13. A Non-Inverting Op-Amp Can Cause Distortion
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Harris CS4225 AES paper
A Single-Chip Stereo 16-bit AID Converter and Quad 16-bit
D/A Converter for Automotive and Consumer Applications
Steven Harris, Jeff Scott, Andy Krone, Shao-Chyi Lin
Crystal Semiconductor Corporation
POBox 17847
Austin, Texas 78760, USA
A single CMOS chip has been realized which includes two 16-bit AID converters and four 16-bit
D/A converters. Also included is an adjustable input gain section, as well as an adjustable output
level section. An on-chip PLL allows the device to be clocked by an audio sample rate clock (for
example 44.1 kHz). Topics discussed include design trade-offs in filter performance to achieve low
cost, and novel techniques used to achieve a low-jitter integrated PLL.
1.0 Device Overview
Delta-sigma analog-to-digital and digital-to-analog converters (ADC's and DAC's) offer the digital
audio equipment designer many benefits, including freedom from complex analog anti-aliasing and
reconstruction filters, perfect differential non linearity, high integration and low cost. WeIland [1]
and Sooch [2] papers contain excellent analyses of delta-sigma conversion for both ADC's and
DAC's. This paper discusses a combined ADC and DAC device which brings a much greater level
of integration to the system designer. This single chip CMOS device contains 2 delta-sigma, 16-bit,
ADC's, 4 delta-sigma, 16-bit, DAC's, adjustable input gain stage, adjustable output level stage, a
crystal oscillator, a Phase Lock Loop (PLL) and an auxiliary 12-bit ADC. The device has 3 pairs of
analog inputs, 1 auxiliary digital input, 4 analog outputs, an audio DSP port and a low speed control
port (Figure 1). The device operates from a +5 V power supply.
The intended application for this device is automotive sound systems where each DAC drives one
speaker, located in each comer of the automobile interior. Additional applications include low cost
surround systems and home theater systems.
This paper was presented at the 94th AES Convention, Berlin, March 1993, Preprint #3588
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2.0 Input Level Adjustment
A programmable gain block is provided prior to the ADCs. The range of adjustment is OdB to +46.5
dB in 1.5 dB steps. The gain is adjusted in 2 stages. Firstly, a standard op-amp based stage
implements coarse gain steps of 6dB. Secondly, fine gain steps of 1.5dB are implemented by small
changes in the value of the input sampling capacitor to the delta-sigma modulator.
Changing the gain of the input circuit at a random time can cause a step function in the output
signal. The magnitude of the step function will depend on the instantaneous value of the signal at
the time the gain is changed. A series of such gain changes can result in an objectionable audible
sound, commonly known as "zipper noise". To overcome this effect, changes in gain are only
allowed to occur on zero crossings of the analog signal. This is achieved using a comparator, which
monitors the analog signal and compares it to "zero". (Since this device runs from a power supply
voltage of +5V, signal zero is actually -2.5V). If the signal is very small, or has a small DC offset,
it is possible that no zero crossings occur. If no zero crossings occur, then the level change is
implemented after a time out period of 511 samples (l1.6ms at an audio sample rate (Fs)=44.1kHz).
3.0 ADC Architecture
The ADC's use 4th order, switched-capacitor delta-sigma modulators. Capacitor sizes are chosen to
yield a dynamic range of 85 dB, while requiring minimum silicon die area. High frequency
anti-alias filtering is achieved by including a series resistor on the silicon immediately prior to each
modulator sampling capacitor. The modulator side of this resistor is brought out to a pin, where the
addition of an external O.OluF NPO or COG capacitor completes a single pole RC filter. This
architecture avoids the need to have an RC filter on each one of the 6 analog input pins, thereby
reducing the external component count and complexity.
The modulator is followed by a single stage 1024 tap FIR filter, similar in architecture to [3]. This
filter has a passband of DC to 0.454 Fs (-3dB), passband ripple of <±G.1dB, and stopband rejection
of>75d B. Figures 2, 3 and 4 show the filter response. The filter also includes a "near to dipping"
indicator. Bits in the status register are set if the signal is >-6dB, >-3dB and;WdB (clipping) with
respect to full scale. This gives the system designer a low overhead method of detecting an almost
clipping situation.
The ADC offset is calibrated by internally zeroing the input signal and noting the output of the
digital filter. This output is then subtracted from all future readings to compensate for the modulator
offset. This calibration is done after the end of the reset period.
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Harris CS4225 AES paper
4.0 DAC Architecture
Each of the four DACs consists of a digital interpolation filter, a digital delta sigma modulator and a
one-bit DAC feeding a switched capacitor output smoothing filter.
The digital interpolation filter uses the silicon efficient multiplier free architecture previously
described by Scott [4], where the Finite Impulse Response (FIR) coefficients are reduced to -1,0,+ 1.
Compact disk de-emphasis can be selected and is implemented by selecting an alternate distribution
of -1,0,+ 1 coefficients for the FIR filter. This avoids the possible truncation and dithering concerns
that have plagued Infinite Impulse Response (UR) digital filter implementations of de-emphasis.
The de-emphasis magnitude and phase requirements are accurately realized over the entire audio
band. The interpolation filter also compensates for imperfections in the phase response of the
analog switched capacitor filter, yielding an overall linear phase response within ±O.5 out to
0.45Fs (Figure 5).
0
The third order digital delta-sigma modulator accepts the interpolated data and outputs a I-bit data
stream at 192Fs or 256Fs. This data stream is then filtered by a 1 pole switched capacitor filter,
whose architecture is inherently tolerant of clock jitter [2]. Figures 6, 7 & 8 show the overall
response of the DAC. The passband is DC to 0.476Fs (-3dB), the passband ripple is ± O.IdB and
the stopband rejection is >57 dB, with an externa12Fs time constant RC filter.
The DAC outputs are calibrated to yield a low output offset voltage. The uncalibrated DAC offset is
measured with the previously calibrated ADC. The digital input value required to achieve zero
offset is then stored in an offset calibration register, and is subsequently used to correct all future
conversions.
The DAC output mutes after the occurrence of 512 consecutive zeros, yielding a very quiet
(-lOOdB) background noise in the absence of signal. The DAC also has a "hold on error" function.
If a digital value is presented to the DAC's that is flagged as invalid, then the output of the DAC
will stay held at the previously valid level. This is much better than allowing a potentially damaging
full scale excursion through to the DAC. Another possibility is a linear interpolation of up to 8
consecutive erroneous samples [5], however this requires significant die area to achieve. The
frequency spectrum of a signal with a held region is similar to the spectrum of a signal with a linear
interpolated region, particularly if the region is small, which is the case here. Thus there is little
audible difference between hold and linear interpolation.
5.0 Output Level Adjustment
Each of the DAC outputs is followed by an adjustable output level attenuator whose range is OdB to
-II7dB in I.OdB steps. The attenuator is implemented in 2 stages. The first stage is a coarse digital
attenuator prior to the DAC. The step size of the coarse attenuator is 6dB, which is implemented
simply by shifting the data by one bit location. The fine attenuator (IdB steps) is implemented in
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Harris CS4225 AES paper
the analog switched capacitor output filter by scaling the capacitor values. The first 32dB of
attenuation is implemented entirely by the analog attenuator. This causes the background noise to
be attenuated along with the signal, thus the attenuator behaves and sounds like a resistive potential
divider type of volume control. Once the analog attenuator has reached -32dB, then the residual
noise is so low that subsequent changes made in the digital domain do not cause audible changes in
the noise floor.
The output attenuator also implements zero crossing switching, thereby minimizing "zipper noise"
in a similar fashion to the input gain stage.
6.0 Clocking Requirements and Phase Locked Loop Architecture
Oversampled converters require high frequency clocks to operate the digital filters and the switched
capacitor circuits. As well as the usual pins to attach an external high frequency clock or crystal, an
on-chip Phase Locked Loop (PLL) has been provided. This allows the device to lock onto an
external audio sample rate clock source, such as a CD transport, and generate the necessary high
frequency clocks internally. The latest DSP for audio from Motorola, the 56004, also has an on-chip
PLL, thus allowing a system where no external high frequency clocks are present on the circuit
board. This reduces radio frequency emissions.
Low clock jitter is important to preserve signal fidelity in ADC's [6]. However PLL's can add jitter,
particularly with high multiply ratios. The DAC's require a 256Fs clock, resulting in a X256
multiply ratio from the sample rate clock (Fs) in the PLL. The resulting jitter is primarily the
product of VCO phase noise not being filtered by the PLL. How much jitter is acceptable?
Considering only gaussian noise jitter, then the signal to noise ratio (SNR) caused by jitter alone is:
SNR dB
=20 10glO (1I(21tfcr»
[7]
where f = the frequency of the signal (Hz) and cr = the rms jitter amplitude (seconds). The SNR
specification for this device is 85 dB. If we assume a worst case audio signal of OdB (full scale for
the converters) at 20kHz, then cr::; 447ps to achieve 85 dB SNR. This is a very aggressive target for
a X256 PLL, however a 20kHz full scale signal very rarely occurs in actual music signals.
To allow maximum flexibility, the device can be clocked in 3 ways: a) Using a high frequency
external crystal oscillator, or using the on-chip high frequency crystal oscillator. This results in
negligible clock jitter impact on SNR. b) Using the serial bit clock from a remote audio source. This
clock will be at 32 or 64X Fs. The chip's internal PLL will only have to multiply this by 4 or 8, thus
introducing minimal extra jitter. c) Using an external word clock at Fs. The internal PLL has to
mUltiply this by 256, thus there is the possibility of introducing jitter which will cause measurable
degradation in SNR (with full scale, 20kHz signals). Whether this results in any audible artifacts
with music signals is beyond the scope of this paper.
8-140
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Harris CS4225 AES paper
Figure 9 shows the overall clock generation function on the chip. Inputs are a high frequency clock
at 256,384 or 512 Fs, or a serial bit clock at 32 Fs or 64 Fs, or a low frequency clock at Fs. Outputs
are a high frequency (256 Fs or 192 Fs) analog quality clock for the DAC's, a medium frequency
(64 Fs) analog quality clock for the ADC's, a high frequency (512 Fs) digital quality clock for the
DAC interpolation filters and a selection of clocks connected to the CLKOUT pin for driving
external devices. To generate the 512 Fs digital clock, a simple delay locked loop (DLL) multiplies
the 64 Fs analog clock up to 512 Fs.
The PLL consists of a phase detector, charge pump, loop filter, Voltage Controlled Oscillator
(VCO) and divider (Figure 10). The charge pump has a deliberate constant current sink (iJeak),
which forces the phase detector to always operate in a linear region. Careful choice of iJeak removes
the "dead zone" problem of the phase detector, while keeping the introduced deterministic phase
jitter below that of the random phase jitter introduced by the VCO. The loop filter consists of a
4kohm internal resistor with a 0.2 uF external capacitor to ground. There is an additional 20 pF
capacitor close to the input of the VCO. Reference [8] discusses the trade-offs in choosing loop
filter components.
Figure 11 shows the VCO design. To minimize pull range for different clock modes, the ring
oscillator operates with a variable number of delay elements. For 384Fs clock modes, the VCO is
operated at 192Fs and 9 delay elements are used. For 256 & 512 Fs clock modes, the VCO is
operated at 256 Fs and 7 delay elements are used.
Two internal inverters are provided for use as the amplifier in a crystal oscillator clock source. One
inverter is set up for use with high frequency crystals. The other inverter is set up for use with low
frequency crystals ( -44.1 kHz). Inverter selection is achieved using a control bit.
7.0 12-bit ADC
An auxiliary 12-bit ADC is provided to allow the background noise inside the automobile to be
measured. This allows the possibility of simple output level adjustments based on the ambient
noise, as well as more sophisticated noise cancellation algorithms.
The 12-bit converter uses a 2nd order switched capacitor modulator followed by a sinc 3 response
decimation filter [9]. This filter completely decimates to the same audio sample rate (Fs) as the
16-bit converters. The resolution over 0 to Fs/2 bandwidth is limited to 11.5 bits, but the user may
apply subsequent additional filtering to realize higher precision over lower bandwidths. This allows
users to customize an external low-pass digital filter to suit their particular requirements. The output
noise of the on-chip filter is shown in Figure 12.
8-141
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Harris CS4225 AES paper
8.0 Audio Data Formats
Figure 13 shows the formats for the DAC input data and for the ADC output data. Format 0 is
compatible with the fs format. Format 1 is compatible with many converters. Format 2 is
compatible with many Compact Disc decoders. Format 3 is compatible with general purpose
DSP's, where the LRCK signal is a positive pulse at the beginning of each 16-bit word.
9.0 Control Port Formats
The internal operating modes of the device can be set in 3 ways: hardware, SPI compatible serial
control port and I 2C compatible serial control port. In hardware mode, only limited functionality is
possible; for example, the input gain cannot be changed, and neither can the output level.
Up to 4 devices can be controlled by the same serial control lines. Each chip has its own unique
address, which is set by connecting the chip address pins to a particular binary pattern. The SPI and
I2C control modes have a chip address field included in the command protocol. The control port is
also compatible with Crystal's Audio Local Area Network (A-LAN) chip, previously described in
[10]
10.0 Applications Schematic and Board Layout
Figure 14 shows the recommended connection diagram for the device. Notice the lack of required
external components. All the analog inputs and outputs are internally biased to -0.5 the power
supply (+5V), therefore DC blocking capacitors are required if the analog signals are referenced
aroundOV.
The grounding and layout arrangements around this device must be correct in order to achieve the
best performance. Figure 15 shows an overall board layout, with the chip package (44 pin PLCC)
mounted over the analog ground plane. Notice that the package is oriented with the digital pins
close to the digital section of the board. Figure 16 shows an enlarged view of just the decoupling
capacitor arrangements. Notice that the smaller capacitors are shown close to the device package.
Harris [11] has previously discussed how to get the best performance from delta sigma converters.
Crystal offers a free schematic and layout review service, which is best used before the first
prototype is built.
8-142
.._-_
.-_
._.-.
_
..--__
...
Harris CS4225 AES paper
11.0 Specification Summary
Analog Inputs & ADC
DAC & Analog Outputs
ADC resolution
Dynamic Range
THD+N
Frequency Response
Phase response
Input gain
Step size
DAC resolution
16-bits
Total Dynamic Range 100dB
Instantaneous
Dynamic Range
88dB
Frequency Response 0 to 0.476Fs
Phase response
<0.5°
oto 117dB
Output Attenuator
Step size
l.OdB
16 bits
85dB
85dB
o to 0.454Fs
<0.5°
o to 46.5dB
l.5dB
Global Specifications
Sample rate
Power supply voltage
Power supply current
Full scale signal level
4kHz to 50kHz
+5V
120mA
1 Vrms
All dynamic range specifications are A-weighted. Total dynamic range is the ratio between the full
scale output of the chip and the noise floor when maximum attenuation is selected. Instantaneous
dynamic range is the DAC dynamic range with the output attenuator set to OdB.
12.0 Conclusions
A single chip containing two 16-bit ADC's, four 16-bit DAC's, a programmable input gain stage
and a programmable output attenuator stage has been presented. This device will allow the next
generation of automotive sound systems to be realized in a cost-effective manner. Novel techniques
in filter design yield a small die area. The inclusion of a PLL for high frequency clock generation
frees the system designer from having to route high frequency clocks around the system.
8-143
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Harris CS4225 AES paper
13.0 References
[1] D. R. WeIland, B. P. Del Signore, E. J. Swanson, T. Tanaka, K. Hamashita, S. Hara, and K.
Takasuka, "A Stereo 16-bit Delta-Sigma AID Converter for Digital Audio", JAES, Vol 37, No.6,
June 1989.
[2] N. S. Sooch, J. W. Scott, T. Tanaka, T. Sugimoto, C. Kubomura, " 18-Bit Stereo D/A Converter
with Integrated Digital and Analog Filters", 91st AES Convention, October 1991, New York,
Pre-print #3113(y-l)
[3] Max W. Hauser, Paul J. Hurst and Robert W. Brodersen, "MOS ADC-Filter Combination That
Does Not Require Precision Analog Components", 1985 IEEE International Solid-State Circuits
Conference Digest of Technical Papers pp. 80-81, February 1985.
[4] J.W. Scott, "Multiplier-Free Interpolation for Oversampled Digital-to-Analog Conversion",
92nd AES Convention, March 1992, Vienna, Pre-print #3317
[5] SAA7220 digital interpolation filter data sheet, Philips Semiconductors.
[6] S. Harris, " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital
Converters, and on Oversampling Delta Sigma ADC's", JAES, July 1990.
[7] Internal memo at Crystal Semiconductor.
[8] "CS5317 data sheet DS27F2, MARCH 1992", Crystal Semiconductor
[9] J.C.Candy, "Decimation for Sigma Delta Modulation", IEEE Transactions on Communication,
January 1986, pp 72-76.
[10] D.J. Knapp, H. Hetzel, "Audio Local Area Network Chip for Cars", AES 92nd Convention,
Vienna, March 1992.
[11] S. Harris, "How to Achieve Optimum Performance from Delta-:Sigma AID & DIA
Converters" ,AES 93rd Convention, San Francisco,October 1992.
8-144
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Harris CS4225 AES paper
DEM
HIS
RST/PDN
AOUT1
LRCK
AOUT2
SCK
AOUT3
SDIN1
SDIN2
AOUT4
2
SDOUT1
SDOUT2
DIFO/HOLD
ISO/ADO,
IS1/AD1
AIN1L
AIN1R
AIN2L
AIN2R
AINAUX
Auxiliary Digilallnput
OVL
CLKOUT
XTI XTO
FILT
AIN3L
AIN3R
AGND2
CL CR DATAUX LRCKAUX SCKAUX AGND1 DGND
Figure 1. Chip Block Diagram
10,-----------------------------------~
0.2
OT---~--L-~--~~
-10 -
-0.0
-20
-0.1
CD
-30
~
T"""------"""/'~~~----""7',--------r;------______,
0.1
'E.. -0.2
~'"
-40
~ -50
-0.3
g' -0.4
.~ -60
::!'
-0.5
::!' -70
-0.6
-80
-0.7
-90
-100 +---j---r----t---r---t----t-'--'---+-'---I-~-'---_'_I
0.0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
Inpu1 Frequency (Fs)
Figure 2. ADC Filter Response
-0.8 T---r------j----t----j---t---j---r---j-~_r___I
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Inpu1 Frequency (Fs)
Figure 3. ADC Passband Ripple
8-145
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----------------------
Harris CS4225 AES paper
2.5,-----------------------------------,
O·,--=~~---------------------------,
-10
2.0
-20
1.5
-30
m
-40
:!:!.
U)
1.0
~
0.5
-'
,
,
,
,
,
,
,
§, -60
.,
:;-o.o~~-_\,'----~ -0.5
-
~ ~50
::;; -70
-1.0
-80
-1.5
-90
-2.0
-
-
-
,
J
-
-
,
-
-
'-
-
-
- - '-
-2.5 +---t----1---t---t---+---t--t--t----t---i
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
-100 +---r------t---t----j---t--t---j-.JL-r--"-t----1
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (Fs)
Figure 4. ADC Transition Band
Figure 5. DAC Phase
10
0.2,-------------------,
0
0.1
-10
-,-
-,-
-,
- ,-
- - -
- - - -
- - - - - - - - - - - - -
-0.0
-20
m
J
~
to
-30
-0.1
.,
:!:!. -0.2
.,
:!:!. -40
"C -50
·2
"
::;;
"C
.a
:E
-0.3
g> -0.4
C) -60
"
::;;
-50
-60
-70
-80
-90
-100 +--t---t--t---j--t---t--t---t--r------i
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)
Figure 8. DAC Transition Band
8-146
----------- ----------XTL (H.F.)
Harris CS4225 AES paper
------------~
Fs
XTL (L.F.) -'-'FS=-----I
LRCK ------>I
LRCKAUX
Fs
5:1
SCK 32 or 64Fs MUX
SCKAUX 32 or 64Fs
__---------1-92-o-r-2-5-6-F-s-+
~:a:log
Clock
(DAC's)
L.F.
1<+_ _-+___________--'6=-4c..:F-=sc...... Analog
Clock
(ADC's)
512 Fs
Digital
Clock
512 Fs
t=~~~==J_---------------+CLKOUT
Figure 9. Chip Clock Generation Block Diagram
-
Charge
Pump
Fs
Clock
up
-----<
-----<
Phase
Detector
Logic
down
Loop
Filter
qyb
~ib ~il9ak
4k
~
VCO
-
20pF
~O.2UF
-------1
I
I
I
I
I
+256 or
I
+ 192
I
I
I
I_ _ _ _ _ _ _ -.J
Divide
Logic
Figure 10. Phase Lock Loop
8-147
.._-_
_.-_..--_
__
...-..
Harris CS4225 AES paper
d =variable delay element
2:1
MUX
From
Loop
Filter
VIa I
Figure 11. Voltage Controlled Oscillator
0.00
,-.-~~~~~~~~~~~~~~~~~~~,
-15.00
-30.00
-45.00
~
-,- - -
-60.00
,-
-
- -,-
;
-
UJ
§
t::
-75.00
z
~ -90.00
::;:
-105.00
-120.00
-135.00
-150.00
-t-'~-r-~-r~-r~-t~----j~~r-~t-~-t-~-r-~--1
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0040
0045
0.50
FREQUENCY (Fs)
Figure 12. 12-bit ADC Output Spectrum with Full Scale Signal
8-148
----------- ----------LRCK
FORMATO:
FORMAT 1:
SCK
Harris CS4225 AES paper
I
SDIN
_ _.L'CMSBr""S,-, !B :: :,-,[LSB]""S
...
B "--_ _---'-'CMSBr"'-'S=B
LRCK
~
SCK
LRCK
SCK
SDIN
LRCK
FORMAT 3:
SCK
LRCK
SCK
SDOUT
FORMAT 1
LRCK
Left
~-
1
---~
1
LSB
I
1
MSBI
I
IL .-~- IL
1
1
-_I LSB
MSBI
1
: SLf--:•
1
LSB
1
••I
1
1
IL
1
MSBI
I
Right
Left
SLf--:- : : I
-,-,[LSB]",S
...
B"--_ _---'-'[MSBl""'S=B
Right
1
-I LSB
MSBI
~
.~
:~
MSBI
~ -_ - - - -L~ft- -__ - - ~c __ - Right _ -_ -_ -__ ~
~-._IL-._~-
SDIN
FORMATO
Right
~:-_-Jl_-_~-
SDIN
FORMAT 2:
1
Left
1
I
IL- _IL
MSBI
Left
•_-
~----~--
_ _. J.[MSB]-,-"M:=SB::.t- : : _[LSB]c=L=SB::..L_ _ _l':[MSB]C'::S=B
~
Left
SCK~-
1
~
_'-----u-u-
: : :c.:[LSB]:=S=--B"--_ _--L[MSB]:.:.:S=B
I
Il.ILJL; .•. IL· •. IL
•. IL·
Right
SDOUT
LRCK
FORMAT 2
SCK
SDOUT
~
1
Left
su:-::~:
Right
I
•• :.~::.::~:-.::~
c=[LS8]=SB--..t..._ _...J[MSBJL'"M=SB=:: L"W""S
...
B "--_ _---.J[MSBJ.o:M=S=B • _ _
~
FORMAT 3
SDOUT
--=1M=S=B1_-1-----.l : .. [LSB]
IMSBI
Figure 13. Audio Input and Output Data Formats
8-149
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Harris CS4225 AES paper
Ferrite Bead
+5V
Supply
2.0n
'-'-------,
CS4225
40 k
~
0.0022 uF~ 10 F
NPO
v~' u
1.0 uF
40 k
~
0.0022 uF ~
F
NPO
~1.0u
AIN1R
)
~
0.0022 uF
> 1 0 uF
NPO ~-.
~0.47UF
)
<
.
40 k
1.0 uF
CR
CL
0.01 uF
NPO
0.01 uF
~~NPO
SCUCCLKlIFO j4---~
SDAlCDO/CKFOr------->I MicroAD3/CS/IF1
Controller
AD2ICDI/CKF1
~~
r---L__
~
AINAUX
0.01 uF
0 47 F'
NPO ~.
u
DATAUX
Digital
Audio
Source
LRCKAUX
SCKAUX
DIFOIHOLD
Mode
Setting
and
RSTIPDN
HIS
DEM
ISO/ADO
IS1/AD1
Controls
SDIN1
SDIN2
SDOUT1
SDOUT2
LRCK
DSP
SCK
CLKOUT
OVL
FILT XTO
• AC blocking
capacitor is
unnecessary if the
input is already
centered around
CMOUT
Audio
Ott' --<
XTI
-
1c1 1 C2
V
7'
Figure14. External Components
8-150
External
Clock
Input
All unused inputs
should be tied toOV.
All NC pins should
be left floating.
----------- -----------
Harris CS4225 AES paper
~1/8"
Digital
Ground
Plane
Note that the CS4225
is oriented with its
digital pins towards the
digital end of the board.
Ground
Connection
+5V
Ferrite
Bead
CPU & Digital
Logic
Codec
digital
signals
Codec
analog
signals &
Components
Figure 15. Suggested Layout Guideline
,--------"'8:--...,w-
-
Analog
Supply
Digital
Supply
00000000000
L ______________ J
Figure 16. Recommended Decoupling Capacitor Layout
8-151
__..-_-_
.-.-.
-..-_
..-.. ....
Harris
-Notes-
8-152
CS~225
AESpaper
---------------------
Sanchez SCMS AES paper
An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission.
Clifton W. Sanchez,
Applications Engineer
Crystal Semiconductor
Austin, TX
U.S.A.
ABSTRACT
The Serial Copy Management System, referred to as SCMS, provides protection
from prolific unauthorized digital duplication of copyrighted material. This
protection is achieved through the use of channel status bits in the "consumer"
digital audio interface standard. Any piece of equipment, either professional or
consumer, containing a "consumer" digital audio interface will be required to
support the SCMS protocol. This paper explains the SCMS protocol in detail,
and presents several easy methods of implementation.
oINTRODUCTION
With the advent of digital audio and a transmission standard for digital audio [1], [2], the ability to
make perfect copies of an original work deprives the recording artist and record companies of potential
revenue. The Serial Copy Management System, SCMS, was designed to eliminate unauthorized prolific
digital duplication of copyrighted material. The SCMS standard is being added to IEC-958 [1] as
Amendment No.1 [3] and will be required on all consumer interfaces. In the United States, the "Audio
Home Recording Act of 1992" [4] was passed by Congress to protect copyrighted works. The Act
requires all equipment containing a consumer interface to support the SCMS protocol. This includes
- but is not limited to - consumer equipment containing a digital audio interface, professional equipment
containing a consumer digital audio interface, and equipment that translates digital audio from one
standard to another.
While the standards stipulate that professional equipment containing a consumer interface is required
to support the SCMS protocol, professionals owning the copyright and engaging in lawful business
are allowed to circumvent the SCMS system.
1 DIGITAL AUDIO INTERFACE OVERVIEW
The digital audio interface provides a means to transmit digital audio information over a single
transmission line from one transmitter to one receiver. The transmission consists of timing information,
as well as up to 24 bits/channel/sample period, control information, user information, and some error
detection capability. The control information is transmitted as one bit per audio sample, with each
channel of the stereo signal containing independent control data. The control information accumulates
This paper was presented at the 94th AES Convention, Berlin, March 1993, Preprint #3518
8-153
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._.-.
_
..--__.._-_
...
Sanchez SCMS AES paper
in a block structure and contains all the information needed to implement the SCMS protocol. The
digital audio data is biphase encoded which allows the receiver to extract a clock from the data. Special
biphase codes, defined as preambles, delineate the audio samples.
An audio sample is placed in a structure called a sub-frame. The sub-frame, shown in Figure I, consists
of four bits of preamble, four bits of auxiliary data, twenty bits of audio data, and four individual bits
called validity, user, channel status, and parity. A frame consists of two sub-frames and contains
channel A and channel B. When the interface is defined for stereo data, channel A is left and channel B
is right. As shown in Figure I, 192 frames are considered a channel status block with the "Z" preamble
indicating the start of the block. Since channel status data is independent for each channel, 192 bits,
or 24 bytes, make up each channel status block.
The preamble indicates the start of a sub-frame and contains biphase coding violations that render the
preamble unique when compared to the rest of the data. These violations enable the digital audio
receiver to quickly locate and lock onto the data stream. Three unique preamble codes indicate the start
of: a channel A sub-frame, a channel B sub-frame, and a channel status block (which is also the start
of a channel A sub-frame).
The next four bits are auxiliary bits and may be used to extend the audio data to 24 bits. Another use
of the auxiliary bits in the professional mode is a single coordination signal [2]. This audio signal uses
12-bit words and spans three consecutive sub-frames (4 auxiliary bits per sub-frame).
The next portion of the sub-frame is a 20-bit field for audio data that is transmitted LSB first. As
previously mentioned, if the audio data is greater than 20 bits, the auxiliary field may be used to expand
the audio data to 24 bits.
V is the validity bit and indicates whether the audio sample is "suitable for conversion to an analog
signal." For example, since data must be continually transmitted in the digital audio data stream, if a
CD decoder chip has an unrecoverable error, the erroneous data could be sent with the V bit for that
sample set, indicating that the data may be corrupted. The receiver, upon receiving the audio data plus
the V bit, could try patching the data. Some examples of patching the data include: interpolating through
the erroneous data, reusing the last valid sample (which is only 3 dB worse than interpolation), or
muting the DACs.
The parity bit, P, at the end of the sub-frame, is a simplistic error detection mechanism defined for even
parity; therefore, a sub-frame should always contain an even number of one's. Given a single parity
bit, the receiver can only detect when an odd number of bits are in error.
The U bit is defined as the user bit and has no strict definition. This bit gives the interface a user-defined
data channel providing flexibility to adapt to different requirements. This flexibility can be seen in
some of the uses to date: DCC systems send textual data such as titles and captions in this channel [5];
the AES has defined a protocol which passes messages in this channel using a unidirectional HDLC
format [6]; and some systems use the channel as an audio LAN [7] to send messages around a ring of
devices in an automotive or home environment.
8-154
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Sanchez SeMS AES paper
The most important bit for implementing copy protection is the C or channel status bit. The C bit is
strictly defined and contains all the SCMS information in the consumer version of the interface. This
bit is unique for each channel and is accumulated over the I92-frame block. The channel status block
is delineated by a unique preamble that replaces the preamble indicating channel A once every
192 frames. The channel status block is the same length for professional and consumer interfaces but
the bit definitions are different with the exception of the first bit in the block. The first bit indicates
whether the rest of the channel status block is defined according to the consumer or the professional
format.
2 PROFESSIONAL/CONSUMER DIFFERENCES
The standards for professional and consumer interfaces are very similar and are listed under various
organizations and titles as seen in Figure 2. A few digital audio interfaces predate the sub-frame
structure previously mentioned. One of the original formats for digital audio communications was
based on the internal serial audio bus structure of the Sony PCM-Fl digital audio processor [8]. This
interconnect format consisted of three signal pins: a data pin containing two channels, a bit clock, and
a word clock indicating the particular channel - left or right. Another early format was SDIF-2 (Sony
Digital InterFace) which was used on the PCM161011630 transports [8]. The SDIF-2 format also
consisted of three signals: left channel data, right channel data, and a word clock. The SDIF-2 format
comes closer to the current digital audio interface since it contains 32 bits per word (albeit each word
has its own line), and contains control and user bits. This format appears to be where the Copy bit,
labeled "Dubbing-prohibition bit", originated.
The main digital interfaces to come after the SDIF-2 format were the S/PDIF (SonylPhilips Digital
InterFace) and the AESIEBU specifications. The AESIEBU format [2] was designed for professional
use. It became a standard in 1985, and was updated in 1992. The SIPDIF was designed as a consumer
format and was included on many early CD players. Both of these digital interface formats were
standardized in Japan in 1987 by the EIAJ as the CP-340 Digital Audio Interface specification [9]. The
AESIEBU professional format was labeled Type I or Broadcast, and the S/PDIF format was labeled
Type II or Consumer. In 1989, the International Electrotechnical Commission in Europe issued the
same standard under the IEC-958 Digital Audio Interface specification [1] with some clarifications.
Updates to the IEC-958 standard include the SCMS protocol [3]. The IEC-958 standard is currently
the most up-to-date specification for consumer equipment. In October 1992, the United States Congress
passed an Act [4] requiring the SCMS protocol on all equipment containing a consumer interface.
Other professional organizations such as the CCIR [10] and the EBU [11] have released their own
versions of the professional format. Consequently, although digital audio interfaces have many titles,
there are basically two formats: professional and consumer.
2.1 Specifications.
In the professional world, digital audio data may need to travel throughout an entire building. In the
consumer environment equipment is normally localized in one area, so the distance the digital audio
interface needs to traverse is shorter. The professional format is designed to transmit data over a
minimum of 100 meters, whereas the consumer format is specified for only 10 meters. The specifications were also designed to use an existing transmission medium. The professional interface uses
8-155
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_.-_..--_-.._-_...._.-.
Sanchez SCMS AES paper
balanced, shielded twisted-pair, 110 n cable with XLR connectors, i.e. microphone cable. The
consumer interface uses single-ended, 75 n coax cable with RCA connectors, i.e. home audio cable.
Since the professional interface transmits over longer distances, 5 Vpp is typically used, whereas the
consumer environment is more concerned with EMI and shorter transmission distances so 0.5 Vpp is
used. The consumer standard also allows an optical interface [12] where data is transmitted over fiber
optic cable. The most common form of optical connector is the rectangular version listed in [12]. The
coding for the channel status block is also different, with the first bit determining whether the rest of
the block is defined as professional or consumer.
2.2 Professional Channel Status
Professional channel status is indicated by the first bit in the channel status block being one. The rest
of the channel status block differs from the consumer definition. Since professional equipment is
designed for use in studios, and the business of professionals is to create and work with copyrighted
material, no copy protection scheme exists in the professional environment. The channel status block
structure for the professional mode is shown in Figure 3. Since this paper is focused on the SCMS
protocol in the consumer interface, detailed definitions for the professional channel status block are
omitted. A general purpose guideline for both the professional and consumer interfaces can be found
in [13]. The standards containing the professional definition are [1], [2], [9], [10], and [11], with [2]
being the most up to date as of the writing of this paper.
2.3 Consumer Channel Status
Consumer channel status is indicated by the first bit, PRO, in the channel status block being zero. This
defines the rest of the channel status block as shown in Figure 4. The channel status (CS) block for
consumer stereo is usually the same for both left and right channels. When designing a consumer digital
audio interface, the following bits must be implemented.
Bit 1, Audio, specifies whether the data is audio (0) or non-audio (1). Although the consumer interface
was designed to transmit digital audio, C 1 provides an indication that digital data replaces the audio
data. Bit 2 is the copyright assertion bit which indicates whether the material is copy protected (0) or
can be copied freely (1). If Cl is defined as audio data, and C4 and C5 are zero (indicating 2-channel
audio) then C3 indicates the audio data has been emphasized. Bits 6 and 7 indicate the mode which
defines the interpretation of channel status bytes 1 through 3. The only currently defined mode is 0,
C6 = C7 = 00. Channel status bits 8 through 14, defined as the category code, indicate the type of
equipment sending the digital audio transmission. The last bit of interest is channel status bit 15, the
generation or L bit, which indicates whether the data is original or a copy. A full definition of all the
bits in the consumer interface is shown in Figure 5 and can be found in [1], [9], and [13]. The areas of
interest to the SCMS protocol are the Copy bit (C2), the Category Code (C8 - CI4), and the Generation
or L bit (CI5).
Bits not defined or defined as reserved must be transmitted as zero for future compatibility. Bit
combinations that are not explicitly defined must not be used (i.e. undefined category codes).
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3 GENERAL SCMS
The SCMS protocol allows consumers to make copies of a prerecorded, copyrighted work. The original
prerecorded work can always be copied, but SCMS will block home recordings of copyrighted material
from further copying. The copy of the original work is called a first generation copy. A copy made
from the first generation copy is labeled a second generation copy and so on. SCMS allows fIrst
generation copies of copyrighted works but prohibits second generation or higher copies. This system
gives the consumer the ability to make a copy, change the order, or merge audio thereby conforming
the data to the consumer's tastes. It also gives some degree of protection to the copyright owners since
the original work is needed to make a copy and any copies of the work (fIrst generation) will be
protected.
SCMS uses a combination of channel status bits in the consumer interface to determine if the audio or
digital data is copyright protected; and, if copyright protected, then whether the data is an original or
a copy.
3.1 Copy Bit - C2
The first bit of interest is the Copy bit which is channel status bit 2 (C2) and indicates whether copyright
has been asserted over the material. When Copy = 1, the material is not copyrighted and it may be
freely copied. When Copy = 0, copyright is either asserted over the material, or no copyright
information is available and copyright is assumed to be asserted.
3.2 Generation Status Bit - CIS
The next bit used in the SCMS protocol is the "generation status" or "L" bit and is channel status bit 15
(C15 or byte 1, bit 7) which is used only if copyright is asserted (Copy =0). The L bit indicates whether
the data is original or a copy of an original. Original data is defined as data which is published by or
with the authority of the copyright owner, such as commercially released prerecorded compact discs
or digital audio tapes. A copy of an original is considered a fIrst generation copy, such as a home
recording of a commercially available CD. The Copy and the L bits give the basic information needed
to implement the SCMS protocol. The L bit would be simple to use except that the polarity of the L bit
changes depending on the type of equipment sending the data.
33 Category Codes - Bits C8 - C14
A code defining the type of equipment sending the data is contained in channel status bits 8 through 14
(C8-CI4 or byte 1, bits 0-6) and is called "Category Code." The list of defIned category codes is shown
on the right side of Figure 5. Reserved category codes must not be used. This includes both entire
groups (Solid State Memory, l11xxxx, etc.) and combinations not explicitly listed in the specifIcations.
Equipment for which an exact category code does not exist should use the most appropriate, explicitly
defIned code.
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If the category code is Broadcast Reception or Laser-Optical, L = 0 is defined as original or commercial
prerecorded work, and L = 1 is afirst generation or higher copy. Broadcast Reception is category code
001 xxxx (0 lllxxx is also Broadcast Reception but is currently reserved) and Laser-Optical is category
code 100xxxx. All other category codes reverse the L bit definition, with L = 1 defined as an original
or commercial prerecorded work, and L = 0 defined as afirst generation or higher copy. Therefore, in
the SCMS protocol, the category code must be used to interpret the meaning of the L bit.
3.4 Exceptions
Two exceptions to the above protocol exist. The first is that two categories are unable to indicate Copy
and L bit information. The categories are General (0000000) and AID Converters without copy
protection information (011 OOxx). When either of these two categories is received, the received Copy
and L bits should be ignored and the receiving equipment must force the Copy bit to 0 (indicating that
the work is copyright protected) and the L bit to original (with the polarity of the L bit determined by
the category code of the receiving equipment).
The second exception occurs when receiving data from a CD player, category code 1000000. Since
CD players have been around much longer than the SCMS protocol and have already been standardized,
the SCMS protocol has to fit into the standard CD format as defined in IEC 908 [14]. Although the
Copy bit is defined in IEC 908 [14], the L bit is not. Therefore, a different method is needed to indicate
generation status. For this category code (1000000), the Copy bit is used to indicate both copyright
and generation status. If Copy = 1, then the disc is not copyrighted. If Copy = 0 the disc is copyright
protected and is original. If Copy alternates between 0 and 1 at a 4 to 10 Hz rate then the disc is
copyrighted and is afirst generation or higher copy.
4 SCMS IMPLEMENTATIONS
Different types of equipment are required to react differently to the SCMS protocol. This section
describes a few category groups and their response to SCMS. Devices which do not store, decode, or
interpret the data stream are considered totally transparent from input to output and do not need to
implement the SCMS protocol. Examples of this type of equipment are digital amplifiers, digital
frequency equalizers, and digital routers. This does not include pass-through equipment (as defined in
the next section) configured to pass the input to the output without modification since pass-through
equipment decodes the digital audio data stream.
The SCMS protocol specifies that if the copyright status is ambiguous, then the Copy bit should be set
to copyright asserted (0) and the L bit should be set to original. This includes the General (0000000)
and AID Converters without copy protection information (01100xx) categories, except as noted below
for pass-through devices. It is assumed that devices which convert from the professional to the
consumer interface fall into this group. Since a professional interface does not include copyright
information, the Copy bit should be set to copyright asserted (0), and the L bit should be set to original
in lieu of other inputs to the device indicating copyright status. Since this is only ap interpretation of
the specifications, the specifications may later show that conversion between professional and
consumer interfaces is not allowed.
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The General category code (0000000) was used in older equipment that did not fully support the
Consumer interface. Any SCMS device receiving the General category should force the Copy bit to 0
(copyright protected) and the L bit to original. For example, the General category was used in some
Japanese digital audio broadcast receivers that did not include any copyright information. The General
category should not be used in newly designed equipment. The Experimental category should be used
in experimental equipment that is not commercially available.
4.1 Pass-Through Devices
Pass-through devices receive and decode a digital input, then encode and transmit a digital output
without a permanent storage ability. These devices come under the category code of Digital-to-Digital
Converters, 01Oxxxx. For digital-to-digital converters, if ALL digital inputs come from the category
code AID Converters without copyright information (01100xx), then the category code at the digital
audio output may remain at 0 1100xx. This category allows an extra generation copy since the receiving
device should respond to this category code by setting the Copy bit to copyright asserted and the L bit
to original. If the pass-through device uses its own category code, it must set the Copy bit to copyright
asserted and the L bit to original. Then the receiving device will change the L bit to indicate first
generation or higher, and no more copies will be allowed. If the digital input contains any category
code other than OllOOxx, the pass-through device must use its own category code, 01Oxxxx, and
interpret and output the Copy and L bits appropriately, regardless of whether the device is configured
to modify the incoming data or not.
4.1.1 Digital Sound Samplers
Digital Sound Samplers, category code 0100010, sample portions of a digital input and assemble the
digital samples into one or more digital outputs. The standard rules of SCMS for pass-through devices
must be applied if ANY digital input is sampled for more than one second.
4.1.2 Digital Signal Mixers
Digital signal mixers, category code 0100100, mix one or more digital inputs and output one or more
digital outputs. The exception listed above for ND converters with category codes 01100xx applies
only if ALL inputs are from that category. If ANY input has the Copy bit set to copyright asserted,
then the digital output must set the Copy bit to copyright asserted with the exception of category codes
0000000 and 01100xx as previously mentioned. Also, if ANY input has the Copy bit set to copyright
asserted and the L bit set to first generation or higher, then the output must also be set to first generation
or higher. Therefore, a digital audio output must contain the highest level of protection of anyone of
the digital audio inputs used to create that output.
4.2 Digital Audio Recorders
Digital audio recorders, DARs, are defined as devices that can store data for later retrieval. This includes
the Laser-Optical category (IOOxxxx) and Magnetic Media category (llOxxxx) with the exception of
the DAT category code 1100000 which is discussed in Section 4.3. Although Solid State Memory
(OOOlxxx) could be considered a digital audio recorder, this entire category code group is reserved and
cannot be used.
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Digital audio recorders should store channel status information pertinent to the data, such as the
Professional/Consumer, AudiolNon-audio, and Emphasis bits. When the data received from a digital
audio interface is in the consumer format, the DAR must store the Copy and L bits as per the SCMS
standard. This information will be needed by devices receiving the recorded data from the DAR. The
only exception is the CD category of 1000000 which cannot store the L bit and was previously
described in Section 3.4. When recording from an internal AID converter, information regarding the
copyright status of the analog signal is usually unavailable. In this scenario the DAR should interpret
the data as if it were coming from category code 0110000, AID Converters without copyright
information, unless explicit copyright information is available. Therefore, the data is assumed copyright
protected and original.
DARs designed exclusively for receiving the consumer digital audio interface should not store data
received from a professional device. DARs capable of receiving both professional and consumer
interfaces must be able to distinguish between the two. Although not explicitly stated in the standards,
if no copyright information exists when converting a professional interface to a consumer interface,
the data should be assumed copyright protected and original. Part of the conversion should include
other channel status information such as AudiolNon-audio, Emphasis, and Sample frequency.
4.3 Digital Audio Tape Recorders
Consumer digital audio tape recorders, DATRs, containing the SCMS protocol have an explicitly
defined algorithm as defined in [15]. Professionals using consumer DAT players need to understand
how the DATR will respond to an incoming digital audio transmission. This algorithm is illustrated in
Figure 6 and describes the order of questions to be asked, whether the data can be stored on the DAT
recorder, and if the data can be stored, the setting of the Copy and L bits to be stored with the data.
The SCMS protocol for DATRs applies to consumer interfaces (PRO. = 0) containing audio data
(Audio =0). If either of the first two channel status bits are not zero (either professional or Non-audio),
then the DATR should not store the data onto tape. If the category code is undefined, the DATR stores
the data and assumes the data is copyright protected and aftrst generation or higher (i.e. not original).
Since this data is stored as not original, no further copies can be made from this tape. If the category
code is General or AID Converters without copyright information, then the DATR stores the data and
assumes the data is copyright protected and an original. Since this data is stored as original, a copy of
this recording can be made through the digital audio output. If the category code is CD compatible
with IEC-908 (1000000), and the Copy bit is alternating between 4 and 10 Hz, then the received data
is coming from a home-recorded (not original) CD and the DATR should not store the data onto tape.
At this point in the algorithm, the Copy and L bits are assumed to be implemented accurately. If the
Copy bit indicates that copyright has not been asserted, the data is stored on tape and limitless copies
can be made through the digital audio interface. If the Copy bit is set to copyright asserted, then the
L bit must be used to determine if the incoming information is original, or a copy of original data. If
the L bit is set tofirst generation or higher; the DATR will not store the data on tape. If the incoming
data is designated original, the DATR will store the data and store an indication that the data is copyright
protected and not original (a copy). Therefore, no further copies can be made from this recording.
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When the DATR is recording from its internal AID converter, it responds as if the data were coming
from the AID Converters without copyright information category (OI100xx) and sets the Copy bit to
copyright asserted and the L bit to original.
5 CIRCUITS TO ACCOMPLISH SCMS
There are numerous ways to implement the SCMS protocol. Systems containing processors could use
digital audio transmitters and receivers that attach to the processor's bus as peripherals. Using this
approach, the SCMS protocol could be implemented through software on the processor. Systems
without processors could use stand-alone transmitters and receivers with external decode logic to
implement the SCMS protocol. The decode logic described below is implemented using 16VS
programmable logic devices (PLDs) for ease of use. Even though these PLDs are fairly inexpensive,
the designs can be converted to even lower cost PLDs such as 16R4s or 16RSs. Separate circuits are
used to implement each section of the SCMS protocol. In this way, only the circuits needed for a
particular application have to be implemented. Also, the circuits described below could be combined
into larger PLDs for a lower chip count, albeit usually at a higher cost. All files used to program the
PLDs are listed at the end of this paper.
5.1 Transmitters
If the system contains a processor, then the CS8401 Digital Audio Transmitter [16] can be attached to
the processor's parallel bus as a peripheral (as shown in Figure 7). The CSS401 internally buffers an
entire block of channel status data (24 bytes) allowing all channel status bits to be controlled by the
processor. Since the internal buffer is circular, the processor only needs to write the channel status data
when a change is desired. Using the CSS401, the SCMS algorithm is written entirely in software on
the processor.
The CSS402 Digital Audio Transmitter [16] is a stand-alone transmitter that does not need a processor
to implement a digital audio interface. To keep the cost of the CSS40210w, only the most important
channel status bits are available on pins. The other channel status bits can, if desired, be entered through
the C input pin. The channel status bits available on pins are logically OR'edat the proper time to the
data entered on the C pin. One of the charmel status pins - PRO, which is the Professional/Consumer
bit - CO, determines the function of the other five channel status pins. When PRO = 1 (consumer) the
channel status pins of interest to the SCMS protocol are C2 (Copy), CIS (L), and CS/C9 (two MSBs
of the category code). If any of the other category code bits (ClO-CI4) need to be set, they must be
entered on the general purpose channel status input pin C. Figure 8 illustrates a simple method of
entering channel status bits CIO through C14 using an inexpensive 16V8labeled TX_CAT. The CBL
pin output from the CS8402 indicates the start of the channel status block. This PLD counts up from
CBL rising to the proper location of ClO through C14 at which time the ClO through C14 inputs to
the PLD are multiplexed onto the C pin.
Although TX_CAT gets the extra category code bits from pins, the category code bits could be
internally generated allowing for future software updates by reprogramming the PLD. The equation
for COUT can be modified so that the terms used to create COUT consist only of the counter values
when a "1 ': in. the category code is desired. This method is illustrated at the end of the TX_CAT.PDS
file in commented form.
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5.2 Receivers
When a processor is available, the CS8411 Digital Audio Receiver [17] provides the most flexible
approach to implementing the SCMS protocol. The CS8411 internally holds an entire block of channel
status data (24 bytes). This receiver can also interrupt the host processor if any ·of the important data
in bytes 0 to 3 change, thereby greatly reducing the processor overhead. Since the SCMS protocol is
implemented entirely in software, -any changes to the specifications become a software update. The
CS8411 circuit is illustrated in Figure 9.
The CS8412 Digital Audio Receiver [17] is a stand-alone receiver that does not require a processor to
implement the digital audio interface standards. All channel status bits are serially output from the
C pin. The start of the channel status block is indicated on the CBL pin which can be used to locate
the channel status bits of interest. The CS8412 also outputs six of the most important channel status
bits, recovered from the received digital audio data, to pins. These pins are multiplexed with error and
frequency information. Although the pins do not need to be dedicated for channel status, the following
circuits assume the multiplexed pins are in the channel status mode while CBL is high.
The CO output contains the first channel status bit (PRO) and determines the function of the other five
outputs. When CO =1, the data received is from a consumer interface and the other five pins are defined
as: Ca =Cl =AudiolNon-audio, Cb =C2 =Copyright asserted/Copyright not asserted, Cc =C3 =No
Ernphasis/Emphasis Added, Cd = ORlO = Original/Copy, Ce = IOCAT = 0000000 or 01100xx
category codes/all other category codes. The last two pins, ORlO and IOCAT, are-decoded channel
status bits. ORIO is a decoded version of the L bit. Since the L bit definition is inverted for certain
category codes, ORlO takes the category codes into account such that ORlO is always low if the L bit
indicates original. There are two category codes that cannot indicate copyright status: General0000000, and AID Converters without copyright information - 01100xx. When either of these
categories is received, the Copy and L bits should be ignored and the Copy bit forced to copyright
asserted and the L bit to original. IOCAT is low when the incoming channel status indicates either of
these two category codes, thereby giving the system the ability to act accordingly ..
The amount of information needed to implement the SCMS protocol varies based on the type of
equipment being designed (category codes). Although the CS8412 does some decoding in the ORlO
and IOCAT pins, more decoding is necessary to implement the entire SCMS protocol. The.following
circuits are diVIded into three sections that can be optionally implemented based on the type of
equipment being designed. The three circuits are labeled: CONVERT, which fully decodes the Copy
and L bits and indicates when data storage is prohibited; RX_CAT, which indicates when an unknown
category code has been received; and CD_DECOD, which checks for the Copy bit alternating at a
frequency of 4 to 10 Hz indicating that the data received is from a CD player and is not original (a
copy or first generation or higher).
The first CS8412 circuit, shown in Figure 10, uses one 16V8 PLD labeled CONVERT, and provides
the' following fully decoded SCMS outputs: C2, CIS, and COPYPROH. C2 indicates the Copy bit,
CIS indicates the generation status or L bit, and COPYPROH high indicates that the incoming data
should not be stored. If either the "uriknown category code" or "CD copy" circuits are not implemented,
the corresponding inputs, UNKCAT and CDCOPY respectively, should be tied low. The CBLD output
is only needed if the CD_DECOD circuit is used. Since extra space is available in the PLD, other
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channel status bits provided by the CSS412 (CO, Cl, and C3) are latched for convenience. This allows
the CS8412 channel status pins to be used for error and frequency reporting when CBL is low.
The second CS8412 circuit, shown in Figure II, is labeled CD_DECOD and checks for the Copy bit
(C2) alternating between 0 and 1 at a 4 to 10Hz rate. This circuit is also comprised of one 16VS PLD.
If available, the category code received should be input to the PLD; otherwise, the C8 through C14
pins should be set to the CD category code (1000000) since this is the only category where the Copy
bit can alternate. Since the frequency of the Copy bit is extremely low, CBL, which only rises once
every 192 frames, is used as an input to the internal counter which divides CBL by 32. Then
CD_DECOD checks for a transition from 0-to-1 or I-to-O. The CDCOPY output is updated at the end
of the counting interval and is set high if a transition occurred at any time during the interval.
The third CS8412 circuit, shown in Figure 12, is labeled RX_CAT and checks for a valid category
code. This circuit is comprised of two ICs: an HCT595 shift register and latch, and a 16V8 PLD. The
HCT595 shift register continually loads channel status bits from the C pin. RX_CAT counts channel
status bits from the start of the channel status block (CBL going high) and signals the HCT595 to latch
the category code. RX_CAT then compares the latched category code to an internal list of valid category
codes and the UNKCAT output goes high if the category code is undefined. As the standards are
updated and new category codes are defined, RX_CAT can be reprogrammed to include the new
category codes.
5.3 Transceivers
The CSS401 transmitter shown in Figure 7, and the CSS411 receiver shown in Figure 9 can be
connected together on the same bus with different decodes for the chip selects (RD and WR). This
arrangement gives the processor total control of the SCMS protocol, since each chip stores an entire
block of channel status data.
The CSS412 receiver and the CSS402A transmitter can be combined with minor changes to the PLDs.
For example, Figure 13 illustrates a digital audiQ transceiver circuit that implements the entire SCMS
protocol for a pass-through device. Support for the professional interface has also been included. The
previous PLD used to transmit category codes (TX_CAT) has been modified (and renamed TX_CAT2)
to allow professional channel status to pass from the receiver to the transmitter unhindered .. When
receiving the consumer format, TX_CAT2Ioads the entire device category code from inside the PLD
and the CS and C9 pins on the CS8402A are not used. When the AID Converters without copyright
information (01100xx) category code is received, TX_CAT2 transmits the same category code (IGCAT
and C9 indicate that particular category code). Since this PLD has to count from CBL rising to get the
category code locations and since there are extra inputs on TX_CAT2, C1 from the receiver is input
to the PLD and multiplexed into the channel status output COUT at the proper time.
The second PLD changed for the CSS412/02A transceiver circuit is RX_CAT which verifies the
category code received from the CSS412. This receiver PLD has been changed from a 16VS to a 22VlO
PLD to allow for professional mode support. The new PLD,labeled RX_CAT2, still decodes unused
categories, and also decodes sample frequency pins FC1 and FCO on the CSS402A. The sample
frequency channel status bits are C24 and C25 which are received by RX_CAT2 and encoded onto the
FC1 and FCO pins. When a received digital audio interface indicates the professional format (CO =0),
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Sanchez SCIVIS'AES paper
FCI is set high, placing the'CS84'02A in transparent mode and TX_CAT2 allows the received channel
status to flow through to the transmitter. A MODEO output is also included on RX_CAT2 since extra
space is available. This output should always be high since Mode =0 is the only mode defined in the
consumer interface. Since this transceiver circuit is designed for a pass-through device and unknown
category codes are not supposed to be used (according to the digital audio interface standards),the
category code portion, along with the HCT595; could be eliminated and the PLD changed back to a
16V8.
TheCS8425 '[7] is a digital audio transceiver that supports both a software/peripheral and a hard- .
ware/stand-alone mode. Although the CS8425 is designed primarily for the consumer interface, the
professional interface can be minimally supported. The CS8425 can be configured to run the transmitter
and receiver independently, or to lock the transmitter to the receiver. When using the CS8425 with a
processor (see Figure 14), the CS8425 stores two bytes worth of channel status for both the transmitter
and the receiver including all the bits necessary to implement the SCMS protocol. The channel status
bits stored are CO-C4, C8-CI5', C24, and C25 and are illustrated in Figure 15.
The CS8425 can be configured as a stand-alone transceiver that does not need a processor. In this mode
channel status bits can be entered/received through a serial. port, but no ·decoded parallel bits are
available as in the CS8402 transmitter and the CS8412 receiver. Therefore, more decode logic would
be needed to support the full SCMS protocol.
6 CONCLUSION
This paper is intended as a guide to understanding the SCMS protocol. A detailed view of the SCMS
protocol as well as an overview of the digital audio,transmission standards and differences have been
presented. Circuits to implement the SCMS protocol were also presented to aid in the understanding
of the requirements of an SCMS equipped digital audio system.
Although every effort has been made to verify the data presented in this paper, some of the
specifications are ambiguous for certain applications and some specifications are still in the draft stage.
The standards m;e subject to revision and could be amended at any time. Also, this paper does not
address the royalty provisions listed in some specifications [4]. Those wishing to guarantee compliance
should obtain the latest standards information from the appropriate standards organizations.
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7 REFERENCES
[1] IEC-958, Digital Audio Interface, International Electrotechnical Commission, Geneva, Switzerland (1989).
[2] AES3-1992, AES Recommended practice for digital audio engineering - Serial transmission
formatfor two-channel linearly represented digital audio data, Audio Engineering Society, New York,
NY, USA (1992).
[3] IEC-84, Amendment to document IEC-958: Digital Audio Interface, International Electrotechnical Commission, Geneva, Switzerland (1990).
[4] Audio Home Recording Act of 1992, United States Code, Title 17, Chapter 10.
[5] ITTS, Interactive Text Transmission System, Reference Document, Philips Consumer Electronics B. V., Eindhoven, The Netherlands (1992 July)
[6] AES 18-1992, AES Recommended practice for digital audio engineering - Format for the user
data channel of the AES digital audio interface, Audio Engineering Society, New York, NY, USA
(1992).
[7] CS8425 Data Sheet, "A-LAN - Audio Local Area Network Transceiver", DS93PP2, Crystal
Semiconductor Corp., Austin, TX, USA (1992 Aug.).
[8] M. Lambert, "Digital Audio Interfaces", J. Audio Eng. Soc., vol. 38, pp. 681-696 (1990 Sept.).
[9] CP-340, Digital Audio Interface, Electronic Industries Association of Japan. (1987)
[10] CCIR Recommendation 647, A digital audio interface for broadcast studios, Green Book,
vol.lO-part 1, International Radio Consultative Committee (CCIR), Dubrovnik, Yugoslavia (1986).
[11] EBU Tech 3250, Specifications of the digital audio interface, European Broadcast Union
(1985) In process of revision.
[12] RC-5720, Connectors for Optical Fiber Cables for Digital Audio Equipment, Electronic
Industries Association of Japan. (1989)
[13] C. Sanchez and R. Taylor, "Overview of Digital Audio Interface Data Structures",
AN21REVl, Analog/Digital Conversion IC's Data Book, vol. 1, ch. 6, pp. 99-106, Crystal Semiconductor Corp., Austin, TX, USA (1992).
[14] IEC·908, Compact disc digital audio system, International Electrotechnical Commission,
Geneva, Switzerland (1987)
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[15] 60A (CO) 136, DigitalAudio Tape Cassette System - Part 6: Serial Copy Management System,
Draft International Standard from the International Electrotechnical Commission, Geneva, Switzerland
(1991)
[16] CS8401A1CS8402A Data Sheet, "Digital Audio Interface Transmitter", DS60PP5, AnaloglDigital Conversion Ie's Data Book, vol. 1,ch. 2, pp. 229-260, Crystal Semiconductor Corp.,
Austin, TX, USA (1992).
[17] CS8411/CS8412 Data Sheet, "Digital Audio Interface Receiver", DS61PP3, Analog/Digital
Conversion IC's Data Book, vol. 1, ch. 2, pp. 261-294, Crystal Semiconductor Corp., Austin, TX, USA
(1992).
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~---
Start of Channel Status Block
Frame 0 ---~I---- Frame 1
Sub-frame
J
Sub-frame
-1
I
1 4 - - - - - - - - - - - - - - - - - Sub-frame
bit
~---~~--~,r8~-------------------~_r~~~~,
LSB
Audio Data
vo;'"
User Data
~
1) 1
Channel Status Data
Parity Bit
Figure 1. Digital Audio Transmission Format
Professional
Consumer
Standards
AES3-1992
S/PDIF
CP-340: Type I
CP-340 Type-II
IEC-95a Broadcast
IEC-95a Consumer
CCIR647
EBU 3250
Hardware
5Vpp
0.5 Vpp
Balanced
Single Ended
110 0 Twisted Pair
750 Coax
XLR Connectors
RCA/Phono
or Optical
Software
Channel Status Bits
Channel Status Bits
Figure 2. Professional/Consumer Differences
8-167
_-__
_--•..-_
.. .......
..._.-.
Sanchez SeMS AES paper .
byte/bit
..
L.I 0
0 - PRO=1 I Audio I
1
2 3 -
Reference
4 5 -
~
4
I
5
6
7
Fs
User Bit Management
I
Word Length
Reserved
I
Reserved
Reserved
Reserved
Emphasis
Channel Mode
AUX Use
I
-
~~
3
2
I Lock I
23
31
39
47
~--------------------------------------~
87
Alphanumeric channel destination data
i~=:
1
15
55
121 3 - L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1617-
7
Alphanumeric channel origin data
;1~=
l
block
bit
I ..
~
119
Local sample address code
(32-bit binary)
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
:=
~
1
151
Time of day code
1
2021~
(32-bit binary)
~------------------------------------~
~-\
Reserved
Reliability flags
\183
~
~ -\
Cyclic redundancy check character
Figure 3. Professional Channel Status Block Structure
8-168
\191
----------------------
Sanchez SCMS AES paper
byte/bit
+ L.I
~1 =
0
PRO=O I
2 3 -
+
4
5
6
----
2
4
5
6
7
Emphasis
Mode
I
Category Code
I L
Channel
Num.
Source Num.
I
Reserved
Fs
I Clock Acc.
I
3
AuaIo I Copy I
block
bit
I
+
7
15
23
31
39
Reserved
7
8
9
1011 -
121314 -
1516 -
1718-
1920 21-
22 23 -~____________________________________________~191
Figure 4. Consumer Channel Status Block Structure
8-169
.._-_.
.-_
--._.
.. ...
-
~-
-
Sanchez SCMS AES paper
,.£:.R<2.=O-.ico~u~r) _ _ _ _ _
c~o~s~lTle! l!s~ o.f cehlm!1~1 ~ta-,u~ I>100c~
' Professional use of channel status bloc
Audio
~tL
0 - ~qlg!iBJ ~~iq---:1
' Non-Audio
~t~ _ ,Q?pl1 C.QPY.t:i9h L _____
c~py_in)1il>it~-' 9OP~righ! a.ss.ert~ .
:i:
0
' Coov oermitted / copyright not asserted
!;: 1
JII bit ~ !L ,E!e~p~s~ ifEit !J!; Qidi!L.au~o't-=' 0 0 0 c N.o~e.- ? ceh~n!1~ll!u~i() . . . . . . _
100 ~ 55l/~ 5. u~ -.2.c~a!1n.el_a~d!o .
x x 1 ' Reserved - 4 channel audio
bit 0
0
1
t- -
_
~t~!L ,.!!...bi~isJ.Jn.Q!1-~io.L
o00
-
-
000 1 x x x Reserved - Solid state memQIY
/
--
0.0.1. Q0.0. o.iapa.n .
001 001 1United States
~O:< ~ ~¢~u!op~
001 o 0 0 1Electronic software delivl!!Y.
,Digital data
_ _ _ _ _ --c- _ ~
, Mode 0 (defines bytes 1-3 as listed bel w)
i
bit~ _,~o~
t- 0 0
"""'''' """",-"coo.
_______ ~
--
t - OOOQoOO:-G;;-eral
. 0000001, Experimental
0001:~~x: ~oijd:s~t~ r),~m:orY. ' ' , ' , , ,
00 1 x'.x ~ x:
o 1 ox:.x~x:
011 05ll5x!
01101 xx'
0111:xxx;
1 OOx'~~x:
w
x:!< l5X;
!;: 101
11 OX'!igit~d ~~u~d:~mpl~r:
0.1.0. Q 1. O. ¢l)igi~1 ~ign~l.mix~r .
010 1 1 0 0Samole-rate converter
011 o 0 0 OAID converter w/o copy protection i~
011 o 1 0 OAID converter w/ copy protection info
011
Brciadcastrecaption'ofdigitafaudio'
(a~er-qpjicjl( : : : : : : : : : :
1 00
~u~icea~ lr1s!ru,m!ln,ts, ~ic.s" e!c.,
~
~ajJr1e~c ,T~p~ ~r pi~k, , _ , , _ ,
Reserved
L: Generation Status
_
1,0,1,
Category Codes: 10 OX x-;Zx
10 1
001xxxx 0111xxx
1 x x x Reserved - Broadcast rec. of dig. audi!>
000 OCD - compatible with IEC-90B
,-,-,- ",-",O-""a;m""o"";,,,,,,,,-
~ '" io,;..t::::-9
oniY
' : '9riliir:ia!lqo~,n~;c!a~y J;~e-!~90!d~, '
; No indication/1 st generaltion or highE
-
OO.o,O*3Y,nt~e,si~e! ' , , , , , , , , , , ,
1 0 0 !lMicrophone
ClYi~e~ ~~e !e~rd,er_
FSYNC~
'--_5'----1 FSYNCI
__-=3'-1~~ C10
6
C11
_-,-7~
.~ C-1-2
COUT
__-=8~ C13
16V8
---"'-I~
rest of
Category
Code
.. 4
15
CBl 14----'--------'--'----1 CBl
___9---.J C14
17
10
Category
Code
<
TX_CAT
~
C
13..
C8
14..
C9
4 ..
C2
12..
C15
Emphasis _---'-1~ C3
24
3
---=--I~~
FC1
FCO
PRO
Figure 8. CS8402 Transmitter - Category Codes
8-172
----------- -----------
Sanchez SCMS AES paper
+5V
47 kn
19
MCK
-..
-.-
25
ERF
-
Audio
Data
Processor
24
~
CS
-
23
RDIWR
AO-A4
....-
DO- D7
....
Data
Processor
-..
14
INT
CS8411
Audio
11
12
26
FSYNC
SCK
SDATA
or
Microcontroller
...
Figure 9. CS8411 Receiver, Software SCMS
CS8412
FSYNC
C1
C3
-
11
1
CONVERT
--.
2 ~
19:-
5
3
..
-
4
6
CO
15
CBl
- - - 27
IGCAT
-- 2
ORIG
3
4
5:6 ..
C2
-
*CDCOPY
(from CD_DECOD)
*UNKCAT
-
17
...
-
18
...
Emphasis
15
·.
...
·..
Copy
Prohibit
C1
I>
-C11N
-C31N
--
C21N
--
C3
CBlD
COIN
CBl COPYPROH
--IGCAT
--7
C15
-.. ORIG
C2
16V8
8
CDCOPY
9:CO
UNKCAT
..
(from RX_CAT)
16
14
13
12
~
Audio
l
Copy
·.
PRO
111
* if not used, tie input to GND
Figure 10. CS8412 Receiver - SCMS Decode
8-173
----------.-----------
Sanchez SCMS ~ES paper
CBLD
CS8412
(from CONVERT)
4
C2
Either Category
Code if available
or
tieCS high
andC9-C14
low
1
CD-DECOD
-2
3-- C21N
4 ... C8
19
C9
5 :
C10
6:'
C11
16V8
C12
9 ... C13
... C14
CDCOPY
7:
8:
f1
Figure 11. CS8412 Receiver· CD Copy (4.10 Hz) Decode
FSYNC
C
CO
11
11
12 ,2
~ ~
7,8
-
~
" lClKOG
-
14
DIN
11
CS8412
FSYNC
OF
OE
OD
Oc
Os
SClK OA
RESET
CDCOPY
C\l
T,....,...
0
,....
19
1
m co
0000000
-
I".
"(IT,,,
r
,....
16V8
9 8 7 6 5 4 3
6
5
4
3
10
9
8
7
4
3
2
1
15
2
11
~
10
11
12
SCK
C 1
15
CBl
27
IGCAT
AXCm
j
+5V
C8 PlATCH 23
C9
Cl0 MODEO ~
21
Cll 0 FCl
20
C12 :;: FCO
C13 gj CBl
1-l14
C8 C9
24
3
~
C14 AX CIN ~3
CO
FSYNCI
19
UNKCAT t--
ll>
~
TXCBl
>
~
5
C2 4
3
6
cp
....
ORIG 2
7
CO 6
4
Cl 5
2
C3 3
19
_t
COPYPROH
RX_C9
5
3
4
FSYNCI
9
IGCAT
6
CONVERT
9
UNKCAT
~15
CBl
CBLD
8
C21N CDCOPY
12
CO
IGCAT
13
C2
ORIG
14
C15
COIN
17
CllN ~C1
18
~ C3
C31N
FSYNC
RX_CIN
RXCBl COUT
Cl
TX_CAT2
16V8
~
,..
19
17
CS8402A
15
10
CBl
C
F1
en
-
I»
:l
2
4
12
7
1
Figure 13. CS8412102 Transceiver· Pass Through Design
(if
I
.....
FClfTRNPT
FCO
JCO
f----!4.
,..,
i'·
.1:
....
'":.,,
6
C)
PRO
C2
C15
FSYNC
C3
SCK
:::r
IS
en
o
s:
en
:J>
m
'tI
I»
'tI
ell
...
.. ...
.-._._
..--_--~.
Sanchez SCMS AES paper'
+5V
Processor
CS8425
> 47 kn
07-00/
A7-AO
07-00/
A7-AO
.
--..
...
ALE
RO
-
WR
....
INT ....
ALE
RO
WR
-
-
INT
M1
MO
~
~
-
-
-
Figure 14. CS8425 Transceiver - Software SCMS Decode
RCSO
0
1
2
CSO
CS1
CS2
3
456
CS3 ] CS4]
x
7
] CS24 ] CS25 ]}
,
RCS1
csa
CS9
TCSO
x
CS1
Receiver
I CS10 I CS11 I CS12 I CS13 I CS14 I CS15 I
CS2
CS3 ] CS4]
x
] CS24 ] CS25 ]}
.
TCS1
csa
CS9
I
CS10
I CS11 I CS12 I CS13 I CS14 I
Transmitter
CS15
Figure 15. CS8425 Transceiver - Channel Status Register Set
8-176
I
----------- -----------
Sanchez SeMS AES paper
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
Transmit Full Category Codes
PATTERN TX_CAT
REVISION 1.0
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
1/10/93
CHIP
tx_cat
PALCE16V8
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarations --------------PIN 1
FSYNCB
; IN - /FSYNC must be L/R and not I2S format
if I2S pin 1 must be FSYNC
;PIN 2
not used
; IN Category code (byte 1, bit 2)
PIN 3
/CI0
IN
IN - Channel status block start signal
PIN 4
CBL
IN - FSYNC - must be L/R and not I2S format
PIN 5
FSYNCI
IN - Category code (byte 1, bit 3)
PIN 6
/Cll
IN - Category code (byte 1, bit 4)
PIN 7
/C12
PIN 8
/C13
IN - Category code (byte 1, bit 5)
PIN 9
/C14
IN - Category code (byte 1, bit 6)
PIN 10
GND
PIN 11
IN - Output Enable for regs, not used
JOE
PIN 12
A3
OUT - MSB of 4 bit synchronous counter
PIN 13
A2
OUT This counter counts
PIN 14
Al
OUT channel status bits
PIN 15
AO
OUT - LSB of 4 bit synchronous counter
PIN 16
/FSYNC
OUT - /FSYNC - for clock (pin 1)
PIN 17
COUT
OUT - Channel status output
;PIN 18
not used
could be used to enter other channel
;PIN 19
not used
; status bits not supported by the CS8402
PIN 20
VCC
STRING FINISH 'A3 * A2 * A1 * AO'
;----------------------------------- Boolean Equation Segment -----EQUATIONS
A3 - AO are a synchronous counter that counts up and stops at all ones.
CBL low clears counter, CBL high allows counter to count up.
AO .- (/AO + FINISH) * CBL
A1 := (/A1 * AO + A1 * lAO + FINISH) * CBL
A2 := (/A2 * Al * AO + A2 * (/A1 + /AO) + FINISH) * CBL
A3 := (A2 * A1 * AO + A3) * CBL
PAL 1.1 TX_CAT.PDS - Transmit Category Codes
8-177
.._-_
_.-_....__-_._
....-...
'
.
=
IFSYNC
Sanchez SCMS AES paper
connected to clock - pin 1
IFSYNCI
C8 and C9 are entered on CS8412
COUT
+
+
+
+
C10
C11
C12
C13
C14
*
*
*
*
*
A3
A3
A3
A3
A3
* IA2 *
A1 * lAO
A1 * AO
A2 * IA1 * lAO
A2 * IA1 * AO
A2 * A1 * lAO
* IA2 *
*
*
*
C8 - C14 can be internally fixed by entering the counter codes where a
category code bit should equal 1. Using this method, if the category
code has to be updated in the future, this PLD just needs to be
reprogrammed and no hardware needs to be changed.
As an example, if the category code is 101 1000 - microphone
Then the equation for COUT is:
;COUT
A3 * IA2 * IA1 * lAO
A1 * lAO
+ A3 * IA2 * A1 * AD
+ A3 * IA2 *
C8 on (don't use C8 on CS8402)
C10 on
C11 on - all others off by default
PAL 1.2 TX_CAT.PDS - Transmit Category Codes
8-178
----------- ---_._-----
Sanchez SCMS AES paper
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
Receive and convert Copy, L, and Copy Prohibit Flags
PATTERN CONVERT
REVISION 1.1
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
1/13/93
CHIP
_convert PALCE16V8
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarations --------------PIN 1
FSYNC
IN - FSYNC must be L/R and not I2S format
if I2S, pin 1 must be /FSYNC
IN - Channel Status bit 1 - CS8412, Ca
PIN 2
/ClIN
IN - Channel Status bit 2 - CS8412, Cb
PIN 3
/C2IN
IN - Channel Status bit 0 - CS8412, /CO
PIN 4
/COIN
IN - Channel status block start signal
PIN 5
CBL
IN - two category codes - CS84l2, Ce
PIN 6
/IGCAT
IN - decoded L bit - CS8412, Cd
/ORIG
PIN 7
IN - C2 at 4-10Hz rate (CD_DECOD.PDS)
PIN 8
CDCOPY
IN - undefined category code (RX_CAT.PDS)
PIN 9
UNKCAT
GND
PIN 10
IN - Output Enable for regs, not used
PIN 11
fOE
OUT - Latched /CO bit = /PRO
PIN 12
/CO
OUT - decoded copyright bit
PIN 13
/C2
OUT - decoded generation status (L) bit
/C15
PIN 14
OUT - CBL delayed by FSYNC rising
PIN 15
CBLD
OUT - copy prohibit signal
PIN 16
COPYPROH
PIN 17
/C1
OUT - Latched /C1 bit = Audio
PIN 18
/C3
OUT - Latched /C3 bit = /Pre-Emphasis
PIN 19
/C3IN
IN - Channel Status bit 3 - CS8412, Cc
PIN 20
VCC
STRING ENAB
'CBL * /CBLD'
i----------------------------------- Boolean Equation Segment -----EQUATIONS
CBLD := CBL
(also used by CD_DECOD.PDS)
if (received C2 == 1
&& (category code != (0000000 I I 01100xx»
/*
IGCAT
&& (CO != Professional)
then C2 out = 1
/* copyright not asserted */
else C2 out forced to 0
/* copyright asserted */
o
*/
C2 .- C2IN * /IGCAT * /CDCOPY * /COIN * ENAB
+ C2 * CBL * CBLD
+ C2 * /CBL
PAL 2.1 CONVERT.PDS - Convert SCMS Bits
8-179
----------- -----------
Sanchez SCMS AES paper
The Following C15 definitions assumes this PLD IS NOT attached to the
following category codes: o01xxxx , 0111xxx, 100xxxx
C15
:=
ORIG * ICDCOPY * ENAB
+ IGCAT * ENAB
+ COIN * ENAB
+ C15 * CBL * CBLD
+ C15
C15
=
1 if original & !CDCOPY
or if ignorant category
or if professional
* ICBL
The Following C15 definitions assumes this PLD IS attached to the
following category codes: 001xxxx, 0111xxx, 100xxxx
;IC15 .- ORIG * ICDCOPY * ENAB
+ IGCAT * ENAB
+ COIN * ENAB
+ C15 * CBL * CBLD
+ C15 * ICBL
C15
=
0 if original & !CDCOPY
or if ignorant category
or if professional
COPYPROH = TRUE if
(C2 == copy protected && L == 1st generation && !ignorant category)
I I CO == professional channel status (optional)
I I CD - C2 alternating between 4 and 10 Hz rate (copy)
COPYPROH := /C2IN * IORIG * IIGCAT * ENAB
+ ICOIN * ENAB
; add if professional should not be copied
+ CDCOPY * ENAB
+ COPYPROH * CBL * CBLD
+ COPYPROH * ICBL
The following bits are not needed for the SCMS system and they provide a
latched version of the bits on the CS8412. They are latched from the CS8412
when CBL goes high. In this way, CBL can be connected to SEL, and the
error and frequency reporting features of the CS8412 may be used when CBL
is low.
ICO
:=
ICOIN * ENAB
+ ICO * CBL * CBLD
+ ICO * ICBL
latched version of ICO: CO - PRO bit
ICl .- IC1IN * ENAB
+ ICl * CBL * CBLD
+ ICl * ICBL
latched version of IC1: Cl - IAudio
IC3 .- IC3IN * ENAB
+ IC3 * CBL * CBLD
+ IC3 * ICBL
latched version of IC3: C3 - Pre-Emphasis
PAL 2,2 CONVERT.PDS - Convert SCMS Bits
8-180
.-_
._.-.
_
..--__.._-_
...
Sanchez SCMS AES paper
;PALASM Design Description
.---------------------------------- Declaration Segment -----------TITLE
Decodes C2 Alternating Between 4 and 10 Hz
PATTERN CD_DECOD
REVISION 1.1
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
1/15/93
CHIP
_cd_decod
PALCE16V8
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarat10ns --------------CBL delayed (from CONVERT.PDS)
IN
CBLD
PIN 1
IN - Channel Status bit 2 - Copyright bit
/C2IN
PIN 2
IN - Category Code (byte 1, bit 0)
C8
PIN 3
IN - Category Code (byte 1, bit 1)
PIN 4
C9
IN - Category Code (byte 1, bit 2)
C10
PIN 5
IN - Category Code (byte 1, bit 3)
Cll
PIN 6
IN - Category Code (byte 1, bit 4)
PIN 7
C12
IN - Category Code (byte 1, bit 5)
PIN 8
C13
IN - Category Code (byte 1, bit 6)
PIN 9
C14
PIN 10
GND
IN - Output Enable for regs, not used
PIN 11
JOE
A4
OUT - MSB of 5 bit synchronous counter
PIN 12
OUT A3
PIN 13
OUT counts CBLs (-230 Hz)
PIN 14
A2
OUT Al
PIN 15
OUT - LSB of 5 bit synchronous counter
PIN 16
AO
OUT - C2 at start of sequence
PIN 17
CSTART
OUT - C2 changed during sequence
PIN 18
CCNG
CDCOPY
PIN 19
OUT - CCNG at end of sequence
PIN 20
VCC
;----------------------------------- Boolean Equation Segment -----EQUATIONS
A4 - AO are a synchronous counter that counts up and rolls over.
CBL (delayed) is the clock which at Fs = 44.1 kHz produces CBL = -230 Hz
Therefore the counter rolls over at a frequency of 230/32 = 7 Hz
CCNG is looking for a transition on C2 - in either direction.
C2 frequency will be between 4 and 10 Hz which mean a transition will
occur at double that rate or 8 to 20 Hz.
Since CDCOPY is checking for a transition at a 7 Hz rate, CDCOPY should
catch the minimum of 8 Hz.
AD
:=
lAO
Al
:=
/Al * AD + Al * /AO
A2
:=
IA2 * Al * AD + A2 * (/Al + /AO)
A3 := IA3 * A2 * Al * AD + A3 * (jA2 + IA1 + lAO)
M
.-
1M * A3 * A2
* Al * AO
+ A4
* (lA3
+ /A2 + /Al + /AO)
PAL 3.1 CD_DECOD.PDS - Decode CD, C2 changing at 4 to 10 Hz
8~181
--------.--------------
Sanchez SeMS AES paper
; CSTART stores the value of C2IN at the beginning of the counting interval.
CSTART .- C2IN * A4 * A3 * A2 * A1 * /AO
+ CSTART * (/A4 + /A3 + /A2 + /A1 + AD)
CCNG
=
1 if C2IN changes with respect to CSTART at any time during the
counting interval.
CCNG .- CSTART * IC2IN + /CSTART * C2IN
+ CCNG * (/A4 + /A3 + IA2 + /A1 + lAO)
CDCOPY latches CCNG at the end of the counting interval. If C2IN is changing
at a 4 to 10 Hz rate, then CCNG should go high at least once every counting
interval and, since CDCOPY latches CCNG at the end of the interval, CDCOPY
should stay high.
CDCOPY := CCNG * A4 * A3 * A2 * A1 * AD
* C8 * /C9 * /C10 * /C11 * /C12 * /C13 * /C14
+ CDCOPY * (/A4 + /A3 + /A2 + /A1 + lAO)
cat. code 100 0000
If C8 - C14 are not available, tie C8 high and C9 - C14 low.
PAL 3.2 CD_DECOD.PDS - Decode CD, C2 changing at 4 to 10 Hz
8-182
----------- -----------
Sanchez SCMS AES paper
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
Receive Category codes and verify
PATTERN RX_CAT
REVISION 1.0
AUTROR
Clif Sanchez
COMPANY Crystal
DATE
1/2/93
CRIP
_rx_cat
PALCE16V8
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarations --------------FSYNC must be L/R and not I2S format
FSYNC
IN
PIN 1
if I2S pin 1 must be /FSYNC
IN - Category code (byte 1, bit 5)
C13
PIN 2
IN - Category code (byte 1, bit 4)
C12
PIN 3
IN - Channel status block start signal
PIN 4
CBL
FSYNCI
IN - FSYNC - must be L/R and not I2S format
PIN 5
IN - Category code (byte 1, bit 3)
PIN 6
Cll
IN - Category code (byte 1, bit 2)
PIN 7
Cl0
PIN 8
C9
IN - Category code (byte 1, bit 1)
IN - Category code (byte 1, bit 0)
PIN 9
C8
GND
PIN 10
IN - Output Enable for regs, not used
PIN 11
/OE
C14
IN - Category code (byte 1, bit 6)
PIN 12
PIN 13
A3
OUT - MSB of 4 bit synchronous counter
PIN 14
A2
OUT This counter counts
PIN 15
Ai
OUT channel status bits
PIN 16
AO
OUT - LSB of 4 bit synchronous counter
PIN 17
PLATCR
OUT - parallel latch signal for RC595
PIN 18
KNOWN
OUT - some of the valid category codes
PIN 19
UNKCAT
OUT - all unknown category codes
PIN 20
VCC
;----------------------------------- Boolean Equation Segment -----EQUATIONS
A3 - AO form a synchronous counter that counts up to all ones and stops.
CBL low resets counter which waits for CBL high to start counting again.
AO := (/AO + PLATCR) * CBL
Ai := (/Al * AO + Ai * /AO + PLATCR) * CBL
A2 := (/A2 * Ai * AO + A2 * (/Ai + /AO) + PLATCR) * CBL
A3 .- (A2 * Ai * AO + A3) * CBL
PLATCR should rise after channel status bit 15 is latched by the serial
shift register of the RCT595. PLATCR rising causes the RCT595 to internally
parallel load the latch register of the RCT595 from its shift register.
Therefore the HCT595 outputs always contain the category codes.
PLATCR
=
(A3 * A2 * Ai * AO * /FSYNCI + PLATCR) * CBL
PAL 4.1 RX_CAT.PDS - Receive Category Codes
8-183
-
--------
:'==~;=6.
Sanchez SCMS AES paper
UNKCAT is the inverse of all known category codes. Since the 16VB PLD allows
a maximum of 7 OR terms, the total defined category codes must be split over
two output cells, UNKCAT and KNOWN. The actual product terms have been
minimized such that most product terms incorporate two known category codes
as shown in the comment section to the right of each term.
IUNKCAT
+
+
+
+
+
+
KNOWN
ICB * IC9 * IC10 *
ICB * IC9 * C10
ICB * IC9 * C10 *
ICB * C9 * IC10 *
ICB * C9 * IC10
ICB * C9 * C10 *
ICll * IC12
* IC12
ICll * IC12
ICll * IC12
* C12
ICll
* IC13
* IC13 *
*
*
* IC13 *
* IC13 *
IC14
C14
IC14
IC14
IC14
000
001
001
010
010
all
OOOx
xOOO
OOxO
OOxO
x100
OxOO
(2)
(2)
(2)
(2)
(2)
(2)
since KNOWN is OR'd into UNKCAT, KNOWN's product terms are just an
extension of UNKCAT's product terms.
KNOWN
+
+
+
+
CB
CB
CB
CB
CB
* IC9 * IC10 * fC11 * IC12 * IC13 * IC14
* IC9 * IC10 * C11 * IC12 * IC13
* IC9 * C10
* IC12 * IC13 * IC14
* C9 * IC10 * IC11 * IC12 * IC13
* C9 * IC10 * C11 * /C12 * IC13 * IC14
100
100
101
110
110
0000
100x
xOOO
OOOx
1000
(1) CD
(2)
(2)
(2)
(1) VTR
since each output can handle up to seven product terms, KNOWN has room for
two more terms if the defined category code list is updated.
PAL 4.2 RX_CAT.PDS - Receive Category Codes
8-184
----------- -----------
Sanchez SeMS AES paper
;PALASM Design Description
.---------------------------------- Declaration Segment -----------TITLE
Receive Category codes & verify, rec. Fs, and Mode
PATTERN RX_CAT2
REVISION 1.1
AUTHOR
Clif Sanchez
COMPANY Crystal
DATE
1/16/93
CHIP
_rx_cat2
PALCE22V10
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarations --------------FSYNC must be LIR and not I2S format
IN
FSYNC
PIN 1
if I2S pin 1 must be IFSYNC
IN - Category code (byte 1, bit 6)
C14
PIN 2
IN - Category code (byte 1, bit 5)
C13
PIN 3
IN - Category code (byte 1, bit 4)
C12
PIN 4
IN - Channel status block start signal
CBL
PIN 5
IN - FSYNC - must be LIR and,not I2S format
FSYNCI
PIN 6
IN - Category code (byte 1, bit 3)
Cll
PIN 7
IN - Category code (byte 1, bit 2)
C10
PIN 8
IN - Category code (byte 1, bit 1)
PIN 9
C9
IN - Category code (byte 1, bit 0)
PIN 10
C8
IN - Channel Status bit 0 - PRO
PIN 11
ICO
PIN 12
GND
IN - Channel Status from CS8412, C pin
PIN 13
ruCCIN
OUT - LSB of 4 bit synchronous counter
PIN 14
AO
OUT PIN 15
A1
OUT This counter counts
PIN 16
A2
OUT channel status bits
A3
PIN 17
PIN 18
A4
OUT - MSB of 4 bit synchronous counter
PIN 19
UNKCAT
OUT - all unknown category codes
OUT - rx Fs (C24, C25) for CS8402
PIN 20
FCO
PIN 21
FC1
OUT - rx Fs (C24, C25) + Transparent mode
PIN 22
MODEO
OUT - C6 = C7 = 0 - mode 0 (only 1 defined)
PIN 23
PLATCH
OUT - parallel latch signal for HC595
PIN 24
VCC
,._-----------------------------------------------------------------RX_CAT2 replaces RX_CAT in pass through designs that support both
; professional and consumer interfaces.
;----------------------------------- Boolean Equation Segment -----EQUATIONS
A4 - AO form a synchronous counter that counts up to all ones and rolls
over.
CBL low resets counter which waits for CBL high to start counting again.
AO
:=
lAO
A1
:=
(/A1
*
CBL
* AO
+ A1
* lAO) * CBL
A2 .- (/A2 * A1 * AO + A2 * (/A1 + lAO))
* CBL
PAL 5.1 RX:...CA T2.PDS - Rec. Category Codes, Pass Thru Design
8-185
-
--'/1.-------~-~-----
Sanchez SCMS' AES paper
A3 := (/A3 * A2 * Al * AO + A3 * (/A2 + IAl + lAO»
* CBL
A4 := (/A4 * A3 * A2 * Al * AO + A4 * (/A3 + IA2 + IAl + lAO»
* CBL
PLATCH should rise after channE=l status bit 15 is latched by the serial
shift register of the HCT595. PLATCH rising causes the HCT595 to internally
parallel load the latch register of the HCT595 from its shift register.
Therefore the HCT595 outputs always contain the category codes.
PLATCH
=
(/A4 * A3 * A2 * Al * AO * IFSYNCI + PLATCH) * CBL
UNKCAT is the inverse of all known category codes. Since the center
product terms of the 22VIO PLD allows a maximum of 16 OR terms, the total
defined category codes can be contained in one output cell, UNKCAT.
The actual product terms have been minimized such that most product terms
incorporate two known category codes as shown in the comment section to the
right of each term.
IUNKCAT
+
+
+
+
+
+
+
+
+
+
leB *
ICB *
ICB *
ICB *
ICB *
ICB *
CB *
CB *
CB *
CB *
CB *
IC9 * ICIO * ICll *
*.
IC9 * CIO
IC9 * CIO * ICll *
C9 * ICIO * ICll *
*
C9 * ICIO
C9 *
CIO * ICll
* ICll *
* Cll *
*
* ICll *
* Cll *
IC9 * ICIO
IC9 * ICIO
IC9 * CIO
C9 * ICIO
C9 * ICIO
IC12 * IC13
IC12 * IC13 * IC14
* C14
IC12
IC12
* IC14
C12 * IC13 * IC14
* IC13 * IC14
IC12 * IC13 * IC14
IC12 * IC13
IC12 * IC13 * IC14
IC12 * IC13
IC12 * IC13 * IC14
000
001
001
010
010
all
100
100
101
110
110
OOOx
xOOO
OOxO
OOxO
xlOO
OxOO
0000
100x
xOOO
OOOx
1000
(2)
(2)
(2)
(2)
(2)
(2)
(1) CD
(2)
(2)
(2)
(1) VTR
UNKCAT has' room for five more terms if needed
FCl and FCO are used by the CSB402 in consumer mode to set the channel
status bits C24 and C25, sample frequency. When PRO mode is received
CO = 1, FClon the CSB402 is de"fined as TRNPT which defines transparent
mode. In this mode, all parallel channel status inputs are ignored and all
channel status data comes from the C input pin. This PLD uses transparent
mode when professional channel status is received.
.
FCl := RX_CIN * A4 * A3 * IA2 * IAl * lAO
-+ FCl * (/A4 + IA3 + A2 + Al + AO)
+ CO
store C24
any other time, remember FCl
set TRNPT = 1 when CO = 1
FCO := IFCl * RX_CIN * A4 * A3 * IA2 * IAl * AO
+ FCO * (/A4 + IA3 + A2 + Al + lAO)
set if C24 = 1 and C25 = 1
any other time, remember FCO
MODE a is defined in consumer channel status as C6 = C7 = O. This is the
only mode currently defined. The following output indicates when mode a
is received; however, since both C6 and C7 cannot be stored by one output
cell, this pin will go high for one channel status bit period (C6) and then
return low if C6 = a and C7 = 1.
IMODEO
RX_CIN * IA4 * IA3 * A2 * Al * lAO
* (A4 + A3 + IA2 + IAl + AO)
+ RX_CIN * IA4 * fA3 * A2 * Al * AO
:=
+ IMODEO
store C6
any other time remember C6
if C7 = 1, set IMODEO
PAL 5.2 RX-CAT2.PDS - Rec. Category Cj)des, Pass Thru Design
8-186
.._-_
._.-.
_.-_..--__
...
Sanchez SCMS AES paper
;PALASM Design Description
;---------------------------------- Declaration Segment -----------TITLE
Transmit Category Codes, allow A/D exception, pass thru PRO
PATTERN TX_CAT2
REVISION 1.2
AUTHOR
Clif Sanchez
COMPANY Crystal Semiconductor
DATE
1/16/93
CHIP
_tx_cat2
PALCE16V8
; (C) 1993 Crystal Semiconductor Corp.
;---------------------------------- PIN Declarations --------------PIN 1
FSYNCB
IN - /FSYNC must be L/R and not 12S format
if 12S pin 1 must be FSYNC
IN - CS bit 0 - PRO - for pass thru mode
PIN 2
/CO
IN - Receive serial channel status line
RX_CIN
PIN 3
IN - CS block start signal from CS8412
RXCBL
PIN 4
IN - FSYNC - must be L/R and not 12S format
FSYNCI
PIN 5
IN - Channel Status bit 1, /Audio/Non-audio
/C1
PIN 6
; IN unused
;PIN 7
RX_C9
IN - CS bit 9 used in conjunction w/ IGCAT
PIN 8
IN - used with C9 to find A/D w/o copy cat.
/IGCAT
PIN 9
PIN 10
GND
IN - Output Enable for regs, not used
PIN 11
/OE
OUT - MSB of 4 bit synchronous counter
PIN 12
A3
OUT This counter counts
PIN 13
A2
OUT channel status bits
PIN 14
A1
OUT - LSB of 4 bit synchronous counter
PIN 15
AD
OUT - /FSYNC - for clock (pin 1)
PIN 16
/FSYNC
PIN 17
COUT
OUT
Channel status output
CAT_CODE
OUT - this equip. category code
PIN 18
TXCBL
I/O - CS block start signal for CS8402A
PIN 19
PIN 20
VCC
STRING
FINISH 'A3 * A2 * A1 * AO'
i----------------------------------------------------- -------------TX_CAT2 replaces TX_CAT in pass through designs that want to support the
professional mode. Also, a CS8402A is needed since only the "A" version
supports transparent mode.
;----------------------------------- Boolean Equation Segment -----EQUATIONS.
A3 - AO are a synchronous counter that counts up and stops at all ones.
TXCBL low clears counter, TXCBL high allows counter to count up.
AO .- (/AO + FINISH) * TXCBL
A1
:=
(/A1 * AO + A1 * /AO + FINISH) * TXCBL
A2 .- (/A2 * A1 * AO + A2 * (/A1 + /AO) + FINISH) * TXCBL
A3
:=
(A2 * A1 * AO + A3) * TXCBL
PAL 6.1 TX_CAT2.PDS - Tx Category Codes, Pass Thril Design
8-187
-
.-._._
..--__..--_.
...
Sanchez SeMS AES~ paper
TXCBL is an input from the CS8402A in consumer, and an output (RXCBL) when
in professional mode
TXCBL = RXCBL * CO
TXCBL.TRST = CO
connected to clock - pin 1
/FSYNC = /FSYNCI
if (Professional)
COUT = received channel status data, i.e. pass through
else if (received category code != 01100xx)
COUT = CAT_CODE, which is specified category code
else
(received category code == 01100xx)
COUT = 0110000 category code
COUT
+
+
+
+
+
RX_CIN *
C1 * /A3
CAT_CODE
CAT_CODE
A3 * /A2
A3 * /A2
CO
*
*
*
*
*
if PRO
/Audio,
/A2 * /A1 * AO
/IGCAT * /CO
I GCAT * /RX_C9 * /CO
/A1 * AO * IGCAT * RX_C9 *
A1 * /AO * IGCAT * RX_C9 *
- pass thru rec'd CIN
Non-Audio
/CO
/CO
set to category code
0110000 if same rec.
If the CS8412 SEL pin changes between channel status and error/frequency
reporting, IGCAT must be latched.
C8 - C11 & C14 are internally fixed by entering the counter codes only
Do not use category code bits C8 and C9 on CS8402 (tie high)
The category code set below is 0100000 - PCM encoder/decoder. If other
codes are desired, remove semicolon (comment) from start of line for bits
that need to be a one.
CAT_CODE
+
+
+
+
+
+
A3
A3
A3
A3
A3
A3
A3
* /A2 *
* /A2 *
* /A2 *
* /A2 *
* A2 *
* A2 *
* A2 *
/A1
/A1
A1
A1
/A1
/A1
A1
*
*
*
*
*
*
*
AO
/AO
/AO
AO
/AO
AO
/AO
C9 = 1
add if
add if
add if
add if
add if
add if
C8
C10
Cll
C12
C13
C14
needs
needs
needs
needs
needs
needs
to
to
to
to
to
to
be
be
be
be
be
be
PAL 6.2 TX_CAT2.PDS- Tx Category Codes, Pass Thru Design
8-188
a
a
a
a
a
a
1
1
1
1
1
1
--- -------------------
McDonald CS4231 AES paper
A Single Chip Stereo Audio Codec for PC Multimedia Applications
Scott McDonald, Mike Duffy, Tim Dupuis, Bill Wagner
Crystal Semiconductor Corporation
PO Box 17847
Austin, Texas 78760
A system solution has been realized consisting of a single CMOS chip and associated software
providing complete audio capabilities for a multimedia enabled computer. Topics covered in this
paper include design trade-offs between feature implementation in hardware or software, computer
performance issues (sound quality and throughput), chip features and low cost implementation.
1.0 System Architecture
In multimedia computer implementations both software and hardware are required. In this solution,
software components provided include device drivers and input/output control applications. The
hardware features in this mixed signal implementation include stereo delta-sigma analog-to-digital
and digital-to-analog converters (ADC's and DAC's), analog input and output controls, 4 stereoll
monophonic channel mixer, parallel computer bus support and hardware data compression and
decompression. Figure 1 illustrates the block diagram of the chip.
2.0 Software Architecture
Figure 2 shows the general architecture of the audio software support. The application
programming interface (API) provides a hardware independent functional interface for application
writers. The device driver for a particular hardware solution interprets the API interface calls and
invokes the appropriate hardware function. Figure 3 shows an example multimedia programming
environment for Microsoft Windows 3.1. In this case the application programming interface is
called a Media Control Interface or MCI.(Microsoft [1])
In multimedia computer implementations optimized software and hardware architectures are
required for the lowest cost, highest quality implementation. These trade-offs include sound
quality, system throughput, feature set and cost. Performance design goals highlight the
requirements on system architecture and the importance of efficient software. Audio is a real-time
process, however most applications and operating systems today are non real-time. Therefore, most
applications simply slow down when the performance capacity of the computer is exceeded. Since
audio is a real-time process, it cannot slow down; therefore, discontinuities will be inserted into the
This paper was presented at the 95th AES Convention, New York, October 1993, Preprint #3716
8-189
-
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McDonald CS4231 AES paper
data stream. This results in audible errors such as "stutters" or "popping and clicking". System
failures of this nature are very annoying and reduce the usefulness of audio in computing
applications. Careful hardware design and high quality software can minimize these affects for
computer audio applications.
Software applications provide the user interface for the chip feature set. An input and output
control application is provided for this solution with visual control of the volume, input/output
selection, muting and special features such as dither.
3.0 Analog Input and Control
The analog input has a 4-way multiplexer to select the ADC input. Three of the inputs to the chip
are analog and the final input is the output of the mixer. A programmable gain stage is provided at
the input of the ADC providing a 0 to +22.5dB gain adjustment of the signal in 1.5dB steps. In
addition, a 20dB gain block is provided on the microphone input stage to minimize the external
gain required.
Changing the gain of the input circuit at a random time can cause a step function in the output
signal. The magnitude of the step function will depend on the instantaneous value of the signal at
the time the gain is changed. A series of such gain changes can result in an objectionable audible
sound, commonly know as "zipper noise". To overcome this effect, changes in gain are only
allowed to occur on zero crossings of the analog signal. This is achieved using a comparator which
monitors the analog signal and compares it to "zero". (Since this device runs from a power supply
voltage of + 5V, signal zero is approximately 2.10 V.) If the signal does not have a zero crossing
the volume level change will occur after a time out period of between 512 and 1024 samples.
4.0 ADC Architecture
Each ADC uses a 4th-order, switched-capacitor delta-sigma modulator, similar in architecture to
that described by WeIland et al [2]. Capacitor sizes are chosen to minimize die area and yield a
typical dynamic range of 85dB. High frequency anti-alias filtering is achieved by including a series
resistor on the silicon immediately prior to each modulator sampling capacitor. The modulator side
of this resistor is brought out to a pin, where the addition of an external 1000pf NPO capacitor
completes a single pole RC filter. This architecture avoids the need to have a RC filter on each one
of the 3 analog inputs to the input multiplexer, thereby significantly reducing the external
component count. In addition, the location of the filter allows the mixer output to be filtered before
it is digitized by the ADC.
Following the modulator is a 1024-tap FIR filter. This filter has a passband of DC to 0.4 Fs,
passband ripple of 0.1 dB and a stopband rejection of 74 dB. Figures 4, 5 and 6 show the filter
response. The ADC offset is calibrated by a reference "zero" signal being sent to the ADC and
capturing the resulting output code. All subsequent operations with the ADC wi11 have this value
8-190
----------- -----------
McDonald CS4231 AES paper
subtracted to remove the offset. To totally eliminate DC offset for all input conditions, a digital
high pass filter option is controllable at the software interface. This approach eliminates all DC
offsets at all gain settings.
5.0 DAC Architecture
The components of the DACs are a digital interpolation filter, a digital delta-sigma modulator and a
one-bit DAC feeding a switched capacitor output smoothing filter, as previously described by
Sooch et al [3].
The digital interpolation filter uses the silicon efficient multiplier free architecture where the Finite
Impulse Response (FIR) coefficients are reduced to -1,0,+1. (Scott [4]) Compensation for
imperfections in the phase response of the analog switched capacitor filter are also accomplished by
the interpolation filter. This approach yields an overall linear phase response within ±0.50 degrees
out to OAFs (Figure 7).
The DAC also uses a 4th-order digital delta-sigma modulator accepting interpolated data and
outputting a I-bit data stream at 64 Fs or 128 Fs. The higher output I-bit data stream is used at the
lower sampling rates to minimize the noise of the modulator in the audible frequency range. This
data stream is then filtered by a 3-pole Butterworth switched-capacitor filter. Figures 8, 9 and 10
show the overall response of the DAC. The passband is DC to OAFs, the passband ripple is
±O.ldB, and the stopband rejection is 74dB, with an external 2Fs time constant RC filter.
DAC outputs are calibrated to yield a low output offset voltage. The uncalibrated DAC offset is
measured with the previously calibrated ADC. The digital input value required to achieve zero
offset is then stored in an offset calibration register, and is subsequently used to correct all future
conversions.
In the computer environment, data underrun or overrun error conditions will occur when the system
is overloaded. To help avoid audible artifacts during underrun conditions, the DAC will hold the
last sample transmitted to the device. This results in an almost inaudible recovery from this type of
error, particularly if only a few samples are affected.
6.0 Mixer
Three of the stereo inputs (line, auxl and aux2) and the monophonic input are controlled by
independent volume controls and are mixed with the output of the DAC. The volume control on
each of the stereo inputs is controlled by 5-bit volume control registers. The range on the volume
controls is from + 12dB gain to -34.5dB attenuation in 1.5dB steps. A mute is also included for
each channel. These inputs are provided to mix other stereo input sources in a multimedia
computer such as a music synthesizer, CD ROM audio output and an auxiliary input from an
external source such as a cassette or video player. The monophonic input is provided to mix the
8-191
-
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McDonald CS4231 AESpaper
internal monophonic "PC speaker" sound that is provided by most computers. This input has a
4-bit attenuator, providing the control for proper mixing with the other audio signals. Each volume
controlleve1 represents 3dB of attenuation. All stereo volume controls contain zero crossing
detectors, thereby minimizing "zipper noise" in a similar fashion to the input gain stage. The output
of the mixer is stereo and monophonic. The stereo output is a line level signal for use as a high
quality output. The monophonic output is the mix of the left and right channels and is provided as a
output for an internal PC speaker. For this use a amplifier of the appropriate size is selected for the
computer system and driven by the monophonic signal. This mixer provides a single control point
for all the audio in a personal computing environment.
An additional feature of the mixer is calibration. During a full calibration cycle each op amp is
calibrated individually. This procedure provides for minimum offsets throughout the mixer
eliminating most pops and clicks.
7.0 Data Format EncodelDecode
A data format block provides support for several data types and compression/decompression. The
data types supported are 8-bit linear data unsigned format(Figure 11) and 16-bit linear in
two's-complement format. In addition, the 16-bit data stream supports low byte first (little endian)
or high byte first formats (big endian). In the 8-bit linear modes dither can be optionally selected.
When selected, a triangular probability distribution of random noise is added to the signal prior to
quantization. This results in the elimination of artifacts such as the "crunching noise" associated
with quantization.
Data compression (for the ADC output) and decompression (for the DAC input) is also supported in
the form of companding using the CCITT G.711 Il-law and A-law formats (Figure 12) and
Adaptive Differential Pulse Code Modulation (ADPCM) that is compliant with the Interactive
Multimedia Association (IMA) definition. The ADPCM reduces the bus data rate and disk storage
requirements by 4:1, providing near 16-bit quality with only 4 bits per sample.
8.0 Computer Parallel Bus Interface Architecture
The bus interface supports many parallel architectures such as the Industry Standard Architecture
(lSA), Micro Channel and PC98. In addition, the feature set includes 3rd party Direct Memory
Access (DMA), I/O access to control ports, full duplex operation, synchronization timer, 16 sample
First In First Out (FIFO) buffers on input and output and 16 milliamp current drivers for lower cost
implementation. DMA support is provided to minimize the amount of storage required on the audio
device. This is accomplished by allowing the audio device to control data movement in and out of
the host memory using the DMA controller on the host computer. Simultaneous operation of DMA
channels is provided to support full duplex operation (simultaneous capture and playback). The
data format control on capture and playback is controlled independently. This feature allows
applications such as voice control of the PC and audio playback to run together.
8-192
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McDonald CS4231 AES paper
Maximum DMA latency represents the time required to move the required audio data to or from the
device. If the amount of time is exceeded, loss of data on capture or an audible defect on playback
will result. For example, if there is a single sample buffer and the sample rate is 44. 1kHz the
latency would be 22 microseconds. In a computer environment this short period of time can result
in errors. To minimize this effect two 16-sample FIFO buffers are provided. This additional
buffering provides enough latency so that this error condition is virtually eliminated.
The final two features include the synchronization timer and electrical bus drive. The
synchronization timer is provided to aid in the multimedia application execution, particularly the
timing of multiple real time data streams. The timer has a resolution of 10 microseconds and
maximum time of 650 milliseconds. The parallel data path has a bus drive capability of 16 rnA
enabling its use without bus driver chips in many applications.
9.0 Application Schematic and Board Layout
The PC environment is extremely sensitive to implementation cost and printed circuit board layout
area. As shown in the recommended connection diagram in Figure 13, both items are optimized
with this device. All internal signals are internally biased to approximately 2.10 V and require AC
coupling capacitors on all input and output signals.
Printed circuit board layout and grounding are critical items in the use of this device to provide
optimal performance. Figure 14 shows the layout of the printed circuit board around the device,
with the majority of the chip over the analog ground plane and the parallel bus pins over the digital
ground plane. Figure 15 shows the recommended grounding and decoupling capacitor
arrangements. Two important points to notice in this figure are the short decoupling paths and the
component placement of the smaller capacitors, which are as close to the device package as
possible. Crystal offers a free schematic and layout review service, which is best used before the
first prototype circuit board is built. Harris[5] has previously discussed optimum clock choices and
layout guidelines for delta-sigma converters.
10.0 Typical Specification Summary
Analog Inputs & ADC
ADC resolution
Total Dynamic Range
Instantaneous
Dynamic Range
Frequency Response
Input Gain
Step Size
16 bits
95dB
85dB
o to 0.40Fs
Oto 22.5dB
1.5dB
DAC & Analog Outputs
DAC resolution
Total Dynamic Range
Instantaneous
Dynamic Range
Frequency Response
DAC Attenuator
16 bits
95dB
85dB
o to O.4Fs
o to 94.5dB
8-193
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-------~--- -----------
McDonald CS4231 AES paper
Mi.xcl:
Gain!Attenuation
Step Size
+12 to -34.5dB
1.5dB
Global Specifications
Sample Rate
Digital Power Supply
Analog Power Supply
Power Supply Current
Full Scale Signal Level
5.5kHz to 48kHz
+5Vor +3.3V
+5V
110 rnA (+5V)
1 Vnns
All dynamic range specifications are A-weighted. Total dynamic range of the DAC is the ratio
between the full scale output of the chip and the noise floor when the maximum attenuation is
selected. Total dynamic rage of the ADC is the ratio between the full scale input and the noise floor.
The instantaneous dynamic range of the ADC and DAC is measured with the gain and attenuator
set to OdB.
11.0 Conclusions
A complete audio solution has been presented including software and a single chip computer audio
integrated circuit. Complete system design will allow high quality, low cost audio to be easily and
quickly implemented in computing environments.
8-194
----------------------
McDonald CS4231 AES paper
12.0 References
[1] Microsoft Corporation, "Microsoft Windows Multimedia Programmer's Workbook", Microsoft
Press, 1991.
[2] D.R. WeIland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, and K.
Takasuka, "A Stereo 16-Bit Delta-Sigma AID Converter for Digital Audio", JAES, Vol 37, No.6,
June 1989.
[3] N.S.Sooch, J.W.Scott, T.Tanaka, T. Sugimoto, C. Kubomura, "18- Bit Stereo D/A Converter
with Integrated Digital and Analog Filters", 91st AES Convention, October 1991, New York,
Pre-print #3113(y-l).
[4] J.W. Scott, "Multiplier-Free Interpolation for Oversampled Digital-to-Analog Conversion",
92nd AES Convention, March 1992, Vienna, Pre-print #3317.
[5] S. Harris, "How to Achieve Optimum Performance form Delta-Sigma AID & D/A Converters",
AES 93rd Convention, San Francisco, October 1992.
8-195
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McDonald CS4231 AESpaper
ADDR
FIFO
16 Samples
IRQ
LMIC
RMIC
Linear
u-Iaw
A-law
LUNE
RUNE
LAUXI
RAUXI
ADPCM
DBDIR
DBEN
CS
lOR
lOW
Parallel
Bus
Interface
PDRQ
Data Format
CDRQ
f-----++
:g 0.0
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:g
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"
"
-50
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"- -1.0
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-1.5
-2.0
-90
-100
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Inpul Frequency (Fs)
Figure 6. ADC Transition Band
8-198
-0.5
.c
OJ
::;; -70
-so
-j
2.0
-20
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Inpul Frequency (Fs)
Figure 7. DACPhase
----------- -----------
McDonald CS4231 AES paper
0.2
c;--~~----;=r-~-~~~~_____~-~~
-
0.1
-10
-20
·40
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0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
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0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Inpu1 Frequency (Fs)
Figure 8. DAC Frequency Response
Figure 9. DAC Passband Ripple
o'.-~=----------------------------
-10
-20
-30
~
-40
-
~ -50
::l
.~
-60
~ -70
-80
-90
-100+--+_-r-----j----t--r--+---t-~+____j-~
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (Fs)
Figure 10. DAC Transition Band
8-199
----------- -----------
McDonald CS4231 AESpaper
+FS,-----------------------------~
+FS,--------------------------------,
LII
:::>
~
~
o - -- -
~~-'--~-,-,,-~-
- - - - - -
C
8-bit
-FS
unsigned:
0
2.i~~~p: -32768
65
128
191
255
-16384
0
16384
32767
DIGITAL CODE
Figure 11. Linear Transfer Functions
8-200
-FS
A-Law: 2Ah
15h
u~Law:
3Fh
OOh
55h1D5h
7Fh/FFh
95h
BFh
AAh
80h
DIGITAL CODE
Figure 12. Companded Transfer Functions
----------- -----------
McDonald CS4231 AES paper
Ferrite Bead
+5 V
Supply
I -< +5V Analog (optional)
2.0 n
If a separate +5V analog
supply is available, attach here
and remove the 2.0 n resistor.
'"'--.--.---......---------1
0.33 uF
Inputs~
30
27
LLiNE
A1 .JL------I
AO ,10
WR ,61
RD 60
RLiNE
0.33 uF
Auxilary
Inputs
>------1
>
0.33 UF
>0.33 UF
RAUX1
1
LAUX2
1
RAUX2
1
MIN
) 0.33 UF
>0.33 UF
LAUX1
1
0.33 uF
10002p6F RFILT
~
This trace
must be
very short
NPO
,--_--".31'--1 LFILT
1000 pF
V
NPO
I
_ _--3=.:2=-1 VREF
~ 0.47uF
,-----'''--......_--'3''''3'-1 VREFI
~ 10 uF ~ 0.1 uF
CS4231
XCTLO
SAl
SAO
IOWC
IORC
ISA
56
XCTL1
BUS
D7
D6
D5
D4
03
D2
D1
DO
DBDIR
DBEN
PDRQ
CDRQ
PDAK
CDAK
IRQ
-
D7
06
D5
04
D3
D2
D1
DO
1-'-14"--_ _r>--_ _~
12
~13=---_ _ _ _--I
~11-'----_ _ _ _--I
f--"-58=---__{>--_ _~
DGND3 -+ DGND8
DRQ
DRQ
DAK
IRQ
l
Board Analog
Ground
Board Digital
Ground
Figure 13. Typical Connection Diagram
8-201
----------- -----------
McDonald CS4231 AES paper
~1/8"
Digital
Ground
Plilhe
Ground
connection
+5V
Ferrite
Bead
~I
Codec
digital
signals
CPU & Digital
Logic
Codec
analog signals
&
Components
Figure 14. Suggested Layout Guideline
VD
VD
VD
Figure 15. Recommended Decoupling Capacitor Layout
8-202
--- -------------------
Harris CS3310 AES paper
A Single-CJ:Rp Stereo Volume Control
Larry L. Harris and Baker P. Scott III
Crystal Semiconductor Corporation
PO Box 17847
Austin, Texas 78760, USA
A CMOS stereo volume control has been designed specifically for micro-processor controlled audio
systems. It features a 16-bit serial interface that controls two independent audio channels with a
total adjustable range of 127dB in steps of O.5dB. The range is divided into 95.5dB of attenuation
and 31.5dB of gain. The part is capable of driving a load of 600 ohms in parallel with a 100pF
capacitor and achieves 0.0007% THD over a 20Hz to 20kHz bandwidth.
1.0 INTRODUCTION
Digitally controlled, analog signal path volume controls have historically either been large in size
compared to other components in an audio system, or have been small in size with very poor
distortion and noise performance. An example of a large size solution is a stepper motor driving a
wire wound potentiometer. While this solution has very low THD, the potentiometer must be
buffered with a high quality audio amplifier and drive circuits for the stepper motor are necessary.
An example of a small size solution is a multiplying Digital-to-Analog Converter. For a 1kHz
signal which is fed into the reference input, the distortion of a multiplying DAC is typically limited
to 86dB to 88dB.
New digital audio products address the size problem by implementing volume control in the digital
domain. All digital volume controls reduce the output signal but do not reduce the noise. Therefore,
as the signal is attenuated, the signal to noise ratio becomes worse. To address these problems, an
audio volume control, complete with mute functions, and two independent analog audio channels,
has been designed. This part is packaged in a 16 pin SOle. The part achieves 0.0007% THD over
the audio band, has a total integrated noise of IOIlV rms over the audio band, and has virtually no
clicks or pops during volume changes.
As can been seen in Figure 1, the part consist of two completely independent analog channels with
a common digital control port and associated digital control logic to set the volume of the two
analog channels. The analog section is operated from ±5V supplies while the digital section is
operated from OV to 5V supplies.
This paper was presented at the 95th AES Convention, New York, October 1993, Preprint #3759
8-203
-
----------------------
Harris CS331 0 AES paper
2.0 ANALOG SIGNAL PATH
The analog signal path of the chip contains two independent channels. Each channel contains an
input attenuator and a non-inverting buffer amplifier. The non-inverting buffer amplifier has an
attenuator in the feedback path. This feedback path attenuator allows the gain of the non-inverting
buffer amplifier to be adjusted from unity gain to +31.5dB in steps of 0.5dB. The input attenuator
adjustable range is from OdB down to -95.5dB.
Special care in the design and layout of the attenuators insures that minimal distortion and noise is
introduced into the audio path due to the intrinsic non-linear nature of integrated circuit resistors.
The resistor material used is heavily doped polysilicon (approximately 80 ohms per square). To
shield the polysilicon from digitally induced noise present in the substrate, a Pwell is placed
underneath each resistor. The input and output resistor attenuators are laid out in segments of 16dB.
The Pwell shield of the first 16dB input attenuator segment is driven directly by the analog input.
The Pwell shield of the second 16dB input attenuator is driven by a buffered version of the -16dB
analog signal. The Pwell shield of the remaining 16dB input attenuator segments are tied to analog
ground. The technique of driving the Pwell of the first two 16dB attenuators reduces depletion
width modulation of the polysilicon resistors. This technique also bootstraps the non-linear
polysilicon to Pwell capacitance [1], [2]. The output feedback attenuator is similar in construction
to the first two 16dB input attenuator segments, except that the Pwell of the first 16dB output
attenuator is driven by the output of the non-inverting buffer amplifier.
The buffer amplifier is a class A-B amplifier that contains an input common-mode feedback loop
and an offset calibration circuit. A simplified schematic of the buffer amplifier without the
common-mode feedback loop is shown in Figure 2.
The input stage is a conventional folded-cascade design with the addition of a common-mode
current feedback loop. Since this class A-B amplifier is operated in a non-inverting mode, the
amplifier needs to have very high input common-mode rejection. Figure 3 shows a simplified
schematic of the input stage which includes the common-mode current feedback loop. The input
common-mode rejection is improved by the gain of this feedback loop. This feedback loop is a
single pole circuit with the node at which the dominant pole is located being outside of the main
analog signal path. Therefore, the common-mode current feedback has a much higher bandwidth
than the analog signal path, thus allowing good input common-mode rejection even atrelatively
high frequencies.
The output stage of the class A-B amplifier is a composite design. The output pull-down n-channel
transistor is driven by the output of the first stage buffered by a n-channel source follower. The
output pull-up p-channel transistor is driven by a composite amplifier. This composite amplifier
contains a common gate n-channel transistor driven by a common collector p-channel transistor.
The gate of the common collector p-channel is connected to the output of the first stage. The drain
of the common gate n-channel is connected to a p-channel diode that drives the output p-channel
8-204
----------- -----------
Harris CS3310 AES paper
pull-up transistor. The dc bias voltage of the common gate n-channel transistor determines the
crossover characteristics of the output push-pull stage [3]. This amplifier also has a short circuit
current limit of ±20mA.
The offset of the amplifier is calibrated to less than 200IlV. A calibration is invoked when the
"MUTE" pin is taken to +5v. In hardware mute mode, the output of the amplifier is disconnected
from the output bond pad by turning off a series pass gate. The compensation of the amplifier is
switched out of the circuit and the amplifier is operating as a high gain comparator. An offset
calibration current is injected into the first stage p-channel current sources with the output of the
amplifier itself indicating the polarity of the offset. The digital control logic of the calibration forces
the calibration current to servo out the offset of the open-loop amplifier. When the mute pin is taken
back low, the part holds the state of the servo controller thus maintaining a very low offset for the
amplifier [4].
As with any precision analog circuit, the on chip power bus routing is of extreme importance to
insure the channel to channel cross talk is minimized along with keeping artifacts of the digital
control signals out of the analog signal paths. Each analog channel has a separate ground pin which
further improves channel to channel cross talk.
3.0 DIGITAL CONTROL
The digital control port interface is a 3 pin interface consisting of a Chip Select pin, a Serial Data
Input pin, and a Serial Clock pin. There is also a Serial Data Output pin to allow easy daisy
chaining of several volume control parts. This is achieved by connecting together the Chip Select
pin on all of the parts. The Serial Clock pin must also be connected together on all of the parts. The
Serial Data Output pin of the first unit in the chain is connected to the Serial Data Input of the
second unit in the chain. Likewise, the Serial Data Output pin of the second unit in the chain is
connected to the Serial Data Input of the third unit in the chain. This sequence continues on until all
units are connected. This is a very useful feature in multi-channel mixing boards, or in distributed
speaker based intercom/music system, where the individual speaker volume can be tailored to the
environment. Figure 4 is a diagram showing 3 volume control parts connected in a daisy chain.
To change the volume setting of the part, a 16 bit word must be written to the volume control
registers via the control port. To write a new volume setting the Chip Select pin is held low, then
the Serial Data Clock strobes in a 16 bit Serial Data Input word one bit at a time. Figure 5 shows the
timing diagram. After the new volume setting is written to the control port, the Chip Select pin must
be taken back high and held there. In order to allow correct timing in "daisy chained" parts, the
Serial Data Input is latched into the part on rising edges of Serial Clock while the Serial Data
Output changes value on the falling edges of the Serial Clock. Serial Data Output has a 16 bit data
latency from a Serial Data Input.
8·205
-
----------- -----------
Harris CS3310 AES paper
4.0 MISCELLANEOUS FUNCTIONS
A common problem with digitally controlled analog circuits is zipper noise. Zipper noise is a "pop"
or "click" introduced into the audio channel caused by steps in amplitude during volume control
changes. There is a pin selectable feature on the part that only allows analog channel volume
changes to occur when the audio signal is passing through a zero crossing or when a built in timer
times out 0.1 seconds. The built in timer is to insure that the volume setting will change even when
there is no zero crossing of the analog signal. The two analog channels have separate zero crossing
detectors to insure that volume changes to each channel will occur independently. To reduce digital
noise, the built in timer is only operational during changes in the volume setting. The built in timer
and zero crossing detectors are disabled when the zipper noise reduction feature is not selected.
When the zipper noise reduction feature is not selected, the analog volume setting will change
immediately after the Chip Select pin is taken high.
When the part is initially powered up, a power-on-reset circuit is activated which clears all registers
to an all zero's state. This all zero's state is also known as "soft mute"; In "soft mute" mode the
input to the buffer amplifier is connected to "analog ground". This prevents any audible audio
signal from being passed from the analog input, through the buffer amplifier, to the analog output.
This "soft mute" mode is also activated when a volume control setting of all zero's is written to the
control port.
5.0 MEASURED RESULTS
The data presented in Figures 6 & 7 was generated by an Audio Precision System One analyzer.
The bandwidth of the analyzer was limited to 22kHz with a sample rate of 44. 1kHz. The part was
placed into unity gain for these tests and has an output load capacitance of 100pF.
Figure 6 is a plot of three curves showing total harmonic distortion + noise vs. frequency for a 2V
rms input. The first curve (best THD) is for an open circuit load, the second curve is for a load of 2k
ohms, the third curve (worst THD) is for a load of 600 ohms.
Figure 7 is a family of curves showing output total harmonic distortion + noise vs. frequency for
three different input amplitudes. The input amplitudes were 1V rms, 2V rms, and 2.SVims. All these
curves were for an open circuit load.
FigureS is a plot of output attenuation amplitude vs. input code. This data was generated using a
precision 7 digit DVM and a precision low noise dc voltage source. The deviation of the lab data
from that of the ideal line at high attenuation is due to series ground resistance in the analog ground
leads.
Table 1 show all the critical analog characteristics for the part.
8-206
----------- -----------
Harris CS331 0 AES paper
6.0 CONCLUSION
A digitally controlled single chip stereo volume control has been discussed. The performance
levels, cost and power consumption achieved make this device suitable for a wide variety of
applications.
7.0 ACKNOWLEDGMENTS
We would like to thank Dave Souydalay and Pat Radzik for the layout of the chip, A. Ganesan for
the design of the chip's master current bias generator and help in review of this paper, Mark Hagen
and Joel George for taking lab data, and Steve Harris for help in review of this paper and help in
preparing a print quality manuscript.
8.0 REFERENCES
[1] J. L. McCreary, "Matching Properties, and Voltage and Temperature Dependence ofMOS
Capacitors", IEEE J. Solid-State Circuits, vol. SC-16, pp. 608-616, Dec. 1981.
[2] D. A. Kerth, private communication, 1992.
[3] 1. N. Babanezhad and R. Gregorian, "A Programmable GainILoss Circuit",
Solid-State Circuits, vol. SC-22, pp. 1082-1090, Dec. 1987.
IEEE J.
[4] J. H. Atherton and H. T. Simmonds, "An Offset Reduction Technique for Use with CMOS
Integrated Comparators and Amplifiers", IEEE J. Solid-State Circuits, vol. SC-27, pp. 1168-1175,
August 1992.
8-207
-
----------- -_.
--------CS
Harris CS331 0 AES paper
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8-208
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Harris CS331 0 AES paper
THD+N(%) vs FREQ(Hz)
CS3310 L&Rfigure8a
_________ _
28 JUN 93 11 :55:36
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0.0001
20
100
1k
10k
20k
-
Figure 6. THD+N vs. Frequency
2VRMS Ouptut Signal, Volume Set to 0 dB
LOAD =600 ohm, 2 kohm, open ckt
8-209
----------- -----------
Harris CS331 0 AES paper
0.1000
14 JUN 9314:32;39
THD+N(%) vs FREQ(Hz)
CS3310 L&R33VTHD
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Volume Set to 0 dB, LOAD =open ckt,
Signal =1 VRMS, 2 VRMS, 2.8 VRMS
8-210
10k
20k
----------- -----------
Harris CS3310 AES paper
ANALOG CHARACTERISTICS
(TA = 25 cC, VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; RL = 2k.Q; CL = 20 pF;
10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specifiedJ
Parameter
Symbol
Min
DC Characteristics
Steo Size
Gain Error (31.5 dB Gain)
Gain Matching Between Channels
RIN
I~ut Resistance
Input Capacitance
CIN
AC Characteristics
Total Harmonic Distortion plus Noise (Vin = 2Vrms, 1 kHz) THD+N
Dynamic Range
105
Input/Output Voltage Range
I(VA-)+1.25
Output Noise
(Note 1)
-80
Digital Feedthrough (Peak Component)
(1 kHz)
-100
Interchannel Isolation
Out"ut Buffer
(Note 1) Vas
Offset Voltaae
Load Caoacitance
Short Circuit Current
Unity Gain Bandwidth Small Signal
(Note 2)
2
Power Su""lies
Supply Current (No Load, AIN = OV)
IA+
IA10+
Power Consumotion
PD
Power Supply Rejection Ratio (250 Hz)
PSRR
Typ
Max
Units
0.5
+0.05
-
dB
dB
dB
k.Q
of
±D.05
10
25
-
0.001
110
0.0025
8.4
-110
0.25
%
dB
(VA+)-1.25
V
15
!lVrmS
dB
dB
-
-
20
0.75
100
-
-
-
5.0
5.0
350
52.0
80
8.0
8.0
800
84.0
-
-
mV
pF
rnA
MHz
rnA
rnA
uA
mW
dB
Notes: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings> 1.
2. This parameter is guaranteed by design and/or characterization.
Table 1. Analog Characteristics
8-211
--- -------------------
Harris CS331 0 AES paper
.Notes.
8-212
."""'......__..,..,.....
.............
I Music Synthesis I
~
Semiconductor Corporation
Application Note
A Tutorial on MIDI and Wavetable Music Synthesis
by
Jim Heckroth
Introduction
The Musical Instrument Digital Interface (MIDI)
protocol has been widely accepted and utilized
by musicians and composers since its conception
in the 1982/1983 time frame. MIDI data is a
very efficient method of representing musical
performance information, and this makes MIDI
an attractive protocol for computer applications
which produce sound, such as multimedia
presentations or computer games. However, the
lack of standardization of synthesizer capabilities
hindered applications developers and presented
MIDI users with a rather steep learning curve to
overcome. Fortunately, thanks to the publication
of the General MIDI System specification, wide
acceptance of the most common PCIMIDI
interfaces, support for MIDI in Microsoft
WINDOWS, and the evolution of low-cost
high-quality wavetable music synthesizers, the
MIDI protocol is now seeing widespread use in a
growing number of applications. This paper
gives a brief overview of the standards and
terminology associated with the generation of
sound using the MIDI protocol and wavetable
music synthesizers.
Use of MIDI in Multimedia Applications
Originally developed to allow musicians to
connect synthesizers together, the MIDI protocol
is now finding widespread use in the generation
of sound for games and multimedia applications.
There are several advantages to generating sound
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
with a MIDI synthesizer rather than using
sampled audio from disk or CD-ROM. The first
advantage is storage space. Data files used to
store digitally sampled audio in PCM format
(such as .WAV files) tend to be quite large.
This is especially true for lengthy musical pieces
captured in stereo using high sampling rates.
MIDI data files, on the other hand, are extremely
small when compared with sampled audio files.
For instance, files containing high quality stereo
sampled audio require about 10 MBytes of data
per minute of sound, while a typical MIDI
sequence might consume less than 10 KBytes of
data per minute of sound. This is because the
MIDI file does not contain the sampled audio
data, it contains only the instructions needed by
a synthesizer to play the sounds.
These
instructions are in the form of MIDI messages,
which instruct the synthesizer which sounds to
use, which notes to play, and how loud to play
each note. The actual sounds are then generated
by the synthesizer.
The smaller file size also means that less of the
PCs bandwidth is utilized in spooling this data
out to the peripheral which is generating sound.
Other advantages of utilizing MIDI to generate
sounds include the ability to easily edit the
music, and the ability to change the playback
speed and the pitch or key of the sounds
independently. This last point is particularly
important in synthesis applications such as
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
NOV '93
AN27REV3
8-213
-
-_-__-_
.. ...-.
. --_._.
....
MIDI and Music Synthesis Tutorial
karaoke equipment, where the musical key and
tempo of a song may be selected by the user.
The MIDI data output from a MIDI controller or
sequencer is transmitted via the devices' MIDI
OUT connector.
MIDI Systems
The recipient of this MIDI data stream is
commonly a MIDI sound generator or sound
module, which will receive MIDI messages at its
MIDI IN connector, and respond to these
messages by playing sounds. Figure 1 shows a
simple MIDI system, consisting of a MIDI
keyboard controller and a MIDI sound module.
Note that many MIDI keyboard instruments
include both the keyboard controller and the
MIDI sound module functions within the same
unit. In these units, there is an internal link
between the keyboard and the sound module
which may be enabled or disabled by setting the
"local control" function of the instrument to ON
or OFF respectively.
The Musical Instrument Digital Interface (MIDI)
protocol provides a standardized and efficient
means of conveying musical performance
information as electronic data.
MIDI
information is transmitted in "MIDI messages",
which can be thought of as instructions which
tell a music synthesizer how to play a piece of
music. The Synthesizer receiving the MIDI data
must generate the actual sounds. The MIDI 1.0
Detailed Specification, published by the
International MIDI Association, provides a
complete description of the MIDI protocol.
The MIDI data stream is a unidirectional
asynchronous bit stream at 31.25 kbitslsec. with
10 bits transmitted per byte (a start bit, 8 data
bits, and one stop bit). The MIDI interface on a
MIDI instrument will generally include three
different MIDI connectors, labeled IN, OUT, and
THRU.
The MIDI data stream is usually
originated by a MIDI controller, such as a
musical instrument keyboard, or by a MIDI
sequencer. A MIDI controller is a device which
is played as an instrument, and it translates the
performance into a MIDI data stream in real
time (as it is played). A MIDI sequencer is a
device which allows MIDI data sequences to be
captured, stored, edited, combined, and replayed.
The single physical MIDI channel is divided into
16 logical channels by the inclusion of a 4 bit
channel number within many of the MIDI
messages. A musical instrument keyboard can
generally be set to transmit on any one of the
sixteen MIDI channels. A MIDI sound source,
or sound module, can be set to receive on
specific MIDI channel(s).
In the system
depicted in Figure 1, the sound module would
have to be set to receive the channel which the
keyboard controller is transmitting on in order
to play sounds.
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Figure 1: A Simple MIDI System
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MIDI and Music Synthesis Tutorial
Information received on the MIDI IN connector
of a MIDI device is transmitted back out
(repeated) at the devices' MIDI THRU
connector. Several MIDI sound modules can be
daisy-chained by connecting the THRU output
of one device to the IN connector of the next
device downstream in the chain.
using an acoustic bass sound, and the drum
machine plays the percussion part received on
MIDI channel 10.
In the last example, a different sound module is
used to play each part.
However, sound
modules which are "multi-timbral" are capable
of playing several different parts simultaneously.
A single multi-timbral sound module might be
configured to receive the piano part on channel
1, the bass part on channel 5, and the drum part
on channel 10, and would play all three parts
simultaneously.
Figure 2 shows a more elaborate MIDI system.
In this case, a MIDI keyboard controller is used
as an input device to a MIDI sequencer, and
there are several sound modules connected to the
sequencer's MIDI OUT port. A composer might
utilize a system like this to write a piece of
music consisting of several different parts, where
each part is written for a different instrument.
The composer would play the individual parts on
the keyboard one at a time, and these individual
parts would be captured by the sequencer. The
sequencer would then play the parts back
together through the sound modules. Each part
would be played on a different MIDI channel,
and the sound modules would be set to receive
different channels. For example, Sound module
number 1 might be set to play the part received
on channel 1 using a piano sound, while module
2 plays. the information received on channel 5
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Figure 3 depicts a PC-based MIDI system. In
this system, the PC is equipped with an internal
MIDI interface card which sends MIDI data to
an external multi-timbral MIDI synthesizer
module.
Application software, such as
Multimedia presentation packages, educational
software, or games, send information to the
MIDI interface card over the PC bus. The MIDI
interface converts this information into MIDI
messages which are sent to the sound module.
Since this is a multi-timbral module, it can play
many different musical parts, such as piano, bass
and drums, at the same time.
Sophisticated
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Figure 2: An Expanded MIDI System
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MIDI and Music Synthesis Tutorial
MIDI sequencer software packages are also
available for the PC. With this software running
on the PC, a user could connect a MIDI
keyboard controller to the MIDI IN port of the
MIDI interface card, and have the same music
composition capabilities discussed in the last
paragraph.
There are a number of different configurations of
PC-based MIDI systems possible. For instance,
the MIDI interface and the MIDI sound module
might be combined on the PC add-in card. In
fact, the Microsoft Multimedia PC (MPC)
Specification states that a PC add-in sound card
must have an on-board synthesizer in order to be
MPCcompliant. Until recently, most MPC
compliant sound cards included PM synthesizers
with limited capabilities and marginal sound
quality. With these systems, an external
wavetable synthesizer module might be added to
get better sound quality.
Recently, more
advanced sound cards have been appearing
which include high quality wavetable music
synthesizers on-board, or as a daughter-card
options. With the increasing use of the MIDI
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MIDI Messages
A MIDI message is made up of an eight bit
status byte which is generally followed by one or
two data bytes. There are a number of different
types of MIDI messages. At the highest level,
MIDI messages are classified as being either
Channel Messages or System Messages.
Channel messages are those which apply to a
specific channel, and the channel number is
included in the status byte for these messages.
System messages are not channel specific, and
no channel number is indicated in their status
bytes.
Channel Messages may be further
classified as being either Channel Voice
Messages, or Mode Messages. Channel Voice
Messages carry musical performance data, and
these messages comprise most of the traffic in a
typical MIDI data stream.
Channel Mode
messages affect the way a receiving instrument
will respond to the Channel Voice messages.
MIDI System Messages are classified as being
System Common Messages, System Real Time
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Music Scoring
Games
Multimedia Presentation Packages
Educational Packeges
Reference Ubraries
Figure 3: PC-Based MIDI System
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Messages, or System Exclusive Messages.
System Common messages are intended for all
receivers in the system. System Real Time
messages are used for synchronization between
clock-based MIDI components.
System
Exclusive messages include a Manufacturer's
Identification (ID) code, and are used to transfer
any number of data bytes in a format specified
by the referenced· manufacturer. The various
classes of MIDI messages are discussed in more
detail in the following paragraphs.
Channel Voice Messages
Channel Voice Messages are used to send
musical performance information. The messages
in this category are the Note On, Note Off,
Polyphonic Key Pressure, Channel Pressure,
Pitch Bend Change, Program Change, and the
Control Change message.
In MIDI systems, the activation of a particular
note and the release of the same note are
considered as two separate events. When a key
is pressed on a MIDI keyboard instrument or
MIDI keyboard controller, the keyboard sends a
Note On message on the MIDI OUT port. The
keyboard may be set to transmit on anyone of
the sixteen logical MIDI channels, and the status
byte for the Note On message will indicate the
selected channel number. The Note On status
byte is followed by two data bytes, which
specify key number (indicating which key was
pressed) and velocity (how hard the key was
pressed).
The key number is used in the
receiving synthesizer to select which note should
be played, and the velocity is normally used to
control the amplitude of the note. When the key
is released, the keyboard instrument or controller
will send a Note Off message. The Note Off
message also includes data bytes for the key
number and for the velocity with which the key
was released. The Note Off velocity information
is normally ignored.
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Some MIDI keyboard instruments have the
ability to sense the amount of pressure which is
being applied to the keys while they are
depressed. This pressure information, commonly
called "aftertouch", may be used to control some
aspects of the sound produced by the synthesizer
(vibrato, for example). If the keyboard has a
pressure sensor for each key, then the resulting
"polyphonic aftertouch" information would be
sent in the form of Polyphonic Key Pressure
messages. These messages include separate data
bytes for key number and pressure amount. It is
currently
more
common
for
keyboard
instruments to sense only a single pressure level
for the entire keyboard. This "channel
aftertouch" information is sent using the Channel
Pressure message, which needs only one data
byte to specify the pressure value.
The Pitch Bend Change message is normally
sent from a keyboard instrument in response to
changes in position of the pitch bend wheel.
The pitch bend information is used to modify the
pitch of sounds being played on a given channel.
The Pitch Bend message includes two data bytes
to specify the pitch bend value. Two bytes are
required to allow fine enough resolution to make
pitch changes resulting from movement of the
pitch bend wheel seem to occur in a continuous
manner rather than in steps.
The Program Change message is used to specify
the type of instrument which should be used to
play sounds on a given channel. This message
needs only one data byte which specifies the
new program number.
MIDI Control Change messages are used to
control a wide variety of functions in a
synthesizer.
Control Change messages, like
other MIDI channel messages, should only affect
the channel number indicated in the status byte.
The control change status byte is followed by
one data byte indicating the "controller number",
and a second byte which specifies the "control
value". The controller number identifies which
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MIDI and Music Synthesis Tutorial
function of the synthesizer is to be controlled by
the message.
such as reverb or chorus, in synthesizers which
have these capabilities.
Controller Numbers 0 - 31 are generally used for
sending data from switches, wheels, faders, or
pedals on a MIDI controller device such as a
musical instrument keyboard. Control numbers
32 - 63 are used to send an optional Least
Significant Byte (LSB) for control numbers 0
through 31, respectively. Some examples of
synthesizer functions which may be controlled
are modulation (controller number 1), volume
(controller number 7), and pan (controller
number 10). Controller numbers 64 through 67
are used for switched functions. these are the
sustain/damper pedal (controller number 64),
portamento (controller number 65), sostenuto
pedal (controller number 66), and soft pedal
(controller number 67). Controller numbers
16-19 and 80-83 are defined to be general
purpose controllers, and controller numbers
48-51 may be used to send an optional LSB for
controller numbers 16-19. Several of the MIDI
controllers merit more detailed descriptions, and
these controllers are described in the following
paragraphs.
Controller number 6 (Data Entry), in conjunction
with Controller numbers 96 (Data Increment),97
(Data Decrement), 98 (Registered Parameter
Number LSB), 99· (Registered Parameter
Number MSB), 100 (Non-Registered Parameter
Number LSB), and 101 (Non-Registered
Parameter Number MSB), may be used to send
parameter data to a synthesizer in order to edit
sound patches. Registered parameters are those
which have been assigned some particular
function by the MIDI Manufacturers Association
(MMA) and the Japan MIDI Standards
Committee (JMSC). For example, there are
Registered Parameter numbers assigned to
control pitch bend sensitivity and master tuning
for a synthesizer. Non-Registered parameters
have not been assigned specific functions, and
may be used for different functions by different
manufacturers. Parameter data is transferred by
first selecting the parameter number to be edited
using controllers 98 and 99 or 100 and 10 1, and
then adjusting the data value for that parameter
using controller number 6, 96, or 97.
Controller number zero is defined as the bank
select. The bank select function is used in some
synthesizers in conjunction with the MIDI
Program Change message to expand the number
of different instrument sounds which may be
specified (the Program Change message alone
allows selection of one of 128 possible program
numbers). The additional sounds are commonly
organized as "variations" of the 128 addressed
by the Program Change message. Variations are
selected by preceding the Program Change
message with a Control Change message which
specifies a new value for controller zero (see the
Roland General Synthesizer Standard topic
covered later in this paper).
Controller Numbers 121 through 127 are used to
implement the MIDI "Channel Mode Messages".
These messages are covered in the next section.
Controller numbers 91 through 95 may be used
to control the depth or level of special effects,
8·218
Channel Mode Messages
Channel Mode messages (MIDI controller
numbers 121 through 127) affect the way a
synthesizer responds to MIDI data. Controller
number 121 is used to reset all controllers.
Controller number 122 is used to enable or
disable Local Control (In a MIDI synthesizer
which has it's own keyboard, the functions of
the keyboard controller and the synthesizer can
be isolated by turning Local Control off).
Controller numbers 124 through 127 are used to
select between Omni Mode On or Off, and to
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select between the Mono Mode or Poly Mode of
operation.
When Omni mode is On, the synthesizer will
respond to incoming MIDI data on all channels.
When Omni mode is Off, the synthesizer will
only respond to MIDI messages on one channel.
When Poly mode is selected, incoming Note On
messages are played polyphonically. This means
that when multiple Note On messages are
received, each note is assigned its own voice
(subject to the number of voices available in the
synthesizer). The result is that multiple notes are
played at the same time. When Mono mode is
selected, a single voice is assigned per MIDI
channel. This means that only one note can be
played on a given channel at a given time. Most
modem MIDI synthesizers will default to Omni
OnlPoly mode of operation. In this mode, the
synthesizer will play note messages received on
any MIDI channel, and notes received on each
channel are played polyphonically. In the Omni
OfflPoly mode of operation, the synthesizer will
receive on a single channel and play the notes
received on this channel polyphonically. This
mode is useful when several synthesizers are
daisy-chained using MIDI THRU. In this case
each synthesizer in the chain can be set to play
one part (the MIDI data on one channel), and
ignore the information related to the other parts.
Note that a MIDI instrument has one MIDI
channel which is designated as its "Basic
Channel". The Basic Channel assignment may
be hard-wired, or it may be selectable. Mode
messages can only be received by an instrument
on the Basic Channel.
System Common Messages
The System Common Messages which are
currently defined include MTC Quarter Frame,
Song Select, Song Position Pointer, Tune
Request, and End Of Exclusive (EOX). The
MTC Quarter Frame message is part of the
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MIDI Time Code information used for
synchronization of MIDI equipment and other
equipment, such as audio or video tape
machines.
The Song Select message is used with MIDI
equipment, such as sequencers or drum
machines, which can store and recall a number
of different songs. The Song Position Pointer is
used to set a sequencer to start playback of a
song at some point other than at the beginning.
The Song Position· Pointer value is related to the
number of MIDI clocks which would have
elapsed between the beginning of the song and
the desired point in the song. This message can
only be used with equipment which recognizes
MIDI System Real Time Messages (MIDI Sync).
The Tune Request message is generally used to
request an analog synthesizer to retune its'
internal oscillators. This message is generally
not needed with digital synthesizers.
The EOX message is used to flag the end of a
System Exclusive message, which can include a
variable number of data bytes.
III
System Real Time Messages
The MIDI System Real Time messages are used
to synchronize all of the MIDI clock-based
equipment within a system, such as sequencers
and drum machines. Most of the System Real
Time messages are normally ignored by
keyboard instruments and synthesizers. To help
ensure accurate timing, System Real Time
messages are given priority over other messages,
and these single-byte messages may occur
anywhere in the data stream (a Real Time
message may appear between the status byte and
data byte of some other MIDI message). The
System Real Time messages are the Timing
Clock, Start, Continue, Stop, Active Sensing,
and the System Reset message. The Timing
Clock message is the master clock which sets the
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tempo for playback of a sequence. The Timing
Clock message is sent 24 times per quarter note.
The Start, Continue, and Stop messages are used
to control playback of the sequence.
The Active Sensing signal is used to help
eliminate "stuck notes" which may occur if a
MIDI cable is disconnected during playback of a
MIDI sequence. Without Active Sensing, if a
cable is disconnected during playback, then
some notes may be left playing indefinitely
because they have been activated by a Note On
message, but will never receive the Note Off. In
transmitters which utilize Active Sensing, the
Active Sensing message is sent once every 300
ms by the transmitting device when this device
has no other MIDI data to send. If a receiver
who is monitoring Active Sensing does not
receive any type of MIDI messages for a period
of time exceeding 300 ms, the receiver may
assume that the MIDI cable has been
disconnected, and it should therefore turn off all
of its' active notes. Use of Active Sensing in
MIDI transmitters and receivers is optional.
The System Reset message, as the name implies,
is used to reset and initialize any equipment
which receives the message. This message is
generally not sent automatically by transmitting
devices, and must be initiated manually by a
user.
System Exclusive Messages
System Exclusive messages may be used to send
data such as patch parameters or sample data
between MIDI devices. Manufacturers of MIDI
equipment may define their own formats for
System Exclusive data.
Manufacturers are
granted unique identification (ID) numbers by
the MMA or the JMSC, and the manufacturer ID
number is included as the second byte of the
System Exclusive message. The manufacturers
ID byte is followed by any number of data
bytes, and the data transmission is terminated
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MIDI and Music Synthesis Tutorial
with the EOX message. Manufacturers are
required to publish the details of their System
Exclusive data formats, and other manufacturers
may freely utilize these formats, provided that
they do not alter or utilize the format in a way
which conflicts with the original manufacturers
specifications.
There is also a MIDI Sample Dump Standard,
which is a System Exclusive data format defined
in the MIDI specification for the transmission of
sample data between MIDI devices.
Running Status
MIDI data is transmitted serially.
Musical
events which originally occurred at the same
time must be sent one at a time in the MIDI data
stream, and therefore these events will not
actually be played at exactly the same time.
However, the resulting delays are generally short
enough that the events are perceived as having
occurred simultaneously.
The MIDI data
transmission rate is 31.35 kbitls with 10 bits
transmitted per byte of MIDI data. Thus, a 3
byte Note On or Note Off message takes about 1
ms to be sent. For a person playing a MIDI
instrument keyboard, the time skew between
playback of notes when 10 keys are pressed
simultaneously should not exceed 10 ms, and
this would not be perceptible. However, MIDI
data being sent from a sequencer can include a
number of different parts. On a given beat, there
may be a large number of musical events which
should occur simultaneously, and the delays
introduced by serialization of this information
might be noticeable.
To help reduce the amount of data transmitted in
the MIDI data stream, a technique called
"running status" may be employed. It is very
common for a string of consecutive messages to
be of the same message type. For instance,
when a chord is played on a keyboard, 10
successive Note On messages may be generated,
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----------- ----------followed by 10 Note Off messages. When
running status is used, a status byte is sent for a
message only when the message is not of the
same type as the last message sent on the same
channel. The status byte for subsequent
messages of the same type may be omitted (only
the data bytes are sent for these subsequent
messages). The effectiveness of running status
can be enhanced by sending Note On messages
with a velocity of zero in place of Note Off
messages. In this case, long strings of Note On
messages will often occur. Changes in some of
the the MIDI controllers or movement of the
pitch bend wheel on a musical instrument can
produce a staggering number of MIDI channel
voice messages, and running status can also help
a great deal in these instances.
MIDI Sequencers and Standard MIDI files
MIDI messages are received and processed by a
MIDI synthesizer in real time.
When the
synthesizer receives a MIDI "note on" message it
plays the appropriate sound.
When the
corresponding "note off" message is received,
the synthesizer turns the note off. If the source
of the MIDI data is a musical instrument
keyboard, then this data is being generated in
real time. When a key is pressed on the
keyboard, a "note on" message is generated in
real time. In these real time applications, there
is no need for timing information to be sent
along with the MIDI messages. However, if the
MIDI data is to be stored as a data file, and/or
edited using a sequencer, then some form of
"time-stamping" for the MIDI messages is
required.
The International MIDI Association publishes a
Standard MIDI Files specification, which
provides a standardized method for handling
time-stamped MIDI data. This standardized file
format for time-stamped MIDI data allows
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different applications, such as sequencers,
scoring packages, and multimedia presentation
software, to share MIDI data files.
The specification for Standard MIDI Files
defines three formats for MIDI files. MIDI
sequencers can generally manage multiple MIDI
data streams, or "tracks". MIDI files having
Format 0 must store all of the MIDI sequence
data on a single track. This is generally useful
only for simple "single track" devices. Format I
files, which are the most commonly used, store
data as a collection of tracks. Format 2 files can
store several independent patterns.
Synthesizer Polyphony and Timbres
The polyphony of a sound generator refers to its
ability to play more than one note at a time.
Polyphony is generally measured or specified as
a number of notes or voices. Most of the early
music synthesizers were monophonic, meaning
that they could only play one note at a time. If
you pressed five keys simultaneously on the
keyboard of a monophonic synthesizer, you
would only hear one note. Pressing five keys on
the keyboard of a synthesizer which was
polyphonic with four voices of polyphony
would, in general, produce four notes. If the
keyboard had more voices (many modem sound
modules have 16, 24, or 32 note polyphony),
then you would hear all five of the notes.
The different sounds that a synthesizer or sound
generator can produce are often referred to as
"patches", "programs", "algorithms", sounds, or
"timbres". Modern synthesizers commonly use
program numbers to represent different sounds
they produce. Sounds may then be selected by
specifying the program numbers (or patch
numbers) for the desired sound. For instance, a
sound module might use patch number 1 for its
acoustic piano sound, and patch number 36 for
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III
---------------------its fretless bass sound. The association of patch
numbers to sounds is often referred to as a patch
map. A MIDI Program Change message is used
to tell a device receiving on a given channel to
change the instrument sound being used. For
example, a sequencer could set up devices on
channel 4 to play fretless bass sounds by sending
a Program Change message for channel four
with a data byte value of 36 (this is the General
MIDI program number for the fretless bass
patch).
A synthesizer or· sound generator is said to be
multi-timbral if it is capable of producing two or
more different instrument sounds simultaneously.
Again, if a synthesizer can play five notes
simultaneously, then it is polyphonic. If it can
produce a piano sound and an acoustic bass
sound at the same time, then it is also
multi-timbral. A synthesizer or sound module
which has 24 notes of polyphony and which is 6
part multi-timbral (capable of producing 6
different
timbres
simultaneously)
could
synthesize the sound of a 6 piece band or
orchestra.
A sequencer could send MIDI
messages for a piano part on channell, bass on
channel 2, saxophone on channel 3, drums on
channel 10, etc. A 16 part multi-timbral
synthesizer could receive a different part on each
of MIDI's 16 logical channels.
The polyphony of a multi-timbral synthesizer is
usually allocated dynamically among the
different parts (timbres) being used. In our
example, at a given instant five voices might be
used for the piano part, two voices for the bass,
one for the saxophone, and 6 voices for the
drums, leaving 10 voices free. Note that some
sounds utilize more than one voice, so the
number of notes which may be produced
simultaneously may be less than the stated
polyphony of the synthesizer, depending on
which sounds are being utilized.
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MIDI and Music Synthesis Tutorial
The General MIDI (GM) System
At the beginning of a MIDI sequence, a Program
Change message is usually sent on each channel
used in the piece in order to set up the
appropriate instrument sound for each part. The
Program Change message tells the synthesizer
which patch number should be used for a
particular MIDI channel. If the synthesizer
receiving the MIDI sequence uses the same
patch map (the assignment of patch numbers to
sounds) that was used in the composition of the
sequence, then the sounds will be assigned as
intended. Unfortunately, prior to General MIDI,
there was no standard for the relationship of
patch numbers to specific sounds for
synthesizers. Thus, a MIDI sequence might
produce different sounds when played on
different synthesizers, even though the
synthesizers had comparable types of sounds.
For example, if the composer had selected patch
number 5 for channel I, intending this to be an
electric piano sound, but the synthesizer playing
the MIDI data had a tuba sound mapped at patch
number 5, then the notes intended for the piano
would be played on the tuba when using this
synthesizer (even though this synthesizer may
have a fine electric piano sound available at
some other patch number).
The General MIDI (GM) Specification,
published by the International MIDI Association,
defines a set of general capabilities for General
MIDI Instruments.
The General MIDI
Specification includes the definition of a General
MIDI Sound Set (a patch map), a General MIDI
Percussion map (mapping of percussion sounds
to note numbers), and a set of General MIDI
Performance capabilities (number of voices,
types of MIDI messages recognized, etc.). A
MIDI sequence which has been generated for
use on a General MIDI Instrument should play
correctly on any General MIDI synthesizer or
sound module.
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MIDI and Music Synthesis Tutorial
The General MIDI system utilizes MIDI
channels 1-9 and 11-16 for chromatic instrument
sounds, while channel number 10 is utilized for
"key-based" percussion sounds. The General
MIDI Sound set for channels 1-9 and 11-16 is
given in table 1. These instrument sounds are
grouped into "sets" of related sounds. For
example, program numbers 1-8 are piano
sounds, 6-16 are chromatic percussion sounds,
17-24 are organ sounds, 25-32 are guitar sounds,
etc.
The General MIDI system specifies which
instrument or sound corresponds with each
program/patch number, but General MIDI does
not specify how these sounds are produced.
Thus, program number 1 should select the
Acoustic Grand Piano sound on any General
MIDI instrument. However, the Acoustic Grand
Piano sound on two General MIDI synthesizers
which use different synthesis techniques may
sound quite different.
For the instrument sounds on channels 1-9 and
11-16, the note number in a Note On message is
used to select the pitch of the sound which will
be played. For example if the Vibraphone
instrument (program number 12) has been
selected on channel 3, then playing note number
60 on channel 3 would play the middle C note
(this would be the default note to pitch
assignment on most instruments), and note
number 59 on channel 3 would play B below
middle C. Both notes would be played using the
Vibraphone sound.
The Roland
Standard
The General MIDI percussion map used for
channel 10 is given in table 2. For these
"key-based" sounds, the note number data in a
Note On message is used differently. Note
numbers on channel 10 are used to select which
drum sound will be played. For example, a Note
On message on channel 10 with note number 60
will playa Hi Bongo drum sound. Note number
59 on channel 10 will play the Ride Cymbal 2
sound.
It should be noted that the General MIDI system
specifies sounds using program numbers 1
through 128.
The MIDI Program Change
message used to select these sounds uses an 8-bit
byte, which corresponds to decimal numbering
from 0 through 127, to specify the desired
program number. Thus, to select GM sound
number 10, the Glockenspiel, the Program
Change message will have a data byte with the
decimal value 9.
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General
Synthesizer
(GS)
The Roland General Synthesizer (GS) functions
are a superset of those specified for General
MIDI. The GS system includes all of the GM
sounds (which are referred to as "capital
instrument" sounds), and adds new sounds which
are organized as variations of the capital
instruments.
Variations are selected using the MIDI Control
Change message in conjunction with the
Program Change message. The Control Change
message is sent first, and it is used to set
controller number 0 to some specified nonzero
value indicating the desired variation (some
capital sounds have several different variations).
The Control Change message is followed by a
MIDI Program Change message which indicates
the program number of the related capital
instrument. For example, Capital instrument
number 25 is the Nylon String Guitar. The
Ukulele is a variation of this instrument. The
Ukulele is selected by sending a Control Change
message which sets controller number 0 to a
value of 8, followed by a program change
message on the same channel which selects
program number 25.
Sending the Program
change message alone would select the capital
instrument, the Nylon String Guitar. Note also
that a Control Change of controller number 0 to
a value of 0 followed by a Program Change
message would also select the capital instrument.
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Pr02#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Instrument Name
Acoustic Grand Piano
Bright Acoustic Piano
Electric Grand Piano
Honky-tonk: Piano
Electric Piano 1
Electric Piano 2
Harpsichord
Clavi
Celesta
Glockenspiel
Music Box
Vibraphone
Marimba
Xylophone
Tubular Bells
Dulcimer
Drawbar Organ
Percussive Organ
Rock Organ
Church Organ
Reed Organ
Accordion
Harmonica
Tango Accordion
Acoustic Guitar (nylon)
Acoustic Guitar (steel)
Electric Guitar Uazz)
Electric Guitar (clean)
Electric Guitar (muted)
Overdriven Guitar
Distortion Guitar
Guitar harmonics
Acoustic Bass
Electric Bass (finger)
Electric Bass (pick)
Fretless Bass
Slap Bass 1
Slap Bass 2
Synth Bass 1
Synth Bass 2
Violin
Viola
Cello
MIDI and Music Synthesis Tutorial
Pro2#
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Instrument Name
Contrabass
Tremolo Strings
Pizzicato Strings
Orchestral Harp
Timpani
String Ensemble 1.
String Ensemble 2
SynthStrings 1
SynthStrings 2
Choir Aahs
Voice Oohs
Synth Voice
Orchestra Hit
Trumpet
Trombone
Tuba
Muted Trumpet
French Horn
Brass Section
SynthBrass 1
SynthBrass 2
Soprano Sax
Alto Sax
Tenor Sax
Baritone Sax
Oboe
English Horn
Bassoon
Clarinet
Piccolo
Flute
Recorder
Pan Flute
Blown Bottle
Shakuhachi
Whistle
Ocanna
Lead 1 (square)
Lead 2 (sawtooth)
Lead 3 (calliope)
Lead 4 (chiff)
Lead 5 (charang)
Lead 6 (voice)
Pro2#
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Instrument Name
Lead 7 (fifths)
Lead 8 (bass + lead)
Pad 1 (new age)
Pad 2 (warm)
Pad 3 (polysynth)
Pad 4 (choir)
Pad 5 (bowed)
Pad 6 (metallic)
Pad 7 (halo)
Pad 8 (sweep)
FX 1 (rain)
FX 2 (soundtrack)
FX 3 (crystal)
FX 4 (atmosphere)
FX 5 (brightness)
FX 6 (goblins)
FX 7 (echoes)
FX 8 (sci-fi)
Sitar
Banjo
Shamisen
Koto
Kalimba
Bag pipe
Fiddle
Shanai
Tinkle Bell
Agogo
Steel Drums
Woodblock
Taiko Drum
Melodic Tom
Synth Drum
Reverse Cymbal
Guitar Fret Noise
Breath Noise
Seashore
Bird Tweet
Telephone Ring
Helicopter
Applause
Gunshot
Table 1: General MIDI Sound Set (All Channels Except 10)
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MIDI and Music Synthesis Tutorial
Note # Drum Sound
35
Acoustic Bass Drum
36
Bass Drum 1
Side Stick
37
38
Acoustic Snare
39
Hand Clap
40
Electric Snare
41
Low Floor Tom
Closed Hi-Hat
42
43
High Floor Tom
44
Pedal Hi-Hat
45
Low Tom
46
Open Hi-Hat
47
Low Mid Tom
48
Hi Mid Tom
49
Crash Cymbal 1
50
High Tom
Note # Drum Sound
Ride Cymbal 1
51
Chinese Cymbal
52
53
Ride Bell
54
Tambourine
55
Splash Cymbal
56
Cowbell
Crash Cymbal 2
57
58
Vibraslap
Ride Cymbal 2
59
60
Hi Bongo
61
Low Bongo
62
Mute Hi Conga
63
Open Hi Conga
64
Low Conga
65
High Timbale
66
Low Timbale
Note # Drum Sound
High Agogo
67
Low Agogo
68
Cabasa
69
Maracas
70
71
Short Whistle
Long Whistle
72
Short Guiro
73
74
Long Guiro
Claves
75
76
Hi Wood Block
77
Low Wood Block
78
Mute Cuica
Open Cuica
79
80
Mute Triangle
81
Open Triangle
Table 2: General MIDI Percussion Map (Channel 10)
The GS system also includes adjustable
reverberation and chorus effects. The effects
depth for both reverb and chorus may be
adjusted on an. individual MIDI channel basis
using Control Change messages. The type of
reverb and chorus sounds employed may also be
selected using System Exclusive messages.
Synthesizer
Wavetable
Implementations:
FM
vs.
There are a number of different technologies or
algorithms used to create sounds in music
synthesizers. Two widely used techniques are
Frequency Modulation (FM) synthesis and
Wavetable synthesis. FM synthesis techniques
generally use one periodic signal (the modulator)
to modulate the frequency of another signal (the
carrier). If the modulating signal is in the
audible range, then the result .will be a
significant change in the timbre of the carrier
signal. Each PM voice requires a minimum of
two signal generators. These generators are
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commonly referred to as "operators", and
different PM synthesis implementations have
varying degrees of control over the operator
parameters. Sophisticated FM systems may use
4 or 6 operators per voice, and the operators may
have adjustable envelopes which allow
adjustment of the attack and decay rates of the
signal. Although FM systems were implemented
in the analog domain on early synthesizer
keyboards,
modem
FM
synthesis
implementations are done digitally.
FM synthesis techniques are very useful for
creating expressive new synthesized sounds.
However, if the goal of the synthesis system is
to recreate the sound of some eXlstmg
instrument, this can generally be done more
accurately with digital sample-based techniques.
Digital sampling systems store high quality
sound samples digitally, and then replay these
sounds on demand. Digital sample-based
synthesis systems may employ a variety of
special techniques, such as sample looping, pitch
shifting,
mathematical
interpolation,
and
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MIDI and Music Synthesis Tutorial
polyphonic digital filtering, in order to reduce
the amount of memory required to store the
sound samples (or to get more types of sounds
These
from a given amount of memory).
sample-based synthesis systems are often called
"wavetable" synthesizers (the sample memory in
these systems contains a large number of
sampled sound segments, and can be thought of
as a "table" of sound waveforms which may be
looked up and utilized when needed). A number
of the special techniques employed in this type
of synthesis are discussed in the following
paragraphs.
where the characteristics of the sound are
changing less dynamically. Figure 4 shows a.
waveform with portions which could be
considered the attack and the sustain sections
In this example, . the spectral
indicated.
characteristics of the waveform remain constant
throughout the sustain section, while the
amplitude is decreasing at a fairly constant rate.
This is an exaggerated example, in most natural
instrument
sounds,
both
the
spectral
characteristics and the amplitude continue to
change through the duration of the sound. The
sustain section, if one can be identified, is that
section for which the characteristics of the sound
are relatively constant.
Wavetable Synthesis Techniques
Looping and Envelope Generation
One of the primary techniques used in wavetable
synthesizers to conserve sample memory space is
the looping of sampled sound segments. For a
large. number of instrument sounds, the sound
can be modeled as consisting of two major
sections, the attack section and the sustain
section. The attack section is the initial part of
the sound, where the amplitude and the spectral
characteristics of the sound may be changing
very rapidly. The sustain section of the sound is
that part of the sound following the attack,
Attack Section
A great deal of memory can be saved in
wave-table synthesis systems by storing only a
short segment of the sustain section of the
waveform, and then looping this segment during
playback. Figure 5 shows a two period segment
of the sustain section from the waveform in
Figure 4, which has been looped to create a
steady state signal. If the original sound had a
fairly constant spectral content and amplitude
during the sustained section, then the sound
resulting from this looping operation should be a
good approximation of the sustained section of
the original.
Sustain Section
Figure 4: Attack and Sustain Portions of a waveform
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MIDI and Music Synthesis Tutorial
For many acoustic string instruments, the
spectral characteristics of the sound remain fairly
constant during the sustain section, while the
amplitude of the signal decays. This can be
simulated with a looped segment by multiplying
the looped samples by a decreasing gain factor
during playback to get the desired shape or
envelope. The amplitude envelope of a sound is
commonly modeled as consisting of some
number of linear segments. An example is the
commonly used four part piecewise-linear
Attack-Decay-Sustain-Release (ADSR) envelope
model.
Figure 6 depicts a typical ADSR
envelope shape, and Figure 7 shows the result of
applying this envelope to the looped waveform
from Figure 5.
A typical wavetable synthesis system would
store separate sample segments for the attack
~I
I
I
I-I
section and the looped section of an instrument.
These sample segments might be referred to as
the initial sound and the loop sound. The initial
sound is played once through, and then the loop
sound is played repetitively until the note ends.
An envelope generator function is used to create
an envelope which is appropriate for the
particular instrument, and this envelope is
applied to the output samples during playback.
Playback of the initial wave (with the the Attack
portion of the envelope applied) begins when a
Note On message is received. The length of the
initial sound segment is fixed by the number of
samples in the segment, and the length of the
Attack and Decay sections of the envelope are
generally also fixed for a given instrument
sound. The sustain section will continue to
repeat the loop samples while applying the
Sustain envelope slope (which decays slowly in
2 period segment
of sustain sound
-
Wavefonn resuHing from
looping segment above
Figure 5: Looping a Sound Segment
Ampl~ude
4-------~----~----------------------__--------~.
:
Attack
Decay
Sustain
TIme
Release
Figure 6: A Typical ADSR Amplitude Envelope
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MIDI and Music Synthesis Tutorial
'I
1
1
1
1
Attack
,
Decay
Sustain
Release
1
Figure 7: ADSR Envelope Applied to Looped Sound Segment
our examples), until a Note Off message is
applied. The Note Off message triggers the
beginning of the Release portion of the
envelope.
Loop Length
The loop length is measured as a number of
samples, and the length of the loop should be
equal to an integral number of periods of the
fundamental pitch of the sound being played (if
this is not true, then an undesirable "pitch shift"
will occur during playback when the looping
begins). Of course, the length of the pitch
period of a sampled instrument sound will
generally not work out to be an integral number
of sample periods. Therefore, it is common to
perform a "resampling" process on the original
sampled sound, to get new a new sound sample
for which the pitch period is an integral number
of sample periods.
In practice, the length of the loop segment for an
acoustic instrument sample may be many periods
with respect to the fundamental pitch of the
sound. If the sound has a natural vibrato or
chorus effect, then it is generally desirable to
have the loop segment length be an integral
multiple of the period of the vibrato or chorus.
8-228
One-Shot Sounds
The previous paragraphs discussed dividing a
sampled sound into an attack section and a
sustain section, and then using looping
techniques to minimize the storage requirements
for the sustain portion. However, some sounds,
particularly sounds of short duration or sounds
whose characteristics change dynamically
throughout their duration, are not suitable for
looped playback techniques. Short drum sounds
often fit this description. These sounds are
stored as a single sample segment which is
played once through with no looping. This class
of sounds are referred to as "one-shot" sounds.
Sample Editing and Processing
There are a number of sample editing and
processing steps involved in preparing sampled
sounds for use in a wave-table synthesis system.
The requirements for editing the original sample
data to identify and extract the initial and loop
segments, and for resampling the data to get a
pitch period length which is an integer multiple
of the sampling period, have already been
mentioned.
Editing may also be required to make the
endpoints of the loop segment compatible. If the
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__ ...amplitude and the slope of the waveform at the
beginning of the loop segment do not match
those at the end of the loop, then a repetitive
"glitch" will be heard during playback of the
looped section. Additional processing may be
performed to "compress" the dynamic range of
the sound to improve the signal/quantizing noise
ratio or to conserve sample memory. This topic
is addressed next.
When all of the sample processing has been
completed, the resulting sampled sound
segments for the various instruments are
tabulated to form the sample memory for the
synthesizer.
Sample Data Compression
The signal-to-quantizing noise ratio for a
digitally sampled signal is limited by sample
word size (the number of bits per sample), and
by the amplitude of the digitized signal. Most
acoustic instrument sounds reach their peak
amplitude very quickly, and the amplitude then
slowly decays from this peak.
The ear's
sensitivity dynamically adjusts to signal level.
Even in systems utilizing a relatively small
sample word size, the quantizing noise level is
generally not perceptible when the signal is near
maximum amplitude. However, as the signal
level decays, the ear becomes more sensitive,
and the noise level will appear to increase. Of
course, using a larger word size will reduce the
quantizing noise, but there is a considerable
price penalty paid if the number of samples is
large.
Compression techniques may be used to improve
the signal-to-quantizing noise ratio for some
sampled sounds. These techniques reduce the
dynamic range of the sound samples stored in
the sample memory. The sample data is
decompressed during playback to restore the
dynamic range of the signal. This allows the use
of sample memory with a smaller word size
AN27REV3
MIDI and Music Synthesis Tutorial
(smaller dynamic range) than is utilized in the
rest of the . system. There are a number of
different compression techniques which may be
used to compress the dynamic range of a signal.
For signals which begin at a high amplitude and
decay in a fairly linear fashion, a simple
compression technique can be effective. If the
slope of the decay envelope of the signal is
estimated, then an envelope with the
complementary slope (the negative of the decay
slope) can be constructed and applied to the
original sample data. The resulting sample data,
which now has a flat envelope, can be stored in
the sample memory, utilizing the full dynamic
range of the memory. The decay envelope can
then be applied to the stored sample data during
sound playback to restore the envelope of the
original sound.
Note that there is some compression effect
inherent in the looping techniques described
earlier. If the loop segment is stored at an
amplitude level which makes full use of the
dynamic range available in the sample memory,
and the processor and D/A converters used for
playback have a wider dynamic range than the
sample memory, then the application of a decay
envelope during playback will have a
decompression effect similar to that described in
the previous paragraph.
Pitch Shifting
In order to mmmllze sample memory
requirements, wavetable synthesis systems utilize
pitch shifting, or pitch transposition techniques,
to generate a number of different notes from a
single sound sample of a given instrument. For
example, if the sample memory contains a
sample of a middle C note on the acoustic piano,
then this same sample data could be used to
generate the C# note or D note above middle C
using pitch shifting.
8-229
----------- ----------Pitch shifting is accomplished by accessing the
stored sample data at different rates during
playback. For example, if a pointer is used to
address the sample memory for a sound, and the
pointer is incremented by one after each access,
then the samples for this sound would be
accessed sequentially, resulting in some
particular pitch. If the pointer increment was two
rather than one, then only every second sample
would be played, and the resulting pitch would
be shifted up by one octave (the frequency
would be doubled).
Frequency Accuracy
In the previous example, the sample memory
address pointer was incremented by an integer
number of samples. This allows only a limited
set of pitch shifts. In a more general case, the
memory pointer would consist of an integer part
and a fractional part, and the increment value
could be a fractional number of samples. The
integer part of the address pointer is used to
address the sample memory, the fractional part is
used to maintain frequency accuracy.
For
example if the increment value was equivalent to
112, then the pitch would be shifted down by one
octave (the frequency would be halved). When
non-integer increment values are utilized, the
frequency resolution for playback is determined
by the number of bits used to represent the
fractional part of the address pointer and the
address increment parameter.
MIDI and Music Synthesis Tutorial
might simply ignore the fractional part of the
address when determining the sample value to be
sent to the DIA converter. The data values sent
to the D/A converter when using this approach
are indicated in the Figure 8, case I. A slightly
better approach would be to use the nearest
available sample value.
More sophisticated
systems would perform some type of
mathematical interpolation between available
data points in order to get a value to be used for
playback. Values which might be sent to the
DIA when interpolation is employed are shown
as case II. Note that the overall frequency
accuracy would be the same for both cases
indicated, but the output is severely distorted in
the case where interpolation is not used.
There are a number of different algorithms used
for interpolation between sample values. The
simplest is linear interpolation. With linear
interpolation, interpolated value is simply the
weighted average of the two nearest samples,
with the fractional address used as a weighting
constant. For example, if the address pointer
indicated an address of (n+K), where n is the
integer part of the address and K is the fractional
part, than the interpolated value can be
calculated as s(n+K) = (l-K)s(n) + (K)s(n+l),
where sen) is the sample data value at address n.
More sophisticated interpolation techniques can
can be utilized to further reduce distortion, but
these techniques are computationally expensive.
Oversampling
I nterpoiation
When the fractional part of the address pointer is
non-zero, then the "desired value" falls between
available data samples.
Figure 8 depicts a
simplified addressing scheme wherein the
Address Pointer and the increment parameter
each have a 4-bit integer part and a 4-bit
fractional part. In this case, the increment value
is equal to 1 1/2 samples. Very simple systems
8·230
Oversampling of the sound samples may also be
used to improve distortion in wavetable
synthesis systems.
For example, if 4X
oversampling were utilized for a particular
instrument sound sample, then an address
increment value of 4 would be used for playback
with no pitch shift. The data points chosen
during playback will be closer to the "desired
values", on the average, than they would be if no
oversampling were utilized because of the
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MIDI and Music Synthesis Tutorial
increased number of data points used to
represent the waveform.
Of course,
oversampling has a high cost in terms of sample
memory requirements.
interpolation and selective oversampling can
produce excellent results.
Splits
In many cases, the best approach may be to
utilize linear interpolation combined with
varying degrees of oversampling where needed.
The linear interpolation technique provides
reasonable accuracy for many sounds, without
the high penalty in terms of processing power
required for more sophisticated interpolation
methods. For those sounds which need better
accuracy, oversampling is employed. With this
approach, the additional memory required for
oversampling is only utilized where it is most
needed.
The combined effect of linear
When the pitch of a sampled sound is changed
during playback, the timbre of the sound is
changed somewhat also. For small changes in
pitch (up to a few semitones), the timbre change
is generally not noticed. However, if a large
pitch shift is used, the resulting note will sound
unnatural. Thus, a particular sample of an
instrument sound will be useful for recreating a
limited range of notes using pitch shifting
techniques.
To get coverage of the entire
instrument range, a number of different samples
of the instrument are used, and each of these
Address Increment Perameter
Integer Part Fractional Part
10,0,0,111,0,0,01
Address Pointer Initial Value
11
'O'O'OIO'O~~1
.
( ~ ";;as---;enlto DiA with fractlon;-ad~;tgn~ '\
1.
' - -'" - - - - - - - -----"
"
..
-
~
I
T
.
1
1
'"
'"
14
_ Sample Value
Stored In Memory
~ TIme
Integer Part Fractional Part 1000'---------'------'------'--------'--------'----1100
1001
1011
1101
1010
1,0,0,0
1,0,0,1
1,0,1,1
1,1,0,0
0,0,0,0
1,0,0,0
0,0,0,0
1,0,0,0
Address Pointer Value
During Playback
_II
'"
'"
0,0,0,0
1,0,0,0
0,0,0,0
1,0,0,0
III
Memory Address
(~ta~u~S~_~/~wh~~~9~~-;~)
r
Integer Part Fractional Part 1000
1,0,0,0
1,0,0,1
1,0,1,1
1,1,0,0
,.
'"
'. . ---1 I'" --
InterpOlated Value
"
!
1001 ... 1010
I
1011
'"
~,
,
1100 '"
Sample Value
Stored In Memory
,.
~
Time
1101
, Memory Address
Address Pointer Values
During Playback
Figure 8: Sample Memory Addressing and Interpolation
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MIDI and Music Synthesis Tutorial
samples is used to synthesize a limited range of
notes. This technique can be thought of as
splitting a musical instrument keyboard into a
number of ranges of notes, with a different
sound sample used for each range. Each of these
ranges is referred to as a split, or key split.
generally have more of a problem with aliasing
noise.
Low-pass filtering applied after
interpolation can help eliminate the undesirable
effect of aliasing noise.
The use of
oversampling also helps eliminate aliasing noise.
Velocity splits refer to the use of different
samples for different note velocities. Using
velocity splits, one sample might be utilized if a
particular note is played softly, where a different
sample would be utilized for the same note of
the same instrument when played with a higher
velocity.
LFOs for vibrato and tremolo
Note that the explanations above refer to the use
of key splits and velocity splits in the sound
synthesis process. In this case, the different
splits utilize different samples of the same
instrument sound. Key splitting and velocity
splitting techniques are also utilized in a
performance context.
In the performance
context, different splits generally produce
different instrument sounds. For instance, a
keyboard performer might want to set up a key
split which would play a fretless bass sound
from the lower octaves of his keyboard, while
the upper octaves play the vibraphone.
Similarly, a velocity split might be set up to play
the acoustic piano sound when keys are played
with soft to moderate velocity, but an orchestral
string sound plays when the keys are pressed
with higher velocity.
Aliasing Noise
The previous paragraph discussed the timbre
changes which result from pitch shifting. The
resampling techniques used to shift the pitch of a
stored sound sample can also result in the
introduction of aliasing noise into an instrument
sound. The generation of aliasing noise can also
limit the amount of pitch shifting which may be
effectively applied to a sound sample. Sounds
which are rich in upper harmonic content will
8-232
Vibrato and tremolo are effects which are often
produced by musicians playing acoustic
is
basically
a
instruments.
Vibrato
low-frequency modulation of the pitch of a note,
while tremolo is modulation of the amplitude of
the sound.
These effects are simulated in
synthesizers by implementing low-frequency
oscillators (LFOs) which are used to modulate
the pitch or amplitude of the synthesized sound
being produced. Natural vibrato and tremolo
effects tend to increase in strength as a note is
sustained. This is accomplished in synthesizers
by applying an envelope generator to the LFO.
For example, a flute sound might have a tremolo
effect which begins at some point after the note
has sounded, and the tremolo effect gradually
increases to some maximum level, where it
remains until the note stops sounding.
Layering
Layering refers to a technique in which multiple
sounds are utilized for each note played. This
technique can be used to generate very rich
sounds, and may also be useful for increasing
the number of instrument patches which can be
created from a limited sample set. Note that
layered sounds generally utilize more than one
voice of polyphony for each note played, and
thus the number of voices available is effectively
reduced when these sounds are being used.
AN27REV3
_.-_..--_._.
__.._-_
...-.
Polyphonic Digital
Enhancement
Filtering
MIDI and Music Synthesis Tutorial
for
Timbre
It was mentioned earlier that low-pass filtering
may be used to help eliminate noise which may
be generated during the pitch shifting process.
There are also a number of ways in which digital
filtering is used in the timbre generation process
to improve the resulting instrument sound. In
these
applications,
the
digital
filter
implementation is polyphonic, meaning that a
separate filter is implemented for each voice
being generated, and the filter implementation
should have dynamically adjustable cutoff
frequency and/or Q.
For many acoustic instruments, the character of
the tone which is produced changes dramatically
as a function of the amplitude level at which the
instrument is played. For example, the tone of
an acoustic piano may be very bright when the
instrument is played forcefully, but much more
mellow when it is played softly. Velocity splits,
which utilize different sample segments for
different note velocities, can be implemented to
simulate this phenomena.
Another very
powerful technique is to implement a digital
low-pass filter for each note with a cutoff
frequency which varies as a function of the note
velocity.
This polyphonic digital filter
dynamically adjusts the output frequency
spectrum of the synthesized sound as a function
of note velocity, allowing a very effective
recreation of the acoustic instrument timbre.
Another important application of polyphonic
digital filtering is in smoothing out the
transitions between samples in key-based splits.
At the border between two splits, there will be
two adjacent notes which are based on different
samples. Normally, one of these samples will
have been pitch shifted up to create the required
note, while the other will have been shifted
down in pitch. As a result, the timbre of these
two adjacent notes may be significantly
different, making the split obvious.
This
AN27REV3
problem may be alleviated by employing a
polyphonic digital filter which uses the note
number to control the filter characteristics. A
table may be constructed containing the filter
characteristics for each note number of a given
instrument. The filter characteristics are chosen
to compensate for the pitch shifting associated
with the key splits used for that instrument.
It is also common to control the characteristics
of the digital filter using an envelope generator
or an LFO. The result is an instrument timbre
which has a spectrum which changes as a
function of time. For example, It is often
desirable to generate a timbre which is very
bright at the onset, but which gradually becomes
more mellow as the note decays. This can easily
be done using a polyphonic digital filter which is
controlled by an envelope generator.
The PC to l\flDI Interface and the MPU-401
To use MIDI with a personal computer, a PC to
MIDI interface product is generally required
(there are a few personal computers which come
equipped with built-in MIDI interfaces). There
are a number of MIDI interface products for
PCs.
The most common types of MIDI
interfaces for IBM compatibles are add-in cards
which plug into an expansion slot on the PC bus,
but there are also serial port MIDI interfaces
(connects to a serial port on the PC) and parallel
port MIDI interfaces (connects to the PC printer
port). The fundamental function of a MIDI
interface for the PC is to convert parallel data
bytes from the PC data bus into the serial MIDI
data format and vice versa (a DART function).
However, "smart" MIDI interfaces may provide
a number of more sophisticated functions, such
as generation of MIDI timing data, MIDI data
buffering,
MIDI
message
filtering,
synchronization to external tape machines, and
more.
8-233
----------------------
MIDI and Music Synthesis Tutorial
The defactQ standard.JQr MIDI interface add-in
cards fQr the PC is the RQland MPU-401
interface.
The MPU-401 is a smart MIDI
interface, which alSQ SUPPQrts a dumb mQde .of
QperatiQn (.often referred tQ as "pass-thrQugh
mQde" .or "UART mQde"). There are a number
.of MPU-401 cQmpatible MIDI interfaces .on the
market. In additiQn, many add-in sQundcards
include built-in MIDI interfaces which
implement the UART mQde functiQns .of the
MPU-401.
Compatibility Considerations
Applications on the PC
for
MIDI
There are tWQ levels .of cQmpatibility which must
be cQnsidered fQr MIDI applicatiQns running .on
the PC.
First is the cQmpatibility .of the
applicatiQn with the MIDI interface being used.
The secQnd is the cQmpatibility .of the
applicatiQn with the MIDI synthesizer.
CQmpatibility cQnsideratiQns under DOS and the
MicrosQft WindQws .operating system are
discussed in the fQllQwing paragraphs.
sQund mQdules. PriQr tQ the General MIDI
standard, there was nQ widely accepted standard
patch set fQr synthesizers, SQ applicatiQns
generally needed tQ provide SUPPQrt fQr each .of
the mQst PQPular synthesizers at the time. If the
applicatiQn did nQt SUPPQrt th~ particular mQdel
.of synthesizer .or sQund mQdule that was attached
tQ the PC, then the sQunds produced by the
applicatiQn might nQt be the sQunds which were
intended.
MQdern applicatiQns can provide
SUPPQrt fQr a General MIDI (GM) synthesizer,
and any GM-cQmpatible sQund SQurce shQuld
produce the CQrrect sQunds. SQme .other mQdels
which are cQmmQnly supPQrted are the RQland
MT-32, the RQland LAPC-l, and the RQland
SQund Canvas. The RQland MT-32 was an
external MIDI SQund mQdule which utilized
RQland's Linear Additive (LA) synthesis, and
the MT-32 cQmbined with an MPU-401 interface
became a PQPular MIDI synthesis platfQrm fQr
the pc. The LAPC-1 was a PC add-in card
which cQmbined the MT-32 synthesis functiQn
with the MPU-401 MIDI interface. The SQund
Canvas is RQland's General Synthesizer (GS)
sQund mQdule, and this unit has becQme an
industry standard.
DOS Applkations
DOS
applicatiQns
which
utilize
MIDI
synthesizers include MIDI sequencing sQftware,
music scoring applicatiQns, and a variety .of
games. In terms .of MIDI interface cQmpatibility,
virtually all .of these applicatiQns SUPPQrt the
MPU-401 interface, and mQst utilize .only the
UART mQde. These applicatiQns shQuld wQrk
cQrrectly if the PC is equipped with a MPU-401,
a full-featured MPU-401 compatible, .or a sQund
cru:d with a MPU-401 UART-mQde capability.
Other MIDI interfaces, such as serial PQrt .or
parallel PQrt MIDI adapters, will .only wQrk if
the applicatiQn provides SUPPQrt fQr that
particular mQdel .of MIDI interface.
A particular applicatiQn may provide SUPPQrt fQr
a number .of different mQdels .of synthesizers .or
8-234
Mkrosojt Windows and the Multimedia PC
(MPC)
The number .of applicatiQns fQr high quality
audiQ functiQns .on the PC (including music
synthesis) grew explQsively after the intrQductiQn
.of MicrosQft WindQws 3.0 with Multimedia
ExtensiQns ("WindQws with Multimedia") in
1991. The Multimedia PC (MPC) specificatiQn,
.originally published by MicroSQft in 1991 and
nQW published by the Multimedia PC Marketing
CQuncil (a subsidiary .of the SQftware Publishers
AssQciatiQn), specifies minimum requirements
fQr multimedia-capable PersQnal CQmputers. A
system which meets these requirements. will be
able tQ take full advantage .of Windows with
Multimedia. NQte that many .of the functiQns
.originally included in the Multimedia ExtensiQns
AN27REV3
----------- ----------have been incorporated into the Windows 3.1
operating system.
The audio capabilities utilized by Windows 3.1
or Windows with Multimedia include audio
recording and playback (linear PCM sampling),
music synthesis, and audio mixing. In order to
support the required music synthesis functions,
MPC-compliant audio adapter cards must have
on-board music synthesizers.
The MPC specification defines two types of
synthesizers; a "Base Multitimbral Synthesizer",
and an "Extended Multitimbral Synthesizer".
Both the Base and the Extended synthesizer
must support the General MIDI patch set. The
difference between the Base and the Extended
synthesizer requirements is in the minimum
number of notes of polyphony, and the minimum
number of simultaneous timbres which can be
produced. Base Multitimbral Synthesizers must
be capable of playing 6 "melodic notes" and "2
percussive" notes simultaneously, using 3
"melodic timbres" and 2 "percussive timbres".
The formal requirements for an Extended
Multitimbral Synthesizer are only that it must
have capabilities which exceed those specified
for a Base Multitimbral Synthesizer. However,
the "goals" for an Extended synthesizer include
the ability to play 16 melodic notes and 8
percussive notes simultaneously, using 9 melodic
timbres and 8 percussive timbres.
The MPC specification also includes an
authoring standard for MIDI composition. This
standard requires that each MIDI file contain
two arrangements of the same song, one for
Base synthesizers and one for Extended
synthesizers.
The MIDI data for the Base
synthesizer arrangement is sent on MIDI
channels 13 - 16 (with the percussion track on
channel 16), and the Extended synthesizer
arrangement utilizes channels 1 - 10 (percussion
is on channel 10). This technique allows a single
MIDI file to play on either type of synthesizer.
AN27REV3
MIDI and Music Synthesis Tutorial
Windows
applications
generally
address
hardware devices such as MIDI interfaces or
synthesizers through the use of drivers. The
drivers provide applications software with a
common interface through which hardware may
be accessed, and this simplifies the hardware
compatibility issue. Before a synthesizer is
used, a suitable driver must be installed using
the Windows Driver applet within the Control
Panel. The device drivers supplied with
Windows 3.1 include a driver for the
MPU-401ILAPC-l MIDI interface, and a driver
for the original AdLib PM synthesizer card.
Most other MIDI interfaces andlor synthesizers
are shipped with their own Windows drivers.
When a MIDI interface or synthesizer is installed
in the PC and a suitable device driver has been
loaded, the Windows MIDI Mapper applet will
appear within the Control Panel. MIDI messages
are sent from an application to the MIDI
Mapper, which then routes the messages to the
appropriate device driver. The MIDI Mapper
may be set to perform some filtering or
translations of the MIDI messages in route from
the application to the driver. The processing to
be performed by the MlDr Mapper is defined in
the MIDI Mapper Setups, Patch Maps, and Key
Maps;
MIDI Mapper Setups are used to assign MIDI
channels to device drivers. For instance, If you
have an MPU-401 interface with a General
MIDI synthesizer and you also have a Creative
Labs Soundblaster card in your system, you
might wish to assign channels 13 to 16 to the Ad
Lib driver (which will drive the Base-level FM
synthesizer on the Soundblaster), and assign
channels 1 - 10 to the MPU-401 driver. In this
case, MPC compatible MIDI files will play on
both the General MIDI synthesizer and the FM
synthesizer at the same time. The General MIDI
synthesizer will play the· Extended arrangement
on MIDI channels I - 10, and the PM
synthesizer will play the Base arrangement on
channels 13-16. The MIDI Mapper Setups can
8-235
-
---------------------also be used to change the channel number of
MIDI messages. If you have MIDI flles which
were composed for a General MIDI instrument,
and you are playing them on a Base Multitimbral
Synthesizer, you would probably want to take
the MIDI percussion data coming from your
application on channel 10 and send this
information to the device driver on channel 16.
MIDI and Music Synthesis Tutorial
Some MIDI applications, such as MIDI
sequencer software packages, can be set to make
use of the MIDI Mapper, or to address the
device driver directly (bypassing the MIDI
Mapper). Other Windows applications always
utilize the MIDI Mapper.
Summary
The MIDI Mapper patch maps are used to
translate patch numbers when playing MPC or
General MIDI flles on synthesizers which do not
use the General MIDI patch numbers. Patch
maps can also be used to play MIDI flles which
were arranged for non-GM synthesizers on GM
synthesizers.
For
example,
the
Windows-supplied MT-32 patch map can be
used when playing GM-compatible .MID flles
on the Roland MT-32 sound module or LAPC-l
sound card.
The MIDI Mapper key maps perform a similar
function, translating the key numbers contained
in MIDI Note On and Note Off messages. This
capability
is
useful
for
translating
GM-compatible percussion parts for playback on
non-GM synthesizers or vice-versa.
The
Windows-supplied MT~32 key map changes the
key-to-drum sound assignments used for General
MIDI to those used by the MT-32 and LAPC-l.
8-236
The MIDI protocol provides an efficient format
for conveying musical performance data, and the
Standard MIDI Files specification ensures that
different applications can share time-stamped
MIDI data. The storage efficiency of the MIDI
flle format makes MIDI an attractive vehicle for
generation of sounds in multimedia applications,
computer games,
or high-end karaoke
equipment. The General MIDI system provides
a common set of capabilities and a common
patch map for high polyphony, multi-timbral
synthesizers.
General
MIDI-compatible
Synthesizers employing high quality wavetable
synthesis techniques provide an ideal MIDI
sound generation facility for multimedia
applications.
AN27REV3
----------- -----------
Knapp CD-Quality Audio Paper
DESIGN TECHNIQUES FOR CD-QUALITY AUDIO
IN MULTIMEDIA COMPUTER SYSTEMS
Ron Knapp
Applications Engineer
Crystal Semiconductor
50 Airport Parkway
San Jose, CA 95110 (PC-059)
Background
With the advent of new data conversion architectures, particularly "delta-sigma", or "1-bit
DAC" technology, it is now possible to integrate
high resolution analog-to-digital (AID) and digital-to- analog (O/A) converters into VLSI digital
integrated circuits (IC's). The result has been
many IC's recently introduced which allow CDquality audio record and playback capability to
be added to personal computers (PC's) and
workstations with as little as one IC (Fig. 1). Already the PC market has seen a wide variety of
sound cards which plug into the computer bus,
but the high level of integration which reduces
the number of components, and therefore the
space required, can now allow computer designers to integrate the audio function into the
computer motherboard. This, together with low
cost below a critical threshold, is radically
changing the whole computer market with a
frenzy of multimedia activity which will change
the way we use and communicate with computers forever. PC deSigners, who are under
intense pressure to respond to these demands,
need to be able to quickly and easily design
these audio IC's into their add-on boards or
motherboards. With nearly all the analog circuits
contained in a comprehensive, mixed-signal IC
which includes all the digital interface and control functions, the design job, which previously
would be reserved for only experienced analog
engineers, can now be done by computer designers with little analog experience.
Presented at Silicon Valley Personal Computer
Design Conference July 1993
However, to achieve CD-quality audio, the
physical layout and interconnects of the analog
section are extremely critical. The harsh environment of the computer system contains high
frequency digital signals which can interfere with
the audio in many ways. There are a number of
analog design rules and circuit techniques which
will result in multimedia designs that work first
time with full data sheet performance.
Ground Planes
The most fundamental rule in audio designs is
the use of separate analog and digital ground
planes (Fig. 2). All the analog components and
associated circuits should be placed exclusively
over the analog ground plane while the digital
components and pc board traces should be restricted exclusively to the digital ground plane.
In computer systems, there are high speed digital signals with fast edges that will couple onto
the ground plane. Ground planes provide a convenient way of distributing a low impedance, low
inductance ground reference over a wide area,
but they should not be considered incorruptible.
The impedance may be very close to zero at dc,
but may increase significantly at high frequency.
Fast edges of high speed logic contain high frequency components that may be much higher
than the fundamental data or clock frequency. If
the digital traces were to run over the analog
ground plane, capacitive coupling occurs. It is
easy to calculate just how much by taking the
area, A, of the trace and the thickness, d, of the
layers separating the two. Obtaining the dielectric constant, e, of the pc board material from
8-237
-
--------.. -----------,."
the manufacturer, one can calculate the capacitance by C=Ae/d. Notice that the capacitance is
inversely proportional the thickness, so that if a
situation makes this unavoidable, the coupling
can be minimized by placing as many layers as
possible between the trace and the. ground
plane.
An equivalent argument applies to analog traces
which extend over the digital ground plane. Anyone who has measured the quality of the
ground plane in a computer with an oscilloscope
knows that there is a great deal of noise. This is
why the ground clip on the probe must be very
close to the component being measuring to get
a clean waveform. PC chips sets in a computer
can dump a lot of high speed, high current transients into ground that modulate the ground
plane voltage. This "signal" can couple onto the
traces which are over the ground plane. Keep in
mind that "CD quality" requires a signal-to-noise
ratio (SIN) of BOdB, or one part in 10,000. With
1Vrms audio signals, or 2.BVp-p, the noise floor
level is around 2BOuV. It doesn't take very much
coupling to transfer tens of millivolts of signal
from the digital ground plane onto the sensitive
analog traces. One of the worst things to do is
to overlap the analog and digital ground planes
because the· intersecting area could be large,
creating significant capacitance.
Power Planes
For similar reasons, power planes should be
used with care. They are not always necessary,
since in analog design it is often good practice
to provide separate power supply traces from
the regulator or power supply to each of the
critical analog components, rather than "daisychain" the supply or make a power grid. If there
is any ripple or high frequency glitches from
transient currents, power planes can easily couple this into the analog traces. If used, never
bridge the split between the analog and digital
ground planes. Keep the analog supply plane
entirely under (over) the analog ground plane.
Power planes can even add crosstalk and inter8-238
Knapp CD-Quality Audio Paper
action within the analog section. The power
plane forms a commOn capacitor plate between
two analog traces. While this occurs on the
ground planes as well, ground is much lower impedance than the power, which often comes
from an IC regulator. Since the analog components usually have a high degree of power
supply rejection built in, it is sufficient to simply
provide wide traces to each of the analog supply pins, and let the bypass capacitors do their
job.
Ground Plane Connections
If there were no ground planes, all the ground
connections would be returned to one single
"star ground" pOint, normally at the power supply, voltage regulator, or the power connector
(Fig. 2). Using ground planes, there should be
only one connec~ion between the analog and
digital planes, at this star point to avoid any
ground loops. There are sometimes exceptions
to this rule. If you have control over the whole
system, it may be possible to provide separate
analog and digital power supply and ground
wires from each board to the power supply. The
star ground point in this case is the power supply. Because there are many variables in analog
circuit design which cannot be anticipated or
calculated, having several options for ground
connections is the safest thing to do. It is advisable to have a few jumper options at different
places to connect the analog and digital ground
planes, either at the power connector, voltage
regulator, close to the data converter, or none,
allowing separate wires back to the power supply. In through hole boards, add plated through
via holes attached to each plane directly across
the separation between the planes. Later, the
jumper wire can be eliminated by a metal layer
change to short the two. Adding additional
drilled holes is usually a costly change. On surface mount boards, plan for zero ohm resistors
at each option point. This component can be replaced with a short on a subsequent layer
revision. This sort of empirical design is normal
for high accuracy analog design, usually done
Presented at Silicon Valley Personal Computer
Design Conference July 1993
.-_
._.-.
_
..--__.._-_
...
with breadboard experiments. lime to market,
cost, and complexity of computer design, especially motherboards, does not allow
breadboards. Going directly to Rev.O product
means that any breadboarding must be done
with manufacturing options.
Knapp CD-Quality Audio Paper
well to reduce digital interference transmitted
into the analog section.
Ground Plane Shields
There are most likely very high transient currents at high frequency on the digital ground
plane. Even though the ground plane is low impedance, significant IR voltage drops can occur.
These transient voltages can couple across the
isolation barrier to the analog ground plane. The
analog ground plane may have very low DC impedance, but it may not be nearly as good at
high frequencies, making it susceptible to coupling from the adjacent digital ground plane.
With both ground planes on the same layer, the
cross sectional area is small because the metal
layers are thin, but the total area significantly
adds up over the long length of peripheral distance across the board. For this reason, provide
a generous separation between the analog and
digital ground planes. If possible, 1/8" is recommended (Fig. 2), but at least 1/16" is required.
For a good analog deSign, two layers is adequate for ground plane and traces. Additional
layers can add more variables to an already
complex situation. However, for high density,
most computer designs require multilayer pc
boards with 4-8 layers in add-on cards, and 816 layers in the case of motherboards. There is
no particular advantage to multilayer analog designs other than it may be desirable to have
more than one ground plane, and to shield the
analog traces on the inner layers between
ground planes on each surface. This may be especially important for plug-in cards, where an
analog audio card could be plugged into a slot
adjacent to a card containing graphics, video,
disk controller, or other high speed digital circuits that can radiate interference into the
sensitive analog circuit. There is not much that
can be done to protect the components and exposed pins, but at least the analog traces can
be protected by sandwiching them between
ground planes.
Ground Plane Fill
Location on the Board
Most of the interference on the PC board comes
from the digital section into the analog section
laterally across the board. Experimental data
has shown that adding a ground plane fill in the
analog section helps to form a guard around the
sensitive analog traces and can reduce coupling
from digital to analog by as much as 30dB.
Rather than leave the area between the traces
empty, fill in these spaces, as much as the design rules will allow, with solid pieces of metal,
connected to the main ground plane with vias
(Fig. 3). Avoid any unconnected, floating pieces
of fill, which can enhance the coupling mechanism, worse than not having any fill at all.
In most CMOS analog IC's, both positive and
negative power supplies are required to obtain
the most operating voltage range and highest
signal to noise (SIN) ratio. It is normal to find
the substrate connected to the most positive
power supply. In these IC's, strict adherence to
good analog to digital isolation demands that
the split between analog and digital ground
planes run directly under the. data conversion
IC's between the groups of digital and analog
pins.
Ground Plane Split
Although not always possible, ground plane fill
is recommended between the digital traces as
Presented at Silicon Valley Personal Computer
Design Conference July 1993
In computer systems, negative supply voltages
are usually not available on the bus. Rather
than require an extra negative supply or a DCDC converter, multimedia analog components
have been designed to work on a single positive
8-239
-
--- _....--------_------power supply, normally +5V. The negative power
input, therefore, is ground. These analog IC's for
single supply systems are designed with the
substrate connection to ground, with analog and
digital grounds internally connected to the substrate. Although there are both analog and
digital ground pins, both must be connected to
the analog ground plane for best results. Also,
bypass capacitor return current must be referenced to the analog ground as well. As such, it
is better to place the whole IC over a single,
analog ground plane, even though some of the
basic design rules are violated.
Place the IC as close to. the digital ground split
as possible to minimize the distance the digital
traces must cross the analog ground plane (Fig.
2). Rotate the IC so that the digital pins face the
digital ground plane and the analog pins face
away, toward the analog I/O connectors. For
IC's that have an integrated ISA bus interface,
the bus drivers may have significant current capability, up to 24mA. These buffers have
separate ground returns and separate power
supply connections to isolate these high transients which are most likely asynchronous to the
sample rate of the A/D and D/A converters
within the IC. In this case, extend the digital
ground plane partially under the IC, only enough
to separate the analog ground plane from the
bus data, control, and supply pins (Fig. 4).
For PC plug-in cards (Fig. 2), the normal I/O
connectors for audio LINE IN, LINE OUT, and
MIC IN are on a bracket mounted on the rear of
the card sliding into the rear of the chassis. This
dictates that the analog section for the audio
should be at the rear of the card to minimize the
analog connections. For motherboards, the best
place for the analog section is to reserve a corner of the board at the rear to allow the audio
I/O connectors mounted on the board to align
with holes in the rear panel (Fig. 5). Avoid placing the analog in the middle of the board with
digital surrounding it. Also avoid long buses, like
SCSI, or ISA bus from running adjacent to the
analog ground plane. It· this is unavoidable, at
8-240
Knapp CD-Quality Audio Paper
least separate the bus and analog ground plane
with a piece of digital ground plane as a guard.
Power Supply Bypassing
Adequate bypass capacitors between the power
supply pins and appropriate ground are mandatory. It is critical to connect these capacitors as
close to the pins of the IC as possible. The efficiency of the capacitor will be lost if there is too
much resistance or inductance in series with it.
Usually two capacitors are recommended for
each supply pin, a small 0.01 uF-0.1 uF ceramic
capacitor together with a 1uF-1 OuF tantalum capacitor. Because the small capacitor handles the
high frequency transients, it needs to be the
closer of the two, while the larger one can afford
to be further away. On surface mount boards
(Fig. 6), the capacitors should be on the component side so that a direct connection can be
made to the pins of the IC without going through
vias, which add impedance to the connection. A
simple test can be performed to see if the capacitor connection can be improved by soldering
the small capacitors directly to the IC pins. If the
performance changes, most likely the capacitors
connections are not optimum.
Power Supplies
The are at least two separate power supplies
required for multimedia audio IC's, analog and
digital. There are several options to generate
each +5V input. The safest and preferred
method is to use a higher voltage, such as
+ 12V, which sometimes is available on the bus,
to generate a quiet, clean, +5V analog voltage
using a linear, three terminal IC regulator for the
+5V analog supply. Use this output through a
small resistor and filter capacitors for the digital
supply (Fig. 7a). Even though the digital input is
for the digital circuits, it is on a sensitive analog
IC. Excessive noise not filtered by the bypass
capacitors could couple through the substrate
into the analog part of the IC. By deriving the
digital from analog supply, a relatively low noise
digital supply is assured. Any transient current
Presented at Silicon Valley Personal Computer
Design Conference July 1993
----------------------
Kflapp CD-Quality Audio Paper
which feeds back into the analog supply is synchronous to the AID, and will not be a problem.
is important to keep all dynamic signals, both
analog and digital, away from this pin.
The second option is to use a regulator for the
analog supply as above, but use the main digital
supply from the computer for the IC digital input
(Fig. 7b). There is a risk that noise could degrade performance, but a much smaller
regulator can be used since the analog supply
is usually only a fraction of the digital supply. In
this case, do not install a resistor between the
analog and digital supply pins, but include a
ferrite bead in series with the digital supply. Ferrite bead selection is made more by size and
current capability than by value. Although impedance vs. frequency curves are given, the
choice is somewhat empirical, by trying different
ones. Most manufacturers offer a kit with many
sizes and types to find the most effective one.
Minimum Analog Trace Length
A third option is to use the computer supply for
everything, with no regulator. In this case, connect the +5V from the bus through a ferrite bead
first to the digital supply pin with associated bypass capacitors, then connect this pin through a
small resistor to the analog pin and its bypass
capacitors, which form an extra filter (Fig. 7c).
Some IC's have a second digital supply for the
interface logic, which can have high current buffers that switch asynchronously to the AID and
D/A operation, causing excessive interference.
Isolate this from the other power pins by connecting it directly to the +5V on the bus, with a
ferrite bead between it and the other digital supply pins on the IC (Fig. 7d).
Voltage Reference
The voltage reference output is often the most
sensitive analog pin on an AID. External bypass
capacitors are necessary to make sure this voltage is stable. It is critical to position these
capacitors as close to the pins as possible,
again the smaller value closer to the chip. Any
high frequency Signals or noise injected into this
pin can either produce tones in the audible
range or elevate the entire noise floor, or both. It
Presented at Silicon Valley Personal Computer
Design Conference July 1993
The pc board trace lengths connecting the analog inputs from the card-edge connectors,
through any input amplifiers, to the analog input
on the IC, should be made as short and direct
as possible. Rotate the input amplifiers in 90 degree increments to the best orientation to
accomplish this. Pay special attention to keep
high impedance lengths as short as possible,
like the summing junction of op amps. Low impedance output sources are less susceptible to
noise and coupling.
Distortion Effects
Avoid non-inverting amplifier configurations. All
op amps have circuits on the input that attempt
to maintain the offset voltage and offset current
constant over the specified input voltage range.
However, the residual common mode rejection
ratio (CMRR) is not perfect, and can contribute
a significant signal dependent error. This nonlinearity results in distortion in high quality audio
circuits. Sometimes non-inverting amplifiers are
necessary when driving from a high impedance
source, like a resistor divider. If possible always
use inverting amplifier configurations where the
summing junction of the input is held at a virtual
ground. In this case the CMRR is not a factor,
or a second order effect at most.
Use only metal film resistors in the analog signal
path. Carbon resistors can add noise and distortion from voltage coefficient effects. Use only
NPO (COG) dielectric ceramic capacitors in the
analog signal path as well. Capacitors made
with Z5U or X7R material can have a high degree of dielectric absorption, causing
non-linearity and distortion.
8-241
-
.._-_
_.-_..--_._.
__
...-.
Aliasing
In order to correctly digitize an audio signal, the
AID must sample at least twice the highest signal frequency. This minimum requirement is
called the Nyquist rate, with the sample rate .frequency, Fs, equal to or above twice the
maximum frequency in the input bandwidth, Fb.
Any signal which is. higher than Fb and within a
window of Fs plus or minus Fb will be translated
to a lower frequency equal to the absolute difference from Fs. In an audio example, it is
common to sample at the same rate used in CD
players, Fs=44.1 kHz. This is slightly more than
adequate to meet the Nyquist criteria for the
audio bandwidth with Fb=20kHz. An AID operating at the minimum Nyquist rate is said to have
no oversampling. In this case, any noise that
may be at 45.1 kHz, a 1kHz difference, will appear as a 1kHz tone. This repeats at all the
multiples of the sample rate as well, in this example at 88.2kHz, 132.3kHz, 176.4kHz, etc., all
with windows of susceptibility of 20kHz above
and below each one.
Delta-sigma converters make the AID much less
susceptible to noise because they take advantage of very high oversampling rates, much
higher than the Nyquist minimum. It is common
for the AID's in multimedia IC's to operate at
64x oversampling ratio. Using the example
above, with Fb=20kHz, the input audio signal is
actually sampled at 64xFs, or about 2.8MHz.
Digital filters inside the AID process all these
samples to produce an output word rate (OWR)
equal to the Nyquist rate, or 44.1 kHz. The digital
filters also have sharp cutoff characteristics just
above Fb, attenuating everything up to Fb below
the 64xFs frequency. Delta-sigma AID's can reject any noise or interference over this wide
band. However, there are narrow windows of
susceptibility at all the multiples of the oversampiing rate, 20kHz above and below each one.
Only noise around 2.8MHz, 5.6MHz, 8.4MHz,
11.2MHz, etc., can alias down to the audio
range. This can be a problem in computer systems, because it is unavoidable to have
frequencies, or harmonics of these frequencies,
8-242
Knapp CD-Quality Audio Paper
in this range. Proper layout and bypassing can
minimize aliased noise which could couple
through the power supply pins and voltage reference.
High frequency energy within the oversampling
windows that may be present on the analog
audio input must be filtered with an external
anti-alias filter. With no oversampling, a high-order active .filter with sharp cutoff characteristics
in necessary. Using a delta-sigma converter with
a high oversampling rate, this anti-alias filter requirement is greatly reduced. In the above
example, with 20kHz bandWidth, Fb, and 64x
oversampling ratio, a filter with "3dB bandwidth
just above Fb can roll off gradually (Fig. 8). The
attenuation at the first oversampling window
must be below the noise floor of the converter.
With 64x oversampling, a simple, single pole,
RC passive filter is sufficient to attenuate any
high frequencies on the input to less than -80dB
at a frequency of (64xFs)-Fb, or
(64x44.1 kHz)-20kHz =
2.8224MHz-20kHz =
2.8024MHz.
Aliasing can be avoided by synchronizing all the
digital systems to the AID sample rate, If there
is coupling at exactly 64xFs, it will alias to a frequency of zero, becoming a DC offset, which
can be compensated for electrically, by software, or using autocalibration if available by the
AID. The problem with computer systems is that
synchronization of the different parts of the PC
is not possible. The graphics and video, the disk
controller, the CPU, the communications ports,
all need to have particular frequencies of operation. Other than avoiding these oversampling
windows, separation and shielding are the best
means to minimize interference.
Summary
By following the layout and design techniques
described above, CD- quality audio can be designed into personal computers and
workstations for multimedia applications. As outPresented at Silicon Valley Personal Computer
Design Conference July 1993
_.-_..---.-.
__.._-_
...-.
lined in the checklist below, proper grounding,
bypassing, and isolation of digital and analog
circuits are critical. Experience has shown that
strict adherence to these rules will result in a
high rate of success of audio systems with low
noise and free of digital interference.
Knapp CD-Quality Audio Paper
Acknowledgments
The author would like to thank Steve Harris, Applications Manager at Crystal Semiconductor, for
his valuable contribution to this paper and for
preparing most of the figures.
Layout and Design Rules:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Split analog and digital ground planes.
Separation between ground planes 1/8".
Analog signals only over analog ground plane.
Digital signals only over digital ground plane.
Analog and digital ground planes linked on
only one place.
Use of ground plane fill.
Ground plane shields.
Locate analog section away from high speed
digital circuits.
Position bypass capacitors as close as possible to supply and voltage reference pins.
Mount surface mount bypass capacitors on
component side, with direct connection to
pins.
Place smallest bypass capacitor closest to
IC pin.
Separate linear regulator recommended for
analog supply with
digital supply derived from analog supply.
Minimum trace length for analog inputs and
outputs.
Use inverting amplifier configuration.
Use metal film resistors and NPO capacitors
in analog signal path.
Synchronize AID and DIA converters to digital circuit clock frequencies.
Presented at Silicon Valley Personal Computer
Design Conference July 1993
8-243
--------,.,--.. --------VDl
VD2
Knapp CD-Quality Audio Paper
VD3
VD4
VREF
VREFI
LFILT RFILT
VAl VA2
LMIC
RMIC
D<7:0>
A<1:0>
~==;::+==~ RLiNE
LUNE
io--
Unear
FIFO
16 Semples
IRQ
DBDIR
DBEN
~-law
A-law
ADPCM
io-1-++--~ LAUXl
H+++--~.RAUXl
CS
AD
WR
Parallel
Bus
Interface
PDRQ
CDRQ
:H-+---~ LOUT
Linear
PDAK
FIFO
16 Sample.
CDAK
~-Iaw
MOUT
A-law
ADPCM
:J-+-t-+--<>-------~
XCTL1
ROUT
XCTLO
~~~~-~LAU~
PDWN
RAU~
DGNDl
DGND2
DGND3I4I718
XTALll
XTAL10
XTAl21
XTAl20
MIN
AGNDl
AGND2
Figure 1. Parallel interface multimedia
audio subsystem IC.
~1/8"
11
Digital
Ground
Plane
Pins
Ground
Connection
"Anij~ij;'~
+5V
GroUnd'; .
Ferrite
Bead
Plllrf~: '.
~I
CPU & Digital
logic
Codec
digital
signals
Codec
analog signals
&
Components
Figure 2. Isolated digital and analog
traces over separate ground planes.
8-244
Presented at Silicon Valley Personal Computer
Design Conference July 1993
-_-----.._-_.
------_
..-
__.
Knapp CD-Quality Audio.Paper
•••••
•••••
•••••
•••••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
Figure 3. Example of ground plane fill.
Traces are surrounded by ground plane
(dark area), except for high density digital
lines in the center.
Presented at Silicon Valley Personal Computer
Design Conference July 1993
8-245
-_ _-_.
.. ..------_
---_
..-
Knapp CD-Quality Audio Paper
--------------~I
I
0000000 OOOOOOOO~,
I
I
I
1 1 ' 3 .
'3.
: VA
BUS VD
'-- -
-
Q
..
g Q
0.1
0.1 "F
VD
f1F
VD
Figure 4. Analog ground plane under entire IC, except
for digital ground plane along 13 bus interface pins
Audio Sub-system
Keyboard
Mouse
Serial Port'
Microphone
Line Out
Linelri
Video
Figure 5.· Multimedia audio IC mounted on motherboard.
8-246
Presented at Silicon Valley Personal Computer
Design Conference July 1993
---------- .. _----------
Knapp CD-Quality Audio Paper
00000000000
DigitaI
Supply
C• •1
00000000000
Figure 6. Surface mount bypass capacitors connect
directly to the 44PLCC pins on the componenet side
of board. The smaller value is closer to the IC pin.
+5V
Analog
a.
b.
+5V
Supply
C.
+5V
Supply
d.
+5V Analog (preferred)
If a separate +5V analog
supply Is available, attach here
and remove the 2.00 resistor
+5V
Analog
>,
Ferrlte_BE!ad
2.00
""V0--.__-....-" 000 \,.....----_--<
36
35
-
0.1 ~F
0.1 ~F
19
15
VA2 VA1 VD4
VD3
0.1 ~F 1 ~F 0.1 ~F
VD1
+5V
Supply
VD2
Figure 7. a) Digital +5V derived from analog +5V, b) separate digital
and analog supplies, c) analog +5V derived from digital +5V, and
d) separate digital supply for interface (pins 1, 7) and audio logic
and control supply (pins 15, 19,24,25, and 54).
Presented at Silicon Valley Personal Computer
Design Conference July 1993
8-247
_-_
........_.-.
-.-_
..-_
__
dB
Knapp CD-Quality Audio Paper
Input
spectrum
/
I
/
Easy
Anti-alias
I '~~~~~~:e,
=--
---- -------
H'Ig h Samp I'ng
1
Frequency
---- ------- ----
fb __ Large Separation
---.. fs-fb
between fb and (fs-fb)
Frequency
fs
Figure 8. In delta-sigma AID's, digital filters reject frequencies
between Fb and Fs-Fb. A simple anti-alias filter is also needed
on the input to make sure there is no energy above Fs-Fb.
8-248
Presented at Silicon Valley Personal Computer
Design Conference July 1993
.-_
_
..--_._.
__.._-_
...-.
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
9
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
9-1
-. ..--_._.
...~- • •~~IIIIIII.
~~
DATA ACQUISITION PRODUCTS
INTRODUCTION
Using SMART Analog technology, Crystal Semiconductor has created a family of CMOS NO Converters which feature patented on-chip, self-calibrating architectures to. maintain accuracy and linearity over
their full temperature range and device lifetime. Each of our NO Converters features an on-chip sample
and hold, and is manufactured in low-power CMOS. Most devices include a power-down sleep mode.
CS5012A, CS5014, CS5016 SAR Family
CS5102A 16-bit 20 kHz Low Power ADC
The CS5012A, CS5014 and CS5016 converters
have 12, 14 & 16 bits of resolution respectively,
with conversion times of 7 Ils to 16 Ils. The converters are tested for static and dynamic performance, at full rated conversion speed. On-chip selfcalibration ensures that linearity, offset and fullscale errors remain with specification, with no·
missing codes. Specifications are maintained over
the full temperature range.
The CS5102A is a low power version of the
CS5101A. Requiring only 44 mW from ±5 V supplies, along with aimW poWer down mode, the
CS5102A is ideal for battery powered applications.
CS5030, CS5031 12-bit 500kHz ADCs
The CS5030 family features an on-chip reference
which is very stable over temperature. This yields
a 12-bit ADC which has a total unadjusted error(including reference error) of <± 0.5 LSB over
the military temperature range.
CS5101A, CS5126 16-bit 100 kHz ADC
The CS5101A is a 16-bit ADC capable of converting in 8 Ils, yielding sample rates of 100 kHz.
A 2-channel analog input mux is included. Output
data is available serially, with 4 interface modes.
An on-chip crystal oscillator is provided, along
with a power-down control. The CS5126 is a lowcost version of the CS5101A, intended for audio
signal processing applications.
.
9-2
CS5412 12-bit, 1 MHz ADC
Using a 2-step flash approach, the CS5412
achieves 12-bit performance at 1 MHz sample
rate. Self calibration insures accuracy over time
and the military temperature range. Available in
both DIP and J-lead LCC packages, with on-chip
S/H, the IC offers a very compact ADC solution.
CS5501, CS5503 16/20-bit DC Measurement
ADC
The CS5501 and CS5503 feature an on-chip, 6pole, low-pass ·filter, with adjustable comer frequencies from 0.1 Hz to 10 Hz. The ADC's
achieve linearity errors of 0.0007%, with no missing codes. A highly flexible serial interface, along
with 25 mW power consumption, all in a 20 pin
package, make the parts ideal for weigh scale and
process control applications. The CS5503 is the
20-bit versIon of the CS5501, offering increased
dynamic range, often removing the need for external gain scaling.
----------- -----------
DATA ACQUISITION PRODUCTS
CS5504/5/6nt8/9 1,2 & 4-channel, 16/20-bit
DC Measurement ADC
CS5516,CS5520 16/20-bit Bridge Transducer
ADC
Very low power consumption of 1.5 mW, along
with an optional 2 or 4-channel input mux, make
this part ideal for process control and hand held
meter applications. These ADC's are available in
16 or 20 bit versions, with single channel, 2 channel or 4 channel inputs, and DIP or surface mount
packages.
The CS5516 and CS5520 are complete solutions
for digitizing low level signals from strain gauges,
load cells and pressure transducers. Any family of
mV output transducers, including those needing
bridge excitation, can be directly interfaced to the
CS5516 or CS5520. The devices offer an on-chip
software programmable instrumentation amplifier,
choice of AC or DC bridge excitation, software
selectable reference and signal demodulation.
CS5317
CS532617
CS532819
CS533617
CS533819
GP
Modem
Seismic
Audio
Audio
Audio
16
16
24
16118
16
18120
GP Fast
12
16120
16120
16120
50
2
22kHz
1.25
1 MHz
1
4 MHz
4
1
10Hz
60/100Hz
1/214
60Hz
1
.01 %
.0007 %
10Hz
.0015%
.0007%
CS5030
CS5031
CS5101A
CS5102A
CS5126
GP
GP
12114/16
7114116
100/56150
12
2
500
1
Specifications
Application
Resolution (bits)
Conversion Time (us)
Throughput (kHz)
Number of Inputs
1
Input Bandwidth
Integral Non-Linearity .0061.0021.001 % .25LSB
Differential (± LSB)
0.2510.251NMC
0.5
Dvnamic Ranoe dB
Power Needed mWl
Conversion Method
8140
100/20
2
20
1
1
50
2
50
2
10kHz
500 Hz
22120 kHz
22kHz
.0015%
CS5516
CS5520
12Hz
NMC
NMC
NMC
NMC
NMC
NMC
0.9
0.1251NMC
0.125
0.5
16
16
20
16118
16
18120
12
16120
16118
16120
.0081.003/.001
-80 dB
.001
.007
.0003
.0015
.0015
.0015
.02
92
87
1051110
70
120
150
Delta
Sigma
951100'
4501400
90
100/325
1051110
De~a
25
Delta
Si rna
3
Delta
Sigma
70
750
2-Step
Flash
De~a
Sigma
30
Delta
Sigma
j
j
j
j
j
J
J
.;
73/83/92
72
92
80
73/83/92
150
Succ.
Approx.
72
50
92
280/44
Suee.
Suee.
Aoorox.
Approx.
84
220
Delta
Sigma
.;
.;
~~d~~rdSample
j
j
j
j
j
j
j
j
j
j
j
j
j
j
j
j
J
j
J
Temperature Range
Com
Ind
Mil
Com
Ind
Mil
Com
Ind
Mil
Com
Ind
Mil
Com
Ind
28
PLCC
.;
.;
j
-"-
Com
Ind
Mil
Ind
Mil
Ind
Mil
j
24
28
18
DIP
SOIC
DIP
PLCC
LCC
DIP
SOIC
• CS5328 In Mono Mode
.;
j
.;
.;
NMC-No MISSing Codes
Sigma
j
Staticali Tested
Dynamicali Tested
40
DIP
PLCC
LCC
.;
550
Delta
Sigma
j
.;
j
On-Chip V. Ref
On-Chip Filtering
Packages
CS5412
CS5501
CS5503
12
Power Down Mode
Number of Pins (DIP)
CS5345 CS5389
CS5349 CS5390
12114/16
Non~Linearity
No Missing Codes
Total Harmonic
Distortion (%)
Signal-to-Noise
plus Distortion (dB)
CS5504
CS5505
CS5506
CS5507
CS5508
CS5509
DC Measurement
CS5321
CS5322
CS5323
CS5324
CS5012A
CS5014
CS5016
Com
Ind
Mil
Com
Ind
Mil
Com
Ind
Com
28
28
2B
40
20
20/24
24
DIP
SOIC
DIP
SOIC
DIP
DIP
JLCC
DIP
SOIC
DIP
SOIC
DIP
SOIC
GP=General Purpose
9-3
,.
.. ...
. ..--_
.....
~-
.."
-
~~-
~~
CS5321, CS5322, CS5323, CS5324, 24-bit Variable Band width ADC
The CS5323 or CS5321 modulator, combined
with the CS5322 digital filter, offers> 120 dB dynamic range in the DC to 1500 Hz frequency
band. Seven different filter comer frequencies and
output update rates are offered, allowing the ADC
to be optimized for different types of seismic
measurements. The CS5324 includes a modulator
and the fIrst stage of digital filtering, allowing users to implement their own [mal filter stage.
DATA ACQUISITION PRODUCTS
CS531716-bit Voice Band ADC
The CS5317 is well suited for a wide range of
voiceband applications, from speech recognition to
passive sonar. An on-chip PLUClock generator
makes the part perfect for high-performance modems. The device features a 20 kHz word rate, a
10 kHz band width, 84 dB dynamic range and
80 dB THD.
CS5336 Audio Bandwidth ADC's
Selected members of our audio ADC family are
now available in industrial or military versions
(See the Digital Audio AID Converter Section).
For complete data sheets on the products in this
chapter, see the Crystal Semiconductor Data Acquisition data book, or contact Crystal.
CONTENTS
CS5012A14/6 16, 14, & 12-Bit, Self-Calibrating AID Converters
CS5030/l 12-Bit, 500 kHz, Sampling AID Converters .
CS5101A12A 16-Bit, 100 kHzl20 kHz AID Converters .
CS5126 16-Bit, Stereo AID Converter for Digital Audio
CS5317 16-Bit, 20 kHz Oversampling AID Converter
CS5321 High Dynamic Range Delta-Sigma Modulator
CS5322/3 24-Bit Variable Bandwidth AID Converter
CS5324 120 dB, 500 Hz Oversampling AID Converter
CS5412 12-Bit, IMHz Self-Calibrating AID Converter
CS550113 Low-Cost, 16 & 20-Bit Measurement AID Converter
CS5504 Low Power, 20-Bit AID Converter .
CS5505/6/7/8 Very Lo,w Power, 16-Bit and 20-Bit AID Converters
CS5509 Single Supply, 16-Bit AID Converter
CS5516/20 16-Bitl20-Bit Bridge Transducer AID Converters
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
... ...
••""IIIIII.
~"
~-.~.
~~
~
Semiconductor Corporation
~
CS5016 CS5014 CS5012A
16, 14 & 12-8it, Self-Calibrating AID Converters
Features
General Description
The CS5012A114/16 are 12, 14 and 16-bit monolithic
analog to digital converters with conversion times of
7.2I1S, 14.2511S and 16.25I1S. Unique self-calibration circuitry insures excellent linearity and differential nonlinearity, with no missing codes. Offset and full scale
errors are kept within 1/2 LSB (CS5012A114) and
1 LSB (CS5016), eliminating the need for calibration.
Unipolar and bipolar input ranges are digitally selectable.
• Monolithic CMOS AID Converters
Microprocessor Compatible
Parallel and Serial Output
Inherent Track/Hold Input
• True 12, 14 and 16-Bit Precision
The pin compatible CS5012A114/16 consist of a DAC,
conversion and calibration microcontroller, oscillator,
comparator, microprocessor compatible 3-state I/O,
and calibration circuitry. The input track-and-hold, inherent to the devices' sampling architecture, acquires
the input signal after each conversion using a fast
slewing on-chip buffer amplifier. This allows throughput
rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and
50 kHz (CS5016).
• Conversion Times:
CS5016
16.25 Ils
CS5014
14.25 Ils
CS5012A 7.21ls
• Self Calibration Maintains Accuracy
Over Time and Temperature
An evaluation board (CDB5012/14/16) is available
which allows fast evaluation of ADC performance.
• Low Power Dissipation: 150 mW
• Low Distortion
ORDERING INFORMATION:
Contact Crystal Semiconductor
HOLD
CS
RD
AO
BPIUP
RST
BW
INTRLV
CAL
EOT
EOC
SCLK
SDATA
40
20
ClKIN
REFBUF
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
CLOCK
GENERATOR
29
28
VREF
AGND
~ro,
16 BIT CHARGE
REDISTRIBUTION
DAC
26
AIN
27
DO (LSB)
Dl
D2
D3
D4
D5
D6
D7
D8
D9
Dl0
Dll
D12
D13
D14
D15 (MSB)
STATUS REGISTER
25
VA+
30
VA-
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 455 7581
11
VD+
36
VD-
10
DGND
31
TST
MAR '92
DS14F5
9-5
-
..""......""''''''......
......
.
.,
""
""
Semiconductor Corporation
I CS5030CS5031' I
."
."
12-Bit, 500 kHz, Sampling AID Converters
General Description
Features
The CS5030, and CS5031 are complete monolithic
CMOS analog-to-digital converters capable of 500 kHz
throughput. On-chip calibration circuitry achieves true
12-bit accuracy for the ADC and on-chip reference
over the full operating temperature range without external adjustments.
• Monolithic CMOS AID Converter
0.5118 Track/Hold Amplifier
211S AID Converter
2.5V Voltage Reference
Flexible Parallel, Serial and Byte
interface
The CS5030/CS5031 have a high speed digital interface with three-state data outputs and standard control
inputs allowing easy interfaCing to common microprocessors and digital signal processors.
Conversion
results are available in either 12-bit parallel, two a-bit
bytes, or serial data.
• 12-Bit ADC and Reference Accuracy
Total Unadjusted Error: ±1/2 LSB
Ref Tempco: 1ppm/oC
• Low Distortion
Signal-to-Noise Ratio: 72 dB
Total Harmonic Distortion: 0.01 %
Peak Harmonic or Noise: 0.01 %
The CS5030/CS5031 are available in a 24-pin, 0.3"
plastic dual-in-line package (PDIP), Cerdip and small
outline (SOIC) package.
• Low Power: 50mW
ORDERING INFORMATION:
Contact Crystal Semiconductor
VA+
VADB11IHBEN
DB10/SSTRB
TIH
AIN
(>----01
DB9/SCLK
DBB/SDATA
DB7/LOW
REF OUT
DB6ILOW
DB5ILOW
DB4ILOW
CLKIN O------~O----'
,----1-,
DB3/DB11
CONTROL
and
INTERFACE
DB2IDB10
FORMAT 0 - - - - - - - - - - > 1
BUSY/INT
DB1/DB9
DBO/DBB
AGND
DGND
Preliminary Product Information
CS
RD
CONVST
IThis ?ocument contains inforr!1ation for a. new. product. Crystal
.
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
.
(All Rights Reserved)
JAN '93
DS90PP3
9-6
.....
...
.......
.... __.....
~
CS5101A
CS5102A
~~~.
."
Semiconductor Corporation
16-Sit, 100 kHzl20 kHz AID Converters
Features
General Description
• Monolithic CMOS AID Converters
Inherent Sampling Architecture
2-Channel Input Multiplexer
Flexible Serial Output Port
The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters capable of 100 kHz
(5101A) and 20 kHz (5102A) throughput. The
CS5102A's low power consumption of 44 mW, coupled
with a power down mode, makes it particularly suitable
for battery powered operation.
• Ultra-Low Distortion
S/(N+D): 92 dB
THO: 0.001%
On-chip self-calibration circuitry achieves nonlinearity
of ±0.001% of FS and guarantees 16-bit no missing
codes over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with
harmonics below -100 dB. Offset and full-scale errors
are minimized during the calibration cycle, eliminating
the need for external trimming.
• Conversion Time
CS5101A: 81ls
CS5102A: 40 Ils
• Linearity Error: ± 0.001 % FS
Guaranteed No Missing Codes
• Self-Calibration Maintains Accuracy
Over Time and Temperature
• Low Power Consumption
CS5101A: 320 mW
CS5102A: 44 mW
Power-down Mode: < 1 mW
The CS5101A and CS5102A each consist of a 2-channel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architecture of the device eliminates the need for an external
track and hold amplifier.
The converters' 16-bit data is output in serial form with
either binary or 2's complement coding. Three output
timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar
input ranges are digitally selectable.
• Evaluation Board Available
ORDERING INFORMATION:
Contact Crystal Semiconductor
ClKIN
SClK
XOUT
REFBUF
VREF. O=~-+---i
TEST
'---"'----~
SCKMOD
AIN1
OUTMOD
AIN2
CH1/2
AGND
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581
25
23
6
VA+
VA-
DGND
7
VD-
VD+
FEB '92
DS45F1
9-7
..
.
..,..
.....,
.. ~~
~~~
.w~_
.•
~~
. . ..
CS5126
Semiconductor Corporation
·1
16-Bit, Stereo AID Converter for Digital Audio
Features
General Description
• Monolithic CMOS AID Converter
Inherent Sampling Architecture
Stereo or Monaural Capability
Serial Output
The CS5126 CMOS analog-to-digital converter is an
ideal front-end for stereo or monaural digital 'audio systems. The CS5126 can be configured to handle two
channels at up to 50kHz sampling per channel, or it
can be configured to sample one channel at rates up
to 100kHz.
• Monaural Sampling Rates up to 100 kHz
50 kHZ/Channel Stereo Sampling
• Signal-to-(Noise+Distortion): 92 dB
• Dynamic Range: 92 dB
95dB in 2X Oversampling .Schemes
• Interchannel Isolation: 90 dB
• 2's Complement or Binary Coding
• Low Power DissiRation: 260 mW
Power Down Mode for Portable
Applications
The CS5126 executes a successive approximation algorithm using a charge redistribution architecture.
On-chip self -calibration circuitry has 18-bit resolution
thus avoiding any degradation in performance with lowlevel signals. The charge redistribution technique also
provides an inherent sampling function which avoids
the need for external sample/hold amplifiers.
Signal-to-(noise+distortion) in stereo operation is 92dB,
and is dominated by internal broadband noise (1/2 LSB
rms). When the CS5126 is configured for 2X .oversampiing, digital post-filtering bandlimits this white noise to
20kHz, increasing dynamic range to 95dB.
ORDERING INFORMATION:
• Evaluation Board Available
HOLD
CS5126-KP
CS5126-KL
SLEEP RST STBY CODE
0 °c to 70°C
0 °c to 70°C
(was CSZ5126-KP)
28-Pin Plastic DIP
28-Pin PLCC
TRKl TRKR SSH1 SSH2 SDATA
SClK
3_ _ _---.1
elKIN 0-.::.
~------~
TST1
REFBUF 0.=.21'--_ _ _ _ _----,
TST2
VREF ('F20'--_ _--l
AINl
19
AINR
26
TST3
16 BIT CHARGE
27
TST4
REDISTRIBUTION
DAC
4
NC
UR
22
AGNDQ--------~
25
23
VA+
VA-
CrystalSemiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 TWX: 910-874-1352
7
6
DGND
VD-
VD+
MAR '92
DS32F1
9-8
....
. ....
....
~
..,..,~.
CS5317
~-~~
."
Semiconductor Corporation
16-Sit, 20 kHz Oversampling AID Converter
General Description
Features
• Complete Voiceband DSP Front-End
16-Bit AID Converter
Internal Track & Hold Amplifier
On-Chip Voltage Reference
Linear-Phase Digital Filter
• On-Chip PLL for Simplified Output
Phase Locking in Modem Applications
• 84 dB Dynamic Range
.80 dB Total Harmonic Distortion
• Output Word Rates up to 20 kHz
The CS5317 is an ideal analog front-end for voiceband
signal processing applications such as high-performance modems, passive sonar, and voice recognition
systems. It includes a 16-bit AID converter with an internal track & hold amplifier, a voltage reference, and a
linear-phase digital filter.
An on-chip phase-lock loop (Pll) circuit simplifies the
CS5317's use in applications where the output word
rate must be locked to an external sampling signal.
The CS5317 uses delta-sigma modulation to achieve
16-bit output word rates up to 20 kHz. The delta-sigma
technique utilizes oversampling followed by a digital filtering and decimation process. The combination of
oversampling and digital filtering greatly eases antialias
requirements. Thus, the CS5317 offers 84 dB dynamic
range and 80 dB THD and signal bandwidths up to 10
kHz at a fraction of the cost of hybrid and discrete solutions.
The CS5317's advanced CMOS construction provides
low power consumption of 220 mW and the inherent
reliability of monolithic devices.
• DSP-Compatible Serial Interface
• Low Power Dissipation: 220 mW
ORDERING INFORMATION:
Contact Crystal Semiconductor
Block Diagram
VCOIN
PHDT
RST
MODE
ClKIN
DOE
3
REFBUF
12
5
VOLTAGE
REFERENCE
CLKOUT
3COMPARATOR
384th Order
DECIMATION
FILTER
AIN
DATA
DOUT
NC
14
VA+
VA-
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 512445- 7581
15
AGND
2
10
4
VD+
VD-
DGND
MAR '92
DS27F2
9-9
-
.. ........
.......,......
~~
I CS5321 I
,.,,~~
~~
Semiconductor Corporation
High Dynamic Range Delta-Sigma Modulator
DESCRIPTION
FEATURES
The CS5321 is a high dynamic range, fourth-order
delta-sigma modulator intended for geophysical and
sonar applications. Used in combination with the
CS5322 digital FIR filter, a unique high resolution AID
system results.
• Delta-Sigma Architecture
- Fourth-Order Modulator
- Variable Sample Rate
- Internal Track-and-Hold Amplifier
The CS5321 provides an oversampled serial bit stream
at 256 Kbits per second (SOWR=1) and 128Kbits per
second (SOWR=O) operating with a clock rate of 1.024
MHz.
• Dynamic Range
- 124 dB @ 411 Hz Bandwidth
- 121 dB @ 822 Hz Bandwidth
• Signal-to-Distortion: 115 dB
The monolithic CMOS design of the CS5321 insures
high reliability while minimizing power dissipation.
• Input Range: ± 4.5V
• Low Power Dissipation:
- Normal Mode: 40 mW
- Low Power: 20 mW
VA+
ORDERING INFORMATION:
CS5321-BL
CDB5321
VA-
AGND
VD+
VD-
-55°C to +85°C
Evaluation Board
28-pin PLCC
DGND
LPWR
OFST
MFLG
AINR
AIN+
AIN-
SOWR
MCLK
MSYNC
MDATA
MDATA
VREF+
VREF-
Preliminary Product Information
I This
document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS88PP2
9-10
.... --- ...
""" .."""..
...
.
.., """""" .....,
~.
CS5322/CS5323
Semiconductor Corporation
24-Bit Variable Bandwidth AID Converter
General Description
Features
The CS5323 analog modulator and the CS5322 digital
filter function together as a unique high resolution AID
converter intended for geophysical and other applications which require high dynamic range. The
CS5323/CS5322 combination performs sampling, AID
conversion, and anti-alias filtering.
• Monolithic CMOS AID Converter
• Dynamic Range
- 130dB @ 25 Hz Bandwidth
- 120dB @ 411 Hz Bandwidth
The pair use Delta-Sigma modulation to produce highly
accurate conversions. The CS5323 oversamples, virtually eliminating the need for external anti-alias filters.
The CS5322 linear-phase FIR digital filter decimates
the output to anyone of seven selectable update periods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data is
output from the digital filter in a 24-bit serial format.
• Delta-Sigma Architecture
- Variable Oversampling: 64X to 4096X
- Internal Track-and-Hold Amplifier
• Flexible Filter Chip
- Hardware or Software Selectable
Options
- Seven Selectable Filter Corner (-3d B)
Frequencies: 25, 51,102,205,411,
824 and 1650 Hz
• Low Power Dissipation:
< 100mW
The CMOS design of the CS5322/CS5323 achieves
high reliability while minimizing power dissipation.
ORDERING INFORMATION
CS5322-KL 0 to +70 °C 28-pin
CS5322-BL -40 to +85 °C 28-pin
CS5323-KL 0 to +70 °C 28-pin
CS5323-BL -40 to +85 °C 28-pin
CDB5322/3 Evaluation Board
CS5322
CS5323
VA1+
IREF
INT
SUM
SFF
----~
~
VA2+
1
PLCC
PLCC
PLCC
PLCC
VA1-
VA2-
-
---
Analog
SYNC CLKIN CS
RIW
RESET
-MSYNC
1
~
Modulator
VD+
RSEL
SCLK
SID
SOD
MFLG
-MCLK
ERROR
DRDY
-MDATA -
ORCAL
DECA
VD+
DGND
DECB
CSEL
DECC
VD+
VD-
DGND
AGND1
AGND2
HIS TDATA PWDN
USEOR DGND
Preliminary Product Information IThiS .document contains info~ation for a. new. product.
Crystal
.
Semiconductor reserves the right to modify thiS product Without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
MAR '92
DS70PP5
9-11
..............
. .........
.,,-_
"""
"...
~
CS5324
~
Semiconductor Corporation
120 dB, 500 Hz Oversampling AID Converter
General Description
Features
The CS5324 analog to digital converter is a unique,
very high resolution AID converter intended for geophysical and sonar applications. It is a complete analog
front end to a Digital Signal Processor and provides
the DSP with a low distortion digital input suitable for
precision signal analysis. The CS5324 performs sampling, AID conversion, and anti-alias filtering.
• Monolithic CMOS AID converter
• 120dB Dynamic Range
• dc-500 Hz Bandwidth
The CS5324 uses delta-sigma modulation to produce
highly accurate conversions. The device oversamples
at 256X, virtually eliminating the need for external antialiasing filters. An on-chip linear-phase FIR digital filter
decimates the output to a 32 kHz output word rate.
Data is transmitted to the DSP as two, 8-bit bytes. An
additional FIR filter in the DSP further decimates the
signal to achieve 120 dB dynamic range over 500 Hz
bandwidth with signal-to-distortion of 110 dB.
• 110 dB Total Harmonic Distortion
• Internal Track-and-Hold Amplifier
• Delta-Sigma Architecture
-256X Oversampling
-Linear Phase Digital Filter
-Output Word Rate 32 kHz
The CMOS design of the CS5324 ensures high reliabilityand power dissipation of less than 180 mW.
ORDERING GUIDE:
• Low Power Dissipation: 150 mW
CS5324-Kl
CS5324-Bl
CDB5324
• Evaluation Board Available
INT
SUM
VA1+
VA2+
VA1-
7
12
6
VA2-
AGND1
13
5
AGND2
11
0° to 70°C
28-pin PlCC
-40° to +85°C 28-pin PlCC
Evaluation Board
VD+
VD-
DGND
22
23
21
~
~
~
8
ANALOG MODULATOR
9
4
IREF
10
SFF
28
FIR 1
15
FSYNC
S
~
PWDN
14
3
TST TSA
2
~
~
1
20
DO
D1
D2
D3
D4
D5
~
D6
E.
D7
TSB TSC ClKIN
Preliminary Product Information IThis document contains information for a new product.
Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581
August '91
DS36PP3
9-12
....
..,..
.....,
~~~.
•~.w _ _
•
.~
~~
Semiconductor Corporation
CS5412
I
12-8it, 1MHz Self-Calibrating AID Converter
Features
General Description
• Monolithic CMOS Sampling ADC
On-Chip Track and Hord Amplifier
Microprocessor Interface
The CS5412 CMOS analog to digital converter provides a true 12-bit representation of an analog input
signal at sampling rates up to 1MHz. To achieve high
throughput, the CS5412 uses pipelined acquisition and
settling times as well as overlapped conversion cycles.
• Throughput Rates up to 1MHz
• True 12-Bit Accuracy over Temperature
Typical Nonlinearity: 3/4 LSB
No Missing Codes to 12 Bits
• Total Harmonic Distortion: 0.02%
• Dynamic Range: 72dB
• Self-Calibration Maintains Accuracy
over Time and Temperature
• Low Power Dissipation: 750mW
Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
Unique self-calibration circuitry insures 12-bit accuracy
over time and temperature. Also, a background calibration process constantly adjusts the converter's linearity,
thereby insuring superior harmonic distortion and signal-to-noise performance throughout operating life.
The CS5412's advanced CMOS construction provides
low power consumption of 750mW and the inherent reliability of monolithic devices.
An evaluation board is available which allows fast con-.
firmation of performance, as well as example ground
and layout arrangements.
ORDERING INFORMATION:
Contact Crystal Semiconductor
APR '92
DS2F1
9-13
...
..........
.. ••181"""" ..,
~~
~
~.
~~
CS550,1
CS5503
Semiconductor Corporation
Low-Cost, 16 & 20-8;t Measurement AID Converter
Features
General Description
The CS5501 and CS5503 are low-cost CMOS AID converters ideal for measuring low-frequency signals
representing physical, chemical, and biological processes. They utilize charge-balance techniques to
achieve 16-bit (CS5501) and 20-bit (CS5503) performance with up to 4kHz word rates at very low cost.
• Monolithic CMOS ADC with Filtering
6-Pole, Low-Pass Gaussian Filter
• Up to 4kHz Output Word Rates
The converters continuously sample at a rate set by the
user in the form of either a CMOS clock or a crystal.
On-chip digital filtering processes the data and updates
the output register at up to a 4kHz rate. The converters'
low-pass, 6-pole Gaussian response filter is designed to
allow corner frequency settings from .1 Hz to 10Hz in
the CS5501 and .5Hz to 10Hz in the CS5503. Thus,
each converter rejects 50Hz and 60Hz line frequencies
as well as any noise at spurious frequencies.
• On Chip Self-Calibration Circuitry
- Linearity Error: ±O.0003% .
- Differential Nonlinearity:
CS5501: 16-Bit No Missing Codes
(DNL ±1/8LSB)
CS5503: 20-Bit No Missing Codes
• System Calibration Capability
The CS5501 and CS5503 include on-chip self-calibration circuitry which can be initiated at any time or
temperature to insure offset and full-scale errors of typically less than 1/2 LSB for the CS5501 and less than
4LSBfor the CS5503. The devices can also be applied
in system calibration schemes to null offset and gain
errors in the input channel.
• Flexible Serial Communications Port
- J.LC-Compatible Formats
- 3-State. Data and Clock Outputs
- UART Format (CS5501 only)
• Low Power Consumption: 25mW
- 10J.LW Sleep Mode for Portable
Applications
Each device's serial port offers two general purpose
modes of operation for direct interface to shift registers
or synchronous serial ports of industry-standard microcontrollers. In addition, the CS5501's serial port offers a
third, UART-compatible mode of asynchronous communication.
.
• Evaluation Boards Available
ORDERING INFORMATION:
Contact Crystal Semiconductor
• Pin-Selectable Unipolar/Bipolar Ranges
BPIUP
SLEEP
12
SC1
SC2
11
CAL
'-------------1
VREF
AIN
10
8
DGND
5
VA+
1
7
VA-
1
15
VD+
1
6
VD-
6-Pole Gaussian
9
AGND
14
20-BII Charge-Balance AID Converter
1
SDATA
ClKOUT
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: 512 445-7581
ClKIN
DRDY
CS
MODE
SClK
MAR '92
DS31F1
9-14
....
...
.. .....
~
•
~
~~
.r . . . •
.,.,
CS5504
~.
Semiconductor Corporation
Low Power, 20-Bit AID Converter
Features
General Description
• Offers superior performance to VFCs
and dual-slope integrating ADCs
The CS5504 is a 2-channel, fully differential 20-bit, serial-output CMOS AID converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high resolution measurement at output word
rates up to 100 samples per second.
• On-Chip Self-Calibration Circuitry
The on-chip digital filter offers superior line rejection at
50Hz and 60Hz when the device is operated from a
32.768 kHz clock (output word rate=20 Hz.).
• Two Differential Inputs
• Output update rates up to 100/second
The CS5504 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to insure
minimum offset and full-scale errors.
• Pin-Selectable Unipolar/Bipolar Ranges
Low power, high resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and batterypowered inStruments.
• Linearity Error: ±0.0015% FS
• 20-bit No Missing Codes
• Common Mode Rejection: 120 dB
Ordering Information:
CS5504-BP
-40°C to +85°C
CS5504-BS
-40°C to +85°C
• Low Power Consumption: 1.5 mW
VREF+
12
VREF-
VA+
VA-
13
14
15
DGND
VD+
16
17
20-pin PDIP
20-pin SOIC
2
AIN1+
AIN1AIN2+
AIN2-
AO
~
~
9
i--------
,---
M
U
X
~
~
4th-Order
Delta-sigma
Modulator
------
18
Interface
19
Logic
Digital
20
1
T
4
Calibration uC
I
CS
SCLK
SDATA
DRDY
Filter
11
~T
Serial
Calibration
SRAM
l
I
J
3
CONY
7
CAL
BP/UP
OSC
Is
16
XIN
XOUT
Preliminary Product Information[ThiS document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT '93
DS126PP1
9-15
III
.. .........
..... ......
~~
~~
."
CS5505
CS5507
~~
Semiconductor Corporation
CS5506
CS5508
Very Low Power, 16-Bit and 20-Bit AID Converters
General Description
Features
• Very Low Power Consumption
Single supply +5V operation: 1.5 mW
Dual supply ±5V operation: 3.0 mW
• Offers superior performance to VFCs
and multi-slope integrating ADCs
• Differential Inputs
Single Channel and Four-Channel
pseudo-differential versions
The CSSSOS/6/7/8 are a family of low power CMOS
AID converters which are ideal for measuring low-frequency signals representing physical,chemical, and
biological processes.
The CSSS07/8 have single-channel differential analog
and reference inputs while the CSSSOS/6 have four
pseudo-differential analog input channels. The
CSSSOS17 have a 16-bit output word. The CSSS06/8
have a 20-bit output word. The CSSSOS17 sample upon
command up to 100 output updates per second. The
CSS506/8 sample up to 60 updates per second.
The on chip digital filter offers superior line rejection at
SO and 60Hz when the device is operated from a
32.768 kHz clock (output word rate=20 Hz.).
• On Chip Self-Calibration Circuitry
The CSSS05/6/7/8 include on-chip self-calibration circuitry which can be initiated at any time or temperature
to insure minimum offset and full-scale errors.
• Linearity Error: ±O.0015% FS
• Flexible Serial Port
The CSSSOS/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers ot
synchronous serial ports of industry-standard microcontrollers.
• Pin-Selectable Unipolar/Bipolar Ranges
Ordering Information:
• Output update rates up to 100/second
VA+
VREFOUT
VREF+
VREFAIN1+
AIN2+
AIN3+
AIN4+
AIN-
16
VA-
"
I
I
Voltage Reference
1
14
15
I
17
18
VD+
DGND
"
"
20
19
2
23
21
22
Serial
Interface
Logic
~
,1Q.....
~
~
Contact Crystal Semiconductor
M
U
X
----->
Differential 4th
order deltasigma modulator
------>
I Calibration I
Digital
SRAM
Filter
!
----->
~
1-->
AO A1
-----L
Calibration uC
1
1 24
CS
DRDY
SCLK
SDATA
I OSC
13
15
CONY
XIN
M/SLP
~ CAL
~ BP/UP
)6
XOUT
The CS5505/6 are illustrated. The CS5507/8 are single-channel differential input devices.
Crystal.Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
APR '92
DSS9F2
9-16
. .... ....
~
~~~.
CS5509
~-. ,•
• 181181 • • • ~
Semiconductor Corporation
Single Supply, 16-Bit AID Converter
Features
General Description
• Offers superior performance to VFCs
and dual-slope integrating ADCs
The CS5509 is a single supply, 16-bit, serial-output
CMOS AID converter. The CS5509 uses charge-balanced (delta-sigma) techniques to provide a low cost,
high resolution measurement at output word rates up
to 100 samples per second.
• On-Chip Self-Calibration Circuitry
The on-chip digital filter offers superior line rejection at
50Hz and 60Hz when the device is operated from a
32.768 kHz clock (output word rate=20 Hz.).
• Differential Input
• Output update rates up to 100/second
The CS5509 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to insure
minimum offset and full-scale errors.
• Pin-Selectable Unipolar/Bipolar Ranges
Low power, high resolution and small package size
make the CS5509 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery
powered instruments_
• Linearity Error: ±0.0015% FS
• Differential Nonlinearity: ±1/2 LSB
• Common Mode Rejection: 120 dB
Ordering Information:
CS5509-BP
-40°C to +85°C
CS5509-BS
-40°C to +85°C
• Low Power Consumption: 1.5 mW
VREF+
9
AIN+
AIN-
VREF-
VA+
10
11
GND
VD+
12
13
8
Differential 4th
order deltasigma modulator
-.
1
14
Serial
Interface
Logic
7
Digital
16-pin PDIP
16-pin SOIC
15
16
CS
SCLK
SDATA
DRDY
Filter
1
T
3
Calibration uC
I
Calibration
SRAM
6
CAL
BP/UP
I_
I-
I
OSC
12
14
15
CONY
XIN
XOUT
Preliminary Product Informationl ThiS document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Samiconductor Corporation 1993
(All Rights Resarvad)
SEPT '93
DS125PP1
9-17
-
.... .....
..............
.....
CS5516
CS5520·
~~"..
."
Semiconductor Corporation
16-Bitl20-Bit Bridge Transducer AID Converters
Features
General Description
• On-chip Instrumentation Amplifier
• On-chip Programmable Gain Amplifier
• On-Chip 4-Bit D/A For Offset Removal
• Dynamic Excitation Options
• Linearity Error: ±0.0015% FS Max
Offset and Full-Scale Errors: ±8 LSB20
20-Bit No Missing Codes
• CMRR at 50 / 60Hz >200dB
• System Calibration Capability with
calibration read/write option
• 3, 4 or 5 wire Serial Communications
Port
• Low Power Consumption: under 30mW
10~W Standby Mode for Portable
applications
VA+
VA-
3
4
AGNDI
5
AGND2
The CS5516 and CS5520 are complete solutions for
digitizing ·Iow level signals from strain gauges, load
cells, and pressure transducers. Any family of mV output transducers, including those requiring bridge
excitation, can be interfaced directly to the CS5516 or
CS5520. The devices· offer an on-chip software programmable instrumentation amplifier block, choice of
DC or AC bridge excitation, and software selectable
reference and signal demodulation.
The CS5516 uses delta-sigma modulation to achieve
16-bit resolution at output word rates up to 60Hz. The
CS5520 achieves 20-bit resolution at word rates up
to 60Hz.
The CS5516 and CS5520 sample at a rate set by the
user in the form of either an external CMOS clock or a
crystal. On-chip digital filtering provides rejection of all
frequencies above 12Hz for a 4.096 MHz clock.
The CS5516 and CS5520 include system calibration to
null offset and gain errors in the input channel. The
digital values associate.d with the system calibration
can be written to, or read from, the calibration RAM
locations at any time via the serial communications
port. The 4-bit DC offset D/A converter, in conjunction
with digital correction, is initially used to zero the input
offset Value.
ORDERING INFORMATION:
Contact Crystal Semiconductor
MDRV-
MDRV+
8
2
VD+
VD-
20
21
DGND
19
AIN+
INI
OUT 1
AIN2-Channel
Delta-Sigma
Modulator
VREF+
IN2
2-Channel
FIR
Filter
OUT2
VREF-
BXl
SOD
BX2
SID
XIN
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222." Fax (512) 445-7581
XOUT
SMODE
SCLK
DRDY
CS
RST
I.ThiS document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
APR '92
DS74PP2'
9-18
.._-_
_
__
...
.-_..--._.-.
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
10
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
10-1
---------------------Low Power Tl, El and ISDN
Primary Rate Line Interface Circuits
Crystal Semiconductor offers a
broad family of low power CMOS
PCM line interface circuits, with
each device optimized for a unique
system application. The CS6152,
CS61535A,
CS61574A
and
CS61575 are recommended for use
in new designs. Since introducing
the industry's first T1 and E1 line
interface circuits (the CS61534 and
CS61544), we have shipped more
CMOS PCM line interface ICs than
any other vendor worldwide. Crystal Semiconductor's leadership continues with the best in pulse shapes,
jitter attenuation, jitter tolerance and
low power consumption.
COMMUNICATIONS PRODUCTS
CS6152
CS61535A
CS61574A
Tl
Tl/El
Tl/El
Tl/El
Receiver
Functions
Data
Slicer
Clock/Data
Recovery
ClocklData
Recovery &
Jitter Atten.
Clock/ Data
Recovery &
Jitter Atten.
Transmitter
Functions
Driver
Jitter Atten.
& Driver
Driver
Driver
Serial Control
Port
-
,/
,/
,/
DIP Package
24-pin, .3"
28-pin, .6"
28-pin, .6"
28-pin, .6"
28-pin
PlCC
28-pin
PlCC
28-pin
PlCC
28-pin
PlCC
-
,/
,/
,/
> 300 UI
28 UI
138 UI
Product
Rate
Surface Mount
AMIIB8ZS1
HDB3 Coder
Jitter Tolerance > 300 UI
of Receiver
Line Interface Comparison Table
CS6152: Basic DSX-l driver and receive buffer.
For low power cards using digital-ASIC clock recovery. Ideal for trunk card bays where TI density is limited by heat dissipation.
CS61574A and CS61575: Receive-side jitter attenuation supports loop-timing in customer-premises equipment and in channel banks. In the presence of large amplitudes of received jitter, the
CS61575 provides more jitter attenuation than
any device in the industry, and is ideal for AT&T
62411 applications.
CS61535A: Enhanced transmit-side jitter attenuator supports SONET VT1.5 and VT2, and other
high speed transmission systems such as digital
microwave radio and M13 multiplexers.
Tl Transceiver
Our CS2180B T1 Transceiver is a
perfect companion to our T1 line interface ICs. This device handles encoding and decoding of all T1
frame formats (D4, SLC-96 and
TlDM and ESF). Serial interface
and control registers make it simple
to configure from a microprocessor,
including per channel control options. Packages available include
40-pin DIP or 44-lead PLCe.
10-2
CS61575
Ta
Syst em
Backp lane
J Frame
·1
1
Encoder
Frame
I Decoder
,I
1
I
r-- l
CS2180B Transceiver
Jitter
Attenuator
Driver
rIII
Receiver [
CS61574 Line Interface
II
To
Network
~
PCM Line Card
The CS2180B is ideal for use with Crystal's family of line interface IC's
Quartz Crystals
To complement our family of T1
Line Interface circuits, Crystal
Semiconductor supplies pullable
quartz crystals. The CXT6176 (for
T1 applications at 1.544 Mbps) and
CXT8192 (for El applications at
2.048 Mbps) are designed for 100%
compatibility with our PCM line interface and jitter attenuator circuits.
._.-.
_.-_...,-__.._-_
...
Modem Analog Front End
Crystal's CS6453 provides the industry's first analog front end designed to support data and voice
communications. The CS6453 is optimized for PC modem cards that
implement telephone set, answering
machine emulation, and need to
support business audio 10. In addition to providing an 84dB ADC and
DAC for connection to the Data
Access Arrangement, the CS6453
includes a 125 ohm earphone driver,
an 8 ohm speaker driver, and interface circuitry for an electret microphone. The CS6453 can operate
with either 3.3V or 5.0V power supplies.
Acoustic Echo Cancellers
Crystal's CS6400 and CS6401 provide the industry's first echo cancellers optimized for cost sensitive applications. The CS6400 is an echo
canceling codec that includes a 16bit voiceband codec plus a application-specific DSP that provides 30
dB of echo return loss for echo tails
of up to 64 ms in length. The DSP
implements a fully adaptive, least
mean square update algorithm with
graded beta normalization. Proprietary algorithms also provide outstanding voice quality in environments with echo tails longer than 64
ms.
COMMUNICATIONS PRODUCTS
Ethernet
Crystal is the first company to bring
the benefits of low-power CMOS
technology to EthernetlCheapernet
transceivers. The CS83C92C uses
up to 40% less power than the
DP8392A and DP8392B. This
translates into increased reliability
and compatibility with surface
mount technology. The CS83C92C
is the first Ethernet transceiver
which is fully compliant with
ISOIIEEE 802.3.
Jitter Attenuation Circuits
Our jitter attenuation technology is
available stand-alone for a wide variety of applications. The CS61600
is ideal for T1 and El applications
while the CS80600 attenuates jitter
in T2, 2nd-level CEPT lines and
Token Ring LANs. Both attenuators
can be used with external divide circuits to handle low frequencies.
In 1994, Crystal will be introducing
a broad family of highly-integrated
10Base-T products.
DTMF Receivers
Crystal has improved on industry
standard DTMF receiver ICs while
maintaining 100% pin compatibility. Our device features on-chip filters which offer the best possible
signal-to-noise ratio allowing highly
accurate decoding of telephone
tones.
The CS6401 is a programmable
echo canceller which can be used to
develop algorithms for the CS6400.
10-3
.-_
_
..--_._.
__.._-_.
...-
COMMUNICATIONS PRODUCTS
CONTENTS
CS2180AIB T 1 Framerffransceiver .
CS6152 T1 (1.544MHz) Analog Interface
CS61535A T1 (1.544 MHz) & E1 (2.048 MHz ) Line Interface
CS61574A T1 (1.544 MHz) & E1 (2.048 MHz ) Line Interface
CS61600 T1 (1.544 MHz) & E1 (2.048 MHz ) Jitter Attenuator
CXT6176/8192 6.176 MHz and 8.192 MHz Crystals
CS6400 Echo-Cancelling Codec .
CS6401 Programmable Echo Canceller .
CS6453 Modem and Audio Analog Front End
CS80600 4.5 MHz to 8.5 MHz Jitter Attenuator
CS83C92A1C Coaxial Transceiver Interface
CS8870 DTMF Receiver .
See the Crystal Telecommunications Data Book
for the complete data sheets on the above products
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
... ....-.......
~~
CS2180B
CS2180A
~~
..,
..,
Semiconductor Corporation
~
~~
T1 Transceivers
General Description
Features
The CS2180A and CS2180B are monolithic CMOS devices which encode and decode T1 framing formats.
The devices support bit-seven and B8ZS zero suppression, and bit-robbed signaling. Clear channel mode can
be selected on a per channel basis.
• Monolithic T1 Framing Device
• Both Transceivers support D4 and
ESF framing formats
• CS2180B also supports SLC-96 and
T1 DM framing formats
• CS2180B has updated AIS and Carrier
Loss detection criteria
• CS2180B is Pin Compatible with
CS2180A, DS2180A and DS2180
TMSYNC
TFSYNC
The serial interface has been enhanced to allow the
CS2180A and CS2180B to share a chip select signal
and register address space with the CS61535A,
CS61574A and CS61575 PCM Line Interface ICs.
Applications
• T1 Line Cards
• ISDN Primary Rate Line Cards
Ordering Information:
CS2180B-IP
CS2180B-IL
CS2180A-IP
CS2180A-IL
40
44
40
44
Pin
Pin
Pin
Pin
Plastic DIP
PLCC
Plastic DIP
PLCC
-40
-40
-40
-40
to
to
to
to
85°C
85 °C
85°C
85 °C
TSER TABCO
9
TCLK
TLCLK
7
TSIGSEL
TMO
4
8
TSIGFR
6
mT-~~T~Ttj=:;~t========Jj
TCHCLK
TPOS
TLiNK 10
TNEG
INT
CS
SCLK
SOl
SOO
SPS
Serial
Interface
Registers
40
VOO
20
VSS
RST
TEST
RLOS
RSER~----r------'
RBV
RCL
RPOS
RNEG
RABCO
RLiNK
RLCLK
RSIGFR
RSIGSEL
RCHCLK
24
RFER
RCLK
RYEL RBL (CS2180B·IL only)
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
MAY'93
DS44F6
10-5
.. ........
. .. .......
,
,
.,~
~
..,
~~
~~
I
~
Semiconductor Corporation
CS6152
I
Low Power T1 Analog Interface
General Description
Features
The CS6152 combines the analog transmit and receive
line interface functions for T1 system interface in one
device. The T1 analog interface operates from a 5 Volt
supply, and is transparent to the T1 framing format.
Crystal's EXPERT Pulse™ circuitry shapes the transmit pulse intemally, providing the appropriate pulse
shape at the DSX-1 cross-connect for line lengths
ranging from 0 to 655 feet. The device provides the
ideal. front-end to digital gate array based clock recovery circuits.
• Provides Analog T1 Line Interface
• Low Power Consumption
(normally 180 mW)
• EXPERT Pulse ™ Programmable
Pulse-Shaping Line Driver
Applications
• Provides Receiver AMI-to-TTL Buffer
Which Compliments Digital Gate Array
Clock-Recovery Circuits
•
Interfacing Network Equipment such as Multiplexer,
Channel Banks and Switching Systems to a DSX-1
Cross Connect.
•
Interfacing Qustomer Premises Equipment such as
PABX's, T1 Multiplexer, Data PBX's and LAN Gateways to a Channel Service Unit or T1 modem.
• Driver Performance Monitor
ORDERING INFORMATION
CS6152A-IP
- 24 Pin Plastic, 300 mil DIP
CS6152-IL
- 28 Pin J-Iead PLCC
• Minimal External Components
Block Diagram
HIGHZ
TAOS
LENO
LEN1
LEN2
TGND
TV+
;
;
TPOS
TTIP
CONTROL
TNEG
TRING
TCLK
:: :
LINE
RECEIVER
DATA
DETECTION
RTIP
RRING
MTIP
MRING
* *
RV+
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
RGND
DPM
IThis .document contains inforr~ation for a. new. product. Crystal
.
Semiconductor reserves the nght to modify thiS product without notice.
APR '90
DS29PP5
1().6
..
...,., ...
.,~~.
•.,~
..r _ _
I CS61535A I
.~.
~
~
Semiconductor Corporation
PCM Line Interface
General Description
Features
The CS61535 and CS61535A combine the analog
transmit and receive line interface functions for a
T1/PCM-30 interface in a single 28-pin device. The line
interface unit (LlU) operates from a single 5 Volt supply
and is transparent to the framing format. Crystal's EXPERT Puise™ circuitry shapes the transmit pulse
internally, providing the appropriate pulse shape for
CCITT G.703, or for connecting to DSX-1 cross-connects for line lengths ranging from 0 to 655 feet. The
transmitter uses a 32-bit elastic store to remove jitter
from the transmit data.
• Provides Analog PCM Line Interface
for T1 and PCM-30 Applications
• Provides Line Driver, and Data and
Clock Recovery Functions
• Transmit Side Jitter Attenuation
Starting at 6 Hz, with> 300 UI of Jitter
Tolerance
Applications
• Low Power Consumption
(typically 175 mW)
•
• B8ZS/HDB3/AMI Encoders/Decoders
Interfacing network transmission eguipment such as
SONET multiplexer and M13 to a DSX-1 cross connect.
Interfacing customer premises equipment to a CSU.
Interfacing to PCM-30 links. .
•
•
• 14 dB of Transmitter Return Loss
Ordering Information
• Compatible with SONET, M13 , CCITI
G.742, and Other Asynchronous
Muxes
CS61535A-IP1
CS61535A-IL1
CS61535-IP1
CS61535-IL 1
28
28
28
28
Pin
Pin
Pin
Pin
Plastic DIP
PLCC O-Ieads)
Plastic DIP
PLCC O-Ieads)
T1
T1
T1
T1
& PCM-30
& PCM-30
& PCM-30
& PCM-30
Block Diagram
XTALIN XTALOUT
TCLK
TPOS
(TDATA)
~
TNEG
(TCODE)
~
RCLK
RPOS
(RDATA)
RNEG
(BPV)
19
F-.,------
~
~
i!-
,-orIeI
I
L
--J
--J
AMI,
B8ZS,
HDB3
CODER
4-4--
l
I
I
I
~
ATIENUATOR
128 123 124
15
j10
JITIER
(CLKE) (INT) (SDI) (SOO)
TAOS LENO LEN1 LEN2
MODE
-----------
CONTROL
I
TGND
~14
125
PULSE
SHAPER
CLOCK &
DATA
RECOVERY
I
BACK
I'---
f----+
13
TTIP
>16
LINE
19
RECEIVEYI+---'-"-
~~
1
SIGNAL
QUALITY
MONITOR
t2 21!
ACLKI LOS
RV+
TRING
RTIP
RRING
~ MTIP
DRIVER
MONITOR
RLOOP LLOOP
(CS)
(SCLI<)
~15
LINE DRIVER
V
LOOP
L6 127
TV+
2d
~
~
(RCODE)
MRING
(PCS)
DPM
(AIS)
RGND
Preliminary Product Information IThis ~ocument contains infor~ation for a. new. product. Crystal
.
Semiconductor reserves the nght to modify thiS product Without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1992
(All Rights Reserved)
NOV '92
DS40PP2.2
10-7
lIllI'
.... ... ..
. ..........
~
~
~~~
~~
CS61575 CS61574A
CS61574
~
Semiconductor Corporation
PCM Line Interlace
General Description
Features
The CS61575, CS61574A and CS61574 combine the
analog transmit and receive line. interface functions for
a T1/PCM-30 interface in a single 28-pin device.
The line interface unit (LlU) operates from a single 5
Volt supply and is transparent to the framing format.
Crystal's EXPERT Pulse™ circuitry shapes the transmit
pulse internally, providing the appropriate pulse shape
for CCITT G.703, or for connecting to DSX-1 crossconnects for line lengths ranging from 0 to 655 feet.
The CS61575 receiver uses a 128-bit elastic store to
remove jitter from the incoming data. The CS61574A
and CS61574 employ a 32-bit elastic store.
• Provides Analog PCM Line Interface
for T1 and PCM-30 Applications .
• Provides Line Driver, Jitter Attenuation
& Clock Recovery Functions
• Fully Compliant with AT&T 62411
(1990 Version) Jitter/Synchronizer
(Stratum 4, Type II) Requirements
Applications
• Low Power Consumption
(typically 175 mW)
•
InterfaCing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect
• Interfacing Customer Premises Equipment to a
CSU
• Building Channel Service Units
ORDERING INFORMATION Contact Crystal Semiconductor
• B8ZS/HDB3/AMI Encoders/Decoders
• 14 dB of Transmitter Return Loss
Block Diagram
MODE
,----
2
TCLK
TPOS
(TDATA)
TNEG
(TCODE)
RCLK
RPOS
(RDATA)
RNEG
(BPV)
----..
~
-t
-t
~
!-
7
6
L
R
E
0
L~
~ ~
A
C
t
PULSE
SHAPER
JITIER
ATIENUATOR
9
10
Preliminary Product Information
CLOCK &
DATA
RECOVERY
~~P
~ ~
C
,~"I ~
RLOOP XTALIN XTALOUT ACLKI
(CS)
TV+
+14
+15
LINE DRIVER
13
'----
f--------.
>16
/'
0
10
L I
o
I
IL
0
4-
CONTROL
TGND
IL
E I
4-
123 124 125
1 28
f-t
l; f-t
~,.
TI
AMI.
B8ZS,
HDB3
CODER
15
(CLKE) (INT) (SDI) (SDO)
TAOS LENO LEN1 LEN2
LLOOP
(SCLK)
I
SIGNAL
QUALITY
MONITOR
LINE
RECEIVER
4-~
r-
~
~~
~
DRIVER
MONITOR
121
LOS
21
!
RV+
22
t
~
r-------1J.
TIIP
TRING
RTIP
RRING
MTIP
(RCODE)
MRING
(PCS)
DPM
(AIS)
RGND
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581
JUN'90
DS20PP5
10-8
. .........
.............
~.a
• •..,..,~ •
CS61600
Semiconductor Corporation
PCM Jitter Attenuator
General Description
Features
• Minimal External Components Required
The CS61600 from Crystal Semiconductor accepts T1
(1.544 Mb/s) or CCITT standard (2.048 Mb/s) data and
clock inputs, and tolerates at least 7 (and up to 14) unit
intervals, peak-to-peak, of jitter. Before outputting data
and clock, jitter is attenuated using an internal clocktracking variable oscillator and a 16 bit FIFO elastic
store.
.14 Pin DIP
The jitter attenuation function can be determined by
appropriate specification of the external crystal.
• Unique Clock-Tracking Circuitry Filters
50 Hz or Higher Frequency Jitter for
T1 and PCM-30 Applications
The CS61600 is transparent to data format, and is intended for application in carrier systems, switching
systems, Local Area Network gateways and multiplexers.
• Single 5 Volt Supply
• 3 Micron CMOS for High Reliability
and Low Power Dissipation: 50 mW
Typical at 25°C
ORDERING INFORMATION
CS61600-ID1
CS61600-IP1
-
14 Pin CERDIP; T1 and 2.048 MHz
14 Pin Plastic DIP; T1 and 2.048 MHz
Block Diagram
FIFORST OVR
2
- - - -
-3 -
RESET
- - - -
FIFO CONTROL
DIN
,9
13.
~------~~DOUT
FIFO
CLKIN~8~'~
, 10
~-..-----~CLKOUT
,12
o--jol--,-----~
ARC
•
, 14
~V+
'7
+;---------"GND
4
XTALIN
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
5
XTALOUT
11
OSCOUT
APR '90
DS9F3
10-9
..,..""'''''' .......
.....
........
CXT6176
CXT8192
.."..,,~
Semiconductor Corporation
Pullable Quartz Crystals
Description
Features
Crystal Semiconductor's line interface and jitter attenuator IC's require unique performance specifications for
the crystals. The CXT6176 and CXT8192 are built to
meet Crystal's specifications for T1 and PCM-30 applications respectively.
• Complements CS61534, CS61535,
CS61535A, CS61544, CS61574,
CS61574A, and CS61575 PCM Line
Interface integrated circuits and
CS61600 PCM Jitter Attenuator.
Ordering Information
CXT6176
CXT8192
Crystal for T1 Applications
Crystal for PCM-30 Applications
0
CXT6176
,-----------1
eXT81.2
1--------------- 1
CMOS OSCILLATOR CIRCUIT MODEL
1
1
I
I
I
I
1
1
I
C load
I
A
Crystal Line Interface or Jitter Attenuator I.C.
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
. (512) 445-7222 FAX: (512) 445-7581
IThis
document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
APR '91
DS39PP4
10-10
....
..
.
... .......
~
~~
CS6400
~-~~
~
Semiconductor Corporation
~
Echo-Cancelling Codec
General Description
Features
The CS6400 is an application-specific digital signal
processor optimized for acoustic echo and noise cancellation applications.
A high-quality codec is
integrated with the processor to provide a complete,
low-cost echo and noise-cancellation solution.
• Applicable in:
Digital-Cellular Hands Free
Analog-Cellular Hands Free
Office Speaker Phones
Desktop & Video Teleconferencing
Noise Cancellation
Network/Base Station
The CS6400 is a fully independent processor that requires no signal processing support to implement its
cancellation functions. Volume control, mute, sleep,
and two loop back functions are also provided.
The on-chip A/D and D/A converters employ oversampiing technology, which eliminates the need for
complex external anti-aliasing and reconstruction filters,
further reducing system cost.
• Echo Cancellation
- 512 Tap (64 ms at 8 kHz Fs)
- Split Mode For Two ECs
- Cascadable For Longer Response
- Coefficient Dump/Restore
- No Signal Delay
The CS6400 has a zero glue-logic serial interface that
is compatible with most DSPs. A clock and sync line
control the transfer of serial data via the separate serial
data-in and data-out pins. Both is-bit audio data and
control/status information are multiplexed on this serial
channel using a steering bit.
• Zero-Glue Serial Data/Control Interface
• On-Chip Codec
- > 80 dB Dynamic Range
- > 70 dB S/(N+D)
- 300-3400 Hz Bandwidth
The CS6400 can easily be tailored to special applications via metal-mask options. Custom development
services for producing such derivatives are available
from Crystal.
The CS6400 is packaged in a 28-pin PLCC.
• Optional Supplementary Voice Switching
ORDERING INFORMATION:
RESET
ClKIN
ClKOUT
TIN
TOUT
CS6400
TMODE VREFBUF
SYNCOUT
Serial 110
Analog VO
DSP
CONFIG
SDI_B
AOUT_P
SDI_A
/'----:.~
SClK
SDO
SFRAME
SMASTER
SSENSE
AOUT_M
~I
SSYNC
: Status,
L . _ _- - - '
--+
'---,--,----'
AIN
VD1+ VD2+ VD3+
Preliminary Product Information I
DGND1
DGND2
DGND3
VA+
AGND
This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
AUG '93
DS80PP1
10-11
.... .
~~~
•~..r _ _
•
CS64o'1·1
.~
. . . .t-'t-' •
I·
....
Semiconductor Corporation
Programmable Echo Canceller
Features
General Description
• For All Echo Canceller Applications
- Digital Cellular Network Equipment
- Analog Cellular Hands Free
- Digital Cellular Hands Free
- Office Speaker Phones
- Desktop Teleconferencing
- Long Distance Network Equipment
The CS6401 is a digital signal processor optimized for
acoustic and/or network echo cancellation algorithms.
The CS6401 implements all the adaptive filtering and
control algorithms needed for high quality echo cancellation for a variety of applications .. Crystal has
developed the echo cancellation algorithms, and provides the DSP object code with the evaluation board.
Custom algorithm development services are available
from Crystal.
The CS6401 contains four main blocks:
• 16 MIPS, 16-Bit Programmable DSP
• 512-tap Adaptive FIR Filter Hardware
Accelerator
• Data 1-0 Serial Interface
• Boot/Control Interface
• Echo Cancellation
- 8 kHz Sampling Rate
-512 tap (64 ms)
- Split Mode for Two ECs
(total taps = 512)
ORDERING INFORMATION
CS6401-CQ 64-pin Plastic QFP
CDB6401
Evaluation Board with object code
• Cascadable For Longer Impulse
Response
VOO VSS
8
-+
XTALI
{9
.
XTALO
CLKO
110
112
19
+7
{s
B17-B10
RESET
Oscillalor
I
1
TESTI TESTO TESTM TCLKEN
114
I
I
1
1
t15
~
Test
1
1
1
SSI1
59
58
SO
BSEL
B011-B01
BOO
E-.
~
BooU
1S-Bit
Control
OSP
61
Adaptive
Serial
Filter
Interface
Co-Processor
5Q
54
5!i
E-
~ 18~21
BIE1
53
BIE2
BOE
P f'
Pdt I ~
t'
re Immary ro uc norma Ion
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Is
15
SMOOE1 SMOOEO
S4
SCLKM
llj,~~
SYNCM
, SOl1
:S001
: SYNC1
: SSI1
, SYNC01
~ S-01N2
'S002
, SSI2
, SYNC2
: SYNC02
SCLK
SYNCP
IThis document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconducror Corporation 1992
(All Rights Reserved)
OCT '92
DS98PP1
10-12
... ..-....,
~~
~
~
~~~.
~~
CS6453
.~.
Semiconductor Corporation
Modem and Audio Analog Front End
General Description
Features
The CS6453 is a high-resolution analog-to-digital and
digital-to-analog converter for V.fast, V.32bis, V.32 and
other high performance modems.
• Complete Voiceband DSP Front-End
24-Bit AID Converter
18-Bit DIA Converter
The CS6453 also supports telephone emulation. In
telephone emulation the CS6453 and external DSP
collectively implement both modem and telephone set
capabilities. This allows an end-user to connect a
handset to the "modem" card, and alternatively use the
telephone connection for voice and data.
• 84 dB Dynamic Range and 80 dB
Signal-to-Distortion (at full scale)
• Supports telephone emulation
The CS6453 has 5 kHz bandwidth for modem and
telephone applications, and 10 kHz bandwidth for business audio applications. The business audio capability
allows the modem to playback and input audio files.
• Supports business audio
• On-chip speaker driver for modem
monitoring
The CS6453 also supports the digital speaker signal of
the PCMCIA interface standard. The modem can transfer the modem monitor signal via PCMCIA to the
system speaker.
• Supports PCMCIA digital speaker
signal
• 3.0 to S.SV power supply range
ORDERING INFORMATION:
CS6453-CQ
44-Pin QFP package
AFECLK
MIC+
MIC·
RX+
RX·
2
2
3rd order
IIR
FILTER
RXDATA
EAR+
EAR·
RXENA
SERIAL
LOCAL DIGITAL
LOOPBACK
DSPKR
SPKR+
SPKR·
RXSTR
AND
TXDATA
SPKOFF
ST+
STTX+
TX·
TXENA
DIFFERENTIAL
SWITCHED
RI--<~-+-1. CAPACITOR
FILTERS
2nd ORDER
ZERO ORDER HOLD
TXSTR
& 2nd ORDER
MODULATOR
IIR FILTER
I Transmit
TXOFF
TXV+
Preliminary Product Information
TXGND
TESTO
TESTl
DV+ DGNDRESET
IThis
document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
OCT '93
DS110PP3
10-13
-
181_
..
..,..
.....
"-''''~.
CS80600
.:. 1IItr . . .· . . ..
~..,
Semiconductor Corporation
High Speed Jitter Attenuator
Features
General Description
• Accepts Input Clock with Frequency of
4.5 MHz to 8.5 MHz
The CS80600 from Crystal Semiconductor accepts 4.5
to 8.5 MHz clock and data inputs and removes up to
±3 data bits of jitter before outputting the data and
clock. Jitter is removed using an internal clock tracking
circuit and an 8-bit FIFO elastic store.
• Unique Clock-Tracking Circuitry
Applications
• Tolerates and Attenuates At Least 3
Unit Intervals of Jitter
• Token Ring: The CS80600 can be used
to eliminate the accumulation of data-pattern dependent jitter which is the primary
factor limiting the size of token rings. The
CS80600 is Intended for application in station adapter cards,in active wiring
concentrators, and in repeaters.
.
• Minimal External Components Required
.14 Pin DIP
• Single 5 Volt Supply
• PCM: TIC~ T2, and CEPT2 and second or.
der multiplexers.
• 3 Micron CMOS for High Reliability
and Low Power Dissipation: 50 mW
Typical at 25 DC
ORDERING INFORMATION
CS80600-P
- 14 Pin Plastic DIP
Block Diagram
FIFORST OVR RESET
2
r
-
-
-
-
1
3
- - - --
- -
--
-
- -
-- --- -
-
-
FI FO CONTROL
DIN
ClKIN
·9
13
FIFO
8'
•
:10
f
,f
IHAlF FUlll
DETECT
~
VARIABLE OSCillATOR
-
,6
- - - - - - ~L ___ 5 _____
'12
I
DOUT
ClKOUT
ARE
ARC
.#-.
V+
'7
~
GND
11. ___ '
XTALIN XTAlOUT OSCOUT
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
APR '90
bS10i=3
10-14
.........
...
....".,,,., .....
".,
_- .
~.
CS83C92A
CS83C92C
.~
Semiconductor Corporation
Coaxial Transceiver Interface
General Description
Features
• Implemented in High Voltage, Low
Power CMOS
• Compatible with National's DP8392A
• CS83C92C is Compliant With
ISO/IEEE 802.3 10Base5 (Ethernet)
and 10Base2 (Cheapernet)
• All Transceiver Functions Integrated
Except Signal and Power Isolation
• Squelch Circuitry Rejects Noise
The CS83C92 Ethernet Transceiver interfaces an Ethernet or Cheapernet Local Area Network (LAN) to a
LAN Adapter board, and may be located up to 50 meters from the station equipment. The Transceiver
operates with the Crystal LAN components CS8005
Ethemet Data Link Controller and the CS8023A Manchester Code Converter. The CS83C92A is fully
compatible with the DP8392A but the CS83C92A is
built in CMOS technology (hence the 83"C"92). The
CS83C92C is a higher performance grade which is
compliant with IEEE 802.3 specifications.
• Receive & Transmit Mode Collision
Detection
For Ethernet applications, the CS83C92 is mounted on
the COAX cable, and connects to the station equipment via an AUI cable. In a Cheapernet network, the
CS83C92 is usually mounted on the LAN adapter card
in the station equipment where it connects to the thin
COAX through a BNC connector.
• Standard 16-pin DIP Package & 28 pin
PLCC
ORDERING INFORMATION:
CS83C92A-CP
PDIP
I CS83C92C-CP PDIP
CS83C92A-CL
PLCC
CS83C92C-CL PLCC
• CD Heartbeat Externally Selectable
Allowing Operation with IEEE 802.3
Compatible Repeaters
RECEIVE
PAIR
LOW PASS
FILTER
lk
TXO
GND
~~-ft----l-l----~TX+
'-----~
VEE
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
TRANSMIT
1 4 - - - - + - - - - - - o T X _ PAIR
DTE INTERFACE
Jul '92
DS79F2
10-15
.. ...
...
......,.
.. __
~-
~~,..,.
.., .,.,
CS8870
Semiconductor Corporation
DTMF Receiver
General Description
Features
• Full Receiver Implementation
• Central Office Quality
• Adjustable Receive Sensitivity
• Adjustable Detection and Release Time
The CS8870 is a fully integrated DTMF (Dual Tone
Multifrequency) receiver for decoding tone pairs generated by a tone dialing telephone. The decoded signal is
output as a four bit binary code. All of the functions
needed to decode the 16 DTMF tone pairs are integrated in the CS8870 using Crystal's CMOS
double-poly process, taking advantage of the low power
and high performance offered by this technology.
• Single Supply Operation
• Low Power Consumption
• 18 Pin Package
ORDERING INFORMATION
• Pin Compatible with MT8870B
CS8870-IP
-
18 Pin Plastic DIP
Block Diagram
VSS
VREF
9
4
BIAS
CIRCUIT
Q1
POWER
BIAS
IN+
DIAL TONE
IN-
FILTER
GS
DIGITAL
ZERO CROSSING
DETECTORS
DETECTION
ALGORITHM
CODE
CONVERTER
AND
LATCH
O-j-------"
3
~-,.-~
7
OSC1
CHIP CLOCKS
8
OSC2
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
17
SVGT
APR '90
DS1F3
10-16
.._-_
_
__
...
.-_..--._.-.
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & D/A CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
11
SALES OFFICES
11-1
APPENDICES
CONTENTS
Definitions
11-2
- Product Category Levels .
11-3
- Product Preview,Preliminary and Final Data Sheets
11-4
Radiation Performance
11-4
Reliability Methods
11-5
Mechanical Data
11-12
_.-_..........
__.._-_
..._.-.
DEFINITIONS
PRODUCT CATEGORY LEVELS
Level II -- Production Level II
Crystal's integrated circuit (IC) products are fabricated, assembled and tested either in-house or
through one or more subcontractors. Qualification and manufacturability criteria are defined for
each of four product category levels achievable
during the product life cycle of an IC. Products
are classified by the most stringent category level
requirements met. Crystal's goal is to achieve
Level I (World-Class) status for the majority of its
product families. The product category levels are:
Level IT is the high volume production qualification level for IC products. Level IT products have
met the goals for sustainable manufacturability
and reliability by passing a comprehensive series
of qualification tests, completing product documentation, and demonstrating product performance through detailed characterization.
Level IV:
Level III:
Level IT:
Level I:
Engineering Prototype (EP) Release
Production Level III
Production Level IT
World Class
Level IV -- Engineering Prototype Qualification (EP)
Level IV is the first qualification level for IC
products. It is used for early sampling and risk
production builds. Qualification tests to achieve
Level III begin shortly after the receipt of first
functional devices. Level IV packaged devices
are marked with an additional "EP".
Level I -- World Class Products
Level I is the highest level attainable for any
product family. Qualification tests for Level I involve routine monitoring of ramped product families over a period of time to measure increasingly
stringent reliability and quality levels that require
a substantial number of devices and device-hours.
Additionally, sources of variation throughout the
manufacturing process (fab, assembly and test)
are monitored and reduced over time following
industry standard learning curves. This provides a
statistical, pro-active approach to direct improvements in reliability performance and outgoing
qUality. It is the goal of every product family to
achieve Level I status.
Level III -- Production Leyel III
Level III is the second qualification level for IC
products. This level is applicable to devices
which are on track to achieving a Production
Level IT qualification and provides an interim reduction in the risk of substandard product shipments to customers. Comprehensive production
test programs (with guardbands) are used for testing Level III products. Characterization of initial
products is complete. Qualification tests have
been completed per the criteria shown in the
Qualification Criteria Table at the front of this
databook.
11-3
.._-_
_
...-.
.-_..__
~--.-.
. DEFINITIONS
DEFINITION OF DATA SHEET TYPES
RADIATION RESISTANCE PERFORMANCE
Each product developed by Crystal will be supported by technical literature where the data
sheets progr:ess through the following levels of refinement:
Crystal· products are manufactured using various
CMOS technologies. While not able to withstand
large doses of radiation, our products are suitable
for operation in low dose applications. Indeed, the
self calibrating architecture of many of the NO
Converters is able to compensate for the effects of
radiation.
I. Product Preview
This is a I-to-4 page document which describes
the main features and specifications for a product
that is under development. Some specifications
such as exact pin-outs may not be finalized at
time of publication. The purpose of this document
is to provide customers with advance product
planning information.
II. Preliminary Product Information
This is the first document completely describing a
new product. It contains an overview, specifications, timing diagrams, theory of operation, pinout diagram, applications information, ordering
guide and mechanical information. The numbers
in this data sheet are based on prototype silicon
performance and on worst-case simulation models. The specifications represent the designer's
best estimate for the "real"
numbers. Min and
max values are included where possible. The purpose of this document is to provide system designers with technical information sufficiently detailed to guarantee that they can safely begin active development.
III. Final Data Sheet
This is an updated version of the preliminary data
sheet reflecting actual production performance of
the final product. Updates include tighter specifications, more min and max values, and any application information that has arisen during the early
life of the part. The purpose of this document is to
communicate the confirmed performance of products which have passed qualification, been fully
characterized, and are in production.
11-4
Crystal will assist customers to test parts for radiation resistance by supplying free, data-logged
parts. In exchange,. we would like the parts returned to us, so that we can measure their post-radiation performance. In addition, we would like a
copy of any report that is generated, along with
permission to publish the report for other customer's information.
Several customer's have already undertaken radiation testing of our NO Converters. Please contact
the factory for the latest information and copies of
the radiation performance reports.
----------------------
RELIABILITY METHODS
RELIABILITY METHODS
I. CONCEPT OF RELIABILITY
In general terms, the reliability of a semiconductor device is defined as the measure of the
functional stability of the device with respect to
time. Expressed in a more quantitative sense, it is
the probability that the device will operate with a
specified performance over a specified period of
time under a given set of conditions.
Reliability characteristics are usually stated in reverse terms as the loss of ability to function, or
failure rate. The reliability performance of a device can best be summarized by the reliability life
or "bathtub" curve (Figure 1). The reliability performance is characterized by three phases: infant
mortality, useful life, and wearout. Infant mortality failures can be reduced by proper
manufacturing controls and screening techniques.
The useful life period is typically a long period of
time where only occasional random failures occur.
During this time the failure rate is usually very
low. The final period is aptly named wearout. Using proper design guidelines and device
applications, this period is shifted well beyond the
lifetime required by the user.
Reliability Life
( Bathtub) Curve
t
Digital Device or Crystal
Smart Analog Device .7'/
Traditional Analog IC
-----y /'
--Infant Mortality
Failures
Random
Failures
Operating Life
Wearout
Failures
---+
Figure 1.
An item of great importance in evaluating reported reliability characteristics is the definition of
a failure. Crystal's definition of a failure is any
device that fails to meet ANY data sheet parameter. Crystal's digital self-calibration techniques
provide stable performance over temperature and
REL3
life. Traditional Analog IC's and hybrids exhibit
wearout mechanisms very early in the life of the
product. One competitor's analog-to- digital converter's linearity error stability is specified at
± .00075 % per WOO hours at 25°C. Stability
degradation at 70 °C is unspecified and is likely
to be accelerated greatly as temperature increases.
The dashed line of Figure 1 is typical of the
wearout seen in a competitor's Analog IC or hybrid. As you can see, wearout begins much earlier
than a digital device or a mixed analog and digital
chip utilizing Crystal's SMART analog design architecture and CMOS wafer technology.
II. CRYSTAL SEMICONDUCTOR
RELIABILITY STRESSING
These stresses are done on every new product, assembly house or fabrication· subcontractor. Some
of Crystal's acceptance criteria and goals are as
described in the Qualification Criterion Table in
section 1 of this data book.
Accelerated Operating Life Stress
Accelerated operating life stressing is performed
to accelerate thermally-activated failure mechanisms through the application of extreme
temperature and dynamic biasing conditions. The
typical temperature and voltage conditions used in
the stress are 125°C with a bias level at the maximum data sheet specifications. Some devices may
be stressed at an even higher voltage level to further stress the oxides of the device. All devices
used in life stress are sampled directly from the
production flow with no special processing or prescreening. Stressing is performed per Mll.. STD
883, method 1015, condition D (dynamic signals).
These dynamic conditions simulate as much as
possible actual operating conditions in an application.
11-5
•
.. .
. ,.,,-_._.
~~~. . . .~~ • • •1IIir
Infant mortality (48 hrs at 125°C), early operating life stress (168 hrs at 125°C) and long term
operating life (typically 1000 hrs at 125°C) are
reported . Infant mortality life simulates approximately 3-4 months in the field at 55°C and is
reported as a percent. Early and Long term life
simulate the total failures seen in the field and are
expressed in FITS (failures in time ). 1 FIT = 1
failure per billion device-hours. Derating of early
and long term operating life is done using Arrhenius thermal equations along with Weibull
statistics. A 60 % upper confidence limit (UCL)
and .7 electron volts (eV) activation energy are
used in this calculation.
85 °CI85% R.B.
85 0c/ 85% R.H. is an environmental stress performed at a temperature of 85°C and at a relative
humidity of 85%. The test is designed to measure
the moisture resistance of plastic encapsulated devices. A nominal-voltage static bias is applied,
with minimum power consumption, to the device,
to accelerate the electrolytic corrosion of the metallization. Failures are expressed in % ltime with
168, 500, and 1000 hour cumulative results reported.
Autoclave
Autoclave is also an environmental stress which
measures the moisture resistance of plastic encapsulated devices. Conditions for this test are
121°C, 100% relative humidity, and 1 atmosphere of pressure (15 psig), with no bias applied
to the circuit. Corrosion of the die is the expected
failure mechanism. Stressing is usually performed
for 144 hours. Failures are expressed in %/time
with 48,96, and 144 hour results reported.
Temperature Cycling
Temperature cycling typically accelerates the effects of the thermal expansion mismatch among
the different components within a specific pack11-6
RELIABILIty METHODS
age and circuit. The stress is performed per Mll..,
STD 883, method 1010, Condition B (-55°C to
+125 0c) or C (-65°C to +150 0c). Stressing is
done in an air environment. A cycle consists· of
ten minutes at -65°C, five minutes transfer time,
and ten minutes at + 150 0c, Stressing is typically
performed for 1000 cycles. Failures are expressed
in %/cycles, with 100,500, and 1000 cycle results
reported.
Thermal Shock
The objective of thermal shock is basically the
same as that of temperature cycling - to exercise
the difference in thermal expansion coefficients
within the integrated circuit package and die.
Thermal shock provides additional stress as the
device is exposed to a rapid change in· temperature, due to a maximum transfer time of ten
seconds, as well as the increased thermal cbnductivity of a liquid environment. This test is
performed per Mll.., STD 883, method 1011, Condition B (-55°C to +125 0c). In one cycle of
thermal shock, devices are placed in a fluorocar~
bon bath cooled to -55 °Cfor five minutes, then
transferred to an adjacent bath ftlled with fluorocarbon at 125°C for five minutes. Stressing is
performed for 500 cycles. Failures are expressed
in %lcycles, with results reported at 100, 200, and
500 cycles.
Electrostatic Discharge
Electrostatic discharge testing is performed to determine the handling sensitivity of a
semiconductor device. This test is perfomed per
MIL STD 883 method 3015, which simulates the
resistance (15000) and capacitance (100 pF) of
the human body. Also the machine model test is
performed with a
resistance and a capacitance
of 200 pF to simulate, as its name implies,. a typical insertion tool, handler, etc. that comes in.
contact with the leads of a semiconductor device.
on
REL3
--------~------------Latchup
Latchup testing is perfonned to ascertain whether
a device can sustain SCR latchup due to a DC
current input. The pin being tested has a DC current forced to it with the device power supplies at
nominal voltage and inputs at ground state. Susceptibility of each input is tested with both a
positive and negative DC current forced into it.
This test is perfonned per the standard test procedure recognized by JEDEC.
C dvldt Latchup Testing
This test is perfonned to evaluate the susceptibility of a CMOS device's power pin to
supinstantaneous ESD discharge into a power
ply pin or a rapid ramp of a power pin during
power up. Positive and negative pulses are supplied to the power supply pins with a change in
voltage of greater than 500 V IllS and a 0 to 5 V
risetime of less than 15 ns. Ground, Vss , and the
pin under test are connected to ground. The supply current is monitored for excessive current.
III. FAILURE RATE CALCULATIONS
Failures during typical reliability stressing generally are in the infant mortality and random failure
sections of the "bathtub" curve. Thennally accelerated failure rates can be derated to actual
operating conditions by commonly accepted
mathematical models.
Operating life stress is usually reported in the derated fonn. That is, operating life is perfonned at
125°C and results are reported for, an equivalent
time at a typical operating stress temperature for
an application, generally 25°C, 55 DC, or 70°C.
Failure rates for other temperatures are calculated
using a computed acceleration factor.
There are many probability models used in reliability analysis for calculating failure .rates. The
REL3
RELIABILITY METHODS
simplest fonn of calculating a failure rate (ER.)
would be to divide the number of failures observed after test (N) by the number of
device-hours of stress.
ER.=~
(1)
D-H
where D is the number of devices stressed and H
is the number of stress hours. If this number is
multiplied by 109 we obtain the failure rate expressed as Failure In Time (FIT). FITS are
expressed as failures per billion device operating
hours.
(2)
FITS = (ER.)(lO 9)
However, using equation (1) allows only for a
failure rate calculation at the stress temperature. In
order to apply the equation to the desired use temperature we use the well-known Arrhenius
relationship to determine the thennal acceleration
factor, Fa. One hour of device operation at temperature Tl is equivalent to Fa hours of operation
at temperature T2. The activation energy, EA, is
an important parameter in the Arrhenius equation
and is discussed below. The Arrhenius equation is:
Fa(TI ~ T2)
EA".....k
=;k ~ T{
1
T2 )
(3)
where k = Boltzman's Constant (8.63 x 10-5
eV10 K) and TI is the accelerated stress junction
temperature and T2 is the desired use operating
junction temperature in degrees Kelvin.
Junction temperatures, TI and T2, should be used
in determining acceleration factors. This temperture can be obtained from the equation below.
Tj
=Ta + 8jaPd
(4)
where Ta is the operating ambient temperature
11-7
_.-_..-__.....-_-_
...-..
RELIABILl1Y METHODS
and 9ja is the package thermal dissipation (0C! W)
and Pd is the device power dissipation.
acceleration factors can result in greatly differing
failure rates.
Crystal utilizes a low power CMOS process
which typically raises the junction temperature
about 7 to 15°C, whereas analog bipolar It's and
hybrids can have power dissipations in the 1 W
range. These differences in device junction operating temperatures can greatly affect the
acceleration factors. For example, let's calculate
the acceleration factors of a device with a power
di.ssipation of 1 watt packaged in a 40 pin ceramic
package. This is equivalent to a junction 'temperature change from 160°C to 60 °C and from Table
2 the acceleration factor is 277. A typical Crystal
device junction temperature is 10 °C higher than
the ambient which results in a junction temperature change from 135°C to 35 DC. This results in
an acceleration factor of 636, as shown in Table 2.
By comparing the results in Table 2 one can see
how derating to a lower use temperature or failing
to consider junction temperature when calculating
Table 3 compares acceleration factors for different
activation energies. Using a 1.0 eVactivation energy versus a .7 eV activation energy results in a
factor of four increase in the acceleration factor.
Crystal uses an activation energy of.? eY, a conservative value, compared to the .8 eV to 1.0 eV
used by some other analog IC vendors.
TEMPERATURE CHANGE
125 ~
125 ~
125 ~
135 ~
160 ~
70°C
55°C
25°C
35·C
60·C
TYPICAL ACCELERATION
FACTOR (.7 E.A.)
26.3
77.5
933.0
636
277
TABLE 2
ACCELERATION FACTORS FOR DIFFERENT
TEMPERATURES (E.A. = .7 eV)
E.A.
1.0
.9
.8
.7
.6
.5
.4
.3
ACCELERATION FACTOR
106.0
66.7
41.7
26.3
16.4
10.3
6.5
4.1
TABLE 3
ACCELERATED FACTORS FOR DIFFERENT
ACTIVATION ENERGIES (125 cC -+ 70 cC)
11-8
We now take the failure rate equation (1) at accelerated temperatures expressed in FITS and factor
in the acceleration factors from the Arrhenius relationships considering junction temperatures and
arrive at the equation below.
9
FITS = 10 N
DHFa
(5)
Using composite Crystal data through the 1st
quarter of 1988, a failure rate at 25°C can be calculated by substituting in equation (5} above:
N= 108
D-H = 28,475,272
Fa 641 (Assuming .7 eV and stress temperature
of 125°C, using junction temperature derating)
=
D-H is the summation of the devices stressed at
each readpoint multiplied by that number of stress
hours.
Substituting we get:
(109)(108)
FITS 25°C
=(28,475,272)(641) = 5.9 FITS
The Weibull distribution is often used for product
life predictions because it can describe increasing
and decreasing failure rates. Also the Weibull distribution has both a shape parameter, ~, and a
scaling parameter, ex. This is very useful in accurately describing the shape and scaling of the
"bathtub" curve. These more accurate descriptions
of the failure rate of the Weibull distribution make
REL3
.._-_
.-_
_
..--_._.
__
...-.
RELIABILITY METHODS
this method superior to the uniform failure distribution described in Equation (1). The Weibull
probability distribution function (PDF) f(t) is the
probability of failure between time t and t + dt.
In
(.-L)
=1a
lR(t)
We again take the natural logarithm and obtain:
f(t)
-(-t~)
~
= - t(~-1)e
a
(6)
a
The Weibull PDF can also be expressed as a function of the Reliability function" R(t) , and the
instantaneous failure rate function, h(t), therefore:
f(t)
=h(t)R(t)
(7)
The Reliability function is found by integrating
the Weibull PDF from t to 00. This function is the
probability that a device will survive to time t.
00
R(t) = if(t')dt' = ~
t
(t~)
a-
(8)
The instantaneous failure rate function is the
probability that a device will fail between time t
and t+dt:
h(t)
=_1 dR = ~
R dt
a
t(~-I)
(9)
The Reliability function is used to calculate the
shape parameter, 13, and the time scale parameter,
a. The shape parameter is the key function in
shaping the infant mortality portion of the "bathtub" curve. A 13 of 1 indicates a uniform failure
rate, 13 > 1 ihdicates wearout and 13 < 1 indicates a .
declining failure rate. To use Weibull statistics,
failures that occur during operating life stresses
are' used to produce values of R(t). Failure times
and R(t) values can be combined to estimate a
and 13. We, first take the natural logarithm of both
sides of equation (8).
REL3
In [ln~t) ]
=
13 In(t) - In(a)
(10)
This last equation is now in the form of a linear
function. Using linear regression techniques or
Weibull plotting paper we obtain the Weibull
shape and scale parameter. Some semiconductor
manufacturers perform a burn-in screening on devices to insure that the end customer receives a
population of devices that have minimal infant
mortality and are from the useful life period of the
reliability "bathtub" curve. It is very important to
include this data for the entire lifetime of the device to obtain an accurate curve fit for obtaining
a and 13.
Once the parameters a and ~ for the Weibull distribution are known we utilize R(t) to calculate
FITS. Crystal uses a 10 year lifetime in its FIT
calculations and typically uSes a 48 hour burn-in
at 125°C hence:
t10 = 10 yrs =87,600 hours
t1 = 48 hours
The number of devices that will fail in the ten
year lifetime following bum-in is given by:
N
=D [R(tI)- R(t1 + tl0)]
(11)
where D is the total number of devices stressed.
The number of device-hours accumulated in 10
years can be estimated by counting the devices
surviving after 10 years.
DH ;::: D • R(tI+t1O) • t10
(12)
11-9
.-....--...--------_-------
RELIABILITY METHODS
Using equation (2) for expressed failures in FITS
we obtain the equation below for a Weibull distribution
9 D [ R(tl) - R(tl + ti~)]
FITS ~ 10 D. R(tl + tlO) • (tlO)
_ 109 [ R(tI) - R (tI+tlO)]
R(tI+ tlO) • (tlO)
(13)
The above equation applies only at the stress temperature. In order to apply the equation to the
desired use temperature 'we factor in the acceleration faCtors, Fa, from the Arrhenius relationship as
it relates to time in the reliability function. Therefore in equation (12) above we replace R(tl + tlO)
by R(tI + tIofFa). Note that the device lifetime tlO
is still 10 years but the reliability function must
have the acceleration factor considered for derating to use temperature. Using composite Crystal
data through the second quarter of 1993, yields a
failure rate at 25°Cof 8.7 FITS.
This failure rate is a more accurate measure of
Crystal reliability than that provided by the constant failure rate model of equation (5).
Reliability evaluations involve only samples of an
entire population of devices. Therefore a confidence level, (CL), should be placed on the
average failure rate. At any time a sample is
stressed from a population there' exists a finite
chance of failures. If many separate samples were
stressed from the same population and failure
rates plotted, a normal distribution of failure rates
would occur. Therefore, valid statistical methods
for a normal distribution should be used to determine the desired CL. Confidence levels for
reliability analysis are expres!ied in upper confidence levels (UCL) , typically at 60% or 90%
depending on the criticality of the device's application. The total sample size stressed is critical in
defining the UCL. Therefore rather large sample
11-10
sizes must be stressed to more accurately demon"
strate the true failure rate. A larger spread
will
exist between the 60% and 90% UCL distribution
for smaller sample sizes due to the greater probability that the sample stressed was not
representative of the entire population.
Environmental stresses, such as autoclave, temperature cycling, thermal shock, storage life and
85°C/85%RH., usually have their actual results
reported, due to the lack of widely recognized
derating models. These stresses are experiments
in which a given device will either pass or fail.
Test results can be expressed as a simple failure
rate - the number of failing devices divided by the
total number of devices. However, the true failure
rate is usually very small, so often there will be
no failures observed. Instead of reporting an observed failure rate of zero, a confidence bound on
the true failure rate is determined. Crystal uses a
90% confidence level in a standard formula to determine the test results for environmental stresses.
x2 (2f+2)
FR=
'2n
(14)
The failure rate, FR, is computed by finding an
upper bound confidence interval from a standard
chi-squared table and dividing it by 2n, where n is
the number of parts in the test, and f is the number of failures observed.. X2(2f+2) is the right
endpoint of the interval starting at zero which
under the chi~squared curve
spans 90% of the'
with 2f+2degrees of freedom. This forrriula results from a Poisson approximation to the
Binomial distribution, which is appropriate when
the Binomial distribution is heavily skewed towards zero. A chi-squared value arises as an easy
way to compute Poisson probabilities. This calculation agrees with the widely accepted lot
area
REL3
---------------------tolerance percent defective, LTPD, plans that are
based on 90 % upper confidence.
Of course it is not satisfactory to have accurate
methods on reporting failure rates without having
programs and methods in place to continuously
improve the reliability of the product. Crystal uses
methodologies in every level of the company to
provide the highest possible quality and reliability
standards of its products.
RELIABILITY METHODS
For further information on a summary of Crystal's
methods of insuring high quality and reliability
standards see the Quality and Reliability information in section 1 of this data book, or contact
Crystal's Reliability and Quality Assurance Department at the factory.
In summary Crystal Semiconductor uses conservative models that are accepted throughout the
semiconductor industry to determine the reliability
of its devices and has active programs in place to
continuously improve the quality and reliability of
its devices.
REL3
11-11
----------------------
MECHANICAL DATA
MECHANICAL DATA
28 pin
Ceramic
Side-Brazed
DIP
MILLIMETERS
MAX
MIN
14.73' 15.34
35.20 I 35.92
2.54 BSC
1.40
0.76
0.53
0.38
1.52
1.02
4.32
2.79
4.57
2.54
10°
14.99 15.49
0.30
0.20
DIM
A
B
C
D
E
F
G
H
-
J
K
L
Spin
r- ---1
m:JH
Plastic DIP
B
J U~~W1J
DIM
A
B
C
D
E
F
G
H
J
K
L
M
e
D E F SEATING
M
K
PLANE
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13MM (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
16 pin
Plastic DIP
MILLIMETERS
MIN
MAX
6.10
6.60
9.14
10.2
0.38
1.52
2.54 BSe
1.02
1.78
0.38
0.53
0.51
1.02
3.81
5.08
2.92
3.43
0"
10"
7.62BSC
0.20 I 0.38
DIM
A
B
C
D
E
F
G
C D E
F
SEATING
PLANE
H
J
NOTES:
K
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
L
0.13MM (0.005") AT MAXIMUM MATERIAL CONDITION, IN
M
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
11-12
INCHES
MIN
MAX
0.580 0.604
1.386 1.414
0.100 BSC
0.030 0.055
0.015 0.021
0.040 0.060
0.110 0.170
0.100 0.180
10°
0.590 0.6tO
0.008 0.012
-
INCHES
MAX
MIN
0.240 0.260
0.360 0.400
0.015 0.060
0.100 BSe
0.040 0.070
0.015 0.021
0.020 0.040
0.150 0.200
0.115 0.135
10"
0"
0.300BSC
0.008 I 0.015
MILLIMETERS
MAX
MIN
6.10
6.60
18.80 19.30
2.89
1.32
2.54 BSC
1.78
1.02
0.53
0.38
0.51
1.02
5.08
3.81
2.92
3.43
0°
10°
7.62BSC
0.20
0.38
INCHES
MAX
MIN
0.240 0.260
0.740 0.760
0.015 0.035
0.100 BSC
0.040 0.070
0.015 0.021
0.020 0.040
0.150 0.200
0.115 0.135
0°
10°
0.300BSC
0.008 0.Q15
MD4
----------------------
MECHANICAL DATA
f~t :::::::::{~I!A
14
B
24 pin
Plastic
Skinny DIP
F
C
D
E
~I
F
J~Gti~
C D E
DIM
A
B
G
H
J
K
SEATING
PLANE
L
M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25MM (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
28 pin
Plastic DIP
DIM
A
B
C
D
E
F
G
H
J
SEATING
PLANE
K
L
M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25MM (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
MD4
MILLIMETERS
MIN
MAX
6.10
6.60
31.37 32.13
1.65
2.16
2.54BSC
1.02
1.52
0.36
0.56
1.02
0.51
3.94
4.57
2.92
3.43
0'
15'
7.62 BSC
0.20
0.38
INCHES
MAX
MIN
0.240 0.260
1.235 1.265
0.065 0.085
0.100 BSC
0.040 0.060
0.014 0.022
0.020 0.040
0.155 0.180
0.115 0.13515'
0'
0.300 BSC
0.008 0.015
MILLIMETERS
MIN
MAX
13.72 14.22
36.45 37.21
1.65
2.16
2.54 BSC
1.02
1.52
0.36
0.56
0.51
1.02
3.94
5.08
2.92
3.43
0'
15'
15.24 BSC
0.20
0.38
INCHES
MIN
MAX
0.540 0.560
1.435 1.465
0.065 0.085
0.100 BSC
0.040 0.060
0.014 0.022
0.020 0.040
0.155 0.200
0.115 0.135
0"
15'
0.600 BSC
0.008 0.Q15
11-13
-_ _-_.
.. .....,.
. ..__
.......
.., . "
MECHANICAL 'oATA
8 Pin
SOIC
DIM
A
B
C
D
E
F
e
G
H
I
-.+
KnJl_n~d ~
D ..
...
E
J
K
L
pins
16
20
24
28
SOIC
-.1 I+- B
-.I~ M
e
++-
D"
•
11-14
kHnn"dem J E
F~
G-'\I+
HfcPIIL JII~~
J
--L-+---.-
K--
DIM
A
B
C
D
E
F
G
H
I
J
K
L
M
MILLIMETERS
INCHES
MAX
MIN
MAX
MIN
5.30 0,207 0.209
5.25
1.27TYP
0.050TYP
7° NOM
7°NOM
0.120 0.180 0.005 0.007
1.86 0.071 0.073
1.80
45° NOM
45°NOM
7° NOM
7°NOM
0.195 0.205 0.0078 0.00.82
2°
4°
4°
2°
-
6.57
7.85
-
-
-
6.63
7.95
0.259
0.308
0.261
0.312
MILLIMETERS
MAX
MIN
9.91
10.41
12.45 12.95
14.99 15.50
17.53 18.03
INCHES
MIN
MAX
0.390 0.410
0.490 0.510
0.590 0.610
0.690 0.710
MILLIMETERS
MAX
MIN
INCHES
MIN
MAX
see table above
1.27
7°
0.127
2.41
45°
7°
0.203
2°
7.42
S.76
10.16
0.33
BSe
NOM
0.330
2.67
NOM
NOM
0.381
8°
7.59
9.02
10.67
0.51
0.050
7°
0.005
0.095
45°
7°
0.008
2°
0.292
0.345
0.400
0.013
BSe
NOM
0.013
0.105
NOM
NOM
0.015
SO
0.298
0.355
0.420
0.020
MD4
---------------------ITENR<;';I~~L I MIN . A
MAX
MECHANICAL DATA
I MIN
B MAX
I MIN
28
10.92
12.32
12.57 11.43 11.58 9.91
(0.485) (0.495) (0.450) (0.456) (0.390) (0.430)
44
17.40 17.65
(0.685) (0.695)
16.51
16.66
(0.650) (0.656)
r
1
1.27(0.050)
x45deg.NOM
2.41 (0.095)
MIN
T
A
28144 pin
PLCC
1'14(0:5)X45deg. ~
~
,
0.25 (0.010) R
MAX
4
B
14.98 16.00
(0.590) (0.630)
4.62 (0.18~
4.11 (0.162)
1.14 (0.045)
0.63 (0.025)
C
lTl
I
C MAX
B --'N.:..:O:.::M"---_->l1
A _ _ _ _41
~ _-""--,,",'-'n"-'rl'-'f"--""-'f"1L.-
L
~46(0.018)
.35 (0.053)
1.19 (0.047)
~33(0.Q13)
-=;:~~=-c~
0
3 NOM ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
I MIN
4.20 (0.165) Min
5.08 (0.200) Max
A MAX
~
1.07 (0.042) Min
1.42 (0.056) Max
1
x45deg.NOM
I MIN
B MAX
1~
I MIN
C MAX
I
B8pln
PLCC
0.51 (0.020)
111f
b' "
~O"
2.29 (0.090) Min 0.25 (0.010) R '
3.30 (0.130) Max
Max
~
l-
-*-C
4
B
::f-~)Min
1.219 (0.048) Max
x 45deg. Nom
A
~33 (0.013 )Mln
~53 (0.021) Max
-=;::::Jt:=~-='!:)
3 NOM
0
MD4
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
11-15
----------------------
MECHANICAL DATA
44 PIN QUAD FLATPACK
44 Pin TQFP
1.4 mm Package Thickness
INCHES
MILLIMETERS
MIN
MIN
MAX
MAX
DIM
11.75
12.25
9.90
10.10
70
00
0.80 BSe
0.35 BSe
120
0.54
0.74
0.54
0.74
1.50
1.35
0.05
1.60
0.17
20
10 0
0.35
0.65
A
B
C
D
E
F
G
H
I
J
I-~L
M
N
0.463
0.390
00
0.031
0.014
0.021
0.021
0.053
0.002
20
0.014
0.482
0.398
70
BSe
BSe
12 0
0.029
0.029
0.059
0.063
0.007
100
0.026
F
*
+
N
0.102 MAX
Lead eoplanarity
A
B
A
B
;gO
~.---.L
~~
e
11·16
G
H
D
MD4
_.-_..--_._.
__.._-_
...-.
MECHANICAL DATA
A
S
100-pin TQFP
DIM
A
B
C
D
E
F
G
A
S
H
I
J
MILLIMETERS
MAX
MIN
15.75 16.25
13.90 14.10
0.50 sse
0.10
0.20
1.25
1.55
0.00
0.20
1.00 sse
0.35
0.65
0.077 0.177
0°
10°
INCHES
MAX
MIN
0.620
0.547
0.020
0.004
0.049
0.000
0.039
0.014
0.003
0°
0.640
0.555
sse
0.012
0.061
0.008
sse
0.026
0.007
10°
§o
1
e
MD4
D
11-17
_.-_..---.-.
__.._-_
...-.
MECHANICAL·DATA
• Notes •
11-18
MD4
----------- -----------
AUDIO DATA BOOK CONTENTS
GENERAL INFORMATION
DIGITAL-TO-ANALOG CONVERTERS
ANALOG-TO-DIGITAL CONVERTERS
COMBINED AID & DIA CONVERTERS (CODECS)
Serial Interface
Parallel ISA Bus Interface
Software
DIGITAL SIGNAL PROCESSORS
Audio Decoder & D/A Converter
Synthesizers
DIGITAL AUDIO INTERFACES
AES/EBU & SPDIF Transmitters & Receivers
SPDIF & A-LAN Transceiver
SUPPORT FUNCTION PRODUCTS
Power Monitor
Volume Control
APPLICATION NOTES & PAPERS
DATA ACQUISITION PRODUCTS
General Purpose & Military
Seismic
DC Measurement & Transducer Interface
COMMUNICATIONS PRODUCTS
T1/CEPT Line Interfaces, Framers & Jitter Attenuators
Local Area Network
APPENDICES
Reliability Calculation Methods
Package Mechanical Drawings
SALES OFFICES
12
12-1
------------.----------
SALES OFFICES
CONTENTS
12-2
Crystal Area Sales Offices
12-3
United States Representatives
12-3
United States Distributors
12-7
Canada Representatives
12-8
Europe Representatives
12-9
Far East Representatives
12-11
.._-_
.-_
._.-.
_
..--__
...
SALES OFFICES/REPRESENTATIVES
UNITED STATES
SALES OFFICES
WESTERN AREA
CENTRAL AREA
EASTERN AREA
Sales Office and
Applications Support:
Crystal Semiconductor Corp.
50 Airport Parkway
San Jose, CA 95110
Ph: 408-437-7743
FAX: 408-437-4943
Crystal Semiconductor Corp.
4210 So. Industrial Dr.
Austin, TX 78744
Ph: 512-445-7222
FAX: 512-445-7581
Crystal Semiconductor Corp ..
8601 Six Forks Rd., Suite 703
Raleigh, NC 27615
Ph: 919-846-4832
FAX: 919-846-4839
Crystal Semiconductor Corp.
Salem Business Center
68 Stiles Road
Salem, NH 03079
Ph: 603-894-5544
FAX 603-894-5533
Crystal Semiconductor Corp.
27281 Las Ramblas, Suite 200
Mission Viejo, CA 92691
Ph: 714-348-8770
FAX: 714-348-9556
SALES REPRESENTATIVES
ALABAMA
CAliFORNIA
COLORADO
CP&F, Inc.
2317 Starmount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558
Earle Associates, Inc.
7585 Ronson Road, Suite 200
San Diego, CA 92111
Ph: 619-278-5441
FAX: 619-278-5443
Easylink: 62835672
PromoTech
2901 S. Colorado Blvd., Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416
ALASKA
Bager Electronics
17220 Newhope St., Suite 209
Fountain Valley, CA 92708
Ph: 714-957-3367
FAX: 714-546-2654
Alpha-Omega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
B ager Electronics
6324 Variel Avenue, Suite 314
Woodland Hills, CA 91367
Ph: 818-712-0011
FAX: 818-712-0160
DELAWARE
CONNECTICUT
Electronic Engineering Sales
17020 S.w. Upper Boones Ferry Rd.,
Suite 301
Portland, OR 97224
Ph: 503-639-3978
FAX: 503-684-3326
ARIZONA
Western High Tech Marketing, Inc.
9414 E. San Salvador, Suite 206
Scottsdale, AZ 85258
Ph: 602-860-2702
FAX: 602-860-2712
ARKANSAS
TL Marketing, Inc.
14850 Quorum Dr., #100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-960-6075
NORCOMP, Inc.
1267 Oakmead Pkwy
Sunnyvale, CA 94086
Ph: 408-733-7707
FAX: 408-774-1947
NORCOMP, Inc.
8880 Wagon Way
Granite Bay, CA 95746
Ph: 916-791-7776
FAX: 916-791-2223
Vantage Sales Company
1930 E. Marlton Pike
Cherry Hill, NJ 08003
Ph: 609-424-6777
FAX: 609-424-8909
DISTRICT OF COLUMBIA
New Era Sales, Inc.
890 Airport Park Rd. Suite #103
Glen Burnie, MD 21061-2559
Ph: 410-761-4100
FAX: 410-761-2981
12-3
_.-_..__.._-_.
...
.......
SALES RI;~RESENTATIVES
~--
FLORIDA
INDIANA
MARYLAND
CP&F Florida, Inc.
7335 Lake Ellenor Drive
P.O. Box 593229
Orlando, FL 32809·6219
Ph: 407-855-0843
FAX: 407-851-1464
TMC Electronics
1526 E. Greyhound Pass
Carmel, IN 46032-1036
Ph: 317-844-8462
FAX: 317-573-5472
New Era Sales, Inc.
890 Airport Park Rd. Suite #103
Glen Burnie, MD 21061-2559
Ph: 410-761-4100
FAX: 410-761-2981
TMC Electronics
4630-10 W. Jefferson Blvd.
Ft. Wayne, IN 46804-6800
Ph: 219-432-5553
FAX: 219-432-5555
MASSACHUSETTS
GEORGIA
CP&F Florida, Inc.
2866 Buford Hwy.
Duluth, GA 30136
Ph: 404-497-9404
FAX: 404-497-9412
Call Crystal Head Office
Ph: 512-445-7222
TMC Electronics
1214 Appletree Lane
Kokomo, IN 46902-5701
Ph: 317-459-5152
FAX: 317-457-3822
IDAHO
IOWA
HAWAII
Anderson Associates
270 South Main Street, Suite 108
Bountiful, UT 84010
Ph: 801-292-8991
FAX: 801-298-1503
Stan Clothier Co.
1930 St. Andrews N.E.
Cedar Rapids, IA 52402
Ph: 319-393-1576
FAX: 319-393-7317
KANSAS
Electronic Engineering Sales
17020 S.W. Upper Boones Ferry Rd,
Suite 301
Portland, OR 97224
Ph: 503-639-3978
FAX: 503-684-3326
Stan Clothier Co.
13000 West 87th St. Pkwy #105
Lenexa, KS 66215
Ph: 913-492-2124
FAX: 913-492-1855
ILliNOIS
KENTUCKY
Micro Sales Inc.
901 W. Hawthorn
Itasca, IL 60143
Ph: 708-285-1000
FAX: 708-285-1008
T MC Electronics
718 Amherst Place
Louisville, KY 40223-3486
Ph: 502-245-7411
FAX: 502-245-4818
Stan Clothier Co.
3910 Old Hwy. 94 S.
Suite 116
St. Charles, MO 63304
Ph: 314-928-8078
FAX: 314-447-5214
LOUISIANA
TL Marketing, Inc.
14343 Torrey Chase Blvd, Suite 1
Houston, TX 77014
Ph: 713-587-8100
fAX: 713-580-7517
MAINE
Alpha-Omega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
Alpha-Omega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
MICHIGAN
J.M.J. & Associates, Inc.
5075 Cascade Rd. S.E.
Grand Rapids MI 49546
Ph: 616-285-8887
FAX: 616-285-7633
MINNESOTA
The Twist Company
12800 Industrial Park Blvd. ,Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-550-0925
MISSISSIPPI
CP&F, Inc.
2317 Starrnount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558
MISSOURI
Stan Clothier Co.
3910 Old Hwy. 94 S.
Suite 116
St. Charles, MO 63304
Ph: 314-928-8078
FAX: 314-447-5214
.._-_.
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SALES REPRESENTATIVES
MONTANA
NEW YORK
OHIO
Electronic Engineering Sales
8405 165th Avenue NE
RedlIlond, VVA 98052
Ph: 206-883-3374
Fax: 206-882-1347
Nexus Technology Sales
2460 LelIloine Ave
Fort Lee NJ 07024
Ph: 201-947-0151
FAX: 201-947-0163
TMC Electronics
7838 Laurel Ave.
Cincinnati, OH 45243-2609
Ph: 5l3-271-3860
FAX: 5l3-271-6321
ProlIloTech
2901 S. Colorado Blvd., Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416
Bob Dean, Inc.
2415 North TriphalIllIler Road
P.O. Box E
Ithaca, NY 14851
Ph: 607-257-1111
FAX: 607-257-3678
TMC Electronics
7017 Pearl Road
Middleburg Heights, OH 44130-8406
Ph: 216-885-5544
FAX: 216-885-5011
NEBRASKA
Stan Clothier Co.
l3000 VVest 87th St. Pkwy #105
Lenexa, KS 66215
Ph: 9l3-492-2124
FAX: 9l3-492-1855
NEVADA
NORCOMP, Inc.
3350 Scott Blvd., #24
Santa Clara, CA 95054
Ph: 408-727-7707
FAX: 408-986-1947
OKLAHOMA
Bob Dean, Inc.
Suite lD, Hollowbrook Park
15 Myers Comer Road
VVappingers Falls, NY 12590
Ph: 914-297-6406
FAX: 914-297-5676
NORTH CAROLINA
CPF Atlantic, Inc.
1 Centerview Drive, Ste 306
Greensboro, NC 27407
Ph: 919-852-4498
FAX: 919-852-4556
TL Marketing, Inc.
14850 QUOrulIl Dr., #100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-960-6075
OREGON
Electronic Engineering Sales
17020 S.W Upper Boones Ferry Rd.,
Suite 301
Portland, OR 97224
Ph: 503-639-3978
FAX: 503-684-3326
NEW HAMPSHIRE
Alpha-OlIlega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
PENNSYLVANIA
TMC Electronics
7017 Pearl Road
Middleburg Heights, OH 44l30-8406
Ph: 216-885-5544
FAX: 216-885-5011
NEW JERSEY (NORTH)
Nexus Technology Sales
2460 LelIloine Ave
Fort Lee N.J. 07024
Ph: 201-947-0151
FAX: 201-947-0163
Vantage Sales COlIlpany
1930 E. Marlton Pike
Cherry HilI, NJ 08003
Ph: 609-424-6777
FAX: 609-424-8909
NEW JERSEY (SOUTH)
Vantage Sales COlIlpany
1930 E. Marlton Pike
Cherry HilI, NJ 08003
Ph: 609-424-6777
FAX: 609-424-8909
12-5
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SALES REPRESENTATIVES
RHODE ISLAND
TEXAS
WASHINGTON
Alpha-Omega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
TL Marketing, Inc.
8100 Shoal Creek, Suite 250
Austin, TX 78758
Ph: 512-371-7272
FAX: 512-371-0727
Electronic Engineering Sales
11200 Kirkland Way #103
Kirkland, WA 98033
Ph: 206-889-2988
FAX: 206-889-2998
SOUTH CAROLINA
TL Marketing, Inc.
14343 Torrey Chase Blvd., Suite 1
Houston, TX 77014
Ph: 713-587-8100
FAX: 713-580-7517
CPF Atlantic, Inc.
1 Centerview Dr.
Suite 306
Greensboro, NC 27407
Ph: 919-218-0800
FAX: 919-218-0710
SOUTH DAKOTA
The Twist Co.
12800 Industrial Park Blvd., Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-550-0925
TENNESSEE (WEST)
CP&F, Inc.
2317 Starmount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558
TENNESSEE (EAST)
CP&F, Florida
2866 Buford Hwy.
Duluth, GA 30136
Ph: 404-497-9404
FAX: 404-497-9412
12-6
TL Marketing
14850 Quorum Dr., #100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-960-6075
UTAH
Anderson Associates
270 South Main Street, Suite 108
Bountiful, UT 84010
Ph: 801-292-8991
FAX: 801-298-1503
VERMONT
Alpha-Omega Sales Corp.
325 Main St, Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212
VIRGINIA
New Era Sales, Inc.
801 West Main Street
Charlottesville, VA 22901
Ph: 804-979-2470
FAX: 804-979-2958
WEST VIRGINIA
TMC Electronics
7838 Laurel Ave.
Cincinnati, OH 45243-2609
Ph: 513-271-3860
Fax: 513-271-6321
WISCONSIN (S.E.)
Micro Sales, Inc.
210 Regency Ct., Suite L101
Waukesha, WI 53186
Ph: 414-786-1403
FAX: 414-786-1813
WISCONSIN (N. w.)
The Twist Co.
12800 Industrial Park Blvd.
Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-550-0925
WYOMING
PromoTech
2901 S. Colorado Blvd.
Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416
----------------------
SALES REPRESENTATIVES
U. S. DISTRIBUTORS
ALABAMA
COLORADO
MICHIGAN
Reptron Electronics, Inc.
4835 University Square, Suite 12
Huntsville, AL 35816
Ph: 205-722-9500
.FAX: 205-722-9565
Insight Electronics
384 Inverness Dr. So #105
Englewood, CO 80112
Ph: 303-649-1800
FAX: 303-649-1818
(Detroit)
Reptron Electronics
34403 Glendale
Livonia, MI48150
Ph: 313-525-2700
FAX: 313-525-3209
Nu Horizons Electronics
4801 University Sq, Suite 11
Huntsville, AL 35816
Ph: 205-722-9330
FAX: 205-722-9348
FLORIDA
Nu Horizons Electronics
3421 N.W. 55th St.
Fort Lauderdale, FL 33309
Ph: 305-735-2555
FAX: 305-735-2880
ARIZONA
Insight Electronics
Tempe,AZ
1515 W. University Drive, Suite 103
Tempe, AZ 85281
Ph: 602-829-1800
Ph: 602-792-1800 (Tucson)
Ph: 505-823-1800 (New Mexico)
FAX: 602-967-2658
CALIFORNIA
(Los Angeles)
Insight Electronics
4333 Park Terrace Dr. #101
West Lake Village, CA 91361
Ph: 818-707-2101 (San Fernando
Valley)
FAX: 818-707-0321
(Orange County)
Insight Electronics, Inc.
Two Venture Plaza, Suite 340
Irvine, CA 92718
Ph: 714-727-3291
FAX: 714-727-1804
Insight Electronics
6885 Flanders Drive
San Diego, CA 92121
Ph: 619-587-1100
FAX: 619-587-1380
Insight Electronics
1295 Oakmead Pkwy
Sunnyvale, CA 94086
Ph: 408-720-9222
FAX: 408-720-8390
Nu-Horizons Electronics
600 South North Lake Blvd.,Suite 270
Altamonte Springs, FL 32701
Ph: 407-831-8008
FAX: 407-831-8862
GEORGIA
Nu Horizons Electronics
5555 Oakbrook Pkwy, Suite 340
Norcross, GA 30093
Ph: 404-416-8666
FAX: 404-416-9060
ILLINOIS
(Chicago)
Reptron Electronics
1000 E. State Parkway, Suite K
Schaumburg, IL 60173
Ph: 708-882-1700
FAX: 708-882-8904
MINNESOTA
(Minneapolis)
Reptron Electronics
5929 Baker Road
Minnetonka, MN 55345
Ph: 612-938-0000
FAX: 612-938-3995
NEW JERSEY
Nu-Horizons Electronics
39 U.S. Route 46
Pine Brook, NJ 07058
Ph: 201-882-8300
FAX: 201-882-8398
Nu- Horizons Electronics
18000 Horizon Way #200
Mount Laurel, NJ 08054
Ph: 609-231-0900
FAX: 609-231-9510
NEW YORK
Nu-Horizons Electronics
6000 New Horizons Blvd.
North Amityville, NY 11701
PH: 516-226-6000
FAX: 516-226-6140
MARYLAND
Nu-Horizons Electronics
8975 Guilford Road, Suite 120
Columbia, MD 21046
Ph: 410-995-6330
FAX: 410-995-6332
Nu-Horizons Electronics
333 Metro Park
Rochester, NY 14623
Ph: 716-292-0777
FAX: 716-292-0750
MASSACHUSETTS
Nu-Horizons Electronics
19 Corporate Place
107 Audubon Road, Bldg. 1
Wakefield, MA 01880
Ph: 617-246-4442
FAX: 617-246-4462
12-7
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SALES REPRESENTATIVES
U. S. Distributors (Cont.)
NORTH CAROLINA
OREGON
TEXAS
Reptron Electronics
5954-A Six Forks Rd.
Raleigh, NC 27609
Ph: 919-870-5189
FAX: 919-870-5210
Insight Electronics
8705 S.w. Numbus, Suite 200
Beaverton, OR 97005
Ph: 503-644-3300
FAX: 503-641-4530
(Dallas)
Insight Electronics
1778 N. Plano Road, Suite 320
Richardson, TX 75081
Ph: 214-783-0800 (Richardson)
Ph: 817-338-0800 (Ft. Worth)
FAX: 214-680-2402
OHIO
(Cleveland)
Reptron Electronics
30640 Bainbridge Rd.
Solon, OH 44139
Ph: 216-349-1415
FAX: 216-349-1634
Insight Electronics
15437 McKaskle
Sugarland, TX 77478
Ph: 713-448-0800
Insight Electronics
12701 Research Blvd,Suite 301
Austin, TX 78759
Ph: 512-331-5887
FAX: 512-331-5811
WASHINGTON
Insight Electronics
12002 115th Ave. N.E.
Kirkland, WA 98034
Ph: 206-820-8100
FAX: 206-821-2976
CANADA
BRITISH COLUMBIA
ONTARIO
QUEBEC
MICROWE Electronics Corp.
5330 Wallace Ave.
Delta, BC
Canada, V4M lAI
Ph: 604-943-5020
FAX: 604-943-8184
InTELaTECH inc
1115 Crestlawn Dr., Suite 1
Mississauga, Ontario
Canada, L4W lA7
Ph: 416-629-0082
FAX: 416-629-1795
InTELaTECH inc
29Charlevoix
Kirkland, Quebec
Canada, H9J 2S4
Ph: 514-630-6041
FAX: 514-630-5612
275 Michael Copeland Dr.
Kanata, Ontario
Canada, K2M 2G2
Ph: 613-253-1369
FAX: 613-253-1370
12-8
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...
SALES REPRESENTATIVES
EUROPE
Europe Sales Office
and Applications Support:
Crystal Semiconductor (UK) Ltd.
Lyons House
2 Station Road
Frimley
Surrey GU165HF
Ph: +44(0276)685761
FAX: +44(0276)691090
Crystal Semiconductor
Muhlfelder-Strasse 2
D-82211 Herrsching
Germany
Ph: +49(815)22030
FAX: +49(815)240077
AUSTRIA
FRANCE
ITALY
Eurodis Electronics GmbH
Lamezanstrasse 10
A-1232 Wien
Austria
Ph: +43(1)61062-0
FAX: +43(1)61062151
Newtek S. A.
8, Rue De L'Esterel
Silic 583
94663 Rungis Cedex
France
Ph: +33(01468)72200
FAX: +33(014687)8049
TLX: 842-263046
Newtek Italia S.p.A.
Via G. Da Procida 10
20149 Milano
Italy
Ph: +39(233)105308
FAX: +39(233)103694
BEWIUM & LUXEMBOURG
Alcorn Electronics NYISA
Singe! 3
2550 Kontich
Belgium
Ph: +32(0345)83033
FAX: +32(0345)83126
DENMARK
Scansupply A/S
Gladsaxevej 356
DK-2860 Soborg,
Denmark
Ph: +45(039)665090
FAX: +45(039)665040
Scansupply A/S
Marselisborg
Havnevej 36
DK-8oo0 Aarhus C
Denmark
Ph: +45 86 127788
FAX+45 86 127718
FINLAND
Integrated Electronics OyAB
Turkhaudantie 1
SF-00700 Helsinki
Finland
Ph: +358(0)3513133
FAX: +358(0)3513134
Newtek Sud-Est
4, Rue de l'Europe
ZAC Font-Ratel
38640 CLAIX
France
Ph: +33(076)985601
FAX: +33(076)981604
GERMANY
Atlantik Elektronik GmbH
Fraunhoferstrasse, llA
82152 Planegg
Germany
Ph: +49(089)8570000
FAX: +49(089)8573702
TLX: 841-521-5111
Atiantik Elektronik GmbH
Steindamm 39
2000 Hamburg 1
Germany
Ph: +49 (040) 241072
FAX: +49 (040) 241074
ISRAEL
Telsys
Atidim Industrial Park Bldg. 3
Dvora Hanevia St., Neve Sharet,
Tel-Aviv 61431, Israel
Ph: +972(03)492001
TLX: 32392 and 371279
FAX: +972(03)497407
NORWAY
NC ScandComp Norway AS
Aslakveien 20F
.
0753 Oslo
Norway
Ph: +47(22)500650
FAX: +47(22)502777
SPAIN & PORTUGAL
Amitron SA
Avda De Valladolid, 47, D
28008 Madrid
Spain
Ph: +34(91)5420906
FAX: +34(91)2487958
HOLLAND
Alcorn Electronics BV
Essebaan 1
2900 AI Capelle AID DSSEL
Holland
Ph: +31(010)4519533
FAX: +31(010)4586482
12-9
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_................
SALES REPRESENTATIVES
EUROPE (Cont.)
SWEDEN
SWITZERLAND
UNITED KINGDOM
Ab Gosta Backstrom
Aistromergatan 22
P.O. Box 12009
10221 Stockholm
Sweden
Ph: +46(086541)080
FAX: +46(086531)251
TLX: 10135
MemotecAG
Gaswerkstrasse 32
P. O. Box
4901 Langenthal
Switzerland
Ph: +41(063)281-122
FAX: +41(063)223-506
TLX: 845-982550
Sequoia Technology Ltd.
Unit 5
Bennet Place
Bennet Road
Reading
Berks RG2 OQX
United Kingdom
Ph: +44(0734)311822
FAX: +44(0734)312676
FAR EAST
AUSTRAliA
JAPAN
TAIWAN
ACD (N.S.W.)
Unit 1,106 Belmore Rd. Nth.
P. O. Box 402
Riverwood, N. S. W. 2210, Australia
Ph: +61(02)534-6200
TLX: AA121398
FAX: +61(02)534-4910
Asahi Kasei Microsystems Co., Ltd.
T5 Bldg.
24-10, Yoyogi l-Chome,
Shibuya-ku, Tokyo, Japan
Ph: +81(03)320-2070
FAX:+ 81(03)320-2078
TLX: 222-2792 - AKMC J
Cirrus Logic International Ltd.
Taiwan Branch
IOF, No.214 Tun Hwa North Road
Taipei,
Taiwan RO.C.
Ph: +886(02)718-4533
FAX: +886(02)718-4526
ACD (Pegasus)
Unit 2, 17-19 Melrich Road
Bayswater, Victoria, 3153, Australia
Ph: +61(03)762-7644
FAX: +61(03)762-5446
Cirrus Logic K.K.
Shinjuku Green Tower Bldg. 26F
6-14-1 Nishi-Shinjuku,
Shinjuku-ku,
Tokyo 160
Ph: +81(03)3340-9111
FAX: +81(03)3340-9120
Morrihan International Corp.
8F-5 No. 57 Fu-Hsing N. Rd.,
Taipei,
Taiwan, R O. C.
Ph: +886(02)752-2200
FAX: +886(02)741-4690
TLX: 20422 MORRIHAN
Taichung Branch
Ph: +886(04)224-6666
FAX:+886(02)741-4690
ACD (Queensland)
1048 Beaudesert Road
Coopers Plains, Queensland, 4108,
Australia
Ph: +61(07) 875-1113
FAX:+61(07)275-3662
HONG KONG
CETLtd.
22fF Chuang's Finance Centre
81-85 Lockhart Road
Hong Kong
Ph: (852)520-0922
FAX: (852)865-0639
12-10
KOREA
Hanaro Corp.
Hana Bldg, 122-30 Chungdam-Dong
Gangnam-Ku, Seoul, Korea 135-100
Youngdong P. O. Box 1588 Seoul, Korea 135-615
Ph: +82(02)516-1144
FAX: +82(02)516-1151
TLX: K26376 HANARO
MAlAYSIA
DCP (M) SDN BHD
6th Floor, Wisma Denko
41, Aboo Sitee Lane
10400 Penang, Malaysia
Ph: +604-281860
FAX: +604-281420
SINGAPORE
Dynamar Computer Products, Pte Ltd.
109 Defu Lane 10
Singapore 1953
Ph: +65-281-3388
FAX: +65-281-3308
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