1994_Cypress_Programmable_Logic_Data_Book 1994 Cypress Programmable Logic Data Book

User Manual: 1994_Cypress_Programmable_Logic_Data_Book

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Programmabl
Logi

l

Programmable logic
Data Book
1994/1995

~

~~YPRESS===============================
How To Use This Book
Overall Organization

Key to Waveform Diagrams

This book has been organized by product type, beginning with Product Information. The products are
next, starting with Small PLDs, then CPLDs, FPGAs,
and Software. A section containing Quality and Reliability is next, followed by a Package Diagrams section. Within each section, data sheets are arranged in
order of part number.

Rising edge of signal will
occur during this time.
Falling edge of signal will
occur during this time.

Recommended Search Paths

To search by:

Use:

Product line

Table of Contents or flip
through the book using the
tabs on the right-hand pages.

Size

The Product Selector Guide
in section l.

Numeric part number Numeric Device Index. The
book is also arranged in order of part number.

Signal may transition
during this time (don't
care condition).
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
state during this time.

Other manufacturer's The Cross Reference Guide
part number
in section l.
Military part number

The Military Selector Guide
in section 1.

Published July 7, 1994
All trademarks listed herein are of their respective companies.

© Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it conveyor imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant
injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes ali risk of such use and in so doing indemnifies
Cypress Semiconductor against ali damages.

~

Table of Contents

....... ?cYPRESS
Table of Contents

Page Number

General Product Information
Cypress Semiconductor Background ......................................................................... 1-1
Ordering Information ..................................................................................... 1-4
Cypress Semiconductor Bulletin Board System (BBS) Announcement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Application Notes Listing .................................................................................. 1-6
Product Selector Guide .................................................................................... 1-7
Product Line Cross Reference .............................................................................. 1-9
Military Overview ...................................................................................... " 1-14
Military Product Selector Guide .......................................................................... " 1-15
Military Ordering Information ............................................................................. 1-17

Small PLDs (Programmable Logic Devices)
Introduction to Cypress PLDs
Device
PAL20 Series
PALC20 Series
PALCE16V8
PALCE20V8
PLDC20G10
PLDC20GlOB
PLD20GI0C
PLDC20RAlO
PALC22VlO
PALC22VlOB
PAL22VlOC
PAL22VPlOC
PAL22VlOCF
PAL22VPlOCF
PALC22VlOD
PAL22VlOG
PAL22VPlOG
CY7C330
CY7C331
CY7C332
CY7C335
CY7C258
CY7C259

2-1
Description
4.5-ns, Industry-Standard PLDs 16L8, 16R8, 16R6, 16R4 ............................ 2-6
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
Flash Erasable, Reprogrammable CMOS PAL Device ............................ " 2-30
Flash Erasable, Reprogrammable CMOS PAL Device ............................ " 2-38
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-39
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-39
Generic 24-Pin PAL Device .................................................. " 2-47
Reprogrammable Asynchronous CMOS Logic Device ............................. 2-57
Reprogrammable CMOS PAL Device ........................................... 2-68
Reprogrammable CMOS PAL Device ........................................... 2-69
Universal PAL Device ........................................................ 2-70
Universal PAL Device ........................................................ 2-70
Universal PAL Device ........................................................ 2-81
Universal PAL Device ........................................................ 2-81
Flash Erasable, Reprogrammable CMOS PAL Device ............................ " 2-82
Universal PAL Device ........................................................ 2-91
Universal PAL Device ........................................................ 2-91
CMOS Programmable Synchronous State Machine ....................... . . . . . . .. 2-101
Asynchronous Registered EPLD .............................................. 2-112
Registered Combinatorial EPLD .............................................. 2-126
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-136
2K x 16 Reprogrammable State Machine PROM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151
2K x 16 Reprogrammable State Machine PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151

CPLDs (Complex PLDs)
Device
CY7C340 EPLD Family
CY7C341
CY7C341B
CY7C342
CY7C342B
CY7C343
CY7C343B
CY7C344
CY7C344B
CY7C346
CY7C346B

Description
Multiple Array Matrix High-Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
192-Macrocell MAX EPLD ..................................................... 3-7
192-Macrocell MAX EPLD ..................................................... 3-7
128-Macrocell MAX EPLD .................................................... 3-24
128-Macrocell MAX EPLD .................................................. " 3-24
64-Macrocell MAX EPLD ..................................................... 3-42
64-Macrocell MAX EPLD ................................................... " 3-42
32-Macrocell MAX EPLD ..................................................... 3-58
32-Macrocell MAX EPLD " ................................................. " 3-58
128-Macrocell MAX EPLD .................................................... 3-73
128-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -73
iii

Table of Contents
CPLDs (Complex PLDs) (continued)
Device
CY7C361
FLASH370 CPLD Family
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
CY7C376
CY7C377
CY7C378
CY7C379

Page Number

Description
Ultra High Speed State Machine EPLD ......................................... 3-91
High-Density Flash CPLDs .......................... , ......................... 3-92
32-Macrocell Flash CPLD ..................................................... 3-99
64-Macrocell Flash CPLD .................................... . . . . . . . . . . . . . . .. 3 -107
64-Macrocell Flash CPLD .................................................... 3-115
128-Macrocell Flash CPLD ................................................... 3-125
128-Macrocell Flash CPLD ................................................... 3-135
192-Macrocell Flash CPLD ................................................... 3-146
192-Macrocell Flash CPLD ................................................... 3-147
256-Macrocell Flash CPLD ................................................... 3-148
3-149
256-Macrocell Flash PLD

FPGAs (Field Programmable Gate Arrays)
Device
pASIC380 Family
CY7C381A
CY7C382A
CY7C3381A
CY7C3382A
CY7C383A
CY7C384A
CY7C385A
CY7C386A
CY7C387A
CY7C388A
CY7C389A

Description
Very High Speed CMOS FPGAs ................................................ 4-1
Very High Speed lK (3K) Gate CMOS FPGA ..................................... 4-8
Very High Speed lK (3K) Gate CMOS FPGA ......... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8
3.3V High Speed lK (3K) Gate CMOS FPGA ... . . . . . . . . . .. . . .. . . . .. . .. . . .. .. .. .. 4-17
3.3V High Speed lK (3K) Gate CMOS FPGA ................................... , 4 -17
Very High Speed 2K (6K) Gate CMOS FPGA .................................... 4-25
Very High Speed 2K (6K) Gate CMOS FPGA .................................... 4-25
Very High Speed 4K (12K) Gate CMOS FPGA .................................. , 4-34
Very High Speed 4K (12K) Gate CMOS FPGA ................................... 4-34
Very High Speed 8K (24K) Gate CMOS FPGA .. .. . . . . . . . .. .. .. . . .. . .. . . . .. . . .. .. 4-45
Very High Speed 8K (24K) Gate CMOS FPGA .................................. , 4-45
Very High Speed 12K (36K) Gate CMOS FPGA .................................. 4-56

Software
PLD, CPLD, and FPGA Development Tools Overview .......................................................... 5-1
Device
Description
Warp2 CY3120/CY3125
VHDL Compiler for PLDs, CPLDs, and FPGAs ................................... 5-2
Warp3 CY3130/CY3135
VHDL Development System for PLDs and FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
Impulse3
Device Programer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
Third-Party Tools ........................................................................................ 5-14

Quality and Reliability
PLD Programming Information ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
pASIC380 Family Reliability Report ......................................................................... 6-3
Power Characteristics of Cypress Programmable Logic Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-12
Quality, Reliability, and Process Flows ...................................................................... 6-20
Thpe and Reel Specifications .............................................................................. , 6-35

Packages
Thermal Management and Component Reliability ............................................................. 7-1
Package Diagrams ........................................................................................ 7 - 8

Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
iv

Numeric Device Index
Page Number

Device Number

Description

CY3120/CY3125
CY3130/CY3135
CY7C330
CY7C331
CY7C332
CY7C335
CY7C258
CY7C259
CY7C340 EPLD Family
CY7C341
CY7C341B
CY7C342
CY7C342B
CY7C343
CY7C343B
CY7C344
CY7C344B
CY7C346
CY7C346B
CY7C361
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
CY7C376
CY7C377
CY7C378
CY7C379
CY7C381A
CY7C382A
CY7C3381A
CY7C3382A
CY7C383A
CY7C384A
CY7C385A
CY7C386A
CY7C387A
CY7C388A
CY7C389A
FLASH370 CPLD Family
Impulse3
PAL20 Series
PALC20 Series
PAL22VlOC
PAL22VPlOC
PAL22VlOCF
PAL22VPlOCF
PAL22VI0G
PAL22VPlOG
PALC22VlO
PALC22VlOB

Wmp2 VHDL Compiler for PLDs, CPLDs, and FPGAs ............................. 5-2
Warp3 VHDL Development System for PLDs and FPGAs ........................... 5-7

CMOS Programmable Synchronous State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-101
Asynchronous Registered EPLD .............................................. 2-112
Registered Combinatorial EPLD .............................................. 2-126
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-136
2K x 16 Reprogrammable State Machine PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151
2K x 16 Reprogrammable State Machine PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151
Multiple Array Matrix High-Density EPLDs ....................................... 3-1
192-Macrocell MAX EPLD ..................................................... 3-7
192-Macrocell MAX EPLD ..................................................... 3-7
128-Macrocell MAX EPLDs ................................................... 3-24
128-Macrocell MAX EPLDs ................................................... 3-24
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-42
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-42
32-Macrocell MAX EPLD ..................................................... 3-58
32-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-58
128-Macrocell MAX EPLDs ................................................... 3-73
128-Macrocell MAX EPLDs ................................................... 3-73
Ultra High Speed State Machine EPLD ......................................... 3-91
32-Macrocell Flash CPLD ..................................................... 3-99
64-Macrocell Flash CPLD ........................................... . . . . . . . .. 3 -107
64-Macrocell Flash CPLD .................................................... 3-115
128-Macrocell Flash CPLD ................................................... 3-125
128-Macrocell Flash CPLD ................................................... 3-135
192-Macrocell Flash CPLD ................................................... 3-146
192-Macrocell Flash CPLD ................................................... 3-147
256-Macrocell Flash CPLD ................................................... 3-148
256-Macrocell Flash PLD .................................................... 3-149
Very High Speed lK (3K) Gate CMOS FPGA ..................................... 4-8
Very High Speed lK (3K) Gate CMOS FPGA ..................................... 4-8
3.3V High Speed lK (3K) Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-17
3.3V High Speed lK (3K) Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-17
Very High Speed 2K (6K) Gate CMOS FPGA .................................... 4-25
Very High Speed 2K (6K) Gate CMOS FPGA .................................... 4-25
Very High Speed 4K (12K) Gate CMOS FPGA ................................... 4-34
Very High Speed 4K (12K) Gate CMOS FPGA ................................... 4-34
Very High Speed 8K (24K) Gate CMOS FPGA ................................... 4-45
Very High Speed 8K (24K) Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-45
Very High Speed 12K (36K) Gate CMOS FPGA .................................. 4-56
High-Density Flash CPLDs .................................................... 3-92
Device Programer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
4.5-ns, Industry-Standard PLDs 16L8, 16R8, 16R6, 16R4 ............................ 2-6
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
Universal PAL Device
2-70
Universal PAL Device
2-70
Universal PAL Device
2-81
2-81
Universal PAL Device
2-91
Universal PAL Device
Universal PAL Device ........................................................ 2-91
Reprogrammable CMOS PAL Device ........................................... 2-68
Reprogrammable CMOS PALR Device .......................................... 2-69
v

Numeric Device Index
Device Number

Description

PALC22V10D
PALCE16V8
PALCE20V8
pASIC380 Family
PLDC20GlO
PLDC20G10B
PLD20G1OC
PLDC20RA10

Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-82
Flash Erasable, Reprogrammable CMOS PAL Device .......... ; . . . . . . . . . . . . . . . . . .. 2-30
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-38
Very High Speed CMOS FPGAs ................................................ 4-1
CMOS Generic 24-Pin Reprogrammable Logic Device .............. '............... 2-39
CMOS Generic 24-Pin Reprogrammable Logic Device. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-39
Generic 24-Pin PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
Reprogrammable Asynchronous CMOS Logic Device ............................. 2-57

Page Number

vi

Generallnformafion 1
II

1.

?cYPRESS

General Product Information

Section Contents
Page Number

Cypress Semiconductor Background ......................................................................... 1-1
Ordering Information ..................................................................................... 1-4
Cypress Semiconductor Bulletin Board System (BBS) Announcement .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
Application Notes Listing .................................................................................. 1-6
Product Selector Guide ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Product Line Cross Reference .............................................................................. 1-9
Military Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-14
Military Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-15
Military Ordering Information ............................................................................. 1-17

key changes to their systems very late in the development cycle
to ensure competitive advantage. Used extensively in an wide
range of applications, PLDs constitute a large and growing market. Cypress's UltraLogic TM product line addresses the high-density programmable logic market. UltraLogic includes the
pASIC380 family of field-programmable gate arrays (FPGAs),
the industry'S fastest. It also includes the highest performance
complex PLDs, the FLASH370 family. Both of these product
families are supported by Cypress's VHDL (Very high-speed integrated circuit Hardware Description Language) based
Wafp3 TM , the industry's most advanced software design tool. Cypress pioneered the use of VHDL for PLD programming, and
Wap software is a key factor in the company's overall success in
the PLD market.
Cypress is a leading provider of the industry-standard 22VlO
PLD with a wide range of offerings including a BiCMOS 22VlO
at 5 ns. Cypress is committed to competing in all ranges of the
PLD market, with small devices, the MAX TM CY7C340 EPLD
line, and the UltraLogic products. To support these products,
Cypress offers one of the industry's broadest range of programming tools and software for the programming of its PLDs.
Cypress provides one of the industry's broadest ranges of CMOS
EPROMs and PROMs. Cypress owns a large share of the highspeed CMOS PROM market, and with its new cost structure, is
effectively penetrating the mainstream EPROM market with a
popular 256 Kbit EPROM and the introduction of the world's
fastest 1 Megabit EPROM at 25 ns.
FCT Logic products are used in bus interface and data buffering
applications in almost all digital systems. With the addition of
the FCT logic product line, Cypress now offers over 46 standard
logic and bus interface functions. The products are offered in
the second generation FCT-T format, which is pin-compatible
with the older FCT devices, but adds TTL (transistor-to-transistor logic) outputs for significantly lower ground bounce and improved system noise immunity. Cypress also offers the most
popular devices with on-chip 25-ohm termination resistors
(FCT2-T) to further lower ground bounce with no speed loss.
Included in the new product family is the CYBUS3384, a bus
switch that enables bidirectional data transfer between multiple
bus systems or between 5 volt and 3.3 volt devices. This broad
product offering is produced on Cypress's high-volume, CMOS
manufacturing lines.

Cypress Semiconductor Background
Cypress Semiconductor was founded in April 1983 with the
stated goal of serving the high-performance semiconductor market. This market is served by producing the highest -performance
integrated circuits using state-of-the-art processes and circuit design. Cypress is a complete semiconductor manufacturer, performing its own process development, circuit design, wafer fabrication, assembly, and test. The company went public in May
1986 and has been listed on the New York Stock Exchange since
October 1988.
The initial semiconductor process, a CMOS process employing
1.2-micron geometries, was introduced in March 1984. This process is used in the manufacturing of Static RAMs and Logic circuits. In the third quarter of 1984, a 1.2-micron CMOS EPROM
process was introduced for the production of programmable
products. At the time of introduction, these processes were the
most advanced production processes in the industry. Following
the 1.2-micron processes, a O.8-micron CMOS SRAM process
was implemented in the first quarter of 1986, and a O.8-micron
EPROM process in the third quarter of 1987.
In keeping with the strategy of serving the high-performance
markets with state-of-the-art integrated circuits, Cypress introduced two new processes in 1989. These were a bipolar submicron process, targeted for ECL circuits, and a BiCMOS process
to be used for most types of TTL and ECL circuits.
The circuit design technology used by Cypress is also state of the
art. This design technology, along with advanced process technology, allows Cypress to introduce the fastest, highest-performance circuits in the industry. Cypress's offers products in four
divisions: the Static Memory Division, the Programmable Products Division, the Computation Products Division, and the Data
Communications Division.
Static Memories Division
Cypress is a market-leading supplier of SRAMs, providing a
wide range of SRAM memories for leading companies worldwide. SRAMs are used in high-performance personal computers, workstations, telecommunications systems, industrial systems, instrumentation devices, and networking products.
Cypress's lower production cost structure allows the company to
compete effectively in the high-volume personal computer and
workstation market for SRAMs, including providing cache
RAMs to support today's high-performance microprocessors,
such as Pentium TM , and PowerPC TM. This business, combined
with upcoming low-voltage products for the cellular communications, portable instrument, and laptop/notebook PC markets,
positions Cypress for future success in this key product area.
Multichip modules is a fast-growing market segment that consists of multiple semiconductor chips mounted in packages that
can be inserted in a computer circuit board. Cache modules for
personal computers are the mainstay of this product line, and
Cypress has announced major design wins for these products in
IBM's PSNaluePoint TM line of PCs, and in Apple Computer's
highest performing Power Macintosh TM products.

Data Communications Division
This is an especially significant area for Cypress since it represents a more market-driven orientation for the company in a
fast-growing market segment. As part of the new company strategy' Cypress has dedicated this product line to serve the highspeed data communications market with a range of products
from the physical connection layer to system-level solutions.
HOTLink 1M, high-speed, point-to-point serial communications
chips have been well received. HOTLink, along with the recently announced SONET./SDS Serial Transceiver (SSTTM), address
the fast-growing market segments of Asynchronous Transfer
Mode (ATM) and Fibre Channel communications. The data
communications division encompasses related products including RoboCiock, a programmable skew clock buffer that adjusts
complex timing control signals for a broad range of systems. The
division also offers a broad range of First-In, First-Out (FIFO)
memories, used to communicate data between systems operating
at different frequencies, and Dual-Port Memories, used to distribute data to two different systems simultaneously.

Programmable Products Division
With increasing pressure on system designers to bring products
to market more quickly, programmable logic devices (PLDs) are
becoming extremely popular. PLDs are logic control devices
that can be easily programmed by engineers in the field, and later erased and reprogrammed. This allows the designers to make

1-1

II

Computation Products Division

Manufacturing at the site since 1990 with a charter to specialize
in IC packaging, the Alphatec facility has almost a century of
person-years experience working for U.S. semiconductor suppliers. Thoroughly modern, MIL 883-certified, and with fully developed administrative, logistic, and manufacturing systems in
place, the facility has earned an exceptional reputation for hermetic assembly and out-going quality.
Cypress San Jose maintains complete management control of
Cypress Bangkok's assembly, test, mark, and ship operations
within the facility, thus assuring complete continuity of San
Jose's back-end operations and quality.
Cypress has added Tape Automated Bonding (TAB) to its package offering. TAB, a surface-mount packaging technology, provides the densest lead and package footprint available for fully
tested die.
From Cypress's facility in Minnesota, a VME Bus Interface
Products group has been in operation since the acquisition of
VTC's fab in 1990. Cypress manufactures VIC and VAC VME
devices on the 0.8 micron CMOS process.
The Cypress motto has always been "only the best-the best facilities, the best equipment, the best employees ... all striving to
make the best CMOS, BiCMOS, and bipolar products."

This division focuses on the high-volume, high-growth market
surrounding the desktop computer. It is the second of Cypress's
market-oriented divisions. The division includes timing technology products offered through Cypress's IC Designs Subsidiary in
Kirkland, Washington, and a new line of PC chipsets. IC Designs products are used widely in personal computers and disk
drives, and the product line provides Cypress with major inroads
into these growing markets. IC Designs clock oscillators control
the intricate timing of all aspects of a computer system, including
signals for the computer's central processing unit (CPU), keyboard, disk drives, system bus, serial port, and real-time clock.
They replace all of the metal can oscillators used in the system.
This product line includes QuiXTAL
-a programmable metal can oscillator that replaces individual oscillators used to control timing signals in virtually every type of electronics equipment. Cypress's chipset offerings include products for 486-based
personal computers, as well as PCI local bus controllers for
graphics and multimedia desktop applications. Cypress has announced plans to introduce a low-power, 3.3 volt chipset for the
Pentium P54C, as well as P54C bus controller.
1M -

Cypress Facilities
Situated in California's Silicon Valley (San Jose), Round Rock
(Austin), Texas, and Bloomington, Minnesota, Cypress houses
R&D, design, wafer fabrication, and administration. There are
additional Cypress Design Centers in Starkville, Mississippi, Colorado Springs, Colorado, and the United Kingdom, and a PLD
software design group in Beaverton, Oregon. The facilities are
designed to the most demanding technical and environmental
specifications in the industry. At the Texas and Minnesota facilities, the entire wafer fabrication area is specified to be a Class 1
environment. This means that the ambient air has less than 1
particle of greater than 0.2 microns in diameter per cubic foot of
air. Other environmental considerations are carefully insured:
temperature is controlled to a ±0.1 degree Fahrenheit tolerance;
filtered air is completely exchanged more than 10 times each
minute throughout the fab; and critical equipment is situated on
isolated slabs to minimize vibration.
Attention to assembly is equally critical. Cypress manufactures
100 percent of our wafers in the United States, at our front-end
fabrication sites in California (San Jose), Minnesota (Bloomington), and Texas (Round Rock). Cypress Texas, our largest fab,
and Cypress Minnesota, our newest fab, are both Class 1 facilities.
To improve our global competitiveness, we chose to move most
of our back-end assembly, test, and mark operations to a facility
in Thailand. Be assured that Cypress's total quality commitment
extends to the new site-Cypress Bangkok.
The move to Bangkok consummated an intense search by Cypress for a world-class, environmentally sophisticated facility
that we could bring on line quickly. The Cypress search team
scrutinized fifteen manufacturing facilities in five countries and
chose a site managed by Alphatec Electronics Co., Ltd., a privately owned, entrepreneurial company promoted by the Thailand Board of Investment. Cypress Bangkok occupies almost
25,000 square feet-a significant portion of the manufacturing
floor space available within the facility. The full facility at Bangkok occupies more than 85,000 square feet on a site that encompasses 25 acres-sufficient room for expansion to a number of
buildings in a campus-like setting.

Cypress Process Technology
In the last decade, there has been a tremendous need for highperformance semiconductor products manufactured with a balance of SPEED, RELIABILITY, and POWER. Cypress Semiconductor overcame the classically held perceptions that CMOS
was a moderate-performance technology.
Cypress initially introduced a 1.2-micron "N" well technology
with double-layer poly and a single-layer metal. The process
employed lightly doped extensions of the heavily doped source
and drain regions for both "N" and "P" channel transistors for
significant improvement in gate delays. Further improvements in
performance, through the use of substrate bias techniques, have
added the benefit of eliminating the input and output latch-up
characteristics associated with older CMOS technologies.
Cypress pushed process development to new limits in the areas
of PROMs (Programmable Read Only Memory) and EPLDs
(Erasable Programmable Logic Devices). Both PROMs and
EPLDs have existed since the early 1970s in a bipolar process
that employed various fuse technologies and was the only viable
high-speed nonvolatile process available. Cypress PROMs and
EPLDs use EPROM technology, which has been in use in MOS
(Metal Oxide Silicon) since the early 1970s. EPROM technology
has traditionally emphasized density while forsaking performance. Through improved technology, Cypress produced the first
high-performance CMOS PROMs and EPLDs, replacing their
bipolar counterparts.
To maintain our leadership position in CMOS technology, Cypress introduced a sub-micron technology in 1987. This 0.8 micron breakthrough made Cypress's CMOS one of the most advanced production processes in the world. The drive to maintain
leadership in process technology has not stopped with the
0.8-micron devices. Cypress introduced a 0.65-micron process in
1991. A O.5-micron process is currently in production.
Although not a requirement in the high-performance arena,
CMOS technology substantially reduces the power consumption
for any device. This improves reliability by allowing the device to
operate at a lower die temperature. Now higher levels of integration are possible without trading performance for power. For in-

1-2

stance, devices may now be delivered in plastic packages without
any impact on reliability.
While addressing the performance issues of CMOS technology,
Cypress has not ignored the quality and reliability. aspects of
technology development. Rather, the traditional failure mechanisms of electrostatic discharge (ESD) and latch-up have been
addressed and solved through process and design technology innovation.
ESD-induced failure has been a generic problem for many highperformance MOS and bipolar products. Although in its earliest
years, MOS technology experienced oxide reliability failures, this
problem has largely been eliminated through improved oxide
growth techniques and a better understanding of the ESD problem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits.
Focusing on these constraints, Cypress has developed ESD protection circuitry specific to 1.2-, 0.8-, 0.65-, and O.S-micron
CMOS process technology. Cypress products are designed to
withstand voltage and energy levels in excess of 2001 volts and
0.4 milli-joules.
Latch-up, a traditional problem with CMOS technologies, has
been eliminated through the use of substrate bias generation

techniques, the elimination of the "P" MOS pull-ups in the output drivers, the use of guardring structures and care in the physical layout of the products.
Cypress has also developed additional process innovations and
enhancements: multilayer metal interconnections, advanced
metal deposition techniques, silicides, exclusive use of plasma for
etching, and 100-percent stepper technology with the world's
most advanced equipment.
Cypress has developed a BiCMOS technology to augment the
capabilities of the Cypress CMOS processes. The new BiCMOS
technology is based on the Cypress 0.8-micron CMOS process
for enhanced manufacturability. Like CMOS, the process is scalable, to take advantage of finer line lithography. Where speed is
critical, Cypress BiCMOS allows increased transistor performance. It also allows reduced power in the non-speed critical sections of the design to optimize the speed/power balance. The
BiCMOS process makes memories and logic operating up to 400
MHz possible.
Cypress technologies have been carefully designed, creating
products that are "only the best" in high-speed, excellent reliability, and low power.

IBM PC and IBM ESCON are registered trademarks of International Business Machines Corporation.
QuickPro II, HOTLink, and Wa1p2 are trademarks of Cypress Semiconductor Corporation.

1-3

II

Ordering Information
In general, the valid ordering codes for all products follow the format below; e.g., CY7C128-45DMB, PALC16R8L-35PC
PAL&PLD
PREFIX DEVICE
'PALC'
PALC
PALC
PALCE
PLDC
CY

rt6R81
16R8
22VlO
16V8
20010
7C330

SUFFIX
• -25 L M B'

L:::~~
~8l
-25 P
C
-25 WC
-33 P C

FAMILY
PAL 20
LOW POWER PAL 20
PAL 24 VARIABLE PRODUCT TERMS
FLASH-ERASABLE PAL20
GENERIC PLD 24
PLD SYNCHRONOUS STATE MACHINE
PROCESSING
B = MIL-STD-883C FOR MILITARY PRODUCT
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCT
T = SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED
R = LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIAL (O°CTO +70°C)
I = INDUSTRIAL (-40°C TO +85°C)
M= MILITARY (-55°CTO +125°C)
PACKAGE
B =PLASTIC PIN GRID ARRAY (PPGA)
D = CERAMIC DUAL IN-LINE PACKAGE (CERDIP)/BRAZED DIP
E =TAPE AUTOMATED BONDING (TAB)
F =FLATPACK (SOLDER-SEALED FLAT PACKAGE)
G =PIN GRID ARRAY (PGA)
H = WINDOWED LEADED CHIP CARRIER
J =PLASTIC LEADED CHIP CARRIER (PLCC)
K =CERPACK (GLASS-SEALED FLAT PACKAGE)
L =LEADLESS CHIP CARRIER (LCC)
N =PLASTIC QUAD FLATPACK (PQFP)
P =PLASTIC DUAL IN-LINE (PDIP)
Q = WINDOWED LEADLESS CHIP CARRIER (LCC)
R = WINDOWED PIN GRID ARRAY (PGA)
S =SOIC (GULL WING)
T =WINDOWED CERPACK
U =CERAMIC QUAD FLATPACK (CQFP)
V =SOJ
W =WINDOWED CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
X =DICE (WAFFLE PACK)
Y = CERAMIC LEADED CHIP CARRIER
Z =TSOP
HD = HERMETIC DIP (MODULE)
HV = HERMETIC VERTICAL DIP
PF =PLASTIC FLAT SIP
PS =PLASTIC SIP
PZ =PLASTICZIP
BG =BALL GRID ARRAY

SPEED (ns or MHz)
L = LOW-POWER OPTION
A, B, C, D, G, CF = REVISION LEVEL

Cypress FSCM #65786

1-4

Cypress Semiconductor Bulletin Board System (BBS) Announcement
Cypress Semiconductor supports a 24-hour electronic Bulletin Board System (BBS) that allows Cypress
Applications to better serve our customers by allowing them to transfer files to and from the BBS.
The BBS is set up to serve in multiple ways. One of its purposes is to allow customers to receive the most
recent versions of programming software. Another is to allow the customers to send PLD programming files
that they are having trouble with to the BBS. Cypress Applications can then find the errors in the files, correct them, and place them back on the BBS for the customer to download. The customer may also ask questions in our open forum message area. The sysop (system operator) will forward these questions to the appropriate applications engineer for an answer. The answers then get posted back into the forum. The BBS
also allows the customer to communicate with their local FAE electronically, and to download both application notes and the latest versions of selected datasheets.
Communications Set-Up
The BBS uses a US Robotics HST Dual Standard modems capable of 14.4-Kbaud rates without compression
and rates upwards of 19.2-Kbaud with compression. It is compatible with ccnT Y.32 bis, Y.32, Y.22
(2400-baud), Bell 212A (1200-baud), CCITT Y.42, and CCITT Y.42 bis. It also handles MNP levels 2, 3, 4,
and 5.
To call the BBS, set your communication package parameters as follows:
Baud Rate:

1200 baud to 19.2 Kbaud. Max. is determined by your modem.
Data Bits: 8
Parity: None (N)
Stop Bits: 1

In the U.S. the phone number for the BBS is (408) 943-2954. In Japan the BBS number is
81-423-69-8220. In Europe the BBS number is 49-810-62-2675. These numbers are for transmitting
data only.
If the line is busy, please retry at a later time. When you access the BBS, an initial screen with the following
statement will appear:
Rybbs Bulletin Board

Mter you choose the graphics format you want to use, the system will ask for your first and last name. If you
are a first-time user, you will be asked a few questions for the purposes of registration. Otherwise you will be
asked for your password, and then you will be logged onto the BBS, which is completely menu driven.
Downloading Application Notes and Datasheets
A complete listing of files that may be downloaded is included on the BBS. Application notes and selected
datasheets are available for downloading in two formats, PCL and Postscript. An "hp" in front of the file
name indicates it is a PCL file and can be downloaded to Hewlett-Packard LaserJets and compatible printers. Files without the hp preceding them are in Postscript and can be downloaded to any Postscript printer.
If you have any problems or questions regarding the BBS, please contact Cypress Applications at (408)
943-2821 (voice).

1-5

II

Application Notes

Contact a Cypress representative or use the Cypress Bulletin Board System to get copies of the application notes listed here.

ABEL 4.0/4.1 and the CY7C330, CY7C331, and CY7C332
Bus-Oriented Maskable Interrupt Controller
CMOS PAL Basics
CY7C330 as a Multi-Channel Mbus Arbiter
CY7C331 Asynchronous Self-Timed VMEbus Requestor
CY7C344 as a Second-Level Cache Controller for the 80486
Design Tips for Advanced Max Users
Designing a Multiprocessor Interrupt Distribution Unit with MAX
DMA Control Using the CY7C342 MAX EPLD
FDDI Physical Connection Management Using the CY7C330
FIFO RAM Controller with Programmable Flags
Interfacing PROMs and RAMs to DSP Using Cypress MAX Products
Introduction to Programmable Logic
PAL Design Example: A GCR EncoderlDecoder
pASIC380 Power vs. Operating Frequency
PLD-Based Data Path For SCSI-2
State Machine Design Considerations and Methodologies
T2 Framing Circuitry
Understanding the CY7C330 Synchronous EPLD
Using ABEL to Program the Cypress 22VlO
Using ABEL to Program the CY7C330
Using ABEL 3.2 to Program the CY7C331
Using CUPL with Cypress PLDs
Using LoglIC to Program the CY7C330
Using One-Hot-State Coding to Accelerate a MAX State Machine
Using the CY7C330 in Closed-Loop Servo Control
Using the CY7C331 as a Waveform Generator
Using the CY7C344 with the PLD ToolKit
Are Your PLDs Metastable?
State Machine Design Considerations and Methodologies
Designing with the CY7C335 and Wmp2 VHDL Compiler
The FLASH370 Family Of CPLDs and Designing with Warp2
Implementing a Reframe Controller for the CY7B933 HOTLink Receiver in a CY7C371 CPLD
Architectures and Technologies for FPGAs
Designing with FPGAs
An Introduction to Cypress's 380 Family of FPGAs and the Warp3 Design Tool
CY7C380 Family Quick Power Calculator
Using Scan Mode on pASIC380 For in-Circuit Testing
Getting Started Converting .ABL Files to VHDL
Top-Down Design Methodology With VHDL (Designing an Interrupt Controller)
Abel - HDL vs. IEEE-1076 VHDL
VHDL Techniques for Optimal Design Fitting
Describing State Machines with Warp2 VHDL
Using Hierarchical VHDL Design
Glossary '93
Glossary '94

1-6

-'f~

Product Selector Guide

'CYPRESS
PLDs
Size

Organization

Pins

Speed (ns)

Part Number

PAL20
PAL20
PAL20

16L8
16R8
16R6

20
20
20

PAL16L8
PAL16R8
PAL16R6

PAL20

16R4

20

PAL16R4

tpo = 4.5/5/7
ts/co = 2.5/4.5,2.5/5,3.5/6
tpo/s/co = 4.5/2.5/4.5,5/2.5/5,
7/3.5/6
tpo/s/co = 4.5/2.5/4.5,5/2.5/5,
7/3.5/6
tpo = 20
ts/co = 15/12
tpo/s/co = 20/20/15
tpo/s/co = 20/20/15
tpo/s/co = 7.5/5/5, 10/6/7, 15/10/8
tPD/s/co = 7.5/5/5, 10/6/7, 15/10/8
tpo/s/co = 25/15/15
tpo/s/co = 15/10/10

PAL20
PALlO
PAL20
PAL20
PALCE20
PALCE24
PAL24
PAL24

16L8
16R8
16R6
16R4
16V8-Macrocell
20V8-Macrocell
22V10-Macrocell
22V10-Macrocell

20
20
20
20
20S
24
24S
24S

PALC16L8/L
PALC16R8/L
PALC16R6/L
PALC16R4/L
PALCE16V8
PALCE20V8
PALC22VlO/L
PALC22VlOB

PAL24

22V10-Macrocell

24S

PAL22VlOC

PAL24

22VP1 O-Macrocell

24S

PAL22VP10C

PALCE24
PAL24
PAL24
PLD24
PLD24
PLD24
PLD24
PLD28

22V10-Macrocell
22VlO-Macrocell
22VPlO-Macrocell
20G 10-Generic
20G 1O-Generic
20G 1O-Generic
20RA10-Asynchronous
7C330-State Machine

24
24
24
24S
24S
24S
24S
28S

PALC22V10D
PAL22VlOG
PAL22VPlOG
PLDC20GlO
PLDC20GlOB
PLD20G10C
PLD20RAlO
CY7C330

tpo/s/co =6/3/5.5,7.5/3/6,
10/3.6/7.5
tpo/s/co = 6/3/5.5,7.5/3/6,
10/3.6/7.5
tpo/s/co = 7.5/5/5, 10/6/7, 15/10/8
tpo/s/co = 5/2.5/4,6/3/5.5
tpo/s/co = 5/2.5/4,6/3/5.5
tpo/s/co = 25/15/15
tpo/s/co = 15/12/10
tpo/s/co = 7.5/3/6.5, 10/3.6/7.5
tpo/s/co = 15/10/15
fMAX., tIS, tco = 66 MHz/3ns/12ns

PLD28

7C331-Asynchronous,
Registered
7C335-Universal
Synchronous

28S

CY7C331

tPD/S/CO = 20/12/20

28S

CY7C335

fMAX/tIS = 100MHz/2ns,
83MHz/2ns

PLD28

IccflsB

Packages

(rnA@ns)

Availability

180
180
180

D,J,P
D,J,P
D,J,P

Now
Now
Now

180

D,J,P

Now

70,45
70,45
70,45
70,45
115/90/55
115/90/55
90,55
90

Now
Now
Now
Now
Now
Q494
Now
Now

190

D,L,P,Q,Y,W
D,L,P'Q, Y,W
D,L,P'Q,Y,W
D,L,P'Q,Y,W
D,J,L,P
D,J,L,P
D,J,K,L,P,Q,W
D,H,J,K,L,
P,Q,W
D,J,L,P

190

D,J,L,P

Now

130/90/90
190
190
55
70
190
80
130@50
MHz
120@25ns

D,J,L,P
D,J,L
D,J,L
D,J,L,P,Q,W
D,H,J,L,P,Q,W
D,J,L,P
D,H,J,L,P,Q,W
D,H,J,L,P,Q,W

Now
Now
Now
Now
Now
Now
Now
Now

D,H,J,L,P,Q,W

Now

140

D,H,J,L,P,Q,W

Now

Now

CPLDs
Size
MAX28
MAX44
MAX68
MAX84
MAX100
FLASH37044
FLASH37044
FLASH37084
FLASH37084
FLASH370160
FLASH370160
FLASH370240
FLASH370160
FLASH370240

Organization
7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C346-128 Macrocell

Pins

28S
44
68
84
84,
100
7C371-32-Macrocell 44
FlashCPLD
7C372-64-Macrocell 44
FlashCPLD
7C373-64-Macrocell 84,
FlashCPLD
100
7C374-128-Macrocell 84,
FlashCPLD
100
7C375-128-Macrocell 160
FlashCPLD
7C376-192-Macrocell 160
FlashCPLD
7C377-192-Macrocell 240
FlashCPLD
7C378-256-Macrocell 160
FlashCPLD
7C379-256-Macrocell 240
FlashCPLD

Speed (ns)

Part Number

IccflsB

Packages

(rnA)

Availability

CY7C344/B
CY7C343/B
CY7C342/B
CY7C341/B
CY7C346/B

tpo/s/co = 15/9/10,10/6/5
tpo/s/co = 20/12/12, 12/8/6
tpo/s/co = 25/15/14, 12/8/6
tpo/s/co = 25/20/16, 15/10/7
tpo/s/co = 25/15/14, 15/10/7

200/150
135/125
250/225
380/360
250/225

D,H,J,P,W
H,J,R
H,J,R
H,J,R
H,J,N,R

Now
Now
Now
Now
Now

CY7C371

fMAX/tsitco = 143MHz/6.5 ns/6.5 ns

150n'BD

J,Y

Now

CY7C372

fMAX/tsltco= 100 MHz/6.5 ns/6.5 ns

180n'BD

J,Y

Q494

A,J,G,Y

Q494

300n'BD

A,J,G,Y

Now

300n'BD

A,G,U

Now

CY7C376

fMAX/tsitco = 100 MHz/6.5 nsf
6.5ns
fMAX/tsitco = 100 MHz/6.5 nsf
6.5ns
fMAX/tS/tco = 100 MHz/6.5 nsf
6.5ns
fMAX/ts/tco = 83 MHz/l 0 ns/10 ns

180n'BD

300n'BD

A,G

Q495

CY7C377

fMAXIts/tco = 83 MHz/l 0 ns/lO ns

300n'BD

BGA,N,G

Q495

CY7C378

fMAX/ts/tco = 83 MHz/lO ns/lO ns

300n'BD

A,G

Q295

300n'BD

BGA,N,G

Q295

CY7C373
CY7C374
CY7C375

CY7C379

fMAX/tsitco = 83 MHz/lO ns/lO ns

1-7

II

~rcypRESS

Product Selector Guide

FPGAs
Size
pASIC380lK
pASIC380lK
pASIC380lK3.3V
pASIC380lK3.3V
~~SIC380-

pASIC3802K
pASIC3804K
pASIC3804K
~~SIC380-

~~SIC380-

pASIC38012K

Organization
CMOS8xI2,IKGates
FPGA
CMOS 8x12, lK Gates
FPGA
3.3V CMOS 8x12, lK
Gates FPGA
3.3V CMOS 8x12, lK
Gates FPGA
CMOS 12x16, 2K Gates
FPGA
CMOS 12x16, 2K Gates
FPGA
CMOS 16x24, 4K Gates
FPGA
CMOS 16x24,4KGates
FPGA
CMOS 24x32, 8K Gates
FPGA
CMOS 24x32, 8K Gates
FPGA
CMOS 32x36, 12K Gates
FPGA

Pins

Part Number

Speed Grade

ICc/ISB
(rnA)

44

CY7C381A

-0,"-1,-2

ISB= 10

68,
100
44

CY7C382A

-0, -1,-2

CY7C3381A

-0,-1,-2

CY7C3382A

Packages

Availability

J

Now

ISB = 10

A,G,J

Now

ISB=2

J

Q394

-0,-1,-2

ISB=2

A,G,J

Q394

CY7C383A

-0,-1,-2

ISB= 10

J

Now

CY7C384A

-0,-1,-2

ISB = 10

A,G,J

Now

CY7C385A

-0,-1,-2

ISB= 10

A,J

Now

CY7C386A

-0, -1,-2

ISB= 10

A,G,U

Now

CY7C387A

-0,-1,-2

ISB = 10

A,G

Q195

208

CY7C388A

-0,-1,-2

ISB = 10

N,G

Q195

208

CY7C389A

-0,-1,-2

ISB = 10

N

Q495

68,
100
68
84,
100
84,
100
144
160
144

Design and Programming Tools
Part Name

Wa1p2 for PC
Wmp2 for Sun
Wa1p3 for PC
Wa1p3 for Sun
Impulse3

Part Number

lYpe
VHDL Design Tool
VHDL Design Tool
VHDL/CAE Design Tool
VHDL/CAE Design Tool
Programmer

CY3120
CY3125
CY3130
CY3135
CY3500

Notes:
The above specifications are for the commercial temperature range of O°C to 70°e. Military temperature range (-55°C to + 125°C) product processed
to MIL-STD-883 Revision C is also available for most products. Speed and power selections may vary from those above. Contact your local sales office
for more information.
Commercial grade product is available in plastic, CERDlp, or LCe. Military grade product is available in CERDIP, LCC, or PGA. F, K, and T packages
are special order only.
All power supplies are Vee = 5V ± 10%.
22S, 24S, 28S stands for 300 mil. 22-pin, 24-pin, 28-pin, respectively. 28.4 stands for 28-pin 400 mil, 24.4 stands for 24-pin 400 mil.
PLCC, SOJ, and SOIC packages are available on some products.
F, K, and T packages are special order only.
Package Code:
B = PLASTIC PIN GRID ARRAY
D = CERDIP
E = TAPE AUTOMATED BOND
(TAB)
F = FLATPACK
G = PIN GRID ARRAY (PGA)
H = WINDOWED HERMETIC LCC
J = PLCC
K = CERPACK
L = LEADLESS CHIP CARRIER (LCC)
N = PLASTIC QUAD FLATPACK
P = PLASTIC
Q = WINDOWED LCC
R = WINDOWED PGA

S
T
U
V
W
X
Y
Z
HD
HV
PF
PS
PZ
BG

=
=
=
=
=
=
=
=
=
=
=
=
=
=

SOIC
WINDOWED CERPACK
CERAMIC QUAD FLATPACK
SOJ
WINDOWED CERDIP
DICE
CERAMIC LCC
TSOP
HERMETIC DIP (Module)
HERMETIC VERTICAL DIP
PLASTIC FLAT SIP
PLASTIC SIP
PLASTIC ZIP
BALL GRID ARRAY

1-8

.....;:::===:;.

-.

-~

Product Line Cross Reference

~}CYPRESS

CYPRESS
PALC16L8-25C
PALC16L8-30M
PALC16L8-35C
PALC16L8-40M
PALC16L8L- 35C
PALC16R4-25C
PALC16R4-30M
PALC16R4-35C
PALC16R4-40M
PALC16R4L- 35C
PALC16R6-25C
PALC16R6-30M
PALC16R6-35C
PALC16R6-40M
PALC16R6L- 35C
PALC16R8-25C
PALC16R8-30M
PALC16R8-35C
PALC16R8-40M
PALC16R8L-35C
PALC22VlO-35C
PALC22VlO-40M
PALC22VlOL- 25C
PALC22VlOL- 35C
PLDC20G10-35C
PLDC20GlO-40M

CYPRESS
PALC16L8L- 25C
PALC16L8-20M
PALC16L8-25C
PALC16L8-30M
PALC16L8L-25C
PALC16R4L- 25C
PALC16R4-20M
PALC16R4-25C
PALC16R4-30M
PALC16R4L- 25C
PALC16R6L- 25C
PALC16R6-20M
PALC16R6-25C
PALC16R6-30M
PALC16R6L- 25C
PALC16R8L- 25C
PALC16R8-20M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-25C
PALC22VlO-25C
PALC22VlO-30M
PALC22V10- 25C
PALC22V10L- 25C
PLDC20G10-25C
PLDC20GlO-30M

ALTERA

CYPRESS
PREF1X:CY
7C344-25WC
7C344-20WC
7C344-15WC
Call Factory
7C344-20WC
7C344-25WC
7C344-25WMB
7C344- 25WMB
7C344-25HC
7C344-20HC
7C344-15HC
Call Factory
7C344-20HC
7C344-25HC
7C344-20H1
7C344- 25HMB
7C344-25HMB
7C344-25JC
7C344-20JC
7C344-15JC
Call Factory
7C344-2OJC
7C344-25JC
7C344-25PC
7C344-20PC
7C344-15PC
Call Factory
7C344-20PC
7C344-25PC
7C343-35HC
7C343-25HC
7C343-30HC
7C343-35HI

PREF1X:EPM
5032DC
5032DC-2
5032DC-15
5032DC-17
5032DC-20
5032DC-25
5032DM
5032DM-25
5032JC
5032JC-2
5032JC-15
5032JC-17
5032JC-20
5032JC-25
503211-20
5032JM
5032JM-25
5032LC
5032LC-2
5032LC-15
5032LC-17
5032LC-20
5032LC-25
5032PC
5032PC-2
5032PC-15
5032PC-17
5032PC-20
5032PC-25
5064JC
5064JC-1
5064JC-2
506411

ALTERA
5064JM
5064LC
5064LC-1
5064LC-2
5128AGC-1
5128AGC-2
5128AGC-3
5128AJC-1
5128AJC-2
5128AJC-3
5128ALC-1
5128ALC-2
5128ALC-3
5128GC
5128GC-1
5128GC-2
5128GM
5128JC
5128JC-1
5128JC-2
512811
512811-2
5128JM
5128LC
5128LC-1
5128LC-2
5128LI
5128LI-2
5130GC
5130GC-1
5130GC-2
5130GM
5130JC
5130JC-1
5130JC-2
5130JM
5130LC
5130LC-1
5130LC-2
5130LI
5130LI-2
5130QC
5130QC-1
5130QC-2
5130Q1
5192AGC-1
5192AGC-2
5192AJC-l
5192AJC-2
5192ALC-1
5192ALC-2
5192GC
5192GC-1
5192GC-2
5192JC
5192JC-1
5192JC-2
519211
5192LC
5192LC-1
5192LC-2

CYPRESS
7C343-35HMB
7C343-35JC
7C343-25JC
7C343-30JC
7C342B-12RC
7C342B-15RC
7C342B-20RC
7C342B-12HC
7C342B-15HC
7C342B-20HC
7C342B-12JC
7C342B-15JC
7C342B-20JC
7C342-35RC
7C342-25RC
7C342-30RC
7C342-35RMB
7C342-35HC
7C342-25HC
7C342-30HC
7C342-35H1
7C342-30HI
7C342-35HMB
7C342-35JC
7C342-25JC
7C342-3OJC
7C342-35JI
7C342-30H1
7C346-35RC
7C346-25RC
7C346-30RC
7C346-35RM
7C346-35HC
7C346-25HC
7C346-30HC
7C346-35HM
7C346-35JC
7C346-25JC
7C346-30JC
7C346-35JI
7C346-301l
7C346-35NC
7C346-25NC
7C346-30NC
7C346-35N1
7C34IB-15RC
7C34IB-20RC
7C341B-15HC
7C34IB-20HC
7C34IB-15JC
7C43IB-2OJC
7C341-35RC
7C341-25RC
7C341-30RC
7C341-35HC
7C341-25HC
7C341-30HC
7C341-35H1
7C341-35JC
7C341-25JC
7C341-3OJC

1-9

AMD
SMDPN
5962-8515501RX
5962-85155012X
5962-8515502RX
5962-85155022X
5962-8515503RX
5962-85155032X
5962-8515504RX
5962-85155042X
5962-8515505RX
5962-85155052X
5962-8515506RX
5962-85155062X
5962-8515507RX
5962-851550nX
5962-8515508RX
5962-85155082X
5962-8515509RX
5962-85155092X
5962-851551ORX
5962-85155 102X
5962-8515511RX
5962-85155112X
5962-8515512RX
5962-85155122X
5962-8515513RX
5962-8515514RX
5962-85155 15RX
5962-8515516RX
5962-8515517RX
5962-8515518RX
5962-8515519RX
5962-8515520RX
5962-8605301LA
5962-86053013A
5962-8605301KA
5962-8605302LA
5962-86053023A
5962-8605302KA
5962-8605304LA
5962-86053043A
5962-8605304KA
5962-86053053A
5962-8605305KA
5962-8605305LA
5962-8851501RX
5962-885150l2X
5962-8851502RX
5962-88515022X
5962-8851503RX
5962-88515032X
5962-8851504RX
5962-88515042X
PREF1X:Am
PREF1X:SN
SUFF1X:B
SUFF1X:D
SUFF1X:F
SUFF1X:L
SUFF1X:P
MACHllO-12JC
MACHllO-15JC

CYPRESS
SMDPN
5962-8871309RX
5962-8871309XX
5962-8871310RX
5962-88713 lOXX
5962-88713 11RX
5962-88713 11 XX
5962-88713 12RX
5962-88713 12XX
5962-8871309RX
5962-88713 09XX
5962-88713 10RX
5962-8871310XX
5962-8871311RX
5962-88713 11XX
5962-88713 12RX
5962-88713 12XX
5962-92338 OlMRX
5962-92338 OlMXX
5962-923380lMRX
5962-9233802MXX
5962-9233803MRX
5962-9233803MXX
5962-9233804MRX
5962-9233804MXX
5962-9233801MRX
5962-9233802MRX
5962-9233803MRX
5962-9233804MRX
5962-9233801MRX
5962-9233802MRX
5962-9233803MRX
5962-9233804MRX
5962-8984101LX
5962-89841013X
5962-89841 01KX
5962-89841 01 LX
5962-89841013X
5962-8984101KX
5962-89841 02LX
5962-89841023X
5962-89841 02KX
5962-89841063X
5962-89841 06KX
5962-8984106LX
5962-88713 09RX
5962-88713 09XX
5962-88713 lORX
5962-8871310XX
5962-88713 11RX
5962-88713 llXX
5962-88713 12RX
5962-88713 12XX
PREF1X:CY
PREF1X:CY
SUFF1X:B
SUFF1X:DORW
SUFF1X:F
SUFF1X:L
SUFF1X:P
7C371-83JC
7C371-66JC

II

':arcYPRESS
AMD
MACHllO-20JC
MACHIIO-20/BXA
MACHI30-ISJC
MACH130- 20JC
MACH130-20/BXA
MACH21O-I2JC
MACH21O-ISJC
MACH210-20JC
MACH21O- 20/BXA
MACH210A-lOJC
MACH21OA-I2JC
MACH230-ISJC
MACH230-2OJC
MACH43S -ISJC
MACH43S-20JC
PAL16L8-4C
PAL16L8-SC
PAL16L8-7C
PAL16L8-10/B
PAL16L8 -12/B
PAL16L8-D/2
PAL16L8A-4C
PAL16L8A-4M
PALI6L8AC
PAL16L8ALC
PALI6L8ALM
PAL16L8AM
PAL16L8BM
PALI6L8C
PAL16L8LC
PAL16L8LM
PAL16L8M
PALI6L8QC
PAL16L8QM
PAL16R4-4C
PAL16R4-SC
PAL16R4-7C
PAL16R4-1O/B
PAL16R4-12/B
PAL16R4-D/2
PAL16R4A -4C
PAL16R4A-4M
PAL16R4ALC
PAL16R4ALM
PAL16R4AM
PAL16R4BM
PAL16R4C
PALI6R4LC
PAL16R4LM
PAL16R4M
PAL16R4QC
PAL16R4QM
PAL16R6-4C
PAL16R6-SC
PAL16R6-7C
PAL16R6-1O/B
PAL16R6-I2/B
PAL16R6- D/2
PAL16R6A -4C
PAL16R6A -4M
PAL16R6AC
PAL16R6ALC

CYPRESS

7C37I-66JC
7C37I-66YMB
7C373-83JC
7C373-66JC
7C373-66YMB
7C372-100JC
7C372-83JC
7C372-66JC
7C372-66YMB
7C372-I2SJC
7C372-100JC
7C374-83JC
7C374-66JC
7C374-83JC
7C374-66JC
PALI6L8-4C
PAL16L8-SC
PAL16L8-7C
PAL16L8-lOM
PAL16L8-lOM
PAL16L8-7C
PALC16L8L- 3SC
PALC16L8-40M
PALC16L8-2SC
PALC16L8-2SC
PALC16L8-30M
PALC16L8-30M
PALC16L8-20M
PALC16L8-3SC
PALC16L8-3SC
PALCI6L8-40M
PALC16L8-40M
PALC16L8L-3SC
PALC16L8-40M
PAL16R4-4C
PAL16R4-SC
PALI6R4-7C
PALI6R4-lOM
PAL16R4-lOM
PAL16R4-7C
PALC16R4L-3SC
PALCI6R4-40M
PALC16R4-2SC
PALC16R4-30M
PALC16R4-30M
PALCI6R4-20M
PALCI6R4-3SC
PALC16R4-3SC
PALC16R4-40M
PALC16R4-40M
PALCI6R4L-3SC
PALCI6R4-40M
PALI6R6-4C
PAL16R6-SC
PAL16R6-7C
PAL16R6-10M
PAL16R6-lOM
PAL16R6-7C
PALCI6R6L-3SC
PALCI6R6-40M
PALC16R6-2SC
PALC16R6-2SC

Product Line Cross Reference
AMD
PALI6R6ALM
PAL16R6AM
PALI6R6BM
PALI6R6C
PALI6R6LC
PALI6R6LM
PALI6R6M
PAL16R6QC
PALI6R6QM
PAL16R8-4C
PAL16R8-SC
PALI6R8-7C
PALI6R8 -1O/B
PAL16R8-12/B
PAL16R8-D/2
PAL16R8A -4C
PAL16R8A-4M
PALI6R8AC
PAL16R8ALC
PAL16R8ALM
PALI6R8AM
PALI6R8BM
PAL16R8C
PAL16R8LC
PAL16R8LM
PAL16R8M
PAL16R8QC
PAL16R8QM
PAL22VlO-7JC
PAL22VlO-7PC
PAL22VlO-lODC
PAL22VlO-lOJC
PAL22VlO-lOPC
PAL22VlO-12/B3A
PAL22VlO-12/BLA
PAL22VlO -lSDC
PAL22VIO-lSJC
PAL22VlO-1SPC
PAL22VIO- 20/B3A
PAL22VlO- 20/BLA
PAL22VIO/B3A
PAL22VlO/BLA
PAL22VIOA/B3A
PAL22VIOA/BLA
PAL22VIOADC
PAL22VIOAJC
PAL22VlOAPC
PAL22VIODC
PAL22VlOJC
PAL22VlOPC
PALCEI6V8H-7JC/4
PALCE16V8H-7PQ4
PALCEI6V8H-IOJQ4
PALCEI6V8H-lOPC/4
PALCE16V8H-lSJQ4
PALCE16V8H-ISPC/4
PALCE16V8H-25JQ4
PALCEI6V8H-25PC/4
PALCE16V8Q-lSJC/4
PALCE16V8Q-lSPQ4
PALCE16V8Q-25JQ4
PALCE16V8Q-25PQ4

CYPRESS

PALCI6R6- 30M
PALCI6R6-30M
PALCI6R6- 20M
PALCI6R6-3SC
PALCI6R6-3SC
PALCI6R6-40M
PALC16R6-40M
PALCI6R6L- 3SC
PALCI6R6-40M
PALI6R8-4C
PALI6R8-SC
PAL16R8-7C
PAL16R8-lOM
PALI6R8-lOM
PAL16R8-7C
PALC16R8L-3S
PALC16R8-40M
PALC16R8-2SC
PALC16R8-2SC
PALCI6R8-30M
PALC16R8- 30M
PALC16R8-20M
PALC16R8-3SC
PALC16R8-3SC
PALC16R8-40M
PALC16R8-40M
PALC16R8L-3S
PALC16R8-40M
PALC22VIOD -7JC
PALC22VlOD-7PC
PALC22VIOD-IODC
PALC22VlOD-lOJC
PALC22VIOD-lOPC
PALC22VlOB-lOLMB
PALC22VlOB-lODMB
PALC22VIOB-lSDC
PALC22VlOB-lSJC
PALC22VlOB-ISPC
PALC22VlOB-20LMB
PALC22VlOB-20DMB
PALC22VlO-3SLMB
PALC22VlO-3SDMB
PALC22VlO-25LMB
PALC22VIO-2SDMB
PALC22VI0- 2SDC
PALC22VlO- 2SJC
PALC22VlO- 25PC
PALC22VlO- 3SDC
PALC22VlO-3SJC
PALC22VIO-3SPC
PALCE16V8-7JC
PALCE16V8-7PC
PALCE16V8-10JC
PALCE16V8-lOPC
PALCEI6V8-1SJC
PALCE16V8-1SPC
PALCEI6V8-2SJC
PALCE16V8-2SPC
PALCE16V8L-lSJC
PALCEI6V8L-ISPC
PALCE16V8L-25JC
PALCE16V8L-25PC

AMD
PALCE22VIOH-7JC
PALCE22VlOH-lOPC
PALCE22VIOH-lOJC
PALCE22VlOH-lOPC
PALCE22VlOH
-IS/B3A
PALCE22VIOH
-lS/BLA
PALCE22VlOH-lSJC
PALCE22VlOH-ISPC
PALCE22VlOH
-20/B3A
PALCE22VlOH
-20/BLA
PALCE22VlOH
-2S/B3A
PALCE22VlOH
-2S/BLA
PALCE22VlOH-2SJC
PALCE22VlOH-2SPC
PALCE22VlOH
-30/B3A
PALCE22VlOH
-30/BLA

ATMEL
PREFIX:AT
22VlO
22VlO-1S

CYPRESS

PREFIX:CY
PALC22VlO
PALC22VlOB

HARRIS

CYPRESS

PREFIX:HM
PREFIX:HPL
SUFFIX:8
PREFIX: 1
PREFIX:9
PREFIX:4
PREFIX:3
16LC8-S
16LC8-8
16LC8-9
16RC4-S
16RC4-8
16RC4-9
16RC6-S
I6RC6-8
16RC6-9
16RC8-S
I6RC8-8
16RC8-9

PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
PALC16L8L- 3SC
PALC16L8-40M
PALC16L8-40M
PALC16R4L- 3SC
PALC16R4-40M
PALC16R4-40M
PALCI6R6L-3SC
PALCI6R6-40M
PALC16R6-40M
PALC16R8L- 3SC
PALC16R8-40M
PALC16R8-40M

INTEL
PREFIX:8SC
PREFIX:8SC
PREFIX:D
PREFIX:L
PREFIX:P
SUFFIX:/B
22VlO-10C
22VlO-lOC
22VlO-lOC
22VlO-lOC
22VlO-lSC
22VlO-1SC

PREFIX:CY
PREFIX:PLD
SUFFIX:D
SUFFIX:L
SUFFIX:P
SUFFIX:B
PALC22VlOD-7C
PALC22VlOD -lOC
PAL22VlOC-7C+
PAL22VlOC-I0C+
PALC22VlOB-lSC
PALC22VlOD-ISC

Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and S rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SorConly

1-10

CYPRESS

PALC22VlOD-lOJC
PALC22VlOD-7PC
PALC22VlOD-IOJC
PALC22VIOD-lOPC
PALC22VlOD
-lSLMB
PALC22VlOD
-ISDMB
PALC22VlOD-ISJC
PALC22VlOD-lSPC
PALC22VlOD
-20LMB
PALC22VIOD
-20DMB
PALC22VIOD
-2SLMB
PALC22VIOD
-2SDMB
PALC22VlOD-2SJC
PALC22VlOD-2SPC
PALC22VlOD
-2SLMB
PALC22VlOD
-2SDMB

CYPRESS

-.,~

Product Line Cross Reference

,CYPRESS
LATTICE
PREFIX:EE
PREFIX: GAL
PREFIX:ST
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
GALl6V8A-lOU
GALl6V8A-lOLP
GALl6V8A -l5U
GALl6V8A -l5LP
GALl6V8A -15QJ
GALl6V8A -l5QP
GAL16V8A - L5U
GAL16V8A - 25LP
GAL16V8A-25QJ
GAL16V8A-25QP
GAL16V8B-7U
GAL16V8B-7LP
GAL16V8B-lOU
GAL16V8B-lOUI
GAL16V8B-lOLP
GAL16V8B-lOLPI
GAL16V8B-15UI
GAL16V8B-15LPI
GAL16V8B- 25UI
GAL16V8B- 25LPI
GAL20V8A
GAL20V8B
GAL22VlOB-7U
GAL22VlOB -7LP
GAL22VlOB-IOU
GAL22VlOB-lOLP
GAU2VlOB-l5LD
/883
GAL22VlOB-l5U
GAL22VlOB-15UI
GAL22VlOB-15LP
GAL22VlOB -l5LPI
GAL22VlOB -l5LR
/883
GAL22VlOB- 20UI
GAL22VlOB- 20LD
/883
GAL22VlOB- 20LPI
GAL22VlOB- 20LR
/883
GAL22V10B - 25LD
/883
GAL22VlOB - 25U
GAL22VlOB - 25UI
GAL22VlOB - 25LP
GAL22VlOB- 25LPI
GAL22VlOB- 25LR
/883
GAL22VlOB - 30LD
/883
GAL22VlOB - 30LR
/883
GAL22VlOC-5U
GAL22VlOC-7U
GAL22VlOC-7PC

CYPRESS
PREFIX:CY
PREFIX:PALCE
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
PALCEl6V8-l0JC
PALCEl6V8 -lOPC
PALCEl6V8-l5JC
PALCE16V8-15PC
PALCE16V8L-15JC
PALCE16V8L-l5PC
PALCEl6V8-25JC
PALCEl6V8 - 25PC
PALCE16V8L-25JC
PALCE16V8L-25PC
PALCE16V8-7JC
PALCE16V8-7PC
PALCEl6V8-lOJC
PALCE16V8-lOJI
PALCE16V8-10PC
PALCE16V8 -lOPI
PALCEl6V8-l5JI
PALCE16V8-15PI
PALCE16V8- 25JI
PALCE16V8-25PI
PALCE20V8
PALCE20V8
PALC22VlOD-7JC
PALC22VlOD -7PC
PALC22VlOD-lOJC
PALC22V10D-lOPC
PALC22VlOD15DMB
PALC22VIOD-15JC
PALC22VlOD-l5JI
PALC22VlOD-l5PC
PALC22VIOD-l5PI
PALC22VlOD15LMB
PALC22VlOD-l5JI
PALC22VlODl5DMB
PALC22VlOD-l5PI
PALC22VlODl5LMB
PALC22V10D25DMB
PALC22VIOD-25JC
PALC22VlOD-25JI
PALC22VlOD-25PC
PALC22VIOD-25PI
PALC22VlOD25LMB
PALC22VIOD25DMB
PALC22VIOD25LMB
PAL22VlOG-5JC
PAL22VIOD-7JC
PAL22VlOD-7PC

MMI/AMD
SUFFIX:883B
SUFFIX:F
SUFFIX:J
SUFFIX:L
SUFFIX:N
SUFFIX:SHRP
PALl2LlOC
PALl 2Ll OM
PALl4L8C
PALl4L8M
PAL16L6C
PALl6L6M
PALl6L8A-2C
PAL16L8A - 2M
PAL16L8A -4C
PAL16L8A-4M
PAL16L8AC
PAL16L8AM
PAL16L8B-2C
PAL16L8B-2M
PALl6L8B-4C
PALl6L8B-4M
PAL16L8BM
PAL16L8C
PAL16L8D-4C
PAL16L8D-4M
PAL16L8M
PALl6R4A-2C
PALl6R4A-2M
PALl6R4A-4C
PALl6R4A-4M
PALl6R4AC
PALl6R4AM
PALl6R4B-2C
PAL16R4B-2M
PALl6R4B-4C
PALl6R4B-4M
PALl6R4BM
PALl6R4C
PALl6R4D-4C
PAL16R4M
PAL16R6A - 2C
PALl6R6A - 2M
PALl6R6A-4C
PALl6R6A-4M
PALl6R6AC
PALl6R6AM
PALl6R6B-2C
PAL16R6B-2M
PALl6R6B-4C
PALl6R6B-4M
PAL16R6BM
PALl6R6C
PALl6R6D-4C
PAL16R6M
PALl6R8A - 2C
PALl6R8A-2M
PALl6R8A-4C
PAL16R8A-4M
PALl6R8AC
PAL16R8AM
PAL16R8B-2C

CYPRESS
SUFFIX:B
SUFFIX:F
SUFFIX:D
SUFFIX:L
SUFFIX:P
SUFFIX:B
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLD20GlO-40M
PLD20GlO-35C
PLDC20GlO-40M
PALC16L8-35C
PALC16L8-40M
PALC16L8L-35C
PALC16L8-40M
PALCl6L8-25C
PALC16L8-30M
PALC16L8-35C
PALC16L8-30M
PALC16L8L- 35C
PALC16L8-40M
PALC16L8-20M
PALC16L8-35C
PALCl6L8L- 25C
PALC16L8-30M
PALCl6L8-40M
PALC16R4- 35C
PALC16R4-40M
PALC16R4L- 35C
PALCl6R4-40M
PALCl6R4-25C
PALC16R4-30M
PALCl6R4-25C
PALC16R4-30M
PALCl6R4L- 35C
PALCl6R4-40M
PALC16R4-20M
PALC16R4-35C
PALCl6R4L- 25C
PALCl6R4-40M
PALC16R6-35C
PALCl6R6-40M
PALCl6R6L- 35C
PALCl6R6-40M
PALCl6R6-25C
PALCl6R6-30M
PALC16R6-25C
PALC16R6-30M
PALC16R6L- 35C
PALCl6R6-40M
. PALC16R6-20M
PALC16R6-35C
PALCl6R6L- 25C
PALC16R6-40M
PALC16R8-35C
PALC16R8-40M
PALCl6R8L- 35C
PALC16R8-40M
PALC16R8 - 25C
PALC16R8-30M
PALCl6R8-25C

1-11

MMI/AMD
PALl6R8B-2M
PALl6R8B-4C
PALl6R8B-4M
PALl6R8BM
PALl6R8C
PALl6R8D-4C
PALl6R8M
PAL18L4C
PALl8L4M
PAL20LlOAC
PAL20LlOAM
PAL20LlOC
PAL20LlOM
PAL20L2C
PAL20L2M
PAL20L8A-2C
PAL20L8A-2M
PAL20L8AC
PAL20L8AM
PAL20L8C
PAL20L8M
PAL20R4A-2C
PAL20R4A-2M
PAL20R4AC
PAL20R4AM
PAL20R4C
PAL20R4M
PAL20R6A - 2C
PAL20R6A-2M
PAL20R6AC
PAL20R6AM
PAL20R6C
PAL20R6M
PAL20R8A-2C
PAL20R8A - 2M
PAL20R8AC
PAL20R8AM
PAL20R8C
PAL20R8M
PALC22VIO/A

CYPRESS
PALCl6R8-30M
PALCl6R8L- 35C
PALCl6R8-40M
PALCl6R8-20M
PALCl6R8 - 35C
PALCl648L- 25C
PALCl6R8-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20G10-30M,.
PLDC20GlO-35C
PLDC20GIO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO- 30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G10-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PALC22VlO-35C

NATIONAL
PREFIX:DM
PREFIX:GAL
PREIFX:IDM
PREFIX:NM
PREFIX:NMC
SUFFIX:J
SUFFIX:N
18L4C
l8L4M
20L2M
GAL22VIO-15C
GAL22VlO-2OI
GAL22V1O-20M
GAL22VIO-25C
GAL22VIO-3OI
GAL22VIO-30M
PALl 64A2M
PAL16L8A2C
PALl6L8A2M
PAL16L8AC

CYPRESS
PREFIX:CY
PREFIX:None
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:D
SUFFIX:P
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-40M
PALC22VlOD-15C
PALC22VlOD-l5I
PALC22VlOD-15M
PALC22VIOD - 25C
PALC22VIOD - 251
PALC22VlOD-25M
PALC16R4-40M
PALC16L8-35C
PALC16L8-40M
PALCl6L8-25C

II

Product Line Cross Reference
NATIONAL
PAL16LSAM
PAL16LSB2C
PAL16LSB2M
PAL16LSB4C
PAL16LSB4M
PAL16LSBM
PAL16LSC
PAL16LSM
PAL16R4A2C
PAL16R4AC
PAL16R4AM
PAL16R4B2C
PAL16R4B2M
PAL16R4B4C
PAL16R4B4M
PAL16R4BM
PAL16R4C
PAL16R4M
PAL16R6A2C
PAL16R6A2M
PAL16R6AC
PAL16R6AM
PAL16R6B2C
PAL16R6B2M
PAL16R6B4C
PAL16R6B4M
PAL16R6BM
PAL16R6C
PAL16R6M
PAL16R8A2C
PAL16R8A2M
PAL16R8AC
PAL16R8AM
PAL16R8B2C
PAL16R8B2M
PAL16R8B4C
PAL16R8B4M
PAL16R8BM
PAL16R8C
PAL16R8M
PAL20L2C
PAL20LSAC
PAL20LSAM
PAL20LSBC
PAL20LSBM
PAL20LSC
PAL20LSM
PAL20LlOB2C
PAL20LlOB2M
PAL20LlOC
PAL20LlOM
PAL20R4AC
PAL20R4AM
PAL20R4BC
PAL20R4BM
PAL20R4C
PAL20R4M
PAL20R6AC
PAL20R6AM
PAL20R6BC
PAL20R6BM
PAL20R6C

CYPRESS
PALC16LS-30M
PALC16LS-25C
PALC16LS-30M
PALC16LSL- 35C
PALC16LS-40M
PALC16LS-20M
PALC16LS-35C
PALC16LS-40M
PALC16R4-35C
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
PALC16R4-30M
PALC16R4L-35C
PALC16R4-40M
PALC16R4-20M
PALC16R4-35C
PALC16R4-40M
PALC16R6-35C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-30M
PALC16R6L- 35C
PALC16R6-40M
PALC16R6-20M
PALC16R6-35C
PALC16R6-40M
PALC16R8-35C
PALC16R8-40M
PALC16R8-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8 - 30M
PALC16R8L-35C
PALC16R8-40M
PALC16R8- 20M
PALC16R8-35C
PALC16R8-40M
PLDC20GlO-35C
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G 1O-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G 10-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20G 10-30M
PLDC20GlO-35C
PLDC20G1O-40M
PLDC20GlO-25C
PLDC20G 10-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C

NATIONAL
PAL20R6M
PAL20R8AC
PAL20R8AM
PAL20R8BC
PAL20R8BM
PAL20R8C
PAL20R8M

CYPRESS
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20G 10-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M

QUICKLOGIC
PREFIX:QL
8X12B-*CG68C
8X12B- *CG681
8X12B-*CG68M
8X12B- *PF100C
8X12B-*PFlOOI
8X12B-*PL44C
8X12B- *PL441
8X12B-*PL68C
8X12B- *PL681
12X16B- *CG84C
12X16B-*CG84I
12X16B- *CG84M
12X16B- *PF100C
12X16B-*PFlOOI
12X16B- *PL68C
12X16B- *PL68I
12X16B- *PLS4C
12X16B- *PLS4I
16X24B-*GC144C
16X24B- *GC144I
16X24B-*GC144M
16X24B- *PF100C
16X24B- *PFlOOI
16X24B- *PF144C
16X24B-*PF144I
16X24B- *PLS4C
16X24B- *PLS4I
24X32B- *GC44C
24X32B-*GC1441
24X32B-*GC144MB
24X32B-*GC208C
24X32B- *GC2081
24X32B-*GC208M
24X32B-*PF144C
24X32B- *PF144I
24X32B- *PF208C
24X32B- *PF2081

CYPRESS
PREFIX:CY
7C382A-*GC
7C382A-*GI
7C382A - *GMB
7C382A-*AC
7C382A-*AI
7C381A-*JC
7C381A-*JI
7C382A-*JC
7C382A-*JI
7C384A-*GC
7C384A-*GI
7C384A - *GMB
7C384A-*AC
7C384A-*AI
7C383A-*JC
7C383A-*JI
7C384A-*JC
7C384A-*JI
7C386A-*GC
7C386A-*GI
7C386A-*GMB
7C385A-*AC
7C385A-*AI
7C386A-*AC
7C386A-*AI
7C385A-*JC
7C385A-*JI
7C387A-*GC
7C387A-*GI
7C387A-*GMB
7C388A-*GC
7C388A-*GI
7C388A-*GMB
7C387A-*AC
7C387A-*AI
7C388A-*AC
7C388A-*AI

TI
PREFIX:JBP
PREFIX:PAL
PREFIX:SM
PREFIX:SMJ
PREFIX:SN
PREFIX:TBP
PREFIX:TIB
PREFIX:TMS
SUFFIX:F
SUFFIX:J
SUFFIX:N
22V10AC
22VlOAM
PAL16LS-5C

CYPRESS
PREFIX:CY
SUFFIX:P
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:F
SUFFIX:L
SUFFIX:D
PALC22VlO-25C
PALC22VlO-30M
PAL16LS-5C

TI
PAL16LS-7C
PAL16LS-7M
PAL16LS-10C
PAL16LS-10M
PAL16LS-12M
PAL16LS-15C
PAL16LS-15M
PAL16LS-20M
PAL16LS-25C
PAL16LS-30M
PAL16LSA-2C
PAL16LSA-2M
PAL16LSAC
PAL16LSAM
PAL16R4-5C
PAL16R4-7C
PAL16R4-7M
PAL16R4-lOC
PAL16R4-lOM
PAL16R4-12M
PAL16R4-15C
PAL16R4-15M
PAL16R4-20M
PAL16R4-25C
PAL16R4-30M
PAL16R4A-2C
PAL16R4A-2M
PAL16R4AC
PAL16R4AM
PAL16R6-5C
PAL16R6-7C
PAL16R6-7M
PAL16R6-lOC
PAL16R6-lOM
PAL16R6-12M
PAL16R6-15C
PAL16R6-15M
PAL16R6-20M
PAL16R6- 25C
PAL16R6-30M
PAL16R6A-2C
PAL16R6A-2M
PAL16R6AC
PAL16R6AM
PAL16R8-5C
PAL16R8-7C
PAL16R8-7M
PAL16R8-lOC
PAL16R8-10M
PAL16R8-12M
PAL16R8-15C
PAL16R8-15M
PAL16R8-20M
PAL16R8-25C
PAL16R8-30M
PAL16R8A-2C
PAL16R8A-2M
PAL16R8AC
PAL16R8AM
PAL20LSA - 2C
PAL20LSA - 2M
PAL20LSAC

Note: Unless othetwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* - meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConly

1-12

CYPRESS
PAL16LS-7C
PAL16LS-7M
PAL16LS-7C
PAL16LS-lOM
PAL16LS-lOM
PAL16LS-7C
PAL16LS-lOM
PALC16LS-20M
PALC16LS-25C
PALC16LS-30M
PALC16LS-35C
PALC16LS-40M
PALC16LS- 25C
PALC16LS-30M
PAL16R4-5C
PAL16R4-7C
PAL16R4-7M
PAL16R4-7C
PAL16R4-lOM
PAL16R4-lOM
PAL16R4-7C
PAL16R4-lOM
PALC16R4-20M
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PAL16R6-5C
PAL16R6-7C
PAL16R6-7M
PAL16R6-7C
PAL16R6-lOM
PAL16R6-lOM
PAL16R6-7C
PAL16R6-10M
PALC16R6-20M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PAL16R8-5C
PAL16R8-7C
PAL16R8-7M
PAL16R8-7C
PAL16R8-10M
PAL16R8-lOM
PAL16R8-7C
PAL16R8-10M
PALC16R8-20M
PALC16R8-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8-40M
PALC16R8-25C
PALC16R8-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C

Product Line Cross Reference
TI
PAL20L8AM
PAL20LlOA-2C
PAL20LlOA - 2M
PAL20LlOAC
PAL20LlOAM
PAL20R4A - 2C
PAL20R4A - 2M
PAL20R4AC
PAL20R4AM
PAL20R6A-2C
PAL20R6A - 2M
PAL20R6AC
PAL20R6AM
PAL20R8A - 2C
PAL20R8A - 2M
PAL20R8AC
PAL20R8AM
PAL22VlO-7C
PAL22VIO-7C
PAL22VlO-15C
PAL22VlO-20M
PAL22VlOAC
PAL22VIOAC
PAL22VlOAM
PAL22VIOAM
PAL22VIOC
PAL22VlOC

CYPRESS

PLDC20GIO-30M
PLDC20GlO-25C
PLDC20GlO- 30M
PLDC20GlO-35C
PLDC20G 10-30M
PLDC20GlO-25C
PLDC20G 10-30M
PLDC20GlO- 25C
PLDC20G 10- 30M
PLDC20GlO-25C
PLDC20GlO- 30M
PLDC20GlO-25C
PLDC20GlO- 30M
PLDC20GlO-25C
PLDC20GlO- 30M
PLDC20GlO- 25C
PLDC20G 10- 30M
PALC22VlOD -7C
PAL22VlOC-7C
PALC22VlOB-15C
PALC22VlOB-20M
PALC22VIO- 25C
PALC22VlOL- 25C
PALC22VlO-25MB
PALC22VIO- 30MB
PALC22VlO-35C
PALC22VlOL- 35C

a

1-13

Military Overview
at Group A are listed in a table at the end of each final data sheet,
with a notation as to which specific Group A test subgroups apply.

Features
Cypress products are designed using our state-of-the-art CMOS
and BiCMOS processes, and they must meet the full - 55 to + 125
degrees Celsius operational criteria for military use. The commitment continues with the 1986 DESC certification of our automated U.S. facility in San Jose, California. Cypress meets the
stringent quality and reliability requirements of MIL-STD-883D
and MIL-I-38535B and participates in each of the military processing programs: MIL-STD-883D compliant, SMD (Standardized Military Drawing), and QML.

Assembly Traceability Code@)
Cypress Semiconductor places an assembly traceability code on
every military package that is large enough to contain the code.
The ATC automatically provides traceability for that product to
the individual wafer lot. This unique code provides Cypress with
the ability to determine which operators and equipment were used
in the manufacture of that product from start to finish.

Quality and Reliability

Product Design
Every Cypress product is designed to meet or exceed the full temperature and functional requirements of military product. This
means that Cypress builds military product as a matter of course,
rather than as an accidental benefit of favorable test yield. Designs
are being carried out in our industry-leading O.65-micron CMOS
and BiCMOS processes. Cypress is able to offer a family of products that are industry leaders in density, low operating and standby
current, and high speed. In addition, our technology results in
products with very small manufacturable die sizes that will fit into
the LCCs and flatpacks so often used in military programs.

DESC-Certified Facility
On May 8, 1986, the Cypress facility at 3901 North First Street in
San Jose, California was certified by DESC for the production of
JAN Class B CMOS Microcircuits. And, most recently, on February 16, 1994, Cypress received QML (Qualified Manufacturers
List) transitional certification from DESC to the requirements of
MIL- I - 38535B. This certification allows Cypress to continue to
produce JAN products as well as manufacture devices listed on the
QML. QML certification attests to Cypress' commitment to quality and reliability through the use of statistical process control and
total quality management. Our wafer fabrication facilities are
Class 10 (San Jose) and Class 1 (Round Rock, TX and Bloomington, MN) manufacturing environments and our assembly facility is
also a clean room.

Datasheet Documentation
Every Cypress final data sheet is a corporate document with a revision history. The document number and revision appears on each
final data sheet. Cypress maintains a listing of all data sheet documentation and a copy is available to customers upon request. This
gives a customer the ability to verify the current status of any data
sheet and it also gives that customer the ability to obtain updated
specifications as required.
Every final data sheet also contains detailed Group A subgroup
testing information. All of the specified parameters that are tested

MIL-STD-883D and MIL-I-38535B spell out the toughest of
quality and reliability standards for military products. Cypress
products meet all of these requirements and more. Our in-house
quality and reliability programs are being updated regularly with
tighter and tighter objectives. Please refer to the chapter on Quality, Reliability, and Process Flows for further details.

Military Product Offerings
Cypress offers three levels of processing for military product.
First, all Cypress products are available with processing in full
compliance with MIL-STD-883, Revision D.
Second, selected products are available to the SMD (Standardized
Military Drawing) program administered by DESC. These products are not only fully MIL-STD-883D compliant, but are also
screened to the electrical requirements ofthe applicable military
drawing.
Third, selected products are available as JAN devices. These products are processed in full accordance with MIL-I -38535B and they
are screened to the electrical requirements of the applicable JAN
slash sheet.

Product Packaging
All packages for military product are hermetic. A look at the package appendix in the back of this data book will give the reader an
appreciation of the variety of packages offered. Included are cerDIPs, windowed CerDIPs, leadless chip carriers (LCCs), windowed leadless chip carriers, cerpaks, windowed cerpaks, quad
cerpaks, windowed quad cerpaks, bottom-brazed flatpacks, and
pin grid arrays.

Summary
Cypress Semiconductor is committed to the support of the military marketplace. Our commitment is demonstrated by our product designs, our DESC-certified facility, our documentation and
traceability, our quality and reliability programs, our support of all
levels of military processing, and by our leadership in special
packaging.

Assembly Traceability Code is a trademark of Cypress Semiconductor Corporation.

1-14

II

-.,~

Military Product Selector Guide

,CYPRESS
PLDs
Organization
PAL20
PALC20
PALC20
PLD24
PLD24
PLDC24
PLD24
PLDC24
PLD24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC28
PLDC28
PLDC28
PLDC28
PLDC28
PLD28

16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
22VlOC-Macrocell
22V10C-Macrocell
22VlO-Macrocell
22VlO-Macrocell
22VlO-Macrocell
22VlO-Macrocell
22V10-Macrocell
22V10-Macrocell
22VlOD-Macrocell
20G 10-Generic
20RA10-Asynchronous
7C330-State Machine
7C330-State Machine
7C331-Asynchronous
7C331-Asynchronous
7C332-Combinatorial
7C335-Synchronous

Pins
20
20
20
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
28S
28S
28S
28S
28S
28S

Part Number
PAL16XX
PALC16XX
PALC16XX
PAL22VlOC
PAL22VPlOC
PALC22VlO
PALC22VlOB
PALC22VlO
PALC22VlOB
PALC22VlOB
PALC22VlOB
PALC22VlOD
PLDC20G10
PLD20RA10
CY7C330
CY7C330
CY7C331
CY7C331
CY7C332
CY7C335

JAN/SMD
Number!l]"
5962-92338(0)
5962-88678(W)
5962-88713(0)
5962-91760(0)
5962-91760(0)
5962-87539(W)
5962-87539(W)
5962-88670(0)
5962-88670(0)
M38510/507(W)
M3851 0/508( 0)
5962-89841(0)
5962-88637(0)
5962-90555(0)
5962-89546(W)
5926-90802(0)
5962-90754(W)
5962-89855(0)
5962-91584(W)
5862-9451O(W)

Speed (ns/MHz)
tpD=7,1O
tpD = 20,30
tpD = 20,30
tpD/S/CO = 10/3.6/7.5
tpD/S/CO = 10/3.6/7.5
tPD/S/CO = 25/18/15
tPD/S/CO = 20/17/15
tpD/S/CO = 25/18/15
tpD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/S/CO = 10/6/7
tPD/S/CO = 20/17/15
tpD/SU/CO = 20/10/20
50,40,28 MHz
50,40,28 MHz
tpD = 25, 30, 40
tpD = 25,30,40
tpD = 20,25,30
fMAX5 = 66.6,50,83

Icc

(rnA@ns/MHz)

883
Availability

180@7
70@20
70@20
190@1O
190@1O
100@25
100@20
100@25
120@15
120@15
120@15
130@1O
80@30
100@25
180@40MHz
180@40MHz
200@20MHz
200@20MHz
200@24MHz
160@ 66.6 MHz

Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now

CPLDs
Organization
MAX28
MAX40
MAX68
MAX84
MAX100
PLDC28
FrAsH370
-44
FrAsH370
-44
FrAsH370
-84
FLAsH370
-84
FrAsH370
-160
FrAsH370
-160
FrAsH370
-240
FrAsH370
-160
FrAsH370

Pins

Part Number

7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C346-128 Macrocell
7C361-State Machine
7C371-32 Macrocell

28S
40/44
68
84
84/100
28S
44

CY7C344
CY7C343
CY7C342
CY7C341
CY7C346
CY7C361
CY7C371

7C372-64 Macrocell

44

CY7C372

7C373-64 Macrocell

84

CY7C373

7C374-128 Macrocell

84

CY7C374

7C375-128 Macrocell

160

CY7C375

7C376-192 Macrocell

160

CY7C376

7C377-192 Macrocell

240

CY7C377

7C378-256 Macrocell

160

CY7C378

7C379-256 Macrocell

240

CY7C379

-240

JAN/SMD
Number ll ]*
5962-9061l(W)
5962-92158(W)
5962-89468(W)
5962-92062(W)
5962-91344(W)
5962-94684(0)

Icc

Speed (ns/MHz)

(rnA@ns/MHz)

883
Availability

tpD=25,35
tpD = 25,30,35
tpD = 30,35,40
tpD = 30,35,40
tpD = 30,35
100,83,66 MHz
fMAX/tS/tco = 83MHz/
10/10
fMAX/tS/tco= 83MHz/
8/8
fMAX/tS/tco = 83MHz/
8/8
fMAX/tS/tco = 83MHz/
8/8
fMAX/tS/tco = 83MHz/
8/8
fMAX/tS/tco = 83MHz/
12/12
fMAX/tS/tco=83MHz/
12/12
fMAX/tS/tco = 83MHz/
12/12
fMAX/tS/tco = 83MHz/
12/12

220@25
225@25
320@30
480@30
320@35
150@100MHz
260@83

Now
Now
Now
Now
Now
Now
Now

Speed (ns/MHz)

(rnA@ns/MHz)

883
Availability

300@83

3094

300@83

3094

370@83

Now

370@83

Now

300(fBD

4095

300(fBD

4095

300(fBD

2095

300(fBD

2095

FPGAs
Organization
1KFPGA
2KFPGA
4KFPGA

CMOS8x12
CMOS 12x16
CMOS 16x24

8KFPGA

CMOS 24x32

Pins
68
84
145/
160
145/
160/
208

Part Number

JAN/SMD
Number!l]*

Icc

CY7C382A
CY7C384A
CY7C386A

-0,-1
-0,-1
-0,-1

20
20
20

3094
4094
Now

CY7C387N8A

-0,-1

20

1095

1-15

·

~.;~

'CYPRESS

Military Product Selector Guide

Notes:

The Cypress facility at 3901 North First Street in San Jose, CA is DESC-certified for JAN class B production.
All of the above products are available with processing to MIL-STD-883D at a minimum. Many of these products are also available either to SMD
(Standardized Military Drawings) or to JAN slash sheets.
The speed and power specifications listed above cover the full military temperature range.
22S stands for
24S stands for
28S stands for
32S stands for

22-pin 300-mil DIP.
24-pin 300-mil DIP.
28-pin 300-mil DIP.
32-pin 300-mil DIP.

a

1-16

Military Ordering Information
Cypress Semiconductor fully supports the DESC standardized
Military Drawing Program for devices that are compliant to the
Class B requirements of MIL-STD-883D.

Listed below are the SMDs for which Cypress is an approved
source of supply. Please contact your local Cypress representative for the latest SMD update.

DESC SMD (Standardized Military Drawing) Approvals[1]
Package [3)
SMDNumber
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-88637
5962-88637
5962-88637
5962-88637
5962-88637
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713
5962-88713

01LX
013X
02LX
023X
03LX
04LX
043X
01KX
01 LX
02KX
02LX
023X
01KX
01LX
013X
02KX
02LX
023X
03KX
03LX
04KX
04LX
043X
05KX
05LX
053X
01XX
02XX
03RX
03XX
04RX
04XX
07XX
09RX
09XX
10RX
lOXX
llRX
11 XX
12RX
12XX
01RX
05RX
05XX
06RX
07RX
07XX
08RX
08XX
09RX
09XX
lORX
lOXX
11RX
11XX
12RX
12XX

Cypress [2)
Part Number
PALC22V10-25WMB
PALC22VlO-25QMB
PALC22VlO- 30WMB
PALC22VlO- 30QMB
PALC22V10-40WMB
PALC22VlOB-20WMB
PALC22V10B-20QMB
PLDC20G 10-40KMB
PLDC20G10-40DMB
PLDC20G 10-30KMB
PLDC20GlO-30DMB
PLDC20GlO-30LMB
PALC22V10-25KMB
PALC22V10-25DMB
PALC22VlO-25LMB
PALC22VlO- 30KMB
PALC22V10- 30DMB
PALC22VlO-30LMB
PALC22VlO-40KMB
PALC22V10-40DMB
PALC22VlOB- 20KMB
PALC22V10B- 20DMB
PALC22V10B-20LMB
PALC22V10B-15KMB
PALC22VlOB-15DMB
PALC22V10B -15LMB
PALC16L8-40QMB
PALC16R8-40QMB
PALC16R6-40WMB
PALC16R6-40QMB
PALC16R4-40WMB
PALC16R4-40QMB
PALC16R6- 30QMB
PALC16L8-20WMB
PALC16L8-20QMB
PALC16R8-20WMB
PALC16R8-20QMB
PALC16R6-20WMB
PALC16R6-20QMB
PALC16R4-20WMB
PALC16R4-20QMB
PALC16L8-40DMB
PALC16L8- 30DMB
PALC16L8- 30LMB
PALC16R8- 30DMB
PALC16R6- 30DMB
PALC16R6- 30LMB
PALC16R4- 30DMB
PALC16R4- 30LMB
PALC16L8-20DMB
PALC16L8-20LMB
PALC16R8-20DMB
PALC16R8-20LMB
PALC16R6-20DMB
PALC16R6-20LMB
PALC16R4-20DMB
PALC16R4-20LMB

Description

1Ype

24.3 DIP
28SLCC
24.3 DIP
28 S LCC
24.3 DIP
24.3 DIP
28 S LCC
24CP
24.3 DIP
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
24CP
24.3 DIP
28S LCC
24CP
24.3 DIP
28SLCC
20SLCC
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20S LCC
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20S LCC
20.3 DIP
20SLCC
20.3 DIP
20.3 DIP
20SLCC
20.3 DIP
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20S LCC
20.3 DIP
20SLCC
20.3 DIP
20S LCC

W14
Q64
W14
Q64
W14
W14
Q64
K73
D14
K73
D14
L64
K73
D14
L64
K73
D14
L64
K73
D14
K73
D14
L64
K73
D14
L64
Q61
Q61
W6
Q61
W6
Q61
Q61
W6
Q61
W6
Q61
W6
Q61
W6
Q61
D6
D6
L61
D6
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61

1-17

Product
Description
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD
20-Pin CMOS PLD

--

-.;~

Military Ordering Information

'CYPRESS

DESC SMD (Standardized Military Drawing) Approvals[l]

(continued)

Package[3]
SMDNumber
5962-89468
5962-89468
5962-89468
5962-89546
5962-89546
5962-89546
5962-89546
5962-89546
5962-89546
5962-89546
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-90555
5962-90555
5962-90555
5962-90555
5962-90555
5962-90555
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-91584
5962-91584
5962-91584
5962-91584
5962-91584

01XX
01YX
01ZX
01XX
02XX
02YX
023X
03XX
03YX
033X
01KX
01LX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
05KX
05LX
053X
06KX
06LX
063X
01MYX
OlMZX
OlM3X
02MXX
02MYX
02MZX
03MXX
03MYX
03MZX
03M3X
01 LX
02KX
02LX
023X
03KX
03LX
OlMYX
OlMZX
02MYX
02MZX
02M3X
03MXX
03MYX
03MZX
03M3X
01MYX
01MZX
02MYX
02MZX
02M3X

Cypress [2]
Part Number
CY7C342-35RMB
CY7C342-35HMB
CY7C342-35TMB
CY7C330-28WMB
CY7C330-40WMB
CY7C330-40TMB
CY7C330-40QMB
CY7C330-50WMB
CY7C330-50TMB
CY7C330-50QMB
PALC22V10D-30KMB
PALC22VlOD- 30DMB
PALC22VlOD-30LMB
PALC22VIOD- 20KMB
PALC22VlOD-20DMB
PALC22V10D- 20LMB
PALC22VlOD-15KMB
PALC22V1·0D-15DMB
PALC22VlOD-15LMB
PALC22VlOD- 25KMB
PALC22VlOD-25DMB
PALC22VlOD - 25LMB
PALC22VlOD-15KMB
PALC22VlOD-15DMB
PALC22VlOD-15LMB
PALC22VlOD-lOKMB
PALC22VlOD -lODMB
PALC22VlOD-10LMB
CY7C331-40KMB
CY7C331-40YMB
CY7C331-40LMB
CY7C331-30DMB
CY7C331-30KMB
CY7C331-30YMB
CY7C331-25DMB
CY7C331-25KMB
CY7C331-25YMB
CY7C331-25LMB
PLDC20RAlO-35DMB
PLDC20RAlO- 25KMB
PLDC20RA10- 25DMB
PLDC20RAlO- 25LMB
PLDC20RAlO-20KMB
PLDC20RAlO-20DMB
CY7C331-40TMB
CY7C331-40HMB
CY7C331-30TMB
CY7C331-30HMB
CY7C331-30QMB
CY7C331- 25WMB
CY7C331-25TMB
CY7C331-25HMB
CY7C331-25QMB
CY7C332-25TMB
CY7C332-25HMB
CY7C332-20TMB
CY7C332- 20HMB
CY7C332-20QMB

Description

1YPe

Product
Description

68PGA
68S01
68QFP
28.3 DIP
28.3 DIP
28CP
28SLCC
28.3 DIP
28CP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28 SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28S LCC
24CP
24.3 DIP
28SLCC
28CP
28 SJCQ
28S LCC
28.3 DIP
28CP
28 S JCQ
28.3 DIP
28CP
28 S JCQ
28SLCC
24.3 DIP
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28CP
28 SJCQ
28CP
28 SJCQ
28SLCC
28.3 DIP
28CP
28 SJCQ
28SLCC
28CP
28 S JCQ
28CP
28SJCQ
28 SLCC

H81
R68
T91
W22
W22
T74
Q64
W22
T74
Q64
K73
D14
L64
K73
D14
L64
K73
D14
L64
K73
D14
L64
K73
D14
L64
K73
D14
L64
K74
Y64
L64
D22
K74
Y64
D22
K74
Y64
L64
D14
K73
D14
L64
K73
D14
T74
H64
T74
H64
Q64
W22
T74
H64
Q64
T74
H64
T74
H64
Q64

128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
PLD State Machine
PLD State Machine
PLD State Machine
PLD State Machine
PLD State Machine
PLD State Machine
PLD State Machine
CMOSEEPLD
CMOSEEPLD
CMOS EE PLD
CMOSEEPLD
CMOS EE PLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOS EE PLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOSEEPLD
CMOS EE PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous CMOS OTP PLD
Asynchronous CMOS OTP PLD
Asynchronous CMOS OTP PLD
Asynchronous CMOS OTP PLD
Asynchronous CMOS OTP PLD
Asynchronous CMOS OTP PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD

1-18

II

~~

Military Ordering Information

,CYPRESS

DESC SMD (Standardized Military Drawing) Approvals[1]

(continued)

Package[3]
SMDNumber
5962-91760
5962-91760
5962-91760
5962-91760
5962-91760
5962-91760
5962-92062
5962-92062
5962-92062
5962-92062
5962-92158
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-92338
5962-93144
5962-93144
5962-93144
5962-93144

OlM3X
02M3X
03M3X
04M3X
05M3X
06M3X
OlMXX
01MYX
02MXX
02MYX
02MXX
01MRX
01MSX
01MXX
02MRX
02MSX
02MXX
03MRX
03MSX
03MXX
04MRX
04MSX
04MXX
05MRX
05MSX
05MXX
06MRX
06MSX
06MXX
07MRX
07MSX
07MXX
08MRX
08MSX
08MXX
01MZX
01MUX
02MZX
02MUX

Cypress [2]
Part Number
PAL22VI0C-15LMB
PAL22VI0C-12LMB
PAL22VI0C-lOLMB
PAL22VPlOC-15LMB
PAL22VPI0C-12LMB
PAL22VPlOC-I0LMB
CY7C341-40HMB
CY7C341-40RMB
CY7C341- 30HMB
CY7C341-30RMB
CY7C343-30HMB
PALI6L8-lODMB
PAL16L8-lOKMB
PALI6L8-10LMB
PALI6R8-lODMB
PALI6R8-10KMB
PALI6R8-lOLMB
PALI6R6-lODMB
PALI6R6-10KMB
PALI6R6-lOLMB
PAL16R4-lODMB
PALI6R4-10KMB
PALI6R4-lOLMB
PAL16L8-7DMB
PALI6L8-7KMB
PALI6L8-7LMB
PALI6R8-7DMB
PAL16R8-7KMB
PALI6R8-7LMB
PALI6R6-7DMB
PALI6R6-7KMB
PALI6R6-7LMB
PALI6R4-7DMB
PALI6R4-7KMB
PALI6R4-7LMB
CY7C346-35RMB
CY7C346- 35HMB
CY7C346-30RMB
CY7C346 - 30HMB

Description

1Ype

28 SLCC
28SLCC
28SLCC
28SLCC
28SLCC
28SLCC
84SJCQ
84PGA
84 SJCQ
84PGA
44 SJCQ
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
100PGA
84 S JCQ
lOOPGA
84SJCQ

L64
L64
L64
L64
L64
L64
H84
R84
H84
R84
H67
D6
K71
L61
D6
K71
L61
D6
K71
L61
D6
K71
L61
D6
K71
L61
D6
K71
L61
D6
K71
L61
D6
K71
L61
RI00
H84
RlOO
H84

Product
Description
BiCMOS OTP PLD
BiCMOS OTP PLD
BiCMOS OTP PLD
BiCMOS OTP PLD
BiCMOS OTP PLD
BiCMOS OTP PLD
192-Macrocell UV EPLD
192-Macrocell UV EPLD
192-Macrocell UV EPLD
192-Macrocell UV EPLD
64-Macrocell UV EPLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
20-Pin BiCMOS PLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD

Notes:
1. Devices listed have been approved by DESC for the SMD
indicated as of the date of publication. Contact your local Cypress
representative, or the Cypress SMD Hotline at 408/943-2716, for
the latest update.
2. Use the SMD part number as the ordering code.

3. Package:

SMD Hotline: 408/943-2716

1-19

24.3 DIP = 24-pin 0.300" DIP;
24.6 DIP = 24-pin 0.600" DIP;
28 R LCC = 28 terminal rectangular LCC,
S = Square LCC, TLCC = Thin LCC
24 CP = 24-pin ceramic flatpack (Configuration 1);
FP = brazed flatpack;
PGA = Pin Grid Array.

~~

Military Ordering Information

?CYPRESS

JAN M38510 Qualifications
Package [3]
JAN Number

Cypress[2]
Part Number

Description

'lYpe

Product
Description

Qualification
Status

JM 3851O/5070lBLA
JM 3851O/5070lB3A
JM 38510/50702BLA
JM 38510/50702B3A
JM 38510/50703BLA
JM 38510/50703B3A
JM 38510/50704BLA
JM 38510/50704B3A
JM 3851O/5080lBLA
JM 3851O/5080lBKA
JM 3851O/5080lB3A
JM 38510/50802BLA
JM 38510/50802BKA
JM 38510/50802B3A
JM 38510/50803BLA
JM 38510/50803BKA
JM 38510/50803B3A
JM 38510/50804BLA
JM 38510/50804BKA
JM 38510/50804B3A

PALC22VlOB - 30WMB
PALC22VIOB-30QMB
PALC22VIOB-25WMB
PALC22VlOB - 25QMB
PALC22VlOB - 20WMB
PALC22VIOB - 20QMB
PALC22VlOB -15WMB
PALC22VlOB-15QMB
PALC22VlOB - 30DMB
PALC22VIOB-30KMB
PALC22VIOB-30LMB
PALC22VlOB-25DMB
PALC22VlOB- 25KMB
PALC22VIOB-25LMB
PALC22VlOB - 20DMB
PALC22VlOB-20KMB
PALC22VlOB-20LMB
PALC22VIOB-15DMB
PALC22VIOB-15KMB
PALC22VIOB-15LMB

24.3 DIP
28SLCC
24.3 DIP
28S LCC
24.3 DIP
28SLCC
24.3 DIP
28 S LCC
24.3 DIP
24CP
28S LCC
24.3 DIP
24CP
28S LCC
24.3 DIP
24CP
28SLCC
24.3 DIP
24CP
28SLCC

W14
Q64
W14
Q64
W14
Q64
W14
Q64
D14
K73
L64
D14
K73
L64
D14
K73
L64
D14
K73
L64

CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSUVPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD
CMOSPLD

Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified

1-20

a

==~PRESS

Military Ordering Information

SMD Ordering Information

---[L--

5962-XXXXX 01

LX

LEAD FINISH
A = Solder Dip
B = TinPlate
C = Gold
X = Don't Care (The letter "X" will not be marked on the device, but will be
replaced with the actual lead finish designation.)
PACKAGE TYPE (Not a complete list)
V = 18-pin 0.300 DIP
J =
R = 20-pin 0.300 DIP
Q =
S = 20-pin Cerpack
K =
2 =
W = 22-pin 00400 DIP
3 =
L = 24-pin 0.300 DIP

24-pin 0.600 DIP
40-pin 0.600 DIP
24-pin Cerpack
20-pin SQ LCC
28-pin SQ LCC

X, Y, Z, U, T, M, Nand 4, 5, 6, 7, 8, 9 = Non-dedicated package designations
and will vary per drawing.
L--_ _ _ DEVICE CLASS DESIGNATOR
No character = Old (Pre March 1990) SMD
= New "One Part-One Part Number" System SMD, Class B
M
1--_ _ _ _ _ DEVICE TYPE
' - - - - - - - - - - DRAWING NUMBER
'-------------DRAWINGPREFIX
5962 = Federal Stock Class (FSC) for microcircuits. Pre-1985 drawings do
not have this prefix.

Cypress Military Marking Information
Manufacturer's identification:
Cypress Logo, CYPRESS, CYP, and CY are trademarks of Cypress Semiconductor Corporation.
Manufacturer's designating symbol or CAGE CODE:
Designating symbol = CETK or ETK
CAGE CODE/FSCM Number

= 65786

Country of origin:
USA = United States of America
THA

= Thailand

In general, the codes for all products (except modules) follow the format below.
PAL&PLD
PREFIX DEVICE
'PALC'
PALC
PLDC
CY
PALCE

SUFFIX

~ '-20 DMB i
22VlO
20GIO
7C330
16V8

-15
-20
-50
-25

WMB
WMB
DMB
DMB

FAMILY
PAL 20
PAL 24 VARIABLE PRODUCT TERMS
GENERIC PLD 24
PLD SYNCHRONOUS STATE MACHINE
FLASH-ERASABLE PAL20

e.g., PALC16R8-20DMB
Cypress FSCM #65786

1-21

Small PLDs 2
fI

.z;p

~PRESS

Section Contents

Small PLDs (Programmable Logic Devices)

Page Number

Introduction to Cypress PLDs .............................................................................. 2-1
Device
PAL20 Series
PALC20 Series
PALCE16V8
PALCE20V8
PLDC20GlO
PLDC20G10B
PLD20GlOC
PLDC20RAlO
PALC22VlO
PALC22VlOB
PAL22VlOC
PAL22VPlOC
PAL22VlOCF
PAL22VPlOCF
PALC22VlOD
PAL22VlOG
PAL22VPlOG
CY7C330
CY7C331
CY7C332
CY7C335
CY7C258
CY7C259

Description
4.5-ns, Industry-Standard PLDs 16L8, 16R8, 16R6, 16R4 ............................ 2-6
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
Flash Erasa:ble, Reprogrammable CMOS PAL Device .............................. 2-30
Flash Erasable, Reprogrammable CMOS PAL Device .............................. 2-38
ttMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-39
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 2-39
Generic 24-Pin PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
Reprogrammable Asynchronous CMOS Logic Device ............................. 2-57
Reprogrammable CMOS PAL Device ........................................... 2-68
Reprogrammable CMOS PAL Device ................................. " ........ 2-69
Universal PAL Device ........................................................ 2-70
Universal PAL Device
2-70
Universal PAL Device ........................................................ 2-81
Universal PAL Device ........................................................ 2-81
Flash Erasable, Reprogrammable CMOS PAL Device .................... " ........ 2-82
Universal PAL Device ........................................................ 2-91
Universal PAL Device ........................................................ 2-91
CMOS Programmable Synchronous State Machine ........... . . . . . . . . . . . . . . . . . . .. 2-101
Asynchronous Registered EPLD .............................................. 2 -112
Registered Combinatorial EPLD .............................................. 2-126
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-136
2K x 16 Reprogrammable State Machine PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151
2K x 16 Reprogrammable State Machine PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-151

~~

Introduction to Cypress PLDs

; CYPRESS

fixed OR array. The sum of these can be expressed in a Boolean
transfer function and is limited only by the number of product
terms available in the AND-OR array. A variety of different sizes
and architectures are available. This allows for more efficient logic
optimization by matching input, output, and product terms to the
desired application.

Cypress PLD Family Features
Cypress Semiconductor's PLD family offers the user a wide range
of programmable logic solutions that incorporate leading-edge circuit design techniques as well as diverse process technology capabilities. This allows Cypress PLD users to select PLDs that best suit
the needs of their particular high-performance system, regardless
of whether speed, power consumption, density, or device flexibility
are the critical requirements imposed by the system.
Cypress offers enhanced-performance industry-standard 20- and
24-pin device architectures as well as proprietary 28-pin application-tailored architectures. The range of technologies offered includes leading-edge 0.8-micron CMOS EPROM for high speed,
low power, and high density, 0.65-micron FLASH technology for
high speed, low power and electrical alterability, and 0.5-micron
BiCMOS for high-speed, power-sensitive applications.
The reprogrammable memory cells used by Cypress serve the same
purpose as the fuse used in most bipolar PLD devices. Before programming, the AND gates or product terms are connected via the
reprogrammable memory cell to both the true and complement inputs. When the reprogrammable memory cell is programmed, the
inputs from a gate or product term are disconnected. Programming
alters the transistor threshold of each cell so that no conduction
can occur, which is equivalent to disconnecting the input from the
gate or product term. This is similar to "blowing" the fuses ofBiCMOS or bipolar fusible devices, which disconnects the input gate
from the product term. Selective programming of each of these reprogrammable memory cells enables the specific logic function to
be implemented by the user.
The programmability of Cypress's PLDs allows the users to customize every device in a number of ways to implement their unique
logic requirements. Using PLDs in place of SSI or MSI components results in more effective utilization of board space, reduced
cost and increased reliability. The flexibility afforded by these
PLDs allows the designer to quickly and effectively implement a
number of logic functions ranging from random logic gate replacement to complex combinatorial logic functions.
The PLD family implements the familiar "sum of products" logic
by using a programmable AND array whose output terms feed a

PLD Notation
To reduce confusion and to have an orderly way of representing the
complex logic networks, logic diagrams are provided for the various part types. In order to be useful, Cypress logic diagrams
employ a common logic convention that is easy to use. Figure 1
shows the adopted convention. In part (a), an "x" represents an
unprogrammed EPROM cell or intact fuse link that is used to perform the logical AND operation upon the input terms. The convention adopted does not imply that the input terms are connected on
the common line that is indicated. A further extension of this convention is shown in part (b), which shows the implementation of a
simple transfer function. The normal logic representation of the
transfer function logic convention is shown in part (c).

PLD Circuit Configurations
Cypress PLDs have several different output configurations that
cover a wide spectrum of applications. The available output configurations offer the user the benefits of both lower package counts
and reduced costs when used. This approach allows designers to select PLDs that best fit their applications. An example of some of
the configurations that are available are listed below.

Programmable I/O
Figure 2 illustrates the programmable I/O offered in the Cypress
PLD family that allows product terms to directly control the outputs ofthe device. One product term is used to directly control the
three-state output buffer, which then gates the summation of the
remaining terms to the output pin. The output of this summation
can be fed back into the PLD as an input to the array. This programmable I/O feature allows the PLD to drive the output pin
when the three-state output is enabled or, when the three-state
output is disabled, the I/O pin can be used as an input to the array.

INTRO-1

(a)

INTRO-2

(b)

INTRO-3

(c)

Figure 1. Logic Diagram Conventions

2-1

Introduction to Cypress PLDs

rcYPRESS
INPUTS FEEDBACK AND /0

11111111111111111111111111111

B"o
INTRO-4

Figure 2. Programmable I/O

INPUTS, FEEDBACK, AND I/O

.--

CLOCK

~

.......

~b-

.---

I- D

QI--

~

~~

-

......
INTRO-5

Figure 3. Registered Outputs with Feedback

Registered Outputs with Feedback
Figure 3 illustrates the registered outputs of!ere.d on a nUI?ber of
the Cypress PLDs which allow any of these CIrcUIts to fll:nctlOn as. a
state sequencer. The summation of the product terms IS stored m
the D-type output flip-flop on the rising edge of the system c~ock.
The Q output of the flip-flop can then be gated to the outpu~ pm by
enabling the three-state output buffer. The output of the flIp-flop
can also be fed back into the array as an input term. The output
feedback feature allows the PLD to remember and then alter its
function based upon that state. This circuit can be used to execute
such functions as counting, skip, shift, and branch.

Programmable Macrocell
The programmable macrocell, illustrated in Figure 4, pro~i.des the
capability of defining the architecture of each output mdlVldually.
Each of the potential outputs may be specified to be "registered"
or "combinatorial." Polarity of each output may also be individually selected allowing complete flexibility of output configuration.
Further configurability is provided through "array" configurable
"output enable" for each potential output. This feature allows the
outputs to be reconfigured as inputs on an individual basis or alternately used as a bidirectionalI/O controlled by the programmable
array (see Figure 5).

Buried Register Feedback
The CY7C331 and CY7C335 PLDs provide registers that may be
"buried" or "hidden" by electing feedback of the register output.
These buried registers, which are useful in state mach~nes, may.be
implemented without sacrificing the use of the associated devIc~
pin as an input. In previous PLDs, when the feedback path was activated, the input pin-path to the logic array was blocked. The p~o­
prietary CY7C335 reprogram~able sync~ronous st~te mac~me
macrocell illustrates the shared mput multiplexer, WhICh proVIdes
an alternative input path for the I/O pin associated with a buri~d
macrocell register (Figure 6). Each pair of macrocells shares an m-

put multiplexer, and as long as alternate macro cells are buried, up
to six of the twelve output registers can be buried wi~hout the lo~s
of any I/O pins as inputs. The CY7C335 also con tams four dedIcated hidden macro cells with no external output that are used as
additional state registers for creating high-performance state machines (Figure 7).

Asynchronous Register Control
Cypress also offers PLDs that may be used in asynchronous systems in which register clock, set, and reset are controlled by the
outputs ofthe product term array. The clock signal is created by t~e
processing of external inputs and/or internal feedback by the lOgIC
ofthe product term array, whichis then routed to the register clock.
The register set and reset are similarly controlled by product ter.m
outputs and can be triggered at any time indepen?ent of the regISter clock in response to external and/or feedback mputs process~d
by the logic array. The proprietary CY7C.3~ 1 Asynchr?no~s RegI~­
tered PLD, for which the I/O macrocellis Illustrated mFlgure 8, IS
an example of such a device. The register clock, set, and reset functions of the CY7C331 are all controlled by product terms and are
dependent only on input signal timing an? combi~atorial ~elay
through the device logic array to enable theIr respective functions.

Input Register Cell
Other Cypress PLDs provide input re~ister cells to captur~ short
duration inputs that would not otherwIse be present at the mputs
long enough to allow the device to respond. The proprietary
CY7C335 Reprogrammable Synchronous State Mac~ine pr0v.ides
these input register cells (Figure 9).The clock for !he mPl!t regIster
may be provided from one of two external clock mput pms selectable by a configuration bit, C4, dedicated for this purpose .for each
input register. This choice of input register clock allows SIgnals to
be captured and processed from two independent sy~tem sou~ces,
each controlled by its own independent clock. These mput regIster
cells are provided within I/O macrocells, as well as for dedicated input pins.

2-2

Introduction to Cypress PLDs
CLOCK AR

I

DE
0

I

..L.L

>-

I- MACRO·
CELL

~>

~ r--

11

SP

~

INTRO-6

Figure 4. Programmable Macrocell

co
OUTPUT REG
BYPASS MUX
OUTPUT
ENABLE t - - - - t - .
~O~U~T_P_U_T_E_N_A_B_LE_PR_O~D_U~C~T_T_E_R_M_ _ _ _ _ _ _O, MUX
PIN 14: OE

SET PRODUCT TERM

.
:

SCLK1
SCLK2
RESET PRODUCT TERM
TO ARRAY

o
FEED
BACK
MUX

C1
ICLK1

INPUT REGISTER

o

C2

D

o

ICLK2

TO ARRAY
INTRO-7

CX (11 -16)

FROM ADJACENT MACROCELL

Figure S. CY7C33S I/O Macrocell

2-3

liD

Introduction to Cypress PLDs

FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
INTRO-8

Figure 6. CY7C335 I/O Macrocell Pair Shared Input MUX

SET PRODUCT TERM

S

>-----1

D

Q

i
SCLK1
SCLK2

RESET PRODUCT TERM

INTRO-9

Figure 7. CY7C335 Hidden Macrocell

2-4

---

-'f~

Introduction to Cypress PLDs

; CYPRESS

PIN 14 _ _ _---J
OE
MUX

SET PRODUCT TERM

S
Q I--....- - - - . . . . J

D

OUTPUT
REGISTER

CLOCK PRODUCT TERM

R

RESET PRODUCT TERM

__

~~

r ________

~FEEDBACK

S

MUX

D

Q

INPUT
REGISTER

R
INTRO-10

TO SHARED
INPUT MUX

Figure 8. CY7C331 Registered Asynchronous Macrocell

1

.----

INPUT REGISTER

INPUT
PIN

--ICLK1

ICLK2

Q

D

0
-..

.--INPUT
REG
BYPASS
MUX

1

I-

2_

C7

0'----INPUT
CLOCK I-MUX

TO ARRAY

1

t>
INTRO-11

C6

Figure 9. CY7C335 Input Macrocell

Document #: 38-00165-B

2-5

J:"AL®~U ~erleS

16L8/16R8
16R6/16R4

4.5-ns, Industry-Standard PLDs
Features

Functional Description

• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tPD = 4.5 ns
-ts = 2.5 ns
- fMAX = 142.9 MHz (external)
• Popular industry standard architectures
• Power-up RESET
• High reliability
- Proven Ti-W fuses
- AC and DC tested at the factory

Cypress PAL20 Series devices consist of
the PAL16L8, PAL16R8, PAL16R6, and
PAL16R4. Using BiCMOS process and
Ti-W fuses, these devices implementthe familiar sum-of-products (AND-OR) logic
structure.
The PAL device is a programmable AND
array driving a fixed OR array. The AND
array is programmed to create custom
product terms while the OR array sums selected terms at the outputs.

• Security fuse

The product selector guide details all the
different options available. All the regis-

tered devices feature power-up RESET.
The register Q output is set to a logic LOW
when power is applied to the devices.
A security fuse is provided on all the devices to prevent copying of the device fuse
pattern.

Programming
The PAL20 Series devices can be programmed using the Impulse programmer
available from Cypress Semiconductor.
See third party information in thirdparty
tool section for further programmer information.

Logic Symbols and DIP Pinouts
16R8

16R4

16R6

11

16L8

Vee

Vee

Vee

Vee

o
o
o
o
o
o
o
o

I/O

I/O
I/O

o

DE

o
o
~LLl~=

I/O

o

I/O

0

"---'''~--'"''ll/O

o
o
o

o
o

I/O

I/O

I/O

I/O

I/O

o

0

LLr'--LJ~=

I/O

Vss
20-2

20-3

20-4

20-Pin PLCC/LCC Pinouts

o
o
o
o
o

o

20-5

o
o
o
o

o
o
o
o

1/0

I/O
I/O
I/O
I/O
I/O

20-6

20-7

20-8

28-Pin PLCC (-4 Speed Bin Only) Pinouts
()

---y--I

Vss

m:

0
Vss
0

Vss

o~o~o~o

I

I

CP

Vss

CP

Vss

CP

Vee
0
Vss
0
Vss

OE

Vee

OE

Vee

I/O

I/O

1/0

I/O

Vss
0
Vss

Vss
0
Vss

Vss

Vss

0000000 000

~

~

PAL is a registered trademark of Monolithic Memories Inc.

2-6

I

Vee
0
Vss

0
Vss

I/O

I/O

I/O

I/O

Vss

Vss

Vss

Vss

o~o~o~o

~

Vss

20-11

g~g~g~g

>

>

>

20-12

--.

PAL20 Series
16L8/16R8
16R6/16R4

~.;:Z

'CYPRESS
Function Selection Guide
Device

Dedicated Inputs

Outputs

Product Terms/Outputs

Feedback

PAL16L8

10

6 comb.
2 comb.

7
7

I/O

Enable
prog.
prog.

-

PAL16R8

8

8 reg.

8

reg.

pin

PAL16R6

8

6 reg.
2 comb.

8
7

reg.
I/O

pin
prog.

PAL16R4

8

4 reg.
4 comb.

8
7

reg.
I/O

pin
prog.

Speed Selection Guide (Commercial -4/-S/-7, Military -7/-10)
Speed Bin

tpD (ns)

ts (ns)

teo (ns)

fMAX (MHz)

Iec (rnA)

-4

4.S

2.5

4.S

142.9

180

-s

S

2.S

S

133.3

180

-7

7

3.S

6

lOS.3

180

-10

10

4.5

7

87.0

180

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -6SoC to + IS0°C
Ambient Temperature with
Power Applied ........................ -SsoC to + 12SoC
Supply Voltage to Ground Potential ......... -O.SV to + 7.OV
DC Voltage Applied to Outputs
in High Z State ..................... -O.SV to Vee + O.SV
DC Input Voltage ................... -1.2V to Vee + O.SV

DC Input Current
(except during programming) ... . . . . . . .. - 30 rnA to + S rnA
Operating Range
Ambient
Temperature

Vee

O°C to +70°C

SV±S%

-SSOC to + 12SoC

SV ±10%

Range
Commercial
Military[l]

DC Electrical Characteristics Over the Operating Range
Parameter
VOH

VOL

Description
Output HIGH Voltage

Output LOW Voltage

Min.

Test Conditions
Vee = Min.,
VIN = Vm or VIL

IOH = -3.2 rnA

Commercial

IOH= -2mA

Military

Vee = Min.,
VIN = Vm or VIL

IOL = 24 rnA

Commercial

IOL = 12 rnA

Military

Max.

Unit
V

2A

O.S

V

Vm

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for All Inputs[2]

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for All Inputs[2]

IIX

Input Leakage Current

OAV ~ VIN ~ 2.7Y, Vee = MaxJ3]

II

Maximum Input Current

VIN

Ioz

Output Leakage Current

Vee = Max., Vss ~ VOUT ~ Vee[3]

-100

+100

IlA

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.SV[4]

-30

-130

rnA

Icc

Power Supply Current

Vee = Max., VIN = GND, Outputs Open

180

rnA

= S.SY, Vee =

Notes:
L TA is the "instant on" case temperature.
2. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
3. I/O pin leakage is the worse case of IlL and IOZL (or IIH and IOZH).

2.0
-2S0

Max.

4.

2-7

V
0.8

V

SO

IlA

1

rnA

Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.

PAL20 Series
16L8/16R8
16R6/16R4
Capacitance[5]
Parameter

Description

qN

Input Capacitance

I CPo OE
I 11 - Is

Test Conditions

1Ypical

TA = 25°C, f = 1 MHz,
VIN = 0, Vee = 5.0V

8

pF

5

pF

8

pF

Output Capacitance

COUT

Unit

AC Test Loads and Waveforms
5V

ls1

f.r.
1

OUTPUT

J

_ R2

-

TEST POINT

CL

-

Commercial

Specification

Sl

tpD, teo

Closed

tpzx, tEA

Z.H: Open
Z. L: Closed

tpxz, tER

H. Z: Open
L. Z: Closed

Military

CL

Rl

R2

Rl

R2

Measured Output Value

50pF

200Q

390Q

390Q

750Q

1.5V
1.5V

5pF

H • Z: VOH - 0.5V
L. Z: VOL + 0.5V

Switching Characteristics Over the Operating Range[6]

-s

-4

-7

-10

Description

Min.

Max.

Min.

Max.

tpD

Input or Feedback to Non-Registered Output 16L8,
16R6,16R4

1

4.5

1

5

2

7

2

10

ns
ns

Parameter

Min. Max. Min. Max.

Unit

tEA

Input to Output Enable 16L8, 16R6, 16R4

2

6.5

2

6.5

2

7

2

10

tER

Input to Output Disable Delay 16L8, 16R6, 16R4

2

5.5

2

5.5

2

7

2

10

ns

tpzx

Pin 11 to Output Enable 16R8, 16R6, 16R4

1

6

1

6

2

7

2

10

ns

tpxz

Pin 11 to Output Disable 16R8, 16R6, 16R4

1

5

1

5

2

7

2

10

ns

teo

Clock to Output 16R8, 16R6, 16R4

1

4.5

1

5

2

6

2

7

ns

tSKEWR

Skew Between Registered Outputs 16R8, 16R6,
16R4[5]

1

ns

0.75

1

1

ts

Input or Feedback Set-Up Time 16R8, 16R6, 16R4

2.5

2.5

3.5

4.5

ns

tH
tp

Hold Time 16R8, 16R6, 16R4

0

0

0

0

ns

Clock Period (teo + ts)

7

7.5

9.5

11.5

ns

tw

Clock Width

3

3

3.5

5

fMAX

Maximum
Frequency

I External Feedback (l/tp )[7]
I Internal Feedback[5, 8]

Notes:
5. Tested initially and after any design or process changes that may affect
these parameters.
6. See the last page of this specification for Group A subgroup testing information.
7. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.

8.

2-8

ns

142.9

133.3

105.3

87

175

175

150

133

MHz

This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal-only feedback can
operate.

PAL20 Series
16L8/16R8
16R6/16R4

-'i~

·

'CYPRESS
Switching Waveforms[9]
INPUTS I/O, ........................REGISTERED
FEEDBACK ~'-""-"'-¥

CP

REGISTERED -----"""!"'"~:-7!"_
OUTPUTS

II

----------~~~

COMBINATORIAL
OUTPUTS

----------------------~~~~

REGISTERED
OUTPUT 1 _

t_SKEW~R

__

__

REGISTERED
OUTPUT 2

20-13

Note:

9.

Input rise and fall time is 2-ns typical.

Power-Up Reset
The power-up reset feature ensures that all flip-flops will be reset
to LOW after the device has been powered up. The output state
will be HIGH due to the inverting output buffer. This feature is
valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways

Parameter Symbol

Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:
1. The Vee must be monotonic.
2. Following reset, the clock input must not be driven from LOW
to HIGH until all applicable input and feedback set-up times
are met.

Parameter Description

tpR

Power-Up Reset Time

ts

Input or Feedback Set-Up Time

tWL

Clock Width LOW

Max.
1000

I
I

Unit
ns

See Switching Characteristics

Power-Up Reset Waveform
POWER

~~------------------------------------------------------Vcc

_______________4_V~,~~_______________

tpR ______________

~.I

REGISTERED
ACTIVE LOW
OUTPUT

CLOCK
20-14

2-9

=:;;p::-

PAL20 Series
16L8/16R8
16R6/16R4

~

7CYPRESS
16L8 Logic Diagram 20-Pin DIP/PLCC/LCC (28-Pin PLCC) Pinouts
10

@]

1
0

(24)

3

4

7

8

11

12

15

16

19

20

23

24

27 28

31

0

rJ-

·

·

I-

0----Ci:::
(25)

2
512

,......,

··

I--

736

4

--<

(27)

768

··
·

.....992

5

2

(28)

1024

~~

~248

6

2

(2)

1280

~~

~504

7

2

(3)

1536

·
··

,.......

~760

(4)

2

... 1792

~O16

9

<>.

A

~

1/°6

16

1/0 5

(16)

15
(14)

14

1/03

(12)

13
(10)

12
(8)
11

19

(7)

(5)

Vss

iJ
rJ.

·

··

Is

17
(18)

...

···

8

iJ
iJ
iJ

18
(20)

,

··
·

16

Os

<>.1---

.....480

(26)

19
(22)

256

··
·

3

Vee

(1,23

3

4

7

8

11

12

15 16

19

20

23

24

27 28

31
20-15

(6,9,11,13,15,17,19,21)

2-10

PAL20 Series
16L8/16R8
16R6/16R4

-.,~

7 CYPRESS

16R8 Logic Diagram 20-Pin DIP/PLCC/LCC (28-Pin PLCC) Pinouts
elK 1
0

(24)

3

4

7

8

11

12

15

16

19

20

23

24

27 28

§] Vee

31

(1,23

0

~
(25)

.....,

~

~

··
·

~

512

A

"i.

··
·

~

...<'

(27)

768

.....

··

~

(16)

.....992

5

.... ...

.?
~

(28)

1024

···

l.-/

(14)

r!..248

6

.A

.... .....

~
~

(2)

1280

···

~~
l.-/

.,

1504

16

7

L

(3)

1536

~~
l.-/

~

(4)

A

"i.

£

1792

·
··

9

A

~

"i.

~

(8)

---I

19

18
(20)

~~
Q

736

4

..<

(27)

768

~92
r

(28)

.....

.2

'"

·
6

U
.A

" .2

< ....

r

(2)

L,.../'

~04

7
r

.L

')..

1536

·
~60

8
(4)

.;?

'""'"'"'

016

9

..<

(5)

Vss

~

~

~

~J
~J

05

(16)

(14)

(12)

13
(10)

'"

1792

··
·

18

~

~

1280

··
·

(3)

~

~

1024

1248

15

(18)

~

·

5

1/08

(22)

34

7

8

11

12

15 16

19

20

23 24

27 28

12
(8)

- 1500V input protection from
electrostatic discharge
-100% AC and DC tested
-10% power supply tolerances
- High noise immunity
- Security feature prevents pattern
duplication
-100% programming and functional
testing

= 70mA

• Commercial and military temperature
range

Cypress PALC20 Series devices are highspeed electrically programmable and UVerasable logic devices produced in a proprictary N-well CMOS EPROM process.
These devices utilize a sum-of-products
(AND-OR) structure providing users with
the ability to program custom logic functions serving unique requirements.

Logic Symbols and DIP and SOJ Pinouts
16R8

16L8

16R4

16R6

vee

Vee

Vee

Vee

0

I/O

0

0
0
0
0

0
0
0
0

I/O
I/O

0
0

0
0

0

I/O

I/O
I/O

OE

OE

OE

vss

I/O
I/O
I/O
I/O
I/O
I/O

0
0
0
0

0
C20-4

C20-3

C20·2

LCC Pinouts

8

80

0..
__ 0::>
0

0..
__ 0::>

0..

80

0

_ __ .J;?o

_-0::>:::::.

~

32,1,2019
18
17
16
15
14
910111213

a
a
a
a
a

32,1,2019
18
17
16
15
14
910111213

a
a
a

- ~I~--

C20·5

- ~I~go

C20-6

3 2/,2019
18

0

17

16
15
14
910111213

0

- ~I~gg

PAL is a registered trademark of Advanced Micro Devices.

2-16

I/O

a
a
a
a

C20-7

I

I/O
I/O
I/O
I/O
I/O

4
5
6
7
8
-~

-og

C20-8

-.,~

PALC20 Series

'CYPRESS

EPROM technology is the basis for a superior product with inherent advantages in reliability, testability, programming, and
functional yield. EPROM technology has the inherent advantage
that all programmable elements may be programmed, tested, and
erased during the manufacturing process. This also allows the device to be 100% functionally tested during manufacturing. An
ability to preload the registers of registered devices during the
testing operation makes the testing easier and more efficient.
Combining these inherent and designed-in features provides an
extremely high degree of functionality, programmability and assured AC performance, and testing becomes an easy task.
The register preload allows the user to initialize the registered devices to a known state prior to testing the device, significantly simplifying and shortening the testing procedure.

Functional Description (continued)
All combinatorial outputs on the 16R6 and 16R4 as well as 6 of
the combinatorial outputs on the 16L8 may be used as optional
inputs. All registered outputs have the Q bar side of the register
fed back into the main array. The registers are automatically initialized upon power-up to Q output LOW and Q output HIGH.
All unused inputs should be tied to ground.
All PALC devices feature a security function that provides the
user with protection for the implementation of proprietary logic.
When invoked, the contents of the normal array may no longer be
accessed in the verify mode. Because EPROM technology is used
as a storage mechanism, the content of the array is not visible under a microscope.
Cypress PALC products are produced in an advanced 1.2-micron
N-well CMOS EPROM technology. The use of this proven

II

Commercial and Industrial Selection Guide
Generic
Part
Number
16L8
16R8
16R6

16R4

tpD (ns)

Icc (rnA)
Logic

Output
Enable

Outputs

(8) 7-wide
Programmable ~6~ Bidirectional
AND-OR-Invert
2 Dedicated
(8) 8-wide AND-OR Dedicated
Registered Inverting
(6) 8-wideAND-OR Dedicated
Registered Inverting
(2) 7-wide
Programmable Bidirectional
AND-OR-Invert
(4) 8-wideAND-OR Dedicated
Registered Inverting
(4) 7-wide
AND-OR-Invert

L

Com'I/Ind

-25

-35

45

70

25

45

70

45

70

45

70

ts (ns)
-25

-35

teo (ns)
-25

-35

35

-

-

-

-

-

-

20

30

15

25

25

35

20

30

15

25

25

35

20

30

15

25

-40

-20

Programmable Bidirectional

Military Selection Guide
Generic
Part
Number
16L8
16R8
16R6

16R4

tpD (ns)
Logic

Output
Enable

Icc

Outputs

(8) 7-wide
Programmable ~ 6~ Bidirectional
AND-OR-Invert
2 Dedicated
(8) 8-wide
Dedicated
Registered
AND-OR
Inverting
(6) 8-wide
Dedicated
Registered
Inverting
AND-OR
(2) 7-wide
Programmable Bidirectional
AND-OR-Invert
(4) 8-wide
Dedicated
Registered
AND-OR
Inverting
(4)7-wide
Programmable Bidirectional
AND-OR-Invert

ts (ns)

teo (ns)

(rnA)

-20

-30

-40

70

20

30

40

-

-

-

-

-

-

70

-

-

-

20

25

35

15

20

25

70

20

30

40

20

25

35

15

20

25

70

20

30

40

20

25

35

15

20

25

2-17

-20

-30

-30

-40

~

=:

PALC20 Series

rCYPRESS

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Volt~ge to Ground Potential
(Pm 20 to Pm 10) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 24 mA
DC Programming Voltage ......................... 14.0V

UV Exposure ........................... 7258 Wsec/cm 2
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA

Operating Range
Ambient
Temperature

Range
Commercial
Military!l]

O°C to +75°C

Vee
5V ±10%

-55°C to +125°C

5V ±10%

Industrial

-40°C to +85°C

Electrical Characteristics Over the Operating Range (unless otherwise noted)!2]
Parameter
VOH

VOL

Description
Output HIGH Voltage
Output LOW Voltage

Min.

Test Conditions
Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l/Ind

IOH= -2mA

Military

Vee = Min.,
VIN = VIH or VIL

IOL = 24 rnA

Com'l/Ind

IOL = 12 rnA

Military

Input HIGH Level

Guaranteed Input Logical HIGH!3] Voltage for All Inputs

VIL

Input LOW Level

Guaranteed Input Logical LOW!3] Voltage for All Inputs

IIX

Input Leakage Current

Vss ~ VIN ~ Vee

-10

Vpp

Programming Voltage

Ipp = 50 rnA Max.

13.0

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.5V[4]

Icc

Power Supply Current

All Inputs = GND, Vee = Max.,
lOUT = 0 mA!S]

2.0

Vee = Max., Vss ~ VOUT ~ Vee

V

V
0.8

V

10

f,lA

14.0

V

-300

rnA

"~'

45

mA

Com'l/Ind

70

rnA

70

mA

100

f,lA

Military
Output Leakage Current

Unit
V

0.4

VIH

loz

Max.

2.4

-100

Notes:
1.
2.
3.

TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

4.

5.

2-18

Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.
ICC(AC) = (0.6 rnNMHz) X (Operating Frequency in MHz) +
ICC(DC)- ICC(DC) is measured with an unprogrammed device.

-'i~

PALC20 Series

'CYPRESS
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[2] (continued)
Parameter

Vx

tpxz (-)

1.5V

tpxz (+)

2.6V

Output Waveform-Measurement Level
VOH 0.5V

tpzx (+)

Vthc

tpzx (-)

Vthc

tER (-)

1.5V

O.5V

VOL

0.5V

Vx
Vx

0.5V

VOH 0.5V
tER (+)

2.6V

tEA (+)

Vthc

tEA (-)

I

~

t
I
I
t

0.5V

Vx
Vx

~

0.5V

VOL

Vthc

~

0.5V

~
~
~
~
~
~
~
~

VX

C20-9

VX
C20-10

VOH
C20-11

VOL

C20-12

VX

C20-13

VX
C20-14

VOH
C20-15

VOL

C20-16

Capacitance[6]
Parameter
CIN

Description
Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

TA = 25°C, f = 1 MHz

10

pF

VIN = 0, Vee = 5.0V

10

pF

Unit

Switching Characteristics Over Operating Rangd 2, 7, 8]
Commercial/Industrial

-25
Parameter

Description

Min.

Military

-35
Min.

Max. Min.

-30

Max.

Unit

Input or Feedback to Non-Registered
Output 16L8, 16R6, 16R4

25

35

20

30

40

ns

tEA

Input to Output Enable 16L8, 16R6,
16R4

25

35

20

30

40

ns

tER

Input to Output Disable Delay 16L8,
16R6,16R4

25

35

20

30

40

ns

tpzx

Pin 11 to Output Enable 16R8, 16R6,
16R4

20

25

20

25

25

ns

tpxz

Pin 11 to Output Disable 16R8, 16R6,
16R4

20

25

20

25

25

ns

25

ns

Clock to Output 16R8, 16R6, 16R4
Input or Feedback Set-Up Time
16R8, 16R6, 16R4

15

25

20

30

Max.

Min.

-40

tpD

teo
ts

Max.

-20

15
20

20
25

35

ns

0
60

ns

tH
tp

Hold Time 16R8, 16R6, 16R4

0

0

0

0

Clock Period

35

55

35

45

tw
fMAX

Clock Width

15

Maximum Frequency

20
28.5

Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7 _ Part (a) (part (c) for military) of AC Test Loads and Waveforms is used
for all parameters except tEA, tER, tpzx and tpxz. Part (b) (part (d) for
military) of AC Test Loads and Waveforms is used for tEA, tER, tpzx
and tpxz-

12
18

8.

2-19

Max. Min.

20
28.5

ns

25
22

ns
16.5

MHz

The parameters tER and tpxz are measured as the delay from the input
disable logic threshold transition to VOH - O.SV for an enabled HIGH
output or VOL + O.5V for an enabled LOW output. Please see Electrical Characteristics for waveforms and measurement reference levels.

PALC20 Series
AC Test Loads and Waveforms
SV T-}R117SQ

SV T-}R117SQ

OUTPUT

so pF

I

=

R2133Q

I S pF

=

R2133Q

=

~R1337Q

~

C20-18
C20·17

Equivalent to:
THEVENIN EQUIVALENT MILITARY

OUTPUT

J

o------vvv----o 2.16V = Vthc

SV T-}R1337Q

OUTPUT

so pF

7SQ

OUTPUT

(b) Commercial

(a) Commercial

SV

Equivalent to:
THEVENIN EQUIVALENT COMMERCIAL

OUTPUT

R2247Q

I

-=

S pF

R2247Q

-=

(c) Military

143Q

OUTPUT

-=

o------vvv----o 2.11 V = Vthm
C20·19

(d) Military

C20·20

3.0V - - - ~-----s..
GND
C20·21

(e)

Switching Waveforms
INPUTS I/O, _ _"'""''tI.
REGISTERED
FEEDBACK ~"-¥...l.-'..~

CP

REGISTERED
OUTPUTS _ _ _ _ _-""'___

tEA
COMBINATORIAL
OUTPUTS _____________

~~~

C20·22

Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
PALC device. In addition, high ambient light levels can create
hole-electron pairs that may cause "blank" check failures or
"verify errors" when programming windowed parts. This p~e­
nomenon can be avoided by using an opaque label over the WIndow during programming in high ambient light environments.

The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV inte?sity
multiplied by exposure time) of 25 Wsec/cm2 . For an ultravIolet
lamp with a 12 mW/cm 2 power rating, the exposure would be approximately 35 minutes. The PALC device needs to be placed
within 1 inch of the lamp during erasure. Permanent damage may
result if the device is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm 2 is the recommended maximum dosage.

2-20

---:z

PALC20 Series

1 CYPRESS

Logic Diagram PALC16L8
INPUTS (0

- 31)

1
0

3

4

7

8

11

12

15

16

19

20

23

24

27 28

31

.....

0

l:M
~rJ

··
·

~

~
~

0---Ci=

.A

L....

.....

8

--..:"1--.....
~

~
~
~
~

··
·

19

18

.....a.J-

15

.A

3

..

< .....

.2
16

··
·

...r--'

23

4

24

·

··

31

5

.2

·

··

39

.2

··
·

.£...
48

··
·

14

rJ-

13

~

12

;J

55
~

56

··
·

....

63

9

15

:rJ-

~~

47

8

16

.....

40

7

....

.....

32

6

.A

~

--<'

17

<::
-v-....

~

3

4

7

8

11

12

15 16

19

20

23

24

27 28

11

31
C20-23

2-21

LZ#~

PALC20 Series

.'CYPRESS
Logic Diagram PALC16R4
INPUTS (0 - 31)

1
0

3

4

7

8

11

12

15

16

19

20

23 24

27 28

31

. ~
.-

0

·
··

l-

....

~

.
.-

8

t-

··
·

lI-

b----

15

3

L

··
·

'~

23

I

"""'I

..-

-

....

-

L

.A

....-

39

L-

~
'"""1
A

-2

-

40

·
··

~
"'V"oo.I

...?

~

~

-:=r ~~
.A

~

-v "'I

-

- ~-

48

~

~

~

~

47

J--,

··
·

..-

13

........

55

--.:;:

L

....

56

··
·

63

9

-.:::

"'V"oo.I

··
·

8

-

./

1-""""

32

7

~~

)--0,

24

31

6

,

~

··
·

5

~J

18

"""'I

16

4

19

-cJ

II-

A

-v....,

~*
-H
--.:;:

~

A

"'.....

3

4

7

8

11

12

15 16

19 20

23 24

27 28

12

11

31
C20-24

2-22

PALC20 Series
Logic Diagram PALC16R6
INPUTS (0 - 31)

1
0

3

4

7

8

11

12

15

16

19

20

23

24

27 28

31

~~

0

·

"V .......

8

I--

··

~

L....

1--1
~

.A'.

"""-I

·

I--

....

23

~

~

~

~

24

....

I-II--

·

~
~

L....i--I

31

A

5

<:
-v .....

~

~

··

~

I--

~~
i--I

39

.A

<::

~
-)0--,

""'- ~

40

···

,....

~

i--I
A

"""<;:.

~

"V .....

~

~

~

~

~

~

)-

~~

··

I-~'f..-/
~

""""'

55

£

....

56

~

A

.....

1=~

··
·

1--'

"_

12

t-+-'
,......
~

63

9

~

~

....J---<

48

8

"'"

I-I--L /

47

7

~

~

-)0--,

32

6

~

II--

16

4

~

I-

15

3

:J

~~

0--CC

19

~

~

11

·v .....

3

4

7

8

11

12

15 16

19

20

23

24

27 28

31
C20·25

2-23

E

=====;~

PALC20 Series

'CYPRESS

Logic Diagram PALC16R8
INPUTS (0 - 31)

3

4

7

8

11

12

15

16

19

20

23

24

27 28

31

3

4

7

8

11

12

15 16

19

20

23

24

27 28

31

4

&l
I

e.
C/)

:2

ffif-

5

f-

U

::::>
0

0

[

6

2-24

C20-26

·

-.;~

PALC20 Series

'CYPRESS
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.6 r - - - - - , - - - - - - - - - ,

NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4 .-------,----,----.-----.,

~ 1.2~--+--~--~---1

o

«

:2

1.01----+----JiL--+---1

a:::

oz

TA = 25°C
f = fMAX

-

1.41-~---+-------1

1.21---~--+-------I

N

:J

«

~

O.BI---7I~--t-

oz

1.01----~------1

O.BI-----+---~o;;;:---1

w

~ 1.1 ~----I---___F------l

«

~

a:

15
Ul

5:

;

UJ
0

~-----:#----------l

AMBIENT TEMPERATURE (0C)

I------+--___F--_I

:2

z

5

L

V
V
200

400

v

O.B
4.0

1.01------#-'------_1
0.9 '---_ _ _.....J...._ _ _ _ _--1
- 55
25
125
AMBIENT TEMPERATURE (OC)

" '"

~5

~O

~

5~

"ao

SUPPLY VOLTAGE (V)

/

./

~

1.1

o
w

N

:J 1.0

«

:2

""

~

a:::

o
Z

600

:~

0.9

O.B
4.0

BOO 1000

4.5

5.0

~

5.5

"
6.0

SUPPLY VOLTAGE (V)

NORMALIZED CLOCK-TO-OUTPUT
TIME vs. TEMPERATURE

1.1 .------.-----,--....-----,

a

a

o

o
UJ

u

u

~

1.01----+--...3\oc--+--_I

N

:J

:2

«

oz

o

~

a:::

a:::

o

0.9

NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE

UJ
N

UJ

~ 1.1

z

NORMALIZED CLOCK-TO-OUTPUT
TIME vs. SUPPLY VOLTAGE

1.3 . - - - - - - - , - - - - - - - - ,

«

a:
0

CAPACITANCE (pF)

NORMALIZED SET-UP TIME
vs. TEMPERATURE

o

10

o
o

0.9 '---_ _ _.....L.._ _ _ _ _---I
- 55
25
125

I-----+-----J~

""

1.2

E.

1.2

~

20

o

~

«

DELTA PROPAGATION TIME
vs. OUTPUT LOADING

1.3

1.0

N

AMBIENT TEMPERATURE (0C)

NORMALIZED PROPAGATION
DELAY vs. TEMPERATURE

1.2 i - - - - - - f - - - - - - J ' - l

1.1

:J 1.0

SUPPLY VOLTAGE (V)

oz

~
0

w

0.6'--_ _ _-'-_ _ _ _ _--'
-55
25
125

0.6'--_-'-_ _---'-_ _-'--_--'
~o
4~
5.0
5~
ao

5:

1.2

..5:?

oW

UJ
N

:J

u

NORMALIZED PROPAGATION
DELAY vs. SUPPLY VOLTAGE

1.11-----+--~----1

Z

0.9'---_--'-_ _---'--_ _-'--_--'
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)

2-25

25

125

AMBIENT TEMPERATURE (0C)

·

-.,~

PALC20 Series

'CYPRESS
Typical DC and AC Characteristics (continued)
DELTA CLOCK-TO-OUTPUT TIME
vs. OUTPUT LOADING
20.0

15.0
Ul

.s
o

~ 10.0

~

w

Cl

5.0
0.0

V

o

V

200

/'

..-

V

-

« 200

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

.s 175
rE

150

if

125

~
z

100

::>

U5

ir

50
25

400

600

800 1000

20

25

-

-

(ns)
-

-

35

-

-

-

-

0.0

-

-

100

t)

80

\.

w

'\..

'~

t)

J

1.0

if

120

w

::>
~

60

(f)

40

o

L

o 1/

140

2.0

Vee = 5.0V TA = 25°C

I-

I

::>

3.0

-

::>
::=

o

20

0

4.0

0.0

OUTPUT VOLTAGE (V)

Package
Name

"-~

1.0

2.0

Package 1:ype

70

PALC16L8-20DMB

D6

20-Lead (300-Mil) CerDlP

PALC16L8-20LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16L8-200MB

061

20-Pin Windowed Square Leadless Chip Carrier

PALC16L8- 20WMB

W6

20-Lead (300-Mil) Windowed CerDlP

PALC16L8L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALC16L8L- 25VC

V5

20-Lead (300-Mil) Molded SO]

PALC16L8L- 25WC

W6

20-Lead (300-Mil) Windowed CerDlP

PALC16L8-25PC/PI

P5

20-Lead (300-Mil) Molded DIP

PALC16L8-25VC

V5

20-Lead (300-Mil) Molded SO]

PALC16L8-25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16L8-30DMB

D6

20-Lead (300-Mil) CerDlP

PALC16L8- 30LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16L8- 300MB

061

20-Pin Windowed Square Leadless Chip Carrier

PALC16L8- 30WMB

W6

20-Lead (300-Mil) Windowed CerDlP

PALC16L8L-35PC

P5

20-Lead (300-Mil) Molded DIP

PALC16L8L- 35VC

V5

20-Lead (300-Mil) Molded SO]

PALC16L8L- 35WC

W6

20-Lead (300-Mil) Windowed CerDlP

PALC16L8- 35PC/PI

P5

20-Lead (300-Mil) Molded DIP

PALC16L8-35VC

V5

20-Lead (300-Mil) Molded SO]

PALC16L8- 35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16L8-40DMB

D6

20-Lead (300-Mil) CerDIP

PALC16L8-40LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16L8-400MB

061

20-Pin Windowed Square Leadless Chip Carrier

PALC16L8-40WMB

W6

20-Lead (300-Mil) Windowed CerDIP

45

70

45

70

2-26

"

'"""'"

3.0

4.0

OUTPUT VOLTAGE (V)

Ordering Code

70

40

/

1!z

(rnA)

70

30

----

/

75

g

I-

Ordering Information
tpD
ts
teo Icc
(ns)

/

I-

CAPACITANCE (pF)

(ns)

/"

l-

OUTPUT SOURCE CURRENT
vs. VOLTAGE

~

Operating
Range
Military

Commercial

Military

Commercial

Military

-

-,,~

PALC20 Series

'CYPRESS
Ordering Information (continued)
tpD
ts
teo
Icc

Package
Name

Package
1Ype

(ns)

(ns)

(ns)

(rnA)

Ordering Code

20

20

15

70

PALCI6R4-20DMB

D6

20-Lead (300-Mil) CerDIP

PALCI6R4- 20LMB

L61

20-Pin Square Leadless Chip Carrier

PALCI6R4-200MB

061

20-Pin WindowedSquareLeadless Chip Carrier

PALCI6R4-20WMB

W6

20-Lead (300-Mil) Windowed CerDIP

PALCI6R4L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALCI6R4L-25VC

V5

20-Lead (300-Mil) Molded SO]

PALCI6R4L- 25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R4 - 25PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALCI6R4-25VC

V5

20-Lead (300-Mil) Molded SO]

PALCI6R4- 25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALCI6R4-30DMB

D6

20-Lead (300-Mil) CerDIP

25

20

15

45

70

30

35

25

30

20

25

70

45

70

40

35

25

70

PALCI6R4-30LMB

L61

20-Pin Square Leadless Chip Carrier

PALCI6R4-300MB

061

20-Pin WindowedSquareLeadlessChip Carrier

PALCI6R4-30WMB

W6

20-Lead (300-Mil) Windowed CerDIP

PALCI6R4L-35PC

P5

20-Lead (300-Mil) Molded DIP

PALCI6R4L- 35VC

V5

20-Lead (300-Mil) Molded SO]

PALCI6R4L- 35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALCI6R4- 35PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALCI6R4- 35VC

V5

20-Lead (300-Mil) Molded SO]

PALCI6R4- 35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALCI6R4-40DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R4-40LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R4-400MB

061

20-Pin Windowed SquareLeadless Chip Carrier

PALC16R4-40WMB

W6

20-Lead (300-Mil) Windowed CerDIP

2-27

Operating
Range
Military

Commercial

Military

Commercial

Military

II

PALC20 Series
Ordering Information (continued)
tpD
(os)

(ns)

(ns)

(rnA)

20

20

15

70

25

ts

20

teo

15

Icc

45

70

30

35

25

30

20

25

70

45

70

40

35

25

70

Ordering Code

Package
Name

Package
Type

PALC16R6- 20DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R6-20LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R6- 200MB

061

20-Pin WindowedSquare Leadless Chip Carrier

PALC16R6-20WMB

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R6L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALC16R6L- 25VC

V5

20-Lead (300-Mil) Molded SO]

PALC16R6L- 25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R6- 25PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALC16R6-25VC

V5

20-Lead (300-Mil) Molded SO]

PALC16R6-25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R6-30DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R6-30LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R6-300MB

061

20-Pin WindowedSquareLeadlessChipCarrier

PALC16R6-30WMB

W6

20-Lead (300-Mil) Windowed CerDlP

PALC16R6L- 35PC

P5

20-Lead (300-Mil) Molded DIP

PALC16R6L-35VC

V5

20-Lead (300-Mil) Molded SO]

PALC16R6L- 35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R6-35PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALC16R6- 35VC

V5

.

20-Lead (300-Mil) Molded SO]

PALC16R6-35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R6-40DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R6-40LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R6-400MB

061

20-Pin WindowedSquareLeadlessChip Carrier

PALC16R6-40WMB

W6

20-Lead (300-Mil) Windowed CerDIP

2-28

Operating
Range
Military

Commercial

Military

Commercial

Military

·

-.;~

PALC20 Series

'CYPRESS
Ordering Information (continued)
tpD
(ns)

ts
(ns)

tco
(ns)

(rnA)

20

15

70

-

-

20

15

45
70

-

25

30

-

20

25

70

45
70

-

35

25

PALCI6R8-20DMB

D6

Package
lYPe
20-Lead (300-Mil) CerDIP

PALCI6R8- 20LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R8-200MB

061

20-Pin WindowedSquareLeadless Chip Carrier

PALCI6R8-20WMB

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R8L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALC16R8L- 25WC

W6

20-Lead (300-Mil) Windowed CerDIP

Icc

70

Ordering Code

Package
Name

PALC16R8-25PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALC16R8-25WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R8-30DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R8-30LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R8-300MB

061

20-Pin Windowed Square Leadless Chip Carrier

PALC16R8-30WMB

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R8L- 35PC

P5

20-Lead (300-Mil) Molded DIP

PALC16R8L-35WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R8-35PCIPI

P5

20-Lead (300-Mil) Molded DIP

PALC16R8-35WC/WC

W6

20-Lead (300-Mil) Windowed CerDIP

PALC16R8-40DMB

D6

20-Lead (300-Mil) CerDIP

PALC16R8-40LMB

L61

20-Pin Square Leadless Chip Carrier

PALC16R8-400MB

061

20-Pin WindowedSquareLeadless Chip Carrier

PALC16R8-40WMB

W6

20-Lead (300-Mil) Windowed CerDIP

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Switching Characteristics

Parameter

Subgroups

Parameter

Subgroups

VOH
VOL
VIR

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

tpD

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

VIL
IIX
Vpp
Icc
Ioz

tpzx
teo
ts
tH

Document #: 38-00001-F

2-29

Operating
Range
Military

Commercial

Military

Commercial

Military

II

PRELIMINARY

PALCEl6V8

Flash Erasable,
Reprogrammable CMOS PAL ® Device
Features

• Up to 16 input terms and 8 outputs

Functional Description

• Advanced second-generation PAL architecture
• Lowpower
- 90 rnA max. commercial (10, 15, 25
ns)
-115 rnA max. commercial (7 ns)
- 130 rnA max. military/industrial
(10, 15,25 ns)

• DIP, LCC, and PLCC available
-7.5, 10, 15, and 25 ns com'l version
5 ns teo
5 ns ts
7.5 ns tpD
125-MHz state machine

The Cypress PALCE16V8 is a CMOS
Flash Electrical Erasable second-generation programmable array logic device. It
is implemented with the familiar sum-ofproduct (AND-OR) logic structure and
the programmable macrocell.

• Quarter power version
-55 rnA max. commercial (15,25 ns)
• CMOS Flash technology for electrical
erasability and reprogrammability
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation

-10, 15, and 25 ns military/
industrial versions
7 ns teo
10 ns ts
10 ns tpD
62-MHz state machine

The PALCE16V8 is executed in a 20-pin
300-mil molded DIP, a 300-mil cerdip, a
20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip
carrier. The device provides up to 16 inputs and 8 outputs. The PALCE16V8 can
be electrically erased and reprogrammed.
The programmable macrocell enables the
device to function as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.

• High reliability
- Proven Flash technology
-100% programming and functional
testing

Logic Block Diagram (PDIP/CDIP)

1/°1

1/°0

Pin Configuration

1/°2

1/°3

1/0 4

DIP
Top View

I/Os

1/05

PLCC/LCC
Top View
0

~

CLK/lo
11
12
13
14
15
Is
17
Is

GND

1/07
1/°6
1/05
1/04
1/°3
1/°2
1/01
1/°0
OE/Ig

c..>

....

~-=d ~~

vee
13
14
15
16
17
1SVS-2

PAL is a registered trademark of Advanced Micro Devices.

2-30

1/°6
1/05
1/04
1/°3
1/02
1SVS·3

- a~~~
IX)

Cl

mOT"""

1/07

Vee

1SVS·1

PRELIMINARY

PALCEl6V8

Functional Description (continued)

Electronic Signature

The PALCE16V8 features 8 product terms per output and 32 input
terms into the AND array. The first product term in a macrocell
can be used either as an internal output enable control or as a data
product term.
There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macro cells and 16 that apply locally, two bits per macrocell. The architecture bits determine
whether the macrocell functions as a register or combinatorial with
inverting or noninverting output. The output enable control can
come from an external pin or internally from a product term. The
output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated
input. Feedback paths are selectable from either the input/output
pin associated with the macrocell, the input/output pin associated
with an adjacent pin, or from the macro cell register itself.

An electronic signature word is provided in the PALCE16V8 that
consists of 64 bits of programmable memory that can contain userdefined data.
Security Bit
A security bit is provided that defeats the readback of the internal
programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation through
the use of CMOS technology, and increased testability with Flash
reprogrammability.

fI

Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs.

Configuration Table
Devices Emulated

CGo

CGI

CLOx

0

1

0

Registered Output

Registered Med PALs

0

1

1

1

0

0

Combinatorial I/O
Combinatorial Output

Small PALs

1
1

0

1
1

Combinatorial I/O

1

Cell Configuration

Registered Med PALs

Input

Small PALs
16L8 only

MacroceII
To
Adjacent
Macrocell

DE

Vee

-=-

0 X
0

1 0
0 0
0

-=-

CG 1

ClOx
1
0 X

0

Q

0

a

ClK

CG1 for pin 13 to 18
CGo for pin 12 and 19

From
Adjacent
Pin
16V8-4

2-31

~

PRELIMINARY

-=-rcYPRESS

PALCEl6V8

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ....................... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... -0.5V to +7.0V
Output Current into Outputs (LOW) .............. 24 rnA
DC Programming Voltage ......................... 12.5V

>200mA

Latch-Up Current
Operating Range
Ambient
Temperature

Range
Commercial
Military[l]

O°C to +75°C

Vee
5V±5%

-55°C to +125°C

5V ±1O%

Industrial

-40°C to +85°C

5V ±10%

Electrical Characteristics Over the Operating Rangel 2]
Parameter
VOH

VOL

Description
Output HIGH Voltage

Output LOW Voltage

Min.

Test Conditions
Vee = Min.,
VIN = VIH or VIL
Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l

IOH= -2mA

Mil/Ind

IOL = 24 rnA

Com'l

IOL = 12 rnA

Mil/Ind

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

2.0

VIL[4]

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[3]

-0.5

IIL[S]

Input or I/O LOW Leakage OV ~ VIN ~ VIN (Max.)
Current

IIH

Input or I/O HIGH Leakage 3.5V ~ VIN ~ Vee
Current

Ise

Output Short Circuit Current Vee = Max., VOUT = 0.5V[6,7]

Icc

Operating Power Supply
Current

Vee = Max.,
VIL = Ov, VIH = 3V,
10,15,25 ns
Output Open,
f = 15 MHz
-15L, -25L
(counter)
10,15,25 ns

-30
Com'l

Mil/Ind

Unit
V

0.5

VIH

7 ns

Max.

2.4

V

V
0.8

V

-100

!-LA

10

!-LA

-90

rnA

115

rnA

90

rnA

55

rnA

130

mA

Capacitance[7]
Parameter
CIN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

'!Yp.
5
5

Unit
pF
pF

Endurance Characteristics[7]
Description
Minimum Reprogramming Cycles

Test Conditions
Normal Programming Conditions

Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.

5.
6.
7.

2-32

The leakage current is due to the internal pull-up resistor on all pins.
Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

~

ff-.,~

PRELIMINARY

,CYPRESS

PALCEl6V8

AC Test Loads and Waveforms
ALL INPUT PULSES

3.0V--90%

GND

1SV8-5

5V

151

EI

OUTPUT f - T 1 TEST POINT
_

-

.•
Specification

R2

r

CL
1SV8-S

-

Military

Commercial
SI

tpD, teo

Closed

tpzx, tEA

Z.H: Open
Z. L: Closed

tpxz, tER

H.Z: Open
L. Z: Closed

CL

Rl

R2

Rl

R2

Measured Output Value

SOpF

200Q

390Q

390Q

7S0Q

l.SV
l.SV

H • Z: VOH - O.5V
L. Z: VOL + O.SV

SpF

2-33

..::$iiii!iiiia

'~PRESS

PRELIMINARY

PALCEl6V8

Commercial Switching Characteristics[2]
16V8-7
Parameter

Description

16V8-10

16V8-15

16V8-25

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

7.5

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay[8, 9]

tpzx

OE to Output Enable

6

10

15

20

ns

tpxz

OE to Output Disable

6

10

15

20

ns

tEA

Input to Outp'ut
Enable Delay[7]

9

10

15

25

ns

tER

Input to Output
Disable Delay[7, 10]

9

10

15

25

ns

tco

Clock to Output Delay[8, 9]

2

12

ns

ts

Input or Feedback
Set-Up Time

5

2

5

7

2

10

12

7.5

2
15

ns

tH

Input Hold Time

a

a

a

a

ns

tp

External Clock Period
(tco + ts)

10

14.5

22

27

ns

tWH

Clock Width HIGH[7]

4

6

8

12

ns

4

6

8

12

ns

tWL

Clock Width LOW[7]

fMAXl

External Maximum
Frequency (l!(tco + ts)W' 11]

100

69

45.5

37

MHz

fMAX2

Data Path Maximum
Frequency
(l!(tWH + twdW' 12]

125

83

62.5

41.6

MHz

fMAX3

Internal Feedback Maximum
Frequency (l!(tCF + tS»[7, 13]

125

74

50

40

MHz

tCF

Register Clock to
Feedback Inpud 7, 14]

tpR

Power-Up Reset Time[7]

3

6

1

1

Notes:
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. This parameteris measured as the time after 0 E pin or internal disable
input disables or enables the output pin. This delay is measured to the
point at which a previous HIGH level has fallen to 0.5 volts below VOH
min. or a previous LOW level has risen to 0.5 volts above VOL max.

8
1

10
1

ns
flS

11. This specification indicates the guaranteed maximum frequency at which
a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which
a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 10 above) minus tS.

2-34

-'f~

•

PRELIMINARY

-=-,p CYPRESS

PALCEl6V8

Military and Industrial Switching Characteristics[2]
16V8-10
Parameter

Description

16V8-15

16V8-25

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay!8, 9]

tpzx

OE to Output Enable

10

15

20

ns

tpxz

10

15

20

ns

tEA

OE to Output Disable
Input to Output Enable Delayl7j

10

15

tER

Input to Output Disable Delayl7, lOj

10

15

25
25

ns
ns

12

ns

tco

Clock to Output Delayl~, '1j

2

ts

Input or Feedback Set-Up Time

10

12

15

tH
tp

Input Hold Time

0

0

0

ns

17

22

27

ns

6

8

12

ns

+ ts)

7

2

10

2

ns

tWH

External Clock Period (tco
Clock Width HIGHl7j

tWL

Clock Width LOWl7j

6

8

12

ns

fMAXl

External Maximum Frequency
(lI(tco + tS)[7, 11]

58

45.5

37

MHz

fMAX2

Data Path Maximum Frequency
(lI(twH + twL»[7, 12]

83

62.5

41.6

MHz

fMAX3

Internal Feedback Maximum
Frequency (lI(tcF + tS»[7, 13]

62.5

50

40

MHz

tCF

Register Clock to
Feedback Input!7, 14]

tpR

Power-Up Reset Time l7j

6
1

10

8
1

1

ns
~s

Switching Waveform
INPUTS, I/O, - - -..........
REGISTERED
FEEDBACK _ _ _-'-v

CP

REGISTERED
OUTPUTS _ _ _ _ _ _....L..;.~

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _""'-K-V
16va·?

Power-Up Reset Waveform
~~9~0~%--------------------------VCC

POWER
10%
SUPPLY VOLTAGE ------......;;;.,.-

~------------- tpR------------~~

REGISTERED -------+-+-------~~~~~~~~~~~--------­
ACTIVE LOW
OUTPUTS -------+-+-------~~~~~~~~~
CLOCK

tpR MAX = 1 !J.s

2-35

16va·a

I

PRELIMINARY

PALCEl6V8

Functional Logic Diagram for PALCEl6V8

r-

1

"~
00
64
128

0

INPUT LINE
NUMBERS

PRODUCT LINE FIRST CELL NUMBERS
3

4

7

8

11 12

15 16

19 20

Vee

I
23 24

2728

31.--...J

32
96

192 160

~

A

-""I-

=f>

256 288
320
384 352
448 416
.....

480

1- ~f>

3
512

4

.A

5

1152

~

J

1280
1344
1408

~

:~ ~

1376

A

1600
1664

1632

1- =>

8

1856
1920

1888

.A

'-I>

~.I--

J

~

MC1
CL1 2054
CLO 2126
PTD 2176
2183 ~

:~ ~

1824

1984 1952
.... 2016

9

MC2
CL1 2053
CLO 2125
PTD 2168
2175 ~

:~ -@

1568

1728
...... 1760

1792

->

'50..1- -

J

1536

.1- I-

1312

1472 1440
.... 1504

7

j4-

~I>

1184
12261248

6

18

MC3 ICL1 2052
CLO 2124 rPTD 2160
2167 14-

1056
1120

.A

~

~

1024
1088

-

~I>

~I- t-

J

rr-

MC4 FCL1 2051
CLO 2123 rPTD 2152
2159
~

800
832
896 864

A

~

~I>

768

960 928
.... 992

r-@]

~~

~.I- I-

J

MC6
CL1 2049
CLO 2121
PTD 2136
2143

~~

MC5 FCL1 2050
CLO 2122 rPTD 2144
2151
~

544
576
640 608
704 672
.... 736

MC7
CL1 2048
CLO 2120
PTD 2128
2135

0

3 4

IT I

7

8

11 12

15 16

19 20

23 24

2728

T

M

'1" Of' '1
'1"' '1" ",
'~'
BYTE, BYTE 1 I BYTE 2 I BYTE 3 I BYTE 4 I BYTE 5 I BYTE 6 I BYTE : I

MSB LSB

MSB

2-36

-

'r

31

USER ELECTRONIC SIGNATURE ROW

00

MCO
CL1 2055
CLO 2127
PTD 2184
2191 ~

LSB

11

GLOBAL ARCH BITS
CG o=2192
CG1=2193

16V8-9

==

PRELIMINARY

-?cYPRESS

PALCEl6V8

Ordering Information
(rnA)

tpD
(ns)

ts
(ns)

teo
(ns)

115

7.5

5

5

ICC

90

10

130
130
90

10
10
15

130
130
55

15
15
25

55

25

90

25

130
130

25
25

7.5
10
10
12
12
12
12
15
15
15
15

7
7
7
10
10
10
10

12
12
12
12

Ordering Code

Package
Name

Package 1Ype

PALCE16V8-7JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-7PC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-lOJC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-lOPC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-lOJI

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-lOPI

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-lODMB

D6

20-Lead (300-Mil) CerDIP

PALCE16V8-lOLMB

L61

20-Pin Square Leadless Chip Carrier

PALCE16V8-15JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-15PC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-15JI

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-15PI

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-15DMB

D6

20-Lead (300-Mil) CerDIP

PALCE16V8-15LMB

L61

20-Pin Square Leadless Chip Carrier

PALCE16V8L- 25JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8L- 25JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8L- 25PC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8- 25JC

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-25PC

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-25JI

J61

20-Lead Plastic Leaded Chip Carrier

PALCE16V8-25PI

P5

20-Lead (300-Mil) Molded DIP

PALCE16V8-25DMB

D6

20-Lead (300-Mil) CerDIP

PALCE16V8-25LMB

L61

20-Pin Square Leadless Chip Carrier

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH
VOL
VIR
VIL
IIX
Ioz
Icc

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11

teo
ts
tH

Document #: 38-00364-A

2-37

Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Commercial
Commercial
Industrial
Military

ADVANCED INFORMATION

PALCE20V8

Flash Erasable,
Reprogrammable CMOS PAL ® Device
Features
• Advanced second·generation PAL
architecture
• Lowpower
- 90 rnA max. commercial
(10, 15, 25 ns)
-115 rnA max. commercial (7 ns)
-130 rnA max. military/industrial
(15,25 ns)
• Quarter power version
- 55 rnA max. commercial
• CMOS Flash technology for electrical
erasability and reprogrammability
• User-programmable macrocell
- Output polarity control

- Individually selectable for regis.
tered or combinatorial operation
• DIP, LCC, and PLCC available
-7.5, 10, 15, and 25 ns com'l version
5 ns tco
5 ns ts
7.5 ns tpD
125·MHz state machine
- 10, 15, and 25 ns military/
industrial versions
7 ns tco
10 ns ts
10 ns tpD
62·MHz state machine
• High reliability
- Proven Flash technology
-100% programming and functional
testing

Functional Description
The Cypress PALCE20V8 is a CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin
300-mil molded DIP, a 300-mil cerdip, a
28-lead square ceramic leadless chip carrier, and a 28-lead square plasticleaded chip
carrier. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can
be electrically erased and reprogrammed.
The programmable macrocell enables the
device to function as a superset to the familiar 24-pin PLDs such as 20LB, 20R8,
20R6,20R4.

Logic Block Diagram (PDIP/CDIP)

01:/111

112

1100

110 2

1/0 1

Pin Configuration

110 3

1/05

1/0 4

110 6

110 7

113

Vee
20V8-1

PLCC/LCC
Top View

DIP
Top View

0

CLK/lo

1

24

11
12

23
22

13
14
15

21
20

16
17

Is
19
110

GND

19

g u U MO
..£-I..!""uzY..!""""

Vee
113

1/0 7
1106
1105
110 4
110 3
110 2
1/0 1
110 0

13
14
15

1/0 6
1/0 5
1/0 4

NC

NC

1/0 3
110 2
1/0 1

16
17

Is

112

01:/113

'" 0

0

u

~

008

-.r~z~..!""""

20V8-2

PAL is a registered trademark of Advanced Micro Devices, Inc.

Document #: 38-00367-A

2-38

20V8-3

PLDC20G 10B/PLDC20G10

CMOS Generic 24-Pin
Reprogrammable Logic Device
Features
• Fast
- Commercial: tpD = 15 ns, teo = 10
ns, ts = 12 ns
- Military: tPD = 20 ns, teo = 15 ns,
ts = 15 ns
• Lowpower
- Icc max.: 70 rnA, commercial
- Icc max.: 100 rnA, military
• Commercial and military temperature
range
• User-programmable output cells
- Selectable for registered or combinatorial operation
- Output polarity control
- Output enable source selectable
from pin 13 or product term

• Generic architecture to replace standard logic functions including: 20LI0,
20L8, 20R8, 20R6, 20R4, 12L10, 14L8,
16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE
product term per output
• CMOS EPROM technology for
reprogrammability
• Highly reliable
- Uses proven EPROM technology
- Fully AC and DC tested
- Security feature prevents logic pattern duplication

- ± 10% power supply voltage and
higher noise immunity

Functional Description
Cypress PLD devices are high-speed electrically programmable logic devices. These
devices utilize the sum-of-products (ANDOR) structure providing users the ability to
program custom logic functions for unique
requirements.
In an unprogrammed state the AND gates
are connected via EPROM cells to both
the true and complement of every input.
By selectively programming the EPROM
cells, AND gates may be connected to either the true or complement or disconnected from both true and complement inputs.
Cypress PLDC20G 10 uses an advanced
O.S-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent

Logic Block Diagram

I/OE

II0g

I/Os

1/0 7

1/06

1105

1/03

1/0 4

I/O,

1/0 2

Vee

1/0 0

20G10-1

Pin Configurations

Q

Z

(f

(f

880

_ _ Q>

Q

80

__

_ _ _ u~:::;;:.:::::.

::0::0

NC

PLDC20G10
PLDC20G10B

I

JEDEC PLCC[l)
Top View

STDPLCC
Top View

LCC
Top View

10

NC

1/0 2
1/0 3
1/0 4

1/0 5
1/°6
1/0 7

--$~§'~§E

NC

1/02

I
I
NC

1/°3
1/0 4
1/0 5

I
I

1/0 6
1/07

t§E9~~
1/°2
1/°3
1/04

I

NC

NC

1/0 5
1/°6
1/07

NC

NC

---$~§'~
20G1D-2

Note:
1. The CG7C323 is the PLDC20GlO packaged in the JEDEC-compat-

ible 28-pin PLCC pinout. Pin function and pin order is identical for

2-39

20G10-4

- - $ §E~ §' g

20G10-3

both PLCC pinouts. The difference is in the location of the "no connect" or NC pins.

I

PLDC20G10B/PLDC20G10

:"'rCYPRESS
Selection Guide
tpD (ns)

Icc (rnA)

Generic
Part Number

Com/Ind

20GlOB-15

70

20GI0B-20

70

Mil

Mil

20

20

100

20GI0B-25

ts (ns)

Com/lnd
15

55
55

Mil

15

12

15

18
20

40

Functional Description (continued)
advantage of being able to program and erase each cell enhances
the reliability and testability of the circuit. This reduces the burden
on the customer to test and to handle rejects.
A preload function allows the registered outputs to be preset to any
pattern during testing. Preload is important for testing the functionality of the Cypress PLD device.

20GIO Functional Description
The PLDC20G 10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to:
20LlO, 20LS, 20R8, 20R6, 20R4, 12LlO, 14LS, 16L6, 18L4, 20L2,
and 20V8. Thus, the PLDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin devices.
It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When
the windowed cerDIP is exposed to UV light, the 20G 10 is erased
and then can be reprogrammed.
The programmable output cell provides the capability of defining
the architecture of each output individually. Each of the 10 output
cells may be configured with registered or combinatorial outputs,
active HIGH or active LOW outputs, and product term or Pin 13
generated output enables. Three architecture bits determine the
configurations as shown in the Configuration Table and in Figures
1 through 8. A total of eight different configurations are possible,

35

25

with the two most common shown in Figure 3 and Figure 5. The default or unprogrammed state is registered/active/LO W /pin 11 0 E.
The entire programmable output cell is shown in the next section.
The architecture bit 'Cl' controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is
fed back to the array. This allows the creation of control-state machines by providing the next state. The registeris clocked by the signal from Pin 1. The register is initialized on power up to Q output
LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit 'C2'. The OE signal may be generated within the
array, or from the external OE (Pin 13). The Pin 13 allows direct
control of the outputs, hence having faster enable/disable times.
Each output cell can be configured for output polarity. The output
can be either active HIGH or active LOW. This option is controlled
by architecture bit 'CO'.
Along with this increase in functional density, the Cypress
PLDC20GlO provides lower-power operation through the use of
CMOS technology and increased testability with a register preload
feature.

Programmable Output Cell
r-------------------~
OE PRODUCT TERM

OUTPUT
ENABLE
MUX

C2

I
I
I
I
I

C2 ------+---~------------------~--r__+--~
Cl

Co

20
25

30

80

15
15

30
35

20GI0-40

Com/Ind
10

15

80

20GI0-35

12

25
25

20GI0-30

tco (ns)

Mil

12

100

20GlO-25

Com/Ind

------+-------------------------~
PIN 13

2-40

20G10-5

-.;~

PLDC20G10B/PLDC20G10

'CYPRESS
Configuration Table
Figure

C2

Cl

Co

1

0

0

0

Product Term OE/Registered/Active LOW

Configuration

2

0

0

1

Product Term OE/Registered/Active HIGH

5

0

1

0

Product Term OE/Combinatorial/Active LOW

6

0

1

1

Product Term OE/Combinatorial/Active HIGH

3

1

0

0

Pin 13 OE/Registered/Active LOW

4

1

0

1

Pin 13 OE/Registered/Active HIGH

7

1

1

0

Pin 13 OE/Combinatorial/Active LOW

8

1

1

1

Pin 13 OE/Combinatorial/Active HIGH

Registered Output Configurations

D

D

Q

Q

20G10-6

20G10-7

Figure 1. Product Term OE/Active LOW

Figure 2. Product Term OE/Active HIGH

Q

20G10-9

Figure 3. Pin 13 OE/Active LOW

Figure 4. Pin 13 OE/Active HIGH

Combinatorial Output Configurations[2]
C2 = 0
Cl = 1
Co = 1

C2 = 0
Cl = 1
Co = 0

20G10-10

20G10-11

Figure 6. Product Term OE/Active HIGH

Figure 5. Product Term OE/Active LOW

$

PIN 13

$

"G""

PIN 13

~"-,

Figure 8. Pin 13 OE/Active HIGH

Figure 7. Pin 13 OE/Active LOW
Note:
2. Bidirectional 110 configurations are possible only when the combinatorial output option is selected

2-41

C2 = 1
Cl = 1
Co = 1

~

==:r- _ -..,.,..

PLDC20G1OB/PLDC20G10

i&7CYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage
PLDC20GlOB and CG7C323B-A ................ 13.0V
PLDC20GlO and CG7C323-A ................... 14.0V

Latch-Up Current ........................... >200 rnA
Static Discharge Voltage ......................... > 500V
(per MIL-STD-BB3, Method B015)

Operating Range
Ambient
Temperature
O°C to +75°C

Range
Commercial

Vee
5V ±10%

Militaryl3J

-55°C to + 125°C

5V ±10%

Industrial

-40°C to +B5°C

5V ±10%

Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[4]
Parameter
VOH
VOL

Description
Output HIGH Voltage
Output LOW Voltage

Test Conditions

Min.

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l/Ind

IOH= -2 rnA

Military

Vee = Min.,
VIN = VIH or VIL

IOL = 24 rnA

Com'l/Ind

IOL = 12 rnA

Military

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputsl:lJ

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputsl:lJ

IIX

Input Leakage Current

Ise
lee

Power Supply Current

Output Leakage Current

loz

Unit
V

0.5

VIH

Vss ~ VIN ~ Vee
Output Short Circuit Current Vee = Max., VOUT = 0.5Vl6,7J

Max.

2.4

V

2.0
-10

V

O.B

V

+10

/-lA

- 90

rnA

O~ VIN~ Vee

Com'l/lnd-15, -20

70

rnA

Vee = Max.,
lOUT = ornA
Unprogrammed Device

Com'l/Ind-25, -35

55

rnA

Military-20, -25

100

rnA

Military-30, -40

BO

rnA

100

/-lA

Vee = Max., Vss~ VOUT~ Vee

-100

Capacitance[7]
Parameter
CIN

Description
Input Capacitance

COUT

Output Capacitance

Test Conditions

Notes:
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

TA = 25°C, f = 1 MHz

Max.
10

Unit
pF

VIN = 2.0V, Vee = 5.0V

10

pF

6.
7.

2-42

Not more than one output should be tested at a time. Duration ofthe short
circuit should not be more than one second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

PLDC20G 10B/PLDC20G10
AC Test Loads and Waveforms (Commercial)
R12380

R12380

5V:F1(3190MIL)

5V : F 1 ( 3 1MIL)
90
OUTPUT

OUTPUT

INCLUDING
JIG AND
SCOPE

1-=

R21700
(2360 MIL)

50 pF

INCLUDING
JIG AND
SCOPE

-=
(a)

Equivalent to: THEVENIN EQUIVALENT (Commercial)
990
OUTPUT
2.08V = Vthc

1-=

R21700
(2360 MIL)

5 pF

-=

20G10-14

(b)

Equivalent to: THEVENIN EQUIVALENT (Military/Industrial)
1360
OUTPUT
2.13V = Vthm

o-------vw---o

o----vvv------o

20G10-15

20G10-16

Switching Characteristics Over Operating Rangel 3, 8, 9)
Commercial

B-15
Parameter

Description

-25

B-20

-35

Min. Max. Min. Max. Min. Max. Min. Max.

Unit

tpD

Input or Feedback to Non-Registered Output

15

20

25

35

tEA

Input to Output Enable

15

20

25

35

ns

tER

Input to Output Disable

15

20

25

35

ns

tpzx

Pin 11 to Output Enable

12

15

20

25

ns

tpxz

Pin 11 to Output Disable

12

15

20

25

ns

teo

Clock to Output

10

12

15

25

ns

ns

ts

Input or Feedback Set-Up Time

12

12

15

30

ns

tH
tp[lO)

Hold Time

0

0

0

0

ns

Clock Period

22

24

30

55

ns

tWH

Clock High Time

8

10

12

17

ns

tWL

Clock Low Time

fMAX[ll)

Maximum Frequency

Notes:
8. Part (a) of AC Test Loads and Waveforms used for all parameters except tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms
used for tER, tpzx, and tpxz.
9. The parameters tER and tpxz are measured as the delay from the input
disable logic threshold transition to VOH - 0.5V for an enabled HIGH
output or VOL + O.5V for an enabled LOW input.
10. tB minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tp = ts + teo. The minimum

8

10

12

17

ns

45.4

41.6

33.3

18.1

MHz

guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (tWH + twL) or (ts + tH).
11. fMAX, minimum guaranteed operating frequency, is that guaranteed
for state machine operation and is calculated from fMAX = 1/(ts +
teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of l/(tWH + twL) or
1/(ts + tH).

2-43

PLDC20G10B/PLDC20G10
Switching Characteristics Over Operating Rangel 3, 8, 9] (continued)
Military/lndustrial

B-20
Parameter

Description

tpD

Input or Feedback to Non-Registered Output

B-25

-40

-30

Min. Max. Min. Max. Min. Max. Min. Max.
20

25

30

tEA

Input to Output Enable

20

25

tER

Input to Output Disable

20

25

tpzx

Pin 11 to Output Enable

17

tpxz

Pin 11 to Output
Disable

17

teo

Clock to Output

ts

Input or Feedback
Set-UpTime

15

Hold Time

15

ns

30

40

ns

30

40

ns

20

25

25

ns

20

25

25

ns

15
18

Unit

40

20
20

25

ns

35

ns

tH
tp(10]

0

0

0

0

ns

Clock Period

30

33

40

60

ns

tWH

Clock High Time

12

14

16

22

ns

tWL

Clock Low Time

12

14

16

22

ns

fMAX[ll]

Maximum Frequency

33.3

30.3

25.0

16.6

MHz

Switching Waveform
INPUTS I/O, 7r'"7'r""K''7\"'"7\.
REGISTERED
FEEDBACK _ .........w...N

CP

tpzx

REGISTERED
OUTPUTS _ _ _ _ _ _~~~

tEA
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _""'"-II~.JI..¥
20G10·17

2-44

~-....",..

PLDC20G 10B/PLDC20G10

JeYPRESS
Functional Logic Diagram

1-ri>

0

4

8

12

16

20

24

28

32

36

40

.---

OE
0

·

"

......,

~7

OUTPU
CELL

~

OE
0

2

·
~7

·

~7

·
----D:

~

""

J-(

./

OUTPU

~ CELL

~

7

~

~

OUTPU
CELL

:tf3"

--t<= 7

~

~

21

20

19

OgJr~l

~

---D7

1><1-- ~,

OE
0

·

8

OUTPU

I> CELL

7 -D7

7

-v

OE
0

OUTPU
~ CELL

~,

OUTPU

~,

"""'\

·

~

~7

~

~

OE
0

··

IP~

-b>7

~

OE
0

·

~~~

10 ~7

11

22

B=\

··

9

23

1P<1-- ~,

OE
0

8

OUTPUl

I> CELL

~

·

6

""
~

OE
0

5

c1----......

t:Ff

OE
0

4

OUTPU
~ CELL

.....

OE
0

3

""

......,

~
~
~
~
~

~

~

I> CELL

5

~'4
if
UTPUT
CELL

13

20G10-18

2-45

6

E

PLDC20G10B/PLDC20G10

irCYPRESS
Ordering Information
tpD
(ns)

ts
(ns)

tco
(ns)

(rnA)

Ordering Code

Package
Name

Package 1Ype

15

12

10

70

20

12

12

70

20

15

15

100

25

15

15

55

25

18

15

100

30

20

20

80

35

30

25

55

40

35

25

80

PLDC20G lOB -15JC/JI
PLDC20G lOB -15PC/PI
PLDC20G lOB-15WC
CG7C323B-A15JC/JIlILj
PLDC20G lOB - 20JC/JI
PLDC20G 10B- 20PC/PI
PLDC20G lOB- 20WC
CG7C323B- A20JC/JIllLj
PLDC20G 10B-20DMB
PLDC20G lOB - 20LMB
PLDC20G lOB- 20WMB
PLDC20G 10-25JC/JI
PLDC20G 10 - 25PC/PI
PLDC20G10-25WC
CG7C323 - A25JC/JIllLJ
PLDC20G lOB- 25DMB
PLDC20G 10B- 25LMB
PLDC20G lOB- 25WMB
PLDC20GI0-30DMB
PLDC20G10-30LMB
PLDC20G 10-30WMB
PLDC20G 10-35JC/JI
PLDC20G 10-35PC/pI
PLDC20G 10-35WC
CG7C323- A35JC/JI[1Lj
PLDC20G 10-40DMB
PLDC20G 10-40LMB
PLDC20G 1O-40WMB

J64
P13
W14
J64
J64
P13
W14
J64
D14
L64
W14
J64
P13
W14
J64
D14
L64
W14
D14
L64
W14
J64
P13
W14
J64
D14
L64
W14

28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP

Icc

Note:
12. The CG7C323 is the PLD20G10 packaged in the JEDEC-compatible
28·pin PLCC pinout. Pin function and pin order is identical for both
PLCC pinouts. The principle difference is in the location of the "no
connect" (NC) pins.

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Switching Characteristics

Parameter

Subgroups

Parameter

Subgroups

VOH

1,2,3

tpD

9,10,11

VOL
VIR

1,2,3

tpzx

9,10,11

VIL

1,2,3
1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

9,10,11
teo
9,10,11
ts
9,10,11
tH
Document #: 38-00019-G

2-46

Operating
Range
Commercial!
Industrial

Commercial!
Industrial

Military

Commercial!
Industrial

Military

Military

Commercial!
Industrial

Military

PLD20GIOC

Generic 24-Pin PAL® Device
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD

= 7.5 ns

-tsu = 3 ns
-

fMAX

= 105 MHz

• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Generic architecture to replace standard logic functions including: 20L10,
20L8, 20R8, 20R6, 20R4, 12L10, 14L8,
16L6, 18L4, 20L2, and 20V8
• Up to 22 inputs and 10 outputs for
more logic power

• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- Pin or product term output enable
control
• Preload capability for flexible design
and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse

Functional Description
The PLD20G 10C is a generic 24-pin device
that can be used in place of 24 PAL devices.
Thus, the PLD20G10C provides significant
design, inventory, and programming flexibility over dedicated 24-pin devices.

Using BiCMOS process and Ti-W fuses,
the PLD20G10C implements the familiar
sum-of-products (AND-OR) logic structure. It provides 12 dedicated input pins
and 10 I/O pins (see Logic Block Diagram). By selecting each I/O pin as permanent or temporary input, up to 22 inputs
can be achieved. Applications requiring up
to 21 inputs and a single output, down to 12
inputs and 10 outputs can be realized. The
output enable product term available on
each I/O or a common pin controlled OE
function allows this selection.
The PLD20G lOC automatically resets on
power-up. The Q output of all internal registers is set to a logic LOW and the Q output to a logic HIGH. In addition, the PRELOAD capability allows the registers to be
set to any desired state during testing.
A security fuse is provided to prevent copying of the device fuse pattern.

Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration

Gl0C-l

Pin Configurations

LCC(L)
Top View

PLCC (J)
Top View
a:; °°86
__ 0S)S);;;,;;;,

I

Vss
I

I

vss
I

I

Gl0C-3

PAL is a registered trademark of Advanced Micro Devices

2-47

LJd

.

-:::z

PLD20GIOC

z1rcYPRESS
Selection Guide
Icc (rnA)

Commercial
Military

tpD (ns)

Commercial

20GIOC-7
190

20GIOC-IO
190
190
10
10
3.6
3.6
7.5
7.5
90
90

7.5

Military
ts (ns)

Commercial

teo (ns)

Commercial
Military
Commercial

3.0

Military

fMAX (MHz)

6.5
105

Military

20GIOC-12
190
190
12
12
4.5
4.5
9.5
9.5
71

20GIOC-15

71

57

190
15
7.5
10

Programmable Macrocell

Programming

The PLD20GlOC has 10 programmable I/O macrocells (see MacroceU). Two fuses (C 1 and Co) can be programmed to configure
output in one of four ways. Accordingly, each output can be registered or combinatorial with an active HIGH or active LOW polarity. The feedback to the array is also from this output. An additional fuse (C2) determines the source of the output enable signal. The
signal can be generated either from the individual OE product
term or from a common external OE pin.

The PLD20G 10C can be programmed using the Impulse3 '" programmer available from Cypress Semiconductor. See third party
information is Cypress's Third Party Tools datasheet for further information.

Macrocell

,---------------------1
I

I

OE PRODUCTTERM

10

OUTPUT I-t---t--T"i

1-_ _°...;.°.... S~~~T
01
CP

C,

Co

C,

I
I
I
_ _ _ oJ
OJ: PIN

Impulse3 is a trademark of Cypress Semiconductor Corporation.

2-48

G10C-4

PLD20GIOC
Configuration Table
Figure

C2

Cl

1

0

0

2
5

0
0

6

Configuration

C;o

O·

Product Term OE/Registered/Active LOW

0

1

Product Term OE/Registered/Active HIGH

1

0

Product Term OE/Combinatorial/Active LOW

0

1

1

Product Term OE/Combinatorial/Active HIGH

3

1

0

0

Pin OE/Registered/Active LOW

4

1

0

1

Pin OE/Registered/Active HIGH

7

1

1

0

Pin OE/Combinatorial/Active LOW

8

1

1

1

Pin OE/Combinatorial/Active HIGH

Registered Output Configurations
C2 = 0
Cl = 0
Co = 0

D

C2 = 0
Cl = 0
Co = 1

Q

G10C-6

Figure 1. Product Term OE/Active LOW

Figure 2. Product Term OE/Active HIGH
C2 = 1
Cl = 0
Co = 0

D

C2 = 1
Cl = 0
Co = 1

Q

G10C-8

Figure 3. Pin OE/Active LOW

Figure 4. Pin OE/Active HIGH

Combinatorial Output Configurations[1]
C2
Cl
Co

=0
=1
=0

G10C-9

G10C-10

Figure 5. Product Term OE/Active LOW

Figure 6. Product Term OE/Active HIGH

Figure 7. Pin OE/Active LOW

Figure 8. Pin OE/Active HIGH

Note:
1. BidirectionalI/O configurations are possible only when the combinatorial output option is selected.

2-49

E

::sF

-'f~

PLD20GIOC

=-,CYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
,
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55 ° C to + 125 ° C
Supply Voltage to Ground Potential ........ -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................... -O.5V to Vee
DC Input Voltage .... ; .................... -O.5V to Vee

DC Input Current .................... - 30 rnA to +5 rnA
(except during programming)
DC Program Voltage .............................. 10V

Operating Range
Range
Commercial
Military[2]

Ambient
Temperature
O°C to +70°C

Vee
5V±5%

-55°C to + 125°C

4.75V to 5.5V

DC Electrical Characteristics Over the Operating Range
Description

Parameter
VOH

Min.

Test Conditions

Output HIGH Voltage

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com'l

IOH= -2mA

Mil

IOL = 16 rnA

Com'l

IOL = 12 rnA

Mil

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for All Inputs[3]

IIX

Input Leakage Current

Vss~ VIN ~2.7V,

II

Maximum Input Current

VIN = Vee, Vee = Max.

Max.

Unit
V

2.4

0.5

V

V

2.0
0.8

V

50

[lA

Com'l

100

f,lA

Mil

250

-250

Vee = Max.

Ioz

Output Leakage Current

Vee = Max., Vss~ VOUT~ Vee

-100

100

f,lA

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.5V[4]

-30

-120

rnA

lee

Power Supply Current

Vee = Max., VIN = GND, Outputs Open

Com'l

190

rnA

Mil

190

Capacitance[5]
Parameter

Description

CIN

Input Capacitance

COUT

Output Capacitance

Notes:
2. TA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration ofthe short
circuit should not be more than one second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.

5.

2-50

Max.

Unit

8
10

pF
pF

Tested initially and after any design or process changes that may affect
these parameters.

PLD20GIOC
AC Test Loads and Waveforms
R12380

OUTP~~ ~(3190
MIL)

I

R21700
(2360 MIL)

CL

INCLUDING
':'
JIG AND
SCOPE

PID
J/K/L

G10C-13

o--------vw----

Parameter

tER (+), tpLZ 2.6V

Equivalent to: THEVENIN EQUIVALENT

tEA (+), tPZH 1.5V

1360

o--------vw---Military

2.13V = Vthm

tEA ( -), tpZL 1.5V

Note:
6. CL = 5 pF for tER and tpxz measurements for all packages.

2-51

Output Waveform-Measurement Level

Vth

tER (-), tpHz 1.5V

2.08V = Vthc

Commercial

OUTPUT

15 pF
50pF

':'

Equivalent to: THEVENIN EQUIVALENT
990
OUTPUT

Package

CL[6)

VOH O.5V

t

VOL

O.5V

1.5V

O.5V

1.5V

O.5V

~
~

t

~
~
~
~

1.5V

G10C-14

2.6V
G10C 15

VOH
G10C-16

VOL

G10C-17

I

PLD20GIOC
Switching Characteristics PLD20GIOC[7]
20GIOC-7
Description

Min.

Max.

20GIOC-IO 20GIOC-12 20GIOC-15
Min.

Max.

Min.

Max.

Min.

Max.

Unit

tpD

Input to Output Propagation Delay[8]

2

7.5

2

10

2

12

2

15

ns

tEA

Input to Output Enable Delay

2

7.5

2

10

2

12

2

15

ns

tER

Input to Output Disable Delay[9]

2

7.5

2

10

2

12

2

15

ns

tpzx

OE Input to Output Enable Delay

2

7.5

2

10

2

12

2

15

ns

tpxz

OE Input to Output Disable Delay

2

7.5

2

10

2

12

2

15

ns

tco

Clock to Output Delay[8]

1

6.5

1

7.5

1

9.5

1

10

ns

ts

Input or Feedback Set-Up Time

3

tH

Input Hold Time

0

0

0

0

ns

tp

External Clock Period (tco + ts)

9

11.1

14

17.5

ns

tWH

Clock Width HIGH[5]

3

3

3

6

ns

tWL

Clock Width LOW[5]

3

3

3

6

ns

fMAX1

External Maximum Frequency (lI(tco + tS))[10]

105

90

71

57

MHz

fMAX2

Data Path Maximum Frequency
(lI(tWH + twL))[5, 11]

166

166

166

83

MHz

fMAX3

Internal Feedback Maximum Frequency
(lI(tcF + tS))[12]

133

100

83

66

MHz

tCF

Register Clock to Feedback Inputl13]
Power-Up Reset Timd 14]

Parameter

tPR

4.5
1

Notes:
7. AC test load used for all parameters except where noted.
8. This specification is guaranteed for all device outputs changing state in
a given access cycle.
9. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
10. This specification indicates the guaranteed maximum frequency at which
a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.

4.5

3.6

6.4
1

7.5

7.5
1

ns

7.5
1

ns
I-ts

12. This specification indicates the guaranteed maximum frequency at which
astatemachineconfigurationwithinternaloniyfeedbackcanoperate. This
parameter is tested periodically by sampling production product.
13. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see Note 12) minus ts.
14. The registers in the PLD20G lOC have been designed with the capability to reset during system power-up. Following power-up, all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. This feature is useful in establishing state
machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in power-up reset waveforms must be satisfied.

2-52

---~

PLD20GIOC

JCYPRESS
Switching Waveform
INPUTS I/O, ......- REGISTERED
FEEDBACK ~'-¥.~.,...

CP

II

tpzx
REGISTERED ------...,...;;;...
OUTPUTS: _ _ _ _ _

LlI..~

COMBINATORIAL
OUTPUTS:

tEA

---------~~~,..,.:
--------------~~~

G10C-18

Power-Up Reset Waveform[14]

4V~~~~~~~~~~~~~~~-------------------VCC

POWER _ _ _ _ _ _ _ _ _

~ ~

REGISTERED
ACTIVE LOW

tpR------.......I.'

----------.:..-------~~---==:;;:Jr_--------­

OUTPUT---------------------------------------------~

G10C-19

2-53

~CYPRESS

PLD20GIOC

Preload Waveform[15)
PIN 13 (1S)

-k

t OPR1

.......\

PIN 2(3)
PIN3 (4)

I

PINS (7)

~

I(

PIN 8 (10)

~

\
I(

PINS (11)

PRELOAD DATA
PINS 14-23
(17-21,23-27)

"-

t OPR2

CLOCK PIN 1 (2)

J

t OPR1

~.

t OPR1

\

1

I

t OPR1

~

\

t OPR1

) -r
'-

/

"-

/
t OPR2 t OPR2

t OPR2

\..

t OPR2 t OPR2

t OPR1

L

t OPR1

\

OUTPUTS
DISABLED

-,
I

~ t OPR1
t OPR1 1\-

PRELOAD
DATA
CLOCKED
IN
PRELOAD DATA
VILP or VIHP[16]

REGISTE RS
PRELOAD ED,
OUTPUT
ENABLED
PRELOAD
DATA
REMOVED
G10C-20

Notes:
15. Pins 4 (5),5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; Vee
(Pin 24 (1 and 28» at VeeI'

16. Pins 2-8 (3-7, 9,10),10 (12),11 (13) can be set at VIHP or VILP to
insure asynchronous reset is not active.

D/K/P (J/L) Pinouts
Forced level on register pin
during preload

Register Q output state
after preload

VIHP

HIGH

VILP

LOW

Name

Description

Min.

Max.

Unit

Vpp

Programming Voltage

9.25

9.75

V

tDPRl

Delay for Preload

1

its

tDPR2

Delay for Preload

0.5

Its

VILP

Input LOW Voltage

0

0.4

V

VIHP

Input HIGH Voltage

3

4.75

V

Vecp

V cc for Preload

4.75

5.25

V

2-54

.

-.,~

PLD20GIOC

'CYPRESS
Functional Logic Diagram for PLD20GIOC
1-ri>

0

(2)

4

8

12

16

20

24

28

32

36

40

W ::1-- =~

OE

0

·

> cell

--f::>7

,

OE

0

2

·
-D7

W ::1--

Macro·

~ cell

(3)
OE

t:S--\

0

1P(1.-

·

3

-r::;:/

Macro·
~ cell

(4)
OE

0

I§"")

·

(5)

4

Macro·

> cell

CI-----

@

-D7
0

·

5

.....,.

'"

Macro·
~ cell

CI-----

OE

0

6
(7)

""-

....,.

-f:::/

Macro·
~ cell

~

OE

0

7
(9)

-b

·7

Macro·
~ cell

....,.

~

OE

0

·

8

'"

Macro·
~ cell

./

..jj:

---{27

~

(10)

....

OE

·

9

'"

./
"1,J-

21
(25)

20

19

8
21)

7
20)

~(;

Macro·
cell

~'4

I>

CI-----~

(11 )

.....

OE

0

·

10

'"

-D7

CI-----"-

(12)

11
(13)

--f2
DIK/P (J/L) Pinouts

2-55

6
9)

Macro·
cell

0

---f2 7

22
(26)

23)

(6)

·

~
~
~
~(
~:
~:
~~

(24)

OE

---t2 7

23

(27)

z::

G10C-21

5
8)

(1 7)

13

(16)

I

~ ~.;~

PLD20GIOC

'CYPRESS
Ordering Information
IcC
(rnA)

190

tpD (ns)

fMAX

7.5

(MHz)
105

10

90

12

15

71

57

Ordering Code
PLD20G 10C-7DC
PLD20GlOC-7JC
PLD20G lOC-7PC
PLD20G lOC-lODC
PLD20G lOC -lOJC
PLD20G lOC-lOPC
PLD20GlOC-lODMB
PLD20GlOC-lOKMB
PLD20G lOC-10LMB
PLD20G 10C-12DC
PLD20GlOC-12JC
PLD20G lOC -12PC
PLD20GlOC-12DMB
PLD20GlOC-12KMB
PLD20G lOC-12LMB
PLD20GlOC-15DMB
PLD20GlOC-15KMB
PLD20GlOC-15LMB

Package
Name
D14
J64
P13
D14
J64
P13
D14
K73
L64
D14
J64
p13
D14
K73
L64
D14
K73
L64

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

VOL
VIH
VrL
Irx
Ioz

Icc

Switching Characteristics
Parameter

Subgroups

tpD

7, 8, 9,
7,8,9,
7, 8, 9,
7, 8, 9,

teo
ts
tH

10, 11
10, 11
10, 11
10, 11

Document #: 38-A-00027-A

2-56

Package 1Ype
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier

Operating
Range
Commercial

Commercial

Military

Commercial

Military

Military

PLDC20RAIO

Reprogrammable
Asynchronous CMOS
Logic Device
Features
• Advanced-user programmable macrocell
• CMOS EPROM technology for reprogrammability
• Up to 20 input terms
• 10 programmable I/O macrocells
• Output macrocell programmable as
combinatorial or asynchronous Dtype registered output
• Product-term control of register
clock, reset and set and output enable
• Register preload and power-up reset
• Four data product terms per output
macrocell

- Military/Industrial
tpD = 20 ns
teo 20 ns
tsu = 10 ns

mabie logic device employing a flexible macrocell structure that allows any individual
output to be configured independently as a
combinatorial output or as a fully asynchronous D-type registered output.

=

• Low power
- Icc max - 80 rnA (Commercial)
-Icc max = 85 rnA (Military)

The Cypress PLDC20RAlO provides lower-power operation with superior speed
performance than functionally equivalent
bipolar devices through the use of high -performance 0.8-micron CMOS manufacturing technology.

• High reliability
- Proven EPROM technology
- >2001V input protection
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, PLCC available

Functional Description
The Cypress PLDC20RAlO is a high-performance, second-generation program-

• Fast
- Commercial
tpD 15 ns
teo 15 ns
tsu 7 ns

=
=
=

The PLDC20RAlO is packaged in a 24 pin
300-mil molded DIP, a 300-mil windowed
cerDIP, and a 28-lead square leadless chip
carrier, providing up to 20 inputs and 10
outputs. When the windowed device is exposed to UV light, the 20RAlO is erased
and can then be reprogrammed.

Logic Block Diagram

I/Og

1/06

I/Os

1/00

Vee
RA10-1

Selection Guide
Generic Part
Number

tpD ns
Com'l

20RAI0-15

15

20RAlO-20

20

tsu ns

Mil/Ind

Com'l

teo ns

Mil/Ind

7
20

10

Com'l

Icc ns

Mil/Ind

15

10

20

Com'l

MiI/lnd

80
20

80

85

20RAI0-25

25

15

25

85

20RAI0-35

35

20

35

85

2-57

II

=r

~'i~

PLDC20RAIO

'CYPRESS
Pin Configurations
STD PLCC/HLCC
Top View

LCC
Top View

~-=31~
12

5

13
14
15
16
17
NC

6

4 3 2'1; 282726
• •
25

9 g'~

.:- 31~ ~

9 g'~

NC
1/02
1/03
1/04
1/05
1/06
1/07

10
11

JEDEC PLCC/HLCC [1]
Top View

12131415161718

NC
13
14
NC
15
16

5

1/°2
1/°3
1/°4
1/05
1/°6
1/07
NC

NC

.!'
RA10-2

_00_'" $I~ ~ ~
RA10-3

Macrocell Architecture
Figure 1 illustrates the architecture of the 20RAlO macrocell. The
cell dedicates three product terms for fully asynchronous control of
the register set, reset, and clock functions, as well as, one term for
control of the output enable function.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automatically chosen for all outputs since, for this case, the external output enable pin must be tied LOW The active polarity of each
output may be programmed independently for each output cell
and is subsequently fixed. Figure 2 illustrates the output enable
options available.
When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term
outputs to be HIGH under all input conditions. This is achieved by
programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration
options.

An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-defined
logic functions.

Programmable I/O
Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a
total of nine programmable plus ten dedicated inputs (a total of
nineteen inputs) and one output down to a ten-input, ten-output
configuration with all ten programmable I/O cells configured as
outputs. Each input pin available in a given configuration is avail-

1/°2
1/°3
1/°4
NC
1/0 5
1/°6
1/07

12
13
14
NC
15
16
17

_00_'" $

~I~~ ~

RA10-4

able as an input to the four control product terms and four uncommitted product terms of each programmable I/O macrocell that has
been configured as an output.
An I/O cell is programmed as an input by tying the output enable
pin (pin 13) HIGH or by programming the output enable product
term to provide a Law, thereby disabling the output buffer, for all
possible input combinations.
When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as
an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed
back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation.

Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each
register to be set by loading each register from an external source
prior to exercising the device. Testing of complex state machine designs is simplified by the ability to load an arbitrary state without
cycling through long test vector sequences to reach the desired
state. Recovery from illegal states can be verified by loading illegal
states and observing recovery. Preload of a particularregister is accomplished by impressing the desired state on the register output
pin and lowering the signal level on the preload control pin (pinl)
to a logic LOW level. If the specified preload set-up, hold and
pulse width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initialization,
all registers are preset to a logic LOW state upon power-up, thereby setting the active LOW outputs to a logic HIGH.

Note:
1. The CG7C324 is the PLDC20RAIO packaged in the JEDEC-compatib1e 28-pin PLCC pinout. Pin fuction and pin order is identical for
both PLCC pinouts. The principle differencd is in the location of the
"no connect" (NC) pins.

2-58

PLDC20RAIO

OUTPUT ENABLE
(FROM PIN 13)

PRELOAD
(FROM PIN 1)

TO I/O PIN

I
RA10-5

Figure I. PLDC20RAIO Macrocell

Programmable

Output Always Enabled

~-

-~[)o--

RA10-7

RA10-6

Combination of
Programmable and Hardwired

External Pin

RA10-8

RA10-9

Figure 2. Four Possible Output Enable Alternatives for the PLDC20RAIO

2-59

PLDC20RAIO

Registered/Active LOW

Combinatorial/Active LOW

RA10-10

RA10-11

Combinatorial/Active HIGH

Registered/Active HIGH

RA10-12

Figure 3. Four Possible Macrocell Configurations for the PLDC20RAIO

2-60

RA10-13

.~

PLDC20RAIO

'CYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)

Latch-Up Current ............................ >200 rnA
DC Program Voltage .............................. 13.0V

Storage Temperature ................... -6SoC to +1S0°C
Ambient Temperature with
Power Applied ........................ -SSoC to +12SoC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................ -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.SV to +7.0V
DC Input Voltage ...................... -3.0 V to + 7.0 V
Output Current into Outputs (LOW) ............... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-SS3, Method 301S)

Operating Range
Ambient
Temperature

Range
Commercial

Vee
SV ± 10%

O°C to +7SoC

Industrial

-40°C to +SSoC

SV ± 10%

Military[2]

-SSoC to +12SoC

SV ± 10%

Electrical Characteristics Over the Operating Rangel3]
Parameter
VOR

Description

Test Conditions

Output HIGH Voltage

Vee = Min.,
VIN=VIHorVIL

Min.

lOR = -3.2 rnA

Com'l

= -2 rnA
IOL = SrnA

Mil/Ind

lOR

Max.

2.4

Unit
V

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIHor VIL

VIR

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[4]

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[4]

O.S

V

IIX

Input Leakage Current

Vss ~ VIN ~ Vee, Vee = Max

-10

+10

!lA

loz

Output Leakage Current

Vee = Max., Vss ~ VOUT ~ Vec

-40

+40

I-tA

Isc

Output Short Circuit Currend5]

Vcc = Max., VOUT = 0.SV[6]

-30

-90

rnA

ICCI

Standby Power Supply Current

Vcc= Max., VIN

ICC2

Power SUP~7 Current at
Frequency 5

= GND Outputs Open

V CC = Max., Outputs Disabled (In High Z
State) Device Operating af fMAX

0.5

Com'l

2.0

V
V

7S

rnA

Mil/Ind

SO

rnA

Com'l

SO

rnA

Mil/Ind

SS

rnA

Capacitance[S]
Parameter

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
VIN = 2.0 V @ f = 1 MHz
VOUT = 2.0 V @ f

= 1 MHz

Max.

Unit

10

pF

10

pF

Notes:
2.
3.
4.

TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to devicee ground and all overshoots due to system or tester noise are included.

5.
6.

2-61

Tested initially and after any design or process changes that may affect
these parameters.
Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second. VOUT = 0.5 V has
been chosen to avoid test problems caused by tester ground degradation.

II

PLDC20RAIO
AC Test Loads and Waveforms (Commercial)
R14S7Q
(470Q MIL)

SV~
I

OUTPUT

SO pF

~~8~~~NG

-=

R14S7Q
(470Q MIL)

90%
S V 5 n R2
R2
OUTPUT
GND
270Q
270Q
(319Q Mil)
S pF
(319Q Mil)

-=

SCOPE

I

~~8~~~NG

OUTPUT

Parameter
tpXZ(-)

tpXZ(+)

-=

SCOPE
(a)

Equivalent to:

ALL INPUT PULSES
3.0V----

-=
RAl0-15

RAl0-14

(b)

THEVENIN EQUIVALENT (Commercial)

~

Equivalent to:

1.86V=Vthc

THEVENIN EQUIVALENT (Military/Industrial)
OUTPUT

RAl0-16.

~

2.02V=Vthc

,

Output Waveform-Measurement Level

Vth
l.SV
2_6V

VOH O.5V

O.SV

VOL

O.5V

tpZX(+)

Vthc

Vx

tpZX(-)

Vthc

Vx

tER(-)

l.SV

VOH O.5V

tER(+)

2_6V

O.5V

Vthc

Vx

tEA(-)

Vthc

Vx

,

O.5V

VOL

tEA(+)

t
t
t
t

O.SV

O.5V

(c)

2-62

t
t

,

F;
~
~

F;
~

~
~
~

Vx

RAl0-1B

Vx
RAl0-19

VOH
RAl0-20

VOL

RA10-21

Vx

RAl0-22

Vx
RA10-23

VOH

VOL

..

RAl0-24

RAl0-25

RA10-17

,

-.;~

PLDC20RAI0

'CYPRESS
Switching Characteristics Over the Operating Rangel 3, 7, 8]
Commercial
-15
-20
Parameter

Description

tpD

Input or Feedback to
Non-Registered Output

Min.

Max.

Min.

Military/Industrial
-25

-20

Max.

Min.

Max.

15

20

20

Min.

Max.

-35

Min.

Max.

Unit

25

35

ns

tEA

Input to Output Enable

15

20

20

30

35

ns

tER

Input to Output
Disable

15

20

20

30

35

ns

tpzx

Pin 13 to Output
Enable

12

15

15

20

25

ns

tpxz

Pin 13 to Output
Disable

12

15

15

20

25

ns

tco

Clock to Output

15

20

20

25

35

ns

tsu

Input or Feedback
Set-UpTime

7

15

10

10

20

ns

tH

Hold Time

3

5

3

5

5

ns

tp

Clock Period
(tsu '+ tCO)

22

30

30

40

55

ns

tWH

Clock Width HIGH[5]

10

13

12

18

25

ns

tWL

Clock Width LOW[5]

10

13

12

18

25

ns

fMAX

Maximum Frequency
(l/tp )[5]

45.5

33.3

33.3

25.0

18.1

MHz

ts

Input of Asynchronous
Set to Registered
Output

15

20

20

25

40

ns

tR

Input of Asynchronous
Reset to Registered
Output

15

20

20

25

40

ns

tARW

Asynchronous Reset
Width[5]

15

20

20

25

25

ns

tASW

Asynchronous Set
Width[5]

15

20

20

25

25

ns

tAR

Asynchronous Set/
Reset Recovery Time

10

12

12

15

20

ns

twp

Preload Pulse Width

15

15

15

15

15

ns

tsup

Preload Set-Up Time

15

15

15

15

15

ns

tHP

Preload Hold Time

15

15

15

15

15

ns

Notes:
7. Part (a) of AC Test Loads was used for all parameters except tEA, tER,
tpzx and tpxz, which use part (b).
8. The parameters tER and tpxz are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled

2-63

HIGH output or VOL +O.5V for an enabled LOW output. Please see
part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.

PLDC20RAIO
Switching Waveform
INPUTS, REGISTERED
FEEDBACK

CP
ASYNCHRONOUS
RESET
ASYNCHRONOUS
SET
OUTPUTS
(HIGH ASSERTED)
OUTPUT ENABLE
INPUT PIN

RA10-26

Preload Switching Waveform
PIN 13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN 1
PRELOAD
CLOCK

RA10-27

Asynchronous Reset
ASYNCHRONOUS
RESET
OUTPUT

RA10-28

Asynchronous Set
ASYNCHRONOUS
SET

OUTPUT

RA10-29

2-64

Functional Logic Diagram
1

....
--y

-

[t· ~
~
-

0

7

3""""

~

.

h

D· R

~~

It

22

'

3"

~

II

DR

~~

Z3

" ...

21

~ ~

A
~

......

2'

ttR'

-~~

3,

.....

U

31

• P

L-

-

h

.n

~~~

.7

-

fD ~17

-~

55

8 ....

• P

",

L-

511

......

g.J'o"

:=

........
~

~

L-

...

-v

[j
• P

h

~~

10 .J'-.

L-

PL

• p

L-

72

~ fD ~r

.....,

71

11

R"
DR"

~~

ID

71

8

• P

..

..:=

R'
fDR'

[1

9

R P

6-"
.a

o

PL

- --~~

5'"

7.]'0,

23

....

-

.A

PL

• P

~

13

D 3

•

7

. " 12 15 I i II 20 2l 2' 27 21 31 32 35 31

2-65

I

-

-.,~

PLDC20RAIO

,CYPRESS

Ordering Information
ICC2

tpD
(ns)

tsu
(ns)

tco
(ns)

80

15

7

15

80

85

85

85

20

20

25

35

10

10

15

20

20

20

25

35

Ordering Code

Package
Name

Package 1Ype

Operating
Range
Commercial

PLDC20RAI0-15HC

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RA1O-15JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O-15PC

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAI0-15WC

W14

24-Lead (300-Mil) Windowed CerDIP

CG7C324- A15HC

H64

28-Pin Windowed Leaded Chip Carrier

CG7C324- A15JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O-20HC

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RA1O- 20JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O- 20PC

P13

24-Lead (300-Mil) Molded DIP

PLDC20RA1O- 20WC

W14

24-Lead (300-Mil) Windowed CerDIP

CG7C324- A20HC

H64

28-Pin Windowed Leaded Chip Carrier

CG7C324- A20JC

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O-20DI

D14

24-Lead (300-Mil) CerDIP

PLDC20RA1O-20JI

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O- 20PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RAI0-20WI

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RA1O- 20DMB

D14

24-Lead (300-Mil) CerDIP

PLDC20RAI0- 20HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RA1O-20LMB

L64

28-Square Leadless Chip Carrier

PLDC20RA1O- 200MB

064

28-Pin Windowed Leadless Chip Carrier

PLDC20RAI0-20WMB

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RA1O-25DI

D14

24-Lead (300-Mil) CerDIP

PLDC20RA1O-25JI

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RAI0- 25PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RA1O-25WI

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RA1O- 25DMB

D14

24-Lead (300-Mil) CerDIP

PLDC20RA1O- 25HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RA1O- 25LMB

L64

28-Square Leadless Chip Carrier

PLDC20RA1O- 250MB

064

28-Pin Windowed Leadless Chip Carrier

PLDC20RA1O- 25WMB

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RA1O-35DI

D14

24-Lead (300-Mil) CerDIP

PLDC20RA1O-35JI

J64

28-Lead Plastic Leaded Chip Carrier

PLDC20RA1O-35PI

P13

24-Lead (300-Mil) Molded DIP

PLDC20RA1O-35WI

W14

24-Lead (300-Mil) Windowed CerDIP

PLDC20RA1O-35DMB

D14

24-Lead (300-Mil) CerDIP

PLDC20RAI0-35HMB

H64

28-Pin Windowed Leaded Chip Carrier

PLDC20RA1O-35LMB

L64

28-Square Leadless Chip Carrier

PLDC20RA1O-350MB

064

28-Pin Windowed Leadless Chip Carrier

PLDC20RA1O-35WMB

W14

24-Lead (300-Mil) Windowed CerDIP

2-66

Commercial

Industrial

Military

Industrial

Military

Industrial

Military

~~

PLDC20RAIO

. 'CYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

I

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

tpzx
teo
tsu
tH

Document #: 38-00073-E

2-67

This is an abbreviated datasheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the PALC22VIOD.

PALC22VIO
Reprogrammable CMOS
PAL® Device
• 2S, 30, 40 ns military
• Up to 22 input terms and 10 outputs
• High reUability
- Proven EPROM technology
-100% programming and functional
testing
• Windowed DIP, windowed LeC, DIP,
LCC, and PLCC available

Features
• Advanced second-generation PAL
architecture
• Lowpower
- SS mA max. un'
- 90 mA max. standard
-120 mA max. miUtaay
• CMOS EPROM technology for
reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macroceU
- Output polarity control
- Individually selectable for registered or combinatorial operation
• 20, 2S, 3S ns commercial and
industrial

Functional Description
The Cypress PALC22V10 is a CMOS second-generation programmable logic
array device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and a new concept, the "programmable macrocel1."
The PALC22V10 is available in 24-pin
300-mil molded DIPs, 300-mil windowed
cerDIPs, 28-lead square ceramic leadless

chip carriers, 28-lead square plastic leaded
chip carriers, and provides up to 22 inputs
and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22V10 is
erased and can then be reprogrammed.
The programmable macrocell provides the
capability of defining the architecture of
each output individually. Each of the 10
potential outputs may be specified as registered or combinatorial. Polarity of each
output may also be individually selected,
allowing complete fleXibility of output
configuration. Further configurability is
provided through array-configurable output enable for each potential output. This
feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or
aIternatelyused as a combination I/O CODtrolled by the programmable array.

Logic Block Diagram (pDIP/CDIP) and Pin Configurations
'Iss

CP/I

PLee

Lee

Top View

I >5
I
6
I
NC
I
9
10
11

,

Top View

--~~~gg
'4 '3 '2 ;1' 282726 "
•-

25
24
23
22
21
20
19
12131415161718
-

-

--~~~g'g
1/02

li03
1/0 4
NC
1/0 5
1/0 6
1/0 7

(1)0- '" co

~z

~~

V10-2

PAL is a registered trademark of Advanced Micro Devices.

Document #: 38-00020-H
2-68

I

N/C
I
I

- - $ ~-

~

g

V10-3

This is an abbreviated data sheet. Contact a Cypress
Representative for complete specifications. For new designs,
please refer to the PALC22VIOD.

PALC22VIOB
Reprogrammable CMOS PAL® Device
Features
• Advanced second-generation PAL architecture
• Low power
- 90 rnA max. standard
-100 rnA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
- "IS" commercial and industrial
10 ns tco
10 ns ts

•
•

•

•

15 ns tpD
50 MHz
- "IS" and "20" military
10/15 ns tco
10/17 ns ts
15/20 ns tpD
50/31 MHz
Up to 22 input terms and 10 outputs
Enhanced test features
- Phantom array
-Top test
- Bottom test
-Preload
High reliability
- Proven EPROM technology
-100% programming and functional
testing
Windowed DIP, windowed LCC, DIP,
LCC, PLCC available

Functional Description
The Cypress PALC22VlOB is a CMOS second-generation programmable logic
array device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and a new concept, the "Programmable Macrocell."
The PALC22VIOB is executed in a 24-pin
300-mil molded DIP, a 300-mil windowed
cerDIP, a 28-lead square ceramic leadless
chip carrier, a 28-lead square plastic leaded
chip carrier, and provides up to 22 inputs
and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22VIOB is
erased and can then be reprogrammed.

Logic Block Diagram (PDIP/CDIP) and Pin Configurations
Vss

CP/I

1104

1/01

1/°2

1/°3

1/°0

VCC
V10B·1

LeC

PLCC

Top View

Top View
_ _ 1:i:&?886
OZ:5::::'::::::'

--~~yg'~

1/°2
1/°3

1

1

N/C

--cnO;jlz

moo

QQ

1

1/0 4

N/C

N/C
1/0 5
1/°6
1/°7
-

V10B·2

PAL is a registered trademark of Advanced Micro Devices.

Document #: 38-00195-A

2-69

-

cnQ-

~z

(J)

co

~ ~

V10B·3

PAL22VIOC
PAL22VPIOC
Universal PAL® Device
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tPD

= 6 ns

-ts = 3 ns
-fMAX

= 117 MHz

BiCMOS process and Ti-W fuses, the
PAL22VlOC and PAL22VPlOC use the
familiarsum-of-products(AND-OR)logic
structure and a new concept, the programmable macrocell.

• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VPI0C)
• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory

• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vcc and Vss pins for lowest
ground bounce
.
• Up to 22 inputs and 10 outputs for
more logic power

• Security Fuse

Functional Description

• Variable product terms
- 8 to 16 per output

The
Cypress
PAL22VlOC
and
PAL22VPIOC are second-generation programmable array logic devices. Using

Both the PAL22VlOC and PAL22VPI0C
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22VIOC and PAL22VPlOC
feature variable product term architecture,
where 8 to 16 product terms are allocated
to each output. This structure permits
more applications to be implemented with

Logic Block Diagram and PDIP (P)/CDIP (D) and Pin Configurations
Vss

CP/I

1105

I

4 3 2:1: 282726
25
24
23
PAL22V1DC 22
9 PAL22VP1 DC 21
10
20
11
19
12131415161718
-

-

C/)

00-

:!fl:!fl

1/°1
v10c·1

a: () () 85

--~~~g'g

Vss

1/°2

PLCC (J)/CLCC (y)
Top View

LCC{L)
Top View

I
I

11°3

11°4

--()~~:;":;,,

110 2
I

1/°2
1/°3
1/°4

Vss

Vss

I

1/05
1/°6
1/07

1/°3

11°4

Vss

1/05

11°6
11°7

m co

gg

-

v10c·2

PAL is a registered trademark of Advanced Micro Devices.

2-70

-

Cf) Cf)-

:!fl:!fl

m co

gg

v10c·3

•

PAL22VIOC
PAL22VPIOC

-'f~

'CYPRESS
Functional Description (continued)

Programmable Macrocell

these devices than with other PAL devices that have fixed number
of product terms for each output.

The PAL22VlOC and PAL22VPIOC each has 10 programmable
output macrocells (see Macrocell figure). On the PAL22VlOC two
fuses (CI and Co) can be programmed to configure output in one of
four ways. Accordingly, each output can be registered or combinatorial with an active HIGH or active LOW polarity. The feedback to the array is also from this output (see Figure 1). An additional fuse (C2) in the PAL22VPIOC provides for two feedback
paths (see Figure 2).

Additional features include common synchronous preset and
asynchronous reset product terms. They eliminate the need to use
standard product terms for initialization functions
Both the PAL22VlOC and PAL22VPlOC automatically reset on
power-up. In addition, the preload capability allows the output regIsters to be set to any desIred state during testing.

Programming

A security fuse is provided on each of these two devices to prevent
copying of the device fuse pattern.

The PAL22VIOC and PAL22VPlOC can be programmed using the
QuickPro II programmer available from Cypress Semiconductor
and also with Data I/O, Logical Devices, STAG and other programmers. Please contact your local Cypress representative for
further information.

W~th the programmable macrocells and variable product term archItecture, the PAL22VlOC and PAL22VPIOC can implement
logic functions in the 700 to 800 gate array complexity, with the inherent advantages of programmable logic.

Macrocell
OE

r----------------------.I
I
I
I

AR

~-+----------~~

D

QI--------~

OUTPUT
SELECT
MUX

Qt-....- - - I

CP

Key:
AR
SP
OE
CP

SP

INPUT/
FEEDBACK
MUX

S1

~

C1

Co
C2 [1]

--------~------~----------------------------~
MACROCELL

I
I
I
I

~----------------------~

v10c·4

Output Macrocell Configuration
CP]

Cl

Co

Output'IYPe

0

0

0

Registered

Active LOW

Polarity

Feedback
Registered

0

0

1

Registered

Active HIGH

Registered

X

1

0

Combinatorial

Active LOW

lIO

X

1

1

Combinatorial

Active HIGH

I/O

1

0

0

Registered

Active LOW

lIO[I]

1

0

1

Registered

Active HIGH

lIO[I]

Note:
1. PAL22VPlOC only.

2-71

=
=
=
=

Asynchronous RESET
Synchronous PRESET
Output Enable
Clock Pulse

•

PAL22VIOC
PAL22VPIOC

AR

AR

C2 [1] = 0
C1 = 0
Co = 1

C2[1] = 0
C1 = 0

Co = 0

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

C2 [1] = x
C1 = 1
Co = 1

C2[1] = X
C1 = 1

Co = 0
v10c-7

v10c-8

110 FEEDBACK, COMBINATORIAL, ACTIVE-LOW OUTPUT

I/O FEEDBACK, COMBINATORIAL, ACTIVE-HIGH OUTPUT

Figure 1. PAL22VIOC and PAL22VPIOC Macrocell Configurations

AR

SP

SP
v10c-9

v10c-10

I/O FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

110 FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

Figure 2. Additional Macrocell Configurations for the PAL22VPIOC

2-72

PAL22VIOC
PAL22VPIOC

-.;~

'CYPRESS
Selection Guide
22VIOC-6
22VPI0C-6
190

Commercial

lee (rnA)

22VIOC-7
22VPIOC-7
190

22VIOC-IO
22VPI0C-IO
190

22VIOC-12
22VPIOC-12

190

190
12

Military
tpD (ns)

Commercial

ts (ns)

Commercial

teo (ns)

Commercial

fMAX (MHz)

Commercial

190

6.0

7.5

10
10

12

3.0

3.0

3.6

4.5

3.6

4.5

5.5

6.0

7.5

9.5

7.5

9.5

117

111

90

71

90

71

Military
Military
Military
Military

22VI0C-15
22VPIOC-15
190
15
7.5
10
57

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential ........ -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................... -0.5V to Vee
DC Input Voltage ......................... -0.5V to Vee

DC Input Current. . . . . . . . . . . . . . . . . . .. -30 rnA to + 5 rnA
(except during programming)
DC Program Voltage ............................ 10.0 V

Operating Range
Range
Commercial
Military[2]

Ambient
Temperature
O°C to +70°C

Vee
5V±5%

-55°C to +125°C

5V±5%

DC Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL

Description

Test Conditions

Output HIGH Voltage

= -3.2 rnA
IOH = -2 rnA
IOL = 16 rnA
IOL = 12 rnA
IOH

Vee = Min.,
VIN = VIH or VIL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

Min.
Com'l
Com'l

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for All Inputs[3]

IIX

Input Leakage Current

Vss~ VIN~2.7V,

II

Maximum Input Current

VIN

Ioz

Output Leakage Current

Ise

Output Short Circuit Current

lee

Power Supply Current

0.5

V

2.0

V
0.8

V

50

flA

Com'l

100

flA

Mil

250

= Max.

= Max., Vss~ VOUT~ Vee
= Max., VOUT = 0.5V[4]
Vee = Max., VIN = GND, Outputs Open

V

Mil

VIL

= Vee, Vee = Max.

Uuit

Mil

VIH

Vee

Max.

2.4

-250

Vee

-100

100

flA

Vee

-30

-120

rnA

Com'l

190

rnA

Mil

190

Capacitance[5]
Parameter

Max.

Unit

CIN

Input Capacitance

Description

8

pF

COUT

Output Capacitance

10

pF

Notes:
2. tA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has

5.

2-73

been chosen to avoid test problems caused by tester ground
degradation.
Tested initially and after any design or process changes that may affect
these parameters.

•

==:IF

_

PAL22VIOC
PAL22VPIOC

~

=====:;;:~

'CYPRESS
AC Test Loads and Waveforms
R1238Q

ALL INPUT PULSES
3.0V----

5V : F l ( 3 1 9
MIL)
Q
OUTPUT

j~8~~~NG
SCOPE

Equivalent to:

I-=

CL

-=

R2
170Q
(236Q

GND

THEVENIN EQUIVALENT

Parameter

Vx

tER(-)

1.5V

J/K/LN

o-------vvv----

Output Waveform-Measurement Level

2.08V = Vthc

THEVENIN EQUIVALENT

tER(+)

2.6V

tEA(+)

1.5V

tEA(-)

1.5V

136Q

OUTPUT

P/D

50pF
v10c-16

v10c-11

Commercial
Equivalent to:

Package

15 pF[7]

MIL)

99Q

OUTPUT

CL[6]

90%

o-------vvv----

2.13V = Vthm

Military
Notes:
6_ CL = 5 pF for tER measurement for all packages.

7.

VOH 05V
VOL

05V

Vx

05V

Vx

05V

~
~
~
~

t
~
~

t

Vx

v10c-12

Vx
v10c-13

VOH
v10c-14

VOL

v10c-15

For high-capacitive load applications (CL = 50 pF), use PAL22VlOG/
PAL22VPlOG.

Switching Characteristics[8]
22VIOC-6
22VIOC-7
22VIOC-IO
22VIOC-12
22VIOC-15
22VPIOC-6 22VPIOC-7 22VPIOC-IO 22VPIOC-12 22VPIOC-15
Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tpD

Input to Output Propagation
Delay[9]

1

6

2

75

2

10

2

12

2

15

ns

tEA

Input to Output Enable Delay

1

6

2

75

2

10

i

12

2

15

ns

tER

Input to
Delay[lO]

1

6

2

75

2

10

2

12

2

15

ns

tco

Clock to Output Delay[9]

1

55

1

6.0

1

75

1

95

1

10

ns

ts

Input or Feedback Set-Up Time

3

3

3.6

45

75

ns

tH

Input Hold Time

0

0

0

0

0

ns

tp

External Clock Period
(tco + ts)

85

9

11.1

14

17.5

ns

tWH

Clock Width HIGH[5]

3

3

3

3

6

ns

tWL

Clock Width LOW[5]

3

3

3

3

6

ns

fMAXI

External Maximum Frequency
(l/(tco + tS»[l1]

117

111

90

71

57

MHz

fMAX2

Data Path Maximum Frequency
(l/(tWH + twd)[5, 12]

166

166

166

166

83

MHz

fMAX3

Internal Feedback Maximum
Frequency (l/(tCF + tS»[13]

142

133

100

83

66

MHz

tCF

Register Clock to Feedback
Inpud l4]

tAW

Asynchronous Reset Width

tAR

Asynchronous Reset Recovery
Time

Parameter

Output

Disable

4

45

6.4

75

75

ns

7.5

8.5

10

12

15

ns

4

5

6

7

10

ns

2-74

PAL22VIOC
PAL22VPIOC
Switching Characteristics[8]
22VIOC-6
22VIOC-7
22VIOC-IO
22VIOC-12
22VIOC-15
22VPIOC-6 22VPIOC-7 22VPIOC-IO 22VPIOC-12 22VPIOC-15
Parameter

Description

Min. Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

2

12

2

12

2

14

2

20

ns

tAP

Asynchronous Reset to
Registered Output Delay

2

tSPR

Synchronous Preset Recovery
Time

4

5

6

7

10

ns

tpR

Power-Up Reset Time[15]

1

1

1

1

1

fls

11

Switching Waveform

R~~Mi~~~'6

•

-----

FEEDBACK
SYNCHRONOUS _ _ _....L.V
PRESET
14-_14----.1

CP - - - - - - - - ' 1

ASYNCHRO~E~~~

-

___________4-________~~JI

REGISTERED
OUTPUTS _ _ _ _ _ _ _l..JL~

COMBINATORIAL
OUTPUTS
v10c-17

Power-Up Reset Waveform[15]

~------------------------------------------------------VCC

1

POWER ________________
4V

"'"1-------~

REGISTERED
ACTIVE LOW
OUTPUT

tpR----------------~.!

-------------------------~~-----------------------------------------------~~

CLOCK
v10c-18

Notes:
8. AC test load used for all parameters except where noted.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.

13. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
14. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see Note 13) minus ts.
15. The registers in the PAL22VlOC/PAL22VPlOC have been designed
with the capability to reset during system power-up. Following powerup, all registers will be reset to a logic LOW state. The output state will
depend on the polarity of the output buffer. This feature is usefulin establishing state machine initialization. To insure proper operation, the
rise in Vee must be monotonic and the timing constraints depicted in
power-up reset waveforms must be satisfied.

2-75

PAL22VIOC
PAL22VPIOC

~

~PRESS

--

Preload Waveform[16]

PIN 13 (16)

Vpp

J.:

t OPR1

....\

PIN 2 (3)
PIN 3 (4)

I{

PIN 6(7)

\
If

PIN8 (10)

\

\

,

PIN 9 (11)

PRELOAD DATA
PINS 14-23
(17-21,23-27)

t OPR2

"'

l

CLOCK PIN 1 (2)

t OPR1

~X

t OPR2

tOPR1

-,Jl

t OPR2

t

~OPR1

\-

) -r
'-

/

./

t OPR2

\.

t OPR2

"-

t OPR2

t OPR1

t OPR1

L
t OPR1

X

-,r---:.

t OPR1

t OPR1 X

I

OUTPUTS
DISABLED

PRELOAD
DATA
CLOCKED
IN
PRELOAD DATA
VILP

or VIHP[17j

REGISTE RS
PRELOADED,
OUTPUT
ENABLE D
PRELOAD
DATA
REMOVED
v10c-19

D/K/P (J/LIY) Pinouts
Forced Level on Register Pin
During Preload

Register Q Output State
After Preload

VIHP

HIGH

VILP

LOW

Name

Description

Min.

Max.

Unit

VPP

Programming Voltage

9.25

9.75

V

tDPRl

Delay for Preload

1

tDPR2

Delay for Preload

0.5

VILP

Input LOW Voltage

0

0.4

V

VIHP

Input HIGH Voltage

3

4.75

V

Veep

Vee for Preload

4.75

5.25

V

lAs
lAS

Notes: (The numbers in parenthesis are for the J, L, and Y pins).
16. Pins 4 (5), 5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; V CC (Pin 24 (1 and 28» at V CeI'
17. Pins 2-8 (3-7, 9, 10), 10 (12), 11 (13) can be set at VIHP or VILP to insure asynchronous reset is not active.

2-76

PAL22VIOC
PAL22VPIOC
Functional Logic Diagram for PAL22VIOC/PAL22VPIOC
1
2)

rC>

0

4

8

12

16

20

24

28

32

36

40

AR

OE
0

;6b

~

Lb7·

~c::1--

cell

~~

OE
0

Wo- ~tb

·

~ cell

---f:::: 11

(4)

OE
0

R--'

(26)

21

(25)

TT

~
~
l=

cell

I>

~fr;J-

13

4

cell

S~

·
(5)

=tb
=tb
rr

~

·

22

L-.o--

s

OE
0

3

(27)

~

9

2
(3)

23

20

(24)

::=[h
~~
IT
=[h
~~
IT
::[h
~~
TT
=[h,

OE
0

1=
t=

I=~
~

5

OE
0

---f::;

I=~

1=
I=:~

OE
0

~

~

~~

OE
0

~

·

SAt - -

9

9

~

~ C1---

--D7

(12)

cell

6

( 19)

Tr

::[0,

~,.

OE
0

·

11
(13)

(20)

I=:

8

10

17

cell

~

~

---f:::: 13

11

(11)

(21)

~

15
OE
0

·
(10)

18

~

8

·
7
(9)

cell

1=
~

··
6
(7)

19
(23)

~

---f:::: 15

(6)

cell

~

I>

cell

5

(18)

T-r

;:~
cell

14
(1 7)

L.....-,-

-i::;SP

~

D/KIP (J/L!Y) Pinouts

2-77

13
(16)
v10c-20

I

PAL22VIOC
PAL22VPIOC
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

1.6

1.4

Jl1.2

~

II:

oZ

1.0

Y
0.8

~

~

/"

.9
0

w 1.2
:::J
N

«
~

1.0

II:

0

z
0.8

I
4.5

5.0

SUPPLY VOLTAGE

5.5

~

"
----'---w

1.2 , - - - - - . , - - - - - - - ,

0.9

0.8
4.0

25
125
AMBIENT TEMPERATURE (OC)

5.0

r---

5.5

6.0

NORMALIZED SET·UP TIME
vs. SUPPLY VOLTAGE

OUTPUTSS~CHING

o

4.5

---

SUPPLY VOLTAGE (V)

TYPICAL CORRECTION TO tpD
AND tco vs. NUMBER OF

z

'-......

:::J 1.0
«
::2
a:
0

M

NORMALIZED PROPAGATION
DELAYvs. TEMPERATURE

1\

N

0.6
-55

6.0

1.1

0

Z

TA = 25°C
0.6
4.0

1.2

1.4

()

o
~

~

NORMALIZED PROPAGATION
DELAYvs. SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT vs.
AMBIENT TEMPERATURE

O""'-r-~~~--'--~~~~

1.2

i=

~ ~ -0.2

~

1.1 1 - - - - - - + - - - - - - - - 1

Cl

w

~ 1.01-----~:;......------1

~
a:
o

a:~

8a: ;:0 -0.4 I--+-:'~+--I--+,...q..-+--f-I
wa:
2:: 0 -0.6 I--+--+--+-:II'F---I--+--+--i---l

~

0

(!l~

~ ~ -0.8 l--+--::rIF--+--+--+-+-+--f-1

z 0.91'-----1--------1

~·~'--5-----L.25-------1-:-'25·

~a::

-1.0

~

-1 .2

1.2

1.1 1------1------::;1"""--1

81.1

g:j

::::i 1.01------it#-'--------1

«

::2

I\.

~
~ 1.0
a:

1--~~--I--------1
25

1':--=-=--!-:~-=--:!:--!:--:!:-~

0.9

0.8
4.0

125

AMBIENT TEMPERATURE (0C)

o
Z

4.5

5.0

5.5

SUPPLY VOLTAGE

6.0

M

NORMALIZED CLOCK TO
OUTPUT TIME vs. TEMPERATURE

1.4,....------.--------,

o

Cl

0.9

«

~

-....----- ~

"-

a:

o

NORMALIZED CLOCK TO OUTPUT
TIME vs. SUPPLY VOLTAGE

NORMALIZED SET·UP TIME
vs. TEMPERATURE

~

:::J 1.0

NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE

1.2 , . . . . - - - - - , - - - - - - - - ,

a:

1.1

N

Z

AMBIENT TEMPERATURE (OC)

~

~

ow

0.9

0.8
4.0

"" --......
4.5

5.0

SUPPLY VOLTAGE

0

;:

1.3

0

w 1.2

N

:::J

'-.......

5.5

M

«

::2 1.1
a:
0
Z

6.0
AMBIENT TEMPERATURE (0C)
v10c·21

2-78

PAL22VIOC
PAL22VPIOC
1Ypical DC and AC Characteristics (continued)
DELTA tpo. teo vs.
OUTPUT LOADING

8.0

OUTPUT SINK CURRENT

E..
a()

oIl.
~

6.0 I----+----+---~~-I

/

w 90
~ 75

Z

II

2.0

I---"..."----+-~"""""-t---I

~ 60
Z

en
Iir
I-

::::l

o
25

50

75

45

30
15

/

/

0.0

..s

70

!zw

60

~ 50

/

"

§5
o
Vee = 5.0V TA = 25°C -

I

1.0

2.0

3.0

4.0

'"

"I\..

~ 40

o

OUTPUT VOLTAGE (V)

CAPACITANCE (pF)

vs. VOLTAGE

::::l

II

o

100

/

J

::::l

4.0 1----+-----17'''---+----1

:...J

W
Cl

<,120

.s
105
I-

en

OUTPUT SOURCE CURRENT

<'

vs. OUTPUT VOLTAGE

r----,---...,.---,-----,

""

30

~

20

~

10

o

0

~

::::l
::::l

1.0

0.0

2.0

\

3.0

OUTPUT VOLTAGE

\

4.0

M
v10c·22

Ordering Information
ICC

tpD

(mA)

(ns)

190

6

fMAX
(MHz)
117

7.5

111

Ordering Code
PAL22VlOC-61C
PAL22VlOC-7DC
PAL22VlOC-71C
PAL22VI0C-7PC
PAL22VlOC-7YC

10

90

PAL22VlOC-lODC
PAL22VI0C-101C
PAL22VlOC-lOPC
PAL22VI0C-lOYC
PAL22VlOCM -lODMB
PAL22VlOCM -lOKMB
PAL22VlOCM -lOLMB
PAL22VlOCM -lOYMB

12

71

PAL22VlOC-12DC
PAL22VlOC-121C
PAL22VlOC-12PC
PAL22VlOC-12YC
PAL22VlOCM -12DMB
PAL22VlOCM -12KMB
PAL22VlOCM -12LMB
PAL22VlOCM -12YMB

15

57

PAL22VlOCM -15DMB
PAL22VlOCM -15KMB
PAL22VlOCM -15LMB
PAL22VlOCM -15YMB

Package
Name
164
D14
164
P13
Y64
D14
164
P13
Y64
D14

Package
1Ype
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP

24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack

L64
Y64
D14

28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP

164

28-Lead Plastic Leaded Chip Carrier

P13

24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier

L64
Y64
D14
K73
L64
Y64

2-79

Commercial

28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier

K73

Y64
D14
K73

Operating
Range
Commercial
Commercial

24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack

Military

Commercial

Military

28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier

Military

I

PAL22VIOC
PAL22VPIOC

==- -'f~~
~

'CYPRESS
Ordering Information (continued)
ICC
(mA)

190

tpD
(ns)
6
7.5

fMAX
(MHz)
117
111

10

90

12

15

71

57

Ordering Code
PAL22VPlOC-6JC
PAL22VPI0C-7DC
PAL22VPlOC-7JC
PAL22VPlOC-7PC
PAL22VPlOC-7YC
PAL22VPlOC-lODC
PAL22VPlOC-lOJC
PAL22VPlOC-lOPC
PAL22VPlOC-lOYC
PAL22VPlOCM -lODMB
PAL22VPlOCM -lOKMB
PAL22VPlOCM -10LMB
PAL22VPlOCM -lOYMB
PAL22VPlOC-12DC
PAL22VPlOC-12JC
PAL22VPlOC-12PC
PAL22VPlOC-12YC
PAL22VPlOCM -12DMB
PAL22VPlOCM -12KMB
PAL22VPlOCM -12LMB
PAL22VPlOCM -12YMB
PAL22VPlOCM -15DMB
PAL22VPlOCM -15KMB
PAL22VPlOCM -15LMB
PAL22VPlOCM -15YMB

Package
1Ype
J64
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3
1,2,3

VIL

Irx
Ioz
Icc

1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameters

Subgroups

tpD

7, 8, 9, 10, 11

teo
ts
tH

7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11

Document #: 38-A-00020-D

2-80

28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Carrier

Operating
Range
Commercial
Commercial

Commercial

Military

Commercial

Military

Military

~

This is an abbreviated data sheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the PALC22VIOD
or PAL22VIOG.

'CYPRESS
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tPD = 7.5 ns
-ts = 3 ns
- fMAX = 100 MHz
- Drives SO-pF load (Cd
• "No Connect" PLCC pinout
• Up to 22 inputs and 10 outputs for
more logic power
• Variable product terms
- 8 to 16 per output
• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VPI0CF)

PAL22VIOCF
PAL22VPIOCF

Universal PAL® Device

• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse

Functional Description
The
Cypress
PAI22VlOCF
and
PAI22VPlOCF are second-generation
programmable array logic devices. Using
BiCMOS process and Ti-W fuses, the
PAL22VlOCF and PAL22VPI0CF use the
familiar sum-of-products (AND-OR) logic structure and a new concept, the programmable macro cell.

Both the PAL22VlOCF and PAI22VPlOCF
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22VlOCF and PAL22VPlQCF
feature variable product-term architecture, where 8 to 16 product terms are
allocated to each output. This structure
permits more applications to be implemented with these devices than with other
PAL devices that have fixed number of
product terms for each output.

Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
Vss

CPjl

10cl-1

Pin Configuration

PLCC (J)
Top View

__

~~9g'g

I
NC

-

- ;,

~- ~ ~

PAL is a registered trademark of Advanced Micro Devices.
Document #: 38-A-00047
2-81

10cf-2

I

PALC22VIOD

Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Advanced second-generation PAL architecture
• Lowpower
- 90 mA max. commercial (10 ns)
-130 mA max. commercial (7.5 ns)
• CMOS nash EPROM technology for
electrical erasabUity and reprogrammabillty
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macroceU
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 22 input terms and 10 outputs

• DIP, LCC, and PLCC available
-7.5 ns commercial version
S ns teo
Snsts
7.5 nstpD
133-MHz state machine
-10 ns military and industrial versions
6nsteo
6ns ts
10 ns tpD
nO-MHz state machine
-lS-ns commercial and military
versions
- 2S-ns commercial and military
versions
• High reUabillty

- Proven nash EPROM technology
-100% programming and functional
testing

Functional Description
The Cypress PALC22VIO~ is ~ CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the
programmable macrocell.
The PALC22VIOD is executed in a 24-pin
300-mil molded DIP, a 300-mil cerDIP, a
28-lead square ceramic leadless chip carrier,a28-leadsquareplasticleadedchipcarrier, and provides up to 22 inputs and 10
outputs. The 22VIOD can be electrically

Logic Block Diagram (pDIP/CDIP) and Pin Configurations

V10D-1

PLCC

LCC

Top View

Top View

__ ~~9g'~

I
I
NC
I

1/°2
1/°3
1/0 4

I

N/C

1/0 4

NC

1/0 5
1/0 6

I

N/C
1/05
I/OS
1/0 7

1/°2
1/03

1/07

- - oou-$'z

0><0

V10D-2

gg

PAL is a registered trademark of Advanced Micro Devices.

2-82

- - $ ~ - gg

V10D-4

--

-"~

PALC22VIOD

; CYPRESS

Functional Description (continued)
erased andreprogrammed. The programmable macrocell provides
the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as "reg.istered" or "combinatorial." Polarity of each output may also be llldividually selected, allowing complete flexibility of output
configuration. Further configurability is provided through "array"
configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by
the programmable array.
PALC22V10D features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms p~r
output. By providing this variable structure, the PALC22VlOD IS
optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22VlOD include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macro cells, eliminating the need
to dedicate standard product terms for initialization functions. The
device automatically resets upon power-up.

10 potential outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily enabled as an
output and an input through the selective use of individ~al pr?duct
terms associated with each output. Each of these outputs IS achieved
through an individual programmable macrocell. These macrocells are
programmable to provide a combinatorial or registered inverting or
non-inverting output. In a registered mode of operation, the output of
the register is fed back into the array, providing current status information to the array. This information is available for establishing the
next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, ifthe output is disabled, the signal present on the I/O pin is made available to the array.
The flexibility provided by both programmable product term control
of the outputs and variable product terms allows a significant gain in
functional density through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALC22V10D provides lower-power operation through the use of .
CMOS technology, and increased testability with Flash reprogrammability.

Configuration Table
Registered/Combinatorial

The PALC22V1 aD, featuringprogrammablemacrocells and variable
product terms, provides a device with the flexibility to implement logic
functions in the 500- to 800-gate-array complexity. Since each of the
10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only
a single output and down to 12 inputs and 10 outputs are possible. The

Cl

Co

a

0

Configuration
Registered/Active LOW

a

1

Registered/Active HIGH

1

0

Combinatorial/Active LOW

1

1

Combinatorial/Active HIGH

Macrocell

,,
,

~----------------------I

AR

,
,

>--.....'-----+--i

Q 1--------1

D

OUTPUT
SELECT
MUX

01--..----1

CP

SP
INPUT/
FEEDBACK
MUX

,,

C1

,

Co --------~------------------~~~~~--------~
L _ _ _ _ _ _ _ _ _ _MACROCELL
____________ ,
~

2-83

V10D·5

I

~CYPRESS

PALC22VIOD

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to +125°C
Supply Volt~ge to Ground Potential
(Pm 24 to Pm 12) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -O.5V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage ......................... 12.5V
Latch-Up Current ........................... >200 rnA

Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............. >2001V

Operating Range
Ambient
Temperature

Range
Commercial
Military[l]

O°C to +75°C

Vee
5V±5%

-55°C to +125°C

5V ±10%

Industrial

-40°C to +85°C

5V ±10%

Electrical Characteristics Over the Operating Rangd 2]
Parameter

Description

Min.

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.,
VIN = VIR or VIL

IOH= -3.2 rnA

Com'l

IOH= -2 rnA

Mil/Ind

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIR or VIL

IOL = 16 rnA

Com'l

IOL = 12 rnA

Mil/Ind

Max.

Unit

2.4

V

V

0.5

VIH

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

2.0

VIL[4]

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs[3]

-0.5

0.8

V

IIX

Input Leakage Current

Vss.5. VIN.5. Veo Vee = Max.

-10

10

flA

Ioz

Output Leakage Current

Vee = Max., Vss.5. VOUT .5. Vee

-40

40

flA

Ise

Output Short Circuit Current Vee = Max., V OUT = 0.5V[S,6]

-30

-90

rnA

IcC!

Standby Power Supply
Current

Ieez l6J

Operating Power Supply
Current

10,15,25 ns
Vee = Max.,
VIN = GND,
7.5
ns
Outputs Open in
Unprogrammed
15,25 ns
Device
10 ns

Com'l

10,15,25 ns

Com'l

Vee = Max., VIL =
Ov, VIR = 3V,
Output Open, Device Programmed as
a lO-Bit Counter,
f= 25 MHz

Mil/Ind

7.5 ns
15,25 ns

Mil/Ind

lOns

V

90

rnA

130

rnA

120

rnA

120

rnA

110

rnA

140

rnA

130

rnA

130

rnA

Capacitance[6]
Parameter
CIN
COUT

Description
Input Capacitance
Output Capacitance

Test Conditions
VIN = 2.0V @ f = 1 MHz

Min.

VOUT = 2.0V @ f = 1 MHz

Max.
10
10

Unit
pF
pF

Endurance Characteristics[6]
Description
Minimum Reprogramming Cycles

Test Conditions
Normal Programming Conditions

Notes:
1.
2.
3.
4.

TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.

5.
6.

2-84

Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.

-- -.,:z.
7 CYPRESS

PALC22VIOD

AC Test Loads and Waveforms
R1238Q

R1238Q

OUTP:~:F9(319Q
MIL)

5V:F1(319QMIL)
OUTPUT

INCLUDING
JIG AND
SCOPE

I-=

R2170Q
(236Q MIL)

CL

I-=

INCLUDING
JIG AND
SCOPE

-=

R2170Q
(236Q MIL)

5 pF

OUTPUT O--IP----1750Q
(1.2KQ
CL
MIL)

r

-=

V10D-6

(a)

(c)

(b)
ALL INPUT PULSES
3.0V---90%

I

GND

V10D-7

(d)

Equivalent to: THEVENIN EQUIVALENT (Military)

Equivalent to: THEVENIN EQUIVALENT (Commercial)

136Q

99Q

OUTPUT

o-----vw-------

2.08V = Vthc

OUTPUT

o-----vw-------

2.13V = Vthm

V10D-8

Load Speed
7.5,10, 15, 25 os

CL
50pF

Package
PDIP, CDIp,
PLCC,LCC

V10D-9

Parameter

Vx

tER(-)

1.5V
VOH 0.5V

tER(+)

2.6V

tEA(+)

OV

tEA(-)

Output Waveform-Measurement Level

Vthc

~

VOL

0.5V

Vx

1.5V

Vx

0.5V

~

~

~

~
~
~
~

(e) Test Waveforms

2-85

VX

V10D-10

Vx
V10D-11

VOH
V10D-12

VOL

V10D-13

\.~CYPRESS

PALC22VIOD

Commercial Switching Characteristics (PALC22VIOD) [2, 7]
22VIOD-7
Parameter

Description

22VIOD-IO

22VIOD-15

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

7.5

3

10

3

15

ns

tpD

Input to Output
Propagation Delay[8, 9]

tEA

Input to Outp'ut
Enable Delay[lO]

8

10

15

ns

tER

Input to Output
Disable Delay[ll]

8

10

15

ns

8

ns

tco

Clock to Output Delay[8, 9]

2

tSI

Input or Feedback Set-Up Time

5

6

10

tS2

Synchronous Preset Set-Up Time

6

7

10

ns

tH

Input Hold Time

0

0

a

ns

tp

External Clock Period (tco

10

12

20

ns

tWH

Clock Width HIGH[6]

3

3

6

ns

tWL

Clock Width LOW[6]

3

3

6

ns

fMAXI

External Maximum
Frequency (l!(tco + tS»[12]

100

76.9

55.5

MHz

fMAX2

Data Path Maximum Frequency
(l!(tWH + twd)[6, 13]

166

142

83.3

MHz

fMAX3

Internal Feedback Maximum
Frequency (l!(tCF + tS»[6, 14]

133

111

68.9

MHz

tCF

Register Clock to
Feedback Inputl 6, 15]

tAW

Asynchronous Reset Width

8

10

15

ns

tAR

Asynchronous Reset
Recovery Time

5

6

10

ns

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset
Recovery Time

6

8

10

ns

tpR

Power-Up Reset Timd6, 16]

1

1

1

f!s

+ ts)

5

2

2.5

7

2

3

12

ns

4.5

13

20

ns

ns

Notes:
7.

Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA( +). Part (b) of AC Test Loads and Waveforms is used
for tER. Part (c) of AC Test Loads and Waveforms is used for tEA( +).
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. The test load of part (a) ofACTest Loads and Waveforms is used for
measuring tEA(-l' The test load of part (c) of AC Test Loads and
Waveforms is used for measuring tEA( + ) only. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and
measurement reference levels.
11. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC Test Loads and Waveforms

12.
13.
14.
15.
16.

2-86

for enable and disable test waveforms and measurement reference
levels.
This specification indicates the guaranteed maximum frequency at which
a state machine configuration with external feedback can operate.
This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
This specification indicates the guaranteed maximum frequency at which
a state machine configuration with internal only feedback can operate.
This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 11 above) minus ts.
The registers in the PALC22VlOD have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
state machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.

--;:Z

PALC22VIOD

'CYPRESS

Military and Industrial Switching Characteristics (PALC22VIOD) [2, 7]
22VIOD-IO
Parameter

Description

22VIOD-15

22VIOD-25

Min.

Max.

Min.

Max.

Min.

Max.

Unit

3

10

3

15

3

25

ns

tpD

Input to Output
Propagation Delay[8, 9]

tEA

Input to Output Enable Delay[lO]

10

15

25

ns

tER

Input to Output Disable Delay[ll]

10

15

25

ns

tco

Clock to Output Delay[8, 9]

2

15

ns

tSI

Input or Feedback Set-Up Time

6

10

18

ns

tS2

Synchronous Preset Set-Up Time

7

10

18

ns

tH

Input Hold Time

0

0

0

ns

tp

External Clock Period (tco

12

20

33

ns

tWH

Clock Width HIGH[6]

3

6

14

ns

tWL

Clock Width LOW[6]

3

6

14

ns

fMAXI

External Maximum Frequency
(l/(tco + tS»[12]

76.9

50.0

30.3

MHz

fMAX2

Data Path Maximum Frequency
(l/(tWH + twd)[6, 13]

142

83.3

35.7

MHz

fMAX3

Internal Feedback Maximum
Frequency (1/(tCF + tS»[6, 14]

111

68.9

32.2

MHz

tCF

Register Clock to
Feedback Inputl6, 15]

+ ts)

7

2

3

8

2

4.5

13

ns

tAW

Asynchronous Reset Width

10

15

25

ns

tAR

Asynchronous Reset
Recovery Time

6

12

25

ns

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset
Recovery Time

8

20

25

ns

tpR

Power-Up Reset Timd6, 16]

1

1

1

Ils

12

2-87

25

20

ns

I

PALC22VIOD

rcYPRESS
Switching Waveform

R~~Mi~~~% ---T"7000.

FEEDBACK
SYNCHRONOUS ---~
PRESET
CP

ASYNCHRONOUS
RESET -------+~----+_JI
REGISTERED
OUTPUTS _ _ _ _ _ _...t...;.¥.,V

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _--'-~
V10D-14

Power-Up Reset Waveform[16]
POWER
SUPPLY VOLTAGE

10%

~~9~0~%-----------------------""VCC

------.::If''"

~------------ tpR------------~

REGISTERED -------1-t------~~~~~~~~~~~--------­
ACTIVE LOW
OUTPUTS -------i-+-------'~~~~~~~~
CLOCK
V10D-1S

2-88

PALC22VIOD
Functional Logic Diagram for PALC22VIOD

1-ri>

4

1

1

2

4

8

3

36

40

AR
OE

~~ ::~
"'"
~th

0

·

--f:>7
OE

--I

9

~

OE
0

·

"
::j~

11

3
OE
0

~

"'"

/

4

~srr-

13

OE
0

·
5

"'-

0

"'-

·

~

15

OE
0

22

L-.-

::~

21

cell

11"

::~

20

cell

IT

~1
ceil

::~

9

18

ceil

T

::tb
srr""

·
7

~ cell

~ IT

15

OE

6

23

-,.

0

2

cell

13

OE
0

H
~
~

·

=t-'"
S~

11

8

cell

17

rr

::~16
~

cell

TT

f~ ::th'5

OE
0

·

cell

9

...,

9
OE
0

~

·

@

~

7

10

:-~

~~
-v

SP

""T"T"

cell

~

/"t

11

13
V10D-16

2-89

14

•

PALC22VIOD
Ordering Information
(rnA)

Ice

tpD
(ns)

ts
(ns)

teo
(ns)

130

7.5

5

5

90

10

150

10

15

90
120

15

25

6
6

7.5
7.5

15

7
7

10
10

15

Ordering Code

Package
Name

PALC22V10D-7JC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22V10D-7PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-10JC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-lOPC

P13

24-Lead (300-Mil) Molded DIP

PALC22V10D-lODMB

D14

24-Lead (300-Mil) CerDIP

PALC22VlOD-101l

J64

28-Lead Plastic Leaded Chip Carrier

PALC22V10D-lOKMB

K73

24-Lead Rectangular Cerpack

PALC22V10D-lOLMB

L64

28-Square Leadless Chip Carrier

PALC22VlOD-lOPI

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-15JC

J64

28-Lead Plastic Leaded Chip Carrier

PALC22V10D-15PC

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-15DMB

D14

24-Lead (300-Mil) CerDIP

PALC22VlOD-1511

J64

28-Lead Plastic Leaded Chip Carrier

PALC22VlOD-15KMB

K73

24-Lead Rectangular Cerpack

PALC22VlOD-15LMB

L64

28-Square Leadless Chip Carrier

PALC22VlOD-15PI

P13

24-Lead (300-Mil) Molded DIP

PALC22VlOD-25DMB

D14

24-Lead (300-Mil) CerDIP

PALC22VlOD - 2511

J64

28-Lead Plastic Leaded Chip Carrier

PALC22V10D-25KMB

K73

24-Lead Rectangular Cerpack

PALC22VlOD-25LMB

L64

28-Square Leadless Chip Carrier

PALC22VlOD -25PI

P13

24-Lead (300-Mil) Molded DIP

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH
VOL
VIH
VIL
IIX
Ioz
IcC

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameter

Subgroups

tpD

9,10,11
9,10,11
9,10,11
9,10,11

teo
ts
tH

Package 1Ype

Document #: 38-00185-G

2-90

Operating
Range
Commercial
Commercial
Military/
Industrial

Commercial
Military/
Industrial

PAL22VIOG
PAL22VPIOG

PRELIMINARY

Universal PAL® Device
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tPD = 4ns
-ts = 2.5 ns
- fMAX = 166 MHz (External)
• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Up to 22 inputs and 10 outputs for
more logic power
• Variable product terms
- 8 to 16 per output
• 10 user-programmable output
macrocells
- Output polarity control

- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VPI0G)
• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse

Functional Description
The
Cypress
PAl22VlOG
and
PAl22VPlOG are second-generation programmable array logic devices. Using BiCMOS process and Ti-W fuses, the
PAL22V10GandPAL22VP10Gusethefamiliar sum-of-products (AND-OR) logic

structure and a new concept, the programmabIe macrocell.
Both the PAL22V10G and PAL22VPlOG
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22V10G and PAL22VPlOG
feature
variable
product
term
architecture, where 8 to 16 product terms
are allocated to each output. This
structure permits more applications to be
implemented with these devices than with
other PAL devices that have fixed number
of product terms for each output.

Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
CP/I

Vss

1109

1/°8

1/°7

1/°6

1/°4

1/°5

1/°3

1/°2

1/°1

v10g-1

Vss

PLCC (J)
Top View

LCC(L)
Top View

DIP (P,D)
Top View
CP/I

Vcc

1/°0

Pin Configurations
__ l\:uuBo
u5t5t;;:,:::,

__ l\:uuBrS
u5t5t:::,:::,

Vee
1/00
1/°1
1/°2
1/°3
1/04
1/05
I/Os
1/0 7
I/Os
I/Og
I

I
Vss
I

4 3 2:1: 282726
25
24
23
PAL22V10G
22
PAL22VP10G
9
21
10
20
11
19
12131415161718

1/0 2
1/03
1/04
Vss
1/0 5
1/°6
1/0 7

--CI)U)-O)a;)

v10g-2

:§P:§P

PAL is a registered trademark of Advanced Micro Devices.

2-91

~~

1/°2
1/0 3
1/°4
Vss
1/05
1/°6
1/°7

I
Vss
I

-

v10g-3

-

(J)

(f)-

:§P:§P

0)

ex)

~ ~

v10g-4

•

LJP~

PRELIMINARY

.'CYPRESS

PAL22VIOG
PAL22VPIOG

Functional Description (continued)

Programmable Macrocell

Additional features include common synchronous preset and
asynchronous reset product terms. They eliminate the need to use
standard product terms for initialization functions
Both the PAL22VlOG and PAL22VPlOG automatically reset on
power-up. In addition, the preload capability allows the output registers to be set to any desired state during testing.
A security fuse is provided on each of these two devices to prevent
copying of the device fuse pattern.
With the programmable macrocells and variable product term architecture, the PAL22VlOG and PAL22VPlOG can implement
logic functions in the 700 to 800 gate array complexity, with the inherent advantages of programmable logic.

The PAL22VI0G and PAL22VPI0G each has 10 programmable
output macrocells (see Macrocell figure). On the PAL22VlOG
two fuses (C1 and Co) can be programmed to configure output in
one of four ways. Accordingly, each output can be registered or
combinatorial with an active HIGH or active LOW polarity. The
feedback to the array is also from this output (see Figure 1). An
additional fuse (C2) in the PAL22VPlOG provides for two feedback paths (see Figure 2).

Programming
The PAL22VI0G and PAL22VPlOG can be programmed using
the Impulse3 programmer available from Cypress Semiconductor
and also with Data I/O, Logical Devices, STAG and other programmers. Please contact your local Cypress representative for
further information.

Macrocell
OE

r----------------------,

I
I
I
I
I
I

AR

r--+----------.-~

D

Q 1-------1

OUTPUT
SELECT
MUX

01--.-----1

CP

Key:
AR =
SP =
OE =
CP =

SP

INPUT/
FEEDBACK
MUX
S1

~

C1

Co --------~------~------------------------------~

C2 [1]

L _ _ _ _ _ _ _ _ _ _MACROCELL
___________ _
---------+-------'
v10g-5

Output Macrocell Configuration
C2[1J

Cl

Co

Output'JYpe

0

0

0

Registered

0

0

1

Registered

Active HIGH

Registered

X

1

0

Combinatorial

Active LOW

I/O

Polarity
Active LOW

Feedback
Registered

X

1

1

Combinatorial

Active HIGH

I/O

1

0

0

Registered

Active LOW

1/0[1]

1

0

1

Registered

Active HIGH

1/0[1]

Notes:
1. PAL22VPIOG only.

2-92

Asynchronous RESET
Synchronous PRESET
Output Enable
Clock Pulse

PAL22VIOG
PAL22VPIOG

PRELIMINARY

AR

AR

C 2 [11=

0

C2[11=

C1 = 0
Co = 0

0

= 0
Co = 1
C1

v10g-6

v10g-7

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

C2 [1 1= X
C1 = 1
Co = 0

C2[1 1= X

C1 = 1
Co = 1
v10g-9

v10g-B

I/O FEEDBACK, COMBINATORIAL, ACTIVE-LOW OUTPUT

I/O FEEDBACK, COMBINATORIAL, ACTIVE-HIGH OUTPUT

Figure I. PAL22VIOG and PAL22VPIOG Macrocell Configurations

AR

AR

SP

SP
v10g-10

v10g-11

I/O FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

I/O FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

Figure 2. Additional Macrocell Configurations for the PAL22VPIOG

2-93

•

_.~

-=--,

-=r

PAL22VIOG
PAL22VPIOG

PRELIMINARY

CYPRESS

Selection Guide

Icc (rnA)

Commercial

tpD (ns)

Commercial

22VI0G-4
22VPI0G-4
190

22VI0G-S
22VPI0G-S
190

22VI0G-6
22VPI0G-6
190

4

5

6.0

7.5

Military

22VI0G-7
22VPI0G-7
190
190

Commercial
Military

2.5

2.5

3.0

7.5
3.0
3.0

Commercial

3.5

4/4.5

5.5

6.0

166

153.8

117

6.0
111

Military
ts (ns)
teo (ns)

Military
fMAX (MHz)
(External)

Commercial

111

Military

22VI0G-I0
22VPI0G-I0
190
190
10
10
3.6
3.6
7.5
7.5
90
90

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................... -O.5V to Vee
DC Input Voltage ......................... -O.5V to Vee
DC Input Current .................... - 30 rnA to +5 rnA
(except during programming)

DC Program Voltage .............................. lOV
Junction Temperature (PLCC) ....... , ............ 150°C

Operating Range
Range
Commercial
Military[2]

Ambient
Temperature
O°Cto +70°C

Vee
5V±5%

-55°C to + 125°C

5V ± 10%

DC Electrical Characteristics Over the Operating Range
Parameter
VOH

Description
Output HIGH Voltage

Test Conditions

Min.

Max.

Unit

Vee = Min.,
VIN = VIH or VIL

IOH = -3.2 rnA

Com' I

2.4

V

IOH= -2 rnA

Mil

2.4

V

IOL = 16 rnA

Com'l

IOL = 12 rnA

Mil

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for All Inputs[3]

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for All Inputs[3]

IIX

Input Leakage Current

Vss.5. VIN.5. 2.7V, Vee = Max.

II

Maximum Input Current

VIN = Vee, Vee = Max.

0.5

V

0.5

V

2.0

V
0.8

V

50

~A

Com'l

100

~A

Mil

250

flA

-250

Ioz

Output Leakage Current

Vee = Max., V ss .5. VOUT .5. Vee

-100

100

flA

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.5V[4]

-30

-120

rnA

Icc

Power Supply Current

Vee = Max., VIN = GND, Outputs Open

Com'l

190

rnA

Mil

190

Notes:
2. tA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

4.

2-94

Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground
degradation.

PAL22VIOG
PAL22VPIOG

PRELIMINARY
Capacitance[5]
Parameter

Description

Unit

'!Yp.

CrN

Input Capacitance

6

pF

COUT

Output Capacitance

8

pF

AC Test Loads and Waveforms
R1238Q

ALL INPUT PULSES

OUTP~~ : F l ( 3 1 9MIL)
Q
INCLUDING
JIG AND
SCOPE

I-=

3.0V---90%
R2170Q
(236Q MIL)

CL

-=

GND

Equivalent to: THEVENIN EQUIVALENT
99Q

OUTPUT

v10g-17

v10g-12

o-------wv-----

Parameter

Vx

tER(-)

1.5V

2.08V = Vthc

Commercial
Equivalent to: THEVENIN EQUIVALENT

tER(+)

2.6V

tEA(+)

L5V

tEA(-)

1.5V

136Q

OUTPUT

o-------wv----Military

2.13V = Vthm

Notes:
5.
6.

Tested initially and after any design or process changes that may affect
these parameters.
CL = 5 pF for tER measurement for all packages.

2-95

Output Waveform-Measurement Level

VOH O.5V

~

VOL

O.5V

Vx

O.5V

Vx

O.5V

~

~

I t:
I t:
~

Vx

v10g-13

Vx
v10g-14

VOH
v10g-15

VOL

v10g-16

•

PAL22VIOG
PAL22VPIOG

~

PRELIMINARY

rCYPRESS
Switching Characteristics[7)

Parameter
tpD
tEA
tER
tco
ts
tH
tp
tWH
tWL
fMAXl
fMAX2
fMAX3
tCF
tAW
tAR
tAP

tSPR
tpR

Description
Input to Output
Propagation Delay[8)
Input to Output
Enable Delay
Input to Output
Disable Delay[9)
Clock to Output
Delay[8)
Input or Feedback
Set-Up Time
Input Hold Time
External Clock
Period (tco + ts)
OockWidthHlGHL:lJ
Oock Width WWL5J
External Maximum
Frequency
(lJ(tco + tS))[lO)
Data Path Maximum
Frequency [5, 11, 12)
Internal Feedback
Maximum Fre~uency
(lJ(tCF + ts))[ , 13)
Register Clock to
Feedback Input[14)
Asynchronous Reset
Width
Asynchronous Reset
Recovery Time
Asynchronous Reset
to Registered
Output Delay
Synchronous 'l"i'eset
Recovery Time
Power-Up Reset
Timd 15 )

22VIOG-4
22VPIOG-4
Min. Max.
1
4

22VIOG-5
22VPIOG-5
Min. Max.
1
5

22VIOG-6
22VPIOG-6
Min. Max.
1
6

22VIOG-7
22VPIOG-7
Min. Max.
2
7.5

22VIOG-IO
22VPIOG-IO
Min.
Max.
10
2

Unit
ns

1

5

1

6

1

6

2

7.5

2

10"

ns

1

4

1

5

1

6

2

7.5

2

10

ns

1

3.5

1

4

1

5.5

1

6.0

1

7.5

ns

2.5

2.5

3

3

3.6

ns

0
6.0

0
6.5

0
8.5

0
9

0
11.1

ns
ns

2.0
2.0
166

2.5
2.5
153.8

3
3
117

3
3
111

3
3
90

ns
ns
MHz

250

200

166

166

133

MHz

181.8

181.8

142

133

100

MHz

3

4

3

4.5

6.4

ns

5

6

7.5

8.5

10

ns

4

4

4

5

6

ns

2
4
1

6

.

7

2

2

11

2

12

2

12

ns

4

4

5

6

ns

1

1

1

1

[lS

Notes:
7. AC test load used for all parameters except where hoted.
8. Th~~ specification is guaranteed for all device outputs changing state in
a gIven access cycle.
9. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
10. This specification indicates the guaranteed maximum frequency at which
a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
12. Lesser of I/(tWH +twL), Ilteo or l/(tS+tH)'

13. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal-only feedback can
operate.
14. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see Note 11) minus ts.
15. The registers in the PAL22VI0G and PAL22VPlOG have been designed with the capability to reset during system power-up. Following
power-up, all registers will be reset to a logic LOW state. The output
state will depend on the polarity of the output buffer. This feature is
useful in establishing state machine initialization. To insure proper operation, the rise in Vee must be monotonic and the timing constraints
depicted in power-up reset waveforms must be satisfied.

2-96

PRELIMINARY

PAL22VIOG
PAL22VPIOG

Switching Waveform

R~~~,T~~~'6

- ..............-.

FEEDBACK
SYNCHRONOUS _--'-...K....I_
PRESET
14--+t-~

CP------"I

tER[9]

tEA

tER[9]

tEA

REGISTERED
OUTPUTS _ _ _ _ _ _........_

II

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _...............
v10g-18

Power-Up Reset Waveform[15]

4_V~~~-----------

Vee

POWER _ _ _ _ _ _ _ _

tpR

REGISTERED
ACT~G~~u~

.1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

v10g-19

2-97

PAL22VIOG
PAL22VPIOG

~

===

PRELIMINARY

rcYPRESS

Preload Waveform[16]

PIN 13 (16)

Vpp

J.:

\

t OPR1

I--

PIN2 (3)

PIN 3 (4)

If

PIN 6 (7)

\

If

PIN 8 (10)

~

\
If

PINg (11)

PRELOAD DATA
PINS 14-23
(17-21,23-27)

t OPR2

t OPR2

/
t OPR2

_J

If..
CLOCK PIN 1 (2)
t

OPR1

t OPR2

tOPR1

'"

-,I,

t OPR2

I

..\I
t OP R1

'"

>-

/

"-

"-

t OPR2

t OPR1

t OPR1

IL
t OPR1

'"

OUTPUTS
DISABLED

-,

~
t OPR1

VILP

or VIHP[17j

~

t OPR1

1\

I
PRELOAD
DATA
CLOCKED
IN

PRELOAD DATA

"-

V-

REGISTE RS
PRELOAOED,
OUTPUT
ENABLE
PRELOAD
DATA
REMOVED

o

v10g-20

Notes (the numbers in parantheses refer to J and L packages):
16. Pins 4 (5), 5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; Vee (Pin 24 (1 and 28)) at VeeI'
17. Pins 2-8 (3-7, 9,10),10 (12),11 (13) can be set at VIHP or VILP to insure asynchronous reset is not active.
Forced Level on Register Pin
During Preload

Register Q Output State
Mter Preload

VIHP

HIGH

VILP

LOW

Name

Description

Min.

Max.

Vpp

Programming Voltage

9.25

9.75

Delay for Preload

1

tDPR2

Delay for Preload

0.5

VILP

Input LOW Voltage

VIHP

Input HIGH Voltage

Vccp

V cc for Preload

tDPRl

Unit
V
f,lS
f,ls

0

0.4

V

3

4.75

V

4.75

5.25

V

2-98

.

-.;~

PAL22VIOG
PAL22VPIOG

PRELIMINARY

'CYPRESS
Functional Logic Diagram for PAL22VIOG/PAL22VPIOG
1

(2)

-r{>

0

4

8

12

16

20

24

28

AR
OE

Lf:::7

·

(26)

"""r""""""T'"""

OE
0

S~
S~

::±r
==frJ- IT
::±r
¥-- TT
::±r
rr- TT
::±r
==frJ- IT
=±r
n~d- ::±r

0

~

-"
~

·
0

~
~

0

0

~
~

0

5~

OE
0

·

16
(19)

15

cell

(18)

9

9

TT'

OE
0

·
11
(13)

~

S~

11

8

(12)

cell

Sr--

·

10

17
(20)

~

~

13

OE

(11)

cell

S

·

(10)

18
(21)

5

15

OE

7

cell

~

~

(9)

19
(23)

'""'"'"'
:;::j

~

(7)

cell

~

5

15

OE

6

20
(24)

S

·
(6)

cell

~

~

13

OE

5

TT

=.

OE

21
(25)

cell

S~

11

3

4

22

cell

9

·

(5)

23

(27)

I=>ct---- ::±r
= ::±r

0

(4)

40

cell

OE

(3)

36

Wd- :::&

0

2 -r:::

32

IW

;::&

:::1----

~7
~SP

........,

cell

14

(17)

'---r""'
13
(16)

DIP (J/L) Pinouts

2-99

v10g·21

I

-.;~
~;CYPRESS
Ordering Information
tpD
Icc
fMAX
(rnA)

190

(ns)
4
5
6
7.5

(MHz)
166
153.8
117
111

10

90

tpD
(ns)
4
5
6
7.5

fMAX
(MHz)
166
153.8
117
111

10

90

Icc

(rnA)

190

PRELIMINARY

Ordering Code
PAL22VlOG-41C
PAL22VlOG-51C
PAL22VlOG-61C
PAL22V10G-71C
PAL22VlOG-7PC
PAL22VIOG-7LMB
PAL22VIOG-101C
PAL22VlOG-lOPC
PAL22VlOG-lOLMB
Ordering Code
PAL22VPlOG-41C
PAL22VPlOG-51C
PAL22VPlOG-61C
PAL22VPlOG-71C
PAL22VPlOG-7PC
PAL22VPlOG-7LMB
PAL22VPlOG-101C
PAL22VPlOG-IOPC
PAL22VPlOG-lOLMB

Package
Name
164
164
164
164
Pl3
L64
164
P13
L64

28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-MiI)Molded DIP
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Square Leadless Chip Carrier

Package
'!Ype
164
164
164
164
P13
L64
164
P13
L64

Package
'!Ype
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Square Leadless Chip Carrier

Shaded area contains advanced information.

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameters

Subgroups

VOH
VOL
VIH

1,2,3
1,2,3
1,2,3

VrL

1,2,3

Irx

1,2,3

Ioz

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

tpD

7, 8, 9, 10, 11

teo
ts

7, 8, 9, 10, 11
7,8,9, 10, 11

tH

7, 8, 9, 10, 11

PAL22VIOG
PAL22VPIOG

Document #: 38-A-00044-B

2-100

Package '!Ype

Operating
Range
Commercial
Commercial
Commercial
Commercial
Military

Military
Operating
Range
Commercial
Commercial
Commercial
Commercial
Military

Military

CY7C330

CMOS Programmable
Synchronous State Machine
Features
• 1Welve I/O macrocells each having:
- registered, three-state I/O pins
- input register clock select multiplexer
- feed back multiplexer
- output enable (OE) multiplexer
• All twelve macrocell state registers
can be hidden
• User-configurable state registersJK, RS, T, or D
• One input multiplexer per pair of I/O
macrocells allows I/O pin associated
with a hidden macrocell state register
to be saved for use as an input
• Four dedicated hidden registers
• Eleven dedicated, registered inputs

• Three separate clocks-two inputs,
one output
• Common (pin 14-controlled) or
product term-controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
• 66-MHz operation
- 3-ns input set-up and 12-ns clock to
output
-15-ns input register clock to state
register clock
• Lowpower
-130mAlcc

• 28-pin, 300-mil DIP, LCC
• Erasable and reprogrammable

Functional Description
The CY7C330 is a high-performance, erasable, programmable, logic device (EPLD)
whose architecture has been optimized to
enable the user to easily and efficiently
construct very high performance synchronous state machines.
The unique architecture of the CY7C330,
consisting of the user-configurable output
macrocell, bidirectional I/O capability, input registers, and three separate clocks, enables the user to design high-performance
state machines that can communicate either with each other or with microprocessors over bidirectional parallel buses of
user-definable widths.

Logic Block Diagram

Selection Guide
Maximum Operating Frequency,
fMAX (MHz)

Commercial

Power Supply Current ICCl (rnA)

Commercial

7C330-66
66.6

Military
140

7C330-50
50.0

7C330-40

50.0

40.0

2-101

7C330-28
28.5

130

130
160

Military

7C330-33
33.3

150

150

~'i~

CY7C330

'CYPRESS
Pin Configuration

Input Clock Multiplexer, and architecture configuration bit C4
which determines the input clock selected.
I/O Macrocell

LCC/PLCC
Top View
5)!

The logic diagram of CY7C330 I/O macrocell is shown in Figure 2
There are a total of twelve identical macrocells.

-~8dg'g-~

Functional Description (continued)
Three separate clocks permit independent, synchronous state
machines to be synchronized to each other. The two input clocks,
Cl, C2, enable the state machine to sample input signals that may
be generated by another system and that may be available on its
bus for a short period of time.
The user-configurable state register flip-flops enable the designer
to designate JK-, RS-, T-, or D-type devices, so that the number of
product terms required to implement the logic is minimized.
The major functional blocks of the CY7C330 are (1) the input
registers and (input) clock multiplexers, (2) the EPROM (AND)
cell array, (3) the twelve I/O macrocells and (4) the four hidden
registers.
Input Registers and Clock Multiplexers

Each macro cell consists of:
- An Output State register that is clocked by the global state
counter clock, CLK (Pin 1). The state register can be configured
as aD, JK, RS, or T flip-flop (default is a D-typeflip-flop). Polarity can be controlled in the D flip-flop implementation by use of
the exclusive or function. Data is sampled on the LOW to HIGH
clock transition. All of the state registers have a common reset
and set which are controlled synchronously by Product Terms
which are generated in the EPROM cell array.
- A Macrocell Input register that may be clocked by either the
CK1 or CK2 input clock as programmed by the user with architecture configuration bit C2, which controls the I/O Macrocell Input Clock Multiplexer. The Macrocell Input registers are initialized upon power-up such that all of the Q outputs are at logic
LOW level and the Q outputs are at a logic HIGH level.
- An Output Enable Multiplexer (OE), which is user programmable using architecture configuration bit CO, can select either
the common OE signal from pin 14 or, for each cell individually,
the signal from the output enable product term associated with
each macrocell. The output enable input signal to the array product term is clocked through the input register by the selected input register clock, CK1 or CK2.
- An Input Feedback Multiplexer, which is user programmable,
can select either the output of the state register or the output of
the Macrocell Input register to be fed back into the array. This
option is programmed by architecture configuration bit Cl. If the
output of the Macrocell Input register is selected by the Feedback
Multiplexer, the I/O pin becomes bidirectional.

There are a total of eleven dedicated input registers. Each input
register consists of a D flip-flop and a clock multiplexer. The
clock multiplexer is user-programmable to select either CK1 or
CK2 as the clock for the flip-flop. CK2 and OE can alternatively
be used as inputs to the array. The twenty-two outputs of the registers (i.e., the Q and Q outputs of the input registers) drive the
array of EPROM cells.

co

An architecture configuration bit (C4) is reserved for each dedicated input register cell to allow selection of either input clock
CKI or CK2 as the input register clock for each dedicated input
cell. If the CK2 clock is not needed, that input may also be used as
a general-purpose array input. In this case the input register for
this input can only be clocked by input clock CKl. Figure 1 illustrates the dedicated input cell composed of an input register, an
D

TO ARRAY

e330-4
FROM ADJACENT MACROCELL

C4
C3

e330-3

Figure 2. Macrocell and Shared Input Multiplexer

Figure 1. Dedicated Input Cell

2-102

CY7C330
Functional Description (continued)
Macrocell Input Multiplexer
Each pair ofl/O macrocells share a Macrocell Input Multiplexer that
selects the output of one or the other of the pair's input registers to
be fed to the input array. This multiplexer is shown in Figure 2. The
Macrocell Input Multiplexer allows the input pin of a macrocell, for
which the state register has been hidden by feeding back its input to
the input array to be preserved for use as an input pin. This is possible as long as the other macrocell of the pair is not needed as an
input or does not require state register feedback. The input pin input
register output that would normally be blocked by the hidden state
register feedback can be routed to the array input path of the companion macrocell for use as array input.
State Registers
By use of the exclusive OR gate, the state register may be configured as aJK-, RS-, orT-type register. The default is aD-type register. For the D-type register, the exclusive OR function can be
used to select the polarity or the register output.
The set and reset of the state register are global synchronous signals. They are controlled by the logic of two global productterms,
for which input signals are clocked through the input registers by
either of the input clocks, CK1 or CK2.
Hidden Registers
In addition to the twelve macrocells, which contain a total of
twenty-four registers, there are four hidden registers whose outputs are not brought out to the device output pins. The Hidden
State Register Macrocell is shown in Figure 3.
The four hidden registers are clocked by the same clock as the
macrocell state registers. All of the hidden register flip-flops have

'-

J)

1S

"'

D

./

PIN 1, CLK
GLOBAL RESET PRODUCT TERM

-I>

Each pair of macrocells has a total of thirty-two product terms.
Two product terms of each macrocell pair are used for the output
enables (OEs) for the two output pins. Two product terms are
also used as one input to each ofthe two exclusive OR gates in the
macrocell pair. The number of product terms available to the designer is then 32 - 4 = 28 for each macrocell pair. These product
terms are divided between the macrocell state register flip-flops
as show in Table 1.
Table 1. Product Term Distribution for Macrocell
State Register Flip-Flops
Macrocell

Pin Number

Product Terms

0
1
2
3
4
5
6
7
8
9
10
11

28
27
26
25
24
23
20
19
18
17
16
15

9
19
11
17
13
15
15
13
17
11
19
9

Hidden State Register Product Term Distribution
Each pair of hidden registers also has a total of 32 product terms.
Two product terms are used as one input to each of the exclusive
OR gates. However, because the register outputs do not go to any
output pins, output enable product terms are not required.
Therefore, 30 product terms are available to the designer for each
pair of hidden registers. The product term distribution for the
four hidden registers is shown in Table 2.

GLOBAL SET PRODUCT TERM

:_/

a common, synchronous set, S, as well as a common, synchronous
reset, R, which override the data at the D input. The Sand R signals are product terms that are generated in the array and are the
same signals used to preset and reset the state register flip-flops.
Macrocell Product Term Distribution

Table 2. Product Term Distribution for Hidden Registers

Q

a I--

"-+-

Hidden Register Cell

Product Terms

0
1
2
3

19
11
17
13

TO ARRAY

~

...

Architecture Configuration Bits

e330·5

Figure 3. Hidden State Register Macrocell

2-103

The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in
Table 3.

CY7C330
Table 3. Architecture Configuration Bits
Architecture
Configuration Bit
Output Enable
CO
Select MUX
C1

C2

C3

C4

Number of Bits

Function

12 Bits, 1 per I/O Macrocell

Value
0-Virgin State
1-Programmed

Output Enable Controlled by Pin 14

State Register
Feedback MUX

12 Bits, 1 per I/O Macrocell

0-Virgin State

State Register Output is Fed Back to Input Array

1-Programmed

I/O Macrocell is Configured as an Input and Output of Input Register is Fed to Array

I/O Macrocell
Input Register
Clock Select MUX

12 Bits, 1 per I/O Macrocell

0-Virgin State

CK1 Input Register Clock (Pin 2) is Connected to
I/O Macrocell Input Register Clock Input

1-Programmed

CK2 Input Register Clock (Pin 3) is Connected to
I/O Macrocell Input Register Clock Input

I/O Macrocell Pair
Input Select MUX

6 Bits, 1 per I/O Macrocell
Pair

0-Virgin State

Selects Data from I/O Macrocell Input Register
of Macrocell A of Macrocell Pair

1-Programmed

Selects Data from I/O Macrocell Input Register
of Macrocell B of Macrocell Pair

0-Virgin State

CK1 Input Register Clock (Pin 2) is Connected to
Dedicated Input Register Clock Input

1-Programmed

CK2 Input Register Clock (Pin 3) is Connected to
Dedicated Input Register Clock Input

Dedicated Input
Register Clock
Select MUX

11 Bits, 1 per Dedicated
Input Cell

Output Enable Controlled by Product Term

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................. -65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 22 to Pins 8 and 21) ................ -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ -O.5V to +7.0V
DC Input Voltage ...................... -3.0Vto +7.0V
Output Current into Outputs (LOW) .............. 12 rnA
Static Discharge Voltage ....................... >2001V
(per MIL-STD-883, Method 3015)

2-104

Latch-Up Current ........................... >200 rnA
DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . .. 13.0V

Operating Range
Range
Commercial
Military[lj

Ambient
Temperature
O°C to +75°C

Vee
5V ± 10%

-55°C to +125°C

5V ± 10%

Note:
1. TA is the "instant on" case temperature.

CY7C330
Electrical Characteristics Over the Operating Rangd 2]
Description

Parameter

Min.

Test Conditions

Unit

Max.

2.4

VOR

Output HIGH Voltage

Vee = Min., VIN = VIR or VIL
lOR = -3.2 rnA (Com'l), lOR = -2 rnA (Mil)

VOL

Output LOW Voltage

Vee = Min., VIN = VIR or VIL,
IOL = 12 rnA (Com'l), lOR = 8 rnA (Mil)

VIR

Input HIGH Voltage

Guaranteed Logical HIGH Voltage for all Inputs[3]

VIL

Input LOW Voltage

Guaranteed Logical LOW Voltage for all Inputs[3]

IIX

Input Leakage Current

Vss < VIN < Vee, Vee

V
0.5

V

2.2

= Max.

-10

= Max., Vss < VOUT < Vee,
= Max., VOUT = 0.5V[5]
Commercial - 66
Vee = Max., VIN = GND

V
0.8

V

+10

!-LA

loz

Output Leakage Current

Vee

-40

+40

!-LA

Isd 4]

Output Short Circuit Current

Vee

-30

-90

rnA

IcC!

Standby Power Supply
Current

140

rnA

Outputs Open

Power Sup~ly Current at
Frequency 4, 6]

Iee2

Commercial -33, -50

Vee = Max.
Outputs Disabled
(in High Z State),
Device Operating at fMAX
External (fMAXI)

130

Military -50

160

Military -28, -40

150

Commercial - 66

180

Commercial - 33, - 50

160

Military -50

200

Military -28, -40

180

rnA

Capacitance[4]
Parameter

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Min.

= 2.0V at f = 1 MHz,
VOUT = 2.0V at f = 1 MHz,
VIN

Notes:
2. See the last page of this specification for Group A subgroup testing
information.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4. Tested initially and after any design or process changes that may affect these parameters.

5.

6.

Max.

Unit

10

pF

10

pF

Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
Tested by periodic sampling of production product.

AC Test Loads and Waveforms
R1313Q

R1313Q

OUTP~~ § f l ( 4 7 0Mil)Q

I

50 pF
INCLUDING _
JIG AND
SCOPE

OUTP~~ S f 1 ( 4 7 0Mil)Q
R2 20SQ
(319Q Mil)

_
-

Equivalent to:

I

(b)

~

c330-7

c330·6

Equivalent to:

THEVENIN EQUIVALENT (Commercial)

OUTPUT

90%

R2 20SQ
(319Q Mil) GND
_
~ 5 ns
-

5 PF
INCLUDING _
JIG AND
SCOPE

(a)

ALL INPUT PULSES
3.0V

THEVENIN EQUIVALENT (Military)

190Q
OUTPUT ()--'W'V----() 2.02V = Vthm

2.00V = Vthc
c330-8

2-105

c330-9

..

~

CY7C330

-=-~ CYPRESS

AC Test Loads and Waveforms (continued)
Parameter
tpXZ(-)

tpXZ(+)

Vx

1.5V

Output Waveform-Measurement Level

O.5V~

2.6V
VOL

tpZX(+)

tCER(-)

tCER(+)

Vthc

1.5V

VOH

0.5V~

2.6V
VOL

tCEA(+)

0.5V~

Vthc
Vx

tCEA(-)

Vthc

c330-11

VOH
c330-12

~~

VOL

c330-13

~~

Vx

c330-14

~~

Vx

~~

VOH

c330-15

c330-16

~~

Vx
0.5V;

c330-10

Vx

~~

0.5V~
0.5V~

Vx

Vx

~~

O.5V~

Vthc
Vx

tpZX(-)

~~

O.5V~

VOH

VOL

0330-17

(c) Test Waveforms and Measurement Levels

Switching Characteristics Over the Operating Rangd 2, 7]

Parameter
tIS

tos
tco
tIH
tCEA
tCER
tpzx
tpxz

Description
Input or Feedback
Set-Up Time to Input
Register Clock
Input Register Clock to
Output Register Clock
Output Register Clock to
Output Delay
Input Register Hold Time
Input Register Clock to
Output Enable Delay
Input Register Clock to
Output Disable Delay[8]

Military
Commercial
-50
-50
-40
-28
-66
-33
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
10
5
5
10
3
5

15
12

20
20

15

35

25
15

20

ns
25

ns

20

20

30

20

25

35

ns
ns

20

20

30

20

25

35

ns

20

20

30

20

25

35

ns

20

20

30

20

25

35

ns

5

Pin 14 Enable to Output
Enable Delay
Pin 14 Disable to
Output Disable Delay[8]

30

20

Unit
ns

5

5

5

5

5

tWH

Input or OutRut Clock
Width HIGH[4, 6]

6

8

12

8

10

15

ns

tWL

Input or Out~ut Clock
Width LOW '1,6]

6

8

12

8

10

15

ns

2-106

·

-.,~

CY7C330

'CYPRESS
Switching Characteristics Over the Operating Rangd 2, 7] (continued)

Parameter

Description
Output Data Stable Time
from S~nchronous Clock
Input[
troH- tIH Output Data Stable Time
This Device Minus liP
Reg Hold Time Same
Devicd lO]
tOH

Military
Commercial
-66
-50
-33
-50
-40
-28
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
3
3
3
3
3
3

Unit
ns

0

0

0

0

0

0

ns

tOH - tIH
33x

Output Data Stable Time
Minus liP Reg Hold Time
7C330 and 7C332
Devices[ll]

0

0

0

0

0

0

ns

tp

External Clock Period
(treo + trs), Input and
Output Clock Common
Maximum External
Operating FreJtuency
(l/(tco + trs» 2]
Maximum Regster Toggle
Frequency[6, ]

15

20

30

20

25

35

ns

66.6

50.0

33.3

50.0

40.0

28.5

MHz

83.3

62.5

41.6

62.5

50.0

33.3

MHz

74.0

57.0

37.0

57.0

45.0

30.0

MHz

fMAXI

fMAX2
fMAX3

Maximum Internal
Operating Frequency[14]

Notes:
7. Part (a) of AC Test Loads is used for all parameters except tCEA,
tCER, tpzx, and tpxz, which use part (b).
8. This parameter is measured as the time after output register disable
input that the previous output data state remains stable on the output. This delay is measure to the point at which a previous HIGH level has fallen to O.SV below VOH Min. or a previous LOW level has
risen to O.SV above VOL Max. Please see part (c) of AC Test Loads
and Waveforms for enable and disable test waveforms and measurement reference levels.
9. This parameter is measured as the time after output register clock input
that the previous output data state remains stable on the output.
10. This difference parameter is designed to guarantee that any 7C330
output fed back to its own inputs externally or internally will satisfy
the input register minimum input hold time. This parameter is guaranteed for a given individual device and is tested by a periodic sampling of production product.

11. This specification is intended to guarantee feeding of this signal to
another 33X family input register cycled by the same clock with sufficient output data stable time to insure that the input hold time minimum
of the following input register is satisfied. This parameter difference
specification is guaranteed by periodic sampling of production product
of 7C330 and 7C332. It is guaranteed to be met only for devices at the
same ambient temperature and V cc supply voltage.
12. Thisspecificationindicates the guaranteed maximum frequency at which
a state machine configuration with external feedback can operate.
13. This specification indicates the guaranteed maximum frequency at
which an individual input or output register can be cycled.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with only internal feedback can
operate. This parameter is tested periodically on a sample basis.

Switching Waveform
I/O INPUTS,
REGISTERED _ _ _....
FEEDBACK
INPUTS
INPUT CLOCK

OUTPUT CLOCK

OUTPUTS

---"""'-r

PIN 14
OE
c330·18

2-107

I

.;~
~'CYPRESS
~

CY7C330

CY7C330 Logic Diagram (Upper Halt)

2-108

CY7C330

CY7C330 Logic Diagram (Lower Half)

2-109

s=-_~

CY7C330

_,CYPRESS
Ordering Information
(max)

fMAX
(MHz)

140

66.6

ICCI

160

130

150

130

150

50

50

40

33.3

28.5

Ordering Code

Package
Name

Package 1Ype

CY7C330-66HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-661C

164

28-Lead Plastic Leaded Chip Carrier

CY7C330 - 66PC

P21

28-Lead (300-Mil) Molded DIP

CY7C330-66WC

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C330-50DMB

D22

28-Lead (300-Mil) CerDIP

CY7C330-50HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-50LMB

L64

28-Square Leadless Chip Carrier

CY7C330-500MB

064

28-Pin Windowed Leadless Chip Carrier

CY7C330-50TMB

T74

28-Lead Windowed Cerpack

CY7C330-50WMB

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C330-50HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-501C

164

28-Lead Plastic Leaded Chip Carrier

CY7C330-50PC

P21

28-Lead (300-Mil) Molded DIP

CY7C330-50WC

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C330-40DMB

D22

28-Lead (300-Mil) CerDIP

CY7C330-40HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-40LMB

L64

28-Square Leadless Chip Carrier

CY7C330-400MB

064

28-Pin Windowed Leadless Chip Carrier

CY7C330-40TMB

T74

28-Lead Windowed Cerpack

CY7C330-40WMB

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C330-33HC

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-331C

164

28-Lead Plastic Leaded Chip Carrier

CY7C330-33PC

P21

28-Lead (300-Mil) Molded DIP

CY7C330-33WC

W22

28-Lead (300-Mil) Windowed CerDIP

CY7C330- 28DMB

D22

28-Lead (300-Mil) CerDIP

CY7C330-28HMB

H64

28-Pin Windowed Leaded Chip Carrier

CY7C330-28LMB

L64

28-Square Leadless Chip Carrier

CY7C330- 280MB

064

28-Pin Windowed Leadless Chip Carrier

CY7C330- 28TMB

T74

28-Lead Windowed Cerpack

CY7C330-28WMB

W22

28-Lead

2-110

(300~Mil)

Windowed CerDIP

Operating
Range

Commercial

Military

Commercial

Military

Commercial

Military

-

-.,:Z

CY7C330

?CYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

Switching Characteristics
Parameter

Subgroups

tIS

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

tos
tco
tCEA

tpzx

Document #: 38-00064- D

2-111

CY7C331

Asynchronous Registered EPLD
Features
• Thelve I/O macrocells each having:
- One state flip-flop with an XOR
sum-of-products input
- One feedback flip-flop with input
coming from the I/O pin
- Independent (product term) set,
reset, and clock inputs on all
registers
- Asynchronous bypass capability on
all registers under product term
control (r = s = 1)
- Global or local output enable on
three-state I/O
- Feedback from either register to
the array
• 192 product terms with variable distribution to macrocells

• 13 inputs, 12 feedback I/O pins, plus 6
shared I/O macrocell feedbacks for a
total of 31 true and complementary
inputs
• High speed: 20 ns maximum tpD
• Security bit
• Space-saving 28-pin slim-line DIP
package; also available in 28-pin
PLCC
• Lowpower
- 90 rnA typical Icc quiescent
-180 rnA Icc maximum
- UV-erasable and reprogrammable
- Programming and operation 100%
testable

Functional Description
The CY7C331 is the most versatile PLD
available for asynchronous designs. Central resources include twelve full D-type
flip-flops with separate set, reset, and clock
capability. For increased utility, XOR
gates are provided at the D-inputs and the
product term allocation per flip-flop is
variably distributed.

I/O Resources
Pins 1 through 7 and 9 through 14 serve as
array inputs; pin 14 may also be used as a
global output enable for the I/O macrocell
three-state outputs. Pins 15 through 20 and
23 through 28 are connected to I/O macrocells and may be managed as inputs or outputs depending on the configuration and
the macrocell OE terms.

Logic Block Diagram
10

1/0 11

1/0 10

II0g

IIOa

1/0 6

1/0 1

Vee

GND

1/0 0

C331-1

Selection Guide
Generic Part
Number
CY7C331-20

IcC! (rnA)
Com'l
Mil

CY7C331-25

160
150

CY7C331-30
CY7C331-40

130
120

tpD (ns)
Com'l

ts (ns)
Mil

20

150

25

25
30
40

2-112

Com'l
12
12

Mil
15
15
20

tco (ns)
Com'l
Mil
20
25

25
30
40

-'i~

CY7C331

'CYPRESS
Pin Configuration

PLCC

The D-type flip-flop that is fed from the array (i.e., the state flipflop) has a logical XOR function on its input that combines a single
product term with a sum(OR) of a number of product terms. The
single product term is used to set the polarity of the output or to
implement toggling (by including the current output in the product
term).

Top View

.£'~:.9g'~~
1/0 3
1/04
1/0 5

The Rand S inputs to the flip-flops override the current setting of
the '0' output. The S input sets '0' true and the R input resets '0'
(sets it false). If both Rand S are asserted (true) at once, then the
output will follow the input ('0' = 'D') (see Table 1).

Vee
GND
1/0 6
1/0 7
o

~ N

~

0

(J)

ex:>

.:-.:-~~~~~

Table 1. RS Truth Table

C331-2

I/O Resources (continued)
It should be noted that there are two ground connections (pins 8
and 21) which, together with Vee (pin 22) are located centrally on
the package. The reason for this placement and dual-ground structure is to minimize the ground-loop noise when the outputs are
driving simultaneously into a heavy capacitive load.

The CY7C331 has twelve I/O macrocells (see Figure 1 ). Each macrocell has two D-type flip-flops. One is fed from the array, and one from
the I/O pin. For each flip-flop there are three dedicated product terms
driving the R, S, and clock inputs, respectively. Each macrocell has
one input to the array and for each pair of macrocells there is one
shared input to the array. The macrocell input to the array may be
configured to come from the '0' output of either flip-flop.

R

S

Q

1

o

o

1
1

1
D

o

Shared Input Multiplexer
The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the '0' output of the flip-flop coming from the I/O pin is used
as the input signal source (see Figure 2).

Product Term Distribution
The product terms are distributed to the macro cells such that 32
product terms are distributed between two adjacent macrocells.

TO PIN 14 (INVERTED)
OE PTERM

OUT SET PTERM

TO I/O PIN
OUT ClK PTERM

OUT RESET PTERM
IN ClK PTERM
IN SET PTERM
IN RESET PTERM
XOR PTERM
OR PTERMS
TO INPUT BUFFER

INPUT FLIP-FLOP

TO SHARED
INPUTMUX

C331-3

TO PIN 14 (INVERTED)

Figure 1. I/O Macrocell

2-113

CY7C331
Product Term Distribution (continued)
The pairing of macrocells is the same as it is for the shared inputs.
Eigh t of the product terms are used in each macrocell for set, reset,
clock, output enable, and the upper part of the XOR gate. This
leaves 16 product terms per pair of macrocells to be divided between the sum-of-products inputs to the two state registers. The
following table shows the I/O pin pairing for shared inputs, and the
product term (PT) allocation to macrocells associated with the I/O
pins (see Table 2).
Table 2. Product Term Distribution
Macrocell

Pin Number

0
1
2
3
4
5
6
7
8
9
10
11

28
27
26
25
24
23
20
19
18
17
16
15

Product Terms
4
12
6
10
8
8
8
8
10
6
12
4

OUTPUT FROM
LOGIC ARRAY
MACROCELLA
FEEDBACK TO - - - 7 ' 1
LOGIC ARRAY _ _~~
Q-OUTPUT FROM
INPUT REGISTER OF
1/0 MACROCELL A
INPUTTO - - - . . , . . . ,
LOGIC ARRAY

----o-..J

Q-OUTPUT FROM
INPUT REGISTER OF
I/O MACROCELL B

r-----.J..--...,

The CY7C331 is configured by three arrays of configuration bits
(CO, Cl, C2). For each macro cell, there is one CO bit and one Cl
bit. For each pair of macro cells there is one C2 bit.
There are twelve CO bits, one for each macrocell. If CO is programmed for a macro cell, then the three-state enable (OE) will be
controlled by pin 14 (the global OE). If CO is not programmed,
then the OE product term for that macrocell will be used.
There are twelve Cl bits, one for each macrocell. The Cl bit selects
inputs for the productterm (PT) array from either the state register
(if the bit is unprogrammed) or the input register (if the bit is programmed).
There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the C2 bit
is not programmed, then the input to the product term array comes
from the upper macrocell (A). If the C2 bit is programmed, then
the input comes from the lower macrocell (B).
The timing diagrams for the CY7C331 cover state register, input
register, and various combinational delays. Since internal clocks
are the outputs of product terms, all timing is from the transition of
the inputs causing the clock transition.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -65°C to +150°C
Ambient Temperature with
Power Applied ....................... , -55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 8 or 21) .................... -O.5V to +7.0V
DC Input Voltage ........................ -3.0V to +7.0V
Output Current into Outputs (LOW) ............... 12 rnA
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . .. 13.0 V

Operating Range

OUTPUT FROM
LOGIC ARRAY

Range
Commercial

MACROCELLB
FEEDBACK TO
LOGIC ARRAY ----2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
DC Programming Voltage .......................... 13.0V

C4

MACROCELL
INPUT REGISTER

Operating Range
C2

CO

C1

Range
Commercial

C332-5

Figure 3. I/O Macrocell

Military[l]

Ambient
Temperature
O°C to +75°C

Vcc
5V ± 10%

-55°C to + 125°C

5V ± 10%

Electrical Characteristics Over the Operating Range
Parameter
VOH

VOL

Test Conditions

Description
Output HIGH Voltage

Output LOW Voltage

Vee == Min.,
VIN == VIR or VIL
Vee == Min.,
VIN == VIR or VIL

Min. Max.

lOR == - 3.2 mA

Commercial

lOR == -2mA

Military

10L == 12mA

Commercial

10L == 8mA

Military

2.4

Unit
V

0.5

V

VIR

Input HIGH Voltage

Guaranteed HIGH Input, all Inputs[2]

VIL

Input LOW Voltage

Guaranteed LOW Input, all Inputs[2]

IIX

Input Leakage Current

Vss < VIN < Vee, Vee == Max.

loz

Output Leakage Current

Vee == Max., Vss < VOUT < Vee,

-40

+40

f-lA

-30

-90

mA

Commercial

120

rnA

Commercial -15

130

Isc

Output Short Circuit Current

Vee == Max., VOUT == 0.5V[3]

lecl

Standby Power Supply
Current

Vee == Max., VIN == GND
Outputs Open

lec2

Power Sup~ly Current at
Frequency 4, 5]

Vee == Max.
Outputs Disabled (In High Z State)
Device Operating at fMAX
External (fMAXl)

Notes:
1. TA is the "instant on" case temperature.
2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.

4.
5.

2-128

V

2.2

-10

0.8

V

+10

f-lA

Military

150

Military -20

160

Commercial

180

Military

200

Tested by periodic sampling of production product.
Refer to Figure 4 configuration 2.

rnA

--:--

-.,~

CY7C332

; CYPRESS
Capacitance[6]
Parameter

Test Conditions

Description

CIN

Input Capacitance

COUT

Output Capacitance

= 2.0V at f = 1 MHz,
VOUT = 2.0Vat f = 1 MHz,
VIN

Max.

Unit

10

pF

10

pF

Note:
6. Tested initially and after any design or process changes that may affect
these parameters.

AC Test Loads and Waveforms
R1313Q

R1313Q

OUTP~~ §=l(470Q
MIL)
50 pF

I

INCLUDING
JIG AND
SCOPE

_
-

R2 208Q
(319Q MIL)
_
-

I_
(b)

3.0V

90%

R2 208Q
(319Q MIL) GND

5 PF

INCLUDING
JIG AND
SCOPE

(a)
Equivalent to:

ALL INPUT PULSES

OUTP~~ 5 r } ( 4 7 0MIL)Q

I

~ 5 ns

_
C332-6

C332-7

Equivalent to:

THEVENIN EQUIVALENT (Commercial)

THEVENIN EQUIVALENT (Military)

190Q
OUTPUT ~ 2.02V = Vthm

125Q

OUTPUT ~ 2.00V = Vthc

C332-9

C332-8

Parameter
tpXZ(-)

Vx
1.5V

Output Waveform-Measurement Level
VOH

o.svl
tpXZ(+)

2.6V
VOL

tPZX(+)

Vthc
Vx

tpZX(-)

tER(-)

tER(+)

Vthc

1.5V

2.6V

Vthc

Vthc

~~
~~

VX

C332-10

Vx
C332-11

VOH
C332-12

o.svl

~F:

Vot

C332-13

o.sJ

~F:

Vx

C332-14

VOH

Vx
tEA(-)

O.5V~

Vx

VOL
tEA(+)

O.5V~

~F:

O.5V~
O.5V~

Vx

o.svl

~~

~~

~F:

(c) Test Waveforms and Measurement Levels

2-129

Vx
C332-15

VOH
C332-16

VOL

C332-17

~

.,~:rcYPRESS

CY7C332

Switching Characteristics Over the Operating Range[2]
Commercial

-15[7]
Parameter

Description

Military

-20

-20[7]

-25

-25

-30

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Unit

tpD

Input to Output
Propagation Delay[8]

15

20

25

20

25

30

ns

tlca

Input Register Clock to
Output Delay[9]

18

20

25

23

25

30

ns

tIS

Input or Feedback
Set-Up Time to Input
Register Clock[9]

3

3

3

4

4

4

ns

tm

Input Register Hold
Time [9]

3

3

3

4

4

4

ns

tEA

Input to Output Enable
Delay[lO,l1]

20

20

25

25

25

30

ns

tER

Input to Output Disable
Delay[lO,l1]

20

20

25

25

25

30

ns

tpzx

Pin 14 Enable to Output
Enable Delay[8, 12]

15

15

20

20

20

25

ns

tpxz

Pin 14 Disable to Output Disable Delay[8, 12]

15

15

20

20

20

25

ns

tWH

Input Clock Width
High[4,9]

9

10

10

10

10

12

ns

tWL

Input Clock Width
Low[4,9]

9

10

10

10

10

12

ns

tIOH

Output Data Stable
Time from Input Register Clock Input[7, 9]

3

3

3

3

4

4

ns

tIOH-tm

Output Data Stable
Time This Device Minus
lIP Reg Hold Time
Same Devicel7, 13, 14]

0

0

0

0

0

0

ns

tIOH tm 33x

Output Data Stable
Time Minus lIP Reg
Hold Time 7C330 and
7C332 Devicel9, 15]

0

0

0

0

0

0

ns

tpE

External Clock Period
(tlCO + tIS)[9]

21

23

28

27

29

34

ns

fMAXI

Maximum External
Operating Fre~uency
(1I(tlca + tIS» 9]

47.6

43.4

35.7

37

34.4

29.4

MHz

fMAX

Maximum Frequency
Data Path[9]

55.5

50.0

40.0

50.0

40.0

33.3

MHz

Notes:
7. Preliminary specifications.
8. Refer to Figure 4 configuration 1.
9. Refer to Figure 4 configuration 2.
10. Part (a) of AC Test Loads and Waveforms is used for all parameters
except tEA, tER, tpzx, and tpxz, which use part (b). Part (c) shows test
waveform and measurement reference levels.
11. Refer to Figure 4 configuration 3.
12. Refer to Figure 4 configuration 4.
13. Refer to Figure 4 configuration 5.

14. This specification is intended to guarantee that configuration 5 of Figure 4 with input registered feedback can be operated with all input register clocks controlled by the same source. These parameters are
tested by periodic sampling of production product.
15. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C332. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supplyvoJtage. These parameters are tested periodically by sampling of production product.

2-130

-=====-.

-=-~PRESS

CY7C332

CONFIGURATION 1

PIN

~-------{~===l

INPUT OR I/O PIN

INPUT REGISTER
CONFIGURATION 2

CLOCK 1 OR2

~-------{~==:l PRODUCT
TERM
ARRAY

CONFIGURATION 3

INPUT OR I/O PIN

~I~

1-------------------.

PIN

~-------{~==j

CONFIGURATION 4

INPUT OR I/O PIN

INPUT REGISTER

DATA
INPUT

CONFIGURATION 5

PRODUCT
TERM
ARRAY

CLOCK 1 OR2

DATA
OUTPUT

CLOCK 1 OR2

C332-18

Figure 4. Timing Configurations

Switching Waveforms
INPUT OR
I/O PIN[16]

INPUT
CLOCK[17]

PIN 14
ASOE
4 - - troH[5]

tpZX[12]

OUTPUT

C332-19

Notes:
16. Because OE can be controlled by the OE product term, input signal
polarity for control of OE can be of either polarity. Internally the
product term OE signal is active HIGH.

17. Since the input register clock polarity is programmable, the input clock
may be rising- or falling-edge triggered.

2-131

~

-~,:rcYPRESS

CY7C332

CY7C332 Logic Diagram (Upper Half)

~~o

8

16

24

32

L9603
(GO, 1,3)

48
L971 0 (MBO .. 10)

~72~~~

L9600
(GO, 1,3)

&{ ..

40

L550

L9650
(GO..4)
28

L9655
(GO..4)
27

19

.

3
L9606
(GO .. 3)

-<:J-

L9742 (MB32..44)

L1600

"~
~B:5

.

4

L9755

L961 0
(GO .. 3)

L9660
(GO..4)
26

.. 63)

L9665
(GO..4)
25

17

...

L9774(~78)

5
L9614
(GO .. 3)

13

...

L9670
(GO..4)
24

...

6
L9618
(GO.. 3)

L3950
L9675
(GO..4)
23

2-132

==-- - ~

CY7C332

'CYPRESS
CY7C332 Logic Diagram (Lower Half)

I

7

-- TO UPPER SECTION

~~_~_~lijll~II~II~I~I~II~II~I~II~1~11~lijl~
L4800

L9622
(CO ..3)

L9680

(CO..4)
20

~

L9823 (MS 113 .. 127)

L5650

L9685

(CO..4)
19

13

.

10

~

L6400

L9630
(CO .. 3)

L9690

(CO..4)
18

17

....

~

11

~~:~

L7350

L9634

(CO .. 3)

L9695

(CO..4)
17

....
12
L9638
(CO .. 3)

L9870 (MB160 .. 180)

L8000

L9700

(CO..4)
16

19

13
L9891
L9642

L9050

(CO .. 3)
9
L9646

(CO .. 3)

~~~mH~~~~~mm~illW
2-133

(M~.191)

~

tt:::=:::