1994_Harris_Data_Acquisition 1994 Harris Data Acquisition

B:ON BUFFER 000···00 TO 111···10 FIGURE 3. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 6-52 . , ~OV HI1166 Test Circuits (Continued) lIN ·1V A -2V -5.ZV FIGURE 4. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT H111. LOGIC ANALVZER 1024 SAMPLES Aperture jitter Is defined as follows: Au 256 TAJ = of At = of ( T x 2ld) FIGURE SA. FIGURE 5B. APERTURE JmER TEST METHOD Where 0 (unit: LSB) is the deviation of the output codes when the input ft:equency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 5. SAMPUNG DELAY AND APERTURE JmER TEST CIRCUIT 6·53 HI 1276 a-Sit, 500MSPS Flash December 1993 AID Converter Features Description • Differential Uneartty Error ±O.5 LSB or ..... The HI1276 is a 6-bit ultra high speed flash Analog·ta-Digital converter Ie capable of digitizing analog signals at a maximum rate of 500MSPS. The digital VO levels of this AID con· verter are compatible with EeL 100Kl10KHl10K. • Integral Unearlty Error ±O.7 LSB or I.88s • Built-In Integral UnearHy Compensation Circuit • Ultra High Speed Operation with Maximum Conversion Rate oI500MSPS (Min.) The HI1276 is available in the Industrial temperature range and is supplied in a 68 lead ceramic Lee package. • Low Input capacitance 20pF (Typ.) • Wide Analog Input BandWIdth 300MHz (Min. for Full-Scale Input) Ordering Information • Single Power Supply -5.2V PART NUMBER • Low Power Consumption 2.8W (Typ.) • Low Error Rate • capable of Driving TEMPERATURE RANGE PACKAGE -2O"C to +1 oO"C 68 Lead Ceramic LCC H11276AIL son Loads • Evaluation Board Available Applications • Radar Systems • Communication Systems • Digital Oscilloscopes • Direct RF Down-Converalon Pinout H11276 (LeC) TOP VIEW Z S If! ZgZi§ SSSS '" '" g SIS is SIS g g D !Ja is!!l!! !i! g S DGND1 DGND1 DYe OS DVM D1 56 DO D7 DO 57 "5Ii OR UNV AVe AVe NC VRIlI VRJ AVEE AVEE AGND MINV m • 35 34 33 32 31 30 28 23 27 CLK AVEE AVEE NC VRBS VRB AVEE AVe AGND !i!!i!i!i!liillIJJI!i!!i!!i!!i! CAUTION: These d8\licea are aansiIIve \0 electrostatic discharge. Users should follow proper I.e. Handling Procedu..... Copyrlght@Harris Corporation 1993 6·54 File Number 3578.1 HI1276 Functional Block Diagram MlNV ~--------------------~:~,}---------------~ COMPARATOR ENCODE LOGIC I--+--!ljtt"", ~::!::=---<1}-------..II UNV 6-55 Specifications HI1276 Thermal Information Absolute Maximum Ratings Til" +25"C Supply Voltage (AVEE' DVEE) •••••••••••••••••••• -7V to +O.5V Thermal ResIstance 9JA . 9JC HI1276A/L ••• ••• ..... •• ••. ••••••• . 18"CIW 4"CN1 Analog Input Voltage (V,N) •••••••••••••••••.••.• -2.7 to +O.5V MaxlIIIU'II Power DIssipation ........................... 3.8W Reference Input Voltage VRT, VReo VAM ••••••••••••••••••••••••••••• AVEE to +O.5V Operating Temperature (Note 5) Til" ................................... -2O"C to +1 OO"C IVRrVRBI .........................................2.5V Tc .••••••••••••••••••••••••••••••.•••• -2O"C to +125"C Digital Input Voltage Maximum Junction Temperature •••••••••••••••••••••• +175"C MINV~ ................................. -4V to +O.5V CLK, Q~ ............................... DVEE to +O.5V ICLK-CLKI ••••••••••••••••••••••••••••• , •.••••••• 2.7V VRM Pin Input Current (IYAM) ................... -3mA to +3mA Digital Output Current (100 to 107, lOR, iDa to iD7, iOR) ............. -3OmA to 0mA Storage Temperature Range (TSTG)' ••••••••••• -65"C to +15O"C Lead Temperature (Soldering 1Os). • • • • • . • • • • . • • • • • • • • +3OO"C CAUTION: s _ allow IhoSIJ nst.d In 'l4bsoIuII Mex/mum Rat/ntIS" may cause"."".".", damage to /he dBvIca ~ Is • _ only I8ling and opBl8tion of tha dwIt» .t Iheaa or any 0111... CD/ldilJonll abow Ihoae IndIcatad In /he opatational SiICIioM of IIIIs specification Is not imp/i«I. Operating Conditions (Note 1) Supply Voltage AVEE, DVEE ••.•••••••.•••••••••••••••.••• -5.5V to -4.95V AVEF:"DVEE .............................. -o.05V to O.05V AGND-DGND ............................ -o.05V to O.05V Electrical Specifications TA Reference Input Voltage VAT.......................................-o.1VtoO.1V VRB ..................................... -22Vto-1.8V Analog Input VoIlage, Y,N ••••••••••.••••••••••••• ,VRB to VAT =+25"C, AVEE = DVEE = -5.2V, VAT' VATS = OV, VAllo VRBS " -2V (Note 1) PARAMETER TEST CONDITIONS I MIN I TYP I MAX I UNIT SYSTEM PERFORMANCE Aperture Jitter, TAl Input = 150MHz 500 - 11 - Sampling Delay, Tos Input = 150MHz 0.2 0.8 1.5 30 - 70 Resolution Integral Unearity Error, (INL) Fc=500MHz Differential Unearity Error, (DNL) Fc=5OOMHz DYNAMIC CHARACTERISTICS Input", 1kHz, Ful Scale Fc .. 5OOMHz Input 100MHz, Full Scale Fc=5OOMHz Input 100MHz, Full Scale Error> 18 LSB, Fc .. 400MHz Input .. 125MHz, Full Scale Error> 18 LSB, Fc. 500MHz Signal to Noise Rello (SINAD) RMSSlgnai RMS Noise + Distortion = = = Error Rete Differential Gain Error, DG NTSC 40IRE Mod. Ramp, Fc = 500MSPS Differential Phase Error, DP Overrenge Recovery Time Maximum Conversion Rate, Fc 8 to.3 - Bits to.7 LSB to.3 to.5 LSB 46 37 - dB dB 10.11 10~ TPS (Note 3) 10" 10" TPS (Note 3) 1.0 0.5 1.0 - % Degree ns MSPS ps ns ANALOG INPUT Input Bias Current, liN V,N =-1V Full Scale Input Bandwidth Y,N =2Vp.p 300 - 620 - 70 110 160 Note 2 0.1 0.5 2.0 R2 0.5 52 10 R3 R4 0.5 1.6 5.0 0.5 8.7 20 R5 0.1 0.5 2.0 Analog Input Capacllance, C'N Y,N = 1V + O.07VRMs Analog Input Resistance, R,N 20 pF kO JIA MHz REFERENCE INPUTS Reference Resistance, RREF Realdual Resistance R1 6-56 n n n n n n Specifications HI1276 Electrical Specifications TA =+25"C, AVEE = DVEE =-5.2V, Vm , vms =OV, VRIIo VRBS =-2V (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - V DIGITAL INPUTS - -1.10 Logic H L.svel, VIH Logic L L.svel, VIL Logic H Current, IIH Input Connected to -a.8V logic L Current, IlL Input Connected to -1.6V Input Capacitance -50 - ~=500 logic L Level, VOL ~=500 - -1.03 - V 70 JIA JIA 60 - 6 DIGITAL OUTPUTS logic H Level, VOH -1.55 I I pF V V -1.58 TIMING CHARACTERISTiCS Clock Duty Cycle Output Rise Time, T R Output Fall Time, T F =500, 20% to 80% ~ =500, 80% to 20% ~ Output Delay, Too 45 50 55 % 0.5 0.7 1.0 ns 0.5 0.7 1.0 ns 1.5 1.9 2.3 ns -680 -520 I - 2.8 I 3.6 POWER SUPPLY CHARACTERISTICS Supply Current, lEE Power Consumption, Po - Note 4 rnA I W NOTES: 1. Electrical Specifications guaranteed within stated operallng oondltlons. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. (VRT-V RB ) 2 4. P D = IEEA eAVEE+IEEDeDVEE+--=R:---REF 5. TA is specilled in slill air and without heatslnk. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2). Timing Diagram ANALOG IN ----- '. " .., .., .., .... CLK DIGITAL OUT N-1 N FIGURE 1. 6-57 HI1276 Typical Performance Curves -0.45 20r-------~--------_r--------,_~ !J -0.47 $ ~ i I i t -0.411 B ~ 10r--------i---------t--------;--; ~ -0.51 ."" " iil -0.53 ~ °0~------~--------~2--------~3~ -0.55-50 o AIR FLOW (mls) -0.80 ./ -0.85 w !g -CIB.O / -0.85 -1.05 1 / Iiw IX! IX! 8 ~ / -1.00 CI V ~ -16 '!so -20 ~ c; w 50 100 CASE TEMPERATURE <"C) -22 -24 150 -50 -1.60 ~ w ! -1.65 g ... -1.70 , '" 50 100 CASE TEMPERATURE ("C) 150 ........... ~ -1.32 , w !g -1.34 ifi ~ -1.36 I~ -1.38 ~ ~ -1.80 o o -1.30 ........... ~ -1.75 § / / FIGURE 5. REGISTER STRING CURRENT va TEMPERATURE CHARACTERISTICS FIGURE 4. DO PIN HIGH LEVEL VOLTAGE V$ TEMPERATURE CHARACTERISTICS -1.55 V IX! / o /' -18 IX! -1.1 150 v -14 ~ 2: ~ 50 100 CASE TEMPERATURE <"C) FIGURE 3. SUPPLY CURRENT V$ TeMPERATURE CHARACTeRISTICS FIGURe 2. THERMAL RESISTANCE MOUNTED ON-BOARD ...w ...:c>w '"'" 50 100 CASE TEMPERATURE ("C) -1.40-50 150 -- ..---- 0 50 ......... 100 CASE TEMPERATURE <"C) FIGURe 6. DO PIN LeVEL VOLTAGE va TEMPERATURE CHARACTeRISTICS FIGURE 7. CD< PIN OpeN VOLTAGE va TEMPERATURE CHARACTERISTICS 6-58 150 HI1276 Typical Performance Curves (Continued) 40 50 r--- 45 m 40 I"- 40 \., :!!. z~ 3S ! 30 , -40 THIRD HARMON~ .so ~ .so -80 10 100 INPUT FREQUENCY (MHz) 1 ~ ·70 600 1 - ~ ~~ 100 10 INPUT FREQUENCY (MHz) 500 10-6 10-6 INPUT FREQUENCY. CLOCK FREQUENCY/, 16 LSB OR MORE ERROR 10".7 ft:. 1cr4' a: 5!a: w ~ FIGURE 9. HARMONIC DISTORTION va INPUT FREQUENCY CHARACTERlSnCS FIGURE 8. SINAD va INPUT FREQUENCY CHARACTERISnCS ~ a: "" ./ ~ ~COND HARMONIC ::Ii 1\ 25 20 I ~ iii ~,. 10-' / /' V / iii" I 10"7 t;: ~ a: , ) 10" a: V 5!a: w 10-' / CLOCK FREQUENCY: 500MHz INPUT FREQUENCY: 126.001 MHz FULL SCALE 16 LSB OR MORE ERROR 10.10 450 10.10 500 550 CLK FREQUENCY (MHz) 800 FIGURE 10. ERROR RATE va CONVERSION FREQUENCY CHARACTERISTICS 104 iii" 60 CLK DUTY CYCLE (%) FIGURE 11. ERROR RATE va CLOCK DUTY CYCLE CHARACTERISTICS INPUT FREQUENCY. CLOCK FREQUENCYI 4 + 1kHz FULL SCALE INPUT I I CLOCK FREQUENCY 500MHz 560MHz 450MHz 10" t;: 10" w ~ 0 10-' a: ~ 10.7 a: w 10" 10" 10.10 012345678 12 1. 24 THRESHOLD LEVEL (LSB) 32 FIGURE 12. ERROR RATE va THRESHOLD LEVEL CHARACTERISTICS 6-59 100 HI1276 Pin Descriptions PIN NUMBER SYMBOL 1 llNV 110 STANDARD VOLTAGE lEVEL I ECl DGND1 51 43 37 52 MINV DESCRIPTION EQUIVALENT CIRCUIT Polarity selection for LSBs (refer to the AID Output Code Table.) Pulled low when left open. ~, 61 R ~~ R UNVG) OR MlNV 37 42 48 R V •~~ - Polarity selection for MSB (refer to the AID Output Code Table). Pulled low when left open. 1 3V •

B:ON 000···00 TO 111···10 FIGURE 3. INTEGRAL AND DIFFERENTIAL UNEARITY ERROR TEST CIRCUIT 6·62 . ~OV \ HI1276 Test Circuits (Continued) -2V -w -5.2V FIGURE 4. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT eLK Hn2711 8 LOGIe ANALVZER VIiI--"""">II~--- 1024 SAMPLES eLK Aperture jitter Is defined as follows: 4U 256 TAJ = 01 4t = 0/(2 x21tf) FIGURE5A. FIGURE SB. APERTURE JmER TEST METHOD Where 0 (unit: LSB) Is the deviation of the output codes when the Input frequency Is exactly the same as the clock and is sampled at the largest slew rate point FIGURE 5. SAMPUNG DELAY AND APERTURE JmER TEST CIRCUIT HI1386 a-Bit, 75MSPS Flash AID Converter December 1993. Features Description • Differential Unearlty Error ±D.5 LSB or Less The H11386 is a 8-bit high-speed flash analog-te-digital converter Ie capable of digitizing analog signals at a maximum rate of 75MSPS. The digital 1/0 levels of this ND converter are compatible with EeL 100Kl1 OKHl1 OK. • Integral Unearlty Error ±D.5 LSB or Less • Bullt·ln Integral Unearlty Compensation Circuit • High-Speed OperaUon with Maximum Conversion Rate of 75MSPS (Min.) • Low Input Capacitance 17pF (Typ.) The HI1386 is available in the commercial and industrial temperature range and is supplied in 28 lead plastic DIP and 44 lead ceramic Lee packages. • Wide Analog Input Bandwidth 150MHz (Min. for Full Scale Input) Ordering Information • Single Power Supply -5.2V PART NUMBER • Low Power Consumption 580mW (Typ.) TEMPERATURE RANGE PACKAGE • Low Error Rate • Operable at 50% Clock Duty Cycle • Capable of Driving 50n Loads HI1386JCP ·25°C Ie! +75°C 28 Lead Plaslic DIP HI1386AIL ·2500 10 +10ooe 44 Lead Lee • Evaluation Board Available Applications • Video Digitizing • HDTV (High Definition TV) • Radar Systems • Communication Systems • Direct RF Down-Conversion • Digital Oscilloscopes Pinouts HII386 (PDlP) TOP VIEW H11386 (LCC) TOP VIEW CAUTION: Thase davie.. are eenaltlve 10 electroeta1lc discharge. Users should follow proper I.C. Handling Procedures. Copyrlght@Harrls Corporation 1993 6·64 File Number 3583.1 HI1386 Functional Block Diagram MINY R1 COMPARATOR D7(MSB) D6 os D4 OUTPUT D3 D2 R2 ENCODE I--+~rr""" lOGIC 01 DO (lSB) R3 ClK CLX ~---1rc;"~' ~----~-----r--------~ UNY 6-65 Specifications HI1386 Absolute Maximum Ratings TA = +25"C Thermal Information Supply Voltage (AVEE , DVEE) .................... -7V to +O.5V Analog Input Voltage (VIN) ••••••••••••••••••••• -2.7V to +O.5V Reference Input Voltage VAT' VRBo VRM ............................. -2.7V to +0.5\1 IVAT -VRBI .•••••••.•..••••••••.••••••••••••••••••• 2.5V Digitall~ Voltage ClK, ClK, MINV, llNV ....................... -4V to +O.5V IClK-ClKi ••••••••••••••••••••••••••••••••••••••• 2.7V VRM Pin input Current (IVRM) .•••••••••••••••••• -3mA to +3mA Digital Output Current (100 to ID7) ••••••••••••••• -30mA to OmA Storage Temperature Range (TSTG)' ••••••••••• -65°C to +150°C Lead Temperature (Soldering lOs) ••••••••••..•.•••••• +300"C Thermal Resistance 9JA 9JC HII386JCP ••••••••••••• • • • • • • ••• • SSOCIW HII386All........................ 45"CIW 11"C1W Maximum Power Dissipation .......................... 1.17W Maximum Junction TemperabJre HI1386All ••••••••••••••••••••••••••••••••••••. +1750 C HI1386JCP •••••••••••.•••••••••••.•.•••••.•••• +15O"C Operating Temperature (Note 4) HII386JCP (TAl ........................... -20"C to +750 C HII386All (Tc) .......................... -2O"C to +1 OO"C CAUTION: Stresses abo"" those Ilslsd In "Abso/uls Maximum Ratings" may cause permanent damage to the dav/cB. This is a stress only rating and operatiDn of the dellice at these or any other conditions above those indicated in the operational sections of this spac/flcatJDn Is not impHed. . Operating Conditions Supply Voltage AVEE, DVEE .............................. -5.5V to -4.95V AVEE-DVEE .............................. -O.05V to O.05V AGND-DGND ............................ -0.05V to O.05V Reference Input Voltage VAT ...................................... -a.1VtoO.1V VRB •••••••.••.•.•••••••••••••••••••••••• -2.2V to -1.8V Electrical SpeCifications Analog Input Voltage, VIN .........................VRB to VAT .Pulse Width of Ciock TPWt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.ens Min. Tpwo ••••• : •••••••••••••••••••••••••••••••••• 6.6ns Min. TA = +25"C, AVEE = DVEE = -5.2V, VAT = OV, VRB = -2V (Note I) PARAMETER TEST CONDITIONS I MIN TYP MAX I UNrr SYSTEM PERFORMANCE Resolution Integral linearity Error, (INl) Fc=75MHz Differential linearity Error, (DNL) Fc=75MHz 8 8 8 Bits - to.3 to.5 LSB to.3 to.5 LSB - 49 - dB 41 - dB - 1009 DYNAMIC CHARACTERISTICS Signal to Noise Ratio (SINAD) RMSSignai RMS Noise + Distortion Input = 1MHz, Full Scale Fc=75MHz Error Rate Input = 18.749MHz, Full Scale Error> 16 lSB, Fc = 75MHz Differential Gain Error, DG Differential Phase Error, DP NTSC 40IRE Mod. Ramp, Fc =75MSPS Maximum Conversion Rate, Fc Error Rate of 1009 TPS (Note 2) = Input= 18.75MHz, Full Scale Fc=75MHz - 75 1.0 0.5 - - Aperture Jitter, TAJ - 10 Sampling Delay, T os - 3.0 - - TPS (Note 2) % Degree MSPS ps ns ANALOG INPUT Input Bandwidth VIN = 2Vp.p , Input frequency at -3dB Analog Input Capacitance, CIN VIN = IV + 0.07VRMS - Analog Input Resistance, RIN Input Bias Current, liN 150 VIN =-IV - MHz 17 - pF 390 - kn - - 200 JIA 75 110 155 n REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT VAT 8 18 32 mV EoB VRB 0 10 24 mV 6-66 Specifications HI1386 Electrical Specifications TA =+25"<:, AVEE =DVEE =-5.2V, VAT =OV, VRB =-2V (Note 1) (Continued) MIN TYP Logic H Level, VIH -1.13 - - Logic L Level, VIL PARAMETER TEST CONDITIONS MAX UNIT DIGITAL INPUTS Logic H Current, 'IH -0.8V is Applied to Input 0 Logic L Current, 'lL -1.6V Is Applied to Input -50 Input Capacitance - V - -1.50 V - 50 50 IlA IlA - pF - 7 - DIGITAL OUTPUTS Logic H Level, VOH RL = 6200 to DVEE -1.03 Logic L Level, VOL RL = 6200 to DVEE - - V - -1.62 V - ns TIMING CHARACTERISTICS H Pulse Width of Clock, TPW1 6.6 L Pulse Width of Clock, Tpwo 6.6 - ns Output Rise Time, TR RL = 6200 to DVEE , 20% to 80% - 0.9 Output Fall Time, TF RL = 6200 to DVEE , 20% to 80% - 2.1 - ns 4.0 6.5 9.0 ns -150 -104 - - 580 Output Delay, Too ns POWER SUPPLY CHARACTERISTICS Supply Current, lEE Power Consumption, Po Note 3 - rnA mW NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. (VRT-VRSI2 3. Po = 'EE·VEE+-"""""R,----REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram ! I I FfGURE 1. 6-67 HI1386 Pin Descriptions and VO Pin Equivalent Circuit PIN NUMBER DIP LCC 19,21, 23,25 31,33, 18,26, 28 27,28, 40,41, STANDARD VOLTAGE LEVEL DESCRIPOON SYMBOL I/O AGND - OV Analog GND. Used as GND for Input buffers and latches of comparators. Isolated from DGND, DGND1, and DGND2. AVEE - -5.2V Analog VEE -5.2V (Typ.). InternalIy connected to DVEE (Resislance: 4n to 6(1). Bypass with 0.1jIF to AGND. I Eel 35,aT EQUIVALENT CIRCUIT 44 16 23 elK 15 22 elK elK Input DONO, DOND1 O...J p~ R R H. ~ ~~ R R eLK CLK A DVEE ~ ~~ R ~R ~-a Input complementary to elK. When open pulled down to-~ Device is operable without elK input, but use of c~lementary inputs of elK and LK is recommended to obtain stable high speed operation. .J ~ f ~ ~ f O...J 3,12 - DGND - OV Digital GND (used for internal circuits and output transistors). - 5,19 DGND1 - OV Digital GND (used for internal circuits and output transistors). - 6,16 DGND2 - OV Digital GND (used for output buffers). 2,13 4,20 DVEE - -5.2V Digital VEE' Internally connected to AV EE (resistance: 4n to 611). Bypass with 0.111F to DGND 4 8 DO 0 Eel DOND 5 9 6 10 02 7 11 03 8 12 D4 9 13 05 10 14 06 11 15 07 ~~ Lo 01 Fi ~ lSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required. A~

c( -2V VRT Analog input pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions. · • COMPARATOR 255 Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically OV. HI1386 AID OUTPUT CODE TABLE MINV1 UNV1 V1N(Note 1) STEP OV 0 1 -1V I 07 DO ,." 000·····00 000·····00 000·····01 ··· 127 128 011 ••••• 11 254 255 111·····10 111· .... 11 -2V NOTE: 100·····00 ·· · 111·····11 0 1 I 07 1 0 DO 07 I 0 0 DO 011 ••••• 11 011 ••••• 11 100· ... ···00 100 .... ·00 .. 100· .... 01 ·· · ··· 011 .... ~ 10 011 .... ·11 011 •••• '11 I DO 011 ••• "10 111 .... ·11 111 .... ·11 111 ••••• 10 111· .... 11 011 ••••• 11 100 ..... 01 100· .... 00 100· .... 00 000 ·····01 000···· -00 000····· 00 · · · 000·····00 ··· 111·····11 000· .... ·00 07 ·· · ··· 100·····00 1. V RT =OV,VRB =-2V Test Circuits FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT OUT 00000000 TO 11111110 FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT FIGURE 4. INTEGRAL AND DIFFERENTIAL UNEARITY ER· ROR TEST CIRCUIT 6·70 HI1386 Test Circuits (Continued) -2V FIGURE5A. FIGURE5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS CLK HI1386 8 LOGIC ANALVZER VIN ----,'iF---- 1024 SAMPLES eLK Aperture jitter is defined as follows: Au 256 T AJ = 0/ At = 0/ ("'2 x 2ltf) FIGURE6A. FIGURE 6B. APERTURE JmER TEST METHOD Where 0 (unit: LSS) Is the deviation of the output codes when the input frequency Is exacUy the same as the clock and Is sampled at the largest slew rate point. FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 6-71 HI1396 a-Bit, 125MSPS Flash AID Converter December 1993 Features Description • • • • The HI1396 is an 8-bit ultra high speed flash analog-to-digilsi converter IC capable of digitizing analog signals at the maximum rate of 125MSPS. The digital 110 levels of the converter are compatible with ECl 1OOKl1 OKHl1 OK. Differential Unearlty Error ±O.5 LSB (Typ.) or Less Integral Unearlty Error ±O.5 LSB (Typ.) or Less Built-In Integral Unearlty Compensation Circuit Ultra High Speed Operation with Maximum Conversion Rate of 125MSPS (Min.) • Low Input Capacitance 18pF (Typ.) • Wide Analog Input Bandwidth 200MHz (Min. for FullScale Input) • Single Power Supply -5.2V • Low Power Consumption 870mW (Typ.) • • • • The HI1396 is available in the Commercial and Industrial te'mperature ranges and is supplied in a 68 lead ceramic lCC, 42 lead ceramic DIP and plastiC DIP packages. Ordering Information Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50n Loads Evsluatlon Board Avsilable Applications TEMPERATURE RANGE PACKAGE H11396JCJ ·20"C to +75°C 42 Lead Ceramic DIP HI1396AIL ·200 C to +1 OO"C 68 Lead Ceramic LCC HI1396JCP ·20"C to +75OC 42 Lead Plastic DIP PART NUMBER • Video Digitizing • Communication Systems • Radar Systems • HDTV (High DeflnHlon TV) • Direct RF Down-Convarsion • DlgHaI Oscilloscopes Pinouts H11396 (CDIP, PDIP) HI1396 (LCC) TOP VIEW TOP VIEW a a a a Z Z sZ Z UUUUUCI iSCI a:CI iSClUUUUU ZZZZZC>C>C>CZZZZZ DGND2 (LSB) DO 01 D2 D3 D4 D6 DB (MSB)07 DGND2 DGND2 Ne NC AVEE AVEE NC VAT NC AVEE Ne NC Ne UNV Ne DVEE Ne DGND1 DGND2 Ne CAUTION: These devices are sensHIve to electrostatic dlacharga. Users should follow proper I.C. Handling Procedures. Copyright@HarrisCorporation 1993 6·72 Ne AVEE AVEE Ne VAS Ne NC Ne eLK C1:K 32 31 30 211 28 27 File Number Ne MINV Ne DVEE Ne Ne Ne 3576.1 HI1396 Functional Block Diagram MINV R1 COMPARATOR D7(MSB) D8 os D4 OUTPUT D3 D2 R2 ENCODE LOGIC t--+.......:r, D1 DO (LSB) UNV 6-73 Specifications HI1396 Absolute Maximum Ratings TA = +250 C Thermal Information Supply Voltage (AVEE , DVEE) •••••••••••••••••••••••••••• -7V Analog Input Voltage (VIN ) ..................... -2.7V to +(105V Reference Input Voltage VRT, VRBo VRM ............................. -2.7V to +O.5V IVRTVRBI ......................................... 2.5V Digitall~ Voltage ClK, CO<, MINV, LlNV ....................... -4V to +O.5V IClK-CiJ(1 ••••.••••••••• ; •••••••••••••••••••••••• 2.7V VRM Pin Input Current (I VRM) •••••••••••••••.••• -3mA to +3mA Digital Output Current (IDO to 107) •••••••••••••.• -SOmA to OmA Storage Temperature Range (TSTG) •••••••••••• -6500 to +15O"C lead Temperature (Soldering lOs) •••••••••••••••••••• +3000C Thermal Resistance 9JA HI1396JCP ••••••••••••••••••••••• 52°C/W l2OC1W HI1396JCJ •••••••••••••••••••••••• 360CfW 1O"C1W HII396All •••••••••••••••••••••••• 390CfW Maximum' Power Dissipation Ceramic Package ................................ 1.61W Plastic Package •••••••• '.' •••••••••••••••••••••••• 1.44W Operating Temperature (Note 4) HI1396JC~ TA............................ -20"C to +75°C HII396JCJ, TA............................ -20"C to +75°C H11396All, Te ........................... -20"C to +1000C Maximum Junction Temperature HI1396JCP ........ : ........................... +150oC H11396JCJ, H11396AIL ........................... +1750 C CAUTION: Stresses ab01I8 these listed in "Abso/uts Maximum Ratings" may cause permsnent damage to ths davice. This is a stress only rating and operation of ths devies at thsse or any other conditions ab01I8 those Indicated in ths operational sections of this sp«:iflcation is not impHed. Operating Conditions (Note 1) Supply Voltage AVEE, DVEE •••.•••••••••.•.••.••..••••••• -5.5V to -4.95V AVEE-DVEE .............................. -D.05V to O.05V AGND-DGND ............................ -O.05V to O.05V Reference Input Voltage VRT ...................................... -D.1VtoO.1V· VRB ..................................... -2.2Vto-l.8V Electrical Specifications Analog Input Voltage, VIN ........................ ,VRB to VRT Pulse Width of Clock TPWI •••.••••••••••••••••••••••••••••••••••• 4.0ns Min. TPWO ....................................... 4.0ns Min. TA = +2500, AVEE = DVEE = -5.2V, VRT = OV, VRB = -2V (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNrr 8 - - Bits - - to.5 LSB - - to.8 LSB - - to.5 LSB - to.7 LSB MHz SYSTEM PERFORMANCE Resolution Integral linearity Error, (INl) H11396JCJ, HII396All Fe = 125MHz H11396JCP Differential linearity Error, (DNl) H11396JCJ, HII396All Fc = 125MHz H11396JCP ANALOG INPUT Input Bandwidth VIN=2Vp_p Analog Input CapaCitance, CIN VIN = IV +O.07VRMS Analog Input Resistance, RIN Input Bias Current, liN VIN =-1V 200 - - 18 50 190 - 20 130 400 IIA 75 110 155 0 pF kn REFERENCE INPUTS Reference Resistance, RREF Offset Voltage eaT VRT 8 19 32 mV EOB VRB 0 9 24 mV 6-74 Specifications HI1396 Electrical Specifications TA = +2500, AVEE = DVEE = -5.2V, VAT = OV, VRB = -2V (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.50 V 50 JlA PARAMETER DIGITAL INPUTS Logic H Current, IIH Input Connected to -0.8V 0 Logic L Current, IlL Input Connected to -1.6V 0 - 50 JlA - 7 - pF - V -1.62 V Input Capacitance DIGITAL OUTPUTS logic H Level, VOH At. = 50n to -2V -1.10 logic L Level, VOL RL = 50n to -2V - - TIMING CHARACTERISTICS Output Rise TIme, TR RL = 50n to -2V, 20% to 80% 0.5 0.9 1.2 ns Output Fall TIme, TF RL = 50n to -2V, 20% to 80% 0.5 1.0 1.3 ns Output Dalay, Too 3.0 3.6 4.2 ns H Pulse Width of Clock, TPWl 4.0 - L Pulse Width of Clock, Tpwo 4.0 - - ns 125 - MSPS - 1.5 - ns DYNAMIC CHARACTERISTICS Maximum Conversion Rate, Fe Error Rate 10"" TPS (Note 2) Aperture Jitter, TAl Sampling Delay, Tos 10 - ps ns Signal to Noise Ratio (SINAD) RMSSlgnal = RMS Noise + Distortion Input = 1MHz, Full Scale Fc= 125MHz - 46 Input = 31.5MHz, Full Scale Fc= 125MHz - 40 Error Rate Input = 31.249MHz, Full Scale Error> 16 LSB, Fc= 125MHz - - 10-9 Differential Gain Error, DG NTSC 40IRE Mod. Ramp, Fe = 125MSPS - 1.0 - % - 0.5 - Degree -230 -160 - rnA - 870 - mW Differential Phase Error, DP dB dB TPS (Note 2) POWER SUPPLY CHARACTERISTICS Supply Current, lEe Power Consumption Note 3 NOTES: 1. Electrical Specilications guaranteed within stated operating conditions. 4. TA specified in stili air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. 6-75 HI1396· Timing Diagram FIGURE 1. Pin Descriptions and VO Pin Equivalent Circuit PIN NUMBER DIP LCC SYMBOL IfO STANDARD VOLTAGE LEVEL 29,31, 49,51, AGND OV 33,35 53,55 - Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. 1,25, 26,38, AVEE - -5.2V 62,63, 39 ff1 Analog VEE -52V (Typ.). InternalIy connected to DVEE (Resislance: 40 to 60). Bypass with O.lI1F to AGND. 21 35 ClK I ECl 41,42, EQUIVALENT CIRCUIT ClKlnput DGND1 20 34 ClK DESCRIPTION ,,. ~ ~ t'" i" ~~ R R V R R elK m h=:..lo:: ~ DVEE i" R ~R o-J 6-76 ~~~ .) .) ~ Input complementary to ClK. When left open pulled down to -1.3V. Device is operable Without ClK Input, but use of co~ mentary Inputs of ClK and ClK is recommended to obtain slable high speed operation. HI1396 Pin Descriptions and va Pin Equivalent Circuit (Continued) PIN NUMBER UO DIP LCC SYMBOL 5,16 7,24 DGNDl 6,15 8,23 DGND2 4,17 5,30 DVEE - 7 14 DO 0 STANDARD VOLTAGE LEVEL EQUIVALENT CIRCUIT Digital GND for Internal circuits. OV Digital GND for output transistors. -5.2V Digital VEE. Internally connected to AVEE (resistance: 40 to SO). Bypass with O.lI1F to DGND ECl ~D2 8 15 01 9 lS D2 10 17 03 11 18 D4 12 19 05 13 20 OS 14 21 07 3 3 LlNV Fl ~ ..! MINV Data outputs. External pull-down resiStors are required. ¢ OV;: I I ECl Input pin for 07 (MSB) output palarity Inversion (see AID Output Code Table). Pulled low when left open. R II'R UNY OR MINY MSB of data outputs. External pull-down resistor Is required. Input pin for DO (LSB) to D6 output polarity inversion (see AID Output Code Table). Pulled low when left open. ECl II' 32 LSB of data outputs. External pull-down resistor is required. 4 DG~ 18 DESCRIPTION OV R ~1.3Y ~~ OVEE '" R ¢ ;J 30,34 50,54 VIN I VRT to V RB AGND t: YIN YiN 4 s-n ~l~~ Analog input pins. These two pins must be connected externally, since they are not Internally connected. HI1396 Pin Descriptions and VO Pin Equivalent Circuit (Continued) PIN NUMBER DIP LCC SYMBOL 110 STANDARD VOLTAGE LEVEL 23 39 VRB I -2V 32 52 VRM I VRF12 41 65 VRT '1 Reference voltage (bottom). Typically -2V. Bypass with a O.l"F and 10"F to AGNO. Reference voltage mid point. Can be used as a pin for Integral linearitY compensation. Reference voltage (top) typically OV. When a voltage different from AGNO is applied to this pin, bypass with a 0.1J'F and 10"F to AGNO. R COMPARATOR 1 OV I DESCRIPTION EQUIVALENT CIRCUIT R COMPARATOR 2 r R YRM ·• ~COMPARATOR 127 R2 o--¥Iv-+ R -COMPARATOR 128 R -COMPARATOR 128 R J~-'~· R • RI2 COMPARATOR 255 YRB 2,19, 22,24, 27,28, 36,37, 40,42 1,2,4, 6,9-13, 25-29, 31,33, 36-38, 40, NC R3 - - Unused pins. No internal connections have been made to lhasa pins. Connecting them to AGNO or OGNO on PC board is recornmended. 43-48, 56-61, 64,66, 68 AID OUTPUT CODE TABLE MINV 1, UNV 1 V1N(Note 1) STEP I DO 000·····00 OV -lV 07 1,0 0,1 07 I DO 0 1 000·····00 000·····01 100··· .. 00 100·····00 100····. 01 127 128 011·····11 100·····00 111·····11 000·····00 254 255 111·····10 111· ····11 111·····11 011·.·· ·10 011····~11 011 ••••• 11 -2V NOTE: 1. VRT=OV, VRB =-2V. ·· · ··· ·· · ··· 6-78 07 I 0,0 DO 07 I DO 011 ·····11 011 ••••• 11 011 •••• ·10 111·····11 111·····11 111 ••••• 10 111·····11 011·····11 100·····01 100·····00 100·····00 000····· 00 ·· · 000 ·····00 ··· · ·· ··· 100·····00 000·····01 000·· ••• 00 H11396 Test Circuits FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT HI20201 DG.OP FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT VIN OUT H11386 BUFFER t 8 elK (125MHz) CONTROLLER t---..I 00000000 TO 11111110 FIGURE 4. INTEGRAL AND DIFFERENTIAL UNEARITY ERROR TEST CIRCUIT 6-79 HI1396 Test Circuits (Continued) HI1386JCJIJCP -5.2V A lEE -5.2V F1GURE5A. FIGURE5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS /'\. /'\. /'\. /'\. - OV :rVV\T~::: CLK H11386 8 ~ LOGIC ANALVZER V~ ------~----~ :~:~O(LSB) 127 126 1024 SAMPLES 125 CLK Aperture jitter is defined as follows: .1.U 256 T AJ = 01 .1.1 = 0 / ( T X21tf) FIGURE6A. FIGURE 6B. APERTURE JITTER TEST METHOD Where 0 (unit: LSB) is the deviation of the output codes when the Input frequency is exactly the same as Ihe clock and Is sampled at the largest slew rate point. FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 6·80 HI-5700 a-Bit, 20MSPS Flash AID Converter December 1993 Features Description • 20MSPS with No Missing Codes The HI-5700 is a monolithic. 8 bit. CMOS Flash Analog-toDigital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 20MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5700 delivers ±C.5 LSB differential nonlinearity while consuming only 725mW (typical) at 20MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 9 bit resolution. • 18MHz Full Power Input Bandwidth • No Missing Codes Over Temperature • Sample and Hold Not Required • Single +5V Supply Voltage • CMOSITTL • Overflow Bit • Improved Replacement for MP7684 • Evaluation Board Available • 1883 Version Available Applications The HI-5700 is available in Commercial and Industrial temperature ranges and is supplied in 28 lead Plastic DIP and SOIC packages. Ordering Information • Video Digitizing PART NUMBER • Radar Systems TEMPERATURE RANGE PACKAGE • Medical Imaging HI3-570OJ-5 ooc to +700C 28 Lead Plastic DIP • Communication Systems H19P570OJ-5 O"C to +70"C 28 Lead SOIC • High Speed Data Acquisition Systems HI3-5700A-9 -4O"C to +85°C 28 Lead Plastic DIP H19P5700A-9 -400c to +85°C 28 Lead SOIC Pinout HI-57oo (PDIP, SOIC) TOP VIEW CAUTION: These devices are sensitive to electroatatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 6-81 File Number 3174.3 HI·5700 Functional Block Diagram ~ OVERFLOW (OVF) 1-f--I»--f2 COMPARATOR LATCHES AND ENCODER LOGIC r------I[>>---- VDD[] CLK~---"l L--------~~~---'2 GND~ 6-82 D7 (MSB) Specifications HI-S700 Absolute Maximum Ratings Thermal Information Supply Voltage, Vee to GND ••.•••••• (GND - 0.5) < Vee < +7.0V Analog and Reference Input Pins •••• (Vss - 0.5) < VINA < (Voo +O.5V) Digital 1/0 Pins ••••••••••••••• (GND - 0.5) < VIIO < (Vee +O.5V) Stoilige Tempelliture Range • • • • • • • • ••••••• -6500 to +15O"C Lead Temperature (Soldering, 10s) •••••••....••......• 300"C Thermal Resistance 9JA 9JC HI3-5700J-5, HI3-5700A-9 •••••.•• . • • 55"CIW HI9P5700J-5, H19P5700A-9 • • • • • • • • • • 75°CIW Maximum Power Dissipation +7O"C ••••••••••••••.••••• 1.05W Operating Temperature Range HI3-570OJ-5, HI9P5700J-5 ••••••.•••••••••••• O"C to +70"C HI3-57ooA-9, H19P57ooA-9 • • • • • • • • • • • • • •• -40"C to +9500 Junction Temperature ••••••••••••.••••••••.•••••••• +15O"C CAUTION: S/rtISSes abol/8 those NslBd In ths -Absolute Maximum Ratings" may causa permanent damage to the daviee. This is a s/rtlSS only raUng and opBraUon of the device at these or any other conditions above thoselnd/calBd In ths operaUon section of this specification Is not ImpUed. Electrical Specifications = = = = = AVee Voo +S.OV; VREF. +4.0V; VREF• GND AGND SO% Duty Cycle; CL 30pF; Unless Otherwise Specified. = =OV; Fs = Specified Clock Frequency at (NOTE 2) OOCto+70oC -400C to +8SOC +2SOC PARAMETER TEST CONDITION MIN TYP MAX MIN MAX UNITS SYSTEM PERFORMANCE Resolution 8 Bits 8 Integral Unearity Error (INL) (Best Fit Method) Fs = 1SMHz, fiN = DC Fs = 20M Hz, fiN = DC ±0.9 ±1.0 ±2.0 ±2.25 ±2.25 ±3.25 LSB LSB Differential Linearity Error (DNL) (Guaranteed No Missing Codas) Fs = lSMHz, fiN = DC Fs= 20MHz, fiN DC ±0.4 ±0.5 ±0.9 ±0.9 ±1.0 ±1.0 LSB LSB f2 ±5.0 ±5.0 ±8.0 ±8.0 ±9.S ±9.S LSB LSB we/) ±O.S ±0.6 ±4.S ±4.S ±8.0 ±8.0 LSB LSB Offset Error (VOS) Full Scale Error (FSE) = Fs = 15MHz, fiN =DC Fs =20MHz, fiN =DC Fs= 1SMHz, fiN = DC Fs 20MHz, fiN DC = = No MIssing Codes 20 Minimum Conversion Rate No Missing Codes (Note 2) Full Power Input Bandwidth Fs =20MHz Signal to Noise Ratio (SNR) RMS Signal = RMSNolse Fs = 1SMHz, fiN = 100kHz Fs = 1SMHz, fiN = 3.58MHz Fs 1SMHz, fiN 4.43MHz Fs = 20MHz, fiN 100kHz Fs 2OMHz, fiN = 3.58MHz Fs = 20MHz, fiN = 4.43MHz Signal te Noise Ratio (SINAD) RMS Signal = RMS Noise + Distortion Total Harmonic Distortion Differential Gain Differential Phase Error 25 MSPS 20 0.125 0.125 MSPS 18 MHz 46.5 44.0 43.4 45.9 42.0 41.6 dB dB dB dB dB dB Fs 15MHz, fiN = 100kHz Fs = 15MHz, fiN = 3.58MHz Fa 15MHz, fiN = 4.43MHz Fa 2OMHz, fiN = 100kHz Fs - 20MHz, fiN - 3.S8MHz Fs = 20M Hz, fiN = 4.43MHz 43.4 34.3 32.3 42.3 35.2 32.8 dB dB dB dB dB dB Fa = 15MHz, fiN = 100kHz Fs = 15MHz, fiN" 3.58MHz Fa = 15MHz, fiN 4.43MHz Fa 2OMHz, fiN 100kHz Fs = 2OMHz, fiN 3.58MHz Fs 20MHz, fiN 4.43MHz -46.9 -34.8 -32.8 -46.6 -36.6 -33.5 dBc dBc dBc dBc dBc dBc 3.5 0/0 0.9 Degree = = >ct Z...I 011. o ~ DYNAMIC CHARACTERISTICS Maximum Conversion Rate ~ D::x: = = = = = = = = = = = Fa =14MHz, fiN =3.58MHz Fa =14MHz, fiN =3.58MHz 6-83 Specifications HI-S700 Electrical SpecificatIons AVOr:) = Voo =+5.ov; VREF+ = +4.0V; VREF. = GND = AGND = OV; Fs = Specified Clock Frequency at 50% Duty Cycle; Cl = 30pF; Unless Otherwise Specified. (Continued) (NOTE 2) oOCto +700C -400c to +85°C +25OC PARAMETER TEST CONDmON MIN TYP 4 10 60 ±0.01 MAX MIN MAX UNITS ±1.0 MO pF j1A ANALOG INPUTS Analog Input Resistance,. ~N Analog Input Capacitance, CIN Analog Input Bias Current, IB VIN =4V VIN=OV VIN =OV,4V ±1.0 REFERENCE INPUTS Total Reference Resistance, ~ 250 Reference Resistance Tempco, Tc 330 235 0 nrc +0.31 DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low VoHage, Vil Input logic High Current, IIH Input Logic Low Current, III Input CapaCitance, CIN 2.0 2.0 0.8 1.0 1.0 VIN =5V VIN=OV 0.8 1.0 1.0 7 V V j1A j1A pF DIGITAL OUTPUTS Output Logic Sink Current, 10l Output Logic Source Current, 10H Output Leakage, loz Output Capacltance, COUT 5.0 rnA rnA j1A pF 6 ns 3.2 -3.2 3.2 -3.2 Vo=0.4V Vo =4.5V CE2 = OV, Vo = OV, 5V CE2 .. 0V ±1.0 ±1.0 TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data OUtput Enable Time, leN Data OUtput Disable Time, loiS Data Output Delay, 100 Data OUtput Hold, 1M ps 30 18 15 20 20 25 20 25 Voo=5V±10% Voo 5V±10% = ±0.1 ±0.1 ±2.75 ±2.75 ±5.0 ±5.0 LSB LSB Fs =20MHz 145 180 190 mA 10 30 25 30 5 ns lIS ns lIS POWER SUPPLY REJECTION Offset Error PSRR, 11VOS Gain Error PSRR,IlFSE POWER SUPPLY CURRENT Supply Current, 100 NOTES: 1. Dissipation rating assumes device is mountad with all leads soldered to printed circuil board. 2. Parameter guaranteed by design or characterization and nol production tested. 6-84 HI-S700 Timing Waveforms ENCODER DATA IS LATCHED INTO THE OUTPUT REGISTERS COMPARATOR DATA IS LATCHED CLOCK INPUT SAMPLE N-2 , AUTO , BALANCE SAMPLE N-1 , AUTO \ BALANCE SAMPLE / ' SAMPLE ;(AMPLE _ - - N 'AUTO' N+1 , AUTO \ N+2 , BALANCE BALANCE tAB ANALOG~ INPUT ............... _ ---I f4- tAP ________ ------------ tAJ~ X ,,__DA:__rA_N_-3_-.JX DATA"""" OUTPUT . / ' ._ _D_Ii._rA_N-_4_J f4- DATA N-2 X tH ___ toD 11__ ---I DATA N-1 1-X~-DA:-:r,-A-N- FIGURE 1_ INPUT-TO-OUTPUT TIMING CD-~---~----~ _lots __ tEN ~1 I tOlS I~ DO - D7 DATA" HIGH / DATA " HIGH / DATA _ _- , / IMPEDANCE"""'_ _ _-'~ I M P E D A N C " ' " " I _ - - - - - - - - - - - - - - - - OVF DATA " HIGH I D,A':r,'A _ _ _ _ _ _ _ _ _ _ _ _~~IMPEDANCE'''I_--"-"--------------- FIGURE 2. OUTPUT ENABLE TIMING 6-85 HI-S700 Typical Performance Curves I 8 VDO·5V.~~-4V TA~21'C' VOO-IV. "AEF+=4V s·1 !MHz, n=1 ~kHz 7 1==== ~ r-- r--. FS-15M i ........ Fs" 2OMHZ, fln 10011 ~ !z FS-~ F==: ! Fs 20M II, fin - 3.81 MHz ~ 11.522.533.544.1 060 I -40 -20 0 +20 +40 INPUT FREQuENCY - ... (MHz) '\ r-.. '" &0 FIGURE 4. EFFECTIVE NUMBER OF BITS vs TEMPERATURE -- 48 44 42 40 3, -30 VDD - IV. "IE.... _ 4V 48 - f-- -34 "- ........... __~ Fs-15MHz,fln- ookHz B. Fs -15MHz, fln _ 4.43MHz 34 -CO Fs. 2OMHz, fln • 100kHz -0. Fs _ 2OIIIb, fln _ 4.43M 32 30 ~ -38 i-40 \. 0 +2D +4D / -45 -10 -zo / -45 28 I-=- 060 +60 +80 +100 +120 +140 ~ ;;...0"" - -40 -zo 0 4 fln_100kHz Fs-20MHz 2.6 0.76 ",. ~ 2 ./ 18 !I 0.5 -'" ~ 1.5 I-- ....- 0.5 o -20 0 A- II-- +60 +80 +100 +120 +140 +20 +40 -- :::::: , - Fs-20MHz ......: FsL5M~ 0.25 FS-115MHf -40 .- V.x: .. 5V!VAEF!. 4~ fin _ 100kllz - -vo!, .. sJ. VIEJ+ - 4 -10 +20 +40 -- I""'" FIGURE 6. TOTAL HARMONIC DISTORTION va TEMPERATURE AGURE5. SHRvsTEMPERATURE 3 7 TEMPERATURE ("e) TEMPERATURE ("C) 3.5 ~ D. Fs" 20MHz, fin _ 4.43MHz -44 R- ~io"'"e. A- s.1 MHz, fin _100kHz Fs" 15MHz, fin .. 4.43MHz r-a. I-c. Fs" 20MHz, fin .. 100kHz -42 \. "' "-.... D. ~ -35 c. 28 -40 B. VDD - 6V. VAEF+" 4V -32 B. • -10 +80 +100 +120 +140 +60 TEMPERATURE ("C) FIGURE 3. EFFEcnYE NUMBER OF BITS VI fiN !I "- 4 00.5 18. ~ ...... 5 - f - - Fs -15MHz, fin .. 3.85MHz 4 '1 r--.. """'- I I +60 +80 +100 +120 +140 o -10 -40 -20 0 +20 +40 +10 +80 +100 +120 +140 TEMPERATURE <"e) TEMPERATURE ("C) FIGURE 7. INL va TEMPERATURE FIGURE 6-86 a. DNL V8 TEMPERATURE HI-5700 Typical Performance Curves (Continued) 8 2 vri • 5V,' VREF~ .4V: 7 ~ 6 ~ Voo'·6V, AEF:.4V 1.5 FS='20MHl FS=15M~ ~ ...... 4 ~ \ i'- ~ i' 0.5 ~ I- ......... Fs-2OMI z ........... ......;;", ...... ~ 3 o 2 -60 -40 -20 0 +20 +40 +60 I -60 +80 +100 +120 +140 -40 0 -20 TEMPERATURE ('Ie) eu 25 -- toD L. ~ """"" 16 +60 +60 +100 +120 +140 Voo=5V, VREF+a4V AD.~PF 20 +40 FIGURE 10. FULL SCALE ERROR vs TEMPERATURE V'.5V';VREF~.4\ 30 +20 TEMPERATURE ('Ie) FIGURE 9. OFFSET VOLTAGE va. TEMPERATURE 35 -~: FS-I'5M~Z ~ ~ - 0.5 ..- t: ~~ PS RVO PSRRF E tHOP -D.5 7 10 -60 -40 ·20 0 +20 +40 +60 -60 +60 +100 +120 +140 ~ 0 -20 FIGURE 11. OUTPUT DELAY va TEMPERATURE 200 180 170 160 ....... 180 170 _ 160 160 _ ~ ........... 160 ...... -c 140 E 130 ~ ......... 120 110 100 ""- ....... 110 80 -60 -40 ·20 0 -- +20 +40 Fs-20MHz~ -I- ~ ~ ~ ~~00~2O~4O FIGURE 12. POWER SUPPLY REJECTION vs TEMPERATURE VD = 5V, VREF+. 4V: 180 ~ TEMPERATURE ("C) TEMPERATURE ('Ie) F... 1MHz "'T"-4I I +60 +80 +100 +120 +140 111111111 , Vooa5V,VREF+=4V TA=25oe 140 L III 130 120 - 0 tAB -c 110 _. =iAB+is E 100 80 60 70 60 50 40 30 0.1 ~ ./ 0.50'" I 0.25% -~ 0.10% 11111 1111 I 1 10 100 eLOeKFREQUENeY(MH~ TEMPERATURE ('Ie) FIGURE 13. SUPPLY CURRENT va TEMPERATURE FIGURE 14. SUPPLY CURRENT vs CLOCK .. DUTY CYCLE 6-87 HI-5700 TABLE 1. PIN DESCRIPTION PIN' DESCRIPTION NAME The CMOS HI-5700 works by alternately switching between a "Sample" mode and an "Auto Balance" mode. Splitting up the comparison process in this CMOS technique offers a number of significant advantages. The offset voltage of each CMOS comparator is dynamically canceled with each conversion cycle such that offset voltage drift is virtually eliminated during operation. The block diagram and timing diagram illustrate how the HI-5700 CMOS flash converter operates. Clock Input 1 ClK 2 07 BI17, OUtput (MSB) 3 OS Bil6, OUtput 4 05 Bit 5, OUtput 5 D4 Bit 4, OUtput 6 1/.R 1/.th Point of Reference Ladder 7 Digital Power Supply 9 Vee GND 3/4R 3/.th Point of Reference Ladder 10 D3 Bil3, OUtput 11 D2 Bit 2, Output 12 01 13 DO Bit " OutpUI Bit 0, Output (LSB) 8 Ou1pu1 word, plus an additional comparator to detect an overflow condition. The input clock which controls the operation of the HI-5700 Is first split Into a non-inverting ,1 clock and an Inverting ,2 clock. These two clocks, in turn, synchronize all internal timing of analog switches and control logic within the converter. Digital Ground 14 OVF Overflow, Output 15 CE2 Tri-state Output Enable Input, Active High. (See Table 2) 16 CEl Trl-State Output Enable Input, Acijve Low. (See Table 2) 17 VREF + Reference Voltage Positive Input 18 AVoo Analog Power Supply, +5V 19 AGND Analog Ground 20 AGND Analog Ground 21 Analog Power Supply, +5V 22 AVoo 1/2R 23 AVoo Analog Power Supply, +5V 24 AGND Analog Ground 25 AGND Analog Ground In the "Auto Balance" mode (,1), all ,1 switches close and ,2 switches open. The Ou1put of each comparator is momentarily tied to its own input, self-biasing the comparator midway between GND and Voo and presenting a low impedance to a small input capacitor. Each capacitor, in turn, is connected to a reference voltage tap from the resistor ladder. The Auto Balance mode quickly precharges all 256 input capaCitors between the self-bias voltage and each respective tap voltage. ,1 In the "Sample" mode (,2), all switches open and ~ switches close. This places each comparator in a sensitive high gain amplifier configuration. In this open loop state, the input impedance is very high and any small voltage shift at the, input will drive the output either high or low. The ~ state also switches each input capacitor from its reference tap to the input signal. This instantly transfers any voltage difference between the reference tap and input voltage to the comparator input. All 256 comparators are thus driven simultaneously to a defined logic state. For example, if the input voltage is at mid-scale, capacitors precharged near zero during will push comparator inputs higher than the self bias voltage at ,2; capacitors precharged near the reference voltage push the respective comparator inputs lower than the bias point. In general, all capacitors precharged by taps above the input voltage force a "low" voltage at comparator inputs; those precharged below the input voltage force "high" inputs at the comparators. 1/2 Point of Reference Ladder ,1 26 AVee Analog Power Supply, +5V 27 VREF - Reference Voltage Negative Input 28 VIN Analog Input ,1 Theory of Operation During the next Auto-Balancing state, comparator outpu1 data is latched into the encoder logic block and the first stage of encoding takes place. The following ,2 state completes the encoding process. The 8 data bits (plus overflow bit) are latched into the output flip-flops at the next falling clock edge. The Overflow bit is set if the input voltage exceeds VREF + - 0.5 LSB. The output bus ~ be either enabled or disabled according to the state of CEl and CE2 (See Table 2). When disabled, output bits assume a high impedance state. The HI-5700 is an 8 bit analog-to-digital converter based on a parallel CMOS "flash" architecture. This flash technique is an extremely fast method of AID conversion because all bit decisions are made simultaneously. In all, 256 comparators are used in the HI-5700: (28_1) comparators to encode the As shown in the timing diagram, the digital output word becomes valid after the second ,1 state. There is thus a one and a half cycle pipeline delay between input sample and digital output. "Data Output Delay" time indicates the slight time delay for data to become valid at the end of the ,1 state. TABLE 2. CHIP ENABLE TRUTH TABLE CEl CE2 0 1 Valid 1 1 Trl-State Valid 0 Trl-State Tri-State X OVF 00-07 Valid X's = Don t Care. 6-88 HI-S700 10~ CLOCK INPUT ANALOG SIGNAL INPUT soo D6 OS DIGITAL TO ANALOG D4 VDI) +5V +-----~,:0~~r----t:O.:O,~~~F--------~~ ANALOG 1/4R VDI)(+5V) TO ANALOG GND DIGITAL GROUND FIGURE 15. TEST CIRCUIT Applications Information Voltage Reference The reference voltage is applied across the resistor ladder between VREF + and VREF -. In most applications, VREF - is simply tied to analog ground such that the reference source drives VREF +. The reference must be capable of supplying enough current to drive the minimum ladder resistance of 23S0 over temperature. The HI-S700 is specified for a reference voltage of 4.011, but will operate with voltages as high as the Voo supply. In the case of 4.0V reference operation, the converter encodes the analog input into a binary output in LSB increments of (VREF+ - VRE d/2S6, or 1S.6mV. Reducing the reference voltage reduces the LSB size proportionately and thus increases linearity errors. The minimum practical reference voltage is about 2.SV. Because the reference voltage terminals are subjected to internal transient currents during conversion, it is important to drive the reference pins from a low impedance source and to decouple thoroughly. Again, ceramic and tantalum (0.01j.1F and 10j.1F) capacitors near the package pin are recommended. It is not necessary to decouple the '/4R, '/2 R, and 3/4R tap point pins for most applications. It is possible to elevate VREF- from ground if necessary. In this case, the VREF - pin must be driven from a low impedance reference capable of sinking the current through the resistor ladder. Careful decoupling is again recommended. Digital Control and Interface The HI-S700 provides a standard high speed interface to external CMOS and TTL logic families. Two chip enable inputs control the tri-state outputs of output bits DO through 07 and the Overflow (OVF) bit. As indicated in the Truth Table, all output bits are high impedance when CE2 is low, and output bits DO through 07 are independently controlled byCE1. Although the Digital Outputs are capable of handling typical data bus loading, the bus capacitance charge/discharge currents will produce supply and local group disturbances. Therefore, an external bus driver is recommended. Clock The clock should be properly terminated to digital ground near the clock input pin. Clock frequency defines the conversion frequency and controls the converter as described in the "Theory of Operation" section. The Auto Balance ,1 half cycle of the clock may be reduced to approximately 20ns; the Sample ,2 half cycle may be varied from a minimum of 2Sns to a maximum of 5J.ts. Signal Source A current pulse is present at the analog input (YIN) at the beginning of every sample and auto balance period. The transient current is due to comparator charging and switch feedthrough in the capacitor array. It varies with the amplitude of the analog input and the converter's sampling rate. The signal source must absorb these transients prior to the end of the sample period to ensure a valid signal for conversion. Suitable broad band amplifiers or buffers which exhibit low output impedance and high output drive include the HFA-OOOS, HA-S004, HA-SOO2, and HA-S003. 6-89 HI-5700 The signal source may drive abow or below the power supply rails, but should not exoeed O.SV beyond the rails or damage may occur. Input IIOltages of -c.SV to +O.S LSB are conV$rted to all zeroes; input IIOltages of VREF+ -O.S LSB to Voo +O.SV are converted to all ones with the Overflow bit set. Full Scale Offset Error Adjustment In applications where accuracy is of utmost importance, three adjustments can be made; i.e., offset, gain, and reference tap point trims. In general, offset and gain correction can be done in the preamp circuitry. Offset Adjustment Offset correction can be done in the preamp driving the conwrter by introducing a DC component to the input signal. An alternate method is to adjust VREI'" to produce the desired offset. It is adjusted such that the 0 to 1 code transition occurs at O.S LSB. Gain Adjustment In general, full scale error correction can be done in the preamp Circuitry by adjusting the gain of the op amp. An alternate method is to adjust the VREF+ IIOltage. The reference IIOltage is the ideal location. Quarter Point Adjustment not necessary to decouple the 1/4R, 1/2R, and 3/4R tap points in most applications. Power Supplies The HI-S700 operates nominally from SV supplies but will work from 3V to 6V. Power to the device is split such that analog and digital circuits within the HI-S700 are powered separately. The analog supply should be well regulated and 'clean" from significant noise, especially high frequency noise. The digital supply should match the analog supply within about O.SV and should be referenced externally to the analog supply at a single point. Analog and digital grounds should not be separated by more that O.SV. It is recommended that power supply decoupling capaCitors be placed as close to the supply pins as possible. A combination of O.OIJ,1F ceramic and 10J,1F tantalum capacitors is recommended for this purpose as shown in the test circuit. Reducing Power Consumption Power dissipation in the HI-S700 is reiated to clock frequency and clock duty cycle. For a fixed SO% clock duty cycle, power may be reduced by lowering the clock frequency. For a given conversion frequency, power may be reduced by decreasing the Auto-Balance (~1) portion of the clock duty cycle. This relationship is illustrated in the performance curws. The reference tap points are brought out for linearity adjustment or creating a nonlinear transfer function if desired. It is TABLE 3. CODE TABLE CODE DESCRIPTION INPUT VOLTAGE· VREF += 4.0V VREF-=O.OV BINARY OUTPUT CODE LSB MSB (V) DECIMAL COUNT OVF 07 D6 05 D4 D3 D2 01 Overflow (OVF) 4.000 511 1 1 1 1 1 1 1 1 1 Full Scale (FS) 3.9766 255 0 1 1 1 1 1 1 1 1 FS-1LSB 3.961 254 0 1 1 1 1 1 1 1 0 314FS 2.992 . 192 0 1 1 0 0 0 0 0 0 112 FS 1.992 128 0 1 0 0 0 0 0 0 0 1/4FS 0.992 64 0 0 1 0 0 0 0 0 0 1 LSB 0.0078 1 0 0 0 0 0 0 0 0 1 Zero 0 0 0 0 0 0 0 0 0 0 0 • The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage. 6-90 DO HI-5700 Glossary of Terms Aperture Delay: Aperture delay is the time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter: This is the RMS variation in the aperture delay due to variation of internal and ~ clock path delays and variation between the individual comparator switching times. ,1 Differential Unearlty Error (DNL): The differential linearity error is the difference in LSBs between the spacing of the measured midpoint of adjacent codes and the spacing of ideal midpoints of adjacent codes. The ideal spacing of each midpoint is 1.0 LSB. The range of values possible is from -1.0 LSB (which implies a missing code) to greater than +1.0 LSB. Full Power Input Bandwidth: Full power bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-topeak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Full Scale Error (FSE): Full Scale Error is the difference between the actual input voltage of the 254 to 255 code transition and the ideal value of VREF + - 1.5 LSB. This error is expressed in LSBs. = LSB: Least Significant Bit (VREF+ - VREF-)/256. All HI5700 specifications are given for a 15.6mV LSB size VREF+ =4.0V, VREF- =O.OV. Offset Error (VOS): Offset error is the difference between the actual input voltage of the 0 to 1 code transition and the ideal value of VREF- + 0.5 LSB, Vos Error is expressed in LSBs. Power Supply ReJection Ratio (PSRR): PSRR is expressed in LSBs and is the maximum shift in code transition points due to a power supply voltage shift This is measured at the 0 to 1 code transition point and the 254 to 255 code transition point with a power supply voltage shift from the nominal value of 5.0V. Signal to Noise Ratio (SNR): SNR is the ratio in dB of the RMS signal to RMS noise at speCified input and sampling frequencies. Signal to Noise and Distortion Ratio (SINAD): SINAO is the ratio in dB of the RMS signal to the RMS sum of the noise and harmonic distortion at specified input and sampling frequencies. Total Harmonic Distortion (THD): THO is the ratio in dBc of the RMS sum of the first five harmonic components to the RMS signal for a specified input and sampling frequency. Integral Unearlty Error (INL): The integral linearity error is the difference in LSBs between the measured code centers and the ideal code centers. The ideal code centers are calculated using a best fit line through the converter's transfer function. (/) a: I!:! a:X III(/) >cr: Z....I OIL. (.) ~ 6-91 HI-S700 Die Characteristics DIE DIMENSIONS: 154.3 x 173.2 x 19 ± 1mils METALLIZATION: Type: Si-AI Thickness: 11kA ± 1kA GLASSIVATION: Type: Si02 Thickness: akA ± 1kA TRANSISTOR COUNT: 8000 SUBSTRATE POTENTIAL (Powered Up): V+ Metallization Mask Layout H1-5700 ! I:i ......... d D4 AGNO 1/4R VDD AGNO AVDD VDD lIaR GINO AVDD GNO AGNO 3/4R AGNO D3 AVDD 6-92 HI-S701 6-Bit, 30MSPS Flash AID Converter December 1993 Features Description • 30 MSPS with No Missing Codes The HI-5701 is a monolithic. 6 bit. CMOS flash Analog-toDigital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 30MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5701 delivers ±O.7LSB differential nonlinearity while consuming only 250mW (typical) at 30MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 7 bit resolution. • 20MHz Full Pawsr Input Bandwidth • No Missing Codes Over Temperatura • Semple and Hold Not Required • Single +5V Supply Voltage • 300mW (Max) Pawsr Dissipation • CMOSITTL Compatible • Overflow Bit • Evaluation Board Available • 1883 Version Available Applications The HI-5701 is available in Commercial and Industrial temperature ranges and is supplied in 18 lead Plastic DIP and SOIC packages. Ordering Information • Video Digitizing PART NUMBER • Radar Systems TEMPERATURE RANGE PACKAGE • Communication Systems HI3-5701K-S O"C to +7O"C 18 Lead Plastic DIP • High Speed Oats Acquisition Systems HI9PS701 K-S O"C to +70"C 18 Lead SOIC (W) HI3-S7018-9 -4O"C to +8SoC 18 Lead Plastic DIP H19PS7018-9 -40°C to +85"C 18 Lead SOIC (W) Pinout H1-5701 (PDIP. SOIC) TOP VIEW CAUTION: These devices are eensltive to electrostalle discharge. Users should follow proper I.C. Handling Proceduree. Copyright @ Harris Corpora1lon 1993 6-93 File Number 2937.5 HI-5701 Functional Block Diagram 01 1211 02 1211 t---I::'-U OVERFLOW (OVF) COMPARATOR t-I--I::'--LJ D& (MSB) t-H-I::'-U D4 t-H-I::'-U D3 LATCHES AND 63T08 ENCODER LOGIC t-H-I::'-U D2 D1 t-H-I::'-·LJ L..---'".LJ CE2 CLOCK~~ 02 (SAMPLE) PHASE 1211 (AUTO BALANCE) ' .. . 00 (LSB) 6-94 o Veo o Vss Specifications HI·5701 Absolute Maximum Ratings Thermal Information Supply Voltage, Voo to Vss .••...••..• (Vss - 0.5) < Voo < +7.0V Analog and Reference Input Pins •••... (Vss - 0.5) < V,NA < (Voo +O.5V) Digital VO Pins ...•.........•.. (Vss - 0.5) < VIJO < (Voo +O.5V) Storage Temperature Range . . . . . . . . . . ..... -65OC to +15O"C Lead Temperature (Soldering lOs) .•.......••...•....• +300"C Thermal Resistance OJA H13-5701 •.•••••..••••••••.•••••••••.•.•••.•••• 95°CIW HI9P5701 .•......•.••...........•.............. 95"CIW Maximum Power Dissipation at +70"C .•.•.••.•..•••..• 635mW Operating Temperature Range HI3-5701-5 .....................••••....•• O"C to +70"C HI9P5701-9 ................•.•.••.••. -4O"C to +85°C Junction Temperature ••.••••••.•••••••••••••..••••• +15O"C CAUTION: Stresses abo... thOB" Ns19d in thB 'Absolu19 Maxhnum RaUngs' may caus" permanent damage to the dav/ce. ThIs Is 8 stress only rating and cpsraUon oIth" dwk:" at thes" or eny other conditions above /hos8 indica19d in the operation section of this specifICation Is not ImpNed. Electrical Specifications: voo = +5.0V; VREF+ = +4.0V; VREF• = Vss = GND; Fs = Specified Clock Frequency at 50% Duty Cycle; CL = 3OpF; Unless Otherwise Specified. (NOTE 2) OOCto+70oC -40°C to +8S"C +25OC PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS 6 - - 6 - Bits - to.5 ±1.25 - ±2.0 LSB ±1.5 - - LSB ±0.3 ±0.6 ±O.75 LSB - - ±2.0 - ±2.5 LSB - SYSTEM PERFORMANCE Resolution Integral Linearity Error (INL) (Best Fit Line) Fs =20MHz Fs =20MHz - Fs=3OMHz - ±0.7 Fs = 20MHz (Note 2) · ±0.5 - ±0.5 - Fs = 20MHz (Note 2) to.25 ±2.0 Fs =30MHz - ±0.25 - 30 40 - - Fs=3OMHz Differential Linearity Error (DNL) (Guaranteed No Missing Codes) Offset Error (VOS) (Adjustable to Zero) Fs =30MHz Full Scale Error (FSE) (Adjustable to Zero) LSB - LSB ±2.5 LSB - LSB 30 - MSPS 0.125 - 0.125 MSPS 20 - - - MHz · · · · dB dB · · - dB · dB · - dBc - - - DYNAMIC CHARACTERISTICS Maximum Conversion Rate No Missing Codes Minimum Conversion Rate No Missing Codes (Note 2) Full Power Input Bandwidth Fs=3OMHz - Signal to Noise Ratio (SNR) Fs = 1MHz, fiN = 100kHz · 36 · Fs = 3OMHz, fiN = 4MHz · 31 · Signal to Noise Ratio (SINAD) RMS Signal = RMS Noise + Distortion Fs= 1MHz, fiN = 100kHz 35 · Fs = 3OMHz, fiN = 4MHz · · 30 · Total Harmonic Distortion Fs = 1MHz, fiN = 100kHz · -44 Fs = 3OMHz, fiN = 4MHz - -38 - 2 - - 2 - - RMS Signal = RMSNoise Differential Gain Fs = 14.32MHz, fiN = 3.58MHz Differential Phase Fs = 14.32MHz, liN = 3.58MHz 6-95 - dBc % Degree Specifications HI·5701 Electrical Specifications: voo = +5.0V; VREF+ = +4.0V; VREF• = Vss = GND; Fs = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. (Continued) (NOTE 2) OOCto +70oC -40oC to +sSOC +25°C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS ANALOOINPUTS Analog Input Resistance, RIN VIN =4V Analog Input CapaCitance, CIN VIN=OV Analog Input Bias Current, IB VIN = OV,4V - - - - Mel 20 - pF 0.01 ±1.0 - ±1.0 jiA 250 370 235 - +0.266 - - O/"C 2.0 - V 30 REFERENCE INPUTS Total Reference Resistance, RL Reference Resistance Tempeo, Tc - el DIGITAL INPUTS Input Logic High Voltage, VIH 2.0 - Input Logic Low Voltage, VIL Input Logic High Current, IIH VIN =5V Input Logic Low Current, IlL VIN=OV - Input Capacitance, CIN 7 1.0 1.0 - - - V - 1.0 jiA 1.0 jiA - pF - rnA - ±1.0 jiA - pF - - ns - - ps 20 ns 20 ns - DIGITAL OUTPUTS Output Logic Sink Current, IOL Vo=0.4V 3.2 Output Logic Source Current, IOH Vo =4.5V -3.2 Output Leakage, IOFF CE2=OV Output Capacitance, COUl CE2=OV - - 3.2 - -3.2 - - ±1.0 5.0 - - 6 - 30 - 12 20 11 20 mA TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ - Data Output Enable Time, teN (Note 2) Data Output Disable Time, tolS (Note 2) Data Output Delay, too (Note 2) - 14 20 - 20 ns Data Output Hold, IH (Note 2) 5 10 - 5 - ns ±0.1 ±1.0 - ±1.5 LSB ±0.1 ±1.0 - ±1.5 LSB 50 60 - 75 mA POWER sUPPLY REJECTION Offset Error PSRR, AVOS Voo =5V±10% Gain Error PSRR, AFSE Voo= 5V± 10% - Fs=30MHz - POWER SUPPLY CURRENT Supply Current, 100 ~OTES: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 2. Parameter guaranteed by design or characterization and not production tested. 6-96 HI-S701 Timing Waveforms CLOCK INPUT PHASE-HIGH __ 02-.. 01_.I- - 01 ENCODED DATA IS LATCHED INTO THE OUTPUT REGISTERS COMPARATOR DATA IS LATCHED I 02 01 01 :, 02 ,, , SAMPLE N-2 CLOCK INPUT PHASE-LOW I AUTO \ BALANCE tAB SAMPLE N-1 Is I AUTO \ BALANCE X DATAN-4 ,: : -I:~------ --l f-IAJ =--I I-- --.......... DATA OUTPUT SAMPLE i SAMPLE _ - - f~, BALANCE AUTO \ N+1 I AUTO 1 N+2 I BALANCE, ,: ~ ANALOG INPUT SAMPLE N lAP X X DATAN-3 DATA N-2 ~! Itt --l 1-too --l ;,..1-__ X DATA N-1 X DATA N FIGURE 1. INPUT-TO-OUTPUT TIMING ~ CE2 ~ -1,, i ,i ! lOIS I---l DO-OS DATA '\.. I OVF , lEN 1---1 HIGH / IMPEDANCE' , \ I, ~ : teN ~ " IMPEDANCE' ' lOIS DATA I ___________________ - '" / DATA HIGH HIGH / / IMPEDANCE'~ DATA ____________________ __ DATA, FIGURE 2. OUTPUT ENABLE TIMING 6-97 HI-S701 Typical Performance Curves - 8 -r- - Ii 5 ~ ~ II: w t J - r- r- ~OMHz 8 I FS·~MHz irl ID I I 4 4.5 f I f I I 3 5 -40 -30 -20 -10 FIGURE 3. EFFECTIVE NUMBER OF BITS va fiN -34 VOO. SV, VREF+. 4V 38 -38 Fa. 30MHz, fIN • 4MHz ~ "". ..... -42 24 0 10 20 30 40 50 80 70 80 -- 80 """'" ~ Fa .. 1MHz, fill .1 ookHz r- .... 0 10 20 30 40 50 80 70 TEMPERATURE ("C) 80 90 FIGURE 6. TOTAL HARMONIC DiStoRTION va TEMPERATURE I f~.1.:ok~ I I Voo. sv, VRE~. 4V 1.S 0.75 Fs·30MHz dI !l 1 O.S Fa=30MHz 0.5 O.2S Fa· 1MHz o Fa • 3OMHz, fIN .. 4MHz --. -40 -30 -20 -10 fiN = 100kHz Voo. sv, VREF+" 4V ~ 80 -4S 80 FIGURE 5. SNR va TEMPERATURE I 70 I I I I I r- TEMPERATURE ("C) 2 80 Voo. SV, VREF+" 4V ""'" -40 -30 -20 -10 10 20 30 40 50 TEMPERATURE I"C) -38 ~ ..-. ~ ~ 28 28 ..... ..... ..... FS = 1MHz, fIN .. 100kHz 34 0 FIGURE 4. ENOB vs TEMPERATURE , 38 FS • 3OMHz, fill .. 4MHz VOO. SV, VREF+. 4V 1.5 2 2.5 3 3.5 INPUT FREQUENCY (flN!- MHz 0.5 I- jt.,.rT - 11;4 ~~Fct~_i4V o s I"'"" FS·4OMHz 4 3 jS.1tH -40 -30 -20 -10 0 10 20 30 40 50 80 Fa = 1MHz o 70 aD SID -40 -30 -20 -10 TEMPERATURE ("C) 0 10 20 30 40 50 80 70 80 90 TEMPERATURE (oC) FIGURE 8. DNL va TEMPERATURE FIGURE 7. INL va TEMPERATURE 6-98 HI-S701 Typical Performance Curves (Continued) ~. VDD" 5V 60 ± 10%, VREF+ .. 4V I I 0.5 VDD • 5V, VREF+. 4V 55 50 I I PSRRVOS 45 FS .. 30MHz :(' 40 !. jl35 PSRR FSE --- 30 25 -0.& "I 16 -1 -40 -30 -20 -10 0 ~ I 10 10 20 30 40 60 60 70 80 110 TEMPERATURE <"C) - FS·1MHz 20 -40 -20 o 20 40 60 TEMPERATURE ("C) 100 80 FIGURE 10. SUPPLY CURRENT VI TEMPERATURE FIGURE 9. POWER SUPPLY REJECTION VI TEMPERATURE 6.0 ",.1MHz 5.5 -............ 5.0 V II 5i +-4-++~*-~44+H~~L+O=~~ 4.5 w 4.0 ~ ~W ". 0 .. 10... 3.5 ---- 3.0 2.5 2.0 10 +-~~~~~----~~~~~----~~LLUL4 0.1 1 10 CLOCK FREQUENCY (MHz) 1.5 100 FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE 30 40 50 CLOCK FREQUENCY (MHz) FIGURE 12. EFFECTIVE NUMBER OF BITS VI CLOCK FREQUENCY 6-99 60 HI-S701 The CMOS HI-5701 works by alternately switching between a "Sample" mode and an "Auto Balance" mode. Splitting up the comparison process in this CMOS technique offers a number of significant advantages. The offset voltage of each CMOS comparator is dynamically canceled with each conversion cycle such that offset voltage drift Is virtually eliminated during operation. The block diagram and timing diagram illustrate how the HI-5701 CMOS flash converter operates. TABLE 1. PIN DESCRIPTION PIN' NAME DESCRIPTION 1 05 Bit 6, Output (MSB) 2 OVF Overftow. Output 3 Vss Olgltsl Ground 4 NC No Connection 5 CE2 Trl-Stste· OUtput Enable Input, ActIve High (See Table 2). 6 CEl Trl-Stste OUtput Enable Input, ActIve Low (See Table 2). 7 CLK Clock Input 8 PHASE Sample Clock Phase Control Input. When Phase is Low, Sample Unknown (,1) Occurs When the Clock is Low and Auto Balance (cjl2) Occurs When the Clock Is High (See Text). 9 VREF+ Reference Voltsge Positive Input 10 VREF- Reference Voltsge NegatiVe Input 11 VIN Analog Signal Input 12 Voo Power Supply, +5V 13 DO Bit 1, Output (LSB) 14 01 Bit 2, Output 15 02 Bit 3, Output 16 1/2R2 Reference Ladder Midpoint 17 03 Bit 4, Output 18 D4 Bit 5, Output The input clock which controls the operation of the HI-5701 is first split into a non-Inverting ,1 clock and an inverting cjl2 clock. These two clocks. in turn. synchronize all internal timing of analog switches and control logic within the converter. In the "Auto Balance" mode (,1), all ,1 switches close and ,2 switches open. The output of each comparator is momentarily tied to its own input, seH-biasing the comparator midway between Vss and Voo and presenting a low impedance to a small input capacitor. Each capacitor, in turn, is connected to a reference voltage tap from the resistor ladder. The Auto Balance mode quickly precharges all 64 input capacitors between the seH-bias voltage and each respective tap voltage. In the "Sample" mode (,2). all ,1 switches open and ,2 switches close. This places each comparator in a sensitive high gain amplifier configuration. In this open loop state, the input impedance is very high and any small voltage shift at the input will drive the output either high or low. The ,2 state also switches each input capacitor from its reference tap to the input signal. This instantly transfers any voltage difference between the reference tap and input voltage to the comparator input. All. 64 comparators are thus driven simultaneously to a defined logic state. For example, if the input voltage is at mid-scale, capacitors precharged near zero during ,1 will push comparator inputs higher than the seH bias voltage at ,2; capacitors precharged near the reference voltage push the respective comparator inputs lower than the bias point. In general, all capacitors precharged by taps above the input voltage force a "low" voltage at comparator inputs; those precharged below the input voltage force "high" inputs at the comparators. TABLE 2. CHIP ENABLE TRUTH TABLE DO-D5 CEl CE2 0 1 Valid 1 1 Trl-Stste Valid X 0 Tri-Stste Tri-Stste During the next ,1 state, comparator output data is latched into the encoder logic block and the first stage of encoding takes place. The following ,2 state completes the encoding process. The 6 data bits (plus overflow bit) are latched into the output flip-flops at the next falling clock edge. The Overflow bit is set if the input voltage exceeds VREF+ - '/2LSB. The output bus may be either enabled or disabled according to the state of CEl and CE2 (See Table 2). When disabled, output bits assume a high impedance state. OVF Valid X =Don't Care Theory of Operation The HI-5701 is a 6 bit analog-to-digital converter based on a parallel CMOS "flash" architecture. This flash technique is an extremely last method of AID conversion because all bit decisions are made simultaneously. In all, 64 comparators are used in the HI-5701; 63 comparators to encode the output word, plus an additional comparator to detect an overflow condition. As shown in the timing diagram, the digital output word becomes valid after the second ,1 state. There is thus a one and a haH cycle pipeline delay between input sample and digital output. "Data Output Delay" time indicates the slight time delay for data to become valid at the end of the ,1 state. Refer to the Glossary of Terms for other definitions. 6-100 HI-S701 os D4 OVF D3 Vss 112R CE2 01 DO CE1 Voo DATA OUPUT NC D2 0.01 I1F CLOCK INPUT CLK +8Vto+12V PHASE +4V ANALOG SIGNAL INPUT VIN VREf. VREF+ 10l1F +5V T T FIGURE 13. TEST CIRCUrr Applications Information are high impedance when CE2 is low, and output bits DO through 05 are independently controlled by m. Voltage Reference The reference voltage is applied across the resistor ladder at the input of the converter, between VREF+ and VREF-' In most applications, V REF - is simply tied to analog ground such that the reference source drives V REF +. The reference must be capable of supplying enough current to drive the minimum ladder resistance of 2350 over temperature. The HI-5701 is specified for a reference voltage of 4.0V, but will operate with voltages as high as the Voo supply. In the case of 4.0V reference operation, the converter encodes the analog input into a binary output in LSB increments of (VREF + - VREF -)/64, or 62.5mV. Reducing the reference voltage reduces the LSB size proportionately and thus Increases linearity errors. The minimum practical reference voltage is about 2V. Because the reference voltage terminals are subjected to internal transient currents during conversion, it is important to drive the reference pins from a low Impedance source and to decouple thoroughly. Again, ceramic and tantalum (0.01I1F and 10l1F) capacitors near the package pin are recommended. It is not necessary to decouple the '/2 R tap point pin for most applications. It is possible to elevate VREF- from ground if necessary. In this case, the V REF - pin must be driven from a low impedance reference capable of sinking the current through the resistor ladder. Careful decoupling is again recommended. Digital Control and Interiace The HI-5701 provides a standard high speed interface to external CMOS and TTL logic families. Four digital inputs are provided to control the function of the converter. The clock and phase inputs control the sample and auto balance modes. The digital outputs change state on the clock phase which begins the sample mode. Two chip enable inputs control the tri-state outputs of output bits DO through 05 and the Overflow OVF bit. As indicated in Table 2, all output bits Although the Digital Outputs are capable of handling typical data bus loading, the bus capacitance charge/discharge currents will produce supply and local ground disturbances. Therefore, an external bus driver is recommended. Clock The clock should be properly terminated to digital ground near the clock input pin. Clock frequency defines the conversion frequency and controls the converter as described in the "Theory of Operation" section. The Auto Balance ~1 half cycle of the clock may be reduced to 16ns; the Sample ~2 half cycle may be varied from a minimum of 16ns to a maximum of 81lS. TABLE 3. PHASE CONTROL CLOCK PHASE 0 0 0 Sample Unknown (~2) 1 Auto Balance (.1) 1 0 1 Sample Unknown (.2) 1 INTERNAL GENERATION Auto Balance (.1) Gain and Offset Adjustment In applications Where accuracy is of utmost importance, three adjustments can be made; i.e., offset, gain, and midpoint trim. In general, offset and gain correction can be done in the preamp circuitry. Offset Adjustment The preferred offset correction method is to introduce a DC component to VIN of the converter. An alternate method is to adjust the VREF- input to produce the desired offset adjustment. The theoretical input voltage to produce the first transition is '/2 LSB. VIN (0 to 1 transition) 6-101 ='/2LSB ='/2(VREP64) =VREP128 HI-5701 Gain AdJustment In general, full scale error correction can be done in the preamp circuitry by adjusting the gain. of the op amp. An alternate method Is to adjust the VREF + input voltage. This adjustment is performed by setting VIN to the 63 to owrflow transition. The theoretical input voltage to produce the transition is 1/2 LSB less than VREF+ and is calculated as follows: The signal source must be capable of recovering fron1 the transient prior to the end of the sample period to ensure a valid signal for conversion. Suitable broad band amplifiers or buffers which exhibit low output Impedance and high output drive include the HFA- §: ;g !!l §; :c m:c 8 ~ :c Vss(3) CE2(5) CE1(6) is: ~ to) g w til C ... :I: e .tw 0: > 0- :c Ii. W 0: > 6-104 :c ~ N" :c Q Q > DATA ACQUISITIO_ 7 AID CONVERTERS - SUBRANGING PAGE AID CONVERTERS - SUBRANGING SELECTION GUIDE. . . • . . . • • . . . . . • • . . . • . . • • . • . . . • • . . • • . • . . . . • . . 7·2 AID CONVERTERS - SUBRANGING DATA SHEETS HI1175 8-BIt, 20MSPS Flash AID Converter ....•........•••.••••••...•.•••............... 7·3 HI1176 8-BIt, 20MSPS Rash AID Converter ............................................. . 7·12 H15800 12-BIt, 3MSPS Sampling AID Converter .••..•.•...•..••.••••......•.•..•.•.....•.. 7·23 HI·7153 8 Channel, 1D-Bit High Speed Sampling AID Converter ............................... . 7-37 NOTE: Bold 'TYPe Designates a New Product from Harris. 7·1 8-BIT SUBRANGING AID CONVERTER CONVERSION TYPE CONVERSION TIME (ns) BANDWIDTH (MHz) TECHNOLOGY RANGE MIN (V) INL (LSB) DNL (LSB) Parallel, Binary, 8-Bit Latch, Three-State Two-Step 50 18 CMOS 2 ±1.3 ±0.5 Low Power 60mW Typ at 20 MSPS Internal Reference HI1176JCQ Parallel, Binary, 8-Bit Latch, Three-State Two-Step 50 18 CMOS 2 ±1.3 ±0.5 Low Power 60mW Typ at 20 MSPS DC Restore Intemal Reference HI1179JCQ Parallel, Binary, 8-Bit Latch, Three-State Two-Step 30 60 CMOS 2 +1.3 -1.0 ±0.5 Low Power 80mW Typ at 35 MSPS DC Restore Intemal Reference H15714/40CB Parallel, Binary Two-Step Folding DEVICE SUFFIX CODE MIL SPEC HI1175JCB HI1175JCP OUTPUTS FEATURES 25ns 15 HBC10 2 ±0.75 ±0.5 ENOB = 7.8 Bits H15714/60CB 16ns 15 HBC10 2 ±O.75 ±0.5 High ENOB = 7.7 Bits : HIS71417SCB 13ns 15 HBC10 2 ±0.75 ±0.5 ENOB = 7.7 Bits I - CD CD 10-BIT SUBRANGING AID CONVERTER -..j '" DEVICE SUFFIX CODE MIL SPEC OUTPUTS CONVERSION TYPE CONVERSION TIME (liS) RANGE TECHNOLOGY MIN (V) LINEARITY (LSB) CLOCK TYP FEATURES HI5703KCB Offset Binary, 2'5 Complement Pipeline 25ns BiCMOS 1.25 +1.S 1-40MSPS Track and Hold, 400mW, +5V, 9+ ENOB HI5702JCB Offset Binary, 2'5 Complement Pipeline 28ns BiCMOS 1.25 ±1.S 1-40 MSPS Track and Hold, 600mW, +5V, 9+ ENOB HI5710JCQ Offset Binary, 2's Complement 2 Step Flash SOns CMOS 2 ±1.0 HI5705KCB Offset Binary, 2's Complement Pipeline 25ns BiCMOS 1.25 +1.S CONVERSION TYPE CONVERSION TIME (ns) HIS702KCB 25ns SUFFIX CODE MIL SPEC OUTPUTS Parallel, Binary, Three-State,8-Bit Bus,12-Bit Bus and 16-Bit Bus HI5800BID HIS800JCD HI5800KCD Two-Step Track and Hold, 140mW, +5V 1-40MSPS LowCostND - - - - '----~ RANGE TECHNOLOGY MIN (V) BiCMOS 5 INL (LSB) REFERENCE VOLTAGE ±1.0 Internal2.5V ±2.0 FEATURES High Performance Sampling ND, System +11.S ENOB, V REF Sampiing and Hold, 20MHz BW ±1.0 Pipeline HIS804KCB 330ns 200ns ~ ::s o C> . a. CD 0.S-20 MSPS 12-BIT SUBRANGING AID CONVERTER DEVICE en BiCMOS 2.3V ±2.0 Internal -100MHzBW HI1175 a-Bit, 20MSPS Flash AID Converter December 1993 Features Description • Resolution: 8-Blt ±O.5 LSB (DNL) The Hi1175 is an B-bit CMOS analog-to -digital converter for video use. The adoption of a 2-step parallel system achieves low power consumption at a maximum conversion speed of 20MSPS minimum, 35MSPS typical. • Maximum Sampling Frequency: 20MSPS • Low Power Consumption: 60mW (st 20MSPS Typ.) (Reference Current Excluded) • Built-In Sample snd Hold Circuit • Built-In Reference Voltage Self Bias Circuit • Trl-State TTL Compatible Output The HI1175 is available in the Commercial temperature range and is supplied in 24 lead plastic DIP (400 mil) and SOIC (200 mil) packages. Ordering Information • Single +5V Power Supply PART NUMBER • Low Input Capacitance: 11 pF (Typ.) • Reference Impedance: 3000 (Typ.) • Evaluation Board Available TEMPERATURE RANGE PACKAGE H11175JCP ·20oC to +75°C 24 Lead Plastic DIP (400 mil) H11175JCB -200c to +75°C 24 Lead SOIC (200 mil) • LowCost Applications • Video Digitizing • Image Scanners • MuHlrnedla • High Speed Data Acquisition Systems Pinout HI1175 (PDIP, SOIC) TOP VIEW DVss VRB DO (LSB) v_ 3 AVss AVss VIN AVoo VRT VRTS D7(MSB) AVoo DVoo AVoo CLK ----.----......-- DVDD CAUTION: These devices are sansftiw to electrostatic discharge. Users shculd follow proper I.C. Handling Procedures. Copyrlght@Harrls COrporation 1993 7-3 File Number 3Sn.1 HI1175 Functional Block Diagram DVss LOWER COMPARATORS WITH SIH (4 BIT) 1+----++..., AVss AVss LOWER COMPARATORS WITH SIH (4 BIT) 1+---+-+-' UPPER COMPARATORS WITH SIH (4 BIT) 1+--++--..... Typical Application Schematic R11 1K 1C1 I'PC254 R12>4_"""," 1K HC04 >--tt:::. R13 500 +5V CLOCK IN 0 » ......-CLK :$...--II~---t~ D7(MSB) D6 os D4 03 D2 D1 DO (LSB) -12V * : Ceramic Chip Capacitor O.1J1F V : Analog GND ~: Digital GND NOTE: It is necessary that AVoo and DVoo pins be driven from the same supply. The gain of analog Input signal can be changed by adjusting R3. 7-4 Specifications HI1175 Absolute Maximum Ratings Thermal Information Supply Voltage, Voo •••••••••••••••••••.••••••••••••••• 7V Reference VoHage, VRT, VRB •••••••••••••••••••••• Voo to Vss Analog Input Voltage, VIN ••••••••••••••••••••••••• Voo to Vss Digital Input Voltage, ClK. •••••••••••••••••••••••• VDO to Vss Digital Output Voltage, VOH , VOL' ..••••.••.•••.••.. Voo to Vss Storage Temperature, TSTG •••••••••••••••••• -55°C to +15O"C lead Temperature (Soldering 1Os). • . • • • . • • . • . • . • • • . • . +300"C Thermal Resistance 9,JA HI1175JCP (Plastic DIP) • • • • • • • • • • • • . • • • • • • • • • •• 78"CfN HII175JCB (SOIC) •••••••••••.•.•••••••••••••• 98"CfN Maximum Power Dissipation •••••••.•••••••••••••••• 108mW Operating Temperature, TA •••••••••••••••••••• -20"C to +75"C Maximum Junction Temperature ••••••••••••••.•••••• +15O"C CAUTION: Stresses above thosa Hsted in "Absoluta Maximum Rafjngs" may causa permanent damagfJ to tha davlce. This is a stress only ral/ng 8IId operation of the device at lhasa or any other condifjons above lhasa indicated in tha operational sections of this specification is not imp/IBd. Operating Conditions (Note 1) Supply Voltage AVoo , AVss, DVoo , DVss ••••.••••••••.••• +4.75V to +5.25V IDGND·AGNDI. •••.•••••••.•••••••.••••.•• 0mV to l00mV Reference Input Voltage VRB ••••••••.•.••••••••••••.••••••••••.•. OV and Above VRT •••••••••••••••••••.•••••••••••••••• 2.8V and Below Electrical SpeCifications Fe Analog Input Voltage, VIN •••••••••• VRB to VRT (1.8Vp.p to AVoo) Clock Pulse Width TPW1 ••••••••••••••••••••••••••••••••••••••• 25ns (Min.) Tpwo••••••••••••••••••••••••••••••••••••••• 25ns (Min.) =20MSPS, Voo =+5V, VRB =0.5V, VRT =2.5V, TA =+25"C (Note 1) MIN TVP MAX UNIT EOT -60 -35 -10 mV EOB 0 +15 +45 mV =20MSPS, VIN =0.6V to 2.6V Fe =20MSPS, VIN =0.6V to 2.6V · ±0.5 ±1.3 LSB · ±a.3 ±a.5 LSB =20M Hz, fiN =1MHz Fs =20MHz, fiN =3.58MHz - 46 . dB - 46 - dB 20 30 . MSPS · · 1.0 PARAMETER TEST CONDITIONS SYSTEM PERFORMANCE Offset Voltage Integral Non·Unearity, (INl) Differential Non-Unearlty, (DNl) Fe DYNAMIC CHARACTERISTICS Signal to Noise Ratio (SINAD) = RMSSignal RMS Noise + Distortion Maximum Conversion Speed, Fe Differential Gain Error, DG Fs =0.6V to 2.6V, FIN =1kHz Ramp NTSC 40 IRE Mod Ramp, Fe =14.3MSPS VIN Differential Phase Error, DP - Aperture Jitter, tAJ Sampling Delay, tos 0.5 - Degree 30 - ps 4 - ns % ANALOG INPUTS - 18 - - MHz 11 Reference Pin Current, IREF 4.5 6.6 8.7 rnA Reference ReSistance (VRT to VRB), RREF 230 300 450 n Analog Input Bandwidth (·1 dB), BW Analog Input Capacitance, CIN VIN =1.5V + O.07VRMS pF REFERENCE INPUT 7-5 I' i Specifications HI1175 Electrical Specifications Fe =20MSPS, Voo = +5V, VAil = 0.5V, Vrrr = 2.5V, TA = +25°C (Note 1) (Continued) MIN TYP MAX UNIT 0.60 0.64 0.68 V 1.96 2.09 2.21 V 2.25 2.39 2.53 V VIH 4.0 - - V VIL - - 1.0 V VIH=VOO - - 5 JiA VIL=OV - - 5 JiA VOH = Voo -0.5V -1.1 - - rnA VOL = 0.4V 3.7 - - rnA - - 16 JiA - 16 JiA - 18 30 ns - 12 17 rnA PARAMETER TEST CONDITIONS INTERNAL VOLTAGE REFERENCE Self Bias Mode 1 VRS Short VRB and VRIlS. Short Vrrr and Vrrrs Vrrr - VRB Self Bias Mode 2, Vrrr VRB = AGND, Short Vrrr and Vrrrs DIGITAL INPUTS Digital Input Voltage Digital Input Current IIH Voo=Max. IlL DIGITAL OUTPUTS Digital Output Current IOH OE = Vss. Voo = Min. IOL Digital Output Current IOZH OE = Voo, Voo = Max. VOH = Voo lOll VOL=OV TIMING CHARACTERISTICS Output Data Delay, TOL POWER SUPPLY CHARACTERISTIC Supply Current, 100 Fe = 20MSPS, NTSC Ramp Wave Input NOTE: 1. Electrical specifications guaranteed only under the stated operating conditions. 7-6 HI1175 Timing Diagrams Tpwt i TPWO CLOCK ANALOGINPOT DATA OUTPUT TD-I8ne 0: POINT FOR ANALOG SIGNAL 5AMPUNG FIGURE 1. ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK UPPER DATA LOWER REFERENCE VOLTAGE LOWERCOMPARARmBLOCKA LOWERDATAA LOWER COMPARATOR BLOCK B I ::>< ::><: C (1) I 5 (2) X MD (0) MD (1) X RV (0) C (2) RV (1) S (3) I X X C (3) $ (4) I X MD (2) I >C MD (3) X RV (2) C (4) X RV (3) ~I~S~(I~)-L___H_(~I)~__~I_C_(~I)~__S~P~)~____H~P~)__~_C_(~3)~1___ ... :;>c________ M_)______-'~~________ LD __ H(O) LOWERDATAB DIGITAL OUTPUT 5 (1) :;>c 5(2) C(O) LD("z) OUT (.2) LD_(_I)______ X X C(2) OUT (-1) X I I X LO(O) FIGURE 2. 7-7 H(2) OUT (0) X 5(4) ~><:: H(4) LO(2) OUT (1) >C HI1175 Typical Performance Curves 20 100 Vpp. 5.0V, Vm" 2.5V, VAS. O.SV TA - +25"c, VIN - 2Vpp 20 i 15 - 1 j 15 ./ 10 5 ~ 4.0 V 4.5 - V .....- 10 5.0 5.5 TA-+25"C, Vm_2.5V, VAS-0.5V Veo" 5.0Y, f... 20 MSPS !-"" 2 --- 0; is !5 50 a: !... 30 35 FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING RATE FIGURE 3. SUPPLY CURRENT ,!S SUPPLY VOLTAGE o o ......... 10 15 20 25 SAMPUNG RATE (MSPS) 5 POWER SUPPLY VOLTAGE (V) 1A ~ Ii 4 II 8 10 INPUT FREQUENCY (MHz) FIGURE 5. DIFFERENTIAL NON-LINEARITY va INPUT FREQUENCY 7-8 HI1175 Pin Descriptions and Equivalent Circuits PIN NUMBER 1 SYMBOL DESCRIPTION EQUIVALENT CIRCUrr When OE When OE OE + =low, Data Is yalid~ =High, 00 to D7 pins high Impedance. DVss Digital GND. 2,24 DVss 3-10 001007 11,13 DVoo Digital +5V. 12 elK Clock inpul. DO (LSB) 10 07 (MSB) output + 12 16 VATS DVss Shorted with VAT generates, +2.6V. ~AVOO 16 17 VAT ?AVOO 23 VRB ~~~ ~~~ 17 Reference Yoltage (lop). Reference Yoltage (bottom). 23 AAVss 14,15,18 AVoo Analog+5V. 19 VIN Analog input. >~AVm '~~ ~~ X AVss 20,21 AVss 22 VRBS AnalogGND. ~AVSS 7-9 Shorted with VRB generates +O.6V. HI1175 AID OUTPUT CODE TABLE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP VAT 0 ··• ·· ·· · VRB . USB LSB 1 1 1 0 ··· 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 127 1 0 0 128 0 1 1 255 0 0 0 0 ·· · ··· ·· · Detailed Description The HI1175 is a 2-step AID converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can be obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling (S). hold (H). and compare (C). The operation of the part is illustrated In Figure 2. A reference voltage that is between VAT-V RB Is constantly applied to the upper 4-bit comparator group. V,(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples V,(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LO(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B aiternate generating the lower data in order to increase the overall AID sampling rate. Power, Grounding, and Decoupllng To reduce noise effects. separate the analog and digital grounds. In order to avoid latchup at power uP. it is necessary that AVoo and DIIoo be driven from the same supply. Bypass both the digital and analog V00 pins to their respective grounds with a ceramic 0.111f capacitor close to the pin. Analog Input The input capacitance is small when compared with other flash type AID converters. However. it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation. it may be necessary to insert a resistor between the output of the amplifier and the AID input. Reference Input The range of the AID is set by the voltage between VAT and VRB. The internal bias generator will set VATS to 2.6V and VRBS to 0.6V. These can be used as the part reference by shorting VAT and VATS and V RB to VRBS• The analog input range of the AID will now be from 0.6V to ·2.6V and is referred to as Self Bias Mode 1. Self Bias Mode 2 is where VRS is connected to AGND and VAT is shorted to VATS. The analog input range will now be from OV to 2.4V. 7-10 HI1175 Test Circuits VIN DUT HI1175 BUFFER 8 CLK(20MHz) 000···00 TO 111···10 FIGURE 6. INTEGRAL AND DIFFERENTIAL NON-UNEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT ",.,. . '5:1. . ERROR RATE r----, 0.6V '--_ _ _-0 1 21 r:=J 1 t=J 40 IRE 100 IRE 2.6V MODULATION {: BURST o -40 O.6V SYNC -6.2V FC FIGURE 7. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT Veo VAT 2.6V V,N 0.6V .n. 11 Veo VAT 2.6V IOL VAS HI1175 CLK VOL OE GND VIN 0.6V .n. + VAS HI1175 - IoH CLK or GND I. FIGURE 8. DIGITAL OUTPUT CURRENT TEST CIRCUIT 7-11 HI1176 aD HARRIS \KJ SEMICONDUCTOR 8-Bit, 20MSPS Flash AID Converter December 1993 Features Description • Resolution 8-Blt ±O.5 LSB (DNL) • Maximum Sampling Frequency 20MSPS • Low Power Consumption 60mW (at 20MSPS Typ.) (Reference Current Excluded) The H11176Is an a·bit CMOS analog·to-digital converter for video use that features a sync clamp function. The adoption of a 2·step parallel method realizes low power consumption and a maximum conversion speed of 20MSPS. • Built-In Sync Clamp Function • Built-In Monoateble MulOvlbrator for Clamp Pulse GeneraOon • Built-In Sync Pulse Polarity Selection Function • Clamp Pulse Direct Input Possible • Built-In Clamp ON/OFF FuncOon • Built-In Reference Voltage Self Bias Circuit The HI1176 is available In the Commercial temperature range and is supplied in 32 lead Plastic Metric Quad Flatpack (MQFP) package. • • • • • • Ordering Information Input CMOS CompaOble Trl-State TTL Compatible Output Single +5V Power Supply Low Input Capacitance 11 pF (Typ.) Reference Impedance 300n (Typ.) Evaluation Board Available PART NUMBER H11176JCQ TEMPERATURE RANGE ·20oC to +75°C PACKAGE 32 Lead Plastic Metric Cuad Flatpack Applications • Video DlglOzlng • Image Scanners • Low Cost High Speed Date Acquisition Systems • Multimedia Pinout HI1176 (MQFP) TOP VIEW (LSB)DO VRB D1 D2 AYss D3 YIN D4 AVoo AYss os AVoo D8 YRT (MSS)D7 YRTS CAUTION: Thasa ~evices ara sensHIve 10 elec1ros1a1ic discharge. Users should follow proper I.C. Handling Procedures. Copyrlghl © Harris Corporation 1993 7·12 File Number 3582.1 HI1176 Functional Block Diagram DVa r----------------CH~----------------------------_, DO (LSB) 1 AVa lONER SAMPUNG COMPARA1llR ~----~~~ (4 BIT) AVa lONER SAMPUNG COM~1l)R ~---+--r+~ (4 BIT) UPPER SAMPUNG COMPARA1llR ....~HI---...1 D7(MSB) (4 BIT) 8 DVoo DVOO ClK NC mCCPVREF Typical Application Schematic +5V (DIGITAL) HC04 CLOCK IN VIDEO IN 1& 15 14 13 12 11 10 II 8 17 7 18 D7 D6 111 os • 20 21 22 • .... 10pF7 23 24 25H27H211303132 +5V (DIGITAL) WHEN CLAMP IS NOT USED (SELF BIAS USED) 7-13 DD-----oo OD-----oo OD-----oo 5 DD-----oo 4 DD-----oo 3 ClD-----oo 2 ClD-----oo 1 OD-----oo D4 D3 D2 D1 DO Specifications HI1176 Absolute Maximum Ratings Thermal InformatIon. Supply Voltage, Voo ••••••••••••••••••••••••••••••••••• 7V Reference Voltag"" Vm; VAS••••••••••••••••••••••• Voo to Vss Analog Input Voltage, VIN ••••••••••••••••••••••••• VDO to Vss Digital Input Voltage, CLK ••••••••••••••••••••••••• Voo to Vss Digital Output Voltage, VOH' VOL •••••••••••••••••••• Voo to Vss Storage Temperature, TSTG •••••••••••••••••• -5500 to +15O"C Thermal Resistance 9JA H11176JCQ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 122!'c/w Maximum Power Dissipation ••••••••••••••••••••••••• 108mW Operating Temperature, T" •••••••••••••••••••• -20"C to +750 C Maximum Junction Temperature •••••••••••••••••••••• +15O"C CAUTION: stresses abo.... Ihoss lisled In 'AbsolUle Maximum Ratings" may cause psrmenent damage to 1M davlce. This Is a _ of the device at lhese or any other conditions abo.... 1hoss Indicated In 1M ope/Blfone/ sactIons of /his speclHcation is not i1Jf'/lBd. only /B/lng and CJpe/Btion Operating Conditions (Note 1) Supply Voltage AVOD , AVss, OVOI) OVss ••••••••••••••••• +4.75V to +5.25V IDGND-AGNDI •••••••••••••••••••••••••••• 0mV to l00mV Reference Input Voltage VRB ••••••••••••••••••••••••••••••••••••• OV and Above VRT ••••••••••••••••••••••••.••••••••••• 2.8V and Below Electrical Specifications Analog Input Voltage, VIN •••••••••• VRB to VRT (1.8Vp.p to AVoo) Clock Pulse Width TPWI ••••••••••••••••••••••••••••••••••••••• 25ns (Min.) Tpwo••••••••••••••••••••••••••••••••••••••• 25ns (Min.) Fe = 20MSPS, Voo = +5'1, VRB = 0.5V, VRT = 2.5V, T" = +2SOC (Note 1) MIN TYP MAX UNIT EOT -eo -40 -20 mV EOB +20 +40 +80 mV ±O.5 ±1.3 LSB ±O.3 ±O.5 LSB PARAMETER TEST CONDITIONS SYSTEM PERFORMANCE Offset Voltage Integral Non-Linearity, (INL) Fe = 2OMSPS, VIN = 0.5V to 2.5V Differential Non-Unearlty, (DNL) Fe = 20MSPS, VIN = 0.5V to 2.5V - Signal to Noise Ratio (SINAD) RMSSlgnal RMS NOise + Distortion Fs = 20MHz, fiN = 1MHz - 46 Fs = 20MHz, fiN = 3.58MHz - 46 Maximum Conversion Speed, Fe VIN = 0.5V to 2.5V, FIN = 1kHz Ramp 20 35 Differential Gain Error, DG NTSC 40 IRE Mod Ramp, Fc = 14.3MSPS DYNAMIC CHARACTERISTICS = Differential Phase Error, DP Aperture Jitter, tAJ Sampling Delay, tos - 4 - 18 - MHz 11 - pF 1.0 0.5 30 dB dB MSPS % .Degree ps ns ANALOG INPUTS - Analog Input Bandwidth (-1 dB), BW Analog Input Capacitance, CIN VIN = 1.5V + O.07VRMS REFERENCE INPUT Reference Pin Current, IREF 4.5 6.6 8.7 rnA Reference Resistance (VRT to VRB), RREF 230 300 450 n 7-14 Specifications HI1176 Electrical Specifications Fc = 20MSPS, voo = +5V, VRB = 0.5V, VAT .. 2.5V, TA .. +25"C (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNrr 0.48 0.52 0.56 V 1.96 2.08 2.22 V - V 1.0 V 5 IIA 5 IIA INTERNAL VOLTAGE REFERENCES Self Bias VRB Short VRB and VRIISo Short VAT and VRTS VAT - VRB DIGITAL INPUTS Digital Input VoltagB VIH 4.0 Vil - - - - VOH = Voo -C.5V -1.1 - VOL = 0.4V 3.7 - - DIgital Input Current Voo=Max. IIH VIH=VOO Vll=OV III DIGITAL OUTPUTS Digital Output Current OE = Vss, Voo = Min. IOH IOl rnA rnA Digital Output Current - - 16 IIA - 16 IIA - 18 30 ns Fc = 20MSPS, NTSC Ramp Wave Input - 12 18 rnA VIN = DC, PWS = 3f.IS8C VREF =0.5V 0 +20 +40 mV VREF =2.5V -50 -30 -10 mV 1.75 2.75 3.75 lIS - 25 - ns OE .. Voo, Voo = Max. IOZH VOH"VOO VOl=OV IOZl TIMING CHARACTERISTICS Output Data Delay, TDl POWER SUPPLY CHARACTERISTIC Supply Current, 100 CLAMP CHARACTERISTICS Clamp Offset Voltage, Eoc Clamp Pulse Width (Sync Pin Input), tcpw C = 100pF, R = 130kQ on Pin 15 Clamp Pulse Delay, tcpd NOTE: 1. Electrical specifications guaranteed only under the stated operating conditions. 7-15 HI1176 Timing Diagrams TPW1 i TPWO CLOCK ANALOG INPUT DATA OUTPUT 0: POINT FOR ANALOG SIGNAL SAMPUNG FIGURE 1. ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK UPPER DATA LOWER REFERENCE VOLTAGE LOWER COMPARATOR BLOCK A LOWER DATA A LOWER COMPARATOR BLOCK B I S (1) :::>< C(O) LD(4) OUT (4) I S (3) X I I X C (3) MD(2) X RV(1) S(3) C(1) S (2) H (2) FIGURE 2. 7-16 X C (4) X RV(3) C(3) S(4) X OUT (0) X I >C I I C(2) I >C MD(3) LD(1) LD_(O.;..)_ _ _ OUT (.1) I H(3) X,,___ X S (4) X RV(2) I I X LD(·1) H(O) C (2) MD(1) H(1) :x ::>< S (2) X RV(O) S(1) LOWERDATAB D1GITALOUTPUT MD(O) :x I I X C (1) H (4) LD(2) OUT (1) >C HI1176 Typical Performance Curves 20 100 Vpp. 5.0V, VAT. 2.5V, VAS .O.IV TA. +25OC, VIN. ZVpp 20 _ 15 15 1 j 10 5 V 4.0 ,/' ./ ./ ~ ~ 10 4.5 5.0 ~ s 5.5 10 15 20 25 SAMPUNG RATE (MSPS) POWER SUPPLY VOLTAGE (V) ! i TA. +26OC, VAT. 2.5V, VRB. o.sv VDD. I.OV, ,..20 MSPS 1.0 i ::a! 0.6 ~ ItZ5 ~ 0.2 o o 2 4 6 8 10 INPUT FREQUENCY (MHz) FIGURE S. DIFFERENTIAL NON-LINEARITY vs INPUT FREQUENCY Pin Descriptions PIN NUMBER SYMBOL 1-8 DOlO 07 DESCRIPTION EQUIVALENT CIRCUIT DO (LSB) to 07 (MSB) output D1 10,11 30 35 FIGURE 4. SUPPLY CURRENT AND POWER VI SAMPUNG RATE FIGURE 3. SUPPLY CURRENT va SUPPLY VOLTAGE 1A ---- --- Digital +5V. DVoo 7-17 HI1176 Pin Descriptions (Continued) PIN NUMBER SYMBOL 12 ClK Clock Input. 13 SEl When SEl Is low, the failing edge of Pin 14 (sync) triggers the monostable. When SEl Is high, the rising edge of Pin 14 (sync) triggers the monostable. 14 SYNC 11'lgger pulse Input to the monostable multivibrator. Trigger polarity can be controlled by Pin 13 (SEl). 15 PW When a clamp pulse Is generated by the monostable, the pulse width Is determined by the external Rand C. When the clamp pulse Is direcUy input, It Is Input to Pin 15 (PW). 16,19,20 AVoo Analog +5v' 17 VRTS When shorted with Vim generates approx. +2.6V. DESCRIPTION EQUIVALENT CIRCUIT ~AVDD 17 18 VRT Reference voltage (top). 24 VRB Reference voltage (bottom). 7-18 HI1176 Pin Descriptions (Continued) PIN NUMBER SYMBOL EQUIVALENT CIRCUIT 22,23 DESCRIPTION Analog input. 21 Analog ground. AVss 25 IAVss When shorted with VRB, generates approx. + z< ,' Za: Om ~ 3.0 Throughput Rate le- U;:) , DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB below full scale) Signal to Noise Ratio (SNR) RMSSignai = RMSNoise en W "z a: 66 67 - 3.0 - 66 67 71 69 68 70 67 68 - -74 -70 -70 -68 76 72 - -74 -66 - - 0.9 0.05 12 20 10 20 76 71 - -75 -74 -70 84 - -62 75 MSPS dB dB dB dB dBc dBc dBc dBc -82 -70 - 0.9 - % - 0.05 - Degrees 12 20 ns 10 20 ps - dBc en ' Specifications H15800 Electrical Specifications AVcc = +5V, DVcc = +5V, AVEE = ·5V, DVEE = ·5V; Internal Reference Used Unless Otherwise Specified (Continued) H15800JCWAIDlJCD HI5800KCWBIDlKCD O·Cto +700 C ·40"C to :l"85OC O"C to +70"C ·40"C to +85°C TYP MAX ±2.7 · ±2.5 ±2.7 V 3 · MO 5 · · 1 5 · pF 1 ±10 1 ±10 p.A · 20 · · · · 20 · MHz 2.450 2.500 2.550 2.470 2.500 2.530 V 2 · 2 · · rnA · 20 · · · 20 · ppm/·C · · 2.5 2.S · 2.5 2.S V 200 · · 200 · 0 · · · 2.0 · · · V 0.8 0.8 V 1 ±10 p.A 5 · pF V TYP MAX Input Voltage Range · ±2.5 Input Resistance 1 3 Input Capacitance Input Current · · Input Bandwidth TEST CONDITION UNITS MIN MIN PARAMETER ANALOG INPUT INTERNAL VOLTAGE REFERENCE Reference Output Voltage, REFOUT (loaded) Reference Output Current Note 5 Reference Temperature Coefficient REFERENCE INPUT Reference Input Range Reference Input Resistance DIGITAL INPUTS Input logic High Voltage, VIH NoteS 2.0 · · · 1.0 ±10 5.0 · · · · 2.4 4.3 · 2.4 4.3 · Input logic low Voltage, VIL Input logic Current, IlL VIN=OV,5V Digital Input Capacitance, CIN VIN=OV DIGITAL OUTPUTS Output logic High Voltage,VoH lOUT = .1SOp.A Output logic low Vottage,VoL lOUT = 3.2rnA · 0.22 0.4 · 0.22 0.4 V Output logic High Current, IOH -0.1 SO S S 3.2 6 3.2 6 · · rnA Output logic low Current, IOL · · -0.160 Output TrI·state leakage Current, VouT =OV,5V loz · ±1 ±10 · ±1 ±10 p.A Digital Output CapaCitance, COUT · 10 · · 10 · pF · · · · · · 10 10 15 0 · · · · · · ns · · · · · · · · rnA TIMING CHARACTERISTICS Minimum CONY Pulse, t1 (Notes 2, 3) 10 CS to CONY Setup Time, t2 (Note 2) 10 CONY to CS Setup Time, t3 (Note 2) 0 Minimum OE Pulse, t4 (Notes2,4) 15 CS to OE Setup Time, 15 (Note 2) 0 7·26 0 ns ns ns ns Specifications HI5800 Electrical Specifications AVcc = +5V, DVcc = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used Unless Otherwise Specified (Continued) PARAMETER TEST CONDITION OE 10 CS Selup Time, t6 (Note 2) IRQ Delay from Start Convert, t7 (Note 2) IRQ Pulse Width, t8 Hf5800JCMlAfDlJCD HI5800KCMlBIDlKCD OOC to +70oC -400C to +85°C OOCto+70oC -400C to +85°C MIN TVP MAX MIN TYP MAX UNITS 0 - - 0 - - ns 10 20 25 10 20 25 ns 190 205 230 190 205 230 ns - - 333 - 333 333 ns 0 +5 -5 0 +5 ns Minimum Cycle Time for Conversion, t9 IRQ to Data Valid Delay, t1 0 (Note 2) -5 Minimum AO Pulse, t11 (Notes2,4) 10 - - 10 - - ns Data Access from OE Low, 112 (Note 2) 10 18 25 10 18 25 ns LSB, Nibble Delay from AO High, t13 (Note 2) - 10 20 - 10 20 ns MSB Delay from AO Low, t14 (Note 2) - 14 20 - 14 20 ns CS 10 Float Delay, 115 (Nole2) 10 18 25 10 18 25 ns Minimum CS Pulse, t16 (Notes2,4) 15 - - 15 - - ns 18 25 10 18 25 ns 5 20 20 ns 5 20 - 5 5 20 ns 180 220 220 mA 190 - 180 158 158 190 mA CS to Data Valid Delay, t17 (Note 2) 10 Output Fall Time, tf (Note 2) Output Rise Time, Ir (Note 2) - POWER SUPPLY CHARACTERISTICS IDVcc - IDVEE - IVcc IVEE - Power Dissipation PSRR Vcc , VEE±5% 27 40 - 27 40 mA 2.7 5 - 2.7 5 mA 1.8 2.2 1.8 2.2 W 0.01 0.05 0.01 0.05 %1% - NOTE: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 2. Parameter guaranteed by design or characterization and not production tested. 3. Recommended pulse width for CONV Is 60ns. 4. Recommended minimum pulse width Is 25ns. 5. This is the addHlonal current available from the REFoUT pin with the REFoUT pin driVing the REFIN pin. 6. The Ali pin V1H at-40OC may exceed 2.0V by up to O.4V al initial power up. 7. Excludes error due to internal reference temperature drift. 7-27 HI5800 Timing Diagrams k CONV--- "?, ,, : Ci~'lcK:'~"";"",- - - - - 111 IRQ ~ ~,------ -..jt7~ : : ACQUIRE N ~"N-C-ON--~-E-~--ON'"_ _ _ _ _ _ _ _-+i______o;i____ OATAVAUO ______N_"_1_DA_r._A_'_ _ _J~,_ _ _ _ _ _ _ _~--N-0-At-A--~---- A6 ----------------------------------~----------~----­ OE --------------...~,------~,~-----~---- DO-011,OVF ----------------~--~K(~N~DA;~~)~r----+~K::: -: 115 l-..- ~11Z --l ~117f4_ FIGURE 1. SINGLE SHOT TIMING Ci • 1:. $... ~ \ IZ CONY . ..\ ; t3 , Ci " i .. "'\ OE ~t1=:r FIGURE 2A. START CONVERSION SETUP TIME IS $: :i . . ..j \ , ,, II ~14~ FIGURE 2B. OUTPUT ENABLE SETUP TIME FIGURE 2. -CO~ '\l.; CS~ ~,.---------------------------I --117 IRQ ...;A.;;COU;..;;.;.;;.IR.;;;E;.;N~ X DATA VAUO _____N_-1_DA_r._A_ _ _ _ _.J NDATA >K N+1 DATA ;~---------------------t 111~----~j-------\.WU",! ~ i l '--,.-~_-~~~~~:-----+:--~;~----04-D11 -------------~.-~:< 011-04 ~-DO, oooo~ 011-04 .. . -«(,..----------~ NDATA X,,-----__N_+_1_DA__:rA__ DO- 011, OVF _____________+! ---\l1zf...= FIGURE 3. CONTINUOUS CONVERSION TIMING 7-28 HI5800 Typical Performance Curves 70/----.,..-__-+__;;;;;;;;--1 80~--------~~--------~------------, 90 60 70 60r_--------~r_--------_+----------~ 60 50r_--------~r_--------_+----------~ mao m ~40r_--------~r_--------_+----------~ ~4O 30r_--------~r_--------_+----------~ 30 20r_--------~r_--------_+----------~ 20 10r---------~~--------_+----------~ OL-________-L__________ 20K SOOK ~ ________ 10 0 20K ~ 1M 2M SOOK 1M 2M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) FIGURE 5. TYPICAL THO va INPUT FREQUENCY FIGURE 4. TYPICAL SNR va INPUT FREQUENCY 80 QOr----------,----------~----------, 80~::t:::~~ 70 70~ &0 &or----------t----------t----------i so m 50r_---------;----------_+----------, m 40 ~ ~ 4O~--------_1----------_+----------, 30r_---------;----------_+----------, 30 20 2Or----------t----------t----------i 10 10r_---------;----------_+----------, OL-________-L__________ ________ ~ 0 20K &OOK 1M SOOK 20K 2M FIGURE 6. TYPICAL SNO va INPUT FREQUENCY FIGURE 7. TYPICAL SFOR VI INPUT FREQUENCY 11.5 )"",. 11.25 10r_--------~~--------_+----------~ ~ m 8r_--------~r_--------_+----------~ 1.0 IL 0 d 10.75 z ~ 6r---------~~--------_+----------~ w g > fi ~ 4r----------+----------t---------~ 20K 500K 1M 10.5 ~ 10.25 w IL 2r----------+----------t---------~ OL-________-L__________L -________ 2M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) ~ m ~ 1M 10.0 ~ 11.75 0.5 2M ~I / ,. - / / 1.0 1.SO INPUT FREQENCY (Hz) 2.00 2.50 VREF(V) FIGURE 8. TYPICAL EFFECTIVE BITS va INPUT FREQUENCY 7-29 FIGURE 9. EFFECTIVE NUMBER OF BITS va REFERENCE VOLTAGE (Fs 3MHz, FIN 20kHz) = = HI5800 Typical Performance Curves (Continued) 1.0...-----,-----,------,-----" 1.0 ...----..,..-----,------r----n -0.5 1···················,+······,,····,.. ····,··;··,··················+····..·····,,····,,·····H -0.5 1····················+··,······......,..·..·.,......·....·...."..·,..·,·....•·....·,......1·1 ·1.0 1..-_ _ _- ' -_ _ _- ' -_ _ _--'-_ _ _--''-' ·1.0 ' - - - - - - ' - - - - - ' - - - - - - ' - - - - - - '.... o 2000 1000 o 4000 3000 1000 3000 2000 CODE CODE 4000 FIGURE 11. INTEGRAL NON·LINEARITY FIGURE 10. DIFFERENTIAL NON·UNEARITY 10...----~---~~---~---_" o ..................."1 ..................."1"..............······I······.. ············t· ; : ::::::::::::::::::::1::::::::::::::::::::1:::::::::::::::::::::1::::::::::::::::::::1: ~ !. . . . . . . . . . !. . . . . . . . . . .\. . . . . . . . . . !. ·75 .................... ~ 0.100 1\1 r ' r I r ,. I I I t I ill' 'I I .. ·125 ·135 ~-----. o 3SSK 730K 1.095M 1.46M FREQUENCY (Hz) ·126 ·136 ~-~ 3SSK 730K 1.0II5M 1.46M o FREQUENCY (Hz) FIGURE 12. FFT SPECTRAL PLOT FOR FIN" 20kHz, Fa .. 3MHz FIGURE 13. FFT SPECTRAL PLOT FOR FIN" 1MHz, Fa .. 3MHz 10r-----r----..------,----~~ o -------------..-----t-------······-------1-----······--_. ·····r····--_. 10r---,----,-----,---~--_,_--~ ·····u·····t· ol....,..•..·..·f ......,....·.. t .... ··..·n..·t·............·i.. ·..........·.. f....·,......,..·1 i:::~::t:=t=:t=j .l. . . . . . . . . .,j.................. 1. ..I ~ ..1 .................... .75 ................... 0·100 ·125 ·135 I I " , I ' I I \1 --o 365K 730K 1.095M FREQUENCY (Hz) 1.46M FIGURE 14. FFT SPECTRAL PLOT FOR FIN .. 2MHz, Fa .. 3MHz 18.3K 3UK 55K 73.3K FREQUENCY (Hz) fI1.6K 110K FIGURE 15. INTERMODULATION DISTORTION PLOT FOR FIN II 49kHz, 50kHz at Fa .. 3MHz 7·30 HI5800 Pin Description 44 PIN PLCC 40 PIN 2 1 3 2 REFIN RO ADJ 4 3 RGADJ DAC gain adjust (Connect to AGND if not used). 5 4 AVcc Analog positive power supply, +5V. 6 5 1 - REFouT NC DIP PIN NAME PIN DESCRIPTION External reference input. DAC offset adjust (Connect to AGND if not used). Internal reference output, +2.5V. No connection. Analog input voltage. 7 6 V1N 8 7 AGND Analog ground. 9 8 ADJ+ Sample.'hold offset adjust (Connect to AGND if not used). 10 9 ADJ- Sample.'hold offset adjust (Connect to AGND if not used). 11 10 AVEE Analog negative power supply, -5V. 13 11 12 AVcc AGND Analog positive power supply, +5V. 14 15 13 AVEE 16 14 AO 17 15 CS Chip Select input, active low. Dominates all control inputs. 12 - NC No connection. 18 16 OE Output Enable input, active low. 19 17 CONV Convert start input. Initiates conversion on the falling edge. If held low, continuous conversion mode overrides and remains In effect until the input goes high. 20 18 19 DVEE DGND Digital negative power supply, -5V. 21 22 20 DVcc Digital positive power supply, +5V. 24 21 Analog positive power supply, +5V. 25 22 AVcc DO 26 23 01 27 24 02 Data bit 2. 28 25 03 Data bit 3. 23 - NC No connection 29 26 D4 Data bit 4. 30 27 05 Data bit 5. 31 28 06 Data bit 6. 32 29 07 33 30 AVEE Analog ground. Analog negative power supply, -5V. Output byte control input, active low. When low, data Is presented as a 12 bit word or the upper byte (011 - 04) in 8 bit mode. When high, the second byte contains the lower LSBs (03 - DO) with 4 trailing zeroes. See Text. Digital ground. Data bit 0, (LSB). Data bit 1. Data bit 7. Analog negative power supply, -5V. 35 31 AGND Analog ground. 36 32 DGND Digital ground. 37 33 34 DVcc 08 Digital positive power supply, +5V. 38 39 34 35 09 Data bit 9. - NC No connection. 40 36 010 Data bit 10. 41 37 011 Data bit 11 (MSB). 42 38 Analog positive power supply, +5V. 43 39 AVcc OVF 44 40 IRQ Data bit 8. Overflow output. Active high when either an overrange or underrange analog Input condition Is detected. Interrupt ReQuest output. Goes low when a conversion Is complete. 7-31 HI5800 'Description Stand Alone Operation The H15800 is a 12-bit two step sampling analog to digital converter which uses a subranging technique with digital error correction. As illustrated in the block diagram, It uses a sample and hold front end, 7-bit R-2R DtA converter which is laser trimmed to 14 bits accuracy, a 7-bit BiCMOS flash converter, precision bandgap reference, digital controller and timing generator, error correction logic, output latches and BiCMOS output drivers. The converter can be operated in a stand alone configllration with bus inputs controlling the converter. The conversion will be started on the negative edge of the convert (CONV) pulse as long as this pulse Is less than the converter throughput rate. If the converter is given multiple convert commands, it will ignore all but the first command until such time when the acquisition period of the next cycle is complete. At this point It will start a new conversion on the first negative edge of the Input command. This allows the converter to be synchronized to a multiple of a faster external clock. The new output data of the conversion is available on the same cycle at the negative edge of the IRQ pulse and is valid until the next negative edge of the IRQ pulse. Data may be accessed at any time during these cycles. It should be noted that If the data bus is kept enabled all the time (OE is low), then the data will be updating just before the IRQ goes low. During this time, the data may not be valid for a few nanoseconds. The falling edge of the convert command signal puts the sample and hold (StH) in the hold mode and the conversion process begins. At this point the Interrupt Request (IRQ) line is set high indicating that a conversion is in progress. The output of the S/H circuit drives the input of the 7-bit flash converter through a switch. After allowing the flash to settle, the intermediate output of the flash Is stored in the latches which feed the DtA and error correction logic. The DtA reconstructs the analog signal and feeds the gain amplifier whose summing node subtracts the held signal of the StH and amplifies the residue by 32. This signal is then switched to the flash for a second pass using the input switch. The output of the second flash conversion is fed directly to the error correction which reconstructs the twelve bit word from the fourteen bit input. The logic also decodes the overflow bit and the polarity of the overflow. The output of the error correction is then gated through the read controller to the output drivers. The data is ready on the bus as soon as the IRQ line goes low. 110 Control Inputs The converter has four active low inputs (CS, CONV, DE and AO) and fourteen outputs (DO - 011, IRQ and OVF). All inputs and outputs are TTL compatible and will also interface to the newer TTL compatible families. All four inputs are CMOS high input impedance stages and all outputs are BiMOS drivers capable of driving 100pF loads. In order to initiate a conversion or read the data bus, CS should be held low. The conversion is initiated by the falling edge of the CONV command. The DE input controls the output bus directly and is Independent of the conversion process. The data on the bus changes just before the IRQ goes low. Therefore if the DE line is held low all the time, the data on the bus will cha~ just before the IRQ line goes low. The byte control signal AO is also independent of the conversion process and the byte can be manipulated anytime. When AO is low the 12 bits and overflow word is read on the bus. The bus can also be hooked up such that the upper byte (011 04) is read when AO is low. When AO is high, the. lower byte (03 - DO) is output on the same eight pins with trailing zeros. In order to minimize switching noise during a conversion, byte manipulations done uSinQ.!t1e AO signal should be done in the single shot mode and AO should be changed during the acquisition phase. For accuracy, allow sufficient time for settling from any glitches before the next conversion. Once a conversion Is started, the converter will complete the conversion and acquisition periods irrespective of the Input states. If during these cycles another convert command is issued, it will be ignored until the acquire phase is complete. Continuous Convert Mode The converter can be operated at its maximum rate by taking the CONV line low (supplying the first negative edge) and holding it low. This enables the continuous convert mode. During this time, at the end of the internal acquisition period, the converter automatically starts a new conversion. The data will be valid between the IRQ negative edges. Note that there is no pipeline delay on the data. The output data Is available during the same cycle as the conversion and is valid until the next conversion ends. This allows data access to both previous and present conversions in the same cycle. When initia!!!:!sa conversion or a series of conversions, the last signal (CS and CONV) to arrive dominates the function. The same condition holds true for enabling the bus to read the data (CS and O.§h To terminate the bus operations, the first signal (CS and OE) to arrive dominates the function. Interrupt Request Output The interrupt request line (IRQ) goes high at the start of each conversion and goes low to indicated the start of the acquisition. During the time that IRQ is high, the internal sample and hold is in hold mode. At the termination of IRQ, the sample and hold switches to acquire mode which lasts approximately 1oons.. If no convert command Is issued for a period of time, the sample and hold simply remains in acquire mode tracking the analog input signal until the next conversion cycle is initiated. The IRQ line is the only output that is not tri-stateable. Analog Input, VIN The analog input of the HI5800 is coupled into the input stage of the Sample and Hold amplifier. The input is a high impedance bipolar differential pair complete with an ESD protection circuit. Typically it has >3MO input impedance. With this high input impedance circuit, the HI5800 is easily interfaced to any type of op-amp without a requirement for a high drive capabiiity. Adequate precautions should be taken while driving the input from high voltage output op-amps to 7-32 HI5800 ensure that the analog input pin is not overdriven above the specified maximum limits. For a +2.5V reference, the analog input range is ±2.5V. This input range scales with the value of the external reference voltage if the internal reference is not used. For best performance, the analog ground pin next to the analog input should be utilized for signal return. Figures 16 and 17 illustrate the use of an input buffer as a level shifter to convert a unipolar signal to the bipolar input used by the H15800. Figure 16 is an example of a non-inverting buffer that takes a 0 to 2.5V input and shifts it to ±2.5V. The gain can be calculated from VOUT = [ 1 + (Rl~~R3)] x VIN - [ Rl : l R3] x VOFFSET Reference Input, REFIN The converter requires a voltage reference connected to the REFIN pin. This can be the above internal reference or it can be an external reference. It is recommended that adequate high frequency decoupling is provided at the reference input pin in order to minimize overall converter noise. A user trying to provide an external reference to a HI5800 is faced with two problems. First, the drift of the reference over temperature must be very low. Second, it must be capable of driving the 2000 input impedance seen at the REFIN pin of the H15800. Figure 18 is a recommended circuit for doing this that is capable of 2ppm/oC drift over temperature. HASI77 HASOO2 +IS +IS R1 R 3 VOFFSET -W'v-....- -......- .. HISSOO REFIN O.~ LOW TC RESISTOR FIGURE 18. EXTERNAL REFERENCE ~_ _ _ VO_U_T-t HISSOO Supply and Ground Considerations VIN O.~ FIGURE 16. NON-INVERTING BUFFER Figure 17 is an example of an inverting buffer that level shifts a OV to 5V input to ±2.5V. Its gain can be calculated from VOUT V IN = (-R 2/R 1) xV IN R1 1M R3 21ffi VOFFSET (R 2/R 3) XVOFFSET R2 llffi O.~ The HI5800 has separate analog and digital supply and ground pins to help keep digital noise out of the analog signal path. For the best performance, the part should be mounted on a board that provides separate low impedance planes for the analog and digital supplies and grounds. Only connect the two grounds together at one place preferably as close as possible to the part. The supplies should be driven by clean linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the H15800. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. VOUT HISSOO V IN O.~ Refer to the Application Note ·Using Harris High Speed AID Converters" (AN9214) for additional suggestions to consider when using the H15800. Error Adjustments FIGURE 17. INVERTING BUFFER Note that the correct op amp must be chosen in order to not degrade the overall dynamic performance of the circuit. Recommended op amps are called out in the figures. Voltage Reference, REFoUT The HI5800 has a curvature corrected internal band-gap reference generator with a buffer amplifier capable of driving up to 15mA. The band-gap and amplifier are trimmed to give +2.50V. When connected to the reference input pin REFIN , the reference is capable of driving up to 2mA externally. Further loading may degrade the performance of the output voltage. It is recommended that the output of the reference be decoupled with good quality capacitors to reduce the highfrequency noise. For most applications the accuracy of the HI5800 is sufficient without any adjustments. In applications where accuracy is of utmost importance three external adjustments are possible: S/H offset, D/A offset and D/A gain. Figure 19 illustrates the use of external potentiometers to reduce the HI5800 errors to zero. The D/A offset (ROADJ) and S/H offset (ADJ+ and ADJ-) trims adjust the voltage offset of the transfer curve while the D/A gain trim (RG ADJ) adjusts the tilt of the transfer curve around the curve midpoint (code 2048). The 10kO potentiometers can be installed to achieve the desired adjustment in the following manner. 7-33 HI5800 vee r- ;::.: ..... ROADJ ~ RG ADJ 10kD ..~ VEE r- ADJ+ ..... 10kD 0..... ..... ADJ- J"'" VEE FIGURE 19. D/A OFFSET, D/A GAIN AND S/H OFFSET ADJUSTMENTS Typically orily one of the offset trimpots needs to be used. The offset should first be adjusted to get code 2048 centered at a desired DC input voltage such as zero volts. Next the gain trim can be adjusted by trimming the gain pot until the 4094 to 4095 code transition occurs at the desired voltage (2.500V - 1.5 LSBs for a 2.5V reference). The gain trim can also be done by adjusting the gain pot until the code 0 to 1 transition occurs at a particular voltage (-2.5V + 0.5 LSBs for a 2.5V reference). If a nonzero offset is needed, then the offset pot can be adjusted after the gain trim is finished. The gain trim is simplified if an offset trim to zero is done first with a nonzero offset trim done after the gain trim is finished. The D/A offset and S/H offset trimpots have an identical effect on the converter except that the S/H offset is a finer resolution trim. The D/A offset and D/A gain typically have an adjustment range of ±30 LSBs and the S/H offset typically has an adjustment range of ±20 LSBs. TABLE 1. VO TRUTH TABLE INPUTS OUTPUT CS CONV OE AD IRQ 1 X X X X No operation. 0 0 X X X Continuous convert mode. 0 X 0 0 X Outputs all 12-bits and OVF or upper byte D11 - D4 in 8 bit mode. 0 X 0 1 X In 8-bit mode, outputs lower LSBs D3 - DO followed by 4 trailing zeroes and OVF, (See text). 0 1 X X 0 Converter is in acquisition mode. 0 X X X 1 Converter is busy doing a conversion. 0 X 1 X X Data outputs and OVF in high impedance state. X's FUNCTION =Don't Care TABLE 2. AID OUTPUT CODE TABLE CODE DESCRIPTION LSB = 2 (REFIN) (NOTE 1) INPUT VOLTAGE REF1N =2.5V (V) OUTPUT DATA (OFFSET BINARY) MSB LSB OVF 011 010 09 08 07 06 05 04 03 02 01 DO +2.5000 1 1 1 1 1 1 1 1 1 1 1 1 1 +FS - 1LSB +2.49878 0 1 1 1 1 1 1 1 1 1 1 1 1 +314FS +1.8750 0 1 1 1 0 0 0 0 0 0 0 0 0 +1/2FS +1.2500 0 1 1 0 0 0 0 0 0 0 0 0 0 +lLSB +0.00122 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0.0000 0 1 0 0 0 0 0 0 0 0 0 0 0 -1 LSB -0.00122 0 0 1 1 1 1 1 1 1 1 1 1 1 -1/2FS -1.2500 0 0 1 0 0 0 0 0 0 0 0 0 0 0 4096 ~+FS ~ -314FS -1.8750 0 0 0 1 0 0 0 0 0 0 0 0 -FS + 1LSB -2.49878 0 0 0 0 0 0 0 0 0 0 0 0 1 :s;-FS :s; -2.5000 1 0 0 0 0 0 0 0 0 0 0 0 0 NOTE; 1. The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage. 7-34 HI5800 If no external adjustments are required the following pins should be connected to analog ground (AGND) for optimum performance: ROADJ• RG ADJ • ADJ+. and ADJ-. Typical Application Schematic A typical application schematic diagram for the H15800 is shown with the block diagram. The adjust pins are shown with 10Kn potentiometers used for gain and offset adjustments. These potentiometers may be left out and the respective pins should be connected to ground for best untrimmed performance. frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the AID. The sine wave input to the part is -O.5dS down from full scale for all these tests. Distortion results are quoted in dSc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Signal-ta-Noise Ratio (SNR) SNR is the measured rms signal to rms noise at a specified input and sampling frequency. The noise is the rms sum of all of the spectral components except the fundamental and the first five harmonics. Signal-ta-Noise + Distortion Ratio (SINAD) Definitions Static Performance Definitions SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding Offset. fullscale. and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus fullscale values. The results are all displayed in LSS·s. Effective Number Of Bits (ENOB) Offset Error (VOS) The effective number of bits (ENOS) is derived from the SINAD data. ENOS is calculated from: The first code transition should occur at a level 1/2 LSS above the negative lullscale. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Fullscale Error (FSE) The last code transition should occur for a analog input that is 11/2 LSSs below positive fullseale. Fullscale error is defined as the deviation 01 the actual code transition from this pOint. Differential Unearlty Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSS. The converter is guaranteed for no missing codes over all temperature ranges. Integrel Unearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated Irom the measured data. Power Supply Rejection (PSRR) Each of the power supplies are moved plus and minus 5% and the shift in the offset and lullscale error is noted. The number reported is the percent change in these parameters versus fullscale divided by the percent change in the supply. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5800. A low distortion sine wave is applied to the input. it is sampled. and the output is stored in RAM. The data is then transformed into the DC. ENOS where: =(SINAD - 1.76 + VCORR) /6.02 VCORR = 0.5dS Total Harmonic Distortion (THO) THO Is the ratio 01 the RMS sum of the first 5 harmonic components to the rms value of the measured input signal. Spurious Free Dynamic Range (SFOR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component If the harmonics are buried in the noise Iloor it Is the largest peak. Intermodulatlon Distortion (IMO) Nonlinearities in the signal path will tend to generate intermodulation products when two tones. 11 and 12. are present on the inputs. The ratio of the measured signal to the distortion terms is calculated. The IMD products used to calculate the total distortion are (12-11). (12+11). (211-12). (211 +12). (212f1). (212+f1). (3f1-f2). (3f1+12). (312-f1). (312+f1). (212-211). (212+211). (211). (212). (211). (212). (4f1). (412). The data reflects the sum of all the IMD products. Full Power Input Bandwidth Full power bandwidth is the frequency at which the amplitude 01 the lundamental of the digital output word has decreased 3dS below the amplitude of an input sine wave. The input sine wave has a peak-ta-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. 7-35 HI5800 Die Characteristics DIE DIMENSIONS: 202 x 283 x 19 ± 1mils METALUZATION: Metal 1: Type: AISiCu, Thickness: Metal 1: Type: AISiCu, Thickness: sKA +1500Al-750A 1SKA +2500Al-11 ooA GLASSIVATION: Type: Sandwich Passiviltion - Nitride + Undoped &i Glas§ (USG) Thickness: Nitride - 4KA, USG Total - 12KA ±2KA aKA, TRANSISTOR COUNT: 10K SUBSTRATE POTENTIAL (POWERED UP): VEE Metallization Mask Layout HI5800 o Q VIN AGND AGND ADJ+ D8 Dvcc AVec DGND AVec AGND VEe AGND D7 D6 AO l/!!!!!!!H;I!!IIB D6 cs D4 Q 7-36 S HI-7153 8 Channel, 10-Bit High Speed Sampling AID Converter December 1993 Features Description • SJ.18 Conversion Tlme • 8 Channel Input Multiplexer The HI·7153 is an 8 channel high speed 10 bit AID converter which uses a Two Step Flash algorithm to achieve through-put rates of 200kHz. The converter features an 8 channel CMOS analog multiplexer with random channel addressing. A unique switched capacitor technique allows a new input voltage to be sampled while a conversion is taking place. • 200,000 ChannelS/Second Throughput Rate • Over 9 Effective Bits at 20kHz • No Offset or Gain Adjustments Necessary • Analog and Reference Inputs Fully Buffered Internal high speed CMOS buffers at both the analog and reference inputs simplifies interface requirements. • On-Chlp Track and Hold Amplifier A Track and Hold amplifier is included on the chip. consisting of two high speed amplifiers and an internal hold capacitor. reducing external Circuitry. • I1P Compatible Interface • 2's Complement Data Output • 1S0mW Power Consumption • /883 Version Available Microprocessor bus interfacing is simplified by the use of standard Chip Select. Read. and Write control signals. The digital three-state outputs are byte organized for bus interface to 8 or 16 bit systems. An Out-of-Range pin. together with the MSB bit. can be used to indicate an under or over-range condition. Applications The HI-7153 operates with ±5V supplies. Only a single +2.5V reference is required to provide a bipolar input range from -2.5V to +2.5V. • Only a Single 2.SV Reference Required for a ±2.5V Input Range • Out-of·Range Rag • I1P Controlled Data Acquisition Systems Ordering Information • DSP • Avionics • Sonar PART NUMBER • Process Control • Automotive Transducer Sensing • Industrial • Robotics • Digital Communications Functional Diagram VREF>- (ANALOG GND) Amo". REF AMP REF INVERT AG>---f ... + r-- ..:.. AIN2 >- AMP ±1.0 LSB O"C to +7O"C 40 Lead Plastic DIP HI3-7153A·9 ±1.0 LSB .4Q"C to +85°0 40 Lead Plastic DIP HI1-7153S·2 ±1.0LSB ·5500 to +12500 4OLeadOeramicDlP 33 ~ ·•• I w INPUT BUFFER a: ...... ~ 1 AuI&>- ~ MUX AINS >AtN7>- -·· - ... 00 LATCHES AND OUTPUT BUFFERS • BUS CTRL TRACK HOLD AMP :~ A~~ v+, TEST >- GND>- (DIGITAL GND) TWO STEP FLASH f AtNI>AtN4>- V->- PACKAGE HI3-7153J-5 I'""""""' is AtNl >- LINEARITY TEMPERATURE (MAX JlE) RANGE CONTROL LOGIC POWER SUPPLY DISTRIBUTION DO' _ OVR -< BUS -< HBE ... 1Il5tD -<1m --- HI-7153 Typical Dynamic Performance Characteristics EFFECTIVE NUMBER OF Brrs - -..... 10 ~ ......... o 10 20 ~ 10 """ 5 SIGNAL-TO-NOISE RATIO 30 ........ 40 r--..... 50 I I -- ...... " 55 50 10 45 70 o 20 10 FREQUENCY (kHz) TOTAL HARMONIC DISTORTION -80 -40 o - , -75 ~ 10 20 ~ r-.... i.e& "- "'- 30 40 w !z ~ 50 .. -80 -40 70 o 20 10 30 ..... , 10 ~ " :!. 55 I'\. 50 45 o 40 FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE 40 70 10 -- -45 80 70 I 10 .ao r-- FREQUENCY (kHz) iii' 50 PEAK NOISE -70 ~ 40 ............. ...... FREQUENCY (kHz) -70 ~ 30 r--..... 20 "" 30 40 FREQUENCY (kHz) 7-46 ........ 50 r-10 70 50 10 70 HI-7153 Typical Dynamic Performance Characteristics (Continued) FFT SPECTRUMS o o -10 -20 -30 -10 -20 -30 &1-40 -40 i-..u ~o ~ ~o l!l ::I -60 ~ 5 -70 ... -60 ~ -110 -100 -110 -120 -70 :J -80 -130 t-~--'--'---'--;--1--r-+---'--r ... -110 ~ -100 -110 -120 -130 -140 t--,--,.---,r-...,--..---,--r--r--r-, o 10 20 30 40 50 60 70 80 80 100 FREQUENCY (kHz) NOTES: FREQUENCY (kHz) NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THO: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 4931Hz 200kHz 59.40dB -{)726<18 -75.98dB INPUT FREQUENCY:, 14697Hz SAMPLING RATE: 200kHz SNR: 58.98dB THO: -61.44dB PEAK NOISE: -77 29dB SPURIOUS FREE DYNAMIC RANGE: -63.42dB 3RO HARMONIC: -72.44dB -68.36<18 -77.19dB 12,,, W'W ! Ii:Wz~ , >cc o o -10 -20 -30 -10 -20 -30 &I -40 &1-40 ~ ~o ~..u l!l::I I!l::I -60 5 5 -70 ~ -80 00( -110 -100 -110 -120 -130 Za: Om u:::» ~ en -80 -70 ~ -80' 00(-110 t--'T--.--r-'--,--,.---,-...,--..---,--r FREQUENCY (kHz) NOTES: FREQUENCY (kHz) NOTES: INPUT FREQUENCY: 24462Hz SAMPLING RATE: 200kHz SNR: 58.36dB THO: -55.59dB PEAK NOISE: -76.65dB SPURIOUS FREE DYNAMIC RANGE: -57.72dB 3RD HARMONIC:-64.53dB INPUT FREQUENCY: SAMPLING RATE: SNR: THO: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 7-47 4399Hz 200kHz 58.26dB -48.19dB -74.34dB -48.66dB -62.B7dB I HI-7153 Pin Description DIP PIN SYMBOL 1 VREF Reference voltage Input (+2.50V) 2 AG Analog ground reference (OV) 3 AINO Analog Input channel 0 4 AINI Analog Input channell 5 AIN2 Analog input channel 2 6 AIN3 Analog input channel 3 7 AIN4 Analog Input channel 4 8 AIN5 Analog Input channelS DESCRIPTION DIP PIN SYMBOL DESCRIPTION 21 BUS Bus select input. High =all outputs enabled together 00-09, OVR low =Outputs enabled byHBE 22 HBE Byte select (HBEllBE) Input for 8 bit bus. High =High byte select, DB - 09, OVR Low =low byte select, DO - 07 23 ClK Clock Input. TTL compatible. 24 OG Digital ground (OV) 25 EOC End-of-conversion status. Pulses high at the end-ol-conversion. 26 HOLD Start of conversion status. Pulses low at the start-of-converslon. 9 A1N8 Analog input channel 6 10 ~N7 Analog input channel 7 11 NC No connect or tie to V+ only 27 DO Bit 0 (lSB) Test pin. Connect to OG for normal operation 28 01 Bit 1 Mux address Input. (LSB) Active high. 29 02 Bit 2 Output Mux address Input. (LSB) Active high. 30 03 Bit 3 Data 04 Bit 4 Bits 12 TEST 13 AO 14 AI 15 A2 Mux address input. (MSB) Active high. 31 16 ALE Mux address enable. When high, the latch Is transparent. Address data is latched on the falling edge. 32 05 BitS 33 06 Bit 6 34 07 BII7 35 DB Bit 8 36 09 BII9(MSB) 37 OVR 17 WR Write Input. With CS low, starts conversion when pulsed low; continuous conversions when kept low. 18 CS Chip select input. ActIve low. 19 RO Read input. With CS low, enables output buff· ers when pulsed low; outputs updated at the end of conversion. 20 SMOOE Slow memory mode input. Active high. Out of Range flag. Valid at end of COnversion when output exceeds full scale. 36 V+ Positive supply voltage input (+5.0V) 39 GNO Ground return for comparators (OV) 40 V- Negative supply voltage input (-5.0V) Detailed Description Analog to Digital The HI-7153 is an 8 channel high speed 10 bit AID converter which achieves throughput rates of 200kHz by use of a Two Step Flash algorithm. A pipelined operation has been achieved through the use of switched capacitor techniques which allows the device to sample a new input voltage while a conversion is taking place. The 8 channel multiplexer can be randomly addressed. The HI-7153 requires a single reference input of +2.5V. which is internally inverted to -2.5V, thereby allowing an input range of -2.5V to +2.5V. The ten bits are two's complement coded. The analog and reference inputs are internally buffered by high speed CMOS buffers, which greatly simplifies the external analog drive requirements for the device. Section The HI-7153 uses a conversion technique which is generally called a "Two Step Flash" algorithm. This algorithm enables very fast conversion rates without the penalty of high power dissipation or high cost. A detailed functional diagram is presented in Figure 1. The reference input to the HI-7153 is buffered by a high speed CMOS amplifier which is used to drive one end of the resistor string. Another high speed amplifier configured in the inverting unity gain mode inverts the reference voltage with respect to analog ground and forces it onto the other end of the resistor string. Both reference amplifiers are offset trimmed during manufacturing in order to increase the accuracy of the HI-7153 and to simplify its usage. 7-48 HI-7153 The input voltage is first converted into a 5 bit result (plus Out of Range information) by the flash converter. This flash converter consists of an array of 33 auto-zeroed comparators which perform a comparison between the input voltage and subdivisions of the reference voltage. These subdivisions of the reference voltage are formed by forcing the reference voltage and its negative on the two ends of a string of 32 resistors. The 5 bit result of the first flash conversion is latched into the upper five bits of double buffered latches. It is also converted back into an analog signal by choosing the ladder voltage which is closest to but less than the input voltage. The selected voltage (VTAP) is then subtracted from the input voltage. The residual is then amplified by a factor of 32 and referenced to the negative reference voltage (VSCA 32(VIN - VTAP) + VREF-). This subtraction and amplification operation is performed by a Switched Capacitor amplifier (SCA). The output of the SCA amplifier is between the positive and negative reference voltages and can therefore be digitized by the original 5 bit flash converter (second flash conversion). = The 5 bit result of the second flash conversion is latched into the lower five bits of double buffered latches. At the end of a conversion, 10 bits of data plus an Out of Range bit are latched into the second level of latches and can then be put on the digital output pins. The conversion takes place in three clock cycles and is illustrated in Figure 2. When the conversion begins, the track and hold goes into its hold mode for 1 clock cycle. During the first half clock cycle the comparator array is in its auto-zero mode and it samples the input voltage. During the second half clock cycle, the comparators make a comparison between the input voltage and the ladder voltages. At the beginning of the third half clock cycle, the first most significant 5 bit result becomes available. During the first clock cycle, the SCA was sampling the input voltage. After the first flash result becomes available and a ladder tap voltage has been selected the SCA amplifies the residue between the input and ladder tap voltages. During the next three half clock cycles, while the SCA output is settling to its required accuracy, the comparators go into their auto-zero mode and sample this voltage. During the sixth half clock cycle, the comparators perform another comparison whose 5 bit result becomes available on the next clock edge. Reference Input The reference input to the HI-7153 is buffered by a high speed CMOS amplifier. The reference input range is 2.2V to 2.6V. The reference input voltage should be applied following the application of V+ and V- supplies. ,-----1 D~Jg:R AZ 1+-----------, AZ OVR AO DO BUS HBE SCAZ SCAZ Rom im CONTROL TEST ~ MUX DECODER ALE >-I LATCHES III AD A1 A2 I I LOGIC TRACK BUFFER WR cs SMODE AMP CLJ( EOC v+ v- OND DO FIGURE 1. DETAILED BLOCK DIAGRAM 7-49 HI-7153 Analog MuHlplexer The multiplexer channel assignments are shown in Table 1 and can be randomly addressed. Address inputs AO - A2. are binary coded and are TIUCMOS compatible. During power up the circuit is initialized and multiplexer channel AINO is selected. The multiplexer address is transparent when ALE is high andeS is low. The address data is latched on the falling eclile of the ALE signal. The multiplexer channel acquisition timing (liming Diagrams, Slow Memory Mode) occurs approximately 500ns after the rising edge of HOLD. The multiplexer features a typical break-before-make switch action of 44ns. The timing signals· for the Track and Hold amplifier are generated internally, and are also provided externally (HOLD) for synchronization purposes. All of the intemal amplifiers are offset trimmed during manufacturing to give improved accuracy and to minimize the number of extemal components. If necessary, offset error can be adjusted by using digital post correction. TABLE 1. MULTIPLEXER CHANNEL SELECTION ADDRESS AND CONTROL INPUTS Track And Hold A Track and Hold amplifl8r has been fully integrated on the front end of the AID converter. Because of the sampling nature of this AID converter, the input is required to stay constant only during the first clock cycle. Therefore, the Track and Hold (T/H) amplifier "holds" the input voltage only during the first clock cycle and it acquires the input voltage for the next conversion during the remaining two clock cycles. The high input impedance of the TIH input amplifier simplifies analog interfacing. Input signals up to ±VREF can be directly connected to the AID without buffering. The TIH amplifier typically settles to within 1/4 LSB in 1.5jl.S. The AID output code table is presented in Table 2. CS ALE ANALOG CHANNEL SELECTED 0 0 1 AtNO 1 0 1 AINI 0 0 1 AIN2 A2 A1 AO 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 AtNa AtN4 1 0 1 0 1 Aim 1 1 0 0 1 AtNS 1 1 1 0 1 AIN7 N CONVERSION CLOCK TRACK AND HOLD N+1 CONVERSION ..J 2 --1 HOLDVIN(N) 4 3 L 6 & ....._____________1 HOLDVIN(N+1) TRACK VIN (N+1) COMPARATOR AUTO-ZERO (AZ) SAMPLE RESIDUAL SCA AUTO-ZERO (SCAZ) AMPUFY RESIDUAL SAMPLE VIN (N) INr:~~f+DtJ~ SAMPLE VIII (N+1) -'11""""""""""""""""'11,,,""11"""" --4 VIN (N) DATA FIGURE 2. INTERNAL AOC TIMING DIAGRAM TABLE 2. AID OUTPUT CODE TABLE ANALOG INPUT* LSB = 2(VAEF)I1 024 OUTPUT DATA (2'S COMPLEMENT) =2.500V MSB OVR 9 8 7 6 5 4 3 2 1 LSBO C!:+VAEF 2.500 to V+ (+OVR) 1 0 0 0 0 0 0 0 0 0 0 +VAEF -1LSB 2.49512 (+FuU Scale) 0 0 1 1 1 1 1 1 1 1 1 +1LSB 0.00488 0 0 0 0 0 0 0 0 0 0 1 0 0.000 0 0 0 0 0 0 0 0 0 0 0 -1LSB -0.00488 0 1 1 1 1 1 1 1 1 1 1 -VAEF -2.500 (-Full Scale) 0 1 0 0 0 0 0 0 0 0 0 S -VREF - 1LSB 2.50488 to 1 1 0 0 0 0 0 0 0 0 0 V AEF v- (-OVR) • The voltages listed above are the Ideal centers of each OUlput code shown as a function of Its associated reference voltage. 7-50 HI-7153 Dynamic Performance Microprocessor Interface Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance for one channel of the AID system. A low distortion sine wave is applied to the input of the AID converter. The input is sampled by the AID and its output stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THO. See typical performance characteristics. The HI-7153 can be Interfaced to microprocessors through the use of standard Write, Read, Chip Select, and HBE control pins. The digital outputs are two's complement coded, three-state gated, and byte organized for bus interface with 8 and 16 bit systems. The digital outputs (DO - 09, OVR) may be accessed under control of BUS, byte enable input HBE, chip select, and read inputs for a simple parallel bus interface. The microprocessor can read the current data in the output latches in typically 60nslbyte (tRO)' An over-range pin (OVR) together with the MSB (09) pin set to either a logic 0 or 1 will indicate a positive or negative over-range condition respectively. All digital output buffers are capable of driving one TIl load. The multiplexer can be interfaced to either multiplexed or separate address and data bus systems. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured rms signal to rms sum of noise at a specified input and sampling frequency. The noise is the rms sum of all except the fundamental and the first fIVe harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR (6.02N + 1.76)dB. For an ideal 10 bit converter the SNR is 62dB. Differential and integral linearity errors will degrade SNR. = SNR = 1010 Sinewave Signal Power g Total Noise Power Signal-To-Noise + Distortion Ratio SINAD is the measured rms signal to rms sum of noise plus harmonic power and is expressed by the following. SINAD = 101 Sinewave Signal Power og Noise + Harmonic Power (2nd thru 6th) Effective Number of Bits The effective number of bits (ENOB) is derived from the SINADdata; ENOB = SINAD-1.76 6.02 Total Harmonic Distortion The total harmonic distortion (THO) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. THO = 101 Total Harmonic Power (2nd - 6th harmonics) og Sinewave Signal Power Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) Is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. It is usually determined by the largest harmonic. However, if the harmonics are buried in the noise floor it is the largest peak. SFDR = 1010 Sinewave Signal Power g Highest Spurious Signal Power Clock The clock Input is TIl compatible. The converter will function with clock inputs between 10kHz and 800kHz. The HI-7153 can be interfaced to a microprocessor using one of three modes: slow memory, fast memory, or DMA mode. Slow Memory Mode In slow memory mode, the conversion will be initiated by the microprocessor by selecting the chip (CS) and pulsing WR low. This mode is selected by hardwiring the SMODE pin to V+. Note that the converter will change to the DMA interface mode if the WR to RD active timing is less than 100ns. The end-of-conversion (EOC) output signals an interrupt for the microprocessor to jump to a read subroutine at the end of conversion. When the 8 bit bus operation is selected, high and low byte data may be accessed in either order. An I/O truth table is presented in Table 3 for the slow memory mode of operation. Fast Memory Mode The fast mem~ mode of operation is selected by tying the SMODE and WR pins to DG. In this mode, the chip performs continuous conversions and only CS and RD are required to read the data. Whenever the SMODE pin is low, WR is independent of CS in starting a conversion cycle. During the first conversion cycle, HOLD follows WR going low. HOLD will be one clock period wide for subsequent conversion cycles. Data can be read a byte at a time or all 11 bits at once. When the 8 bit bus operation Is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode of operation. The conversion data can be read after HOLD has gone low. An I/O truth table is presented in Table 4 for the fast memory mode of operation. DMAMode This is a hardwired mode where the HI-7153 continuously converts. The user implements hardware to store the results in memory, bypassing the microprocessor. This mode is r&COQ!!!.zed by the chip when SMODE is connected to V+ and CS, RD, WR are connected to DG. When 8 bit bus operation is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode. The conversion data can be read approximately 300ns after HOLD has gone low. An VO truth table Is presented in Table 5 for the DMA mode of operation. 7-51 HI-7153 TABLE 3. SLOW MEMORY MODE 110 TRUTH TABLE ($MODE. V+) FUNCTION HBE ALE X X X Initiates a conversion. X X 1 Selects mux channel.: Addreas data Is latched on failing edge of 'ALE. LaEh X X X Disables aU chip commands. 0 1 X Enables DO - 09 and OVA. 0 X 0 0 0 X X 0 X 0 0 1 X High byte enable: DB - 09, OVR X X 1 X X X DIsables all outputs (high Impedance). CS WR RD 0 0 X 0 X X 1 X X 0 X BUS Is transparent when ALE Is hIgh~ Low byte enable: DO - 07 x =Don't Care TABLE 4. FAST MEMORY MODE 110 TRUTH TABLE (SMODE. 00) cs WR RD BUS HBE ALE 0 0 X X X X Continuous conversion, WR may be tied to 00. 0 X X X X 1 Selects mux channel. Address data Is latched on failing edge of AlE. LaEh Is transparent when AlE Is high. FUNCTION 1 X X X X X Disables all chip commands. 0 X 0 1 X X .Enables DO - 09 and OVA. 0 X 0 0 0 X Low byte enable: DO - D7 0 X 0 0 1 X High byte enable: DB - 09, OVR X X 1 X X X Disables all outputs (high Impedance). X= Don'tC8re TABLE 5. DMA MODE 110 TRUTH TABLE (SMODE .. V+, CS = WR = RD =00) BUS HBE ALE FUNCTION X X 1 Selects mux channel. Address data Is latched on failing edge of ALE. Latch Is transparent when AlE is high. 1 X X Enables DO - 09 and OVA. 0 0 X Low byte enable: DO • 07 0 1 X High byte enable: D8 - 09, OVA X =Don't Care Optimizing System Performance The HI-7153 has three ground pins (AG, 00, GND) .for improved system accuracy. Proper grounding and bypassing is illustrated in Figure 3. The AG pin Is a ground pin and is used intemally as a reference ground. The reference input and analog input should be referenced to the analog ground (AG) pin. The digital inputs and outputs should be referenced to the digital ground (00) pin. The GND pin Is a retum point for the supply current of the comparator array. The comparator array is designed such that this current Is approximately constant at ali times and does not vary with input vo~age. By virtue of the switched capacitor nature of the comparators, It is necessary to hold GND firmly at zero volts at all times. Therefore, the system ground star connection should be located as close to this pin as possible. As in any analog system, good supply bypassing is necessary In order to achieve optimum system performance. The power supplies should be bypassed with at least a 201JF tantalum and a O.1I.1F ceramic capacitor to GND. The reference input should be bypassed with a O.1I.1F ceramic capacitor to AG. The capacitor leads should be as short as possible. The pins on the HI-7153 are arranged such that the analog pins are well isolated from the digital pins. In spite of this arrangement, there is always some pin-tOopin coupling. Therefore the analog inputs to the device should not be driven from very high output Impedance sources. PC board layout should screen the analog and reference inputs with guard rings on both sides of the PC board, connected to AG. Using a solder mask is good practice and helps reduce leakage due to moisture contamination on the PC board. 7-52 HI-7153 Applications Figure 4 illustrates an application where the HI-7153 is used to form a multi·channel data acquisition system. Either slow memory or fast memory modes of operation can be selected. Fast memory mode should be selected for maxi· mum throughput The output data is configured for 16 bit bus operation in these applications. By tying BUS to DG and connecting the HBE input to the system address decoder. the output data can be configured for 8 bit bus systems. ANALOG INPUT ) o SMODE FIGURE 3. GROUND AND POWER SUPPLY DECOUPUNG ADDRESS BUS I I ADDRESS DECODER L.......- >-- AO·A2 I a YREF I I MICROPROCESSOR WR SIG NAL GND AG +5\/>-.fN>-- Y+ Y· DG ....fa !i: :c RD ALE EOC GND TEST ---< eLK 600kHz I DO· De, OYR 8 BIT DATA BUS FIGURE 4. MULTI-CHANNEL DATA ACQUISITION SYSTEM 7-53 I DATA ACQUISITIO_ 8 CIA CONVERTERS PAGE D/A CONVERTERS SELECTION GUIDES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 D/A CONVERTERS DATA SHEETS AD7520, AD7530, AD7521, AD7531 1a-Bit, 12-Bit Multiplying D/A Converters ........................................... . 8-5 AD7523, AD7533 8-Bit Multiplying D/A Converters .................................................. . 8-13 AD7541 12-Bit Multiplying D/A Converter .................................................. . 8-21 AD7545 12-Bit Buffered Multiplying CMOS DAC ............................................ . 8-28 CA3338, CA3338A CMOS Video Speed 8-Blt R2R D/A Converter ..................................... . 8-35 HI-565A High Speed Monolithic D/A Converter with Reference ................................. . 8-42 HI-DAC80V, HI-DAC85V 12-Bit, Low Cost, Monolithic D/A Converter ......................................... . 8-50 HI1171 8-Blt, 40MSPS High Speed D/A Converter ........................................ . 8-57 H120201, HI20203 1018-Blt, 160MSPS Ultra High Speed D/A Converter ................................ . 8-65 NOTE: Bold Type Designates a New Product from Harris. 8-1 DIGITAL TO ANALOG CONVERTERS (NOTES 2, 3) DEVICE SUFFIX CODES MIL SPEC SETTLING TIME TECHNOLOGY (Il s ) INL LSB DNL LSB ±1/2 Monotonic 200 Max CMOS-JI 20Typ CMOS-SOS MULTIPLYING OUTPUT IN INPUT BUFFER REFERENCE X I No ~External V Yes External FEATURES 8-BITCMOS AD7523J N 7 - 4/ 7 - 8/ AD7523K AD7523l HIGH SPEED 8-BIT CA3338A D M ±3/4 ±1/2 M ±1 ±3/4 ±1.3 ±1/4 8-Bit Video Speed, low Glitch E CA3338 D en CD CD E HI1171 JCB 25 Typ CMOS I Yes External 8-Bit Video Speed, low Glitch, low Power, low Cost, 40 MSPS OJ '" HI20203 JCB ±1 ±1/2 4.3 Typ CMOS Yes I Yes External 8-Bit 160MHz D/A with ECl Inputs,low Glitch, low Power JCP _. ~ o ::J G') t: _. HIGH SPEED 10-BIT HI5721 BIB BIP ±0.5 ±0.5 4.5ns BiCMOS Yes I Yes Internal 10-Bit, 125MHz, low Glitch, low Power, TTL/CMOS Inputs HI20201 JCB ±1 ±1/2 5.2 Typ CMOS Yes I Yes External 10-Bit 160MHz D/A with ECl Inputs, low Glitch, low Power HI3050 JCQ ±2 ±1/2 I Yes External Triple DAC, 50 MHz JCP CMOS ------ - a. CD DIGITAL TO ANALOG CONVERTERS (Continued) (NOTES 2, 3) DEVICE SUFFIX CODES MIL SPEC INL LSB DNL LSB SETTLING TIME TECHNOLOGY (Il s ) MULTIPLYING OUTPUT INPUT IN BUFFER REFERENCE FEATURES 10-BITCMOS AD7520J D AD7520J N AD7520K D AD7520K N - ±1 AD7520L D '"":1/ - 2 AD7520L N '"":1/ AD7520S D ±2 500 Typ r--±2 CMOS-JI X I No External Full Input Static Protection r--±1 - AD7520SD/883B en - CD CD 2 ±2 (') CD W AD7520T D AD7520U D AD7530J N AD7520UD/883B ~ ±1/2 ±2 AD7530K - ±1 AD7530L -.;;; AD7533J o-. ±1 - N 500 Typ X I No Full Input Static Protection External _. s:: ±2 800 Max CMOS-JI I X No Full Input Static Protection External CD '0 o a ---::- :;" ±1/2 AD7533L ::l G) c. 2 - ±1 AD7533K CMOS-JI s:: C1> ~ 12-BITCMOS HI3-DAC80V -5 HI3-DAC85V -4, -9 H11-565AJD -5 H11-565AKD H11-565ASD H11-565ATD -2 ±1/2 ±3/4 ±1/2 ±1/2 H11-565ASD/883 ±1/2 ±3/4 H11-565ATD/883 ±1/4 ±1/2 ±1/2 ±3/4 ±1/4 ±1/2 1.5 Max Bipolar V No Internal 0.5 Typ Bipolar-DI I No Internal -- DJA CONVERTERS .- -- Low Cost, Internal Op Amp - -_._- -------- DIGITAL TO ANALOG CONVERTERS (NOTES 2, 3) DEVICE AD7521J SUFFIX CODES MIL SPEC N (Continued) INL LSB DNL LSB ±B SETTLING TIME (flS) TECHNOLOGY MULTIPLYING OUTPUT IN INPUT BUFFER REFERENCE 0.5 Typ CMOS-JI X I No External 0.5 Max CMOS-JI X I No External 1.0 Max CMOS-JI X I No External en !eo (I) External o ::s r--±4 AD7521K FEATURES f---AD7521L AD7531J ±2 ±B N r--±4 AD7531K f---AD7531L AD7541J AD7541K 7 - 2! AD7541L ±1/2 ±2 ±4.0 ±1 ±1.0 .i>. AD7545J ±2 ±4.0 AD7545K ±1 ±1.0 N _._--- _. g, Monotonic AD7545B AD7545A CD ±2 ±1 N 2.0 Max CMOS-JI X I Yes C) t: Co _. (I) '0 o aS" I: <11 E:: AD7520, AD7530 AD7521, AD7531 10-Bit, 12-Bit Multiplying CIA Converters December 1993 Features Description • AD75201AD7530 10 Bit ResolutlO.1; 8, 9 and 10 Bit Linearity The AD75201AD7530 and AD7521/AD7531 are monolithic, high accuracy, low cost H)·bit and 12-bit resolution, multiplying digital-ta-analog converters (DAC). Harris' thinfilm on CMOS processing gives up to 1D-bit accuracy with TTUCMOS compatible operation. Digital inputs are fully protected against static discharge by diodes to ground and positive supply. • AD7521/AD7531 12 Bit Resolution; 8,9 and 10 Bit Linearity • Low Power Dissipation of 20mW (Max) • Low Nonlinearity Tempco at 2ppm of FSR/"C • Current Settling Time 1.01lS to 0.05% of FSR • ±5V to +15V Supply Voltage Range Typical applications include digitaVanalog Interfacing, multiplication and division, programmable power supplies, CRT character generation, digitally controlled gain circuits, integrators and attenuators, etc. • TTUCMOS Compatible • Full Input Static Protection • 1883B Processed Versions Available The AD7530 and AD7531 are identical to the AD7520 and AD7521, respectively, with the exception of output leakage current and feedthrough speCifications. Ordering Information NONLINEARITY TEMPERATURE RANGE AD7520JN, AD7530JN 0.2% (8-8it) O"C to +70"C 16 Lead Plastic DI P AD7520KN,AD7530KN 0.1 % (9-8it) O"C to +70"C 16 Lead Plastic DIP AD7521JN, AD7531JN 0.2% (8-Bit) O"C to +70"C 18 Lead Plaslic DIP AD7521KN,AD7531KN 0.1 % (9-Bil) O"C 10 +70"C 18 Lead Plastic DIP AD7520LN,AD7530LN 0.05% (lO-Bil) -40"C 10 +85°C 16 Lead Plastic DIP AD7521LN, AD7531LN PART NUMBER PACKAGE 0.05% (lO-Bit) -4O"C 10 +85°C 18 Lead Plaslic DIP AD7520JD 0.2% (8·Bil) -25°C 10 +85°C 16 Lead Ceramic DIP AD7520KD 0.1% (9·Bit) ·25°C 10 +85°C 16 Lead Ceramic DIP AD7520LO 0.05% (lO-BII) ·250 C 10 +85°C 16 Lead Ceramic DIP AD7520SD, AD7520SD/883B 0.2% (8·Bit) -5500 10 +125"C 16 Lead Ceramic DIP AD7520TD 0.1% (9·Bit) -5500 10 +125"C 16 Lead Ceramic DIP 0.05% (lO-Bit) -550 C to + 125°C 16 Lead Ceramic DIP AD7520UD, AD7520UD/883B (/) a: ~ w > z o C.J ~ C Pinouts AD7520, AD7530 (CDIP, PDIP) TOP VIEW AD7521, AD7531 (PDIP) TOP VIEW IOUT1 1 RFEEDBACK Bill (MSB) 4 CAUTION: These dovices are sensHive to electrostatic discharge. Users should follow proper I.e. Handling Procedures. Copyright@Harrls Corporation 1993 8-5 File Number 3104 Specifications AD7520, AD7530, AD7521, AD7531 Absolute Maximum Ratings Therm'al Information Supply Voltage 01+ to GND) •••••.••••••••.••••.••••••• +17V VREF •••....••••••.•••••.••••.••••••••••••••••••••••.•• ±25V Digital Input Voltage Range •••••••••.••••••••••••• V+ to GND Output Voltage Compliance •••••••••••••••••••• -loomV to V+ Storage Temperature •••.••••••••••••••••••• -650 C to +1 SOOC Lead Temperature (Soldering lOs) •••..•.••.•.••..••••• 300°C Thermal Resistance 8JA 8JC 16 Lead Plastlc DIP •••••••••••.••.• ; l00"C/W 18 Lead Plastic DIP •.••••••••••••.•• 9O"C/W 800 C/W 24OC/w 16 Lead Ceramic DiP •••••••••.••••• Maximum Power Dissipation Up to +750 C ••.••••••••••••••••••••••••.•••••••• 450mW Derate Above +75OC at 6mWfC Operating Temperature JN, KN, LN Versions ••••••••••••••••.•••.••• OOC to +700C JD, KD, LD Versions ••••••••••••••••••••••• -25°C to +85°C SO, TD, UD Versions ••••..••.••••••••••••. -55°C to +1250 C CAUTION: Strsssss abo"" those listed in "Absolute Maximum Ratings" may cause permanent damage to the daviee. This is a stress only lilting and opellltion of the dlilVice at these or any other conditions abo"" those indicated In the opellltional sections of this specification is not Implied. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fi6/ds. Keep unused units in conductive foam at all times. Do not apply voltagss higher then VDD or IBss than GND potential on any terminal except VREF and RFEEDBACK. Electrical Specifications V+ =+15V, VREF =+10V, TA =+25 C Unless Otherwise Specified 0 AD75201AD7530 AD75211AD7531 I MIN I MIN I TYP 10 10 10 12 12 12 Bits - - ±0.2 (8-Bit) - - ±0.2 (8-Bit) %01 FSR - - ±0.1 (9-Bil) - - ±0.1 (9-Bit) %01 FSR - - ±0.05 (10-Bit) - - ±C.05 (10-Bit) %01 FSR - - ±2 - ±0.3 - Over the Specified Temperature Range - - Output Current Settling Time To 0.05% 01 FSR (All Digital Inputs Low To High And High To Low) (Note 3) (Figure 7) - Feedthrough Error VREF = 20Vp.p, 10kHz (50kHz) All Digital Inputs Low (Note 3) (Figure 6) PARAMETER TEST CONDITIONS MAX TYP MAX UNITS SYSTEM PERFORMANCE (Note 1) Resolution Nonlinearity J,S S Over -55°C to +125°C (Notes 2, 5) (Figure 2) K,T T Over -55°C to +125°C (Figure 2) L,U -10VSVREF S+l0V U Over -55°C to +125°C (Figure 2) Nonlinearity Tempeo - ±2 ppm 01 FSRfC - - ±C.3 - %01 FSR ±10 - - ±10 ppm 01 FSRfC ±200 (±300) - - ±200 (±300) nA 1.0 - - 1.0 - jIS - - 10 - - 10 mVp_p All Digital Inputs High loun at Ground 5 10 20 5 10 20 kO All Digital Inputs High (Note 3) (Figure 5) - 200 - - 200 - - 75 All Digital Inputs Low (Note 3) (Figure 5) - 75 -10V S VREF S +10V (Notes 2, 3) Gain Error Gain Error Tempeo Output Leakage Current (Either Output) , DYNAMIC CHARACTERISTICS REFERENCE INPUT Input Resistance ANALOG OUTPUT Output Capacitance IIoUT1 IOUT2 loun ~ IOUT2 - 8-6 200 - - - - 75 - pF pF 75 - pF 200 - pF Specifications AD7520, AD7530, AD7521, AD7531 Electrical Specifications V+ =+15V, VREF =+10V, TA =+25°C Unless Otherwise Specified (Continued) AD7521/AD7531 AD75201AD7530 PARAMETER TEST CONDITIONS Output Noise MIN TYP MAX MIN - Equivalent to 10kn - - - - Both Outputs (Note 3) (Figure 4) TYP MAX UNITS Equivalent tol0kn - Johnson Noise 0.8 V DIGITAL INPUTS Low State Threshold, VIL Over the Specified Temperature Range VIN OV or +15V High State Threshold, VIH = - - 2.4 - - ±1 - Input Current, IlL' IIH Input Coding See Tables 1 & 2 - - 0.8 2.4 - - V ±1 IIA ±0.OO5 - % FSR/% I!N+ Binary/Offset Binary POWER SUPPLY CHARACTERISTICS - = Power Supply Rejection V+ 14.5V to 15.5V (Note 2) (Agure 3) Power Supply Voltage Range ±0.005 - - +5 to +15 1+ Total Power Dissipation - ±1 - - ±1 - IIA All Digital Inputs High or Low Excluding Ladder Network - - 2 - - 2 mA Including the Ladder Network - 20 - - 20 - mW NOTES: 1. Full scale range (FSR) is 10V for Unipolar and ±1 OV for Bipolar modes. 2. Using internal feedback resistor RFEEDBACK. 3. Guaranteed by design, or characterization and not production tested. 4. Accuracy not guaranteed unless outputs at GND potential. 5. Accuracy Is tested and guaranteed at V+ =15Vonly. Functional Diagram 10kn VREF 20kn SPOT NMOS SWITCHES V +5 to +15 All Digital Inputs at OV or V+ Excluding Ladder Network 10kn 20kn (l 1 10kn .. 10kn 20kn 20kn 20kn 20kn -=.E=" GND Y ! r'! y r'! Y II i 6 6 MSB BIT 2 II ! f 1 Y rY 1 loun 1our1 10kn BIT 3 RFEED8ACK Switches shown for Digital Inputs "High". Resistor values are typical. 8-7 AD7520, AD7530, AD7521, AD7531 Pin Descriptions AD7520130 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD7521131 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN NAME DESCRIPTION Current Out summing junctlQll of the R2R ladder network. loun Current· Out virtual ground. return path for the R2R ladder network' IOUT2 Digital Ground. Ground potential for digital side of DlA. GND Bils l(MSB) Most Significant Digital Data Bit Bit 2 Digital Bit 2 Bit 3 Digital Bit 3 Bit 4 Digital Bit 4 Bit 5 Digital Bit 5 Bit 6 Digital Bit 6 Bit 7 Digital Bit 7 Bit 8 Digital Bit 8 Bit 9 Digital Bit 9 Bit 10 Digital Bit 10 (AD7521J31). Least Significant Digital Data Bit (AD7520130) Bit 11 Digital Bit 11 (AD7521J31) Bit 12 Least Significant Digital Data Bit (AD7521J31) Power Supply +5 to +15 Volts V+ VREF Voltage Reference Input to set the output range. Supplies the R2R resistor ladder. RFEEDBACK Feedback resistor used for the current to voltage conversion when using and external OP-Amp. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best straight line" through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of Z-N of the full-scale range. e.g. Z-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settie to within specified error band around its final value (e.g. 1/2 LSB) for a given digital input change. I.e. all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full-scale range. I.e. all digital inputs at HIGH state. It is expressed as a percentage of full-scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to loun with all digital inputs LOW. power TTUCMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuH of the DAC is shown In the Functional Diagram. The NMOS SPOT swHches steer the ladder leg currents between lcun and 10UT2 buses which must be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuHs are comprised of three inverters wHh positive feedback from the output of the second to the first. see Figure 1. This configuration results in TTUCMOS compatible operation over the full military temperature range. With the ladder SPOT switches driven by the level shifter. each switch is binarily weighted for an ON resistance proportional to the resPective ladder leg current This assures a constant voltage drop across each switch. creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents. Output CapaCitance: CapaCitance from loun. and IOUT2 terminals to ground. v+ Output Leakage Current: Current which appears on loun. terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. .~ DTLlTTU .. ~ Detailed Description CMOS INPUT The AD7520. AD7530. AD7521 and AD7531 are monolithic. multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPOT switches form the basis of the converter circuit. 'CMOS level shifters permit low 8-8 r'1~' * II... • f- ~ I~.( rl~6 H~8 49 49 s ~ FIGURE 1. CMOS SWITCH TO LADDER ~ 1 , Ioun louT1 AD7520, AD7530, AD7521, AD7531 Test Circuits The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531. UNGROUNDED SINE WAVE GENERATOR 400Hz 1.0Vp.p SKO.Ol% 10 BIT BINARY COUNTER +10V V REF .nn. CLOCK 500kn BIT 1 (MSB) BIT10 ! (LSB) FIGURE 2. NONLINEARITY FIGURE 3. POWER SUPPLY REJECTION +IIV (ADJUST FOR VOUT =OV) +15V l.lkHz BW.1Hz NC +15V +15V QUAN TECH MODELI34D .....,~V, .... O~UT.... 1mY;'"'" AN~~~ER 14 16 NC = FIGURE 4. NOISE VREF = 20Vp.p 100kHz SINE WAVE FIGURE 5. OUTPUT CAPACITANCE +15V ·10V VREF 51: I%SETTUNG(lmV) EXTRAPOLATE 81: 0.03% SETTUNG I=RlSEllME +15V BI11 (MSB) BIT 1 (MSB) 16 AD7520 , +~~.IUUl.. ~ IOUTl IOUT2 ~~~ -~iiLS~1!~~~ BIT 10 (LSB) - BIT 10 (LSB) - - - FIGURE 6. FEEDTHROUGH ERROR FIGURE 7. OUTPUT CURRENT SETTLING TIME 8·9 AD7520, AD7530, AD7521, AD7531 "Digital Input Code/Analog Output Value" table for bipolar mode is given in Table 2. Applications Unipolar Binary OpereUon +15V The circuit configuration for operating the AD7520 in unipolar mode is shown in Agure 8. Similar circuits can be used for AD7521, AD7530 and AD7531. With positive and nega· tive VREF values the circuit is capable of 2·Quadrant multipli· cation. The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 1. +15V BIT 1 (MSB) DIGITAL ! FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPUCATION) VOUT INPUT! 0-:--_.
TABLE 2. BIPOLAR (OFFSET BINARy) CODE TABLE BIT10 (LSB) DIGITAL INPUT ANALOG OUTPUT -VREF (1_2-(N.l) FIGURE 8. UNIPOLAR BINARY OPERATION (2·QUADRANT MULTIPUCATION 1111111111 1000000001 -VREF (2-(N.1) TABLE 1. CODE TABLE· UNIPOLAR BINARY OPERATION 1000000000 0 0111111111 VREF (2-(N.l~ DIGITAL INPUT ANALOG OUTPUT .VREF (1.2-N) 1111111111 1000000001 ·VREF (1/2 + 2·N) 1000000000 ·VREF2 0111111111 ·VREF (1/2 0000000001 .VREF (2· N) 0000000000 0 ·:rN) = Zero Offset Adjustment 2. N N = 1. Connect all digital Inputs to GND. 2. Adjust the offset zero adjust trim pot of the output opera· tional amplifier for OV at VOUT' Gain Adjustment =10 for 7520, 7521 =12 for 7530,7531 = 0'" Offset Adjustment 1. Adjust VREF to approximately + 1OV. 2. Connecl all digital inputs to "Logic 1". 1. Connect all digital inputs to V+. = 0000000000 A "Logic 1" input at any digital Input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A "Logic CJ' input forces the bit current to 10UT2 bus. For any code the 10UT1 and IOUT2 bus currents are complements of one another. The current amplifier at 10UT2 changes the polarity of IOUT2 current and the transconduclance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB "Logic 1", All other bits "Logic is corrected by using an external resistor, (10MO), from VREF to 10UT2. 1. LSB 2-N VREF 2. N 10 for 7520, 7530 N = 12 for 7521, 7531 2. Monitor VOUTfor a ·VREF (1.2"N) reading. (N AD7520130 and N 12 for AD7521131). VREF (1_2-(N.l) V REF NOTES: 1. LSB = 2-(N.l) VREF NOTES: = 0000000001 3. Adjust IOUT2 amplifier offset adjust trim pot for OV ±1 mV at 10UT2 amplifier output. =10 for 4. Connect MSB (Bit 1) to "Logic 1" and all other bits to "Logic a'. 3. To decrease VOUT, connect a series resistor (0 to 2500) between the reference voltage and the VREF terminal. 5. Adjust 10lIT1 amplifier offset adjust trimpot for OV ±1 mV at Voor 4. To increase VOUT, connect a series resistor (0 to 2500) in the IOUT1 amplifier feedback loop. Gain Adjustment Bipolar (Offset Binary) Operation 2. Monitor VOUT for a ·VREF (1_2.!N.1) volts reading. (N 10 for AD7520 and AD7530, and N =12 for AD7521 and AD7531). 1. Connecl all digital inputs to V+. = The circuit configuration for operating the AD7520 in the bipolar mode is given in Figure 9. Similar circuits can be used for AD7521, AD7530 and AD7531. Using offset binary digital input codes and positive and negative reference volt· age values, 4·Quadrant multiplication can be realized. The 3. To increase VOUT, connecl a series resistor of up to '2500 between VOUT and RFEEDBACK' 4. To decrease VOUT, connecl a series resister of up to 2500 between the reference voltage and the VREF terminal. 8·10 AD7520, AD7530 Die Characteristics DIE DIMENSIONS: 101 x 103mils (2565 x 2616micrms) METALLIZATION: Type: Pure Aluminum Thickness: 10± 1kA GLASSIVATION: Type: PSG/NITRIDE PSG: 7 ± 1.4kA NITRIDE: 8 ± 1.2kA PROCESS: CMOS Metal Gate Metallization Mask Layout AD7520. AD7530 PIN? BIT 4 PIN & BIT 3 PINS BIT 2 PIN 4 BIT 1 (MSB) PIN 3 GND PIN 2 PIN I BITS lour2 PIN 1 IOUT1 PINg BIT & PIN 10 BIT 7 PIN 1. RFEEDBACK PIN 11 BIT I PIN 1S VAEF PIN 14 V+ PIN 12 BIT9 PIN 13 BIT 10 (LSB) NC 8-11 NC AD7521, AD7531 Die Characteristics DIE DIMENSIONS: 101 x 103mils (2565 x 2616micrms) METALLIZATION: Type: Pure Aluminum Thickness: 10± 1kA GLASSIVATION: Type: PSG/NITRIDE PSG: 7± 1.4kA NITRIDE: 8 ± 1.2kA PROCESS: CMOS Metal Gate Metallization Mask Layout AD7521, AD7531 PIN 7 BIT 4 PINS BIT 3 PINS BIT 2 PIN 4 BIT 1 (MSB) PIN 3 GND PIN 2 PIN a BITS 1oUT2 PIN1 IoUT1 PINS BIT 6 PIN 10 BIT 7 RFEEDBACK PIN 11 BIT PIN 17 a VAEF PIN 16 V+ PIN 12 BITS PIN 13 BIT10 PIN 14 BIT 11 8-12 PIN 15 BIT12 (LSB) AD7523, AD7533 8-Bit Multiplying D/A Converters December 1993 Features Description • 8,9 and 1()"Blt Unearlty The AD7523 and AD7533 monolithic, low cost, high performance, 8-bit and 10-bit accurate, multiplying digital-to-analog converter (DAC), in a 16 pin DIP. • Low Gain and Unearlty Temperature Coefficients • Full Temperature Range Operation Harris' thin film resistors on CMOS circuitry provide 10-bit resolution (8, 9 and 10-bit accuracy), with TTUCMOS compatible operation. • Static Discharge Input Protection • TTUCMOS Compatible The AD7523 and AD7533s accurate four quadrant multiplication, full military temperature range operation, full input protection from damage due to static discharge by clamps to V+ and GND, and very low power dissipation make it a very versatile converter. • +5V to +15V Supply Range • Fast Settling Time: 150ns Max at +25°C • Four Quadrant Multiplication Low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD7523 and AD7533. • AD7533 Direct AD7520 Equivalent Ordering Information PART NUMBER NONLINEARITY TEMPERATURE RANGE 02% (8-Bit) O"C to +70"C 16 Lead Plaslic DIP AD7523KN, AD7533KN 0.1% (9-8il) O"C 10 +70"C 16 Lead Plaslic DIP AD7523LN,AD7533LN 0.05% (10-Bil) O"C 10 +70"C 16 Lead Plastic DIP AD7523JN, AD7533JN PACKAGE U) II: ~ W > Z Pinout o o Functional Block Diagram AD7523. AD7533 (CDIP. PDIP) TOP VIEW 10k!} 10k!} c~ 10k!} 10k!} (15) 20k!} 20k!} 20k!} =(3) BIT 1 (MSB) 4 BITZ :~ SWITCHES ---+,---'"ii----ll--......- - -.... L+, i ---O i o " MSS (4) BIT 2 (5) ~~ Ioun (1) : " BIT 3 (6) RFEEDBACK (16) NOTE: 1. NC for AD7523 only. Switches shown for digital inputs "High" CAUTION: These devices are sansHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright@ Harris Corporation 1993 8-13 File Number 3105 Specifications AD7523, AD7533 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to GNo) ••••••••••••••••••••.•••••• +17V VREF •••.••..•••••••••••••••••••.•••••.••.••••••••••••• ±2SV Digital Input Voltege Range •••.••.•••••••••••••••• V+ to GNo Output Voltege Compliance •••• , ••••••••••••••• -l00mV to V+ Storage Temperature •••••••••••••••.••••••• -65°C to +150°C Lead Temperature (Soldering lOs) •.•••••••••••••••••• +300oC Thermel Resistence 8JA Plastic DIP Package ••••••••••••••••••••••••••• lOOOC1W Operating Temperature IN, KN, LN Versions •••••••••••••••••••••••• O"C to +70"C CAUTION: StrBssss abo"" thos8 listed In "Absolute Maximum Ratings" may cause psrmanent damage to the device. This is a stress only rating and operation of the dwice at /hess or any other conditions _ those Indicated In the operational sections of this specifICStion is not implied. Electrical Specifications v+ =+lSV, VREF =+10V, VOUT1 =VOUT2 =ov, Unless Otherwise Specified AD7533 AD7523 TA +2SoC PARAMETER TEST CONDITIONS TAMIN-MAX TA+25°C TAMIN-MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS B - B - 10 - 10 - Bits - ±0.2 - ±D.2 - ±0.2 - ±D.2 %01 FSR - ±0.1 - ±D. 1 - ±D.l ±0.1 %01 FSR - ±O.OS - ±O.OS - ±D.OS - ±D.OS %01 FSR SYSTEM PERFORMANCE Resolution Nonlinearity J -K,T -10VSVRE FS+l0V VOUT1 VOUT2 OV (Note 1, 2, S) = = -L Monotonlcity Gain Error All olgitellnputs High (Note 2) Nonlinearity Tempco -10V S VREF S + 10V (Notes 2,3) Gain Error Tempeo Output Leakage Current (Either Output) Guaranteed Guarantead VOUT1 =VOUT2 =0 - ±l.S - ±l.B - ±1.4 - ±l.B %01 FSR - ±2 - ±2 - ±2 - ±2 ppm of FSRI"C - ±10 - ±10 - ±10 - ±10 ppm 01 FSRI"C - ±oo - ±200 - ±SO - ±200 nA - ±0.02 - ±0.03 - ±D.OOS - ±O.OOB %01 FSRI% oflN+ - lS0 - 200 - 600 - BOO ns - ±1/2 - ±1 - ±D.OS - ±0.1 LSB S DYNAMIC CHARACTERISTICS = Power Supply Rejection V+ 14.0V to lS.0V (Note 2) Output Current Settling lime To 0.2% 01 FSR, RL 1000 (Note 3) Feedthrough Error VREF 2OVpp, 200kHz Sine Wave, All olgltel Inputs Low (Note 3) = = REFERENCE INPUTS Input Resistance (Pin lS) Temperature Coefficient All Dlgitellnputs High IOUT1 at Ground (Note 3) - S - 20 - 20 -500 - -SOO S - 8-14 - - S - kG 20 - 20 kG -300 - -300 ppmfOC AD7523, AD7533 Electrical Specifications V+ = +15V, VREF = +10V, VOUTl = VOUT2 = OV, Unless Otherwise Specified (Continued) AD1533 AD1523 TA+25°C PARAMETER TEST CONDITIONS TAMIN-MAX TA+2SOC TAMIN-MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS - 100 100 - 100 - 100 pF - 30 30 - 35 - 35 pF 30 - 35 - 35 pF 100 - 100 pF ANALOG OUTPUT - 30 - - 100 - 100 Low Slate Threshold, V1L - 0.8 - 0.8 - 0.8 - 0.8 V High State Threshold, V1H 2,4 - 2,4 - 2.4 - 2.4 - V - ±1 - ±1 - ±1 - ±1 I'A 4 pF Output Capacilance ~ COUT2 All Digilallnputs High (Note 3) COUTl All Dlgilallnputs Low (Note 3) OUT2 -C DIGITAL INPUTS Input Current (Low or High), 'IL"IH Input Coding See Tables 1 & 3 Input Capacilance (Note 3) V1N =OVor+15V Binary/Offset Binary - 4 - Binary/Offset Binary 4 - 4 - POWER SUPPLY CHARACTERISTICS Power Supply Vollage Range (NoteS) 1+ All Digilallnputs High or Low (Excluding Ladder Network) - 2 - V +5 to +16 +5 to +16 2.5 - 2 - 2.5 rnA NOTES: 1. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes. 2. Using intemal feedback resistor, RFEEDBACK. 3. Guaranteed by design or characterization and not production tested. 4. Accuracy not guaranteed unless outputs at ground potential. 5. Accuracy is tested and guaranteed at V+ =+15V, only. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best straight line" through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of 2-N of the full-scale range, e.g. ZN VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g. 112 LSB) for a given digital input change, i.e. all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full-scale range, i.e. all digital inputs at HIGH state. It is expressed as a percentage of full-scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to loun with all digital inputs LOW. Output Capacitance: CapaCitance from loun, and 10UT2 terminals to ground. Output Leakage Current: Current which appears on loun, terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. For further information on the use of this device, see the following Application Notes: ADD2 "Principles of Data Acquisition and Conversion" AD1S "Do's and Don'ts of Applying AID Converters", by Peter Bradshaw and Skip Osgood A042 "Interpretation of Data Conversion Accuracy Specifications" 8-15 AD7523, AD7533 Detailed Description The AD7523 and AD7533 are monolithic multiplylng D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPOT switches form. the basis of the converter circuit, CMOS level shifters permit low power TTU CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPOT switches steer the ladder leg currents between loun and IOUT2 buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. ±10V +15V VREF MSB DATA INPUTS j 1& 4 R2 14 16~--------~~-' M11523/1F~.....---I AD7533 ! ; NOTES: 1. R1 and R2 used only if gain adjustment is required. 2. CF1 protects AD7523 and AD7533 against negative transients. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. FIGURE 2. UNIPOLAR BINARY OPERATION TABLE 1. UNIPOLAR BINARY CODE - AD7523 DIGITAL INPUT USB LSB The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTUCMOS compatible operation over the full military temperature range. With the ladder SPOT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and high accurate leg currents. ANALOG OUTPUT 255 11111111 -V REF (256) 10000001 -V REF (256) 10000000 -V REF (256) 01111111 -V REF (256) 00000001 -V REF (256) 00000000 -V REF (256) 129 128 V REF . = - -2 - 127 1 0 =0 NOTES: TTU -'YVv-......r.-j~.... 1. 1 LSB CMOS INPUT = (2-8) (V REF ) = Zero Offset Adjustment 1. Connect all digital inputs to GND. FIGURE 1. CMOS SWITCH 2. Adjust the offset zero adjust trimpot of the output operational amplifier for OV ±1 mV (max) at Vour- Typical Applications Gain Adjustment Unipolar Binary Operation - AD7523 (8 Bit DAC) 1. Connect all digital inputs to V+. The circuit configuration for operating the AD7523 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 1. 2. Moniior Vour for a -VREF (1 - 1/28 ) reading. 8-16 3. To increase Vour, connect a series resistor, R2, (On to 2500) in the Ioun amplifier feedback loop. 4. To decrease Vour, connect a series resistor, Rl, (On to 2500) between the reference voltage and the VREF terminal. AD7523, AD7533 Unipolar Binary Operation· AD7533 (10 Bit DAC) Gain Adjustment 1. Connect all digital inputs to V+. The circuit configuration for operating the AD7533 in unipolar mode is shown in Figure 2. With pOSitive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 2. 2. Monitor VOUT for a -VREF (1 - 112 10) reading. 3. To increase VOUT' connect a series resistor, R2, (On to 250n) in the loun amplifier feedback loop. 4. To decrease VOUT, connect a series resistor, R1, (On to 250n) between the reference voltage and the VREF terminal. TABLE 2. UNIPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB (NOTE 1) NOMINAL ANALOG OUTPUT 1111111111 1023 -VREF (1024) 1000000001 513 -VREF (1024) 1000000000 V REF 512 -V REF (1024) = - 2 0111111111 511 -V REF (1024) 0000000001 1 -V REF (1024) 0000000000 0 -V REF (1024) =0 Bipolar (Offset Binary) Operation. AD7523 The circuit configuration for operating the AD7523 in the bipolar mode is given in Figure 3. USing offset binary digital input codes and positive and negative reference voltage values, Four-Quadrant multiplication can be realized. The "Dig ital Input Code/Analog Output Value" table for bipolar mode is given in Table 3.} TABLE 3. BIPOLAR (OFFSET BINARY) CODE - AD7523 DIGITAL INPUT MSB LSB ANALOG OUTPUT 11111111 127 -VREF (128) 10000001 1 -V REF (128) 10000000 0 01111111 1 +V REF (128) 00000001 127 +V REF (128) 00000000 128 +V REF (128) NOTES: 1. VOUT as shown In the Functional Diagram. 2. Nominal Full Scale for the circuit of Figure 2 is given by 1023 FS = -VREF (1024) 3. Nominal LSB magnitude for the circuit of Figure 2 Is given by 1 LSB = V REF (1024) NOTES: Zero Offset Adjustment 1. 1 LSB = 1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for OV ±1 mV (max) at VOUT- (2-7 ) (V REF ) = (1~8) A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to loun bus. A "Logic (1' input forces the bit current to IOUT2 bus. For any code the R2 RFEEDBACK DATA INPUTS ii AD7523/ 1 IoUT1 ~ ~~------------.-~~~ 10UT2 R45K R35K LSB R610MC (V REF ) - FlGURE3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) 8-17 YOUT AD7523, AD7533 IOUTl and looT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of looT2 current and the transconductance amplifier at lOUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB "Logic 1", all other bits "Logic 0"), is corrected by suing an external resistor, (10MO), from VREF to looT2 (Figure 3). = = Offset Adjustment A "Logic 1" input at any digital input forces the corresponding tadder switch to steer the bit current to 1000l bus. A "Logic 0" input forces the ~ current to 10UT2 bus. For any code the 1000l and IOUT2 bus currents are complements of one another. The current amplifier atl0UT2 changes the polarity of IOUT2 current and the transconductance amplifier at 1000l output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB "Logic 1", all other bits = "Logic 0"), is corrected by using an extemal resistor, (10MO), from VREF to looT2. = 1. Adjust VREF to approximately + 1OV. TABLE 4. UNIPOLAR BINARY CODE· AD7533 2. Connect all digital Inputs to "Logic 1". DIGITAL INPUT MSB LSB 3. Adjust looT2 amplifier offset adjust trimpot for OV ±1 mV at 10UT2 amplifier output. (NOTE t) NOMINAL ANALOG OUTPUT 1111111111 51t -VREd 512 ) 1000000001 1 -V REF (512) 1000000000 0 2. Monitor VOUT for a -VREF (1 - 1/28) volts reading. 0111111111 1 +VREd512) 3. To increase VOUT, connect a series resistor, R2, of up to 2500 between VOUT and RFEEDBACK. 0000000001 511 +V REF (512) 0000000000 512 +VREF (512) 4. Connect MSB (B~ 1) to "Logic 1" and all other bits to "Logic 0". 5. Adjust 1000l amplifier offset adjust trimpot for OV ±1 mVat VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 4. To decrease VOUT, connect a series resistor, Rl, of up to 2500 between the reference voltage and the VREF terminal. Bipolar (Offset Binary) Operation· AD7533 The circuit configuration for operating the AD7533 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The "Digital Input Code/Analog Output Value" table for bipolar mode is given in Table 4. NOTES: 1. VOUT as shown In the Functional Diagram. 2. Nominal Full Scale for the circuit of Figure 6 is given by FSR 1023 = VREF (512) 3. Nominal LSB magnitude for the circuit of Figure 3 is given by LSB 1 = VREF (512) ±lOV BIPOLAR ANALOG INPUT 10K MAGNITUDE BITS DIGrrAL INPUT 10K YOUT LSB GND mGNBrro---------------------------~ FIGURE 4. to-BIT AND SIGN MULTIPLYING DAC 8-18 AD7523, AD7533 Offset Adjustment Gain Adjustment 1. Adjust VREF to approximately +1OV. 1. Connect all digital inputs to V+. 2. Connect all digital inputs to "Logic 1". 2. Monitor VOUT for a -VREF (1 - 2"9) volts reading. 3. Adjust IOUT2 amplifier offset adjust trimpot for OV ±1 mV at IOUT2 amplifier output. 3. To increase VOUT• connect a series resistor of up to 2500 between VOUT and RFEEDBACK. 4. Connect MSB (B~ 1) to "Logic 1" and all other b~ to "Logic 0". 4. To decrease VOUT• connect a series resistor of up to 250.0 between the reference voltage and the VREF terminal. 5. Adjust IOUT1 amplifier offset adjust trimpot for OV ±1mVat VOUT- CAUBRATE 10K 1""'1 ... 6.8V (2) r- L...I SQUARE WAVE +15V Voo NC AV' DIGITAL FREQUENCY { CONTROL WORD TRIANGULAR WAVE OUT2 LSB FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR ~ ~ W z> 8 ~ Q +15V BIT 1 OUT2 OUT1 __~-VOUT VOUT =-V'NID Where: o = Bit1 2 1 + Bit2 + .•. BitS 2 2 2 WhereO 2 (OSOS~~:) 1 Bit 2 Bit 8 = -Bit2 1 + - 2 +"'-8 22 (0< Os 255) 256 FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN) FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET 8-19 AD7523, AD7533 Die Characteristics DIE DIMENSIONS: 101 x 103mils(2565 x 2616mlcrms) METALUZATION: Type: Pure Aluminum Thickness: 10 ± 1kA GLASSIVATlON: Type: PSGINitride PSG: 7± 1.4kA Nitride: 8 ± 1.2kA PROCESS: CMOS Metal Gate Metallization Mask Layout AD7523, AD7533 PIN 7 BIT 4 PINS BIT 3 PIN 4 BIT 1 (MBB) PINS BITZ PIN 3 GND PINZ PIN. BIT & IaurZ PIN 1 1our1 PIN I BITS PIN 10 BIT 7 PIN 16 RFEEDBACK PIN 11 BIT 8 (LSB) PIN 15 VAEF NC NC (PIN 12, BIT I, AD7&33) (PIN 13, BIT 10, AD7&33) NC 8-20 NC PIN 14 V+ AD7541 HARRIS SEMICONDUCTOR 12-Bit Multiplying D/A Converter December 1993 Features Description • 12-81t Linearity 0.01% The AD7541 is a monolithic. low cost. high performance. 12bit accurate. multiplying digital-to-analog converter (DAC). • Pretrimmed Gain Harris' wafer level laser-trimmed thin-film resistors on CMOS circuitry provide true 12-bit linearity with TTUCMOS compatible operation. • Low Gain and Linearity Tempcos • Full Temperature Range Operation • Full Input Static Protection Special tabbed-resistor geometries (improving time stability). full input protection from damage due to static discharge by diode clamps to V+ and ground. large lOUT! and IOUT2 bus lines (improving superposition errors) are some of the features offered by Harris AD7541. • TTUCMOS Compatible • +5V to +15V Supply Range • 20mW Low Power Dissipation • Current Settling Time 1J.ls to 0.01% of FSR Pin compatible with AD7521. this DAC provides accurate four quadrant multiplication over the full military temperature range. • Four Quadrant Multiplication Ordering Information PART NUMBER NONLINEARITY TEMPERATURE RANGE PACKAGE AD7541AD 0.02% (11-811) -25°C 10 +85OC AD7541BD 0.01% (12-BII) -25"C 10 +85°C 18 Lead Plastic DIP AD7541JN 0.02% (11-BII) OOCto +700 C 18 Lead Plastic DIP AD7541KN 0.01% (12-BII) OOClo +700 C 18 Lead Plastic DIP AD7541LN 0.01% (12-BII) Guaranteed Monotonic OOCto +700 C 18 Lead Plastic DIP AD7541SD 0.02% (11-BII) -55°C 10 +125°C 18 Lead Plastic DIP o o AD7541TD 0.01% (12-BII) -55°C to +125OC 18 Lead Plastic DIP !! Q Pinout 18 Lead Plastic DIP 12 ~ W > Z Functional Diagram AD7541 (PDIP) TOP VIEW 101en 201en BITl (MSB) 4 1 Olen 101en 1Olen (17) 201en :: '-+--,.<1>+-_+----_--....,--0 ~~ SWITCHES IoUTI (1) j o : ~ 0 MSB BIT 2 BIT 3 (4) (5) (6) RFEEDBACK (18) Switches shown are for Digital Inputs "High" CAUTION: These devices are sens~ive to electrostatic: discharge. Users should follow proper I.C. Handling Procadures. Copyright © Harris Corporation 1993 8-21 File Number 3107 Specifications AD7541 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to GND) ••••••••••••••••••••••••••• +17V VREF ••••.••••••••••••••••••••••••••••••••••••••••••••• ±2.5V Digital Input Voltage Range •.•.•.•.•..•.......••.. V+ to GND output Voltage Compliance •••••••••••••••••••• -100mV to V+ Storage Temperature ••••••••••••••••••••••• -65"C to +15O"C Lead Temperature (Soldering 1Os). . . . . . . . . . . . • . . . . • .. +3OO"C Thermal Resistance 9JA Plastic DIP Package ••••••••••••••••••••••••••• •9f1'CIW Operating Temperature JN, KN, LN Versions •••••••••••••••••••••••• O"C to +70"C AD, BD Versions •••••••••••••••••••••••••• -25°C to +85°C SO, TDVerslon •••••••••••••••••••••••••• -55"Cto+125°C Maximum Power Dissipation Plastic DIP Package up to +70"C ••••••••••••••••••• frlOmW Junction Temperature •••••••••••••••••••••••••••••• +15O"C CAUTION: SItNs.. abo.. those listed In "AbsDIu/s Maximum Ratings" mey cause permanent damage to the davies. ThIs Is. sltNs only raling end operation of the device at thesa or any other conditions abo.. thoee Indicated In the operational sectiona of this specification Is not implied. Electrical Specifications v+ =+15V, VREF =+10V, VOUTI =V0UT2 =OV, T" =+25"C, Unless Otherwise Spacifled TAMIN-MAX TA +2!i"C PARAMETER MIN TEST CONDInONS TYP MAX MIN MAX UNITS - 12 - Bits - - to.024 % 01 FSR - - to.012 %of FSR - - to.012 %oIFSR ±0.4 %oIFSR ±200 nA to.01 % 01 FSRI% of 1:N+ 1 lIS 1 mVp-p 5 20 kO - 200 pF 60 60 pF 60 - 60 pF 200 - 200 pF 0.8 V - V SYSTEM PERFORMANCE Resolution Nonlinearity 12 A,S,J B,T,K L -10V:s; VREF:S; +10V Voun V0UT2 OV See Figure 3 (Note 4) = = Monotonicity ±o.o24 to.012 to.012 - Guaranteed Gain Error -10V:S; VREF:s; +10V (Note 4) Output Leakage Current (Either Output) Voun - =VOUT2 =0 - ±0.3 - ±50 - to.OO5 - DYNAMIC CHARACTERISTICS = V+ 14.5V to 15.5V . See Figure 5, (Note 4) Power Supply Rejection Output Current SeWing Time To 0.1%01 FSR See Figure 9, (Note 5) Feedthrough Error VREF 20Vpp, 10kHz All Digital Inputs Low See Figure 8, (Note 5) = - - 5 10 1 1 - REFERENCE INPUTS Input Resistance All DigitallnpUIs High IOUtl at Ground 20 ANALOG OUTPUT Voltage Compliance Output Capacitance Both Outputs, See Maximum Ratings (Note 6) COUll -100mVto V+ - All DlgitallnpUIs High See Figure 7, (Note 5) - CoUT2 CoUTl COUT2 Output Noise (Both Outputs) All Digital Inputs Low) See Figure 7, (Note 5) See Figure 6 - 200 Equivalent to 10k0 Johnson Noise DIGITAL INPUTS Low State Threshold, V1L - (Note 1, 5) High State Threshold, V1H 2.4 8-22 - 0.8 - 2.4 Specifications AD7541 Electrical Specifications V+ =+15V, VREF =+10V, VOUTI =VOU1'2 =OV, TA =+250 C, Unless Otharwlse Specified (Continued) T,,+25°C PARAMETER TEST CONOmONS = Input Current VIN OV or V+ (Note 5) Input Coding See Tables 1 & 2 (Note 5) Input Capacitance (NoteS) T"MIN-MAX MIN TYP MAX MIN MAX UNITS - - ±1 - ±1 I1A 8 pF Binary/Offset Binary - - 8 - POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range Accuracy Is not guaranteed over this range 1+ All Digital Inputs High or Low (Excluding Ladder Network) - - 2.0 Total Power Dissipation (Including Ladder Network) - 20 - V +5 to +16 - 2.5 mA - mW NOTES: 1. The digRal control inputs are zener protected; however, permanent damage may occur on unconnec1ed units under high energy electrostatic fields. Keep unused units in conductive loam at all times. 2. Do not apply voltages higher than VOD or less than GND potential on any terminal except VREF and RFEEDBACK. 3. Full scale range (FSR) is 10V for unipolar and ±1 OV for bipolar modes. 4. Using intemal feedback resistor, RFEEDBACK. 5. Guaranteed by design or characterization and not production tested. 6. Accuracy not guaranteed unless outputs at ground potential. Definition of Terms Detailed Description Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best fit straight line" function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF range. The AD7541 is a 12-bit, monolithic, multiplying D/A converter. A highly stable thin film R-2R resistor ladder network and NMOS SPOT switches form the basis of the converter circuit. CMOS level shifters provide low power TTUCMOS compatible operation. An external voltage or current reference and an operational amplifier are all that Is required for most voltage output applications. A simplified equivalent circuit of the CAC is shown on page 1, (Functional Diagram). The NMOS SPOT switches steer the . ladder leg currents between IOUT1 and IOUT2 buses which must be held at ground potential. This con· figuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further eliminated by using wider metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset (leakage) errors to a negligible level. Resolution: Value of the LSB. For example, a unipolar converter with n bits has a resolution of LSB (VREF)I2-N. A bipolar converter of n bits has a resolution of LSB (V REF)/ 2-(N-1). Resolution in no way implies linearity. = = Settling nme: Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, i.e., 0 to Full Scale. Gain Error: Ratio of the DAC's operational amplifier output voltage to the nominal input voltage value. Feedthrough Error: Error caused by capacitive coupling from VREF to output with all switches OFF. Output Capacitance: Capacitance from 10UT1' and IOUT2 terminals to ground. Output Leakage Current: Current which appears on 10UT1' terminal when all digital inputs are LOW or on IOUT2 terminal when all inputs are HIGH. Each circuit is laser·trimmed, at the wafer level, to better than 12·bits linearity. For the first four bits of the ladder, special trim·tabbed geometries are used to keep the body of the reSistors, carrying the majority of the output current, undis· turbed. The resultant time stability of the trimmed circuits is comparable to that of untrimmed units. The level shifter Circuits are comprised of three inverters with a poSitive feedback from the output of the second to first (Figure 1). This configuration results in TTL/COMS compati· ble operation over the full military temperature range. With the ladder SPOT switches driven by the level shifter, each switch is binary weighted for an "ON" resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equiPotential ter· mlnations for the 2R ladder resistor, resulting in accurate leg currents. 8-23 AD7541 v+--~----~------~--~- +15V VAEF ________--, • :t10V FIGURE 1. CMOS SWITCH FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Typical Applications Zero Offset Adjustment General Recommendations 1. Connect all digital inputs to GND. Static performance of the AD7541 depends on lOUT! and IOUT2 (pin 1 and pin 2) potentials being exactly equal to GND (pin3). 2. Adjust the offset zero adjust trlmpot of the output operational amplifier for OV ±O.5mV (max) at VOUT' Gain Adjustment The output amplifier should be selected to have a low input bias current (typically less than 75nA), and a low drift (depending on the temperature range). The voltage offset of the amplifier should be nulled (typically less than ±200I1V). 1. Connect all digital inputs to Voo2. Monitor VOUT for a -VREF (1 - 1/212) reading. 3. To increase VOUT, connect a series reSistor, (On to 250n), in the IOUT1 amplifier feedback loop. The bias current compensation resistor in the amplifier's non-inverting input can cause a variable offset. Non-inverting input should be connected to GND with a low resistance wire. 4. To decrease Vour. connect a series resistor, (00 to 2500), between the reference voltage and the VREF terminal. Ground-loops must be avoided by taking all pins going to GND to a common pOint, using separate connections. TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION DIGITAL INPUT The V+ (pin 18) power supply should have a low noise level and should not have any transients exceeding +17V. Unused digital inputs must be connected to GND or Voo for proper operation. A high value resistor (-1Mn) can be used to prevent static charge accumulation, when the inputs are open-circuited for any reason. When gain adjustment is required, low tempco (approximately 50ppmJ"C) resistors or trim-pots should be selected. ANALOG OUTPUT 111111111111 -VREF (1 - 1/212) 100000000001 -VREF (1/2 + 1/212j 100000000000 -VREr:f2 011111111111 -VREF (1/2 - 1/212) 000000000001 -VREF (1/212) 000000000000 0 Unipolar Binary Operation The circuit configuration for operating the AD7541 in unipolar mode is shown in· Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication; The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 1. A Schottky diode (HP5082-2811 or equivalent) prevents lOUT! from negative excursions which could damage the device. This precaution is only necessary with certain high speed amplifiers. Bipolar (Offset Binary) Operation The circuit configuration for operating the AD7541 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values Four-Quadrant multiplication can be realized. The "Digital Input Code/Analog Output Value" table for bipolar mode is given In Table 2. 8-24 AD7541 A "Logic 1" input at any digital input forces the corresponding Gain Adjustment ladder switch to steer the bit current to loun bus. A "Logic rJ' 1. Connect all digital inputs to VOl> input forces the bit current to 10UT2 bus. For any code the loun and IOUT2 bus currents are complements of one 2. Monitor VOUT for a -VREF (1 - '/2") volts reading. another. The current amplifier at IOUT2 changes the polarity 3. To increase VOUT, connect a series resistor, (00 to 2500), of IOUT2 current and the transconductance amplifier at loun in the loun amplifier feedback loop. output sums the two currents. This configuration doubles the output range of the DAC. The difference current resulting at 4. To decrease VOUT' connect a series resistor, (00 to 2500), zero offset binary code, (MSB = "Logic 1", All other bits = between the reference voltage and the VREF terminal. "Logic 0"), is corrected by using an external resistive divider, from VREF to louT2. TABLE 2. CODE TABLE - BtPOLAR (OFFSET BINARy) OPERATION Offset Adjustment 1. Adjust VREF to approximately +10V. ANALOG OUTPUT DIGITAL INPUT 2. Set R4 to zero. 111111111111 -VREF (1 - '/2") 3. Connect all digital inputs to "Logic 1". 100000000001 -VREF ('/2") 4. Adjust loun amplifier offset zero adjust trimpo! for OV ±C. 1mV at IOUT2 amplifier output. 100000000000 0 5. Connect a short circuit across R2. 011111111111 VREF (1/2") 6. Connect all digital inputs to "Logic (J'. 000000000001 VREF (1 - '/2'1) 7. Adjustl0UT2 amplifier offset zero adjusttrimpot forOV ±C. 1mV at loun amplifier output. 000000000000 VREF 8. Remove short circuit across R2. 9. Connect MSB (Bit 1) to "Logic 1" and all other bits to "Logic rJ'. 10. Adjust R4 for OV ±C.2mV at VOUT. 10V VREFo-------~~--------------------------~ BIT 1 (MSB) 18t------------------, IoUT1 >---t-- VOUT DIGITAL INPUT AD7541 R110K R210K --'---115 BIT 12 (LSB) 3 = R3 390k 21-....- -.....-r.... R4 500n GNO = NOTE: Rl AND R2 SHOULD BE O.OI%, LOW-TCR RESISTORS F1GURE3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) 8-25 AD7541 Test Circuits .1 IV VAEF---" BIT 1 (USB) 17 ,. 4 12-BIT BINARY RFEEDBACK 18 & 1 10m AD7541 COUNTER 16 BIT 12 (LSB) ..n.n. CLOCK VAEF 14-B1T REFERENCE DAC 1-----""" FIGURE 4. NONUNEARITY TEST CIRCUIT .16V UNGROUNDED SINE WAVE GENERATION 500K 4OHzl.0Vp..p .10V VAEF-.-----~_r---~~--~~~ BIT 1 (MSB) 17 ,. 4 18 t-:-==;:;.....=.:=.L.I t--..,..-+I& 1 AD7541 BIT 12 (LSB) FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT .,1V (ADJUST FOR Vour- OV) .,5V 1K F_1KHz BW .. 1Hz QUAM Vour TECH MODEL 134D WAVE ANALVZER FIGURE 6. NOISE TEST CIRCUIT 8-26 AD7541 Test Circuits (Continued) +15V BIT 1 (USB) ~;:::=::::I NC +15V 17 16 ; VREF. 20Vpp 10kHz SINE WAVE BIT 1 (MSB) NC 18 +15V 16 181-----......, 1K AD7541 11--_W.,...., +-1....---115 ....;r--' BIT 12 (LSB) ........:;......... BIT 12 (LSB) .... FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT +15V V..:R:::EF:.-_~ +10V BIT 1 (MSB) EXTRAPOLATE 17 ~~...nn.n.. t:::,==~: _---+ l' 16 +10OmV.J'U1". OSCILLOSCOPE AD7541 DIGITAL INPUT BIT12 (LSB) 31: 5% SETTUNG 81: 0.01% SETTUNG 1 15 3 2 1000 GND FIGURE 9. OUTPUT CURRENT SETTUNG TIME TEST CIRCUIT Dynamic Performance The dynamic performance of the DAC, also depends on the output amplifier selection. For low speed or static applications, AC specifications of the amplifier are not very critical. For high-speed applications slew-rate. settling·time. openloop gain and gain/phase-margin specifications of the amplifier should be selected for the desired performance. The output impedance of the AD7541 looking into loun varies between 10kn (RFEEDBACK alone) and 5Kn (RFEEDBACK in parallel with the ladder resistance). Similarly the output capacitance varies belween the minimum and the maximum values depending on the input code. These variations necessitate the use of compensation capacitors. when high speed amplifiers are used. A capacitor in parallel with the feedback resistor (as shown in Figure 10) provides the necessary phase compensation to critically damp the output. A small capacitor connected to the compensation pin of the amplifier may be required for unstable situations causing oscillations. Careful PC board layout. minimizing parasitic capacitances. is also vital. +1SV VREF +10V FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR. Cc 8-27 AD7545 12-Bit Buffered Multiplying. CMOSDAC December 1993 Features Description • 12-81t Resolution The AD7545 Is a low cost monolithic 12-bit CMOS multiplying DAC with on-board data latches. Data is loaded in a single 12-bit wide word which allows interfaCing directly to most 12-bit and 16-bit bus systems. Loading of the input latches is under the control of the CS and WR Inputs. A logic low on these control inputs makes the input latches transparent allowing direct unbuffered operation of the DAC. • Low Gain T.e. 2ppnVOC Typ • Fast TTUCMOS Compatible Data Latches • Single +5V to +1SV Supply • LowPower • LowCost • /883 Processed Versions Available Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE AD7545JN O"C to +70"C 20 Lead PlasUc DIP AD7545KN O"C to +70"C 20 Lead Plastic DIP AD7545AN -40"C to +85°C 20 Lead Plastic DIP AD7545BN -40"C to +85°C 20 Lead PlasUc DIP AD7545AD -4O"C to +85°C 20 Lead Ceramic DIP AD7545BD -40"C to +85°C 20 Lead Ceramic DIP AD7545SD -5500 to +125"C 20 Lead Ceramic DIP Pinout Functional Diagram AD7545 (PDIP, CDlP) TOP VIEW RFB DONO 3 DB11 (MSa) 4 OBI 0 DBIl cs DBO(LSB) DBll - DBO (PINS 4-15) CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 8-28 File Number 3108 Specifications AD7545 Absolute Maximum Ratings Thermal Information Supply Voltage (Voo to DGND) ••.••..•••••••.•••• -0.3V, +17V Digital Input Voltage to DGND •••.•••••••••••• -o.3V, Voo +O.3V VRFB, VREF to DGND •••••••••••••..••..••••••••••••••••• ±25V VPIN1 to DGND ....•......••.•.........•••• -0.3V, Voo +O.3V AGND to DGND ••••••••••••••••.•••••••••• -o.3Y, Voo +O.3V Storage Temperature ••.•••••.•.•••••••••••• -65"C to +1 SO"C Lead Temperature (Soldering 1Os) •••••••••••••••••••• +300"C Thermal Resistance 9JA Ceramic DIP Package ••••••••••••••• 71°C/W Plastic DIP Package •••••••••••••••• 12O"CNI Operating Temperature Commercial (J, K, Grades) ••••••••••••••••••• O"C to +70"C Industrial (A, B, Grades) •••••.••••.•••••.••• -4O"C to +85°C Extended (S Grades) •••••••••••••••••••••• -55°C to +125°C CAUTION: Stresses aboII8 thDse listed in "Absolute MaxImum Ratings' may cause permenent damage to the dsvice. This is a stress only rating and operation of the device at these or any other conditions above thDse indicatsd In the operational sections of this specification is not impUed. Electrical Specifications TA = See Note I, VREF = +10V, VOUT1 = Ov, AGND = DGND, Unless Otherwise Specified Voo=+15V Voo=+5V PARAMETER TEST CONDITIONS MIN TYP MAX - ±2 MIN TYP MAX UNITS - ±2 LSB STATIC PERFORMANCE Resolution - J,A,S Differential Nonlinearity J,A,S lo-Bi1 Monotonic TMIN to TMAX K,B 12-8R Monotonic TMIN to TMAX DAC Register Loaded with 1111 1111 1111 - K,B Gain Error (Using Internal RFB) J,A,S K,B Gain Error Is Adjustable Using the Circuits of Figure 5 and 6, (Note 2) Gain Temperature Coefficient AGainlATemperature Typical Value Is 2ppmi"C for Voo = +5V, (Note 3) DC Supply Rejection AGainlAVoo AVoo=±5% Output Leakage Current atOUTl 12 12 RelatiVe Accuracy J,K - A,B -S DBO-DB11 =OV; WR,OS=OV (Note 1) - ±1 LSB - ±4 LSB - ±1 LSB ±20 - ±25 LSB ±10 - - ±15 LSB ±5 - - ±10 ppnV"C 0.03 0.01 - 0.02 % ±4 - - ±1 - - - - - - O.ot5 - - - Bits - - - - ±1 50 - - 50 nA 50 - 50 nA 200 - - 200 nA DYNAMIC CHARACTERISTICS Current Setting Time To 1/2 LSB OUT1 LOAD = loon. DAC output measured from failing edge of WR, OS = Ov, (Note 3) - - 2 - - 2 lIS Propagation Delay from Digital Input Change to 90% of Final Analog Output OUT1 LOAD = loon CEXT = 13pF (Note 3 and 4) - - 300 - - 250 ns Digital to Analog Glitch Impulse VREF = AGND nVsec 5 - - VREF =±10V,IOkHzSil1llWlMl, (NoteS) - 250 AC Feedthrough At OUTI - - 70 - - - 200 - - - 400 5 - mVp.p 70 pF 200 pF ANALOG OUTPUTS Output CapaCitance COUT1 Q!!l :.Q.Bll = OV, WR, CS = Ov, (Note 3) COUT1 ~ :.Q.B 11 = Voo, WR, CS = OV, (Note 3) 8-29 Specifications AD7545 Electrical Specifications = TA See Note 1. VREF =+10V. VOUT1 =OV. AGNO =OGNO. Unless Otherwise Specified (Continued) Voo=+ISV VDO=+5V PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS - - 7 - lin - - 25 25 lin - 13.5 V REFERENCE INPUT Input Resistance. (Pin 19 to GNO) Input Resistance TC -300ppmPC typ = Typical Input Resistance ll11n = 7 - DIGITAL INPUTS Input High Voltage, VIH Input Current. liN VIN =0 or Voo. (Note 6) 0.8 ±10 ±1 - 7 - - 20 - - 200 120 0 - 240 100 - Input Low Voltage. VIL - - 2.4 ±1 1.5 V ±10 jiAmax Input Capacitance OBO-OBll WR.CS =O. (Note 3) VIN =O. (Note 3) VIN - 7 pF 20 pF SWITCHING CHARACTERISTICS (Note 3) - - Chip Select to Write Setup Time. tes See Figure 1 380 200 ns Chip Select to Write Hold Time. teH See Figure 1 0 - Write Pulse Width. tWR Ics ~ 1wR.1cH ~ o. See Figure 1 400 175 Data Setup Time. los See Figure 1 210 100 120 60 - ns Data Hold Time. IoH See Figure 1 10 - - 10 - - ns All OigHallnputs VIL or VIH - - 2 - All OlgHallnputs OV or Voo - 100 500 All Digital Inputs OV or Voo - 10 - ns ns POWER SUPPLY CHARACTERISTICS 100 - NOTES: 1. Temperature Ranges as follows: J. K versions: O"C to +700 C A. B versions: -2O"C to +85°C S version: -55°C to +125°C TA +25"C for TYP Specifications. MIN and MAX are measured over the specified operating range. = 2. This includes the effect of 5ppm maximum gain TC. 3. Parameter not tested. Parameter guaranteed by design. Simulation. or characterization. 4. OBO - OBll = OV to Voo or Voo to OV in plastic and sldebraze package. 5. Feedthrough can be further reduced by connecting the metal lid on the ceramic package to OGNO. 6. Logic inputs are MOS gates. Typical Input current (+2500) is less than 1nA. 7. Typical values are not guaranteed but reflect mean performance specification. Specifications subject to change without notice. 8-30 - 2 mA 100 500 jiA 10 - jiA AD7545 Timing Diagram R Ir'---- R R Veo o RFB Veo ~r-~+-~++--~~~~~++-i~---o OUT1 L--+~--~--~~~~--~-4-----o AGNO o OB11 Veo OATAIN (OBO·OB11) OB10 DBI OB1 DBO (LSB) (USB) o FIGURE 2. SlMPUFIED DlA CIRCUIT OF AD7545 FIGURE 1A. TYPICAL WRITE CYCLE TOLADOER o Veo o OATAIN --"""-~~~~...&."\It--­ (OBO·OB11) Veo o AGND FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH FIGURE lB. PREFERRED WRITE CYCLE The capacitance at the OUT1 bus line, COUll, Is code dependent and varies from 70pF (all switches to AGNO) to 200pF (all switches to OUT1). FIGURE 1. WRITE CYCLE TIMING DIAGRAM MODE SELECTION WRITE MODE: OUT 1 The input resistance at VREF (Figure 2) is always equal to RLDR (RLOR is the Rl2R ladder characteristic resistance and is equal to the value oR',. Since RIN at the VREF pin is constant, the ref· erence terminal can be driven by a reference voltage or a refer· ence current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature coefficient extemal RFB is recommended to define scale factor)Circuit Information • Digital Section. HOLD MODE: CS and WR low, DAC responds Either CS or WR high, data bus to data bus (OBO • DB11) inputs (OBO· OB11) is locked out; DAC holds last data present when WR or CS assumed high state. NOTES: 1. Voo=+5V;tR=tF=20ns 2. Voo = +15V; IR = tF = 40ns 3. All input signal rise and fall times measured from 10% to 90% of VOD' 4. Timing measurement reference level is (V1H + VIUI2. 5. Since input data latches are transparent for CS and WR both low, It is preferred to have data valid before CS and WR both go low. This prevents undesirable changes at the analog output while the data inputs settle. Figure 4 shows the digital structure for one bit. The digital signals CONTROL and CONTROL are generated from CS andWR. Circuit Information· DIA Converter Section The input buffers are simple CMOS inverters designed such that when the A07545 is operated with Voo 5V, the buffers convert TTL input levels (2.4V and O.8V) into CMOS logic levels. When V,N is in the region of 2.0V to 3.5V the input buffers operate in their linear region and draw current from the power supply. To minimize power supply currents it is recommended that the digital Input voltages be as close to the supply rails (Voo and OGNO) as is practically possible. Figure 2 shows a simplified circuit of the O/A converter section of the A07545. Note that the ladder termination resistor is connected to AGNO. R is typically 11 kn The A07545 may be operated with any supply voltage in the range 5V s Voo s 15V. With Voo +15V the input logic lev· els are CMOS compatible only, i.e., 1.5V and 13.5V. = The binary weighted currents are switched between the OUT1 bus line and AGNO by N-channel switches, thus maintaining a constant current in each ladder leg indepen· dent of the switch state. One of the current switches is shown in Figure 3. 8·31 = o Ill: ~ W ~ o (.) !! Q AD7545 Application Basic Applications Output Offset Figures 5 and 6 show simple unipolar and bipolar circuits using the AD7545. Resistor Rl is used to trim fOr full scale. Capacitor Cl provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. Note that the circuits of Figures 5 and 6 have constant input impedance at the VREF terminal. CMOS current-steering D/A converters exhibit a· code dependent output resistance which in turn causes a code dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output which depends on Vos where Vos is the amplifier input offset voltage. To maintain monotonic operation it is recommended that Vos be no greater than (25 x 10-6) (VREF) over the temperature range of operation. . General Ground Management AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545. In more complex systems where the AGND and DGND connection Is on the backplane, It is recommended that two diodes be connected in inverse parallel between the AD7545 AGND and DGND pins (1 N914 or equivalent). Digital Glitches When WR and CS are both low the latched are transparent and the D/A converter inputs follow the data inputs. In some bus systems, data on the data bus is not always valid fOr the whole period during which WR Is low and as a result invalid data can briefly occur at the D/A converter inputs during a write cycle. Such invalid data can cause unwanted glitches at the output of the D/A converter. The solution to this problem, if it occurs, is to retime the write pulse (WR) so that it only occurs when data is valid. Another cause of digital glitches is capacitive coupling from the digital lines to the OUTl and AGND terminals. This should be minimized by Isolating the analog pins of the AD7545 (Pins 1,2, 19,20) from the digital pins by a ground track run ~tween pins 2 and 3 and between pins 18 and 19 of the AD7545. Note how the analog pins are at one end of the package and separated from the digital pins by V DO and DGND to aid isolation at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digital to analog sections of the AD7545, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is minimized by using Voo +5V. However, great care should be taken to ensure that the +5V used to power the AD7545 .is free from digitally induces noise. = The circuit of Figure 5 can either be used as a fixed reference D/A converter so that it provides an analog output voltage in the range OV to -VIN (note the inversion introduced by the op amp) or V1N can be an ac signal in which case the circuit behaves as an attenuator (2-Quadrant Multiplier). V1N can be any voltage in the range -20V S V 1N S +20V (provided the op amp can handle such voltages) since VREF is permitted to exceed Voo- Table 2 shows the code relationship for the circuit of Figure 5. Figure 6 and Table 3 illustrate the recommended circuit and code relationship fOr bipolar operation. The D/A function itself uses offset binary code and inverter U 1 on the MSB line converts 2's complement input code to offset binary code. If appropriate, inversion of the MSB may be done in software using an exclusive -OR instruction and the inverter omitted. R3, R4 and R5 must be selected to match within 0.01 % and they should be the same type of resistor (preferably wire-wound or metal fOil), so that their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full scale error. Mismatch of .A5 to R4 and R3 causes full scale error. The choice of the operational amplifiers in Figure 5 and Figure 6 depends on the application and the trade off between required precision and speed. Below is a list of operational amplifiers which are good candidates fOr many applications. The main selection criteria for these operational amplifiers is to have low Vos , low Vos drift, low bias current and low settling time. These amplifiers need to maintain the low nonlinearity and monotonic operation of the D/A while providing enough speed for maximum converter performance. Operational Amplifiers HA5127 HA5137 HA5147 HA5170 Ultra low Noise, Precision Ultra low Noise, Precision, Wide Band Ultra low Noise, Precision, High Slew Rate Precision, JFET Input TABLE 1. RECOMMENDED TRIM RESISTOR VALUES vs GRADES FOR Veo = +5V Temperature Coefficients The gain temperature coefficient of the AD7545 has a maximum value of 5ppmf'C and a typical value of 2ppmJOC. This corresponds to worst case gain shifts of 2lSBs and 0.8lSBs respectively over a 100°C temperature range. When trim resistors Rl and R2 are used to adjust full scale range, the temperature coefficient of Rl and R2 should also be taken into account. 8-32 TRIM RESISTOR J,A,S K,B RI 5000 2000 R2 1500 680 AD7545 TABLE 2. UNIPOLAR BINARY CODE TABLE FOR CIRCUIT OF FIGURE 5 BINARY NUMBER IN DAC REGISTER TABLE 3. 2'S COMPLEMENT CODE TABLE FOR CIRCUIT OF FIGURE 6 ANALOG OUTPUT DATA INPUT ANALOG OUTPUT 1111 1111 1111 -V {4095} IN 4096 1000 0000 0000 2048 -VIN {4096} 0000 0000 0001 1 -VIN {4096} 0000 0000 0000 OV = _!V 2 IN Voo 0111 1111 1111 2047 +VIN - {2048} 0000 0000 0001 1 +V IN - {2048} 0000 0000 0000 OV 1111 1111 1111 1 -VIN - {2048} 1000 0000 0000 2048 -V IN • {2048} R2. VIN Your cs 0 - - - - - - - ' • REFER TO TABLE 1 DB11 - DBO (pINS 4-15) FIGURE 5. UNIPOLAR BINARY OPERATION Voo R2. R4 20k >-....._ Ci------' ·FOR VALUES OF Rl AND R2 SEE TABLE 1 DATA INPUT FIGURE 6. BIPOLAR OPERATION (2'S COMPLEMENT CODE) 8-33 Vour AD7545 Die Characteristics DIE DIMENSIONS: 121 x 123mils (3073 x 3124micrms) METALUZATlON: Type: Pure Aluminum Thickness: 10± 1kA GLASSIVATlON: Type: PSG/Nitride PSG: 7± 1.4kA Nitride: 8 ± 1.2kA PROCESS: CMOS Metal Gate Metallization Mask Layout A07545 PIN 7 OBI PIN. DBe PIN 4 0811 (MSB) PINS DB10 r---~~--~~-;;;;;;;ii;;~~;;;;;;;;'~~;-~:::;-;;;;;;'~N3 DONO PIN 2 AOND PIN 1 OUT1 PIN 8 DB7 PINe DBS PIN 10 DBS PIN 11 DB4 PIN 20 RFEEDBACK PIN1e YREF PIN 12 DB3 PIN 13 PIN 18 DB2 Yeo ~N14 DB1 PlN1S DBO (LSB) 8-34 PIN 1. PIN 17 Ci WR CA3338, CA3338A CMOS Video Speed 8-Bit R2R CIA Converter December 1993 Features Description • CMOs/SOS Low Power The CA3338 family are CMOs/SOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce "rail-ta-rail" output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground. The data complement control allows the inversion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, "glitch" energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits. • R2R Output, Segmented for Low "Glitch" • CMOSITTL Compatible Inputs • Fast Settling: 20ns (Typ) to 1/2 LSB • Feedthrough Latch for Clocked or Unclocked !Jse • ±O.5 LSB Accuracy (Typ) • Data Complement Control • High Updste Rate 50MHz (Typ) • Unipolar or Bipolar Operation The CA3338 is manufactured on a sapphire substrate to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance. Applications • TVNideo Display • High Speed Oscilloscope Display • Digital Waveform Generator • Direct Digital Synthesis Ordering Information Pinout CA3338, CA3338A (POIP, CDlP, SOIC) TOP VIEW PART NUMBER LINEARITY (INL,DNL) TEMPERATURE RANGE CA3338E ±1.0LSB -40°C to +85°C 16 Lead Plastic DIP CA3338AE ±0.75LSB -40°C to +85°C 16 Lead Plastic DIP CA3338D ±1.0 LSB -55°C to +125°C 16 lead Ceramic 01 P CA3338AD ±O.75LSB -55°C to +125OC 16 Lead Ceramic DIP CA3338M ±1.0 LSB -40 C to +85°C 16 Lead Plastic SOIC eN) CA3338AM ±0.75LSB -40 C to +85°C 16 Lead Plastic SOIC eN) 0 0 CAUTION: Theae del/ices ara sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 8-35 PACKAGE File Number 1850.1 CA3338, CA3338A Functional Diagram 16 13 Voo LE VREF+ 16 12 VOUT 3-81T T07-UNE THERMOMETER ENCODER COMP R D7 LEVEL SHIFTERS D6 os D4 D3 D2 D1 DO Vss FEEDTHROUGH LATCHES 3 R R 4 5 R 6 R 7 R II R 8 2R 11 VREP 10 VEE Rs;16On Die Characteristics DIE DIMENSIONS: 2.050l1m x 2.200l1m x 530 ± 50l1m METALLIZATION: Type: AI with a./}% Si Thickness: 11kA± 1kA GLASSIVATlON: Type: 3% PSG Thickness: 13kA ± 2.6kA 8-36 Specifications CA333B, CA333BA Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range •••••••••.••••.•.•••.• -0.5V to +8V (Voo - Vss or Voo - VEE, whichever is greater) Input Voltage Range Digital Inputs (LE, COMP DO - D7) ••.•. Vss - 0.5V to Voo + 0.5V Analog Pins (VREf'+, VREF -, VOUT) •..••. Voo - 8V to Voo + 0.5V DC Input Current Digital Inputs (LE, COMp, DO - D7) ......•.....•....••.• ±20rnA Recommended Supply Voltage Range •..•..•••••••. 4.5V to 7.5V Storage Temperature Range, TSTG' •••••••••••• -65°C to +150°C Le8ct Temperature (Soldering 1Os) •••.••••..•••••••••. +300oC Thermal Resistance Ceramic DIP Package ......•.•..•..• Plastic DIP Package •••••••••.••.... SOIC Package ••••••••..•••••••..•. Maximum Power Dissipation, Po TA = _55°C to +55°C ••.••..•.•••.•.•••••••••.•.•• 315mW Operating Temperature Range (TA) Ceramic Package, D suffix ••.••••...••....•. -55°C to +125°C Plastic Package, E suffix, M suffix •.•.••.••••.•. -4ooC to +65°C Junction Temperature Ceramic Package •••••.••.•••...•••••••••••••••• +175°C Plastic Package ...•.•..••••••••.•••.••••••.••••• +150°C CAUTION: Sl!esses abOI/8 those listed In ·Absolute Maximum Ratings· may cause permanent damage to the device. This Is • stress only mUng and opemtion of the devies at these or any other conditions aOOI/8 those indicated in the opemtional sacUons ot this specification Is not impHed. Electrical Specifications TA =+25°C, voo =5V, VREf'+ =4.608V, Vss =VEE =VREF- =GND, LE clocked at 20MHz, RL ~ 1 Mo, Unless Otherwise Specified PARAMETER MIN TYP MAX UNITS 8 - - Bits - - ±1 LSB ±0.75 LSB - - ±0.75 LSB ±a.5 LSB CA3338 - LSB - - ±0.75 CA3338A ±a.5 LSB ±0.25 LSB TEST CONDITIONS ACCURACY Resolution Integral Linearity Error See Figure 4 CA3338 CA3338A Differential linearity Error See Figure 4 CA3338 CA3338A Gain Error Offset Error Input Code =FFHEX, See Figure 3 - Input Code =OOHEX; See Figure 3 DIGITAL INPUT TIMING Update Rate To Malntaln 1/2 LSB Settling DC 50 - MHz Update Rate VREF - =VEE DC 20 - MHz Set Up Time TSU1 For Low Glitch -2 - ns Set Up Time TSU2 For Data Store - 8 - ns Hold Time TH For Data Store - 5 Latch Pulse Width Tw For Data Store - 5 Latch Pulse Width Tw VREF- =VEE =-2.5V, VREf'+ =+2.5V - 25 =-2.5V, VREF+ =+2.5V - ns - ns ns OUTPUT PARAMETERS RL Adjusted for 1Vp•p Output Output Delay T01 From LE Edge - 25 Output Delay TD2 From Data Changing - 22 Rise Time TR 10% to 90% of Output Settling Time TS 10% to Settling to 1/2 LSB - Output Impedance VREF+ =6V, Voo =6V Glitch Area Glitch Area VREF- =VEE =-2.5V,VREF+ =+2.5V 8-37 - ns ns 20 - 120 160 200 n - 250 4 150 - ns ns pV-s pV-s CA3338, CA3338A Electrical Specifications TA = +25"C, Voo = 5V, VREJ'+ = 4.608V, Vss = VEE = VREF - = GND, LE clocked at 20MHz, F\ ~ 1 Mo, Unless Otherwise Specified (Condnued) PARAMETER TEST ,CONDITIONS MIN TYP VREF-+3 - MAX UNITS REFERENCE VOLTAGE Voo V VREF+- 3 V 40 50 rnA 100 220 - 100 I1A I1A - mA VREJ'+ Range (+) Full Scale, Note 1 VREF- Range (-) Full Scale, Note 1 VEE VREJ'+ Input Current VREJ'+ = 6V, Voo ='6V - LE = Low, DO - 07 = High - LE = Low, DO - 07 = Low - VOUT = 10MHz, OV to 5V Square Wave - 20 - SUPPLY VOLTAGE Static 100 or lEE Dynamic 100 or lEE Dynamic 100 or lEE VOUT = 1OMHz, ±2.5V Square Wave Voo Rejection 50kHz Sine Wave Applied VEE Rejection 50kHz Sine Wave Applied 25 3 1 - - rnA mVN mVN DIGITAL INPUTS DO - 07, LE, COMP - 2 - - 0.8 V Leakage Current - ±1 ±5 I1A Capacitance - 5 - pF - 200 - ppmi"C High Level Input VoHage Note I Low Level Input Voltage Note I V TEMPERATURE COEFFICIENTS Output Impedance NOTE: 1. Parameter not tested. but guaranteed by design or characterization. Pin Descriptions DigitaJ Signal Path PIN NAME I 07 2 06 Input 3 05 Data 4 04 Bits (High = True) 5 03 6 D2 7 01 8 Vss 9 DESCRIPTION Most Significant Bit Digital Ground Do Least Significant Bit. Input Data Bit 10 VEE Analog Ground 11 VREF- 12 VOUT Reference Voltage Negative Input Analog Output 13 VREFi" Reference Voltage Positive Input 14 COMP Data Complement Control input. Active High 15 LE 16 Voo The digital inputs (LE, COMp, and DO - D7) are of TTL compatible HCT High Speed CMOS design: the loading is essentially capacitive and the logic threshold is typically 1.SV. The 8 data bits, DO (weighted 2~ through D7 (weighted 27), are applied to Exclusive OR gates (see Functional Diagram). The COMP (data complement) control provides the second input to the gates: if COMP is high, the data bits will be inverted as they pass through. The input data and the LE (latch enable) signals are next applied to a level shifter. The inputs, operating between the levels of Voo and Vss, are shifted to operate between Voo and VEE' VEE optionally at ground or at a negative voltage, will be discussed under bipolar operation. All further logic elements except the output drivers operate from the Voo and VEE supplies. The upper 3 bits of data, DS through D7, are input to a 3-to-7 line bar graph encoder. The encoder outputs and DO through , D4 are applied toa feedthrough latch, which is controlled by LE (latch enable). Latch Enable Input. Active Low Digital Power Supply, +5V 8-38 CA3338, CA3338A In unipolar operation. VREF" would typically be retumed to analog ground. but may be raised above ground (see speci· fications). There is substantial code dependent current that flows from VREF+ to VREF· (see VREF+ input current in specifications). so VREF· should have a low impedance path to ground. T8U2 LATCH LATCHED ENABLE In bipolar operation. V REF • would be retumed to a negative voltage (the maximum voltage rating to V DD must be observed). VEE. which supplies the gate potential for the out· put drivers. must be retumed to a point at least as negative as VREF·. Note that the maximum clocking speed decreases when. the bipolar mode is used. FIGURE 1. DATA TO LATCH ENABLE TIMING INPUT DATA Static Characteristics The ideal B-bit D/A would have an output equal to VREF· with an input code of OOHEX (zero scale output). and an output equal to 255/256 of VREF+ (referred to VREF"l with an input code of FFHEX (full·scale output). The difference between the ideal and actual values of these two parameters are the OFFSET and GAIN errors. respectively; see Figure 3. LATCH ENABLE OUTPUT VOLTAGE FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING Latch Operation Data is fed from input to output while LE is low: LE should be tied low for non·clocked operation. Non·clocked operation or changing data while LE is low is not recommended for applications requiring low output "glitch" energy: there is no guarantee of the simultaneous changing of input data or the equal propagation delay of all bits through the converter. Several parameters are given if the converter is to be used in either of these modes: T D2 gives the delay from the input changing to the output chang· ing (10%). while TSU2 and TH give the set up and hold times (referred to LE rising edge) needed to latch data. See Figures 1 and 2. If the code into an 8-bit D/A is changed by 1 count. the output should change by 1/255 (full·scale output·zero scale output). A deviation from this step size is a differential linear· ity error. see Figure 4. Note that the error is expressed in fractions of the ideal step size (usually called an LS8). Also note that if the (-) differential linearity error is less (in absolute numbers) than 1 LSB. the device is monotonic. (The output will always increase for increasing code or decrease for decreasing code). If the code into an 8-bit D/A is at any value. say "N". the out· put voltage should be N1255 of the full·scale output (referred to the zero·scale output): Any deviation from that output is an integral linearity error. usually expressed in LSBs. See Figure 4. Note that OFFSET and GAIN errors do not affect integral lin· earity. as the linearity is referenced to actual zero and full· scale outputs. not ideal. Absolute accuracy would have to also take these errors into account. GAIN ERROR ~ 2551256 -.-_ _ _ _ _ _ _ _ _ _ _{:..;.S....;H....;.;.OW;.;.;N.}r-I- Clocked operation is needed for low "glitch" energy use. Data must meet the given TSU1 set up time to the LE falling edge. and the T H hold time from the LE rising edge. The delay to the output changing. TD1. is now referred to the LE falling edge. !; >'" l!i There is no need for a square wave LE clock; LE must only meet the minimum Tw pulse width for successful latch oper· ation. Generally. output timing (desired accuracy of settling) sets the upper limit of usable clock frequency. If off 2531256 Z ~ C ~ 21256 The latches feed data to a row of high current CMOS drivers. which in tum feed a modified R2R ladder network. 11256 8-39 OFFSET 31256 Output Structure The "N" channel (pull down) transistor of each driver plus the bottom "2R" resistor are retumed to VREF· this is the (.) full· scale reference. The "P" channel (pull up) transistor of each driver is retumed to VREF+. the (+) full·scale reference. 1" I _ = IDEAL TRANSFER CURVE .,,. = ACTUAL TRANSFER CURVE 254/256 o 00 01 02 03 FD FE FF INPUT CODE IN HEXADECIMAL (COMP LOW) = FIGURE 3. DlA OFFSET AND GAIN ERROR en II: ~W ~ o o o~ CA3338, CA3338A - _IDEAL TRANSFER CURVE ' ' ' . ACTUAL TRANSFER CURVE ~lli "Glitch" energy is defined as a spurious voltage that occurs as the output is changed from one voltage to another. In a binary input converter. it is usually highest at the most signIficant bit transition (7FHEX to 80HEX for an 8 bit device). and can be measured by displaying the output as the input code alternates around that point. The "glitch" energy Is the area between the actual output display and an ideal one LSB step voltage (subtracting negative area from positive). at either the positive or negative-going step. It is usually expressed in pV-s. t . "J--.: '''''' • -'--- { , : • T INTEGRAL UNEARITY ERROR (SHCM/N -) The CA3338 uses a modified R2R ladder. where the 3 most significant bits drive a bar graph decoder and 7 equally weighted resistors. This makes the "glitch" energy at each 118 scale transition (1 FHEX to 2Ot-iEX. 3FHEX to 40HEX• etc.) essentially equal. and far less than the MSB transition would otherwise display. B II" C c.;;.;;:.:=r--r- o A • IDEAL STEP SIZE (1J255 OF FULL SCALE -"0" SCALE VOLTAGE) B - A. +DlFFERENTIAL UNEARITY ERROR _"'-'IL-_ _ _--=C:.;-;.::A:.:.:.;-.::DI::.F:..:FE:.:.R::E::.:NTI.:.:::AL==U:::NE::AR=ITY:.:..:E::.:R::.:RO:::R~ INPUT CODE 00 FIGURE 4. DlA INTEGRAL AND DIFFERENTIAL LINEARITY ERROR Dynamic Characteristics Keeping the full-scale range (VREF+ - VREF"> as high as possible gives the best linearity and lowest "glitch" energy (referred to W). This provides the best "P" and "N" channel gate drives (hence saturation resistance) and propagation delays. TheVREF+ (and V REF - if bipolar) terminal should be well bypassed as near the chip as possible. For the purpose of comparison to other converters. the output should be resistively divided to 1V full-scale. Figure 5 shows a typical hook-up for checking "glitch" energy or settlingtime. The settling time of the AID is mainly a function of the output resistance (approximately 160n in parallel with the load resistance) and the load plus internal chip capacitance. Both "glitch" energy and settiing time measurements require very good circuit and probe grounding: a probe tip connector such as Tektronix part number 131-0258-00 is recommended. CA3338 +2.5V -2.5V ::E:::::~~~~:~~~+:I::~~~:"'R11v---4-°t~:-n3 ~~ ORBNC CONNECTOR R2 + ANALOG GROUND FUNCTION Oscilloscope Display Match 930 Cable Match 750 Cable Match SOO Cable CONNECTOR R1 R2 R3 Vour (PK-PK) Probe Tip BNC 820 75 620 160 NlC 1V 93 BNC BNC 18 Short 130 75 75 SO tV tV 079V NOTES: 1. Vou,{PK) is approximate. and will vary as RoUT of DlA varies. 2. All drawn capacitors are O.Ij1F multilayer ceramicl4.7l1F tantalum. 3. Dashed connections are for unipolar operation. Solid connection are for bipolar operation. FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT 8-40 CA333B, CA333BA 4V CA3338 1S LE I CLOCK 8 DATA BITS 4V Vour1 . Voo VREf+ 4.71'F ·: ··· · 13 TAN V~N NOTES: 1. Both VREF+ pin and 3920 resistor should be bypassed within '/4 inch. 2. Keep nodal capacitance at CA3450 pin 3 es low as possible. 3. Vour Range = ±3V at CA3450. .eV FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULnPLE COAXIAL LINES VRE.,+ VREFSTEP SIZE 5.12V 5.00V 4.608V 2.56V 2.50V 0 0 -2.56V -2.50V 0.0200V O.0195V O.0180V O.0200V O.0195V o Input Code 111111112 = FFHEX 5.1000V 4.9805V 4.5900V 2.5400V 2.4805V 111111102=FEHEX 5.0800 4.9610 4.5720 2.5200 2.4610 10000001. = 81 HEx 2.5800 1000000~ = 80HEX 2.5600 01111111 2 =7FHEX 2.5400 2.5195 2.5000 2.4805 2.3220 0.0200 0.0195 2.3040 0.0000 0.0000 22860 -0.0200 -0.0195 0000OOOl.=Ol HEX OOOOOOO~ = OOHEX 0.0195 0.0000 0.0180 0.0000 0.0200 0.0000 -2.5400 -2.4805 -2.5600 -2.5000 Applications The output of the CA3338 can be resistively divided to match a doubly terminated SOO or 750 line, although peakto-peak SWings of less than 1V may result. The output magnitude will also vary with the converter's output impedance. Figure 5 shows such an application. Note that because of the HCT input structure, the CA3338 could be operated up to +7.5V Voo and VREF+ supplies and still accept OV to 5V CMOS input voltages. If larger voltage swings or better accuracy is desired, a high speed output buffer, such as the HA-5033, HA-2542, or CA3450, can be employed. Figure 6 shows a typical application, with the output capable of driving f2.V into multiple SOO terminated lines. 8-41 HI-565A ~HARRlS -..J SEMICONDUCTOR High Speed Monolithic D/A Converter with Reference December 1993 Features Description • 12-Blt DAC and Reference on a Single Chip o Pin Compatible With AD565A The HI-565A is a fast, 12 bit current output, digital to analog converter. The monolithic chip includes a precision voltage reference, thin-film R2R ladder, reference control amplifier and twelve high speed bipolar current switches. o Very High Speed: Settles to ±O.5 LSB In 250ns, Max. Full Scale SWitching Time 30ns, Typ. o Guaranteed For Operation With ±12V Supplies The Harris dielectric isolation process· provides latch free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code dependent ground currents. o Monotonlclty Guaranteed Over Temperature o ±O.5 LSB Max. Nonlinearity Guaranteed Over Temp o Low Gain Drift (Max., DAC Plus Ref) 25ppnVOC • Low Power Dissipation 250mW HI·565A dice are laser trimmed for a maximum integral nonlinearity error of ±O.5 LSB at +25 0 C. in addition, the low noise buried zener reference is trimmed both for absolute value and temperature coefficient. Power dissipation is typi· cally 250mW, with ±15V supplies. Applications o CRT Displays o High Speed AID Converters o Signal Reconstruction o Waveform Synthesis The HI·565A is offered in both commercial and military grades. See Ordering InformatiOn. Ordering Information LINEARITY (INL) LINEARITY (DNL) TEMPERATURE RANGE PACKAGE Hll·565AJD·5 0.50LSB 0.75 LSB O"C to +75°C 24 Lead Ceramic Side Brazed DIP Hll·565AKD-5 0.25LSB O.50LSB O"C to +75°C 24 Lead Ceramic Side Brazed DIP HII-565ASD-2 0.50 LSB 0.75 LSB -55°C to +125OC 24 Lead Ceramic Side Brazed DIP HII-565ATD-2 0.25 LSB 0.50 LSB -55°C to + 12SOC 24 Lead Ceramic Side Brazed DIP HII-565ASD/883 0.50LSB 0.50lSB -55°C to +125°C 24 Lead Ceramic Side Brazed DIP HII-565ATD/883 0.25LSB 0.50 LSB -55°C to +125°C 24 lead Ceramic Side Brazed DIP PART NUMBER Functional Diagram Pinout HI.565A (CDIP, SOIC) TOP VIEW NO NO Vcc REF OUT (+10V) REFGND 5 REF IN BIT 1 (MSB) IN BIT 2 IN BIT 3 IN BIT4IN BIP.OFF 4 8 112QV SPAN HI-565A SK IREFO.SmA REF IN 6 1010V SPAN USK SK " lUSK OUT UK 5 -VEE BIPOLAR R IN 8 20VSPAN R 11 POWERGND 12 REF OUT REF GND - 4 BIT 11 IN -VEE PWR MSB GND LSB - 13 BIT 12 (LSB) IN CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 8-42 File Number 3109 Specifications HI-565A Absolute Maximum Ratings Thermal Information VcctoPowerGND •.•.•.....•......•...•••...•• OVto +18V VEE to Power GND •..••.••.•.••................. OV to -18V Voltage on DAC Output (Pin 9) •..•.•••..••.••.••.. -3V to +12V Digital Inputs (Pins 13-24) to Power GND ••.•.••... -W to +7.0V REF In to REF GND .........•......••.........•.•..•.•. ±12V Bipolar Offsetto REF GND •..........•......•....... , ..•. ±12V tOV Span R to REF GND .••....••.....•....•..•......••. ±12V 20V Span R to REF GND ............................•... ±24V REF Out. ..•........•.••...••. Indefinite Short to Power GND Momentary Short to Vee Transistor Count. • . . . . • • • . . . • . . . . • . . . . . • . . . • • . . . • . • .. 200 Process. . . . . . • . . . . . . • • • • • • • • • . . . • • • . . . • • . . . • •. Bipolar-DI Thermal Resistance 8JA 9JC Ceramic Side Brazed DIP Package. . .• . 63"C1W 12"C1W Maximum Package Power Dissipation Ceramic Side Brazed DIP Package •..........••..... SOOmW SOIC Package •....•.•...••.•.•••..••••.•.•..••• SOOmW Operating Temperature Range HI-565AS,T-2 .....•••••••••.••••......•.. -55°C to +125°C H1-565AJ, K-5 ......•.•.....••.•.......••.. OOC to +750 C Junction Temperature •••••.....••.•..•..•........... 175°C Storage Temperature Range ••....•.••.•..•••• -6500 to + 1SOoC Lead Temperature (Soldering 10s) •.............• , •..• +3OOOC CAUTION: Stresses above those Hsted in "Absolute MSJdmum RaUngs" mey causa permenent damage to the dBvic.. This is a stress only raUng and operation of the dBvice at these or any other conditions above thosa indicatsd in the operational sections of this specificaBon is nof implied. Electrical Specifications (TA =+25°C, vee =+15V, VEE =-15V, Unless Otherwise Specified) HI-565AJ, HI565AS HI-565AK, H1-565AT TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNrrS Input Voltage Bit ON Logic "1" (TMIN to TMAX) +2.0 - +5.5 +2.0 +5.5 V Input Voltage Bit OFF Logic "f1' (TMIN to Tr.wcl - +0.8 +0.8 V Logic Current Bit ON Logic "1" (TMIN to TMAX) 0.01 +1.0 0.01 +1.0 Logic Current Bit OFF Logic "0" (TMIN to TMAX> - - -2.0 -20 - -2.0 -20 IIA IIA 12 - - 12 - - Bits PARAMETER DATA INPUTS (Pins 13 to 24) (Note 1) Resolution - OUTPUT U) II: Unipolar Current (All Bits ON) -1.8 -2.0 -2.4 -1.6 -2.0 -2.4 rnA Bipolar Current (All Bits ON or OFF) ±0.8 ±1.0 ±1.2 ±0.8 ±1.0 ±1.2 rnA Resistance (Exclusive of Span Resistors) 1.8K 2.5K 3.2K 1.8K 2.5K 3.2K 0 S; - 0.01 0.05 0.05 %ofF.S. :! Q 0.05 0.15 0.05 0.1 %ofF.S. 20 - - 0.Q1 20 - pF -1.5 - +10 -1.5 - +10 V - to.25 (0.006) to.50 (0.012) - to.12 (0.003) to.12 (0.006) LSB %ofF.8. to.50 (0.012) to.75 (0.018) to.25 (0.006) to.50 (0.012) LSB %ofF.S. to.25 to.50 LSB 2 ppml"C Unipolar Offset at +250 C to.07"C Over Temperature Bipolar Offset at to.2 (T), to.25 (S) Over Temperature (Figure 2, ~ Fixed) =SOO Capacitance Compliance Voltage (TMIN to TMAX> ACCURACY (Error Relative to Full Scale) Integral Non-Linearity (+25°C) End Point Method Integral Non-Linearity (TMIN toTMAX> End Point Method Differential Non-Linearity +2500 Differential Non-Linearity - to.50 ±0.75 - MONOTONICITY GUARANTEED TMINtoTMAX TEMPERATURE COEFFICIENTS Wtth Internal Reference Unipolar Zaro - Wtth Internal Reference Bipolar Zero - With Internal Reference Gain (Full Scale) 843 2 - 5 10 - 5 10 ppml"C 15 40 - 10 25 ppml"C 1 1 ~ W o (,) ! HI·565A Electrical Specifications (TA =+25"C, vee =+15V, vee =-15V, Unless Otherwise Specified) (Continued) HI-565AK, HI-565AT tll-565AJ, HI565AS PARAMETER TEST CONDITIONS With Internal Reference Differential Nonlinearity MIN TYP MAX MIN TYP MAX UNrrs - 2 - - 2 - ppm"'C 350 500 150 250 SETTLING TIME TO ±a.5 LSB With High, Z External Load (Note 2) With 750 External Load - - 350 500 ns 150 250 lIS 15 30 ns 30 SO ns FULL SCALE TRANSITION (From 50% of logic Input to 90% of Analog OUtput) - Rise Time Fall Time 15 30 30 SO 9.0 11.8 -9.5 - POWER REQUIREMENTS Vee (+11.4 to +16.5VDC) VeE (+11.4 to -16.5VDC) - 9.0 11.8 rnA -14.5 - -9.5 -14.5 rnA 3 .10 - 3 10 ppm of F.s.1% 15 25 - 15 25 ppm of F.S.I% POWER SUPPLY GAIN SENSITIVITY (Note 3) Vee (+11.4 to+16.5VDC) Vee (+11.410 -16.5VDC) - PROGRAMMABLE OUTPUT RANGES (See Table 2) Unlpoler 5 (Note 1) Oto+5 oto +5 V Bipolar 5 (Note 1) -2.510 +2.5 -2.5 to +2.5 V Unlpoler 10 (Note 1) 010 +10 oto +10 V Bipolar 10 (Nole 1) -5 to +5 -510+5 V Bipolar 20 (Note 1) -10 to +10 -1010 +10 V EXTERNAL ADJUSTMENTS Gain Error with Fixed 500 Resister for R2 (Figure 1) Bipolar Zero Error with Fixed SOO Resister for R3 (Figure 2) - ±a.l ±a.25 ±a.05 ±a.15 - - ±a.l ±a.25 %ofF.s. ±a.os ±0.1 %ofF.S. ±a.15 - - Gain Adjustment Range (Figure 1) ±a.25 Bipolar Zero Adjustment Range ±a.15 - 15K 20K 25K 15K 20K 25K 9.90 10.00 10.10 9.90 10.00 10.10 V 1.5 2.5 - 1.5 2.5 - rnA ±a.25 %ofF.s. %ofF.S. REFERENCE INPUT Input Impedance - REFERENCE OUTPUT Voltage Current (Available for External Loads) NOTES: 1. Guaranteed by characterization or design but not tested over the operating temparature range. 2. See settling time discussion and Figure 3. 3. The Power Supply Gain Sensitivity Is tested in reference to a Vee. Vee of ±15V. 8-44 HI-565A Definitions of Specifications Digital Inputs The HI-565A accepts digital input codes in binary format and may be user connected for anyone of three binary codes. Straight Binary, Two's Complement (Note 1), or Offset Binary, (See Operating Instructions). TABLE 1. ANALOG OUTPUT DIGITAL INPUT STRAIGHT BINARY OFFSET BINARY Zero -FS (Full Scale) (NOTE 1) TWO'S COMPLEMENT Compliance Voltage Is the maximum output voltage range that can be tolerated and still maintain its specified accuracy. Compliance Limit implies functional operation only, and makes no claims to accuracy. Glitch a glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half-scale or the major carry code transition from 011 ... 1 to 100...0 or vice versa. For example, if turn ON is greater than turn OFF for 011 ... 1 to 100...0, an intermediate state of 000... 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably. MSB..•LSB 000 ..• 000 Detailed Description Zero 100..• 000 112 FS Zero -FS 111 ..• 111 +FS-l LSB +FS·l LSB Zero-I LSB 011 ... 111 112FS -1 LSB Zero· 1 LSB +FS·l LSB op Amp Selection The HI-565As current output may be converted to voltage using the standard connections shown in Figures 1 and 2. The choice of operational amplifier should be reviewed for each application, since a significant trade-off may be made between speed and accuracy. NOTE: 1. Invert MSB with externallnvertllr to obtain 1\Yo's Complement Coding. Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON) (End Point Method). Differential Nonlinearity for a D/A converter, It is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases for an increasing input. Settling Time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within ±a.5 LSB of final value. Gain Drift is the change in full scale analog output over the specified temperature range, expressed in parts per million of full scale range per °C (ppm of FSRloC). Gain error is measured with respect to +250 C at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH -25°C) and low ranges (+25 0 C -Td by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst-case drift. Offset Drift is the change In analog output with all bits OFF over the specified temperature range expressed In parts per million of full scale range per OC (ppm of FSRloC). Offset error is measured with respect to +250 C at high (TH) and low (TL) temperatures. Offset Drift is calculated for both high (TH -25OC) and low (+25OC -TL) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst-case drift. Power Supply Sensitivity Is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V or +15V supplies. It is specified under DC conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of FSR/%). For highest precision, use an HA·5130. This amplifier contributes negligible error, but requires about 11 J.1S to settle within ±a. 1% following a 10V step. The Harris Semiconductor HA-2600 is the best all-around choice for this application, and it settles In 1.5J.1S (also to ±a.l% following a 10V step). Remember, settling time for the DAC amplifier combination is the square root of to2 plus where to. tA are settling times for the DAC and amplifier. tl, No-Trim Operation The HI-565A will perform as specified without calibration adjustments. To operate without calibration, substitute son resistors for the loon trimming potentiometers: In Figure 1 replace R2 with 50n also remove the network on pin 8 and connect 50n to ground. For bipolar operation in Figure 2, replace R3 and R4 with 50n resistors. With these changes, performance is guaranteed as shown under Specifications, "External Adjustments". Typical unipolar zero will be ±a.5 LSB plus the op amp offset. The feedback capacitor C must be selected to minimize settlingtime. Calibration Calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero. For the HI-565A, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. Refer to Table 2 for the voltage output case, along with Figure 1 or Figure 2. Calibration is a two step process for each of the five output ranges shown in Table 2. First adjust the negative full scale (zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e. a1fects each code by the same amount. Next adjust positive FS. This is a gain error adjustment, which rotates the output characteristic about the negative FS value. 8-45 rn II: ~ W z> 8 ~ Q HI-565A For the bipolar ranges, this apprOach leaves an error at ·the zero code, whose maximum value is the same as for integral nonlinearity error. In general, only two values of output may be calibrated exactly; all others must tolerate some error. Choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes. TABLE 2. OPERATING MODES AND CAUBRAnON CIRCUIT CONNECTIONS MODE Unipolar (See Figure 1) Bipolar (See Figure 2) CAUBRAnON OUTPUT PRANGE PIN 10 TO PIN 11 TO ADJUST TO SET Vo Oto+l0V Vo Pin 10 1.431< AilD's Alii's Rl R2 OV +9.99756V Oto+5V Vo Pin 9 1.lK AllO's Alii's Rl R2 OV +4.99678V ±10V NC Vo 1.69K AIIO's Alii's R3 R4 ·10V +9.99512V ±5V Vo Pin 10 1.431< AlIO's AlI1's R3 R4 ·5V +4.99756V ±2.5V Vo Pin 9 UK AIIO's Alil's R3 R4 ·2.5V +2.49878V REF OUT APPLY RESISTOR (R) INPUT CODE BIP. OFF. 8 1001ca R4 10QQ fi R1 +1SV SOIca ·1SV Rf:~8~~~~~~ ::~Q'6+_-+_..I\I\~ 7 12 24 ••• 13 L...-------F USB LSB ,VEE pwR GND FIGURE 1. UNIPOLAR VOLTAGE OUTPUT R3 1000 REF OUT BlP. OFF. 8 R4 1000 HI-56SA IREF Rf:~8~~~~_~ REFq;5'+_-+.......I\I\~ GND 24 ... 13 LSB usa -VEE pwR GND FIGURE 2. BIPOLAR VOLTAGE OUTPUT 8-46 HI-565A Settling Time This is a challenging measurement. in which the result depends on the method chosen. the precision and quality of test equipment and the operating configuration of the DAC (test conditions). As a result. the different techniques in use by converter manulacturers can lead to consistently different results. An engineer should understand the advantage and limitations 01 a given test method before using the specified settling time as a basis for deSign. The approach used for several years at Harris Analog Products Division calls for a strobed comparator to sense final perturbations of the DAC output waveform. This gives the LSB a reasonable magnitude (81411V for the HI-565A). which provides the comparator with enough overdrive to establish an accurate ±O.5 LSB window about the final settled value. Also. the required test conditions simulate the DACs environment for a common application - use in a successive approximation AID converter. Considerable experience has shown this to be a reliable and repeatable way to measure settling time. The usual specification is based on a 10V step. produced by simultaneously switching all bits from off-to-on (IoN) or on-tooff (toFF). The slower of the two cases is specified. as measured from 50% of the digital input transition to the final entry within a window 01 ±O.5 LSB about the settled value. Four measurements characterize a given type of DAC: (a) toN, to final value + Z 0 CJ a VAEFIN .V. BIT6 BIPOLAR 12 BIT 7 IDAC OUT BITe BITI 10V SPAN srr10 20V SPAN POWER GND 8-49 BIT 12 (LSB) BIT 11 (m (.KJ HI-DAC80V HI-DAC85V HARRIS. SEMICONDUCTOR 12-Bit, Low Cost, Monolithic OfA Converter December 1993 Description Features • • • • • • The HI-DAC80V is a monolithic direct replacement for the popular DAC80 and AD DAC80. The HI-DAC85V is a monolithic direct replacement for the. popular DAC85 and. AD DAC85 as well as the HI-5685V. Single chip construction along with several design innovations make the HI-DAC80V the optimum choice for low cost, high reliability applications. Harris' unique Dielectric Isolation (DI) processing reduces internal parasitlcs resulting in fast switching times and minimum glitch. On board span resistors are provided for good tracking over temperature, and are laser trimmed to high accuracy. DAC 80V/DAC 85V Alternative Source MonolithIc Construction Fast Settling TIme 1.5J.lS (typ.) Guaranteed Monotonlclty Wafer Laser Trimmed Unearlty, GaIn, Offset Span Resistors On-Chlp • On-Board Reference • ±12V Supply Operation Applications Intemally the HI-DAC80VIHI-DAC85V eliminates code dependent ground currents by routing current from the positive supply to the intemal ground node, as determined by an auxiliary R2R ladder. This results in a cancellation of code dependent ground currents allowing virtually zero variation in current through the package common, pin 21. • High Speed AID Converters • Precision Instrumentation • CRT Display Generation Ordering Information PART NUMBeR TEMPERATURE RANGE PACKAGE HI3-DA080V-5 O"C to +75"0 24 Lead Plastic DIP HI3-DA080V-7 O"C to +75°0 24 Lead Plastic DIP HI3-DA085V-4 -25"0 to +85°0 24 Lead Plastic DIP HI3-DA085V-9 -40"0 to +85"C 24 Lead Plastic DIP . The HI-DAC80V is available as a voltage output device which is guaranteed over the oOC to +75OC temperature range. An extended bum in screening of 96 hours is available in the HI-DAC80V-7 model. The HI-DAC85V is available as a voltage output device which Is guaranteed over the -25"C to +85OC temperature range. It includes a buried zener reference featuring a low temperature coefficient as well as an on board operational amplifier. The HI-DAC80V requires only two power supplies and win operate In the range of ± (11.4V to 16.5V). Pinout HI-DACBOVJHI-DAC85V (PDIP) TOP VIEW (MSB) BIT 1 I.3VAEFOUT BIT 2 GAIN ADJUST +vs COMMON BIT4 4 BITS 1 BIT 6 20VAANGE BIT 7 BITS 17 BlPOLAAOFFSET 16 AEFINPUT CAUTION: These devices are sensitive 10 electroslatJc discharge. Users should foUow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 8-50 File Number 3110 HI-DACSOV, HI-DACS5V Functional Block Diagram BIPOLAR OFFSET REF IN OUT 10Y SPANR COMMON 6.3K SPAN:!: JUNCTION YOUT 8K GAIN ADJUST 8K -Ys ~ ~ W > z 8 ~ c 8-51 Specifications HI-DAC80V, HI-DAC85V Absolute Maximum Ratings Thennallnformation Power Supply Inputs +Vs ••••••••••.••.•••••••••••••••••••••••••••••• +2OV -Vs•••••••••••.••.•.••••••••••••••••••••••••••••• -20V Reference Input (Pin 16) ••.••.••••••••••••••••••••••••••••••• +Vs Output Drain ••••••.••••••••••••••••••••••••••••• 2.5mA DlgltallnpUls (Bits 1 to 12) ••.•••••.•••••••••.••••. -w to +Vs Process. • • • • • • • • • • • • • • • • • . • . • • • • . • • . • • • • • • • • .• Bipolar-DI Transistor Count. ..•••.•.•..•....•........•.•..•....• 214 Storage Temperature Range •••••••••••.••••• -65"0 to +15O"C Lead Temperature (Soldering 1OS) ••••.••••.••.••••... +3OO"C Thermal Resistance 9JA Plastlc DIP Package ••••••••••••••••••••••••••••• 75"CIW Maximum Power DIssIpation Plastlc DIP Package ••••••••••••••••••••••••••••• 550mW OperaUng Temperature Range HI-DACSOV •••••••••••••••••.•.••.•••••••• O"C to +750 C HI-DAV85V ••.•.••••.•••.••.••••••• , ••••• -40"C to +85°C Max JuncUon Temperature •••.•••••••••.••.•.••••••• +15O"C CAUTION: ~. aWl /h()N Istsd In "Absolute MaxImum RatinflS" may cause ".".,.,.."t damtIge fD /he devk:e. ThIs Is • stress only rating and operation of the device .t these Dl'any oIhsr conditions 8boWI /h()N Ind/catsd In the operatlona/sllClJons of this spec/f/cafon Is not /mpIkKJ. Electrical Specifications TA =+25°C, Vs t12V to t15V (Note 4), Pin 16 to Pin 24, Unless Otherwise Spacilied HI-DACSOV-S, HI-DAC85V-S PARAMETER I TEST CONDITIONS MIN I TYP MAX UNITS - 12 Bits t'/a t3/e LSB SYSTEM PERFORMANCE - Resolution ACCURACY (Note 2) - Unear Error Full Temperature Differential Unearity Error Full Temperature Monotonicity Full Temperature Gain Error Full Temperature (Notes 1, 3) Offset Error Full Temperature (Note 1) I tIe t 12 LSB Guaranteed - to.1 to.3 %FSR to.05 to.15 %FSR ANALOG OUTPUT - OUtput Ranges OUtput Current ±5 - OUtput Resistance Short Circuit Duration To Common ±2.5 ±5 t10 Oto5 - - V V V V - rnA - ±20 ppml"C to.06 to.15 %FSR to.06 to.1 %FSR t15 t30 ppml"C ppml"C Ot010 0.05 Continuous V n - DRIFT (Note 2) Total Bipolar Drift (Includes Gain, Offset and Unearity Drifts) - Full Temperature Total Error Unipolar Full Temperature (Note 5) Bipolar Full Temperature (Note 5) Gain - With Internal Reference - Without Internal Reference Unipolar Offset Bipolar Offset 8-52 t7 - tl ±3 ppml"C ±5 tl0 ppml"C Specifications HI-DACBOV, HI-DACB5V Electrical Specifications TA =+250 C, Vs ±12V to ±15V (Note 4), Pin 16 to Pin 24, Unless Otherwise Specified (Continued) HI-DACBOV·5, HI-DAC85V·5 TYP MAX 3 1.5 - - 1.5 · 10 15 - 6.250 +6.3 6.350 V - 1.5 n External Current - . · +2.5 rnA Tempco of Drift - 5 · ppmf'C - PARAMETER TEST CONDITIONS MIN UNITS CONVERSION SPEED SeltlingTime With 10K Feedback Full Scale Transition All Bits ON to OFF or OFF to ON to ±0.01 % or FSR (Note 2) - - With 5K Feedback For 1 LSB Change Slew Rate lIS lIS lIS VIlIS INTERNAL REFERENCE Output Voltage Output Impedance DIGITAL INPUT (Note 2) Logic Levels Logic "1" TTL Compatible At +1jiA +2 +5.5 V Logic "0" TTL Compatible At -100jiA 0 - +O.S V +15V Supply . 0.001 0.002 %FSR/%Vs -15VSupply - 0.001 0.002 % FSR/% Vs POWER SUPPLY SENSITIVITY (Notes 2, 4) POWER SUPPLY CHARACTERISTICS (Note 4) tJ) Voltage Range IE: +Vs Full Temperature +11.4 +15 +16.5 V -Vs Full Temperature -11.4 -15 ·16.5 V ~W +12 +15 rnA 8 -15 -20 mA Current = =±15V +Is Full Temperature, Vs ±15V -Is Full Temperature, Vs - NOTES: 1. Adjustable to zero USing external potentiometers. 2. See Definitions. 3. FSR is "Full Scale Range: and is 20V for ±1 OV range, 10V for ±5V range, etc. 4. The HI-DACSOVIHI-DAC85Vwilloperate with supply voltages as lowas±11.4V.1tIs recommended that output voltage range-10V to +1 OV not be used If the supply voltages are less than ±12.5V. 5. With Gain and Offset errors adjusted to zero at +250 C Definitions of Specifications TABLE 1. ANALOG OUTPUT Digital Inputs The HI-DAC80V accepts digital input codes in complementary binary, complementary offset binary, and complementary two's complement binary. Settling Time COMPLEMENTARY TWO'S COMPLEMENTt COMPLEMENTARY STRAIGHT BINARY COMPLE· MENTARY OFFSET BINARY 000 .•• 000 + Full Scale + Full Scale -!.SB 100.•• 000 Mid Scale-1 LSB ·1 LSB + Full Scale 111 ••. 111 Zero -Full Scale Zero 011 ••• 111 +1/2 Full Scale Zero - Full Scale DIGrrAL INPUT MSB ••• LSB That interval between application of a digital step input, and final entry of the analog output within a speCified window about the settled value. Harris Semiconductor usually specifies a unipolar 10V full scale step, to be measured from 50% of the input digital transition, and a window of ±1/2 lSB about 8-53 tlnvert MSB wtth externallnvertar to obtain CTC Coding > z ~ c HI-DAC80V, HI-DAC85V the final value. The device output is then rated according to the worst (longest settling) case: low to high, or high to low. In a 12-bit system ±% LSB = ±O.012% of FSR. ' Thermal'DrIft Thermal drift is based on measurements at +25"C, at ,high (T and low (T temperatures. Drift calculations are made for the high (TH -25"C) and low (+25~C-TL) ranges, and the larger of the two values is given as a specification representing worst case drift. w u Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift are calculated in parts per million per °C as follows: GainDrift = AF~~AOC x106 Total Error The net output error resulting from all, internal effects (primarily non-ideal Gain, Offset, Linearity and Reference Voltage). Supply voltages may be set to any values within the specified operating range. Gain and offset errors must be calibrated to zero at +250 C. Then the specified limits for Total Error apply for any input code and for any temperature within the specified operating range. Power Supply Sensitivity Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change inVs, or +Vs supplies. It is specified under DC conditions and expressed as full scale range percent of change divided by power supply percent change. AFull ScaleRange x 100 D'f _ AOffset/AoC 106 Offsetnt FSR x PSS = __F_S....,R..,..,<;.-N_o..."m-=in:;:-a.....:I)__ AV S x100 AVREF/(AOC) ReferenceDrift = 'V x 106 REF AVO/(AOC) rotal BipolarDrift FSR x 10E VS(Nominal) Glitch = = NOTE: FSR Full Scale OUtput Voltage - Zero Scale Output Voltage AFSR = FSR (TH) - FSR (+25"C) or FSR (+250 C) - FSR (TL) VO Steady State response to any input code. = Total Bipolar Drift is the variation of output voltage with temperature, in the bipolar mode of operation. It represents the net effect of drift in Gain, Offset, Linearity and Reference Voltage. Total Bipolar Drift values are calculated, based on measurements as explained above. Gain and Offset need not be calibrated to zero at +25"C. The specified limits for TBD apply for any input code and for any power supply setting within the specified operating range. Accurecv A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half-scale i.e. the major carry code transition from 011 ... 1 to 100...0 or vice versa. For example, if turn ON is greater than OFF for 011 ... 1 to 100...0, an intermediate state of 000...0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably. (Measured as one half the Product of duration and amplitude.) Decoupllng and Grounding For best accuracy and high frequency performance, the grounding and decoupling scheme shown in Figure 1 should be used. Decoupling capaCitors should be connected close to the HI-DAC80VIHI-DAC85V (preferably to the device pins) and should be tantalum or electrolytic bypassed with ceramic types for best high frequency noise rejection. -Vs linearity Error (Short for "Integral Linearity Error:' Also, sometimes called "Integral Nonlinearity" and "Nonlinearity".) The maximum deviation of the actual transfer characteristic from an ideal straight line. The ideal line is positioned according to end-point linearity for D/A converter products from Harris Semiconductor, i.e. the line is drawn between the end-points of the actual transfer characteristic (codes 00.. ,0 and 11 ... 1). Differential Linearity Error The difference between one LSB and the output, voltage change corresponding to any two C9nsecutive codes. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity. Monotonlclty The property of a D/A converter's transfer function which guarantees that the output derivative will not change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a code change is to remain constant, increase for Increasing code, or decrease for decreasing code. O·01 I1F ~I IV_ .. IL 111F 111F " " ~'721 14 22 18 111 r-- 24 20 0 0 0 ---.' 0 0 0 0 0 0 0 0 ........... 0 0 '--- 16 ..- (Note 3) 0.5 0.5 - Degree - 2.0 V - MO 30 1.2 pV-s % REFERENCE INPUT Voltage Reference Input Range Reference Input Resistance (Note 3) 1.0 Input Logic High Voltage, V IH (Note 3) 3.0 Input Logic Low Voltage, V IL (Note 3) Input Logic Current, IlL, IIH (Note 3) Digital Input Capacitance, C IN (Note 3) DIGITAL INPUTS - - V 1.5 V - ±5.0 IIA 5.0 - pF - ns - ns 10 - ns 10 15 ns - - ns TIMING CHARACTERISTICS Data Setup Time, tsu See Figure 1 5 Data Hold Time, tHLD See Figure 1 10 Propagation Delay Time, tpo See Figure 9 Settling Time, tSET (to 112 LSB) See Figure 1 - CLK Pulse Width, T PW1' T PW2 See Figure 1 12.5 8-59 - en a: ~ w z> o (J acr: Specifications HI1171 Electrical Specifications = AVDD = +4.75 to +5.25V, Dlfoo +4.75 to +5.25V, VREF = +2.0V, fs = 40MHz, ClK Pulse Width =12.5ns, TA =+2500 (Note 4). (Continued) PARAMETER TEST CONDITION MIN TYP MAX UNITS 1M 11.5 rnA 4.2 4.8 rnA . 80 mW POWER SUPPLY CHARACTERISITICS IAVDD 14.3MHz, at Color Bar Data Input IDVoo 14.3MHz, at Color Bar Data Input · · Power Dissipation 2000 load at 2Vp•p Output · NOTES: 1. 2. 3. 4. Dissipation rating assumes device Is mounted with all leads soldered to printed circuit board Excludes error due to extemal reference drift. Parameter guaranteed by design or characterization and not production tested. Electrical specifICations guaranteed only under the stated operating conditions. Timing Diagram TPWI :I ,. TPW2 eLK DATA -------10,.... : I : DlAOUT , : tpo ; :~ I !: : !! --------.. . ---.. . . r----·, -----.. . . . ----.. . !---.... " : tpo : r: . -.. ---------------.. . : ! ---- .. -..... -..... ----~----- .. _--------------·50% : I : : tpD : : FIGURE 1. 8·60 --·100% : I ~ ~----O% HI1171 Typical Performance Curves 200~-----------,------------~----~ € w 2.0 ~ ~ W g Ul ::I ::> II. ...5 5 0 1.0 / I.e. / i /V i Veo" s.ov, R =2000 16R =3.3kO, TA =+2S"C 2.0 1.0 ./ ~ 100r------------;------------~~--~ 100 FIGURE 4. OUTPUT FULL SCALE VOLTAGE VB REFERENCE VOLTAGE € w ~ FIGURE 5. OUTPUT RESISTANCE vs GLITCH ENERGY 2.0r-----;------+----~r_----+_----~ :.J ~ i ::I 1.8 r-----;------+----~r_----+_----~ ~ 5 ~ VDD = s.ov, VREF =2.0V R =2000, 16R =3.3ldl O~____~_____L____~TA~=_+~~~o_C~____~ ~ 200 OUTPUT RESISTANCE (0) REFERENCE VOLTAGE (V) 0 ~ " AMBIENT TEMPERATURE ("C) n FIGURE 6. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE 8-61 HI1171 Pin Description 24 PIN SOIC PIN NAME 1-8 DO(LSB) thru D7(MSB) 9 BLNK Blanking line, used to clear the Intarnal data register to the zero condition when High, normal operation when low. 10,13 DVss Digital Ground 11 VB Voltage Bles, connect a 0.1 12 ClK Data Clock Pin 100kHz to 40MHz 14 AVss Analog Ground 15 IREF Current Reference, used to set the current range. Connect a resistor to AVss that is 16 times greater than the resistor on loun. (See Typical Applications Circuit) 16 VREF Input Reference Voltage used to set the output full scale range. 17 VG Voltage Ground, connect a 0.1 j!F capacitor to AVor;;- 18,19,22 AVoo Analog Supply 4.75V to 7V 20 lOUT! Current Output Pin. 21 loun Current Output pin used for a virtual ground connecUon. Usually connected to AVss 23,24 DVoo Digital Supply 4.75V to 7V PIN DESCRIPTION Digital Data Bit 0, the Least Significant BIt thru Digital Data Bit 7, the Most Significant Bit "F capacitor to rNss Detailed Description The HI1171 is an 8 bit, current out D/A converter. The DAC can convert at 40MSPS and run on a single +5V supply. The architecture is an encoded, switched current cell arrangement. Voltage Output Mode The output current of the HI1171 can be converted into a voltage by connecting an external resistor to loon. To calculate the output resistor use the following equation: RoUT =VFS IIFS Clock Phase Relationship The internal latch is closed when the clock line is high. The latch can be cleared by the BLNK line. When BLNK is set (HIGH) the contents of the internal data latch will be cleared. When BlNK is low data is updated by the elK. Noise Reduction where VFS can range from +O.5V to +2.0V and IFS can range from OmA to 15mA In setting the output current the IREF pin should have a resistor connected to it that is 16 times greater than the output resistor. RREF As the values of both RouT and RREF increase, power consumption is decreased, but glitch energy and output settling time is increased. To reduce power supply noise separate analog and digital power supplies should be used with O.1J.lF ceramic capacitors placed as close to the body of the HI1171 as possible. The analog (AVss) and digital (DVss) ground returns should be connected together back at the power supply to ensure proper operation from power up. =16 X RoUT 8-62 HI1171 Test Circuits OSCIllOSCOPE BBIT COUNTER WITH LATCH ClK 40MHz SQUARE WAVE 2000 --------~:_I 3.3Icn FIGURE 7. MAXIMUM CONVERSION SPEED TEST CIRCUIT CONTROLLER 2000 ClK ~MHz--_-----~:_I SQUARE WAVE 3.3Icn FIGURE 8. DC CHARACTERISTICS TEST CIRCUIT 8-63 HI1171 Test Circuits (Continued) 1---------....---1 AVDD OSCIllOSCOPE 2000 CLK 1~Hz------~----------~~ SQUARE WAVE 3.3kn FIGURE 9. PROPAGATION DELAY TIME TEST CIRCUIT 8 BIT COUNTER WITH LATCH •• OSCILLOSCOPE •• 7in ClK 1MHz ,QUARE WAVE 1.2kn FIGURE 10. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT 8-64 H120201, HI20203 10/B-Bit, 160MSPS Ultra High Speed 01A Converter December 1993 Features Description • 160MSPS Throughput Rate The HI20201/03 is a 160MHz ultra high speed D/A converter. The converter is based on an R2R switched current source architecture that includes an input data register with a complement feature and is Emitter Coupled logic (Eel) compatible. • 10 (H120201)" 8 (H120203) Bit Resolution • 0.5 LSB Differential Linearity Error • Low Glitch Noise The H120201 is a 10 bit accurate D/A with a linearity error of 1 lSB. The H120203 is an 8 bit accurate D/A with a linearity error of 0.5 lSB. • Analog Multiplying Function • Low Power Consumption 420mW • Evaluation Board Available The H120201/03 are available in a commercial temperature range and are offered in a 28 lead plastic sOle (300 mil) and a 28 lead plastic DIP package. Applications • Wireless Communications · Ordering Information SI gnal Reconstruct on PART NUMBER • Direct Digital Synthesis TEMPERATURE RANGE PACKAGE 28 Lead SOIC (300 mil) • High Definition Video Systems HI20201JCB -20°C to +75"C • Digital Measurement Systems HI20203JCB ·200 C to +75"C 28 Lead SOIC (300 mil) HI20201JCP ·200 C to +75°C 28 Lead Plastic DIP HI20203JCP ·2000 to +75"C 28 Lead Plastic DIP • Radar Pinout Typical Applications Circuit H120201, HI20203 (POIP, SOIC) HI2G201103 TOP VIEW DIGITAL DATA (ECl) De De (MSS) (1) 08 08(2) 07 07(3) 08 06(4) 05 05(5) 04 04(6) 03 03(7) 02 02(8) D1 D1 (II) DO DO (LSB) (10) (11) - (12) 1310 (27)VREF (26) AVEE O.047"F ~.O"F 750 COAX CABLE (20) lOUT (18,19,21-25) NC W(13) CLK(14) ClK ·1.3V (28) AVss (17) DVss (16)COMPl (15) DVEE - 1.0"F G.047I1F -5.2V 3.6M -5.2V CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 8-65 File Number 3581.1 H120201, HI20203 Functional Block Diagram (lSB) 00 D1 D2 D3 D4 os D6 D7 D8 (MSB)D9 ----- COMPL CLK CLK AVEE AVSS ::I DVEE - .- r--- :.-.. r- .- .r 6LSB'S . r CURRENT CELLS .r--- INPUT BUFFER 8 BIT REGISTER fff- UPPER 4-BIT ENCODER R2.R NETWORK 15 2. r- p ~ .... ~ ~ 15 r! 2. ~ 0 15 SWITCHED CURRENT CELLS loUT T CLOCK BUFFER ~ I DVSS 8-66 BIAS CURRENT GENERATOR VREF Specifications H120201, HI20203 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVEE to DVss ••••••.••......••••• -7.0V Analog Supply Voltage AVDD to AVss •..•..••••••..••.•• -7.0V Digital Input Voltage ..•.••••••••.....•.•.•••••+0.3 to DVEE V Reference Input Voltage .•••.••.•••••.••••••••• +0.3 to AVEE V Output Current ••.•.••.••.•••.........•..••••..•...• 20rnA Storage Temperature Range ••••...•...•..•.. -65°C to +1 SOOC Lead Temperature (Soldering lOs) .................... +300oC Thermal Resistance (Typ, See Note 1) 9JA SOIC Package •..•..•.••..••...•••....••••••.• 700 CIW Plastic DIP Package •••...••••....•.••.....•.•• 600 CIW Maximum Power Dissipation HI20201JCB ..•.•.....•.•••................••.• 575mW H120203JCB ...•••.•..•••..••..•.•••••...•.•••• 575mW Operating Temperature Range •..••...••...•..• -2ooC to +75°C Junction Temperature .....•..•••.•••••.•••••..•..•• +1 SOOC CAUTION: StTesses abo"" thDse listed in "Absolute Msximum Ratings" may cause permanent damage to the davies. This is a stress only tating and opstalion of the devies at these or any other conditions abo"" those Indicated in the opetalionsJ sections of this spscificalion is notlmpHed. Electrical Specifications AVEE = -4.75 to -5.25V, DVEE = -4.75 to -5.25V, VREF = AVEE +0.5 to AVEE +1.5V, fs = 160MHz, Logic Levels VIH = -1.0 to -o.7V, VIL = -1.9 to -1.6V RLOAO = -, VOUT= -W, TA = +250 C (Note 4). HI20203JCBlJCP HI20201JCBlJCP PARAMETER TEST CONDITION MIN TVP MAX MIN TVP MAX UNITS 10 - - 8 - - Bits - ±1.0 LSB ±0.50 - ±0.5 - ±0.50 LSB 7 - - 1.8 - LSB SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fs = 160MHz (End Point) Differential Linearity Error, DNL fs= 160MHz Offset Error, Vos (Adjustable to Zero) (Note 3) - Full Scale Error, FSE (Adjustable to Zero) (Note 3) - - ±102 - - ±26 LSB - - 20 - - 20 rnA 160 - - 160 - - MSPS - 15 - - 15 - pV-s With respect to AVE E +0.5 - +1.4 +0.5 - +1.4 V Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS Throughput Rate See Figure 11 Glitch Energy, GE RoUT =750 REFERENCE INPUT Voltage Reference Input Range Reference Input Current VREF = -4.58V -0.1 -0.4 -3.0 -0.1 -0.4 -3.0 jiA Voltage Reference to Output Small Signal Bandwidth -3dB point IV pop Input - 14.0 - - 14.0 - MHz Output Rise Time, tR RLOAD =750 - 1.5 - - 1.5 - ns Output Fall Time, tF RLOAD =750 - 1.5 - - 1.5 - ns -1.0 -0.89 -1.0 -0.89 DIGITAL INPUTS Input Logic High Voltage, VIH (Note 2) Input Logic Low Voltage, VIL (Note 2) Input Logic Current, IlL IIH (For 09 thru 06, COMPL) (Note 2) VIH =-0.89V VIL = -1.75V 0.1 1.5 Input Logic Current, IlL IIH (For 05 thru DO) (Note 2) VIH =-o.89V VIL =-1.75V 0.1 0.75 -1.75 8-67 -1.6 V -1.75 -1.6 V 6.0 0.1 1.5 6.0 jiA 3.0 0.1 0.75 3.0 jiA Specifications H120201, HI20203 Electrical Specifications = AVEE = -4.75 to-5.25V, DVEE -4.7510 -5.25V, VREF = AVEE +0.5 to AVEE +1.5V, fs = 16oMHz, Logic Levels VIH = -1.0to..().7V, VIL = -1.9to-1.6V RLOAD =-, VOUT= -1Y, TA +25"C (Note4).(Contlnued) = HI20203JCBlJCP H120201 JCBlJCP PARAMETER TEST CONDmON MIN TYP MAX - - MIN TVP MAX UNITS 5 - - ns 1 - - 3.8 - - 4.3 - ns TIMING CHARACTERISTICS Data Setup Time, tsu See Figure 11 5 Data Hold Time, ~LD See Figure 11 1 - Propagation Delay Time, fpo Se.e Figure 11 - 3.8 Settling Tlme,lsET (to 112 LSB) See Figure 11 - 5.2 .a0 -75 -90 .aD -75 -90 rnA - 420 470 - 420 470 mW ns ns POWER SUPPLY CHARACTERISITICS lEE Power Dissipation 750 load NOTES: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board 2. Parameter guaranteed by design or characterization and not production tested. 3. Excludes error due to reference drift. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram ..... eLK .""",''''''......' •• ,"""""' "",1,".,",-" elK DATA tau \ IttD "'""","""4 I -/N+1 N ~ ~ ov ......................................... ~.mo -1V ...( ~ 110% f-sO% f-10% ~ N , N+1 ~ FIGURE 1_ LADDER S.EnLlNG TIME FULL POWER BANDWIDTH (LS) 8-68 HI20201, HI20203 Typical Performance Curves ·2.0 TA • +25oC, VEE .. -5.2V y- ... UNEARAREA ~ ./ ~ 0.5 i.---'" ........ 1"-0.. - ............ RL .. 10kO ......... i.--'" i-""'"" -- - ~ V o , RL·75n ........... ~ ~ 1.0 o 1.5 "- iii 'GAIN feLK • 100MHz ./ 10.0 /~ 0 ..... 1\ iii w II: c:I PHASE , " -90 ~ w ~ :z: ... ·180 -20 10K ........ 20 40 60 AMBIENT TEMPERATURE ("C) ;: 8.0 ~ - FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT TEMPERATURE FIGURE 2. VO(FS) RATIO vs (VREF"VEE) iz ·10 RLoo10kO_ f""".,. RLoo75n VREF"VEEM o ~ V .!!. ~w z w :z: ...u ::I 6.0 4.0 c:I 2.0 ./ V -so 100K 1M 10M 100M MULTIPLYING INPUT SIGNAL FREQUENCY (Hz) FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING INPUT SIGNAL FREQUENCY V ./ 0 50 CASE TEMPERATURE ("C) 100 FIGURE 5. GLITCH ENERGYvs CASE TEMPERATURE (FULL SCALE·1023mV) 8·69 HI20201, HI20203 Pin Description 28 PIN SOIC 1-10 11,12,19, 21- 25 13 14 15 16 PIN NAME DO (LSB)-D9 (MSB) NC ClK ClK DVEE COMPl DVss AVss 17 18 20 26 27 28 101lT AVEE VREF AVss PIN DESCRIPTION Digital Data Bit 0, the least Significant Bit tlvu Digital Data Bit 9, the Most Significant Bit. No connect, not used. NegatiVe differential Clock input Positive differential Clock Input Digital (ECl) Power Supply -4.75V to -7V. Data Complement Pin. When set to a (ECl) logic High the input data Is complemented in the Input buffer. When cleared to a (ECl) logic low the Input data Is not complemented. Digital Ground Analog Ground Current Output Pin. Analog Supply -4.75V to -7V. Input Reference Voltage used to set the output full scale range. Analog Ground Detailed Description TheHI20201 isa 10bit,currentoutputDlAconverter. The DAC can run at 160MSPS and is ECl compatible. The architecture is sagmentedlA2R combination to reduce glitch and improve linearity. The HI20203 is an 8 bit, current output D/A converter. The converter has 10 data bits but yields 8 bit performance. Architecture The HI202OI031 is a combined R2R1segmented current source design. The 6 least significant bits of the converter are derived by a traditional R2R network to binary weight the 1rnA current sources. The upper 4 most significant bits are implemented as segmented or thermometer encoded current sources. The encoder converts the incoming 4 bits to 15 control Ones to enable the most significant current sources. The thermometer encoder will convert binary to individual control lines. See Table 1. TABLE 1. THERMOMETER ENCODER THERMOMETER CODE 1 =ON,O=OFF MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 8 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 7 0 0 1 1 0 0 1 1 0 0 1 .1 0 0 1 1 BIT 6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 115 -10 000 0000 0000 0000 00000000000 0001 000 0000 0000 0011 000 0000 0000 0111 000 0000 0000 1111 000000000011111 000000000111111 000000001111111 000000011111111 000000111111111 000001111111111 000011111111111 000111111111111 001111111111111 011111111111111 111111111111111 The architecture of the HI20201/03 is designed to minimize glitch while providing a manufacturable 10 bit design that does not require laser trimming to achieve good linearity. Glitch Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the tum off time is faster than the turn on time (TTL designs). In an ECl system where the logic levels switch from one non-saturated level to another, the switching times can be considered close to symmetrical. This helps to reduce glitch in the D/A. Unequal delay paths through the device can also cause one current source to change before another. To minimize this the Harris H1202011 03 employes an internal register, just prior to the current sources, that is updated on the clock edge. lastly the worst case glitch usually happens at the major transition i.e. 01 1111 1111 to 10 0000 0000. But in the HI20201/03 the glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. This is achieved by the split A2R1segmented current source architecture. This decreases the amount of current switching at anyone time and makes the glitch practically constant over the entire output range. By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. In measuring the output glitch of the H120201103 the output is terminated into a 750 load. The glitch is measured at the major carry's throughout the DACs output range. HI20201/03 34 MHz LOW PASS FILTER (20) lOUT 75n 'i7 r!£O PE son 'i7 FIGURE 6. HI20201103 GLITCH TEST CIRCUIT 8-70 H120201, HI20203 The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 7 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt-seconds (pV-sec). Integral Unearlty The Integral Linearity is measured using the End Point method. In the End Point method the gain is adjusted. A line is then established from the zero point to the end point or Full Scale of the converter. All codes along the transfer curve must fall within an error band of 1 lSB of the line. Figure 10 shows the linearity test circuit. Differential Unearlty , A(mV) The Differential Linearity is the difference from the ideal step. To guarantee monotonicity a maximum of 1 lSB differential error is allowed. When more than 1 lSB is specified the converter is considered to be missing codes. Figure 10 shows the linearity test circuit. GUTCH ENERGY = (a x t)/2 !,, Clock Phase Relationship , ,, , The H120201/03 are designed to be operated at very high speed (i.e. 160MHz). The clock lines should be driven with ECl lOOK logic for full performance. Any external data drivers and clock drivers should be terminated with 50n to minimize reflections and ringing. ~ °t(ns) • Internal Data Register FIGURE 7. GLITCH ENERGY Setting Full Scale The Full Scale output voltage is set by the Voltage Reference pin (27). The output voltage performance will vary as shown In Figure 2. The HI20201/03 incorporates a data register as shown in the Functional Block Diagram. This register is updated on the rising edge of the ClK line. The state of the Complement bit (COMPL) will determine the data coding. See Table 2. TABLE 2. INPUT CODING TABLE The output structure of the H120201 can handle down to a 75n load effectively. To drive a 50n load Figure 8 is suggested. Note the equivalent output load is -750. HI20201/03 380 OUTPUT CODE INPUT CODE COMPL= 1 00 00000000 0 COMPL=O -1 1000000000 -0.5 -0.5 1111111111 -1 0 Thermal Considerations 500 COAX CABLE (20) loUT J-!Mf..-r~Dl~A~O~UT!] The temperature coefficient of the full scale output voltage and zero offset voltage depend on the load resistance connected to lOUT. The larger the load resistor the better (i.e. smaller) the temperature coefficient of the D/A. See Figure 3 in the performance curves section. 1000 --+ (18,19,21-25) NC 1 - - -.... Noise Reduction Digital switching noise must be minimized to guarantee system specifications. Since 1 lSB corresponds to 1mV for 10 bit resolution, care must be taken in the layout of a circuit board. FIGURE 8. HI20201103 DRIVING A 50n LOAD Variable AHenuator Capability The HI20201/03 can be used in a multiplying mode with a variable frequency input on the VREF pin. In order for the part to operate correctly a DC bias must be applied and the incoming AC signal should be coupled to the V REF pin. See Figure 13 for the application circuit. The user must first adjust the DC reference voltage. The incoming signal must be attenuated so as not to exceed the maximum (+1.4V) and minimum (+0.5V) reference input. The typical output Small Signal Bandwidth is 14MHz. Separate ground planes should be used for DVss and AVss. They should be connected back at the power supply. Separate power planes should be used for DVEE and AVEE. They should be decoupled with a 11lF tantalum capacitor and a ceramic 0.0471lF capacitor positioned as close to the body of the IC as possible. 8-71 HI20201, HI20203 Test Circuits S.2V iiJT, FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE UNEARrrY ERRORS ARE MEASURED AS FOLLOWS S1 S2 S3 S9 S10 DlAOUT .... 0 0 0 0 0 0 0 0 0 .... .... .... 0 0 1 0 1 0 Va V, V2 1 1 1 ·· .... 1 1 V'023 · INTEGRAL LINEARITY ERROR ·· DIFFERENTIAL LINEARITY ERROR Va V, V2 V4 Va Vle V32 V84 V'28 V'92 V,-Vo V2-V, V4 -V3 Va- V7 V,e-V,s V32 - V3l V84 - Vea Vl28 - V127 V'92- V'8' ·· ·· VW) Vw)- V858 V'023 Error at Individual measurement points are calculated according to the following definition. (Vl023 - VoV1023 =VO(Fsy1023 FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR 8-72 .. 1 LSB. H120201, HI20203 Test Circuits (Continued) bt. 1" HD100151 2 o 82 Q Q 131 131 -S.2V -5.2V CLKF -5.2V DL: Delay line -1.3V Capacitors are O.047I1F ceramic chip capacitors unless otherwise specified. FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND SETIUNGTIME ~ ~ Q V = VO(FS) (1 - e·ft ). The settling time for respective accuracy of 10, 9 and 8-bit is specified as =0.9995 VO(FS) =0.999 VO(FS) =0.999 VO(FS) which results in the following: = = 1 for 1O-bit, for 9-bit, and for a-bit, ! Rise time (tR) and fall time (tF) are defined as the time interval to slew from 10% to 90% of full scale voltage (VO(FS»: V V =0.1 VO(FS) =0.9 VO(FS) and calculated as tR =3.45tR =3.15tR =6.241R V 1 ..···········..···..·····t··········· ............................. t---: FIGURE 12. DlA OUTPUT WAVEFORM =tF =2.20't. The settling time is obtained by combining these expressions: ts Is ts ~ o (.) Settling time is measured as follows. The relationship between V and VO(FS) as shown in the D/A output waveform in Figure 12 is expressed as ts 7. 60't Is 6.93't Is = 6.24't II: W Measuring Settling Time V V V t/) for 1Q-bit, for 9-bit, and for 8-bit 8-73 H120201, HI20203 Test Circuits (Continued) Adjust so that the voltage at point B becomes -1 V with no AC input. O.1~ 1----;-... ~ 51 TO SCOPE ~ CLK AGND FIGURE 13A. At..------lIirV---.. .-. WAVEFORM AT POINT A .. '7 .. .-..-. ..-... : : : : : FIGURE 13B. WAVEFORM AT POINT B FIGURE 13C. FIGURE 13. MULTIPLYING BANDWIDTH 8-74 nb DGND DATA ACQUISITION 9 SWITCHES PAGE SWITCHES SELECTION GUIDES •.••.•.•..........................................•............ SINGLE POLE SINGLE THROW (SPST, FIGURE 1) .•..•..........•.•.........••.....•.••....... 9·3 9·3 DUAL SINGLE POLE SINGLE THROW (2 x SPST, FIGURE 2) .................................... . 9·3 QUAD SINGLE POLE SINGLE THROW (4 x SPST, FIGURE 3) .................................... . 9·5 (4PST, FIGURE 4) .......................•....................... 9·6 FOUR POLE SINGLE THROW SINGLE POLE DOUBLE THROW (SPOT, FIGURE 5) .•.....••......••••....•........•......•.... 9·7 (2 x SPOT, FIGURE 6) ......... ; ......................... . 9·7 (DPST, FIGURE 7) .........•.......••....•.............•...... 9·8 DUAL DOUBLE POLE SINGLE THROW (2 x DPST, FIGURE 8) ••....••••...•.••....•.•............ 9·9 DUAL DOUBLE POLE DOUBLE THROW (2 x DPDT, FIGURE 9) ........•.............•....•....... 9·10 ("l" SWITCH, FIGURE 10) ........•...•......•...•..........•........ 9·10 DUAL SINGLE POLE DOUBLE THROW DOUBLE POLE SINGLE THROW RFNIDEO "l" SWITCHES 0, SWITCHES DATA SHEETS (I) W ::E: DG200, DG201 CMOS DuaVQuad SPST Analog Switches ....•.............••.•.....•............... 9·13 00201 A, 00202 Quad SPST CMOS Analog Switches ............••.•........•....•.......••........ 9·21 DG211, DG212 SPST 4 Channel Analog Switch .....•..•...........•..••........•..•.•..•......... 9·25 DG300A, DG301A, DG302A, DG303A TTL Compatible CMOS Analog Switches .•......................•.......••...••...•• 9·30 DG308A, DG309 Quad Monolithic SPST CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 DG401, DG403, DG405 Monolithic CMOS Analog Switches •. . . . . . . . . . . • . . • . . • . . . • • . . . • . . . . . . . . . . . . . . . . . . 9·42 ~ (I) NOTE: Bold Type Designates a New Product from Harrts. 9-1 Switches (Continued) PAGE 00411, 00412, , 00413 MonolHhlc Quad SPSTCMOS Analog Swltche8 ......•.•...•••.• ' ..•..•.• '. • • • . . • • . . 9-44 OG441 , OG4:42 Monolithic Quad SPST CMOS Analog SWitche8 . . . . . . . . • . • . . . • • . • • • • • • • • . • . • • • . . . . . 9-53 OG444, OG445 Monolithic Quad SPST CMOS Analog SWitChe8 . • • . • • . . . . • • . . • . . • • • • • • • . • . • . . • . . .. • 9-63 HI-200, HI-201 DuaVQuad SPST CMOS Analog Switches. • . • . . . . . . . . . . . . . . . . . . . • • • . . • • . . . . • . . . . . . . • 9-73 HI-201 HS High Speed Quad SPST CMOS Analog Switch. . . . • • • . • . • . . . • . • • . . . . . . . . . . . . . . . . . • . . . 9-82 HI-300 thru HI-307 CMOS Analog Switches. . • • . • . • . • . • . . . • . . . • . . . . . . . . . . . . . . • . . • • . . . • . . . • • • . • . • . . . . 9-93 HI-381 thru HI-390 CMOS Analog Switches... . . . ..• .• .•.•. ....•.. . . . .. ..•.• . .... . . . .. . .. ... .. ... . . . 9-103 HI-5040 thru CMOS Analog Switches. . . . . . . . . . . . • . . • • . . • • . • . • • • . . . . • . . . . . . . . . • . • • . . . . • . . . . . . . HI-5051, HI-5046A and HI-5047A 9-110 IH5043 Dual SPOT CMOS Analog Switch. • • • . • . . • . . . . . • • . . . • • . . . • . • . • • • . . . . . . • • . . . . . . . . . . 9-121 IH5052, IH5053 Quad CMOS Analog Switch..... •.••. . . . •. . •. ••• . . .••••••••••. . . •. . . • . ..• . . .• . . . . 9-128 IH5140 thru IH5145 High-Level CMOS Analog Switch ••••••••••••.••...••••••••.•. . •••. . • . . . . • . . . . . . . 9-134 IH5151 Dual SPOT CMOS Analog Switch. . • . • . • • . • • . • . . • • • • . . . . . . . . . . • . • .. . • . .. . . . . • . . . •• ' 9-147 IH5341, IH5352 Dual SPST, Quad SPST CMOS RFNideo Switches • • • . • . . . . • • • . . . • . • . . . • . . . . . . . . . • • . • 9-155 NOTE: Bold Type Designates a New Product from Harris. 9-2 ~. SINGLE POLE SINGLE THROW (NOTES2,3) DEVICE Hll-5040 IH5140 l: SUFFIX CODES -2, -5,-7 MJE,CJE, CPE (SPST, FIGURE 1) (NOTE 1) RDS(ON) n MAX SWITCH "ON" (V) SWITCH "OFF"M TECHNOLOGY IsoFF(±nA) TYP TON (n8) TVP TOFF (n8) TYP HI1-50401883 75 3.0 0.8 36VCMOS-DI 0.8 370 280 IH514OMJEl883B 75 2.4 0.8 36VCMOS.J1 5.0 175 150 50 4.0 0.8 44VCMOS-DI 0.04 210 160 Very Low Leakage, TTL Inpu1s 50 11.0 3.5 44VCMOS-DI 0.04 160 100 CMOS Logic Very Low Leakage MIL SPEC Hll-0301 -2,-5,-7 Hll-0301/883 HI2-0301 -2,-5 H12-0301/883 HI3-0301 -5 HI9P0301 -5 HI9P0301 -9 HI1-0305 -2,-5 Hll-0305I883 HI2-0305I883 HI2-0305 -2,-5 HI3-0305 -5 HI9P0305 -5 HI9P0305 -9 tJ) SUFFIX CODES CD 2_. ::J G) _. MIL SPEC C Q. (2 X SPST, FIGURE 2) (I) (NOTE 1) RDS(oN) n MAX SWITCH "ON"M SWITCH "OFF"M IsoFF(±nA) TYP TON (n8) TECHNOLOGY TYP TOFF (n8) TYP DG200 AA,AK BA,BK CK DG200AAl883B DG200AKI883B 80 2.4 0.8 36VCMOS-JI 5.0 1000 500 DG300A AA,AK BA,BK CJ,CK DG300AAAl883B DG300AAKI883B 50 4.0 0.8 44VCMOS-JI 0.1 150 130 DJ,DY DG401AKI883 45 2.4 0.8 44VCMOS.J1 -0.01 100 60 DG401 (I) o DUAL SINGLE POLE SINGLE THROW (NOTES2,3) DEVICE FEATURES ------ ~ SWITCHES __ I FEATURES Very Low ROS{ON) DUAL SINGLE POLE SINGLE THROW (2 x SPST, FIGURE 2) (Continued) (NOTES 2,3) DEVICE ~ SUFFIX CODES MIL SPEC Hll-0200 -2, -4, -5, -7 Hll-02OO1883 H12-0200 -2, -4, -5, -7 HI2-02OOI883 HI3-0200 -5 HI9P0200 -5, -9 Hll-0300 -2, -5 Hll-0300I883 H12-0300I883 H12-0300 -2, -5 HI3-0300 -5 HI9P0300 • -5,-9 H11-0304 -2,-5 HI1-03041883 H12-0304 -2,-5 HI2-03041883 HI3-0304 -5 HI9P0304 -5,-9 H11-0381 -2,-5 HI1-03811883 H12-0381 -2,-5 HI2-03811883 HI3-0381 -5 HI9P0381 -5, -9 HI 1-5041 -5 HI 1-5048 -2, -5,-7 HI3-5048 -5 SWITCH "ON"M SWITCH "OFF' (V) TECHNOLOGY TYP TON (ns) TYP TOFF(ns) TYP 80 0.8 2.4 44VCMOS-OI 1.0 240 500 50 4.0 0.8 44VCMOS-OI 0.04 210 160 IsoFF(±nA) FEATURES Very Low Leakage en CD 50 11.0 3.5 44VCMOS-OI 0.04 160 100 ...iDo_. (") CMOS Logic Very Low Leakage :s C') 50 4.0 0.8 44VCMOS-OI 0.04 210 160 c ii Very Low Leakage CD ng -2, -5, -7, -8 HI1-50411883 HI3-5041 (NOTE 1) RDS(oN) 0 MAX HI1-50481883 75 3.0 0.8 36VCMOS-OI 0.8 370 280 100 ROS(ON) Matching 45 3.0 0.8 36VCMOS-OI 0.8 370 280 50 ROS(ON) Matching !f Ii a I 1H5141MJEl8838 IH5141 CJE,CPE MJE IH5341 CPO,ITW, 1H5341 MTW18838 MTW 75 2.4 0.8 36VCMOS..J1 5.0 150 125 75 2.4 0.8 36VCMOS..J1 1.0 150 80 I RF Video T-Switch QUAD SINGLE POLE SINGLE THROW (4 x SPST, FIGURE 3) (NOTES2,3) DEVICE 00201 (NOTE I) RDS(oN) n MAX SWITCH "ON" (V) SWITCH "OFF"(V) TECHNOLOGY ISOFF(±nA) TYP TON (ns) TVP TOFF (ns) TYP 100 2.4 O.B 36VCMOS-J1 0.01 480 370 Very Low Leakage DG201AAKI883B 115 Typ O.B 2.4 44VCMOS-J1 0.01 480 370 Very Low Leakage DG202AKlBB3B 115 Typ 2.4 O.B 44VCMOS-J1 0.01 480 370 MIL SPEC AK,BK,CJ oo2OIAKI883B FEATURES 00201 A AK,BK, CJ,CK 00201 A BY,CY 00202 AK,BK, CJ,CK 00211 CJ,CY 150 Typ O.B 2.4 44VCMOS-J1 0.01 460 360 Low Cost 00212 CJ,CY 150Typ 2.4 O.B 44VCMOS-J1 0.01 460 360 Low Cost AK,BK DG3OBAAKlBB3B CJ,CK,CY 60Typ 11.0 3.5 44VCMOS-J1 0.01 130 90 AK, BK, DG309AKlBB3B CJ,CK,CY 60Typ 3.5 11.0 44VCMOS-JI 0.1 130 90 CMOS Logic, Single or Dual Supply Operation 35 2.4 O.B 44VCMOS-J1 -0.1 110 100 Very Low ROS(ON) O.B 44VCMOS-J1 -0.1 110 100 Very Low ROS(ON) oo3OBA 00309 ~ SUFFIX CODES DG411 DJ,DY DG411AKlBB3 CMOS Logic, Single or Dual Supply Operation en CD CD n ~ o ::J C) C Do CD -. DG412 DJ,DY DG412AKI883 35 2.4 00413 DJ,DY oo413AK1883 35 2.4 O.B 44VCMOS-J1 -0.1 110 100 Very Low ROS(ON) 00441 DJ,DY DG441AKlBB3 B5 2.4 O.B 44VCMOS-J1 0.01 150 90 ng Low ROS(ON)' Low Leakage §f 00442 DJ,DY DG442AKlBB3 B5 2.4 O.B 44VCMOS-J1 0.01 150 110 Low ROS(ON)' Low Leakage .s 00444 DJ,DY B5 2.4 O.B 44VCMOS-J1 0.01 150 90 Low ROS(ON)' Low Leakage DG445 DJ,DY B5 2.4 O.B 44VCMOS-J1 0.01 150 110 Low ROS(ON)' Low Leakage eo 0.8 2.4 44VCMOS-DI 2.0 185 220 Hll-0201 -2, -4, -5, -7,-8 HI3-0201 -5 HI4P0201 -5 HI9P0201 -5,-9 Hll-020118B3 HI4-0201/883 I. S~TC~ES ___ lu c QUAD SINGLE POLE SINGLE THROW (NOTES2,3) DEVICE SUFFIX CODES HI1-0201HS -2, -4, -5, -7, -8 HI3-0201HS -4,-5 HI4P0201HS -5 HI9P0201HS -5, -9 MIL SPEC HIH)201 HS/883 (4 x SPST, FIGURE 3) (Continued) (NOTE 1) ROS(ON) 0 MAX SWITCH "ON" (V) SWITCH "OFF" (V) TECHNOLOGY TYP TON (ns) TVP TOFF (ns) TYP 50 0.8 2.4 33VCMOS-OI 0.3 30 40 IsoFF(±nA) FEATURES High Speed, Low ROS(ON) en CD HI4-0201 HS/883 a: IH5052 COE,MOE 80 0.8 2.4 36VCMOS-J1 5.0 1000 500 IH5053 COE,MOE 80 2.4 0.8 36VCMOS-JI 5.0 1000 SOO IH5352 CPE,IJE, MJE 75 2.4 0.8 36VCMOS-J1 2.0 150 80 IH5352MJEI883S CD (') ~ RF Video T-Switch o ::s CSP,ISP IH5352 C) _. -- c FOUR POLE SINGLE THROW (NOTES2,3) DEVICE SUFFIX CODES HI1-5047 -2, -5,-7 HI3-5047 -5 HI1-5047A MIL SPEC HI1-50471883 -2, -5, -7,-8 HI1-5047A1883 HI3-5047A -5 HI4P5047A -5 a. (4PST, FIGURE 4) ----- CD n (NOTE 1) RDS(oN) 0 MAX SWITCH "ON" (V) SWITCH "OFF" (V) ISOFF(±nA) TYP TON (ns) TECHNOLOGY TYP TOFF (ns) TYP 75 3.0 0.8 36VCMOS-JI 0.8 370 280 100 Max ROS(ON) Matching 45 3.0 0.8 36VCMOS-J1 0.8 370 280 50 Max ROS(ON) Matching ! FEATURES I I SINGLE POLE DOUBLE THROW (SPOT, FIGURE 5) (NOTES 2, 3) DEVICE 00301 A ~ SUFFIX CODES MIL SPEC AA,AK DG301 AAA/8838 BA,BK 00301 AAKI883B CA,CJ,CK DG303A BY,CY HI1-Q387 -2,-5 H11-Q3871883 H12-o387 -2, -5 HI2"()3871883 HI3-0387 -5 H19P0387 -5 HI 1-5042 -2,-5, -7 HI3-5042 -5 HI1-5050 -2,-5, -7 HI3-5050 -5 (NOTE 1) RDS(ON) 0 MAX SWITCH "ON" (V) SWITCH "OFP' (V) TECHNOLOGY IsOFF(±nA) TYP TON (ns) TVP TOFF(ns) TYP 50 2.4 0.8 44VCMOS-J1 0.1 150 130 Channel 1 "ON", Channel 2 "oFF", TTL Inputs 50 4.0 0.8 44VCMOS-DI 0.04 210 160 Channel 1 "ON", Channel 2 "oFF", Very Low Leakage FEATURES en (I) ...o_. iD n HI1-50421883 H11-505OI883 75 3.0 45 0.8 3.0 36VCMOS-DI 0.8 36VCMOS-DI 0.8 0.8 370 370 280 280 Channel 1 "ON", Channel 2 "OFF", 100 Max RDS Matching Channel 1 "ON", Channel 2 "OFF", 50 Max RDS Matching :s C) c c: (I) "0 DUAL SINGLE POLE DOUBLE THROW (2 X SPOT, FIGURE 6) (NOTES 2, 3) DEVICE ~ ~ c (NOTE 1) RDS(ON) 0 MAX SWITCH "ON" (V) SWITCH "OFF" (V) SUFFIX CODES MIL SPEC DJ,DY DG403AK/883 45 2.4 0.8 44VCMOS-J1 HI1-Q303 -2, -5 H11·0303I883 50 4.0 0.8 44VCMOS-DI HI3-Q303 -5 HI9P0303 -5,-9 DG403 ~ - -S~IT~~E~ ISOFF(±nA) TECHNOLOGY TYP -I TON (ns) TVP ToFF(ns) TYP -0.01 100 60 0.04 210 160 FEATURES Channel 1 "ON", Channel 2 "OFF", Very Low Leakage, TTL Inputs ! DUAL SINGLE POLE DOUBLE THROW (2 (NOTES 2, 3) DEVICE co a, SUFFIX CODES HI1-0307 -2,-5,-7 HI3-0307 -5 HI9P0307 -5,-9 Hll-0390 -2,-5 HI3-0390 -5 HI9P0390 -5,-9 HI1-5043 -2, -5-8 HI3-5043 -5 H19P5043 -5,-9 H13-5051 SPDT, FIGURE 6) (Continued) (NOTE 1) RDS(ON)n MAX SWITCH "ON" (V) SWITCH "OFF" (V) TECHNOLOGY IsoFF(±nA) TYP TON (ns) TVP TOFdns) TYP H11-0307/883 50 11.0 3.5 44VCMOS-DI 0.04 160 100 Channell 'ON", Channel 2 'OFP, Very Low Leakage HI 1-0390/883 50 4.0 0.8 44VCMOS-DI 0.04 210 160 Channell 'ON", Channel 2 'OFP, Very Low Leakage HI 1-50431883 75 2.4 0.8 36VCMOS-DI 0.8 370 MIL SPEC CD 280 -5 HI9P5051 -5,-9 CDE,CJE, CPE, CY, MJE IH5043 45 3.0 0.8 36VCMOS-DI 0.84 370 280 HI1-5044 -2, -5,-7 HI3-5044 -5 CJE,CPE, MJE IH5144 - - ::J C) Channell 'ON" Channel 2 'OFP 5n Max ROS(ON) Matching _. s::: CD , IH5043MJEl8838 DOUBLE POLE SINGLE THROW SUFFIX CODES ~ a. --- (NOTES 2, 3) DEVICE CD (') Channell 'ON" Channel 2 'OFP 10n Max ROS(ON) Matching o -5 HI4P5051 FEATURES en -2, -5, -7, -8 HI1-5051/883 H11-5051 x - 3.0 80 ---- ---- 0.8 - -_ .. _ - - 36VMCOS-JI - ---- 5.0 ----- - - - 1000 - 500 g Channell 'ON" Channel 2 'OFP ~ c(1) .s - (DPST, FIGURE 7) (NOTE 1) RDS(ON) n MAX SWITCH "ON" (V) SWITCH "OFF" (V) TECHNOLOGY ISOFF(±nA) TYP TON (ns) TVP TOFF (ns) TYP H11-50441883 75 3.0 0.8 36VCMOS-DI 0.8 370 2BO IH5144MJEl8838 75 2.4 0.8 36VCMOS-JI 5.0 250 150 MIL SPEC '0 FEATURES 10n Max ROS(ON) Matching -- DUAL DOUBLE POLE SINGLE THROW (NOTES 2,3) DEVICE :g (2 x DPST, FIGURE 8) (NOTE 1) RDS(ON) a SUFFIX CODES MAX SWITCH "ON" (V) SWITCH "OFF" (V) TECHNOLOGY TYP TON (ns) TVP TOFF (ns) MIL SPEC ISOFF(±nA) TYP FEATURES DG302A AK, BI<, CI<,CJ DG302AAKl883B 50 4.0 0.8 44VCMOS-J1 0.1 150 130 TTL Inputs DG405 DJ,DY DG405AKl883 45 2.4 0.8 44VCMOS-J1 -0.01 100 60 Very Low ROS(ON) HI1-Q302 -2,-5 HI1-0302I883 50 4.0 0.8 44VCMOS-DI 0.1 210 160 TTL Inputs HI3-Q302 -5 H19P0302 -5, -9 HI1-0306 -2,-5 HI1-0306l883 50 11.0 3.5 44VCMOS-DI 0.1 160 100 CMOS Logic H13-0306 -5 HI9P0306 -5,-9 HI1-0384 -2,-5 HI3-0384 -5 HI9P0384 -5,-9 HI1-5045 -2, -5,-7 HI3-5045 -5 -5,-9 HI1-5049 -2,-5, -7 HI3-5049 -5 IH5145 CD .... n _. o HI1-03841883 4.0 50 44VCMOS-DI 0.8 0.04 210 160 Very Low Leakage ::::J C) C c: CD HI1-5045I883 75 4.0 0.8 36VCMOS-DI 0.04 210 160 Very Low Leakage HII-5049I883 CJE,CPE, IH5145MJEl883B MJE i ::I C CD .s HI4-50451883 H195045 en CD 45 3.0 0.8 36VCMOS-DI 0.8 370 280 75 2.4 0.8 36VCMOS-JI 5.0 150 125 - I - SWITCHES -- ------------ - - - - -- - • ---- .- 5a ROS(ON) Matching DUAL DOUBLE POLE DOUBLE THROW (2 X DPDT, FIGURE 9) (NOTES2,3) DEVICE (NOTE 1) RDS(oN) 0 SUFFIX CODES Hll-5046 -2, -5,-7 H13-5046 -5 Hll-5046A -2,-5, -7 HI3-5046A -5 MAX SWITCH "ON" (V) SWITCH "OFF" (V) TECHNOLOGY ISOFF(tnA) TYP TON (ns) TVP TOFF(ns) TYP HI1-50461883 75 0.8 2.4 36VCMOS-OI 0.8 370 280 Channel 1 "ON" Channel 2 "OFP 100 Max Ao8(ON) Matching HI1-5046AI883 45 3.0 0.8 36VCMOS-OI 0.8 370 280 Channel 1 "ON" Channel 2 "OFP 50 Max RDS(ON) Ma1l:hing MIL SPEC RFNIDEO "r' SWITCHES (NOTES2,3) DEVICE 1H5341 ~ o SUFFIX CODES ("r' SWITCH, FIGURE 10) MIL SPEC IlW,M1W IH5341M1W/883B IH5341 CPO IH5352 IJE,MJE IH5352 CPE IH5352 CBP IH5352 IBP FEATURES 1H5352MJEl883B , (NOTE 1) RDS(ON)O MAX "ON" (V) SWITCH "OFF" (V) 75 2.4 0.8 36VCMOS-J1 75 2.4 0.8 36VCMOS-J1 SWITCH IsoFF(tnA) TECHNOLOGY TYP TON (ns) TYP TOFF (ns) TYP 1.0 150 80 DualSPST 2.0 150 80 QuadSPST FEATURES . I tn CD CD _. !l o ::J C) C- o: CD n ~ ::a ! NOTES: 1. The ROS(ON) of a CMOS switch varies as a function of supply voltage. analog signal voltage. and temperature. Values shown are maximum (unless noted "Typ" = typical) at +25°C. SWITCH "ON" V: Digital Threshold to "CLOSE" a particular switch. (Minimum if greater than "OFF". Maximum if less than "oFF"). SWITCH "OFF" V: Digital Threshold to "oPEN" a particular switch. (Minimum if greater than ·ON". Maximum if less than "ON"). V1NL: Digital Threshold to represent a "Low" select signal. (Maximum. voltage levels greater than this value are not guaranteed to produce a "LOW). V 1NH: Digital Threshold to represent a "HIGH" select signal. (Minimum. voltage levels less than this value are not guaranteed to produce a "HIGH"). ~ 2. Package codes: DG Types - SUFFIX: A 10 Lead TO-l00 J Plastic 01 P K Ceramic DIP P Ceramic DIP IH Types - Middle SUFFIX Letter: J Ceramic DIP P Plastic 01 P T TO-l00Can B SOIC HI Types - PREFIX: Hll Ceramic DIP HI2 Metal Can HI3 Plastic DIP HI4 Ceramic LCC HI4P PLCC HI9P SOIC en (1) ...oCD_. (') ::J C) _. 3. Temperature Code Suffix: -1 : 0" to +20000 -2. A. orM: -55°Cto+125'C -4 or B: -25°C to +85°C -5: O"C to +75°C O"C to +70"C C: -7: O"C to +75°C with Burn-In -8: -55°C to + 125°C with Burn-In -9: -4O"C to +8500 1883: Mil-Std-883. Class B. -55°C to + 125°C with Burn-In I: Industrial. -2500 or -40°C to +85°C. see data sheet C C. (1) "0 g ~ c CD .s 4. Double Throw switches have one switch ON and the other switch OFF for each input state. See data sheet. I SWITCHES I ~SI IN10----c0i>--L Dl ~S2 INZ o - - - - c O i > - - L D2 S 0--:0----0 D INo-O-[>j SI ~S3 IN3 o - - - - c O i > - - L --0-;0---0 Dl • INI 0-0-[>-: INz 0--0-[>-1 ~S4 • 0~D4 S40 en CD Ao-O-[>.l D4 FIGURE 2. DUAL SPST · S3~D3 IN4-o-t>--L S2~Dz 0'(0---0 Dl SZ~D2 D3 • FIGURE 1. SPST SI 0 FIGURE 3. QUAD SPST CD FIGURE 4. 4PST () ~ 0 ~ N SI 0 o~Dz SI 0 C~D1 S3 0 0..:.,0--00, S3 0 0-;0 INI . SI --0-;0---0 Dl Szo oio--oDz INo-O-[>J 0 0--+--0 Dz IN20-0-[>i · S2~Dl O~O--OD4 SWITCH SOURCE ON) Sz~o, S4 0 01'0----0 D4 Ao-O-[>J FIGURE 9. DPDT · • C) _. 00, C INI 0 - 0 - [ > ' : CONTROL INPUT .. SI 0 O~D1 Szo c~ r------- __ SWITCH oj 0-0 DRAIN (OUT) ~DRIVER TRANSLATOR = FIGURE 10. "T" SCHEMATIC IN2 0-0-[>-, CD S 2 - + - - o D2 '0 S4~D4 S· FIGURE 8. DUAL DPST ..s · FIGURE 7. DPST ------..o(.~ a. • 0°2 IN 0 - 0 - [ > ' : FIGURE 6. DUAL SPOT 0{0---0 Dl SI o--O-[>-l S4 0 FIGURE 5. SPOT Sz ·• :::J C CD r --.l----: r----L ... . IN1~~IN2 S2 SIb Dl : • FIGURE 11. "T" SWITCH 0 3- Dz DG200, DG201 CMOS Dual/Quad SPST Analog Switches December 1993 Features Description • SwHches Greater than 28Vp-p Signals with ±1S Supplies • Break-Bafore-Make Switching Typical toFF 250ns, toN The DG200 and DG201 solid state analog gates are designed using an improved, high voltage CMOS monolithic technology. They provide ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates has been eliminated by Harris's CMOS technology. 700ns • TTL, DTL, CMOS, PMOS Compatible • Non-latching with Supply 1\Jrn-Off The DG200 and DG201 are completely specification and pinout compatible with the industry standard devices. • Complete Monolithic Construction • Industry Standard (DG200, DG201) Ordering Information Applications PART NUMBER TEMPERATURE PACKAGE • Data Acquisition DG200AA -55°C to +125°C 10 Pin Metal Can • Sample and Hold Circuits DG200AK -55°C to +125°C 14 Lead Ceramic DIP • Operational Amplifier Gain Switching Networks DG200BA -25°C to +85OC 10 Pin Metal Can DG200BK -2500 to +85OC 14 Lead Ceramic DIP DG200cJ O°C to +7ooC 14 Lead Plastic DIP DG200AAl883B -55°C to +125°C 10 Pin Metal Can DG200AKI883B -55°C to + 125°C 14 Lead Ceramic DIP DG201AK -55°C to +125°C 16 Lead Ceramic DIP DG201BK -25°C to +85OC 16 Lead Ceramic DIP DG201CJ OOCto +7000 DG201AKl883B 16 Lead Plastic DIP -55°C to +125°C 16 Lead Ceramic DIP Pinouts DG200 (CDIP, PDIP) TOP VIEW DG200 (To-l00 METAL CAN) TOP VIEW DG201 (CDIP, PDIP) TOP VIEW v+ (SUBSTRATE AND CASE) 12 v+ (SUBSTRATE) 13 V+(SUBSTRATE) CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 9-13 File Number 3115 DG200,DG201 Schematic Diagram ~/2 DG200, 1/4 DG201) V+ ~ I~ Q3 It:: Ja7 II-' I~ II- II- U 11- ~~n as l II-'- a15 T~ I"':; Q8 al VREF ~I Lr - l V+ II-'n I"':; al0 aID U ~ 1[.013 V I.,. Q2 I.,. Q8 GATE PROTECTION RESISTOR :1::1: II-'-U II-'-J I~ I..,. Q4 11-J -=..F . SI as Il-J 1 \10 INPUT Functional Diagram .......- - - - - - o S IN L.....---+---OD 00200, 00201 SWITCH CELL 9-14 011 DI Specifications DG200 Absolute Maximum Ratings Thermal Information V+, v- ••...•....••••••.•••••••••••••.••••••••••••• <36V v+-vo •....•..•••••••••.•••••.••••••••••••••••••• <30V v o - V- •••••••••••••••••••••••••••••••••••••••••••• <30V vo-vs •••••••••••••••••.••••.•••••••••••••••••••• <2SV VIN - GND ••••••••.•••••••••••••••••••.•••••••••••• <20V Storage Temperature Range ••..••••••••••••• -65OC to +1 SOOC Lead Temperature (Soldering 10s) •••••••••••••••••••• +3OOoC Thermal Resistance 9JA Ceramic DIP Peckage ••••••••.•••••• 95"CN1 Plastic DIP Package ••••••••••••.••• 1OOOCN-l Metal Can Package ••••••••••••••••• 1313OCN-l 65OCN-l Operating Temperature Range "A" Suffix •••••••••••••••••••••.•••.••••• -55°C to +1250 C "B" Suffix •••••••••••••••••••••.•••••••••• -25"C to +85°C "c" Suffix •••••••••••••••••••.••••••••••••• OOC to +700C CAUTION: Stresses aboIIIIlhose listsd In "AbsoJuts Maxinwm Ratings" may caus. permanent damag. to the device. This Is a stress only l8t1ng 8nd opfIl8tkm of III. device at Ihss. or any oilier conditions ab01/8 11105. indicatsd In the opfIl8tionaJ sllCtions of 1II1s spllCification Is not impUed. Electrical Specifications (TA = +25°C, V+ = +15V, v- = -15V) COMMERCIAL I INDUSTRIAL MILITARY TEST CONDITIONS PARAMETER -55°C +25°C +125°C OOCTO _25°C +25"C +700CTO +85"C UNITS ±10 ±10 IIA Input logic Current, IIN(ON) VIN = O.SV (Notas 2, 3) ±10 ±1 ±10 . Input Logic Current, IN(OFF) VIN = 2.4V (Notes 2, 3) ±10 ±1 ±10 . ±10 ±10 IIA Drain-Source On Resistance, rOS(ON) Is = 10mA, VANALOG = ±10V 70 70 100 SO SO 100 0 - 25 (Typ) - - 30 (Typ) - 0 - ±15V . - ±15V . V ±2 100 - ±5 100 nA ±2 100 ±5 100 nA ±2 200 ±10 200 nA 1.0 - 0.5 - - - - Channel-to-Channel rOS(ON) Match, rOS(ON) Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, IOlOFF) VANALOG = -14V to +14V Switch OFF Leskage Current,IS(OFF) VANALOG = -14V to +14V Switch ON Leskage Cur- Vo = Vs = -14V to +14V rent, IOlON) + Is(oN) Switch "ON" Time (Note 1), toN RL = 1110, VANALOG = -10V to +1 OV (Figure 5) Switch "OFF" TIme, toFF RL = 1110, VANALOG = -10V to +10V (Figure 5) Charge Injection, OjINJ.) Figure 6 Minimum Off Isolation Rejection Ratio, OIRR 1= 1MHz, RL = 1000, CL S5pF (Figure 7, Note 1) +Power Supply Quiescent Current, VIN = OV or VIN = 5V - 15 (Typ) 54 (Typ) - 50 (Typ) - 1.0 0.5 20 (Typ) jLS jLS mV dB 1000 1000 2000 1000 1000 2000 IIA 1000 1000 2000 1000 1000 2000 IIA - 54 (Typ) - - 50 (Typ) - dB IVI -Power Supply Quiescent Current, 1V2 Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR One Channel Off NOTES: 1. Pull Down Resistor must be S 2kO. 2. Typical values are lor design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high "1" logic Inputs and all channels are turned on by low "0" Inputs; however O.SV to 2.4V describes the minimum range lor switching propel1y. Peak Input current required lor transition is typically -1201lA. 9-15 Specifications DG201 Absolute Maximum Ratings Thermal Information V+ to V-........................................... <36V V+ to Vo ••••••••••••••••••.••••.•••••••••••••••••• ----[1 PUT 10,OOOpF + FIGURE 6. FIGURES. 510 'l---voUT 1 1000 • Pull Down R..lstor must be oS 2kn FIGURE 7. Typical Applications UsIng the VREF TermInal The DG200 and DG201 have an internal voltage divider set· ting the TTL threshold on the input control lines for V+ equal to +15V. The schematic shown in Figure 8 with nominal resistor values, gives approximately 2.4V on the VREF pin. As the TTL input Signal goes from +D.8V to +2.4V, Q1 and Q2 switch states to turn the switch ON and OFF. V+(+15V) If the power supply voltage is less than +15V, then a resistor must be added between V+ and the VREF pin, to restore +2.4V at VREF The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. In general, the "low" logic level should be or V1N exceeding V+ or V- will be clamped by internal diodes. Llmitfolward diode current to maximum current ratings. 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. The algebraic convention whereby 1I1e most negative value Is a mlnlmum, and the most positive Is a maximum, Is used In 1I11s data sheet 4. ID(ON) Is leakage from driver Into ON Switch. 9-23 DG201A, DG202 Test Circuits LOGIC "0" • SWITCH ON LOGIC· 3V INPUT ,.---- +15V V+ SWITCH INPUT Sl \I < 2On. tF<20ne SWITCH OUTPUT VS .. +2V o-t-----"io--+---t---"t---o Vo SWITCH INPUT Vs --i-:--;:;;:;:::::::::::::j::::;:;--:-=--0.9 RL _ 1kn Vo J. CL 35pF (REPEAT TEST FOR INz, INa AND IN4> "Logic shown for OG201A, invert for OG202 FIGURE 1. TON AND TOFF SWITCHING TEST As l Ox Sx r Vo / Vo 1"·'- INx INx ON \ \ OFF / AVo f ON NOTES: = 1. INo Measured voltage error due to charge Injection. 2. The error voltage in coulombs Is AQ Cl X AVo. = FIGURE 2. CHARGE INJECTION TEST CIRCUIT +15V +15V j} j} r-'-----, ,......~--.., 500 ANALYZER CHANA CHAN B I---;_--.A:-I-=.....I = C 0.001 JIF /I 0.1 j!F Chip Capacitors OIRR = C =0.OO1j!F 1I0.1j!F Chip Capacitors 20Log\~:\ FIGURE 3. OFF ISOLATION TEST CIRCUIT CCRR = 20 LOg\VVS1 \ 02 FIGURE 4. CHANNEL TO CHANNEL CROSSTALK TEST CIRCUIT 9-24 DG211, DG212 SPST 4 Channel Analog Switch December 1993 Features Description • SwHches ±1SV Analog Signals The DG211 and DG212 are low cost, CMOS monolithic, Quad SPST analog switches. These can be used in general purpose switching applications for communications, instrumentation, process control and computer peripheral equipment. Both devices provide true bidirectional performance in the ON condition and will block signals to 30V peak-to-peak in the OFF condition. The DG211 and DG212 differ only in that the digital control logic is inverted, as shown in the truth table. • TTL Compatibility • LogiC Inputs Accept Negative Voltages • RON::;17S0 Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE DG211CJ OOCto +70OC 16 Lead Plastic DIP DG212CJ O"c to +70°C 16 Lead Plastic DIP DG211CY O"C to +70"C 16 Lead SOIC (N) DG212CY OOC to +70OC 16 Lead SOIC (N) Pinout Functional Diagrams OG211,OG212 (POIP, SOIC) TOP VIEW OG212 OG211 (/) Sl 01 ~ INz Dz S3 IN3 ~ S4 IN4 04 NOTES: 1. Four SPST switches per package. 2. Switches shown for logic "I" input TRUTH TABLE LOGIC DG211 DG212 0 ON OFF 1 OFF ON Logic "0- SO.8V, Logic "I" :-'IM-.....-t IN 9-26 Specifications DG211, DG212 Absolute Maximum Ratings Thermal Information V+to V-•••••••••••••••••••••••••••••••••••••••••••• 44V VIN to Ground ••••••••••.•.•..•..•.•••..••..••••.••• V-, V+ VL to Ground ••••••••••.•••••••••••••••.••.••..• -0.3V,25V Vs or Vo to V+ •••..•••••..•.•.••••••.••.•••.•••••. 0, -36V Vs or Vo to v- ..•••.•..•.••••.••••••.•...••.••••.• 0, 36V V+ to Ground ••••.•••••.......•.........••..•.•••.•• 25V V- to Ground ••.•••.•••••.••.•••••••••••••••.•••••••• -25V Current, any Terminal Except S or 0 ..•••••.•••••••••••• 30mA Continuous Current, S or 0 •.•••••..••••..••.••••••••• 20mA Peak Current, S or 0 (Pulsed at 1ms, 10% Duty Cycle Max) •••• 70mA Lead Temperature (Soldering lOs) ..••••••••••.••.•••. +3OOoC Storage Temperature Range ••••••••••••••••• -6500 to +125°C Thermal Resistance 9JA Plastic DIP Package •••.••.•.••••••••...•••.•••• 1ooOC/W SOIC Package .••••••.•...••••••••••••••••••••• 120"CIW Junction Temperature ••••.••••••••••.•••••••••.•••• + 15O"C Operating Temperature .••..••••••••••••••••••• O"C to +700 C dev«:.. CAUTION: Stressss above those listed in "Absolulll Maximum Ratings" may cause permanent damage to the This Is a stress only m/lng and Op8mtion of the device at tlrese or any other conditions above those indicated in the optlmtlonal sections of this specification is not implied. Electrical Specifications V+ = +15V, v- = -15V, vL = +5V, GND, TA = +25°C TEST CONDITIONS PARAMETERS (NOTE 1) MIN (NOTE 2) TVP MAX UNITS - 460 1000 ns - 360 500 ns DYNAMIC CHARACTERISTICS Turn-On Time, ioN See Figure 1 Vs = 10V, RL = lkn, CL = 35pF Turn-Off Time, IoFF1 IoFF2 Source OFF Capacitance, CS(OFF) Vs = OV, VIN = 5V, f = lMHz (Note 2) Vo = OV, VIN = 5V, f = lMHz (Note 2) Vo = Vs = OV, VIN = OV, f = lMHz (Note 2) - 450 5 - ns pF - 5 - 16 - 70 - dB - 90 - dB VIN=2.4V -1.0 -0.0004 - j1A VIN = 15V - 0.003 1.0 j1A VIN=OV -1.0 -0.0004 - j1A Analog Signal Range, VANALOG V- = -15V, VL = +5V -15 - 15 V Drain Source On Resistance, ROS(ON) Vo = tl0V, VIN = 2.4V (DG212) Is = lmA, VIN = O.BV (DG211) - 150 175 n Source OFF Leakage Current, IS(OFF) VIN = 2.4V (00211) VIN = O.BV (DG212) Vs = 14V, Vo = -14V - 0.01 5.0 nA Vs = -14V, Vo = 14V -5.0 -0.02 - nA Drain OFF Capacitance, CO(OFF) Channel ON Capacitance, Co + S(ON) OFF Isolation, OIRR (Note 4) VIN = 5V, RL = lkn, CL = 15pF, Vs = lVRMS , f = 100kHz (Note 2) Crosstalk (Channel to Channel), CCRR pF pF INPUT Input Current with Voltage High, IINH Input Current with Voltage Low, IINL SWITCH Drain OFF Leakage Current, IO(OFF) Drain ON Leakage Current, IO(ON) (Note 3) Vs = -14V, Vo = 14V - 0.01 5.0 nA Vs = 14V, Vo = -14V -5.0 -0.02 - nA - 0.1 5.0 nA -5.0 -0.15 - nA Vs = Vo = -14V, VIN = O.BV (00211) VIN = 2.4V (DG212) 9-27 .Specifications DG211,DG212 Electrical Specifications V+ =+15V, V- =-15V, v L =+5V, GND, TA =+25"C (Continued) PARAMETERS (NOTE 1) MIN TEST CONDmONS (NOTE 2) TYP MAX UNITS 0.1 10 jiA 0.1 10 jiA 0.1 10 jiA POWER SUPPLY CHARACTERISTICS Posltlve Supply Current, 1+ VIN - =OV and 2.4V - Negative Supply Current. 1Logic Supply Current, IL NOTES: 1. The algebraic convention whereby Ihe most negative value Is a minimum, and the most positive is a maximum, Is used In this data sheet 2. For design reference only, not 100% tested. 3. ID(ON) is leakage from driver Into ON switch. Vs 4. OFF Isolation = 2OIog IT' V s = Input to OFF switch, V 0 = output o 5. Switching times only sampled. Test Circuits = Switch outpyt waveform shown for Vs constant with logic input waveform as shown. Note the Vs may be + or - as per switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform. LOGIC· SWITCH INPUT SI SWITCH Dl OUTPUT Vs-l0V _1-----0"';0--+_ _...._ _..-_ Vo RL _ lien INPUT~Nd tR<20na ",<20n8 SWITCH INPUT v S +15V V+ l36 CL PF (REPEAT TEST FOR IN2, INa AND IN.) --i---;;:====:;:;t=j"--:-:-+-_ SWITCH _ _ OUTPUT(Vo) • Logic shown for DG211. Invert for 00212. FIGURE 1. SWITCHING TIME TEST WAVEFORMS FIGURE 2. SWITCHING TIME TEST CIRCUIT 9-28 DG211, DG212 Metallization Topology DIE DIMENSIONS: 21591lffi x 223511m METALLIZATION: Type: AI Thickness: 10kA± 1kA GLASSIVATION: Type: PSG/Nitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness: akA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DG211,DG212 PIN 16 IN2 PIN 1 IN 1 PIN 14 52 PIN3 51 en W PIN 4 ::t: O y- J- PIN 12 PINS GND YL PIN6 PIN 11 53 54 PINg IN3 PINS IN4 9-29 ~ DG300A, DG301A DG302A, DG303A TTL Compatible CMOS Analog Switches December 1993 Features Description • Low Power Consumption The DG300A through DG303A family of monolithic CMOS switches are truly compatible second source of the original manufacturer. The switches are latch-proof and are designed to biock signals up to 30Vp_p when OFF. Featuring low leakage and low power consumption, these switches are ideally suited for precision application in instrumentation, communication, data acquisition and battery powered applications. Other key features include Break-Before-Make switching, TTL and CMOS compatibility, and low ON resistance. Single supply operation (for positive switch voltages) is possible by connecting v- to Ov. • Break-Before-Make Switching tOFF 130ns, toN 150ns Typical • TTL, CMOS Compatible • Low RDS(ON) (s 500) • Single Supply Operation • True Second Source Ordering Information PART NUMBER DG300AAK DG301AAK DG302AAK DG303AAK DG300ABK OO301ABK OO302ABK OO303ABK DG300ACK DG301ACK DG302ACK DG303ACK OO300ACJ DG301ACJ TEMPERATURE -55°C to +125°C -55°C to +125°C -55°C to +125°C -55°C 10 +125°C -25°C to +85°C -25°C to +85°C -25°C to +85°C -25°C to +85OC O°C to+700C DOC to +700C OOC to+700C 0"0 to +700 C OOCto +700 C OOC 10+700 C PACKAGE 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Piastlc DIP 14 Lead Plastic DIP PART NUMBER DG302ACJ DG303ACJ DG300AAA DG301AAA DG300ABA DG301ABA DG300ACA DG301ACA DG303ACY DG300AAAI883B DG300AAKl883B 00301 AAAl883B DG301 AAKI8838 DG302AAKI883B DG303AAKI883B TEMPERATURE 0"0 to +70"0 0"0 to +700C PACKAGE 14 Lead Plastic DIP 14 Lead Plastic DIP 10 Pin Metal Can 10 Pin Metal Can 10 Pin Metal Can -25°C 10 +85"C 10 Pin Metal Can 10 Pin Metal Can OOC 1o+700C 10 Pin Metal Can OOCto +700C OOC to +70"0 16 Lead SOIC (W) -55°C to +125"0 10 Pin Metal Can -55°C to +125"0 14 Lead Ceramic DIP -55"C to +125OC 10 Pin Metal Can -55°C to +125"0 14 Lead Ceramic DIP -55°C to +125"0 14 Lead Ceramic DIP -55"C to +125°C 14 Lead Ceramic DIP -55°C to +125"0 -55°C to +125°C -25°C to +85OC Pinouts and Functional Diagrams OG300A (METAL CAN) TOP VIEW V+ (SUBSTRATE AND CASE) DG300A S'o-+----_.-:,_-t_o :, , OG300A (COtP, POIP) TOP VIEW D, ~~. GND TRUTH TABLE LOGIC SWITCH o OFF ON Logic "0" s 0.8V, Logic "1" .! 1... ~~ LOGIC INPUT ~~ 50"4 1\ -.ls0"4 tR<2Ona tF<20na _ D Vo RL lCL PF 1k1l 13s -::~ SWITCH INPUT ) SWITCH OUTPUT = toNVINH-15V VINL-OV -1SV FIGURE 1. toN AND toFF SWITCHING TEST 9-40 f- 90"4 i- - '~L -toFF DG30BA, DG309 Die Characteristics DIE DIMENSIONS: 205BIIDl x 21 091lm METALLIZATION: Type: AI Thickness: 1 ± 1kA okA GLASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness:8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Ncm 2 Metallization Mask Layout DG308A, DG309 PIN 14 S2 PIN 13 V+ (SUBSTRATE) PIN 11 S3 PIN 15 D2 PIN 10 03 PIN 16 IN2 PINIIIN3 en W ::t: 0 I- PIN 1 01 PIN81N4 PIN 2 IN1 PIN 7 D4 PIN 3 'S1 PIN 4 V- PIN 5 GNO 9-41 PIN 6 54 i en DG401, DG403 DG405 Monolithic CMOS Analog Switches December 1993 Features Description • ON-Resistance < 35Q The OG401, 00403 and OG40S monolithic CMOS analog switches have TTL and CMOS compatible digital inputs. These switches feature low analog ON resistance « 3Sn) and fast switch time (ioN < 150ns). Low charge injection simplifies sample and hold applications. The improvements in the OG401/40314OS series are made possible by using a high voltage silicon-gate process. An epitaxiallayer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30V peak-te-peak signals. Power supplies may be single-ended from +SV to +34V, or split from ±5V to ±17V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±1SV analog input range. The three different devices provide the equivalent of two SPST (00401), two SPOT (OG403) or two OPST (OG40S) relay switch contacts with CMOS or TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as needed. • Low Power Consumption (Po < 351lW) • Fast SWitching Action - tON <1S0ns - toFF <100ns • Low Charge Injection • DG401 Dual SPST; Same Pinout as HI-S041 • DG403 Dual SPOT; DG190,IH5043,IHS1S1, HI-50S1 • DG40S Dual DPST; DG184, HI-5045,IH5145 • TTL, CMOS Compatible • Single or Split Supply Operallon Applications • Audio Switching • Battery Operated Systems • Data Acquisition Ordering Information • HI-Rei Systems • Sample and Hold Circuits PART NUMBER TEMP. RANGE • Communication Systems DG401AK1883 -5SoC to +12SoC • Automatic Test Equipment DG401DJ DG401DY DG403AK1683 DG403DJ DG403DY -4OOC to +85°C -4OOC to +85°C -ssoo to +12SoC -4OOC to +8SoC OG405AKI883 -4OOC to +85°C -5500 to +12SOC DG40SDJ OG4050Y -4OOC to +85OC -4OOC to +85°C PACKAGE 16 lead Ceramic DIP 16 Lead Plastic DIP 16 lead SOIC (N) 16 lead Ceramic DIP 16 Lead Plastic 01 P 16 Lead SOIC (N) 16 Lead Ceramic DIP 16 lead Plastic 01 P 16 Lead SOIC (N) Pinouts 00401 00403, 00405 TOP VIEW TOP VIEW (NC) NO CONNECTION CAUTION: These devices are sensitive to electrostatic discharge. Usara should follow proper I.e. Handling Procedures. Copyright @ Harris Corporation 1993 9-42 File Number 3284.1 DG401, DG403, DG405 Functional Diagrams Switches Shown for Logic '1" Input 00401 YL OG405 OG403 Y+ Y+ YL 11 51 16 1 01 51 i: 5a 51 01 3 4 Da Sa ! . ..1 .. j 16 01 4 Sa i! 8 Da Sa 5. ! 9 5 6 14 GND Da Sa D. 5. ! ! ! 9 5 GND 14 GND Y- Truth Table OG401 00403 OG405 LOGIC SWITCH SWITCH 1,2 SWITCH 3,4 SWITCH 0 OFF OFF ON OFF 1 ON ON OFF ON NOTE: Logic "0" sO.av. Logic "1" : ±2000V • Low Charge Injection • Upgrade from OG201A1DG202 The improvements in the DG441 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40V peak-ta-peak signals. Power supplies may be single-ended from +5V to +34V, or split from ±5Vto±20V. • TTL, CMOS Compatible • Single or Split Supply Operation Applications • Audio Switching The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The switches in the 00441 and DG442 are identical, differing only in the polarity of the selection logic. • Battery Operated Systems • Data Acquisition • HI-Rei Systems Ordering Information • Sample and Hold Circuits • Communication Systems PART NUMBER TEMPERATURE RANGE DG441AKl883 -55"C to +125°C DG441DJ -4O"C to +85°C 16 Lead Plastic DIP DG441DY -4O"C to +85°C 16 Lead SOIC (N) DG442AKl883 -55°C to +125°C 16 Lead Ceramic DIP DG442DJ -4O"C to +85°C 16 Lead Plastic DIP DG442DY -400 C to +85°C 16 Lead SOIC (N) • Automatic Test Equipment Pinout PACKAGE 16 Lead Ceramic DIP Functional Diagrams 00441 DG441,DG442 (PDIP, CDIP, SOIC) TOP VIEW DG442 51 INI INI 01 52 IN2 IN2 Dt Sa IN3 INa Da 54 IN4 IN4 04 SWITCHES SHOWN FOR LOGIC "1" INPUT CAUTION: Thesa del/ices ara sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procadures. Copyright © Harris Corporation 1993 9-53 File Number 3281.2 DG441, DG442 Schematic Diagram (One Channel) V+ ,............................. __ ..................... _-, • 1NX GND t ...... _____ ... _... ___ . . ____ ........ ~ 1 PER DIE COMMON TO EVERY CHANNEL y. 9-54 Specifications DG441, DG442 Absolute Maximum Ratings Thermal Information V+toV-••••••••••••.••••••.•••.•••••••••••••••••• +44.0V GND to V- •••••••••••••••••••••••••••••.•••••••••••• 25V Digital Inputs (Note 1) •.••••.••••• (V-) -2V to (V+) + 2Vor 3OmA, Whichever Occurs First Continuous Current, S or D (Note 1)....•..........•...•.. ±30mA Peak Current, S or 0 (Note 1) ...•.•....•.•..•..•••..•••±100mA (Pulsed 1ms. 10% Duty Cycle) Storage Temperature Range (A Suffix) •.••••••• -65"C to +15O"C (0 Suffix) .••••••••. _65°C to +125°C Thermal Resistance (Note 3) 9JA 9JC Plastic DIP Package.. •• • . •• . •• • • • • • 11X1'C1W Ceramic DIP Package. • • • • • • • • • • • • • • 85"CIW 24"C1W SOIC Package. • • • • • • • • • • • • • • • • • • • • 12O"C1W Operating Temperature (A Suffix) ••.•••••....•• -55"C to +125°C (0 Suffix) ••••••••••••••• -40"C to +85°C Junction Temperature (CDIP) ••••••••..•••••••••••••• +175°C (PDiP, SOIC) .••..•••••••••••••• +15O"C CAUTION: Stresses abOll8 those listed in "'AbsoJuIB Maximum RaUngs' may cause pfI{manent damage to the davica. This Is a stress only raUng and operation of the device at these or any other conditions above those indicated in the opsrational sections of this specification is not impHed. Operating Conditions Operating Voltage Range •.....•...•.•.....•••..•.•.. ±20V Max Operating Temperature Range ........••..•••• -55"C to +125°C Input Low VoHage •••••••••.•.....•.•••.•••..••.•• 0.8V Max Input High Voltage ••..••.•.•.•.••••••••••••••••••• 2.4V Min Input Rise and Fall11me ••••••••••••..•..•••••..•••••. 20ns Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V, VANALOG = Vs• Yo. Unless Otherwise Specified DSUFFIX -4O"C TO +85°C A SUFFIX ·55°C TO +125°C PARAMETER TEST CONDITION (NOTE 2) TEMP MIN (NOTE 4) TVP MAX MIN (NOTE 4) TVP MAX UNITS +25"C - 1SO 2SO - 150 250 ns - 90 120 - 90 120 ns 110 170 110 170 ns - - -1 - pC DYNAMIC CHARACTERISTICS Turn-ON 11me, TON Turn-OFF 11me, TOFF Rl = 11<0, CL = 35pF, Vs =±10V, See Figure 18 +25°C DG441 DG442 CL = 1nF, Vs = OV, VGEN = OV, RGEN = 00 +25OC - -1 OFF Isolation RL = 500, CL = 5pF, f=1MHz +25"C - 60 - - 60 - dB Crosstalk (Channel-toChannel) RL = SOO, CL = 5pF, f= lMHz +25°C - -100 - - -100 - dB Source OFF Capacitance, CS(OFF) f= 1MHz +25"C - 4 - - 4 - pF Drain OFF Capacitance, CO(OFF) f= 1MHz +25°C - 4 - - 4 - pF Channel ON Capacitance, CO(ON) + CS(ON) VANALOG = 0 +25°C - 16 - - 16 - pF Full -15 - 15 -15 - 15 V Charge Injection, a ANALOG SWiTCH Analog Signal Range, VANALOG Note 4 Drain-Source ON Resistance, ROS(ON) Is= 10mA, Vo =±8.5V, V+ = 13.5V, V- = -13.5V +25"C - 50 85 - SO 85 0 Hot - - 100 - - 100 0 Switch OFF Leakage Current, lS(oFF) V+= 16.5V, V-=-16.5V, Vo =±15.5V, Vs= +15.5V +25°C -0.5 0.01 0.5 -0.5 0.01 0.5 nA Hot -20 - 20 -20 - 20 nA Switch OFF Leakage Current, ID(OFF) V+= 16.5V, V-=-16.5V, Vo = ±15.5V, Vs= +15.5V +25OC -0.5 0.01 0.5 -0.5 0.01 0.5 nA Hot -20 - 20 -20 - 20 nA 9-55 Specifications DG441, DG442 Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, v- = .15V, VIN = 2.4V, 0.8V, VANALOG =Vs. VIJo Unless Otherwise Specified (Continued) DSUFFIX -4O"C TO +85°C A SUFFIX -55°C TO +l25°C PARAMETER TEST CONDITION (NOTE 2) TEMP MIN (NOTE 4) TVP MAX MIN (NOTE 4) TVP MAX UNITS +2500 -0.5 0.08 0.5 -0.5 0.08 0.5 nA Hot 040 - 40 040 - 40 nA ANALOG SWITCH (Continued) Channel ON Leakage Current, IO(ON) + I8(ON) V+= 16.5V, V- = -16.5V, Vs = Vo = ±15.5V DIGITAL CONTROL Input Current VIN Low, IlL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 -0.00001 0.5 -0.5 -0.00001 0.5 I1A Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5· 0.00001 0.5 -0.5 0.00001 0.5 I1A - I1A I1A I1A I1A MAX UNITS POWER SUPPLIES Positive Supply Current, 1+ V+ = 16.5V, V- = -16.5V, VIN = OVor 5V Negative Supply Current, I- Ground Current, IGNO Full - 15 100 - 15 100 +25OC -I -0.0001 - -I -0.0001 Full -5 - - - -5 - Full -100 -15 - -100 -15 Electrical Specifications (Single Supply) Test Conditions: V+ = 12V, V- = Ov. VIN = 2.4V, 0.8V, Unless Otherwise Specified A SUFFIX -55°C TO +125°C (NOTE 2) TEMP MIN (NOTE 4) TYP RL = lKn, CL = 35pF, See Test Clrcuil, Vs=8V +25°C - 300 +25°C - 60 =6V, +25OC - 2 Full 0 - +25°C - Full - PARAMETER TEST CONDITION DSUFFIX _40°C TO +8SOC (NOTE 4) MAX MIN TYP 400 - 300 400 ns 200 - 60 200 ns - - 2 - pC 12 0 - 12 V 100 160 - 100 160 - 200 - 200 n n DYNAMIC CHARACTERISTICS Tum-ON TIme, TON Tum-OFF TIme, TOFF Charge Injection, Q CL = 1nF, VGEN RGEN=OO ANALOG SWITCH Analog Signal Range, VANALOG Note 4 Drain-Source ON-Resistance, R08(ON) Is = 10mA, Vo V+= 10.8V =3V, 8V V+ = 13.2V, VVIN =OVor5V =OV, - POWER SUPPLIES Positive Supply Current, 1+ Negative Supply Current, I- Ground Current, IGNO Full - 15 100 - 15 100 +25°C -I -0.0001 - -I -0.0001 -100 -0.0001 - - Full -100 -0.0001 Full -100 -15 . -100 -15 - NOTES: 1. All leads soldered to PC Board. 2. Room: +25°C. Cold: A suffix -55"C, D suffix -4ooC. Hot: A suffix +125°C, D suffix +85°C 3. Dissipation rating assumes device Is mounted With all leads soldered to printed circuit board. 4. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. 9-56 - I1A I1A I1A I1A DG441, DG442 Typical Performance Curves 80 V+.+15V ¥-=-15V _ 70 - 60 ./'~ --- ------- r-....."" ----- 50 - -- --,.. - ~40 ~ ~30 20 OOC V . / +40oC ' / - - +12SOC ------. +8SOC ~ +25O C ~ - ~oC - I o 10 0~~~ -20 __L-__L-~~~~~~~~~ 0 20 120 100 g 80 ~ 60 ~ 40 ~ V , /V ~ ~~ ~ t-OoC / - -- -- r--... - V+ .. +l2V V-.OV +125O C ..aSOc Jsoc 10- ~ V 250 ......... ........ J" J" ~ ~~ I/ FIGURE 2. RDS(ON) VB Vo AND TEMPERATURE 300 I ~ g ~ Z'150 j -.....::: 100 +400C . / 50 20 o 6 / ,..... ./ ~ :::::- IV+=+5V r-- ~+8V +10V +15V -: I ........ 0 / I+,IGNO 1 102 / j 10 ~ -; V 50 TEMPERATURE (OC) 20 FIGURE 4. RDS(ON) VB Vo AND UNIPOLAR POWER SUPPLY VOLTAGE / ~ - 1 0.01 125 FIGURE 5. INPUT CURRENT VB TEMPERATURE 0.001 ~5 ..,. / ' /" ~ ~-) 0.1 100 +2OV 10 VO(V) / 10 • ..... -. +12V VoM V-=OV ~5 I V- .. OV r o o 12 FIGURE 3. RDS(ON) VB Vo AND TEMPERATURE (SINGLE 12V SUPPLy) 0-1 I 200 ~SOc o 15 Vo(V) FIGURE 1. RDS(ON) VB Vo AND POWER SUPPLY VOLTAGE 140 o -15 VoM o 50 TEMPERATURE ("C) 100 FIGURE 6. SUPPLY CURRENT VB TEMPERATURE 9-57 125 DG441, DG442 Typical Performance Curves (Continued) 140r-~--'-----~-----'r-----~----.., 50 _ V+_+15V V·.·15V 40 SINGLE SUPPLY V+=+12V V·.OV 30 100 ----+~fIC--_i 2O~------+----~--~fIC-~~fIC----i 80 jjj' 1. a~10r------+----~~--~~~~~~ o 60 40 V+_+15V V· .. ·15V REF10dBm 20 o~ 102 ____ ~ ~6.~~--+-------+-------~------~ ____ ~~ __ ~~ ____ 104 105 FREQUENCY (Hz) 103 ~ ____... -30.1L.0----I-5:-----J.0------:5~---1~0 107 10' VaN) FIGURE 8. CHARGE INJECTION vs SOURCE VOLTAGE FIGURE 7. CROSSTALK AND OFF ISOLATION vs FREQUENCY 160 I V+",+15V V..·15V toN (DG441 140 120 ~ L. .0 I- toFF (00442) "- 60 20 2 3 INPUT VOLTAGE M 4 ..". IS(ON) + ID(ON) . " " /' toFF (DG441) 40 - ·100 ·15 5 FIGURE 9. SWITCHING TIMES vs INPUT VOLTAGE I IS(OFFJo lD(oFF) /' i"'" /" ~ ·10 V+=+15V V..·15V FOR I(OFFJo VD" .Va -- -5 0 V.. VDM I I 5 10 15 FIGURE 10. SOURCE/DRAIN LEAKAGE CURRENTS 25 Vu:15V V·.·15V I 20 - I 1.6 CS(ON) + CD(ON) Ii:' 15 .e. ~ z :> Q ~ I-' ./ V ~ (f 10 0.8 5 - '""'==- CS(OFFJo CD(OFF) 0 °0~L--±~5-~--~~0:--~--±~1~5-~-±20~-~ ·15 p~nV~EGAnVESUPPUES(~ FIGURE 11. SWITCHING THRESHOLD va SUPPLY VOLTAGE ·10 o 5 10 VAN) FIGURE 12. SOURCEIDRAIN CAPACITANCE V8 ANALOG VOLTAGE 9·58 15 DG441, DG442 Typical Performance Curves (Continued) 20 - - 15 ~ ~ 10 10 I I I I _...... V V+ .. +12V V- .. OV CS(ON) + CD(ON) I o ~ :c .s. -10 .9 Q ji -20 (f V ~ CS(OFF)o CD(OFF) 5 -30 o - I IS(OFF)o ID(OFF) o -40 12 6 VA (V) FIGURE 13. SOURCEIDRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLy) )~ ~N)+ID(ON) /' V /" V+.+12V V-=OV FOR 10. VsaO FOR Is. VD=O o 12 6 VS. VD(V) FIGURE 14. SOURCEIDRAIN LEAKAGE CURRENTS (SINGLE 12VSUPPLy) 400 160 ioN ioooo- V+=+12V V-= OV -- 140 120 ioN (00441) 300 r--- ioN (00442) 100 I 80 ~ 60 ""'- ~ 'oFF 100 20 ±10 'oFF (0G442) """"- 40 ±12 ±14 ±16 ±18 ±20 'oFF (00441) o ±22 3 4 INPUT VOLTAGE (V) 2 SUPPLY VOLTAGE (V) FIGURE 15. SWITCHING TIME vs POWER SUPPLY VOLTAGE (OG441) 500 FIGURE 16. SWITCHING TIMES vs INPUT VOLTAGE I v-=ov .......... 400 300 "'- ~IoN .......... 200 100 o - 8 ~ i'-. - 'oFF 10 12 14 16 18 + SUPPLY VOLTAGE (V) 20 22 FIGURE 17. SWITCHING TIME vs POWER SUPPLY VOLTAGE (OG441) 9-59 5 DG441, DG442 Pin Description TRUTH TABLE PIN SYMBOL 1 IN, Logic control for Switch 1 DESCRIPTION 2 0, Drain (output) terminal for switch 1 3 S, Source (input) terminal for switch 1 4 V- Negative power supply terminal 5 GND 6 Source (Input) terminal for switch 4 7 S4 04 8 IN. logic control for switch 4 LOGIC VIN 00441 00442 0 sO.8V ON OFF 1 ~.4V OFF ON Ground terminal (Logic Common) Drain (output) terminal for switch 4 9 INs Logic control for switch 3 10 03 Drain (output) terminal for switch 3 11 12 S3 NC No Internal connection 13 V+ Positive power supply terminal (substrate) 14 S2 Source (input) terminal for switch 2 15 O2 Drain (output) terminal for switch 2 16 IN2 Logic control for switch 2 Source (input) terminal for switch 3 Test Circuits Vo is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. If! <20na LOGIC INPUT V+ tF<20na OV 0, SWITCH INPUT Vo SWITCH INPUT Va SWITCH OUTPUT RL LOGIC INPUT 3V J CL - V- OV Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications CL (includes fixture and stray capacitance) R V - V L 0- S RL +rOS(ON: NOTE: logic Input waveform Is Inverted for switches that have the opposite logic sense. FIGURE 18A. FIGURE 18B. FIGURE 18. SWITCHING TIME ~ V+ RG ov--.! 0, Vo '1 v- - GNO FIGURE 19A. INX~ (00441) OFF r INx (00442) ~ \ t ON ON Q.AVOxCL FIGURE 19B. FIGURE 19. CHARGE INJECTION 9-60 AVO I \ OFF OFF DG441, DG442 Applications Test Circuits (Continued) GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE. OP AMP OFFSET AND CMRR WILL UMIT ACCURACY OF CIRCUIT +15V FETINPUT VIN o-_.::O~P.;;A;;.;;M;,;..P-=--f"'" ..--~L)~'---r- VOUT 2 GAlN, Ay_1 3 R, 80kn 15 GAlN2 Ay_10 16 R2 5kn 10 GAlN3 Ay_20 GND FIGURE 20. CROSSTALK II R3 4kn 7 GAIN. Ay_100 8 +15V ov, 2.4V R4 1kn WITH SW4 CLOSED FIGURE 23. PRECISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER GND FIGURE 21. OFF ISOLATION FIGURE 24. OPEN lOOP SAMPLE AND HOLD OV.2.4V IMPEDANCE ANALYZER f=1MHz GND -15V FIGURE 22. SOURCE/DRAIN CAPACITANCES 9-61 DG441, DG442 Die Characteristics DIE DIMENSIONS: 216011'" x 1760llm x 485 ± 2511m METALLIZATION: Type:CuAI Thickness: 12kA± 1kA GLASSIVATION: Type: Nitride Thickness: akA ±1kA WORST CASE CURRENT DENSITY: 9.1 x 104A/cm2 Metallization Mask Layout DG441 , 00442 (16) OJ (14)~ (13) V+ SUBSTRATE (12)NC (11) 9-62 Sa DG444, DG445 Monolithic Quad SPST CMOS Analog Switches December 1993 Features Description • ON-Resistance 850 Max The DG444 and DG445 monolithic CMOS analog switches are dropin replacements for the popular DG211 and DG212 series devices. They include four independent single pole single throw (SPST) analog switches, TTL and CMOS compatible digital inputs and a voltage reference for logic thresholds. • Low Power Consumption (Po < 35mW) • Fast Switching Action - tON < 250ns - tOFF < 120ns (DG444) These switches feature lower analog ON resistance «850) and faster switch time (ioN < 250ns) compared to the DG211 and DG212. Charge injection has been reduced, simplifying sample and hold applications. • ESD Protection> ±2000V • Low Charge Injection • Upgrade from DG211IDG212 The improvements in the DG444 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling ±20V signals when operating with ±20V power supplies. • TTL, CMOS Compatible • Single or Split Supply Operation Applications The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The switches in the DG444 and DG445 are identical, differing only in the polarity of the selection logic. • Audio Switching • Battery Operated Systems • Data Acquisition • HI-Rei Systems Ordering Information • Sample and Hold Circuits PART NUMBER • Communication Systems • Automatic Test Equipment Pinout TEMPERATURE RANGE DG444DJ -4O"e to +85°e DG444DY -40"e to +85°C DG445DJ -400e to +85oe DG445DY -400C to +85°e PACKAGE 16 Lead Plastic 01 P 16 Lead sOle (N) 16 Lead Plastic DIP 16 Lead sOle (N) U) w ::z: i Functional Diagrams DG444, DG445 DG444 (PDIP, SOIC) TOP VIEW DG445 SI INI SI INI 01 01 Sz INz Sz INz Dz Sz INa Dz S3 INa Da Da S4 S4 IN4 IN4 04 04 SWITCHES SHOWN FOR LOGIC "1" INPUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 9-63 File Number 3586.1 DG444, DG445 Typical Schematic Diagram (One Channel) ~~~~----------+-----~--+-----~----+-----------~ INx_~---4 GND~+- ______ ~~ __ ~ ____ ~ ~~+-----------------------+-----~----~----~ 9-64 Specifications DG444, DG445 Absolute Maximum Ratings Thermal Information v+tov-•••..•.•••••••••••••..••..•••.•••••.••.••••• 44V GND to v- .•••...••.••••..••.•••..•.••.••••.•••••••. 25V VL .•.•.•••••••••••••.•••••••••• (GND - 0.3V) to (V+) + 0.3V Digital Inputs, Vs, Vo (Note 1) ••••• (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) '" •••••••••••..••••• 30mA Currant, S or 0 (Pulsed lrns, 10% Duty Cycle) •.•••••.••• l00mA Storage Temperature Range (0 Suffix) .•..•••.• -65°C to +150°C Thermal Resistance (Note 3) 9JA Plastic DIP Package •••••.••.••••••••••••••••••• 100oCIW SOIC Package ••..••.•...••••••••••.•.••.•.•••• 1200CIW Operating Temperature (0 Suffix) ••••••••••••••• -400C to +85°C Junction Temperature (PDIP, SOIC) ••••••••••••••••••. +1500C CAUTION: Stresses abOIIII those listed In 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions abo1l8 those indicated in the operational sections of this specification is not itrplied. Operating Conditions Operating Voltage Range .•.•.••••.•••••••••••.•••••• ±20V Max Operating Temperature Range .•.•••••••••••.• -55°C to +125°C Input Low Voltage ••.••••.•..•..••.••.•••.••..•... O.BV Max Electrical Specifications Input High Voltage •••••••••••••••••••••••••••••••• 2.4V Min Input Rise and Fall Time •••••••.•.••..•••••••••.•••••.••. S20ns Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, O.BV (Note 3), Unless Otherwise Specified o SUFFIX -400C TO +85°C PARAMETER (NOTE 4) (NOTE 5) (NOTES) (NOTE 5) TEST CONDITIONS TEMP MIN TVP MAX UNITS RL = lkn,CL=35pF, Vs =il0V, (See Figure lB) +2500 - 150 250 ns ns DYNAMIC CHARACTERISTICS Turn-ON Time, TON Turn-OFF Time, TOFF DG444 +2500 DG445 +2500 Charge Injection, Q CL = lnF, Vs = OV, VGEN = OV, RGEN =00 +2500 - - OFF Isolation RL = 500, CL = 5pF, f = lMHz +2500 Crosstalk (Channel-to-Channel) Any Other Channel Switches RL = 500, CL = 5pF, f = lMHz +25°C Source OFF Capacitance, CS(OFF) f=IMHz +2500 Drain OFF Capacitance, COIOFF) f=IMHz +25°C Channel ON CapaCitance, COlON) + CS(ON) VANALOG=O +2500 - 90 120 110 170 ns -1 - pC SO - dB 100 - dB 4 - pF 4 IS - pF pF DIGITAL CONTROL Input Current VIN Low, IlL VIN Under Test = O.BV, All Others = 2.4V Full -0.5 -0.00001 0.5 jtA Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = O.BV Full -0.5 0.00001 0.5 jtA Full -15 Drain-Source ON Resistance, ROS(ON) Is =-10mA, Vo=±B.5V, V+= 13.5V, V-=-13.5V +25OC Full Switch OFF Leakage Current, IS(OFF) V+ = IS.5V, V- = -IS.5V, Vo = ±15.5V, Vs = + 15.5V Switch OFF Leakage Current, ID{OFF) Channel ON Leakage Current, 101ON) + IS(ON) ANALOG SWITCH 15 V - 50 85 0 - - 100 0 +2500 -0.5 0.01 0.5 nA Hot -20 - 20 nA V+ = IS.5V, V- = -IS.5V, Vo =±15.5V, Vs= +15.5V +25°C -0.5 0.01 0.5 nA Hot -20 - 20 nA V+ = IS.5V, V- = -IS.5V Vs =Vo =±15.5V +25OC -0.5 O.OB 0.5 nA Hot -40 - 40 nA Analog Signal Range, VANALOG 9-65 Specifications DG444, DG445 Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Othe.rwise Specified (Continued) D SUFFIX -4O"C TO +85°C PARAMETER TEST CONDITIONS (NOTE 4) TEMP (NOTE 5) MIN (NOTE 6) TVP (NOTE 5) MAX +25°C - 0.001 1 - S +25OC -1 -0.0001 Hot -5 - - +25OC - 0.001 1 - 5 +2SOC -1 -0.001 Hot -5 - UNITS POWER SUPPLIES Positive Supply Current, 1+ V+= 16.5V, V- = -16.5V, VIN =OVor5V Hot Negative Supply Current, I- Logic Supply Current, IL Hot Ground Current, IGNO Electrical Specifications - 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. (Unipolar Supplies) Test Conditions: V+ = +12V, v- = OV, VL = SV, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified o SUFFIX -40oC TO +85°C PARAMETER TEST CONOrrlONS (NOTE 4) TEMP (NOTES) MAX UNITS 300 400 ns 60 200 ns 2 - pC (NOTES) MIN (NOTE 6) TVP - DYNAMIC CHARACTERISTICS Turn-ON Time, TON TUrn-OFF TIme, TOFF Charge Injection, a RL = 1110, CL = 35pF, Vs = 8V, (See Figure 18) +2SoC CL = 1nF, V+ = 12V, VGEN = 6V, +2SoC - Full 0 +25OC ~EN=OO - ANALOG SWITCH Analog Signal Range, VANALOG (Note 5) Drain-Source ON Resistance, ROS(ON) Is=-10mA, Vo=..3V,8V V+ = 10.8V, VL = 5.25V +25OC V+ = 13.2V, VIN = OV or 5V +25OC Full - - 12 V 100 160 0 - 200 0 0.001 1 - 5 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. 11ft. POWER SUPPLIES Positive Supply Current, 1+ Negative Supply Current, I- Logic Supply Current, IL Ground Current, IGNO VIN =OVor5V VL = S.2SV, VIN = OV or SV VIN = OVor SV Full - +25OC -1 -0.0001 Full -5 +25OC 0.001 1 Full - - - S +25OC -1 -0.001 Full -5 - - - NOTES: 1. Signals on Sx, Ox, or INx exceeding V+ or V- will be clamped by internal diodes. Umit forward diode current to maximum current ratings. 2. All leads welded or soldered to PC Board. 3. VIN = input voltage to perform proper function. 4. Hot = as determined by the operating temperature suffix. 5. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, is used in this data sheet. 6. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. 7. Guaranteed by design, not subject to production test. 9-66 DG444, DG445 Typical Performance Curves 105 104 4~----~-----+----~------+-----~ , 103 3~----;------+----~------;-----~ C" 102 J 10 .s. I"'" I+.IGND/ V ..I. :£ ~V 0.1 0.01 °0~----~~----~~~----~~2-----+~--~ 0.001 -55 ~ -" ~V / ~ V".(\-) /" / . / IL f o 50 TEMPERATURE ("C) SUPPLY VOLTAGE M 100 125 FIGURE 2. SUPPLY CURRENT VB TEMPERATURE FIGURE 1. SWITCHING THRESHOLD VB SUPPLY VOLTAGE 80 105 V+=+1SV y. .. ·15V 70 60 103 g:50 V ./ 10 -'" 0.1 -55 0 /' ~ / )40 V 30 100 125 120 80 40 102 103 DoC -40oC" I o ~- 104 105 FREQUENCY (Hz) o ·15 60 40 +15 10' V+_+15V Y..·15V /' .// / 30 20 / // g 10 C L " 1 0 Y /cL=1nF o V/ ./ ·10 20 _ V+ .. +1SV V· .. ·15V REF10dBm o :::::::::::: FIGURE 4. RDS(ON) VB VD AND TEMPERATURE OFFISOLAl1~ 60 ----- +2SOC VD(Yl '" '" '" " 100 i -.......... +85oC ~ 10 FIGURE 3. INPUT CURRENT VB TEMPERATURE ........... -.... 20 - 50 TEMPERATURE ("C) 140 --- ----,,~ ~ ! ........ -20 107 -30 ·10 o +10 Vs(Yl FIGURE 5. CROSSTALK AND OFF ISOLATION VB FREQUENCY 9·67 FIGURE 6. CHARGE INJECTION VB SOURCE VOLTAGE DG444, DG445 Typical Performance Curves (Continued) 20 25 I V+,,+15V ¥- .. ·15V I 20 I .e. ".,- Q If 10 o ~ - - C8ION) + CD(ON) Ii:' 15 ~ ~ V ". o ·10 -Ii 0 5 10 ·100 ·15 15 ./ V+,,+15V v...·15V FOR I(OFF)o VO" .VB - -Ii ·10 VAM FIGURE 7. SOURCE/DRAIN CAPACrrANCE vs ANALOG VOLTAGE V+,"+15V ¥-.·15V ioN 120 80 80 40 20 2 15 "'" - IoN ~ 120 I 100 ~ 'oFF 80 ~ 80 .......... ~ 'oFF 40 3 4 INPUT VOLTAGE (V) 20 ±10 S ±12 ±14 ±16 ±18 SUPPLY VOLTAGE (V) ±20 ±22 FIGURE 10. SWITCHING TIME VB POWER SUPPLY VOLTAGE (DG444) 180 400 V+.+12V,V· .. OV VL"SV VL"SV ~ 140 ~ 120 ~ I 10 140 FIGURE 9. SWrrCHING nME VB INPUT VOLTAGE I I 5 FIGURE 8. SOURCEIDRAIN LEAKAGE CURRENTS - 140 100 0 Vs. Vo (V) 160 160 :g ~ ." IS(ON) + ID(ON) " , . " V -80 ·15 ~ r- -=- CS(OFl')o CD(OFF) 5 - I is(OFl')o ID(OFF) -- ".. 100 80 ioN 300 /' ioN 60 100 r-- 'oFF 40 20 ±10 ±12 ±14 ±18 ±1. SUPPLY VOLTAGE M ±20 ±22 FIGURE 11. SwrrCHING TIME VB POWER SUPPLY VOLTAGE (DG445) o 2 3 4 INPUT VOLTAGE M S FIGURE 12. SWrrCHING TIME VB INPUT VOLTAGE (DG444) 9·68 DG444, DG445 Typical Performance Curves (Continued) 150 600 V+ .. +1SV, v.. ·15V VL-5V , 100 v..OV, VL. 5V 400 ~ ............ ~~ toFF , ~ ~N(4441 300 200 ............ ........ 50 2 3 4 INPUT VOLTAGE M o8 5 FIGURE 13. SWITCHING TIME VI INPUT VOLTAGE (DG445) i"--- to~ 100 o r--.. 10 -- -- -~ toFF(4~ 12 14 16 18 V+ SUPPLY VOLTAGE (VI 20 FIGURE 14. SWITCHING TIMESvs POWER SUPPLY VOLTAGE 10 ~~""'''''''-'''''---r''''''''''~~''''''''''T-''''''''''~ V+.+15V V· .. ·1SV ! ISCOFF)o io(OFF) o ..........~..........-r..........-;~..........+-..........~ ~~ ·10 ~ 10~""''''''~'''''---r''''''''''-;~'''''~~~~~ a -30 ·1 0 0L-..............L............- 4.L-............................- L ................. -40 / v. " ~ V ~ V+ .. +12V V·.OV FORlo.Vs·O FOR Is. VD.O o 6 Va. VD(V) 20 15 - Cs(ON) + Co(ON) ~ CS(OFF)o Co(OFf) 5 o , ",.". FIGURE 16. SOURCEIDRAIN LEAKAGE CURRENTS (SINGLE 12V SUPPLy) III V+.+12V v..OV o 6 VAM - / ~ 12 FIGURE 17. SOURCEIDRAIN CAPACITANCE VI ANALOG VOLTAGE (SINGLE 12V SUPPLy) 9·69 - ~ IS(oN) + IDlON) VIM FIGURE 15. CHARGE INJECTION VI SOURCE VOLTAGE (SINGLE 12V SUPPLy) 22 12 DG444, DG445 Pin Description TRUTH TABLE PIN SYMBOL 1 INI Logic control for switch 1 2 Dl Drain (output) terminal for switch 1 3 Source (input) tenninal for switch 1 4 SI V- 5 GND DESCRIPTION LOGIC VIN 00444. DG445 0 :s0.8V ON OFF :1:2.4V OFF ON 1 Negative power supply terminal Ground tenninal (Logic Common) 6 S4 7 D4 Source (input) terminal for switch 4 Drain (output) terminal for switch 4 8 IN. Logic control for switch 4 Logic control for switch 3 9 INs 10 Ds Drain (output) terminal for switch 3 11 S3 Source (input) tenninal for switch 3 12 VL Logic reference voltage. 13 V+ Positive power supply terminal (substrate) 14 S2 Source (input) tenninal for switch 2 15 D2 Drain (output) terminal for switch 2 16 IN2 Logic control for switch 2 Test Circuits Vo is the steady state output with the switch on. Feedthrough via switch capacitance trailing edge of the output waveform. LOGIC INPUT tR<20ns tF<20na 01 SWITCH INPUT OV SWITCH INPUT Vs Vo SWITCH OUTPUT may result in spikes at the leading and Vo RL LOGIC INPUT o.avo OV J CL 3V - Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications CL (includes fixture and stray capacitance) . R ioN L NOTE: Logic Input waveform Is inverted for switches that have the opposite logic sense. Vo = Vs , , - - - - RL +rDS(ON) FIGURE 1BA. FIGURE 1BB. FIGURE 1B. SWITCHING TIME RG 01 VG': I v- - GNO ov--.l Vo INx r (00444) INx (00445) ~ ~ ON / ON \ Q=AVOXCL FIGURE 19B. FIGURE 19A. FIGURE 19. CHARGE INJECTION 9-70 , ~ \ AVo OFF OFF DG444, DG445 Test Circuits (Continued) Typical Applications FETINPUT OPAMP .15V -~~;;;:..t1~:J.._--t---o VOUT VIN 2 VL GAIN! Ay.l 15 GAlNZ Ay.l0 16 10 g GAlN3 Ay_20 7 FIGURE 20. CROSSTALK GAiNe AV· 1OO B Re llUl 4 GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE, OP AMP OFFSET AND CMRR WILL UMIT ACCURACY OR CIRCUIT OVo 2.4V WITH SWe CLOSED FIGURE 23. PRECISION WEIGHTED RESISTOR PROGRAMMA· BlE GAIN AMPLIFIER FIGURE 21. OFF ISOLATION +5V .15V v• • 15V .15V .....-t--o~o.--t-.....--o VOUT L.J: .5V OV INX Jl.. VIN 101Ul OV,2.4V IMPEDANCE ANALYZER FIGURE 24. lEVEL SHIFTER I =lMHz FIGURE 22. SOURCEIDRAIN CAPACITANCES 9·71 DG444, DG445 Die Characteristics DIE DIMENSIONS: 216011fl1 x 1760llm x 485 ± 251lm METALLIZATION: Type:CuAI Thickness: 12kA ± 1kA GLASSIVATION: Type: Nitride Thickness: akA ± 1kA WORST CASE CURRENT DENSITY: 9.1 x 104Ncm2 Metallization Mask Layout 00444, 00445 INI IN2 (1) (18) (15)0, (14)Sz (13) V+ SUBSTRATE Vo(4) GND(S) (11)8, S.(8) 9-72 (8) (10) I~ Dz HI-200, HI-201 Dual/Quad SPST CMOS Analog Switches December 1993 Features Description • • • • • • HI-20O/H1-201 are monolithic devices comprising independently selectable SPST switches which feature fast switching speeds (HI-200 240ns, and HI-201 185ns) combined with low power dissipation (15mW at +25OC). Each switch provides low "ON" resistance operation for input signal voltage up to the supply rails and for signal current up to 80mA. Rugged 01 construction eliminates latch-up and substrate SCR failure modes. Analog Voltage Range ......................... ±15V Analog Current Range •••••••••••••••••••••• SOmA Turn-On Time .••••••••••.••••••••••••••••• 240ns Low RON ••••••••••••••••••••••••••••••••••• 550 Low Power Dissipation ••••••••••••••••••••• 1SmW TIUCMOS Compatible Applications • • • • High Frequency Analog Switching Sample and Hold Circuits Digital Filters Operational Amplifier Gain Switching Networks All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. HI-2oolHl-201 are ideal components for use in high frequency analog switching. Typical applications include signal path switching, sample and hold circuit, digital filters, and operational amplifier gain switching networks. Functional Diagram _-t---+---------__. +v LOGIC INPUT VREF HI-200 is a dual SPST CMOS analog switch available in DIP and (TO-99) metal cans and is pin compatible with other available "200 series" switches. For Mil-Std-883 compliant parts, request the HI-200/883 data sheet. INPUT REFERENCE, LEVEL SHIFTER, AND DRIVER L~ +_____ -v __ OUTPUT ~===J-o HI-201 is a quad SPST CMOS analog switch available in DIP and SOIC package and pin compatible with other available "200 series" switches. For Mil-Std-883 compliant parts, request the HI-201/883 data sheet. Pinouts HI-200 (CDlP, PDIP, SOIC) HI-201 (CDIP, PDIP, SOIC) HI-201 (20 PIN PLCC, CLCC) TOP VIEW TOP VIEW TOP VIEW INl II- Ne GND 1N4 HI-200 (CAN) TOP VIEW -., L!J LaJ l~j L~J t!9J ~J -., !J -., !J -., !J -., !J r-, r-" ,.-, r-" r-' • 8' '10' '11' '12' '13' § V+ ~ ~ ~ § OUT2 CAUTION: These d9Vices are sens~ive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 . 9-73 File Number 3121 H/~200, HI-201 Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE HI2-02QO-5 OOC to +75"C 10 Pin Melal Can H11-02QO-5 OOC to +75"C 14 Lead Ceramic DIP HI2-0200-4 -25"C 10 +85°C HI3-02DO-5 O"C to +75"C HI2-02DO-7 O"C to +7500 +96 Hr. Burn-In 10 Pin Metal Can HI1-0200-7 O"C 10 +75"C +96 Hr. Burn-In 14 Lead Ceramic DIP Hll-02DO-2 -55"C 10 +12500 14 Lead Ceramic DIP Hll-0200-4 -25°C 10 +85OC 14 Lead Ceramic DIP HI2-02QO-2 -55"C to +12500 10 Pin Metal Can Hll-0201-7 O"C to +75"C +96 Hr. Burn-In 16 Lead Ceramic DIP Hll-0201-5 000 10+75OC 16 Lead Ceramic DIP Hll-0201-4 -25"C 10 +85"C 16 Lead Ceramic DIP H14P0201-5 OOC 10 +75"C 20 Lead PLCC HI9P0201-5 000 to+75°C 16 Lead SOIC (W) H19P0201-9 -4O"C 10 +85°C 16 Lead SOIC (W) Hll-0201-2 -55°C 10 +125"C 16 Lead Ceramic DIP HI3-0201-5 OOC 10+75°C 16 Lead Plastic DIP HI9P0200-5 OOC to +75"C 14 Lead SOIC (N) HI9P0200-9 -40°C 10 +85OC 14 Lead SOIC (N) Hll-0200l883 -55°C 10 +125OC 14 Lead Ceramic DIP HI2-0200l883 -55°C 10 +125"C 10 Pin Melal Can Hll-02011883 -55°C 10 +12500 16 Lead Ceramic DIP HI4-02011883 -55°C 10 +125"C 20 Lead CLCC 9-74 10 Pin Metal Can 14 Lead Plastic DIP HI-200, HI-201 Schematic Diagrams SWITCH CELL TTUCMOS REFERENCE CIRCUIT VREF CELL ..y ~>-------~----------~~ y+ OUTPUT A'>-----------~--------~ GND= DIGITAL INPUT BUFFER AND LEVEL SHIFTER ...----.I--+-- A' y .. P9 ~ 2000 A P10 Y- '---t--t--t--;-- 9-75 x' Specifications HI-200, HI-201 Thermal Information Absolute Maximum Ratings Supply Voltage ..................................44V (:t22) VREF to Ground ..................................+2OV. -5V Digital Input Voltage •••••••••••••••••••••••••• +VSUPPlY +4V ,VSUPPlY -4V Analog Input Voltage (One SwItch) ••••••••••••• ,+VSUPPlY +2.0V ·VSUPPlY -2.0V Storage Temperature ....................... -65"C to +15O"C Lead Temperature (Soldering. 108) ••••••••••••••••••• +300"C Thermal Resistance 9JA Ceramic DiP Package .............. . 80"C1W PLCC Package ................... . 8O"CIW Plastic DIP Package ............... . 10O"C1W Plastic SOP Package (14 Lead) •.••••• 12O"C1W Plastic SOP Package (16 Lead) ••••••• 100"C1W Metal Can Package ................ . 136"C1W 65"C1W Operating Temperature Range HI-2QO-2. HI-201-2•••••••••••••••••••••••• -55"C to +1250 C HI-200-4. HI-201-4......................... -2SOC to +85°C HI-2oo-5. HI-201-5 .......................... ooC to +750 C CAUTION: _ _ abo"" IhDss listed In "Absolute Maximum RaUngs' may caUS/l permanent damage to thB device. This Is a stress only raling and operation of thB d/lvlcs at these or any othBr conditions abo"" those Indicated in the operational sections of this speciflcaUon Is not implied. Electrical Specifications Supplies = +15V. -15V; VREF = Open; VNj (Logic Level High) = 2.4V. VAL (Logic Level Low) = +0.8V. Unless Otherwise Specified. HI-200-4 has Same Specifications as HI-200-5 Over -2ooC to +850 C Temperature Range TEST CONDITIONS HI-20G-2. H1-201-2 TO +125°C -ssec TYP MAX MIN · 60 · · 30 · · · · 240 500 185 TEMP MIN HI-200 +25OC HI-201 +25OC HI-2OO +25OC HI-201 +25OC PARAMETER H1-20G-S, H1201-S OOCTO +7SoC TVP MAX UNITS · 60 · ns · 30 · ns · · 240 1000 · · 1000 · · · ns 500 330 500 · · · · · ns 220 1000 · ns 70 · · dB 80 5.5 · pF 5.5 · · · · pF 0.8 V · V 1.0 IIA SWITCHING CHARACTERISTICS Break-Before-Make DelaY.IoPEN (Note 3) Switch On Time. ioN Full 185 ns ns SwItch Off Time. 10Ft: 220 500 Full · · · 1000 · HI-2oo +25°C - 70 HI-201 +25OC 5 · · · · · · HI-2oo +2SOC HI-201 +2SOC "Off Isolation" 500 ns (Note 4) · · · · Output Switch Capacitance. CO(OFF) +2SOC Output Switch Capacitance. COlON) +25OC Digital Input Capacitance. CA +25°C · · · · · Draln·to-Source Capacitance. Co. S(OFF) +2SOC · 0.5 · · · · 0.8 · · 2.4 1.0 · Input Switch Capacitance. CS(OFF) +2SOC 80 5.5 5.5 11 · 11 · · 5 0.5 dB pF pF pF DIGITAL INPUT CHARACTERISTICS Input Low Threshold. VAl Full · Input High Threshold. VNj Full 2.4 Full · Input Leakage Current (High or Low). IA (Note 2) 9-76 · · · Specifications HI-200, HI-201 Electrical Specifications Supplies =+15V, ·15V; VREF =Open; VAH (Logic LElVel High) =2.4V, VAL (Logic lIIVel Low) =+ IZ W w ~~ Y+=1+15Y, Y.~.15Y/ -:> 100.0 !ZW U f-- Y+D+12Y,Y. ••12Y/ ..", FIGURE 3. "ON" RESISTANCE va ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE 100.0 II: II: """'" 0 ·15 +15 FIGURE 2. "ON" RESISTANCE VB ANALOG SIGNAL LEVEL AND TEMPERATURE :) ----'-.. , ......... 10 10 1 ,+1OV, y•• ·10Y "- 60 ~ ~ w I Y+ .. +lY, y. D"~ "'" w u 50 ./ +125"C .......... """'"-...... II: 30 ~ I TA,,+25oC Y+ D +15Y, y. .. ·15Y . .. ~ 0 2 4 ANALOG INPUT M 6 8 10 12 14 FIGURE 7. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE t Theoretically, leakage current will continue to decrease below +25OC. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. 9·86 HI-201HS Typical Performance Curves (Continued) 60 40 VAL-OV, VAH2-3V, VAllI- 5V_ 20 - 10 8 V+ _ +15V, \L _ -15V, TA _ +25OC 8 ISOFF .... Vo - OV 7 IooFF .... Vs - OV IAlil o l :: C : ..s 4 I: aw ~ ~ - _ Ia ~ -100 -120 -140 -160 -160 -200 _~ ~~ 1AH2 IAL -220 -5 -7 -5 -II -1 0 -16.0 -15.5 -15.0 -14.5 -14.0 +14.0 +14.5 +15.0 +15.5 +16.0 ANALOG INPUT M -240 -260 -2BD:z5 35 45 55 65 75 65 85 .. 105 115 125 TEMPERATURE ("C) FIGURE 8. DIGITAL INPUT LEAKAGE CURRENT VB TEMPERATUREf 1BO FIGURE 9. LEAKAGE CURRENT VB ANALOG INPUT VOLTAGE 350 I 180 f - - toFF2 140 1: 250 V+=+15V V- .. -15V RL-1kO CL=35pF ~ 1= 100 w ::& >= C5 z ~ f--f- ~ toFFl 40 20 r- r- 0-55 RL =1K, CL =35pF, TA" +250 C 300 1 120 i: ~ w -2 '" t'-.., 200 r\ 150 " 100 t;:; ~ ~1 50 toN -35 5254565 -15 85 105 ~ 125 ±5 TEMPERATURE <"C) FIGURE 10. SWITCHING TIME vs TEMPERATURE 350 250 >= C5 z 200 :::E I 350 300 '\ "I\. '" ~....,. 100 7 8 t15 V+=+15V, RL,,1kO CL" 35pF, TA. +25OC w ~ ~FF2 " 200 """ C5 0 11/1 15 ~ .... II 10 11 12 POSITIVE SUPPLY M I\.. 100 ......... toFFl 50 I toN 6 ±14 1: 250 175 150 t7 ±B ±B t10 t11 t12 t13 POSInVE AND NEGAnVE SUPPLY M FIGURE 11. SWITCHING TIME vs POSITIVE AND NEGATIVE SUPPLY VOLTAGE V- _ -15V, RL .1kO CL" 35pF, TA" +25oC 300 1:w ~~ 13 14 0 -5 15 FIGURE 12. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE ..... ~FF2 ~1 toN ~ -5 -7 -II -II -10 -11 -12 NEGAnVE SUPPLY M -13 -14 -15 FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE t Theoretically, leakage current will continue to decrease below +25"0. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. 9-87 HI·201HS Typical Performance Curves (Continued) ...... 3.0 r--.---~....,.--~--,--..,...--~-.---..- HO~----~--~~--------------~-' V+ .. +1SY, \Io ••1SV. RL,,1kn 3001---t---t-f- CL" HpF. VAL" OV, TA" +2S"C ! HOt-----+---~H-----_r----_t----~ ! aot-----+----i~----_r----_t----~ 11S01----If----H~~-tom~....- i €U~~~--+-~~--4--+--r-~~ i ~:: ~f-1Irlii' ··i ii·,·i · · ·• •·i·i · ·_· ·i· · ·i· ·~·i· ,~·~·,· i ·.,~· · m ..._ j!:1.5I--+--+--+--+~~+--I--+--+--I ....- - " " § 1.01-+-1-+-1-+-1-+-1-+--1 1001---1---i1---1---1----I i I 50r-----t-~~~~==~~FF~~===$====~ I ~N I ~~----~1----~2----~3~----4~--~6 0.51--+--+--+--+~f-+--1--+--+--I ±6 0:li ±7 DIGITAL INPUT AMPUTUDE (V) FIGURE 14. SWITCHING TIME VI INPUT LOGIC AMPUTUDE ±6 ±I ±10 ±11 ±12 ±13 ±14 ±16 POWER SUPPLY VOLTAGE (V) FIGURE 15. INPUT SWITCHING THRESHOLD VI POSITIVE AND NEGATIVE SUPPLY VOLTAGES H~::~::::~::~~COO~N~::::~:::t1 30./ ~H~~---~---~---~---+--~~ ~ ~ al--~--4--+---+--I--~ i~ 15~-4---r-~~-~-~--4~ i'CooFF OR CSOFF 10 ....0 - CosoFF 61--~--+-~~-+--~--f~ V+,"+16V,\Io .. ·16V CL .. 1000pF, RIN .. OQ ~~~0------~~~----~0~--~-~~--~--+~10 ~15 ·10 -I ANALOG INPUT (V) FIGURE 16. CHARGE INJECTION VI ANALOG INPUT 140 V+.+15V, \Io.·15V 120 VIN·3V_ VA·3V V+ .. +15V, Yo .. ·15V ..... i 60 ~ 40 • IN """--- .... r-. -= I fi:~ 80 RL,,10Dn 1t-t+tttH 60 ~~-W.~+I v 20 OFFlSOLAnON dOLOG v: .. ~ OUT' ~I::"""""~HI'I'i1..+fF""oI=:- VINsf°l~~O -= +15 120 1---+--+-H-l+++I---+--+-H- VIN" 3VR.... VA" 3V _100 m 80 •••••• +10 FIGURE 17. CAPACITANCE VI ANALOG INPUT 140~-----------,~-nnTnr--~rrTn~ ~_ 0 +5 ANALOG INPUT (V) 11111 U I ++HI*11I1--I-t-t-l+f+H VIN ~ _ RL,,1kSl -= 1;V02 _RL"1kn 40 20 V02 CROSSTALK. aLOG O~~~~~____~V~OlWU~L--L~~~ 10K 100K 1M 10M FREQUENCY (Hz) fO~K~~~~~1~00~K~~~~ll1~M~L-LL~Ul~0'M FREQUENCY (Hz) FIGURE 18. OFF ISOLATION VI FREQUENCY FIGURE 19. CROSSTALK VI FREQUENCY 9·88 HI-201HS Test Circuit 13 SWITCH INPUT 3 2 VIN .. + 1 0 V - - t - - -.... o---+~-+-- ......- SWITCH OUTPUT Vo LOGIC INPUT CL INCLUDES CFlXTURE + CpROBE GND FIGURE 20. SWITCHING TEST CIRCUIT (toN' toFFI' tom> Switching Characteristics Typical delay. toN. toFI1 settling time and switching transients in this circuit. If RL or CL is increased. there will be corresponding increases in rise and/or fall RC times .. V+=+15V N GND FIGURE 21A. LOGIC INPUT 3 2 o FIGURE 21B. FIGURE 21. SWITCHING CHARACTERISTICS vs INPUT VOLTAGE 9-89 HI-201HS Switching Characteristics (ContInued) +10 +6 +6 o o 22A. VIN =+10V 22B. V IN • +5V +5 o o .. +5 22C. VIN =OV 220. VIN o -5 ·10 22E. V IN • -10V FIGURE 22. Vo - OUTPUT SWITCHING WAVEFORMS 9-90 =-5V HI-201HS Application Information Power Supply Considerations Logic Compatibility The electrical characteristics specified in this data sheet are guaranteed for power supplies ±Vs = ±15V. Power supply voltages less than ±15V will result in reduced switch performance. The following information is intended as a design aid only. The HI-201HS is TTL compatible. Its logic inputs (Pins 1, 8, 9, 16) are designed to react to digital inputs which exceed a fixed, internally generated TTL switching threshold. The HI-201HS can also be driven with CMOS logic (OV-15V), although the switch performance with CMOS logic will be inferior to that with TTL logic (OV-5V). POWER SUPPLY VOLTAGES t12< tVst15V The logic input design of the HI-201 HS is largely responsible for its fast switching speed. It is a design which features a unique input stage consisting of complementary vertical PNP and NPN bipolar transistors. This design differs from that of the standard HI-201 product where the logic inputs are MOS transistors. Although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. Therefore, the HI-201HS will exhibit larger digital input leakage currents in comparison to the standard HI-201 product. Charge Injection Charge injection is the charge transferred, through the internal gate-ta-channel capacitances, from the digital logic input to the analog output. To optimize charge injection performance for the HI-201 HS, it is advisable to provide a TTL logic input with fast rise and fall times. If the power supplies are reduced from ±15V, charge injection will become increasingly dependent upon the digital input frequency. Increased logic input frequency will result in larger output error due to charge injection. SWITCH PERFORMANCE Minimal Variation tVs t16V Not Recommended. Single Supply The switch operation of the HI-201HS is dependent upon an internally generated switching threshold voltage optimized for ±15V power supplies. The HI-201 HS does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI-300 series of switches is recommended. The HI-300 series will remain operational to a minimum +5V Single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels (±15V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For Further Information See Application Notes 520, 521, 531,532,543 and 557. 9-91 HI-201HS Die Characteristics DIE DIMENSIONS: 2440J.Un x 2860J.Un x 485J.Un.± 25ltm METALLIZATION: Type: CuAI Thickness: 1SkA±2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.qkA ± '\.kA Silox Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 9.5 x 104Ncm2 Metallization Mask Layout HI-201HS A1 OUT2 OUT1 IN2 IN1 v+ GND 1N4 IN3 OUT4 ooT3 A4 A3 9-92 HI-300 thru HI-307 CMOS Analog Switches December 1993 Features Description • • • • • • • • • The HI·300 thru HI·307 series of switches are monolithic devices fabricated using CMOS technology and the Harris dielectric isolation process. These switches feature break-beforemake switching, (HI-301, HI-303, HI-30S and HI-307 only), low and nearly constant ON resistance over the full analog signal range, and low power dissipation, (a few mW for the HI-300 thru HI-303, a few hundred mW for the HI-304 thru HI-307). Analog Signal Range (±15V Supplies) ±15V Low Leakage (TypIcal at +250 C) 40pA Low Leakage (Typical at +l25°C) 1nA Low On Resistance (TypIcal at +250 C) 350 Break-Before-Make Delay (TypIcal) SOns Charge Injection 30pC TTL, CMOS CompatIble Symmetrical SwItch Elements Low OperatIng Power 1.0mW (TypIcal for HI-300 - 303) Applications • • • • • Sample and Hold (I.e. Low Leakage SwItching) Op Amp GaIn SwitchIng (I.e. Low On ResIstance) Portable, Battery Operated CIrcuIts Low Level SwitchIng CIrcuits Dual or SIngle Supply Systems The HI-300 thru HI-303 are TTL compatible and have a logic "(1' condition with an Input less than O.8V and a logic "1" condition with an input greater than 4.0V. The HI-304 thru HI-307 switches are CMOS compatible and have a low state with an input less than 3.SV and a high state with an input greater than l1V. (See pinouts for switch conditions with a logic "1" input.) All the devices are available in a 14 lead Epoxy or Ceramic DIP. The H1-300, HI-301 , HI·304 and HI-30S are also available in a 10 pin Metal Can. Each of the switch types are available in either the ·SSoC to +12SOC or OOC to +7SoC operating ranges. Pinouts (SwItch States are for a logic "1" Input) DUAL SPST HI-300 AND HI-304 TOP VIEWS (CDIP, PDIP, SOIC) (METAL CAN) SPST HI-30l AND H1-305 TOP VIEWS (CDIP, PDIP, SOIC) (METAL CAN) v+ v+ D:I NC NC GND LOGIC SWITCH o OFF ON * The substrate and case are internally tied to Va. (The case should not be used as the Vconnection, however.) DUAL DPST HI-302 AND HI-306 (PDIP, CDIP, SOIC) TOP VIEW LOGIC SWl SW2 o OFF ON ON OFF * The substrate and case are internally tied to Va. (The case should not be used as the Vconnection, however.) DUAL SPOT H1-303 AND HI-307 (PDIP, CDIP, SOIC) TOP VIEW LOGIC SWITCH 0 OFF LOGIC SWl SW2 1 ON 0 OFF ON 1 ON OFF CAUTION: These devices are sensitiva to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 9-93 SW3 SW4 File Number 3125 HI-300 thru HI-307 Ordering Information PART NUMBER HI1-030Q-2 HI1-0300-S HI2-0300-2 HI2-0300-S HI3-0300-S H19P03D0-5 HI9P0300-9 HI1-0301-2 HI1-0301-S HI2-0301-2 HI2-0301-S HI3-0301-S HI9P0301-5 HI9P0301-9 HI1-0302-2 HI1-0302-S HI3-0302-S H19P0302-5 HI9P0302-9 HI1-0303-2 HI1-0303-S HI3-0303-S HI9P0303-5 HI9P0303-9 TEMPERATURE RANGE -Ssoc to +12S·C O"C to +7SOC -ssOC to +12S·C O"C to +7SOC DOC to +7SOC O"C to +7SOC -4O"C to +8SOC -SSOC to +12S·C O"C to +7SOC -55OC to +1250C DOC to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC -55OC to +12S·C O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC -SSOC to +12S·C O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC PACKAGE 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin TQ-S Can 10 Pin TQ-S Can 14 Lead Plastic DIP 14 LeadSOIC 14 LeadSOIC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin TQ-S Can 10 Pin T0-5 Can 14 Lead Plastic DIP 14 LeadSOIC 14 Lead SOIC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Plastic DIP 14LeadSOlC 14LeadSOlC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Plastic DIP 14 Lead SOIC 14 LeadSOIC PART NUMBER HI 1-0304-2 H11-0304-5 HI2-0304-2 HI2-0304-S HI3-0304-S H19P0304-6 HI9P0304-9 H11-0305-2 HI1-0305-S HI2-0305-2 HI2-0305-S HI3-0305-S HI9P0305-5 HI9P0305-9 HI1-0306-2 HI1-0306-S HI3-0306-S HI9P0306-5 HI9P0306-9 HI1-0307-2 HI1-0307-S HI3-0307-5 HI19P307-5 HI9P0307-9 Functional Block Diagram TYPICAL SWITCH HI-3OO SERIES IN 9-94 TEMPERATURE RANGE -55OC to +12SOC O"C to +7SOC -55OC to +12SOC O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC -55OC to +125"C O"C to +7SOC -SSOC to +1250C O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC -55OC to +12S·C O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +85OC -55OC to +125·C O"C to +7SOC O"C to +7SOC O"C to +7SOC -4O"C to +8SOC PACKAGE 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin T0-5 Can 10 Pin TQ-S Can 14 Lead Plastic DIP 14LeadSOlC 14 LeadSOIC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin TQ-S Can 10 Pin TQ-S Can 14 Lead Plastic DIP 14 Lead SOIC 14LeadSOlC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Plastic DIP 14LeadSOlC 14LeadSOlC 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Plastic DIP 14 LeadSOIC 14 LeadSOIC HI-300 thru HI-307 Schematic Diagrams SWITCH CELL A __--~~====~--~ OUT IN A__----~====~--~ DIGITAL INPUT BUFFER AND LEVEL SHIFTER v+ D2A LOGIC IN D1A GND v- SWITCH CELL DRIVER (ONE PER SWITCH CELL) 9-95 Specifications HI-300 thru HI-307 Absolute Maximum Ratings Thermal Information Voltage Between Supplies ••••••••••••••••••••••• 44V (±22V) Digital Input Voltage •••••••••••••••••.•••••••• +VSUPPLV +4V -VSUPPLY -4V Analog Input Voltage •••••••••••••••••••••.•• +VSUPPLY +1.5V -VSUPPLY -1.5V Storage Temperature Range ••••••••••••••••• -6500 to +1oooC Lead Temperature (Soldering 1Os) ••••.••••••••••••••• +3000C Typical Derating'Factor••••••••••• 1.5mAlMHz Increase In ICCOP ESD Classification ••••••••••••••••••••••••••••.••• Class 1 Thermal Resistance 9JA 9Jc 14 Lead Ceramic DIP •••••••••••••• • 95"CIW 24°CIW 14 Lead Plastic DIP ••••••••••• '•••••••• 1000 CIW 14 Lead SOIC • • • • • • • • • • • • • • • • • • • • • 12O"C1W 10 Pin TO-1oo Metal Can • • • • • • • • • • • • 136"CIW 650 CIW Maximum Power Dissipation Ceramic DIP •••••••••••••••••.••••••••••••••••• 588mW Plastic DIP ••••••••.•••••••••••••••••••••••••••• 526mW Metal Can ••••••••••••••••••••••••••••••••••••• 435mW Derate 6.9mWfOOC above TA +700 C Operating Temperature Range HI-3XX-2 .••••••••••.••••••••.•••••••••• -55°C to +125°C HI-3XX-5 ••••••••••••••••••••••••••••••••• O"C to +750 C Junction Temperature Ceramic DIP. TO-Can ••••••.••••••••••••.••••••.• +175°C Plastic DIP. SOIC ••••••••••••.•••.••••••••••••••• +150oC = CAUTION: Stresses above /hose Psted In "Absolute Maximum RaUngs" may cause permanent damage to /he device. This Is a stress only raUng and operation of /he device at these or any other conditions above those indicated In the operational sections of this specificaUon Is not implied. Electrical Specifications = = = Supplies +15V. -15V; VIN logic Input. HI-3OO-303: VIN - for Logic "1" 4V. for Logic "0" HI-304-307: VIN - for Logic "1" 11V. for Logic"rr z 3.5V. Unless Otherwise Specified. = I -55°C TO +125°C OOCTO+75°C TEMP MIN TYP MAX MIN Break-Balora-Make DelaY.IoPEN (Note 15) +25OC - Switch On Time. ioN (Note 13) - 60 +25OC - PARAMETERS =0.8V. TYP MAX UNITS SWITCHING CHARACTERISTICS Switch Off Time. IoFF (Note 13) +25°C Switch Off Time. ioN (Note 14) +25OC Switch Off Time.IoFF (Note 14) +25°C "Off Isolation" (Note 6) +25°C Charge Injection (Nota 7) +25°C Input Switch Capacitance. CS(OFF) +25°C - - 210 300 160 250 160 250 100 150 60 - 3 16 Output Switch CapaCitance. CD(OFF) +25°C Output SWitch CapaCitance. CO(ON) +25°C - 35 14 (High) Digital Input Capacitance. CIN +25OC +25OC - 5 (Low) Digital Input Capacitance. CIN - 5 - - - - - - 60 - ns 210 300 ns 160 250 ns 160 250 ns 100 150 ns 50 - dB 3 16 14 35 - mV pF pF pF 5 - pF - 5 pF DIGITAL INPUT CHARACTERISTICS Input Low Level. VINL (Note 13) Full - Input High Level. VINH (Note 13) Full 4 Input Low Level. VINL (Nota 14) Full - Input High Level. VINH (Note 14) Full 11 Input Leakage Current (Low). IINL (Note 5) Full Input Leakage Current (High). IINH (Note 5) Full · · - - 0.8 V - 4 - - V 3.5 · · · · · 3.5 V 0.8 11 . 1 - 1 · · . 1 1 V IIA IIA ANALOG SWITCH CHARACTERISTICS Analog Signal Range On Resistance. RoN (Nota 2) Off Input Leakage Current. IS(OFF) (Nota 3) Full ·15 . +15 ·15 +25°C - 35 50 40 75 0.04 1 1 100 Full - +25°C · · Full 9·96 +15 V - · 35 50 (} · · · 40 75 n 0.04 5 nA 0.2 100 nA Specifications HI-300 thru HI-307 Electrical Specifications Supplies = +ISV, -ISV; VIN = Logic Input. HI-300-303: VIN - for Logic "I" = 4V, for Logic "0" = 0.8V. HI-304-307: VIN - for Logic "I" = llV, for Logic "0" = 3.SV, Unless Otherwise Specified. (Continued) OOCTO+75°C ·55°C TO + 125°C PARAMETERS Off Output Leakage Current, IO(OFF) (Note 3) On Leakage Current, IO(ON) (Note 4) TEMP MIN TVP MAX MIN TVP MAX UNITS +2SOC · 0.04 1 · 0.04 S nA 100 0.2 100 nA Full - 1 - +25°C · 0.03 1 - 0.03 S nA Full - O.S 100 · 0.2 100 nA +2SoC 0.09 O.S · 0.09 O.S mA - 1 · - 1 rnA +25°C - 0.01 10 0.01 100 Full · - 100 - +25°C - 0.01 10 0.01 100 /.LA /.LA /.LA - 100 0.01 10 - - - POWER SUPPLY CHARACTERISTICS Current, 1+ (Notes 8, 13) Full Current, I· (Notes 8, 13) Current, 1+ (Notes 9, 13) Full - Current, 1- (Notes 9,13) +2SoC - Current,l+ (Notes 10, 14) +2SoC - Full - Full Current,l- (Notes 10, 14) +25°C Full Current, 1+ (Notes II, 14) +25OC Current, 1- (Notes II, 14) +2SoC · · Full - - Full - 100 0.01 10 . 100 0.01 10 . 100 0.01 10 - 100 0.01 10 - 100 - - - - - 0.Q1 100 I1A /.LA /.LA - - 0.01 100 I1A - . /.LA 0.01 100 I1A - - /.LA 0.01 100 I1A I1A - - 0.01 100 /.LA - - I1A NOTES: 1. As wtth all semiconductors, stresses listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resutting in permanent damage. This 15 a stress ratlng only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Specifications" are the only conditions recommended for satisfactory operation. 2. Vs = ±10V, lOUT = +.10mA. On resistance derived from the voltage meesured across the switch under the above conditions. 3. Vs =±14V, Vo= + 14V. 4. Vs = Vo = ±14V. 5. The digital Inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. Vs= lVRMS , 1= SOOkHz,C L = 15pF, RL= lK. 7. Vs = OV, CL = 10,OOOpF, logic Drive = SV pulse. (HI-300 - 303) SWitches are symmetrical; S and D may be interchanged. Logic Drive = ISV (HI-304 - 307). 8. VIN = 4V (one input) (an other inputs = OV). 9. VIN = 0.8V (all inputs). 10. VIN = ISV (an Inputs). 11. VIN = OV (all inputs). 12. To drive Irom DTLlrTL circuits, pullup resistors to +SV supply are recommended. 13. HI-3oo thru HI-303 only. 14. HI-304 thru HI·307 only. IS. HI-301, HI-303, HI-30S, HI-307 only. 9-97 HI-300 thru HI-307 Typical Performance Curves ~~---r----T---~----~----r----' TA,,+2iiOC Y+" +15Y, y." ·15Y 1/ --. r-- ,....... B r-- r-- DRAIN VOLTAGE (V) FIGURE 1. RDS(oN) vs VD AND TEMPERATURE 100 Y+" +15Y, y." ·1SY TA. +25°C, Ys ,,15V, RL" 2K 80 I I iii' :l!. ~ 60 j /1 1 It 0 ~51 "'" 15 ~.100n "~ I'.... I 1 10 100 1K 10K 100K 1M LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) 110.0 Ig 10 20 107 10' FREQUENCY (Hz) FIGURE 3. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY SINGLE LOGIC INPUT ~~ ~ Y+ .. +15V, y." ·15V CLOAD" 3OpF, Ya ,,1YAMS RL= lien 0 !I! 40 HI-304 THRU HI-307L I -- ./ FIGURE 2. RDS(oN) vs VD AND POWER SUPPLY VOLTAGE 100 0.1 A A Y+ .. +15Y, y. .. ·15Y B Y+" +10Y, y." ·10Y ~ Y+ .. +7.SY, y." ·7.SY D Y+" +&Y, y... 4Y ~15 oS 0 5 ·10 DRAIN YOLTAGE (V) ~~5--~~~0~--~4~--~0----~5~---1~0~--~15 HI-300 THRU HI-3~ _I '- ;..... ..- FIGURE 4. OFF ISOLATION vs FREQUENCY 10.0 Y+" +15Y, y." ·15Y Y+. +15Y, y." ·15Y I YD 1.1 YB 1.14Y 1.0 .- ./ 0.1 0.01 25 ./" ./ 0.01 25 75 125 TEMPERATURE rC) FIGURE 5. I8(OFF) OR ID(OFF) vs TEMPERATUREt 7S 125 TEMPERATURE rC) FIGURE 6. Io(ON) VI TEMPERATUREt t The net leakage Into the source or drain Is the n-channelleakage minus the p-channelleakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 9·98 HI-300 thru HI-307 Typical Performance Curves (Continued) +15V9 I V+ £ D 6r-~*-~~~E~~~~~ Hl400 THRU HI403 4r-+-~-+~r-r-~~-.--.-~ i :~~~~~~~~~~~~~~~ R!J J,CL 10kn.£,. J10PF ~ t--t-- o 7A. TEST CIRCUIT £ LOGIC INPUT 0.4 0.1 nME (Jl8) 1.2 1.6 7B. VIN(LOGlC) VB TIME 15r-~--~~~r-~:~H~14~M~TH~R=U~H~14~~~ 10f--f--+-+--+-;~:E--t--r--t---t--l 5 5r-~--r--r~r-~--r--r--r--r~ ~ O~~H+~~~~~~~~~~~~ u § f--+--+ LOGIC INPUT3::~:--+--+_+--+---! ; o 0.4 0.8 nME (Jl8) o 1.2 0.4 0.1 nME("s) 1.2 1.8 1.2 1.6 1.2 1.8 70. VOUT VB TIME 7C. V1N(LOGlC) VB TIME £w ~ ~r-+-~-+--~~~~~--r-+-~ g O~~J~#H****~~~~~~ 5 ~ - - VGEN· 5V o 0.4 -:E--+--+--+--+--l 0.8 nME(j1a) 1.2 o 1.6 7E. Vour VB TIME o 0.4 0.1 nME (jla) 0.4 0.8 nME (jla) 7F. VOUT VB TIME o 1.2 7G. VOUT VB TIME 0.4 0.8 nME (jla) 7H. VOUT VB TIME NOTE: If RGEN , RL or CL is Increased, there will be proportional Increases In rise and/or fall RC times. FIGURE 7. TYPICAL DELAY, RISE, FALL, SEnLING TIMES AND SWITCHING TRANSIENTS 9-99 HI-300 thru HI-307 Typical Performance Curves (Continued) 60r---r---r---r---r---r---r---~--~ iw (,) i 50 2 ~ ~ ~ 12r---t---t---t---t---t---+---;---~ ~ .~~~~~~+-~-+~ TRANSITION (INDETERMINATE 40 C1 z z o 0 ... 30 !; i l- i!! DUE TO ACTIVE INPUT) HJ.3OO THRU HJ.303 ___ ~~~--1---1---~--~---r--" 4t:~==~=~1;~1~~~1~~1:1 I ~I HJ.304 THRU HJ.307 I I 4 6 8 10 12 14 jANSmlON 20 0 2 4 10 12 14 18 o 8 6 DRAIN VOLTAGE IV) 2 16 INPUT VOLTAGE (V) FIGURE 8. OUTPUT ON CAPACITANCE VB DRAIN VOLTAGE FIGURE 9. DIGITAL INPUT CAPACITANCE VB INPUT VOLTAGE V+ .. +15V, Yo .. ·15V VINH _15V, VINL _ OV !I 200r--;---+---r--;---t---r--;~~--~ >~ __ r-__ ~--~ i ~UI 10ol:::=l;;;::::+=+-+:::t--F9==f==J 'oFF .fi -35 ·15 5 25 45 66 86 105 125 .fi TEMPERATURE JOC) -3& ·15 5 25 46 66 86 106 125 TEMPERATURE JOC) FIGURE10. SWITCHINGTIMEvBTEMPERATURE,HJ.300THRU HJ.303 FIGURE 11. SWITCHING TIME VB TEMPERATURE, HJ.304 THRU HI-307 - ~ 1=200 i 'oFF !! 1001-----+~~--+----"""" o 5 10 NEGATIVE SUPPLY M FIGURE 12. SWITCHING TIME VB NEGATIVE SUPPLY VOLTAGE, HJ.300 THRU HI·303 o 16 10 5 NEGATIVE SUPPLY (V) FIGURE 13. SWITCHING TIME V8 NEGATIVE SUPPLY VOLTAGE, HJ.304 THRU HI-307 9-100 15 HI-300 thru HI-307 Typical Performance Curves (Continued) 1.8 V- _ ·1SV, TA _ +25OC VINH - 4.0V, VINL - OV V- ••1SY, TA. +25°C VINH • 15V, VINL. OV 1.6 1.4 Jw 1.2 \ I ::Ii i= 1.0 \. \ ~ ~ ~ 0.8 ~ 0.8 ~ 0.4 IOF~ 0.2 IoFF- ioN taBU H14011303 ONLY o o 5 10 posmVE SUPPLY VOLTAGE (V) 15 100-. IoN ~- 5 10 posmVE SUPPLY VOLTAGE M fiGURE 14. SWITCHING TIME VI POSITIVE SUPPLYVOLTAGE, HI·304 THRU HI-307 fiGURE 15. SWITCHING TIME AND BREAK·BEfORE.MAKE TIME VI POSITIVE SUPPLY VOLTAGE, HI-300 THRU HI-303 ~ 7~-------r--------~------~ w V-_·15Y, TA- ~ 81-----11-- ~ sl-----+---....., !a: 41------1- ~ 1,1----- j!: 3 I--------F--------I~ i 15 °0L---------~5~--------~10----------~15 POSITIVE SUPPLY VOLTAGE M fiGURE 16. INPUT SWITCHING THRESHOLD VI POSITIVE SUPPLY VOLTAGE, H1-300 THRU HI-307 9-101 HI-300 thru HI-307 Test Circuits SWlTCHTYPE V1NH SWITCH TYPE V1NH HI-300 Ihru HI-303 4V HI-30l. HI-303 5V HI-304 thru HI-307 l5V HI-305. HI-307 l5V +1SV +15V V+ V+ Vs =+3V ~+--~,~-+~-----.--.~OUT1 S O _ +_ _-o1o-_....._D~~......----oVO SWITCH OUTPUT o-+--~~-+~~-.---+--t~OUT2 LOGIC INPUT LOGIC INPUT V-15V -1SV LOGIC INPUT OV LOGIC ·1"" SWITCH ON LOGIC RU = RL2 " 3000 Cu " CL2 • 33pF VINH 1 " - -..... IN:~~50% Vs i, 9 0% __ ..ir--/:. ' ; OV SWITCH OUTPUT LOGIC ·1" • SWITCH ON --.::.J +~!,,;;,50%;.;.;.._ __ ; __ i-.'ioN' fiGURE 18. BREAK·BEfORE-MAKE TEST CIRCUIT (tBBM) fiGURE 17. SWITCHING TEST CIRCUIT (ioN. 'oFF) 9-102 HI-381 thru HI-390 CMOS Analog Switches December 1993 Features Description • • • • • • • • The H1-381 thru HI-390 series of switches are monol~hic de· vices fabricated using CMOS technology and the Harris dielectric isolation process. These devices are TIL compatible and are available in four switching configurations. (See device pinout for particular switching function with a logic "1" input.) Analog Signal Range (±15V Supplies) ±15V Low Leakage 40pA Low On Resistance 350 Break-Befora-Make Delay 60ns Charge Injection 30pC TTL Compatible Symmetrical Switch Elements Low Operating Power 1.0mW These switches feature low leakage and supply currents, low and nearly constant ON resistance over the analog signal range, break-before-make switching and low power dissipation. The HI-381 and HI-387 switches are available in a 14 lead Plastic, Ceramic DIP, or 10 pin Metal Can. The HI-384 and HI-390 are available in a 16 lead Plastic or Ceramic DIP. Each of the indivual switch types are available in the -SSoC to +12SoC, -40°C to +SSoC, or OOC to +7SOC operating ranges. Applications • • • • • Sample and Hold (I.e. Low Leakage Switching) Op Amp Gain Switching (I.e. Low On Resistance) Portable, Battery Operated Circuits Low Level Switching Circuits Dual or Single Supply Systems Pinouts (Switch States are for a logic "1" Input) SPDTHI-387 TOP VIEWS DUAL SPST HI-381 TOP VIEWS (CDIP, PDIP, SOIC) (METAL CAN) o OFF ON ~ (CDIP, PDIP, SOIC) (METAL CAN) D2 • The substrate and case are Internally tied to V-. (The case should not be used as the Vconnection, however.) • The substrate and case are Internally tied to V-. (The case should not be used as the Vconnection, however.) DUAL DPST HI-384 (CDIP, PDIP, SOIC) TOP VIEW o OFF ON ON OFF DUAL SPOT HI·390 (CDlP, PDIP, SOIC) TOP VIEW LOGIC SW1-4 0 1 OFF LOGIC SW1 SW2 ON 0 OFF ON 1 ON OFF CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corpotation 1993 9-103 SW3 SW4 File Number 3126 HI-3S1 thru HI-390 Functional Slock Diagram Ordering Information PART NUMBER HI1-0381-2 HI1-0381-5 H11-03811883 HI2-0381-2 HI2-0381-5 TEMPERATURE RANGE -55°C to +125°C 00Cto+75°C -55OC to +125°C -55°C to +125OC 00Cto+75°C H12-03811883 HI1-0384-2 HI1-0384-5 HI1-03841883 H19P0384-5 HI1-0387-2 HI1-0387-5 HI2-0387-2 HI2-0387-5 HI9P0387-5 HI1-0390-2 HI1-0390-5 H11-03901883 H19P0390-5 HI3-0381-5 H19P0381-5 HI9P0381-9 -55OC to +125°C -55°C to +125°C OOCto +75°C H11-0387/883 HI2-0387/883 HI3-0387-5 HI9P0387-9 HI3-039Q-5 HI3-0390-9 HI3-0384-5 HI3-0384-9 -55°C to +125°C -55°C to +125°C OOCto +75°C -400C to +85OC OOCto +75OC -400C to +85OC -55OC to +125°C OOC to+75°C -55°C to +125OC OOCto +75°C -55°C to +125°C OOCto +75°C OOCto +75OC -55OC to +125°C OOCto +75°C -55°C to +125°C oOC to +75°C Ooc to +75°C Ooc to +75°C -400C to +85OC OOCto +75°C -400C to +85°C TYPICAL SWITCH 3XX SERIES PACKAGE 14 Lead Ceramic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin TO-5 Metal Can 10 Pin T0-5 Metal Can 10 Pin T0-5 Metal Can 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic SOIC (W) 14 Lead Ceramic DIP 14 Lead Ceramic DIP 10 Pin TO-5 Metal Can 10 Pin T0-5 Metal Can 14 Lead Plastic SOIC 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic SOIC (W) 14 Lead Plastic DIP 14 Lead Plastic SOIC 14 Lead Plastic SOIC 14 Lead Ceramic DIP 10 Pin T0-5 Metal Can 14 Lead Plastic DIP 14 Lead Plastic SOIC 16 Lead Plastic DIP 16 Lead SOIC (W) 16 Lead Plastic DIP 16 Lead SOIC (W) Schematic Diagrams SWITCH CELL DIGITAL INPUT BUFFER AND LEVEL SHIFTER D2A 2000 LOGIC~WH-"" IN D1A GND~ __ ~ ____ ~ ______ ~ ______ ~ ~~---+--------------------------~--------+------4------~--r---~ SWITCH CELL DRIVER (ONE PER SWITCH CELL) 9-104 Specifications HI-381 thru HI-390 Absolute Maximum Ratings Thermal Information Voltage Between Supplies ••••••••.••.••.•••••••• 44V (±22V) Digital Input Voltage ••••••••••.••••••••.•.•••• +VSUPPLY +4V Thermal Resistance 8JC 8JA 2400IW Ceramic DIP Package, 14 Lead •••••••• 95"CIW 2400IW Ceramic DIP Package, 16 Lead •••••••• BO"CIW Plastic DIP Package, 14 Lead ••••••••• 100"C1W Plastic DIP Package, 16 Lead •.••• ,•••• 100"C1W Plastic.SOIC Package,14 Lead ••••••• 12O"C1W Plastic SOIC Package, 16 Lead ••••••• 100"C1W Metal Can Package ••••••••••••••••• 13600lW 6500IW Junction Temperature Ceramic DIP ••••••••••••••••••••••••••••••••••• +175°C Plastic DIP ••••••••••••••••••••••••••••••••••••• +1 SOOC Plastic SOlO ••••••••••••••••••••••••••••••••••• +1 SOOC Metal Can ••••••••••••••••••••••••••••••••••••• +175°C Operating Temperature Range HI-3XX-2 .•••••••••••••••••••••••••••••• -5500 to +1250 C HI-3XX-5 ••••••••••••••••••••••••••••••••• O"C to +7500 HI-3XX-9 •••••••••••••••••••••••••••••••• -40"C to +65"C -VSUPPLY -4V Analog Input Voltage •••••••••••••••••••••••• +VSUPPLy +1.5V -VSUPPLy-1.5V Storage Temperature Range ••••••••••••••••• -65°C to +150oC Lead Temperature (Soldering 10s) •••••••••••••••••••• +300"C CAUTION: Strsssss &bow thoss listed In "Abso/uts Max/mum Ra/lngs' may cause permanent damage 10 1M dav;c.. This is a slrllSs only m/lng and op9mtlon 0/ the dlWice atlhsse or any other condiliOflS"'bow thoss indicated in 1M operational sections o/this specification is not impned. Electrical Specifications = = Supplies +15V, -15V; VIN Logic Input. VIN for Logic "1" Unless Otherwise Specified. =4V, for Logic "0" =O.BV, HI-3XX-2 PARAMETERS TEST CONDITIONS TEMP I I MAX I MIN TYP - 60 - 210 300 160 250 I HI-3XX-5-9 MIN TYP MAX UNITS - 60 - ns SWITCHING CHARACTERISTICS Break-Before-Make DelaY,loPEN (HI-387/HI-390 Only) +2500 Switch On TIme,loN +2500 Switch Off TIme, IoFF +2500 "Off Isolation" (Note 5) +2500 Charge Injection (Note 6) +2500 Input Switch Capacitance, CS/OFF) +2500 OUtput Switch Capacitance, CO(OFF) +2500 Output Switch CapacitanCe, COlON) +2500 DIgltallnput Capacitance (High), CIN +2500 Digital Input Capacitance (Low), CIN +2500 - - 5 - - O.B - - 60 3 16 14 35 5 - - - 210 300 160 250 60 3 16 14 35 5 5 - - ns ns dB mV pF pF pF pF pF DIGITAL INPUT CHARACTERISTICS Input Low Level, VINL Full - Input High Level, VINH Full 4 Input Leakage Current (Low), IINL (Note 4) Full Input Leakage Current (High), IINH (Note 4) Full - Full -15 On Resistance, RoN (Note 1) +2500 - Off Input Leakage Current, IS(OFF) (Note 2) +2500 - - - 4 1 -15 1 - O.B V - V 1 j1A 1 j1A ANALOG SWITCH CHARACTERISTICS Analog Signal Range Full Full Off Output Leakage Current, IO(OFF) (Note 2) +2500 Full On Input Leakage Current, IS(ON) (Note 3) +25°C Full 9-105 - - - +15 35 50 40 75 0.04 1 1 100 0.04 1 1 100 0.03 1 0.5 100 - - - +15 V 35 50 45 75 n n 0.04 5 nA 0.2 100 nA 0.04 5 nA 0.2 100 nA 0.03 5 nA 0.2 100 nA Specifications HI-381 thru HI-390 Electrical Specifications Supplies = +1SV, -1SV; VIN = Logic Input VIN for Logic "1" = 4V, for logic "0"= 0.8V, Unless OtherwIse Specified. (Continued) HI-3XX-2 PARAMETERS I TEST CONDITIONS TEMP (Note 7) +2S"C MIN I TYP HI-3XX-5-9 MAX I I MAX I UNITS MIN TYP - 0.09 O.S rnA - 1 rnA 0.Q1 100 p.A - - p.A 0.01 100 p.A - - p.A 0.01 100 p.A - - p.A POWER SUPPLY CHARACTERISTICS Current,l+ - Full Current, 1- (Note 7) +25"C Full Current, 1+ (Note 8) +2S"C Full Current, 1- (Note 8) +2S"C Full 0.09 O.S - 1 0.01 10 - 100 0.01 10 - 100 0.01 10 - 100 - - NOTES: 1. Vs=t10V,lour= +1OmA. On resistance derived from the voltsge meesured across the switch under the above conditions. 2. Vs=t14V,Vo= +14V. 3. Vs=Vo=t14V. 4. The digltsllnputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. = = = = 7. VIN =4V (one Input) (aU other inputs =OV). 8. VIN =0.8V (all Inputs). = = S. Vs = 1VRMS, f= sookHz, CL 15pF, RL 11(, CL CFllCTURE + CPROSE "off Isolation" 20t.0v Vs/Vo. 6. Vs OV, CL 10,ooOpF, logic Drive = SV pulse. Switches are symmebical; S and D may be Interchanged. Typical Performance Curves eo 80 V+ ,,+15V, V- .-15V 80 80 g i'... 1 r--...: :::::::: 40 a: 20 r-- 0 -15 +125"c +25"c -5&"C -' :--....... .....;" -10 I TA·+25"C 1 0 5 DRAIN VOLTAGE M ~~ ~ g J --- 10 40 ""'- r--- ---""'- ./ ~~ B A 20 A V+.+15V, V. .. -15V B V+.+10V, V-.-10V C V+_+7.5V,V..-7.5V o DV+.+5V,V-.1V -15 -10 -S 0 5 DRAIN VOLTAGE M 1& F~URE1. ~~VIVoANDTEMPERATURE ./ --- ~ 10 1& FIGURE 2.. RDS(~ VI Vo AND POWER SUPPLY VOLTAGE 9-106 HI-381 thru HI-390 Typical Performance Curves (Continued) 100 100 V+_+15V, v...-15V TA" +250 C, Va • 15V, RL" 2K 80 1 / iii ~ z 60 ~ II! 40 Q HI-381 THRU HI-390......... / ~ V+ _ +15V, V-. -15V CLOAD.30pF, Vs .1VRMS ~~ ~.100n "~ RL.1~ ~ IL IL 0 20 0.1 107 10' FREQUENCY (Hz) 1 10 100 1K 10K 100K 1M LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 4. OFF ISOLATION va FREQUENCY FIGURE 3. DEVICE POWER DISSIPATION va SWITCHING FREQUENCY (SINGLE LOGIC INPUT) 10.0 ~ 10.0 V+ .. +15V, v.. _-15V F V+. +1SV, V-" -1SV ~ IVol.IVsl-14V I- C .sIF 1.0 1.0 l JII: Ii: "- J j ./ 0 ./ 0.1 0.01 25 . / i""" 0.1 0.01 25 75 125 TEMPERATURE ~) - 75 125 TEMPERATURE ~) FIGURE 5. is(oFF) OR ID(OFF) va TEMPERATURE' FIGURE 6. ""ON) vs TEMPERATURE' * The nelleakage inlo the source or drain is the n-channel leakage minus lhe p-channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greaUy from unillo unit. 70 16 60 12 40 .2: 8 30 4 Ii:" Ii:" .2: j TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) HI-381 THRU HI-390 .-I'-. ;f 20~ o __ ~ 2 __L -__L -__L -__L -__L -__ ~ 4 6 8 10 DRAIN VOLTAGE M 12 14 - . . , . .I __ ~ o 16 FIGURE 7. OUTPUT ON CAPACITANCE va DRAIN VOLTAGE 2 4 8 8 10 INPUT VOLTAGE M 12 14 18 FIGURE 8. DIGITAL INPUT CAPACITANCE V8 INPUT VOLTAGE 9-107 HI-381thru HI-390 TypIcal Performance Curves (Continued) +1SV • V+ HI-384 THRU Il1-38O H1-381 INVERTED LOGIC £4 5 Q, ii!E I - 2 0 r- ~ LOGIC INPUT y. o -15V D.4 0.. TIME ()1a) 1.2 1.8 98. VIN LOGIC VI nME 9A. TEST CIRCUIT E £w ! ~ +10 +5 ,.-- 0 I d: VGCN.10V I ~r-.. l I I SEENOTE - ...... ~ 100. - =1' ~E ~ o 0.4 o.s 1.' 1.2 TIME ()1a) - ~8 OA 1.' 1.2 1.' -A T J. '"""- ,-VGEN--SV 'j ~~ =E 0.8 TlME{)1a) 9E. VOUT va nME 1.2 TIME ()1a) 90. VOUT V8 nME .i ..... OA =~ ~~ o _VQEH_OV o '~~ _.VQEH_5V 9C. VOUT VI TIME .... ,;1; r-. .J 1.' 1.2 o 0.4 I ~8 TIME ()1a) 9F. VOUT va TIME ~E ,; .A '\' \ ~E VQEH_-10V 'j o ~~ ~~ OA I =1' :~ 0.' TIME ()1a) 1.2 90. VOUTVI TIME NOrE: If RaEN, 1\ or CL Is Increased, there will be proportional Increases In rise and/or fall RC times. FIGURE 9. TYPICAL DELAY, RISE, FALL, SETTLING TIMES AND SWITCHING TRANSIENTS 9-108 HI-381 thru HI-390 Typical Performance Curves (Continued) . I 300 v+. +15V, V·. ·1SV VINH =4.0Y, VINL =OV --- :;:200 It .9 z .9 100 tON ~ ~ -- -- -~ IoN 200 toFF V+ .. +1SV, TAa+250C VNI. +4V, VINL - OV - I j toFF 300 j 100 o -ss -35 ·15 5 25 45 55 TEMPERATURE ("C) 85 105 o 125 FIGURE 1O. SWITCHING TIME VI TEMPERATURE, H1-381 THRU HI·390 .. ~ Yo ...1SV, TA =+2SOC _ VINH a 4.0Y, YINL a OV !II ~ I:: S 0.8 Z .9 O.S \. -~ ~ 0.4 toFF0.2 o o V•••15V,TA_ ai-----+-----+-------f I:~--------;---------~----------~ \ .5 1.0 7....------r----..,.--------, ~&~----~------+-----~ 1A 1.2 1S FIGURE 11. SWITCHING TIME VI NEGATIVE SUPPLY VOLTAGE, HI-381 THRU HI-390 1.8 1.S 5 10 NEGATIVE SUPPLY M I'~------­ toN ~- 5 10 POSITIVE SUPPLY VOLTAGE (V) i 15 0 0~--------~&----------1~0----------~15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 12. SWITCHING TIME VI POSITIVE SUPPLY VOLTAGE, H1-381 THRU H1-390 FIGURE 13. INPUT SWITCHING THRESHOLDvs POSITIVE SUP· PLY VOLTAGE, HI-381 THRU HI-390 9·109 HI-S040 thru HI-SOS1 HI-S046A and HI-S047A CMOS Analog Switches December 1993 Features Description • ±15V Wide Analog Signal Range This family of CMOS analog switches offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 80mA. "ON" resistance is low and stays reasonably constant over the full range of operating signal voltage and current. RON remains exceptionally constant for input voltages between +5V and -5V and currents up to 5OmA. Switch impedance also changes very little over temperature. particularly between OOC and +750 C. RoN is nominally 250 for HI-5048 through HI-5051 and HI-5046A and HI-5047A and 500 for HI-5040 through HI-5047. • Low "ON" Resistance 250 (Typical) • High Current Capability 80mA (Typical) • Break-Before-Make Switching - Tum-On TIme 370ns (Typical) - Tum-Off TIme 280ns (Typical) • No Latch-Up • Input MOS Gates are Protected from Electrostatic Discharge • DTL. TTL, CMOS. PMOS Compatible Applications • High Frequency Switching • Sample and Hold There are 14 devices in this switch series which are differentiated by type of switch action and value of RON (see Functional Description). All devices are available in 16 lead DIP packages. The HI-5040 and HI-5050 switches can directly replace IH-5040 series devices except IH5048. and are functionally compatible with the 00180 and DG190 family. Each switch type is available in the -55°C to +1250 C and OOC to +750 C performance grades. • Digital Filters • Operational Amplifier Gain Switching Functional Block Diagram Functional Description PART NUMBER TYPE All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input and output leakage currents (0.8nA at +250 C). This family of switches also features very low power operation (1.5mW at +25°C). TYPICAL DIAGRAM RON HI-5040 SPST 500 HI-5041 OualSPST 500 HI-5042 SPOT 500 HI-5043 OualSPOT 500 HI·5044 OPST 500 HI·5045 OualOPST 500 HI·5046 OPOT 500 HI·5046A OPOT 250 HI-5047 4PST 500 HI·5047A 4PST 250 HI·5048 OualSPST 250 HI-5049 OualOPST 250 HI·5050 SPOT 250 HI·5051 OualSPOT 250 r II N II A T -t> CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 9-110 s ~~ D File Number 3127 HI-5040 Series Ordering Information PART NUMBER TEMPERATURE RANGE HI1-5040-7 OOC to+7SoC + 96 Hr. Burn-In 16 Lead Ceramic DIP HI3-5040-S OOC to+75"C -SSoC to +12SoC 16 Lead Plastic DIP HI1-504Q-2 PART NUMBER PACKAGE Hll-5048-S HI1-5048-7 TEMPERATURE RANGE OOC to+7SOC OOC to+7SOC + 96 Hr. Burn-In PACKAGE 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP HI3-5048-S OOC to+7SOC 16 Lead Ceramic DIP HI1-5048-2 -SSoC to +12SOC 16 Lead Ceramic DIP HI3-5041-S OOC to+7SOC OOC to+7SoC 16 Lead Plastic DIP Hll-5049-S DOC to+7SOC 16 Lead Ceramic DIP HI1-5041-S OOC to+7SoC 16 Lead Ceramic DIP HI1-5049-2 -SSoC to + 12SOC 16 Lead Ceramic DIP HI1-5041-2 -55"C to +12SoC 16 Lead Ceramic DIP HI3-5049-S DOC to +7SOC HI1-5041-7 16 Lead Ceramic DIP HI1-5049-7 DOC to+7SOC + 96 Hr. Burn-In 16 Lead Ceramic DIP HI3-5042-S oOC to +7SoC + 96 Hr. Burn-In OOC to+7SoC 16 Lead Plastic DIP OOC to+7SoC 16 Lead Ceramic DIP Hll-50SQ-S HI1-50SQ-2 DOC to+7SOC -SSoC to +12SoC 16 Lead Ceramic DIP HI1-5042-S HI 1-5042-7 OOC to+7SoC + 96 Hr. Burn-In -SSoC to +12SoC DOC to +7SoC + 96 Hr. Burn-In -SSoC to +12SoC 16 Lead Ceramic DIP HI3-SDSQ-S HI1-505Q-7 DOC to+7SoC DOC to +7SoC + 96 Hr. Burn-In DOC to+7SoC 16 Lead Plastic DIP HI3-5043-S DOC to+7SoC HI1-5043-S OOC to+7SoC Hll-S044-7 Hll-504Q-S HI 1-5042-2 HI1-5043-7 HI1-5043-2 Hll-5044-S HI3-5044-S HI1-5044-2 Hll-5045-S HI1-5045-7 Hll-SD45-2 HI3-5045-S 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Ceramic DIP HI1-50S1-S -SSoC to +12SoC 16 Lead Ceramic DIP 16 Lead Ceramic DIP HI1-50S1-2 HI1-50S1-7 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP DOC to +7SOC + 96 Hr. Burn-In HI4PSDS1-S DOC to+7SOC 20 Lead PLCC DOC to+7SoC + 96 Hr. Burn-In 16 Lead Ceramic DIP HI3-50S1-5 DOC to+75°C 16 Lead Plastic DIP DOC to+7SoC DOC to+7SoC 16 Lead Ceramic DIP HI1-50401883 -55°C to +125°C 16 Lead Ceramic DIP HI1-5041/883 HI1-50421883 -55°C to +125OC -55°C to +125OC 16 Lead Ceramic DIP 16 Lead Ceramic DIP -SSoC to +12SoC 16 Lead Plastic DIP 16 Lead Ceramic DIP HI1-5043I883 -55°C to +125°C 16 Lead Ceramic DIP OOC to+7SoC 16 Lead Ceramic DIP HI1-5044I883 DOC to +7SoC + 96 Hr. Bum-In -SSoC to +12SoC 16 Lead Ceramic DIP HI1-5045I883 -55°C to +125°C -55°C to +125OC 16 Lead Ceramic DIP HI1-5046I883 -55°C to +125°C 16 Lead Ceramic DIP H11-5046AI883 -55°C to +125OC 16 Lead Ceramic DIP HI1-5047/883 -55°C to +125OC 16 Lead Ceramic DIP HI1-5047A1883 HI1-5048I883 -55°C to +125°C 16 Lead Ceramic DIP -55°C to +125OC 16 Lead Ceramic DIP HI1-50491883 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP HI1-5046-2 OOCto+7SOC -SSoC to +12SoC Hll-5046-S DOC to+7SoC 16 Lead Ceramic DIP HI1-5046-7 OOCto+7SoC + 96 Hr. Burn-In 16 Lead Ceramic DIP HI3-5046-S 16 Lead Plastic DIP HI1-505OI883 HI1-5046A-7 DOC to +7SOC DOC to+7SoC + 96 Hr. Burn-In -S5°C to +1250C -55°C to +1250C 16 Lead Ceramic DIP HI1-5051/883 -55°C to +1250C 16 Lead Ceramic DIP HI4-50431883 -S50C to +1250C 2D Lead CLCC HI3-5046A-S DOC to+7SoC 16 Lead Plastic DIP HI4-5045I883 -55°C to +125°C 16 Lead Ceramic DIP HI1-5046A-2 -SSoC to +12SoC 16 Lead Ceramic DIP HI4-5051/883 -S5°C to +12SOC 16 Lead Ceramic DIP Hll-5046A-S OOC to +7SoC OoC to+7SoC 16 Lead Ceramic DIP H19P5043-5 OOC to+7SOC 16 SOIC (N) 16 Lead Ceramic DIP HI9P5045-5 DOC to+75OC 16S0IC(N) OOC to+7SoC + 96 Hr. Burn-In 16 Lead Ceramic DIP H19P5049-5 OOC to+75OC 16S0lC (N) H19PSD51-5 16S0IC(N) HI1-5047-2 -SSoC to +12SoC 16 Lead Ceramic DIP H19P5043-9 HI3-5047-S 16 Lead Plastic DIP HI9PS045-9 HI1-5047A-S OOCto +7SOC OOCto+7SoC OOCto +75OC -400c to +8SoC -4OOC to +85OC 16 Lead Ceramic DIP HI9P5049-9 -4OOC to +B5°C 16S0IC(N) HI1-5047A-2 -SSoC to +12SoC 16 Lead Ceramic DIP H19PSD51-9 -4OOC to +85OC 16S0IC(N) HI3-5047A-S OOC to +7SoC HI1-5047A-7 OOC to+7SoC + 96 Hr. Burn-In HI1-5047-S HI 1-5047-7 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP 9-111 16 Lead Ceramic DIP 16S0IC(N) 16S0IC(N) HI-5040 Series Pin Configurations SWitch States are Logic ocr Input SINGLE CONTROL SPST HI-5040 (500) SPOT HI-S042 (SOO), HI-5050 (250) OPST HI-5044 (SOO) U t-~__--i1II11St A y. VA VL OPOT H1-5046 (500), HI-5046A (250) 4PST HI-5047 (500), HI-5047A (250) ro---f!~S2 A V· VA VL DUAL CONTROL OUALSPST H1-5041 (500) OUALSPDT H1-5043 (500), HI-5051 (250) DUALSPST H1-5048 (250) DUALSPDT HI-S043 (500), HI·5051 (250) ~ Q ~ 0 NOTE: Unused pins may be internally connected. Ground all unused pins. 9·112 C OUALOPST HI-5045 (500), HI-S049 (250) HI-5040 Series Switch Functions Switch States are Logic "1" Input SPST HI-5040 (500) VL 12 S SPDT HI·5042 (500) DUALSPST HI-5041 (500) V+ VL 12 11 16 D SI V+ VL 16 Dl I . SI I AI At A 15 S2 I II Y. I VR DUALSPDT HI-5043 (500) VL 12 SI S3 AI At Sz S4 VL 12 11 16 3 Dl 0, SI Sz 10 8 6 9 5 13 VR D:! A Dl 4 3 D:! 15 D:! 14 Y. VR V· DUAL DPST HI·5045 (500) V+ VL V+ 11 16 Dl 4 3 ~ SI S3 AI 3 At Sz A D4 8 6 S4 Dl 0, D:! D4 14 V· VR DPOT H1-5046 (500). HI-5046A (250) VL 8 16 DPST HI·5044 (500) V+ 4 Sz ~ 13 VR V+ 11 Y. VR 4PST HI-5047 (500). HI-5047A (250) V+ VL V· DUALSPST HI·5048 (250) V+ VL U) W SI Dl SI Sz D:! Sz Sa 0, Sa D4 S4 A S4 A 3 8 6 Dl SI VR DUALDPST HI·5049 (250) 0, AI D4 At SI S3 AI VL 12 3 Dl 0, SI Sz At Sz 8 6 S4 VR Y. 5 V· ~ VL 12 16 Dl 3 SI D:! 9·113 V+ 11 16 4 3 Dl 0, AI S4 V· D:! V· Sa 15 At Sz D4 Dl DUALSPDT HI·5051 (250) 11 A 15 6 VR V+ 4 :J: g ~ SPOT HI-5050 (250) V+ 3 D:! Sz VR 4 10 II ~ 5 D4 VR y. Specifications HI-5040 Series Absolute Maximum Ratings Thermal Information Supply Voltage (V+. V-) ............................... 36V VR to Ground •••••••••••••••.••••••••••••••••••••• V+. VDigital and Analog Input Voltage ••••• +VSUPPLY +4V. -VSUpPLy -4V Analog Current (S to D) Continuous ••••••••••••••••••••• 30mA Analog Current (S to Dl Peak ••••••••••.••••.•••••••••. 80mA Storage Temperature .' •••••••••••••••••••••• -65"C to +1SOOC Lead Temperature (Soldering 10s) •••••••••••••••••••• +3OO0 C Thermal Resistance 9JA Ceramic DIP Package ••••••••••••••• 800c/w soic Package ••••••••••.••.••••••• 1200c/w Plastic DIP Package •••••••••••••••• 1000c/w 800c/w PLCC Package •••••••.•••••••••••• ,CLCCPackage •••••••..••••••••.•• 75"CiW 200c/w JunctiOn Temperature Plactic Packages ••••••••••••.••••.•••••••••••••• +1SOoC Ceramic Packages •••••••••••••••••••••••••••••• +175°C Operating Temperature Range HI-SOXX-2 •••••••••••••••••••••••••••••• -55"C to +125"C HI-50XX-5. -7 •••••••••••••••••••••••••••••• OOC to +750 C HI-50XX-9 ••••••••••••••••••••••••••••••• -4OOC to +85°C CAUTION: Stresses above those Hsted In "Absolute MsxJmum RatJnf/S" may caUl/e permanent damage to the device. This Is a stress only ratJng and operation of the device at these or any other conditions above those Indicated In the operatJonsl sectIons of this speclflca/Jon Is not imp/ied. Electrical Specifications = = = = = Supplies +15V. -15V; VR OV; VAH (Logic Level High) 2.4V. VAL (Logic Level Low) +C.8V. VL +5V. Unless Otherwise Specifled. For Test Conditions. Consult Performance Characteristics. Unused Pins are Grounded. OOCTo+75°C -550 C To +125°C TEST CONDITIONS TEMP MIN TVP MAX MIN ioN. Switch On Time (Note 4) +25°C 500 IoFF. Switch Off Time +2SOC 280 500 Charge Injection (Note 2) +25°C - 370 (Note 4) 5 20 "Off Isolation" (Note 3) +25°C 75 80 "Crosstalk" (Note 3) PARAMETER TVP MAX UNITS - 370 500 ns - 280 500 ns - 5 80 - 88 - mV - 11 - pF 11 - pF 22 - pF 5 - pF - 0.5 - pF - 0.8 V - V SWITCHING CHARACTERISTICS +25°C 80 88 - CS(OFF)' Input Switch Capacitance +25°C - 11 - CO(OFF)' Output Switch Capacitance +25OC - 11 - CO(ON)' Output Switch Capacitance +25°C - +25°C - 22 CA' Digital Input Capacitance 5 COS(OFF). Drain-To-Source Capacital)Ce +25OC - 0.5 - dB dB DIGITAL INPUT CHARACTERISTICS VAL. Input Low Threshold Full - - 0.8 - VAH. Input High Threshold Full 2.4 - - 2.4 IA• Input Leakage Current (High or Low) Full - 0.01 1.0 - 0.01 1.0 I1A Full -15 - +15 -15 - +15 V +25°C - 50 75 75 - - ISO +25°C - 25 45 Full - - 50 - 50 Full n n n n - 2 10 1 5 0.8 2 100 200 ANALOG SWITCH CHARACTERISTICS Analog Signal Range RoN. On Resistance RoN. On Resistance (Note 1A) (Note lB) RoN. Channel-to-Channel Match (Note 1A) +25OC RoN. Channel-to-Channel Match (Note lB) +25°C = IS(OFF) ID(OFF)' Off Input or Output Leakage Current +2SOC Full 9-114 - - - - ISO 25 45 - 50 2 10 1 5 n n 0.8 2 nA 100 200 nA Specifications HI-5040 Series Electrical Specifications = Supplies = +lSV, -lSV; VR = OV; VAH (logic Laval High) 2.4V, VAl. (logic Laval Low) = +O.8V, VL = +SV, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins are Grounded. (Continued) PARAMETER TEST CONDmONS -55"C To +l25"C TEMP MIN Full - Po, Quiescent Power Dissipation +25"C - I+,I-,IL,IR +2S·C - ID(ON), On Leakage Current +25"C O"C To +75"C MAX MIN TYP 0.01 2 - 0.Q1 2 nA 2 200 - 2 200 nA 1.S - - 1.S - 0.2 - - 0.3 - 0.3 - - 0.3 - 0.3 TYP MAX UNITS POWER REQUIREMENTS - 1+, +lSV Quiescent Current (Note 4) Full 1-, -lSV Quiescent Current (Note 4) Full IL' +SV Quiescent Current (Note 4) Full - IR' Ground Quiescent Current (Note 4) Full - mW - 0.3 rnA - O.S mA - O.S rnA - - O.S rnA - - O.S rnA NOTES: 1. VOUT =±10V, lOUT = +1rnA A). For HI-5040 thru HI-5047 B). For HI-5048 thru HI-S051, HI-5046A15047A. 2. VIN = OV, CL = 10,ooOpF. 3. RL = lOon, f = 100kHz, VIN = 2.0Vp-p, CL = SpF. 4. VAl. = OV,VAH = SV. Switching Waveforms INPUT ~ OUTPUT ( , I I\.. INPUT -\ If OUTPUT Top: TTL Input (WlDiv.) VAH = SV, VAL = OV Bottom: Output (2V1Div.) Horizontal: 20OnsiDiv. \ J Top: CMOS Input (SVlDiv.) VAH = 10V, VAl. = OV Bottom: Output (5V1Div.) Horizontal: 200nslDiv. FIGURE 1. FIGURE 2. 9-115 HI-5040Series Typical Performance Curves and Test Circuits TA =+25OC, V+",+15V, V-=-15V, VL=+sv. VR=OV, VAH =3.0V and VAL = 0.8\1, Unless Otherwise SpecJlled 1mA U.> Vz RoN- . 1mA -112- IN ±VIN= I I loUT J .I = FIGURE 3. ·ON" RESISTANCE V8 ANALOG SIGNAL LEVEL, SUPPLY VOLTAGE AND TEMPERATURE 80 w S! w 80 V+_+12V V-_-12V u iii w 40 a: ~ P 20 1.2 i~ 1.1 I I ~~ z :! 1/1 u ........ ...... V+=+10V V-.-10V 1"000.. 1-00.. --10 ~e p~ '> -- ~~ ei / ~i -5 0 +5 ANALOG SIGNAL LEVEL (V) +10 1.0 0.8 0.6 +15 FIGURE 4. ·ON" RESISTANCE V8 ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE ~ 0.11 :&~ 0.7 z V+_+15V Yo. -15V I 0 -15 w+ ..... V1N.o!.- ';11" - ~~ " -50 -25 0 +25 +75 +50 TEMPERATURE <"C) +100 FIGURE 5. NORMALIZED ·ON" RESISTANCE vs TEMPERATURE OFF LEAKAGE CURRENT vs TEMPERATURE IS(OFF) ID(OFF) ~~ 100nA ±10V= ... zw 10nA a: a: :::) U w 1nA ~~.I ~ .,..... I latON) 100pA 10P~1"'" ON LEAKAGE CURRENT vs TEMPERATURE OUT I I ~ I <2 50 75 TEMPERATURE <"C) 100 'F10V ~ liN cw ..J = ~ ".. IS(OFF) • ID(OFF) +125 125 FIGURE 6. ON/OFF LEAKAGE CURRENT VB TEMPERATURE 9-116 = -!- 1D(ON) ±10V HI-5040 Series Typical Performance Curves and Test Circuits TA =+25"C, V+ .. +15V, V-=-15V, V L =+5V, VR=OV, VAH = 3.0V and VAL" O.BV, Unless Otherwise Specified (Continued) 1.4 w u ~ 1.3 ~~ 1.2 ~1 wZc "ON" RESISTANCE VII ANALOG CURRENT p~ .L CD: WW !:I:Ii cD: ±VIN 1.1 =;- :!iZ ~ 1.0 20 0 40 60 ANALOG CURRENT (mA) = liN ~ r-ooUTI VIN RoN-I ~ -=- 110 FIGURE 7. NORMALIZED "ON" RESISTANCE VII ANALOG CURRENT -200 iii' IN :!!. -160 ~ S ti" II! ...... II ~~ -80 0 '::'V"" RL_100n -120 0 1"1iI II 1 10 100 ....... I lOUT oY~ RL VIN ) "OFF" ISOLATION - 20 LOG ( VOUT RL=1Okn -40 I IIII I 1K 10K 100K FREQUENCY (Hz) 1M FIGURE 8. "OFF" ISOLATION VII FREQUENCY 200 iii' 160 • :!!. ... ~ I! 1/1 ~ 0 . " ~ 120 1/1 15 . SWITCHED CHANNEL- f'- ... 80 i"~ 40 0 1 10 100 VIN,$ (2V)pp 1K -::!?- i'oo t lon ~ ., 1-0 I"- VIN ) "CROSSTALK".20LOG ( ~ 1-0 10K 100K 1M FREQUENCY (Hz) FIGURE 9. CROSSTALK VB FREQUENCY 9·117 VOUT \t RL -=l=" HI-5040 Series Typical Performance Curves and Test Circuits TA =+25"C. V+=+15V. V-=-15V. VL=+5V. VR=OV. VAH =3.0V = and VAL O.SII, Unless Otherwise Specified (Continued) 200 I - I I _ , 160 120 -10Y - 40 10K / I o-t-::---o~---t-' TOGGLE I 10 I +10Yo-t--.rt----n I AT 50% DUTY J ~ +6Y 100K +15V -15Y 1M TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 10. POWER CONSUMPTION VB FREQUENCY Switching Characteristics ---OUT1 +10Y __--OUT2 eO% 1K FIGURE 11. ON/OFF SWITCH TIME VB LOGIC LEVEL 720 720 660 660 600 600 540 480 420 360 540 '\ ........ '\ 300 ....... 420 ~ ....... !oFF 120 2.4 360 -- 110 60 II 410 ~ 240 I 3.0 3.6 300 240 .... 110 120 4.2 60 4.1 DIGITAL "HIGH" M FIGURE 12. SWITCHING TIMES FOR POSITIVE DIGITAL TRANSITION v ~ i""" I o 0.5 / / 1/ V !oFF ~ " . I 1.0 1.5 DIGITAL "LOW" M FIGURE 13. SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSITION 9-118 HI·5040 Series Switching Characteristics (Continued) ----ip----- v+ r-----....----...... VL ~----~--------~----~ ~i R6 l! ~i li li R4 P13 li RS v+ VR QP7 l! QN2 li R7 QP2 N16 H---'1r-- V- ' - - - - - - - to VL FIGURE 14. TTLICMOS REFERENCE CIRCUIT (Note 1) NOTE: 1. Connect V+ to VL for minimizing power consumption when driving from CMOS circuits. 9-119 HI·5040 Series Switching Characteristics (Continued) A, (AV >----_----......-..., IN A, (AV OUT >-----+---.....1 FIGURE 15. SWITCH CELL v+ R4 tl~;:t:=t=t=+==I==t:::t:: A1 A1 +----~~1_---1_--+-+_--+-+ 2000 A2 . -....- - t - t + A2 V- NOTES: 1. AU n-channel bodies to V-, all p-channel bodies to V+ except es shown. 2. For further information refer to Application Notes 520,521,531,532 and 557. FIGURE 16. DIGITAL INPUT BUFFER AND LEVEL SHIFTER 9-120 IH5043 Dual SPOT CMOS Analog Switch December 1993 Features Description • See HI504X and IH514X for Other Functions The IH5043 analog switch uses an improved, high voltage CMOS monolithic technology. These devices provide ease of use and performance advantages not previously available from solid state switches. • Dual SPOT • Switches Greater than 20Vpp Signals with ±15V Supplies • Quiescent Current Less than 1mA • Break·Before·Make Switching tOFF 200ns, tON 300ns Typical • TTL, DTL, CMOS, PMOS Compatible Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE IHS043MJE -ssoC 10 +12SoC 16 Lead Ceramic DIP IHS043CJE oOC to+70OC 16 Lead Ceramic DIP IHS043CPE OOC to +700C 16 Lead Plastic DIP IHS043CY OOC 10+70oC 16 Lead SOIC (W) IHS043MJE/883B -Ssoc 10 +12SoC Pinout Key performance advantage is TTL compatibility and ultra low power operation. The quiescent current requirement is less than 1mA. Also, the IH5043 guarantees Break-BeforeMake switching, accomplished by extending the !oN time (300ns Typ.), so that it exceeds !oFF time (20Ons Typ.). This insures that an ON channel will be turned OFF before an OFF channel can turn ON. The need for external logic required to avoid channel to channel shorting during switching is eliminated. The IH5043 is a pin·for·pin, improved performance replacement for other analog switches. 16 Lead Ceramic DIP Functional Block Diagram FUNCTIONAL DRIVER, TYPICAL DRIVER, GATE ('/2 AS SHOWN) IH5043 (CDIP, PDIP, SOIC) TOP VIEW y+ 01 IN 03 yCAUTION: Those devices are sensitive to electrostatic discharge. Users should foRow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 9-121 File Number 3130 Specifications IH5043 Absolute Maximum Ratings Thermal Information V+toV-•.••••••••••••••••••••••••••••••••••••••••• <36V V+ to Vo .•••••••••••••••••••••••.••••••••••••••••• <3OV Voto v- •.•••.••••••••••••••••••••••••••••••••••••• <30V Vo to Vs .•••••••••••••••••••••••••••••••••••••••• <±22V VLtov- •.••••••••••••••••••••••••••••••••••••••••• <33V v L to V1N .••••••••••••••••••••••••••••••.•••••••••• <3OV v L to GND •••.••••••••••••••••••••••••••••••••••••• <20V V1N to GNO •••••••••••••••••••••••••••••••••••••••• <20V Continuous Current (S-O) ••••••••••••••••••••••••••••• 30mA Peak Current (S-O) •••••••••••••••••••••••••••••••••• 70mA (Pulsed at 1ms, 10% duty cycle Max) Storage Temperature •••••••••••.•.••••••••• -65"C to +15O"C Lead Temperature (Soldering 1Os) •...••.•••..•••.•.•. +3O(JOC Thermal ResIstance 9JA Ceramic DIP Package ••••••••••••••• BO"CNI Plastic DIP Package •••••••••••••••• 1000c1W SOIC Package ••••••••••••••••••••• 1000c1W Operating Temperature M Suffix •••••••••••••••••••••••••••••••• -55"C to +125°C C Suffix •••••••••••••••••••••••••••••••••• OOC to +700 C Junction Temperature Plastic Packages ••••••••••••••••••••••••••••••• +15O"C Ceramic Package •••.•••.••••••.•••••••••••••••• +1750 C CAUTION: StrssSflS abo.... those listsd In 'Abso/uts Mexlmum Ratings' msy cause permanent damsge to the cIevIcs. This is a stress only rating and operation of the device al these or any other conditions abo.... those Indicalad in the operational sections of this speclficallon is notI""Had. Electrical Specifications +25"C, V+ = +15V, v- = -15V, VL = +5V COMMERCIAL MILITARY PER CHANNEL PARAMETERS TEST CONDITIONS -55"C +25°C +125°C OOC +25"C +70oC UNIT Input logic Current, IIN(ON) VIN=2.4V ±1 ±1 10 ±1 ±1 10 jIA Input Logic Current, IIN(OFF) V1N=0.BV ±1 ±1 10 ±1 ±1 10 jIA Drain Source On Resistance, ROS(ON) Is = 10mA, VANALOG = -10V 75 75 150 80 80 130 0 to +10V - 25 (Typ) - - 30 (Typ) - 0 - ±10 (Typ) - V ±5 100 nA Channel to Channel ROS(ON) Match, IIRos(ON) Switch OFF Leakage Current, ID(OFFY'IS(OFF) VANALOG = -10V to +10V - ±1 100 - Switch On Leakage Current, IO(ON)+IS(ON) Vo = Vs= -10V to +10V - ±2 200 - ±10 100 nA Switch "ON" Time, ioN RL = 1kO, VANALOG=-10Vto +10V, see Figure 7 - ns RL = 1kO, VANALOG " -10Vto +10V, see Figure 7 - 1000 Switch "OFP Time, IoFF - 500 - ns 20 (Typ) - mV 50 (Typ) - dB - Minimum Analog Signal Handling Capability, VANALOG Charge Injection, Q(INJ) See Figure B Minimum Off Isoiation Rejection Ratio,OIRR 1= 1MHz, RL = 1000, CL :S 5pF, See Figure 4 - ±11 (Typ) 1000 500 15 (Typ) - 54 (Typ) - - V+ Power Supply Quiescent Current, 1+0 ±1 ±1 10 10 10 100 jIA V- Power Supply Quiescent Current, V+ = +15V, v- = -15V, I-a VL=+5V ±1 ±1 10 10 10 100 jIA +5V Supply Quiescent Current, I-La ±1 ±1 10 10 10 100 jIA Ground Supply Quiescent Current, IGNO ±1 1 10 10 10 100 jIA - 54 (Typ) - - 50 (Typ) - dB Minimum Channel to Channel CrosS One Channel Off; Any Other Coupling Rejection Ratio, CCRR Channel Swttches as per Figure 3 NOTE: 1. "TYPical values are lor design aid only, not guaranteed and not subject to production testing. 9-122 IH5043 Typical Performance Curves (Per Channel) 1&Or_----------,---_r--_r---,--~r_~ 100r_----------~--_r--~~~r_--~~ Is·1mA AT ±15V SUPPUES Is·1mA 140 AT ±15V SUPPUES +---+---t---t--~t---t 80~--~--+---+---+---4---4---~--~ 120t-~r_~r_--t---+---r---+---+_~~ 9: 100 60 9: +aoc !!: a: !!: -550 C - I +12V 80 a: 40 ~--- +10V +1250 C +15V 60 40 20 20 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 -10.0 10.0 -7.5 ...... ....... 100 iii" :!. iii ~ a: -2.5 0 2.5 5.0 200mVpp CCRR .. 20LOG VOUT (mVpp) i"- ..... i"""'- ....... 80 ~ ....... ....... 60 I"-.... e. -§- 40 201--+-+-+--+--11--+-+-+--+-1--+-1 °1~~~10~~-1~00--~-1~K~~-10~K--L-1-0~OK--~1M FREQUENCY (Hz) FIGURE 3. -120 -100 iii" -80 :!. If !2. -§- I........... OIRR.20LOG r--... ~ ....... ........ ..... -60 7.5 FIGURE 2. RDS(ONI v& POWER SUPPLY VOLTAGE FIGURE 1. RDS(oN) vs VANALOG 120 -5.0 VANALOG(V) VANALOG (V) 2000mVpp VOUT(mVpp) - AT1MC""' 2 V P P I T !51(1 OFF STATE --0--[::>..... -=·~VOUT l100Q -40 -20 °1~-L~10~-L-1~070~~1~K~~~1~OK~~~1~00~K~~1M FREQUENCY (Hz) FIGURE 4. 9-123 10.0 IH5043 Typical Performance Curves (Per Channel) (Continued) 3V,......, LOGIC IN ,......, OV ..... ~~ -j~1rl- r ~ .. I 10"r--r--'-~---r-'---r--r--T--~~ /V t ~~~---+--~--+-~r--t---r--, I ~ ~ 1" I-+ __+--+__+-+__-+-~~V __+--+~ ~ I J J H~~r--t---+---r--~--+---t-~ V/ !. 6 .I-~---+--~--+-~~~---r--~ J~~+-~~-+~--r-+-~ 10~-+--;--+~~~-;--+--1--+--+-~ vv/' 1:c:~t;~~~E::3:::J~~:::l:=:J ·10.0 -6.0 -2.5 0 2.5 5.0 7.5 10.0 °1~-Y~1~0--~-1~"~~~1K~~~10~K~~1~"K .7.& LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) VAIW.OGM FIGURE 5. POWER SUPPLY QUIESCENT CURRENTVlI LOGIC FREQUENCY RATE FIGURE 6. CHARGE INJECTION vs VANALOG (SEE FIGURE 8) Test Circuits ANALOG INPUT ANALOG INPUT l LOGIC~h 3V 10Y OYJ1.~.... INPUT ovJ1. ~·..l J -=- LOGIC~·L YOUT 10pF Il 3Y 1 - INPUT J -=-1kn 10,OHPF FIGURE 7. FIGURE&. 114 Yo QND Switch states shown are for logic "1" input. FIGURE 9. SWITCHING STATE DIAGRAM 9-124 VOUT IH5043 Typical Applications +15V • 1• 1& r;:==:;:::~W-r~--, 51Q 14 -15V -15V 10,OOOpF -!-POLYSTYRENE LOGIC INPUT • II +3V .. > SAMPLE MODE OV .. > HOLD MODE IHS043 FIGURE 10. IMPROVED SAMPLE AND HOLD 1. +VANALOG .n. 15 14 tiL LOGIC STROBE -1&V 13 EXAMPLE: If -VANALOG = =-10Voc and 12 +VANALOG +10Voc then Ladder Legs are switched between t10Voc. depending upon state of Logic Strobe. 11 +5V U) - W :c CJ .n. +15V 10 • 2R R R ETC., ...-¥,ftr-........J!I.'I HOLD MODE FIGURE 11. USING THE CMOS SWITCH TO DRIVE AN Rl2R LADDER NETWORK (2 LEGS) 9-125 j U) IH5043 Typical Applications (Continued) l00kn SIGNAL INPUT --'IIo.Ir-_--I LOPASS OUTPUT Constant gain, constant Q, Variable frequency fiHer which provides simultaneous Lowpass, Bandpass, and Highpass outputs. With the component values shown, center frequency will be 235Hz and 23.5Hz for high and low logic Inputs respectively, Q = 100, and Gain" 100. 1 fN Center Frequency 211: RC = = OV:.rt. LOGIC STROBE FIGURE 12. DIGITALLY TUNED LOW POWER ACTIVE FILTER r'#"#"""""'~ +1SY ~ ; ~ ~ ~ ~ J1.. i i r2L LOGIC , GATE I Rexr 10kn~ (lkQTO 2Okn) IN LOGIC INPUT GND -=- V+ F VL v-J1.. lNSl14 +15V 15V~V+~5V OV~V-~·15V V+ ~ ~ 20kQ ~ 15V TTL ~ II""",,,,,,,,,,,"" FIGURE 13. INTERFACING WITH TTL OPEN COLLECTOR LOGIC (TYP EXAMPLE FOR +15V CASE SHOWN) FIGURE 14. INTERFACING WITH CMOS LOGIC +IV J1.. r2L +IV L ~ LOGIC 100 V++1SVOR+Vcc (VI TERMINAL) ' FIGURE 15. TTL LOGIC INTERFACE 9-126 IH5043 Die Characteristics DIE DIMENSIONS: 17781!m x 19051!m METALLIZAT10N: Type: AI Thickness: 10kA ± 1kA GLASSIVATION: Type: PSGlNitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness: 8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout IHS043 S3 Yo U) W l: 0 GND i U) v+ (SUBSTRATE) SCM (,203 B 9·127 IH5052, IH5053 Quad CMOS Analog Switch December 1993 Features DescrIption • SwHches Greater 1lIan 20Vpp Signals wHh ±15V Supplies The IH5052, IH5053 analog switches use an improved, high voltage CMOS technology, which provides performance advantages not previously available from solid state switches. Key performance advantages are TTL compatibility and ultra low-power operation. The quiescent current requirement is less than 101lA. • Quiescent Current Less Than 101lA • Break-Befora-Make SwHchlng toR: = soons, toN = l000ns Typical • TTL, CMOS Compatible • IH5052 4 Normally Closed Switches • IH5053 4 Normally Open SWitches • Low ROS(ON) son Typical Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE IHS052CDE -O"C to +70"C 16 lead Ceramic DIP IHS052MDE -SSoC to +12SoC 16 Lead Ceramic DIP IHS053CDE -O"C to +70 C 16 Lead Ceramic DIP IHS053MDE -SSoC to +12SoC 16 Lead Ceramic DIP 0 Pinouts The IH5052, IH5053 also guarantees Break-Before-Make switching. This is accomplished by extending the toN time (1000ns) such that it exceeds IoFF time (500ns). This insures that an ON channel will be turned OFF before an OFF channel can turn ON, and eliminates the need for external logic required to avoid channel to channel shorting during switching. With a logic "rY' (0.8V or less) at its control inputs, the IH5052 switches are closed, while the IH5053 switches are closed with a logic "1" (2.4Vor more) at its control inputs. Functional Diagram IH5052 (CDIP) TOP VIEW (1/4 AS SHOWN) V+ 13 V+ (SUBSTRATE) IN IH5053 (CDIP) TOP VIEW 12 VLlSUBSTRATE) y. Switch slates shown for logic "I" input CAUTION: These d8\lices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright@Harris Corporation 1993 9-128 File Number 3131 Specifications IH5052, 1H5053 Absolute Maximum Ratings Thermal Information v+ to V- •.•.••••..•.•..•.••.••..••.•••.•.•.••.••••• <36V v+ to Vo ••••••.•••••.•..••.••..•.....•••.••••••••• <30V Vo to v- •••.••••••.•.••.••.•..•.••.••.•......••.•.• <30V Vo to Vs .•.•...•...••........••.•••••••..•.•••.•• <±22V v L to v- ....•..•......•.•..•..•.••........•.....•.. <33V v L to VIN .•.•...•..•.•..•.••.•...••.••.•....••..•.. <30V v L to GNO .••..•.•.•.•..••.•....••••.......•.••••.• <20V VIN to GNO ••••••.•.•.•.•..•.•.....•.•.•..•..••••.• <20V Continuous Current (S-O) ......•.....•..•..•.••....••• 30mA Peak Current (S-O) .•...........••..•..••••.••.••.••• 70mA (Pulsed at 1ms, 10% duty cycle Max) Storage Temperature .•.•.•.....••.••••••..• -65"C to +15O"C Lead Temperature (Soldering lOs) •..••.••.•.••.•••••• +3000 C Operating Temperature M Suffix ••••.••.•••••••••••••••••••••••. -55"C to +125°C C Suffix • • • . • • • . • • • • • • • • • • • • • • • • • • • • . • • • •• O"C to +70"C Junction Temperature ••••••••.••.•.•••..•••..•••••• +175°C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the devic6. This is a stress only raUng and operation of the device at these or any other conditions above those indicated in the operational secUons of this spscificaUon is not Implied. Electrical Specifications TA = +250 C, v+ = +15V, v- = -15V, v L = +5V MSUFFIX CSUFFIX -55°C +25°C +125°C OOC + 25°C + 70°C UNITS Input Logic Current, IIN(ON) VIN = 2.4V (lH5053) = 0.8V (IH5052) 10 ±1 10 - ±10 - IlA Input Logic Current, IIN(OFF) VIN = 0.8V (IH5053) = 2.4V (IH5052) 10 ±1 10 - ±10 - I!A Drain Source On Resistance, ROS(ON) Is = 10mA, VANALOG = -10V to +10V 75 75 100 80 80 100 0 Channel to Channel, ROS(ON) Match (Note 1) - 25 (Typ) - - 30 (Typ) - 0 Minimum Analog Signal Handling Capability, VANALOG (Note 1) - ±11 (Typ) - ±10 (Typ) - V Switch OFF Leakage Current, IO(OFF)' lS(oFF) VANALOG = -10V to +lOV - ±1 100 ±5 100 nA Switch On Leakage Current, IO(ON) + IS(ON) Vo = Vs = -10V to +lOV ±2 200 ±10 100 nA SWitch 'ON" Time, ioN RL = 1kCl, VANALOG = -10Vto+10V See Figure 7 - - 500 - - 1000 - ns Switch 'OFP lime, TOFF RL = 1kCl, VANALOG = -lOVto +10V See Figure 7 - 250 - - 500 - ns Charge Injection, Q(INJ) See Figure 8 (Note 1) - 15 (Typ) - 20 (Typ) 1= 1MHz, RL = 1000, CL :s; 5pF See Figure 4 (Note 1) - 54 (Typ) - 50 (Typ) - mV Minimum Off Isolation Rejection RatioOIRR - + Power Supply Quiescent Current, 1+ V+=+15V, V-=-15V, VL = +5V 10 10 100 10 10 100 I!A - Power Supply Quiescent Current, 1- V+ = +15V, V- = -15V, VL = +5V 10 10 100 10 10 100 I!A +5V Supply Quiescent Current, IVL V+ = +15V, V- = -15V, VL = +5V 10 10 100 10 10 100 I!A Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR One Channel Off - 54 (Typ) - - 50 (Typ) - dB PER CHANNEL PARAMETERS TEST CONDITIONS NOTE: 1. Typical values are lor Design Aid only, not guaranteed nor production tested. 9-129 dB IH5052, IH5053 Typical Performance Curves 1"~----------r---r---~--~--~--~ Is .. 1mA AT ±15V SUPPUES 1401---11---11---1---t---t---+---+---, 80r---r---t---t---t---;---;---;---, g +125"C 80 - +2!i"C ! a: I 40 -&S"C 40r---11---11---r---t---t---+---;---, 20r---r---t---t---t---;---;---;---, -~O.O -7.5 -1.0 -2.5 0 2.5 5.0 20r---1I---1I---r---t---t---+---;---, O~~--~--~--~---L---L--~--~ 10.0 7.8 -10.0 -7.6 -6.0 -2.5 I" 100 iii 80 :3a: 80 -::- 40 :!!. U; ~ 2.5 5.0 7.5 FIGURE 2. RDS(oN) va POWER SUPPLY VOLTAGE FIGURE 1. RDS(oN) va VANALOG 120 0 VANALOG(V) VANALOG (V) 2Vpp CCRR .. 20LOG ...... ....... Vour(Vpp) r--... r-.... r--.... ~ 2- ........ 20 0 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 3A. FIGURE 3B. FIGURE 3. CROSS COUPLING REJECTION VB FREQUENCY -120 ~f''''',--r--r-'--'--r--TII--r--Ir-TII-T"""""II -100 r-+~I:-;--+--1 OIRR • 2OLOG I" "..... ~ ! -80 Vour(Vpp) 2Vpp I-+~I-+~--I ~, AT ~_ ~ ~+-~-+-+-+~~~~-+-4-4--~ -::- 12~~: !PSlll -- DEPENDS~ •••• OFF STATE ...........'1-+-1----' -- ONPART~F Vour -40 100n -20 o 1 10 1K 10K 100K 1M FREQUENCY (Hz) FIGURE4A. FIGURE4B. FIGURE 4. OFF ISOLATION VB FREQUENCY 9-130 10.0 IH5052, IH5053 Typical Performance Curves (ContInued) TTLLEVEL~ -j0.1T!4 l 5 ...... ;:) II? T I 1000 100 l§ + a: /' w ~ 10 !i III • .9 • /' /' 10 /' ~ V :/ :/ 40 r-~r-~r-~---i---i---+---+---4 35 ~--~~~~--~---f---f---+---; ; 30 ,g r-~r-~r-~---i---i---+---+--~ u Ur-~---r--;---+-~r--+---r--, J ~r--+--~--+--;---r--+-~r-~ V 15 ~--~~~~---f---f---f---+---; 1: C:~~~~:j:::3:::l~~:::t==:J 100 10K 1K 100K -10.0 -7.5 -5.0 -2.5 LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) 0 2.5 5.0 7.5 FIGURE S. POWER SUPPLY QUIESCENT CURRENT vs LOGIC FREQUENCY RATE FIGURE 6. CHARGE INJECTION V8 VANAlOG (SEE FIGURE 8) CL = 10,OOOpF Test Circuits ANALOG INPUT 3V LOGIC TTL INPUT ANALOG INPUT l ~ h ovJl..~ .... 3V 10V OV VOUT J 10pF 10.0 VANALOG(V) Jl.. L~C Il ·L 1 - --D----[>. . l VOUT INPUT 10,OOOPFJ -=-1kO FIGURE 7. FIGURE 8. 9-131 -=- IHSOS2, IHSOS3 Typical Applications :: .._----------------:: ..11V Aexr •• (1110 1'0 2OIcO) •• IN • r-.~~~~-----i~ • LOGIC •• INPUT ••• •• ••• , - -=-:• !• 1SVTTLGATE ! '...................., ('_ TTL LOGIC INPUT ..J""'L ·· · . · ~: ~ . FIGURE 9. +1SV OPEN COLLECTOR TTL INTERFACE TO Uf50UIlHS053 +1SV IHS052IIH5053 VINI • 2 CHI Vour v_ 1. CH2 V.. 10 CHI V... 7 CH. 100110 +IV 1000 ·1SV +IV FIGURE 10. ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY 9-132 IH5052, IH5053 Typical Applications SEQUENCER ANALOG SWITCH DECODER 128fT BINARY COUNTER) S, VIN' J J.K Q NUX SEQUENCE -t---4 FlLP RATE KFLOPCS RESET ~ D, v. t;p;Hr-HttL~\"""'f-t--q 0. RESET v. 8, D, V".. 0. DUAL J. K FLIP FLOP POSSlBIUnES Tn.·SN5473 CMOS· CD4027 OUT 3 INPUT NAND POSSIBIUnES Tn.. 1'" SN5410 E N A S L E _ - - - - - - -.... CMOS .1'" CD4023 FIGURE 11. 4 • CHANNEL SEQUENCING MUX TRUTH TABLE (IH5052) ENABLE MUX SEQUENCE RATE 0 SEQUENCER OUTPUT 'i' 2' 0 0 1 0 1 SWITCH STATES (. DENOTES OFF) SWI SW2 SW3 SW4 0 · 0 ON · · · 0 1 Pulse 1 0 1 2 Pulses 0 1 · · · · · · 1 3 Pulses 1 1 · 1 4 Pulses 0 0 ON · · · · · ON · · · A Latching DPDT Switch +ISV The latch feature insures positive switching action in response to non-repetitive or erratic commands. The A, and ~ inputs are normally low. A HIGH input to ~ turns 8, and 82 ON. a HIGH to A, turns 8 3 and 84 ON. Desirable for use with limit detectors. peak detectors. or mechanical oontact closures. ON · +IV 12 A, ......-1.._ OUT 1 TRUTH TABLE (lH5052) COMMAND STATE OF SWITCHES AFTER COMMAND ~ A, Sa and S. S, andSz 0 0 Same Same 0 1 On Off 1 0 Off On 1 1 QUAD 2 INPUT NAND GATES Tn.-DM7400 ORDM5400 CMOS - CD4011 ORDM74COO INDETERMINATE FIGURE 12. A LATCHING DPDT 9-133 OUT 2 an HARRIS IKJ SEMICONDUCTOR IH5140 thru IH5145 High-Level CMOS Analog Switch December 1993 Features Description • Super Fast Break-Befora-Make Switching The IH5140 Family of CMOS switches utilizes Harris' latch· free junction isolated processing to build the. fastest switches currently.available. These switches can be toggled at a rate of greater than 1MHz with fast toN times (BOns typical) and faster toFF times (sOns typical), guaranteeing break before make switching. This family of switches combines the speed of the hybrid FET DG180 family with the reliability and low power consumption of a monolithic CMOS construction. • toN 80ns Typ, !OFF SOns Typ (SPST Switches) • Power Supply Currents Less Than 111A • OFF Leakages Lass Than 100pA at +250 C Typical • Non-latching with Supply TUrn-Off • Single Monolithic CMOS Chip • Plug-In Replacements for IH5040 Family and Part of the DG180 Family to Upgrade Speed and Leakage • Greater Than 1MHz Toggle Rate • SwItches Greater Than 2OVp-p Signals with ±15V Supplies • TTL, CMOS Direct Compatibility • Internal Diode In Series with V+ for Fault Protection Very low quiescent power is diSSipated in either the ON or the OFF state of the switch. Maximum power supply current is 101lA (at +25°C) from any supply and typical quiescent currents are in the 10nA which makes these devices ideal for portable equipment and military applications. The IH5140 Family is completely compatible with TIL (5V) logic, TIL open collector logic and CMOS logic. It is pin compatible with Harris'IH5040 family and part ofthe DG1801 DG190 family as shown in the switching state diagrams. Pinouts IH5140 IH5141 (PDIP, CDIP) (PDIP, CDIP) TOP VIEW TOP VIEW IH5142 (PDIP, CDIP) IH5143 (pDIP, CDIP) TOP VIEW TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyrlght@Harrls Corporation 1993 9-134 , File Number 3132 IH5140 Series Pinouts (Continued) IH5144 (PDIP, CDIP) TOP VIEW IH5145 (PDIP, CDIP) TOP VIEW 16 81 I:!~~ 011Q:~1!1 1 16 81 ~ 1iI1N NclI 1iI1N1 Dt, [! i!I V- Cal::! my- ~[! jiJONO 8alI ~ONO ~YL ill Y+ 84~ ~YL 04[! my+ [! !mNC NclL ~IN2 NC [! :!INC Dt [! :!I 82 01 1 NC NCl:! NC [! NC Ordering Information FUNCTION TEMPERATURE RANGE IH5140MJE SPST -55°C to + 125°C 16 Lead Ceramic DIP IH5140CJE SPST O"C to +70"C 16 Lead Ceramic DIP IH5140CPE SPST O"C to +700 C 16 Lead Plastic DIP PART NUMBER IH5141MJE Dual SPST IH5141CJE Dual SPST -55°C to + 125°C O"C to +70"C PACKAGE 16 Lead Ceramic DIP 16 Lead Ceramic DIP IH5141CPE Dual SPST O"c to +70"C IH5142MJE SPDT -5500 to +125°C 16 Lead Ceramic DIP IH5142CJE SPDT O"C to +700 C 16 Lead Ceramic DIP O"C to +70"C 16 Lead Plastic DIP IH5142CPE SPDT IH5143MJE DualSPDT IH5143CJE DualSPDT O"C to IH5143CPE DualSPDT O"C to +700 C -5500 16 Lead Plastic DIP to + 125°C 16 Lead Ceramic DIP +700 C 16 Lead Ceramic DIP 16 Lead Plastic DI P IH5144MJE DPST -55°C to +125°C 16 Lead Ceramic DIP IH5144CJE DPST O"C to +70"C 16 Lead Ceramic DIP IH5144CPE DPST O"C to +700 C 16 Lead Plastic DIP IH5145MJE Dual DPST -55°C to +125°C 16 Lead Ceramic DIP IH5145CJE Dual DPST O"C to +70"C 16 Lead Ceramic DIP IH5145CPE Dual DPST +700 C IH5140MJEl883B SPST IH5141MJEl883B IH5142MJEI883B O"C to 16 Lead Plastic DIP -5500 to +125OC 16 Lead Ceramic DIP Dual SPST -5500 to +125"C 16 Lead Ceramic DIP SPDT -55°C to +125OC 16 Lead Ceramic DIP IH5143MJEl883B DualSPDT -5500 to + 125°C 16 Lead Ceramic DIP IH5144MJEI883B DPST -55°C to +125°C 16 Lead Ceramic DIP IH5145MJEI883B Dual DPST -55°C to + 125°C 16 Lead Ceramic DIP NOTES: 1. For MIL-STD-883 compliant parts, request the 1883 datasheet on the above products. 9-135 IH5140 Series Functional Block Diagram v+ rlL INPUT -WH>-tl<...., TYPICAL DRIVERIGATE ·IH5142 9·136 IH5140 Series Switching State Diagrams V+ V+ 11 11 81 18 8 _+----0'111.......-0 0 ~~===::;';:J.21~ 01 INI IN INa • 14 GNO GNO ¥o ¥o DIP(JE,PE) DIP(JE,PE) SPSTIH5140 DUAL SPST IH5141 VL VL V+ 11 V+ 81 11 16 3 8. 16 81 01 4 3 Sa 01 Os INI Da INa 8 8a 6 84 GNO Da 04 V- t/) GNO W ¥o :J: (.) DIP(JE, PEl DIP (JE,PE) SPDTIH5142 DUAL SPDT IH5143 VL i t/) V+ 11 VL 81 V+ 16 3 8, 11 16 01 Os INI 81 01 4 3 8a INa Da Sa 84 j • 6 14 14 GNO 8 5 GNO V- ¥o DIP (JE, PEl DIP (JE, PEl DPSTIH5144 DUAL DPST 1H5145 9-137 Da 04 Specifications IH5140 Series Thermal Information Absolute Maximum Ratings V+to V-•••••••••••••••••••••••••••••••••••.•••••.• lied. Electrical Specifications +25"C, V+ .. +15V, y.. .. -15V, VL .. +5V MIUTARY PER CHANNEL PARAMETERS I -55°C I +25°C TEST CONDITIONS COMMERCIAL +125°C I O"C +WC I +7O"C I UNITS LOGIC INPUT Input LogIc Current, IJNH VIN .. 2.4V, Note 1 Input Logic Current, IINL VIN = O.8V, Note 1 ±1 10 I - ±10 ±1 10 - ±10 10 jiA 50 50 75 75 75 100 0 - 25 (Typ) - · 30 (Typ) . 0 - V ±1 I ±1 I I I 10 I jiA SWITCH Drain Source On Resistance, RoS(oN) Is=-10mA, VANALOO =-1OVto +10V Channel to Channel Ros(ON) Match, ARDS(ON) . Minimum Analog SIgnel Hancllng Capability, VANALOG - ±0.5 100 - ±5 100 nA ±a.5 100 · ±5 100 nA ±1 200 · ±2 200 nA 54 (Typ) - - 50 (Typ) - dB - - 15 (Typ) - pC ±11 (Typ) SwItch OFF Leakage Current, ID(OFF)+IS(OFF) Vo = +1OV, Vs = -10V Switch On Leakage CUrrent, IO(ON)+IS(oN) Vo = Vs= -10Vto+10V Minimum Channel to Channel Cross Coupling RejecUon Rallo, CCRR One Channel Off; Any Other Channel SwItches, See Performance Characteristics Switch "ON" Time, IoN See swftchlng time specifICations and timing diagrams Switch "OFP Time, toFF See switching time specifications and timing diagrams Charge Injection, a.1NJ) See PeIfcrmance Characteristics Minimum Off Isolation Rejecllon Ratio,OIRR . Vo • -1OV, Vs" +10V f = 1MHz, RL = 1000, CL :!: 5pF, See Performance Characteristics - - 10 (Typ) 54 (Typ) ±10 (Typ) 50 (Typ) . dB SUPPLY + Power Supply Quiescent Current, 1+ V+ = +15V, V- = -15V, VL = +5V. See Performance • Power Supply QuIescent Current, ICharacteristics +5V Supply Quiescent Current, IL 1.0 1.0 10 10 10 100 jiA 1.0 1.0 10 10 10 100 jiA 1.0 1.0 10 10 10 100 jiA Ground Supply Quiescent Current, IGNO 1.0 1.0 10 10 10 100 jiA NOTE: 1. Some channels are tumed on by high (1) logic Inputs and other chenn81s are turned on by low (0) inputs; however O.BV to 2.4V describes the mlnlroom range for swftching properly. Refar to logic diagrams to lind logical value of logic input required to produce ON or OFF state. 2. Typical vslues ars for design aid only, not guaranteed and not subject to production testing. 9-138 Specifications IH5140 Series Switching Time Specifications (IoN,IoFF are Maximum Specifications end ioN -IoFF is Minimum Specillcatlon) PART NUMBER TEST CONDITIONS SPECIFICATIONS IH5140,IH5141 SWitch "OFF" Time, IoFF Break-Before-Make,IoN -IoFF Switch "ON" Time,loN Figure 7 - Figure 8, Note 2 - Switch "OFF" Time, IoFF IH5142,IH5143 Switch "ON" Time, ioN +12SOC 100 - Figure 3, Note 2 Switch "ON" Time, ioN Switch "OFF" Time, IoFF Break-Before-Make,IoN -IoFF Figure 8, Note 2 Switch "ON" Time,loN Switch "OFF" Time, IoFF - 10 - - 200 - - 125 Switch "ON" Time, ioN 175 - 125 Figure 7 Switch "OFF" Time, IoFF - 150 - 5 150 - ns - ns 175 150 5 300 - ns ns ns 150 5 - ns 300 - ns ns ns 5 - 250 - ns 5 - ns 300 - ns 150 - ns ns - 150 - ns - 150 - ns ns 250 - ns - 150 - - 125 ns 250 - 125 - - 200 ns - - 10 - - - 10 - O"C +25°C +70"C UNITS - - 125 - Break-Before-Make,IoN -IoFF - 175 - Break-Before-Make, ioN -IoFF - 125 - Switch "OFF" Time, IoFF 125 200 - Figure 2, Note 2 Switch "ON" Time, ioN 150 - 10 - SWitch "OFF" Time, IoFF - 10 125 Figure 7 Switch "ON" Time, ioN 75 175 - Switch "OFF" Time, IoFF Break-Before-Make,IoN -IoFF IH5144,IH5145 +25°C - Figure 8, Note 2 Switch "ON" Time, ioN COMMERCIAL MILITARY -55OC ns NOTES: 1. Switching times are measured at 90% points. 2. Typical values are for design aid only, not guaranteed and not subject to production testing. Typical Performance Curves 90 80 80 70 80 g 40 30 I 100 \ IH5141 DATA -- r-.r-. ....... i--- - 20 +10 ~ +1250 C ""- - +2SOC I +6 - .......... +4 +2 0 -2 -4 -Ii ANALOG SIGNAL VOLTAGE (V) -8 r-..... .......... .... 20 +10 -10 ~ -..... I --- t15~, P--. +8 +6 +4 V tl0V, +SV SUPPUES 40 30 T~ . .~OC IH5141 DATA ,,~+5V SUPPUE 150 r--5SOC +6 60 1. +2 0 I I I +5V SUPp UES -2 -4 -Ii ANALOG SIGNAL VOLTAGE (V) FIGURE1. RDS(ON)V8TEMPERATUREATt15V,+5VSUPPLIES 9-139 FIGURE 2. RoS(oN) V8 POWER SUPPLIES -8 -10 IH5140 Series Typical Performance Curves (Continued) -120 ......... _-100 ID " :!. ~ " ~ .......... C.1 .... o 100 1K 10K 100K FREQUENCY (Hz) SOCKET ON COPPER GROUND PLANE JIG 10M 3a. 3A. FIGURE 3. "OFF" ISOLATION VI FREQUENCY 2.1 2.1 2.4 2.2 2.0 1.1 c1.l ~k-SUPPLY I! 1.4 -1.2 1.0 0.8 0.6 D.4 0.2 ~ \\ \.\. X\. ~GND '"~ ~ o ~ 8 10V '--_ _- - ' 10 100 - PERIOD OF PULSE REPETITlON RATE (J18) 1000 4a. FIGURE 4. POWER SUPPLY CURRENTS VB LOGIC STROBE RATE \. NC CHANNEL PINS (3, 4) ,V ;' '" ~ "J .......7.......(l' NC ~HANrEL -10 -I 0 +100 "" NS +11 - 18) +10 ANALOG SIGNAL VOLTAGE (V) sa. SA. FIGURE 5. CHARGE INJECTION VI ANALOG SIGNAL 9-140 --l pI-- 1000 IL < O.06mA FROM 1J18 to DC_ ~ I 4A. +10 +3V JU'L- ov \.\. . / ... SUPPLY p_4oona IH5140 Series Typical Performance Curves (Continued) vour COAX (~FF CHANNEL) r--~--. -120 ...... ........... ....... ........ = o 100 1K 10K 100M 1M 10M FREQUENCY (Hz) 6A. 68. FIGURE 6. CHANNEL TO CHANNEL CROSS COUPUNG REJECTION VI FREQUENCY Test Circuits +3V ~ TTL INPUT FIGURE 7. IH5141 toN AND 'oFF (3V DIGITAL INPUT) IoN toFF -..i ;.....--.;1..... , ov! i i 1 +10Y ,Your i +15V ii i ~CINPUT ov! i\ ....j ! -10Y i;vour i---ii-- IoN NOTE: SWITCHING TIMES ARE MEASURED AT 110'11. POINTS FIGURE 8. IH5141 toN AND 'oFF (15V DIGITAL INPUT) 9-141 toFF IH5140 Series Test Circuits (Continued) toN i +1SV OV"""" '1l----' ::.:.J +1SV L- TTL INPUT toFF i+10Vi i JA1t;;' 80%' ! ! i i iVOUTAORB -10V i i i 10% i ~15V! i ... r---t~L I ... INPUT !!..I ! !i 9B. 9A. FIGURE 9. IH5143 toN AND toFF (15V DIGITAL INPUT) +3V 2:!JL IH5143 TTL INPUT FIGURE 10. IH5143 toN AND toFF (3V DIGITAL INPUT) Typical Applications To maximize switching speed on the IH5140 family. TIL open collector logic (15V with a 1kn or less collector resistor) should be used. This configuration will result in (SPST) IoN and IoFF times of SOns and 50ns. for signals between -10V and +1 Ov. The SPOT and OPST switches are approximately 30ns slower in both !oN and !oFF with the same drive configuration. 15V CMOS logic levels can be used (OV to +15V). but propagation delays in the CMOS logic will slow down the switching (typical 50ns -+ 100ns delays). ANALOG When driving the IH5140 Family from either +5V TIL or CMOS logic. switching times run 20ns slower than if they were driven from +15V logic levels. Thus ioN is about 105ns. and IoFF 75ns for SPST switches. and 135ns and 105ns (IoN. IoFF) for SPOT or OPST switches. The low level drive can be made as fast as the high level drive If ±5V strobe levels are used instead of the usual OV -+ +3.0V drive. Pin 13 is taken to -5V Instead of the usual GNO and strobe Input Is taken from +5V to -5V levels as shown in Figure 11. OUT 1 OUT n :!.J L CMOS LEVEL INPUT STROBE ANALOG FIGURE 11. The typical channel of the IH5140 family consists of both P and N-channel MOSFETs. The N-channel MOSFET uses a "Body Puller" FET to drive the body to -15V (±15V supplies) to get good breakdown voltages when the switch is in the off state (see Figure 12). This "Body Puller" FET also allows the N-channel body to electrically float when the switch is in the 9-142 IH5140 Series ANALOG IN .-10V on state producing a fairly constant ROS(ON) with different signal voltages. While this "Body Puller" FET improves switch performance. it can cause a problem when analog input signals are present (negative signals only) and power supplies are off. This fault condition is shown in Figure 13. r /'" = ~'II_ _ _+--J GND WHEN POWER SUPPLIES ARE OFF r--"~"" ANALOG IN " -15V o - -...........J Np N QND WHEN PatlER SUPPUES ARE OFF FIGURE 13. This fault situation can also be eliminated by placing a diode in series with the negative supply line (pin 14) as shown in Figure 14. Now when the power supplies are off and a negative input signal is present this diode is reverse biased and no current can flow. "BODY PULLER" FET ANALOG OUT FIGURE 12. Current will flow from -10V analog voltage through the drain to body junction of 01. then through the drain to body junction of 03 to GND. This means that there Is 10V across two forward-biased silicon diodes and current will go to whatever value the input signal source is capable of supplying. If the analog input signal is derived from the same supplies as the switch this fault condition cannot occur. Turning off the supplies would turn off the analog signal at the same time. lN814 OR EQUIVALENT Iill----.,M-- -15V FIGURE 14. Typical Switching Waveforms (Scale: Vertical =5V1DIV.• Horizontal .. 100nslDIV.) 15A. -55"C 9-143 IH5140 Series Typical Switching Waveforms (Scale: Vertical =5V1DIV., Horizontal =100ns/DIV.) 15C. +1~C FIGURE 15. nL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 12) 16A. -55°C 16C. +12SOC FIGURE 16. nL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 13) ..9-144 (Continued) IH5140 Series Typical Switching Waveforms (Scale: Vertical = SVlDIV., Horizontal = l00ns/DIV.) FIGURE 17. +2S"C TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 14) (Continued) FIGURE 18. +250 C TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 19) Typical Applications +15V >..:6~_... OUTPUT 2 16 6 AN~~~ _+-..:3~ 15 r;==::;::~wrt~--, 14 .15V ·15V 510 10,OOOpF -!-POLYSTYRENE 13 LOGIC INPUT 11 +15V 10 II 8 +3V. > SAMPLE MODE OV => HOLD MODE IH5143 FIGURE 19. IMPROVED SAMPLE AND HOLD USING IH5143 ~_ _ _~~~_________~~__.1~6 +V~MDG .It. 15 14 .15V = 12 +5V EXAMPLE: If ·V~AlOG ·10Voc and +VANAlOG = +10Voc then Ladder Legs are switched between ±10Voc , depending upon state of Logic Strobe. rZLLOGlC STROBE = 11 +15V .It. 10 L..f';';:"'---< rZL LOGIC L....-=-If-______-- HOLD MODE ETC.+-..,.,.,,.,,....-..,.,.,,.,...-..,.,.,,.,...-< ETC. FIGURE 20. USING THE CMOS SWITCH TO DRIVE AN Rl2R LADDER NETWORK (2 LEGS) 9·145 IH5140 Series Typical Applications (COntinued) 100lc0 HI PASS OUTPUT 100kn SIGNAL -.J"J.'/Ir-_-.... + INPUT Constant galn, constant Q, variable frequency filter which provides simultaneous Lowpass, Bandpass, and Highpass outputs. With the component values shown, center frequency will be 235Hz and 23.5Hz for high and low logic inputs respectively, Q =100, and Gain =100. 1 f N = Center Frequency = 211: RC FIGURE 21. DIGITALLY TUNED LOW POWER ACTIVE FILTER 9-146 IH5151 Dual SPOT CMOS Analog Switch December 1993 Features Description • Low ROS(ON) of 25.Q The IH5151 solid state analog switch is designed using an improved, high voltage CMOS technology. • Switches Greater than 2OVI4' Signals with ±15V Supplies • Quiescent Current Less than 100llA • Break-Bafora-Make Switching tOFF 120ns Typ., tON 200ns Typical • TTL, CMOS Compatible • Complete Monolithic Construction • ±5V to ±15V Supply Range Key performance advantages in the IH5151 are TTL compatibility and ultra low power operation. ROS(ON) switch resistance is typically In the 140 to 1ao area, for signals in the -10V to +10V range. Quiescent current is less than lallA. The IH5151 also guarantees Break-Befora-Make switching which is logically accomplished by extending the ioN time (2oons typ.) such that it exceeds IoFF time (12Ons typ.). This insures that an ON channel will be turned OFF before an OFF channel can turn ON. The need for external logic required to avoid channel to channel shorting during switching is thus eliminated. Ordering Information TEMPERATURE RANGE PART NUMBER PACKAGE O"C to +70"C IH5151CPE 16 Lead Plastic DIP IH5151CJE O"C to +7O"C 16 Lead Ceramic DIP IH5151MJE ·55"C to +125°C 16 Lead Ceramic DIP IH5151MJElB83B ·55°C to +12500 16 Lead Ceramic DIP tn W ::x: Pinout ~ Switching State Diagram tn IH5151 (COIP, PDlP) TOP VIEW SWITCH STATE SHOWN FOR LOGIC "I" INPUT. VL v+ 11 SI Sa 16 01 4 3 0, i ooJ liz 9 s. 5 ~ : 6 GNO CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 9·147 8 OJ o. Yo File Number 3133 IH5151 Functional Block Diagram ONE SET OF SWITCHES SHOWN +1SV(V+) s TTL IN --M,.....+-...~;;...., s 9·148 Specifications IH5151 Absolute Maximum Ratings Thermal Information V+ to V-........................................... <36V V+ to Vo .......................................... <3IJV Vo to V- •••••••••••••••••••••••••.••••••••••••••••• <3IJV Vo to Vs ••••.•••••••••••••••••••••••••••••••••••• <±22V vL to v- ........................................... <33V vL to VIN •••••••••••••••••••••••••••••••••••••••••• <3IJV VL ••••••••••••••••••••••••••••••••••••••••••••••• <2.OV VIN ••.••••••••••••••••••••••••••••••••••••••••••• <2.OV Currant (Any Terminal) ............................... 50mA Storaga Temperatura ....................... -65"C to +15O"C Lead Tamperature (Soldering 1Os) •••••••••••••••••••• +300"C Tharmal Reslstanca 9JA Caramlc DIP Package ••.••...••••.•• 77"CIW Plastic DIP Packaga .............. .. 100"C1W Operating Tamperature C Suffix .................................. O"C to +70"C M Suffix •••••••••••••••••••••••••••••••• -55"C to +125"C Junction Tamperatura Caramlc DIP Packaga •••••••••••••••••••••••••••• +175"C PlastIc DIP Packaga ••••••••••••••••••••••••••••• +15O"C CAUTION: SIrfIssfJs allow IhoBB lislBd in "Absa/uIlJ Muimum Ratings" may caUl/e ".,rTlllnent damege to the dtwic8. This Is a strees only "'ling and operation of the device lit these or any other conditions abo1I8 IhoBB IndlcalBd in the op8",/Ionai sacIions of this specification is not jrr¢ed. Electrical Specifications TA = +25"C, V+ = +15V, V- = -15V, VL = +5V MILrrARY PER CHANNEL PARAMETERS I -55"C I +25°C TEST CONDrrtONS COMMERCIAL +125°C I O"C +25°C +7O"C I - I ±1 ±10 ±1 ±10 I UNrrs LOGIC INPUTS Input Logic Currant, IIN(ON) VIN = 2.4V (Nota 1) Input Logic Current, IIN(OFF) VIN = O.BV (Note 1) ±1 I ±1 I ±1 ±10 ±1 ±10 25 50 - 30 - 0 - - 15 (Typ) - 0 - V ±2.0 100 nA ±2.0 100 nA pA I pA SWITCH Drain Sourca On Resistance, ROS(ON) 25 Vo = ±10V,ls = -10mA - Channel to Channel ROS(ON) Match, (Note 2) b.ROS(ON) Minimum Analog Signal Handling Capability, VANALOG (Note 2) Switch OFF Leakaga Currant, ID(OFF)' IS(OFF) VANALOG = -10V to +10V Switch On Leakage Currant, ID(ON)+IS(ON) Vo = Vs = -10V to +10V Charge InJection, Q(INJ) (F"l\Jure 5, Note 2) Minimum Off Isolation RaJection Ratio,OIRR f = 1MHz, ~ = 1000, CL s 5pF (Rgure 3, Note 2) Switch "On" Tlrna, ioN ~ = 1kn, VANALOO = -10V (Note 3) SWitch "Off' Tlrna, IoFF To +10V; (Figure 6, Note 3) - - 10 (Typ) ±14 (Typ) ±1.0 100 ±1.0 100 10 (Typ) - 54 (Typ) - - 500 250 ±14 (Typ) 10 (Typ) - 50 (Typ) - - - mV dB 500 ns 250 ns POWER SUPPLY CHARACTERISTICS + Power Supply Quiescent Current, V+=+15V, V-=-15V, VL=+5V, 1+ VR=O 10 10 100 - Power Supply Quiescent Current, 1- 10 10 100 +5V Supply Quiescent Currant, IL 10 10 100 Ground Supply Quiescent Currant, IGNO 10 10 100 - - 54(Typ) - - Minimum Channal to Channel Cross Coupling Rejection Ratio, CCRR (Figure 2, Note 2) 10 10 10 10 50 (Typ) - pA pA pA pA dB NOTE: 1. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) Inputs; however O.BV to 2.4V describes the minimum range for switching properly. Reier to logic diagrams to find logical value of logic Input required to produce ON or OFF state. 2. Typical values are for design aid only, not guaranteed or production tested. 3. For IH5151 d8llices, channels which are off for logic Input:! 2.4V (Pins 3 and 4, 5 and 6) have slower IoN time, than channels on Pins 1, 16 and B, 9. This Is done so switch will maintain break-before-make action when connected In DT configuration, I.a. Pin 1 connected In Pin 3. 9-149 IH5151 Typical Performance Curves Per Channel '"~-r~~'-~~--'--r~~'-~--r-, .~4--r-+~~~+-4--r-+~r-t-; 80 70~~-+~r-+-+--r-+~~+-~-+-; g 8O~~~~~-+~~~~~~~-+__~~ ~ At---~~-i--+-~-i--t-~-i--+--r~ 1 ~~r-r-~~~~~~~~~~ 30 20 10 :t:5Y SUPPU;!. _ tt-::~;~~;~~~i~~~~r:±:'5VcSU:rP:PuiES:;f~-~t-fj; O~L-~~~~~~I~I~I~L-~ ·12 ·10 .:a .. -4 4 0 2 4 • • RD8(ON) AT ±11V, IY SUPPUES (V) 10 12 FIGURE 1. RD8(ON) va ANALOG INPUT VOLTAGE ...... 120 iii' :l!- i ~ '" :--.... ...... 80 "'" 2000mYp.p CCRR .. 2OLOG Your (mYp.p) i"""- ....... ...... r-.. ........ ..... 80 .,:. 40 20 0 1 10 1K 10K '" FREQUENCY '"K 1M (Hz) FIGURE2A. FIGURE2B. FIGURE 2. CROSS COUPUNG REJECTION va FREQUENCY .'2O~ ·100 iii' ~ 2O"mYp.p YOUT (mYp.p) r--. ....... _ -80 :l!- It' e. .,:. OIRR .. 20LOG AT 2 1MHz Y""' P . P I T !510 -60 OFF STATE 1 -= '000 40 0 -D-(:>..... 1 "i---oYour -40 10 '" 1K 10K FREQUENCY (Hz) '"K 1M FIGURE3A. FIGURE3B. FIGURE 3. OFF ISOLATION va FREQUENCY 9-150 IH5151 Typical Performance Curves Per Channel (Continued) 2000 1 5" ... ...:::» . IIJ 200 ~ + a: w :z: t: !!:!. 20 I- ~ j III 21 / V V V V V V /' V 3V r--I LOGIC IN r--I OV-...I ~ L.... --J0.1TI- • 10 100 1K 10K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) T 100K FIGURE4A. F1GURE4B. FIGURE 4. POWER SUPPLY QUIESCENT CURRENT VB LOGIC FREQUENCY RATE Test Circuits ANALOG INPUT 3V ov.I1. ~ ....l ~ -= LOGIC~·L 1 -VOUT INPUT 10.000PF~ FIGURE 5. CHARGE INJECTION TEST CIRCUIT 10PF J _ FIGURE 6. SWITCHING TIME TEST CIRCUIT 9-151 • I IH5151 Typical Applications 27pF Nulling Out Charge Injection Charge Injection (Oinj. on spec. sheet) is caused by gate to drain, or gate to source capacitance of the output switch MOSFETs. The gates of these MOSFETs typically swing from -15V to +15V as a rapidly-changing pulse; thus this 30Vp_p pulse is coupled through gate caPacitance to output load capacitance, and the output "step· is a voltage divider from this combination. For example: Qinject (V pp) !!! J1.. 1000PFS&Hlrl------. CAPACITOIt.I.._ 2 C C GATE x 30V step. I - - - t -.....-< TTL 10 STROBE len -15V LOAD I.e. C GATE = 1.5pF, C LOAD = 100pF, then FIGURE 8. NO-ADJUST CHARGE INJECTION COMPENSATION CIRCUIT 1.5pF QlnJect(Vpp) = 100pFx30VsteP = 45mV pp Thus if you are using a switch in a Sample & Hold application with CSAMPLE 1000pF, a 45mVp_p "Sample to Hold error step" will occur. = To null this error step out to zero the circuit in Figure 7 can be used. 27pF r-----Ilt-----, 1000pFS&H~ CAPACIlOR.I.. 1 2 3V I---+-""-< -=- 05l.. TTL STROBE POT -15V FIGURE 7. ADJUSTABLE CHARGE INJECIlON COMPENSAnoN CIRCUIT The circuit in Figure 7 nulls out charge injection effects on switch pins 1 and 16; a similar circuit would be required on switch pins and 9. a = = OmVp_p Fault Condition Protection If your system has analog voltage levels which are independent of the ±15V (Power Supplies), and these analog levels can be present when supplies are shut off, you should add fault protection diodes as shown in Figure 9. If the analog input levels are below ±15V. the pn junctions of 013 & 015 are reversed biased. However if the ±15V supplies are shut off and analog levels are still present, the configuration becomes as shown in Figure 10. The need for the. diodes in this circumstance is shown in Figure 11. If ANALOG INPUT is greater than W, then the pn junction of 015 is forward biased and excessive current will be drawn. The addition of IN914 diodes prevents the fault currents from destroying the switch. A similar event would occur if ANALOG INPUT was less than or equal to -W, wherein 013 would become forward biased. The IN914 diodes form a "back to back" diode arrangement with 013 and 015 bodies. &OK Simply adjust the pot until VOUT VANALOG OV. This configuration will produce a typical charge injection of VOUT ±10mVp.p into the 1000pF S & H capacitor shown. pulse, with This structure provides a degree of overvoltage protection when supplies are on normally, and analog input level exceeds supplies. This circuit will switch up to about ±BV ANALOG overvoltages. Beyond this drain(N) to body(P) breakdown VOLTAGE of 013 limits overvoltage protection. If you do not desire to do any adjusting, but wish the least amount of charge injection pOSSible, then the circuit in Figure should be used. . a 9-152 IH5151 FROM DRIVER 1 r---~P~ ~P~_ _~ all N +15 IN814.15V ANALOG INPUT OUTPUT SWITCH PAIR ·16V 1-_~..;;.1N8;.;;.1~4 +15V 013 P N 5 i-N=-=---~ T FROM DRIVER FIGURE 10. SWITCH WITHOUT PROTECTION DIODES FIGURE 9. ADDING DIODES PROTECTS SWITCH ~a15 ~alS P ~--~P~ ~~P_ _~ N OV WHEN +16V SUPPLY SHUTOFF ANALOG INPUT P 1N814 +15V OVERVOLTAGE ANALOG INPUT 1 OV WHEN ·15V IS SHUTOFF ·16V SAY·10V TO+10V P N N N Ta 13 FIGURE 11. FAULT CONDITION WITHOUT PROTECTION DIODES FIGURE 12. FAULT CONDITION WITH PROTECTION DIODES 9-153 IH5151 Die Characteristics DIE DIMENSIONS: 25151UTl x 30741UTl METALLIZATION: Type: AI Thickness: 10kA ± 1kA GLASSIVATlON: Type: PSG Over Nittlde PSG Thickness: 7kA it: 1.4kA Nitride Thickness: akA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout IH5151 PINS PIN 4 s. Sa PIN 3 PINe D. Da PIN 8 PIN 1 ~ Da PINS! Sa PINS IN1 PIN 10 INz 9-154 IH5341,IH5352 Dual SPST, Quad SPST CMOS RFNideo Switches December 1993 Description Features • ROS(ON) < 750 • Switch Attenuation Varies Less Than 3dB From DC to 100MHz • ·OFF" Isolation> 70dB Typical at 10MHz • Cross Coupling Isolation> 60dB at 10MHz • Compatible With TTL, CMOS logic • Wide Operating Power Supply Range • Power Supply Current < 1J.1A The IH5341 (IH5352) is a dual (quad) SPST, CMOS monolithic switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high "OFF" isolation while maintaining good frequency response in the "ON" condition. Construction of remote and portable video equipment with extended battery life is facilitated by the extremely low current requirements. Switching speeds are typically ioN = 150ns and IoFF = 8Ons. "Break-Befora-Make" switching is guaranteed. Switch "ON" resistance is typically 400 - 50n with ±15V power supplies, increasing to typically 175n for ±5V supplies. • "Break-Befora-Make" Switching • Fast Switching (80nsl150ns Typ) Ordering Information Applications PART NUMBER • Video Switch • Communications Equipment IH5341CPD • Disk Drives • Instrumentation • CATV TEMPERATURE RANGE PACKAGE O"C to +70"C 14 Lead Plastic DIP IH5341ITW -2!fC to +85°C 10 Pin T0-100 Can IH5341MTW -5500 to +125°C 10 Pin T0-100 Can IH5341 MTW1883B -5500 to +125°C 10 Pin T0-100 Can IH5352CPE O"C to +70"C 16 Lead Plastic DIP IH5352IJE -25°C to +85°C 16 Lead Ceramic DIP IH5352MJE -5500 to +125°C 16 Lead Ceramic DIP IH5352MJEI883B -55°C to +125°C 16 Lead Ceramic DIP IH5352CBP O"C to +70"C 20 LeadSOIC IH53521BP -25°C to +85°C 20 Lead SOIC Pinouts IH5341 (PDIP) TOP VIEW IH5341 (T0-100 CAN) TOP VIEW IH5352 IH5352 (COIP, POIP) (SOIC) TOP VIEW TOP VIEW GNO IIN4 - ._ _ _ _.1-1 VL CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 9-155 File Number 3134 IH5341,IH5352 Functional Block Diagrams 1H5352 1H5341 81 a '1oa---oOa • Dl --_0 Dz al'o-a • a1-Dz Sao a1-Dz ~M-[>----1 IN1--[>-i It a Ita ~Na-t;>--J IN2--[>-i Switches are open for a logic "0" control Input. and closed for a logic "1" control Input Schematic Diagram (1/2 IH5341. 1/4 1H5352) +15V '--~--+--oO TTL o-M"--t-I~.., 9-156 8 Specifications IH5341, IH5352 Absolute Maximum Ratings Thermal Information V+ to Ground ••••••••••••••••••••••••••••.••••••••• +18V V- 10 Ground •••••.•••••••.••..•••.•••.••.••••••••••• -18V VL to Ground ••••••••••••••••••••••••••••••••••••• V+ to VLogic Control Voltage •••.•••.••••••••••••.••••••••• V+ to VAnalog Input Voltage ••••••••••.••••••••••••..••••• V+ to VCurrent (Any Terminal) •••.••••••••••••.•••••••••••••• SOmA Storage Temperature ••••••••••••••••••••••• -6500 10 +15O"C Lead Temperature (Soldering, 10s) ••••••••••••••••••• +3OO"C Thermal Resistance 8JA Ceramic DIP Package ••••••••••••••• 700CNi TO-1oo Can Package ••••••••••••••• 136"C1W SOIC Package ••••••••••••••••••••• 1200c1W Plastic DIP Package •••••••••••••••• 1000c1W Operating Temperature (M Version) •......••••.••....•.••••.•••. -5500 10 +125°C (I Version) ••••••.••••••••.••••.•••••••••• -2SOC to +8500 (C Version) ••••••••••••••••••••.••••••••••• O"C to +70"C CAUTION: Stresses abol/8 those listed in "Absolute Maximum ReUngs" may cause permanent d8.ma{18 to IhtI d8.vIce. This is a stress only rating and operation of the device at thssa or any other conditions aboII8 those Indicated In thll operational sections of this specification is not I"'PHad. Electrical Specifications v+ = +15V, v L = +5V, v- = -15V, TA =+25'C Unless Otherwise Specified. M GRADE DEVICE (NOTE 1) PARAMETER TEST CONDITIONS TYP -55°C +'1S°C +12SOC IIC GRADE DEVICE _'1S0 C/ +85°C/ O"C +2SOC +70oC UNITS DC CHARACTERISTICS Supply Voltage Ranges (Nole3) Positive Supply, V+ 510 15 - - Logic Supply, VL 510 15 - - - -5to-15 - Vo = ±5V, Is = 10mA, Y,N ~ 2.4V (Note 4) 50 75 Vo = ±10V, Is = 10mA, Y,N ~ 2.4V (Note 4) 100 Switch "ON" Resistance, ROS(ON) V+ = VL = +5V, Y,N = 3V, V- = -5V,Vo = ±3V, Is = 10mA On Resistance Match Between Channels, .l.RoS(ON) Is = 10mA, Vo = ±5V Negative Supply, VSwitch "ON" Resistance, ROS(ON) - - - - - - - 75 100 75 75 100 n 125 125 00175 150 150 175 n 175 250 250 350 300 300 350 n 5 - - - - - - n - - - - V - - V ta.5 50 ±1 100 nA - ±1 SO ±2 100 nA ±1 50 - - - - - - ±1 100 ±1 >2.4 Logic "0" Input Voltage, V,L <0.8 VSID =±5Vor±14V, V,N SO.8V (Notes 2 and 4) Switch "ON" Leakage, IO(ON) + IS(ON) VSID = ±5V, Y,N ~ 2.4V IH5341 IH5341 IH5352 VSID = ±14V, Y,N ~ 2.4V VSID = ±5Vor ±14V, V,N SO.8V IH5352 - Logic '" Input Voltage, V,H Switch "OFF" Leakage, lD(oFF) or IS(OFF) - - - V V V ±2 100 nA ±2 100 nA 100 - ±2 100 nA Input Logic Current, liN YiN > 2.4V or < OV 0.1 ±1 ±1 10 ±1 ±1 10 mA Positive Supply Quiescent Current, 1+ Y,N = OV or +5V 0.1 1 1 10 1 1 10 mA Negative Supply Quiescent Current, 1- Y,N = OV or +5V 0.1 1 1 10 1 1 10 IiA Logic Supply Quiescent Current, IL Y,N = OV or +5V 0.1 1 1 10 1 1 10 IiA 9·157 Specifications IH5341, IH5352 Electrical Specifications V+ = +15V, v L = +5'1, V- = -15V, TA = +25°C Unless Otherwise Specified. (Continued) M GRADE DEVICE PARAMETER TEST CONDITIONS IIC GRADE DEVICE "~ (NOTE 1) -55"C +25°C +125"C TYP +85"CI +25°C +70oC UNITS O"C AC CHARACTERISTICS Switch "ON" Time, toN - Switch "OFP Time, toFF - ·OFP Isolation Rejection Ratio,OIRR - Cross Coupling Rejection Ralio,CCRR - - - SWitch Attenuation adB Frequency, f_ 150 300 80 150 60 - 100 - 70 - - - - - ns - ns dB dB MHz NOTES: 1. "TYPical values are not tested in production. They are given as a design aid only. 2. Positive and negative voltages applied to opposite sides of switch, in both directions successively. 3. These are the operating voltages at which the other parameters are tested, and are not directly tested. 4. The logic Inputs are either greater than or equal to 2.4V or less than.or equal to O.BV, as required, for this test. Typical Performance Curves· 70 180 PIN 3. +15Y, PIN 7. -16V PIN 10 .. +5V, TA" ..as°c 60 V §: Z' ~ II: 40 .-" ~ V §: ~ / 80 80 -5 -16 ! 70 II: II: l5 60 50 / "" °c TA=+25 80 ~ 80 ! "- ',,- I" 70 II: 8 ........ 80 ,r\ ~ 60 " 40 1 10 FREQUENCY (MHz) +6 0 ANALOG INPUT VOLTAGE LEVEL (V) 100 40 30 0.1 V FIGURE 2. RDS(ON) VI ANALOG INPUT LEVEL WITH ±5V POWER SUPPUES TAoo+25°c .......... ~ 100 FIGURE 1. RDS(ON) va ANALOG INPUT VOLTAGE WITH ±15V POWER SUPPUES 80 J" 140 1120 -10 -5 0 5 10 ANALOG INPUT VOLTAGE LEVEL (V) 100 L 160 I 50 30 -15 / PIN 3 .. PIN10 .. +6V PIN 7 • -5V, TAOO +25"c 30 0.1 100 FIGURE 3. OFF ISOLATION REJECTION VI FREQUENCY (SEE FIGURE 8) 1 10 FREQUENCY (MHz) 100 FIGURE 4. CROSS COUPUNG REJECTION VI FREQUENCY (SEE FIGURE 9) 9-158 1H5341,IH5352 Typical Performance Curves (Continued) -3.41--+-+-H-HJH+--f-+--I+++++I--+++++tI1-I i~ -3.5 !::; ~ -3.sl--+-+-H+l-H+--f-+--I+++++I--+++++I-I-H z ~~7~-r~+H-Hr--r+~~~-r~~H-H i -3.8 ~-r~+H-Hr--r+~ttt~-r~-lfl-H-H Z ' CONTROL INPUT 1 o1'a L ..... SOURCE 0 (VIDEO INPUT) DRIVER TRANSLATOR SWITCH a{0-0 SOURCE ! (VIDEO OUTPUT) • -=- NOTE: 1 channel of 4 shown. The control input level shifting circuitry is very similar to that of the IH5140 series of Analog Switches, and gives very high speed, guaranteed "Break-Befora-Make" action, low static power consumption and TTL compatibility. FIGURE 6. INTERNAL SWITCH CONFIGURATION Test Circuits +5V =+3.5V Vour VANALOG+SV +3V:rL OV 110% OV TTL IN toFF --t"'+'"""1 OV 100n Vour VANALOQ·5V 10'1(, ·15V =-3.5V 110% NOTE: Only one channel shown. Other acts Identically. FIGURE 78. SWITCHING TIME WAVEFORMS FIGURE 7A. SWITCHING TIME TEST CIRCUIT FIGURE 7. 9-159 IH5341, IH5352 Test Circuits (Continued) +15V VIN VIN OIRR = 2010gVOUT +5V = 225mV RMS at f = 10MHz VIN CCRR = 2010gVOUT NOTE: Only one channel shown. Other acts Identically. FIGURE 8. OFF ISOLATION TEST CIRCUIT FIGURE 9. OFF ISOLATION TEST CIRCUIT RL AnN: = 2010g R DS(ON) +R L Nominally, at DC, this ratio is equal to -4dB. When the attenuation reaches -1 dB, the frequency at which this occurs Is f3dB NOTE: Only one channel shown. Other acts identically. FIGURE 10. SWITCH AnENUATION VI FREQUENCY ~160 IH5341,IH5352 Typical Applications Since Individual parts are very consistent In their charge Injection, It Is possible to replace the potentiometer with a pair of fixed resistors, and achieve less than SmV error for all devices without adjustment. Charge Compensation Techniques Charge Injection results from the signals out of the level translation circuit being coupled through the gate-channel and gate-source! drain capacltences to the switch Inputs and outputs. TIlls feedthrough Is particularly troublesome In Sample-and-Hold or Track-and-Hold applications, as it causes a Sample (Track) to Hold offset. The IHS341 devices have a typical Injected charge of 3OpCSOpO (corresponding to 3OmV-SOmV In a 1OOOpF capacitor), at VSID ofaboutOV. TIlls Sample (1I'ack) to Hold offset can be compensated by bringing In a signal equal In magnitude but of the opposite polarity. The circuit of Flgure 11 accomplishes this charge Injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a generator of a compensating signal. The 1kO potentiometer allows the user to adjust the net In]ected charge to exactly zero for any analog voltage in the -SV to +SV range. 750 +15V --I\M--~., VOUT An alternative arrangement, USing a standard TTL inverter to generate the required inversion, Is shown in Figure 12. The capacitor needs to be Increased, and becomes the only method of adjustment. A fixed value of 22pF is good for analog values referred to ground, while 3SpF Is optimum for AC coupled signals referred to -SV es shown In the figure. The choice of -SV Is besed on the virtual disappearance at this analog level of the transient component of switching charge injection. This combination will lead to a Virtually "glitch-free" switch. Overvoltage Protection If sustained operation with no supplies but with analog signals applied is possible, It is recommended that diodes (such as 1N914) be inserted in series with the supply lines to the IHS341. Such conditions can occur if these signals come from a separate power supply or another location, for example. The diodes will be reverse biased under this type of operation, preventing heavy currents from flowing from the analog source through the IHS341. The same method of protection will provide over 2SV 0 vervoltage protection on the analog Inputs when the supplies are present. The schematic for this connection is shown in Figure 13. ~ 8 -15V +15V - ANALOG INPUT -p---.., ... 4 10pF CHOLD I-=- 1000pF ..r-L:"+3V OV TTL IN (STROBE) ""'-'1--- -15V • Adjust pot for Omvp.p steip at Your with no analog (AC) signal present. FIGURE 11. CHARGE INJECTION COMPENSATION FIGURE 13. OVERVOLTAGE PROTECTION +5V +5V VOUT DC BIAS VOLT~~ -"M...-. 750 ANALOG>--H_~+.;..I INPUT 1"F 22pF-35pF CHOLD ~1000PF +3V":r"L .. +4V . . . . . OV- ..... OV TTL CONTROL IN FIGURE 12_ ALTERNATIVE COMPENSATION CIRCUIT 9-161 1H5341 Die Characteristics DIE DIMENSIONS: 238811fTl x 2515J.Lm METALLIZATION: Type: AI Thickness: 1okA ± 1kA GLASSIVATION: Type: PSG/Nitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness: 8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout IH5341 V+ (SUBSTRATE) GND 1Hz 9-162 IH5352 Die Characteristics DIE DIMENSIONS: 2617~ x 5233J.lm METALLIZATION: Type: AI Thickness: 1okA ± 1 kA GLASSIVATION: Type: PSG/Nitride PSG Thickness: ;t:. Nitride Thickness: BkA ± 1.2kA 7kA 1.4kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout IH5352 C/) W J: oI§ C/) 9-163 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I DATA ACQUISITIO_ 10 MULTIPLEXERS PAGE MULTIPLEXERS SELECTION GUIDES SINGLE 1 xB ........•..........•.•.•.•..•...••••••...•••..•....................•....••... 10-2 SINGLE 1 x 16 .............•••....•.....•...••••.••....•.............•........••••..••.... 10-3 DUAL1x4 •••...•...••.......................•.•...•.•.•••....••..•..•••..•...•...•....•. 10-4 DUAL1xB ...............................•.•.•......•••.•.•.......•...••••••••....•...... 10-5 LATCHABLE MULTIPLEXERS, (.1PROCESSOR COMPATIBLE, SELECT LATCHES ...••..••.•..••••••... 10-6 PROGRAMMABLE CONFIGURATION SINGLE 1 OF 16 OR DIFFERENTIAL 2 OF B •....•..•.•...•••.... 10-7 PROGRAMMABLE CONFIGURATION SINGLE 1 OF B OR DIFFERENTIAL 2 OF 4 .••.••...•.........•.• 10-7 70V PEAK-TO-PEAK OVERVOLTAGE PROTECTED MULTIPLEXERS •.••...•.........•.............• 10-7 DIFFERENTIAL INPUT MULTIPLEXERS •.........•...••.•.•.•....•..••.•.••.••...•.•...•...... 10-9 MULnPLEXERS DATA SHEETS D0406, DG407 Single 16-ChannellDlfferential 8-Channel CMOS Analog Multiplexers .......•...•. 10-15 DG408, 00409 Single 8-ChannellDlfferential 4-Channel CMOS Analog Multiplexers .••••••.••..•. 10-17 DG458, DG459 Single 6-ChannellDlfferential 4-Channel Fault Protected Analog Multiplexers ••.•••• 10-31 w >< w oo506A, 00507A, CMOS Analog Multiplexers •.•...••.•.....•.•••..•.•..•...•...•.•.•.•••..•.•• DG50BA, oo509A 10-41 a. 5 00526, 00527, oo52B, 00529 Analog CMOS Latchable Multiplexers••.....•.••...........•.•.....•...•.•.•••• 10-54 :2 HI-1B18A, HI-182BA Low Resistance, Single B Channel and Differential 4 Channel CMOS Analog Multiplexers .... 10-70 HI-506, HI-507, HI-50B, HI-509 Single 16 and 8IDifferential8 and 4 Channel CMOS Analog Multiplexers •••••..••.•••. 10-78 HI-506A, HI-507A, HI-508A, HI-509A 16 Channel, B Channel, DifferentialB and Differential 4 Channel, CMOS Analog MUXs with Active Overvoltage Protection •••••....•...••.••••.•.••..•......•...• 10-95 HI-516 16 ChanneVDifferential 8 Channel CMOS High Speed Analog Multiplexer ••...••.•.... 10-109 HI-518 B ChannelIDifferential4 Channel CMOS High Speed Analog Multiplexer •..•...•.•..•. 10-116 HI-524 4 Channel Wldeband and Video Multiplexer •....•..•.•••.....•.••.•••••••....... 10-123 HI-539 Monolithic, 4 Channel, Low Level, Differential Multiplexer •.....••..••.•••.•...•...• 10-129 HI-546, HI-547, HI-548, HI-549 Single 16 and B, DifferentialB and 4 Channel CMOS Analog MUXs with Active OIIeNoItage Protection •••.•.•....••••••...•.••••.••...•.••....•..•..•.•••••••••• 10-140 NOTE: Bold "TYPe Designates a New Product from Harris. 10-1 0 a: ....I = TABLE 1. SINGLE 1 x 8 (FIGURES 1, 2) (NOTES 2, 3) DEVICE DG408 (NOTE 1) ROS(ON) (QMAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY DG408AKl883 40 2.4 0.8 44VCMOS-JI SUFFIX CODES MIL SPEC DJ, DY IDOFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) 115 105 Low Fault Protected DG458AKl883 1200 2.4 0.8 44VCMOS-JI 0.03 200 250 DG508A AK, BK, BY, CJ,CK,CY DG508AAKl883B 450 2.4 0.8 44VCMOS-DI 0.3 250 250 DG528 AK, BK, BY, CJ,CK, CY DG528AKl883B 450 2.4 0.8 44VCMOS-JI 0.015 1,000 400 Hll-0508 -2, -4, -5, -7, -8, -9 H11-0508l883 400 2.4 0.8 44VCMOS-DI 0.3 250 250 H13-0508 -5 DG458 DJ,DY HI4P0508 -5 HI9P0508 -5, -9 Hll-0508A -2,-5, -7,-8 H13-0508A -5 FEATURES RDS(ON) Microprocessor Compatible en CD z Hll-0518 -2, -5, -8,-9 H13-0518 -5, -9 H14-0518 -8 HI4P0518 -5, -9 HI9P0518 -5, -9 Hll-0548 -2, -4,-5 HI3-0548 -5, -9 HI4P0548 -5 HI9P0548 -5, -9 H11-1818A -2, -5,-7 H13-1818A -5 HI4P1818A -5 -_. (;) H14-0508l883 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 Active Overvoltage Protection. See Table 8 (Note 5) 750 2.4 0.8 33VCMOS-DI 0.015 120 140 Programmable 1 of 8, Differential 2 of 4, Figure 2, See Table 8, (Note 5) (') o :J C) _. C a. CD Hll-05481883 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 400 4.0 0.4 40VCMOS-DI 0.1 300 300 HI4-05481883 HI1-1818A1883 - - - - - - - _ .. - Active Overvoltage Protection. 7% RDS(ON) Matching. See Table 8 (Note 5) TABLE 2. SINGLE 1 x 16 (FIGURE 3) (NOTES 2. 3) DEVICE 00406 (NOTE 1) ROS(ON) (0 MAX) V1NH MIN (V) VINL MAX (V) TECHNOLOGY IDOFF TYP(±nA) TON TYP(ns) TOFF TYP (ns) DG406AKl883 50 2.4 0.8 44VCMOS-JI 0.01 lS0 70 SUFFIX CODES MIL SPEC DJ,DY FEATURES Low ROS(ON)' Low Leakage DG506A AK, BK,BY, CJ,CK,CY DGS06AAKl883B 450 2.4 0.8 44VCMOS-DI 0.3 2S0 250 00526 AK,BK,BY, CJ, CK,CY DGS26AKl883B 400 2.4 0.8 44VCMOS-J1 0.2 700 400 Hll-0506 ·2, -4, ...5, -7, -8, -9 Hll-0506I883 400 2.4 0.8 44VCMOS-DI 0.3 2S0 250 HI3-0506 -S en HI4P0506 -S (j) HI9P0506 -S, -9 e. o Microprocessor Compatible CD (') H14-0506r'883 -~ Hll-0506A -2, -S, -7, -8 HI3-0506A -5 Hll-0S16 -2, -S,-8 H13-0S16 -5 H14-0S16 -8 HI4POS16 -S HI9POS16 -S, -9 Hll-0546 -2, -4, -S, -7 HI3-0546 -5, -9 HI4P0546 -S HI9P0546 -S,-9 Hll-05161883 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 Active Overvoltage Protection. See Table 8 (Note S) 750 2.4 0.8 33VCMOS-DI 0.03 120 140 Programmable, 1 of 16, Dlfferenlial2 of 8. See Table 8 (NoteS) :::J C) C a:CD '0 HI4-05161883 ~ :::I C II HI 1-05461883 H14-0546I883 - - 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 Active OvervoHage Protection. See Table 8 (Note S) 7% ROS(ON) Matching .s TABLE 3. DUAL 1 x 4 (FIGURE 4) {NOTE 1) RoS(oN) (QMAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY oo409AKl883 40 2.4 0.8 44VCMOS-JI oo459AKl883 1200 2.4 0.8 SUFFIX CODES MIL SPEC 00409 DJ,DY 00459 DJ,DY (NOTES 2, 3) DEVICE TYP{±nA) TON TYP(ns) 115 105 Low ROS(ON) 44VCMOS-JI 0.03 200 250 Fault Protected lDOFF TOFF TYP(ns) oo509A AK,BK,BY, CJ,CK, CY oo509AAKl883B 400 2.4 0.8 44VCMOS-J1 0.3 250 250 DG529 AK,BK, BY, CK,CY oo529K1883B 450 2.4 0.8 44VCMOS-J1 0.008 1000 400 400 2.4 0.8 44VCMOS-DI 0.3 250 250 Hll-0509 -2, -4, -5, -7, -8, Hll-0509l883 FEATURES Microprocessor Compatible en -9 (I) HI3-0509 -5 (j) HI4P0509 -5 HI9P0509 -5,-9 (') :J C) HI4-0509l883 ~ ~ eo o Hll-0509A -2, -5, -7, -8 HI3-0509A -5 Hll-0518 -2,-5,-8,-9 H13-0518 ·5,·9 H14-0518 -8 HI4P0518 -5, -9 HI9P0518 -5, -9 Hll-0539 -2, -4, -5, -8 HI3-0539 -5 HI4P0539 -5 --- 1800 750 4.0 2.4 0.8 0.8 44VCMOS-DI 33VCMOS-DI 0.1 0.015 300 120 300 140 Active Overvoltage Protection, See Table 8 (Note 5) Programmable 1 of 8, Differential 2 of 4, (Figure 2), See Table 7 _. C a. (I) o ~ :; C ID .s 850 4.0 0.8 33VCMOS-DI 0.001 250 160 Low Level Signals, 3% Max ROS(ON) Matching TABLE 3. DUAL 1 X 4 (FIGURE 4) (Continued) (NOTES 2, 3) DEVICE SUFFIX CODES MIL SPEC HI1-D549 -2, -4,-5 HI1-0549/883 HI3-D549 -5, -9 HI4P0549 -5 HI9P0549 -5, -9 (NOTE 1) RoS(oN) (0 MAX) V1NH MINM V1NL MAXM TECHNOLOGY IDOFF TYP (±nA) TON TYP(ns) TOFF TYP(ns) 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 400 4.0 0.4 4OVCMOS-DI 125 Max 300 300 FEATURES 70V Active Overvoltage Protaction, 7% ROS(ON) Matching, See Table 8 (Note 5) HI4-05491883 HI1-1828A -2,-5,-7 HI3-1828A -5 H14P1828A -5, -8 HI1-1821l1883 , en , eo oj HI4-1828A1883 .... z: C) TABLE 4. DUAL 1 X 8 (FIGURE 5) (NOTES2,3) DEVICE s:: (NOTE 1) ROS(ON) (0 MAX) V1NH MINM V1NL MAXM TECHNOLOGY IooFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) SUFFIX CODES MIL SPEC DJ,DY DG407AKl883 50 2.4 0.8 44VCMOS-JI 0.01 150 70 DG507A AK, BK, BY, CJ,CK,CY DG507AAKl883B 450 2.4 0.8 44VCMOS-J1 0.03 250 250 DG527 AK,BK,BY, CJ,CK,CY DG527AKl883B 400 2.4 0.8 44VCMOS-J1 0.2 700 400 400 2.4 0.8 44VCMOS-DI 0.3 250 250 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 DG407 H11-D507 H13-D507 -5 -5 HI9P0507 -5,-9 H11-D507A -2,-5, -7,-8 H13-0507A -- _ . _ - - - -5 FEATURES Low ROS(ON)' Low Leakage a:CD n ~::J C -2, -4, -5, -7, -8, HI1-0507/883 -9 HI4P0507 CD CD (') Microprocessor Compatible HI4-0507/883 MULTIPLEXERS Active Overvoltage Protaction, See Table 8 (Note 5) ! TABLE 4. DUAL 1 x 8 (FIGURE 5) SUFFIX CODES MIL SPEC Hll-0516 -2, -5,-8 Hll-05161883 H13-0516 -5 H14-0516 -8 HI4P0516 -5 (NOTES 2, 3) DEVICE HI9P0516 (Continued) (NOTE 1) ROS(ON) (0 MAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY IOOFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) 750 2.4 0.8 33VCMOS-DI 0.03 120 140 Programmable, 1 of 16, Differential 2 of 8, See Table 8 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 Active Overvoltage Proteclion, 7% ROS(ON) Matching, See Table 8 (Note 5) FEATURES HI4-05161883 -5, -9 -2,~-4, HI1-0547 -5,-9 HI 1-05471883 -5, -9 HI3-0547 HI4P0547 -5 HI9P0547 -5,-9 en CD CD n HI4-05471883 __ '--- ~ o TABLE 5. LATCHABLE MULTIPLEXERS, ~PROCESSOR COMPATIBLE, SELECT LATCHES ~ ~ (NOTES 2, 3) DEVICE SUFFIX CODES MIL SPEC :::J C) (NOTE 1) ROS(ON) (0 MAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY IOOFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) 2.4 0.8 44VCMOS-JI 0.2 700 400 1 of 16 Channels, Microprocessor Compatible _. C Co CD '0 FEATURES DG526 AK, BK, CJ, CK DG526AKl883B 400 DG527 AK, BK, CJ, CK DG527AKl883B 400 2.4 0.8 44VCMOS-JI 0.2 700 400 Differenliall if 8 Channel, Microprocessor Compatible 00528 AK, BK, CJ, CK DG528AKl883B 450 2.4 0.8 44VCMOS-JI 0.015 1,000 400 1 of 8 Channels, Microproces- i sor Compatible , DG529 AK, BK, CJ, CK DG529AKl883B 450 2.4 0.8 44VCMOS-JI 0.008 1,000 400 Dual 1 of 4 Channel, Microprocessor Compatible -~ ~ ;, I C III S: TABLE 6. PROGRAMMABLE CONFIGURATION SINGLE 1 OF 16 OR DIFFERENTIAL 2 OF 8 (FIGURE 6) (NOTE 1) (NOTES 2, 3) DEVICE Hll·0S16 SUFFIX CODES -2, -S,-8 H13-0S16 -S H14-0S16 -8 HI4POS16 -S HI9POS16 -S, -9 MIL SPEC Hll-0Sl61883 RoS(oN) (0 MAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY IDOFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) 7S0 2.4 0.8 33VCMOS-DI 0.03 120 140 FEATURES Programmable, 1 of 16, Differential 2 of 8 HI4-0S161883 en CD TABLE 7. PROGRAMMABLE CONFIGURATION SINGLE 1 OF 8 OR DIFFERENTIAL 2 OF 4 (FIGURE 7) (NOTES 2, 3) DEVICE ~ '? -.j SUFFIX CODES Hll-0S18 -2, -S, -8, -9 H13-0518 -5, -9 H14-0518 -8 HI4P0518 -5, -9 MIL SPEC (NOTE 1) RoS(oN) (0 MAX) V1NH MIN (V) V1NL MAX (V) TECHNOLOGY IDOFF TYP(±nA) TON TYP(ns) TOFF TYP (ns) 7S0 2.4 0.8 33VCMOS-DI 0.015 120 140 CD FEATURES Programmable, 1 of 8, Differential 2 of 4 (') ~ o :l G) _. C Q. CD TABLE 8. 70V PEAK-TO-PEAK OVERVOLTAGE PROTECTED MULTIPLEXERS (NOTE 6) "0 ~ :i" (NOTE 1) (NOTES2,3) DEVICE SUFFIX CODES Hll-0506A -2,-S,-7 HI3-0506A -5 HI4-0506A -8 Hll-0507A -2, -S,-7 HI3-0507A -5 HI4-0507A -8 MIL SPEC V1NH MIN (V) V1NL MAX (V) 1800 4.0 0.8< 1800 4.0 0.8 ROS(ON) (0 MAX) I MULTIPLEXERS I TECHNOLOGY IDOFF TYP(±nA) TON TYP(ns) TOFF TYP(ns) NO. OF CHANNELS 44VCMOS-DI 0.1 300 300 1 x 16 44VCMOS-DI 0.1 300 300 2x8 FEATURES Differential Inputs c CD .s TABLE 8. 70V PEAK-To-PEAK OVERVOLTAGE PROTECTED MULTIPLEXERS (NOTE 6) (NOTES 2,3) DEVICE SUFFIX CODES Hll"()508A -2, -5,-7 HI3-0508A -5 HI4-0508A -8 HI1"()509A -2, -5,-7 HI3-0509A -5 HI4..()509A -8 HI1-0546 -2, -4,-5 HI3-0546 -5 HI4P0546 -5 HI9P0546 -5, -9 MIL SPEC Hll"()5461883 (Continued) (NOTE 1) RDS(ON) (0 MAX) VINH MINM MAXM TECHNOLOGY TYP(±nA) TON TYP(ns) TOFF TVP(ns) NO. OF CHANNELS 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 h8 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 2x4 Differential Inputs 1800 4.0 0.8 44VCMOS-DI o.r 300 300 1 x 16 7% ROS(ON) Matching V1NL IooFF FEATURES Hll"()5471883 Hll"()547 HI3-0547 -2, -4,-5 HI4P0547 -5 H19P0547 -5, -9 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 2x8 7% ROS(ON) Matching Differenllallnpuls -2, -4,-5 HI3-0546 -5 HI4P0546 . -5 HI9P0546 -5, -9 C) c a: CD HI4-05471883 HI1"()548 CD ~ o ::s HI4-05461883 ~ en CD Hll"()5481883 HI4..()5461883 1800 4.0 0.8 -- 44VCMOS-DI 0.1 300 300 lx8 7% RoS(ON) Matching i= 1 TABLE 8. 70V PEAK-TO-PEAK OVERVOLTAGE PROTECTED MULTIPLEXERS (NOTE 6) (NOTES 2, 3) DEVICE SUFFIX CODES MIL SPEC Hll-0549 -2, -4,-5 H 11-0549/883 HI3-0549 -5 HI4P0549 -5 HI9P0549 -5, -9 (Continued) (NOTE 1) RDS(oN) (QMAX) V1NH MIN(y) V1NL MAX (V) TECHNOLOGY IDOFF TYP(±nA) TON TYP(ns) TOFF TVP(ns) NO. OF CHANNELS 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 2x4 FEATURES 7% ROS(ON) Matching Differential Inputs HI4-0549/883 en TABLE 9. DIFFERENTIAL INPUT MULTIPLEXERS DG507A AK, BK, BY, CJ,CK,CY DG507AAKl883B 450 2.4 0.8 44VCMOS-JI 0.03 250 250 8 ...oCD_. DG509A AI<, BI<, CJ, CK DG509AAKl883B 400 2.4 0.8 44VCMOS-JI 0.3 250 250 4 C) 400 2.4 0.8 44VCMOS-DI 0.1 250 250 2x8 (NOTES 2,3) DEVICE ~ (1) Hll-0507 SUFFIX CODES MIL SPEC (NOTE 1) RDS(oN) (QMAX) V1NH MIN(y) V1NL MAX (V) -2, -4, -5, -7, - Hll-0507/883 8,-9 HI3-0507 -5 HI4P0507 -5 HI9P0507 -5, -9 TECHNOLOGY IDOFF TYP(±nA) TON TYP (ns) TOFF TVP(ns) NO. OF CHANNELS (') FEATURES ::J _. C Q. (1) '0 ~::I C S. HI4-0507/883 Hll-D507A -2, -5, -7, -8 HI3-0507A -5 HI4-0507A Hll-0509 HI3-0509 1800 4.0 0.8 44VCMOS-DI 0.1 300 300 2x8 450 2.4 0.8 44VCMOS-DI 0.3 250 250 2x4 -8 -2, -4, -5, -7, - Hll-0509/883 8,-9 -5 HI4P0509 -5 HI9P0509 -5, -9 HI4-0509/883 MULTIPLEXERS_I_ ~ Active Overvoltage Protection See Table 8 (NoteS) TABLE 9. DIFFERENTIAL INPUT MULTIPLEXERS (Continued) (NOTES2,3) D.EVICE SUFFIX CODES HI1-0509A -2,-5,-7, -8 HI3-0509A -5 HI4-0509A MIL SPEC (NOTE 1) RDS(ON) (llMAX) VINH MIN (V) VINL MAX (V) IDOFF TYP(±nA) TON TOFF TECHNOLOGY TYP(ns) TYP(ns) NO. OF CHANNELS 1800 4.0 0.8 44VCMOS-OI 0.1 300 300 2x4 Active Overvoltage Protection See Table 8 (Note 5) 1800 4.0 0.8 33VCM08-01 0.1 500 500 1x16 7% ROS(ON) Malching 750 2.4 0.8 33VCMOS-OI 0.015 120 140 4 -8 HI1-0516 -2, -5,-8 HI3-0516 -5 HI4-0516 -8 HI4P0516 -5 H19P0516 -5, -9 HI1-0518 -2, -5, -8,-9 HI3-0518 -5, -9 HI4-0518 -8 HI4P0518 -5, -9 HI9P0518 -5, -9 HI1-05161883 HI4-05161883 en ~ HI1-0539 -2, -4, -5,-8 H13-0539 -5 HI4P0539 -5 HI1-0547 -2, -4, -5,-9 HI3-0547 -5, -9 HI4P0547 -5 HI9P0547 -5, -9 Programmable 1 of 8, Oifferenlial2 of 4, Rgure 2, See Table 7 HI1-0547/883 850 4.0 0.8 33VCM08-01 0.001 250 160 4 1800 4.0 0.8 44VCM08-01 0.1 300 300 2x8 Low Level Slgnals, 3% Max Ros(ON) Malching Active Overvoltage Protection, 7% ROS(ON) Malching See Table 8 (Note 5) HI4-0547/883 HI1-0549 -2, -4,-5 HI3-0549 -5, -9 HI4P0549 -5 1i19P0549 -5, -9 HI1-1828A -2, -5,-7 HI3-1828A -5 HI4-1828A -8 HI4P1828A -5 (I) CD (') =::!:. o ::J ~ o FEATURES HI1-0549/883 1800 4.0 0.8 44VCM08-01 0.1 300 300 2x4 400 4.0 0.4 4OVCM08-01 125 Max 300 300 2x4 HI4-0549/883 HI1-1828A1883 HI4-1828A1883 70V Active Overvoltage Protection, 7% ROS(ON) Malching, See Table 8 (Note 5) C) C c: (I) '0 g !f Ii .s NOTES: = 1. The RoS(ON) of a CMOS switch varies as a function of supply voltage, analog signal voltage, and temperature. Values shown are maximum (unless noted"lW" typical) at +250 C. SWITCH "ON" V: Digital Threshold to "CLOSE" a particular switch. (Minimum If greater than "OFP. Maximum If less than "OFF"). SWITCH "OFP V: Digital Threshold to "OPEN" a particular switch. (Minimum If greater than "ON". Maximum if less than "ON"). V1NL: Digital Threshold to represent a "Low" select signal. (Maximum, voltage levels greater than this value are not guaranteed to produce a "LOW"). V1NH: Digital Threshold to represent a "HIGH" select signal. (Minimum, voltage levels less than this value are not guaranteed to produce a "HIGH"). 2. Package codes: OG Types - SUFFIX: A 10 Lead T0-100 J Plastic DIP IH Types - MIddle SUFFIX Letter: J CaramIc DIP P Plastic DIP HI Types - PREFIX: HI1 Ceramic DIP HI2 Metal Can ... ~ K Ceramic DIP P Ceramic DIP T T0-100 Can B SOIC HI3 Plastic DIP HI4P PLCC HI4 Ceramic LCC HI9 Ratpack HI9P SOIC 3. Temperature Code Sumx: -1: 00 to +2OQOC -2, A, or M: -5500 to + 12SOC -4 or B: -2500 to +8500 -5: OOC to +750 C C: OOC to +7OOC -7: OOC to +7500 with Bum-In -8: -55OC to +12SOC with Bum-In -9: -4OOC to +85°C 1883: MII-Std-883, Class B, -5500 to +125"C with Bum-In I: Industrial, -2SOC or -4OOC to +8500, see data sheet. 4. Double Throw swi1ches have one switch ON and the other switch OFF for each Input state. See data sheet. 5. OvervoItage Protection: Analog Inputs can Withstand up to 70V peak to peak levels, with no channal interaction. 6. Fault ProtecIIon: AI channels ara OFF when supply power Is off, up to +25V inputs. Any channel turns OFF when Input exceeds supply rail f CD ~ _. o ::J G) C s:CD a ! I Sa S] !Is S5 S4 Sa Sa SI frr rrrrr VooIlLS I Ao Al A-t EN (ENABLE INPUl) IN lA D FIGURE 1. 1 x 8 MULTIPLEXER EN>-~--------------~-+~ z~ ~ A-t , ~H , II II 1 OUTA DECODER IN SA en (I) S16 S15 S14 S13 S12 Sl1 SIO S9 Sa S] S6 S5 S4 S3 S2 SI ... I frrrrrrrrrrrrrIr I IN1B .._. CD (') 0 D OUTB ~ J\) :::s Q '-----oil DECODER INSB _. C Q. (I) Ao Al A-t A3 EN FIGURE 3. 1 x 16 MULTIPLEXER '0 ~ 0 ~ = =,.,.. "11",1111""""11,.,1""",1'""#"""""",,,,""" INPUT BUFFER AND DECODERS MULTIPLEXER SWITCHES A3 DECODER S4B S38 SzB SIB S4A S3A S2A SIA ~?U Os DA FIGURE 4. DUAL 1 x 4 MUX A3 Q Q H H L L L H v- L L FIGURE 2. PROGRAMMABLE ::J g. C CD oS Sn! Sea SSB S4B BaB ~B S1B SaA S7A BaA SSA S4A S3A BaA S1A rrrrrrrf rrrrrfrf I I SIB Os "0 A1 A:! EN (ENABLE INPUT) DA FIGURE 5. DUAL 1 x 8 MUX VooJLLS .,.""""""""""'" ~ ~ ~ ~ EN)' ~ ~ ~: ~ Co> Ao VooJLLS ...' ............." ' ........' ................( .......................................................... ~~ A I.. - i' I ~ INIA i I'~~OUTA ,II ttl III ~',"""","""""'. ~ I ! A1) C'D INIA ~ CD .11 , a o I'I~OUTA I I I DECODER :::J ,- I I ! G) (IN4A _. C A:! ~ ~ ~ C. C'D ! i ~ en , i i >-~-------rfllrrl-ll C IN BA j ~ ~ ~ ~ ~ , EN)' "0) ~ ,- DECODER , <"""""""""1""''''''''''''''' i INIB INIB ::I OUTB OUTB DECODER I DECODER ~ ~ ~ ~ ~ ~ IN4B INBB Aa A2 DECODER DECODER ....... ~ -, ~ V" : I......." " ' ' ' ' ' " , , . , , . , . ' ' ' ' ' ' ' ' , , , , . ' ' ' ' , . ' ' ' , . ,...'~'',I'....' ' ' ...,,,"'"'~ ; ~ ~ INPUT BUFFER AND DECODERS 1 MULTIPLEXER SWITCHES A3 Q Q H H L L L H v- L L FIGURE 6. PROGRAMMABLE SINGLE 16 OR DIFFERENTIAL 8 MULTIPLEXERS i ~ y)-l """'""'"''''''''''"'''"'''''''''''.I''''~'''''''''''''",'. INPUT BUFFER AND DECODERS MULTIPLEXER SWITCHES FIGURE 7. PROGRAMMABLE SINGLE 8 OR DIFFERENTIAL 4 Q Q H H L L L H v- L L DG406, DG407 Single 16-Channel/Differential 8-Channel CMOS Analog Multiplexers PRELIMINARY December 1993 Features Description • ON-Resistance 1000 Max The DG406 and DG407 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A and DG507A series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. • Low Power Consumption (Po < 1.2mW) • Fast Transition Time (3OOns Max) • Low Charge InJection • TTL, CMOS Compatible • Single or Split Supply Operation These multiplexers feature lower signal ON resistance «1000) and faster transition time (tTRANS < 250ns) compared to the DG506A and DG507A. Charge injection has been reduced, simplifying 'sample and hold applications. Applications • Battery Operated Systems • Data Acquisition The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30V peak-to-peak signals when operating with ±15V power supplies. • Medical Instrumentation • Hi-Rei Systems • Communication Systems • Automatic Test Equipment The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE -40oe to +8Soe 28 Lead Plastic DIP DG406DY -40oe to +8Soe 28 Lead sale Narrow Body DG407DJ -40oe to +85°e 28 Lead Plastic DIP DG407DY -40oe to +85°e 28 Lead sale Narrow Body DG406DJ Pinouts DG406 (PDIP, SOIC) TOP VIEW DG407 (PDIP, SOIC) TOP VIEW CAUTION: These devices are sensitl... to electroslatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-15 File Number 3116 DG406, DG407 Functional Block Diagrams 00407 DG406 D TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXlNG 10-16 DG40B, DG409 Single 8-Channel/Differential 4-Channel CMOS Analog Multiplexers December 1993 Description Features • ON-Resistance 1000 Maximum (+250 C) • Low Power Consumption (Po < 11 mW) • Fast Switching Action - tTRANS < 250ns - tONlOFF(EN) < 150ns • Low Charge Injection • Upgrade from DG508A1DG509A • TTL, CMOS Compatible • Single or Split Supply Operation Applications • Data Acquisition Systems • Audio Switching Systems • Automatic Testers • HI-Rei Systems • Sample and Hold Circuits The DG408 Single a-Channel and DG409 Differential 4Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular DG50BA and DG509A series devices. They each include an array of eight analog switches, a TTUCMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ENABLE input for device selection when several multiplexers are present. The DG408 and DG409 feature lower signal ON resistance « 1000) and faster switch transition time (tTRANS < 250ns) compared to the DG508A or DG509A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG408 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±20V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog Signals is quite low over a ±5V analog input range. • Communication Systems • Analog Selector Switch Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE DG408AKl883 -55°C to +125°C 16 Lead Ceramic DIP DG408DJ -4O"C to +85°C 16 Lead Plastic DIP DG408DY -4O"C to +85°C 16 Lead SOIC (N) DG409AKI883 -55°C to +125°C 16 Lead Ceramic DIP DG409DJ -4O"C to +85°C 16 Lead Plastic DIP DG409DY -4O"C to +85°C 16 Lead SOIC (N) Pinouts DG408 DG409 TOP VIEW TOP VIEW CAUTION: These devices ara sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1992 10-17 File Number 3283.1 " DG408, DG409 Functional Block Diagrams DG408 DG409 5l A 04-01'-.....- - - - - - - - - - ; - • i •• • L ................ DECODERI DRIVER 5. 0-11-0' 00....... ! i.................... : I. ••••••••••••••••••••••• * DIGITAL DECODERI DRIVER * DIGITAL INPUT PROTEcnON INPUT PROTECTION EN 10-18 DA Specifications DG40B, DG409 Absolute Maximum Ratings Thermal Information v+ to V" ......................................... +44.0V GNDtoV· .......................................... 25V Digital Inputs (Note 9) .••.•.••••.. (V·) -2V to (V+) + 2Vor 20mA, Whichever Occurs First Current (Any Terminal, Except S or D) •.••••.•..•••..•.•• 30mA Continuous Current, S or 0 ........................... 20mA Peak Current, S or 0 ...••.••••...••..•••..•••....... 4OmA (Pulsed lms, 10% Duty Cycle) Storage Temperature Range (0 Suffix) •..•••..• -65°C to +125°C Thermal Resistance 9JA 9JC Ceramic DIP Package............... 7O"C/W 19"C/w Plastic DIP Package • • . . • • • • • • . • • • • • l00oC/W SOIC (N) Package.................. 120"C/w Operating Temperature (0 Suffix) ...•.••••.•••••. -40C to +85°C Junction Temperature (0 Suffix) •.••••.••..••••••••••. +15O"C CAUTION: Stresses abol/ll those listed in "Absolufll Maximum Ratings" may cause permanent damage to the davice. This is a stress only IBling and opelBlion of the device at these or any other condffions above those indicated in the opelBtional sections of this specification is not impHed. Electrical Specifications Test Conditions: V+ = +15V, V· = -15V, V!oJ. = 0.8V, VNI = 2.4V, Unless Otherwise Specified D SUFFIX -40"C TO +8SoC PARAMETER TEST CONDITION (NOTE 9) TEMP (NOTE 2) MIN (NOTE 4) TYP (NOTE 2) MAX UNITS 160 250 ns DYNAMIC CHARACTERISTICS Transition Time, tTRANS (See Figure 25) Full · Break-Before·Make Interval, IoPEN (See Figure 27) Room 10 · · ns Enable Turn-ON Time, IoN(EN) (See Figure 26) Room · 115 150 ns Full · 225 ns Full · · · 150 ns 20 · pC 75 · dB Enable Turn·OFF Time, IoFF(EN) (See Figure 26) Charge Injection, Q CL = lOnF, Vs = OV Room OFF Isolation VEN = OV, RL = lka, f = 100kHz (Note 7) Room · · Logic Input Capacitance, CIN f= lMHz Room · 8 · pF Source OFF Capacitance, CS(OFF) VEN = OV, Vs = OV, f= lMHz Room · 11 · pF Drain OFF Capacitance, CD(OFF) VEN = OV, Vo = OV, f= lMHz DG408 DG409 Drain ON Capacitance, CD(ON) DG408 VEN = 3V, Vo = OV, f=lMHz,VA =OVor3V 00409 Room · 40 · pF Room · 20 · pF Room · · 54 · pF Room 34 · pF ANALOG SWITCH Analog Signal Range, VANALOG (Note 3) Full -15 · 15 V Drain·Source ON Resistance, ROS(ON) Vo =±10V,ls =-10mA (Note 5) Room · 40 100 a Full 125 a Vo= 10V,-10V Room · · · rOS(ON) Matching Between Channels, MOS(ON) · 15 a Room -0.5 · 0.5 nA Full -50 · 50 nA Room -1 · 1 nA Full -100 100 nA 1 nA 50 nA Source OFF Leakage Current, IS(OFF) VEN = OV, Vs = ±10V, Vo= +10V Drain OFF Leakage Current, 'D(OFF) VEN = Ov, Vo = ±10V, Vs=+10V DG408 DG409 VEN = Ov, Vo = ±10V, Vs=+10V Room -1 · · Full -50 · 10-19 Specifications DG408, DG409 Electrical Specifications Test Conditions: v+ = +15V, v- = -15Y, VAl. = O.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) D SUFFIX -40"C TO +85°C PARAMETER TEST CONDITION (NOTE9) TEMP (NOTE2) MIN (NOTE4) TYP (NOTE2) MAX UNITS ANALOG SWITCH (Continued) Drain ON Leakage Current, ID(ON) oo40B Vs=Vo=±10V Sequence Each SWItch ON 00409 Room -1 Fuji -100 Room -1 Full -50 - 1 nA 100 nA 1 nA 50 nA DIGITAL CONTROL Logic Input Current, Input Voltage High, IAH VA = 2.4V, 15V Full -10 - 10 jlA Logic Input Current, Input Voltage Low, IAI. VEN = OV, 2.4V, VA=OV Full -10 - 10 jlA VEN = OV, VA = OV Full - - 75 jlA Full -75 POWER SUPPLIES PosRive Supply Current, 1+ Negative Supply Current, 1Positive Supply Current, 1+ VEN = 2.4V, VA = OV Negative Supply Current, 1- - Room Full Full -500 - - - jlA 0.5 2 rnA - jlA Electrical Specifications (Single Supply) Test Conditions: V+ = 12V, V- = OV, VAL = O.BV, VAH = 2.4V, Unless Otherwise Specified D SUFFIX -4O"C TO +85°C PARAMETER TEST CONDITION (N0TE9) TEMP (NOTE2) MIN (NOTE4) TYP (NOTE2) MAX UNITS - 1BO - ns lBO - ns DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANS VS1 = BV, Vss = OV, V'N=2.4V Room Enable Tum-ON Time, TON(EN) V'NH = 2.4V, V'NL = OV, VS 1 =5V Room CL = 10nF, VGEN = OV, Room - Full 0 Room - Enable Tum-OFF Time, TOFF(EN) Charge Injection, Q Room ~EN=On 120 - ns 5 - pC - 12 V - n ANALOG SWITCH Analog Signal Range, VANAlOG (Note 3) Drain-Source ON-Resistance, ROS(ON) Vo = 3V, 10V, Is = -1 rnA (NoteS) 90 NOTES: 1. All leads soldered to PC Board. 2. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used In this data sheet. 3. Guaranteed by design, not subject to production test. 4. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. 5. Sequence each switch ON. 6. 4rOS(ON) = rOS(ON) MAX - rOS(ON) MIN. 7. Worst case isolation occurs on channel 4 due to proximity to the drain pin. B. Signals on Sx, Dx, or INx exceeding V+ or V- will be clamped by Internal diodes. limit forward diode current to maximum current ratings. 9. Room = +25"C, Cold and Hot = as determined by the operating temperature suffix. 10-20 DG40B, DG409 Typical Performance Curves 3.5 75 3.0 / V+ .. +15V V-=-15V 2.0 C' .eo J 1.0 --~ 0.5pA 0.0 -1.0 ··: · ,/ o V CD(OFF) CS(OFF) o 10 5 15 I V-=-15V Q -V I CD(OFF) "" .:f 0 ) f' ~ , -200 C' .eo J -400 -600 CS(OFF) o 12 8 VSUPPLY = 115V VIN=OV 20 -800 o -15 -55 15 VA (V) FIGURE 3. SOURCEIDRAIN CAPACITANCE va ANALOG VOLTAGE 60 4 VA (V) FIGURE 2. SOURCEIDRAIN CAPACITANCE va ANALOG VOLTAGE (SINGLE 12V SUPPLy) ./ CD(ON) 40 o ) 60 ~ L 25 I- V+,,+15V .eo --- 50 V'N(V) FIGURE 1. INPUT LOGIC CURRENT va LOGIC INPUT VOLTAGE 80 ~ CD(ON) 5 45 TEMPERATURE ("C) 85 125 FIGURE 4_ LOGIC INPUT CURRENT va TEMPERATURE 100 r---~r---~----~----r---~-----' 40 60 20 20 ~ V+=15V V-,.-15V Vs • -Vo FOR ID(OFF) Vo " VS(OPEN) FOR 'D(ON) 40 ~ -50 -100 -140 2 4 6 8 10 E....__......L____....L-____L -__......L____....L-__- - - ' -15 0 15 Vs. Vo(V) FIGURE 6. DRAIN LEAKAGE CURRENT vs SOURCEIDRAIN VOLTAGE 12 Vo(V) FIGURE 5. DRAIN LEAKAGE CURRENT va SOURCEIDRAIN VOLTAGE (SINGLE 12V SUPPLy) 10-21 DG408, DG409 Typical Performance Curves (COntinued) 20 15 V+.+l6V V-.-15V ',.,,- 10 % IF j , ,,~ 5 ~ ./ o 1.& E z 1.0 ..,...~ I""" r { 2.0 , ./ V+.+12V V- .. ~V "> - 0.5 0.0 -10 o -15 4 15 12 ±VSUPPLY (V) 8 VsM FIGURE 7. SOURCE LEAKAGE CURRENT va SOURCE VOLTAGE 105 ~ ~ ./ EN.2.4V / . / 102 V 103 V 102 :c s..:!: EN.OV ~~ 10 ~ :: :::;....-' I V$UPPLY" ±15V 104 103 / 10 EN .. 2.4V V 0.1 0.1 /" 0.01 100 20 FIGURE 8. INPUT SWITCHING THRESHOLD vs SUPPLY VOLTAGE 104 I VSUPPLY" ±15V 16 1k 10k 100k 1M SWITCHING FREQUENCY (Hz) 10M FIGURE 9. NEGATIVE SUPPLY CURRENT VI SWITCHING FREQUENCY 100 ." /' ~ EN .. OV - I 1k 10k 100k 1M SWITCHING FREQUENCY (Hz) 10M FIGURE 10. POSITIVE SUPPLY CURRENT VI SWITCHING FREQUENCY 105 VSUPPLY" ±15V -- ~ '\. o 104 I " - - 1 + 103 :c .s. .... .i ./ 102 .-" 10 0.1 0.01 , -200 V ~ /' V ~ .ss - ,./ -400 I-- - -(1-) I 45 85 .ss 125 TEMPERATURE ("C) FIGURE 11. I$UPPLY VI TEMPERATURE (LOG SCALE) VIN=OV VEN=OV I -800 5 I 5 45 TEMPERATURE (OC) , \ V+.15V v- .. -15V 85 125 FIGURE 12. NEGATIVE SUPPLY CURRENT vs TEMPERATURE 10-22 DG40B, DG409 Typical Performance Curves (Continued) ""- 15 l.:!: I ~ 20 "'" ~~ 10 I V+_15V V-.-15V VIN"OV VEN" OV - so so - t- CL· 10,OOOpF L VIN"SVp..p 70 - /' so ~ CI 50 40 20 5 10 o -10 / 5 45 85 125 .......... -15 -10 FIGURE 13. POSITIVE SUPPLY CURRENT VB TEMPERATURE (DG408) o 140 iI' J so \4 20 -- - t.... ~ I /"to±8V _ ±10V I-- I ±20V o -20 -16 100 jZ' 80 - - 60 ~ ~ ±15V 9: --:::: ..-.,.:::V ~!,......,c: '7 r- 120 V I 40 _ 10 S 1S 160 100 V 40 20 o -12 .. -4 0 Vo(V) 4 8 12 16 20 FIGURE 15. fDS(ON) va Vo AND SUPPLY r--.. V V+=15V V-=-15V -1--+----1 110 60 so so 9: Z' 40 Z' 70 j 30 50 20 ...... r-- / ,..., -o o 10 15 ,,'\. 12V . 15V "-", 20V t-- 22V - I 8 4 12 VoM 16 ...... ~ -- I '- +12SoC +ssoc ./ I I"'" ---- +25oC ." ~ ~-oOC / 20 -40oC -ssOC / o / V 22 .". --- ~ I'.. ",. l' .- I' t'-.... I'.. V+=12V ~=oy _ 4 8 FIGURE 18. fOS(ON) vs Vs AND TEMPERATURE (SINGLE SUPPLy) 10-23 .-.. -' Vs(V) VsM FIGURE 17. fDS(ON) VS Vs AND TEMPERATURE 10V - ....... f·15 I .., V- .. ov I I 30 f- 10 o VU7jSV \ / 130 1-_......._-11- \ FIGURE 16. fDS(ON) VB Vo (SINGLE SUPPLy) 80 i v FIGURE 14. CHARGE INJECTION vs ANALOG VOLTAGE Vs (DG408, DG409) 120 ~ / Vs(V) TEMPERATURE ("C) 9: ./ o k-_+-~*V~--F=::::::f/:"'V+.'2V ./ V- .. OV -55 70 v 30 12 DG40B, DG409 Typical Performance Curves (Continued) -150 275 .----r--.,.--.....,..---.---~-__. 250 225 -110 1-~..,l"....,..-+----1f--+--+_-_I - ! 200 175 -70 I---+--+----'~~~+--+_-_I 150 -50 1---"'-+-- 125 40L---4_ _ 100 1k ~_~~_~_---'~~~ 10k 100k 1M 10M 100 100M i\ '-."-- ~ "" ........... ...... 10 8 I 125 -'" V /' 150 - ±12 ITRANS / IoN(EN) - 110 10.... IoFFT- IoN(EN) 90 t1a ±14 180 ±18 ±20 ±22 2 I 160 /" ~ FIGURE 22. SWITCHING TIME vs V IN (SINGLE SUPPLy) I ~ RL=1kn o ~ <, "- -1 I-_ - 1o'1N) 80 V+=+15V V- .-15V REF.1VRMS ~ , .... 1oFF(EN) 3 5 4 3 VIN(V) ITRANS _ _ _ 2 15 IOFF(EN) FIGURE 21. SWITCHING TIME vs BIPOLAR SUPPLY 100 14 13 "" 170 VSUPPLyM 120 12 130 ~ . 140 r-..... FIGURE 20. SWITCHING TIME VB SINGLE SUPPLY 190 V 100 75 ±10 - ",.- ITRAN8/ 150 IoFF(EN) --- VSUPPLY(V) FIGURE 19. OFF ISOLATION AND CROSSTALK vs FREQUENCY 175 ~ IoN(EN) 11 FREQUENCY (Hz) 200 -- ITRANS ...... 4 RL-500 .- 5 10 FIGURE 23. SWITCHING TIME vs VIN (BIPOLAR SUPPLy) 102 103 104 105 10' FREQUENCY (Hz) - 107 FIGURE 24. INSERTION LOSS vs FREQUENCY 10-24 10· DG40B, DG409 Pin Description - (OG409) Pin Description - (OG408) PIN SYMBOL 1 Ao 2 DESCRIPTION DESCRIPTION PIN SYMBOL Logic decode Input (bit 0, LSB) 1 Ao Logic decode Input (bit 0, LSB) EN Enable input 2 EN Enable input 3 V- Negative power supply terminal 3 V- Negative power supply terminal 4 S, Source (input) for channel 1 4 S'A Source (Input) for channell a 5 S2 Source (Input) for channel 2 5 ~A Source (input) for channel 2a 6 S3 Source (input) for channel 3 6 S3A Source (input) for channel 3a 7 S4 Source (input) for channel 4 7 S4... Source (input) for channel 4a 8 0 Drain (output) 8 0 ... Drain a (output a 9 Sa Source (input) for channel 8 9 DB Drain b (output b) 10 S7 Source (input) for channel 7 10 S4B Source (input) for channel 4b 11 S6 Source (input) for channel 6 11 S3B Source (input) for channel 3b 12 S5 Source (input) for channel 5 12 S2B Source (input) for channel 2b 13 V+ Positive power supply terminal (substrate) 13 SIB Source (input) for channel 1b 14 GND Ground terminal (Logic Common) 14 V+ Positive power supply terminal 15 A, Logic decode input (bit 2, MSB) 15 GND 16 A, Logic decode input (bit 1) 16 A, Ground terminal (Logic Common). Logic decode input (bit 1, MSB» TRUTH TABLE DG408 TRUTH TABLE DG409 A, AI Ao EN ON SWITCH AI Ao EN ON SWITCH X X X 0 NONE X X 0 NONE 0 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 1 2 0 1 0 1 3 1 0 1 3 0 1 1 1 4 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 NOTES: 1. VAH Logic "1""'2.4V 2. VAL Logic -0" SO.8V 10-25 DG40B, DG409 Test Circuits +15V +15V = - - = SWITCH OUTPUT VD - - - SWITCH OUTPUT Voa - FIGURE 25A. F1GURE25B. 'R<20na 'F<20n. 3V LOGIC INPUT OV VSl SWITCH OUTPUT VD 5, ON O.IVSl OV Vsa 'TRANS Sa ON 'TRANS FIGURE 25C. FIGURE 25. TRANSITION TIME +15V +1SV Ao AI -'2 Ao -SV 52- 5• - - = -5V AI SWITCH OUTPUT VD = - - FIGURE 26A. FIGURE26B. 'R <20n. LOGIC INPUT 'F<20ns 3V--50% 50% OV OV SWITCH OUTPUT VD Vo FIGURE26C. FIGURE 26. loN(ENI'toFF(EN) 10-26 SWITCH OUTPUT Voa DG408, DG409 Test Circuits (Continued) +15V +2.4V LOGIC INPUT V+ EN ALL SAND DA ±10V Ao OV tR<20na tF<20na 'u- Vs SWITCH OUTPUT VD \ / 3V SWITCH OUTPUT VD OV FIGURE 27B. FIGURE 27A. FIGURE 27. BREAK-BEFORE-MAKE INTERVAL +15V LOGIC 3V - - INPUT OV D 1-_--0 VOUT SWITCH OUTPUT _ON~_/ OFF AVO IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER ERROR, Q Q=CLxAVO FIGURE 28A. FIGURE 28B. FIGURE 28. CHARGE INJECTION OV +15V OV +15V VIN VOUT D t - o -......~ lkn SIGNAL GENERATOR SIGNAL GENERATOR V- ANALVZERt-------------------------~ OFF ISOLATION SI Sx I I S. A2 AI EN V+ Vour D Ao V- ANAL~Rt-----------------------~ VOUT 20LOO ~ IN CROSSTALK FIGURE 29. OFF ISOLATION = V OUT 20LOG - V - IN FIGURE 30. CROSSTALK 10-27 DG40B, DG409 Test Circuits (Continued) OY +15Y _.a{ YOUT D t-o--.......~ SELECT SIGNAL GENERATOR OY +1SY EN Y+ Aa SI I I S, AI / f IMPEDANCE ANALYZER Au D ¥- - ANALYZERt-------------------------~ INSERTION LOSS = YOUT 20 LOG - y IN FIGURE 31. INSERTION LOSS FIGURE 32. SOURCEIDRAIN CAPACITANCES Typical Applications Overvoltage Protection v+ A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 33). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or belOW the normal V+ or Vvalue. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference Vs - (V-) doesn't exceed -44V. The addition of these diodes will reduce the analog Signal range to 1V below V+ and 1V above V-, but it preserves the low channel resistance and· low leakage characteristics. r-C""::;'+--+--~ 0--+--0 D ¥- Typical application information is for Design Aid Only, not guaranteed and not subject to production testing. FIGURE 33. OVERVOLTAGE PROTECTION USING BLOCKING DIODES 10-28 DG40B Die Characteristics DIE DIMENSIONS: 1BOOJ.1lTl x 3320llm x 4B5 ± 251lm METALLIZATION: Type: SiAl Thickness: 12kA ± 1kA GLASSIVATION: Type: Nitride Thickness: BkA ± 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm 2 Metallization Mask Layout DG408 EN Ao (2) (1) Ai (16) Az QND (15) (14) NC V-(3) (13)V+ S1 (4) (12)S5 tn (11)S6 ~(5) NC (8) o 10-29 (9) (10) S. S7 It ~oJ a. 5 :l :::& I ! DG409 Die Characteristics DIE DIMENSIONS: 1800J.1l" x 3320J.1l" x 485 ± 25ILm METALLIZATION: Type: SiAl Thickness: 12kA± 1kA GLASSIVATlON: Type: Nitride Thickness: 8kA ± 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm 2 Metallization Mask Layout DG409 EN Ao AI (2) (1) (16) NC GND (15) NC (14)V+ (13) SIB (12)~B (11) S3B 10-30 DG458, DG459 Single 8-ChannellDifferential 4-Channel Fault Protected Analog Multiplexers PRELIMINARY December 1993 Features Description • Fault and Overvoltage Protection The DG458 Single 8-Channel and DG459 Differential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular IH5108 and IH5208 series devices. They each include an array of eight analog switches, a series N-channeVP-channeVN-channel fault protection circuit, a TTUCMOS compatible digital decode circuit for channei selection, a voltage reference for logic thresholds and an ENABLE input for device selection when several multiplexers are present. • ON-Resistance < 1.Sk.Q (+2S0C) • Low Power Consumption (Po < 3mW) • Fast Switching Action - tA < SOOns - tONlOFF(EN) < 2S0ns • Fail Safe with Power Loss (No Latch-Up) • Upgrade from IHS10811H5208 • TTL, CMOS Compatible Logic The DG458 and DG459 feature lower Signal ON resistance (4500 typical) and faster switch transition time (200ns typical) compared to the IH5108 or IH5208. The improvements in the DG458 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Applications • Data Acquisition Systems • Audio Switching Systems • Automatic Testers • Hi-Rei Systems The 44V maximum voltage range permits controlling 20V peak-ta-peak signals, while withstanding continuous overvoltages up to ±35V, providing an open fault circuit. • Sample and Hold Circuits • Communication Systems • Analog Selector Switch The analog switches are bilateral, break-before-make, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. Ordering Information PART NUMBER DG4580J TEMPERATURE RANGE -40"C to +85OC PACKAGE 16 Lead Plastic 01 P OG458DY -4O"e to +85°e 16 Lead sOle (W) DG458AKl883 -55OC to +125"e 16 Lead Ceramic DIP DG459DJ -40"C to +85OC 16 Lead Plastlc DIP DG4590Y -40"C to +85°C 16 Lead SOIC (W) OG459AKI883 -55OC to +125°C 16 Lead Ceramic DIP Pinouts 00458 (CDIP, PDIP, SOIC) TOP VIEW 00459 (CDIP, PDIP, SOIC) TOP VIEW CAUTION: These devices are sensHlve to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-31 File Number 3280.1 DG458, DG459 Functional Block Diagrams DG458 r. -..-.-.;:::===::;---1i o-t-<~,.O. -.-...1. IN1 OUT IN2 DECODER! DRIVER •• • IN8 L................... * DIGITAL INPUT PROTECTION DG459 IN1A OUTA •• IN4A •• IN1B OUTB • IN4B ~ ...................... DECODER! DRIVER * DIGITAL INPUT PROTECTION 10-32 Specifications DG458, DG459 Absolute Maximum Ratings Thermal Information V+toV-........................................... +44V V+toGND •••••••••••••••••••••.••.••.•.•.••.•.••.• 22V v- to GND ••••.•••••••••.•.••.••••••••••••••••••.••. -25V Digital Input, VEN , VA .....................(V-) -4V to (V+) +4V Analog Input Overvoltage wlPrmer On, Vs •••• (V-) -20V to (V+) +20V Analog Input Overvoltage wlPrmer Off, Vs .•.••.••••• -35V to +35V Continuous Current, S or 0 ........................... 20mA Peak Current, S or 0 ••••.••••••.•..•.••••..••••••••• 4OmA (Pulsed lrns, 10% Duty Cycle Max) Storage Temperature Range (0 Suffix) ••.••.•.• -65°C to +125°C Lead Temperature (Soldering lOs) •••••••••.•••••••••• +3oooC Thermal Resistance 9JA 9JC Plastic DIP Package................ l00"Cm Ceramic DIP Package............... 700C1W leocm SOIC Package.. .. .. • .. .. .. .. • .. .. • loooCm Operating Temperature (0 Suffix) .•........••••• -4O"C to +85OC Ceramic DIP ............................ -55OC to +125°C Junction Temperature (0 Suffix) •••••••••.•••••••••••• +150°C Ceramic DiP •••••••••••..••.••••..•••••••••••.• +175°C CAUTION: S/nIsses above those listed in "AbBoIute Maximum RaUngs" may cause permanent damage to the davice. This is a s/nlss only /Bling and opetatJon of the dsvice at these or any other condiUons above those indicated in the opfI/8tJona/ secUons of this specification is not ImpHed. Electrical Specifications v+ = +15V, v- = -15V, VAL = O.BV, VAH = 2.4V, Unless Otherwise Specified DSUFFIX -40·C TO +85"C PARAMETER (NOTE 1) TEMP TEST CONDITIONS (NOTE 3) MIN (NOTE 2) TYP (NOTE 3) MAX UNITS DYNAMIC CHARACTERISTICS Transition Time, tA Break-Belore-Make Time, teeM Enable Tum-ON Time, IoN(EN) See Figure 15 +25°C - 200 500 ns See Figure 16 +25°C 10 45 See Figure 17 +25°C - - ns 140 250 ns - 500 ns 50 250 ns - 500 ns - lIS Full +25°C Enable Tum-OFF Time, IoFF(EN) Full Settling Time, Is To 0.1% +25°C - To 0.01% +25°C OFF Isolation VEN =OV,RL =lkn CL= 15pF Vs = 3V RMS, I = 100kHz (Note 7) +25OC - Logic Input CapaCitance, C1N f= lMHz +25°C - 1.2 3.5 90 - lIS dB - 5 - pF +25°C DG45B +25°C - 15 pF +25°C - - DG459 DG458 +25OC - DG459 +25OC - Source OFF Capacitance, CS(OFF) 5 pF Drain OFF CapaCitance, CO(OFF) 10 - pF 40 - pF Drain ON Capacitance, CD(ON) 35 - pF ANALOG SWITCH Analog Signal Range, VANALOG Note 4 FUll -10 Drain-Source ON ReSistance, RoS(oN) Vo = ±9.5V,l s = -lmA (Note 5) +25°C - Vo = ±5V, Is = -lmA (Note 5) +25OC Vo = OV, Is = -lmA (Note 6) +25°C ROS(ON) Matching Between Channels, ARoS(ON) Full Source Off Leakage Current, IS(OFF) VEN = OV, Vs = ±10V, Vo= 'F10V Drain Off Leakage Current, IO(OFF) 10-33 - - 10 V 0.45 1.5 kn kn - I.B 180 400 n 6 - % +25°C -1 0.03 1 nA Full -50 - 50 nA Specifications DG458, DG459 Electrical Specifications V+ = +15V, v- =-15V, VAL = 0.811, VAH = 2.4V, Unless Otherwise Specified (Continued) .DSUFFIX ""DOC TO +BSOC PARAMETER (NOTE 1) TEMP TEST CONDITIONS (NOTE 3) MIN (NOTE 2) TVP +25°C -1 0.1 Full -200 +25OC -2 Full -100 Full -50 - +25OC -5 0.1 Full -200 (NOTE 3) MAX UNITS ANALOG SWITCH (Continued) VEN =OV, Vs = +10V, Vo =±10V 00458 DG459 Differential Off Drain Leakage Current, IOIFF DG459 Only 0.1 - 1 nA 200 nA 2 nA 100 nA 50 nA Drain On Leakage Current, IOlON) DG458 Vs=Vo=±10V VAL = 0.8V, VAH = 2.4V Sequence Each Switch On DG459 +25°C -5 Full -100 0.05 - 5 nA 200 nA 5 nA 100 nA V DIGITAL CONTROL Input Low Threshold, VAL Full - - 0.8 Input Low Threshold, VAL Full 2.4 - V Full - - -1 1 jiA 0.02 VA =2.4V or 0.3V Logic Input Control, IA FAULT Output Leakage Current (With Overvoltage), IO(OFF) Vs = ±33V, Vo = OV (See Figure 14) +25OC - nA -2000 2000 nA Input Leakage Current (With Overvoltage),IS(OFF) Vs =±25V, Vo = ±10V (See Figure 14) - - Full +25OC -10 0.005 10 jiA Input Leakage Current (With Power Supplies Off), IS(OFF) VA =±25V, Vsups=OV Vo=Ao= A, =~= EN =OV +25°C -5 0.001 5 jiA VEN =High or Low VA =OV +25°C - 0.05 Full +25°C -0.1 -0.01 Full -0.2 +25°C ±4.5 POWER SUPPLIES Positive Supply Current, 1+ Negative Supply Current, IPower Supply Range for Continuous Operation - 0.1 rnA 0.2 rnA - rnA - rnA ±18 V NOTES: 1. Full = as determined by the operating temperature suffix. 2. Typical values are for Design Aid Only, not guaranteed nor subject to production testing. 3. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In this data sheet. 4. When the analog signal exceeds the +13.5Vor -12V ROS(ON) starts to rise until only leakage currents flow. 5. Electrical Charecteristics such as ROS(ON) change when supplies other than ±15V are used. RDS (ON) MAX - RDS (ON) MIN 6. dR DS (ON) = ---'-----:-.;:;-R----;:A""V;;;E:--'-a OS (ON) 7. Worst case is channel 4 due to close proximity of input and output leads of package. This parameter varies with package style. 10-34 DG458, DG459 Typical Performance Curves +25°C, Unless Otherwise Specified 1m 100" g w ~ cC w .......... :::0 '" 10" w 1" 10n f-oo- 1n OPERAnNG RANGE -40 r-of-- 1n "-""" 10P -30 -20 -10 0 10 20 INPUT VOLTAGE (V) 30 40 OPERAnNG RANGE f--~ 100P "-""" 1P -50 50 -40 ~~ ["\... -30 -20 -10 0 10 20 INPUT VOLTAGE (V) 30 40 50 FIGURE 2. OFF CHANNEL LEAKAGE CURRENT vs INPUT VOLTAGE 2000 V+. +15V, V-. -15V 1600 100p g w ~cC 0 10n ... '" 1n ~ ~ h IIIII! -40 -30 -20 -10 0 10 20 INPUT VOLTAGE (V) 30 ~ o 50 40 -20 -15 FIGURE 3. OUTPUT LEAKAGE VI OFF CHANNEL OVERVOLTAGE " -10 IJ "- 25 +12SOC ~ 100~~ 0 2.5 5.0 ±15V :l20V I I I 15 20 25 V+ .. +15V, V- .. -15V 7.5 IS(OFF) 10 ",.. 5 ",1' 0 ',- i"""'" t..,....- ...... ~-5 I -10 -15 ...- ~ - ID(OFF) -IDlON) -20 O~--~--~--~--'~--'~--'----'----' -2.5 ~~10V 15 iw -5.0 .J -5 0 5 10 INPUT VOLTAGE (VI 20 -7.5 iJ ...... ±lV SUPP UES FIGURE 4. ROSION) VI INPUT VOLTAGE V+ .. +15'1, V· .. -15V -10 " ., 800 400 v ...... "- ~ 1p -1p -50 ...... w U1200 / 10p I!: :::0 100n !; -~ 100p :::0 1" ~~ 100n FIGURE 1. INPUT LEAKAGE vs INPUT VOLTAGE w 10" g 1p -50 ....... - V+. +15V, V-. -15V 100" 10p g , 1m V+.V-.OV -25 -15 10 VDM FIGURE 5. RDS(ON) VI VD AND TEMPERATURE -12 -II -6 -3 0 3 Vs. VD(VI 6 II FIGURE 6. LEAKAGE CURRENT VI Vs. VD 10-35 12 15 DG458, .DG459 Typical Performance Curves +250 C. Unless Othl!rwlse Speclfled (Continued) ~Or---~~---r---------'----------, 10 V+ .. +15V. y... ·15V Vs. VD=±10V IO(ON) ~O~----~~~------- h ..... ~ P"" 1s(0FF) IO(OFF) ......~ ..... ~1~~--------~~~~--~----------~ ..s !II = ~ 120 ~--------~------- ~ P' 0.10 ~~--------~--~----~----------~ 40L-________ ". 0.01 -55 -35 ·15 -5 25 45 65 TEMPERATURE rC) 85 105 ±5 125 0 - 200 ~ ..s 160 1/1 w ::Ii ~ 120 ...- ~ .......... ~ P"'" ~ ~ ~ 40 o -55 .......... ~ - ~F)Ei;,I ·15 ~ w ..., !i -80 ":z:: tr: -40 C I ·70 "'", U -50 10k CL,"1nF :-r: ............. 85 105 -60 ·10 125 ./ - CL-10nF- I -605 ANALOG INPUT (V) FIGURE 10. o.NJ vs Vs ..... 'IIII " :::- ... CROSSTALK' -60 I.... V+ .. +15V. y...·15V RL·1kn '" ' ... '" -30 w -50 -5 25 45 65 TEMPERATURE rC) ·110 ! V+ .. +15V. V· .. ·15V l'OFjN-35 ~ ±20 U' .!!: z -20 FIGURE 9. SWITCHING TIMES VB TEMPERATURE ·100 ±15 ·10 T~ ~ l.,...-- V ~ ±10 FIGURE 8. SWITCHING TIMES (~ANS. toN. toFF> VS ±V SUPPLIES V+ .. +15V. y..oo ·15V 240 T,OFF)EN ________ __________ ±VSUPPLY (V) FIGURE 7. LEAKAGE CURRENT VB TEMPERATURE 2~ ~ IIII I 1 OFF ISOLATION 1'....1111111 Nitttit 100k 1M FREQUENCY (Hz) 10M ±VSUPPLY (V) FIGURE 11. OFF ISOLATION AND CROSSTALKvS FREQUENCY3 FIGURE 12. LOGIC INPUT SWITCHING THRESHOLD VB ±V SUPPLIES 10·36 10 DG458, DG459 Pin Description PIN SYMBOL 00458 TRUTH TABLE DESCRIPTION DG458 ~ Al At, EN ON SWITCH X X X 0 NONE 1 Ao Logic decode input (bit 0, LSB) 0 0 0 1 1 2 EN Enable input 0 0 1 1 2 3 v- Negative power supply terminal 0 1 0 1 3 4 SI Source (input) for channel 1 5 S2 Source (input) for channel 2 6 Ss Source (input) for channel 3 7 S4 Source (input) for channel 4 8 0 Drain (output) 9 Sa Source (input) for channel 8 10 S7 Source (input) for channel 7 11 S6 Source (input) for channel 6 12 S5 Source (input) for channel 5 13 V+ Positive power supply terminal (substrate) 14 GND 15 16 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 00459 TRUTH TABLE Al At, X Ground terminal (Logic Common) ~ Al EN ON SWITCH X· 0 NONE 0 0 1 1A,1B Logic decode input (bit 2, MSB) 0 1 1 2A,2B Logic decode input (bit 1) 1 0 1 3A,3B 1 1 1 4A,4B DG459 1 Ao Logic decode input (bit 0, LSB) 2 EN Enable input NOTES: 1. VAH Logic "1" ---1 -5V 51 A:.t -5V EN DG506A (NOTE 1) DG507A (NOTE 2) =>-----. 52 THRU 516 - A2 Ao 511. THRU SeA........ DA. S2B THRU Sas Al Ao EN SWITCH OUTPUT Vo De 50n EN 11Ul 50n J 11Ul 35PF - - - - - SWITCH OUTPUT Vo <>-..---_-0 DB ....... -=- J 35pF NOTE: 1. Similar conneclions for DG50BA NOTE: 2. Similar conneclions for DG509A FIGURE 4A. ENABLE toN and toFFSWlTCHING TIME TEST CIRCUrr FIGURE 4B. ENABLE toN and toFF SWrrCHING TIME TEST CIRCUrr 3V OV ___ OV EN .I SWITCH OUTPUT Vo FIGURE 4C. ENABLE toN and toFF SWITCHING TIME WAVEFORMS +15V +2.4V V+ EN ALL 5 AND DA +5V 3V - - - - , . - - - - - - _ \ LOGIC INPUT OG506A DG507A --II ov _ _ L- (NOTE 3) r--_--<>--t A:.t GND SWITCH OUTPUT Vo SWITCH OUTPUT VD DB V11Ul -=- J 35pF OV_~-i. ~ tR <20ns tF< 20n8 NOTE: 3. Similar connections for DG50BA. DG509A. FIGURE 5A. toPEN (BREAK-BEFORE-MAKE) SWITCHING TIME TEST CIRCUIT FIGURE 5B. toPEN (BREAK-BEFORE-MAKE) SWITCHING TIME WAVEFORMS 10-47 DG506A, DG507A, DG50BA, DG509A Typical Performance Curves (Continued) +15V +15V Vo. V+ .------1. EN ,...------1 EN DG506A DG507A (NOTE 1) (NorE2) A1 Ao LOGIC INPUT D J Vo J LOGIC INPUT 1000pF 1000pF - - - - NOTE: 1. Similar connections for DG508A NOTE: 2. Similar connections for DG509A FIGURE 6A. CHARGE INJECTION TEST CIRCUIT .FIGURE 68. CHARGE INJECTION TEST CIRCUIT' 3V EN o Vo IN0 is the measured voltage error due to charge Injection. The error voltage in Coulombs Is Q = CL x INa- FIGURE 6C. CHARGE INJECTION WAVEFORMS 10·48 DG506A, DG507A, DG508A, DG509A Truth Tables DG507A DG506A A3 A2 Al Ao EN ON SWITCH A2 Al Ao EN ON SWITCH X X X X 0 None X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 2 0 0 1 1 2 0 0 1 0 1 3 0 1 0 1 3 0 0 1 1 1 4 0 1 1 1 4 0 1 0 0 1 5 1 0 0 1 5 0 1 0 1 1 6 1 0 1 1 6 0 1 1 0 1 7 1 1 0 1 7 0 1 1 1 1 8 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 Logic "0" = VAL, VENL S 0.8V, Logic "1" = VAH , VENH ;" 2.4V. DG508A DGS09A A2 Al Ao EN ON SWITCH Al Ao EN ON SWITCH X X X 0 None X X 0 None 0 0 0 1 1 0 0 1 lA,lB 0 0 1 1 2 0 1 1 2A,2B 0 1 0 1 3 1 0 1 3A,3B 0 1 1 1 4 1 1 1 4A,4B 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 Ao,A 1, EN Logic ·1" =VAH ;" 2.4V, Logic "0" =VAL S 0.8V Ao,A h A2 , EN Logic "1" = VAH ;" 2.4V, Logic "0" = VAL S 0.8V 10-49 DG506A Die Characteristics DIE DIMENSIONS: 3B10j.UTl x 2770j.UTl METALLIZATION: Type: AI Thickness: 10kA± 1kA GLASSIVATION: Type: PSG/Nitride . Thickness: PSG: 7kA ± 1.4kA. Nitride: BkA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DGS06A NC NC V+ D V· SI6 S. SI5 S7 SI4 Sa SI3 S5 SI2 S4 SI1 S3 SIO S2 Sa SI 10·50 DG507A Die Characteristics DIE DIMENSIONS: 3810J.ll11 x 2770~m METALLIZATION: Type: AI Thickness: 10kA± 1kA GLASSIVATION: Type: PSGINitride Thickness: PSG: 1kA ± 1.4kA. Nitride: 8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DG507A SaB SSA S7B s"A S6B SeA SSB SSA S4B S4A S3B S3A S2B S2A SIB, SIA en 10·51 II: W >< W ..J Q. 5:::I ::& DG50BA Die Characteristics DIE DIMENSIONS: 3100!lm x 2083!lm METALLIZATION: Type: AI Thickness: 10kA ± 1kA GLASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA ± l.4kA, Nitride: akA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DG508A 10-52 DG509A Die Characteristics DIE DIMENSIONS: 3100j.llT1 x 2083Jlm METALLIZATION: Type: AI Thickness: 10kA ± 1kA GLASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA ± 1.4kA. Nitride: akA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DGS09A U) v+ a:: w >< w .oJ v· SIB Q. 5::::I ::::i! 10-53 DG526, DG527 DG528, DG529 Analog CMOS Latchable Multiplexers December 1993 Features Description • Direct RESET The DG526, 00527, 00528, and DG529 are CMOS monolithic 16 channeVdual 4 channel analog multiplexers. Each device has on-chip address and control latches to simplify design in microprocessor based applications. The 00526 uses 4 address lines to control ~s 16 channels; the 00527, DG528 both use 3 address lines to control their 8 channels; and the 00529 uses 2 address lines to control its 4 channels. The enable pin is used to enable the address latches during the WR pulse. It can be hard wired to the logic supply if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used to clear all latches regardless of the state of any other latch or control line. The WR pin is used to transfer the state .of the address control lines to their latches, except during a reset or when EN is low. • TIL and CMOS Compatible Address and Enable Inputs • 44V Maximum Power Supply Rating • Break-Before-Make Switching • Alternate Source Applications • Data Acquisition Systems • Communication Systems • Automatic Test Equipment A channel in the ON state conducts signals equally well in both directions. In the OFF state each channel blocks voltages up to the supply rails. The address inputs, WR, RS and the enable input are TIL and CMOS compatible over the full specified operation temperature range. • Microprocessor Controlled System Ordering Information PART NUMBER TEMPERATURE PART NUMBER PACKAGE DG526AK -550 C to +125°C 28 Lead Ceramic DIP DG526AKl883B -55°C to +125°C DG526BK -25°C to +85°C DG526BY TEMPERATURE PACKAGE DG528AK -55"C to +125°C 18 Lead Ceramic DIP 28 Lead Ceramic DIP DG528AKI883B -55"C to +125°C 18 Lead Ceramic DIP 28 Lead Ceramic DIP DG52IlBK -25°C to +85°C 18 Lead Ceramic DIP -25°C to +85°C 28 Lead Plastic SOIC DG528BY -25°C to +85°C 18 Lead PlastiC SOIC DG526CJ O"C to +70"C 28 Lead Plastic DI P DG528CJ o"c to +70"C 18 Lead Plastic DIP DG526CK O"C to +70"C 28 Lead Ceramic DIP DG528CK O"C to +70"C 18 Lead Ceramic DIP DG526CY O"C to +70"C 28 Lead PlastiC SOIC DG528CY O"C to +70"C 18 Lead Plastic SOIC DG527AK -55°C to +1·25°C 28 Lead Ceramic DIP DG529AK -55"C to +125°C 18 Lead Ceramic DIP DG527AKl883B -55"C to +125°C 28 Lead Ceramic DIP DG529AKI883B -55"C to +125°C 18 Lead Ceramic DIP DG527BK -25°C to +85°C 28 Lead Ceramic DIP DG529BK -25°C to +85°C 18 Lead Ceramic DIP DG527BY -25°C to +85°C 28 Lead Plastic SOIC DG529BY -25"C to +85°C 18 Lead Plastic SOIC DG527CJ O"C to +70"C 28 Lead Plastic Dll> DG529CJ O"C to +70"C 18 Lead Plastic DIP DG527CK O"C to +70"C 28 Lead CeramiC DIP DG529CK O"C to +70"C 18 Lead Ceramic DIP DG527CY O"C to +70"C 28 Lead PlastiC SOIC DG529CY O"C to +70"C 18 Lead Plastic SOIC CAUTION: These dElI/ices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-54 File Number 3139 DG526, DG527, DG528, DG529 Pinouts DG526 (PDIP, SOle) TOP VIEW 00527 (PDIP, SOle) TOP VIEW DG528 (PDIP, sOle) TOP VIEW DG529 (PDIP, sOle) TOP VIEW 10-55 DG526, DG527, DG528, DG529 Functional Diagrams D0527 DG526 16 CHANNEL SINGLE ENDED MULTIPLEXER v+ V- T T DIFFERENTIAL 8 CHANNEL MULTIPLEXER GND T ,,L :'" I I I I I I I I I I I I I I I I I I I I I I I I I I I -<~ ~ I I I I I I I I I I I I I I • • I · · ··· · · · ·· L: · · ·· ·: ··· :: · · · ·· .A"_: · · : · · · · • · : ·• • • • • • • •• · · · . ·· ·· • •• · /_:• •• • • •• · · · • • : ···· L: • • ·· ·• • • • : ·· · · · · .....-: -{- : : L: /_ I ..r_ : /- 0_ I I 1"""'"•• I • H I I I • • • • • •• • •• I I I I I I I I I I I DECODER LOGIC AND LATCHES l> ~ ~ ~ 0 v· /- ..r_ I I ···· • ·· • ·: ·· ,y-• · H •I r! I 0 I I I I 0 I I ,}- ~. I r:o- 0_ ~ EN fo- ·· · · · r!,. • · • · ·· • ··· · ··· ·· • ··: ••• ,y-: ·· · J._· • :0: : J._ · • · · · J.-- • : ·· ··· • ·· ··· ··· ·•• ·· · ... -{I L I I I I I I I • •• I I I I I _t I I I I I I J. I • • I I I I I I I I I I -0 I I I I I I I ...:0 DECODER LOGIC AND LATCHES ~ l> l> l> EN DG528 8 CHANNEL SINGLE ENDED MULTIPLEXER v+ T L_ /,- ... GND L_ •• • • • •• I I T I I I J_ : 0- I v· ' T 0 1_1or--' ,,- : v+ DG529 DUAL 4 CHANNEL MULTIPLEXER GND V- GND Slo-f---------------------------~o-~ SlAO-f---------------------------~o-_, ~~-------------------v~o-~~ ~A~~--------------~,~~--~__+ S3o_~----------------~~o--4_~~_+ S4o-~--------------~c~_r--+_~~_t S3Ao-t---------~;0_------~------~--_t D S4A S5 SlBO-f-~------~~------~------~"o__, ~ ~~~~----~----~,~----~~ ~ S. ~~~----~~~----~----~~~ WR S4Bo-~~C~----~~------~------~---J As t--t-O As WR -t---t EN 10-56 DG526, DG527, DG528, DG529 Schematic Diagrams LOGIC INTERFACE AND LEVEL SHIFTER v+~~~----+-----~--~ LOGIC t--I---'-I".... TRIP POINT REF GND AX,EN, Ri, WFi v- ~--JJ:j=OV, RS=OV, WR=OV -10 -10 -30 VA=OV -30 Analog Signal Range, VANALOG Note 7 -15 Drain Source ON Resistance, ROS(ON) Vo = tl0V, VAL = 0.8V, VAH = 2.4\1, Is = -200jlA, Sequence Each Switch ON Source Off Leakage Current, IS(OFF) VEN=,oV Drain OFF Leakage Current, ID(OFF) VEN=OV - - - 30 - -30 - -30 - -30 +15 - 500 - 50 - - - jIA 30 jIA - jIA - jIA jIA - - jIA - - % 500 0 - nA 300 nA 200 nA 200 nA 100 nA 300 nA 200 nA 200 nA 100 nA SWITCH 00526 00527 00528 DG529 Drain ON Leakage Current, IO(ON) DG526 DG527 DG528 DG529 Sequence Each Switch On, VAL = 0.8V, VAH = 2.4V (Note 5) - - Vs=tl0V, Vo= + 10V -50 - Vs =tl0V, Vo =+10V -300 Vs= +10V, Vo=t10V -200 VO=VS(ALl.) =tl0V -200 -100 -300 -200 -200 -100 10-60 - - - 300 -300 200 -200 200 -200 100 -100 300 -300 200 -200 200 -200 100 -100 - Specifications DG526, DG527, DG528, DG529 Minimum Input Timing Requirements Over Full Temperature Range MIN. UNITS WRITE Pulse Width. tww PARAMETER WR. See Rgure 1 MEASURED TERMINAL 300 ns A. EN Data Valid After WRITE (Stabilization Tme). low 180 ns A. EN Data Valid After WRITE (Hold Time). two Ao. A1• (A:!). EN. WR; See Figure 1 Ao. A1• (A:!). EN. WR; See Figure 1 30 ns RESET Pulse Width. 11m RS. (Note 6). Vs 500 ns =SV. See Figure 2 NOTES: 1. Signals on Vs. Vo or VIN exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings. 2. Typical values are for design aid only. not guaranteed and not subject to production testing. 3. The algebraic convention whereby the most negative value Is a minimum. and most positive value Is a maximum. is used In this datasheet. IVsl 4. OFFlsolation = 20 - . where Vs IVol =Input to OFF switch. and Vo =output due to Vs. S. ID(ON) is leakage from driver into 'ON" switch. 6. Period of Reset (RS) pulse must be at least 5011S during or after power ON. 7. Parameter not tested. Parameter guaranteed by design or characterization. Waveforms and Test Circuits 3V WR , &~l=-=! I{ \1.SV J 0 -Iww- I-- lOW 3V Ao. A1. (A:zl EN 0 ) Iwo - 2.0V O.8V C FIGURE 1. WR TIMING WAVEFORMS Va SWITCH OUTPUT IoFF(RS) O.8Va OV FIGURE 2. RSTIMING WAVEFORMS 10-61 ~ DG526, DG527, DG52B, DG529 Waveforms and Test Circuits (Continued) +15V +2.4V +15V +2.4V v+ ~N 00528- iii v+ EN SI DG529- iii SzTHRUS, Ao SzA THRU S4A, DA Sz.,. AND SaB S, S4B Ao AI Az SWITCH OUTPUT VD D SIB SWITCH OUTPUT VDB D& AI 1Mn IMn J35pF 35PF = - - - FIGURE 3A. tTRANSIlJON - - J SWITCHING TIME TEST CIRCUIT • Similar connections for 00526 - - FIGURE 3B. tTRANSl110N SWITCHING TIME TEST CIRCUIT • Similar connections for DG527 3V 60% 0'--_ _ VSI O.BVSI SWITCH OUTPUT VD ~--+"\ o O. 8Vsa Vsa TRANSITION SION TRANSITION LOGIC INPUT tR<20na tF<20na FIGURE 3C. 3V 50% roo roo 0 tTRANSInoN SWITCHING TIME WAVEFORM , I J +1SV +2.4V V+ EN \ iii SWITCH OUTPUT VD DG529DG529 ALL SAND DA +5V VS 80% OV roo .... SWITCH OUTPUT '1kn _ LOGIC INPUT 1R<20na tF<20ns FIGURE 4A. IoPEN (BREAK-BEFORE-MAKE) SWITCHING TIME WAVEFORM J VD 35pF FIGURE 4B. IoPEN (BREAK-BEFORE-MAKE) SWITCHING TIME TEST CIRCUIT • Similar connections for 00526, DG527 10-62 DG526, DG527, DG528, DG529 Waveforms and Test Circuits (Continued) +15V +15V ,..--t---...... EN r--_-_~ EN .flV SI !It THRU Sr SI A THRU S4A, 0A. S2110 Sa........_----. S4B t-c--..., Ao Al At EN SIB OG52\l· 00528· SWITCH OUTPUT SWITCH OUTPUT 0 Al VD EN 500 lkr.l VDB 500 lkr.l J J 35PF 35PF - - - - - FIGURE 5A. ENABLE toN AND toFF SWITCHING TIME TEST CIA- - - FIGURE 5B. ENABLE toN AND toFF SWITCHING TIME TEST CIRCUlT CUIT • Similar connections lor 00526 • Similar connections lor DG527 3V 50% 0'--_ _.1 SWITCH OUTPUT VD 0 ~--....,_ O.lVo O.BVo Vo Va EN IR < 20l1li IF < 20l1li FIGURE SC. ENABLE toN AND toFF SWITCHING TIME WAVEFORMS +15V +2.4V V+ 3V EN ~ g:sg. SIOR SIB +5V Ao. AI. (At) REMAINING SWITCHES SWITCH OUTPUT H>----. Vo ....---o-liiS O.2Vo Wii OV - - - - - - - - - SWITCH OUTPUT Da(O) Device must be reset prior to applying iNA pulse. lkr.l _ J Vo 35pF FIGURE 6B. WRITE toN SWITCHING TIME TEST CIRCUIT FIGURE 6A. WRITE toN SWITCHING TIME WAVEFORMS • Similar connections lor 00526. DG527 10-63 DG526•. DG527. DG528. DG529 Waveforms and Test Circuits (Continued) . +15V EN 00528 DG528· V+ SI OR SIB +5V AgAl. (-'2) REMAINING SWITCHES SWITCH OUTPUT Va .. ... 0.8Vo . SWITCH OUTPUT Va Os (D) AS AS lkn -J 35PF FIGURE 7B. RESET toFF SWITCHING TIME TEST CIRCUIT • Similar connections for DG526. 00527 FIGURE 7A. RESET toFF SWITCHING TIME WAVEFORMS +15V V+ AS AgAl.(A:!) 3V +2.4V OG528 0G529· EN o ·· ·· x - D Va --~ Va EN iN0 is the measured voltage error due to charge injection. The error voltage in Coulombs is Q CL X INo- = FIGURE 8A. CHARGE INJECTION WAVEFORMS FIGURE 8B. CHARGE INJECTION TEST CIRCUIT • Similar connections for DG526. 00527 550 500 400 r 320 r (0) 1o.-200jIA VEN-+5V 350 450 , 400 ~ 350 Z' 300 I!! 250 II: 200 e. 280 ... (8) ~240 (A) 1 200 io"""" 11:150 150 (A) (8) (C) (0) 100 50 o ~) V+,,+15V Y.=-15V VEN-2.4V 1o--200"A - ~ I - I .",.,. jl0VSIG.v.--: ~ ~ ".,.- +10VSIGNALS ~ 120 V+ .. +lSY, V- _ -15V V+ _ +12V. Yo .. -12V _ V+ _ +10V. Yo .. -10V V+_+7.5V. V-.-7.SV LlJIIIIII- 80 40 o -15 -13 -11 -8 -7 -5 -3 -1 0+1 +3 +5 +7 +9 +11 +13 +15 ANALOG SIGNAL VOLTAGE (V) FIGURE 9. RDS(ON) VI ANALOG SIGNAL VOLTAGE VI SUPPLY VOLTAGE -55 -25 0 +25 +45 +70 yEMPERATURE("C) +100 +125 FIGURE 10. TYPICAL RDS(oN) VARIATION WITH TEMPERATURE 10-64 DG526, DG527, DG528, DG529 Truth Tables 00527 00526 ~ ~ AI Ao EN WR RS ON SWITCH ~ AI Ao EN WR Latching X X X X X IJ 1 Maintains Previous Switch State Latching X X X X J Reset X X X X X X 0 None (LatchesCleered) Reset X X X X X Transparent Operation X X X X 0 0 1 None X X 0 0 0 0 1 0 1 1 Transparent Operation X 0 0 0 0 1 0 0 0 1 1 0 1 2 0 0 1 0 0 1 0 1 0 1 3 0 1 0 0 1 1 1 0 1 4 0 1 0 1 0 0 1 0 1 5 1 0 0 1 0 1 1 0 1 6 1 0 0 1 1 0 1 0 1 7 1 RS ON SWITCH 1 Maintains Previous Switch State 0 None (LatchesCleared) 0 1 None 0 1 1 1 0 1 2 0 1 0 1 3 1 1 0 1 4 0 1 0 1 5 1 1 0 1 6 1 0 1 0 1 7 1 1 1 0 1 8 0 1 1 1 1 0 1 8 1 1 0 0 0 1 0 1 9 Logic "1" = VAH • VENH ~ 2.4V 1 0 0 1 1 0 1 10 1 0 1 0 1 0 1 11 1 0 1 1 1 0 1 12 1 1 0 0 1 0 1 13 1 1 0 1 1 0 1 14 1 1 1 0 1 0 1 15 1 1 1 1 1 0 1 16 Logic "0" = VAL. VENL :s; 0.8V 00528 Az AI Ao EN WR RS X X X X X X X X X 0 00529 ON SWITCH A, ..r 1 Maintains Previous Switch Condition X X X 0 None (Latches Cleared) X 0 0 1 None 0 0 1 0 1 1 0 0 0 1 1 0 1 2 0 0 1 0 1 0 1 3 1 0 1 1 1 0 1 4 1 1 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 Ao EN WR RS ON SWITCH X X ..r 1 Maintains Previous Switch Condition X X X X 0 None (Latches Cleared) X X 0 0 1 None 0 1 0 1 1 1 1 0 1 2 0 1 0 1 3 1 0 1 4 logic "1": VAH~2.4V Logic "0": VAL:S; 0.8V 10-65 DG526 Die Characteristics DIE DIMENSIONS: 3810jUTI x 27691lm METALLIZATION: Type: AI Thickness: 10kA ± 1kA GLASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA oJ: 1.4kA Nitride Thickness: 8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout 00526 PIN 11 lie PIN 10 510 PINSI 511 PIN 8 512 PIN 7 513 PINS 514 PINS 51S PIN 4 516 PIN 12 GND PIN 3 Rs PIN13 WR PIN 14 ' PIN 2 Ne A:! PIN1S A:z PIN 1 PIN 16 v+ AI PIN 28 D PIN 17 Ao PIN 27 _.. PIN18 EN ~ e~ ;1t!J PIN 18 51 PIN 20 PIN 21 Sz 10-66 Sa PIN22 PIN23 54 5s PIN 24 PIN 25 lie Sr PIN 26 5. Y- DG527 Die Characteristics DIE DIMENSIONS: 3B 1OJ.1m x 2769J.1m METALLIZATION: Type: AI Thickness: 10kA ± 1kA GLASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness: BkA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm 2 Metallization Mask Layout DG527 PIN11 SIB PIN10 Sa PINSI S3B PIN a S. PIN 7 SIB PIN 6 PINS Sm Sn! PIN 4 SIB PIN 12 GND PIN3 irs PIN 13 WR PIN14 NC PIN 2 Da PIN 15 Az U) PIN1 PIN 16 v+ AI PIN 28 DA PIN 17 Ao a:: ...~ Q. 5:::» :E PIN 27 ..... PINIS EN ~ .... H- HII! Uiii PIN1S1 SIA PIN 20 PIN 21 S3A Su 10-67 PIN 22 PIN 23 SSA S4A PIN 24 PIN 25 SeA S7A PIN 26 SeA v- DG528 Die Characteristics DIE DIMENSIONS: 3100lJ1l1 x 20831lm METALLIZATION: Type: AI Thickness: 10kA± lkA GLASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA ~ l.4kA Nitride Thickness: 8kA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DG528 PIN 15 GND PIN 14 v+ PIN 13 S5 PIN 12 PIN 11 St S7 PIN16 A2 PIN 17 AI PIN 18 Rs PIN10 S, PIN 1 PINg D ViR PIN 2 Ao PIN3 EN PIN 4 v- 10-68 PINS SI PIN 6 S2 PIN 7 S3 DG529 Die Characteristics DIE DIMENSIONS: 3100~m x 20B3~m METALLIZATION: Type: AI Thickness: 10kA±1kA GLASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA iF 1.4kA Nitride Thickness: akA ± 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 Alcm 2 Metallization Mask Layout DG529 PIN 1S V+ PIN 14 51G PIN 13 PIN 12 5e 538 PIN 11 548 PIN16 GND PIN18 PIN 10 iii 5aA PIN1 ViR PIN2 Ao PIN 8 54A PIN3 EN PIN 4 PINS PINS PIN 7 V- 511, 52A 5aA 10-69 HI-1818A, HI-1828A t.:m HARRIS· ~ SEMICONDUCTOR Low Resistance, Single 8 Channel and Differential 4 Channel CMOS Analog Multiplexers December 1993 Features Description • Signal Range of +15V The HI-181BA and HI-1828A are monolithic high performance CMOS analog multiplexers offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. Dielectric Isolation (01) processing is used for enhanced reliability and performance (see Application Note 521). Substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. Low output leakage (typically 0.1 nA) and low channel ON resistance (2500) assure optimum performance in low level or current mode applications. • "ON" Resistance 2500 • Input Leakage (Max) SOnA • Access TIme 350ns • Power Consumption Smw • DTUTTL Compatible Address • -5SoC to +12rC Operation Applications The HI-181BA is a single-ended 8 channel multiplexer, while the HI-1 B28A is a differential 4 channel version. Either device is ideally suited for medical instrumentation, telemetry systems, and microprocessor based data acquisition systems. • Data Acquisition Systams • Precision Instrumentation • Demultiplexlng For MIL-STO-8B3 compliant parts, request the HI-181BN 883; HI-182BNBB3 data sheet. • Selector Switch Pinouts H1-1818A (CDIP, PDlP) HI-1828A (COIP, POIP) TOP VIEW TOP VIEW ADDRESS.A1· 1 +5VSUPPLY 2 .EN'lia' ADDRESS A(, ADDRESSA1 1 6 ADDRESSAo +5VSUPPLY 2 -YSUPPLY INlILf 3 AODRESSAt 4 3 4 +YSUPPLY OUT6THRU8 4 2 OUT1 THRU 4 HI-1818A (PLCC) TOP'VIEW HI-1828A (CLCC, PLCC) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge. Users should follow preper I.C. Handling Procedures. Copyright @Harrls Corporation 1993 10-70 File Number 3141 HI-1818A, HI-1828A Ordering Information PART NUMBER TEMPERATURE RANGE PART NUMBER PACKAGE OOC to +7SoC + 96 Hour Burn-In 16 Lead Ceramic DIP HI3-1828A-S O"C to +7SoC 16 Lead Plastic DIP 16 Lead Ceramic DIP HI4Pl828A-S O"C to +7SoC 20 Lead PLCC O"C to +75°C 16 Lead Plastic DIP HI1-1818A-2 -55OCto +12SoC 16 Lead Ceramic DIP HI1-1818A-S O"C to +75°C OOC to +7SOC + 96 Hour Burn-In H14P1818A-S O"C to +7SoC HI1-1818A1883 HI1-1828A-S PACKAGE HI1-1828A-7 HI3-1818A-5 HI1-1818A-7 TEMPERATURE RANGE 16 Lead Ceramic DIP HI1-1828A-2 -SSOC to + 12SoC 20 Lead PLCC HI1-1828A1883 -5SOC to +12SoC 16 Lead Ceramic DIP -ssOC to +12SoC 16 Lead Ceramic DIP HI4-1828A1883 -ssOC to +12SOC 20 Lead CLCC O"C to +7SoC 16 Lead Ceramic DIP HI4-1828A-8 -S50C to + 12SoC 20 Lead CLCC Functional Diagrams HI-1818A DIGITAL ADDRESS ~ _ _ _ _~A~_ _~~~ ADDRESS { INPUT BUFFERS r=;;..;...----roOIN 1 H1-1828A AODRESS{ INPUT BUFFERS ;;:-:;:;;;'--oOIN 1 t-lr--;~~==*=l-~~--r----.r===~:::OUT54 INa 10-71 16 Lead Ceramic DIP HI-18.18A,HI-1828A Schematic Diagrams ADDRESS INPUT BUFFER t--t-t-A All No Channel BocIIea to vAH P-Channel BocIIea to y+ Unless 0IherwIsa SpecIIIed V- ADDRESS DECODER All N· Channel Bodies to VAil P-Channel Bodies to y+ A2 or Ai not used for HI·1828A MULTIPLEXER SWITCH FROM DECODE All N· Channel Bodies to y. All P-Channel Bodies to V+ Unless Otherwtse Speclfied FROM DECODE 1()"72 Specifications HI-1818A, HI-1828A Absolute Maximum Ratings (Note 1) Thermal Information Voltage Between Supply Pins ••.••••.••••.••••.•.•••.•• 4O.0V Logic Supply Voltage ...•••..•••.•••••..••...••••.••• 3O.0V Analog Input Voltage: +VIN •.•..•••••.•••••••••.••••••••••••.•• +VSUPPLY +2V -VIN· .••..••••••••••••••••••••.••••••••••• -VSUPPLY -2V Digital Input Voltage ••..••••.•••••••...•• -VSUPPlY to +VSUPPLY Storage Temperature PDIP, PLCC •••••••••.•••.••••••••.•••••• -65°C to +15O"C Thermal Resistance 9JA Ceramic DIP Package ••••••••••••••• 77"C/'N 75"CIW Ceramic LCC Package ••••••••••.••• Plastic DIP Package •••••••••••••••• l000ctw Plastic PLCC Package •••••••••••.••• 8OOC/W Operating Temperature Rangas HI-1818MiI-1828A-2, -8 ••..•.••••••••••••• -55°C to +125°C HI-1818A1HI-1828A-5, -7 •••.••••.•••••••••••• OOC to +75°C Junction Temperature CDIP, CLCC ••••••••••.•••.•••.•••.••••..••..•.. +1750 C PDIp, PLCC ••.•••.••••...•.••....•••.•••••••.•• +15O"C CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings" may cause permanent damage to the davice. This is a stress only rating and operation of the device at these or any other conditions abo... those indicated in the operational sections of this specification is not irnpHed. Electrical Specifications Supplies = +15V, -15V, +5V; VAl. = 0.4V, VAH = 4.0V, Unless Otherwise Specified PARAMETER H1-1818A11828A ·2,-8 TEST CONOmONS TEMP (Note 4) +25°C I MAX HI·1818A11828A ·5,·7 I MIN TYP · · 350 500 . 1000 25 - - 1.08 - - MAX I UNITS MIN TYP . 350 . ns - 1000 ns 100 - ns SWITCHING CHARACTERISTICS Access Time, TA Full Break-Belore-Make Delay +25°C - Settling Time 0.1% +25°C 0.025% +25°C Channel Input Capacttance, CIN +25°C - 2.8 4 - - 1.08 2.8 - 4 - 20 +25OC HI-1828A +25OC Drain-To-Source Capacitance, COS(OFF) +25°C Digital Input Capacitance, Co +25OC Enable Delay (ON), IoN(EN) +25OC Full Enable Delay (OFF), IoFF(EN) +25°C Full - 20 10 - 5 - 300 500 - 1000 300 500 - 1000 0.6 - lIS - lIS pF - pF - Channel Output Capacitance, COUT HI-1818A - 10 - pF - pF 1000 ns ns - 1000 ns - 0.4 V V - 1 IIA 0.6 5 300 300 pF ns DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH (Note 3) Input Leakage Current, IA - - Full · Full 4.0 Full - Full -15 +25°C - - 500 - 50 - 0.4 - 4.0 1 - - +15 -15 250 400 - - ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN ON Resistance, RoN (Note 2) Full Input Leakage Current, IS(OFF) Full - +15 V 250 400 0 - 500 0 50 nA - On Channel Leakage Current, 'O(ON) HI-1818A Full Full - - HI-1828A - 125 HI-1818A Full - Full - - 250 HI-1828A 250 - 250 nA - - 125 nA - - 250 nA 125 nA Output Leakage Current, IO(OFF) 10·73 125 - - Specifications HI-1818A, HI-1828A Electrical Specifications Supplies =+15\1, -15V, +5V; VAl. =0.4V, VAH =4.0V, Unless Otherwise Specified TEST CONDITIONS PARAMETER TEMP I I HI-1818AJ1828A·2,·8 MIN TVP MAX - 27.5 I I HI·1818A11828A -5,·7 I I UNITS MIN TYP MAX - - 27.5 mW 0.5 mA - 1 mA - 1 mA POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Full '- Current, 1+ Full - Current, I- Full Current,I L Full - - - 0.5 - - 1 - - 1 NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceabiUty of the circutt may be impaired. Functional operation under any of these conditions Is not necessarily Implied. 2. VOUT=±10V,loUT= 'l'1mA. 3. To drive from DTUTTl circuits, 1kQ pull-up resistors to +5.0V supply are recommended. 4. Time measured to 90% of final output level; VOUT =-5.0V to +5.0V, Digital Inputs =OV to +4.0V. Switching Waveforms +15 -15 +5.0 .... ENABLE DRIVE A2 +V -V VL INI HI-1818A (NOTE 1) IN 2-8 +5V -\ ENABLE DRIVE 2VIDIV 200 OUTPUT '\ 2VIDIV I n - I -=- OUT VA I - ~ I-- 50nsIDIV NOTE: 1. SimiiarconneclionsforHI-1828A FIGURE 1A. FIGURE 1B. FIGURE 1C. FIGURE 1. ENABLE DELAY, toN(EN)' toFF(EN) +15 -15 +5.0 ADDRESS DRIVE A2 +V VL VA INPUT 2VIDIV INI 4.0V 1\ ~ -V ADDRESS ~Al "" \ ~ V OUTPU~ 1VIDIV l00nsIDlV NOTE: 1. Similar connections for HI-1828A FIGURE2B. FIGURE 2. BREAK-BEFORE-MAKE DELAY, toPEN 10-74 I y- V -l t-tOPEN FIGURE2A. I FIGURE2C. HI-1818A, HI-1828A Typical Performance Curves _1mA -Va- OUT Vz RoN = '1,;;A 350 60 w U z 250 IIIw 200 ...gz ~ ./ +~ r-- ~ II: :h.: C 40 300 § -- w / :;) u 100 -10 -8 -6 -4 z ~... -ss~ -2 0 2 4 SIGNAL LEVEL (V) ! O N = +12~ -40 ~ 8 -60 10 -II -10 -6 -5VOC 0 - + - - 0 IN 3-8 ~ ~~4V -!--!- 8 'l'10V= ~[H?lt ±10V= ='I'10V -4 -2 0 2 4 6 VOLTAGE ACROSS SWITCH (V) ACCESS TIME A ID(OFF) = +12SoC 1N1 +5VDC o--t----q 1N2 4V OUT 'l'10V= ~ L / +25°C FIGURE 4_ ON CHANNEL CURRENT vs VOLTAGE ON LEAKAGE : =±10V ~ -20 ~~ ~ ~oc- -+2tC 6 FIGURE 3_ ON RESISTANCE vs ANALOG SIGNAL LEVEL OFF LEAKAGE 0 CI ~ 150 20 II: II: ~, Z 0 ~ • Two measurements per channel: +10V/-10Vand -10V/+10V (Two measurements per device for ID(OFF): +1 OV/-1OV and -10V/+10V OV TO 4V * Similar connection for HI-1828A. 100nA 4V .JIll' . / .JIll' 10nA 1nA =HI-1818A_ HI-1828A ~ r----' § ID(ON) - lD(oFF) "Y'L / ' ..... ! IS(OFF) ~V ~ HI-1818A HI-1828A i 10pA 25 50 75 TEMPERATURE rC) f-- i i .// 100pA AoINPUT 2VIOIV - 100 ~ 125 80% TA OUTPUT ISV::i J 4 100nsIDIV FIGURE 5_ LEAKAGE CURRENTS vs TEMPERATURE' FIGURE 6. ACCESS TIME 10-75 I 10 HI-1818A, HI-1828A HI-1818A TRUTH TABLE H1-1828A TRUTH TABLE ADDRESS ~ A, Ao ADDRESS EN MON" CHANNEL A, Ao EN "ON" CHANNEL L L L 1 and 5 L L L L . 1 L L H L 2 L H L 2and6 L H L L 3 H L L 3and7 L H H L 4 H H L 4and8 H L L L 5 X X H None H L H L 6 H H L L 7 H H H I,. 8 X X X H None 10-76 HI-1818A, HI-1828A Die Characteristics DIE DIMENSIONS: 67.7x 103.5 mils METALLIZATION: Type: Cu/AI Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride/Silox Thickness: Silox: 12kA ± 2kA. Nitride: 3.5kA ± 1kA WORST CASE CURRENT DENSITY: 1.43 x 105 Ncm 2 at 25m A Metallization Mask Layout HI-1818A HI-1828A -lSVSUPPLY OUTS THRU 8 +VSUPPLY IN 8 IN7 IN6 INS IN4 IN3 IN2 IN6 IN 5 10-77 IN4 IN3 IN2 HI-50,6, HI-507 HI-50S, HI-509 ~HARRlS \KJ SEMICONDUCTOR December 1993 Single 16 and 81Differential 8 and 4 Channel CMOS Analog Multiplexers Features Description • Low On Resistance 1800 The HI-5061H1-507 and HI-50BIHI-509 monolithic CMOS multiplel(9rs each include an array of sixteen and eight ana· log switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplel(9rs are present. The Dielectric Isolation (01) process used in fabrication of these devices eliminates the problem of latch up. 01 also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Applicalion Note AN521). • Wide Analog Signal Range ±15V • TTL/CMOS Compatible • Access Time 250ns • 44V Maximum Power Supply • Break·Before·Make Switching • No Latch·Up • Replaces DG506A1DG506AA and DGS07AlDGS07AA • Replaces DG508A1DG508AA and DG509A1DG509AA Applications • Data Acquisition Systems • Precision Instrumentation • Demultlplexlng • Selector Switch. The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic "1" and maximum o.av for logic "(1'. This allows direct interface wilhout pullup resistors to signals from most logic families: CMOS, TIL, DTL and some PMOS. For protec· tion against transient overvoltage, the digital inputs include a series 2000 resistor and diode clamp to each slJPply. The HI-506 is a single 16 channel, the HI-507 is an a channel differential, the HI-50a is a single a channel and the HI· 509 is a 4 channel differential multiplel(9r. The HI-506IH1-507 are available ina 2a pin ceramic or plastic DIP, 2a pad lead· less chip carrier (LCC), 2a pin plastic leaded chip carrier (PLCC) and 2a lead SOICpackages. The HI-508lHI-509 are available in a 16 pin plastic or ceramic DIP, a 20 pin plastic leaded chip carrier (PLCC), 20 pad ceramic leadless chip carrier (LCC) and 16 lead SOIC packages. If input overvoltages are present the HI-5461HI-547/HI-5481 HI-549 multiplexers are recommended. For further Information see Applicalion Notes AN520 and AN521. The HI-5061 HI-507/HI-50BIHI-509 is offered in both commercial and military grades. For additional High Reliability Screening including 160 hour burn-in specify the "-a" suffix. For MiI-Sld-aa3 compliant parts,. requesl the HI-506l683, HI-507/a83, HI5081883 or HI-509/aa3 dalasheet CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-7a File Number 3142 HI-S06, HI-S07, HI-50S, HI-S09 Ordering Information PART NUMBER TEMPERATURE RANGE HI1-0506I883 _55°C to +125°C 28 Lead Ceramic DIP HI1-0508I883 -55"C to +125°C 16 Lead Ceramic DIP HI-Rei Processing with Burn-In 28 Lead Ceramic DIP HI1-0508-8 Hi-Rei Processing with Burn-In 16 Lead Ceramic DIP HI1-0506-9 -4000 to +85°C 28 Lead Ceramic DIP HI1-Q508-9 -4OOC to +85°C 16 Lead Ceramic DIP HI4-0506I883 -55°C to +125OC 28 Lead Ceramic LCC HI4-0508I883 -55"C to + 125°C 20 Lead Ceramic LCC HI1-0507/883 -55"C to +125°C 28 Lead Ceramic DIP H11-0509/883 -55"C to +125°C 16 Lead Ceramic DIP HI9P0506-9 -400C to +85°C 28 Lead SOIC HI1-0508-5 OOCto +75°C 16 Lead Ceramic DIP HI3-0506-5 OOCto +75°C 28 Lead Plastic DIP HI3-0508-5 OOC to +75"C 16 Lead Plastic DIP HI1-0506-7 OOCto +75°C + 96 Hour Burn-In 28 Lead Ceramic DIP HI1-0508-4 -25°C to +85°C HI1-0508-2 -55°C to +125°C HI4P0508-5 OOC to +75"C HI1-Q508-7 OOC to +75"C + 96 Hour Burn-In HI1-0506-8 PART NUMBER PACKAGE TEMPERATURE RANGE PACKAGE 16 Lead Ceramic DIP 16 Lead Ceramic DIP HI9P0506-5 OOCto +75°C HI40506-5 OOCto +75°C 28 Lead PLCC HI1-0506-5 OOC to +75"C 28 Lead Ceramic DIP HI1-0506-4 -25°C to +85°C 28 Lead Ceramic DIP HI9P0508-9 -400C to +85°C 16 Lead SOIC (N) HI1-0506-2 -55°C to +125OC 28 Lead Ceramic DIP HI9P0508-5 OOCIo +75OC 16 Lead SOIC (N) HI1-0507-8 HI-Rei Processing with Burn-In 28 Lead Ceramic DIP HI1-0509-8 HI-Rei Processing with Burn-In HI1-0507-9 -400C to +85OC 28 Lead Ceramic DIP HI1-0509-9 -40°C to +85°C 16 Lead Ceramic DIP HI4-0507/883 -55°C to +125°C 28 Lead Ceramic LCC H14-0509/883 -55°C to + 125°C 20 Lead Ceramic LCC HI1-0507-4 -25°C to +85"C 28 Lead Ceramic DIP HI9P0509-5 OOC to +75"C 16 Lead SOIC (N) H14P0507-5 OOCto +75°C 28 Lead PLCC H19P0509-9 -4OOC to +85"C 16 Lead SOIC (N) H19P0507-5 OOC to +75"C 28 LeadSOIC HI1-0509-4 -25°C to +85OC 16 Lead Ceramic DIP HI1-0507-5 OOCto +750C 28 Lead Ceramic DIP HI1-0509-5 OOCto +75°C 16 Lead Ceramic DIP 28 Lead Plastic DIP HI3-Q509-5 00CIo+75°C 16 Lead Plastic DIP 28 Lead Ceramic DIP HI4P0509-5 OOC to +75"C 20 Lead PLCC HI1-Q509-2 -55°C to + 125°C 16 Lead Ceramic DIP HI1-0509-7 OOCto +75OC + 96 Hour Burn-In 16 Lead Ceramic DIP 28 Lead SOIC HI3-0507-5 OOCto +75°C HI1-0507-7 OOCto +75°C + 96 Hour Burn-I n HI9P0507-9 -400C to +85°C 28 Lead SOIC HI1-0507-2 -55°C to +125°C 28 Lead Ceramic DIP 10-79 20 Lead PLCC 16 Lead Ceramic DIP 16 Lead Ceramic DIP HI-506, HI-507, HI-50S, HI-509 Pinouts HJ.0507 (POIP, COIP, SOIC) TOP VIEW HI·506 (POIP, CDlP,SOIC) .TOPVIEW +VSUPPLY +VSUPPLY Ne Ne OUTB IN16 INaB Ne IN1S IN7B INS IN14 INIB IN13 INSB IN3 IN12 IN4B IN 11 IN3B IN2B 17 ADDRESS Au ADDRESS", -,. 14 _ _ _ _..r- HI·506 (LCC,PLCC) TOP VIEW :! l! IN 15 f zu ~ ~+. 5 0 HI·507 (LCC,PLCC) TOP VIEW ~ t ~ .. m m l! l! _, t!J ttJ tg,j L~J ttBj t~j ttBJ ._ !J L~S m u z 8 ......~ i ~ . I'" .. 0( 8 ~ 0( l! _, t!J ltj 19,j L~J ltBJ l~j Lt6J._ !J L~5 IN 7 IN7B IN14 IN8 INO IN13 INS INO IN~ IN12 IN4 INU INU INll IN3 IN 10 IN2 r-,. r - .. r - .. .. -" r - .. .. - .. ~_ .. '12' '13' '14' '15' '18' '17' '18' IN~ IN~ IN~ IN1B IN1A r-'" r- .. r- ... ... - .. r-,. .. - .. r--. '12' '13' '14' '15' '16' '17' '18' u Q z ~ 10·80 IN7A u z HI-S06, HI-SOT, HI-50B, HI-509 Pinouts (Continued) HI-508 (PDIP, CDIP, SOIC) TOP VIEW HI-509 (pDIP, CDIP, SOIC) TOP VIEW Ao Ao ENABLE ENABLE -YSUPPLY -YSUPPLY IN1 IN1" 2" IN2 IN IN3 IN3A IN4 IN4A OUT OUT A HI-508 (LCC,PLCC) TOP VIEW HI-509 (LCC,PLCC) TOP VIEW ...IDw C zw -YSUPPLY IN1 Ne IN2 IN3 -., _4...I .f Uz L!.J LaJ L~J C ~ LiOJ L1.lIJ --, r- 118 L_ GND -., 5 I -., &I -YSUPPLY r117 L_ +YSUPPLY r- -..I IN 1,\ l!.6 Ne -.,1 -..I 7 Ne r15~ IN 5 IN2A IN6 IN3" L_ -., 8 I -..I -..I r-., r-, r-, r-, r-" I III 1101 1111 1121 1131 L!.J LaJ L~J LtDJ L1.lIJ ~J rl!.8 +YSUPPLY -, r- !J -., !J -., !J -., !J l!! IN 1B rl!.6 Ne r;5~ IN2B ,,IN3B r-., r-., r-, r-., r-., I III 1101 1111 1121 1131 .. u ID z i!5 10-81 HI-S06, HI-S07, HI-SOB, HI-S09 Functional Diagrams HI-50s IN1 o-+---~LO_l_r-;:::::::::~--r-0 IN 2 o-I---C),,; •• • IN 16 o-!---c)'; HI-507 IN 1A OUT <>-II---C:r: 0 ....-------+-o OUT A • IN8A DECODER! DRIVER IN 1B <>-11-+-00-: 0"1-.:====:;--to OUT B DECODER! DRIVER INaB 10-82 HI-S06, HI-S07, HI-SOB, HI-S09 Schematic Diagrams ADDRESS DECODER TO N-CHANNEL DEVICE OF THE SWITCH ENABLE DELETE -'3 OR ~ INPUT FOR HI-507 DELETE -'3 OR & INPUT FOR H1-508 DELETE A:t OR A:t INPUT FOR H1-509 ADDRESS INPUT BUFFER LEVER SHIFTER +y t---ir--+-- +y 01 200n -y -Y ALL N-CHANEL BODIES TO YALL P-CHANNEL BODIES TO Y+ UNLESS OTHERWISE INDICATED 10-83 A HI-506, HI-507, HI-508, HI-509 Schematic Diagrams (Continued) TTl REFERENCE CIRCUIT MULTIPLEX SWITCH v+ - FROM DECODE Yo GND 10-84 Specifications HI-S06, HI-S07, HI-SOB, HI-S09 Absolute Maximum Ratings Thermal Information VSUPPlY(+) to VSUPPLY(.)' ...•••.•••..•.•••••••••••••••• +44V VSUPPLY(+) to GND .................................. +22V VSUPPLY(.) to GND •••.•.••••..••.....•...•••••..••..•• ·2SV Digital Input OVervoltage +VEN' +VA •••••••.•••••••.••..•.••.•.••••• +VSUPPlY +4V ·VEN , ·VA •..•.......•••.. .' ...•..•..••...•.• ,VSUPPly-4V or 20mA, whichever occurs lirst Analog Signal OVervoltage (Note 7) +VS ....•••••.••••••••••••••.•••••••••••• +VSUPPLY +2V •Vs· •...•••.•.•••••.••••....•••.•••••••••• ,VSUPPLy-2V Continuous Current, S or D ........................... 20mA Peak Current, S or D ................................ 40mA (Pulsed at 1ms, 10% duty cycle max) Storage Temperature Range ................. ·6SoC to +ISOoC Lead Temperature (Soldering lOs) .....•.•••.•••.••... +300"C Thermal Resistance 9JA 16 Lead Ceramic DIP Packages .••••.• 800 CrN 16 Lead SOIC Packages ..•••••..••.. IISOCrN 16 Lead Plastic DIP ................ . l000 CrN 200 CrN 20 Lead Ceramic LCC Packages •••••. 7S°CNtl 800CrN 20 Lead PLCC .................... . SSoCrN 200CrN 28 Lead Ceramic DIP Packages ••..••• 28 Lead Plastic DIP Package ••.•.•••• 60°CNtl 70°CNtl 28 Lead SOIC Package ............. . II°CrN 600CNtl 28 Lead Ceramic LCC Packages •••••• 28 Lead PLCC Packages .......... .. 70°CNtl Operating Temperature Ranges HI·S06IS07/S08IS09·2,·8 .................. ·SSoC to +12SoC HI·S06IS07/S08IS09-4 ••••..••.••••••••••.•• -2SoC to +85°C HI·S06IS07/S08lS0g·S .•••..•.••.•.•••..•• -65°C to +IS0 °C Junction Temperature Ceramic •••..•....•.•..••.....•..•...•......••. +17SoC Plastic •••••••.••••••..••...•••...•....•••.•••• + lSOoC CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings" mey cause permanent damege to the davie... This is a stress only rating and operation of the device at these or any other condiffons abo... those indicated in ths operational sections of this specification is not implied. Electrical Specifications Supplies = +ISV, -ISV; VAH (Logic Level High) = +2.4V; VAL (Logic Level Low) = +D.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves. PARAMETER H1-5XX-2, HI-5XX-8 TEST CONDITIONS TEMP (Note 1) +2SOC I HI-5XX-4. HI-5XX-5 I I UNITS MAX MIN TYP 2S0 500 · 2SO - ns - 1000 - - 1000 ns MIN TVP Full · · MAX SWITCHING CHARACTERISTICS Access Time, IA Break-Belore-Make Delay, !oPEN (Note 1) +25OC 2S 80 - 2S 80 Enable Delay (ON), !oN(EN) (Note 1) +2SoC - 2S0 SOO 2SO - 1000 - Full Enable Delay (OFF)'!oFF(EN) (Note 1) +2SOC Full - 2S0 500 . 1000 - Settling Time 10 0.1 %, ts (HI-S06 and HI·S07) +2SoC · 1.2 Settling Time to 0.01%, ts (HI-S06 and HI·S07) +2SoC - 2.4 Settling Time to 0.1 %, Is (HI·S08 and HI-509) +2SOC · 360 Settling Time to 0.01%, ts (HI-S08 and HI-509) +2SOC · . - ns ns 1000 ns 2SO · ns - . 1000 ns · 12 - lIS - - 2.4 - 360 - 600 - · 600 · ns - lIS ns +25OC SO 68 SO 68 · dB Channel Input Capacitance, CS(OFF) +2SOC - 10 - - 10 - pF Channel Output Capacitance, CO(OFF) (HI-506) +2SoC - 52 - - 52 · pF Channel Output Capacitance, CO(OFF) (HI-507) +25OC · 30 - · 30 · pF Channel Output Capacitance, CO(OFF) (HI-5OB) +2SoC 17 - - 17 - pF Channel Output Capacitance, CO(OFF) (HI-509) +25°C 12 . - 12 - pF Digital Input Capacitance, CA +2SoC 6 - · 6 - pF "Off Isolation" (Note 5) 10-85 Specifications HI-506, HI-SOT, HI-50S, HI-509 Electrical Specifications Supplies. +15V. -1SV; VAH (logic Level High) .. +2.4V; VN.. (logic Level Low) = +o.BV. Unless Otherwise Specified. For Test Conditions. Consult Performance Curves. (Continued) HI-5XX·2, HI-SXX-8 TEST CONDITIONS PARAMETER Input to Output Capacitance, COS(OFF) HI-5XX-4. HI-5XX-5 TEMP MIN TYP MAX MIN TYP MAX UNITS +25"0 · 0.08 · · 0.08 · pF · · · +O.B V · V 1.0 IIA DIGITAL INPUT CHARACTERISTICS Input Low Threshold. VN.. (Note 1) Full · - +O.B · Input High Tlveshold. VAH (Note 1) Full +2.4 Full · · (Notes 1. 4) Full -15 +25"0 · · · · 50 · · · nA 50 nA 0.3 · · nA · · 300 · · 0.3 nA · · · 300 200 200 nA · · 200 · · · 200 nA · 100 nA · 0.3 · · 0.3 - nA · 300 · · · · · · · Input Leakage Current (High or Low). IA · +2.4 · 1.0 · · +15 -15 1BO 300 - 5 · 0.03 - ANALOG CHANNEL CHARACTERISTICS Analog Signal Range. Vs On Reslstsnce, RoN (Notes 1. 2) ARoN, (Any TwoChaMels) +25"0 Off Input Leakage Current, lS(oFf) (Note 3) +25°C Full Off Output Leakage CUrrent, (Note 3) +25"0 IOlOFF) · · HI-50S Full HI-507 Full · HI-50B Full HI-509 Full · · On Channel Leakage Current, (Note 3) +25"0 IOlON) HI-50S Full HI-507 Full - HI-50S Full HI-509 Full (Note 1) Current, 1+, Pin 1 HI-5081HI-507 Current, 1+. HI-508IHI-509 100 · +15 V 180 400 Q · 5 · - 0.03 300 nA 200 nA 200 nA 100 nA - 200 · · 200 - · 100 Full · · 50 · · 50 nA (Note S) Full 3.0 3.0 rnA 1.5 2.4 1.5 2.4 rnA Current, I·, Pin 27 HI-508IHI-507 (NoteS) Full 0.4 1.0 0.4 1.0 rnA Current, I·. HI-508IH1-509 (NoteS) Full - · · · 1.5 Full · · · 1.5 (NoteS) 0.4 1.0 - 0.4 1.0 rnA HI-508IHI-507 Full · · 80 · 60 mW Full · · HI-508IHI-509 51 51 mW Differential Off Output Leakage Current, IOIFF (HI-507. HI-509 Only) - % POWER REQUIREMENTS Power Dissipation, Po - - - NOTES: 1. 100% tested lor Dash B. Leakage currents not tested at -55°C. 2. VOIJT " ±10V, lOUT +1rnA. 3. Ten nanoarnps Is the practical lower Omit lor high speed measurement In the production test environment. 4. Digital Input leakage Is primarily due to the clamp diodes (see Schematic). Typical leakage Is less than 1nA al +250 C. 5. VEN O.av, RL 1K. CL 15pF, Vs 7VRMS' I 100kHz. S. VEN • VA OVor 2.4V. 7. Signal voltage at any analog input or outpul (S or D) will be clamped to the supply rail by Internal diodes. Limit the resul1lng current as shown under absolute maximum ratings. If an overvoltage condition Is anticipated (analog Input exceeds either power supply voltage). the Harris HI-546IHI-5471H1-548IHI-549 multiplexers are recommanded. = = = = = = = 10-86 HI-S06, HI-S07, HI-SOB, HI-S09 Performance Curves TA =+25"C, VSUPPLY =±15V, VAH =2.4V, VAL =O.BV, Unless Otherwise Specified _ _ _ 1mA • • V2 IN OUT ;.'r! VIN FIGURE 1A. TEST CIRCUIT 400 2.2 +1250C~TA~.os"C >2.0 § ...v 300 w o :i ~ 200 a: z o 100 w" 0 .. '- .... ...- ,., - -...- TA-+25"C I ", ~ Ill~ 1.6 I,..- ~ TA = +12s"C I ~~ 1.8 w-' a:~ 5l~ 1.4 ~ !:I 51 1.2 :=ia: ~~ TA-.ss°C zw "" ............ ......... 1.0 ~ e. 0.1 o -15 -10 .0 0 +5 0.6 ±7 +15 +10 ANALOG INPUT (V) ±I ±SI ±10 ±11 ±12 ±13 FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 1 DOnA I 10nA I OFF OUTPUT LEAKAGE CURRENT III(OFF) - ...z w a: a: ~ ::> 0 inA I' ./" III(ON)~ V ~ C w -' 100pA V . / ......... OFF INPUT LEAKAGE CURRENT . IS(OFF) ::: - 10pA 25 50 75 ±14 SUPPLY VOLTAGE M FIGURE 18. ON RESISTANCE VS ANALOG INPUT VOLTAGE, TEMPERATURE w _ VIN=OV 100 125 TEMPERATURE ("C) FIGURE 2A. LEAKAGE CURRENT va TEMPERATURE FIGURE 28. Io(OFF) TEST CIRCUIT 10-B7 ±15 HI-S06, HI-507, Hr·SOB, HI-S09 Performance Curves TA = +25 0 C, VSllPPLY = ±15V, VAH '" 2.4V, VAL =O~8V, Unless Otherwise Specified (Continued) t- J ±10V OUT OUT •• •• = J +O.'V EN f--o = J "'10V Ao "'lOY EN Al 1 1 FIGURE 2C. IS(OFF) TEST CIRCUIT A ID(ON) - J ±10V +2.4V FIGURE 2D. ID(ON) TEST CIRCUIT FIGURE 2. ON RESISTANCE NOTE: 1. Two measurements per channel: +10V/·l0V and ·10Vl+l0V. (Two measurements per device for lD(oFF) +1 OVl·lOV and ·1 OVl+lOV) 4 100 :E c 3 :!!. 5:z: ~ Ul i ~"IK m --.. !=; w - 2 ..9 It 0 ~ ~ 1 l!: ~ ~ 80 0 40 20 r- ±, ±10 ±12 ±14 ±16 POWER SUPPLY VOLTAGE (V) 104 ±20 ±1' FIGURE 3. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE C 2.0 U !Ew .... VEN,,2.4V - ~ DD- ~ 2.0 II: II: - 8 -- - ~ DD- VEN= OV ::) II: 107 S ::) Ul I" 105 106 FREQUENCY (Hz) 3.0 C ~ II: I" FIGURE 4. OFF ISOLATION vs FREQUENCY 3.0 z VEN= OV CLQAD" 2'pF VS·7VRM8 I 0 ±6 1-0 RL-l0M I- ..S I I III r"-oi"o iii '0 II: i!: ~ I ..... ::) 1.0 Ul II: 1.0 w ~ D- D-Ii J........-" Z I EN '!' OV r - - 0 O -55 - EN .. 5V -35 ·15 +25 +45 +66 TEMPERATURE ("C) -5 -55 +85 +105 +125 FIGURE SA. HI·506JH1-507 -35 ·15 +25 +45 +65 +'5 +105 +125 TEMPERATURE ("C) -5 FIGURE 58. HI·50BlHI·509 FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE 10-88 HI-506, HI-507, HI-50B, HI-509 Performance Curves TA =+25°C, VSUPPLY (Continued) =±15V, VAH =2.4V, VAL =O.8V, Unless Otherwise Specified 70 60 1... zw 50 40 II: II: ::I U :z: 30 ~ 20 In 10 ±2 ±4 ±6 ±8 ±10 ±12 VOLTAGE ACROSS SWITCH (V) ±14 ±16 FIGURE SA. ON CHANNEL CURRENT vs VOLTAGE FIGURE S8. TEST CIRCUIT FIGURE S. ON CHANNEL CURRENT VB VOLTAGE 8 I VSUPPLY" ±1SV 'i" 6 .§. J !zw II: II: a4 2 A_ r----~~-i~ +3.SV HIGH .. 3.5V ..,. VvSUPPLY" ±10V 10K 100K TOGGLE FREQUENCY (Hz) A 1M IN2~~--~ AI IN7115--":~_.....J Ao IN 8/16 ±10Vl±5V EN 10 GND V { LOW .. OV I 1K HI-S06t THRU ./ o ±10VI±5V A:z VI ......~ ::I In / Mn 50% DUTY CYCLE 10M FIGURE 7A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 78. TEST CIRCUIT FIGURE 7. SUPPLY CURRENT +1SV 600 i ;;; 400 ~ ~ g: VA w +V IN1 A:z IN 2 THRU IN7f1S AI - ~ 200 A:z - Ao HI-S06t IN16 \ ....................................... ~ +3.5V o 2 3 " 4 5 13 LOGIC LEVEL (HIGH) (V) 14 15 = 10-89 ! - ~ ~....................................J tSimiiar connection lor HI-5071H1-50BI HI-509 FIGURE 88_ TEST CIRCUIT FIGURE SA. ACCESS TIME VB LOGIC LEVEL (HIGH) ~ HI-506, HI-507, HI-50B, HI-509 Switching Waveforms I I I - - ,.OV I 1 VAINPUT 2VIDlV l S1 0N +10V ~"~ OUTPUT OUTPUT SVIDIV ... ----_·10V tA !-- i i SisON J 200ns/DlV fiGURE BC. WAVEfORMS fiGURE BD. ACCESS TIME fiGURE B. ACCESS TIME +15V ~ A:! VA AI +V HJ.506t IN 1 IN2THRU IN711N 15 IN 8116 Ito EN VOUT OUT ·V 200 !l SOpF tSimiiar connection for H~5071H1·508IHI·509 fiGURE 9A. TEST CIRCUIT 3,SV f-- ,, , . - - - OUTPUT A -)1-1 Il S1 0N ADDRESS DRIVE (VAl OV I I VA INPUT 2VIDlV SISON 'I I OUTPUT 1VIDlV , " ~ IV 1- toPEN 100na/DIV fiGURE 9B. WAVEFORMS fiGURE 9C. BREAK-BEfORE-MAKE DELAY ('oPEN) fiGURE 9. BREAK-BEfORE-MAKE DELAY ('oPEN) 10-90 HI-506, HI-507, HI-50S, HI-509 Switching Waveforms (Continued) +ISV At AR HI-506t IN I A, IN 2 THRU IN 711N 15 IN 8/16 +V +IOV - Ao EN VOUT OUT 50 200 0 SOpF 0 tSimiiar connec1ion for HI-S071HI-SOSlHI·S09 FIGURE 10A. TEST CIRCUIT 1 ENABLE DRIVE 3.SV 5~:.!::::....................... \.,50% : 907[* OV IoN(EN) ,I ~TPUTA '1 r-- j i ! --:.... tL ENABLE DRIVE 2VID4V - - IOFF{EN) , S, ON ] - t- S160FF i-- 1 FIGURE 10B. WAVEFORMS , S2THRU J I j i !--: I\, OUTPUT' 2VIDIV I I FIGURE 10C. ENABLE DELAY toN(EN).IoFF(EN) FIGURE 10. ENABLE DELAY 10·91 HI-S06, HI-507, HI-50S, HI-S09 Truth Tables HI-506 HI-508 EN ·ON" CHANNEL A,. AI Ao EN ·ON" CHANNEL X L None L H 1 H H 2 H L H 3 L H H H 4 5 H L L H 5 6 H L H H 6 H 7 H H L H 7 H 8 H H H H 8 L H 9 L H H 10 H L H 11 H H 12 AI Ao EN "ON" CHANNEL PAIR L L H 13 X X L None L H H 14 L L H 1 H H L H 15 L H H 2 H H H H 16 H L H 3 H H H 4 ~ A,. AI Ao X X X X L None X X L L L L H 1 L L L L L H H 2 L L L L H L H 3 L L L H H H 4 L H L L H L H L H H L H H L L H H H H L L H L H L H L H H H H H H H HI-509 HI-507 . Az AI Ao EN "ON" CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 10-92 HI-S06, HI-S07 Die Characteristics DIE DIMENSIONS: 129 mils x 82 mils METALLIZATION: Type: CuAI Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride/Silex Nitride Thickness: 3.5kA ± 1kA Silex Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 1.4 x 105 Alcm 2 TRANSISTOR COUNT: 421 PROCESS: CMOS-DI SUBSTRATE POTENTIAL": -VSUPPLY • The substrate appears resistive to the conductor at -VSUPPLY potential -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a Metallization Mask Layout Ht-506 HI-507 EN Ao At ~ NC GND ,,~ 1 '"f (J) a: >< ILl ILl IN 1 IN9 INIA INIB IN2 IN 10 IN2A IN2B IN 3 IN 11 IN3A IN3B IN4 IN 12 IN4A IN4B INS IN 13 IN SA IN6 IN 14 IN 7 IN 15 IN7A IN 8 IN 16 IN8A ..J c.. S ;:) ::::E -y OUT +y NC -y OUTA NOTE: Pad numbers correspond to DIP pin numbers only. 10-93 +Y OUTB HI-50S, HI-S09 Die Characteristics DIE DIMENSIONS: 81.9 mils x 90.2 mils METALLIZATION: Type: CuAI Thickness: 1SkA ± 2kA GLASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.SkA ± 1kA Silox Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 1.4 x 105A1cm 2 TRANSISTOR COUNT: 234 PROCESS: CMOS-OI SUBSTRATE POTENTIAL": -VSUPPLY • The substrate appears resistive to the -VSUPPLY terminal, therefore il may be left floating (Insulating Die Mount) or it may be mounted on a conduclor at -VSUPPLY potential Metallization Mask Layout HI-508 HI-509 GND EN Ao Al GND -Vsup IN1 INS IN1A IN1B IN2 IN6 IN2A IN2B IN3 IN3A IN7 IN4 OUT IN3B INa IN4A OUTA NOTE: Pad numbers correspond to DIP pin numbers only. 10-94 OUTB IN4B HI-506A, HI-507A HI-50BA, HI-509A 16 Channel, 8 Channel, Differential 8 and Differential 4 Channel, CMOS Analog MUXs with Active Overvoltage Protection December 1993 Features Description • Analog OVervoltage 70Vp.p • No Channel Interaction During OVervoltage The HI-506A, HI-007A, HI-50BA and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70V peak-to-peak levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each Input presents 1kO of resistance under this condition. These features make the HI-006A, HI-007A, HI-508A and HI-S09A ideal for use In systems where the analog Inputs originate from external eqUipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-S06A is a single 16 channel multiplexer, the HI-S07A is an 8 channel differential multiplexer, the HI-S08A is a single 8 channel multiplexer and the HI-009A is a differential 4 channel multiplexer. If Input overvoltage protection is not needed the HI-5061507/S08/509 multiplexers are recommended. For further information see Application Notes ANS20 and ANS21. • 44V Maximum Power Supply • Fall Safe with Power Loss (No Latch-Up) • Break-Before-Make Switching • Analog Signal Range ±1SV • Access Time SOOns • Power Dissipation 7.SmW Applications • Data Acquisition Systems • Industrial Controls • Telemetry The HI-SOSAlS07A devices are available in a 28 lead Plastic or Ceramic DIP and the HI-508A1S09A devices are available in a 16 lead Plastic or Ceramic DIP package. The HI-SOXA are offered In IndustriaVcommercial and military grades, additional HI-Rei screening Including 160 hour burn-In Is specified by the "8" suffix. For Mil-Std-883 compliant parts, request the HI-5461883, HI-547/883, HI-548I883 or HI-S49/883 data sheets. Ordering Information PART NUMBER TEMPERATURE RANGE 28 Lead Ceramic DIP Hll-0S08A-2 -SSoC to +12SoC 16 Lead Ceramic DIP OOCto +7SoC 28 Lead Ceramic DIP Hll-0008A-S OOC to +7S"C 16 Lead Ceramic DIP 00Cto+7SoC + 96 Hour Burn-In 28 Lead Ceramic DIP Hll-0508A-7 OOC to +75°C + 96 Hour Burn-In 16 Lead Ceramic DIP Hll-0ooSA-8 -SSoC to +12SoC + 160 Hour Burn-In 28 Lead Ceramic DIP Hll-0508A-8 -55"C to +12SoC + 160 Hour Burn-In 16 Lead Ceramic DIP HI3-0S06A-S Hll-0S07A-2 +O"C to +7S"C -SS"C to +12SoC Hll-0S07A-S PART NUMBER TEMPERATURE RANGE Hll-0ooSA-2 -SS"C to +12SoC Hll-0ooSA-5 Hll-0ooSA-7 PACKAGE PACKAGE 28 Lead Plastic DIP HI3-0508A-S +O"C to +7SoC 28 Lead Ceramic DIP Hll-0509A-2 -55"C to +12SoC OOCto +7SoC 28 Lead Ceramic DIP Hll-0509A-S OOCto+7SoC 16 Lead Ceramic DIP Hll-0S07A-7 OOCto +7SoC + 96 Hour Burn-In 28 Lead Ceramic DIP Hll-0509A-7 OOCto +7SoC + 96 Hour Burn-In lS Lead Ceramic DIP Hll-0oo7A-8 -SSoC to +12SoC + 160 Hour Burn-In 28 Lead Ceramic DIP Hll-OS09A-8 16 Lead Ceramic DIP H13-0oo7A-S OOC to +7S"C 28 Lead Plastic DIP HI3-0509A-S -SSoC to +12SoC + 160 Hour Burn-In OOCto +7SoC CAUTION: These devices are sens~ive to electrostatic discharge. Users shculd follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-95 16 Lead PlastiC DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP File Number 3143 HI-S06A, HI-S07A, HI-SOBA, HI-S09A Pinouts HI1-506A (CDIP) HI3-506A (PDIP) TOP VIEW +VSUPPLY H11-507A (CDIP) HI3-507A (PDIP) TOP VIEW 1 +VSUPPLY 17 ADDRESS 1 Ao 17 ADDRESS ' -_ _ _ _.....15 ADDRESS A2 Ao -,L-._ _ _ _--11-5 ADDRESS A2 H11-50BA (CDIP) HI3-50BA (PDIP) TOP VIEW HI1-509A (CDIP) HI3-509A (PDIP) TOP VIEW 10-96 HI-S06A, HI-S07A, HI-SOBA, HI-S09A Functional Diagrams HI·507A HI·506A r-----------------------------,OUT A 1K ,,, , IN 1 1K o-~~~----~~~,o-t-­ IN 2 o-f-"IM-----:,.....;--- ,, , •• IN 16 OUT B • 1K G-I"""""""-""!""++-DECODER! DRIVER OVERVOLTAGE CLAMP AND SIGNAL ISOLATION OVERVOLTAGE CLAMP AND SIGNAL ISOLATION • DIGITAL INPUT PROTECTION • DIGITAL INPUT PROTECTION HI·50BA 1K IN1 1K IN2 INa •• • HI·509A OUT ~ !-IN4A DECODER! DRIVER OUT A 1K IN1A •• 1K OUT B 1K IN1B 1K IN4B •• 1K OVERVOLTAGE CLAMP AND SIGNAL ISOLATION OVERVOLTAGE CLAMP AND SIGNAL ISOLATION • DIGITAL INPUT PROTECTION • DIGITAL INPUT PROTECTION 1()"97 DECODER! DRIVER HI-506A, HI-507A, HI-SOBA, HI-S09A Schematic Diagrams ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT -- ... ,,, ,, ,, , ,,, : -- ... --- ... ---.. V+ : , ,,, ,, , , .. :Q1 ~.-~~ , :.. _____ -~ ~'!'? :: :, , :, :, ___ J LEVEL SHIFTER OVERVOLTAGE PROTEcnON LEVEL SHIFTED ADDRESS TO DECODE r--------.. . .: : V+ : :' ,~ ,~ : R1 :' :200 : n v- : '-!'----------' !---- ---_ . . . .' ;...................................... -_ . . . ---_ .. --_. . . . . . -----_ ............... -_ . . _.................... -_ ....................................... _............. -_ . . .. : ADD IN ADDRESS DECODER TO NoCHANNEL DEVICE OF THE SWITCH AzORAz ENABLE Aa DELETE As OR INPUT FOR HI-507A AND HJ.609A 10-98 HI-S06A, HI-507A, HI-SOBA, HI-S09A Schematic Diagrams (Continued) MULTIPLEX SWITCH FROM DECODE >>--------------1~--------------~--, OVERVOLTAGEPROTECTION N ~... • ••• ••• . ------ . ------- . ------- ··••• • : : ----- .. ----------- R11 1K IN 1-~.--'lMr-+--. ·•••• • • •• • •• · ·! ~_r-----¥~-------;_--. • ··;------------_ .. _-------_.. ---- .... _-_ .. ------ ...: FROM DECODE >.>-______..._______...J 10-99 Specifications HI-506A, HI-S07A, HI-SOBA, HI-S09A Absolute Maximum Ratings Thermal Information VSUPPLY(+) to VSUPPLY(.)' •••••••••••••••••••••••••••••• +44V VSUPPLY(+) to GND •••••••••••••••••••••.••••.••••••• +22V VSUPPLY(.) to GND ••••••••••••••••••••••••••••••••••• +25V Digital Input OVervoltage +VEN. +VA •••••••••••••••••••••••••••••••• +VSUPPLY +4V -VEN • -VA' ••••••••••••••••••••••••••••••••• -VSUPPLy -4V or 2OmA. whichever occurs Ilrst Analog Signal Overvoltage +Vs ••••••••••••••..••••••••••.••••••••• +VSUPPLY +20V -Vs ••••••••••••••••••••••••••••••••.••••• -VSUPPLY -20V Continuous Current. S or 0 ••••••••.•••••••••••••••••• 20mA Peak Current. S or 0 ................................ 40mA (PUlsed at 1ms. 10% duty cycle max) Storage Temperature Range •••••.••.••••.••• -65°C to +150°C Lead Temperature (Soldering lOs) ..•.......•.•....•.• +3000C Thermal Resistance 9JA 9JC 28 Lead Ceramic DIP Packages (HI-506A. HI-507A) ••••••••••••.•••• 200c1'N 55°CI'N 16 Lead Ceramic DIP Packages (HI-508A. HI-509A) ••••••••••••••••• 24°CI'N 800CI'N 28 Lead Plastic DIP Packages (HI~506A. HI-507A) •••••••••••••••••••••••••• • 600c1'N 16 Lead Plastic DIP Packages (HI-50BA. HI-509A) •••••••••• • • • • • • • • • . • • • • •• 1000CI'N Operating Temperature Ranges HI-506A1507Al50BA/509A-2. -8 ..........•... -5500 to +1250 C HI-506A1507Al50BA/509A-5. -7 •.••.••••.•.••.• OOC to +75 °C Junction Temperature Ceramic DiP •••••••••••••••.•.••••••••••••••••• +1750 C Plastic DIP ••••••••••••••••••••••••••••.••••••.• +1500C CAUTION: Stresses above /hose listed in "Absolute Maximum Ratings" may cause permanent damage to the davlce. This is a stress only rating and operation of the device at these or any other conditions above those indicated In the operational sectlons of this specification is not ImpHed. Electrical Specifications Supplies =+15V. -15V; VREF Pin =Open; VAH (Logic Level High) = +4.0V; VAL (Logic Level Low) =+O.8V. Unless Otherwise SpeCified. For Test Conditions. Consult Performance Curves. HI-50XA-5,-7 HI-50XA-2,-8 MIN TVP +25OC - 0.5 Full - - Break-Belore-Make Delay. !oPEN (Note 1) +25OC 25 80 Enable Delay (ON)'!oN(EN) (Note 1) +25"C - PARAMETER TEMP MAX MIN TYP - - 0.5 - - 25 80 - ns MAX UNITS - lIS 1.0 lIS SWITCHING CHARACTERISTICS Access Time. tA (Nola 1) Full Enable Delay (OFF)'!oFF(EN) (Note 1) +25°C t.O - 300 500 - 300 1000 - - - ns - 1000 ns 300 500 300 - ns - - 1000 1000 ns Full - SeWing Time to 0.1%. Is (HI-50BA and HI-507A) +25°C - Settling Time to 0.01%. Is (HI-50BA and HI-507A) +25OC Settling Time to 0.1 %. Is (HI-50BA and HI-509A) +25°C - 1.2 Settling Time to 0.01 %.Is (HI-508A and HI-509A) +25OC - 3.5 'Off Isolallon" (Note 6) +25OC 50 68 Channel Input Capac Hance. CS(OFF) +25OC - Channel OUtput CapaCitance. CO(OFF) (HI-506A) +25OC Channel Output Capacitance. CO(OFF) (HI-507A) +25°C Channel Output Capacitance. CO(OFF) (HI-508A) +25°C - Channel OUtput CapaCitance. CO(OFF) (HI-509A) +25"C Digital Input Capacitance. CA Input to Output Capacitance. COS(OFF) 1.2 3.5 12 52 30 - - - 25 - - 12 - +25"C - 10 - +25"C - 0.1 - - +0.8 - - - 1.2 - 3.5 - 1.2 - lIS - 3.5 50 68 - dB - - - 12 - lIS lIS lIS pF 30 - pF 25 - pF 12 - pF 10 - pF 0.1 - pF 52 pF DIGITAL INPUT CHARACTERISTICS Input Low Threshold. TTL Drive. VAL (Note 1) Full - Input High Threshold. VAH (Notes 1. 8) Full +4.0 Input Leakage Current (High or Lowl. IA (Notes 1. 5) Full - MOS Drive. VAL. HI-50BA/HI-507A (Nola 9) +25OC - - MOS Drive. VAH • HI-506AIH1-507A (Nola 9) +25°C 6.0 - 10-100 1.0 0.8 - +4.0 - 6.0 - +0.8 V - - V 1.0 IlA - 0.8 V - - V Specifications HI-S06A, HI-S07A, HI-SOBA, HI-S09A Electrical Specifications = = = Supplies +15V, -15V; VREF Pin Open; VAH (Logic Level High) +4.0V; VAL (Logic Level Low) = +a.BV, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves. (Continued) HI-SOXA-2, -8 PARAMETER HI-SOXA-5, -7 TEMP MIN TVP MAX MIN TYP MAX UNITS Analog Signal Range, Vs (Note 1) Full -15 - +15 -15 +15 V On Resistance, RoN, (Notes 1, 2) +25°C - 1.2 1.5 1.5 1.B lin Full - - - 1.5 1.B 1.B 2.0 kO +25OC 0.03 - 0.03 nA - 50 - - 0.1 - 0.1 - 300 - 200 4.0 ANALOG CHANNEL CHARACTERISTICS HI-50SA Full - HI-507A Full - HI-50BA Full - Full - +25°C - Off Input Leakage Current, IS(OFf) (Notes 1, 3) Full Off Output Leakage Current, 100oFF) (Notes 1, 3) HI-509A With Input Overvoltage Applied, (looFF) (Note 4) +2SoC Full On Channel Leakage Current, IO(ON) (Notes 1, 3) +2SOC - - - 100 - 4.0 - - - 2.0 - 0.1 200 - - - - 50 nA - nA 300 nA 200 nA 200 nA 100 nA - - nA j1A 0.1 - - 300 nA - 200 nA nA - 300 Full - - 200 HI-50BA Full - - 200 - 200 nA HI-509A Full - - 100 - - 100 nA 50 - - 50 nA 1.5 2.0 1.5 2.4 0.02 1.0 7.5 - HI-50SA Full HI-507A Differential Off Output Leakage Current, IOIFF. (HI-507A, HI-509A Only) Full POWER REQUIREMENTS Current, 1+, Pin 1 (Notes 1, 7) Full Current, 1+, HI-508AIH1-509A (Notes 1, 7) Full Current, 1-, Pin 27 (Notes 1, 7) Full Power Dissipation, Po Full - - 1.5 2.0 mA 1.5 2.0 mA 0.02 1.0 mA 7.5 - mW NOTES: 1. 100% tested lor Dash B. Leakage currents not tested at -55°C. 2. VOUT=±10V,loUT= +100j1A. 3. Ten nanoamps Is the practical lower limit lor high speed measurement in the production test environment. 4. Analog Overvoltage = ±33V. 5. Digital Input leakage Is primarily due to the clamp diodes (see Schematic). Typical leakage Is less than 1nA at +25°C. S. VEN = O.BV, Rl = 11<, Cl = 15pF, Vs = 7VRMS, I = 100kHz. 7. VEN , VA =OVor4.0V. B. To drive from DTLlTTL Circuits, lkO pull-up resistors to +5.0V supply are recommended. 9. VREF = +10V. 10-101 HI-506A, HI-50'7A, HI-50BA, HI;.509A Performance Curves and Test Circuits TA = +25OC, VSUPPLY = ±15V, v AH = +4V, vAL = O.BV, VREF = Open, Unless Otherwise Specified +-_ _ -100"" I V2 I OUT IN ;!~ V~ Flo -'- - FIGURE 1A. TEST CIRCUIT 1.4 TA-+125"C I I ~ 1.2 ~ I I I I +125"C;,TA;'.u"C_ VIN-..sV " i"'I., ~ 1.1 ~ 1.0 TA-+25OC iiia: 0.9 TA,,-55"C I/) " i!io.a 0.7 . -2 0 +2 +4 ANALOG INPUT (V) .... +8 +8 0.8 +10 FIGURE 1 B. ON RESISTANCE V8 ANALOG INPUT VOLTAGE ±6 ±6 ±7 ...... ~ ±8 ±II ±10 ±11 ±12 ±13 ±14 ±15 SUPPLY VOLTAGE M FIGURE 1C. NORMALIZED ON RESISTANCE V8 SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA 10nA ... zw OFF OUTPUT CURRENT ID(OFF) ON LEAKAGE a: a: • :::0 u w 1nA i CURRENT ID(ONl ..... ~ 100pA /" /' 50 // 1I t~ / ' /""-. - =: ~~- =- ±10V OFFINPUT LEAKAGE CURRE~ IscoFF) :: 75 100 TEMPERATURE <"CI a .J- 125 FIGURE 2A. LEAKAGE CURRENT V8 TEMPERATURE FIGURE 2B. ID(OFF) (NOTE 1) NOTE: 1. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V) FIGURE 2. LEAKAGE CURRENTS 10-102 A ID(OFF) = J =F1OV HI-S06A, HI-S07A, HI-SOBA, HI-S09A Performance Curves and Test Circuits I'J = ±10V TA = +250 C. VSUPPLY =±15V. VAH = +4V. vAL = O.BV. VREF = Open. Unless Otherwise Specified (Continued) OUT OUT •• = J - +II.8V •• EN EN J ±10V "'1OV +2.4V FIGURE 20. 10(00) TEST CIRCUIT (NOTE 1) FIGURE 2C. lS(oFF) TEST CIRCUIT (NOTE 1) NOTE: 1. Two measurements per channel: ±10V and :;:10V. (Two measurements per device for IO(OFF) ±10V and :;:10V) FIGURE 2. LEAKAGE CURRENTS (Continued) A IO(OFF) = J ±15 ±18 ±21 ±24 ±27 ±30 ±VIN :t33 ANALOQINPUTOVERVOLTAGE~ FIGURE 3A. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS FIGURE 3B. TEST CIRCUIT FIGURE 3. OVERVOLTAGE CHARACTERISTICS ±14 -650 ±12 0 ±2 o i/ o ~ ±2 V d. r b ~ v" .....250 C ~ VI ~ V"+125oC ±4 ±6 ±8 ±10 ±12 VOLTAGE ACROSS SWITCH (V) ±14 FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT FIGURE 4. ON CHANNEL CURRENT 10-103 HI-506A,. HI.;.507A, HI-50BA, HI-509A Performance Curves and Test Circuits TA =+250C, VSUPPLY =±15V, VAH =+4V, vAl =o.av, VREF =Open, Unless Otherwise Specified (Continued) 8 I +V INl Aa ~--'-1-~Aa JI VaUPPLy·±l&'{, VSUPPLy·±10V, ""- lK 10K lOOK TOGGLE FREQUENCY (Hz) ±10VI±5V IN2~~--~ At IN 7~:~ .......~__-' Au IN &liN 18 '" 10Vl'" SV +4V ..,.. (7 o HI-606At 10 MO 1M 10M -15V1-10V t Similar connection for HI-507AlHI-508AIH1-509A FIGURE SA. SUPPLY CURRENT va TOGGLE FREQUENCY FIGURE 58. TEST CIRCUIT FIGURE 5. SUPPLY CURRENTS +15V VREF VREF'" OPEN FOR LOGIC HIGH LEVEL S 6V ....oS. 800 As I- VREF =LOGIC HIGH FOR LOGIC HIGH LEVELS> 6lL .---.....-+-1 Aa +V INl I~N2;J;~~~ ......- - - . , w 700 :Ii HI-508At ~ 600 m w 1= IN16 \ ~ 500 ....... 400 300 3 4 +4V ....... .... S 8 7 8 8 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 15 t Similar connection for HI-507AlHI-580AIHI-509A FIGURE 6A. ACCESS TIME va LOGIC LEVEL (HIGH) FIGURE 68. TEST CIRCUIT FIGURE 6. ACCESS TIME Switching Waveforms I I I I-- _ VAINPUT 2VIDIV OV r +10V OUTPUT \,,90% \ - - - -_ _10V --. tA 1-- OUTPUT SVIDIV I FIGURE 7. ACCESS TIME 10-104 AI I J \ 200nsIDIV FIGURE 78. FIGURE7A. I HI-S06A, HI-S07A, HI-SOBA, HI-SOBA Switching Waveforms ~ (Continued) ~ HI-506At At IN1 HI-506At At IN1 IN2THRU IN711N 15 IN811N16 IN2THRU AI IN711N 15 AI Ao IN IIIN 16 Ao +4_0V EN OUT 1k SOpF n lk SOpF n t Similar connection for HI-507Al/HI-50BAlHI-509A FIGURE9A_ 1'------l . In VAH=4_0V ADDRESS DRIVE (VAl 5O%---0-V- I OUTPUT i ~UTPUT ! ! ..j toN(EN) FIGURE8B_ I OUT n FIGURE8A_ r---- - 50 -VA t Similar connection for HI-507AlHI-50BAlHI-509A OV +10V -- i --..! toFF(EN) ~ FIGURE9B_ ~ ~\ I VA INPUT 2VIDIV I 10N 160N I( 1\ , ~UTP~~\ O_SVIDIV 10N / I r-- INI THRU ~I V ( OUTPUT \ 2VIDIV I I IN 16 OFF 100nsJDIV 100nsJDIV " FIGURE8C_ FIGURE9C_ FIGURE 8_ BREAK-BEFORE-MAKE DELAY FIGURE 9_ ENABLE DELAY toN(EN)' toFF(EN) 10-105 HI-506A, HI-507A, HI-50BA, HI-509A Truth Tables HI-506A HI·SOBA A3 A, At Ao EN "ON" CHANNEL A, At Ao EN "ON" CHANNEL X X X X L None 'IX X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H . L H 11 H L H H H 12 At Ao H H L L H 13 X H H L H H 14 L H H H L H 15 L H H H H H 16 HI·S09A HI·S07A EN "ON" CHANNEL PAIR X L None L H 1 L H H 2 H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 Az At Ao X X L L L L 10·106 EN "ON" CHANNEL PAIR X L None L H 1 H H 2 H L H 3 H H H 4 HI-506A, HI-507A Die Characteristics DIE DIMENSIONS: 159 mils x 83.9 mils x 19 mils METALLIZATION: Type: CuAI Thickness: 16kA ± 2kA GLASSIVATION: Silox: 12kA ± 2kA Nitride: 3.5kA ± 1kA WORST CASE CURRENT DENSITY: 1.4 x 1Q5A1cm 2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI SUBSTRATE POTENTIAL": -VSUPPLY • The substrate appears resistive to the -VSUPPLY terminal, therefore It may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential Metallization Mask Layout HI-506A HI-507A Al A:z GND en a:: IN1 (19) W >< W IN2 (20) ..J D.. 5::l IN3 (21) IN 11 (II) IN4 (22) IN 12 (8) == INS (23) INS (24) INSB (7) IN6B (6) V-(27) 10-107 OUT A (28) +V (1) HI-SOBA, HI-S09A Die Characteristics DIE DIMENSIONS: 108 mils x 83 mils METALLIZATION: Type:CuAI Thickness: 16kA±2kA GLASSIVATION: Silox: 12kA ± 2kA Nitride: 3.5kA ± 1kA WORST CASE CURRENT DENSITY: 1.4 x 105Alcm 2 TRANSISTOR COUNT: 253 PROCESS: CMOS-OI SUBSTRATE POTENTIAL·: -VSUPPLY • The substrate appears resistive to the -VSUPPLY terminal, therefore It may be left floating (Insulating Die Mount) or It may be mounted on a conductor at -VSUPPLY potential Metallization Mask Layout HI-50BA HI-S09A OUT A INS (12) +V (13) GND +V (14) (14) Az (15) Al (16) Ao EN GND (1) (2) (15) 10-108 Al (16) Ao EN (1) (2) HI-516 16 Channel/Differential 8 Channel CMOS High Speed Analog Multiplexer December 1993 Features Description • Access Time (Typical) 130ns The HI-516 is a monolithic dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual function of address input A3 enables the HI-516 to be user programmed either as a single ended 16-channel multiplexer by connecting 'out A' to 'out B' and using A3 as a digital address input, or as an 8-channel differential multiplexer by connecting A3 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Harris Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (lOOFF < 100pA at +25°C) and fast settling (tSETILE =800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. • Settling Time 250ns (0.10/0) • Low Leakage (Typical) • IS(OFF) 1OpA • IO(OFF) 30pA • Low Capacitance (Max) • CS(OFF) 10pF • CO(OFF) 25pF • Off Isolation at 500kHz 55dB (Min) • Low Charge Injection Error 20mV • Single Ended to Differential Selectable (SDS) For MIL-STD-883 compliant parts, request the HI-5161883 data sheet. • Logic Level Selectable (LLS) Ordering Information Applications • Data Acquisition Systems • PreciSion Instrumentation • Industrial Control PART NUMBER H14P0516-5 HI3-0516-5 Hll-0516-5 Hll-0516-2 Hll-0516-8 HI4-0516-8 H19P0516-5 H19P0516-9 HI1-05161883 HI4-05161883 TEMP. RANGE OOC 10+75°C OOC 10+75°C OOC 10+75OC -55°C 10 +125°C -55°C 10 +125°C -55°C 10 +125OC DOC 10+75°C -4QDC to +85°C -55°C to +125OC -55°C to +125°C PACKAGE 28 Lead PLCC 28 Lead Plaslic DIP 28 Lead Ceramic DIP 28 Lead Ceramic DIP 28 Lead Ceramic DIP 28 Lead Ceramic LCC 28 LeadSOIC 28 Lead SOIC 28 Lead Ceramic DIP 28 Lead Ceramic LCC Pinouts HI-SI6 (CDIP, PDlP, SOIC) TOP VIEW HI-S16 (LCC, PLCC) TOP VIEW ID s ~ iE NC IN 1618B IN1S17B 5 ID (J z C I- l- ::> 0 :t ::> 0 ::I- i iE _, l~J l!J L!J t~J l~8J t~J l!.~ r- IN 1S17B !J t~s IN 7nA IN 616A IN 515A IN 414A IN 313A IN 212A -, 111 • ..1 r-~ r-., r-., r-., r-, ,.-., r-., 119 L. '12' '13' '14' '15' '16' '17' '18' CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright toFF(EN) +1SV +2.4V EN Vo r--+--:~~ 0--=:..:................-0 -!- FIGUREBA. FIGURESB. I!N0 is the measured voltage error due to charge injection. The error voltage In coulombs is a = CL X INo FIGURE S. CHARGE INJECTION TEST CIRCUIT 10·114 Vo CL=100pF HI-516 Die Characteristics DIE DIMENSIONS: 2250llm x 3720llm x 485~ ±251lm METALLIZATION: Type: CuAI Thickness: 1SkA ± 2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA ± 1kA Silox Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 1.64 x 105A/cm2 Metallization Mask Layout HI-516 ENABLE Ao AI . Az (18) (17) (16) (15) ~/sDS (14) VDDIl.LS GND (13)· (12) IN lf1A (19) (10) IN 9f1B IN 2I2A (20) IN 3I3A (21) (8) IN 1113B IN 414A (22) (7) IN 1214B en a:: w >< W ..J a.. S :;:) IN 515A (23) (6) IN 13J5B IN6I6A (24) (5) IN 14J6B INmA(2S) (4) IN 15nB IN 8/8A (26) (3) IN 1618B (27) (28) (1) (2) -V OUlA +V OUlB 10-115 :::& HI-518 8 Channel/Differential 4 Channel CMOS High Speed Analog Multiplexer December 1993 Features Description • Access Time (Typical) 130ns The HI-518 is a monolithic dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an Inhibit input for disabling all channels. The dual function of address input ~ enables the HI-518 to be user programmed either as a single ended 8-channel multiplexer by connecting 'out A' to 'out S' and using A2 as a digital address input, or as a 4-channel differential multiplexer by connecting A2 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Harris Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (IOOFF < 100pA at +25°C) and fast settling (tSETTLE BOOns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. • Settling Time 250ns (0.1%) • Low Leakage (Typical) - IS(OFF) 10pA - 1D(0FF) 15pA • Low Capacitance (Max) - CS(OFF) 5pF - CO(OFF) 10pF • Off Isolation at 500kHz 45dB (Min) • Low Charge Injection Error 25mV • Single Ended to Differential Selectable (SDS) • Logic Level Selectable (LLS) Applications • Data Acquisition Systems • Precision Instrumentation • Industrial Control = Ordering Information TEMP. RANGE PART NUMBER HI3-0518-5 HI1-0518-5 HI1-0518-2 HI1-0518-8 H14P0518-5 HI4-0518-8 HI1-0518-9 HI3-0518-9 HI4P-0518-9 H19P-0518-5 HI9P-0518-9 PACKAGE 18 Lead Plastic DIP 18 Lead Ceramic DIP 18 Lead Ceramic DIP 18 Lead Ceramic DIP 20 Lead Plastic PLCC 20 Lead Ceramic LCC 18 Lead Ceramic DIP 18 Lead Plastic DIP 20 Lead PlastiC LCC 18 LeadSOIC 18 Lead SOIC DOC to+75OC OOCto +75°C -55°C 10 +1250C -55°C to +125°C DOClo+75OC -55°C to +125OC -4DOC to +85°C -4DOC to +85OC -4OOC 10 +85°C 000to+75°C -4OOC to +85OC Pinouts HI-518 (CDIP, PDIP) TOP VIEW HI-518 (LCC, PLCC) TOP VIEW < ID 50 -., IN8I4B IN7138 IN6I2B IN5I1B GND + ll.J la..J .!J -., !J -., !J -., lJ -., !J CAUTION: These devices are sensitive \0 electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harrls Corporation 1993 10-116 () >. z 50 l~J l~o.J :> ltll.J r- l!.B IN4I4A [!'r IN3I3A [~6 IN2I2A r1~ IN111A Lo- r- 114 ENABLE Lo_ File Number 3147 HI·518 Functional Block Diagram IN 1A EN OUT A IN4A IN1B .....--i_-+.. INPUT BUFFER AND DECODERS MULTIPLEXER SWITCHES A 2 DECODE ~ Q a H H L L L H v- L L 10-117 OUT B Specifications HI-518 Absolute Maximum Ratings (Note 1) Thermal Information V+to V- ..•..•••••••••..•••.••••••••••.•••.•••••.••• 33V Analog Input Voltage +VIN •.•.•..•••.•••.•.•••..•••••••.•••••••••• (V+) +2V -V1N ••.•••.•••••...•...•••.••••••••..••..••••• (V-) -2V Digital Input Voltage TTL Levels Selected (VoolLLS Pin = GND or Open) +VA .•.•......••...••..•••..•••••••.•••..•••••••• +6V -VA ..•.....•..•....•..•..••..•..•.•.••••••••••••.•-6V +A:!ISDS ••.••.•.••.•..••••••••••••.•••••••••• (V+) +2V -A:!ISDS ••••••••••••••••.•..•••..•••••••..•••• (V-) -2V CMOS Levels Selected (VoolLLS Pin = Voo) +VA......................................... (V+) +2V -VA" .•.••.•••••••••••.....•••.•.••••.••.•••••••• -2V Storage Temperature Range ••••••••••••••••• -65°C to +150oC Lead Temperature (Soldering 10s) .••••••••..•••••.••• +300oC Thermal Resistance 9JA 90"CfIN Plastic DIP Package •••••••••••••.•• Plastic PLCC Package .............. . SO"CfIN 77"CfIN Ceramic DIP Package .............. . 23°CfIN 650 CfIN . Ceramic LCC Package .••..•.••••••• 12°CfIN SOIC Package .•...•.•.•••••••.•••. 1000 CfIN Junction Temperature Ceramic DIP, Ceramic LCC ........................ +1750 C Plastic DIP, Plastic PLCC, SOIC .................... +150oC Operating Temperature Ranges HI-51S-2,-S ............................. -55°C to +125°C HI-518-5 .•••••••••.••••••••••••••••••••••• O"C to +750 C HI-51S-9•••.•.••••.•••••••••••••••••.•.•• -4O"C to +85°C CAUTION: Stresses above those listed in 'Absolute Maximum Ratings' may cause pflfmanent damage to the device. This Is a stress only rating and operation a/the device at these or any other condmons above those indicated in the operational sections 0/ this specification is not Implied. Electrical Specifications Supplies =+15V, -15V; VAH (Logic Level High) = +2.4V, VAL (Logic Level Low) =+O.SV; VoolLLS = GND. (Note 1), Unless Otherwise Specilied. PARAMETER TEST CONDITIONS I HI-518-2. -8 TEMP HI~18-5.-9 MAX MIN TYP 130 175 - 130 175 ns - 225 - - 225 ns 10 MIN TYP - MAX UNITS SWITCHING CHARACTERISTICS Access Time, tA +25OC Full - Break-Belore-Make Delay, \oPEN +25°C 10 20 20 - ns +25°C - - Enable Delay (ON), \oN(EN) 120 175 120 175 ns Enable Delay (OFF), \oFF(EN) +25°C - 140 175 140 175 ns 0.1% +25OC - 250 - ns +25°C - 250 0.01% 800 ns - 25 mV - dB - 5 pF - 10 pF - Settling Time - 25 45 - - 5 - +25OC - - 10 - Digital Input Capacitance, CA +25OC 5 - +25OC - - ·Input to Output Capacitance, COS(OFF) 0.02 - Charge Injection Error Note 4 +25OC - Off Isolation Note 5 +25°C 45 Channel Input Capacitance, CS(OFF) +25°C Channel Output CapaCitance, CO(OFF) 800 - - 5 pF - 0.02 - pF - - O.S V - V 0.3Voo V - V DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL (TTL) Full - Input High Threshold, VAH (TTL) Full 2.4 Input Low Threshold, VAL (CMOS) Full Input High Threshold, VAH (CMOS) Full O·7Voo - - 0.7Voo Input Leakage CUffent, IAH (High) Full - - - 1 IIA Full - 1 Input Leakage Curfent, IAL (Low) 20 - - 20 IIA 10-118 O.S - - - 0.3Voo 2.4 - - - Specifications HI-518 Electrical Specifications Supplies =+15V, -15V; VAH (Logic Level High) =+2.4V, VAL (Logic Level Low) =+0.8V; VooiLLS (Note 1), Unless Otherwise Specified. (Continued) TEST CONDITIONS PARAMETER HI-518-5, -9 HI-518-2, -8 TEMP I MIN =GND. I MIN MAX TVP UNITS TVP MAX +14 -15 - +15 V 480 750 480 750 D - - 1,000 - - 0.01 ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN Note 2 Full -14 On Resistance, RON Note 3 +25°C Off Input Leakage Current, IS(OFF) +25°C - Full - Off Output Leakage Current, IO(OFF) +25°C On Channel Leakage Current, IO(ON) +25°C Full Full Full - - 50 - - 0.Q15 - 50 - 0.015 - - 50 - - 450 1,000 D 0.01 - nA - 50 nA 0.015 nA - - 50 nA 0.Q15 - nA 50 nA - - 540 mW 18 mA 18 mA - POWER SUPPLY CHARACTERISTICS Power Dissipation, Po Full 1+, Current Note 6 Full 1-, Current Note 6 Full 15 15 NOTES: 1. VooiLLS pin = open or grounded lor TTL compatibility. VooiLLS pin = Voo lor CMOS compatibility. 2. At temperatures above +9OOC, care must be taken to assure VIN remains at least 1.0V below the VSUPPLY lor proper operation. 3. VIN = ±10V, lOUT = -100jiA. 4. VIN =OV, CL =l00pF, enable input pulse =3V, I =500kHz. 5. CL =40pF, RL =1k. Due to the pin to pin capacitance between IN 8I4B and OUT B, channel 8I4B exhibits 60dB 01 OFF isolation under the above test conditions. 6. VEN = +2.4V. TRUTH TABLE HI-518 Used as an 8-Channel Multiplexer or 4-Channel Differential Multiplexer ON CHANNEL TO Az CONNECT TO V- SUPPLY Ao OUT A OUTB ENABLE A1 X None None L X USE A2 AS DIGITAL ADDRESS INPUT ENABLE Az A1 L X X TRUTH TABLE HI-518 Used as a Dlfferential4-Channel Multiplexer ON CHANNEL TO Ao OUT A OUTB X None None H L L L lA None H L L lA lB H L L H 2A None H L H 2A 2B H L H L 3A None H H L 3A 3B H H H 4A 4B H L H H 4A None H H L L None lB H H L H None 2B H H H L None 3B H H H H None 4B 10-119 HI-518 Test Circuits -louT 100,.A o.av EN OUT ....- - - V2 RoN" 100~A = ±10V:. -!- FIGURE 1. ON RESISTANCE VI INPUT SIGNAL LEVEL .~ 'l'10V FIGURE 2. ID(OFF) (NOTE 1) OUT OUT EN A 1o(0N) +O.8V ±10V ~ 'l'1OV= ~ 'F10V : . ±1OV ~ FIGURE.3. IS(OFF) (NOTE 1) 2.4V -!- FIGURE 4. Io(ON) (NOTE 1) +15V V+ . ' - - - - OV PROBE +10V OUTPUT ! \ ! -l )-.. _-8,.;,V;.... _ _ _ _ .10V tA !-- FIGURE SA. FIGURESB. FIGURE S. ACCESS TIME NOTE: 1. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V) 10·120 HI-518 Test Circuits (Continued) +15V V+ +SV IN1 ¥DS ADDRESS DRIVE (VAl IN 2·7 OV VA At 5~V"S-~--- OUTPUT A INa Ao OUT 2AV Vour aoo 12.5pF n --i i-- tOPEN - FIGURE6A. FIGURE6B. FIGURE 6. BREAK·BEFORE·MAKE DELAY ('oPEN) +15V 3.5V 5~-m--m--\5_~ V+ ... _ _ _ _ OV --: , OUTPUT A ,, ,,, , ,, tON(EN) :.- : AiSDS , 12.5pF - - tOFF(EN) : - - FIGURE7A. FIGURE7B. FIGURE 7. ENABLE DELAY 'oN(EN» 'oFF(EN) +15V +2AV 3.0V OV EN--AVO Vo FIGURE SA. FIGURESB. I!.Vo is the measured voltage error due to charge injection. The error voltage in coulombs is Q =CL X I!.Vo FIGURE S. CHARGE INJECTION TEST CIRCUIT 1()"121 HI-518 Die Characteristics DIE DIMENSIONS: 89x93 mils METALLIZATION: Type: AI Cu . Thickness: t6kA ±2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.qkA ±1.DkA Silox Thickness: 12kA ± 2.0kA WORST CASE CURRENT DENSITY: 1.43 x 105Ncm2 TRANSISTOR COUNT: 356 PROCESS: CMOS-DI SUBSTRATE POTENTIAL": -VSUPPLY * The substrate appears resistive to the -VSUPPlY terminal, therefore it may be left floating (Insulating Ole Mount) or it may be mounted on a conductor at -VSUPPlY potential Metallization Mask Layout HI-518 EN VDoILLS GND IN lilA IN 5I1B IN 212A IN6I2B IN 313A IN 713B IN 414A IN 8I4B 10-122 HI-524 4 Channel Wideband and Video Multiplexer December 1993 Description Features • • • • The HI-524 Is a four channel CMOS analog multiplexer designed to process single-ended signals with bandwidths up to 10MHz. The chip includes a 1 of 4 decoder for channel selection and an enable input to inhibit all channels (chip select). Crosstalk (10MHz) < -SOdB Fast Access Time 150ns Fast Settling Time 200ns TTL Compatible Three CMOS transmission gates are used in each channel, as compared to the single gate in more conventional CMOS multiplexers. This provides a double barrier to the unwanted coupling of signals from each input to the output. In addition, Dielectric Isolation (01) processing helps to insure the Crosstalk Is less than -SOdS at 10MHz. Applications • • • • Wldeband Switching Radar TV Video ECM The HI-524 is designed to operate into a wideband buffer amplifier such as the Harris HA-2541. The multiplexer chip includes two ·ON" switches In series, for use as a feedback element with the amplifier. This feedback resistance matches and tracks the channel RoN resistance, to minimize the amplifier Vos and its variation with temperature. Ordering Information PART NUMSER HI1-0524-5 HI1-0524-2 H14P0524·5 HI3·0524-5 HI1·0524-8 HI4·0524-8 HI1-05241883 HI4-05241883 Pinouts TEMP. RANGE OOC to+75°C -55°C to +125°C OOC to +75°C OOC to+75°C -55°C to +125°C -55°C to +125°C -55°C to +125°C -55°C to +1250C (COIP, PDIP) TOP VIEW PACKAGE 18 Lead Ceramic DIP 18 Lead Ceramic DIP 20 Lead PLCC The HI-524 is well suited to the rapid switching of video and other wideband signals in telemetry, instrumentation, radar and video systems. 18 Lead Plastic DIP 18 Lead Ceramic DIP 20 Lead LCC 18 Lead Ceramic DIP 20 Lead LCC For MIL-STD-883 compliant parts, request the HI-5241883 data sheet. Functional Diagram tn a:: w INI >< a.. FB(IN) W ..I 5 SIGGND IN2 ;:) ::E FB(OUT) SIGGND OUTPUT IN3 (LCC, PLCC) TOP VIEW I- S _. SIGGND 41 SIGGND 51 IN4 SIGGND IN3 .. z ~ ~ 0::- If =:- SIGGNO IN4 l~J l~J l~J •• " 1... SIGGND SIGGND -15V SUP +15V EN GND CAUTION: These devices are sansnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-123 Ao Al File Number 3148 Specifications HI-524 Thermal Information Absolute Maximum Ratings Voltage Between Supplies ••••••••••••••.•••••••••••••• 33V Thermal Resistance 8JA Ceramic DIP Package ••••••••••••••• 80"CNI Digital Input Voltage 7SOCNI LCC Package •••••••••••••••••••.•• +VA •••••••••••••' •••••••••••••••••••••••••••••••• +6V Plastic DIP Package •••.•••••••••••• 900 CNI -VA ..•••••• ; •••••••••...••••••••••••••••••••••••• -6V PLCC Package ••.••.••.••••••••.•• BO"eNl Analog Input Voltage +V1N •..••.•••.•.••.••••••.•••..••••••••• +VSUPPLY +2.OV Operating Temperature Range HI-S24-2, -8 .•..•••••.••..•.•.••..••••••• -SSoC to + 12SoC -VIN ••.••.•...•..•.....•..••••..••.•••.•• -VsUPPLy·2.OV HI-S24-S ••••••••.••••.••.••••••••..••.•••• O"C to +7SoC Either Supply to Ground ••••••...••••.•••.•••••••••••. 16.SV Junction Temperature •••• : .•.•••.•..•.••..••.•.•••• +17SoC Storage Temperature (CDIP, CLCC) •...••••.•..••.••.•.•.•••••••••••• +17SoC (CDIP, CLCC) .•••..•••••..••.••.••.••••. -6SoC to +150oC (PLCC) ••••••••••.••.•..••.••.•••••...• -6SoC to +150oC (PLCC, PDIP) •.••.••.••••.•••••••..•••••••••••• +15O"C Lead Temperature (Soldering, lOs) ..••••••.•••••••••• +3OOoC CAUTION: stressss above those listed In "Absolute Maximum Ratings" may cause parmanent damage to the daonc.. This Is a stress only tating and opetation otthe dBonc. at these or any other conditions above those indicated in the opetationsl sections of this specifICation Is notimpHBd, Electrical Specifications = Supplies +15V, -ISV; VAH (Logic Level High) Unless Otherwise Specified =+2.4v, VAL =(Logic Level Low) =+O.SV; VEN =+2.4V, HI-524-S HI-S24-21-8 TEST CONDITIONS TEMP MIN TVP MAX MIN TVP MAX UNITS Access Time, tA (NoteS) +2SoC 300 +2SoC 20 - - (NoteS) - ISO Break-Before-Make DelaY,IoPEN 180 300 180 250 - 180 200 - 200 PARAMETER SWITCHING CHARACTERISTICS =soon, ioN (EN) Enable Delay (OFF), RL =SOOn, 'oFF (EN) +2SoC Enable Delay (ON), RL +2S"C - ISO 300 ns - 20 os - 180 - ns 600 os os Settling Time (0.1%) (NoteS) (0.01%) Crosstalk +2S"C +2S"C (Note 6) +2SoC Channel Input Capacitance, CS(OFF) +2SoC Channel Output Capacitance, CO(OFF) +2S"C Digital Input Capacitance, CA +2S"C - - 10 - S - - 0.8 - - 600 -6S 4 - ns -6S - dB - 4 - pF - 10 - pF - S - pF - - 0.8 V - - V O.OS 1 jiA - 2S jiA DIGITAL INPUT SPECIFICATIONS Input Low Threshold (TTL), VAL Full - Input High Threshold (TTL), VAH Full 2.4 Input Leakage Current (High), IAH Full Current (Low), AL Full - 2.4 - O.OS 1 - 2S - ANALOG CHANNEL SPECIFICATIONS Full -10 - +10 -10 - +10 V On Resistance, RoN (Note 2) +2S"C - 700 - - 700 - n Full - - I.S - - I.S Kn Off Input Leakage Current, I;;; (OFF) (Note 3) +2S"C - 0.2 - 0.2 - nA Full - - SO - SO nA 0.2 - nA - SO nA - 0.7 - nA 50 nA - MHz Analog Signal Range, V1N Off Output Leakage Current, 10 (OFF) On Channel Leakage Current, 10 (ON) 3dB Bandwidth (Note 3) (Note 3) (Note 4) +2SoC - 0.2 - - Full - - SO - - +2SoC - 0.7 Full - - SO - - +2SoC - 8 - - 8 10-124 Specifications HI-524 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = +2.4v, VAl. = (logic Level Low) = +O.5V; VEN = +2.4V, Unless Otherwise Specified (Continued) HI-524-21-8 TEST CONDITIONS PARAMETER TEMP I HI-524-5 MIN TYP MAX - 750 I I MIN TYP MAX UNITS - 750 mW 25 rnA 25 rnA POWER SUPPLY CHARACTERISTICS Current, 1+ (Note 7) Full - Current,l- (Note 7) Full - Power Dissipation, Po Full - - 25 - 25 NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. 2. VIN = OV; lOUT = 10011A (See Test Circuit 1). 3. Vo =±10V; VIN = ±10V. (See Test Circuits 2,3,4) 4. MUX output is buffered with HA-5033 amplifier. 5. 6V Step, ±3V to ±3V, See Test Circuit 5. 6. VIN = 10MHz, 3Vp•p on one channel, with any other channel selected. (worst case Is channel 3 selected with input on channel 4). MUX output is buffered with HA·2541 as shown in Applications section. Terminate all channels with 75Q. 7. Supply currents vary less than 0.5mA for switching rates from DC to 2MHz. Performance Curves and Test Circuits TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAl. = O.BV, Unless Otherwise Specified _ _ _ lOUT 1001lA • V2 I IN ). OUT l' VIN V2 RoN .. 100vA TEST CIRCUIT 1. ON RESISTANCE 1,000 I I TA=+12SOC 900 800 9:z rP 700 ,...,. 1,000 ~ """ V I 900 , TA=+250C VIN=OV ~ " TA-+2SO-=- .."..,. .""."'" ..... 600 TA=-550C 500 400 ·10 '\ -II ... -4 -2 0 ."". V .."..,. 2 4 6 ~ ./ 8 800 10 VIN(V) 700 II 10 11 ~ "- 12 ~~ 13 ........ r-.. ~ 14 (V) FIGURE 1. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 2. ON RESISTANCE vs SUPPLY VOLTAGE 10-125 15 HI-524 Performance Curves and Test Circuits TA =+25°C, VSUPPLY =±15V, VAH =2.4V, VAL =O.BV, Unless Otherwise Specified (Continued) .., I ,. . /" / I ID(~ .- , ,. f 'S(ofX L ~ 0.1 V / o 25 ID(OFF) ·1 50 75 100 TEMPERATURE (OC) 125 150 FIGURE 3. LEAKAGE CURRENT VB TEMPERATURE TEST CIRCUIT 2. LEAKAGE CURRENT (NOTE 1) OUT OUT +0.8V EN = .l ±10V ~ = I-=- A ID(ON) EN = 'l'10V J TEST CIRCUIT 3. LEAKAGE CURRENT (NOTE 1) J 'l'10V HOV +2.4V TEST CIRCUIT 4. LEAKAGE CURRENT (NOTE 1) HA-624 ±3V _ - - - - - - - - ..•.....•....... VAH-2.4V _+-0-_.., .......•.•..•..•..•..•..•..•........•.•..•....•....•....•.••..•...... VAL=o.8V HA·2641 -3V OUTPUT ± 0.01 % OF F/s (OR±o.o1%) FIGURE 4. POWER SUPPLY CURRENT va TEMPERATURE TEST CIRCUIT 5. SETTLING TIME, ACCESS TIME, BREAK· BEFORE·MAKE DELAY (NOTE 2) NOTE: 1. Two measurements per channel: ±10V and +lOV. (lINo measurements per device lor ID(OFF) ±10V and =t=10V) 2. This test requires channel inputs 1 and 4 at the same level. 3. Capacitor value may be selected to optimize AC performance. 10-126 HI-524 Performance Curves and Test Circuits TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = O.8V, Unless Otherwise Specified (Continued) I --." 5VIDIV. _\ , IIV ,\.. ~~ .I1 ...... '1 I.J VIDIV. I 50rsIDli·- FIGURE 5. ACCESS TIME TABLE 1. TRUTH TABLE Al Ao EN ON CHANNEL X X L None L L H 1- L H H 2 H L H 3 H H H 4 -Channel 1 Is shown selected In the Functional Diagram Typical Applications Often it is desirable to buffer the HI-524 output, to avoid loading errors due to the channel ·ON" resistance: HA-524 CHI 12 ./0- 750 CH2 750 '714 ,,, 7 CH3 2 18 I ./0-- f ~Ml ___ + r--o BUFFERED - OUTPUT *20pF* 16 5 Note that the on-chip feedback element between pins 16 and 18 includes two switches In series, to simulate a channel resistance. These switches open for VEN Low. This allows two or more HI-524's to operate Into one HA-2541, with their feedback elements connected in parallel. Thus, only the selected multiplexer provides feedback, and the amplifier remains stable. = All HI-524 DIP package pins labeled 'SIG GNO' (pins 3.4, 6,13,15) should be externally connected to signal ground for best crosstalk performance. 750l CH4 plus ±100mA output current for driving coaxial cables. For general wideband applications, the HA-2541 offers the convenience of unity gain stability plus 90ns settling (to ±O.1 %) and ±10V output swing. Also, the HI-524 includes a feedback resistance for use with the HA-2541. This resistance matches and tracks the channel ·ON" resistance, to minimize offset voltage due to the buffer's bias currents. Bypass capaCitors (0.1I1F to 1.0I1F) are recommended from each HI-524 supply pin to power ground (pins 1 and 17 to pin 8 DIP package). Locate the buffer amplifier near the HI-524 so the two capacitors may bypass both devices. /- 750 ";,. - CapaCitor value may be selected to optimize AC performance. The buffer amplifier should offer sufficient bandwidth and slew rate to avoid degradation of the anticipated signals. For video switching, the HA-5033 and HA-2542 offer good performance If an analog input 1V or greater is present when supplies are off, a low resistance Is seen from that input to a supply line. (For example, the resistance is approximately 1600 for an Input of -3V.) Current flow may be blocked by a diode in each supply line, or limited by a resistor In series with each channel. The best solution, of course, is to arrange that no digital or analog Inputs are present when the power supplies are off. 10-127 HI-S24 Metallization Topology DIE DIMENSIONS: 22501lfll x 3720llm x 4851lfll ±251lm METALLIZATION: Type: Cu Al Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.qkA ± 1kA Silox Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 1.58 x 105 A/crr1J. Metallization Mask Layout HI·524 EN AO SUPPLY GND A1 IN1 IN3 SIG SlG GND GND IN4 SlG GND SlG GND .y FBIIN) +Y OUT 10·128 HI-539 Monolithic, 4 Channel, Low Level, Differential Multiplexer December 1993 Features Description • Differential Performance, Typical: - Low ARoN , +125°C ••.•••••••••.••••••••••• 5.50 - Low AIO(ON), +125°C ••.••...••.••.•.••.••• O.6nA - Low A(Charge Injection) •••••••••••••••.•• O.1pC - Low Crosstalk .••.•••••••••••••••••••••• -124dB The Harris HI-539 is a monolithic, four channel, differential multiplexer. Two digital inputs are provided for channel selection, plus an Enable input to disconnect all channels. • Settling Time, ±D.010/0 •••••••••••••••••••••• 900ns • Wide Supply Range..................... ±5Vto±18V • Break-Before-Make Switching • No Latch-Up Performance is guaranteed for each channel over the voltage range ±10V, but is optimized for low level differential signals. Leakage current, for example, which varies slightly with input voltage, has its distribution centered at zero input volts. In most monolithic multiplexers, the net differential offset due to thermal effects becomes significant for low level signals. This problem is minimized in the HI-539 by symmetrical placement of critical circuitry with respect to the few heat producing devices. Supply voltages are ±15V and power consumption is only 2.5mW. Applications • Low Level Data Acquisition • Precision Instrumentation Ordering Information • Test Systems PART NUMBER TEMPERATURE RANGE PACKAGE HI4P0539-5 0"0 to +75"0 Hll·0539-2 -5SOC to +125°C 20 Lead PLCC HI3-0539-5 O"C to +75"0 Hll-0539-4 -25"0 to +85°C 16 Lead Ceramic DIP Hll-0539-5 O"C to +75OC 16 Lead Ceramic DIP Hll-0539-8 -55°C to +125"0 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP Pinouts HII-539 (CDIP) HI3-539 (PDIP) TOP VIEW H14P539 (PLCC) TOP VIEW iii ~ ~ c 0 i§ .v IN 18 NC IIUB IN3B ~ Ii c !50 i CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 10-129 II II § iI ~ File Number 3149 Specifications HI-539 Absolute Maximum Ratings Thermal Information Voltage Between Supply Pins (+V, -V) ••.•••.••••.••.••••• 40V Voltage From Either Supply to GND •.••••••••••••••.••••• 20V Analog Input Voltage, VIN ••.••.••••••••••••••••• -V S VIN S +V DlgitallnpulVoltage ....•.•...•....•.•.••.•.•.•.-V S VA S +V Current (SoLirce or Drain) ............••......•••.....• 20mA Lead Temperature (Soldering lOs) •.•••••••.•.••••.••• +3OOoC Storage Temperature Range ......•.•••...•.• -65°C to +150oC Thermal Resistance OJC °JA Ceramic DIP Package .••••.••.•.•••• 78°Cm 2aocm Plastic DIP Package •.••••.••••••••• loooCm Plastic PLCC Package ••••..••••••... 800CNi Operating Temperature Range HI-539-2, -8 ............................. -55°C to +125°C HI-539-4••••.•••••••••.•.••.••.•••.•••••• -25°C to +85°C HI-539-5 .• '.' ••..••••••.••••.•••••••••••••• OOC to +750 C Junction Temperature Ceramic DiP •.•••••.•••••••••••.•••••.•••.••••• +1750 C Plastic DIP, Plastic PLCC •••••••••.••••.••..•••••• +1500C . CAUTION: Strsssss above /hose listed in "Ab&o/ulB Maximum Ratings' may cause permanent damage to the device. This Is a stress only /Sting and Op8/Stion 01 the device at these or any other conditions above those Indicated In the op8taffonalsecffons ol/hls specification Is not implied. Electrical Specifications Supplies =t15V. VEN =+4.0v. VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +O.8V. See the "Performance Curves·. Selected parameters are defined in "Delinitions·, Unless Otherwise Specnied. PARAMETER TEST CONDITION TEMP I I H1-539-2, -4, -S, TYP MAX (MIN) I I HI-539 -5 TYP MAX (MIN) UNITS SWITCHING CHARACTERISTICS +25OC 250 750 250 750 ns Full - 1,000 - 1,000 ns +25°C 85 (30) 85 (30) Full - (30) - (30) +25°C 250 750 250 750 ns ns ns Full - 1,000 - 1,000 ns +25OC 160 650 160 650 ns Full - 900 - 900 ns +25°C Full 0.9 - JlS !J. Charge Injection (Output) Full 0.1 Charge Injection (Input) Full 10 Access Time, TA Break-Belore-Make Delay, TOPEN Enable Delay On, TON(EN) Enable Delay Off, TOFF(EN) Settling Time, to to.Ol% Charge Injection (Output) 3 Differential Crosstalk Note 3 +25OC 124 Single Ended Crosstalk Note 3 +25OC 100 Cha,nnellnput Capacitance, CS(OFF) Full 5 Channel Output CapaCitance, CO(OFF) Full 7 Channel On Output Cepacitance, COlON) Input to Output Capacitance, Cos Full 17 Full 0.08 Digital Input Capacitance, CA DIGITAL INPUT CHARACTERISTICS Full 3 Input Low Threshold, VAL Full Input High Threshold, VAH Input Leakage Current (High), IAH Full Input Leakage Current (Low), IAL Full Note 4 Full - - - - 0.9 3 0.1 10 124 100 1 dB dB (4.0) V - 1 I1A I1A 0.08 1 pC - - 0.8 pC 3 17 (4.0) - pC - 5 - - - 7 0.8 1 pF pF pF pF pF V ANALOG CHANNEL CHARACTERISTICS Full - (-10)/+10 - (-10)/+10 V VIN=OV +25°C 650 850 650 850 VIN =tl0V +25°C 700 900 700 900 VIN=OV VIN =tl0V Full 950 1.3k 800 lk Full 1.lk Uk 900 Uk n n n n Analog Signal Range, VIN. On Resistance, RaN 10-130 Specifications HI-S39 Electrical Specifications Supplies = ±15V. VEN = +4.ov. VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +O.8V. See the "Performance Curves". Selected parameters are defined in "Definitions", Unless Otherwise Specified. (Continued) HI-539 -5 H1-539-2, -4, -8, PARAMETER (Side A-Side B), ARClN Off Input Leakage Current, lS(oFF) (Side A-Side B), AIS(OFF) Off Output Leakage Current, lo(oFF) (Side A-Side B), AID(oFF) TEST CONDITION TEMP TYP MAX (MIN) TYP MAX (MIN) UNITS VIN=OV +25OC 4.0 24 4.0 24 V1N = ±10V +25OC 4.5 27 4.5 27 VIN=OV FuN 4.75 28 4.0 24 V1N =±10V Condition OV (Note 1) Full 5.5 33 4.5 27 a a a a +25°C 30 - Condition ±10V (Note 1) +25°C 100 - 30 100 Condition OV (Note 1) Full 2 10 Condition ±10V (Note 1) Full 5 Condition OV +25°C 3 Condition ±10V +25OC 10 - 10 - pA ConditionOV Full 02 2 0.02 02 nA Condition ±10V Full 0.5 5 0.05 0.5 nA Condition OV (Note 1) +25°C 100 - pA +25°C - 30 Condition ±10V (Note 1) 30 100 Condition OV (Note 1) Full 2 10 0.2 1 nA Condition ±10V (Note 1) Full 5 25 0.5 2.5 nA Condition OV +25°C 3 - 3 pA Condition ±1 OV +25°C 10 - - 10 - pA Full 0.2 2 0.02 0.2 nA 5 0.05 0.5 nA pA Condition OV Condition ±10V On Channel Leakage Current, ID(ON) (Side A-Side B), Alo(ON) Differential Offset Voltage, AVos Full 0.5 Condition OV (Note 1) +25°C 50 Condition ±10V (Note 1) +25OC Condition OV (Note 1) Condition ±10V (Note 1) - pA - pA 0.2 1 nA 25 0.5 2.5 nA - 3 - pA pA 150 - 150 - Full 5 25 0.5 2.5 nA Full 6 40 0.8 4.0 nA ConditionOV +25°C 10 - 10 Condition ±10V +25OC 30 - pA Condition OV Full 0.5 5 30 0.05 0.5 nA Condition ±10V Full 0.6 6 0.08 0.8 +25OC 0.02 0.02 Full 0.70 - +25OC 2.3 - 2.3 Note 2 50 0.08 - pA pA nA IIV IIV POWER REQUIREMENTS Power Dissipation, Po Full Current, 1+ +25°C Full Current, 1- +25OC Full Supply Voltage Range, ±V Full - mW 45 mW - mA 2.0 mA - mA 0.001 - 2.0 1.0 - 1.0 mA ±15 (±5)1±18 ±15 (±5)1±18 V 0.150 45 - 0.150 0.001 NOTES: 1. See Figures 2B, 2C, 2D. The condition ±10V means: lS(oFF) and IO(OFF): (Vs = +10V, Vo = -10V), then (VS = -10V, Vo = +10V) lo(ON): (+10V, then -10V) 2. AVos (Exclusive of thermocouple effects) = RoN AIO(ON) + ID(ON) AAoN. See Applications section for discussion of additional Vos error. 3. V1N = 1kHz, 15VPOP on all but the selected channel. See Figure 7. 4. Calculated from typical Single-Ended Crosstalk performance. 10-131 HI-S39 Performance Curves Unless Otherwise Specified TA = +25"C, +V = +15V, -v _ _ _ 100"" I- &00 • I VIN-OV s I Vz =-15V, VAH =+4V and VAl. =+( \ I '. ~_j,L ••••••••• ~: I I I I I RON +J RoN -I I I I I .1· .1· 1MT010M :1: .,' .,' I I ~ '7 ~g:~~UPPLY +v 1-v I I I I ,.t., POWER SUPPLY V 'l~' COMMON FIGURE8B. The amplifier in Rgure SA Is unussble because Its bias currents cannot return to the power supply. Figure 8B shows two alternative paths for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source. 10-13S HI-539 Die Characteristics DIE DIMENSIONS: 92 mils x 100 mils METALLIZATION: Type: AI Cu Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.qkA ± 1kA Silox Thickness: 12kA ± 2.0kA WORST CASE CURRENT DENSITY: 2.54 x 105A/cm2 at 20mA TRANSISTOR COUNT: 236 PROCESS: CMOS-DI SUBSTRATE POTENTIAL": -VSUPPLY " The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential Metallization Mask Layout HI-539 IN1A IN1B IN2A 1N2B IN3A IN4A OUlA OUTB 10-139 IN4B IN3B HI-546, HI-547 HI-548, HI-549 Single 16 and 8, Differential 8 and 4 Channel CMOS Analog MUXs with Active Overvoltage Protection December 1993 Features Description • Analog Overvoltage Protection ••••••• 70V p.p The HI-546. HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed RON matching. Analog Input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity Is maintained even under fault conditions that would destroy other multiplexers. • No Channel Interaction During Overvoltage • Guaranteed RON Matching • 44V Maximum Power Supply • Break-Before-Make Switching • Analog Signal Range •....•......•.....•±15V • Access Time (Typlcel) •••••••••••••• 500ns • Standby Power (Typical) ••••••••••••7.5mW Applications • Data AcquIsition • Industrial Controls • Telemetry Analog inputs can withstand constant 70Vp.p levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1Kn of resistance under this condition. These features make the HI546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from extemal equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16 channel, the HI547 Is an 8 channel differential, the HI-548 is a single 8 channel and the HI-549 is a 4 channel differential device. If Input overvoltage protection is not needed the HI-5061507/508l509 multiplexers are recommended. For further information see Application Notes 520 and 521. The HI-546 and HI-547 devices are available in a 28 lead Plastic or Ceramic DIP and a 28 pad Ceramic LCC package. The HI-54eJ549 devices are available ina 16 lead Plastic or Ceramic DIP and a 20 pad Ceramic LCC package. The HI-546,HI-547, HI-548 and HI-549 are offered in industriaVcommercial and military grades. Additional Hi-Rei screening including 160 hour Bum-In Is specified by the "-8" suffix. For Mil-Std-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-5491 883 datasheets. Ordering Information PART NUMBER TEMPERATURE RANGE PART NUMBER PACKAGE TEMPERATURE RANGE PACKAGE: H11-0546-4 -250C to +8500 28 Lead Ceramic DIP HI1.Q547-5 ooC 10 +7500 28 Lead Ceramic DIP HI 1-0546-5 00CIO+75oo 28 Lead Ceramic DIP HI 1-0547-9 -4OOC to +8500 28 Lead Ceramic DIP H11-0546-2 -5500 10 +125°C 28 Lead Ceramic DIP HI1-0547/883 -5500 10 +12500 HI1-0546/883 -5500 10 +125°C 28 Lead Ceramic DIP HI3-0547-5 ooC 10 +7500 28 Lead Plastic DIP ooCIO +7500 28 Lead Plastic DIP 1:\13-0547-9 -4OOC 10 +8500 28 Lead Plastic DIP HI3-0546-9 -4OOC 10 +8500 28 Lead Plastic DIP HI4-0547/883 -5500 to +125°C 28 Lead Ceramic LCC HI4-0546I883 -5500 10 +125°C 28 Lead Ceramic LCC HI4P0547-5 ooC 10 +7500 H14P0546-5 ooCIO +75OC 28 Lead PLCC HI9P0547-5 ooCto+75oo 28 Lead Plastic SOIC H19P0546-5 OOC10 +75°C 28 Lead Plastic SOIC HI9P0547-9 -40"C 10 +8500 28 Lead Plastic SOIC HI3-0546-5 HI9P0546-9 -4OOC to +8500 28 Lead Plastic SOIC HI 1-0547-2 -55°C 10 +125°C 28 Lead Ceramic DIP HI 1-0547-4 -2500 to +8500 28 Lead Ceramic DIP CAUTION: These devices are sensitive to electrostatic discharge. Users should foRow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 10-140 28 Lead Ceramic DIP 28 Lead PLCC File Number 3150 HI-546, HI-547, HI-548, HI-549 Ordering Information (Continued) PART NUMBER TEMPERATURE RANGE TEMPERATURE RANGE PART NUMBER PACKAGE PACKAGE Hll-0548-2 -55°C to +125°C 16 Lead Ceramic DIP Hll-0549-2 ·55°C to + 125°C Hll-0S48-4 -2SoC to +8SoC 16 Lead Ceramic DIP HI 1-0549-4 -25OC to +8SOC 16 Lead Ceramic DIP Hll-0548-5 OOCto +75°C 16 Lead Ceramic DIP Hll-0549-5 OOCto +75OC 16 Lead Ceramic DIP -55°C to +125°C 16 Lead Ceramic DIP Hll-05491883 -55°C to +125°C 16 Lead Ceramic DIP Hll-0548/883 16 Lead Ceramic DIP HI3-0548-S OOC to+75°C 16 Lead Plastic DIP HI3-0549-5 OOCto +75°C HI3-0548-9 -40OC to +85°C 16 Lead Plastic DIP HI3-0549-9 -40OC to +8SOC 16 Lead Plastic DIP 16 Lead Plastic DIP HI4-0548/883 -55°C to +125°C 20 Lead Ceramic LCC .HI4-05491883 -55OC to +125°C 20 Lead Ceramic LCC HI4P0548-5 OOCto +7SoC 20 Lead Plastic LCC HI4P0549-5 OOC to +75°C 20 Lead Plastic LCC HI9P0548-5 OOCto +7SoC 16 Lead Plastic SOIC HI9P0549-S OOCto +75OC 20 Lead Plastic SOIC HI9P0548-9 -40oC to +85°C 16 Pin SOIC (W) HI9P0549-9 -40OC to +85°C 16 Pin SOIC (W) Pinouts Hll·0546 (CDIP), HI3-0546 (PDIP), HI9P0546 (SOIC) TOP VIEW HI1·0547 (CDIP), HI3-0547 (PDIP), HI9P0547 (SOIC) TOP VIEW +VSUPPLY 1 +VSUPPLY 1 OUTB NC IN7B IN6B IN5B 17 ADDRESS Au 17 ADDRESS Au 16 ADDRESS AI -,1.-____-r1-5 ADDRESS A:t HI4P0546 (PLCC) TOP VIEW ~ :!! ! ~ Go Go (,) z (,) z J+ HI4P0547 (PLCC) TOP VIEW I:::) 0 ~ ID CD CD ! ! z :::) 0 ~... ~ C I- :::) 0 _, t!J l!J llJ L~J lt8J _, t!J l!J llJ L~J ltBJ l~J tl6J r- ......~ ~ l~J C CD ! tt6J r- 125 IN7 L_ IN 7B IN14 INS ~~ ~U IN13 IN5 ~m ~~ IN12 IN4 ~~ ~~ INll IN3 IN10 IN2 IN15 51 _J (,) ID I- IN II r-"'1 .. - .. ,.-"" ,..-.. "-"1 .. - .. ,.-.. ~J l~5 INIB INI INIA r-, ,.-.. r-"'I ,..- .... - .. r-.. r-.. '12' '13' '14' '15' '16' '17' '18' '12' '13' '14' '15' '16' '17' '18' c z ~ C!I Z W 10-141 IN 7A HI-546, HI-547, HI-548, HI-549 Pinouts (Continued) H11-0548 (CDIP) HI3-0548 (PDlP) HI9P0549 (SOIC) TOP VIEW HI1-o548 (CDIP) HI3-0548 (PDIP) HI9P0548 (SOIC) TOP VIEW Ao Ao ENABLE ENABLE ·YSUPPLY ·YSUPPLY INIA IN2 IN2A IN3 IN3A IN4 IN4A OUT OUT A HI4·0549 (LCC) H14P0549 (PLCC) TOP VIEW H14P0548 (PLCC) TOP VIEW -., L!J LlJ L~j L~J LU'J -., ~J -., .YSUPPLY ~J .YSUPPLY INI .!!J INIA .!!J .!J -., .!J -., .!J NC .!J -., .!J -., .!J NC IN2 IN3 -., -., IN2A IN3A L!J LlJ L~j LtoJ LU'J -., r-., r-., r-, r-" r-., 19111011111 1121 1131 ...m ~ Functional Diagrams HI·547 HI·546 OUT lk INI IN2 • • • IN 16 lk •• "-- INIA -- INBA DECODERI DRIYER OUT A 1k IN1B lk INBB •• lk •• lk OUT B OVERYOLTAGE CLAMP & SIGNAL ISOLATION OVERVOLTAGE CLAMP & SIGNAL ISOLATION • DIGITAL INPUT PROTECTION * DIGITAL INPUT PROTECTION YREF Ao At -'2 As EN YREF 10·142 Ao A1 -'2 EN HI-546, HI-547, HI-548, HI-549 Functional Diagrams (Continued) HI·548 HI-549 t t ~--- 1k IN2 INa • • • _--------------_OUT OUT 1k IN1 tt ___ -- -- 1k IN1A IN4A DECODER! DRIVER IN1B 1k t ~- ...... IN4B -...- •• A 1k OUT B •• 1k OVERVOLTAGE CLAMP! SIGNAL ISOLATION OVERVOLTAGE CLAMP! SIGNAL ISOLATION • DIGITAL INPUT PROTECTION • DIGITAL INPUT PROTECTION Schematic Diagrams ADDRESS DECODER TO N-cHANNEL DEVICE OF THE SWITCH ENABLE DELETE A, OR ~ INPUT FOR HI-549 DELETE A:! OR A:! INPUT F~R H1-549 1()"143 HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) MULTIPLEX SWITCH DE~~~ ,>'>-------------------~--------------------~~---, OVERVOLTAGE PROTECTION ........ --------_ .. _------------- ···• ·••• ···•• • -----.;.-------------------,• N Y+ R11 1K IN •• • : ·· · Y- ~------------ ... • -----------------..-- ------.... _---_....._----,• DE~~~ >>-----------------------~~----------------~ ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT Y+· R10 R9 •• • • ••• · •• :... _--_..........GND. _....... _-_ .... LEYEL SHIFTER OYERVOLTAGE PROTECTION ... : .,,, . v+ ,~ .: , : R1 : 200 ~ : LEYEL SHIFTED ADDRESS TO DECODE --------- ..... .,,, ~ n , ~ V- : ~-i~~~im. .1.._------------.---------------------------------------__________________________________ _ 10-144 Specifications HI-546, HI-547, HI-548, HI-549 Absolute Maximum Ratings Thermal Information VSUPPLY(+) to vSUPPLYH' .............................. +44V VSUPPLY(+) to GND .................................. +22V VSUPPLY(.) to GND .................................... -25V Digital Input Overvoltage Thermal Resistance OJC OJA Ceramic Packages 16 Lead DiP ......••••..•....••.•• 24"C/w 80oC/W 55·C/W 200c/w 28 Lead DiP •••••....••.•.••.••..• 20 Lead LCC ..•.........•...•••.• 75°C/W 20"C1W 28 Lead LCC •••......•..•••.•.... 60·c/w 11"C/w Plastic DIP Packages 28 Lead ....•..••........•••••.•• 60oC/W 16 Lead .••....••....•....•..•.•. l00·C/w Plastic PLCC Packages 70·c/w 28 Lead •.•••••...••••.•.•••..... eooC/W 20 Lead ....•....•.......•....... SOIC 28 Lead .....•.•.............•.•. 700c/w 16 Lead ..................•.•...• l00oC/W Operating Temperature Ranges HI-546/547/548I549-2 •.•.••......... _..••• -55°C to +125°C HI-546/547/548I549-4 ......•..•.••••.••.••• -25°C to +85·C HI-548I547/548I549-5, -7 ........•••••.....•• O"C to +75·C HI-546/547/548I549-9 ...........•.•••...... -40"C to +85·C Junction Temperature Ceramic Package ............................... +175°C Plastic Package ....••.•..........•••....•..••.•• + 150·C +VEN' +VA ············•··············•···· +VSUPPLy+4V -VEN' -VA' ...................•..•.•..•..•.. -VSUPPLy-4V or 20mA, whichever occurs first Analog Signal Overvoltage (Note 6) +Vs ............................•.....•. +VSUPPLY +20V -Vs· .................................••.. -VSUPPLY -20V Continuous Current, S or D .......•........••.•••..•.• 20mA Peak Current, S or D ....•........................... 40mA (Pulsed at 1ms, 10% duty cycle max) Storage Temperature Range .....•....•...... -65°C to + 150°C Lead Temperature (Soldering lOs) •......•............ +300oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only tating and Op6talion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications Supplies = +15V, -15V; V REF Pin = = Open; VAH (Logic Level High) +4V; VAL (Logic Level Low) = +O.8V; Unless Otherwise Specified. For Test Conditions, Consult Performance Curves. PARAMETER TEST CONDITION HI-54X-4, -5, -9 H1-54X-2 TEMP MIN TYP MAX MIN TYP MAX UNITS 0.5 - - 0.5 - lIS - 1.0 25 80 SWITCHING CHARACTERISTICS Access Time, tA +25°C Full - - 1.0 Break-Before Make Delay, !oPEN +25°C 25 80 - Enable Delay (ON), !oN (EN) +25°C 300 500 - 1000 300 500 - 1000 - Full Enable Delay (OFF), !oFF(EN) +25°C Settling Time (0.1 %) (0.01%) +25°C - Full 'Off Isolation" Channel Input Capacitance, CS(OFF) Note 5 300 - 1000 ns ..J 300 - ns - - 5:::l 1000 ns - 1.2 - lIS 3.5 - - +25°C - 3.5 +25°C 50 68 - 50 68 +25°C - 5 - - 5 52 - - 1.2 lIS - - ns ns lIS dB pF Channel Output Capacitance CO(OFF) HI-546 +25°C HI-547 +25°C HI-548 +25°C HI-549 +25°C Input to Output Capacitance, COS(OFF) +25°C 10-145 30 - 25 12 0.1 - - 52 30 25 - 12 - 0.1 - pF pF pF pF pF 8!w >< W D. :e Specifications HI546, HI·547, HI·548, HI·549 Electrical Specifications • Supplies = +15V, -15V; VREF Pin = Open; VAH (logic Level High) = +4V; VAL (Logic Level Low) = -Hl.BV; Unless Otherwise Specified. For Test Conditions, Consult Performance Curves. (Continued) PARAMETER TEST CONDITION H1-54X-4, -5, -9 H1-54X-2 TEMP MIN TVP MIN TYP MAX UNITS O.B - O.B V - - 4.0 - - V - MAX DIGITAL INPUT CHARACTERISTICS Full - Input High Threshold, VAH Note 7 Full 4.0 - MOS Drive (HI-546f547 Only), VAL NoteB +25°C - - MOS Drive (HI-546f547 Only), VAH NoteB +25°C S.O Input Leakage Current (High or Low), IA Note 4 Full Full Input Low Threshold, TTL Drive, VAL O.B - O.B V - - V - - - S.O 1.0 - - 1.0 IIA -15 - +15 -15 - +15 V - 1.5 1.B kn - 1.8 2.0 kO - 7.0 % 0.03 - nA - 50 nA 0.1 - nA - 300 nA - 200 nA - 200 nA 100 nA 4.0 - nA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, Vs On Resistance, RoN, Note 1 aRoN, (Any Two Channels) Off Input Leakage Current, IS(OFF) 011 Output Leakage Current, ID(OFF) Note 2 Note 2 O +25 C - 1.2 1.5 Full - 1.5 1.B +25°C - - 7.0 +25°C - 0.03 - Full - - 50 +25°C - 0.1 - HI-546 Full HI-547 Full HI-548 Full HI-549 Full - 4.0 With Input Overvoltage Applied, IO(OFF) Note 3 +25°C Full - On Channel Leakage Current, IO(ON) Note 2 +25°C HI-546 Full HI-547 Full HI-546 Full HI-549 200 - - - 200 100 - 2.0 - - - IIA - 0.1 - - 0.1 - nA - - 300 - - 300 nA - - - - 200 nA 200 nA 100 nA 50 nA Full - - Full Differential Off Output Leakage Current (HI-547, HI-549 Only), IOIFF - 300 - 200 200 50 - - 100 POWER REQUIREMENTS Full - 7.5 - - 7.5 ,mW NoteS Full - 0.5 2.0 - - Current, 1+ 0.5 2.0 rnA Current,l- NoteS Full 0.02 1.0 - 0.02 1.0 rnA Power Dissipation, Po NOTES: 1. VOUT = ±10V, lOUT = '" 1001lA. 2. 10nA is the practical lower limit for high speed measurement In the production test environments. 3. Analog Overvoltage = ±33V. 4. Digital input leakage Is primarily due to the clamp diodas (see Schematic). Typlcalleakage is less than 1nA at +25°C. 5. VEN = O.BV, RL = 11<, CL = 15pF, Vs = 7VRMS, f= 100kHz. S. VEN , VA =OVor4.0V. 7. To drive from DTLlTTLCircuits, 1kn pull-up resistors to +5.0VsuPPLY are recommended. B. VREF = +10V. 10-146 HI-546, HI-547, HI-548, HI-549 Performance Curves TA =+25°C, VSUPPLY =±15V, VAH =+4V, vAL =O.8V, VREF =Open, Unless Otherwise Specified _ _ _ -100j1A • I Vz IN OUT )~ VIN Ro _L... FIGURE 1A. ON RESISTANCE TEST CIRCUIT ....- 1.4 1.3 TA-+12SoC I g1.2 I w> 1.5 U" I z~ w 1.1 U z ;! 1.0 SI 0 -w ;:3 ..,. TA=+2SoC 51 z $. -8 -4 -2 0 +2 " 01- 1.1 :::Ja: ~a: !§ ~ 1.0 0.7 -8 """"I\.. 1.3 00 1.2 ~ 0.8 0.6_10 1.4 z~ TA-+SSoC w 0.9 a: z ~ Ie ...", +4 +6 +8 " ....... ~ 0.9 0.8 +10 ±5 ANALOG INPUT (VI ±6 ±7 ±6 ±9 ±10 ±11 ±12 ±13 ±14 ±15 SUPPLY VOLTAGE M FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMAUZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 10-147 HI-546, HI-547, HI-548, HI-549 Performance Curves T" =+25OC, VSUPPLY =±15V, VAM =+4\1, VAl. =o.av, VREF =Open, Unless Otherwise Specified (Continued) 100nA 10nA iw rr: rr: 8w OFF OUTPUT CURRENT ID(OFF) .// ON LEAKAGE - CURRENT '~ io(ON), 1nA :: I 1 V "',,, .~ ...... ~ L-.,. /' V 100pA 10pA 25 7& t~ = J = 100 J == = J "'1OV 125 TEMPERATURE ("C) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. lo(oFF) TEST CIRcurr OUT OUT ,, , A Io(OFF) =. ±1OV OFF INPUT LEAKAGE CURRENT IS(OFF) 50 ~~- , +0.8V EN ±1'OV '"--0 EN = 1. - A - ±10V "'1OY FIGURE 2C. Is(oFF) TEST CIRcurr +2.4V + FIGURE 20. ID(oN) TEST CIRCUIT FIGURE 2. LEAKAGE CURRENT NOTE: 1. Two measurements per channel: +10Vl-10V and ·10Vl+10V. (1\vo measurements per device for ID(OFF): +1 OV/·1OV and .10Vl+10V) 10-148 HI-546, HI-547, HI-548, HI-549 Performance Curves TA = +25°C, VSUPPlY = ±15V, VAH = +4V, V,"- = O.BV, V REF = Open, Unless Otherwise Specified (Continued) 18.---r---r---r---r---r---r---.-~ C g ~ B !; ~ ~~ i- 15 1---+---+---+- 12 1--+--+--+-+--+~-+-~'---I41 ~ 5 ~ 9 3 6 2 3 ~ W ~ A ID(OFF) ~ ... OL-_~_~_~_-L_-L_-L_~_~O ±IS 6~ ±36 ±18 ±21 ±24 ±27 ±30 ±33 ANALOG INPUT OVERVOLTAGE (V) FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF LEAKAGE CURRENT VS ANALOG INPUT OVERVOLTAGE FIGURE 3B. ANALOG INPUT OVERVOLTAGE TEST CIRCUIT FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS ±14 -5S0~ l/: ~~ ~~ ±2 o ~ +2SoC ,/ ..........+I2SoC ~V V 1/ o ±2 ±4 ±6 tS tl0 t12 t14 VOLTAGE ACROSS SWITCH (V) FIGURE 4A. ON CHANNEL CURRENT VB VOLTAGE FIGURE 4B. ON CHANNEL CURRENT TEST CIRCUIT FIGURE 4. ON CHANNEL CURRENT 8 I C 6 g +V IN 1 HI-S46t Az IN2 THRU A, INIS ~ ~ W II: II: i3 VSUPPLY =± 1SV 4 ~ VSUPPLY8±10V,,,,- Do. Do. :::) IV _ 800 _ Aa ! ~ 600 !;l 500 \ HI-546t \ IN16 +4V I'~ 400 300 +V IN1 IN 2 ~~~ 1-_--, ;; 700 ::I 1= VREF 3 4 5 6 7 8 8 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 16 tSlmllar connection for HI-5471H1-548/HI-549 FIGURE 6A. ACCESS TIME VI LOGIC LEVEL (HIGH) FIGURE 6B. ACCESS TIME TEST CIRCUIT FIGURE 6. ACCESS TIME Switching Waveforms t: - r- I I V"INPUT 2V/DtV OV r +10V \ OUTPUT tA II OUTPUT A 5VIDIV I I , ): ..... 90% _ _ _ _ -10V \ i-- J ..... ZOOnaIDIV FIGURE 7A. ACCESS TIME MEASUREMENT FIGURE 7B. ACCESS TIME WAVEFORMS FIGURE 7,. ACCESS TIME t tReler to Figure 68 for Test Circuit 10-150 HI-546, HI-547, HI-548, HI-549 Switching Waveforms -'3 A:! (ContInued) HI-546t -'3 +SV IN1 HI-546t A:! INI At IN2THRU IN16 +10V IN2THRU +4.0V At IN1S Ao IN16 EN OUT - VOUT EN 1k SO -VA 50pf n - Ao OUT 1k GND n - SOpf n - - tSimila, connection fo, HI·5471H1-5481H1-549 fSimila, connection fo, HI-547/HI·5481H1-549 FIGURE BA. BREAK-BEfORE-MAKE DELAY TEST CIRCUIT fiGURE 9A. ENABLE DELAY TEST CIRCUIT VAH,,4.0V So:f·······················t. SO% . ___ 1-1 ' ~~~ ADDRESS DRIVE (VAl OV i OUTPUT --1: fiGURE BB. BREAK-BEFORE-MAKE DELAY MEASUREMENT ;--- i tON(EN) =-- --i OV tOFF(EN) i l-- FIGURE 9B. ENABLE DELAY MEASUREMENTS ~ I I VA INPUT 2VIDIV ~\ I BAON 1AON I( 1\ J '1 'Il OUTPUT A \ O.5VIDIV V ) 1AON I I-- ~I IN1 THRU IN B Off r OUTPUT A \ 2VIDIV I I ~ 100naIDlV 100nsIDIV FIGURE BC. BREAK-BEFORE-MAKE DELAY WAVEFORMS FIGURE 9C. ENABLE DELAY WAVEfORMS FIGURE B. BREAK-BEfORE-MAKE DELAY (tOPEN) FIGURE 9. ENABLE DELAY (tON(EN)' tOFF(EN~ 10-151 HI-546, H1547, HI-548, HI-549 Truth Tables HI-546 HI-548 A3 A" Al Ao X X X X L None X X L L L L H 1 L L L L L H H 2 L L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 Al Ao EN "ON" CHANNEL PAIR H H L L H 13 X X L None H H L H H 14 L L H 1 H H H L H 15 L H H 2 H H H H H 16 H L H 3 H H H 4 EN "ON" CHANNEL A" Al Ao EN ·ON" CHANNEL PAIR X L None L H 1 L H H 2 L H L H 3 L H H H 4 H L L H 5 H L. H H 6 H H L H 7 H H H H 8 Al Ao X X L L L "ON" CHANNEL X L None L H 1 L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 HI-549 HI-547 A2 EN 10-152 HI-546, HI-547 Die Characteristics DIE DIMENSIONS: 83.9 mils x 159 mils x 19 mils METALLIZATION: . Type:CuAI Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA ± 1kA Silox Thickness: 12kA ± 2kA WORST CASE CURRENT DENSITY: 1.4 x 1Q5A1cm 2 TRANSISTOR COUNT: HI-546: 485 HI-547: 485 PROCESS: CMOS-OI SUBSTRATE POTENTIAL t: -VSUPPLY t The substrate appears resistive to the conductor at -VSUPPLY potential. -vSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a Metallization Mask Layout Hf-547 U) a:: w >< W ..J D.. !j :::) :& IN3 IN3B (21) (9) IN4 (22) IN4B (8) IN5B (7) IN6B (6) IN7 (25) 10-153 HI-548, HI-549 Die Characteristics DIE DIMENSIONS: 83 mils x 108 mils x 19 mils METALLIZATION: Type:CuAI Thickness: 16kA ± 2kA GLASSIVATION: Type: Nitride Over Silox' Nitride Thickness: 3.5kA ± 1kA SiioxThickness: 12kA±2kA WORST CASE CURRENT DENSITY: 1.4 x 1Q5A1cm 2 TRANSISTOR COUNT: HI-548: 253 HI-549: 253 PROeESS: CMeS~t)1 SUBSTRATE POTENTIALt: -VSUPPLY t The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or ~ may be mounted on a conductor at -vSUPPLY potential. Metallization Mask Layout HI-548 HI-549 OUT A OUT INS (12) +V (13) GND (14) At Ao (16) (1) EN GND (15) (2) 10-154 Ao EN (16) (1) (2) A, DATA ACQUISITIO_ 11 COMMUNICATION INTERFACE PAGE COMMUNICATION INTERFACE PRODUCTS DATA SHEETS HIN230 thru HIN241 +5V Powered RS-232 TransmltteralRecelvers . • . . . . . . . . . . . . . . . . • • • • • . . . . . . . . . . . . . . . 11·3 ICL.232 +5V Powered Dual RS·232 Transmitter/Receiver. . . • . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . 11·8 NOTE: Bold lYpe Designates a New Product from Harris. 11-1 m~~ HIN230 thru HIN241 +5V Powered RS-232 Transmitters/Receivers ADVANCE INFORMATION December 1993 Features Description • Meets All RS-232C and V.28 Specifications The HIN230-HIN241 family of RS-232 transmitters/receivers Interface circuits meet all ElA RS-232C and V.28 specifications, and are particularly suited for those applications where ±12V is not available. They require a single +5V power supply (except HIN231 and HIN239) and features onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. The family of devices offer a wide variety of RS232 transmitter/receiver combinations to accommodate various applications (see Selection Table). • Requires Only Single +5V Power Supply - (+5V and +12V - HIN231 and HIN23I1) • Onboard Voltage Doublernnverter • Low Power Consumption • Low Power Shutdown Function • Trl-State TTUCMOS Receiver Outputs The drivers feature true TTUCMOS input compatibility. slewrate-limited output. and 300n power-off source impedance. The receivers can handle up to +3OV. and have a 3kn to 7kn input impedance. The receivers also feature hysteresis to greatly improve noise rejection. • MuHlple Drivers - ±10V Output Swing for +5V Input - 300n Power-Off Source Impedance - Output Current Umltlng - TTUCMOS Compatible - 30VlJ,18 Maximum Slew Rate Applications • MuHlple Receivers - ±30V Input Voltage Range - 3kn to 7kn Input Impedance - O.sV Hysteresis to Improve Noise ReJection • Any System Requiring R8-232 Communications Port - Computer - Portable, Mainframe, Laptops - Peripheral - Printers and Terminals • Portable Instrumentation • Modems Selection Table PART NUMBER POWER SUPPLY VOLTAGE NUMBER OF RS-232 DRIVERS NUMBER OF RS-232 RECENERS EXTERNAL COMPONENTS LOW POWER SHUTDOWN nTL TRI-5TATE NO. OF LEADS HIN230 +5V 5 0 4 Capacitors YESINO 20 HIN231 +5V and +7.5V to 13.2V 2 2 2 Capacitors NOINO 16 HIN232 +5V 2 2 4 Capacitors NOINO 16 HIN234 +5V 4 0 4 Capacitors NOINO 16 HIN236 +5V 4 3 4 Capacitors YESlYES 24 HIN237 +5V 5 3 4 Capacitors NOINO 24 HIN236 5V 4 4 4 Capacitors NOINO 24 HIN239 +5V and +7.5Vto 13.2V 3 5 2 Capacitors NOIYES 24 HIN240 +5V 5 5 4 Capacitors YESlYES 44 HIN241 +5V 4 5 4 Capacitors YESlYES 28 CAUTION: These dwices are sensiIMI to electrostatic discharge. Use,. sho\lklloHow proper I.e. Handling Procedures. Copyright @Harrls Corporation 1993 11-3 File Number 3138 HIN230 thru HIN241 Ordering Information PART NUMBER TEMPERATURE RANGE PART NUMBER PACKAGE TEMPERATURE' RANGE PACKAGE HIN230CB O"C to +7000 20 Lead SOIC HIN237CP .O"C to +7O"C 24 Lead Plastic DIP HIN230lB -4O"C to +85°C 20 Lead,SOIC HIN2370B 0°0 to +7000 24 Lead SOlO Ole HIN237IP -4O"C to +8500 24 Lead Plastic DIP -4O"C to +8500 24 Lead SOlO HIN230BY HIN2S1CB O"C to +70°0 16 Lead SOlO (W) HIN2371B HIN2311B -4O"C to +85OC 16 Lead SOIC (W) HIN237BY HIN231BY Die Ole HIN23BCP 0"0 to +7O"C 24 Lead Plastic DIP HIN232CP OoC to +7000' 16 Lead Plastic DIP HIN23BCB O"C to +7000 24 Lead SOlO HIN232CB O"C to +70"C 16 Lead SOIC (W) HIN2381P -4000 to +8500 24 Lead Plastic DIP HIN2321P -4O"C to +8500 16 Lead Plastic DIP HIN2381B -40°0 to +8500 24 Lead SOIC HIN2321J -40°0 to +85 C 16 Lead Oeramlc DIP HIN238BY HIN232IB -40°0 10 +85°C 16 Lead SOlO (W) HIN239CP O"C to +7000 24 Lead Plastic DIP HIN232MJ -55°0 to +125°0 16 Lead Ceramic DIP HIN2390B 0"0 to +7000 24 Lead SOlO Die HIN2391P -40"0 to +8500 24 Lead Plastic DIP -4O"C to +8500 24 Lead SOlO O HIN232BY HIN234CB 0"0 to +70"C 16 Lead SOIC(W) HIN239IB HIN2341B -4O"C to +8500 16 Lead SOlO (W) HIN239BY HIN234BY Die HIN240CN Ole Die 0"0 to +700 C 44 Lead MQFP HIN236CP O"C to +7O"C 24 Lead Plastic DIP HIN240lN -40"0 to +8500 44LeadMQFP HIN236CB 0"0 to +70"0 24 Lead SOlO HIN241CB 0"0 to +70"0 28 Lead SOlO HIN2361P -4000 to +85°0 24 Lead Plastic DIP HIN2411B -4O"C to +85°0 28 Lead SOlO HIN236IB -40"C to +8500 24 Lead SOlO HIN2410A 0°0 to +70°0 28 Lead SSOP Die HIN2411A -4O"C to +8500 28 Lead SSOP HIN236BY 11-4 HIN230 thru HIN241 Pin Description PIN FUNCTION Vee Power Supply Input SV ±10% v+ Internally generated positive supply (+10V nominal), HIN231 and HIN239 requires +7.SV to +13.2V. VGNO Internally generated negative supply (-10V nominal). Ground lead. Connect to OV. C+ External capacitor (+ terminal) Is connected to this lead. e- External capacitor (- terminal) is connected to this lead. C2+ External capacitor (+ terminal) Is connected to this lead. C2- External capaCitor (- terminal) is connected to this lead. TIN Transmitter Inputs. These leads accept TTUCMOS levels. An Internal400Kn pull-up resistor to Vee is connected to each lead. TOUT RIN RoUT Transmitter Outputs. These are RS-232 levels (nominally ±1 OV). Receiver Inputs. These Inputs accept RS-232 input levels. An InternalSKn pull-down resistor to GNO Is connected to each Input Receiver Outputs. These are TTLJCMOS levels. =SV, the outputs are placed EN Enable input. This is an active low input which enables the receiver outputs. With EN in a high Impedanca state. SO Shutdown Input With SO SV, the charge pump Is disabled, the receiver outputs are in a high impedance state and the transmitters are shut off. NC No Connect. No connections are made to these leads. = Z o -III ~U g~ Za:: ::)111 ::E~ 8- 11-5 Specifications HIN230 thru HIN241 Absolute Maximum Ratings Thermal Information vee to Ground ....•••.•..•••••••••••.(GND -o.3V) --f~ TO (2) TRANSwr DATA INPUTS OUTPUTS TTLICMOS +lV>---.----, R~_¥.(y-~CTR (20) DATA 6 • C4 TERMINAL READY DSRS (24) DATA SIGNAUNG RATE SELECT +6V RII-232 INPUTS AND OUTPUTS .±[.1 "F RS-Zsz -=- INPUTS I. OUTPUTS >_-+1;.;:4. TD (2) TRANSMIT DATA INPUTS OUTPUTS TTLICMOS ~--f~ DTR (20) DATA TERMINAL 7 INPUTS OUTPUTS TTLlCMOS ....--< SIGNAL GROUND (7) I---t=-< FIGURE 10. SIMPLE DUPLEX RS-232 PORT WITH CTSIRTS HANDSHAKING In applications requiring four R8-232 inputs and outputs (Figure 11), note that each circuit requires two charge pump capacitors (C1 and C2) but can share common reservoir 16 READY DSRS (24) DATA SlGNAUNG RATE SELECT DCD (8) DATA CARRIER DETECT R1 (22) RING INDICATOR SIGNAL GROUND (7) FIGURE 11. COMBINING TWO ICL2321 FOR 4 PAIRS OF R5-232 INPUTS AND OUTPUTS 11-12 DATA ACQUISITIO_ 12 DISPLAY DRIVERS PAGE DISPLAY DRIVERS DATA SHEETS CA3161 BCD to Seven Segment Decoder/Driver..........••.•.....•.••................. , • . . . 12-3 ICM7211, ICM7212 4-Digit ICM7211 (LCD) and ICM7212 (LED) Display Drive . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . 12-6 ICM722B B-Digit I1P Compatible LED Display Decoder Driver. . . . . . . . . . . . . • . . . . . . . . . . • . • . . . • . . . . . 12-19 ICM7231, ICM7232 Numeric/Alphanumeric Triplexed LCD Display Driver .. , , ... , , ..............••....• , .•. , 12-37 ICM7243 8-Character I1P-Compatible LED Display Decoder Driver , , , , , , , , , , , , , , , , . , , , , , , , , , . . • . 12·52 5i0.: U)' -' Q 12-1 CA3161 BCD to Seven Segment Decoder/Driver December 1993 Features Description The CA3161 E is a monolithic integrated circuit that performs the BCD to seven segment decoding function and features constant current segment drivers. When used with the • Eliminates Need for Output Current Umltlng Resistors CA3162E AID Converter the CA3161E provides a complete digital readout system with a minimum number of external • Pin Compatible wHh Other Industry Standard , parts. Decoders The CA3161 is supplied in the 16 lead dual in line plastic • Low Standby Power Dissipation 18mW (Typ) package (E suffix). • TTL Compatible Input logic Levels • 25mA (Typ) Constant Current Segmant Outputs Ordering Information PART NUMBER CA3161E TEMPERATURE RANGE PACKAGE O"C to +70"C 16 lead Plastic DIP Pinout Functional Block Dia ram I!! ~ {21 Q 22 (J m 5 I!! :::) ... A. NC 3 8a: w NC 5 ~ {23 Q 2° (J m GND 8 > 13 T ~ i 12 2'- ~ CONSTANT CURRENT SEGMENT DRIVERS ! 11 10 SI 15 14 iw 8 b C d I!! :::) ~0 a: !:.! a: •f ...z Q g w ::Ii CJ w III ::Ii CI w III tf ~ffi SEGMENT 8-g SEGMENT DRIVER II Cc m SEGMENT IDENnFlCAnON CAUTION; These devices are sensitive to elactrostailc discharge. Users should follow proper I.C. Handling Procedures. Copyright@Harrls Corporation 1993 12-3 D..> cn-0: File Number 1079.2 Specifications CA3161 Absolute Maximum Ratings Thermal Information DC VSUPPlY (Between Terminals 1 and 10) ..••..........• +7.0V Input Voltage (Terminals 1,2,6,7) •.....••.•••••.....•.• +5.5V Output Volta\le Output 'Off" .•.•.•.•..........•......••....•....••. +7V Output 'On" (Note 1) .....•...•..............•....•. +1OV Device Dissipation Up To TA +55°C .......•.........•...•••..•.••.•••. 1W Above TA +55°C ...........•..Derate Linearly at 10.5mWI"C Ambient Temperature Range Operating .••.•••.•.••....•....•••..•••...• 00C to +75°C Storage .•.•.••.••...•....•............. -6500 to +15O"C Lead Temperature (Soldering 1OS) •...•••...••...•••.. +265°C Thermal Resistance 9JA Plastic DIP Package .••.••.....•.••..•.••.•....• 100"CJW Junction Temperature ••...•••.•••...••..•.•........ +15O"C = = CAUTION: Stresses above Ihose/lsted in "Absolute Maximum RaUngs" may cause permanent damage to the device. This Is a stress only taUng and opetation of the device at these or any other condiUons above those indicated In the op8taUonal secUons of this specification Is not impHed. Electrical Specifications TA =+2500 LIMrrs MIN TYP MAX UNrrs 4.5 5 5.5 V - 3.5 8 rnA 18 25 32 rnA Output Current High (Vo = 5.5V) - 250 jU\ Input Voltage High (Logic "1" Level) 2 - - V Input Voltage Low (Logic "0" Level) - 0.8 V - jU\ - jU\ PARAMETERS VSUPPlY Operating Range, V+ Supply Current, 1+ (All Inputs High) Output Current Low (VO = 2V) - Input Current High (Logic "1") 2V -30 Input Current Low (Logic "0") OV -40 Propagation Delay Time tPHL - 2.6 • tpLH - 1.4 - lIS lIS NOTE: 1. This Is the maximum output voltage for any single output. The output voltage must be consistent with the maximum dissipation and derating curve for worst case conditions. Example: All segments 'ON", 100% duty cycle. 12-4 CA3161 TRUTH TABLE BINARY STATE ~ INPUTS 21 :z2 d e , 9 DISPLAY 0 L L L L L L L L L L H II LI 1 L L L H H L L H H H H OUTPUTS 2° a b c 2 L L H L L L H L L H L 3 L L H H L L L L H H L I I I 1~ I J 4 L H L L H L L H H L L LI 1 5 L H L H L H L L H L L 6 L H H L L H L L L L L 1~ 1- 7 L H H H L L L H H H H 8 H L L L L L L L L L L 9 H L L H L L L L H L L a I I a11 11 J 10 H L H L H H H H H H L 11 H L H H L H H L L L L 12 H H L L H L L H L L L 13 H H L H H H H L L L H 1- t-. LI 11 J L 14 H H H L L L H H L L L 15 H H H H H H H H H H H ,-11 BLANK 12·5 ~~ 0.> cn- ..JW -0: 00 ICM7211,ICM7212 4-Digit ICM7211 (LCD) and ICM7212 (LED) Display Drive December 1993 Features ICM7211 (LCD) Description • Four Digit Non-MuHlplexad 7 Segment LCD Display Outputa WIth Backplane Driver The ICM7211 (LCD) and ICM7212 (LED) devices constitute a family of non-multiplexed four-digit sewn-segment CMOS display decoder-drivers. • Complete Onboard· RC Oscillator plane Frequency to Generate Back· The ICM7211 devices are configured to drive conventional LCD displays by providing a complete RC oscillator, divider chain, backplane driver, and 28 segment outputs. • Backplane Input/Output Allows Simple Synchronization of Slave-DevIces to a Master • ICM7211 Devices Provide Separate DlgH Select Inputs to Accept MuHlplexed BCD Input (Pinout and Functionally Compatible WIth SlIIconlx DF411) • ICM7211 M Davlces Provide Data and Digit Addreaa Latches Controlled by Chip Select Inputs to Provide a Direct High Speed Proceaaor Interface • ICM7211 Decodes Binary to Hexadecimal; ICM7211 A Decodes Binary·. to Code B (0-9, Dash, E, H, L, P, Blank) • ICM7211A Available In Surface Mount Package Features ICM7212AM (LED) • 28 Current-Umltecl Segment Outputs ProvIde 4-DlgH Non-Multlplexed Direct LED Drive at >SmA Per Segment • Brightness Input Allows Direct Control of LED Segment Current With a Single PotenUometer or DlgHally as a Display Enable • ICM7212AM Davlee Provides Same Input Configuretlon and Output Decodfng Options as the ICM7211AM The ICM7212 devices are configured to drive commonanode LED displays, providing 28 current-controlled, low leakage, open-drain n-channel outputs. These devices provide a BRighTness input, which may be used at normal logic levels as a display enable, or with a potentiometer as a continuous display brightness control. These devices are available with multiplexed or microprocessor input configurations. The multiplexed versions provide four data inputs and four Digit Select inputs. This configuration is suitabla for interfacing with multiplexed BCD or binary output devices, such as the ICM7217, ICM7226, and ICL7135. The microprocessor wrslons provide data Input latches and Digit Address latches under control of high-speed Chip Select inputs. These devices simplify the task of implementing a cost-effectiw alphanumeric sewn-segment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and display updating. The standard devices will provide two different decoder configurations. The basic device will decode the four bit binary inputs into a sewn-segment alphanumeric hexadecimal output. The "A" wrsions will provide the "Code B" output code, i.e., 0-9, dash, E, H, L, Po blank. Either device will correctly decode true BCD to seven-segment decimal outputs. Devices In the ICM7211 and ICM7212 family are packaged in a standard 40 lead plastic dual-in-line and 44 lead plastiC MQFP packages and all inputs are fully protected against static discharge. Ordering Information PART NUMBER DISPLAY TYPE DISPLAY DECODING INPUT INTERFACING DISPLAY DRIVE TYPE TEMPERATURE RANGE PACKAGE Hexadecimal Multiplexed Direct Drive -4O"C to +85OC 40 Lead Plastic DIP LCD Hexadecimal Microprocessor Direct DrIve -4O"C to +85OC 40 Lead Plastic DIP LCD CodeB Multiplexed Direct Drive -4O"C to +85OC 40 Lead Plastic DIP ICM7211AMIPL LCD CodeB Microprocessor Direct Drive -4O"C to +85OC 40 Lead Plastic DIP ICM7211A1M44 LCD CodeB Multiplexed Direct DrIve -4O"C to +85OC 44 Lead MQFP Flatpack ICM7211AMIM44 LCD CodeB Microprocessor Direct Drive -4O"C to +85"C 44LeadMQFP Flatpack ICM7212AMIPL LED CodeB Microprocessor Convnon Anode -4O"C to +85OC 40 Lead PlastIc DIP ICM72111PL LCD ICM7211 MIPL ICM7211A1PL CAUTION: These davices are senab;'" to electrostatic discharge. Users should IoIIow prcper I.e. Handling Procedures. Copyright @ Harris Corporation 1993 12-8 File Number 3158 ICM7211,ICM7212 Pinouts ICM7211M,ICM7211AM (POIP) TOP VIEW ICM7211,ICM7211A (POIP) TOP VIEW 33 CHIP SELECT 1 32 DIGIT AORESS BIT 2 31 DIGIT AORESS BIT 1 ICM7212AM (POIP) TOP VIEW Yeo .1 BRT 5 82 b2 C2 33 CHIP SELECT 1 d2 32 DIGIT ADRESS BIT 2 31 DIGIT ADRESS BIT 1 84 -'L_ _ _ _ _.r- 12-7 ICM7211,ICM7212 Pinouts (Continued) ICM7211A (PLASTIC FLATPACK) TOP VIEW 82 VIiS b2 o..} C2 D3 d2 D2 D1 NC 82 NC DIGIT SELECT INPUTS g2 B3 } B2 DATA B1 INPUTS f2 d3 b3 BO C3 f4 ICM7211AM (PLASTIC FlATPACK) TOP VIEW iii:: &.~~:;1ililii8 82 Vss b2 CHIP SELECT 2 C2 CHIP SELECT 1 d2 DIGITAL ADRESS BIT 2 82 DIGITAL ADRESS BIT 1 NC NC 92 f2 -} B2 B1 d3 b3 BO f4 C3 8o.\2:i~!3;J3. 12-8 DATA INPUTS ICAf7211,ICAf7212 Functional Block Diagrams ICM7211A D4 SEGMENT OUTPUTS 03 D2 01 SEGMENT OUTPUTS SEGMENT OUTPUTS SEGMENT OUTPUTS DIGIT SELECT INPUTS OSCILLATOR 19kHz FREE-RUNNING OSCILLATOR INPUT +128 BP INPUT/OUTPUT ICM7211AM D4 SEGMENT OUTPUTS 03 02 01 SEGMENT OUTPUTS SEGMENT OUTPUTS SEGMENT OUTPUTS s~ o.W (I)~ -II: Cc DATA INPUTS 2-BIT DIGIT AORESS INPUT SEL~~~~ SEL~~f2 OSCILLATOR INPUT 19kHz ----r--;:::===:-""1~FR::E:E-:R~U:N:N~IN:G:.J 12-9 BP INPUTIOUTPUT ICAf7211,ICAf7212 Functional Block Diagrams (Continued) ICM7212AM D4 SEGMENT OUTPUTS D3 D2 SEGMENT OUTPUTS SEGMENT OUTPUTS 01 SEGMENT OUTPUTS I DATA INPUTS 2-BIT DIGIT AORESS INPUT ~ SELECT 1 SELI~D~P2 12-10 Specifications ICM7211, ICM7212 Absolute Maximum Ratings Thermal Information Supply Voltage (Voo - Vss) •••.••••••••••••••••..•••.••• 6.5V Input Voltage (Any Terminal) (Note 1) •••. Vss- 0.3V to Voe. + 0.3V Storage Temperature Range ••.••.••••••••..• -55"0 to +1250 C Lead Temperature (Soldering, lOs) •........••........ +3oooC Junction Temperature. • • • • • • • • • • • • • • • • • • • • • • • • • • • • . +150°C Thermal Resistance OJA Plastic DIP Package •..•••••• . • • • • • • • • . • • • . . . •• 500 cm Plastic MQFP Package. • • • • • • • • • • • • • • • • • • • • • • •• 8O"CrN Operating Temperature Range ...•.•••••••••••• -4COC to +85°C CAUTION: Stresses abo... thoBB listed in 'Absolute Maximum Ratings' msy cause perm8118nt damsge to the d8vica. This is a straas only rating and operation 01 the dav/ce at thesa or any other condiUons aboI'8 those indicated In the operational sections 01 this specillcation is not IrnpUed. Electrical Specifications PARAMETER TEST CONDITIONS I MIN TYP MAX UNITS ICM7211 CHARACTERISnCS (LCD) Voo = 5V 10%, T A = +25°C, VSS = OV Unless Otherwise Specified. Operating Supply Voltage Range (Voo - Vssl, VSUPPlY Operating Current, 100 Test circuit, Display blank Oscillator Input Current, losci Pin 36 Segment Rise/Fall Time, tR, tF CL =200pF Backplane Rise/Fall Time, IR, ~ CL = 5000pF Oscillator Frequency, fosc Pin 38 Floating Backplane Frequency, fsp Pin 36 Floating 3 5 6 V - 10 50 ±2 ±10 I1A I1A 0.5 - lIS - kHz - 1.5 19 - lIS - 150 - Hz 4 5 6 V 10 50 200 - ICM7212 CHARACTERISTICS (Common Anode LED) Operating Supply Voltage Range (Voo - Vssl, VSUPPlY Operating Current Display Off. ISTBY Pin 5 (Brightness). Pins 27-34 Vss Operating Current. 100 Pin 5 at Voo, Display all 8's Segment Leakage Current, ISLK Segment Off - ±0.01 ±1 I1A Segment On Current. ISEG Segment On, Va = +3V 5 8 - rnA Logical "1' Input Voltage, VIH 4 - - V - - Logical "(1' Input Voltage, VIL 1 V ±0.01 ±1 I1A I1A rnA INPUTCHARACTERISnCS (ICM7211 and ICM7212) Input Leakage Current. IILK Pins 27-34 Input Capacitance, CIN Pins 27-34 BPlBrightness InputLeakage. IBPLK Measured at Pin 5 with Pin 36 at Vss BPlBrightness Input Capacitance. CSPI All Devicas - - pF 5 ±0.01 ±1 I1A 200 - pF - lIS AC CHARACTERISTICS - MULnPLEXED INPUT CONFIGURATION Digit Select Active Pulse Width. lwH Refer to nming Diagrams 1 Data Setup Time. los 500 Data Hold Time,loH 200 Inter-Digit Select Time, "os - - 2 - 200 - ns ns - lIS - - ns - ns AC CHARACTERISnCS - MICROPROCESSOR INTERFACE Chip Select Active Pulse Width. tWL Other Chip Select either held active, or both driven together Data Setup Time, los 100 - Data Hold Time. IoH 10 0 Inter-Chip Select Time. tiCS 2 - - ns lIS NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltagas greater than VDO or less than Vss may cause destrUCtive device latchup. For this reason. It Is recommended that no Inputs from external sources not operating on the same power supply be applied to the device before its supply is established. and that In multiple supply systems. the supply to the ICM7211 and ICM7212 be turned on first. 12-11 Specifications iCM7211,ICM7212 Input Definitions In this table, Voo and Vss are considered to be normal operating InputJoglc levels. Actual input low and high levels ere specified under Operating Characteristics. For lowest power consumption, Input signals should swing over the full supply. INPUT TERMINAL BO 27 B1 28 B2 29 B3 30 OSC (LCD Devices Only) 36 CONDITIONS FUNCTION =logical One =Logical Zero Voo =logical One Vss =logical Zero Voo =Logical One Vss =Logical Zero Voo =logical One Vss =LogIcal Zero Ones (Least Significant) Voo Vss Twos Data Input Bits Fours Eights (Most SlgnHlcant) Floating or with external capacitor to Voo Oscillator Input Vss Disables BP output devices, allowing segments to be synchronized to an external signal Input at the BP terminal (Pin 5) ICM7211 Multiplexed-Binary Input Configuration INPUT TERMINAL 01 31 FUNCTION CONDITIONS Voo =Inactive Vss =Active 01 Digit Select (Least Significant) 02 32 D3 33 03 Digit Select D4 34 D4 Digit Select (Most Significant) 02 Digit Select ICM7211 MIICM7212M Microprocessor Interface Input Configuration INPUT DESCRIPTION TERMINAL DA1 Digit Address Bit 1 (LSB) 31 DA2 Digit Address Bit 2 (MSB) 32 CS1 Chip Select 1 33 CS2 Chip Select 2 34 FUNCTION CONDITIONS =logical One =Logical Zero Voo =logical One Vss =Logical zero Voo =Inactive Vss =Active Voo =Inactive Vss =Active Voo Vss 12-12 DA1 & DA2 serve as a two bit Digit Address Input DA2, DA1 00 selects D4 DA2, DA1 01 selects 03 DA2, DA1 10 selects D2 DA2, DA1 11 selects 01 = = = = When both CS1 and CS2 are taken low, the data at the Data and Digit Select code Inputs are written Into the Input latches. On the rising edge of either Chip Select, the data Is decoded and written Into the output latches. ICAf7211,ICAf7212 Timing Diagrams DIGIT SELECT ~, DIGIT SELECT Dt. _ _ _ _ _ _'""""'f DATAVAUD ~, FIGURE 1. MULTIPLEXED INPUT CSi ~~ (CS2) __________________-J/ CS2 (CS1) DATA AND DIGIT ADDRESS "_DON'TCARE FIGURE 2. MICROPROCESSOR INTERFACE INPUT Typical Performance Curves 30 LCD DEVICES, TEST CIRCUIT DISPLAY BLANK, PIN 36 OPEN 25 180 I I I I I I .' TA",-2ff'C/ 20 01 TA-+25 C " " , V • . / ... 2 3 4 eDo ~ 5 [...0'" N' '/ 110 .' .!! 1 VsuppM FIGURE 3. ICM7211 OPERATING SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE ~ ~ .. .. o 7 ", Case. 22P!,.. ~ Cosc= 220pF 30 & ./ 1/ -- " ....- 60 l....o": ~ "'TA -+700C ~~ I I .-::: ;io"'" I I I I 5 COSC·OpF (PIN 36 OPEN) 120 ./ ~ 10 II I 150 ", , LCD DEVICES, TA =+2SOC 2 3 I I 4 Vsupp(V) 5 I & FIGURE 4. ICM7211 BACKPLANE FREQUENCY AS A FUNC:TION OF SUPPLY VOLTAGE 12-13 ICM7211,ICM7212 Typical Performance Curves (Continued) 15 I PIN 5 AT VOl) TA. +ZSOC .,'" .,- " 12 I I 't' / 8 L ./ VsuppaSV -- ~ / If/ / .VSUpp·4V r/ 5 :/ 4 l- / 2 I' 2 3 / SEGMENT OUTPUT AT +3V TAa+25oC 10 Vsuppa6V ~ 10 I 5 4 - ./ ~ o o 6 / ,1 Vo(V) 2 3 4 VOLTAGE ON BRT PIN 5 (V) 5 6 FIGURE 6. ICM7212 LED SEGMENT CURRENT AS A FUNCTION OF BRIGHTNESS CONTROL VOLTAGE FIGURE S. ICM7212 LED SEGMENT CURRENT AS A FUNCTION OF OUTPUT VOLTAGE 1800 LED DEVICES, DISPLAY ALL EIGHTS LED FORWARD VOLTAGE DROP 1500 VFLED .. 1.7V, PIN 5 AT VOl) TA. +2SoC i oS II: ~ 1200 ~ V 800 600 / I'" .. ~ , ...... I.,..;' 300 o 5 VSUpp(V) 4 6 FIGURE 7. ICM7212 OPERATING POWER (LED DISPLAy) AS A FUNCTION OF SUPPLY VOLTAGE Description Of Operation LCD Devices The LCD devices In the family (ICM7211, ICM7211A, ICM7211 M, ICM7211AM) provide outputs suitable for driving conventional four-digit, seven-segment LCD displays. These devices include 28 individual segment drivers, backplane driver, and a seH-contained oscillator and divider chain to generate the backplane frequency. The segment and backplane drivers each consist of a CMOS inverter, with the n-channel and p-channel devices ratioed to provide identical on resistances, and thus equal rise and fall times. This eliminates any DC component, which could arise from differing rise and fall times, and ensures maximum display life. The backplane .output devices can be disabled by connecting the OSCillator input (pin 36) to Vss. This allows the 28 segment outputs to be synchronized directly to a signal Input at the BP terminal (pin 5). In this manner, several slave devices may be cascaded to the backplane output of one master device, or the backplane may be derived from an external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave device represents a load of approximately 200pF (comparable to one additional segment). Thus the limitation of the number of devices that can be slaved to one master device backplane driver is the additional load represented by the 12-14 ICM7211,ICM7212 larger backplane of displays of more than four digits. A good rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less than about 51ls. The backplane output driver should handle the backplane to a display of 16 one-half inch characters. It is recommended, if more than four devices are to be slaved together, the backplane signal be derived externally and all the ICM7211 devices be slaved to it. This external signal should be capable of driving very large capacitive loads with short (1 - 21ls) rise and fall times. The maximum frequency for a backplane signal should be about 150Hz although this may be too fast for optimum display response at lower display temperatures, depending on the display type. voltage at this pin is transferred to the gates of the output devices for ·on" segments, and thus directly modulates the transistor's ·on" resistance. A brightness control can be easily implemented with a single potentiometer controlling the voltage at pin 5, connected as in Figure 9. The potentiometer should be a high value (100k!l to 1M!l) to minimize power consumption, which can be Significant when the display is off. ----1---- Voo (LED ANODES) 100kn TO 1MO The onboard oscillator is designed to free run at approximately 19kHz at microampere current levels. The oscillator frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running; the oscillator frequency may be reduced by connecting an external capacitor between the OSCillator terminal and VOl} The oscillator may also be overdriven if desired, although care must be taken to ensure that the backplane driver is not disabled during the negative portion of the overdriving signal (which could cause a D.C. component to the display). This can be done by driving the OSCillator input between the positive supply and a level out of the range where the backplane disable is sensed (about one fifth of the supply voltage above Vss). Another technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsecond. The backplane disable sensing circuit will not respond to signals of this duration. OSCILLATOR n r-tl-l " " " " " n n r"""t~ n n n rFREQUENCY.JU UUUU UUU UUUU ~128CYCLES BACKPLANE ----..06 INPUTIOUTPUT 64 CYCLES 1----"'" 64 CYCLES OFF SEGMENTS SEGMEN~ - - -....1 r- I...____ _ BRIGHTNESS PINS FIGURE 9. BRIGHTNESS CONTROL The BRighTness input may also be operated digitally as a display enable; when high, the display is fully on, and low fully off. The display brightness may also be controlled by varying the duty cycle of a signal swinging between the two voltages at the BRighTness input. Note that the LED device has two connections for Vss; both of these pins should be connected. The double connection is necessary to minimize effecis of bond wire resistance with the large total display currents possible. When operating LED devices at higher temperatures and/or higher supply voltages, the device power dissipation may need to be reduced to prevent excessive chip temperatures. The maximum power dissipation is 1W at +25 0 C, derated linearly above +350 C to 500mW at +70oC (-15mW/oC above +35°C). Power dissipation for the device is given by: where V FLEO is the LED forward voltage drop, ISEG is segment current, and nSEG is the number of ·on" segments. It is recommended that if the device is to be operated at elevated temperatures the segment current be limited by use of the BRighTness input to keep power dissipation within the limits described above. Input Configurations and Output Codes FIGURE 8. DISPLAY WAVEFORMS LED Devices The LED device in the family (ICM7212AM) provides outputs suitable for directly driving four-digit, seven-segment common-anode LED displays. These devices include 28 individual segment drivers, each consisting of a low-leakage, current-controlled, open-drain, n-channel transistor. The drain current of these transistors can be controlled by varying the voltage at the BRtrighTness input (pin 5). The The standard devices in the ICM7211 and ICM7212 family accept a four-bit true binary (Le., pOSitive level = logical one) input at pins 27 thru 30, least significant bit at pin 27 ascending to the most significant bit at pin 30. The ICM7211 and ICM7211 M devices decode this binary input into a seven- segment alphanumeric hexadecimal output, while the ICM7211A, ICM7211AM, and ICM7212AM decode the binary input into seven-segment alphanumeric ·Code B" output, Le. 0-9, dash, E, H, L, P. blank. These codes are shown explicitly in Table 1. Either decoder option will 12-15 ~ffi c..> -a: Cc 0- ICM7211,ICM7212 correctly decode true BCD to a seven-segment decimal output. TABLE 1. OUTPUT CODES BINARY HEXADECIMAL ICM7211 1CM7211M CODEB 1CM7211A 1CM7212AM B3 82 81 SO 0 0 0 0 a a 0 0 0 1 I I 0 0 1 0 0 0 1 1 0 1 0 0 2 3 Lf 2 3 Lf 0 1 0 1 5 5 0 1 1 0 5 5 0 1 1 1 7 1 0 0 0 1 0 0 1 1 0 1 Q B 9 R 7 B 9 1 0 1 1 b 1 1 0 0 L H 1 1 0 1 d L 1 1 1 0 E P 1 1 1 1 F BLANK r These devices are actually mask-programmable to provide any 16 combinations of the seven segment outputs decoded from the four input bits. For large quantily orders custom decoder options can be arranged.· Contact the factory for details. The ICM7211 and ICM7211A devices are designed to accept multiplexed binary or BCD input. These devices provide four separate digit lines (least significant digit at pin 31 ascending to most significant digit at pin 34), each of which when taken to a positive level d8codes and stores in the output latches of its respective digit the character corresponding to the data at the input port, pins 27 through 30. The ICM7211M, ICM7211AM, and ICM7212AM devices are intended to accept data from a data bus under processor control. In these devices, the four data input bits and the two-bit digit address (DA1 pin 31, DA2 pin 32) are written into i~ buffer latches when both chip select inputs (CST pin 33, CS2 pin 34) are taken low. On the rising edge of either chip select input, the content of the data input latches is decoded and stored in the output latches of the digit selected by the contents of the digit address latches. An address of 00 writes into 04, DA2 = 0, DA1 = 1 writes into 03, DA2. 1, DA1 0 writes into 02, and 11 writes into 01. The timing relationships for inputting data are shown in Figure 2, and the chip select pulse widths and data setup and hold times are specified under Operating Characteristics. = E I FIGURE 10. SEGMENT ASSIGNMENT 12-16 ICAf7211,ICAf7212 Test Circuit Voo ~--"";:+~II~-~--'" VA V (MICROPROCESSOR"\ DO \.VERSION ) . MULTIPLEXE~ EACH SEGMENT VA ( \'VERSION OUTPUT 10 BACKPLANE ) WlTHA200pF CAPACITOR FIGURE 11. Typical Applications De D7 D6 os • BACKPLANE t 2 SLAVE 28 + l i V - Voo BCDIBIN ARY oATA VA OSC SEGMENTS HIGH ORDER ICM7211A B3-BO D4D3D2D1 BP 14 I 4 ~ D3 01 D2 DODD DODD Ll Ll Ll Ll Ll Ll Ll Ll 8 DIGIT LCD DISPLAY J.L D4 BACKPLANE MASTER +liV~ Voo J.L VA OSC 83·BO -hI 28 SEGMENTS LOW ORDER ICM7211A D4 D3 02 D1 BP 14 De D7 D6 DIGIT SELECTS os D4 D3 D2 01 FIGURE 12. GANGED ICM7211's DRIVING B-DIGIT LCD DISPLAY 12·17 BACKPLANE 1 ICAf721~/CAf7212 Typical Applications (Continued) 8 DIGIT LCD DISPLAY DDDDDODD L1 L1 L1 L1 L1 L1 L1 L1 h +6 40 28 Vee Yoo ~ ~ f* y20 P1027 ss 4 RESET 7EA ,~ --_. 3XTAL2 I-- 28 29 30 31 32 33 P1734 P2021 2XTAL1 I-- ICM7211M HIGH ORDER DIGITS 110 I 1YOO 2,3,4 36 V SEGMENTS 6-28 BPS ss DATA 37-40 3&OSC B0-B3 A • DS1 DS2 CSi CS2 27 28 29 30 31 32 33 34 . ICM7211M LOW ORDER DIGITS 2,3,4 1 YOO 1--+6V 6-28 SEGMENTS 36 V BP5 37-40 ss DATA 3&OSC BCl-aa • DS1 DS2 CSi CS2 27 28 29 30 31 32 33 34 . 22 23 24 Nc - 5SS 8OC48 "COMPUTER P2738 -110 1 TO INPUT E DB012 13 14 15 18 17 18 DB718 39T1 81NT ALE 11 36 3& 37 R'ER' PROG Wii ii6 9 26 I 10 8 II FIGURE 13. 80C48 MICROPROCESSOR INTERFACE 12-18 . ~ ICM7228 a-Digit ~p Compatible LED Display Decoder Driver December 1993 Features Description • Improved 2nd Source to Maxim ICM7218 • Fast Write Access Time of 200ns The Harris ICM722B display driver interfaces microprocessors to an B digit, 7 segment, numeric LED display. Included on chip are two types of 7 segment decoder, multiplex scan circuitry, LED display segment drivers, LED display digit drivers and an B-byte static memory as display RAM. • MuHiple Microprocessor Compatible Versions • Hexadecimal, Code B and No Decode Modes • Individual Segment Control with "No Decode" Feature • Digit and Segment Drivers On-Chip • Non-Overlapping Digits Drive • Common Anode and Common Cathode LED Versions • Low Power CMOS Architecture • Single 5V Supply Applications • Instrumentation • Test Equipment • Hand Held Instruments • Bargraph Displays • Numeric and Non-Numeric Panel Displays • High and Low Temperature Environments where LCD Display Integrity is Compromised Data can be written to the ICM722BA and ICM722BB's display RAM in sequential B digit update or in single digit update formal. Data is written to the ICM722BC and ICM722BD display RAM in parallel random access formal. The ICM722BA and ICM722BC drive common anode displays. The ICM722BB and ICM722BD drive common cathode displays. All versions can display the RAM data as either Hexadecimal or Code B formal. The ICM722BA and ICM722BB incorporate a No Decode mode allowing each bit of each digit's RAM word to drive individual display segments resulting in independent control of all display segments. As a reSUlt, bargraph and other irregular display segments and formats can be driven directly by this chip. The Harris ICM722B is an alternative to both the Maxim ICM721B and the Harris ICM721B display drivers. Notice that the ICM722BA1B has an additional single digit access mode. This could make the Harris ICM721BAIB software incompatible with ICM722BAfB operation. Ordering Information TEMP. RANGE PACKAGE ICM722BAIPI PART NUMBER Sequential Common Anode -40oC to +85OC 28 Lead Plastic DIP ICM7228BIPI Sequential Common Cathode -40oC to +8SOC 28 Lead Plastic DIP ICM7228CIPI Random Common Anode -4QDC to +85°C 28 Lead Plastic DIP ICM7228DIPI Random Common Cathode -40°C to +85OC 2B Lead Plastic DIP ICM722BAIJI Sequential Common Anode -40OC to +85OC 28 Lead Ceramic DIP ICM7228BIJI Sequential Common Cathode -40oC to +8SOC 28 Lead Ceramic DIP ICM7228CIJI Random Common Anode -40oC to +85°C 28 Lead Ceramic DIP ICM7228DIJI Random Common Cathode 28 Lead Ceramic DIP DATA ENTRY PROTOCOL DISPLAY TYPE ICM722BAIBI Sequential Common Anode -40°C to +85°C -40oC to +85OC ICM7228BIBI Sequential Common Cathode -40oC to +85°C 28 LeadSOIC ICM7228CIBI Random Common Anode -40oC to +85°C 28 Lead SOIC ICM7228DIBI Random Common Cathode -4Q°C to +85OC 28 Lead SOIC ICM722BAMJI Sequential Common Anode -55°C to +125°C 28 Lead Ceramic DIP ICM7228BMJI Sequential Common Cathode -55°C to +125°C 28 Lead Ceramic DIP ICM7228CMJI Random Common Anode -55°C to +125°C 28 Lead Ceramic DIP ICM7228DMJI Random Common Cathode -55°C to +125°C 28 Lead Ceramic DIP ICM7228AMJI883B Sequential Common Anode -55°C to +125°C 28 Lead Ceramic DIP ICM7228BMJI883B Sequential Common Cathode -55°C to +125°C 28 Lead Ceramic DIP ICM7228CMJI883B Random Common Anode -55°C to +125°C 28 Lead Ceramic DIP ICM7228DMJI883B Random Common Cathode -55°C to +125OC 28 Lead Ceramic DIP CAUTION: These devices are sensnive to electrostatic dischsrge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 12-19 Sffi a.. > 0 -II: Cc 28 LeadSOIC File Number 3160 ICM7228 Pinouts ICM72288 (CDIP, PCIP SOIC) COMMON CATHODE TOP VIEW ICM7228A (CDIP, PCIP SOIC) COMMON ANODE TOP VIEW Vas DlGIT4 1 SEGe 1 SEGe 2 DIGIT 7 SEGb 3 SEGg DP4 SEGd DIGITS DIGIT 1 4 106 (HEXAICODn) 106 (HEXAICODE B) IDS(~) IDS (DECODE) 107 (DATA COMING) DIGITI 107 (DATA COMING) Wiii'Ii DIGIT 7 WFii'i'f DIGIT 4 104 (SHUTDOWN) 10 ICM7228C (CDIP, PCIP SOIC) COMMON ANODE TOP VIEW ICM7228D (CDIP, PCIP SOIC) COMMON CATHODE TOP VIEW DlGIT4 1 DIGIT 3 DIGIT 1 DAO (DIGIT ADDRESS 0) 5 DAO (DIGIT ADDRESS 0) DA1 (DIGIT ADDRESS 1) I DA1 (DIGIT ADDRESS 1) I 107 (INPUT DP) 107 (INPUTDP) 7 WFii'i'f 8 HEXAICODE BlSHufDdNN 9 HEXAICODE BlSHUfOOWN 9 DA2 (DIGIT ADDRESS 2) 10 DA2 (DIGIT ADDRESS 2) 10 WRiTE 12·20 8 ICM7228 Functional Block Diagram ICM7228C. ICM7228D ICM7228A. ICM7228B 100·107 INPUT DATA 104·107 CONTROL INPUTS MODE * 81,..- "" t ~ DECODE j-: t SHUTDOWN CONTROL LOGIC HEXAICODEB , 11-' 1V ~ .- ~ ,41,..- ...... !t I' t "--- * 'L , WRITE ADDRESS COUNTER '..L , READ -ADDRESS MULTlPLEXER ~ ,41-' !} +- .... MULTlPLEX OSCILLATOR r-!I-' I·BYTE STATlC RAM ...11-' READ ADDRESS. DIGIT MULTlPLEXER HEXADECIMAU CODEB 7,; DECODER SHUTDOWN 1 17 1 t 71-' ,31; ,1~ WRITE ADDRESS COUNTER -,8 L ...1V 5 ... V THREE LEVEL INPUT LOGIC r- l' 8-BYTE STATlC RAM 100 ·103 DAD· DA2 107 DIGIT DATA INPUT WRITE ADDRESS HEXADECIMAU CODE BI SHUTDOWN WRITE HEXADECIMAU CODEB DECODER MULTlPLEX OSCILLATDR ,1V It- DECODE NO-DECODE 8 1 DECIMAL POINT 8 SEGMENT DRIVERS I ... V 11; ... "" 1 ... INTERDIGIT BLANKING 7 8 DIGIT DRIVERS DECIMAL POINT 8 SEGMENT DRIVERS 8V I, 1~ , INTERDIGIT BLANKING , DIGIT DRIVERS ~ffi 0.> cn-IE: Cc 12·21 Specifications ICM7228 Absolute Maximum Ratings Thermal Information Supply Voltage (Voo - vss> •••••••••••••••••••••••••••••• 6V Digit OUtput Current. ••••••••••••••••••••••••••••••• 500mA Segment Output Current •••••••••••••••••••••••••••• 100mA Input Voltage (Note 1) (Any Terminal) •• (Vss-0.3V)< VIN < (Voo+ 0.3V) Storage Temperature Range •••••••••••••• -65·C < Ts < +16O"C Lead Temperature (Soldering 108) •••••••••••••••••••• +300·C Junction Temperature IPI,IJI,IBI Suffix •••••••••••••••••••••••••••••••• +15O"C MIJI Suffix. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • +175·C Thermal Resistance 940 2O"CNI Ceramic DIP Package ••••••••••••••• Plastic DIP Package •••••••••••••••• SOIC Package ••••••••..••.•••••••• Operating Temperature Range IPI, IJI, IBI Suffix •••••••••••••••••••••• -40"C < TA < +85·C MWI Suffix •••••••••••••••••••••••••• -5500 < TA < +125·C CAUTION: Stresses above thoss listed in -Absolute Maximum Ratings" may cause permanent damage to ths davlce. ThIs Is a stress only rating and opIHBtion of the device at thsss or any other conditions above thOSB indicated in ths operational sections of this specification Is not ;mpHed. Electrical Specifications voo = +5.0V ± 10%, Vss = OV, Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI,IJI, LBI DEVICES PARAMETER Supply Voltage Range, VSUPPlY TEST CONDrTlONS Operating MIN 4 TA=+25·C MAX TYP - 6 - Power Down Mode 2 O\iiescent Supply Current, IQ Shutdown, ICM7228A, IMC7228B 1 2.5 100 100 Operating Supply Current, Shutdown, 7228C, 72280 Common Anode, ICM7228A1C Segments = ON Outputs = OPEN - 200 450 Common Anode, ICM7228A1C Segments = OFF Outputs = OPEN - 100 450 Common Cathode, ICM7228B1D Segments = ON Outputs = OPEN - 250 - 100 Common Cathode, ICM7228B1D Segments = OFF Outputs = OPEN Digit Drive Current, IOIG Digit Leakage Current, lou< Common Anode, ICM7228A1C VOUT = Voo - 2.0V Common Cathode, ICM7228B1D VOUT = Vss + 1.0V Shutdown Mode, VOUT = 2.0V Common Anode, ICM7228A1C Shutdown Mode, VOUT = 5.0V Common Cathode, 7228810 Peak Segment Drive Current, ISEG Segment Leakage Current, Isu< Common Anode, ICM7228A1C VOUT= Vss + 1.0V Common Cathode, 7228810 VOUT = Voo - 2.0V Shutdown Mode, VOUT = Voo Common Anode, ICM7228A1C Shutdown Mode, VOUT = Vss Common Cathode, ICM7228B1D Input Leakage Current, IlL All Inputs except Pin 9 ICM7228C, ICM722aD VIN = Vss All Inputs except Pin 9 ICM7228C, ICM7228D VIN = 5.0V Display Scan Rate, fMUX Inter-Digit Blanking Time, ~OB Per Digit 12-22 -40·C:s TA :s +85"C MIN TVP MAX 4 2 - - 6 100 2.5 100 200 450 - 100 450 450 - 250 450 175 450 - 175 450 200 - 50 - - - - - 1 100 1 100 1 100 - 1 100 20 25 - 20 10 12 - 10 - - - 1 50 - 1 50 - 1 50 1 50 - 1 - - 1 - - -1 - - -1 - 390 - 390 2 10 - - 40 2 - V - 1 175 UNITS - IIA IIA mA IIA mA IIA IIA Hz jIS Specifications ICM7228 Electrical Specifications Voo = +5.0V ± 10%. Vss = OV. Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI,IJI, LBI DEVICES (Continued) PARAMETER TEST CONDITIONS Logicar"l" Input Voltege. VINH Floating Input. VINF Logical "0- Input Voltege. VIN~ Three Level Input Impedance. ZIN Three Level Input: Pin 9 ICM7228C. ICM7228D Hexadecimal Voo=5V Three Level Input: Pin 9 ICM7228C. ICM7228D Code B Voo=5V Three Level Input: Pin 9 ICM7228C. ICM7228D Shutdown Voo=5V Vcc=5V Pin 9 of ICM7228C and ICM7228D MIN TA =+25°C TYP MAX - - 4.2 - - V 2.0 - 3.0 2.0 - 3.0 V - - 0.8 - - 0.8 V 50 - - 50 - - kll - - 2.0 - - V - - 0.8 - - 0.8 V 250 850 540 - AU Inputs except 2.0 Pin 9 of ICM7228C. ICM7228D Voo=5V Logical "0" Input Voltege, VI~ AU Inputs except Pin 9 of ICM7228C. ICM7228D Voo=5V SWITCHING SPECIFICATIONS Voo = +5.0V ± 10%. Vss = OV. VIL = +D.4V. VIH = +2.4V Write Pulsewidth (Low).1wL. 100 200 Mode Hold Time. tMH ICM7228A. ICM7228B 0 Mode Setup Time. tMS ICM7228A. ICM7228B 250 .e5 150 250 160 0 .eO 250 110 0 .eO Date Setup Time. los Date Hold Time,loH Digit Address Setup Time,l.\s Digit Address Hold Time. tAH Electrical Specifications ICM7228C. ICM7228D ICM7228C, ICM7228D UNITS 4.2 Logical "1" Input Voltage. VIH Write Pulsewidth (High). IwH -4ooC ~ TA ~ +sSOC MAX TVP MIN - 1200 0 250 250 0 250 0 - - ns ns ns ns ns ns ns ns voo = +5.0V ± 10%. Vss = OV. Unless Otherwise Specified MILITARY TEMPERATURE RANGE, MIJI, DEVICES -5SOC~TA~+125OC TA=+25OC PARAMETER TEST CONDITIONS Supply Voltege Range. VSUPPlY Quiescent Supply Current. IQ MIN TVP MAX MIN TYP MAX Operating 4 4 V 2 2 - V Shutdown. ICM7228A. IMC72288 - - - 6 Power Down Mode - 6 1 100 J1A 2.5 100 - 200 550 J1A J1A 450 - 100 450 J1A 250 450 - 250 550 J1A - 175 450 - 175 450 J1A Common Anode. Voo = 5V VOUT = Voo - 2.0V 200 - - 170 Common Cathode. Voo = 5V VOUT=Vss+l.0V 50 - - 35 - - Shutdown, 7228C. 72280 Operating Supply Current, 100 Common Anode, ICM7228A1C Segments = ON Outputs = OPEN Common Anode. ICM7228AIC Segments = OFF Outputs = OPEN Common Cathode, ICM7228B1D Segments = ON Outpute '" OPEN Common Cathode, ICM7228B1D Segments = OFF Outputs = OPEN Digit Drive Current, IOIG - UNITS 12-23 1 100 - 2.5 100 200 450 - 100 - mA mA Specifications ICM7228 Electrical Specifications voo = +5.0V ± 10%, Vss = OV, Unless Otherwise Specified MIUrARY TEMPERATURE RANGE, MIJI, DEVICES (ConUnued) TA=+25OC PARAMETER Digit Leakage Current, IOLK Peak Segment Drive Current, ISEG Segment Leakage Current, IBlK Input Leakage Current, III , Display Scan Rate, fMUX Inter-Digit Blanking TIme, ~OB Logical '1' Input Voltsge, VINH TEST CONDITIONS UNITS · Shutdown Mode, VOUT = 5.0V Common Cathode, 7228810 Common Anode, ICM7228A1C VOUT= Vss + 1.0V,Voo= 5V Common Cathode, 7228810 VOUT = Voo - 2.0V, Voo = 5V Shutdown Mode, VOUT = Voo Common Anode, ICM7228A1C · 1 100 · 1 20 25 . 20 25 10 12 - 10 12 - - 1 50 - 1 50 JIA · 1 50 - 1 50 JIA - - 1 - . 1 JIA ·1 · - -1 JIA - 390 Hz 10 - 2 4.2 lIS V - 3.0 2.4 - 3.0 V - 0.8 - - 0.4 V - - 50 - - 2.0 - - - 0.8 - - 0.8 - 250 1200 115 840 -65 165 160 -60 100 -60 2 4.2 - - ICM7228A, ICM7228B 250 Oats Setup TIme,los Oats Hold TIme,loH Digit Address Setup TIme, tAs Digit Address Hold TIme, tAH ·55"C S TA S +125°C MIN TVP MAX 1 100 Shutdown Mode, VOUT = 2.0V Common Anode, ICM7228AIC 390 10 - Thres Level Input: Pin 9 ICM7228C, ICM7228D Hexadecimal Voo=5V Floating Input, VINF Thres Level Input: Pin 9 2.0 ICM7228C, ICM7228D Code B Voo=5V Logical "f1' Input Voltsge, VINl Thres Level Input: PinS ICM722SC, ICM7228D Shutdown Voo=5V Three Level Input Impedance, ZIN Vcc=5V 50 Pin 9 of ICM7228C and ICM7228D Logical'1' Input Voltsge, VIH AU Inputs except 2.0 Pin 9 of ICM7228C, ICM7228D Voo=5V Logical "f1' Input Voltsge, Vil All Inputs except Pin 9 of ICM7228C, ICM7228D· Voo=5V SWITCHiNG SPECIFICATiONS (Voo = +5.0V ± 10%, Vss = OV, Vil = +D.4V, VIH = +2.4V) Write Pulsewidth (Low), 1wL 200 100 Write Pulsewidth (High),1wH 540 850 Mode Hold TIme, tMH ICM7228A, ICM7228B 0 -65 Mode Setup TIme, ~s MAX. TVP 1 Shutdown Mode, VOUT = Vss Common Cathode, ICM7228B1D AU Inputs except Pin 9 ICM7228C, ICM7228D VIN = Vss All Inputs except Pin 9 ICM7228C, ICM7228D VIN = 5.0V Per Digit MIN 250 0 150 160 ICM7228C, ICM7228D 250 -60 110 ICM7228C, ICM7228D 0 -60 100 - - - · 0 250 250 0 250 0 100 - - - - JIA JIA rnA rnA kn V V ns ns ns ns ns ns ns ns NOTES: 1. Due to the SCR structure Intierent in the CMOS process used to fabrICate these devices, connecting any terminal to a voltage greater then Voo or less then Vss may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM7228 should be turned on first 12-24 ICM7228 Timing Diagrams .-------rL MODEJl TYPE OF DECODER?lD6 DECODEINO DECODE? 105 SHUTDOWN? 104 DATA COMING 107 TYPE OF DECODER?ID6 DECODEINO DECODE? 105 SHUTDOWN?I04 DATA COMING 107 FIGURE 1. ICM7228AIB WRITE CYCLE DIGIT ADDRESS DAO-DAZ FIGURE 2. ICM7228AIB SEQUENTIAL 8 DIGIT RAM UPDATE ~--IWL=~1::4 --f:!.- I DATA ~ VAUD ~~ ,.~", _ _ _",_".j!DS;;' VAUDDATA ~ FIGURE 3. ICM7228C1D WRITE CYCLE --1 L 1-I320~TYP. 1C1jlaTYP. I . - FREE RUNNING FREE RUNNING (PER DIGIT) INTERDIGITBLANKING ,..., __ ,..., __ ,..., ._ ,..., __ ,..., __ ,..., __ ,..., __ ,..., __ INTERNAL SIGNAL ~~ ~5-I ....~ ~~ ...~ ....~ 1oooi5-1 ~~ r- :-Il ll m_~ ________I_~ __R_~DI~~~B~LA~N~K1~N~G-------------------------- 07 ______________ TYPICAL DIGITS OUTPUT PULSES D8 ~~~ ___________________ - ------------------------~, D6 ______________________ _________ .~------------------ ~I1~ 04 _____________________________ r-1~ oo ____________________________________ FIGURE 4. DISPLAY DIGITS MULTIPLEX (COMMON ANODE; DISPLAy) 12·25 ____ ~~ ICM7228 Typical Performance Curves .fi"c ....... fo, 0 / +25"<: ........ f,,//II +125"C ........ 100 '.J 1'fI !I'I b-- +125"C r- 300 4.0 '0 " 20 -65°C 3.0 2.0 o o 1.0 11'..1.: ,I." o i I'""" , 2.0 1.0 +25OC ,. V /' V //V 40 500 --- ~ 60 11 400 I S.O !. ~ ~/, Jf. cE C +25"c- -5SOC 80 200 II. +125OC 3.0 VDlTVDIG(V) 4.0 r-- - 5.0 VseG(V) FIGURE 5. COMMON ANODE DIGIT DRIVER IoiG VI (VOO - VDla> FIGURE 6. COMMON ANODE SEGMENT DRIVER IseG VI VSEG ° .....- +25"c o -55 C ....... ~ IIf2""I // [':..1 10 +125"C ~ 20 'f' V -5SOC200 /- 100 o lhi .....: :::;.........: ~~ o 1.0 2.0 1/ +25oC --- +l25"f- I 3.0 4.0 30 V - j 40 ~ ~ - i so I 5.0 5.0 4.0 3.0 2.0 1.0 o VDlTVSEG (V) VDlGM FIGURE 7. COMMON CATHODE DIGIT DRIVER IDiG VI VDIG FIGURE 8. COMMON CATHODE SEGMENT DRIVER ISEG VI (Voo- Vsea> 12-26 ICM7228 TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME DESCRIPTION FUNCTION 1 SEGc OUtput 2 SEGe 3 SEGb 4 DP 5 106, (HEXAICODE B) Input When "MODE" Low: Display Data Input, Bil 7. When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 105, (DECODE) input When "MODE" Low: Display Data Input, Bit 6. When "MODE" High: Control Bit, DecodelNo Decode Selection: High, No Decode; Low, Decode. 7 107, (DATA COMiNG) Input When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data. When "MODE" High: Controi Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. 8 WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control RegIster; Low, Loads Display RAM. 10 104, (SHUTDOWN) Input When "MODE" Low: Display Data Input, Bit 5. When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. 11 101 Input When "MODE" Low: Display Data Input, Bit 2. When "MODE" High and "107 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update Mode. 12 100 Input When "MODE" Low: Dispiay Data Input, Bit 1. When "MODE" High and "107 (DATA COMING)" Low: Digit Address. LSB, Single Digit Update Mode. 13 102 Input When "MODE" Low: Display Data Input, Bit 3. When "MODE" High and '07 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update Mode. 14 103 Input When "MODE" Low: Display Data Input, Bit 4. When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM BankB 15 DIGITI 16 DIGIT 2 17 DIGIT 5 18 DIGIT 8 Output LED Display Segments c, e, b and Decimal Point Drive Unes. LED Display Digits I, 2, 5 and 8 Drive Unes. s~ a.,W (/)~ -a:: CICI 19 Voo Supply Device PosItive Power Supply Rail. 20 DIGIT 4 Output LED Display Digits 4, 7, 8 and 3 Drive Unes. Output LED Display Segments f, d, g and a Drive Unes. Supply Device Ground or Negative Power Supply Rail. 21 DIGIT 7 22 DIGIT 6 23 DIGIT 3 24 SEGf 25 SEGd 26 SEGg 27 SEGa 28 Vss 12-27 ICM7228 TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME DESCRIPTION FUNCTION 1 DIGIT 4 2 DIGIT 6 3 DIGIT 3 4 DIGIT 1 5 106, (HEXAICODE B) Input When "MODE" Low: Display Data Input, Bit 7. When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 IDS, (DECODE) Input When "MODE" Low: Display Data Input, Bit 6. When "MODE" High: Control Bit, DecodeINo Decode Selection: High, No Decode; Low, Decode. 7 107, (DATA COMING) Input When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data. When "MODE" High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No Data Coming. 8 WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge 01 WRITE. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. 10 104, (SHUTDOWN) Input When "MODE" Low: Display Data Input, Bit 5. When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low, Oscillator and Display Disabled. 11 101 Input When "MODE" Low: Display Data Input, Bit 2. When "MODE" High and "107 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update Mode. 12 IDO Input When "MODE" Low: Display Data Input, Bit 1. When "MODE" High and "107 (DATA COMING)" Low: Digit Address, LSB, Single Digit Update Mode. 13 102 Input When "MODE" Low: Display Data Input, Bit 3. When "MODE" High and '07 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update Mode. 14 103 Input When "MODE" Low: Display Data Input, Bit 4. When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM BankB. OUtput LED Display Decimal Point and Segments a. b, and d Drive Lines 15 DP 16 SEGa 17 SEGb 18 SEGd OUtput LED Display Digits 4, 6, 3 and 1 Drive Unes. 19 Voo Supply Device Positive Power Supply Rail. 20 SEGc Output LED Display Segments c, e, 1and g Drive Lines. 21 SEGa Output LED Display Digits 8, 2, 5 and 7 Drive Lines. Supply Device Ground or Negative Power Supply Rail. 22 SEGt 23 SEGg 24 DIGIT 8 25 DIGIT 2 26 DIGITS 27 DIGIT 7 28 Vss 12·28 ICM7228 TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME DESCRIPTION FUNCTION 1 SEGc 2 SEGe 3 SEGb 4 DP 5 DAO Input Digit Address Input, Bit 1 LSB. 6 DA1 Input Digit Address Input, Bit 2. 7 107, (INPUTDi5) Input Display Decimal Point Data Input, Negative li'ue. 8 WRITE Input Data Input Will Be Written to Display RAM on Rising Edge of WRITE. 9 HEXAICODE BI SHUTDOWN Input Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator, and Display Disabled. 10 DA2 Input Digit Address Input, Bit 3, MSB. Input Display Data Inputs. 11 101 12 100 13 102 14 103 15 DIGIT 1 Output LED Display Segments c, e, band Decimal Point Drive Lines. OUtput LED Display Digits 1, 2, 5 and 8 Drive Lines. 16 DIGIT 2 17 DIGIT 5 18 DIGIT 8 19 Voo Supply Device Positive Power Supply Rail. 20 DIGIT 4 Output LED Display Digits 4, 7, 6 and 3 Drive Lines. 21 DIGIT7 22 DIGIT 6 23 DIGIT 3 24 SEGf 25 SEGd 26 SEGg 27 SEGa 28 Vss ~~ Q.W CI)~ Output LED Display Segments f, d, g and a Drive Lines. Supply Device Ground or Negative Power Supply Rail. 12-29 -II: 00 ICM7228 TABLE 4. ICM7228D PIN ASSIGNMENTS AND DESCRIPTIONS PIN NO. NAME 1 DIGIT 4 2 DIGIT 6 3 DIGIT 3 FUNCTION Output DESCRIPTION LED Display Digits 4, 6, 3 aIld 1 Drive Lines. 4 DIGIT 1 5 DAO Input Digit Address Input, Bit 1 LSB. 6 DA1 Input Digit Address Input, Bit 2. 7 107, (INPUT DP) Input Display Decimal Point Data Input, Negative True. 8 WRITE Input Data Input Will Be Written to Display RAM on Rising Edge 01 WRITE. 9 HEXAICODE BI SHUTDOWN Input Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator and Display Disabled. 10 DA2 Input Digit Address Input, Bit 3, MSB. 11 101 Input Display Data Inputs. 12 IDO 13 102 14 103 15 DP 16 SEGa 17 SEGb 18 SEGd 19 Output LED Display Decimal Point and Segments a, b, and d Drive Lines. Voo Supply Device Positive Power Supply RaIl. 20 SEGc Output LED Display Segments c, e, 1 and g Drive Lines. 21 SEGe 22 SEGI 23 SEGg 24 DIGIT 8 Output LED Display Digits 8, 2, 5 and 7 Drive Lines. 25 DIGIT 2 26 DIGIT 5 27 DIGIT 7 28 Vss Supply Device Ground or Negative Power Supply Rail. 12-30 ICM7228 Detailed Description independent of selected bank, a turned on decimal point will remain on for either bank. Selection of the RAM banks is controlled by 103 input. The 103 logic level (during Control Register update) selects which bank of the internal RAM to be written to and/or displayed. System Interfacing and Data Entry Modes, ICM7228A and ICM7228B The ICM7228AIB devices are compatible with the architectures of most microprocessor systems. Their fast switching characteristics makes it possible to access them as a memory mapped device with no wait state necessary in most microcontroller systems. All the ICM7228AIB inputs, including MODE, feature a 25011s minimum setup and Ons hold time with a 200ns minimum WRiTE pulse. Input logic levels are TIL and CMOS compatible. Figure 9 shows a generic method of driving the ICM722aAIB from a microprocessor bus. To the microprocessor, each device appears to be 2 separate I/O locations; the Control Register and the Display RAM. Selection between the two is accomplished by the MODE input driven by address line AO. Input data is placed on the 100 - 107 lines. The WRiTE input acts as both a device select and write cycle timing pulse. See Figure 1 and Switching Specifications Table for write cycle timing parameters. Control Register Update without RAM Update The Control Register can be updated without changing the display data by a single pulse on the WRi'fE input, with MODE high and DATA COMING low. If the display is being decoded (Hex/Code B), then the value of 103 determines which RAM bank will be selected and displayed for all eight digits. va Sequential 8 Digit Update The logic state of DATA COMING (107) is also latched during a Control Register update. If the latched value of DATA COMING (107) is high, the display becomes blanked and a sequential 8 digit update is initiated. Display data can now be written into RAM with a successive WRITE pulses, starting with digit 1 and ending with digit 8 (See Figure 2). After all 8 RAM locations have been written to, the display turns on again and the new data is displayed. Additional write pulses are ignored until a new Control Register update is performed. All 8 digits are displayed in the format (Hex/Code B or No Decode) specified by the control word that preceded the 8 digit update. If a decoding scheme (Hex/Code B) is to be used, the value of 103 during the control word update determines which RAM bank will be written to. The ICM7228AIB have three data entry modes: Control Register update without RAM update, sequential 8 digit update and single digit update. In all three modes a control word is first written by pulSing the WRii'E input while the MODE input is high, thereby latching data into the Control Register. The logic level of individual bits in the Control Register select Shutdown, DecodeINo Decode, Hex/Code B, RAM bank AlB and Display RAM digit address as shown in Tables 1 and 2. Single Digit Update The ICM7228AIB Display RAM is divided into 2 banks, called bank A and B. When using the Hexadecimal or code B display modes, these RAM banks can be selected separately. This allows two separate sets of display data to be stored and displayed alternately. Notice that the RAM bank selection is not possible in No-Decode mode, this is because the display data in the No-Decode mode has a-bits, but in Decoded schemes (Hex/Code B) is only 4-bits (100 - 103 data). It should also be mentioned that the decimal point is In this mode each digit data in the display RAM can be updated individually without changing the other display data. First, with MODE input high, a control word is written to the Control Register carrying the following information; DATA COMING (107) low, the desired display format data on 104 106, the RAM bank selected by 103 (if decoding is selected) and the address of the digit to be updated on data lines 100 102 (See Table 5). A second write to the ICM7228A1B, this time with MODE input low, transfers the data at the 100 - 107 -~ " k ~ Iii ti II: 0 VOOR MEMORY WRITE PULSE 100 y DECODER ENABLE g II: Go DEVICE SELECT AND WRITE PULSE ADDRESS DECODER ~ (J :iii rI-- . 107 HARRIS ICM7228AIB til til - " V DATA BUS 00-07 ~ 1'1. WRi'i'E SEGMENTS DRIVE MODE LED DISPLAY k ----v' DIGITS DRIVE A15 ,/ ..... ~ ADDRESS BUS AO· A15 FIGURE 9. ICM7228AIB MICROPROCESSOR SYSTEM INTERFACING 12-31 ti·····------Q 11 -----------1 1 ~. ~. it ICM7228 inputs into the selected digit's RAM location. In single digit update mode, each Individual. digit's data can be specified independently for being displayed in Decoded or No-Decode mode. For those digits which decoding scheme (Hex/Code B) is selected, only one can be effective at a time. Whenever a control word is written, the specified decoding scheme will be applied to all those digits which selected to be displayed in Decoded mode. TABLE 5. DIGITS ADDRESS, ICM7228AIB INPUT DATA LINES 102 102 100 SELECTED DIGIT 0 0 0 0 0 0 0 OIGIT1 1 0lGIT2 1 be written is placed on lines 100 - 103 and 107, then a low pulse on WRITE input will transfer the data in. See Figure 3 and Switching Characteristics Table for write cycle timing parameters. The ICM7228C1D devices do not have any control register, and also they do not provide the No Decode display format. Hexadecimal or Code B character selection and shutdown mode are directly controlled through the three level input at Pin 9, which is accordingly called HEXNCODE BI SHUTDOWN. See Tables 3 and 4 for input and output definitions of the ICM7228C/0 devices. Display Formets 1 0 1 1 0lGIT4 0 DIGITS 1 0 0 1 0lGIT6 1 1 0 OIGIT7 1 1 1 OIGIT8 The ICM7228A and ICM7228B have three possible display formats; Hexadecimal, Code B and No Decode. Table 6 shows the character sets for the decode modes and their corresponding input code. OIGIT3 The display formats of the ICM7228A1B are selected by writing data to bits 104, 105 and 106 of the Control Register (See Table 1 and 2 for input Definitions). Hexadecimal and Code B data is entered via 100-103 and 107 controls the decimal point. System Interfacing. ICM7228C and ICM7228D The ICM7228CID devices are directly compatible with the architecture of most microprocessor systems. Their fast switching characteristics make it possible to access them as a memory mapped 1/0 device with no wait state necessary in most microcontroller systems. All the ICM7228CID inputs, excluding HEXNCODE B/SHUTDOWN, feature a 250ns minimum setup and Ons hold time with a 20Qns minimum WRii'E pulse. Input logic levels are TIL and CMOS compatible. Figure 10 shows a generic method of driving the ICM7228CID from a microprocessor bus. To the microprocessor, the 8 bytes of the Display RAM appear to be 8 separate I/O locations. Loading the ICM7228C/0 is quite similar to a standard memory write cycle. The address of the digit to be updated is placed on lines OAO - OA2, the data to -K TABLE 6. DISPLAY CHARACTER SETS INPUT DATA CODE 102 101 100 HEXADECIMAL CODEB 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 2 2 0 0 1 1 3 3 0 1 0 0 4 4 0 1 0 1 5 5 .A DATA BUS DO - 07 'I Jt DISPLAY CHARACTERS 103 " y J\ V 100-103 ANDID7 ::I! I!! ~ 511/1 a: HARRIS ICM7228CJD 110 OR MEMORY WRITE PULSE DECODER ENABLE w 0 0 a: ~ a: DEVICE SELECT AND WRITE PULSE ADDRESS DECODER ~ ..... A3-A15 ) - - I y p Wiiii'E SEGMENTS DRIVE LED DISPLAY ::::) 1O·----------D 1-----------1 1 ~. ~.- DIGITS DRIVE ..... ADDRESS BUS AO - A15 y FIGURE 10. ICM7228C/D MICROPROCESSOR SYSTEM INTERFACING 12-32 ~. 5J ICM7228 TABLE 6. DISPLAY CHARACTER SETS (Continued) INPUT DATA CODE The ICM7228AIB is shutdown by writing a control word with Shutdown (104) low. The ICM7228C/0 is put into shutdown mode by driving pin 9, HEXNCOOE B/SHUTOOWN, low. DISPLAY CHARACTERS 103 102 101 100 HEXADECIMAL CODEB 0 1 1 0 6 6 0 1 1 1 7 7 1 0 0 0 8 8 1 0 0 1 9 9 1 0 1 0 A . 1 0 1 1 b E 1 1 0 0 C H 1 1 0 1 d L 1 1 1 0 E P 1 1 1 1 F (Blank) The ICM7228 operating current with the display blanked is within 1001lA - 2001lA for all versions. All versions of the ICM7228 can be blanked by writing Hex FF to all digits and selecting Code B format. The ICM7228A and ICM7228B can also be blanked by selecting No Decode mode and writing Hex 80 to all digits (See Tables 6 and 7). Common Anode ICM7228C FIGURE 10. DIGITS SEGMENT ASSIGNMENTS TABLE 7. NO DECODE SEGMENT LOCATIONS 107 Controlled Segment Decimal Point 106 105 104 103 102 101 a b c e g f Drivers, ICM7228A and The common anode digit and segment driver output schematics are shown in Figure 12. The common anode digit driver output impedance is approximately 40. This provides a nearly constant voltage to the display digits. Each digit has a minimum of 200mA drive capability. The N-channel segment driver's output impedance of 500 limits the segment current to approximately 25m A peak current per segment. Both the segment and digit outputs can directly drive the display, current limiting resistors are not required. The No Decode mode of the ICM7228A and ICM7228B allows the direct segment-by-segment control of all 64 segments driven by the device. In the No Decode mode, the input data directly control the outputs as shown in Table 7. DATA INPUT Display 100 d An input high level turns on the respective segment, except for the decimal point, which is turned on by an input low level on 107. The No Decode mode can be used in different applications such as bar graph or status panel driving where each segment controls an individual LED. The ICM7228C and ICM72280 have only the Hexadecimal and Code B character sets. The HEXNCOOE B/ SHUTDOWN input, pin 9, requires a three level input. Pin 9 selects the Hexadecimal format when pulled high, the Code B format when floating or driven to mid-supply, and the shutdown mode when pulled low (See Tables 3 and 4). Table 6 also applies to the ICM7228CID devices. Shutdown and Display Banking When shutdown, the ICM7228 enters a low power standby mode typically consuming only 11-1A of supply current for the ICM7228AIB and 2.5\lA for the ICM7228CID. In this mode the ICM7228 turns off the multiplex scan oscillator as well as .the digit and segment drivers. However, input data can still be entered when in the shutdown mode. Data is retained in memory even with the supply voltage as low as 2V. Individual segment current is not Significantly affected by whether other segments are on or off. This is because the segment driver output impedance Is much higher than that of the dign driver. This feature is important in bar graph applications where each bar graph element should have the same brightness, independent of the number of elements being turned on. Common Cathode Display Drivers, ICM72288 and ICM7228D The common cathode digit and segment driver output schematics are shown in Figure 13. The N-channel digit drivers have an output impedance of approximately 150. Each digit has a minimum of SOmA drive capability. The segment drivers have an output impedance of approximately 1000 with typically 10mA peak current drive for each segment. The common cathode display driver output currents are only '/4 of the common anode display driver currents. Therefore, the ICM7228A and ICM7228C common anode display drivers are recommended for those applications where high display brightness is desired. The ICM7228B and ICM72280 common cathode display drivers are suitable for driving bubblelensed monolithic 7 segment displays. They can also drive individual LED displays up to 0.3 inches in height when high brightness is not required. Display Multiplexing Each digit of the ICM7228 is on for approximately 320l-1s, with a multiplexing frequency of approximately 390Hz. The ICM7228 display drivers provide interdigit blanking. This ensures that the segment information of the previous digit is gone and the information of the next digit is stable before the next digit is driven on. This is necessary to eliminate display ghosting (a faint display of data from previous digit superimposed on the next digit). The interdigit blanking time is 10j.1S typical with a guaranteed 2j.1S minimum. The ICM7228 turns off both the digit drivers and the segment drivers during the interdigit blanking period. The digit multiplexing sequence is: 02, OS, 01, 07, 08, 06, 04 and 03. A typical digit's drive pulses are shown on Figure 4. 12-33 ICM7228 Due to the display multiplexing, the driving duty Cycle for each digit is 12% (100 x 1/e) This means the average current for each segment is 1fe of Its peak current. This must be considered while designing and selecting the displays. SEGMENT DATA 00200mA INTERDIGIT Driving Larger Displays BI:ANKINQ 1000 If very high display brightness is desired, the ICM7228 display driver outputs can be externally buffered. Figures 14 thru 16 show how to drive either common anode or common cathode displays using the ICM7228 and external driver circuit for higher current displays. Another method of increasing display currents is to connect two digit outputs together and load the same data Into both digits. This drives the display with the same peak current, but the average current doubles because each digit of the display is on for twice as long. i.e.• 1/4 duty cycle versus 1/e. Voo t--"fv-- COMMON CATHODE SEGMENT OUTPUT SHUTDOWN _ ............................-11 Vas NOTE: When SHuTDOwN goes low INTERDIGIT BLANKING also smyslow. FIGURE 138. SEGMENT DRIVER FIGURE 13. COMMON CATHODE DISPLAY DRIVERS DIGIT STROBE 00200mA INTERDIGIT Voo BLANKiNG , :•• COMMON ANODE DIGIT OUTPUT • DIGIT: OUTPUT : ICM7228AIB SHUTDOWN--....................................-il~ NOTE: When SHUTDOWN goes low INTERDIGIT BlANKING also smyslow. FIGURE 12A. DIGIT DRIVER Vas Vas FIGURE 14. DRIVING HIGH CURRENT DISPLAY, COMMON ANODE ICM7228A1C TO COMMON ANODE DISPLAY SEGMENT DATA COMMON ~ODE INTERDIGrr BLANKING SEGMENT OUTPUT SHutDOWN ............--l Vas FIGURE 128. SEGMENT DRIVER FIGURE 12. COMMON ANODE DISPLAY DRIVERS DIGIT STROBE COMMON CATHODE DIGIT OUTPUT iNTERDidlt BLANKiNG SHutDOWN ...._ _- 1 13A. DIGIT DRIVER FIGURE 15. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228BID TO COMMON CATHODE DISPLAY 12-34 ICM7228 74C126 TRI-5TATE BUFFER >------ HIGH. HEX LOW .. SHUTDOWN PINII HIGH .. HEX OR SHUTDOWN LOW.CODEB CD4016 CD4066 t------ HIGH "HEX LOW. SHUTDOWN PIN II HIGH .. HEX OR SHUTDOWN LOW.CODEB HIGH .. CODEB (100mA PEAK) PINg LOW. HEX 1N4148 HIGH .. SHUTDOWN 1II1II LOW.CODEB VM VM HIGH .. SHUTDOWN LOW. HEX FIGURE 16. DRIVING HIGH CURRENT DISPLAY, COMMON CATHODE ICM7228B1D TO COMMON CATHODE DISPLAY HIGH .. SHUTDOWN LOW.CODEB Three Level Input, ICM7228C and ICM7228D As mentioned before, pin 9 is a three level input and controls three functions: Hexadecimal display decoding, Code B display decoding and shutdown mode. In many applications, pin 9 will be left open or permanently wired to one state. When pin 9 can not be permanently left in one state, the circuits illustrated in Figure 17 can be used to drive this three level input. [:>~D4069 PINg OPEN DRAIN OR OPEN COLLECTOR OUTPUT [::> - PINe -0 FIGURE 17. ICM7228CJD PIN 9 DRIVE CIRCUITS Power Supply Bypassing Connect a minimum of 471lF in parallel with 0.1!1F capacitors between VDD and Vss of ICM7228. These capacitors should be placed in close proximity to the device to reduce the power supply ripple caused by the multiplexed LED display drive current pulses. ' Test Circuits 4 ~J- ~ ~ '25t ~ 106 (HEXAICODE B) ~ 5 E: ~ IDS (DECODE) ::; 107 (DATA COMING) '231 E: ~ 7 WRITE ::; ~ '2;1 ICM7229A 8 E MODE ::; g ID4 (SHUTDOWN) ~ 20 ~j- ~ 101 100 ~!- r- f- :!! ,~ VDD :t Y Y Y Y Y Y Y Y Y Y 5V -Vss 17 tw 13 ~ IDr-ffi 14 t= 'is' i=' Veo I 47~~+ J1F +0.1 fd- I VM [ COMMON ANODE DISPLAY PINe 0 6 rr-~ gaD2 01 C IB. B.iB. B.iB.iB.IB.1B.1o: FIGURE 18. FUNCTIONAL TEST CIRCUIT.l 12-35 8 ICM7228 Test Circuits (CcInUnued) ~ ~ " ~ ~ 7 28 7 IIIGI1' ADDRESS 0 7 ~ ~ 23 IIIGI1' ADDRESS 1 ~ 1D7(D.P.) ~ WIll! :;: IIEXNCODI! ItISIIVTOOWR r;:• DIGIT ADDRESS 2 Voo -y + SV . Vas ,,, f22i E: E: 1CM7228D ~ == t~ 1D1~ IDO~2 ~-J!!.li ~ ~ E! ~ t t t t t t tw-Voo 47~:~ +0.1 .... V.. Lg -f '---a "'---- c d b • D8 DB OS D4 D3 D2 D1 IB.IB.IB.IB.IB.IB.IB. ~I DP FIGURE 19. FUNCTIONAL TEST CIRCUIT 12 12·36 D7 COMMON ANODE DISPLAY ICM7231,ICM7232 Numeric/Alphanumeric Triplexed LCD Display Driver December 1993 Features Description • ICM7231 Drives 8 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input In Perallel Format The ICM7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching waveforms required to drive triplexed liquid-crystal displays. These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. • ICM7232 Drives 10 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input In Serial Format • All Signal8 Required to Drive Rows and Columns of Trlplexed LCD DIsplay are Provided • DIsplay Voltage Independent of Power Supply • On-Chlp Oscl/Jator ProvIdes All DIsplay TImIng The family is designed to interface to modern high performance microprocessors and microcomputers and ease system requirements for ROM space and CPU time needed to service a display. • Total Power ConsumptIon lYplcally 200I1W. MaxImum SOOI1Wat SV • Low·Power Shutdown Mode RetaIns Data WIth SI1W lYplcal Power ConsumptIon at SV. 111W at 2V • DIrect Interface to Hlgh·Speed Microprocessors Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE NUMBER OF DIGITS INPUT FORMAT ICM7231 BFIJL -25°C to +85°C 40 Lead Ceramic DIP 8DlgII Parallel ICM7231 BFIPL -25°C to +85°C 40 Lead Plastic DIP 8 Digit Parallel ICM7232 AFIJL -2SOC to +85°C 40 Lead Ceramic DIP 10 Digit Serial ICM7232BFIPL -25°C to +85°C 40 Lead Plastic DIP 10 Digit Serial ICM7232CRIPL -25°C to +85°C 40 Lead Plastic DIP 10 Digit Serial NOTE: All versions intended for trlplaxed LCD displays. CAUTION: These devices are sensblve to electrostatic discharge. Users should follow proper I.C. Hsndling Procedures. Copyright@Harris Corporation 1993 12-37 File Number 3161 ICM7231, ICM7232 Pinouts ICM7231BF Cs ICM7232AF, BF (PDIP) (PDIP) TOP VIEW TOP VIEW DATA CLOCK INPUT VOCSP Veo VOCSP A2 BPl Al BP1 BP2 AO BP2 Vss BP3 bl, C1, anl1 BDS .....l---" r----,I-- BP3 b1, C1, an11 a1,g1, dl BD2 a1, g1, d1 ft, 81, an21 BD1 ft, 81, an21 a b2, C2,an12 BOO II 82, g2, d2 AN2 b2, C2, an12 a2, g2, d2 f2,82,an22 AN1 b3, d, an13 fa, aa,an28 83, g3, d3 12,82, an22 b3,d, an13 aa, ga,dl f3, 83, an23 ba,cI,anl' a3, g3, d3 13,83, an23 b4, C4, an14 fT,87, an27 b4, C4, an14 84, g4, d4 f4, 84, an24 bs, CS, anlS as, g5, ds f5, 116, an25 a7, g7,d7 b7,c7,an17 84, g4, d4 f4, 84, an24 b5, CS, ant5 fI, 86, an26 a6, g6, d6 as, gs, dS b6, c6,an16 f5,II6, an25 --.. _ _ _ _ _..r- ICM7232CR (PDIP) TOP VIEW DATA CLOCK INPUT VDlSP Veo WRiTE INPUT 2 DATA INPUT DATA ACCEPTED OUTPUT BP1 BP2 Vss BP3 bl,C1,ant1 b6, C6, an16 a1, g1, d1 86, g6, ds ft, 81, an21 b2, C2, an12 fI, 86, an26 II b7, C7, an17 82,g2,d2 a7, g7, d7 12,82,an22 fT, 87, an27 b3, C3,an13 ba, ca, an18 aa, ge, de a3, g3, d3 f3, 83, an23 fe,al, an2e be, cII,anll1 b4, C4,an14 a4,g4, d4 ae,ge,dll f4,84,an24 fe, ell, an28 b5, C5,an15 bl0, C10, an110 a5,gs,d5 a10, g10, d10 f5,85, an25 --.._ _ _ _ _..r- fto, 810, an210 12-38 ICAl7231,ICAl7232 Functional Block Diagrams ICM7231 DB rYI DB D5 D4 - - .i9.\i. - - I,i dli.3 D3 D2 D1 i~E .~~ i&!~ .tlili Voo VH ON CHIP DISPLAY VL VOLTAGE LEVEL GENERATOR VDlSP ",-+--11-- PIN 2 (INPUT) BP1 L~=~=1 COMMON UNE BPZ DRIVERS BP3 DlSPl.AY TIMING GENERATOR AN1 BDO .. BD2 DATA INPUTS ADDRESS INPUTS NOTE: See FIgure 13 for display segment connections 12-39 ICM7231, ICM7232 Functional Block Diagrams (Continued) ICM7232 D10 '-- D8 D7 D8 D6 D4 Da Voo ON CHIP VH DISPLAY VOLTAGE LEVEL VL GENERATOR VOISP +++-+-PIN 2 (INPUT) BP1 L._ DIGIT ADDRESS DECODER DATA DECODER , : : : , AN1:,AN2:,BOO:, BDt:,BDa: BDa . AO A1 A2 ENt------. A3 ~_M_/ CLOCK DATA DATA DATA . Wiiii'E DATA INPUT CLOCK INPUT ACCEPTED INPUT OUTPUT SHIFTS RIGHT TO LEFT ON RISING EDGE OF DATA CLOCK NOTE: See Figures 13 and 14 for display segment connectlons. 12-40 ........... COMMON UNE DRIVERS BPa _ _ _.. BP3 DISPLAY TIMING GENERATOR Specifications ICM7231, ICM7232 Absolute Maximum Ratings Thennallntonnatlon Supply Voltage (VOO - Vss) ••••••••••••••••••••• ' •••••••• 6.5V Input Voltage (Note 1)•••••••••••••••••.•• Vss - 0.3 S VIN S 6.5 Display Voltage (Note 1) .................... 0.3 S VOISPS +0.3 Storage Temperature Range ••••••••••••••••• -65"C to + l5O"C Lead Temperature (Soldering, 10s) • • • • . . • . • • • . . • • • • . • +3OO"C Thermal Resistance 8~ 8,IC Plastic DIP Package .. .. .. .. .. .. .. .. EI.1'CIW CeramIc DIP Package .. .. .. .. .. .. .. • 45"CIW 1S"CJW Operating Temperatura Range ••........ -25"C to -t86"C Junction Temperat\I'e CeramIc ....................................... +175"C PIestIc ........................................ +15O"C CAUTION: SIr8ss8s abo... Ihose /isltKf In "Abso/uIB MaJlimum Ratings" may C8USB piNI1I8IIBfIt damet1e ID the ....... .". lila .".. only tatlng and OI»/atlon of the 4 5.5 V 2 1.6 - V 30 100 IlA 10 IlA UNITS Shutdown Total Current, Is VOISP Pin 2 Open - Display Voltage Range, VOISP VSSSVOISPSVOO 0 Display Voltage Setup Current, IOISP VOISP = 2V, Current from Voo to VDlSP On-Chlp - 15 40 75 - - '/4 1 % (VOO - VOISP) 60 90 120 Hz - - 0.8 V 100 Display Voltage Setup Resistor Value, ROISP One of Three Identical Resistors In StrIng DC Component of Display Signals (Sample Test Only) Display Frame Rate, folSP See Figure 5 Input Low Level, Vil ICM7231, PIllS 30 - 35, 37 - 39, 1 ICM7232, PillS I, 38, 39 (Note 3) Input High Level, VIH 1 2.0 - Input Leakage, IILK Pin 37,1CM7232,lol -lmA. Output High Level, VOH Voo = 4·5V,IoH Operating Temperature Range, Top Industrial Range =-5001lA V 30 IlA V 1 IlA - 5 4.1 -25 - kn - 0.1 - Input CapaCitance, CIN Output Low Level, VOL Voo 0.4 pF V - V +85 °C AC Specifications Voo=5V + 10% Vss= OV, -25"CSTA S+85"C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 350 - lIS PARALLEL INPUT (ICM7231) See Figure 1 Chip Select Pulse Width, Ics (Note 2) 500 Address/Data Setup Time, los (Note 2) 200 - Address/Data Hold Time, IoH (Note 2) 0 -20 Inter-Chlp Select Time, tiCS (Note 2) 3 - Data Clock Low Time, ta: (Note 2) 350 - Data Clock High Time, !cl (Note 2) 350 Data Setup Time, los (Note 2) 200 - Data Hold Time, IoH (Note 2) 0 -20 Write Pulse Width, twP (Note 2) 500 350 Write Pulse to Clock at Initialization, tWLL (Note 2) 1.5 Data Accepted Low Output Delay,tool (Note 2) Data Accepted High Output DelaY,looH (Note 2) Write Delay After Lest Clock, !cws (Note 2) - ns lIS jIS SERIAL INPUT (ICM7232) See Figures 2, 3 12-41 350 - - 200 400 lIS 1.5 3 jIS - - lIS - lIS ns ns lIS ns jIS Specifications ICM7231, ICM7232 Table of Features TYPE NuMBER ANNUNC~TORLOCATIONS OUTPUT CODE INPUT OUTPUT CodeB Both Annunciators on BP3 Perallel Entry, 4-bit Data, 2-bit 8 Digits plus Annunciators, 3-bit Address 16 Annunciators ICM7232AF Hexadecimal Both Annunciators on BP3 ICM7232BF CodeB Serial Entry, 4-bn Data, 2-blt Annunciators, 4-blt Address ICM7232CR CodeB ICM7231BF 10 Digits plus 20 Annunciators 1 Annunciator BPI 1 Annunciator BP3 Terminal Definitions TERMINAL I PIN NO. FUNCTION DESCRIPTION ICM7231 PARALLEL INPUT NUMERIC DISPLAY ANI 30 Annunciator 1 Control Bit High AN2 31 Annunciator 2 Control Bit Low BOO 32 Least Significant BDI 33 BD2 34 BD3 35 Most SignifICant AO 37 Least Significant AI 38 A2. 39 CS 1 I 4-blt Binary Data Inputs } 3-bit Digit Address Inputs Most Significant Data Input Strobe/Chip Select (Note 3) =ON =OFF Input Data (See Table 1) See Table 3 = = HIGH logical One (1) LOW Logical Zero (0) Input Address (See Table 2) Trailing (PosWve going) edge latches data, causes data input to be decoded and sent out to addressed digit ICM7232 SERIAL DATA AND ADDRESS INPUT = = Data Input 38 Data+ Address ShHt Register Input HIGH Logical One (1) LOW Logical Zero (0) WRITE Input 39 Decode, Output, and Reset Strobe When DATA ACCEPTED Output is LOW, posjijve going edQ8 of WRITE causes data in shift register to be decoded and sent to addressed digit, then shift register and conlrollogic to be~When DATA ACCEPTED OUtput is HIGH, positive going edge of WRITE triggers reset only. Data Clock Input 1 Data Shift Register and Control Logic Clock Positive gOing edge advances data In shift register. ICM7232: Eleventh edge resets shift register and control logic. DATA ACCEPTED Output 37 Handshake Output Output LOW when correct number of bits entered into shift register. 2 Negative end of on-chip resistor string Display voltage control. When open (or less than tv from Voo) chip used to generate intermediate voltage lev- is shutdown; oscillator stops, all display pins to VODels for display. Shutdown Input. ALL DEVICES Display Voltage V01SP Common Line Driver Outputs 3,4,5 Segment Line Driver Outputs 6-29 6-35 Voo 40 Drive display commons, or rows (On ICM7231) (On ICM7232) Drive display segments, or columns. Chip Positive Supply Chip Negative Supply 36 Vss NOTE: 1. Due to the SCR structure Inherent In these devices, connecting any display terminal or the display voltage terminal toa voltage outside the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than -0.3V below ground, but maybe connected to voltages above Voo but not more than 6.5V above Vss. 2. For Design reference only, not 100% tested. 3. CS has a special "mid-level" sense circuit that establishes a test mode if it is held near 3V for several ms. Inadvertent triggering of this mode can be avoided by pulling it high When inactive, or ensuring frequent activity 12-42 ICAf7231,ICAf7232 Timing Diagrams DATA ADDRESS INPUT DO NOT CARE ~~Imm; FIGURE 1. ICM7231 INPUT TIMING DIAGRAM ELEVENTH CLOCK WITH NO Wiii'E PULSE RESETS SR + LOGIC DATA CLOCK INPUT (PER BIT OF DATA) ---,1(;1) DATA---~-~---------~:~--~ ACCEPTED OUTPUT Wiii'E INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH DO NOT CARE IlM9I DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW FIGURE 2. ICM7232 ONE DIGIT INPUT TIMING DIAGRAM, WRITING BOTH ANNUNCIATORS 12-43 ICM7231, ICM7232 Timing Diagrams ICM7232 WRITE ORDER DATA _ _ _...,j CLOCK INPUT DATA-----+---------------"l~---------~ ACCEPTED OUTPUT Wiii'I'l INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH DONOTCARE~ DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW FIGURE 3. ICM7232 INPUT TIMING DIAGRAM, LEAVING BOTH ANNUNCIATORS OFF ICM7231 Family Description The ICM7231 drives displays with 8 seven-segment digits with two independent annunciators per digit, accepting six data bits and three digit address bits from parallel inputs controlled by a chip select input. The data bits are subdivided into four binary code bits and two annunciator control bits. The ICM7232 drives 10 seven-segment digits with two independent annunciators per digit. To write into the display, six bits of data and four bits of digit address are clocked serially into a shift register, then decoded and written to the display. Input levels are TTL compatible, and the DATA ACCEPTED output on the serial input devices will drive one LSTTL load. The intermediate voltage levels necessary to drive the display properly are generated by an on-chip resistor string, and the output of a totally self-contained on-chip oscillator is used to generate all display timing. All devices in this family have been fabricated using Harris' MAXCMOS® process and all inputs are protected against static discharge. MAXC~ Figure 5 shows the voltage waveforms of the common lines and one segment line, chosen for this example to be the "a, g, d" segment line. This line intersects with BP1 to form the "a" segment, BP2 to form the "g" segment and BP3 to form the "d" segment. Figure 5 also shows the waveform of the "a, g, d" segment line for four different ON/OFF combinations of the "a", "g" and ad" segments. Each intersection (segment or annunciator) acts as a capacitance from segment line to common line, shown schematically in Figure 6. Figure 7 shows the voltage across the Kg' segment for the same four combinations of ON/OFF segments used in Figure 5. SEGMENT UNES is a regislered lrademark of Harris Corporation. Trlplexed (113 Munlplexed) Uquld Crystal Displays Figure 4 shows the connection diagram for a typical 7-segment display with two annunciators such as would be used with an ICM7231 or ICM7232 numeric display driver. lid an2 aOl BACKPLANE CONNECTIONS SEGMENT UNE CONNECTIONS 12-44 FIGURE 4. CONNECTION DIAGRAMS FOR TYPICAL 7-SEGMENT DISPLAYS ICAf7231,ICAf7232 ,, , 1,1 1,21 ~ 1,1'1,2'1,3'1 BP1 rr::::::::;.:::r ~ lvp BP1 ::::~::::::::: ~~p BP2 BP3 IJl~~;':;~Ei ~~ -----~:~~~t1~~-- ~~ISP :an1 an2 : FIGURE 6. DISPLAY SCHEMATIC COMMON UNE WAVEFORMS -------~----------- Veo VP • (V+) • V DlSP 1,1 I~ I~ 1'1'1~'1'3'1 ,------------------------- +VP ON CHIP RESISTOR STRING BP3~----· .!!:!.- · ----------t:r-I I I I I I I :c : , I I I I I I I .•••••• ------------ 'b ,, .:, BP2 I I I I I I I :--SEGMENT : UNES f:, : AU.OFF VL • VOISP E~1"""1-··q:[ 0 =W-_LJm __ ••. _.•••••. _•..•• __ ..... ·vp .------------------------ VDD SEGMENT UNE] ALL OFF ----------_ . rmmmr.!!:!.- = V RMS VP "3 = VRMSOFF -' VL ------------------------- VDlSP a SEGMENT I I I I I I I ·-----------n--------· -75kn PIN 2 Veo ----r------i--------·.!!:!.- ON a,dOFFI.J----------~ VL I 1---rrT-T--1 VDlSP -----------....,----- Veo a. 9 ON --------,...-a------t---dOFF , ______ -------------------------. +VP VOISP INPUT TYPICAL SEGMENTUNE WAVEFORMS . ------------------------. ·vp I I I I I i----I +VP + ____ .... ........,. VH ~ dOFF .L...J.------------.L VDlSP ALL ON II I II I I l~~~::::::~I-m------F- ---I-----t-- .. -.•..•......••.... -••• -. ·vp · •••••••• -. • -. - •• - -.. • VL • ---------- VDlSP NOTES: 1. ,1, ,2, ~, • BP High with Respect to Segment 2. 3. 4. 5. 0 +VP +1', ,2', ~', • BP Low with Respect to Segment BP1 Active during ,1, and ,1'. BP2 Active during ,2, and ,2'. BP3 Active during ,3, and ,3'. AU. ON -i----+------il- 0 ---------------- ·vp I I 1 I I FIGURE 5. DISPLAY VOLTAGE WAVEFORMS VRIotSON The degree of polarization of the liquid crystal material and thus the contrast of any intersection depends on the RMS voltage across the Intersection capacitance. Note from Figure 7 that the RMS OFF voltage is always Vpl3 and that the RMS ON voltage is always 1.92 Vpl3. For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF volt· ages is fixed at 1.92, achieving adequate display contrast with this ratio of applied RMS voltage makes some demands on the liquid crystal material used. Voltage Contrast Ratio = V OFF = RiotS J11 r.;. = 1.92 ",3 NOTES: 1. ,1, ,2, '3, . BP High with Raspecl to Segment 2. ,1', ,2', ,3', • BP Low with Respect to Segment a, BP1 Active during ,1, and ,1'. 4. BP2 Active during ,2, and ,2'. 5. BPa Active during ,a, and ,a '. FIGURE 7. VOLTAGE WAVEFORMS ON SEGMENT g(VGl 12-45 ~~ ....IW D.> cn-a: Cc ICM7231, ICM7232 FlQure 8 sha.Ns the CUM! of contrast versus applied RMS voltage for a rlquid crystal material tailored for Vp = 3.1 V, a typical value for 1/3 muftipleJGad displays in calculators. Note that the RMS OFF voltage Vp/3 - 1V is just below the "threshold" voltage YI11ere c0ntrast begins to i1crease. This places the RMS ON voltage at 2.1 V. which provides about 85% cont~ when viewed straight on. ,, A more important effect of temperature is the variation of threshold voltage. For typical liquid crystal materials suitable for multiplexing, the peak voltage has a temperature coeffICient of -7 to -14mVFC. This means that as temperature rises, the threshold voltage goes down. Assuming a fixed value for VFl when the threshold voltage drops below Vp/3 OFF segments begin to be visible. Figure 9 shows the temperature dependence of peak voltage for the same liquid crystal material of Figure 8. 6 J P~AK ~OL~AGEI FO~ I I 5 ... 110% CONTRAST (ON) - 100 II0 9 .. -100 TA=+2S"C r 80 7ot-- ~ 6.-300"" l 60 01-- VOFF1·1VRMS 0 0 o I-- ~10 I ~VON.2.1V I PEAK VOLTAGE FOR 10% CONTRAST (OFF) I 0 I I I I 10 20 30 40 AMBIENT TEMPERATURE ("C) 50 FIGURE 9. TEMPERATURE DEPENDENCE OF LC THRESHOLD I Ij r- l"- ~'f' / ' " 6.+100 30 0 f\ I"- ~ .,.~ / rp V I: 20 ~/ .6'9.0 ~ I 1 For applications where the display temperature does not vary widely, Vp may be set at a fixed voltage chosen to make the RMS OFF voltage, Vp/3, just below the threshold voltage at the highest temperature expected. This will prevent OFF segments turning ON at high temperature (this at the cost of reduced contrast for ON segments at low temperatures). I I 123 APPUED VOLTAGE (VRMSl 4 FIGURE 8. CONTRAST va APPUED RMS VOLTAGE All members of the ICM7231 and ICM7232 family use an internal resistor string of three equal value resistors to generate the voftages used to drive the display. One end of the string is connected on the chip to Voo and the other end (user input) Is available at pin 2 (VDl5P) on each chip. This anows the display voltage input (VOI5P) to be optimized for the particular liquid crystal material used. Remember that Vp = Voo - VOl5P and should be three times the threshold voltage of the liquid crystal material used. Also it is very important that pin 2 never be driven below Vss. This can cause device latchup and destruction of the chip. Temperature Effects and Temperature Compensation The performance of the LCD material is affected by temperature in two ways. The response time of the display to changes of applied RMS voltage gets longer as the display temperature drops. At very low temperatures (-20°C) some displays may take several seconds to change a new character after the new information appears at the outputs. However, for most applications above OOC this will not be a problem with available muitiplexed LCD materials, and for low-temperature applications, high-speed liquid crystal materials are available. At high temperature, the effect to consider deals with plastic materials used to make the polarizer. For applications where the display temperature may vary to wider extremes, the display voltage VOl5P (and thus Vp) may require temperature compensation to maintain sufficient contrast without OFF segments becoming visible. Display Voltage and Temperature Compensation These circuits allow control of the display peak voltage by bringing the bottom of the voitage divider resistor string out at pin 2. The simplest means for generating a display voltage suitable to a particular display is to connect a potentiometer from pin 2 to V55 as shown in Figure 10. A potentiometer with a maximum value of 200kn should give sufficient range of adjustment to suit most displays. This method for generating display voltage should be used only in applications where the temperature of the chip and display won't vary more than ±5°C (±9°F), as the resistors on the chip have a positive temperature coefficient, which will tend to increase the display peak voitage with an increase in temperature. The display voitage also depends on the power supply voitage, leading to tighter tolerances for wider temperature ranges. Some polarizers become soft at high temperatures and permanently lose their polarizing ability, thereby seriously degrading display contrast. Some displays also use sealing materials unsuitable for high temperature use. Thus, when specifying displays the following must be kept in mind: liquid crystal material, polarizer, and seal materials. 200knf'" r "- ~ .. 10nF FIGURE 10. SIMPLE DISPLAY VOLTAGE ADJUSTMENT 12-46 ICM7231,ICM7232 Figure 11A shows another method of setting up a display voltage using five silicon diodes in series. These diodes, 1N914 or equivalent, will each have a forward drop of approximately O.65V, with approximately 20j.lA flowing through them at room temperature. Thus, 5 diodes will give 3.2SV, suitable for a 3V display using the material properties shown in Figures 4 and S. For higher voltage displays, more diodes may be added. This circuit provides reasonable temperature compensation, as each diode has a negative temperature coefficient of -2mVf'C; five in series gives -10mVI cc, not far from optimum for the material described. the ICL7663S, as shown in Figure 12. This circuit allows independent adjustment of both voltage and temperature compensation. +5V VIN+ Vour1 LOGIC SYSTEM PROCESSOR, ETC. The disadvantage of the diodes in series is that only integral multiples of the diode voltage can be achieved. The diode voltage multiplier circuit shown in Figure 11 B allows fine-tuning the display voltage by means of the potentiometer; it likewise provides temperature compensation since the temperature coefficient of the transistor base-emitter junction (about -2mVf'C) is also multipled. The transistor should have a beta of at least 100 with a collector current of 10llA The inexpensive 2N2222 shown in the figure is a suitable device. - VOI1T2 ICL7663S Voo ...J 1.IMO VSET - - < VTC ONO 1 ICM7233 ~ => 2.7MO L -=..E=" DATA BUS Voo VDlSP ONO '1 FIGURE 12. FLEXIBLE TEMPERATURE COMPENSATION Description Of Operation 1N914 DIODES 2 VDlSP ICM7231 ICM7232 40 Parallel Input Of Data And Address (ICM7231) 36 The parallel input structure of the ICM7231 device is organized to allow simple, direct interfaCing to all microprocessors, (see the Functional Block Diagram). In the ICM7231, address and data bits are written into the input latches on the rising edge of the Chip Select input. -!-10nF FIGURE 11A. STRING OF DIODES Voo 2 VDlSP 200110 POTENTIOMETER ICM7231 ICM7232 40110 40 +5 36 The rising edge of the Chip Select also triggers an on-chip pulse which enables the address decoder and latches the decoded data into the addressed digiVcharacter outputs. The timing requirements for the parallel input device are shown in Figure 1, with the values for setup, hold, and pulse width times shown in the PC Specifications section. Note that there is a minimum time between Chip Select pulses; this is to allow sufficient time for the on-chip enable pulse to decay, and ensures that new data doesn't appear at the decoder inputs before the decoded data is written to the outputs. Serial Input Of Data And Address (ICM7232) T 10nF FIGURE 11B. TRANSISTOR-MULTIPLIER FIGURE 11. DIODE-BASED TEMPERATURE COMPENSATION For battery operation, where the display voltage is generally the same as the battery voltage (usually 3 - 4.SV), the chip may be operated at the display voltage, with VolSP connected to Vss. The inputs of the chip are designed such that they may be driven above Voo without damaging the chip. This allows, for example, the chip and display to operate at a regulated 3V, and a microprocessor driving its inputs to operate with a less well controlled SV supply. (The inputs should not be driven more than 6.SV above GND under any circumstances.) This also allows temperature compensation with The ICM3232 trades six pins used as data inputs on the ICM7231 for six more segment lines, allowing two more 9segment digits. This is done at the cost of ease in interfacing, and requires that data and address information be entered serially. Refer to Functional Block Diagram and timing diagrams, Figures 2 and 3. The interface consists of four pins: DATA Input, DATA CLOCK Input, iiVFiii'E Input and DATA PCCEPTED Output. The data present at the DATA Input is clocked into a shift register on the riSing edge of the DATA CLOCK Input Signal, and when the correct number of bits has been shifted into the shift register (8 in the ICM7232), the DATA ACCEPTED Output goes low. Following this, a low-going pulse at the WRITE input will trigger the chip to decode the data and store it In the output latches of the addressed digiVcharacter. After the data is latched at the outputs, the shift register and the control logic are reset, 12-47 ICAf7231,ICAf7232 returning the DATA ACCEPTED Output high. After this occurs, a pulse at the WRii'E input will not change the outputs, but will reset the control logic and shift register, assuring that each data bit will be entered into the correct position in the shift register depending on subsequent DATA CLOCK inputs. .TABLE 1. BINARY DATA DECODING ICM7231 AND ICM7232 The shift register and control logic will also be reset if too many DATA CLOCK INPUT edges are received; this prevents incorrect data from being decoded. In the ICM7232, the eleventh clock resets the shift register and control logic. BOS 0 CODE INPUT BD2 BD1 0 0 BOO 0 0 0 0 1 The recommended procedure for entering data is shown in the serial input timing diagram, Figure 2. First, when DATA ACCEPTED is high, send a WRITE pulse. This resets the shift register and control logic and initializes the chip for the data input sequence. Next clock in the appropriate number of correct data and address bits. The DATA ACCEPTED Output may be monitored if desired, to determine when the chip Is ready to output the decoded data. When the correct number of bits has been entered, and the DATA ACCEPTED Output is low, a pulse at WRi'fE will cause the data to be decoded and stored in the latches of the addressed digiV character. The shift register and control logic are reset, causing DATA ACCEPTED to return high, and leaving the chip ready to accept data for the next digiVcharacter. 0 0 1 0 DISPLAY OUTPUT HEX CODEB II LI I I I 1-. 0 0 1 1 I II LI I I , 1-. I ~ ~ , , 0 1 0 0 LI U 0 1 0 1 I- I- Note that for the ICM7232 the eleventh clock resets the shift register and control logic, but the DATA ACCEPTED Output goes low after the eighth clock. This allows the user to abbreviate the data to eight bits, which will write the correct character to the 7-segment display, but will leave the annunciators off, as shown in Figure 3. 0 1 1 0 0 1 1 1 If only AN2 is to be turned on, nine bits are clocked in; if AN1 Is to be turned on, all ten bits are used. 1 0 0 0 The DATA ACCEPTED Output will drive one low-power Schottky TTL input, and has equal current drive capability pulling high or low. 1 0 0 1 1 0 1 0 Note that in the serial Input devices, it is possible to address digits/characters which don't exist. As shown in Table 2 when an incorrect address is applied together with a WRi'fE pulse, none of the outputs will be changed. 1 0 1 1 The standard versions of the ICM7231 and ICM7232 chips are programmed to drive a 7-segment display plus two annunciators per digit. See Table 3 for annunciator input controls. 1 1 0 0 1 1 0 1 The "C" devices place the left hand annunciator on BP1 and the right hand annunciator (usually a decimal point) on BP3. (See Figure 14). The "CO devices provide only a "Code B" output for the 7-segments. 12-48 J I- I- I I 1, a., a., II a D 0 Q 1, - 1 11- L 1-1 -, -, l1 Display Fonts and Output Codes The "A" and "B" suffix chips place both annunciators on BP3. The display connections for one digit of this display are shown in Figure 13. The "A" device~ decode the input data into a hexadecimal 7-segment output, while the "B" devices supply Code B outputs (see Table 1). .J a,- - D 1 1 1 1 1 1 0 1 I 11-. 1- ,- I L a I BLANK ICAf7231,ICAf7232 TABLE 2. ADDRESS DECODING (ICM7231 AND ICM7232), SEGMENT LINES DISPLAY OUTPUT CODE INPUT ICM7232 ONLY A3 A2 A1 AO 0 0 0 0 D1 0 0 0 1 D2 0 0 1 0 D3 0 0 1 1 D4 0 1 0 0 D5 0 1 0 1 D6 0 1 1 0 D7 0 1 1 1 D8 1 0 0 0 D9 1 0 0 1 Dl0 1 0 1 0 NONE 1 0 1 1 NONE DIGIT SELECTED 1 1 0 0 NONE 1 1 0 1 NONE 1 1 1 0 NONE 1 1 1 1 NONE SEGMENT LINE CONNECTIONS BPl BP2 BP3 BACKPLANE CONNECTIONS FIGURE 13. ICM7231 AND ICM7232 DISPLAY FONTS ("A" AND "B" SUFFIX VERSIONS) SEGMENT LINES SEGMENT LINE CONNECTIONS TABLE 3. ANNUNCIATOR DECODING SEGMENT LINES CODE INPUT AN2 ANl 0 0 0 1 1 1 BPl DISPLAY OUTPUT 0 1 ICM7231A AND ICM7231B ICM7232A AND ICM7232B BOTH ANNUNCIATORS ONBP3 1, 0 1, .0 1, o. 1, . 0. ICM7231C ICM7232C an2 ANNUNCIATOR BP1 an1 ANNUNCIATOR BP3 1, 0 1, D. ·1, 0 ·1, o. BP2 - ' - ' - - - BP3 -~----'----'-BACKPLANE CONNECTIONS ~ffi 0.> -II: cc (f)- NOTE: ,6., t 1. Annunciators can be: I STOP I , @Q] -arrows that point to information printed around the display opening etc., whatever the designer display opening etc., whatever the designer chooses to incorporate in the liquid crystal display. FIGURE 14. ICM7231 DISPLAY FONTS ("C" SUFFIX VERSIONS) Compatible Displays Compatible displays are manufactured by: G.E. Displays Inc., Beechwood, Ohio (216) 831-8100 (#356E3R99HJ) Epson America Inc., Torrance CA (Model Numbers LDB726/7/8). Seiko Instruments USA Inc., Torrance CA (Custom Displays) Crystaloid, Hudson, OH 12·49 ICAf7231,ICAf7232 Typical Applications .tPERIODJ JINTERVAL J t UNIT I t TEST I t FREQ. RAnO J IFREQUENCY I OOOOODOD I I Ll. Ll. Ll. Ll. Ll. Ll. Ll. Ll. ewER RANGE '1 . BOO·3 1CM7231CF Ci AN2 AN1 INPUT A INPUTB -- BCD 27 AO A1 A2 QO Q1 Q2 r-- DPH> I ICM7226A FUNcnON 01·08 LIlJ RANGE t ~ fl E1 CD4532 00·07 ~ V+ os ~ 10K ,:..a:- NOTE: The annunciators show function and the decimal points Indicate the range of the current operation. the system can be efficiently battery operated. FIGURE 23. 10MHz FREQUENCYIPERIOD POINTER WITH LCD DISPLAY 12·50 ICAf723~/CAf7232 Typical Applications (Continued) D7 D8 c::::J . os D6 D1 D2 D3 D4 a a a a a 0 o a Ll•• Ll•• Ll•• Ll., Ll•• Ll., Ll•• Ll. COM 1 I COM 2 ~3 Ixlvlzl Ixlvlzl Ixlvlzl Ixlvlzl Ixlvlz Ixlvlzl Ixlvlzl Ixlvlzl it if 11r- ICM7231AF AND ICM7231 BF TOP VIEW 1 II lm- II FIGURE 24. "FORWARD" PIN ORIENTATION AND DISPLAY CONNECTIONS 010 OIl ISELECT I I]Q] 11 11 D8 IFORWARD I D7 D6 os ~ ~ ~ D4 D3 D2 D1 ISTOP I IWAIT I 1001 11 11 ·0 a 0 0 D. D. Ll. D. D. D. Ll. Ll. Ll. L1. 0 11 COM 1 COM 2 COM 3 ~ffi D.> 0- -a: Cc ICM7232CR TOP VIEW PCB TRACES UNDER PACKAGE ' - -_ _ _ } TO INPUT FIGURE 17. MREVERSE" PIN ORIENTATION AND DISPLAY CONNECTIONS 12·51 ICM7243 8-Character J.1P-Compatible LED Display Decoder Driver December 1993 Features Description • 14-Segment and 16-Segment Fonts With Decimal Point The ICM7243 is an 8-character alphanumeric display driver and controller which provides all the cirCUitry required to interface a microprocessor or digital system to a 14-segment or 16-segment display. It is primarily intended for use in microprocessor systems. where it minimizes hardware and software overhead. Incorporated on-chip are a 54-character ASCII decoder. 8 x 6 memory. high power character and segment drivers. and the multiplex scan circuitry. • Mask Programmable for Other Font-8ets Up Characters to 84 • Microprocessor Compatible • Directly Drives LED Common Cathode Displays • Cascadeble Without AddHional Hardware • Standby Feature TUrns Display Off; Puts Chip In Low Power Mode • Sequential Entry or Random Entry of Data Into Display • Single +5V Operation • Character and Segment Drivers, All MUX Scan Circuitry, 8 x 6 Static Memory and 64-Character ASCII Font Generator Included On-Chip Ordering Information NUMBER TEMPERATURE RANGE PACKAGE ICM7243AIJL -25°C to +85°C 40 Laad Ceramic DIP ICM7243AIPL -2500 to +85°C 40 Laad Plastic DIP ICM7243BIJL -2SOC to +8500 40 Laad Ceramic DIP ICM7243BIPL -2500 to +85°C 40 Lead Plastic DIP 6-bit ASCII data to be displayed is written into the memory directly from the microprocessor data bus. Data location depends upon the selection of either Sequential (MODE 1) or Random access mode (MODE 0). In the Sequential Access mode the first entry is stored in the lowest location and display8d in the "Ieft-mosr character position. Each subsequent entry is automatically stored in the next higher location and displayed to the immediate ·right" of the previous entry. A DISPlay FUll signal is provided after 8 entries; this signal can be used for cascading devices together. A Ci:ii'ijji pin is provided to clear the memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word. = = The character multiplex scan runs whenever data is not being entered. It scans the memory and CHARacter drivers. and ensures that the decoding from memory to display is done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting. CAUTION: These devices are sensltlw to electrostatic dlacharga. Uaara should follow proper I.C. Handling Procaduraa. Copyright @ Harris Corpcntion 11193 . 12-52 File Number 3162 ICM7243 Pinouts ICM7243A (16-SEGMENT CHARACTER) (PDIP) ICM7243B (14-SEGMENT CHARACTER) (PDIP) TOP VIEW TOP VIEW SEom SEGI SEGI SEGg2 SEGe SEGg1 3 SEGb SEGg1 SEGg2 SEGI SEGb SEGf SEol SEGd2 SEof SEGd1 DP DP SEGa1 SEGh SEGh SEGI 01 SEGI DO MODE D2 MODE AQ/SEN 01 AQ/SEN D3 D2 A1ICLR D4 A1/crR D3 A2JD1SP FULL os A2IDISP FULL D4 os~ CS oscio'FJ! os CHAR 1 CS CHAR 1 CHAR 2 CHAR 3 Cs Wii CHAR 2 Wii CHARI CHAR 4 CHARI CHAR 4 CHAR 7 Vss CHAR 7 Vss CHARS CHARS CHARS CHARS 12·53 CHAR 3 ICM7243 Functional Block Diagram 17 ' Q DATA INPUT DO-OS D 84 x 17 LA~~~ES ROM (NOTE 1 SEGMENT (NOTE 1) DRIVERS SEGMENT OUTPUTS SEGx CL Wii (NOTE 1) as CS CS 8 MODE 3 SEL SEL AOISEN A1iCOi MUX ADDRESS MUUTPLEXER AND DECODER A2IDISP FULL INTER-CHARACTER BLANKING NOTE: 1. ICM7243A has only one CS and no 08. ICM7243B has 15 Segments. 12-54 CHARN CHARACTER OUTPUTS Specifications ICM7243 Absolute Maximum Ratings Thermal Information Supply Voltage Voo - Vss •.•••..••.•••.•••.••••..•••.. +6.ov Input Voltage (Any Terminal) •••••••.••.• Voo +ut pin (active low). For an acUve high write pulse, CS can be used, and WR can be used as CS. MODE 31 Selects data entry MODE. High selects Sequential Access (SA) mode where first entry Is displayed in 'eftmosr character and subsequent entries appear to the "rlghr. Low selects the Random Access (RA) mode where data is displayed on the character addressed via AD - A2 Address pins. Ao/sEN 30 In RA mode it Is the LSB of the character Address. In SA mode It Is used for cascading devices for displays of more than 8 characters (active high enables device controller). A1/CLeaR 29 In RA mode this is the second bit of the address. In SA mode, a low Input will CLeaR the Serial Address Counter, the Data Memory and the display. A2IDISPIay FULL 28 In RA mode this is the MSB of the Address. In SA mode, the output goes high after eight entries, Indicating DISPlay FULL. OSc/OFF 27 OSCillator input pin. Adding capacitance to Voo will lower the Internal oscillator frequency. An external oscillator can be applied to this pin. A low at this input sets the device Into a (shutdown) mode, shutting OFF the display and oscillator but retaining data stored In memory. SEGa-SEGm, DP 2 - 9, 32-40 (2 - 7), (32 - 40) CHARacter 1 - 8 18 - 21, 23-26 SEGment driver outputs. CHARacter driver outputs. 12-57 ICM7243 Test Circuit 17 SEGMENTS • • • • • . • • • ..--------..c--WJ.-BJ.-BJ.-BJ.-BJ.-B!l.-BJ.-BJ. CHAR. CHAR 7 CHAR SCHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1 • CHARACTERS SEGMENTS SEGMENTS DISPLAY ~~~~=-------+--.------ FU~ OUTPUT FIGURE 6. 12·58 ICM7243 Typical Applications .. .. • CHARACTERS • CHARACTERS 11111111 11111111 /\. /'/' - +6V RRI CS RBR7 S L ..... 1M8403 UART RBR1-RBRI DRR ZOk V· ..... r CHAR SEG CiJI I......-t CS ICM7243B r a,a D~ wfl,+[ DO-OS DlSP FULL SEN a.WI!i DO-OS CS ..0- f ICM7243B DlSP FULL SEN ~ CS . f • BIT BUS CS CS ~ ICL7566 a f---< V CS CS ~ SEN ICM7243B CUi DELAY TH 1 V DO-OS SEN TR ~ I SEG .~ DR i OUT CHAR CJ:li RBR. /'~ DlSP FULL ICM7243B r-""" Ci ..... DlSP FULL Etc. CiJI CHAR SEG CHAR '",iI' ~,," ~"," SEG ZOOpF nW . ..)' 11111111 1111111.1. .. .. • CHARACTERS • CHARACTERS FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT 12-59 ICM7243 Typical Applications (Continued) 8 CHARACTER LED DISPLAY 8 CHARACTER LED DISPLAY 8 CHARACTER LED DISPLAY "" "" "" 8 1 CDi R 8 NaTE 1 CHAR f- r DlSP FULL DATA BUS :i DO-D& VSS~ CS 6 r DO·OS SEG DlSP FULL 1---+6 Voo ~+5V SEN +6V- MODE Voo ~+6V , . . Wli ~Wli CHAR SEG I - - SEG f-- +6V- SEN +6V- MODE 8 - LCDi CHAR f- NaTE 1 cs Vas r:J" CS 6--- 6 CS, (WR) FIRST 8 CHARACTERS NaTE: 1. 17 FOR ICM7243A, 15 FOR ICM7243B. SECOND 8 CHARACTERS ---- NTH 8 CHARACTERS FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE +5V +5V +5V +5V +6V 1.4APEAK 2N6034 2N22111 2m (100mA PEAK) 2N22111 GND =- GND FIGURE 9A. COMMON CATHODE DISPLAY GND GND FIGURE 98. COMMON ANODE DISPLAY FIGURE 9. DRIVING LARGE DISPLAYS 12·60 NOTE 1 ICM7243 Typical Applications (Continued) .. .. .. .. 1.1.1.1.1.1.1.1. 1.1.1.1.1.1.1.1. 1.1.1.1.1.1.1.1.1.1.1.1.3.1.1.1. 8 CHARACTERS P20 80C35 80C48 • CHARACTERS 8 CHARACTERS 1CM7243AIB 1CM7243AIB 1CM7243AIB 1CM7243AIB CSA2A1 AODO-Dl9m CSA2A1 AODO-Dl9m CSA2A1 AODO-DlWIi CS A2A1 AO DO-DlWIi J 1 I P22 PZ1 8 CHARACTERS I I f>. J -rt> DB7 DBa II BIT BUS DBS-DBO WIi I FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM Display Font and Segment Assignments 05,04 0 0 o 1 1 0 1 1 a {! R1 Lr :0 Lc ,e-GH 1I iLl ,t( t-J t1 t~ P{} R..cJ TI {_I! ~/ W/\\/ VI l Lr \ ] / ~ / I J, I / \ I[ /, / I f / - • / $~ • t U I{J 1I ~:J J - 5 5 ( 8 • / L -- b\ ,- , , , ., a ., 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D3 FIGURE 11. ICM7232A 1&-SEGMENT CHARACTER FONT WITH DECIMAL POINT 12-61 ICM7243 Display Font and Segment Assignments (Continued) I"- If}1ll lrif I< 0 02 ,eP!.J I~ , ,i- i- 10 {D ,-( ,- 1", IB Li- 1 l-- Ll 1-1 I ILl L t1 tJ LI" ~ d 05,04 0 0 0 1 1 0 1 \/ [! _I ~/ ~J /\ V~ UI! ,~ J IT I • 1 ( ( ( 8I 03 0 0 D2 0 01 DO , 11'! ~ ( I ( '- \ \ ) / it - / // / I ~ • 1- i- t U ..) D I8 -, 1-'D • / '- -- ....\ ? ,J , - l- , \/ 7 I t7 I / \ / 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 NOTE: Segments a and d appear as 2 segments each, but both halves are driven together. FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT VDO SEGMENT DRIVER !, ,, : : VLED .. 1.6V RTYPICAL • 100!, ,,, , , R! SEG x DISPLAY SEGMENT LEO. FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT 12-62 ICM7243 Detailed Description Data Entry - The input Data is latched on the riSing edge of WR (or Its equivalent) and then stored in the Data Memory WR, CS, CS - These pins are immediately functionally ANDed, so all actions described as occurring on an edge of WR, with CS and CS enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR or CS due to the additional inverter required on the former. MODE - The MODE pin input is latched on the falling edge of (or its equivalent, see above). The location (in Data Memory) where incoming data will be placed is determined either from the Address pins or the Sequential Address Counter. This is controlled by MODE input. MODE also controls the function of AO/SEN, A1/CLR, and A21DISPlay FULL lines. WR Random Access Mode - When the internal mode latch is set for Random Access (RA) (MODE latched low), the Address.!DE.ut on AO, A 1 and A2. will be latched by the falling edge of WR (or its equivalent). Subsequent changes on the Address lines will not affect device operation. This allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by WR. Sequential Access Mode - If the internal latch Is set for Sequential Access (SA), (MODE latched high), the Serial ENable input or SEN will be latched on the falling edge of WR (or its equivalent). The CLR input is asynchronous, and will force-clear the Sequential Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank) at any time. The DISPlay FULL output will be active in SA mode to indicate the overflow status of the Sequential Address Counter. If this output is low, and SEN is (latched) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is low, or DISPlay FULL is high, no action will occur. This allows easy "daisy-chaining" of display drivers for multiple character displays in a Sequential Access mode. Changing Modes - Care must be exercised in any application involving changing from one mode to another. The change will occur only on a falling edge of WR (or its equivalent). When changing mode from Sequential Access to Random Access, note that A2IDISPlay FULL will be an output until WR has fallen low, and an Address drive here could cause a conflict. When changing from Random Access to Sequential Access, A1/CLR should be high to avoid inadvertent clearing of the Data Memory and Sequential Address Counter. DISPlay FULL will become active immediately after the rising edge of WR. location determined as described above. The six Data bits can be multiplexed with the Address information on the same lines in Random Access mode. Timing is controlled by the WR input. OSc/OFF - The device includes a relaxation oscillator with an internal capacitor and a nominal frequency of 200kHz. By adding external capacitance to V DD at the OSC/OFF pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on this pin. The oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the Multiplex Counter, to drive the CHARacter drive lines (see Figure 3). An inter-character blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the DISPlay FULL output (if active), and clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipat Ion mode in which all outputs are effectively open circuits, except for parasitiC diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including another ICM7243) without driver conflicts. DIsplay Output - The output of the Multiplex Counter is decoded and multiplexed into the address input of the Data Memory, except during WR operations (in Sequential Access mode, with SEN high and DISPlay FULL low), when it scans through the display data. The address decoder also drives the CHARacter outputs, except during the inter-character blanking interval (nominally about 5115). Each CHARacter output lasts nominally about 30011S, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on internal oscillator without external capacitor). The 6 bits read from the Data Memory are decoded in the ROM to the 17 (15 for ICM7243B) segment signals, which drive the SEGment outputs. Both CHARacter and SEGment outputs are disabled during WR operations (with SEN high and DISPlay FULL Low for Sequential Access mode). The outputs may also be disabled by pulling OSC/OFF low. The decode pattern from 6 bits to 17 (15) segments is done by a ROM pattern according to the ASCII font shown. Custom decode patterns can be arranged, within these limitations, by consultation with the factory. 12-63 DATA ACQUISITIO_ 13 COUNTERS WITH DISPLAY DRIVERSI TIMEBASE GENERATORS PAGE COUNTERS WITH DISPLAY DRIVERSITIMEBASE GENERATORS DATA SHEETS HA721 0 Low Power Crystal Oscillator.. . . . . ..•. .. .. .•.. . . ..•.•. . . . ... . . . .• . .. •. •.. . . . ... 13-3 ICM7213 One Second/One Minute Timebase Generator... •.• . . ....... . •.•. . . . . . . .••. . . . . . . .. . 13-16 ICM7216A, ICM7216B, ICM7216D a-Digit Multi-Function Frequency CounterlTimer •••• . . . •.•• .•. . .••. . . •. . . .••. . . . . . . .. . 13-22 ICM7217 4-Digit LED Display Programmable Up/Oown Counter. . • . . . . . . • . . . . . . • . . • . . . . . • . . . . . • • . 13-39 ICM7224 41/ 2 Digit LCD Display Counter. . • . . • . . . . • • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 13-57 ICM7226A. ICM7226B a-Digit Multi-Function Frequency CounterlTimers . . . • • . . . . . . . . . . . . . • • . . • . . . • . • . . . . . • . . 13-64 ICM7249 5 1/ 2 Digit LCD I1-Power EventIHour Meter ...•.•...••..........•.•.•..•.••••..... '" . 13-82 NOTE: Bold "fYpe Designates a New Product from Harris. 13-1 HA7210 Low Power Crystal Oscillator December 1993 Features Description • Single Supply Operatlon@ 32kHz ••••••• 2.0V to 7.0V The HA721 0 is a very low power crystal-controlled oscillator that can be externally programmed to operate between 10kHz and 10MHz. For normal operation it requires only the addition of a crystal. The part exhibits very high stability over a wide operating voltage and temperature range. • Operating Frequency Range •••••••• 10kHz to 10MHz • Supply Current at 32kHz ......................511A • Supply Current at 1MHz ....................13011A • Drives 2 CMOS Loads • Only Requires an External Crystal for Operation The HA7210 also features a disable mode that switches-the output to a high impedance state. This feature is useful for minimizing power dissipation during standby and when multiple oscillator circuits are employed. Ordering Information Applications PART NUMBER • Battery Powered Circuits • Remote Metering • Embedded Microprocessors • Palm TopJNotebook PC Pinout TEMPERATURE RANGE PACKAGE HA7210IP -40oC to +85"C 8 Lead Plastic DIP HA7210lB -40"C to +8SoC 8 Lead SOIC HA7210Y -40oC to +8SoC DIE Typical Application Circuit t4A721 0 TOP VIEW II OSC IN Ii ~ Veo OSC OUT Vss [! [i ::!I ENABLE II FREQ 2 ::!I FREQ 1 :!J OUTPUT tn 32.768kHz tna: a:O CLOCK ~~ FREQUENCY SELECTION TRUTH TABLE ENABLE FREQ1 FREQ2 1 1 1 10kHz - 100kHz 1 1 0 100kHz -IMHz 1 0 1 lMHz-SMHz 1 0 0 SMHz - 10MHz+ 0 X X High-Z OUTPUT RANGE ;:)W 32.768kHz OZ UW CJ MICROPOWER CLOCK OSCILLATOR CAUTION: These devices are sensitive to electrostatic discharge. Users should Iollow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 13-3 File Number 3389.3 HA7210 Simplified Block Diagram VDD 8 ENABLE . -......- - - - 1 EXTERNAL CRYSTAL t--t-~O"..;.;;.-., Voo ·1.4V - 5 IBIAS VDD VDD & OUT FREQ1 Voo RF 7 VAN FREQ2 OSCILLATOR ENABLE FREQ1 FREQ2 SWITCH 1 1 1 51a,b,c 10kHz· 100kHz 1 1 0 52 100kHz· 1MHz 1 0 1 53 1MHz·5MHz 1 0 0 54 5MHz ·10MHz+ 0 X X X High Impedance 13-4 OUTPUT RANGE Specifications HA7210 Absolute Maximum Ratings Operating CondHlons Supply Voitege ••••••••••••••••••••••••••••••••••••• 10.0V Voltege (any pin) ••••••••••••••••••••••• Vss-o.3V to Voo+O.3V Junction Temperature (Plastic Package) ••••••••••••••• +15OOC ESD Rating (Note 2) ............................... >4OOOV Lead Temperature (Soldering 10&) •••••••••••••••••••• +3OOOC Operating Temperature (Note 3) •••••••••••••••• -40"C to +85°C Storage Temperature Range •••••••••••••••••• -6500 to +15O"C SOIC •••••••••••••••••••••••••••••••••••••••• 17C1'C1W Plastic DIP •••••••••••••••••••••••••••••••••••• 15O"C1W CAUTION: StrIJssea ...... /hose listed In ~.. MaxImum Ratings" may C8UU ".",..,..", damage to the dIwice. TIlls Is • stress on/jI tatill(l8nd opetalfon of /he dtwIce .t IINJaa or any ol/r.,. t:tJfIdItioM abow /hose IndIt:atsd in the optItationaJ SBCtIorJs of /his specification Is not 1npIIed. Electrical SpeCifications Vss =GND, TA =+2500, Unless Otherwise Specified. Voo -5V PARAMETER = Veo Supply Range (lose 32kHz) 100 Supply Current =32kHz, EN = 0 Standby lose =32kHz, CL = 10pF (Note 1), EN =1, Freq1 =1, Freq2 = 1 lose lose = 32kHz, CL = 4OpF, EN = 1, Freq1 = 1, Freq2 = 1 lose = 1MHz, CL = 10pF (Note 1), EN = 1, Freq1 = 0, Freq2 = 1 lose = 1MHz, CL = 4OpF, EN = 1, Freq1 = 0, Freq2 = 1 VOH Output High Voltage (lOUT = -1mA) TVP MAX MIN TYP MAX UNITS 2 5 7 - - - V 5.0 9.0 - - jiA 5.2 10.2 3.6 6.1 jiA 10 15 6.5 9 jiA 4.0 130 200 - 270 350 - 4.9 - 0.07 0.4 -10 -5 - - - - - - - 12 25 - 12 12 25 54 60 41 - IOH Output High Current (VOUT ~ 4V) - IOL Output Low Current (VOUT S 0.4V) 5.0 10.0 - 0.1 VOL Output Low Voitege (lOUT = 1rnA) Trl-Stete Leakage Current (VOUT = OV, 5V, TA .. 25°C,-4O"O) (VOUT = OV, 5V, TA = 85"C) liN Enable, Freq1, Freq2 Input Current (VIN = Vss to VOO) - 10 - - 0.4 1.0 - - VIH Input High Voltage Enable, Freq1, Freq2 2.0 VIL Input Low Voltege Enable, Freq1, Freq2 - Enable Time (CL = 18pF, RL = 1kn) Disable Time (CL = 18pF, RL = 1kn) ~ Output Rise Time (10% - 90%, lose = 32kHz, CL = 4OpF) '" Output Fall Time (10% - 90%, lose = 32kHz, CL " 4OpF) Duty Cycle (CL = 4OpF) lose" 1MHz, Packaged Part Only (Note 4) Duty Cycle (CL = 4OpF) lose = 32kHz. (See Typical Curves) Frequency Stebilityvs. Supply Voltage (lose = 32kHz, Voo =5V, CL=1OpF) Frequency Stability vs, Temperature (lose" 32kHz, Voo = 5V, CL..10pF) Frequency Stebilltyvs. Load (fosc = 32kHz, Voo = 5V, CL=10pF) Voo '"3V MIN 40 - 800 90 1 0.1 0.01 0.8 - - NOTES: 1. Calculated using the equatlon 100 = 100 (No Load) + (VOD) (loscl(CL,) 2. Human body model. 3. This product is production tested at +25"C only. 4. Duty cycle will vary with supply voltege, oscillation frequency, and parasitic capacitance on the crystal pins. 13-5 90 160 jiA 160 270 jiA 2.8 - V - rnA rnA - nA - nA 0.1 14 44 - - V jiA V V ns ns ns ns % % ppmIV ppmI"C ppmlpF HA7210 Test Circuits mance. The reduced operating voltage of the oscillator section reduces power consumption and limits transconductance and bandwidth to the frequency range selected. For frequencies at the edge of a range, the higher range may provide better performance. The crystal oscillator waveform on pin 3 is squared up through a series of inverters to the output drive stage. The Enable function is implemented with a NAND gate in the Inverter string, gating the signal to the level shifter and output stage. Also during Disable the output is set to a high impedance state useful for minimizing power during standby and when multiple oscillators are OR'd to a single node. Design Considerations FIGURE 1 In production the HA7210 is tested with a 32kHz and a 1MHz crystal. However for characterization purposes data was taken using a sinewave generator as the frequency determining element, as shown in Figure 1. The 1Vp_p input is a smaller amplitude than what a typical crystal would generate so the transitions are slower. In general the Generator data will show a "worst case" number for 100. duty cycle, and riselfall time. The Generator test method is useful for testing a variety of frequencies quickly and provides curves which can be used for understanding performance trends. Data for the HA7210 using crystals has also been taken. This data has been overlaid onto the generator data to provide a reference for comparison. Theory of Operation The HA7210 is a Pierce Oscillator optimized for low power consumption, requiring no external components except for a bypass capacitor and a Parallel Mode Crystal. The Simplified Block Diagram shows the Crystal attached to pins 2 and 3, the Oscillator input and output. The crystal drive circuitry is detailed showing the simple CMOS inverter stage and the P-channel device being used as biasing resistor RF The inverter will operate mostly in its linear region increasing the amplitude of the oscillation until limited by its transconductance and voltage rails, Voo and VRN• The inverter is self biasing using RF to center the oscillating waveform at the input threshold. Do not interfere with this bias function with external loads or excessive leakage on pin 2. Nominal values for RF are 17MO in the lowest frequency range to 7MO in the highest frequency range. The HA7210 optimizes its power for 4 frequency ranges selected by digital inputs Freq1 and Freq2 as shown in the Block Diagram. Internal pull up resistors on Enable, Freq1 and Freq2 allow the user simply to leave one or all digital inputs not connected for a corresponding ·1" state. All digital inputs may be left open for 10kHz to 100kHz operation. A current source develops 4 selectable reference voltages through series resistors. The selected voltage, VRN , is buffered and used as the negative supply rail for the oscillator section of the circuit. The use of a current source in the reference string allows for wide supply variation with minimal The low power CMOS transistors are designed to consume power mostly during transitions. Keeping these transitions short requires a good decoupling capacitor as close as possible to the supply pins 1 and 4. A ceramic 0.1 IlF is recommended. Additional supply decoupling on the circuit board with 1IlF to 10J.t.F will further reduce overshoot, ringing and power consumption. The HA7210, when compared to a crystal and inverter alone, will speed clock transition times, reducing power consumption of all CMOS circuitry run from that clock. Power consumption may be further reduced by minimizing the capacitance on moving nodes. The majority of the power will be used in the output stage driving the load. Minimizing the load and parasitic capacitance on the output, pin 5, will play the major role in minimizing supply current. A secondary source of wasted supply current is parasitic or crystal load capacitance on pins 2 and 3. The HA7210 is designed to work with most available crystals In Its frequency range with no external components required. Two 1SpF capacitors are internally switched onto pins 2 and 3 to compensate the oscillator in the 10kHz to 100kHz frequency range. The supply current of the HA721 0 may be approximately calculated from the equation: =loo(Disabled) + Voo x Fosc x CL where: 100 =Total supply current 100 Voo = Total voltage from Voo (pin 1) to Vss (pin4) Fosc = Frequency of Oscillation CL = Output (pinS) load capacitance Example.1: = Voo SV, Fosc -100kHz, CL = 30pF loo(Disabled) = 4.Sj.lA (Figure 10) 100 = 4.Sj.lA + (SV)(100kHz)(30pF) = 19.5j.lA Measured 100 2O.3j.lA = Example 12: = Voo 5V, Fosc = SMHz, CL = 30pF loo(Disabled) = 7Sj.lA (Figure 9) 100 = 7Sj.lA + (5V)(SMHz)(3OpF) = 82Sj.lA Measured 100 = 809j.lA 13-6 HA7210 Crystal Selection For general purpose applications, a Parallel Mode Crystal is a good choice for use with the HA7210. However for applications where a precision frequency is required, the designer needs to consider other factors. Crystals are available in two types or modes of oscillation, Series and Parallel. Series Mode crystals are manufactured to operate at a specified frequency with zero load capacitance and appear as a near resistive impedance when oscillating. Parallel Mode crystals are manufactured to operate with a specific capacitive load in series, causing the crystal to operate at a more inductive impedance to cancel the load capacitor. Loading a crystal with a different capacitance will "pulf' the frequency off its value. The HA7210 has 4 operating frequency ranges. The higher three ranges do not add any loading capacitance to the oscillator circuit. In the lowest range, 10kHz to 100kHz, the HA721 0 automatically switches in two 15pF capacitors onto OSC IN (pin2) and OSC OUT (pin3) to eliminate potential start-up problems. These capacitors create an effective crystal loading capacitor equal to the series combination of these two capaCitors. For the HA7210, in the lowest range, the effective loading capaCitance is 7.5pF. Therefore the choice for a crystal, in this range, should be a Parallel Mode crystal that requires a 7.5pF load. In the higher 3 frequency ranges, the capacitance on pins 2 and 3 will be determined by package and layout parasitics, typically 4 to 5pF. Ideally the choice for crystal should be a Parallel Mode set for 2.5pF load. A crystal manufactured for a different load will be ·pulled" from its nominal frequency (see Crystal Pullability). For best oscillator performance, two conditions must be met: the capacitive load must be matched to both the inverter and crystal to provide ideal conditions for oscillation, and the frequency of the oscillator must be adjustable to the desired frequency. In Method two these two goals can be at odds with each other; either the oscillator is trimmed to frequency by de-tuning the load circuit, or stability is increased at the expense of absolute frequency accuracy. Method one allows these two conditions to be met independently. The two fixed capacitors, C 1 and C2 , provide the optimum load to the oscillator and crystal. C3 adjusts the frequency at which the circuit oscillates without appreciably changing the load (and thus the stability) of the system. Once a value for C3 has been determined for the particular type of crystal being used, it could be replaced with a fixed capacitor. For the most preCise control over oscillator frequency, C3 should remain adjustable. This three capacitor tuning method will be more accurate and stable than method two and is recommended for 32kHz tuning fork crystals; without it they may leap into an overtone mode when power is initially applied. Method two has been used for many years and may be preferred in applications where cost or space is critical. Note that in both cases the crystal loading capacitors are connected between the oscillator and Voo; do not use Vss as an AC ground. The Simplified Block Diagram shows that the oscillating inverter does not directly connect to Vss but is referenced to Voo and V RN • Therefore Voo is the best AC ground available. Frequency Fine Tuning Two Methods will be discussed for fine adjustment of the crystal frequency. The first and preferred method (Figure 2), provides better frequency accuracy and oscillator stability than method two (Figure 3). Method one also eliminates start-up problems sometimes encountered with 32kHz tuning fork crystals. U)~ ffi~ l-iCC Za: ::;)w OZ (,)W (!J FIGURE 3 .---4---'" Veo + VREG HA721 0 Typical values of the capacitors in Figure 2 are shown below. Some trial and error may be required before the best combination is determined. The values listed are total capacitance including parasitic or other sources. Remember that in the 10kHz to 100kHz frequency range setting the HA7210 switches in two internal 15pF capacitors. FIGURE 2 13-7 HA7210 CRYSTAL FREQUENCY LOAD CAPS C1,C2 TRIMMER CAP 32kHz 33pF 5-5OpF 1MHz 33pF 5-5OpF 2MHz 25pF 5-5OpF 4MHz 22pF 5-100pF In a similar way. the Series Mode resonant frequency may be calculated from a Parallel Mode crystal and then you may calculate hOW much the frequency will "pulr with a neW load. C3 Layout Considerations Crystal Pullabillty Figure 4 shows the basic equivalent circuit for a crystal and its loading circuit. ~ L ____________!~~:oo Due to the extremely low current Marvin E. Frerking "Crystal Oscillator Design and Temperature Compensation". New York: Van Nostrand-Reinhold. 1978. Pierce Oscillators Discussed pp56-75. J Where: Fp = Parallel Mode Resonant Frequency Fs = Series Mode Resonant Frequency 13-8 HA7210 Die Characteristics DIE DIMENSIONS: 68x64x 14± 1mils METALUZATION: Type: Si ·AI Thickness: 1 ±1 okA kA GLASSIVATlON: Type: Nitride (Si3N41 Over ~ilox (Si02• 3% Phos) Silox Thickness: 7kA '}. 1kA Nitride Thickness: akA ± 1 kA DIE ATTACH: Material: Silver Epoxy· Plastic DIP and sOle SUBSTRATE POTENTlAL: Vss Metallization Mask Layout HA721 0 (7)FREQ2 CRYSTAL (2) CRYSTAL (3) (6) FREQ 1 (/)~ ffi~ Za::, !-icC :::IW OZ ow CJ 13·9 HA7210 Typical Performance Curves CL" 40pF, Fose" 5MHz, VDD" 5V, VSS" GND CL " 18pF, FOSC" 5MHz, VOO. SV, Vss • GND I \ \, .\ \ J ,j I - 1.0VIDIV. , - 20.0nslDtV. 1.0VIDIV. FIGURE 5. OUTPUT WAVEFORM (CL = 40pF) EN _1, F1 _1, F2 .1, FIN -100kHz, CL" 30pF, Vee" 5V 25 "- ............. t--... j:" 950 zw " '" GENERATOR' (1Vp.p) II: II: B 900 " ~ 8: 850 75~100 -50 0 50 ............ ............. ~ XTAL AT +2SOC ~ / - 111 100 18 -100 150 -50 TEMPERATURE (DC) 0 50 100 150 TEMPERATURE (DC) FIGURE 8. SUPPLY CURRENT VI TEMPERATURE FIGURE 7. SUPPLY CURRENT VI TEMPERATURE 7.5 350 EN. 0, F1 .. 1, F2 =1, FIN .. 100kHz, Vee. IV FIN" 5MHz, EN .. 0, F1 .. 0, F2 .. 0, Vee" 5V 300 '1 -250 ~ ~ """ ~ ~ w ~ 200 B ~ 150 - 100 50 o " ....GENERATOR' (1Vp.p) "' XTAL AT +25°C 800 8: i =1BpF) 25 FIN" 5MHz, EN =1, F1 ,,0, F2" 0, C L" 30pF, Vee. 5V I '1 :I UI 20.0nslDtV. FIGURE 6. OUTPUT WAVEFORM (CL 1050 1000 \ J I-- -100 -50 " XTALAT+~ r-::-.~ o ~GENERATOR' (1Vp.p) I GENERATOR' (1Vp.p) 50 - "'- 100 '" XTAL AT +2SOC 4.5 4 -100 150 0 50 / 100 150 TEMPERATURE (DC) TEMPERATURE (DC) FIGURE 9. DISABLE SUPPLY CURRENT va TEMPERATURE -50 "- FIGURE 10. DISABLE SUPPLY CURRENT va TEMPERATURE , Refer to Test Circuit (Figure 1). 13-10 HA7210 Typical Performance Curves (Continued) 3000 1400 I. J. I ,I. .".! EN .,, F1 • 0, F2 .. 0, C L .11pF, GENERATOR' (1Vp-p) EN .,, F1 .0, F2 .1, CL .'lpF, GENERATOR' (1Vp-p) 1200 2500 1 l VCC·+8\ !z 2000 ~ 81500 ~ V .-- ~ .,,- - --- i-"""" Do !!iUI 1000 500 ~ 5 4 5 ./ VCC·+SV 10 II -- o 11 FREQUENCY (MHz) FIGURE 11. SUPPLY CURRENT vs FREQUENCY VCC,V ./ ---- . . . " VCC=+3V ~ Y 200 I 7 / / f,--- o o / VCC·+8V ~ 2 5 4 3 6 FREQUENCY (MHz) FIGURE 12. SUPPLY CURRENT vs FREQUENCY 300 EN = " F1 = 1, F2 = 0, CL=1IpF, GENERATOR' (1Vp-p) 250 I I VCC=+IV ~ ~ ~ V ..". / 50 o o ~ ,/ ~ ~~-+--+--+--+--+--+--+--+--t--i--; V l ffi30~~--+-~--+--+--+--+~~-4--4-~ VCC.+SV..... ~ ~ ...- 10- ! ........ .",. V ~ ~ ...- EN .1, F1 .0, F2.1, CL-1IpF, GENERATOR' (1Vp.p) ~20~-+-+--t--b~I--+ VCC=+3V 1"""- i--""'" 100 200 300 400 500 600 700 100 900 1000 11 00 00 FREQUENCY (kHz) 10 20 30 40 50 60 80 70 FIGURE 13. SUPPLY CURRENT vs FREQUENCY EN = 0, F1 = 0, F2 = 0, CL =18pF, GENERATOR' (1Vp.p) 120 Vcc·+IV 110 VCC·+5V l100 !Z 90 ~ II: 80 8 70 ~ ~ 60 UI - Vcc-+IV o V_ /. V VCC·+5V_ 7 I II FREQUENCY (MHz) 10 V/ CJI/.I V CJ 50 VCC·+3V- 2 11 3 4 5 FREQUENCY (MHz) FIGURE 15. DISABLED SUPPLY CURRENTvs FREQUENCY FIGURE 16. DISABLE SUPPLY CURRENT vs FREQUENCY , Refer to Test Circuit (Figure 1). 13-11 ~!cc Za: OZ ~ VCCj+3V 0a: a:O ::)1/.1 50 6 100 110 EN .. 0, F1 .0, F2 .1, CL • 18pF, GENERATOR' (1Vp-p) 250 5 80 FREQUENCY (kHz) FIGURE 14. SUPPLY CURRENT vs FREQUENCY 6 HA7210 Typical Performance Clirves (Continued) EN .. 0, F1 .. 1, F2 .. 0, CL .. 1IpF, GENERATOR· (1Vp.p) 3S I EN.O, F1 .1, F2 .1, CL .11pF, GENERAtOR· (1Vp.p) 11 I Vcc·+8V ,.;' 10 V Kc:.~ ~ :::;.. / . t:::: V" ./ ~ ,,- ,,- "". Vcc .. +3V ." / ~~ 1. I !E II! a: I 8 ~ ~ :;/ 100 200 300 400 500 600 700 100 900 1000 11 00 ~ 7 -- 5 4 2 :.- ~ ~ ~ :.o 10 20 30 40 2500 i UI 1500 1000 5 .-~ I / / ./ io"""" CL·1IpF 10 9 o o 11 ../ ~.1IPF_ V ~ 200 7 5 2 FREQUENCY (MHz) 3 5 4 FIGURE 20. SUPPLY CURRENT vs FREQUENCY EN .1, F1 .. 1, F2 .. 1, Vee" +!iV, GENERATOR" (1Vp.p) , , EN _1, F1 .. 1, F2. 0, Vee" +5V, GENERATOR· (1Vp.p) 35 300 CL,"40pF CL"40~ ,/ V ,/ 1/ ~,/ ,,/ "". V 50 ~ "".,. V "". CL=18pF V i-"""" ~ o o 6 FREQUENCY (MHz) FIGURE 19. SUPPLY CURRENT vs FREQUENCY , V 100 110 V V" --- I--""" 90 CL"40pF""",, 1200 V / / 10 EN .. 1, F1. 0, F2 .. 1, Vcc .. +5y, GENERATOR· (1Vp.p) CL,,40pF ..". 70 1400 I I io'" 60 SO FIGURE 18. DISABLE SUPPLY CURRENTvs FREQUENCY EN .. 1, F1 .0, F2. 0, Ve e" +5'1, GENERATOR" (1Vp.p) 3000 ~ ...- ...r ...- -Vj.+3'1- ~ :.- - FREQUENCY ( kHz) FIGURE 17. DISABLE SUPPLY CURRENT va FREQUENCY ffi 2000 - Vcc=+!iV I 6 FREQUENCY (kHz) 1 ~ I-- ...- ...- 3 5 o Vee!+8V' 10 ~~ 5 100 200 300 400 500 600 700 800 900 1000 11 00 FREQUENCY (kHz) FIGURE 21. SUPPLY CURRENT vs FREQUENCY o o 10 20 """" ~ ,,- V l"...o-' "".,. io'" CL=18pF ./ ." 30 40 so 60 70 80 FREQUENCY (kHz) 80 100 110 FIGURE 22. SUPPLY CURRENT vs FREQUENCY • Refer to Test Circuit (Figure 1). 13-12 HA7210 Typical Performance Curves (Continued) liN • 100kHz, Fl .1, F2 81, CL" 30pF, Vee. 5V FIN" 5MHz, F1 .. 0, F2" 0, CL. 3OpF, Vee. 6V 6O...---"T""---'T---T"'""--"T""----. 70 "~--+---~---+--~--~ 60 GENERA~R* (1Vp.p) ' - ............ ~60~--+-~~~~~~~~ i Gr------+-i~--~~---+--~~+_~~_i XTAL AT +25"<: ~- '\ '" ~ 5 @r-----~~--+---~~~--~~~ ~ 20 10 ·100 ~1~00~--~~~0~----~0----~5~0----~1~00~--~150 TEMPERATURE ( °c ) FIGURE 23. DUTY CYCLE vs TEMPERATURE 50 o TEMPERATURE (OC ) 100 150 FIGURE 24. DUTY CYCLE vs TEMPERATURE 70 Fl .. F2aO, Voo" SV, CL = 18pF, Cl .. ~ .. 0 DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY g DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY 65 65 ~ '\ \ .. -- V"" 1/ so 45 ....".. \. / V ~ 5 10 FREQUENCY. (MHz) 15 20 FIGURE 25. DUTY CYCLE vs FREQUENCY F1 / \ , / r--...... 45 40 o I o ,/ 2346678' FREQUENCY (MHz) FIGURE 26. DUTY CYCLE V8 FREQUENCY =0, F2 =0 RECOMMENDED FOR 5MHz TO 10MHz RANGE F1 =0, F2 =1 RECOMMENDED FOR 1MHz TO 5MHz RANGE F1 =1, F2. 0, Voo,,5V, CL,,18pF, Cl" ~ .. O 65 DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY DATA COLLECTED USING CRYSTALS 46 _ 60 ~ ~ ~ 55 ~ 550 \/ 45 / r-- -- ./ / / \ ~ a:: 0 ~ti Za:: OZ ::;)w ./ \ UW (,:J \ / V 42 41 40 (I)! ~ATEACHFREQUENCY 40 o 500 1000 1600 2000 2500 3000 3500 o FREQUENCY(lcHz) 60 100 160 200 FREQUENCY (kHz) FIGURE Z7. DUTY CYCLE vs FREQUENCY F1 = 0, F2 = 0 RECOMMENDED FOR 100kHz TO 1MHz RANGE FIGURE 28. DUTY CYCLE vs FREQUENCY F1 • Refer to Test Circuit (Figure 1). 13-13 =1, F2 =1 RECOMMENDED FOR 10kHz TO 100kHz RANGE HA7210 Typical Performance Curves (Continued) Vcc.SV, CL.30pF, GENERATOR" (1Vp.p) 30 II C 32kHz 1MHz 5MHz _ A ~ + <> 25 ~20 ... ;;; 15 10MHz \ ~ 4 c:J :i 10 li 5 zt 5 ~ t. 3 w 8-5 w 9:.10 ~ 2 w \J, 8 w 4 2 FIGURE 29. FREQUENCY CHANGE vs VDD Deviation from 5.0V Frequency 12 8 =-- 6 5 4 ~ - II! ,- Tr XTAL AT +25O( 50 ~ <#' 5 I o 50 CL" 18pF, GENERATOR" (1Vp.p) :[25 w _ 14 13 .! 12 ~ :120 § § ~ 15 II! .c m it --- 11 I I TI (FIN" 5MHz) ~' - - - TI (FIN" 100kHz) ~, , Tr (FIN =SMHz) "-\.'- 10 8 Tr (FIN. 100kHz) ~ 8 "- ~ 7 10 ...... 6 5 50 60 150 FIGURE 32. RISEJFALL TIME va TEMPERATURE 15 40 100 TEMPERATURE <"C) Vcc" 5V, GENERATOR" (1Vp.p) 30 Tr XTAL AT +25"c ~ ·100 FIGURE 31. RISEIFALL TIME vs TEMPERATURE 20 ~ .-.-'I ~ TEMPERATURE (OC) S 10 Tf XTAL AT +25"C ~ 2 150 ~ 8 Tr GENERATOR" (1Vp.pl 7 3 100 ,.. ~~ I 4 I I 8 m6 I o -50 5.... ~ ~ I 10 :I I Tr GENERATOR" (1Vp.p)- TI XTAL AT +25"¥ ---' 3 2 ·100 !w J-...o'-""1 , 9 150 TI GENERATOR" (1Vp.p) 11 .A I 10 m7 ~ 12 I TI GENERATOR" (1Vp.p) ,.,- 11 100 FIN .. 100kHz, F1 .1, F2 .1, C L" 30pF, Vee. 5V I I I 0 50 TEMPERATURE <"C) -50 FIGURE 30. EDGE JITTER vs TEMPERATURE FIN" 5MHz, F1 .. 0, F2 =0, CL" 30pF, Vcc. 5V 13 I ~100 6 Veo SUPPLY VOLTAGE (V) 9 \. FIN" 100kHz, F1 .1, F2.1 ·20 ~ ~ 1"- l{ ·15 ! II FIN=5MHz, F1.0, F2 .. 0 It.. ffi 0 , vr / 70 80 80 42 100 110 CL(PF) FIGURE 33. RISEJFALL TIME vs CL 3 ~\ S S II Vee (+Volts) 7 --- FIGURE 34. RISEJFALL TIME vs Vee " Refer to Test Circuit (Figure 1). 13·14 8 HA7210 Typical Performance Curves (Continued) Voo =sv, Vss = GND ~ 500 VOD =SV, VSS = GND 620 580 540 w 500 o ~ g 420 Q 380 ........ 1""' '" lil 340 z ••.•.••.••...••.•••••••.•.••• 6.0V Output Current (Any output) •...••.•.....•••••.•.....•• 20mA All Input and Oscillator Voltages •....•••• Vss - 0.3V to Voo + 0.3V All Output Voltages •.•.•.•••••.••••.••••••••••.• Vss to 6.0V Operating Temperature Range •••••••.••••••••• -25°C to +65°C Storage Temperature Range •.•...•.•••.•.•.. -55°C to +l50oC Lead Temperature (Soldering, lOs) .•.•••.•••.•...•.•. +3OO"C Thermal Resistance 9JA Plastic Package. • • . • • • . . • . • • • . . • . . • . • . . • . . . .• 145"CIW Junction Temperature .......•••.•.••.••••••.••.•.•. +15O"C CAUTION; s _ sboII8 thoss listed In "Absalu" Maximum Ratings· may C8US11 parmanent damage to the davies. This Is a stress only tatlng and opstation of the dwics at thsss or any other conditions abol/ll those indicated in the opBtationaJ ssctIons of this specification Is not impHed. Electrical Specifications Voo - Vss = 3.0V, fosc =4.194304MHz, Test Circuit, TA = 25°C Unless Otherwise Specified PARAMETER TEST CONDITIONS Supply Current, 100 MIN TYP MAX UNIT - 100 140 jiA Guaranteed Operating Supply Voltage Range (Voo - Vss>, VSUPPlY -200C < TA < +65°C 2 - 4 V Output Leakage Current, IOlK Any output, Your = 6V - - 10 jiA Output Sat. Resistance, RoUT Any output, IOLK = 2.5mA 200 n Inhibn terminal connected to Voo - 120 Inhibit Input Current, I, 10 40 jiA Tast Point Input Current, Irp Test point terminal connected to Voo - 10 40 jiA Width Input Current, Iw Width terminal connected to VDO - 10 40 jiA - - 118 10 MHz - ppm Oscillator Transconductance, gM 100 Voo=2V Oscillator Frequency Range (Note 1), fose Oscillator Stability, fSTAB 1 - 2V 100 I VSUPPLy=3V CIN • COUl =30pF _ \, ~ U "'" ~ Do Do :::> 110 III 80 70 -40 Fosc • 4.19MHz I ~ V 0L-__4 -__ __ __ __-L__ 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE VOD - Vss M ~ -20 0 +20 +40 TEMPERATURE <"C) +60 +80 FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF TEMPERATURE ~ ~ ~ FIGURE 4. SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 13-19 ICM7213 Typical Performance Curves 30 E +1.5 8: S- . a: a: 15 I I CIN. CaUT AND QUARTZ CRYSTAL MAINTAINED AT +aoc lose. 4.1 DMHz ~ +0.5 1---.F---I6,.oo00llC:'\ ~ !i!w 5 -0.5 ~ 6 10 t-1_~~--4-~~~~===i::~ I::I ~ "",.Vg." z 5 1-*--,4-- / I ~ -1.0 '"' ~ OL---~--~--~--~--~~ o ~ 0.1 0.2 0.3 0.4 0.5 0.& OUTPUT SATURAnON VOLTAGE (ANY OUTPUT) (V) FIGURE 5. OUTPUT CURRENT AS A FUNCTION OF OUTPUT SATURATION VOLTAGE / -1.5 -40 t V V V -20 0 +20 +40 TEMPERATURE fC) +50 +80 FIGURE 6. OSCILLATOR STABILITY AS A FUNCTION OF DEViCE TEMPERATURE 8 5 J 4 ./ 3 o,,~ 2 3.0 4.0 SUPPLY VOLTAGE Voo - Vss (V) WINDOW o 5.0 10kHz 100kHz 1MHz FIGURE 8. WINDOW OF CORRECT OPERATION FIGURE 7. OSCILLATOR STABILITY. AS A FUNCTION OF SUPPLy VOLTAGE Test Circuit WIDTH +-_...~N;::.;:;;o.:"'--I INHIBIT '--..q" 0-:.;::';;;;"---1 CRYSTAL PARAMETER 1= 4.1D4304MHz RS.360 (PARALLEL RESONANT) CM_17mpF CO =2.5pF N.O. T.P. )1).--__....____00 + 100 13-20 VSUPPLY 10MHz ICM7213 Detailed Description Control Inputs Supply Voltage Considerations The ICM7213 may be used to provide various precision out· puts with frequencies from 2048Hz to 1160Hz using a 4. 194304MHz quartz oscillator. and other output frequencies may be obtained using other quartz crystal frequencies. Since the ICM7213 uses dynamic high frequency dividers for the initial frequency division there are limitations on the VSUPPLY range depending on the OSCillator frequency. If. for example. a low frequency quartz crystal is selected. the VSUPPLY should be selected in the center of the operating window. or approximately 1.7V. The TEST input inhibits the 2 18 output and applies the 29 output to the 221 divider. thereby permitting a speedup of the testing of the + 60 section by a factor of 2048 times. This also results in alternative output frequencies (see table). The WIDTH input may be used to change the pulse width of OUT 4 from 125ms to 1s. or to change the state of OUT 4 from ON to OFF during INHIBIT. See Figures 1 and 2 for output waveforms and effect of can· trol inputs. Vs+ The VSUPPLY to the ICM7213 may be derived from a high voltage supply by using a simple resistor divider (if power is of no concern). by using a series resistor for minimum cur· rent consumption. or by means of a regulator. Outputs EXAMPLE: f,.4.2MHz BV s V S 12V (10 NOMINAL) 11 ~1001'A 12- 1mA Rt-31en Pull up resistors will generally be required to interface with other logic families. These resistors must be connected between the various outputs and the positive power supply. Rl- a.BIen 12 Oscillator Considerations The oscillator consists of a CMOS inverter and a feedback resistor whose value is dependent on the voltage at the oscillator input and output terminals and the VSUPPLY' Oscil· lator stabilities of approximately 0.1 ppm per 0.1V variation are achievable with a nominal VSUPPLY of 5V and a single voltage dropping resistor. The crystal specifications are shown in the Test Circuit. It is recommended that the crystal load capacitance (Cl) be no greater than 22pF for a crystal having a series resistance equal to or less than 750. otherwise the output amplitude of the oscillator may be too low to drive the divider reliably. It a very high quality oscillator is desired. it is recommended that a quartz crystal be used having a tight tuning tolerance ±10ppm. a low series resistance (less than 25Q). a low motional capacitance of 5mpF and a load capacitance of 20pF. The fixed capacitor CIN should be 30pF and the ascii· lator tuning capacitor should range between approximately 16pF and 60pF. Use of a high quality crystal will result in typical stabilities of 0.05ppm per 0.1V change of VSUPPLY' Vs· FIGURE9A. EXAMPLE: lose ,. 4.2MHz Vs+ BV S V s 12V (10 NOMINAL) 11- 1OOIlA R3 R3=(10·3) 10.4 len -6BIen CBYPASS O.OlILF . Vs· FIGURE9B. FIGURE 9. BIASING SCHEMES WITH HIGH VOLTAGE SUPPLIES U)~ a:O ~tc Za: OZ UW CJ ;:)W 13·21 ICM7216A,ICM72168 ICM7216D a-Digit Multi-Function . Frequency CounterlTimer December 1993 Features All Versions • Functions as a Frequency Counter (DC to 10MHz) • Four Internal Gate Times: 0.01s, 0.1s, 1s, 10s In Frequency Counter Mode • Directly Drives Digits and Segments of Large Multiplexed LED Displays (Common Anode and Common Cathoda Versions) • Single Nominal 5V Supply Required • Highly Stable Oscillator, Uses 1MHz or 10MHz Crystal The ICM7216A and ICM7216B are fully integrated Timer Counters with LED display drivers. They combine a high frequency oscillator, a decade timebase counter, an a·decade data counter and latches, a 7-segment decoder, digit multiplexers and 8 segment and 8 digit drivers which directly drive large multiplexed LED displays. The counter inputs have a maximum frequency of 10MHz in frequency and unit counter modes and 2M Hz in the other modes. Both inputs are digital inputs. In many applications, amplification and level shifting will be required to obtain proper digital signals for these inputs. • Functions Also as a Period Counter, UnH Counter, Frequency Ratio Counter or nme Interval Counter The ICM7216A and ICM7216B can function as a frequency counter, period counter, frequency ratio (f""8) counter, time interval counter or as a totalizing counter. The counter uses either a 10MHz or 1MHz quartz crystal timebase. For period and time interval, the 10MHz tlmebase gives a 0.1118 resolution. In period average and time interval average, the resolution can be in the nanosecond range. In the frequency mode, the user can select accumulation times of 0.01 s. 0.1 s, 1s and 10s. With a 10s accumulation time, the frequency can be displayed to a resolution of 0.1 Hz in the least significant digit. There is 0.2s between measurements in all ranges. • 1 Cycle, 10 Cycles, 100 Cycles, 1000 Cycles In Period, Frequency Ratio and nme Interval Modes The ICM7216D functions as a frequency counter only, as described above. • Measures Period From 0.51J.8 to 108 All versions of the ICM7216 incorporate leading zero blanking. Frequency is displayed in kHz. In the ICM7216A and ICM7216B, time is displayed in I1S. The display is multiplexed at 500Hz with a 12.2% duty cycle for each digit. The ICM7216A is designed for common anode displays with typical peak segment currents of 25mA. The ICM7216B and ICM7216D are designed for common cathode displays with typical peak segment currents of 12mA. In the display off mode, both digit and segment drivers are turned off, enabling the display to be used for other functions. • Internally Generated Daclmal Points, Intardlgit Blanking, Leading Zero Blanking and OVerflow Indication • Display Off Mode TUrns Off Display and Puts Chip Into Low Power Mode ' • Hold and Reset Inputs for Additional Flexibility Features ICM7216A and ICM7216B Features ICM7216D • Decimal Point and leading Zero Banking May Be Externally Selected Ordering Information TEMPERATURE RANGE PACKAGE ICM7216AIJI -2500 to +85OC 28 Lead Ceramic DIP ICM7216BIPI ·2500 to +8500 28 Lead Plastic DIP ICM7216DIPI ·2500 to +85°C 28 Lead Plastic DIP PART NUMBER CAUTION: These dwlces &Ie sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 13·22 File Number 3166 ICM7216A, ICM72168, ICM7216D Pinouts ICM7216B COMMON CATHODE (PDIP) TOP VIEW ICM7216A COMMON ANODE (CDIP) TOP VIEW CONTROL INPUT 1 CONTROL INPUT 1 FUNCTION INPUT DECIMAL POINT OUTPUT SEGeOUTPUT FUNCTION INPUT 9 OUTPUT DIGIT 2 OUTPUT INPUTB SEG DIGIT 1 OUTPUT 4 DIGIT 3 OUTPUT SEGaOUTPUT DIGIT 4 OUTPUT 7 Vss 8 24 EXT OSC INPUT 23 DECIMAL POINT OUTPUT 22 SEG 9 OUTPUT 21 SEG e OUTPUT DIGIT 5 OUTPUT 9 SEG b OUTPUT 10 DlGIT60UTPUT 10 SEG C OUTPUT 11 DlGIT70UTPUT 11 DIGIT 8 OUTPUT 12 SEG f OUTPUT 12 FiESE'f INPUT 19 SEG d OUTPUT 13 16 DIGIT 7 OUTPUT FiESE'f INPUT 13 16 SEG c OUTPUT RANGE INPUT 14 15 DIGIT 8 OUTPUT RANGE INPUT 14 15 SEGfOUTPUT ICM7216D COMMON CATHODE (PDIP) TOP VIEW CONTROL INPUT r.M=ETAS~UmR~E~MnE~N=tmpROGRESS DIGIT 1 OUTPUT 3 DIGIT 3 OUTPUT DIGIT 2 OUTPUT 23 DECIMAL POINT OUTPUT DIGIT 4 OUTPUT 6 0 1 011: Vss 7 ffi~ !Z~ ;:)W DIGIT 5 OUTPUT DIGIT 6 OUTPUT 9 DlGIT70UTPUT 10 OZ (JW DIGIT 8 OUTPUT 11 FiESE'f INPUT 12 EX. DECIMAL POINT INPUT 13 16 SEG C OUTPUT RANGE INPUT 14 15 SEG f OUTPUT 13·23 " ICM7216A,ICM7216B,ICM7216D Functional Block Diagram EXT OSC INPUT OSC INPUT OSC OUTPUT ~ 3 OSC SELECT DECODER • DIGIT DRIVERS ~DI.GIT OUTPUTS (8) REFERENCE COUNTER +103 f---. l RANGE CONTROL LOGIC RANGE SELECT LOGIC r-RANGE INPUT +104 OR +10' 100Hz I 5 ~ INPUT CONTROL LOGIC 6 ....... ..... INPUT A - INPUTB (NOfE11 r+lEN +103~~NTER CL "4~~~ INPUT CONTROL LOGIC {4 {4 {4 ~4 INPUT EXT DP INPUT (NOTE 21 r--- 1 f---t 4 DECODER LOGIC 4 f+ SEGMENT DRIVER ~SEGMENT 0 UTPUTS (81 Q L...tD INPUT ~ CONTROL CL LOGIC OUTPUT (NOfE21 MAIN ~ FF LFN CONTROL LOGIC T r-CONTROL DP I ~ l LOGIC OVERFLOW DATA LATCHES AND STORE" OUTPUTMUX L FUNCTION INPUT (NOTE 1I J STORE AND RESET LOGIC 8 HOLD INPUT NOTES: 1. Function inpU1 and inpU1 B available on ICM7216A1B only. 2. Ext DP input and MEASUREMENT IN PROGRESS oU1pu1 available on ICM7216D only. 13-24 Specifications ICM7216A,ICM7216B,ICM7216D Absolute Maximum Ratings Thermal Information Maximum Supply Voltage (Voo - VSS> •••.••••••••.••••••• 6.5V Maximum Digit Output Current •••••••••••.•••••••.••• .4oomA Maximum Segment Output Current •••••••••••••••.••.•• 60mA Voltage On Any Input or Output Terminal (Note 1) •••••••.••.. (Voo +O.3V) to (Vss ~.3V) Storage Temperature Range ••••••••.•••••••• -6500 to +l50oC Lead Temperature (Soldering lOs) ..•••••.•••••••.••.• +3OOoC Thermal ReSistance Ceramic DIP Package ••••.•••••••••• Plastic DIP Package •••••.••.•.••••• Junction Temperature Ceramic Packages •••.•.•.•....•.•.•...........•. +175°C Plastic Packages ••••••••.•..••.••••••••••••••••• +1 SOOC Operating Temperature Range ••.••.•••••.••••• -25°C to +65°C CAUTION: Stresses aboII8 those listsd in ·Absolute Maximum Ratings· may cause permanent damage to the davies. This is a stress only rating and operation ol"'e device at these or any o"'er conditions above thass Indicated in the operational sscUons 01 this specification Is not Implied. Electrical Specifications voo = 5.0V, Vss = OV, TA = +25°C, Unless Otherwise Specified TEST CONDITIONS PARAMETER MIN TVP MAX UNITS - 2 5 rnA - 6.0 V - MHz - MHz ICM7216NB Operating Supply Current, 100 Display Off, Unused Inputs to Vss SupplyVottage Range (Voo -VsS>, VSUPPLY INPUT A, INPUT B Frequency at IMAX 4.75 Maximum Frequency INPUT A, Pin 28, IA(IIAX) Figure 9, Function = Frequency, Ratio, Unit Counter 10 Function = Period, TIme Interval 2.5 Figure 10 2.5 - 250 - - ns 10 - - MHz - - 100 kHz - IlS Maximum Frequency INPUT B, Pin 2, IB(MAX) Minimum Separation INPUT A to INPUT B TIme Interval Figure 1 Function Maximum Oscillator Frequency and External OsciUator Frequency, losc Minimum External OSCillator Frequency, lose 2000 - - MHz Oscillator Transconductance, gil Voo = 4.75V, TA = +65°C Multiplex Frequency, Illux losc= 10MHz - 500 Hz TIme Between Measurements lose = 10MHz - - 200 - ms Input Low Voltage, VINL - - 1.0 V Input High Voltage, VINH 3.5 - 100 400 - - Input Vo~ages: Pins 2, 13,25,27,28 Input Resistance to Voo Pins 13,24, RIN V1N = Voo -1.0V Input Leakage Pin 27,28,2, IILK Input Range 01 Change, dV1N/dt Supplies Well Bypassed 15 - V kO 20 j1A - mV/j1S ICM7216A Digit Driver: Pins 15, 16, 17, 19,20,21,22,23 High Output Current, IOH VOUT = Voo -2.0V -140 -180 - rnA Low Output Current, IOL Vour= Vss +1.0V - 0.3 - rnA Low Output Current, IOL Vour=Vss+l.5V 20 High Output Current, IOH VOUT = Voo -2.5V Segment Driver: Pins 4, 5, 6, 7,9,10,11,12 35 - rnA -100 - j1A V Multiplex Inputs: Pins 1,3,14 Input Low Voltage, V1NL - - 0.8 Input High Voltage, V1NH 2.0 - 50 100 - Input Resistance to Vss, RIN VIN = Vss +1.0V 13-25 V kO Specifications ICM7216A,·'CM7216B, ICM7216D Electrical Specifications voo =5.0V, Vas = ov, TA = +25°C, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN T'iP MAX UNITS - rnA ICM72168 Digit Driver: Pins 4, 5, 6, 7, 9, 10, 11, 12 VOUT=Vas+1•3V 50 75 VOUT = Voo -2.5V - -100 High Output Current, 10H VOUT = Voo -2.0V -10 Leakage Current, ISLK VOUT = Voo -2.5V - - Input Low Voltage, VINl - - Input High Voltsge, VINH Voo -0.8 Low Output Current, 10l High Output Current, 10H - p.A Segment Driver: Pins 15, 16, 17, 19,20,21,22,23 - mA 10 p.A Voo -2.0 V Multiplex Inputs: Pins 1, 3, 14 Input Resistance to Voo , RIN VIN = Voo -2.5V - - V 100 kO 360 - 2 5 - 6.0 V - - MHz 100 kHz - ).IS ICM7216D Operating Supply Current, 100 Display Off, Unused Inputs to Vss Supply Voltage Range (Voo -Vas), VSUPPLY INPUT A Frequency at IMAX Maximum Frequency INPUT A, Pin 28, IA(uAX) Figure 9 Maximum OSCillator Frequency and External Oscillator Frequency, losc 4.75 10 10 - Minimum External OSCillator Frequency, lose Oscillator Transconductsnce, gu Voo = 4.75V, TA = +85°C Multiplex Frequency, l MUX losc= 10MHz Time Between Measurements lose = 10MHz 2000 - - 500 200 rnA MHz - ms 1.0 V - V Hz Input Voltages: Pins 12, 27, 28 Input Low Voltsge, VINl - InpU1 High Voltsge, VINH 3.5 - 100 400 - 20 - mV/1lS Input Resistance to Voo Pins 12,24, RIN VIN=Voo-l.0V VOl=+O·4V 0.36 OU1put Current, Pin 2, IOH VOH = Voo -o.8V 265 - Input Rate 01 Change, dVIN/dt Supplies Well Bypassed - 15 Input Leakage, Pins 27, 28, IllK OU1put Current, Pin 2, 10l - kO p.A mA p.A Digit Driver: Pins 3, 4, 5, 6, 8, 9, 10, 11 Low Output Current, 10l VOUT= +1.3V 50 75 - rnA High Output Current, 10H VOUT = Voo -2.5V - 100 - p.A High Output Current, 10H VOUT = Voo -2.0V 10 15 Leakage Current, ISlK VOUT = Voo -2.5V - - 10 p.A Input Low Voltage, VINl - - Voo -2.0 V Input High Voltage, VINH Voo -o·8 - 100 360 Segment Driver: Pins 15, 16, 17, 19,20,21,22,23 rnA Multiplex Inputs: Pins I, 13, 14 Input Resistance to Voo, AjN VIN = Voo-l.0V - V kO NOTE: 1. The ICM7216 may be triggered Into a destructive latchup mode il either Input signals are applied before the power supply Is applied or If Input or outputs are lorced to voltsges exceeding Voo to Vas by more than 0.3V. 13-26 ICM7216A, ICM7216B, ICM7216D Timing Diagram INTERNAL STORE ~ --I 1--40ma n ~- :J nL - 30ma TO 40ma SOma INTERNAL RESET - --I , UPDATE FUNcnON: TIME INTERVAL ,"---io---l 7oma: • UPDATE : :111Oma TO 2OOma-"·.;..:..._ - PRIMING MEASUREMENT iN PROGRESS (INTERNAL ON 7216A1B) MEASUREMENT INTERVAL .... , ---.*:..._ - ',--------~-----~: INPUT A INPUTS , MEASURED INTERVAL (LAST) NOTE: 1. If range is set to 1 event, first and last measured Interval will coincide. FIGURE 1. WAVEFORMS FOR TIME INTERVAL MEASUREMENT (OTHERS ARE SIMILAR, BUT WITHOUT PRIMING PHASE) Typical Performance Curves 20r-------------------------------~ 'N' 300 15 200 !. tz w 0 C g 10 j ;:) fA (MAX) fa (MAX) PERIOD, nME INTERVAL MODES W II: ... 4.5 S Voo S 6.0V 100 5 TA. +25"c O~ 0 3 5 4 ______ ~_L~~ _ __L_ _ _ _ _ _ _ _ o 6 Voo-Vss(V) 2 VDo-VOUT (V) FIGURE 2. fA(MAX), fa(MAX) AS A FUNCTION OF SUPPLY FIGURE 3. ICM7216A TYPICAL IDiG VB VDD"VOUT 13-27 ~ 3 ICM7216A, ICM7216B, ICM7216D Typical Performance Curves (Continued) 30 80 4.5 S VDD S LOV TA=+25"C 80 20 l l I!I j 11 40 10 20 2 3 Voo-VourM VourM FIGURE 5. ICM7216A TYPICAL ISEG VI Your FIGURE 4. 1CM7216B .. ICM7216D TYPICAL ISEG VI Voo-VOUT Vour(V) VourM FIGURE 6. ICM7216B .. ICM7216D TYPICAL IaIGIT VI Your FIGURE 7. ICM7216A TYPICAL ISEG VI Your l j Vour(Y) FIGURE 8. ICM7216B .. ICM7216D TYPICAL IDIGIT VB Your 13·28 ICM7216A,ICM7216B,ICM7216D n:f.= Description COUNTED RANSlll0NS INPUTS A and B INPUTS A and B are digital inputs with a typical switching threshold of 2.0V at VDD = 5.0V. For optimum perlormance the peak-to-peak input signal should be at least 50% of the supply voltage and centered about the switching voltage. When these inputs are being driven from TTL logic, it is desirable to use a pullup resistor. The circuit counts high to low transitions at both inputs. (INPUT B is available only on ICM7216A and ICM7216B). I..... o.SV 50ns MIN Table 1 shows the functions selected by each digit for these inputs. TABLE 1. MULTtPLEXED INPUT FUNCTIONS FUNCTION DIGIT FUNCTiON INPUT (Pin ....F_re_q..;.ue_OCV...:..-_ _ _ _ _t-_DD_s1........j 3, ICM7216A and B Period Only) RANGE INPUT, Pin 14 CONTROL INPUT, Pin 1 r:---~-:-----+~-:--i Frequency Ratio 02 Time Interval Unit Counter 05 D4 Oscillator Frequency 03 O.01s11 Cycle 01 I--~~~------~~--~ O.1s110 Cycles 02 1s1l00 Cycles 03 1Dsll K Cycles Display Off D4 and D4 Hold Display Test OS 1MHz Select 02 01 03 External Oscmator Enable External Decimal Point Enable tA _ tF _10n. ~MEASURED_ IINTERVAL - MuHlplexed Inputs Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of operation is selected, since changes in voltage on the digit drivers can be capacitively coupled through the LED diodes to the multiplex inputs. For maximum noise immunity, a 10kn resistor should be placed in series with the multiplexed inputs as shown in the application circuits. --~ --' FIGURE 9. WAVEFORM FOR GUARANTEED MINIMUM fA(MAX) FUNCTION = FREQUENCY, FREQUENCY RATIO, UNIT COUNTER Note that the amplitude of the input should not exceed the device supply (above the VDD and below the Vss) by more than 0.3\1, otherwise the device may be damaged. The FUNCTION, RANGE, CONTROL and EXTERNAL DECIMAL POINT inputs are time multiplexed to select the function desired. This is achieved by connecting the appropriate Digit driver output to the inputs. The function, range and control inputs must be stable during the last half of each digit output, (typically 125I1S). The multiplexed inputs are active high for the common anode ICM7216A and active low for the common cathode ICM72168 and ICM7216D. 5On.MIN INPUT A 4.5V - - - - - " " ' " I-~~~.INPUT A OR 4.5V ---60flA. A 10kO pull-up resistor to Voo on the EQUAL or ZERO outputs is recommended for highest speed operation, and on the CARRY/BORROW output when it is being used for cascading. Figure 2 shows control outputs timing diagram. Multiplex SCAN Oscillator The on-board multiplex scan oscillator has a nominal freerunning frequency of 2.5kHz. This may be reduced by the addition of a single capacitor between the SCAN pin and the positive supply. Capacitor values and corresponding nominal oscillator frequencies, digit repetition rates, and loading times are shown in Table 1. SCAN INPUT ICM7217 R1 10kn SCAN INPUT ICM7217 R2 20kn c 1Mn O.01f11' FIGURE 10B. FIGURE 10A. CI)~ 10kn~+--lI'7~-;' ffie l-iCC Za: :::IW OZ Ow Cl 3kn SCAN INPUT ICM7217 2000 ov FIGURE 10C. FIGURE 10. BRIGHTNESS CONTROL CIRCUITS 13-45 I ICM7217 TABLE 1. ICM7217 MULTIPLEXED RATE CONTROL SCAN CAPACITOR NOMINAL OSCILLATOR FREQUENCY DIGIT REPETITION RATE ISTER pins; (see below). When functioning as outputs, the BCD I/O pins will drive one standard TTL load. Common anode versions have internal pull down resistors and common cathode versions have internal pull up resistors on the four BCD I/O lines when used as inputs. SCAN CYCLE TIME' (4 DIGITS) None 2.5kHz 625Hz 1.6ms 20pF 1.25kHz 300Hz 3.2ms 90pF 600Hz 150Hz Bms LOADing the COUNTER and REGISTER The internal oscillator output has a duty cycle of approxi· mately 25:1, providing a short pulse occurring at the oscillator frequency. This pulse clocks the four-state counter which provides the four multiplex phases. The short pulse width is used to delay the digit driver outputs, thereby providing interdigit blanking which prevents ghosting. The digits are scanned from MSD (04) to LSD (01). See Figure 1 for the display digit multiplex timing. During load counter and load register operations, the multiplex oscillator is disconnected from the SCAN input and is allowed to free-run. In all other conditions, the oscillator may be directly overdriven to about 20kHz, however the external oscillator signal should have the same duty cycle as the internal signal, since the digits are blanked during the time the external signal is at a positive level (see Figure 1). To insure proper leading zero blanking, the Interdigit blanking time should not be less than about 2flS. Overdriving the oscillator at less than 200Hz may cause display flickering. The display brightness may be altered by varying the duty cycle. Figure 10 shows several variable-duty·cycle oscillators suitable for brightness control at the ICM7217 SCAN input. The inverters should be CMOS CD4000 series and the diodes may be any inexpensive device such as IN914. Counting Control, STORE, Fi'ESE'f As shown in Figure 2, the counter is incremented by the ris· ing edge of the COUNT INPUT signal when UP/DOWN is high. It is decremented when UP/DOWN is low. A Schmitt trigger on the COUNT INPUT provides hysteresis to prevent double triggering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited duro ing reset and load counter operations. The S'fC5RE pin controls the internal latches and consequently the signals appearing at the 7-Segment and BCD outputs. Bringing the STORE pin low transfers the contents of the counter into the latches. The counter is asynchronously reset to 0000 by bringing the RESET pin low. The circuit performs the reset operation by forcing the BCD input lines to zero, and "presetting" all four decades of counter in parallel. This affects register loading; if LOAD REGISTER is activated when the RESET input is low, the register will also be set to zero. The STORE, RESET and UP/DOWN pins are provided with pullup resistors of approximately 75k!}. BCDVO Pins The BCD I/O port provides a means of transferring data to and from the device. The ICM7217 versions can multiplex data into the counter or register via thumbwheel switches, depending on inputs to the LOAD COUNTER or LOAD REG- The BCD I/O pins, the LOAD COUNTER (LC), and LOAD REGISTER (LR) pins combine to provide presetting and compare functions. LC and LR are 3-level inputs, Qeing selfbiased at approximately %Voo for normal operation. With both LC and LR open, the BCD I/O pins provide a multiplexed BCD output of the latch contents, scanned from MSD to LSD by the display multiplex. When either the LOAD COUNTER (Pin 12) or LOAD REGISTER (Pin 11) is taken low, the drivers are turned off and the BCD pins become high-impedance inputs. When LC is connected to V oo , the count input is inhibited and the levels at the BCD pins are multiplexed into the counter. When LR is connected to V oo , the levels at the BCD pins are multiplexed into the register without disturbing the counter. When both are connected to V oo , the count is inhibited and both register and counter will be loaded. The LOAD COUNTER and LOAD REGISTER inputs are edge-triggered, and pulsing them high for 500ns at room temperature will initiate a full sequence of data entry cycle operations (see Figure 3). When the circuit recognizes that either or both of the LC or LR pins input is high, the multiplex oscillator and counter are reset (to 04). The internal oscillator is then disconnected from the SCAN pin and the preset circuitry is enabled. The oscillator starts and runs with a frequency determined by its internal capacitor, (which may vary from chip to chip). When the chip finishes a full 4 digit multiplex cycle (loading each digit from 04 to 03 to 02 to 01 in turn), it again samples the LOAD REGISTER and LOAD COUNTER inputs. If either or both is still high, it repeats the load cycle, If both are floating or low, the oscillator is reconnected to the SCAN pin and the chip returns to normal operation. Total load time is digit "on" time multiplied by 4. If the Digit outputs are used to strobe the BCD data into the BCD 1/ inputs, the input must be synchronized to the appropriate digit (Figure 3). Input data must be valid at the trailing edge of the digit output. o When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pins go to the high impedance state, and the segment and digit drivers are turned off. This allows the display to be used for other purposes and minimizes power consumption. In this display off condition, the circuit will continue to count, and the CARRY/BORROW, EQUAL, ZERO, UP/DOWN, FiESEi' and S'i"5RE functions operate as normal. When LC is connected to ground, the BCD I/O pins are forced to the high impedance state without disturbing the counter or register. See "Control Input Definitions" (Table 2) for a list of the pins that function as tri-state self-biased inputs and their respective operations. Note that the ICM7217 and ICM7217B have been designed to drive common anode displays. The BCD inputs are high true, as are the BCD outputs. 13-46 ICM7217 ~D40611 INPUT 1N4148 OUTPUT ~ ~D40611 INPUT 1N4148 OUTPUT ,l1li INPUT OUTPUT INPUT OUTPUT High High High Disconnected Low Disconnected Low High FIGURE 11A. CMOS INVERTER FIGURE 11 B. CMOS INVERTER CD4602B CD74HC03 INPUT A D INPUTS ~ INPUT A OUTPUT INPUTS OUTPUT INPUTB INPUT A OUTPUT INPUTB INPUT A OUTPUT High High Low High High Disconnected High Low Disconnected High Low Disconnected Low High Disconnected Low High High Low Low Disconnected FIGURE 11C. CMOS OPEN DRAIN Low Low Low FIGURE 11D. CMOS TRI-STATE BUFFER FIGURE 11. DRIVING 3-LEVEL INPUTS OF ICM7217 ---------.----------Voo SOlin DN DIGIT UNE ---'tIVv-~ DISPLAY 60ren DNDlGlTUNE CONTROL ~ VOO ICM7217 ICM72178 FIGURE 12A. COMMON ANODE FIGURE 128. COMMON CATHODE FIGURE 12. FORCING LEADING ZERO DISPLAY .. _--------, DIGIT DRIVE • ••• •• • : ----------, •• •• •• Voo · SEGMENT DRIVE • 1CM7217 1CM7217 1CM7217S ICM7217C SEGMENT DRIVE VDD ·· CI)~ ffie : • l-iC za: :;)w oZ, (,)W CJ DIGIT DRIVE •• ••• •• · ._---_..... _...! •• ••• • · • Vas ._-----_ ......! FIGURE 13A. COMMON ANODE DISPLAY Vas FIGURE 138. COMMON CATHODE DISPLAY FIGURE 13. DRIVING HIGH CURRENT DISPLAYS 13-47 ICM7217 VDD=5V VDD=5v Lr-v-~ .,J;.. 35. 04 LCODISPLAY 03 37-40 DODD ¢= L' L' L' L' ICM7211 2-26 / 28 SEGMENTS ANO BACKPLANE 34 33 32 02 01 31 30 OB3 29 OB2 28 OB1 27 OBO 4~~ 5 6 7 ~ ~~ H 12 48 C A~ ~ ~ A.. ~ A~ A II- A~ A A ~ A A~ 28 D1 D2 27 :..!2... ICM7217 03 26 IJI D4 25 A y '0 Y 1 ~ STORE-L REsEr....l!.. A OC .1L 1. COUNT-L UPIDN AI. 4a 2s 8 C 10kO-20kO FIGI,IRE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES The ICM7217A and the ICM7217C are used to drive common cathode displays, and the BCD inputs are low true. BCD outputs are high true. Notes on Thumbwheel Switches and Multiplexing As it was mentioned, the ICM7217 is basically designed to be used with thumbwheel switches for loading the data to the device. See Figure 14 and Figure 17. The thumbwheel switches used with these circuits (both common anode and common cathode) are TRUE BCD coded; i.e. all switches open corresponds to 0000. Since the thumbwheel switches are connected in parallel, diodes must be provided to prevent crosstalk between digits. In order to maintain reasonable noise margins, these diodes should be specified with low forward voltage drops (IN914). Similarly, if the BCD outputs are to be used, resistors should be inserted in the Digit lines to avoid loading problems. Output and Input Restrictions LOAD COUNTER and LOAD REGISTER operations take 1.6ms typical (5ms maximum) after LC or LR are released. During this load period the EQUAL and ZERO outputs are not valid (see Figure 3). Since the Counter and register are compared by XOR gates, loading the counter or register can cause erroneous glitches on the EQUAL and ZERO outputs when codes cross. LOAD COUNTER or LOAD REGISTER, and RESEi' input can not be activated at the same time or within a short period of each other. Operation of each input must be delayed 1.6ms typical (5ms fo(guaranteed proper operation) relating to the preCeding one. Counter and register can be loaded together with the same value if LC and LR inputs become activated exactly at the same time. Notice the setup and hold time of UP/DOWN input when it is changing during counting operation. Violation of UP! DOWN hold time will result in incrementing or decrementing the counter by 1000,100 or 10 where the preceding digit is transitioning from 5 to 6 or 6 to 5. The RESET input may be susceptible to noise if its input rise time is greater than about 500l1s This will present no problems when this input is driven by active devices (i.e., TTL or CMOS logic) but in hardwired systems adding virtually any 13-48 ICM7217 capacitance to the RESET input can cause trouble. A simple circuit which provides a reliable power-up reset and a fast rise time on the RESET input is shown on Figure 11. ~~----~----,--------Voo When using the circuit as a programmable divider (+ by n with equal outputs) a short time delay (about 11-1s) is needed from the EQUAL output to the RESET input to establish a pulse of adequate duration. (See Figure 16). REsE'i' INPUT ICM7217 10kO 5kO --------~~~-------V_ When the circuit is configured to reload the counter or register with a new value from the BCD lines (upon reaching EQUAL). loading time will be digit "on" time multiplied by four. If this load time is longer than one period of the input count. a count can be lost. Since the circuit will retain data in the register. the register need only be updated when a new value is to be entered. RESET will not clear the register. FIGURE 15. POWER ON RESET Voo 33k II 47pF EaiiAL o------W....-----.j-~--------_oo RESET FIGURE 16. EQUAL TO"fiEsEi' DELAY Test Circuit III!!IIIII. C - - - - , COMMON ANODE DISPLAY ~ llIUMBWHEEL SWITCHES D2 01 BCDU088~~~~~~~~~----------~ BCDU04s BCD UO 2s DISPLAY CONTROL 99991----------f6l BCDU01S~::::::::::::~~============Fs tf) tf)a: COUNT INPUT - a:O ~~ Za: OZ UW CJ ;:)W +5V vss 13-49 ICM7217 Applications Tape Recorder Position Indicator/controller 3-levellnput8 ICM7217 has three Inputs with 3-level logic states; High. Low and Disconnected. These inputs are: LOAD REGISTER/OFF, LOAD COUNTERII/O OFF and DISPLAY CONT. The circuit in Figure 20 shows an application which uses the up/down counting feature of the ICM7217 to keep track of tape pOSition. This circuit is representative of the many applications of up/down counting in monitoring dimensional position. The circuits illustrated on Figure 11 can be used to drive these inputs in different applications. 'E'QijAL and ZERO outputs are used to control the recorder. FIxed Decimal Point In the common anode versions, a fixed decimal point may be activated by connecting the DP segment lead from the appropriate digit (with separate digit displays) through a 390 series resistor to Ground. With common cathode devices, the DP segment lead should be connected through a 750 series resistor to Voo. To force the device to display leading zeroes after a fixed decimal point. use a bipolar transistor and base resistor in a configuration like that shown in Figure 12 with the resistor connected to the digit output driving the DP for left hand DP displays, and to the next least significant digit output for right hand DP display. Driving Larger Displays For displays requiring more current than the ICM7217 can provide, the circuits of Figure 13 can be used. LCD Display Interface The low-power operation of the ICM7217 makes an LCD interface desirable. The Harris ICM7211 4 digit BCD to LCD display driver easily interfaces to the ICM7217 as shown In Figure 14. Total system power consumption is less than 5mW. System timing margins can be improved by using capaCitance to ground to slow down the BCD lines. The 10kn - 20kn resistors on the switch BCD lines serve to isolate the switches during BCD output. Unit Counter with BCD Output The simplest application of the ICM7217 is a 4 digit unit counter (Figure 18). All that is required is an ICM7217, a power supply and a 4 digit display. Add a momentary switch for reset, an SPOT center-off switch to blank the display or view leading zeroes. and one more SPOT switch for up/ down control. Using an ICM7217A with a common-cathode calculator-type display results in the least expensive digital counter/display system available. In the tape recorder application, the LOAD REGISTER, To make the recorder stop at a particular point on the tape, the register can be set with the stop point and the EQUAL output used to stop the recorder either on fast forward, play or rewind. To make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. Resetting the counter at the starting point of the tape, a few feet from the end of the leader. allows the ZERO output to be used to stop the recorder on rewind, leaving the leader on the reel. The 1MO resistor and 0.004711F capacitor on the COUNT INPUT provide a time constant of about 5ms to debounce the reel switch. The Schmitltrigger on the COUNT INPUT of the ICM7217 squares up the signal before applying it to the counter. This technique may be used to debounce switchclosure inputs in other applications. Precision Elapsed Time/Countdown Timer The circuit in Figure 21 uses an ICM7213 preCision one minute/one second timebase generator using a 4.1943MHz crystal for generating pulses counted by an ICM7217B. The thumbwheel switches allow a starting time to be entered into the counter for a preset-countdown type timer, and allow the register to be set for compare functions. For instance, to make a 24-hour clock with BCD output the register can be preset with 2400 and the EQUAL output used to reset the counter. Note the 10k resistor connected between the LOAD COUNTER terminal and Ground. This resistor pulls the LOAD COUNTER input low when not loading, thereby inhibiting the BCD output drivers. This resistor should be eliminated and SW4 replaced with an SPOT center-off switch if the BCD outputs are to be used. This technique may be used on any 3-level input. The 100kO pullup resistor on the count input is used to ensure proper logic voltage swing from the ICM7213. For a less expensive (and less accurate) timebase, an ICM7555 timer may be used in a configuration like that shown in Figure 19 to generate a 1Hz reference. Inexpensive Frequency Counter/ Tachometer 8-D191t Up/down Counter This circuit uses the low power ICM7555 (CMOS 555) to generate the gating, STORE and RESET signals as shown in Figure 19. To provide the gating signal, the timer is configured as an a stable multivibrator, using RA, Re and C to provide an output that is positive for approximately one second and negative for approximately 300jJ.S - 500jJ.S. The positive waveform time is given by twp 0.693 {RA + Re)C while the negative waveform is given by two = 0.693 ReC. The system is calibrated by using a 5MO potentiometer for RA as a "coarse" control and a 1kn potentiometer for Re as a "fine" control. CD40106Bs are used as a monostable multivibrator and reset time delay. This circuit (Figure 22) shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked, the Q output of the flip flop goes high and turns on the NPN transistor, thereby inhibiting leading zero blanking on the.low order counter. = a It is possible to use separate thumbwheel switches for presetting, but since the devices load data with the oscillator free-running, the multiplexing of the two devices is difficult to synchronize. 13-50 ICM7217 Precision Frequency CounterlTachometer The circuit shown in Figure 23 is a simple implementation of a four digit frequency counter, using an ICM7207A to provide the one second gating window and the STORE and RESET signals. In this configuration, the display reads hertz directly. ':'ith P~n 11 of the ICM7027A connected to Voo , the gating time Will be 0.1 s; this will display tens of hertz at the least significant ~igit. For shorter gating times, an ICM7207 may b~ us~d (with a 6.5536MHz crystal), giving a 0.01 s gating With Pin 11 connected to Voo , and a O.ls gating with Pin 11 open. To implement a four digit tachometer, the ICM7207A with one second gating should be used. To get the display to read directly in RPM, the rotational frequency of the object to be measured must be multiplied by 60. This can be done electronically using a phase-locked loop, or mechanically by using a disc rotating with the object with the appropriate number of holes drilled around its edge to interrupt the light from an LED to a photo-dector. For faster updating, use O.ls gating, and multiply the rotational frequency by 600. Auto-tare System This circuit uses the count-up and count-down functions of the ICM7217, controlled via the EQuAL and ZERO outputs, to count in SYNC with an ICL7109A and ICL7109D Converter as shown in Figure 24. By RESETing the ICM7217 on a "tare" value conversion, and STORE-ing the result of a true value conversion, an automatic fare subtraction occurs in the result. The ICM7217 stays in step with the ICL71 09 by counting up and down between 0 and 4095, for 8192 total counts, the same number as the ICL7109 cycle. See applications note No. A047 for more details. TABLE 2. CONTROL INPUT DEFINITIONS ICM7217 INPUT TERMINAL VOLTAGE FUNCTION STORE 9 Voo (or floating) Vss Output Latches Not Updated Output Latches Updated UP/DOWN 10 Voo (or floating) Vss Counter Counts Up Counter Counts Down RESET 14 Voo (or floating) Vss Normal Operation Counter Reset LOAD COUNTER! 12 Unconnected Voo Vss Normal Operation Counter Loaded with BCD data BCD Port Forced to Hi Z CondHion LOAD REGISTER! OFF 11 Unconnected Voo Vss Normal Operation Register Loaded with BCD Data Display Drivers Disabled; BCD Port Forced to Hi Z Condition, mpx Counter Reset to 04; mpx Oscillator Inhibited DISPLAY CONTrol 23 Common Anode 20 Common Cathode Unconnected Normal Operation Segment Drivers Disabled Leading Zero Blanking Inhibited iiC5""OFF Voo Vss U) U)II: 11:0 ~~ ZII: :::;)W OZ (,)W c.:J 13-51 ICM7217 TOD4STROBE TOD1 STROBE TO D4 STROBE TOD1STROBE IN914OR EQUIVALENT .. 842 842 TO BCD INPUTS OF ICM7217,ICM7217B TO BCD INPUTS OF ICM7217A, ICM7217C FIGURE 17. THUMBWHEEL SWlTCtUDIODE CONNECTIONS 21-23I--------r7~SE=GM=E::-:NTS="1 25-28 CARRY ZERO _w{ COMMON CATHODE ...- - - - - - - - -.... LED DISPLAY DODO " 5 L' L' L' L' 6 7 8 COUNT INPUT ii'OiiE 9 ICM7217A 24t----......-00 Voo DISPLAY 20 CONTROL ~lt:"'~L INHIBlTLZB 1 9 t - - - -... 111~4_ _ _~15~-~18~-------~CKmr-~ RESET~ 4D100 FIGURE 18. UNIT COUNTER 13-52 ICM7217 V 24 DD t ))--1--------!STORE LED DISPLAY ICM7217 ~~-~t:r::>----~1COUNT t ~ ~LI I L _I , Vss 20 GND INVERTERS: CD401 06B NANDS: CD4011B COUNT INPUT - - - - ' FIGURE 19A. r GATE 1. 3001'8 -i n n 21 U l2 FIGURE 19B. FIGURE 19. INEXPENSIVE FREQUENCY COUNTER COMMON CATHODE LOGIC TO GENERATE RECORDER CONTROL SIGNALS n,,,,,... REEL SWITCH CLOSED ONCEIREV \ 0000 Ll Ll Ll Ll 1M +~--~--------~ r-~V~oo~FO~RW~A~R~D~O-o~-~-1UProowN 0.0047I'F ..·i'. . . BLANK NORMAL o INHIBIT LZB 1.. Voo LOADCTR 4 DIGITS FIGURE 20. TAPE RECORDER POSITION INDICATOR 13-53 we a: a: l-icC za: :;)w! oz (,)W o LOAD REG t/)t/) CJ ICM7217 VDD 1001( mm} =Ll:nO 30pF - TOLOOICGENERAnNG SIGNALS FOR CONTROL OF EXTERNAL EQUIPMENT 4.1943MHz CRYSTAL Rs<75Q DIGITS 4 THUMBWHEEL SWITCHES 0000 BLANK '~=t=S~W8~Voo ~Brr ELAPSED COUNTDOWN VDD,------_ LOAD SET PT. DISPLAY OFF VDD------_ Ll Ll Ll Ll +/ COMMON ANODE LED DISPLAY 7 VDD PRESET SW4 RESET ~ ICM7217 SWS-'- FIGURE 21. PRECISIONS TIMER 13-54 SEGMENTS ICM7217 COMMON-ANODE LED DISPLAY BBBB~ ~ l,DDD DDD~ COUNT INPUT CARAYIBORROW .;;C.;.;AR;.;;AY.;.;...;;OUT;';;';"_ _-+_-I~ ~ 4DJGr1'S , 4 DJGrI'S ' 7 SEGMENTS -B-C-D-OU-T-P-UT-S--+~ '4-14 " -7 )'D1 HIGH ORDER DIGITS BCOOUTPUTS HIGHO~DIGITS 24 20 1CM7217 V+~N~8 -11 ' 15-18 10 21,22 I--V+ 7 SEGIoENTS " .. 4 JA r'7:' >'1B~ 14 1CM7217 CD4011 HIGH ORDER 15 -18 21,22 LOW ORDER v+ ...... &OlIO &Oke .. FIGURE 22. 8 DIGIT UPIDOWN COUNTER 13-55 1--+----' ICM7217 Y+. 5Y !22pF! 22pF 10k.Q ..., '- 2 ~ r-4 HDI-'" 1-5 -f BCD OUT 14 - _ .---: 13 ---:-v-25-28 ~ 4 DIGITS 4 24 S J l- 6 DlIDD 7 DDL1D ICM7207A 10 C~~:S~J:E ICM7217 tCOUNT 6 'S"i'!5Rr CRYSTAL 1/4 f. &.24288MHz 8 II 15-111 21,22 '7SEGMENTS CD4011 RS=7SO J!imT 14 201} .-L INPUT FIGURE 23. PRECISION FREQUENCY COUNTER (MHZ MAXIMUM) +SY 400mY 4 DIGIT COMMON ANODE LED DISPLAY FULL SCALE INPUT + 0.11Lf .# +BY 100K TARE FIGURE 24. AUTO-TARE SYSTEM FOR AID CONVERTER 13-56 U"l,L lLIJD ICM7224 41/ 2 Digit LCD Display Counter December 1993 Features Description • High Frequency Counting· Guaranteed 15MHz, Typl· cally 25M Hz at 5V The ICM7224 device is a high-performance CMOS 41/ 2 digit counter, including decoder, output latch, display driver, count inhibit, leading zero blanking, and reset circuitry. • Low Power Operation. Typically Less Than 100llW Quiescent • S1'6RE and RESET Inputs Permit Operation as Fre- quency or Period Counter • True COUNT INHIBIT Disables Rrat Counter Stage • 'CAR'RY Output for cascading Four·Dlglt Blocks • Schmltt·Trlgger on the COUNT Input Allows Operation In Noisy Environments or with Slowly Changing Inputs • Leading Zero Blanking INput and OUTput for Correct Leading Zero Blanking with Cascaded Devices • Provides Complete Onboard Oscillator and Divider Chain to Generate Backplane Frequency, or Back· plane Driver May be Disabled Allowing Segments to be Slaved to a Master Backplane Signal Pinout TOP VIEW 1 These devices also incorporate several features intended to simplify cascading four-digit blocks. The CARRY output allows the counter to be cascaded, while the Leading Zero Blanking INput and OUTput allows correct Leading Zero Blanking between four-decade blocks. The BackPlane driver of the LCD devices may be disabled, allowing the segments to be slaved to another backplane Signal, necessary when using an eight or twelve digit, single backplane display. These devices provide maximum count of 19999. The display drivers are not of !he multiplexed type and each display segment has its own individual drive pin, providing high quality display outputs. (PDlP, CDIP) VDO The counter section provides direct static counting, guaranteed from DC to 15MHz, using a 5V ± 10% supply over the operating temperature range. At normal ambient temperatures, the devices will typically count up to 25M Hz. The COUNT input is provided with a Schmitt trigger to allow operation in noisy environments and correct counting with slowly changing inputs. The COUNT INHIBIT, STORE and RESET inputs allow a direct interface with the ICM7207 and ICM7207A to implement a low cost, low power frequency counter with a minimum component count. D1 E1 C1 Q1 81 Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE A1 OSCILLATOR Vss i'I'6iil RESET ICM72241PL -25°C to +85°C 40 Lead Plastic DIP ICM7224RIPL t -25°C to +85°C 40 Lead Plastic 01 P t "R" Indicates Device With Reversed Leads Configuration. COUNT E2 COUNT INHIBIT G2 LZBOUT F2 LZBIN A3 CAiiIiV B3 1/2 - DIGIT C3 F4 D3 G4 E3 E4 G3 D4 F3 C4 A4 54 CAUTION: These devices are sensRiva to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 13-57 File Number 3168 ICM7224 Functional Block Diagram LSD DIGIT 1 SEGMENT OUTPUTS DIGIT 2 SEGMENT OUTPUTS DIGIT 3 SEGMENT OUTPUTS DIGIT 4 SEGMENT OUTPUTS MSD l/z DIGIT OUTPUT STORE - -.... LEADING ZERO BLANKING OUTPUT -===;1 COuNT" iNiliiii'i' r COUNT INPUT RESET------~--~~--+----+-~~~---~--~--~~~-~ OSClUATOR INPUT H~----------------------- BP INPUT/OUTPUT 13-58 Specifications ICM7224 Absolute Maximum Ratings Thermal Information Supply Voltage (Voo - Vss) ••••••••••••••.•••••••••••••• 6.SV Input Voltage (Any Terminal) (Note 1). • .• (Voo + 0.3V) to (Vss - 0.3V) Storage Temperature Range ••••..•••••••••.• -65°C to +1SO"C Lead Temperature (Soldering, 10s) ••••••••••••••••••• +300"C Thermal ReSistance 8JA Plastic Package. . . . • . . • • • • • . • . • • • • . • • • . . . • . .. sO"cm Operating Temperature Range ••••••••••••••••• -2SoC to +8SoC Junction Temperature •••.•••••••••••••••••••••••••. + 150°C CAUTION: Stresses abo... those listed in "Absolute Maximum RaUngs- may cause pBrmanent damage to the davlce. This is a stress only raUng and operation of the device at these or any other conditions abo... those indicated in the operational seefions of this specification Is not ImpHsd. Electrical Specifications voo = SV, vss= OV, TA = +2SoC, Unless Otherwise Indicated PARAMETER Operating Current, TEST CONDITIONS MIN TYP MAX UNIT - 10 SO IlA 3 - 6 V ±2 ±10 IlA O.S - IJS 1.5 - IJS 19 - kHz Test Circuit, Display Blank 100 Operating Supply Voltage Range (VOO · VSS>' VSUPPlY OSCILLATOR Input Current, losci Segment Rise/Fall Time, ~, - Pin 36 It: CLOAO = 200pF BackPlane Rise/Fall Time, ~, '" - CLOAD = SOOOpF Oscillator Frequency, losc Pin 36 Floating Backplane Frequency, I BP Pin 36 Floating - 1S0 Input Pullup Currents, Ip Pins 29, 31,33, 34, VIN = Voo - 3V - 10 Input High Voltage, VIH Pins 29,31,33,34 3 Input Low Voltage, VIL Pins 29,31,33,34 - - COUNT Input Threshold, VCT - 2 COUNT Input Hysteresis, VCH - O.S - IlA - V 1 V - V Hz V Output High Current, IOH CARRY Pin 28 Leading Zero Blanking OUT Pin 30 VOUT = Voo - 3V -350 -500 - IlA Output Low Current, IOL CARRY Pin 28 Leading Zero Blanking OUT Pin 30 VOUT =+3V 3S0 500 - IlA Count Frequency, lCOUNT 4.SV < Voo < 6V 1S MHz - IJS 0 STORE, RESET Minimum Pulse Width, Is, ~ 3 - NOTE: 1. Due to the SCR structure Inherent In the CMOS process, connecting any terminal to voltages greater than Voo or less than Vss may cause destructive device latchup. For this reason, It is recommended that no inputs Irom sources operating on a different power supply be applied to the device belore Its supply is established, and that in multiple supply systems, the supply to the ICM7224 be turned on first Timing Waveforms OSCILLATOR FREQUENCY .nr1.nnnr1r1.nr~ BACKPLANE --------~~ INPUTIOUTPUT OFF SEGMENTS r-- 128 CYCLES ::::l L- .'.UCY~~ - - - - ; I4CYCLES ____r- ON SEGMENTS FIGURE 1. ICM7224 DISPLAY WAVEFORMS 13-59 ICM7224 Typical Performance Curves 30 2S ~ !iw D~VlC~S r r J:D • .:sST DISPLAY BLANK PIN 38 OPEN 20 .f a: a: 15 , V TAa+2S"C tx: ~ 10 ./. ~ :::) II> ~~ 5 ~ I.... 2 N 100 /11' ~ :z: !~ • '/ '" I I 4 I I :s / e. 10 I I 6 1 7 ~~ ,,~ VSUPPLya4V II ) I .~ ~ VSUPPLy-3V II 10 1 100 1000 FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF OSCILLATOR CAPACITOR Cose 10 I SINE WAVE INPUT SWINGING FULL SUPPLY -- V+=5V TAa+WC 1/ ~ _35 ". i""" 130 I ,......0,;;: Cosc(pF) FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 40 VSUPPLy-6V ~ SUPPLY VOLTAGE (V) 45 aSv II ~ F= = 5 VSUPPLY , TA-+7O"C r 3 ~~ /~ TA--2O"C :::) It: I I LCD DEVICES TA-+WC 'I I u ~ 1000 ~Rc'u1T 2S " 20 / ~I V ~ I"'" V ~ TA--2o"C TA-:!:'C l..-- joo"'" ~ TA,"+70oC_ ..,.1"'" i,....ooo" l..,..oo" .,1"'" """-= ~ 15 5 4 0.01 6 1kHz ~ i-'" 10kHz SUPPLY VOLTAGE M FIGURE 4. MAXIMUM COUNT FREQUENCY (TYPICAL) AS A FUNCTION OF SUPPLY VOLTAGE 100kHz 1MHz jCOUNT 10MHz FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF COUNT FREQUENCY TABLE 1. CONTROL INPUT DEFINITIONS TERMINAL 29 INPUT FUNCTION VOLTAGE Leading Zero Blanklng Voo or Floating Leading Zero Blanking·Enabled INput Vss Leading Zeroes Displayed 31 COUNT INHIBIT Voo or Floating Counter Enabled Vss Counter Dlsablad 33 RESET Voo or Floating Inactive Vlls Counter Reset to 0000 Voo or Floating Output Latches not Updated Vss Output Latches Updated 34 STORE 100MHz 13-60 ICM7224 Control Input Definitions In Table 1, Voo and Vss are considered to be normal operating input logic levels. Actual input low and high levels are specified in the Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. Detailed Description The ICM7224 provides outputs suitable for driving conventional 41/ 2 digit by seven segment LCD displays. It includes 29 individual segment drivers, a backplane driver, and a selfcontained oscillator and divider chain to generate the backplane frequency (See Functional Block Diagram). The segment and backplane drivers each consist of a CMOS inverter, with the n-channel and p-channel devices ratioed to provide identical on resistances, and thus equal rise and fall times. This eliminates any D.C. component which could arise from differing rise and fall times, and ensures maximum display life. The backplane output can be disabled by connecting the OSCILLATOR input (pin 36) to Vss. This synchronizes the 29 segment outputs directly with a signal input at the BP terminal (pin 5) and allows cascading of several slave devices to the backplane output of one master device. The backplane may also be derived from an external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave device will represent a load of approximately 200pF (comparable to one additional segment). The limitation on the number of devices that can be slaved to one master device backplane driver is the additionalload represented by the larger backplane of displays of more than four digits, and the effect of that load on the backplane rise and fall times. A good rule of thumb to observe in order to minimize power consumption, is to keep the rise and fall times less than about 5 microseconds. The backplane driver of one device should handle the back-plane to a display of 16 one-half-inch characters without the rise and fall times exceeding 511S (i.e., 3 slave devices and the display backplane driven by a fourth master device). It is recommended that if more than four devices are to be slaved together, that the backplane Signal be derived externally and all the ICM7224 devices be slaved to it. This external backplane signal should be capable of driving very large capacitive loads with short (1-2I1S) rise and fall times. The maximum frequency for a backplane signal should be about 150Hz, although this may be too fast for optimum display response at lower display temperatures, depending on the display used. The onboard oscillator is designed to free run at approximately 19kHz, at microampere power levels. The oscillator frequency is divided by 126 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running. The oscillator frequency may be reduced by connecting an external capacitor between the OSCillator terminal (pin 36) and Voo; see the plot of oscillatorlback-plane frequency in "Typical Performance Curves· for detailed information. The oscillator may also be overdriven if desired, although care must be taken to insure that the backplane driver is not disabled during the negative portion of the overdrlving signal (which could cause a D.C. component to the display). This can be done by driving the OSCILLATOR input between the pOSitive supply and a level out of the range where the backplane disable is sensed, about one fifth of the supply voltage above the negative supply. Another technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsecond. The backplane disable sensing circuit will, not respond to signals of this duration. Counter Section The ICM7224 implements a four-digit ripple carry resettable counter, including a Schmitt trigger on the COUNT input and a CARRY output. Also included is an extra D-type flip-flop, clocked by the CARRY signal which controls the half-digit segment driver. This output driver can be used as either a true half-digit or as an overflow indicator. The counter will increment on the negative-going edge of the signal at the COUNT input, while the CARRY output provides a negativegoing edge following the count which increments the counter from 9999 to 10000. Once the half-digit flip-flop has been clocked, it can only be reset (with the rest of the counter) by a negative level at the RESET terminal, pin 33. However, the four decades will continue to count in a normal fashion after the half-digit is set, and subsequent CARRY outputs will not be affected. A negative level at the COUNT INHIBIT input disables the first divide-by-two in the counter chain without affecting its clock. This provides a true inhibit, not sensitive to the state of the COUNT input, which prevents false counts that can result from using a normal logic gate to prevent counting. Each decade of the counter directly drives a four-ta-seven segment decoder which develops the required outP~ The output data is latched at the driver. When the STORE pin is low, these latches are updated, and when it is high or floating, the latches hold their contents. The decoders also include zero detect and blanking logic to provide leading zero blanking. When the Leading Zero Blanking INput is floating or at a poSitive level, this circuitry is enabled and the device will blank leading zeroes. When it is low, or the half-digit is set, leading zero blanking is inhibited, and zeroes in the four ~igits will be displayed. The Leading Zero Blanking OUTput is provided to allow cascaded devices to blank leading zeroes correctly. This output will assume a positive level only when all four digits are blanked; this can only occur when the Leading Zero Blanking INput is at a positive level and the half-digit is not set. For example, in an eight-decade counter with overflow using two ICM7224 devices, the Leading Zero Blanking OUTput of the high order digit would be connected to the Leading Zero Blanking INput of the low order digit device. This will assure correct leading zero blanking for all eight digits. 13-61 (/)~ ffi~ !-icC Zct ::)w OZ (,)W CJ ICM7224 The STORE•..RESET. COUNT INHIBIT. and Leading Zero Blanking INputs are provided With pullup devices. so that they may be left open when a positive level is desired. The CARRY and Leading Zero Blanking OUTputs are suHable for interfacing to CMOS logic in general. and are specifically designed to allow cascading of the devices in four-digit blocks. Applications Figure 8 shows an 8 digit precision frequency counter. The circuit uses two ICM7224s cascaded to provide an 8 digit display. Backplane output of the second device is disabled and is driven by the first device. The 1/2 digit output of the second device is used for overflow indication. The input signal is fed to the first device and the COUNT input of the second is driven by the ~ output of the first. Notice that leading zero blanking is controlled on the second device and the LZB OUT of the second one is tied to LZB IN of the first one. An ICM7207A device is used as a timebase generator and frequency counter controller. It generates count window. store and reset signals which are directly compatible with ICM7224 inputs (notice the need for an inverter at COUNT INHIBIT input). The ICM7207A provides two count window signals (1s and 0.1s gating) for displaying frequencies in Hz or tens of Hz (x10Hz). II 1-1 t I I .,J U, C 1~ L ., D 1 o 1-1 Q _1 (BLANK) FIGURE 7. SEGMENT ASSIGNMENT AND DISPLAY FONT ...• --.. _ _ _ _ _ _r21- •• ••• •:• ····I~···········.··························J 200pF EACH SEGMENT TO BACKPLANE WITH 200pF CAPACITOR FIGURE 6. TEST CIRCUtT 13-62 ICM7224 D D DO! -----===--.... DDDD HIGH ORDER DIGITS LOW ORDER DIGITS r--=--=--=--~. r-----,~/1~OV=ER;.;.;..;FL=OW"__l _ Ll Ll Ll Ll .;Ll Ll Ll Ll 3 SEG 4 SEG , ~ ISEG ~ DIGIT LCD DISPLAY WITH OVERFLOW , 4SEG ~,f1 BACKPLANE &SEG I 15 SEG ~alssl:. 1SSEG II I 10kn I I I I l=: -3 aV·lv Voo ~IIII' 4 5 f---t[] t-- 0- T 12111 ~C/ ~-----------J SWITCH OPEN 1. GATING SWITCH CLOSED 0.1' GATING 10~~~--------+---------------~~----------~ I • r- I CtN ....-----+---"""'1'1 1111111111111.ml 14H~------I--........- - - - - + - f - l 1.- !:oUT IIlilr 131-------------+---1 I- 7_ _---1 8 l!' II I I I ICM7207A _I CRYSTAL CIN-22pF !:oUT· 22pF to =5.24288MHz Rs<75Q Cs. o.015pF Cp. a&pF ~~N~ CONDITIONING (PRESCALER LEVEL SHIFTING) FIGURE 8. EIGHT·DIGIT PRECISION FREQUENCY COUNTER 13-63 - INPUT SIGNAL ICM7226A ICM72268 ~HARRlS ~ SEMICONDUCTOR a-Digit MUlti-Function Frequency CounterlTimers December 1993 Features Description • CMOS Design for Very Low Power • Output Drivers Directly Drive Both Segments of Large 8 Digit LED Displays Digits and • Measures Frequenclea from DC to 10MHz; Periods froni 0.511S to 10s • Stable High Frequency Oscillator uses either 1MHz or 10MHz Crystal • Both Common Anode and Common Cathode Extemal Systems Available • Control Signals Available for Interfacing • MuHlplexed BCD Outputs Applications • Frequency Counter • Period Counter • Unit Counter • Frequency Ratio Counter • Time Interval Counter Ordering Information TEMPERATURE RANGE PACKAGE ICM7226AIJL -25OC to +85OC 40 Lead Ceramic DIP ICM7226BIPL -25OC to +85OC 40 Lead Plastic DIP PART NUMBER The ICM7226 is a fully integrated Universal Counter and LED display driver. It combines a high frequency oscillator, a decade timebase counter, an S-decade data counter and latches, a 7-segment decoder, digit multiplexer and segment and digit drivers which can directly drive large LED displays. The counter inputs accept a maximum frequency of 10MHz in frequency and unit counter modes and 2M Hz in the other modes. Both inputs are digital inputs. In many applications, amplification and level shifting will be required to obtain proper digital signals for these inputs. The ICM7226 can function as a frequency counter, period counter, frequency ratio (fAitS) counter, time interval counter or as a totalizing counter. The devices require either a 10MHz or 1MHz quartz crystal timebase, or if desired an external timebase can also be used. For period and time interval, the 10MHz timebase gives a 0.1~ resolution. In period average and time interval average, the resolution can be in the nanosecond range. In the frequency mode, the user can select accumulation times of 0.01s, 0.1s, 1s and 10s. With a 10s accumulation time, the frequency can be displayed to a resolution of 0.1 Hz. There is 0.2s between measurements in all ranges. Control signals are provided to enable gating and storing of prescaler data. Leading zero blanking has been incorporated with frequency display In kHz and time in I1S. The display is multiplexed at a 500Hz rate with a 12.2% duty cycle for each digit. The ICM7226A is designed for common anode displays with typical peak segment currents of 25mA, and the ICM7226B is designed for common cathode displays with typical segment currents of 12mA. In the display off mode, both digit drivers and segment drivers are turned off, allowing the display to be used for other functions. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @HarrisCorporation 1993 13-64 File Number 3169 ICM7226A, ICM72268 Pinouts ICM7226A COMMON ANODE (CDIP) TOP VIEW CONTROL INPUT INPUT A HOLD INPUTB MEASUREMENT lR PROGRESS 3 BUFOSCOUT FUNCTION 4 NC(NOTE1) S'I'ORl 5 OSCOUT BCD 4 OSCIN BCDS NC(NOTE1) EXT OSC IN SEas II RSTOUT sEag EXTRANaE SEas D1 D2 Vss SEad D3 SEab D4 SEac OS SEG r Veo BCD 2 D6 BCD 1 D7 RS'I'INPUT DB EXTDPIN RANGE ICM7226B COMMON CATHODE (PDIP) TOP VIEW CONTROL INPUT INPUT A INPUTB HOLD MEASUREMENT iN PROGRESS 3 BUFOSCOUT FUNCTION 4 NC(NOTE1) STORE OSCOUT BCD 4 OSCIN NC(NOTE1) EXT OSC IN RSTOUT D2 EXT RANGE D4 DPOUT Vss os SEGS D6 SEas D7 SEad sEag Veo DB 2 BC02 SEab SEac BCD 1 RS'I'INPUT SEar EXTDPIN RANaE NOTE: 1. For maximum frequency Slabllity, connect to Vee or Vss 13-65 CI) Cl)a: a:O ~!c Za: ::)W OZ (.)W 0 ICM7226A, ICM7226B Functional Block Diagram 8~ DECODER r ......--.~.. DRIVERS DIGIT REFERENCE COUNTER +103 3 1 I errosco-_ _ _~~L--, INPUT IN~-I>-~ -+ OSC _ _ OUTPUT BUFOSC OUTPUT RANGE CONTROL .....- - - 0 RANGE LOGIC INPUT 1 100Hz OSC SELECT r+ 4rr.:===:::'U--_.J STORE AND RESET LOGIC It- RANGE SELECT LOGIC err RANGE INPUT L 6 ~_+-~~-_+4_4_-~--+~~ RmT INPUTo---tIl-----tt;:::::::::~~-~~:::t~J, INPUT INPUT A o - - _ + " CONTROL INPUT Bo-......+-+.. rl i MAIN EN COUNTER RESET , I tltilt'l~L~;+::!1~03:...r-TOV~E~R:.:FL;OW:,JIH-+-II-4--+I {4 {4 {4 {4 {4 {4 {4 14 LOGIC 18 I I. o Q I DP LOGIC INPUT L-....t CONTROL H++__ CL MAIN LOGIC FF EXT DP INPUT 1 L.......t 4 CONTROL .----0 LOGIC CONTROL INPUT f-t DATALATCHES j.4!OUTPUTMUX STOREi L DIGIT OUTPUTS (8) t---;::===:::;--====--:i;L---o 8 DECODER ALZB LOGIC 4 SEGMENT ~ DRIVERS ~ SEGMENT L.._ _..I OUTPUTS (8) R BCD OUTPUTS ~~~4~_ _ _ _--o~) FN FUNCTI~_ CONTROL INPUT MEAsiN LOGIC f 1-4-i---If--+------4--I1-l RESET OUTPUT 6 PROGRESS OUTPUT S'i'6RE I~~~~-----------.J OUTPUT 13-66 Specifications ICM7226A, ICM72268 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage (Voo - VsS> •.••••••.•••••..•.•• B.5V Maximum Digit Output Current. •••.......•••.....•.•. .400mA Maximum Segment Output Current •.••••••••.•...•••... SOmA Voltage On Any Input or Output Terminal (Note 1) ..•.•....... (Voo +O.3V) to (Vss -O.3V) Storage Temperature Range ••...•..••..••... -55°C to + 150°C Lead Temperature (Soldering lOs) •.•••••.••••.••••.•• +300oC Thermal Resistance Ceramic DIP Package ••....•..••••.• Plastic DIP Package •••••••••••••••• Junction Temperature Ceramic DIP Package .••.•.••...•••.•.•..•••.•.•• +175°C Plastic 01 P Package .•.•..•..•.•••.•••••.••....•. +150°C Operating Temperature Range ••••••••••.•.•••• -25°C to +85°C CAUTION: Stresses abo"" those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions abo"" those indicated in the operational sections of this specification is not implied. Electrical Specifications voo = 5.0V, TA = +25°C, Unless Otherwise Specified MIN TVP MAX UNITS - 2 5 mA -25°C < TA < +85°C, INPUT A, INPUT B Frequency at IMAX 4.75 - B.O V Maximum Frequency INPUT A, Pin 40, fA(MAX) -25°C < TA < +85°C 4.75V < Voo < B.OV, Figure 9 Function = Frequency, Ratio, Unit Counter 10 14 - MHz Function = Period, Time Interval 2.5 MHz -25°C < TA < +85°C 4.75V < Voo < 6.0V, Figure 10 2.5 - - Maximum Frequency INPUT B, Pin 2, IB(MAX) - MHz Minimum Separation INPUT A to INPUT B, Time Interval Function -25°C < TA < +85°C 4.75V < Voo < B.OV, Figure 1 250 - - ns 0.1 - 10 MHz PARAMETER TEST CONDITIONS Operating Supply Current, 100 Display Off, Unused Inputs to Vss Supply Voltage Range (Voo -VSS>, VSUPPLY Oscillator Frequency and Ex1ernal Oscillator Frequency, -25°C < TA < +85°C 4.75V < Voo < B.OV losc OSCillator Transconductance, gM Voo -4.75V, TA = +85°C 2000 - - 500 lose = 10MHz - 200 Inputs A, B - 15 Multiplex Frequency, I MUX losc= 10MHz TIme Between Measurements Input Rate 01 Charge, dVIr/dt - jJS Hz IllS mV/jIlI Input Voltages: Pins 2, 19, 33, 39, 40, 35 Input Low Voltage, VIL -25°C < TA < +85OC Input High Voltage, VIH - - 3.5 Pins 2, 39, 40, Input Leakage, A, B, IILK 1.0 V - V 20 jIA Input Resistance to Voo Pins 19,33, RIN VIN = Voo -1.0V 100 400 - kO Input Resistance to Vss Pin 31, RIN VIN =+1.0V 50 100 - kO - - 25 35 - 100 - Low Output Current, Pins 3, 5-7,17,18,32,38, IOL VOL =+O·4V 400 High Output Current, Pins 5-7,17,18,32, HaL VOH=+2.4V 100 High Output Current, Pins 3, 38, HOl VOH = Voo -O.8V 265 Vo =+1.5V jIA jIA jIA ICM7226A Segment Driver: Pins 8-11, 13-18 Low Output Current, IOL High Output Current, IOH Vo = Voo -1.0V mA jIA MUltiplex Inputs: Pins 1, 4, 20, 21 Input Low Voltage, VIL - - 0.8 V Input High Voltage, VIH 2.0 - - V 50 100 - kO Input Resistance to VSS, RIN VIN = +1.0V 13-67 (I)~ a:O Output Current ~~ Za: OZ OW CJ ;:)W Specifications ICM7226A, ICM7226B Electrical Specifications voo = 5.0V, TA = +250 C, Unless Otherwise Speclfled (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - -0.3 - mA 150 180 - mA Digit Driver: Pins 22-24, 26-30 Low Output Current, IOL Vo=+1.0V High Output Current, IOH Vo = Voo -2.0V ICM7226B Segment Driver: Pins 22-24, 26-30 - - 10 IIA 10 15 - mA Input Low Voltage, VIL - - Voo-2.0 V Input High Voltage, VIH Voo-0.8 - VIN = Voo -1.0V 100 360 Vo = +1.0V 50 75 - 100 Leakage Current, IL Vo=Vss High Output Current, IOH Vo = Voo -2.0V Multiplex Inputs: Pins 1, 4, 20, 21 Input Resistance to Vss , RIN V " - kO Digit Driver: Pins 8-11, 13-16 Low Output Current, IOL High Output Current, IOH Vo = Voo -2.5V - mA IIA NOTES: 1. Destructive latch up may occur if input signals are applied before the power supply is established or if inputs or outputs are forced to voltages exceeding Voo or Vss by 0.3V. 2. Assumes aI/leads soldered or welded to PC board and free air flow. 3. Typical values are not tested. Timing Waveform --I STORE ~ 30ms TO 40ms RESET 1--40ms -~"""-;LJ L eOma --~----~~~--~~ --I 7oms! :...UPDATE : 190ms TO 200ms , ;00 , . . : FUNCll0N: llME INTERVAL PRIMING -...;....... : .. o < _ - - - MEASUREMENT INTERVAL _ _ _.....~~... P_D_AT_E ' MEASUREMENT IN PROGRESS INPUT A INPUTS -- ,, , MEASURED INTERVAL (LAST) NOTE: 1. II range is set to 1 event, first and last measured interval will coincide. FIGURE 1. WAVEFORMS FOR TIME INTERVAL MEASUREMENT (OTHERS ARE SIMILAR, BUT WITHOUT PRIMING PHASE) 13-68 ICM7226A, ICM72268 Typical Performance Curves 300 200r----------r----------r---------~ 4.5 S YDD SLOY 200 :c .§. l j j 100 °o~--------~~£--L----~------~ YourM YDO"YourM FIGURE 2. ICM7226B TYPICAL IDlGlT VI Vour FIGURE 3. ICM7226A TYPICAL IDIG VI VDO"Vour 30r---------~----------r_------~~ 4.5 S YDD S S.oy 20~--------_+----------+_~~~--~ 10~--------_+----~----+_--------~ °0~----~~~----------~2--------~3 YourM YDO"YourM FIGURE 4. ICM7226B TYPICAL ISEG VI VDO"Vour FIGURE 5. ICM7226A TVPICAL !seG VI Vour U) U)a: a:O t!:!!c Za: ::;)W OZ (J l j YOIJTM YourM FIGURE 6. ICM7226B TYPICAL IctGlT VI Vour FIGURE 7. ICM7226A TYPICAL ISEG VI Vour 13-69 ~ , ICM7226A, ICM7226B Typical Performance Curves (Continued) fA (MAX) FREQUENCY UNIT~ FREQUENCY RATIO MODES 1& ~ I I" fA (MAX) fS (MAX) PERIOD TIME INTERVAL MODE!-- & TA-+25"C o 3 5 4 6 VorrVssM FIGURE 8. fA{MAX), fs{MAX) AS A FUNCTION OF SUPPLY Description INPUTS A and B The signal to be measured is applied to INPUT A in frequency period, unit counter. frequency ratio and time interval modes. The other Input signal to be measured is applied to INPUT B in frequency ratio and time interval. fA should be higher than fe during frequency ratio. COUNTED TRANSITIONS INPUT A 4.SV o.5V Both inputs are digital inputs with a typical switching threshold of 2.0V at VDD 5.0V and input impedance of 25Okn. For optimum performance. the peak to peak input signal should be at least 50% of the supply voltage and centered about the switching voltage. When these inputs are being driven from TTL logic. it is desirable to use a pullup resistor. The circuit counts high to low transitions at both inputs = Note that the amplitude of the Input should not exceed the device supply (above the V DD and below the Vss) by more than 0.3V. otherwise the device may be damaged. -----'\1 SOn. MIN Multiplexed Inputs FIGURE 9. WAVEFORM FOR GUARANTEED MtNIMUM fA{MAX) FUNCTION FREQUENCY. FREQUENCY RATIO, UNIT COUNTER = INPUT A OR 4.5V INPUTe O.5V FIGURE 10. WAVEFORM FOR GUARANTEED MINIMUM fstMAX) AND fA{MAX) FOR FUNCTION. PERIOD AND.TIME INTERVAL The FUNCTION. RANGE. CONTROL and EXTERNAL DECIMAL POINT inputs are time multiplexed to select the function desired. This is achieved by connecting the appropriate Digit driver output to the inputs. The function. range and control inputs must be stable during the last half of each digit output. (typically 125Jl.S). The multiplexed inputs are acti.ve high for the common anode ICM7226A and active low for the common cathode ICM7226B. Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of operation is selected. since changes In voltage on the digit drivers can be capacitively coupled through the LED diodes to the multiplex inputs. For maximum noise immunity. a 10kn resistor should be placed in series with the multiplexed inputs as shown in the application circuits. 13-70 ICM7226A, ICM72268 Table 1 shows the functions selected by each digit for these inputs. TABLE 1. MULTIPLEXED INPUT FUNCTIONS FUNCTION FUNCTION INPUT Pin 4 RANGE INPUT Pin 21 DIGIT Frequency 01 Period 08 Frequency Ratio 02 Time Interval 05 Unit Counter 04 Oscillator Frequency 03 0.01 S/1 Cycle 01 0.1S/10 Cycles 02 1S/1 00 Cycles 03 10S/1 K Cycles 04 Enable External Range Input CONTROL INPUT Pin 1 External OP INPUT Pin 20 05 Display Off 04 and Hold Display Test 08 1MHzSelect 02 External Oscillator Enable 01 External Decimal Point Enable 03 The implementation of different functions is done by routing the different signals to two counters. called "Main Counter" and "Reference Counter". A simplified block diagram of the device for functions realization is shown in Figure 11. Table 2 shows which signals will be routed to each counter in different cases. The output of the Main Counter is the information which goes to the display. The Reference Counter divides its input to 1, 10, 100 and 1000. One of these outputs will be selected through the range selector and drive the enable input of the Main Counter. This means that the Reference Counter, along with its' associated blocks, directs the Main Counter to begin counting and determines the length of the counting period. Note that Figure 11 does not show the complete functional diagram (See the Functional Block Diagram). After the end of each counting period, the output of the Main Counter will be latched and displayed, then the counter will be reset and a new measurement cycle will begin. Any change in the FUNCTION INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the FUNCTION INPUT is changed. In all cases, the 1-0 transitions are counted or timed. TABLE 2. INPUT ROUTING Decimal point is output for same digit that is connected to this input. Function Input The six functions that can be selected are: Frequency, Period, Time Interval, Unit Counter, Frequency Ratio and Oscillator Frequency. 100Hz INPUT A MAIN COUNTER FUNCTION COUNTER 100Hz (Oscillalor +105 or 104) Frequency (fA) InpulA Period (tA) Oscillator Input A Ratio (fAils) Input A InputB Time Interval (A.....B) OSCillator Input A InpulB UnitCounler (CounIA) Input A Not Applicable Osc. Freq. (fosc) Oscillator 100Hz (OsCillator +1 OS or 104) INTERNAL CONTROL INTERNAL CONTROL 1 ! INPUT SELECTOR CLOCK INPUTB REFERENCE COUNTER 1+11+101+100 1+1 000 INTERNAl.CONTROL INTERNAL OR EXTERNAL OSCILLATOR INPUT A INTERNAL CONTROL RANGE SELECTOR L INPUT SELECTOR ENABLE CLOCK MAIN COUNTER FIGURE 11. SIMPLIFIED BLOCK DIAGRAM OF FUNCTIONS IMPLEMENTATION 13-71 (I)~ a:O ~!cc Za: OZ OW CJ ;:)W I ICM7226A, ICM72268 Frequency - In this mode Input A is counted .by the Main Counter for a precise period of time. This time is determined by the time base oscillator and the selected range. For the 10MHz (or 1MHz) time base~ the. resolutions are 100Hz, 10Hz, 1Hz and 0.1 Hz. The decimal point on the display is set for kHz reading. Period - In this mode, the tlmebase oscillator is counted by the Main Counter for the duration of 1,10,100 or 1000 (range selected) periods of the signal at input A. A 10MHz timebase gives resolutions of 0.1 jI.S to 0.000111S fOr 1000 periods averaging. Note that the· maximum input frequency for period measurement is 2.5MHz. Frequency Ratio - In this mode, the Input A Is counted by the Main Counter for the duration of 1,10,100 or 1000 (range selected) periods of the signal at input B. The frequency at input A should be higher than input B for meaningful result. The result in this case is unitless and its resolution can go up to 3 digits after decimal point. Time Interval - In this mode, the timebase oscillator is counted by the Main Counter for the duration of a 1-0 transition of input A until a 1-0 transition of input B. This means input A starts the counting and input B stops it. If other ranges, except 0.01 sf1 cycle are selected the sequence of input A and B transitions must happen 10,100 or 1000 times until the display becomes updated; note this when measuring long time intervals to give enough time for measurement completion. The resolution in this mode Is the same as for period measurement. See the TIme Interval Measurement section also. Unit Counter - In this mode, the Main Counter is always enabled. The input A is counted by the Main Counter and displayed continuously. Oscillator Frequency - In this mode, the device makes a frequency measurement on its timebase. This is a self test mode for device functionality check. For 10MHz tlmebase the display will show 10000.0, 10000.00, 10000.000 and Overflow in different ranges. Range Input The RANGE INPUT sel8cts whether the measurement period is made for 1,10,100 or 1000 counts of the Reference Counter or it Is controlled by EXT RANGE input. As it is shown In Table 1, this gives different counting windows for frequency measurement and various cycles for other modes of measurement. In all functional modes except Unit Counter, any change in the RANGE INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the RANGE INPUT is changed. Control Input Unlike the other multiplexed inputs, to which only one of the digit outputs can be connected at a time, this input can be tied to different digit lines to select combination of controls. In this case, isolation diodes must be used in digit lines to avoid crosstalk between them (see Figure 19). The direction of diodes depends on the device version, common anode or common cathode. For maximum noise immunity at this input, in addition to the 10K resistor which was mentioned before, a 39pF to. 100pF capacitor should also be ·placed between this input and the VDO or Vss (See Figure 19). Display Off - To disable the display drivers, it is necessary to tie the D4 line to the CONTROL INPUT and have the HOLD input at VOl> While in Display Off mode, the segments and digit drivers are all off, leaving the display lines floating, so the display can be shared with other devices. In this mode, the oscillator continues to run with a typical supply current of 1.5mA with a 1OMHz crystal, but no measurements are made and multiplexed inputs are inactive. A new measurement cycle will be initiated when the HOLD input is switched to Vss. Display Test - Display will turn on with .all the digits showing 8s and all decimal points also on. The display will be blanked if Display Off is selected at the same time. 1MHz Select - The 1MHz select mode allows use of a 1MHz crystal with the same digit multiplex rate and time between measurement as with a 1OMHz c7stal. This is done by dividing the oscillator frequency by 10 rather than 105. The decimal point Is also shifted one digit to the right In period and time interval, since the least significant digit will be in I1s increment rather than 0.111S increment. External OsCillator Enable - In this mode, the signal at EXT OSC INPUT is used as a. timebase instead of the on-board crystal oscillator (built around the OSC INPUT, OSC OUTPUT inputs). This input can be used for an extemal stable temperature compensated crystal oscillator or for special measurements with any external source. The on-board crystal oscillator continues to work when the external oscillator is selected. This is necessary to avoid hang-up problems, and has no effect on the chip's functional operation. If the on-board oscillator frequency Is less than 1MHz or only the extemal oscillator Is used, THE OSC INPUT MUST BE CONNECTED TO THE EXT OSC INPUT providing the timebaSe has enough voltage swing for OSC INPUT (See Electrical Specifications). If the external timebase is TTL level a pullup resistor must be used for OSC INPUT. The other way is to put a 22MO resistor between OSC INPUT and OSC OUTPUT and capacitlvely couple the EXT OSC INPUT to OSC INPUT. This will bias the OSC INPUT at its threshold and the drive voltage will need to be only 2Vp.p. The external timebase frequency must be greater than 100kHz or the chip will reset itself to enable the on-board oscillator. External Decimal Point Enable - In this mode, the EX DP INPUT is enabled. A decimal point will be displayed for the digit that its output line is connected to this input (EX DP INPUT). Digit 8 should not be used since it will override the overflow output. Leading zero blanking is effective for the digits to the left of selected decimal point. Hold Input Except in the unIt .counter mode, when the HOLD input is at Vop , any measurement in progress (before STORE goes low) is stopped, the main counter is reset and the chip is held ready to initiale a new measurement as soon as HOLD goes low. The latches which hold the main counter data are not updated, so the last complete measurement is displayed. In unit counter mode when HOLD input is at Voo, ttle counter is not stopped or reset, but the display is frozen at that instantaneous value. When HOLD goes low the count continues from the new value in the new counter. 13-72 ICM7226A, ICM7226B 1-1_ To_-1 RSTIN Input The RST IN is provided to reset the Main Counter, stop any measurement in progress, and enable the display latches, resulting in the all zero display. It is suggested to have a capacitor at this input to Vss to prevent any hangup problem on power up. See application circuits. I ---1....1-1 IN PROGRESS REFERENCE COUNTER CLOCK ~ EXT RANGE INPUT ~ ~ MEAl! IN PROGRESS 1 1...-_ _ 30n:o~~ f=1~ 60ma n RESET OUT -------------1~ EXT RANGE Input This input is provided to select ranges other than those provided in the chip. In any mode of measurement the duration of measurement is determined by the EXT RANGE if this input is enabled. This input is sampled at lOms intervals by the 100Hz reference derived from the timebase. Figure 12 shows the relationship between this input, 100Hz reference signal and MEAS IN PROGRESS. EXT RANGE can change state anywhere during the period of 100Hz reference by will be sampled at the trailing edge of the period to start or stop measurement. I f__40ma ~f__-~-ma----- FIGURE 13. RESET OUT, STORE AND MEASUREMENT IN PROGRESS OUTPUTS BETWEEN MEASUREMENTS BCD Outputs The BCD representation of each display digit is available at the BCD outputs in a muHiplexed fashion. See Table 3 for digits truth table. The BCD output of each digit is available when its corresponding digit output is activated. Note that the digit outputs are multiplexed from D8 (MSD) to Dl (lSD). The positive going (ICM7226A, common anode) or the negative going (ICM7226B, common cathode) digit drive signals lag the BCD data by 2~s to 6~. This starting edge of each digit drive signal should be used to externally latch the BCD data. Each BCD output drives one low power Schottky TTL load. leading zero blanking has no effect on the BCD outputs. TABLE 3. TRUTH TABLE BCD OUTPUTS NUMBER BCD8 PIN 7 0 0 1 0 2 0 3 0 0 0 1 1 4 0 1 0 0 FIGURE 12. EXTERNAL RANGE INPUT TO END OF MEASUREMENT IN PROGRESS This input should not be used for short arbitrary ranges (because of its sampling period), it is provided for very long gating purposes. A way of using the ICM7226 for a short arbitrary range is to feed the gating signal into the INPUT B and run the device in the Frequency Ratio mode. Note that the gating period will be from one positive edge until the next positive edge of INPUT B (0.01 S/1 cycle range). MEAS IN PROGRESS, STORE, RST OUT Outputs These outputs are provided for external system interfacing. MEAS IN PROGRESS stays low diJring measurements and goes high for intervals between measurements. Figure 13 shows the relationship between these outputs for intervals between measurements. All these outputs can drive a low power Schottky TTL. The MEAS IN PROGRESS can drive one ECl load if the ECl device is powered from the same power supply as the ICM7226. BCD4 PIN 6 BCD2 PIN 17 BCD 1 PIN 18 0 0 0 0 0 1 1 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 BUF OSC OUT Output The BUFFered OSCillator OUTput is provided for use of the on-board oscillator signal, without loading the oscillator itself. This output can drive one low power Schottky TTL load. Care should be taken to minimize capacitive loading on this pin. Decimal Point Position FREQUENCY PERIOD Table 4 shows the decimal point position for different modes of ICM7226 operation. Note that the digit 1 is the least significant digit. Table is given for 10MHz timebase frequency. FREQUENCY RATIO TIME INTERVAL UNIT COUNTER OSCILLATOR FREQUENCY 0.01 sl1 Cycle 02 02 01 02 01 02 0.1 sl1 0 Cycle 03 03 02 03 01 03 1s1100 Cycle D4 04 03 D4 01 D4 1Osl1 K Cycle 05 05 D4 05 01 05 External NlA NlA NlA NlA NlA NlA 13-73 0::0 ~!ci: zo:: TABLE 4. DECIMAL POINT POSITIONS RANGE CII ClIO:: ::)w OZ CJ (.)W ICM7226A, ICM7226B Overflow Indication When overflow happens in any measurement. ~ will be indicated on the decimal point of the dig~ 8. A separate LED indicator can be used. FlQure 14 shows how to connect this indicator. 0123455789 CATHODE ANODE ICM7226A Decimal Point 08 ICM7226B 08 Decimal Point FIGURE 14. SEGMENT IDENTIFICATION AND DISPLAY FONT Time Interval Measurement When in the time Interval mode and measuring a single event. the ICM7226A and ICM7226B must first be "primed" prior to measuring the event of interest. This is done by first generating a negative going edge on Channel A followed by a negative going edge on Channel B to start the "measurement interval". The Inputs are then primed ready for the measurement. Positive going edges on A and B. before or after the priming. will be needed to restore the original condition. Priming can be easily accomplished using the circuit in Figure 15. SIGNAL A 2 INPUT A INPUTB N.O. VDD I ~ I PRIME I The oscillator is a high gain complementary FET inverter. An external resistor of 10Mn or 22Mn should be connected between the oscillator input and output to provide biasing. The oscillator is deSigned to work with a parallel resonant 10MHz quartz crystal with a static capacitance of 22pF and a series resistance of less than 35n. Among suitable crystals is the 10MHz CTS KNIGHTS ISI-002 For a specific crystal and load capacitance. the required gM can be calculated as follows: CO)2 gM=co2 CINCOUTRs ( I+C L CINCOUT ) whereC L = ( C C IN+ OUT = CO Crystal Static Capacitance Rs = Crystal Series Resistance CIN Input Capacitance COUT Output Capacitance co = 2ltf = = The required gM should not exceed 50% of the gM specified for the ICM7226 to insure reliable startup. The OSCillator INPUT and OUTPUT pins each contribute about 4pF to CIN and COUTo For maximum stability of frequency. CIN and COUT should be approximately twice the specified crystal static capacitance. In cases where non decade prescalers are used. it may be desirable to use a crystal which is neither 10MHz or 1MHz. In that case both the multiplex rate and time between measurements will be different. The multiplex rate is SIGNALB VDD During any lime interval measurement cycle. the ICM7226A and ICM7226B requires 200ms following B going low to update all internal logic. A new measurement cycle will not take place until completion of this internal update time. Oscillator Considerations LED overflow indicator connections: Overflow ill be indicated on the decimal point output of digit 8. DEVICE When timing repetitive signals. it is not necessary to "prime" the ICM7226A and ICM7226B as the first alternating signal states automatically prime the device. See Figure 1. 'osc 'osc 'MUX = - - 4 for 10MHz mode and 'MUX = - - 3 for the ?xl0 2xl0 6 lMHz mode. The time between measurements is 10 in 150K 2xl0 5 . 2tosc the 10MHz mode and -,-- In the lMHz mode. osc Vss Vss DEVICE Vss TYPE 1 CD4049B Inverting Buffer 2 CD4070B Exclusive - OR FIGURE 15. PRIMING CIRCUIT, SIGNALS A .. B BOTH HIGH OR LOW Following the priming procedure (when in single event or 1 cycle range) the device is ready to measure one (only) event. The buffered oscillator output should be used as an oscillator test point or to drive additional logic; this output will drive one low power Schottky TIL load. When the buffered oscillator output is used to drive CMOS or the external oscillator input, a 10ka resistor should be added from the buffered oscillator output to VDOThe crystal and oscillator components should be located as close to the chip as practical to minimize pickup from other signals. Coupling from the EXTERNAL OSCILLATOR INPUT to the OSCILLATOR OUTPUT or INPUT can cause undesirable shifts in oscillator frequency. 13-74 ICM7226A, ICM7226B Display Considerations The display is multiplexed at a 500Hz rate with a digit time of 2441ls. AIl interdigit blanking time of SIlS is used to prevent display ghosting (faint display of data from previous digit superimposed on the next digit). Leading zero blanking is provided. which blanks the left hand zeroes after decimal point or any non zero digits. Digits to the right of the decimal point are always displayed. The leading zero blanking will be disabled when the Main Counter overflows. The ICM722SA is designed to drive common anode LED displays at peak current of 25mNsegment. using displays with V F 1.8V at 25mA. The average DC current will be greater than 3mA under these condHions. The ICM722SB is deSigned to drive common cathode displays at peak current of 15mN segment using displays with V F = 1.8V at 15mA. Resistors can be added in series wHh the segment drivers to lim it the display current. if required. The Typical Performance Curves show the digit and segment currents as a function of output voltage for common anode and common cathode drivers. = To increase the light output from the displays. Voo may be increased to S.OV. However. care should be taken to see that maximum power and current ratings are not exceeded. The SEGment and Digit outputs in both the ICM722SA and ICM722SB are not directly compatible with either TTL or CMOS logic. Therefore. level shifting with discrete transistors may be required to use these outputs as logic signals. External latching should be down on the leading edge of the digit signal. Accuracy In a Universal Counter. crystal drift and quantization errors cause errors. In frequency. period and time Interval modes. a signal derived from the oscillator is used in either the Reference Counter or Main Counter. and in these modes. an error in the oscillator frequency will cause an identical error in the measurement. For instance. an oscillator temperature coefficient of 20ppml"C will cause a measurement error of 20ppml"C. In addition. there is a quantization error inherent in any digital measurement of ±1 count. Clearly this error is reduced by displaying more digits. In the frequency mode maximum accuracy is obtained with high frequency inputs and in period mode maximum accuracy is obtained with low frequency inputs. As can be seen in Figure 1S. In time Interval measurements there can be an error of 1 count per interval. As a result there is the same inherent accuracy in all ranges as shown in Figure 17. In frequency ratio measurement can be more accurately obtained by averaging over more cycles of INPUT B as shown in Figure 18. o "' MAXIMUM nME INTERVAL _ I"' "",OR 10 INTERVALS 3 / I "'"' MAXIMUM nME INTERVA~ _ F j 10lNrRV J 7 jLS 8 10 103 FREQUENCY (Hz) 1 107 105 FIGURE 16. MAXIMUM ACCURACY OF FREQUENCY AND PERIOD MEASUREMENTS DUE TO LIMITATIONS OF QUANTIZATION ERRORS 10 102 I MAXlMUMnME INTERVAL FOR If 102 INTERVALS ~ "- 103 104 105 10' nME INTERVAL (J1S) 107 10· FIGURE 17. MAXIMUM ACCURACY OF TIME INTERVAL MEASUREMENT DUE TO LIMITATIONS QUANTIZATION ERRORS OF CI)~ ffig I-CC za: :::)w oz Ow c.:J 10 102 103 104 105 10' 107 108 f/llla FIGURE 18. MAXIMUM ACCURACY FOR FREQUENCY RATIO MEASUREMENT DUE TO LIMITATION OF QUANTIZATION ERRORS 13-75 ICM7226A, ICM72268 Test Circuit DISPLAY DISPlAY OfF TEST 1MHz VDD-S.OV EXT EXT OSC DP TEST INPUT A CONTROL INPUT 1NII14. Vss a ..IF..U_NCTI=O..N...LoK ...---001 1CM7228A +--_03 8 CRYSTAL SPECS•• FO 10.00MHz Co 22pF RS 35{.1 BCOB 5 BCOA reseT -'-0--+--1 fa 100kll a 8 os • DB D7 08o__---' LEO OVERFLCMI INDICATOR ' " 8 88.8.8.8.8.8.8. 01 LED OVERFLOW INDICATOR CONNECTIONS DEVICE ICM7226A ICM7226B CATHODE ANODE OP 08 DB OP NOTE: OIIerfIow will be indicated on the decimal pOint output of digit 7. FIGURE 19. 13-76 OENOTESBU WITH a CONDUCTORS ICM7226A, ICM72268 Typical Applications The ICM7226 has been designed as a complete stand alone Universal Counter, or used with prescalers and other circuitry in a variety of applications. Since INPUT A and INPUT B are digital inputs, additional circuitry will be required in many applications, for input buffering, amplification, hysteresis, and level shifting to obtain the required digital voltages. For many applications a FET source follower can be used for input buffering, and an ECl10116 line receiver can be used for amplification and hysteresis to obtain high impedance input, sensitivity and bandwidth. However, cost and complexity of this circuitry can vary widely, depending upon the sensitivity and bandwidth required. When TTL prescalers or input buffers are used, a pull up resistors to Voo should be used to obtain optimal voltage swing at INPUTS A and B. 10kn If prescalers aren't required, the ICM7226 can be used to implement a minimum component Universal Counter as shown in Figure 20. For input frequencies up to 4OMHz, the circuit shown in Figure 21 can be used to implement a frequency and perIod counter. To obtain the correct value when measuring frequency and period, It is necessary to divide the 1OMHz oscillator frequency down to 2.5MHz. In doing this the time between measurements is lengthened to 800ms and the display multiplex rate is decreased to 125Hz. If the input frequency is prescaled by ten, the oscillator frequency can remain at either 10MHz or 1MHz, but the decimal point must be moved. Figure 22 shows use of a +10 prescaler in frequency counter mode. Additional logic has been added to enable the ICM7226 to count the input directly in perIod mode for maximum accuracy. DISPLAY DISPLAY EXT OSC BLANK TEST ENABLE ICM7226A, ICM72268 AIN c VDD 10lI0 VDD 3Icn 8 1251--1-_ VDD BIN 4 1001cn B B.B.B.B.B.B.B. 3 OVERFLC7N • FIGURE 21. 40MHz FREQUENCY, PERIOD COUNTER 13-78 ICM7226A, ICM72268 EXT DISPLAY DISPLAY osc OFF TEST EN 10 len 8 t-----t-tD Yeo EXT OSC IN 30 PF ICM7226A 1 22Mn 30pF TYP Yoo Yoo 8 D1 4 5 S6 RANGE OS 1 DOlen 2 B B.B.B.B.B.B.B. D1 8 (I) ~ ffi~ FIGURE 22. 100MHz MULTI-FUNCTION COUNTER 13-79 l-icC Za: ::IW OZ (,)W CJ , ICM7226A, ICM7226B INPUT 38pF __ 10kn V~~~ ~~ DISPlAY DISPLAY __________________ OFF__ TEST ~ V~ ~ \ -....- - . 0 1N814a _V~ SWITCH +-<~--LJ OPENFREQ CLOSED PERIOD -!- . . . - - - -... F 3 1 - - - - -....... 0 39pF TVP • 4 2 • B B.B.B.B.B.B.B. OVERFLOW FIGURE 23. 100MHz FREQUENCY, PERIO.D COUNTER 13-80 V~ 10kn V~ FUNCTION , ~~~ "'--- ICM7226A, ICM72268 Figure 23 shows the use of a CD4016 analog multiplexer to multiplex the digital outputs back to the FUNCTION Input. Since the CD4016 is a digitally controlled analog transmission gate, no level shifting of the digit output is required. CD4051's or CD4052's could also be used to select the proper inputs for the multiplexed input on the ICM7226 from 2 or 3 bit digital inputs. These analog multiplexers may also be used in systems in which the mode of operation is controlled by a microprocessor rather than directly from front panel switches. TTL multiplexers such as the 74LS153 or 74LS251 may also be used, but some additional circuitry will be required to convert the digit output to TTL compatible logic levels. The circuit shown in Figure 24 can be used in any of the circuit applications shown to implement a single measurement mode of operation. This circuit uses the STORE output to lffi)I!il OUTPUT put the ICM7226 into a hold mode. The HOLD input can also be used to reduce the time between measurements. The circuit shown in Figure 25 puts a short pulse into the HOLD input a short time after STORE goes low. A new measurement will be initiated at the end of the pulse on the HOLD input. This circuit reduces the time between measurements to about 40ms from 200ms; use of the circuit shown in Figure 25 on the circuit shown in Figure 21 will reduce the time between measurements from 600ms to about 160ms. Using LCD Display Figure 26 shows the ICM7226 being Interfaced to LCD displays, by using its BCD outputs and 8 digit lines to drive two ICM7211 display drivers. HOLD INPUT Voo 100kO ~ 100kO OUTPUT HOLD INPUT SWITCH FUNCTION 81 Open-Single Meas Mode Enabled 52 Closed-Initiate New Measurement 53 Closed-Hold Input J N.O. HOLD SWlTCH"!!- FIGURE 24. SINGLE MEASUREMENT CIRCUIT FOR USE WITH ICM7226 FIGURE 25. CIRCUIT FOR REDUCING TIME BETWEEN MEASUREMENTS o 011: ffi~ l-iCt ZII: ;:)w OZ (.)W " FIGURE 26. 10MHz UNIVERSAL COUNTER SYSTEM WITH LCD DISPLAY 13-81 ICM7249 51/2 Digit LCD J.1..Power Event/Hour Meter December 1993 Features Description • Hour Meter Requires Only 4 Parts Total The ICM7249 TimerlCounter is intended for long-term battery-supported Industrial applications. The ICM7249 typically draws 1jlA during active timing or counting. due to Harris' special low-power design techniques. This allows more than 10 years of continuous operation without baltery replacement. The chip offers four timing modes. eight counting modes and four test modes. • Mlcropower Operation: < 1J.IA at 2.8V TyplcsJ • 10 Year Operation On One Uthlum eell. 21/2 Year Battery Ute with Display Connected • Directly Drives 51/ 2 Digit LCD • 14 Progremmable Modes of Operation • TImes Hrs., 0.1 Hrs., 0.01 Hrs., 0.1 Mlns. • Counts1's, 10's, 100's, 1000's • Dual Funtlon Input Circuit - Selectable Debounce for Counter - High-Pass Filter for TImer The ICM7249 is a 48 lead device. powered by a single DC voltage source and controlled by a 32.768kHz quartz crystal. No other external components are required. Inputs to the chip are TTL-compatible and outputs drive standard direct drive LCD segments. Pinout ICM7249 (PDIP) • Direct AC Une Triggering with Input Resistor • Winking "TImer Active" Display Output TOP VIEW • Display Test Feature Applications b61c6 DT 15 SIS • AC or DC Hour Meters C3 C2 • AC or DC Totalizers C1 • Portable Battery Powered Equipment co 05 • Long Range Service Meters GND b5 OSCOUTPUT OSCINPUT Ordering Information 114 PART NUMBER ICM7249IPM TEMPERATURE RANGE -2O"C to +85"C PACKAGE 48 Lead Plastic DIP VDD 84, BP d4 W c4 .1 b4 b1 84 01 f3 d1 g3 .1 e3 111 oS " 82 b3 e3 12 lIZ d2 --..------....---- CAUTION: Th_ devices are aansltlve to e1ec:troatatiC discharge. Users should follow proper I.C. Handling Procedures. Copyright@HarrisCorporation 1993 13-82 a2 File Number 3170 ICM7249 Functional Block Diagram OSC IN OSC OUT 13-83 Specifications ICM7249 Thermal Information Absolute Maximum Ratings Supply Voltage (Voo - Vss) •••••••••••••••••••••••••••••• 6V Input Voltage, Pins 43 - 48 (Note 1) ••• (Vss - 0.3V) to (Voo + 0.3V) Storage Temperature Range ••••••••••••••••• -65OC to +15O"C Lead Temperature (Soldering, 108) ••••••••••• , ••••••• +300"C Thermal Resistance 9JA Plestlc Package. • • • • • • • • • • .• • • • •.. • • • • • • • • • • • •• 5r:1'CIW Operating Temperature Range ••••••••••••••••• -40"C to +85°C Junction Temperature •••••••••••••••••••••••••••••• +15O"C CAUTION: SIrrIssss abov8 thoSB listed In "AbsoIufl!l Maximum Ratif7(J$' may cause permanent damage to the dsvice. This Is a stress only /BUng and op8/Btion of /he device at these or any other condlJions abov8 Ihoee indicatBd in the op8/Btional seclions of /his specilication Is not ImpNed. Electrical Specifications Temperature = -4()0C to +85OC, Voo = 2.5V to 5.5V, Vss = OV, Unless Otherwise Specified. Typical Specifications Measured at Temperature = +25OC and Voo = 2.8V, Unless Otherwise Specified UMrrs PARAMETER Operating Voltage, Voo Operating Current, 100 TEST CONDmONS Note 2 MIN TYP MAX UNrrs 2.5 - 5.5 V A1llnpu1s = Voo or GND, Note 3 - Voo =2.8V Voo= 5.5V 1.0 10.0 IJA 4.0 20.0 IJA INPUT CURRENT 0.0 - 1 IJA 0.5 1.5 3.0 IJA 40.0 - 110 IJA V1L - 0.3Voo V V1H O·7Voo - CO-C3,IIN SiS,lss A1llnpuls Voo or GND Voo= 2.8V Note 4 DT,loT INPUT VOLTAGE CO - C3, DT, SIS - , V Segment OUtput Voltage VOL IoL =11JA - VOH IOH = 11JA Voo -0.8 - VOL IOL = 101JA - VOH IOH = 101JA Voo -0.8 0.8 V - V - 0.8 V - - V 0.1 - ppm 5 - ppm 10,000 lIS - lIS - lIS Backplane Output Voltage OSCILLATOR STABILITY - Temperature = +25°C, Voo = 2.5V to 5.5V Temperature = -4O"C to +85OC, VDO = 2.5V to 5.5V SIS PULSE WIDTH High-Pass Filter (Modes 0 - 3), THP 5 Debounce (Modes 4, 6, 8, 10), TOE 10,000 WHhout Debounce (Modes 5, 7, 9, 11), TOE 5 - NOTES: 1. Due to the SCR structure Inherent In Junction-isolated CMOS devices. the circuit can be put in a latchup mode Hlarge curren1s are Injected into device Inpuls or outputs. For this reason special care should be taken in a system wHh multiple power supplies to prevent voltages being applied to Inpuls or outpu1s before power is applied. If only inpu1s are affected, latchup also can be prevented by limiting the current Into the input terminal to less than 1mAo 2. Internal reset to 00000 requires a maximum Voo rise time of 111S. Longer rise times at power-up may cause Improper reset. 3. Operating current is measured wHh the LCD disconnected, and Input current Iss and lOT supplied externally. 4. Inpu1s CO - C3 are latched internally and draw no DC current after swHchlng. During swHching. a 90IJA peak current may be drawn for 1Ons. 13-84 ICM7249 Timing Waveforms ONE 1/2 BACKPLANE CYCLE ____+,J OSCOUT 10 - 32.768kHz :'234511 , BPWHi lap. 32Hz :, ON~A! SEGMENTS 0@W"4, ISEG-32Hz : OFF SEGMENTS ?»J'»»/'2I, ~!, : FIGURE 1. POWER ONIRESET WAVEFORMS TIMING ACTIVE DURING INTERVAL MVM» - { ,~>,_ } ___________ 11MINGINTERMINA I ~ !--THP SlSINVAUD -------i 10m. /23.8 I Rs ICLl068 1.235V 121en '. ~ COMMON INLO V l1'1.000V ADJ lien r402Q 1 SCALE ZERO 51en SAD590 t v+ 7.5kq, 151en 26.1 len , vFIGURE 11. BASIC DIGITAL THERMOMETER. CELSIUS AND FAHRENHEIT SCALES R Rt Rz R3 Rc Rs of 9.00 4.02 2.0 12.4 10.0 0 OC 5.00 4.02 2.0 5.11 5.0 11.8 1len 0.1% B Rn = 28kn nominal ALL values in kn The ICL7106 has a VIN span of ±2.0V and a VCM range of (V+ -0.5) volts to (V- +1) volts. R is scaled to bring each range within VCM while not exceeding VIN• VREF for both scales is 500mV maximum rending on the celsius range +199.9OC limited by the (short-term) maximum allowable sensor temperature. Maximum reading on the fahrenheit range is +199.9°F (+93.3°C) limited by the number of display digits. See Figure 11 and notes below. SCALE Slen 2.261en 1SIen ADJ A0580 1 v- Notes for Figure 11, Figure 12 and Figure 13 Since all 3 scales have narrow V/N spans. some optimization of ICL7106 components can be made to lower noise and preserve CMR. The table below shows the suggested values. Similar scaling can be used with the ICL7126 and ICL7136. REF HI REFLO ICL71 06 IN HI 1.DOIen ~ 307 COMMON This circuit allows "zero adjustmenr as well as slope adjustment. the IC18069 brings the input within the common-mode range. while the 5kO pots trim any offset at +218°K (-55°C). and set the scale factor. See Figure 13 and notes below. yv+ l ICL71 06 IN HI FIGURE 13. BASIC DIGITAL THERMOMETER. KELVIN SCALE WITH ZERO ADJUST n=l 7.SIen REF HI REFLO INLO 5 L T T ~ 307 COMMON SCALE VINRANGEM R1NT(kn) CAZ(jiF) K 0.223 to 0.473 220 0.47 C -0.25 to +1.0 220 0.1 F -0.29 to +0.996 220 0.1 For all: CREF =O.lI1F CINT = O.22!1F Cose=100pF Rose =100k0 INLO 8A0580 , v· FIGURE 12. BASIC DIGITAL THERMOMETER. KELVIN SCALE 14-9 AD590 ~----~------------o~w nn ZERO SET NO. 1 10mVI"C 101en 0.1% SOlen ~+_5Mw.n"""'~4--1"'" V+ 1181rn (IV MIN) 20kn FULL-SCALE V· VOUT-(Tz-Tj}x (1 OmVI"C) NO. 2 ADJUST • 101en +1001lA FIGURE 14. CENnGRADE THERMOMETER (O"C - +100"C) FIGURE 15_ DIFFERENTIAL THERMOMETER The ultra-low bias current of the ICL7611 allows the use of large value gain resistors, keeping meter current error under 1/2%, and therefore saving the expense of an extra meter driving amplifier. See Figure 14. The 50kO pot trims offsets in the devices whether internal or external, so it can be used to set the size of the difference interval. this also makes it useful for liquid level detection (where there will be a measurable temperature difference). See Figure 15. V+ r··· --- -- .......... ---- ...... ------_ .... -_ .. -_ .... ;• : + 1JlA1"K:• • ·._---. ----_ _--------------------; .... ·••••• •• '.. •• • l:• SEEBECK COEFFICIENT _ 4Cl!LVI"K TYPEK V+ = FIGURE 16_ COLD JUNCTION COMPENSAnON FOR TYPE K THERMOCOUPLE The reference junction(s} should be in close thermal contact with the AD590 case. V+ must be at least 4'1. while ICLB069 current should be set at 1mA • 2mA. Calibration does not require shorting or removal of the thermocouple: set R1 for V2 10.98mV. If very precise measurements are needed, adjust R2 to the exact Seebeck coefficient for the thermocouple used (measured or from table) note V1, and set R1 to buck out this voltage (i.e., set V2 = V 1)' For other thermocouple types, adjust values to the appropriate Seebeck coefficient. See Figure 16. = 14-10 AD590 COLUMN ---ROW SELECT ENABLE +1SV +1SV R (OPTION- 2 SELECT 13 AL) 2 1N&48 1 0 ENABLE 2 8 CHANNEL I 4 MUX 2 8 4 0 S I 2 HJ.CII4I I CHANNEL MUX 7 3 12 4 11 I 10 • FIGURE 17. MULnPLEXING SENSORS If shorted sensors are possible, a series resistor in series with the 0 line will limit the current (shown as R, above: only one is needed). A six-bit digital word will select one of 64 sensors. 14-11 I 3 AD590 Die Characteristics DIE DIMENSIONS: 37 xsax 14± 1mils METALLIZAnON: Type: Aluminum 1()()Ok Thickness: 1SkA± 1kA GLASSIVATION: Type: PSGlNitride PSG Thickness: 7kA ± 1.4kA Nitride Thickness: akA ± 1.2kA Metallization Mask Layout AD590 14-12 ICLB069 Low Voltage Reference December 1993 Features Description • Low Bias Current - SOIlA Min The ICL8069 is a 1.2V temperature compensated voltage reference. It uses the band-gap prinCiple to achieve excellent stability and low noise at reverse currents down to 501lA. Applications include analog-to-digital converters, digital-toanalog converters, threshold detectors, and volt\lge regulators. Its low power consumption makes it especially suitable for battery operated equipment. • Low Dynamic Impedance • Low Reverse Voltage • LowCost Ordering Information PART NUMBER PACKAGE MAXIMUM TEMPCO TEMPERATURE RANGE ICL8069CCZR O.OO5%fOC O"C to +70"C TO-92 ICL8069CCsa O.OO5%fOC OOC 10+70oC TO-52 ICL8069DCZR 0.0I%fOC O"C 10 +70oC To-92 TO-52 O.OI%1"C O"C to +70oC ICL8069CCBA O.OO5%fOC O"C to+70oC 8 LeadSOIC ICL8069DCBA O.OI%1"C O"C to +7O"C B Lead SOIC ICL8069CMSa O.OD5%1°C -55"C 10 +125°C TO-52 ICL8069DMSa O.OI%1"C -55°C to +125"C TO-52 ICL8069DCSa Pinouts ICLS069 (SOIC) TOP VIEW ICLS069 (TO-52) TOP VIEW COMP ICL8069 (T0-92) TOP VIEW ~ ~ CAUTION: These dill/ices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @Harris Corporation 1993 14-13 File Number 3172 ICL8069 Functional Block Diagrams SIMPLE REFERENCE (t.2V OR LESS) ----1~---..av 8.1kn • : ICL80It 1 10lI0 ::i!:___ : ~"~_~t--_} 2 "our ., (H0TE1) 4.71lf_... BUFFERED tOY REFERENCE USING A SINGLE SUPPLY +15V ICU08t 2~1 r" 1&lin 2 ~7 ~M1~' ra 4~~. 5 11en +10Vour 0.01 .... 1len 8.2Icn DOUBLE REGULATED tOOmY REFERENCE FOR ICL7t07 ONE·CHIP DPM CIRCUIT --~--~---~V 1CL7107 1 1CLI08t ~~ 2 101cn :..t!!2.- +V REF HI COMMON ~+----~ REFLO 14-14 Specifications ICLB069 Absolute Maximum Ratings Thermal Information Reverse Voltage. • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• See Note 2 Forward Current •••••••••••••••••••••••••••••••••••• 10mA Reverse Current. ••••••••••••••••••••••••••••••••••• 10mA Storage Temperature ••••••••••••••.•.•••••• -65"C to +15O"C Lead Temperature (Soldering, 10s) .••••.••••••••••••• +300"C Junction Temperature SOP ••••••••••••••••••••••.•••••••••••••••••• +15O"C Thermal Resistance 6JA SOIC Package ••••••••••••••••••••••••••••••••• 16O"C1W Operating Temperature ICL8069C •••••••••••••••••••••••••••••••• O"C to +70"C ICL8069M ••••••••••••••••.••••••••••••• -55"C to +125°C Power Dissipation •••••• Limited by MAX Forward/Reverse Current Electrical Specifications TA = +25"C Unless Otherwise specmed PARAMETERS TEST CONOmONS MIN TYP MAX UNITS 1.20 1.23 1.25 V Reverse Breakdown Voltage IR = SOOjiA Reverse Breakdown Voltage Change SOjiAS IR S 5mA - 15 20 mV Reverse Dynamic Impedance IR = SOjiA - 1 2 n IR = 500jiA - 1 2 n - 0.7 1 V 5 - I1V 1 - ppmlkHR Forward Voltage Drop IF = SOOjiA RMS Noise Voltage 10Hz S F S 10kHz IR = 500jiA Long Term Stability IR = 4.75mA - TA=+25°C Breakdown Voltage Temperature CoeffICient IR = 5OOjiA, TA = Operating Temperature Range (Note 3) ICL8069C ICL8069D Reverse Current Range 1.18Vto 1.27V - - 0.005 %l"C - 0.01 %l"C 0.050 - 5 mA NOTES: 1. If circuit strays in excess of 200pF are anticipated, a 4.7i1F shunt capacitor wHI ensure stability under all operating conditions. 2. In normal use, the reverse voltage cannot exceed the reference voltage. However when plugging units into a powered-up test fixture, an instantaneous voltage equal to the compliance of the test circuit will be seen. This should not exceed 20V. 3. For the military part, measurements are made at +25"C, -55°C, and +125°C. The unit is then classified as a function of the worst case TC from +25"C to -55"C, or +25"C to +125"C. 14-15 ICLB069 Typical Performance Curves 14 100mA >' 12 .§. ~ ~ w ~ !j . 10 g 4 ~ 2 o 0 5 .wC/ 6 // .J1. ~+26oc, , +125"C- ~ +1[7 10mA 10011 1mA REVERSE CURRENT (A) 0.2 FIGURE 1. VOLTAGE CHANGE AS A FUNCTION OF REVERSE CURRENT 1.245 ./ ,-- c::::. ~ ", /+25"C/ V::;OC"f 0.4 0.' 0.' 1.0 REVERSE VOLTAGE (VI FIGURE 2. REVERSE VOLTAGE AS A FUNCTION OF CURRENT IR-5OOIlA 1.240 JI' ".,.- ~ 1.220 1.215 -SO -25 1.2 0 +25 +50 +75 TEMPERATURE rC) +100 +125 FIGURE 3. REVERSE VOLTAGE AS A FUNCTION OF TEMPERATURE 14·16 ICM7170 IlP-Compatible Real-Time Clock December 1993 Features Description • 8-blt I1P Bus Compatible - Multiplexed or Direct Addressing The ICM7170 real time clock is a microprocessor bus compatible peripheral. fabricated using Harris' silicon gate CMOS LSI process. An 8-bit bidirectional bus is used for the data I/O circuitry. The clock is set or read by accessing the 8 internal separately addressable and programmable counters from 1/100 seconds to years. The counters are controlled by a pulse train divided down from a crystal oscillator circuit. and the frequency of the crystal is selectable with the onchip command register. An extremely stable oscillator frequency is achieved through the use of an on-chip regulated power supply. • Regulated OSCillator Supply Ensures Frequency Stability and Low Power • Time From 1/100 Seconds to 99 Years • Software Selectable 12124 Hour Format • Latched Time Data Ensures No Roll Over During Read • Full Calendar with Automatic Leap Year Correction • On-Chlp Battery Backup Swltchover Circuit • Access Time Less than 300ns • 4 Programmable Crystal Oscillator Frequencies Over Industrial Temperature Range • 3 Programmable Crystal OSCillator Frequencies OVer Military Temperature Range • On-Chlp Alarm Comparator and RAM • Interrupts from Alarm and 6 Selectable Periodic Intervals • Standby Micro-Power Operation: 1.211A Typical at 3.0V and 32kHz Crystal Applications • Data logging • Industrial Control Systems • Point·Of Sale Internal latches prevent clock roll-over during a read cycle. Counter data is latched on the chip by reading the 10Othseconds counter and is held indefinitely until the counter is read again. assuring a stable and reliable time value. Ordering Information TEMPERATURE RANGE The ICM7170 generates two types of interrupts. periodic and alarm. The periodic interrupt (100Hz. 10Hz, etc.) can be programmed by the internal interrupt control register to provide 6 different output Signals. The alarm interrupt is set by loading an on-chip 51-bit RAM that activates an interrupt output through a comparator. The alarm interrupt occurs when the real time counter and alarm RAM time are equal. A status register is available to indicate the interrupt source. An on-chip Power Down Detector eliminates the need for external components to support the battery back-up function. When a power down or power failure occurs, internal logic switches the on-chip counters to battery back-up operation. Reacllwrite functions become disabled and operation is limited to time-keeping and interrupt generation, resulting in low power consumption. • Portable and Personal Computars PART NUMBER The device access time (tACC) of 300ns eliminates the need for wait states or software overhead with most microprocessors. Furthermore. an ALE (Address Latch Enable) input is provided for interfacing to microprocessors with a multiplexed address/data bus. With these two special features. the ICM7170 can be easily interfaced to any available microprocessor. PACKAGE ICM71701PG -40"C to +85°C 24 Lead Plastic DIP ICM7170lDG -40"C to +85°C 24 Lead Ceramic ICM7170lBG -400C to +85°C 24 Lead SOIC ICM7170MDG -55OC to +12SoC 24 Lead Ceramic ICM7170AIPG -40"C to +85°C 24 Lead Plastic DIP ICM7170AIDG -40"C to +8SoC 24 Lead Ceramic ICM7170AIBG -40"C to +B5°C 24 Lead SOIC ICM7170AMDG -5SOC to +12SoC 24 Lead Ceramic NOTE: "A" Parts Screened to <511A ISTBy at 32kHz CAUTION: These devices are sensftillll to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright @ Harris Corporation 1993 14·17 File Number 3019 ·/CM7170 Pinouts ICM7170 (PDIP, CDIP) TOP VIEW ICM7170 (SOIC) TOP VIEW WIi 'liD ALE VDD Ci D7 DI os A2 AD A3 OSCOUT 3 M OSCIN Ci ALE INTSOURCE 5 D4 IN'i' D3 VSS D2 VBACKUP 8 D1 INT SOURCE 11 Al 9 Wii 'liD VDD VBACK\JP iFlfERil15T _1.,2'---_ _ _....r- Vas (GND) Functional Block DIagram OSCILLATOR CRYSTAL OSC OUT OSC IN INTERRUPTS ..-...I.-.. 'liD U24!!..... Wii ALE t--+I PERIODIC COMPARE { ~r--~ Ci INT 11 SOURCE VDD V~~KUP Vas .,·....,...· ..... DATA I/O "'·--~'·DO - ADDRESS} INPUTS AD-M 14-18 D7 Specifications ICM7170 Absolute Maximum Ratings Thermal Information Supply Voltage ••••••••••••••••••••••••••••••••••••• +B.ov Power Dissipation (Note 1) •••••••••••••••••••••••••• 500mW Storage Temperature Range ••••••••••••••••• -65"0 to +15O"C Lead Temperature (Soldering 1OS). • • • • • • • • • • • • • • • • • • • +3OO"C Input Voltage (Any Terminal) (Note 2) ••••• VDD +O.3V to Vas -0.3V Thermal Resistance 9JA Plastic Package •••••••••••••••••••. 75"CIW 12"CIW Ceramic DIP Package ••••••••••••••. 63"CIW 75"CIW SOIC Package ••••••••••••••••••••• Junction Temperature Plastic Package •••••••••••••••••••••••••••••••• +15O"C Ceramic Package •••••••••••••••••••••••••••••• +175"C CAUTION: StressflS above /hose Rsted In ·AbsoIute MaxImum RaUngs· may cause permanent demage to /he device. This Is a stress only ra6ng and operation of /he device at lllese or any other conditions above /hose indicated In /he operaUona/ sections of /his spacifica60n Is not imp/isd. DC Electrical Specifications TA = -40"C to +65"0, VDD +5V ±lO%, vBACKUP VDD ' Vas = OV Unless Otherwise Speclfled AIiIDD specJflC8t1ons Include all Input and output leakages (ICM7170 and ICM7170A) MIN TYP MAX UNITS Fosc = 32kHz 1.9 5.5 V Fosc = 1,2, 4MHz 2.6 - 5.5 V PARAMETER VDD Supply Range, VDO Standby Current, ISTaY(l) TEST CONOmONS Fosc = 32kHz Pins 1 - 8,15 - 22 and 24 = Voo ICM7170 - 1.2 20.0 IIA Voo=Vas; VBACKUP = Voo - 3.0V For ICM7170A See General Notes 5 ICM7170A - 1.2 5.0 IIA - 20 150 IIA - 0.3 1.2 rnA 1.0 2.0 rnA 0.8 V - V Standby Current, ISTay(2) Fosc=4MHz Pins 1 - 8,15 - 22 and 24 = Voo Voo=Vas; VBACKUP = Voo - 3.OV Operating Supply Current, 100(1) Fosc = 32kHz ReacUWrlte Operation at 100Hz Operating Supply Current, 10 0(2) Fosc = 32kHz ReacUWrite Operation at 1MHz Input Low Voltage (Except Osc.), VIL Voo =5.0V - Input High Voltage (Except Osc.), VIH Voo =5.0V 2.4 Output Low Voltage (Except Osc.), VOL IOL= 1.6mA - . 0.4 V Output High Voltage Except INTERRUPT (Except Osc.), VOH IOH = -4OO11A 2.4 - - V - Input Leakage Current, IlL VIN =Voo or Vas -10 0.5 +10 Tri-state Leakage Current (DO - D7),loL(1) Vo =Voo or Vas -10 0.5 +10 IIA IIA Backup Battery Voltage, VBATTERY Fosc = 1,2, 4MHz 2.6 Voo -l.3 V Backup Battery Voltage, VBATTERY Fosc = 32kHz leakage Current INTERRUPT, IOL(2) Vo=Voo 1.9 INTSOURCE Connected to Vas - - CAPACITANCE DO - 07, Coo CAPACITANCE AO - M, CAODREas CAP. RD, WR, CS ALE, CCONTROL Total Osc. Input Cap., CIN Osc. 14-19 0.5 8 Voo -l.3 V 10 IIA - pF 6 - 3 - 6 pF pF pF ..JW c(CI) -0 CJD. Wa: D.;:) Cl)D. Specifications ICM717,O AC Electrical Specifications TA = -40"C to +85"C; VDi> = +5V ± 10%, VBACKUP = VDD , DO - 07 Load CapacItence .15OpF, V1L =0.4V, V1H = 2.BV, Unless Otherwise Specified PARAMETER MIN MAX UNITS 250 ns 300 ns READ CYCLE TiMING - READ to DATA Valid, tRD ADDRESS Valid to DATA Valid, tACe READ Cycle Time, levc 400 Read High Time,lRH 150 - ns ns - 25 ns ADDRESS to READ Set Up Time, WI 50 - ns ADDRESS HOLD Time After READ,lAA 0 - ns ADDRESS Valid to WRITE Strobe, tAD 50 - ns ADDRESS Hold Time for WRITE, tWA 0 - ns AD High to Bus Trl-state, lRH WRITE CYCLE TIMING WRITE Pulse Width, Low, tWL 100 WRITE High Time, tWH 300 DATA IN to WRITE Set Up Time, tow 100 DATA IN Hold Time After WRITE, two 30 WRITE Cycle Time, levc 400 - ALE Pulse Width, High, h 50 - ns ADDRESS to ALE Set Up Time, tAL 30 - ns ADDRESS Hold Time After ALE, \A 30 - ns ns ns ns ns ns MULTiPLEXED MODE TIMING NOTE: 1. TA=25·C 2. Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than VDD or less than Vss may cause destructive device latchup. For this reason, it is reconvnended that no inputs from external sources not operating on the same power supply be applied to the device befDre its supply Is established, and that in multiple supply systems, the supply to the ICM7170 be turned on first " 14-20 ICM7170 Timing Diagrams AO.A4,CS DO·D7 FIGURE 1. READ CYCLE TIMING FOR NON·MULTIPLEXED BUS (ALE .. AO.A4.CS V.H•WR .. V.tt> ADDRESS VALID. CS LOW tAD-- l--twA . tCYC I tWL 'l / I . • tDIY -tWD- "" INPUT DATA VALID FIGURE 2. WRITE CYCLE TIMING FOR NON·MULTIPLEXED BUS (ALE = VIII. iffi = VIII) AD .. A4, DO .. 07, Ci ~IIIIII'" -----..,.. ~----....... i--tc---- 11""",,1. OUTPUT DATA VAUD ',',11,""1 tLl. - -..... ALE ..JW cc(l) -0 (JQ. Wa: tAL 0.:;) (1)0. FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR .. VIHl 14·21 ICM7170 Timing Diagrams (Continued) - ...,..........." ....AC ADDRESS VAUD, CS LOW 1>-'.....",.., .." AO· At, DO· 07, Ci tLL ALE ---'" INPUT DATA VAUD >,"""""'1''''4 I- tow"::r- I--tLA --two ~twA- V-- -tALtAD tcYC ~-twL- ~ Wli FIGURE 4. WRrTE CYCLE nMING FOR MULTIPLEXED BUS (Ro. "- Vw Pin Description PIN NUMBER SOIC PIN NUMBER WR 1 19 ALE 2 20 Address Latch Enable Input Chip Select Input SIGNAL DESCRIPTION Write Input 3 21 4·8 22·2 OSCOUT 9 3 OSCIN 10 4 OsclUator Input INTSOURCE 11 5 Interrupt Source INTERRUPT 12 6 Interrupt Output Vss(GNO) 13 7 Digital Common VBACKUP 14 8 Battery Negative Side DO· 07 CS A4-AO Address Inputs OsciUator Output 15·22 9·16 Veo 23 17 POSitive Digital Supply OataVO RO 24 18 Read Input TABLE 1. COMMAND REGISTER FORMAT COMMAND REGISTER ADDRESS (10001b, 11h) WRrTE-QNLY 07 06 05 D4 D3 02 01 DO nla nla NormaVTest Mode Interrupt Enable RunlStop 12124 Hour Format Crystal Frequency Crystel Frequency TABLE 2. COMMAND REGISTER BIT ASSIGNMENTS D5 TESTBrT D4 INTERRUPT ENABLE D3 RUN/STOP D2 0 Normal Mode 0 Interrupt disabled 0 Stop 1 Test Mode 1 Interrupt enable 1 Run 14-22 24f12 HOUR FORMAT Dl DO CRYSTAL FREQUENCY 0 12 Hour Mode 0 0 32.768kHz 1 24 Hour Mode 0 1 1.048576MHZ 1 0 2.097152MHz 1 1 4.194304MHz ICM7170 TABLE 3. ADDRESS CODES AND FUNCTIONS DATA ADDRESS A4 A3 A2 AI AO HEX FUNCTION D7 0 0 0 0 0 00 Counter-1/100 seconds 0 0 0 0 1 01 Counter-hours 0 0 1 0 02 Counter-minutes 0 0 0 1 1 03 Counter-seconds 0 0 1 0 0 04 Counter-month OS D4 D3 D2 D1 DO - - - 0-23 - - - - - 1 -12 0-59 0-59 0 0 1 0 1 05 Counter-date 0 0 1 1 0 06 Counler-year 0 0 1 1 1 07 Counter-day of week - 0 1 0 0 0 08 RAM-1/100 seconds M 0 1 0 0 1 09 RAM-hours - M t M 0 1 0 1 0 OA RAM-minutes M - 0 1 0 1 1 OB RAM-seconds M - 0 1 1 0 0 OC RAM-month M - - - 1 -12 - - 1 -31 12 Hour Mode 0 1 1 0 1 00 RAM-date M 0 1 1 1 0 OE RAM-year M 0 1 1 1 1 OF RAM-day of week M 1 0 0 0 0 10 Interrupt Status and Mask Register + 1 0 0 0 1 11 Command register - - VALUE 0-99 t 12 Hour Mode 0 D6 - 1 -12 - - 1 - 31 0-99 - - - - 0-6 0-99 - 0-23 - 1-12 0-59 0-59 0-99 - - - - 0-6 - NOTES: Addresses 10010 to 11111 (12h to 1Fh) are unused. '+' Unused btt for Interrupt Mask Register, MSB bit for Interrupt Status Register. '-' Indicates unused bits. . 't' AMIPM Indicator bit In 12 hour format Logic "0" Indicates AM, logic "1" indicates PM 'M' Alarm compare for particular counter will be enabled If btt Is set to logic "0" TABLE 4. INTERRUPT AND STATUS REGISTERS FORMAT INTERRUPT MASK REGISTER ADDRESS (10000b,10h) WRITE-oNLY D7 D6 D5 D4 D3 D2 01 DO .JW NOT USED DAY HOUR MIN SEC 1110 SEC 1/100 SEC ALARM -0 On. Wa: -+ Alarm/Compare Mask Bit 01((1) Periodic Interrupt Mask Bits ~ INTERRUPT STATUS REGISTER ADDRESS (10000b,10h) READ-ONLY D7 D6 OS D4 D3 D2 D1 DO GLOBAL INTERRUPT DAY HOUR MIN SEC 1/10 SEC 1/100 SEC ALARM Periodic and Alarm Flags ~ Periodic Interrupt Flags 14-23 -+ Alarm Compare Rag n.:::::I (l)n. ICM7170 Detailed Description Oscillator The ICM7170 has an onboard CMOS Pierce oscillator with an intemally regulated voltage supply for maximum accuracy, stability, and low power consumption. It operates at any of four popular crystal frequencies: 32.768kHz, 1.046576MHz, 2.097152MHz, and 4.194304MHz (Note 1). The crystal should be designed for the parallel resonant mode of oscillation. In addition to the crystal, 2 or 3 load capacitors are required, depending on the circuit topology used. The oscillator output is divided down to 4000Hz by one of four divider ratios, determined by the two frequency selection bits in the Command Register (DO and 01 at address 11 H). This 4000Hz is then divided down to 100Hz, which is used as the clock for the counters. Time and calendar information is provided by 8 consecutive, programmable counters: 100ths of seconds, seconds, minutes, hours, day of week, date, month, and year. The data is in binary format with 8 bits per digit. See Table 3 for address information. Any unused bits are held to a logic "fY' during a read and ignored during a write operation. NOTE: I. 4.94304MHz is not available over military temperature range. Alarm Compare RAM On the chip are 51 bits of Alarm Compare RAM grouped into words of different lengths. These are used to store the time, ranging froin 10ths of seconds to years, for comparison to the real-time counters. Each counter has a corresponding RAM word. In the Alarm Mode an interrupt is generated when the current time is equal to the alarm time. The RAM contents are compared to the counters on a word by word basis. If a compariSon to a particular counter is unnecessary, then the appropriate 'M' bit in Compare RAM should be set to logic ·1". The 'M' bit, referring to Mask bit, causes a particular RAM word to be masked off or ignored during a compare. Table 3 shows addresses and Mask bit information. Periodic Interrupts The interrupt output can be programmed for 6 periodic signals: 100Hz, 10Hz, once per second, once per minute, once per hour, or once per day. The 100Hz and 10Hz interrupts have instantaneous errors of :l:2.5% and ±D.15% respectively. This is because non-integer divider circuitry is used to generate these signals from the crystal frequency, which Is a power of 2. The time average of these errors over a 1 second period, however, is zero. Consequently, the 100Hz or 10Hz interrupts are not suitable as an aid in tuning the oscillator; the 1 second interrupt must be used instead. See General Notes 6. The periodic interrupts can occur concurrently and in addition to alarm interrupts. The periodic interrupts are controlled by bits in the interrupt mask register, and are enabled by setting the appropriate bit to a "1" as shown in Table 4. Bits 01 through D6 in the mask register, in conjunction with bits 01 through D6 of the status register, control the generation of interrupts according to Figure 4. The interrupt status register, when read, Indicates the cause of the interrupt and resets itself on the rising edge of the RD signal. When any of the counters having a corresponding bit in the status register increments, that bit is set to a "1" regardless of whether the corresponding bit in the Interrupt mask register is set or not. ALARM MASK BIT INTERRUPT MASK REGISTER L..:I~T'""""...&."T""'-lrT"'-lr"T"" gJ ~ VIG INT SOURCE PIN II INTERRUPT STATUS • Ri5 OF ADD HEX 10. >RESET REGISTER L..:I~-""'",&,-""'"""'-"""-+T ALARM FLAG BIT GLOBAL INTERUPT FLAG BIT FIGURE 4. INTERRUPT OUTPUT CIRCUIT 14-24 INTERRUPT ENABLE COMMAND REGISTER BIT 04 ICM7170 Consequently, when the status register is read it will always indicate which counters have increments and if an alarm compare occurred, since the last time it was read. This requires some special software consideretions. If a slow interrupt is enabled (i.e. hourly or daily), the program must always check the slowest interrupt that has been enabled first, because all the other lower order bits in the status register will be set to "1" as well. Bit 07 is the global interrupt bit, and when set to a "1", indicates that the ICM7170 did indeed generate a hardware interrupt. This is useful when other interrupting devices in addition to the ICM7170 are attached to the system microprocessor, and all devices must be polled to determine which one generated the interrupt. See General Notes 6. Interrupt Operation The Interrupt Output N-channel MOSFET (Figure 4) is enabled whenever both the Interrupt Enable bit (04 of the Command Register) and a mask bit (DO - 06 of the Interrupt Mask Register) are set. The transistor is turned ON when a flag bit is set that corresponds to one of the set mask bits. This also sets the Global Interrupt Flag Bit (07 of the Interrupt Status Register). It is turned OFF when the Interrupt Status Register is read. An interrupt can occur in both the operational and standby modes of operation. Since system power is usually applied between Voo and Vss' the user can connect the Interrupt Source (pin No. 11) to Vss. This allows the Interrupt Output to turn on only while system powers applied and will not be pulled to Vss during standby operation. If interrupts are required only during standby operation, then the interrupt source pin should be connected to the battery's negative side (VBACKUP)' In this configuration, for example, the interrupt could be used to turn on power for a cold boot. Power Down Detector The ICM7170 contains an on-chip power down detector that eliminates the need for external components to support the battery-backup switchover function, as shown in Figure 5. Whenever the voltage from the Vas pin to the VBACKUP pin Is less than approximately 1.0V (the VTH of the N-channel MOSFET), the data bus 1/0 buffers in the ICM7170 are automatically disabled and the chip cannot be read or written to. This prevents random data from the microprocessor being written to the clock registers as the power supply is going down. Actual switchover to battery operation occurs when the voltage on the VBACKUP pin is within ±5OmV of Vss. This switchover uncertainty is due to the offset voltage of the CMOS comparator that is used to sense the battery voltage. During battery backup, device operation is limited to timekeeping and interrupt generation only, thus achieving micropower current drain. If an external battery-backup switchover circuit is being used with the ICM7170, or if standby battery operation is not required, the VBACKUP pin should be pulled up to Voo through a 2K resistor. Time Synchronization Time synchronization is achieved through bit 03 of the Command Register, which is used to enable or disable the 100Hz clock from the counters. A logic "1" allows the counters to function and a logic "a' disables the counters. To accurately set the time, a logic "0- should be written into 03 and then the desired times entered into the appropriate counters. The clock is then started at the proper time by writing a logic "1" into 03 of the Command Register. Latched Data To prevent ambiguity while the processor is gathering data from the registers, the ICM7170 incorporates data latches and a transparent transition delay circuil. POSITIVE SUPPLY RAIL (+IV) ~----------------------------~-------+ VDD UODiSABLE R2 L-WIr--I VUCK 2K 1-_------------------.....--. VIQ INTERNAL GROUND PIN 14 Vss DIGITAL GROUNDPIN 13 L-_________________________________________________ FIGURE 5. SIMPUFIED ICM7170 BAnERY BACKUP CIRCUIT 14-25 ICM7170 By accessing the 100ths of seconds counter an internal store signal is generated and data from all the counters is transferred into a 36-bit latch. A transition delay circuit will delay a 100Hz transition during a READ cycle. The data stored by the latches is then available for furtherprocessl!:!a until the 10aths of seconds counter Is read again. If a RD signal is wider than 0.01 sec., 100Hz counts will be ignored. t---IDI-·XI OSCIN Control Unes The RD, WR, and CS signals are active low inputs..Q!ta is placed on the bus from counters or registers when RD is a ~c "0". Data is t!!.!lsferre~ counters or registers when WR is a Io.s!£ "0". RD and WR must be accompanied by a logical "(Y' CS as shown in Figures 2 and 3. The ICM7170 will also work satisfactorily with CS grounded. In this mode, access to the ICM7170 is controlled by AD and WR only. With the ALE (Address Latch Enable) input, the ICM7170 can be Interfaced directly to microprocessors that use a multiplexed address/data bus by connecting the address lines AO - A4 to the data lines DO - 04. To address the chip, the address is placed on the bus and ALE is strobed. On the failing edge, the address and CS in~ation is read into the address latch and buffer. RD and WR are used in the same way as on a non-multiplexed bus. If a non-multiplexed bus is used, ALE should be connected to Voo. Test Mode The test mode is entered by setting 05 of the Command Register to a logic "1". This connects the 100Hz counter directly to the oscillator's output. ~- SpF-35pF The new load configuration (Figure 6) allows these two conditions to be met independently. The two load capacitors, C1 and C2, provide a fixed load to the oscillator and crystal. C3 adjusts the frequency that the circuit resonates at by reducing the effective value of the crystal's motional capacitance, CO. This minute adjustment does not appreciably change the load of the overall system, therefore stability is no longer affected. by tuning. Typical values for these capacitors are shown in Table 5. C1 and C2 must always be greater than twice the crystal's recommended load capacitance in order for C3 to be able to trirri the frequency. Some experimentation may be necessary to determine the ideal values of C1 and C2 for a particular crystal. TABLE 5. TYPICAL LOAD CAPACITOR VALUES T ,. OSCIN CRYSTAL FREQUENCY LOAD CAPS (C1. C2) TRIMMER CAP 32kHz 33pF 5-50pF 1MHz 33pF S-5QpF 2MHz 2SpF S -SOpF 4MHz 22pF S -100pF (ca) This three capacitor tuning method will be more stable than the original design and is mandatory for 32kHz tuning fork crystals: without it they may leap into an overtone mode when power is initially applied. C3 OSCOUT F-t? Cl~2xLOAD FIGURE 7. ORIGINAL OSCILLATOR CONFIGURATION Voo XI 11 ICM7170 Load Design: A new oscillator load configuration, shown in Figure 6, has been found that eliminates start-up problems sometimes encountered with 32kHz tuning fork crystals. ~D __. . OSCOUT F-t?~ Oscillator Considerations ~ ..... " Voo r!!. ICM7170 FIGI,IRE 6. NEW OSCILLATOR CONFIGURATION Two conditions must be met for best oscillator performance: the capacitive load must be matched to both the inverter and crystal to provide the ideal conditions for oscillation, and the resonant frequency of the oscillator must be adjustable to the desired frequency. In the original design (Figure 7), these two goals were often at odds with each other; either the oscillator was trimmed to frequency by detuning the load circuit, or stability was increased at the expense of absolute frequency accuracy. The original two-capacitor circuit (Figure 7) will continue to work as well as it always has; and may continue to be used in applications where cost or space is a critical consideration. It is also easier to tune to frequency since one end of the trimmer capacitor is fixed at the AC ground of the circuit (Voo), minimizing the disturbance cause by contact between the adjustment tool and the trimmer capacitor. Note that in both configurations the load capacitors are connected between the oscillator pins and Vol> - do not use Vss as an ACground. Layout: Due to the extremely low current (and therefore high impedance) deSign of the ICM7170s oscillator, special attention must be given to the layout of this section. Stray capacitance should be minimized. Keep the oscillator traces on a 14-26 ICM7170 single layer of the PCB. Avoid putting a ground plane above or below this layer. The traces between the crystal, the capacitors, and the ICM7170 OSC pins should be as short as possible. Completely surround the oscillator components with a thick trace of Voo to minimize coupling with any digital signals. The final assembly must be free from contaminants such as solder flux, moisture, or any other potential sources of leakage. A good solder mask will help keep the traces free of moisture and contamination over time. Oscillator Tuning Trimming the oscillator should be done indirectly. Direct monitoring of the oscillator frequency by probing OSC IN or OSC OUT is not accurate due to the capacitive loading of most probes. One way to accurately trim the ICM7170 is by turning on the 1 second periodic interrupt and trimming the oscillator until the interrupt period is exactly one second. This can be done as follows: 1. Turn on the system. Write a OOH to the Interrupt Mask Register (location 10H) to clear all interrupts. 2. Set the Command Register (location 11 H) for the appropriate crystal frequency, set the Interrupt Enable and Run/Stop bits to 1, and set the Test bit to O. 3. Write a 08H to the Interrupt Mask Register to turn on the 1 second interrupt. 4. Write an interrupt handler to read the Interrupt Status Register after every interrupt. This resets the interrupt and allows it to be set again. A software loop that reads the Interrupt Status Register several times each second will accomplish this also. 5. Connect a precision period counter capable of measuring 1 second within the accuracy desired to the interrupt output. If the interrupt is configured as active low, trigger on the falling edge. If the interrupt is active high, trigger on the rising edge. Be sure to measure the period between when the transistor turns ON, and when the transistor turns ON a second later. 6. Adjust C3 (C2 for the two-capacitor load configuration) for an interrupt period of exactly 1.000000 seconds. Application Notes Digital Input Termination During Backup To ensure low current drain during battery backup operation, none of the digital inputs to the ICM7170 should be allowed to float. This keeps the input logiC gates out of their transition region, and prevents crossover current from flowing which will shorten battery life. The address, data, CS, a~ ALE should be pulled to either Voo or Vss, and the RD and WR inputs should be pulled to VOD- This is necessary whether the internal battery switchover circuit is used or not. E!!!!l IBM/PC Evaluation Circuit Figure 8 shows the schematic of a board that has been designed to plug into an IBM PCIXT (Note 1.) or compatible computer. In this example CS is perman.!!:!!ly tiedJ2.W and access to the chip is controlled by the RD and WR pins. These si~ are generated by U1, which gates the ISMs iOR and lOW with a device select signal from U3, which is functioning as an I/O block address decoder. DS1 selects the interrupt priority. U5 is used to isolate the ICM7170 from the PC databus for test purposes. It is only required on heavily-loaded TTL databusses - the ICM7170 can drive most TTL and CMOS databusses directly. Since the IBM PClXT (Note 1) requires a positive interrupt transition, the ICM7170S interrupt output transistor has been configured as a source follower. As a source follower, the interrupt output signal will swing between OV and 2.5V. When trimming the oscillator, the frequency counter must be triggered on the rising edge of the interrupt signal. TABLE 6. BAnERIES CRYSTALS Panasonic Saronlx 32kHz NTF3238 Rayovac Statek 32kHz CX-1V Selko 2MHz GT-38 NOTE: 1. IBM, IBM PC, and IBM XT are trademarks of IBM Corp. 14-27 ICM7170 A11AEN>---------------------~ A28 AS >-________.J A25 AS >_----........--------..J A24 A7 >_---------------1 A23A8 >-_ _ _ _ _ _ _ _..J A22A8>------------------I ~1AO>---~~----~ ~O A1 >---~~--~ A28A2>---~I_I~~~~--_IrRl A28 ~ A27 A4 >---I-..J >---I--..J -r:... TP1 B25IRQ3~ R1 5V B3.1128 ~ GNDB1.B31 POSITIVE INTERRUPT 1K OS! INTERRUPT SELECT FIGURE 8. IBM PC INTERFACE FOR ICM7170 14·28 ICM7170 General Notes I. TIME ACCESS - To update the present time registers (Hex 00 07) the 1/1 00 register must be read first. The 7 real time counter registers (Hours, Minutes, Seconds, Month, Date, Day, and Year) data are latched only if the 1/100 second counter register is read. The 111 00 seconds data ilseH Is not latched. The real time data will be held in the latches until the 1/1 00 seconds is read again. See the data sheet section on LATCHED DATA. None of the RAM data is latched since it Is static by nature. 2. REGULATED OSCILLATOR - The oscillator's power supply Is voltage regulated with respect to Voo. In the 32kHz mode the regulator's amplitude is l:VIn + Vip (=1.8V). In the I, 2, and 4MHz mode the regulator's amplitude is l:VIn + VIn + Vip (=2.6V). As a result, signal conditioning Is necessary to drive the oscillator with an extemal signal. In addition, it Is also necessary to buffer the oscillator's signal to drive other extemel clocks because of its reduced amplitude and offset voltage. 3. INTERNAL BATTERY BACKUP - When the ICM7170 is using its own intemal battery backup circuitry, no other circuitry interfaced to the ICM7170 should be active during standby operation. When Voo (+5V) is tumed off (Standby operation), Voo should equal Vss OV. AIIICM7170 I/O should also equal Vss. At this time, the VBACKUP pin should be 2.6V to 3.5V below Vss when using a Uthium battery. 4. EXTERNAL BATTERY BACKUP - The ICM7170 may be placed on the same power supply as battery-backed up RAM by keeping the ICM7170 in Its operational state and having an extemal circuit switch betwean system and backup power for the ICM7170 and the RAM. In this case VBACKUP should be pulled up to Voo through a 2K resistor. Although the ICM7170 Is always ·on" in this configuration, its current consumption will typicelly be less than a microamp greater than that of standby operation at the same supply voltage (See Note 9). Proper consideration must be given to disabling the ICM7170s and the RAMs I/O before system power Is removed. This Is important because meny microprocessors can generate spurious write signals when their supply falls below their specified operating voltage limits. NANDing 2!.(or WR) with a POWERGOOD signal will create a CS (or WR) that Is only valid when system power Is within specifications. The POWERGooD signal should be generated by an accurate supply monitor such as the ICL7665 underlover voltage detector. An alternate method of disabling the ICM7170's I/O is to puU VBACKUP down to under a volt above Vss (Vss < VBACKUP <1.0V). This will cause the ICM7170 to internally disable all I/O. Do not allow VBACKUP to equal VSSo since this could cause oscillation of the battery backup comparator (See Figure 5). VBACKUP Vss + 0.5V will disable the I/O and provide enough overdrive for the comparator. = = 5. ICM7170A PART - The ICM7170A part is binned at final test for a 32.768kHz maxlmum current of 511A. All other specifications remain the same. 6. INTERRUPTS - The Interrupt Status Register (address 10H) always indicates which of the real time counters have been incremented since the last time tha register was read. NOTE: this is independent of whether or not any mask bits are set. The status register Is always reset immediately after it Is read. If an interrupt from the ICM7170 has occurred since the last time the status register was read, bit 07 of the register will be set. If the source was an alarm interrupt, bit DO will also be set. II the interrupt transistor has been turned on, reading the Interrupt Status Register will reset it. To enable the periodic interrupt, both the Command Register's Interrupt Enable bit (04) and at least one bit in the Interrupt Mask Register (01 - 06) must be set to a I. The periodic interrupt is triggered when the counter corresponding to a mask bit that has bean set Is incremented. For example, if you enable the I second interrupt when the current value in the l00ths counter Is 57, the first interrupt will occur 0.43 seconds later. All subsequent interrupts will be exactiy one second apart. The interrupt servica routine should then read the Interrupt Status Register to rase! the interrupt transistor and, If necessary, determine the cause of the interrupt (periodic, alarm, or non-ICM7170 generated) from the contents of the status register. To enable the alarm interrupts, both the Command Register's Interrupt Enable bit (04) and the Interrupt Mask Register's Alarm bit (DO) must be set to a I. Each time there is an exact match betwean the values in the alarm register and the values In the real time counters, bits DO and 07 of the Interrupt Status Register will be set to a 1 and the N-channel interrupt transistor will be turned on. As with a periodic interrupt, the service routine should then read the Interrupt Status Register to reset the interrupt transistor and, since periodic and alarm interrupts may be simultaneously enabled, determine the cause of the interrupt if necessary. Mask bits: The ICM7170 alarm interrupt compares the data in the alarm registers with the data in the real time registers, ignoring any registers with the mask bit set. For exemple, if the alarm register is set to 11-23-95 (Month-Day-Year), 10:59:00:00 (Hour-Minutes-Seconds-Hundredths), and DAY = XX (XX = masked off), the alarm will generate a single interrupt at 10:59 on November 23,1995.11 the alarm register Is set to II-XX-95, 10:XX:00:00, and DAY =2 (2 =Tuesday); the alarm will generate one interrupt fNery minute from 10:00-10:59 on fNery Thesday in November, 1995. NOTE: Masking off the l00ths of a second counter has the same effect as setting it to 00. 7. RESISTOR IN SERIES WITH BATTERY - A 2K resistor (R2) must be placed in series with the battery backup pin of the ICM7170. The UL laboratories have requested the resistor to limit the charging and discharging currant to the battary. The resistor also serves the purpose of degenerating parasitic SCR action. This SCR action mey occur if an input Is applied to the ICM7170, outside of its supply voltage range, while it is in the standby mode. 8. VBACKUP DIODE - Uthium batteries may explode if charged or if discharged at too high a rate. These conditions could occur if the battery was installed backwards or in the case of a gross componentfailure. A lN914-type diode placed in series with the battery as shown in Figure 8 will prevent this from occurring. A resistor of 2Mf.I or so should parallel the diode to keep the VBACKUP terminal from drifting toward the Vss terminal and shutting off ICM7170 I/O during normal operation. 9. SUPPLY CURRENT - ICM7170 supply current is predominantly a function of oscillator frequency and databus actMty. The lower the oscillator frequency, the lower the supply current. When there Is IitUe or no activity on the data, address or control lines, the current consumption of the ICM7170 in its operational mode approaches that of the backup mode. 14-29 DATA ACQUISITIO_ 15 HARRIS QUALITY AND RELIABILITY PAGE HARRIS QUALITY . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . 15-3 INTRODucnON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 THE ROLE OF THE QUALITY ORGANIZAnON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 THE IMPROVEMENT PROCESS. . . . . . . . .. . . . . . . . . .. . . . .. . . . .. . . . . . . . . .. . . . .. . .. . . . . .. . . . . . . . . 15-3 DESIGNING FOR MANUFACTURABILITY . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 15-3 SPECIAL TESTING...................... ........•......................................... 15-5 HARRIS SEMICONDUCTOR STANDARD PROCESSING FLOWS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 CONTROLLING AND IMPROVING THE MANUFACTURING PROCESS· SPC/DOX . . . . . . . . . . . . . . . . . . . . • 15-8 AVERAGE OUTGOING QUALITY (AOQ). . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . . • . . . . . • . . . • . . • 15-9 Training. .. . .. . . • . . . . . . . . . . . . . . . . . . . . . . . .. • . . . . . . .. . . ••. . . . . . . .. . . . . •.. . . . .. . .. ... . .. . .• 15-9 Incoming Materials. . . .. . .. .. . . . .. . . . . . . . . . . ..... . . . .. . . . .. . . . ..... ..... .. . . . .. .•. .. . . ••.• . 15-9 CALIBRAnON LABORATORy............................................................... 15-11 MANUFACTURING SCIENCE· CAM, JIT, TPM .. . .. .. . . . . .. . . . . . .. . . . . . . .. . . . .. .. . . . . .. .. . . .. . . . 15-11 Computer Aided Manufacturing (CAM) . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Just In Time (JIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Total Productive Maintenance (TPM). . . . . .. . .. . . . . .. . .. .. .. . .. . . . . . . .. . . . . . . . .. . . . . .. .. . . .. . . . 15-11 HARRIS RELIABILITY ..................•........••....•..•.•......•..........•........ '" .. 15-12 PROCESSIPRODUCTIPACKAGE QUALIRCATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 PRODUCTIPACKAGE RELIABITY MONITORS. .. . . . ... . ... . . . ... . . .... . .... . .. . . . .... . . . . .. .. . . 15-12 FIELD RETURN PRODUCT ANALYSIS SySTEM................................................. 15-13 FAILURE ANALYSIS LABORATORY.. . . . .. . . . .. . . . .•. . . .• . . . .. .• . .. . . . . . .• . ... . . . . .•... . . . . . . . 15-16 ANALYnCAL SERVICES LABORATORY. .. . .. .. .. . .. . . . .. . .. .. . . . .. . . . .. .. . .. . . . . .. . .. . . . . . . . • 15-16 RELIABILITY FUNDAMENTALS AND CALCULAnON OF FAILURE RATE. . . . .• . . . .•. . .. . .. . ..• . . .. • . 15-17 Failure Rate Calculations. . . . . .. .•. . . ••. . •. . . . . . .. . . . ••. . . .. .• . . . . . . . . . . . .. . . ... .. . .. . .• .. . . 15-17 Acceleration Factors .•... . . • . . • . . . . . • . . • . . . . . . . . . . • • . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 Activation Energy. . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . • . . . . . • . . . . . . . . . . 15-18 15·1 Harris Quality The Improvement Process Introduction Success in the integrated circuit industry means more than simply meeting or exceeding the demands of today's market. It also includes anticipating and accepting the challenges of the future. It results from a process of continuing improvement and evolution, with perfection as the constant goal. t IMPACTON PRODUCT auAUTY Harris Semiconductor's commitment to supply only top value integrated circuits has made quality improvement a mandate for every person in our work force - from circuit designer to manufacturing operator, from hourly employee to corporate executive. Price is no longer the only determinant in marketplace competition. Quality, reliability, and performance enjoy significantly increased importance as measures of value in integrated circuits. Quality in integrated circuits cannot be added on or considered after the fact. It begins with the development of capable process technology and product design. It continues in manufacturing, through effective controls at each process or step. It culminates in the delivery of products which meet or exceed the expectations of the customer. The Role of the Quality Organization The emphasis on building quality into the design and manufacturing processes of a product has resulted in a significant refocus of the role of the Quality organization. In addition to facilitating the development of SPC and DOX, Quality professionals support other continuous improvement tools such as control charts, measurement of equipment capability, standardization of inspection equipment and processes, procedures for chemical controls, analysis of inspection data and feedback to the manufacturing areas, coordination of efforts for process and product improvement, optimization of environmental or raw materials quality, and the development of quality improvement programs with vendors. At critical manufacturing operations, process and product quality is analyzed through random statistical sampling and product monitors. The Quality organization's role is changing from policing quality to leadership and coordination of quality programs or procedures through auditing, sampling, consulting, and managing Quality Improvement projects. To support specific market requirements, or to ensure conformance to military or customer specifications, the Quality organization still performs many of the conventional quality functions (e.g., group testing for military products or wafer lot acceptance). But, true to the philosophy that quality is everyone's job, much of the traditional on-line measurement and control of quality characteristics is where it belongs - with the people who make the product. The Quality organization is there to provide leadership and assistance in the deployment of quality techniques, and to monitor progress. STAGE IV 1 PRODUCT ~l OPllMiZAnoN STAGE "I PROCESS OPTIMIZAll0N STAGE" PROCESS CONTROL STAGE I PRODUCT SCREENING SOPHISTICATION OF QUAUTYTECHNOLOGY - FIGURE 1. STAGES OF STATISTICAL QUALITY TECHNOLOGY Harris Semiconductor's quality methodology is evolving through the stages shown in Figure 1. In 1981 we embarked on a program to move beyond Stage I, and we are currently in the transition from Stage III to Stage IV, as more and more of our people become involved in quality activities. The traditional "quality" tasks of screening, inspection, and testing are being replaced by more effective and efficient methods, putting new tools into the hands of all employees. Table 1 illustrates how our quality systems are changing to meet today's needs. Designing for Manufacturability Assuring quality and reliability in integrated circuits begins with good product and process design. This has always been a strength in Harris Semiconductor's quality approach. We have a very long lineage of high reliability, high performance products that have resulted from our commitment to design excellence. All Harris products are designed to meet the stringent quality and reliability requirements of the most demanding end equipment applications, from military and space to industrial and telecommunications. The application of new tools and methods has allowed us to continuously upgrade the design process. Each new design is evaluated throughout the development cycle to validate the capability of the new product to meet the end market performance, quality, and reliability objectives. The validation process has four major components: 15-3 1. Design simulation/optimization 2. Layout verification 3. Product demonstration 4. Reliability assessment. ~~ ........ c(~ID o!$ !aul a: a: a:Q c(z Xc( Harris QUtJlity TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS AREA WaferFab MANUFACTURING CONTROLS FUNCTION X • JAN Self-AudH • Environmental RoomlHood Particulates - Temperature/Humidity - Water Quality - X X • Product Junction Depth Sheet Resistivities Defect Density CrHical Dimensions - Visual Inspection Lot Acceptance X X X X X X - - Capacitance Voltage Changes • Process Film Thickness Implant Dosages - Conformance to Specification • Equipment Repeatability Profiles Calibration Preventive Maintenance - Assembly QA/QC MONITOR AUDIT X X X X X X X X X X - Water Quality • Product - Documentation Check Dice Inspection - Wire Bond Pull Strength/Controls X X - Ball Bond Shear/Controls - Die Shear Controls - Post-BondlPre-Seal Visual Fine/Gross Leak PINDTest Lead Finish Visuals, Thickness Solderability X X X X - • Process Operator Quality Performance Saw Controls - - - Die Attach Temperatures - Seal Parameters - Seal Temperature Profile - Sta-Bake Profile - Temp Cycle Chamber Temperature - ESD Protection - Plating Bath Controls - Mold Parameters 15-4 X X X X X X X X • JAN Self-Audit • Environmental - RoomlHood Particulates - Temperature/Humidity X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Harris Quality TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS (Continued) AREA Test MANUFACTURING CONTROLS FUNCTION • TemperatureJHumidity X • ESD Controls X • Temperature Test Callbrat/on X • Test System Calibration X X • Test Procedures • Control Unit Compliance X • Lot Acceptance Conformance X X • Group A Lot Acceptance X • JAN Self·Audit Bum·ln • Wafer Repeat Correlation X • Visual Requirements X X • Documentation X X • Process Performance X • Functionality Board Check X • Oven Temperature Controls X • Procedural Conformance X • JAN Self·Audit X • ESD Controls X X • Brand Permanency X X • Temperature/Humidity X X • Procedural Conformance aCI Inspection • JAN Self·Audit X • Group B Conformance X • Group C and 0 Conformance X Harris designers have an extensive set of very powerful Computer-Aided Design (CAD) tools to create and optimize product designs (see Table 2). TABLE 2. HARRIS I.C. DESIGN TOOLS PRODUCTS DESIGN STEP X X • JAN Self·Audit Brand AUDIT X • JAN Self-AudH Probe QA/OC MONITOR ANALOG DIGITAL Functional Simulation Cds Spice Cds Spice Verilog Parametric Simulation Cds Spice Monte Carlo Cds Spice Schematic Capture Cadence Cadence FunctlonalChec~ng Cadence Cadence Rules Checking Cadence Cadence Parasitic Extraction Cadence Cadence Special Testing Harris Semiconductor offers several standard screen flows to support a customer's need for additional testing and reliability assurance. These flows include environmental stress testing, bum-in, and electrical testing at temperatures other than +25"C. The flows shown on pages 9-6 and 9-7 indicate the Harris standard proceSSing flows for a Commercial Linear part in PDIP Package. In addition, Harris can supply products tested to customer specifICations both for electrical requirements and for nonstandard environmental stress screening. Consult your field sales representative for details. 15-5 , Harris Semiconductor Standard Processing Flows COMMERCIAL PROBEIDICE PREPARATION HIGH/ROOM TEMP PROBE TEST VISUAL INSPECTION MODIFIED MIL-STD-883 METHOD 2010 CONDITIONB WITH QC MONITOR ASSEMBLY (1) • * DIE ATTACH CONTROL OPERATION QUALITY MONITOR DIE MOUNT MOUNT CURE CONTROL YES QUALITY DIE ATTACH CONTROL (SPC) YES * WIRE BOND CONTROL POST BOND VISUAL WIRE BOND * LEAD FINISH CONTROL YES QUALITY WIRE BOND CONTROL (SPC) POST BOND INSPECTION (RTPC) * MOLD CONTROL YES QUALITY POST BOND INSPECTION MOLDING YES YES AS APPLICABLE YES MOLD CONTROL (SPC) YES BOTTOM CODE YES POST MOLD CURE YES TRIMlFORMIDERAIL YES SINGULATED SOLDER DIP YES 100% VISUAL INSPECTION YES LOAD SHIPPING TUBES YES * * QA LOT ACCEPTANCE YES QA DOCUMENTATION INSPECTION YES (1) Example for a PDIP Package Part 15-6 Harris Semiconductor Standard Processing Flow (Continued) COMMERCIAL' TEST (2) • * AC/DC SINGLE INSERTION TEST CAPABILITY; HIGHILOW TEMP OPERATION QUALITY MONITOR 100% ELECTRICAL TEST TOP BRAND BURN·IN QUALITY LOT ACCEPTANCE PDIPLEAD SCANNING YES YES PRE·BURN·IN ELECTRICAL TEST IF APPUCABLE BURN·IN IF APPLICABLE POST BURN·IN ELECTRICAL TESTS IF APPUCABLE APPLY BURN·IN PDA IF APPUCABLE * QC PRESHIP LOT ACCEPTANCE TEST YES 100% LEAD SCANNING YES PACKING YES * YES QC PRESHIP LOT ACCEPTANCE INSPECTION FINAL DATA REVIEW (2) Example for a Linear ParI in PDIP Package 15·7 YES Harris Quality TABLE 3. SUMMARIZING CONTROL APPLICATIONS FAB • Diffusion Junction Depth - Sheet ReSistivities - Oxide Thickness Implant Dose Calibration - UnHormlty • Thin Film - Film Thickness Uniformity Refractive Index - Aim Composition • Pre-Seal - Die Prep Visuals Yields - Ole Attach Heater Block Die Shear - Wire Pull - Ball Bond Shear - Saw Blade Wear Pre-Cap Visuals • Post-Seal Internal Package Moisture Tin Plate Thickness PIND Defect Rate Solder Thickness Leak Tests Module Rm. Solder Pot Temp. Seal Temperature Cycle - • Photo Resist - Critical Dimension Resist Thickness - Etch Rates - - • Measurement Equipment - Critical Dimension - Film Thickness - 4 Point Probe Ellipsometer - ASSEMBLY - - - • Measurement XRF - Radiation' Counter Thermocouples GM-Force Measurement - - - -- TEST System - HandlersiTest - Defect Pareto Charts - Lot % Defective - ESD Failures per Month - Monitor Failures - Lead Strengthening Quality - After Burn-In PDA OTHER • IQC Vendor Performance Material Criteria Quality Levels - • lac Measurement/Analysis XRF ADE 4 Point Probe Chemical Analysis Equipment • Environment Water Quality Clean Room Control Temperature Humidity - - - - - Controlling and Improving the Manufacturing Process - SPCIDOX Statistical process control (SPC) is the basis for quality control and improvement at Harris Semiconductor. Harris manufacturing people use control charts to determine the normal variabilities in processes, materials, and products. Crkical process variables and performance characteristics are measured and control limits are plotted on the control charts. Appropriate action is taken if the charts show that an operation is outside the process control limits or indicates a nonrandom pattern inside the limits. These same control charts are powerful tools for use in reducing variations in processing, materials, and products. Table 3 lists some typical manufacturing applications of control charts at Harris Semiconductor. SPC is important, but still considered only part of the solution. Processes which operate in statistical control are not always capable of meeting engineering requirements. The conventional way of dealing with this in the semiconductor industry has been to implement 100% screening or inspection steps to remove defects, but these techniques are insuffICient to meet today's demands for the highest reliability and perfect quality performance. Harris still uses screening and inspection to "grade" products and to satisfy specific customer requirements for burn-in, multiple temperature test insertions, environmental screening, and visual inspection as value-added testing options. However, inspection and screening are lim ked in their ability to reduce product defects to the levels expected by today's buyers. In addition, screening and inspection have an associated expense, which raises product cost. (See Table 4). TABLE 4. APPROACH AND IMPACT OF STATISTICAL QUALITY TECHNOLOGY STAGE I Producl Screening II Process Control APPROACH IMPACT • Stress and Test • Limited Quality • Defective Prediction • Costly • After-The-Fact • Statislical Process Control • Just-ln-TIme Manufacturing • Identifies variabiUty • Reduces Costs • Realllme III Process • Design of Experl• Minimizes Variability Optimization ments • Before-The-Fact • Process Simulation IV Product • Design for ProducOptimization ibillty • Product Simulation 15-8 • Insensitive to Veriability • Designed-In Quality • Optimal Results Harris Quality Harris engineers are, instead, using Design of Experiments (DOX), a scientifically disCiplined mechanism for evaluating and implementing improvements in product processes, materials, equipment, and facilities. These improvements are aimed at reducing the number of defects by studying the key variables controlling the process, and optimizing the procedures or design to yield the best result. This approach is a more time-consuming method of achieving quality perfection, but a better product results from the efforts, and the basic causes of product nonconformance can be eliminated. SPC, DOX, and design for manufacturability, coupled with our 100% test flows, combine in a product assurance program that delivers the quality and reliability performance demanded for today and for the future. Average Outgoing Quality (AOQ) Average OutgOing Quality is a yardstick for our success in quality manufacturing. The average outgoing electrical defective is determined by randomly sampling units from each lot and is measured in parts per million (PPM). The current procedures and sampling plans outlined in JEDEC STD 16, MIL-STD-883 and MIL-I-38535 are used by our quality inspectors. The focus on this quality parameter has resulted in a continuous improvement to less than 100 PPM, and the goal is to continue improvement toward 0 PPM. Training The basis of a successful transition from conventional quality programs to more effective, total involvement is training. Extensive training of personnel involved in product manufacturing began in 1984 at Harris, with a comprehensive devel- opment program in statistical methods. Using the resources of Harris statisticians, private consultants, and internally developed programs, training of engineers, supervisors, and operatorsitechnicians has been an ongoing activity in Harris Semiconductor. Over the past years, Harris has also deployed a comprehensive training program for hourly operators and supervisors in job requirements and functional skills. All hourly manufacturing employees participate (see Table 5). Incoming Materials Improving the quality and reducing the variability of critical incoming materials is essential to product quality enhancement, yield improvement, and cost control. With the use of statistical techniques, the influence of Silicon, chemicals, gases and other materials on manufacturing is highly measurable. Current measurements indicate that results are best achieved when materials feeding a statistically controlled manufacturing line have also been produced by statistically controlled vendor processes. To assure optimum quality of all incoming materials, Harris has Initiated an aggressive program, linking key suppliers with our manufacturing lines. This user-supplier network is the Harris Vendor Certification process by which strategic vendors, who have performance histories of the highest quality. participate with Hams in a tined network; the vendor's factory acts as if it were a beginning of the Hams production line. SPC seminars, development of open working relationships, understanding of Hams' manufacturing needs and vendor capab~ities, and continual improvement programs are all part of the certifICation process. The sole use of engineering Umits no longer is the only quantitative requirement of inooming materials. TABLE 5. SUMMARY OF TRAINING PROGRAMS COURSE TOPICS COVERED AUDIENCE SPC, Basic Manufacturing Operators, Non-Manufacturing Personnel Harris Philosophy of SPC, StatistiCal Definitions, Statistical Calculations, Problem Analysis Tools, Graphing Techniques, Control Charts SPC, Intermediate Manufacturing Supervisors, Technicians Harris Philosophy of SPC, Statistical Definitions, Statistical Calculations, Problem Analysis Tools, Graphing Techniques, Control Cherts, Distributions, Measurement Process Evaluation, Introduction to Capability SPC, Advanced Manufacturing Engineers, Manufacturing Managers Harris Philosophy of SPC, StatistiCal Definitions, StatistiCal Calculations, Problem AnalysIs Tools, Graphing Techniques, Control Charts, Distributions, Measurement Process Evaluation, Advanced Control Cherts, Variance Component Analysis, Capability Analysis Design of Experiments (DOX) Engineers, Managers Factorial and Fractional Designs, Blocking Designs, Nested Models, Analysis of Variance, Normal Probability Plots, Statistical Intervals, Variance Component Analysis, Multiple Comparison Procedures, Hypothesis Testing, Model AssumptionslDiagnostics Regression Engineers, Managers Simple Unear Regression, Multiple Regression, CoeflicientlntervaJ estimation, Diagnostic Tools, Variable Selection Techniques Response Surface Methods (RSM) Engineers, Managers Steepest Ascent Methods, Second Order Models, Cantral Composite Designs, Contour Plots, Box-8ehnkan Designs 15-9 Harris Quality Specified requirements include centered means, statistical control limits, and the requirement that vendors deliller their products from their own statistically evaluated; In-control manufacturing processes. In addition to the certification process, Harris has worked to promote improved quality In the performance of all our qualified vendors who must meet rigorous incoming Inspection criteria (see Table 6). TABLE 6. lNCOMING QUALITY CONTROL MATERIAL QUALITY CONFORMANCE MATERIAL Silicon INCOMING INSPECTIONS • • • • Resistivity Crystal Orientation Dimensions Edge Conditions Taper • • • • • Thickness Total Thickness Variation Backside Criteria Oxygen Carbon · ChemicalsiPhotoreslsts/ Geses • Equipment Capability Control Charts - Oxygen - Resistivity • Control Charts Related to - Enhanced Getterlng Total Thickness Variation Total Indicated Reading - Particulates • Certificated of Analysis for all Critical Parameters • Control Charts from On-Line Processing • Certificate of Conformance - • • • • Certificate of Analysis on all Critical Parameters Certificate of Conformance Control Charts from On-Line Processing Control Charts Assay - Contaminants Water Selected Parameters • Control Charts - Assay - Contaminants • Control Charts on Photospeed Thickness UV Absorbance Filterability - Water - Contaminants • Chemicals - Assay - Major Contaminants • Molding Compounds - Spiral Flow - Thermal Characteristics - • Gases - Impurttles • Photoreslsts Viscosity Film Thickness Solids Pinholes - Thin Film Materials Assembly Materials VENDOR DATA REQUIREMENTS - - • Assay • Selected Contaminants • Control Charts from On-Line Processing • Control Charts Assay - Contaminants - Dimensional Cl1aracterlstlcs • Certificate of Analysis for all Critical Parameters • Certificate 01 Conformance • • • • • • • • • • • Certificate of Analysis • Certificate of Conformance • Process Control Charts on Outgoing Product Chacks and In-Line Process Controls - Visual Inspection Pl1yslcal Dimension Cl1ecks Glass Composition Bondability Intermetalilc Layer Adhesion Ionic Contaminants ThermaiCharacterlstics Lead Coplanarity Plating Thickness Hermeticlty 15-10 Harris Quality Calibration Laboratory Another important resource in the product assurance system is a calibration lab in each Harris Semiconductor operation site. These labs are responsible for calibrating the electronic, electrical, electro/mechanical, and optical equipment used in both production and engineering areas. The accuracy of instruments used at Harris is traceable to a national standards. Each lab maintains a system which conforms to the current revision of MIL-STD-45662, "Calibration System Requirements:' Each instrument requiring calibration is assigned a calibration interval based upon stability, purpose, and degree of use. The equipment is labeled wnh an identification tag on which is specified both the date of the last calibration and of the next required calibration. The Calibration Lab reports on a regular basis to each user department. Equipment out of calibration is taken out of service until calibration is performed. The Quality organization performs periodic audns to assure proper control in the using areas. Statistical procedures are used where applicable in the calibration process. Manufacturing Science - CAM, JIT, TPM In addition to SPC and DOX as key tools to control the product and processes, Harris is deploying other management mechanisms in the factory. On first examination, these tools appear to be directed more at schedules and capacity. However, they have a significant impact on quality results. Computer Aided Manufacturing (CAM) CAM is a computer based inventory and productivity management tool which allows personnel to quickly identify production line problems and take corrective action. In addition, CAM improves scheduling and allows Harris to more quickly respond to changing customer requirements and aids in managing work in process (WIP) and inventories. Just In Time (JIT) The major focus of JIT is cycle time reduction and linear production. Significant improvements in these areas result in large benefits to the customer. JIT is a part of the Total Quality Management philosophy at Harris and includes Employee Involvement, Total Quality Control, and the total elimination of waste. Some key JIT methods used for improvement are sequence of events analysis for the elimination of non-value added activities, demand/pull to improve production flow, TQC check pOints and Employee Involvement Teams using root cause analysis for problem solving. JIT implementations at Harris Semiconductor have resulted in significant improvements in cycle time and linearity. The benefits from these improvements are better on time delivery, improved yield, and a more cost effective operation. JIT, SPC, and TPM are complementary methodologies and used in conjunction with each other create a very powerful force for manufacturing improvement. Total Productive Maintenance (TPM) TPM or Total Productive Maintenance is a specific methodology which utilizes a definite set of principles and tools focusing on the improvement of equipment utilization. It focuses on the total elimination of the six major losses which are equipment failures, setup and adjustment, idling and minor stoppages, reduced speed, process defects, and reduced yield. A key measure of progress within TPM is the overall equipment effectiveness which indicates what percentage of the time is a particular equipment producing good parts. The basic TPM principles focus on maximum equipment utilization, autonomous maintenance, cross functional team involvement, and zero defects. There are some key tools wnhin the TPM technical set which have proven to be very powerful to solve long standing problems. They are initial clean, P-M analysis, condition based maintenance, and quality maintenance. The use of CAM has resulted in significant improvements in many areas. Better wafer lot tracking has facilitated a number of process improvements by correlating yields to process variables. In several places CAM has greatly improved capacity utilization through better planning and scheduling. Queues have been reduced and cycle times have been shortened - in some cases by as much as a factor of 2. Utilization of TPM has shown significant increases in utilization on many tools across the Sector and is rapidly becoming widespread and recognized as a very valuable tool to improve manufacturing competitiveness. The most dramatic benefit has been the reduction of WIP inventory levels, in one area by 500%. This results in fewer lots in the area and a resulting quality improvement. In wafer fab, defect rates are lower because wafers spend less time in production areas awaiting processing. Lower inventory also improves morale and brings a more orderly flow to the area. CAM facilitates all of these advantages. The major benefits of TPM are capital avoidance, reduced costs, increased capability, and· increased quality. It is also very compatible with SPC techniques since SPC is a good stepping stone to TPM implementation and it is in turn a good stepping stone to JIT because a high overall equipment effectiveness guarantees the equipment to be available and operational at the right time as demanded by JIT. 15-11 Harris Reliability The reliability operations for Harris Semiconductor are consolidated into three locations; in Palm Bay, Florida, and Research Triangle Park, North Carolina, for integrated circuits products, and Mountaintop, Pennsylvania for Power Discrete Products. This consolidatiOn brought the reliability organizations together to form a team that possesses a broad cross section of expertise in: o Custom Military o Automotive ASICs o Harsh Environment Plastic Packaging o Advanced Methods for Design for Reliability (DFR) o Strength in Power Semiconductor o Chemical/Surface Analysis Capabilities The reliability focus is customer satisfaction (external and internal) and is accomplished through the development of standards, performance metrics and service systems. These major systems are summarized below: o A process and product development system which emphasizes getting new products to market over product design. Uses empowered cross functional development teams. o Standard test vehicles (96 in all) for process characterization of wearout failure mechanisms using conventional stresses (for modeling FITslMTTF) and wafer level reliability characterization during development. o Common qualification standards and philosophy for all sites and developments. o Matrix monitor standard - a reliability monitoring system for products in production to insure ongoing reliability and verification of continuous improvement. o Field return failure analysis system deployed world wide to track and expedite root cause analysis and irreversible corrective actions in a timely manner for our customers. The system is called by the team name PFAST, Product Failure Analysis Solution Team. Failure analysis sites are located in Brussels, Mountaintop, Palm Bay, Singapore, Kuala Lumpur, and Toyko. In order to optimize our response time to the customer all locations are networked for optimum communication, trend analysis, and performance tracking. Integrated circuits reliability home base is in Palm Bay, Florida. This new facility has consolidated the reliabil~y organization of the standard products divisions reliability group from Palm Bay, Florida; Somerville, New Jersey; Santa Clara, California, and the Military and Aerospace Division in Palm Bay, Florida. This facility contains o A 9,000 square foot reliability analYSis laboratory, o An 8,000 square foot reliability stress testing facility, o A 5,000 square foot analytical (chemistry/surface analysis) laboratory, . o A 3,000 square foot of engineering office space. The .facil~ies are well equipped and manned with highly trained and disciplined analysts. The reliability facil~ies are JAN certified and certified by a host of customers including major automotive and telecommunications companies. ProcesS/ProductlPackage Qualifications Qualification activ~ies at Harris begin w~ the in-depth qualification of new wafer processes. These process qualifications focus on the use of test vehicles to characterize wearout mechanisms for each process. These data are used to establish design ground rules for each process to eliminate wearout failure during the useful life Of the product. Products designed within the establishe!l ground rules are qualified individually prior to introduction. New package configurations are qualified individually prior to being available for new products. Harris qualification procedures are specified via controlled documentation. Product/Package Reliability Monitors Many of the accelerated stress-tests used during initial reliability qualification are also employed during the routine monitoring of standard production product. Harris' continuing reliability mon~oring program consists of three groups of stress tests, labeled Matrix I, II and III. As an example, Table 7 outlines the Matrix tests used to monitor plastic packaged CMOS Logic ICs in Harris' Malaysia assembly plant, where .each wafer fab technology is sampled weekly for both Matrix I and II. Matrix I consists of highly accelerated, short duration (48 hours or less) tests, which provide real-time feedback on product reliabil~y. Matrix II consists of the more traditional, longer term stress-tests, which are similar to those used for product qualification. Finally, Matrix III, performed monthly on each package style. monitors the mechanical reliability aspects of the package. Any failures occurring on the Matrix monitors are fully analyzed and the failure mechanisms identified, with corrective actions obtained from Manufacturing and Engineering. This information along with all of the test results are routinely transmitted to a central data base in Reliability Engineering, where failure rate trends are analyzed and tracked on an ongoing basis. These data are used to drive product improvements, so as to ensure that failure rates are continuously being reduced over time. TABLE 7. PLASTIC PACKAGED CMOS LOGIC ICS MALAYSIA RELIABILITY MONITORING TESTS. MATRIX I TEST Bias Life HAST 15-12 CONDITIONS DURATION SAMPLE +175°C 48 Hours 40 +145°C, 85% RH 20 Hours 40 Harris Reliability TABLE 7. PLASTIC PACKAGED CMOS LOGIC ICS MALAYSIA RELIABILITY MONITORING TESTS (Continued) MATRIX II The system and procedures define the processing of product being returned by the customer for analysis performed by Product Engineering, Reliability Failure Analysis and/or Quality Engineering. This system is designed for processing ·sample" returns, not entire lot returns or lot replacements. CONDITIONS DURATION SAMPLE Bias Life +125°C 1000 Hours 50 Dynamic Ufe +125OC 1000 Hours 50 +850 C, 85% RH 1000 Hours 50 Goals: quick, accurate response, uniform deliverable (consistent quality) from each site, traceability. 15 PSIG, +121°C, 100%RH 192 Hours 50 The PFAST system is summarized in the following steps: Storage Ufe +1SOOC 1000 Hours 50 Temp. Cycle -6500 to + 1500C 1000 Cycles 50 Thermal Shock ·6500 to + 1500C 1000 Cycles 50 TEST Biased Humidity Autoclave The philosophy is that each site analyzes its own product. This applies the local expertise to the solutions and helps toward the goal of quick turn time. 1) Customer calls the sales rep about the unit(s) to return. 2) Fill out PFAST Action Request - see the PFAST form in this section. This form is all that is required to process a Field Return of samples for failure analysis. This form contains essential information necessary to perform root cause analysis. (See Figure 2). 3) The units must be packaged in a manner that prevents physical damage and prevents ESO. Send the units and PFAST form to the appropriate PFAST controller. This location can be determined at the field sales office or rep using "Iook-up'"tables in the PFAST document. MATRIX III TEST CONDITIONS SAMPLE Solderability Mil·Sld 88312003 15 Lead Fatigue Mil-SId 88312004 15 Brand Adhesion Mil-SId 88312015 20 (UL-94 Vertical Burn) 5 Rammabllity 4) The PFAST controller will log the units and route them to ATE testing for data log. 5) Test results will be reviewed and compared to customer complaint and a decision will be made to route the failure to the appropriate analytical group. Field Return Product Analysis System The purpose of Ihis system is to enable Harris' Field Sales and Quality operations to properly route, track and respond to our customers' needs as they relate to product analysis. The Product Failure Analysis Solution Team (PFAST) consists of the group of people who must act together to provide timely, accurate and meaningful results to customers on units returned for analysis. This team includes the salesman or applications engineer who gets the parts from the customer, the PFAST controller who coordinates the response, the Product or Test Engineering people who obtain characterization and/or test data, the analysts who failure analyze the units, and the people who provide the ultimate corrective action. It is the coordinated effort of this team, through the system described in this document that will drive the Customer responsiveness and continuous improvement that will keep Harris on the forefront of the semiconductor business. 6) The customer will be contacted with the ATE test results and interim findings on the analysis. This may relieve a line down situation or provide a rapid disposition of material. The customer contact is valuable in analytical process to insure root cause is found. 7) A report will be written and sent directly to the customer with copies to sales, rep, responsible individuals with corrective actions and to the PFAST controller so that the records will capture the closure of the cycle. 8) Each report will contain a feedback form (stamped and preaddressed) so that the PFAST team can assess their performance based on the customers assessment of quality and cycle time. 9) The PFAST team objectives are to have a report in the customers hands in 28 days, or 14 days based on agreements. Interim results are given real-time. 15-13 Harris Reliability lIJ~~8E~l§ Request Customer Analysis II II PFAST ACTION REQUEST Date: ORIGINATOR CuSTOMER No. TyppjpART No. l.ocATION/PHONE DEVICE No. LocATION PURCHASE ORnER SAMPLES RETURNED No. QUANTITY RECEIVED THE COMPlBTENESS AND TIMELY RESPONSE OF TIlE EVAWATION IS DIRECTLY RELATED TO TIlE COMPLETENESS OF TIlE DATA PROVIDED. PLEAsE PROVIDE AlL PERTINENT DATA. ATTACH ADDITIONAL SHEETS IF NECESSAR.Y. DETAILS OF REJECI' TYPE OF PROBLEM (Wb.... ppropri.te ..rializ••• 111 ••d specify for ..ok) 1. D INcoMING INSPECTION [] 100% ScREEN [] SAMPLE INsPECTION No. TEsTED No. OF REIECTs -- -- ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS? [] YES [] NO [] BRIEP DESCRlI'TION OF EVALUATION AND RESULTS ATTACHED 2. [] IN PROCESS/MANUFACTURING FAILURE [] BOARD CHEcKOUT D SYSTEM CHEcKOUT [] FAILED ON 1URN-ON [] FAILED AFTER HOURS OPERATION WAS UNIT RETESTED UNDER INCOMING INSPECTION CONDITIONS? DYES D NO [] BRIEF DESCRII'TION OF HOW FAILURE WAS ISOLATED TO COMPONENT ATTACHED 3. D FIELD FAILURE FAILED AFTER HOURS OPERATION EsTIMATED FAILURE RATE _ _% PER 1000 HOURS END USER I..ocATiON AMBIENT TEMPERATURE Q MIN. C MAx. C RIlL. HUMIDITY % D END USER FAILURE CORRESPONDENCE ATTACHED -- TEsT CONDITIONS RELATING TO FAILURE [] 'fEsTER USED (MFGR/MODEL) [] TEsT ThMPERAlURE [] TEsT TIME: [] CoNTINUOUS TEsT [] ONE SHOT (f SEC) [] DESCRII'TION OF ANY OBSERVED CONDITION TO =__ WHICH FAILURE APPEARS SENSITIVE: 1. D DC FAILURES D D 2. D -- -- ACTION ADDRESS OF FAiUNG I..ocAnoN (IF APPUCABLE) -- ATTACHED: POWER SUPPLY AND DRIVER D LiST OF REQUESTED BY CUSTOMER SPECIFIC ACTION REQUESTED IMPACT OF FAILED UNITS ON CUSTOMER'S SITuATION: --- CUSTOMER CoNTACTS WITH SPECIFIC KNOWLEDGE OF REJECTS NAME PosITION PHoNE OPENS [] SHORTS D LEAKAGE D STRESS POWER DRAIN D INPUT LEvEL D OUTPUT LEvEL [] LIST OF FORCING CONDITIONS AND MEASURED RESULTS FOR EACH PIN IS ATTACHED [] POWER SUPPLY SEQUENCING ATTACHED ACFAlLURES LiST FAiUNG CHARACTERISTICS 3. D LEvELs (Include pictures of waveforms). [] UST OF OUTPUT LEVELS AND LOADING CONDITIONS [] INPUT AND OUTPUT TIMING DIAGRAMS D DESCRIl'TION OF PATTERNS USED (If not standard patterns, give very complete description including address sequence). PROM PROORAMMING FAILURES ADDRESS OF FAILURES PROORAMMER USED (MFG/MoDEl/REV. No.) 4. [] PHYslCAIlAssEMBLY RELATED FAILURES D SEE CoMMENTS BELOW Additional Comments: FIGURE 2. PFAST ACTION REQUEST 15·14 D SEE ATTACHED Harris Reliability INSTRUcnONS FOR COMPLETING PFAST AcnON REQUEST FORM Thc purpo&e of this form is to hclp us providc }'Ou with a more aCC\U'ate, complcte, and timcly RSpOnsc to failulU which may OCC\Ir. Acc1Inte and completc information is ......ntial to ensure that thc appropriatc concctive action can be implemented. Due to this need for accunte and complcte information, requests without a complcted PFAST Action Requcst form will be retumed. Source of Problem: This section requcsts the prod\lCl leading to the failure. Mark an 'X' in thc appropriate boxes up 10 and including the step which dctected the failu~. Also mark an 'X' in the appropriate box under ARE RESULTS REPRESENTATIVE OP PREVIOUS LOTS? 10 indicatc whether this is a rare failure or • repeated problem. now Example 1. No incoming electrical test was performed, tbe units were installed onto boards, the boards fllJ1Ctioned correctly for twO hours and then 1 unit failed. The customer rarely has • failure due to this Harris device. ~ 100 OIlt of tbe SOD unilS shipped were telled at inc:oming and all~. The unilS _re installed into boards and the boards~. The boards were installed into the system and the systcm failed immediatcly wilen tumed on. There were 3 system failures due to this put. The customcr frequently has failures 01 this Harris cIcvice. The 3 uni'" were not n:tClted at iDcomiDg. SOURCE OF PROBLEM SOURCE OF PROBLEM t&., die 1- ~ •• _ of e¥flfl, (Elllr . . . .nee 0',","_ II die .... ~ ill . . bu. pnwkkd) I. VISUAiJMa:HANlCAI. VISUAiJMECHANICAL C DESCRIBE C DESCRIBE • 2. INcoMING nsr C 100% TEsTED No. nsno NOT i'E1U'OIIMED C SAMrUi lllsTED No. Of REn;crs 2. INCOMING Tf.sT C 100% lllsTED No. TEsTED -- -- ARE. RfSut.TS REPRESan'AnVE OF PREVIOUS L01S? • C TIS -L- • -- OTIS • -- • NO ARE IU!SULTS REPRESENTATIVE Of PREVIOUS LOTS? NO -- NO .12- NO 4. flEW FAILURE FAlUiO AfTEIt _ _ HOURS OPERA11ON fsl1 ....1100 fAlLll1IE U110 _ _lIoPER END USER LocAl1ON ·C AYE. MiN. "C MAx. S. OTHER o FAlUio AfTEIt HOURS Of TSSTlNG WAS UNIT RE'I'FSTED AT lNOOMINO 1HSPEC11ON? ARE RESUL'r3 REPRESENTATIVE Of PREVIOUS LOTS? • TIS 3. IN PRocESSiMANUFACruIUNG FAIUIII£ • 80AJlD nsr • SYSTEMnsr How MANY UNITS fAlUiD? ~ FAILED AFTER HOURS OF lBTlNO WAS UNIT RE'JESTED AT INCOMING 1NS1'EC110N? OTIS L ARE IU!SULTS REPlESENTA11VE Of PREVIOUS LOTS? C TIS C NO 3. IN PROCESSiMANUFACIlIIIING FAlUIII£ • BoAJU) Tf.sT C SYSTEMnsr How MANY UNITS fAl1£D? L C NOT PERfOllMED SAMru; nsno No. Of REn;crs • 1£L TIS o NO 4. flEW FAILURE FAILED AfTEIt _ _ HOURS OPERATION fsl1 ....11OD FAILURE U110 _ _lIoPER END USE8 LocA11ON ·C AYE. MiN. MAx. "C OTHER ·C s. -- -- -- "C Action Requested by Customer: This section should be completed with the customer's expectations. This information is essential for an appropriate ruponsc. Reason for Electrical Reject: This section should be completed if tbe type of failure could he identifJCd. If this information is c:onlained in attached customer corRSpOndcnce there is no need to transpose onto the PFAST Action Request form. PFAST REQUIREMENTS Thc value of retuming failing prod\lCUl is in the corrective actions that an: aenerated. Failun: to meet the following requitements can cause an erroneous c:ondusion and correctM: action; then:fore, failun: to meet these requirements will lUult in the requCII heing retumed. Contact the local PPAST Coordinator if}'Ou have any questions. Units with conformal c:oating should include the c:oating manufacturer and model. This is requested since tbe c:oating must he n:mOIIcd in order to perform elcctric:al or bermeticity telling. 1) Units must be n:tumed with proper ESD protection (ESD-Afe shipping tubes witbin shielding boxfbag or inserted into c:ondllClive foam within shielding boxfbag). No tape, paper bags, or plastic bags sbould be used. This requirement ens\llU that the cIcvic:cs an: not demaaed during sbipment badt 10 Harris. 2) Units mllSt he intaC! (lid not removed and at least part of each packaae lead present). This requitement is in place since the parts must be intact in order to perform electrical test. Also, opening the packaae can rem<>oe evidence of tbe cause for failun: and lead to an incorrect conclusion. 3) Programmable parts (ROMs, PROMS, UVEPROMs, and EEPROMs) must include a master unit witb the same pattern. This requitement is to provide tbe pattern so all failing locations can be identified. A master unit is required if a failun: analysis is requested. FIGURE 2. PFAST ACTION REQUEST (Continued) 15-15 Harris Reliability Failure Analysis Laboratory The Failure Analysis Laboratory's capabilities encompass the isolation and Identification of all failure mOdeslfailure mechanisms, preparing comprehensive technical reports, and assigning appropriate corrective actions. Research vital to understanding the basic physics of the failure is also undertaken. Failure analysis is a method of enhancing product reliability and determining corrective action. It is the final and crucial step used to isolate potential reliability problems that may have occurred during 1'eliability stressing. Accurate analysis results are imperative to assess effective corrective actions. To ensure the integrity of the analysiS, correlation of the failure mechanism to the initial electrical failure is essential. A general failure analysis procedure has been established in accordance with the current revision of MIL-STD-883, Section 5003. The analysis procedure was designed on the premise that each step should provide information on the failure without destroying information to be obtained from subsequent steps. The exact steps for an analysis are determined as the situation dictates. (See Figures 3 and 4). Records are maintained by laboratory personnel and contain data, the failure analyst's notes, and the formal Product AnalysiS Report. complete analytical studies. The capabilities of each area are shown below. SPECTROSCOPIC METHODS: Colorimetry. Optical Emission, Ultraviolet Visible, Fourier Transform-Infrared, Flame Atomic Absorption, Furnace Organic Carbon Analyzer, Mass Spectrometer. CHROMATOGRAPHIC METHODS: Gas Chromatography, Ion Chromatography. THERMAL METHODS: Differential Scanning Colorimetry, Thermogravimetric Analysis, Thermomechanical Analysis. PHYSICAL METHODS: Profilometry, Microhardness, Rheometry. CHEMICAL METHODS: Volumetric, GravimetriC, Specific Ion Electrodes. ELECTRON MICROSCOPE: Transmission Electron Microscopy, Scanning Electron Microscope. X-RAY METHODS: Energy Dispersive X-ray Analysis (SEM), Wavelength Dispersive X-ray AnalysiS (SEM), X-ray Fluorescence Spectrometry, X-ray Diffraction Spectrometry. Analytical Services Laboratory SURFACE ANALYSIS METHODS: Scanning Auger Microprobe, Electron Spectroscopy/Chemical Analysis, Secondary Ion Mass Spectrometry, Ion Scattering Spectrometry. Ion Microprobe. Harris facilities, engineering, manufacturing, and product assurance are supported by the Analytical Services Laboratory. Organized into chemical or microbeam analysis methodology, staff and instrumentation from both labs cooperate in fully integrated approaches necessary to The department also maintains ongoing working arrangements with commercial, university, and equipment manufacturers' technical service laboratories, and can obtain any materials analysis in cases where instrumental capabilities are not available in our own facility. FIGURE 3. NON-DESTRUCTIVE FIGURE 4. DESTRUCTIVE 15-16 Harris Reliability where. Reliability Fundamentals and Calculation of Failure Rate A. = failure rate in FITs (Number fails in 109 device hours) p = # of distinct possible failure mechanisms Table 8 below defines some of the more important terminology used in describing the lifetime of integrated circuits. k xi Of prime importance is the concept of "failure rate" and the calculation thereof. i= 1. 2 .... P = Total device hours of test time (unaccelerated) for Life Test j. j = 1. 2. 3 •... k AFij = Acceleration factor for appropriate failure mechanism i = 1. 2 •... k TDH j Failure Rate Calculations Reliability data may be composed of several different failure mechanisms and the combining of potentially diverse failure rates into one comprehensive failure rate is desired. The failure rate calculation is complicated because the failure mechanisms are thermally activated at differing rates. Additionally. this data is usually obtained on a number of life tests performed at unique stress temperatures. The equation below accounts for these considerations along with a statistical factor to obtain the upper confidence level (UCL) for the resulting failure rate. 1: - J=1 .1: = # of life tests being combined = # of failures for a given failure mechanism 13 k [i-1 xI 1 TDH j AF ij • MX1Q9 13 " X. ~ I i=1 M= x2 (11.2r+2) 2 where. X2 chi square factor for 2r + 2 degrees of freedom r total number of failures (1: Xi) (I = risk associated with UCL; Le. (I = (100-UCL(%»/100 = = In the failure rate calculation. Acceleration Factors (AFij) are used to derate the failure rate from the thermally accelerated life test conditions to a failure rate indicative of actual use temperature. Although no standard exists. a temperature of +550 C has been popular. Harris Semiconductor Reliability Reports will derate to +550 C and will express failure rates at 60% UCL. Other derating temperatures and UCLs are available upon request. TABLE 8. FAILURE RATE PRIMER TERMS DEFINITIONS/DESCRIPTION Failure Rate A. Measure of failure per unit of time. The failure rate typically decreases slighHy over early life. and then becomes relatively constant over time. The on set of wearout will show an increasing failure rate. which should occur well beyond useful life. The useful life failure rate Is based on the exponential life distribution FIT (Failure In Time) Measure of failure rate in 109 device hours; e.g.• 1 FIT = 1 failure in 10S device hours. 100 FITS = 100 failure in 109 device hours. etc. Device Hours The summation of the number of units in operation multiplied by the time of operation. MTTF (Mean Time To Failure) Mean of the life distribution for the population of devices under operaHon or expected lifetime of an individual. MTTF = which is the time where 63.2% of the population has failed. Exampled: ForA. = 10 FITS (or 10 E-9/Hr.). MTTF = In.. = 100 million hours. Confidence Level (or limit) Probability level at which population failure rate estimates are derived from sample life test: 10 FITs at 95% UCL means that the population failure rate Is estimated to be no more than 10 FITs with 95% certainty. The upper limit of the confidence intervai is used. Acceleration Factor (AF) A constant derived from experimental data which relates the times to failure at two different stress,es. The AF allows extrapolation of failure rates from accelerated test conditions to use conditions. In... 15-17 Harris Reliability Acceleration Factors Activation Energy Acceleration factor is determined from the Arrhenius Equation. This equation is used to describe physiochemical reaction rates and has been found to be an appropriate model for expressing the thermal acceleration of semiconductor failure mechanisms. The Activation Energy (Ea) of a failure mechanism Is determined by performing at least two tests at different leveis of stress (temperalure and/or voltage). The stresses will provide the lime to failure (If) for the two (or more) populations Ihus allowing the simultaneous solution for the activation energy as follows: AF = EXP [ ~ E k In (_1___1_)] Tuse = C + Ea In (t12) = C + kT, By subtracting the two equations, and solving for the activation energy, the following equation is obtained: where, AF (tl1) Tstress Ea = Acceleration Factor = k [In(~,) - In(It:!)) (1fT! - lfT2) E,. = Thermal Activation Energy (See Table 9) where, k = Boltzmann's Constant (8.63 x 10-5 eVI"K) Ea = Thermal Activation Energy (See Table 9) Both Tuse and Tsl,ass (in degrees Kelvin) include the internal temperature rise of the device and therefore represent the junction temperature. k = Boltzmann's Constant (8.63 x 10-5 eVI"K) T 1, T2 = Life test temperatures in degrees Kelvin TABLE 9. FAILURE MECHANISM FAILURE MECHANISM ACTIVATION ENERGY SCREENING AND TESTING METHODOLOGY CONTROL METHODOLOGY OXide Defects 0.3-0.5eV High temperature operating life (HTOL) and voltage stress. Defect density test vehicles. Statistical Process Control of oxide parameters, defect density control, and voltage stress testing. Silicon Defects (Bulk) 0.3 -0.5eV HTOL & voltage stress screens. Vendor statistical Quality Control programs, and Statistical Process Control on thermal processes. Highly accelerated stress testing (HAST) Passivation dopant contrOl, hermetic seal control, Improved mold compounds, and product handling. Temperature cycling, temperature and mechanical shock, and environmental stressing. Vendor Statistical Quality Control programs, Statistlcal Process Control of assembly processes, proper handling methods. Test vehicle charac1erlzations at highly elevated temperatures. Design ground rules, wafer process statistical process steps, photoresist, metals and passivation CorrOSion 0.45eV Assembly Defects 0.5-0.7eV Electromlgration - AI Line - Contect O.BeV O.geV Mask Defects! Photoresist Defects 0.7eV Mask FAB comparator, print checks, defect density monitor in FAB, voltage stress test and HTOL. Clean room control, clean mask, pellicles, Statistical Process Control of photoresist/etch processes. Contamination 1.00V C-V streSs at oxide/Interconnect, wafer FAB device stress test and HTOL. Statistical Process Control of C-V data, oxide/interconnect cleans, high integrity glassivation and clean assembly processes. Charge Injection 1.3eV HTOL & oxide characterization. Design ground rules, wafer level Statistical Process Control and critical dimensions for oxides. 15-18 DATA ACQUISITIO_ 16 APPLICATION NOTE ABSTRACTS ANt mLE ABSTRACTS 001 Glossary of Data Acquisition Terms Specification definitions, terminology and most often used terms used in the field of data acquisition. 002 Principles of Data and Conversion Basic Data Acquisition system design, quantizing theory, sampling theory, data coding, amplifiers and filters, settling time, DAC types, ADC types, reference circuits, analog multiplexers, sample and holds, specifications, and selection criteria. 004 The IH5009 Analog Switch Series Circuit operation, logic compatibility, switching speed and crosstalk, and application circuits. 009 Pick Sample-Holds by Monolithic considerations, error analysis, droop discussion, capacitor characteristics, Accuracy and Speed and deglitching sample and holds, and cascaded sample and hold designs. Keep Hold Gapacitors in Mind 012 Switching Signals with Semiconductors Analog switches are fast, low cost, and work well with the high Impednace of most signal circuits. Often they can replace reed relays. 016 Selecting AID Converters Important selection parameters, the Integrating converter, the SAR type converter, multiplexed data systems, and a definition of terms. 017 The Integrating AID Converter The dual slope conversion technique, analyzing errors, capacitor induced errors and a noise discussion. 018 Do's and Don'ts of Applying AID Converters System power routing errors, PCB layout rules, component selection, thermal effects, and maximizing the FSR range of the converter. 020 A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing High speed system block diagram, layout considerations, multiplexer considerations differential amplifiers, sample and hold amplifier, SAR type ADCs, DAC design, and microprocessor interfacing 023 Low Cost Panel Meter Designs Cost advantages of display converters, Evaluation kit usage, display types, capacitors recommended, and proper power supply range. 028 Building an Auto-Ranging Basic circuit configuration and operation, decimal point drive, interface to parallel data DMM with the ICL7103A1 systems, auto-ranging designs, issues and solutions for proper operation. ICL8052A AID Converter Pair See page i for Information on Ordering Lkereture 16-1 Application Note Abstracts (Continued) ANi 030 TITLE ICL71 04 A Binary Output AID Converter for Microprocessors ABSTRACTS Interfacing to a digital system In non-hai'ld~aking mode, a handshaking mode interface to various processOrs, perfOrmance enhancement techniques, and an auto-zero loop discussion. 032 Understanding the AutoTheory of operation for the four integration phases, CMRR and the common mode voltage effects, the auto-zero loop residual, and In depth error analysis. Zero and Common Mode Performance of the ICL71 06/ 7107n1oe Family 042 Interpretation of Data Converter Accuracy Specifications A Discussion of data converter transfer functions, quantization noise and dynamic range, non-ideal data converter operation, nonlinearity, temperature induced errors, error budgets, layout and grounding rules. 043 Video Analog to Digital Conversion Comparator based flash converters, quantization noise, the decoder, a 2 stage flash converter, and hybrid considerations. 046 Building a Battery Operated Auto Ranging DVM with the ICL71 06 Auto-ranging circuitry design, the input range/reSistor divider, an auto-range clock circuit design, power supply requirements, measuring resistance and transconductance, and using the ICL7126 and ICL7107. 047 Games People Play with Harris AID Converters Various real world applications for AID converters, LCD annunciator drivers, decimal point drivers, a low battery detect application, blanking the display on low battery detect, controlling LED brightness, instant continuity detector, high voltage display driver, a gas discharge plasma display, DVM circuit, a tachometer design, measuring the gain of a transistor, running off a 1.5V supply, a simple capacitor meter, and a weighing system 048 Know Your Converter Codes Analyzing digital codes, ADC and DAC operating basics, Bipolar coding techniques, and coding limitations. 049 Applying the 7109 AID Converter A description of the ICL7109s, differential Input section, differential reference, digital section and how to measure bridges, and offsets. Interface examples to parallel processors, serial interfaces and how to replace Voltage to frequency converters. 052 Tips for Using Single Chip 31/ 2 Digit AID Converters Some of the more commonly asked questions concerning the 31/ 2 digital display converters ranging from power supply Inputs, display types aod drive, to timing, ratiometrlc operation, and component selection. A troubleshooting guide is provided. 054 Display Driver Family Combines Convenience of Use with Microprocessor Interfaceability Advantages of IC display drivers, non-multiplexed display operation, functional block diagrams, multiplexed display operation, and binary to bar graph display applications circuits. 059 Digital Panel Meter Experiments for the Hobbyist Discusses the fundamentals of designing a panel meter for measuring, DC Voltages, AC Voltages, resistance measurements, current measurements, temperature measurement, and designing multi-range DVMs. 517 Applications of Monolithic Sample and Hold Amplifiers General Sample and Hold infOrmation and fOurteen specific applications, including filtered Sample and Hold DAC de-glitcher Integrate-Hold-Reset, gated op amp, etc. See page i lor inlormation on Ordering Lnerature 16'-2 Application Note Abstracts (Continued) AN' TITLE ABSTRACTS 520 CMOS Analog Multiplexers and Switches; Application Considerations Switch selection criteria, datasheet definitions, care and feeding of multiplexers and switches, digital Interface, practical multiplexer applications alternative to CMOS switches and multiplexers. 521 Getting the Most Out of CMOS Devices for Analog Switching Jobs CMOS vs bipolar device performances, over wltage and channel interaction conditions, JI technology and latch-up, floating body JI technology, fool proof CMOS analog multiplexer, other 01 benefits. 522 Digital to Analog Converter Terminology Explains DAC terminology, Resolution Gain Error, Offset Error, Linearity Error, Differential Linearity Error, Drift, Settling Time, etc. 524 Digital to Analog Converter High Speed ADC Applications Use of High Speed DAC's in tracking, serw, and successive approximation Analog to Digital Converters. Design ideas for Data Acquisition Systems. 531 Analog Switch Applications in AID Data Conversion Systems System configurations, analog switch types, CMOS switch selection guidelines, alternative uses of CMOS switches. 532 Common Questions Concerning CMOS Analog Switches Power supply considerations, input overwltage protection, single supply operation, various questions about Harris 01 switches. 534 Additional Information on the HI-300 Series Switch "ON" resistance, leakage currents, switching speeds, power supply requirements, internal switch operation and schematics, single supply operation, charge Injection, power supplies conditions and protective circuitry. 535 Design Considerations for a Data Acquisition System (DAS) A collection of guidelines for the design of a Data Acquisition System. Includes signal conditioning, transducers, Single-ended vs differential signal paths, low level signals, filters Programmable Gain Amplifiers, sampling rate, and computer interfaCing. 538 Monolithic SamplelHold Combines Speed and Precision Description and electrical specifications for the HA-5320 SamplelHold Amplifiers, explanation of error sources, and HA-5320 applications. 539 A Monolithic 16-6it D/A Converter Detailed description of a 16 bit DAC deSign and layout. Second order errors sources that contribute to linearity errors are discussed as well as architectural design, ground cancelation effects, settling time measurement techniques, suggested amplifier configurations for wltage output, and data-bus interfacing. 543 New High Speed Switch Offers Sub 50ns Switching Times Application enhancement using the HI201 HS, high speed multiplexers, high speed sample and hold, analog switch and op amp circuitry, integrator with start/reset, low pass filter with select break frequency, amplifier with programmable gain, future applications. 557 Recommended Test Procedures for Analog Switches Description of analog switch test methods employed at Harris Semiconductor. 559 HI-222 VideolHF Switch Optimizes Key Parameters Description of the key specifICations of the HI222 such as, power supply range vs RoN, TON, differential gain and phase errors, switching transients and charge injection, continuous and peak current capability, off isolation, crosstalk and PC board layout. See page i lor inlormatlon on Ordering Literature 16-3 Application Note Abstracts AN. MLE (Continued) ABSTRACTS 8759 Low Cost Data Acquisition System Features SPI AID Converter Discussions of a typical serial interface system, detailed description of the 68HC68 architecture, multiple zone heating system design, digital storage scope deSign, and microcode for a low cost DAS. 9213 Advantages and Application of Display Integrating AID Converters Theory of operation of a dual slope integrating type AID converter used for bridge measurement, low level sensors and several application circuits including, a capacitance meter, and digital thermometer. Using Harris High Speed PCB layout, grounding and power considerations for high speed converter board deSign, suggested voltage reference circuits, analog input buffers, bandwidth considerations, accuracy adjustments, logic family compatibility and interface examples, antialiasing filter theory, multiplexed inputs and input clamping for video signals. 9214 AID Converters 9215 Using the HI5700 Evaluation Board Theory of operations discussion for the H15700, a description and use of the evaluation board, typical performance curve data on the H15700, board layout and schematics. 9216 Using the HI5701 Evaluation Board Theory of operations discussion for the HI5701, a description and use of the evaluation board, typical performance curve data on the HI5701, board layout and schematics. 9309 Using the HI58OO1HI5801 Evaluation Board H15800 and Hl58010peration and architecture, an evaluation kit description, operating modes, layout and schematics. 9313 Circuit Considerations in Imaging Applications Discussions of Video formats such as RS170, circuit design conSiderations, system deSign, test results and time division multiplexed systems. 9316 Power Supply Considerations for the HI-222 High Frequency Video Switch A guide to proper power supply sequencing for the HI-222 Video Switch. 9328 Using the HI1166 Evaluation Board A description of how to use the H11166, 250MHz, 8-bit AID evaluation board. 9329 Using the HI117611171 Evaluation Board A description of how to use the H1117611171 Video AID and D/A evaluation board. 9330 Using the HI1396 Evaluation Board A description of how to use the HI1396, 125MHz, 8-bit AID evaluation board. 9331 Using the HI1175 Evaluation Board A description of how to use the HI1175 Video AID evaluation board. 9332 Using the HI1276 Evaluation Board A description of how to use the HI1276, 500MHz, 8-bit AID evaluation board. 9333 Using the HI1386 Adapter Board A description of how to use the H11386 75MHz 8-bit AID adaptor board. To be used with HI1396 evaluation board. 9337 Reduce CMOS Multiplexer Troubles through Proper Device Selection How to deal with output leakage, Overvoltage fault .protection techniques, and new architectural designs to provide better fault protection. See page i lor Ihlarmatlon on Ordering Literatur. 16-4 DATA ACQUISITIO_ 17 PACKAGING INFORMATION DATA ACQUISmON PACKAGE SELECTION GUIDE. . • . . . . . • . . . • . . . . • . . . . . • • . . . . . . . . . • . • . • . . . . . . . . . 17-2 DUAL-IN-LiNE PLASTIC PACKAGES................................................... .......•. 17-7 SMALL OUTLINE (SOIC) PLASTIC PACKAGES. . . . . . . . . . . • . . . • . • . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . 17-13 SHRINK SMALL OUTLINE (SSOP) PLASTIC PACKAGES. . . • . . . • . . • • . . • . . . . . . . . • . . • • . • . . . • . . . • . . . . . 17-18 PLASTIC LEADED CHIP CARRIER (PLCC) PACKAGES •..........••...........•..•........•••..... 17-19 METRIC PLASTIC QUAD FLATPACK PACKAGES. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 DUAL-IN-LiNE FRIT-SEAL CERAMIC PACKAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 METAL SEAL DUAL·IN-LiNE CERAMIC PACKAGES ................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 METAL SEAL LEADLESS CERAMIC CHIP CARRIER PACKAGES. . . • . . . . . . . . . . . . • . . . . . . . . . • . . . . . • . . . 17-33 SINGLE·IN·LlNE PLASTIC PACKAGES (SIP). . . . . . . . . . . . . . . . . . • . . . • • . . . . • . . . . . . . . • . . . . • . . . . • . • . . . • 17-40 METAL CAN PACKAGES. . . . . . . • . . . . . • . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . • . • 17-41 17-1 Data Acquisition Package Selection Guide Using the Selection Guide: The first character of each entry indicates the package type, while the number preceding the decimal point details the package lead count. Except for MQFP, LCC, SIP, and Can packages, the decimal point and succeeding numbers specify the reference package width in inches (e:g.. 15 150 mil width). The entire entry indicates the package table containing the appropriate package dimensions (e.g. 8 lead PDIP dimension are detailed in Table E8.3). The index on page 17-1 Usts page numbers for PDIP,SOIC, PLCC, MQFP, CDIP, Sidebraze, LCC, SIP and Can tables. = PART NUMBER PDIP SOICI SSOP MQFP PLc:C CERDIP SIDEBRAZE LCC AD590 AD7520 SIP CAN T3.A F16.3 E16.3 AD7521 E1S.3 AD7523 E16.3 AD7530 E16.3 AD7531 E1S.3 , AD7533 E16.3 AD7541 E1S.3 AD7545 E20.3 ADCOS02 E20.3 ADCOS03 E20.3 ADCOS04 E20.3 CA3l6l E16.3 CA3l62 E16.3 CA3l62A E16.3 CA3l68 E20.3 CA3l6SE E20.3 CA3304 E16.3 M16.3 F16.3 CA3306 E1S.3 M20.3 F1S.3 CA331 0 E24.3 M24.3 F24.3 CA33l0A E24.3 M24.3 F24.3 CA331SC E24.6 M24.3 F24.6 CA333S E16.3 M16.3 F16.3 CA333SA E16.3 M16.3 F16.3 CA555 ES.3 M8.l5 DG200 E14.3 DG201 E16.3 DG201A E16.3 F20.3 M20.3 F20.3 F20.3 J20.B TS.C F14.3 Tl0.S F16.3 M16.3 F16.3 DG202 E16.3 DG2ll E16.3 M16.l5 F16.3 DG2l2 E16.3 M16.l5 DG300A E14.3 F14.3 T10.S DG301A E14.3 F14.3 T10.S DG302A E14.3 F14.3 DG303A E14.3 M16.3 F14.3 EXAMPLE: M 16 .15 TL PACKAGEJ TYPE LEAD COUNT 17-2 BODY WIDTH Data Acquisition Package Selection Guide (Continued) PART NUMBER PDIP SOICI SSOP DG30BA E16.3 M16.15 F16.3 DG309 E16.3 M16.15 F16.3 DG401 E16.3 M16.15 F16.3 DG403 E16.3 M16.15 F16.3 DG405 E16.3 M16.15 F16.3 DG406 E16.3 M16.15 MQFP PLCC CERDIP DG407 E16.3 M16.15 DG40B E16.3 M16.15 F16.3 DG409 E16.3 M16.15 F16.3 DG411 E16.3 M16.15 F16.3 DG412 E16.3 M16.15 F16.3 DG413 E16.3 M16.15 F16.3 DG441 E16.3 M16.15 F16.3 F16.3 DG442 E16.3 M16.15 DG444 E16.3 M16.15 M16.15 DG445 E16.3 DG506A E2B.6 M2B.3 F2B.6 DG507A E2B.6 M2B.3 F2B.6 DG50BA E16.3 M16.3 F16.3 DG509A E16.3 M16.3 F16.3 DG526 E2B.6 M2B.3 F2B.6 DG527 E2B.6 M2B.3 F2B.6 DG52B E1B.3 M1B.3 F1B.3 F1B.3 DG529 E1B.3 M1B.3 HA7210 EB.3 MB.15 HI-0200 E14.3 HI-0201 E16.3 HI-0201-HS HI-0300 SIDEBRAZE LCC F14.3 SIP CAN T10.B M16.15 N20.35 F16.3 E16.3 M16.3 N20.35 F16.3 E14.3 M14.15 F14.3 T10.B HI-0301 E14.3 M14.15 F14.3 T10.B HI-0302 E14.3 M14.15 F14.3 HI-0303 E14.3 M14.15 F14.3 HI-0304 E14.3 M14.15 F14.3 T10.B HI-0305 E14.3 M14.15 F14.3 T10.B HI-0306 E14.3 M14.15 F14.3 HI-0307 E14.3 M14.15 F14.3 HI-03B1 E14.3 M14.15 F14.3 HI-03B4 E16.3 M16.3 F16.3 HI-03B7 E14.3 M14.15 F14.3 HI-0390 E16.3 M16.3 F16.3 HI-0506 E2B.6 M2B.3 N2B.45 EXAMPLE: F2B.6 M 16 .15 TL PACKAGEJ TYPE LEAD COUNT 17-3 BODY WIDTH J20.A T10.B T10.B J2B.A Data Acquisition Package Selection Guide (Continued) PART NUMBER PDIP HI-OS06A E2B.6 HI-OS07 E2B.6 HI-OS07A E2B.6 SOICI SSOP MQFP PLCC CERDIP SIDEBRAZE LCC F2B.6 M2B.3 N2B.4S F2B.6 J2B.A F2B.6 HI-OSOB E16.3 HI-OSOBA E16.3 HI-OS09 E16.3 HI-OS09A E16.3 HI-OS16 E2B.6 M2B.3 N2B.4S F2B.6 J2B.A HI-OS1B E1B.3 M1B.3 N20.3S F1B.3 J20.A J20.A M16.1S N20.3S F16.3 J20.A F16.3 M16.1S N20.3S F16.3 J20.A F16.3 HI-OS24 E1B.3 N20.3S F1B.3 HI-OS39 E16.3 N20.3S F16.3 HI-0546 E28.6 M28.3 N28.45 F28.6 HI-OS47 E28.6 M28.3 N28.4S F2B.6 J2B.A HI-OS48 E16.3 M16.15 N20.3S F16.3 J20.A HI-OS49 E16.3 M16.1S N20.35 F16.3 J28.A J20.A D24.6 HI-OS6SA HI-OS74A E28.6 D2B.6 J44.A HI-0674A E28.6 D2B.6 J44.A HI-0774 E28.6 D28.6 J44.A HI1166 J68.A M24.2-S HI1171 HI117S E24.4-S M24.2-S HI1176 Q32.7x7-S H11179 Q32.7x7-S HI1276 J68.B HI1386 E28.6A-S HI1396 E42.6A-S J44.B D42.6 J68.A Q64.14x20-S HI30S0 HIS721 E28.6 HI-1818A E16.3 M28.3 N20.3S HI-1828A E16.3 N20.35 HI-S040 E16.3 F16.3 HI-S041 E16.3 F16.3 HI-S042 E16.3 HI-S043 E16.3 HI-5044 E16.3 HI-S04S E16.3 HI-S046 E16.3 F16.3 HI-S046A E16.3 F16.3 HI-S047 E16.3 F16.3 HI-S047A E16.3 F16.3 F16.3 F16.3 J20.A F16.3 M16.1S F16.3 F16.3 M16.1S F16.3 EXAMPLE: M 16 .15 TL PACKAGEJ TYPE LEAD COUNT 17-4 BODY WIDTH J20.A SIP CAN Data Acquisition Package Selection Guide (Continued) PART NUMBER PDIP SOICI SSOP HI-S04B E16.3 HI-S049 E16.3 HI-SOSO E16.3 HI-SOS1 E16.3 M16.1S HI-S700 E2B.6 M2B.3 HI-5701 E1B.3 M1B.3 PLCC MQFP CERDIP M16.1S F16.3 F16.3 M28.3 HI5703 M28.3 N20.35 HI5710 F16.3 J20.A Q48.7x7-S HI5800 D40.6 HIS810 E24.3 M24.3 F24.3 HI5B12 E24.3 M24.3 F24.3 HIS813 E24.3 M24.3 HI7131 E40.6 Q44.10x10 HI7133 E40.6 Q44.10x10 HI7159A E2B.6 HI7190 E20.3 M20.3 HI20201 E28.6A-S M28.3A-S HI20203 E2B.6A-S M28.3A-S HI-DACBOV E24.6 HI-DAC8SV E24.6 HIN230 M20.3 HIN231 M16.3 E16.3 HIN234 F24.3 F20.3 M16.3 F16.3 M16.3 HIN236 E24.3 M24.3 HIN237 E24.3 M24.3 HIN238 E24.3 M24.3 M24.3 HIN239 HIN240 Q44.10x10 HIN241 M2B.31 M28.209 ICL232 E16.3 ICL7106 E40.6 Q44.10xl0 ICL7107 E40.6 Q44.10xl0 ICL7109 E40.6 ICL7116 E40.6 ICL7117 E40.6 ICL7126 E40.6 ICL71C03 E28.6 ICL7129 E40.6 LCC F16.3 HI5702 HIN232 SIDEBRAZE M16.3 F16.3 F40.6 Q44.10xl0 Q44.10x10 EXAMPLE: M 16 .15 TL PACKAGEJ TYPE LEAD COUNT 17-5 BoDy WIDTH D40.6 SIP CAN Data Acquisition Package Selection Guide (Continued) PART NUMBER SOICI PDIP SSOP PLCC MQFP ICL7135 E2B.6 ICL7136 E40.6 Q44.10x10 ICL7137 E40.6 Q44.10x10 ICL7139 E40.6 ICL7149 E40.6 ICLB052 E14.3 CERDIP SIDE· BRAZE F14.3 D14.3 F14.3 D14.3 LCC SIP CAN Z3.05A T2.A Q44.10x10 ICLB06B ICLB069 MB.15 ICM7170 E24.6 M24.3 ICM7211 E40.6 ICM7212 E40.6 ICM7213 E14.3 ICM7216A E2B.6 F2B.6 ICM7216B E2B.6 F2B.6 ICM7216D E2B.6 F2B.6 ICM7217 E2B.6 F28.6 F24.6 Q44.10x10 ICM7218 ICM7224 E40.6 ICM7226A E40.6 ICM7226B ICM7228 F40.6 E28.6 M28.3 F28.6 ICM7231 E40.6 F40.6 ICM7232 E40.6 F40.6 ICM7242 EB.3 ICM7243 E40.6 ICM7249 E4B.6 ICM7555 EB.3 ICM7556 E14.3 IH5043 E16.3 MB.15 F40.6 MB.15 TB.C F14.3 M16.3 F16.3 IH5052 F16.3 IH5053 F16.3 IH5140 E16.3 F16.3 IH5141 E16.3 F16.3 IH5142 E16.3 F16.3 IH5143 E16.3 F16.3 IH5144 E16.3 F16.3 IH5145 E16.3 F16.3 IH5151 E16.3 F16.3 IH5341 E14.3 IH5352 E16.3 T10.B M20.3 F16.3 EXAMPLE: M 16 .15 TL PACKAGEJ TYPE LEAD COUNT 17·6 BODY WIDTH T10.B Package Outlines Dual-In-Line Plastic Packages E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LiNE PLASTIC PACKAGE INCHES SYMBOL MAX MIN A NOTES: MILLIMETERS MIN 0.210 MAX NOTES 5.33 4 4 Al 0.015 A2 0.115 0.195 B 0.014 0.022 Bl 0.045 0.070 C 0.008 0.014 0 0.355 Q.400 01 0.005 E 0.300 0.325 El 0.240 0.280 6.10 7.11 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions. the inch dimensions control. e O.l00BSC 2.54BSC eA 0.3OOBSC 7.62BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1962. eB I 3. Symbols are defined in the 'MO Series Symbol Llsr in Section 2.2 of Publication No. 95. L 0.115 N 0.430 0.150 2.93 6 10.92 7 3.81 4 8 8 5 9 4. Dimensions A, Aland L are measured with the package seated In JEDEC seating plane gauge GS-3. Rev. 0 12193 5. D. D1. and El dimensions do not Include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LiNE PLASTIC PACKAGE 6. E and ~ are measured with the leads constrained to be perpendicular to datum ~. 7. eB and ec are measured at the lead tips with the leads unconstrained. ec must be zero or greater. INCHES SYMBOL MAX MIN A 8. Bl maximum dimensions do not Include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N Is the maximum number of terminal positions. 10. Corner leads (1. N. NI2 and NI2 + 1) for E8.3. E16.3. E18.3. E28.3. E42.6 will have a Bl dimension of 0.030 • 0.045 inch (0.76· 1.14mm). MILLIMETERS MIN 0.210 MAX NOTES 5.33 4 4 0.39 Al 0.015 A2 0.115 0.195 2.93 4.95 0.558 B 0.014 0.022 0.356 Bl 0.045 0.070 1.15 1.77 C 0.008 0.014 0.204 0.355 0.775 D 0.735 Dl 0.005 E 0.300 0.325 El 0.240 0.280 19.68 5 5 7.62 8.25 6 6.10 7.11 5 18.66 0.13 e O.l00BSC 2.54BSC eA 0.3OOBSC 7.62 BSC 0.430 eB L N 0.115 0.150 14 8 10.92 2.93 3.81 14 6 7 4 9 Rev. 0 12193 17-7 Package Outlines Dual-In-Line Plastic Packages (Continued) E16.3 (JEDEC MS-001-BB ISSUE oj 16 LEAD DUAL-IN-UNE PLASTIC PACKAGE =--CTIt ~~ INCHES SYMBOL IrE=;1 UE~m ~_ ~~~~ -c- • m MAX A2 A ., f$i 0.010 (0.25)@I C I A IB@ I 88 NOTES: 1. Controlling Dimensions: INCH. In case of connict between English and Melrlc dimensions, the Inch dimensions control. 2. Dimensioning and toIerancing per ANSI Y14.5M-1982. 4 4 A2 '0.115 0.195 2.93 4.95 8 0.014 0.022 0.356 0.558 81 0.045 0.070 1.15 1.77 C 0.008 0.014 0.204 0.355 0.775 18.66 8,10 0 0.735 01 0.005 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 19.68 5 e 0.1008SC 2.548SC 0.3008SC 7.62BSC 0.430 0.115 5 0.13 eA L [::£:]. NOTES 0.39 0.015 N 4. Dimensions A, A1 and L sre measured with the package seated in JEDEC seating plane gauge GS-3. 5. 0, 01, and E1 dimensions do not Include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and [i] sre measured with the leads constralned to be perpendiculsr to datum MAX 5.33 A1 es 3. Symbols sre defined In the "MO Series Symbol usr In Section 2.2 of Publication No. 95. MILUMETERS MIN 0.210 A -I D PLANE,- MIN I 0.150 6 10.92 3;81 2.93 16 7 4 16 9 Rev. 0 12193 E18.3 (JEDEC M8-001-BC ISSUE D) 18 LEAD DUAL-IN-UNE PLASnC PACKAGE INCHES SYMBOL 7. es andec are measured at the lead tips with the leads unconstralned. ec must be zero or greater. 8. 81 maximum dimensions do not include dambsr protrusions. Oambsr protrusions shall not exceed 0.010 inch (0.25mm). 9. N Is the maximum number of terminal positions. MIN MAX A 10. Corner leads (1, N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a 81 dimension of 0.030 - 0.045 inch (0.76-1.14mm). MILUMETERS MIN 0.210 MAX ,NOTES 5.33 4 A1 0.D15 0.39 A2 0.115 0.195 2.93 4.95 4 0.558 8 0.014 0.022 0.356 81 0.045 0.070 1.15 1.77 C 0.008 0.014 0.204 0.355 0.880 8,10 0 0.845 01 0.005 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 21.47 22.35 0.13 5 e 0.100BSC 2.548SC eA 0.3008SC 7.628SC es I I L N 0.115 18 0.430 0.150 5 2.93 18 6 10.92 7 3.81 4 9 Rev. 0 12193 17-8 Package Outlines Dual-In-Line Plastic Packages (Continued) E20.3 (JEDEC M8-001·AD ISSUE D) 20 LEAD DUAL-IN·L1NE PLASTIC PACKAGE INCHES SYMBOL MIN MAX 0210 A NOTES: MILLIMETERS MIN A1 0.015 A2 0.115 MAX NOTES 5.33 4 0.39 4 0.195 2.93 4.95 8 0.014 0.022 0.356 0.558 B1 0.045 0.070 1.55 1.n C 0.008 0.014 0.204 0.355 1.060 24.89 26.9 8 5 0 0.980 01 0.005 E 0.300 0.325 7.62 825 6 E1 0240 0280 6.10 7.11 5 0.13 5 e 0.100 BSC 2.5485C eA 0.3OO8SC 7.628SC 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M·1982. ea 3. Symbols are defined in the "MO Series Symbol list" in Section 22 of Publication No. 95. N L 0.430 0.150 0.115 2.93 7 3.81 4 20 20 6 10.92 9 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge G8-3. Rev. 0 12193 5. 0, 01, and E1 dimensions do not include mold flash or protru· sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and [!J are measured with the leads constrained to be per· pendlcular to datum E2:]. E24.3 (JEDEC M8-001·AF ISSUE D) 24 LEAD NARROW BODY DUAl-IN·LINE PLASTIC PACKAGE INCHES SYMBOL MIN MAX A 7. ea and Be are measured at the lead tips with the leads unconstrained. Be·must be zero or greater. 8. 81 maximum dimensions do not include dambar protrusions. Damber protrusions shall not exceed 0.010 inch (025mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1,N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a 81 dimension of 0.030 - 0.045 Inch (0.76·1.14mm). MILLIMETERS MIN 0.210 Al 0.015 A2 0.115 MAX NOTES 5.33 4 0.39 4 0.195 2.93 4.95 0.558 B 0.014 0.022 0.356 81 0.045 0.070 1.15 1.n C 0.008 0.014 0.204 0.355 1280 0 1.230 01 0.005 E 0.300 0.325 E1 0.240 0280 31.24 32.51 5 7.62 825 6 6.10 7.11 5 0.13 5 e 0.100 BSC 2.548SC eA 0.3OO8SC 7.628SC ea L N 0.430 0.115 I 24 0.150 8 10.92 2.93 3.81 24 6 7 4 9 Rev. 0 12193 "z zO a~ ~:E O~ ~~ 17·9 Package Outlines Dual-In-Line Plastic Packages (Continued) E24.6 (JEDEC MS-Oll·AA ISSUE B) 24 LEAD DUAL.JN-LiNE PLASTIC PACKAGE INCHES SYMBOL MIN MAX 0.250 A NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions. the Inch dimensions control. 2. Dimensioning and toleranclng per ANSI YI4.5M-1982. 3. Symbols are defined In the "MO Series Symbol List" In Section 2.2 of pubrlCatlon No. 95. O.ot5 A2 0.125 0.195 NOTES 4 4 3.18 4.95 0.558 B 0.014 0.022 0.356 Bl 0.030 0.070 0.77 1.77 C 0.008 0.015 0.204 0.381 1.290 29.3 32.7 8 5 0 1.150 01 0.005 E 0.600 0.625 15.24 15.67 6 El 0.485 0.580 12.32 14.73 5 0.13 5 e O.I00BSC 2.54BSC eA O.600BSC 15.24 SSC 0.700 0.115 N [2]. MAX 6.35 0.39 AI ea L 4, Dimensions A. Aland L are measured with the package seated In JEOEC seating plane gauge GS-3. 5. O. 01. and El dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 Inch (0.25mm). 6. E and ~ are measured with the leads constrained to be perpendicular to datum MILLIMETERS MIN 0.200 2.93 24 6 17.78 7 5.08 4 24 9 Rev. 0 12193 E28.6 (JEDEC MS-Oll·AB ISSUE B) 28 LEAD DUAL·IN.LlNE PLASTIC PACKAGE INCHES SYMBOL 7. ea and ec are measured at the lead tips with the leads unconstrained. ec must be zaro or greater. 8. B1 maximum dimensions do not Include darnbar protrusions. Oambar protrusions shall not exceed 0.010 Inch (0.25mm). 9. N Is the maximum number of terminal positions. 10. Comer leads (1. N. NI2 and NI2 + 1) for E8.3. EI6.3. EI8.3. E28.3. E42.6 will have a Bl dimension of 0.030 - 0.045 inch (0.76 -1.I4mm). MIN MAX A MILLIMETERS MIN 0.250 AI O.ot5 A2 0.125 MAX NOTES 6.35 4 0.39 . 0.195 4 3.18 4.95 0.558 B 0.014 0.022 0.356 Bl 0.030 0.070 0.77 1.77 C 0.008 O.ot5 0.204 0.381 1.585 35.1 39.7 8 0 1.380 01 0.005 E o.eOO 0.625 15.24 15.87 6 El 0.485 0.580 12.32 14.73 5 0.13 5 e 0.100 BSC 2.54BSC eA O.600BSC 15.24 SSC ea I L N 0.115 I 28 0.700 0.200 5 2.93 28 6 17.78 7 5.08 4 9 Rev. 0 12193 17·10 Package Outlines Dual-In-Line Plastic Packages (Continued) E40.6 (JEDEC MS-011-AC ISSUE B) 40 LEAD DUAL-IN-LiNE PLASTIC PACKAGE ,~-CQt ~.. INCHES SYMBOL E -wmM~m ~~,. ~~!~ -c- • m A2 A ., I$i 0.010 (0.25)®1 c I A IB@ I ee NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions. the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol usr in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and l are measured with the package seated In JEDEC seating plane gauge as-3. 5. D. 01. and El dimensions do not Include mold flash or protruslons. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and ~ are measured with the leads constrained to be perpandicular to datum 7. es and ec are measured at the lead tips with the leads unconstrained. ec must be zero or greater. 8. Bl maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Comer leads (1. N. NI2 and NI2 + 1) for E8.3. EI6.3. E18.3. E28.3. E42.6 will have a 81 dimension of 0.030 - 0.045 Inch (0.76 - 1.14mm). 1::2:J. MAX MILLIMETERS MIN MAX 0.250 A I. =;1 -I D PLANE~ MIN 6.35 A1 0.015 0.39 A2 0.125 0.195 3.18 4.95 B 0.014 0.022 0.356 0.558 B1 0.030 0.070 0.77 1.77 C 0.008 0.015 0.204 0.381 2.095 NOTES 4 4 50.3 8 0 1.980 01 0.005 E 0.800 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73' 5 53.2 0.13 5 e 0.100BSC 2.54BSC eA 0.600BSC 15.24BSC es l I 0.115 N I 0.700 0.200 2.93 40 5 6 17.78 7 5.08 4 40 9 Rev. 0 12193 E48.6 (JEDEC MS-011.AD ISSUE B) 48 LEAD DUAL-IN-LiNE PLASTIC PACKAGE INCHES SYMBOL MIN MAX A MILLIMETERS MIN MAX 0.250 6.35 AI 0.015 0.39 A2 0.125 0.195 3.18 4.95 8 0.014 0.022 0.356 0.558 Bl 0.030 0.070 0.77 1.77 C 0.008 0.015 0.204 0.381 2.480 NOTES 4 4 60.70 63.1 8 0 2.385 01 0.005 E 0.600 0.625 15.24 15.87 6 El 0.485 0.580 12.32 14.73 5 0.13 5 e O,l00BSC 2.54B8C eA 0.600B8C 15.24BSC es l N 0.700 0.115 0.200 48 5 17.78 2.93 5.08 48 6 7 4 9 Rev. 0 12193 CJZ zQ c:;!cc ~:5 (.)~ ~~ 17-11 Package Outlines Dual-In-Line Plastic Packages (Continued) E24.4 24 LEAD DUAL-IN-LiNE PLASTIC PACKAGE (400 MIL) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.142 0.161 3:60 4.10 2 A1 0.020 - 0.50 - 2 B 0.016 0.023 0.40 0.60 B1 0:042 0.053 1.05 1.35 C 0.008 0.013 0.20 0.35 D 1.185 1.204 30.10 30.60 3 E1 0.331 0.348 8.40 8.80 3 e eA RGURE1 L 0.100BSC 10.16 SSC 0.400 BSC 0.119 N IX 2.54BSC - I 24 I 00 4 - 3.0 2 24 15° rf' 5 1SO Rev. 0 12193 E28.6A E42.6A 28 LEAD DUAL·IN·LlNE PLASTIC PACKAGE 42 LEAD DUAL·IN·LlNE PLASTIC PACKAGE INCHES MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 0.178 0.196 4.5 5.0 A1 0.020 - 0.50 - B 0.016 0.023 0.40 0.60 B1 0.042 0.053 1.05 1.35 C 0.008 0.13 0.20 0.35 D 1.485 1.503 37.7 E1 0.508 0.523 12.9 MILLIMETERS NOTES SYMBOL MIN MAX 2 A 0.193 0.212 4.9 2 A1 0.040 - 1.0 MIN MAX 5.4 - - B 0.018 0.025 0.45 0.65 B1 0.046 0.057 1.15 1.45 C 0.008 0.013 0.20 0.35 36.2 3 D 2.162 2.181 54.9 13.3 0.516 0.531 13.1 NOTES 2 2 - 55.4 3 13.50 3 3 E1 e 0.100BSC 2.54BSC - e 0.100 BSC 2.54BSC - eA 0.600BSC 15.24SSC 4 eA 0.600BSC 15.24BSC 4 L IX - 0.119 N 00 - 3.0 28 28 15° 00 2 L 5 N 1SO IX Rev. 0 12193 NOTES: 1. ContrOlling Dimensions: MILUMETER. In case of conflict between English and Metric dimensions, the metric dimensions control. 2. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS·3. 3. D and E1 dimension's do not Include mold flash or protrusions. 4. is measured with the leads constrained to be perpendicular to base plane. 5. N Is the maxlmum number of terminal positions. !!AI 17·12 - 0.119 00 - 3.0 42 42 15° 00 2 5 1SO Rev. 0 12193 Package Outlines Small Outline (SOle) Plastic Packages ~fr T N 1 !I$I....... @I.@I 7!J (ltrn Jl 2l:j3l:jl:j SEAliNG PLANE ~D-1 B -- INCHES Al MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 AI 0.0040 0.0098 0.10 025 · · 9 hx4!i" ~1' ~L c MILLIMETERS SYMBOL L~I 1 r~Eilll /-,} e~1 M8.15 (JEDEC M5-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B 0.013 0.020 0.33 0.51 C 0.0075 0.0098 0.19 0.25 · D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 H 02284 0.2440 5.80 620 · · h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 127 e J 1010.10(0.004) 1 RIH 0.25(0.010) <&1)1 C 1A@I B ®I O.050BSC N a. 1.27BSC 8 0" B" I 0" 6 7 8 B" · Rev. 0 12193 NOTES: 1. Symbols are defined in the "MO Series Symbol usr In Section 22 of Publication Number 95. M16.15 (JEDEC M5-012·AC ISSUE C) 2. Dimensioning and tolerancing per ANSI YI4.5M·1982. 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS 3. Dimension "0" doss not include mold flash, protrusions or gate burrs. Mold flash, protrusion end gate burrs shall not exceed O.I5mm (0.006 inch) per side. SYMBOL MIN MAX MIN MAX NOTES 4. Dimension"E" does not include interlead flash or protrusions. In· terlead flash end protrusions shall not exceed 0.25mm (0.010 Inch) per side. A 0.0532 0.0688 1.35 1.75 · AI 0.0040 0.0098 0.10 025 · B 0.013 0.020 0.33 0.51 9 5. The chamfer on the body is optional. If It is not present, a visual index feature must be located within the crosshatched area. C 0.0075 0.0098 0.19 025 · D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. H 02284 02440 5.80 620 · · h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 127 e 8. Terminal numbers are shown for referance only. 9. The lead width "8", as measured O.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. O.050BSC N a 1.27BSC 16 0" 16 8° 0" 6 7 B" · Rev. 0 12193 17·13 Package Outlines Small Outline (SOle) P~astic Packages (Continued) M16.3 (JEDEC M8-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 A1 0.0040 0.0118 0.10 0.30 · · 9 B 0.013 0.0200 0.33 0.51 C 0.0091 0.0125 0.23 0.32 · D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.0506SC · 1.27BSC H 0.394 0.419 10.00 10.65 · h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 16 N a. 1.27 16 0° 8° 00 6 7 B" · Rev. 0 12193 NOTES: 1. Symbols are defined in the "MO Series Symbol usr in Section 2.2 of Publication Number 95. M18.3 (JEDEC M8-013-AB ISSUE C) 18 LEAD WIDE BODY SMALL OUTl.INE PLASTIC PACKAGE 2. Dimensioning and toleranclng per ANSI Y14.5M-1982. 3. Dimension"D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall-not exceed 0.15mm (0.006 Inch) per side. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 A1 0.0040 0.0118 0.10 0.30 · · 9 4. Dimension "E" does not include interlead flash or protrusions. In· terlead flash and protrusions shall not exceed 0.25mm (0.010 Inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual Index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 6 0.013 0.0200 0.33 0.51 C 0.0091 0.0125 0.23 0.32 - D 0.4469 0.4625 11.35 11.75 3 E 0.2914 0.2992 7.40 7.60 4 H 0.394 0.419 10.00 10.65 · · h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 e 8. Terminal numbers are shown for reference only. 9. The lead width "S", as measured O.36mm (0.014 Inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 Inch) 10. Controlling dimension: MILLIMETER. Converted Inch dimensions are not necessarily exact. 0.0506SC 18 N a. 1.2768C 00 I 18 8° 00 6 7 B" · Rev. 0 12193 17·14 Package Outlines Small Outline (SOle) Plastic Packages (Continued) M20.3 (JEDEC M5-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTUNE PLAS'nC PACKAGE INCHES MIN MAX MIN MAX A 0.0926 0.1043 2.35 2.65 A1 0.0040 0.0118 0.10 0.30 ~D---1 ~~--+-§i :~ ~ 1010.10(0.00 11 1$J0.25(o.0101@lcIA@la@1 4 NOTES - 9 - B 0.013 0.0200 0.33 0.51 C 0.0091 0.0125 0.23 0.32 D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050B50 1.27880 - H 0.394 0.419 10.00 10.65 h 0.010 0.029 0.25 0.75 5 L 0.Q16 0.050 0.40 1.27 6 80 00 20 N a NOTES: 1. Symbols are defined In the "MO Series Symbol Usr in Section 2.2 of Publication Number 95. 2. Dimensioning and toleranclng per ANSI Y14.5M-1982. 3. Dimension "0" does not Include mold flash. protrusions or gate burrs. Mold flash. protrusion and gate burrs shall not exceed O.l5mm (0.006 inch) per side. 4. Dimension "eo does not include Interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 Inch) per side. MILUMETERS SYMBOL 20 00 7 80 Rev. 0 12193 M24.3 (JEDEC MS.013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASnC PACKAGE MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 A1 0.0040 0.0118 0.10 0.30 · 5. The chamfer on the body Is optional. If It is not present, a visual Index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" Is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Tha lead width "B", as measured O.36mm (0.014 Inch) or greater above tha seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILUMETER. Converted Inch dimensions are not necessarBy exact. B 0.013 0.020 0.33 0.51 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05BSC 1.27BSO 9 - H 0.394 0.419 10.00 10.65 · h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 24 N a 00 24 SO 00 I 6 7 SO · Rev. 0 12193 17·15 Package Outlines Small Outline (SOle) Plastic Packages (Continued) M24.2 24 LEAD SMALL OUTUNE PLASTIC PACKAGE (200 MIL) INCHES MIN MAX MIN MAX A 0.067 0.066 1.70 2.25 Al 0.002 0.011 0.05 0.30 6 0.014 0.021 0.35 0.55 C 0.006 0.011 0.15 0.30 0 0.567 0.606 14.9 15.4 1 E 0.205 0.220 5.2 5.6 2 f--D---I~ ~~J e 0.296 0.326 7.5 8.3 L 0.012 0.027 0.30 0.70 N r::Il+I~o.24~@r"l1 a 24 0" NOTES 1.27 esc 0.0506SC H -T T-£;~~ NOTES: 1. Dimension "0" does not Include mold flash, protrusions or gate burrs. 2. Dimension "E" does not Include Interlead flash or protrusions. 3. "L" Is the length of terminal for soldering to a substrate. 4. "N" Is the number of terminal positions. 5. Terminal numbers are shown for reference only. 6. Controlling dimension: MILLIMETER. Converted Inch dimensions are not necessarily exact. MILLIMETERS SYMBOL 3 24 10" 0" 4 - 10" Rev. 0 12193 M28.3A 28 LEAD SMALL OUTLINE PLASTIC PACKAGE (300 MIL) INCHES MILLIMETERS SYMBOL MIN MAX MIN A AI 0.085 0.106 2.15 2.7 0.002 0.011 0.05 0.30 6 0.014 0.021 0.35 0.55 C 0.004 0.009 0 0.737 0.755 E 0.296 0.311 e 0.056SC H 0.390 L 0.012 N a 0.10 0.25 18.7 19.2 7.50 7.90 1.2769C 0.421 9.90 0.027 0.30 28 O· MAX 10.70 0.70 28 10" 0" NOTES - 1 2 3 4 10" Rev. 0 12193 17-16 Package Outlines Small Outline (SOle) Plastic Packages (Continued) M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE NiMr.L.L...u....y MILUMETERS INCHES SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 Al 0.0040 0.0118 0.10 0.30 · · B 0;013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 · D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 rELo-j M~--t-§i e :-.l~ 1010.10(0.00411 f+lo.25(o.olol@lcIA@IB®1 1.27BSC · H 0.394 0.419 10.00 10.65 · h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 N a NOTES: 1. Symbols are defined in the "MO Series Symbol 2.2 of Publication Number 95. 0.05BSC 0" 8" 0" 6 7 28 28 8" · Rev. 0 12/93 usr in Section 2. Dimensioning and tolerancing per ANSI Y14.5M·1982. 3. Dimension "0- does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not Include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 Inch) per side. 5. The chamfer on the body is optional. If it Is not present, a visual index feature must be located within the crosshatched area. 6. "L" Is the length of terminal for soldering to a substrate. 7. "N. Is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "8., as measured 0.36mm (0.014 Inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted Inch dimensions are not necessarily exact. 17·17 Package Outlines Shrink Small Outline (SSOP) Plastic Packages M28.209 (JEDEC Mo.1so.AH ISSUE A) 28 LEAD SHRINK SMALL OUTLINE PLAsnc PACKAGE MILUMETERS INCHES SYMBOL MIN MAX MIN A - 0.083 - 2.13 A1 0.002 0.009 0.05 0.25 0.38 ~D-1 W~-+-.I±Il :--1 ~ 1+1 0.25(0.010) @I c IA41;j B@I NOTES· 8 0.009 0.014 0.22 C 0.004 0.007 0.09 0.20 9 - D 0.390 0.413 9.90 10.50 3 E 0.197 0.220 5.00 5.60 4 e 0.026BSC H 0.292 L 0.025 a I I 0.658SC 00 I - 0.322 7.40 8.20 - 0.040 0.63 1.03 6 7 8" 00 28 N 1010.10(0.004)1 MAX 28 8" Rev. 0 12193 NOTES: 1. Symbols are defined In the "MO Series Symbol Ust" In Section 2.2 of Publication Number 95. 2. Dimensioning and toleranclng per ANSI Y14.5M-1982. 3. Dimension "0- does not Include meld 1Iash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed O.2Omm (0.0078 Inch) per side. 4. Dimension "eo does not Include interlead nash or protrusions. Interlead flesh and protrusions ahall not exceed O.2Omm (0.0078 Inch) per side. 5. The chamfer on the body Is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" Is the length of termlnsi for soldering to a substrate. 7. "N" Is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "8", as measured O.36mm (0.014 Inch) or greater above the seating plane, shall not exceed a maximum value of 0.51mm (0.020 Inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 17-18 Package Outlines Plastic Leaded Chip Carrier (PLCC) Packages 0.042 (1.07) h"'r-·' \' .T!!" . ' . . .",'" h . . . . ." 0.042 (1.07) 0.056 (1.42) 0.048 (1.22) 0 ~ ~045 (1.14) ~) 1~ I mr~L E1 E .j. N20.35 (JEDEC M8-018 ISSUE A) I I 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.004 (0.10) C INCHES MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 · Al 0.090 0.120 2.29 3.04 · 0 0.385 0.395 9.78 10.03 · ~ ~J - '::~f"'" 1t:'=:Jr= ~~-~' A1 IA_ D1 o 0.020 (0.51) MAX 3PLCS MILLIMETERS SYMBOL 01 0.350 0.356 8.89 9.04 3 02 0.141 0.169 3.59 429 4,5 E 0.385 0.395 9.78 10.03 - El 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4,5 N MIN 20 20 6 Rev. 0 12193 ~SEAnNG • 0.026 (0.66) 0.032 (0.81) PLANE N28.45 (JEDEC M5-018 ISSUE A) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE m-.t·"' . . 0.045 (1.14) MIN 0.013 (0.33) c::! INCHES 0.025 (0.84) MIN MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 420 4.57 - Al 0.090 0.120 229 3.04 · 0 0.485 0.495 12.32 12.57 - 01 0.450 0.456 11.43 11.58 3 02 0.191 0.219 4.86 5.56 4,5 E 0.485 0.495 12.32 12.57 - El 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4,5 VIEW "A" TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M·1982. 3. Dimensions 01 and El do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. 4. To be measured at seating plane ~ contact point. 28 N 5. Centerline to be determined where center leads exit plastic body. 28 6 Rev. 0 12193 6. "N" is the number of terminal positions. N44.65 (JEDEC M5-018 ISSUE A) 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 420 4.57 - Al 0.090 0.120 229 3.04 - 0 0.685 0.695 17.40 17.65 · 01 0.650 0.656 16.51 16.68 3 02 0.291 0.319 7.40 8.10 4,5 E 0.685 0.695 17.40 17.65 - El 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4,5 N 44 44 6 Rev. 0 12193 ., 17-19 Package Outlines Metric Plastic Quad Flatpack Packages ~~ Q32.A 32 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES rt:=iro!=!o!""""!o!o!o!=!o!!!"', ,, ,, @ i ,, -.--------r--------- -- • MILUMETERS SYMBOL MIN MAX MIN MAX A 0.054 0.072 1.35 1.85 Al 0.000 0.011 0.00 0.30 B 0.008 0.017 0.20 0.45 5 0 0.347 0.362 8.80 9.20 2 01 0.272 0.287 6.90 7.30 3,4 E 0.347 0.362 8.80 9.20 2 El 0.272 0.287 6.90 7.30 3,4 L 0.012 0.027 0.30 0.70 N 32 32 e 0.032BSC 0.80BSC NOTES - 6 Rev. 0 12193 PIN 1 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. DImensions 0 and E to be determined at seating plane E2:]. 3. Dimensions 01 andEl to be determined at datum PlanetB:]. 4. Dimensions 01 and El do not inclUde mold protrusion. 5. Dimension B does not include dambar protrusion. 6. "N" is the number of terminal pOSitions. 17-20 Package Outlines Metric Plastic Quad Flatpack Packages (Continued) Q44.A (JEDEC MO.108AA·2ISSUEA) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE ~~~~,;!'I INCHES ,, , ~ ~.~ ........ t-.........1 e PIN 1 MILLIMETERS MIN MAX MIN MAX A . 0.093 - 2.35 Ai 0.000 0.010 0.00 0.25 A2 o.on 0.083 1.95 2.10 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.510 0.530 12.95 13.45 3 D1 0.390 0.398 9.90 10.10 4,5 E 0.510 0.530 12.95 13.45 3 E1 0.390 0.398 9.90 10.10 4,5 L 0.026 0.037 0.65 SYMBOL NOTES - - - 0.95 N 44 44 e 0.032BSC O.GOBSC 7 Rev. 0 12193 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be detennlned at seating plane [:2:]. GtI. 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not Include mold protrusion. Allowable protrusion is 0.25mm (0.010 Inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 Inch) total. 7. "N" is the number of terminal positions. 17-21 Package Outlines Metric Plastic Quad Flatpack Packages (Continued) Q44.B 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES e MILLIMETERS SYMBOL MIN MAX MIN MAX A - 0.093 - 2.35 NOTES A1 0.000 0.004 0.00 0.10 A2 0.081 0.089 2.05 2.25 B 0.012 0.Q18 0.30 0.45 D 0.544 0.559 13.80 14.20 3 D1 0.390 0.398 9.90 10.10 4.5 6 E 0.544 0.559 13.80 14.20 3 E1 0.390 0.398 9.90 10.10 4.5 L 0.042 0.053 1.05 - 1.35 N 44 44 e 0.032BSC 0.80BSC 7 Rev. 0 12/93 NOTES: 1. Controlling dimension: MILUMETER. Converted Inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane~. 4. Dimensions D1 and E1 to be determined at'datum plane 8:8. 5. Dimensions D1 and E1 do not Include mold protrusion. Allowable protrusion Is 0.25mm (0.010 Inch) per side. 6. Dimension B does not Include dambar protrusion. Allowable dambar protrusion shall be O.OSmm (0.003 Inch) total. 7. "N" is the number of terminal positions. 0.13/0.20 0.00510.008 17-22 Package Outlines Dual-In-Line Frit-Seal Ceramic Packages ----"~--- I! ~ T r I I 1 + E PLANE£ A A ". . b-I- B:11 QP II ~ A MAX MIN MAX A · 0.200 · 5.08 · b 0.014 0.026 0.36 0.66 2 bl 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 b3 0.023 0.045 0.58 1.14 4 c:::b ~ U] •• L I I t m I$Icec@ICIA.S®lo®1 ~ :.t- ~ ~ ~ eA c ... I- NOTES: 1. Index area: A nolch or a pin one identification mark shall be locat· ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer's Identification shall not be used as a pin one identification mark. 4. Corner leads (1. N. Nl2. and Nl2+ 1) may be configured with a partial lead paddle. For this configuration dimension b3 replacas dimansion bl. 5. This dimension allows for off-center lid. meniscus. and glass overrun. · c 0.008 0.018 020 0.46 2 0.008 0.015 0.20 0.38 3 D · 0.785 E 0.220 0.310 · 5.59 19.94 5 7.87 5 e O.l00BSC 2.54BSC eA 0.3OOBSC 7.62BSC 0.150BSC · · · 3.81 BSC L Q 0.125 0.200 3.18 5.08 · 0.Q15 0.060 0.38 1.52 6 7 Sl 0.005 0.005 · · 0.13 52 0.13 · · a 900 1050 900 1050 aaa · · · · 0.015 · 0.38 bbb 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfacas. when solder dip or tin plate lead finish Is applied. NOTES cl eA12 l$Iaaa@lcIA.S®lo® 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M appllas to lead plating and finish thickness. MILLIMETERS MIN SECTlONA·A ~O---l----.l SEA11NGJ~Rf ~ ~ (e) INCHES SYMBOL (b) I$Ibbb®lcIA.S®lo®1 81 b2 H :tfAi 1 rtb1M~ ----~-.B- SASE PLANE LE,NISH F14.3 MIL·ST~1835 GDIP1·T14 (~1. CONFIGURATION A) 14 LEAD DUAL-IN-UN!: FRIT·SEAL CERAMIC PACKAGE ccc M 0.030 0.010 0.0015 N · 0.76 · · 14 · · · · 0.25 · 0.038 2 14 8 F16.3 MIL-sT~l835 GDIP1·T16 (~2. CONFIGURATION A) 16 LEAD DUAL-IN·UNE FRIT·SEAL CERAMIC PACKAGE MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A · 0.200 · 5.08 NOTES · b 0.014 0.026 0.36 0.66 2 3 6. Dimension Q shall be measured from the seating plane to the base plane. bl 0.014 0.023 0.38 0.58 7. Measure dimension Slat all four corners. b2 0.045 0.065 1.14 1.65 8. N Is the maximum number of terminal positions. · b3 0.023 0.045 0.58 1.14 4 9. Dimensioning and Ioleranclng per ANSI Y14.5M· 1982. 10. ContrOlling Dimension: INCH c 0.008 0.018 020 0.46 2 cl 0.008 0.015 0.20 0.38 3 D · 0.840 · 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.548SC eA 0.300BSC 7.628SC eA/2 3.818SC L 0.125 0.200 3.18 5.08 · Q 0.015 0.060 0.38 1.52 6 · 0.13 7 51 0.005 52 0.005 · 0.13 · · a 900 1050 900 1050 aaa · · · · 0.015 · · · · 0.38 bbb ccc M N 17·23 0.15085C · · · 0.030 0.010 0.0015 16 0.76 0.25 0.038 16 · · · · · 2 8 Package Outlines Dual-In-Line Frlt-Seal Ceramic Packages (Condnued) 01 LEAD FINISH ~~~l (e) F18.3 MIL-STD-l835 GDIP1-T18 ([).6, CONFIGURATION A) 18 LEAD DUAL-IN-UNE FRIT-SEAL CERAMIC PACKAGE INCHES MilliMETERS SYMBOL MIN MAX MIN MAX A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 bl 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 cl 0.008 0.015 0.20 0.38 3 D - 0.960 - 24.38 5 E 0.220 0.310 5.59 7.Pi1 5 e 0.100 BSC 2.54BSC eA 0.300BSC 7.62BSC eA/2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and corM shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead flnish is applied. 3. Dimensions bl and cl apply to lead base metal only. Dimension M spplies to lead plating and finish thickness. 4. Corner leads (1, N, Nl2, and Nl2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimenslon bl. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension Sl at all four comers. 8. N is the maximum number of terminal positions. 9. Dimensioning and toleranclng per ANSI Y14.5M - 1982. 10. ContrOlling Dimension: INCH 17-24 NOTES 0.150BSC - 3.81 BSC - L 0.125 0.200 3.18 5.08 a 0.015 0.070 0.38 1.78 6 Sl 0.005 - 0.13 7 52 0.005 - - 0.13 - a 90" 105° 90" 105" aaa bbb ccc M N - 0.015 0.030 0.010 - 0.0015 18 - 0.25 - 0.038 2 0.38 - 0.76 - 18 8 Package Outlines Dual-In-Line Frit-Seal Ceramic Packages (Continued) e1 LEAD FINISH ~~~l (e) F20.3 MIL-STD-1835 GDIP1-T20 (0..8, CONFIGURAnON A) 20 LEAD DUAL-IN-UNE FRIT-SEAL CERAMIC PACKAGE MILUMETERS INCHES SYMBOL MIN MAX MIN MAX A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 bl 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 cl 0.008 0.Q15 0.20 0.38 3 D - 1.060 - 26.92 5 E 0.220 0.310 5.59 7.87 5 e 0.10088C 2.548SC eA 0.30088C 7.6288C eA/2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin ona Identification mark. 2. The maximum limits of lead dimensions band c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or lin plate lead finish is applied. 3. Dimensions bl and cl apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Comar leads (1, N, Nl2, and Nl2+1) maybe configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension Sl at all four corners. 8. N Is the maximum number of terminal positions. 9. Dimensioning and toleranclng per ANSI Y14.5M -1982. 10. Controlling Dimension: INCH 17-25 NOTES O.l5088C 3.81 esc L 0.125 0.200 3.18 5.08 Q 0.015 0.070 0.38 1.78 Sl 0.005 - 0.13 S2 0.005 - 0.13 - a. 90" 1050 90" 1050 eaa - 0.015 - 0.38 bbb ccc M N - 0.030 0.010 0.0015 20 - 0.76 20 6 7 - - 0.25 - 0.038 2 8 Package Outlines Dual-In-Line Frit-Seal Ceramic Packages (Continued) F24.3 MIL-sTD-1835 GDIP3-T24 (0-9, CONFIGURAnON A) 24 LEAD DUAL-IN-UNE FRIT-SEAL CERAMIC PACKAGE INCHES MIWMETERS SYMBOL MIN MAX MIN MAX A - 0.220 - 5.08 - b 0.014 0.026 0.36 0.66 2 3 b1 0.014 0.023 0.36 0.56 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.56 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.280 - 32.51 5 E 0.220 0.310 5.59 7.ff1 5 e 0.100BSC 2.54BSC eA 0.3OOBSC 7.62BSC eAI2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one Identification mark. 2. The maximum limits of lead dimensions band c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish Is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, Nl2, and Nl2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension shall be measured from the seating plane to the base plane. a 7. Measure dimension S1 at all four comers. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: INCH 17-26 NOTES 0.150BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 a 0.D15 0.060 0.38 1.52 6 S1 0.005 0.13 - 7 S2 0.005 - a. 90" 105° aaa bbb ccc M N - 0.015 0.030 0.010 0.0015 24 0.13 - 900 10SO - 0.38 0.76 0.25 0.038 24 2 8 Package Outlines Dual-In-Line Frit-Seal Ceramic Packages (Continued) e1 LEAD FINISH ~:r&:=~l (e) F24.6 MIL-STI).1835 GDlP1-T24 (0-3, CONFIGURATION A) 24 LEAD DUAL-IN-UNE FRIT-SEAL CERAMIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 bl 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 cl 0.008 0.015 0.20 0.38 3 D - 1.290 - 32.n 5 E 0.500 0.610 12.70 15.49 5 e 0.100BSC 2.5488C eA 0.600BSC 15.2488C eA/2 N0TE8: 1. Index area: A notch or a pin one Identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions band c or M shall be maasured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish Is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimanslon M applies to lead plating and finish thickness. 4. Corner leads (t, N, N/2, and N/2+ 1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimansion b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the bese plane. 7. Measure dimension 81 at all four comers. 8. N is the maximum number of terminal positions. 9. Dimensioning and toleranclng per AN81 Y14.5M - 1982. 10. Controlling Dimension: INCH 17-27 NOTES 7.6288C 0.300BSC - L 0.120 0.200 3.05 5.08 - Q 0.015 0.075 0.38 1.91 6 81 0.005 - 0.13 S2 0.005 - 0.13 - ex aaa 90° 105° 90" 105° - 0,015 - 0.38 bbb ccc M N - 0.030 0.010 0.0015 24 - 0.76 24 7 - 0.25 - 0.038 2 8 Package Outlines Dual-In-Llne Frit-Seal Ceramic Packages (Continued) e1 LEAD FINISH ~~~l (e) F28.6 MIL·STD-1835 GDIP1·T28 (D-10, CONFlGURAnON A) 28 LEAD DUAL-IN-UNE FRIT-8EAL CERAMIC PACKAGE MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 3 b1 0.014 0.023 0.36 0.58 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.Q18 0.20 0.46 2 c1 0.008 0.015 020 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 12.70 15.49 5 e O.10088C 2.54BSC eA 0.60088C 15.24BSC eA/2 NOTES: 1. Index area: A notch or a pin one Identification mark shall belceated adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Comer leads (1, N, N/2, and Nl2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for olf-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimenslon S1 at all four corners. 8. N Is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M -1982. 10. Controlling Dimension: INCH 17-28 NOTES 7.62BSC 0.30088C - L 0.125 0.200 3.18 5.08 Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 7 S2 0.005 - - 0.13 - a 90° 105° 900 105" aaa bbb ccc M N - 0.015 0.030 0.010 - 0.0015 28 - 0.38 0.76 0.25 0.036 28 - 2 8 Package Outlines Dual-In-Line Frit-Seal Ceramic Packages (Continued) e1 LEAD FINISH ~~~l Ie) F40.6 MIL·ST\).1835 GDIP1·T40 (0-5, CONFIGURATION A) 40 LEAD DUAL-IN-UNE FRIT·SEAL CERAMIC PACKAGE INCHES MIWMETERS SYMBOL MIN MAX MIN MAX A · 0.225 · 5.72 · b 0.014 0.026 0.36 0.66 2 3 b1 0.014 0.023 0.36 0.58 b2 0.045 0.065 1.14 1.65 · b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D · 2.096 53.24 5 E 0.510 0.620 15.75 5 2. The maximum limits of lead dimensions band c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or lin plate lead finish Is applied. 0.100BSC 2.54BSO eA 0.600BSC 15.24BSC 0.200 3.18 5.08 a 0.015 0.070 1.78 81 S2 0.005 0.005. . . 0.38 0.13 . a 90" 105° 90" 10SO · 0.015 · · 0.38 aaa bbb 4. Corner leads (1, N, Nl2, and Nl2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. N a 7. Measure dimension S1 at atl four corners. 8. N Is the maximum number of terminal posilions. 9. Dimensioning and tolerancing per ANSI Y14.5M· 1982. 10. Controlling Dimension: INCH 17·29 7.62BSC 0.125 ccc 6. Dimension shall be measured from the seating plane to the base plane. 0.300BSC L 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 5. This dimension allows for off-center lid, meniscus, and glass overrun. · 12.95 e eAI2 NOTES: 1. Index area: A nolch or a pin one Identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's Identification shall not be used as a pin one IdentifICation mark. NOTES M · · 0.030 0.010 · 0.0015 40 . 0.13 0.76 · 0.25 · 0.038 40 · · · · 6 7 · · · · · 2 8 Package Outlines Metal Seal Dual-In-Line Ceramic Packages c1 LEAD FINISH $f. ~! Mtb1~ (b) ~D~ t t SEAnN~ NW~AU PLANE£ I •• P~N~ S1 b2 =tW [JJ:1(:C:1~ ~ ~ A A~ !:b--- []] I$lccc®lcIA-e®ID®1 INCHES I I L t MIN MAX MIN MAX A - 0.232 - 5.92 - b 0.014 . 0.026 0.36 0.66 2 3 ~ rf--i ~' BA c __ MIU.IMETERS SYMBOL SECTIONA-A I$lbbb@lcIA-e@ID@1 M 028.6 MIL-sT1).1835 CDlP2·T28 (1).10, CONFIGURATION C) 28 LEAD METAL SEAL DUAI.-IN-UNE CERAMIC PACKAGE l- I$lccc@lcIA-e@ID(S b1 0.014 0.023 0.36 0.58 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 0.46 ,. 0.38 2 c 0.008 0.018 0.20 c1 0.008 0.D15 0.20 D - 1.490 - 37.85 5 E 0.500 0.610 12.70 15.49 5 e 0.100BSC 2.54B8C sA 0.600BSC 15.24B8C eM NOTE8: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centrOid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, Nl2, and NI2+1) mey be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscUS, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the basepiane. 7. Measure dimension 81 at all four corners. 8. Measure dimension 82 from the top of the ceramic body to the nearest metallization or lead. 9. N Is the maximum number of terminal positions. 10. Braze fillets shall be concave. 11. Dimensioning and tolerancing per AN81 Y14.5M - 1982. 12. Controlling Dimension: INCH. NOTES - 7.62BSC 0.3OOBSC L 0.125 0.200 3.18 5.08 Q 0.015 0.060 0.38 1.52 6 81 0.005 0.13 - 7 S2 0.005 - 0.13 - a. 90" 1050 90" 1050 0.015 - 0.38 aea bbb ccc M N - 0.030 0.010 0.0015 28 - 8 - - 0.78 0.25 - 0.038 28 . , 17-30 3 2 9 Package Outlines Metal Seal Dual-in-Line Ceramic Packages (Continued) D40.6 MIL.sTo.1835 CDIP2-T40 (1).5, CONFIGURATION C) 40 LEAD METAL SEAL DUAL-IN-LINE CERAMIC PACKAGE INCHES MIWMETERS NOTES SYMBOL MIN MAX MIN MAX A · 0.225 · 5.72 · b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 · b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D · 2.096 · 53.24 5 E 0.510 0.620 15.75 5 e 0.100BSC 2.54BSC · eA 0.600BSC 15.2468C · · · eAI2 NOTE8: 1. Index area: A notch or a pin one Identification mark shall be locat· ed adjacenl to pin one and shall be located within the shaded area shown. The manufaclurar's Identification shall not be used as a pin one identification mark. 2. The maximum limits 01 lead dimensions b and c or M shall be measured at the cantroid of the finished lead surfaces, when sol· der dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N12, and NI2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension 81 at all four corners. 8. Measure dimension 82 from the top of the ceramic body to the nearest metallization or lead. 9. N Is the maximum number of terminal positions. 10. 6raze fillets shall be concave. 11. Dimensioning and tolerancing per AN81 Y14.5M· 1982. 12. Controlling Dimension: INCH. 17-31 12.95 7.62680 0.300BSC L 0.125 0.200 3.18 5.08 Q 0.015 0.070 0.38 1.78 81 0.005 S2 0.005 . 0.13 . . a aaa 90" 1050 900 1050 · · 0.015 · 0.38 bbb ccc M N . 0.030 · 0.010 · 0.0015 40 0.13 · · · 8 0.25 · · · · 0.038 2 0.76 40 6 7 9 PaCkage Outlines Metal Seal Dual-in-Line Ceramic Packages (Continued) c1 LEAD FINISH .--'-Is'ssm=~l Ie) 042.6 42 LEAD METAL SEAL DUAL-IN·UNE CERAMIC PACKAGE INCHES MILUMETERS SYMBOL MIN MAX MIN MAX A 0.142 0.225 3.60 5.72 · b 0.014 0.026 0.36 0.68 2 3 NOTES: 1. Index area: A notch or a pin one identification mark shall be locat· ed edJacent to pin one and shall 'be loCated within the shaded area shown. TIKi msnufacturer's identification shall not be used as a pin one Identification mark. 2. The maximum IlmIIs ot lead dimensions band corM shall be msasured at the centroid ot the finished lead surfaces, when soldar dip or tin plate lead tlilish Is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M appUes to lead plating and finish thickness. 4. Comer leads (1, N, Nl2, and NI2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows tor otf-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all tour corners. B. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. ~ 9. N is the maximum number ot terminal positions. 10. Braze fillets shaD be concave. 11. Dimensioning and toleranclng per ANSI Y14.5M ·1982. 12. Controlling dimension: INCH. 17·32 b1 0.014 0.022 0.36 0.56 b2 0.035 0.043 1.90 1.10 b3 · · · · NOTES · 4 c 0.009 0.015 0.23 ,0.36 2 c1 0.009 0.012 0.23 0.30 3 D 2.0B3 2.122 52.9 53.9 5 E 0.510 0.620 12.95 15.75 5 · e O.looBSC 2.54880 eA 0.6ooBSC 15.24BSC eA/2 0.3OOBSC 7.62880 L 0.130 · 3.30 Q 0.039 1.00 Sl 0.005 0.13 S2 0.005 · · · 0.13 · · · · a 90" 1050 90" 1050 aaa · 0.015 · · · · 0.36 bbb ccc M N · 0.030 · · 0.010 0.0015 42 0.76 42 · · · 6 7 8 · · · 0.25 · 0.038 2 9 Package Outlines \IIIetal Seal Leadless Ceramic Chip Carrier Packages J20.A MIL·STD-l835 CQCCl-N20 (C-2) 20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER INCHES E3 8 MIN MAX MIN MAX NOTES A 0.060 0.100 1.52 2.54 6,7 Al 0.050 0.088 1.27 2.23 7 8 - - - - Bl 0.022 0.028 0.56 0.71 E L B2 TL r h x 45" k=---""lJJ A L, M , 1 TII~~~~~~~II 1 MILUMETERS SYMBOL PLANE 2 PLANE 1 B3 0.006 0.022 0.15 0.56 0 0.342 0.358 8.69 9.09 01 0.200BSO 5.089S0 D2 O.I00BSO 2.549S0 - 0.358 - 9.09 E 0.342 0.358 8.69 9.09 El O.200BSO 5.089SC 2.548S0 E2 O.I00BSO E3 - e 0.050BSO 9.09 1.279SC - 0.015 - - 0.38 2 2 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 Ll 0.045 0.055 1.14 1.40 L2 0.075 0.095 1.91 2.41 L3 0.003 0.015 0.08 NO t t 0.358 - - 03 el 83 - 1.83 REF 0.072 REF 4 2,4 5 0.38 5 - - - 3 NE 5 5 3 N 20 20 3 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.381mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N° is the maximum number of terminals. Symbols "NO" and "NE" are the number of terminals along the sides of length "0- and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrlcally connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Ohlp carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 inch solder thickness on pads. 17·33 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J20.B 20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER MILUMETERS INCHES E3 SYMBOL MIN MAX MIN MAX NOTES A 0.070 0.097 1.78 2.46 6,7 A1 0.054 0.077 1.37 1.96 7 B - - - - B1 0.020 0.030 0.51 0.76 E ~ill B2 I 0.022 0.15 0.56 0 0.342 I 0.358 8.69 9.09 D2 ,11 . . . 2.54BSC 8.26 8.51 E 0.342 0.358 8.69 9.09 e e1 t 0.100BSC 0.335 E2 i 5.08BSC 0.325 E3 83 0.200BSC D3 E1 PLANE 1 1.83 REF 0.006 01 A1 0.072 REF B3 5.08BSC 0.200BSC 0.100BSC 0.325 2.54BSC 0.335 O.050BSC 8.51 1.27BSC - 0.015 8.26 - 0.38 2 2 - 2,4 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.042 0.058 1.07 1.47 L1 0.042 0.058 1.07 1.47 L2 0.075 0.095 1.91 2.41 L3 0.003 0.015 0.08 0.38 - NO 5 5 3 NE 5 5 3 N 20 20 3 NOTES: 1. Metallized castellaUons shall be connected to plane 1 terminala and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connecUon with the optional plane 2 terminals. 2. Unless otherwise specilled, a minimum clearance of 0.015 inch (0.381 mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads. etc.) 3. Symbol "N" Is the maxlmum number of terminals. Symbols "NO" and "NE" are the number of termlnala along the sides of length "0" and -eo, respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectricaUy connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 Inch solder thickness on pads. 17-34 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J28.A MIL·STD-1835 CQCC1·N28 28 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER SYMBOL A Al 8 81 82 83 0 01 02 03 E El E2 E3 e el h j L Ll l2 L3 NO NE N INCHES MIN MAX 0.060 0.100 0.050 0.088 · . 0.022 0.028 0.072 REF 0.006 0.022 0.442 0.460 0.3008Se 0.1506Se 0.460 0.442 I 0.460 0.3006Se 0.1506Se · I 0.460 0.0506Se . 0.015 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 0.003 0.015 7 7 28 · MILLIMETERS MIN MAX 1.52 2.54 1.27 223 · . 0.56 0.71 1.83 REF 0.15 0.56 11.23 11.68 7.628Se 3.816Se 11.68 11.23 I 11.68 7.626Se 3.816Se 11.68 1.276Se . 0.38 1.02 REF 0.51 REF 1.14 1.40 1.14 1.40 1.90 2.41 0.038 0.08 7 7 28 NOTES 6, 7 7 2,4 · 2 · 2 2 5 5 3 3 3 NOTES: 1. Metallized castel lations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwfse specified, a minimum clearance of 0.015 Inch (0.381mm) shall be maintained between all metallized features (e.g., lid, castellalions, terminals, thermal pads, etc.) 3. Symbol "N"ls the maximum number of terminals. Symbols "NO" and "NE" are the number of terminals along the sides of length "0" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminels shall be eliectricaUy connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from thet shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 inch solder thickness on pads. 17·35 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J44.A ~:"""I._~_~ -+--......... I x 45" l-! MIL·STD-1835 COCC1-N44 (0.5) 44 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER I T E3 B TL r h x 45" A L MIN MAX MIN MAX NOTES A 0.064 0.120 1.63 3.05 6,7 A1 0.054 0.068 1.37 2.24 7 B 0.033 0.039 0.84 0.99 4 B1 0.022 0.028 0.561 0.71 2,4 E ~JJJ L B2 I TII~~~~~~~II 1 I 0.022 0.15 0 0.840 I 0.662 16.28 0.002 E 0.840 0.002 E3 e e1 B3 0.500BSC . 8.35BSC 16.81 16.81 12.70BSC 6.35BSC 0.662 O.050BSC . 16.81 1.27BSC . 0.015 16.81 16.26 0.250 BSC . 0.56 . 0.38 · · · · · 2 · · · 2 · 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 L1 0.045 0.055 1.14 1.40 L.2 0.075 0.095 1.90 2.41 La 0.003 0.015 0.08 0.38 NO i t 0.250BSC . E2 I 12.70BSC 0.500BSC 03 E1 PLANE 1 1.83 REF 0.006 02 lpLANEZ 0.072 REF B3 01 M I MILLIMETERS INCHES SYMBOL 11 · · · · 11 3 NE 11 11 3 N 44 44 3 NOTES: 1. MetalUzed castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise speclfled, a minimum clearance of 0.015 Inch (0.381 mm) shall be maintained between all metallized features (e.g., lid, castellalions, terminals, thermal pads, ele.) 3. Symbol "N" is the maximum number of terminals. Symbols "NO" and "NE" are the number of terminals along the sides of length "0" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrically connected. 5. The corner shape (square, noleh, radius, ele.) may vary at the manufacturer's option, from that shown on the drawing. 8. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 Inch solder thickness on pads. 17·36 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J44.B 44 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER INCHES E3 B L IT 1-. MIN MAX MIN MAX NOTES A 0.067 0.087 1.70 2.20 6,7 A1 0.058 0.072 1.47 1.83 7 B - - - - - Bl 0.022 0.028 0.565 0.705 2,4 B3 0.006 0.022 0.15 0.56 0 0.640 0.664 16.26 16.86 E l=---------'jJJ . 01 0.500BSC 02 0.250BSC 0.50 12.30 12.70 E 0.640 0.664 16.26 16.86 E2 11,...." PLANE1 e1 e h j -j L.rnvnvrM"1'i'1""M"1'1'n'~ . - ! E l l - - - - + ----E~ as i t 0.500BSC 12.70BSC 0.250BSC 0.484 I 6.35BSC 0.500 0.050BSC 0.015 12.7 I.27BSC - I 12.3 0.040 REF 0.020 REF - 0.38 - - 6.35BSC 0.484 E3 11 1~ ~ ~ ~ ~ ~ ~ 1 T 12.70BSC 03 El A1 A MILLIMETERS SYMBOL 2 2 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 0.614 1.4 Ll 0.045 0.055 0.614 1.4 L2 0.065 0.105 1.66 2.66 L3 0.003 0.015 0.08 0.38 - - NO 11 11 3 NE 11 11 3 N 44 44 3 NOTES: 1. Metallized castellations s!.all be connected to plane 1 terminals and extend toward plana 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.381 mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol"N" is the maximum number of terminals. Symbols "NO" and "NE" are the number of terminals along the sides of length "0" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrlcally connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 inch solder thickness on pads. 17-37 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J68.A 68 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER INCHES E3 B L IT MIN MAX MIN MAX NOTES A 0.067 0.087 1.70 2.20 6,7 Al 0.058 0.072 1.47 1.83 7 8 - - 81 0.033 0.039 B3 0.006 0.022 0 0.940 0.965 E k=-------'lJJ 01 02 M ,.-:r-+----+----f--E- t t - 20.328SC Q.400BSC 10.168SC E 0.940 0.965 23.88 24.51 el B3 0.56 24.51 16.05 e L/'tM'1Vr'M"'r~~ 0.15 23.88 15.65 J I 2,4 0.632 E3 :::jL..,f 0.99 0.616 E2 ~;: :. . J'TI:; : :~:; : :~; : : ;~:;: : r;~;: : ;:;:~=;:;:~ I~ ::: 0.800BSC 0.85 03 El A MILLIMETERS SYMBOL 0.8008SC 20.328SC Q.4008SC 0.616 I 10.168SC 0.632 0.050BSC 0.Q15 16.05 1.27BSC - I 15.65 - 0.38 0.040 Ref 1.00 Ref L 0.045 0.055 1.14 1.40 Ll 0.045 0.055 1.14 1.40 L2 0.075 0.095 1.91 2.41 L3 0.003 0.015 0.08 0.38 - - 2 - 2 2 5 - - NO 17 17 3 NE 17 17 3 N 68 68 3 NOTES: 1. Metallized castellalions shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 Inch (0.381 mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol""'" Is the maximum number of terminals. Symbols 'NO" and "HE' are the number of terminals along the sides of length '0' and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 Inch solder thickness on pads. 17-38 Package Outlines Metal Seal Leadless Ceramic Chip Carrier Packages (Continued) J6B.B J:f4I. --~---t +-"'T"" 68 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER INCHES 'T 8 L IT E3 MIN MAX MIN MAX NOTES A 0.092 0.118 2.34 3.00 6,7 Al 0.067 0.083 1.71 2.11 7 8 0.033 0.039 0.85 0.99 81 0.033 0.039 0.085 0.99 B3 0.006 0.022 0.15 0.56 0 0.940 0.960 23.88 24.38 E k=--------'lli 01 0.80085C 02 0.40085C I 0.705 17.65 I 17.91 E 0.940 I 0.960 23.88 124.38 E2 e el j t 10.168SC 0.695 E3 83 20.328SC 03 El t MILUMETERS SYMBOL 0.80085C 20.3285C 0.4OO85C 0.695 I 10.168SC 0.705 O.05085C 17.91 1.27BSC - 0.015 17.65 0.020 Ref - 0.38 0.51 Ref L 0.042 0.058 1.07 1.47 Ll 0.042 0.058 1.07 1.47 L2 0.080 0.090 2.03 2.29 L3 0.003 0.015 0.08 0.38 2 2 - 2,4 2 5 - NO 17 17 3 NE 17 17 3 N 68 68 3 NOTES: 1. Metallized caslellatlons shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 Inch (0.381 mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N° is the maximum number of terminals. Symbols "NO" and "NE" are the number of terminals along the sides 01 length "0" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be eliectrlcaHy connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed 01 a minimum of two ceramic layers. 7. Maximum IImlis allows for 0.007 Inch solder thickness on pads. 17-39 Package .Outlines Single-In-Llne Plastic Packages (SIP) Z3.05 3 LEAD PLASTIC SINGLE-IN·L1NE PACKAGE INCHES MIN MAX A 0.170 0.195 4.32 b 0.014 0.020 0.36 0.51 E 0.130 0.095 0.155 0.105 3.30 2.41 3.94 2.67 0.045 0.055 1.14 1.40 0.500 0.610 12.70 15.49 2.41 e e1 L a (2X) MILLIMETERS SYMBOL MIN MAX 4.95 R 0.085 0.095 2.16 S1 0.045 0.060 1.14 1.52 W 0.016 0.022 0.41 0.56 0 0.175 0.195 4.45 4.95 a 4° 6° 4° SO Rev. 0 12193 NOTES: 1. Package outline exclusive of any mold flashes dimension; 2. Package outline exclusive of Burr dimension. 17-40 Package Outlines Metal Can Packages T2.A 2 LEAD METAL CAN PACKAGE INCHES MIWMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.130 0.150 3.30 3.81 - b 0.016 0.019 0.41 0.48 0 0.205 0.22 5.21 5.59 01 F 0.180 0.010 0.190 0.025 4.57 0.25 4.63 0.64 k 0.033 0.046 0.64 1.17 j 0.033 0.045 0.84 1.14 L 0.500 0.560 12.70 14.22 NOTES: 1. Measured from mexlmum diameter of the actual device. 2. Measured from tab centerline. 3. N Is number of leads. - e el O.loo88C - - 1 - a 45 45 2 N 2 2 3 2.5488C T3.A 3 LEAD METAL CAN PACKAGE INCHES MILUMETERS SYMBOL MIN MAX MIN A 0.130 0.150 3.30 3.81 b 0.019 0.41 0.48 0 0.016 0.205 0.220 5.21 5.59 01 0.160 0.190 4.57 4.83 F 0.010 0.025 0.25 0.64 - k 0.033 0.048 0.84 1.22 1 j 0.036 0.046 0.91 1.17 L o.soo 0.560 12.70 14.22 NOTES: 1. Measured from maximum diameter of the actual device. 2. Measured from tab centerline. 3. N Is number of leads 17-41 MAX NOTES - - e O.loo88C 2.548SC el O.05088C 1.2788C a 45 45 2 N 3 3 3 Package Outlines Metal Can Packages (Continued) T10.8 MIL-STD-1835 MACY1·X10 (A2) 10 LEAD TO-100 METAL CAN e1 INCHES Q MILLIMETERS NOTES SYMBOL MIN MAX MIN MAX A 0~165 0.165 4.19 4.70 · 0b 0.016 0.019 0.41 0.48 1 0b1 0.016 0.021 0.41 0.53 1 0b2 0.016 0.024 0.41 0.61 · 00 0.335 0.375 6.51 9.52 001 0.305 0.335 7.75 8.51 002 0.110 0.160 2.79 4.06 BASE AND SEATING PLANE FINISH SECTIONA-A NOTES: 1. (All leads) 0b applies between L1 and L2. 0b1 applies between L2 and 0.500 from the reference plane. Diameter Is uncontroUed In L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product 3. als the basic spacing from the centerline of the tab to terrnlnal1 and ~ is the basic spacing of each lead or lead position (N -1 places) from a. looking at the bottom of the package. 4. N Is the maximum number of terminal positions. 5. Dimensioning and toleranclng per ANSI 414.5M -1982. 6. Controlling dimension: INCH. 17-42 e 0.23OBSC 5.64BSC e1 0.115 BSC 2.92B8O F . 0.040 . k 0.027 0.034 0.69 k1 0.027 0.045 L 0.500 0.750 L1 - 0.050 L2 0.250 - - Q 0.010 0.045 · · · · · 0.86 - 0.69 1.14 2 12.70 19.05 1 1.27 1 6.35 - 1 0.25 1.14 1.02 · a 36"B8O 36°BSC ~ 36"B8O 3SOBSC 3 N 10 10 4 3 DATA ACQUISITIO_ 18 HOW TO USE HARRIS AnswerFAX What is AnswerFAX? AnswerFAX is Harris' automated fax response system. It gives you on-demand access to a full library of the latest data sheets, application notes, and other information on Harris products . ••• What do I need to use AnswerFAX? Just a fax machine and a touch-tone phone. You can access it 24 hours a day, 7 days a week . ••• How does it work? You call the AnswerFAX number, touch-tone your way through a series of recorded questions, enter the order numbers of the documents you want, and give AnswerFAX a fax number to send them to. You'll have the information you need in minutes. The chart on the next page shows you how. ••• How do I find out the order number for the publications I want? The first time you call AnswerFAX, you should order one or more on-line catalogs of product line information. There are nine catalogs: • New Products • Digital Signal Processing (DSP) Products • Rad Hard Products • LinearfTelecom Products • Discrete & Intelligent Power Products • CMOS Logic Products • Data Acquisition Products • Microprocessor Products • Application Notes Once they're faxed to you, you can call back and order the publications themselves by number. ••• How do I start? Dial 407-724-7800. That's it. ANSWER FAX Please refer to next page for a map to AnswerFAX. 18-1 Your Map to Harris AnswerFAX m~~ ANSWER A complete AnswerFAX catalog listing is available, please call 1-800-442-7747 and request document BR-OS7 (84 pages) FIX: FAX IDENTIFIER ENTER A DOCUMENT NUMBER DOCUMENT fi1 ENTER YOUR NAME OR VOICE PHONE IABC NUMBER 2 L.:..J ORDER ORDER WELCOME TO AnswerFAXI CATALOG GET HELP NEW PRODUCTS ~ LINEAR AND TELECOM PRODUCTS ~ ~ DONE (UP TO THREE) ENTER YOUR CORRECT FAX NUMBER AND CONFIRM MORE DESCRIPTION OF AnswerFAX MORE[!J DATA ACQUISITION PRODUCTS QJ QJ QJ (A~C QJ [w:vJ ENTERS "Q" MICROPROCESSOR PRODUCTS + ) ENTERS "Z" RADIATION HARDENED PRODUCTS + ENTERS"&" [ ! J [ ! J BLANK SPACE r;;;l L.::.) G BACK-UP ONE CHARACTER HELP (ORDER UP TO THREE CATALOGS) 8 APPLICATION WXY 9 NOTES CHOOSE A CATALOG REFERENCE GUIDE FOR SPECIAL CHARACTERS AT LEFT OF PAGE [!JDONE -~~I:I PRODUCTS GETHELP """OK DISCRETE AND INTELLIGENT POWER PRODUCTS + EJ DONE0[!J DIGITAL SIGNAL PROCESSING SPECIAL CHARACTERS ENTER YOUR NAME -, ORDER SOMETHING ELSE CONFIRM I • ENTER YOUR VOICE PHONE NUMBER II # I DONE Harris AnswerFAX Data Book Request Form - Document #199 Data Books Available Now ./ PUB . NUMBER DATA BOOK/DESCRIPTION 7004 Complete Set of Commercial Harris Data Books 7005 Complete Set of Commercial and Military Harris Data Books DB223B POWER MOSFETs (1994: 1,328pp) This data book contains detailed technical information including standard power MOSFETs (the popular RF·series types, the IRF·series of industry replacement types, and JEDEC types), MegaFETs, logic· level power MOSFETs (L2FETs), ruggedized power MOSFETs, advanced discrete, high· reliability and radiation-hardened power MOSFETs. DB235B RADIATION HARDENED (1993: 2,232pp) Harris technologies used include dielectric isolation (DI), Silicon-on-Sapphire (50S), and Silicon-on-Insulator (501). The Harris radiation-hardened products include the CD4000, HCS/HCTS and ACS/ ACTS logic families, SRAMs, PROMs, op amps, analog multiplexers, the 80C85/80C86 microprocessor family, analog switches, gate arrays, standard cells and custom devices. DB260.2 CDP6805 CMOS MICROCONTROLLERS & PERIPHERALS (1995: 436pp) This data book represents the full line of Harris Semiconductor CDP6805 products for commercial applications and supersedes previously published CDP6805 data books under the Harris, GE, RCA or Intersil names. DB301B DATA ACQUISITION (1994: 1,104pp) Product specifications on AID converters (display, integrating, successive approximation, flash); D/A converters, switches, multiplexers, and other products. DB302B DIGITAL SIGNAL PROCESSING (1994: 528pp) Product specifications on one-dimensional and two-dimensional filters, signal synthesizers, multipliers, special function devices (such as address sequencers, binary correlators, histogrammer). DB303 MICROPROCESSOR PRODUCTS (1992: 1,156pp) For commercial and military applications. Product specifications on CMOS microprocessors, peripherals, data communications, and memory ICs. DB304.1 INTELLIGENT POWER ICs (1994: 946pp) This data book includes a complete set of data sheets for product specifications, application notes with design details for specific applications of Harris products, and a description of the Harris quality and high reliability program. DB309.1 MCTnGBT/DIODES (1995: 706pp) This MCTIIGBT/Diodes Databook represents the full line of these products made by Harris Semiconductor Discrete Power Products for commercial applications. DB314 SIGNAL PROCESSING NEW RELEASES (1995: 690pp) This data book represents the newest products made by Harris Semiconductor Data Acquisition Products, Linear Products, Telecom Products and Digital Signal Processing Products for commercial applications. DB450.4 TRANSIENT VOLTAGE SUPPRESSION DEVICES (1995: 400pp) Product specifications of Harris varistors and surgectors. Also, general informational chapters such as: "Voltage Transients - An Overview," "Transient Suppression - Devices and Principles," "Suppression - Automotive Transients." DB500B LINEAR AND TELECOM ICs (1993: 1,312pp) Product specifications for: op amps, comparators, S/H amps, differential amps, arrays, special analog circuits, telecom ICs, and power processing circuits. Digital Military DIGITAL MILITARY (1989: 680pp) Harris CMOS digital iCs - microprocessors, peripherals, data communications and memory - are included in this data book. Analog Military ANALOG MILITARY (1989: 1,264pp) This data book describes Harris' military line of Linear, Data Acquisition, and Telecommunications circuits. DB312 ANALOG MILITARY DATA BOOK SUPPLEMENT (1994: 432pp) The 1994 Military Data Book Supplement, combined with the 1989 Analog Military Product Data Book, contain detailed technical infonmation on the extensive line of Harris Semiconductor Linear and Data Acquisition products for Military (MIL-STD-883, DESC SMD and JAN) applications and supersedes all previously published Linear and Data Acquisition Military data books. For applications requiring Radiation Hardened products, please refer to the 1993 Harris Radiation Hardened Product Data Book (document #DB235B) PSG201.22 PRODUCT SELECTION GUIDE (1995: 816pp) Key product information on all Harris Semiconductor devices. Sectioned (Linear, Data Acquisition, Digital Signal Processing, Telecom, Intelligent Power, Discrete Power, Digital Microprocessors and Hi-ReI/Military and Rad Hard) for easy use and includes cross references and alphanumeric part number index. SG103 CMOS LOGIC SELECTION GUIDE (1994: 288pp) This product selection guide contains technical information on Harris Semiconductor High Speed 54174 CMOS Logic Integrated Circuits for commercial, industrial and military applications. It covers Harris' High Speed CMOS Logic HC/HCT Series, AC/ACT Series, BiCMOS Interface Logic FCT Series and CMOS Logic CD4000B Series. NAME: __________________________________________ PHONE: _____________________________ MAIL STOP: _____________________________________ FAX: _________________________________ COMPAN~ ___________________________________________________________________________ ADDRESS: ___________________________________________________________________________ LITERATURE REQUESTS SHOULD BE DIRECTED TO: HARRIS FULFILLMENT 18-3 FAX #: 610-265-2520 m AnswerFAX Technical Support . Application Note Listing HARRIS SEMICONDUCTOR AnswerFAX DOCUMENT NUMBER PART NUMBER 27007 BR007 Complete Listing of Harris Sales Offices, Representatives and Authorized Distributors World Wide (7 pages) 9001 ANOO1 Glossary of Data Conv~rslon Terms (6 pages) 9002 AN002 9004 AnswerFAX DOCUMENT NUMBER PART NUMBER 9049 AN049 Applying the 7109 AID Converter (5 pages) 9051 AN051 Principles and Applications of the ICL7660 CMOS Voltage Converter (9 pages) Principles of Data Acquisition and Conversion (20 pages) 9052 AN052 Tips for Using Single Chip 3.5 Digit AID Converters (9 pages) AN004 The IH5009 Analog Switch Series (9 pages) 9053 AN053 9007 AN007 Using the 804818049 Log/Antilog Amplifier (6 pages) The ICL7650 A New Era In GlitCh-Free Chopper Stabilized Amplifiers (19 pages) 9054 AN054 9009 ANOO9 Pick Sample-Holds by Accuracy and Speed and Keep Hold Capacitors in Mind (7 pages) Display Driver Family Combines Convenience of Use with Microprocessor Interfaceability (18 pages) 9059 AN059 9012 AN012 Switching Signals with Semiconductors (4 pages) Digital Panel Meter Experiments for the Hobbyist (7 pages) 9108 AN108 82C52 Programmable UART (12 pages) 9109 AN109 82C59A Priority Interrupt Controller (14 pages) 9111 AN111 Harris 80C286 Performance Advantages Over the 80386 (12 pages) 9112 ANl12 80C286180386 Hardware Comparison (4 pages) 9113 ANl13 Some Applications of Digital Signal Processing Techniques to Digital Video (5 pages) 9114 ANl14 Real-Time Two-Dimensional Spatial Rlterlng with the Harris Digital Riter Family (43 pages) . 9115 ANl15 Digital Filter (OF) Family Overview (6 pages) 9116 ANl16 Extended OF Configurations (10 pages) 9120 AN120 InterfaCing the 80C286-16 With the 80287-10 (2 pages) DESCRIPTION 9013 AN013 Everything You Always Wanted to Know About the ICL8038 (4 pages) 9016 AN016 Selecting AID Converters (7 pages) 9017 AN017 The Integrating AID Converter (5 pages) 9018 AN018 Do's and Don'ts of Applying AID Converters (4 pages) 9020 AN020 A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing (23 pages) 9023 AN023 Low Cost Digital Panel Meter Designs (5 pages) 9027 AN027 Power Supply Design Using the ICL8211 and 8212 (8 pages) 9028 AN028 Build an Auto-Ranging DMM with the ICL7103A18052A AID Converter Pair (6 pages) DESCRIPTION 9030 AN030 ICL7104: A Binary Output AID Converterfor Microprocessors (16 pages) 9121 AN121 9032 AN032 Understanding the Auto-Zero and Common Mode Performance of the ICL71 06171 07171 09 Family (8 pages) Harris 80C286 Performance AdVantages Over the 80386SX (14 pages) 9400 AN40ci Using the HS-3282 ARINC Bus Interface Circuit (6 pages) 9040 AN040 Using the ICL8013 Four Quadrant Analog Multiplier (6 pages) 9509 AN509 A Simple Comparator Using the HA-2620 (1 page) 9042 AN042 Interpretation of Data Converter Accuracy Specifications (11 pages) 9514 AN514 The HA-2400 PRAM Four Channel Operational Amplifier (7 pages) 9043 AN043 Video Analog-to-Digital Conversion (6 pages) 9515 AN515 Operational Amplifier Stability: Input CapaCitance Considerations (2 pages) 9046 AN046 Building a Battery Operated Auto Ranging DVM with the ICL7106 (5 pages) 9517 AN517 Applications of Monolithic Sample and Hold Amplifier (5 pages) 9047 AN047 Games People Play with Intersli's AID Converter's (27 pages) 9519 AN519 Operational Amplifier Noise Prediction (4 pages) 9048 AN048 Know Your Converter Codes (5 pages) 18-4 AnswerFAX Technical Support Application Note Listing II HARRIS SEMICONDUCTOR AnswerFAX DOCUMENT NUMBER PART NUMBER AnswerFAX DOCUMENT NUMBER PART NUMBER 9520 AN520 CMOS Analog Miltiplexers and Switches; Applications Considerations (9 pages) 9556 AN556 Thermal Safe-Operating-Areas for High Current Op Amps (5 pages) 9521 AN521 Getting the Most Out of CMOS Devices for Analog Switching Jobs (7 pages) 9557 AN557 Recommended Test Procedures for Analog Switches (6 pages) 9522 AN522 Digital to Analog Converter Terminology (3 pages) 9558 AN558 Using the HV-1205 AC to DC Converter (2 pages) 9524 AN524 Digital to Analog Converter High Speed ADC Applications (3 pages) 9559 AN559 HI-222 VldeolHF Switch Optimizes Key Parameters (7 pages) 9525 AN525 HA-5190/5195 Fast Settling Operational Amplifier (4 pages) 9571 AN571 Using Ring Sync with HC-5502A and HC-5504 SLiCs (2 pages) 9526 AN526 Video Applications for the HA-5190/ 5195 (5 pages) 9573 AN573 The HC-5560 Digital Line Transcoder (6 pages) 9531 AN531 Analog Switch Applications in AID Data Conversion Systems (4 pages) 9574 AN574 Understanding PCM Coding (3 pages) 9576 AN576 HC-5512 PCM Filter Cleans Up CVSD Codec Signals (2 pages) 9532 AN532 Common Questions Concerning CMOS Analog Switches (4 pages) 9607 AN607 Delta Modulation for Voice Transmission (5 pages) 9534 AN534 Additional Information on the HI-300 Series Switch (5 pages) 95290 AN5290 Integrated Circuit Operational Amplifiers (20 pages) 9535 AN535 Design Considerations for A Data Acquisition System (DAS) (7 pages) 96048 AN6048 Some Applications of A Programmable Power Switch/Amp (12 pages) 9538 AN538 Monolithic SampleiHold Combines Speed and Precision (6 pages) 96077 AN6077 9539 AN539 A Monolithic 16-611 D/A Converter (5 pages) An IC Operational-TransconductanceAmplifier (OTA) With Power Capability (12 pages) 96157 AN6157 9540 AN540 HA-5170 Precision Low Noise JFET Input Operation Amplifier (4 pages) Applications of the CA3085 Series Monolithic IC Voltage Regulators (11 pages) 9541 AN541 Using HA-2539 or HA-2540 Very High Slew Rate. Wideband Operational Amplifier (4 pages) 96182 AN6182 9543 AN543 New High Speed Switch Offers Sub-50ns Switching TImes (7 pages) Features and Applications of Integrated Circuit Zero-Voltage Switches (CA3058. CA3059 and CA3079) (31 pages) 96386 AN6386 9544 AN544 Micropower Op Amp Family (6 pages) Understanding and Using the CA3130. CA3130A and CA3130B30Al30B BiMOS Operation Amplifiers (5 pages) 9546 AN546 A Method of Calculating HA-2625 Gain Bandwidth Product vs. Temperature (4 pages) 96459 AN6459 Why Use the CMOS Operational Amplifiers and How to Use it (4 pages) 9548 AN548 A Designers Guide for the HA-5033 Video Buffer (12 pages) 96565 AN6565 Design of Clock Generators For Use With COSMAC Microprocessor CDP1802 (3 pages) 9549 AN549 The HC-550X Telephone Subscriber Une Interface Circuits (SLlC) (19 pages) 96669 AN6669 FET-Bipolar Monolithic Op Amps Mate Directly to Sensitive Sources (3 pages) 9550 AN550 Using the HA-2541(6 pages) 96915 AN6915 Application of CA 1524 Series Pulse-Width Modulator ICs (18 pages) 9551 AN551 Recommended Test Procedures for Operational Amplifiers (6 pages) 96970 AN6970 Understanding and Using the CDP1855 Multiply/Divide Unit (11 pages) (I):f 97063 AN7063 Understanding the CDP1851 Programmable VO (7 pages) l:z DESCRIPTION 9552 AN552 Using the HA-2542 (5 pages) 9553 AN553 HA-5147137/27. Ultra Low Noise Amplifiers (8 pages) 9554 AN554 Low Noise Family HA-5101/02l04l11/12114 (7 pages) 97174 18-5 AN7174 DESCRIPTION The CA 1524E Pulse-Width ModulatorDriver for an Electronic Scale (2 pages) >< -a: a: w a:~ cC(I) cC AnswerFAX Technical· Support Application Note Listing AnswerFAX DOCUMENT NUMBER PART NUMBER 97244 AN7244 Understanding Power MOSFETs (4 pages) 97254 AN7254 Switching Waveforms of the L2FET: A 5 Volt Gate-Drive Power MOSFET (8 pages) DESCRIPTION AnswerFAX DOCUMENT NUMBER PART NUMBER 98823 AN8823 CMOS Phase-Locked-Loop Applications Using the CD54174HCJHCT4046A and CD54174HCIHCT7046A (23 pages) 98829 ANBB29 SP600 and SP601 an HVIC MOSFET/ IGBT Driver for Half-Bridge Topologies (6 pages) 98910 ANB910 An IntroductIon to Behavioral Simulation Using Harris Ac/ACT Logic SmartModels™ From Logic Automation Inc. (9 pages) 99001 AN9001 Measuring Ground and VCC Bounce In Advanced High Speed (Ac/ACT/FCn CMOS Logic ICs (4 pages) DESCRIPTION 97260 AN7260 Power MOSFET Switching Waveforms: A New Insight (7 pages) 97275 AN7275 User's Guide to the CDP1 B79 and CDP1879C1 CMOS Real-Time Clocks (1B pages) 97326 AN7326 Applications of the CA3228E Speed Control System (16 pages) 97332 AN7332 The Application of Conductivity-Modulated Field-Effect Transistors (5 pages) 99002 AN9002 Transient Voltage Suppression in Automotive Vehicles (B pages) 97374 AN7374 The CDP1871A Keyboard Encoder (9 pages) 99003 AN9003 98602 ANB602 The IGBTs - A New High Conductance MOS:Gated Device (3 pages) Low-Voltage Metal-Oxlde VaristorProtection for Low Voltage (:S:5V) ICs (13 pages) 99010 AN9010 98603 ANB603 Improved IGBTs with Fast Switching Speed and High-Current Capability (4 pages) HIP2500 High Voltage (500Vocl HalfBridge Driver IC (B pages) 99011 AN9011 Synchronous Operation of Harris Rad Hard SOS 64K Asynchronous SRAMs (4 pages) 99101 AN9101 High Current Off Line Power Supply (4 pages) 99102 AN91 02 Noise Aspects of Applying Advanced CMOS Semiconductors (9 pages) 99105 AN91 05 HVIC/IGBT Half-Bridge Converter Evaluation Circuit (1 page) 99106 AN9106 Special ESD Considerations for the HS65643RH and HS-65647RH Radiation Hardened SOS SRAMs (2 pages) 99108 AN9108 Harris Multilayer Surface Mount Surge Suppressors (10 pages) 99201 AN9201 Protection Circuits for Quad and Octal Low Side Power Drivers (8 pages) 99202 AN9202 Using the HFA1100. HFA1130 Evaluation Fixture (4 pages) 99203 AN9203 Using the HI5800 Evaluation Board (13 pages) 99204 AN9204 Tools for Controlling Voltage Surges and Noise (4 pages) 99205 AN9205 liming Relationships for HSP45240 (2 pages) 99206 AN9206 Correlating on Extended Data Lengths (2 pages) 99207 AN9207 DSP Temperature Considerations (2 pages) 99208 AN9208 High Frequency Power Converters (10 pages) 98610 AN861 0 Spicing-Up Spice II Software for Power MOSFET Modeling (8 pages) 98614 AN8614 The CA1523 Variable Interval Pulse Regulator (VI PUR) For Switch Mode Power Supplies (13 pages) 98707 AN8707 The CA3450: A Single-Chip Video Line Driver and High Speed Op Amp (14 pages) 98742 ANB742 Application of the CD22402 Video Sync Generator (4 pages) 98743 AN8743 Micropower Crystal-Controlled Oscillator Design USing CMOS Inverters (8 pages) ·98754 ANB754 Method of Measurement of Simultaneous Switching Transient (3 pages) 98756 AN8756 A Comparative Description of the UART (16 pages) 98759 AN8759 Low Cost Data Acquisition System Features SPI AID Converter (9 pages) 98761 AN8761 User's Guide to the CDP6BHC6BT1 Real-Time Clock (14 pages) 98811 ANB811 BIMOS-E Process Enhances the CA5470 Quad Op Amp (8 pages) 98618 AN8B18 Exceptional Radiation Levels from Sillcon-on-Sapphire Processed HighSpeed CMOS Logic (5 pages) 98820 AN8820 Recommendations for Soldering Terminal Leads to MOV Varistor Discs (2 pages) AnswerFAX Technical Support Application Note Listing AnswerFAX DOCUMENT NUMBER PART NUMBER A Splce-2 Subcircult Representation for Power MOSFETs, Using Empirical Methods (4 pages) 99316 AN9316 Power Supply Considerations for the HI-222 High Frequency Video SWitch (2 pages) AN921 0 A New PSplce Subcircult for the Power MOSFET Featuring Global Temperature Options (12 pages) 99317 AN9317 Micropower Clock Oscillator and Op Amps Provide System Control for Battery Operated Circuits (2 pages) AN9211 Soldering Recommendations for Surface Mount Metal Oxide Varistors and Multilayer Transient Voltage Suppressors (8 pages) 99321 AN9321 Single Pulse Unclamped Inductive Switching: A Rating System (5 pages) 99322 AN9322 A Combined Single Pulse and Repetitive UIS Rating System (4 pages) 99323 AN9323 HIP5061 High Efficiency, High Performance, High Power Converter (10 pages) AnswerFAX DOCUMENT NUMBER PART NUMBER 99209 AN9209 99210 99211 DESCRIPTION DESCRIPTION 99212 AN9212 HIP5060 Family of Current Mode Control ICs Enhance 1MHz Regulator Performance (7 pages) 99213 AN9213 Advantages and Application of Display Integrating AID Converters (6 pages) 99327 AN9327 HC-5509A1 Ring Trip Component Selection (9 pages) 99214 AN9214 Using Harris High Speed AID Converters (10 pages) 99328 AN9328 Using the HI1166 Evaluation Board (9 pages) 99215 AN9215 Using the HI-5700 Evaluaton Board (7 pages) 99329 AN9329 Using the H111761H11171 Evaluation Board (5 pages) 99216 AN9216 Using the HI5701 Evaluation Board (8 pages) 99330 AN9330 Using the HI1396 Evaluation Board (9 pages) 99217 AN9217 High Current Off Line Power Supply (11 pages) 99331 AN9331 Using the HI1175 Evaluation Board (4 pages) 99301 AN9301 High Current Logic Level MOSFET Driver (3 pages) 99332 AN9332 Using the HI1276 Evall!ation Board (10 pages) 99302 AN9302 CA3277 Dual 5V Regulator Circuit Applications (9 pages) 99333 AN9333 Using the H11386 Adapter Board (2 pages) 99303 AN9303 Upgrading Your Application to the HI7166 or HI7167 (7 pages) 99334 AN9334 99304 AN9304 ESD and Transient Protection Using the SP720 (5 pages) Improving Start-Up Time at 32kHz for the HA7210 Low Power Crystal Oscillator (2 pages) 99337 AN9337 99306 AN9306 The New 'C' III Series of Metal Oxide Varistors (5 pages) Reduce CMOS-Multiplexer Troubles Through Proper Device Selection (6 pages) 99307 AN9307 The Connector Pin Varistor for Transient Voltage Protection in Connectors (7 pages) 660001 MMOO01 HFA-0001 Spice Operational Amplifier Macro-Model (4 pages) 660002 MMOOO2 99309 AN9309 Using the HI5800lH15801 Evaluation Board (8 pages) HFA-0Q02 Spice Operational Amplifier Macro-Model (4 pages) 660005 MMOOO5 99310 AN931 0 Voltage Transients and their Suppression (5 pages) HFA-0005 Spice Operational Amplifier Marco-Model (4 pages) 662500 MM2500 99311 AN9311 The ABCs of MOVs (3 pages) HA2500102 Spice Operational Amplifier Macro-Model (5 pages) 99312 AN9312 Suppression of Transients in an Automative Environment (11 pages) 662510 MM251 0 HA-251 0112 Spice Operational Amplifier Macro-Model (4 pages) 99313 AN9313 Circuit Considerations in Imaging Applications (8 pages) 662520 MM2520 HA-2520122 Spice Operational Amplifier Macro-Model (4 pages) 662539 99314 AN9314 Harris UHF Pin Drivers (4 pages) 99315 AN9315 RF Amplifier Design USing HFA30461 3096/3127/3128 Transistor Arrays (4 pages) 662540 18-7 MM2539 MM2540 HA-2539 Spice Operational Amplifier Macro-Model (4 pages) HA-2540 Spice Operational Amplifier Macro-Model (4 pages) II (I)~ -0: O:w o:~ cC(I) ::C z cC '--- mHARRls· W AnswerFAX Technical Support Application Note Listing SEMICO.NDU.CTOR AnswerFAX DOCUMENT NUMBER PART NUMBER AnswerFAX DOCUMENT NUMBER PART NUMBER 662541 MM2541 HA-2541 Spice Operational Amplifier Macro-Model (5 pages) 665020 MM5020 HA-2542 Spice Operational Amplifier Macro-Model (5 pages) HA-5020 Spice Current Feedback Operational Amplifier Macro-Model (4 pages) 662542 MM2542 662544 665033 MM5033 MM2544 HA-2544 Spice Operational Amplifier Macro-Model (5 pages) HA-5033 Spice Buffer Amplifier Macro-Model (4 pages) 665101 MM5101 662548 MM2548 HA-2548 Spice Operational Amplifier Macro-Model (5 pages) HA-5101 Spice Operational Amplifier Macro-Model (5 pages) 665102 MM51 02 662600 MM2600 HA-2600/02 Spice Operational Amplifier Macro-Model (5 pages) HA-5102 Spice Operational Amplifier Macro-Model (5 pages) 665104 MM5104 662620 MM2620 HA-2620122 Spice Operational Amplifier Macro-Model (5 pages) HA-5104 Spice Operational Amplifier Macro-Model (5 pages) 665112 MM5112 662839 MM2839 HA-2839 Spice Operational Amplifier Macro-Model (4 pages) HA-5112 Spice Operational Amplifier Macro-Model (5 pages) 665114 MM5114 662840 MM2840 HA-2840 Spice Operational Amplifier Macro-Model (4 pages) HA-5114 Spice Operational Amplifier Macro-Model (5 pages) 665127 MM5127 662841 MM2841 HA-2841 Spice Operational Amplifier Macro-Model (4 pages) HA-5127 Spice Operational Amplifier Macro-Model (4 pages) 665137 MM5137 662842 MM2842 HA-2842 Spice Operational Amplifier Macro-Model (4 pages) HA-5137 Spice Operational Amplifier Macro-Model (4 pages) 665147 MM5147 662850 MM2850 HA-2850 Spice Operational Amplifier Macro-Model (4 pages) HA-5147 Spice Operational Amplifier Macro-Model (4 pages) 665190 MM5190 665002 MM5002 HA-5002 Spice Buffer Amplifier Macro-Model (4 pages) HA-5190 Spice Operational Amplifier Macro-Model (4 pages) 665221 MM5221 665004 MM5004 HA-5004 Spice Current Feedback Amplifier Macro-Model (4 pages) HA-5221122 Spice Operational Amplifier Macro-Model (4 pages) 797338 MM Harris Power MOSFET and MCT Spice PWRDEV Model Library (16 pages) DESCRIPTION 18-8 DESCRIPTION DATA ACQUISITIO_ 19 SALES OFFICES A complete and current listing of all Harris Sales, Representative and Distributor locations worldwide is available. Please order the "Harris Sales Listing" from the Literature Center (see page i). HARRIS HEADQUARTER LOCATIONS BY COUNTRY: U.S. HEADQUARTERS Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 ASIA EUROPEAN HEADQUARTERS Harris Semiconductor PTE Ltd. No. 1 Tannery Road Cencon 1, #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400 Harris Semiconductor Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: 32272421 11 TECHNICAL ASSISTANCE IS AVAILABLE FROM THE FOLLOWING SALES OFFICES UNITED STATES INTERNATIONAL CALIFORNIA Calabasas ......................... 818-878-7955 Costa Mesa ........................ 714-433-0600 San Jose .......................... 408-985-7322 FLORIDA Palm Bay .......................... 407-729-4984 GEORGIA Duluth ............................. 404-476-2035 ILLINOIS Schaumburg ........................ 708-240-3480 INDIANA Carmel ............................ 317-843-5180 MASSACHUSETTS Burlington .......................... 617-221-1850 NEW JERSEY Voorhees .......................... 609-751-3425 NEW YORK Hauppauge ......................... 516-342-0291 Wappingers Falls .................... 914-298-1920 TEXAS Dallas ............................. 214-733-0800 FRANCE Paris ............................ 33-1-346-54046 GERMANY Munich ........................... 49-89-63813-0 HONG KONG Kowloon ........................... 852-723-6339 ITALY Milano ......................•..... 39-2-262-0761 JAPAN Tokyo ........................... 81-3-3265-7571 KOREA Seoul ...................... " .... 82-2-551-0931 SINGAPORE Singapore ........................... 65-748-4200 TAIWAN Taipei ........................... 886-2-716-9310 UNITED KINGDOM Camberley ....................... 44-1276-686886 For literature requests, please contact Harris at 1-800-442-7747 (1-800-4HARRIS) or call Harris AnswerFAX for immediate fax service at 407-724-7800 19-1 North American Sales 0"'"IceS an d Representatives Clark Hurman Associates Un~ 14 20 Regan Road Brampton, Ontario Canada L7A IC3 TEL: '(905) 840-6066 FAX: 905 840-6091 ALABAMA Harris Semiconductor 600 Boulevard South Suite 103 Huntsville, AL 35802 TEL: (205) 883-2791 FAX: 205 883 2861 308 Palladium Drive Suite 200 Kanata, Ontario Canada K2B lA1 TEL: (613) 599-5626 FAX: 613 599 5707 Giesting & Associates Su~e 15 4835 University Square Huntsville, AL 35816 TEL: (205) 830-4554 FAX: 205 830 4699 ARIZONA Compa$s Mktg. & Sales, Inc. 11801 N. Tatum Blvd. #101 Phoenix, AZ 85028 TEL: (602) 996-0635 FAX: 602 996 0586 2410 W. Ruthrauff, Rd. #110 Tucson, AZ 85705 TEL: (520) 292-0222 FAX: 520 2921008 CALIFORNIA Harris Semiconductor • 1503 So. Coast Drive Suite 320 Costa Mesa, CA 92626 TEL: (714) 433-0600 FAX: 714 433 0682 Harris Sem iconductor • 3031 Tisch Way 1 Plaza South San Jose, CA 95128 TEL: (408) 985-7322 FAX: 4089857455 CK Associates 8333 Clairemont Mesa Blvd. Suite 102 San Diego, CA 92111 TEL: (619) 279-0420 FAX:619 279 7650 GEORGIA Giesting & Associates • 2434 Hwy. 120,Suite 108 Duluth, GA 30136 TEL: (404) 476-0025 FAX: 404476 2405 ILLINOIS Harris Sem iconductor '1101 Perimeter Dr., Suite 600 Schaumburg, IL 60173 TEL: (708) 240-3480 FAX: 708 6191511 78 Donegani, Suite 200 Pointe Claire, QUl;lbec Canada H9R 2V4 TEL: (514) 426-0453 FAX: 5144260455 Oasis Sales 1101 Tonne Road Elk Grove Village, IL 60007 TEL: (708) 640-1850 FAX: 708 640 9432 COLORADO Compass Mktg. & Sales, Inc. 5600 So. Quebec 51. Suite 350D Greenwood Village, CO 80111 TEL: (303) 721-9663 FAX: 303 721 0195 Giesting & Associates 370 Ridgepoint Dr. Carmel, IN 46032 TEL: (317) 844-5222 FAX: 317 844 5861 CONNECTICUT Advanced Tech. Sales, Inc. WeStview Office Park . Bldg. 2, Suite lC 850 N. Main Street ExtenSion Wallingford, CT 06492 TEL: (508) 664-0888 FAX: 203 284 8232 IOWA Oasis Sales 4905 Lakeside Dr., NE Suite 203 Cedar Rapids, IA 52402 TEL: (319) 377-8738 FAX: 319377 8803 FLORIDA Harris Semiconductor • 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (407) 729-4984 FAX: 407 729 5321 Ewing Foley, Inc. 185 Linden Avenue Auburn, CA 95603 TEL: (916) 885-6591 FAX: 916 885 6594 Ewing Foley, Inc. 10495 Bandley Avenue Cupertino, CA 95014-1972 TEL: (408) 342-1200 FAX: 408 342 1201 Vision Technical Sales, Inc. • 26010 Mureau Road Suite 140 Calabasas, CA 91302 TEL: (818) 878-7955 FAX: 818 878 7965 CANADA Blakewood Electronic Systems, Inc. #201 - 7382 Winston Street Burnaby, BC Canada V5A 2G9 TEL: (604) 444-3344 FAX: 604 444 3303 INDIANA Harris Semiconductor • 11590 N. Meridian 51. Suite 100 Carmel, IN 46032 TEL: (317) 843-5180 FAX: 317843 5191 KANSAS Advanced Tech. Sales, Inc. 601 North Mur-Len, Suite 8 Olathe, KS 66062 TEL: (913) 782-8702 FAX: 913 7828641 Sun Marketing Group 1956 Dairy Rd. West Melbourne, FL 32904 TEL: (407) 723-0501 FAX: 407 723 3845 Sun Marketing Group 905 No~ern Dancer Way #107 Casselberry, FL 32707 TEL: (407) 699-3036 FAX: 407 699 3075 Sun Marketing Group 4175 East Bay Drive, Su~e 128 Clearwater, FL 34624 TEL: (813) 536-5771 FAX: 813 536 6933 Sun Marketing Group 600 S. Federal Hwy., Suite 218 Deerfield Beach, FL 33441 TEL: (305) 429-1077 FAX: 305 429 0019 KENTUCKY Glestlng & Associates 204 Pintail Court P.O. Box 909 Versailles, KY 40383 TEL: (606) 873-2330 FAX: 606 873 6233 MARYLAND New Era Sales, Inc. 890 Airport Pk. Rd, Suite 103 Glen Burnie, MD 21061 TEl: (410) 761-4100 FAX: 410761-2981 MASSACHUSETTS Harris Semiconductor • Six New England Executive Pk. Burlington, MA 01803 TEL: (617) 221-1850 FAX: 617 2211866 • Field Application Assistance Available 19-2 August 14, 1995 Advanced Tech Sales, Inc. 348 Park Street, Suite 102 Pari< Place West N. Readihg, MA 01864 TEL: (508) 664-0888 FAX: 508 664 5503 MICHIGAN Harris Semiconductor • 27777 Franklin Rd., Suite 460 Southfield, MI 48034 TEL: (810) 746-0800 FAX: 810 746 0516 Glestlng & Associates 34441 EightMileRd.,Su~el13 Livonia, MI 48152 TEL: (810) 478-8106 FAX: 810 477 6908 MINNESOTA Oasis Sales 7805 Telegraph Road Suite 210 Bloomington, MN 55438 TEL: (612) 941-1917 FAX: 612 941 5701 MISSOURI Advanced Tech. Sales 13755 St. Cha~es Rock Rd. Bridgeton, MO 63044 TEL: (314) 291-5003 FAX: 314291 7958 NEBRASKA Advanced Tech. Sales, Inc. 601 North Mur-Len, Su~e 8 Olathe, KS 66062 TEL: (913) 782-8702 FAX: 913 782 8641 NEW JERSEY Harris Semiconductor • Plaza 1000 at Main Street Suite 104 Voorhees, NJ 08043 TEL: (609) 751-3425 FAX: 609 751 5911 Harris Semiconductor 724 Route 202 P.O. Box 591 SomelVille, NJ 08876 TEL: (908) 685-6150 FAX: 908 685-6140 Tritek Sales, Inc. One Mall Dr., Suite 410 Cherry Hill, NJ 08002 TEL: (609) 667-0200 FAX: 6096678741 NEW MEXICO Compass Mktg. & Sales, Inc. 4100 Osuna Rd., NE, Sune 109 Albuquerque, NM 87109 TEL: (505) 344-9990 FAX: 5053454848 North American Sales Offices and Representatives (Continued) NEW YORK Harris Semiconductor Hampton Business Center 1611 Rt. 9, Suite U3 Wappingers Falls, NY 12590 TEL: (914) 298·0413 FAX: 914 298 0425 Harris Semiconductor • 490 Wheeler Rd, Suite 165B Hauppauge, NY 11788·4365 TEL: (516) 342·0291 Analog TEL: (516) 342·0292 Digital FAX: 516 342 0295 Foster & Wager, Inc. 300 Main Street Vestal, NY 13850 TEL: (607) 748·5963 FAX: 607 748 5965 Foster & Wager, Inc. 2511 Browncroft Blvd. Rochester, NY 14625 TEL: (716) 385·7744 FAX: 716 586 1359 Foster & Wager, Inc. 7696 Mountain Ash Liverpool, NY 13090 TEL: (315) 457·7954 FAX: 3154577076 Trlonlc Associates, Inc. 320 Northern Blvd. Great Neck, NY 11021 TEL: (516) 466·2300 FAX: 5164662319 NORTH CAROLINA Harris Semiconductor 4020 Stirrup Creek Dr. Building 2A, MS/2T08 Durham, NC 27703 TEL: (919) 405·3600 FAX: 9194053660 New Era Sales 1215 Jones Franklin Road Suite 201 Raleigh, NC 27606 TEL: (919) 859·4400 FAX: 919 859 6167 OHIO Giesting & Associates P.O. Box 39398 2854 Blue Rock Rd. Cincinnati, OH 45239 TEL: (513) 385·1105 FAX: 5133855069 6324 Tamworth Ct. Columbus·, OH 43017 TEL: (614) 792·5900 FAX: 6147926601 6200 SOM Center Rd. SuiteD·20 Solon, OH 44139 TEL: (216) 498·4644 FAX: 216 498 4554 OKLAHOMA Nova Marketing 8421 East 61st Street, Suite P Tulsa, OK 74133·1928 TEL: (800) 826·8557 TEL: (918) 660·5105 FAX: 918 3571091 OREGON Northwest Marketing Assoc. 6975 SW Sandburg Rd. Su~e 330 Portland, OR 97223 TEL: (503) 620·0441 FAX: 503 684 2541 August 14, 1995 Nova Marketing 8310 Capitol of Texas Hwy. Suite 180 Austin, TX 78731 TEL: (512) 343·2321 FAX: 512 343·2487 8350 Meadow Rd., Suite 174 Dallas, TX 75231 TEL: (214) 265·4600 FAX: 2142654668 Corporate Atrium II, Suite 140 10701 Corporate Dr. Stafford, TX 77477 TEL: (713) 240·6082 FAX: 713 240 6094 PENNSYLVANIA Giesting & Associates 471 Walnut Street Pittsburgh, PA 15238 TEL: (412) 828·3553 FAX: 412 828 6160 UTAH Compass Mktg. & Sales, Inc. 5 Triad Center, Su~e 320 Salt Lake City, UT 84180 TEL: (801) 322·0391 FAX: 801 322·0392 TEXAS Harris Semiconductor • 17000 Dallas Parkway, Su~e 205 Dallas, TX 75248 TEL: (214) 733·0800 FAX: 2147330819 WASHINGTON Northwest Marketing Assoc. 12835 Bel·Red Road SuHe 330N Bellevue, WA 98005 TEL: (206) 455·5846 FAX: 206 451 1130 WISCONSIN Oasis Sales 1305 N. Barker Rd. Brookfield, WI 53005 TEL: (414) 782·6660 FAX: 4147827921 North American Authorized Distributors and Corporate Offices Hamilton Hallmark and Zeus are the only authorized North American distributors for stocking and sale of Harris Red Hard Space products. Alliance Electronics 7550 E. Redfield Rd. Scottsdale, AZ 85260 TEL: (602) 483·9400 FAX: (602) 443 3898 Allied Electronics 7410 Pebble Dr. Ft. Worth, TX 76118 TEL: (800) 433·5700 Arrow/schweber Electronics 25 Hub Dr. Melville, NY 11747 TEL: (800) 777·2776 Electronics Marketing Corporation (EMC) 1150 West Third Avenue Columbus, OH 43212 TEL: (614) 299-4161 FAX: 614 299 4121 Hamilton Hallmark 10950 W. Washington Blvd. Culver City, CA 90230 TEL: (800) 332·8638 Newark Electronics 4801 N. Ravenswood Chicago, IL 60640 TEL: (312) 784·5100 FAX: 312275·9596 Farnell Electronic Services 300 North Riverrnede Rd. Concord, Ontario Canada L4K 3N6 TEL: (416) 798·4884 FAX: 416 798 4889 Wyle Electronics (Commercial Products) 3000 Bowers Avenue Santa Clara, CA 95051 TEL: (800) 414·4144 FAX: 801226·0210 Gerber Electron ics 128 Carnegie Row Norwood, MA 02062 TEL: (617) 769·6000, xl56 FAX: 617 762 8931 • Field Application Assistance Available 19·3 Zeus Electronics, An Arrow Company 100 Midland Avenue Pt. Chester, NY 10573 TEL: (800) 524·4735 Obsolete Products: Rochester Electronics 10 Malcom Hoyt Drive NeWburyport, MA 01950 TEL: (508) 462·9332 FAX: 508 462 9512 North American Authorized Distributors (Continued) ALABAMA ArrowfSchweber Huntsville TEL: (205) 837-6955 Hamilton Hallmark Huntsville TEL: (205) 837-8700 Wyle Electronics Huntsville TEL: (205) 830-1119 Zeus, An Arrow Company Huntsville TEL: (407) 333-3055 TEL: (800) 52-HI-REL ARIZONA Alliance Electronics, Inc. Scottsdale TEL: (602) 483-9400 Arrow/Schweber Tempe TEL: (602) 431-0030 Hamilton Hallmark Phoenix TEL: (602) 437 -1200 Wyle Electronics Phoenix TEL: (602) 804-7000 Zeus, An Arrow Company Tempe TEL: (408) 629-4789 TEL: (800) 52-HI-REL CALIFORNIA Arrow/Schweber Calabasas TEL: (818) 880-9686 Fremont TEL: (408) 432-7171 Irvine TEL: (714) 587-0404 San Diego TEL: (619) 565-4800 San Jose TEL: (408) 441-9700 Hamilton Hallmark Costa Mesa TEL: (714) 641-4100 Los Angeles TEL: (818) 594-0404 Sacramento TEL: (916) 632-4500 San Diego TEL: (619) 571-7540 San Jose TEL: (408) 435-3500 Wyle Electronics Calabasas TEL: (818) 880-9000 Irvine TEL: (714) 789-9953 Rancho Cordova TEL: (916) 638-5282 San Diego TEL: (619) 565-9171 Santa Clara TEL: (408) 727-2500 Zeus, An Arrow Company San Jose TEL: (408) 629-4789 TEL: (800) 52-HI-REL Irvine TEL: (714) 921-9000 TEL: (800) 52-HI-REL CANADA Arrow/Schweber Burnaby, British Columbia TEL: (604) 421-2333 Dorval, Quebec TEL: (514) 421-7411 Nepan, Ontario TEL: (613) 226-6903 Mississagua, Ontario TEL: (905) 670-7769 Farnell Electronic Services Burnaby, British Columbia TEL: (604) 421-6222 Calgary, Alberta TEL: (403) 273-2780 Concord, Ontario TEL: (416) 79S-4884 V. SI. Laurent, Quebec TEL: (514) 697-8149 Nepean, Ontario TEL: (613) 596-6980 Winnipeg, Manitoba TEL: (204) 786-2589 Hamilton Hallmark Mississagua, Ontario TEL: (905) 564-6060 Montreal TEL: (514) 335-1000 Ottawa TEL: (613) 226-1700 Vancouver, B.C. TEL: (604) 420-4101 Toronto TEL: (905) 564-6060 COLORADO Arrow/Schweber Englewood TEL: (303) 799-0258 Hamilton Hallmark Denver TEL: (303) 790-1662 Colorado Springs TEL: (719) 637-0055 Wyle Electronics Thornton TEL: (303) 457-9953 Zeus, An Arrow Company TEL: (408) 629-4789 TEL: (800) 52-HI-REL CONNECTICUT Alliance Electronics, Inc. Shelton TEL: (203) 926-0087 Arrow/Schweber Wallingford TEL: (203) 265-7741 Hamilton Hallmark Danbury TEL: (203) 271-2844 Zeus, An Arrow Company TEL: (914) 937-7400 TEL: (800) 52-HI-REL FLORIDA ArrowfSchweber Deerfield Beach TEL: (305) 429-8200 Lake Mary TEL: (407) 333-9300 Hamilton Hallmark Miami TEL: (305) 484-5482 Orlando TEL: (407) 657 -3300 Largo TEL: (813) 541-5016 Wyle Electronics Fort Lauderdale TEL: (305) 420-0500 SI. Petersburg TEL: (S13) 576-3004 Zeus, An Arrow Company Lake Mary TEL: (407) 333-3055 TEL: (800) 52-HI-REL GEORGIA Arrow/Schweber Duluth TEL: (404) 497-1300 Hamilton Hallmark Atlanta TEL: (404) 623-4400 Wyle Electronics Duluth TEL: (404) 441-9045 Zeus, An Arrow Company TEL: (407) 333-3055 TEL: (800) 52-HI-REL ILLINOIS Arrow/Schweber Itasca TEL: (708) 250-0500 Hamilton Hallmark Chicago TEL: (708) 773-7941 Newark Electronics, Inc. Chicago TEL: (312) 907-5436 Wyle Electronics Addison TEL: (708) 620-0969 Zeus, An Arrow Company Itasca TEL: (708) 250-0500 TEL: (800) 52-HI-REL INDIANA Arrow/Schweber Indianapolis TEL: (317) 299-2071 Hamilton Hallmark Carmel TEL: (317) 575-3500 Zeus, An Arrow Company TEL: (708) 250-0500 TEL: (800) 52-HI-REL • Field Application Assistance Available 19-4 August 14, 1995 IOWA Arrow/Schweber Cedar Rapids TEL: (319) 395-7230 Hamilton Hallmark Cedar Rapids TEL: (319) 362-4757 Zeus, An Arrow Company TEL: (214) 380-4330 TEL: (800) 52-HI-REL KANSAS Arrow/Schweber Lenexa TEL: (913) 541-9542 Hamilton Hallmark Kansas City TEL: (913) 888-4747 Zeus, An Arrow Company TEL: (214) 380-4330 TEL: (SOO) 52-HI-REL MARYLAND Arrow/Schweber Columbia TEL: (301) 596-7800 Hamilton Hallmark Columbia TEL: (410) 720-3400 Wyle Electronics Columbia TEL: (410) 312-4844 Zeus, An Arrow Company TEL: (914) 937-7400 TEL: (800) 52-HI-REL MASSACHUSETTS Arrow/Schweber Wilmington TEL: (508) 658-0900 Gerber Electronics Norwood TEL: (617) 769-6000 Hamilton Hallmark Peabody TEL: (508) 532-9893 Wyle Electronics Bedford (617) 271-9953 Zeus, An Arrow Company Wilmington, MA TEL: (508) 658-4776 TEL: (800) HI-REL MICHIGAN Arrow/Schweber Livonia TEL: (313) 462-2290 Hamilton Hallmark Plymouth TEL: (313) 416-5800 Zeus, An Arrow Company TEL: (708) 250-0500 TEL: (800) 52-HI-REL North American Authorized Distributors (Continued) MINNESOTA Alliance Electronics, Inc. Bumsville TEL: (612) 891-1813 Arrow/schweber Eden Prarie TEL: (612) 941-5280 Hamilton Hallmark Minneapolis TEL: (612) 881-2600 Wyle Electronics Minneapolis TEL: (612) 853-2280 Zeus, An Arrow Company TEL: (214) 380-4330 TEL: (800) 52-HI-REL MISSOURI Arrow/schweber SI. Louis TEL: (314) 567-6888 Hamilton Hallmark SI. Louis TEL: (314) 291-5350 Zeus, An Arrow Company TEL: (214) 380-4330 TEL: (800) 52-HI-REL NEW JERSEY Arrow/schweber Marlton TEL: (609) 596-8000 Pinebrook TEL: (201) 227-7880 Hamilton Hallmark Cherry Hill TEL: (609) 424-0110 Parsippany TEL: (201) 515-1641 Wyle Electronics Mt. Laurel TEL: (609) 439-9110 Rochester TEL: (716) 427-0300 Hamilton Hallmark Long Island TEL: (516) 434-7400 Hauppauge TEL: (516) 434-7470 Rochester TEL: (716) 272-2740 Zeus, An Arrow Company PI. Chester TEL: (914) 937-7400 TEL: (800) 52-HI-REL NORTH CAROLINA Arrow/schweber Raleigh TEL: (919) 876-3132 EMC Charlotte TEL: (704) 394-6195 Hamilton Hallmark Raleigh TEL: (919) 872-0712 Wyle Electronics Raleigh TEL: (919) 481-3737 TEL: 800-950-9953 Zeus, An Arrow Company TEL: (407) 333-3055 TEL: (800) 52-HI-REL OHIO Alliance Electronics, Inc. Dayton TEL: (513) 433-7700 Arrow/schweber Solon TEL: (216) 248-3990 Pine Brook TEL: (201) 882-6356 :zeus, An Arrow Company TEL: (914) 937-7400 TEL: (600) 52-HI-REL NEW MEXICO Hamilton Hallmark Albuquerque TEL: (505) 828-1056 Zeus, An Arrow Com~r/1 TEL: (408) 629-4789 ../ TEL: (800) 52-HI-REL NEW YORK Alliance Electronics, Inc. Huntington TEL: (516) 673-1930 Arrow/schweber Farmingdale TEL: (516) 293-6363 Hauppauge TEL: (516) 231-1000 Melville TEL: (516) 391-1276 TEL: (516) 391-1300 TEL: (516) 391-1633 Centerville TEL: (513) 435-5563 EMC Columbus TEL: (614) 299-4161 Hamilton Hallmark Cleveland TEL: (216) 496-1100 Columbus TEL: (614) 888-3313 Dayton TEL: (513) 439-6735 Toledo TEL: (419) 242-6610 Wyle Electronics Cleveland TEL: (216) 248-9996 Zeus, An Arrow Company TEL: (708) 595-9730 TEL: (800) 52-HI-REL OKLAHOMA Arrow/Schweber Tulsa TEL: (916) 252-7537 Hamilton Hallmark Tulsa TEL: (918) 254-6110 Zeus, An Arrow Company TEL: (214) 380-4330 TEL: (800) 52-HI-REL August 14, 1995 OREGON Almac/Arrow Beaverton TEL: (503) 629-8090 Hamilton Hallmark Portland TEL: (503) 526-6200 Wyle Electronics Beaverton TEL: (503) 643-7900 Zeus, An Arrow Company TEL: (408) 629-4789 TEL: (800) 52-HI-REL WASHINGTON Almac/Arrow Bellevue TEL: (206) 643-9992 Hamilton Hallmark Seattle TEL: (206) 882-7000 Wyle Electronics Redmond TEL: (206) 881-1150 Zeus, An Arrow Company TEL: (408) 629-4789 TEL: (800) 52-HI-REL PENNSYLVANIA Arrow/Schweber Pittsburgh TEL: (412) 856-9490 Hamilton Hallmark Pittsburgh TEL: (800) 332-8638 Zeus, An Arrow Company TEL: (914) 937-7400 TEL: (800) 52-HI-REL WISCONSIN Arrow/schweber Brookfield TEL: (414) 792-0150 Hamilton Hallmark Milwaukee TEL: (414) 780-7200 Wyle Electronics Brookfield TEL: (414) 879-0434 Zeus, An Arrow Company TEL: (708) 250-0500 TEL: (800) 52-HI-REL TEXAS Allied Electronics, Inc. FI.Worth TEL: (800) 433-5700 Arrow/schweber Austin TEL: (512) 835-4180 Dallas TEL: (214) 380-6464 Houston TEL: (713) 647-6868 Hamilton Hallmark Austin TEL: (512) 219-3700 Dallas TEL: (214) 553-4300 Houston TEL: (713) 781-6100 Wyle Electronics Austin TEL: (512) 345-8653 Houston TEL: (713) 679-9953 Richardson TEL: (214) 235-9953 Zeus, An Arrow Company Carrollton TEL: (214) 380-4330 TEL: (600) 52-HI-REL UTAH Arrow/schweber Salt Lake City TEL: (801) 973-6913 Hamilton Hallmark Salt Lake City TEL: (801) 266-2022 Wyle Electronics Orem TEL: (801) 226-0991 West Valley City TEL: (801) 974-9953 Zeus, An Arrow Company TEL: (408) 629-4769 TEL: (600) 52-HI-REL Harris Semiconductor Chip Distributors Chip Supply, Inc. 7725 N. Orange Blossom Trail Orlando. FL 32810-2696 TEL: (407) 298-7100 FAX: (407) 290-0164 Elmo Semiconductor Corp. 7590 North Glenoaks Blvd. Burbank, CA 91504-1052 TEL: (818) 768-7400 FAX: (818) 767-7038 Minco Technology Labs, Inc. 1805 Rutherford Lane Austin, TX 78754 TEL: (512) 834-2022 FAX: (512) 837-6265 Puerto Rican Authorized Distributor Hamilton Hallmark EI Senorail MIS Box 862 San Juan, PR 00926 TEL: (809) 760-1158 FAX: 809 754-4356 South American Authorized Distributor Graftec Electronic Sales Inc. One Boca Place, Suite 305 East 2255 Glades Road Boca Raton, Florida 33431 TEL: (407) 994-0933 FAX: 407 994-5518 BRASIL Graftec Brasil Ltda. Rua baroneza De ITU 336 - 5 01231-000 - Sao Paulo - SP TEL: 55-11-826-5407 FAX: 55-11-826-6526 t/) W ~ LL. LL. 0 t/) W ...I oCt • Field Application Assistance Available t/) 19-5 European Sales Offices and Representatives European Sales Headquarters Harris S.A. Mercure Center Rue de la Fusee 100 B·1130 Brussels, Belgium TEL: 32272421 11 FAX: 32 2 724 22051...09 DENMARK Delco AS Titangade 15 DK • 2200 Copenhagen N TEL: 45 35 8212 00 FAX: 4535821205 FINLAND J. Havullnna & Son Reinikkalan Kartano SF - 51200 Kangasniemi TEL: 358 59 432031 FAX: 358 59 432367 FRANCE Harris Semiconducteurs SARL • 2-4, Avenue de l'Europe F - 78941 Velizy Cedex TEL: 33 1 34 65 40 80 (Dist) TEL: 33 1 34 65 40 27 (Sales) FAX: 33 1 39 46 40 54 August 14, 1995 Harris Semiconductor GmbH Kieler Strasse 55-59 D·254510uickbom TEL: 49 41 06 50 02-04 FAX: 494106 6 88 50 Harris Semiconductor GmbH Wegener Strasse, 5/1 D - 71063 Sindelfingen TEL: 49 7031 86940 FAX: 49 7031 87 38 49 Ecker Mlchelstadt GmbH In den Dorfwiesen 2A Postfach 33 44 D • 64720 Michelstadt TEL: 49 6061 22 33 FAX: 49 6061 5039 Erwin W. Hildebrandt Nieresch 32 D • 48301 Noltuln-Darup TEL: 49 2502 60 65 FAX: 49 2502 18 89 FINK Handelsvertretung Laurinweg, 1 D • 85521 Oltobrunn TEL: 49 89 6 09 70 04 FAX: 498960981 70 Hartmut Welte • Hepbacher Strasse llA D - 88677 Markdorf TEL: 49 7544 7 25 55 FAX: 49 7544 7 25 55 GERMANY Harris Semiconductor GmbH • Putzbrunnerstrasse 69 D·81739 MOnchen TEL: 49 89 63813-0 FAX: 49 89 6377891 ISRAEL Aviv Electronics Ltd Hayetzira Street, 4 Ind. Zone IS - 43651 Ra'anana PO Box 2433 IS - 43100 Ra'anana TEL: 972 9 983232 FAX: 972 9 916510 ITALY Harris SRL • Viale Fulvio Testi, 126 1-20092 Cinisello Balsamo, (Milan) TEL: 39 2 262 07 61 (Disti & OEM ROSE) TEL: 39 2 240 95 01 (Disti & OEM Italy) FAX: 39226222158 (ROSE) TURKEY EMPA Besyol Londra AsiaHi TK - 34630 Sefakoy/lstanbul TEL: 90 1 599 3050 FAX: 90 1 599 3059 UNITED KINGDOM Harris Semiconductor Ltd • Riverside Way Camberley Surrey GU15 3VO TEL: 44 1276686886 FAX: 44 1276682323 Laser Electronics Ballynamoney Greenore Co. Louth, Ireland TEL: 353 4273165 FAX: 3534273518 NETHERLANDS Harris Semiconductor SA Benelux OEM Sales Office Kouterstraat 6 NL - 5345 AR Oss TEL: 31 412038561 FAX: 31 412034419 Complementary Technologies Ltd Redgate Road South Lancashire, Ind. Estate Ashton-In-Makerfield Wigan, Lanes WN4 8DT TEL: 44 1942 274731 FAX: 441942 274732 SPAIN ElcosS. L. CIAvda. Europa, 30 1 B-A Spain 28224 Pozuelo de Alarcon Madrid TEL: 34 1 352 3Q52 FAX: 3413521147 Stuart Electronics Ltd. Phoenix House Bothwell Road Castlehill, Cartuke Lanarkshire ML8 5UF TEL: 441555 751566 FAX: 441555 751562 European Authorized Distributors AUSTRIA Avnet E2000 GmbH Waidhausenstrasse 19 A-1140Wien TEL: 43 1 9112847 FAX: 43 1 9113853 EBV Elektronik • Diefenbachgasse 35/6 A-1150Wien TEL: 4318941774 FAX: 43 1 8941 775 Eurodls Electronics GmbH Lamezanstrasse 10 A-1232Wien TEL: 431610620 FAX: 43161062151 Spoerle Electronic Heiligenstadter Str. 52 A-1190Wien TEL: 43 1 31872700 FAX: 43 1 3692273 BELGIUM Diode Spoerle • Keiberg" Minervastraat, 14/B2 B-1930 Zaventem TEL: 32 2 725 46 60 FAX: 32 2 725 4511 EBV Elektronik • Excelsiorlaan 35B B - 1930 Zaventem TEL: 32 2 716 0010 FAX: 32 2 720 8152 Dltz Schweitzer Vallensbaekvej 41 Postboks 5 DK - 2605 Brondby TEL: 45 42 45 3044 FAX: 45 42 45 92 06 FINLAND Avnet Nortec Italahdenkatu, 18 SF - 00210 Helsinki TEL: 358 061 318250 FAX: 358 06922326 Eurodis Texim Electronics • Avenue des Croix de Guerre 116 B - 1120 Brussels TEL: 32 2 247 49 69 FAX: 32 2 215 81 02 DENMARK Avnet Nortec Transformervej, 17 DK - 2730 Herlev TEL: 45 42 84 2000 FAX: 45 44 92 1552 Bexab Sinimaentie 10C P.O. Box 51 SF - 02630 ESPOO TEL: 358 061 352 690 FAX: 358 061 352 655 FRANCE 3D ZI des Glaises 6/8 rue Ambroise Croizat F - 91127 Palaiseau TEL: 33 1 64 47 29 29 FAX: 33 1 64 47 00 84 • Field Application Assistance Available 19-6 Arrow Electronlque 73 - 79, Rue des Solets Silic 585 F - 94663 Rungis Cedex TEL: 33 1 49 78 49 78 FAX: 33 1 4978 05 96 Avnet EMG France • 79, Rue Pierre Semard P.B.90 F-92322 Chatillon Sous Bagneux TEL, 33 1 49 65 25 00 FAX: 33 1 49 65 25 39 CCI Electronlque • 12, Allee de la Vierge Silic 577 F - 94653 Rungis TEL: 331 41 807000 FAX: 33 1 46 75 32 07 EBV Elektronlk Pare Club de la Haute Maison 16, Rue Galilee Cite Descartes F - n420 Champs-sur-Mame TEL: 33 1 6468 86 09 FAX: 33 1 6468 27 67 European Authorized Distributors (Continued) Harris Semiconductor Chip Distributors EdgeteklRood Tech Zai De Courtaboeuf Avenue Des Andes 91952 Les Ulis Cedex TEL: 33 1 64 46 06 50 FAX: 33 1 69 28 43 96 TWX: 600333 GREECE SemiconCo. 104 Aeolou Street GR • 10564 Athens TEL: 30 1 32 53 626 FAX: 30 13216063 Elmo Z. A. De La Tuilerie B. P. 1077 78204 Mantes·La·Jolie TEL: 33 1 3477 16 16 FAX: 33 1 34 77 95 79 TWX: 699737 Hybritech CM (HCM) 7, Avenue Juliot Curie F· 17027 LA Rochelle Cedex TEL: 33 46 451270 FAX: 33 46 45 04 44 TWX: 793034 EASTERN COUNTRIES HEVGmbH Berliner Strasse, 8 D • 15537 Erkner TEL: 49 3362 580120 FAX: 49 3362 580111 GERMANY AvnetlE2000 • Stahlgruberring, 12 0- 81829 MOnchen TEL: 49 89 4511001 FAX: 49 89 45110129 EBV Elektronlk GmbH • Hans·Pinsel-Strasse 4 o - 85540 Haar-bei-MOnchen TEL: 49 89 45610-0 FAX: 49 89 464488 Eurodis Enatechnik Electronics GmbH • Pascalkehre, 1 0- 25451 Quickbom P.B.1240 o - 25443 Quickbom TEL: 49 4106 701-0 FAX: 49 4106 701268 . Indeg Industrie EIekIronik Emil Kommerling Strasse 5 o - 66954 Pirmasens Postfach 1563 o - 66924 Pirmasens TEL: 49 6331 94065 FAX: 49 6331 94064 SascolHED Semiconductor • Hermann-Oberth Strasse 16 o - 85640 Putzbrunn-beiManchen TEL: 49 89 4611-0 FAX: 49 89 4611-270 Spoerle Electronic • Max-Planck Strasse 1-3 0- 63303 Oreieich-bei-Franklurt TEL: 49 6103 304-8 FAX: 49 6106 3 04-201 ISRAEL Aviv Electronics Hayetzira Street 4, Ind. Zone IS·43651 Ra'anana PO Box 2433 IS· 43100 Ra'anana TEL: 972 9 983232 FAX: 972 9 916510 ITALY EBV Elektronik • Via C. Frova, 34 I • 20092 Cinisello Balsamo (MI) TEL: 39 2 660 17111 FAX: 39 2 660 17020 Eurelettronlca Via Enrico Fermi, 8 1- 20090 Assago (MI) TEL: 39 2 457 841 FAX: 39 2 488 02 75 Lasl Elettronica Viale Fulvio Testi 280 1·20126 Milano TEL: 39 2 66 10 1370 FAX: 39266101385 Silverstar Viale Fulvio Testi 280 1- 20126 Milano TEL: 39 2 66 12 51 FAX: 39 2 66101359 NETHERLANDS Aurlema Nederland BV • Beatrix de Rijkweg, 8 NL - 5657 EG Eindhoven TEL: 3140 502602 FAX: 31 40510255 Diode Spoerle • CoMbaan 17 NL - 3439 NG Nieuwegein TEL: 31340291234 FAX: 31 340235924 Diode Spaerle Postbus 7139 NL - 5605 JC Eindhoven TEL: 31 40 54 54 30 FAX: 31 40535540 EBV Elektronik • Planetenbaan, 2 NL - 3606 AK Maarssenbroek TEL: 31 346562353 FAX: 31 346564277 NORWAY Avnet Nortec Smedsvingen 4B Box 123 N - 1364 Hvalstad TEL: 4766846210 FAX: 47 66 84 65 45 August 14, 1995 PORTUGAL Amitron-Arrow Quinta Grande. Lote 20 Alfragide P • 2700 Amadora TEL: 351.1.47148 06 FAX: 351.1.4710802 SPAIN Amitron-Arrow S.A. Albasanz,75 SP • 28037 Madrid TEL: 34 1 304 30 40 FAX:34 1 327 24 72 EBV Elektronlk • Calle Maria Tubau, 6 SP - 28049 Madrid TEL: 34 1 358 86 08 FAX: 34 1 358 85 60 SWEDEN Avnet Nortec Englundavagen 7 P.O. Box 1830 S· 171 27 Solna TEL: 46 8 6291400 FAX: 46 8 627 0280 Bexab Sweden AB P.O. Box 523 Kemistvagen, lOA S -183 25 Taby TEL: 46 8 630 88 00 FAX: 46 8 732 70 58 SWITZERLAND Avnet E2000 AG Boehirainstrasse 11 CH - 8801 Thalwil TEL: 41 1 7221330 FAX: 411 7221340 Baslx Fur Elektronlk Hardturmstrasse 181 CH - 8010 ZOrich TEL:4112761111 FAX: 41 1 2761234 EBV Elektronik • Vorstadtstrasse 37 CH - 8953 Oietikon TEL: 4117401090 FAX: 4117415110 Eurodls Electronic AG Bahnstrasse 58160 CH - 8105 Regensdorf TEL: 41 .1 8433 111 FAX: 411 8433910 Fabrlmex Spoerle Cherstrasse 4, B.P.B. CH - 8152 Zurich TEL: 41 1 8746262 FAX: 41 1 8746200 TURKEY EMPA Besyol Londra AsfaHi TK - 34630 Sefakoy/lstanbul TEL: 90 212 599 3050 FAX: 902125993059 • Field Application Assistance Available 19-7 UNITED KINGDOM Arrow-Jermyn Electronic Vestry Industrial Estate Sevenoaks Kent TN14 5EU TEL: 44 1234 270027 FAX: 441732 451251 AvnetEmg Jubilee House, Jubilee Road Letchworth Hertfordshire SG6 lQH TEL: 44 1462 488500 FAX: 44 1462 488567 Farnell Electronic Components Armley Road, Leeds West Yorkshire LS12 2QQ TEL: 44 1132 790101 FAX: 441132 633404 Farnell Electronic Services Edinburgh Way. Harlow Essex CM20 20E TEL: 44 1279 626777 FAX: 441279 441687 Micromark Electronics Boyn Valley Road Maidenhead Berkshire SL6 40T TEL: 44 1628 76176 FAX: 441628 783799 Thame Components Thame Park Rd. Thame, Oxfordshire OX9 3ua TEL: 441844 261188 FAX: 441844 261681 Harris Semiconductor Chip Distributors Die Technology Ltd. Corbrook Rd., Chadderton Lancashire OL9 9S0 TEL: 44 61 626 3827 FAX: 4461 6274321 TWX: 668570 Rood Technology Test House Mill Lane, Alton Hampshire GU34 2QG TEL: 44 420 88022 FAX: 44420 87259 TWX: 21137 South African Authorized Distributor TRANSVAAL Allied Electronic Components 10, Skietiood Street Isando, Ext. 3, 1600 P.O. Box 69 Isando, 1600 TEL: 27 11 392 3804/. .. 19 FAX: 27119749625 FAX: 27119749683 Asian Pacific Sales Offices and Representatives JAPAN Harris K.K. Kojimachi-Nakata Bldg. 4F 5-3-5 Kojimachi Chiyoda-ku, Tokyo, 102 Japan TEL: (81) 3-3265-7571 TEL: (81) 3-3265-7572 (Sales) FAX: (81) 3-3265-7575 HONG KONG Harris Semiconductor H.K. Ltd. 13/F Fourseas Building 208-212 Nathan Road Tsimshatsui, Kowloon TEL: (852) 2723-6339 FAX: (852) 2739-8946 TLX:78043645 AUSTRALIA VSI Electronics Ply, Ltd. Unit C 6-8 Lyon Park Road North Ryde NSW 2113 TEL: (612) 878-1299 FAX: (612) 878-1266 INDIA Intersn Private Limited Plot 54, SEEPZ Marol Industrial Area Andheri (E) Bombay 400 096 TEL: (91) 22-832-3097 FAX: (91) 22-836-6682 KOREA Harris Semiconductor YH RM1I419-1 Korea Air Terminal Bldg. 159-6, Sam Sung-Dong, Kang Nam-ku, Seoul 135·728, Korea TEL: 82-2-551-0931/4 FAX: 82-2-551-0930 SINGAPORE Harris Semiconductor Pte Ltd. 1, Tannery Road #09-01 Cencon 1 , Singapore 1334 TEL: 65-748-4200 FAX: 65-748-0400 TAIWAN Harris Semiconductor Room 1101, No. 142, Sec. 3 Ming Chuan East Road Taipei, Taiwan TEL: (886) 2-716-9310 FAX: (886) 2-715-3029 TLX: 78525174 Applied Component Tech. Corp. 8F No. 233-1, Pao-Chia Road Hsin lien CItY, Taipei Hsien, Taiwan, R.O.C. TEL: (886) 2 9170858 FAX: (886) 2 9171895 TECO Enterprise Co., Ltd. 10FL., No. 292 Min-Sheng W. Rd. Taipei, Taiwan TEL: (886) 2-555-9676 FAX: (886) 2-558-6006 Galaxy Far East Corporation 8F-6, No. 390, Sec. 1 Fu Hsing South Road Taipei, Taiwan TEL: (886) 2-705-7266 FAX: (886) 2-708-7901 THAILAND Electronics Source Co., Ltd. 138 Banmoh Rd. Pranakorn, Bangkok 10200 TEL: 66 2 2264145 FAX: 66 2 2254985 Asian Pacific Authorized Distributors AUSTRALIA VSI Electronics Pty, Ltd. Unit C 6-8 Lyon Park Road North Ryde NSW 2113 TEL: (612) 878-1299 FAX: (612) 878-1266 INDIA Graftec Electronic Sales Inc. 49 J.C. Road, Bangalore-560002 TEL: (91) 80 223334612225688 FAX: (91) 802226490 CHINA Edal Electronics Co., Ltd. Room 911-913, Chevalier Commercial Centre, 8, Wang Hoi Road, Kowloon Bay, Kowloon, Hong Kong TEL: (852) 2305-3863 FAX: (852) 2759-8225 JAPAN Hakuto Co., Ltd. 1-1-13 Shinjuku Shinjuku-ku Tokyo 160 TEL: 81-3-3355-7615 FAX: 81-3-3355-7680 Jeplco Corp. Shinjuku Dalichi Seimei Bldg. 2-7-1, Nishl-Shinjuku Shinjuku-ku, Tokyo 163 TEL: 03-3348-0611 FAX: 03-3348-0623 Means Come Ltd. Room 1007, Harbour Centre 8 Hok Cheung Street Hung Hom, Kowloon TEL: (852) 2334-8188 FAX: (852) 2334-8649 H.B. Corporation 135-260, 5th/FI, Aju Bldg. 184·11, Poi-Dong, Kangnam-Ku, Seoul TEL: 82(02) 579-3495-6, 579-6918 FAX: 82(02) 579-6919-703 Inhwa Company, Ltd. Room 11305 Daegyo Bldg., 56-4, Wonhyoro - 2GA, Young San-Ku, Seoul 14Q-113, Korea TEL: 822-703-7231 FAX: 822-703-8711 August 14, 1995 Macnica Inc. Hakusan High Tech Park 1-22-2, Hakusan Midori-ku, Yokohama-shi, Kanagawa 226 TEL: 045-939-6116 FAX: 045-939-6117 Sunnlce Electronics Co., Ltd. Flat F, 51F, Everest Ind. Ctr. 396 Kwun Tong Road Kowloon TEL: (852) 2790-8073 FAX: (852) 2763-5477 Micron, Inc. DJK Kouenji Bldg. 5F 4-26-16, Kouenji-Minami Suginaml-Ku, Tokyo 166 TEL: 03-3317-9911 FAX: 03-3317-9917 HONG KONG Array Electronics Limited 241F., Wyler Centre, Phase 2 200 Tai Un Pai Road Kwai Chung New Territories, H.K. TEL: (852) 2418-3700 FAX: (852) 2481-5872 KumOh Electric Co., Ltd. 203-1, Jangsa-Dong, Chongro-ku, Seoul TEL: 822-279-3614 FAX: 822-272-6496 NEW ZEALAND Components and Instrumantatlon NZ, Ltd. 19 Pretoria Street LowerHutt P.O. Box 38-099 Wellington TEL: (64) 4-566-3222 FAX: (64) 4-566-2111 Inch cape Industrial 10/F, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fang New Territories TEL: (852) 2410-6555 FAX: (852) 2401-2497 Klngty Intematlonal Co., Ltd. Flat 03, 161F, Block A, Hi-Tech Ind. Centre 5-12 Pak Tin Par St., Tsuen Wan New Territories, H.K. TEL: (852) 2499-3109 FAX: (852) 2417-0961 Okura Electronics Co., Ltd. Okura Shoji Bldg. 2-3-6, Ginza Chuo-ku, Tokyo 104 TEL: 03-3564-6871 FAX: 03-3564-6870 Takachiho Koheki Co., Ltd. 1-2-8, Yotsuya Shinjuku-ku, Tokyo 160 TEL: 03-3355-6696 FAX: 03-3357-5034 KOREA KumOh Electric Co., Ltd. 203-1, Jangsa-Dong, Chongro-ku, Seoul TEL: 822-279-3614 FAX: 822-272-6496 • Field Application Assistance Available 19-8 Inhwa Company, Ltd. Room #305, Daegyo Bldg., 56-4, Wonhyoro - 2GA, Young San-Ku, Seoul 140-113, Korea TEL: 822-703-7231 FAX: 822-703-8711 NEW ZEALAND Components and Instrumentation NZ, Ltd. 19 Pretoria Street, Lower Hutt P.O. Box 38-099 Wellington TEL: (64) 4-566-3222 FAX: (64) 4-566-2111 SINGAPORE B.B.S Electronics Pte, Ltd. 1 Genling Link #05-03 Perfect Indust. Bldg. Singapore 1334 TEL: (65) 748-8400 FAX: (65) 748-8466 TAIWAN Applied Component Tech. Corp. 8F No. 233-,1 Pao-Chial Road Hsin lien City, Taipei Hsein, TEL: (02) 9170858 FAX: (02) 9171895 Galaxy Far East Corporation 8F-6, No. 390, Sec. 1 Fu Hsing South Road Taipei, Taiwan TEL: (886) 2-705-7266 FAX: (886) 2-708-7901 TECO Enterprise Co., Ltd. 10FL., No. 292, Min-Sheng W. Rd. Taipei, Taiwan TEL: (886) 2-555-9676 FAX: (886) 2-558-6006 THAILAND Electronics Source Co., Ltd. 138 Banmoh Rd. Pranakom, Bangkok 10200 TEL: 66 2 2264145 FAX: 66 2 2254985