1994_Harris_Digital_Signal_Processing_Data_Book 1994 Harris Digital Signal Processing Data Book
User Manual: 1994_Harris_Digital_Signal_Processing_Data_Book
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New Digital Signal Processing Products
HSP50016
II
~______D_I_G_rr._~L
__
DO_WN
___
C_O_NV_E_RT
__
E_R______~
(Page 6-3)
• SINGLE CHIP NARROW BAND DOWN CONVERTER
=52 MSPS
OUTPUT SAMPLE RATE =82Hz TO 459Hz
TUNING RESOLUTION =0.OO12Hz
HSP43216
~__________HA
__
L_F_B_AN_D
__
R_LTE
__
R________~
(Page 3-43)
• UPIDOWN CONVERSION BY Fs/4
• INPUT SAMPLE RATE
• INTERPOLATIONIDECIMATION BY 2
•
• SHAPE FACTOR
•
=1.24
• PASSBAND RIPPLE < 0.OOO5dB
• STOPBAND ATIENUATION > 90dB
H$P50016-EV
II
HSP43124
~_______D_D_C_EV
__
A_Lu_~_n_O_N_B_O_A_R_D______~ ~_________S_E_R_IA_L_UO
__F_I~_JE_R
__________~
(Paga 8-10)
(Page 3-3)
• PC BASED DATA AND CONTROL
• 24 BIT INPUT, 32 BIT OUTPUT DATA
• REAL TIME DATA AND CONTROL
• 256 TAP PROGRAMMABLE FIR FILTER
• RAPID PROTOTYPING
• 5 CASCADED HALF BAND FILTERS
HSP50110
DIGITAL QUADRATURE TUNER
(Page 6-25)
• FRONT END OF DEMODULATION CHIP SET
• DEMODULATES PSK, FSK, AM, FM
• PROVIDES TUNING, INITIAL FILTERING
• INPUT SAMPLE RATE =60MSPS
• DATA BITS
=10
$5.00
HARRIS SEMICONDUCTOR
DSP PRODUCTS
This Digital Signal Processing databook represents the full line of Harris
Semiconductor DSP products for commercial and military applications
and supersedes previously published DSP material under the Harris, GE,
RCA or Intersil names. For a complete listing of all Harris Semiconductor
products, please refer to the Product Selection Guide (PSG-201 S;
ordering information below.)
For complete, current and detailed technical specifications on any Harris
devices please contact the nearest Harris sales, representative or distributor office; or direct literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-28
Melbourne, FL 32901
TEL: 1-800-442-7747
FAX: (407) 724-3937
See Section 12 for Data Sheets Available on AnswerFAX
See Technical Assistance Listing on Page vi
u.s. HEADQUARTERS
EUROPEAN HEADQUARTERS
Harris Semiconductor
1301 Woody Burke Road
Melbourne, Florida 32902
TEL: (407) 724-3000
Harris Semiconductor
Mercure Centre
Rue de la Fusee, 100
1130 Brussels, Belgium
TEL: 32224621 11
SOUTH ASIA
NORTH ASIA
Harris Semiconductor H.K. Ltd
131F Fourseas Building
208-212 Nathan Road
Tsimshatsui, Kowloon
Hong Kong
Harris K.K.
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-Ku, Tokyo 163 Japan
TEL: (81) 3-3345-8911
TEL: (852) 723-6339
See our
specs in
CAPS
Copyright © Harris Corporation 1994
(All Rights Reserved)
Printed in USA, 211994
iii
Harris Semiconductor products are sold by description only. All specifications in this product
guide are applicable only to packaged products; specifications for die are available upon
request. Harris reseNes the right to make changes in circuit design. specifications and other
information at any time without prior notice. Accordingly, the reader is cautioned to verify that
information in this publication is current before placing orders. Reference to products of other
manufacturers are solely for convenience of comparison and do not imply total equivalency of
deSign. performance. or otherwise.
iv
DIGITAL SIGNAL PROCESSING
FOR COMMERCIAL AND MILITARY APPLICATIONS
II
Multipliers II
One Dimensional Filters II
Video Processing II
General Information
Signal Synthesizers
II
II
Special Function II
Development Tools II
Application Notes and Tech Briefs IJ
Quality and Reliability iii
Down Conversion and Demodulation
Packaging Information
II
IE
Sales Offices IE
How to Use Harris AnswerFAX
v
TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook.
please contact the Field Applications Engineering staff available at one of the following Harris Sales Offices:
UNITED STATES
CALIFORNIA
San Jose ...... '" ................. 408-985-7322
Woodland Hills ...................... 818-992-0686
FLORIDA
Melbourne. " ...................... 407-723-0501
GEORGIA
Duluth ............................. 404-476-2035
ILLINOIS
Schaumburg ........................ 708-240-3480
NEW JERSEY
Voorhees .........•................ 609-751-3425
NEW YORK
Great Neck ......................... 516-829-9441
INTERNATIONAL
FRANCE
Paris. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1-346-54046
GERMANY
Munich ........................... 49-8-963-8130
HONG KONG
Kowloon ........................... 852-723-6339
ITALY
Milano ............................ 39-2-262-0761
JAPAN
Tokyo ........................•.. 81-33-345-8911
KOREA
Seoul ............................ 82-2-551-0931
SINGAPORE
Singapore ........................... 65-291-0203
UNITED KINGDOM
Camberley ........... " .......... 44-2-766-86886
For literature requests. please contact Harris at 1-800-442-7747 (1-800-4HARRIS)
vi
OS p-------t 1
GENERAL INFORMATION
ALPHA NUMERIC PRODUCT INDEX
PAGE
Z
.... 0
DECI-MATETM
Harris HSP43220 Decimating Digital Filter Development Software ................ .
8-3
~ti
HMA510
16 x 16-8it CMOS Parallel Multiplier Accumulator ................. ',' .......... .
2-3
Za:
HMA51 0/883
16 x 16-8it CMOS Parallel Multiplier Accumulator ............................. .
2-10
CJu..
~
HMU16
16 x 16-8it CMOS Parallel Multipliers ....................................... .
2-15
HMU17
16 x 16-8it CMOS Parallel Multipliers ....................................... .
2-15
HMU161883
16 x 16-8it CMOS Parallel Multiplier ........................................ .
2-25
HMU17I883
16 x 16-8it CMOS Parallel Multiplier ........................................ .
2-31
HSP-EVAL
DSP Evaluation Platform ................................................. .
8-7
HSP43124
Serial 110 Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
HSP43168
Dual FIR Filter ......................................................... .
3-18
HSP43168/883
Dual FIR Filter ......................................................... .
3-35
HSP43216
Halfband Filter . ....................................................... .
3-43
HSP43220
Decimating Digital Filter ................................................. .
3-60
HSP43220/883
Decimating Digital Filter ................................................. .
3-83
HSP43481
Digital Filter ........................................................... .
3-90
HSP43481/883
Digital Filter ........................................................... .
3-105
HSP43881
Digital Filter ........................................................... .
3-110
HSP43881/883
Digital Filter ........................................................... .
3-125
HSP43891
Digital Filter ........................................................... .
3-131
HSP43891/883
Digital Filter ........................................................... .
3-147
HSP45102
12-8it Numerically Controlled Oscillator ..................................... .
5-3
DECI-MATETM is a Trademark of Harris Corporation
NOTE: Bold Type Designates a New Product from Harris.
1883 Data Sheet Format - In the interests of conserving space, data sheets for 1883 qualified products have been printed without the Pinouts,
Pin Description, Waveforms, AC Test Load Circuit and Design Information sections. The information in these sections
can be obtained from the corresponding portion of the commercial data sheets.
1-1
w::E
Wo
ALPHA NUMERIC PRODUCT INDEX (Continued)
PAGE
HSP45106
16-Bit Numerically Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
5-10
HSP451 061883
16-Bit Numerically Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20
HSP45116
Numerically Controlled Oscillator/Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
5-26
HSP451161883
Numerically Controlled Oscillator/Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-47
HSP45116-DB
HSP45116 Daughter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-8
HSP45240
Address Sequencer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3
HSP45240/883
Address Sequencer. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-15
HSP45256
Binary Correlator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-21
HSP452561883
Binary Correia tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-34
HSP48212
Digital Video Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
HSP48410
Histogrammer/Accumulating Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12
HSP4841 0/883
Hlstogrammer/Accumulatlng Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-23
HSP48901
3 x 3 Image Filter. . . . . . .. .. . .. . . . . . . . . . . . . . .. . . . .. . . . .. . . . . . . . . . . . . . .. . .
4-31
HSP48908
Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-40
HSP489081883
Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-57
HSP50016
Digital Down Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3
HSP50016-EV
DDC Evaluation Plat10rm . . . . .. . . . .. . . . . . . .... . . . ... . . .. . . . .. . . . . . . . . .. . .
8-10
HSP50110
Digital Quadrature Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-25
HSP9501
Programmable Data Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-64
HSP9520
Multilevel Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-42
HSP9521
Multilevel Pipeline Registers. . . . . . . . .. . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . .
7-42
NOTE: Bold lYpe DeSignates a New Product from Harris.
1883 Data Sheet Format - In the interests of conserving space, data sheets for 1883 qualified products have been printed without the Pinouts,
Pin DeseripUon, Waveforms, AC Test Load Circuit and Design InformaUon sections. The Information in these sections
can be obtained from the corresponding porUon of the commercial data sheets.
1-2
PRODUCT INDEX BY FAMILY
PAGE
DEVELOPMENT TOOLS
DECI-MATETM
Harris HSP43220 Decimating Digital Filter Development Software. . . . . . . . . . . . . . .
8·3
HSP·EVAL
DSP Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
8·7
HSP45116·DB
HSP45116 Daughter Board. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
8·8
H5P50016-EV
DDC Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8·10
DOWN CONVERSION AND DEMODULATION
HSP50016
Digital Down Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3
H5P50110
Digital Quadrature Tuner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6·25
HMA510
16 x 16·Bit CMOS Parallel Multiplier Accumulator. . . . . . . . . . . . . . . . . .. . . . . . . . . .
2·3
HMA51 0/883
16 x 16·Bit CMOS Parallel Multiplier Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·10
HMU16, HMU17
16 x 16-Bit CMOS Parallel Multipliers. . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
2·15
HMUl61883
16 x 16·Bit CMOS Parallel Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-25
HMU17/883
16 x 16-Bit CMOS Parallel Multiplier. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
2·31
MULTIPLIERS
ONE DIMENSIONAL FILTERS
H5P43124
5erlaill0 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·3
HSP43168
Dual FIR Filter. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·18
HSP43168/883
Dual FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·35
H5P43216
Halfband Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·43
HSP43220
Decimating Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·60
HSP43220/883
Decimating Digital Filter. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·83
HSP43481
Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·90
HSP43481/883
Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·105
HSP43881
Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·110
HSP43881 1883
Digital Filter. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·125
HSP43891
Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·131
HSP43891/883
Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·147
NOTE: Bold Type Designates a New Product from Harris.
1883 Data Sheet Format· In the interests of conserving' space, data sheets for 1883 qualified products have been printed without the Pinouts,
Pin Description, Waveforms, AC Test Load Circuit and Design Information sections. The information in these sections
can be obtained from the corresponding portion of the commercial data sheets.
1·3
PRODUCT INDEX BY FAMILY (Continued)
PAGE
SIGNAL SYNTHESIZERS
HSP45102
12-Bit Numerically Controlled Oscillator. . . . . . . .. . . . .. . . . .. . . . . . . . . . . . • . ... .
5-3
HSP45106
16-Bit Numerically Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10
HSP451 06/883
16-Bit Numerically Controlled Oscillator. . .. . . . . . . . . .. . . . .. . . . .. . . . .. . . . . . . .
5-20
HSP45116
Numerically Controlled Oscillator/Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26
HSP451161883
Numerically Controlled Oscillator/Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-47
SPECIAL FUNCTION
HSP45240
Address Sequencer. . . . . . . .. . . . . . . . . . . . . . . . .• ... . . . .. . . . .. . . ... . . . . . . .
7-3
HSP45240/883
Address Sequencer.. . . . . . .. . . . .. . . . .. . . . . . . . . .. . . . . . . . . . . . . . .. . . . .. . .
7-15
HSP45256
Binary Correlator . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-21
HSP45256/883
Binary Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-34
HSP9520, HSP9521
Multilevel Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-42
VIDEO PROCESSING
HSP48212
Digital Video Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
HSP48410
Histogrammer/Accumulating Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12
HSP4841 0/883
Histogrammer/Accumulating Buffer. . . .. . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . .
4-23
HSP48901
3
x 3 Image Filter. . . ... . . . . . . . . . . . . . ... . . .. . . . . . . . . .. . . . . . . . . .. . . . .. . .
4-31
HSP48908
Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-40
HSP489081883
Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-57
HSP9501
Programmable Data Buffer. . .. . . . .. . . . .. . .. .. . . . . . . . . .. . . . . . . . . . . . . . .. . .
4-64
NOTE: Bold Type Designates a New Product from Harris.
1883 Data Sheet Format - In the interests of conserving space, data sheets for /883 qualified products have been printed without the Pinouts,
Pin Description, Waveforms, AC Test Load Circuit and Design Information sections. The Information in these sections
can be obtained from the corresponding portion of the commercial data sheelS.
1-4
DATA ACQUISITION PRODUCTS
AID CONVERTERS· DISPLAY
CA3162
AID Converter for 3-Digit Display
HI7131, HI7133
31/ 2 Digit Low Power, High CMRR LCD/LED Display Type AID Converter
ICL7106,ICL7107
3 1/ 2 Digit LCD/LED Display AID Converter
ICL7116,ICL7117
3 1/ 2 Digit LCD/LED Display AID Converter with Display Hold
ICL7126
3 1/ 2 Digit Low Power Single-Chip AID Converter (AnswerFAX Only) Document # 3084
See Section 12
ICL7129
4 1/ 2 Digit LCD Single-Chip AID Converter
ICL7136, ICL7137
3 1/ 2 Digit LCDILED Low Power Display AID Converter with Overrange Recovery
ICL7139,ICL7149
33/ 4 Digit Autoranging Multimeter
ICL80521ICL71C03,
ICL80681ICL71 C03
Precision 4 1/ 2 Digit AID Converter (AnswerFAX Only) Document # 3081 See Section 12
AJD CONVERTERS· FLASH
CA3304
CMOS Video Speed 4-Bit Flash AID Converter
CA3306
CMOS Video Speed 6-Bit Flash AID Converter
CA3318C
CMOS Video Speed 8-Bit Flash AID Converter
HI1166
8-Blt, 2S0MSPS Flash AID Converter
HI1276
8-Blt, SOOMSPS Flash AID Converter
HI1386
8-Blt, 7SMSPS Flash AID Converter
HI1396
8-Blt, 12SMSPS Flash AID Converter
HI-5700
8-Bit, 20MSPS Flash AID Converter
HI-S701
6-Blt, 30MSPS Flash AID Converter
AJD CONVERTERS· INTEGRATING
HI-7159A
Microprocessor Compatible 51/ 2 Digit AID Converter
ICL7109
12-Bit Microprocessor Compatible AID Converter
ICL7135
4 1/ 2 Digit BCD Output AID Converter
ICL80521ICL7104,
ICL80681ICL7104
14/16-Bit I1P-Compatible, 2-Chip AID Converter (AnswerFAX Only) Document # 3091
See Section 12
NOTE: Bold Type Designates a New Product from Harris.
1-5
DATA ACQUISITION PRODUCTS
(Continued)
AID CONVERTERS - SAR
ADcoa02, ADCoa03, a-Bit IlP Compatible AID Converters
ADCOa04
CA3310, CA3310A
CMOS 10-Bit AID Converter with Internal Track and Hold
HI-574A,
HI-674A,
HI-774
Complete 12-Bit AID Converter with Microprocessor Interface
HI581 0
CMOS 10llS 12-Blt Sampling AID Converter with Internal Track and Hold
HI5812
CMOS 20llS 12-Blt Sampling AID Converter with Internal Track and Hold
HI5813
CMOS 3.3V, 251ls 12-Blt Sampling AID Converter with Internal Track and Hold
HI7152
10-Bit High Speed AID Converter with Track and Hold (AnswerFAX Only) Document # 3100
See Section 12
HI7151
10-Bit High Speed AID Converter with Track and Hold (AnswerFAX Only) Document # 3099
See Section 12
ICL7112
12-Bit High-Speed CMOS IlP-Compatible AID Converter (AnswerFAX Only) Document # 3639
See Section 12
ICL7115
14-Bit High Speed CMOS IlP-Compatible AID Converter (AnswerFAX Only) Document # 3101
See Section 12
AID CONVERTERS - SIGMA-DELTA
HI7190
24-Blt High Precision Sigma-Delta AID Converter
AID CONVERTERS - SUBRANGING
HI1175
8-Blt, 20MSPS Flash AID Converter
H11176
8-Blt, 20MSPS Flash AID Converter
HI5800
12-Blt, 3MSPS Sampling AID Converter
HI-7153
a Channel, 10-Bit High Speed Sampling AID Converter
COMMUNICATION INTERFACE
HIN230thru
HIN241
+5V Powered RS-232 TransmitterS/Receivers
ICL232
+5V Powered Dual RS-232 Transmitter/Receiver
NOTE: Bold Type Designates a New Product from Harris.
1-6
DATA ACQUISITION PRODUCTS
(Continued)
COUNTERS WITH DISPLAY DRIVERSITIMEBASE GENERATORS
HA721 0
Low Power Crystal Oscillator
ICM7213
One Second/One Minute Timebase Generator
ICM7216A,
8-Digit Multi-Function Frequency CounterlTimer
ICM7216B,ICM7216D
ICM7217
4-Digit LED Display Programmable Up/Down Counter
ICM7224
41/ 2 Digit LCD Display Counter
ICM7226A, ICM7226B8-Digit Multi-Function Frequency CounterlTimers
ICM7249
5 1/ 2 Digit LCD j.1-Power Event/Hour Meter
01A CONVERTERS
AD7520, AD7530,
AD7521, AD7531
10-Bit, 12-Bit Multiplying D/A Converters
AD7523, AD7533
8-Bit Multiplying D/A Converters
AD7541
12-Bit Multiplying D/A Converter
AD7545
12-Bit Buffered Multiplying CMOS DAC
CA3338, CA3338A
CMOS Video Speed 8-Blt R2R D/A Converter
HI-562A
12-Bit High Speed Monolithic D/A Converter (AnswerFAX Only) Document # 3580
See Section 12
HI-565A
High Speed Monolithic D/A Converter with Reference
HI-DAC80V,
HI-DAC85V
12-Bit, Low Cost, Monolithic D/A Converter
H11171
8-Blt, 40MSPS High Speed D/A Converter
H120201, HI20203
1018-Bit, 160MSPS Ultra High Speed D/A Converter
ICL7121
16-Bit Multiplying Microprocessor-Compatible D/A Converter (AnswerFAX Only)
Document # 3112 See Section 12
ICL7134
14-Bit Multiplying J.lP-Compatible D/A Converter AnswerFAX Only) Document # 3113
See Section 12
DISPLAY DRIVERS
CA3161
BCD to Seven Segment Decoder/Driver
ICM7211,ICM7212
4-Digit ICM7211 (LCD) and ICM7212 (LED) Display Drive
ICM7228
8-Digit J.lP Compatible LED Display Decoder Driver
ICM7231, ICM7232
Numeric/Alphanumeric Triplexed LCD Display Driver
ICM7243
B-Character J.lP-Compatible LED Display Decoder Driver
NOTE: Bold Type Designates a New Product from Harris.
1-7
DATA ACQUISITION PRODUCTS
(Continued)
MULTIPLEXERS
DG406, DG407
Single 16-ChanneUDlfferentlal 8-Channel CMOS Analog Multiplexers
DG408, DG409
Single 8-ChanneUDlfferentlal 4-Channel CMOS Analog Multiplexers
DG458, DG459
Single 8-ChanneUDlfferentlal 4-Channel Fault Protected Analog Multiplexers
DG506A, DG507A,
DG50SA, DG509A
CMOS Analog MuHiplexers
DG526, DG527,
DG52B, DG529
Analog CMOS latchable Multiplexers
HI-1B1SA, HI-l828A
low Resistance, Single a Channel and Differential 4 Channel CMOS Analog MuHiplexers
HI-506, HI-507,
HI-50S, HI-509
Single 16 and 81Differentiala and 4 Channel CMOS Analog Multiplexers
HI-506A, HI-507A,
HI-50BA, HI-509A
16 Channel, a Channel, Differential a and Differential 4 Channel CMOS Analog MUXs with Active Overvoltage Protection
HI-516
16 ChanneVDifferentiala Channel CMOS High Speed Analog MuHiplexer
HI-51S
B ChanneVDifferential 4 Channel CMOS High Speed Analog MuHiplexer
HI-524
4 Channel Wideband and Video Multiplexer
HI-539
Monolithic, 4 Channel, low level, Differential Multiplexer
HI-546, HI-547,
HI-54S, HI-549
Single 16 and a, DifferentialB and 4 Channel CMOS Analog MUXs with Active
Overvoltage Protection
IH610S
a-Channel CMOS Analog Multiplexer (AnswerFAX Only) Document # 3156 See Section 12
IH620S
4-Channel Differential CMOS Analog MuHiplexer (AnswerFAX Only) Document # 3157
See Section 12
SPECIAL PURPOSE
AD590
2 Wire Current Output Temperature Transducer
ICla069
low Voltage Reference
ICM7170
lIP-Compatible Real-Time Clock
NOTE: Bold Type DeSignates a New Product from Harris.
l-B
DATA ACQUISITION PRODUCTS
(Continued)
SWITCHES
DG181 thru DG191
High-Speed Driver with JFET Switch (AnswerFAX Only) Document # 3114 See Section 12
DG200, DG201
CMOS DuaVQuad SPST Analog Switches
DG201 A, 00202
Quad SPST CMOS Analog Switches
DG211, DG212
SPST 4 Channel Analog Switch
DG300A, DG301 A,
DG302A, DG303A
TTL Compatible CMOS Analog Switches
DG308A, DG309
Quad Monolithic SPST CMOS Analog Switches
DG401, DG403,
DG405
Monolithic CMOS Analog Switches
DG411,DG412,
DG413
Monolithic Quad SPST CMOS Analog Switches
DG441 , DG442
MonolHhlc Quad SPST CMOS Analog Switches
DG444, DG445
Monolithic Quad SPST CMOS Analog Switches
HI-200, HI-201
DuaVQuad SPST CMOS Analog Switches
HI-201 HS
High Speed Quad SPST CMOS Analog Switch
HI-222
High FrequencyNideo Switch (AnswerFAX Only) Document # 3124 See Section 12
HI-300 thru
HI-307
CMOS Analog Switches
HI-381 thru
HI-390
CMOS Analog Switches
HI-5040 thru
HI-5051, HI-5046A
and HI-5047A
CMOS Analog Switches
IH401A
QUAD Varafet Analog Switch (AnswerFAX Only) Document # 3128 See Section 12
IH5009 thru IH5012, Virtual Ground Analog Switch (AnswerFAX Only) Document # 3129 See Section 12
IH5014, IH5016 thru
IH5020, IH5022,
IH5024
IH5043
Dual SPOT CMOS Analog Switch
IH5052, IH5053
Quad CMOS Analog Switch
IH5140 thru IH5145
High-Level CMOS Analog Switch
IH5151
Dual SPOT CMOS Analog Switch
IH5341,IH5352
Dual SPST, Quad SPST CMOS RFNideo Switches
IH6201
Dual CMOS Driver/voltage Translator (AnswerFAX Only) Document # 3136 See Section 12
NOTE: Bold Type Designates a New Product from Harris.
1-9
LINEAR AND TELECOM PRODUCTS
COMPARATORS DATA SHEETS
CA139, CA239,
CA339, LM339
Quad Voltage Comparators for Industrial, Commercial and Military Applications
CA3098
Programmable Schmitt Trigger - with Memory Dual Input Precision Level Detectors
CA3290
BiMOS Dual Voltage Comparator with MOSFET Input, Bipolar Output
HA-4900, HA-4902,
HA-4905
Precision Quad Comparator
HFA-0003,
HFA-0003L
Ultra High Speed Comparator
DIFFERENTIAL AMPLIFIERS DATA SHEETS
CA3028, CA3053
DifferentiaVCascode Amplifiers for Commercial and Industrial Equipment from DC to 120MHz
CA3049, CA3102
Dual High Frequency Differential Amplifiers For Low Power Applications Up 500MHz
CA3054
Transistor Array - Dual Independent Differential Amp for Low Power Applications from DC to 120MHz
OPERATIONAL AMPLIFIERS DATA SHEETS
CA124, CA224,
CA324, LM324·,
LM2902·
Quad Operational Amplifiers for Commercial, Industrial, and Military Applications
CA 158, CA258,
CA358, CA2904,
LM358·, LM2904·
Dual Operational Amplifiers for Commercial Industrial, and Military Applications
CA741 , CA1458,
CA1558, LM741·,
LM1458·, LM1558·
High Gain Single and Dual Operational Amplifiers for Military, Industrial and Commercial Applications
CA3020
Multipurpose Wide-Band Power Amps Military, Industrial and Commercial Equipment at Frequency Up to
8M Hz
CA3060
Operational Transconductance Amplifier Arrays
CA3078
Micropower Operational Amplifier
CA3080
Operational Transconductance Amplifier (OTA)
CA3094
Programmable Power Switch/Amplifier for Control and General Purpose Applications
CA31 00
Wideband Operational Amplifier
CA3130
BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3140
BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
CA3160
BiMOS Operational Amplifiers with MOSFET Input/CMOS Output
CA3193
BiCMOS Precision Operational Amplifiers
CA3240
Dual BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
CA3260
BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3280
Dual Variable Operational Amplifier
NOTE: Bold Type Designates a New Product from Harris.
1-10
LINEAR AND TELECOM PRODUCTS (Continued)
OPERATIONAL AMPLIFIERS DATA SHEETS (Continued)
CA3420
Low Supply Voltage, Low Input Current SiMOS Operational Amplifiers
CA3440
Nanopower SiMOS Operational Amplifier
CA3450
Video Line Driver, High Speed Operational Amplifier
CA5130
SiMOS Microprocessor Operational Amplifier with MOSFET Input/CMOS Output
CA5160
SiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
CA5260
SiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
CA5420
Low Supply Voltage, Low Input Current SiMOS Operational Amplifier
CA5470
Quad Microprocessor SiMOS-E Operational Amplifiers with MOSFET InputlBipolar Output
HA-2400, HA-2404,
HA-2405
PRAM Four Channel Programmable Amplifiers
HA-2406
Digitally Selectable Four Channel Operational Amplifier
HA-2444
Selectable, Four Channel Video Operational Ampllfler
HA-2500, HA-2502,
HA-2505
Precision High Slew Rate Operational Amplifiers
HA-2510, HA-2512,
HA-2515
High Slew Rate Operational Amplifiers
HA-2520, HA-2522,
HA-2525
Uncompensated High Slew Rate Operational Amplifiers
HA-2529
Uncompensated, High Slew Rate High Output Current, Operational Amplifier
HA-2539
Very High Slew Rate Wide band Operational Amplifier
HA-2540
Wideband, Fast Settling Operational Amplifier
HA-2541
Wideband, Fast Settling, Unity Gain Stable, Operational Amplifier
HA-2542
Wideband, High Slew Rate, High Output Current Operational Amplifier
HA-2544
Video Operational Amplifier
HA-2548
Precision, High Slew Rate, Wideband Operational Amplifier
HA-2600, HA-2602,
HA-2605
Wideband, High Impedance Operational Amplifiers
HA-2620, HA-2622,
HA-2625
Very Wideband, Uncompensated Operational Amplifiers
HA-2640, HA-2645
High Voltage Operational Amplifiers
HA-2705
Low Power, High Performance Operational Amplifier
HA-2839
Very High Slew Rate Wldeband Operational AmplHler
HA-2840
Very High Slew Rate Wldeband Operational Amplifier
HA-2841
Wideband, Fast Settling, Unity Gain Stable, Video Operational Amplifier
HA-2842
Wldeband, High Slew Rate, High Output Current, Video Operational Ampllfler
HA-2850
Low Power, High Slew Rate Wldeband Operational Amplifier
NOTE: Bold Type Designates a New Product from Harris.
1-11
LINEAR AND TELECOM PRODUCTS (Continued)
OPERATIONAL AMPLIFIERS DATA SHEETS (Continued)
HA-4741
Quad Operational Amplifier
HA-5002
Monolithic. Wideband. High Slew Rate. High Output Current Buffer
HA-5004
100MHz Current Feedback Amplifier
HA-5020
100MHz Current Feedback Video Amplifier
HA5022, HAS024
Dual, Quad 100MHz Video Current Feedback Amplifier with Disable
HA5023, HAS025
Dual, Quad 100MHz Video Current Feedback Amplifier
HA-5033
Video Buffer
HA-S101. HA-5111
Low Noise. High Performance Operational Amplifiers
HA-5102. HA-5104.
HA-5112. HA-5114
Low Noise. High Performance Operational Amplifiers
HA-5127
Ultra-Low Noise Precision Operational Amplifier
HA-5130. HA-5135
Precision Operational Amplifiers
HA-5134
Precision Quad Operational Amplifier
HA-5137
Ultra-Low Noise Precision Wideband Operational Amplifier
HA-Sl42. HA-5144
DuaVQuad Ultra-Low Power Operational Amplifiers
HA-5147
Ultra-Low Noise Precision High Slew Rate Wideband Operational Amplifier
HA-5160. HA-5162
Wideband. JFET Input High Slew Rate. Uncompensated. Operational Amplifiers
HA-5170
Precision JFET Input Operational Amplifier
HA-5177
Ultra-Low Offset Voltage Operational Amplifier
HA-5190. HA-5195
'Wideband. Fast Settling Operational Amplifiers
HA-5221. HA-5222
Low Noise. Wideband Precision Operational Amplifiers
HAS232, HAS234
Precision Dual and Quad Operational Amplifiers
HFA-0001
Ultra High Slew Rate Operational Amplifier
HFA-0002
Low Noise Wideband Operational Amplifier
HFA-0005
High Slew Rate Operational Amplifier
HFA 1100, HFA 1120 Ultra High-Speed Current Feedback Amplifiers
HFA11 OS, HFA 1106, High-Speed, Low Power, Current Feedback Operational Amplifiers
HFA1135, HFA114S
HFA1110
7S0MHz Low Distortion Unity Gain, Closed Loop Buffer
HFA1112
Ultra High-Speed Closed Loop Buffer Amplifier
HFA1113
High-Speed, Output Clamping Closed Loop Buffer
HFA1130
Output Clamping, Ultra High-Speed Current Feedback Amplifier
ICL7611. ICL7612
ICL76XX Series Low Power CMOS Operational Amplifiers
ICL7621.ICL7641.
ICL7642
ICL76XX Series Low Power CMOS Operational Amplifiers
ICL7650S
Super Chopper-Stabilized Operational Amplifier
NOTE: Bold "tYpe Designates a New Product from Harris.
1-12
LINEAR AND TELECOM PRODUCTS (Continued)
SAMPLE AND HOLD AMPLIFIER DATA SHEETS
HA-2420.
HA-2425
Fast Sample and Hold Amplifiers
HA-5320
High Speed Precision Monolithic Sample and Hold Amplifier
HA-5330
Very High Speed Precision Monolithic Sample and Hold Amplifier
HA-5340
High Speed. Low Distortion. Precision Monolithic Sample and Hold Amplifier
HA5350, HA5351
Ultra Fast (50ns) Sample and Hold Amplifiers
HA5352
Ultra Fast (50ns) Dual Sample and Hold Amplifier
SPECIAL ANALOG CIRCUITS DATA SHEETS
CA555. LM555
Timers for Timing Delays and Oscillator Applications in Commercial. Industrial and Military Equipment
CA1391. CA1394
TV Horizontal Processors
CA3089
FM IF System
CA3126
TV Chroma Processor
CA3189
FM IF System
CA3194
Single Chip PAL Luminance/Chroma Processor
CA3217
Single Chip TV Chroma/Luminance Processor
CA3256
BiMOS Analog Video Switch and Amplifier
CD22402
Sync Generator for TV Applications and Video Processing Systems
HA-2546
Wideband Two Quadrant Analog Multiplier
HA-2547
Wideband Two Quadrant Analog Multiplier
HA-2556
Wldeband Four Quadrant Voltage Output Analog Multiplier
HA-2557
Wldeband Four Quadrant Current Output Analog Multiplier
HA721 0
Low Power Crystal Oscillator
HFA5250
Ultra High-Speed Monolithic Pin Driver
ICL8013
Four Quadrant Analog Multiplier
ICL8038
Precision Waveform GeneratorNoltage Controlled Oscillator
ICL8048. IC18049
Log/Antilog Amplifiers
ICM7242
Long Range Fixed Timer
ICM7555. ICM7556
General Purpose Timers
TELECOMMUNICATIONS DATA SHEETS
CD221 00
CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating)
CD221 01. CD22102 CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory
CD22103A
CMOS HDB3 (High Density Bipolar 3) Transcoder for 2.048/8.448 Mbls Transmission Applications
CD22202. CD22203 5V Low Power DTMF Receiver
NOTE: Bold Type Designates a New Product from Harris.
1-13
LINEAR AND TELECOM PRODUCTS (Continued)
TELECOMMUNICATIONS DATA SHEETS
(Continued)
CD22204
5V Low Power Subscriber DTMF Receiver
CD22301
Monolithic Pan Repeater
CD22354A,
CD22357A
CMOS Single-Chip, Full-Feature PCM CODEC
CD22M3493
12 x 8 x 1 BIMOS-E Crosspoint Switch
CD22M3494
16 x 8 x 1 BiMOS-E Crosspoint Switch
CD22859
Monolithic Silicon COS/MOS Dual-Tone Multifrequency Tone Generator
CD74HC22106,
CD74HCT22106
aMOS 8 x 8 x 1 Crosspoint Switch with Memory Control
HC-5502B
SUC Subscriber Line Interface Circuit
HC-5504B
SUC Subscriber Line Interface Circuit
HC-5504DLC
SLiC Subscriber Line Interface Circuit
HC-5509A1
SLIC Subscriber Line Interface Circuit
HC-5509B
SLIC Subscriber Line Interface Circuit
HC-5524
SLiC Subscriber Line Interface Circuit
HC-5560
PCM Transcoder
HC-55536
Continuous Variable Slope Delta-Demodulator (CVSD)
HC-55564
Continuously Variable Slope Delta-Modulator (CVSD)
TRANSISTOR ARRAY DATA SHEETS
CA3018
General Purpose Transistor Arrays
CA3039
Diode Array
CA3045, CA3046
General Purpose N-P-N Transistor Arrays
CA3081, CA3082
General Purpose High Current N-P-N Transistor Arrays
CA3083
General Purpose High Current N-P-N Transistor Array
CA3086
General Purpose N-P-N Transistor Array
CA3096
N-P-N/P-N-P Transistor Array
CA3127
High Frequency N-P-N Transistor Array
CA3141
High-Voltage Diode Array For Commercial, Industrial & Military Applications
CA3146, CA3183
High-Voltage Transistor Arrays
CA3227, CA3246
High-Frequency N-P-N Transistor Arrays For Low-Power Applications at Frequencies Up to 1.5GHz
HFA3046, HFA3096, Ultra High Frequency Transistor Array
HFA3127, HFA3128
NOTE: Bold Type Designates a New Product from Harris.
1-14
DS~-------t
2
MULTIPLIERS
PAGE
MULTIPLIERS DATA SHEETS
HMA510
16 x 16-Bit CMOS Parallel Multiplier Accumulator ............................. .
2-3
HMA51 0/883
16 x 16-Bit CMOS Parallel Multiplier Accumulator ............................. .
2-10
HMU16, HMU17
16 x 16-Bit CMOS Parallel Multipliers ....................................... .
2-15
HMU161883
16 x 16-Bit CMOS Parallel Multiplier ........................................ .
2-25
HMU17/883
16 x 16-Bit CMOS Parallel Multiplier ........................................ .
2-31
2-1
U)
a:
w
:J
D.
5::I
:IE
HMA510
16 X 16-Bit CMOS Parallel
Multiplier Accumulator
January 1994
Features
Description
• 16 x 16-bit Parallel Multiplication with Accumulation to
a 35-Bit Result
The HMA510 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier accumulator capable of operating at 45ns
clocked multiply-accumulate cycles. The 16-bit X and V
operands may be specified as either two's complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product. and preloading the accumulator registers from the external inputs.
• High-Speed (45ns) Multiply Accumulate Time
• Low Power CMOS Operation:
=
5001JA Maximum
- Iccop = 7.0mA Maximum at 1.0MHz
• HMA510 is Compatible with the CY7C510 and the
IDT721 0
- ICCSB
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit accumulator output
register is broken into three parts. The 16-bit least significant
product (LSP), the 16-bit most significant product (MSP).
and the 3-bit extended product (XTP) registers. The XTP
and MSP registers have dedicated output ports. while the
LSP register shares the V-inputs in a multiplexed fashion.
The entire 35-bit accumulator output register may be preloaded at any time through the use of the bidirectional output
ports and the preloaded control.
• Supports Two's Complement or Unsigned Magnitude
Operations
• TTL Compatible InputS/Outputs
• Three-State Outputs
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HMA510JC-45
OOC to +70oC
68 Lead PLCC
HMA510JC-55
OOC to +70oC
68 Lead PLCC
HMA510GC-55
OOC to +70oC
68 Lead PGA
Block Diagram
X0-1S
16
RND
TC
SUB
ACC
Y0-1S PO-1S
16
PRELOAD
CLKP
OEM ______---'-P~16.;..-3.;..1;..J
OEC
---------------1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
2-3
File Number
2806.2
HMA510
Pinouts
HMA510 PLCC
VOl V1/
X14 X13X12X11 X10 X9 X8 XT X6 X5 X4 X3
X2 Xl
XO
PO P1
•
X15
Y2/ P2
OEL
V31 P3
RND
Y41 P4
SUB
Y5/P5
ACC
Y6/P6
CLIO(
Y7! P7
ClKY
GND
VCC
GND
68 lEAD PLCC
vcc
Y81 P6
TOPVIf3N
vcc
Y91 P9
vcc
Y10/P10
TC
Y11/ P11
OEX
Y12/ P12
PREl
Y131 P13
OEM
Y14/ P14
ClKP
Y15/ P15
P16
P34
27 28 29 30 31
32 33 34 35 36 37 38 39 40 41
42 43
P33 P32 P3l P3D P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17
HMA51 0 CERAMIC PGA
NiC
11
10
6
X15
-
ACC
ClKY
TC
PREL
ClKP
P33
SUB
CLIO(
VCC
-OEX
-OEM
P34
P32
N/C
X13
X14
Xll
X12
P30
P31
X9
Xl0
P26
P29
X7
X8
P26
P27
P24
P25
X5
OEl
RND
68 lEAD
PIN GRID ARRAY
X6
TOP VIEW
3
X3
X4
P22
P23
Xl
X2
P20
P21
VOl
PO
XO
P18
P19
P17
N/C
A
Yll
Pl
Y31
P3
Y51
P5
Y71
P7
Y81
P8
Y10/
Pl0
Y12/
P12
Y14/
P14
P16
V21
P2
Y41
P4
Y61
P6
GND
V91
P9
Vl1/
Pll
V131
P13
Y15!
P15
N/C
B
C
D
G
H
2-4
K
HMA510
Pin Descriptions
NAME
PLCC
PIN NUMBER
VCC
17-20
TYPE
DESCRIPTION
The +5V power supply pins. 0.1 ~F capacitors between the VCC and GND pins are
recommended.
GND
53,54
XO-X15
1-10,63-68
I
The device ground.
X-Input Data. These 16 data inputs provide the multiplicand which may be in two's
complement or unsigned magnitude format.
YO-Y15/
PO-P15
45-52,55-62
I/O
Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which
may be in two's complement or unsigned magnitude format. It may also be used for
output of the Least Significant Product (PO-P1 5) or for preloading the lSP
register.
P16-P3
29-44
I/O
MSP Output Data. This 16-Bit port is used to provide the Most Significant Product
Output (P16-P31 ).It may also be used to preload the MSP register.
P32-P34
26-28
I/O
XTP Output Data. This 3-Bit port is used to provide the Extended Product Output
(P32-P34).lt may also be used to preload the XTP register.
TC
21
I
Two's Complement Control. Input data is interpreted as two's complement when
this control is HIGH. A LOW indicates the data is to be interpreted as unsigned
magnitude format. This control is latched on the rising edge of CLKX or CLKY.
ACC
14
I
Accumulate Control. When this control is HIGH, the accumulator output register
contents are added to or subtracted from the current product, and the result
is stored back into the accumulator output register.
When lOW, the product is loaded into the accumulator output register overwriting
the current contents. This control is also latched on the rising edge of CLKX or
ClKY.
SUB
13
I
Subtract Control. When both SUB and ACC are HIGH, the accumulator register
contents are subtracted from the current product. When ACC is HIGH and SUB is
lOW, the accumulator register contents and the current product are summed. The
SUB control input is latched on the rising edge of ClKX or ClKY.
RND
12
I
Round Control. When this control is HIGH, a one is added to the most significant
bit of the lSP. When lOW, the product is unchanged.
PREl
23
I
Preload Control. When this control is HIGH, the three bidirectional ports may be
used to preload the accumulator registers. The three-state controls (OEX, OEM,
OEl) must be HIGH, and the data will be preloaded on the rising edge of ClKP.
When this control is lOW, the accumulator registers function in a normal manner.
OEl
11
I
Y-lnput/lSP Output Port Three-state Control. When OEl is HIGH, the output
drivers are in the high impedance state. This state is required for V-data input
or preloading the lSP register. When OEl is lOW, the port is enabled for lSP
output.
OEM
24
I
MSP Output Port Three-state Control. A lOW on this control line enables the port
for output. When OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP register.
OEX
22
I
XTP Output Port Three-state Control. A lOW on this control line enables the port
for output. When OEX is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the XTP register.
ClKX
15
I
X-Register Clock. The rising edge of this clock latches the X-data input register
along with the TC, ACC, SUB and RND inputs.
ClKY
16
I
V-Register Clock. The rising edge of this clock latches the V-data input register
along with the TC, ACC, SUB and RND inputs.
ClKP
25
I
Product Register Clock. The rising edge of ClKP latches the lSP, MSP and XTP
registers. If the preload control is active, the data on the I/O ports is loaded into
these registers. If preload is not active, the accumulated product is loaded into the
the registers.
2-5
HMA510
Functional Description
PRELOAD FUNCTION TABLE
The HMA510 is a high speed 16 x 16-bit multiplier
accumulator (MAC). It consists of a 16-bit parallel multiplier
follower by a 35-bit accumulator. All inputs and outputs are
registered and are latched on the rising edge of the
associated clock signal. The HMA510 is divided into four
sections: the input section, the multiplier array, the
accumulator and the output/preload section.
OUTPUT REGISTERS
PREL
OEX
OEM
0Ei:
XTP
MSP
LSP
0
0
0
0
Q
Q
Q
0
0
0
1
Q
Q
Z
0
0
1
0
Q
Z
Q
0
0
1
1
Q
Z
Z
0
1
0
0
Z
Q
Q
0
1
0
1
Z
Q
z
0
1
1
0
Z
Z
Q
0
1
1
1
Z
Z
Z
1
0
0
0
Z
Z
Z
1
0
0
1
Z
Z
PL
1
0
1
0
Z
PL
Z
1
0
1
1
Z
PL
PL
1
1
0
0
PL
Z
Z
1
1
0
1
PL
Z
PL
1
1
1
0
PL
PL
Z
1
1
1
1
PL
PL
PL
The input section has two 16-bit operand input registers for
the X and Y operands which are latched on the rising edge
of CLKX and CLKY respectively. A four bit control register
(TC, RND, ACC, SUB) is also included and is latched from
either of the input clock signals.
The 16 x 16 multiplier array produces the 32-bit product of
the input operands. Two's complement or unsigned
magnitude operation can be selected by the use of the TC
control. The 32-bit result may also be rounded through the
use of the RND control. In this case, a '1' is added to the
MSB of the LSP (bit P15). The 32-bit product is zero-filled
or sign-extened as appropriate and passed as a 35-bit
number to the accumulator section.
The accumulator functions are controlled by the ACC, SUB
and PREL control inputs. Four functions may be selected:
the accumulator may be loaded with the current product;
the product may be added to the accumulator contents; the
accumulator contents may be subtracted from the current
product; or the accumulator may be loaded from the
bidirectional ports. The accumulator registers are updated
at the rising edge of the CLKP signal.
Z
= Output Buffers at High Impedance (Disabled).
Q = Output Buffers at LOW Impedance. Contents of Output Register
Available Through Output Ports.
PL
The output/preload section contains the accumulator/
output register and the bidirectional ports. This section is
controlled by the signals PREL, OEX, OEM and OEL. When
PREL is high, the output buffers are in a high impedance
state. When one of the controls OEX, OEM or OEL are also
high, data present at the outputs will be preloaded into the
associated register on the rising edge of CLKP. When PREL
is low, the signals OEX, OEM and OEL are enable controls
for their respective three-state output ports.
= Output
disabled. Preload data supplied to the output pins will be
loaded into the register at the rising edge of CLKP.
ACCUMULATOR FUNCTION TABLE
2-6
PREL
ACC
SUB
P
L
L
X
Q
Load
OPERATION
L
H
L
Q
Add
L
H
H
Q
Subtract
H
X
X
PL
Preload
HMA510
INPUT FORMATS
Fractional Two's Complement Input
x
y
6
2
4
1
115 14 13 12 11 10
_20 2- 1 2-2 2-3 2-4 2- 5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
(S.gn)
°
6
4
115 14 13 12 11 10
01
_20 2-1 2-2 2-3 2-4 2- 5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-15
(S.gn)
Integer Two's Complement Input
x
115
14 13
12 11
y
6
10
4
01 115
_2 '5 2 '4 213 2'2 2" 210 29 28 27 26 2 5 24 2 3 22
(S.gn)
2'
20
14 13
12 11
10
4
01
-215 214 213 212 211 210 29 28 27 26 25 24 2 3 22
(S.gn)
2'
20
Unsigned Fractional Input
x
y
6
4
14 13 12 11 10 9
01
2-12-22-32-42-52-62-72-82-92-102-112-122-132-142-152-16
Lll_5_1_4_13_1_2_1_1_10_ _
9 ____
6 ___
4 _ _ _ _1_o--'1 115
2-12-22-32-42-52-62-72-82-9 2-102-112-122-132-142-152-16
Unsigned Integer Input
x
y
Lll_5_1_4_13_1_2_1_1_10_ _ _ _ _ _ _ _4_ _ _ _ _o--'1 115
215 2'4 213 212 2" 210 29
28 27
26 25 24 23
22
21
20
14 13
12 11
4
10
215 214 213 212 211 210 29 28
27
26 25
24 23
22
2'
01
20
OUTPUT FORMATS
Two's Complement Fractional Output
XTP
MSP
LSP
134 333211313029 28 27 26 25 24 23 22 21 20
_242322
19
18
17
161115
21202-12-22-32-42-52-62-72-82-92-10 2-11 2-122-132-14
14
13
12
11
10
9
4
0
I
2-152-162-172-182-192-202-212-222-232-242-252-26 2-27 2-28 2-29 2-30
(Sign)
Two's Complement Integer Output
XTP
134
MSP
33 321131
_234 233 232
(Sign)
LSP
30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13
231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
12
11
10 9 8 7 6 5 4 3 2 1 0
I
215 214 213 212 211 210 29 28 27 26 25 24 23 22 2' 20
Unsigned Fractional Output
XTP
MSP
134333211313029282726252423 22
LSP
21
20
19
18
17
161115
14
13
12
11
10
9
4
0
I
222' 20 2-12-22-32-42-52-62-72-82-92-10 2-11 2-122-13 2-14 2-15 2-16 2-172-182-192-202-212-222-232-242-252-262-272-28 2-29 2-30 2-31 2-32
Unsigned Integer Output
XTP
MSP
134 33 321131
234 233 232
30 29 28 27 26 25 24 23 22 21
LSP
20 19 18 17 161115 14 13
231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
2·7
12 11 10 9 8 7 6 5 4 3 2 1 01
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
Specifications HMA51 0
Absolute Maximum Ratings
Operating Conditions
Supply Voltage ..•...•....••...••...•..•.....•....•••.. +8.0V
Input, Output or I/O Voltage Applied •... G ND -0.5V to VCC +0.5V
Storage Temperature Range ..••...•.....••.. -65 0 C to +150 0 C
Gate Count •••...•..•.••........•••....•...•....• 4800 Gates
Junction Temperature •..•........ 1500 C (PLCC), +175 0C (PGA)
Lead Temperature (Soldering, Ten Seconds) •.•.•.•..•.• +300 0 C
ESD Classification .•..........•........•.....•....•... Class 1
Operating Voltage Range •..•.•....•......... +4.75V to +5.25V
Operating Temperature Range .•....•.......•.... OoC to +70 0 C
D.C. Electrical Specifications
PARAMETER
Reliability Information
aja .......•••••........... 43.2 0 C/W (PLCC), 42.69 0 C/W (PGA)
ajc ...••..•...•..••..•••..• 15.1 0C/W (PLCC), 1 O.Ooc/W (PGA)
Maximum Package Power Dissipation at 70 0 C ...... 1.7W (PLCC)
2.46/W (PGA)
(Vcc = 5.0V ±5%, TA = OOC to +70°C)
MAX
UNITS
TEST CONDITIONS
SYMBOL
MIN
Logical One Input Voltage
VIH
2.0
-
V
VCC= 5.25V
Logical Zero InputVoltage
VIL
-
0.8
V
VCC= 4.75V
Output HIGH Voltage
VOH
2.6
-
V
10H = -400~A, VCC = 4.75V
Output LOW Voltage
VOL
-
0.4
V
10L = +4.0mA, VCC = 4.75V
II
-10
10
~
VIN = VCC or GND, VCC = 5.25V
Output or I/O Leakage Current
10
-10
10
~A
VOUT = VCC or GND, VCC = 5.25V
Standby Power Supply Current
ICCSB
500
~A
VIN = VCC or GND, VCC = 5.25V, Outputs Open
Operating Power Supply Current
ICCOp
-
7.0
mA
f = 1.0MHz, VIN = VCC or GND
VCC = 5.25V (Note 1)
SYMBOL
MIN
MAX
UNITS
CIN
-
10
pF
10
pF
15
pF
Input Leakage Current
Capacitance
(TA = +250 C, Note 2)
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
COUT
CliO
TEST CONDITIONS
FREQ = 1 MHz, VCC = Open all Measurements
are Referenced to Device Ground.
NOTES:
,. Operating Supply Current is proportional to frequency, typical rating is
5.0mAiMHz.
A.C. Electrical Specifications
PARAMETER
2. Not tested, but characterized at initial deSign and at major process/design
changes.
(VCC = 5.0V ±5%, TA = OOC to +700 C)
HMA51 0-45
HMA51 0-55
SYMBOL
MIN
MAX
MIN
MAX
UNITS
TMA
45
55
ns
25
-
30
ns
25
-
30
ns
Note 1
25
-
30
ns
Note 1
20
-
ns
2
-
ns
3-State Enable Time
TENA
3-State Disable Time
TDIS
-
Input Setup Time
TS
18
Input Hold Time
TH
2
TpWH
15
-
20
-
Multiply Accumulate Time
Output Delay
Clock High Pulse Width
TD
TpWL
15
-
Output Rise Time
TR
8
Output Fall Time
TF
-
Clock Low Pulse Width
8
20
TEST CONDITIONS
-
ns
8
ns
From 0.8V to 2.0V
8
ns
From 2.0V to 0.8V
ns
NOTES:
1. Transition is measured at ±200mV from steady state voltage with loading
specffied in A.C. Test Circuit; V, = '.5V, R, = soon and CL = 40pF.
2. For A.C. Test load, refer to A.C. Test Circuit with V, = 2.4V, R, =
and CL = 40pF.
CAUTION: These devices are sensitive to electrostatiC discharge. Proper I.C. handling procedures should be followed.
2·8
soon
HMA510
A.C. Test Circuit
A.C. Testing Input, Output Waveforms
a::
--1-.5V---..7('-_ _ _ _ _ _
A.C. Testing:
"'Includes Stray and Jig Capacitance
.J~,..-1.-5V-- : : :
All Parameters tested as per test circuit.
Input rise and fall times are driven at 1nsN.
Timing Diagram
SET-UP AND HOLD TIME
DATA
INPUT
) ()()()O()()() ( ~:~
500()()()o(
I
THREE STATE CONTROL
TS
TH
I
THREE
STATE
OV
CONTROL
~~~3~ =============c=-.~~.=.~.=============~~~
OUTPUT - - - - - " "
THREE
STATE
HMA510 TIMING DIAGRAM
HIGH IMPEDANCE
)--------(1
PRELOAD TIMING DIAGRAM
TpWH
CLKP _ _ _/1
PREl
OEX
OEM
OEl
OUTPUT'7~~jt~~~~~~V'~~~~J
PINS
2-9
HMA51 0/883
16 X 16-Bit CMOS Parallel
Multiplier Accumulator
January 1994
Features
Description
• This Circuit Is Processed in Accordance to MIL-STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HMA510/883 is a high speed, low power CMOS 16 x
16·bit parallel multiplier accumulator capable of operating at
55ns clocked multiply·accumulate cycles. The 16·bit X and Y
operands may be specified as either two's complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product. adding or subtracting
the accumulator contents and the current product. and preloading the accumulator registers from the external inputs.
• 16 x 16-blt Parallel Multiplication with Accumulation to
a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- ICCSB = 500ilA Maximum
- Iccop = 7.0mA Maximum at 1.0MHz
• HMA5101883 is Compatible with the CY7C510 and the
IDT721 0
• Supports Two's Complement or UnSigned Magnitude
Operations
• Three-State Outputs
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HMA510GM·551883
·55°C to +125°C.
68 Lead PGA
HMA510GM-65/883
·55°C to +125°C
68 Lead PGA
HMA510GM·751883
·55°C to +125°C
68 Lead PGA
All inputs and outputs are registered. The registers are all
positive edge triggered. and are latched on the rising edge of
the associated clock signal. The 35·bit accumulator output
register is broken into three parts. The 16·bit least significant
product (LSP). the 16·bit most significant product (MSP).
and the 3·bit extended product (XTP) registers. The XTP
and MSP registers have dedicated output ports. while the
LSP register shares the Y·inputs in a multiplexed fashion.
The entire 35·bit accumulator output register may be pre·
loaded at any time through the use of the bidirectional output
ports and the preloaded control.
Block Diagram
XO·15
RND
SUB
YO-15 PO-15
PRELOAD
CLKP
Oei: _ _ _ _ _ _ _ _ _ _ _ _ _......J
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper LC. Handling Procedures.
Copyright © Harris Corporation 1994
2-10
File Number
2807.2
Specifications HMA510/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage ........................................ +8.0V
Input or Output Voltage Applied ........ G ND-O.SV to VCc+O.SV
Storage Temperature Range .•.........••. '" -6S o C to +1S0 0 C
Junction Temperature ................................ +17So C
Lead Temperature (Soldering 10 sec) ....•.••.•.•....... 3000C
ESD Classification .................................... Class 1
Thermal Resistance
0ja
0jc
Ceramic PGA Package. • • . • . . . • . . • • . • • • .. 43 0 C/W 100 C/W
Maximum Package Power Dissipation at +12So C
Ceramic PGA Package ................ , ........... 1.17 Watt
Gate Count '" ................................... 4800 Gates
CAUTION: Stresses above those listed in l'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only fating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ....................... +4.SV to +S.SV
Operating Temperature Range ........•.....• -SSoC to +12S o C
TABLE 1. HMAS10/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Logical One Input
Voltage
VIH
VCC=S.SV
1,2,3
-SSoC ~ TA ~ +12S o C
2.2
-
V
Logical Zero Input
Voltage
VIL
VCC=4.SV
1,2,3
-SSoC :::TA::: +12So C
-
0.8
V
IOH=-400~A
1,2,3
-SSoC ~TA ~ +12SoC
2.6
-
V
IOL=+4.0mA
VCC = 4.SV(Note 1)
1,2,3
-SSoC :::TA::: +12SoC
-
0.4
V
VIN = VCC or GND
VCC= S.SV
1,2,3
-SSoC ::: TA ~ +12S o C
-10
+10
"A
Output HIGH Voltage
VOH
VCC = 4.SV (Note 1)
Output LOW Voltage
VOL
Input Leakage Current
II
Output or I/O Leakage
Current
10
VOUT = VCC or GND
VCC=S.SV
1,2,3
-SSoC ~TA ~ +12SoC
-10
+10
"A
Standby Power Supply
Current
ICCSS
VIN = VCC or GND,
VCC = S.SV, Outputs
Open
1,2,3
-SSoC ::: TA::: +12SoC
-
SOO
"A
Operating Power
Supply Current
ICCOp
f= 1.0MHz,
VIN=VCCorGND
VCC = S.SV (Note 2)
1,2,3
-SSoC :::::TA::::: +12SoC
-
7.0
mA
7,8
-SSoC < TA < +12So C
-
-
Functional Test
FT
(Note 3)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency. typical rating
IS
3. Tested as follows: f = 1MHz. VIH (clock inputs) = 3.2V. VIH (all other
Inputs) = 2.6V. VIL = O.4V. VOH ~ 1.5V. and VOL $ 1.SV.
5mA/MHz.
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Ie handling procedures should be followed.
2-11
Specifications HMA51 0/883
TABLE 2. HMA51 0/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
(NOTE 1)
CONDITIONS
GROUPA
SUBGROUPS
-55
-65
PARAMETER
SYMBOL
TEMPERATURE
MIN
Multiply
Accumulate Time
TMA
9,10,11
-550C :5rA~ +125 0 C
-
55
-
65
-
75
ns
Input Setup
Time
TS
9,10,11
-550C ::;TA.:5 +125 0 C
20
-
25
-
25
-
ns
Clock HIGH
Pulse Width
TpWH
9,10,11
-550C,5TA~+1250C
20
-
25
-
25
-
ns
Clock LOW
Pulse Width
TpWL
9,10,11
-550C~TA~+1250C
20
-
25
-
25
-
ns
9,10,11
-550 C,5TA5 +125 0 C
-
30
-
35
ns
-550C,5 TA 5. +125 0 C
-
30
-
35
9,10,11
30
-
35
ns
Output Delay
TD
3-State
EnableTime
TENA
(Note 2)
NOTES:
1. AC Testing as follows: VCC = 4.SV and S.SV. Input levels OVand 3.0V (OV
and 3.2V for clock inputs). Timing reference levels = 1.SV, Output load per
test load circuit, with V1 = 2.4V, R1 = soon and CL = 40pF.
MAX MIN
-75
MAX MIN
MAX UNITS
2. Transition is measured at ±20QmV from steady state voltage, Output
loading per test load circuit, with V1 = 1.5V. Rl = 500n and CL = 40pF.
TABLE 3. HMA510/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
-55
-65
MAX MIN
-75
MAX MIN
MAX UNITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
MIN
Input Capacitance
CIN
VCC=Open,
f= lMHz All
measurements are
referenced to
device GND.
1
TA=+250C
-
10
-
10
-
10
pF
1
TA=+250C
-
10
-
10
-
10
pF
Output Capacitance
COUT
I/O Capacitance
CI/O
1
TA=+250C
-
15
-
15
-
15
pF
Input Hold Time
TH
1
-550C,5TA5.+1250C
3
-
3
-
3
-
ns
TDIS
1
-550C~TAS: +125 0 C
-
30
-
30
-
30
ns
1
-550C :5TA~ +125 0 C
-
10
-
10
ns
1
-
10
-550 C,5 TA~ +125 0 C
10
ns
3-State Disable
Time
Output Rise Time
TR
Output Fall Time
TF
From 0.8V to 2.0V
From 2.0VtoO.8V
10
10
NOTE:
1. The parameters listed in Table 3 are controlled via design or process pa~
ramalers and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2,3, 8A,8B, 10,11
-
1,2,3,7, 8A, 8B, 9,10,11
Samples/5005
1,7,9
Group A
GroupsC&D
CAUTION: These devices
are sensitive to electrostatic discharge. Proper Ie handling procedures should be followed.
2-12
HMA510/883
Burn-In Circuit
N/C
x,.
RND
ACC
CLKY
TC
PREL
CLKP
p.a
x,.
x,.
Oe:
SUB
CLKX
VCC
OEX
OEM
PM
P32
HlC
X11
X12
P30
pa'
xo
x'o
poa
PO,
X1
xa
poa
P07
po.
po.
11
'0
X5
68 LEAD
PIN GRID ARRAY
X8
TOPIfIEW
4
xa
X4
poo
poa
x,
xo
P20
PO,
VO/
PO
xo
P'8
P'O
P17
HlC
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
VB!
P8
V'OI
P'O
Y12/
Y14/
P,O
P,.
P18
va/
po
GND
VOl
PO
Y11/
P11
V'3/
P"
V'5/
P,.
HlC
D
E
G
H
V3/
pa
V5/
P5
VO/
PO
V4/
P.
C
A
PGA
PIN
PIN
NAME
V7/
P7
V1/
P'
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
K
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
86
X6
F1
F1
Y9IP9
F2
K7
P26
VCC/2
E11
ACC
F1
A6
X5
F2
G2
Y10/P10
F3
L7
P27
VCC/2
010
SU8
F2
85
X4
F3
G1
Y11/P11
F5
K8
P28
VCC/2
011
RND
F3
AS
X3
F4
H2
Y12/P12
F4
L8
P29
VCC/2
C10
OEL
VCC
84
X2
F5
H1
Y13/P13
F4
K9
P30
VCC12
C11
X15
F8
A4
X1
F6
J2
Y14/P14
F8
19
P31
VCC/2
810
X14
F9
83
XO
F7
J1
Y15/P15
F9
K10
P32
VCC12
A10
X13
F10
A3
YOIPO
F8
K2
P16
VCC/2
K11
P33
VCC/2
89
X12
F11
8L
Y1IP1
F9
L2
P17
VCC/2
J10
P34
VCC/2
A9
X11
F12
81
Y2IP2
F10
K3
P18
VCC/2
J11
CLKP
FO
88
X10
F13
C2
Y3IP3
F11
L3
P19
VCC/2
H10
OEM
GND
AS
X9
F14
C1
Y4/P4
F12
K4
P20
VCC/2
H11
PREL
F6
87
X8
F15
02
Y5/P5
F13
L4
P21
VCC/2
G10
OEX
GND
A7
X7
F7
01
Y6IP6
F14
K5
P22
VCC/2
G11
TC
F5
A2
N.C.
N.C.
E2
Y7/P7
F15
L5
P23
VCC/2
F10
VCC
VCC
K1
N.C.
N.C.
E1
GND
GND
K6
P24
VCC/2
F11
CLKY
FO
L10
N.C.
N.C.
F2
Y8IP8
F1
L8
P25
VCC/2
E10
CLKX
FO
811
N.C.
N.C.
NOTES:
1. Vee - 5.5V +O.5W-o.OV with 0.1 pF dacoupllng capacHor to GND
2. FO = 100kHz, F1 = FO/2, F2 - F1/2, ...••••••, 10%
4. 47kO load r••istore used on all pins except Vee and GND (Pin-Grid
identifiers F10, G10, G11 and H11)
3. VIH • Vee - 1V ± 0.5V (Min), VIL = O.8V (Max)
2-13
HMA5101883
Die Characteristics
DIE DIMENSIONS:
184 x 176 x 19± 1mils
METALUZATION:
Type: Si - AI or Si-AI-Cu
Thickness: akA
GLASSIVAnON:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY: 0.9 x 105Ncm2
Metallization Mask Layout
HMA5101883
!!:
.. .
;:
p
..
~ ...~
= = ,~, = =
~
=
..
>C
10 NC
Y3/P3 51
11
XIS
Y4/P4 58
12
OEL
Ys/PS 57
13
AND
Ya/PI 58
14 SUB
Y7/P7 55
15
ACC
18
CLKX
17
CLKY
18
Vee
II
Vee
20
TC
21
OEX
GND 54
GND 53
ye/PI 52
YI/PI 51
YIO/PIO 50
YII/PII 48
Y12/P12 48
22 'PREL
Y13/P13 47
23
,OeM
24
eLKP
25
P3C
YI4IPI4 4a
YIS/PIS 45
PI. 44
l!:
EE:
r e ~ :: :
2-14
HMU16, HMU17
16 X 16-Bit CMOS Parallel Multipliers
January 1994
Features
Description
• 16 x 16-Blt Parallel Multiplier with Full 32-Blt Product
The HMU16 and HMU17 are high speed, low power CMOS
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications.
• High-Speed (35ns) Clocked Multiply Time
• Low Power Operation:
- IcesB = 500~A Maximum
- leeop = 7.0mA Maximum at 1MHz
• Supports Two's Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• HMU16 Is Compatible with the AM29516, LMU16,
IDT7216 and the CY7C516
• HMU17 is Compatible with the AM29517, LMU17,
1DT1217 and the CY7C517
• TTL Compatible InputS/Outputs
• Three-State Outputs
Applications
• Digital Filtering
• Graphic Display Systems
• Image Processing
• Radar and Sonar
Additional inputs are provided for format adjustment and
rounding. The format adjust control (FA) allows the user to
select either a left shifted 31-bit product or a full 32-bit product, whereas the round control (RND) provides the capability
of rounding the most significant portion of the result.
The two halves of the product may be routed to a single
16-bit three-state output port via a multiplexer, and in addition, the LSP is connected to the V-input port through a separate three-state buffer.
• Speech Synthesis and Recognition
Ordering Information
TEMPERATURE
RANGE
Two 16-bit output registers are provided to hold the most
and least significant halves of the resuH (MSP and LSP). For
asynchronous output these registers may be made transparent through the use of the feedthrough control (FT).
The HMU16 has independent clocks (CLlO(, CLKY, CLKL,
CLKM) associated with each of these registers to maximize
throughput and simplify bus interfacing. The HMU17 has
only a single clock.!!:!.e!!,t (CL~ut makes use of three register enables (ENX, ENY and ENP). The ENX and ENY inputs
control the X and Y input registers, while ENP controls both
the MSP and LSP output registers. This configuration facilitates the use of the HMU17 for microprogrammed systems.
• Fast Fourier Transform Analysis
PART NUMBER
The X and Y operands along with their mode controls (TCX
and TCY) have 17-bit input registers. The mode controls
independently specify the operands as either two's complement or unsigned magnitude format, thereby allowing mixed
mode multiplication operations.
PACKAGE
HMU16JC-35
OOC to +70oC
68 Lead PLCC
HMU16JC-45
OOC to +70oC
68 Lead PLCC
HMU16GC-35
OOC to +70°C
68 Lead PGA
HMU16GC-45
OOC to +70oC
68 Lead PGA
HMU17JC-35
O°Cto +70oC
68 Lead PLCC
HMU17JC-45
OOCto +70oC
68 Lead PLCC
HMU17GC-35
OOCto +70oC
68 Lead PGA
HMU17GC-45
OOC to +70oC
68 Lead PGA
All outputs of the HMU16 and HMU17 multipliers also offer
three-state control for multiplexing results onto multiuse
busses.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
2-15
File Number
2803.2
HMU16/HMU17
Package Pinouts
CERAMIC 68 PIN GRID ARRAY (PGA)
TOP VIEW
N/C
x,a
X11
X'2
x,.
X9
11
'0
X"
RNO
TCY
vce
Tex
vcc
GNO
cUO(
FT
---
-FA
-OEP
ClKM
-
N/C
X'O
paDI
P,.
P31!
P"
X1
XB
P28/
P'2
P29/
XO
X6
P26/
P27/
Pll
xa
x.
x,
X2
-OEl
XO
-
GNO
(ENX)
MSPSEL
(ENP)
P'O
68 LEAD
PIN GRID ARRAY
TOPIIIEW
p,a
P24/
P8
P25/
P22/
P6
P23/
P201
P21/
P'
PO
P19!
P9
P1
ClKY
CLKl
P18/
(ENy)
(ClK)
P2
pa
Pt61
PO
PHI
P'
N/C
A
YOI
Y21
PO
P2
Y1/
P'
yal
pa
C
YOI
Y81
PO
P8
Yl0/
P'O
Y'2/
P'2
Y14/
P'
Y'I
Y71
Y91
Y11/
V13/
Y15/
P7
P9
Pll
Y'I
P,
o
p,a
P"
P'5
G
N/C
K
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
NC
X12
Xll
Xl0
X9
X8
X7
X6
X5
X4
P5, P21
X3
X2
Xl
XO
OEl
CLKL (ClK)
ClKY (ENY)
2-16
HMU16/HMU17
Functional Block Diagram
HMU16
XO -15 TCX
CL.KX
RND
TCY YO -151PO -15
--+----","""
C~-~----~--r-~
FA
FORMAT ADJUST
FT
UJ
CU € V OH
1.5V
1.5V
OV
-----VOL
* Includes Stray and Jig Capacitance
A.C. Testing: All parameters tested as per test circuit. Input rise and fall times
are driven at 1nsN.
Timing Diagram
SET-UP AND HOLD TIME
I~~~~ OOOOOO(
~~~~
THREE STATE CONTROL
)OOOOOOOC t~
I }S_TH.. I
THREE
STATE
CONTROL
ov
~--:========!~~
OUTPUT ------~
THREE
STATE
HMU16 TIMING DIAGRAM
HIGH IMPEDANCE
)-------<1
1.7V
1.3V
HMU17 TIMING DIAGRAM
I,TPWH. 1
CLK
ENX
ENY
~~~-----~----~
OUTPUT Y .,,;.::.~;::...:.::...::;~,"",-"..::.;,.~,,",,-.::.;:....g;:...;;:V1 '--_ __
MSPSEL~~~~~~~~~-L+-
____+-_ _
2·24
-----'I
1TSE
I
I
1 f------- TPWL
THE
,-,.--r-r-r"""""""""""""""""
~~~-~-~~~~~~~~~~
HMU16/883
16 X 16-Bit CMOS Parallel Multiplier
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL·STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HMU161883 is a high speed, low power CMOS 16x 16-bit
parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be
independently specified as either two's complement or
unsigned magnitude format, thereby allowing mixed mode
multiplication operations.
• 16 x 16·Blt Parallel Multiplier with Full 32·Bit Product
• High-Speed (45ns) Clocked Multiply Time
• Low Power CMOS Operation
• ICCSB = 500ilA Maximum
• Iccop 7.0mA Maximum at 1MHz
=
• HMU161883 Is Compatible with the AM29516, LMU16,
IOTI216, and the CY7C516
• Supports Two's Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
• Three-State Outputs
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HMU16GM·45/883
·55°C to +125°C
68 Lead PGA
HMU16GM-60/883
-55°C to +125°C
68 Lead PGA
Additional inputs are provided to accommodate format
adjustment and rounding of the 32-bit product. The Format
Adjust control allows the user to select a 31-bit product with
the sign bit replicated in the LSP. The Round control provides for rounding the most significant portion of the result
by adding one to the most significant bit of the LSP.
Two 16-bit output registers (MSP and LSP) are provided to
hold the most and least significant portions of the result,
respectively. These registers may be made transparent for
asynchronous operation through the use of the feedthrough
control (FT). The two halves of the product may be routed to
a single 16-bit three-state output port via the output mUltiplexer control, and in addition, the LSP is connected to the
V-input port through a separate three-state buffer.
The HMU16/883 utilizes independent clock signals (CLlO(,
CLKY, CLKL, CLKM) to latch the input operands and output
product registers. This configuration maximizes throughput
and simplifies bus interfacing. All outputs of the HMU161883
also offer three-state control for multiplexing onto multiuse
system busses.
Functional Diagram
XO-15 TCX
RND
TCY
YO-15JPO-15
CLIO( -_-~'"""
CLKY
-_------;--+--'
MULTIPUER ARRAY
OEP
----------4\,)
Pl6-311P0-15
CAUTION: These devices are sensHive to electroslatic discharge. Users should follow proper I.e. Handling Procedures.
Copyrighl © Harris Corporalion 1994
2-25
File Number
2804.2
Specifications HMU16/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage ........................................ +8.0V
Input or Output Voltage Applied •...••.. GND-0.5V to VCC+0.5V
Storage Temperature Range ..••..•.•........ -650C to +150 0 C
Junction Temperature ................................ +175 0 e
Lead Temperature (Soldering 10 sec) ................... 3000C
ESD Classification .................................... Class 1
Thermal Resistance
9ja
9jc
Ceramic PGA Package. . . . . . . . . • . .. 42.69 0 C/W 10.00 C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package ............................ 1.17 Watt
Gate Count ...................................... 4500 Gates
CAUTION: Stresses above those listed in "Abso/ute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ....................... +4.5V to +5.5V
Operating Temperature Range •...•......•... -550C to +125 0 C
TABLE 1. HMU16/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
2.2
-
V
Logical One Input
Voltage
VIH
VCC= 5.5V
1,2,3
-55°C :5 TA :5 +125 0 C
Logical Zero Input
Voltage
VIL
Vce =4.5V
1,2,3
-55°C ::;TA::; +1250 C
-
0.8
V
Output HIGH Voltage
VOH
10H =-400~A
Vec = 4.5V (Note 1)
1,2,3
-55°C::; TA :5 +125 0 C
2.6
-
V
Output LOW Voltage
VOL
IOL=+4.0mA
VCC = 4.5V (Note 1)
1,2,3
-55°C::; TA :5 +125 0C
-
0.4
V
Input Leakage Current
II
VIN=VCCorGND
Vec=5.5V
1,2,3
-550C ::;TA::; +125 0 C
-10
+10
~A
Output or I/O Leakage
Current
10
VOUT=VeeorGND
Vec=5.5V
1,2,3
-55°C.::: TA:5 +1250 C
-10
+10
~A
Standby Power Supply
Current
ICCSB
VIN = VCC or GND,
Vec = 5.5V, Outputs
Open
1,2,3
-55°C :5 TA'::: +125 0 C
-
500
~
Operating Power
Supply Current
ICCOp
f = 1.0MHz,
VIN = Vee or GND
Vee = 5.5V (Note 2)
1,2,3
-550C ::;TA::; +1250 C
-
7.0
mA
7,8
-55°C.::: TA'::: +125 0C
-
-
Functional Test
FT
(Note 3)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Operaltng Supply Current is proportional to frequency. tYPical ratmg is
3. Tested as follows: f = 1MHz, VIH (Clock Inputs) = 3.0. VIH (All other
Inputs) 2.6. VIL 0.4. VOH ? 1.5V. and VOL :$ 1.5V.
=
=
SmA/MHz.
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Ie handling
2·26
procedures should be followed.
Specifications HMU16/883
TABLE 2. HMU16/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranleed and 100% Tested
PARAMETER
SYMBOL
-45
(NOTE 1)
GROUP A
CONDITIONS SUBGROUPS
TEMPERATURE
:s
+125 0 C
-60
MIN
MAX
MIN
MAX
UNITS
-
70
-
90
ns
TMUC
9,10,11
-55°C ~ TA
Clocked MultiplyTime
TMC
9,10,11
-55°C ~TA:S +125 0 C
-
45
-
60
ns
X, Y, R NO Setup Time
TS
9,10,11
-550C~TA:s. +125 0 C
18
-
20
ns
Clock HIGH Pulse
Width
TpWH
9,10,11
-55°C
:s TA :s +1250 C
15
-
20
-
Clock LOW Pulse
Width
TpWL
9,10,11
-550C~TA
15
-
20
-
ns
TpDSEL
9,10,11
-55°C :sTA :s.+1250C
-
25
-
30
ns
Output Clock to P
TPDP
9,10,11
-55°C
-55°C
30
ns
3-State Enable Time
TENA
(Note 2)
9,10,11
-550C ~ TA :s. +125 0 C
25
-
ns
9,10,11
-
30
TpDY
:s TA :s + 125°C
:s TA :s + 125°C
25
Output Clock 1o Y
30
ns
Clock Low Hold Time
CLKXY Relative to
CLKML
THCL
(Note 3)
9,10,11
-550C:S TA:S +125 0 C
0
-
0
-
ns
Unclocked Multiply
Time
MSPSEL to Product
Out
:S+1250C
25
ns
NOTES:
1. AC Testing as follows: Vee = 4.SV and S.SV. Input levels OV and 3.0V,
Timing reference levels = 1.5V. Outpulload per test load circuil, with V1 =
2.4V. R, ~ 500n and CL ~ 40pF.
3. To ensure the correct product is entered tn the output registers, new data
may not be entered Into the input registers before the output registers
have been clocked.
2. Transition is measured at ± 200 mV from steady stale voltage, Output
loading per test load circuit, with V1 = 1.SV, R1 = 50
and CL = 40pF.
on
2-27
Specifications HMU 16/883
TABLE 3. HMU16/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
-45
PARAMETER
-60
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
CIN
VCC = Open, f= 1 MHz
All Measurements
are referenced to
deviceGND.
1
TA=+25 0 C
-
15
-
15
pF
1
TA=+250 C
-
10
-
10
pF
Input Capacitance
Output Capacitance
COUT
I/O Capacitance
X, Y, RND Hold Time
CI/O
1
TA=+25 0 C
-
10
-
10
pF
TH
1,2
-550 C :S TA :S + 1250 C
3
-
3
-
ns
TDIS
-
25
ns
10
-
30
-
10
ns
10
ns
:S
1,2,3
-55 0 C
Output Rise Time
TR
From 0.8V to 2.0V
1,2,4
-55 0 C It
parallel multiplier Ideal for fast, real time digital Signal processing
applications. The 16-/)lt X and Y oparends may be Independently
specified as either two's complement or unsigned magnitude for·
mat, thereby allOwing mixed mode multiplication operations.
• 16 x 16-BIt Parallel Multiplier with Full 32-Blt Product
• High-Speed (45ns) Clocked Multiply Time
• Low Power CMOS Operation:
- IcesB = 50011A Maximum
- Iccop. 7.0mA Maximum at 1MHz
• HMU17/883 Is Compatible with the AM29517, LMU17,
1017217, and the CY7C517
• Supports lWo's Complement, UnSigned Magnitude
and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
• Three-8tate Outputs
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HMU17GM-451883
-55"C to +125"0
68 Lead PGA
HMU17GM·6OI883
-55"C to +125°0
68LeadPGA
Additional Inputs are provided to accommodate format adjust·
ment and rounding of the 32-bit product. The Format Adjust
control allows the user the option of selecting a 31·blt product
with the sign bit replicated LSP. The Round control Is provided
to accommodate rounding of the most significant portion of the
result. This is accomplished by adding one to the most significant bit of the LSP.
Two 16-blt output registers (MSP and LSP) are provided to hold
the most and least significant portions of the result, respectively.
These registers may be made transparent for asynchronous
operation through the use of the feedthrough control (FT). The
two halves of the product may be routed to a single 16-bllthreestate output port via the output multiplexer contrOl, and in addition, the LSP Is connected to the V-input port through a separate
three-state buffer.
The HMU171883 utilizel!..!..!in.9!!...clock ~I (eLK) along with
three register enables (ENX, ENY, and ENP) to latch the ~
operands and the output product registers. The ENX and ENY
Inputs enable the X and Y Input registers, while ENP enables
both the LSP and MSP output registers. This configuration facilitates the use of the HMU17/883 for micro-programmed systems.
All outputs of the HMU17/883 also offer three-state control for
multiplexing onto multiuse system busses.
Functional Diagram
XD-1& lCX
CLK
....J+-===:tt:+-l--1
ENi-+-+-q-,
nw -+......._ _ _ _
0E\i
lCY YD-1S1PD-1&
RND
~-+_..J
----------<,..J
P16-311PD-15
CAUTION: These devices ara sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @Harris Corporation 1994
2-31
File Number
2805.2
Specifications HMU17/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage ••.....•...........•..•••....•.....••••. +8.0V
Input or Output Voltage Applied •.•.•••• GND-0.5V to VCC +0.5V
Storage Temperature Range ...•.•...•.•....• -650C to +1500 C
Junction Temperature .••.••••......••....•.....••.... +175 0 C
Lead Temperature (Soldering 10 sec) •...•.•....•••....• 3000C
ESD Classification ..••...•••.•.•..•....•.......••..... Class 1
Thermal Resistance
Sja
Sjc
Ceramic PGA Package. . .• •• . •• •• •• 42.69 0 C/W 10.00C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package ••............•..•••.•...... 1.17 Watt
Gate Count •...••.....•.•••..........••.••••.••.. 4500 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ....••.....••....•••... +4.5V to +5.5V
Operating Temperature Range ..........•.... -550C to +1250 C
TABLE 1. HMU16/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
GROUP A
SUBGROUPS
CONDITIONS
LIMITS
MIN
MAX
UNITS
2.2
-
V
-55°C :S TA :S +125 0 C
-
0.8
V
TEMPERATURE
Logical One Input
Voltage
VIH
VCC=5.5V
1,2,3
-55°C
Logical Zero Input
Voltage
VIL
VCC=4.5V
1,2,3
:s:TA :S + 125°C
Output HIGH Voltage
VOH
10H = -4001lA
VCC = 4.5V (Note 1)
1,2,3
-550C:S T A:S +125 0 C
2.6
-
V
Output LOW Voltage
VOL
IOL=+4.0mA
VCC = 4.5V (Note 1)
1,2,3
-550C:s TA:S +125 0 C
-
0.4
V
Input Leakage Current
II
VIN=VCCorGND
VCC= 5.5V
1,2,3
-55°C :STA:S +125 0 C
-10
+10
IlA
Output or I/O Leakage
Current
10
VOUT=VccorGND
VCC=5.5V
1,2,3
-550 C:STA:S+1250C
-10
+10
~A
Standby Power Supply
Current
Iccse
VIN = VCC or GND,
VCC = 5.5V, Outputs
Open
1,2,3
-55°C :S TA:S +1250 C
-
500
~A
Operating Power
Supply Current
ICCOp
f= 1.0MHz,
VIN = VCC or GND
VCC = 5.5V (Note 2)
1,2,3
-550C :STA:S +1250 C
-
7.0
mA
7,8
-55°C ::5TA::5 +1250 C
-
-
Functional Test
FT
(Note 3)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency, typical rating is
SmA/MHz.
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Ie
3. Tested as follows: f = 1 MHz, VIH (Clock Inputs) = 3.0. VIH (All other
inputs) = 2.6, VIL = 0.4. VOH ~ 1.5V. and VOL So 1.5V.
handling procedures should be followed.
2-32
Specifications HMU17/883
TABLE 2. HMU17/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
-45
(NOTE 1)
GROUPA
SYMBOL CONDITIONS SUBGROUPS
-60
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
-
70
-
90
ns
45
-
60
ns
ns
20
-
TMUC
9,10,11
-55 0 C,:STA,:S+1250C
Clocked MultiplyTime
TMC
9,10,11
-55°C < TA:S; +125 0 C
-
X, Y, RND Setup Time
TS
9,10,11
-550C <
><
)(
...
. .
><
;;;
!:!.
!::!.
:::.
><
:;;
!!!.
!!!.
!:!.
E:
e
0
;;:
!§;
~
><
.,
...
. .
.i
><
><
!!!.
><
<;
!!!.
0
;;:
;;;
e
(56) X13
(55) X14
(9) YO, PO
(54) X15
(10) V1, P1
(53)~
(ENX)
(52) RND
(11) V2, P2
(12) V3, P3
(51) TCX
(13) V4, P4
(50)TCV
(14) V5, P5
(15) V6, P6
(49) Vee
(16) Y7, P7
(48) VCC
(17) va, P8
(1a) VB, PB
(47) GND
(19) V10, P10
(20) V11, P11
(46) GND
(21) V12, P12
(45) MSPSEL
(22) V13. P13
(44) FT
(23) V14, P14
(43)
(24) V15. P15
FA
(42) DEP
(41)~M
(END)
co
Ii:
. .Ii: ..Ii: .. .. ... .. .... ... . ...... ...... ..
Ii:
Ii:
..;
II.
Vi ;; ;:::
t
!::!.
!::!.
!::!.
,.;
II.
0
p
II.
~
II.
II.
vi
II.
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3
ONE DIMENSIONAL FILTERS
PAGE
ONE DIMENSION ALTER DATA SHEETS
VO Filter . ....................................................... .
HSP43124
Serial
HSP43168
Dual FIR Filter ......................................................... .
3-18
HSP431681883
Dual FIR Filter ..........................•..•.•....•...............•.•...
3-35
HSP43216
HaHband Filter . ....................................................... .
3-43
HSP43220
Decimating Digital Filter ..............•.......•................•..........
3-60
a:
w
!J
HSP43220/883
Decimating Digital Filter ••............••••...••••.....•....•..•......•....
3-83
Q
HSP43481
Digital Filter .......•....•....••...••..........•.............•...........
3-90
HSP43481/883
Digital Filter ..•.•.......................................................
3-105
HSP43881
Digital Filter .....•.......................................•..............
3-110
HSP43881 1883
Digital Filter ........................•.......•...........................
3-125
HSP43891
Digital Filter .•...•...............••.••••.•..•••..•..•..••••.............
3-131
HSP43891 1883
Digital Filter •...•.•................•..•....••.•...•......•.•.•.........•
3-147
3-3
(I)
NOTE: Bold Type Designates a New Product from Harris.
3-1
u:
....
HSP43124
PRELIMINARY
Serial VO Filter
January 1994
Features
Description
• 45MHz Clock Rate
The Serial 110 Filter is a high performance filter engine that is
ideal for off loading the burden of filter processing from a
DSP microprocessor. It supports a variety of multistage filter
configurations based on a user programmable filter and
fixed coefficient halfband filters. These configurations
include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band
filters each decimate by a factor of two, and the FIR filter
decimates from one to eight. When all six filters are
selected, a maximum decimation of 256 is provided.
• 256 Tap Programmable FIR Filter
• 24-Blt Data. 32-Blt Coefficients
• Cascade of up to 5 Half Band Filters
• Decimation from 1 to 256
• TWo Pin Interface for Down Conversion by Fr;/4
• Multiplier for Mixing or Scaling Input with an External
Source
For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be
multiplied, or mixed, by a user supplied mix factor. A two pin
interface is provided for serially loading the mix factor from
an external source or selecting the mix factor from an onboard ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one
quarter of the sample rate, Fsl4. This allows the chip to function as a digital down converter when the filter stages are
configured as a low-pass filter.
• Serial 110 Compatible with Most DSP Microprocessors
Applications
• Low Cost FIR Riter
• Filter Co-Processor
• Digital Tuner
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
The serial interface for input and output data is compatible
with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface. This product is available in 28 pin
DIP and SOIC packages.
PACKAGE TYPE
HSP43124PC-45
O"C to +70"C
28 Lead Plastic DIP
HSP43124SC-45
O"C to +70"C
28 Lead SOIC
Block Diagram
DIN
•••
DOUT
SCLK
SYNCIN
MXIN
•••
SYNCOUT
CLKOUT
SYNCMX
CAUTION: These devICes are sensHive to electrostatic dIscharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993
3-3
File Number
3555.1
~
w
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ii:
Q
.,..
HSP43124
Pinout
28 LEAD PLASTIC DIP, SOIC
TOP VIEW
DIN
DOUT
SYNCOUT
CLKOUT
Vee
C7
C6
C5
C4
GND
C3
C2
C1
CO
3-4
HSP43124
Pin Description
DESCRIPTION
NAME
PDIP, SOIC PIN
TYPE
Vcc
7,14,24
GND
3, 19
-
DIN
28
I
Serial Data Input. The bit value present on this input is sampled on the rising edge
of SCLK. A "HIGH" on this input represents a "1", and a low on this input represents
"0". The word format and operation of serial interface are contained in the Data Input
Section.
SYNCIN
2
I
Data Sync. The HSP43124 is synchronized to the beginning of a new data word on
DIN when SCLK samples SYNCIN "HIGH" one SCLK before the first bit of the new
word. Note: SYNCIN should not maintain a "HIGH" state for longer than one SCLK
cycle.
SCLK
1
I
Serial Input CLK. The riSing edge of SCLK clocks data on DIN and MXIN into the
part. The following signals are synchronous to this clock: DIN, SYNCIN, MXIN,
SYNCMX.
MXIN
4
I
Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising
edge of SCLK. A "HIGH" on this input represents a "1", and a low on this input represents "0". Also used to specify the Weaver Modulator ROM output. Details on word
format and operation are contained in the Mix Factor Section.
SYNCMX
5
I
Mix Factor Sync. The HSP43124 IS synchronized to the beginning of a serially input mix
factor when SCLK samples SYNCMX "HIGH" one SCLK before the first bit of the new
mix factor. Note: SYNCMX should only pulse "HIGH" for one SCLK cycle. Also used to
specify Weaver Modulator ROM output.
FCLK
8
I
Filter Clock. The filter clock determines the processing speed of the Filter Compute
Engine. Clock rate requirements on FCLK for particular filter configurations IS discussed in the Filter Compute Engine Section. This clock may be asynchronous to the
serial input clock (SCLK). FSYNC# is synchronous to this clock.
FSYNC#
6
I
Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter
compute engine so that the data sample following the next SYNC IN cycle is the first
data sample into the filter structure. If a data stream is currently being input, the data
is "canceled" and the DIN pin is ignored until the next SYNC IN cycle occurs.
WR#
9
I
Write. The falling edge of WR# loads data present on CO-7 into the configuration or
coefficient register specified by the address on AO-2. The WR# signal IS asynchronous to all other clocks. Note: WR# should not be low when RD# is low.
RD#
10
I
Read. The falling edge of RD# accesses the control registers or coefficient RAM addressed by AO-2 and places the contents of that memory location on CO-7. When
RD# returns "HIGH" the CO-7 bus functions as an input bus. The RD# pin is asynchronous to all other clocks. Note: RD# should not be low when WR# is low.
AO-2
11,12,13
I
Address Bus. The AO-2 inputs are decoded on the falling edge of both RD# and
WR#. Table 1 shows the address map for the control registers.
C0-7
15,16,17,18,20,
21,22,23
1/0
Control and Coefficient bus. This bi-directional bus is used to access the control registers and coefficient RAM.
CLKOUT
25
0
Output Clock. Programmable bit clock for senal output. Note: assertion of
FILTSYNC# initializes OCLK to a high state.
SYNCOUT
26
0
Output Data Sync. SYNYOUT is asserted HIGH for one OCLK cycle before the first
bit of a new output sample is available on DOUT.
DOUT
27
0
Serial Data Output. The bit stream is synchronous to the rising edge of OCLK. See
the Serial Output Formatter section for additional details.
+5V Power Supply
Ground
3-5
HSP43124
.............................................................., ,,------- -----------------.-- --------------------- ------- --, ,. .......................,
!
: :
:::: FORMATTER
OUTPUT:
:
INPUT FORMATTER
: :
FILTER COMPUTE ENGINE
:
"
,"" ,
DIN
: :
:
~
57
, ...... -......... _-_ ... -----, ",'f,
"
,
,,
:
MULTIPLYI
: ::
:
:
ACCUMULATOR
",
",
,,
""
, f
:
::: :
,
HI
~====:r.~~;:,]:::,
,
:::
, ,
,
,,,
,,
~---------------- .. ---,,
,,,
,,,
,,
,,
,,,
,,
CONTROL
,,:
,,:
,,
,,
,,
,
,,
,,
,
,,
,_______
,
",
,f
MXIN
:
",
,,
SYNCMX
: ~:
SYNCOUT
CLKOUT
L...---Ir:-'" DOUT
_ _ _ _ _ _ J. _ _ _ _
..
A~2 ------------+---------------~~_+~--------~~------------~
C~7 +-----------+-----------------~_+~--------~~--------------~
WR. ------------+-------------------~~--------~~----------------~
RD.
FSYNC.
------------+---------------------~--------4_4_----------------~
------------+-------------------------------~
FCLK ------------+---------------------------------~
SCLK - - - - - - - - - - - '
FIGURE 1. SERIAL FILTER BLOCK DIAGRAM
Functional Description
Data is written to the control registers on the falling edge of the
WR# input. This requires that the address, Ao.2, and data, Co.7,
be set up to the falling edge of the WR# as shown in Figure 2.
Note: WR# should not be active low when RD# is active low.
The HSP43124 is a high performance digital filter designed
to process a data stream which is input serially. A second
serial input is provided for inputting mix factors which are
multiplied by the input samples as shown in Figure 1. The
result of this operation is passed to the Filter Compute
Engine for processing.
The Filter Compute Engine centers around a single multiplyl
accumulator (MAC). The MAC performs the sum-of-products
required by a particular filter configuration. The processing
rate of the MAC is determined by the filter clock, FCLK.
Increasing FCLK relative to the input sample rate increases
the length of filter that can be realized.
Data is read from the control registers on the falling edge of
the RD# input. The contents of a particular register are
accessed by setting up an address, AO-2, to the falling edge
of RD# as shown in Figure 2. The data is output on Co.7.
The data on CO-7 remains valid until RD# returns HIGH, at
which point the CO-7 bus is Three-Stated and functions as
an input. For proper operation, the address on AO-2 must be
held until RD# returns "high" as shown in Figure 2. Note:
RD# should not be active low when WR# is active low.
The filtered results are passed to the Output Formatter
where they are rounded or truncated to a user defined bit
width. The Output Formatter then generates the timing and
synchronization signals required to serially transmit the data
to an external device.
wRITEnMING
WRII
A0-2
C0-7
Filter Configuration
The HSP43124 is configured for operation by writing a
series of control registers. These registers are written
through a bidirectional interface which is also used for reading the control registers. The interface consists of an 8-bit
data bus, CO-7, a 3-bit address bus, AO-2, and read/write
lines, RD# and WR#. The address map for the control registers is shown in Table 1.
3-6
REAOnMING
ROIl
AO-2
C0-7
FIGURE 2. READIWRITE TIMING
HSP43124
TABLE 1. CONFIGURATION REGISTERS
ADDRESS
000
REGISTER DESCRIPTION
Filter Configuration
BIT
POSITIONS
2-0
BIT FUNCTION
Specifies the number of halfbands to use. Number ranges from 0 to 5.
Other values are invalid.
= Bypass.
3
FIR filter bypass bit. 0
4
Coefficient read enable. When set to 1, enables reading and disables
writing of coefficient RAM. Note: this bit must be set to 0 prior to writing
the Coefficient RAM.
7-5
FIR Decimation Rate. Range is 1-8 (8 = 000).
001
Programmable Filter Length
7-0
Number of Taps in the Programmable Filter. For even or odd symmetric
filters, values range from 4- 256, 1 to 3 are invalid, and. 0000000 =256.
For asymmetric filters, values range from 2 - 128.
010
Coefficient RAM Access
7-0
Coefficient RAM is loaded by multiple writes to this address. See Writing
Coefficients section for additional details.
011
Input Format
4-0
Number of bits in input data word, from 8 (01000) to 24 (11000). Values
outside the range of 8 - 32 are invalid.
5
6
7
100
Output Timing
4-0
5
101
Output Format
Filter Symmetry
111
Mix Factor Format
Unused
Number of FCLKS per OCLK. Range 1 to 32. (00000
1 =MSB First, 0
=32 FCLKS)
= LSB First.
6-7
Unused
4-0
Number of bits in output data word, from 8 to 32. A value of 32
sented by 00000, and values from 1 to 7 are invalid.
IS
repre-
5
Round Select. 0 = Round to Selected Number of Bits, 1 = Truncate.
6
=Two's Complement, 1 =Offset Binary.
Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling.
00 = Symmetric FIR Coefficients
01 = Non-Symmetric Coefficients
10 = Odd Symmetric FIR
7
110
=Two's Complement, 1 =Offset Binary.
Serial Format. 1 = MSB First, 0 = LSB First.
Number System. 0
1-0
Number System. 0
7-2
Unused
4-0
Number of bits in mix factor, from 8 (01000) to 24 (11000). Values outside the range of 8 - 32 are invalid.
5
Serial Format. 1 = MSB First, 0
6
Mix Factor Select. 1 = Senallnput, 0 =Weaver modulator look-up-table.
7
Unused
Writing Coefficients
The HSP43124 provides a register bank to store filter coefficients for configurations which use the programmable filter.
The register bank consists of 128 thirty-two-bit registers.
Each register is loaded by 4 one byte writes to the bidirectional interface used for loading the configuration registers.
The coefficients are loaded in order from least significant
byte (LSB) to most significant byte (MSB).
= LSB First.
The coefficient registers are loaded by first setting the coeffieient read enable bit to "0" (bit 4 of the Filter Configuration
Register). Nex1, coefficients are loaded by setting the A2.-0
address to 010 (binary) and writing one byte at a time as
shown in Figure 3. The down loaded bytes are stored in a
holding register until the 4th write cycle. On completion of
the fourth write cycle, the contents of the holding register are
loaded into the Coefficient RAM, and the write pointer is
incremented to the nex1 register. If the user attempts to write
3-7
HSP43124
more than 128 coefficients, the pointer halts at the 128th
register location, and writing is disabled. The coefficient
address pointer is reset when any other configuration register is written or read. Note: a new coefficient set may be
loaded during a filter calculation at the risk of corrupting output data until the load is complete.
• ••
WRII
AO-2
CQ.7
of length N, N/2 coefficients must be loaded if the filter length
is even, and (N+l)/2 coefficients must be loaded if the filter
length is odd. For example, a 17 tap symmetric filter would
require the loading of 9 coefficients. Enough storage is provided for a 256 tap symmetric filter.
~----:--A~Q.-2-=-01-0-(B-I-N-A"RY-)------ • • •
",,-LAST
FILTER TAP
------ ------FIRST COEFFICIENT
1-_ _ _+ OUTPUT
SECOND COEFFICIENT
FIGURE 5. THREE TAP TRANSVERSAL FILTER ARCHITECTURE
FIGURE 3. COEFFICIENT LOADING
The number of coefficients that must be loaded is dependent
on whether the coefficient set exhibits even symmetry, odd
symmetry, or asymmetry (see Figure 4).
EVEN SYMMETRIC
POINT
.
~
ODD LENGTH,
SYM~~TR~
EVEN LE_N...G_T,..H......,!.J........_
,
,
NOTE: Filters with even symmetric coefficients exhibit symmetry
about the center of the coefficient set. Most FIR filters have
coefficients which are symmetric in nature.
ODD SYMMETRIC
For asymmetric filters the entire coefficient set must be
loaded. The coefficients are loaded in order starting with the
first tap and ending with the final filter tap (see Figure 5 for
tap/coefficient association). Enough storage is provided for a
128 tap asymmetric filter.
Reading Coefficients
The coefficients are read from the storage registers one byte
at a time via CO-7 as shown in Figure 6. To read the coefficients, the user first sets the Coefficient Read Enable bit to 1
(bit 4 of Filter Configuration Register). Setting this bit resets
the RAM read pOinter and disables the RAM from being written. Next, with A2-0 010, multiple "high" to "low" transitions
of RD#, output the coefficients on CO-7, one byte at a time,
in the order they were written. Note: RD# should not be "low"
when WR# is "low".
=
RD#
•••
AO·2
-4-.:.........:;:::~:.::.:.::J.::~::.::.:J....______ • • •
0.1
NOTE: Odd symmetric coefficients have a coefficient envelope
which has the characteristics of an odd function (i.e. coefficients
which are equidistant from the center of the coefficient set are equal
in magnitude but opposite in sign). Coefficients designed to function
as a differentiator or Hilbert Transform exhibit these characteristics.
•••
CO-7
lSB
MSB
LSB
MSB
--------- --------FIRST COEFFICIENT
SECOND COEFFICIENT
FIGURE 6. COEFFICIENT READING
ASYMMETRIC
Data Input
NOTE: Asymmetric Coefficient sets exhibit no symmetry.
FIGURE 4. COEFFICIENT CHARACTERISTICS
For filters that exhibit either even or odd symmetry, only the
unique half of the coefficient set must be loaded. The coefficients are loaded in order starting with the first filter tap and
ending with the center tap. The coefficient associated with
the first tap is the first to be multiplied by an incoming data
sample as shown in Figure 5. For even/odd symmetric filters
Data is serially input to the HSP43124 through the DIN input.
On the riSing edge of SCLK, the bit value present at DIN is
clocked into the Variable Length Shift Register. The
beginning of a serial data word is designated by asserting
SYNCIN "high" one SCLK prior to the first data bit as shown
in Figure 7. On the following SCLK, the first data bit is
clocked into the Variable Length Shift Register. Data bits are
clocked into the shift register until the data word, of user
programmable length (8 to 24-bits), is complete. At this
pOint, the shifting of data into the register is disabled and its
contents are held until SYNCIN is asserted on the rising
3-8
HSP43124
given in Table 2. When SYNCIN is high on the rising edge of
SCLK, the output of the ROM is transferred to the Mix Factor
holding register, and the SYNCMX and MXIN inputs are
decoded to produce a new ROM output. As a result, there is
a latency of one SYNCIN cycle between when the SYNCMX
and MXIN inputs are decoded and when the ROM output is
loaded into the Mix Factor Holding register.
edge of SCLK. When this occurs, the contents of the
Variable Length Shift Register are transferred to the Input
Holding Register, and the shift register is enabled to accept
serial data on the following SCLK. The serial data word may
be two's complement or offset binary and may be input most
significant bit (MSB) first or least significant bit (LSB) first as
defined in the Input Format Register (see Table 1). If a data
word is specified to be less than 24-bits, the least significant
bits of the Input Holding Register are zeroed. Note: SYNCIN
should not be "high" for longer than one SCLK cycle.
SCLK
SYNCINI
TABLE 2. WEAVER MODULATOR ROM DECODING
SYNCMX
MXIN
MIX FACTOR
0
0
0
0
1
-1
1
0
0
1
1
1
-fl..I1J111nJl.n.nJ
~:
SYCNMX'
r--f\:
:~s-J
:~
M~:~~
Serial Multiplier
NOTE: Assumes data is being loaded LSB first.
The Serial Multiplier multiplies the Mix Factor Holding
register by the contents of the Input Holding register. The
multiplication cycle is initiated when SYNCIN is sampled
high by the rising edge of SCLK. This transfers the contents
of the Variable Length Shift register to the Input Holding
Register, and loads the output of the Mix Factor Holding
Register into the Serial Multipler. On subsequent SCLK's,
the contents of the Input Holding Register are shifted into the
Serial Multiplier for processing. When the last data bit is
shifted into the multiplier, the multiplication cycle is complete
and the result is written to the Register File on the next riSing
edge of FCLK.
FIGURE 7. SERIAL INPUT TIMING FOR EITHER DIN OR MXIN
INPUTS
Mix Factor
The HSP43124 provides a second serial interface for loading values which are multiplied by the input samples in the
serial multiplier. These values, or mix factors, are input using
the MXIN and SYNCMX pins. Aside from being used as a
serial input, this interface can also be used to select mix factors from the Weaver Modulator ROM. The mix factor source
is specified in the Mix Factor Format Register (see Table 1).
Note: data is passed unmodified through the serial multiplier
by selecting the Weaver Modulation ROM as the mix factor
source and tieing both SYNCMX and MXIN "high".
The synchronization between a data sample and the mix
factor it is to be multiplied by is dependent on which mix factor source is specified. For mix factors which are input serially, the mix factor is loaded concurrently with the data
sample is to be multiplied by (see Figure 8).
The procedure for loading mix factors serially is similar to
that for the loading of data via the DIN input. The bit value
present on MXIN is clocked into the Variable Length Shift
register by the rising edge of SCLK. The beginning of the
serial word is designated by the assertion of SYNCMX one
SCLK prior to the first bit of the serial word as shown in Figure 7. After the serial word has been clocked into the shift
register, the shifting of bits into the register is disabled and
its contents are held until the next assertion of SYNCMX.
When SYNCMX is asserted on the rising edge of SCLK, the
contents of the Variable Length Shift register are transferred
into the Mix Factor Holding Register. The parallel output of
the Mix Factor Holding Register feeds directly into the serial
multiplier. The mix factor data word is programmable in
length from 8 to 24-bits and may be input MSB or LSB first
as specified in the Mix Factor Format Register. If a data word
is specified to be less than 24-bits, the least significant bits
of the Mix Factor Holding Register are zeroed.
SCLK
SYNCIN
JU1.I1.•••~
r-\J-...
~
,
,
,
DIN~•••~
----::
.: ~
: .
I
:
SYNCMX
:--------I
:
xo
I
I
':
I\...L
...~
,
,
,
MXIN~•••~
---------MO
In configurations which use the Weaver Modulator ROM to
generate the mix factors, the MXIN and SYNCMX inputs
function as ROM addresses. These inputs are latched on the
rising edge of SCLK when SYNCIN is high as shown in Figure 9. The mapping of SYNCIN and MXIN to ROM outputs is
FIGURE 8. DATA/MIX FACTOR SYNCHRONIZATION FOR SERIALLY INPUT MIX FACTORS
NOTE: Figure 8 shows the loading of a data sample, XO, such that it
will be multiplied by a mix lactor designated by MO. For mix lactor bit
widths which are less than the Input bit Width, SYNCMX may be
asserted belore SYNCIN il deSired.
3-9
~
W
~
u::
....o
HSP43124
If the mix factor is generated by the Weaver Modulator ROM,
the mix factor must be specified on MXIN and SYNCMX one
SYNCIN before that which precedes the target data word
(see Figure 9).
Ol~--~--~~~~----'-~
,---~----~--~~~~~~~
~T\.'\.
-41.69831"""
ii
SCLKJ1..fl-tlJ1rl.f1-rLnJ
r-\.:
SYNCIN,
z
~
r-t\.;
:~
:~s--J
DIN~~
I
I
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SYC:::
X ; xSXX
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_ _ _;
I
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I
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~:~:?0~ \ \
~~:7\ ~
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-12S.09SI---+---+---t--+++-\-\iH
l
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,""."'
-166.7931---+---+--+--..IflILf-l
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o
0.0998
0.1996
0.2994
0.3992
0.4990
t=x : X*XXXXXX
FREQUENCY
FIGURE 10. COMPOSITE RESPONSE OF FIXED COEFFICIENT
HALFBAND FILTERS
MO
FIGURE 9. OATAlMIX FACTOR SYNCHRONIZATION WEAVER
MODULATOR MIX FACTORS
NOTE: Figure 9 shows the specification of a ROM based mix factor,
MO, so that it will be multiplied with the target data sample designated
by XO.
Filter Compute Engine
The Filter Compute Engine centers around a multiply accumulator which is used to perform the sum-ol-products
required for a variety of filtering configurations. These configurations include a cascade of up to 5 halfband filters, a
single symmetric filter of up to 256 taps, a Single asymmetric
filter of up to 128 taps, or a cascade of halfband filters followed by a programmable filter. The filter configuration is
specified by programming the Filter Configuration Register
(see Table 1).
The cascade of up to five halfband filters is an efficient decimating filter structure. Each fixed coefficient filter in the chain
introduces a decimation of two, and the aggregate decimation rate of the entire halfband filtering stage is given by
DECHB = 2(NUMBER OF HALFBAND FILTERS SELECTED).
Thus, a cascade of 3 halfband filters would decimate the
input sample stream by a factor of 8.
The frequency responses of the five filters is presented
graphically in Figure 10 and in tabular form in Table 3. The
transition band for the fifth halfband filter, HB5, is the narrowest while that for the first halfband filter, HB1, is the widest.
The cascade of the halfband filters always terminates with
HB5 and is preceded by filters in order of increasing transition bandwidth. For example, if the HSP43124 is configured
to operate with three halfbands, the chain of filters would
consist of HB3 followed by HB4 and terminated with HB5. If
only one halfband is selected, HB5 is used.
The coefficients for each of the halfband filters is given in
Table 4. These values are the 32-bit, two's complement,
integer representation of the filter coefficients. Scaling these
values by 2-31 yields the fractional two's complement
coefficients used to achieve unity gain in the Filter
Processor.
II a specific Irequency response is desired, a programmable
filter may be activated. The filter compute engine takes
advantage of symmetry in FIR coefficients is by summing
data samples sharing a common coefficient prior to
multiplication. In this manner, two filter taps are calculated
per multiply accumulate cycle. II an asymmetric filter is
specified, only one tap per multiply accumulate cycle is
calculated.
The processing rate of the Filter Compute Engine is
proportional to FCLK. As a result, the frequency of FCLK
must exceed a minimum value to insure that a filter
calculation is complete before the result is required for
output. In configurations which do not use decimation, one
input sample period is available for filter calculation before
an output is required. For configurations which employ
decimation, up to 256 input sample periods may be available
for filter calculation. The following equation specifies the
minimum FCLK rate required for configurations which use
the programmable filter as an FIR filter.
Min FCLK =(FsiDECHB )(TAPS/(2*DEC FIR ) + HB cLKS + 1)
In this equation Fs is the sample rate, TAPS is the number of
taps in the FIR filter (0 to 256), DEC F1R is the decimation rate
of the programmable FIR (1 to 8), and HBcLKS is a compute
clock factor based on the number of halfband filters in the
configuration (see Table 5). The term DEC HB is the aggregate decimation rate for the cascade of halfband filters (see
Table 5). For example, if the input sample rate is 800kHz, a
128 tap FIR filter with no decimation is selected, and a cascade of 2 halfband filters is used, a minimum FCLK rate of
19.6MHz would be required. Note: for configurations in
which the hallband filters are used, the FCLK rate must
exceed 14Fs.
3-10
HSP43124
TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS
.1
NORMALIZED
FREQUENCY
HALFBAND
HALFBAND
HALFBAND
HALFBAND
HALFBAND
112
.3
.4
.5
0.000000
-0.000000
0.007812
0.000000
0.000000
0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
0.015625
-0.000113
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
0.023438
-0.000677
-0.000006
-0.000000
-0.000000
-0.000000
0.031250
-0.002243
-0.000052
-0.000000
-0.000000
-0.000000
0.039062
-0.005569
-0.000227
-0.000000
-0.000000
0.000000
0.046875
-0.011596
-0.000719
-0.000001
0.000000
-0.000000
0.054688
-0.021433
-0.001859
-0.000009
-0.000000
-0.000000
0.062500
-0.036333
-0.004165
-0.000041
-0.000000
-0.000000
0.070312
-0.057670
-0.008391
-0.000149
-0.000001
-0.000000
0.078125
-0.086916
-0.015557
-0.000448
-0.000012
-0.000000
0.085938
-0.125619
-0.026983
-0.001175
-0.000066
-0.000000
0.093750
-0.175382
-0.044301
-0.002767
-0.000258
-0.000000
0.101562
-0.237843
-0.069457
-0.005963
-0.000815
-0.000000
0.109375
-0.314663
-0.104701
-0.011924
-0.002208
-0.000000
0.117188
-0.407509
-0.152566
-0.022368
-0.005313
-0.000000
-0.000000
0.125000
-0.518045
-0.215834
-0.039695
-0.011613
0.132812
-0.647925
-0.297499
-0.067100
-0.023435
-0.000031
0.140625
-0.798791
-0.400727
-0.108640
-0.044186
-0.000287
0.148438
-0.972266
-0.528809
-0.169262
-0.078552
-0.001468
0.156250
-1.169959
-0.685131
-0.254777
-0.132639
-0.005427
0.164062
-1.393465
-0.873129
-0.371785
-0.214009
-0.016180
0.171875
-1.644372
-1.096269
-0.527552
-0.331613
-0.041152
0.179688
-1.924262
-1.358019
-0.729872
-0.495620
-0.092409
0.187500
-2.234728
-1.661842
-0.986908
-0.717181
-0.187497
0.195312
-2.577375
-2.011181
-1.307047
-1.008144
-0.349593
0.203125
-2.953834
-2.409468
-1.698769
-1.380771
-0.606862
0.210938
-3.365774
-2.860128
-2.170548
-1.847495
-0.991193
0.218750
-3.814917
-3.366593
-2.730783
-2.420719
-1.536664
0.226562
-4.303048
-3.932319
-3.387764
-3.112694
-2.278126
0.234375
-4.832037
-4.560817
-4.149669
-3.935463
-3.250174
0.242188
-5.403856
-5.255675
-5.024594
-4.900864
-4.486639
0.250000
-6.020599
-6.020600
-6.020600
-6.020600
-6.020600
0.257812
-6.684504
-6.859450
-7.145791
-7.306352
-7.884833
0.265625
-7.397981
-7.776287
-8.408404
-8.769932
-10.112627
0.273438
-8.163642
-8.775419
-9.816921
-10.423476
-12.738912
0.281250
-8.984339
-9.861469
-11.380193
-12.279667
-15.801714
0.289062
-9.863195
-11.039433
-13.107586
-14.352002
-19.344007
3-11
HSP43124
TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)
HALFBAND
'3
HALFBAND
'4
HALFBAND
'5
-12.314765
-15.009147
-16.655094
-23.416153
-13.693460
-17.095793
-19.205034
-28.079247
NORMALIZED
FREQUENCY
HALFBAND
'1
HALFBAND
'2
0.296875
-10.803663
0.304688
-11.809574
0.312500
-12.885208
-15.182171
-19.379534
-22.019831
-33.409992
0.320312
-14.035372
-16.788332
-21.873730
-25.119940
-39.508194
0.328125
-15.265501
-18.520315
-24.593418
-28.528942
-46.509052
-20.387625
-27.555685
-32.274414
-54.604954
0.335938
-16.581776
0.343750
-17.991278
-22.401131
-30.780161
-36.389088
-64.087959
0.351562
-19.502172
-24.573368
-34.289623
-40.912403
-75.444221
0.359375
-21.123947
-26.918915
-38.110786
-45.892738
-89.610390
0.367188
-22.867725
-29.454887
-42.275345
-51.390583
-108.973686
0.375000
-24.746664
-32.201569
-46.821358
-57.483341
-152.503693
0.382812
-26.776485
-35.183285
-51.795181
-64.272881
-153.443375
0.390625
-28.976198
-38.429543
-57.254162
-71.898048
-158.914017
0.398438
-31.369083
-41.976673
-63.270564
-80.556969
-156.960175
0.406250
-33.984089
-45.870125
-69.937607
-90.550629
-153.317627
0.414062
-36.857830
-50.167850
-77.378593
-102.379677
-161.115540
0.421875
-40.037594
-54.945438
-85.762718
-117.007339
-153.504684
0.429688
-43.585945
-60.304272
-95.332924
-136.890198
-158.650345
0.437500
-47.588165
-66.385063
-106.462181
-185.130432
-154.637756
0.445312
-52.164894
-73.392075
-119.793030
-187.297241
-153.870453
0.453125
-57.495132
-81.640152
-136.802948
-182.300125
-161.882385
0.460938
-63.861992
-91.658478
-175.030167
-203.460876
-152.278915
0.468750
-71.755898
-104.468010
-158.939362
-174.691895
-164.329758
0.476562
-82.156616
-122.641861
-157.095886
-174.737076
-153.535690
0.484375
-97.627930
-166.537369
-155.613434
-175.108841
-153.507477
0.492188
-139.751450
-165.699081
-154.708450
-169.966568
-167.665482
TABLE 4. HALFBAND FILTER COEFFICIENTS (32-BITS, UN-NORMALIZED)
COEFFICIENT
HALFBAND'2
HALFBAND'l
HALFBAND'3
HALFBAND'4
HALFBAND'5
CO
-67230275
12724188
624169
-197705
23964
C1
0
0
0
0
0
C2
604101076
-105279784
-6983862
2303514
-242570
C3
1073741823
0
0
0
0
C4
604101076
629426509
38140187
-13225905
1306852
C5
0
1073741627
0
0
0
C6
-67230275
629426509
-145867861
51077176
-4942818
C7
0
0
0
0
C8
-105279784
650958284
-161054660
14717750
3-12
HSP43124
TABLE 4. HALFBAND FILTER COEFFICIENTS (32·BITS, UN·NORMALIZED) (Continued)
COEFFICIENT
HALFBAND'l
HALFBANDI3
HALFBAND'2
HALFBAND'4
HALFBAND'5
0
1073741793
0
0
12724188
650958284
657968488
·37027884
C11
0
1073741825
0
C12
·145867861
657968488
84032070
C13
0
0
0
C14
38140187
·161054660
·191585682
C9
C10
C15
0
0
0
C16
·6983862
51077176
670589251
C17
0
0
1073741824
C18
624169
·13225905
670589251
C19
0
0
C20
2303514
·191585682
C21
0
0
C22
·197705
84032070
C23
0
C24
·37027884
C25
0
C26
14717750
C27
0
C28
-4942818
C29
0
C30
1306852
C31
0
C32
·242570
C33
0
C34
23964
TABLE 5. PERFORMANCE ENVELOPE PARAMETERS
Max TAPS = 2DECFIR( (FCLKlFs)DEC HB • HBcLKS • 1)
NUMBER OF
HALFBANDS
The maximum throughput sample rate may be specified by
solving the above equation for Fs. The resulting equation is
HB cLKS
DEC HB
0
0
1
1
13
2
2
33
4
3
69
8
4
125
16
5
221
32
Max Fs
=FCLK*DECHB I(TAPS/(2*DECF1R) + HBcLKS + 1).
NOTE: for configurations using filters with asymmetric coefficients.
the term TAPS in the above equations should be multiplied
by two in order to determine the correct FCLK.
The longest length FIR filter realizable for a particular config·
uration is determined by solving the above equation for
TAPS. The resulting expression is given below.
The Filter Compute Engine is synchronized with an incoming
data stream by asserting the FYSNC# input. When this input
is sample low by the rising edge of FCLK, the Compute
Engine is reset, and the data word following the next asser·
tion of SYNCIN is recognized as the first data sample input
to the filter structure.
3·13
tn
a::
w
!:i
ii:
...
Q
HSP43124
External devices synchronize to the beginning of an output
data word by monitoring SYNCOUT. This output is asserted
"high" one CLKOUT prior to the first bit of the next data word
as shown in Figure 11.
Serial Output Formatter
The Output Formatter serializes the parallel output of the
filter compute engine while generating the timing and
synchronization signals required to support a serial
interface. The Formatter produces serial data words with
programmable lengths from B to 32-bits. The data words
may be organized with either most or least significant bit
first. Also, the data word may be rounded or truncated to the
desired length and the format of the output data may be
specified as either two's complement or offset binary. To
simplify applications where the Serial I/O Filter is used as a
down converter, the output formatter can be configured to
scale the output by a factor of 2. The above options are
programmed via the Output Format and Output Timing
Registers given in Table 1.
CLKOUT
-I1-fl-.n..f1rLn..n.IlJ
SYNCOUT~~
':
OOUT
S~
~~
NOTE: Assumes data is being output LSB first.
FIGURE 11. SERIAL OUTPUT TIMING
The HSP43124 outputs a bit stream through DOUT which is
synchronous to a programmable clock signal output on CLKOUT. The output clock, CLKOUT, is derived from FCLK and
has a programmable rate from 1 to '/32 times FCLK. The
duty cycle of CLKOUT is 50% for rates that have an even
number of FCLK's per CLKOUT. For rates that have and odd
number of FCLK's per OCLK the high portion of the CLKOUT waveform spans (n+1)/2 FCLK's and the low portion
spans (n-1)/2 FCLK's where n is the number of FCLK's.
Input and Output Data Formats
The data formats for the input. output and coefficients are
fractional two's complement. The bit weighting's in the data
words are given in Figure 12. Input or output data words programmed to have less than 24-bits. map to the most significant bit positions of the 24-bit word. For example. an input
word defined to be B-bits wide would map to the bit positions
with weightings from _20 to 2.7 •
FRACTIONAL TWO'S COMPLEMENT FORMAT FOR 24-BIT INPUT AND OUTPUT
FRACTIONAL TWO'S COMPLEMENT FORMAT FOR 32-BIT COEFFICIENTS
FIGURE 12. DATA FORMATS
3-14
Specifications HSP43124
Absolute Maximum Ratings
Supply Voltage ....•.....•.....•.................... +7.0V
Input, Output Voltage .•............... GND -o.sv to V cc +o.sv
Storage Temperature ....•..............•... -6SOC to + 150°C
ESD .....•...............•.....•....•.....••... Class I
Junction Temperature ....•...••.....•..•. +ISOoC (SOIC,PDIP)
Lead Temperature (Soldering lOs) .................... +300oC
Thermal Resistance
SOIC Package ..••..•..............
Plastic DIP Package .....•..•...•...
Maximum Package Power Dissipation
SOIC Package ................................... 1.23W
Plastic DIP Package .............................. 1.78W
Gate Count ............••......•.....•........... .40,304
CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicsted in the operationsl sections of this specificstion is not implied.
Operating Conditions
Operating Voltage Range (Commercial) ........... 4.7SV to S.2SV
DC Electrical Specifications
PARAMETER
Operating Temperature Range (Commercial) •...... O°C to +700 C
(Vcc = S.OV: S%, TA = 0° to +700 C)
SYMBOL
MIN
MAX
UNITS
Power Supply Current
Iccop
-
203
mA
Vcc =Max, FCLK = SCLK =4SMhz
Notes I, 2
Standby Power Supply Current
IcesB
-
SOO
uA
Vee
= Max, Outputs Not Loaded
Input Leakage Current
II
-10
10
uA
Vee
= Max, Input = OV or Vee
Output Leakage Current
10
-10
10
V
Vce
= Max, Input = OV or Vcc
Clock Input High
V IHC
3.0
-
V
Vee
=Max, FCLK and SCLK
Clock Input Low
Vile
0.8
V
Vee = Min, FCLK and SCLK
Logical One Input Voltage
VIH
2.0
-
V
Vec
Logical Zero Input Voltage
V il
-
0.8
V
Vec=Min
Logical One Output Voltage
VOH
2.6
-
V
10H = -SmA, Vec = Min
Logical Zero Output Voltage
Val
0.4
V
IOl = SmA, Vee = Min
Input Capacitance
C IN
10
pF
10
pF
FCLK SCLK = 1MHz
All Measurements Referenced to GND.
T A +2SoC, Note 3
Output Capacitance
COUT
-
NOTES:
1. Power supply current is proportional to frequeney. Typical rating is 4.SmAlMHz.
2. Output load per test circuit and C l = 40pF.
3. Not tested, but characterized at initial design and at major process/design changes.
3-15
TEST CONDITIONS
=Max
=
=
Specifications HSP43124
AC Electrical Specifications
(Note 1) (Vcc = 5.0V.;I; 5%, TA = 0° to +70°C)
45MHz
PARAMETER
SYMBOL
MIN
MAX
COMMENTS
FCLK, SCLK Period
Tcp
22
ns
FCLK, SCLK High
TCH
8
ns
FCLK, SCLK Low
TCl
8
ns
Setup nme DIN, MXIN, SYNCIN, SYNCMX to SCLK
Tos
8
ns
Hold Time DIN, MXIN, SYNCIN, SYNCMX from SCLK
TOH
0
ns
Setup Time FSYNC to FCLK
TSS
8
ns
Hold nme FSYNC from FCLK
TSH
0
ns
Setup Time CO-7, AO-2 to Falling Edge of WR#
Tws
10
ns
Hold nme CO-7, AO-2 from Falling Edge of WR#
TWH
3
ns
Setup nme AO-2 to Falling Edge of AD#
TRS
10
ns
Hold nme AO-2 from Aising Edge of RD#
TRH
0
ns
WR# High
TWRH
10
ns
WAllow
TWRL
10
ns
AD# High
TROH
10
ns
AD# Low to Data Valid
TRoo
25
ns
AD# High to Output Disable
Too
6
ns
FCLK to CLKOUT
TFOC
12
ns
CLKOUT to SYNCOUT, DOUT
Too
8
ns
Output Aise, Fall Time
TRF
3
ns, Note 2
NOTES:
1. AC tests performed with Cl =40pF, 10L =5mA, and 10H =-5mA. Input reference level for FCLK and SCLK is 2.0V, all other inputs 1.5V.
Test V1H =3.0V, V1HC =4.0V, V1L =OV.
2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
changes.
AC Test Load Circuit
··,. ------------------------------ - ------- ...
·
.
-.,
-., -.,
OUT
51:
:
D~~
1
*CL
~
*TESTHEAD
CAPACITANCE
~
~
·
·
:
-
•
:
~
~
~
~ 10H
±
-
-
1.SV
t
10L
..
:
.,
- .
:
EQUIVALENT CIRCUIT
___________________________________________
J:
SWITCH S1 OPEN FOR ICCSB AND Iccop
3-16
HSP43124
Waveforms
OUTPUT RISE AND FALL TIMES
TIMING RELATIVE TO WR.
a-
TWRL
WRf
O.8V
CO·7,
A0-2
TIMING RELATIVE TO READ
INPUT DATA TIMING
RD#
SCLK
AO·2
DIN,MXIN,
SYNCIN,
SYNCMX
CO·7
TIMING RELATIVE TO FLCK AND CLKOUT
3·17
HSP43168
HARRIS
SEMICONDUCTOR
Dual FIR Filter
January 1994
Features
Description
• Two Independent 8-Tap FIR Filters Configurable as a
Single 111..Tap FIR
The HSP43168 Dual FIR Filter consists of two independent
8-tap FIR filters. Each filter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coefficients.
The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The
outputs of the FIR cells are either summed or multiplexed by
the MUXlAdder. The compute power in the FIR Cells can be
configured to provide quadrature filtering, complex filtering,
2-D convolution, 1-0/2-0 correlations, and interpolating/decimating filters.
• 10..Blt Data & Coefficients
• On..Board Storage for 32 Programmable Coefficient
Sets
• Up To: 256 FIR Taps, 16 x 16 2.. 0 Kernels, or 10 x 19-Bit
Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication.
This allows an 8-tap FIR to be implemented using only 4
multipliers per filter cell. These cells can be configured as
either a single 16-tap FIR filter or dual 8-tap FIR filters.
Asymmetric filtering is also supported.
• Standard Microprocessor Interface
Applications
• Quadrature, Complex Filtering
• Image Processing
Decimation of up to 16 is provided to boost the effective
number of filter taps from 2 to 16 times. Further, the decimation registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16x16.
• PolyPhase Filtering
• Adaptive Filtering
The flexibility of the Dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering.
Ordering Information
TEMPERATURE
RANGE
OoC to +70oC
PART NUMBER
HSP43168VC-33
OOC to +70oC
OOC to +70oC
HSP43168VC-45
HSP43168JC-33
PACKAGE
100 Lead MQFP
100 Lead MQFP
OOC to +70oC
OoC to +70oC
84 Lead PLCC
HSP43168GC-33
HSP43168GC-45
OOC to +70oC
84 Lead PGA
HSP43168JC-45
The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of
the device is controlled through a standard microprocessor
interface.
84 Lead PLCC
84 Lead PGA
Block Diagram
_-21~0~
CINO - 9
AD - 8
__+-__________________-.__________~--::~~~-,
-_<.L---f-_1>---------------+--.....------o-I
CONTROLI
CONFIGURATION
cSE~~:-~---t-~-~-----------t--II~~--~~~~~~~
INAO _ 9
..:1~0~+-_________..r'"""":=-=~~
1°r--+--+1
IN BO _ 91 . OUTO-8
OUT9-27
OEL#
OEH#
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-18
File Number
2808.3
3-19
HSP43168
Pinouts (Continued)
100 LEAD MQFP
TOP VIEW
MUX1
MUXO
CIN8
NC
ClN7
NC
CIN6
ClN5
CIN4
GND
GND
ClN3
CIN2
CIN1
CINO
INA9
INA8
INA7
INA6
INAS
RVRS.
NC
FWD.
SHIFTEN.
TXFR.
ACCEN
Vee
Vee
ClK
GND
GND
OEH#
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT1S
OUT17
vee
Vee
INA4
INA3
INA2
INA1
INAO
NC
NC
INB9
INB8
INB7
NC
Vee
Vee
GND
GND
3-20
HSP43768
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
VCC
B5, Dll, Kl0
K7,Fl
VCC: +5V power supply pin.
GND
A9,El0,Lll
K4,D2
Ground.
CINO-9
El-3,Dl,
Cl-2, Bl-3,
Al
I
Control/Coefficient Data Bus. Processor interiace for loading control data and coefficients.
CINO is the LSB.
AO-8
A5-8, B6-8,
C6-7
I
Control/Coefficient Address Bus. Processor interiace for addressing control and coefficient
registers. AO is the LSB.
WR#
Al0
I
Control/Coefficient Write Clock. Data is latched into the control and coefficient registers
on the rising edge of WR#.
CSELO-4
A2-4, B4,C5
I
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by
FIR A and B. This input is registered and CSELO is the LSB.
INAO-9
Kl,Jl-2,
Hl-2, Gl-3,
F2-3
I
Input to FIR A. INAO is the LSB
INBO-9
Ll-5,K2-3
K5-6, J5
I/O
OUT9-27
F9-11,G9-11,
Hl0-ll,Jl0-ll
J7,Kll,
K8-9,L6-10
0
SHFTEN#
Bll
I
Shift Enable. This active low input enables clocking of data into the part and shifting of data
through the decimation registers.
FWRD#
Cl0
I
Forward ALU Input Enable. When active low, data from the forward decimation path is input
to the ALU's through the "a" input. When high, the "a" inputs to the ALUs are zeroed.
RVRS#
All
I
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input
to the ALU's through the "b" input. When high, the "b" inputs to the ALUs are zeroed.
TXFR#
Cll
I
Data Transfer Control. This active low input switches the LIFO being read into the reverse
decimation path with the LIFO being written from the forward decimation path
(see Figure 1).
MUXO-l
B9-10
I
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0
lists the various configurations.
CLK
E9
I
Clock. All inputs except those associated with the processor interface (CINO-9, AO-8,
WR#) and the output enables (OEL#, OEH#)are registered by the rising edge of CLK.
OEL#
J6
I
Output Enable Low. This tristate control enables the LSB's of the output bus
to INBl-9 when OEL# is low.
OEH#
Ell
I
Output Enable High. This tristate control enables OUT9-27 when OEH# is low.
ACCEN
Dl0
I
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator.
A low on this input latches the FIR Accumulator contents into the Output Holding
Registers while zeroing the feedback path in the Accumulator.
Bidirectionallnputfor FIR B.INBO is the LSB and is input only. When
used as output, INB 1-9 are the LSB's of the output bus, and INB9 is the MSB of these bits.
19 MSB's of Output Bus. Data format is either unsigned or two's complement depending
on configuration. OUT27 is the MSB.
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3-21
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muuuuuu"uuuun~
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.......... -- .. --- -_ ................... __ .. - ...... --_ .......... -_ ................. ---
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ROUND.CTRL
______________________________________________
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OUTl-27
HSP43168
Functional Description
As shown in Figure 1.0, the HSP43168 consists of two 4multiplier FIR filter cells which process 10 bit data and
coefficients. The FIR cells can operate as two independent
8-tap FIR filters or two 4-tap asymmetric filters at maximum
I/O rates. A single filter mode is provided which allows the
FIR cells to operate as one 16-tap FIR filter or one 8-tap
asymmetric filter. On board coefficient storage for up to 32
sets of 8 coefficients is provided. The coefficient sets are
user selectable and are programmed through a
microprocessor interface. Programmable decimation to 16
is also provided. By utilizing decimation registers together
with the coefficient sets, polyphase filters are realizable
which allow the user to trade data rate for filter taps. The
MUX/ Adder can be configured to either add or multiplex
the outputs of the filter cells depending upon whether the
cells are operating in single or dual filter mode. In addition, a
shifter in the MUX/Adder is provided for implementation of
filters with 10 bit data and 20 bit coefficients or vice versa.
LSBs are programmed with a value of 0010, the forward
and reverse shifting decimation registers are each
configured with a delay of 3. Bit 4 is used to select whether
the FIR cells operate as two independent filters or one
extended length filter. Coefficient symmetry is selected by
bit 5. Bits 6 and 7 are programmed to configure the FIR
cells for odd or even filter lengths. Bit 8 selects the FIR B
input source when the FIR cells are configured for independent operation. Bit 9 must be programmed to O.
The 4 LSB's of the control word loaded at address 001 Hare
used to configure the format of the FIR cell's data and coefficients. Bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the backward
shifting decimation registers. Bits 5-9 are used to support
programmable rounding on the output.
TABLE 2
CONTROL ADDRESS 001 H
~icroprocessorlnterface
BITS
The Dual has a 20 pin write only microprocessor interface
for loading data into the Control Block and Coefficient Bank.
The interface consists of a 1O-bit data bus (CINO-9), a 9 bit
address bus (AO-8), and a write input (WR#) to latch the
data into the on-board registers. The control and coefficient
data can be loaded asynchronously to CLK.
Control Block
The Dual FIR is configured by writing to the registers within
the Control Block. These registers are memory mapped to
address OOOH (H = Hexadecimal) and 001 H on AO-8. The
format of these registers is shown in Table 1 and Table 2.
Writing the Control/Configuration registers causes a reset
which lasts for 6 CLK cycles following the assertion of
WR#. The reset caused by writing registers in the Control
Block will not clear the contents of the Coefficient Bank.
FUNCTION
0
FIR A Input Format
O=Unsigned
1 = Two's Complement
1
FIR A Coefficient
Format
(Defined same as FIR A input)
2
FIR B Input Format
(Defined same as FIR A input)
3
FIR B Coefficient
(Defined same as AR A input)
4
Data Reversal
Enable
0= Enabled
1 = Disabled
8-5
Round Position
0000 = 2- 10
1011=2 1
9
Round Enable
0= Enabled
1 = Disabled
Each FIR filter cell is based on an array of four 11 x1 0 bit
two's complement multipliers. The multipliers get one input
from the ALUs which combine data shifting through the
forward and backward decimation registers. The second
input comes from the user programmable coefficient bank.
The multiplier outputs feed an accumulator whose result is
passed to the output section where it is multiplexed or
added.
DESCRIPTION
Decimation Factor
OOOO=No Decimation
1111=Decimation by 16
4
Mode Select
o = Single Filter Mode
1 = Dual Filter Mode
5
Odd/Even Symmetry
o = Even symmetric coefficients
1 = Odd symmetric coefficients
6
FIR A odd/even taps
o = Odd number of taps in filter
1 = Even number of taps in filter
7
FIR B odd/even taps
(Defined same as FIR A above)
8
FIR B Input Source
0= Input from INAO-9
1 = Input from INBQ-9
9
Not Used
Set to 0 for proper operation
The 4 LSBs of the control word loaded at address OOOH are
used to select the decimation factor. For example, if the 4
Decimation Registers
The forward and backward shifting registers are
configurable for decimation by 1 to 16 (see Table 1). The
backward shifting registers are used to take advantage of
symmetry in linear phase filters by aligning data at the
ALU's for pre-addition prior to multiplication by the
common coefficient. When the FIR cells are configured in
single filter mode, the decimation registers in each cell are
cascaded. This lengthened delay path allows computation
of a filter which is twice the size of that capable in a single
cell. The decimation registers also provide data storage for
poly-phase or 2-D filtering applications (See Applications
Examples section).
3-23
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FIR Filter Cells
CONTROL ADDRESS OOOH
3-0
DESCRIPTION
NOTE: Address locations 002H to OffH are reserved, and wnting to these
locations will have unpredictable effects on part configuration.
TABLE 1
BITS
FUNCTION
u::
....Q
HSP43168
When the decimation paths are cascaded, data is routed
through the delay stage in FIR A's Data Feedback Circuitry.
The Data Feedback Circuitry in each FIR cell is responsible
for transferring data from the forward to the backward shifting decimation registers. This circuitry feeds blocks of samples into the backward shifting decimation path in either reversed or non-reversed sample order. The MUXIDEMUX
structure at the input to the Feedback Circuitry routes data
to the LIFO's or the delay stage depending on configuration.
The MUX on the Feedback Circuitry Output selects the storage element which feeds the backward shifting decimation
registers.
The configuration of the FIR cells as even or odd length
filters determines the point in the forward decimation path
from which data is multiplexed to the Data Feedback
Circuitry. For example, if the FIR cell is configured as an
odd length filter, data prior to the last register in the third forward decimation stage is routed to the Feedback Circuitry.
If the FIR cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed
to the Feedback Circuitry. This is required to insure proper
data alignment with symmetric filter coefficients (See Application Examples).
In applications requiring reversal of sample order, such as
FIR filtering with decimation, the FIR cells are configured
with data reversal enabled (see Table 2). In this mode, data
is transferred from the forward to the backward shifting registers through a ping-ponged LIFO structure. While one
LIFO is being read into the backward shifting path, the other
is written with data samples. The MUX/DEMUX controls
which LIFO is being written, and the MUX on the Feedback
Circuitry output controls which LIFO is being read. A low on
TXFR# and SHIFTEN#, switches the LIFO's being read
and written, which causes the block of data read from the
structure to be reversed in sample order (See Example 4 in
the Application Examples section).
ALUs
Data shifting through the forward and reverse decimation
path feeds the "a" and "b" inputs of the AlUs respectively.
The AlU's perform an "b+a" operation if the FIR cell is
configured for even symmetric coefficients or an "b-a"
operation if configured for odd symmetric coefficients.
For applications in which a pre-add or subtract is not required, the "a" or "b" input can be zeroed by disabling
FWRD# or RVRS# respectively. This has the effect of producing an AlU output which is either "a","-a", or "b" depending on the filter symmetry chosen. For example, if the
FIR cell is configured for an even symmetric filter with
FWRD# low and RVRS# high, the data shifting through the
forward decimation registers would appear on the AlU output.
The frequency with which TXFR# is asserted determines
size of the data blocks in which sample order is reversed.
For example, if TXFR# is asserted once every three ClK's,
blocks of 3 data samples with order reversed, would be fed
into the backward decimation registers. Note: altering the
frequency or phase of TXFR# assertion once a filtering operation has been started will cause unknown results.
Coefficient Bank
In applications which do not require sample order reversal,
the FIR cells must be configured with data reversal disabled
(see Table 2). In addition, TXFR# must be asserted to
ensure proper data flow. In this configuration, data to the
backward shifting decimation path is routed though a delay
stage instead of the ping-pong LIFO's. The number of
registers in the delay stage is based on the programmed
decimation factor. Note: data reversal must be disabled and
TXFR# must be asserted for filtering applications which do
not use decimation.
The shifting of data through the forward and reverse
decimation registers is enabled by asserting the SHFTEN#
input. When SHFTEN# transitions high, data shifting is
disabled, and the data sample latched into the part on the
previous clock is the last input to the forward decimation
path. When SHFTEN# is asserted, shifting of data through
the decimation paths is enabled. The data sample at the part
input when SHFTEN# is asserted will be the next data
sample into the forward decimation path.
The output of the AlU is multiplied by a coefficient from one
of 32 user programmable coefficient sets. Each set consists
of a coefficients (4 coefficients for FIR A and 4 for FIR B).
The active coefficient set is selected using CSElO-4. The
coefficient set may be switched every clock to support
polyphase filtering operations.
The coefficients are loaded into on-board registers using
the microprocessor interface, CINO-9, AO-a, and WR#.
Each multiplier within the FIR Cells is driven by a coefficient
bank with one of 32 coefficients. These coefficients are
addressed as shown in Table 3. The inputs AO-1 specify the
Coefficient Bank for one of the four multipliers in each FIR
Cell; A2 specifies FIR Cell A or B; Bits A7-3 specify one of
32 sets in which the coefficient is to be stored. For example,
an address of 10dH would access the coefficient for the
second multiplier in FIR B in the second coefficient set.
When operating the FIR cells as two independent filters, FIR
A receives input data via INAO-9 and FIR B receives data
from either INAO-9 or INBO-9 depending on the configuration (Table 1). When the FIR cells are configured as a single
extended length filter, the forward and backward
decimation paths are cascaded. In this mode, data is
transferred from the forward decimation path to the backward decimation path by the Data Feedback Circuitry in FIR
B. Thus, the manner in which data is read into the backward
shifting decimation path is determined by FIR B's configuration.
3-24
TABLE 3
AS
A7-3
A2
A1-0
FIR
BANK
1
xxxxx
1
xxxxx
0
00
A
0
0
01
A
1
1
xxxxx
0
10
A
2
1
xxxxx
0
11
A
3
1
xxxxx
1
00
B
0
1
xxxxx
1
01
B
1
1
xxxxx
1
10
B
2
1
xxxxx
1
11
B
3
HSP43168
FIR Cell Accumulator
The registered outputs from the multipliers in each FIR cell
feed the FIR cell's accumulator. The ACCEN input controls
each accumulator's running sum and the latching of data
from the accumulator into the Output Holding Registers.
When ACCEN is low, feedback from the accumulator adder
is zeroed which disables accumulation. Also, output from
the accumulator is latched into the Output Holding Registers. When ACCEN is asserted, accumulation is enabled
and the contents of the Output Holding Registers remain
unchanged.
OUTPUT DATA FORMAT OUT9-27
FRACTIONAL TWO'S COMPLEMENT
127126125124123122121120119118117116115114113112111 110 19I
~~~~~~~~~~~~~~~~~~~
OUTPUT DATA FORMAT OUTO-8
FRACTIONAL TWO'S COMPLEMENT
Output MUX/Adder
The contents of each FIR Cell's Output Holding Register is
summed or multiplexed in the Mux/Adder. The operation of
the Mux/Adder is controlled by the MUX1-0 inputs as
shown in Table 4. Applications requiring 10 bit data and 20
bit coefficients or 20 bit data and 10 bit coefficients are
made possible by configuring the MUX/Adder to scale FIR
8's output by 2- 10 prior to summing with FIR A. When the
Dual FIR is configured as two independent filters, the
MUX1-0 inputs would be used to multiplex the filter outputs
of each cell. For applications in which FIR A and 8 are
configu red as a single filter, the M UX/Adder is configured to
sum the output of each FIR cell.
INPUT DATA FORMAT INAO-9, INBO-9
FRACTIONAL UNSIGNED
9
8
20
.2-1
I
7
2-2
1 6
2-3
1 5
2-4
1 4
2- 5
1 3
2-6
121
2-7
0
2-8
2-9
OUTPUT DATA FORMAT OUT9-27
FRACTIONAL UNSIGNED
TABLE 4
127126125124123122121120119118117116115114113112111 110 19 1
MUX1-0 DECODING
MUX1-0
~~~~~~~~~~~~~~~~~~~
OUTO-27
00
FIRA + FIRB (FIR B Scaled by 2-1 0)
01
FIRA+ FIRB
10
FIRA
11
FIRB
OUTPUT DATA FORMAT OUTO-8
FRACTIONAL UNSIGNED
Input/Output Formats
The Dual FIR supports mixed mode arithmetic with both
unsigned and two's complement data and coefficients. The
input and output formats for both data types is shown below. If the Dual FIR is configured as an even symmetric filter
with unsigned data and coefficients, the output will be
unsigned. Otherwise, the output will be two's complement.
INPUT DATA FORMAT INAO-9,INBO-9
FRACTIONAL TWO'S COMPLEMENT
98171615141312110
-20
.2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
The MUX/Adder can be configured to implement programmable rounding at bit locations 2- 10 through 21. The round
is implemented by adding a 1 to the specified location (see
Table 2.0). For example, to configure the part such that the
output is rounded to the 10 MS8s, OUT18-27, the round
position would be chosen to be 2- 1.
Application Examples
In this section a number of examples which show even, odd,
symmetric, asymmetric and decimating filters are
presented. These examples are intended to show different
operational modes of the HSP43168. The examples are all
based on a dual filter configuration. However, the same
principles apply when the part is configured with both FIR
cells operating as a single filter.
3-25
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HSP43168
Example 1. Even-Tap Symmetric Filter Example
The HSP43168 may be configured as two independent 8tap symmetric filters as shown by the block diagram in Figure 2. Each of the FIR cells takes advantage of symmetric
filter coefficients by pre-adding data samples common to a
given coefficient. As a result, each FIR cell can implement
an 8-tap symmetric filter using only four multipliers. Similar·
Iy, when the HSP43168 is configured in single filter mode a
16-tap symmetric filter is possible by using the multipliers
in both cells.
A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE
FEED FORWARD STAGE.
The operation of the FIR cell is better understood by comparing the data and coefficient alignment for a given filter
output, Figure 3, with the data flow through the FIR cell, as
shown in Figure 4. The block diagrams in Figure 4 are a
simplification of the FIR cell shown in Figure 1. For simplicity, the ALU's and FIR Cell Accumulators were replaced by
adders, and the pipeline delay registers were omitted.
HSP43168
(X7+ XO)CO+ (X6+ X1)C1+ (X5+ X2)C2+ (X4+ X3)C3
B. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE
FEED FORWARD STAGE.
INAO -9
FIR A
INBO -9
ARB
1---1--
OUT9 - 27
FIGURE 2. USING HSP43168 AS TWO INDEPENDENT
FILTERS
In Figure 4, the order of the data samples within the filter cell
is shown by the numbers in the forward and backward shift·
ing decimation paths. The output of the filter cell is given by
the equation at the bottom of each block diagram. Figure 4a
shows the data sample alignment at the pre-adders for the
data/coefficient alignment shown in Figure 3.
C. DATA FLOW AS DATA SAMPLE 9 IS CLOCKED INTO THE
FEED FORWARD STAGE.
h(n)
x(n)
(X8+ X1)CO+ (X7+ X2)C1+ (X6+ X3)C2+ (X5+ X4)C3
I
X9
II I II IIII
xa
X7
X6
X5
X4
X3
X2
Xl
Xo
FIGURE 3. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP
EVEN SYMMETRIC FILTER
The dual filter application is configured by writing 1 dOH to
address OOOH via the microprocessor interface, CINO-9,
AO-8, and WR#. Since this application does not use
decimation, the 4th bit of the control register at address
001 H must be set to disable data reversal (see Table 2).
Failure to disable data reversal will produce erroneous
results.
3·26
(X9+ X2)CO+ (X8+ X3)C1+ (X7+ X4)C2+ (X6+ X5)C3
FIGURE 4. DATA FLOW DIAGRAMS FOR 8-TAP
SYMMETRIC FILTER
HSP43168
Using this architecture, only the unique coefficients need to
be stored in the Coefficient Bank. For example, the above
filter would be stored in the first coefficient set for FIR A by
writing CO, C1, C2, and C3 to address 100H, 101 H, 102H,
and 103H respectively. To write the same filter to the first
coefficient set for FIR B, the address sequence would
change to 104H, 105H, 106H, and 107H.
To operate the HSP43168 in this mode, TXFR# is tied low
to ensure proper data flow; both FWRD# and RVRS# are
tied low to enable data samples from the forward and
reverse data paths to the AlU's for pre-adding; ACCEN is
tied low to prevent accumulation over multiple ClK's;
SHFTEN# is tied low to allow shifting of data through the
decimation registers; MUXO-1 is programmed to multiplex
the output the of either FIR A or FIR B; CSElO-4 is programmable to access the stored coefficient set, in this example CSEl = 00000.
Example 2. Odd-Tap Symmetric Filter Example
The HSP43168 may be configured as two independent
7-tap symmetric filters with a functional block diagram
resembling Figure 2. As in the 8-tap filter example, the
HSP43168 implements the filtering operation by summing
data samples sharing a com mon coefficient prior to multiplication by that coefficient However, for odd length filters the
pre-addition requires that the center coefficient be scaled
by 1/2.
A. DATA FLOW AS DATA SAMPLE 6 IS CLOCKED INTO
THE FEED FORWARD STAGE.
6
+ Xl3)Cl0
+ (X2+ X2l)C2+ (XS+ X18)CS+ (X8+ Xl5)C8+ (Xl1+ X12)Cll
J'T""""""i\ I .- ~ I
.!rt-t-\!
1"-: ! r-'~: I 't-
FIGURE 12. CONTROL SIGNAL TIMING FOR 24-TAP
DECIMATE X3 FILTER
C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS
CLOCKED INTO THE FEED FORWARD STAGE
Example 5. Odd-Tap Decimating Symmetric Filter
This example highlights the use of the HSP43168 as two independent, 23-tap, symmetric, decimate by 3 filters. In this
example, the operational differences in the control signals
and data reversal structure may be compared to the previously discussed even-tap decimating filter.
23
~~~:J~
I
ACCUMULATOR
I
1
X(0)C3+ (X8+ Xl1)C8+
(XO+ X(3)CO+ (X3+
(X9+ X14)C9
+ (Xl+ X(2)C1+ (X4+ X19)C4+ (X7+ Xl6)C7+ (X1C>+ Xl3)Cl0
+ (X2+ X(1)C2+ (XS+ X18)CS+ (X8+ Xl5)C8+ (Xll+ Xl2)Cll
To operate in this mode the Dual is configured by writing
1d2 to address OOOH via the microprocessor interface,
CINO-9, AO-8, and WR#. Data reversal must be enabled
see (Table 2.0). The 12 unique coefficients for this example
are stored as three sets of coefficients for either FIR cell. For
FIR A, the coefficients are loaded into the Coefficient Bank
by writing C2, C5, C8, C11, C1, C4, C7, C10, CO, C3, C6,
and C9 to address 100H, 101 H, 102H, 103H, 108H, 109H,
10aH, 10bH, 11 OH, 111 H, 112H, and 113H respectively.
As in the 24-tap example, an output is required every third
ClK which allows 3 ClK's for computation. On each ClK,
one of three sets of coefficients are used to calculate the filter taps. Since this is an odd length filter, the center coefficient must be scaled by 1/2 to compensate for the
summation of the same data sample from the forward and
backward shifting decimation paths.The block diagrams in
Figure 14 show the data flow and accumulator output for
the data coefficient alignment in Figure 13.
Proper data and coefficient alignment is achieved by asserting TXFR# once every three ClK's to switch the LIFO's
which are being read and written. For odd length filters, data
prior to the last register in the forward decimation path is
routed to the Feedback Circuitry. As a result, TXFR# should
be asserted one cycle prior to the input data samples which
align with the center tap. The timing relationship between
the CSElO-5, ACCEN, and TXFR# are shown in
Figure 15.
3-30
HSP43168
C. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS
CLOCKED INTO THE FEED FORWARD STAGE
xCn)
trllrI!rt!IIr!
23 22 21 20 19 18 17 16 15 14 13 12 11 10
ItTtrIII
76543210
FIGURE 13. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP
DECIMATE BY 3 SYMMETRIC FILTER
(XO+ X22)CO+ (X3+ X19)C3+ (X6+ X16)C8+ (X9+ X13)C9
+ (X1+ X2l)Cl+ (X4+ X18)C4+ (X7+ Xl5)C7+ (Xl0+ Xl2)Cl0
+ (X2+ X20)C2+ (X5+ Xl7)C5+ (X8+ X14)C8+ (Xll+ Xll)Cll(.1
D. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS
CLOCKED INTO THE FEED FORWARD STAGE
23
~
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u:::
....Q
(X5+ X23)C2+ (X8+ X20)C5+ (Xl1+ Xl7)C8+ (X14+ X14)Cll(.1
(X2+ X(0)C2+ (X5+ Xl7)C5+ (X8+ X14)C8+ (Xl1+ Xl1)Cl1f.2
A. COMPUTATIONAL FLOW AS DATA SAMPLE 20 IS
CLOCKED INTO THE FEED FORWARD STAGE
FIGURE 14. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE
BY 3 SYMMETRIC FILTER
CLK
INAO -9
CSELO -4
ACCEN
TXFR#
FIGURE 15. CONTROL SIGNAL TIMING FOR 23-TAP
SYMMETRIC FILTER
(X1+ X2l)C1+ (X4X18)C4+ (X7+ Xl5)C7+ (Xl 0+ X12)Cl0
+ (X2+ X20)C2+ (X5+ Xl7)C5+ (X8+ X14)C8+ (Xll+ Xll)Cll(.1
B. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS
CLOCKED INTO THE FEED FORWARD STAGE
To operate in this mode, the Dual is configured by writing
112H to address OOOH via the microprocessor interface,
CINO-9, AO-8, and WR#. Data reversal must be enabled
(see Table 2.0). The 12 unique coefficients for this example
are stored as three sets of coefficients for either FIR cell. For
FIR A, the coefficients are loaded into the Coefficient Bank
by writing C2, C5, C8, (C11)/ 2, C1, C4, C7, C10, CO, C3,
C6, and C9 to address 100H, 101 H, 102H, 103H, 108H,
109H, 1OaH, 10bH, 11 OH, 111 H, 112H, and 113H respectively.
3-31
Specifications HSP43168
Absolute Maximum Ratings
Supply Voltage ................................................................................................. +8.0V
Input, Output Voltage .......................................................................... GND -o.sv to VCC +o.sv
Storage Temperature ................................................................................. -6So C to +1S00C
ESD ......................................................................................................... Class1
Maximum Package Power Dissipation at +700 C ••••••••••••••••.••••••••••••••.•••• 2.4W (MOFP), 3.6W (PLCC), 3.1 W (PGA)
Eljc .................................................................. 13.So C/W (MQFP), 7.40 C/W (PLCC), 7.SoC/W (PGA)
Elja •••••••••••••••••••••••••••••••••••••••••••.••••••••••••••••••• 33.00 C/W (MQFP), 22.30 C/W (PLCC), 33.So C/W (PGA)
Gate Count ....................................................................................................32S29
Junction Temperature ................................................................... +17S0 C (PGA), +1SOoC (PLCC)
Lead Temperature (Soldering 10s) .............................................................................. +3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only fating and
operation of the device at these or any other conditions above those indicated in the operational sect/ons of this specffication Is not ImplIed.
Operating Conditions
Operating Voltage Range, Commercial .......................................................................... sv ± S%
Operating Temperature Range
Commercial ........................................................................................... OoC to + 700 C
D.C. Electrical Specifications
SYMBOL
PARAMETER
ICCOp
Power Supply Current
Iccse
Standby Power Supply Current
MIN
MAX
UNITS
-
363
mA
VCC=Max
CLK Frequency 33MHz
Note 2, Note 3, Note 4
TEST CONDITIONS
-
SOO
!1A
VCC = Max, Outputs Not Loaded
II
Input Leakage Current
-10
10
!1A
VCC = Max,lnput = OVorVCC
10
Output Leakage Current
-10
10
!1A
VCC = Max,lnput = OVorVcc
VIH
Logical One Input Voltage
2.0
-
V
VCC=Max
VIL
Logical Zero Input Voltage
-
0.8
V
VCC=Min
VOH
Logical One Output Voltage
2.6
-
V
IOH = -400ElA, VCC = Min
VOL
Logical Zero Output Voltage
-
0.4
V
IOL = 2mA, VCC = Min
VIHC
Clock Input High
3.0
-
V
VCC=Max
VILC
Clock input Low
0.8
V
VCC=Mln
CIN
Input CapaCitance
-
12
pF
Output Capacitance
-
12
pF
CLK Frequency 1 MHz
A" measurements referenced
toGND.
TA = +2S0 C, Note 1
COUT
NOTES:
1. Controlled via deSign or process parameters and not directly tested. Characterized upon In Rial design and after major process and/or changes.
2. Power Supply current Is proportional to operating frequency. Typical
rating for ICCOp Is 11 mNMHz.
3. Output load per test load circuH and CL = 40pF.
4. Maximum junction temperature must be considered when operating part
at high clock frequencies.
3-32
Specifications HSP43168
A.C. Electrical Specifications vcc
= +4.75V to +5.25V, TA = OOC to HOoC (Note 1)
33MHz
SYMBOL
PARAMETER
MIN
45MHz
MIN
MAX
MAX
COMMENTS
8
-
22
-
ns
10
-
ns
10
8
-
ns
0
-
ns
10
-
ns
TCp
ClKPeriod
30
-
TCH
ClKHigh
12
TCl
ClKlow
12
TWp
WR#Period
30
TWH
WR# High
12
TWl
WR#low
12
TAWS
Set-up Time AO-8 to WR# Going low
10
TAWH
Hold Time AO-8 from WR# Going High
0
-
TCWS
Set-up Time CINO-9 to WR# Going High
12
TCWH
Hold Time CINO-9 from WR# Going High
1
TWlCl
Set-up Time WR# low to ClK low
5
TCVCl
Set-up Time CINO-9 to ClK low
7
-
7
-
TECS
Set-up Time CSElO-5, SHFTEN#, FWRD#, RVRS#, TXFR#,
INAO-9, INBO-9, ACCEN, MUXO-1 to ClK Going High
15
-
12
-
ns
TECH
Hold Time CSElO-5, SHFTEN#, FWRD#, RVRS#, TXFR#,
INAO-9, INBO-9, ACCEN, MUXO-1 to ClK Going High
0
-
0
-
ns
TOO
ClK to Output Delay OUTO-27
-
14
-
12
ns
TOE
Output Enable Time
12
ns
Output Disable Time
12
-
12
TOO
-
12
ns, Note 3
TRF
Output Rise, Fall Time
-
6
-
6
ns, Note 3
22
8
-
1
3
NOTES:
=
=
=
1. AC tests performed wHh CL 40pF,IOL 2mA, and IOH -400~A.lnpul
refe~ence level eLK = 2.0V. Input reference level for all other inputs is
1.5V. Tesl VIH
a.ov, VIHC 4.0V, VIL OV, VILC OV.
=
=
=
=
2. Set-up time requirement for loading of data on CINO-9 to guarantee
recognition on the following clock.
3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and lor changes.
A.C. Test Load Circuit
--I
1- - - - - - - - - - - 1
1
1
1
1
1
1
1
1
t
1.5V
SWITCH Sl OPEN FOR
ICCSB AND ICCOp
1
1
-
-
1
IOL
-
EQUIVALE;;T CIRCUIT -
______________ J
3-33
1
1
1
ns
ns
ns
ns
ns
ns, Note 2
ns, Note 2
en
II:
w
~
u::
o
HSP43168
Waveforms
CLK
CSELO - 4, MUXO - 1
SHFTEN-#, FWRD-#,
RVRS-#, TXFR -#,
INAO - 9, INBO - 9,
ACCEN
TECS 1--t---0.1
OUTO - 27
--TWLCL r-e----TWP
WR-#
AO -8
CINO -15
OEL-#,OEH-#
OUTO - 27
t_·5_:0-E-.-~---~T:O
-----4
_
HIGH
.~>---
1.3V
HIGH
IMPEDANCE
IMPEDANCE
OUTPUT ENABLE, DISABLE TIMING
~
MV
_
OUTPUT RISE AND FALL TIMES
3-34
TRF
HSP43168/883
HARRIS
SEMICONDUCTOR
Dual FIR Filter
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL-STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HSP43168 Dual FIR Filter consists of two independent
a-tap FIR filters. Each filter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coeffiCients.
The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The
outputs of the FIR cells are either summed or multiplexed by
the MUXlAdder. The compute power in the FIR Cells can be
configured to provide quadrature filtering, complex filtering,
2-D convolution, 1-0/2-0 correlations, and interpolating/decimating filters.
• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR
• 10-Blt Data & Coefficients
• On-Board Storage for 32 Programmable
Coefficient Sets
• Up To: 256 FIR Taps, 16 x 162-0 Kernels, or
10 x 20-Bit Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
• 33MHz, 25.6MHz Versions
Decimation of up to 16 is provided to boost the effective
number of filter taps from 2 to 16 times. Further, the decimation registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16x16.
Applications
• Quadrature, Complex Filtering
• Correlation
• Image Processing
The flexibility of the Dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering.
• PolyPhase Filtering
• Adaptive Filtering
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication.
This allows an a-tap FIR to be implemented using only 4
multipliers per filter cell. These cells can be configured as
either a single 16-tap FIR filter or dual a-tap FIR filters.
Asymmetric filtering is also supported.
PACKAGE
HSP43168GM-25/883
-55°C to +125°C
84 Lead PGA
HSP43168GM-331883
-55°C to +125°C
84 Lead PGA
The HSP4316a is a low power fully static design implemented in an advanced CMOS process. The configuration of
the device is controlled through a standard microprocessor
interface.
Block Diagram
_~10~~-.
____________________. -________~r--:::::~--'
CINO - S
CONTROLI
AO - 8 ----.l-'-L.--+-_1>-----------------+--_------o-J CONFIGURATION
CSE~~:--~----t--j--1t==-----------t--t-~~--~~~::~~~
INAO-9
_l~O~~~________+r~::::~~
>----------.
OEL.
OEH#
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-35
OUTS - 27
File Number
3177.2
8!w
!:i
iL
c....
HSP431681883
Pinouts
84 PIN PGA
TOP VIEW
11
L
10
a
8
7
S
4
3
2
INB1
INB4
INB5
INB6
INB9
L
GNO
INB7
INBS
INA1
K
INAO
INA2
J
INA3
INA4
H
S
GNO OUT1S OUT14 OUT12 OUT10 OUT11
K
OUT18
J
OUT19 OUT17
H
OUT21 OUT20
G
OUT24 OUT23 OUT25
INA7
INA5
INA6
G
F
OUT27 OUT22 OUT26
INAS
INA9
Vee
F
E
OEHII
GNO
CIN2
CIN1
CINO
E
o
Vee
~CCEN
GNO
CIN3
o
C
TXFR.
CIN6
CIN4
C
CIN7
CIN5
B
B
Vee
OUT16 OUT13
•
SHFT
EN. MUXO MUX1
11
10
INBO
INB2
OUTa
OEL.
INB3
CLK
FWRO
A RVRS# WRII
Vee
GNO
AS
AS
CSELO
AO
A3
A2
Vee
A1
A4
A7
A8
7
6
5
9
CSEL2 CIN9
CSEL1 CSEL3 CSEL4 ClNS
4
3
2
4
3
2
A PIN 'A1'
10
84 PIN PGA
BOTTOM VIEW
11
10
9
A
RVRS
#
WR#
GNO
B
SHFT
ENII
MUXO MUX1
7
S
5
A1
A4
A7
A8
AO
A3
A2
Vee
A5
A6
CSELO
CSEL1 CSEL3 CSEL4
ClNS
PIN 'A1'
A
CIN7
CIN5
B
CIN6
CIN4
C
GNO
CIN3
o
CIN2
CIN1
CINO
E
F OUT27 OUT22 OUT26
INAS
INA9
Vee
F
G OUT24 OUT23 OUT25
INA7
INA5
INA6
G
INA3
INA4
H
INAO
INA2
J
C TXFR#
FWRO
•
o
Vee
ACCE~
E
OEH#
GNO
H
OUT21 OUT20
J
OUT19 OUT17
K OUT1S
L
GNO
11
CSEL2 CIN9
CLK
OUT9
OEL# INB3
INB2
GNO
INB7
INBS
INA1
K
OUT15 OUT14 OUT12 OUT10 OUT11 INB1
INB4
INB5
INB6
INB9
L
4
3
2
Vee
10
OUT16 OUT13
9
Vee
7
INBO
6
3-36
5
10
Specifications HSP43168/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage ••...••.•.•...••...••..•.••••..•....• +8.0V
Input, Output or 1/0 Voltage •••.••..••••• GND-O.5V to Vee+O.5V
Storage Temperature Range ...•••..••.••.•.. -65°C to +150oC
Junction Temperature .......•........•...•...•...•. + 175°C
Lead Temperature (Soldering lOs) .•.•••••..•......••• +300oC
ESD Classification .........•........•........•.... Class 1
Thermal Resistance
9JA
Ceramic PGA Package . . . . • • • • • • •• 33.50 CIW
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Packazge • • • • . • • • . . • • . • . . • • . . . • . . •• 1.49 W
Gate Count ...•.••••.••••..••••••••••••..••.• 32529 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the deVIce at these or any other conditions above those indicated in the operational sections of this specification is not implied
Operating Conditions
Operating Voltage Range .•..•••...•..•.....•. +4.5V to +5.5V
Operating Temperature Range .•...•.•.••..•.• -55°C to +125°C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
LIMITS
GROUP A
SUB"
GROUPS
TEMPERATURE
MIN
MAX
UNITS
2.2
-
V
Logical One Input
Voltage
VIH
Vcc =5.5V
1,2,3
-55°';; TA ,;; + 125°C
Logical Zero Input
Voltage
VIL
Vee = 4.5V
1,2,3
.55°,;; TA
,;;
+ 1250C
.
0.8
V
Logical One Input
Voltage Clock
V IHe
Vee =5.5V
1,2,3
.55°,;; TA
,;;
+ 125°C
3.0
-
V
Logical Zero Input
Voltage Clock
VILe
Vec =4.5V
1,2,3
.55°,;; TA ,;; + 125°C
-
0.8
V
Output HIGH Voltage
VOH
IOH=-400~
1,2,3
.55°,;; TA
,;;
+ 125°C
2.6
.
V
IOL=+2.0mA
Vce= 4.5V (Note 1)
1,2,3
.55°,;; TA
,;;
+ 125°C
-
0.4
V
,;;
VOL
Input Leakage Current
II
VIN = Vee or GND
Vcc= 5.5V
1,2,3
.55°,;; TA
+ 125°C
-10
+10
IJ.A
Output Leakage Current
10
VIN = Vce or GND
Vcc =5.5V
1,2,3
.55°,;; TA ,;; + 125°C
·10
+10
IJ.A
Standby Power Supply
Current
leese
VIN = Vee or GND
Vee =5.5V,
Outputs Open
1,2,3
-55°,;; TA
,;;
+ 1250C
SOO
I1A
Operating Power Supply
Current
Icoop
f = 25.6MHz, VIN = Vec
or GND, Vee = 5.5V
(Note 2)
1,2,3
.55°,;; TA
,;;
+ 125°C
.
281.6
rnA
7,8
.55°,;; TA
,;;
+ 125°C
-
-
-
Functional Test
!:i
u:::
Vee= 4.5V (Note 1)
Output LOW
Voltage
~
w
FT
(Note 3)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency, typical rating is 11 mAIM Hz.
3. Tested as follows: f = lMHz, VIH(clock inputs) = 3AV, V IH (all other inputs) = 2.6V, VIL = 0.4V, VOH ~ 1.5V, and VOL';; I.SV.
3-37
c
....
Specifications HSP431681883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
(-33MHz)
(-25MHz)
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
-
39
-
ns
15
-
ns
ClKPeriod
Tcp
9,10,11
_55° S TA S +125OC
30
CLKHigh
TCH
9,10,11
_55° S TA S +125OC
12
CLKlow
TCl
9,10,11
_55° S TA S +125°C
12
WRit Period
Twp
9,10,11
_55° S TA S +12SOC
30
WRit High
TWH
9,10,11
_55° S TA S +125°C
12
WRit low
TWL
9,10,11
-55° S TA S +12SOC
12
-
15
Set-up Time;
AO-8 to WRit Low
TAWS
9,10,11
-55°STAS+125°C
10
-
Hold Time;
AO-8 to WRit High
TAWH
9,10,11
-55OSTAS+125OC
1
Set-up Time;
CINO-9 to WRit High
Tcws
9,10,11
-55°STAS+125°C
Hold Time;
CINO-9 to WRit High
TCWH
9,10,11
Set-up Time;
WRit low to ClK low
TWlCl
Note 3
Set-up Time;
CINO-9 to ClK low
TCVCl
Note 3
Set-up Time;
CSElO-5, SHFTENIt,
FWRDIt, RVRSIt,
TXFRIt, MUXO-l to
ClKHigh
-
15
ns
ns
10
-
-
I
-
ns
12
-
15
-
ns
_55° S TA S +125OC
1.5
-
1.5
-
ns
9,10,11
_55° S TA S +125°C
5
-
8
-
ns
9,10,11
_55° S TA S +125°C
8
-
8
-
ns
TECS
9,10,11
-55°STAS+125°C
15
-
17
-
ns
Hold Time;
CSElO-5, SHFTENIt,
FWRDIt, RVRSIt,
TXFRIt, MUXO-l to
ClKHigh
TECH
9,10,11
-55° S TA S +125OC
0
-
0
-
ns
ClK to Output Delay
OUTO-27
Too
9, tO,11
-55°s TAS +12SOC
-
15
-
17
ns
Output Enable Time
TOE
9, 10, 11
-55°STAS+125°C
-
12
-
12
ns
Note 2
39
15
ns
ns
ns
NOTES:
1. AC testing is performed as follows: Input levels (ClK Input) 4.0V and OV; Input levels (all other Inputs) 3.0V and OV; Timing reference
levels (ClK) 2.0V; All others 1.5V. Vcc = 4.5V and 5.5V. Output load per test load circuit with Cl = 40 pF. OUtput transition Is measured
atVOH > 1.5V and VOL < f.5V.
2. Transition is measured at ±200mV from steady state voltage, Output loading per test load circuit, Cl = 40pF.
3. Set-up time requirements for loading of data on CINO-9 to guarantee recognition on the following clock.
3-38
Specifications HSP431681883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(-33MHz)
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
CIN
Vcc = Open, 1=1 MHz
All measurements
are relerenced to
device GND.
1
TA = +25°C
1
TA = +25°C
1,2
-55°"TA ,,+125°C
Output Capacitance
COUT
Output Disable Time
Too
Output Rise Time
Output Fall Time
MIN
MAX
MIN
MAX
UNITS
12
-
12
pF
12
-
12
pF
12
12
ns
8
-
8
ns
8
-
8
ns
-
TR
From 0.8V to 2.0V
1,2
-55°" TA" +125°C
TF
From 2.0V to 0.8V
1,2
-55°" TA" +125°C
(-25MHz)
-
NOTE:
1. The parameters In Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and
aiter major process and/or design changes.
2. Loading is as specified in the test load circuit with CL = 4OpF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
Initial Test
1000/cJ5004
Interim Test
lOOO/cJ5004
-
PDA
100%
1
Final Test
100%
2,3, 8A, 8B, 10, 11
-
1,2,3,7, 8A, 8B, 9,10,11
Samples/5005
1,7,9
Group A
Groups C and D
~
w
SUBGROUPS
!:i
u::
...o
AC Test Load Circuit
...........................................................................................,
~
~
:
1
SI
I
I
!
.clI
DUTC]
:
• INCLUDES STRAY
AND JIG
CAPACITANCE
:
I - ,~,~~;.: ~'~
t ..........................................................................................
SWITCH SI OPEN FOR IcesB AND Iccop TEST
3-39
HSP431681883
Waveforms
Tcp _ _ _
TCL
CLK
TEes TECH
CSEL0-4. MUX0-1
SHFTENI. FWRDI.
RVRst. TXFRI.
INA0-9. INB0-9
----'I"--!--'I"....p.---
OUT0-27
--
TWLCL
---
~---- Twp
TWL
WRI
A0-8 _ _ _
""I~
__+"I'_-+__
Tews
TCWH
CIN0-1S
OELI.OEHI
1.SV
1.SV
TOE
Too
'III(
OUTO-27
..
1.7V
HIGH
IMPEDANCE
1.3V
OUTPUT ENABLE. DISABLE TIMING
OUTPUT RISE AND FALL nMES
3-40
HIGH
IMPEDANCE
HSP43168/883
Burn-In Circuit
84PINPGA
BOTTOM VIEW
I
I
7
•
5
GND
A1
M
A7
AI
CSEl1 CSEL3 CSEL4 ClNI
APIN 'A1'
ID
B
SHFT MUXD MUX1
ENI
AO
A3
A2
Vee
CSEU CINe ClN7
ClN6
B
C
TXFRI FWRD
I
AS
AI
CSELO
CINe
ClN4
C
GND
ClN3
D
ClN1
ClND
E
11
10
A
RVRS
I
WAf
4
2
3
D
Vee
ACCEN
E
OEHt
GND
F
OUT27 OUT22 OUT26
INAI INAe
Vee
F
G
OUT24 OUT23 puT25
INA7 INAS
INAS
G
H
OUT21 OUT20
INA3
INM
H
J
OUT18 OUT17
INAO
INA2
J
ClN2
ClK
OUTe
OELI INB3
U)
l
Vee OUT1e DUT13
INB2
GND
INB7 INB'
INA1
K
GND OUT1S ruTH OUT12 OUT1C 0UT11 INB1
INB4
INBS INBS
INBI
l
K OUT1'
11
10
8
Vee
I
INBO
~
u:::
...
C
•
7
a::
11.1
6
4
3
2
5. FO= 100KHztl0%, Fl = F0I2, F2 = Fl/2 ... , F1S= Fl512,
40 to 60% duty cycle.
NOTES:
1. V ed2 (2.7V tl0%) used lor outputs only.
S. Input voltage limits:
V 1L = O.BV Max, V 1H = 4.5 tl0%
2. 47KO (±20%) resistor connected to all pins except Vee and GNO
3. Vee = 5.5 tD.5V.
4. 0.1111 (Min) capaeitorbetween Vee and GNO per position.
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
Al
GINS
F9
611
I SHFTEN
A2
GSEl4
F12
Cl
A3
CSEL3
Fll
C2
ICiN4
CINS
F9
Fll
A4
CSEll
F9
C5
CSElO
FB
Gl
INAS
A5
A8
F12
OS
AS
Fll
G2
INA5
A6
A7
FlO
C7
A5
F12
G3
A7
A4
Fll
010
FWRO
F13
G9
AB
Al
F12
Gll
TXFR
Fll
Gl0
A9
GNO
GNO
01
CIN3
FlO
Al0
WRB
F6
02
GNO
All
RVRS
F12
010
ACCEN
Bl
CIN5
FB
011
B2
CIN7
FlO
B3
CIN9
B4
B5
B6
B7
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
K2
INBS
F9
K3
INB7
F8
Ved2
K4
GNO
GNO
F7
K5
INB2
F3
FS
KS
INBO
Fl
INA7
FB
K7
KB
I SUM23
Ved2
Vcd2
Vee
SUM13
Vee
SUM25
K9
I SUM1S
Gll
SUM24
V ed2
Kl0
Vee
GNO
Hl
INA4
F5
Kll
Vee
SUM1B
F13
H2
INA3
F4
II
INB9
FlO
Vee
Hl0
SUM20
Vcd2
L2
INBS
F7
El
Vee
CINO
F7
Hll
SUM21
l3
INB5
F6
FlO
E2
CINl
FB
Jl
INA2
Vcd2
F3
L4
INB4
F5
CSEL2
FlO
E3
CIN2
F9
J2
INAO
Fl
L5
INBl
F2
Vee
A2
Vee
Fll
E9
ClK
FO
J5
INB3
F4
l6
SUM11
El0
GNO
GNO
JS
OElB
F13
l7
SUM10
Verf2
Verf2
I F14
F9
I SUM26
F7
F10
I SUM22
SUM27
Verf2
Ved2
Ved 2
Ved2
Ved2
A3
FlO
Ell
OEHB
F14
J7
SUM9
Ved2
lB
SUM12
Verf2
B8
AD
F13
Fl
SUM17
SUM14
Ved2
F13
F2
Jll
SUM19
Ved2
Vcd2
19
MUXl
Vee
FlO
Jl0
B9
Vee
INA9
.SUM15
Bl0
MUXO
F12
F3
INAB
F9
Kl
INAl
F2
l10
L11
3-41
GND
Vcd2
GND
HSP43168/883
Metallization Topology
GLASSIVATION:
DIE DIMENSIONS:
Type: Nitrox
Thickness: 10kA
314 x 348 x 19 ± 1mils
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Si-AI or li-A'-CU
Thickness: 8k
1.93 x 105 Alcm 2
Metallization Mask Layout
HSP431681BB3
...z
U
z0>
U
:5
!:l
W
W
::;
!:I
W
W
-'
W
0
0
0
...
'"
!C !fl !:l
:l:
~
~
:c '"
0
.
z a: ><
::>
0
CJ
:=
::IE
0
><
::>
::IE
CIN7
CIN6
CINS
CIN4
GND
CIN3
ClK
CIN2
CINl
CINO
GND
INA9
OEH#
INA8
OUT27
INA7
OUT26
INA6
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
Vee
...
ID
3r:
....
ID
3r:
U>
ID
3r:
'"3r:
ID
0
Z
CJ
..
ID
3r:
.,
ID
3r:
'"3r:
ID
Iii
;:
3r:
::>
0
3-42
HSP43216
Halfband Filter
January 1994
Features
Description
• Sample Rates to 52 MSPS
The HSP43216 Halfband Filter addresses a wide variety of
sample frequency)
applications by combining Fsf4 (Fs
quadrature up/down convert circuitry with a fixed coefficient
halfband filter processor as shown in the block diagram.
These elements may be configured to operate in one of the
four following modes: decimate by 2 filtering of a real input
signal; interpolate by 2 filtering of a real input signal; Fsf4
quadrature down conversion of a real input signal followed
by decimate-by-2 filtering to produce a complex analytic
signal; interpolate·by-2 filtering of a complex analytic signal
followed by Fsf4 quadrature up conversion to produce a real
valued output.
• Architected to Support Sample Rates to 104 MSPS
Using External Multiplexer
• Four Modes of Operation:
• Interpolate by 2 Filtering
• Decimate by 2 Filtering
• Quadrature to Real Signal Conversion
• Fsl4 Quadrature Down Conversion Followed by
Decimate by 2 Filtering
• 67 Halfband FIR Filter with 20-BH Coefficients
• 1.24:1 Filter Shape Factor, >9OdB
Attenuation, <0.0003dB Passband Ripple
Stopband
• Two's Complement or Offset Binary Outputs
• Programmable Rounding on Outputs
Applications
• Digital Down Conversion
• D/A and AID pre/post Filtering
• Tuning Bandwidth Expansion for HSP45116 and
HSP45106
=
The frequency response of the HSP43216's halfband filter
has a shape factor, (passband+transition band)/passband,
of 1.24:1 with 90dB of stopband attenuation. The passband
has less than 0.0003dB of ripple from OFs to 0.2Fs with
stopband attenuation of greater than 90dB from 0.3Fs to
Nyquist. At 0.25Fs the filter provides 6dB of attenuation.
The HSP43216 processes data streams with word widths up
to 16-bits and data rates up to 52 MSPS. The processing
through put of the part is easily doubled to rates of up to 104
MSPS by using the part together with an external multiplexer
or demultiplexer. Programmable rounding is provided to sup·
port output precisions from a·bits to 16-bits.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
TYPE
HSP43216GC-52
O"C to +70"C
85 Lead PGA
HSP43216JC-52
O"C to +70"C
84 Lead PLCC
Block Diagram
AINO-15
--...
BINO-15
--...
SYNC /I
USBlLSB /I
MODED-1
---
Fw4
INPUT DATA
QUADRATURE
FLOW
DOWN
CONVERT
CONTROLLER ----I
PROCESSOR
f---t
f---t
67-TAP
HALFBAND
FILTER
PROCESSOR
tT
rf---t
Fw4
QUADRATURE
UP CONVERT
PROCESSOR
T
......
......
I
OUTPUT DATA
FLOW
CONTROLLER!
FORMAITER
-
-
AOUTO-15
BOUTO -15
INTIEXT /I
RNDD-2
FMT 1/
CAUTION: These d""ices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-43
File Number
3365.3
HSP43216
Pinouts
85 PINPGA
TOP VIEW
8
7
6
5
4
3
2
l
BOUT
15
BOUT
13
BOUT
12
BOUT
10
BOUT
GND
BOUT
4
BOUT
1
VCC
GND
RND1
l
K
AOUT
2
AOUT
0
BOUT
14
BOUT
11
BOUT BOUT
II
5
BOUT
3
BOUT
0
OEB#
RND2
BIN1S
K
J
AOUT
3
AOUT
1
BOUT
7
BOUT
2
RNDO
BIN14
J
H
GND
AOUT4
BIN13
BIN12
H
11
10
II
8
BOUT
6
G
AOUT7 AOUT6 AOUT8
BIN8
BIN10
BIN9
G
F
AOUT
10
AOUTS AOUT9
BIN7
BIN6
BIN11
F
E
AOUT
11
AOUT
12
BIN3
BIN4
BINS
E
D
AOUT
14
AOUT
1S
BIN1
BIN2
D
C
GND
OEM
B
VCC
AINO
AIN1
A
FMT
AlN2
AIN3
11
10
AOUT
13
9
lSB#
BINO
C
ClK
SYNC#
INTI
EXTI
B
GND
VCC
AIN10
AIN14
AIN4
AIN7
AIN6
AIN13
MODE
0
AlNS
AIN8
AIN11
AIN12
AIN1S MODE1
8
6
S
USBI
INDEX
PIN
AIN9
4
3
2
8
9
10
A
PIN'A1'
ID
85 PINPGA
BOITOMVIEW
2
3
l
RND1
GND
VCC
K
BIN1S
RND2
OEBIt
J
BIN14
RNDO
H
BIN12
BIN13
G
BIN9
BIN10
F
BIN11
BIN6
4
BOUT1 BOUT4
6
GND
7
BOUT8 BOUT
10
BOUTO BOUT3 BOUTS BOUT9
BOUT
11
BOUT
12
BOUT
13
11
BOUT
15
BOUT
AOUTO AOUT2
14
BOUT2 BOUT6 BOUT7
l
K
AOUT1 AOUT3
AOUT4
GND
H
BIN8
AOUT8 AOUT6 AOUT7
G
BIN7
AOUT
AOUT9 AOUTS
10
F
BIN3
AOUT
12
AOUT
11
E
AOUT
1S
AOUT
14
D
OEM
GND
C
AOUT
13
E
BINS
BIN4
D
BIN2
BIN1
C
BINO
USB INDEX
ILSB.
PIN
B
INTI
EXTI
SYNC.
ClK
A
VCC
GND
MODE1
AIN1S
2
3
4
PIN'A1'
ID
S
AIN14
AIN10
AlN9
MODEO AIN13
AIN6
AlN7
AIN4
AIN1
AINO
vee
B
AIN12
AlN11
AIN8
AINS
AIN3
AIN2
FMT
A
S
6
7
9
10
11
3·44
HSP43216
Pinouts (Continued)
84 LEAD PLCC
TOP VIEW
_0
8~Q~~iiiiii!!~!!!i~zi
>d~iiccccccCCCCCCCCCC
SYNC.
USBIlSBI
INT/EXTI
BINO
BINI
BIN2
BIN3
BIN4
BIN5
BiNi
BIN7
BINI
BINg
BIN10
BINll
BIN12
BIN13
BINI.
BIN15
RNDO
RNDI
•
12
13
14
15
16
17
II
19
20
21
22
74
73
72
71
70
69
23
24
25
26
27
21
29
30
31
32
~M$~n~~~~~u"~~UUU~~~~
S-QUS-5~-555G§QO-N~-~
mzu ~ ~~
S z------
~~~>oogogoooo
mm
m mmmmm
3-45
~~~~~~S
gggggg
FMT
OEAI
vee
GND
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
AOUT9
AOUTI
AOUT7
AOUT6
AOUT5
GND
AOUT4
AOUT3
AOUT2
AOUTI
AOUTO
HSP43216
Pin Description
NAME
PLCCPIN
TYPE
DESCRIPTION
VCC
11,36,72
-
GND
9,35,47,59,71
CLK
10
I
Clock Input (CMOS LEVEL)
AIND-15
75 -84,1 -6
I
Input Data Bus A. AINO is the LSB. Input data format is 16-bit Two's
Complement
BINO-15
15- 30
I
Input Data Bus B. BINO is the LSB. Input data format is 16-bit Two's
Complement
MODEO-1
7,8
I
The Mode Select Inputs set one of four operational modes as
highlighted in Table 1.
INT/EXT'
14
I
The Internal\External multiplexer select inputs set whether the data
multiplex/demultiplex function required in the various operational
modes is performed internally (High State) or externally to the chip
(Low State).
SYNC.
12
I
This input is used to synchronize the input sample stream with the zero
degree phase of the up or down convert Local Oscillators. In the
straight decimate modes, this input can be use to synchronize the input
sample stream with a particular phase of the halfband filter. (See the
Operational Modes Section for additional information)
USBlLSB#
13
I
The Upper and Lower Sideband select line is used to specify the
direction of frequency translation imparted on the data stream in the
Up Convert and Quadrature to Real Convert Modes. (See Operational
Modes Section for additional information)
RNDD-2
31 -33
I
The Round Select inputs set the number of output bits from eight
(RND=OOO) to sixteen (RND=ll0). Least significant output bits are
zeroed. See Table 4.
OEM
73
I
Three State Control Output Bus A, OUTAO-15. Active Low.
OEB#
34
I
Three State Control Output Bus B, OUTBO-15. Active Low.
FMT
74
I
The Format select input is used to convert the two's complement
output to offset binary (unsigned). When asserted high, the AOUT15
and BOUT15-bits are inverted from the normal two's complement
representation.
AOUTO-15
54-58,60-70
0
Output Bus A. AOUTO is the LSB.
BOUTO-15
37-46,48-53
0
Output Bus B. BOUTO Is the LSB.
+5V Power
Ground
3-46
HSP43216
INPUT DATA FLOW
CONTROLLER
AOUTG-15
·
····
**:·
R:
1,1,-1,.:
,
BOUTG-15
a
E
I,
I,
:.g-GTrm''-Tjm-uuJ LuummmJ:---u-U---I-I-"--muTrrj-----j
E EX: : G
::
::
':
RNDD~ ------------------------------------------------------------~FMT#
I
OEB.
_
** INDICATES ELEMENTS WHICH OPERATE AT CLK12 WHEN THE INTIEXT# CONTROL INPUT IS HIGH.
FIGURE 1. HALFBAND BLOCK DIAGRAM
Functional Description
Input Data Flow Controller
The operation of the HSP43216 centers around a fixed
coefficient. 67-Tap, Halfband Filter Processor as shown in
Figure 1. The Halfband Filter Processor operates stand
alone to provide two fundamental modes of operation,
interpolate or decimate by two filtering of a real signal. In two
other modes, the Quadrature Up/Down Convert circuitry
operates together with the Filter Processor block to provide
Fsl4 Down Conversion with decimate by 2 filtering or
Quadrature to Real Conversion.
The Input Data Flow Controller routes data samples from the
AIN0-15 and BIN0-15 inputs to the internal processing
elements of the Halfband. The data routing paths are based
on mode of operation and are more fully discussed in the
Operational Modes section.
In Down Convert and Decimate mode, a real input sample
stream is spectrally shifted by Fsl4. Each component of the
resulting complex signal is then halfband filtered and
decimated by 2 to produce real and imaginary output
samples at half of the input data rate.
In Quadrature to Real Conversion mode, the real and imaginary components of a quadrature input are interpolated by
two and halfband filtered. The filtered result is then spectrally
shifted by Fsl4 and the real component of this operation is
output at twice the input sample rate.The HSP43216 is configured for different operational modes by setting the state of
the mode control pins, MODE1-0 as shown in Table 1.
TABLE 1. MODE SELECT TABLE
MODE1-0
MODE
00
Decimate by Two
01
Interpolate by Two
10
Down Convert and Decimate
11
Quadrature to Real Conversion
Fg4 Quadrature Down Convert Processor
The Fsl4 Quadrature Down Convert Processor operates as
a Quadrature LO which provides the negative Fsl4 spectral
shift required to center the upper sideband of a real input
signal at DC. This operation is equivalent to multiplying the
real sample stream, x(n), by the quadrature components of
the complex exponential e-i(irl2)n as given below:
x(n)e-j (ltn/2) = x(n)cos(ltn/2) +jx(n) sin (-ltn12)
For added flexibility, a spectrally reversed version of the
above process may be realized by configuring the Down
Convert processor to impart a positive Fsl4 spectral shift on
the input signal. This has the effect of centering the lower
sideband of the input signal at DC and is achieved by
reversing the sign of the sine term in the quadrature mix as
shown below:
x (n) ej (ltn/2) = x (n) cos (ltn/2) + jx (n) sin (ltn/2)
The direction of the spectral shift imparted by the Down
Convert Processor is set by the Upper Sideband! Lower
Sideband control input, USB/LSB#. When this input is
"High", a -Fsl4 spectral shift is used to center the input
signal's upper sideband at DC. When asserted low, a
spectral shift of Fsl4 is used to center the lower sideband at
3-47
TABLE 2. FREQUENCY RESPONSE OF THE 67-TAP HALFBAND FILTER NORMALIZED TO THE SAMPLE RATE
FREQUENCY
(NORMALIZED)
~
00
MAGNITUDE
(dB)
FREQUENCY
(NORMALIZED)
MAGNITUDE
(dB)
FREQUENCY
(NORMALIZED)
MAGNITUDE
(dB)
FREQUENCY
(NORMALIZED)
MAGNITUDE
(dB)
0.000000
-0.000256
0.125000
-0.000278
0.250000
-6.020594
0.375000
-90.469534
0.003906
-0.000143
0.128906
-0.000098
0253906
-7.989334
0.378906
-91.528735
0.007812
-0.000071
0.132812
0.000001
0.257812
-10.364986
0.382812
-98.960202
0.011719
-0.000013
0.136719
o.oooon
0.261719
-13.194719
0.386719
-105.235066
0.015625
-0.000004
0.140625
0.000166
0.265625
-16.533196
0.390625
-97.073218
0.019531
-0.000001
0.144531
0.000106
0.269531
-20.447622
0.394531
-101.790858
-103.660592
0.023438
0.000032
0.148438
0.000015
0.273438
-25.024382
0.398438
0.027344
-0.000000
0.152344
-0.000022
0.2n344
-30.379687
0.402344
-96.903272
0.031250
-0.000026
0.156250
-0.000048
0.281250
-36.6794n
0.406250
-97.160860
-106.804655
0.035156
0.000002
0.160156
-0.000074
0.285156
-44.169450
0.410156
0.039062
0.000036
0.164062
-0.000022
0.289062
-53.259353
0.414062
-96.213761
0.042969
0.000050
0.167969
0.000005
0.292969
-64.619008
0.417969
-91.368358
-91.202963
0.046875
0.000021
0.171875
0.000009
0.296875
-79.291213
0.421875
0.050781
0.000008
0.175781
0.000041
0.300781
-90.24n48
0.425781
-96.903271
0.054688
-0.000012
0.179688
0.000095
0.304686
-91.540418
0.429688
-1 03.058722
0.058594
-0.000140
0.183594
0.000090
0.308594
-96.987389
0.433594
-92.156508
0.062500
-0.000226
0.187500
-0.000012
0.312500
-97.990997
0.437500
-90.24n41
0.066406
-0.000138
0.191406
-0.000037
0.316406
-94.450644
0.441406
-91.623161
0.070312
0.000010
0.195312
-0.000145
0.320312
-94.268681
0.445312
-98.760392
0.074219
0.000036
0.199219
-0.000208
0.324219
-97.250387
0.449219
-103.883238
0.078125
0.000179
0.203125
-0.000927
0.328125
-103.660592
0.453125
-96.861830
0.082031
0.000190
0.207031
-0.005089
0.332031
-105.940671
0.457031
-96.987388
-100.046559
0.085938
0.000064
0.210938
-0.018871
0.335938
-98.212931
0.460938
0.089844
0.000011
0.214844
-0.053894
0.339844
-94.313447
0.464844
-1 06.804655
0.093750
-0.000064
0.218750
-0.128250
0.343750
-95.354251
0.468750
-104.119091
0.097656
-0.000018
0.222656
-0.266964
0.347656
-98.447393
0.472656
-105.235066
0.101562
-0.000000
0.226562
-0.501238
0.351562
-103.249457
0.476562
-104.637666
0.105469
0.000020
0.230469
-0.866791
0.355469
-93.387604
0.480469
-1 05.940673
0.109375
0.000053
0.234375
-1.401949
0.359375
-91.390894
0.484375
-107.323099
0.113281
0.000012
0.238281
-2.145948
0.363281
-94.404415
0.488281
-102.375213
0.117188
-0.000022
0.242188
-3.137997
0.367188
-103.883234
0.492188
-94.009640
0.121094
-0.000149
0.246094
-4.416657
0.371094
-93.245384
0.496094
-91.312516
,
....
~~
0)
HSP43216
Fg4 Quadrature Up Convert Processor
DC. The SYNC# control input may be used to synchronize
the incoming data stream with the zero degree phase of the
complex exponential as described in the Operational Modes
section.
The Fsl4 Quadrature Up Convert Processor provides the
Fsl4 spectral shift used to construct a real signal from a
complex sample stream. The operation performed is
equivalent to multiplying a quadrature data stream,
i(n)+jq(n), by samples of a complex exponential, e-i(nJ2)n, and
outputting the real part of that mathematical operation as
given below:
The real and imaginary sample streams generated by the
down convert operation are passed to the Halfband Filter
block on the upper and lower processing legs respectively.
The Down Convert Processor is only active in Down Convert
and Decimate Mode, MODE1-0
10. In the other modes,
the data on the upper and lower processing legs pass
unaltered.
=
Real { (i (n) + jq(n) ) e j (ltnl2) }
Real (Ii (n) cos (ltn/2) - q(n) sin (ltn/2))
+ j Ii (n) sin (ltnl2) + q(n) cos (ltn/2))}
67-Tap Halfband Filter Processor
i (n) cos (ltn/2) - q(n) sin (Itnl2)
The processing required to implement the 67-Tap Halfband
filter is distributed across two polyphase branches
comprised of even and odd tap filters as shown in Figure 1.
The Even Tap Filter performs a filtering operation using the
even indexed coefficients (even phase) of the halfband filter.
The Odd Tap Filter uses the odd indexed coefficients (odd
phase) of the halfband filter. Note: the odd tap filter's
processing reduces to a delay and scale operation since the
center tap is the only non-zero odd tap for a halfband filter.
Together the polyphase filters perform the sum of-products
required to implement the 67 tap halfband filter in an
architecture capable of supporting a variety of operational
modes. The frequency response of the halfband filter is
given graphically in Figure 2 and in tabular form in Table 2.
The polyphase implementation of the halfband filter provides
the flexibility to realize a variety of filter configurations. In
Decimate by Two Mode, the outputs of the each polyphase
branch are summed to yield the filter output. In Interpolate
by Two mode, the polyphase filters produce independent
outputs which are multiplexed into a single sample stream at
the interpolated data rate. In the Up Convert and Down
Convert Modes, the polyphase branches filter the real and
imaginary components of a complex sample stream with the
equivalent of identical 67-Tap Halfband Filters. For these
modes, the real component is processed by the Even Tap
filter and the imaginary component is processed by the Odd
Tap filter. The Operational Modes Section provides further
details regarding the data flow and operation of the Filter
Processor for the various modes.
o
\
-18
\
iii' -36
i (n) cos (Itn/2) + q(n) sin (-1tn/2)
In the above operation, a positive Fsl4 spectral shift is
imparted on the quadrature input which causes the upper
sideband of the resulting real output to be defined by the
spectral content of the input signal. For added flexibility, the
Up Convert processor may be configured to impart a
negative Fsl4 shift on the quadrature input which generates
a real output whose lower sideband is defined the spectrum
of the quadrature input. The state of the USB/LSB# control
input determines the direction of the spectral shift. If this
input is set "High", a positive Fsl4 shift is introduced by the
Up Convert Processor. If USB/LSB# is asserted "Low", a
negative Fsl4 spectral shift is introduced.
The Up Convert Processor implements the up convert
operation by multiplying the in-phase and quadrature
samples on the upper and lower processing legs by the
nonzero sine and cosine terms in the above expression. The
resulting data is then multiplexed together in the Output Flow
Controller to yield the real output sample stream. The
SYNC# control input may be used to align the zero degree
phase of the Up Convert LO with a particular input sample
as described in the Operational Modes Section.
The Up Convert Processor also scales the data streams
output from the Filter Processor as required by the
operational mode. In the modes which employ interpolation,
the Up Convert Processor scales the Filter Processor's
output by two to compensate for the attenuation of one half
caused by the interpolation process. In down convert and
decimate mode, the filter processor output is also scaled by
two to compensate for the attenuation introduced by the
down covert process. The scaling operations performed are
summarized in Table 3.
TABLE 3. SCALE FACTORS APPLIED BY UP CONVERT
PROCESSOR vs MODE
e.w
0-54
E
z
MODE
SCALE FACTOR
~ -72
-91
-109
0.0
0.1
rn~ ltvJ
"
0.2
0.25
0.3
NORMALIZED FREQUENCY
0.4
0.5
FIGURE 2. FREQUENCY RESPONSE OF 67 - TAP HALF BAND
FILTER
3-49
Decimate by Two (MODE1-0 = 00)
1.0
Interpolate by Two (MODE1-0 = 01)
2.0
Down Convert and Decimate (MODE1'() = 10)
2.0
Quadrature to Real (MODE1-0 =11)
2.0
HSP43216
Output Data Flow Controller
The Output Flow Controller routes data to the AOUTO-15
and BOUTO-15 output depending on mode of operation. In
decimate by two mode (MODE1-0
00). output from the
filter processor's polyphase branches are summed and
output through AOUTO-15. In Down Convert and Decimate
mode (MODE1-0
10). real and imaginary data streams
produced by the down convert process pass are output
directly to AOUTO-15 and BOUTO-15 respectively. In the two
modes using interpolation. MODE1-0 = 01 or 11. with
internal multiplexing enabled. INT/EXT# set high. data sam
pies output from the polyphase branches are internally multiplexed into a single stream and output via AOUTO-15. If a
mode using interpolation is specified together with external
multiplexing. INT/EXT# set low. the data stream multiplexing
is performed off chip and the data on the upper and lower
processing legs is output through AOUTO-15 and BOUT015.
X3.X2.Xl.XO
=
TABLE 4. OUTPUT ROUNDING CONTROL
RND
2-0
ROUND FUNCTION
000
Round output to 8-bits. AOUTl5-8 and BOUT15-8. zero
lower bits.
001
Round output to 9-bits. AOUT15-7 and BOUT15-7. zero
lower bits.
010
Round output to 1Q-bits. AOUT15-6 and BOUT15-6. zero
lower bits.
011
Round output to l1-bits. AOUT15·5 and BOUT15-5. zero
lower bits.
100
Round outputto 12-bits. AOUT15·4 and BOUT15-4. zero
lower bits.
101
Round output to 14-bits. AOUT15·2 and BOUT15-2. zero
lower bits.
110
Round output to 16·bits. AOUT15-0 and BOUT15-0.
111
Zero all outputs.
111 • t ~ ...
co Cl
C2 C3 C4 C5 C 6 i " l ! . J "
Y4.Y2.YO
Y(O) = XO(CO)+Xl (Cl )+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)
, Y(l) Xl (CO)+X2(Cl )+X3(C2)+X4(C3)+X5(C4)+X6(C5)+X7(C6)
Y(2) .. X2(CO)+X3(Cl)+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)
=
=
The Output Data Flow Controller also sets the binary format
and precision of the parts two 16-bit outputs. The data format is specified as either two's complement (FMT input low)
or offset binary (FMT input high). The preCision of the output
data is set from 8 to 16-bits via the round control inputs.
RND2-0. The RND2-0 inputs round the output data to a
precision ranging from 8 to 16-bits as specified in Table 4.
Saturation logic is incorporated in the output flow controller
to insure that numerical growth associated with a worst case
signal input or rounding condition saturates to a 16-bit value.
t.
, Y(3) .. X3(CO)+X4(Cl )+X5(C2)+X6(C3)+X7(C4)+X8(C5)+X9(C6)
•
•
•
'INDICATES SAMPLES DISCARDED BY DECIMATION PROCESS
FIGURE 3. TRANSVERSAL IMPLEMENTATION OF DECIMATE
BY 2 HALFBAND FILTER
By inspecting the sum-of-products for the decimated output
in Figure 3. it is seen that even indexed input samples are
always multiplied by the even filter coefficients and the odd
samples are always multiplied by the odd coefficients. This
computational partitioning is realized in the polyphase
implementation shown in Figure 4.
In the polyphase implementation. the input data is broken
into even and odd sample streams which are processed by a
set of polyphase filters running at one half of the input data
rate. These filters are deSignated as even or odd tap filters
depending upon whether the coefficients were derived from
the even or odd indexed coefficients of the original
transversal filter. This architecture only produces the outputs
which are not discarded by the decimation proces. NOTE:
since the only non-zero tap for a halfband filter is the center
tap. the Odd Tap Filter reduces to a delay and multiply
operation.
The operation of the HSP43216 in Decimate by Two mode is
analogous to the polyphase implementation in Figure 4. In
this mode. the internal data paths are routed as shown in
Figure 5A and Figure 58. The different data flows depend on
whether internal or external multiplexing has been selected
using the INT/EXT# control input. In either case. an input
data stream is decomposed into even and odd sample
streams which are then routed to the even and odd tap
polyphase filters. The output of each polyphase filter is
summed and output via AOUTO-15.
EVEN TAP ALTER
•.• ,x4.X2.XO
COC2 C4 C6
~D
•..• X5.X3.Xl
R
EI-t
~
Operational Modes
TAP FILTER
..• Y2.Yl.YO
+
1
• •
C1C3C5
Y(O) = XO(CO)+Xl (Cl )+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)
Y(l) = X2(CO)+X3(Cl )+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)
Decimate By 2 Filter Mode (Model-0= 00)
The concept of operation for Decimate by Two Filter mode is
most easily understood by comparing the 7 tap transversal
filter implementation to the equivalent polyphase
implementation. The transversal implementation is shown in
Figure 3.
3-50
•
••
FIGURE 4. POLYPHASE IMPLEMENTATION OF DECIMATE BY
2 HALFBAND FILTER
HSP43216
**
**
**
DELAY 2 -35
**
EVEN TAP
FILTER
**
DELAY 111
ODD TAP
FILTER
** CLOCKED AT CLKJ2
FIGURE 5A_ DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INTJEXT'
=1)
DELAY 2- 35
EVEN TAP
FILTER
DELAY 19
ODD TAP
FILTER
~
w
FIGURE 5B_ DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INTJEXT'
=
If internal multiplexing is selected (INT/EXT# 1), the input
data stream is decomposed into even and odd samples
internally by the processing elements operating at one half
of the input ClK (see elements marked by···.. in Figure 5A).
In this mode, the Data Flow Controller routes data samples
input through AINO-15 to upper and lower processing legs
with a one sample relative delay. Since a new data sample is
clocked into either of the processing legs at ClKl2, each leg
processes a data stream comprised of every other input
sample, and the one sample relative delay of each leg's
input forces the even samples to be clocked into one leg
while the odd samples are clocked into the other. The user
may choose which sample gets routed to the upper (even)
processing leg by asserting SYNC#. Specifically, a sample
input on the ClK following the assertion of SYNC# will be
routed to the upper processing leg as shown in Figure 6.
With internal multiplexing, the minimum pipeline delay on the
upper processing leg is 14 ClK's and the pipeline delay on
the bottom leg is 47 ClK's. The filtered and decimated data
stream is held on AOUTO-15 for 2 ClK's.
I! external multiplexing is selected (INT/EXT# = 0), a
demultiplex function is required off chip to break the input
data into even and odd sample streams for input through
AINO-15 and BINO-15. In this mode, the Data Flow Controller
routes the even and odd sample streams directly to the
following processing elements which are all running at the
input ClK rate. This allows the device to perform decimate
by two filtering on signals sampled at up to twice the
maximum ClK rate of the device (104 MSPS). With external
multiplexing, the minimum pipeline delay through the upper
processing leg is 9 ClK's and the pipeline delay through the
lower processing leg is 26 ClK's as shown in Figure 5B. In
!:i
=0)
u:::
this mode, SYNC# has no effect on part operation. NOTE:
for proper operation, the samples demultiplexed to the AINO15 input must precede those input to the BINQ-15 input in
sample order. For example, given a data sequence xO, x1,
x2 and x3, the demultiplex function would route xO and x2 to
AINO-15 and x1 and x3 to BINQ-15.
o
1
2
CLK~:::
!~
SYNCI
AIN0-15
:
:
i~
EVEN!
ODD 1
EVEN
INPUTS DESIGNATED AS EVEN ARE PROCESSED ON THE UPPER
LEG, INPUTS DESIGNATED AS ODD ARE PROCESSED ON THE
LOWER LEG.
FIGURE 6. DATA SYNCHRONIZATION WITH PROCESSING
LEGS (INTJEXT# 1)
=
Interpolate By 2 Filter Mode (Mode1-0 = 01)
As with the Decimate by Two mode the concept of operation
for the Interpolate by Two Filter mode is more easily
understood by comparing a 7 tap transversal filter
implementation to the equivalent polyphase implementation.
The transversal implementation is shown in Figure 7.
By inspecting filter outputs in Figure 7, it is seen that the
even indexed outputs are the result of the sum-of-products
for the odd coefficients, and the odd indexed outputs are
theresult of the sum-of-products lor the even coefficients.
This computational partitioning is evident in the polyphase
implementation shown in Figure B.
3-51
....Q
HSP43216
7 TAP HALFBAND FILTER
•••X2,X1,xO
f
2
t.lll.t
•.x1.0.XO.O
co C1
....Y1.YO
C2 C3C4 CSC6
YeO) = O(CO)+XO(C1)+O(C2)+X1(C3)+O(C4)+X2(C5)+O(C6)
V(1) = XO(CO)+O(C1 )+X1 (C2)+O(C3)+X2(C4)+O(CS)+X3(C6)
V(2) = O(CO)+X1 (C1)+O(C2)+X2(C3)+0(C4)+X3(CS)+0(C6)
Y(3) = X1 (CO)+O(C1)+X2(C2)+O(C3)+X3(C4)+O(C5)+X4(C6)
.
FIGURE 7. TRANSVERSAL IMPLEMENTATION OF
INTERPOLATE BY TWO HALFBAND FILTER.
EVEN TAP FILTER
•••Y5.Y3.Y1
••••X2.X1.XO
COC2 C4 C6
ODD TAP FILTER
.I .
C1 C3 C5
•••Y4.Y2,YO
YO =XO(C1 )+X1 (C3)+X2(C5)
Y1 = XO(CO)+X1 (C2)+X2(C4)+X3{C6)
Y2 = X1 (C1 )+X2(C3)+X3(C5)
.
FIGURE 8. POLYPHASE IMPLEMENTATION OF
INTERPOLATE BY TWO HALFBAND FILTER
In the polyphase implementation. the input data stream
feeds even and odd tap filters running at the input sample
rate. The interpolated sample stream is derived by
multiplexing the output of each polyphase branch into a
single data stream at twice the input sample rate. As in the
Decimate by Two example. the even or odd tap filters are
comprised of the even or odd indexed coefficients from the
original transversal filter.
The operation of the HSP43216 in Interpolate by Two mode
is analogous to the polyphase example above. In this mode
the internal data flow is routed as shown in Figure 9A and
Figure 98. The different data flows depend on the selection
of internal or external multiplexing via INT/EXT.. In this
mode. data input through AINO-15 is fed to the even and odd
polyphase branches of the filter processor. The output of
each branch is multiplexed together to generate the output
data stream at the interpolated rate. NOTE: the output of
each polyphase branch is scaled by two to compensate for
the attenuation of one half caused by interpolation.
If internal multiplexing is selected (INT/EXT# = 1). the data
stream input through AINO-1S is fed to both the upper and
lower processing legs as shown in Figure 9A. The output of
each processing leg is then multiplexed together to produce
the interpolated sample stream at twice the input sample
rate. In this mode the device is clocked at the interpolated
data rate to support the multiplexing of each processing leg's
output into a single data stream. The upper and lower
processing legs each run at the input data rate of ClK12 as
indicated by the ..... marking the various registers and
processing elements in Figure 9A. In this mode, data samples are clocked into the part on every other rising edge of
ClK. The SYNC' Signal is used to specify which set of ClK
FIGURE 9A. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INT/EXT.
=1)
1-1>-+ AOUT0-15
OEA#
BOUT0-15
OEB.
FIGURE 9B. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INTIEXT# = 0)
3-52
HSP43216
INPUT SIGNAL SPECTRUM
cycles are used to register data at the part's input. Specifically, every other rising edge of ClK starting one ClK after
the assertion of SYNC# will be used to clock data into the
part. With internal multiplexing the minimum pipeline delay
through the upper processing leg is 15 ClK's and the pipeline delay through the lower processing leg is 48 ClK's.
/\/'~~\l'.,
Fsf2
Fs
DOWN CONVERTED SIGNAL
II external multiplexing is selected (INT/EXT# = 0), the upper
and lower processing legs are output through AOUTD-15
and BOUTO-15 for multiplexing into a single data stream off
chip.This allows the processing legs to run at the maximum
clock rate which coincides with an interpolated output data
rate of 104 MSPS. NOTE: the samples output on BOUTD-15
precede those on AOUTD-15 in sample order. This requires
a multiplexing scenario in which BOUTO-15 is selected
before AOUTO-15. With external multiplexing, the minimum
pipeline delay through the upper processing leg is 9 ClK's
and the pipeline delay through the lower processing leg is 26
ClK's as shown in Figure 9B. In this mode SYNC# has no
effect on part operation.
Down Convert and Decimate Mode (MODE1-0
o
-FII2
-FII2
Fsf2
Fs
FILTERED SIGNAL
~/ FILTER PASSBAND
ILPl
I
0
FsJ2
-F1I2
1:1'1.
Fs
DECIMATED OUTPUT SIGNAL SPECTRUM
= 10)
L0,b4\L(\
In Down Convert and Decimate Mode a real input signal is
spectrally shifted -Fsl4 which centers the upper sideband at
DC. This operation produces real and imaginary
components which are each filtered and decimated by
identical 67 -tap halfband filters. For added flexibility, a
positive Fs/4 spectral shift may be selected which centers
the lower sideband at DC. The direction of the spectral shift
is selected via USB/lSB# as described in the Quadrature
Down Convert section. A spectral representation of the down
convert and decimate operation is shown in Figure 10 (USB/
lSB#=1). NOTE: each of the complex terms output by the
Filter Processor are scaled by two to compensate for the
attenuation of one half introduced by the down conversion
process.
o
2F·s
FS = INPUT SAMPLE RATE
F's = DECIMATED SAMPLE RATE,Fsf2
FIGURE 10. DOWN CONVERT AND DECIMATE OPERATION
HALFBAND FILTER
t •
111• t
CO Cl C2 C3 C4 CS C6
HALFBAND FILTER
The Down Convert and Decimate mode is most easily
understood
by
first
considering
the
transversal
implementation using a 7 tap filter as shown in Figure 11.
t.lll.t
By examining the combination of down conversion, filtering
and decimation, it is seen that the real outputs are only
dependent on the sum-of-products for the even indexed
samples and filter coefficients, and the imaginary outputs
are only a function of the sum-of-products for the odd
indexed samples and filter coefficients. This computational
partitioning allows the quadrature filters required after down
conversion to be realized using the same poly-phase
processing elementsused in the previous two modes.
CO Cl C2 C3 C4 CS C6
~I~(~~)
REAL OUTPUTS
=
=
=
RO XO(CO)+O(Cl )-X2(C2)+0(C3)+X4(C4)+O(CS)-X6(C6)
, Rl = 0(CO)-X2(Cl)+0(C2)+X4(C3)+0(C4)-X6(CS)+0(C6)
R2 -X2(CO)+0(Cl)+X4(C2)+O(C3)-X6(C4)+0(CS)+X4(C6)
, R3 0(CO)+X4(Cl )+0(C2)-X6(C3)+0(C4)+X4(CS)+0(C6)
A functional block diagram of the polyphase implementation
is shown in Figure 12. In this implementation, the input data
stream is broken into even and odd sample streams and
processed independently by the even and odd tap filters. By
decomposing the sample stream into even and odd samples,
the zero mix terms produced by the down convert lO drop
out of the data streams, and the output of each of the filters
represent the decimated data streams for both the real and
imaginary outputs.
.
IMAGINARY OUTPUTS
10 = 0(CO)-Xl(Cl)+0(C2)+X3(C3)+0(C4)-XS(CS)+0(C6)
, 11 = -Xl (CO)+O(Cl )+X3(C2)+0(C3)-XS(C4)+0(CS)+X7(C6)
12 0(CO)+X3(C1 )+0(C2)-X5(C3)+0(C4)+X7(C5)+0(C6)
• 13 X3(CO)+O(C1 )-XS(C2)+0(C3)+X7(C4)+0(CS)-X9(C6)
=
=
'INDICATES SAMPLES DISCARDED BY DECIMATION PROCESS
FIGURE 11. DOWN CONVERT AND DECIMATE FUNCTION
USING TRANSVERSAL FILTERS
3-53
tn
a:
w
~
u:::
....c
HSP43216
EVEN TAP FILTER
the real (In-phase) component of the quadrature down
conversion and the lower leg processes the complex
(Quadrature) component of the down conversion. The filter
processing block implements the equivalent of a decimate by
two Halfband filter on each of the quadrature legs.
•••• R1.RO
co C2C4 CS
1.-1.1.-1 •••
COSLO
If internal multiplexing is specified (INT/EXT# = 1). the upper
and lower processing legs are fed with even and odd sample
streams which are derived from data input through AINO-15.
The input sample stream may be synchronized with the zero
degree phase term of the down converter lO by using the
SYNC# control input. For example. an input data sample will
be fed into the real (upper) processing leg and mixed with
the zero degree cosine term of the quadrature lO if it is input
on the 4th ClK following the assertion of SYNC# as shown
in Figure 14. The pipeline delay through the real proceSSing
leg (upper leg) is 14 ClK's and the delay through the
imaginary processing leg (lower leg) is 47 ClK·s. The
complex samples output through AOUTO-15 and BOUTO-15
are present for 2 ClK's since the quadrature streams have
been decimated by two in the filter processor.
ODD TAP FILTER
R
l---.lE
G
. I.
....11.10
C1 C3 C5
..1,1,-1,1 ..
SINLO
REAL OUTPUTS
RO .. XO(co)-X2(C2)+X4(C4)-X6(C6)
R1 • -X2(CO)+X4(C2)-X6(C4)+X8(CS)
R2 .. X4(CO)-X6(C2)+X8(C4)-X1 O(CS)
.
IMAGINARY OUTPUTS
10 .. -X1 (C1)+X3(C3)-XS(CS)
11 • X3(C1)-XS(C3)+X7(CS)
12 .. -XS(C1)+X7(C3)-X9(CS)
.
FIGURE 12. DOWN CONVERT AND DECIMATE FUNCTION
USING POLVPHASE FILTERS
The HSP43216's implementation of Down Convert and
Decimate mode is analogous to the polyphase solution
shown in Figure 12. The part's data flow diagram for this
mode is shown in Figure 13A and Figure 13B. As seen in the
figures. the input sample data is broken into even and odd
sample streams which feed the upper and lower processing
legs as described in the Decimate By 2 Mode section. The
data on each processing leg is then modulated with the non
zero quadrature components of the complex exponent (see
Quadrature Down Convert Section). Following this
operation, the upper leg becomes the processing chain for
**
Sy:~K~i
2
1
A1NO-15
3
jOi
i
i
:
:
i
1
:~
.
:
:
:
!
:
:
;
;
0:
0:
o·
i
;
1
!
!
i
THE SAMPLE DESIGNATED BY THE 0° AND 1800 LABELS ARE
MIXED WITH THE RESPECTIVE COSINE TERMS ON THE UPPER
PROCESSING LEG. AND THE OTHER SAMPLES. THOSE LABELED
BY 800 AND 2700. ARE MIXED WITH THE RESPECTIVE SINE TERMS
ON THE LOWER LEG.
FIGURE 14. DATA SYNCHRONIZATION TO 00 PHASE OF
QUADRATURE LO
DELAY 2-35
EVEN TAP
FILTER
OEAI
**
0
!
DELAY19
ODD TAP
FILTER
.. CLOCKED AT CLK12
FIGURE 13A. DATA FLOW DIAGRAM FOR DOWN CONVERT AND DECIMATE MODE (INT/EXTIT
=1)
DELAY 2-35
EVEN TAP
FILTER
DELAY 19
ODD TAP
FILTER
FIGURE 13B. DATA FLOW DIAGRAM FOR DOWN CONVERT AND DECIMATE MODE (INT/EXTIT
3-54
=0)
HSP43216
If external multiplexing is selected (lNT/EXT# = 0), a
demultiplex function is required off chip to break the input
data stream into even and odd samples for input through
AINO-15 and BIND-15. In this mode, the real and imaginary
processing legs run at the input clock rate which allows the
device to perform the down convert and decimate function
on real signals sampled at up to twice the maximum speed
grade of the device (104 MSPS). With external multiplexing,
the minimum pipeline delay through the upper processing
leg is 9 ClK's and the pipeline delay through the lower
processing leg is 26 ClK's as shown in Figure 13B. To
synchronize the even samples input through AIND-15 with
the zero degree cosine term of the quadrature la, SYNC#
should be asserted on the same clock that the target sample
is present at the input of the part as shown in Figure 15.
NOTE: for proper operation, the samples demultiplexed to
the AINO-15 input must precede those input to the BINO-15
input in sample order. For example, given a data sequence
xO,x1,x2,and x3, the demultiplex function would route xO and
x2to AINO-15 and x1 and x3to BINO-15.
A functional block diagram of the polyphase implementation
for Quadrature to Real Conversion mode is shown in Figure
18. In this implementation, the real and imaginary
components of a complex input stream drive the even and
odd tap filters. The output of each filter is then modulated by
the non-zero mix factors and multiplexed into a single real
output stream.
o
-FS
FS
2FS
INTERPOLATED SIGNAL
~/ FILTER PASSBAND
~Ik(\l,
UPCONVERTED SIGNAL
~I ~
CLK
SYNCI
~
/\I~/'~
THE 00 AND 1800 LABELS INDICATE THE PHASE ALIGNMENT OF
THE SAMPLES INPUT THROUGH AINO-15 WITH THE COSINE TERM
OF THE QUADRATURE DOWN CONVERT LQ.
FIGURE 15. DATA SYNCHRONIZATION WITH PHASE OF DOWN
CONVERTLO
F's
Quadrature to Real Conversion Mode (MODE1-0 = 10)
u::
...
Q
FS = INPUT SAMPLE RATE
= INTERPOLATED SAMPLE RATE, 2Fs
FIGURE 16. QUADRATURE TO REAL CONVERSION
The Quadrature to Real Conversion mode is used to
construct a real output from a quadrature input. To
accomplish this, the Halfband Filter Processor interpolates
the quadrature components of the complex input Signal by a
factor of two. Next, the Quadrature Up-Convert Processor
spectrally shifts the signal by Fsl4 and derives the real
output as described in the Fsl4 Quadrature Up-Convert
Processor Section. The direction of the spectral shift is
controlled via the USB/lSB# input and is used to designate
the frequency content of the complex input as either the
upper or lower sideband of the resulting real output signal. A
spectral representation of quadrature to real conversion is
shown in Figure 16 for USB/lSB# = 1. NOTE: the Fsl4 UpConvert Processor uses quadrature mix factors scaled by
two to compensate for the attenuation introduced by the
interpolation process.
The Quadrature to Real Conversion mode is most easily
understood by first considering an implementation using a 7
tap transversal filter as shown in Figure 17. By examining the
combination of interpolation, filtering, and up conversion it is
seen that a particular output is only dependent on the sumof-products for the even indexed samples and coefficientsor
the sum-of-products for the odd indexed samples and
coefficients. This computational partitioning allows the dual
interpolation filters required in this m ode to be realized using
the same poly-phase filter structure used in the other modes.
As in the other modes, the operation of the HSP43216 in
Quadrature to real Conversion mode is analogous to that of
the polyphase solution described above. The data flow
diagrams for this particular mode are shown in Figures 19A
and 19B.
HALFBAND FILTER
COS«n+l)l --....:..:..---'-----'Hdec Fdec
3-69
(1.0)
~
W
!::;
it
Q
..-
HSP43220
This equation expresses the minimum FIR_CK. The minimum FIR_CK is the smallest integer multiple of CLIN
that satisfies equation 1.0. In addition, the TSK specification
must be met (see A.C. Electrical Specifications). Fdec is the
decimation rate in the FIR (Fdec = F_DRATE +1), where
TAPS = the number oftaps in the FIR for even length filters
and equals the number of taps+1 for odd length filters.
Solving the above equation for the maximum number of
taps:
TAPS = 2 (FIR
g~~c
Fdec _ Fdec -4)
(2.0)
In using this equation, it must be kept in mind that CLIN/
Hdec must be less than or equal to 4MHz (unless the HDF is
in bypass mode in which case this limitation in the HDF
does not apply). In the OPERATIONAL SECTION under the
Design Considerations, there is a table that shows the
trade-offs of these parameters. In addition, Harris provides
a software package called DECI. MATEN which designs
the DDF filter from System specifications.
The registered outputs of the data RAM are added or
subtracted in the 17 bit pre-adder. The F_OAD control bit
allows zeros to be input into one side of the pre-adder. This
provides the capability to implement non-symmetric filters.
The selection of adding the register outputs for an even
symmetric filter or for subtracting the register outputs for
odd symmetric filter is provided by the control bit F_ESYM,
which is programmed over the control bus. When
subtraction is selected, the new data is subtracted from the
old data. The 17 bit output of the adder forms one input of
the multiplier/accumulator.
A control bit F_CLA provides the capability to clear the
feedback path in the accumulator such that multiplier
output will not be accumulated, but will instead flow directly
to the output register. The bit weightings of the data and
coefficients as they are processed in the FIR is shown
below.
Input Data (from HDF) 2°.2- 1 ... 2- 15
Pre-adder Output 212°.2-1 ... 2- 15
Coefficient 2°.2- 1 ... 2- 19
Accumulator 28 •.. 20 .21 ... 2- 34
FIR Output
The 40 most significant bits of the accumulator are latched
into the output register. The lower 3 bits are not brought to
the output. The 40 bits out of the output register are
selected to be output by a pair of multiplexers. This register
is clocked by FIR_CK (see Figure 9).
There are two multiplexers that route 24 of the 40 output
bits from the output register to the output pins. The first
multiplexer selects the output register bits that will be
routed to output pins DAT~OUT16-23 and the second
multiplexer selects the output register bits that will be
routed to output pins DATA_OUTO-1S.
The multiplexers are controlled by the control signal F_
BYP and the OUT_SELH pin. F_BYP and OUT_SELH
both control the first multiplexer that selects the upper 8 bits
of the output bus, DATA_OUT16-23. F_BYP controls the
second multiplexer that selects the lower 16 bits of the output bus, DATA_OUTO-1S. The output formatter is shown in
detail in Figure 10.
FIR Control Logic
The DATA_RDY strobe indicates that new data is available
on the output of the FIR. The rising edge of DAT~RDY can
be used to load the output data into an external register or
RAM.
Data Format
The DDF maintains 16 bits of accuracy In both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.
Operational Section
Start Configurations
The scenario to put the DDF into operational mode is: reset
the DDF by asserting the RESET# input, configure the DDF
over the control bus, and apply a start signal, either by
ASTARTIN# or STARTIN#. Until the DDF is put in
operational mode with a start pulse, the DDF ignores all
data inputs.
To use the asynchronous start, an asynchronous active low
pulse is applied to the ASTARTIN# input. ASTARTIN# is
internally synchronized to the sample clock, CK_IN, and
generates STARTOUT#. This signal is also used internally
when the asynchronous mode is selected. It puts the DDF in
operational mode and allows the DDF to begin accepting
data. When the ASTARTIN# input is being used, the
STARTIN# input must be tied high to ensure proper
operation.
To start the DDF synchronously, the STARTIN# is asserted
with a active low pulse that has been externally
synchronized to CK_IN. Internally the DDF then uses this
start pulse to put the DDF in operate mode and start accepting data inputs. When STARTIN# is used to start the DDF
the ASTARTIN# input must be tied high to prevent false
starts.
3-70
HSP43220
~---------------l
I
r---I-~~--r
I
PRE - ADDER LOGIC
I
I
I
16 x512
FROM HDF
DATA
RAM
L------T--~16~----~
I
L _______ ~-ESm____
.-------------------,
20 x256
FROM COEFFICIENT --"''o::~''1 COEFFICIENT H---'''';:-----+I
20
FORMATTER
20'"
RAM
I MULTIPUER/
I ACCUMULATOR
I SECTION
I
I
F CLA
I
I
FROM CONTROL REGISTERS
F
ORATE
F
TAPS
F
BYP
F
DIS
FIR CONTROL LOGIC
I
J
17
r-----.. . .------.
~
w
!:i
iL
FI~CK
....c
FI~CK
DATA_ROY
DATA_ROY
DATA_ OUT 0 -23
FIGURE 9. FIR FILTER
F
BVP = 0
OUT_SELH =
2
2
F
BYP
~----:..,
·16~
F
2
BVP = 0
OUT_SELH = 0
OR
F
·11-
F
-21
_---- F
BVP=
DATA_ 0UT16 -23
DATA_ OUTO -15
FIGURE 10. FIR OUTPUT FORMATTER
3-71
2- 31
BVP=
BYP
HSP43220
INPUT DATA FORMAT
Fractional Two's Complement Input
115114113112111 11019 18 17 16 15 14
I
3
2
1
0
-20.2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-15
FIR COEFFICIENT FORMAT
Fractional Two's Complement Input
I
119118117116115114113112111 110 1 9 1 8 1 7 1 6 1 5 14
-20.2-12-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-15
13 1 2 11 1 0
2-162-172-182-19
OUTPUT DATA FORMAT
Fractional Two's Complement Output
FOR: OUT_SELH = 1
F_BYP = 0
123122121 120 1191181171161
-28 27 26 25 24 23 22 21
I
I
115114113112111 110 9
8
7
6
5
4
3
2
0
20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-112-122-132-142-15
FOR: OUT_SELH = 0
F_BYP = 0
115114113112111 110 19
FOR: OUT_SELH
F_BYP = 1
8
7
6
I
5
4
3
2
o
=X
123122121 120 1191181171161
115114113112111 110 1 9
2-162-172-182-192-202-212-222-23
2-162-172-182-192-202-212-222-232-242-252-262-272-282-292-302-31
FIGURE 11.
3-72
8 1 7 1 6 15
4 1 3
2
0
HSP43220
Multi-Chip Start Configurations
Since there are two methods to start up the DDF, there are
also two configurations that can be used to start up
multiple chips.
The first method is shown in Figure 12. The timing of the
STARTOUT# circuitry starts the second DDF on the same
clock as the first. If more DDF's are also to be started
synchronously, STARTOUT# is connected to their
STARTIN#'s.
The second method to start up DDF's in a multiple chip
configuration is to use the synchronous start scenario.
The STARTIN# input is wired to all the chips in the chain,
and is asserted by a active low synchronous pulse that has
been externally synchronized to CLIN. In this way all
DDF's are synchronously started. The ASTARTIN# input on
all the chips is tied high to prevent false starts. The
STARTOUT# outputs are all left unconnected. This
configuration is illustrated in Figure 13.
TO OTHER DDF'S
+svI
+sv--
STARTIN#
ASTARTIN#
DDF
STARTOUT#
STARTIN#
CILIN
FIR_CK
STARTOUT#
ASTARTIN#
t--
NC
DDF
CILIN
I
FIR_CK
I'
,
tn
a:
w
!:i
u:::
....Q
FIGURE 12. ASYNCHRONOUS START UP
I
+svCILIN
FIR_CK
+sv-
STARTIN#
ASTARTIN#
DDF
STARTOUT#
t--
STARTIN#
CILIN
I
II
FIR_CK
1
"
J
FIGURE 13. SYNCHRONOUS START UP
3-73
STARTOUT#
ASTARTIN#
DDF
t--
NC
HSP43220
Chip Set Application
The HSP43220 is ideally suited for narrow band filtering in
Communications, Instrumentation and Signal Processing
applications. The HSP43220 provides a fully integrated
solution to high order decimation filtering.
The combination of the HSP43220 and the HSP45116
(which is a NCOM Numerically Controlled Oscillator!
Modulator) provides a complete solution to digital receivers.
The diagram in Figure 14 illustrates this concept.
The HSP45116 down converts the signal of interest to
baseband, generating a real component and an imaginary
component. A HSP43220 then performs low pass filtering
and reduces the sampling rate of each of the signals.
The system scenario for the use of the DDF involves a
narrow band signal that has been over-sampled. The signal
is over-sampled in order to capture a wide frequency band
containing many narrow band signals. The NCOM is
"tuned" to the frequency of the signal of interest and
performs a complex down conversion to baseband of this
signal, which results in a complex signal centered at
baseband. A pair of DDF's then low pass filters the NCOM
output, extracting the signal of interest.
HSP45116
NCOM
HSP43220
DDF
SAMPLED
INPUT
DATA
HSP43220
DDF
ED
'
o
. . ..
10MHz
o
20MHz
FIGURE 14. DIGITAL CHANNELIZER
3-74
o
HSP43220
Design Trade-Off Considerations
Equation 2.0 in the Functional Description section
expresses the relationship between the number of TAPS
which can be implemented in the FIR as a function of
C~IN, FIR_CK, Hdec, Fdec. Figure 15 provides a
*
SPEED
GRADE (MHz)
FIR_CK
--CK-IN
MIN
Hdec
33
25.6
15
1
1
1
7
4
33
25.6
15
2
2
2
33
25.6
15
33
25.6
15
tradeoff of these parameters. For a given speed grade and
the ratio of the clocks, and assuming minimum decimation
in the HDF, the number of FIR taps that can be implemented
is given in equation 2.0.
TAPS
Fdec= 1
Fdec=2
Fdec=4
Fdec=8
Fdec= 16
8
4
24
16
4
56
40
16
120
88
40
248
184
88
5
4
2
10
6
28
20
4
64
48
16
136
104
40
280
216
88
4
4
4
3
2
1
14
6
36
20
4
80
48
16
168
104
40
344
216
88
8
8
8
2
1
1
22
6
6
52
20
20
112
48
48
232
104
104
472
216
216
9
·
·
·
ffi
Filter Not Realizable
FIGURE 15. DESIGN TRADE OFF FOR MINIMUM Hdec
...c
DECI-MATE
Harris provides a development system which assists the
design engineer to utilizing this filter. The DECI - MATE
software package provides the user with both filter design
and simulation environments for filter evaluation and
design. These tools are integrated within one standard
DSP CAD environment, The Athena Group's Monarch
Professional DSP Software package.
The software package is designed specifically for the DDF.
It provides all the filter design software for this proprietary
architecture. It provides a user-friendly menu driven
interface to allow the user to input system level filter
requirements. It provides the frequency response curves
and a data flow simulation of the specified filter design
(Figure 16). It also creates all the information necessary to
program the DDF, including a PROM file for programming
the control registers.
IBM PC'"
I
xr"", AT"',
~
u:::
This software package runs on an IBM w PCN, XT N, ATN,
PS/2 N computer or 100% compatible with the following
configuration:
640K RAM
5.25" or 3.5" Floppy drive
hard disk
math co-processor
MS/PC-DOS 2.0 or higher
CGA, MCGA, EGA, VGA and
Hercules graphics adapters
For more information, see the description of DECI-MATE in
the Development Tools Section of this databook.
PS/2"" are registered trademarks of International Business Machines, Inc.
3-75
HSP43220
HSP43220 DDF FILTER SPECIFICATION
vectors\example.DDF
Filter File
33 MHz
Design Mode
Input Sample Rate:
100 kHz
Generate Report
output Rate
20 kHz
Display Response
Passband
7.5 kHz
Save Freq Responses:
Transition Band
0.5 dB
Save FIR Response
Passband Atten
Stopband Atten
80 dB
FIR Type
AUTO
YES
LOG
YES
YES
PRECOMP
HDF Order
HDF Decimation
HDF Scale Factor
FIR
FIR
FIR
FIR
4
110
0.54542
300 kHz
33 MHz
Input Rate
Clock (min)
Order
Decimation
135
3
(C) Harris Semiconductor 1990
HDF Frequency Response
FIR Frequency Response
5. 4842=~...,...---r--.---....,
-5. 2653r----r--~r----r--.....,
1'1
III
'tl-43.9490
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~ -63.9444
...........
oj
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c
:-98.6588
C
:-121.316
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:z:
-5. 7e-15F===~====::::;::::::::----~---!"'-----,
1'1
~-43.3429
y
VI
'tl-86.6859
:l
+'
·
··
...............
.
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I
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............... .
•
•
f
I
-216. 714llr----"'MO'l1:r.r--~nr*~--__.......= - - -........""=_--~
00
40 00
50 00
FIGURE 16. DECloMATE DESIGN MODULE SCREENS
3·76
Specifications HSP43220
Absolute Maximum Ratings
Reliability Information
Supply Voltage ••••••••••••••••••••••••••••••••••••• +8.ov
Input, OUtput or VO Voltage Applied •••••• GND -0.5V to Vee +
05';::- iD in
e
e
-I
OZ :.:
>CJ 0
!:::.t:. !::. !::.
STARTOUT# (12)
(74) GND
Vcc (13)
(73) DATA_OUTO
STARTIN# (14)
(72) DATA_OUn
ASTARTIN# (15)
(71) DATA-OUT2
RESET# (16)
(70) DATA-OUT3
Al (17)
(69) DATA-OUT4
AO (lS)
(6S) DATA_OUTS
WR# (19)
(67) DATA_OUT6
CS# (20)
(66) DATA-OUT7
C_BUS15 (21)
(65) DATA-OUTS
C_BUS14 (22)
(64) DATA-OUT9
C_BUS13 (23)
(63) DATA-OUnO
C_BUS12 (24)
(62) DATA_OUnl
(61) GND
C_BUSll (25)
(60) VCC
C_BUS10 (26)
(59) DATA_OUn2
C_BUS9 (27)
(58) DATA_OUT13
VCC (2S)
GND (29)
(57) DATA_OUn4
C_BUSS (30)
(56) DATA-OUn5
C_BUS7 (31)
(55) DATA-OUn6
C_BUS6 (32)
(54) DATA_OUT17
on
Ul
:::l
..
Ul
:::l
.,
Ul
:::l
'"
Ul
:::l
1ii
:::l
0
Ul
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m m m m m m
1 1 1 1 1 1
0
0
0
0
0
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J:
"* 00
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'Z"' Z>
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LU
Ul
II.
LU
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'P'"
HSP43481
HARRIS
SEMICONDUCTOR
Digital Filter
January 1994
Features
Description
• Four Filter Cells
The HSP43481 is a video-speed Digital Filter (OF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of four filter cells cascaded internally
and a shift-and-add output stage, all in a single integrated
circuit. Each filter cell contains an 8 x 8 multiplier, three decimation registers and a 26-bit accumulator which can add
the contents of any filter cell accumulator to the output stage
accumulator shifted right by eight-bits. The HSP43481 has a
maximum sample rate of 30MHz. The effective multiplyaccumulate (MAC) rate is 120MHz.
• OM Hz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Up to 1032 Tap
• Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 3 or 4
The HSP43481 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cascaded
for larger filter lengths without degrading the sample rate or
a single device can process larger filter lengths at less than
30M Hz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of
no overflows. In practice, most filter coefficients are less than
1.0, making even larger filter lengths possible. The
HSP43481 provides for unsigned or two's complement arithmetic, independently selectable for coefficients and signal
data.
Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP43481JC-20
O"C to +70°C
68 Lead PLCC
HSP43481JC-25
OOC to +70oC
68 Lead PLCC
HSP43481 JC-30
OOC to +70oC
68 Lead PLCC
HSP43481 GC-20
OOC to +70oC
68 Lead PGA
HSP43481 GC-25
OOC to +70oC
68 Lead PGA
HSP43481 GC-30
OOC to +70oC
68 Lead PGA
Each OF filter cell contains three resampling or decimation
registers which permtt output sample rate reduction at rates of
1/2 , 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing applications.
Block Diagram
Vee Vss
DiENii
C'iE'NB
l
l
DINO - DIN7 TCS
5
DCMO-DCMl
E'FiAsE
TCCI
TCCO
CINO-CIN7
COUTO - COUT 7
RESE'i'
'CoE'Na
ClK
ADRO-l
RESE'i'
ClK
ADRO,ADRI
2
SHADD
SENBr
SENiiii
2
SUMO-25
CAUTION: These devices are sensftive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-90
File Number
2759.3
HSP43481
Pinouts
68 PIN CERAMIC PIN GRID ARRAY (PGA)
BOnOMVIEW
C0UT7
C0UT5 COUTlI COUT,
COUTO
CLX
Tceo
COEiiii
COIffl1 COUT. COUl2
1IIW1O
DCM,
EiiASE
VCC
RESET
DEN!
G
TCO
.'NT
•
.... ....
...., ....
....
...., """""
DCMC
WiiiH
68 PIN CERAMIC PIN GRID ARRAY (PGA)
TOP VIEW
SUM. . ADDAD
SUM. .
SUM. . SUM. .
SUM. . SUM. .
SUM"
SUM. .
SUM"
DCMC
COUTD COUT,
CLX
COU12 COUT. COUTa CCENB
SUM"
Q
SU.. , .
PIN GRID ARRAY
SUM,. SUM,s
SUN'S SUM'•
BOTTON VIEW
SUMM
SUMM
VB •
SUMn
SUM10
SUMO
SU'"
SU'"
SUM4
SUMO
SUMO
COOl
COlI
C_
C1NO
SUM7
SUMS
SUMO
SUM'
Wiiii:
C ..,
c_
c...
elM7
COlO
C...
COlI
COlO
SUMO
1IUM2
SUM4
SU'"
SUMO
CIN1
CIN5
C...
C."
iEiiiii:
SUM'
SUMO
SUMS
SUM7
......
C....
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
§1!lil~l~
ct
Q
Z
rl... !ZQ Q~ !!lQ Q~ !!Q Q~ Q
~ I~U u...u
Q
u
u
>
•
COU17
CIN7
COUT8
CiNe
COUTS
CINS
COUT4
CIMO
COUTa
CIN3
COUT2
CIMO
COUll
elN1
COUTO
CIHO
SENeL
SHADD
SU..,
CLK
DC""
8UM1
DC..,
SU'"
ADR1
SUMO
ADRO
SU'"
SENBH
SUMS
SUM25
SUMO
8UM24
SUM7
27 28 2. 30 31 32 33 34 35 38 37
:l
>
as
38 40 41
. . .
...
." il §." ."~ .." i.." ..i" .." i." .." .."i ili .."i
~
:IE
!II
:IE
$!
:IE
$!
:IE
3-91
;!
:IE
TCO
.... .."
....
SUM10 SUN"
TCa
W
AE8E1'
SUN'S SUN'2
CiBiii
(J
iiiiii
SUN,2 SUN,S
DOlO
~
EiiASE
D_
TOP VIEW
V..
VCC
.1N7
88l.EAD
PIN GRID ARRAY
Tceo
....
.... ....
SUM,. SUM17
88l.EAD
-
......
DCM'
C0UT3 COUTa C0UT7
SUM. . SUM,.
SUN'II SUM. .
SUM17
iEiiiiH
....,
i
42 43
, .,"
il il
!I
TCO
HSP43487
Pin Description
SYMBOL
PIN
NUMBER
VCC
61
+5V Power Supply Input
VSS
27
Power Supply Ground Input
CLK
19
I
The CLK input provides the DF system sample clock. The maximum clock frequency is
is 30M Hz.
OlNo-7
64-68
1-3
I
These eight inputs are the data sample input bus. Eight bit data samples are synchronously
loaded through these pins to the X register of each filter cell simultaneously.
The OIENB signal enables loading, which is synchronous on the rising edge of the clock signal.
TCS
4
I
The TCS input determines the number system interpretation of the data input samples
on pins OINO-7 as follows:
TCS = low _ Unsigned Arithmetic
NAME AND FUNCTION
TYPE
TCS = High _ Two's Complement Arithmetic
The TCS signal is synchronously loaded into the X register in the same way
as the OINO-7 inputs.
OIENB
5
I
A low on this enables the data sample input bus (OINO-7) to all the filter cells. A rising
edge of the ClK Signal occurring while OIENB is low will load the X register of
everyfiHer cell with the 8 bit value present on OINO-7. A high on this inpulforces
all the bits of the data sample input bus to zero; a rising ClK edge when i5iENB is high
will load the X register of every filter cell with all zeros. This signal is latched inside
the OF, delaying its effect by one clock internal to the OF. Therefore, it must be low
during the clock cycle immediately preceding presentation of the desired data on the
OINO-7 inputs. Detailed operation is shown in later timing diagrams.
CINo-7
53-60
I
These eight inputs are used to input the 8 bit coefficients. The coefficients are synchronously
synchronously loaded into the C register of filter Cell 0 if a rising edge of ClK
occurs while CIENB is low. The CIENS signal is delayed byone clock as discussed below.
TeCI
62
I
The TCCI input determines the number system Interpretation of the coefficient
inputs on pins CINo-7 as follows:
TCCI = lOW _ UnSigned Arithmetic
TCCI = HIGH _ Two's Complement Arithmetic
The TCCI signal is synchronously loaded into the C register in the same way as
the CINo-7 inputs.
CIENS
63
I
A low on this input enable the C register of every filter cell and the 0 registers (decimation)
of every filter cell according to the state olthe OCMO-1 inputs. A riSing edge of
the ClK signal occurring while CIENS is low will load the C register and appropriate
o registers with the coefficient data present at their inputs. This privides the mechanism
for shifting the coefficients from cell to cell through the device. A high on this input
freezes the contents of the C register and the 0 registers, ignoring the ClK signal.
This signal is latched and delayed by one clock internal to the OF. Therefore, it must be
low during the clock cycle immediately preceding presentation of the desired coefficient
on the CINO-7 inputs. Detailed operation is shown in the Timing Diagrams section.
COUTO-7
10-17
0
These eighlthree-state outputs are used to output the 8 bit coefficients from filter cell 7.
These outputs are enabled by the COENS signal low. These outputs may be tied to the CINO-7
inputs of the same OF to recirculate the coefficients, or they may be tied to the
CINo-7 inputs of another OF to cascade OFs for longer filter lengths.
TCCO
9
0
The TCCO three-state output determines the number system representation of the coefIicienta
output on COUTO-7. H tracks the TCCI signal to this same OF. It should be tied to the TCCI
input of the next OF in a cascade of OFs for increased filter lengths. This signal is enabled
byCOENS low.
3-92
HSP43481
Pin Descriptions
SYMBOL
PIN
NUMBER
TYPE
COENB
8
I
A low on the COENB input enables the COUTO-7 and the TCCO output. A high on this input
places all these outputs in their high impedance state.
DCMO-1
20-21
I
These two inputs determine the use of the internal decimation registers as follows:
DCM1
Decimation Function
DCMO
NAME FUNCTION
0
0
1
1
0
1
0
1
Decimation registers not used
One decimation register is used
Two decimation registers are used
Three decimation registers are used
The coefficients pass from cell to cell at a rate determined by the number of decimation
registers used. When no decimation registers are used, coefficients move from cell to cell
on each clock. When one decimation register is used, coefficients move from cell to cell on
every other clock, etc. These signals are latched and delayed by one clock internal to the DF.
SUMO-25
25,26,
28-51
0
These 26 three-state outputs are used to output the results of the internal filter cell
computations. Individual filter cell results or the result of the shift-and-add output stage
can be output. If an individual filter cell result is to be output, the ADRO-1 signals select
the filter cell result. The SHADD signal determines whether the selected filter cell result
or the output stage adder result is output. The signals SENBH and SENBL enable the most
significant and least significant bits of the SUMO-25 result, respectively. Both SENBH
and SENBL may be enabled simultaneously if the system has a 26 bit or larger bus. However,
individual enables are provided to facilitate use with a 16 bit bus.
SENBH
24
I
A low on this input enables result bits SUM16-25. A high on this input places these
bits in their high impedance state.
SENBL
52
I
A low on this input enables result bits SUMO-15. A high on this input places these
bits on their high impedance state.
ADRQ-1
22,23
I
These two inputs select the one cell whose accumulator will be read through the output bus
(SUMQ-25) or added to the output stage accumulator. They also determine which accumulator
will be cleared when ERASE is low. For selection of which accumulator to read through the
output bus (SUMO-25) or which to add of the output stage accumulator, these inputs are
latched in the OF and delayted by one clock internal to the device. If the ADRO-1 lines remain
at the same address for more than one clock, the output at SUMO-25 will not chenge to reflect
any subsequent accumulator updates in the addressed cell. Only the result available during
the first clock, when ADRO-1 selects the cell, will be output. This does not hinder normal
operation since the ADRO-1 lines are changed sequentially. This feature facilitates the
interface with slow memories where the output is required to be fixed for mdre than one clock.
SHADD
18
I
The SHADD input controls the activation of the shift-and-add operation in the output stage.
This signal is latched in the OF and delayed by one clock internal to the device. A detailed
explanation is given in the OF Output Stage section.
RESET
6
I
A low on this input synchronously clears all the internal registers, except the cell accumulators.
It can be used with ERASE to also clear all the accumulators simultaneously. This Signal is
latched in the OF and delayed by one clock internal to the DF.
ERASE
7
I
A low on this input synchronously clears the cell accumulator selected by the ADRO-1 signals.
If RESET is also low simultaneously, all cell accumulators are cleared.
3-93
HSP43481
Functional Description
The Digital Filter (DF) is composed of four filter cells
cascaded together and an output stage for combining or
selecting filter cell outputs (see Block Diagram). Each filter
cell contains a multiplier-accumulator and several registers
(Figure 1). Each 8 bit coefficient is multiplied by a 8 bit data
sample, with the result added to the 26 bit accumulator
contents. The coefficient output of each cell Is cascaded to
the coefficient input of the next cell to its right.
DF Filter Cell
An 8 bit coefficient (GINO-7, TGGI) enters each cell through
the G register on the left and exits the cell on the right as
signals GOUTO-7 and TGGO. With no decimation, the coefficient moves directly from the G register to the output, and
is valid on the clock following its entrance. When
decimation is selected the coefficient exit is delayed by 1, 2
or 3 clocks by passing through one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient passes is determined by the state of DGMO and
DGM1. The output signals (GOUTO-7, TGGO) are connected to the GINO-7 and TGGI of the next cell to its right.
The GOENB input signal enables the GOUTO-7 and TGGO
outputs of the right-most cell to the GOUTO-7 and TGGO
pins of the DF.
The G and D registers are enabled for loading by GIENB.
loading is synchronous with GlK when GIENB is low. Note
that GIENB is latched internally. It enables the register for
loading after the next GlK following the onset of GIENB low.
Actual loading occurs on the second GlK following the
onset of GIENB low. Therefore, GIENB must be low during
the clock cycle immediately preceding presentation of the
coefficient on the GINO-7 inputs. In most basic FIR operations, GIENB will be low throughout the process, so this
latching and delay sequence is only important during the
initialization phase. When GIENB is high, the coefficients
are frozen.
is loaded synchronously into both the accumulator and
the TREG.
The TREG loading is disabled by the cell select signal,
Gelln, where n is the cell number. The cell select is decoded
from the ADRO-1 signals to generate the TREG load enable.
The cell select is inverted and applied as the load enable to
the TREG. Operation is such that the TREG is loaded whenever the cell is not selected. Therefore, TREG is loaded
every other clock except the clock following cell selection.
The purpose of the TREG is to hold the result of a sum-ofproducts calculation during the clock when the accumulator
is cleared to prepare for the next sum-of-products calculation. This allows continuous accumulation without wasting
clocks.
The accumulator is loaded with the adder output every
clock unless it is cleared. It is cleared synchronously in two
ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers in the DF. Since
both ERASE and RESET are latched and delayed one clock
internally, clearing occurs on the second GlK following the
onset of both ERASE and RESET low.
The second accumulator clearing mechanism clears a
single accumulator in a selected cell. The cell select signal,
Gelln, decoded from ADRO-1 and ERASE signal, Gelln enable clearing of the accumulator on the next GlK.
The ERASE and RESET signals clear the DF internal registers and states as follows:
These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly like GIENB.
The output of the G register is one input of the multiplier.
The other input of the multiplier comes from the output of
the X register. This register is loaded with a data sample
from the DF input signals. DINO-7 and TGS discussed
above. The X register is enabled for loading by DIENB.
loading is synchronous with GlK when DIENB is low. Note
that DIENB is latched internally. It enables the register for
loading after the next GlK following the onset of DIENB low.
Therefore, DIENB must be low during the clock cycle immediately preceding presentation of the sample on the DINO-7
inputs. In most basic FIR operations, DIENB will be low
throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When DIENB is high, the X register is loaded with all zeros.
The multiplier is pipelined and is modeled as a multiplier
core followed by two pipeline registers, MREGO and
MREG1. The multiplier output is sign extended and input as
one operand of the 26 bit adder. The other adder operand is
the output of the 26 bit accumulator. The adder output
ERASE
RESET
1
1
No clearing occurs, internal state
remains same.
1
0
RESET only active, all registers except
accumulators are cleared, including
the internal pipeline registers.
0
1
ERASE only active, the accumulator
whose address is given by the ADRO-1
inputs is cleared.
0
0
Both RESET and ERASE active, all
accumulators as well as all other registers are cleared.
CLEARING EFFECT
The DF Output Stage
The output stage consists of a 26 bit adder, 26 bit register,
feedback multiplexer from the register to the adder, an
output multiplexer and a 26 bit three-state driver stage
(Figure 2).
The 26 bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the outupt buffer.
This operation takes place in one clock period. The eight
lSBs are lost. The filter cell accumulator is selected by the
ADRO-1 inputs.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the 18 MSBs of the output buffer or all zeros for the
adder input. A low on the SHADD input selects zero. A high
on the SHADD input selects the output buffer MSBs, thus
activating the shift-and-add operation. SHADD signal is
latched and delayed by one clock internally.
3-94
HSP43481
DCM1.D
DCMO.D
r---------------------------------,
r-------------------,
RESET.D>-----------~----------------~~----~------------~----~
......_+--...,
CIENB.D >------,~+-------__1-t_--+_---TCCI
THREE-STATE BUFFERS
ON CELL 3 ONLY
>-_--1
------1
CINO-7~==~
Teeo
I
I
I
I
COUTO-7
RESElD
DIENB.D
TCS
DINO-7
"~===::t.....L>~,t===========:::====~==~x
MULTI-
(/)
a::
w
CORE
PLiER
!:i
P<0.17>
CLK
ii:
...c
LATCHES
RESET.D
DCMl
DCM1.D
DCMO
DCMO.D
iiffi1'
RESET.D
iiiENi
DIENB.D
CiENi
CIENB.D
ADRO
ADRO.D
ADRI
ADR1.D
Eiim
ERASE.D
CLK
ERASE.D
CLK
CELL.
ADRO:aCELLO
CELL 1
DECODER
CELL 2
ADRI
CELL 3
CELL.
>------1
AOUT 0-25
FIGURE 1.
HSP43481 FILTER CELL
3-95
HSP43481
CELL RESULTS
o
1
2
lines are changed sequentially. This feature facilitates the
interface wtith slow memories where the output is required
to be fixed for more than one clock.
3
The SUMO-25 output bus is controlled by the SENBii and
SENBL signals. A low on SEriffi[ enables bits SUMO-15. A
low on sENEiH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously if the external system has a
26 bit or larger bus. If the external system bus is only 16
bits, the bits can be enabled in two groups of 16 and 9 bits
(sign extended).
DF Arithmetic
Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS
and TCCI input signals determine the type of arithmetic
representation. Internally all values are represented by a 9
bit ~o's complement number. The value of the additional
ninth bit depends on arithmentic representation selected.
For two's complement arithmetic, the sign is extended into
the ninth bit. For unsigned arithmetic, bit 9 is O.
SHADD
FIGURE 2.
The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum-of-products without
overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient
and data values. As a worst case assume the coefficients
and data samples are always at their absolute maximum
values.
HSP43481 OUTPUT STAGE
The 26 Least Significant Bits (LSBs) from either a cell accumulator or the output buffer are output on the SUMO-25
bus. The output mux determines whether the cell accumulator selected by ADRO-1 or the output buffer is output to the
bus. The mux is controlled by the SHADD input signal.
Control is based on the state of the SHADD during two
successive clocks; in other words, the output mux selection
contains memory. If SHADD is low during a clock cycle and
was low during the previous clock, the output mux selects
the contents of the filter cell accumulator addressed by
ADRO-1. Otherwise the output mux selects the contents of
the output buffer.
If the ADRO-1 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first
clock when ADRO-1 selects the cell will be output. This
does not hinder normal FIR operations since the ADRO-1
Then the maximum numbers of terms in the sum products
are:
NUMBER SYSTEM
MAX #
OF TERMS
Two unsigned vectors
1032
Two two's complement vectors:
• Two positive vectors
• Two negative vectors
• One positive and one negative vector
2080
2047
2064
One unsigned and one two's complement
vector:
• Positive two's complement vector
• Negative two's complement vector
1036
1028
For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.
3-96
HSP43481
Basic FIR Operation
A simple 30MHz 4 tap filter example serves to illustrate
more clearly the operation of the DF. Table 1 shows the
results of the multiply accumulate in each cell after each
clock. The coefficient sequence, Cn, enters the DF on the
left and moves from left to right through the cells. The data
sample sequence, Xn, enters the DF from the top, with each
cell receiving the same sample simultaneously. Each cell
TABLE 1.
accumulates the sum-of-products for one output point.
Four sums-of-products are calculated simultaneously, but
staggered in time so that a new output is available every
system clock.
Detailed operation of the DF to perform a basic 4 tap, 8 bit
coefficient, 8 bit data, 30MHz FIR filter is best understood
by observing the schematic (Figure 3) and timing diagram
25M Hz, 4 TAP FIR FILTER SEQUENCE
DATA
SEQUENCE
INPUT
COEFFICIENT
SEQUENCE
INPUT
CLK
CELLO
CELL 1
CELL 2
CELL 3
SUM/CLR
0
1
2
3
4
5
e
7
C3 xXO
+C2 xXI
+Cl XX2
+CO xX3
C3 xX4
+C2 XXS
0
C3 xX l
+C2 XX2
+Cl xX3
+COxX4
C3 xXS
+C2 xXe
+Cl xX7
0
0
C3 xX2
+C2 xX3
+Cl xX4
+CoxXs
C3 xX e
+C2 xX7
0
0
0
C3 xX 3
+C2 xX4
+Cl xXs
+CoxXe
C3 xX7
-
+Cl xXe
+COxX7
Cell O(Y3)
Cell 1 (Y4)
Cell 2 (Ys)
CeIl3(Ye)
Cell O(Y7)
SAMPLE
DATA IN
IX.1
30MHz
CLOCK
RESET ~
2 BIT
COUNTER
>-rYl
+5V
Yo
I I
I
1
c.....F
.r--
AO
DO-7
4x8 COEFF.
RAM/ROM
-
r-
~
SENBl
26
DlNO-7
SUMO-25
TCCO
HSP43481
-
SUM
OUT
(Y.l
NC
TCCI
COUTO-7
CINO-7
CiENiI
T
DCMl DCMO
I I
iiEsiT iiiAsi
T
I
SYSTEM
RESET
VSS
CiiENa
..
T
I
ERAsE
FIGURE 3.
-f---
TCS
ClK
Al
..
1
DIENB ADRI ADRO Vee SHADD SENBH
30M Hz, 4 TAP FIR FILTER APPLICATION SCHEMATIC
3-97
~
NC
HSP43481
After the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
(Figure 4). The internal pipeline length of the OF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and coefficients at the OINO-7 and CINO-7 inputs to a sum appearing
at the SUMO-25 output is:
k
The output sums, Y(n), shown in the timing diagram are
derived from the sum-of-products equation:
YIn)
+ Td where
= C(O) x X(n) + C(1) x X(n-1) + C(2) x X(n-2) + C(3) x X(n-3)
k = filter length,
Td = 4, the internal pipeline delay of OF
ClK
REiIIT~r--------------------------------------------------------
iiim~
I Xo I XI I X21 x31 x41 x51 x61
DINO-7
x71
DIEHB ~
CINO-7
Ciftii ~
ADRO-l
10111213101112131
I v31 v41 V51 V6 I v71 val Vg I
SUMO-25
SHADDWW~A
SENiii ~~//////fll
SENBH~ffi
I f-I-------------------------------------------------------
DCMO-l
0
3
VN =
L
K
FIGURE 4.
SAMPLE
DATA IN
(X.)
CK x XN-K
=0
30M Hz 4 TAP FILTER TIMING
>,-PROM P5
P4
ClK
P3
30MH,
CLOCK
r - A2
AI
r-
I
P2
PI-
7
..-
SYSTEM
RESET
'---
AD RAM/ROM
YO
YI
Y2
h
+jV * l
I
+r*l
II
DIENB ADRIADROVCC SHADD SENBH SENBl
SUMO-25 ~
TCS
HSP43481
DFO
ClK
j
·1
~
DIND-7
.-
TCS
~
SUMO-25
>---. AI
>---00
A2
00-7
TCCD
TCCI
~ CINO-7
CiEtii DCMI
T
CDUTO-7
DCMO iiEffi ERAsE VSS
I
DOERAS ').
FIGURE 5.
-D-
com
r- r- Ne
CINO-7
COUTO-7
~ r- Ne
CiEtii DeMI DCMO iiEffi ERAsE VSS
•
I
iiiEiiAs ').
-D-
30MHz 8 TAP FILTER USING TWO CASCADED HSP43481s
3-98
TCCO
TCCI
8
f-+-26
HSP43481
DFI
ClK
8x8 COEFF.
ClK
3c~~T
j
J,<- DINO-7
iiiEiiAs
!>---
*]
DIENB ADRI ADRO Vcc SHADDSENBH SENBl
DDERAS
~
j
...
com
SUM
OUT
(Y.)
HSP43481
Extended FIR Filter Length
Filter lengths greater than four taps can be created by either
cascading together multiple DFs or "reusing" a single DF.
Using multiple devices, an FIR filter of over 1024 taps can
be constructed to operate at a 30MHz sample rate. Using
a single DF clocked at 30M Hz, an FIR filter of over 1024
taps can be constructed to operate at less than a 30M Hz
sample rate. Combinations of these two techniques are also
possible.
Cascade Configuration
To design a filter length L > 4, L/4 DFs are cascaded by
connecting the COUTO-7 outputs of the (i)th D F to the
CINO-7 inputs of the (i + 1)th DF. The DINO-7 inputs and
SUMO-25 outputs of all the D Fs are slso tied together. A
specific example of two cascaded DFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 4
tap FIR, except the ERASE and SENBL/SENBH signals
must be enabled independently of the two DFs in order to
clear the correct accumulators and enable the SUMO-25
output signals at the proper times.
TABLE 2.
Single DF Configuration
Using a DF, a filter of length L > 4 can
be constructed by
processing in L/4 passes as illustrated in Table 2 for an 8
tap FIR. Each pass is composed of Tp = 7+L cycles and
computes four output samples. In pass i, the samples with
indices i x 4 to i x 4 + (L+2) enter the DINO-7 inputs. The
coefficients CO-CL-1 enter the CINO-7 inputs, followed by
three zeros. As these zeros are entered, the result samples
are output and the accumulators reset. Initial filling of the
pipeline is not shown in this sequence table. Filter outputs
can be put through a FIFO to even out the sample rate.
Extended Coefficient And
Data Sample Word Size
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 8x8 and
combine these partial products by shifting and adding to
obtain the final result. The shifting and adding can be
accomplished with external adders (for full speed) or with
the DFs shift-and-add mechanism contained in its output
stage (at reduced speed).
a:
w
8 TAP FIR FILTER SEQUENCE USING SINGLE OF
!:i
ii:
...
DATA
SEQUENCE
INPUT
Q
COEFFICIENT
SEQUENCE
INPUT
CLK
CELLO
CELLl
CELL2
CELL3
SUM/CLR
-
0
C7 xXO
0
0
0
1
+Ca XX l
+C5 XX2
C7 XX l
+Ca xX 2
0
0
+C4 xX3
+C3 xX 4
+C5 xX 3
+C4 xX 4
C7 XX 2
+Ca xX 3
+C5 xX 4
C7 xX 3
+Ca xX4
5
+C2 xX5
a
7
+Cl xXa
+C3 xX 5
+C2 xXa
+C4 xX5
+C3 xXa
+Cl XX7
+C2 XX7
+Cl xXa
2
3
4
a
+COXX7
0
9
0
+CoxXa
0
10
0
0
+CO xX9
0
0
+C5 XX5
+C4 xXa
+C3 xX7
+C2 xX a
C7 xX 4
0
0
+Ca XX5
+C5 xX a
C7 XX 5
+CaxXa
0
0
14
+C4 XX7
+C3 xXa
+C5 XX7
la
+C2 xX9
+Cl x XlO
+C2 x Xl0
la
+Cl x Xll
19
+COxXll
0
20
0
+COXX12
0
21
0
0
CeIl0(Y7)
Cell 1 (Ya)
CeIl2(Y9)
11
17
-
Cell 3 (Yl0)
12
13
+C4 XXS
+C3 xX9
-
+Cl xX9
+CO XX lO
0
15
U)
C7 xX a
0
+Ca xX 7
+C5 XXS
C7 xX7
-
-
+CaxXs
-
+C4 XX9
+C5 XX9
-
+C3 xX l0
+C2 xX l l
+C4 XX 10
+C3 XXll
CeIlO(Yll)
+Cl XX12
+C2 XX12
Cell 1 (Y12)
+CO XX 13
0
+Cl XX13
Cell 2 (Y13)
+COXX14
CeIl3(Y14)
3-99
-
HSP43481
o
234
5
6
7
a
ro
9
n
n
~
M
~
~
u
m
u
~
~
""""L.J
L-
FiiiiSE """"L.J
~
DFO ERASE
DFt
1
DINO-7
iiiENs
I Xo I Xt I X21 X31 X41 X51 X61 X71 xal Xg! XtOI Xnl X121 X131 X141 X151
7iZ%l
CINO-7
I C71 C61 C51 C41 C31 C21 C1 I Col C71 C61 C51 C41 C31 C2 I Ct I Col • •
Ci'ENa ;zmI
ADRO-1
101112131011121310111
DFO SUMO-25
1Y7 1 Yal Yg I Y10 1
DF1 SUMO-25
SHADD
000000'h0'~M00l
L
DFO SENBL/H ~
DF1
'--___~I
ffiiBLiii ~'-____-'
DCMO-1
I Y151
I Y11h21 Y131 Y141
1
0
1-1- - - - - - - - - - - - - - - - - - - - - - - - - - ..
7
YN
=I
K
FIGURE 6.
CK x XN-K
=0
30M Hz 8 TAP FIR FILTER TIMING
Decimation/Resampling
The HSP43481 provides a mechanism for decimating by
factors of 2, 3 or 4. From the D F filter cell block diag ram
(Figure 1), note the three D registers and two multiplexers in
the coefficient pass through the cell. These allow the coefficients to be delayed by 1,2 or 3 clocks through the cell. The
sequence table (Table 3) for a decimate-by-two filter
illustrates the technique.
Detailed timing for a 30MHz input sample rate, 15MHz
output sample rate (I.e., decimate-by-two), 8 tap FIR filter,
including pipelining, is shown in Figure 7.
3-100
HSP43481
TABLE 3.
8 TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE, 30MHz IN, 15MHz OUT
DATA
SEQUENCE
INPUT
COEFFICIENT
SEQUENCE
INPUT
CELLO
CELL 1
0
C7 x ><0
0
1
+Ce XXl
0
CLK
2
+CSXX2
C7 XX2
3
+C4 XX3
+Ce XX3
CELL 2
CELL 3
SUM/CLR
-
e
+Cl xXe
+C3 xXe
+CsxXe
+C7 xXe
-
7
+COXX7
+C2 xX7
+C4 xX7
+Ce xX 7
CeIl0(Y7)
a
C7 xXa
+Cl xXa
+C3 xXa
+CsxXa
Cell 0 (Y7)
9
+Ce xX9
+Co xX9
+C2 xX9
+C4 XX9
CellI (Y9)
10
+CS XX10
C7 XX 10
+Cl XX10
+C3 xXl0
CellI (Y9)
11
+C4 XX11
+Ce XXl l
+COXXll
+C2 XXII
CeI12(Yll)
12
+C3 xX12
+CSXXI2
C7 XX12
+Cl XX12
CeIl2(Yll)
13
+C2 xX 13
+C4 XXI3
+Ce xX 13
+COXXI3
Cell 3 (Y13)
14
+Cl XX14
+C3 xX14
+CSXXI4
C7 XX14
Cell 3 (YI3)
IS
+COXXIS
+C2 XXI5
+C4 XXI5
+Ce XX I5
Cell o (Y15)
4
+C3 xX4
+CSXX4
C7 xX4
S
+C2 xXS
+C4 xXS
+CexXs
elK
iimT
EiiAsE
1-J
IXo IXl IX21 X3 IX41
01NO-7
Xsi X61 X71
iiiENi 'l%%Zl
~~~
CiENi ~
I~I~I~I~I~I~I~I~I···
AORO-l
SUMO·2S
YI
SHAOomw~A
SENalP~~~$A
SENiii ~&/ffi00W/~
OCMO-l
1 1-1----------------------------.
1
FIGURE 7.
8 TAP DECIMATE-BY-TWO FIR FILTER TIMING, 30MHz IN, 15MHz OUT
3-101
en
a:
w
!:i
u::
....Q
Specifications HSP43481
Absolute Maximum Ratings
Supply Voltage .....•........................••.•......••.•••.............••.........•.............•..••.••••••• +8.0V
Input, Output Voltage .......................................................................... GND -0.5V to VCC +0.5V
Storage Temperature ................................................................................. -65 0 C to +1500C
ESD .......••...•.......•.........•....••...•••••........•.•..••........•..•.••......•.•...•.•..••.•••.•••.•• Class 1
Maximum Package Power Dissipation at 70 0 C ................................................... 1.9W (PLCC), 2.6W (PGA)
9jc .•.......••...•.................•....•.•....•••...•....•.•••••...•....•..•...•... 15.0W/OC(PLCC),9.92WfOC(PGA)
9ja ..•.................................•••.•.........••.......•...•.••..•.•......•. 43.0W/oC (PLCC), 38.44WfOC (PGA)
Gate Count .•••..........................•....•..........••.•...••...•.......•••........•.•.•....•.••••••.•..•.• 9371
Junction Temperature ...................................................................... 1500 C (PLCC), 1750 C (PGA)
Lead Temperature (Soldering 1 Os) ............................................................................... 3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ........•..........••......••.•............•...••..................................•.. 5V:l:5%
Operating Temperature Ranges ........................................................................... OoC to + 700C
D.C. Electrical SpeCifications
SYMBOL
ICCOp
PARAMETER
Power Supply Current
MIN
MAX
UNITS
-
110
mA
VCC = Max
ClK Frequency 20MHz
Note 1, Note 3
VCC = Max, Note 3
TEST CONDITIONS
-
500
pA
II
Input Leakage Current
-10
10
J1A
VCC = Max, Input = OVorVCC
10
Output Leakage Current
-10
10
pA
VCC = Max, Input = OV orVCC
VIH
Logical One Input Voltage
2.0
-
V
VCC = Max
VIL
Logical Zero Input Voltage
Vcc=Min
IceSB
Standby Power Supply Current
VOH
logical One
VOL
Logical Zero Output Voltage
0.8
V
2.6
-
V
10H = -400pA, VCC = Min
-
0.4
V
10L = 2mA, VCC = Min
VIHC
Clock Input High
3.0
-
V
VCC= Max
VllC
Clock Input Low
-
0.8
V
VCC = Min
CIN
Input Capacitance
PLCC
PGA
10
15
pF
pF
Output Capacitance
PLCC
PGA
10
15
pF
pF
CLK Frequency 1 MHz
All Measurements
Referenced to GND
TA = +25 0 C Note 2
COUT
-
NOTES: 1. Operating supply current is proportional to frequency. Typical
rating is S.SmA/MHz.
2. Controlled via design or process parameters and not directly
tested. Characterized upon initial design and after major process
andlor design changes.
3. Output load per test cirCUit and CL = 40pF.
3-102
Specifications HSP43481
A.C. Electrical Specifications vcc = +4.75V to +5.25V, TA = ooc to +7OGC
-20 (20MHz)
SYMBOL
PARAMETER
MIN
MAX
TCp
Clock Period
50
TCL
Clock Low
20
TCH
Clock High
20
TIS
Input Setup
16
TIH
Input Hold
0
-
TODC
CLK to Coefficient
Output Delay
-
26
TOED
Output Enable Delay
-
20
TODD
Output Disable Delay
-
20
TODS
CLKtoSUM
Output Delay
-
30
TOR
Output Rise
6
TOF
Output Fall
-
-25 (25.6MHz)
-30 (30MHz)
MIN
MAX
MIN
MAX
UNITS
39
33
0
-
ns
0
-
-
22
-
19
ns
16
16
14
-
6
13
13
13
ns
ns
ns
ns
15
ns
15
ns
26
-
21
ns
6
-
6
ns
Note 1
6
-
6
ns
Note 1
15
15
Note 1
~
NOTE: 1. Controlled by design or process parameters and not directly
tested. Characterized upon initial design and after major process
and/or design changes.
UJ
!:i
ii:
Q
..-
Test Load Circuit
[---------------1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.5V
1
1
IOL
1
1
'INCLUDES STRAY AND 1
JIG CAPACITANCE
1_ _ _ _
TEST
CONDITIONS
1
EQUIVALENT~IRCUIT _ _ _ _ J
Swftch S1 Open for ICCSB and ICCOp Tests
3-103
HSP43481
Waveforms
-TCP----<..,
~TCH
2.0V
TCL2.0V
2.0V
CLK
• Input includes: DINO-7, CINO-7, DIENS, CIENS, ERASE, RESET, DCMO-l,
ADRO-l, TCS, TCCI, SHADD
CLOCK AC PARAMETERS
INPUT SETUP AND HOLD
r""
~
so••: :
COUTO - 7
TCCO
TOOS :::::::
1.5V
-._.---
OUTPUT
RISE AND FALL TIMES
SUMO-25, COUTO-7, TCCO OUTPUT DELAYS
AC. Testing: Inputs are driven at 3.0V for a logic "I" and OV for a logic "0".
Input and output timing measurements are made at 1.5V for both a Logic "1"
and "0". ClK is driven at 4.0V and O.OV and measured at 2.0V.
A.C. TESTING INPUT, OUTPUT WAVEFORM
3-104
HSP43481/883
Digital Filter
Jan uary 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL-STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HSP43481/883 is a video-speed Digital Filter (OF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of four fi~er cells cascaded
internally and a shift-and- add output stage, all in a single
integrated circuit. Each filter cell contains an 8 x 8 multiplier,
three decimation registers and a 26-bit accumulator which
can add the contents of any filter cell accumulator to the output stage accumulator shifted right by eight-bits. The
HSP43481/883 has a maximum sample rate of 25.6MHz.
The effective multiply-accumulate (MAC) rate is 102MHz.
• OMHz to 25.6MHz Sample Rate
• Four Filter Cells
• B-Bit Coefficients and Signal Data
• Low Power CMOS Operation
•
•
•
•
- ICCSB = 500j.1A Maximum
- Iccop = 110j.1A Maximum at 20MHz
26-Blt Accumulator Per Stage
Filter Lengths Up To 1032 Taps
Expandable Coefficient Size, Data Size and Filter Length
Decimation by 2, 3 or 4
The HSP43481/883 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cascaded
for larger filter lengths without degrading the sample rate or
a single device can process larger filter lengths at less than
25.6MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of
no overflows. In practice, most filter coefficients are less than
1.0, making even larger filter lengths possible. The
HSP43481/883 provides for unsigned or two's complement
arithmetic. independently selectable for coefficients and signal data.
Applications
•
•
•
•
•
•
1-0 and 2-D FIR Filters
Radar/Sonar
Adaptive Filters
Echo Cancellation
Complex Multiply-Add
Sample Rate Converters
Each OF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates of
1/2 , 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing applications.
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP43481 GM-20/883
-55°C to +125°C
68 Lead PGA
HSP43481 GM-251883
-55°C to +125°C
68 Lead PGA
Block Diagram
vee
i5iENi
vss
¥ ¥
DINO - DIN7 TCS
cmNB~s~~~====~==~==:;~~==~---,
DCMO-DCM1
ERASE
TCCI
TCCO
CINO-CIN7
COUTO - COUT 7
iiESE'i'
CLK~~~-r----4-~----~-r----~
ADRO-1
ADRO,ADR1
2
SHADD>---------------~
SENifL: >----r.;----------.&...:.;.;.~.J
SENaii
2
SUMO-25
CAUTION: These devices are sensitive to electrostatic discharge. Users should Iollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-105
File Number
2450.3
Specifications HSP43481/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage .........•...•..•.......•••••.....••...• +8.0V
Input, Output Voltage Applied ••.••••••• GND-0.5Vto VCC+0.5V
Storage Temperature Range .•....•.•.....•.• -650C to +150 0C
Junction Temperature ••..............•............... +1750 C
Lead Temperature (Soldering, Ten Seconds) •••...•...•. +300 0 C
ESD Classification ...••..••........................... Class 1
Thermal Resistance
Sja
Sjc
Ceramic PGA Package •.......•.•• , 38.440 C/W 9.92 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package •....•••.•••.••..•....•.•••• 1.30 Watt
Gate Count •...•.•••.•....•..........•..•.•...... 9370 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification ;s not implied.
Operating Conditions
Operating Voltage Range ..•.•.••.•.•••.•••..... +4.5V to +5.5V
Operating Temperature Range ••.••...••..•.• -550C to +1250 C
TABLE 1. HSP43481/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
LIMITS
GROUPA
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Logical One Input
Voltage
VIH
VCC=5.5V
1,2,3
-550C.:s: TA:5 +1250 C
2.2
-
V
Logical Zero Input
Voltage
VIL
VCC=4.5V
1,2,3
-550C:5 TA:5 +125 0C
-
0.8
V
Output HIGH Voltage
VOH
10H =-400~A
VCC = 4.5V(Note 1)
1,2,3
-550C.:s: TA:5 +125 0 C
2.6
-
V
Output LOW Voltage
VOL
IOL=+2.0mA
VCC = 4.5V (Note 1)
1,2,3
-550C ~TA.:s: +125 0 C
-
0.4
V
Input Leakage Current
II
VIN=VCCorGND
VCC=5.5V
1,2,3
-550C.::;. TA.:s: +1250 C
-10
+10
~
Output Leakage
Current
10
VOUT = VCC or GND
VCC= 5.5V
1,2,3
-550C !>.TA~ +125 0 C
-10
+10
~
Clock Input High
VIHC
VCC= 5.5V
1,2,3
-550 C.:s:TA.:s:+1250C
3.0
-
V
Clock Input Low
VILC
VCC=4.5V
1,2,3
-550 C:5 TA'::; +125 0C
-
O.S
V
Standby Power Supply
Current
ICCSB
VIN = VCC or GND
VCC=5.5V,
Outputs Open
1,2,3
-550C.:s; TA ~ +125 0 C
-
500
I'A
Operating Power
Supply Current
ICCOp
f=20.0MHz
V CC = 5.5V (Note 2)
1,2,3
-550 C.::;TA'::;+1250C
-
110.0
mA
7,8
-550C.:s; TA:;; +125 0 C
-
-
Functional Test
FT
(Note 3)
NOTES: 1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency. typical
rating is S.SmA/MHz.
3. Tested as follows: f = 1 MHz, VIH = 2.6, VIL = 0.4. VOH
VOL ~ 1.5V, VIHC = 3.4V and VILC = O.4V.
3-106
.<:
1.51/.
Specifications HSP43481/883
TABLE 2. HSP43481/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
-20 (20M Hz)
GROUP A
SYMBOL CONDITIONS SUBGROUPS
PARAMETER
-25 (25.6MHz)
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
39
ns
Clock Period
TCp
Note 1
9,10,11
-550C ~ TA::::: +1250 C
50
Clock Low
TCL
Note 1
9,10,11
-550C::::: TA:s. +1250 C
20
-
TIH
Note 1
9,10,11
-550C < TA :$. +125 0 C
0
-
0
-
Clock High
TCH
Note 1
9,10,11
-550C:S TA ~ +125 0 C
20
-
16
TIS
Note 1
9,10,11
-55°C :S TA :s. +125 0 C
20
-
17
CLK to Coefficient
Output Delay
TODC
Note 1
9,10,11
-55 0 C:s. TA:$. +1250 C
-
24
-
20
ns
Output Enable Delay
TOED
Note 1
9,10,11
-550C :s.TA:$. +1250 C
Note 1
9,10,11
-550C ~ TA~ +125 0 C
31
-
ns
TODS
-
15
CLKtoSUM
Output Delay
25
ns
Input Setup
Input Hold
16
20
ns
ns
ns
ns
NOTE: 1. A.C. Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for a
Logic "1" and O.DV for a logic "0". Input and output timing measurements are made at 1.5Vfor both a Logic "1" and "0". elK is driven at
4.0V and OV and measured at 2.0V.
TABLE 3. HSP43481/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
-20 (20MHz)
PARAMETER
-25 (25.6MHz)
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
CIN
VCC=Open, f=l MHz
All measurements
are referenced to
deviceGND.
1
TA=+250C
-
15
-
15
pF
1
TA=+250C
-
15
-
15
pF
-
20
-
15
ns
7
-
6
ns
7
-
6
ns
Input Capacitance
Output Capacitance
COUT
Output Disable Delay
TODD
1,2
-550C:S TA:$. +1250 C
Output Rise Time
TOR
1,2
-550C:s TA:S +1250 C
Output Fall Time
TOF
1,2
-55°C ~ TA:S +1250 C
NOTES: 1. The parameters listed in Table 3 are controlled via design or procass parameters and are not directly tested. These parameters
are characterized upon initial design and after major process
andlor design changes.
2. loading is as specified in the test load circuit, CL
= 40pF.
TABLE 4. APPLICABLE SUBGROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2, 3,6A, 6B, 10, 11
-
1,2,3, 7,6A, 6B, 9,10,11
Samples/500S
1,7,9
CONFORMANCE GROUPS
Group A
GroupsC&D
3-107
HSP43481/883
Burn-In Circuit
COU17
COUT5
eOU13 COUTl
COUTO
elK
ADDR1
ADORO 8UM25
Teco
COENB
COUTe
COUT4 COU12
SHADD
DCM1
DeMO
SENBH
ERASE
H
G
K
SUMa..
8UM23
Vee
SUM2l
8UM22
RESET
DIENS
SUM18
8UM2O
Tes
DIN7
8UM17
SUM18
68 LEAD
PIN GRID ARRAY
aoTIOMVlf2N
BU"U5 SUM1.
DINS
DINa
DINa
DIN4
Vss
SUM1.
D
DINl
DINa
8UM12
8UM13
e
DINO
elENB
8UM10
8UM11
B
TeCI
CINa
CIH4
elN2
COHO
8UMO
8UM2
SUM4
8UM8
SUM8
SUMe
CIH7
elNS
CIN3
elHl
RENBl
8UMl
8UM3
SU'"
SUM7
..
10
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PIN
NAME
PGA
PIN
BURN-IN
SIGNAL
11
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
K1
TCCO
VCC/2
C2
CIENB
F10
B6
SUMO
VCC/2
H10
SUM19
Vcct2
J1
ERASE
F10
62
CIN6
F6
A6
SEN6l
F10
G10
SUM17
Vcct2
H1
RESET
F11
A2
CIN7
F7
L7
CLK
FO
F10
SUM15
VCC!2
G1
TCS
F7
L3
COUT5
Vcct2
K7
OCM1
F6
E10
VSS
GNO
F1
DlN5
F5
K3
COUT6
Vcct2
67
SUM2
VCC!2
010
SUM12
VCC/2
E1
DlN3
F3
B3
CIN4
F4
A7
SUM1
VCC/2
C10
SUM10
VCC/2
D1
DIN1
F1
A3
CIN5
F5
L8
ADDR1
F1
610
SUM8
VCC/2
C1
DINO
FO
L4
COUT3
VCC/2
K8
DCMO
F5
A10
SUM7
VCC/2
61
TCCI
F8
K4
COUT4
VCC/2
68
SUM4
VCC!2
K11
SUM23
VCC/2
L2
COUT7
VCC/2
64
CIN2
F2
A8
SUM3
VCC/2
J11
SUM22
VCC/2
K2
COEN6
F10
A4
CIN3
F3
L9
ADDRO
FO
H11
SUM20
VCC/2
J2
VCC
VCC
L5
COUT1
VCC/2
K9
SEN6H
F10
G11
SUM18
VCC/2
H2
DIEN6
F10
K5
COUT2
VCC/2
89
SUM6
VCC/2
F11
SUM16
VCC/2
G2
0lN7
F8
65
CINO
FO
A9
SUM5
VCc!2
E11
SUM14
VCC/2
L10
SUM25
SUM13
VCC/2
F2
DIN6
F6
A5
CIN1
F1
VCC/2
D11
E2
DIN4
F4
L6
COUTO
VCC/2
K10
SUM24
VCC/2
C11
SUM11
VCC/2
D2
DIN2
F2
K6
SHADD
F9
J10
SUM21
VCc/2
611
SUM9
VCC/2
NOTES: 1. VCC/2 (2.7V ±10%) used for outputs only.
4.
2. 47KO (±20%) resistor connectsd to all pins except Vee and
GND.
3. Vee
= S.S ±O.SV.
0.1~F
S. FO
(min) capacHor between Vec and GND per position.
= 100KHz ±10%, F1 = FO/2, F2 = F1/2 •.•.• , F11 - F10/2,
40% - 60% Duty Cycle.
6. Input voRage limits: VIL = O.eV max., VIH
3-108
= 4.5V ±10%.
HSP43481/883
Metallization Topology
DIE DIMENSIONS:
253 x 230 x 19 ±1 mils
METALLIZATION:
Type: Si - AI or Si - AI - Cu
Thickness: akA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY:
1.2 x 105Ncm2
Metallization Mask Layout
HSP43481/883
;;
:!
III
III
::>
:J:
III
"'"::>
:!
0
0
00
""
""
a
Z
UI
III
u
u
>
,.
0
:!
u
0
a
a
-'
~
a
~
"u ""
1=
::>
::>
11::>
U
U
U
U
0
0
0
0
en
~
'"
j!
l-
0
0
::>
U
::>
U
..
I-
r::
::>
::>
u
U
U
>
0
0
U
f/)
Vss
TCCO
SUM23
Vss
Vee
COENB
SUM22
ERASE
SUM21
Vee
SUM20
RESET
SUM19
DIENB
VSS
Tes
SUM18
DIN7
SUM17
DIN6
Vee
DINS
SUM16
DIN.
SUM15
DINa
SUM14
SUM13
DIN2
Vss
DIN1
SUM12
OINO
SUM11
Vss
SUM10
CIENB
SUM9
Tcel
SUM8
Vee
...
..
::>
::>
:!
II>
'" :!...::>
:!
:!
III
III
::>
III
U
u
>
M
:!
::>
III
"
:!
::>
III
,.
::>
III
0
:!
::>
III
III
III
>
-'
III
z
UI
en
3-109
0
Z
(j
z
(j
u
U
>
"
~
u
M
Z
(j
...
Z
(j
'"
Z
(j
III
~
..
Z
(j
...
z
(j
a:
W
!:;
ii:
...
C
HSP43881
Digital Filter
January 1994
Features
Description
•
•
•
•
•
•
The HSP43BB1 is a video speed Digital Filter (OF) designed
to effiCiently implement vector operations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a B x B·bit multiplier, three decimation registers and a 26·bit accumulator. The output stage
contains an additional 26·bit accumulator which can add the
contents of any filter cell accumulator to the output stage
accumulator shifted right by B·bits. The HSP43881 has a
maximum sample rate of 30M Hz. The effective multiply
accumulate (mac) rate is 240MHz.
Eight Filter Cells
0 to 30M Hz Sample Rate
8-Blt Coefficients and Signal Data
26-Bit Accumulator Per Stage
Filter Lengths Over 1000 Taps
Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 3 or 4
Applications
The HSP43881 OF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single OF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits pro·
cessing filter lengths of over 1000 taps with the guarantee of
no overflows. In practice, most filter coefficients are less than
1.0, making even larger filter lengths possible. The OF provides for B-bit unsigned or two's complement arithmetic,
independently selectable for coefficients and signal data.
• 1-0 and 2-D FIR Filters
•
•
•
•
Radar/Sonar
Adaptive Filters
Echo Cancellation
Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP43881JC·20
OOC to +70oC
84 Lead PLCC
HSP43881JC·25
OOCto +70oC
84 Lead PLCC
HSP43881JC·30
OOCto +70oC
84 Lead PLCC
HSP43881 GC·20
OOC to +70oC
85 Lead PGA
HSP43881 GC·25
OOC to +70oC
85 Lead PGA
HSP43881 GC·30
OOC to +70oC
85 Lead PGA
Each OF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2·0 operations such as
matrix multiplication and NxN spatial correlations/convolutions for image processing applications.
Block Diagram
Vee
DIENB ~
Vss
~
DINO -DIN7 TCS
CIENB>~5~~~::::~;:Et::~;:3E::~:;:t::::~:3::::~;:t::::i~3:::~==-'
DCMO·1
ERASE
TCCI
CINO-7
Teco
eOUTO·7
RESET
ClK~~~-r----4-~----~-r----~~------~r-----~~----~-+----~
ADRO·2
RESET
ClK
ADRO, ADR1, ADR2
2
SHADD
~»::::;,~:::::::::::::::::::::~~~~
SENBH
2
CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-110
File Number
2758.3
HSP43881
Pinouts
85 PIN GRID ARRAY (PGA)
V'S
00EiiJ
Voo
VCC
Tceo
C
COOTS
AUGH
PIN
D
COUTS
E
coon
Vso
coon
Vss
COOTO
SH'"
ADR'
DGMO
OU(
ADR'
ADAD
Voo
SUM25
K
SENiiH
DCM1
COO,..
RESEr
0lN7
DI""
ERASE
""'"'
DIN3
DIN1
0lN2
DIN5
DI'"
SUM24
SUM"
..=:,:,.:.:;.:-
CiENi
TOCI
elN7
.. ......: ..'
Voo
CI""
VSS
CIN4
CINS
.......
.. :'::':,::',
:::"
DINO
elN2
VCC
elN1
CINO
SE....
SUMO
Voc
'.'
': : ':-'... ...... :.
'. :·.iHSP4388f
I·"'"
VS•
..
'
.
..PlNsilOwi,j"
: ....
SUM2
SUMt
a
a
a
a
a
a
a
a
a
a
SENiii
SUNN
Voo
SUM25
ADRt
ADRO
VS.
COUTt
DCMO
VS.
SUM22
V59
Voc
SUM21
SUM18
SUM14
SUM1S
SUM15
Voo
SUM7
SUM12
SUN13
SUM10
Vss
SU'"
SUMl1
Vss
SUMB
COUT5
Voo
SUMS
Vss
v••
Voo
SUMt.
SUM20
v••
COUTa
01lEN.
SUM13
VS•
SUM15 SUM12 SUNtO
SUM17 SUM18
SUNn
SUMa
SUM7
OU(
PINS UP
ooon
SUMl
SUM3
SUMO
Voo
elN1
elNO
CIN2
DIENS
DINS
0lN4
ERASE
TO.
DtNt
DIN2
RESET
DIN7
0lN8
DIN3
AUGH
PIN
COUTT TCeo
.Q
Vso
Voo
SUMS
COUTO SHADD
COUT3 COUT4
SUM20 SUM17
a a a a a a a a
a a a a a a a a
a a a
a
a
a
a a
HSP43881
BOTTOM
VIEW
a
a a
a
a a
a
a
a a a
a
a a a a a CiENB
a a a
a a a a a a a a
SUM23 9U"'22 SUU2' 9UM18 SUU14
ADA.
....:..:. .. ,'tOP:ViEW
I·'
a
a
a
a
a
a
a
a
a
a
a
DCM1
Voo
ClHO
DINO
0.,7
CINa
TCCI
Voo
a
a
a
a
a
a
a
SEi_-------------------------------....,
>_------------------,
~>---------~---------~--+------~----,
~>_---~-t_-------~--r_--+_----1__r--~
3-STATE BUFFERS
ON CELL 7 ONLY
-------1
TCCI .Ht"----i
I
I
I
I
TCCO
COUTO-7
RESET.O
DIENB.D
TCS
C
DINO-7
i:::==)l-"'-t===========~===:::;:==~
CLK
LATCHES
X PliER
MULTICORE
PO-17
iiEiffi
DCMl
DCM1.0
DCMO
DCMO.D
iiEffi
RESET.D
DIENB
DIENI.D
Ciiiii
CIENB.O
ADRO
ADRO.D
ADRI
ADR1.D
ADR2
ADR2.D
iiim
EHASE.D
CLK
EHASE.D
CELLo
CEll 0
ADRO
ADRI
ADR2
DECODER
••
•
CELLI
CELL 7
CEllI
ADUTD-25
FIGURE 1.
HSP43881 FILTER CELL
3-115
HSP43881
o
1
The SUMO-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUMO-15. A
low on SENBH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously if the external system has a
26-bit or larger bus. If the external system bus is only 16
bits, the bits can be enabled in two groups of 16 and 10 bits
(sign extended).
6 7
OF Arithmetic
Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS
and TCCI inputs determine the type of arithmetic
representation. Internally all values are represented by a
9-bit two's complement number. The value of the additional
ninth bit depends on the arithmetic representation selected.
For two's complement arithmetic, the sign is extended into
the ninth bit. For unsigned arithmetic, bit 9 is O.
18 MSB'S SHIFTED
8 BITS TO RIGHT
(BITS O' 17)
The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without
overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient
and data values. Then maximum numbers of terms in the
sum products are:
NUMBER SYSTEM
CLK
FIGURE 2.
SUMO· 25
HSP43881 OF OUTPUT STAGE
The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the
SUMO-25 bus. The output mux determines whether the cell
accumulator selected by ADRO-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD
input signal. Control is based on the state of the SHADD
during two successive clocks; in other words, the output
mux selection contains memory. If SHADD is low during a
clock cycle and was low during the previous clock, the
output mux selects the contents of the filter cell
accumulator addressed by ADRO-2. Otherwise the output
mux selects the contents of the output buffer.
If the ADRO-2 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent· accumulator updates in the
addressed cell. Only the result available during the first
clock when ADRO-2 selects the cell will be output. This
does not hinder normal FIR operation since the ADRO-2
lines are changed sequentially. This feature facilitates the
interface with slow memories where the output is required
to be fixed for more than one clock.
MAX #
OF TERMS
Two unsigned vectors
1032
Two two's complement:
• Two positive vectors
• Negative vectors
• One positive and one negative vector
2080
2047
2064
One unsigned and one two's complement
vector:
• Positive two's complement vector
• Negative two's complement vector
1036
1028
For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.
Basic FIR Operation
A simple, 30MHz 8-tap filter example serves to illustrate
more clearly the operation of the DF. The sequence table
(Table 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, Cn,
enters the DF on the left and moves from left to right through
the cells. The data sample sequence, Xn, enters the DF from
the top, with each cell receiving the same sample
simultaneously. Each cell accumulates the sum of products
for one output point. Eight sums of products are calculated
simultaneously, but staggered in time so that a new output
Is available every system clock.
3-116
HSP43881
TABLE 1.
HSP43881 30MHz, 8 TAP FIR FILTER SEQUENCE
CO· .. Ce, C7. Co ... Ce. C7
CLK
CELLO
0
1
2
C7 xXO
+Ce XX1
+CSXX2
+C4 XX3
+C3 xX4
+C2 XXS
3
4
S
e
7
a
9
10
11
12
13
14
lS
CELL 1
CELL 2
CELL 3
0
0
0
0
0
0
C7 XX1
+Ce XX2
+Cs xX3
+C4 xX4
C3 xX s
+C2 XXe
+C1 xXe
+COxX7
C7 XXa
+CexXg
+CS XX10
+C4 XX11
+C3 x X12
+C2 x X13
+C1 x X14
+Co XX 1S
--+
C7 XX2
+Ce xX3
+CSXX4
+C4 XXS
+C3 XX e
+C2 XX7
+C1 XX7
+CoxXa
C7 xX9
+Ce xX 10
+CS xX11
+C4 XX12
+C3 xX 13
+C2 xX14
+C1 XX1S
+C1 xXa
+COxXg
C7 xX 10
+Ce XX11
+CSxX12
+C4 xX 13
+C3 xX 14
+C2 XX 1S
C7 XX3
+Ce XX 4
+CsxXs
+C4 XXe
+C3 xX7
+C2 XXa
+C1 xXg
+CO XX10
C7 X X11
+Ce XX 12
+CS xX 13
+C4 xX14
+C3 xX 1S
HSP43881
CELL 4
C7 xX 4
+CexXs
+CsxXe
+C4 XX7
+C3 xXa
+C2 xX9
+C1 xX10
+COXX11
C7 XX12
+Ce xX 13
+CSxX14
+C4 XX1S
•••• Y1S. Y14 ••• Y8, Y7
CELLS
C7 xX S
+CexXe
+CSXX7
+C4 XXa
+C3 xX9
+C2 XX10
+C1 XX11
+COXX12
C7 xX 13
+Ce XX 14
+CS XX1S
CELL 8
CELL 7
SUM/CLR
-
C7 XXe
+Ce XX7
+CsxXs
+C4 xX9
+C3 xX 10
+C2X X11
+C1 XX12
+CO xX 13
+C7 XX 14
+Ce XX1S
Cell 0 (Y7)
Cell 1 (ya)
CeIl2(Yg)
Cell 3 (y10)
Cell 4 (Y11)
CeIlS(y12)
Celle(y13)
Cell 7 (Y14)
Cell 0 (Y1 S)
C7 XX7
+CexXa
+CSxXg
+C4 XX 10
+C3 x X11
+C2 XX12
+C1 x X13
+COxX14
C7 XX1S
SAMPLE
DATA IN
(X n )
30MHz
)-<
CLOCK
BIT
P. COUNTER
3
Y2
Y1
+5V
Yo
I
I
,
A2
Al
"*
AO
Do-D7
8x8 COEFF.
/8
ADR2 ADRl ADRO VCC SHADD SENBH SENBl
SUMO-25
DIN0-7
r<
5iEiiiB
I-
TCS
HSP43881
'--
NC
TCCO
CIN0-7
CiENB
-- -I T
COUT0-7
DCMl DCMO RESET ERASE VSS COENB
I
1 T
~
"E"i'iASE
FIGURE 3.
2e/
TCCI
T I
SYSTEM
RESET
~
CLK
--, , /8
RAM/ROM
I 1 1
HSP43881 30MHz, 8 TAP FIR FILTER APPLICATION SCHEMATIC
3-117
,
8/
NC
HSP43881
Detailed operation of the DF to perform a basic 8-tap, 8-bit
coefficient, 8-bit data, 30M Hz FIR filter is best understood
by observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Figures 1 and 2).
Therefore the delay from presentation of data and
coefficients at the DINO-7 and CINO-7 inputs to a sum
appearing at the SUMO-25 output is:
The output sums, Vn, shown in the timing diagram are
derived from the sum-of-products equation:
V(n) = C(O) x X(n) + C(l) x X(n-l) + C(2) x X(n-2) + C(3)
x X(n-3) + C(4) x X(n-4) + C(5) x X(n-5) + C(6) x X(n-6)
+ C(7) x X(n-7)
Extended FIR Filter Length
Alter lengths greater that eight taps can be created by
either cascading together multiple DF devices or "reusing"
a single device. Using multiple devices, an FIR filter of over
1000 taps can be constructed to operate at a 30MHz
sample rate. USing a single device clocked at 30M Hz, an
FIR filter of over 1000 taps can be constructed to operate at
less than a 30MHz sample rate. Combinations of these two
techniques are also possible.
k +Td
where
k = filter length
Td = 4, the internal pipeline delay of DF
After the pipeline has fiffed, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
o
1
2
3
4
5
6
7
8
9
10 11
12 13 14
15 16
17 18
19
20
ClK
01NO-7
DIENB ______________________________________________________
CINO-7
I c,l c'l c'l c. I c'l C21 c, ICo I c, I c. Ic. I c.1 c'l c21 c, I Co I c'l c'l c. I
~------------------------------------------------------
ADRO-2
101,121,1.1.1.17101
I~I~I~I~I~I~I~I~I
SUMO-24
SHADD ~$~~ffA
SENSl Z000Yftff~$/~A
SENSH '000'"h07~~~ff&Y~
OCMO-'
1 11-----------------------------------------------0
,
YN "" L CK
K= 0
FIGURE 4.
x XN-K
HSP43881 30MHz, 8 TAP FIR FILTER TIMING
SAMPLE
DATA IN
(Xal
rr=[]
o
30MHz
CLOCK
0
I I I T~
ADR1 ADRI ADRZ
L'r
vee
I I
h
IHADD Il"IN IlNIL
"
SUMO-t.. -+--
01NI-7
r- DiiHi
f-
~I-
TC.
H5P43881
elX
OFO
,...~
AI KAMIAOM
e liT
Y1
eTR Y2
Y3
!
SYITEM
RrlIT
"T
--
."
-A3
AGURE 5.
DO-07
~
~
TCeo
--
COUTI-7
"*-
TCCI
ClNO-l
Ciiiii DC.,
DCMO
~
1
Ix11 COEFF.
eLK YI
iiii"iT iiiii Vaa Ciiiiii
I 1;,"
IT~
lOR1 ADM ADa Vtc 'HADD
-
,--.
~
IEN'N ""lL
IUMI-2"
OJNI-7
~
DiiNi
TCO
H5P43881
ClX
OF1
TeeD
TeCI
CINO-7
Ciiii
DC.' DC. .
CDurl-l
iiiiii iiiii 'II Ciiiiii
- .e.
r+ -
l-
I I"
HSP43881 30MHz, 16 TAP FIR FILTER CASCADE APPLICATION SCHEMATIC.
3-118
HSP43881
Cascade Configuration
To design a filter length L>8, L/8 OFs are cascaded by
connecting the CQUTO-7 outputs of the {i)th OF to the
CINO-7 inputs of the {i+1)th OF. The OINO-7 inputs and
SUMO-25 outputs of all the OFs are also tied together. A
specific example of two cascaded OFs illustrates the
technique (Figure 5). Timing (Figure 6) is similar to the
simple 8-tap FIR, except the ERASE and SENBL/SENBH
CLK
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CELLO
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELLS
CELL 7
Co x X21
o
C15 XX7
+C14 xX8
+C13 xX9
+C12 xX 1Q
+C11 XX11
+C1Q xX12
+C9 xX 13
+C8 xX 14
+C7 xX 15
+C6 xX 16
+C5 xX 17
+C4 xX 18
+C3 XX 19
+C2 xX20
+C1 x X21
+COxX22
SUM/CLR
o
o
o
C15 XX3
+C14 xX4
+C13 xX5
+C12 XX6
+C11 XX7
+C10 xX 8
+C9 xX9
+C8 XX 10
+C7 XX11
+C6 xX12
+C5 xX 13
+C4 XX14
+C1 XX14
+Co XX15
+C12 xX11
+C11 XX12
+C10 XX 13
Using a single OF, a filter of length L>8 can be constructed
by processing in L/8 passes as illustrated in the following
table (Table 2) for a 16-tap FIR. Each pass is composed of
HSP438811S-TAP FIR FILTER SEQUENCE USING A SINGLE OF
+C6 xX9
+C5 XX10
+C4 xX 11
+C3 xX 12
+C2 xX 13
C15 X Xs
+C14 XX9
+C13 xX 1Q
Single DF Configuration
TABLE 2.
C15 XXO
+C14 x X1
+C13 xX2
+C12 xX3
+C11 xX4
+C10 xX5
+C9 xX6
+C8 xX7
+C7 XX8
o
o
o
o
o
o
o
signals must be enabled Independently for the two OFs in
order to clear the correct accumulators and enable the
SUMO-25 output signals at the proper times.
CO xX 16
o
o
COXX17
o
o
o
o
o
o
o
o
o
o
o
C15 XX9
o
C15 XX 1Q
+C3 xX 15
+C2 xX 16
+C1 xX17
+CO XX 18
o
o
o
o
o
o
o
C15 XX 11
CO xX 19
o
o
o
o
o
o
o
C15 x X12
COXX20
o
o
o
o
o
o
o
C15 xX 13
+C9 xX 14
+C8 xX 15
o
o
o
o
o
o
C15XX14
~
w
!:i
ii:
....c
CELLO(Y15)
CELL 1 (Y16)
CELL 2 (Y17)
CELL3(Y18)
CELL4(Y19)
CELL 5 (Y20)
CELL6(Y21)
CELL 7 (Y22)
0
0
0
0
0
0
0
C15 xX 15
+C14 xX 16
+C13 xX17
+C7 XX16
+C6 xX17
+C5 XX18
+C12 xX18
+C4 xX 19
+C3 xX 20
+C2 XX21
+C1 xX22
+CO xX 23
o
o
o
o
3-119
+C11 xX19
+C10 XX20
+C9 xX 21
+C8 xX 22
+C7 xX23
+C6 xX24
CELL 0 (Y23)
CELL 1 (Y24)
+C5 xX 25
+C4 xX 26
+C3 xX 27
CELL 2 (Y25)
CELL 3 (Y26)
CELL 4 (Y27)
HSP43881
Tp = 7 + L cycles and computes eight output samples. In
pass i, the sample with indices i*8 to i*8 +(L-1) enter the
DINO-7 inputs. The coefficients Co - CL - 1 enter the
CINO-7 inputs, followed by seven zeros. As these zeros are
entered, the result samples are output and the accumulators reset. Initial filing of the pipeline is not shown in this
sequence table. Filter outputs can be put through a FIFO to
even out the sample rate.
accomplished with external adders (at full speed) or with the
DF's shift-and-add mechanism contained in its output
stage (at reduced speed).
Decimation/Resampling
The HSP43881 DF provides a mechanism for decimating
by factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2, or 3 clocks through the cell.
The sequence table (Table 3) for a decimate-by-two- filter
illustrates the technique (internal cell pipelining ignored for
simplicity).
Extended Coefficient and
Data Sample Word Size
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 8x8 and
combine these partial prod'ucts by shifting and adding to
obtain the final result. The shifting and adding can be
•
,
2
:I
..
I
•
l'
•
t/ 1.
11
12
13
14
11
I.
17
1.
Detailed timing for a 30MHz input sample rate, 15MHz
output sample rate (I.e., decimate-by-two), 16-tap FIR filter,
including pipelining, is shown in Figure 7. This filter requires
only a single HSP43881 DF.
11
21
tr
2'Z 23
2t
25
21
27
2'
21
30
31
32
33
'4
35
al
37
38
31
.. I
D"~-ILJ==~~~~~~~~~~~~~~~~~~~~~::::::::::::::::~~~~~~~~~::::::::=
DF. (RASf _
CIII'-7
e"••
~
'
-
-
R
o
f
i
f
f
DIIII-7
I Xe I x, I X2 I X3 IX.. I Xs I X.I X7 I X, I x, Ix,., Xl1l X,zl X131 X141 XIS' XIII Xnl XI.IXI.,XloIXn!X22!X23IXZ4IX2lIX21IXnIX11IXn!X3aIX31IX32IX331X341X3511311 Xnl
________________________________________
_
Ie" Ie" le"le,,1 e"le"le, I e, I c, Ie. I e,l e, I e, I e,ltole"le" le"le" Ic"le,.1 e,le, Ie, Ie, Ie. Ie, Ie, Ie, I e, I eale"le"le"le" le,,1 c,,1
--.L-_________________________________________
_
Cd
I ' I' I ' I' I ' I • I • I ' I ' I ' I • I , I ' I • I , I ' I • I , I ' I , I
ADR'-'
DFO.UNO-21
OFt SUMO-2S
DfD SfNIUH
IHADO
DF1 SU,utI
DCM'-'
= 0<=i!= =b=#=wr=#=#=0h=W-=#=#=~k=1'r=*=i=ur=fb=#=#=wA=p;=m=m=7h=~=%b=0/-=W.=U=W/'=W.=4=W.=W/'=w.=*,==~;;~;;;;~~~~~~~~~~;;;;
I' r l - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -....
15
.-.
FIGURE 6.
HSP43881 16-TAP 30MHz FIR FILTER TIMING USING TWO CASCADED HSP43881s
3-120
HSP43881
TABLE 3.
HSP4388116-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT
Dala
Sequence
Input
Coefficient
Sequence ••• C15,CO· .• C13,C14,C15
Input
CLK
CELLO
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
e
7
8
9
10
11
12
13
14
15
16
17
18
C15 XXO
+C14 xX1
+C13 xX2
+C12 xX3
+C11 x~
+C10 xX 5
+C9 xXe
+C8 xX7
0
0
C15 xX 2
0
0
0
0
C15 xX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C15 XX 10
0
0
0
0
C15 xX12
0
0
C15 XXe
+C7 XX8
+CexXg
C15 xX8
+C5 xX 10
+C4 xX 11
+C3 xX 12
+C2 xX 13
19
20
21
22
23
24
25
26
27
28
29
SUM/CLR
-
-
0
+C1 XX14
-
-
C15 XX14
+C14 XX15
+C13 xX 16
+C12 XX17
+C11 XX18
+C10 XX 19
+C9 xX 20
+C8 xX21
+C7 XX22
+CO XX15
C15 xX 16
+C14 XX17
+C13 xX 18
+C12 x X19
+C11 xX20
+C10 XX21
+C9 xX 22
+C8 xX 23
+C6 xX 23
+C7 xX 24
+C5 XX24
+Ce xX 25
+C4 XX25
+C5 xX 26
+C3 xX26
+C4 XX 27
+C2 xX 27
+C3 xX 28
+C1 XX28
+C2 xX 29
+CO XX29
+C1 xX30
C15 XX30
+CO xX31 +C14 XX 31 +C14 xX31 +C14 XX31 +C14 xX31 +C14 xX31 +C14 XX31 +C14 XX31
30
31
32
33
34
35
36
37
!
! !
1
2
3
..
5
I
7
1 !
!
•
t
10
11
12
13
14
15
,.
17
18
!
11 20
21
22
23
24
!
25
28
27
28
CELL 0 (Y15)
CELL 1 (Y17)
!:i
CELL 2 (y19)
...
-
CELL3(y21)
CELL 4 (Y23)
CELL 5 (Y25)
CELL 6 (Y27)
CELL 7 (y29)
CELL 8 (Y31)
!
29
30
:t1
32
33
!
34
35
31
3T
3'
39
40
eLK
ERASE
I Xo I X, I X2 I X3 I X4 I X5 I X, I X7 I x. I X9 IX,0 IX11 I X121 x,31 X141 Xlsl X,. Ix171 x, .I XI9 Ix201 x2l1 x221x231 x24 1x25lx26Ix27lx2,lx29Ix301 X:n Ix32 1x331 x341x351 X3.lx371
DIND-7
'lEN8 ---,L________________________________________________________________________________________
CINI-l
~
I C151 C14 1C 31 C 21 C11 1C, ol
C9
I £. I C7 I £. I C5 I C4 I C3 I C2 I c, I Co I C151 C141 t'31 cui Clll C'01 c, I c. I C7 I c, I Cs I Col I C3 I C21
I Co I C'S I C'41 C'31 cui C11l t ,o I
'
'
---,L______________________________________________________________________________________
__
ADRO-2
•
I
Iv,,1
SUMO-25
SHADD
WffffffffMffMWffi'MMWM h0WhM//ffM M$400W@/MWI41
SENal
w#/L.00W!hW4WhW/(0'MffWd000W!u/ffulff//////h/lffrW/H//pW#.#&/ffi'/4
DCM'-1
C,
I
1
1
I
Iv,,1
2
I
Iv,,1
3
I
Iv~1
•
I
Iv,,1
•
I
Iv,,1
•
I
Iv,,1
7
I
Iv,,1
•
I
IV~I
1
I
Iv,,1
1-1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FIGURE 7.
HSP43881 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT
3-121
~
w
ii:
Q
Specifications HSP43881
Absolute Maximum Ratings
Supply Voltage ................................................................................................. +8.0V
Input,OutputVoltage .......................................................................... GND -0.5V to VCC +0.5V
Storage Temperature ................................................................................. -650C to +1500 C
ESD ......................................................................................................... Class1
Maximum Package Power Dissipation at 700C .................................................. 2.4W (PLCC), 2.88W (PGA)
0jc ......................... , ....................................................... 11.1 0 C/W (PLCC), 7.78 0 C/W (PGA)
Oja ................................................................................ 33.70 C/W (PLCC), 34.66 0 C/W (PGA)
Gate Count .................................................................................................... 17763
Junction Temperature ...................................................................... 1500C (PLCC), 1750C (PGA)
Lead Temperature (Soldering 10s) ............................................................................... 3000C
CAUTION: Stresses above those listed in the "Abso/ute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . • . • • . . • . . . . .. 5V ±5%
Operating Temperature Range ............................................................................ OoC to + 700C
D.C. Electrical Specifications
SYMBOL
PARAMETER
ICCOp
Power Supply Current
ICCSB
Standby Power Supply Current
MIN
MAX
UNITS
-
140
mA
VCC = Max
CLK Frequency 20MHz
Note 1, Note 3
TEST CONDITIONS
-
500
IlA
VCC = Max, Note 3
II
Input Leakage Current
-10
10
IlA
VCC = Max, Input = OVorVCC
10
Output Leakage Current
-10
10
IlA
VCC = Max, Input = OV orVCC
VIH
Logical One Input Voltage
2.0
-
V
VCC= Max
VIL
Logical Zero Input Voltage
0.8
V
Vcc=Min
10H = -4001lA, VCC = Min
VOH
Logical One Output Voltage
2.6
-
V
VOL
Logical Zero Output Voltage
-
0.4
V
10L = 2mA, VCC = Min
VIHC
Clock Input High
3.0
-
V
VCC= Max
VILC
Clock Input Low
0.8
V
VCC=Min
CIN
Input Capacitance
-
-
10
15
pF
pF
-
10
15
pF
pF
CLK Frequency 1 MHz
All measurem ents referenced
toGND
TA = +250 C, Note 2
COUT
PLCC
PGA
Output Capacitance PLCC
PGA
NOTES:
1. Operating supply current is proportional to frequency. Typical rating is
7mNMHz.
2. Controlled via design or process parameters and not directly tested. Char·
acterized upon initial design and after major process and/or design
changes.
3. Output load per test load Circuit and Cl = 40pF.
3-122
Specifications HSP43881
A.C. Electrical Specifications
SYMBOL
PARAMETER
vcc = 5V ±5%, TA = ooc to +700 C
-20 (20MHz)
-25 (25.6MHz)
-30 (30MHz)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
39
-
33
ns
13
0
-
0
-
-
20
-
18
ns
-
15
-
15
ns
20
15
-
15
ns
27
-
25
-
21
ns
6
-
6
-
6
ns
Note 1
6
-
6
ns
Note 1
TCp
Clock Period
50
TCl
Clock low
20
TCH
Clock High
20
TIS
Input Setup
16
TIH
Input Hold
0
-
ClK to Coefficient
Output Delay
-
24
-
20
TOOC
TOEO
Output Enable Delay
TOOD
Output Disable Delay
TO OS
ClKtoSUM
Output Delay
TOR
Output Rise
TOF
Output Fall
-
TEST
CONDITIONS
16
16
14
6
13
13
ns
ns
ns
ns
Note 1
NOTE:
1. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
Test Load Circuit
r--------------1
1
1
1
1
1
1
:
1
1
1
I
1
1.5V
1
'INCLUDES STRAY AND 1
JIG CAPACITANCE
1_ _ _ _
Swnch 51 Open for
EQUIVALENT~IRCUIT _ _ _ _
'ccss and ICCOp Tests
3-123
1
J
HSP43881
Waveforms
O.OV
CLK
_TIH1_
3.0V-----INPUT'
O.OV-----...J
~
• Input includes: DINO-7, CINO-7, DIENB, CIENB, ERASE,
RESET, DCMO-1, ADRO-2, TCS, TCCI, SHADD
CLOCK AC PARAMETERS
INPUT SETUP AND HOLD
CLK~------f-=TODC. Taos ______ _
~5V
1..------------
SUMO-25
W[V
O.~
COUTO-7
TCCO
--T-O-R-~-
• SUMo-25, COUTo-7, TCCO are assumed not to be in
high-impedance state
SUMO-25, COUTO-7, TCCO OUTPUT DELAYS
OUTPUT RISE AND FALL TIMES
"SENBL
SENBH
3.0V---",
INPUT
COENB Et--.:-O-E-D-----.:-O-DFV
SUMO-2S
COUTO
TCCO
-7----_
HIGH
1.7V
1.3V
O.OV--_J
D~
IMPEDANCE
~
HIGH
IMPEDANCE
A.C. Testing: Inputs are driven at 3.0V for logic "1" and O.OV for logic "0".
Input and output timing measurements are made at 1.5V for both a Logic "1"
and "0". ClK is driven at 4.0V and OV and measured at 2.0V.
OUTPUT ENABLE, DISABLE TIMING
A.C. TESTING INPUT, OUTPUT WAVEFORM
3-124
HSP438811883
HARRIS
SEMICONDUCTOR
Digital Filter
January 1994
Features
Description
• This Circuit is Processed in Accordance to MIL·STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HSP43881/883 is a video speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells cascaded
internally and a shift and add output stage, all in a single
integrated circuit. Each filter cell contains a 8 x 8-bit multi·
plier, three decimation registers and a 26-bit accumulator.
The output stage contains an additional 26-bit accumulator
which can add the contents of any filter cell accumulator to
the output stage accumulator shifted right by 8-bits. The
HSP43881/883 has a maximum sample rate of 25.6MHz.
The effective multiply accumulate (mac) rate is 204M Hz.
• OMHz to 25.6MHz Sample Rate
• Eight Filter Cells
• 8·Bit Coefficients and Signal Data
• Low Power CMOS Operation
• ICCSB 5001JA Maximum
• Iccop 160mA Maximum at 20MHz
• 26·Bit Accumulator Per Stage
• Filter Lengths Up to 1032 Taps
The HSP43881/883 DF can be configured to process
expanded coefficient and word sizes. Multiple DFs can be
cascaded for larger filter lengths without degrading the sam·
pie rate or a single DF can process larger filter lengths at
less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two's complement
arithmetic, independently selectable for coefficients and sig·
nal data.
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1·0 and 2·0 FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multlply·Add
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2 , 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2·D operations such as
,matrix multiplication and N x N spatial correlations/convolu·
tions for image processing applications.
• Sample Rate Converters
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP43881 GM·20/883
-55°C to +125°C
85 Lead PGA
HSP43881 GM·251883
-55°C to +125°C
85 Lead PGA
Block Diagram
DINO • DIN7 TCS
TCCI
TCCO
CINO-7
COUTO· 7
Rm'f
CLK~~~~""""~~""""""~+-""""~~""""""~+-""""~~""""""~+-""""-"
ADRO-2
iiEsE'i'
ClK
SHADD
ADRO, ADR1, ADR2
2
~»::::;~::::::::::::::::::::::~~~~
SeNBii
2
SUMO-2S
CAUTION: These devices are sens~ive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-125
File Number
2449.3
~
w
!:i
u::
....Q
HSP43881/883
Pinouts
85 PIN GRID ARRAY (PGA)
4
vss
eOENB
Vee
REsET
DIN7
DIN8
DIN3
DINO
TeCI
Vee
vss
B
Vee
COUT7
Teeo
ERASE
Tes
DIN1
OlN2
elENS
ClN7
CIN6
CIN4
e
COUT5
eOUT8
DIENB
DINS
DIN4
CINS
CIN3
0
eOU13
caUT4
CIN2
Vee
E
coun
Vss
COUT2
CINl
CINO
SENBl
Vss
COUTO
SHADD
SUMO
Vee
G
ADR2
DeMO
eLK
SUMl
SUM3
8UM2
H
ADAl
AORO
SUMS
SUM4
Vee
SUM25
SUM7
Vss
S'E'NBH
8UM24
Vss
oeM1
SUM23
0
oeM I
K
0
0
0
VCC
0
ADRI
G
0
ADR2
F
0
VSS
E
o
ALIGN
PIN
0
SUM1?
SUM16
Vee
SUM19
Vss
SUM15
SUM12
SUM10
SUM8
SUMe
SUM22
8UM21
SUM18
SUM1.
Vee
SUM13
Vss
SUM11
SUM9
3
4
5
6
10
11
0
0
0
0
0
0
VSS
Vec
0
0
SUMI9
0
0
VSS
a
7
0
SUMI8 SUMI4
SUM20
SUM25
Vee
0
SUMI3
0
0
9
0
VSS
0
SUMIS SUMI2 SUMIO
0
0
0
SUM5
0
0
0
0
0
VSS
0
0
0
0
0
HSP43881
CLK
SUM1
0
BOTTOM VIEW
COUTO SHADD
0
SUMO
PINS UP
0
0
CINI
COU12
COUT5 COUT6
B
0
VCC
A
0
Vss
0
0
0
VCC
0
CINO
CIN2
0
0
ALIGN
PIN
0
COUT7 TCCO
COENB
0
SUM3
0
COUT3 COUT4
C
0
SUMa
SUM7
0
COUll
0
SUMII
0
SUMI7 SUMI6
ADRO
DCMO
Vss
SUM20
SUM23 SUM22 SUM21
SENBH SUM24
H
11
A
K
L
10
0
VCC
DIENB
0
ERASE
0
RESET
0
TCS
0
DIN7
0
DIN5
0
DINI
0
DIN6
0
DIN4
0
DIN2
0
DIN3
0
CIENB
0
DINO
0
0
SUM6
0
VSS
0
SUM4
0
8UM2
0
Vss
0
SENBL
0
VCC
0
0
CIN5
CIN3
0
0
CIN7
CIN6
0
0
0
VCC
Vss
TCCI
Note: An overbar on a signal name represents an active LOW signal.
3-126
0
SUM9
CIN4
Specifications HSP43881/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage ........................................ +8.0V
Input, Output Voltage Applied .. . . . . . • .. GND-0.5V to V CC+0.5V
Storage Temperature Range ................. -65 0 C to +150 0 C
Junction Temperature ................................ +1750 C
Lead Temperature (Soldering, Ten Seconds) ......•..... +300 0 C
ESD Classification ........•...•...............•....... Class 1
Thermal Resistance
Sja
Sjc
Ceramic PGA Package ...••...... " 34.66 0 C/W 7.78 o C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package ............••.............. 1.44 Watt
Gate Count ...•..........••.•................... 17762 Gates
CAUTION: Stresses above those listed in 'IAbso/ute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specificatIOn is not implied.
Operating Conditions
Operating Voltage Range ......•................ +4.5V to +5.5V
Operating Temperature Range ............... -55 0 C to +125 0 C
TABLE 1. HSP43881/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested
PARAMETER
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
MAX
UNITS
Logical One Input
Voltage
VIH
VCC= 5.5V
1,2,3
-55°C ~ TA ~ +125 0 C
2.2
-
V
Logical Zero Input
Voltage
VIL
VCC=4.5V
1,2,3
-55°C ~ TA::;: +125 0 C
-
0.8
V
SYMBOL
CONDITIONS
Output HIGH Voltage
VOH
10H = -400~A
VCC = 4.5V (Note 1)
1,2,3
-550C.:5.TA.:5.+1250C
2.6
-
V
Output LOW Voltage
VOL
IOL=+2.0mA
VCC = 4.5V (Note 1)
1,2,3
-55°C .:5.TA:S: +125 0 C
-
0.4
V
II
VIN=VccorGND
VCC=5.5V
1,2,3
-55 0 C.:5. TA:S:+1250C
-10
+10
~
Output Leakage
Current
10
VOUT=VCCorGND
VCC=5.5V
1,2,3
-550C.:5. TA:S. +125 0 C
-10
+10
~A
Clock Input High
VIHC
VCC=5.5V
1,2,3
-550 C
< TA:S: +125 0 C
3.0
-
V
VILC
VCC=4.5V
1,2,3
-550 C:S. TA ~ +125 0 C
-
0.8
V
-
500
~A
mA
Standby Power Supply
Current
ICCSB
VIN=VccorGND
VCC=5.5V,
Outputs Open
1,2,3
-550C:S. TA ~ +125 0 C
Operating Power
Supply Current
ICCOp
f=20.0MHz
VCC = 5.5V (Note 2)
1,2,3
-550C ~ TA:S: +125 0 C
-
160.0
7,8
-55°C ~ TA:S. +125 0 C
-
-
Functional Test
FT
a:
w
!:i
ii:
Input Leakage Current
Clock Input Low
(f)
(Note 3)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Operating .Supply Current is proportional to frequency. typical rating is
8.0mA/MHz.
3. Tested as follows: f = 1 MHz, VIH
VOL:s' 1.5V, VIHC = 3.4V, and VILC
3-127
= 26,
= O.4V.
VIL
0.4, VOH
~
1.5V,
....Q
Specifications HSP43881/883
TABLE 2. HSP43881/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Testlld
GROUPA
SYMBOL CONDITIONS SUBGROUPS
PARAMETER
Clock Period
Clock Low
-20 (20M Hz)
25 (25.6MHz)
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
-
ns
ns
TCp
Note 1
9,10,11
-550 C.$TA <+1250 C
50
-
39
TCL
Note 1
9,10,11
-55 0 C.$ TA:::; +1250 C
20
-
16
20
-
16
20
17
0
-
ns
-
20
ns
Clock High
TCH
Note 1
9,10,11
-550 C
.,
~
""
>
SUM23
COUT6
SUM22
COUT7
Vee
Vss
SUM21
Teeo
SUM20
COENB
SUM1.
Vee
SUMt8
ERASE
Vss
RESET
CIENB
8UM17
Tes
8UM1.
DIN7
Vee
DIN&
SUM1S
DIN5
SUM14
DIN4
SUM13
DIN3
DIN2
SUM12
DIN1
Vss
DINO
SUM11
CIENB
SUY10
Teel
SUMI
Vee
SlIMB
SELECT 891
SlIM7
3-130
HSP43891
HARRIS
SEMICONDUCTOR
Digital Filter
January 1994
Features
Description
•
•
•
•
•
•
•
The HSP43B91 is a video-speed Oigital Filter (OF) designed
to efficiently implement vector operations such as- FIR digital
fiiters. It is comprised of eight fiiter cells cascaded internally
and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 9 x 9 two's complement multiplier, three decimation registers and a 26-bit accumulator.
The output stage contains an additional 26-bit accumulator
which can add the contents of any fiiter cell accumulator to
the output stage accumulator shifted right by B-bits. The
HSP43B91 has a maximum sample rate of 30MHz. The
effective multiply-accumulate (mac) rate is 240M Hz.
Eight Filter Cells
OMHz to 30MHz Sample Rate
90Bit Coefficients and Signal Data
26-Bit Accumulator per Stage
Filter Lengths Over 1000 Taps
Expandable Coefficient Size, Data Size and Filter Length
Decimation by 2, 3 or 4
Applications
•
•
•
•
•
•
•
1-0 and 2-D FIR Filters
Radar/Sonar
Digital Video
Adaptive Filters
Echo Cancellation
Complex Multiply-Add
Sample Rate Converters
The HSP43B91 OF can be configured to process expanded
coefficient and word sizes. Multiple OFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single OF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of
no overflows. In practice, most fiiter coefficients are less than
1.0, making even larger fiiter lengths possible. The OF provides for B-bit unsigned or 9-bit two's complement arithmetic,
independently selectable for coefficients and Signal data.
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
Each OF fiiter cell contains three re-sampling or decimation
registers which permit output sample rate reduction at rates
of '/2, '/3 or '/4 the input sample rate. These registers also
provide the capability to perform 2-0 operations such as
matrix multiplication and N x N Spatial correlations! convolutions for image processing applications.
PACKAGE
HSP43891 VC-20
OOClo +700 C
100 Lead MQFP
HSP43891 VC-25
OOC 10 +700 C
100 Lead MQFP
HSP43891 VC-30
OOC to +700 C
100 Lead MQFP
HSP43891 JC-20
OOC to +700 C
84 Lead PLCC
HSP43891 JC-25
OOC to +700 C
84 Lead PlCC
HSP43891 JC-30
OOCto +700 C
84 lead PlCC
HSP43891 GC-20
OOC to +700 C
85 Lead PGA
HSP43891 GC-25
OOCto +700 C
85 Lead PGA
HSP43891 GC-30
OOC to +700 C
85 Lead PGA
Block Diagram
Vce
~
Vss
~
DINO -DlN8
CINO- 8
COUTO· 8
REsE'i'
ClK~~~-f~--~~~--~-f~--~~~----~~----~~~--~-+~--~
ADRO -2
REsE'i'
ADRO, ADR1, ADR2
ClK
2
SHADD>-____________________________
~
SENBL>____~----------------------+L~~~
SENiiii
2
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation '994
3·131
File Number
2785.3
o
a:
w
~
u::
...c
HSP43891
Pinouts
85 PIN GRID ARRAY (PGA)
10
Yee
coun COUTB IlRAft
DONS
DOII8
DINS
DIN1
DIN2
DONS
DO. .
DONO
CINS
VCC
v..
CIN7
COII8
CON<
CON6
CONS
a a a a a a a a
a a a a a a a a
iiENiH
a a
a a a
a a
a a a
HSP43891
BOTTOM VIEW
a a a
a a a
coun Vas coun
DOMl
8U"23 SUMft 8UM2, SUMl. 8UM14
SUMM
c
COUTS
C0UT8
A~~
H
G
VCC
8U ... 25
ADRl
ADRO
AnAl
VS•
K
Vee
SUN25
iEtiiH
SUNN
Yss
DCMl
SUMIS
8UMI2
SUM20 SUMl7
SUMl.
Vee
BUNla
Vas
SUM15 9UM12
BUM21
SUN1S
SUM1.
Vee
SUMS
8UM4
SUM7
Vas
SUN10
SUNS
8UM8
Vss
8UN11
8UM9
aUN1S
DeMO
v••
VCC
SUM19
8UM2O
Vss
Vee
SUM1S 8UMl. SUN10
eLK
COUTO SHADD
11
C 12
SUM22
~
10
9
8
7
8
IS
4
3
2
PINS UP
a
AUGH
cooT7 COUTa
COENS
1
84 83 82 81
•
80 7&
ERASE
0lN8
DIN5
DO...
DlNl
DIN2
Vee
RESET
DIN7
DtN8
74
~
COUT8
au:: E::
=
71~~
SUM1S
Yss
8UN17
72
18
70
= 17
= 18
,.
=
20
SUM1.
21
HSP43891
TOP VIEW
su:c:E:
E
8U::~ :
~
8::: =:
=
8UM14
8UM13
SUM11
24
~
25
31
8UM7
32
V88
~
COENB
:r=~ ::
87
RESET
.. i:: iii£Ni
:F
:F
:F
DINS
DIN7
DIN8
DIN5
DIN4
DIN3
: r= :::
28
SUMS
~
87
58
55
b
~
Q
DINO
CIENB
CINS
54:J Vee
3-132
elENa
DINO
a
a
a
a
a
a
a
a
a
SUM4
SUMl
SUMS
SUM2
SUMO
Yee
CIN1
C ..7
a a a
DINa
78 77 78 715
73:J COUT7
8UM20
8UM8
a
a
a
a
a
a
a
a
a
CIN2
O~OQOO
Vas
SUMa
SUMS
a
a
a
a a a
a a a
DiENi
aee a
a a a a a a
Y
SUMa
Vss
COUT9 COUT4
COUTS COUTe
SUMn
8UM7
a a
13
SUM1.
v••
9UM17 SUM1.
84 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
SUMa3
BUN1S
11
a a a
a a a
CIN8
Vas
SEN'"
VCC
CIN5
CIN3
CINS
CIN4
VCC
Vaa
HSP43891
Pinouts (Continued)
100 LEAD MQFP
TOP VIEW
80
711
78
77
76
75
74
73
72
71
70
611
68
67
66
65
64
63
62
61
60
511
58
57
55
55
54
53
52
51
DCM1
SUM24
Vas
Vas
SUM23
SUM22
Vee
Vee
SUM21
SUM20
SUM111
SUM18
Vas
Vas
SUM17
SUM16
Vee
Vee
SUM15
SUM14
SUM13
SUM12
Vas
SUM11
SUM10
SUMS!
SUM8
SUM7
NC
SUMS
3-133
COUT4
COUTS
Vee
Vee
COUT6
COUT7
Vas
Vas
COUT8
COERB
Vee
Vee
rAm
RESET
biENB
DlN8
DlN7
DlN6
DlN5
DlN4
DlN3
DlN2
DlN1
DlNO
elENB
CIN8
Vee
CIN7
ClN6
Vas
~
W
~
u:::
Q
....
HSP43891
Pin Description
SYMBOL
PIN
NUMBER
VCC
B1,J1,A3,
K4,l7,A10,
F10, D11
VSS
A1, F1, E2,
K3,K6,l9,
A11,E11,
H11
TYPE
NAME AND FUNCTION
+5 power supply input
Power supply ground input.
ClK
G3
I
The ClK input provides the OF system sample clock. The maximum clock frequency is 30M Hz.
01 NO-S
A5-S,
B5-7
C6,C7
I
These nine inputs are the data sample input bus. Nine-bit data samples are synchronously
loaded through these pins to the X register of each filter cell of the DF simultaneously.
The DiEiiiB signal enables loading, which is synchronous on the rising edge of the clock signal.
The data samples can be either 9-bit two's complement or S-bit unsigned values. For 9-bit
two's complement values, DINS is the sign bit. For S-bit unsigned values, DINS must be
held at logical zero.
DIENB
C5
I
A low on this input enables the data sample Input bus (DINO-S) to all the filter cells. A rising
edge of the ClK signal occurring while i5iEiiTB is low will load the X register of every
filter cell with the 9-bit value present on DINO-S. A high on this input forces all the
bits of the data sample input bus to zero; a rising ClK edge when DIENB is high will load
the X register of every filter cell with all zeros. This signal is latched inside the
device, delaying its effect by one clock internal to the device. Therefore it must be
low during the clock cycle immediately preceding presentation of the desired data
on the DINO-S inputs. Detailed operation is shown in later timing diagrams.
CINO-S
A9,B9-11,
C10,C11,
D10,E9,
I
These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously
loaded into the C register of filter CEllO if a rising edge of ClK occurs while CIENB is low.
The CIENB signal is delayed by one clock as discussed below.
E10
The coefficients can be either 9-bH two's complement or S-bit unsigned values. For 9-bH
two's complement values, CINS is the sign bit. For S-bit unsigned values, CINS must be
held at logical zero.
ALIGN
PIN
C3
Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect
In circuit.
CIENB
B8
I
A low on this input enables the C register of every filter cell and the 0 (decimation) registers
of every filter cell according to the state of the DCMO-1 inputs. A rising edge of the ClK
signal occurring while CIENB is low will load the C register and appropriate D registers with
the coefficient data present at their inputs. This provides the mechanism for shifting
coefficients from cell to cell through the device. A high on this input freezes the contents
of the C register and the D registers, ignoring the ClK signal. This signal is latched and
delayed by one clock internal to the DF. Therefore it must be low during the clock cycle
immediately preceding presentation of the desired coefficient on the CINO-8 inputs.
Detailed operation is shown in later timing diagrams.
COUTO-8
B2,B3,C1,
D1, E1, C2,
D2,F2,E3
0
These nine three-state outputs are used to output the 9-bit coefficients from filter CEll7.
These outputs are enabled by the COENB signal low. These outputs may be tied to the
ClNo-S inputs of the same DF to recirculate to coefficients, or they may be tied to the
CINo-S inputs of another DF to cascade DFs for longer filter lengths.
COENB
A2
I
A low on the COENB input enables the COUTO-S outputs. A high on this input places all these
outputs in their high impedance state.
DCMO-1
l1,G2
I
These two inputs determine the use of the Internal decimation registers as follows:
DCM1
0
DCMO
0
DECIMATION FUNCTION
Decimation registers not used
0
1
One decimation register is used
1
0
Two decimation registers are used
1
1
Three decimation registers are used
HSP43891
Pin Description
(Continued)
PIN
NUMBER
TYPE
NAME AND FUNCTION
DCMO-1
(Cont)
L1,G2
I
The coefficients pass from cell to cell at a rate determined by the number of decimation
registers used. When no decimation registers are used, coefficients move from cell to cell
on each clock. When one decimation register Is used, coefficients move from cell to cell on
every other clock, etc. These Signals are latched and delayed by one clock internal to the
device.
SUMO-25
J2, J5-8,
J10, K2,
K5-11
L2-6, LB,
L10,L11
0
These 26 three-state outputs are used to output the results of the internal filter cell
computations. Individual filter cell results or the result of the shlft-and-add output
stage can be output If an individual filter cell result is to be output, the ADRO-2 signals
select the filter cell result. The SHADD signal determines whether the selected filter cell
result or the output stege adder result is output. The signals SEiiiBH and SEiiiB[ enable
the most significant and least significant bits of the SUMQ-25 result respectively. Both
SENBH andSENBL may be enabled simultaneously if the system has a 26-bit or larger bus.
However individual enables are provided to facilitate use with a 16-bit bus.
SENBH
K1
I
A low on this input enables result bits SUM1 6-25. A high on this input places these bits in
their high impedance state.
SENBL
E11
I
A low on this input enables result bits SUMQ-15. A high on this input places these bits in
their high impedance state.
ADRQ-2
G1,H1,H2
I
These three inputs select the one cell whose accumulator will be read through the output
bus (SUMQ-25) or added to the output stage accumulator. They also determine which
accumulator will be cleared when ERASE is low. These inputs are latched in the OF and
delayed by one clock internal to the device. If ADRO-2 remains at the same address for
more than one clock, the output at SUMO-25 will not change to reflect any subsequent
accumulator updates In the addressed cell. Only the result available during the first clock,
when ADRO-2 selects the cell, will be output. This does not hinder normal operation
since the ADRO-2 lines are changed sequentially. This feature facilitates the interface
with slow memories where the output is required to be fixed for more than one clock.
SHADD
F3
I
The SHADD input controls the activation of the shift and add operation in the output stage.
This signal is latched on chip and delayed by one clock internal to the device. Detailed
explanation is given in the OF Output Stage section.
RESET
A4
I
A low on this input synchronously clears all the internal registers, except the cell accumulators It can be used with ERAsE to also clear all the accumulators Simultaneously. This
signal is latched in the OF and delayed by one clock internal to the device.
ERASE
B4
I
A low on this input synchronously clears the cell accumulator selected by the ADRO-2
signals. If RESET is also low simultaneously, all cell accumulators are cleared.
SYMBOL
3·135
HSP43891
Functional Description
The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each 9-bit coefficient is multiplied by a
9-bit data sample, with the result added to the 26-bit
accumulator contents. The coefficient output of each cell is
cascaded to the coefficient input of the next cell to its right.
DF Filter Cell
A 9-bit coefficient (CINO-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUTO-8. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing
through one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient passes is determined by the state of DCMO and
DCM1. The output signals (COUTO-8) are connected to the
CINO-8 inputs of the next cell to its right. The COENB input
signal enables the COUTO-8 outputs of the right most cell
to the COUTO-8 pins of the device.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note
that CIENB is latched internally. It enables the register for
loading after the next CLK following the onset of CIEN Blow.
Actual loading occurs on the second CLK following the
onset of CIENB low. Therefore CIENB must be low during
the clock cycle Immediately preceding presentation of the
coefficient on the CINO-8 inputs. In most basic FIR
operations, CIENB will be low throughout the process, so
this latching and delay sequence is only important during
the initialization phase. When CIENB is high, the
coefficients are frozen.
adder output is loaded synchronously into both the
accumulator and the TREG.
The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number. The cell select is
decoded from the ADRO-2 signals to generate the TREG
load enable. The cell select is inverted and applied as the
load enable to the TREG. Operation is such that the TREG is
loaded whenever the cell is not selected. Therefore, TREG is
loaded every clock except the clock following cell selection.
The purpose of the TREG is to hold the result of a sum-ofproducts calculation during the clock when the accumulator
is cleared to prepare for the next sum-of-products
calculation. This allows continuous accumulation without
wasting clocks.
The accumulator is loaded with the adder output every
clock unless it is cleared. It is cleared synchronously in two
ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device.
Since ERASE and RESET are latched and delayed one
clock internally, clearing occurs on the second CLK
following the onset of both ERASE and RESET low.
The second accumulator clearing mechanism clears a
single accumulator In a selected cell. The cell select signal,
CELLn, decoded from ADRO-2 and the ERASE signal
enable clearing of the accumulator on the next CLK.
The ERASE and RESET signals clear the DF internal
registers and states as follows:
ERASE
RESET
1
1
No clearing occurs, internal state
remains same.
1
0
RESET only active, all registers except
accumulators are cleared, including
the internal pipeline registers.
0
1
ERASE only active, the accumulator
whose address is given by the ADRO-2
inputs is cleared.
0
0
Both RESET and ERASE active, all
accumulators as well as all other
registers are cleared.
These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly like CIENB.
The output of the C register (CO-8) is one input to 9x9 multiplier.
The other input to the 9x9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DINO-8 discussed above. The
X register is enabled for loading by DIENB. Loading is
synchronous with CLK when DIENB is low. Note that
DIENB is latched internally. It enables the register for
loading after the next CLK following the onset of DIENB low.
Actual loading occurs on the second CLK following the
onset of DIENB low; therefore, DIENB must be low during
the clock cycle immediately preceding presentation of the
data sample on the DINO-8 inputs. In most basic FIR
operations, DIENB will be low throughout the process, so
this latching and delay sequence is only important during
the initialization phase. When DIENB is high, the X register
is loaded with all zeros.
The multiplier is pipelined and is modeled as a multiplier
core followed by two pipeline registers, MREGO and
MREG1 (Figure 1). The multiplier output is sign extended
and input as one operand of the 26-bit adder. The other
adder operand is the output of the 26-bit accumulator. The
CLEARING EFFECT
The DF Output Stage
The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driver stage (Figure 2).
The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer.
This result is stored back in the output buffer. This operation
takes place in one clock period. The eight LSBs of the
output buffer are lost. The filter cell accumulator is selected
by the ADRO-2 inputs.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the output buffer 18 MSBs or all zeros for the adder
input. A low on the SHADD input selects zero. A high on the
SHADD input selects the output buffer MSBs, thus activating the shift-and-add operation. The SHADD signal is
latched and delayed by one clock internally.
3-136
HSP43891
OCM1.0
OCMO.O
RESET.O
CIENB.D
>--------------------,
>------.....----------i---+--------i~--__,
3-STATE BUFFERS
ON CEll 1 ONLY
-------1
CINO-8
1
1
~_ _-J\I
DO-I
RESET.D
>------,
OIENB.O
>-------,
1----
lD ClR
X REG
XO-I
1
1
C
.MUlTI-
DINO-8 ~==~>L~~~================:;::=:::::;)lX
PLIER
~
CORE
PO-11
ClK
LATCHES
RESET.O
OCM1
OCM1.0
DCMO
OCMO.D
iiEsEf
iiiOO
CiEiii
RESET.D
DIENB.O
CIENB.O
ADRO
ADRO.D
ADR1
ADR1.0
AOR2
AOR2.D
ERASE
ERASE.D
ACC.00-25
ClK
EHASE.D
CEllO
AORO
AOR1
AOR2
DECODER
••
•
CEll 1
CEll 1
CEll.
AOUTD-Z5
FIGURE 1.
HSP43891 OF FILTER CELL
3-137
COUTO-I
1
1
1
1
HSP43891
Cell RESULTS
o
1
This does not hinder normal FIR operation since the
ADRO-2 lines are changed sequentially. This feature
facilitates the interface with slow memories where the
output is required to be fixed for more than one clock.
6 7
The SUMO-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUMO-15. A
low on SENBH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously If the external system has a
26-blt or larger bus. If the external system bus Is only 16
bits, the bits can be enabled in two groups of 16 and 10 bits
(sign extended).
DF Arithmetic
Both data samples and coefficients can be represented as
either 8-bit unsigned or 9-blt two's complement numbers.
The 9x9 bit multiplier in each cell expects 9-blt two's
complement operands. The binary format of 8-blt two's
complement Is shown below. Note that If the most significant or sign bit Is held at logical zero, the 9-blt two's
complement multiplier can multiply 8-blt unsigned
operands. Only the upper (positive) half of the two's
complement binary range Is used.
SHADD
ClK
The multiplier output is 18 bits and the accumulator Is 26
bits. The accumulator width determines the maximum
possible number of terms In the sum of products without
overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient
and data values. Then maximum numbers of terms In the
sum products are:
SUMO-2S
FIGURE 2. HSP43891 DFP OUTPUT STAGE
The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the
SUMO-25 bus. The output mux determines whether the cell
accumulator selected by ADRO-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD
input signal. Control is based on the state of the SHADD
during two successive clocks; in other words, the output
mux selection contains memory. If SHADD Is low during a
clock cycle and was low during the previous clock, the
output mux selects the contents of the filter cell accumulator addressed by ADRO-2. Otherwise the output mux
selects the contents of the output buffer.
If the ADRO-2 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first
clock when ADRO-2 selects the cell will be output.
MAX # OF TERMS
NUMBER SYSTEM
8-BIT
9-BIT
Two unsigned vectors
1032
N/A
Two two's complement vectors:
• Two positive vectors
• Negative vectors
• One positive and one negative vector
2080
2047
2064
1032
1024
1028
One unsigned 8 bit vector and one two's
complement vector:
• Postive two's complement vector
• Negative two's complement vector
1036
1028
1032
1028
For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.
3·138
HSP43891
Basic FIR Operation
A simple, 30MHz a-tap filter example serves to illustrate
more clearly the operation of the OF. The sequence table
(fable 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, en, enters the OF on the left and moves from left to right through
the cells. The data sample sequence, Xn, enters the OF from
TABLE 1.
HSP43891 30M Hz, 8-TAP FIR FILTER SEQUENCE
--+~
CLK
0
1
2
3
4
5
6
7
a
9
10
11
12
13
14
15
CELLO
C7 XXO
+CSxXl
+C5 XX2
+C4 XX3
+C3 xX4
+C2 xX5
CELL 1
CELL 2
0
+Cl xX6
+COXX7
C7 XXa
+C6 xX9
+C5 XX 10
+C4 xXl l
+C3 xX12
+C2 x X13
C7 xX 1
+CSxX2
+C5 xX3
+C4 XX4
+C3 xX 5
+C2 xXS
+Cl XX7
+CoxXa
C7 xX9
+CS xX l0
+C5 xX l l
+C4 XX12
+C3 xX 13
+C1 XX14
+CO XX 15
+C2 xX14
+Cl xX15
the top, with each cell receiving the same sample simultaneously. Each cell accumulates the sum of products for one
output point. Eight sums of products are calculated simultaneously, but staggered in time so that a new output is
available every system clock.
0
0
C7 xX 2
+C6 xX3
+C5 xX4
+C4 xX 5
+C3 xX6
+C2 XX7
+Cl xXa
+CoxXg
C7 xX l0
+C6 xX"
+C5 xX12
+C4 XX13
+C3 xX 14
+C2 xX15
IHSP43agli
CELL 3
CELL 4
CELL5
CELL 6
CELL 7
SUM/CLR
0
0
0
-
-
-
-
-
C7 xX3
+C6 xX4
+C5 xX5
+C4 XX6
+C3 xX7
+C2 xX a
+Cl xXg
+CO xX lO
C7 x Xl1
+C6 xX12
+C5 XX13
+C4 XX14
+C3 xX 15
-
-
-
-
-
-
-
-
-
-
C7 xX 4
+C6 xX5
+C5 xXS
+C4 XX7
+C3 xXa
+C2 xX9
+Cl xXl0
+CO x X11
C7 XX12
-
C7 xX 5
+CS xX 6
+C5 XX7
+C4 XXa
+C3 xX9
+C2 xX l0
+C1 xX11
+COXX12
C7 XX13
+C6 xX14
+C5 XX 15
+CS x X13
+C5 xX14
+C4 xX 15
-
-
-
-
-
C7 xX S
+C6 xX7
+C5 XXa
+C4 xX9
+C3 xX l0
+C2 xXl1
+C1 XX 12
+CO XX 13
+C7 XX14
+CS xX 15
-
-
-
C7 xX7
+C6 xXa
+C5 xX9
+C4 xX 10
+C3 xX l l
+C2 xX 12
+Cl x X13
+COxX14
C7 xX 15
CeIlO(Y7)
Cell 1 (Ya)
Cell 2 (yg)
Cell 3 (y10)
Cell 4 (Y11)
CeIl5(Y12)
CeliS (Y13)
Cell 7 (Y14)
CeliO (y15)
SAMPLE
DATA IN
(X.)
30MHz
CLOCK
>--1-
3 BIT
COUNTER
Y2
+5V
Yo
Yl
J
I
I .~
i
1
1
""
ADR2 AORl ADRO VCC SHADD SENBH SENBl
l...f..!.
r
OINO-8
26
SUM
OUT
(Y.)
SUMO-25
-f-
COUTO-8
-r- NC
OIENB
ClK
HSP43981
A2
Al
AO
00-08
9x8 COEFF.
RAM/ROM
~
9
CINO-8
CIENB OCMl OCMO RESET
T
I I
SYSTEM
RESET
ERASE
FIGURE 3.
T
I
ERAsE VSS
I
COENB
T
""
HSP43891 30M Hz, 8-TAP FIR FILTER APPLICATION SCHEMATIC
3-139
rn
a::
w
!:i
~
o
.,..
HSP43891
Detailed operation of the DF to perform a basic 8-tap, 9-bit
coefficient, 9-bit data, 30MHz FIR filter Is best understood
by observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Agures 1 and 2).
Therefore the delay from presentation of data and
coefficients at the DINO-8 and CINO-8 Inputs to a sum
appearing at the SUMQ-25 output is: k + Td, where k = filter
length and Td = 4, the internal pipeline delay of the DF.
0123456789
After the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
The output sums, Yn, shown in the timing diagram are
derived from the sum-of-products equation:
Y(n) = C(O) x X(n) + C(l) x X(n-1) + C(2) x X(n-2) + C(3)
x X(n-3) + C(4) x X(n-4) + C(5) x X(n-5) + C(6) x X(n-6)
+ C(7) x X(n-7)
10 11
12 13 14
15 16
17 J8
19
20
ClK
DINO-8
iifftii :z;mI
CINO-8
CiiNi ~
ADRO-2
1011121314151617101
SUMO-25
I~I~I~I~I~I~I~I~I
SHADD ~~$h01
iffiL~$MWhl
SENiii :0'/d/4007hW~~
DCMO-l
1 1-1-------------------------------0
FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING
SAMPLE
DATA IN
IX.1
~
C
30MHz
ClOC K
iii
I
I I I +jV-Fl n
ADR1 ADRI URI Vee IHADO IINIH .E....
~
r
r--"' 'r-
CLK
Y8
4 BIT Yl
CTR. yz
'.1.
-
AI
-A3
IYlTEM T
REBET
' - - - CLI
DO-D'
~I
ADRl ADRI ADO Vee IHADD liNIN IENII.
~
If
iiiiiii
HSP43891
DINO"'I
IUMI-II
HSP43891
DFO
rt
DF1
COUTO-I
CIN ....
CiEiii
~ 21
iiiiii
' - - eLI
COEFF.
.,RAM/ROM
Al
Y3
IU.I-2I
DIN....
I I I +t-fl h
DCMl DC. .
iiiii iiiiii v•• Ciiii
I .6. ~
,
COIffll-1
C'Nt-1
Ciiii DCM'
y
1
DCM.
iiiiii' iiiiiE VI. Cciiii
1
Y 1 1 J
I
I
-40'
~I+ Ne
SUM
OUT
(Y.)
FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC
3-140
HSP43891
Extended FIR Filter Length
Cascade Configuration
Filter lengths greater that eight taps can be created by
either cascading together multiple OF devices or "reusing"
a single device. Using multiple devices, an FIR filter of over
1000 taps can be constructed to operate at a 30MHz
sample rate. Using a single device clocked at 30MHz, an
FIR filter of over 500 taps can be constructed to operate at
less than a 30MHz sample rate. Combinations of these two
techniques are also possible.
To design a filter length l>8, L/8 OFs are cascaded by
connecting the COUTO-8 outputs of the (i)th OF to the
CINO-8 inputs of the (i+1)th OF. The OINO-8 inputs and
SUMO-25 outputs of all the OFs are also tied together. A
specific example of two cascaded OFs illustrates the
technique (Figure 5). Timing (Figure 6) is similar to the
simple 8-tap FIR, except the ERASE and SENBL/SENBH
signals must be enabled independently for the two OFs in
order to clear the correct accumulators and enable the
SUMO-25 output signals at the proper times.
DATA SEQUENCE
TABLE 2.
INPUT
X30 ... X9,X8,X22 .. ,X1'XO
COEFFICIENT SEQUENCE
It
INPUT
Co ,,,C14,C15,O ... O,Co .. · C14,C15 ----IHSP43891r---. ... O,Y30'" Y23'O ... O,Y22'" Y15,O '"
!
CLK
CELLO
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR
6
7
8
9
10
11
12
13
14
15
C15 x Xo
+C14 xX 1
+C13 xX 2
+C12 xX3
0
0
0
0
0
0
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
+C11 XX4
+C10 xX5
+C9 xX6
+C8 xX7
+C7 XX8
+C6 xX9
+C5 XX10
+C4 XX11
+C3 xX 12
+C2 x X13
+C1 XX14
+Co xX 15
0
0
0
0
0
0
0
C15 x Xa
+C14 xX9
+C13 x X10
+C12 XX11
+C11 xX12
+C10 xX 13
+C9 xX14
+C8 xX 15
+C7 x X16
+C6 xX 17
+C5 XX 18
+C4 xX 19
+C3 xX20
+C2 xX21
+C1 xX22
+CO xX 23
0
0
0
0
C15 XX 1
C15 xX 2
C15 XX3
+C14 XX4
+C13 xX5
+C12 xX6
+C11 xX7
+C10 XX8
+C9 xX9
+C8 xX 10
+C7 XX11
+C6 xX 12
+C5 XX13
+C4 xX14
+C3 xX 15
+C2 xX 16
+C1 xX17
+CO xX18
0
0
0
C15 XX4
C15 xX 5
-
-
C15 xX6
-
C15 xX7
+C14 XX6
+C13 xX9
+C12 xX 10
+C11 XX11
+C10 xX 12
+C9 xX 13
+C8 xX14
+C7 xX15
CO xX 16
+C6 xX 16
0
COxX17
+C5 xX17
0
0
+C4 XX18
0
0
COXX19
+C3 xX 19
0
0
0
+C2 xX 20
CO xX 20
0
0
0
0
COxX21 +C1 xX21
0
0
0
0
0
0
+COxX22
0
0
0
0
0
0
0
0
0
0
0
0
0
+C15 XX9
0
0
0
0
0
+C15 xX 10
0
0
0
0
+C15 xX 11
0
0
0
+C15 XX12
0
0
+C15 XX 12
0
+C15 XX14
C15 xX 15
+C14 XX16
+C13 xX 17
+C12 xX 18
+C11 xX19
+ClO xX 20
+C9 xX21
+C8 xX22
+C7 xX 23
+C6 xX24
CO XX 23
0
+C5 xX25
CO xX 25
0
0
+C4x X26
CO xX26
0
0
0
COxX27
+C3 xX27
3-141
-
-
-
CeIl0(y15)
Cell 1(y16)
CeIl2(Y17)
Cell3(Y18)
CeIl4(Y19)
Cell5(Y20)
Cell6(Y21)
CeIl7(Y22)
-
Ce1l0(y23)
Cell 1(Y24)
CeIl2(Y25)
Cell3(Y26)
CeIl4(Y27)
0
HSP43891
812345
&
18
"01112131415181718'9202122232425262728213031323334353837383940
eLK
DFO~IILJ======================================;:==============~============~=========
DF1 ERASE _
I Xo I x, I X21 X3 I X4 I X, I lei X71 x. I Xgl X,DI X111 X121 X131 X'41 X151 X'II X17IX18IX'1 IX20IX21 IX22IX23IX24IX25IX21IX27IX28IX2lIX30IX31 I 321 331 341 351 381 371
oom--oL__________________________________________________________________________
__
X
DINO-.
X
X
X
X
X
CINO..
le'51 e" IC13I C12I C11I C,oIC. lea' t71 e,1 C5 I c.. 1C3 I C2 I e,l Co IC'5IC14 IC13IC'2ICl1 IC,ol cIlt, It7 Ic. Its I c. I C3 IC2 I C, I CoIC'5IC'4IC'3IC'2IC11IC,ol
ADRO-!
1'1'12131'1'1'171'1'12131'1'1'171'1'121_1
CiINi--oL____________________________________________________________________________
DfO SUMO-25
Dft SUMO-!5
DFO
DFt
SEHiDii
SHADD
ifriiIiii
DeMD-!
=====================~;;;;;;~~~~~~~~5;;;;
I' 1-1-------------------------------c",---------------------------------------
,- ,
FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s
Single DF Configuration
Using a single DF, a filter of length L>8 can be constructed
by processing in Ll8 passes, as illustrated in Table 2, for
a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles
and computes eight output samples. In pass i, the sample
with indices i*8 to i*8 +(L-1) enter the DINO-8 inputs. The
coefficients Co - CL - 1 enter the CINO-8 inputs, followed
by seven zeros. As these zeros are entered, the result
samples are output and the accumulators reset. Initial filing
of the pipeline is not shown in this sequence table. Filter
outputs can be put through a FIFO to even out the sample
rate.
bine these partial products by shifting and adding to obtain
the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF's
shift-and-add mechanism contained in its output stage (at
reduced speed).
Decimation/Resampling
Extended Coefficient and
Data Sample Word Size
The HSP43891 DF provides a mechanism for decimating
by factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate-by-twofilter illustrates the technique (internal cell pipelining ignored for simplicity).
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique Is to compute partial products of 9x9 and com-
Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (i.e., decimate-by-two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires
only a single HSP43891 DF.
3-142
HSP43891
TABLE 3. HSP4389116-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT
DATA
SEQUENCE
INPUT
COEFFICIENT
SEQUENCE
INPUT
... C15. CO.'" C13. C14. C15
CLK
CELLO
CELL 1
CELL2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR
6
7
8
C15 XXO
+C14 XXl
+C13 xX2
+C12 XX3
+C11 xX4
+C1Q XX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
10
11
12
13
+CgxX6
+C8 xX7
+C7 xX8
+C6 xX9
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+Cl xX14
+Co xX15
+Cl0 x X7
+C9 xX8
+C8 xX 9
+C7 XX10
+C6 xXll
+C5 XX12
+C4 XX13
+C3 xX 14
C15 xX4
+C14 xX 5
+C13 xX6
+C5 XX26
+C4 xX 27
33
34
+C3 xX 28
+C2 xX 29
+Cl xX30
+Co xX31
35
36
37
o
1
2
3
..
+C7 xX 26
+C6 xX27
+C5 xX 28
+C4 XX 29
+C3 XX30
+C2 xX31
5
8
7
•
0
C15 XX 6
+C14 XX7
+C13 xX8
+C12 xX 9
+C12 XX7
+C11 xX8
0
C15 xX8
0
+Cl0 xX 9
+C14 xX 9
+C9 xX 1Q +C11 xX1Q +C13 x Xl0 C15 xX l0
+C8 xXl l +Cl0 XX l l +C12 xX l l +C14 xX ll
+C7 XX12 +C9 xX 12 +Cll XX12 +C13 xX12
+C6 xX 13 +C8 XX 13 +Cl0 x X13 +C12 XX13
+C5 xX 14 +C7 xX14 +C9 x X14 +Cll xX14
+C4 XX15 +C6 xX 15 +C8 xX 15 +Cl0 XX15
+C3 xX 16 +C5 XX16 +C7 xX16 +C9 xX 16
+C2 XX 15
C15 XX 16 +Cl xX16
+C14 xX 17 +COXX17 +C2 xX 17
+C13 xX18 C15 XX 18 +Cl XX18
+C12 xX19 +C14 xX 19 +CO xX 19
+Cl1 XX20 +C13 x X20 C15 XX 20
+Cl0 x X21 +C12 xX 21 +C14 XX21
+C9 xX22 +Cll xX22 +C13 xX22
+C8 xX23 +C1Q xX 23 +C12 xX 23
+C7 xX24 +C9 xX 24 +Cl1 XX24
+C6 xX 25 +C8 xX25 +C1Q xX 25
32
ClK
+C11 xX6
+C5 xX l0
+C4 x Xll
+C3 xX 12
+C2 xX 13
17
C15 XX 2
+C14 XX3
+C13 XX4
+C12 xX5
+C4 XX 17
+C3 xX 18
+C2 xX 19
+Cl xX20
+CoxX21
C15 XX 22 +Cl XX22
+C14 XX 23 +CO xX 23
+C13 XX24 +C15 XX24
+C12 XX25 +C14 XX25
+C9 xX 26 +Cl1 xX26
+C8 XX27 +C1Q XX27
+C7 xX 28 +CgxX28
+C6 xX 29 +C8 xX 29
+C5 XX30 +C7 XX30
+C4 XX31 +C6 xX 31
I
101112
+C6 xX17
+C5 XX 18
+C4 XX 19
+C3 xX20
+C2 xX21
1314
15
1.
+C13 xX 26
+C12 XX27
+Cl1 xX28
+C1QxX29
+C9 XX30
+C8 xX31
171.
11 20
Z1
-
-
-
0
C15 XX 12
0
+C14 XX13
+C13 xX 14 C15 xX 14
+C12 XX15 +C14 xX 15
+Cl1 xX16 +C13 xX 16
+C8 xX17 +Cl0 xX17
+C7 XX 18 +C9 XX18
+C6 xX 19 +C8 xX19
+C5 XX 20 +C7 XX20
+C4 XX21 +C6 xX21
+C3 xX 22 +C5 XX22
+C2 xX 23 +C4 xX 23
+Cl xX24 +C3 xX24
+Co xX 25 +C2 XX 25
+C15 xX 26 +Cl XX26
+C14 XX27 +COXX27
+C13 xX28 +C15 xX 28
+C12 xX29 +C14 XX 29
+Cl1 xX30 +C13 XX30
+Cl0 xX31 +C12 XX31
22
-
23242521
21
CeIl2(Y19)
CeIl3(Y21)
CeIl4(y23)
CeIl5(y25)
-
+C3 xX26
+C2 XX27
+Cl xX28
CeIl6(y27)
CeIl7(Y29)
+CoxX29
C15 x X30
+C14 XX31
33
34
Q
,..
Cell 1(Y17)
+C7 XX22
+C6 xX23
+C5 xX24
+C4 XX25
32
~
ii:
-
CeIl0(Y15)
+C12 xX17
+Cl1 XX18
+Cl0 xX 19
+C9 xX20
+C8 xX21
28 293031
~
ILl
-
CeIl8(Y31)
35
3.
37
3.
39
40
~----------------------------------------,
I"" I X, I X, IX, I I X, I X, IX, I I IX" Ix,,1 x,,1 x,,1 x,,1 x,,1 x161 x,,1 X" IX" Ix,,1 Ix"lx,,1 x,,1 x"lx"lx"lx"lx" Ix,,1 x,,1 '"Ix" Ix"lx"lx"lx,,1
.,...--.L-____________________________________________________________________________
_
CI.O-'
Ic,,1 c" Ic,,1 c,,1 c,,1 c"l c, Ic, Ic, I c, I c, I c, I c, I c, I c, I Co Ic,,1 c" Ic,,1 c,,1 c,,1 c,,1 c, I c, I c, I c, I c, I c, I c, I c,l c, I Col c,,1 c" Ic,,1 c,,1 c"lc" I
mINi--.L-____________________________
o
I ,
I , I • I , I
I , I
DI.'-'
X.
x~
"a "a
~-----------------------------------------------
ADRO-2
I
,
I
2
I
,
0
Iv,. I Iv,,1 Iv,,1 Iv~1 Iv,,1 Iv,,1 Iv,,1 Iv,,1 Iv,,1 Iv,,1
SHADD ___________________________________________________________________
SIENBL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
SUMO-25
SENIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
DCOO-'
I, f-I- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _
FIGURE 7. HSP4389116-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT
3-143
Specifications HSP43891
Absolute Maximum Ratings
Supply Voltage ••.•.•••...••••...•••.••••.•.•.•.••.•.•••.•••••••..•.•••.••••••••..•.••.•.•.••.•.••.•....•...•... +B.OV
Input, Output Voltage ••..•.•••....•.•.••.•..•.•...••.•.••••...•.....•••...••••.•••...•.•.•....• GND -O.SV to V CC +O.SV
Storage Temperature .•....................••............•..•................••...•.••.•••..•.••••••.. -6So C to +lS00C
ESD ..•.••••.•..•...•.•.•....•....•.•.........•.•.•.•....•....•....•.•...•••..•...•••.••.•..•••.•.....•••••.• Class 1
Maximum Package Power Dissipation at 700 C ...•...••.•.•.••...•••...••••..•••••• 1.7W (MQFP), 2.4W (PLCC), 2.BBW (PGA)
9jc ••...••••••••.•.•••••....••••.•...••••••..•••....••••••.•..•••.•..•••..•...••••.• 11.1 0 C/W (PLCC), 7.7BoC/W(PGA)
9ja .•.••.•••••.........•..•...•......•...••........•......•........ 470 C/W (MQFP), 33.7OC/W (PLCC), 34.66 0 C/W (PGA)
Gate Count ..••••.•....•.••..•...•...••.•••.•..•........•••....•..•..•••........••••.•.•.•••••••••••••••.•...•. 17763
Junction Temperature •••••...•.•..•..•••.•••.•..•.•......•.••...••.••...•.........•.•.••••. lS0 0 C (PLCC), 17So C (PGA)
Lead Temperature (Soldering lOs) ...........•.•.••.......••.••...•...•..•....•......••.•.•.••.•••••••.•••...••.. 3000C
CAUTION: Stresses above those listed in the 'IAbso/ute Maximum Ratings ll may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ...••••.•.••••......•••••••.••••.....••..•.••.•.•.•.••••..•.••••.•.•..••.•••.••..••••• SV ±S%
Operating Temperature Range ............••....•......•••.•.••...••••....•...•...•..••.•...••.•.......... OoC to + 700 C
D.C. Electrical Specifications
SYMBOL
PARAMETER
ICCOp
Power Supply Current
ICCSB
Standby Power Supply Current
MIN
MAX
UNITS
-
140
mA
VCC = Max
CLK Frequency 20MHz
Note 1, Note 3
TEST CONDITIONS
-
500
I1A
VCC = Max, Note 3
II
Input Leakage Current
-10
10
"A
VCC = Max,lnput = OV or VCC
10
Output Leakage Current
-10
10
I1A
VCC = Max,lnput= OVorVCC
VIH
Logical One Input Voltage
2.0
-
V
VCC=Max
VIL
Logical Zero Input Voltage
0.8
V
VCC=Min
VOH
Logical One Output Voltage
2.6
-
V
10H = -400I1A, VCC = Min
VOL
Logical Zero Output Voltage
-
0.4
V
10L = 2mA, VCC = Min
VIHC
Clock Input High
3.0
-
V
VCC= Max
VILC
Clock Input Low
0.8
V
VCc=Min
CIN
Input Capacitance
PLCC
PGA
-
10
15
pF
pF
Output Capacnance
PLCC
PGA
10
15
pF
pF
CLK Frequency 1 MHz
All measurements referenced
toGND
TA=2S0 C. Note 2
COUT
-
NOTES: 1. Operating supply current is proportional to frequency. Typical
rating is 7mA/MHz.
2. Controlled via design or process parameters and not directly
tested. Characterized upon initial design and after major process
and/or design changes.
3. Output load per test load circuit and CL
= 40pF.
3-144
Specifications HSP43891
A.C. Electrical Specifications
vcc
= 5V ± 5%, TA = COC to +7000
-20 (20MHz)
SYMBOL
PARAMETER
MAX
MIN
MAX
MIN
MAX
UNITS
-
39
33
0
-
0
-
ns
14
-
-
18
ns
15
ns
Clock Period
50
TCl
Clock low
20
TCH
Clock High
20
TIS
Input Setup
16
TIH
Input Hold
0
ClK to Coefficient
Output Delay
TOED
Output Enable Delay
TODD
Output Disable Delay
TODS
ClKtoSUM
Output Delay
-30 (30MHz)
MIN
TCp
TODC
-25 (25.6MHz)
-
16
16
-
24
-
20
-
20
15
27
-
-
20
15
25
TOR
Output Rise
-
6
-
6
TOF
Output Fall
-
6
-
6
13
13
13
TEST
CONDITIONS
ns
ns
ns
ns
-
15
ns
21
n8
-
6
n8
Note 1
6
n8
Note 1
Note 1
NOTE: 1. Controlled by design or process parameters and not directly
tested. Characterized upon initial design and after major process
and/or design changes.
Test Load Circuit
r--------------I
1
I
I
I
1
I
:
I
I
I
1.5V
I
I
*INCWDES STRAY AND
JIG CAPACITANCE
1_ _ _ _
1
IOL
EQUIVALENT~IRCUrr _ _ _ _
Swftch S1 Open for ICCSB and ICCOp Tests
3-145
I
I
I
J
HSP43891
Waveforms
CIJ(
_______
TI_"j _
h:;'-TCL~
ax~¥OV
3.0V - - - - - - - -
~
INPUT*
O.OV ________-J
y.2.-OV--'"''--.
MV
• Input includes: DINO-7, CINO-7, DIENB, CIENB, ERASE, RESET,
DCMO-1, ADRO-1, TCS, TCCI, SHADD
INPUT SETUP AND HOLD
CLOCK AC PARAMETERS
o.~~E 4\
TOR=::4T-t--::)-+'\;.~F
OUTPIIT
SUMO-25, COUTO-B, OUTPUT DELAYS
ENABLE
1.5V
TOED
OUTPUT
1.5V
RISE AND FALL TIMES
1.5V
~.7V______________~~TODD
1.3V
AC. Testing: Inputs are driven at 3.0V for a logic "1" and O.OV for a logic
"0". Input and output timing measurements are made at1.SV for both a logic
"1 " and "0". ClK is driven at 4.oV and OV and measured at 2.0V.
A.C. TESTING INPUT, OUTPUT WAVEFORM
OUTPUT ENABLE, DISABLE TIMING
3·146
HSP43891/883
HARRIS
SEMICONDUCTOR
Digital Filter
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL·STD·
883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HSP43891/883 is a video-speed Digital Filter (OF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells cascaded
internally and a shift and add output stage, all in a single
integrated circuit. Each filter cell contains a 9 x 9 two's com·
plement multiplier, three decimation registers and a 26·bit
accumulator. The output stage contains an additional 26-bit
accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right by
8-bits. The HSP43891/883 has a maximum sample rate of
25.6MHz. The effective muttiply-accumulate (mac) rate is
204MHz.
• OMHz to 25.6MHz Sample Rate
• Eight Filter Cells
• 9-Bit Coefficients and Signal Data
• Low Power CMOS Operation
• Iccse = 500~A Maximum
• Iccop = 160~A Maximum at 20MHz
• 26·Bit Accumulator per Stage
• Filter Lengths Up to 1032 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1·0 and 2·0 FIR Filters
•
•
•
•
•
•
Radar/Sonar
Digital Video
Adaptive Filters
Echo Cancellation
Complex Multiply·Add
Sample Rate Converters
Each OF filter cell contains three re-sampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial correlations/convolutions for image processing applications.
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
The HSP43891/883 OF can be configured to process
expanded coefficient and word sizes. Multiple OFs can be
cascaded for larger filter lengths without degrading the sample rate or a single OF can process larger filter lengths at
less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or 9-bit two's complement arithmetic, independently selectable for coefficients
and signal data.
PACKAGE
HSP43891 GM-20/883
-55°C to +125°C
85 Lead PGA
HSP43891 GM-25/883
-55°C
to +125°C
85 Lead PGA
Block Diagram
DINO -DINS
CINO -8
COUTO-S
RESET
ClK~~~-+~--~-+~----~+=~--~-+~----~+=~--~-+~--~~~~--~
ADRO-2
REm
ClK
SHADD
ADRO, ADR1, ADR2
2
>------------------------------+1
~>----~----------------------+L~r._-J
SEmiii
2
CAUTION: These devices are sens~ive 10 electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-147
File Number
2451.3
8!w
!:i
u:::
.Q
HSP43891/883
Pinouts
85 PIN GRID ARRAY (PGA)
7
6
•
10
11
DIN6
DIN3
DINO
CINS
Vee
Vss
DINa
DINl
OlN2
CIENB
CIN7
CIN6
CIN4
DIENB
DINS
DIN4-
CINS
CIN3
CIN2
Vee
CINl
CINa
SENBl
SUMO
Vee
SUMl
SUM3
8UM2
SUMS
SUM4
SUM7
Vas
8UMB
1
2
3
•
5
A
VSS
COENS
Vee
RESET
DIN7
B
Vee
COUT7
COUTa
ERASE
e
COUTS
COUTS
D
COUT3
COUT4
E
COUTl
Vss
COUT2
ALIGN
PIN
6
HSP43891/883
l
F
Vss
COUTO
SHADD
G
ADR2
DeMO
elK
H
ADRl
ADRO
J
Vee
SUM25
K
SENBH
8UM24
Vss
l
oeMl
SUM23
0
DCM1
K
0
0
H
0
ADR1
G
0
ADR2
F
0
VSS
E
o
PlNSOOWl'l
SUM17
SUM16
Vee
SUM19
Vss
SUM15
SUM12
SUM10
SUMB
SUM22
8UM21
SUM18
SUM14
Vee
SUM13
Vss
SUM11
SUMQ
2
3
4
5
6
10
11
0
0
0
0
0
0
0
0
0
VSS
VCC
SUM23 SUM22 8UM21
0
7
0
SUM'S SUM'.
SUM'9
0
0
SUM20
SUM25
VSS
VCC
S
0
SUM'3
0
0
0
VSS
0
SUM'5 SUM'2 SUM'O
0
0
0
0
0
COUTO
0
0
COUT!
Vss
0
0
0
0
COUTS COUTS
B
0
VCC
A
0
Vss
0
0
SUM5
0
0
CLK
0
HSP438911883
BOTTOM VIEW
SHADD
0
SUM1
0
SUMO
PINS UP
0
COUT2
CIN'
0
0
SUM3
0
VCC
0
CINO
0
CIN2
0
0
DIENB
ALIGN
PIN
0
COUT7 COUTS
COENB
0
SUMS
SUM7
ADRO
DCMO
0
SUM1'
0
SUM'7 SUM'6
COUT3 COUT4
C
Vss
SUM20
SENBH 8UM24
VCC
TOP VlEW.
0
VCC
0
ERASE
0
RESET
0
DIN8
0
DIN7
0
DIN5
0
DIN'
0
DINS
3-148
0
DIN4
0
DIN2
0
DIN3
0
CIENB
0
DINO
0
0
SUM9
0
SUM6
0
VSS
0
SUM4
0
SUM2
0
VSS
0
SENBl
0
VCC
0
0
CINS
CIN3
0
0
CIN7
CINS
0
0
0
VCC
Vss
CINS
CIN4
Specifications HSP43891/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage •.•....•....•.........•.•..•.••••..•...• +8.0V
Input, Output Voltage Applied •••.••••.. GND-0.5V to VCC+0.5V
Storage Temperature Range •••••••••.••••••• -650C to +150 0C
Junction Temperature •••••••••••.•••••••••••.•.•••••• +175 0 C
Lead Temperature (Soldering, Ten Seconds) .••.•...••.. +3000 C
ESD Classification ..•••••..•••••••.•••.•.•.•••••••.••• Class 1
Thermal Resistance
9ja
9jc
Ceramic PGA Package •••••••••••.. 34.660 C/W 7.78 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package •••.•.•••••••••••••••••••••. 1.44 Walt
Gate Count •••••••••••••••••••••..•••••••••••••• 17762 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operatlonal sections of this specification ;s not implied.
Operating Conditions
Operating Voltage Range ••••••••••••••••••..••• +4.5V to +5.5V
Operating Temperature Range ••••••••••••••. -SsoC to +12So C
TABLE 1. HSP43891/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
GROUPA
SUBGROUPS
LIMITS
TEMPERATURE
:5 TA:5 +12SoC
MIN
MAX
UNITS
2.2
-
V
Logical One Input
Voltage
VIH
VCC=5.5V
1,2,3
-S50C
Logical Zero Input
Voltage
VIL
VCC=4.SV
1,2,3
-5S0C :5 TA :5 +12SoC
-
0.8
V
Output HIG H Voltage
VOH
10H =-4OOIlA
VCC = 4.SV (Note 1)
1,2,3
-5S0C:5 TA:5. +1250 C
2.6
-
V
Output LOW Voltage
VOL
IOL=+2.0mA
VCC = 4.SV (Note 1)
1,2,3
-S50C :5TA:5. +12SoC
-
0.4
V
Input Leakage Current
II
VIN = VCC or GND
VCC=S.SV
1,2,3
-55°C :5TA:5 +1250 C
-10
+10
flA
Output Leakage Current
10
VOUT = VCC or GND
VCC=S.SV
1,2,3
-5S0 C :5 TA :5. +12SoC
-10
+10
"A
V
Clock Input High
VIHC
VCC=S.5V
1,2,3
-S50 C .+125 0 C
Clock High
TCH
Note 1
9,10, 11
-550C .+125 0 C
20
Input Setup
TIS
Note 1
9,10,11
-550C.:::; TA ~ +125 0 C
Input Hold
TIH
Note 1
9,10,11
ClK to Coefficient
Output Delay
TODC
Note 1
Output Enable Delay
TOED
Note 1
ClKtoSUM
Output Delay
TODS
Note 1
-25 (25.6MHz)
TEMPERATURE
20
-
17
-550C.:$ TA :$ + 125°C
0
-
0
-
9,10, 11
-550C !>.TA !>.+125 0 C
-
24
-
20
ns
9,10, 11
-550 C:S.,TA:S...+1250C
-
15
ns
9,10,11
-
20
-55°C !>.TA!>. +125 0 C
25
ns
31
ns
NOTE: 1. A.C. Testing: VCC = 4.SV and S.SV. Inputs are driven at 3.0V for a
Logic "1" and O.OV for a Logic "0", Input and output timing measurements are made at 1.5V for both a logic "1" and "0". elK is driven at
4.0V and OV and measured at 2.0V.
TABLE 3. HSP43891/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
-20 (20MHz)
PARAMETER
Input Capacitance
-25 (25.6MHz)
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
CIN
VCC=Open, f=l MHz
All measurements
are referenced to
device GND.
1
TA=+250C
-
15
-
15
pF
1
TA=+250C
-
15
-
15
pF
15
ns
6
ns
6
ns
Output Capacitance
COUT
Output Disable Delay
TODD
1,2
-55 0 C.:::;TA.:$+1250C
1,2
-550C!>. TA :$ +125 0 C
-
20
TOR
7
-
TOF
1,2
-55°C!>. TA!>. +125 0 C
-
7
-
Output Rise Time
Output Fall Time
NOTES: 1. The parameters listed in Table 3 are controlled via design or
process parameters and are not directly tested. These
parameters are characterized upon initial design and after major
process andlor design changes.
2. Loading is as specified in the test load circuit, Cl
= 40pF.
TABLE 4. APPLICABLE SUBGROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2,3, 8A, 88, 10, 11
-
1,2,3, 7,8A, 88, 9, 10, 11
Samples/5005
1,7,9
CONFORMANCE GROUPS
Group A
GroupsC&D
3-150
HSP43891/883
Burn-In Circuit
I.
8
0
DCM1
0
0
K
0
SENBH 8U"'24
0
Vee
0
0
Vss
0
0
0
Vss
0
SUM11
0
0
SUMa
SUM1S SUU12 SUM1D
0
0
0
SUU20 BUN17 SUM10
SUM7
0
0
0
0eLK
0
0
HSP43891/883
BOnOMVIEW
COUlD SHADD
0
0
Vss
0
0
D
0
SUU1D
0
SUM1S
SUM5
DeMo
COUT1
E
Vee
0
Vee
0
0
0
0
0
ADRO
ADR2
Vss
0
Vss
0
SUM18 SUM14
0
ADR1
G
0
SUM25
0
H
0
SUM23 SUM22 8UM21
0
0
COUTS
B
0
0
Vee
A
0
COUT8
0
CIN1
0
0
0
0
ALIGN
DIENS
PIN
0
0
eOENS
elNO
CIN2
COUT7 COU18
0
Vss
0
Vee
0
COU12
COUT3 COU14
e
0
SUMS
SUMO
PINS UP
0
SUMl
Vee
0
0
ERASE
0
0
DIN4
0
DINl
DIN8
0
RESET
0
DIN5
0
DIN7
DIN8
0
0
0lN2
0
DINS
GIENB
0
DINa
11
0
SUM.
0
SUMe
0
Vss
0
SUM4
0
9UM2
0Vss
0
SENBl
0
vee
0
0
CINS
CINS
0
0
CIN7
CIN8
0
0
0
Vee
Vss
CIN8
0
ClN4
~
w
!:i
u::
...
Q
PGA
PIN
A1
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
Vss
eOENB
GND
e1
eOUT5
Vee/2
F10
Vee
Vee
K4
Vee
Vee
A2
F10
e2
eOUT6
Vce/2
F11
GND
K5
SUM19
Vec/2
A3
Vee
Vee
C3
ALIGN
NC
G1
VSS
ADR2
F2
K6
VSS
GND
A4
RESET
F11
e5
DIENB
F10
G2
DeMO
F5
K7
SUM15
Vee/2
A5
DIN7
F8
e6
DIN5
F5
G3
eLK
FO
K8
SUM12
Vce/2
AS
DIN6
F6
e7
DIN4
F4
G9
SUM1
Vee/2
K9
SUM10
Vce/2
A7
DIN3
F3
e10
elN5
F5
G10
SUM3
Vec/2
K10
SUM8
Vce/2
AS
DINO
FO
e11
elN3
F3
G11
SUM2
Vee/2
K11
SUM6
Vec/2
AS
elN8ITCCI F8
01
eOUT3
Vec/2
H1
ADR1
F1
L1
DeM1
F6
A10
Vee
Vce
02
eOUT4
Vee/2
H2
ADRO
FO
L2
SUM23
Vee/2
A11
VSS
GND
0,0
CIN2
F2
H10
SUM5
Vee/2
L3
SUM22
Vee/2
B1
Vee
Vce
0,1
Vee
Vec
SUM4
Vee/2
L4
SUM21
Vee/2
B2
eOUT7
Vee/2
E1
eOUT1
Vce/2
H"
J1
Vee
Vee
L5
SUM'8
Vee/2
B3
eOUT8/
Teeo
Vee/2
E2
VSS
GND
J2
SUM25
Vce/2
L6
SUM'4
Vee/2
E3
eOUT2
J5
SUM20
Vee/2
L7
Vee
Vee
84
ERASE
F10
E9
CIN1
Vee/2
F1
J6
SUM17
Vee/2
La
SUM13
Vee/2
B5
DIN8ITes
F7
E10
CINO
FO
J7
SUM16
Vec/2
L9
B6
DIN1
E11
SENBL
F'O
J10
SUM7
Vee/2
L10
Vss
SUM11
Vee/2
F1
VSS
GND
J11
VSS
GND
L11
SUM9
Vee/2
F2
CUTO
Vee/2
K1
SENBH
F10
B7
DIN2
F'
F2
B8
elENB
F'O
B9
elN7
F7
F3
SHADD
F9
K2
SUM24
Vee/2
B'O
elN6
F6
F9
SUMO
Vee/2
K3
VSS
GND
B11
elN4
F4
NOTES: 1. Vee/2 (2.7V ±10%) used for outputs only.
2. 47K!l (±20%) resistor connected to all pins except
Vee and GND.
3. Vee a 5.5 ±0.5V.
GND
4. 0.1~F (min) capacitor between Vee and GND per position.
5. FO = 100KHz ±10%, F1
FO/2, F2 = F1I2 ••••. , F11 - F1012,
40% - 60% Duty Cycle.
6. Input voltage limits: VIL = O.BV max., VIH = 4.5V ±10%
=
3-151
HSP43891/883
Metallization Topology
DIE DIMENSIONS:
328 x 283 x 19 ±1 mils
METALLIZATION:
Type: Si - AI or Si-AI-Cu
Thickness: 8kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY:
1.2 x 10 5A/cm 2
Metallization Mask Layout
HSP43891/883
SUM23
COUT6
SUM22
coun
Vee
Vss
SUM21
COUT8
SUM20
COENS
SUM19
Vee
SUM18
ERASE
Vss
RESET
DIENB
SUM17
DiNS
SUMiS
DINT
Vee
DIN6
SUM15
DINS
SUM14
OlN4
SUM13
DIN3
SUM12
OlN2
DIN1
Vss
DINO
SUM11
elENB
SUM10
CINS
SUM9
SUMS
SElECT 891
SUM7
""::>
"
M
?l
"
i::>
o
?l
" "
o
Z
(j
z
(j
"Z
o
M
Z
(j
~ ~ ~i ~
"
3-152
.
z
(j
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(j
4
VIDEO PROCESSING
PAGE
VIDEO PROCESSING DATA SHEETS
Digital Video Mixer .................................................... .
4·3
HSP48410
Histogrammer/Accumulating Buffer ......................................... .
4·12
HSP4841 0/883
Hlstogrammer/Accumulating Buffer . ..................................... .
4·23
HSP48901
3 x 3 Image Filter ...................................................... .
4·31
HSP48908
Two Dimensional Convolver .............................................. .
4·40
HSP48908/883
Two Dimensional Convolver .............................................. .
4·57
HSP9501
Programmable Data Buffer ............................................... .
4·64
HSP48212
CJ
Z
OU;
w0
OW
-0
>0
a:
D.
NOTE: Bold Type Designates a New Product Irom Harris.
4·1
HSP48212
Digital Video Mixer
January 1994
Features
Description
• 12-6it Pixel Data
The Harris HSP48212 is a 68 pin Digital Video Mixer IC
intended for use in multimedia and medical imaging applications.
• Two's Complement or Unsigned Data
• 12-61t Mix Factor
• 13-61t Signed or Unsigned Three State Output
• Overflow Detection and Output Saturation
• Rounding to 8, 10, 12, or 13-61ts
• Input and Output Pixel Data Synchronous to Clock
• Programmable Pipeline Delay of up to 7 Clock Cycles
for Control of Misaligned Input Data
• TTL Compatible Inputs/Outputs
• DC to 40MHz Clock Rate
Applications
The HSP48212 allows the user to mix two video sources
based on a programmable weighting factor. After weighting
the input data Signals, the Video Mixer simply adds the two
weighted signals mathematically. This results in the mixed
output, which is a weighted sum of the two sources.
The input and output interfaces are synchronous with respect
to the input clock. simplifying the user interface requirements.
Input Data (DINA, DINB), Mix Factor (M) and control signals
(RND, TCB) may be delayed relative to each other in order to
compensate for any misalignment that may have occurred
prior to entering the HSP48212. Each input'S delay may be
independently programmed up to seven clock cycles.
The output data may be rounded to 8, 10, 12, or 13-bits. The
enabling of data onto the output data bus is under the user's
control via an output enable signal (OE#).
• Video Summing (Frame Addition)
• Video Mixing
• Fade In/Out
Ordering Information
• Video Switching
• High Speed Multiplying
PART NUMBER
TEMPERATURE
RANGE
PACKAGE TYPE
HSP48212VC-4D
DOC to +7DoC
64 LeadMQFP
HSP48212JC-4D
DOC to +7DoC
68 Lead PLCC
rlL..._. . .
M
DOUTO-12
DINAO-11-f-+~(Xl"""--'
12~
DOUT = 2 x [DINA x M + DlNB x (1-M))
CAUTION: These d8llices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994
4-3
Z
a:
c..
Block Diagram
DINBo-11
"
OUi
wen
OW
-(,)
>0
File Number
3627
HSP48212
Pinouts
64 LEAD MQFP
TOP VIEW
DlNB11
DlNB10
DlNB.
DlNB8
DlNB7
DlNBS
QND
DINB5
DlNB4
DINB3
DlNB2
DlNB1
DINBO
OEI
43
42
41
40
39
38
RND1
RNDO
DELAY
DOUT12
DOUT11
DOUT10
DOUT9
QND
DOUT9
DOUT7
DOUT6
DOUT5
Vee
DOUT4
DOUT3
DOUTZ
DOUT1
DOUTO
68 PIN PLCC
TOP VIEW
DlNB11
DlNB10
DlNBS
DINB8
DlNB7
DINB6
QND
DINB5
NIC
DINB4
DlNB3
DlNB2
DINB1
DlNBO
RND1
RNDO
DELAY
10
11
12
13
14
15
16
17
18
1S
•
OEI
DOUT12
DOUT11
DOUT10
DOUT9
GND
DOUTB
DOUT7
Nle
DOUT6
DOUT5
Vee
DOUT4
DOUT3
DOUTZ
DOUT1
DOUTO
20
21
22
23
24
25
26
4-4
HSP48212
Pin Description
NAME
PLCCPIN
TYPE
DESCRIPTION
ClK
9
I
Clock input. All signal pins are synchronous with respect to this clock except lD#, DEL,
OE#, and BYPASS.
DINAO-ll
29-31
33-34
36-38
I
Input data bus. Provides data to the Mixer from one video source. Synchronous to the
rising edge of elK.
40-43
DINBO-ll
10-15, 17
19-23
I
Input data bus. Provides data to the Mixer from one video source. Synchronous to the
rising edge of elK.
Mo.ll
62-65
67-68
2-7
I
Mix input bus. The range of M Is from 0 to 1. The number format Is unsigned, with one
bit position to the left of the binary point. If a value greater than 1 is placed on this bus,
the Internal circuitry will saturate M to I, I.e anytime the MSB Is I, the internal value
defaults to 1.00000000000. Synchronous to the riSing edge of elK.
TC#
28
I
Specifies the number format of the input data busses DINA and DINB. 1 = unsigned,
0= 2's complement. The signal has the same number of latency stages as the incoming data. Therefore, the number format affects the incoming data but not the data in
the internal pipeline stages. Synchronous to the rising edge of elK.
RNDo.l
24-25
I
Specifies the number of significant bits on the output bus. 00 = 8-bit, 01 = 10-bit,
10 = 12-bit, 11 = 13-bit. Rounding is performed by adding a binary 1 to the bit pOSition
to the right of the desired LSB. The remaining bits are forced to zero. These control
signals have the same number of latency stages as the incoming data. Therefore, the
output round format does not take effect until the current data has propagated to the
output. Synchronous to the rising edge of ClK.
MIXEN
8
I
Mix enable. This pin is used to disable the clock signal which samples the Mix input.
When MIXEN = l,the MO-ll bus is sampled by the rising edge of elK. When MIXEN
= 0, the MO-ll bus is ignored and the previously stored value of Mo.ll is used. Synchronous to the rising edge of elK.
lD#
27
I
Asynchronous load pin. lD# is used to load the delay control registers. The delay control word is loaded serially from lSB to MSB. This signal drives the clock input to a
15-bit serial shift register. Each lD# cycle, the data is transferred through the register
bank on the rising edge of lD# In order to load the delay control word, the user must
supply exactly 15 lD# pulses.
DEL
26
I
Delay input. This is the serial input data that is sampled by the rising edge of lOll. It is
the inputlo the first stage olthe 15-bit serial shift register which contains the delay control word. Synchronous to the rising edge of lDII.
BYPASS
61
I
Allows user to disable (bypass) the LOll interface and use the default delay paths.
When BYPASS = I, the delay control word is forced to all O·s and no extra delays are
included in the paths. When BYPASS = 0, the delay control word must be initialized
using the lD#/DEl interface in order for the chip to give predictable results. This pin is
.asynchronous and is not intended to change states dunng operation.
DOUTO-12
59-56
54-53
51-50
0
Output data bus. The data on this bus reflects the results of the equation:
2x[AxM + Bx(I-M)). The number format of the output IS either 2's complement or unsigned depending on the value of the Tell signal during data Input. The representation
of DOUT is also dependent on the value sampled on RNDO-l during data input.
(See RNDO-l & TC# pin description)
48-44
OEII
60
I
Output enable. Asynchronous input which takes effect immediately following a transition.
When OEII = 0 the DOUr bus is driving, when OE# = 1 the DOUT bus is not driven (floating).
Vcc
32,49,66
I
5V power supply. There are 3 Vcc pads.
GND
16,39,55
I
OV power supply. There are 3 GND pads.
4-5
C!J
z
00
Wei)
QW
-(,,)
>0
II:
D.
HSP48212
Functional Block Diagram
DlNBo.11
Mo.11
DlNAo.11
t---..
PROGRAMMABLE
DELAY
(zoN)
PROGRAMMABLE
DELAY
(Z0N)
M
BYPASS
DEL
LD#
PROGRAMMABLE
DELAY CONTROL
REGISTER
TCI
RNDO-1
PROGRAMMABLE
DELAY
(Z0N)
PROGRAMMABLE
DELAY
(zoN)
DOUTo.12
FIGURE 10 FUNCTIONAL BLOCK DIAGRAM
4·6
HSP48212
MD-ll supplies the weighting (Mix) factor and has 12-bHs of
precision. MD-ll must be represented in unsigned format and
may range from 0 to 1. If a value greater than 1 is placed on the
bus, the internal circuitry will saturate MD-l1 to 1.00000000000.
Functional Description
The Digital Video Mixer is intended for use in professional
video. multimedia and medical imaging applications. The
HSP48212 allows the user to mix two video sources based
on a programmable weighting factor. After weighting the
input data signals. the Video Mixer simply adds the two
weighted signals mathematically. This results in the mixed
output. which is a weighted sum of the two sources. The fundamental equation implemented by this architecture is:
Eq. (1) DOUT
DINAO-l1, DINBO-ll, and MO-l1 are synchronously registered on the rising edge of elK.
The signal MIXEN allows the user to disable the internal
clock signal which samples the MD-ll input bus. When
MIXEN
O. the MO-ll bus is ignored and the previously
sampled Mo-l1 value is used. When MIXEN 1. the MD-ll
bus is sampled on the rising edge of elK.
=
=2 x [DINA x M + DINB x (l-M)]
where DINA and DINB are the two video sources (pixels)
and M is the weighting (Mix) factor. As expressed by this
equation. the output DOUT is a weighted average of the
incoming pixels. For instance. when M is set to 0 the DINB
input source is passed to the output. and when M is set to 1
the DINA input is passed to the output. and when M is set to
0.5 the output is the sum of the two sources DINA and DINB.
The user can therefore vary the mix factor to apply different
weights to each of the inputs DINA. DINB. This allows functions such as fading in. fading out. fading between images.
graphics overlays. and keying. The multiplication factor of 2
as seen in Eq. (1) is accomplished through a 1-bit shift left
(See Figure 1). This shifter is not programmable and cannot
be accessed by the user.
Programmable Delay
The input data (DINAO-ll. DINBO-ll). mix factor (MO-ll).
and control signals (RNDO-l. TC#). may be delayed relative
to each other in order to compensate for any misalignment
that may have occurred prior to entering the HSP48212.
Each input's delay may be independently programmed for up
to seven delays. In other words. the user can program a different number of pipeline delays for each input. This programmed delay is in addition to the inherent 6 stage delay
required by the architecture.
As shown in Figures 2 and 3. the programmable delay information is loaded using the signals lD# and DEL. lD# is the
asynchronous load pin used to clock in the delay control
word. The delay control word is clocked into a 15-bit serial
shift register on the rising edge of lD# (i.e. DEL is synchronous to lD#). The delay control word data is supplied by the
DEL signal beginning with the least significant bit and continuing until the most significant bit has been clocked in. On
each lD# cycle the DEL data input is transferred through the
register bank. The user must supply exactly 15 lD# pulses;
if the shift register is clocked more than 15 times. only the
most recent 15 data inputs will be stored.
The functional block diagram is shown in Figure 1. It can be
seen that Eq. (1) is directly implemented by this architecture.
The arcMecture has a 6 stage inherent latency. This architecture is extremely flexible in that Rallows the user to account for
misaligned input data by independently programming up to
seven additional delay stages for DINAO-ll. DINBD-l1. and
MO-ll. as well as for the format control signals Te# and
RNDD-l. The programmable delay registers are controlled by
the signals DEL. lD#. and BYPASS.
The HSP48212 input interface is primarily synchronous to the
rising edge of elK wHh the exception of the programmable
delay control signals DEL. lD#. and BYPASS. The output
data bus DOUTD-12 is registered synchronous to the rising
edge of elK and may also be controlled via the asynchronous
output enable signal OE#. The input data. DINAO-ll and
DINBO-ll. as well as the mix factor MD-l1 have 12-bit precision. The output data DOUTD-12 has 13-bit precision to allow
for l-bit of growth.
As previously stated. the length of the control word is 15-bits: 3bits are allocated for each of the 5 inputs. DINAD-ll. DINBD-l1.
MO-l1. RNDD-l. and TC#. Each 3-bits of the control word allow
the user to specify from 0 to 7 additional delay stages by programming the binary equivalent of the desired delay into the
appropriate bit position of the delay control word register (e.g.
OOD for 0 delays. 001 for 1 delay..... 111 for 7 delays).
TABLE 1. DELAY CONTROL WORD
The signals Te# and RNOO-l control the format of the input
and output data. Te# allows DINAO-l1 and DINB 0-11 to be
eHher two's complement or unsigned (Note: DINAO-ll and
DINBO-ll must have the same format. i.e. no mixed mode).
The output data DOUTD-12 can be rounded to 8. 10. 12. or
13-bits as determined by the control signals RNDD-l.
Input Data Format
DINAO-11 and DINBO-ll represent two digital video sources
(pixels). Each input bus has 12-bits of precision. They may
be represented in two's complement form (Te# 0) or in
unsigned form (Te#
1). It is important to note that DINAO11 and DINBO-ll must be represented in the same format
(I.e. No mixed mode operation is allowed).
=
=
=
INPUT SIGNAL
CONTROL WORD BIT POSITION
RNDO-l
12-14
TC#
9-11
MO-ll
6-By
DINBO-lt
3-5
DINAo-l1
0-2
The BYPASS control signal enables the programmable delay
registers to be bypassed. When BYPASS is high. the delay
control word is forced to all O's and no additional delays are
included in any of the input paths. However. when BYPASS
is low. the lD#/DEl serial delay control word interface is
active and the delay control word must be initialized in order
to achieve any meaningful results.
4·7
"
Z
ou;
w0
QW
-(,)
>0
II:
0.
HSP48212
the new configuration will effect the current input data and
will not effect the data in the pipeline stages. For example, if
the rounding selection is changed from 8-bit rounding to 10bit rounding on a given cycle, the output will remain in an 8bit representation while the new data is propagating through
the circuit. When the results of the new data are available at
the output, the number format will change to 10-bits.
DEL _ _-I
LDI_-4-1
The RNDQ-1 control signals determine the number of significant bits on the output bus DOUTO-12. The output data may
be rounded to 8.10.12, or 13-bits.The rounding operation is
performed by adding a binary 1 to the bit position right of the
desired lSB and forcing the undesired bits to O. For example, in 8-bit rounding, a 1 is added to the 9th bit to the right of
the MSB (DOUT4). and DOUTO-4 are forced to 0 (i.e.
DOUTO-12 XXXXXXXXOOOOO).
D6
=
Output Control
03
DOUTQ-12 is the output data bus which represents the
weighted average of the incoming pixel data as indicated by
Eq. (2):
Eq. (2) DOUT
DO
=2 x [(DINA x M) +(DINB x (1-M))]
The output data will be represented in either two's complement format or in unsigned format depending on the value of
the Te# Signal when the input data (DINAO-11 and DINBO11) is sampled by elK. Similarly, the output representation
of DOUTO-12 is also dependent on the value of RNDO-1 during sampling of the input data.
FIGURE 2. DELAY CONTROL WORD SHIFT REGISTER
Format Control Signals
The control signals Te# and RNDO-1 are used to specify the
input data representation and the output data representation
respectively. Te# and RNDQ-1 are synchronous 10 elK,
which allows them to be changed on a cycle by cycle basis if
needed. The conlrol signals are designed to match the
latency of the data paths. When the control inputs change,
The output data DOUTQ-12 is registered at the output of the
HSP48212 on the rising edge of elK. The output data may
be accessed through the activation of the signal OE#. OE# is
an asynchronous input whiCh, when low, causes the
DOUTO-12 bus to drive; when OE# is high, the DOUTQ-12
bus is not driven (floating).
LO.
DEL
I
DO
I 01 I D2
I
03
I 04 I D5
I
D6
I 07 I 08 ! D9 I 010 I 011
!
012
I 013 I 014 !
DINA
DINB
MIX
TCI
RND
DELAY
DELAY
DELAY
DELAY
DELAY
FIGURE 3. DELAY CONTROL WORD TIMING DIAGRAM
4-8
Specifications HSP48212
Absolute Maximum Ratings
Supply Voltage .••.•••..•..•...•.....•..•..........• +8.0V
Input, Output or VO Voltage •.••••••.•.•• GND-o.5V to Vcc+O.5V
Storage Temperature Range ••..•.•.•••...... ·65°C to + 150°C
Junction Temperature .............................. + 150°C
Lead Temperature (Soldering 1Os) ...••..•••.•....•..• +300oC
ESD Classification ................................ Class 1
e
Thermal ReSistance
JA
PLCC Package ...... .. .. .. .. .. .. ..
43°CIW
MQFP Package................. ...
51°CIW
Maximum Package Power Dissipation at +70oC
PlCC Package .................................. 1.86W
MQFP Package .................................. 1.57W
Gate Count •................................. 6,000 Gates
CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
01 the device at these or any other conditions abo... those indicated in the operational sections 01 this specilication is not implied.
Operating Conditions
Operating Voltage Range, Commercial .......•....•.. +5V ± 5%
Operating Temperature Range, Commercial ...•...• O"C to +70oC
DC Electrical Specifications
PARAMETER
SYMBOL
Icoop
Power Supply Current
Iccse
Standby Power Supply Current
TEST CONDITIONS
MIN
MAX
UNITS
·
170
mA
Vee = Max, CLK Frequency 40Mhz,
Note 2, Note 3
500
IJA
Vcc = Max, Outputs Not Loaded
II
Input leakage Current
·10
10
itA
Vcc = Max,lnput = OV or Vcc
10
Output Leakage Current
·10
10
itA
Vcc = Max,lnput = OV or Vcc
V IH
Logical One Input Voltage
2.0
.
V
Vcc= Max
V IL
Logical Zero Input Voltage
·
0.8
V
Vee = Min
CJ
z
00
wtn
QW
-(,)
VOH
logical One Output Voltage
2.6
VOL
Logical Zero Output Voltage
·
V IHC
Clock Input High
VllC
Clock Input Low
C IN
C OUT
>0
V
10H = ·400ItA, Vee = Min
V
10l = 2mA, Vcc = Min
V
Vee = Max
0.8
V
Vee = Min
Inpul CapaCitance
10
pF
Output Capacitance
10
pF
CLK Frequency 1MHz, All Measurements
Referenced to GND.
TA = +25°C, Note 1
0.4
3.0
a:
D.
NOTES:
1. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
changes.
2. Power Supply current is proportional to operating frequency. Typical rating for Icoop is 4.25mAlMHz.
3. Output load per test load circuit and CL = 40pF.
AC Electrical Specifications
40MHz
PARAMETER
SYMBOL
MIN
MAX
UNITS
.
ns
Tcp
CLKPeriod
25
TCH
CLKHigh
10
TCl
CLKLow
10
TlP
LD# Period
25
4·9
n5
n5
.
ns
Specifications HSP48212
AC Electrical Specifications
40MHz
SYMBOL
MIN
PARAMETER
MAX
UNITS
TLH
LO# High
10
ns
TLL
lD#low
10
ns
Tos
Data Setup Time to ClK High
10
ns
TOH
Data Hold Time from ClK High
0
ns
TMS
MIX Data Setup Time to ClK High
10
ns
TMH
MIX Data Hold Time From ClK High
0
ns
Tcs
Control Data Setup Time to ClK High
10
ns
TCH
Control Data Hold Time From CLK High
0
ns
TOLS
DEL Setup to lD# High
12
ns
TOLH
DEL Hold from lD# High
0
ns
TOUT
ClK to Output Data Delay
13
ns
TOE
Output Enable Time
13
ns
Too
Output Disable Time
13
ns, Note 2
TRF
Output Rise/Fall Time
5
ns. Note 2
NOTES:
1. AC tests performed with CL= 40pF,IoL = 2mA, and 10H = -400j1A. Input reference level ClK = 2.0V. Input reference level for all other inputs
is 1.5V. Test VIH = 3.0V, VIHC = 4.0V, VIL = OV, VILC = OV.
2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
Design changes.
AC Test Load Circuit
,,-_ .............. _.. _.. -- _........ -_ .............. -.,,
,,
,,
,,,
,
:
~
OUT
SI
~
*TEST HEAD L
CAPACITANCE
.
.
:.
:
.
J
.j. IOH
-
- 1.5V
-
t
-
IOL
~
.
SWITCH SI OPEN FOR
J:
Iccsa AND Iccop
,,______________________________
EQUIVALENT CIRCUIT
4·10
HSP48212
Waveforms
SYNCHRONOUS TIMING
ASYNCHRONOUS TIMING
TLP
Tep
TLH
TCH
Tel
n-
,...-..,
ClK
---J
Tos
TIlH
DEL
DINA
'V
)1\
DlNB
Tcs
OUTPUT ENABLE, DISABLE TIMING
TCH
V
TCt
DE'
RND
TMS
MIXEN
TMH
DDUT·------------~Q
,
HIGH
IMPEDANCE
1.7V
1.3V
HIGH
IMPEDANCE
"
Z
MIX
00
w0
QW
-(,J
TOUT
DOUT
OUTPUT RISE AND FAll TIMES
,
)
4-11
>0
g:
HSP48410
HARRIS
SEMICONDUCTOR
HistogrammerlAccumulating Buffer
January 1994
Features
Description
10-Blt Pixel Data
The Harris HSP48410 is an 84 lead Histogrammer IC
intended for use in image and signal analysis. The on-board
memory is configured as 1024 x 24 array. This translates to a
pixel resolution of 10-bits and an image size of 4k x 4k with no
possibility of overflow.
• 4k x 4k Frame Sizes
• Asynchronous Rash Clear Pin
• Single Cycle Memory Clear
In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in
Histogram Equalization applications. Other capabilities of the
HSP48410 include: Bin Accumulation, Look Up Table, 24-bit
Delay memory, and Delay and Subtract mode.
• Fully Asynchronous 16 or 24-Blt Host Interface
• Generates
Function
and
Stores
Cumulative
Distribution
• Look Up Table Mode
A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.
• 1024 x 24-Blt Delay Memory
• 24-Blt Three State VO Bus
The HSP48410 includes a fully asynchronous interface which
provides a means for communications with a host, such as a
microprocessor. The interface includes dedicated Read/Write
pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data.
• DC to 40MHz Clock Rate
Applications
• Histogrammlng
• Histogram Equalization
• Image and Signal Analysis
Ordering Information
• Image Enhancement
PART NUMBER
• RGB Video Delay Line
TEMPERATURE
RANGE
PACKAGE
HSP48410JC-33
OOC to +70oC
84 Lead PLCC
HSP48410JC-40
OOC to +70oC
84 Lead PLCC
HSP48410GC-33
OOC to +70oC
84 Lead PGA
HSP48410GC-40
OOC to +70oC
84 Lead PGA
Block Diagram
24
,
24
,
HISTOGRAM
-----t
DIN0-23
PINO-9
IOADDO-9
24
,
10
,
10,
~
10,
MEMORY
ARRAY
DATA
IN
DATA
OUT
~
ADDER
~
010
INTERACE
0100-23
ADDRESS
ADDRESS
GENERATOR
CAUTION: These devices are sens~ive to electrostatic discharge. Users should follow proper I.C. Handling Procadures.
Copyright © Harris Corporation 1994
4-12
File Number
3185.1
HSP48410
Pinouts
84 PIN GRID ARRAY
84 PIN GRID ARRAY
TOP VIEW
BOTTOM VIEW
11
DINa
DlN10 DlN11 DlN13 DlN1. DlN17 DlN11 DlN22 Dl023 Dl022 Dl011
10
DING
DlN7
I
DlN4
DlNI
8
DlN2
DlN3
7
P1Na
DlND
GND
Pto10 Dl012 DlO11
•
vee
DlN1
ClK
Dl08
Dl08 Dl013
5
P1Na
P1N7
P1N1
Dl08
Dl07 GND
4
P1NG
P1N4
DlO4
Dl06
DlO. Dl04
3
P1N3
P1N1
Dl03 Dl01
2
PIN2
FC,
ROIl
1
P1ND
TART
A
B
DI01
Dl022 Dl023 DlN22 DlN11 OIN17 DIN16 DIN13 DIN11 DIN10
DINa
11
0101
Dl020 01021 DlN23 "IN20 OlN21 DlN1S DlN12 DlNI
DIN7
DINS
10
Dl018 Dl016
DI01
Dl018
DlN6
DlN4
g
Dl016 Dl014
DI01 Dl016
DlN3
DIN2
8
PINg
7
DINa DlN12 DlN16 DlN21 DlN20 DlN23 Dl021 DlO20 Dl017
DlN14 GND
DlN18
DlN18 GND
DlN14
DI011 Dl012 Dl010
GND
DlND
Dl08
Dl08
ClK
DlN1
GND Dl07
Dl08
P1Na
P1N7
P1N8
6
PIN4
PIN6
4
PINl
PIN3
3
0101
vcc
6
FCTO
OADD lOAD
I
8
Dl01
Dl03
FCT2
WR'
10~D[ DlOO
UWS 10~DC lOAD
3
Dl02
Dl02 Dloo
lOAD 10~D[ lOAD
0
6
UWS
WR.
FCT2
ROIl
FCt
PIN2
2
lOll
Fcn
GND
lOAD
5
lOAD 10~D[ 10~D[ 10~D[ vcc
7
vcc lOAD
1
lOAD 10:DI lOAD lOAD
2
5
7
GND
FCT1
lOll STAR
•
PINO
1
C
D
E
F
B
A
G
H
J
K
l
l
K
IO:O[ 10~D[ FCTO
H
J
G
F
PIN'A,'
ID
E
D
C
CJ
z
oUi
wtn
OW
-0
>0
84 LEADPLCC
TOP VIEW
a:
D.
~~~~l~~~~~~§i~~~~i~~~
Innnni
. / 11109 8 7 & 5 4 3 2 1 84 83 82 81 80 71 78
FCt~
ROIl
STARn
F~ ~
Fcn
FCTO
WR,
GND
UWS
10AD08
10ADD8
IOADD7
10AD08
10ADDS
10ADD4
10ADD3
10AD02
IOADD1
10ADDO
vec
12
13
14
16
16
17
18
11
20
21
22
23
24
25
28
27
28
21
i=
30
C
31
32
Inn
n
76 75
•
74
73
72
71
70
b!
b!b!
68
68
67
66
.5
DlN17
e4
GND
DIN18
DlN18
DlN20
OIN21
63
.2
61
60
59
58
57
58
55
54
"~~~~~H~~U~~~«~«~60~H~
O-N~.~~~~~~O_N~.:~~~~
~~~~~~~~~~~~~~~~~~~~~
4-13
DlN8
DINa
DIN10
DlN11
DlN12
DlN13
DlN14
DlN15
DIN1S
8
3
DlN22
DlN23
DI023
~
01022
01021
01020
HSP48410
Pin Description
NAME
PLCCPIN
TYPE
DESCRIPTION
ClK
1
I
Clock input. This input has no effect on the chips functionality when the chip is programmed to an asynchronous mode. All signals denoted as synchronous have their
timing specified with reference to this signal.
PINO-9
3-11,83
I
Pixel Input. This Input bus is sampled by the rising edge of clock. It provides the onchip RAM with address values In Histogram, Bin Accumulate and lUT(write) mode.
During Asynchronous modes it is unused.
lD#
15
I
The load pin is used to load the FCTO-2-bits into the FCT registers. (See belOW).
FCTO-2
16-18
I
These three pins are decoded to determine the mode of operation for the chip. The
signals are sampled by the rising edge of lO# and take effect after the rising edge of
lo#. Since the loading of this function is asynchronous to ClK, it is necessary to disable the STARn pin during loading and enable STARn atleast 1 ClK cycle following
the lO# pulse.
STARn
14
I
This pin informs the on-chip circuHry which clock cycle will start and/or stop the current
mode of operation. Thus, the modes are asynchronously selected (via LOt) but are
synchronously started and stopped. This Input Is sampled by the rising edge of ClK.
The actual function of this Input depends on the mode that is selected. START# must
always be held high (disabled) when changing modes. This will provide a smooth transition from one mode to the next by allowing the part to reconfigure itself before a new
mode begins. When START# is high, LUT(read) mode is enabled except for Delay and
Delay and Subtract modes.
FC#
12
I
Flash Clear. This input provides a fully asynchronous signal which effectively resets
all bits in the RAM Array and the input and output data paths to zero.
01NO-23
58-63,
65-82
I
Data input bus. Provides data to the Histogrammer during Bin Accumulate, lUT, Delay
and Delay and Subtract modes. Synchronous to ClK.
0100-23
33-40,
42-57
110
Asynchronous data bus. Provides RAM access for a microprocessor in preconditioning the memory array and reading the results of the previous operation. Configuarable
as either a 24 or 16-bit bus.
IOAOoO-9
22-31
I
RAM address in asynchronous modes. Sampled on the falling edge of WR# or Ro#.
UWS
21
I
Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of 0100-7 as being the upper eight-bits of the data in or out of the Histogrammer.
A zero means that 0100-15 are the lower 16-bits. In all other modes, this pin has no
effect.
WR#
19
I
Write enable to the RAM for the data on 0100-23 when the HSP48410 is configured
in one of the asynchronous modes. Asynchronous to ClK.
RO#
13
I
Read control for the data on 0100-23 in asynchronous modes. Output enable for
0100-23 in other modes. Asynchronous to ClK.
Vce
2,32
GNo
20,41,64,84
+5V. O.lI1F capacitors between the Vee and GNO pins are recommended.
Ground
NOTES:
1. A # after a pin name denotes an active low signal.
2. Bit 0 is the lSB on all busses.
4-14
HSP48410
Functional Description
010 Interface
The Histogrammer is intended for use in signal and image
processing applications. The on-board RAM is 24-bits by
1024 locations. For histogramming, this translates to an
image size of 4k x 4k with 10-bit data. A functional block
diagram of the part is shown in Figure 1.
The 010 Interface Section transfers data between the
Histogrammer and the outside world. In the synchronous
modes, 010 acts as a synchronous output for the data
currently being processed by the chip; RD# acts as the output enable for the 010 bus; WR# and 10ADDO-S have no
effect. When either of the Asynchronous modes are selected
(16 or 24- bit), the RAM output is passed directly to the 010
bus on read cycles, and on write cycles, data input on 010
goes to the RAM Input port. In this case, data reads and
writes are controlled by RD#, WR# and 10ADDO-S.
In addition to histogramming, the HSP48410 will also
perform Histogram Accumulation while feeding the results
back into the memory array. The on-board RAM will then
contain the Cumulative Distribution Function and can be
used for further operation such as histogram equalization.
Other modes are: Bin Accumulate, look Up Table (lUn,
Delay Memory, and Delay and Subtract. The part can also
be accessed as a 24-bit by 1024 word asynchronous RAM
for preconditioning or reading the results of the histogram.
The Histogrammer can be accessed both synchronously
and asynchronously to the system clock (ClK). It was
designed to be configured asynchronously by a microprocessor, then switched to a synchronous mode to process
data. The result of the processing can then be read out
synchronously, or the part can be switched to one of the
asynchronous modes so the data may be read out by a
microprocessor. All modes are synchronous except for the
Asynchronous 16 and 24 modes.
Function Decode
This section provides the signals needed to configure the
part for the different modes. The eight modes are decoded
from FCTO-2 on the rising edge of lD# (see Table 1). The
output of this section is a set of signals which control the
path of data through the part.
The mode should only be changed while START# is high.
After changing from one mode to another. START# must be
clocked high by the rising edge of ClK at least once.
TABLE 1. FUNCTION DECODE
FCT
A Flash Clear operation allows the user to reset the entire
RAM array and all input and output data paths in a single
cycle.
0
0
0
Histogram
Histogram Memory Array
0
0
1
Histogram Accumulate
0
1
0
Delay and Subtract
0
1
1
Look Up Table
1
0
0
Bin Accumulate
1
0
1
Delay Memory
1
1
0
Asynchronous 24
1
1
1
Asynchronous 16
2
The Histogram Memory Array is a 24-bit by 1024 deep RAM.
Depending on the current mode, its input data comes from
either the synchronous input DINO-23, from the asynchronous data bus 0100-23, or from the output of the adder. The
output data goes to the 010 bus in both synchronous and
asynchronous modes.
Address Generator
This section of the circuit determines the source of the RAM
address. In the synchronous modes, the address is taken
from either the output of the counter or PINO-S. The pixel
input bus is used for Histogram, Bin Accumulate, and
lUT(read) modes. All other synchronous modes, i.e.
Histogram Accumulate, lUT(write), Delay, and Delay and
Subtract use the counter output. The counter is reset on the
first rising edge of ClK after a falling edge on STARn.
During asynchronous modes, the read and write addresses
to the RAM are taken from the 10ADD bus on the falling
edge of the RD# and WR# signals, respectively.
Adder Input
The Adder Input Control section contains muxes, registers
and other logic that provide the proper data to the adder. The
configuration of this section is controlled by the output of the
Function Decode section.
1
MODE
0
Flash Clear
Flash Clear allows the user to clear the entire RAM with a
single pin. When the FC# pin is low. all bits of the RAM and
the data path from the RAM to 0100-23 are set to zero. The
FC# pin is asynchronous with respect to ClK: the reset
begins immediately following a low on this Signal. For
synchronous modes, in order to ensure consistent results.
FC# should only be active while START# is high. For
asynchronous modes. WR# must remain inactive while FC#
is low.
4-15
"
Z
oUi
Wen
QW
-0
>0
II:
a..
HSP48410
Functional Block Diagram
-
IN
DIN 0-23
24X1024
RAM
OUT
ADDRESS
100DD 0-8
PIN0-8
ADDER
INPUT
CONTROl
ADDRESS
GENERATOR
~
~""--r-"""
ClK
WR'
Rot
uws
TO ADDRESS GENERATOR
CONTROL
STARn
Fct
TO OUTPUT STAGE
TO RAM
FCT0-2
MUX
CONTROL
SIGNALS
lot
All REGISTERS ARE CLOCKED BY ClK
FIGURE 1. FUNCTIONAL
BLOCK DIAGRAM
Histogram Mode
This is the fundamental operation for which this chip was
intended. When this mode is selected. the chip configures
itself as shown in the block diagram of Figure 2. The pixel
data is sampled on the rising edge of clock and used as the
read address to the RAM array. The data contained in that
address (or bin) is then incremented by 1 and written back
into the RAM at the same address.
At the same time. the new value is also displayed on the 010
bus. This procedure continues until the circuit is interrupted
by START# returning high. When STARn is high. the RAM
write is disabled. the read address is taken from the Pixel
Input bus. and the chip acts as if it is in LUT(read) mode. Figure 3 shows histogram mode timing. STARn is used to disregard the data on PINO-9 at DATA2. STARn is sampled on
the rising edge of clock. but is delayed internally by 3 cycles
to match the latency of the Address Generator. Data is
clocked onto the 010 bus on the riSing edge of elK. RD#
acts as output enable.
elK
STMD~~
PIN M
0100-23
(RI»LOW)
___
DATA 0
-J~~
DATA 1
_ _ _ _ _ _ _ __
DATA 2 DATA 3
DATA 4 DATA 5
~OUTO
OUT 1 OUT 2
ORIGINAL BIN CONTENTS
ME NOT UPDATED
FIGURE 2. HISTOGRAM MODE
BLOCK DIAGRAM
FIGURE 3. HISTOGRAM MODE TIMING
4-16
HSP48410
Histogram Accumulate Mode
This function is very similar to the Histogram function. In this
case, a counter is used to provide the address data to the
RAM. The RAM is sequentially accessed, and the data from
each bin is added to the data from the previous bins. This
accumulation of data continues until the function is halted.
The results of the accumulation are displayed on the 010
bus while simultaneously being written back to the RAM.
When the operation Is complete, the RAM will contain the
Cumulative Distribution Function (COF) of the image.
Figure 4 shows the configuration for this mode. Once this
function is selected, the STARn pin is used to reset the
counter and enable writing to the RAM. Write enable is
delayed 3 cycles to match the delay in the Address Generator. The START# pin determines when the accumulation will
begin. Before this pin is activated, the counter will be in an
unknown state and the 010 bus will contain unpredictable
data. Once the START# pin is sampled low, the data
registers are reset in order to clear the accumulation. The
output (010 bus) will then be zero until a non-zero data value
is read from the RAM. Timing for this operation is shown in
Figure 5.
that the counter is not reset at this point. The counter will be
reset on the first cycle of ClK that STARn is detected low.
To prevent invalid data from being written to the RAM, when
the counter reaches its maximum value (1023), further
writing to the RAM is disabled and the counter remains at
this value until the mode is changed.
At the end of the histogram accumulation, the 010 output
bus will contain the last accumulated value. The chip will
remain in this state until STARn becomes inactive. The
results of the accumulation can then be read out synchronously by keeping START# high, or asynchronously in either
of the asynchronous modes.
Bin Accumulate Mode
The functionality of this mode is also similar to the Histogram
function. The only difference is that instead of incrementing
the bin data by 1, the bin data is added to the incoming DIN
bus data. The DIN bus is delayed internally by 3 cycles to
match the latency in the address generator. Figure 6 shows
the block diagram of the internal configuration for this mode,
while the timing is given in Figure 7. Note that in this figure,
STARn is used to disregard the data on DINO-23 during
DATA2.
CJ
z
RAM
oUi
ADDRESS
OW
-eJ
>0
wU)
II:
Q.
ADDRESS
GENERATOR
FIGURE 6. BIN ACCUMULATE BLOCK DIAGRAM
FIGURE 4. HISTOGRAM ACCUMULATE MODE BLOCK
DIAGRAM
ClK
STARTt~
ClK
~
ADDRESS
STARn~
PINo-t
010 0-23
ADD. 0
DATA
(AOIIow)
DIN 0-23
FIGURE 5. HISTOGRAM ACCUMULATE MODE TIMING
DATA 0
AOO.1
AOO.2
AOO.3
ADD. 4
ADD.S
-=:.==-3--
DATA 1
DATA 2
DATA 3
DATA 4
DATAS
OUTPUT
The START# pin must remain low in order to allow the
accumulated data to overwrite the original histogram data
contained in the RAM. When the START# pin returns to a
high state, the configuration remains intact, but writing to the
RAM is disabled and the part is in lUT(read) mode. Note
0100-23
~
(RD.Iow)I------
4-17
ORIGINAL BIN CONTENTS
ARE NOT UPDATED
FIGURE 7. BIN ACCUMULATE TIMING
HSP48410
Look Up Tab/e Mode
J\.f\J\J\J\.f\. J\.f\J\J\J\.f\.
A look Up Table (LUT) is used to perform a fixed transfor- ClK
mation function on pixel values. This is particularly useful
when the transformation is non-linear and cannot be realized START""i"\\,._ _...:.;(W,;.;.R;;,;ITE,;;:>_ _ _ - '
(READ>
________________
__
directly with hardware. An example is the remapping of the
original pixel values to a new set of values based on the COF ~N~~ _ _ _~~~--_
ADDRESS
obtained through Histogram Accumulation.
D~A
PIN~O
The transformation function can be loaded into the lUT in
one of three ways: in lUT mode, through 0INO-23; in either
asynchronous mode, over the 010 bus as described below
under Asynchronous 16/24 Modes; in the Histogram
Accumulate mode the transformation function is calculated
internally (see description above). The transformation
function can then be utilized by deactivating STARn, putting
the part in lUT mode and clocking the data to be
transformed onto the PIN bus. Note that it is necessary to
wait one clock cycle after changing the mode before clocking
data into the part.
OUTPUT
~
DIO~o]2!:3==::J0~0*~0£·:xG:)i:·IG:)a·K _______ W
• PREVIOUS CONTENTS OF SIN lOCATION.
FIGURE 9. LOOK UP TABLE MODE TIMING
De/ay Memory (Row Buffer) Mode
As seen by comparing Figures 8 and 10, the configuration
for this mode is nearly identical to the lUT mode. In this
mode, however, the counter is always providing the address
and the write function is always enabled.
The block diagram and timing for this mode are shown in
Figures 8 and 9. The left half of the timing diagram shows
lUT(write) mode. On the first ClK that detects START# low,
the counter is reset and the write enable is activated for the
RAM. As long as START# remains low, the counter provides
the wr~e address to the RAM and data is sequentially loaded
through the DIN bus. The DIN bus is delayed internally by 3
cycles to match the latency in the Address Generator. The
010 bus will contain the previous contents of the memory
location being updated. When 1024 words have been written
to the RAM, the counter stops and further writes to the RAM
are disabled. The part stays in this state while START#
remains low.
In order to force this configuration to act as a row delay register, the START# signal must be used to reset the internal
counter each time a new row of pixels is being sampled.
Because of the inherent latency in the address and data
paths, the counter must be reset every N-4 cycles, where N
is the desired delay length. For example, if a delay from DIN
to 010 of ten cycles is desired, the START# signal must be
set low every six cycles (see Figure 11). If the internal
address counter reaches its maximum count (1023), it holds
that value and further writes to the RAM are disabled.
When STARn returns high, the RAM write is disabled, the
read address is taken from the PIN bus, and the chip acts as
a synchronous lUT. (This is known as lUT(read) mode.) In
order to ensure that the internal pipelines are clear, data
should not be input to PINO-9 until the third clock after
START# goes high.
FIGURE 10. DELAY MEMORY BLOCK DIAGRAM
DATA
DIN~
DIO~-~-----------'GJr.l~lrDD~[IIIl])
FIGURE 8. LOOK UP TABLE BLOCK DIAGRAM
FIGURE 11. DELAY MEMORY MODE TIMING FOR ROW
LENGTH OF TEN
4-18
HSP48410
De/ay and Subtract Mode
This mode is similar to the Delay Memory mode. except the
input data is subtracted from the corresponding data stored
in RAM (See Figures 12 and 13).
n
r:1_~
~r;I
ROt
The difference between the Async 16 mode and the Async
24 mode is the number of data bits available to the user. In
16-bit mode. the user can connect the system data bus to
the lower 16-bits of the Histogrammer's DIO bus. The UWS
pin becomes the lSB of the 10 address. which determines if
the lower 16-bits or upper 8-bits of the 24-bit Histogrammer
data is being used. When UWS is low. the data present at
DI00-15 is the lower 16-bits of the data in the IOADDO-9
location. When UWS is high. the upper 8-bits of the
IOADD09 location are present on DI00-7. (This is true for
both reading and writing.) Thus it takes 2 cycles for an
asynchronous 24-bit operation when in Async 16 mode.
Unused outputs are zeros.
FIGURE 12. DELAY AND SUBTRACT BLOCK DIAGRAM
ADDRESS
IOAoo 0-9 - - - - < I . ' GENERATOR
CJ
OATA 1
MINUS
OATA7
..J L
z
wen
ou)
MOOlFlEO OATA
OUTPUT
0I00-H ______________________IJJAT1A~~2~DD-3~C!J~4~I~WC-5
WAf
ROt
QW
-(,,)
>0
uws
OATA 2
MINUS
OATAa
FIGURE 14. ASYNCHRONOUS 16124 BLOCK DIAGRAM
FIGURE 13. DELAY AND SUBTRACT MODE TIMING FOR ROW
LENGTH OF TEN
WRITE CYCLE TIMING
Asynchronous 16124 Modes
WAf
In the Asynchronous modes. the chip acts like a single port
RAM. In this mode. the user can read (access) any bin
location on the fly by simply selting the 10-bit10 address to
the desired bin location. The RAM is then read or written on
the following RD# or WR# pulse. A block diagram for this
mode is shown in Figure 14. Note that all registers and
pipeline stages are bypassed; START# and elK have no
effect in this mode.
Timing waveforms for this mode are also shown in Figure 15.
During reading. the read address is latched (internally) on
the falling edge of RD#. During write operations. the address
is latched on the falling edge of WR# and data is latched on
the rising edge of WR#. Note that reading and writing occur
on different ports. so that. in this mode. the write port always
latches its address and data values from the WR# signal.
while the read port always uses RD# for latching.
I
\
ROt
IOAoo0-9,
UWS
c::::x
X
0100-23
I
READ CYCLE TIMING
WRf
ROt
IOADD0-9,
UWS
4-19
DIO 0-23
I
\
c::::x
c:::::x
>
FIGURE 15. ASYNCHRONOUS 16124 MODE TIMING
a:
Co
Specifications HSP48410
Absolute Maximum Ratings
Thermal Information
Supply Voltage ...•..•..•.•..•.••••.•.•.•..•..•..••• +8.0V
Input, OUtput Voltage .•.••.•..•.•.•.••. GND-O.5V to Vcc+O.5V
Storage Temperature Range ..••.•.•...•.•... -65"<: to + 150°C
Junction Temperature ••.••..••.. + 175°C (PGA), + 150°C (PLCC)
Lead Temperature (Soldering lOs) .•.......•.•..•..... +300oC
ESD ClassifICation • • . • . • . • . • . • • . . . . • . . . • • • . • • . . . .. Class 1
Thermal Resistance . . . . . . . . . . . . . . . . . .
9JA
9JC
PGA Package .. . . . . . . . . . . . . . . . . . .. 34.3°CIW 8.0oCIW
PLCC Package............. ....... 23.0oCIW 7.4°CIW
Maximum Package Power Dissipation at +70oC
PGA Package ...•................................ 3.1W
PLCC Package ..................•................ 3.5W
Gate Count ..•..................•............. 3500 Gates
CAUTION: Stresses abo... those listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions abo... those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range .................•...••••• +5V ±5%
Operating Temperature Range .................. OOC to +70oC
DC Electrical Specifications
SYMBOL
MIN
MAX
UNITS
Logical One Input Voltage
V IH
2.0
-
V
Vce
Logical Zero Input Voltage
V il
-
0.8
V
Vcc= 4.75V
PARAMETER
High Level Clock Input
V
Vcc= 5.25V
-
V
Vee
2.6
-
V
0.4
V
3.0
VllC
Output High Voltage
VOH
Output Low Voltage
VOL
Input Leakage Current
Il
-10
10
I1A
110 Leakage Current
10
-10
10
IlA
ICCSB
-
500
IlA
-
396
Operating Power Supply Current
=5.25V
0.8
V IHC
Low Level Clock Input
Standby Supply Current
TEST CONDITIONS
Icoop
=4.75V
10H =-400IlA, Vec = 4.75V
10l =+2.0mA, Vec =4.75V
VIN =Vce or GND, Vec =5.25V
Your =Vee or GND, Vee =5.25V
VIN =Vcc or GND, Vcc =5.25V,
Outputs Open
f =33 MHz, VIN =Vcc or GND
Vcc =5.25V (Note 1,2)
mA
NOTES:
1. Power supply current is proportional to operating frequency. typical rating for Iceop is 12mAlMHz.
2. Maximum junction temperature must be considered when operating part at high clock frequencies.
Capacitance
TA
=+250 C, Not tested, but characterized at initial design and at major process or design changes.
PARAMETER
Input Capacitance
Output CapaCitance
AC Electrical Specifications
SYMBOL
MIN
MAX
UNITS
-
12
pF
12
pF
C IN
Cour
FREQ = 1 MHz, Vec = Open, all
measurements are referenced to
device ground.
vcc = 5V ± 5%, TA = OOC to +70oC (Note 1)
-40 (40 MHz)
-33 (33 MHz)
SYMBOL
MIN
MIN
Clock Period
Tcp
25
Clock Low
TCH
10
Clock High
TCl
10
12
DIN Setup
Tos
12
13
PARAMETER
TEST CONDITIONS
MAX
MAX
ns
30
-
4-20
12
UNITS
-
ns
ns
-
ns
TEST CONDITIONS
Specifications HSP48410
AC Electrical Specifications
PARAMETER
vee = 5V ± 5%, TA = OOC to +700C (Note 1)
(Continued)
-40 (40 MHz)
-33 (33 MHz)
SYMBOL
MIN
MAX
MIN
0
DINO-23 Hold
TOH
0
-
Clock to 0100-23 Valid
Too
-
15
FC# Pulse Width
TFL
35
-
FCTO-2 Setup to LD#
TFs
10
FCTO-2 Hold from LD#
TFH
0
STARn Setup to ClK
Tss
12
START# Hold from ClK
TSH
0
PINQ-9 Setup Time
Tps
12
PINQ-9 Hold Time
TpH
0
lD# Pulse Width
TLL
10
lD# Setup to STARn
10
0
13
0
13
0
12
TLs
Tep
TWL
12
-
15
WR# High
TWH
12
15
Address Setup
TAS
13
Address Hold
TAH
1
010 Setup to WR#
-
Tws
12
TWH
1
RD# low
TAL
35
RD# High
Tcp
TAH
15
RD# low to 010 Valid
TAD
-
35
ReadlWrite Cycle Time
Tcv
55
010 Valid after RD# High
TOH
0
TOE
18
Output Disable Time
Too
Output Rise Time
TA
Output Fall Time
TF
18
6
-
ns
ns
ns
-
6
ns
ns
ns
ns
ns
ns
ns
ns
Note 2
ns
-
ns
ns
CJ
1
ns
OU;
wt/)
OW
15
-(,,)
ns
17
ns
-
43
>0
a:
ns
43
-
z
ns
-
65
Output Enable Time
-
19
TEST CONDITIONS
15
1
-
UNITS
35
WR#low
010 Hold from WR#
MAX
a.
ns
ns
0
ns
Note 3
19
ns
Note 4
19
ns
Note 3
6
ns
From 0.8V to 2.0V, Note 3
6
ns
From 2.0V to a.8V, Note 3
NOTES:
1. AC Testing is performed as follows: Input levels (ClK) O.OV and 4.0V; Input levels (All other inputs) OV and 3.0V. Timing relerence levels
(ClK) = 2.0V, (All others) = 1.5V. Output load circuit with CL = 4OpF. Output transition measured at VOH " 1.5V and VOL"; 1.5V.
2. There must be at least one rising edge of ClK between the rising edge of LD# and the failing edge of START#.
3. Characterized upon initial design and after major changes to design and/or process.
4. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with CL =40pF.
4-21
HSP48410
Test Load Circuit
....... -_ ...... "'---------
:,
----- ... __ .. --_ .....
,,
OUT
:
1.5V
*INCLUDES STRAY AND JIG CAPACITANCE
SWITCH S1 OPEN FOR Iccsa AND Iccop
t
IOL
EQUIVALENT CIRCUIT
Waveforms
FUNCTION LOAD TIMING
SYNCHRONOUS DATA AND CONTROL TIMING
LOt
elK
DING-23
FCTO-2
----~~~~---+
CLK
STARTt
0I()c)'23
SYNCHRONOUS OUTPUT TIMING
ROt
STARTt
DI()C).23
-
WRITE CYCLE TIMING
WA.
ROt
IOADDG-9
,-~,~-~
F
0100.23
WOS
--
~
FWDH
ROt
IOAOI)C).I
FLASH CLEAR TIMING
READ CYCLE TIMING
'-3=R'~'1
( TRD~
DI()C).23
OUTPUT RISE AND FALL TIMES
TFL
Fe.
s=TOD
-d-
2.GV
o.av
4-22
~
C:TRH
HSP48410/883
HistogrammerlAccumulating Buffer
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL-STD883 and Is Fully Conforment Under the Provisions of
Paragraph 1.2.1.
The Harris HSP48410 is an B4 lead Histogrammer IC
intended for use in image and signal analysis. The on board
memory is configured as 1024 x 24 array. This translates to
a pixel resolution of 10-bits and an image size of 4k x 4k with
no possibility of overflow.
• 10-Bit Pixel Data
• 4k x 4k Frame Sizes
In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in Histogram Equalization applications. Other capabilities of the
HSP48410 include: Bin Accumulation, Look Up Table, 24-bit
Delay memory, and Delay and Subtract mode.
• Asynchronous Flash Clear Pin
• Fully Asynchronous 16-Blt or 24-Blt Host Interface
• DC to 33MHz Clock Rate
A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.
Applications
• Histogrammlng
The HSP48410 includes a fully asynchronous interface
which provides a means for communications with a host,
such as a microprocessor. The interface includes dedicated
ReadlWrite pins and an address port which are asynchronous to the system clock. This allows random access of the
Histogram Memory Array for analysis or conditioning of the
stored data.
• Histogram Equalization
• Image and Signal Analysis
Ordering Information
TEMPERATURE
RANGE
PACKAGE
HSP48410GM-331883
-5SOC to +125"C
84 Lead PGA
HSP48410GM-251883
-55°C to +125°C
84 Lead PGA
PART NUMBER
CJ
z
oUi
Wei)
QW
-(.)
>0
a::
Q.
Block Diagram
HISTOGRAM
L-....t
OING-23
PINO-I
~
MEMORY
ARRAY
DATA
IN
DATA
OUT
r-
ADDER
--
0100-23
010
INTERACE
ADDRESS
ADDRESS
GENERATOR
100DDO-I
CAUTION: These devices are senshive to electrostatic discharge. Users should follow proper I.e. Handling Procedures.
Copyright © Harris Corporation 1994
4-23
File Number
3542.1
HSP484101883
Pinouts
84 LEAD PIN GRID ARRAY
TOP VIEW
11
DlN8
DIN10 DIN11 DIN13 DIN16 DIN17 DIN19 DlN22 DI023 DlO22 DI019
10
DINS
DlN7
DIN4
DIN6
8
DIN2
DIN3
7
PINS!
DINO
aND
DI010 Dl012 DI011
6
VCC
DlN1
ClK
DI09
Dl08
DI013
5
PIN8
PIN7
PIN6
DI06
0107
aND
4
PINS
PIN4
DI04
DIOS
3
PIN3
PIN1
DI01
DI03
2
PIN2
FC.
10ADD DIOO
UWS 10~DC 101DC
0
DI02
PINO ST~RT
PIN'A1'
ID
A
B
DINS! DIN12 DIN1S DlN21 DIN20 DlN23 DI021 DI020 DI017
DIN14 aND
DIN18
Dl018 Dl016
DI015 DI014
FCTO 10ADD 10ADC
II
8
Rot
FCf2
WRf
lDt
FCT1
aND
C
D
E
10AD[ 10AOC 10ADC 100DD 10ADD
VCC
4
2
1
5
7
a
F
H
J
K
l
84 LEAD PIN GRID ARRAY
BOTTOM VIEW
DI019 DI022 DI023 DlN22 DIN19 DIN17 DIN16 DlN13 DIN11 DIN10 DIN8
11
DI017 DI020 DI021 DlN23 DIN20 DIN21 DIN1S DlN12 DIN9
DIN7
DINS
10
DI016 DI018
DIN6
DIN4
9
DIN3
DIN2
8
DIN18 aND DIN14
DI014 DI01S
DI011 DI012 DI010
aND
DINO
PIN9
7
Dl013 DI08
DI09
CLK
DIN1
VCC
6
DI06
PIN6
PIN7
PIN8
S
PIN4
PINS
4
PIN1
PIN3
3
FCI
PIN2
2
,
PINO
B
A
aND
Dl07
Dl05
DI04
DI03
DlO1
DI02
Dloo 100DD IOADD IOADD UWS
0
6
3
WR.
FCT2
Rot
VCC
OADD 10ADD IOADD 100DD 100DD aND
1
2
4
7
5
FCT1
lot STAR
l
K
100DD 10ADO FCTO
8
II
J
H
a
F
4-24
E
D
C
HSP484101883
Pin Description
PIN NUMBER
SYMBOL
TYPE
DESCRIPTION
ClK
C6
I
Clock input. This input has no effect on the chips functionality when the chip is
programmed to an asynchronous mode. All signals denoted as synchronous
have their timing specified with reference to this signal.
PIN(}9
M-5, A7, 83-5, C5
I
Pixel Input. This input bus is sampled by the rising edge of clock. It provides the
on chip RAM with address values In Histogram, Bin Accumulate and lUT(write)
mode. During Asynchronous modes it Is unused.
lO#
Cl
I
The load pin is used to load the FCTO-2 bits into the FCT registers.
(See below).
FCTO-2
01-2, E3
I
These three pins are decoded to determine the mode of operation for the chip.
The signals are sampled by the rising edge of lO# and take effect aiter the rising edge of LOt. Since the loading of this function Is asynchronous to ClK, it Is
necessary to disable the STARn pin during loading and enable STARn at
least 1 ClK cycle following the lO# pulse.
STARn
Bl
I
This pin informs the on chip circuitry which clock cycle will start and/or stop the
current mode of operation. Thus, the modes are asynchronously selected (via
LOt) but are synchronously started and stopped. This input is sampled by the
rising edge of ClK. The actual function of this input depends on the mode that
is selected. STARn must always be held high (disabled) when changing
modes. This will provide a smooth transition from one mode to the next by allowing the part to reconfigure itself before new mode begins. When STARn is
high, lUT(read) mode is enabled except for Delay and Delay and Subtract
modes.
FC#
B2
I
Flash Clear. This input provides a fully asynchronous signal which effectively
resets all bits in the RAM Array and the input and output data paths to zero.
01NO-23
AS-II, B6-11,
C10-11,010-11,
E9-11, F10-11,
G9-11, H10-11
0100-23
J5-7,J10-11,
K2-11, L2-4, l6-11
I/O
Asynchronous data bus. Provides RAM access for a microprocessor in preconditioning the memory array and reading the results of the previous operation.
Conliguarable as either a 24-bit or 16-bit bus
IOAOOO-9
F1 ,F3,G1-3, H1-2,
J1-2,K1
I
RAM address in asynchronous modes. Sampled on the falling edge of WR# or
RO#.
UWS
F2
I
Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes
the contents of 0100-7 as being the upper eight-bits of the data in or out of the
Histogrammer. A zero means that 0100-15 are the lower 16-bits. In all other
modes, this pin has no effect.
WR#
E2
I
Write enable to the RAM for the data on 0100-23 when the HSP48410 is configured in one of the asynchronous modes. Asynchronous to ClK.
RO#
C2
I
Read control for the data on 0100-23 in asynchronous modes. Output enable
for 0100-23 in other modes. Asynchronous to ClK
VCC
A6, l1
+5V
GNO
C7, E1, F9, l5
Ground
I
Data Input bus. Provides data to the Histogrammer during Bin Accumulate,
lUT, Delay and Delay and
Subtract modes. Synchronous to ClK.
4-25
CJ
z
00
wen
QW
-(,)
>0
a:
a..
Specifications HSP4841 0/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage •••••••••••••••••......•.••....•••••. ~.ov
Input, Output Voltage ................. GND
to Vee +O.5V
Storage Temperature •••••••••••..•.•••.•.•• -6500 to +15O"C
Jt.r1CIion 'nimperalure. • • • . • • . • • • • • • • • • • . • . . • • • • . • • • +17500
Lead Temperature (Soldering 1(1s) •••.•.•..••...•....• +3()()OC
ESD ........................................... Class 1
Thermal ResIstance ... . . . • . • • . .. . • .. •
9JA
9JC
Ceramic PGA Package. . . . . . . . . . . • . • 34.3"CIW SJi'Cm
Maximum Package Power Dissipation at +12500
Ceramic PGA Package ......................... 1.46Watt
Gate Count ................................... 3500 Gates
-o.sv
CAUTION: Snues abol/8 Iho5e listed In "Abso/ufrJ MaxImum Ratings" may causa permanent damage to/he dtwIt:e. This is a stress only rallng and operation
of /he dtwIcs at IMH or any o/har ccndltlons aboII8 /hose indicated In the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ..................... +4.5V to +5.5V
Operating Temperature Range •...••..••••..•. -5500 to +125°C
TABLE 1. DC ELECTRICAL SPECIFICAnONS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
UNITS
Vcc= 5.5V
1,2,3
-55"C STAS +125°C
2.2
-
V
VIL
VCC= 4.5V
1,2,3
-55°CSTAS+125°C
-
O.S
V
High Level Clock Input
VIHC
Vee =5.5V
1,2,3
-55°CSTAs+125°C
3.0
-
V
Low Level Clock Input
VILC
Vee =4.5V
1,2,3
-55°C S TAS+125oo
-
O.S
V
Output High Voltage
VOH
IOH = -4OOjiA,
Vee = 4.5V (Note 1)
1,2,3
-55"C S TAS +12500
2.6
-
V
Output Low Voltage
VOL
IOL = +2.OmA,
Vee = 4.5V (Note 1)
1,2,3
-55°C S TAS +12500
-
0.4
V
Input Leakage Current
IL
VIN = VCC or GND,
VCC= 5.5V
1,2,3
-55"C S TAS +12500
-10
10
IIA
VO Leakage Current
10
Vour=VccorGND,
Vee =5.5V
1,2,3
-55°CSTAS+125oo
-10
10
IIA
Standby Supply Current
leesB
VIN = Vee or GND,
Vee =5.5V,
Outputs Open
1,2,3
-55"C STA:5>+125"C
-
500
jiA
Operating Power Supply
Current
IcOOP
f=25.6MHz,
VIN = Vee or GND
Vee = 5.5V (Note 2)
1,2,3
-55°C sTAs +12500
-
308
mA
7,S
-55°C sTAs +1250 C
-
-
-
PARAMETER
SYMBOL
logical One Input Voltage
VIH
logical Zero Input Voltage
Functional Test
FT
CONDITIONS
(Notes 3,4)
NOTES:
1. Interchanging of force and sense conditions Is permitted.
2. Power Supply current is proportional to operating frequency. Typical rating for Icoop Is12mAlMHz. Maximum junction temperature must
be considered when operating part at high clock frequencies.
3. Tested as 1001ows: 1= 1MHz, VIH =2.6V, VIL = 0.4V, VOH ~ 1.5V, VOL S 1.5V, VIHC = 3.4V and VILC = 0.4V.
4. loading is as specIfied In the test load circuit with CL = 4OpF.
4-26
Specifications HSP48410/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: Vee
=5.0V ± 10%, TA =·550C to +1250C (Note 1)
-33 (33MHz)
PARAMETER
Clock Period
Clock Low
Clock High
DIN Setup
DIN 0-23 Hold
Clock to 010 0-23 Valid
FCII Pulse Width
SYMBOL
CONo.
ITIONS
Tcp
TCH
TCL
Tos
TOH
Too
TFL
GROUP A
SUBGROUPS
TEMPERATURE
MIN
9,10,11
-55OC:STA :S+1250C
30
9,10,11
-550C:STA:S+1250C
12
9,10,11
-55°C :STA:S +1250C
12
9,10,11
-55°C :STA:S +1250C
15
9,10,11
-550C:STA:S+1250C
1
-
9,10,11
-550C:S TA:S +1250C
-
9,10,11
-550C:S TA:S +1250C
-25 (25.6MHz)
MAX
-
-
MIN
39
15
15
19
-
24
35
-
35
12
-
15
TFS
9,10,11
FCT 0-2 Hold from lOll
TFH
9,10,11
-5500 :STA :S+1250C
1
-
1
9,10,11
-55°C :STA:S +1250C
15
-
16
9,10,11
-55°C :STA:S +1250C
0
-
0
9,10,11
-550C:STA:S+1250C
15
-
16
9,10,11
-550C:STA :S+1250C
9,10,11
-55°C :STA:S +1250C
12
9,10,11
-550C:STA:S+1250C
Tcp
STARn Hold from ClK
PIN 0-9 Setup Time
PIN 0-9 Hold Time
TSH
Tps
TpH
1
-
lOll Pulse Width
TLL
lOll Setup to STARn
TLS
WRlIlow
TWL
9,10,11
-550C:STA :S+1250C
15
WR#High
TWH
9,10,11
-55°C :STA:S +1250C
15
Address Setup
TAS
9,10,11
-550C:S TA:S +1250C
16
Address Hold
TAH
9,10,11
-550C:s TA:S +1250C
2
010 Setup to WRII
Tws
9,10,11
-550C:s TA:S +1250C
16
-
010 Hold from WRII
TWH
9,10,11
-55°C :STA:S +1250C
2
-
RO# low
TRL
9,10,11
-55°C 0<> TA 0<> +1250C
43
RO# High
TRH
9,10,11
-55°C 0<> TA 0<> +1250C
17
ROll low to 010 Valid
TRO
9,10,11
-55°C :STAo<> +1250C
Output Enable Time
TOE
9,10,11
-55°C :STA:S +1250C
-
ReadiWrite Cycle Time
Tcv
9,10,11
-55°C 0<> TAO<> +1250C
65
Note 2
Note 3
-
1
FCT 0-2 Setup to lO#
Tss
-
16
-550C:S TA:S +1250C
STARn Setup to ClK
MAX
1
15
Tcp
-
43
19
20
20
20
2
20
2
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
55
ns
24
ns
80
-
ns
NOTES:
1. A.C. Testing is performed as follows: Input levels (ClK) O.OV and 4.0V; Input levels (All other inputs) OV and 3.0V. Timing reference levels
(ClK) = 2.0V, (All others) = 1.5V. Output load circuit with C L= 4OpF. Output transition measured at VOH " 1.5V and VOL" 1.5V.
3. Transition is measured at 1200 mV from steady state voltage with loading as specified in test load circuit with C L= 4OpF.
4-27
W(I)
QW
>0
ex:
a.
ns
-
2. There must be at least one rising edge of ClK between the rising edge of lO# and the falling edge of STARn.
~
0(1)
-(.)
ns
ns
55
20
UNITS
Specifications HSP484101883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
-33 (33MHz)
-25 (25.6MHz)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
Input Capacitance
CIN
Vcc = Open, f = 1MHz,
All measurements are
referenced to device
GND.
1
TA = +25°C
-
12
-
12
pF
Output Capacitance
Co
Vcc = Open, f = 1MHz,
All measurements are
referenced to device
GND.
1
TA =+2SoC
-
12
-
12
pF
010 Valid After
RD# High
TOH
1,2
-SSoC,; TA ,; +12SoC
0
-
0
-
ns
Output Disable
lime
Too
1,2
-SSoC'; TA ,; +12SoC
-
27
-
27
ns
Output Rise Time
TR
From 0.8V to 2.OV
1,2
-SSoC'; TA ,; +12SoC
9
9
ns
Output Fall Time
TF
From 2.OV to 0.8V
1,2
-SSoC,; TA ,; +12SoC
9
9
ns
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes.
2. Loading is as specified in the test load circuit with C L = 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/S004
-
Interim Test
100%/S004
-
PDA
100%
1
Final Test
100%
2,3,8A,8B,10,11
-
1,2,3,7,8A,8B,9,10,11
Samples/SOOS
1,7,9
Group A
Groups C and 0
4-28
HSP484101883
Burn-In Circuits
84 LEAD GRID ARRAY
TOP VIEW
DIN10 DIN11 DIN13 DIN16 DIN17 DIN19 DIN22 DI023 DI022 DI018
11
DINS
10
DINS
DIN7
9
DIN4
DINS
8
DIN2
DlN3
7
PINS
DINO
GND
6
VCC
DIN1
CLK
DI09
Dl08
DI013
5
PINS
PIN7
PINS
DI06
DI07
GND
4
PINS
PIN4
DI04
DI05
3
PIN3
PIN1
DI01
DI03
2
PIN2
FC.
PINO ST~RT
DINS
DIN12 DIN15 DIN21 DIN20 DIN23 DI021 DI020 DI017
DIN14
GND
DlN18
DI018 DI016
DI015 DI014
DI010 DI012 DI011
FCTO 10ADD 10~DD
9
Ra.
FCT2
WR.
UWS 10~DD 10~DD 10ADD
DIOO
0
DI02
La.
FCT1
GND
10ADD 10~DD 10~DD 10ADD 10ADD
5
2
1
VCC
CJ
z
OUi
PIN'A1'
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
Al
PINO
Fl
A2
PIN2
A3
PIN3
A
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
F7
Ell
PIN
NAME
0lNI6
BURN-IN
SIGNAL
PGA
PIN
F2
J5
PIN
NAME
0106
BUFIN-IN
SIGNAL
F7
B9
DIN6
F3
Bl0
DIN7
Fa
Fl
IOAOD5
F6
J6
DI09
FlO
F4
Bll
DIN10
Fll
F2
UWS
Fll
J7
01010
Fl1
A4
PIN5
F6
Cl
lD#
Fll
F3
IOADD9
FlO
Jl0
01021
F7
A5
PINB
F9
C2
RD#
Fl
F9
GNO
GNO
Jll
DI023
F9
A6
VCC
VCC
C5
PIN6
F7
FlO
DIN21
F7
KI
10ADOl
F2
A7
PIN9
FlO
C6
ClK
FO
Fll
0lN17
F3
K2
0100
FI
AB
DIN2
F3
C7
GND
GND
Gl
IOAOD7
FB
K3
DIOl
F2
A9
DIN4
F5
Cl0
0lN9
FlO
G2
IOA006
F7
K4
0104
F5
Al0
DIN5
F6
Cll
0lNl1
F12
G3
10ADDB
F9
K5
0107
FB
All
DINB
F9
Dl
FCTl
F13
G9
DIN1B
F4
K6
OIOB
F9
Bl
START#
FlO
D2
FCT2
F14
Gl0
0lN20
F6
K7
01012
F13
B2
FC#
F16
010
0lN12
F13
Gil
0lN19
F5
K8
01015
Fl
B3
PINl
F2
Dll
DIN13
F14
HI
IOA004
F5
K9
OIOlB
F4
B4
PIN4
F5
EI
GNO
GNO
H2
IOAD03
F4
Kl0
01020
F6
B5
PIN7
FB
E2
WR#
F2
HIO
DIN23
F9
Kl1
01022
FB
B6
DINl
F2
E3
FCTO
F12
Hll
0lN22
FB
l1
VCC
VCC
B7
DINO
Fl
E9
DIN14
F15
JI
IOA002
F3
L2
0102
F3
BB
DIN3
F4
El0
0lNI5
Fl
J2
10ADOO
FI
l3
0103
F4
l4
DI05
F6
NOTES:
1. Vcd2 (2.7V ± 10%) used lor outputs only.
4. 0.1111 (min) capacitor between Vcc and GND per position.
2. 47KQ (±20%) resistor connected to all pins except Vcc and GND.
5. Fo = 100KHz± 10%, F1 = FO/2, F2 = F1/2 ... FI6 = F1512,
40% - 60% Duty Cycle.
3. Vcc = 5.5 ± 0.5V.
6. Input Voltage Limits: VIL = O.BV max. VIH = 4.5V ± 10%.
4-29
wtn
QW
-0
>0
a:
a..
HSP484101883
Metallization Topology
DIE DIMENSIONS:
330x281 x 19± lmils
METALLIZATION:
Type: Si - AI or Si-AI-Cu
Thickness: 8kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY:
0.47 x 105 Ncm2
Metallization Mask Layout
0
z
ii:
N
Z z
ii:
ii:
z...
ii:
. .
z
ii:
z
ii:
HSP4841 01883
~
ii:
z...
ii:
co
z
ii:
...u
~
U
U
>
Q
Z
CI
0
i
ii:
Z
is
z
is
!l!
is
...
Z
is
.. ..
Z
is
Z
is
... ...z
Z
is
is
DINe
FC'
DlN9
RD#
DlN10
STARTIJ
DlN11
LD#
DlN12
FCT2
Fcn
FCTO
DlN13
DlN14
DlN15
WR'
DlN16
GND
DlN17
uws
GND
100DD9
DlN18
100DDe
DlN19
IOADD7
DlN20
100DD6
DlN21
100DD5
DlN22
IOADD4
DlN23
IOADD3
Dl023
IOADD2
IOADD1
Dl022
100DDO
Dl021
VCC
01020
8 0 S 8
is
is
is
is
ais
l!l lS
is
is
!)
is
Q
Z
CI
co
g
.
3 00 0 0N 0... 0... 0 ...0 0... 0co ...0
is is is
is
~
is
4-30
is
is
is
is
is
is
HSP48901
3 X 3 Image Filter
January 1994
Features
Description
• DC to 30MHz Clock Rate
• Conflgurable for 1-0 and 2-D Correlation! Convolution
• Dual Coefficient Mask Registers, Swltchable In a Single Clock Cycle
The Harris HSP48901 is a high speed 9-Tap FIR Filter which
utilizes 8-bit wide data and coefficients. It can be configured
as a one dimensional (1-0) 9-Tap filter for a variety of signal
processing applications, or as a two dimensional (2-D) filter
for image processing. In the 2-D configuration, the device is
ideally suited for implementing 3 x 3 kernel convolution. The
30MHz clock rate allows a large number of image sizes to be
processed within the required frame time for real-time video.
• Two's Complement or Unsigned 8-Bit Input Data and
Coefficients
• 20-Blt Extended Precision Output
• Standard J.1P Interface
Data is provided to the HSP48901 through the use of programmable data buffers such as the HSP9500 or any other
programmable shift register. Coefficient and pixel input data
are 8-bit signed or unsigned integers, and the 20-bit
extended output guarantees no overflow will occur during the
filtering operation.
Applications
• Image Filtering
• Edge Detection!Enhancement
• Pattern Matching
• Real Time Video Filters
There are two internal register banks for storing independent
3 x 3 filter kernels, thus facilitating the implementation of
adaptive filters and multiple filter operations on the same
data.
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
PACKAGE
HSP48901 JC-20
oOC to +700 C
68 Lead PLCC
HSP48901 JC-30
OOC to +700 C
68 Lead PLCC
HSP48901 GC-20
OOC to +700 C
68 Lead PGA
HSP48901 GC-30
OOC to +700 C
68 Lead PGA
The configuration of the HSP48901 Image Filter is controlled
through a standard microprocessor interface and all inputs
and outputs are TTL compatible.
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Block Diagram
DIN3 (0-7)
CIND-7
FRAMe.
A0-2
lOt
ClK
HOLD
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
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4-31
File Number
2459.4
HSP48901
Package Pinouts
68 LEAD PLCC
TOP VIEW
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DIN2 (7)
DOUTO
DIN2 (8)
OOU17
DIN2 (5)
DOU18
DIN2 (4)
DOUT8
DIN2 (3)
GND
DIN2 (2)
DOUT10
DIN2 (1)
DOUT11
DIN2 (0)
Dour12
GND
DOU113
DINa (1)
DOUT14
DINa (8)
DOUT15
DINa (5)
DQUT10
DiNa (4)
OOU117
DiNa (3)
DOUT18
DiNa (2)
DOUJia
DiNa (1)
Vee
DiNa (0)
FRAMES#'
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32 33 34 35 36 37 38 38 40 41
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DOU16
DOUT7
DOUT5
vee
DOUT8
DOUTa
11
10
OOUT8 DOUT10 DOUT12
ooun4
00UT16
ooun8 vee
FRAME
#
AO
DOUT4
A.
A1
OOUT1
DOUT2
LOP
HOLD
GND
OOUTO
elNO
GND
DINl (6) DINl (7)
CIN2
GINl
DIN1 (4) DINl (5)
CIN4
CINa
DINl (2) DIN1 (3)
CIN8
CINS
DINl (0) DINl (1)
GND
CIN7
Vee
eLK
Vee
GND
DOUT11 OOUT1a DOUT15 DOUT17 DOUT19
DIN. (7) DIN2 (5) DIN2 (3) DINa (1)
GND
DIN2 (6) DlN2 (4) DIN2 (2) DIN2 (0) DINa
A
B
e
o
en
DIN3 (6) DINa (4) DINa (2)
DIN3 (5) DINS (3) DINS (1) DINa (0)
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4-32
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HSP48901
Pin Descriptions
NAME
PLCCPlN
VCC
9,27,45,61
GND
18, 29, 38, 56
CLK
28
I
Input and System clock. Operations are synchronous with the rising edge of this
clock signal.
DIN1(7-0)
1-8
I
Pixel Data Input bus # 1. These inputs are used to provide 8-bit pixel data to
the HSP48901. The data must be provided In a synchronous fashion, and is
latched on the rising edge of the CLK signal. The DINl (0-7) inputs are also used to
input data when operating in the 9 Tap FIR mode.
DIN2(7-0)
10-17
I
Pixel Data Input bus #2. Same as above. These inputs should be grounded when
operating in the 10 mode.
DIN3(7-0)
19-26
I
Pixel Data Input bus #3. Same as above. These inputs should be grounded when
operating in the 1 0 mode.
CIN7-0
30-37
I
Coefficient Data Input bus. This input bus is used to load the Coefficient Mask
register(s) and the Initialization register. The register to be loaded is defined by
the register address bHs AO-2. The CINO-7 data is loaded to the addressed register
through the use of the LD# input.
DOUTl9-0
46-55,57-60,
82-67
0
Output Data bus. This 20-8it output port is used to provide the convolution result.
The result is the sum of products of the input data samples and their corresponding
coefficients.
FRAME#
44
I
Frame# is an asynchronous new frame or vertical sync input. A low on this input
resets all internal circuitry except for the Coefficient and INT registers. Thus,
after a Frame# reset has occurred, a new frame of pixels may be convolved without
reloading these registers.
TYPE
DESCRIPTION
The +5V power supply pins. 0.1 ~F capacitors between the VCC and GND pins are
recommended.
The device ground.
HOLD
40
I
The Hold Input is used to gate the clock from all of the internal circuitry of the
HSP48901. This signal is synchronous, is sampled on the rising edge of CLK and
takes effect on the following cycle. While this signal is active (high), the clock will
have no effect on the HSP48901 and internal data will remain undisturbed.
A2-0
41-43
I
Control Register Address. These lines are decoded to determine which register in
the control logic is the destination for the data on the CINO-7 inputs. Register
loading is controlled by the AO-2 and LD# inputs.
LD#
39
I
Load Strobe. LD# is used for loading the internal registers of the HSP48901. The
rising edge of LD# will latch the CINo-7 data into the register specified by Ao-2.
The Address on Ao-2 must be set up with respect to the falling edge of LD# and
must be held with respect to the rising edge of LD#.
4-33
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HSP48901
Functional Description
8-Bit Multiplier Array
The HSP48901 can perform convolution of a 3 x 3 filter kernel with 8-bit image data. It accepts the image data in a raster scan, non-interlaced format, convolves it with the filter
kernel and outputs the filtered image. The input and filter
kernel data are both 8-bits, while the output data is 20-bits
to prevent overflow during the convolution operation. Image
data is input via the DIN1, DIN2, and DIN3 busses. This data
would normally be provided by programmable data buffer
such as the HSP9501 as illustrated in the operations
section of this specification. The data is then convolved with
the 3 x 3 array of filter coefficients. The resultant output data
is then stored In the output register. The HSP48901 may
also be used in a one-dimensional mode. In this
configuration, it functions as a 1-D 9-tap FIR filter. Data
would be input via the DIN1(O-7) bus for operation in this
mode.
The multiplier array consists of nine 8 x 8 multipliers. Each
multiplier forms the product of a filter coefficient with a corresponding pixel in the input image. Input and coefficient
data may be in either two's complement or unsigned integer
format. The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution operation as shown below:
Initialization of the convolver is done using the CINO-7 bus
to load configuration data and the filter kernel(s). The address lines AO-2 are used to address the internal registers
for initialization. The configuration data is loaded using the
AO-2, CINO-7 and LD# controls as address, data and write
enable, respectively. This interface is compatible with
standard microprocessors without the use of any additional
glue logic.
Filtered image data is output from the convolver .over the
DOUTO-19 bus. This output bus is 20-bits wide to provide
room for growth during the convolution operation.
I
CINO -7
-I
I
10
11
-
P1
P2
F
P4
P5
P6
G
H
I
P7
P8
P9
The control logic (Figure 1) contains the Initialization
Register and the Coefficient Registers. The control logic is
updated by placing data on the CINO-7 bus and using the
AO-2 and LD# control lines to write to the addressed
register (see Address Decoder). All of the control logiC
registers are unaffected by FRAME#.
ENCRO#
ENCR1#
CASH
CR1#
CRO#
,
I
I
INITIALIZATION
DATA
/
~1~~OO~~qffi~oo~m~ooqMq
H
-+
~ I H1 E
G
-+
I G1 E I F1
F
-+
E
E
-+
S
Q
Q I--
C
FIGURE 1. CONTROL LOGIC BLOCK DIAGRAM
4-34
D
-+
C
-+
I E1 E I D1 E I C1
COEFFICIENT
REGISTER 1
-
P3
COEFFICIENT
REGISTER 0
I
ENCRO#
C
I
r-CR1#
8
E
INITIALIZATION REGISTER
(INT)
CAS #
CRO#
A
0
Control Logic
ADDRESS
DECODE
LD#
INPUT DATA
OUTPUT = (AxP1) + (8 x P2) + (Cx P3)
+ (0 x P4) + (E xP5) + (F x P6)
+ (G x P7) + (H x P8) + (I x P9)
3
AO - 2
ENCR1#
FILTER KERNEL
B
r-
~l B1
A
-+
El A1 EJ
HSP48901
Initialization Register
The initialization register is used to appropriately configure
the convolver for a particular application. It is loaded
through the use of the CINO-7 bus along with the lD# input. Bit 0 defines the input data and coefficients format
(unsigned or two's complement); Bit 1 defines the mode of
operation (1-D or 2- D); and Bits 2 and 3 determine the type
of rounding to occur on the DOUTO-19 bus; The complete
definition of the initialization register bits is given in Table 1.
TABLE 1. INITIALIZATION REGISTER DEFINITION
Address Decoder
FUNCTION = Input & Coefficient
Data Format
0
Unsigned Integer format
1
Two's complement format
BIT1
3
FUNCTION
0
1-0 9-tap filter
1
2-03 x 3 filter
BIT
2
FUNCTION
= Operating Mode
=Output Rounding
0
0
No Rounding
0
1
Round to 16 bits (i.e. OOUT19-4)
1
0
Round to 8 bits (i.e. OOUT19-12)
1
1
NoIValid
The nine coeffiCients must be loaded sequentially over the
CINO-7 bus from A to I. The address of CREGO or CREG1
is placed on AO-2, and then the coefficients are written to
the corresponding coefficient register one at a time by using
the lD# input.
The address decoder (See Figure 1) is used for writing to
the control logic of the HSP48901. loading an Internal register is done by selecting the destination register with the
AO-2 address lines, placing the data on CINO-7, and asserting lD# control line. When lD# goes high, the data on
CINO-7 is latched into the addressed register. The address
map for the AO-2 bus is shown in Table 2.
INITIALIZATION REGISTER
BITO
cient mask is used to process the data. Thus, no clock
cycles have been lost when changing between alternate
3 x 3 filter kernels.
Coefficient Registers (CREGO, CREG1)
The control logic contains two coefficient register banks,
CREGO and CREG1. Each of these register banks is capable of storing nine 8-bit filter coefficient values (3 x 3
Kernel). The output of the registers are connected to the
coefficient input of the corresponding multiplier in the 3 x 3
multiplier array (designated A through I). The register bank
to be used for the convolution is selectable by writing to the
approprite address (See address decoder). All registers in a
given bank are enabled simultaneously, and one of the
banks is always active.
While loading of the control logic registers is asynchronous
to ClK, the target register in the control logic is being read
synchronous to the internal clock. Therefore, care must be
taken when modifying the convolver setup parameters during processing to avoid changing the contents of the registers near a rising edge of ClK. The required setup time
relative to ClK is given by the specification TlCS. For example, in order to change the active coefficient register from
CREGO to CREG1 during an active convolution operation, a
write will be performed to the address for selecting CREG 1
for internal processing (AO-2 = 110). In order to provide
proper uninterrupted operation, lD# should be deasserted
at least TlCS prior to the next rising edge of ClK. Failure to
meet this setup time may result in unpredictable results on
the output of the convolver. Keep in mind that this requirement applies only to the case where changes are being
made in the control logic during an active convolution operation. In a typical convolver configuration routine, where the
configuration data is loaded prior to the actual convolution
operation, this specification would not apply.
For most applications, only one of the register banks is necessary. The user can simply load CREGO after power up,
and use it for the entire convolution operation. (CREGO is
the default register). The alternate register bank allows the
user to maintain two sets of filter coefficients and switch between them in real time. The coefficient masks are loaded
via the CINO-7 bus by using AO-2 and lD#. The selection
of the particular register bank to be used in processing is
also done by writing to the appropriate address (See
address decoder). For example, if CREGO is being used to
provide coefficients to the multipliers, CREG1 can be
updated at a low rate by an external processor; then, at the
proper time, CREG1 can be selected, so that the new coeffi-
4-35
TABLE 2. ADDRESS MAP
CONTROL LOGIC ADDRESS MAP
A2-0
FUNCTION
0 0 0
Reserved for future use
0 0 1
Reserved for future use
0
1 0
Load Coefficient Register 0 (CREGO)
0
1 1
Load Coefficient Register 1 (CREG 1)
1 0 0
Load Initialization Register (INT)
1 0 1
Select CREGO for Internal Processing
1 1 0
Select CREG1 for Internal Processing
1 1 1
No Operation
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HSP489 0 1
Control Signals
8
20
Hold
DOUT 0 -19
The HOLD control input provides the ability to disable internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of ClK and takes effect during
the following clock cycle (Refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.
FILTERED
IMAGE
DATA
HSP48901
INITIALIZATION
DATA
CLK
HOLD _______/
,'---..,-----
INTERNAL
CLOCK
A
B
C
PM -1,N-1
PM -1,N
PM -1,N+ 1
D
E
F
PM,N -1
PM,N
PM,N+ 1
F
H
PM+ 1,N-1
PM+ 1,N
PM+ 1,N+ 1
FIGURE 2. HOLD OPERATION
RLTER KERNEL
FRAME#
The FRAME# input initializes all internal flip flops and registers except for the coefficient and initialization registers. It
is used as a reset between video frames and eliminates the
need to re-initialize the entire HSP48901 or reload the coefficients. The registers and flip flops will remain in a reset
state as long as FRAME# is active. FRAME# is an asynchronous input and may occur at any time. However, it must
be deasserted at least tFS ns prior to the rising clock edge
that is to begin operation for the next frame in order to ensure the new pixel data is properly loaded.
Operation
A single HSP48901 can be used to perform 3 x 3 convolution on 8-bit image data. A block diagram of this configuration is shown in Figure 3. The inputs of an external data
buffer (such as the HSP9501) are connected to the input
data in parallel with the DIN1 (0-7) lines; the outputs of the
data buffer are connected to the DIN2(0-7) bus. A second
external data buffer is connected between the outputs of the
first buffer and the DIN3(0-7) inputs. To perform the convolution operation, a group of nine image pixels is multiplied
by the 3 x 3 array of filter coefficients and their products are
summed and sent to the output. For the example in figure 3,
the pixel value in the output image at location m,n is given
by:
OOUT(m,n) =
A x Pm-1 ,n-1 + B x Pm-1 ,n + ex Pm-1 ,n+1
+ 0 x Pm,n-1
+ Ex Pm,n
+ F x Pm,n+1
+ GxPm+1,n-1 +HxPm+1,n +lxPm+1,n+1
IMAGE DATA
FIGURE 3. 3 x 3 KERNEL ON AN 8-BIT IMAGE
Multiple filter kernels can also be used on the same image
data using the dual coefficient registers CREGO and
CREG1. This type of filtering is used when the
characteristics of the input pixel data change over the
image in such a way that no one filter produces satisfactory
results for the entire image. In order to filter such an image,
the characteristics of the filter itself must change while the
image is being processed. The HSP48901 can perform this
function with the use of an external processor. The
processor is used to calculate the required new filter
coefficients, loads them into the coefficient register not in
use, and selects the newly loaded coefficient register at the
proper time. The first coefficient register can then be loaded
with new coefficients in preparation for the next change.
This can be carried out with no interruption in processing,
provided that the new register is selected synchronous to
the convolver ClK signal.
The HSP48901 can also operate as a one dimensional 9 tap
FIR filter by programming the initialization register to 1-D
mode (i.e. INT bit 1 = '0'). This configuration will provide for
nine sequential input values to be multiplied by the coefficient values in the selected coefficient register and provide
the proper filtered output. The input bus to be used when
operating in this mode is the DIN 1(0-7) inputs.
The equation for the output in the 1-D 9-tap FIR case becomes:
This process is continually repeated until the last pixel of the
last row of the image has been input. It can then start again
with the first row of the next frame. The FRAME# pin is used
to clear the internal multiplier registers and DOUTO-19 registers between frames. The row length of the image to be
convolved is limited only by the maximum length of the external data buffers.
The setup is straightforward. The user must first setup the
HSP48901 by loading a new value into the initialization register. The coefficients can now be loaded one at a time from
A to I via the CINO-7 coefficient bus, and the AO-2 and lD#
control lines.
OOUTn=
A x On-8 + B x On-7 + C x On-6 + 0 x On-5
+ Ex On-4 + F x On-3 + G x On-2 + H x On-1
+ IxOn
Frame Rate
The total time to process an image is given by the formula:
T= RxC/F
where:
T = Time to process a frame
4-36
R = number of rows in the image
C = number of pixels in a row
F = clock rate of the HSP48901
Specifications HSP48901
Absolute Maximum Ratings
Supply Voltage ..................................................•....••......••...•........•................... +8.0V
Input, Output or 110 Voltage Applied .•....•.........................................•.........••. GND -0.5V to VCC +0.5V
Storage Temperature Range ..................•••..••.......•.......................................•. -65 0 C to +1500 C
Maximum Package Power Dissipation at + 700C .............................. PGA Package = 2.56W, PLCC Package = 1.9W
Thermal Impedance Junction To Ambient (Sja) ......•....•............... PGA Package = 41 oC/W, PLCC Package = 42.8 0 C/W
Thermal Impedance Junction To Case (Sjel ....•...•....•........•...••. PGA Package = 160 C/W, PLCC Package = 14.90C/W
Gate Count ...............................••.............•...•...••....•................................ 13,594 Gates
Junction Temperature (TJ) ............................................. PGA Package = +1750 C, PLCC Package = +1500 C
Lead Temperature (Soldering, Ten Seconds) ...•........•....................•.•................................. +3000 C
ESD Classification .....••......••.............•..•.•........................................................... Class 1
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range .......••................•...............................••........•..•....•. +4.75V to +5.25V
Operating Temperature Range .•..........................•..............•............................•... OoC to + 700 C
D.C. Electrical Specifications
(VCC = 5.0V ± 5%, TA = OoC to +70 0 C)
PARAMETER
Logical One Input Voltage
SYMBOL
MIN
MAX
UNITS
TEST CONDITIONS
VIH
2.0
-
V
VCC=5.25V
CJ
VIL
-
0.8
V
VCC=4.75V
High Level Clock Input
VIHC
3.0
-
V
VCC= 5.25V
Low Level Clock Input
VILC
-
0.8
V
VCC=4.75V
Output HIGH Voltage
VOH
2.6
-
V
10H = -400 flA, VCC = 4.75V
Output LOW Voltage
VOL
-
0.4
V
10L = +2.0mA, VCC = 4.75V
11
-10
10
flA
VIN = VCC or GND, VCC = 5.25V
Standby Power Supply Current
ICCSB
-
500
f1A
VIN = VCC or GND, VCC = 5.25V,
Outputs Open
Operating Power Supply Current
ICCOP
-
120
rnA
f = 20MHz, VIN = VCC or GND
VCC = 5.25V (Note 1)
MAX
UNITS
TEST CONDITIONS
10
pF
15
pF
FREQ = 1 MHz, VCC = Open, all measurements
are referenced to device ground.
Logical Zero Input Voltage
Input Leakage Current
CapaCitance
(TA = +25 0 C, Note 2)
SYMBOL
MIN
Input Capacitance
CIN
Output Capacitance
CO
-
PARAMETER
NOTES: 1. Power supply current is proportional to operating frequency. Typical rating for ICCOP
IS
6mA/MHz.
2. Not tested, but charactenzed at initial design and at major process/design changes.
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Ie handling
4·37
procedures should be followed.
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Specifications HSP489 0 1
A.C. Electrical Specifications (VCC = 5.0V ± 5%, TA = ooc to +70°C)
-30
PARAMETER
SYMBOL
MIN
-20
MAX
MIN
MAX
UNITS
-
ns
ns
16
-
0
-
ns
-
30
ns
ns
TCYCLE
33
TpWH
13
-
50
Clock Pulse Width High
Clock Pulse Width Low
TpWL
13
-
20
Data Input Setup Time
TOS
14
TDH
0
-
TOUT
-
21
12
-
Clock Period
Data Input Hold Time
Clock 10 Data Out
20
TEST CONDITIONS
ns
ns
Address Setup Time
TAS
5
Address Hold Time
TAH
2
Configuration Data
Setup Time
TCS
10
-
Configuration Data
Hold Time
TCH
0
-
0
-
ns
LD# Pulse Width
TLPW
13
-
20
-
ns
LD# Setup Time
TLCS
31
TCYCLE+2
40
TCYCLE+2
ns
HOLD Setup Time
THS
10
-
12
ns
-
TCYCLE
-
ns
Note 2
8
ns
From 0.8V to 2.0V
8
ns
From 2.0VtoO.8V
HOLD Hold Time
THH
0
TFPW
TCYCLE
FRAME# Setup Time
TFS
28
Output Rise Time
TR
Output Fall Time
TF
FRAME# Pulse Width
-
5
2
0
40
-
8
8
ns
ns
Note 1
ns
ns
NOTES: 1. This specification applies only to the case where a change in the active coefficient register is being selected during a convolution operation. It
must be met in order to achieve predictable results at the next rising clock edge. In most applications, this selection will be made asynchronously.
and the T LeS specification may be disregarded.
2. While FRAME4#: is asynchronous with respect to eLK, it must be deasserted a minimum ofTFS ns prior to the rising clock edge which is to begin
loading new pixel data for the next frame.
3. A.C. resting is performed os follows: Input levels (ClK Input) = 4.0V and OV; Input levels (All other Inputs) = OV to 3.0V; Input timing reference
2.0V. (Others)
1.5V; Other timing references: VOH ~ 1.5V. VOL $. 1.5V; Output load per test load circuit with CL = 40pF.
levels: (ClK)
=
=
Test Load Circuit
,--------------1
1
1
1
1
1
1
1
1
1
1
1.5V
1
1
1
"INCLUDES STRAY AND
JIG CAPAcrrANCE
1
EQUIVALENT CIRCUIT
1
1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ --1
4-38
HSP489 0 1
Timing Waveforms
TCYClE
ClK
lD#
r
DIN 0-7
AD -2
____
TO_UT
DOUT 0 -19
----------------------
CINO -7
FUNCTIONAL TIMING
CONFIGURATION TIMING
INTERNAL
CLOCK
SYNCHRONOUS LOAD TIMING
FRAME#
HOLD TIMING
~
TFS
CLK
FRAME# TIMING
4-39
HSP48908
Two Dimensional Convolver
January 1994
Features
Description
• Single Chip 3 x 3 Kernel Convolution
The Harris HSP48908 is a high speed Two Dimensional
Convolver which provides a Single chip implementation of a
video data rate 3 x 3 kernel convolution on two dimensional
data. It eliminates the need for external data storage through
the use of the on-chip row buffers which are programmable
for row lengths up to 1024 pixels.
• Programmable On-Chip Row Buffers
• DC to 32MHz Clock Rate
• Cascadable for Larger Kernels and Images
• On-Chlp 8-Blt ALU
• Dual Coefficient Mask Registers, Swltchable In a Single Clock Cycle
• 8-Blt Signed or Unsigned Input and Coefficient Data
• 20-Blt Extended Precision Output
Data is provided to the HSP48908 in a raster scan non interlaced fashion, and is internally buffered on images up to
1024 pixels wide for the 3 x 3 convolution operation. Images
with larger rows and convolution with larger kernel sizes can
be accommodated by using external row buffers and/or mUltiple HSP48908s. Coefficient and pixel input data are 8-bit
Signed or unsigned integers, and the 20-bit convolver output
guarantees no overflow for kernel sizes up to 4 x 4. Larger
kernel sizes can be implemented however, since the filter
coefficients will normally be less than their maximum 8-bit
values.
• Standard IlP Interface
• Low Power CMOS
Applications
• Image Filtering
• Edge Detection
• Adaptive Filtering
• Real nme Video Filters
Ordering Information
TEMPERATURE
RANGE
PACKAGE
HSP48908VC-20
oOC 10+700C
100 Lead MQFP
HSP48908VC-32
OOC 10 +700C
100 Lead MQFP
HSP48908JC-20
Ooc 10 +700C
84 Lead PLCC
HSP48908JC-32
OOC to+700C
84 Lead PLCC
HSP48908GC-20
ooC to +700C
84 Lead PGA
HSP48908GC-32
OOC 10 +7ooC
84 Lead PGA
PART NUMBER
There are internal register banks for storing two independent
3 x 3 filter kernels, thus facilitating the implementation of
adaptive filters and multiple filter operations on the same
data. The pixel data path also includes an on-chip ALU for
performing real-time arithmetic and logical pixel point operations.
The HSP48908 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs are TTL
compatible.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corpo!
CA80&
CAB07
OOUTZ
00014
OOU19
OND
CA803
OND
DOUT3
D0UT7
VCC
CA801
CAS02
OE#
OND
OOU18 OOUT10 DOUT12 DOUT1
DOUT11 DOUT1
DOUT19
OND
CA811
FRAME
#
CA810
CA8&2
VCC
RESET
CA816
CAS'"
CAE ..
CA817
CAE"
C"8110
CA818
CASIa
84 PIN PGA
CASOD
DINO
DIN2
DINS
DI"
DING
DIN8
0lN7
CIN1
elNO
CIN3
CI . .
CIN2
CIN5
DOUT17
DOUT18 DOUn
VCC
DINl
OND
DOUT16
TOP VIEW
#
CIN9
HOLD
LD#
CIN7
OND
VCC
A2
EAW
CASl13
CASI11
CIN8
CIN8
CLI(
A1
cs#
AD
CASI1a
CASI14 CA8112
C
D
0
H
A
K
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Z
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a:
11.
CASOO
CAE07
CIN4
CI""
OOUTO
CINS
DOUT1
elH7
DOUT2
CONB
GND
elN9
DOUT3
GND
84 LEAD PLCC
TOP VIEW
Vee
DOUT4
DOUT5
DOU16
HOLD
DOUT7
LD#
Vee
es#
DOUT8
A'
OND
A1
DOUT9
AD
OOU110
EALU
DOUT11
CASI1S
DOUT12
CASI14
DOUT13
CASI13
00U114
CASI12
GND
~
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()
11
~
()
'it
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S~ S~ ~ ~
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~ 12
c
()
()
()
4-41
'iI Qz
i"
HSP48908
Pinouts (Continued)
100 LEAD MQFP
TOP VIEW
ClN1
CIN2
NC
NC
CIN3
ClN4
CINS
CIN6
ClN7
CINS
CINS
GND
GND
GND
CASes
NC
CAS06
CAS07
DOUTO
DOUT1
DOUT2
GND
GND
DOUT3
DOUT4
DOUTS
DOUT6
DOUT7
ClK
vee
Vee
Vee
Vee
Doura
HOLD
LOt
Cst
GND
GND
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
GND
GND
DOUT15
DOUT16
A2
A1
AO
EAlU
CASI15
CASI14
CASI13
CASI12
NC
NC
CASI11
4·42
HSP48908
Block Diagram
CASOO-7
CINO-9
---""'T-""",",,~
FRAME#--.
~
RESET#--.
oUi
OE#--'
-(.)
Z
wen
QW
>0
a:
11.
CASIO-15
B
z!
3
AO-2 - - - - . , . . ...
DOUTO-'.
ADDRESS
DECODER
LD #
CS#
CLK ~ CLOCK
HOLD~
INTERNAL CLOCK
GEN
4-43
HSP48908
Pin Descriptions
NAME
PlCCPIN
VCC
21,42,63,64
TYPE
The +5V power supply pins.
are recommended.
DESCRIPTION
GND
19,48,54, 61
69,76,82
The device ground.
ClK
20
I
Input and System clock. Operations are synchronous with th? rising edge of
this clock signal.
DINO-7
1-8
I
Pixel Data input bus. This bus is used to provide the 8-bit pixel input
data to the HSP48908. The data must be provided in a synchronous fashion,
and is latched on the rising edge of the ClK signal.
CINO-9
9-18
I
Coefficient Input bus. This input bus is used to load the Coefficient
Mask register(s), the Initialization register, the Row Buffer length register
and the AlU microcode. It may also be used to provide a second operand input
to the AlU. The definition of the CINo-9 bits is defined by the register
address bits AO-2. The CINO-9 data is loaded to the addressed register
through the use of the CS# and lD# inputs.
DOUTO-19
49-53, 55-60,
62,64-68,
70-72
0
Output Data bus. This 20-Bit output port is used to provide the convolution
result. The result is the sum of products of the input data samples and their
corresponding coefficients. The Cascade inputs CAS10-15 may also be added to
the result by selecting the appropriate cascade mode in the Initialization
register.
CAS10-15
29-41 , 43-45
I
Cascade Input bus. This bus is used for cascading multiple HSP48908s to
allow convolution with larger kernels or row sizes. It may also be used
to interface to external row buffers. The function of this bus is
determined by the Cascade Mode bit (Bit 0) of the Initialization register.
When this bit is set to a '0', the value on CAS10-15 is left shifted and
added to DOUTO-19. The amount of the shift is determined by bits 7-8 of the
Initialization register. While this mode is intended primarily for cascading,
it may also be used to add an offset value, such as to increase the brightness
of the convolved image.
0.1~F
capacitors between the VCC and GND pins
When the Cascade mode bit is set to a '1', this bus is used for interfacing to
external row buffers. In this mode the bus is divided into two 8-bit busses
(CASI0-7 and CASI8-15), thus allowing two additional pixel data inputs. The
cascade data Is sent directly to the internal multiplier array which allows for
larger row sizes without using multiple HSP48908s.
CASOO-7
73-75,77-81
0
Cascade Output bus. This bus is used primarily during cascading to handle
larger frames and/or kernel sizes. This output data is the data on DINO-7
delayed by twice the programmed internal row buffer length.
FRAME#
46
I
Frame# is an asynchronous new frame or vertical sync input. A low on this
input resets all internal circuitry except for the Coefficient, AlU, AMC,
EOR and INT registers. Thus, after a Frame# reset has occurred, a new frame
of pixels may be convolved without reloading these registers.
EAlU
28
I
Enable AlU Input. This control line gates the clock to the AlU Register.
When it is high, the data on CINO-7 is loaded on the next rising clock
edge. When EAlU is low, the last value loaded remains in the AlU
register.
HOLD
22
I
The Hold Input is used to gate the clock from all of the internal circuitry of
the HSP48908. This signal is synchronous, is sampled on the rising edge of
ClK and takes effect on the following cycle. While this signal is active (high),
the clock will have no effect on the HSP48908 and internal data will remain
undisturbed.
RESET#
47
I
Reset is an asynchronous signal which resets all internal Circuitry of the
HSP48908. All outputs are forced low in the reset state.
OE#
83
I
Output Enable. The OE# input controls the state of the Output Data bus
(DOUTO-19). A lOW on this control line enables the port for output. When
OE# is HIGH, the output drivers are in the high impedance state. Processing
is not interupted by this pin.
4-44
HSP48908
Pin Descriptions
(Continued)
NAME
PLCCPIN
TYPE
DESCRIPTION
AO-2
25-27
I
Control Register Address. These lines are decoded to determine which register
in the control logic is the destination for the data on the CINO-9 inputs.
Register loading is controlled by the AO-2, LD# and CS# inputs.
LD#
23
I
Load Strobe. LD# is used for loading the internal registers of the HSP48908.
When CS# and LD# are active, the rising edge of LD# will latch the CINO-7 data
into the register specified by AO-2.
CS#
24
I
Chip Select. The Chip Select input enables loading of the internal registers.
When CS# is low, the AO-2 address lines are decoded to determine the meaning
of the data on the CINO-7 bus. The rising edge of LD# will then load the
addressed register.
Functional Description
The HSP48908 two-dimensional convolver performs
convolution of 3 x 3 filter kernels. It accepts the image data
in raster scan, non-interlaced format, convolves it with the
filter kernel and outputs the filtered image. The input and filter kernel data are both 8-bits, while the output data is 20bits to prevent overflow during the convolution operation.
The HSP48908 has internal storage for two 3 x 3 filter kernels and is capable of buffering two 1024 x 8-bit rows for
true single chip operation at video frame rates. An 8-bit ALU
in the input pixel data path allows the user to perform arithmetic and logical operations on the input data in real time
during the convolution. Multiple devices can also be cascaded together for larger kernel convolution, larger frame
sizes and increased precision.
Image data is input to the convolver via the DINO-7 bus. The
data is then operated on by the ALU, stored in the row
buffers and convolved with the 3 x 3 array of filter coefficients. The resultant output data is then latched into the output register. The row buffers are preprogrammed to the
length of one row of the input image to enable the user to
input the image data one pixel at a time in raster scan format
without having to provide external storage.
Initialization of the convolver is done using the CINO-7 bus
to load configuration data, such as the filter kernel(s) and
the length of the row buffers. The address lines AO-2 are
used to address the internal registers for initialization. The
configuration data is loaded using the AO-2, CINO-9, CS#
and LD# controls as address, data, chip select and write
enable, respectively. This interface is compatible with
standard microprocessors without the use of any additional
glue logic.
Multiple convolvers can also be cascaded together for
kernel sizes larger than 3 x 3 and for convolution on images
with row lengths longer than 1024 pixels. The maximum
kernel size is dependent upon the magnitude of the image
data and the coefficients in a given application; care must
always be taken with very large kernel sizes to prevent
overflow of the 20-bit output.
Data Input
Image data coming into the 2D Convolver passes through a
programmable pipeline delay before being sent to the ALU.
The amount of delay (1 to 4 clock cycles) is set in the
initialization register during configuration setup (See
Control Logic). Delays greater than one are used primarily in
cascading multiple HSP48908s to align data sequences for
proper output (See Operation).
4-45
TABLE 1. ALU SHIFT OPERATIONS
ALU MICROCODE REGISTER
REGISTER BIT
0
0
0
8
1
1
1
0
0
1
1
0
0
1
1
1
0
>0
11.
The on-chip ALU provides the user with the capability of
performing pixel point operations on incoming image data.
Depending on the instruction in the ALU microcode register,
the ALU can perform anyone of 19 arithmetic and logical
functions, and shift the resulting number left or right by up
to 3 bits. Tables 1 and 2 show the available ALU functions
and the 10-bit associated microcode to be loaded into the
ALU microcode register. Note that the shifts take place on
the output of the ALU and are completely independent of
the logical or arithmetic operation being performed. The first
input (A) of the ALU is taken from the pixel input bus
(DINO-7). The second input (B) is taken from the ALU
Register. The ALU Register is loaded via the CINO-7 bus
while the EALU control line is valid (see EALU).
9
-0
a:
Arithmetic Logic Unit
Filtered image data comes out of the convolver over the
DOUTO-19 bus. This output bus is 20-bits wide to provide
room for growth during the convolution operation. The
20-bit bus will allow the use of up to 4 x 4 kernels (using
multiple 48908's) without overflow. However, in practical
applications, much larger kernel sizes can be implemented
without overflow since the filter coefficients are typically
much smaller than 8-bit full scale values. DOUTO-19 is also
a registered, three state bus to facilitate cascading multiple
chips and to allow the HSP48908 to reside on a standard
microprocessor system bus.
CJ
z
00
wen
QW
7
0
1
0
1
0
1
0
1
OPERATION
No Shift (Default)
Shift Right 1
Shift Right 2
Shift Right 3
Shift Left 1
Shift Left 2
Shift Left 3
Not Valid
HSP48908
represented by the equation Q = D(n-r), where Q is the row
buffer output, D is the buffer input, n is the current clock
cycle and r is the preprogrammed row length of the input
image. Since the two buffers are connected in series, the
data at the cascade outputs (CASOO-7) is delayed by two
row delays and may be used for cascading multiple
convolvers for larger kernel sizes and/or row lengths. The
programmable row buffers can also be bypassed by
selecting the appropriate cascade mode in the initialization
register. This mode allows the use of external row buffers
for convolving with row lengths longer than 1024 pixels.
TABLE 2. ALU PIXEL OPERATIONS
REGISTER BIT
6
5
4
3
2
1
0
OPERATION
0
0
0
0
0
0
0
Logical (00000000)
1
1
1
1
0
0
0
Logical (11111111)
0
0
1
1
0
0
0
Logical (A) (Default)
0
1
0
1
0
0
0
Logical (B)
1
1
0
0
0
0
0
Logical (A#)
1
0
1
0
0
0
0
Logical (B#)
0
1
1
0
0
0
1
Arithmetic (A + B)
1
0
0
1
0
1
0
Arithmetic (A - B)
1
0
0
1
1
0
0
Arithmetic (B - A)
0
0
0
1
0
0
0
Logical (AAND B)
0
0
1
0
0
0
0
Logical (AAND B#)
0
1
0
0
0
0
0
Logical (A# AND B)
0
1
1
1
0
0
0
Logical (A OR B)
1
0
1
1
0
0
0
Logical (A OR B#)
1
1
0
1
0
0
0
Logical (A# OR B)
1
1
1
0
0
0
0
Logical (A NAND B)
1
0
0
0
0
0
0
8-Bit Multiplier Array
The multiplier array consists of nine a x a multipliers. Each
multiplier forms the product of a filter coefficient with a
corresponding pixel in the input image. Input and coefficient
data may be in either two's complement or unsigned integer
formal The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution
operation as shown below:
INPUT DATA
FILTER KERNEL
Logical (A NOR B)
P1
P2
P3
ABC
P4
P5
P6
DEF
P8
P9
GHI
0
1
1
0
0
0
0
Logical (A XOR B)
1
0
0
1
0
0
0
Logical (A XNOR B)
P7
OUTPUT =
EALU
The EALU control pin enables loading of the ALU Register.
While the EALU line is high, the data on CINO-7 is latched
into the ALU Register on the rising edge of CLK. When
EALU goes low, the current value in the ALU register is held
until EALU is again asserted. Note that the ALU loading
operation makes use of the CINO-7 inputs, but is
completely independent of CS# and LD#. Therefore, in
order to prevent overwriting an internal register, care must
be taken to ensure that CS# and LD# are not active during
an EALU cycle.
(AxP1)+ (BxP2)+ (CxP3)
+ (DxP4)+ (ExP5)+ (FxP6)
+ (G x P7) + (H x P8) + (I x P9)
Control Logic
The control logic (Figure 1) contains the ALU Microcode
Register, the Initialization Register, the Row Length
Register, and the Coefficient Registers. The control logic is
updated by placing data on the CINO-9 bus and using the
AO-2, CS# and LD# control lines to write to the addressed
register (see Address Decoder). All of the control logic
registers are loaded with their default values on RESET#,
and are unaffected by FRAME#.
Programmable Row Buffers
The programmable row buffers are used for bUffering raster
input data for the convolution operation. They can be
thought of as programmable shift registers which can each
store up to 1024 a-bit values, thus delaying each pixel by
up to 1024 clock cycles. Functionally, each row buffer can
be represented as a set of registers connected as a 1024 x
a-bit serial shift register. The output of each buffer can be
ALU Microcode Register
The ALU microcode register is used to store the command
word for the ALU. The ALU command word is a 1O-bit
instruction divided into two fields: the lower 7 bits determine
the ALU operation and the upper 3 bits specify the number
of shifts which occur. The ALU command words are defined
in Tables 1 and 2 (See ALU section).
4·46
HSP48908
AO -2
ENCR1#
3
/
ENCRO#
CAS #
CR1#
CRO#
ADDRESS
DECODE
LD
# __~__
CS
#--""'--'--'
LMC#
EOR#
10
C INO -9
ALU
MICROCODE
ALU MICROCODE REGISTER
lAM C)
I
LMC#
8
INITIALIZATION REGISTER
liNT)
INITIALIZATI ON
DATA
I
CAS#
10
ROW
LENGTH Ir)
ROW LENGTH REGISTER
IRLR)
I
EOR#
COEFFICIENT
REGISTER 0
C RO#
f--Ilo
E1 EI
H
0
I
~
I
.!
I
C R1#
"'----
ENC
R1#----=DENCRO#-R
f..I
I,
·-1
Go
,E-I
Fa if"
I
Eo E
I
r: r: ..:
I
H
EI
G
1
I
I
E-I F 1 E-I
I ECo
Do
I
~
I
~C
"I
I
D,·
~B
I
C,
COEFFICIENT
REGISTER 1
FIGURE 1_ CONTROL LOGIC BLOCK DIAGRAM
4-47
I
Ao
rl
CJ
z
I
oUi
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wtn
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Q.
I
E,
I
if" Bo if"
•
B,
I
I
E-I A, E-I
HSP48908
Initialization Register
Row length Register
The initialization register is used to appropriately configure
the convolver for a particular application. It is loaded
through the use of the CINO-7 bus along with the CS# and
lD# inputs. Bit 0 defines the type of cascade mode to be
used; Bits 1 and 2 select the number of delays to be
included in the input pixel data path; Bits 3 and 4 define the
input and coefficient data format; Bits 5 and 6 determine the
type of rounding to occur on the DOUTO-19 bus; Bits 7 and
8 define the shift applied to the cascade input data. The
complete definition of the initialization register bits is given
in Table 3.
The row length register is used to store the programmed
number of delays for the internal row buffers.
The
programmed delay is set equal to the row length (r) of the
input image. The input pixel data is stored in the row buffers
to allow corresponding pixels of adjacent rows to be
synchronously sent to the mutiplier array for the convolution
operation. The row length register is programmable with
values from 0 to 1023, with 0 defined as a row length of
1024. Row lengths of 1 or 2 lead to meaningless results for
a 3 x 3 kernel convolution, while a row length of 3 defines a
1 x 9 filter (See Operation section). The Row Length register
is written through the use of AO-2, CS# and lD#. Once the
row length register has been loaded, the convolver must be
reset before a new row length can be entered, or else the
new value will be ignored. After RESET# returns high, the
user has 1024 cycles of ClK to load the Row length Register. After 1024 ClK cycles, the Row length Register is automatically set to 0 (row length = 1024) and further writes to
this register are ignored.
TABLE 3. INITIALIZATION REGISTER DEFINITION
INITIALIZATION REGISTER
BIT 0
FUNCTION
=CASCADE MODE
0
Multiplier input from Internal row buffers
1
Multiplier input from external buffers
2BIT1
0
0
FUNCTION
=INPUT DATA DELAY
No data delay registers used
0
1
One data delay register used
1
0
Two data delay registers used
1
1
Three data delay registers used
BIT3
FUNCTION
=INPUT DATA FORMAT
0
Unsigned integer format
1
Two's complement format
BIT4
FUNCTION
=COEFFICIENT DATA FORMAT
0
Unsigned integer format
1
Two's complement format
6BIT5
FUNCTION
=OUTPUT ROUNDING
0
0
No Rounding
0
1
Round to 16 bits (i.e. DOUT19-4)
1
0
Round to 8 bits (i.e. DOUT19-12)
1
1
Not Valid
8BIT7
FUNCTION
=CASIO-15 INPUT SHIFT
0
No Shift
0
1
Shift CASIO-15 left two
1
0
Shift CAS10-15 left four
1
1
Shift CASIO-15 left eight
0
Coefficient Registers (CREGO, CREG1)
The control logic contains two coefficient register banks,
CREGO and CREG1. Each of these register banks is capable of storing nine 8-bit filter coefficient values (3 x 3 Kernel). The output of the registers are connected to the coefficient input of the corresponding multiplier in the 3 x 3 multiplier array (designated A through I). The register bank to be
used for the convolution is selectable by writing to the
appropriate address (See address decoder). All registers in
a given bank are enabled simultaneously, and one of the
banks is always active.
For most applications, only one of the register banks is
necessary. The user can simply load CREGO after power
up, and use it for the entire convolution operation. (CREGO
is the default register). The alternate register bank allows
the user to maintain two sets of filter coefficients and switch
between them in real time. The coefficient masks are loaded
via the CIN bus by using AO-2, CS# and lD#. The
selection of the particular register bank to be used in
processing is also done by writing to the appropriate
address (See address decoder). For example, if CREGO is
being used to provide coefficients to the multipliers, CREG 1
can be updated at a low rate by an external processor; then,
at the proper time, CREG 1 can be selected, so that the new
coefficient mask is used to process the data. Thus, no clock
cycles have been lost when changing between alternate 3 x
3 filter kernels.
The nine coefficients must be loaded sEquentially over the
CINO-7 bus from A to I. The address of CREGO or CREG1
is placed on AO-2, and then the nine coefficients are written
to the corresponding coefficient register one at a time by
using the CS# and lD# inputs.
4-48
HSP48908
Address Decoder
The address decoder (See Figure 1) is used for writing to
the control logic of the HSP48908. loading an internal
register is done by selecting the destination register with the
AO-2 address lines, placing the data on CINO-9, and
asserting the CS# and lD# control lines. When either CS#
or lD# goes high, the data on the CINO-9 lines is latched
into the addressed register. The address map for the AO-2
bus is shown in Table 4.
While loading of the control logic registers is asynchronous
to ClK, the target register in the control logic is being read
synchronous to the internal clock. Therefore, care must be
taken when modifying the convolver setup parameters
during processing to avoid changing the contents of the
registers near a rising edge of ClK. The required setup time
relative to ClK is given by the specification TlCS. For example, in order to change the active coefficient register from
CREGO to CREG1 during an active convolution operation, a
write will be performed to the address for selecting CREG1
for internal processing (A2-0=110). In order to provide
proper uninterrupted operation, lD# should be deasserted
at least TlCS prior to the next rising edge of ClK. Failure to
meet this setup time may result in unpredictable results on
the output of the convolver for one clock cycle. Keep in
mind tllat this requirement applies only to the case where
changes are being made in the control logic during an active convolution operation. In a typical convolver configuration routine, this specification would not be applicable.
TABLE 4. ADDRESS MAP
CONTROL LOGIC ADDRESS MAP
A2-0
Function
000
Load Row Length Register (RLR)
001
Load ALU Microcode Register (AMC)
010
Load Coefficient Register 0 (CREGO)
011
Load Coefficient Register 1 (CREG1)
100
Load Initialization Register (INT)
101
Select CREGO for Internal Processing
110
Select CREG 1 for Internal Processing
11 1
No Operation
to the convolver output. In this manner, multiple convolvers
can be used to implement larger kernel convolution. When
Initialization Register bit 0 Is a '1', the data on CAS10-15 is
divided into two 8-bit portions and is sent to the 3 x 3
multiplier array (Refer to Block Diagram). This mode of
operation allows the use of external row buffers for
convolution of images with row sizes larger than 1024.
Examples of these configurations are given in the
Operations section of this specification.
The data on the cascade inputs (CASI0-15) can also be left
shifted by 0,2,4, or 8 bits. The amount of shift is determined
by bits 7 and 8 of the Initialization Register (See Table 3).
CAS10-15 is shifted by the speCified number of bits and is
added to the 20-bit output DOUT 0-19. The shifting function provides a method for cascading multiple HSP48908s
and allowing a selectable amount of output growth while
maximizing the resolution of the convolver result.
The cascade inputs can also be used as a simple way to
add an offset to the convolved image. Bit 0 of the
configuration register would be set to '0', and the desired
offset placed on the CAS10-15 inputs. While multiple offets
can be used and changed during the convolution operation,
note that the required data setup and hold times with
respect to ClK (TDS and TDH) must be met.
CJ
Cascade Output
The cascade output lines (CASOO-7) are outputs from the
second row buffer. Data at these outputs is the input pixel
data delayed by two times the preprogrammed value in the
row length register. The cascade outputs are used to
cascade multiple convolvers by connecting the cascade
outputs of one device to the data inputs of another (See
Operation section).
Control Signals
HOLD
The HOLD control input provides the ability to disable
internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of ClK and takes effect during
the following clock cycle (Refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.
Cascade I/O
CLK
Cascade Input
The cascade input lines (CASI0-15) have two primary
functions. The first is used to allow convolutions with kernel
sizes larger than 3 x 3. This can be implemented by
connecting the DOUT bus of one convolver to the cascade
Inputs of another. The second function is for convolution on
images wider than 1024 pixels. This type of operation can
be implemented by using external row buffers to supply the
pixel input data to the CAS10-15 inputs. The cascade input
functions are determined by Initialization Register bit O.
When this bit is set to a '0', the cascade input data is added
HOLD
-~/
\'-----
INTERNAL
CLOCK
4-49
FIGURE 2. HOLD OPERATION
z
00
w(I)
QW
-(,)
>0
a:
a..
HSP48908
RESET#
to clear the row buffers, multiplier input latches and
DOUTO-19 registers between frames.
The setup for Single chip operation is straightforward. After
reset, the convolver is configured for row lengths of 1024
pixels, no input data delay, no AlU pixel point operations,
no output rounding, and an unsigned input format. The user
can change this default setup by loading new values into
the AlU microcode, initialization and row length registers.
RESET# also clears the coefficient registers and CREGO is
selected for internal processing. The user can now load the
coefficients one at a time from A to I via the CINO-7 inputs
and the lD# and CS# control lines.
The RESET# signal initializes all internal flip flops and
registers in the HSP48908. It is an asynchronous signal,
and the convolver will remain in the reset state as long as
RESET# is asserted. On reset, all internal registers are set
to zero or their default values, and all outputs are forced low.
Following a reset, the default values in the internal registers
will define the following mode of operation: internal row
buffers used, line length'" 1024, no input data delay, logical
A operation: output of AlU '" A input (DINO-7) output rounding and unsigned input data format.
The convolver can be reset at any time, but must be reset
before updating the Row length register in order to provide
proper operation. After RESET# returns high, the user has
1024 cycles of ClK to load the Row length Register. After
1024 ClK cycles, the Row length Register is automatically
set to 0 (row length", 1024) and further writes to this register are ignored.
Multiple filter kernels can also be used on the same image
data using the dual coefficient registers CREGO and
CREG1. This type of filtering is used when the characteristics of the input pixel data change over the image in such a
way that no single filter produces satisfactory results for the
entire image. In order to filter such an image, the characteristiCS of the filter itself must change while the image is being
processed. The HSP48908 can perform this function with
the use of an external processor. The processor is used to
calculate the required new filter coefficients, loads them into
the coefficient register not in use, and selects the newly
loaded coefficient register at the proper time. The first
coefficient register can then be loaded with new coefficients
in preparation for the next change. This can be carried out
with no interruption in processing, provided that the new
register is selected synchronous to the convolver ClK
signal.
FRAME#
This FRAME# input initializes all internal flip flops and
registers except for the coefficient, AlU, AlU microcode,
row length, and initialization registers. It is used to reset the
convolver between video frames and eliminates the need to
re-initialize the entire convolver or reload the coefficients.
FRAME# is an asynchronous input and may occur at any
time. However, it must be deasserted at least TFS ns prior to
the rising clock edge that is to begin operation for the next
frame. While FRAME# is asserted, the registers and flipflops will remain in the reset state.
The HSP48908 can also operate as a one dimensional 9 tap
FIR filter by programming the row buffer length register with
a value of 3 and setting the initialization register bit 0 to a '0'.
This configuration will provide for nine sequential input
values in the input to be multiplied by the coefficient values
in the selected coefficient register and provide the proper
filtered output. The equation for the output then becomes:
Operation
The HSP48908 has three basic modes of operation: single
chip mode, operation with external row buffers and multiple
devices cascaded together for larger convolution kernels
and/or longer row lengths. The mode of operation is defined
by the contents of the initialization register, and can be
modified at any time by a microprocessor or other external
means.
00UTn =
Ax On-8 + B x 0n-7 + C x On-6 + 0 XOn-5
+ E x On-4 + F xOn-3 + G x On-2 + H x 0n-1
+lxOn
Single Chip Mode
IMAGE _ _ _...8~..
DATA
A single HSP48908 can be used to perform 3 x 3 convolution on 8-bit image data with row lengths up to 1024. A
block diagram of this configuration is shown in Figure 3. In
this mode of operation, the image data is input into the
DINO-7 bus in a raster scan order starting with the upper
left pixel. To perform the convolution operation, a group of
nine image pixels is multiplied by the 3 x 3 array of filter
coefficients and their products are summed and sent to the
output. For the example in Figure 3, the pixel value in the
output image at location (m, n) is given by:
1---,....0_ _ FILTERED
CLK-
INITIAUZATION
DATA
T
FILTER KERNEL
POUT(m,n)
IMAGE
HSP48908
(AxPm-1,n-1) + (BxPm-1 n) + (CXPm-1 n+1)
+ (FxP m n~l)
+ (ExP m nJ
+ (OxPm n-1)
+ (GxPm:r1,n-1) + (HxPm'+l,n) + (IXPm~1,n+1)
This process is continually repeated until the last pixel of the
last row of the image has been input. It can then start again
with the first row of the next frame. The FRAME# pin is used
ABC
OEF
GHI
IMAGE DATA
Pm-1, n-1
Pm,n-1
Pm+1,n-1
Pm-1,n
Pm,n
Pm+1,n
Pm-1,n+1
Pm,n+1
Pm+1,n+1
FIGURE 3. 3 x 3 KERNEL ON AN 8-BIT, 1024 x N IMAGE
4-50
HSP48908
Use Of External Row Buffers
External row buffers may be used when frames with row
sizes larger than 1024 pixels are desired. To use the
HSP48908 in this mode, the cascade mode control bit (bit
0) ofthe initialization register is set to '1' to allow the data on
the cascade inputs CAS10-15 to go to the multiplier array.
The inputs of one external row buffer (such as the
HSP9500) are connected to the input data in parallel with
the DINO-7 lines of the convolver; and its outputs are connected to the CASI0-7 inputs (See Figure 4). A second external row buffer is connected between the outputs of the
first row buffer and the CAS18-15 inputs of the convolver.
The convolution operation can then be performed by the
HSP48908 in the same manner as the single chip mode.
The row length in this configuration Is limited only by the
maximum length of the external row buffers. Note that when
using the convolver in this configuration, the programmable
input data delays and ALU will only operate on the data
entering the DINO-7 inputs (i.e. the bottom row of the 3 x 3
sum of products). If higher order filters or pixel point
operations are required when using external row buffers,
these functions must be implemented externally by the user.
.
FILTERED
OOUTO - 1.1-.....,<_ _ IMAGE
DATA
HSP48908
accomplished just as before. However, the 3 x 3 mask is
divided into two portions for proper convolution output as
fOllows: Convolver #1 = DEFOOOGHI and Convolver #2 =
ABCOOOOOO.
The same configuration can be used to perform 3 x 5
convolution on a 1K x N frame simply by setting up the
coefficients of the convolvers to impiement the 3 x 5 mask
as indicated below:
3x5FILTER
KERNEL
COEFFICIENT MASKS
CONVOLVER #1 CONVOLVER #2
ABC
DEF
GHI
JKL
MNO
GHI
JKL
MNO
•
,
DINO -7
DOUTO ·lD
FIGURE 4. USING EXTERNAL ROW BUFFERS WITH THE
HSP48908
..
f--
CASOo-7
CAstO-IS
Multiple HSP48908s are capable of being cascaded to
perform convolution on Images with row lengths longer than
1024 pixels and with kernel sizes larger than 3 x 3. Figure 5
illustrates the use of two HSP48908s to perform a 3 x 3
kernel convolution on a 2K x N frame. In this case, the
cascade mode control bit (Bit 0) of both initialization
registers are set to a '0'. The loading of the coefficients is
,
DINO-7
..
f--
DEF
ABC
000
000
000
GHI
IMAGE
D::;:A:.:;TA:;:""-l--oIOINO -1
,-.----"'1
...---=--IDINo-7
-
5X5
FILTER KERNEL
FILTERED
~~~E
20
ABCDE
FGHIJ
KLMNO
PORST
UVWXY
DOUTO -18
HSP48906
HSP48908
#1
#2
CASOO-7
CASIO-16
CASIO·18
CASOO-7
CASIO-16
FIGURE 5. 3 x 3 KERNEL CONVOLUTION ON A 2K x N IMAGE
DINO-7
~l
IMAGE
TERED
HSP48908
#4
#2
CASOO·7
a:
a..
r--
CASlO -1.
DOUTO-la
HSP48908
COEFFICIENT MASKS
CONVOLVER #1
CONVOLVER #2
>0
01NO-7
CASOO·7
'----
, ·3
DOUTO-1S
WCI)
#3
f-
f-
DATA
CASOO-7
~
CASlO -115
CONVOLVER
COEFFICIENT MASKS
OKL
OPO
OUV
OAB
OFG
MNO
RST
WXY
CDE
HIJ
000
000
FIGURE 6. 5 x 5 KERNEL CONVOLUTION ON A 1K x N IMAGE
4-51
z
QW
HSP48908
#1
CJ
oui
-(,)
DOUTO -19
HSP48908
Cascading Multiple HSP48908's
ABC
DEF
GHI
000
In addition to larger frames, larger kernels can also be
addressed through cascadability. An example of the
configuration for a 5 x 5 kernel convolution on a 1 K x N
frame is shown in Figure 6. Note that in this configuration,
convolver #2 incorporates a 3 clock cycle delay (z -3) and
convolvers 3 and 4 Incorporate 2 clock cycle delays (z -2)
at their pixel inputs. These delays are required to ensure
proper data alignment in the final sum of products output of
the cascaded convolvers. The number of delays required at
the pixel input is programmable through the use of bits 1
and 2 of the initialization register (Refer to Table 3).
IMAGE
DATA
3x 3 FILTER
KERNEL
ABC
DEF
HSP48908
In any of the cascade configurations, only 16 bits of the 20bit output (DOUTO-19) can be connected to the 16 cascade
inputs (CASI0-15) of another convolver. Which 16 bits are
chosen depends upon the amount of growth expected at
the convolver output. The amount of growth is dependent
on the input pixel data and the coefficients selected for the
convolution operation. The maximum possible growth is
calculated in advance by the user, and the convolvers are
set up to appropriately shift the cascade input data through
the use of bits 7 and 8 of the initialization register (See Cascade 110). Refering to Figure 6, if the maximum growth out
of convolver #1 extends into bit 16 or 17, then DOUT2-17
are connected to the cascade inputs of convolver #3, which
is programmed to shift the input data left by two bits.
Likewise, if the data out of convolver #3 grows into bit 18 or
19, then DOUT4-19 are connected to the CAS10-15 inputs
of convolver #2, which is programmed to shift the input left
by 4 bits.
Cascading For Row Sizes Larger Than 1024
Combining large images with large kernels is accomplished
by implementing external row buffers, external data delay
registers and external adders. Figure 7 illustrates a circuit
for implementation of a 5 x 5 convolution on a 2K x N image.
The 5 x 5 coefficient mask is again distributed among the
four HSP48908's. The width of the DOUT path to be used in
this case is dependent on the amount of resolution required
and the amount of growth expected at the output.
Frame Rate
The total time to process an image is given by the formula:
T=RxC/F
where:
T = time to process a frame
R = number of rows in the image
C = number of pixels in a row
F = clock rate of the HSP48908
Note that the size of the kernel does not enter into the
equation. Convolvers cascaded for larger kernels or larger
frame sizes, as in the examples shown, process the image
in the same amount of time as a single HSP48908
convolving the image with a 3 x 3 kernel. Therfore, there is
no performance degradation when cascading multiple
HSP48908s.
IMAGE
DATA
FILTERED
IMAGE
DATA
FIGURE 7. 5 x 5 KERNEL CONVOLUTION ON A 2K x N IMAGE
4-52
Specifications HSP48908
Absolute Maximum Ratings
Supply Voltage .••••....•.•••.•.•.........••.........•....••...••..••...•.••••••••••••••••..••.•••..•••••••••.•. +8.0V
Input, Output or I/O Voltage Applied ....•...•...................•....•.......................•... GND -0.5V to VCC +0.5V
Storage Temperature Range ...•....••••...•.••••.••...•••....•...••..................•.•..•...•...••. -650C to +1500C
Maximum Package Power Dissipation @ 700C ..•••............•......•......... 1.67W (MQFP), 2.46W (PLCC), 3.04W (PGA)
Thermal Impedance Junction To Case (6ic! ........•.........•.•.•••....•.....•..•••..••• 1 O.OoC/W (PLCC), 7.7 0 C/W (PGA)
Thermal Impedance Junction To Ambient (6ia) ................•...•••.... 480 C/W (MQFP), 32.50 C/W (PLCC), 35.00 C/W (PGA)
Gate Count . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . • . . . • • . • . . . . . • . . . . . . • . . . . • • • . . . • . . • • • . . . • • . . . . • . . • . . . •. 190,000 Transistors
Maximum Junction Temperature (TJ) •.....•..•••..•••..••....••...••.•..•...•...•••...• 1500C (PLCC, MQFP), 1750C (PGA)
Lead Temperature (Soldering, Ten Seconds) ..•••.......•••...•...••• " •.•...•..••.....•.•••••.•••••.•.•••.••.••. +3000 C
ESD Classification ...............•..........•............•....••....•....•.......•...........................•• Class 1
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range .......................•.............•..............•.............•........•. +4.75V to +5.25V
Operating Temperature Range .......••........••....•........•............•.....•....•...•..••....••..••• OoC to + 700C
D.C. Electrical Specifications (Vcc = 5.0V ± 5%, TA = Ooc to +700 C)
PARAMETER
Logical One Input Voltage
SYMBOL
MIN
MAX
UNITS
TEST CONDITIONS
VIH
2.0
-
V
VCC=5.25V
"
Z
00
W(/)
VIL
-
0.8
V
VCC= 4.75V
High Level Clock Input
VIHC
3.0
-
V
VCC= 5.25V
OW
>0
Low Level Clock Input
VILC
-
0.8
V
VCC= 4.75V
D.
Output HIGH Voltage
VOH
2.6
-
V
10H = -40011A, VCC = 4.75V
Output LOW Voltage
VOL
-
0.4
V
10L = +2.0mA, VCC = 4.75V
II
-10
10
I1A
VIN = VCC or GND, VCC = 5.25V
Logical Zero Input Voltage
Input Leakage Current
10
-10
10
I1A
VOUT=VCCorGND
Standby Power Supply Current
ICCSS
-
500
I1A
VIN = VCC or GND, VCC = 5.25V,
Outputs Open
Operating Power Supply Current
ICCOp
-
140
mA
f= 20MHz, VIN =VCC orGND
Note 1
I/O Leakage Current
Capacitance (TA = +25 0 C, Note 2)
SYMBOL
MIN
MAX
UNITS
Input Capacitance
CIN
-
10
pF
Output Capacitance
Co
-
12
pF
PARAMETER
TEST CONDITIONS
FREQ = 1 MHz, VCC = Open, all measurements
are referenced to device ground.
NOTES: 1. Power supply current is proportional to operating frequency.
Typical rating for ICCOp is 7.0mA/MHz.
2. Not tested, but characterized at initial design and at major
process/design changes.
CAUTION: These devices are sensitIVe to electrostatic discharge. Proper Ie handling procedures should be followed.
4-53
-(,)
a::
Specifications HSP48908
A.C. Electrical Specifications (VCC = 5.0V ± 5%. TA = ooc to +700 C)
-32 (32M Hz)
PARAMETER
-20 (20M Hz)
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
TCYCLE
31
TpWH
12
-
50
Clock Pulse Width High
20
-
Clock Pulse Width Low
TpWL
13
-
20
-
Data Input Setup Time
TDS
13
14
Data Input Hold Time
TDH
0
-
Clock to Data Out
Clock Period
ns
ns
ns
0
-
ns
TOUT
-
16
-
22
ns
Address Setup Time
TAS
13
-
13
-
ns
Address Hold Time
TAH
0
-
0
ns
TCDS
14
-
16
TCDH
0
LD# Pulse Width
TLPW
12
-
20
-
LD# Setup Time
TLCS
25
-
30
-
TCS
14
-
16
Configuration Data Setup Time
Configuration Data Hold Time
CINO-7 Setup to CLK
CS# Setup To LD#
TCSS
0
TCH
0
0
0
-
TEST
CONDITIONS
ns
ns
ns
ns
Note 1
ns
ns
CS# Hold From LD#
TCSH
0
-
0
-
RESET# Pulse Width
TRPW
31
-
50
-
ns
TFS
21
25
31
TES
12
TEH
0
-
ns
TFPW
-
HOLD Setup Time
THS
11
-
ns
THH
1
-
12
HOLD Hold Time
1
-
ns
Output Enable Time
TEN
-
16
-
22
ns
Output Disable Time
TOZ
-
28
32
ns
Note 5
Output Rise Time
TR
-
6
-
6
ns
From 0.8 to 2.0 V
Note 5
Output Fall Time
TF
-
6
-
6
ns
From 2.0 to 0.8 V
Note 5
CINO-7 Hold Time From CLK
FRAME# Setup To Clock
FRAME# Pulse Width
EALU Setup Time
EALU Hold Time
NOTES: 1. This specification applies only to the case where the HSP48908
is being written to during an active convolution cycle. It must be
met in order to acheive predictable results at the next rising
clock edge. In most applications, the configuration data and
coefficients are loaded asynchronously and the TLCS specifica·
tion may be disregarded.
2. While FRAME#' is an asynchronous signal, it must be
deasserted a minimum of TFS ns pnor to the riSing clock edge
which is to begin loading pixel data for a new frame.
0
50
14
0
ns
ns
Note 2
ns
ns
ns
Note 3
4. A.C. Testing is performed as follows: Input levels (CLK Input) 4.0 and OV.
Input levels (All other Inputs) OV and 3.0V, Timing reference levels
(CLK) = 2.0V. (Others) = 1.SV. Output load per test load Circuit with
CL = 40pF. Output transition is measured atVOH~ 1.5V and VOL.:S.1.5V.
5. Controlled via deSign or process parameters and not directly tested.
Characterized upon initial design and after major process a~d/or design
changes.
3. Transition is measured at ± 200 mV from steady state voltage
with loading as specified in test load cirCUit with CL = 40pF.
CAUTION: These devices are sensitive to electrostatic discharge. Proper Ie handling procedures should be followed.
4-54
HSP48908
Test Load Circuit
r--------------1
1
1
1
1
1
I
1
1
1
1
1
1
1
-INCLUDES STRAY AND 1
JIG CAPACITANCE
1_ _ _ _
EQUIVALENT~IRCUIT _ _ _ _
1
J
SwilCh S1 Open for ICCSB and ICCOp Tests
Timing Waveforms
FUNCTIONAL TIMING
..
...
\
-K
CLK
.
T CYCLE
TpWt
J
f--
TOS
~.-
~
TpWH
TO..r-
\/
\V
OINO -7, CASIO -15
If\.
1\
~TOUTl<
OOUTO -19, CASCO-7
- -----\1
\V
TCS
CINO - 7 (TO ALU REGISTER)
1\
\'----
CLK;=,,,j_''"J
EALU
TCH
/\
THREE STATE CONTROL
EALU TIMING
'--------
"'
4-55
CJ
\
z
OU)
wei)
OW
>0
-C)
~
Q.
HSP48908
Timing Waveforms (Continued)
CONFIGURATION TIMING
~
Tess
7
!------- I\.
.
T LPW
--
-K-
"""''TAS
AO -2
TeSH
TAH
\V
\V
I\.
I\.
TeDS
TeDH
\V
elNO -9
\V
I\,
J\.
SYNCHRONOUS LOAD TIMING
C~~
_ _
LD#~
HOLD TIMING
CLK
HOLD
INTERNAL
CLOCK
FRAME#/RESET# TIMING
CLK
RESET#
FRAME
#
4-56
HSP48908/883
Two Dimensional Convolver
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL-STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Harris HSP4890Bl883 is a high speed Two Dimensional
Convolver which provides a single chip implementation of a
video data rate 3 x 3 kernel convolution on two dimensional
data. It eliminates the need for external data storage through
the use of the on-Chip row buffers which are programmable
for row lengths up to 1024 pixels.
• Single Chip 3 x 3 Kernel Convolution
• Programmable On-Chip Row Buffers
• DC to 27MHz Clock Rate
• Cascadable for Larger Kernels and Images
• On-Chip 8-Blt ALU
• Dual Coefficient Mask Registers, Swltchable In a Single Clock Cycle
• B-Bit Signed or UnSigned Input and Coefficient Data
• 20-Blt Extended Precision Output
• Standard!1P Interface
Applications
• Image Filtering
• Edge Detection
• Adaptive Filtering
Data is provided to the HSP4890Bl883 in a raster scan noninterlaced fashion, and is internally buffered on images up to
1024 pixels wide for the 3 x 3 convolution operation. Images
with larger rows and convolution with larger kernel sizes can
be accommodated by using external row buffers and/or multiple HSP48908I883s. Coefficient and pixel input data are 8bit signed or unsigned integers, and the 2D-bit convolver output guarantees no overflow for kernel sizes up to 4 x 4.
Larger kernel sizes can be implemented however, since the
filter coefficients will normally be less than their maximum 8bit values.
The HSP489081883 is manufactured using an advanced
CMOS process, and is a low power fully static design. The
configuration of the device is controlled through a standard
microprocessor interface and all inputs/outputs are TTL
compatible.
• Real Time Video Filters
Ordering Information
PART NUMBER
There are internal register banks for storing two independent
3 x 3 filter kernels, thus faCilitating the implementation of
adaptive filters and multiple filter operations on the same
data. The pixel data path also includes an on-Chip ALU for
performing real· time arithmetic and logical pixel point operations.
TEMP. RANGE
PACKAGE
HSP48908GM·20/883
·55°C to +125°C
84 Lead PGA
HSP48908GM·27/883
·550 C
to +125°C
84 Lead PGA
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporalion 1994
4-57
File Number
2783.3
CJ
z
00
wtI)
QW
-(,)
>0
IE
HSP489081883
Pinout
HSP489081883 (PGA)
TOP VIEW
11
CASas
DOUTO
DOUT1
GND
DOUTS
DOUT6
DOUT.
10
CAS04
CAS05
CAS07
DOUT2
DOUT4
DOUT8
GND
CAS03
GND
DOUT3
DOUT7
VCC
8
CAS01
CAS02
7
OE#
GND
DOUT10 DOUT12 DOUT13 DOUT15
DOUT11 DOUT14
GND
DOUT17
DOUT16 DOUT18
VCC
DOUT19
GND
CASI1
FRAME
#
CASIO
CASI2
VCC
RESET
#
CASIS
CASI4
CASI3
CASI7
CASI6
CASI10
CASI8
CASIII
84 PINPGA
6
DlN1
CASOO
DINO
TOP VIEW
5
DlN2
DlN3
DlN4
4
DINS
DlN6
3
DlN7
CIN1
2
ClNO
ClN3
ClN4
CIN2
CIN5
A
B
CINII
HOLD
lD#
CIN7
GND
VCC
A2
EAlU
CASI13
CASI11
CIN6
ClN8
ClK
A1
CS#
AO
CASI15
CASI14 CASl12
C
D
E
F
G
H
J
4-58
K
l
Specifications HSP48908/883
Absolute Maximum Ratings
Reliability Information
Supply Voltage •......•.•...•...•.••....•••.•••••...••• +8.0V
Input, Output or I/O Voltage Applied •..• GND-0.5V to VCC+0.5V
Storage Temperature Range ...••.•••....•..• -650C to +1500C
Junction Temperature •••.•••••......••.....•.. " •.••. +1750 C
Lead Temperature (Soldering 10 sec) ••...••..•••...... +3000C
ESD Classification •..•••.•..••.....••••.....•••••••••• Class 1
Thermal Resistance
9ja
9jc
CeramicPGAPackage •.•••.•••.••...• 35.0 0C/W 7.70 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package ••...•••••••••.•.•••.••......•. 1.45W
Gate Count.. ..••......•....••.••..••...• 190,000 Transistors
CAUTION:
Absolute maximum ratings Bfe limiting values, applied individually beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
Recommended Operating Conditions
Operating Temperature Range •••.....•••••.••• -550 C to +1250 C
Operating Voltage Range .•••••.....••••...••..• +4.5V to +5.5V
TABLE 1. D.C. ELECmlCAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
UNITS
VCC= 5.5V
1,2,3
-5SOC~TA~+1250C
2.2
-
V
VIL
VCC=4.5V
1,2,3
-5SOC 0
II
VIN = VCC or GND
VCC=5.5V
1,2,3
-550C ::;TA::; +1250 C
-10
+10
pA
Output or I/O
Leakage Current
10
VOUT = VCC or GND
VCC=5.5V
1,2,3
-550C ::;TA ~ +1250 C
-10
+10
pA
Standby Power
Supply Current
Iccss
VIN =VCC orGND
VCC=5.5V
Outputa Open (Note 4)
1,2,3
-550C ~TA ~ +1250 C
-
500
pA
Operating Power
Supply Current
ICCOp
f=20.0MHz
VCC=5.5V
Outputs Open,
(Notes 2,4)
1,2,3
-550C ~TA ::;+1250 C
-
160.0
mA
7,8
-550C~TA::;+1250C
-
-
-
NOTES:
FT
QW
-(,)
Input Leakage Current
Functional Test
Wen
(Notes3,4)
1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency, typical
rating is 8.0mNMHz.
3. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH::: 1.5V, VOL:O 1.5V,
VIHC = 3.4V, and VILC = 0.4V.
4. Loading is a specified in the test load
4-59
circu~ w~h
CL
= 40pF.
a:
Q.
HSP489 08/883
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VCC
= 5.0V ±10%, TA = -550C to +125 0 C (Note 4)
LIMITS
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUP
-27 (27MHz)
-20 (20MHz)
TEMPERATURE
MIN
MAX
MIN
MAX
50
20
UNITS
TDH
9,10,11
-550C~TA~+1250C
0
-
0
-
TOUT
9,10,11
-550C:$.TA~+1250C
-
19
-
28
ns
Address Setup Time
TAS
9,10,11
-550C~TA~+1250C
15
-
15
ns
Address Hold Time
TAH
9,10,11
-550C~TA:$.+1250C
0
-
0
Configuration Data
Setup Time
TCDS
9,10,11
-55°C $.TA~ +1250C
17
-
20
-
ns
Configuration Data
Hold Time
TCDH
9,10,11
-550C~TA~+1250C
0
-
0
-
ns
lD# Pulse Width
TlPW
9,10,11
-550C ~TA:$ +1250 C
15
9,10,11
-550 C:$ TA:$.+1250 C
30
37
-
ns
TlCS
-
20
lD# Setup Time
TCS
9,10,11
-550C.:5.TA~ +1250 C
17
-
20
-
ns
TCH
9,10,11
-550C~TA~
0
-
0
ns
TCSS
9,10,11
-55°C ~TA~ +1250C
0
-
0
0
50
-
30
-
TCYClE
9,10,11
-550C~TA~ +1250C
37
Clock Pulse Width High
TpWH
9,10,11
-55°C ~ TA ~ +1250C
15
Clock Pulse Width low
TpWl
9,10,11
-550C~TA ~ +1250C
15
TDS
9,10,11
-550C~TA~ +1250C
16
Clock Period
Data Input Setup Time
Data Input Hold Time
Clock to Data Out
CIN7-0 Setup to ClK
CIN7-0 Hold from ClK
CS# Setup to lD#
Note 1
+1250C
EAlU Hold Time
TEH
9,10,11
-550 C:$TA:$.+1250C
HOLD Setup Time
THS
9,10,11
-550C:$.TA:$. +1250C
13
HOLD Hold Time
THH
9,10,11
-550C ~TA:$. +1250C
2
-
Output Enable Time
TEN
9,10,11
-550C~TA:$. +1250C
-
19
CS# Hold from lD#
TCSH
9,10,11
-550C::;TA~ +1250 C
RESET# Pulse Width
TRPW
9,10,11
-55 0 C.:5. TA:::+1250C
37
9,10,11
-55°C ~TA~ +1250C
25
TFPW
9,10,11
-550C~TA~+1250C
37
TES
9,10,11
-550 C:$TA < +1250C
15
0
FRAME# Setup to ClK
FRAME# Pulse Width
EAlU Setup Time
TFS
Note 2
Note 3
20
17
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
-
2
-
ns
-
28
ns
50
17
0
ns
ns
ns
ns
NOTES: 1. This specification applies only to the case where the HSP48908!
883 is being written to during an active convolution cycle. It must
3. Transition is measured at ±200mV from steady state voltage with loading as
specified in test load circUit with CL = 40pF.
be met in order to achieve predictable results at the next rising
clock edge. In most applications, the configuration data and
coefficients are loaded asynchronously and the TLeS
4. A.C. Testing is performed as follows: Input levels (ClK Input) 4.0V and OV,
Input levels (All other Inputs) OV and 3.0V, Timing Reference levels
(ClK) = 2.0V. (Others) = 1.SV. Output load per test load circu~ with
Cl = 40pF. Output trans~ion is measured at VOH ~ 1.SV and VOL:;' 1 IN.
specification may be disregarded.
2. While FRAME-#: is an asynchronous signal, it must be deasserted
a minimum of TFS ns prior to the rising clock edge which is to
begin loading pixel data for a new frame.
4-60
HSP48908/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
-27
PARAMETERS
SYMBOL
CONDITIONS
NOTES
-20
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
TA =+25OC
-
10
-
10
pF
Input Capacitance
CIN
VCc=Open,
f= 1 MHz, All
measurements are
referenced to
deviceGND.
1
Output Capacitance
Co
VCC = Open,
f=1MHz,AII
measurements are
referenced to
deviceGND.
1
TA=+250 C
-
12
-
12
pF
Output Disable
Time
Toz
1,2
-550 C :5 TA :5 + 1250 C
-
35
-
40
ns
-
6
-
6
ns
6
-
6
ns
Output Rise Time
TR
From O.SVto 2.0V
1,2
-550 C:5 TA ~ +1250 C
Output Fall Time
TF
From 2.0V to O.SV
1,2
-55OC 0
a:
Q,
PDA
100%
1
Final Test
100%
2,3, SA, SB, 10, 11
GroupA
-
1,2,3, 7,SA, S8, 9, 10, 11
Samples/500S
1,7,9
GroupsC&D
Test Load Circuit
1--------------1
1
1
1
1
1
1
:
1
1
1
1.5V
1
1
1
'INCLUDES STRAY AND 1
JIG CAPACITANCE
1 ____
EQUIVALENT~IRCUIT _ _ _ _
Switch S1 Open for ICCSB and ICCOp Tests
4-61
1
J
HSP48908/883
Burn-In Circuit
11
CAS06
DOUTO
OOUTl
GND
00UT5
DOUT8
DOU18
10
CAS04
CASa5
CAS07
00U12
DOU14
OOUT9
GND
9
CASa3
GND
OOUT3
OOUT7
VCC
8
CASal
CAB02
7
OE#"
GND
OOUT10 OOUT12 OOU113 00U115
DOUTll DOUT14
CASI1
CASOD
DINO
5
DIN2
DIN3
DIN4
4
DINS
DIN8
3
DIN7
CINl
2
CINO
CIN3
CIN"
CIN2
CINS
A
B
OOUT19
GND
FRAME
CASIO
#"
84 PIN PGA
DINl
OOUI17
DOU118 DOU118
VCC
6
GND
TOP VIEW
CAS12
VCC
RESEr
#
CASIS
CASK
CASIa
CASI1
CASIS
CASI10
CASIS
CASI9
CINS
HOLD
lD#"
CIN7
GND
VCC
A2
EAW
CASI13
CASl1l
CINe
CINS
ClK
Al
CS#
AO
CASI15
CASI1'" CASI12
c
o
E
G
H
J
F
K
L
PGA BURN-IN SCHEMATIC
PIN
NAME
CIN2
CINO
DIN7
DIN5
DIN2
DINl
OE
CASO.l
CASO.3
CASO.4
CASO.S
CIN5
CIN3
CINl
DINS
DIN3
CASO.o
GND
CASO.2
GND
CASO.5
POUTO
CIN6
CIN4
DIN4
DINO
VCC
CASO.7
PGA
PIN
BURN-IN
SIGNAL
Al
A2
A3
A4
A5
AS
A7
A8
A9
Al0
All
61
62
63
64
65
6S
67
68
69
610
611
Cl
C2
C5
C6
C7
Cl0
F13
F12
F7
F5
F2
Fl
FlO
VCC/2
VCC/2
Vcct2
Vcct2
F12
F13
F12
F6
F3
VCC/2
GND
Vcct2
GND
Vcct2
VCC/2
F13
F13
F4
FO
VCC
Vcct2
NOTES: 1. Vee12 (2.7V ± 10%) used for outputs only.
2. 47KO (±20%) resistor connected to all pins
except Vee and GND.
3. Vee = 5.5 ± 0.5V.
PIN
NAME
POUTl
CIN8
CIN7
POUT2
GND
CLK
GND
CIN9
POUT3
POUT4
POUT5
Al
VCC
HOLD
POUT7
POUT9
POUTS
CS
A2
LOAD
VCC
GND
POUT8
AO
EALU
POUTll
POUT10
CASI.15
PGA
PIN
BURN-IN
SIGNAL
Cll
01
02
010
011
El
E2
E3
E9
El0
Ell
Fl
F2
F3
F9
FlO
Fll
Gl
G2
G3
G9
Gl0
Gll
Hl
H2
Hl0
Hll
Jl
VCC/2
F14
F12
Vcct2
GND
FO
GND
F14
VCC/2
VCC/2
Vcct2
F13
VCC
F14
VCC/2
Vcct2
Vcct2
F12
F14
Fll
VCC
GND
Vcct2
F12
F8
VCC!2
Vcct2
F7
PIN
NAME
CASI.13
CASI.5
CASI.2
CASI.l
POUT14
POUT12
CASI.14
CASI.ll
CASI.l0
CASI.7
CASI.4
VCC
FRAME
POUT19
POUT16
GND
POUT13
CASI.12
CASI.9
CASI.8
CASI.S
CASI.3
RESET
CASI.O
GND
POUT18
POUT17
POUT15
PGA
PIN
BURN-IN
SIGNAL
J2
J5
J6
J7
Jl0
Jll
Kl
K2
K3
K4
K5
KS
K7
K8
K9
Kl0
Kll
Ll
L2
L3
L4
F5
F5
F2
Fl
VCC/2
Vcct2
F6
F3
F2
F7
F4
VCC
F15
Vcct2
Vcc12
GND
VCC/2
F4
Fl
FO
FS
F3
F1S
FO
GND
VCct2
Vcct2
Vcct2
L5
LS
L7
L8
L9
Ll0
Lll
4. 0.111f (min) capacior between Vee and GND per posHion.
5. FO = 100kHz ± 10%, Fl = FO/2, F2 = F112 ... Fl1 = Fl0/2,
40-60% Duty Cycle.
6. Input VoHage Limits: VIL = oav max .. VIH = 4.5V ± 10%.
4-62
HSP489 08/883
Die Characteristics
DIE DIMENSIONS:
341 x 322 x 19 ± 1 mils
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
METALLIZATION:
Type: Si - AI or Si-AI-Cu
Thickness: akA
WORST CASE CURRENT DENSITY:
2 x 105Ncm2
Metallization Mask Layout
HSP48908/883
'"z Z 0z
13 13 13
-
~
.. co
1/1
..,
z z z z
C'I
~
'"z i
2i 2i 2i 2i c 2i
e~ ~ E
e ei:
Q
E
z >
2i
..,""
0
a
a
u
u
- ..
0
~
;;
0
cO
z ~ <
u
(II
"u
< iii iii
U;G
- - ..~
!:!. !:!.
~e!.
iii iii
< u< u u
u
...
..,
u uu u u
u
-
< u<
u
4-63
u;
:!.
..,,..
::0
~a;
~~
,.. c
... z
< gj"
a: ILl
...
a:
Ci'
:!.
..§
0
Q
CD
- .. ..
0
0
0'
e e e e
...
III
§ § §'" §
c
c
0
C
0
c
QW
-(J
>0
(84) DOUT7
HOLD (22)
Z
iii
w0
(87) DOUT4
(85) DOUT8
VCC (21) 1
o
(88) DOUT3
(88) DOUT5
CLK (20)
CJ
HSP9501
Programmable Data Buffer
January 1994
Features
Description
• DC to 32MHz Operating Frequency
The HSP9501 is a 10-Bit wide programmable data buffer
designed for use in high speed digital systems. Two different
modes of operation can be selected through the use of the
MODSEL input. In the delay mode. a programmable data
pipeline is created which can provide 2 to 1281 clock cycles
of delay between the input and output data. In the data recirculate mode. the output data path is internally routed back to
the input to provide a programmable circular buffer.
• Programmable Buffer Length from 2 to 1281 Words
• Supports Data Words to 10-Bits
• Clock Select Logic for Positive or Negative Edge
System Clocks
• Data Recirculate or Delay Modes of Operation
• Expandable Data Word Width or Buffer Length
• Three-State Outputs
• TTL Compatible Inputs/Outputs
• Low Power CMOS
Applications
• Sample Rate Conversion
• Data Time Compression/Expansion
• Software Controlled Data Alignment
• Programmable Serial Data Shifting
• AudiafSpeech Data Processing Videollmage Processing
VideoRmage Processing
• 1·H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:
•
•
•
•
•
High Resolution Monitor Deiay Line
Comb Filter Designs
Progressive Scanning Display
TV Standards Conversion
Image Processing
The length of the buffer or amount of delay is programmed
through the use of the l1-bit length control input port (LCO10) and the length control enable (lCEN#). An ll-bit value
is applied to the lCO-l0 inputs. lCEN# is asserted. and the
next selected clock edge loads the new count value into the
length control register. The delay path of the HSP9501 consists of two registers with a programmable delay RAM
belween them. therefore. the value programmed into the
length control register is the desired length - 2. The range of
values which can be programmed into the length control register are from 0 to 1279. which in turn results in an overall
range of programmable delays from 2 to 1281.
Clock select logic is provided to allow the use of a positive or
negative edge system clock as the ClK input to the
HSP9501. The active edge of the ClK input is controlled
through the use of the ClKSEl input. All synchronous timing
(I.e. data setup. hold and output delays) are relative to the
clock edge selected by ClKSEL. An additional clock enable
input (ClKEN#) provides a means of disabling the internal
clock and holding the existing contents temporarily. All outputs of the HSP9501 are three-state outputs to allow direct
interfacing to system or multi-use busses.
The HSP9501 is recommended for digital video processing
or any applications which require a programmable delay or
circular data buffer.
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP9501JC-25
OOC to +70oC
44 Lead PLCC
HSP9501JC-32
OOC to +70oC
44 Lead PLCC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
4-64
File Number
2786.3
HSP9501
Pinout
44 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
004
VCC
2
i!llw
8 - 0
o 0 ...J ~ §
~
Oel)
wei)
QW
-(.)
>0
Block Diagram
g:
010-9
MOOSEL-_~"
CLKSEL_I"'"---CLKEN
#
10
11
LC 0 -10
EN#
LCEN
#
o
-1279 DELAYS
------'
OE#
000 -9
4·65
HSP9501
Pin Descriptions
NAME
PIN
NUMBER
VCC
12,34
The +5V power supply pin. A 0.1 J.lF capacitor between the VCC and GND pin is recommended.
GND
13,33
The device ground.
DESCRIPTION
TYPE
Input Clock. This clock signal is used to control the data movement through the programmable
buffer. It is also the signal which latches the input data, length control word and mode select. Input
setup and hold times with respect to the clock must be met for proper operation.
ClK
010-9
27,29-32,
35-39
I
Data Inputs. This 10-bit input port is used to provide the input data. When MODSEl is low, data
on the D10-9 inputs is latched on the clock edge selected by ClKSEL.
DOO-9
7-11,
14-18
0
Data Outputs. This 10-bit port provides the output data from the internal delay registers. Data
latched into the D10-9 inputs will appear at the DOO-9 outputs on the Nth clock cycle, where N is
the total delay programmed.
lCo-10
20-26,
41-44
I
length Control Inputs. These inputs are used to specify the number of clock cycles of delay
between the D10-9 inputs and the DOO-9 outputs. An integer value between 0 and 1279 is placed
on the lCO-1 0 inputs, and the total delay length (N) programmed is the lCO-10 value plus 2. In
order to properly load an active length control word, the value must be presented
to'the lCO-10 inputs and lCEN# must be asserted during an active clock edge selected by
ClKSEL.
lCEN#
6
length Control Enable. lCEN# is used in conjuction with lCO-10 and ClK to load a new length
control word. An 11-bit value is loaded on the lCO-10 inputs, lCEN# is asserted, and the next
selected clock edge will load the new count value. Since this operation is synchronous, lCEN#
must meet the specified setup/hold times with respect to ClK for proper operation.
OE#
19
Output Enable. This input controls the state of the DOO-9 output port. A low on this control line
enables the port for output. When OE# is high, the output drivers are in the high impedance state.
Internal latching or transfer of data is not affected by this input.
MODSEl
40
Mode Select. This input is used to control the mode of operation of the HSP9501. A low on
MODSEl causes the device to latch new data at the 010-9 inputs on every clock cycle, and
operate as a programmable pipeline register. When MODSEl is high, the HSP9501 is in the
recirculate mode, and will operate as a programmable length circular buffer. This control signal
may be used in a synchronous fashion during device operation, however, care must be taken to
ensure the required setup/hold times with respect to ClK are met.
ClKSEl
5
Clock Select Control. This input is used to determine which edge of the ClK signal is used for
controlling all internal events. A low on ClKSEl selects the negative going edge, therefore, all
setup, hold, and output delay times are wHh respect to the negative edge of ClK. When ClKSEl is
high, the positive going edge is selected and all synchronous timing is with respect to the positive
edge of the ClK signal.
ClKEN#
2
Clock Enable. This control signal can be used to enable or disable the ClK input. When low, the
ClK input is enabled and will operate in a normal fashion. A high on ClKEN# will disable the ClK
input and will "hold" all internal operations and data. This control signal may also be used in a
synchronous fashion, however, setup and hold requirements with respect to ClK must be met for
proper device operation. This signal takes effect on the clock following the one that latches it in.
4-66
HSP9501
Functional Description
The HSP9501 is a 1O-bit wide programmable length data
buffer. The length of delay is programmable from 2 to 1281
delays in single delay increments.
Data into the delay line may be selected from the data input
bus (DI0-9) or as recirculated output, depending on the
state of the mode select (MaDSEl) control input.
Mode Select
The MaDSEl control pin selects the source of the data
moving into the delay line. When MaDSEl is low, the data
input bus (DI0-9) Is the source of the data. When MaDSEl
is high, the output of the HSP9501 is routed back to the input to form a circular buffer.
The MaDSEl control line is latched at the input by the ClK
signal. The edge which latches this control signal is determined by the ClKSEl control line. In either case, the
MaDSEl line is latched on one edge of the ClK signal with
the following edge moving data into and through the
HSP9501. Refer to the functional timing waveforms for
specific timing references.
Delay Path Control
The HSP9501 buffer length is programmable from 2 to
1281 data words in one word increments. The minimum
number of delays which can be programmed is two,
consisting of the input and output buffer registers only.
The length control inputs (lCO-10) are used to set the
length of the programmable delay ram which can vary in
length from 0 to 1279. The total length of the HSP9501 data
buffer will then be equal to the programmed value on
lCO-10 plus 2. The programmed delay is established by
the 11-bit integer value of the lCO-10 inputs with lC10 as
the MSB and lCO as the lSB.
For example,
programs a length value of 2 6 + 2 0 = 65. The total length of
the delay will be 65 + 2 or 67 delays.
Clock Select logic
The clock select logic Is provided to allow the use of
positive or negative edge system clocks. The active edge of
the ClK input to the HSP9501 is controlled through the use
of the ClKSEl input.
When ClKSEl is low, the negative going edge of ClK is
used to control all internal operations. A high on ClKSEl
selects the positive going edge of ClK.
Table 1 indicates several programming values. The decimal
value placed on lCO-10 must not exceed 1279. Controlled
operation with larger values is not guaranteed.
Values on lCO-10 are latched on the ClK edge selected by
the ClKSEl control line, when lCEN# is active. lCO-10
and lCEN# must meet the specified setup and hold times
relative to the selected ClK edge for proper device
operation.
All synchronous timing (i.e. setup, hold and output
propagation delay times are relative to the ClK edge
selected by ClKSEL. Functional timing waveforms for each
state of ClKSEl are provided (refer to timing waveforms for
details).
TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES
LC10
LC9
LS8
LC7
LC6
LC5
LC4
LC3
LC2
LC1
LCO
2 10
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
1
1
1
0
1
1
0
118
120
PROGRAMMED
LENGTH
TOTAL
LENGTH
N
0
1
1
0
0
1
0
1
0
0
0
808
810
1
0
0
0
0
0
1
1
0
0
1
1049
1051
1
0
0
1
1
1
1
1
1
1
1
1279
1281
4-67
CJ
z
oui
wei)
QW
-C)
>0
II:
r:a.
Specifications HSP950 1
Absolute Maximum Ratings
Supply Voltage ................................................................................................. +8.0V
Input or Output Voltage Applied ................................................................. GND -0.5V to VCC +0.5V
Storage Temperature Range .......................................................................... -65 0 C to +1500 C
Junction Temperature ......................................................................................... +1500 C
Maximum Package Power Dissipation .............................................................................. 1.7W
6JC ....................................................................................................... 16.4°C/W
6JA •....•••......•.......••.•...•.•....••••.....•....•..•....•••••.•.•..........•.•....•.•..............•. 45.20C/W
Lead Temperature (Soldering, Ten Seconds) ..................................................................... +3000 C
CAUTION: Stresses above those listed in the 'lAbsolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ............................................................................. +4.75V to +5.25V
Operating Temperature Range ............................................................................ OoC to + 700 C
D.C. Electrical Specifications
PARAMETER
(VCC = 5.0V + 5%, TA = Ooc to +70 0 C, Commercial)
SYMBOL
MIN
MAX
UNITS
Logical One Input Voltage
Logical Zero Input Voltage
VIH
VIL
2.0
-
V
-
0.8
V
Output HIGH Voltage
VOH
2.4
-
V
IOH = -4mA VCC = 4.75V
Output LOW Voltage
VOL
II
-
0.4
V
IOL = +4.0mA VCC = 4.75V
-10
10
~A
VIN = GND orVCC VCC = 5.25V
10
-10
10
~A
VOUT=GNDorVCC VCC= 5.25V
Standby Current
ICCSB
-
500
~A
VIN =VCCorGND, VCC = 5.25V,
Note 2
Operating Power Supply Current
ICCOp
-
125
mA
f = 25MHz, VIN = VCC or GND
VCC = 5.25V, Note 1, 2
Input Capacitance
CIN
-
10
pF
Output Capacitance
Co
-
10
pF
FREQ - 1 MHz, VCC - Open,
All measurements are referenced
to device G ND
Input Leakage Current
Output Leakage Current
A.C. Electrical Specifications
(VCC = 5.0V ± 5%, TA = Ooc to +700 C, Commercial), (Note 4)
-25
-32
PARAMETER
TEST CONDITIONS
VCC=5.25V
VCC=4.75V
SYMBOL
MIN
MAX
MIN
MAX
UNITS
TCp
-
40
-
ns
-
15
-
ns
Clock Period
Clock Pulse Width High
TpWH
31
12
Clock Pulse Width Low
TpWL
12
Data Input Setup Time
TDS
10
-
15
-
12
ns
ns
Data Input Hold Time
TDH
2
Output Enable Time
Output Disable Time
TENA
TDiS
-
-
20
24
-
-
25
25
ns
ns
CLKEN# to Clock Setup
TES
10
-
12
-
ns
CLKEN# to Clock Hold
LCO-10 Setup Time
TEH
2
2
-
ns
TLS
10
13
TLH
2
LCEN# to Clock Setup
LCEN# to Clock Hold
TLES
10
MODSEL Setup Time
TLEH
TMS
13
2
10
-
-
ns
LCO-10 Hold Time
-
13
-
ns
MODSEL Hold Time
TMH
2
-
2
-
ns
Clock to Data Out
Output Hold from Clock
TOUT
TOH
TRF
-
16
-
22
4
-
4
-
-
6
-
6
ns
ns
ns
Rise, Fall Time
-
2
NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp is SmA/MHz.
2. Output load per test load circuit with switch open and CL = 40pF.
2
2
TEST
CONDITIONS
ns
Note 3
ns
ns
ns
Note 3
3. Controlled by design or process parameters and not directly
Characterized upon initial design and after major process and/or
changes.
4. A.C. Testing is pertormed as follows: Input levels: OV and 3.0V,
reference levels = 1.5V. Input rise and fall times dnven at 1ns/V,
load CL = 40pF.
4-68
tested.
design
Timing
Output
HSP9501
Test Load Circuit
1-----------,
I
I
I
I
I
I
Switch S1 Open for
ICCSS and ICCOp Tests
I
I
I
I
.~~l~:::C~::~EAND 1 _ _ _
~IRCUI~
EQUIVALENT
__
J
Timing Waveforms
CLK
MOOSEL - - -... 1
010 -9
CJ
z
00
w0
OE#
OW
>0
--------l------.J
-(,)
a:
D.
DO 0-9
FUNCTIONAL TIMING (CLKSEL = LOW)
INTERNAL
CLOCK
CLKEN# TIMING (CLKSEL = LOW)
CLK
It.:
0_8V
_
LCEN#
TRF
LCD -10
LENGTH CONTROL TIMING (CLKSEL
OUTPUT RISE AND FALL TIMES
4·69
=LOW)
HSP9501
Timing Waveforms (Continued)
CLK
MOOSEL
010-9
O~----------------~----------'
000 -9
FUNCTIONAL TIMING (CLKSEL
= HIGH)
INTERNAL
CLOCK
CLKEN# TIMING (CLKSEL
= HIGH)
CLK
LCEN#
LC 0 -10
------'r'-~~'I'----------
LENGTH CONTROL TIMING (CLKSEL
4-70
= HIGH)
OS : ) - - - - - - - 1 5
SIGNAL SYNTHESIZERS
PAGE
SIGNAL SYNTHESIZER DATA SHEETS
HSP45102
12-Bit Numerically Controlled Oscillator. . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . .
5-3
HSP45106
16-Bit Numerically Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
5-10
HSP451061883
16-Bit Numerically Controlled Oscillator. . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . .
5-20
HSP45116
Numerically Controlled Oscillator/Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26
HSP45116/883
Numerically Controlled Oscillator/Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-47
5-1
HSP45102
12-Bit Numerically Controlled Oscillator
January 1994
Features
Description
•
•
•
•
•
•
•
•
•
•
The Harris HSP45102 is Numerically Controlled Oscillator
with 32 bit frequency resolution and 12 bit output. With over
69dB of spurious free dynamic range and worst case frequency resolution of 0.009Hz, the NC012 provides dramatic
improvements in accuracy over other frequency synthesis
solutions at a competitive price.
33M Hz, 40MHz Versions
32·Bit Frequency Control
BFSK, QPSK Modulation
Serial Frequency Load
12·Blt Sine Output
Offset Binary Output Format
O.009Hz Tuning Resolution at 40MHz
Spurious Frequency Components < -69dBc
Fully Static CMOS
LowCost
Applications
Two pins, PO-1, are provided for phase modulation. They are
encoded and added to the top two bits of the phase accumulator to offset the phase in 900 increments.
• Direct Digital Synthesis
• Modulation
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
The frequency to be generated is selected from two frequency control words. A single control pin selects which
word is used to determine the output frequency. Switching
from one frequency to another occurs in one clock cycle,
with a 6 clock pipeline delay from the time that the new control word is loaded until the new frequency appears on the
output.
PACKAGE
H8P45102PC-33
O"C 10 +700 C
28 Lead PlasliC DIP
HSP45102PC-40
28 Lead Plastic DIP
HSP45102PI-33
OOClo +700 C
-40°C 10 +85OC
HSP45102PI-40
-4000 to +8500
28 Lead Plastic DIP
HSP45102SC-33
OOC to +7000
28 Lead SOIC
HSP451028C-40
28 Lead SOIC
HSP45102SI-33
O"C to +7O"C
-40°C to +85OC
HSP45102SI-40
-4000 to +8500
28 LeadSOIC
28 Lead Plastic DIP
The 13 bit output of the Phase Offset Adder is mapped to the
sine wave amplitude via the Sine ROM. The output data format is offset binary to simplify interfacing to D/A converters.
Spurious frequency components in the output sinusoid are
less than -69dBc.
The NC012 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.
28 Lead SOIC
Block Diagram
CLK ____________________
P~l
~----------~------_,
____________________+-____
~
MSBILSBI ~r-=~=~
SFTENI
so
SCLK _ ' -_ _ _--'
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
5-3
File Number
2810.4
HSP45102
Pinout
28 PIN DIP, 28 PIN SOIC
TOP VIEW
OUTS
OUT5
OUT7
OUT4
OUT8
OUT3
OUT9
OUT2
OUT10
OUT1
OUT1t
OUTO
GNO
VCC
VCC
GNO
SEL.LIM#
PO
SFTEN#
P1
MSB/LSB#
LOAD#
ENPHAC#
TXFR#
so
CLK
GNO
Pin Description
NAME
PIN
NUMBER
TYPE
DESCRIPTION
VCC
8,22
GND
7,15,21
+5V power supply pin.
PO-l
19,20
I
Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift
of 0, 90,180, or 270 degrees can be selected (Table 1).
ClK
16
I
NCO clock. (CMOS level)
Ground
SClK
14
I
This pin clocks the frequency control shift register.
SELl/M#
9
I
A high on this input selects the least significant 32 bits of the 64 bit frequency register as
the input to the phase accumulator; a low selects the most significant 32 bits.
SFTEN#
10
I
The active low input enables the shifting of the frequency register.
MSB/lSB#
11
I
This input selects the shift direction of the frequency register. A low on this input shifts in the
data lSB first; a high shifts in the data MSB first.
ENPHAC#
12
I
This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of four clocks.
SO
13
I
Data on this pin is shifted into the frequency register by the rising edge of SClK when
SFTEN#' is low.
TXFR#'
17
I
This active low input is clocked onto the chip by ClK and becomes active after a pipeline
delay of four clocks. When low, the frequency control word selected by SELJ./M#' is
transferred from the frequency register to the phase accumulator's input register.
lOAD#'
18
I
This input becomes active after a pipeline delay of five clocks. When low, the feedback in
the phase accumulator is zeroed.
OUTD-l1
1-6,23-28
0
Output data. OUTO is lSB. Unsigned.
All inputs are TIL level, with the exception of elK.
:It sign designates active low signals.
5-4
HSP45102
Functional Description
The NC012 produces a 12 bit sinusoid whose frequency
and phase are digitally controlled. The frequency of the sine
wave is determined by one of two 32 bit words. Selection of
the active word is made by SEL_L/M#. The phase of the
output is controlled by the two bit input PO-1, which is used
to select a phase offset of 0 0 , 90 0 , 1800 , or 270 0 .
As shown in the Block Diagram, the NC012 consists of a
Frequency Control Section, a Phase Accumulator, a Phase
Offset Adder and a Sine ROM. The Frequency Control
section serially loads the frequency control word into the
frequency register. The Phase Accumulator and Phase
Offset Adder compute the phase angle using the frequency
control word and the two phase modulation inputs. The Sine
ROM generates the sine of the computed phase angle. The
format of the 12 bit output is offset binary.
Frequency Control Section
The frequency control multiplexer selects the least
significant 32 bits from the 64 bit frequency control register
when SELL/M# is high, and the most significant 32 bits
when SELL/M# is low. When only one frequency word is
desired, SELL/M# and MSB/LSB# must be either both
high or both low. This is due to the fact that when a frequency control word is loaded into the shift register LSB first, it
enters through the most significant bit of the register. After
32 bits have been shifted in, they will reside in the 32 most
significant bits of the 64 bit register.
When TXFR# is asserted, the 32 bits selected by the frequency control multiplexer are clocked into the phase accumulator input register. At each clock, the contents of this
register are summed with the current contents of the accumulator to step to the new phase. The phase accumulator
stepping may be inhibited by holding ENPHAC# high. The
phase accumulator may be loaded with the value in the input register by asserting LOAD#, which zeroes the feedback to the phase accumulator.
The Frequency Control Section (Figure 1), serially loads the
frequency data into a 64 bit, bidirectional shift register. The
shift direction is selected with the MSB/LSB# input.
When this input is high, the frequency control word on the
SD input is shifted into the register MSB first. When
MSB/LSB# is low the data is shifted in LSB first. The
register shifts on the rising edge of SCLK when SFTEN# is
low. The timing of these signals is shown in Figure 2.
The phase adder sums the encoded phase modulation bits
PO-1 and the output of the phase accumulator to offset the
phase by 0, 90, 180 or 270 degrees. The two bits are
encoded to produce the phase mapping shown in Table 1.
This phase mapping is provided for direct connection to the
in-phase and quadrature data bits for QPSK modulation.
The 64 bits of the frequency register are sent to the Phase
Accumulator Section where 32 bits are selected to control
the frequency of the sinusoidal output.
PO-1 CODING
TABLE 1
P1
PO
0
0
0
0
1
90
1
0
270
1
1
180
PHASE SHIFT (DEGREES)
Phase Accumulator Section
The phase accumulator and phase offset adder compute
the phase of the sine wave from the frequency control word
and the phase modulation bits PO-1. The architecture is
shown in Figure 1. The most significant 13 bits of the 32 bit
phase accumulator are summed with the two bit phase offset to generate the 13 bit phase input to the Sine Rom. A
value of 0 corresponds to 0 0 , a value of 1000 hexadecimal
corresponds to a value of 1800 .
The phase accumulator advances the phase by the amount
programmed into the frequency control register. The output
frequency is equal to N*Fclk/232 , where N is the selected
32 bits of the frequency control word. For example, if the
control word is 20000000 hexadecimal and the clock
frequency is 30M hz, then the output frequency would be
Fclk/8 or 3.75Mhz.
ROM Section
The ROM section generates the 12 bit sine value from the
13 bit output of the phase adder. The output format is offset
binary and ranges from 001 to FFF hexadecimal, centered
around 800 hexadecimal.
5-5
HSP45102
PHASE OFFSET ADDER
R.Po-1
Po-1
ENPHACI
TXFR.
LOAD.
13 MSB'S
--,,
CLK
'0'
FREQUENCY
CONTROL
SECTION
:-----.... ------....32..:
,
A
0
ACCUMULATOR
INPUT
REGISTER
FRCTRL
0-31
0
~
'FRCTRL
32:
32-63
::
~~~,~--~~~~
:
:,
SO -!-........-I-+--+......
SCLK
SFTENI
MSBILSBI
'
:
-+-____...J
:
..,,1------.......1
:
.... _------ .. ------- ...
,: (HIGH SELECTS FRCTRL0-31, LOW SELECTS FRCTR132-63)
,,,
,,,
,,
,,,
,,,
,
,,,
,,
,,
,,,
,,
,,
,,
!,
t.. ... ___________________________________________________ ..
PHASE ACCUMULATOR
FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM
SCLK
SO
\
X
SFTENI
MSBlLSBI
1~
::
I
X
FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN#
SCLK
SO
SFTENI
MSBILSB.
______ _________
~X
~:I:~----~X~---
FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK
SCLK
LOAD.
TXFR.
ENPHAC.
SEL--UM.
OUTo-11
--
---, ...._' ....
FIGURE 3. I/O TIMING
5-6
Specifications HSP451 02
Absolute Maximum Ratings
SupplyVoliage •••••.••••.....••..•.......••....•..•••••.•....••..••.••.•••...•••..••....•.•...•............••.. +8.0V
Input, Output or I/O Voltage Applied .........•..........•.••...•.•••.•.••...••.•••............... GND -0.5V to VCC +0.5V
Storage Temperature Range ....•..•.....••......•.•.••.•...••.•...•••...••.....•••.•••••.••.•..•..... -650C to +1500 C
Junction Temperature ....•.....•......................•••.....••..•••... : .•••.•••••.••••••...•.••..•..••..•... +1500 C
Maximum Package Power Dissipation (Commercial) ................•.....•......................... 1.5W (DIP), 1.1 W (SOIC)
Maximum Package Power Dissipation (Industrial) •......••......•..........................•. 1.30 C/W (DIP), 0.90 C/W (SOIC)
Sjc .•..•••••.•••••...••••.....•..•.......••.•........•••....•.•....••....•••.••••••.• 20.30 C/W (DIP), 21.60 C/W (SOl C)
Sja •••..•..•••..••..••.....••••..............•.•.•.••.•...••.••..••••...•.••.•••••••• 50.1 0 C/W (DIP), 71.40 C/W (SOIC)
Device Count •....•............•.........•.........•.......•.......•..................••...........• 32,528 Transistors
Lead Temperature (Soldering, Ten Seconds) .•.............•......•....••....•••..••..................•••.••.•... +3000 C
ESD Classification ••.•••....•••...•.•....•......•..........••.••...••...••..•.•.••.•.•••.•.•.••..•....•....•••• Class 1
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range (Commercial,lndustrial) ........••••..••.•.....•....•.•....•.........•......••• +4.75V to +5.25V
Operating Temperature Range (Commercial) ....•.•........•.••••..••.•..••••...............•••............. OoC to + 700C
Operating Temperature Range (Industrial) .................••.....••...........•...........•...........•• -400C to +85 0C
D.C. Electrical SpeCifications
SYMBOL
MIN
MAX
UNITS
VIH
Logical One Input Voltage
PARAMETER
2.0
-
V
TEST CONDITIONS
VCC= 5.25V
VIL
Logical Zero Input Voltage
-
0.8
V
VCC-4.75V
VIHC
High Level Clock Input
3.0
-
V
VCC= 5.25V
VILC
Low Level Clock Input
-
0.8
V
VCC=4.75V
VOH
Output HIGH Voltage
2.6
-
V
10H = -400~A, VCC = 4.75V
VOL
Output LOW Voltage
IOL = +2.0mA, VCC = 4.75V
II
Input Leakage Current
-
0.4
V
-10
10
~A
VIN = VCC or GND, VCC = 5.25V
ICCSB
Standby Power Supply Current
-
500
~A
VIN = VCC or GND
VCC = 5.25V, Note 3
ICCOp
Operating Power Supply Current
-
99
mA
f = 33MHz, VIN = VCC or GND
VCC = 5.25V, Notes 1 and 3
MIN
MAX
UNITS
CapaCitance (TA = +25 0 C, Note 2)
SYMBOL
PARAMETER
CIN
Input Capacitance
-
10
pF
Co
Output Capacitance
-
10
pF
TEST CONDITIONS
FREQ = 1 MHz, VCC = Open,
All measurements are referenced
to device ground
NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp is SmA/MHz.
3. Output load per test load circuit with switch open and CL
2. Not tested, but characterized at initial design and at major process/design
changes.
5-7
= 40pF.
Specifications HSP45102
A.C. Electrical Specifications VCC = 5.0V ± 5%, TA = ooC to +700 C, TA = -40 0 C to +850 C (Note 1)
-33 (33MHz)
PARAMETER
-40 (40MHz)
MIN
MAX
MIN
MAX
TCp
Clock Period
30
25
-
TCH
Clock High
12
12
-
SYMBOL
COMMENTS
TCl
Clock low
12
TSW
SCLK High/low
12
TDS
Set-up Time SD to SCLK Going High
12
TDH
Hold Time SD from SClK Going High
0
TMS
Set-up Time SFTEN#, MSB/lSB#
to SClK Going HGgh
15
-
TMH
Hold Time SFTEN#, MSB/lSB#
from SClK Going High
0
-
0
-
ns
TSS
Set-up Time SClK High to ClK
Going High
16
-
15
-
ns, Note 2
10
10
10
12
0
ns
ns
ns
ns
ns
ns
ns
TpS
Set-up Time PO-1 to ClK Going High
15
-
12
TpH
Hold Time PO-1 from ClK Going High
1
-
1
TES
Set-up Time lOAD#, TXFR#,
ENPHAC#, SELL/M# to ClK
GOing High
15
-
13
-
TEH
Hold Time lOAD#, TXFR#,
ENPHAC#, SELL/M# from ClK
Going High
1
-
1
-
ns
TOH
ClK to Output Delay
2
15
2
13
ns
TRF
Output Rise, Fall Time
8
-
8
-
ns
ns
ns
ns, Note 3
NOTES
1. AC. testing is performed as follows: Input levels (CLK Input) 4.0V and OV;
Input levels (all other inputs) OV and 3.0V; Timing reference levels (CLK)
2.0Vj All others 1.SV. Output load per test load circuit with switch closed
and CL = 40 pF. Output transition is measured at VOH ~ 1.5V and
VOL So 1.SV.
2. If TXFR:It is active, care must be taken to not violate set-up and hold times
as data from the shift registers may not have settled before eLK occurs.
3. Controlled via design or process parameters and not directly tested. Charac~
terized upon initial design and after major process and/or design changes.
A. C. Test Load Circuit
r-------------I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
t
I
1.5V
IOl
I
*TEST HEAD
CAPACITANCE
I
~QUIVAlENT-CIRCUIT
I
I
-
1 ______ - - - - - - - -
Switch S1 open for ICCSB and ICCOp
5-8
JI
HSP45102
Waveforms
eLK
PO -1
LOAD#. TXFR#.
TpS
TpH
TES
TEH
ENPHAC#.SEL.LJM#
-
OUTO -11
- T OH
TSW
TSW
SCLK
TOS
TOH
SO
(/)
TMS
TMH
"
II:
.... W
MSBJLSB#
c(!::!
z(/)
CJW
_::E:
(/)1-
Z
>
(/)
5-9
HSP45106
16-Bit Numerically Controlled Oscillator
January 1994
Features
Description
• 25.6MHz, 33MHz Versions
The Harris HSP45106 is a high performance 16-bit quadrature numerically controlled oscillator (NC01S). The NC01S
simplifies applications requiring frequency and phase agility
such as frequency-hopped modems, PSK modems, spread
spectrum communications, and precision signal generators.
As shown in the block diagram, the HSP45106 is divided into
a Phase/Frequency Control Section (PFCS) and a Sine/
Cosine Section.
• 32-Blt Center and Offset Frequency Control
• 16-Blt Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Blt Sine and Cosine Outputs
• Output In TWo's Complement or Offset Binary
• G)G)G)G)(
FIGURE 3. SERIAL OUTPUT 110 TIMING DIAGRAM
5-16
Specifications HSP45106
Absolute Maximum Ratings
Supply Voltage ................................................................................................. +8.0V
Input, Output or I/O Voltage Applied ............................................................. GND -0.5V to VCC +0.5V
Storage Temperature Range .......................................................................... -650C to +1500 C
Maximum Package Power Dissipation ........................................................... 2.3W (PLCC), 2.9W (PGA)
8jc ................................................................................. 11.30 C/W (PLCC), 1 O.OoC/W (PGA)
8ja ................................................................................... 34.00 C/W (PLCC), 36 0 C/W (PGA)
Component Count ................................................................................... 75,000 Transistors
Junction Temperature ................................................................... +150 0 C (PLCC), +1750 C (PGA)
Lead Temperature (Soldering, Ten Seconds) ..................................................................... +3000C
ESD Classification ............................................................................................. Class 1
CAUTION: Stresses above those listed in the IiAbsoJute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. • .. . • . .. . . . . . . • . • . • .. . • . • . .. . .. .. . .. . . . .. .. . .. . . . .. . . . .. . . . . .. .. .. . .. .. . . . .• +4.75V to +5.25V
Operating Temperature Range ............................................................................ OoC to + 700C
D.C. Electrical Specifications
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
VIH
Logical One Input Voltage
2.0
-
V
VCC= 5.25V
VIL
Logical Zero Input Voltage
-
0.8
V
VCC= 4.75V
VIHC
High Level Clock Input
3.0
-
V
VCC= 5.25V
VILC
Low Level Clock Input
-
0.8
V
VCC= 4.75V
VOH
Output HIGH Voltage
2.6
-
V
10H = -400f1A, VCC = 4.75V
VOL
Output LOW Voltage
-
0.4
V
10L = +2.0mA, VCC = 4.75V
Input Leakage Current
-10
10
f1A
VIN = VCC or GND, VCC = 5.25V
110 Leakage Current
-10
10
f1A
VOUT=VCCor GND,
VCC= 5.25V
II
10
ICCSB
Standby Power Supply Current
-
500
f1A
VIN = VCC or GND
VCC = 5.25V, Note 3
ICCOp
Operating Power Supply Current
-
180
mA
f = 25.6MHz, VIN = VCC or GND
VCC = 5.25V, Notes 1 and 3
CapaCitance
SYMBOL
(TA = +250 C, Note 2)
MIN
MAX
UNITS
CIN
Input Capacitance
PARAMETER
-
10
pF
Co
Output Capacitance
-
10
pF
TEST CONDITIONS
FREQ = 1 MHz, VCC = Open,
All measurements are referenced
to device ground
NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp is 7mA/MHz.
3. Output load per test load circuit with switch open and CL
2. Not tested, but characterized at initial design and at major process/design
changes.
5-17
= 40pF.
Specifications HSP45106
A.C. Electrical Specifications vcc =
5.0V ± 5%, TA = OOC to +700 C (Note 1)
33MHz
25.6MHz
SYMBOL
MIN
PARAMETER
TCp
ClKPeriod
39
TCH
ClKHigh
15
TCl
ClKlow
15
TWp
WR#Period
39
TWH
WR#High
15
TWl
WR#low
15
MAX
-
MIN
MAX
30
12
-
30
-
12
COMMENTS
ns
ns
ns
ns
TMCH
Hold Time MODO-2 from ClK Going High
0
-
TECS
Set-up Time ENPOREG#, ENOFREG#, ENCFREG#, ENPHAC#,
ENTIREG#,INHOFR#, PMSEl#,INITPAC#, BINFMT#,
TEST, PAR/SER#, PACI#,INITTAC# to ClK Going High
12
-
12
-
TECH
Hold Time ENPOREG#, ENOFREG#, ENCFREG#, ENPHAC#,
ENTIREG#,INHOFR#, PMSEl#,INITPAC#, BINFMT#,
TEST,PAR/SER#, PACI#,INITTAC# from ClK Going High
0
-
0
-
ns
TOO
ClK to Output Delay SINO-15, COSO-15, TICO#
-
18
-
15
ns
ClK to Output Delay DACSTRB#
2
18
2
15
ns
12
-
12
ns
15
ns, Note 3
8
ns, Note 3
TAWS
Set-up Time AO-2, CS# to WR# Going High
13
TAWH
Hold Time AO-2, CS# from WR# Going High
1
TCWS
Set-up Time CO-15 to WR# Going High
15
TCWH
Hold Time CO-15 from WR# GOing High
0
Set-up Time WR# High to ClK High
16
Set-up Time MODO-2 to ClK Going High
15
TWC
TMCS
TDSO
TOE
Output Enable Time
TOO
Output Disable Time
TRF
Output Rise, Fall Time
-
-
15
8
12
12
13
1
15
0
12
15
0
ns
ns
ns
ns
ns
ns
ns, Note 2
ns
ns
ns
NOTES:
1. A.C. testing is performed as follows: Input levels (CLK Input) 4.0V and OV;
Input levels (all other inputs) OV and 3.0V; Timing reference levels (CLK)
2.0V; All others 1.5V. Output load per test load circuit with switch closed
and CL = 40 pF. Output transition is measured at VOH 2: 1.5V and VOL ~
1.5V.
A.C. Test Load Circuit
2. If ENOFREGIF, ENCFREGIF, ENTIREGIF, OR ENPOREGIF are active,
care must be taken to not violate set-up and hold times to these registers
when writing data into the chip via the CO-15 port.
3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
r---------------,
I
I
I
I
I
I
I
I
I
I
I
I
Switch S 1 open for ICCSB and 'CCOP
I
I
I
I
I
1.5V
IOL
I
I
I
I
CIRCUIT
I
I- - - - EQUIVALENT
----------5-18
HSP45106
Waveforms
SYNCHRONOUS TIMING
ClK
MODO -2
ENABLE!
CONTROL
SIGNALS
SINO - 15. COSO - 15. TICO# _ _.j...I'I'-_ _"
DACSTRB#
(SERIAL MODE ONLy)
ASYNCHRONOUS TIMING
WR#
AO -2. CS#
l(:ws TCWH
co -15
==f= f=
OUTPUT ENABLE, DISABLE TIMING
OES#.OEC#
t~
TOE
""
COSO -15.
SINO -15
t'~
~:_N.
1.3V
HIGH
IMPEDANCE
OUTPUT RISE AND FALL TIMES
5-19
TOO
.~
HIGH
IMPEDANCE
HSP451 06/883
16-Bit Numerically Controlled Oscillator
January 1994
Features
Description
• This Circuit Is Processed In Accordance to MIL-STD883 and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Harris HSP451061883 is a high performance 16-bi!
quadrature numerically controlled oscillator (NC016). The
NC016 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP45106/883 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.
• 25.6MHz Clock Rate
• 32-Blt Center and Offset Frequency Control
• 16-Blt Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Blt Sine and Cosine Outputs
• Output In lINo's Complement or Offset Binary
• .TA.:s;+1250C
13
-
Hold Time AO-2, CS# from WR#
Going High
TAWH
9,10,11
-550 C.$ TA.$ +1250 C
2
-
ns
Set-up Time CO-15 to WR#
Going High
TCWS
9,10,11
-550C.$ TA.$ +1250 C
15
-
ns
Hold Time CO-15 from WR#
Going High
TCWH
9,10,11
-55 0 C.:s;TA'::>' +1250C
1
-
ns
9,10,11
-550C.:s; TA.$ +1250C
16
ClKPeriod
TCp
9,10,11
-550 C.$TA.$ +1250C
39
ClKHigh
TCH
9,10,11
-550C :sTA.$ +125 0C
15
ClKlow
TCl
9,10,11
-550 C.$ TA.$ +125 0C
15
WR# Period
TWp
9,10,11
-550 C.$ TA.$ +1250 C
39
TWH
9,10,11
-550 C.::;TA.:s;+1250C
15
15
WR# High
WR#low
ns
ns
ns
ns
ns
ns
Set-up Time WR# High to ClK High
TWC
-
ns
Set-up Time MODO-2 to ClK
Going High
TMCS
9,10,11
-55°C .$ TA.:s; +1250 C
15
-
ns
Hold Time MODO-2 from ClK
Going High
TMCH
9,10,11
-550C .$TA$ +125 0C
1
-
ns
Set-up Time ENPOREG#,
ENOFREG#, ENCFREG#,
ENPHAC#, ENTIREG#, INHOFR#,
PMSEl#, INITPAC#, BINFMT#,
TEST, PAR/SER#, PACI#,
INITTAC# to ClK Going High
TECS
9,10,11
-550 C.:s;TA$ +1250 C
12
-
ns
Hold Time ENPOREG#,
ENOFREG#, ENCFREG#,
ENPHAC#, ENTIREG#, INHOFR#,
PMSEl#, INITPAC#, BINFMT#,
TEST, PAR/SER#, PACI#,
INITTAC# from ClK Going High
TECH
9,10,11
-550 C.:s;TA.$ +1250C
1
-
ns
ClK to Output Delay SINO-15,
COSO-15, TICO#
TOO
9,10,11
-550C.:s; TA :s +1250C
-
18
ns
TDSO
9,10,11
-550 C.:s;TA.:s;+1250C
2
18
ns
9,10,11
-550C
... co
0
0
PMSEL
MODO
MOD1
MOD2
TEST
WR#
GND
CS#
a:
.JW
o(!:::!
ENCFREG#
Z(/)
CJW
_::J:
ENOFREG#
(/)1-
INHOFR#
ENTIREG#
INITTAC#
ENPOREG#
ENPHAC#
PACI#
INITPAC#
BINFMT#
PAR/SER#
VCC
5-25
(/)
Z
>
(/)
HSP45116
Numerically Controlled
OscillatorlModulator
February 1994
Features
Description
• NCO and CMAC on One Chip
The Harris HSP45116 combines a high performance
quadrature numerically controlled oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a complex vector to be multiplied by the internally generated (cos,
sin) vector for quadrature modulation and demodulation. As
shown in the block diagram, the HSP45116 is divided into
three main sections. The PhaseIFrequency Control Section
(PFCS) and the Sine/Cosine Section together form a complex NCO. The CMAC multiplies the output of the Sine/
Cosine Section with an external complex vector.
• 15MHz, 25.6MHz, 33MHz Versions
• 32·Blt Frequency Control
• 16-Blt Phase Modulation
• l6-Blt CMAC
• O.008Hz Tuning Resolution at 33M Hz
• Spurious Frequency Components < ·90dBc
• Fully Static CMOS
Applications
The inputs to the PhaseIFrequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32-bits, which results in
frequency resolution better than O.008Hz at 33MHz. The output of the PFCS is the argument of the sine and cosine. The
spurious free dynamic range of the complex sinusoid is
greater than 9OdBc.
• Frequency Synthesis
• Modulation· AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
PACKAGE
HSP45116VC·15
O"C 10 +70oC
HSP45116VC·25
OOC 10 +70oC
160 Lead MQFP
HSP45116VC·33
OOC to +70oC
160 Lead MQFP
HSP45116GC·15
OOC 10 +70oC
145 Lead PGA
HSP45116GC·25
OOClo +70oC
145 Lead PGA
HSP45116GC-33
OOC 10 +70oC
145 Lead PGA
HSP45116TM-15
·55°C 10 +125°C
156 Lead TAB
HSP45116TM·25
·55OC 10 +125°C
156 Lead TAB
HSP45116AVC-52
OOCto +70oC
160 Lead MQFP
160 Lead MQFP
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
muttiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 2Q-bit output ports which maintain
the 90dB spectral pur~y. This result can be accumulated internally to implement an accumulate and dump filter.
A quadrature down converter can be implemented by loading a center frequency into the Phase/Frequency Control
Section. The signal to be downconverted is the Vector Input
of the CMAC, which multiplies the data by the rotating vector
from the Sine/Cosine Section. The resulting complex output
is the down converted signal.
The pinout for the TAB package can be obtained by referring
to the Metallization Mask Layout of the HSP451161883 data
sheet.
Block Diagram
VECTOR INPUT
R
I
MICROP~N~~~~!~~
-..
CONTRJ~~::!~~~ - . .
PHASE!
FREQUENCY
CONTROL
SECTION
SINE!
COSINE
ARGUMENT
SINE!
COSINE
SECTION
SIN
! !
cos
CMAC
! !
R
I
VECTOR OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow propsr I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
5·26
File Number
2485.4
HSP45116
Pinouts
145 PIN PGA
TOP VIEW
3
4
A
Vee
IMIN
4
IMIN
IMIN
8
•
IMIN
B
GND
IMIN
(MIN
IMIN
IMIN
1
5
7
10
13
14
e
RIN
RIN
IMIN
IMIN
IMIN
15
16
1M IN
3
6
12
IMIN
17
D
RIN
RIN
17
IMIN INDEX
13
RIN
RIN
RIN
G
H
K
10
14
16
RIN
RIN
11
Vee
RIN
•
RIN
IMIN
10
10
IMIN
10
17
,. ,.
18
10
11
12
13
14
15
10
10
10
10
GND
Vee
18
15
12
10
10
10
10
10
10
14
11
8
10
7
5
2
10
10
10
10
4
10
RO
1
18
10
RO
,.
D
3
RO
17
10
RO
RO
,.
E
RO
RO
13
• •
6
GND
RIN
6
RIN
RIN
3
RIN
0
RO
12
13
11
•
RO
12
10
RIN
RO
8
RO
7
GND
5
1
RIN
4
RO
RO
Vee
•
RIN
SH
0
1
RO
RO
SH
Ace
BYTIL
...
'N""
BINfMT
TlCO
PACI
#
#
GND
MOD LOAD
0
#
...
,NOF
#
PMSEL CLROFR ENT"'"
ENPHAC
#
#
ENI
eLK
#
4
14
Vee
GND
DEl
RO
13
12
11
M
0
e
e
OEA
GND
P
6
3
1
#
e
7
e
Q
5
e
4
Vee
11
0
10
11
12
13
14
•
es
AD
e
e
e
1
15
10
Vee
GND
,.
•
e
•
AO
e
8
e
3
OEI
DEl
e
13
WR
K
#
e
14
#
H
0''''''
e
0
#
G
0
AD
#
B
e
1
"p,
"ODA
A
6
1
#
#
e
"",.
"",.
MU'
~,
e
N
0
en
a:
15
...I
10
10
10
10
10
10
12
15
18
Vee
GND
,.
IMIN
16
IMIN
IMIN
"
11
Zen
OW
•
3
IMIN
•
1M IN
IMIN
8
4
IMIN
IMIN
IMIN
10
10
10
18
1
4
6
9
13
o
AO
17
AO
10
3
0
RIN
17
RIN
19
E
AO
,.
AO
10
AIN
AIN
AIN
18
0
16
RO
RO
RO
,.
RIN
"
RIN
11
RIN
7
AO
AIN
RIN
9
8
9
Vee
G
RO
7
AO
AIN
•
RIN
GND
H
8
Vee
AO
RO
RIN
RIN
4
1
3
RO
AO
SH
AIN
AIN
13
H
GND
K
M
10
12
6
3
IMIN
•
•
INDEX IMIN
,.
• •
1
13
6
AIN
•
1
1
0
•
AO
DEl
PACO
RBYTIUl
Ace
SH
3
1
AO
OEI
#
DEl DE"'"
0
#
OER
#
Vee
15
#
#
0'"""
MOD
#
QUTMUX DU_
e
e
AD
1
•
e
0
e
8
13
14
0
'#
e
e
e
e
e
e
AD
es
1
3
6
9
10
15
1
e
,.
e
e
e
0
4
5
e
7
11
14
13
12
11
10
e
GND
Vee
MODA
#
WR
.,.
ENCF
#
#
0
#
eLK
#
5
#
•
#
PACI
#
#
ENI
EfrlPttAC
#
K
0
PEAK
LOAD MOD .~""
EHTIREG CLROfFl PM$EL
#
5-27
1
D
10
6
GND
Q
17
IMIN
AO
0
N
,.
18
e
10
AO
IMIN
"
10
11
10
IMIN
AIN
11
AO
AO
13
IMIN
18
6
10
14
G
14
IMIN
AIN
• •
10
10
17
IMIN
B
10
16
IMIN
7
GND
10
7
B
IMIN
A
10
10
10
(j)i!=
Vee
10
e
W
Ct::!
BonOMVIEW
15
PACO
OEnEXT
1
#
Vee
•
RO
1
#
PEAK MOD
...
'NOF
• •
#
#
A
,.
RO
#
Q
,.
Vee
14
#
P
"
IMIN
GND
RO
#
N
11
IMIN
0
RIN
7
0
M
2
6
IMIN
GND
...
EN""
M
#
ENOF
"'#
N
Tlea
#
p
Vee
Q
Z
>en
HSP45116
Pinouts (Continued)
160 LEAD MQFP
TOP VIEW
IMINO
RIN18
RIN17
RIN16
RIN15
RIN14
GND
RIN13
RIN12
RIN11
RIN10
RINII
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
GND
RINl
Ne
GND
108
lOS
104
103
GND
102
101
Vee
100
ROlli
GND
R018
R017
R016
R015
R014
Vee
R013
R012
R01l
GND
R010
ROIl
Vee
RIND
SHl
SHO
ACC
ENPHREGt
ENOFREGt
PEAK.
RBYTlLDt
BINFMT.
GND
TlCO.
Vee
R08
R07
GND
ROIl
ROIl
R04
ROO
Vcc
Vee
MODl
MODO
PAct.
LOADI
PMSEL
NC
R02
R01
ROO
GND
DEll
DETO
NOTE:
1. Pin 75 functions as the round enable (RND#) on the HSP45116A. Pin 75 is Vcc on the HSP45116.
5-28
HSP45116
Pin Description
NAME
NUMBER
VCC
Al,A9,A15,Gl,
J15,01,07,015
TYPE
+5 Power supply input
GND
A8,A14, Bl, Hl,
H15, P15, 02, 08
Power supply ground input
CO-15
N8-11, P8-13,
09-14
I
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
ADO-l
N7,P7
I
Address pins for selecting destination of CO-15 data
CS#
P6
I
Chip select (Active low)
WR#
06
I
Write enable. Data is clocked into the register selected by ADO-l on the rising edge of
WR# when the CS# line is low.
ClK
05
I
Clock. All registers, except the control registers clocked with WR#,are clocked (when
enabled) by the rising edge of ClK.
ENPHREG#
Ml
I
Phase register enable. (Active low) Registered on chip by ClK. When active, after being
clocked onto chip, ENPHREG# enables the clocking of data into the phase register.
ENOFREG#
Nl
I
Frequency offset register enable. (Active Low) Registered on chip by ClK. When active,
after being clocked onto chip, ENOFREG# enables clocking of data into the frequency
offset register.
ENCFREG#
N5
I
Center frequency register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENCFREG# enables clocking of data into the center
frequency register.
ENPHAC#
03
I
Phase accumulator register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENPHAC# enables clocking of the phase accumulator
register.
ENTIREG#
P5
I
Time interval control register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENTIREG# enables clocking of data into the time
accumulator register.
ENI#
04
I
Real and imaginary data input register (RIR, IIR) enable. (Active low) Registered on chip by
ClK. When active, after being clocked onto chip, ENI# enables clocking of data into the
real and imaginary input data register.
MODPI/
2PI#
N6
I
Modulo n/2n select. When low, the Sine and Cosine ROMs are addressed modulo 2n (360
degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo n (180 degrees). This input is registered on chip by clock.
ClROFR#
P4
I
Frequency offset register output zero. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ClROFR# zeros the data path from the frequency offset
register to the frequency adder. New data can still be clocked into the frequency offset
register; ClROFR# does not affect the contents of the register.
lOAD#
N4
I
Phase accumulator load control. (Active low) Registered on chip by ClK. Zeroes feedback
path in the phase accumulator without clearing the phase accumulator register.
MODO-l
M3,N3
I
External modulation control bits. When selected with the PMSEl line, these bits add a 0,90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits
of the phase control path are set to zero.
DESCRIPTION
These bits are loaded into the phase register when ENPHREG# is low.
PMSEl
P3
I
Phase modulation select line. This line determines the source of the data clocked into the
phase register. When high, the phase control register is selected. When low, the external
modulation pins (MODO-l) are selected for the most significant two bits and the least
significant two bits and the least significant 14 bits are set to zero. This control is registered
byClK.
RBYTllD#
l3
I
ROM bypass, timer load. Active low, Registered by ClK. This input bypasses the sinel
cosine ROM so that the 16 bit phase adder output and lower 16 bits of the phase
accumulator go directly to the CMAC's sine and cosine inputs, respectively. It also enables
loading of the timer accumulator register by zeroing the feedback in the accumulator.
5-29
HSP45116
Pin Description
(Continued)
NAME
NUMBER
TYPE
DESCRIPTION
PACI#
P2
I
Phase accumulator carry input. (Active low) A low on this pin causes the phase
accumulator to increment by one in addition to the values in the phase accumulator
register and frequency adder.
PACO#
L13
0
Phase accumulator carry output. Active low and registered by ClK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle
has been reached.
TICO#
P1
0
Time interval accumulator carry output Active low, registered by ClK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time
out control events such as synchronizing register clocking to data timing.
RINO-18
C1, C2, D1, D2,
E1-3, F1-3,
G2,G3,H2,
H3, J1-3, K1, K2
I
Real input data bus. This is the external real component into the complex multiplier. The bus
is clocked into the real input data register by ClK when ENI# is asserted. Two's complement
IMINO-18
A2-7,B2-7,
C3-8,D3
I
Imaginary input data bus. This is the external imaginary component into the complex
multiplier. The bus is clocked into the real input data register by ClK when ENI# is
asserted. Two's complement.
SHO-1
K3,L1
I
Shift control inputs. These lines control the input shifters of the RIN and liN inputs of the
complex multiplier. The shift controls are common to the shifters on both ofthe busses.
ACC
l2
I
Accumulate/dump control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in the accumulators is zeroed to cause the accumulators to
load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by ClK.
BINFMT#
N2
I
This input is used to convert the two's complement output to offset binary (unSigned) for
applications using D/A converters. When low, bits R019 and 1019 are inverted from the
internal two's complement representation. This input is registered by ClK.
PEAK#
M2
I
This input enables the peak detect feature of the block floating point detector. When high,
the maximum bit growth in the output holding registers is encoded and output on the
DETO-1 pins. When the PEAK# input is asserted, the block floating point detector output
will track the maximum growth in the holding registers, including the data in the holding
registers at the time that PEAK# is activated.
OUTMUXQ-1
N12,N13
I
These inputs select the data to be output on ROO-19 and 100-19.
ROO-19
C15,D14, D15
E14,E15,F13-15,
G13-15, H13, H14,
J13, J14, K13-15,
l 15, M15
0
Real output data bus. These thres state outputs are controlled by OER# and OEREXT#.
OUTMUXO-1 select the data output on the bus.
100-19
A10-13,B8-15,
C9-14,D13,E13
0
Imaginary output data bus.These three state outputs are controlled by OEI# and OEIEXT#.
OUTMUXO-1 select the data output on the bus.
DETO-1
N15, L14
0
These output pins indicate the number of bits of growth in the accumulators. While PEAK#
is low, these pins indicate the peak growth. The detector examines bits 15-18, real
and imaginary accumulator holding registers and bits 30-33 of the real and imaginary
CMAC holding registers. The bits indicate the largest growth of the four registers.
OER#
P14
I
Three state control for bits ROO-15. Outputs are enabled when the line is low.
OEREXT#
M13
I
Three state control for bits R016-19. Outputs are enabled when the line is low.
OEI#
M14
I
Thres state control for bits 100-15. Outputs are enabled when the line is low.
OEIEXT#
N14
I
Three state control for bits 1016-19. Outputs are enabled when the line Is low.
RND#
N/A
I
Round Enable (Available on HSP45116A only). This input enables rounding of the output
data precision from 9 to 20 bits (ses HSP45116A Description and Operation. This input is
active "low". This input must be tied either high or low.
5-30
HSP45116
Functional Description
Phase and Frequency Control Section
The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16 bit sine and
cosine vectors at a maximum sample rate of 33MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT
twiddle factor; when data is input to the Vector Inputs (see
Block Diagram), the NCOM calculates an FFT butterfly.
The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Figure 1). The PFCS
generates a 32 bit word that represents the current phase of
the sine and cosine waves being generated: the Sine/
Cosine Argument. Stepping this phase angle from
o through full scale (2 32 - 1) corresponds to the phase
angle of a sinusoid starting at 0 0 and advancing around the
unit circle counterclockwise. The PFCS automatically
increments the phase by a preprogrammed amount
on every rising edge of the external clock. The value of the
phase step (which is the sum of the Center and Offset
Frequency Registers) is:
Phase Step '" Signal Frequency x 232
Clock Frequency
The PFCS is divided into 2 sections: the Phase Accumulator
uses the data on CO-15 to compute the phase angle that is
the input to the Sine/Cosine Section (Sine/Cosine
Argument); the Time Accumulator supplies a pulse to mark
the passage of a preprogrammed period of time.
As shown in the Block Diagram, the NCOM consists of
three parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the input vector to form the modulated output.
The Phase Accumulator and Time Accumulator work on the
same principle: a 32 bit word is added to the contents of a
32 bit accumulator register every clock cycle; when the sum
PACO#"
CLK_"'-_.......
o
a:
...JW
PHASE
ADDER
MS INPUT
REGISTER
16
CENTER FREQUENCY
REGISTER
32
PHASE
ACCUMULATOR
ADDER
FREQUENCY
ADDER
A
32
D
D
A
D
D
E
R
01-
o
Z
~
A
D
D
E
R
PHASE
ACCUMULATOR
32 REGISTER
R.EN
PHAC
#"
CLK
eel:::!
Z0
CJW
_J:
R
E
G
16 LSB·.
CLK
32
PHASE
ACCUMULATOR
PACI#"
",.., ~: J '§ I::=: '""'''
CS#"
MSEN#"
~
WR#
ENCFREG#"
ENOFREG#"
CLROFR#"
LOAD#"
PMSEL
ENPHREG#"
ENPHAC#
MODPI/2PI#"
ENTlREG#"
RBYTILD#"
CLK
REG
-
LSEN#
32
I
I
I
TIME
INCREMENT
R.ENCFREG#"
R.ENOFREG#"
R.CLROFR#"
R.LOAD#"
R.PMSEL
R.ENPHREG#"
R.ENPHAC#"
R.MODPI/2PI#"
R.ENTIREG#"
R.RBYTILD#"
I
I
I
R.ENTIREG#"
TIME
ACCUMULATOR
o
I
I
1 _ _ _ _ _ _ _ _ _ _ _ _ _ ----'
FIGURE 1. PHASE/FREQUENCY CONTROL SECTION BLOCK DIAGRAM
5-31
TICO#"
HSP45116
causes the adder to overflow, the accumulation continues
with the 32 bits of the adder going into the accumulator
register. The overflow bit is used as an output to indicate the
timing of the accumulation overflows. In the Time
Accumulator, the overflow bit generates TICO#, the Time
Accumulator carry out (which Is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow is
inverted to generate the Phase Accumulator Carry Out,
PACO#.
The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32 bit number forms the argument of the sine and
cosine, which Is passed to the Sine/Cosine Generator.
Both accumulators are loaded 16 bits at a time over the
CO-15 bus. Data on CO-15 is loaded into one of the three
Input registers when CS# and WR# are low. The data In the
Most Significant Input Register and least Significant Input
Register forms a 32 bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signal; for example, to load the
Center Frequency Register, the data is loaded into the lS
and MS Input Registers, and ENCFREG# is set to zero; the
next rising edge of ClK will pass the registered version of
ENCFREG#, R.ENCFREG#, to the clock enable of the
Center Frequency Register; this register then gets loaded
on the following rising edge of ClK. The contents of the
Input Registers will be continuously loaded into the Center
Frequency Register as long as R.ENCFREG# Is low.
The Phase Register is loaded In a similar manner. Assuming
PMSEl Is high, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG is low. If PMSEl is low, MODO-1 supply
the two most significant bits into the Phase Register (MOD 1
Is the MSB) and the least significant 14 bits are loaded with
o. MODO-1 are used to generate a Quad Phase Shift Keying (QPSK) signal (Table 2).
PSK modulation schemes. These three values are used by
the Phase Accumulator and Phase Adder to form the phase
of the Internally generated sine and cosine.
The sum of the values In Center and Offset Frequency
Registers corresponds to the desired phase Increment
(modulo 232) from one clock to the next. For example, loading both registers with zero will cause the Phase
Accumulator to add zero to its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will be a DC signal. If a hexadecimal 00000001
is loaded into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location In the Sine/Cosine
Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, I.e., the
clock frequency divided by 232. If the input to the Center
Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.
The operation of the Offset Frequency Control Register is
identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency Control Register and updating the Offset
Frequency Control Register with the value of the frequency
offset - the difference between the carrier frequency and
the frequency of the output signal. A logic low on
ClROFR# disables the output of the Offset Frequency
Register without clearing the contents of the register.
TABLE 2. MODO-1 DECODE
TABLE 1. ADO-1 DECODING
AD1
ADO
CS#
WR#
FUNCTION
0
0
0
t
Load least significant bits of
frequency Input
0
1
0
t
Load most significant bits of
frequency input
1
0
0
t
Load phase register
1
1
X
X
Reserved
X
X
1
X
Reserved
MOD1
MODO
PHASE SHIFT (DEGREES)
0
0
0
0
1
90
1
0
270
1
1
180
Initializing the Phase Accumulator Register is done by
putting a low on the lOAD# line. This zeroes the feedback
path to the accumUlator, so that the register is loaded with
the current value of the phase increment summer on the
next clock.
The Phase Accumulator consists of registers and adders
that compute the value of the current phase at every clock. It
has three inputs: Center Frequency, which corresponds to
the carrier frequency of a signal; Offset Frequency, which Is
the deviation from the Center Frequency; and Phase, which
Is a 16 bit number that Is added to the current phase for
The final phase value going to the Generator can be adJusted using MODPI/2PI# to force the range of the phase to
be 0 0 to 1800 (modulo n) or 0 0 to 3600 (modulo 2n).
Modulo 2n is the mode used for modulation, demodulation,
direct digital synthesis, etc. Modulo n Is used to calculate
FFTs. This Is explained In greater detail In the Applications
section.
The Phase Register adds an offset to the output of the
Phase Accumulator. Since the Phase Register is only 16
bits, it is added to the top 16 bits of the Phase Accumulator.
5-32
HSP45116
The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of ClK
while ENTIREG# is low. The output of the Time
Accumulator is the accumulator carry out, TICO#. TICO#
can be used as a timer to enable the periodic sampling of
the output of the NCOM. The number programmed into this
register equals 2 32 x ClK period/desired time interval.
TICO# is disabled and its phase is initialized by zeroing the
feedback path of the accumulator with RBYTllD#.
Sine/Cosine Section
The Sine/Cosine Section (Figure 2) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16 bit sine and cosine inputs to the CMAC.
Complex Multiplier/Accumulator
The CMAC (Figure 3) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier and its associated accumulator; the rest of the circuitry in
this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and liN. The two vectors are
combined in the following manner:
ROUT = COS x RIN - SIN x liN
lOUT = COS x liN + SIN x RIN
RIN and liN are latched into the input registers and passed
through the shift stages. Clocking of the input registers is
enabled with a low on ENI#. The amount of shift on the
latched data is programmed with SHO-1 (Table 3). The output of the shifters is sent to the CMAC and the auxiliary accumulators.
SIN
"'!Z
OUJ
1./.::;
z::l
iiilE<
32
20
~~
~!<
TABLE 3. INPUT SHIFT SELECTION
cos
~ffi
SH1
SHO
SELECTED BITS
0
0
RINO-15,IMINO-15
~~
"'(.?
CLK
0
1
RIN1-16,IMIN1-16
1
0
RIN2-17,IMIN2-17
1
1
RIN3-18,IMIN3-18
R.RBYTILD _ _ _ _ _ _ _ _ _ _ _ _ _---l
:#
FIGURE 2. SINE/COSINE SECTION
The 20 bit word maps into 211 radians so that the angular
resolution is 211/220. An address of zero corresponds to 0
radians and an address of hex FFFFF corresponds to 211(211/220) radians. The outputs of the Generator section are
2's complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents negative full scale, to 7FFF, which represents
positive full scale. Note that the normal range for two's complement numbers is 8000 to 7FFF; the output range of the
SIN/COS generator is scaled by one so that it is symmetric
about O.
The 33 bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the accumulator section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set
of real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUXO- 1 lines (Table 4). BINFMT# controls whether
the output of the Multiplexer is presented in two's
complement or unsigned format; BINFMT# = 0 inverts
ROUT19 and IOUT19 for unsigned output, while BINFMT#
= 1 selects two's complement.
The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the complex vector is less than -90.2dB.
The error in the sine or cosine alone is approximately 2dB
better.
If RBYTllD# is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
through 15 of the NCOM with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the
PFCS appears on IOUTO-15 and the least significant bits
come out on ROUTO-15.
5-33
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT
MUX
1
OUT
MUX
0
0
0
Real
CMAC
31-34
RealCMAC Imag
CMAC
15-30
31-34
ImagCMAC
15-30
0
1
Real
CMAC
31-34
O,Real
CMAC
0-14
Imag
CMAC
31-34
O,lmag
CMAC
0-14
1
0
RealAcc
16-19
RealAcc
0-15
ImagAcc ImagAcc
16-19
0-15
1
1
Reserved Reserved
Reserved Reserved
R016-19
ROO-15
1016-19
100-15
HSP45116
RING-18
IMING-1.
R.ENI#'
---,-'11--'-0--,
R.SHG-1
---,-1--,
----,
·••
·••••
·•••
••
COMPLEX
:
L-_ _......;=~- ACCUMULATOR L-_......;=~- :
----------_ ..... _-_ .... _-----------
----~
OUTMUXG-1
R.BINFMTI
R.BlNFMfT
OElEXTI _ _ _-'7_.....
~..,
1016-19
ENI.
SHG-1
R.ENI'
R.SHG-1
ACC
PEAK.
BINFMT.
R.PEAK'
R.BINFMT'
FIGURE 3. COMPLEX MULTIPLIER/ACCUMULATOR; All REGISTERS CLOCKED BY ClK
5-34
100-15
HSP45116
The Complex Accumulator duplicates the accumulator in
the CMAC. The input comes from the data shifters, and its
20 bit complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUXO-1
determines whether the accumulator output appears on
ROUT and lOUT.
icant bit, while the binary point of RO and 10 is to the right of
the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOM's for FFT applications.
TABLE 5. GROWTH ENCODING
The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DETO-1, is encoded as
shown in Table 5. If PEAK# is low, the highest value of
DETO-1 is latched in the Growth Detect Output Register.
DET1
DETO
NUMBER OF BITS OF GROWTH ABOVE 2 0
The relative weighting of the bits atthe inputs and outputs of
the CMAC is shown in figure 4. Note that the binary point of
the sine, cosine, RIN and liN is to the right of the most signif-
0
0
0
0
1
1
1
0
2
1
1
3
SIN/COS INPUT
14
13
12
11
10 1 9
-20.2-1
15
2-2
2-3
2-4
2-5
2-6
1 8
1 7
2-7
2-8
1 6
1 5
1 4
3
o
2
2-9 2-10 2-11 2-12 2-13 2-14 2-15
t
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, liN)
SH =00
15
14
13 112 111 110 1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
0
-2 0 . 2- 1
t
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, 10)
OUTMUX = 00
19
18
17
16
-2 4
23
22
21
15 114 113 112 111 110 1 9 1 8 1 7 1 6 1 5 1 4
3
2
0
2-10
2-11
2-12
2-13
2-14
2-15
5
1
2-3
2-4
22-6
2-7
2-8
2-9
0
2
.
22
r
t
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, 10)
OUTMUX = 01
19
-2 4
18
17
16
23
22
21
15 114 113 112 111 110 1 9 1 8 1 7 1 6 1 5 1 4
3
2
2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30
0
0
COMPLEX ACCUMULATOR OUTPUT (RO, 10)
OUTMUX = 10
19
18
17
16
15
-2 4
23
22
21
2 0 . 2-1
14 113 112 111 110 1 9
2-2
1 8
1 7
2-3
t
Radix Point
FIGURE 4. BIT WEIGHTING
5-35
1 6
1 5
4
3
2
0
HSP45116
HSP45116A Description and Operation
The operation of the HSP45116A is identical to the
HSP45116 with the exception of a programmable rounding
option added for the data outputs. The added functionality
was acheived by using one of the HSP45116's reserved
configuration registers to specify rounding precision and
replacing a Vee pin with a round enable (RND#) Input. When
RND# is "high", rounding is disabled, and the HSP45116A
functions as a pin-for-pin equivatent of the HSP45116. When
RND# is active "low" rounding is enabled. The RND# input
replaces Vee on PIN 75 of the 160 Lead MQFP package as
seen in the pinout diagram.
The Round Control Register is loaded by placing the round
control value on C15-0, setting AD1-0 = 11, setting CS# =0,
and forcing a low to high transition on the WR# input. The
rounding operation is determined by the least significant 8
bits loaded into the control register as shown in Table 6. The
least significant four bits (C3-0) loaded into the register
govem rounding of the real and imaginary outputs of the
Complex Accumulator (ACC). The next more significant four
bits (C7-4) govern the rounding of the complex outputs of
the complex multiply accumulator (CMAC). The real and
imaginary outputs from the CMAC or ACC are rounded to
the same precision. The rounding is perform by adding a
·one" to the bit poSition below the least signifcant bit desired
in the output. For example, for a configuration that rounds to
the most signifcant 20 bits of the CMAC output, a "one"
would be added to bit position 2- 14 (See Figure 4 for output
bit weightings).
TABLE 6. ROUNDING CONTROL
ROUND CONTROL REGISTER
C15-8
C7-4
C3-0
UNUSED
CMAC
ROUNDING
ACC
ROUNDING
XXXXXXXX
0000
0000
No Rounding
XXXXXXXX
0001
0001
CMAC outputs rounded to most significant 20 bits, bit positions _24 to 2.15
ACC outputs rounded to most significant 20 bits, bit positions _24 to 2.15
XXXXXXXX
0010
0010
CMAC outputs rounded to most significant 19 bits, bit positions _24 to 2.1•
ACC outputs rounded to most significant 19 bits, bit positions _24 to 2.14
XXXXXXXX
0011
0011
CMAC outputs rounded to most significant 18 bits, bit positions _24 to 2.13
ACC outputs rounded to most significant 18 bits, bit positions _24 to 2.13
XXXXXXXX
DIDO
DIDO
CMAC outputs rounded to most significant 17 bits, bit poSitions _24 to 2.12
ACC outputs rounded to most significant 17 bits, bit positions -2' to 2.12
XXXXXXXX
0101
0101
CMAC outputs rounded to most significant 16 bits, bit positions _24 to 2. 11
ACC outputs rounded to most significant 16 bits, bit positions -2' to 2. 11
XXXXXXXX
0110
0110
CMAC outputs rounded to most significant 15 bits, bit positions _24 to 2.10
ACC outputs rounded to most significant 15 bits, bit positions _24 to 2.10
XXXXXXXX
0111
0111
CMAC outputs rounded to most significant 14 bits, bit positions _24 to 2-9
ACC outputs rounded to most significant 14 bits, bit positions -2' to 2-9
XXXXXXXX
10DO
10DO
CMAC outputs rounded to most significant 13 bits, bit positions _24 to 2-8
ACC outputs rounded to most significant 13 bits, bit positions _24 to 2-8
XXXXXXXX
1001
1001
CMAC outputs rounded to most significant 12 bits, bit positions _24 to 2.7
ACC outputs rounded to most significant 12 bits, bit positions _24 to 2.7
XXXXXXXX
1010
1010
CMAC outputs rounded to most signifICant 11 bits, bit positions _24 to 2-8
ACC outputs rounded to most significant 11 bits, bit poSitions -2' to 2-8
XXXXXXXX
1011
1011
CMAC outputs rounded to most significant 10 bits, bit positions _24 to 2-5
ACC outputs rounded to most significant 10 bits, bit positions -2' to 2-5
XXXXXXXX
llDO
llDO
CMAC outputs rounded to most significant 9 bits, bit pOSitions -2' to 2-4
ACC outputs rounded to most significant 9 bits, bit positions -2' to 2-4
XXXXXXXX
1101-1111
1101-1111
ROUNDING OPERATION
Undefined
5-36
HSP45116
Applications
The NCOM can be used for Amplitude, Phase and
Frequency modulation, as well as in variations and
combinations of these techniques, such as QAM. It is most
effective in applications requiring multiplication of a rotating
complex sinusoid by an external vector. These include AM
and QAM modulators and digital receivers. The NCOM
implements AM and QAM modulation on a single chip, and
is a element in demodulation, where it performs complex
down conversion. It can be combined with the Harris
HSP43220 Decimating Digital Filter to form the front end of
a digital receiver.
~
ffi~
!ZS
UJa:
()LL
eLK
1______ - -
Modulation/Demodulation
Figure 5 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the center frequency register, and the modulating input is clocked into the real input of the CMAC, with the
imaginary input set to O. The modulated output is obtained
at the real output of the CMAC. With a sixteen bit, two's
complement signal input, the output will be a 16 bit real
number, on ROUTO-15 (with OUTMUX '" 00).
SIGNAL INPUT
32 1
1
_I
1
(1)0
1_ _ _ _
NCo~
~1
___
16
RO
FIGURE 6. QUADRATURE AMPLITUDE MODULATION (QAM)
Frequency Control Section, the frequency tuning resolution
equals the clock frequency divided by 232. For example, a
25M Hz clock gives a tuning resolution of 0.006Hz.
The NCOM also works with the HSP43220 Decimating Digital Filter to implement down conversion and low pass filtering in a digital receiver (Figure 7). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220's,
one each on the real and imaginary outputs of the
HSP45116, perform low pass filtering and decimation on
the down converted data, resulting in a complex baseband
signal.
~
><
MODULATED OUTPUT:$.
c
HSP45116
NCOM
LO
FIGURE 5. AMPLITUDE MODULATION
By replacing the real input with a complex vector, a similar
setup can generate QAM signals (Figure 6). In this case, the
carrier frequency is loaded into the center frequency register as before, but the modulating vector now carries both
amplitude and phase information. Since the input vector
and the internally generated sine and cosine waves are both
16 bits, the number of states is only limited by the characteristics of the transmission medium and by the analog electronics in the transmitter and receiver.
SAMPLED
INPUT
DATA
The phase and amplitude resolution for the Sine/Cosine
section (16 bit output), delivers a spectral purity of greater
than 90dBc. This means that the unwanted spectral components due to phase uncertainty (phase noise) will be greater
than 90dB below the desired output (dBc, decibels below
the carrier). With a 32 bit phase accumulator in the Phase/
5-37
SIN (wi)
INPUT
NCOM
OUTPUT
DDF
OUTPUT
FIGURE 7. CHANNELIZED RECEIVER CHIP SET
HSP45116
FFT Butterfly
Figure 8 shows a Fast Fourier Transform (FFT) implementation. The FFT is a highly efficient way of calculating the Discrete Fourier Transform [11. The basic building block in
FFTs is called the butterfly. The butterfly calculation involves adding complex numbers and multiplying by complex sinusoids. The Phase/Frequency Control Section and
Sine/Cosine Generator provide the complex sinusoids and
the CMAC performs the complex multiplies and adds.
r-
:--
ACC
B,A
r'--
-
B,A
R
r---
---
A
rr- -
B ""'-_ _ _ _ _ _ _ _ _---"'---~--... S'
k
-1
w
T w" --ROM
MOD
FIGURE 9. DECIMATION IN FREQUENCY BUTTERFLY
t
. : SEQUENCER
A'-A+B
B'=(A - B)W"
FIGURE 8. RADIX-2 FFT BUTTERFLY
The NCOM circuit shown implements the butterfly shown in
Figure 9. The two complex inputs A and B produce two
complex outputs A' and B' using the equations A' = A + B,
B'
(A - B)Wk where Wk
e-jwk
cos(wk) + Jsin(wk).
Two clock cycles are required to calculate the butterfly. A is
clocked into the chip first and then B is clocked in. The complex accumulator in the CMAC section adds A and B. The
=
A'
R
f0-
180,0
-..:::::-------------::;r------+
:--
CMAC
T
CMAC calculates (A - B)Wk as AWk + B(_Wk). -Wk is generated by phase shifting the ROM address 180 degrees using the phase modulation inputs. For radix-2 decimation in
frequency FFTs, the phase of the complex sinusoid starts at
o degrees and increments by a fixed step size (for each
pass) after each butterfly. The phase/frequency section is
initialized to 0 degrees and the frequency control loaded
with the appropriate phase step size for the pass. The resulting words, A' and B', are held in output registers and
multiplexed through the output pins for writing to memory.
Using a single NCOM clocked at 25M Hz, a 1024 point
radix-2 FFT can be computed in (ClK period) x (NI092N),
or 410 microseconds.
=
=
Circuitry is included to implement block floating point FFTs .
In block floating point, an exponent is generated for an entire block of data. To implement block floating point, the
maximum bit growth during a set of calculations is detected. The number of bits of growth is used to adjust the
block's exponent and to scale the block on the next set of
calculations to maintain a desired number of bits of precision. This technique requires less memory than true floating
point and yields better performance than fixed point implementations, though its resolution does not meet that of true
floating point implementations.
References
[11 Oppenheim, A. V. and Schafer, R. W., Discrete Time
Signal Processing, Prentice Hall
5-38
Specifications HSP45116
Absolute Maximum Ratings
Reliability Information
Supply Voltage ••••••••••••••••••••••••••••••••••••• +8.ov
Input, Output or VO Voltage Applied •••••• GND -0.5V to Vcc +
u.
Specifications HSP45116A Preliminary
AC Electrical Specifications
vcc = 5.0V ± 5%, TA = 0° to +70°C), (Note 1)
52MHz(-62)
{PReliMINARY)
SYMBOL
MIN
MAX
WRIl High
TWH
7
Setup Time ADD-I, CSIl to WRIl
TAWS
10
·
·
Hold Time ADO-I, CSIl from WRIl
T AWH
0
-
ns
Setup Time CO-15 to WRIl
Tcws
10
-
ns
Hold Time CO-15 from WRIl
-
ns
PARAMETER
TCWH
0
Setup Time WRIl to CLK
Twc
10
Setup Time MODD-l to CLK
T MCS
10
Hold Time MODO-l from CLK
T MCH
0
Setup Time PACI# to ClK
Tpcs
10
Hold Time PACI# from CLK
COMMENTS
ns
ns
·
·
ns, Note 3
·
-
ns
ns
ns
TpCH
0
-
ns
Setup Time ENPHREGII, ENCFREG#,
ENOFREG#, ENPHACII, ENTIREGII, ClROFRII, PMSEl, lOADlI, EN Ill, ACC,
BINFMTiI, PEAKII, MODPII2PIII, SHO-l,
RBYTllDIl to ClK
Tecs
10
-
ns
Hold Time ENPHREGII, ENCFREGII,
ENOFREGII, ENPHACII, ENTIREGII, ClROFRII, PMSEl, lOAD#, ENIII, ACC,
BINFMTlI, PEAKII, MODPV2PIII, SHO-l,
RBYTllDIl from CLK
TecH
0
·
ns
Setup Time RINO-18,IMIND-18 to CLK
Tos
10
ns
Hold Time RIND-18, IMINO-18 from ClK
TOH
0
·
·
ClK to Output Delay ROO-19, 100-19
Too
ns
Toeo
·
·
12
ClK to Output Delay DETO-l
12
ns
CLK to Output Delay PACOII
TPO
CLK to Output Delay TICOII
TTO
Output Enable Time OERII, OEIII, OEREXTiI, OEIEXTlI
Toe
Output Enable Time OUTMUXO-l
TMO
Output Disable Time
Too
Output Rise, Fall Time
TRF
·
·
·
·
·
·
ns
12
ns
12
ns
8
ns
14
ns
8
ns, Note 2
6
ns, Note 2
NOTES:
1. AC tests performed with C l
V 1H 3.0V, V 1HC 4.0V, V1l
=
=
=40pF, 10l =TBDmA, and 10H =-TBDmA. Input reference level for CLK =2.0V, all other inputs 1.5V. Test
=OV; VOH =TBDV, VOL =TBDV.
2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
changes.
3. Applicable only when outputs are being monitored and ENCFREGII, ENPHREGIl or ENTIREGIl is active.
5-42
Specifications HSP45116TM Preliminary
Absolute Maximum Ratings
Reliability Information
Supply Voltage ..................................... +8.0V
Input or Output Voltage Applied •.•.••.•• GND -0.5V to Vcc +O.5V
Storage Temperature Range ..•••....•.•.•.•• -65°C to +lSOOC
Junction Temperature ••••••.•••••..••..••..•..•...• +175°C
Lead Temperature (Soldering lOs) ••.•.•...•.......•..• 300°C
ESD Classification •••.•••.•.••...•..••.••..•.••... Class 1
Device Count ........................... 103,000 Transistors
CAUTION: Stresses abo... those listed in ·Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions abo... those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range ..................... +4.5V to +5.5V
DC Electrical Specifications
Operating Temperature Range •..••.....•...•. -55°C to +125°C
TA = -55°C to +125°C
SYMBOL
MIN
MAX
UNITS
Logical One Input VoHage
VIH
2.2
.
V
Vcc =5.5V
Logical Zero Input Voltage
VIL
-
0.8
V
Vcc= 4.5V
Logical One Input VoHage Clock
VIHC
3.0
-
V
Vce =5.5V
logical Zero Input Voltage Clock
VllC
·
0.8
V
Vee =4.5V
Output HIGH Voltage
VOH
2.6
V
10H = -4001lA, Vec = 4.5V (Note 1)
Output lOW Voltage
VOL
-
0.4
V
10l = +2.0mA, Vec = 4.5V (Note 1)
Input leakage Current
II
-10
+10
IlA
VIN = Vec or GND, Vee = 5.5V
Output or 110 leakage Current
PARAMETER
.
TEST CONDITIONS
10
-10
+10
leese
·
500
IlA
IlA
VOUT = Vee or GND, Vee = 5.5V
Standby Power Supply Current
Operating Power Supply Current
Iccop
·
-
150
mA
1= 15MHz, VIN = Vee or GND, Vee = 5.5V
(Notes 2, 4)
Functional Test
FT
VIN = Vee or GND, vee = 5.5V, (Note 4)
-
(Note 3)
NOTES:
1. Interchanging 01 lorce and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency, typical rating Is 10mAiMHz.
3. Tested as lollows: I = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other Inputs) = 2.6V, V il = 0.4V, VOH;;' 1.5V, and VOL S 1.5V.
4. Output per test load circuit with switch open and C l = 40pF.
AC Electrical Specifications
TA = -55°C to +125°C
-15 (15MHz)
PARAMETER
ClK Period
ClKHigh
SYMBOL
-25 {25.6MHz)
MIN
MAX
MIN
Tep
66
-
39
TeH
26
-
15
·
ClKlOW
Tel
26
WR#low
TWl
26
·
15
WR#High
TWH
26
·
15
Set-up Time; ADO-1, CS# to WR#
Going High
TAWS
20
-
18
Hold Time; ADO, AD1, CS# Irom WR#
Going High
TAWH
0
-
0
Set-up Time CO-15 Irom WR# Going High
Tcws
20
·
18
5-43
15
MAX
·
·
·
-
·
·
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
(NOTE 1)
CONDITIONS
Specifications HSP45116TM Preliminary
AC Electrical Specifications
TA = -55°C to +125°C
(Continued)
.25 (25.6MHz)
·15 (15MHZ)
PARAMETER
SYMBOL
MIN
TCWH
0
Twc
20
Set-up TIme MODO-l to ClK Going High
TMCS
20
Hold TIme MODO-l from ClK Going High
T MCH
0
Set-up Time PACI# to ClK Going High
Tpcs
25
Hold Time PACI# from ClK Going High
TpCH
0
Set-up Time ENPHREG#, ENCFRCTl#,
ENPHAC#, ENTICTl#, ClROFR#,
PMSEl#, lOAD#, ENI#, ACC, BINFMT#,
PEAK#, MODPI/2PI#, SHO-l, RBYTllD#
from ClK Going High
Tecs
20
Hold TIme ENPHREG#, ENCFRCTl#,
ENPHAC#, ENTICTl#, ClROFR#,
PMSEl#, lOAD#, ENI#, ACC, BINFMT#,
PEAK#, MODPI/2PI#, SHO-l, RBYTllD#
from ClK Going High
TecH
Set-up TIme RINO-1B, IMINO-IB to ClK
Going High
MAX
MIN
MAX
0
·
·
·
-
-
15
·
ns
0
-
0
-
ns
Tos
20
.
15
·
ns
Hold Time RINO-18,IMINO-18, to ClK
Going High
TOH
0
-
0
·
ns
ClK to Output Delay, AOO-19, 100-19
Too
·
40
-
25
ns
ClK to Output Delay, DETO-l
Toeo
-
40
ClK to Output Delay, PACO#
TPO
-
30
·
·
30
.
25
·
40
Hold TIme CO-15 from WA# Going High
Set-up TIme WR# to CLK High
ClK to Output Delay, TICO#
TTO
Output Enable Time, OER#, OEI#,
OEREXT#, OEIEXT#
Toe
OUTMUXO-l to Output Delay
TMO
.
-
UNITS
0
16
16
0
1B
-
(NOTE 1)
CONDITIONS
ns
ns
(Note 2)
ns
ns
ns
ns
27
ns
20
ns
20
ns
-
20
ns
-
28
ns
(Note 3)
NOTES:
1. AC testing is performed as follows: Vcc = 4.5V and 5.5V. Input levels (ClK Input) 4.0V and OV; Input levels (all other inputs) 3.0V and OV;
TIming reference levels (ClK) 2.0V; All others 1.SV. Output load per test load circuit with switch closed and C L = 4OpF. Output transition
is measured at VOH ~ 1.SV and VOL';; 1.5V.
2. Applicable only when outputs are being monitored and ENCFREG#, ENPHREG#, or ENTIREG# is active.
3. Transnion is measured at ±200mV from steady state voltage. Output loading per test load circuit, with switch closed and C L
=40pF.
Electrical Specifications
-25
·15
PARAMETER
Output Disable Time
SYMBOL
NOTES
MIN
·
·
·
Too
1,2
Output Rise TIme
TR
1,2
Output Fall Time
TF
1,2
MAX
MIN
MAX
UNITS
20
-
15
ns
8
ns
From 0.8V to 2.0V
8
ns
From 2.0V to 0.8V
8
.
8
-
CONDITIONS
NOTES:
1. The parameters in this table are controlled via design or process parameters and not directly tested. Characterized upon initial design
and after major process and/or design changes.
2. loading is as specified in the test load circuit with CL = 40pF.
5-44
HSP45116
Waveforms
eLK
TWL
1-
WR#
----~I__--- TWH
------<
_¥r--------{
I'~--------------------j
I~_ _ _ _ _ __
TAWS II__~~~.ITAWH
es#
----------------~~II/
-'k-
7f-
--------------------------~--~~-------------------TAWS 11__---1i----II TAWH
ADO-l------------------------~~
~?-------------------
TewS~L--~~.,~TeWH
eO-15
~
~Ir--,-----
~
-----------------------/1'--------'71(CONTROL BUS TIMING
TCp
TCH
CLK
7' f-
TCl
~
7
TM)k
MODO-1
-, ~
f-
fCH
)kPCH
TP*
PACI#,
CONTROL
INPUTS
RINO -19
IINO -19
TE~
~ECH
[TDH
TDi
*:
~DO
ROUTO-19
IOUTO -19
3
DETO -1
DEO
-TPO
PACO#"
CiTTO
TlCO#,
INPUT AND OUTPUT TIMING
5-45
"*
HSP45116
Waveforms
(Continued)
OER#,
OEI#,
OEREXT#,
OEIEXT#,
OUTMUXO -1
TOD
~:~------
Roo-19
ROO - 19 _ _ _ _-
#
..."'"
#
#
OEREXT
#
MOD LOAD
0
#
ENCF
IlEG
#
PACt PMSEL CU10rn ENT"""
#
GND
#
NPHAC
ENI
#
#
3
4
#
eLK
MOOA
I2PI
#
es
#
WR
AD
0
e
e
e
14
13
8
AD
1
e
e
e
15
10
9
Vee
GND
e
e
I.
#
5
e
• •
#
OUTMUK
OUTMUK
1
0
e
e
3
1
#
e
e
e
e
11
7
5
4
0
10
11
12
13
14
•
e
•
Ot:ILXf
#
OER
0
It
-,W
oCt::!
15
Z0
OW
(i)~
>
0
5·51
HSP457 76/883
Burn-In Circuit
PGA
PIN
PIN
NAME
(Continued)
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
D3
IMIN(O)
F4
03
ENPHAe#
Fl
K14
RO(2)
Vee/2
Al0
/0(18)
Vee/2
e2
RIN(18)
F9
P5
ENTIREG#
F4
L15
RO(3)
Vee/2
88
/0(19)
Vecl2
D2
RIN(17)
F8
04
ENI#
Fl
J14
RO(4)
Vee/2
e8
IMIN(18)
F9
E3
RIN(16)
F7
N6
MODPI/2PI# F16
J13
RO(5)
Vecl2
e7
IMIN(17)
F8
el
RIN(15)
F6
P6
es#
F2
K15
RO(6)
Vee/2
A7
IMIN(16)
F7
E2
RIN(14)
F5
05
eLK
FO
H14
RO(7)
Vecl2
A6
IMIN(15)
F6
Dl
RIN(13)
F4
P7
AD(l)
F4
H13
RO(8)
Vee/2
87
IMIN(14)
F5
F4
F3
RIN(12)
F16
N7
AD(O)
F3
G13
RO(9)
Vee/2
86
IMIN(13)
F2
RIN(ll)
F15
06
WR#
Fl
G15
RO(10)
Vee/2
e6
IMIN(12
F16
El
RIN(10)
F14
P8
e(15)
GND
F15
RO(ll)
Vee/2
A5
IMIN(ll)
F15
G2
RIN(9)
F13
N8
C(14)
GND
G14
RO(12)
Vee/2
85
IMIN(10)
F14
G3
RIN(8)
F12
N9
e(13)
GND
F14
RO(13)
Vee/2
A4
IMIN(9)
F13
Fl
RIN(7)
Fll
09
C(12)
GND
F13
RO(14)
Vecl2
A3
IMIN(8)
F12
H2
RIN(6)
FlO
010
C(11)
GND
E15
RO(15)
Vee/2
84
IMIN(7)
Fll
H3
RIN(5)
F9
P9
e(10)
GND
E14
RO(16)
Vee/2
e5
IMIN(6)
FlO
J3
RIN(4)
F8
Pl0
C(9)
GND
D15
RO(17)
Vee/2
83
IMIN(5)
F9
Jl
RIN(3)
F7
Nl0
C(8)
GND
e15
RO(18)
Vecl2
A2
IMIN(4)
F8
Kl
RIN(2)
F6
011
C(7)
GND
D14
RO(19)
Vee/2
e4
IMIN(3)
F7
J2
RIN(l)
F5
Pll
e(6)
GND
E13
10(0)
Vee/2
e3
IMIN(2)
F6
K2
RIN(O)
F4
012
C(5)
GND
e14
/0(1)
Vee/2
82
IMIN(l)
F5
K3
SH(l)
F3
013
e(4)
GND
815
10(2)
Vee/2
Al
Vee
None
Ll
SH(O)
F2
P12
e(3)
GND
D13
10(3)
Vee/2
A9
Vee
Vee
L2
Ace
F4
Nll
C(2)
GND
e13
10(4)
Vee/2
A15
Vee
None
Ml
ENPHREG#
F16
P13
e(l)
GND
814
10(5)
Vee/2
Gl
Vee
Vee
Nl
ENOFREG#
F4
014
C(O)
Vee
e12
10(6)
Vee/2
J15
Vee
Vee
M2
PEAK#
F8
N12
OUTMUX(l)
Fll
813
10(7)
Vee/2
01
Vee
None
L3
R8YTILD#
F16
N13
OUTMUX(O)
FlO
812
10(8)
Vee/2
07
Vee
Vee
N2
8INFMT#
F4
P14
OER#
FO
ell
10(9)
Vecl2
015
Vee
None
Pl
TleO#
Vecl2
M13
OEREXT#
FO
A13
/0(10)
Vee/2
A8
GND
GND
M3
MOD(l)
GND
N14
OEIEXT#
FO
811
/0(11)
Vee/2
A14
GND
None
N3
MOD(O)
GND
M14
OEI#
FO
A12
/0(12)
Vee/2
81
GND
None
P2
PAel#
F4
L13
PAeO#
Vee/2
el0
/0(13)
Vecl2
Hl
GND
GND
N4
LOAD#
F15
N15
DETO
Vee/2
810
/0(14)
Vee/2
H15
GND
GND
P3
PMSEL
Fl
L14
DETl
Vee/2
All
/0(15)
Vee/2
P15
GND
None
P4
eLROFR#
F4
M15
RO(O)
Vee/2
89
/0(16)
Vee/2
02
GND
None
N5
ENeFREG#
F4
K13
RO(l)
Vee/2
e9
10(17)
Vee/2
08
GND
GND
NOTES:
1. 47KO (±20%) resistor connected to all pins except Vee and GND
2. Vee - S.SV ± O.SV with 0.1 ~F (min) capacijor between Vee and GND per
position
3. FO = 100kHz ± 10%, F1
60% duty cycle
= FO/2, F2 = F1/2 ..... , F1 1 = F10/2, 40% to
4. Input Voltage limits: Vil
= O.SV max, VIH = 4.SV ±10%
5-52
HSP45116/883
Die Characteristics
DIE DIMENSIONS:
350 x 353 x 19 ±1 mils
WORST CASE CURRENT DENSITY: 1.6 x 105A/cm 2
METALLIZATION:
Type: SI-AI or Si-AI-Cu
Thickness: akA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
Metallization Mask Layout
HSP45116/883
(1) IMINO
(2) RIN18
(3) RIN17
(4) RIN16
(5) RIN15
(6) RIN14
(7) GNO
(6) RIN13
(9) RIN12
(10)RlNl1
(11) RIN10
(12) RIN9
(13) RIN6
(14) RIN7
(15) RIN6
(16) RIN5
(17) RIN4
(18) RIN3
(19) RIN2
(20) GND
(21) RINI
(22) Vcc
(23) RINO
(24) SHI
(25) SHO
(26) ACC
(27) ENPHREG #
(28) ENOFREG#
(29) PEAK#
(30) RBYTIW#
(31) BINFMT#
(32) GND
(33) TICO#
(34) Vec
(35) MODI
(36) MODO
(37) PAel#
(38) LOAD#
(39) PMSEL
......",:J!!!L.,
5-53
(117)GND
(116) 106
(115) 105
(114) 104
(113) 103
(112) GND
(111) 102
(110) 101
(109) Vee
(108) 100
(107) R019
(108) GND
(105) R018
(104) R017
(103) R016
(102) R015
(101) R014
(100) Vee
(99) R013
(98) R012
(97) ROtl
(96) GND
(95) R010
(94) R09
(93) Vee
(92) R08
(91) R07
(90) GND
(89) R06
(88) R05
(87) R04
(88) R03
(85) Vee
(84) R02
(83) ROI
(82) ROO
(81) GND
(80) DETI
(79) DETO
6
DOWN CONVERSION AND DEMODULATION
PAGE
DOWN CONVERSION AND DEMODULATION DATA SHEETS
HSP50016
Digital Down Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3
HSP50110
Digital Quadrature Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-25
NOTE: Bold Type Designates a New Product from Harris.
•
6-1
HSP50016
Digital Down Converter
January 1994
Features
Description
• 52 MSPS Input Data Rate
The Digital Down Converter (DOC) is a single chip synthesizer, quadrature mixer and lowpass filter. Its input data is a
sampled data stream of up to 16-bits in width and up to a 52
MSPS data rate. The DOC performs down conversion, narrowband low pass filtering and decimation to produce a
baseband signal.
• 16-Blt Data Input
• Spurious Free Dynamic Range Through Modulator
>102dB
• Frequency Selectivity: 104dB
• Filter ·3dB to ·102dB Shape Factor: <1.5
• Decimation from 64 to 131,072
Lowpass filtering is accomplished via a high decimation filter
(HDF) followed by a fixed finite impulse response (FIR) filter.
The combined response of the two stage filter results in a
-3dB to -102dB shape factor of better than 1.5. The stopband attenuation is greater than 106dB. The composite
passband ripple is less than O.04dB. The synthesizer and
mixer can be bypassed so that the chip operates as a single
narrow band low pass filter.
• IEEE 1149.1 Test Access Port
Applications
• Digital Radio Receivers
• Channelized Receivers
• Spectrum Analysis
The chip receives forty bit serial commands as a control
input. This interface is compatible with the serial 1/0 port
available on most microprocessors.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
HSP50016JC·52
O"C 10 +70"C
44 Lead PLCC
HSP50016GC-52
O"C 10 +70"C
48 Lead PGA
The output data can be configured in fixed point or single
precision floating point. The fixed point formats are 16, 24.
32, or 38 bit. two's complement. signed magnitude. or offset
binary.
The circuit provides an IEEE 1149.1 Test Access Port.
Block Diagram
16
,
DATA
CONTROL
TEST ACCESS
PORT
.10.
/
-
~
HIGH DECIMATION
RLTER
HIGH DECIMATION
RLTER
-
LOW PASS FIR
RLTER
f---.
LOW PASS FIR
FILTER
~
a:
I-w
~S
I-:e
5~
II.
-
OUTPUT
I--
~
cos
SIN
COMPLEX
SINUSOID
GENERATOR
CAUTION: These devices are sansitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
....!...
-
6-3
File Number
3288.3
HSP50016
Pinouts
48PINPGA
BOTTOM VIFEW
48 PIN PGA
TOPVIFEW
1
H
G
F
E
TDI
TOO
0
0
0
0
0
0
GND
vee
GND
vee
vee
GND
0
0
0
0
0
0
elK
DATAO
0
DATAl
DATA8
0
vee
GND
0
0
vee
D
0
B
DATA2
0
DATAS
GND
0
0
0
0
Q
GND
IQSTB
vee
0
1
0
IQClK
0
DATA14 DATA12
0
0
DATAl 0
0
vee
0
IQSTRT'
DATA7
RESEn
DATA9 DATAll
DATA6
0
TMS
0
0
I
A
0
TeK
vee
DATA4
e
DATA3
TRsn
0
0
0
DATA15
0
GND
0
3
7
8
cst
eDATA
eSTB
A
I
B
Q
GND
IQSTB
vee
vee
CClK
e
DATA4
vee
DATA6
DATA15
GND
DATA13
D
vee
DATA3
DATAS
DATA14 DATA12
GND
E
vee
GND
DATA2
DATA9
DATAll
vee
F
elK
DATAO
DATAl
DATA8
DATA7
DATAl 0
G
GND
vee
GND
vee
vee
GND
H
TDI
TOO
TRSTI
TeK
TMS
RESETI
eelK
0
0
eDATA
6
IQSTRTI IQClK
DATA13
0
vee
0
est
0
2
eSTB
0
0
0
0
0
2
3
6
7
8
44LEADPLCC
TOP VIEW
..
~~f!C
888~~f!~u
c !3u>
uu
nnnnnnnnnnn
cClO
z
____ U
/ 6 5 4 3 2 1 44 43 42 41 40
vee
DATA6
DATAS
DATA4
DATA3
vee
GND
elK
DATA2
DATAl
DATAO
•
C7
I::
C
!:
C
C
I::
C
C
C
C
8
9
10
11
12
13
14
15
16
17
39p GND
38
DATA15
37~ DATA14
36
DATA13
35~ DATA12
34P GND
33
DATAll
32~ DATA10
31 P DATA9
30P DATA8
DATA7
g
g
P
29P
1819202122232425 26 27 28
8~~';88~~';~~
>~ ... ~ ... > ~;~~
...
III
6-4
HSP50016
Pin Description
NAME
PLCCPIN
VCC
7,12,18,23,28,40
GND
6,13,19,27,34,39
DATAO-15
8-11, 15-17,29-33,35-38
I
Input data bus. Selectable between two's complement and offset
binary. DATAO is the LSB.
CLK
14
I
Clock for input data bus.
RESET#
26
I
RESET# Initializes the Internal state of the DOC. During RESET#, all
Internal processing stops. RESET# facilitates the synchronization of
multiple chips for Auto Three-State operation. If the Force bits In
control word 7 are Inactive and the IEEE Test Access Port is in an Idle
state, RESET# causes the laCLK, laSTS, I and a outputs to go to a
high impedance state.
DESCRIPTION
TYPE
-
+5V Power
Ground
All control registers are updated from their respective control buffer
registers on the third rising edge of CLK after the deassertion of
RESET#. If RESET# is deasserted TRR nanoseconds prior to the
rising edge of CLK, the Internal reset will deassert synchronously. If
T RR is violated, then the circuit contains a synchronizer which will
cause reset to be deasserted Internally one or more clocks later.
An initial reset is required to guarantee proper operation of the DOC.
Active low.
I
4
0
The I output has three modes: I data; I data followed by a data; real
data.
a
5
0
The a output has two modes: a data and the carry out of the Phase
Adder.
laCLK
3
0
laCLK: bit or word clock for the I and a outputs.
lasTS
1
0
lasTS: beginning or end of word indicator for I and a.
laSTRT#
2
I
Initiates output data sequence. Active low.
CDATA
44
I
Port for control data input.
CCLK
41
I
Control data input bit clock.
CSTS
42
I
Beginning of word indicator for control data.
CS#
43
I
Enables control data loading of DOC. Active low.
TCK
25
I
Bit clock for IEEE 1149.1 data.
TMS
24
I
Test port mode select.
TDI
20
I
Input data IEEE test port.
TOO
22
0
Output data for IEEE test port.
TRST#
21
I
Test port reset Active low.
6-5
MIXER
SECTION
HDF
SECTION
SCAUNG
MULTIPUER
g
ARSECTION
;p
17
:::s
SHIFT
REGISTER
MULTIPUERI
ACCUMULATOR
SHIFTER
C')
g:
!OJ
17
COEFACIENT
ROM
I
DATAO·15
MULTIPUERI
ACCUMULATOR
I
SJ
SHIFT
REGISTER
Q 11)'
~
~
FORMATTER
...l.-,
SCALE
• FACTOR
LOCAL
OSCILLATOR
~
0~
·22
~
5c:
IQSTS
::Il
m
CONTROL
BUFFERS CONTROL
0)
IQSTRTII
IQCLK
CSI--.ct
CSTB--.ct
DECODER
CDATA -----..
TCLK
II
CCLK
TMS
IEEE 1149.1
TEST ACCESS PORT
TDI
~~
RESETII
D
Q
D
Q
TRSTII
g~
....
TOO
HSP50016
Phase Generator Block Diagram
PHASEOFFSET
~
18
,
REG
PHASE WORD
,
PHASE
REGISTER
~
18
33
I'
33,.
PHASE ADDER
CARRY OUT
+
MUX SELECT 0
I
MODE
•
CONTROL
MAXIMUMPHASE - - 0
INCREMENT
MINIMUM PHAS E
INCREMENT - - 0
,
........
~
INITIALIZE
PHASEINCR.
.... TOMAX
3~
REG
INITIAUZE
PHASEINCR.
TO MIN
....
32
REG
,
MUXSELECT1
7
...
:::)
0
~
~
INCREMENT
24/
,
+
T
ADDISUBTRACT
FIGURE 2
6-7
I
PHASE
INCREMENT
REGISTER
II:
REG
CONTROL
.......~
DELTA PHASE
/
32
, '"
HSP50016
FuncUonalDescripUon
The primary function of the DOC is to extract a narrow band
of interest from a wideband input, convert that band to baseband and output it in either a quadrature or real form. This is
accomplished by centering the band of interest at OC by
multiplying the input data times a quadrature sinusoid. A
quadrature lowpass filter (identical reallowpass filters in the
in phase (I) and quadrature phase (0) processing branches)
is applied to the result. Each filtering chain consists of a
cascaded HDF and FIR fiiter, which extract the band of interest. During filtering, the signal is decimated by a rate which
is proportional to the output bandwidth. The bandwidth of the
resulting signal is the double sided passband width of the
lowpass filters. An Output Formatter manipulates the filter
output to provide the data in a variety of formats.
Local Oscillator
Signal data clocked into the DATA()'15 input of the DOC is
multiplied by a quadrature sinusoid in the Mixer section.
(See Figure 1). The data input to the DOC is a 16 bit real
data stream which is sampled on the rising edges of ClK. It
can be in two's complement or offset binary format.
The input data is passed to a mixer, which is composed of
two real multipliers. One of these multiplies the Input data
samples by the in phase (cosine) component of the
quadrature sinusoid and the other multiplies the input data
samples by the quadrature (sine) component. The in phase
and quadrature data paths are designated I and 0
respectively. The sine and cosine are generated in the local
oscillator as shown in Figure 1.
The local oscillator is programmed to produce a quadrature
sinusoid with programmable frequency and phase. The
frequency can be constant (Continuous Wave - CW), linearly
increasing (up chirp), linearly decreasing (down chirp), or
linear up/down chirp. The initial phase of the waveform is set
by the phase offset.
ment, maximum phasa increment, delta phase increment
and mode control. Mode control is used to select the function of the other parameters.
The phase offset Is the initial setting of the phase word going
to the SIN/COS Generator. Subsequent phases of the
sinusoid are calculated relative to this offset. The minimum
phase increment has two mode dependent functions: when
the SIN/COS Generator is forming a CW waveform, the
minimum phase increment is the phase step taken on every
clock. When the SIN/COS Generator is producing a chirped
sinusoid, the minimum phase increment is the smallest
phase step taken. Maximum phase increment is only used
during chirped modes; It is the largest allowable phase
increment. During chirp modes, the delta phase increment is
the difference between successive phase increments.
The four phase parameters are stored In their respective
registers in the Phase Generator. The Phase Register stores
the current phasa angle. On the first clock following the
deassertion of RESET#, the 18 MSBs of the Phase Register
are loaded from the Phase Offset Register. On every rising
edge of ClK thereafter, the output of the Phase Increment
Register is subtracted from the 32 lSBs of the current
phase. The 33 bit difference is stored back in the Phase
Register on the next ClK. The 18 most Significant bits of the
Phase Register form the phase word, which is the input to
the SIN/COS Generator.
Figure 3 gives a graphic representation of the four phase
parameters. To understand their interrelationships, the
phase should be visualized as the angle of a rotating vector.
When the local oscillator In the DOC is programmed to
generate a CW waveform, the multiplexers are configured so
that the Minimum Phase Increment is stored in the Phase
Increment Register; this value is subtracted from the output
of the Phase Register on every ClK and the difference
becomes the new Phase Register value. The Deita Phase
Increment and Maximum Phase Increment are ignored.
The phase, frequency and chirp limits of the quadrature
sinusoid are controlled by the Phasa Generator (Figure 2).
The output of the Phasa Generator is an 18 bit phase word
that represents the current phase angle of the complex
sinusoid. The Phasa Generator automatically increments the
phase angle by a preprogrammed amount on every riSing
edge of CLK. Stepping the output phase from 0 through full
scale (2 18 - 1) steps the phase angle of the quadrature
sinusoid from 0 to (_2+2_17)lt radians.The frequency of the
complex sinusoid is determined by the number of clocks
needed for the phasa to step though its full range of 2lt
radians. The required phase increment for a given local
oscillator frequency is calculated by:
Phase Increment
=233fdfs
PHASE OFFSET
~~:--~-..;o'" 0 RADIANS
PHASE INCREMENT
(1)
SUCCESSIVE
PHASES OF SINUSOID
where:
FIGURE 3. PHASE WORD PARAMETERS FOR CW CASE
fe is the desired local oscillator frequency
fs is the input sampling frequency
There are five parameters which control the Phase
Generator. They are: phase offset, minimum phase incre-
In up chirp mode the local oscillator generates a signal with
a linearly increasing frequency (Figure 4A). The Phase
Increment Register is initially loaded with the Minimum
Phase Increment value; on every clock, the contents of the
6-8
HSP50016
Phase Increment Register is subtracted from the current
output of the Phase Register. Simultaneously, the Delta
Phase Increment Register is added to the 24 lS8s of the
output of the Phase Increment Register. On the next ClK,
that sum is stored back in the Phase Increment Register, the
new phase is stored in the Phase Register and the process
is repeated. The phase increment is allowed to grow until the
next phase increment would exceed the maximum phase
increment value. When this happens, the Phase Increment
Register is reset to the minimum phase increment and the
cycle starts over again. Note that the phase increment is
never equal to the maximum phase increment. From the time
the Phase Generator starts at the minimum phase increment
until it reaches the maximum phase increment, the phase
word on clock n is given by:
Phase Word = Phase Offset - [Minimum Phase Increment
+ n(Delta Phase Increment))
In down chirp mode the local oscillator generates a signal
with a linearly decreasing frequency (Figure 5A). The maximum phase increment is loaded into the Phase Increment
Register and the phase offset value goes into the Phase
Register. The delta phase increment is subtracted from the
24 lS8s of the phase increment to form a new phase
increment at each clock. The phase increment is allowed to
diminish until it reaches the minimum phase increment
value, then it is reset to the maximum phase increment value
and the cycle is repeated. Note that the value of the phase
increment can be equal to, but never less than the minimum
phase increment, since the Phase Increment Register is
reloaded if the next phase increment value would be less
than the minimum phase increment. This feature protects
the DDC from exceeding the Nyquist frequency. In this case,
from the time the Phase Generator starts at the maximum
phase increment until it reaches the minimum phase
increment, the phase word on clock n is given by:
An example of the outputs of the Phase Increment Register,
Phase Register, and the I output of the SIN/COS Generator
are shown in Figure 48.
Phase Word
=Phase Offset - [Maximum Phase Increment
- n(Delta Phase Increment))
See Figure 58 for a graphical representation of this process.
*-----t->--I
FIGURE 5A. PHASE WORD DURING DOWN CHIRP
FIGURE 4A. PHASE WORD DURING UP CHIRP.
PHASE INCREMENT
PHASE INCREMENT
....... ~--MINIMUM
0 RADIANS
~
......................................................................
MAXIMUM
TIME
..............•.......•.•.....................•.........................
MINIMUM
I
I
PHASE WORD
o~h~~
TIME
......•....................•.............................•..•..•.....
PHASE WORD
I
6;:S~;~ ~ ~ ~ ~ ~
r'J\J\j'J\j,
TIME
TIME
COSINE OUTPUT OF SIN/COS GENERATOR
COSINE OUTPUT OF SIN/COS GENERATOR
~l+ -onl-+H-or- +-lVA-I-I-p+-HV~I-r- +'
I
IH-++jO (\+-++0+-+-(\O(\-t--+I
t-t-+-
~VVVVV\
TIME
FIGURE 58. DOWN CHIRP
FIGURE 48. UP CHIRP
6-9
TIME
HSP50016
In up/down chirp mode, the phase accumulator is set to the
phase offset value and the minimum phase Increment is
loaded into the Phase Increment Register. The delta phase
increment is added to the 24 lSBs of the Phase Increment
Register to form a new phase increment at each clock. The
pliase increment Is allowed to grow until It nears the
maxmum phase increment value (as defined in the up chirp
description). The delta phase Increment value Is then subtracted from the least significant bits of the Phase Increment
Register to form a new phase increment at each clock. The
phase increment Is allowed to diminish until it reaches the
minimum phase Increment value (as defined in the down
chirp description). The Phase Increment Register is then
reloaded with the minimum phase increment, and the up/
down cycle begins again. See Figure 6 for a graphical
representation of this process.
The minimum and maximum phase increments have allowable values from 0 to 2 32_1. This corresponds to the phase
increment:
The frequency resolution of the DOC = (frequency of ClK) I
(Number of Phase Register bits). At the maximum clock rate,
this results in a frequency selectivity of 52MHz/233 =
O.OO6Hz. The 18 bit phase word yields a phase noise Figure
of greater than 102dB.
Mixer
The Mixer performs quadrature modulation by multiplying
the output of the SIN/COS Generator by the Input data. The
outputs of the I and Q multipliers are symmetrically rounded
to 17 bits to preserve the 102 dB spurious free dynamic
range (SFDR). The result of the quadrature modulation process is passed to the High Decimating Filter (HDF) section.
High Decimation Riter
The High Decimation Filter (HDF) section is comprised of
two real HDF filters, one processing the I data branch and
one processing the Q data branch. Each branch has the
lowpass response shown in Figure 7. The undecimated
frequency impulse response is given by the equation:
H(f)
0< Phase Increment < x(! - 2.32) radians
The Delta Phase Increment parameter can take on values
from 0 to 224 - 1 which corresponds to the Delta Phase
Increment:
o < Delta Phase Increment < x(2-8 - 2.32) radians
The output of the phase accumulator forms the input to the
SIN/COS Generator which in tum produces a quadrature
vector which rotates clockwise: the outputs are cos(mn) and
-sin(mn). The outputs of the SIN/COS Generator are two's
complement values which are scaled to prevent overflow in
subsequent operations in the DOC under normal operation.
The scale factor has a negligible effect on the end to end
DOC gain.
PHASE INCREMENT
MAXIMUM
MINIMUM
~
•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.
TIME
....................................................................
=
The data path through the HDF was designed to ensure a
true 16 bit noise floor (approximately 98dB) at the output of
the DOC. The structure of the HDF filter used In the DOC Is a
five stage decimation filter. The width of each successive
stage decreases such that the lSBs are lost due to truncation [1). As a result, the data must be processed in the MSBs
of the filter so that the noise due to truncation is below the
required noise floor. This means that the input data of the
HDF must be shifted so that its output data fills the HDF
output word. The shift is a function of the desired HDF
decimation rate R and the number of stages, which is fixed
at 5. The shift is performed by the Data Shifter, which
positions the input data to the HDF for the maximum
dynamic range while avoiding overflow errors. The shift
factor is programmed into the Shift field of Control Word 4.
The value in this field is calculated by the equation:
Shift
PHASE WORD
=75 - Ceiling(5 log2(R))
0
}l\ll1/'d\/
~~\(~l]
ii
TIME
~
l!l
uV~V V Vl)
-
~
(2)
~
"-
5
COSINE OUTPUT OF SINlCOS GENERATOR
~ 0 AntI (\ A
=(Sin(1tf)/Sin(ltflR))5
=
In Figure 7, f' fslR, the input sample rate divided by the
HDF decimation factor. Figure 7 shows this curve from DC to
the first nUll. Note that the HDF is a true FIR filter; i.e., the
phase is linear.
Do
~
I
~
~
TIME
-120
o
FREQUENCY
f'
FIGURE 7. FREQUENCY RESPONSE OF HIGH DECIMATION
FILTER FROM DC TO FIRST NULL
FIGURE 6. UP/DOWN CHIRP
6-10
HSP50016
where R is the HDF decimation rate and Ceiling(X) denotes
the ceiling function of X; i.e., the result is X if X is an integer,
otherwise the result is the next higher integer.
Note that the Scale Factor falls in the interval [1,2). The
output of the scaling multiplier is symmetrically rounded to
17 bits.
The output data rate of the HDF is ClK divided by the HDF
decimation rate (programmed into the HDF Decimation field
in Control Word 5).
The binary formats of the inputs and outputs of the scaling
multiplier are as follows:
Scaling Multipliers
HDF Gain = R5/2Ceiling(5Iog2(R))
(3)
where R is the HDF decimation rate. The compensating
Scale Factor, which is input to both Scaling Multipliers, is
given by the equation:
Scale Factor
-102.3
=2Ceiling(51092(R))1R5
\
" 1 1 1_ _1
"11111'"
'
_ _ _ _1 1
_
(4)
~~
FREQUENCY
OVERALL RESPONSE
a
t,...--"
V- ~
o
~
FREQUENCY
PASSBAND ATTENUATION
\
-104.1
-120
1'/4
-0.03
0.15
-0.5
ao(-20). al(2- 1) a2(2-2) ... a16(2-16)
The Scaling Multiplier output is passed to the FIR Filter,
which performs aliasing attenuation, passband roll off
compensation and transition band shaping. The FIR Filter
Section is functionally two identical 121 tap lowpass FIR
filters, one each for the I and
channel. The two filters are
each implemented as sum of products, each with a single
multiplier, with the coefficients stored in ROM. The filters'
passbands are precompensated to be the inverse of the
response of the HDF. The frequency response of the FIR
filters is shown in Figure 8. The composite HDF and FIR
fiRer frequency response is shown in Figure 9. The FIR
coefficients are scaled so that the maximum gain of the
compOSite filter is less than or equal to OdS. The composite
passband ripple is less than O.04dS.
,
Ut.
o
Output:
o
........
-120
ao(-2'1. al(2-1) a2(2-2) ... a17(2- 17)
ao(20). al(2- 1) a2(2-2) ... a15(2- 15)
FIR Riter
The output of each HDF is passed to a Scaling Multiplier.
The Scaling Multipliers are used to compensate for the HDF
gain, which is between 1 (inclusive) and 0.5 (noninclusive),
or (0.5, 1.0]. The gain through the HDF is dependent on the
decimation factor: when the decimation is a power of two,
the HDF gain is equal to 1; otherwise, the gain must be
compensated for in the Scaling Multiplier. The HDF gain is
given by the equation:
0.15
Scale factor:
Input from HDF:
During RESET#, the HDF is initialized and will not output
any information until it is filled with new data.
VJ
IIIIIII
IIIIIII
~,~
::'I
o
V'
-0.10 ",",#,,
-0.5 0
0.06751'
,
.....
~
'I'
.-
--.r'~
FREQUENCY
OVERALL RESPONSE
~
r-...
--
1'/4
-- h
FREQUENCY
PASSBAND ATTENUATION
0.06751'
FIGURE 9. END TO END FREQUENCY RESPONSE OF DOC
FIGURE 8. FREQUENCY RESPONSE OF FIR FILTER
6-11
HSPSOO16
The coefficients of the filter are quantized to 22 bits to
preserve greater than 10SdB of stopband attenuation. The
sum of products of each filter output calculation is a 38 bit
number with 37 fractional bits.
When a quadrature output is selected, the outputs of the FIR
filters are decimated by a factor of four. When real output is
selected, only the I output is active. The output is decimated
by two in this case. When Filter Only mode is selected, only
the I filter path is active and its output is decimated by four.
The composite filter bandwidths are a function of the HDF
decimation rate and the FIR Filter shape. The double sided
bandwidths are specified by the following equations.
-3dB BW =0.13957 x f'
(5)
-102dB BW = 0.19903 x f'
(6)
TABLE 2. FORMAT FOR CONTROL WORD 1 - PHASE
GENERATOR I TEST ENABLE I OUTPUT
BIT
POSITION
FUNCTION
Address
001
36
Update
0= No Control Register Update
1 Control Register Update
35-4
Minimum
Phase Increment
Bits 35-4 = 231 ...'Zl
3
Test Enable
0= Test Features Disabled
1 .. Test Features Enabled
2-0
Phase
Generator
Mode
000 = Filter Only
001 .. Normal Mode (CW)
010 = Reserved
011 = Up Chirp
100 = Reserved
101 = Down Chirp
110 = Reserved
111 = Up/Down Chirp
The circuit has two serial data outputs, I and a. The timing of
the output bits is referenced to laCLK and laSTB. There are
several modes of operation for the data and control lines, all
of which were designed to be compatible with common
microprocessors. These modes are programmed by loading
the appropriate control words (see Table 1 through Table 8).
auadrature data output can occur in one of two ways:
simultaneously or sequentially. The simultaneous method
clocks out the I and a data on their respective output pins.
The I followed by a method clocks I and a out sequentially
on the I output pin: the entire I word is serially clocked out
first, then the entire a word. In real data output mode, the
Formatter converts the quadrature data to real and clocks it
out serially on the I output pin. In all modes, the I and a
outputs return to the zero state after the last bit is
transmitted.
=Control Weird 1
39-37
Output Control
The I output has three modes: I data out; I data followed by
a data; and real data out. The a pin can output either a data
or the carry out of the Phase Adder. Both outputs can be
programmed to set the number of significant bits transmitted;
the arithmetic representation; the order of the bits, LSB or
MSB first; and the polarity of the data bits, high or low true.
The spectral sense of the output data Is selectable between
normal and reversed. The spectral orientation of the data is
selectable between baseband centered quadrature,
baseband offset quadrature, and baseband real. In addition,
the output drivers for I, a, IQCLK and laSTB can be
individually enabled or placed in a high impedance state
using Control Word 6. These options are explained below.
DESCRIPTION
=
TABLE 3. FORMAT FOR CONTROL WORD 2 - PHASE
GENERATOR
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
010= Control Word 2
36
Update
0= No Control Register Update
1 Control Register Update
35-32
Reserved
All zeroes
31-0
Maximum
Phase
Increment
Bits 31-0 = 231 ...'Zl.
=
TABLE 4. FORMAT FOR CONTROL WORD 3 - PHASE
GENERATOR I OUTPUT TIME SLOT
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
011 = Control Word 3
36
Update
o= No Control Register Update
35-32
Reserved
All zeroes
31-18
nmeSlot
Length
Time Slot length In IQCLK perIods; length = number of bits +
2. Bits 31-18 = 213 ...'Zl.
17-0
Phase Offset
Starting phase angle 01 phase
1 = Control Register Update
TABLE 1. FORMAT FOR CONTROL WORD (0) - CONTROL
REGISTER UPDATE
BIT
POSITION
FUNCTION
DESCRIPTION
=Control Word 0
39-37
Address
000
36
Update
o=No Control Register Update
accumulator; range = 0 to 2x.
Bits 17-0 = ~ ...218
Update
35-32
Reserved
All zeroes
6-12
HSP50016
TABLE 5. FORMAT FOR CONTROL WORD 4" PHASE
GENERATOR 1 HDF 1OUTPUT
BIT
POSITION
FUNCTION
TABLE 7. FORMAT FOR CONTROL WORD 6 "INPUT, OUPUT
FORMATS
BIT
POSI11ON
DESCRIPTION
FUNCTION
DESCRIPTION
39-37
Address
100 = Control Word 4
39-37
Address
110 = Control Word 6
36
Update
o =No Control Register Update
38
Update
o = No Control Register Update
1 = Control Register Update
1 = Control Register Update
35
35-33
Reserved
All zeroes
32-31
Output Spec!rUm
00 = No Up Conversion. Complex Output
01 = Up Convert by 1"/4. Real
Output
10 = Up Convert by 1"12, Complex Output
11 = Reserved Mode
30-7
Delte Phase
Increment
24 Bit Delta Phase Increment.
Bits 30-7 = 'J?3 ...2°.
6-1
HDFData
Shift
HDF input data shift (towards
LSB). Bits 6-1 =
2°.
Shift =75 - Ceiling(5 IogiR))
Spectral
Reverse
o = Normal output
0
ts...
=
BIT
POSITION
FUNCTION
Address
101 = Control Word 5
36
Update
o = No Control Register Update
1 = Control Register Update
20-5
4-3
Bits 34-29 =
28
IOCLK
Polarity
o = Output Data Stable On
IOCLKDuty
Cycle
o = IOCLK Active Time = CLK
IOCLK
Duration
o = Active During I or 0
25-24
IOCLKThree
State Control
00 = Three Stale IOCLK
01 = Enable IOCLK
1x = Auto-Three State Enable
IOCLK
23
IOSTB
Polarity
22
IOSTB
Location
o = Active High
1 =Active Low
o= IOSTB prior to the begin-
DESCRIPTION
39-37
35-21
1 = I and 0 data output on I pin
Time Slot
Number
26
TABLE 6. FORMAT FOR CONTROL WORD 5" HDF 1OUTPUT
o =I and 0 output separately
34-29
27
1 Spectrally Reversed output
I followed by
0
ts ...~.
Rising Edge Of IOCLK; IOCLK
high between I or 0 bit periods
when IOCLK Duration = O.
1 = Output Date Stable On
Falling Edge Of IOCLK; IOCLK
low between I or 0 bit periods
when iOCLK Duration =O.
period.
1 = 50% Duty Cycle
bit
periods only
1 = Active continuously
ning 01 the data word.
1 = IOSTB during the data
Word.
HDF
Decimation
Rate
HOF Decimation Factor Minus
1. Minimum Allowable Value =
15. Bits 35-21 = 214 ... ~.
Decimate by 32,768: Bits 35-21
= All Ones
21-20 -
IOSTBThree
State Control
Scaling
Multiplier
Gain
16 Bit Gain Compensation
Number With Values Between
o and 2, 2 Non Inclusive. Bits
20-5. ~.2"1 ...2"15.
00 = Three Stale IOSTB
01 = Enable IOSTB
1x - Auto Three State Enable
IOSTB
19
I Polarity
0= True data
1 " Inverted Data
16-17
Output
Format
00 = Two's Complement
01 =Offset Bimuy
10 - Sign Magnitude
11 "Single Precision Floating
Point Format
I Three State
Control
00 _ Three State I
01" Enable I
1x = Auto Three Stale Enable I
16
o Polarity
0= True data
1 = Inverted data
15-14
o Three State
Control
00 = Three State 0
01 = Enable 0
1x = Auto Three State Enable 0
13
Input Format
o- Offset Binary
12-0
IOCLKRate
2-1
Number Of
Output Bits
00 = 16 Bits
01 = 24 Bits
10 = 32 Bits
11.38Bits
0
Output Sense
0= LSB First
1 = MSB First
1 = Two's Complement
6-13
IIOCLK Rate, Bits 12-0 =
212 ... 2°.
HSP50016
TABLE 8. FORMAT FOR CONTROL WORD 7· TEST FEATURES
BIT
POSITION
FUNCTION
DESCRIPTION
3~7
Address
36
Update
111 = Control Word 7
o= No Control Register Update
1 = Control Register Update
35-14
Reserved
All zeroes
13
Data
o= Normal Data Input
12-11
FIR
Accumulator
Control
00 = Normal Accumulation
Q Strobe on
RollOver
o= Q carries normal data
Data can also be output in single precision floating point format. (See Table 9.) For all output data formats, the internal
calculations are performed in exact two's complement
integer arithmetic and the resulting data is converted in the
Output Formatter.
TABLE 9. FLOATING POINT FORMAT
SIGN
IE~: I
MANT~
I 0.2"1 to 2-28
Implied 1
1 = Force Input Data to 8000 Hex.
10
The I and Q pins can be programmed for either simultaneous or I followed by Q output. In simultaneous mode, the I
and Q data appear on the I and Q pins, respectively. Each
data sample is preceded by a leading zero bit, followed by
the output data, followed by a trailing zero bit. In I followed by
Q mode, the output data appears on the I pin, and consists
of a leading zero bit, then the I data, a trailing zero, a leading
zero, the Q data, and finally a trailing zero bit. In Figure 10
and Figure 11, the leading and trailing zero bits occur before
bit 0 and after bit N, respectively.
01 = No Accumulation
10 = Continuous Accumulation
11 = Reserved
1 = Q Strobes When Phase
Generator Rolls Over
o= Normal Output Response
9
Force Outputs
8
IQCLK Forced "BIt9= 1, Force IQCLK= Bit 8;
Data
Else Normal
7
IQSTB Forced " Bit 9 =1, Force IQSTB = Bit 7;
Data
Else Normal.
6
I Forced Data
5
Q Forced Data "Bit9= 1, Force Q = Bit 5; Else
Normal.
4-3
Bypass
" Bit 4 = 0 Sin Cos Generator
Normal, " Bit 4 = 1 bypass.
"Bit3 = 0 Scaling Multiplier Normal,
if Bit 3 = 1, then scale factor =1.
2
Reserved
Must be zero for proper operation
while Test Features are enabled.
1 = Force Outputs
1
0
Walt For RAM
Fun
IQCLK is used to delineate the bit or word timing of the I and
Q outputs. There are several options on the configuration of
IQClK, which are controlled with Control Word 6 (See Table
7). The frequency of IQCLK is programmed to be a fraction
of the elK frequency, from (elK rate)12 to (elK rate)18192
(See equation 7). If IQCLK Rate 0, then IQClK remains in
its inactive state and the output bits change on the rising
edges of elK.
"Bit 9 = 1, Force I = Bit 6; Else
Normal.
=
elK
IQCLK Rate = IQCLK Frequency-l
(7)
CLK
IQCLK
" Bit = 0, DOC will output data
normally after a reset, which will
include unpredictable data In data
RAMs. " bit = 1, no chip output will
occur until sufficient data RAM
locations are written.
IORO ---~tx BITN-1 X BlTN
A. IQCLK DUTY CYCLE: ACTIVE TIME. ClK PERIOD
(IQClK POLARITY. 0)
CLK
Disable Over- o= Normal Operation
flow Protection 1 =Disable Overflow Protection
IQCLK
When set for fixed point output, the output data can be in
two's complement, offset binary or signed magnitude form.
Data is converted to offset binary by complementing the
most significant bit of a two's complement number. The
length of the output data word can be 16, 24, 32 or 38 bits.
The first three options are symmetrically rounded to the lSB
of the output data; the fourth option represents the full 38 bit
width of the accumulator and so represents exact arithmetic.
The output has a saturation option to prevent possible overflow due to a step input at power up. When Overflow Protection is enabled the output Is forced to be either the most
positive or most negative number. Saturation is available in
all four fixed point output options.
lOR 0
-_..£......:iIoI.lIJI....J...I.i
IQCLK
IORO
I
BITO
I
BIT 1
:~
BITN
,
C. IQCLK DURATION: CONTINUOUS
IQCLK
IORQ
~~
I BIT 0 (!i!ijLu!±ifiX'iiTn
Do IQClK DURATION: ACTIVE DURING I OR 0 ONLY
FIGURE 10. TIMING FOR CLK, IQCLK, IQSTB, I AND Q
6-14
HSP50016
laClK can be programmed to be active only during I or a
output or it can be active continuously with the IQClK
Duration bit. Using the laClK Duty Cycle bit, IQClK is
selectable as either 50% duty cycle or to be high for one
period of ClK. In addition, the Formatter can be set so that
the data bits are clocked on either the positive or negative
edges of IQClK with the laClK Polarity bit. Figure 10 shows
the various modes of operation with laClK Polarity
programmed for active high operation.
Control word 6 also configures laSTB, as shown in Figure
11. When programmed for Active Prior to Data Word, laSTB
is high for one period of laClK and terminates
simultaneously with the beginning of the first data bit;
otherwise it goes active with the beginning of the first bit and
inactive with the end of the last bit. laSTB can be
programmed to be either active high or low.
IOCLK
10RO
IIQSTB
~~
I BITOIBIT1!~
IOCLK~~
f1iiii""'X]iiT~
,
_ ___,----~2
IOSTB
BITN-1
0ijiC\
~l----....,.\..
B. IOSTB ACTIVE DURING DATA WORD
FIGURE 11. IQSTB TIMING
To avoid the generation of multiple read cycles, laSTRn
must go inactive within 10 cycles of laClK after the initiation
of laSTB. The DOC will not update the output buffer again
until the current output cycle has completed. When
laSTRn is used in this handshake mode, it must consist of
pulses that satisfy the set up and hold requirements listed in
the AC Timing SpeCifications and the pulses must occur at a
rate of ClK/(HDF Decimation x 4 -1). This mode of operation
requires the Time Slot Number in control word 6 to be o.
When handshake mode is not used, laSTRT# should be at
a logic low.
~'~l-------A. IOSTB ACTIVE PRIOR TO DATA WORD
10RO
Data can be read out of the DOC on request through the use
of the laSTRn pin. After passing through the Formatter, the
I and a data are stored in output buffers, which are updated
at the end of the FIR Filter processing cycle. The laSTRT#
and laSTB lines form a two line handshake as shown in
Figure 12. laSTRT# initiates the request. If the buffer has
data in it, the DOC will begin an output data sequence on the
next edge of laClK. The DOC will then put out one bit per
laClK until the output cycle is complete. In I followed by a
mode, one laSTRT# will initiate an I output word followed by
a a output word. In real data output mode, one laSTRn will
initiate two samples of real data on the I pin.
Auto Three State mode for IQClK, laSTB, I and a allows
multiple chips to operate using common data and output
control lines. Each chip is assigned a Time Slot Number on
the bus to use for outputting its data. All outputs programmed for Auto Three State Mode are active during their
time slot and are in a high impedance state at all other times.
A time slot starts one ClK period prior to the beginning of
the first bit of I or a and ends (Time Slot length) ClK periods afterwards. Assignment of a time slot is with reference to
the deassertion of RESEn. The minimum possible Time
Slot length for a given application is:
lengthmin =[(Number of Output Bits + 2) x Modej + 1
(8)
Where Mode = 2 if the DOC is in either Real Output or I
Followed By a mode; else Mode 1.
=
IOSTRT#
Note that equation 8 Is useful in all modes for calculating the
number of IQClKs necessary to complete one output data
cycle. For a given decimation rate and output word length,
the maximum value in the laClK Rate field is:
~l :;;;~;___\
IOSTB
FIGURE 12. REQUESTED DATA OUTPUT TIMING
laCLKRatemax
Decimation) X 4~
= Floor [ ( HDF Length
-
1 (9)
min
CClK
~'-..rV\...r'-..
CDATA _ _UiIhJG~~
CSTB
CSt
~'~l---~21j!__--
l~
FIGURE 13. CONTROL WORD TIMING DIAGRAM
c=
Where Floor(X) represents the integer part of X.
Control Word Input
The DOC has eight 40 bit control words which are loaded
through the four pin control interface. The format and timing
of this interface is compatible with the serial interface timing
of most common DSP microprocessors (See Figure 13). The
words are shifted MSB first, where bit 39 of the control word
is the MSB. Bits 39 through 37 are the control word address,
i.e. the target control buffer. CSt must go low before bit 35 is
clocked in. All 40 bits of the control word must be loaded.
The formats of the control words are shown in Tables 1
through 8.
6-15
•
HSPSOO16
The control words are double buffered: each control word is
initially loaded into one of eight control buffers for subsequent down loading into the corresponding control register.
The internal circuitry of the DOC uses the control registers to
regulate its operation. Control buffers can be downloaded in
one of two ways. Loading a buffer register with bit 36 = 1
causes all control registers to be updated from their
respective control buffers when the current word is finished
loading. If bit 36 = 0, then only that control buffer is updated
and the operation of the DOC is not affected. All control registers are updated from their respective buffers on the third
rising edge of ClK follOWing the deassertion of RESET•.
Note that Control Word 0 is unique in that it is only used to
update the seven control registers, and it is recognized by
the DOC regardless of the state of CSt. In systems with
multiple DOCs, this allows the user to update the configuration of all chips simultaneously without using RESET••
To ensure that the control information is properly loaded, the
frequency of ClK must be greater than the frequency of
CClK. In addition, RESETI must remain Inactive during the
loading of a control word.
Test
The HSP50016 supports two types of testing. Control Word
7 can be used to verify the operation of the circuit through
the divide and conquer method. Setting the Enable Test Bit
(Control Word 1, bit 3) equal to a 1 enables the test features
controlled by Control Word 7. (This bit is in Control Word 1
so that Word 7 does not have to be loaded if the test features
are not being used.) The functions allowed by Control Word
7 are shown in table 8.
The DOC also has a Test Access Port (TAP). This port is full
conformant to IEEE Std. 1149.1 - 1990 - IEEE Standard Test
Access Port and Boundary-Scan. [2] The TAP supports the
following
instructions: BYPASS,
SAMPLE/PRELOAD,
INTEST, EXTEST, RUNBIST and IDCODE. In addition, there
are seven instructions called ROCNTlWD1-7. which read
the contents of the control words over the TAP. The address
bits and bit 36 are only used to determine the destination of
data during loading; they are not stored, so they are not read
out with this instruction.
For demonstration purposes let x(n) .. cos(OVl). The
multiplication then becomes:
u(n) = COS(OVl)(cos(COcn) - jsin(COcn))
.. 1I2[cos((Dlk - COc)n) + COS((Dlk + CIlc)n)
- j(sin((Dlk + COc)n) - sin((Dlk - COc)n)))
The signal u(n) is passed through a low pass filter; assuming
that the filter passes the low frequency terms with no
degradation and attenuates the high frequency terms
completely, the filtering operation produces the output:
v(n) = 112(c;os((Dlk - COc)n) + jsin((Dlk - mJn»
= 112e1("'k - "'c)n
When the magnitude of the input signal x(n) is one, the
magnitude of v(n) is 112. Both the I and Q channels are multiplied by a factor of two to yield:
w(n) = COS((Dlk - O>c)n) + jsin((Dlk - COc)n)
=e1("'k- "'c)n.
Figure 15 shows an HSP50016 in a single channel down
conversion circuit. Notice that the input data is only 12 bits,
so it is justified to the MSB of the DOC's input data. If a
smaller sample width is used, it is recommended that the
MSB of the data is input into DATA15, and the unused bits
are connected to ground. This alignment makes it easier to
locate the position of the MSB in the output data. Note that
the input is configured for offset binary arithmetic and the
output is set up for I followed by Q, which enables the use of
only one serial connection to the output processor. The
serial data clock of the processor and the Control Clock of
the DOC are driven by a TTL compatible oscillator. (IQCLK
cannot be used for this purpose since its frequency is
indeterminate until the DOC has been configured.) Note that
many processors provide a bit clock which eliminates the
need for the external oscillator.
The full description of the operation fo the DOC while under
the control of the TAP will be published in a separate document.
-"'C
B. DOWN CONVERSION AND FU.TERING
FIGURE 14. DOWN CONVERSION
MICROPROCESSOR
Applications
Down Conversion
The primary spectral operation in the DOC is down conversion
of an input signal to base band. See Figure 14. This process
is done in two steps: multiplication of the input waveform by an
internally generated quadrature sinusoid, I.e., modulation and
lowpass filtering to attenuate the unwanted spectral components. The unwanted spectral components have two sources,
the input signal and an artifact of the modulation process.
The modulation process can be written as:
SMHz
OSCILLATOR
u(n) = x(n)e1"'c = x(n)[cos(CIlc) - jsln(CIlc)]
Where x(n) is the real input data sequence, m= 21tf, and CIlc is
the frequency of the signal generated by the SINICOS
Generator.
6-16
FIGURE 15. CIRCUIT FOR SINGLE CHANNEL OPERATION
HSP50016
An example of the control word contents for this mode of
operation is given in Tables 10·15. In this setup, the DOC
has been configured for a constant down conversion fre·
quency, decimation by 64 and Test Features disabled. Bit
fields of three bits or less are in binary notation; longer fields
are in hexadecimal. Control words zero and seven are not
used.
TABLE14. SAMPLE FORMAT FOR CONTROLWORD5· HDFI
OUPUT
BIT
POSITION
TABLE 1O. SAMPLE FORMAT FOR CONTROL WORD 1 • PHASE
GENERATOR I TEST ENABLE
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
001 = Control Word 1
36
Update
1 = Control Register Update
35-4
Minimum Phase
Increment
Minimum Phase Increment
Computed according to
Equation 1.
3
Test Enable
o = Test Features Disabled
2-0
Phase Generator
Mode
001 = Normal Mode
FUNCTION
101 = Control Word 5
Address
36
Update
1 = Control Register Update
35-21
HDF Decimation
F = Decimation by 16 In HDF
20-5
Scaling Multiplier
Gain
8000 = Scaling Multiplier
Gain of 1.
4-3
Output Format
00 = Two's Complement
2-1
Number of Output
Bits
00 =16 BIts
0
Output Sense
1 = MSB First
TABLE 15. SAMPLE FORMAT FOR CONTROL WORD 6·
OUTPUT
BIT
POSITION
39-37
TABLE 11. SAMPLE FORMAT FOR CONTROL WORD 2· PHASE
GENERATOR
BIT
POSITION
DESCRIPTION
FUNCTION
39-37
FUNCTION
Address
DESCRIPTION
110 = Control Word 6
36
Update
1 = Control Regisler update
35
I followed by Q
1 = I and Q data output on I pin
34-29
Time Slot
Time Slot number = 0
28
IQClK Polarity
0= Data stable on rising edge of
IQClK
1 = Control Register Update
27
IQClK Duty Cycle
1 = IQClK duty cycle is 50%
All zeroes
26
IQClK Duration
1 = Active continuously
25-24
IQClKThree
Stale Control
01 = Enable IQClK
o = IQSTB active high
o = IQSTB active prior to the
DESCRIPTION
39-37
Address
010 = Control Word 2
36
Update
o= No Control Regisler Update
35-32
Reserved
31-0
Maximum Phase
Increment
All zeroes
TABLE 12. SAMPLE FORMAT FOR CONTROL WORD3· PHASE
GENERATOR I OUTPUT TIME SLOT
23
IQSTB Polarity
22
IQSTB Location
BIT
POSITION
21-20
IQSTBThree
State
01 = Enable IQSTB
19
I Polarity
o = I output active high
18-17
I Three State
Control
01 = Enable I
16
Q Polarity
o = Q output active high
15-14
Q Three State
Control
00 = Disable Q
beginning of the data word.
FUNCTION
DESCRIPTION
39-37
Address
011 = Control Word 3
36
Update
1 = Control Register Update
35-32
Reserved
All zeroes
31-18
Time Slot Length
All zeroes
17-0
Phase Offset
All zeroes
TABLE 13. SAMPLE FORMAT FOR CONTROL WORD 4· PHASE
GENERATOR IHDFI OUTPUT
BIT
POSITION
FUNCTION
Address
100 = Control Word 4
36
35-33
Update
1 = Control Register Update
Reserved
All zeroes
o= Do not up convert
o = Complex Mode
32
Up Convert
31
Real Mode
30-7
Delta Phase
Increment
All zeroes
6-1
Shift
37 = Decimal 55, the shift
corresponding to HDF decimation by 16
Spectral Reverse
Input Format
1 = Two's complement
12-0
IQClKRale
All zeroes = ClK used to clock
output bits
DESCRIPTION
39-37
0
13
o = No spectral reversal
Quadrature To Real Conversion
After the input data has been processed by the DOC, the
output can be converted into a real signal if desired. In that
case, the baseband centered quadrature signal is upcon·
verted so that the bottom of the spectrum is at baseband.
The real part of the upconverted Signal is taken as the out·
put. To satisfy the Nyquist criteria, the sample rate of the
resulting signal must be at least twice the minimum sample
rate of the I and
components of the quadrature signal.
This prevents one sideband from aliasing onto the other
sideband when the real part of the output signal is taken.
a
6·17
HSP50016
The spectrum of a quadrature signal which has been over
sampled by 2 is shown in Figure 16a. This represents the
output of the filters. As described in the previous paragraph.
the oversampling is a necessary feature of this process.
since the final signal will occupy twice the bandwidth of the
filter output. To prevent aliasing upon taking the real part of
the signal. it is necessary to perform an up conversion by f'"
4. where f" is the decimated sample frequency. (Note that fs
is defined as the input sampling frequency. f' is the input
sampling frequency divided by the HDF decimation rate R.
and f" is f' divided by the FIR decimation rate. f" is the output
sampling rate.) The up conversion function is:
ei2"nf"/4f"
=ei"nl2
For n = O. 1. 2. 3. 4 •... the output values of the local oscillator
in rectangular representation are: 1 + OJ. 0 + j. -1 + OJ. 0 - j. 1
+ OJ •.... Since the real half of the complex multiplication of the
local oscillator values by the filtered signal values (the
desired output is the real part of the product) require only
trivial operations. this up conversion is done in the Formatter.
Figure 16b shows the signal spectrum after up conversion.
Figure 16c shows the spectrum of the real output signal.
This sequence is multiplied by the output of the I and Q
branches of the filter:
w(n)
=cos«~ - roc)n) + jsin«~ - COc)n)
=
ei("'k - .,c)n.
yielding an output sequence:
y
=(RE(w(n)). IM(w(n))).
-RE(w(n+l)). -IM(w(n+l))).
RE(w(n+2)). IM(w(n+2))) •...
The Formatter contains the circuitry to shift the quadrature
output spectrum up by one half of the output sample
frequency f". This operation is independent of the function of
the Phase Generator and Mixer. The spectra of the outputs
of the Filter and Formatter are shown in Figure 17.
The setup is identical to the down conversion configuration.
except that the Up Convert bit is set in Control Word 4.
Continuing with the single tone example from the previous
section. the quadrature signal output from the FIR filters is:
w(n) = c~s«~ - COc)n) + jsin«~ - COc)n)
= el("'k - .,c)n
-'''/2
Multiplying w(n) by the up convert function and summing the
result is equivalent to the output sequence:
-,"'4
o
,"'4
'''/2
A. OUTPUT OF FIR FILTERS: SIGNAL OVERSAMPLED BY 2
=
y(n) 1 x cos«~ - COc)n).
y(n+l) = j xjsin«CIlk - CIlc)(n+l)).
y(n+2) -1 x COS«CIlk - roc)(n+2)).
y(n+3) -j x jsin«~ - CIlc)(n+3)).
y(n+4) 1 x cos«~ - CIlc)(n+4)) •...
=
=
=
y
=cos«~ - CIlc)n). -sin«~ - COc)(n+l)).
-COS«CIlk - COc)(n+2)). sin«~ - COc)(n+3)).
cos«~ - CIlc)(n+4)) •...
Or:
y = RE(w(n)). - IM(w(n+l)). - RE(w(n+2)). IM(w(n+3)).
RE(w(n+4)) •...
=
Since leiltn/21 1 and Iw(n)1
tions are required.
-'''/2
-."'4
o
,"'4
'''/2
B. FIRST OPERAnON IN FORMATTER:
UP CONVERT BY SAMPLE FREQUENCY' 4
=1. no further magnitude correc-
The setup for this application is similar to that of the down
conversion circuit given above. except the Output Formatter
is set for Real Mode (bit 31 in Control Word 4). This bit configures the part for up conversion by f"'4 and summing of the
real and imaginary parts of the filter output.
Up Conversion by ,"'2
This operation allows the user to exchange the positions of
the upper and lower halves of a down converted signal while
leaving each half unchanged. Quadrature up conversion by
f"'2 is performed by multiplying the output signal by ei2ltnf "/2
cos(21tnf"l2) + j sin(21tnf"'2). When sampled at a rate of f".
cos(21tnf"l2) takes on the values 1. -1. 1. -1 •... and sin(21tnf",
2) always = O. Thus. the up convert LO sequence is:
=
ei"n = 1 + jO. -1 + jO. 1 + jO •...
-'''/2
-."'4
o
'"/4
'''/2
C. SECOND OPERAnON IN FORMATTER: 1OUTPUT .. 1+ Q
FIGURE 16. QUADRATURE TO REAL CONVERSION OF AN
OUTPUT SIGNAL
6-18
HSP50016
Quadrature Spectral Reversal
Spectral reversal is often used to negate a spectral reversal
which has occurred due to a previous operation in the
processing chain. Examples of this are spectral reversal in
an analog down conversion or in a constructive aliasing
operation. The DOC gives the user the ability to convert the
signal to baseband in either forward or reverse fashion.
Quadrature spectral reversal is achieved by translating the
lower sideband of the input to baseband rather than the
upper sideband. This is implemented in the DOC by mixing
the input signal with ei21tfcn - that is, up converting the input
rather than down converting it. The resulting signal is:
=
=
u(n)
x(n)ei 2ltfcn x(n)[cos(Olen) + jsin(Olen))
Assuming x(n) COS(CIlkn),
=
u(n)
=cos(CIlkn)[cos(CIlcn) + jsin(Olen)]
=[COS((CIlk - Ole)n) + COS((CIlk + CIlc)n)
+ j(sin((CIlk + CIlc)n) - sin((CIlk - Ole)n))]
After quadrature filtering and correcting for the gain of 1/2,
we have:
w(n) = cos((CIlk - Ole)n) - jsin((CIlk - CIlc)n)
= COS(-(CIlk - CIlc)n) + jsin(-(CIlk - CIlc)n)
= COS((CIlc - CIljJn) + jsin((CIlc - CIlk)n)
ei("'c- "'k)n
=
-'''/2
-'''/4
0 '''/4 '''/2
A. OUTPUT OF AR ALTERS
-'''/2
-'''/4
0 '''/4
The appropriate spectral plots are shown in Figure 18. In up
conversion, the sine output of the SINICOS Generator is
negated so that the vector output of the Local Oscillator
rotates counter clockwise. This is implemented by setting the
Spectral Reverse bit in Control Word 4 to a one. Otherwise,
the setup for this mode is the same as the one for down
conversion.
Real Spectral Reversal
Real spectral reversal is simply quadrature spectral reversal
with quadrature to real conversion in the Formatter. The up
converted and filtered signal w(n) is upconverted again by f"l
4 in the Formatter. Each sideband of the result is spectrally
reversed from the sidebands that would have been produced
by down conversion with quadrature to real conversion. The
output spectrum is shown in Figure 19.
The setup for this application is similar to that of down
conversion, except in control word 4, where the Spectral
Reverse and Real Output bits are set to one.
High Decimation Riter Only
The DOC can be operated as a single high decimation filter.
This is done by setting the Phase Generator to Filter Only
and the Minimum Phase Increment and Phase Offset to o.
This multiplies the incoming data stream by a constant
hexadecimal 3FFFF in the I channel and 0 in the Q channel.
The HDF section of the circuit requires a minimum
decimation rate of 16 to allow sufficient time for the FIR to
compute its response. This mode of operation implements a
filter which has a decimation rate from 64 to 131,072. The
frequency response is shown in Figures 7, 8 and 9. Only the
I output has valid data in this mode; the Q output should be
set to high impedance state to reduce circuit noise.
'''/2
B. ALTER OUTPUT UP CONVERTED BY
OUTPUT SAMPLE FREQUENCY 12
-'''/2 -'"/4 0 '''/4 '"/2
A. OUTPUT OF ALTERS: SIGNAL OVERSAMPLED BY 2
FIGURE 17. UP CONVERSION BY F"'2
-"'2
-'''/4 0 '''14 '''/2
B. ARST OPERAll0N IN FORMATIER:
UP CONVERT BY SAMPLE FREQUENCY /4
c.
-'''/2 -'"/4 0 '"/4 '''/2
SECOND OPERATION IN FORMATIER: I OUTPUT = I + Q
B. UP CONVERSION AND ALTERING
FIGURE 18. UP CONVERSION OF FILTER OUPUT SIGNAL
FIGURE 19. QUADRATURE TO REAL CONVERSION OF AN
OUTPUT SIGNAL
6-19
•
HSP50016
MuHlchannel Operation
DATA
FROM
Several DOCs can be placed in parallel with each one
operating on a different frequency band. To minimize wiring,
their outputs can be configured so that they are connected
over a common serial bus. Each DOC is assigned a time slot
number (Control Word 6) and a time slot length (Control
Word 3). Each DOC in turn controls the bus for long enough
to output its data, then relinquishes the bus. The time slot
assignment and length are programmed at configuration
time. Up to 64 chips can be multiplexed in this manner.
I
IQCLK
IOSTB
IQSTATI
CLK
Alternatively, the processor can request data from each of
the DOCs asynchronously. In this setup, Requested Output
Mode is used. The Data Concentrator polls each channel
individually and is responsible for insuring that each channel
is polled before the output data is lost. The Data Concentrator is a custom circuit designed by the user. A block diagram
of such a system is shown in Figure 22. The interface
between the controller and the DOCs has been omitted for
the sake of clarity.
~
I--
~
CDATA ~
CCLK ~
CSTB ~
cst
CHIP SELECT
D~R
! - - AG-1S
!--
Figure 20 shows a block diagram of this configuration. The
DOCs are configured by the microprocessor by first writing a
logical 0 to its Chip Select line. The control words are written
to that part in any order. When the part has been configured,
CS# is written high again, and the next part is configured in
the same manner. Collisions are prevented by programming
each DOC with a unique Time Slot number, which holds its
output from 0 to 63 output word times before transmission.
Each part also has a Time Slot Length, whose minimum
value is given in equation 8. Note that a value greater than
the minimum can be used to give the processor time to
operate on the data
The corresponding configuration register setup is similar to
that of single channel down conversion, except for the Auto
Three State fields. In this example, the first DOC in the chain
is set to drive IQCLK; the others have this output set for high
impedance. (It makes no difference which DOC is chosen to
be the one to drive IQCLK, but it must be active
continuously.) The unused outputs are put in their high
impedance condition on the other DOCs to minimize power
consumption. Note also that this example shows all DOCs in
I followed by Q mode so that only one data line to the
microprocessor is necessary. Figure 21 gives the timing of
the output data.
MICROPROCESSOR
HSPSOO1&
AID
- r - - I DATAG-15
Alii
- - - - ! - - STAB
HSPS0016
f-t
I
IQCLK
IOSTB
IOSTRT.
DATAG-15
-L..t CLK
SYSTEM
CLOCK
CDATA
CCLK
CSTB
DR
CLKR
FSR
~
OX
CLKX
FSX
~
Cst
OSCILLATOR
FIGURE 20. CIRCUIT FOR MULTIPLE CHANNEL OPERATION
(AUTO THREE STATE)
4 x,.--!I----+I- --;-----f
! TIMESLOTO
! TIMESLOT1
TIMESLOTN-1
DOCO
--!1______~'~_DOC--1-x:t:__!~------~
i i i
FIGURE 21. TIMING FOR MULTIPLE CHANNEL OPERATION
(AUTO THREE STATE)
DATA
FROM
AID
References
DATA
CONCENTRATOR
HSPSOO1&
I
DATAG-15 IQCLK
IOSTB
IOSTATI
[1] Hogenauer, Eugene V., An Economical Class of Digital
Filters for Decimation and Interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing, April
1981
MICROPROCESSOR
CLK
RIW
STAB
HSPSO01&
[2] IEEE Standard Test Access Port and Boundary-Scan
Architecture, IEEE Std 1149.1 - 1990
CLK
SYSTEM
CLOCK
FIGURE 22. CIRCUIT FOR MULTIPLE CHANNEL OPERATION
(REQUESTED OUTPUT)
6-20
Specifications HSP50016
Absolute Maximum Ratings
Reliability Information
Supply Voltage .•.•••••.•...•..•.••••.••.•••.....••• +7.0V
Input, OUtput or VO Voltage .•...•..•.•. GNO-O.SV to vCC+O.sv
Storage Temperature Range ••.•...•..••.••.. -6SoC to +15O"C
Junction Temperature .•.•....•... +17Soo (PGA), +1S00C(PlCC)
lead Temperature (Soldering 10S) ••.•••..••.••...•..• +3000C
ESD ClassifICation •••.••..•..••.•••....•.••......• Class 1
Thermal Resistance
9JA
9JC
PGA Package.. .. ... .. . .. .. .. • ....
41"CJW
SoolW
PlCC Package .. .. .. .. .. .. .. .. .. ..
35°CIW
13°CIW
Maximum Package Power Dissipation at 70°C
PGA Package •.••••••.••.••••••.••.•••.•.•.••••• 1.9SW
PlCC Package .•..•......•.••.•.......•••••..••• 2.28W
Gate Count ••.••••••.••.••..•..••.•.......•• 65,000 Gates
CAUTION: Stl'flSSBS abo.... those listed In "Absolute Maximum Ratings" may cause permanent damage to the davIce. This is a stress only rating and operation
of the device at these or any other conditions aboWl those indicated in the operational sactions of this spacification is not impUed.
Operating Conditions
Operating Voltage Range ..•••.•.••••.•••••• +4.75V to +S.2SV
DC Electrical Specifications
Operating Temperature Range •••••••••••••••.•• OOC to +700 C
vcc = S.OV S%, T A = 0° to +700C
PARAMETER
SYMBOL
MIN
MAX
UNITS
Power Supply Current
Iccop
-
394
mA
Vcc = Max,ClK Frequency 52.6MHz
Notes 1,2
Standby Power Supply Current
ICCSB
-
SOO
IIA
Vee = Max, Outputs Not loaded
II
-Soo
10
IIA
Vcc = Max, Input = OVor Vcc
TMS, TOI, TRST#
-10
10
IIA
Vcc = Max, Input = OV or Vee
All other Inputs
Input leakage Current
TEST CONDITIONS
Output leakage Current
10
-10
10
V
Vcc= Max, Input = OV or Vee
Logical One Input Voltage
VIH
2.0
-
V
Vee = Max
logical Zero Input Voltage
Vil
-
0.8
V
Vcc=Min
logical One Input Vo~age: ClK, TRST#
VIHC
3.0
-
V
Vcc=Max
logical One Output V~ge
VOH
2.6
-
V
10H = -SmA, Vee = Min
logical Zero OUtput Voltage
VOL
0.4
V
10l = 5mA, Vcc = Min
Input Capacitance
CIN
-
10
pF
COUT
-
10
pF
ClK Frequency 1MHz
All measurements referenced to GNO. TA
= +2SoC, Note 3
Output Capacitance
NOTES:
1. Power supply current is proportional to frequency. 'TYPical rating is 7.SmAlMHz. Note that operation at maximum clock frequency will
exceed maximum junction temperature of device. Use of a heat sink and/or air flow is required under these conditions: recommended
heat sink is EG&G Wakefield 0106S0-40.
2. Output load per test circuit and Cl= 4OpF.
3. Not tested, but characterized at initial design and at major process/design changes.
6-21
Specifications HSP50016
AC Electrical Specifications
vcc = S.OV ±So/., TA = 0° to +700C, (Note 1)
-52(52.6)MHz
PARAMETER
PREUMINARY
.75(76.&) MHz
SYMBOL
MIN
MAX
MIN
MAX
CLKPeriod
Tcp
19
13
ClKHigh
TCH
7
·
·
TCL
7
·
·
·
5
ns
Setup TIme DATAQ.15 to ClK
Tos
7
·
ns
Hold Time DATAO-1S from ClK
ToH
1
RESET# Pulse Width
TRL
Tcp+ll
RESET#, IQSTRT# Setup TIme from ClK
T RS
10
·
·
·
·
·
10
TRH
1
-
ClK to I, Q, IQSTB, IQClK Delay
Too
.
lS
CCLKPeriod
Tccp
100
CCLKHigh
TCCH
40
-
CClKlow
TCCL
40
·
CDATA, CSTB, CSt Setup to CCLK
Tcos
30
CDATA, CSTB, CSt Hold from CCLK
TCoH
30
CClK low Setup to ClK
T CLS
30
CLKlow
RESET#, IQSTRT# Hold TIme to ClK
-
-
5
7
1
·
·
12
ns
·
·
·
ns
100
40
40
30
30
-
30
TATS
30
-
30
-
30
Hold Time On All Inputs from TCK
TATH
30
TTCS
30
TCK Hold TIme from ClK
TTCH
30
Output Enable Time from ClK
Toe
-
18
Output Disable TIme from ClK
Too
Output Enable time from TCK
TTOe
Output Disable time from TCK
TTOo
.
32
TRF
-
S
Output rise, fall time
18
32
ns
ns
TToo
TCK Setup Time to ClK
ns
·
TCK to TOO, Data delay
Setup Time On All Inputs to TCK
ns
40
40
40
ns
ns, Note 4
100
TTH
ns, Note 2
-
TTL
TCKHigh
ns, Note 2
100
TTRL
TTP
100
ns
30
TRST# Pulse Width
TCKPeriod
-
ns
-
30
TCKlow
TCHH
30
ns
-
1
Tcp+8
-
CClK High Hold from ClK
TEST CONDITIONS
ns
40
100
·
30
30
·
·
·
-
ns, Notes 2, 3
ns, Notes 2, 3, 6
·
·
ns
30
ns
-
ns
ns, NoteS
ns, NoteS
ns, Note 4
ns, Note 4
12
ns, Note 6
12
ns, Note 6
32
ns, Note 6
32
ns, Note 6
5
ns, Note 6
NOTES:
=
=
=
=
1. AC tests performed with C L 40 pF, 10L SmA, and 10H
V 1H 3.0V, V1HC 4.0V, V1L OV; VOH VOL 2.SV.
=
=
=
=-SmA. Input reference level for ClK, TRST# is 2.0V, all other inputs 1.SV. Test
2. These are asynchronous inputs; setup and hold times must only be maintained in order to predict which clock cycle they take effect
internally.
3. Timing must only be maintained when Update bit is active in control word data being loaded.
4. Special Timing relationship between TCK and ClK is required for Test Instructions RUNBIST, EXTEST and INTEST.
S. All inputs except TRST#, and only when TCK is driving internal clock.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process andlor
design changes.
6-22
HSP50016
AC Test Load Circuit
,,r," ..'-----------------------l,,
,,
OUT
~
*TEST HEAD l
CAPACITANCE
SI
:,
J
-
-
-
,,
:,
,,
,,,
,
,,,
,,
,
-
,
EQUIVALENT CIRCUIT
:
,----------.. --------- .. --------~
SWITCH S1 OPEN FOR Icess AND Iccop
Waveforms
TIMING RELATIVE TO elK
TCp
i--
TCH
{
ClK
./
Tos
DATA()'15,IQSTRT'
TCl
-
)~
TDH
c::
-K
-
TRH
-
-TRlRESETt
/
"
- -TRS
Too
~K.
I, Q, IQSTB, IQClK
TOE
2.7V
I, Q, IOSTB, IQClK
2.3V
Too
"'
I, Q, IQSTB, IQClK
/
TCLS
CClK
TCHH-
I'....
TTCS
TClK
........
.
..
)
:::)"
6-23
TTCH
-
HSP50016
Waveforms (Continued)
TIMING RELATIVE TO CCLK
1 - - - - - - - Tccp ------'J...I
TCCH --","",,--TCCL
CCLK
TCDH
Tcos
CDATA, esTB, est
TIMING RELATIVE TO TCK
TTCP
f--TCK
----/
TTRL
TRSTI
-
TTL
TlH
~
'"
-}
Tmo
Too, 1,0,
10STB, IOCLK
)K:
TATS
TAlH
<
ALL INPUTS
<
TTOE
2.7V
Too, I, O,IOSTB,IOCLK
2.3V .... t-
J
Too, I, 0, 10STB, IOCLK
'I
OUTPUT RISE AND FALL TIMES
2.0V
O.8V
6-24
TTOD
,
HSP50110
ADVANCE INFORMATION
Digital Quadrature Tuner
February 1994
Features
Description
• 10 bit Real or Complex Inputs
The Digital auadrature Tuner (oaT) provides many of the
functions needed for digital demodulation. These functions
include carrier LO. generation, symbol clock generation, preselection filtering, baseband AGC, and IF AGC error detec·
tion. The
OaT facilitates
many different digital
implementations of demodulator tracking loops, which allows
this chip to handle multiple modes andlor data rates simply by
loading a new set of control words.
• Frequency Selectivity <0.014Hz
• Data Rates to 60MSPS
• Third Order Cascaded·lntegrator-Comb (CIC) Filter
conflgureble as Integrate and Dump Filter (First Order
CIC) or Bypassable
• Decimation from 1-4096, or Set by Resampllng NCO
used for BH Synchronization
• Error Datectlon for External IF AGC Loop
• Internal AGC Loop for Output Level Stability
• BI·Dlrectlonal 8-Blt Microprocessor Interface
• Parallel or Serial Output Date Formats
The output of the complex multiplier is gain corrected and feed
into identical preselection filters on both the real and imaginary
processing legs. Each preselection filter is comprised of a deci·
mating low pass filter followed by a compensation filter. The decimating low pass filter is a 3 stage cescade-integrator-comb (CIC)
filter. The CIC filter can be bypassed, conftgured as an integrate
and dump filter with a sin(X)/X response, or a third order filter with
a (sin(X)IX)3 response. The decimation of the CIC filter stage
may be fixed from 14096, or it may be controlled by a re-sampiing NCO used for bit synchronization. The compensation filter
is user selectable for flattening the (sin(X)/X)N response of the
CIC. These onboard filters may be bypassed if custom extemal
filtering is required.
Applications
• Phase and Frequency Modulation
• VSAT, INMARSAT Systems
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
HSP5011OJC-60
O"C to +70OC
The oaT accepts digitized signals in either a real or complex
representation. The digitized band of interest is shifted to DC
through a complex multiplication by an intemally generated La.
The quadrature La is generated by a numerically controlled
oscillator (NCO) with a tuning resolution of approximately
14MHz at a clock rate of 60MHz and a spurious free dynamic
range of 6OdB. For added flexibility, a control interface is provided for real time phase and frequency updates.
PACKAGE
Level detectors are provided to generate error signals for
extemallintemal AGC loops. The OaT output is provided in
either serial or parallel formats to support interfacing with a
variety DSP processors or digital filter components. This
device is configurable over a general purpose a-bit parallel bidirectional microprocessor control bus.
84 Lead PLCC
Block Diagram
COMPLEX
MULTIPUER
10
10
REAL OR COMPLEX
INPUT DATA
'----4...:.,~ I DATA
x
....___.L.._+-___-I-_
i-:r:::t~:;;!::;:;;:;!:_.....
10
IFAGC
CONTROL
CARRIER
TRACKING CONTROL
10
'----1--1-+
Q DATA
__...J::::::;;--t"-.... SAMPLE STROBE
PROGRAMMABLE
CONTROL
CONTROUSTATUS.-t::::::::~8~::~::~IN~T~E~R~FA~C~E~~
________~::::::::~~]
BUS
CAUTION: These devices are sensitive to electrostatic discharge. Users should foUow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
6·25
SAMPLE RATE
CONTROL
File Number
3651
•
OS :)--------1 7
SPECIAL FUNCTION
PAGE
SPECIAL FUNCTION DATA SHEETS
HSP45240
Address Sequencer. . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
7-3
HSP45240/883
Address Sequencer. . .. . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
7-15
HSP45256
Binary Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-21
HSP452561883
Binary Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . .
7-34
HSP9520. HSP9521
Multilevel Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
7-42
...JZ
ceQ
Uti
Wz
D..::::I
(/)11.
7-1
HSP45240
Address Sequencer
February 1994
Features
Description
• Block Oriented 24-Blt Sequencer
The Harris HSP45240 is a high speed Address Sequencer
which provides specialized addressing for functions like
FFTs,1-D and 2-D filtering, matrix operations, and image
manipulation. The sequencer supports block oriented
addressing of large data sets up to 24-bits at clock speeds
up to 50MHz.
• Conflgurable as Two Independent 12-Blt Sequencers
• 24 x 24 Crosspoint Switch
• Programmable Delay on 12 Outputs
• MuHI-Chlp Synchronization Signals
Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the mapping of the 24 address bits at the output of the address generator to the 24 address outputs of the chip. As a result, bit reverse
addressing, such as that used in FFTs, is made possible.
• Standard IlP Interface
• 100pF Drive on Outputs
• DC to SOMHz Clock Rate
Applications
A single chip solution to readlwrite addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a programmable delay is provided on 12 of the address outputs.
• 1-0, 2-D FIHerlng
• Pan/Zoom Addressing
• FFT Processing
The HSP45240 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs, with the exception
of clock, are TTL compatible.
• Matrix Math Operations
Ordering Information
TEMPERATURE
RANGE
OOCto +70oC
68 Lead PLCC
HSP45240JC-40
OOC to +70oC
68 Lead PLCC
HSP45240JC-50
OOCto +700C
68 Lead PLCC
HSP45240GC-33
OOCto+70oC
68 Lead PGA
HSP45240GC-40
OOCto+700C
68 Lead PGA
HSP45240GC-50
OOCto +700C
68 LeadPGA
PART NUMBER
HSP45240JC-33
PACKAGE
Block Diagram
STARTOUTI
AOOVALt
DONE.
BLOCKDONE.
OUT12-23
STARTIN.
START
CIRCUITRY
SEQUENCE
GENERATOR
24
CROSS-POINT
SWITCH
OEH.
OUTG-11
OLYBLK
OEL.
BUSVl
00-6, est, AO, WR.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
7-3
File Number
2489.3
HSP45240
Package Pinouts
ADDRESS SEQUENCER HSP45240
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
~
Q N
~
5
5
~
~
0
~
~
N Q ~ ~
~
~ ~ Q
~.
~ ~
~
~
~8o~o8~88~88~888~
NC
NC
00
OUT12
01
GND
02
OUT11
03
OUT10
04
Vce
05
OUT9
06
OUTe
GNO
GND
WR#
OUT7
OUT6
AO
CS#
Vee
GND
OUT5
ClK
OUT4
GNO
VCC
RST#
OUT3
NC
NC
68 PIN GRID ARRAY (PGA)
(BOTTOM VIEW)
OEH.
L
DLY8LK START
OUT.
START
IN.
BLOCK
vee
DONE#'
GND
ADD
BUSV. DONE#'
OUT1
OUT2
Ne
OUTO
vee
Ne
OU13
Ne
Ne
RST.
vee
GND
OUT.
H
eLK
GND
OUT5
vee
G
eS.'lt
AD
OUT8
OU17
F
WR#
GND
GND
OUT8
E
D8
D5
OUTa
vee
D
D4
D3
OUl10
OUT11
e
D2
D1
GND
OU112
B
DO
Ne
OUT22
OUT21
GND
OUl18
OUT17
GND
OUll41-
Ne
Ne
GND
OUT23
vee
OUT20
OUY18
vee
OUT18
OUT15
OUT13
3
4
5
8
7
8
9
10
K
A
OEl#
VAl#'
7-4
11
HSP45240
Pin Descriptions
NAME
TYPE
PlCC
PIN
NUMBER
DESCRIPTION
VCC
I
6,24,34,41
49,55,68
GND
I
3,9,18,22
38,46,52
58,65
RST#
I
25
RESET: This active low input causes a chip reset which lasts for 26 clocks after RST# has
been de-asserted. The reset Initializes the Crosspoint Switch and some of the configuration
registers as described in the Processor Interface section. The chip must be clocked
for reset to complete.
CLK
I
23
CLOCK: The "ClK" signal is a CMOS input which provides the basic timing for address
generation.
WR#
I
19
WRITE: The rising edge of this input latches the data/address on 00-6 to be latched
into the Processor Interface.
CS#
I
21
CHIP SELECT: This active "low" input enables the configuration data/address on 00-6 to
be latched into the Processor Interface.
AO
I
20
ADDRESS 0: This Input defines 00-6 as a configuration register address if "high", and
configuration data if "low", (see Processor Interface text).
+5V power supply pin.
GROUND
DATA BUS: Data bus for Processor Interface.
00-6
I
11-17
OEH#
I
28
OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers for
OUT12-23.
OEl#
I
29
OUTPUT ENABLE lOW: This asynchronous input Is used to enable the output buffers for
OUTO-11.
STARTIN#
I
31
START-IN: This active low input initiates an addressing sequence. May be tied to
STARTOUT# of another HSP45240 for multi-chip synchronization. STARTIN# should only
be asserted for one ClK because address sequencing begins after STARTIN# is de-asserted.
DlYBlK
I
30
DELAY BLOCK: This active "high" input may be used to halt address generation on
address block boundaries (see Sequence Generator text). The required timing relationship of this signal to the end of an address block is shown in Application Note 9205.
OUTD-23
0
39,40,42,45,
47,48,50,51,
53,54,56,57,
59,62-64,66,
67,1,2,4,5,
7,8
OUTPUT BUS: TTL compatible 24-bit Address Sequencer output.
..JZ
ceQ
-.,..
fd(J
a.. Z
(/)::;)
t.&.
~lOCKDONE#
0
36
BLOCK DONE: This active low output signals when the last address in an address block
is on OUTO-23.
DONE#
0
37
DONE: This active low output signals when the last address of an address sequence
is on OUTO-23.
ADDVAl#
0
33
ADDRESS VALID: This active low output signals when the first address of an address
sequence is on OUTO-23.
STARTOUT#
0
32
START-OUT: This active low output is generated when an address sequence is
initiated by a mechanism other than STARTIN#. May be tied to the STARTIN# of other
HSP45240's for multichip synchronization.
BUSY#
0
35
BUSY: This active low output is asserted one ClK after RST# is de-asserted and will
remain asserted for 25 ClK's. While BUSY# is asserted a\l writes to the Processor Interface
are disabled.
:IF Denotes active low.
7-5
HSP45240
Functional Description
Address Register and a "0" to the adder. The result of this
summation is the first address in the first block of the address sequence. This value is stored in the Block Start Address register by an enable generated from the control section, and the multiplexers are switched to feed the output of
the Holding and Address Increment registers to the adder.
Address generation will continue with the Address Increment added to the contents of the Holding Register until the
first address block has been completed.
The Address Sequencer is a 24-bit programmable address
generator. As shown in the Block Diagram, the sequencer
consists of 4 functional blocks: the start circuitry, the
sequence generator, the crosspoint switch, and the processor interface. The addresses produced by the sequence
generator are input into the crosspoint switch. The
crosspoint switch maps 24 bits of address input to a 24 bit
output. This allows for addressing schemes like "bitreverse" addressing for FFT's. A programmable delay block
is provided to allow the MSW of the output to be skewed
from the lSW. This feature may be used to compensate for
processor pipeline delay when the sequence generator is
configured as two independent 12 bit sequencers. Address
Sequencer operation is controlled by values loaded into
configuration registers associated with the sequence generator, crosspoint switch, and start circuitry. The configuration registers are loaded through the processor interface.
Start Circuitry
The Start Circuitry generates the internal START signal
which causes the Sequence Generator to initiate an addressing sequence. The START signal is produced by writing the Processor Interface's "Sequencer Start" address
(see Processor Interface text), by asserting the STARTIN#
input, or by the terminal address of a sequence generated
under "One-Shot Mode with Restart" (see Sequence Generator section). Care should be taken to assert STARTIN#
for only one clock cycle to Insure proper operation. A programmable delay from 1 to 31 clocks is provided to delay
the initiation of an addressing sequence by delaying the internal START Signal (see Processor Interface text).
The Start Circuitry generates the output Signal ADDVAl#
which is asserted when the first valid output address is at
the pads. In addition, the Start Circuitry generates the
"STARTOUT#" signal for multichip syncronization. Note:
STARTOUT# is only generated when an addressing sequence is started by writing the "Sequencer Start" address
of the Processor Interface, or an internal START is generated by reaching the end of an addressing sequence produced by "One-Shot Mode with Restart".
An address block is completed when the number of
addresses generated since the beginning of the address
block equals the value stored in the Block Size register.
When the last address of the block is generated,
BlOCKDONE# is asserted to signal the end of the address
block (see Application Note 9205). On the following ClK,
the multiplexers are configured to pass the contents of the
Block Start Address and Block Increment registers to the
adder which generates the first address of the next address
block. An enable from the control section allows this value
to update the Block Start Address register, and the
multiplexers are switched to feed the Holding and Address
Increment registers to the adder for generation of the remaining addresses in the block.
The address sequence is completed when the number of
address blocks generated equals the value loaded into the
Number of Blocks register. When the final address in the
last address block has been generated, DONE# and
BlOCKDONE# are asserted to signal the completion of the
address sequence.
The parameters governing address generation are loaded
into five 24-bit configuration registers via the Processor
Interface. These parameters include the Start Address, the
beginning address of the sequence; the Block Size, the
number of addresses in the address block; the Address Increment, the increment between addresses in a block; the
Number of Blocks, the number of address blocks in a sequence (minimum 1); the Block Increment, the increment
between starting addresses of each block. The loading and
structure of these registers is detailed in the Processor
Interface text.
CU:~~ r-=~--=:------------'
Sequence Generator
START
ADDRESS
The Sequence Generator is a block oriented address generator. This means that the desired address sequence is
subdivided into one or more address blocks each containing a user defined number of addresses. User supplied configuration data determines the number of address blocks and
the characteristics of the address sequence to be generated.
STEP SIZE
TO
CROSSPOINT
SWITCH
START
ADDRESS
As shown in Figure 1, the Sequence Generator is subdivided into the an address generation and control section.
The address generation section performs an accumlation
based on the output of MUX1 and MUX2. The control section governs the operation of the multiplexers, enables loading of the Biock Start Address register, and signals completion of an address sequence.
BLOCK
ADDRESS
GENERATION
STEP SIZE
An address sequence is started when the control section of
the Sequence Generator receives the internal START signal
from the Start Circuitry. When the START Signal is received,
the control section multiplexes the contents of the Start
7-6
BLOCK
SIZE
MUX CONTROLSI
REGISTER ENA8l£S
CONTROL
DONE
NUMBER
OF
BLOCKS
8LOCKOONE
DLVBLK
MODE
FIGURE 1. SEQUENCE GENERATOR BLOCK
HSP45240
Three modes of operation may be selected by loading the 6bit Mode Control register (see Processor Interface). The
three modes of operation are:
1. One-Shot Mode without Restart Address generation halts
after completion of the user specified address sequence.
Address generation will not resume until the intemal
START signal Is generated by the Start Circuitry. When
the final address in the final block of the address sequence Is generated, both DONE# and BLOCKDONE#
are asserted and the last address Is held on OUTQ-23
(See Application Note 9205). 2.
2. One-Shot Mode with Restart: This mode Is identical to
One-Shot Mode without Restart with the exception that
the Start Circuitry automatically generates an Intemal
START at the end of the user specified sequence to restart address generation. The end of the address sequence is signaled by the assertion of DONE#,
BLOCKDONE#, and STARTOUT# as shown in Application Note 9205. In this mode, the first address of the next
sequence immediately follows the last address of the current sequence if start delay is disabled.
3. Continuous Mode: Address generation never terminates.
Address generation proceeds based on the Start Address, Address Increment, Block Size, and Block Increment Parameters. The Number of Blocks parameter is
ignored, and the DONE# signal is never asserted.
The Mode Control register is also used to configure the
Sequence Generator for operation as two independent 12-bit
address sequencers. In dual sequencer mode, the adder in
the sequence generator suppresses the carry from the 12
LSBs to the 12 MSBs. With the carry suppressed, two Independent sequences may be produced. These 12-bit address
sequences may be delayed relative to each other by programming the Mode Control register for a delay up to 7
clocks. This feature is useful to compensate for pipeline
delay when using dual sequencer mode to generate read!
write addressing.
The DLYBLK input can be used to halt address generation at
the end of any address block within a sequence. In addition,
DLYBLK can be used to delay an address sequence from
restarting if asserted at the end of the final address block generated under "One-Shot Mode with Restart". See Application
Note 9205 for the timing relationship of DLYBLK to the end of
the address block required to halt address sequencing.
"RSTr. In 1:1 mode the cross-point switch outputs are in the
same order as the input. More details on configuring the
switch registers are contained in the Processor Interface text.
Processor Interface
The Processor Interface consists of a 10 pin microprocessor
interface and a register bank which holds configuration data.
The data is loaded into the register bank by first writing the
register address to the processor Interface and then writing
the data. All auto address Increment mode is provided so that
a base address may be written followed by a number of data
writes.
The microprocessor interface consists of a 7 bit data bus (Do6), a one bit address select (AO) to specify Do-6 as either
address or data, a write input (WR#) to latch data into the Processor Interface, and a chip select Input (CS#) to enable writing to the interface. The Processor Interface input is decoded
as either data or address as shown by the bit map In Table 1.
Crosspoint Switch
The crosspoint switch is responsible for reordering the
address bits output by the sequence generator. The switch
allows any of its 24 inputs to be independently connected to
any of its 24 outputs. The crosspoint switch outputs can be
driven by only one input, however, one input can drive any
number of switch outputs. If none of the inputs are mapped
to a particular output bit, that output will be "low".
The input to output map is configured through the processor
interface. The 1/0 map is stored in a bank of 24 configuration
registers. Each register corresponds to one output bit. The
output bit is mapped to the input via a value, 0 to 23, stored
in the register. After power-up, the user has the option of
configuring the switch in 1:1 mode by using the reset input,
7-7
TABLE 1.
AO D6
D5 D4 D3 02 01
DO
REGISTER ADDRESSES
Switch Output Registers
1 x 0 n n n n n
Sequencer Starling
1 x 1 0 0 0 n n
Address
Sequencer Block Size
1 x 1 0 0 1 n n
Sequencer Number of
1 x 1 0 1 0 n n
Blocks
Sequencer Block
1 x 1 0 1 1 n n
Address Increment
Sequencer Address
1 x 1 1 0 0 n n
Increment
Mode Control
1 x 1 1 0 1 0 0
Test Control
1 x 1 1 0 1 0 1
Start Delay Control
1 x 1 1 0 1 1 0
Address Sequencer
1 x 1 1 1 1 1 1
"START"
DATA WORDS
Current Address Data
0 0 n n n n n n
(no address increment)
Current Address Data
0 1 n n n n n n
(address increment)
NOTES:
1. Table 1 "l(' means "don't care", and"n" denotes bits which are dec0ded as an address In address registers and data in data raglstars.
2. When WAf transitions '1lIgh" to write 1he Sequencer "Starr address
(1 x111111 ),It must remain high unlit altar a rising edge of clock. 0therwise, 1he sequencer "starf' signal win not be generated.
The register bank consists of a series of 6 bit registers which
may be addressed individually as shown in Table 1. The data in
these registers is down loaded into configuration registers in
the Start Circuitry, Sequence Generator, and Crosspoint Switch
when an address sequence is initiated by the intemal START
signal (see Start Circuitry). This double buffered architecture
allows new configuration data to be down loaded to the Processor Interface while an address sequence is being completed
using previous configuration data.
-,Z
ceQ
-I-
fdu
a. Z
(/)~
HSP45240
The register bank has five sets of four registers which contain address generation parameters. These parameters include: Address Start, Block Size, Number of Blocks, Block
Increment, and Address Increment. Each register set maps
to one of five 24-bit configuration registers in the Sequence
Generator block (see Sequence Generator). The mapping of
the 6-bit registers in the register bank to the 24-bit configuration registers is determined by the 2 LSB's of the register
address. The higher the value of the 2 LSB's the higher the
relative mapping of the 6-bit register to the 24-bit register.
For example, if the 2 LSB's of the register address are both
0, the register contents will map to the 6 LSS's of the configuration register.
OOx - Output Delay: Delays OUTO-11 from OUT12-23 by
the following number of clocks.
The register bank has 24 registers which contain the data
for Crosspoint Switch 1/0 mapping. These registers are
accessed via the 5 LSS's of the address for the Crosspoint
Mapping registers in Table 1. A value from 0 to 23 accesses
the mapping registers for OUTO-23 repectively. A value
greater than 23 Is Ignored. The output bit represented by a
particular register is mapped to the input by the 6-bit value
loaded into the register. If the value loaded into the register
exceeds 23, the correponding output bit will be "0". For
example, if the 5 LSS's of the Crosspoint Mapping address
are equal to 3, and the valued loaded into the register
accessed by this address is equal to 23, OUT3 would be
mapped to the MSB of the sequence generator output.
After a reset, the Mode Control, Test Control, and Start
Delay registers are reset as described in the section
describing each register's bit map; the Crosspoint Mapping
registers are reset to a 1:1 crosspoint switch mapping; the
registers which hold the five address generation parameters
are not affected.
To save the user the expense of alternating between
address and data writes, an auto address increment mode
is provided. The address increment mode is invoked by performing data writes with a "1" in the D6 location of the data
word as shown in Table 1. For example, the crosspoint
switch could be configured by 25 writes to the Processor
Interface (one write for the starting address of the
crosspoint mapping registers followed by 24 data writes to
those registers).
TABLE 2. MODE CONTROL REGISTER FORMAT
ADDRESS LOCATION: 1 xll 01 00
05
I
04
002
I
001
I
I
03
000
I
I
001
000
0
0
0
0
0
1
Output Delay of 1
0
1
0
Output Delay of 2
Output Delay of 0
0
1
1
Output Delay of 3
1
0
0
Output Delay of 4
1
0
1
Output Delay of 5
1
1
0
Output Delay of 6
1
1
1
Output Delay of 7
os -
Dual Sequencer Enable: Allows two independent
12- bit sequences to be generated.
A 24-bit sequence is generated.
Two 12-bit sequences are generated.
Mx - Mode: Sequencer Mode.
Ml
MO
0
0
0
1
One-Shot Mode with Restart
1
x
Continuous Mode (x = don't care)
One-Shot Mode without Restart
During reset, this register will be reset to all zeroes. This will
configure the chip as a 24-bit sequencer with zero delays
on the outputs. The chip will also be in one-shot mode without restart.
Start Delay Control Register
The Start Delay Control Register is used to configure the
start circuitry for delayed starts from 1 to 31 clock cycles.
Internal "START", external "START", and restarts will be
delay by the programmed amount. The structure of the Start
Delay Control Register is shown in Table 3.
TABLE 3. START DELAY CONTROL REGISTER FORMAT
ADDRESS LOCATION: lxll0110
Mode Control Register
The Mode Control Register is used to control the operation
of the sequence generator. In addition, it also controls the
output delay between the MSW and the LSW of OUTO-23.
The following tables illustrate the structure of the mode control register.
002
D5
I
D4
SDE
I
SD4
I
I
D3
SD3
I
I
D2
SD2
I
I
Dl
I
DO
SDl
I
SDO
SOE - Start Delay Enable: Enables "START" to be delayed
by the programmed amount. When Start Delay is enabled, a
minimum of "1" is required for the programmed delay.
Start Delay is Disabled.
Start Delay is Enabled.
SOx - Start Delay: Delays the "START" by the decoded
number of clocks.
02
I
01
I
DO
SD4
SD3
SD2
SDl
OS
I
M1
I
MO
0
0
0
1
Start Delay of 1
0
0
0
0
1
0
Start Delay of 2
0
0
0
1
1
Start Delay of 3
1
1
1
1
1
Start Delay of 31
SDO
During reset, this register will be reset to all zeros. This will
bring the chip up in a mode with Start Delay disabled.
7-8
HSP45240
CS - Counter Select: Selects which 12-bit word of the
down counters is muxed to the MSW of the address generator output.
Test Control Register
A Test Control Register is provided to configure the
sequence generator to produce test sequences. In this
mode, the sequence generator can be configured to multiplex out the contents of the down counters in the sequence
generator control circuitry, Figure 2. These counters are
used to determine when a block or sequence is complete.
As shown in Figures 1 and 2, the MSW or LSW in the down
counters is multiplexed to the MSW of the address
generator output. In addition, a test mode is provided in
which the sequence generator performs a shifting operation
on the contents of the start address register. The structure
of the Test Control Register is shown in Table 4.
Image Processing
BLOCKDONE
BLOCI +1250C
15
-
12
-
10
-
ns
Setup Time 00-6
toWR# High
TOS
9,10,11
-55OC.:5TA.:5+1250C
17
-
16
-
14
-
ns
Hold Time 00-6
fromWR#Low
TDH
9,10,11
-55°C :::;TAS: +1250C
a
-
a
-
a
-
ns
Set-up Time A,
CS#, to WR# Low
TAS
9,10,11
-55°C :5TA:::; +125OC
5
-
5
-
5
-
ns
Hold Time A ,CS#,
from WR# High
TAH
9,10,11
-550 C.:5 TA:5+1 250C
a
-
a
-
a
-
ns
Pulse Width for
WR#Low
TWRL
9,10,11
-550C !iTA :5+125OC
18
-
14
-
12
-
ns
Pulse Width for
WR#High
TWRH
9,10,11
-550C :::;TA:5+1250C
18
-
14
-
12
-
ns
la, 11
-550C.:s;TA:5+1250C
39
30
25
-
ns
12
-
10
-
ns
ns
Set-upTime
STARTIN#,
DLYBLK,to
to Clock High
TIS
9,10,11
-550C,:::;TA:5+1250C
15
-
Hold Time
STARTIN#,
DLYBLK,to
Clock High
TIH
9,10,11
-550C.:s;TA:5+1250C
a
-
0
-
a
-
ns
Clock to Output
Prop. Delay
onOUTO-23
TPDO
9,10,11
-550 C:::;TA:::;+1250C
-
18
-
16
-
14
ns
Clock to
Prop. Delay,
on STARTOUT#.
BLKDONE#,
DONE#,ADVAL#,
and BUSY#
TPDS
9,10,11
-550C :::;TA.:5 +1250 C
-
18
-
16
-
14
ns
9,10,11
-550C :::;TA.:5 +1250 C
-
22
-
20
-
15
ns
9,10.11
-550C :::;TA:::; +1250 C
WR# Cycle Time
9,
TWp
Output Enable
Time
TEN
RST # Low Time
TRST
Note 2
2 Clock Cycles
ns
NOTES:
,. A.C. Testing: VCC = 4.5V and 5.5V,lnpuls are driven al 3.0Vfor logic"'"
and O.OV for a Logic "0", Input and output timing measurements are made
at 1.5V for bolh a logic .. , .. and "'0". ClK is driven al 4.0V and OVand
measured at 2.0V.
2. Transition is measured at ±:200mV from steady state voltage with loading
as specnied by lesl load circuli and Cl - 40pF.
7-17
HSP4524 0/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS
SYMBOL
CONDITIONS
NOTES
-2S(2SMHz)
-33 (33MHz)
-40 (40MHz)
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TA=+2SOC
-
10
-
10
-
10
pF
Input
Capacitance
CIN
VCC=Open,
f= 1 MHz,
All measurementsare
referenced to
deviceGND.
1
Output
Capacitance
COUT
Vcc=Open,
f= 1 MHz,
All measurementsare
referenced to
deviceGND.
1
TA=+250C
-
10
-
10
-
10
pF
Output Disable
Delay
TOEZ
1,2
-550C STA.$ +125 0C
-
22
-
20
-
15
ns
Output Rise Time
TOR
1,2
-550C < TA.$. +1250C
-
5
ns
1,2
-55°C .$ TAS. + 125°C
5
-
5
-
3
TOF
-
5
Output Fall Time
3
ns
NOTES: 1. Parameters listed in Table 3 are controlled via design or process
parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or
design changes.
2. Loading is as
spec~ied
in the test load circuit with CL
TABLE 4. ELECTRICAL TEST REQUIREMENTS
METHOD
SUBGROUPS
Initial Test
CONFORMANCE GROUPS
100%/5004
Interim Test
100%/5004
-
PDA
100%
1
FinalTest
100%
2,3, SA, 8B, 10,11
-
1,2,3, 7,8A, 8B, 9,10,11
Samples/500S
1,7,9
GrOlJpA
GroupsC&D
7-18
= 40pF.
HSP45240/883
Burn-In Circuit
OEH#
DlYBU
Ne
Ne
OEl#
RST#
H
G
GND
OUT2
Ne
OUTO
Vee
Ne
OUTS
Vee
GND
OUT4
elK
GND
OUTS
Vee
es#
AD
OUTs
OUT7
GND
OUT8
Vee
START
IN#'
ADD
BUSY#' DONE#'
VAL.#"
68 LEAD
PIN GRID ARRAY
BOTrON VIEW
WR#
GND
D8
D5
OUT8
Vee
D
D4
D3
OUT10
cun1
e
D2
D1
GND
OUT12
B
DO
Ne
OUT22
OUT21
GND
OUT23
Vee
A
3
PIN
NAME
BLOCK
DONE.#"
CUT1
K
PGA
PIN
START
OUT#'
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
GND
OUTt8
OUT17
GND
CUT14
Ne
Vee
CUT1a
CUT15
OUT1a
9
10
OU12O OUT1e
4
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
Ne
11
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
A2
GND
GND
B9
OUT14
VecJ2
F11
OUT8
VecJ2
K6
BUSYB
VecJ2
A3
OUT23
VecJ2
e1'
02
FlO
Gl
eSB
F5
K7
DONEB
VecJ2
A4
Vee
Vee
e2
01
F9
G2
AO
F6
K8
OUTO
VecJ2
AS
OUT20
VecJ2
e10
GND
GND
Gl0
OUT6
VecJ2
K9
Vee
Vee
A6
OUT19
VecJ2
ell
0UT12
VecJ2
Gll
OUT1
Vee/2
Kll OUT3
VecJ2
A7
Vee
Vee
01
04
F12
Hl
eLK
FO
L2
OEHB
F13
AS
OUT16
VecJ2
02
03
Fl1
H2
GND
GND
L3
DLYBLK
F11
A9
OUT15
VecJ2
010
OUT10
VecJ2
Hl0
OUT5
VecJ2
L4
STARTOUTB
VecJ2
Al0
OUT13
VecJ2
011
OUT11
VecJ2
Hl1
Vee
Vee
L5
Vee
Vee
Bl
DO
F8
E1
06
F7
J1
RSTB
F14
L6
BLoeKDONEB VecJ2
B3
OUT22
VecJ2
E2
05
F13
J2
Vee
Vee
L7
GND
GND
B4
OUT21
VecJ2
E10
OUT9
VecJ2
J10
GND
GND
L8
OUT1
VecJ2
B5
GND
GND
Ell
Vee
Vee
J11
OUT4
VecJ2
L9
OUT2
VecJ2
B6
OUT18
VecJ2
F1
WRB
F4
K3
OELB
F12
B7
0UT17
VecJ2
F2
GND
GND
K4
STARTINB F6
B8
GND
GND
FlO
GND
GND
K5
ADVALB
VecJ2
NOTES:
1. Vee12 (2.7V ±1 0%) used for outputs only.
4. O.lpF (min) capacftor between Vee and GND per position.
2. 47KO (±20%) resistor connected to all pins except Vee and GND.
5. FO = 100KHz ±10%, F1 = FO/2, F2
60% Duty Cycle.
3. Vee - 5.5 ±0.5V.
6. Input voRage limits: V,L
7-19
= Fl/2
••... ,F11
= F1 0/2, 40% -
= 0.8V max., V,H = 4.5V ±10%.
HSP45240/883
Metallization Topology
DIE DIMENSIONS:
186 x 222 x 19 ±1 mils
METALLIZATION:
Type: Si - AI or Si-AI-Cu
Thickness: 8kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY:
1.8 x 105Ncm2
Metallization Mask Layout
HSP45240/883
OUT12
DO
GNO
01
OUT11
02
03
OUT10
04
Vee
OUT9
05
OUT8
06
GNO
GNO
OUT7
WR#
OUT6
AO
Vee
CS#
OUTS
GNO
ClK
OUT4
Vcc
GNO
RST#
OUT3
'II>
:z:
W
0
'II>
...I
W
0
lI::
...I
ED
'II>
Z
'II>
...I
~
I/)
rz: e
0
l-
0'11> 'II> 'II> c
0>- w w Z
< >
>
e
::I
~ rz:
C
'II>
I-
i=
<
~
(I)
(I)
z z
0
c
::I 0
ED c
lI::
0
0
...I
ED
7-20
"
I:! 1=::I
::I
0
0
o~
0::1
>
0
HSP45256
HARRIS
SEMICONDUCTOR
Binary Correlator
January 1994
Features
Description
• Reconfigurable 256 Stage Binary Correlator
The Harris HSP45256 is a high·speed, 256 tap binary
correlator. It can be configured to perform one· or two·
dimensional correlations of selectable data precision and
length. Multiple HSP45256's can be cascaded for increased
correlation length. Unused taps can be masked out for
reduced correlation length.
• 1·Bit Reference x 1, 2,4, or 8·Bit Data
• Separate Control and Reference Interfaces
• 25.6, 33M Hz Versions
• Configurable for 1·D and 2·D Operation
• Double Buffered Mask and Reference
The correlation array consists of eight 32·tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8·bit input
data with a l·bit reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
configured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The mask register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
• Programmable Output Delay
• Cascadable
• Standard Microprocessor Interface
Applications
• Radar/Sonar
• Spread Spectrum Communications
• Pattern/Character Recognition
• Error Correction Coding
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
PACKAGE
HSP45256JC·25
OOC to +70oC
84 Lead PLCC
84 Lead PLCC
HSP45256JC·33
OOC to
HSP45256GC·25
OOC to +70oC
85 Lead PGA
HSP45256GC·33
oOC to +70oC
85 Lead PGA
+70oC
The output of the correlation array (correlation score) feeds
the weight and sum logie, which gives added flexibility to the
data format. In addition, an offset register is provided so that
a preprogrammed value can be added to the correlation
score. This result is then passed through a user programma·
ble delay stage to the cascade summer. The delay stage
simplifies the cascading of multiple correlators by
compensating for the latency of previous correlators.
The Binary Correlator is configured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the control and reference registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
Block Diagram
DINO·7
256 TAP
CORRELATION
ARRAY
DREFO·7
WEIGHT
AND SUM
DCONTO·7
'B
CONTROL
AO·2
I
'"'"-
DELAY
[?r--CASCADE
SUMMER
DOUTO·7
AuxoUTo-e
CASOUTO·12
I
CASINO-12
CAUTION: These d9\lices are sensilive 10 electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-21
File Number
2814.3
HSP45256
Pinouts
l
K
J
DREF2
0
0Yee ALOADI
0 CLOADt
0 0o.
0
0
0
0
0
0
0
0
0
0
0
o
0
0
0
0
0
.,
0
0
DeOHT DeOHT
S
•
e
0
e
0
0
GND
0
0
0
C
ClK CASIN INDEX
PIN
0
0
0
0
DIN7
vee
DINO
DINS
0
•
0 0
• •
0
0
0
0
•
0
0
CA:IN CASIN CA~IN
0
C~IN
0
C~~IN
0
1
0
•
0
•
0
,.
0
C~N CASfUTCA!fU1C~OUT
0
0
CAS
OUT
7
CAS
OUT
10
CAS
or-
CAS
OUT
OND
CAS
OUT
12
•
a
OEC
DIN1
H
DREF DREF
5
•
VCC
DREF
0
GND
AUX
OUT
0
OND
AUX
OUT
2
AUX
O~
AUX
OUT
AUX
OUT
AI
AUX
DC?Nl DCON DC~Nl DCgNl OUT
1
AUX
OUT
7
AUX
OUT
Al
DC~Nl DC~Nl
AD
DC~Nl DC~Nl
•
74
CASOUTS
7.
CASOUT9
GND
72
CASOUT10
ClK
71
CASOUT11
VCC
70
GND
DIN7
5i
CASOUT12
DlN5
68
DOUTO
DINS
57
DOUTI
DIN4
66
DIN.
DOUlI
DOUT3
DIN2
65
64
DlNl
63
VCC
DlNO
52
DOUTS
51
DOUT5
DREF7
DOUT4
DREF5
DOUT7
DREFS
AUXOUTO
DREF4
AUXOUTI
DREF3
AUXOUT2
DREF2
AUXOUT3
DREFI
GND
DREFO
AUXOUT4
»~$H~HH~~~~~UU~~~~~~63
8a~~a~<~~~~~~~~~~5§55
§§§§§§§§O~i~~
OEA'
•
11
7·22
DOUT
• •
R
C
LOADI LOADI
TXFR
DOUT
or
•
DREF
2
11
•
AUX
•
K
•
DOUT DOUT
7
VCC DOUT
5S5555 Si
~~~~~~~~~~~i~~~~~~~~u
>~~~~
CAS
OUT
0
~I!i!~!!ii~
CASINO
•
CAS
OUT
DIN2
84 PIN PLCC
TOP VIEW
CASINI
3
11
OND
DIN.
GND C~U
,.
CASIN CASIN
a
12
DREF DREF
1
0
CAS
OUT
10
OUT
CAS
DlNO DREF
7
11
7
CAS
OUT
1
OUT
DOUT DOUT
•
CASIN1 CASIN3 CASiN6 CAstN CASOUTCASOUlCASOUTCASOUTCASOUTCASOU
CAS
DOUT
0 0
CASOUT CASOU
12
CAS
OUT
2
CAS
OUT
0
DIN6
DREF
,.
0 0 0
CASIN CASIN oee.
• •
o
DOUT4
0 0 0
elK CASINO tNDEX
CASIN CASIN CASIN CASIN
3
1
ONO _.001
0 DOUT6
0 ooUTS
0
V"
0 DOUT7
0 DOUT3
0
0
0
0
DOUTO ooUT1 DOUT2
0 0
GNO CASOUT
PlN
•
OND
AUXpUT AUX.pU
0 OREF7
0 OIN1
0
0 0 DIN'
0
DREF6 DlN3
0
0
0
DI. .
DINS
DIH8
0 0Vee
DON7
DING
F
• •
OC~NT DC~NT OEM ~OUT AUX"OUT AU~
DREFS OREF4
G
A CASIN CASIN CASIN CASIN CASIN CASIN
2
7
11
10
DC~ DC~NT DC~NT DCOHTOAU\OUT AUX70UT ~OU
0
OREF3 DREF1
H
TOP VIEW
0
lXFR'
0AI
85 PIN PGA
0
DREFO GND
0
85 PIN PGA
BOTTOM VIEW
•
5
HSP45256
Pin Description
SYMBOL
PlCC PIN NUMBER
Vee
16,33,63
TYPE
DESCRIPTION
The +5V power supply pin.
GND
14,35,55,70,77
DINO-7
17-24
I
The DINO-7 bus consists of eight single data input pins. The assignment of the active
pins Is determined by the configuration. Data is loaded synchronous to the rising edge
of CLK. DINO Is the LSB.
DOUTO-7
60-62, 64-68
0
The DOUTO-7 bus Is the data output of the correlation array. The format of the output
is dependent on the window configuration and bit weighting. DOUTO is the LSB.
Ground.
ClK
15
I
System clock. Positive edge triggered.
CASINO-12
1-13
I
CASINO-12 allows multiple correlators to be cascaded by connecting CASOUTO-12 of
one correlator to CASINO-12 of another. The CASIN bus is added internally to the
correlation score to form CASOUT. CASINO is the LSB.
CASOUTO-12
69,71-76,7B-B3
0
CASOUTO-12 is the output correlation score. This value is the delayed sum of all the
256 taps of one chip and CASINO-12. When the part is configured to act as two
independent correlators, CASOUTO-B represents the correlation score for the first
correlator while the second correlation score is available on the AUXOUTO-B bus. In
this configuration, the cascading feature is no longer an option. CASOUTO is the LSB.
OEC#
B4
I
OEC# is the output enable for CASOUTO-12. When OEC# is high, the output Is threestated. Processing is not interrupted by this pin. (Active low.)
TXFR#
36
I
TXFR# is a synchronous clock enable signal that allows the loading of the reference
and mask inputs from the preload register to the correlation array. Data is transferred
on the riSing edge of CLK while TXFR# is low. (Active lOW.)
DREFO-7
25-32
I
DREFO-7 is an B-bit wide data reference input. This is the input data bus used to load
the reference data. RLOAD# going active initiates the loading of the reference registers.
This input bus is used to load the reference registers of the correlation array. The manner in which the reference data is loaded is determined by the window configuration. If
the window configuration is 1 x 256, the reference bits are loaded one at a time over
DREF7. When the HSP45256 is configured as an B x 32 array, the data is loaded into
all stages in parallel. In this case, DREF7 is the reference data for the first stage and
DREFO is the reference data for the eighth stage. The contents of the reference data
registers are not affected by changing the window configuration. DREFO is the LSB.
RLOAD#
34
I
RLOAD# enables loading of the reference registers. Data on DREFO-7 is loaded into
the preload registers on the riSing edge of RLOAD#. This data is transferred Into the
correlation array by TXFR#. (Active low.)
DCONTO-7
41-4B
I
DCONT0-7 is the control data input, which is used to load the mask bit for each tap as
well as the configuration registers. The mask data is sequentially loaded into the eight
stages in the same manner as the reference data. DCONTO is the LSB.
CLOAD#
37
I
CLOAD# enables the loading of the data on DCONTO-7. The destination of this data is
controlled by A0-2. (Active low.)
A0-2
3B-40
I
AO-2 is a 3-bit address that determines what function will be performed when CLOAD#
is active. This address bus is set up with respect to the rising edge of the load signal,
CLOAD#. AO is the LSB.
AUXOUTO-B
50-54,56-59
0
AUXOUTO-B is a 9-bit bus that provides either the data reference output or the 9-bit
correlation score of the second correlator, depending on the configuration. When the
user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. When the user has programmed the chip to be one correlator,
AUXOUT0-7 represents the reference data out, with the state of AUXOUTO-B
undefined. AUXOUTO is the LSB.
OEM
49
I
The OEM signal is the output enable for the AUXOUTO-B output. When OEA# is high,
the output is disabled. Processing is not interrupted by this pin. (Active low.)
7-23
HSP45256
Functional Description
Weight and Sum Logic
The correlation array consists of eight 32-bit stages. The first
stage receives data directly from input pin DIN7. The other
seven stages receive input data from either an external data
pin, DINO-6, or from the shift register output of the previous
stage, as determined by the Configuration Register. When
the part is configured as a single correlator the sum of correlation score, offset register and cascade input appears on
CASOUTO-12. Delayed versions of the data and reference
inputs appear on DOUTQ-7 and AUXOUTQ-7, respectively.
The input and output multiplexers of the correlation array are
controlled together; for example, in a 1 x 256 correlation, the
input data is loaded into DIN7 and the output appears on
DOUT7. The configuration of the data bits, the length of the
correlation (and in the two- dimensional data, the number of
rows), is commonly called the correlation window.
The Weight and Sum logic provides the bit weighting and
final correlator score from the eight stages of the correlation
array. For a 1 x 256 1-D configuration, the outputs of each of
the stages are given a weight of 1 and then added together.
In a B x 32 (B-bit data) configuration, the output of each
stage will be shifted so that the output data represents an
B-bit word, with stage seven being the MSB.
Correia tor Array
The core of the HSP45256 is the correlation array, which
consists of eight 32-tap stages. A single correlator cell consists of an XNOR gate for the individual bit comparison; i.e.,
if the data and reference bits are either both high or both low,
the output of the correlator cell is high. In addition, two
latches, one for the reference and one for the control data
path are contained in this cell. These latches are loaded
from the preload registers on the rising edge of ClK when
TXFRit is low so that the reference and mask values are
updated without interrupting data processing.
The mask function is implemented with an AND gate. When
a mask bit is a logic low, the corresponding correlator cell
output is low.
The function performed by one correlation cell is:
(Di,n XNOR Ri.n) AND Mi.n
where:
Di.n = Bit i of data register n
=Bit i of reference register n
Mi.n =Bit i of mask register n
Ri.n
The reference and mask bits are loaded sequentially. N bits
at a time. where N depends on the current configuration
(See Table 3). New reference data is loaded on the riSing
edge of RlOADit and new mask data is loaded on the rising
edge of ClOADit. The mask and reference bits are stored
internally in shift registers, so that the mask and reference
information that was loaded most recently will be used to
process the newest data. When new information is loaded in,
the previous contents of the mask and reference bits are
shifted over by one sample. and the oldest information is
lost. There are no registers in the multiplexer array (Figure
1), so the data on DOUTO-7 corresponds to the data in the
last element of the correlation array. When monitoring
DOUTO-7, AUXOUTO-B, and REFOUTO-7. only those bits
listed in Table 3 are valid.
The 13-bit offset register is loaded from the control data bus.
Its output is added to the correlation score obtained from the
correlator array. This sum then goes to the programmable
delay register data input.
When the chip is configured as dual correlators, the user has
the capability of loading two different offset values for the two
correlators.
The Programmable Delay Register sets the number of pipeline stages between the output of the weight and sum logic
and the input of the Cascade Summer. This delay register is
used to align the output of multiple correlators in cascaded
configurations (See Applications). The number of delays is
programmable from 1 to 16, allowing for up to 16 correlators
to be cascaded. When the HSP45256 is configured as dual
correlators, the delay must be set to 0000, which specifies a
delay of 1.
Cascade Summer
This is used for cascading several correlators together. This
value on this bus represents the correlation score from the
previous HSP45256 that will be summed with the current
score to provide the final correlation score. When several
correlators are cascaded, the CASOUTO-12 of each of the
other correlators is connected to the CASINO-12 of the next
correlator in the chain. The CASINO-12 of the first chip is tied
low. The following function represents the correlation score
seen on CASOUTO-12 of each correlator:
CASOUT(n) = (W7 x C07)(n-Delay) + (W6 x C06)(n-Delay) +
(W5 x C05)(n-Delay) + (W4 x C04)(n-Delay) +
(W3 x C03)(n-Delay) + (W2 x C02)(n-Delay) +
(W1 x COl )(n-Delay) + (WO x COO)(n-Delay) +
Offset (n-Delay) + CASIN.
where:
COO-C07 are the correlation score outputs out of the
correlation stages; WO-W7 is the weight given to each stage;
n-Delay represents the delay on the weighted and summed
correlation score through the Programmable Delay Register;
Offset is the value programmed into the Offset register;
CASIN is the cascade input.
7-24
HSP45256
RLOAD#
TXFR#
DlN7
DREF7
DIN6
DOUT0-7
R07
DREF6
DINO
R01
DREFO
MASK.
CON FIG.
t>UXOUT0-8
I-------,~~lCOO
C07
OEM
OFFAL#
OFFAM#
PROGRAMMABLE
DELAY
OFFBL.
OFFBM#
CONFIG.
DCONT0-7
CASIN0-12
MASK.
CONFlG#
AO-2 ___
OFFALII
DECODE
OFFAMII
CLOAD#
DELAYII
OFFBLII
OFFBM#
NOTE: All Registers Clocked With Clk
Unless Otherwise Specified
FIGURE 1. CORRELATOR BLOCK DIAGRAM
7-25
I
HSP45256
TABLE 1_ ADDRESS MAPPING
Control Registers
The 3-bit address value, AO-2, is used to determine which
internal register will be loaded with the data on DCONTD-7.
The function is initiated when CLOAD# is brought low, and
the register is loaded on the rising edge of CLOAD#. Table 1
indicates the function associated with each address. Table 2
shows the function of the bits in each of the registers.
A2
Al
AO
0
0
0
Mask Register
DESTINATION
0
0
1
Configuration Register
0
1
0
Offset Register A-Most Significant Bits
Offset Register A-Least Significant Bits
0
1
1
1
0
0
Programmable Delay Register
1
0
1
Offset Register B-Most Significant Bits
1
1
0
Offset Register B-Least Significant Bits
1
1
1
Reserved
TABLE 2. CONTROL REGISTER BITS
AQ-2
=000 Mask Register
MR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMRl
IMRO
=
MRO-7: Mask Register. When mask register bit N 1, the corresponding reference register bit is enabled. Mask register data is loaded from
the DCONTO-7 bus Into a holding register on the rising edge of CLOAD# and Is written to the mask register on the rising edge of TXFR#.
AQ-2
=001 Configuration Register
I
-
ICONFIG4
ITC
ICONFIG3
ICONFIG2
ICONFIGl
ICONFIGO
TC: Configures correlator for two's complement input. Inverts the MSB of the input data, where the position of the MSB depends on the
current configuration.
=
CONFIG4: The state of CONFIG4 sets up the HSP45256 as either one or two correlators. When CONFIG4 0, the HSP45256 Is configured
as one correlator with the correlation score available on CASOUTQ-12. When CONFIG4 =1, the HSP45256 is configured as dual correlators
with the first correlator's score available on CASOUTO-8 and the second score available on AUXOUTO-8. When the chip is configured as
dual correlators, the Programmable Delay must be set to 0000 for a delay of 1.
CONFIG2-3: Control the number of data bits to be correlated. See Table 3.
CONFIGO-l: CONFIGl and CONFIGO represent the length of the correlation window as indicated in Table 3.
AO-2
=010 MS Offset Register A
-
-
IOFFA12
IOFFA11
IOFFA10
IOFFA9
I
I
OFFA8-12: Most significant bns of Offset Register A. This is the register used in single correlator mode.
AO-2
IOFFA8
=011 LS Offset Register A
OFFA7
IOFFA6
IOFFA5
IOFFA4
IOFFA3
IOFFA2
I OFFAl
IOFFAO
I PDELAY3
IPDELAY2
I PDELAYl
I PDELAYO
OFFAQ-7: Least significant bits of Offset Register A.
AQ-2
=100 Programmable Delay
-
I
-
I
-
I
-
PDELAYO-3: Controls amount of delay from the weight and sum logic to the cascade summer. The number of delays is 1-16, with PDELAY
=0000 corresponding to a delay of 1 and PDELAY =1111 corresponding to a delay of 16.
AQ-2
=101 MS Offset Register B
- I
I
-
-
-
-
-
IOFFSETB8
I
I
I
I
OFFB8: Most significant bit of Offset Register B. In dual correlator mode, this register is used for the correlator whose output appears on
the AUXOUT pins.
AQ-2
=110 LS Offset Register B
OFFB7
IOFFB6
IOFFB5
IOFFB4
IOFFB3
OFFBD-7: Least significant bits of Offset Register B.
7-26
IOFFB2
IOFFBl
IOFFBO
TABLE 3. CONFIGURATION SETUP
CONFIGURAnON
~
4
3
2
1
0
NO.
OF
CORRELATORS
0
0
0
0
0
1
0
0
0
0
1
1
ACnVE INPUTS
DATA
BITS
ROWS
LENGTH
1
1
256
1
2
128
CORRELATOR
DIN
7
7
-
7,3
7,3
DREF
ACTIVE OUTPUTS
OUTPUT WEIGHnNG
AUXOUT
CASOUT
C07
C06
COS
C04
COO
CO2
C01
COO
7
7
12-0
1
1
1
1
1
1
1
1
7,3
7,3
12-0
1
1
1
1
1
1
1
1
DOUT
0
0
0
1
0
1
1
4
64
7,5,3,1
7,5,3,1
7,5,3,1
7,5,3,1
12-0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
e
32
7-0
7-0
7-0
7-0
12-0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
2
1
128
7,3
7
7,3
7,3
12-0
2
2
2
2
1
1
1
1
0
0
1
1
0
1
2
2
64
7,5,3,1
7,5
7,5,3,1
7,5,3,1
12-0
2
2
2
2
1
1
1
1
0
0
1
1
1
1
2
4
32
0
1
0
1
0
1
4
1
64
0
1
0
1
1
1
4
2
32
0
1
1
1
1
1
8
1
32
-
1
0
0
0
1
2
1
1
128
A
7-0
7,6,5,4
7-0
7-0
12-0
2
2
2
2
1
1
1
1
7,5,3,1
7
7,5,3,1
7,5,3,1
12-0
8
8
2
2
4
4
1
1
7-0
7,6
7-0
7-0
12-0
8
8
2
2
4
4
1
1
7-0
7
7-0
7-0
12-0
128
8
32
4
64
2
16
1
7
3
7
3
7
3
1
1
1
1
8-0
1
1
1
7,5
3,1
7,5
3,1
1
-1
-
1
7-4
3-Q
8-0
1
- 11
8-0
2
1
2
2
1
8
2
4
B
1
0
0
1
0
2
1
2
64
A
B
7,5
3,1
1
0
0
1
1
2
1
4
32
A
7-4
B
3-Q
7-4
3-0
A
7,5
3,1
7
3
7,5
3,1
7-4
3-0
7,6
3.2
7-4
B
A
7-4
3-Q
7
3
7-4
B
1
0
1
1
0
2
2
1
64
B
1
1
0
1
1
0
1
1
1
1
2
2
2
4
2
1
32
32
A
SPECIAL
FUNCTION
•
3-Q
3-Q
12-0
-
8-0
12-0
-
-
-
1
-
1
1
1
12-0
1
1
1
1
-
12-0
-
2
-
-
12-0
2
8-0
-
-
12-0
8-0
-
-
8
2
-
2
2
1
-
1
-
1
-
2
1
4
1
-
-
1
-
-
-
-
1
1
-
1
-
1
- 1-
I
~~
m
HSP45256
During reference register loading, the 8-bits, DREF0-7 are
used as reference data inputs. The falling edge of RLOAD#
initiates reference data loading; when RLOAD# returns high,
the data on DREFO-7 is latched into the selected correlation
stages. The active bits on DREFO-7 are controlled by the
current configuration.
The window configuration is determined by the state of control signals upon programming the control register. Table 3
represents the programming information required for each
window configuration. In Table 3, note that the data listed for
Output Weighting refers to the weights given to each of the
Correlation Sum Outputs (COO-7 in Figure 1).
During initialization, the loading configuration for the reference data is set by the user. Table 3 shows the loading
options. These load controls specify whether the reference
data for a given stage comes from the shift register output of
the previous stage or from an external data pin.
Single HSP45256 - 6-Blt Data, 32 Samples
An a x 32 correlation also requires only 1 HSP45256. To initialize the correlator, all the reference bits, control bits, the
value of the programmable delay, and the window configuration must be specified.
Again, the loading of the ~eference and mask registers can
be done simultaneously. Due to the programming initialization, DREFO-7 are used to load the reference data 8-bits at a
time. It will take 32 load pulses each of RLOAD# and
CLOAD# to load both arrays. Upon completion of the mask
and register loading, TXFR# is pulsed low, which transfers
the reference and control data from the preload registers to
the registers that store the active data.
TABLE 5. REGISTER LOADING FOR 8 X 32 CORRELATOR
WITH BINARY WEIGHTING
Applications
A0-2
OCONTO-7
NOTES
001
00001111
1 256-tap correlator; 8 x 32 window configuration, 8-bit data stream; relerence register
is loaded from DREF7 for all stages. Correlatorscore = (128 xC07) + (64 x C03) + (32
xC05) + (16 xC01) + (8 xC06) + (4 x C04)
+ (2 x C02) + COO
010
00000000
Offset Register A = 0000000010000
011
00010000
Single HSP45256 - l·Blt Data, 256 Samples
A 1 x 256 (l-D configuration) correlation requires only 1
HSP45256. To initialize the correlator, all the reference bits,
control bits, the delay value of the variable delay, and the
window configuration must be specified.
TABLE 4. REGISTER CONTENTS FOR 1 X 256 CORRELATOR
WITH EQUAL WEIGHTING
A0-2
001
OCONTO-7
00000000
100
00000000
Programmable Delay = 0
NOTES
101
00000000
1 256-tap correlator: 1 x 256 window
configuration, reference loaded from
DREF7, eight stages weighted equally,
DIN 7 and DOUT7 are the data input
and output, respectively.
110
00000000
Offset Register B = 0 (Loading optional in
this mode.)
010
00000000
011
00000000
100
00000000
Programmable Delay = 0
101
00000000
110
00000000
Offset Register B = 0 (Loading 01 this
register optional in this mode.)
This configuration performs correlation of an a-bit number
with a l-bit reference. Each byte out of the correlation array
gives an a-bit level of confidence that the data corresponds
to the reference. The correlation score is the sum of these
confidence levels.
Offset Register A = 0
Single HSP45256 - Dual Correlators, 2-Blt Data,
64 Samples
The loading of the reference and mask registers may be
done simultaneously by setting AO-2
000, setting the
DREF and DCONT inputs to their proper values and pulsing
RLOAD# and CLOAD# low. In this configuration, DREF7
loads the reference data and DCONT7 loads the mask information; both sets of data are loaded serially. It will take 256
load pulses (RLOAD#) to load the reference array, and 256
CLOAD# pulses to load the mask array. Upon completion of
the mask and register loading, TXFR# is pulsed low, which
transfers the reference and control data from the preload
registers to the reference and mask registers, updating the
data that will be used in the correlation. Reference and mask
data can be loaded more quickly by configuring the correlator as an 8 row by 32 sample array, loading the bits eight at a
time, then changing the configuration back to 1 x 256 to perform the correlation.
=
Dual 2 x 64 correlators require only one HSP45256. To initialize the correlator, all the reference bits, control bits, the
delay value of the variable delay, and the window configuration must be specified.
In this example, each of the dual correlators compares 2-bit
data to a l-bit reference. It will take 64 load pulses
(RLOAD#/CLOAD#) to completely load the reference and
mask registers in the array. The programmable delay must
be set to 0 for the output of the two correlators to be aligned.
7-28
HSP45256
TABLE 6. REGISTER LOADING FOR DUAL 2 X 64
CORRELATORS WITH EQUAL WEIGHTING
A0-2
DCONT0-7
NOTES
001
00010010
Dual correlators: each 2 bit dala, 64
taps; reference register for correlation
A is loaded from DREF7 and DREF5,
the reference register for correlator B is
loaded from DREF3 and DREF1. Correlator #1 = 2x C07 + 2 x C06 + C05 +
C04, correlator #2 = 2 x C03 + 2x CO2
+C01 + COO.
that is, the maximum score out of the first correlator is 256,
the maximum output of the second correlator is 512, etc. In
this configuration, the maximum length of the correlation is
4096. This would be implemented with 16 HSP45256's. The
programmable delay register in the first correlator would be
set for one delay, the second would be set for two, and 50 on,
with the final HSP45256 being set for a delay of 16.
Offset Register A = 0000000010000
010
00000000
011
00010000
100
00000000
Programmable Delay = 0
101
00000000
Offset Register B = 0
110
00000000
Cascading Corre/ators
Correlators can be cascaded in either a serial or parallel
fashion. Longer correlations can be achieved by connecting
several correlators together as shown in Figure 2. Each correlator is in a one data bit, one row, 256 tap configuration.
The number of bits of significance at the CASOUT output of
each correlator builds up from one correlation to the next,
DOU17
CA51N0-12
CASOUTO-12
DIN7
CASIN0-12
Correlations of more bits can be calculated by connecting
CASOUT of each chip to the CASIN of the following chip
(Figure 3). The data on the CASOUT lines accumulates in a
similar manner as in the 1 x 256 mode, except that the
maximum output of the first correlator is decimal 960, (hexadecimal 3CO); in the general case, the maximum number of
correlators that can be cascaded in this manner is eight,
since the maximum output of the last one would be 1EOO,
which nearly uses up the 13-bit range of the cascade
summer. More parts could be cascaded together if some bits
are to be masked out or if the user has a prior knowledge of
the maximum value of the correlation score. As before, the
delay in the first correlator would be set to one, the second
correlator would be set for a delay of two, and so on.
Multiple HSP45256's can be cascaded for two dimensional
one bit data (Figure 4). The maximum output for each chip is
the same as in the 1 x 256 case; the only difference is in the
manner in which the correlators are connected. The programmable delay registers would be set as before.
DOU17
DIN7
CASOUT0-12
CASIN0-12
DOU17
CASOUTO-12
DIN7
CASINO-12
-
DOU17
CASOUT0-12
CORRELATOR
SCORE
OUTPUT
FIGURE 2. 1 BIT, 1024 SAMPLE CONFIGURATION
..JZ
ceQ
-I-
Wz
""
rnu.
0..::::1
DIN7,5,3,1
DOU17, 5, 3, 1
DIN7,5,3,1
CASIN0-12
CASOUTO-12
CASIN0-12
DOU17,5,3,1
CASOUT0-12
DIN7,5,3,1
DOU17, 5, 3. 1
DlN7, 5, 3,1
DOU17, 5, 3, 1
CASIN0-12
CASOUTO-12
CASINO-12
CASOUT0-12
-
CORRELATOR
SCORE
OUTPUT
FIGURE 3. 4 BIT, 256 SAMPLE CONFIGURATION
DATA INPUT
ROWS8-15
DINO-7
CASINO-12
DIN0-7
CASOUTO-12
CASINO-12
DATA INPUT
ROWS 24-31
DATA INPUT
ROWS 16-23
DIN0-7
DIN0-7
CASOUTO-12
CASINO-12
CASOUTO-12
CASIN0-12
CASOUT0-12
CORRELATOR
SCORE
OUTPUT
FIGURE 4_ 1 BIT, 32 X 32 WINDOW CONFIGURATION
7-29
HSP45256
Reloading Data During Operation
RlOAD# and ClOAD# are asynchronous signals that are
designed to be driven by the memory interface signals of a
microprocessor. TXFR# is synchronized to ClK so that the
mask or reference data is updated on a specific clock cycle.
In the normal mode of operation. the user loads the
reference and mask memories. then pulses TXFR# to use
that data. The correlator uses the new mask or reference
information immediately. loading of the reference and mask
data remains asynchronous as long as there Is at least one
cycle of ClK between the rising edge of RlOAD# or
ClOAD# and the TXFR# pulse.
If the system timing makes it necessary for TXFR# and
RlOAD# andlor ClOAD# to be active during the same clock
cycle. then they must be treated as synchronous signals; the
timing for this case is shown in Figure 5 and given in the AC
Tim ing Specifications (TTHCL and TCLLH). In this example.
data is loaded during clock cycle 1 and transferred on the
riSing edge of ClK that occurs in clock cycle two. Another
set of data is loaded during clock cycle 2. which will be
transferred by a later TXFR# pulse. The sequence of events
is as follows:
1. In clock cycle 1. TXFR# becomes active at least TTH nanoseconds after the rising edge of ClK.
2. RlOAD andlor ClOAD# pulses low; the timing is not
critical as long as its rising edge occurs before the end of
clock cycle 1. If this condition is not met. it is undetermined
whether the data loaded by this pulse will be transferred
by the current TXFR# pulse.
3. The rising edge of TXFR# occurs while ClK is high during
clock cycle 2. The margin between the riSing edge of
TXFR# and the falling edge of ClK is defined by TTHCL.
4. RlOAD# and/or ClOAD# pulses low. The rising edge of
RlOAD# and ClOAD# must occur after the falling edge of
ClK. The margin between the two is defined by TCLLH.
The time from the rising edge of TXFR# to the falling edge of
ClK must be greater than TTHCL. and the time from the failing edge of ClK to the riSing edge of RlOAD# or ClOAD#
must be greater than Ts. If this timing is violated. the data
being transferred by the TXFR# pulse shown mayor may not
include the data loaded in clock cycle 2.
CLOCK CYCLE 1
CLOCK CYCLE 2
ClK
TXFR.
RlOAD#.
ClOADt
FIGURE 5. lOADING AND TRANSFERRING DATA DURING THE SAME CLOCK CYCLE
7-30
Specifications HSP45256
Absolute Maximum Ratings
+B.ov
Supply Voltage •.••.•••.••.•.••.••••.•••••••••••.•.•
Input, Output or 1/0 Voltage .•••••..••••• GND-O.5V to Vee+O.5V
Storage Temperature Range •.•.•....•...•... -65°C to + 150°C
Junction Temperature ..•.••.•••• + 1500C (PLCC), +175°C (PGA)
Lead Temperature (Soldering lOs) •...••.••.••...•.••. +3OO°C
ESD Classification .•.........•....••.•.•....••.•.• Class 1
Thermal Resistance
9JA
PLCC Package • • • • . . • . • . • • • . • • • • • •
34°CIW
PGA Package •• • • • . • • • • • • • • . • . • • • .
36°CIW
Maximum Package Power Dissipation at +1250 C
PLCC Package .•••.•••.••••.••.••••••••.••.•••••• 2.2W
PGA Package .••••..•..•.•....•••.••..•..•.•.•••• 2.9W
Gate Count . • • . • . • . . . . • . . . • . • . . . • • • . • • • . • . • • 13,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sactlons of this specification is not imp/ied.
Operating Conditions
Operating Voltage Range .•....•..•.•..•.•.. +4.75V to +5.25V
Operating Temperature Range .•.•.••.••••.•••.• ooC to +700 C
DC Electrical Specifications
PARAMETER
SYMBOL
MIN
MAX
UNITS
TEST CONDITIONS
Logical One Input Voltage
VIH
2.0
·
V
Vcc =5.25V
Logical Zero Input Voltage
VIL
·
0.8
V
Vcc =4.75V
High Level Clock Input
VIHC
3.0
·
V
Vcc =5.25V
Low Level Clock Input
VILC
·
0.8
V
Vcc= 4.75V
Output High Voltage
VOH
2.6
·
V
10H = 4001lA, Vcc = 4.75V
Output Low Voltage
VOL
·
0.4
V
10L = +2.0mA, Vcc = 4.75V
Input Leakage Current
II
-10
10
IIA
VIN = Vee or GND, Vcc = 5.25V
Output Leakage Current
10
-10
10
jIA
Vour= Vee orGND, Vcc= 5.25V
Standby Power Supply Current
ICCSB
·
500
jIA
VIN = Vcc or GND, Vcc = 5.25V, Note 3
Operating Power Supply Current
Iccop
·
179
mA
f = 25.6MHz, VIN = Vcc or GND, Vce = 5.25V,
Note 1, Note 3
..I
Capacitance (TA = 25°C, Note 2)
PARAMETER
Z
cQ
(.)(.)
Wz
0.:;)
-ISYMBOL
MIN
MAX
UNITS
Input Capacitance
CIN
·
10
pF
Output CapaCitance
Co
·
10
pF
TEST CONDITIONS
tnu.
Frequency = lMHz, Vcc = Open
All measurements are referenced to device ground.
NOTES:
1. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 7mAlMHz.
2. Not tested, but characterized at initial design and at major process/design changes.
3. OUtput load per test load circuit and CL = 40pF.
7-31
Specifications HSP45256
AC Electrical Specifications
(Vce = 5.0V ±5%, TA = O"C to +70"C, Note 1)
33MHz
PARAMETER
SYMBOL
MIN
25.6MHz
MAX
MAX
MIN
UNITS
ClK Period
30
39
ns
ClKHigh
12
15
ns
ClKlow
12
15
ns
Set-Up Time DIN to ClK High
12
13
ns
Hold Time ClK High to DIN
o
0
ns
TXFR# Set-Up Time
12
13
ns
TXFR# Hold Time
o
Tos
Output Delay DOUT, AUXOUT, CASOUT
ns
0
15
Too
TEST CONDITIONS
ns
20
ClOAD# Cycle Time
30
39
ns
ClOAD# High
TClH
12
15
ns
CLOAD# Low
TCll
12
15
ns
Set-Up Time, A to RLOAD#, CLOAD#
12
13
ns
Hold Time, RLOAD#, ClOAD# to A
o
0
ns
RLOAD# Cycle Time
30
39
ns
RlOAD# High
12
15
ns
RlOAD# Low
12
15
ns
Set-Up Time, DCONT to CLOAD#
Tocs
12
13
ns
Hold Time, ClOAD# to DCONT
TOCH
o
0
ns
Set-Up Time, DREF to RLOAD#
12
13
ns
Hold Time, RLOAD# to DREF
o
0
ns
Output Enable Time
TOE
15
15
ns
Output Disable Time
Too
15
15
ns
Note 2
6
6
ns
Note 2
Output Rise, Fall Time
3
TXFR# High to ClK low
CLK Low to RLOAD#, CLOAD# High
3
TCllH
ns
Note 2
ns
Note 2
NOTES:
1. AC testing is performed as follows: Input levels (ClK Input) 4.0V and OV; Input levels (all other inputs) OV and 3.0V; Timing reference
levels (ClK) 2.0V; All others 1.5V. Output load per test load circuit with C l = 40pF. Output transition is measured at VOH > 1.5V and
VOL < 1.5V.
2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
design changes.
Test Load Circuit
c····················································....................................]
i
:
SI
OUT
1 ./
i
:
~:
~
:
,clI
[J
~
IOH
±
I.SV
• INCLUDES STRAY
AND JIG
CAPACITANCE
EQUIVALENT CIRCUIT
SWITCH SI OPEN FOR ICCSB AND Iccop TEST
7-32
t
IOL
HSP45256
Timing Waveforms
ClK
TCLC
~N~7
__
~~-4
~
Tcu
TCLH
__ ________ __________
~
-\-
ClOADI
TAS TAH
TXFR#
DOUT~7
C~~~~1~~~
AO-2
DCONT~7
INPUT, OUTPUT TIMING
~
ry;'1..
X -1.
CONTROL INPUT TIMING
OEM,OEC'
J
"\.....=---------
AUXOUT~8 _ _ _ _ _ _=:J
__·TO_D""r- ~. T~~7:L
TRLC
DlOADI
X
•1.____.1.
_______
- - - -...
...J ~________J\, _________
TRLL
-
r
CASOUT~12
TRLH
1.3V ~
/
j
TAS TAH
.1
AO-2
X
1.
""TR'TF
DOUT~7, __________-.j I
CASOUT~12, _________o;r.;iIIolviooII,,_2_.0_V_______________
~
TRS TRH
.1
DREFO-7
X
1.
AUXOUT~8
REFERENCE INPUT TIMING
OUTPUT TIMING
TTHCL
TCLLH
CLK
TXFR.
RlOADI,
ClOAD.
TRANSFER, LOAD TIMING WHEN BOTH OCCUR ON A SINGLE CYCLE
7-33
HSP45256/883
Binary Correlator
January 1994
Features
Description
• This Circuit is Processed In Accordance to MIL-STD883 and Is Fully Conformsnt Under the Provisions of
Paragraph 1.2.1.
The Harris HSP45256 is a high-speed, 256 tap binary
correlator. It can be configured to perform one- or twodimensional correlations of selectable data precision and
length. Multiple HSP45256's can be cascaded for increased
correlation length. Unused taps can be masked out for
reduced correlation length.
• Reconflgurable 256 Stage Binary Correlator
• 1-Blt Reference x 1, 2, 4, or 8-Blt Data
• Separate Control and Reference Interfaces
• Conflgurable for 1-0 and 2-D Operation
• Double Buffered Mask and Reference
• Programmable Output Delay
• Cascadable
• Standard Microprocessor Interface
The output of the correlation array (correlation score) feeds
the weight and sum logic, which gives added flexibility to the
data format. In addition, an offset register is provided so that
a preprogrammed value can be added to the correlation
score. This result is then passed through a user programmable delay stage to the cascade summer. The delay stage
simplifies the cascading of multiple correlators by
compensating for the latency of previous correlators.
Applications
• Radar/Sonar
• Spread Spectrum Communications
• Pattern/Character Recognition
• Error Correction Coding
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
The correlation array consists of eight 32-tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8-bit input
data with a l-bi! reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
configured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The mask register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
PACKAGE
HSP45256GM·20/883
·55°C to +125°C
85 Lead PGA
HSP45256GM·251883
·55°C to +125°C
85 Lead PGA
The Binary Correlator is configured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the control and reference registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
Block Diagram
DOUTO-7
DINO·7
256 TAP
CORRELATION
ARRAY
DREFO·7
WEIGHT
AND SUM
DCONT0-7
AO·2
:1
CONTROL
I
-----.
DELAY
[3r----CASCADE
SUMMER
AUXOUTo.a
CASOUTo.12
1
CASINo.12
CAUTION: These devices are sensitive to electrostatic discharge. Us"," should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994
7-34
File Number
2997.2
HSP452561883
Pinouts
85 PIN PGA
TOP VIEW
.I.
B
C
CASIN
•
CASIN
•
CASIN
5
GND
CASIN
1
CASIN
CLK
CASIN
0
INDEX
PIN
a
DINt
vee
DIN.
DINt
DINt
DREF
DlN3
DlN2
o
•
G
DING
DREF
1
H
DREF
,
DREF
DREF
a
DREF
1
DREF
vee
R
LOADt
GND
TXFRI
K
•
DREF
•
CASIN
1
CASIN
•
CAS
OUT
CAS
OUT
3
CAS
OUT
CAS
OUT
CAS
OUT
1
CAS
OUT
CA.
OUT
CASIN
I.
OECo
CASIN
I.
CASIN
11
C.I.SIN
•
•
CASIN
•
•
•
,
•
10
11
GND
CAS
OUT
CAS
OUT
1
CAS
OUT
10
CAS
OUT
CAS
OUT
11
•
I
DlNI
GND
CAS
OUT
I.
DOUTO
DOUTI
DOUT2
DOUT
•
DOUT
1
DOUT
vee
DOUT
•
DOur
AIIX
OUT
1
AIIX
OUT
0
GND
AIIX
OUT
2
•
a
,
AI
DCONT
,
DCONT
C
LOADt
.1.0
DCONT
•
DCONT
a
OEAI
AUX
OUT
AIIX
OUT
AUX
OUT
.1.1
DCONT
1
DCONT
1
DCONT
DCONT
AUX
OUT
OUT
AIIX
OUT
•
a
•
•
•
•
AUX
a
,
7
85PINPGA
BOTTOM VIEW
0
DREFO
K
0
DREF2
0
0
GND
TXFRI
0v••
RLOADt
0
0
DCDNT
1
0
0.1.0
DCDNT
CLOADt
0AI
DREF1
0
DREF5
G
0
C
B
v"
0
GND
A
0
CASIN
2
DCDNT
0
0
DCONTO AUXOUT
•
0
CASINO
0
CASINI
0
CASIN
•
0
AUXOUT
•
0
,
AUXOUT AllXOUT
7
0 AUXOUT
0 0
0 OEAI
•
•
•
0
0
GND
DCONT
DCONT
0
AUXOUT
a
0
AllXOUl
2
0 0
AllXOUT
1
0
0 DlNI
0 DIN2
0
DINa
0 DINt
0
DINt
0
0
0
0DIN1
0CLK
•
0
,
0
DCONT
3
DREF.
DREF1
DIN.
o
0
0
DlNO
DREFI
0
DCONT
7
0 0
OREn
H
0
.1.1
0 DOUT.
0
0 DOUTt
0
DOUT.
0 DOUTI
0
DOUTO
0
QND
v••
AUXoOUl
0
0
DOUTI
0
DOUTI
0
CASOUT
DOUT'
I.
0
INDEX
PIN
0
CASlN3
0
,
CASIN
0 CASIN
0 OEce
0
•
0 0 0
CASIN CASOUT
0
CASOUT
CASIN
12
0
CASINO
0
CASIN
1
•
0
CASIN
I.
•
0
C.I.SIN
11
7·35
CASOUT
1
0
0
0
•
•
0
,
•
0
CASOUT CASOUT CASOUT
7
0
CASOUT CASOUT CASOUT
a
0
0
0
CASOUT
11
0
CASOUT
10
0
GND
CASOUT
10
11
•
HSP45256/883
Pin Description
SYMBOL
PIN NUMBER
DESCRIPTION
TYPE
Vcc
02,G9, K2
The +5V power supply pin
GNO
AIO, BI, 010,
JIO, L2
Ground.
01NO-7
01, EI-E3, F2,
F3,GI,G3
I
The 0lN0-7 bus consists of eight single data input pins. The assignment of the active
pins is determined by the configuration. Data is loaded synchronous to the rising edge
of ClK. OINO is the LSB.
E9-EII, F9-FII,
GIO, GIl
0
The OOUTO-7 bus is the data output of the correlation array. The format of the output
is dependent on the window configuration and bit weighting. OOUTO is the LSB.
CI
I
System clock. Positive edge triggered.
CASINO-I 2
A I-A6, B2-B5,
C2,C5,C6
I
CASINO-12 allows multiple correlators to be cascaded by connecting CASOUTO-12 of
one correlator to CASINO-12 of another. The CASIN bus is added internally to the
correlation score to form CASOUT. CASINO is the LSB.
CASOUTO-12
A7-A9,AII,
B6-BII, CIO,
CII,OII
0
CASOUTO-I2 is the output correlation score. This value is the delayed sum of all the
256 taps of one chip and CASINO-12. When the part is configured to act as two
independent correlators, CASOUTO-8 represents the correlation score for the first
correlator while the second correlation score is available on the AUXOUTO-8 bus. In
this configuration, the cascading feature is no longer an option. CASOUTO is the LSB.
OEC#
C7
I
OEC# is the output enable for CASOUTO-12. When OEC# is high, the output is threestated. Processing is not interrupted by this pin. (Active low.)
TXFR#
L3
I
TXFR# is a synchronous clock enable signal that allows the loading of the reference
and mask inputs from the preload register to the correlation array. Data is transferred
on the rising edge of CLK while TXFR# is low. (Active low.)
OREFO-7
FI,G2,HI,H2,
JI, J2, KI, LI
I
OREFO-7 is an 8-bit wide data reference input. This is the input data bus used to load
the reference data. RLOAO# going active initiates the loading of the reference registers.
This input bus is used to load the reference registers of the correlation array. The manner in which the reference data is loaded is determined by the window configuration. If
the window configuration is I x 256, the reference bits are loaded one at a time over
OREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into
all stages in parallel. In this case, OREF7 is the reference data for the first stage and
OREFO is the reference data for the eighth stage. The contents of the reference data
registers are not affected by changing the window configuration. OREFO is the LSB.
RLOAO#
K3
I
RLOAO# enables loading of the reference registers. Data on OREFO-7 is loaded into
the preload registers on the riSing edge of RLOAO#. This data is transferred into the
correlation array by TXFR#. (Active low.)
J6, J7, K6, K7,
L5-L8
I
OCONT0-7 is the control data input, Which is used to load the mask bit for each tap as
well as the configuration registers. The mask data is sequentially loaded into the eight
stages in the same manner as the reference data. OCONTO is the LSB.
K4
I
CLOAO# enables the loading of the data on OCONTO-7. The destination of this data is
controlled by A0-2. (Active lOW.)
J5, KS, L4
I
AO-2 is a 3-bit address that determines what function will be performed when CLOAO#
is active. This address bus is set up with respect to the rising edge of the load signal,
CLOAO#. AO is the LSB.
HIO, HII,JII,
K9-KII, L9-L II
0
AUXOUTO-8 is a 9-bit bus that provides either the data reference output or the 9-bit
correlation score of the second correlator, depending on the configuration. When the
user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. When the user has programmed the chip to be one correlator,
AUXOUTO-7 represents the reference data out, with the state of AUXOUTO-8
undefined. AUXOUTO is the LSB.
I
The OEA# signal is the output enable for the AUXOUTO-8 output. When OEM is high,
the output is disabled. Processing is not interrupted by this pin. (Active low.)
OOUTO-7
CLK
OCONTO-7
CLOAO#
AO-2
AUXOUTO-8
OEM
K8
Index Pin
C3
Used for orienting pin in socket or printed cirecuit board. Must be left as a no connect
in circuit.
7-36
Specifications HSP452561883
Absolute Maximum Ratings
Reliability Information
Supply Voltage .•••.•••••.•....•••••.•••••••.••.•••• +lI.OV
Input, Output or VO Voltage ...••••••.•.• GND-o.5V to Vcc+O.5V
Storage Temperature Range .••.••••.•.••••.• -65°C to +150°C
Junction Temperature ••••..•.•.••.•.•••..•.••..•••• +175°C
Lead Temperature (Soldering 1Os) .••....••.•.•..••••• +3OOoC
ESD Classification ..•.•••••.•••..••••••••••.•••••. Class 1
Thermal Resistance. • • • • • . • • • • •• • • •
9J"
9JC
Ceramic PGA Package .•.•••••••• , 36"Otw
1O"Ctw
Maximum Package Power Dissipation at +125°C
Ceramic PGA Package ••.•••••••••.•.•••••••.•.••• 1.39W
Gate Count ••••..•.•••.•....•..•....•••••••• 13,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the dBvic.. This Is a stress only raUng and operaUon
of the device at these or any other conditions above those Indicated In the operaUonal sections of this specification Is not Implied.
Operating Conditions
Operating Voltage Range. • . . • . • . • . • • • • . • • . • .• +4.5V to +5.5V
Operating Temperature Range ••••••••••••.•.• -55"0 to +125°C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
MAX
UNITS
Logical One Input
Voltage
VIH
Vee = 5.5V
1,2,3
-55° ~ T" ~ + 125"0
2.2
-
V
Logical Zero Input
Voltage
VIL
Vcc =4.5V
1.2,3
-55° ~ T" ~ + 125"0
-
0.8
V
Logical One Input
Voltage Clock
VIHC
Vee = 5.5V
1,2,3
-55° ~ T" ~ + 125"0
3.0
-
V
Logical Zero Input
Voltage Clock
VILC
Vee =4.5V
1,2,3
-55" ~ TA ~ + 125°C
-
0.8
V
OUtput HIGH Voltage
VOH
10H = -40Oj.lA
Vcc= 4.5V (Note 1)
1,2,3
-55° ~ T" ~ + 125°C
2.6
-
V
Output LOW
Voltage
VOL
10L= +2.OmA
Vcc= 4.5V (Note 1)
1,2,3
-55" ~ T" ~ + 125"0
-
0.4
V
Input Leakage Current
II
VIN = Vcc or GND
Vcc=5.5V
1,2,3
_55° ~ T" ~ + 125"0
-10
+10
J1A
Output Leakage Current
10
VIN = Vcc or GND
Vcc= 5.5V
1,2,3
-55° ~ T" ~ + 125°C
-10
+10
J1A
Standby Power Supply
Current
ICCSB
VIN = Vcc or GND
Vcc =5.5V,
Outputs Open
1,2,3
-55" ~ T" ~ + 125°C
-
500
J1A
Operating Power Supply
Current
Iccop
1= 20 MHz, VIN = Vcc
or GND, Vee = 5.5V
(Note 2)
1,2,3
-55°~T,,~+125OC
-
140
mA
7,8
-55° ~ T,,~ + 125°C
-
-
-
Functional Test
FT
(Note 3)
NOTES:
1. Interchanging 01 force and sense conditions Is permitted.
2. Operating Supply Current is proportional to frequency, typical rating is 7mAlMHz.
3. Tested as follows: 1= 1MHz, VIH(clock Inputs) = 3.4V, VIH (all other Inputs) = 2.6V, VIL = 0.4V, VOH ~ 1.5V, and VOL ~ 1.5V.
7-37
Specifications HSP452561883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
·25 (25.6MHz)
GROUP A
SUB·
GROUPS
TEMPERATURE
MIN
MAX
-
ClK Period
Tcp
9,10,11
·55" S TA S +125°C
39
ClKHigh
TCH
9,10,11
-55° S TA S +125°C
15
ClKlow
TCl
9,10,11
-55° S TA S +125OC
15
ClOAD# Cycle Time
T ClC
9,10,11
-55° s TA S +125°C
39
ClOAD# High
TClH
9,10,11
-55° S TA S +125OC
15
ClOAD#low
TCll
9,10,11
-55° S TA S +125°C
15
RlOAD# Cycle Time
T RlC
9,10,11
-55° S TA S +125OC
39
RlOAD# High
TRlH
9, 10, 11
-55° S TA S +125OC
15
RlOAD#Low
TRll
9,10,11
_55° S TA S +125°C
15
Set-up Time; DIN to ClK
High
Tos
9,10,11
-55° S TA S +125OC
13
-
Hold Time; DIN to ClK
High
TOH
9,10,11
-55° S TA S +125°C
1
Set-up Time; DREF to
RlOADHigh
T RS
9,10,11
-55° S TA S +125°C
Hold Time; DREF to
RLOADHigh
TRH
9,10,11
DCONT Set up Time
Tocs
DCONT Hold Time
-
·20 (20MHz)
MIN
50
20
MAX
-
UNITS
ns
ns
20
-
ns
50
-
ns
20
-
ns
20
-
ns
50
-
ns
15
-
-
1
-
ns
14
-
15
-
ns
-55° S TA S +125°C
1
-
1
-
ns
9,10,11
_55° S TA S +125OC
13
TOCH
9,10,11
-55° S TA S +125°C
1
Address Set up Time
TAS
9,10,11
_55° S TA S +125OC
13
Address Hold Time
TAH
9, 10, 11
_55° S TA S +125°C
1
TXFR# Set up Time
TTS
9,10,11
-55° S TA S +125°C
13
TXFR# Hold Time
TTH
9,10,11
_55° S TA S +125OC
1
-
ClK to Output Delay
DOUT, AUXOUT,
CASOUT
Too
9, 10, 11
_55° S TA S +125°C
-
Output Enable Time
TOE
Note 2
9,10,11
-55" S TA S +125OC
TXFR# High to ClK low
TTHCl
Note 3
9,10,11
ClK low to RlOAD#,
CLOAD#High
TClLH
Note 3
9,10, t t
20
20
ns
ns
ns
15
-
1
-
ns
20
-
25
ns
-
20
-
20
ns
-55° S TA S +125°C
3
-
4
-55° S TA S +125°C
1
-
1
-
-
15
1
15
1
ns
ns
ns
ns
ns
ns
-
ns
NOTES:
1. AC testing is performed as follows: Vcc = 4.5Vand 5.5V.lnput levels (ClK Input) 4.0V and OV; Input levels (all other Inputs) 3.0Vand OV;
Timing reference levels (ClK) 2.0V; All others 1.5V. Output load per test load circuit with C l = 40pF. Output transistion Is measured at
VOH <: 1.5V and VOL S \.5V.
2. Transistion is measured at ±200mV from steady state voltage, Output loading per test load circuit, C l = 40pF.
3. Applicable only when TXFR# and RlOAD# or ClOAD# are active on the same cycle of ClK.
7·38
Specifications HSP452561883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
-20
·25
PARAMETER
Input Capacitance
SYMBOL
COUT
OUtput Disable
Time
Too
Output Rise Time
TR
Output Fall Time
VCC = Open, f=1
MHz All measure·
ments are referenced
to device GND.
CIN
OUtput Capacltance
NOTES
CONDITIONS
From O.SV to 2.0V
From 2.0V to O.SV
TF
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
10
.
10
pF
10
-
10
pF
-
20
ns
1
-550:S; TA ~a125°C
1
·550:S; TA:S; +125 C
-
1,2
·55°:S; TA:S; +12500
-
20
1,2
·55°:S; TA:S; +12500
.
S
-
S
ns
·5SO:s; TA s +12500
.
S
.
S
ns
O
1,2
NOTES:
1. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon Initial design and
alter major process and/or design changes.
2. Loading is as specified In the test load circuit with CL = 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%15004
-
Interim Test
100°/015004
.
PDA
100%
1
Final Test
100%
2,3, SA, SB, 10, 11
.
1,2,3,7, SA, 88, 9, 10, 11
Samples/5005
1,7,9
Group A
Groups C and D
Test Load Circuit
.........................................................................................
OUT
Cl
1
I
S1
!
.clI
~
i
±
• INCLUDES STRAY
AND JIG
CAPACITANCE
-
•
)
1.5V
-
t
-
IOl
I
i
.........................................................................................,I
EQUIVALENT CIRCUIT
SWITCH S1 OPEN FOR !cess AND Iccop TEST
7·39
HSP452561883
Burn-In Circuits
2
A
PGA
PIN
PIN
NAME
3
4
CASIN CASIN CASIN CASIN CASIN CASIN
S
7
10
11
2
4
B
CASIN CASIN CASIN
GND CASIN
1
3
6
II
C
ClK
D
DlN7
Vee
E
DlN4
DIN5
DIN6
F
DREF
DlN3
DIN2
G
DlNO
DREF
7
DlNl
4
CASIN INDEX
PIN
0
II
10
11
CAS
OUT
5
GND
CAS
OUT
8
CAS
OUT
2
CAS
OUT
1
CAS
OUT
4
CAS
OUT
6
CAS
OUT
7
CAS
OUT
10
CAS
OUT
II
CAS
OUT
11
GND
CAS
OUT
12
DOUTO DOUTl DOUT2
8SPIN PGA
TOP VIEW
DREF DREF
5
4
J
DREF DREF
3
1
K
DREF
2
Vee
R
C
lOAD!I lOAD!I
l
DREF
0
GND
TXFR#
PGA
PIN
8
CAS
OUT
3
CASIN CASIN OECI
8
12
H
BURN-IN
SIGNAL
7
CAS
OUT
0
6
5
A2
PIN
NAME
DOUT
4
DOUT
7
DOUT
3
Vee
DOUT
6
DOUT
5
AUX
OUT
1
AUX
OUT
0
AUX
OUT
6
AUX
OUT
4
AUX
OUT
2
AUX
OUT
3
AUX
DCONT DeONT DCONT DCONT OUT
0
7
1
3
8
AUX
OUT
7
AUX
OUT
5
Al
DCONT DCONT
5
4
AO
DCONT DCONT OEM
2
6
BURN-IN
SIGNAL
GND
PIN
NAME
PGA
PIN
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
AI
CASIN2
F3
BII
CASOUTIO
Vecl2
F9
DOUT4
Ve cl2
K2
Vee
Vee
A2
CASIN4
FS
CI
CLK
FO
FlO
DOUT7
Vecl2
K3
RLOAD#
F3
A3
CASINS
F6
C2
CASINO
FI
FII
DOUT3
Vecl2
K4
CLOAD#
F3
A4
CASIN7
FI
CS
CASINB
F2
GI
DINO
FI
KS
AO
F9
AS
CASINIO
F4
C6
CASINI2
F6
G2
DREF7
Fa
K6
DCONT6
F7
A6
CASINII
FS
C7
OEC#
Fll
G3
DINI
F2
K7
DCONT2
F6
A7
CASOUTO
V e c/2
CIO
CASOUT9
Ve c/2
G9
Vee
Vee
KB
OEM
FII
AB
CASOUT3
V e c/2
CII
CASOUT11
Ve c/2
GIO
DOUT6
V e cl2
K9
AUXOUT6
Vecl2
A9
CASOUTS
Ve c/2
DI
DIN7
Fa
GIl
DOUTS
V e cl2
KIO
AUXOUT4
V ecl2
AIO
GND
GND
D2
Vee
Vee
HI
DREFS
F6
KI1
AUXOUT3
Vecl2
All
CASOUTB
Vcc/2
DIO
GND
GND
H2
DREF4
FB
LI
DREFO
F4
BI
GND
GND
DII
CASOUT12
Vee12
HIO
AUXOUT1
Vecl2
L2
GND
GND
B2
CASINI
F2
EI
DIN4
FS
HII
AUXOUTO
V e cl2
L3
TXFR#
F2
B3
CASIN3
F4
E2
DINS
F6
JI
DREF3
F7
L4
A2
FII
B4
CASIN6
F7
E3
DlN6
F7
J2
DREFI
FS
LS
DCONT7
FB
BS
CASIN9
F3
E9
DOUTO
Vee12
JS
AI
FlO
L6
DCONT1
FS
B6
CASOUT2
Vecl2
EIO
DOUT1
V e c/2
JS
DCONTS
FS
L7
DCONT3
F7
B7
CASOUT1
Ve c/2
Ell
DOUT2
Ve c/2
J7
DCONT4
F8
L8
DCONTO
F4
B6
CASOUT4
V e c/2
FI
DREF6
F7
JIO
GND
GND
L9
AUXOUT8
Vecl2
B9
CASOUT6
Vcc/2
F2
DIN3
F4
JII
AUXOUT2
Vecl2
LIO
AUXOUT7
Vccl2
BIO
CASOUT7
V e c/2
F3
DIN2
F3
KI
DREF2
F6
LII
AUXOUTS
V e c/2
4. O.II'F (min) capacitor between Vee and GND perpos~ion.
NOTES:
I. Vecl2 (2.7V ±IO"IO) used for outputs only.
2. 47kn (±20"1O) resistor connected to all pins except Vee and GND.
S. FO= lookHz± 10%, FI = F0/2, F2 = FI/2 .•. Fl1 = FI0/2, 40-60"10 Duty
Cycle.
3. Vee = S.S ± O.SV.
S. Input Voltage Lim~s: VIL = O.BV max, VIH = 4.S ± 10"10.
7-40
HSP45256/883
Metal Topology
DIE DIMENSIONS:
254x214x19±1mils
METALUZATION:
Type: Si - AI or Si-AI-Cu
Thickness: 8kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA
WORST CASE CURRENT DENSITY:
0.96 x 105 Ncm 2
Metallization Mask Layout
CASINl (74)
CASINO (73)
(12) CASOUT8
GND (72)
. (13) CASOUTe
(14) CASOUT10
CLK (71)
vee
(15) CASOUTll
(70)
(16) GND
DIN7 (69)
(17) CASOUT12
DINS (68)
(18) DOUTO
(19) DOUTl
DlN4 (66)
(20) DOUT2
DlN3 (65)
(21) DOUT3
DlN2 (64)
(22) DOUT4
.JZ
DINl (63)
(23) VCC
DlNO (62)
(24) DOUTS
DREF7 (61)
(25) DOUTS
-~
Uu
Wz
D.:;)
(26) DOUT7
DREF6 (60)
(27) AUXOUTO
DREF5 (59)
(28) AUXOUTl
DREF4 (58)
(29) AUXOUT2
DREF3 (57)
DREF2 (56)
(30) AUXOUT3
I
(31) GND
DREFl (55)
(32) AUXOUT4
DREFO (54)
7-41
ceQ
0u.
HSP9520, HSP9521
Multilevel Pipeline Registers
February 1994
Features
Description
• Four 8-Blt Registers
These devices are multilevel pipeline registers implemented
using a low power CMOS process. They are pin for pin compatible replacements for industry standard multilevel pipeline
registers such as the L29C520 and L29C521. The HSP9520
and HSP5921 are direct replacemens for the AM29520 and
AM29521 and WS59520 and WS59521.
• Hold, Transfer and Load Instructions
• Single 4-Stage or Dual·2 Stage Plpellnlng
• All Register Contents Available at Output
• Fully TTL Compatible
• Three-State Outputs
They consist of four a-bit registers which are dual ported.
They can be configured as a single four level pipeline or a
dual two level pipeline. A single 8-bit input is provided, and
the pipelining configuration is determined by the instruction
code input to the 10 and 11 inputs (see instruction control).
• High Speed, Low Power CMOS
Applications
• Array Processor
• Digital Signal Processor
The contents of any of the four registers is selectable at the
multiplexed outputs through the use of the SO and S1 multiplexer control inputs (see register select).The output is a-bits
wide and is three-stated through the use of the OEI input.
• AID Buffer
• Telecommunication
• Byte Wide Shift Register
• Mainframe Computers
Ordering Information
TEMPERATURE
RANGE
PACKAGE
HSP9520CP
OOCto +700 C
24 Lead Plastic DIP
HSP9520CS
O"C to +700 C
24 Lead SOIC
HSP9521CP
O"C to +70"C
24 Lead Plastic DIP
HSP9521CS
OOC to +700 C
24 Lead SOIC
PART NUMBER
The HSP9520 and HSP9521 differ only in the way data is
loaded into and between the registers in dual two-level operation. In the HSP9520 when data is loaded into the first level
the existing data in the first level is moved to the second
level. In the HSP9521 loading the first level simply causes
the current data to be overwritten. Transfer of data to the
second level is achieved using the Single four level mode (11,
10
'0'). This instruction also causes the first level to be
loaded. The HOLD instruction (11, 10 ='1') provides a means
of holding the countents of aU registers.
=
Pinout
HSP9520, HSP9521 (24 PIN SOIC, NPDIP)
TOP VIEW
CAUTION: These devices are sensijive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @HarrisCorporation 1994
7-42
File Number
2811.4
HSP9520/HSP9521
Block Diagram
10
-
REG.A1
/
00-07
/
REG.A2
8
eLK _
11
~@-
-
REG.B1
I
f Lr--....
REG.B2
-
MUX
r-
~
YO-YT
OE#··
so
Sl
Pin Descriptions
NAME
DIP PIN
VCC
24
GND
12
ClK
11
I
Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and
hold times with respect to the clock must be met for proper operation.
00-7
3-10
I
Data Input Port These inputs are used to supply the a bits of data which will be
latched into the selected register on the next rising clock edge.
yo-7
21-14
0
Data Output Port. This a-bit port provides the output data from the four internal registers.
They are provided in a multiplexed fashion, and are controlled via the multiplexer control
inputs (80 and 81).
10,11
1,2
I
Instruction Control Inputs. These inputs are used to provide the instruction code
which determines the Internal register pipeline configuration. Refer to the Instruction Control
Table for the specific codes and their associated configurations.
80,81
23,22
I
MUltiplexer Control Inputs. These inputs select which of the four internal registers' contents
will be available at the output port. Refer to the Register Select Table for the codes to select
each register.
OE#
13
I
Output Enable. This input controls the state of the output port (y0-Y7). A lOW on this control
line enables the port for ouput When OE# is HIGH, the output drivers are In the high
impedance state. Internal latching or transfer of data is not affected by this pin.
TYPE
DESCRIPTION
The +5V power supply pin.
recommended.
A 0.1J1F capacitor between the VCC and GND pin is
The device ground.
7-43
Specifications HSP9520/HSP9521
Absolute Maximum Ratings
Operating Conditions
Supply Voltage •••••••••.•.•.••...••••.••.......••.•.•• +8.0V
Input or Output Voltage Applied •..••••• G NO -0.5V to Vee +0.5V
Storage Temperature Range ••••.••.......••• -650C to +150 0 e
Junction Temperature .•....•..•...... , .............•. +1500 e
Lead Temperature (Soldering, Ten Seconds) .....•••••.• +3000 e
Operating Voltage Range ........•..•••..••.. +4.75V to +5.25V
Operating Temperature Range ......•.•..•....... ooe to +700 e
Reliability Information
Sja .•••.•.•••.••.•..•••.•. 51.40 C/W (DIP), 77.owfOe (SOIC)
Sjc . . . . • . . . . . • . . . . . . . . . . .. 22.3 0 e/W (DIP), 23.2WfOe (SOIC)
Maximum Package Power Dissipation .... 1.5W (DIP), 1.0W (SOIC)
D.C. Electrical Specifications
PARAMETER
(Vee = 5.0V ± 5%, TA = ooe to +700 e)
SYMBOL
MIN
Logical One Input Voltage
VIH
Logical Zero Input Voltage
VIL
TEST CONDITIONS
MAX
UNITS
2.0
-
V
Vee=5.25V
-
0.8
V
Vee=4.75V
VOH
2.4
-
V
10H = -6.5mA, Vee = 4.75V
VOL
-
0.5
V
10L = +20.0mA, Vee = 4.75V
Input Leakage Current
II
-10
10
IIA
Y,N = Vce or GND, VCC = 5.25V
Output Leakage Current
10
-10
10
IIA
VOUT = Vee or GND
Vee = 5.25V
Standby Power Supply Current
leess
-
500
!IA
VIN=VeeorGND
Vee = 5.25V Outputs Open
Operating Power Supply Current
leeop
-
12
mA
f= 5.0MHz, VIN = Vee orGND
Vee = 5.25V, Ouputs Open, Note 1
Output HIGH Voltage
Output LOW Voltage
Capacitance
(TA = +250 e, Note 3)
PARAMETER
SYMBOL
MIN
MAX
UNITS
TEST CONDITIONS
FREQ = 1 MHz, Vee = Open, all measurements
are referenced to device ground.
Input Capacitance
elN
-
12
pF
Output Capacitance
CO
-
12
pF
A.C. Electrical Specifications
(Vee = 5.0V ± 5%, TA = ooe to HOoe, Note 2)
SYMBOL
MIN
MAX
UNITS
TpD
21
ns
TSELD
-
20
ns
Input Setup Time (DO-7/10-7)
Ts
10
ns
Input Hold Time (DO-7110-7)
TH
3
-
TENA
20
ns
13
ns
-
ns
PARAMETER
Clock to Data Out
Mux Select to Data Out
Output Disable Time
TDIS
-
Clock Pulse Width
TpW
10
Output Enable Time
TEST CONDITIONS (Note 2)
ns
Note 3
NOTES:
1. Power supply current is proportional to frequency. Typical rating for ICCOp is 2.4mNMHz.
2. A.C. Testing is performed as follows: Input levels: OV and 3.0V, Timing reference levels = 1.5V, Input rise and fall times driven at 1nsN. Output load
CL = 40pF.
3. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major design andlor process changes.
7-44
HSP9520/HSP9521
Timing Waveform
CLOCK
(ClK)
INST
(10 -11)
DATA
(DO - 07)
MUXSEL
(SO -Sl)
OUTPUT
(YO - Y7)
ff
t - - - - TSELD THREE STATE _o---",-E#_ _
CONTROL
THREE STATE
OUTPUT
(YO -Yl)
(HIGH IMPEDANCE)
TABLE 1. INSTRUCTION CONTROL
11
0
10
0
'9520
I
A1
l
I
0
1
1
0
A2
1
I
I
I
0
0
~
~
A1
t
A2
I
I
~
r--1
I
B1
J
1
~
SO
'9520 OR '9521
0
0
82
0
1
81
1
0
A2
1
1
Al
ceQ
~
c±J
0
clJ
0
~
0
0
ALL REGISTERS HOLD
S1
..JZ
0
0
B2
A2
1
'9521
I~
~
TABLE 2. REGISTER SELECT
~
ALL REGISTERS HOLD
7-45
-I00
Ul Z
D..::)
mil.
05 0_ _----; 8
DEVELOPMENT TOOLS
PAGE
DEVELOPMENT TOOLS DATA SHEETS
DECI-MATETM
Harris HSP43220 Decimating Digital Filter Development Software. . . . . . . . . . . . . . . . .
8-3
HSP-EVAL
DSP Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
8-7
HSP45116-DB
HSP45116 Daughter Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-8
HSP50016-EV
DOC Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-10
NOTE: Bold Type Designates a New Product from Harris.
!zW
2(1)
Q..J
00
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C
DECloMATE is a trademark of Harris Corporation
8-1
DEC/·MATETM
:II HARRIS
SEMICONDUCTOR
January 1994
Harris HSP43220 Decimating Digital Filter
Development Software
Harris DEC I • MATE Development Software assists the
design engineer to prototype designs for the Harris
HSP43220 Decimating Digital filter (DO F). Developed specifically for the DDF, this software consists of three integrated modules: DDF Design, DDF Simulator and DDF
PROM. The Design module designs a filter from a set of
user specifications for the DDF. The Simulator module models the DDF's internal operation. The PROM module uses
the device configuration created by the Design module to
build a PROM data file that can be used to store and download the DDF configuration.
DDF System Design
The DDF consists of two stages: a High Decimation Filter
(HDF) and a Finite Impulse Response (FIR) filter. Together
these provide a unique narrow band, low pass filter.
Because of this unique architecture, special software is
required to configure the device for a given set of filter
parameters. This software uses system level filter parameters (listed below) to perform the trade off analysis and calculate the values for the DDF's configuration registers and
FI R coefficients.
Design specifications are supplied by the user in terms of:
1. Input sample frequency
Frequency response curves are then displayed showing the
resulting responses in the HDF, FIR and for the entire chip
using the given filter design. Figure 2 is a typical display. The
user may save this frequency response data for further
analysis. The design module also creates a report file documenting the filter design and providing the coefficients and
setup register values for programming the device.
DDF Simulator
The simulator provides an accurate simulation of the device
before any hardware is built. It can be used to simulate any
filter designed with DECI • MATE. The simulator takes into
account the fixed point bus widths and pipeline delays for
every element in the DDF.
The simulator provides the user with an input signal which
can be used to stimulate the filter. This signal is created from
the options shown in Table 1. The user can select a pure
step, impulse, cosine, chirp, uniform or Gaussian noise as
the input signal, or a more complex signal can be generated
by combining that data with an option selected from the Signal #2 column, with the combining operator chosen from the
middle column. The user can also import a signal from an
outside source.
TABLE 1.
SIGNAL #1
2. Required output sample frequency
OPERATION
SIGNAL #2
Step
Step
3. Passband signal bandwidth
Impulse
No Operation
Impulse
4. Transition bandwidth
COSINE
Add
COSINE
5. Amount of attenuation allowed in the passband
Chirp
Concatenate
Chirp
Uniform Noise
Multiply
6. Amount of stopband attenuation required for signals outside of the band of interest.
This information is entered into a menu screen (See Figure
1), providing immediate feedback on the design validity. The
design module calculates the order of the HDF, HDF
decimation required, the FIR input data rate, minimum clock
frequency for the FIR, FIR order and decimation required in
the FIR.
The design module will then generate the FIR filter. Four
different methods are provided for the FIR design:
1. A Standard FIR automatically designed by the module
using the Parks-McClellan method to compute the coefficients of an equiripple (Chebyshev) filter.
2. Any FIR imported into the Design module from another
FIR design program.
3. A precompensated FIR which is automatically designed
by the module to compensate for the roll-off in the passband of the HDF frequency response.
4. The FIR may also be bypassed in which case the optimal
HDF is designed from the user specifications.
Copyright © Harris Corporation 1991
DECloMATE'M is a Trademark of Harris Corporation
Uniform Noise
Gaussian Noise
Gaussian Noise
Imported From Outside
Probes are provided to select specific areas to graphically display data values as well as save into data files for further processing. The DDF Simulator has two levels; the DDF Simulator
Specification screen and the DDF Simulator Main Screen.
The specification screen (see Figure 3) is used to input the
simulation parameters. The users selects display modes in
either continuous or decimated format and data formats in
either decimal or hexadecimal. The specification screen also
provides for selection of the input signal.
The simulator main screen (see Figure 4) defines the simulator test probes and displays the data values per clock
cycle. The interactive simulator screen consists of the
HSP43220 block diagram, test probes and register contents.
The user selects the step size of the input sample clock and
also selects the probes to be monitored. The simulator will
then clock through the specified number of clock cycles and
display the resulting time domain response. Figure 5 shows
a typical probe display.
File Number
8-3
3368
DEC/-MATE
Monarch 2.0 DSP Design Software
System Requirements
DECI- MATE is fully integrated with Monarch 2.0
professional DSP design software. Monarch is a fullfeatured DSP package with FIR IIR filter design and
analysis, Two dimensional and Three dimensional viewing,
a programmable slgnaVsystems laboratory with 100+ DSP/
Math functions, extensive fixed-point support and FFTs/
IFFTs. Monarch is available separately from The Athena
Group, Inc.
IBM PC", Xl", AT", PS/2" computer or 100% compatible
with 640k RAM running MS/PC-DOS 2.0 or higher. One
MegaByte of fixed-disk space with 5.25" or 3.5" floppy
drive. CGA, MCGA, EGA, VGA, 8514, or Hercules graphics
adapter. A Math co-processor is strongly recommended.
When used with Monarch 2.0, DECI - MATE becomes a full
feature design environment for a DSP system. Data can
easily be transferred from DECI- MATE modules to the
Monarch modules for further analysis.
I
SIMULATOR MODULE
DESIGN MODULE
PROM MODULE
HSP43220 DDF FILTER SPECIFICATION
I
Filter File
PRES.DDF
Input Sample Rate:
33 MHz
Output Rate
100 kHz
Passband
5 kHz
Transition Band
700 Hz
Passband Atten
1 dB
Stopband Atten
96 dB
•
FIR Type
D
E
C
Design Mode
Generate Report
Display Response
Save Freq Responses:
Save FIR Response
AUTO
YES
LOG
YES
YES
STANDARD
M
A
T
HDF Order
HDF Decimation
HDF Scale Factor
4
330
0.6903
E
FIR
FIR
FIR
FIR
Input Rate
Clock (min)
Order
Decimation
FIGURE 1. FILTER SPECIFICATION MENU
IBM PC-,
xr, AT'", PS/2- are Registered Trademarks of IBM
8-4
100 kHz
33 MHz
509
1
II
DEC/-MATE
-3.2192~----~-----r----~------,
3.2201~=----r----~----~------,
-33.9581
-50. 4144t~············
-0.0065r======------:------------,------------,------------,-----------,
......................... ........................
-47.6682
~
···············t·························l············............. .
FIGURE 2. FREQUENCY DISPLAY
I
DESIGN MODULE
SIMULATOR MODULE
PROM MODULE
II
!zw
HSP43220 DDF SIMULATOR SPECIFICATION
D
E
Filter File
Probe Display
Save Cont. Output
Display Mode
PRES.DAR
HEX
YES
CONTINUOUS
Input Rate
Output Rate
33 MHz
100 kHz
INPUT SIGNAL SPECIFICATION
I
M
A
T
:::ECII
Q...J
00
..JO
W ...
~
Q
C
-
.•
Signal Origin
Signal itl
Operator
Signal #2
GENERATED
Amplitude
COSINE
1. 00
Frequency
5 kHz
+
GAUSS
Mean
0.00
StdDev
0.500000
E
FIGURE 3. SPECIFICATION MENU
8-5
Phase
0.00
DEC/-MATE
IESIGH
VIEW
ANALYSIS
COttFIG
OSSHELL
HSP43228 DDF SIPIULATOR - MI"
DDFDES
fEi!DiI
DDFPRO"
~]
~]
out_selh HIGH
out_selh LOU
Step Size
ItWllbel' Salll,les In
ItWllbel' SaIllP lea Out:
FIGURE 4. SIMULATOR - MAIN MENU
o
.";:)~I.L~···············································
................... {......................................,.,."...................
-0.
FIGURE 5. SIMULATOR PROBE DISPLAY
8-6
1
8
8
HSP-EVAL
USER'S MANUAL
DSP Evaluation Platform
February, 1993
Features
Description
• Single HSP-EVAL May be Used to Evaluate
a Variety of Parts Within the HSPXXXXX
Family of DSP Products
The HSP-EVAL is the mother board for a set of daughter boards based on
the HSPxxxxx family of Digital Signal Processing products. Each product
specific daughter board is mated with the HSP-EVAL to provide a mechanism for rapid evaluation and prototyping. As shown in Figure 1, the
HSP-EVAL consists of a series of busses which provide input, output, and
control to the target daughter board. These busses are brought out
through dual 96 Pin connectors to support daisy chaining HSP-EVAlj; for
multichip prototyping and evaluation.
• May be Daisy Chained to Support Evaluation of Multi-chip Solutions
• Parallel Port Interface to Support IBM
PC™ Based Evaluation and Control
• Three Clocking Modes for Flexibility In
Performance Analysis and Prototyplng
• Dual 96-Pln Input/Output Connectors
Conforming to the VME J2IP2 Connector
Standard
Applications
• PC Based Performance Analysis
HSPXXXXX Family of DSP Products
• Rapid Prototyping
of
For added flexibility, the input and control busses can be driven by registers on-board the HSP-EVAL which have been down loaded with data via
the parallel port of an IBM PCTM or compatible. In addition, a shift register
is provided to serialize data on the daughter board output busses for
reading into the PC via the status lines of the parallel port. Together, the
1/0 and Control registers can be used to drive the target daughter board
with a PC based vector set while collecting daughter board outputs to the
PC's disk.
Jumper selectable clock sources provide three different methods of
clocking the part under evaluation. In mode one, the clock signal is generated under PC based software control. In mode two, the HSP-EVAL.:s
on-board oscillator may be selected as the clock source. In mode three,
the user may provide an external clock through the 96 Pin Input Connector.
The HSP-EVAL was built into a 3U Euro-Card form factor with dual 96Pin
InputlOuput connectors. The 1/0 connectors conform to the VME J2IP2
connector standard.
DSP Evaluation Platform
!zw
:::lEU)
a...J
00
...10
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Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993 IBM PC'· is a Registered Trademark of IBM
8-7
File Number
3366.1
HSP45116-DB
USER'S MANUAL
HSP45116 Daughter Board
January 1994
Features
Description
• Designed for use with HSP-EVAL
The HSP45116-DB is a daughter board designed to mate with the HSP-EVAL for
rapid evaluation and prototyping of the HSP45116 Numerically Controlled Oscillator
Modulator. Together, the board set provides a mechanism to evaluate HSP45116
operation using IBM PCTM based I/O and control. As shown in the Figure 1, the
HSP45116-DB maps the input, output, and control signals of the HSP45116 to
three 50 pin headers. These headers mate with connectors on board the HSPEVAL to interface the HSP45116's various I/O and control signals with the HSPEVAt:s data busses. This interface establishes a path for PCTM based I/O and control of the HSP45116-DB via the HSP-EVAl.
• Access to HSP45116's input, output, and control signals through
three 50 Pin Headers
• HSP45116 control signal states
may be set through hardware
configuration or software.
• Two separate software packages
for daughter board 1/0 and
control
• High speed VO supported
Applications
• PC Based performance analysis
of HSP45116 when used with
HSP-EVAL
• Rapid prototyping
An IBM PCTM based software package is supplied which controls operation to the
HSP45116-DB/HSP-EVAL board set. The software package provides the user with
a DOS command line interface and graphical user interface for daughter board 1/0
and control. Since the software supports data acquisition from the HSP45116, software based signal analysis may be used to quantify part performance.
The degree of control exerted by the software varies depending upon the clock
supplied to the HSP45116-0B. If a high speed clock is supplied via the HSP-EVAL's
on board oscillator or external clock pin, the software can be used to exert real time
control. If a software controlled clock is provided, the HSP45116-DB can be driven
with a user defined data set while storing results back to the PC for later analysis.
The HSP45116-DB is a 6 layer printed circuit board which comes populated with
one HSP45116GC-25. The PC based software required to control the daughter
board via the HSP-EVAL is also provided
HSP45116 Daughter Board
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993 IBM PCTM is a Registered Trademark of IBM
8·8
File Number
3367.1
HSP45116-DB
The evaluation hardware for the HSP family of products consists of the motherboard, which forms the interface to the PC, and the
daughterboard, which carries the part under evaluation.
IZ
W
::&(1)
1l..J
00
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C
The hardware to evaluate the HSP45116 consists of the HSP-EVAL motherboard and the HSP45116-DB daughterboard. Two software packages are provided for the data and control interface between the HSP45116-DB and the PC. One is menu driven and the
other accepts DOS command lines.
8-9
HSP50016-EV
USER'S MANUAL
DDC Evaluation Platform
January 1994
Features
Description
• Single HSPS0016-EV may be Used to Evaluate
the HSPS0016
The HSP50016-EV is the evaluation board for the HSP50016 Digital Down Converter (DOC). It provides a mechanism for rapid
evaluation and prototyping. The HSP50016-EV consists of a
series of busses which provide input, output, and control to the
DOC. These busses are brought out through dual 96 Pin connectors to support daisy chaining HSP50016-EV's with other Harris
evaluation boards for multichip prototyping and evaluation.
• May be Daisy Chained to Support Evaluation of
Multi-Chip Solutions
• Parallel Port Interface to Support IBM PCTM
Based Evaluation and Control
• Three Clocking Modes for FlexlbilHy In Performance Analysis and Prototyplng
• Dual 96-Pin Input/Output Connectors Conforming to the VME J2IP2 Connector Standard
Applications
• PC Based Performance Analysis of HSPS0016
• Rapid Prototyplng
For added flexibility, the input and control busses can be driven by
registers on-board the HSP50016-EV which have been down
loaded with data via the parallel printer port of an IBM PCTM or
compatible. In addition, the DOC output can be read into the PC
via the status lines of the parallel port. Together, the 110 and Control registers can be used to drive the target DOC with a PC based
vector set while collecting output data on the PC's disk.
Jumper selectable clock sources provide three different methods
of clocking the part under evaluation. In mode one, the clock signal is generated under PC based software control. In mode two,
the HSP50016-EV's on-board oscillator may be selected as the
clock source. In mode three, the user may provide an external
clock through the 96 pin input connector.
The HSP50016-EV was built into a 3U Euro-Card form factor with
dual 96-pin Input/Ouput connectors. The 110 connectors conform
to the VME J2IP2 connector standard.
HSP50016 Evaluation Platform
IBM PC'" is a registered trademark of International Business Machines, Inc.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
COPYright © Harris Corporation 1994
8-10
File Number
3637
OS : ) - - - - - - - l 9
APPLICATION NOTES AND TECH BRIEFS
PAGE
APPLICATION NOTES
AN9401
Reducing the Minimum Decimation Rate of the HSP50016 Digital Down Converter ... .
9-3
AN116
Extended Digital Filter Configurations ....................................... .
9-13
AN9205
Timing Relationships for HSP45240 ........................................ .
9-23
AN9102
Noise Aspects of Applying Advanced CMOS Semiconductors .................... .
9-25
AN9207
Temperature Considerations .............................................. .
9-34
TB310
Common Abuses of the HSP43220 ........................................ .
9-36
TB311
HSP43220 - Design of Filters with Output Rates <2(Passband + Transition) ......... .
9-37
TB308
HSP43220 DECI.MATE Design Rule Checks ................................ .
9-39
TB309
Notes on Using the HSP43220 ............................................ .
9-41
TB312
TECH BRIEFS
HDF Bypass in the HSP43220 ............................................ .
9-44
TB313
Reading Out FIR Coefficients from the HSP43220 ............................. .
9-45
TB314
Quadrature Down Conversion with the HSP45116. HSP43168 and HSP43220 ...... .
9-46
TB316
Pipeline Delay Through the HSP45116 ..................................... .
9-53
TB319
Reading the Phase Accumulator of the HSP45106 ............................ .
9-54
TB317
Pipeline Delay Through the HSP45106 ..................................... .
9-56
TB318
The NCO as a Stable. Accurate Synthesizer ................................. .
9-58
TB305
Histogramming with a Variable Pixel Increment ............................... .
9-61
TB306
Cascading Multiple HSP45256 Correlators ................................... .
9-63
TB307
Correlation with Multibit Data Using the HSP45256 ............................ .
9-65
9-1
QU)
Zu.
Cw
U)wa:
I-CD
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ZO
Q.w
CI-
Harris Semiconductor
No. AN9401
Harris Digital Signal Processing
February 1994
REDUCING THE MINIMUM DECIMATION RATE
OF THE HSP50016 DIGITAL DOWN CONVERTER
Author: Dr. David B. Chester
Introduction
This application note discusses a method for reducing the
minimum decimation rate of the Harris HSP50016 Digital
Down Converter (DOC). As will be described in detail in this
application note, reduction in the minimum decimation rate is
accomplished by first sample rate expanding the data
stream which would normally be directly input to the DOC by
a factor L (placing L-1 zero valued samples between each
sampled data point). While the sample rate expansion process reduces the maximum input sampling rate that the
aggregate circuit (DOC and sample rate expander) can
accept by a factor of L, the ratio of the maximum output
bandwidth to input sample rate of the aggregate circuit is
increased by a factor of L. The output bandwidths as a function of HDF decimation rate M 1, aggregate circuit input sample rate fSA' and sample rate expansion L are:
=0.13957 LfSA/M1
-102dB BW =0.19903 LfSA/M 1.
-3dB BW
The decimation occurs in a two step process. Once the center of the band of interest is shifted to DC by the quadrature
modulator the real and imaginary outputs are each passed
to a high decimation filter (HDF). The decimation rate of the
HDFs, denoted M 1, is programmable from a minimum of 16
to a maximum of 32,768. The outputs of the HDF filters must
be scaled for gain compensation.
The lowpass response of the HDF has a gradual roll off
characteristic requiring a subsequent conventional FIR to
achieve a sharp transition. The DOC employs a fixed shaping filter for ease of use. The output bandwidth of the DOC is
a function of the input sampling rate, the programmable HDF
decimation rate and the fixed shape of the FIR. This relationship is:
-3dB BW
=0.13957 fslM1
=0.19903 fslM1
(3)
-102dB BW
(1)
(4)
where BW is the double sided bandwidth and fs is the input
sample rate.
(2)
The DOC is a fully programmable single chip down converter
architected to meet a wide range of down convert applications. A top level functional block diagram of the DOC architecture is shown in Figure 1. The principal goal of the DOC is
to filter and translate a band of interest to baseband and to
output the band of interest at a sample rate commensurate
with its bandwidth.
The FIR filter's passband compensates for the roll-off inherent in the passband of the HDF filter to meet the goal of a
low passband ripple [1].
The FIR filter automatically decimates by a factor of 4 if a
quadrature output format has been selected. When a real
output is selected, the FIR filters in the DOC automatically
decimate by a factor of 2. The FIR decimation rate is
MODULATOR
1""','",.''....' ' ' ' , 1 ' 1 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' " " " " " " " " " " " " ' 1
INPUT!
LPF
0.
!
~
!,
1
';
~~
t " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' " " " " " " ""
'),.
~
~
~
~
---
LPF
~~-+{x}-+~----+--+·III
:
~
~
HDF
FIR,
WEAVER
:
MODULATOR
'1
r-
~~--+{X~}-~
i
-
~"""
~
II
~
---------------------------------~
""~
SIN/COS
GENERATOR
LO
!
i
~
DECIMATION
RATE
SCALE
FACTOR
~
~""""""",~
FIGURE 1. DOC FUNCTIONAL BLOCK DIAGRAM
Copyright © Harris Corporation 1994
9-3
f-+
FORMATIER
.....---....~
RR·
"'"'' "'" " . " " " " " " , " " " " " " " " " , ---------------------------------~
!:
i
I
r-f-o
-.-~,:----+{X}-r------'I: HDF~
Q
~
Application Note 9401
denoted M2. In the real output mode the FIR outputs are
spectrally shifted by one fourth of the output sampling frequency and combined to produce a two sided spectrum.
This process is conceptually performed by the Weaver Modulator [2] following the FIR filter pair.
For quadrature output mode we see that the minimum DOC
decimation rate is
min(M) = min(M,) x M2 = 16 x 4 = 64.
(5)
The minimum decimation rate for real output mode is 32.
The resulting signal is converted into one of several selectable formats for output. See reference [1] for a detailed
description of the DOC and its operation.
A simple procedure can be used to reduce the minimum
aggregate decimation rate of the DOC with a minimum of
external circuitry. The trade-off in reducing the aggregate
decimation rate is a one to one reduction in maximum input
sampling rate.
Reduction of the Minimum Decimation
Rate
A rate change filter is an interpolation filter combined with a
decimation filter. The combining of the actual filtering processes is done by implementing the filter process that
requires the narrowest bandwidth of the two.
Because interpolation via digital filtering is not introduced in
the DOC data sheet, it is presented at a top level here.
Interpolation
Interpolation is the increase in the sampling rate of a signal
while preserving its original spectral content. The first step in
interpolation is to stuff L-1 zero valued samples between each
valid input sample to expand the sampling rate by a factor
of L. The zero stuffing causes the original signal spectrum to
be repeated L-1times. To perform the actual interpolation the
zero valued input samples must be converted to approximations of signal samples. This is equivalent to preserving the
original Signal spectrum. Thus, the zero stuffed input stream is
fiHered by a lowpass filter which has its passband at the original spectrum location and filters out all of the repeated spectra. This process is shown pictorially in Figure 2.
Rate Change
The minimum decimation rate of the DOC can be reduced by
using a minimal amount of external circuitry to convert the
DOC from a strictly decimating device to a rate change
device. By doing this, the DOC and external circuitry can first
interpolate the input signal to a higher sampling rate before
decimating it. This restricts the sampling frequency, and correspondingly the bandwidth, of the input signal to be less
than the clock frequency of the DOC. The result however is a
reduction in the end-to-end decimation rate of the aggregate
circuit.
The top level block diagram of a rate change filter [2] is
shown in Figure 3A. In the diagram the sampling rate of the
incoming signal is first expanded by a rate L by placing L-1
zero valued samples between each original sample. The
lowpass filter following the sample rate expander is
designed to: 1) remove the L-1 spectral images which result
from the zero padding; 2) multiply the result by a gain of L to
compensate for the power loss that occurs when the spectral
images are removed; and 3) limit the width of the spectrum
to allow sample rate compression by M without aliasing. An
example of this process is illustrated spectrally in Figure 3B.
--------~.I[[;]--------------~.~~------------~
b
/
LPF
bIn·"n
fS12
LfS12
h~~1
LfS12
FIGURE 2. BLOCK DIAGRAM SPECTRAL REPRESENTATION OF THE RATE CHANGE PROCESS
------.I[[;]----------~.I~----------~.~~-----FIGURE 3A. TOP LEVEL BLOCK DIAGRAM OF A RATE CHANGE FILTER
LPF
b
fS12
l&:D··n
h
LfS/2
,",
'/
FIGURE 3B. SPECTRAL REPRESENTATION OF THE RATE CHANGE PROCESS
9-4
B,
/
I
LfS12
'\'~
--
LfS/2M
Application Note 9401
The first and third design criteria are combined by taking the
more severe (narrowest bandwidth & shape factor) of the two.
Example: Decimation By 8
As an example case we will use the DDC to decimate by 8
with a quadrature output. In this example the HDF section is
programmed to decimate by the minimum value of 16 and
the FIR section automatically decimates by 4. The aggregate DDC decimation rate is 16 x 4 =64. To get a decimation
rate of 8 we must interpolate by
In most implementations the least common denominator
(LCD) of Land M is 1. In the application described here this
is not generally true because the DOC itself is not a rate
change device.
The DOC In a Rate Change Configuration to Reduce the
Minimum Decimation Rate
L = DDC Decimation
Desire Decimation
Figure 4 shows a conceptual block diagram of the modulation and filter processes in one of the two real processing
chains in the DOC. The two stage decimation filter configuration is a conventional architecture [2) with the exception of
the scaling multiplier between the first sample rate compressor and the second lowpass filter. The scaling multiplier is
used to compensate for the variable gain of the programmable HDF [1,3.4,5,).
(6)
=64/8=8
The sample rate expander therefore pads 7 zero samples
between each sample that enters it. The maximum sampling
frequency of the input signal is clk/8. For a maximum DDC
clock of 75MHz the maximum input clock for this example is
9.375MHz.
The input to the DDC is first multiplied by a sinusoid from the
digital local oscillator (LO). The sinusoids for the inphase
and quadrature paths are offset in phase by 90 degrees. The
product is passed to the HDF.
Assume that the input signal is wideband and that it is sampled at 2.5 times the highest frequency of interest. The
resulting spectrum at the input to the sample rate expander
is shown in Figure 6. Notice in the figure that to relax the
anti-aliasing filter design, aliasing is allowed to occur at frequencies above the maximum frequency of interest.
Placing a sample rate expander in front of the HDF and
using the fact that the multiplication of the input signal by the
LO is a linear operation we can redraw Figure 4 to get the
rate change capability shown in Figure 5.
In the configuration shown in Figure 5 it is assumed that the
constraint placed on the lowpass filtering by decimation is
more severe than the interpolation constraint. This is in general the case when the decimation rate of the DDC is higher
than the interpolation rate being generated by the external
sample rate expander.
From Figure 5 it can be seen that the sample rate of the
input to the sample rate expander has a maximum value of
clk/L where clk is the DOC clock.
The sample rate expander can be constructed simply as a
divide by L counter and a series of AND gates. Example
implementations are shown later in this applications note.
When the input signal has passed through the sample rate
expander and has been padded with 7 zero samples
between each input sample the one sided spectrum illustrated in Figure 7 results. Also shown in the figure is the HDF
lowpass response. Notice that the power in the original signal and each image is reduced by 18dB from the input power
level, defined as OdB in the figure. This phenomenon occurs
in digital interpolation because padding by L-1 zeros adds L1 spectral repetitions without adding power.
The interpolation process is completed by removing the spectral images via a Iowpass filter operation. This loss of power of
20 x log(L) dB in the filtering operation would result in a corresponding loss in dynamic range if it is not corrected for.
SCAUNG
r""""""'"''''''t-'_'~~_M_U.L:D:n...LL_.....'---L........-a___--'......_~
-120dB
OHz
f'Sf2
-14OdB
=&fSf2 =37.SMHz
FIGURE 19. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 6
CASE
OdB
OdB
-20dB
-2OdB
-40dB
-4OdB
-SOdB
-SOdB
-SOdB
-SOdB
-100dB
-10OdB
-120dB
-12OdB
-140dB
f's/2 = sf512 = 37.SMHz
OHz
FIGURE 20. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 5
CASE
-140dB
f'Sf2 = 4fSf2 = 37.SMHz
OHz
FIGURE 21. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 4
CASE
HDF RESPONSE
OdB
f'Sf2 = 3fSf2
OHz
= 37.SMH.
FIGURE 22. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 3
CASE
HDF RESPONSE
OdB
-20dB
-20dB
-40dB
-40dB
-SOdB
-SOdB
-SOdB
-SOdB
-100dB
-100dB
-120dB
-120dB
-140dB -+;...L-II......I-l...........IJI...L..IJIL-I.......cL.L...I.u.........IJ£..L..a.,
~,~-\~~:~i:~
';
-140dB -+.....;..~L:...:..'""'J-:.:...I.L._Ju..__IL.I._.LJ_~.....;......,
OHz
f'Sf2 = 2fSf2 = 37.SMHz
,,'
;
{,
,
OHz
f'Sf2
,
.'
~
>,
= 32fSf2 =37.SMHz
FIGURE 23. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 2
CASE
FIGURE 24. REPEATED INPUT SPECTRUM WITH THE HDF
RESPONSE CURVE AND NEAR DC IMAGES
SUPERIMPOSED FOR THE INTERPOLATE BY 32
CASE
Center Frequency Calculation
pie rate expander the input sample rate is 11L times the DOC
input sample rate. Therefore, the maximum valid phase step
relative to the input sample rate is 1/L that of the DOC. likewise, the frequency resolution is reduced by L.
Decreasing the minimum decimation rate of the DOC by
interpolation impacts the calculation and resolution of the
local oscillator control words with the exception of Phase
Offset.
The Phase Generator in the DOC uses a 33 bit phase accumulator to generate an 18 bit phase word which controls the
local oscillator (1). In continuous carrier wave (CW) down
convert mode the 32 bit Maximum Phase Increment is used
to control the phase step between successive Phase Generator outputs. The Maximum Phase Increment represents
phase increments from 0 to x(1_2- 32 ) relative to the DOC
input sampling rate. When the DOC is proceeded by a sam-
We now illustrate the afore stated points by way of example.
Assume a 4MSPS input and a desired decimation of 4. The
DOC would be clocked at 64MHz and would be preceded by
a sample rate expander which up samples by a factor of 16.
The HDF decimation rate would be set to 16.
The Maximum Phase Increment can be programmed from
0H to FFFFFFFFH representing an LO frequency from DC to
just under 32MHz. However, the highest input frequency into
9-10
Application Note 9401
DATA
IN
QUAD DUAL PORT REG.
4
10
11
DATA
IN
HSP50016
4
Q
S
DATA 04
4
QUAD DUAL
PORT REG.
DATA 4-7
4
4
DATA 8-11
4
DATA 12-15
QUAD DUAL
PORT REG.
DATA
IN
4
DATA
IN
4
CLK
II-L
4
Q3
CEP
Vee
DOC
CLOCK
CET
SR
4 BIT COUNTER
FIGURE
25. AN EXAMPLE SAMPLE RATE EXPANSION CIRCUIT WITH A MAXIMUM EXPANSION OF 8 AND A MAXIMUM CLOCK
OF 65MHz
the sample rate expander is 2M Hz which is in turn the highest valid LO frequency. This LO frequency corresponds to a
Maximum Phase Increment value of FFFFFFFFH/16 or
FFFFFFFH·
PAL 2
HSPSOO16
If the DOC sampling rate were 4 MHZ the frequency resolution would be 4MHzf233. Since the DOC sampling rate is
64MHz the frequency resolution is 64MHzf233, or 1ILth that
of 4MHzl233.
DATAO-Il
In Chirp mode the Maximum Phase Increment, Minimum
Phase Increment, and Delta Phase Increment must also be
calculated for the input sample rate relative to the DOC sampling rate.
Example Sample Rate Expander Circuit
Figure 25 shows an example sample rate expander circuit
built around a high speed CMOS synchronous counter and
four high speed CMOS quad dual port registers.
The synchronous counter is preset with 9 minus L, the
desired interpolation rate. The count enable parallel (CEP),
count enable trickle (CET), and synchronous reset (SR)
inputs are tied high. For L-1 counts of the DOC clock the
counter's 03 output line is low and is used to select the
grounded 11 inputs into the quad dual port registers. On the
Lth count 03 goes high, initiating two actions. First it selects
the input data on the 10 inputs to the quad dual port registers. Second, it presets the counter. The high rate outputs of
the quad dual port registers are connected to the DOC's data
inputs. This action results in sample rate expansion by L.
This circuit can be used for DOC clock rates up to approximately 65MHz and interpolation rates of up to B. Additional
ANDing logiC can be attached to the counter outputs to
increase the possible interpolation rates to 16.
DA1~
DATA 10-15
INA
17-L
17- L
INB
INC
17-L
IND
INPUT DATA
CLOCK
(TO AID CONVERTER)
17-L
Figure 26 shows a similar circuit using two PAL:s.
9-11
FIGURE 26. AN EXAMPLE SAMPLE RATE EXPANSION CIRCUIT USING TWO PALS WITH A MAXIMUM
EXPANSION OF 8 AND A MAXIMUM CLOCK OF
75MHz
Application Note 9401
The first PAL is configured as a counter and six AND gates
with one input of each AND gate tied to a common control
line coming from the counter and the other input connected
to an input data line. The logical configuration of the first PAL
is as follows.
When the counter rolls over 0 goes high resulting in two
actions. First the input data is passed through the AND gates
and into the registered outputs to be passed to the DOC.
Second, it reloads the counter to begin the count sequence
anew.
DOx = Dlx and 0
This action results in sample rate expansion by L. This circuit
can be used for DOC clock rates up to the maximum 75MHz
and interpolation rates of up to 8. Additional logic can be
incorporated in the counter to increase the possible interpolation rates.
=(0 and A) + (0 and INA)
=(0 and A and S) + (0 and INB) + (0 and A and B)
C =(0 and A and B and C) + (0 and INC)
A
B
+ (0 anq A"8ridB and C)
o =(A and Band C and D) + (0 and IND)
Bibliography
The other PAL is configured as ten AND gates with one input
of each AND gate tied to a common control line coming from
the counter via an input line and 'the other input connected to
an input data line. Logically the second PAL is configured as
follows.
DOx
=Dlx and 0
All outputs are registered.
The operation of this circuit begins as the counter is preset
with a value of 17 minus L, the interpolation factor L can be
up to 8. On successive DOC clocks the counter counts up
until it rolls over to zero. Until the roll over occurs 0 is in a
high state and thus 0 is in a low state. Since 0 is in a low
state all data outputs are in a low state. This stuffs zeros
between the low rate data input to the PALs.
(1) HSP50016 Data Sheet, Harris Semiconductor, Melbourne, FL, 1993.
(2) Crochiere, R.E. and Rabiner, L.R., Multirate Digital Signal Processing, Prentice-Hall, 1983.
(3) Hogenauer, E.B., "An Economical Class of Digital Filters
for Decimation and Interpolation:' IEEE Trans. on ASSP,
Vol. ASSP-29, No.2, pp. 155-162, April 1981.
(4) Riley, CA, et. aI., "High-Decimation Digital Filters:' Proc.
of ICASSP91, Vol. 3, pp. 1613-1616, Toronto, May, 1991.
(5) Chester, D.B, et. al., "VLSI Implementation of a Wide
Band, High Dynamic Range Digital Drop Receiver:' Proc.
of ICASSP91, Vol. 3, pp. 1605-1608, Toronto, May, 1991.
9-12
Harris Semiconductor
-
~
==
'5.. ==
No. AN116
Harris Digital Signal Processing
February1994
EXTENDED DIGITAL FILTER CONFIGURATIONS
Introduction
Harris HSP43891, HSP43881and HSP43481 Digital Filters
(DFs) perform high speed sum-ol-products operations.
These video speed devices operate at 30MHz, offering substantial improvement in processing speed over other available technology. Throughputs in excess of 30MHz are
achieved using multiple devices.
The DF data sheet explains how multiple DFs can be easily
cascaded to achieve long lilters with 8 bit data and coefficients. This note presents extensions of the basic cascaded
configuration for:
• Designing Extended Length Filters Using a Single Device
(the Number of Taps Exceeds the Number of Cells).
• Implementing Higher Precision (Greater Than 8 or 9 Bits)
Full Speed Designs Using Multiple Devices.
weighted sum of the new input value and the L-1 previous
inputs, where L is the order of the filter. With the tapped delay
line architecture (Figure 1) the filter coefficients remain fixed
while the input data shifts from cell to cell on each clock cycle.
The DF's architecture (Figure 2) is different from the traditional tapped delay line filter. In the DF the filter coefficients
shift from cell to cell with each clock cycle. As each new data
sample becomes available it is distributed to all of the cells
at the same time. In addition, every DF cell contains its own
multiplier and accumulator. This allows each cell to maintain
an independent sum-of-products in its accumulator. A new
output value becomes available on each clock cycle by properly sequencing the filter coefficients through the cells.
• Implementing Higher Precision Designs Using a Single
Device.
X(n)
It is assumed that the reader has a basic knowledge of filter
design and some digital hardware experience. Readers who
require more detailed information on the electrical characteristics of the DF family devices should refer to the Harris DF
engineering data sheets. Harris also provides a comprehensive set of hardware and software development tools.
N
yen) "
The Finite Impulse Response Filter
:E h(n)x(n-m)
m.. o
The finite impulse response (FIR) filter is simply a finite-length
sum-of-products digital filter. Each output sam~le is a
FIGURE 1. DIRECT FORM REPRESENTATION OF FIR FILTER
DATA
x(n)
DATA
hen)
N-1
yen) = :E h(m)x(n-m)
m"o
FIGURE 2. OF CELL DIAGRAM
COPYright © Harris Corporation 1994
9-13
•
Application Note 116
Each cell's accumulator is cleared after its contents are
output This allows accumulation of the next sum-of-products to begin. Note that the filter coefficients enter from the
left, shifting one cell to the right with each clock cycle.
A single device may be used to implement filters with a large
number of coefficients. In this case the number of filter taps
will exceed the number of OF cells. This requires manipulating the input data and filter coefficient sequences, maintaining the proper sum-of-products in each cell's accumulator.
This implementation is described in greater detail in the
following section.
Eight Tap Filter With a Four Cell Device
A simple example is the best way to demonstrate how data
and coefficients are properly sequenced. Table 1 illustrates
the situation when an eight tap filter is computed in a single
4 cell HSP43481. The table lists information in six columns.
The first column shows the initial 21 clock cycles, which is
enough to evaluate the example. The next four columns
represent the actions taking place in each of the four OF
cells as a function of the clock. The final column shows the
output results, also a function of the clock.
Within the filter cell are internal pipeline delays. The result is
a startup delay of three CLKs before the data and coefficients present at the input of the OF are processed and
stored in the accumulator of the first cell. This delay is not
TABLE 1.
DATA
SEQUENCE
INPUT
COEFFICIENT
SEQUENCE
INPUT
relevant to the sequential operation of the OF and will be
ignored in subsequent discussions (also ignored in
Table 1).
The basic computational sequence is shown below:
CLK 0 - Initial data point Xo is made available to all four
cells. At the same time coefficient C7 enters Cell O.
• The First Product (C7 x XO) is Computed and Stored in
Accumulator of Cell O.
CLK 1 - Xl is made available to all four cells. At the same
time coefficient Ce enters Cell 0, shifting C7 to Cell 1.
• The Accumulator of Cell 0 is Updated With the Additional
Term Ce x Xl.
• The Product C7 x Xl is Computed and Stored in
Accumulator of Cell 1.
CLK 2 - X2 is made available to all four cells. At the same
time coefficient Cs enters Cell 0, shifting C7 to Cell 2 and
Ce to Cell 1.
• The Accumulator of Cell 0 is Updated With the Additional
Term Cs x X2.
• The Accumulator of Cell 1 is Updated With the Additional
Term Ce x X2.
• The Product C7 x X2 is Computed and Stored in
Accumulator of Cell 2.
etc.
HSP43481 8 TAP FIR FILTER SEQUENCE USING SINGLE 4 CELL DEVICE
X14· .. X S,X4,X3,·· X l,XO
Co···Ca, C7,O,O,O,Co··· Ca,C7
-----,1
---+I..._D_F_..JI+--
... Y14, Y13, Y12, Yll .. · Yg, Ya, Y7
ClK
CEllO
CEll 1
CELL 2
CEll 3
SUM/CLR
0
1
C7 XXO
+Ca xX l
+CSxX2
+C4 XX3
+C3 xX4
0
0
0
0
-
2
3
4
S
a
7
C7 xX l
+Ca xX 2
+CS xX3
+C4 XX4
+C3 XXS
+C2 xX e
a
+C2 XXS
+Cl xX e
+COxX7
0
9
0
+Cl xX7
+CoxXa
0
10
0
0
11
0
12
C7 xX4
+CexXs
13
+CsxXe
14
+C4 XX7
+C3 xXa
lS
le
17
la
+C2 xX 9
+Cl XXlO
C7 xX 2
+Ca xX3
+CSXX4
+C4 XXS
+C3 xX e
+C2 xX7
+Cl xXa
C7 xX3
+Ca XX4
+CsxXs
+C4 xXe
+C3 xX7
+C2 xXa
+CoxXg
+Cl xXg
0
0
+CO XX 10
0
0
0
Cell 0 (Y7)
Cell 1 (Ya)
Cell 2 (Yg)
Cell 3 (Y1O)
C7 XXe
0
+Ce XX7
+CsxXa
-
C7 XX S
+CexXe
+CSXX7
0
0
+C4 XXa
+C3 xX9
+C2 XXlO
+C4 xX 9
+C3 x Xl0
C7 XX7
+CexXa
+CsxXg
+C4 XX10
+Cl xXll
+C2 x Xll
+C3 x Xll
CeIlO(Yll)
+Cl XX12
+C2 xX 12
+Cl x X13
+CO x X14
Cell 1 (Y12)
19
+CoxXll
0
20
0
+COxX12
0
21
0
0
+CO xX 13
0
9-14
Cell 2 (Y13)
Cell 3 (Y14)
Application Note 116
This process continues until eight taps have been
computed and accumulated in each cell. This happens first
in Cell 0, followed one ClK later by Cell 1, two ClKs later by
Cell 2, and three ClKs later by Cell 3. Output points
become available after each cell accumulates the sum of
eight taps in the order given above.
After Cell 3's output becomes available, we are ready to
begin work on the next four output points. We can cycle the
eight filter coefficients in the same fashion as before but the
input data is out of sequence. Before computing the fifth
output point the DF requires X4 to be available at the data
input. Since X4 passed by seven ClKs ago (during ClK 4)
some method of storing the previous seven data points is
necessary.
In order to access the previous seven data values they must
have been originally stored in some form of sequential
memory. FIFOs work very well and will be discussed in the
next section. Starting with ClK 11 the taps once more begin
to accumulate in each of the four cells.
The result of re-accessing data after every four output
points is to lower the effective throughput. The output rate
drops about fifty percent to a rate of four output points for
every eleven ClKs.
L Tap Filter With an N Cell
Device Where L>N
The example above leads to the more general case of implementing an l tap filter with an N cell device (l>N). When an
l tap filter is implemented using an N cell DF (where l>N),
the DF computes a block of N filter output samples at a time.
Between these output blocks there are l-1 ClK cycles
during which no valid output points are available. Therefore,
generating a block of N output points requires l+N-1
ClKs. During these l+N-1 ClKs there are l+N-1 new
input samples being clocked into the DIN (Data IN) port.
It can be seen from Table 1 that N outputs are read out of
the DF during the last N ClKs of each l+N-1 ClK
sequence. After inputting the first l data samples N-1 ClKs
are required to flush the coefficients from the cells. The final
l-1 of the previous l+N-1 input samples must be
re-submitted at the input port. After the outputs are read out
an additional l+N-1 samples are fed in and the process
repeats itself until no more data is available.
In this paper, throughput is defined as the average rate at
which outputs are computed by the DF. When the number
of taps exceeds the number of filter cells, the necessity to
re-access the data stream determines the maximum
throughput. The generalized performance of an l tap, 8x8
FIR filter is shown below. let:
l == Number of taps
N == Number of filter cells in DF
R == Maximum clock rate of DF (20, 25.6, or 30MHz)
Fs == Desired throughput (MHz) where R>Fs
If l, N, and R are known then:
Fs == N x R/(l+N-1)
H l, R, and Fs are known then:
N == Fs (l-1)/(R-Fs)
Since there are either four (HSP43481) or eight
(HSP43881) cells in each DF, the required number of DFs
can be computed as:
# of 4 cell DFs == N/4 (round up to next integer value)
# of 8 cell DFs == N/8 (round up to next integer value)
An example design with l == 128 taps, Fs == 5MHz, and
R == 20MHz would yield:
N == 5 x 127/15 == 43 cells
# of 4 cell DFs == 43/4 == 11
# of 8 cell DFs == 43/8 == 6
Optimum arrangement == 40/8 + 3/4 == Five 8 cell and one 4
cell DFs.
The sequencing of the input data can be realized in various
ways, with the simplest design using FIFOs. Figure 3 shows
the block diagram of a design using an eight cell DF. The
input data buffered in two FIFOs (each must have threestate outputs).
An 8 bit counter is configured to count modulo l+N-1. To
initialize the system, the first l-1 data samples are passed
through FIFO #1 and written into FIFO #2. While this
occurs N more samples are clocked into FIFO #1. Following that a repetitive steady state sequence begins as shown
below:
1. Clock the first l-1 samples from FIFO #2 into the DF.
2. Clock N samples from FIFO #1 into the DF.
3. Clock the last l-1 samples of the sequence in steps 1
and 2 back into FIFO #2.
4. Clock the next N samples into FIFO #1 concurrently
with steps 1-3.
This sequence of steps 1 through 4 can be repeated ad
infinitum.
The output data is available in blocks of N points separated
by l-1 ClK cycles. FIFO #3 acts as a rate buffer for the
output and is optional. The coefficient memory contains the
l coefficients followed by the necessary N-1 zeros.
A design example using the above technique might include
a 57 tap filter with a sample rate of 2.5MHz. This can be
done with a single 8 cell device operating at 20M Hz.
Higher Precision Filters and Correlators
Several digital filtering applications require wider wordwidth
calculations to maintain precision. The DFs are designed to
be flexible in creating filters with input precision levels of 8,
16, 24, 32 bits or greater.
The first step is to restructure the data and/or coefficients
into 8 bit quantities which can be processed by the DF.
9-15
Application Note 116
iRAsE
CLK
AD-2
CADD---I~
DATA
fifO #1
....r~=_=-l_----~OUTPUT
W~_
..r----l
INpuT _ _....
t---.-....
""I
iii
Wi---I-t.._ _--..l
Df
HSP43881
DATA
L __J"'IIf--- ii3
DIN
ii2---I-t.._ _--..l
FIGURE 3.
BLOCK DIAGRAM OF AN 8 CELL DF CONFIGURED TO IMPLEMENT EXTENDED FILTER LENGTHS
(UP TO 249 TAPS)
These quantities are used to form the partial products of the
larger multiplication involving the full precision data and
coefficients. An example of segmenting the partial products
of a 16x8 multiplication (16 bit coefficients and 8 bit data)
would be:
C(16 bit) = CH x 28 + CL x 20
H = High Order Byte
X(8 bit) = X x 20
L = Low Order Byte
Care must be taken when combining the upper and lower
partial sums-of-products into each complete output result.
Figure 5 illustrates how the upper and lower sums of partial
products for each output point must be re-combined. Sign
extension must be used if more than 26 bits are required
from the output stage representing the least significant sum
of partial products.
Two separate techniques can be used in determining higher
precision results:
Consequently,
C x X = (CH x 28 + CL x 20 )X x 20
= CHX x 2 8 + CLX x 2 0
The process of convolution or correlation requires repeated
multiply and accumulate operations. The resulting partial
output word widths are a function of the number of MAC
operations and of the coefficient scaling. Although each
partial product is only 16 bits wide, the sum of the partial
products in the output stage is allowed to accumUlate up to
a maximum width of 26 bits.
1. Use separate DFs, combining the two partial products
using external adders.
- Throughput equals the clock rate of the OF.
2. Accumulate the two partial products in separate cells of
a single OF.
- The SHADD (SHift and ADD) feature of the output
adder allows the data to be properly aligned and
combined.
- Throughput is determined by the number of taps,
partial products, and OF cells, as well as the clock rate
of the OF.
9-16
Application Note 776
The equations describing the filtering operation are the
same for either technique and can be given as:
N-1
YIn) = L C(i)X(n-i)
1=0
However: (CH x 28
+ CL)X = CHX x 28 + CLX
N-1
Therefore: yIn) =
L
N-1
L
CH(I)X(n-i) x 28 +
i=O
CL(I)X(n-1)
i=O
Assuming the coefficients are represented as two's complement numbers, the least significant byte has to be treated as
a positive (unsigned) number. The TCCI input of the OF is
used to take care of this.
Word-Size Extension at Full Speed
Full performance filters with extended precision data and/or
coefficients are easily designed. This is achieved by
computing the partial products in separate OFs and
combining their results with external adders. When external
adders are used the system performance is limited only by
the throughput of the OF itself.
The filter equations listed directly above can be expanded
into their partial products and grouped for processing. An
TABLE 2.
expansion of the first four output points resulting from the
convolution of 16 bit coefficient and 8 bit data is shown
in Table 2.
In this case, for a 4 tap filter, each device accumulates four
partial products at once, one in each cell. The output adder
combines these partial products into the proper result. The
sequence table (Table 2) shows the results of the multiply
accumulate operations for one device (OFO).
Figure 4 is a block diagram that directly implements the
grouping given above. OFO is generating the CLX partial
products while OF1 is generating the partial products for
CHX. The two 8x8 partial products are generated in
separate DFs and combined with an external adder. Notice
that the lower and upper coefficients bytes are separated
and used to supply different OFs. Using this design the
throughput is limited only by the OF (up to 30MHz).
The adder stage of Figure 4 merits further discussion. Each
4 cell OF has 26 output lines (SUMO-25). Therefore, if all the
available bits were preserved we would have a 34 bit sum
as shown in Figure 5. However, many designs require only
16 output bits. Which 16 bits are selected depends on the
coefficient scaling and the input signal level.
HSP43481 4 TAP SINGLE PARTIAL PRODUCT FIR FILTER
y(O) = CH(O)X(O) x 2 8
+ CH(1 )X(1) x 2 8
+ CL(O)X(O)
+ CL(1 )X(1)
y(1) = CH(O)X(1) x 28 + CL(O)X(1)
+ CH(1 )X(2) x 28 + CL(1 )X(2)
+ CH(2)X(3) x 28 + CL(2)X(3)
+ CH(2)X(2) x 2 8 + CU2)X(2)
+ CH(3)X(4) x 28 + CU3)X(4)
+ CH(3)X(3) x 2 8 + CL(3)X(3)
I~
~I~
~I
OF1
CeliO
I~
OFO
CeliO
+ CH(3)X(5) x 2 8 + CU3)X(5)
~I..
OF1
Cell 2
~I
OFO
Cell 1
y(3) = CH(O)X(3) x 28 + CL(O)X(3)
+ CH(1)X(4) x 28 + CL(1)X(4)
+ CH(2)X(5) x 28 + CL(2)X(5)
y(2) = CH(O)X(2) x 28 + CUO)X(2)
+ CH(1 )X(3) x 2 8 + CU1 )X(3)
+ CH(2)X(4) x 2 8 + CU2)X(4)
I..
~I..
OF1
Cell 1
+ CH(3)X(6) x 28 + CL(3)X(6)
I~
~I..
~I
~I
OFO
Cell 2
OF1
Cell 3
OFO
Cell 3
etc.
CLK
CELLO
CELL 1
CELL 2
CELL 3
OUTPUT
0
CL3 x XLO
0
0
0
1
+CL2 xX U
CL3 XX U
0
0
2
+CL1 xXL2
+CL2 xX L2
CL3x XL3
0
3
+CLOxXL3
+CU xXL3
+CL2 XX L3
CL3x XL3
Cell o(YL3)
+CL2 XXL4
Cell O(YL4)
4
CL3XXL4
+CLOXXL4
+CU XXL4
5
+CL2 xXL5
CL3 xX L5
+CLQxXL5
+CU xXL5
Cell 0 (YL5)
6
+CU XXL6
+CL2 XXL6
CL3 xX L6
+CLOx XL6
Cell o(YL6)
7
+CLOxXL7
+CU xXL7
+CL2 xXL7
CL3 xX L7
Cell 0 (YL7)
9-17
•
Application Note 116
DATA IN
(0-7)
DIN
8
,--...
CIN
UPPER BYTE
OF
COEFFICIENT
PROM
BITS 8 - 15
DF1
(481)
ADRD-1
SUMD-17
18
MS8
A
"D':'/-' lSB
ADDER ~ OUTPUT
DIN
8
~
ClK
CIN
SEQUENCER
FIGURE 4.
DFD
....
DF1
DFD
(481)
ADRD-1
lOWER BYTE
OF
COEFFICIENT
PROM
81TS 0 - 7
~B
SUMD-17
L
BLOCK DIAGRAM OF A 30M Hz, 4 TAP, 16x8 FIR FILTER
-
•
26
.. I1--- +-1
26
8
~
SUM
I-
34
.. 1
SELECTED
WORD
FIGURE 5.
IDEAL OUTPUT STAGE ADDER
9-18
D'S
Application Note 116
The results for the 16x8 example can be extended to the
general case of more than four taps. Let:
L = Number of taps
N = Total number of filter cells required
R = Maximum clock rate of DF (20, 25.6, or 30MHz)
Fs = Desired throughput (MHz)
For a full speed (Fs = R) 16x8 design:
single device. An expansion olthe firstfour output points resulting from the convolution of 16 bit coefficient and 8 bit data is
shown below.
The groupings are the same as in the earlier case using multiple DFs. However, in this case individual cells within one DF
are responsible for generating the partial products. This
method of processing eliminates the need for an external adder
in exchange for lower throughput.
N = 2L
There are either four (HSP43481) or eight (HSP43881) cells in
each DF. Therefore, the number of DFs can be computed as:
# of 4 cell DFs = 2 x [L/4 (rounded up to next integer value)]
# of 8 cell DFs = 2 x [L/8 (rounded up to next integer value)]
The sequence table (Table 3) shows the results of the multiply
accumulate operation for the separate cells of a 4 tap 16x8 FIR
filter. Cells 1 and 3 accumulate the partial products CHX. Cells
o and 2 accumulate the partial products CLX.
An example design with L=15 taps and Fs = R = 25MHz
would yield:
After computing and outputting the first result Cell 0 is ready to
accumulate the next partial products. At this point (CLK 11)
Cell 0 needs to re-access X2, which was last available during
CLK 5. In order to accomplish this a temporary storage,
sequential memory (such as a FIFO) is necessary. The design
of Figure 6 shows such a FIFO based design.
# of 4 cell DFs = 2 x [15/4] = 8
# of 8 cell DFs = 2 x [15/8] = 4
Word-Size Extension Using One Device
The second technique for extending the word width
accumulates the partial products in separate cells of a
y(0) = CH(O)X(O) x 28
+ CL(O)X(O)
y(1) = CH(0)X(1) x 28
+ CH(1)X(1)x28 + CL(1)X(1)
+ CL(0)X(1)
+ CH(1 )X(2) x 28 + CL(1 )X(2)
+ CL(2)X(2)
+ CH(2)X(3) x 28 + CL(2)X(3)
+ CH(3)X(3) x 28 + CL(3)X(3)
+ CH(3)X(4) x 28 + CL(3)X(4)
I..
~I..
~I
CH(2)X(2) x 28
~I..
I..
Cell 1
y(2) = CH(0)X(2) x 28
~I
CeliO
Cell 3
+ CL(0)X(2)
+ CL(0)X(3)
+ CH(1 )X(4) x 28 + CL(1 )X(4)
+ CH(2)X(5) x 28 + CL(2)X(5)
y(3) = CH(0)X(3) x 28
+ CH(1)X(3) x 28 + CL(1)X(3)
+ CH(2)X(4) x 28 + CL(2)X(4)
+ CH(3)X(5) x 28 + CL(3)X(5)
I..
~I..
~I
Cell 1
Cell 2
+ CH(3)X(6) x 28 + CL(3)X(6)
~I..
I..
CeliO
Cell 3
9-19
~I
Cell 2
Application Note 116
TABLE 3,
HSP43481 4 TAP, 16x8 FIR FILTER SEQUENCE
INPUT DATA
DIENB
SEQUENCE
X8.' ". X4. XS." ,.X2. X4. X3.X2.X1.XO ~
COEFFICIENT
SEQUENCE CL3. CH3. O. O. CLO. CHO. CL 1. CH1. CL2. CH2. CL3. CH3
OF
Y(5)", Y(4)", Y(3)
CLK
CELLO
CELL 1
CELL 2
CELL 3
OUTPUT
-
2
CH2 XO
CL3 xO
CH3 xO
-
3
+CL2 XX1
+CH2 XX1
CL3 XX1
CH3 xX1
4
CH1 xO
CL2 XO
CH2 XO
CL3 xO
0
CH3 xO
-
-
1
CL3 xXo
CH3 xXO
-
-
5
+Cu xX2
+CH1 xX2
+CL2 XX 2
+CH2 xX 2
S
CHOxO
Cu xO
CH1 XO
CL2 xO
-
7
+CLo xX3
OxO
+CHo xX3
+CU xX3
+CH1 xX3
YL(3)
8
CLOXO
CHOXO
Cu xO
-
9
OXX4
OxX4
+CHO xX 4
YH(3)
CLOXO
-
OXX2
YL(4)
10
CH3 xo
OxO
+CLO xX 4
OxO
11
CL3 xX 2
CH3 xX 2
OXX2
12
CH2 xo
CL3 xO
CH3 xO
OxO
-
13
+CL2 xX3
+CH2 xX3
CH3 xX3
YH(4)
CL3 xO
+CH2 xX 4
-
14
CH1 XO
CL2 xO
CL3 xX3
CH2 xO
15
+CU xX4
+CH1 xX4
+CL2 xX4
1S
CHOxO
Cu xO
CH1 xO
CL2 xO
-
17
+CHO XX5
+CU XX5
+CH1 xX5
YL(5)
18
+CLO xX5
OxO
CLOXO
CHOXO
Cu xO
-
19
OxXs
OxXs
+CHOXXS
YH(5)
CLOXO
-
OXX4
YL(S)
20
CH3 xO
OxO
+CLOXXs
OxO
21
CL3 xX4
CH3 xX 4
OxX4
22
CH2 xO
CL3 xO
CH3 xO
OxO
-
23
+CL2 XX5
+CH2 xX5
CL3 xX 5
CH3 xX5
YH(S)
-
24
CH1 xO
CL2 XO
CH2 XO
CL3 xO
25
+CU xXs
+CH1 xXs
+CL2 xXs
+CH2 xXs
CAOO--~
DATA
INPUT-----r~::-1-'l~:JL--r_:=----J
m----~L-
____
~
ClKS
W2---~.,
____
OUTPUT
DATA
~~-----R2
iii
'BIT FIELD DEPENDS ON COEFFICIENT
SCALING AND NUMBER OF TAPS.
FIGURE 6,
ClK16--~
16
BIT
REG
16x8 4 TAP FIR FILTER BLOCK DIAGRAM
9·20
Application Note 116
In order to interlace the necessary zeros between data
samples we must toggle the DIENB control line. This line is
driven low when passing a valid data sample to the X
register and set high when loading the X register with zero.
The sequencing of the input data through the FIFOs is
similar to the example given in Figure 3.
contents are available to the outside world as either the 16
LSBs (SENBL), 10 MSBs (SENBH), or all 26 bits
(SENBL+SENBH).
The 26 bit adder feeding the output buffer has two possible
inputs. The first input represents the contents of the
selected cell. The zero mux determines whether the other
input to the adder is zero or the 18 MSBs of the output
buffer. A high on the SHADD input selects the 18 MSBs of
the output buffer and a low on the SHADD input selects
zero. The results from the adder are immediately stored in
the output buffer.
The output stage (Figure 7) plays a key role in determining
the final results. In the output stage there are several control
signals. The most important signals controlling the output
stage are SHADD (SHift and ADD), ADRO-1 (cell AdDRess),
SENBL (SumO-15 ENaBled), and SENBH (Sum16-25
ENaBled). SENBL and SENBH are always asserted in this
example, enabling the three-state output buffer and allowing the external register to clock in data at the proper time.
SHADD and ADRO-1 are used to control the flow of data
through the output stage.
Data reaches the three-state buffer by one of two separate
paths. The first path routes the data directly from the cell
result multiplexer through the output multiplexer and onto
the output bus. The second path is from the cell result
multiplexer, through the adder, and finally onto the output
bus. Both of these routes will be used in order to create the
final result from the partial products.
The contents of a selected cell (ADRO-1) are routed to two
separate locations within the output stage; the 26 bit adder
and the output mux. From the output mux the 26 bit cell
CELL RESULTS
0
1
ADRO.D-ADR1.D
SIGN EXT
<18.25>
26
18 (LSB.)
<0.17>
RESEID
SHADD
RESET.D
CLK
<8.25>
26
0·.
RESElD
SUMO-25
CLK
FIGURE 7.
OF OUTPUT STAGE
9-21
Application Note 116
After the partial products are made available to the output
bus they are stored in temporary registers. This allows the
two sections of the final result to be combined properly.
Following this the full result may be stored directly into
some form of memory. Figure 6 shows a block diagram
illustrating the complete concept.
The following summary describes the sequence of events
listed in Table 3 (also refer to Figures 6 and 7).
elK 0-5
• Each Cell Is Accumulating Partial Product Data
• SHADD Not Asserted
elK 6
• Cell 0 Selected (ADRO-1 = 0)
• Erase Accumulator of Cell 0 (ERASE = 0)
• SHADD Not Asserted
elK 7
• Cell 0 Contents Added to Zero and Available at Input to
Output Buffer
• Cell 0 Contents Available at SUMO-15
• Cell 1 Selected (ADRO-1 = 1)
• Erase Accumulator of Cell 1 (ERASE = 0)
• SHADD Not Asserted
elK 8
• External 8 Bit Register Clock Asserted. lower 8 Bits of
SUMO-15 (least Significant Byte of Y(3» Entered Into
External 8 Bit Register
• Cell 0 Contents Entered Into Output Buffer
• Cell 1 Contents Added to Zero and Available at Input to
Output Buffer
• SHADD Asserted
elK 9
• Shift Cell 0 Contents Down 8 Bits and Add to Contents of
Cell 1 (Output Buffer). This 16 Bit Value Becomes Available at SUMO-15
• SHADD Not Asserted
elK 10
• External 16 Bit Register Clock Asserted. All 16 Bits of
SUMO-15 (Most Significant Word of Y(3» Entered Into
External 16 Bit Register
• Cell 2 Selected (ADRO-1 = 2)
• Erase Accumulator of Cell 2 (ERASE = 0)
• SHADD Not Asserted
elK 11
• Cell 2 Contents Added to Zero and Available at Input to
Output Buffer
• Cell 2 Contents Available at SUMO-15
• Cell 3 Selected (ADRO-1 = 3)
• Erase Accumulator of Cell 3 (ERASE = 0)
• Write Y(3) Into Output FIFO (Optional)
• SHADD Not Asserted
elK 12
• External 8 Bit Register Clock Asserted. lower 8 Bits of
SUMO-15 (least Significant Byte of Y(4» Entered Into
External 8 Bit Register
• Cell 2 Contents Entered Into Output Buffer
• Cell 3 Contents Added to Zero and Available at Input to
Output Buffer
• SHADD Asserted
elK 13
• Shift Cell 2 Contents Down 8 Bits and Add to Contents of
Cell 3 (Output Buffer). This 16 Bit Value Becomes Available at SUMO-15
• SHADD Not Asserted
elK 14
• External 16 Bit Register Clock Asserted. All 16 Bits of
SUMO-15 (Most Significant Word of Y(4» Entered Into
External 16 Bit Register
• SHADD Not Asserted
This same pattern repeats until the input data is exhausted.
Note that the value stored in the External Register must be
stored elsewhere before the low byte of the next output
value is sequenced.
The performance specifications for the 16x8 filter are listed
below.
• 2 Outputs/10 ClKS = 1 Output/5.0 ClKS
= 200ns/Output (25.6MHz Device)
= 5MHz Throughput (25.6MHz Device)
The results for the 16x8 design used in this implementation
can be extended to the general case. let:
l
Number of taps
Fs = Sample rate (MHz)
N2 = Number of 2 cell groups
R = Maximum clock rate of DF (20, 25.6, or 30MHz)
(R>Fs)
=
Then:
9-22
Fs = (N2 x R)/(2l+2(N2-1»
N2 = 2Fs (l-1)/R-2Fs )
Harris Semiconductor
No. AN9205
Harris Digital Signal Processing
January 1994
TIMING RELATIONSHIPS FOR HSP45240
Author: Mike Petrowski
The timing diagram in Figure 1 shows the timing relationship
between the various output signals of the HSP45240 when
the sequence generator is programmed for One-Shot Mode
with Restart (see Sequence Generator Section of
Datasheet). In this example. the HSP45240 is configured to
generate a sequence consisting of two address blocks. Each
block is 6 addresses long. and the end of a block is denoted
by the assertion of BLOCKDONE#. As the final address in
the second block is generated. both DONE# and BLOCKDONE# are asserted to signal the end of the address
sequence. On the next clock. a new address sequence is
started (see assertion of ADDVAL#) because the Sequencer
was configured to restart. In this mode the STARTOUT# signal is asserted prior to the end of the address sequence for
the synchronization of multiple HSP45240's.
the final address in the second block is generated, both
DONE# and BLOCKDONE# are asserted and addressing is
halted.
eLK
:
:
~~~--~~~~l-}r~~~~~~~~~~~~
r.
r
DONE.
~~~~~
UJj
~r+-+-+-+4~
START
oun
-~~HUr.~~Hr~~LH
g6~~~--+-+-~-!f
4
~
FIGURE 2. SIGNAL RELATIONSHIPS FOR ONE-SHOT MODE
WITHOUT RESTART
The timing diagram in Figure 3 shows the timing relationship
between the various output signals of the HSP45240 when
the sequence generator is internally started by writing the
Sequencer "STARr' address (see Table 1 of Datasheet).
The output signals are shown with respect to the rising edge
of WR# responsible for the internal START. The address
generation parameters are as above.
NOTE: Asserting STARTIN# after an addressing sequence has
been started will cause the sequencer to restart from the beginning of the sequence.
: :
~~D.-~~~~~~~~~
FIGURE 1. SIGNAL RELATIONSHIPS FOR ONE-SHOT MODE
WITH RESTART
i
~ !
rj
g6~~~
DONE.
The timing diagram in Figure 2 shows the timing relationship
between the various output signals of the HSP45240 when
the sequence generator is programmed for One-Shot Mode
without Restart (see Sequence Generator Section of
Datasheet). As in the above example, the HSP45240 is
configured to generate a sequence consisting of two
address blocks. Each block is 6 addresses long, and the end
of a block is denoted by the assertion of BLOCKDONE#. As
i
i
Jr+-+-+-+-i
OUT~23--~~~~~~~~~~
COPYright © Harris Corporation 1994
9-23
:
:
:
:
SOTAU~
TII ,:,.,:·:.·.
•••
FIGURE
a
:
:
:
:
:
:
:
:
:
:
:
:
:
IIIIIIIIIII~
"""";;;;
: : : : : : : : : : : :
SIGNAL RELATIONSHIPS FOR INTERNALLY
GENERATED START
Application Note 9205
DLYBLK Operation
STARTIN# Operation
Address generation can be halted by assertion of DLYBLK
prior to the completion of an address block (Figure 4 & 5).
Addressing will resume once DLYBLK is de-asserted. Since
there is a pipeline delay between the assertion of DLYBLK at
the pin and when it is internally active, DLYBLK must be
asserted prior to the end of an address block. The pipeline
delay associated with DLYBLK differs for halting address
generation in mid-sequence and halting address generation
after the final address block of a sequence.
The STARTIN# pin has two functions: first, it downloads the
configuration data in the processor interface into the register
bank that controls the operation of the part; second, it starts
the address sequence using the updated configuration.
When STARTIN# is deasserted, the part continues on with
the new sequence. Note that there are four stages of pipeline delay between the sequence generator and the output of
the part; all of the output Signals will continue on using the
original sequence for those four clock cycles.
For halting address generation in mid-sequence, DLYBLK
must be asserted 3 clocks prior to the end of the addressing
block as shown in Figure 4. In this example, DLYBLK is
asserted for one clock cycle which delays the generation of
the next address block by one clock. If addressing has been
halted in mid-sequence, addressing will resume 4 clocks
after de-asserting DLYBLK. Note: BLOCKDONE# will be
asserted and OUTO-23 will be held until addressing
resumes.
After the assertion of STARTIN#. the first value in the
sequence appears on the output after four pipeline delays.
The part will remain in this state for the remainder of the time
that STARTIN# is low, and for four clocks after STARTIN#
returns high. This is shown in Figure 6, note that the old
sequence ends at clock 3; the first address of the new
sequence goes from clock 4 to clock 12; the second address
of the new sequence appears on clock 13.
BLOCK
DONE#
-+-+-+-+-++++..,
gl:~ -+-+-;...-;...-1
OUTV-V-~~~~~~~~~~~~~~~~~
o-23n-~~~~~~~~~~~~~~~~~~
FIGURE 4. SIGNAL RELATIONSHIPS FOR A ONE CYCLE
BLOCK DELAY IN MID-SEQUENCE
Asserting STARTIN# in the middle of a sequence demonstrates the sequence restart function as described above.
The internal count of the HSP45240 returns to the starting
point (the value in the Start Address Register - not the Current Block Start Address Register) on the first rising edge of
ClK that STARTIN# is low. The first address of the
sequence is output four clocks after the assertion of STARTIN#. The Sequencer goes to the second address in the
sequence when STARTIN# goes away; this address appears
on the output pins four clocks later. Sequencing continues
based on the updated configuration. In Figure 7, the new
sequence is started on clock 1; the old sequence will continue unaffected until clock 4, and the first address of the
new sequence becomes valid on the outputs during clock 5.
For halting address generation after the final block of
addresses in a sequence, DLYBLK must be asserted 4
clocks prior to the end of the addressing block as shown in
Figure 5. In this example, DLYBLK is asserted for one clock
cycle which delays the start of a new address sequence by
one clock. The part is assumed to be configured for
One-Shot Mode with Restart. Addressing will resume 5
clocks after de-asserting DLYBLK. Note: BLOCKDONE#
and DONE# will be asserted and OUTO-23 will be held until
addressing resumes. Also, STARTOUT# will be asserted
one clock after the assertion of DlYBLK.
~
0
~ 1 ~ 2 ~ 3~ 4~ 5~ 6~
7
~ 8 ~ 9 ~10~ 11~ 12~13~14i15~16i17i
FIGURE 6. INPUT, OUTPUT SIGNALS WHEN STARTIN# IS
LONGER THAN ONE CLOCK CYCLE.
ClK
BLOCK -+-+-+-+-+-+-+-+-i
DONE.
DONE. --;.-;.-;.-;.-+-+-+-+-;
DlYBlK
OUT;:~~~~~~~~~~~~~~;t;t=t=i
o-23":HH~~::t'1:=+~=+~=+=+=+=+::+=+=+:::f
l.!
STAR,-
oun
:!~
__
4
r
:
DONE.--~~~~-t-t-+-+~~1-1-i-+-~~r-t
BLOCK
DONE.
ADDVAl.
i
--t-HHH--i\' . .
1.\.JJlrt-.l+-+-+-+-+-+-t-HHH-
+-+-+-:---iH.....f
FIGURE 5. SIGNAL RELATIONSHIPS FOR A ONE CYCLE
BLOCK DELAY AFTER FINAL BLOCK IN AN
ADDRESSING SEQUENCE
9-24
FIGURE 7. USING STARTIN# TO RESTART SEQUENCE DURING OPERATION
Harris Semiconductor
.=
=
E
---====
- - -- --=---
.=.
-==
-=-- -- -----=--= =-=-
-=
---
= :====
No. AN9102
-=
Harris Digital Signal Processing
January 1994
NOISE ASPECTS OF APPLYING
ADVANCED CMOS SEMICONDUCTORS
By: R. Kenneth Keenan, Ph.D. and David F. Bennett
Introduction and Summary
This report is about noise aspects of high-speed logic, with a
focus on Advanced CMOS semiconductor applications. The
present report pertains to suppression of ringing for both
short and long traces, with experimental evidence provided
for long traces.
Although termination and decoupling techniques cited here
minimize ringing for all semiconductor technologies (ACt
ACT, LSTTL, HCMOS, AS, etc.), external resistive termination is usually not required for slower semiconductor technologies. Decoupling is an important aspect of design for all
sem iconductor technologies.
The preferred termination technique is a resistor, RT' equal
in value to the trace's characteristic impedance, Zo. in series
with a trace at the driving end of that trace. For ACt ACT,
series termination results in a modest (1 ns to 3ns) increase
in propagation and transition times. The increase in transition times incurred with series termination helps to minimize
interference generation.
The length of traces with distributed loading to which series
termination can be applied is limited by the increased transition times at intermediate points along those traces.
For long traces with distributed loading, AC shunt termination-a resistor in series with a small-value capacitor-is used
from a trace to ground at the receiving end of a trace. The
value of the capacitor depends on clock frequency, but it is
typically 50pF to 200pF. Larger values result in improved
pulse fidelity at the expense of increased power dissipation
in the terminating resistor. At the expense of a capacitor, AC
shunt termination consumes much less power than purely
resistive shunt termination. AC shunt termination does not
appear to materially effect propagation and transition times,
except insofar as it removes the ringing contributing to
shorter transition and propagation times.
Series Termination with a Single Receiver
Resistive Termination
Figure 1 illustrates the waveforms at the receiver for the
case of no termination and for the case where the line is terminated at the driver end of the line. The termination resistor
is 800, approximately equal to the 780 characteristic impedance of the line on the board. In this and all succeeding Figures, the line is 12 inches long.
[>---/[>
80n
Ch. I
Ch. 2
Tl ... ebase
•
•
•
2.080
2.000
,e.0
yolt./dly
yolt./dly
ns/d1v
orr •• t
•
2.508
Off •• t
Deley
•
•
2.500
0.0f/1f/1f/1f/1
/
volts
Yolta
•
FIGURE 1. UNTERMINATED AND TERMINATED (RT "" Zo) LINES
This work was supported by Harris Semiconductor (Harris) and The Keenan Corporation (TKC). The authors thank the external reviewers,
Mr. Richard E. Funk, Manager, Applications Engineering, Harris Semiconductor, and Dr. Leonard Rosi, EMC Engineer, of Hewlelt-Packard's
Corvallis Workstation Operation, for their helpful comments.
Copyright Notice: Copyright 1989, TKC. Reprinted by Harris Semiconductor, April 1989, with permission of TKC.
9-25
Application Note 9102
Zero and five-volt reference lines are shown in each of the
above oscillograms. It is clear from Figure 1 that termination
assists In reducing both the undershoot for the low-to-high
transition and the overshoot for the high-to-Iow transition.
The noise immunity limits for CMOS are given in Table 1.
TABLE 1. NOISE IMMUNITIES AND MARGINS
D.C. SPECIFICATION
VOLTAGE LEVEL
(V)
Maximum Low-Level InputVolfage (Max VIL)
0.8
Minimum High-Level Input Voltage (Min VIH)
2.0
Maximum ,Low-Level Output
Voltage (Max VOL)
0.4
Minimum High-Level Output
Voltage (Min VOH)
2.4
Low-Level Noise Margin (VNML =VIL - VoLl
0.4
High-Level Noise Margin
(VNMH =VOH - VIH)
0.4
For the unterminated line in Figure 1, the maximum V,L 0.8V
is breached . Therefore, CMOS gates driven with the
unterminated-line (upper) waveform in Figure 1 can
mistake the "bump" between t ", 20ns and t ", 30ns for a
"high". Thus, for the unterminated-line waveform, CMOS
gates are subject to logic errors. The terminated line rings
less and provides a signal which is well within the noise
immunity limits for AC/ACT.
The relative sensitivity of the value of termination resistor
was assesed, Figure 2 illustrates experimental results.
From Figure 2, the pulse waveform is marginally improved
for termination resistance greater than the characteristic
impedance, but it becomes more unterminated-like when a
terminating resistance less than the characteristic
impedance is used.
Table 1 summarizes the effects of terminating resistance on
transition times and propagation delays. The propagation
delay of the line, 1.8ns, has been subtracted from the
experimentally-measured propagation delay in the data in
Table 1. The propagation delay was measured as illustrated
in Figure 3.
I
i'
!'
~
-50.000
Ch. I
Ch. 2
r lMeba!le
...
s
2.000 volt:!/div
2.000 volh/dlv
10.0 n!J/div
/
30A
/
130A
/
___ I 50.000
_ L ns_--'
0.00000
•
BOA
Offset
Off !!!Ie t
-
Delay
2.500 volts
2.500 volts
0.00000 •
FIGURE 2. SENSITIVITY OF PULSE TO TERMINATING RESISTANCE
R
T
F
"I
1 . 8 ns
TRANSITION TIMES, ~
SPECTRA
'"
FIGURE 3. MEASUREMENTS
9-26
Application Note 9102
Figure 4 illustrates the effects of AC shunt termination for
two different values of capacitors.
TABLE 2. SUMMARY OF TRANSITION TIMES AND
PROPAGATION DELAYS
TRANSISTION
TIMES (ns)
PROPAGATION
DELAYS (ns)
(0)
tr
tf
tpih
tphl
0
4.0
2.6
3.1
5.0
30
4.6
3.6
3.B
6.0
BO(=ZO)
5.4
5.B
4.B
B.O
130
B.4
7.4
5.6
10.6
RT
In designing an AC shunt termination, the value of the
resistor is equal to the characteristic impedance of the
line: RT = ZOo To allow for complete charging and
discharging of the terminating capacitor (C1) during
one-half the clock period: C1 < 1/6Z0fC. Then the power
dissipated in RT is VCC 2 fCC1 (see Table 7). Forthe present
case of fC = 12MHz, and Zo
80n, C1 < 1/6Z0fC =
174pF. At the extreme, where C1-+oo, the power dissipation
approaches that of a resistive terminator: VCC2/2Z0 for a
50% duty cycle clock.
=
Transition times are measured in the conventions 10%/90%
and 90%/10%, and, similarly, propagation delay is
measured between the 50% points of the waveforms.
Termination with a resistor equal to the characteristic
impedance of the line adds 1.7ns to 3.0ns to the
propagation delays and increases the transition times. From
the perspective of the emissions problems discussed in
Section 9.0, an increase in transition times is good.
However, increased propagation delays may be
undesirable from a functional standpoint. With AC/ACT,
some termination resistance must be used to prevent
ringing which could exceed the noise immunity limits.
For the case C 1 = 56pF, the power dissipation in the
terminating resistor is relatively small: 16.8mW. For the
case C1 = 560pF, the power dissipation approaches that of
a resistive terminator: 156mW (the power dissipation in the
driver is approximately 30mW). However, the waveform with
C1 = 560pF is somewhat better than that with C1 = 56pF.
In shunt term ination, one is always trading power
dissipation in the terminating resistor for pulse fidelity.
Table 3 summarizes propagation and transition times for
AC shunt termination.
TABLE 3. PROPAGATION AND TRANSITION TIMES
Shunt Termination with a Single
Receiver
AC shunt termination is a means of approximating a
resistive termination without incurring the power dissipation
of resistive termination. In laptop computers, power drain is
a battery life issue. In computers and other powerlinepowered digital equipment, power drain causes heat
dissipation and implies a diminution in reliability. CMOS,
in spite of its speed, consumes relatively little power while
operating and near zero power while in standby (or high-Z)
states. Therefore, in a total power "budget", it is
important to consider the power dissipation of termination
resistors.
TRANSISTION
TIMES (ns)
TERMINATION
tr
tf
tPih
None
4.0
2.6
3.1
5.0
BOO/56pF
5.0
4.2
4.6
7.2
BOO/560pF
5.B
4.6
4.2
7.0
..
....
.
I ... .
~
,~~
,~"
kC ts:
~j
------
~+
~
t/
-50.000
T I",ebase
..+.+ .....
-~-{-+-+-
1--'
1->-......
,.~
-
......
~.
t,,- t--.
.-
--.
'n.- ------
--
;
.\
.;,.-
--.-. --:....~
J-<-...... f·........ ......j
[>
/
[>
--~.
+++-.. -+-+-+-+
------ ~-
....
lV\ /
.. _.. _..
----- .. ....... - ------V ___
..
,
Cho 1
Ch. 2
~ ~- ~
.......
tphi
AC shunt termination at the sending end (only) was not
tried. However, in the context of distributed loads with both
ends of the bus AC shunt terminated, the driving-end
termination did not improve the waveform.
~~-=I'{;:~r:r;",~y = = =-.=jg;;,
.0J. H~+ ~+~+
PROPAGATION
DELAYS (ns)
...
"""
,,/
.............. ........ .. ...... --
'\
~+
"'~o
...........
~
/
l\Y-
0 -
J
sll~0ii
o" •• t
orr •• t
Delay
[>
,.,,1/ [>
I
56PF
------ L.
0.00000' •
2.000 volts/dlv
2.000 voits/dlv
10.0 ns/dlv
f............
---
[>
0.--;;0-
2.500 volts
2.500 vol ts
'.0000'
•
FIGURE 4. AC SHUNT TERMINATION AT RECEIVER
9-27
,."1/
I
560PF
[>
Application Note 9102
Since computer bus lines may be in the active high state for
relatively long periods of time, the DC blocking capacitor,
Cl (56pF and 560pF in Figure 4), can be of considerable
benefit when driving CMOS logic. However, when driving
bipolar logic, the current required by the inputs of driven
gates can total much more than that required by a
terminating resistor without a DC blocking capacitor. Then,
AC termination offers insignificant advantages over
conventional resistive termination.
Terminations Applicable to Distributed
Loads
The measurements and waveforms cited below were made
at the gate four inches from the driver and at the gate at the
end of the line. The points designated by arrows in the
figure are referred to as the "intermediate gate" and "end
gate" in the measurements to follow. In all cases, the
waveform at the end gate was the worst case with respect
to ringing.
When a load is distributed along a trace, the characteristic
impedance of that trace is modified in accordance with
[2, p. 148[
Zo = Zoo/[l + distributed load capacitance on line/
capacitance of linej'lz
(1)
Description of Board with Simulated Load
The circuit shown in Figure 5 is the simulated load used
along the bus-like structure on the test board. It is patterned
after the equivalent input curcuitry. The inductor was
formed by a small loop of wire.
Vce
Zoo = Characteristic
distributed loading.
impedance
of
line
without
In the case of the test board, the capacitance along the
unloaded line of 0.72pF/in. x 12in. = 8.6pF, and the
distributed load, including that at the last gate, was (4 x 5pF)
+ 7.5pF = 27.5pF. Then, Zo = 80/[1 + 27.5pF/8.6pFj'lz '"
400.
Series Termination
Figure 7 illustrates waveforms along the line for
unterminated lines, with and without distributed loading,
and for the series-terminated line with RT = ZOo It is clear
from a comparison of the top two oscillograms that the
presence of distributed loading-even without terminationtends to smooth the waveforms. At least in part, this is
probably due to the diodes in the simulated loads, which are
also present in CMOS input gates.
5pF
FIGURE 5. SIMULATED CMOS LOAD
The average value of the input capacitance of a CMOS gate
is 7.5pF. That value was not available, so 5pF capacitors
were used. The above load was distributed along one of the
bus traces at points shown in Figure 6. The diodes are
lN914's, high-speed silicon types.
C
f
12 "
~
2"1_ -~ 2" 4"1 2",
FIGURE 6. DISTRIBUTION OF SIMULATED LOADS ALONG
BUS TRACE
Distributed loading increases line propagation delays by
the same factor by which the characteristic impedance is
decreased, which is a factor of approximately two in the
present case. Propagation delay measurements were taken
as indicated in Figure 2, with 2 x 1.8 = 3.6ns subtracted
from the measured propagation delays to provide the
"distributed load" propagation times in Tables 4 and 5.
The problem with using series termination with distributed
loading is that the waveform along the line will tend to
become a three-level waveform [2, p. 53j. This tendency is
clear in the third oscillogram from the top in Figure 7. Thus,
in Table 5 the transition times at the intermediate point on
the line are greater than those at the end of the line given in
Table 4. If the bus was longer, the "kink" at a line voltage of
2.5 volts would be more noticeable. However, in the present
case, transition times are great enough to smooth the
otherwise sharp three-level waveform. In some applications, an increase in transition times may be acceptable,
and the extra component in the form of the capacitor necessary for AC shunt termination-which does not "three-level"
the waveform along the bus-is not necessary. AC shunt
termination is discussed in the next section.
9-28
Application Note 9102
o
/
0.00000
t;0.~00
'Io
I"
I
2
I j"'~hl"'H'
..
2.000
2.000
-
10.0 ns/d! ...
--
5
Offset
Offset
Delay
'Iolh/ttl ...
voth/dl ...
50:000
•
2.500 volta
2' .500 volts
0.00001 II
FIGURE 7. WAVEFORMS FOR DISTRIBUTED LOADING
the terminating resistor when C = 560pF is substantially
greater than when C = 56pF.
TABLE 4. TRANSITION AND PROPAGATION TIMES-END
GATE
TRANSISTION
TIMES (ns)
PROPAGATION
DELAYS (ns)
(0)
tr
tf
tplh
tphi
O(NoDist.
load)
4.0
2.6
3.1
5.0
o(Dis!.
4.4
3.6
4.4
6.4
RT
Table 6 summarizes propagation and transition time data.
As in the preceding section, gate propagation delay
measured delay -3.6ns.
TABLE 6. SUMMARY OF TRANSITION TIMES AND
PROPAGATION DELAYS
load only)
40 (= ZO) +
Dis!. load
4.8
5.2
5.2
RT
7.8
(0)
TRANSISTION
TIMES/nsl
TR
I
PROPAGATION
DELAYS/nsl
TpLH
TF
I
TpHL
40O/56pF
End Gate I
IntGate
40O/560pF
End Gate
Int Gate
I
TABLE 5. TRANSITION TIMES-INTERMEDIATE GATE
RT
(n)
o(Dis!.
TRANSISTION
TIMES (ns)
PROPAGATION
DELAYS (ns)
I
tr
tf
6.6
5.6
Not measured
8.0
7.8
Not measured
tpih
tphi
load only)
40 (= ZO)+
Dist.load
AC Shunt Termination
This termination technique was previously explored in the
context of a single load. For the case of loads distributed
along a single line, the advantage of shunt termination is
that the tendency toward a three-level waveform with series
termination is absent. Figure 8 illustrates the waveforms
obtained with AC shunt termination. As previously
discussed, the corrected (for distributed loading) value of
the characteristic impedance is 400.
The discussion of trading off waveform integrity for power
dissipation also applies here. The power consumed by
6.0
9.0
8.0
8.8
I
6.0
8.3
I
8.3
9.0
I
I
T
4.4
3.3
Not measured
I
I
3.7
8.0
Not measured
As is evident from a comparison of Tables 5 and 6, shunt
termination with a small capacitor (56pF) does not extract
as much propagation delay "penalty" as does series
termination-nor does a 56pF shunt termination cause a
tendency toward a three-level waveform on the bus. With a
560pF capacitor, the waveform is better in the sense that
there is less ringing, but, as indicated earlier, the power
dissipation of the terminating resistor is substantially
increased.
From a comparison of Figures 7 and 8, series termination
appears to suppress ringing better than shunt terminationat least that shunt termination where, in order to reduce
power consumed by termination resistors, the value of the
capacitor is relatively small. Also, the increased transition
times associated with series termination are very desirable
from the standpoint of minimizing both ringing and
ground bounce.
9-29
Application Note 9102
Termination Techniques
Table 7 illustrates termination techniques which can be
used at the receiving end of a trace; CI is the input
capacitance of the driven semiconductor. The first three
techniques require that the characteristic impedance of the
trace structure be well-defined and constant along the trace
run, which is complicated when a trace is to be run on both
interior and exterior layers of a PCB.
Diode termination allows uncontrolled impedance-such as
that obtained on a two-sided board where the trace-toground trace spacing is variable-but requires more
expensive components than other techniques. In effect,
CMOS input circuitry is a mixture of the series and diode
termination techniques shown in Table 7.
In Table 7, the Termination Dissipation has been computed
by assuming a (worst-case) on source resistance. The
power dissipation expressions apply to use of the
terminating networks at either end of the line. For example,
the expression given for the dissipation of a series
termination applies whether the termination is used on the
sending (proper) end of the line or the receiving (improper)
end of the line.
Series termination has been analyzed in some detail. For
use at either the receiving or sending end, maximum clock
frequency is determined by assuming that, after a high-tolow transition, the input capacitor, CI, must discharge to a
voltage below 5% of VCC before the next clock low-to-high
transition. This requires that three ZOCI time constants
occur during one-half of the clock period, which leads to
the clock-frequency limitation shown for series termination
in Table 7.
The relatively large power consumed In termination
resistors can be a problem. AC shunt termination, as
defined In Table 7 and used in Figures 4 and 8, provides a
worthwhile low-power alternative, to be applied at the
receiving end of a trace. In AC shunt termination, pulse
fidelity is traded off for power dissipation: the larger the
value of the DC blocking capacitor, C 1, the better the pulse,
but the higher the power consumption of the terminating
resistor.
In the limit as the value of C1 is made very large, the power
dissipation of the terminating network approaches that of
purely resistive termination. The improved pulse fidelity with
larger values of C1 is apparent from Figure 8. The maximum
value of C1 which still permits adequate charging/
discharging of the shunt termination network over one-half
of the clock cycle is C1 < 1/6fCZO; this inverse clock-frequency limitation is given in the "Max fC" column ofTable 7.
However, for C1 » 1/6fC ZO, the network is slow enough
that full charging never occurs, the network begins to
approach a purely resistive shunt terminator, and clock
frequencies are limited only by the driver.
AC shunt termination should be used whenever the DC
drive capability of the driving device is approached via
heavy TIL loading.
Decoupling CMOS
Clock-related noise on the VCC bus can arise if too
few decoupling capacitors are used [5, p.3.11-11. It
is recommended that all board layouts allow for one
decoupling capacitor per semiconductor package. However, it is sometimes possible to remove some of the
decoupling capacitors after a working prototype is
developed. This is best done experimentally while carefully
monitoring emissions, particularly at frequencies less than
200MHz. At those frequencies, cable radiation dominates
radiated emissions spectra. Assuming good grounding,
cable radiation is an accurate indicator of VCC bus
contamination.
On large (> 50-pin) devices with more than one VCC pin,
use one decoupling capacitor at each VCC pin. In these
cases, then, more than one decoupling capacitor per
semiconductor package is recommended.
Choosing the Value of a Decoupling CapaCitor
A simplified diagram of the equivalent circuit for the output
of a Harris CMOS device is shown in Figure 10. When the
circuit shown transitions from low to high, switch S1
connects to terminal A and current is drawn from the VCC
bus to charge the capacitor. On a high to low tranSition, the
switch connects to B; current is sourced by the capacitor as
it discharges into ground through S1. Note that the switch
is, in the ideal case, a "break before make" circuit, so that
no current is drawn from A to B as S1 changes state - a
common source of current consumption in early CMOS
logiC.
Departures from ideality include the totem-pole effect: for
time intervals which are smaller than the transition time,
both the upper (PMOS) and lower (NMOS) transistors are
partially "on". Then, during both the low-to-high and
high-to-Iow transitions, there is a pulse of current drawn
from the VCC bus. This is in addition to the current pulse
required-and predicted by the model-for the charging of
Cs when making the low-to-high transition. Also, the
internal gates-those which precede the output gate-require
both totem-pole and charging currents (charging currents
for internal gates are much smaller than that required for the
output gate, as the source capacitance associated with
those gates is on the order of tens of femptofarads [1
femptofarad = 10- 15 farad]).
A decoupling capacitor is the VCC bus for the purpose of
supplying current during transitions. The inductance of a
VCC trace or plane precludes those sources from supplying
all of the rapidly-changing current required during a
transition. Between clock pulse transitions, a trace or plane
supplies recharge current to decoupling capacitors.
Recharging can take place over the much longer time of
one-half of the clock period.
A value of 0.11lF will adequately decouple all known
AC/ACT glue logic and VLSI circuits (even heavily
loaded/fanned out), but the use of that relatively large value
should be resisted in order to maintain the highest possible
self-resonant frequency of the decoupling capacitor. Use
0.OO11lF and 0.01IlF, not so much for reduced cost as for
the purpose of increasing the self-resonant frequency of
the decoupling capacitor.
9-30
Application Note 9102
56pF ~
~
~
;:\
-~)-I:\:~
)
1-
_~
/________________
~
56pF
-=E-
560pF
..:r:...
j:
~:"i;;;;;;::;;:;;:;t::-:::-=-=-
------~A--------~----~~-----~
___~C~~~~~--~-_________~
~
:~
/
,
~/-------~~~~===z:=
560pF ~
-~;.~~~--~------------'1.5~0'-~'-------------=:-,.';~Jn0~n~.~
Ch.!
Ch.::
•
..
:2.000
::.'J00
TIMI!Od,e:
•
10.() ns/dlV
volt$/dlV
volt!o/dlV
Delta. V
..
S.~0Ql
Ofhet
..
2.500
volt'
Ofhet
..
::.S~0
lIoit,
1.600
Delay
n,
volh
FIGURE S. WAVEFORMS FOR AC SHUNT TERMINATION
TABLE 7. RECEIVING END TERMINATION TECHNIQUES
TERMINATION
MAXfC
~ c,
--
J
o
5pF
1
6ZOC1
(667MHz*)
TERMINATION
DISSIPATION
Very Low:
p=VCC 2fCC1
PULSE
INTEGRITY
Improves with small
ZO,C1
Transition times
increased.
(3.8mW)
Series (Controlled ZO)
:E:JC1
1 '1
NOTES
Want Low Zo
Driver-Limited
Very High:
VCC 2 (250mW)
2Z0
Good Reflected %
= 4.4Z0C1
rr-4.4Z0C1
Drive current
= VCC=(100mA}
Zo
Shunt (Controlled ZO)
0
R= Zo
c , (100P~ c ,
oT
AC Shunt (Controlled ZO)
1
-6ZOC1
(33.3MHz, see text)
Driver-Limited
:f3
Low to Moderate,
increasing with C1
Best with largest
possible value of
Must use low-ESL
C1 with short leads
P=VCC 2fC C1
(75mW, about same
as device)
C1 =1/6Z0fC
Intergrity improves
withC1
Want Low Zo
Low
Good with highExternal diodes
costly
speed Schotky
diodes or built-in
protection diodes of
some semiconductors
c,
Diode (Uncontrolled ZO)
• Examples are for Zo = 50, C, = 5pF, Vee = 5, fe = 30M Hz, Duty Cycle = 50%
9-31
Application Note 9102
Vee
CMOS circuits. Two-sided boards designed from an RF
standpoint could be used, but the low component density
associated with such boards is inconsistent with most
contemporary system design requirements.
Vee
-I>t
tr>-
R2
The "Best" Termination Technique: Series Resistor at
Driving End
R2
When loads do not require much DC current, as with CMOS
inputs, the preferred termination technique for a single load
and large class of multiple distributed loads is a terminating
resistor at the driving end of the trace. The value of the
terminating resistor, RT, is ideally equal to the characteristic
impedance of the driven trace, ZO, as modified by any
distributed loading. The correction for distributed loading is
given in equation 1.
FIGURE 9. RESISTIVE TERMINATION IS USED IN MOST
STANDARD BUSES
vcc
\
~
_A
Reduction of the value of a series terminating resistor from
RT = Zo leads to decreased propagation and transition
times. However, for even zero-length traces, reduction of
RT eventually leads to ringing. Although the internal diodes
in the input circuitry of Harris CMOS tend to limit ringing,
noise immunity problems can still occur.
~
"*
FIGURE 10. EQUIVALENT CIRCUIT FOR CMOS OUTPUT
The Equivalent Series Inductance (ESL) of a
Decoupling Capacitor
The equivalent series inductance (ESL) of a decoupling
capacitor and the inductance of the leads/planes used to
connect the decoupling capacitor to a semiconductor
package should be as small as economics and manufacturing practicalities permit. This decreases both ringing and
emissions. It is shown in [5, pp. 3.9-7 through 3.9-10] that
maximum attenuation of noise on the power bus occurs at
the self-resonant frequency of the decoupling capacitor. To
have that attenuation occur at frequencies where ringing
and emissions suppression is otherwise difficult (generally
35MHz to 90MHz) using a capacitor value chosen according to the previous section requires ESL's less than 10nH.
Surface-mount ("chip") capacitors on a multilayer board
with both VCC and ground planes are particularly desirable.
The ESL of a decoupling capacitor is at least as
important as Its capacitance. Above the self-resonant
frequency of a decoupling capacitor which provides
filtering; that inductance should be as small as manufacturing techniques and economy permit.
Placement of Decoupling Capacitor on a Board
A decoupling capacitor should always be placed on that
end of the semiconductor package which points toward the
power entry point on a board. One of the purposes of
decoupling is to minimize VCC noise at the power-entry
point, and the filtration implied by a decoupling capacitor
should be between the semiconductor package and the
power entry point.
Conclusions and Recommendations
Use Multilayer Boards
The inductances associated with two-sided boards are
often too large for successful application of high speed
Increasing the value of the terminating resistor beyond Zo
tends to further enhance the smoothness of the pulse but
can lead to undesirable increases in propagation delays.
The resulting increased transition times tend to suppress
emissions.
For driving-end series termination with distributed loading
on lines 12 inches long, transition times at intermediate
loads are doubled relative to those at the end of the bus.
Longer buses lead to even greater increases in transition
times at intermediate bus points. Should this not be
tolerable, the alternative AC shunt termination discussed
below should be used.
An Alternative Termination Technique
In the above case and/or when a resistively-terminated bus
and/or heavy TTL loads are to be driven by CMOS gates,
AC shunt termination should be considered as an
alternative to putely resistive termination.
At least for the driven-end terminated case considered In
this report, AC shunt termination does not appear quite as
effictive as sending-end series termination in suppressing
ringing.
When terminating high-speed traces, SIP resistors and
capacitors should be avoided. The equivalent series
inductance (ESL) is too large in many applications. Discrete
SMD's are preferred to minimize ESL.
Minimize Power Bus Ringing to Minimize Interference
To minimize ringing on the power bus, It is recommended
that CMOS devices which handle high-frequency periodic
signals be carefully decoupled from the power bus. Specific
decoupling recommendations have been provided in this
report.
9-32
Application Note 9102
Bibliography
[1]
R.K. Keenan, FCC Emissions and Power Bus Noise (Second Edition), Pinellas Park, Florida: TKC, February 1988.
[2]
William R. Blood, Jr., MECL System Design Handbook (Fourth Edition, Rev. 1), Phoenix, Arizona: Motorola Inc., 1988.
[3]
RCA/GE/Harris Semiconductor, GE Solid State Data Book (for) RCA Advanced CMOS Logic ICs, Somerville, N.J.: GE
Corporation, 1987.
[4]
J.D. Kraus, Electromagnetics (Third Edition), New York: McGraw Hill, 1984.
[5]
R.K. Keenan, Decoupling and Layout of Digital Printed Circuits, Pinellas Park, Florida: TKC, 1987.
[6]
R.K. Keenan, Digital Design for Interference Specifications, Pinellas Park, Florida: TKC, 1983.
[7]
H.H. Skilling, Electrical Engineering Circuits, New York: Wiley, 1958.
9-33
Harris Semiconductor
No. AN9207
January 1994
Harris Digital Signal Processing
TEMPERATURE CONSIDERATIONS
Author: Clay Olmstead
Junction Temperature
The energy expended by an integrated circuit is dissipated
as heat. In a CMOS system, current (and hence power)
increase proportionally with switching frequency. With the
advent of fast CMOS circuits, the attendant rise in
temperature causes a variety of problems. In some cases,
the current and/or temperature constraints placed on the
device by its operating environment are the limiting factors
on the clock rate. The increased die temperature due to the
switching speed produces a number of secondary effects.
The propagation delay time of a CMOS gate increases,
causing a decline in the overall performance of the system.
In addition, the effects of various failure mechanisms are
accelerated (see Reliability Fundamentals). Depending on
the failure mechanism, the lifetime of the product can be
decreased by a factor of two for every 10°C rise in junction
temperature.
The internal temperature of a semiconductor device is
defined as junction temperature, TJ. Harris products are
designed to operate with a 10 year lifetime under the stated
operating conditions. For parts in ceramic packages, these
include a maximum junction temperature of 17SoC. For
plastic packages, the maximum TJ is 1S0oC - this is to
maintain the integrity of the package, not the device inside.
Note that the 17SoC limit is set according to military
standards; many users in specific industries set this limit
higher or lower, depending on their individual requirements.
Determination Of Junction Temperature
Once the designer has selected an IC and calculated the
clock frequency that meets the needs of the application, the
operating temperature of the die Gunction temperature) must
be calculated to determine whether it exceeds reliability
guidelines. This involves the concept of thermal resistance:
the temperature differential across a body that is dissipating
a given amount of energy. There are two common sets of
reference pOints for thermal resistance: 9JC is the temperature differential between the p-n junction of a semiconductor
device and the outside surface of the package (case); 9JA is
measured from the junction to ambient conditions. Other
reference pOints for measuring thermal resistance are
defined depending on specific requirements.
To calculate whether a device will exceed its maximum junction temperature, the first step is to multiply the clock rate by
the frequency coefficient (given in mA/MHz) for that product.
This is listed in the D.C. Electrical Specifications section of
the data sheet under Iccop The total package power
dissipation is calculated by multiplying that current by the
maximum Vcc. If this figure is less than the Maximum
Package Power Dissipation listed in the data sheet, then the
operating conditions meet Harris specifications. In some
applications, it is necessary to operate the part using a
higher junction temperature (for applications that can absorb
the penalty in expected lifetime) or lower temperature (for
high reliability applications). Users with these requirements
calculate their actual junction temperature using one of the
following equations. Given the maximum ambient
temperature, the proper equation is:
TJ =(9JA X P) + TA
Equation 1
Where:
TJ =Junction Temperature of the Part In °C
9JA =Thermal Resistance from Junction to Ambient In °CIW
P = Iccop x Vcc
TA =Ambient Temperature
The junction temperature for a given case temperature is:
TJ = (9JC X P) + Tc
Equation 2
Where:
TJ = Junction Temperature of the Part In °C
9JC =Thermal Resistance from Junction to Case In °CIW
P = Iccop x Vcc
T c =Case Temperature
Reducing Junction Temperature
If, after going through the above equations, the junction
temperature exceeds the allowable limit, there are several
possible solutions. With some types of parts, such as digital
filters, the user can replace a single part running at a high
data rate with multiple parts, each operating at a reduced
clock rate. Using this method, the junction temperature of
each IC is reduced but the throughput of the entire circuit is
unaffected. In most cases, the optimum solution is to
improve the heat flow out of the package by adding a heat
sink and/or forcing airflow across the package. Moving air
lowers the effective 9JA of the part as shown in Figure 1.
The required value for the effective thermal resistance is
calculated by solving equation 1 for 9JA:
9JA = (TJ - TA) I P
Equation 3
Once the necessary value for 9JA is known, Figure 1 is used
to locate the corresponding air flow for the package of
Copyright © Ham. Corporation 1994
9-34
Application Note 9207
interest. Note that the improvement in thermal impedance is
a function of the airflow measured in linear feet per minute
(Ifm), but fan manufacturers measure airflow in cubic feet per
minute (cfm). Assuming 100% efficiency, Ifm is converted to
cfm by multiplying the required Ifm by the cross sectional
area of the path of moving air. In reality, obstructions in the
airflow cause back pressure, which diminish the fan output to
between 60% and 80% of its free air capacity; divide the 11m
figure derived from Figure 1 by this compensation factor to
obtain the required fan output.
70
60
r'--
,
,
I>8OIC
50
~
~40 ~
J30
20
10
00
8DIP
44 PLCC
"PGA
--
68 PLCC
"POA
84 PLCC
I
I
200
400
600
turer's catalog will specify the performance for their products
using a chart similar to that shown in Figure 2. Starting with
the power dissipated by the device on the x axis, find the
corresponding temperature rise of the package on the y axis.
Add this value to the ambient temperature, TA , to find the
elevated case temperature. Use Equation 2 to find the new
junction temperature.
If a fan is to be used, then the following procedure is
recommended. Use Equation 3 to calculate the required
total thermal resistance.
Solving Equation 4 for 9sA ,
calculate the maximum thermal resistance allowable for the
heat sink. The literature from the maker of the heat sink will
have a chart similar to Figure 3; find eSA on the right axis and
find the air flow that corresponds to that value on the top
axis. (The placement of the axes is to allow Figures 2 and 3
to be combined into one graph.) Convert 11m to cfm and
divide that value by the compensation factor for back pressure mentioned above; use that figure to select a fan.
1.. PGA
100
./
1000
800
AIR FLOW (LFM)
FIGURE 1. TYPICAL RELATIONSHIP BETWEEN
FLOW FOR VARIOUS PACKAGES
9JA
~
AND AIR
./
/
Another viable solution is to use a heat sink, either by itself
(natural convection) or with moving air (forced convection).
There is a wide range of heat sinks available for virtually any
package type. Note, however, that a heat sink is much more
effective when used in combination with a ceramic package.
This is due to the greater thermal efficiency of the ceramic
material: most of the flow of thermal energy is from the die
directly into the package, where the entire surface of the part
acts as a radiating surface to let the heat escape. Some
energy flows from the die through the bond wires and pins
and out through the copper traces in the board, but this
effect is negligible due to the fact that the bond wires are
only 1 mil in diameter and thus their thermal impedance is
relatively high. In a plastic package, the main path for the
heat flow is from the die through the paddle and the plastic
molding compound and on to the outside world. Since plastic is a relatively poor thermal conductor, other paths, such
as the bond wires, take on a greater proportion of the total
heat transfer so that their contribution is no longer negligible.
For this reason, a heat sink mounted to a plastic package
dissipates less heat than Equation 2 would indicate. Harris
recommends the use of a ceramic package for operating
conditions that require a heat sink.
Addition of a heat sink puts two additional elements in path
of thermal transfer: the heat sink and the thermal joint compound that attaches it to the package. The total value for 9JA
is divided into its component parts: the thermal resistance
from the junction to the surface of the package, from the
package to the heat sink, and from the heat sink to ambient:
9JA
=9JC + 9cs + 9SA
Equation 4
Where CS is the thermal resistance from the IC package to
the heat sink, which is controlled by the mounting technique
and thermal joint compound used. 9SA is the thermal
resistance from the heat sink to ambient.
Under natural convection, heat sink dissipation is a function
of the power dissipation of the Chip. The heat sink manufac-
~
7[
1/ ...
1/
5
2
3
4
HEAT DISSIPATED (WATTS)
FIGURE 2. PACKAGE TEMPERATURE INCREASE AS A FUNCTION OF POWER FOR A TYPICAL HEAT SINK
UNDER NATURAL CONVECTION
AIR VELOCITY (FEET PER MINUTE)
o
200
"'
400
600
800
1~6
l:!
:IE~
:lEi!:
"I ~
....
~
-
......
12
ip
LLI-
wz
~!!!
-
8
4
~i
U><
C(I)
a:w
(1)-
:lEa:
I-UI
0%
me
~~
ffim
o i!!
FIGURE 3. THERMAL RESISTANCE VERSUS AIR VELOCITY
FOR TYPICAL HEAT SINK UNDER FORCED CON·
VECTION
For Further Reading
The discussion above outlines the overall method for
calculating the thermal parameters of a circuit. the interested
reader may refer to the following references for further
information.
MIL STD 883 Method 1012.1; JEDEC ENG. Bulletin No. 20,
January 1975; 1992 Semi Std. Vol. 4, Methods G30-86,
G32·86, G42-88, G43-87
9-35
Zu..
c(w
wa:
Z(.)
Q.w
c(1-
Harris Semiconductor
------ ~ - ~
--------
----
~
--
No. TB310
January 1994
-
- -- .=
--
--
=-==
===--==
==
== =--==
--=-- ==
-~~-~
==
Harris Digital Signal Processing
COMMON ABUSES OF THE HSP43220
1. Loads too many coefficients. Only "half' the coefficients
(including center tap) are needed. Loading more or less
coefficients will cause incorrect operation.
11. System board problems are causing incorrect acquisition
of outputs from DDF. i.e. in a multiplexed bus structure
there is bus contention.
2. Improper reset of part. Both clocks must be active during
reset. Both start pins high during reset and remain high
until programming complete.
12. Customer does not realize data is held at outputs until
next DATA_ROY.
3. Starting part too soon. Under software control, the start
pins may float momentarily before programming is complete. Once started, any writes of coefficients are ignored.
13. Customer does not relax passband attenuation as much
as possible and valuable taps are wasted.
Debug/deas
4. In DECIMATE, customer tries to bypass the HDF by setting Hdec = 1 and Stages = 1. The correct settings are
HDec = 1 and Stages = o.
5. Customer is violating the CK_IN duty cycle requirements
when HDF is bypassed. See A.C. Specifications in data
sheet.
6. Customer confuses even/odd symmetry bit with even/odd
1. Bypass the FIR or HDF sections individually or together. If
the clocks are tied together the HDF section can be pseudo bypassed by selling HDRATE as usual but set
GROWTH = 50 and STAGES = O. The HDF will output every Nth input sample. This will verify correct wiring of the
DATA_IN bus and some of the C_BUS bits.
2. Read out coefficients as per memo.
length filters.
7. Customer tries to run HDF bypassed with CK....IN = FIR_CK.
8. Customer thinks that taking the start pin inactive will stop
the part. Only reset can stop the HDF section once it has
been started.
3. Try writing F_DIS =0 then F_DIS = 1 before loading coefficients. If this helps then poor reset procedure or floating
start pins are likely.
4. Input a DC value, it should pass through a low pass filter.
5. Are DATA_ROY's at correct frequency? (CK_IN/(Hdec+Fdec).
9. Has intermittent or poor results from cheap socket or poor
part insertion.
10. General- input rise/falltime to slow (>10ns), input setup/
hold violations, noise.
COPYright © Harns Corporation 1993
9-36
Harris Semiconductor
-----
- --------- - - ---- -------- ----- ------- -- --------- ------ --- -- - - ---------------- -------~-
-
-
---~-------
----~-----
No. TB311
Harris Digital Signal Processing
January 1994
HSP43220 - DESIGN OF FILTERS WITH OUTPUT RATES
<2(Passband + Transition)
One of the design rule checks in DECI.MATE is that the output rate must be greater than 2 times the sum of passband +
transition band. For the informed user, violation of this rule is
a valid design choice. Suppression of this rule check in
DECI.MATE is not possible, but design of such a filter using
DECI.MATE is possible.
The general solution is to use DEC I. MATE to design a filter
with an output rate that is twice the desired rate, or a integer
multiple of the desired rate that is >2(pass + trans). Outside
of the Design Module the FIR decimation rate is increase by
the factor needed to achieve the desired output rate. The
new filter response is obtained graphically.
Consider a filter with a passband of 70KHz and a transition
band of 60KHz. The desired output rate is 200KHz.
DECI.MATE requires an output rate of >260KHz, an output
rate of 400KHz is chosen (see Figure 1 below and FILTER 1
page 2).
By increasing the FIR decimation by a factor of 2 the folding
point (Fsf2) is moved and the desired output rate is Obtained.
The filter response can be generated graphically. The aliasing component is represented by the dotted line (see Figure
2 below).
o~
Notice in FILTER 1 the stopband attenuation was limited to
40dB (FIR_CK=CK_IN). Because the FIR decimation was
Increased from 5 to 10, there are more taps available with
FIR_CK=20MHz. Using equation 2.0 from the 43220 data
sheet, we see how many taps are available.
HTaps = (
2x20(10) 10
20
10-4) = 172
We can therefore use FILTER 2 which uses 151 taps and
has 96dB stopband. The part will of course be programmed
for FIR decimation rate of 10 and an FIR_CK of 20MHz is
used.
To correctly simulate or generate PROM files for the "new filter" the ·.DAR file must be edited. The corrected value for
FDRATE on line 1 column 4 is entered. The correct output
rate and FIR_CK rate are entered on the next to the last and
the last line of the ·.DAR file.
The above procedure works for standard or Precomp FIR.
Remember the maximum FIR decimation rate is 16.
_ _ _""'
o~
dB
_ _ _""'
dB
-40
70KHz
130KHz
200KHz
Fsf2
200KHz
Fsf2
FIGURE 1
FIGURE 2
Copyright @ Harris Corporation 1993
9-37
Tech Brief 311
DESIGN MODULE
SIMULATOR MODULE
PROM MODULE
HSP43220 DDF FILTER SPECIFICATION
DESIGN MODULE
SIMULATOR MODULE
PROM MODULE
HSP43220 DDF FILTER SPECIFICATION
D
E
C
I
Filter File
filter2.DDF
Input Sample Rate:
20 MHz
output Rate
400 kHz
Passband
70 kHz
Transition Band
60 kHz
Passband Atten
0.1 dB
Stopband Atten
96 dB
FIR Type
Design Mode
Generate Report
Display Response
Save Freq Responses
save FIR Response
AUTO
YES
LOG
NO
NO
STANDARD
M
A
T
HOF Order
HOF Decimation
HDF Scale Factor
4
10
0.61035
E
FIR
FIR
FIR
FIR
Input Rate
Clock (min)
Order
Decimation
FIGURE 4. FILTER DESIGN DISREGARDING FIR CLOCK (MIN).
9-38
2 MHz
40 MHz
151
5
Harris Semiconductor
--------------------------===--====--==
-----= =
----
------
===-~.:=..--==
No. TB308
January 1994
Harris Digital Signal Processing
HSP43220
DECI.MATE DESIGN RULE CHECKS
In order to maximize effectiveness of DECI.MATE software
there are two design rule checks that need some in depth
discussion. Once these crosschecks are understood the
usefulness of DECI.MATE and the DDF will improve
because filters that were previously thought unrealizable are
in fact achievable. Consider the following normalized HDF
response (to first nUll).
In Figure 1 the dotted line represents aliasing. The point
defined by stopband attenuation (SOdB) and the sum of the
passband and transition band frequencies, must not cross
the dotted line. Sometimes in MANUAL design mode you will
come upon a filter in which you can vary either the transitionband or passband frequencies or attenuation by just a few
Hz or a few dB, and find the filter jumps from unrealizable
due to many taps to a viable filter that only needs a few taps.
This may be due to crossing the aliasing curve. This in
effect, renders the HDF ineffective and DECI.MATE is trying
to accomplish everything in the FIR. You may also get the
error message "HDF unrealizable".
large percentage of the output rate, if the passband attenuation is very small, if most of the decimation is being done in
the HDF (which brings the first null of the HDF response in
close to the passband region). The number of stages in the
HDF also determines the rolloff of the HDF response. This
design rule check is done with no knowledge of the type of
FIR being used, STANDARD, IMPORTED, or PRECOMP.
Therefore switching to a PRECOMP, or IMPORTED FIR will
not alleviate a violation of this rule. The PRECOMP FIR can
in fact reduce the HDF rolloff effect when the rolloff is within
the limits stated above.
!
or------__
l!:
E
z
~
-
DESIRED RESPONS
PASSBAND-------- __
1
:::Il
HDF FREQ RESPONSE
FIGURE 2.
o
--t--__ PASSBAND + TRANSITION BAND
It is important the user understand which rule is being violated because the first one is hard and fast, must not be violated. The second is correctable with additional work
(manual design of FIR on other software). It is of course possible that both rules are being broken. There are two simple
tests that can be done to identify what the problem is. If the
difficulty is with HDF rolloff in the passband (rule 2), then
relaxing the passband attenuation will allow the software to
generate a filter.
50
If the problem is intrusion of stopband attenuation past the
dotted line (rule 1), then changing the passband attenuation
will not solve anything. Try reducing the stopband attenuation, a little, then a lot, if this results in a filter design then the
problem is ru Ie 1.
iii"
e.w
o
i:
z
~
HDF FREQ RESPONSE
0.5
Solutions
FIGURE 1.
Violation of the second rule exhibits similar symptoms.
Figure 2 illustrates the design rule check that the HDF rolloff
should not violate the passband attenuation spec. This condition can occur in a variety of ways, if the passband is a
If DECI.MATE was in design mode MANUAL when the problem occurred then the user can adjust the design parameters (input rate, output rate, passband, transition band,
passband attenuation, stopband), or the HDF filter parameters to achieve a filter. For problems with rule 1 try any of the
following: higher input rate, narrower passband, less stop-
COPYright © Harns Corporation 1993
9-39
Tech Brief 308
band attenuation, less HDF decimation, more HDF stages.
For problems with rule 2 try any of the following: higher input
rate, higher output rate, narrower passband, looser passband attenuation, less HDF decimation, fewer HDF stages.
In general, if DECI.MATE was in design mode AUTO when
the problem occurred, then going to manual design mode
and playing with HDF stages, or HDF decimation will not
produce any better results (with the one exception noted
below as "Special Case"). The user then must decide if the
system can tolerate the relaxed design parameters (input
rate, output rate, passband, transition band, passband attenuation, stopband attenuation) needed to achieve a realizable
filter. If not, the user will need to perform a manual design of
the HDF and FIR filter parameters.
Special Case
For those users who have the option of low system decimation rates there are some alternatives. For those with system
decimation rates of less than 10, trying varying combinations
of HDF decimation and HDF stages may prove worth while.
Also, for those that can have system decimation of 16 or less,
bypassing the HDF (setting HDF decimation to 1 and HDF
stages to 0) and using only the FIR may be beneficial.
9-40
Harris Semiconductor
------
---------------- -- -- --- ----==
=-====--=
===
--- -- -- - ---~
No. TB309
January 1994
--==
==
==
Harris Digital Signal Processing
NOTES ON USING THE HSP43220
Operation And Programming
Typical operation of the part using DECI.MATE software is
as follows. RESET# is held low long enough to satisfy the
specification of 4 clocks for the slowest clock. Coming out of
reset both start inputs must be high. After waiting the specified reset recovery time the registers are then loaded.
H_Register1: H_DRATE register will accept values from 0 to
1023. H_BYP is set as desired. F_CLA is typically set to a
zero, F_DIS is set to a zero. H_Register2: H_STAGES is set
as desired, a six or seven may be entered and will be interpreted as a five. H_GROWTH is entered as specified in the
data sheet or DECI.MATE with acceptable values from 0 to
63, with values above 50, the most significant bits of the
input data will be dropped. F_Register: F_TAPS will accept
values from 2 to 511. DECI.MATE always generates odd tap
filters, therefore the value N to be entered will typically be
even. F_DRATE, enter value between 0 and 15 as desired.
F_ESYM, as with most filter design software, DECI.MATE
always generates even symmetric filters, enter a one.
F_BYP, enter as desired. F_OAD, typically set to a zero,
used only for non-symmetric filters and for verifying filter
coefficients. FC_Register, for a the value N loaded in the
F_TAPS register there will be (N/2)+ 1 coefficients to be
entered for odd length filters and N/2 coefficients for even
length filters. It takes two writes to load each coefficient.
Internally the number of coefficients loaded is recorded and
used to determine the length of the filter, NOT F_TAPS.
F_TAPS is used to offset a read pointer in the data RAM and
to determine if an odd or even number of taps is being done
to properly handle the center tap.
With programming of the HSP43220, the part must be
started as described in the data sheet. If STARTIN# is used,
it will be the third rising edge of CK_IN (from STARTIN#
active) that the DATA_IN pins will start accepting data. If
ASTARTIN# is used it will be the fifth rising edge of CK_IN.
If at any time RESET# goes active, or glitches low, the above
procedure must be repeated (except for reloading coefficients). Also see reprogramming.
Implementing Non-symmetric Filters
The HSP43220 can implement up to a 256 tap non-symmetric filter. Correct programming procedures are as follows. By
definition the number of coefficients loaded is equal to the
number of taps (N). The F_TAPS is set equal to 2N-1, and
F_OAD and F_SYM are set to a one. The remaining registers
are loaded normally.
In many cases the source of information to be fed into the
DATA_IN pins will be less than 16 bits wide. The recommended configuration is to connect the input bus to the most
significant bits of DATA_IN and to tie unused DATA_IN pins
to GND. In some systems there will be available a 16 bit bus
to connect to the DATA_IN pins but the full range of the bus
is not being used. For example the upper 4 bits are always
sign bits. This can be adjusted for in software by setting the
growth for three more than normal. Even if the HDF is to be
bypassed this can be accomplished by manually putting the
HDF in bypass. This is done by setting H_STAGES and
H_DRATE to O. For the case described above, H_GROWTH
would be set to 50+3, or 53. This pushes the 3 extra sign bits
off the top of the data shifter.
Output Format
As stated on page 4-5 of the DECI.MATE manual, the FIR
coefficients are computed using the Parks-McClellan
(Remez) method and then scaled by the inverse of the HDF
scale factor as well as an additional factor which accounts
for the maximal ripple gain of the derived FIR. As a resutt,
the output format is as follows. DATA_OUT bits 0-15 are the
most significant bits. If OUT_SELH is held high, then
DATA_OUT bits 16-23 are simply sign extension, if held low
they are the LSB extension, for a total of 24 bits of resolution.
For those that wish more bits of resolution the sign extension
bits can be used. This may be accomplished through the
users own software or the coefficients from DECI.MATE
may be scaled. This is accomplished by determining the
magnitude of the largest coefficient, and then multiplying all
coefficients by the factor 0.999999/mag. The coefficients
must then be quantized to 20 bits. This results in the magnitude of the largest coefficient being about 0.999999, the
largest representable value. This procedure also allows the
realization of filters of greater than 96dB attenuation since it
reduces quantization effects. The new pOSition of the deci-
COPYright © Harris Corporation 1993
9-41
Tech Brief 309
mal point in the output will be moved into the sign extension
bits with its exact position being dependent on the coefficients.
Bypass Modes Of The HDF And FIR
When the H BYP bit is set, H_Register2 bits are affected as
follows. H GROWTH is set to 50, H_STAGES is set to zero.
The clock divider is disabled so CK_DEC=CK_IN. The
H_Register1 value H_DRATE is not altered by setting the
H_BYP bit. H_Register2 must be reloaded after H_BYP has
been returned to a zero.
With H BYP set to a one, the feedback paths in the integrators and the holding registers in the comb are zeroed. The 16
bits of chip input data pass through the HDF section unaltered. As always, the first data sample out of the HDF (after
reset/startup) is a zero due to resetting of the data paths.
Because the FIR section has several operations to complete
between rising edges of CK_DEC it is necessary for FIR_CK
to be faster than CKJN as described in the data sheet. The
duty cycle of CK_IN must meet the conditions described
Tech Brief TB312. DECIMATE can be used to determine the
necessary frequency of FIR_CK or equation 1.0 in the data
sheet can be solved for the case of HDF in bypass by setting
Hdec=1.
When the F BYP bit is set the FIR filter is configured as a 3
tap, even symmetric filter, no decimation with one input to
the pre-adder set to zero (same side as if F_OAD was set).
The output of the coefficient ram is forced to 00004H to aid
in positioning the result in the accumulator. The output multiplexes are set by the F_BYP bit to output data from the bottom of the accumulator. For a 3 tap filter there are two
multiply/accumulate (MAC) cycles. The data flow is as follows. A new piece of data becomes available at the HDF output as signaled by a rising edge of CK_DEC. The FIR is
signaled and the data is written into the data ram. The first
MAC cycle begins. From the data ram the new data and
some old data are read. The new data is added to zero in the
pre-adder, then multiplied by the coefficient, and then accumulated with a zero (because start of new FIR cycle). The
second MAC cycle starts one FIR_CK cycle after the first.
Two old pieces of data are read from ram. But two zeros are
input to the pre-adder because of zeroing the other side of
the pre-adder at the center of odd length tap filters. The
resulting zero is multiplied by the coefficient and accumulated. The accumulator results are sent to the output pins
along with a DATA_RDY.
nous operation of multiple DDFs is maintained. By continuing to load the data ram a transient response is avoided
when the FIR section is restarted. Writing the F_DIS bit also
resets the coefficient ram address pointer to zero (to allow
for reloading coefficients) and enables writing of the coefficient ram (writing is disabled when FIR section is enabled).
Once the bit is set and at least two riSing edges of FIR_CK
have occurred, the user may then reconfigure the FIR section as desired. The FIR section can be re-enabled either by
writing F_DIS to a zero or by generating a high to low transition on either of the start inputs, which automatically clears
F_DIS.
For those users that wish to clear the HDF data paths before
bringing in a new signal, or for those that wish to change
HDF programming and have multiple DDFs running synchronously, activating the RESET# input is recommended.
Re-programming the DDF and restarting will be necessary.
The coefficient ram is not corrupted by reset and will not
need to be reloaded unless new coefficients are needed. It is
also possible to reconfigure the HDF without losing synchronization between DDFs if CK_IN is stopped (high or low)
during writing of the registers. For single chip applications or
where synchronization is not a concern, the HDF registers
can be written on the fly. This will result in a transient
response and changing HDF registers at regular intervals in
an attempt to achieve fractional decimation rates with the
chip is not recommended.
Internal Decimation
The total deCimation in the DDF, also called the system decimation, is equal to the product of Hdec and Fdec. The output
rate of the DDF will be equal to CK_IN divided by system
decimation, regardless of FIR_CK speed. The time from the
start of the DDF to the first DATA_RDY may not be the same
as time between DATA_RDYs. To the user the FIR decimation appears at the FIR output. That means the output of the
DDF is equivalent to using a standard FIR filter and only
looking at every Nth output for FIR decimation of N.
In the HDF the counter used for decimation is initialized to
Hdec. The first CK_DEC (internal to chip) will occur about
Hdec CK_INs after the part is started. The FIR decimation
counter is initialized to zero and the first CK_DEC will always
cause an FIR cycle which generates a DATA_RDY about
tapsl2 FIR_CKs later. Thus the time delay from start of the
DDF to the first DATA_RDY is about CK_IN period times
Hdec plus FIR_CK period times taps/2.
Reprogramming
Transient Response
After initial startup of the HSP43220 the FIR section can be
reprogrammed using the F_DIS bit of H_Register1. When
writing H_Register1 be sure to maintain the same values in
bits 0-10 H DRATE and H BYP. When the F_DIS bit is written the FIR-section will te-;:minate a FIR cycle if one is in
progress, no DATA_RDY is issued. The FIR section is disabled from performing multiply/accumulate cycles. The
FIR CK must continue to run. The HDF section continues to
ope~ate and its output continues to be written into the data
ram. By letting the HDF section continue to run the synchro-
After reset, after changing the source of input data, or after
re-programming the HDF, the output of the DDF will have a
transient response until the data ram is sufficiently full of
"valid" data. There is no transient response when only the
FIR is reprogrammed using the FIR disable bit in the control
register. It is impossible to predict exactly when the transient
is complete as the answer depends on the FIR filter coefficients as well as new data values relative to old data values
in both the FIR and HDF.
9-42
Tech Brief 309
First the integrator stage(s) must be flushed of old data
(except when reset is used). The number of stages and
growth will influence this. But in general the flushing of the
integrator stages is small compared to the remainder of the
chip. For N stages it will take N CK_DEC cycles to flush all
the holding registers in the comb. The number of taps determines how many locations of the data ram needs to be written with new data. The equation for the number of input
samples needed to complete the transient response is:
number of input samples = Hdec(taps + N)
The number of output samples that are part of the transient
response is:
number of output samples
=taps/Fdec + N/Fdec
Because the center coefficients are usually much larger than
outer coefficients the transient response is done before all
the ram locations are filled. In some cases in half the time
described above.
The simulator in DECI.MATE assumes all unwritten ram
locations are zero and may not necessarily reflect the startup transient of the DDF. This can be overcome by making
sure leading zeros are input ahead of the signal for both the
simulator and the chip. For the case of the data input changing (one signal followed by another) the simulator will match
the DDFs transient response. You cannot simulate reprogramming the DDF.
is 100% immune to metastable conditions it was needed to
specify the FIR_CK and CK_IN inputs as synchronous
inputs. Metastable condition refers to when the flop output
oscillates due to the data and clock changing simultaneously.
For the user that finds it very inconvenient to use synchronous clocks. or for one that does not wish to use clocks that
are integer multiples (which is by definition not synchronous). the use of a local synchronizer can be of benefit. This
option puts the risks and control of metastability at the board
level under user control. One example of this might be a user
that has designed the needed filter in DECI.MATE and the
required FIR_CK is 35Mhz with a CK_IN rate of 5Mhz.
Through the use of equation 1.0 in the data sheet the minimum FIR_CK is 32Mhz. The software chose 35Mhz because
it is smallest integer multiple (30Mhz would have been to
slow). Assume the fastest available speed grade of
HSP43220 is 33Mhz. The user may then use a local synchronizer to make the filter realizable. The following is just
one example of a local synchronizer that re-aligns the system clock edges to create a synchronous CK_IN.
The following restrictions are needed to insure maximum
performance.
1. System clock must have high and low times greater than
oscillator period.
2. Have to still meet DATA_IN setup and hold times at DDF
pins. Use of Q bar output makes this easier.
3. Realistically the maximum system clock rate is one sixth
of oscillator.
Clock Inputs
The requirement that the two input clocks be synchronous is
driven by the handshake circuitry between the HDF and FIR
section. In this circuitry there is a flip/flop which has CK_DEC
as the data input and FIR_CK as the clock input. Based on
the theory that it is impossible to design a synchronizer that
Node A can still become metastable but it has one oscillator
period to become stable. The user has access to node A and
can make his own evaluation as to if the circuit performance
is acceptable. In general the higher the speed capabilities of
the flip/flops used makes for faster resolution of the metastable condition if it should occur.
•
9-43
Harris Semiconductor
----
- ----====--:::::::=-= -- ------ - ---
-~
--
==
==
=
== ==
~
No. TB312
Harris Digital Signal Processing
January 1994
HDF BYPASS IN THE HSP43220
When HDF bypass is selected special timing restrictions
exist for signal CK_IN.
By definition of valid part operation, any time Hd = 1 the
FIR_CK will be at least 2 times the frequency of CK_IN.
When no decimation is selected for the HDF section either
by setting the H_BYP bit to 1 or by setting H_DRATE = 0, the
timing requirements for CK-IN require special consideration.
The FIR section of the chip is signaled that there is new data
from the HDF when a transition is detected on the signal
CK_DEC (see Figure 1). Failure to meet the timing requirements on CK_IN when Hd = 1 results in no or erratic
DATA_RDY pulses being issued.
In the example shown in Figure 3, the state of CK_DEC is
always a zero when sampled by the rising edge of FIR_CK.
To insure that signal CK_DEC is sampled in both its high and
low state by the flipflop requires careful control of CK_IN.
The most obvious solution is for the high or low time of
CK_IN to be a minimum of one period of FIR_CK. This guarantees sampling both a 1 and a 0 no matter what the phase
relation of FIR_CK and CK_IN is.
There is a specified range of allowed phase offset between
FIR_CK and CK_IN as given in the AC specifications by
spec T8K. Using this spec with 2ns of margin yields the following minimum CK_IN high or low time with setup and hold
as specified.
TRANSITION
DETECT
FIGURE 1. CILDEC GENERATION AND DETECTION
When Hd > 1, the intemal divider sets the high or low time of
CK_DEC equal to the period of CK_IN, guaranteeing that
CK_DEC will be detected by FIR_CK (Figure 2). When Hd =
1, the duty cycle of CK_DEC is the same as CK_IN as
shown in Figure 3.
CKJN
-IlI....---IInL.._--IIn...__n
CK.JN
CK..DEC
.-J
L
FIGURE 4.
For a 25Mhz part the minimum high or low time requirement
for CK_IN is 19ns (when Hd = 1) given the above timing
(independent of clock frequencies).
FIGURE 2. CIRCUIT TIMING WHEN Ho
CK_IN
CK..DEC
--1l'"-----'n____n...__n
--1l_---In
n
n
FIGURE 3. CIRCUIT TIMING WHEN Ho
Copyright
©
=2
For the typical user, guaranteeing the CK_IN high and low
times greater than or equal to the period of FIR_CK will be
the most desirable solution in terms of hardware. For the
user with additional system constraints, such as those that
vary the frequency of CK_IN but hold a high or low time constant, the above timing yields the most flexible solution.
=1
Harris Corporation t 993
9-44
Harris Semiconductor
------
------
-------- ===--==--== ---- -- - -- - ---
~
==--===--==-~-----
No. TB313
Harris Digital Signal Processing
January 1994
READING OUT FIR COEFFICIENTS FROM THE HSP43220
There are two methods of reading out the FIR coefficients.
With method 1, a single coefficient is output with every
DATA_RDY. With method 2, a coefficient is output every rising edge of FIR_CK.
Instead of an impulse, the DATA_IN pins are held at the
value 0800H. After (tapS/2)(Hdec+10) CK_IN cycles, all the
coefficients will be output on consecutive FIR_CKs in the
order in which they were written.
Method 1
Bypassing The HDF
The premise is to configure the 43220 to look like a FIR filter,
input an impulse, and observe the coefficients at the output.
Use the following equation to determine the Hdec required
with Fdec = 1 (if Fdec was equal to 1 in the original filter then
the correct Hdec is already known).
First, the FIR section of the chip is programmed for no decimation (Fdec = 1)' This may require changing H_DRATE from
the original setup (see BYPASSING THE HDF). The F_REG
is written for the original value of F_TAPS, F_BYP
0,
F_OAD 0, F_ESYM
1, F_DRATE 0, and F_CLA
(H_REG1). The FC_REG is loaded normally. The FIR data
ram must be sufficiently filled with zeros before the impulse.
The minimum number of zeros to clock into the 43220 is
Hdec*taps. The pin OUTSELH should be set to a zero. An
impulse, value 0800H, is input and the coefficients will be
output in the order, outer coeff through center coeff and back
to outer coeff. The 20 bit coefficients are output on the 24
DATA_OUT pins with the format shown below.
=
=
=
=
=
°
Method 2
HDEC =
Round the resultant value for Hdec up to the next integer
value.
=
=
1, set H_BYP
1, in this case an impulse is
For Hdec
defined as the DATA_IN pins having the value 0800H for one
rising edge of CK_IN.
=
=
=
For Hdec
N, N>1, set HBYP
0, H_DRATE
N-1,
H_GROWTH 50, H_STAGES 0. In this case an impulse
is defined as the DATA_IN pins having the value OBOOH for N
rising edges of CK_IN (see Figure 1).
This method allows for reading out the FIR coefficients in
less time than method 1 but requires the system to have the
ability to capture the value on the DATA_OUT pins every
FIR_CK. DATA_RDY has no meaning in this mode. The HDF
section must be configured as described in the BYPASSING
THE HDF portion of this memo. For an NTAP filter, the value
for F_TAPS is either NTAPS or NTAPS-1, which ever is odd.
For example, for either a 67 or 68 tap filter, F_TAPS 67.
Set other FIR parameters as follows: F_BYP = 0, F_OAD = 1,
F_ESYM = 1, F_DRATE 0, and F_CLA 1
=
=
CK_IN [ (taps/2) + 5]
FIR_CK
=
=
I"
~
=
HOECCYCLES
//
,.d
FIGURE 1
OUTPUT FORMAT
OATA..,OUT
SE • SIGN EXTENSION
Copyright © HarriS Corporation 1993
9-45
~I
//
I I L
I
Q(I)
Zu.
c(w
(1)-
wa:
I-
m
OX
ZU
Q.W
c(1-
Harris Semiconductor
------- ----- -- ----- =- - ~
---- - -
-
-~----
No. TB314
Harris Digital Signal Processing
January 1994
QUADRATURE DOWN CONVERSION
WITH THE HSP45116, HSP43168 AND HSP43220
The Harris HSP45116 Numerically Controlled Oscillator!
Modulator (NCOM) can be combined with a low pass filter to
perform down conversion on a digital signal. The NCOM
rotates the spectrum of a real or complex signal and outputs
a complex data stream. The signal of interest is now at base
band, so that the output can be low pass filtered to eliminate
unwanted signals (Figure 1).
SIGNALOF\
INTEREST
t • t •t t t t
INPUT SPECTRUM
OUTPUT OF
SIN/COS
GENERATOR
IN NCOM
t
.ilOt
sion and real to quadrature conversion of an input signal.
This is a generalized block diagram which can be used as
the basis for a specific design.
Several assumptions were made in defining this block diagram. Among these assumptions are:
• Input and output data are sixteen bits. Users requiring less
than that should keep bit 15 as the most significant bit,
grounding the unused bits on the input of the NCOM. In all
cases, bits 0 through 15 on the output of the NCOM
should be connected to the sixteen input bits of the DDF.
To select the output bits of the DDF, note that if the input is
a cosine at frequency A and the NCOM is tuned to frequency B and the phase offset is 0, then the real and
imaginary outputs of the NCOM at sample n are:
• Real Output: cos(An)cos(Bn)
=[cos(An-Bn) + cos(An+Bn)]
• Imaginary Output: cos(An)sin(Bn) = [sin(An+Bn) - sin(An-Bn)]
OUTPUT OF NCOM:
INPUT ROTATED BY
0)
•t t t t
• t t!T\t
t•t
• Note that the factor of 1!2 has been omitted. The output of
the Complex Multiplier is shifted left by one bit internally.
For this reason, both the real and imaginary outputs have
the same magnitude as the input.
_ _" - - ' - - ' - - - - ' _ - ' - - ' - - - ' ' - - - ' -
OUTPUT OF LOW:
PASS FILTER:
PASS ONLY
BASEBAND SIGNAL
t• t
FIGURE 1. DOWN CONVERSION SPECTRAL PLOTS
If the spectrum of the signal of interest is sufficiently narrow,
the output sample rate of the filter can be reduced to ease
the throughput requirements of the downstream processing.
Reducing the sample rate of a Signal is commonly known as
decimation. The input sample rate divided by the output
sample rate is known as the decimation factor, or simply
decimation. Note that decimation by one is equivalent to no
decimation, and decimation by less than one is undefined.
For the purposes of this discussion, base band Signals will
be divided into two categories: wide band signals, where the
decimation factor is 16 or less, and narrow band signals,
where the decimation is greater than 16.
Narrow Band Down Conversion
For narrow band output signals, Harris has a three chip set
with a filter that is capable of decimation by up to 16,384.
Figure 2 shows how the NCOM and HSP43220 Decimating
Digital Filter (DDF) are connected to perform down converCOPYright
© Hams Corporation
• The Phase Register is selected to control the phase of the
NCOM (as opposed to MODO-1) and is initialized along
with the center frequency. In this example, the lOAD# signal is not exercised, so the initial phase of the NCOM is
unknown.
• To shift the positive component of a real input signal to
base band, the Center Frequency Register of the NCOM
is set to a negative number.
• The Offset Frequency Register, Timer Accumulator and
Complex Accumulator of the NCOM are not used.
• The filter clocks of the two DDFs are driven at a higher
rate than the input data clocks. For many applications the
FIR_CK, CK_'N and elK signals can all be connected
together. In this case the divide by N block is not needed.
• The DDFs are reset and started asynchronously with a
pulse generator that receives asynchronous commands
from an outside source and drives the two DDFs simultaneously. The DDF receiving the asynchronous start pulse
performs the synchronization and starts the other part at
the proper time.
t 993
9-46
Tech Brief 314
"0"
RIN16·18
1~
,
AID CONVERTER:
~
"0'
DATA
WEI
ADDRESS
#'
0
w
c
DATA BUS
CO-15
WEI
WR#
#'
DECODEO
DECODE3
DECODE4
MODO·l
VCC_
PMSEl
DATA_ROY
~
~
C_BUSO-15
A0-2
DECODE3
HSP45116
HSP43220
CSt
RESETII
ADO-l
GN
FIR_CK
1~
WRit
;---i STARliN.
GND_ ClROFR#
Ul_
~
ADDRESS BUS
CSt
ENPHREG#
ENCFREG#
DECODEl
DECODE2
r-'l
DATA_OUTO-15
WE.
SHO-l
DATA BUS
ADDRESS BUS
L~
CIUN
IMINO-18
GND
DATA_INO·15
RINO-15
G N D - ENIIt
MICROPROCESSOR
,
16,
ROO-15
VCC
ASTARlIN.
GND
OUT_SElH#
GND
OUT_ENPIt
GND
OUT_ENX#
VCC- ENOFREG#
GND- ENPHAC#
16~
100·15
DATA..JNO·15
VCC- lOAD#
CK_IN
VCC- PACI#
~
FIR_CK
DATA_ROY
,
f--
DATA BUS
VCC- ENTIREG#
C_BUSO·15
VCC- RBYTIlD#
WEI
GND_ MODPII2PI#
ADDRESS BUS
VCC_ BINFMTII
DECODE4
WR#
AO·2
r--
ee
~~
::)w
GND- OEI#
VCC- OEIEXTII
........
wee
D.CI
~~
VCC- PEAK#
RESET.
VCC
STARTIN#
STARTOUTII ~
0
I w~
VCC- OEREXTII
HSP43220
CSII
~~
GND.- OUTMUXO·l
GND- OER#
ASTARTIN#
GND
OUT_SELH#
GND
OUT_ENP#
GND
OUT_ENX#
a:UJ " - - -
GND_ ACC
r
16,
DATA_OUTO-15
-B
ClK
1
OSCillATOR
FIGURE 2. BLOCK DIAGRAM FOR QUADRATURE DOWN CONVERSION WITH HSP45116 AND HSP43220.
9·47
f-+
Tech Brief 314
"0"
RIN0-5,l6-18
1106-15
INA0-8
10/
,
AID CONVERTER:
"0'
MICROPROCESSOR
ADDRESS
DATA BUS
ADDRESS BUS
w
Q
8w
DECODEO
..
DECODE2
DECODE3
Q
-
HSP45116
WEI
WR.
r--
GND_ CLROFRII
~
GND- MODO-l
vcc_
vcc-
GNDGNDGNDVCC
GND-
ADO-l
CSII
ENPHREG#
ENCFREGII
DECODEl
~
DECODE3
CO-15
ADDRESS BUS
L
IMINO-18
~ CLK
GND~ SHO-l
WEI
WE.
GND- INBO
G N D - EN"
DATA BUS
DATA
RIN6-15
PMSEL
if
ENOFREGII
GND- ENPHAC.
I--
GNDGND-
f--t-
106-15
1~
,
INAO-9
GND
VCC- PAC"
~
VCC- ENTIREG.
VCC- RBY11LD#
DATA BUS
GND_ MODPII2PI#
ADDRESS BUS
h
DECODE3
VCC_ BINFMTII
WE.
GNo--. OUTMUXO-l
GND
GND
GND
VCC
GND
GND- OER.
VCC- OEREXn
GND- OEIII
VCC- OEIEXT.
I
f--+
CSEL0-4
ACCEN
CINO-9
AO-8
HSP43168
CSII
WRII
RVRS#
FWRD#
MUX1.
MUXO#
SHFTENII
TXFR.
OEL.
OEH.
~
VCC- LOAD#
VCC_
OUT8-18
GND
GND
PEAKII
INBO
OUT9-18
CLK
CSELO-4
ACCEN
CINO-9
HSP43168
AO-8
~
Cst
WR.
RVRS#
FWRD#
MUX1.
MUXO#
SHFTEN.
TXFR.
OEL.
OEHII
GND_ ACC
OSCILLATOR:
I
CLK
FIGURE 3. BLOCK DIAGRAM FOR WIDE BAND QUADRATURE DOWN CONVERSION WITH HSP45116 AND HSP43168.
9-48
Tech Brief 314
"0"
RINl6-18
10/
,
AID CONVERTER:
.
r
"0'
GND
DATA BUS
DATA
.
WE.
WE.
w
0
0
106-15
IMING-18
r
DECODEO
DECODE2
w DECODE3
-
~
--
ADG-l
§
~
GND_ ClROFR.
GND- MODG-1
OUTSl-18
INBG-II
fo
DECODE3
WE.
HSP45116
ENCFREG.
0
INAG-Il
'.1
ADDRESS BUS
CSt
ENPHREG#
DECODE1
0
CG-15
10.1
DATA BUS
SHO-1
WR.
ADDRESS BUS
L
RING-15
G N D - ENI.
MICROPROCESSOR
ADDRESS
r
R06-15
H
-
ClK
CSEl0-4
ACCEN
CIN(I.SI
A(I.SI
HSP43168
CSi
WR'
GND- AVRS.
GND- FWRDt
MUX1t
MUXO.
GND- SHFTEN#
TXFR.
VCC OEl'
GND- OEH.
VCC_ PMSEl
VCC- ENOFREG#
GND- ENPHACI
VCC- lOAD.
.~~
VCC- PACI#
VCC- ENTlREG#
VCC- RBYTILD#
~
GND_ MODPV2PI#
VCC_ BINFMT#
GND-- OUTMUXG-1
GND- OER#
VCC- OEREXT.
GND- OEI#
VCC- OEIEXT#
VCC- PEAK.
I
GND_ ACC
OSCillATOR:
I
ClK
FIGURE 4. BLOCK DIAGRAM FOR WIDE BAND DOWN CONVERSION WITH HSP45116 AND HSP43168.
9-49
Q
Tech Brief 314
Wide Band Down Conversion
Combined Narrow And Wide Band
Figures 3 and 4 show how the NCOM and HSP43168 Dual
FIR Filter (Dual FIR) are connected to perform down conversion and real to quadrature conversion of an input signal.
Because the Dual FIR can implement either one or two filters, two block diagrams are shown. Figure 3 shows the
case where each 43168 is implementing a single filter. The
maximum number of coefficients in this case is 16 times the
decimation factor for each filter. Figure 4 shows the same
configuration with the exception that the Dual FIR is now
configured as two independent filters, each with a maximum
length of 8 times the decimation factor.
In some applications, it is necessary to pass both wide and
narrow band Signals. In this case, both the HSP43220 and
HSP43168 can be used in parallel, with the user selecting
the output of either set of chips, depending on the characteristics of the signal of interest. Figure 5 shows this application, with most of the control signals eliminated for clarity.
(These Signals can be derived from the previous block diagrams.) In addition, note that the input data clock (CK_IN)
and the FIR clock (FIR_CK) of the DDF have been connected together. This configuration is applicable when the
input data rate is sufficiently high to allow the filter to operate
at this rate also. If this is not the case, the divide by N circuit
used in Figure 2 could be used, with the high speed clock
driving the FIR_CK pins and the divided down clock used for
all other clocks in the circuit.
These are generalized block diagrams which can be used as
the basis for a specific design. Note that they do not represent detailed schematics with all gates represented. For
instance, the control signals are driven with a single
PAl22V10 operating as a self contained state machine; it
reality, the 22V1 0 may not have enough gates to generate all
the necessary output sequences; in that case, it would be
necessary to have a counter generate the states and use the
PAL to decode the counter output, generate the control signals to the 43168, and reset the counter when the sequence
is completed.
The design parameters of these circuits are:
• Input data is 10 bits. Users requiring less than that should
keep bit 15 as the most significant bit of the NCOM,
grounding the unused bits on the input. In all cases, bits 6
through 15 on the output of the NCOM should be connected to the input bits of the Dual. To select the output
bits of the Dual, note that if the input is a cosine at frequency A and the NCOM is tuned to frequency B and the
phase offset is 0, then the real and imaginary outputs of
the NCOM at sample n are:
New Products
Now available from Harris are the HSP50016 Digital Down
Converter, which is a single chip quadrature down converter
and low pass filter (Figure 6). In addition, the HSP43216 Half
Band Filter allows the user to double the input sample rate of
the NCOM for real signals (Figure 7). Contact your local Harris sales office or representative for more details on these
and other new products from Harris.
• Real Output: cos(An)cos(Bn) = [cos(An-Bn) + cos(An+Bn)]
• Imaginary Output: cos(An)sin(Bn)
=[sin(An+Bn) - sin(An-Bn))
• Note that the factor of 1/2 has been omitted. The output of
the Complex Multiplier is shifted left by one bit internally.
For this reason, both the real and imaginary outputs have
the same magnitude as the input.
• The Phase Register is selected to control the phase of the
NCOM (as opposed to MODO-1) and is initialized along
with the center frequency. In this example, the LOAD# signal is not exercised, so the initial phase of the NCOM is
unknown.
• To shift the positive component of a real input signal to
base band, the Center Frequency Register of the NCOM
is set to a negative number.
• The Offset Frequency Register, TImer Accumulator and
Complex Accumulator of the NCOM are not used.
• The decimation rate in the Dual FIRs is greater than one.
For no decimation, TXFR# should be grounded. Note that
the maximum number of coefficients in the 43168 is eight
or sixteen times the decimation rate, depending on the
mode (see above).
9-50
Tech Brief 314
RINl6-18
"0"
INA0-9
ROO-15
I
OUT9-18
RINO-15
AID CONVERTER:
ClK
IMINO-18
"0'
~
HSP43168
OEl.
OEH.
HSP45116
DATA..JNO-15
HSP43220
ClK_IN
FIR_CK
DATA_OUTO-15
OUT_ENP#
OUT ENX#
I
OSCillATOR :
100-15
l
-
OUT9-18
INAO-9
ClK
ClK
WIDE/NARROW
BAND SELECT
~
....
HSP43168
OEl.
OEH#
DATAJNO-15
HSP43220
ClK_IN
FIR_CK
DATA_OUTO-15
t--
OUT_ENP#
OUT ENXIt
FIGURE 5. BLOCK DIAGRAM FOR QUADRATURE DOWN CONVERSION WITH HSP45116, HSP43220 AND HSP43168
9-51
Tech Brief 314
DATA
...._ _ _ _--.. HIGH DECIMATION
CONTROL
TEST ACCESS
PORT
ALTER
LOWPASSAR
ALTER
HIGH DECIMATION
ALTER
LOWPASSAR
ALTER
COS
COMPLEX
SINUSOID
GENERATOR
AGURE 6. BLOCK DIAGRAM OF HSP50016 DIGITAL DOWN CONVERTER
26MHz
COMPLEX
SIGNAL
52M Hz
RE ALINPUT
I
HSP43216
Q
HSP45116
U
'L
HSP43220
BASEBAND
SIGNAL
HSP43220
""",,[}.
SAMPLEFBEQ
2
SIGNAL INPUT
SAMPLEFREg
2
SAMPLEFBEg
2
DOWN CONVERSION
AND ALTERING
ANETUNING
AGURE 7. HALF BAND ALTER IN QUADRATURE DOWN CONVERSION
9-52
SAMPLEFREg
2
NARROW BAND ALTERING
Harris Semiconductor
---- -No. TB316
-----
------
- --- ----
- -=! -
=-:;;
~
:;
= ======
==
Harris Digital Signal Processing
January 1994
PIPELINE DELAY THROUGH THE HSP45116
The following timing diagrams show the pipeline delays
through the HSP45116 NCOM from the time that data is
applied to the inputs until the outputs are affected by the
change. The delay is shown as a number of clock cycles,
with no attempt made to accurately represent the setup and
hold times or the clock to output delays.
ClK
WRITE
WRITE
MS INPUT lS INPUT
WR REGISTER REGISTER
WRITE
PHASE INPUT
_____________________
REGIS;.;T,;;ER~
#~--------------------
WR'--V-
AD0-1 ::::xx:::JOC
ADO-1::::::·~C)·~::::::::::::::::::::::::
::xx:::x;:.c
C~15.::::::·~CJ·~::::::::::::::::::::::::
C0-15
ENCFREG,
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
ENCFREG,
ENOFREG
ENOFREG------~\Jr---------------------
NEW
FREQUENCY
DATA,
TRANSFER DATA TO
PHASE REGISTER
------"''--tl'----------------N-E-W---PHASE
DATA
~gg:l: : : : x : : x : : : : x : : x
~gg:l~:::x::x::::x::x
FIGURE 1. FREQUENCY TO OUTPUT DELAY
FIGURE 2. PHASE TO OUTPUT DELAY
ClK
MODO-1:::::::::::J·Cc:J:l·~:::::::::::::::::
ClK
PMSEL.:::::::::,~-ll:::::::::::::::::::::
TRANSFER DATA TO
PHASE REGISTER
ENPHREGi#::::::::l'__~'c:::::::::::::::::::::
NEW
PHASE
DATA
DATA
WORD0123456789
~:~g:1:
::x:x:x::x:::x:
OUTPUT
WORD
~gg:1:
~gg:1::::::x:::x:::x:
012345
::::x:::x:::x::
I
COMPLEX
L-. MULTIPLY
DATA 0
FIGURE 3. PHASE MODULATION TO OUTPUT DELAY
FIGURE 4. VECTOR INPUT TO OUTPUT DELAY
Copyright © Harris Corporation 1993
9-53
Harris Semiconductor
-----.-
---~--=-----------
~
--
--
No. TB319
~
=:.-=
- --------=
~-
=
-~-
=-==
==
== ;;
==
==
==
Harris Digital Signal Processing
January 1994
READING THE PHASE ACCUMULATOR OF THE HSP45106
The block diagram shown below illustrates the method of
reading the phase accumulator of the NC01S from a microprocessor. The setup shown is very similar to that used
when the part is used for generating a complex sinusoid,
except that the internal SIN/COS lookup is bypassed by putting a logic 1 on the TEST pin. While the TEST pin is high,
the phase accumulator continues to drive the inputs of the
SIN/COS Generator while the most significant 28 bits of the
phase accumulator are multiplexed out onto the output pins.
Because of this, the part can be operated in two modes, one
where the SIN/COS Generator is permanently bypassed,
and one where the phase accumulator output is brought out
to the outputs as a check.
Figure 1 shows the circuit for reading out the phase accumulator all the time. In this case, a microprocessor loads the
frequency and phase registers of the NC01S. This is fairly
straightforward, except the Start logic block, which needs to
be synchronous to the oscillator clock and the microprocessor interface. This has been left as an undefined function,
since it is dependent on the implementation. Also note that
COSO-15 are connected up, although only COS4-15 are
valid in this application. The microprocessor reads the sine
and cosine data busses as if they were RAMs, using the
decoded address bus to select one or the other.
MICROPROCESSOR
HSP45106
The timing for loading the center frequency register and seeing the output on COSO-15 and SINO-15 is shown in Figure 2.
This timing is independent of whether the output data represents the phase accumulator data or the SIN/COS Generator output.
ClK
CSt
-=' D
I
WRITE
WRITE
MSINPUT LSINPUT
REGISTER
REGISTER
WR.
______________________
~~
A~2
C~15
:JC[:X)~
______________________
:::x::x::x:x'--____________________
TRANSFER DATA
TO CENTER OR OFFSET
ENCFREGII,
FREQUENCY REGISTER
ENOFREG·-----....,Ur - - - - - - - - - - NEW
FREQUENCY
1
COS~1S,~
SlN~15
GND
VCC
DECODE
START
lOGIC
VCC
GND
VCC
GND
VCC
VCC
vee
VCC
vee
OSCilLATOR
FIGURE 1. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NC016
FIGURE 2. NC016 PIPELINE DELAY
When the output of the NC01S is to be switched back and
forth between sine/cosine and the phase accumulator, a circuit such as the one shown in Figure 3 could be used. In this
case, the sinusoidal output cannot be interrupted, so the
phase accumulator must be read out between samples. This
is possible due to the fact that the TEST signal is simply the
control line for a multiplexer on the output of the SIN/COS
Generator, but carries with it a limitation on the maximum
possible clock rate. Since TEST is a synchronous input, the
output of the NC01S must be either driven by the SIN/COS
Generator or the phase accumulator for an entire clock
cycle. Therefore, the part must be driven at twice the desired
speed at all times so there is a clock cycle available for
TEST when necessary. Note that the processor must be
driven from the same clock that generates the NCO clock in
order to maintain synchronous operation. The timing is identical to that shown in Figure 2 with ClK replaced with ClKl2.
Copyright @ Harris Corporation 1993
9-54
Tech Brief 319
MICROPROCESSOR~_ _ _--Il~:s;u.l<2.._"T':l
MODO-2
PMSEL SIN0-15
DATAI---~---ICO-15
WE.
ADDRESS
WR.
A0-2
nl----iCS.
I----IENPOREG#
I----IENCFREG#
1----IOEst
I----IOEC.
ENOFREG.
DECODE ~~C
ENPHAct
ENTlGEG.
VCC
GND
INHOFR#
t----iINITPAct
vcc
PACI#
INITTAC.
~~~J vcc
TEST
PARlSER#
BINFMTI!
I--r---ICLK
REGISTER
'---_.....
FIGURE 3. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NC01S WHILE GENERATING SINUSOID
9-55
Harris Semiconductor
------
-----
- -- - = -
---------
---
No. TB317
:
--
-~ ~
--
====- ==
-=
:: =
Harris Digital Signal Processing
January 1994
PIPELINE DELAY THROUGH THE HSP45106
change. The delay is shown as a number of clock cycles,
with no attempt made to accurately represent the setup and
hold times or the clock to output delays.
The following timing diagrams show the pipeline delays
through the HSP45106 NC016 from the time that data is
applied to the inputs until the outputs are affected by the
CLK
cs# ----".
tt=\ '
WRITE
WRITE
MS INPUT
LS INPUT
WR#~
___________________________________________________
REGISTER
REGISTER
AO-2
=-x:::x::::::::
C~15=-X:::X::::::::==============================================
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
ENCFREG#,
ENOFREG#--------~.......,
NEW
FREQUENCY
DATA
C~~~~~ ::::~::::~::::~::::)C::::)C::::)C::::~::==(:::~c::::>c::::>c::::>==
FIGURE 1. FREQUENCY TO OUTPUT DELAY
CLK
WRITE
PHASE INPUT
REGISTER
WR# _ _ _ _ _............,
AO-2
========::::J>c::)(CX============================================
C~15=========>c::)(=========================================
TRANSFER DATA TO
PHASE REGISTER
ENPOREG#---------~'--',-----------------------------------------
NEW
PHASE
DATA
FIGURE 2. PHASE TO OUTPUT DELAY
Copyright © Harris CorporatIon 1993
9-56
..
TB317
elK
MODO-2
PMSEL
============::>x::::J(C:X======================
=========:,~~<,========================:::
TRANSFER DATA TO
PHASE REGISTER
ENPOREG#=========:'~~<'========================:::
NEW
PHASE
DATA
C~~~~~ ~==:z~==~z::=~z::=~.C:=~Wc:=~zC:=~~C:=~C:==~==)C=
FIGURE 3. PHASE MODULATION TO OUTPUT DELAY
9-57
Harris Semiconductor
- - -- - - - ----
-------------- - - - - - - - ----~
----~--------~---
==--=--=-----======~----
=------------------------
No. TB318
- ----- --- - --- -=== -- -- -==
-- - = -====--=
:::::::. .:::::::::::=:: =-------::: :::::=
-- ---------~
Harris Digital Signal Processing
January 1994
THE NCO AS A STABLE, ACCURATE SYNTHESIZER
Low Jitter Frequency Reference
In communication and other circuits, it is often necessary to
produce an accurate reference signal whose frequency and
phase can be precisely controlled in real time. The Numerically Controlled Oscillator (NCO) is ideally suited for this purpose. For some applications, the output reference signal is a
square wave, so the temptation is to use only the MSB of the
NCO output. This is useful in low frequency applications
such as motor controllers, but is inadequate for most communications tasks. This is because the zero crOSSings of this
signal can vary by one period of the Input clock from one
pulse to the next, which creates an unacceptable amount of
jitter in the output. For example, if the NCO is clocked at
30MHz, the jitter is 33nsec. For a 1MHz square wave, this
results in 12" of phase jitter. The straightforward solution Is
to use an NCO with a much higher clock rate. This is not
cost effective for applications requiring phase jitter of less
than Snsec, however, since it requires a sample rate of 200
Mega Samples Per Second, (MSPS), which drives the user
to an ECl NCO.
'
DAC
A much less costly circuit which solves this problem is
shown in Figure 1. The output of the comparator is a square
wave with much less jitter than the NCO alone. The basic
idea is that the sampled sine wave output of the NCO is converted to a smooth sine wave, which is converted back to a
square wave with a comparator. In the circuit shown, the
comparator drives a filter, which attenuates the odd order
harmonics so that the final output of the circuit is a sine
wave. The upper limit on the purity of the sine wave is also
much better than that of the NCO, as will be seen below.
The primary sources of error In this circuit are:
In the NCO, spurs are classified as either AM or PM. PM
spurs are due to truncation of the phase in calculating the
sine and cosine. If M number of bits into the input of the
Sine/Cosine Generator, the PM spur level is -8M + S.17dB[1].
The AM spurs are due to amplitude quantization on the output of the NCO. If the number of NCO output bits is N, the
AM spur level is approximately equal to -6.02N - 1.78dB. [1]
There will also be jitter due to the clock oscillator driving the
=
FILTER
r-_--.:RO~LLOFF
RESPONSE
L----~,~
AM HARMONIC
~~~
1Er"". ~
.....N_CO
___
Ipl t I,t I
~~~
i "".. ~
FILTER
iESPONSE
FCLl(
FIGURE 1. MINIMUM SPUR CIRCUIT
Copyright @ Harris Corporation 1993
9-58
Tech Brief 318
NCO, but since it is only the short term jitter, not the long
term stability of the oscillator that contributes to phase noise,
this will be negligible if a reasonably good oscillator is used.
The DAC introduces additional spurs, which come from
three sources: intermodulation spurs due to non-linearities in
the DAC; a spur at the clock oscillator frequency due to clock
feed-through; and power supply noise. The DAC also faithfully reproduces the aliases and harmonics that are unavoidable products of the NCO due to the digital nature of the
output.
The filter on the output of the DAC eliminates the clock feed
through, aliases due to the sampled nature of the NCO output
and most of the AM spurs are eliminated with the bandpass.
Spurs within the pass band are unchanged. The spectrum of
the DAC output is a tone surrounded by spurs and noise in the
frequency band corresponding to the pass band of the filter
with negligible noise elsewhere. The area comprised of the
tone, spurs and noise is known as the pedestal.
The input of the comparator is a relatively clean sine wave
which the comparator converts into a square wave. This limiting action eliminates the AM spurs but has no effect on the
PM spurs. For this reason, the number of bits used on the
output of the NCO and the input of the DAC has little measurable effect on the output. The primary contributions to
errors on the output of the comparator are the PM spurs on
its input, which are passed through relatively unaffected, and
power supply noise, which is attenuated by the power supply
rejection of the comparator. If the filter on the input of the
comparator did not remove the aliases and clock feed
through, then the comparator will generate intermodulation
components. This makes a good filter and a careful frequency plan essential.
Extended Frequency Resolution
The phase accumulator of the HSP45106 (NC016) is 32bits
wide. This corresponds to a frequency resolution of (Sample
Frequency)/2 32 • For a 25 MSPS sample rate, this results in
an output frequency resolution of 0.006Hz. In certain applications, there is a requirement for much greater resolution.
The NC016 can address these applications using the Time
Accumulator as an extension of the Phase Accumulator. Frequency resolutions of up to 64bits can be obtained in this
configuration. USing the previous example of a 25MHz clock,
the frequency resolution is 25MHzl264 = 1.35picoHertz.
Using the parts in this configuration requires a small change
to the external control logic: the Timer Accumulator register
must be loaded over the control bus interface. This mode of
operation has no effect on any of the other performance
parameters, such as spurious free dynamic range, phase
resolution, etc.
To configure the HSP45106 for this application, the setup
shown in Figure 2. Note that the Timer Accumulator output,
TICO#, is connected to the Phase Accumulator input, PACI#.
To set the output frequency of the part, the Center Frequency Register and the Timer Accumulator must be loaded.
Assuming that the Offset Register is not used, the equation
for calculating the output frequency is now:
MICROPROCESSOR
MODo-:!
PMSEl
DATA~D~~C0-15
WE.
ADDRESS
If the desired output of the circuit is a sine wave rather than a
square wave, the output of the comparator is filtered to
extract the fundamental - that is, to suppress the odd order
harmonics of the square wave signal. Note that this signal is
much cleaner than the output of the first filter, since the comparator has removed the AM spurs.
The circuit shown here is often used to generate the reference tone for an indirect loop Pll synthesizer. In this case,
the output of this circuit is fed into one input of a mixer, with
the other input of the mixer driven by a high frequency VCO.
The output of the mixer is a high frequency tone. The phase
noise at the output of the mixer due to the noise in the reference circuit will be equal to the spur level of the reference
circuit plus 20*log10(output frequency/NCO frequency). For
example, using the 45106 as a 5MHz reference for a 1GHz
synthesizer, the spurs on the output of the reference would
increase by 2010g10(200), so the output spur level would be
-114 + 46 = -68dBc at 1GHz. The NCO frequency resolution
is 0.008Hz at 33 MSPS, so the tuning resolution of the synthesizer is 200(0.008) = 1.6Hz. Finer resolution can be
obtained by cascading the Time Accumulator with the Phase
Accumulator. (See below.)
HSP45106
GND
VCC
SIN0-15
WRII
COS0-15
A0-2
CSt
TICOil
ENPOREG.
ENCFREG.
OESII
LJ------IOECII
ENOFREG.
ENPHACII
ENTIGEGII
INHOFRII
t--;:===!INITPACII
~
PACIII
INmACII
TEST
PAR/SER.
BINFMT#
ClK
FIGURE 2. EXTENDED FREQUENCY RESOLUTION CIRCUIT
Center Frequency
=
ClK Frequency x «Center Frequency Register /232)
+ (Timer Accumulator Register /264)
In this equation, the contents of the value in the Center Frequency Register is a two's complement number, Le., the part
tunes from -(ClK Frequency) / 2 to +(ClK Frequency) I 2.
The value in the Timer Accumulator is an unsigned number.
9-59
Tech Brief 318
It is unsigned because it provides the carry in to the Phase
Accumulator, which is always added to the LSB of the current phase value.
The user should note that there is a flip flop between the
Time Accumulator carry out and the TlCO# pin, and another
flip flop between the PACI# pin and the Phase Accumulator
carry input. This will cause a two clock cycle delay between
the carry out of the timer into the carry in of the accumulator.
This will only have an effect on the output when the frequency register is updated; in effect, the Time Accumulator
lags the Phase Accumulator by two clock cycles. If this is a
concern, this can be compensated for by loading the input
registers for both accumulators, then toggling ENTIREG#
two clock cycles before ENCFREG#.
While the internal architecture of the HSP45116 NCOM and
the HSP45106 NC016 are very similar, this application
works better with the NC016 for two reasons. The first is
that on the NC016, the timer is loaded using a unique pin,
rather than sharing this function with the ROM bypass line.
This means that the output of the NC016 is always valid,
instead of having erroneous results on the output whenever
the timer is updated. The second is that with the NC016, the
data for the various registers is downloaded into separate
input registers, which can be downloaded into the operating
registers with the ENXXREG# pulses. With the NCOM, there
is only one 32bit input register, which must be downloaded
into the appropriate operating register before the next value
can be input into the part. In this application, it means that
the user can adjust the phase between the register updates
with the NC016 but not with the NCOM.
Example
The circuit used to verify this equation is shown in Figure 2.
The clock oscillator frequency was measured at
25.24102MHz. In order to achieve an output frequency of
1.00ooooHz, the center frequency was set to hexadecimal
AA, the offset frequency set to 0, and the Timer Accumulator
set to hexadecimal 28880000. A frequency counter was
attached to bit 15 of the cosine output. The actual frequency
out varied from 0.9999999 to 1.0000003 as the oscillator
drifted with time. A more stable oscillator would yield more
predictable results. Note that going through the calculations
results in an output frequency of 1.000000sHz. The difference is due to the fact that the oscillator frequency measurement was only carried out to 7 digits, but the counter used in
this example had B digits.
References
(1) Cercas, Francisco A. B., Tomlinson, M and Albuquerque,
A. A. Designing with Digital Frequency Synthesizers, Proceedings of RF Expo East, 1990
9-60
Harris Semiconductor
No. TB305
-
January 1994
--------------------------- --
---
===
==
== ==
~=!-
== ==
Harris Digital Signal Processing
HISTOGRAMMING WITH A VARIABLE PIXEL INCREMENT
The HSP48410 Histogrammer/Accumulating Buffer has several modes; two of these are Histogram mode, in which the
part computes the histogram of an input data stream, and
bin accumulate mode, in which it computes the totals of a set
of rank-ordered data. These operations work on generalized
digital data, but for the purposes of this tech brief, image
data will be used as an example.
In Histogram mode (Figure 1),the HSP48410 accepts pixel
data on the PIN0-9 bus. It uses this information as the
address of its internal RAM to compute the number of pixels
in an image that are at each gray level. The contents of the
RAM at the given address is fed into an adder; the other
input of the adder is set to all zeroes except for a one in the
LSB. The output of the adder is written back into the RAM in
the same location. When all pixels have been processed by
the chip, the RAM contains the histogram of the image.
When placed in Bin Accumulate mode (Figure 2), the
HSP48410 operates in a similar manner, except that the
inputs to the adder come from the RAM and the DINO-23
input bus. In this mode, the user loads the DIN bus with the
desired increment value. Since this is a synchronous input, it
can be changed on a pixel by pixel basis. When the operation is finished, the completed histogram will be stored in the
RAM as before.
Figure 3 shows an implementation of the latter function
using a TMS320 for the system microprocessor. The circuit
diagram and timing were derived from the TMS320C25 data
sheet and the 1989 Second Generation TMS 320 User's
Guide. This circuit has not yet been verified with a physical
implementation.
=
Initially, the part is set to Bin Accumulate mode (FCT 100).
The memory is reset with FC# (Flash Clear) prior to data
processing. The input image data is latched into PINO-9, the
histogram increment for that pixel is simultaneously loaded
into DINO-23. The internal pipeline delays align the two sets
of data internally so that the proper bit in the histogram is
incremented with the right number. The SYNC signal is used
to flag the beginning of the new frame of data, and stays low
while image data is being fed into the part.
When one frame of image data has been processed, the histogram can be read out of the memory over the microprocessor interface. After the START# pin is brought high, the
TMS320 uses the FCTO-2 lines to configure the part for 16 bit
Asynchronous mode (FCT 111). The contents of the bins
can now be read out asynchronously to the pixel clock and in
random order. START# remains high during this operation.
FIGURE 1. HISTOGRAMMER MODE BLOCK DIAGRAM
=
FIGURE 2. BIN ACCUMULATE MODE BLOCK DIAGRAM
Copyright © Harris Corporation 1993
9·61
Tech Brief 305
~----------------------------------~ DATA~15
~--~~~----~--~----------------~ A~A10
PIXEL DATA
PINO-II
SYNC
START.
LD#
r'----------r-------alr::::::::-~_I
A11-A15
os
~---------r~ ~
RD.
WR#
PIXEL CLOCK
CLK
FCII
'--l~~------~------------------_IiTRB
74AS32
READY
HSP48410
WAIT STATE
GENERATOR
(1 WAIT
STATE
74AS30
(UNUSED
INPUTS
TIED HIGH)
MICRO
PROCESSOR
(TMS320)
FIGURE 3. HSP48410 CIRCUIT SHOWING INTERFACE TO TMS 320 AND DYNAMIC PIXEL INCREMENT
9-62
Harris Semiconductor
---------------------------No. TB306
--
-- =
------~
--
~
= ==--=
-- ~
~
==
Harris Digital Signal Processing
January 1994
CASCADING MULTIPLE HSP45256 CORRELATORS
When multiple correlators are cascaded for longer reference
data sets, the Programmable Delay is used to adjust the timing between chips so that they can be connected with no
external hardware. Figure 1 shows the portions of two correlators that would be active when two 45256's are set up to
perform a 1 bit, 512 tap correlation. In this case, DOUT? of
one correlator is connected to DIN? of the next one;
CASOUTO- 12 of the first part are connected to CASIN()"12
of the second one. (See the HSP45256 data sheet.) Figure 2
shows the relevant portions of two Correlators which are
cascaded together; in this example, each is configured as
1x256. In the interest of clarity, the only portions shown are
the final stage of the first correlator and the first stage of the
second one. The data sample number at each stage for a
given clock cycle is shown in the boxed in numbers. Note
that the Programmable Delay of the first part is set to a delay
of one (the minimum possible) and the second part is set to a
delay of two. This assures that the proper samples are
added in the Cascade Summer.
HSP45256
HSP45256
INPUT DATA
----;
DINO-7
DOUTO-7
CASOUTO-12
REFERENCE DATA
----; DREFO-7
AUXOUTO-7
DCONT0-7
FROM MICROPROCESSOR:
DATA BUS
A0-2
CLOAD#
f--!
f--!
DlNO-7
f"---l
DREFO-7
CASIN0-12
DCONTO-7
CASOUT0-12
A0-2
CLOAD#
J
r
ADDRESS BITS 0-2
ADDRESS BITS 3-N
WEI
r-------; A
~J--_....J
-EN#
h
a...-
~}-------------------------~
DECODE
FIGURE 1. CIRCUIT BLOCK DIAGRAM
Copyright
© Harris Corporation 1993
9-63
r--+
Tech Brief 306
DATA OUT
~()'12
CASCADE
SUMMER
CORRELATOR 112
"0"
FIGURE 2. CASCADED CORRELATORS SHOWING RELATIVE CLOCK CYCLES.
9-64
Harris Semiconductor
-=! -
---------~~-------------
No. TB307
~-
~
==
Harris Digital Signal Processing
January 1994
CORRELATION WITH MULTIBIT DATA
USING THE HSP45256
For single bit data, the output of the correlator, that is, the
correlation score, represents the total number of data bits
that match the reference at time n. At time n+ 1, the data
slides past the reference by one sample, a new data sample
is input into the device, and the new sum is calculated. When
the data matches the reference most closely, a correlation
peak is obtained. Figure 1 shows a stream of data being correlated with a reference and the corresponding peak in the
output score.
The maximum possible correlation score (corresponding to a
perfect match) equals the number of bits in the data stream.
Assuming that the reference pattern occurs only once in the
data, the correlation score will build slowly until it reaches the
peak. Assuming random input data, most of the time about
half of the data samples will match the reference. The minimum correlation score for a given configuration will then be
one half of the peak score.
This example is ideal; the received pulse is not corrupted by
noise, so correlation is perfect. In the real world, noise on the
input data will lower the correlation peak, making it more difficult to determine its position in the data. Quantizing the data
using more than one bit helps to alleviate this problem. In the
example shown in Figure 2, two bit quantization is used to
illustrate this point. In this case, calculation of the maximum
possible score must take into account the bit weighting. The
output scores are shown normalized to their respective maximums so that a fair comparison is achieved. Note that using
more data bits sharpens the peak of the score.
REFERENCE
CORRELATION SCORE
o
MIN
MAX
DATA
TIME n
n+1
n+2
n=3
n+4
FIGURE 1. CONCEPTUAL DIAGRAM OF CORRELATION OF SINGLE BIT DATA AND REFERENCE
Copyright © Harris Corporation 1993
9-65
Tech Brief 307
REFERENCE
o
o
CORRELATION SCORE:
o
000
o
DATA AT TIME n + 2
o
o
o
o
0
1+1+1+1+0 +1+1+1+0+1+1+1" 10
TOTAL POSSIBLE .12
10112" 0.83
SCORE AT n + 1 = 8112" 0.75
SCORE AT n + 3,. 6112" 0.50
1 BIT QUANTIZATION
00
00
11
11
10
00
00
11
t=====\
I
-
\
10
11
11
00
2 (1+1+1+1+0+1+1+1+0+1+1+1)
+ (1+1+1+1+1+1+1+1+1+1+1+1)" 32
-
I
\
TOTAL POSSIBLE .. 36
32136= 0.89
2 BIT QUANTIZTlON
SCORE AT n + 1 " 21136 " 0.58
SCORE AT n + 3 = 18136 = 0.50
FIGURE 2. COMPARISON OF CORRELATION USING ONE BIT AND TWO BIT DATA
9-66
OS :)--------; 10
HARRIS QUALITY AND RELIABILITY
PAGE
HARRIS QUALITY ........................................................................ .
10-3
INTRODUCTION .......................................................................... .
10-3
THE ROLE OF THE QUALITY ORGANIZATION ................................................. .
10-3
THE IMPROVEMENT PROCESS ............................................................. .
10·3
DESIGNING FOR MANUFACTURABIUTY ..................................................... .
10-3
SPECIAL TESTING ....................................................................... .
10·5
HARRIS SEMICONDUCTOR STANDARD PROCESSING FLOWS .................................. .
10·6
CONTROLUNG AND IMPROVING THE MANUFACTURING PROCESS· SPCIDOX .................... .
10-8
AVERAGE OUTGOING QUAUTY (AOQ) ....................................................... .
10-9
Training ............................................................................... .
10-9
Incoming Materials ....................................................................... .
10-9
CALIBRATION LABORATORY •..............................................................
10-11
MANUFACTURING SCIENCE· CAM, JIT, TPM ................................................. .
10-11
Computer Aided Manufacturing (CAM) ....................................................... .
10·11
Just In Time (JIT) ........................................................................ .
10-11
Total Productive Maintenance (TPM) ......................................................... .
10-11
HARRIS REUABILITY ..................................................................... .
10-12
PROCESS/PRODUCT/PACKAGE QUAURCATIONS ............................................. .
10-12
PRODUCT/PACKAGE RELIABITY MONITORS ................................................. .
10·12
FIELD RETURN PRODUCT ANALYSIS SYSTEM ................................................ .
10-13
FAILURE ANALYSIS LABORATORY .......................................................... .
10-16
~~
cc~~
-cc
..J-
ANALYTICAL SERVICES LABORATORY ...................................................... .
10·16
:»w
REUABIUTY FUNDAMENTALS AND CALCULATION OF FAILURE RATE ........................... .
10-17
CC..J
Failure Rate Calculations .................................................................. .
10-17
Acceleration Factors ..................................................................... .
10-18
Activation Energy ........................................................................ .
10-18
TECH BRIEF 52 Electrostatic Discharge Control A Guide To Handling Integrated Circuits ............... .
10-19
10·1
aa:
Harris Quality
Introduction
The Improvement Process
Success in the integrated circuit industry means more than
simply meeting or exceeding the demands of today's market.
It also includes anticipating and accepting the challenges of
the future. It results from a process of continuing improvement and evolution, with perfection as the constant goal.
t
IMPACTON
PRODUCT
The Role of the Quality Organization
The emphasis on building quality into the design and manufacturing processes of a product has resulted in a significant
refocus of the role of the Quality organization. In addition to
facilitating the development of SPC and DOX, Quality professionals support other continuous improvement tools such as
control charts, measurement of equipment capability, standardization of inspection equipment and processes, procedures for chemical controls, analysis of inspection data and
feedback to the manufacturing areas, coordination of efforts
for process and product improvement, optimization of environmental or raw materials quality, and the development of
quality improvement programs with vendors.
At critical manufacturing operations, process and product
quality is analyzed through random statistical sampling and
product monitors. The Quality organization's role is changing
from policing quality to leadership and coordination of quality
programs or procedures through auditing, sampling, consulting, and managing Quality Improvement projects.
To support specific market requirements, or to ensure conformance to military or customer specifications, the Quality
organization still performs many of the conventional quality
functions (e.g., group testing for military products or wafer lot
acceptance). But, true to the philosophy that quality is everyone's job, much of the traditional on-line measurement and
control of quality characteristics is where it belongs - with
the people who make the product. The Quality organization
is there to provide leadership and assistance in the deployment of quality techniques, and to monitor progress.
I
STAGE III
auAlITY
Harris Semiconductor's commitment to supply only top value
integrated circuits has made quality improvement a mandate
for every person in our work force - from circuit designer to
manufacturing operator, from hourly employee to corporate
executive. Price is no longer the only determinant in marketplace competition. Quality, reliability, and performance enjoy
significantly increased importance as measures of value in
integrated circuits.
Quality in integrated circuits cannot be added on or considered after the fact. It begins with the development of capable
process technology and product design. It continues in manufacturing, through effective controls at each process or
step. It culminates in the delivery of products which meet or
exceed the expectations of the customer.
STAGEIV
PRODUCT ~I
OPTIMIZATION
PROCESS
OPTIMIZATION
STAGE I!
PROCESS
CONTROL
STAGE I
PRODUCT
SCREENING
SOPHISTICATION OF
aUAUTVTECHNOLOGY
FIGURE 1. STAGES OF STATISTICAL QUALITY TECHNOLOGY
Harris Semiconductor's quality methodology is evolving
through the stages shown in Figure 1. In 1981 we embarked
on a program to move beyond Stage I, and we are currently
in the transition from Stage III to Stage IV, as more and more
of our people become involved in quality activities. The traditional"quality" tasks of screening, inspection, and testing are
being replaced by more effective and efficient methods, putting new tools into the hands of all employees. Table 1 illustrates how our quality systems are changing to meet today's
needs.
Designing for Manufacturability
Assuring quality and reliability in integrated circuits begins
with good product and process design. This has always
been a strength in Harris Semiconductor's quality approach.
We have a very long lineage of high reliability, high performance products that have resulted from our commitment to
design excellence. All Harris products are designed to meet
the stringent quality and reliability requirements of the most
demanding end equipment applications, from military and
space to industrial and telecommunications. The application
of new tools and methods has allowed us to continuously
upgrade the design process.
Each new design is evaluated throughout the development
cycle to validate the capability of the new product to meet the
end market performance, quality, and reliability objectives.
The validation process has four major components:
10-3
1. Design simulation/optimization
2. Layout verification
3. Product demonstration
4. Reliability assessment.
Harris Quality
TABLE 1. TYPICAL ON·LlNE MANUFACTURING/QUALITY FUNCTIONS
AREA
Wafer Fab
MANUFACTURING
CONTROLS
FUNCTION
• JAN Sell·Audit
• Environmental
· Room/Hood Particulates
X
X
X
• Temperature/Humidity
• Water Quality
• Product
· Junction Depth
· Sheet Resistivities
· Defect Density
·
·
X
X
X
X
X
X
Critical Dimensions
Visual Inspection
Lot Acceptance
X
X
X
X
X
X
• Process
· Film Thickness
· Implant Dosages
· Capacitance Voltage Changes
· Conlormance to Specification
X
X
X
X
X
• Equipment
· Repeatability
Profiles
X
X
X
X
X
X
X
·
Assembly
QA/QC MONITOR
AUDIT
Calibration
Preventive Maintenance
X
• JAN Self·Audit
Environmental
Room/Hood Particulates
• Temperature/Humidity
• Water Quality
·
X
X
• Product
· Documentation Check
- Dice Inspection
·
·
·
-
·
·
·
X
X
Wire Bond Pull Strength/Controls
Ball Bond Shear/Controls
Die Shear Controls
Post·BondlPre-Seal Visual
Fine/Gross Leak
PIND Test
Lead Finish Visuals, Thickness
Solderability
X
X
X
X
• Process
Operator Quality Performance
Saw Controls
-
·
·
·
·
·
·
·
Die Attach Temperatures
Seal Parameters
Seal Temperature Profile
Sta·Bake Profile
Temp Cycle Chamber Temperature
ESD Protection
Plating Bath Controls
Mold Parameters
10·4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Harris Quality
TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS (Continued)
AREA
Test
MANUFACTURING
CONTROLS
FUNCTION
X
• JAN Self-Audit
• Temperature/Humidity
X
• ESD Controls
X
• Temperature Test Calibration
X
• Test System Calibration
X
X
• Test Procedures
• Control Unit Compliance
X
• Lot Acceptance Conformance
X
X
X
• Group A Lot Acceptance
Probe
• JAN Self-Audit
Burn-In
• Wafer Repeat Correlation
X
• Visual Requirements
• Documentation
X
X
X
X
• Process Performance
X
X
X
• JAN Self·Audit
• Functionality Board Check
X
• Oven Temperature Controls
X
X
X
• Procedural Conformance
Brand
• JAN Self·Audit
QCI Inspection
• ESD Controls
X
X
• Brand Permanency
X
X
• Temperature/Humidity
X
• Procedural Conformance
X
• JAN Self-Audit
X
• Group B Conformance
X
• Group C and D Conformance
X
Harris designers have an extensive set of very powerful
Computer-Aided Design (CAD) tools to create and optimize
product designs (see Table 2).
TABLE 2. HARRIS I.C. DESIGN TOOLS
PRODUCTS
DESIGN STEP
QA/QC MONITOR
AUDIT
ANALOG
DIGITAL
Functional
Simulation
Cds Spice
Cds Spice
Verilog
Parametric
Simulation
Cds Spice
Monte Carlo
Cds Spice
Schematic Capture
Cadence
Cadence
Functional Checking
Cadence
Cadence
Rules Checking
Cadence
Cadence
Parasitic Extraction
Cadence
Cadence
Special Testing
Harris Semiconductor offers several standard screen flows to
support a customer's need for additional testing and reliability
assurance. These flows include environmental stress testing,
burn-in, and electrical testing at temperatures other than
+25 0 C. The flows shown on pages 9-6 and 9-7 indicate the
Harris standard processing flows for a Commercial linear part
in PDIP Package. In addition, Harris can supply products
tested to customer specifications both for electrical requirements and for nonstandard environmental stress screening.
Consult your field sales representative for details.
10-5
Harris Semiconductor Standard Processing Flows
COMMERCIAL
PROBEIDICE
PREPARATION
HIGH/ROOM
TEMP
PROBE TEST
VISUAL INSPECTION
MODIFIED
MIL-STD-883
METHOD 2010
CONDITION B
WITH QC MONITOR
ASSEMBLY (1)
•
*
DIE ATTACH
CONTROL
OPERATION
QUALITY MONITOR
DIE MOUNT
YES
MOUNT CURE CONTROL
YES
QUALITY DIE ATTACH
CONTROL (SPC)
YES
*
WIRE BOND
CONTROL
POST BOND
VISUAL
WIRE BOND
*
POST BOND INSPECTION
(RTPC)
*
MOLD CONTROL
LEAD FINISH
CONTROL
YES
QUALITY WIRE BOND
CONTROL (SPC)
QUALITY POST BOND
INSPECTION
MOLDING
YES
YES
AS APPLICABLE
YES
MOLD CONTROL (SPC)
YES
BOTTOM CODE
YES
POST MOLD CURE
YES
TRIMlFORMlDERAIL
YES
SINGULATED SOLDER DIP
YES
100% VISUAL INSPECTION
YES
LOAD SHIPPING TUBES
YES
*
*
QA LOT ACCEPTANCE
YES
QA DOCUMENTATION
INSPECTION
YES
(1) Example for a PDlP Package Part
10-6
I
Harris Semiconductor Standard Processing Flow (Continued)
COMMERCIAL'
TEST (2)
•
*
ACIDC SINGLE
INSERTION TEST
CAPABILITY;
HIGHILOW TEMP
OPERATION
QUALITY MONITOR
100% ELECTRICAL TEST
YES
TOP BRAND
YES
PRE·BURN·IN ELECTRICAL
TEST
BURN·IN
QUALITY
LOT ACCEPTANCE
PDIP LEAD
SCANNING
IF APPLICABLE
BURN·IN
IF APPLICABLE
POST BURN·IN
ELECTRICAL TESTS
IF APPLICABLE
APPLY BURN·IN PDA
IF APPLICABLE
*
QC PRESHIP LOT
ACCEPTANCE TEST
YES
100% LEAD SCANNING
YES
PACKING
YES
-*
QC PRESHIP LOT
ACCEPTANCE
INSPECTION
YES
FINAL DATA REVIEW
YES
(2) Example for a Linear Part in PDIP Package
10·7
Harris Quality
TABLE 3. SUMMARIZING CONTROL APPLICATIONS
FAB
·
Diffusion
. Junction Depth
- Sheet Resistivities
Oxide Thickness
Implant Dose Calibration
Uniformity
-
• Photo Resist
Critical Dimension
Resist Thickness
Etch Rates
• Thin Film
Film Thickness
. Uniformity
Refractive Index
Film Composition
-
.
"-
-
Measurement Equipment
- Critical Dimension
Film Thickness
4 Point Probe
Ellipsometer
-
-
ASSEMBLY
·-
Pre-Seal
Die Prep Visuals
Yields
Die Attach Heater Block
Die Shear
Wire Pull
Bali Bond Shear
Saw Blade Wear
Pre-Cap Visuals
--
• Measurement
XRF
Radiation Counter
Thermocouples
- GM-Force Measurement
• Post-Seal
Internal Package Moisture
Tin Plate Thickness
PIND Defect Rate
Solder Thickness
Leak Tests
Module Rm. Solder Pot Temp.
Seal
Temperature Cycle
--
--
-
TEST
--
Failures
-- Monitor
Lead Strengthening Quality
HandlersiTest System
Defect Pareto Charts
Lot % Defective
ESD Failures per Month
- After Burn-In PDA
OTHER
·
IQC
Vendor Performance
Material Criteria
Quality Levels
-
·
·-
Environment
Water Quality
Clean Room Control
Temperature
Humidity
IOC MeasuremenVAnalysis
XRF
ADE
- 4 Point Probe
Chemical Analysis Equipment
-
-
-
Controlling and Improving the
Manufacturing Process - SPC/DOX
Statistical process control (SPC) is the basis for quality control
and improvement at Harris Semiconductor. Harris manufacturing people use control charts to determine the normal variabilities in processes, materials, and products. Critical
process variables and performance characteristics are measured and control limits are plotted on the control charts.
Appropriate action is taken if the charts show that an operation is outside the process control limits or indicates a nonrandom pattern inside the limits. These same control charts are
powerful tools for use in reducing variations in processing,
materials, and products. Table 3 lists some typical manufacturing applications of control charts at Harris Semiconductor.
SPC is important, but still considered only part of the solution.
Processes which operate in statistical control are not always
capable of meeting engineering requirements. The conventional way of dealing with this in the semiconductor industry
has been to implement 100% screening or inspection steps to
remove defects, but these techniques are insufficient to meet
today's demands for the highest reliability and perfect quality
performance.
Harris still uses screening and inspection to "grade" products
and to satisfy specific customer requirements for burn-in, multiple temperature test insertions, environmental screening,
and visual inspection as value-added testing options. However, inspection and screening are limited in their ability to
reduce product defects to the levels expected by today's buyers. In addition, screening and inspection have an associated
expense, which raises product cost. (See Table 4).
TABLE 4. APPROACH AND IMPACT OF STATISTICAL
QUALITY TECHNOLOGY
STAGE
I
Product
Screening
II
Process
Control
·
Limited Quality
• Stress and Test
• Defective Prediction • Costly
• After-The-Fact
• Statistical Process
Control
• Identifies Variability
Reduces Costs
RealTime
• Just-In-Time
Manufacturing
··
·
• Minimizes Variability
• Before-The-Fact
Design of Experiments
• Process Simulation
III
Process
Optimization
IV
Product
• Design for Producibility
Optimization
Product Simulation
10-8
IMPACT
APPROACH
·
·
·
Insensitive to Variability
Designed-In Quality
• Optimal Results
Harris Quality
Harris engineers are, instead, using Design of Experiments
(DOX) , a scientifically disciplined mechanism for evaluating
and implementing improvements in product processes,
materials, equipment, and facilities. These improvements
are aimed at reducing the number of defects by studying the
key variables contrOlling the process, and optimizing the
procedures or deSign to yield the best result. This approach
is a more time-consuming method of achieving quality perfection, but a better product results from the efforts, and the
basic causes of product nonconformance can be eliminated.
SPC, DOX, and design for manufacturability, coupled with
our 100% test flows, combine in a product assurance
program that delivers the quality and reliability performance
demanded for today and for the future.
Average Outgoing Quality (AOQ)
Average Outgoing Quality is a yardstick for our success in
quality manufacturing. The average outgoing electrical
defective is determined by randomly sampling units from
each lot and is measured in parts per million (PPM). The
current procedures and sampling plans outlined in JEDEC
STD 16, MIL-STD-883 and MIL-I-38535 are used by our
quality inspectors.
The focus on this quality parameter has resulted in a continuous improvement to less than 100 PPM, and the goal is to
continue improvement toward 0 PPM.
Training
The basis of a successful transition from conventional quality
programs to more effective, total involvement is training.
Extensive training of personnel involved in product manufacturing began in 1984 at Harris, with a comprehensive devel-
opment program in statistical methods. Using the resources
of Harris statisticians, private consultants, and internally
developed programs, training of engineers, supervisors, and
operators/technicians has been an ongoing activity in Harris
Semiconductor.
Over the past years, Harris has also deployed a comprehensive training program for hourly operators and supervisors in
job requirements and functional skills. All hourly manufacturing employees participate (see Table 5).
Incoming Materials
Improving the quality and reducing the variability of critical
incoming materials is essential to product quality enhancement, yield improvement, and cost control. With the use of
statistical techniques, the influence of silicon, chemicals,
gases and other materials on manufacturing is highly
measurable. Current measurements indicate that results are
best achieved when materials feeding a statistically
controlled manufacturing line have also been produced by
statistically controlled vendor processes.
To assure optimum quality of all incoming materials, Harris
has initiated an aggressive program, linking key suppliers
with our manufacturing lines. This user-supplier network is
the Harris Vendor Certification process by which strategic
vendors, who have performance histories of the highest
quality, participate with Harris in a lined network; the vendor's
factory acts as if it were a beginning of the Harris production line.
SPC seminars, development of open working relationships,
understanding of Harris' manufacturing needs and vendor
capabilities, and continual improvement programs are all part of
the certification process. The sole use of engineering limits no
longer is the only quantitative requirement of incoming materials.
TABLE 5. SUMMARY OF TRAINING PROGRAMS
COURSE
AUDIENCE
TOPICS COVERED
SPC, Basic
Manufacturing Operators,
Non-Manufacturing
Personnel
Harris Philosophy of SPC, Statistical Definitions, Statislical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts
SPC, Intermediate
Manufacturing Supervisors,
Technicians
Harris Philosophy of SPC, Statistical Definitions, Statistical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts, Distributions,
Measurement Process Evaluation, Introduction to Capability
SPC, Advanced
Manufacturing Engineers,
Manufacturing Managers
Harris Philosophy of SPC, Statistical Definitions, Statistical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts, Distributions,
Measurement Process Evaluation, Advanced Control Charts, Variance Component Analysis, Capability Analysis
Design of Experiments
(DOX)
Engineers, Managers
Factorial and Fractional Designs, Blocking DeSigns, Nested Models, Analysis
of Variance, Normal Probability Plots, Statistical Intervals, Variance Component Analysis, Multiple Comparison Procedures, Hypothesis Testing, Model
Assumptions/Diagnostics
Regression
Engineers, Managers
Simple Linear RegreSSion, Multiple Regression, Coefficient Interval Estimation, Diagnostic Tools, Variable Selection Techniques
Response Surface
Methods (RSM)
Engineers, Managers
Steepest Ascent Methods, Second Order Models, Central Composite Oesigns, Contour Plots, Box-Behnken Designs
10-9
Harris Quality
Specified requirements include centered means, statistical
control limtts, and the requirement that vendors deliver their
products from their own statistically evaluated, in-control manufacturing processes.
In addition to the certification process, Harris has worked to
promote improved quality in the performance of all our qualified
vendors who must meet rigorous incoming inspection crtteria
(see Table 6).
TABLE 6. INCOMING QUALITY CONTROL MATERIAL QUALITY CONFORMANCE
MATERIAL
Silicon
·.
Equipment Capability Control Charts
- Oxygen
Resistivity
• Resistivity
• Crystal Orientation
Dimensions
··
•
•
•
•
• Control Charts Related to
Enhanced Gettering
Total Thickness Variation
Total Indicated Reading
Particulates
• Certificated of Analysis for all Critical Parameters
Edge Conditions
-
Taper
Thickness
Total Thickness Variation
Backside Criteria
• Oxygen
• Control Charts from On-Line Processing
• Carbon
ChemicalslPhotoresistsl
Gases
• Certificate of Conformance
• Chemicals
- Assay
Major Contaminants
• Certificate of Analysis on all Critical Parameters
• Molding Compounds
- Spiral Flow
Thermal Characteristics
• Control Charts
Assay
Contaminants
Water
Selected Parameters
• Certificate of Conformance
• Control Charts from On-Line Processing
-
-
• Gases
Impurities
-
·-
Photoresists
Viscosity
Film Thickness
Solids
Pinholes
• Control Charts
Assay
Contaminants
-
Thin Film Materials
VENDOR DATA REQUIREMENTS
INCOMING INSPECTIONS
-
• Control Charts on
Photospeed
Thickness
- UV Absorbance
Filterability
Water
- Contaminants
• Control Charts from On-Line Processing
• Assay
• Selected Contaminants
• Control Charts
Assay
- Contaminants
Dimensional Characteristics
-
• Certificate of Analysis for all Critical Parameters
• Certificate of Conformance
Assembly Materials
• Visual Inspection
Physical Dimension Checks
·
·
·
• Certificate of Analysis
·
• Glass Composition
• Bondability
Intermetallic Layer Adhesion
• Ionic Contaminants
• Thermal Characteristics
Lead Coplanarity
··
,
• Certificate of Conformance
Process Control Charts on Outgoing Product Checks
and In-Line Process Controls
Plating Thickness
Hermeticity
10-10
Harris Quality
Calibration Laboratory
Another important resource in the product assurance system
is a calibration lab in each Harris Semiconductor operation
site. These labs are responsible for calibrating the electronic,
electrical, electro/mechanical, and optical equipment used in
both production and engineering areas. The accuracy of
instruments used at Harris is traceable to a national standards. Each lab maintains a system which conforms to the
current revision of MIL-STD-45662, 'Calibration System
Requirements."
Each instrument requiring calibration is assigned a calibration
interval based upon stability, purpose, and degree of use. The
equipment is labeled with an identification tag on which is
specified both the date of the last calibration and of the next
required calibration. The Calibration Lab reports on a regular
basis to each user department. Equipment out of calibration is
taken out of service until calibration is performed. The Quality
organization performs periodic audits to assure proper control
in the using areas. Statistical procedures are used where
applicable in the calibration process.
Manufacturing Science - CAM, JIT, TPM
Just In Time (JIT)
The major focus of JIT is cycle time reduction and linear production. Significant improvements in these areas result in
large benefits to the customer. JIT is a part of the Total Quality
Management philosophy at Harris and includes Employee
Involvement, Total Quality Control, and the total elimination of
waste.
Some key JIT methods used for improvement are sequence
of events analysis for the elimination of non-value added activities, demand/pull to improve production flow, TQC check
points and Employee Involvement Teams using root cause
analysis for problem solving.
JIT implementations at Harris Semiconductor have resulted in
significant improvements in cycle time and linearity. The benefits from these improvements are better on time delivery,
improved yield, and a more cost effective operation.
JIT, SPC, and TPM are complementary methodologies and
used in conjunction with each other create a very powerful
force for manufacturing improvement.
Total Productive Maintenance (TPM)
In addition to SPC and DOX as key tools to control the product and processes, Harris is deploying other management
mechanisms in the factory. On first examination, these tools
appear to be directed more at schedules and capacity. However, they have a significant impact on quality results.
Computer Aided Manufacturing (CAM)
CAM is a computer based inventory and productivity
management tool which allows personnel to quickly identify
production line problems and take corrective action. In addition, CAM improves scheduling and allows Harris to more
quickly respond to changing customer requirements and
aids in managing work in process (WIP) and inventories.
The use of CAM has resulted in significant improvements in
many areas. Better wafer lot tracking has facilitated a number of process improvements by correlating yields to process
variables. In several places CAM has greatly improved
capacity utilization through better planning and scheduling.
Queues have been reduced and cycle times have been
shortened - in some cases by as much as a factor of 2.
The most dramatic benefit has been the reduction of WIP
inventory levels, in one area by 500%. This results in fewer
lots in the area and a resulting quality improvement. In wafer
fab, defect rates are lower because wafers spend less time in
production areas awaiting processing. Lower inventory also
improves morale and brings a more orderly flow to the area.
CAM facilitates all of these advantages.
TPM or Total Productive Maintenance is a specific methodology which utilizes a definite set of principles and tools focusing on the improvement of equipment utilization. It focuses on
the total elimination of the six major losses which are equipment failures, setup and adjustment, idling and minor stoppages, reduced speed, process defects, and reduced yield. A
key measure of progress within TPM is the overall equipment
effectiveness which indicates what percentage of the time is a
particular equipment producing good parts. The basic TPM
principles focus on maximum equipment utilization, autonomous maintenance, cross functional team involvement, and
zero defects. There are some key tools within the TPM technical set which have proven to be very powerful to solve long
standing problems. They are initial clean, P-M analysis, condition based maintenance, and quality maintenance.
Utilization of TPM has shown significant increases in utilization on many tools across the Sector and is rapidly becoming
widespread and recognized as a very valuable tool to improve
manufacturing competitiveness.
The major benefits of TPM are capital avoidance, reduced
costs, increased capability, and increased quality. It is also
very compatible with SPC techniques since SPC is a good
stepping stone to TPM implementation and it is in turn a good
stepping stone to JIT because a high overall equipment effectiveness guarantees the equipment to be available and operational at the right time as demanded by JIT.
10-11
Harris Reliability
The reliability operations for Harris Semiconductor are consolidated into three locations; in Palm Bay, Florida, and Research
Triangle Park, North Carolina, for integrated circuits products,
and Mountaintop, Pennsylvania for Power Discrete Products.
This consolidation brought the reliability organizations
together to form a team that possesses a broad cross section
of expertise in:
The facilities are well equipped and manned with highly
trained and disciplined analysts. The reliability facilities are
JAN certified and certified by a host of customers including
major automotive and telecommunications companies.
• Custom Military
Qualification activnies at Harris begin with the in-depth qualification of new wafer processes. These process qualifications
focus on the use of test vehicles to characterize wearout
mechanisms for each process. These data are used to establish design ground rules for each process to eliminate wearout
failure during the useful life of the product. Products designed
within the established ground rules are qualified individually
prior to introduction. New package configurations are qualified
individually prior to being available for new products. Harris
qualification procedures are specified via controlled documentation.
• Automotive ASICs
• Har!;h Environment Plastic Packaging
• Advanced Methods for Design for Reliability (DFR)
• Strength in Power Semiconductor
• ChemicaVSurface Analysis Capabilities
The reliability focus is customer satisfaction (external and
internal) and is accomplished through the development of
standards, performance metrics and service systems. These
major systems are summarized below:
• A process and product development system which
emphasizes getting new products to market over product
design. Uses empowered cross functional development
teams.
• Standard test vehicles (96 in all) for process characterization of wearout failure mechanisms using conventional
stresses (for modeling FITs/MTTF) and wafer level reliability characterization during development.
• Common qualification standards and philosophy for all
sites and developments.
• Matrix monitor standard - a reliability monitoring system
for products in production to insure ongoing reliability and
verification of continuous improvement.
• Field return failure analysis system deployed world wide to
track and expedite root cause analysis and irreversible
corrective actions in a timely manner for our customers.
The system is called by the team name PFAST, Product
Failure Analysis Solution Team. Failure analysis sites are
located in Brussels, Mountaintop, Palm Bay, Singapore,
Kuala Lumpur, and Tokyo. In order to optimize our
response time to the customer all locations are networked
for optimum communication, trend analysis, and performance tracking.
Integrated circuits reliability home base is in Palm Bay, Florida. This new facility has consolidated the reliability organization of the standard products divisions reliability group from
Palm Bay, Florida; Somerville, New Jersey; Santa Clara, California, and the Military and Aerospace Division in Palm Bay,
Florida. This facility contains
ProcesS/Product/Package Qualifications
Product/Package Reliability Monitors
Many of the accelerated stress-tests used during initial reliability qualification are also employed during the routine monitoring of standard production product. Harris' continuing
reliability monitoring program consists of three groups of
stress tests, labeled Matrix I, II and III. As an example, Table 7
outlines the Matrix tests used to monitor plastic packaged
CMOS Logic ICs in Harris' Malaysia assembly plant, where
each wafer fab technology is sampled weekly for both Matrix I
and II. Matrix I consists of highly accelerated, short duration
(48 hours or less) tests, which provide real-time feedback on
product reliability. Matrix II consists of the more traditional,
longer term stress-tests, which are similar to those used for
product qualification. Finally, Matrix III, performed monthly on
each package style, monitors the mechanical reliability
aspects of the package. Any failures occurring on the Matrix
monitors are fully analyzed and the failure mechanisms identified, with corrective actions obtained from Manufacturing and
Engineering. This information along with all of the test results
are routinely transmitted to a central data base in Reliability
Engineering, where failure rate trends are analyzed and
tracked on an ongoing basis. These data are used to drive
product improvements, so as to ensure that failure rates are
continuously being reduced over time.
TABLE 7. PLASTIC PACKAGED CMOS LOGIC ICS MALAYSIA
RELIABILITY MONITORING TESTS.
MATRIX I
TEST
Bias Life
CONDITIONS
DURATION
SAMPLE
+175°C
48 Hours
40
+145°C, 85% RH
20 Hours
40
• A 9,000 square foot reliability analYSis laboratory,
HAST
• An 8,000 square foot reliability stress testing facility,
• A 5,000 square foot analytical (chemistry/surface analysis)
laboratory,
• A 3,000 square foot of engineering office space.
10-12
Harris Reliability
TABLE 7. PLASTIC PACKAGED CMOS LOGIC ICS MALAYSIA
RELIABILITY MONITORING TESTS (Continued)
MATRIX II
TEST
The system and procedures define the processing of product being returned by the customer for analYSis performed by
Product Engineering, Reliability Failure Analysis anellor
Quality Engineering. This system is designed for processing
·sample" returns, not entire lot returns or lot replacements.
CONDITIONS
DURATION
SAMPLE
Bias Life
+125°C
1000 Hours
50
Dynamic Life
+125°C
1000 Hours
50
+lI5OC, 85% RH
1000 Hours
50
Goals: quick, accurate response, uniform deliverable (consistent quality) from each site, traceability.
15PSIG,+121°C,
100% RH
192 Hours
50
The PFAST system is summarized in the following steps:
Storage Life
+l50oC
1000 Hours
50
Temp. Cycle
-65OC to +150"C
1000 Cycles
50
Thermal Shock
-65°C to +150"C
1000 Cycles
50
Biased Humidity
Autoclave
The philosophy is that each site analyzes its own product.
This applies the local expertise to the solutions and helps
toward the goal of quick turn time.
1) Customer calls the sales rep about the unit(s) to return.
2) Fill out PFAST Action Request - see the PFAST form in
this section. This form is all that is required to process a
Field Return of samples for failure analysis. This form
contains essential information necessary to perform root
cause analysis. (See Figure 2).
3) The units must be packaged in a manner that prevents
physical damage and prevents ESD. Send the units and
PFAST form to the appropriate PFAST controller. This
location can be determined at the field sales office or rep
using "Iook-up'"tables in the PFAST document.
MATRIX III
TEST
CONDITIONS
SAMPLE
Solderability
MIL-5TD 88312003
15
Lead Fatigue
MIL·STD 88312004
15
Brand Adhesion
MIL·STD 88312015
20
(UL-94 Vertical Burn)
5
Flammability
4) The PFAST controller will log the units and route them to
ATE testing for data log.
5) Test results will be reviewed and compared to customer
complaint and a decision will be made to route the failure
to the appropriate analytical group.
6) The customer will be contacted with the ATE test results
Field Return Product Analysis System
and interim findings on the analysiS. This may relieve a
line down situation or provide a rapid disposition of material. The customer contact is valuable in analytical process to insure root cause is found.
The purpose of this system is to enable Harris' Field Sales
and Quality operations to properly route, track and respond
to our customers' needs as they relate to product analysis.
The Product Failure Analysis Solution Team (PFAST) consists of the group of people who must act together to provide
timely, accurate and meaningful results to customers on
units returned for analysis. This team includes the salesman
or applications engineer who gets the parts from the customer, the PFAST controller who coordinates the response,
the Product or Test Engineering people who obtain characterization anellor test data, the analysts who failure analyze
the units, and the people who provide the ultimate corrective
action. It is the coordinated effort of this team, through the
system described in this document that will drive the Customer responsiveness and continuous improvement that will
keep Harris on the forefront of the semiconductor business.
7) A report will be written and sent directly to the customer
with copies to sales, rep, responsible individuals with corrective actions and to the PFAST controller so that the
records will capture the closure of the cycle.
8) Each report will contain a feedback form (stamped and
preaddressed) so that the PFAST team can assess their
performance based on the customers assessment of
quality and cycle time.
9) The PFAST team objectives are to have a report in the
customers hands in 28 days, or 14 days based on agreements. Interim results are given real-time.
10-13
I
Harris Reliability
1IJ~68Bl§
Customer
Request #
Analysis #
PFAST ACTION REQUEST
Date:
ORIGINATOR
CuSTOMER
LoCATION/PHONE
No.
DEVICE TYPE/PART
No. SAMPLES
loCATION
No.
PURCHASE ORDER
RETURNED
No.
QUANTITY RECEIVED
THE COMPUlTENESS AND TIMELY RESPONSE OF THE EVALUATION IS DIRECTLY RElATED TO THE COMPLETENESS
OF THE DATA PROVIDED. PLEASE PROVIDE All.. PERTINENT DATA. ATTACH ADDmONAL SHEETS IF NECESSARY.
DETAllS OF REJEcr
TYPE OF PROBLEM
(Wben: appropriate serialize •• its aDd apeelfy (or eaeb)
1- [] INCOMING INSPECTION
TEsT CONDmONS RELATING TO FAILURE
[] TEsTER USED (MFGR/MODEL)
[] TEsT TEMPERATURE
[] TEsT TIME: [] CONTINUOUS TEsT
[] ONE SHOT (f
SEC)
[] DESCRIPTION OF ANY OBSERVED CONOmON TO
[] 100% SCREEN
[] SAMPLE INSPECTION
No. TEsTED
No. OF REmers
ARE RESULlS REPRESENTATIVE OF PREVIOUS LOTS?
DYES
D NO
D BRIEF DESCRIPTION OF EVALUATION
AND RESULlS ATTACHED
2. [] IN PROCESS/MANUFACTURING FAILURE
D BOARD CHEcKOUT
[] SYSTEM CHEcKOUT
D FAILED ON TuRN-ON
D FAILED AFTER
HOURS OPERATION
WAS UNIT RETESTED UNDER INCOMING INSPECTION
[] NO
CONDmONS?
DYES
D BRIEF DESCRIPTION OF HOW FAILURE WAS ISOLATED
TO COMPONENT ATTACHED
3. D FiELD FAILURE
FAILED AFTER
HOURS OPERATION
EsTIMATED FAILURE RATE _ _% PER 1000 HOURS
--
--
=__
WHICH FAILURE APPEARS SENsmVE:
1.[] DC FAILURES
--
2. []
--
ENoUSER
LocATION
AMBIENT TEMPERATURE
C
MIN.
C
MAx.
C
REI... HUMIDITY
%
D END USER FAILURE CORRESPONDENCE ATTACHED
ADDRESS OF FAILING LocATION (IF APPLICABLE)
--
ACTION
REQUESTED BY
CUSTOMER
SPECIFIC ACTION REQUESTED
IMPACT OF FAILED UNilS ON CuSTOMER'S SITUATION:
[] OPENS [] SHORTS D LEAKAGE [] STRESS
[] POWER DRAIN [] INPUT LEVEL [] OUTPUT LEVEL
[] LisT OF FORCING CONDmONS AND MEASURED
RESULlS FOR EACH PIN IS ATTACHED
[] POWER SUPPLY SEQUENCING ATTACHED
ACFAlLURES
LIsT FAILING CHARACTERISTICS
---
CUSToMER CONTAClS WITH SPECIFIC KNoWLEOOE OF RElEClS
NAME
PosmoN
PHONE
3. []
4. D
ATTACHED:
[] LIsT OF POWER SUPPLY AND DRIVER LEVELS
(Include pictures of waveforms).
[] LIsT OF OUTPUT LEVELS AND LOADING CONDmONS
[] INPUT AND OUTPUT TIMING DIAGRAMS
[] DESCRIPTION OF PATTERNS USED
(If not standard patterns, give very complete
description including address sequence).
PROM PROGRAMMING FAILURES
ADDRESS OF FAILURES
PROGRAMMER USED (MFG/MoDEIJREV. No.)
PHYSICAl/AssEMBLY RElATED FAILURES
[] SEE COMMENlS BELOW D SEE ATTACHED
Addltlonal Comments:
FIGURE 2. PFAST ACTION REQUEST
10-14
Harris Reliability
INSfRUcnONS FOR COMPLrnNG PFAST AcnON REOUEST FORM
The purpose of this form is to help us provide you with a more accurate, complete, and timely response to failures which may occur.
Accurate and complete information is essential to ensure that the appropriate corrective action can be implemented. Due to this need
for accurate and complete information, requests without a completed PFAST Action Request form will be returned.
Source of Problem:
This section requests the product flow leading to the failure. Mark an 'X' in the appropriate boxes up to and including the step which
detected the failure. Also mark an 'X' in the appropriate box under ARE RESULTS REPRESENTATIVE OF PREVIOUS WTS?
to indicate whether this is a rare failure or a repeated problem.
Example 1. No incoming electrical test WIlli performed, the
units were installed onto boards, the boards functioned
correctly for two hours and then 1 unit failed. The
customer rarely has a failure due to this Harris device.
Example 2. 100 out of the SOO units shipped were tested
at incoming and all passed. The units were installed into
boards and the boards passed. The boards were installed
into the system and the system failed immediately when
turned 00. There were 3 system failures due to this part.
The customer frequently has failures of this Harris device.
The 3 units were not retested at incoming.
SOURCE OF PROBLEM
SOURCE OF PROBLEM
xqUKC or CYellI t. die boa. pnmlkd)
(&rcl die ICq.uce or CYU. II di. bol.CII provided)
(Ealer di.
1. VISUAlJMEcHANICAL
\. VISUAl./MECHANlCAL
DESCRIBE
o DESCRIBE
o
•
2. INCOMING TEsT
o
2. INCOMING Tfsr
NOT PERfORMED
0100%=
SAMPLE=
No. TEsTED
No. OF REmcrs
ARE RESULTS REPRESENTATIVE OF PREVIOUS LDTS?
0100%=
--
How MANY UNITS FAILED?
L
3.
•
•
12-
FAILED AFTER
HOtIRS OF TESJ1NG
WAS UNlT RETESTED AT INCOMING INSPECnON?
5.
NO
ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS?
NO
•
o
TIS
NO
4. FIELD FAILURE
FAILED AFTEJl _ _ HOURS OPE.RATION
FAILED AFTER _ _ HOURS OPEJlAnON
EsTIMATED FAILURE ItATE _ _~ Pet
-- ·C
•
OTIS
4. FIELD FAILURE
END USet
MIN.
Omet
.ll!...-
IN PROCESSiMAmJFAC11JIUNG FAIWRE
NO
ARE RESULTS REPRESENTATIVE OF PREVIOUS ~?
OTIS
OF REmcrs
A&E RESULTS REPIlESEJron'ATIVE OF PREVIOUS LDTS?
• TIS
o NO
• BoAlUl Tfsr
• SYS'JEM Tfsr
How MANY UNn'S FAllED? ~
-1-
FAILED AFTER
HOtIRS OF TESJ1NG
WAS UNIT RETfSTED AT INCOMING INSPE'CIlON?
OTIS
NOT PERFORMED
SAMPLE TfsrED
No. TEsTED 1.2JL No.
--
o NO
IN PROCESSiMAmJFAcnnuNG FAlWRE
• BoAlUl Tfsr
o SYSTEM Tfsr
OTIS
3.
o
•
LocATION
AVE.
--
"C
MAx.
EsTIMATED FAILURE RATE _ _~Pet
END USet
MIN.
S. Omet
-- ·C
--
locATION
·C
AVE.
--
·C
MAx.
--
·C
Action Requested by Customer:
This section should be completed with the customer's expectations. This information is essential for an appropriate response.
Reason for Electrical Reject:
This section should be completed if the type of failure could be identified. If this information is contained in attached customer
correspondence there is no need to transpose onto the PFAST Action Request form.
PFAST REQUlREMENTS
The value of returning failing products is in the corrective actions that are generated. Failure to meet the following requirements can
cause an erroneous conclusion and corrective action; therefore, failure to meet these requirements will result in the request being
returned. Contact the local PFAST Coordinator if you have any questions.
Units with confonoal coating should include the coating manufacturer and model. This is requested since the coating must be remOlled
in order to perform electrical or hermeticity testing.
1) Units must be returned with proper ESD protection (ESO..... fe shipping tubes within shielding box/bag or inserted into conductive
foam within shielding box/bag). No tape, paper bags, or plastic bags should be used. This requirement ensures that the devices are
not damaged during shipment back to Harris.
2) Units must be intact (lid not rcmOlled and at least part of eacb package lead present). This requirement is in place since the parts
must be intact in order to perform electrical tesL Also, opening the package can remoyc evidence of the cause for failure and lead to
an incorrect conclusion.
3) Programmable parts (ROMs, PROMS, UVEPROMs, and EEPROMs) must include a master unit witb the same pattern. This
requirement is to provide the pattern SO all failing locations can be identified. A master unit is required if a failure analysis is requested.
FIGURE 2. PFAST ACTION REQUEST (Continued)
10-15
Harris Reliability
Failure Analysis Laboratory
The Failure Analysis Laboratory's capabilities encompass
the isolation and identification of all failure modes/failure
mechanisms, preparing comprehensive technical reports,
and assigning appropriate corrective actions. Research vital
to understanding the basic physics of the failure is also
undertaken.
Failure analysis is a method of enhancing product reliability
and determining corrective action. It is the final and crucial
step used to isolate potential reliability problems that may
have occurred during reliability stressing. Accurate analysis
results are imperative to assess effective corrective
actions. To ensure the integrity of the analysis, correlation
of the failure mechanism to the initial electrical failure is
essential.
A general failure analysis procedure has been established
in accordance with the current revision of MIL-STD-883,
Section 5003. The analysis procedure was designed on the
premise that each step should provide information on the
failure without destroying information to be obtained from
subsequent steps. The exact steps for an analysis are
determined as the situation dictates. (See Figures 3 and 4).
Records are maintained by laboratory personnel and contain data, the failure analyst's notes, and the formal Product
Analysis Report.
complete analytical studies. The capabilities of each area
are shown below.
SPECTROSCOPIC METHODS: Colorimetry, Optical Emission, Ultraviolet Visible, Fourier Transform-Infrared, Flame
Atomic Absorption, Furnace Organic Carbon Analyzer, Mass
Spectrometer.
CHROMATOGRAPHIC METHODS: Gas Chromatography,
Ion Chromatography.
THERMAL METHODS: Differenlial Scanning Colorimetry,
Thermogravimetric Analysis, Thermomechanical Analysis.
PHYSICAL METHODS: Profilometry, Microhardness, Rheometry.
CHEMICAL METHODS: Volumetric, Gravimetric, Specific
Ion Electrodes.
ELECTRON MICROSCOPE: Transmission Electron Microscopy, Scanning Electron Microscope.
X-RAY METHODS: Energy Dispersive X-ray Analysis
(SEM), Wavelength Dispersive X-ray Analysis (SEM), X-ray
Fluorescence Spectrometry, X-ray Diffraction Spectrometry.
Analytical Services Laboratory
SURFACE ANALYSIS METHODS: Scanning Auger Microprobe, Electron Spectroscopy/Chemical Analysis, Secondary Ion Mass Spectrometry, Ion Scattering Spectrometry, Ion
Microprobe.
Harris facilities, engineering, manufacturing, and product
assurance are supported by the Analytical Services
Laboratory. Organized into chemical or microbeam analysis
methodology, staff and instrumentation from both labs
cooperate in fully integrated approaches necessary to
The department also maintains ongoing working arrangements with commercial, university, and equipment manufacturers' technical service laboratories, and can obtain any
materials analysis in cases where instrumental capabilities
are not available in our own facility.
FIGURE 3. NON-DESTRUCTIVE
FIGURE 4. DESTRUCTIVE
10-16
Harris Reliability
where,
Reliability Fundamentals and Calculation
of Failure Rate
I.. = failure rate in FITs (Number fails in 109 device hours)
~
Table 8 below defines some of the more important terminology used in describing the lifetime of integrated circuits.
Xi = # of failures for a given failure mechanism
Of prime importance is the concept of "failure rate" and the
calculation thereof.
i = 1, 2, ...
TDH j
Failure Rate Calculations
~
=Lk
~
r
i-1
-
x.I
£.. TDH j
1
.MX109
~
~ x
AF ij
£..
j= 1
i
=1
I
~
= Total device hours of test time (unaccelerated) for
Life Test j, j
Reliability data may be composed of several different failure
mechanisms and the combining of potentially diverse failure
rates into one comprehensive failure rate is desired. The failure rate calculation is complicated because the failure mechanisms are thermally activated at differing rates. Additionally,
this data is usually obtained on a number of life tests performed at unique stress temperatures. The equation below
accounts for these considerations along with a statistical factor to obtain the upper confidence level (UCL) for the resulting
failure rate.
).,
= # of distinct possible failure mechanisms
k = # of life tests being combined
=1, 2, 3, ...k
AF ij = Acceleration factor for appropriate failure mechanism i 1, 2, ... k
=
M=
x2 (0:, 2r+2)
2
where,
X2 = chi square factor for 2r + 2 degrees of freedom
r total number of failures (l: Xi)
0: = risk associated with UCL;
i.e. 0: (1 00-UCL(%))/1 00
=
=
In the failure rate calculation, Acceleration Factors (AFij) are
used to derate the failure rate from the thermally accelerated
life test conditions to a failure rate indicative of actual use
temperature. Although no standard exists, a temperature of
+55 0 C has been popular. Harris Semiconductor Reliability
Reports will derate to +55 0 C and will express failure rates at
60% UCL. Other derating temperatures and UCLs are
available upon request.
TABLE 8. FAILURE RATE PRIMER
TERMS
DEFINITIONS/DESCRIPTION
Failure Rate ).,
Measure of failure per unit of time. The failure rate typically decreases slightiy over
early life, and then becomes relatively constant over time. The on set of wearout will
show an increasing failure rate, which should occur well beyond useful life. The useful
life failure rate is based on the exponential life distribution
FIT (Failure In Time)
Measure of failure rate in 109 device hours; e.g., 1 FIT = 1 failure in 109 device hours,
100 FITS = 100 failure in 109 device hours, etc.
Device Hours
The summation of the number of units in operation multiplied by the time of operation.
MTTF (Mean Time To Failure)
Mean of the life distribution for the population of devices under operation or expected
lifetime of an individual, MTTF = 1/)." which is the time where 63.2% of the population
has failed. Exampled: For)., = 10 FITS (or 10 E-9/Hr.), MTTF = 1/).,= 100 million hours.
Confidence Level (or Limit)
Probability level at which population failure rate estimates are derived from sample life
test: 10 FITs at 95% UCL means that the population failure rate is estimated to be no
more than 10 FITs with 95% certainty. The upper limit of the confidence Interval is
used.
Acceleration Factor (AF)
A constant derived from experimental data which relates the times to failure at two
different stresses. The AF allows extrapolation of failure rates from accelerated test
conditions to use conditions.
10-17
Harris Reliability
Acceleration Factors
Activation Energy
Acceleration factor is determined from the Arrhenius
Equation. This equation is used to describe physiochemical
reaction rates and has been found to be an appropriate
model for expressing the thermal acceleration of semiconductor failure mechanisms.
The Activation Energy (Ea) of a failure mechanism is determined by performing at least two tests at different levels of
stress (temperature and/or voltage). The stresses will provide the time to failure (t f) for the two (or more) populations
thus allowing the simultaneous solution for the activation
energy as follows:
AF
=
ExplEa
l
(_1_ -_1_)J
k
T use
In
(tl1)
=
C +
In
(tf2)
=
C
+
T stress
By subtracting the two equations, and solving for the activation energy, the following equation is obtained:
where,
AF
Ea
= Acceleration Factor
=
k [In(ltl) - In(tf2 )]
(1fT! - lfT2)
Ea = Thermal Activation Energy (See Table 9)
where,
k = Boltzmann's Constant (8.63 x 10- 5 eVf'K)
Ea = Thermal Activation Energy (See Table 9)
Both Tuse and Tstrass (in degrees Kelvin) include the internal
temperature rise of the device and therefore represent the
junction temperature.
k = Boltzmann's Constant (8.63 x 10-5 eVf'K)
T 1, T2
= Life test temperatures in degrees Kelvin
TABLE 9. FAILURE MECHANISM
FAILURE
MECHANISM
ACTIVATION
ENERGY
SCREENING AND
TESTING METHODOLOGY
CONTROL METHODOLOGY
Oxide Defects
0.3- 0.5eV
High temperature operating life (HTOL) and
voltage stress. Defect density test vehicles.
Statistical Process Control of oxide parameters,
defect density control, and voltage stress testing.
Silicon Defects
(Bulk)
0.3- 0.5eV
HTOL & voltage stress screens.
Vendor statistical Quality Control programs, and
Statistical Process Control on thermal processes.
Highly accelerated stress testing (HAST)
Passivation dopant control, hermetic seal control,
improved mold compounds, and product handling.
Temperature cycling, temperature and mechanical shock, and environmental stressing.
Vendor Statistical Quality Control programs, Statistical Process Control of assembly processes,
proper handling methods.
Test vehicle characterizations at highly elevated temperatures.
Design ground rules, wafer process statistical process steps, photoresist, metals and passivation
Corrosion
0.45eV
Assembly
Defects
0.5 -0.7eV
Electromigration
- AI Une
- Contact
0.6eV
0.geV
Mask Defects!
Photoresist
Defects
0.7eV
Mask FAB comparator, print checks, defect
density monitor in FAB, voltage stress test
and HTOL.
Clean room control, clean mask, pellicles, Statistical Process Control of photoresist/etch processes.
Contamination
1.0eV
C-V stress at oxide/interconnect, wafer FAB
device stress test and HTOL.
Statistical Process Control of C-V data, oxide/interconnect cleans, high integrity glassivation and
clean assembly processes.
Charge Injection
1.3eV
HTOL & oxide characterization.
Design ground rules, wafer level Statistical Process Control and critical dimenSions for oxides.
10-18
Harris Semiconductor
---------------------- - ----=- - -- --
No. TB52
--~-=-~
--Harris Digital
January 1994
ELECTROSTATIC DISCHARGE CONTROL
A GUIDE TO HANDLING INTEGRATED CIRCUITS
This paper discusses methods and materials recommended
for protection of ICs against ESD damage or degradation
during manufacturing operations vulnerable to ESD exposure. Areas of concern include dice prep and handling. dice
and package inspection. packing. shipping. receiving. testing. assembly and all operations where ICs are involved.
All integrated circuits are sensitive to electrostatic discharge
(ESD) to some degree. Since the introduction of integrated
circuits with MOS structures and high quality junctions. safe
and effective means of handling these devices have been of
primary importance.
If static discharge occurs at a sufficient magnitude. 2kV or
greater. some damage or degradation will usually occur. It
has been found that handling equipment and personnel can
generate static potentials in excess of 10kV in a low humidity
environment; thus it becomes necessary for additional measures to be implemented to eliminate or reduce static
charge. Avoiding any damage or degradation by ESD when
handling devices during the manufacturing flow is therefore
essential.
ESD Protection and Prevention Measures
One method employed to protect gate oxide structures is to
incorporate input protection diodes directly on the monolithic
Chip. However. there is no completely foolproof system of
chip input protection in existence in the industry.
In areas where ICs are being handled. certain equipment
should be utilized to reduce the damaging effects of ESD.
Typically. equipment such as grounded work stations. conductive wrist straps. conductive floor mats. ionized air blowers and conductive packaging materials are included in the
IC handling environment. Any time an individual intends to
handle an IC. in any way. they must insure they have been
grounded to eliminate circuit damage.
Grounding personnel can. practically. be performed by two
methods. First. grounded wrist straps which are usually
made of a conductive material. such as Velostat or metal. A
resistor value of 1 megohm (1/2 watt) in series with the strap
to ground completes a discharge path for ESD when the
operator wears the strap in contact with the skin. Another
method is to insure direct physical contact with a grounded.
conductive work surface.
This consists of a conductive surface like Velostat. covering
the work area. The surface is connected to a 1 megohm (1/2
watt) resistor in series with ground.
In addition to personnel grounding. areas where work is being
performed with ICs. should be equipped with an ionized air
blower. Ionized air blowers force positive and negative ions
simultaneously over the work area so that any nonconductors
that are near the work surface would have their static charge
neutralized before it would cause device damage or degradation.
Relative humidity in the work area should be maintained as
high as practical. When the work environment is less than 40%
RH. a static build-up condition can exist on nonconductors
allowing stored charges to remain near the ICs causing possible static electricity discharge to ICs.
Integrated Circuits that are being shipped or transported require
special handling and packaging materials to eliminate ESD
damage. Dice or packaged devices should be in conductive
carriers during all phases of transport and handling. Leads of
packaged devices can be shorted by tubular metalic carriers.
conductive foam or foil.
Do's and Don'ts for Integrated
Circuit Handling
Do's
Do keep paper. nonconductive plastic. plastic foams and films
or cardboard off the static controlled conductive bench top.
Placing devices, loaded sticks or loaded burn-in boards on top
of any of these materials effectively insulates them from ground
and defeats the purpose of the static controlled conductive surface.
Do keep hand creams and food away from static controlled
conductive work surfaces. If spilled on the bench top. these
materials will contaminate and increase the resistivity of the
work area.
Do be especially careful when using soldering guns around
conductive work surfaces. Solder spills and heat from the gun
may melt and damage the conductive mat.
Do check the grounded wrist strap connections daily. Make certain they are snugly fitted before starting work with the product.
Do put on grounded wrist strap before touching any devices.
This drains off any static build-up from the operator.
Do know the ESD caution symbols.
Do remove devices or loaded sticks from shielding bags only
when grounded via wrist strap at grounded work station. This
also applies when loading or removing devices from the antistatic
sticks or the loading on or removing from the burn-in boards.
Copyright © Harris Corporation 1994
10-19
Tech Brief 52
Do wear grounded wrist straps in direct contact with the bare
skin never over clothing.
driver circuits when not grounded. This also applies to burnin programming cards containing ICs.
Do use the same ESD control with empty burn-in boards as
with loaded boards if boards contain permanently mounted
ICs as part of driver circuits.
Don't unload stick on a metal bench top allowing rapid discharge of charged devices.
Do insure electrical test equipment and solder irons at an
ESD control station are grounded and only uninsulated
metal hand tools be used. Ordinary plastic solder suckers
and other plastic assembly aids shall not be used.
Don't touch leads. Handle devices by their package even
though grounded.
Don't allow plastic "snow or peanut" polystyrene foam or
other high dielectric materials to come in contact with
devices or loaded sticks or loaded burn-in boards.
Do use ionizing air blowers in static controlled areas when
the use of plastic (nonconductive) materials cannot be
avoided.
Don't allow rubber/plastic floor mats in front of static controlled work benches.
Don'ts
Don't solvent-clean devices when loaded in antistatic sticks
since this will remove antistatic inner coating from sticks.
Don't allow anyone not grounded to touch devices, loaded
sticks or loaded burn-in boards. To be grounded they must
be standing on a conductive floor mat with conductive heel
straps attached to footwear or must wear a grounded wrist
strap.
Don't touch the devices by the pins or leads unless
grounded since most ESD damage is done at these points.
Don't handle devices or loaded sticks during transport from
work station to work station unless protected by shielding
bags. These items must never be directly handled by anyone
not grounded.
Don't use freon or 'chlorinated cleaners at a grounded work
area.
Don't wax grounded static controlled conductive floor and
bench top mats. This would allow build-up of an insulating
layer and thus defeating the purpose of a conductive work
surface.
Don't touch devices or loaded sticks or loaded burn-in
boards with clothing or textiles even though grounded wrist
strap is worn. This does not apply if conductive coats are
worn.
Don't allow personnel to be attached to hard ground. There
must always be 1 megohm series resistance (1/2 watt
between the person and the ground).
Don't touch edge connectors of loaded burn-in boards or
empty burn-in boards containing permanently mounted
R
Recommended Maintenance Procedures
Daily:
Perform visual inspection of ground wires and terminals on
floor mats, bench tops, and grounding receptacles to ensure
that proper electrical connections via 1 megohm resistor (1/2
watt) exist.
Clean bench top mats with a soft cloth or paper towel dampened with a mild solution of detergent and water.
Weekly:
Damp mop conductive floor mats to remove any accumulated dirt layer which causes high resistivity.
Annually:
Replace nuclear elements for ionized air blowers.
Review ESD protection procedures and equipment for
updating and adequacy.
Static Controlled Work Station
The figure below shows an example of a work bench properly equipped to control electro-static discharge. Note that
the wrist strap is connected to a 1 megohm resistor. This
resistor can be omitted in the setup if the wrist strap has a 1
megohm assembled on the cable attached.
R
...,. CONDUCTIVE WRIST
STRAP
CONDUCTIVE BENCH TOP
WRIST STRAP GROUND
LEAD IS ATTACHE DTO
CONDUCTIVE BEN CHTOP
ESD WARNING SYMBOLS
Don't use antistatic sticks for more than one throughput process. Used sticks should not be reused unless recoated.
I
I
--, CONDUCTIVE FLOOR MAT
I: ;,:.;'0\'~~ILD!N~ ,F~O?R,: ,
u
,<;<:
"
R
GROUND, I••• COLD WATER
PIPE OR EQUIVALENT
10-20
R=1 MEGOHM
"
'J
OS p,....-----------I 11
PACKAGING INFORMATION
PAGE
DSP PACKAGE SELECTION GUIDE. . . . .. . . ... . . . ... .... ... .. . . . .. . .... . . . .. . . . ... . .. . . . . .. . .
11·3
PACKAGE OUTLINES... . .. .. . . ... . . . .. . . . .. . . . ... .... .. . .. . .. .. . .... . . . .. . . . .. . . .. . .. . . .. .
11·4
METRIC PLASTIC QUAD FLATPACK (MQFP) PACKAGES. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
11·4
PLASTIC LEADED CHIP CARRIER (PLCC) PACKAGES. .... . . ... . .... ..... . .. .. . . . . .. . .. . . . . ... .
11·6
SMALL OUTLINE PLASTIC (SOIC) PACKAGES.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
11·7
DUAL·IN·LlNE PLASTIC (PDIP) PACKAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11·8
CERAMIC PIN GRID ARRAY (CPGA) PACKAGES. . . .. . .... . . ... . .. .. ..... . . .... . . . ... .. . . . . ....
11·9
TAPE AUTOMATED BONDING (TAB) PACKAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
11·14
TAPE AUTOMATED BONDING (TAB) SUGGESTED LEAD FORM DIMENSIONS.. . ........ . .... .. . .. . .
11·16
11·1
DSP Package Selection Guide
Using the Selection Guide:
The first character of each entry indicates the package type, while the number preceding the decimal point details the pack·
age lead count. Except for CPGA and TAB packages, the decimal point and succeeding numbers relate to the package body
dimensions (e.g .. 14 x 20 14mm x 20mm; .95 950 mil sq.; .3 300 mils. The entire entry indicates the table containing
the appropriate package dimensions (e.g. 24 lead PDIP dimension are detailed in Table E24.3). The index on page 11·1 lists
page numbers for MQFP, PLCC, SOIC, PDIP, CPGA and TAB tables.
=
PART NUMBER
=
MQFP
HMA510
=
SOIC
PLCC
PDIP
G68.A
N68.95
G68.A
N68.95
G68.A
HMA51 0/883
HMU161883
G68.A
HMU17
HMU17/883
G68.A
HSP43124
M28.3
Q100.14x20
E28.6
N84.1.15
G84.A
N84.1.15
G85.A
N84.1.15
G84.A
HSP431681883
G84.A
HSP43216
HSP43220
Q100.14x20
HSP43220/883
HSP43481
G68.A
N68.95
G68.A
HSP43881
N84.1.15
G85.A
HSP43881/883
G85.A
Q100.14x20
G85.A
N84.1.15
HSP43891/883
G85.A
HSP45102
M28.3
HSP45106
N84.1.15
HSP451 081883
N84.1.15
HSP45116
Q160.28x28
HSP45116A
Q160.28x28
E28.6
G85.A
G85.A
G145.A
HSP45116/883
G145.A
HSP45240
N68.95
G68.A
N84.1.15
G85.A
HSP45240/883
G68.A
HSP45256
HSP45256/883
HSP48212
G85.A
Q64.14x14
N68.95
HSP48410
N84.1.15
G84.A
HSP4841 0/883
N84.1.15
G84.A
HSP48901
HSP48908
S84.A
G84.A
HSP434811883
HSP43891
TAB
G68.A
HMU16
HSP43168
CPGA
N68.95
Q100.14x20
N68.95
G68.A
N84.1.15
G84.A
HSP489081883
G84.A
HSP50016
N44.65
HSP9501
N44.65
G48.A
HSP~520
M24.3
E24.3
HSP9521
M24.3
E24.3
11·3
S156.A
Package Outlines
Metric Plastic Quad Flatpack (MQFP) Packages
Q64.14x14 (JEDEC M0-108BD-2ISSUEA)
64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
,--t-----ii~~!B;;;I·1
INCHES
,,
,,
,,
:
~
e
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
.
0.130
.
3.30
·
Al
0.004
0.010
0.10
0.25
A2
0.100
0.120
2.55
3.05
·
B
0.012
0.018
0.30
0.45
6
Bl
0.012
0.016
0.30
0.40
·
0
0.667
0.687
16.95
17.45
3
4,5
01
0.547
0.555
13.90
14.10
E
0.667
0.687
16.95
17.45
3
El
0.547
0.555
13.90
14.10
4,5
L
0.026
0.037
0.65
·
0.95
N
64
64
e
0.032BSC
0.80BSC
7
·
Rev. 0 1194
NOTES:
1. ContrOlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M·1982.
3. Dimensions 0 and E to be determined at seating plane ~.
4. Dimensions 01 and El to be determined at datum plane
M'
0.1310.17
0.00510.00.
E!B.
5. Dimensions 01 and El do not Include mold protrusion.
Allowable protrUSion is 0.25mm (0.010 inch) per side.
6. Dimension B does not Include dambar protrUSion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
T
BASE METAL
WITH PLATING 0.1310.23
0.00510.009
11·4
7. "N" is the number of terminal positions.
Package Outlines
Metric Plastic Quad Flatpack (MQFP) Packages (Continued}
Q1 00.14x20 (JEDEC M()'loaCC-l ISSUE A)
100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES
~
~ ~--------
r- - - - e
PIN 1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.134
3.40
0.010
0.25
-
-
Al
-
-
A2
0.100
0.120
2.55
3.05
-
B
0.009
0.015
0.22
0.38
6
Bl
0.009
0.013
0.22
0.33
-
D
0.904
0.923
22.95
23.45
3
Dl
0.783
0.791
19.90
20.10
4,5
E
0.667
0.687
16.95
17.45
3
El
0.547
0.555
13.90
14.10
4,5
L
0.026
0.037
0.65
-
-
0.95
N
100
100
7
e
0.026BSC
O.65BSC
ND
30
30
NE
20
20
-
Rev. 0 1194
Q160.28x28 (JEDEC M()'10BDD-l ISSUE A)
160 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
-
0.160
4.07
Al
0.010
-
0.25
A2
0.125
0.144
3.17
3.67
-
B
0.009
0.015
0.22
0.38
6
Bl
0.009
0.013
0.22
0.33
-
D
1.219
1.238
30.95
31.45
3
4,5
NOTES
-
-
Dl
1.098
1.106
27.90
28.10
E
1.219
1.238
30.95
31.45
3
El
1.098
1.106
27.90
28.10
4,5
L
0.026
0.037
0.65
-
0.95
N
160
160
e
0.026BSC
0.65BSC
7
Rev. 0 1194
NOTES:
1. ContrOlling dimension: MILUMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI YI4.5M-I982.
3. Dimensions D and E to be determined at seating plane ~.
4. Dimensions Dl and El
to be determined at datum plane ~.
5. Dimensions Dl and El do not Include mold protrusion.
Allowable protrusion Is 0.25mm (0.010 Inch) per side.
6. Dimension B does not Include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 Inch) total.
7. "N" Is the number of terminal positions.
11-5
Package Outlines
Plastic Leaded Chip Carrier (PLCC) Packages
kt:~~~l~ IT! h~f"·'·
0.042 (1.07)
0.048(1.22)
iN (1) IDENTIFIER
..-j
\
'f1
~
I
0.042 (1.07)
0.056 (U2)
0.050 (1.27) TP
r·· ~
\....,..0
~
+
IrEl
~
~
~.'
0.020 (0.51) MAX
3PLCS
N44.65 (JEDEC MS-018 ISSUE A)
0.004(0.10)IC I 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.026 (0.64) R
INCHES
MILLIMETERS
-
D2IE2
0.090
0.120
2.29
3.04
~
0
0.685
0.695
17.40
17.65
-
01
0.650
0.656
16.51
16.66
3
~ D2IE2
D2
0.291
0.319
7.40
8.10
4,5
;
~::
~::: ~:::
~:::
'~ -= b'~1--l~ IA.,
VIEW "A"
E2
0.020(0.51)
0.291
N
MIN
0.319
7.40
44
-
;
4,5
8.10
6
44
Rev. 0 12193
r.c:..
SEATING
L....;:..J PLANE
N68.95 (JEDEC M8-018 ISSUE A)
68 LEAD PLASnC LEADED CHIP CARRIER PACKAGE
0.013 (0.33)
-.i 0.021 (0.53)
~12
INCHES
0.025 (0.64)
0.046 (1.14)
MIN
:: NOTES
A1
::.r=tt
D1
D
0.026 (0.66)
0.032 (0.81)
SYM.BOL::' :.: ::
~~_
~
[
it:
10
MILLIMETERS
SYMBOL
MIN
MAX
MIN
A
0.165
0.160
4.20
MIN
VIEW "A"TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
2. Dimensions and toleranclng per ANSI Y14.5M-1982.
3. Dimensions 01 and El do not Include mold protrusions. Allowable mold protrusion Is 0,01 0 Inch (0.25mm) per side.
4. To be measured at seating plane ~ contact point.
Al
0.090
0.120
2.29
3.04
0
0.985
0.995
25.02
25.27
01
0.950
0.958
24.13
24.33
3
D2
0.441
0.469
11.21
11.91
4,5
E
0.985
0.995
25.02
25.27
El
0.950
0.956
24.13
24.33
3
E2
0.441
0.469
11.21
11.91
4,5
N
5. Centerline to be determined where center leads exit plastic body.
NOTES
MAX
4.57
68
68
6
Rev. 0 12193
6. "N" is the numbar of terminal positions.
N84.1.15 (JEOEC M8-018 ISSUE A)
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
Al
0.090
0.120
2.29
3.04
0
1.185
1.195
30.10
30.35
-
01
1.150
1.156
29.21
29.41
3
D2
0.541
0.569
13.75
14.45
4,5
E
1.185
1.195
30.10
30.35
-
El
1.150
1.156
29.21
29.41
3
E2
0.541
0.569
13.75
14.45
4,5
N
84
84
-
6
Rev. 0 12193
11-8
Package Outlines
r
vtj
( Jl
Small Outline Plastic (SOle) Packages
~F
N
1
T
L~I
SEATING PLANE
Al
~~Jnll
1 r-
hX4s"
/-.J
e~1
~~1'
B -lal
ktH 0.25(0.010) @Ic IA@IB®I
INCHES
SYMBOL
2H3H H~
r-£B-D-j
M24.3 (JEDEC M5-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
!1iI_.dIBijl
0.10(0.004)
I
~L
c
MILLIMETERS
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
-
MAX
MIN
9
B
0.013
0.020
0.33
0.51
C
0.0091
0.0125
0.23
0.32
-
0
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
J
MIN
0.05BSC
1.27BSC
-
H
0.394
0.419
10.00
10.65
h
0.010
0.029
0.25
0.75
5
L
0.Q16
0.050
0.40
1.27
6
8"
0"
N
a.
24
24
0"
7
8°
NOTES:
Rev. 0 12/93
1. Symbols are defined in the "MO Series Symbol Usf in Section
2.2 of Publication Number 95.
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
INCHES
3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
SYMBOL
4. Dimension "E" does not Include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
A
5. The chamfer on the body is optional. If It Is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured O.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
MILLIMETERS
MAX
MIN
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
0
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
MIN
0.05BSC
MAX
1.27BSC
NOTES
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.Q16
0.050
0.40
N
a.
28
0°
127
28
8°
0"
6
7
8°
Rev. 0 12/93
11-7
Package Outlines
Dual-In-Line Plastic (PDIP) Packages
E24.3 (JEDEC M~01·AF ISSUE D)
24 LEAD NARROW BODY DUAL-IN·UNE PLASTIC PACKAGE
,~-CDt
INCHES
SYMBOL
MAX
MIN
A
MILUMETERS
MIN
0.210
MAX
NOTES
5.33
4
4
E1
NOTES:
e
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.240
0280
6.10
7.11
0.100 BSC
2.54 BSC
0.300 BSC
7.62 BSC
0.430
2. Dimensioning and toleranclng per ANSI Y14.5M-1982.
L
3. Symbols are defined In the "MO Series Symbol List" In Section
2.2 of Publication No. 95.
0.115
N
0.150
2.93
24
6
10.92
7
3.81
4
9
24
4. Dimensions A, A 1 and L are measured with the package seated
In JEDEC seating plane gauge GS·3.
Rev. 0 12193
5. 0, 01, and E1 dimensions do not Include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 Inch
(025mm).
leAl
5
6. E and
are measured with the leads constrained to be perpendicurafto datum
@:].
E28.6 (JEDEC MS-01'-AB ISSUE B)
28 LEAD DUAL·IN·UNE PLASTIC PACKAGE
INCHES
SYMBOL
7. ea and 8c are measured at the lead tips with the leads unconstrained. ec must be zero or greater.
MIN
MAX
A
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 Inch (025mm).
9. N Is the maximum number of terminal positions.
10. Comer leads (1, N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 -1.14mm).
MILUMETERS
MIN
0.250
A1
0.015
A2
0.125
MAX
NOTES
6.35
4
4
0.39
0.195
3.18
4.95
0.558
B
0.014
0.022
0.356
B1
0.030
0.070
o.n
1.n
C
0.008
0.015
0.204
0.381
1.565
8
o
1.380
01
0.005
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
L
0.100 BSC
2.54BSC
O.600BSC
15.24BSC
0.115
0.700
0.200
28
5
5
0.13
I
N
39.7
35.1
2.93
28
6
17.78
7
5.08
4
9
Rev. 0 12193
11·8
Package Outlines
Ceramic Pin Grid Array (CPGA) Packages
G48.A
48 LEAD CERAMIC PIN GRID ARRAY PACKAGE
INCHES
MIN
MAX
MIN
MAX
A
-
-
-
-
-
Al
0.080
0.120
2.03
3.05
3
8
b
0.016
0.0215
0.41
0.55
0.Q16
0.020
0.41
0.51
-
b2
0.040
0.060
1.02
1.52
4
-
2.03
-
20.07
20.57
C
-
0.80
0
0.790
0.810
E
A
----;-+=-r-....,.....,
I~I
SECTION B-B
0.7ooBSC
0.790
0.810
20.57
20.07
-
0.7ooBSC
17.78 BSC
-
e
0.100 BSC
2.54BSC
6
k
-
-
-
-
L
0.090
0.110
2.29
2.79
0
0.40
0.060
1.02
1.52
SI
N
1.27 BSC
O.050BSC
-
-
M
b
I
17.78 BSC
El
S
"~
NOTES
bl
01
SEE
NOTE 7
MILLIMETERS
SYMBOL
-
1
8
64
-
5
10
-
-
8
-
64
2
NOTES:
1. "M" represents the maximum pin matrix size.
2. "N" represents the maximum allowable number of pins. Number
of pins and location of pins within the matrix is shown on the
pinout listing in this data sheet.
3. Dimension "AI" includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity up.
Dimension does not include heatsinks or other attached
features.
SEATING PLANE
AT STANDOFF
k
4. Standoffs are intrinsic and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimensionsO.
5. Dimension "0" applies to cavity-up configurations only.
6. All pins shall be on the 0.100 inch grid.
7. Datum C is the plane of pin to package Interface for both cavity
up and down configurations.
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
have a radius or chamfer.
9. Corner shape (chamfer, notch, radiUS, etc.) may vary from that
shown on the drawing. The index comer shall be clearly unique.
10. Dimension OS" is measured with respect to datums A and B.
11. Dimensioning and tolerancing per ANSI YI4.5M-1982.
12. Controlling Dimensions: Inch.
13. Lead Finish: Type C.
14. Materials: Compliant to MIL-I-38535.
11-9
Package Outlines
Ceramic Pin Grid Array (CPGA) Packages (Continued)
1I
E
I_...o;--_ _ _
~r ;
G68.A MIL·STI).1835 CMGA3-PN (P·AC)
68 LEAD CERAMIC PIN GRID ARRAY PACKAGE
I±l ..~I -,
]I------'J
INCHES
-
-(~ @@@@@@@@@@I-f++-+--.--
T
@@@@@@@@@@@@
@@@@@@@@@@@@
@@@
@@@
Is] @@@
@@@
l-L-e--:-:::,@ :o--@=-o__@@@
+
E1
E
'@@@
@@@
@@@
@@@
@@@
@@@
@@@@@@@@@@@@
@@@@@@@@@@@@
@~ @@@@Iq>@@ @@I-{(0T-+--''-t -l f--c
-- Iw
-
G84.A MIL-ST[)'1835 CMGA3-PN (P.AC)
84 LEAD CERAMIC PIN GRID ARRAY PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.215
0.345
5.46
8.76
-
AI
0.070
0.145
1.78
3.68
3
8
b
0.016
0.0215
0.41
0.55
bl
0.016
0.020
0.41
0.51
-
b2
0.042
0.058
1.07
1.47
4
C
-
0.080
-
2.03
0
1.140
1.180
28.96
29.97
-
E
L INDEX CORNER
SEE NOTE 9
SECTION B-B
Olo.ooal c I
IQ I
~~B
A
F=~
--l
F=~,......, I
F=
~ =,--i
A1
==
==
==
~2
0.100BSC
2.54BSC
6
k
0.008 REF
0.20 REF
-
29.97
L
0.120
0.140
3.05
3.56
-
Q
0.040
0.060
1.02
1.52
5
S
O.OOBSC
0.000 BSC
-
0.003
11
-
10
-
0.08
11
121
-
1
121
2
~.L
5. Dimension 00" applies to cavity-up configurations only.
6. All pins shall be on the 0.100 inch grid.
7. Datum C is the plane of pin to package interface for both cavity
up and down configurations.
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
have a radius or chamfer.
9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique •
b
==A
00.030
C A@IB@I
!r+Lf-- --I-- a
00.010
C
00.007
C
.1
e
28.96
4. Standoffs are intrinsic and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimensionsQ.
SECTION A-A
::jP! ..-
-
1.180
3. Dimension "AI" includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity up.
Dimension does not include heatsinks or other attached
features.
~~n~t==::
f
==
A
--
25.4 BSC
1.140
NOTES:
1. "M" represents the maximum pin matrix size.
2. "N" represents the maximum allowable number of pins. Number
of pins and location of pins within the matrix is shown on the
pinout listing in this data sheet.
b
t
L
~
-
25.4 BSC
1.000 BSC
N
SEATING PLANE
;TkSTANDOFF
_
1.000 BSC
E1
E
M
SEE
NOTE 7
I--
01
SI
b1~
NOTES
10. Dimenslon"S" is measured wnh respect to datums A and B.
11. Dimensioning and tolerancing per ANSI YI4.5M-1982.
12. Controlling Dimensions: Inch.
A1
r-
13. Lead Finish: Type C.
14. Materials: Compliant to MIL-I-38535.
11-11
Package Outlines
Ceramic Pin Grid Array (CPGA) Packages (Continued)
G8S.A MIL-ST[)'1835 CMGA3-PN (P-AC)
85 LEAD CERAMIC PIN GRID ARRAY PACKAGE
INCHES
MIN
MAX
MIN
MAX
A
0.215
0.345
5.46
8.76
-
A1
0.070
0.145
1.78
3.68
3
8
b
0.016
0.215
0.41
0.55
0.016
0.020
0.41
0.51
-
b2
0.042
0.058
1.07
1.47
4
C
-
0.080
-
2.03
-
D
1.140
1.180
28.96
29.97
A
---l*=-r--r,
SECTION B-S
I 29.97
25.4BSC
-
e
0.100 BSC
2.54BSC
6
k
0.008 REF
0.20 REF
-
1.140
1.180
28.96
L
0.120
0.140
3.05
3.56
Q
0.040
0.060
1.02
1.52
S1
O.OOOBSC
N
-
0.003
O.OOBSC
-
11
121
-
5
10
-
0.08
11
M
b
25.4BSC
1.000 BSC
S
"~
1.000 BSC
E1
E
SEE
NOTE 7
NOTES
b1
D1
INDEX CORNER
SEE NOTE 9
MILLIMETERS
SYMBOL
1
121
2
NOTES:
1. "M" represents the maximum pin matrix size.
I~I
SEATING PLANE
AT STANDOFF
k
2. "N" represents the maximum allowable number of pins. Number
of pins and location of pins within the matrix is shown on the
pinout listing in this data sheet.
3. Dimension "A 1" includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity up.
Dimension does not include heatsinks or other attached
features.
4. Standoffs are intrinsic and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimensionsQ.
5. Dimension"cr applies to cavity-up configurations only.
6. All pins shall be on the 0.100 inch grid.
7. Datum C is the plane of pin to package Interface for both cavity
up and down configurations.
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
have a radius or chamfer.
9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique.
C
10. Dimension"S" is measured with respect to datums A and B.
11. Dimensioning and tolerancing per ANSI Y14.5M-1982.
12. ContrOlling Dimensions: lneh.
13. Lead Finish: Type C.
14. Materials: Compliant to MIL-I-38535.
11-12
Package Outlines
Ceramic Pin Grid Array (CPGA) Packages (Continued)
G145.A MIL·STD-1835 CMGA7·PN (P·AG)
~ I~ -. ;------IdJl--------;.~I·I_
TI~~ @@@@@ @@@@@-f+H-..-
@@@@@@@@@@@@
@@@@@@@@@@@@
@@@
@@@
Is] @@@
@@@
Lf-e.@@
@@@
t @@@
+
@@@
@@@
@@@
@@@
@@@
@@@@@@@@@@@@
@@@@@@@@@@@@
Ir±
El
E
r- c
rm
'.. ~
-
'- INDEX CORNER
SEE NOTE 9
SEE
NOTE 7
I-
SECTION B-B
Qlo.0081 C 1
Ic:J I
r-- u..cA
-
t=p~
IAlt
::=*A
t
t
r-- k
b2
.
t
- r-Al
0.345
5.46
8.76
·
A1
0.070
0.145
1.78
3.68
3
8
NOTES
b
0.016
0.0215
0.41
0.55
b1
0.016
0.020
0.41
0.51
·
b2
0.042
0.058
1.07
1.47
4
C
.
0.080
2.03
·
D
1.540
1.590
.
El
1.400 BSC
35.5698C
-
e
0.100BSC
2.54BSC
6
k
0.008 REF
0.20 REF
Dl
1.400 BSC
1.540
L
0.120
Q
0.040
8
81
I
39.12
40.38
0.140
3.05
3.56
-
0.060
1.02
1.52
5
-
O.OOBSC
15
225
10
-
0.08
15
-
40.38
35.56B8C
0.00098C
0.003
M
N
1.590
39.12
-
1
225
2
5. Dimension '0' applies to cavity-up configurations only.
6. All pins shall be on the 0.100 inch grid.
7. Datum C is the plane of pin to package interface for both cavity
up and down configurations.
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
have a radius or chamfer.
9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique.
@@@@I-te-lG)-t--'--
+-1
145 LEAD CERAMIC PIN GRID ARRAY PACKAGE
11. Dimensioning and tolerancing per ANSI Y14.5M-1982.
12. ContrOlling Dimensions: Inch.
I--
13. Lead Finish: Type C.
14. MaterialS: Compliant to MIL-I-38535.
Q
11-13
Package Outlines
Tape Automated Bonding (TAB) Packages
S84.A
84 LEAD TAPE AUTOMATED BONDING PACKAGE
INCHES
SYMBOL
MAX
MIN
A
DETAIL "A"
c
MILLIMETERS
MIN
0.034
MAX
NOTES
0.86
b
0.002
0.004
0.05
0.10
2,7
c
0.0010
0.0018
0.025
0.046
2,7
Bl
0.019
0.021
0.47
0.53
5
B2
0.023
0.028
0.60
0.70
5
D
0.559
0.569
14.20
14.45
E
0.562
0.572
14.27
14.53
Dl
0.410
0.420
10.41
10.67
El
0.409
0.419
10.39
10.64
3
D2
0.300
0.310
7.62
7.87
4
E2
0.300
0.310
7.62
7.87
4
D3IE3
o.sOOBSC
12.70BSC
D4IE4
0.531 BSC
13.475 BSC
D5IE5
1.061 BSC
3
26.95 BSC
D6
1.372
1.382
34.85
35.10
E6
1244
1.314
31.62
33.37
D7/
0.345
0.351
8.77
8.92
E7
0.344
0.350
8.74
8.89
D8
0.360
0.370
9.14
9.40
E8
0.358
0.368
9.09
9.35
e
0.015 BSC
0.38BSC
2
el
0.016 BSC
0.40 BSC
5
F
0.054
0.057
1.39
G
0.055
0.057
1.40
1.45
1.45
H
1.253 BSC
31.83 BSC
Hl
0.187 BSC
4.75 BSC
aaa
0.003
0.08
NOTES:
1. All dimensioning and tolerancing per ANSI Y14.5M1982.
;H
2. Controlling dimension is MilLIMETERS except for dimensions b, c and e which are in INCHES.
3. Dimensions Dl/El define the package "body size".
4. Dimensions D2IE2 define the maximum allowable dimension between the outside edges of the outermost
leads. This dimension provides necessary clearance
from the OlB window corners for excise operations.
SECTION A·A
5. This dimension applies to all test pads.
6. All lead and test pad arrays shall be arranged in a symmetric configuration with respect to datums D or B-C.
7. Dimensions band c apply to base material only.
8. lead Material: Copper
lead Finish: Gold over nickel underplate
9. Film format and test pads per JEDEC US-001, Ax - 2x.
10. TAB packages shipped in slide carriers per JEDEC
CS-006 with the leads unformed (flat).
11-14
Package Outlines
Tape Automated Bonding (TAB) Packages
(Continued)
S156.A
156 LEAD TAPE AUTOMATED BONDING PACKAGE
INCHES
SYMBOL
MIN
A
r--E7~
~
-.
fA
MAX
MILLIMETERS
MIN
MAX
0.034
NOTES
0.86
b
0.002
0.004
0.05
0.10
2
c
0.0010
0.0018
0.025
0.046
2,7
B1
0.019
0.021
0.47
0.53
5
B2
0.023
0.028
0.60
0.70
5
0
0.559
0.569
14.20
14.45
E
0.562
0.572
14.27
14.53
01
0.429
0.439
10.90
11.15
E1
0.431
0.441
10.95
11.20
3
02
0.380
0.390
9.65
9.90
4
E2
0.380
0.390
9.65
9.90
4
D3IE3
0.500BSC
12.70BSC
D4IE4
0.531 BSC
13.475BSC
D5IE5
1.061 BSC
3
26.95BSC
06
1.372
1.382
34.85
35.10
E6
1.244
1.314
31.62
33.37
07
0.349
0.355
8.87
9.02
E7
0.346
0.352
8.79
8.94
08
0.360
0.370
9.14
9.40
E8
0.367
0.377
9.32
9.57
e
0.010BSC
0.254BSC
2
e1
0.016 BSC
0.40 BSC
5
F
0.054
G
0.055
1.45
H
H1
0.187 BSC
4.75BSC
aaa
0.002
0.05
NOTES:
1. All dimensioning and tolerancing per ANSI Y14.5M1982.
2. Controlling dimension is MILLIMETERS except for dimensions b, c and e which are in INCHES.
3. Dimensions D1/E1 define the package 'body size".
DETAIL "A"
4. Dimensions D2lE2 define the maximum allowable dimension between the outside edges of the outermost
leads. This dimension provides necessary clearance
from the OLB window comers for excise operations.
5. This dimension applies to all test pads.
SECTIONA-A
6. All lead and test pad arrays shall be arranged in a symmetric configuration with respect to datums 0 or B-C.
7. Dimensions b and c apply to bese material only.
8. Lead Material: Copper
Lead Finish: Gold over nickel underplate
9. Film format and test pads per JEDEC US-001, Ax - 2x.
10. TAB packages shipped in slide carriers per JEDEC
CS-006 with the leads unformed (flat).
11-15
Package Outlines
Tape Automated Bonding (TAB) Suggested Lead Form Dimensions
-r--I---
~:~
e
.i
T
Ey
1
01
02
I
1
07 K
J
b
.i
T
c
l::!:~p-G-~"I--.l.
~L--'~+----------~'--~~~
T ~M
1
11-"--'---
:----;a;a.ll R
.. I
s
T
CONSTANT DIMENSIONS
b
1
G
0.003
I
0.475
I
I
H
0.515
I
I
J
0.472
I
I
K
0.512
I
I
L
0.020
I
I
M
0.0114
I
I
c
0.0014
I
I
R
0.0057
I
I
S
0.0224
DEVICE DEPENDENT DIMENSIONS
DEVICE
LEADS
E1
D1
E2
D2
C
e
Ex
Ey
E7
D7
Z
0.025
0.015
0.0545
0.0550
0.348
0.349
0.019
0.032
0.010
0.0256
0.0245
0.350
0.353
0.019
HSP43220
84
0.414
0.415
0.305
0.305
HSP45116
156
0.436
0.434
0.385
0.385
11·16
DS=---~
- - - - - - I
12
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PSG201S
PRODUCT SELECTION GUIDE (1992: 320pp) Key product infonnation on all Harris Semiconductor devices. Sectioned (Analog, Data Acquisition, Digital, Application Specific, Power, Hi-Rei & Rad-Hard,
ASIC) for easy use and includes cross references and alphanumeriC part number index.
DB500B
LINEAR AND TELECOM ICa (1993: 1,312pp) Product specifications for: op amps, comparators, S/H
amps, differential amps, arrays, special analog circuits, telecom ICs, and power processing circuits.
DB301B
DATA ACQUISITION (1994: 1,104pp) Product specifications on AID converters (display, integrating,
successive approximation, flash); D/A converters, switches, multiplexers, and other products.
DB302A
DIGITAL SIGNAL PROCESSING (1993: 380pp) This new edition includes specifications on one- and
two-dimensional filters, signal synthesizers, multipliers, special function devices (such as address sequencers, binary correlators, histogrammer). Includes sections on development tools, application notes
and Quality/Reliability.
DB304
INTELLIGENT POWER ICa (1992: 512pp) Product specifications for low- and high-side switches, half
bridges, AC-DC converters, full bridges, regulators & power supplies, protection circuits, and special function ICs. Includes application notes and Quality/Reliability sections.
DB450C
TRANSIENT VOLTAGE SUPPRESSION DEVICES (1994: 400pp) Product specifications of Harris varistors and surgectors. Also, general informational chapters such as: ·Voltage Transients - An Overview,"
"Transient Suppression - Devices and Principles," ·Suppression - Automotive Transients."
DB223.2
POWER MOSFETa (1992: 1,504pp) Product specifications on MOSFETs (N- and P-channel, logic level,
military and radiation-hardened); IGBTs; Intelligent discretes; power drivers and switches; and ultra-fast
rectifiers. Includes industry replacement guide and application notes.
DB220.1
BIPOLAR POWER TRANSISTORS (1992: 592pp) Technical information on over 750 power transistors
for use in a wide range of consumer, industrial and military applications. Indexing and packaging included.
DB303
MICROPROCESSOR PRODUCTS (1992: 1,156pp) For commercial and military applications. Product
specifications on CMOS microprocessors, peripherals, data communications, and memory ICs. Includes
application notes and Quality/Reliability chapters.
DB309
MCTnGBT/DIODES (1994: 528pp) This databook fully describes Harris Semiconductor's line of MOS
Controlled Thyristors, Insulated Gate Bipolar Transistors (IGBTs) and Power Diodes/Rectifiers. It includes a complete set of datasheets for product specifications, application notes with design details for
specific applications of Harris products, and a description of the Harris Quality and Reliability program.
Analog Military
ANALOG MILITARY (1989: 1,264pp) This databook describes Harris' military line of Linear, Data Acquisition, and Telecommunications circuits.
Digital Military
DIGITAL MILITARY (1989: 680pp) Harris CMOS digitallCs -- microprocessors, peripherals, data communications and memory -- are included in this databook.
NAME: ________________________________
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FAX FORM TO: HARRIS FULFILLMENT
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ATTN: LAURIE MALANTONIO
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Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2014:01:08 16:48:01-08:00
Modify Date : 2014:01:09 01:17:28-08:00
Metadata Date : 2014:01:09 01:17:28-08:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:3dc592fd-f87d-4f5c-9d13-499bc6e570ab
Instance ID : uuid:05865ac2-98b0-47de-a3b8-b104a0a769f6
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 534
EXIF Metadata provided by EXIF.tools