1994_Harris_Intelligent_Power_ICs 1994 Harris Intelligent Power ICs
User Manual: 1994_Harris_Intelligent_Power_ICs
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HARRIS SEMICONDUCTOR
This Intelligent Power ICs Databook represents the full line of Harris Semiconductor
Intelligent Power· products for commercial, industrial and automotive applications
and supersedes previously published Intelligent Power product databooks under the
Harris, GE, RCA or Intersil names. For a complete listing of all Harris Semiconductor
products, please refer to the Product Selection Guide (SPG-201 S; ordering information belOW).
For complete, current and detailed technical specifications on any Harris devices
please contact the nearest Harris sales, representative or distributor office; or direct
literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-25
Melbourne, FL 32901
TEL: 1-800-442-7747
FAX: (407) 724-3937
See Section 14 for Data Sheets Available on AnswerFAX
U.S. HEADQUARTERS
Harris Semiconductor
1301 Woody Burke Road
Melboume, Florida 32902
TEL: (407) 724-3000
EUROPEAN HEADQUARTERS
Harris Semiconductor
Mercure Center
Rue de la Fusee, 100
1130 Brussels, Belgium
TEL: 32224621 11
SOUTH ASIA
Harris Semiconductor H.K. Ltd
13IF Fourseas Building
208-212 Nathan Road
Tsimshatsui, Kowloon Hong Kong
TEL: (852) 723-6339
NORTH ASIA
Harris KK
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-08 Japan
TEL: (81) 3-3345-8911
See our
specs in
CAPS
Copyright C Harris Corporation 1994
(AU Rights Reserved)
Printed in USA, 411994
INTELLIGENT POWER PRODUCTS
Harris Semiconductor is a pioneer in developing and producing advanced Intelligent
Power products for the most demanding commercial, industrial and automotive applications in this world -- and beyond.
This databook fully describes Harris Semiconductor's line of Intelligent Power products. It includes a complete set of data sheets for product specifications, application
notes with design details for specific applications of Harris products, and a description of the Harris quality and high reliability program.
Harris Semiconductor also offers an extensive line of power discrete components.
These devices (MOSFETs, MegaFETs, L2FETs, enhanced-mode insulated gate
bipolar transistors, ruggedized power MOSFETs and advanced discrete) can be
found in the Harris Power MOSFETs and Harris MCTIIGBT/Diodes catalogs.
This book is divided into 15 major sections. Section 1 contains general information.
Sections 2 through 10 cover each major category of devices offered by Harris Intelligent Power. Section 11 provides additional application notes to supplement the data
sheets. Harris Quality and Reliability, Packaging Information, AnswerFAX and Sales
Offices appear in Section 12, 13, 14 and 15, respectively.
It is our intention to provide you with the most up-to-date information on Intelligent
Power Products. For complete, current and detailed technical specifications on any
Harris devices please contact the nearest Harris sales, representative or distributor
office; or direct literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-25
Melbourne, FL 32902
1-800-442-7747
FAX 407-724-3937
See Section 14 for Data Sheets Available on AnswerFAX
Harris Semiconductor products are sold by description only. All specifications in this product guide are
applicable only to packaged products; specifications for die are available upon request. Harris reserves the
right to make changes in circuit design, specifications and other information at any time without prior
notice. Accordingly. the reader is cautioned to verify that Information In this publication Is current before
placing orders. Reference to products of other manufacturers are solely for convenience of comparison
and do not imply total equivalency of design, performance, or otherwise.
INTELLIGENT POWER
INTEGRATED CIRCUITS
FOR COMMERCIAL, INDUSTRIAL & AUTOMOTIVE APPLICATIONS
General Information
Low Side Switches
High Side Switches
Half Bridges
AC to DC Converters
Full Bridges
Regulators/Power Supplies
Protection Circuits
Multiplex Communication Circuits
Special Functions _
I
Application Notes _
Harris Quality and Reliability _
Packaging Information _
How To Use Harris AnswerFAX _
Sales Offices _ _
iii
TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook,
please contact the Field Applications Engineering staff available at one of the following Harris Sales Offices:
UNITED STATES
CALIFORNIA
Costa Mesa ........................ 714-433-0600
San Jose .......................... 408-985-7322
Woodland Hills .•.................... 818-992-0686
FLORIDA
Melbourne ......................... 407-724-3576
GEORGIA
Duluth ......................•...... 404-476-2035
ILLINOIS
Schaumburg ........................ 708-240-3480
MASSACHUSETTS
Burlington .......................... 617-221-1850
NEW JERSEY
Voorhees .......................... 609-751-3425
NEW YORK
Great Neck ......................... 516-829-9441
TEXAS
Dallas ............................. 214-733-0800
INTERNATIONAL
FRANCE
Paris. . . . . . • . . . . . . . . . . . . . . . . . . . .. 33-1-346-54046
GERMANY
Munich ...•....................•.. 49-8-963-8130
HONG KONG
Kowloon ........................... 852-723-6339
ITALY
Milano ............................ 39-2-262-0761
JAPAN
Tokyo ........................... 81-33-345-8911
KOREA
Seoul .....•...................... 82-2-551-0931
SINGAPORE
Singapore ........................... 65-291-0203
UNITED KINGDOM
Camberley ....................... 44-2-766-86886
For literature requests, please contact Harris at 1-800-442-7747 (1-SOO-4HARRIS)
iv
PRODUCT STATUS DEFINITIONS
DEFINITION OF TERMS
DATA SHEET
IDENTIFICATION
PRODUCT STATUS
DEFINITION
Advance Information
Formative or in Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
Pre Production Samples
Available
This datasheet contains preliminary data, and supplementary data will be published at a later date. Harris
Semiconductor Corporation reserves the right to
make changes at any time without notice in order to
improve design and supply the best possible product.
No Identification
Noted
Full Production
This data sheet contains final specifications. Harris
Semiconductor Corporation reserves the right to
make changes at any time without notice in order to
improve design and supply the best possible product.
v
INTELLIGEN
POWERICs
I
Ii.
1
GENERAL INFORMATION
PAGE
GENERAL ORDERING INFORMATION ....................................................... .
1-3
ALPHA NUMERIC PRODUCT INDEX ...................•......................................
1-4
PRODUCT INDEX BY FAMILY ............................................................... .
1-6
APPLICATION INDEX ..................................................................... .
1-9
INTELLIGENT POWER PRODUCTS CROSS REFERENCE LIST ..............................•.....
1-12
1-1
Z
.,JO
liHi
W::s
Za:
WO
CJu.
~
General Ordering Information - - - - - - - .
PRODUCT CODE EXAMPLE
PART NUMBER
2
HIP
TV
o
5
J
T
o
P
T
PACKAGE
VOLTAGE
PREFIX
FAMILY
H: Harris
IP: Intelligent Po_
V: High Voltage
P: PIastlc DIP
Multiply by 10 for C8pab1tity
(I.e. 50 = SOOV
B: SOIC
HNegative (-) Is Used for First
DIgit. Do Not Multiply by 10
M:
S: PowerSIP
(I.e. -6 .. 5V)
PLCC
J: Ceramic DIP
W:Wafer
TOPOLOGY
D: Die
0: Low Side SwItch
1: High Side Switch
2: HaH BrIdge
TEMPERATURE
3: AC/DC
Converters
A: Automotive
(-40"0 to +15O"C)
C: CommercIal
(O"C to +7O"C)
4: Full Bridge
5: RegulatorlPower
Supply
I: IndusIJIaI
(-40"0 to ..asoc)
M: MIDtary
7: Multiplex
Convnunlcatlon Clroult
9: Special Function
(-55"C to +1250 C)
D: EDP
(O"C to ..asoc)
SEQUENTIAL
NUMBER
Based on Order of
Development ()-9
1-3
Alpha Numeric Product Index
PAGE
CA723
Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 15DmA
Without Extemal Pass Transistors. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3
CA723C
Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 15DmA
Without External Pass Transistors. . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . • . . . . . . . . . . . . .
7-3
CA1523
Voltage Regulator Control Circuit for Variable Switching Regulator ...• ,. . . . . . . . . . . . ..
7-11
CA1524
Regulating Pulse Width Modulator. . . . . . . .• .. . . . . .. . . .. . . . .. . . . . . . . . . . . . . . . .. .
7-16
CA2524
Regulating Pulse Width Modulator ........•....•..............• , . . . . . . . . . . . . . .
7-16
CA3020
Multipurpose Wide-Band Power Amps Military. Industrial and Commercial Equipment at
Frequency Up to 8MHz . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . • . . ..
10-3
CA3059
Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . . . .
5-3
CA3079
Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . . . .
5-3
CA3085
Positive Voltage Regulators from 1.7V to 46V at Currents Up to l00mA .. . . • .. . . . .. . . .
7-31
CA3085A
Positive Voltage Regulators from 1.7V to 46V at Currents Up to 100mA .• . . . .. . . . . . . . .
7-31
CA3085B
Positive Voltage Regulators from 1.7V to 46V at Currents Up to 100mA .. " . .. . . . .. . •.
7-31
CA3094
Programmable Power Switch/Amplifier for Control and General Purpose Applications . . ..
10-11
CA3165
Electronic Switching Circuit. • • • • • . . • • . . . . . • . • . . . . . • • . • . • • . . • • • . • . . . . . . . . . . . ..
10-25
CA3228
Speed Control System with Memory. .••. . . .•.•. . .. .••.••. ••• .•• ..•• .•. . . . .. . ..
10-31
CA3242
Quad-Gated Inverting Power Driver For Interfacing Low-Level Logic to High
Current Load. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . • . . • . . . . . . . . . . . . . . . . . . .
2-3
CA3262
Quad-Gated Inverting Power Drivers ................. , ......•..•......... ,. . . .
2-7
CA3262A
Quad-Gated Inverting Power Drivers. . . . . . .•. .. . .. . . . .. . . . .. . . . .• . . . .. . . . .. . . .
2-7
CA3272
Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output.. . . . .. . . .
2-13
2-13
CA3272A
Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output ..........
CA3273
High-Side Driver . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
CA3274
Current Limiting Power Switch With Current Limiter Sense Flag ............ " . . .. . ..
10-40
CA3275
Dual Full Bridge Driver .. . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
6-3
CA3277
Dual 5V Regulator with Serial Data Buffer Interface for Microcontroller
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . • . . .
7-39
CA3282
CMOS Octal Serial Solenoid Driver. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . .
2-20
CA3292A
Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output .... . . . . . .
2-13
CA3524
Regulating Pulse Width Modulator. •. . . . ••. •.. .• .. .. . .•. . . . . .. • .. ••• .. . . . .. . . .
7-16
CDP68HC68S1
Serial Bus Interface. . . • . . . • . . . . • . . . • . • • • • • • • . . • . . • • • • • . . . . • . . . . . . . . • . . . . . . .
9-3
HIP0080
Quad Inverting Power Drivers with Serial Diagnostic Interface. • . . . . . . . . . . . . . . . . • . . . .
2-28
HIP0081
Quad Inverting Power Drivers with Serial Diagnostic Interface. . . . . . . • . . • . . . . . . . . . . . .
2-28
HIP0082
Quad Power Driver with Serial Diagnostic Interface. . . . • . . . . . . . . . . • . . • • . . . . . . . . • • .
2-36
HIP1030
1A High Side Driver with Overload Protection. • . . . . . • . . . . . . . . . . . . . . . . . . . . • . . • . . . .
3-6
HIP1031
Half Amp High Side Driver with Overload Protection.. . . . .. . . . . . . . . .. •• . .. . . . .. . . .
3-10
HIP1090
Protected High Side Power Switch with Transient Suppression. . . . . . . .. . . . .. . . . .. . . .
3-13
HIP2030
30V MCTIIGBT Gate Driver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • • . . . .
4-3
HIP2500
Half Bridge 500V oc Driver. . . . . . .. . . . .. . . . .. . . . . . . . . . . . . . . . . . • .. • . . .. . . . . . . . .
4-10
1-4
Alpha Numeric Product Index
(Continued)
PAGE
HIP4010
Power Full Bridge Driver for Low Vohage Motor Drive with Direction and Brake Control ....... .
HIP4011
Three Phase Brushless DC Motor Controller ..............................•.....
6-7
6-11
HIP4080
80V/2.SA Peak, High Frequency Full Bridge FET Driver..•.••..•............•......
6-14
HIP4080A
80V/2.SA Peak, High Frequency Full Bridge FET Driver......•..........•.....•....
6-28
HIP4081
80V/2.5A Peak, High Frequency Full Bridge FET Driver........................... .
6-41
HIP4081A
80V/2.5A Peak, High Frequency Full Bridge FET Driver........................... .
6-54
HIP4082
80V/l.25A Peak Current Full Bridge FET Driver ................................. .
6-67
HIPS060
Power ControllC Single Chip Power Supply.................•...................
7-47
HIPS061
7 A, High Efficiency Current Mode Controlled PWM Regulator ..•....................
7-53
HIPS062
Power ControllC Single Chip Dual Switching Power Supply ....•......•......•.....
7-73
HIPS063
Power ControllC Single Chip Power Supply..............•.................•....
7-80
Z
...J
O
~~
HIPSSOO
High Voltage IC Half Bridge Gate Driver ...•.........•...••.......•••...........
7-84
HIPS600
Thermally Protected High Voltage Linear Regulator ..........••....••........•....
7-94
Za:
HIP7010
J1850 Byte Level Interface Circuit. ........................................... .
9-17
HIP7020
J1850 Bus Transceiver I/O for Multiplex Wiring .................................. .
--;-".
;,~t$6PS~~·I.1{,gra~~jh
;";: ... , ;...~;,
CA01i31'
Pin
Fairchild
USR712a;312
LM72;1H
Pin
Fairchild
U5R7123393
CA0723CT
Pin
Fairchild
U6A7123393
CA0723CE
Pin
Fairchild
Pin
Fairchild
.!-W23CN
,
CA1$91E
C;A30eeEPin,·.·· . Fairchild
1IA723CA
GA01~3CE
. LM723CN
.CA0723CT
l'
Pin
Signetics
Pin
Signeti(:S
.~in
Texas Instr.
1IA723C4
LM723CH
Pin
Texas I.nstr.
1IA723CN .
CA0723CE
Pin
Philips
CA07230e
Pin
Signetics
1IA723CN
NOtE:'1.-
.. (
COMPETITOR
1IA723CN
CA0723CE
Pin
Texas Instr.
1IA723CN
LM723CN
Pin
Philips
1IA723CN
LM723CN
Pin
Signetics
1IA723CN
LM723CN
Pin
Texas Instr.
J;lA723HC
CA0723CT
Pin
AMD
j)A723HC
LM723CH
Pin
Motorola
pA723HM
CA0723T
Pin
Fairchild
jJA123HM
LM723H
Pin
Fairchild
1IA123ML
CA0723T
Pin
Fairchild
J.lA723ML
LM723H
Pin
Texas Instr.
jJA723MN
CA0723E
Pin
Texas Instr.
j)A723PC
CA0723CE
Pin
Motorola
1IA723PC
LM723CN
Pin
Motorola
j)A780PC
CA3070
Upgrade
Fairchild
j)A787PC
CA3126E
Upgrade
Fairchild
UC1524AJ
CA1524F
Pin
Unitrode
UC1524N
CA1524E
Pin
Unitrode
UC3524N
CA3524E
Pin
Unitrode
UDN2541B
CA3262AE
Pin
Sprague
UDN2547EB
CA3272Q
Pin
Sprague
ULN·2111A
CA2111AE
Pin
Sprague
ULN-2.124A
CA3070
Pin
Sprague
ULNoo2287A
CA3088E
Pin
Sprague
ULN-2289A
CA3089E
Function
Sprague
ULN·2289A
CA3089E
Function
Sprague
ULN-2291M
CAt391E
Pin
Sprague
ULN2111N
CA2111AQ
Pin
Sprague
ULN2212
CA3012
Function
Sprague
ULN3889A
CA3189E
Upgrade
Sprague
VI·7660-2
ICL7660ClV
Pin
Datel
VH660-2
ICL7660SClV
UpgradelPin
Datel
.'.
...
Pin
j)A30891; .
'.'
PIN!
FUNCTION
UPGRADE
Teledyne
U5R1723312
U6A71233.93
HARRIS
PART
NUMBERS
I~~te$ SpecificatiQlls M&o/ Vary
1·16
INTELLIGEN
POWERICs
2
LOW SIDE SWITCHES
PAGE
LOW SIDE SWITCHES SELECTION GUIDE . ................................................... .
2-2
LOW SIDE SWITCHES DATA SHEETS
CA3242
w(I)
QW
Quad-Gated Inverting Power Driver For Interfacing Low-level logic to High
Current load ......................•..•...............•.••......•••.....
2-3
CA3262A, CA3262 Quad-Gated Inverting Power Drivers ...•....................•.........•.....
2-7
CA3272, CA3272A, Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output. ...•...•
CA3292A
2-13
CA3282
CMOS Octal Serial Solenoid Driver ........................................ .
2-20
HIP0080, HIPOO81
Quad Inverting Power Drivers with Serial Diagnostic Interface ....................•
2-28
HIP0082
Quad Power Driver with Serial Diagnostic Interface ............................ .
2-36
2-1
-:I:
(1)(.)
~1::
O~
..J(I)
Low Side Switches Selection Guide
,
TYPE NUMBERS
CA3242
QUAD
CA3262
QUAD
CA3262A
QUAD
CA32n
CA3212A
QUAD
Max. Output Voltage, No Load
50V
60V
60V
60V
32VTyp
(Clamp)
Max. Rated DC Load Current
0.6A
0.1A
0.1A
0.6A
0.6A
0.8Vat 0.6A
0.6Vat 0.6A
0.5Vat 0.6A
O.4Vat 0.5A
0.4VaI0.5A
35V
40V
40V
40V
28V
1.4A
(Latches-Off)
1.6A
1.3A
1.2A
1.2A
Output Thermal Limiting and/or"
Shutdown Protection (Temperature TJ )
No
+155°e
+155OC
+165°e
+165°C
Thermal Shutdown, Hysteresis
No
No
No
1SOC
15°C
Fault Indicator Flag
No
No
No
Yes
Yes
Diagnostic Feedback
No
No
No
No
No
Temperature Range
-400 C to +(Max) °e
105
85
125
125
125
16DIP
16DIP
16 DIP and
28PLCC
28PLCC
28PLCC
BIPOLAR TYPES
Max. VSAT OUtput Voltage
Max. Load Switching Voltage, VCESUS or
VCLAMP Limited
Output Current Limiting and/or
Shutdown Protection
Package
CA3292A
QUAD
TYPE NUMBERS
HIP0080 QUAD
HlPO081 QUAD
HIPOO82 QUAD
CA3282
OCTAL
Max. Oulput Voltage, No Load
36VTyp
(Clamp)
80VTyp
(Clamp)
80VTyp
(Clamp)
32VTyp
(Clamp)
Max. Rated DC Load Current
lA
2A
2A and 5A
lA
MOSFET TYPES
Max.
RoN Output Resistance
1.00 atO.5A
0.50 at lA
0.510 at 2A
1.0OatO.5A
Max. Load Switching Voltage (VCESUS or VCLAMP
Limited)
21V
13V
12V
30V
Output Current Limiting and/or Shutdown Proteclion
1.8A
(Latches-Qlf)
3.SA
(Latches-Off)
2.1A and 5.1A
(Latches-Off)
I.SA
(Latches-Off)
Output Thermal limiting and/or Shutdown Proteclion, TJ
+15000
+15O"C
+165°C (Aag)
No
Thermal Shutdown, Hysteresis
15°C
15°C
150 e
No
Fault Indicator Flag
Yes
Yes
Yes
Yes
Diagnostic Feedback
Yes
Yes
Yes
Yes
Temperature Range -40°e to +(Max) °C
125
125
125
125
28PLCe
15SIP
15 SIP
15SIP
Package
2-2
CA3242
Quad-Gated Inverting Power Driver For
Interfacing Low-Level Logic to High Current Load
April 1994
Features
Description
• Driven Outputs Capable of Switching 600mA Load
Currents Without Spurious Changes In Output State
The CA3242 quad-gated inverting power driver contains four
gate switches for interfacing low-level logic to inductive and
resistive loads such as: relays, solenoids, AC and DC
motors, heaters, incandescent displays, and vacuum fluorescent displays.
• Inputs Compatible with TTL or 5V CMOS Logic
• Suitable for Resistive or Inductive Loads
Output overload protection is provided when the load current
(approximately 1.2A) causes the output VCE(sat) to rise
above 1.3V. A built-in time delay, nominally 25J.!S, is provided
during output turn-on as output drops from Voo to VSAT' That
output will be shut down by its protection network without
affecting the other outputs. The corresponding Input or
Enable must be toggled to reset the output protection circuit.
• Output Overload Protection
• Power-Frame Construction for Good Heat Dissipation
Applications
• Relays
• Solenoids
Steering diodes in the outputs in conjunction with external
zener diodes protect the IC against voltage transients due to
switching inductive loads.
• AC and DC Motors
• Heaters
To allow for maximum heat transfer from the chip, the four
center leads are directly connected to the die mounting pad.
In free air, junction-to-air thermal resistance (ROJA) is SOoCI
W (typical). This coefficient can be lowered by suitable
design of the PC board to which the CA3242 is soldered.
• Incandescent Displays
• Vacuum Ruorescent Displays
Ordering Information
PART NUMBER
CA3242E
TEMPERATURE
RANGE
-40"C to +1 05°C
Pinout
PACKAGE
16 Lead Plastic DIP
Block Diagram
CA3242 (PDIP)
TOP VIEW
TRUTH TABLE
CAUTION: These devices are sensRlve to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
2-3
ENABLE
IN
H
H
L
H
L
H
L
X
H
File Number
OUT
1561.2
wen
OW
-:x:
en(.)
~t::
O~
....len
Specifications CA3242
Absolute Maximum Ratings (Note 1)
Thermal Information
Logic Supply Voltage, Vcc ••••••••••••••••••••••••••••.• 7V
Logic Input Voltage, VIN • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • 15V
Output Voltage, VCEX •.••••••.••..••.••••.•••••••••• 50Voc
Output Sustaining Voltage, VCESUS .•.....•.•.....•.••• 35VDC
Output Current, 10 , •..••.......••..•.•....•.••....•.. 1Aoc
Thermal Resistance
8JA
8JL
Plastic DIP.. • •• • • • •• •• • • •• • •• • • . 600 eIW
Plastic DIP (to Pins 4,5,12,13) • • • • •
12°CIW
Power Dissipation, Po
Up to 60°C •••••••••••.•••••••••••.••••••••••••••• 1.5W
Above 60°C •••••••••••••••••• Derate Linearly at 16.6mWI"C
Up to 900C wlHeat Sink (pC Board) •.••••••••••••••••• 1.5W
Above 900C wlHeat Sink (PC Board) •• Derate Linearly at 25mWI"C
Ambient Temperature Range
Operating •••••••.•••••••••.••••••••••••• -40"C to +1 05°C
Storage ..•.....••.•.•••••.•.••.••••.... -55°C to +150°C
Maximum Junction Temperature, TJ ••••••••••••••••••• +l50oC
Lead Temperature (During Soldering)
At distance 1/16 inch ± 1/32 Inch (1.59 ± 0.79mm) from
case for lOs max ••••••••••••••••••••••••••.••••• +2650 C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications At TA = -400 C to +1 050 C, Vcc = 5V Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
ICEX
VCE = 50V, VIN = O.BV
-
100
IIA
Output Sustaining Voltage
VCE(SUS)
Ic = 100mA, VIN = O.BV
30
-
V
Collector Emitter Saturation Voltage
VCE(SAT)
Ic = 100mA, VIN = 2.4V
0.35
V
0.6
V
O.B
V
O.B
V
±10
IIA
Output Leakage Current
Input Low Voltage
VIL
Input Low Current
IlL
VIN=O.BV
-
Input High Voltage
VIH
Ic=600mA
2
-
V
Input High Current
IIH
Ic = 700mA, VIN = 4.5V
10
IIA
Supply Current ON
IcC(oN)
BO
mA
Supply Current OFF
ICC(OFF)
5
mA
100
IIA
1.B
V
Ic = 400mA, VIN = 2.4V
Ic = 6OOmA, VIN = 2.4V
Clamp Diode Leakage Current
IR
VR =50V
Clamp Diode Forward Voltage
VF
IF= 1A
-
IF= 1.5A
-
2.5
V
Ic = 700mA, Vcc = VIH = 5.5V
Turn-On Delay
\PHL
-
20
jlS
Turn-Off Delay
\PLH
-
30
jlS
NOTE:
1. TA = +25°C, Unless Otherwise Specified
2-4
~
~
f\1
"'"
1\)-
NO"[E:·Allf~stance
GND
values are ko, aU capacitors are in pF.
FtGlffllt,. ~ATlCDlAGRAM OF THECA3242 (SW\tetl.$ECtIONA)
LOW SIDE
SWITCHES
CA3242
CA3242
FIGURE 3. TYPICAL APPLICATIONS FOR THE CA3242 QUAD
FIGURE 2. LOGIC DIAGRAM FOR EACH OUTPUT
S1
R1
LATCH ·1
S2
R2
LATCH-2
S3
R3
LATCH-3
54
R4
LATCH -4
ENABLE
MISC. SWITCHING
APPUCATIONS
FIGURE 5. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER
FIGURE 4. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER
2-6
HARRIS
SEMICONDUCTOR
CA3262A,CA3262
Quad-Gated Inverting Power Drivers
April 1994
Features
Description
•
•
•
•
•
•
•
The CA3262 and CA3262A are used to interface low· level
logic to high current loads. Each Power Driver has four
inverting switches consisting of a non-inverting logic input
stage and an inverting low-side driver output stage. All input
stages have a common enable input. Each output device
has independent current limiting (I LIM) and thermal limiting
(TLIM) for protection from overload conditions. Steering
diodes connected from each output (in pairs) to the Clamp
pins may be used in conjunction with external zener diodes
to protect the IC against overvoltage transients that result
from inductive load switching. To allow for maximum heat
transfer from the chip, all ground pins on the DIP and PLCC
package are directly connected to the mounting pad of the
chip. An integral heat spreading lead frame directly connects
the bond pad and ground leads for good heat dissipation.
Independent Over-Current Umltlng on Each Output
Independent Over-Temperature Umltlng On Each Output
Output Drivers Capable of Switching 700mA Load
Inputs Compatible With TTL or SV CMOS Logic
Suitable For Resistive, Lamp or Inductive Loads
Power-Frame Construction for Good Heat Dissipation
Operational Temperature Ranges
- CA3262A •••••••••••••••••••••• -40oC to +12SoC
- CA3262 •••••••••••••••••••.•••• -40 oC to +8SoC
Applications
System Applications
•
•
•
•
•
•
•
•
•
•
Solenoid
Relay
Light
Steppers
Motors
Displays
Pinouts
Automotive
Appliance
Industrial Control
Robotics
The CA3262 and CA3262A can drive four incandescent
lamp loads without modulating their brilliance when the
·cold" lamps are energized. Outputs may be parallel connected to drive high current loads. The maximum output cur·
rent of each output is determined by the over-current limiting
threshold which is typically 1.2A but may be as low as 0.7A.
CA3262, CA3262A (PDIP)
TOP VIEW
Ordering Information
TEMP. RANGE
PACKAGE
CA3262E
PART NUMBER
-4O"C to +85°C
16 Lead Plastic DIP
CA3262AE
-40oC to +125°C
16 Lead Plastic DIP
CA3262AQ
-40oC to +125°C
28 Lead PLCC
Functional Block Diagram
"""""''''''''''''''''''''''''''''''''''1
Vcco-t-+
,
v+
:
TUM
CA3262A (PlCC)
TOP VIEW
~!i~~~j
GND
GND
OUT 0
IN 0
ot'----::fl~C;:.~
IN C
. - - - -......-+-0 OUT C
o-t----tr)..:l:::;::~
CLAMP
ENABLE
GND
..---_-+0 OUT B
GND
GND
GND
IN B 0-;:---+-1
CLAMP
r-----~~~OUTA
IN A <>i--tf"""""'l~I=:;:~
CAUTION: These devices are senshive to electrostatic discharge. Users should follOw proper I.C. Handling Procedures.
Copyright @Harris Corporation 1994
2-7
File Number
1836.4
CA3262A, CA3262
Vee - - -- - --- ______ -- - - --- -- -- --- -- - -- -- - ---- __
+5V P.S. o·
• v+
11 (18):
,
a. _____ --_
~
:
: OUTD
IND:
e (16)!
,,
,
INC:
TTL OR
CMOS
LOGIC
LEVEL
INPUTS
15 (27):
•
:
2(3)
IN A :
:
1 (2)
L~~i~_~TT
!
.
·
·:
16(28):
~
,,
..... -------- ... -- ... -... -- ..
:
- .. -... ---',
-...-... -... -... -.... -----....-... -------
TRUTH TABLE (Each Output)
ENABLE
IN
OUT
H
H
L
H
L
H
L
X
H
H = High, L = Low, X
LAMP
:,
PINS 4, 5,12 & 13 GROUND (PACKAGE E)
PINS 5-11 & 19-25 GROUND (PACKAGE Q)
PIN #'S IN PARENTHESIS APPLY TO PACKAGE Q
=Don't Care
FIGURE 1. QUAD INVERTING POWER DRIVER (QDR) SHOWN WITH TYPICAL APPLICATION LOADS
Vee
REFERENCE
VOLTAGE
1.2 VOLTS
ENABLE
TO SUBSEQUENT STAGES
FIGURE 2. CA3262A EQUIVALENT SCHEMATIC OF ONE INPUT STAGE
2-8
Specifications CA3262A, CA3262
Absolute Maximum Ratings
Thermal Information
Logic Supply Voltage, Vcc ••••••••••.•.••••••••..•••..• 7.0V
Logic Input Voltage, VIN .••••.••.•••.•...•••..•.....••• 15V
Output Voltage, VCEX •••.••••.•••••.•••.••••••.••••.•• BOV
Output Sustaining Voltage, VCE(SUS) •••.••••••••••.••••••• 40V
Output Transient Current . • • • • • • • • • • . . • • . . . . . . . . . •• (Note 1)
Output Load Current. . • • . . • • . • • . • . . . . • . . • • . • . • . . .• (Note 2)
Storage Temperature Range •.••.•••..••••••• -65°C to + 150°C
Operating Temperature Range
CA3262AE, CA3262AO •..•..••..•.•••••.• -40oC to +125°C
CA3262E •.............•....•....•....••. -400C to +S5°C
Thermal Resistance (Note 3)
CA3262AO •••••..•..•••••••••••••.••.•••••
CA3262E, CA3262AE •••••..•••••••.••••••••
Power Dissipation, Po
CA3262E,CA3262AE
Up to +SOoC (Free Air) .....•••••••••••••••••••••••• 1.5W
Above +BOoC •••.••••••..••.• Derate Linearly at 16.6mWI"C
Up to +90oC With Heat Sink (PC Board) ••••••..••••••• 1.5W
Above +90oC;
With Heat Sink (PC Board) •...••• Derate Linearly at 25mW/oC
CA3262AO
Up to +65°C (Free Air) •.•..••••••••.••••••••••••..• 1.5W
Above +65°C ...••.•••••••••••• Derate Linearly at 23mWI"C
Up to + 105°C with Heat Sink (PC Board) ..•..•••.••..• 1.5W
Above +1050 C;
With Heat Sink (PC Board) ••••••• Derate Linearly at 33mWI"C
Maximum Junction Temperature •••••••.•••.•.••.••••• +150°C
Lead Temperature (Soldering lOs) ••••.•••••••••.••••• +265°C
I
CAUTION: Stresses abo... those listed in 'Absolute Maximum RaUngs' may cause permanent damage to the device. This Is a stress only rating and operatkJn
01 the device at these or any other conditions abo... those indicated In the operaUonaJ secUons 01 this specilicatkJn is not implied.
Wt/)
Electrical Specifications
Output Leakage Current
SYMBOL
lcex
Output Sustaining
Voltage
Vce(SUS)
Collector Emitter
Saturation Voltage
(See Figures 4B & 5B)
VCE(SAl)
TEST CONDITIONS
VCE = 60V, VENABLE = 0.8V
Note 4
VIN = 2V, Vee = 4.75V
Ic = 100rnA
Ic=200mA
Ic=300rnA
Ic=400rnA
Ic=500rnA
Ic=600rnA
Ic = 700mA, TA =-4OOC
Input Low Voltage
Input High Voltage
VIL
VIH
Input Low Current
IlL
VIN =0.8V
Input High Current
IIH
VIN = VENABLE = 5.5V,
Ic=BOOmA
Supply Current,
All Outputs ON,
(See Figures 4A and 5A)
ICC(ON)
Supply Current, All
Outputs OFF,
(See Figures 4A and 5A)
ICC(OFF)
IR
Clamp Diode Forward
Voltage,
(See Figures 40 and 50)
VF
Over Current Limiting
-
VR =60V
IF =lA, VIN = OV
MAX
-
100
4>liLo Irui lour = 500rnA
IUM
VouT =2V,
VIN = 5.5V, VENABLE = 5.5V
2-9
MIN
TYP
MAX
UNrrs
-
lIA
0.6
50
-
-
40
-
-
-
-
0.25
-
0.05
0.15
V
-
0.2
V
0.25
V
02
0.3
V
-
0.4
0.5
V
V
0.75
-
0.5
V
0.8
V
-
-
-
0.4
0.6
0.6
0.8
-
-
2
V
-
V
10
10
lIA
lIA
(Note 4)
55
rnA
-
70
-
-
-
5
-
(Note 4)
5
rnA
-
-
100
-
-
50
IIA
1.7
-
10
10
-
2.1
-
-
-
8
-
0.7
-
(Note 1)
0.7
-
IF =1.5A, VIN = OV
:=1:
0:=
40
2
VIN = 2V, VENABLE = 5.5V,
IOUTA = 250rnA, IOUTB = 250rnA,
IOUTC = 250rnA, IOUTO = 250rnA
TYP
VIN=OV
Clamp Diode Leakage
Current
Turn-On Delay,
(See Figures 4C and 5C)
MIN
t/)CJ
CA3262A
CA3262
PARAMETERS
QW
-:1:
vcc = 5.5V, TA= _40°C to +125°C for CA3262A and Vcc = 5.5V, TA= _40°C to +S5°C for CA3262
Unless Otherwise Specified
-
-
1.7
V
2.1
V
8
115
(Note 1)
A
...It/)
Specifications CA3262A, CA3262
Electrical Specifications
Vcc =5.5V. TA=_40°C to +125°C for CA3262A and Vec =5.5V. TA=-40°C to +85°C for CA3262
Unless Otherwise Specified (Continued)
CA3262
CA3262A
I
PARAMETERS
SYMBOL
TEST CONDITIONS
I MIN TYP MAX I MIN TYP I MAX IUNrrs
DESIGN PARAMETERS
Over Temperature Limiting
155
155
°C
TUM
(Junction Temperature)
Input Capacitance. Input
pF
C1N
3
Enable Capacitance
4.4
pF
CEN
NOTES:
1. The CA3262 and CA3262A have on-chip limiting for transient peak currents. Under short-cIrcuit conditions with voltage applied to the collector
of the output transistor and with the output transistor turned ON. the current will Increase to 1.2A. typical. Over-Current Limiting protects a short
circuit condition for a normal operating range of output supply voltage. During a short cllCult condition. the output driver will shortiy thereafter
(approx. 5ms) go Into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than 2A, each output will
typically withstand a direct short circun up to supply voltage levels of 16V. Excessive dissipation before thermallirniting oocurs may cause darnage to the chip for supply voltages greater than 18V, The CA3262 and CA3262A are rated to withstand peak current cold turn-on conditions
of #168 or #194 lamp loads.
2. The total DC current for the CA3262 and CA3262A with all 4 outputs ON should not exceed the total of (4 X 0.7A + Max. Icc) - 2.85A. This
level of current will slgnificantiy increase the chip temperature due to Increased dissipation and may cause thermal shutdown In high ambient
temperature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed 0.7A but may be subject
to Over-Current Limiting above the IUM min. limn of 0.7A. As a practical limit, no single output should be loaded to more than lA max.
. 3. Normal applications require a surface mount of the 28 lead PLCC package on a PC Board. The package has a power lead frame construction
where ground pins 5 - 11 and 19 - 25 conduct heat from the frame to the PC Board. wnh approximately a 2 square Inch copper erea adjacent
to the ground pins. the thermal resistance on the mounted package may be as low as 3lY'CNV.
4. Icc varies with temperature. Typically, Icc(ON) Is 18mA at +125°C and 41 mA at -40"C. Typically, ICC(OFF) is 22mA at +125°C and 12mA at -40"C.
5. Tested with a switched-off 500mA Load (240 series resistanca). VBA1T = 12V and the outputs (Vcel clamped to +40V maximum with an external zener diode.
-
-
-
-
-
-
-
-
Applications
Typical circun configurations for applying the CA3262 and
CA3262A are shown in the application circuit of Figure 1. To
their rated capabilities. both circuits can be used to drive inductive. resistive and lamp loads. The CA3262A has a lower VSAT
than the CA3262 and is rated for +125OC ambient temperature
applications. The CA3262 data sheet rating is -+&i°C. Otherwise. the protection features described apply to both the
CA3262 and CA3262A
The maximum voltage for full load current switching is the output
sustaining voltage. VCE(SUS) which should not exceed 40 Volts.
To provide a means of over-voltage protection. on-chip steering
diodes are connected from each output to one of two CLAMP
pins. Over-voltage pulses may be generated from inductive load
switching and must be clamped or limited to a peak voltage less
than VCE(SUS). To limit an inductive voltage pulse. a zener diode
should be connected to the appropriate CLAMP pin. When the
voltage pulse exceeds the zener threshold. the excess energy is
dumped to ground via the on-chip steering diode and the external zener diode.
Note that the rate of change of the output current during load
switching is fast. Therefore. even small values of inductance.
including the inductance of a few meters of hook-up wire to
the load Circuit. can generate voltage spikes of considerable
amplitude at the output terminals and may require clamping
to protect the device ratings.
Current-limiting is provided as protection for shorted or overloaded output conditions. Voltage is sampled across a small
metal resistor in the emitter of each output stage. When the
voltage exceeds a preset comparator level. drive is reduced
to the output. Current limiting is sustained unless thermal
conditions exceed the preset thermal shutdown temperature
of +155OC.
If an output is shorted. the remaining three outputs will continue to function normally unless the continued heat spreading is sufficient to raise the junction temperature at any other
output to a level greater than +155OC. High ambient temperature conditions may allow this to happen. The degree of interaction is minimized at chip layout design by separating the
The on-Chip diodes may be used in a free-wheeling mode by output devices. each to a separate corner of the chip.
connecting the CLAMP pins to an external clamp supply
voltage. Zener diode clamp protection is preferred over the As noted. the thermal resistance values of both the DIP and
power supply clamp option. primarily because the power sup- PLCC packages are improved by direct connection of the
plies may be subject to large transient changes; including turn- leads to the chip mounting pad. In free air. the junction-to-air
ON and turn-OFF conditions where non-tracking conditions thermal resistance. 9JA is +60"CIW (typical) for the DIP packbetween supplies could allow forward conduction through the age and +42!>CIW (typical) for the PLCC package. This coeffisteering diodes. For all transient conditions of either method. the cient can be lowered to +40"CIW and +31f'CIW respectively
clamp voltage should greater than the maximum supply voltage by increasing ground copper area on the PC board next to
the ground pins of the IC.
of the switching outputs and less than VCE(SUS)'
2-10
CA3262A, CA3262
la
EACH OF THE ODR OUTPUTS SHOWN IN FIG 31S A
COMPOSITE CIRCUIT WITH OVER-TEMPERATURE
SENSE FOR THERMAL UMmNG " OVER-CURRENT
SENSE TO PROVIDE CURRENT UMlnNG
FIGURE 3. QUAD INVERTING POWER DRIVER (QDR) OUTPUT EQUIVALENT CIRCUIT
Typical Performance Curves
80
~
~ 0.7
SUPPLY VOLTAGE (Vcel- 5.5V
70
-
0.6
~
0.5
z
....... r---...
"'"
I
10
~
VIN - 2V,IoUT :J50mA (EACH)
..........
K
I
I
~
I:
~
I
0
20
40
60
80 100
AMBIENT TEMPERATURE ( °C)
~
:
120
0.3
f.-""
IC· 600mA -
~U
"-
~
,
-20
. ...- /',..
........
- -
IC- 7oomA
(I)
VIN - OV,IoUT- OmA
o
r
~0.4
15
THERMAL SHUTDOWN
-40
:!i
~
SUPPLY VOLTAGE (vccl- 4.7SV
140
FIGURE 4A. TYPICAL SUPPLY CURRENT (PIN 11)
CHARACTERISTICS
0.1
-40
o
20 40 60
80 100
AMBIENT TEMPERATURE ( °C)
-20
120 140
FIGURE 4B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUADGATED INVERTING POWER DRIVER OUTPUT
4
VIN
:t50%
8,10,15,16
(16)(17) (27)(28)
tPliL - VOUT _ _ _ _-,/
-
-
IF-1.5A
I
1,3,6,8
(2) (4) (12) (14)
I
IF-1A
tpLH
o
-40
-20
0
20
40
60
80 100 120
AMBIENT TEMPERATURE (GC)
-40
FIGURE 4C. TYPICAL PROPAGATION DELAY
TIME CHARACTERISTICS
-20
0
20
40
60
80 100 120
AMBIENT TEMPERATURE (GC)
140
FIGURE 4D. TYPICAL CLAMP-DIODE FORWARD
VOLTAGE CHARACTERISTICS
FIGURE 4. TYPICAL CHARACTERISTICS OF THE CA3262E
2-11
CA3262A, CA3262
Typical Performance Curves (Continued)
80
SUPPLY VOLTAGE (Vee)- 4.75
0.7 _ loUT" 600mA
SUPPLY VOLTAGE (Vee)" S.5V
70
a:~
C 60
.s
l-
Z
so
W
a:
a: 40
:::>
(.)
~ 30
Q.
Q.
:::> 20
()
0
11
··
- -_ ............ -_ .......... -..........................
- .·.
.,.................
-~
CAUTION: These devices are sensHive to electrostatic discharge. Users should 101l0w proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994.
2-13
File Number
2223.4
wen
QW
-x:
en"
~I::
O~
.....
en
CA3272, CA3272A, CA3292A
Block Diagram of the CA3272, CA3272A
18
26
ENABLE
1
--0
Vee
:--·,.· .....· .... --.... ---.. --------"".-..1;-..:
~---+'~
:
OUTD:
1.
·•••
.··:•
OUTC:
····•••••
.
.·•
·
···•:
·
•
IND
-
·
L..,;;;;;"r--tJ 0.020
, .... -_ ................ - - ..................................... f
~
12
17
INC
!
•
·
1I.,,;=.r--u 0.020
:
-_ .................. -_ ...................................... _,
2
~---1~~~D
OUlA
•
-
f ...... _ .. _ ...... _ .. _ .. _____ ._ .. ____ • _ .. __ .... .1
·
:
4
INB
!
-
·
........1"""""""1....1
0.020
.·
·
···
··.
··•
··•
•
:
•
•
:
1I.,,;;;;;;..r--u 0.020
OUTB:
27
:
:
:
·
... __ ...... -_ .. --- --.----- ..~--- .. "" .... --!
, ........ _- - - ...... - ... - . - - . - .. _ .......... - - - - - f
:
2
:
OUTA!
28
INA
·
-
NOTE:
THE CA3292A IS EQUIVALENT TO THE
CA3272 AND CA3272A EXCEPT FOR THE
COLLECTOR·TO·BASE ZENER
DIODE ON EACH OUTPUT (Z,J.
USED AS AN OVER·VOLTAGE CLAMP TO
PROTECT THE OUTPUT WHEN SWITCHING
INDUCTIVE LOADS
f __________________ .. ________ .. ____ ~
1
~
GROUND PINS
5·11.18·25
TRUTH TABLE
INPUT
27
1
ENABLE
28
1
ENABLE
IN
H
H
L
H
L
H
L
X
H
OUT
H =High, L =Low, X =Don't Care
TO PRE DRIVER
AND
OUTPUT STAGES
FAULT LOGIC TABLE
IN
NOTE:
1. INPUT AND ENABLE PULLDOINN SOURCES FORCE
OUTPUT TURN·OFF FOR UNTERMINATED INPUTS
FIGURE 1. SCHEMATIC OF ONE INPUT STAGE
2·14
OUT
FAULT
MODE
H
L
H
Normal
H
H
L
L
L
L
Over Current, Over Temperature
Open Load or Short to Power Supply
L
H
H
Normal
Specifications CA3272, CA3272A, CA3292A
Absolute Maximum Ratings
Thermal Information
output Voltage. Vo (CA3272. CA3272A) ••••••••••••••••• +SOV
Output Sustaining Voltage. VCE(SUS) (CA3272. CA3272A) ••••• 40V
Output Voltage. Vo (CA3292A) ••••••••••••••••••••••• VCLAMP
Output Clamp Energy. EOK (CA3292A) •••••••••••••••• TBDmJ
Output li"ansient Current, (Note 1) • • • • • • • • • • • • • • • • •• 1.6A Max.
Output Load Current, (Note 2) •••••••••••••••••••••••••• 0.7A
Supply Voltage. Vee .••••••••••••••••••••••••••••••••• +7V
Logic Input Voltage. VIN •.••••••••••••••••••••••••••••• 15V
FAULT Output Voltage. VF .•••••••••••••••••••••••••••• 16V
Operating Temperature Range •••••••••••••••• -4OOC to +125°C
Junction Temperature •••••••••••••••••••••••••••••• +lSOOC
Thermal Resistance .••••.••••••••••.•••••••••••••
8JA
PLCC ••••••••••••••••••••••••••••••••••••
45°CIW
PLCC (With PC Board Heat Sink) ••••••••••••••
3O"CIW
Power Dissipation (No Heat Sink)
Up to +85°C ••••••••••••••••••••.•••••••••••••••• 1.5W
Above +85°C •••••••••••••••••• Derate linearly at 23mWI"C
Power Dissipation: (WIth PC Board Heat Sink. Note 3)
Up to +85°C •••••••••••••.••••••.•••••••••••••••• 22.W
Above +85°C ••••••••••••.••••• Derate Unearly at 33mWI"C
Storage Temperature Range ••••••••••••••••.• -6500 to +1 SOOC
Lead Temperature (Soldering lOs) •••••.•••••••••••••• +265°C
CAUTION: SlressliS above thoss listed In 'Absolute Maximum Ratings' may cause permanent damage to the davies. This Is a stress only /Bting and opIJ/B/Jon
01 the device at thess Of any other conditions above those Indicated in the ops/B/Jonsl sections 01 this spsci/ica/Jon Is not Implied.
Electrical Specifications
TA = -400 C to +1250 C. vee = 5.5V. Unless Otherwise Specified
CA3272A. CA3292A
CA3272
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ICEX
VIN = 0.8V; VEN = 5.5V; (Note 4)
Vee = 60V br CA3272. CA3272A;
Vee = 24V for CA3292A
·
30
100
·
30
100
j1A
40
·
·
40
·
.
V
·
·
·
28
32
36
V
Ic = 400rnA. T" = +12SOC
·
·
0.4
·
·
0.3
V
Ic = SOOrnA. TA = +2500
·
·
0.5
·
·
0.4
V
Ic = 6OOrnA. TA = -4ooC
·
·
·
·
·
0.5
V
Ic = SOOmA, TA = -4ooC
-
-
0.6
-
-
-
V
Vee =3.5V
-
0.8
-
0.8
V
OUTPUT PARAMETERS
Output (OFF) Current
Output Sustaining Voltage:
CA3272. CA3272A
VCE(SUS)
Note 7
Output Clamp Voltage:
CA3292A
VClAMP
Ic = 300j1A; VEN = 0.8V
Coliector·to·Emltter
Saturation Voltage
VCE(SAT)
VIN = 2V. Vee = 4.75V.
LOGIC INPUT THRESHOLDS
Input Low Voltage
VIL
Input High Voltage
V1H
2
-
-
2
-
-
V
Input Low Current
IlL
VIN = VEN = 0.8V; Vcc = 4.75V
10
45
70
10
45
70
j1A
Input High Current
IIH
VIN = VEN = 5.5V
10
45
70
10
45
70
j1A
VIN = VEN = 5.5V; IourA = IOUTB
-
-
65
-
-
65
rnA
VIN=OV
-
·
10
-
-
10
rnA
IpHL
ILOAD = SOOrnA
10
10
lIS
3
10
-
3
IpLH
-
3
ILOAD = 500rnA
3
10
lIS
Output Low Current.
IF(SINK) (with Fault)
IOL
VIN = 0.8V; VEN = 2.0V; VF = 4V
VOUT = Low = 1V; (Note 5)
0.04
0.09
0.12
1
2
4
rnA
Output High Current. IF(lK)
IOH
No Fau~ (Note 5)
-
-
2
-
-
20
j1A
SUPPLY CURRENT
All Outputs ON
ICC(ON)
= IOUTC = !aUTO = 400rnA
All Outputs OFF
ICC(OFF)
PROPAGATION DELAY
Turn-ON Delay
Turn-OFF Delay
FAULT PARAMETERS
2-15
Specifications CA3272, CA3272A, CA3292A
Electrical Specifications TA = -4O"C to +125°C, vcc = 5.5V, Unless Otherwise Specified (Continued)
CA3272A, CA3292A
CA3272
PARAMETERS
SYMBOL
Outpu1 Low Voltage
VOL
TEST CONDITIONS
External Load Equal Min. 10l
=0.8V; VEN =2V (Note 6)
Output Driver Fault Sense,
High Threshold (Open)
VHTHD
VIN
Output Driver Fault Sense,
Low Threshold (Short)
VlTHD
VIN =VEN
=2V (Note 6)
MtN
TYP
MAX
MIN
TYP
MAX
UNITS
-
0.2
0.4
-
0.2
0.4
V
3
4
5.5
3
4
5.5
V
3
4
5.5
3
4
5.5
V
0.6
-
Note 1
0.6
-
Note 1
A
PROTECnON PARAMETERS
VIN =VEN =2V, VOUT =40 to
16V
Over-Current Limiting
IUM
Over-Temperature
Limiting
(Junction Temperature)
TUM
-
165
-
-
165
-
OC
Over-Temperature
Limiting, Hysteresis
THyS
-
15
-
-
15
-
4°C
Input Capacitance
CIN
3
-
-
pF
CEN
-
3
Enable Capacitance
-
DESIGN PARAMETERS
4.6
4.6
pF
NOTES:
1. Ou1put Transient Currents are controlled by on-chlp limiting for each output Under short-circuit conditions with voltage applied 10 the
collector of the OUtpu1 transistor and with the ou1put transistor turned ON, the current will Increase to 1.2A, typical. Over-Current limIting protects a short circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output
driver will shortly thereafter (approx. 5ms) go into Over-Temperature Shutdown. While Over-Current Limiting may range to peak currents as high as 1.6A, each outpu1 will typically withstand a direct short circuit at normal single battery supply levels. Excessive dissipation before thermal shutdown occurs may cause damage to the chip for supply voltages greater than 16V. When sequentially
switched, the outputs are rated to withstand peak current, cold turn-on conditions of lamp loads such as #168 or #194 lamps.
2. The total DC current with all 4 ou1puts ON should not exceed the total of (4 X 0.7A + Max. IcC>- 2.85A This level of current will significantly
increase the chip temperature due to increased dissipation and may cause thermal shu1down in high ambient temperature conditions (See
Absolute Maximum Ratings for Dissipation). Anyone outpu1 may be allowed to exceed 0.7A but may be subject 10 Over-Current Limiting
above the IUM minimum limit of 0.7A. No single output should be loaded to more than Over-Current Limiting above the IUM minimum limit
ofO.7A. As a practical limit, no single outpu1 should be loaded to more than lA maximum.
3. Normal applications require a surtace mount of the 28 lead PLCC package on a PC Board. The package has a power lead frame construction where ground pins 5 - 11 and 19 - 25 conduct heat from the frame to the PC Board. With approximately a 2 square inch copper area
adjacent to the ground pins, the thermal resistance on the mounted package may be as low as 3OOCNi.
4. ICEX Is the static leakage current at each output when that output Is OFF (ENABLE Low). Refer to the Figure 3 illustration of an output
stage. The value of IcEX Is both the leakage into the output driver and a pull-down current sink, IO(SINK). The purpose of the current sink
is 10 detect open load conditions.
5. The IOl value of "Output Low Current, IF(SINK)" at the FAULT pin is both the static leakage of the ou1put driver QF and the current sink,
IF(SINK)· The current sink is active only when a fault exists. When no fault exists, the IOH current at the FAULT pin Is the maximum leakage
current, IF(lK). Refer to Figure 2 for an illustration of the FAULT ou1put and associated external components. Refer to FAULT LOGIC TABLE
for Fault Modes.
6. The Voltages, VHTHD, VlTHD are the comparator threshold reference values (Min. & Max. Range) sensed as a high and low state transitions for voltage forced at the outputs. VHTHD Indicates an open load fault when the output is decreased to less than the threshold.
VlTHD Indicates a shorted load when the Ou1put is Increased greater than the threshold. The output voltage is changed until the FAU LT
pin indicates a Low (Fault). Refer to Figure 2 for test value of external resistor. Refer to 10l and IOH FAULT PARAMETERS Test Limits
to determine VOL and VOH at the FAULT pin.
7. Tested with 120mA switched off In a Load of 70mH and 320 series reslsJence;
CA3272, CA3272A: Outputs clamped with an external zener diode, limiting VOUT to the VCE(SUS) maximum rating of +4OV.
CA3292A: Ou1puts limited to the VCLAMP voltage by the Internal collector-to-base zener diode and output transistor clamp.
2-16
CA3272, CA3272A, CA3292A
Applications
The CA3272, CA3272A and CA3292A are quad-gated inverting low-side power drivers with a fauR diagnostic flag output.
Both circuits are rated for +12SoC ambient temperature applications and have current limiting and thermal shutdown. While
functionally similar to the CA3262AO, they differ in the mode
of over-voRage protection and have the added feature of a
FAULT flag output. Also, inputs to channels A, B, C, D and
ENABLE have internal pulldowns to turn ·OFP' the outputs
when the inputs are floating.
As noted in the Block Diagrams, the CA3292A is equivalent to
the CA3272 and CA3272A except that it has internal clamp
diodes on the outputs to handle inductive switching pulses
from the output load. The structure of each CA3292A output
includes a zener diode from collector-ta-base of the output
transistor. This is a different form of protection from other quad
drivers with current steering clamp diodes on each output,
paired to one of two ·CLAMP" output pins. The CA3292A output transistor will turn-on at the zener diode clamp voRage
threshold which is typically 32V and the output transistor will
dump the pulse energy through the output driver to ground.
Block Diagram illustrates the logic functions associated with
Fault detection. The diagnostic output for each of the four
channels of switching is processed through the fault logic circuit associated with each channel. It is then passed to an OR
gate which controls the FAULT flag output transistor, OF thru a
2 input AND gate.
The ENABLE input is common to each of the 4 power switches
and also disables the FAULT flag output at the 2 input AND gate
when it is low. The FauR Logic circuit senses the IN and OUT
states and switches OF ·ON" if a fauR is detected. Transistor OF
activates a sink current source to pull-down the FAULT pin to a
(low) state when the fault is detected. Both shorted and open
load conditions are detected.
o
It is normal for thermal shutdown and current limiting to
occur sequentially during a short circuit fault condition. A
precaution applies for potential damage from high transient
dissipation during thermal shutdown. (See Note 1 following
the Electrical Characteristics Table).
FAULT SENSE
FAULT
FAULT FLAG
DIAGNOSTIC
~~~~ 3V
Turn-On Delay
~L
10 = 500mA, No Reactive Load
Turn-Off Delay
tpLH
10 = 500rnA, No Reactive Load
Fault Reference Voltage
Fault Reset Delay (After CE Low
to High Transition)
Output OFF Voltage
VOREF
iuD
VOFF
-
-
1.05
1.5
-
A
-
1
10
I1S
-
2
10
I1S
V
Output Programmed ON, Fault Detected
IfVO>VOREF
1.6
1.8
2.0
See Figure 1
50
80
250
I1S
-
0
1
V
Output Programmed OFF, Output Pin
Floating
LOGIC INPUTS (MOSI, CE, SCK and RESET)
Threshold Voltage at Falling
Edge
VT.
Voo = 5V ± 10010
0.2VOD
0.3Voo
-
V
Threshold Voltage at Rising
Edge
VT•
Voo=5V± 10%
-
0.6Voo
0.7VOD
V
Hysteresis Voltage
VH
VT.- VT•
0.85
1.4
2.25
V
-10
-
+10
JlA
20
pF
Input Current
II
VDD = 5.5V, 0 < VI < VOD
Input Capacitance
CI
O
~~
5~
Ow
3=1::
03=
....•.....
.Jrn
~
............. """
-.... -"
~
1.5
-"
-'0:
-'0:
e(:o
z-,
we( 1.0
OW
-x
rn(,)
-"
":0
MAX. ALL ON
CURRENT UMIT
(EaUAL CURRENT)
0::0
O:a
:Ow
Ox
w~
if!.
0
--4--(3)
--+-(4)
0.5
~
::Il
=
CURVE (3): ROS(ON) 1a
CURVE (4): ROS(ON) O.SQ
THERMAL RESISTANCE, 9JC = 30 CNi
=
0.0
50
75
100
125
150
CASE (HEAT SINK TAB) TEMPERATURE (OC)
FIGURE
5. HIPOOB1 CURRENT vs CASE (TAB) TEMPERATURE, ALL OUTPUTS ON WITH EQUAL CURRENT
16
HIP0081 WITH EXT.
6°CIW HEAT SINK
(9JA = gOCIW)
14
/'
2
-so
-25
o
25
50
AMBIENT TEMPERATURE ("C)
75
FIGURE 6. DISSIPATION DERATING CURVES
2-35
100
125
150
HIP0082
Quad Power Driver with
Serial Diagnostic Interface
PRELIMINARY
April 1994
Features
Description
• Low Side Power MOSFET Output Drivers
- Output Voltage Rating •••••••••••••••••••••• 7SV
- Maximum Output Current Switching ••••••••••• 2A
- Max. Output RDSON {TJ = +1S00C) •••••• 0.S7010.620
The HIP0082 Quad Power Driver contains four individually
protected NDMOS transistor switches to drive inductive and
resistive loads such as: fuel injectors. relays. solenoids. etc.
The outputs are low-side switches driven by active·low
CMOS logic inputs. Each output is protected against excessive current due to a short·circuit. Internal drain-to·gate
zener diodes provide output clamping for over·voltage. An
integrated charge pump allows operation from a single 5V
logic supply. Diagnostic circuits provide ground short (SG).
supply short (SC) and open load (Ol) detection for each of
the four output stages and indicate over-temperature. Diagnostic information may be read via a synchronous serial
interface. Six bits 01 write/store data controls the Ol fault
delay time or sets Outputs 3 and 4 to the 2A or 5A mode.
• Programmable Output Current Limiting
- Bit Select 2A or SA on Outputs 3 and 4
• Output Protection
- Output Over-Current Shutdown
- Output Over-Voltage Clamp
- Over-Temperature Diagnostic Feedback
• Diagnostics for Shorts, Opens and Over-Temperature
• Synchronous Serial Interface with
- 22-Blt Serial Diagnostic Register
- SPI Compatible Interface
• Low Icc Supply Current with Full Load •••••••• 10mA
The HIP0082 is fabricated in a Power SiMOS IC process and
is intended lor use in automotive and other applications with
a wide range of temperature and electrical stress. It is particularly suited for driving high-current inductive loads requiring
high breakdown voltage and high output current.
• Low 9JC Power SIP Package •••••.••••••.••• •3°CIW
• -40oC to +12SoC Operating Temperature
The HIP0082 is supplied in a 15 Lead Power SIP package
with lead form options for either vertical or surface mount.
Applications
Ordering Information
• Single SV Supply Operation with CMOS logic Inputs
• Drivers For
- Solenoids
- Relays
- Power Output
- Lamps
-
• System Use
- Automotive
- Appliances
- Industrial
- Robotics
Injectors
Steppers
Motors
Displays
Pinout
PART NUMBER
TEMPERATURE
RANGE
PACKAGE AND
LEAD FORM
HIPOO82AS1
-4Q°C to +125°C
15 lead Plastic SIP
Staggered Vertical Mount
HIPOO82AS2
-400 C to +125°C
15 Lead Plastic SIP
Surface Mount
Block Diagram
HlPO082 (SIP)
TOP VIEW
HEAT SINK TAB INTERNAllY CONNECTED
TO PIN 8 GROUND (vssl
:OUTx
I
o
o
TXD
ClK
CAUTION: These d9\lices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporetion 1994
2·36
File Number
3643
Specifications HIP0082
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Logic and Control), Vcc •..••..•.•.. -0.3V to 7V
Power MOSFET Drain Voltage, Vo (Note 1) .•....•• -0.7 to VClAMP
Output Clamp Energy, EoK •.••.....•••.•........•..• TBDmJ
Input Voltage (Logic and Driver Inputs), VIN •... -0.5V to Vcc +0.5V
Maximum Output Current, Outputs 1 and 2 ........••...... +2A
Maximum Output Current, Outputs 3 and 4 ....•.••••...••• +5A
Maximum Total Output Current, All Outputs ON ••••......... +8A
Maximum Peak Output Current, 10(MAX)' (Note 2) .••.•.. -SA to Isc
Operating Ambient Temperature Range ....••... -4lliOo-------;~~
_ _ _ _-:
tCLKL
Output Short-ta-Ground Detection
When the voltage on an output pin is below VSG and the output is off, a ground short is detected and stored in the diagnostic register after a delay tSG' The outputs of the short-toground (SG) comparators are also connected directly to the
diagnostic register so that they can be monitored via the
serial interface.
tCSHOZ
--.!,'
_m
__- - .
:,,
:
, -
HIP0082
TMP Bit - Indicates that the chip temperature has exceeded
the limit TTMP. The outputs are not switched off when this
occurs; the condition is indicated by the setting of the TMP
bit. Sensors for the TMP bit are located near the power drivers and are OR'd to provide a single bit for the chip.
SCx Bits - Indicate a short-circuit to battery or over-current
on the corresponding output.
OLx Bits - Indicate that no load (or a high resistance load) is
connected to the corresponding output.
SGx Bits - Indicate that the voltage on the corresponding
output is below the VSG limit.
The final 8 bits (most significant bits) of the diagnostic word
indicate the states of the open-load and Short-to-ground
comparators when the CS pin went from high to low. Using
this feature, an external microprocessor can monitor the status of the OL and SG comparators directly.
Diagnostic Write Operation
When the RiW pin is in the low state it is possible to write six
bits to the IC to influence its mode of operation. The write
operation is illustrated in Figure 3. The programmable bits
are as follows:
Test Bit - Used to put the IC in test mode (not recommended). This bit should be low for normal operation.
ISC Bit - This bit programs the short-circuit level for outputs
3 and 4. When this bit is set high the lower value for the current shutdown threshold is set.
Td_OLx Bits - These bits set the delay times for the openload measurements individually for each of the four outputs.
A logical high sets the open-load delay time to its shorter
value.
Pin Descriptions
vee
and GND • 5V Supply and Ground connections. A
charge pump is used to boost the Power MOSFET gate
drive. This allows a single 5V supply to satisfy all logic and
drive requirements.
OUT1 - OUT4 - Low-side output drivers with 0.620 (OUT1
and OUT2) or 0.570 (OUT3 and OUT4) on resistance. The
outputs are provided with over-current shutdown and overvoltage clamping. Additionally open-load and short-toground detection is carried out when the outputs are ON.
IN1 - iiii4 - Active-low CMOS logic inputs which control the
output stages OUT1 - OUT4. These inputs are provided with
pull-up resistors.
RS'i' - Active-low logic-level reset input with internal pull-up
resistor. When RS'f is in the low state all outputs are off and
all registers and counters are reset. When the reset pin is
taken high the IC remains in reset mode for a time tRST.
CLK - Clock input for synchronous serial interface with internal pull-up resistor. This input must be high when CS transitions from high to low.
es - Active-low chip select input for serial interface. This
input has an internal pull-up resistor.
R/Vi - Read/write control pin for serial interface. This input
controls whether the TXD pin is an input or output.
TXD - Bidirectional data pin for serial interface. When RiW is
high diagnostic data can be read from HIP0082. When RiW
is low, 6 bits may be written to the internal program register.
ClK
TXD
ZZ .. HIGH IMPEDANCE
DIRECT COMPA~TOR OUTPUTS
FIGURE 2. SERIAL INTERFACE READ OPERATION
ClK
_I=~~;-~~~~~r~~~
__~~__~~__~r
zzzz
TXD
ZZ .. HIGH IMPEDANCE
FIGURE 3. SERIAL INTERFACE WRITE OPERATION
2-40
INTELLIGEN
-
POWERICs
3
HIGH SIDE SWITCHES
PAGE
HIGH SIDE SWITCHES SELECTION GUIDE ................................................... .
3-2
HIGH SIDE SWITCHES DATA SHEETS
CA3273
High-Side Driver ....................................................... .
3-3
HIP1030
1A High Side Driver with Overload Protection ................................ .
3-6
HIP1031
Half Amp High Side Driver with Overload Protection ........................... .
3-10
HIP1090
Protected High Side Power Switch with Transient Suppression ................... .
3-13
HV400
High Current MOSFET Driver •.............................................
3-18
HV400MJ/883
High Current MOSFET Driver ............................................. .
3-28
ICL7667
Dual Power MOSFET Driver .............................................. .
3-38
3-1
wen
-J:
en(,)
OW
~t:::
-3:
J:en
High Side Switches Selection Guide
TYPE
FUNCTION
MAX
SUPPLY
DC SUPPLY
RANGE
PEAK MAX
CURRENT
DC MAX
CURRENT
PACKAGE
RECOMMENDED
APPLICATIONS
PROTECTED POWER SWITCHES
CA3273
Single
Power
40V
4V10 24V
1.2A
O.6A
3 Lead Mod.
TO-202
Solenoid, Relay,
Lamp and Molar
HIP1030
Single
Power
35V
4.5V10 25V
2.5A
1.lA
5 Lead
TS·OO1AA
Solenoid, Relay,
Lamp and Molar
HIP103l
Single
Power
35V
4.5V10 25V
1.7A
O.7A
5 Lead
TS·OO1AA
Solenoid, Relay,
Lamp and Molor
HIP1090
Single
Power
±90V,
l5ms
4Vlo l6V
2A
lA
3 Lead
TO-220
Solenoid, Relay,
Lamp and Molor
TYPE
FUNCTION
MAX
SUPPLY
DC
SUPPLY
RANGE
PEAK MAX
CURRENT
MAX
FREQUENCY
PACKAGE
RECOMMENDED
APPLICATIONS
MOSFET DRIVERS
HV400
Single
High Speed
35VDC
l5V 10 30V
6A (Source)
30ASink
(Pulsed)
20kHz (MC)
200kHz
(SMPS)
8 Lead PDIP
andSOIC
SMPS,
FET Drivers., and
Molar Conlrollers
ICL7667
Dual Power
l5V
4.5V 10 l5V
1.5A (Pulsed
Gale)
200kHz
8 Lead
TO-99,PDIP,
CerDIP, and
SOIC
SMPS,
FET Drivers, and
Molar Controllers
3-2
CA3273
HARRIS
S EM I CO N D U C TO R
High-Side Driver
April 1994
Features
Description
• Equivalent High Pass P-N-P Transistor
The CA3273 is a power IC equivalent of a P-N-P pass transistor operated as a high-side-driver current switch in either
the saturated (ON) or cutoff (OFF) modes. The CA3273
incorporates circuitry to protect the pass currents, excessive
input voltage, and thermal overstress. The high-side driver is
intended for general purpose, automotive and potentially
high-stress applications. If high-stress conditions exist, the
use of an external zener diode of 35V or less between supply and load terminals may be required to prevent damage
due to severe conditions (such as load dump, reverse battery and positive or negative transients). The CA3273 is
designed to withstand a nominal reverse-battery
(VBAT = 13V) condition without permanent damage to the
IC. The CA3273 is supplied in a modified 3-lead TO-202
plastic power package.
• Current Limiting •••••••••••••••••••••• O.SA to 1.2A
• Over-Voltage Shutdown ••••••••••••••• +25V to +40V
• Junction Temperature Thermal Limit ••••••••• +150 oC
• Equivalent Beta of 25•••••••••••••••••• 400mAlO.5V
• Internal Bandgap Voltage and Current Reference
Applications
• Fuel Pump Driver
• Relay Driver
• Solenoid Driver
• Stepper Motor Driver
Ordering Information
• Remote Power Switch
TEMPERATURE
RANGE
PART
NUMBER
• Logic Control Switch
-4O"C to +85°C
CA3273
Pinout
TO-202 Modified SIP
Block Diagram
en :
:. __ ._--------_ .... _-----_._--------.
CA3273 (SIP)
TOP VIEW
:====:
PACKAGE
vee
(3)Vo(LOAD)
PIN 1
(2) Vsw (CONTROL)
~:====. (1) vee (SUPPLY)
:
·
···: I
Icc
··: I
Rs
OUTPUT PASS
TRANSISTOR
I ¥ I
DRIVE AND UMlTlNG
CONTROL
[9_~~2JL
_____________
PIN2
Vsw
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-3
10
Vo
PIN 3
I
RL
LOAD
-=-=
t---------!
I
CONTROL
INPUT
File Number
2113.4
Specifications CA3273
Absolute Maximum Ratings
Thermal Information
Fault Max, Supply Voltage, Vee •.....•........•..•.•.••• 40V
Maximum Operating Vee:
At 10=400mA (-40"C to +85°C Ambient) ••••.•••••••••• l6V
At 10=60OmA (-40"C to +250 C Ambient) ••••..••••••••• 24V
Max. Positive Output Peak Pulse, Vsw Open •••..••••. Vcc+12V
Max. Operating Output load Current ••.••••••.••••••.. 600mA
Short Circuit load Current, Ise •.•••...••••.... Internal limiting
Reverse Battery • . • . • . . . . . . • . . • • • . . . • • . • . • . • • • • • • • •• -13V
Thermal Resistance
OJA
Plastic SIP Package •.•.......•...........•..... +700 C/W
Maximum Power Dissipation, Po
At +25°C Ambient, TA (Note 1) •••••••••••••....••••.. 1.8W
Derate above +25°C (No Heat Sink) ••••.•.•••••• 14.3mWI"C
Maximum Junction Temperature, TJ (Note 2) •.•••••.••••• 150°C
Ambient Operating Temperature Range •••.•••••• -4O"C to +85°C
Storage Temperature Range •••••.•.•••••••.•. -400 C to +150°C
lead Temperature (Soldering lOs max) .......•........ +265°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and oparation
of the device st these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TA = -40°C to +850 C, Unless Otherwise Noted, See Block Diagram for Test Pin Reference
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
24
V
0.5
V
Operating Voltage Range
Vee
Vee Reference to Vsw
4
Saturation Voltage(Vcc - Vol
VSAT
10 = -400mA, Vsw = OV, Vee = 16V
-
Operating load
RL
Vsw = OV (Switeh ON)
TA = +85°C, Vee = 16V
TA =
Over-Voltage Shutdown Threshold
Over-Current limiting
+250 C,Vee
= 24V
25
33
40
V
10(UM)
Vee =16V,Vsw = IV (SWitch ON)
-
-
1.2
A
150
-
°C
-
-15
-
mA
-
-22
mA
-33
mA
Vee = 24V
-50
-50
-
-
rnA
Vee = 7V
Vee = 24V,Vsw = 23V
-200
-
+50
IIA
Vee = 7V, Vsw = 6V
-200
+50
IIA
Vsw =16V
-100
+100
IIA
Vsw =15V
-100
+100
IIA
TUM
Isw
Vee =16V, Vsw = OV
10=OmA
10 =-400mA
Control Current, Max. load,
Switch ON
Output Current leakage
0
Vsw = OV,R L = 1kQ,Increase Vee.
(Vo goes low)
Over-Temperature limiting
Min. Control Current, No Load,
SwitehOFF
40
Vee(THO)
Control Current, Switch ON
Max. Control Current,High and
low Vee
0
40
Vee = 24V,Vsw = OV,lo = -600mA
ISW(MAX)
ISW(NL)
IO(LEAK)
RL = 400, Vsw =1V
rnA
Va = Open,(Switeh OFF)
Va = OV, Vee = 16V, (Switch OFF)
-
NOTES:
1. The calculation for dissipation and junction temperature rise due to dissipation is: Po = (Vee - Vo)x 10 + Vee x Isw and
TJ = TA + Po x OJA where TJ is device Junction temperature, TA is ambient temperature and OJA is the junctlon-to-amblent
thermal resistance.
2. Therrnallimiting occurs at +150°C on the chip.
3-4
CA3273
,,r--'" -- --, .. --;- -_ ... --- -- ........ ---, --- .. -- ............... --... -_ ...... -- ......................... -- ................................. ..
:,,
,,
,,
,,
,,
,,,
,,
,
:,,
~-----r--*-----1---*-~ o~~~lg~~~E
,,
CONTROL CIRCUIT
,,,
~- ... ---- .. ..
............. -.. "' . .... .. -. --- . -....... ----- .... ----- .................... ---_ .... _-
Vee
INPUT
-- ----
Vo
OUTPUT
-- --
Vsw
CONTROL INPUT
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF CA3273
Vee
Vee
+4 TO+24V
(SUPPLY INPUT)
1Kn
-=-
OFF
OFF
2N5320
OR EQUIVALENT
FIGURE 2. TYPICAL APPLICATION WITH ZENER DIODE FOR
OVER-VOLTAGE PROTECTION WITH INDUCTIVE
LOAD SWITCHING. Vz SHOULD BE LESS THAN
35V. WHEN CURRENT IS SWITCHED OFF IN THE
OUTPUT LOAD (L), THE INDUCTIVE KICK PULSE
GOES NEGATIVE. THE CLAMPED CLAMP LEVEL
OF THE NEGATIVE GOING PULSE IS Vcc - VZ.
>-----~~r-----~~
-
"- ~
>-______-l(V"N)
"
o
25
50
75
TEMPERATURE (OC)
100
125
SOLENOID
....yC>J
>-______-l(V"N)
o
-25
2N5320
OR EQUIVALENT
RESISTIVE
DERATING 700 CIW
IVITH~UT HEAT SINK)
K
-=-
FIGURE 3. OPTIONAL RANGE SHIFTII'JG OF THE Vee INPUT
VOLTAGE USING A ZENER DIODE TO OFFSET
THE Vsw CONTROL PIN. (I.E.,THE OVER-VOLTAGE SHUTDOWN THRESHOLD WILL BE INCREASED TO VCC(THD) + Vz AND THE MINIMUM
Vcc OPERATING VOLTAGE IS Vz + 4V).
2
-50
Vz
ONITONTROL
INPUT o---v.rv-of:
ONITONTROL
INPUTo-WH!:::
RELAY
150
FIGURE 4. DISSIPATION DERATING CURVES
FIGURE 5. TYPICAL LOADS
3-5
HIP 1030
HARRIS
SEMICONDUCTOR
1A High Side Driver with
Overload Protection
PRELIMINARY
April 1994
Features
Description
• Over Operating Temperature Range
- 1V Max VSAT at 1A
- 1A Current Switching Capability
- 4.SV to 2SV Power Supply Range
-400 C
to +12SoC
• Over-Voltage Shutdown Protected
• Over-Current Limiting
The Functional Block Diagram for the HIP1030 shows the
protection control circuit functions of over-current, overvoltage
and over-temperature. A small metal resistor senses overcurrent in the power supply path of the pass transistor and
load. Overvoltage detection and shutdown of the output driver
occurs when a comparator determines that the supply voltage
has exceeded a comparator reference level. Overtemperature is sensed from a VSE differential sense element
that is thermally close to the output drive transistor. In addition
to the input detected overvoltage protection, negative peak
voltage of a switched inductive load is clamped with an internal zener diode. An internal bandgap voltage source provides
a stable voltage reference over the operating temperature
range, providing bias and reference control for the protection
circuits.
• Thermal Umlting Protection
• 60Vp K Load Dump
• Reverse Battery Protection to -16V
Applications
• Motor Driver/Controller
• Driver for Solenoids, Relays and Lamps
• MOSFET and IGBT Driver
• Driver for Temperature Controller
Ordering Information
PART
NUMBER
HIP1030AS
TEMPERATURE
RANGE
PACKAGE
-40°C to +125°C
5 Lead TS·001AA SIP
Pinout
The HIP1030 is a High Side Driver Power Integrated Circuit
designed to switch power supply voltage to an output load. It
is the equivalent of a PNP pass transistor operated as a
protected high side current switch in the saturated ON state
with low forward voltage drop at the maximum rated current.
The HIP1030 has low output leakage and low idle current in
the OFF state.
The HIP1030 is particularly well suited for driving lamps,
relays, and solenoids in automotive and industrial control
applications where voltage and current overload protection
at high temperatures is required. The HIP1030 is supplied in
a 5 lead TS-001AA Power SIP package.
Functional Block Diagram
HIP1030 (SIP)
TOP VIEW
1 : ~~g:ONTROL)
3TASGND
2 VOUT (LOAD)
1 Vee (SUPPLy)
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-6
GND
File Number
2788.5
Specifications HIP1030
Absolute Maximum Ratings
Thermal Information
Max. Supply Voltage Vcc ........ See O.V. Shutdown Limit, Vovso
Input Voltage, VIN (Note 1) ......•.••••...•..-w to (Vcc - 0.5V)
Load Current, lOUT' ........••....•..••••.... Internal Limiting
Load Dump (Survival) •........•.••...••.••.•.••••. ±60VPK
Reverse Battery . . . . . . . • . . . . . . . . . . . . . • • . . • . • • . . • . • .• -16V
Thermal Resistance
9JA
9JC
Plastic SIP Package ..••.......... " 500 CIW
4°CIW
Maximum Power Dissipation (Note 2)
At TA = +125°C, Infinite Heat Sink •••..••....••....... 6.25W
Maximum Junction Temperature, TJ ••••••••..••••...•.. 150°C
Ambient Operating Temperature .••...••••••••. -40oC to +125°C
Storage Temperature Range ••••..••...•.••.•• -400C to +150°C
Lead Temperature (Soldering 10s max) ..•.•..•...•.•.. +265°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not Implied.
Electrical Specifications
PARAMETERS
Operating Voltage Range
Over-Voltage Shutdown
TA =_40°C to +125°C, VIN
SYMBOL
=2V, Vcc =+12V, Unless Otherwise Specified.
TEST CONDITIONS
Vce
Vovso
Rl
=1Kn; VIN =2V
MIN
TYP
MAX
UNITS
4.5
-
25
V
26
33
38
V
Over-Temperature Limiting
Tso
Negative Pulse
Output Clamp Voltage
Vel
lel = -100mA; Vee
Short Circuit Current Limiting
Isc
(Note 4)
Input Control ON
VIH
Input Control OFF
Vil
-
Input Current High
IIH
VIN
=5.5V, Vec =6V to 24V
6
III
VIN = 0.8V, Vcc =6V to 24V
6
-
Input Current Low
150
=4.SV to 25V
Supply Current, Full Load
Input Control ON
ICCMAX
VIN = 2V; lOUT =1.0A;
Supply Current, No Load
Input Control OFF
ICCMIN
VIN
Input-Output Forward Voltage
Drop (VCC - VOUT)
Output Leakage
Turn ON Time
Turn OFF Time
=OV; lOUT =OA;
VSAT
lOUT =1A; Vcc =4.5V to 25V
IOUT_lK
VIN = 0.8V; Vee = 6V to 24V
ioN
Rl
=SOn; (Note 3)
IoFF
Rl
=SOO; (Note 3)
°C
(Vee - 3S)
(Vee - 30.5)
(V cc - 2S)
V
1.1
1.6
2.5
A
2.0
-
-
V
O.S
V
40
I1A
30
I1A
-
1.05
1.1
A
-
55
100
I1A
-
0.6
1
V
4
50
I1A
5
20
I1S
25
65
I1S
-
NOTES:
1. The Input Control Voltage, VIN shall not be greater than (Vee - 0.5V) and shall not exceed +7V when Vec is greater than 7.5V.
2. The worst case thermal resistance, 8JC for the SIP TS-001 AA 5 lead package is 4°CIW. The calculation for dissipation and junction temperature rise due to dissipation is:
Po = (VCC-VOUT)(IOUT) + (VCC)(lCCMAX - lour) or (VCC)('CCMAX) - (VOUT)(IOUT)
TJ = TAMBIENT + (Po) (8Jd for an Infinite Heat Sink.
Refer to Figure 2 for Derating based on Dissipation and Thermal Resistance. Derating from +150°C is based on the reciprocal of thermal
resistance, 8JC +8HS ' For example: Where 8JC = 4°CIW and given 9HS = ffCNoI as the thermal resistance of an eX1ernai Heat Sink, the
junction-to-air thermal reSistance, 8JA = 100CIW. Therefore, for the maximum allowed dissipation, derate 0.1Wf'C for each degree from
TAMB to the maximum rated junction temperature of +150oC. I!TAMB = +100oC, the maximum Po is (150 -100) x 0.1Wf'C = SW.
3. Refer to Figure 3A and 38 for typical switching speeds with a 200 Load.
4. Short circuit current will be reduced when thermal shutdown occurs. Testing of short circuit current may require a short duration pulse.
See Figure 7.
3-7
HIP 1030
Typical Application
-~o'-_--+ POWER
SUPPLY
LOADS:
RELAYS
SOLENOIDS
LAMPS
MOTORS
'.:=. . . . . . . . . . . . . . . :,.,~~.:;
-=- GND
TO VIN
-=- GND
Typical Performance Curves
16
"-
,
WITH EXT. "
6 0 CIW H. S.
1\
\
I"-
1.5
WITH EXT.
OOCIW H.S.
(INFINITE
HEAT SINK)
\
I'..
~
=lon, Vee = VSAT + IL RU VSAT =(Vee - VOUT)
=5V
DATA TAKEN USING 110CM x 110CM
>A:
,
""-
RL
INPUT: VIN
FLAT ALUM. HEAT SINK
1.0
I
§
IL
~
g
IL
.50
100
o
150
15
,,
TON
Vee = 12V, LOAD = 200 IN PARALLEL
WITH 2200pF; TA. +25OC
INPUT: VIN = 2V 10 OV STEp, lms PERIOD, 500~ PULSE-
r"-.. t"--,.
J
o
o
2
FIGURE 3A. OUTPUT TURN-ON TIME (liS)
..l
~
TOFF
1
150
'\.
I
o
100
1\
f'\~
o
50
FIGURE 2. TYPICAL FORWARD VOLTAGE DROP,VSAT
CHARACTERISTICS vs AMBIENT OPERATING
TEMPERATURE
Vee = 12V, LOAD 20n IN PARALLEL
WITH 2200pF; TA = +25 0 C
INPUT: VIN OV 10 2V STEp, 1ms PERIOD, 500~. PULSE
=
0
AMBIENT TEMPERATURE ("C)
FIGURE 1. DISSIPATION DERATING CURVES
=
V
J
-50
AMBIENT TEMPERATURE ("C)
15
~
= 1.0 A
IL = O.SA
~
~
0
V
I
"- c\
~
~
I
:!
~
o
=1.25A
I
I
10
20
FIGURE 3B. OUTPUT TURN-OFF TIME (liS)
FIGURE 3. TYPICAL RISE TIME AND FALL TIME CHARACTERISTICS OF THE HIP1030 WITH A RESISTIVE AND CAPACITIVE
LOAD. THE TURN-ON TIME OF APPROXIMATELY 1.1I1S IS PRIMARILY DETERMINED BY THE Vee SUPPLY. THE OUTPUT FALL TIME IS LIMITED BY RC TIME CONSTANT OF THE LOAD.
3-8
HIP1030
Typical Performance Curves (Continued)
15 ,---------------------------------,
Vee = 12V, LOAD .160; TA" +250 C
Vee. 15V, LOAD .. 70mH + 22.30 IN SERIES; TA=+2SOC
INPUT: VIN .. OV to 2V STEP, 50% DUTY CYCLE PULSE
INPUT: VIN = OV to 2V STEP, 50% DUTY CYCLE PULSE
~
:;;; 15
w
CI
~
g
CI
10 r__f---r--i---r__f---r--+-~r__f--~
g~
w
~
~~
Q.
Q.
~
~
5 r__f---r--i---r__f---r--+-~r__f--~
10
0
~
~
~~~:J~~~~NpDJt~~V~
~ -5
La
o
~
-15
0.4
0.8
1.2
SWITCHING TIME (ms)
1.6
o
2.0
FIGURE 4. TYPICAL SWITCHING CHARACTERISTIC OF THE
HIP1030 WITH AN OUTPUT RESISTIVE LOAD
6
2
4
5
INDUCTIVE PULSE SWITCHING TIME (ms)
FIGURE 5. TYPICAL OUTPUT INDUCTIVE LOAD SWITCHING
PULSE. THE NEGATIVE CLAMP VOLTAGE
(Vee -31V) FOR THE INDUCTIVE KICK PULSE IS
REFERENCED TO THE Vee SUPPLY INPUT
6
Vee=4.5V, LOAD = SO, TA = +250 C
INPUT: VIN" OV to 2V STEP, 1ms PERIOD, 500..s PULSE
Vee" 4.5V, LOAD. en, TA. +250 C
INPUT: VIN" OV to 2V STEP, 1m. PERIOD, 500.... PULSE
--TON~
4
~
"I'..
2
................
J
TOFF
o
o
2
3
4
o
5
I
o
FIGURE SA. TURN-ON TIME (Ils)
T
I
4
12
S
16
20
FIGURE S8. TURN-OFF TIME (IlS)
FIGURE S. TYPICAL LOW SUPPLY VOLTAGE SWITCHING CHARACTERISTICS OF THE HIP1030. THE TURN-ON AND TURN-OFF
CHARACTERISTICS ARE SHOWN FOR Vee = 4.5V.
3
Vee = 24V, LOAD = 10; TA = +25oC
INPUT: VIN = 2V, 1 ms PERIOD, 100..s PULSE
~
w
~
!j
g
Vee VARIED FROM 4V TO 36V, NO LOAD
INPUT: VIN" 2V (DC); TA. +2SOC
I I
2
-
--rl~~~~T
w
~
:::>
II.
~
:::>
I
~~
,-
I
I
OVER-VOLTAGE
/.SHUTDOWN
Q.
~
~
0
o
o
....
\.
40
so
120
160
OUTPUT PULSE TIME II's)
o
200
o
5
10
15
20
25
30
35
40
45
50
SUPPLY VOLTAGE (V)
FIGURE 7. TYPICAL OUTPUT CURRENT PULSE WHEN
SWITCHING INTO A LOW IMPEDANCE (10), OR
SHORTED LOAD. FOR THE CONDITIONS SHOWN,
OUTPUT CURRENT LIMITING IS -1.7A
3-9
FIGURE
8. TYPICAL IDLE CURRENT vs SUPPLY VOLTAGE
WITH NO LOAD
HIP 1031
Half Amp High Side Driver with
Overload Protection
PRELIMINARY
March 1994
Features
Description
• Over Operating Range: -40oC to +125 0 C
• 1.0V Max V SAT at O.6A
• 4.5V to 25V Power Supply Range
The HIP1031 is a High Side Driver Power Integrated CirCUIT
designed to switch power supply voltage to an output load. It
is the equivalent of a PNP pass transistor operated as a
protected high side current switch in the saturated ON state
with low forward voltage drop at the maximum rated current. It
has low output leakage and low idle current in the OFF state.
• Over·Voltage Shutdown Protected
• Over·Current Limiting
The Functional Block Diagram for the HIP1031 shows the
protection control cirCUIT functions of over-current. overvoltage
and over-temperature. A small metal· resistor senses
overcurrent in the power supply path of the pass transistor
and load. Overvoltage detection and shutdown of the output
driver occurs when a comparator determines that the supply
voltage has exceeded a comparator reference level. Overtemperature is sensed from a VSE differential sense element
that is thermally close to the output drive transistor. In addition
to the input detected overvoltage protection, negative peak
voltage of an inductive load is clamped with an internal zener
diode. An internal bandgap supply voltage source provides a
stable voltage reference over the chip operating temperature
range, providing bias and reference control for the protection
circuits.
• Thermal Limiting Protection
• 60VpK Load Dump
• Reverse Battery Protection to -16V
Applications
• Motor Driver/Controller
• Driver for Solenoids, Relays & Lamps
• MOSFET and IGBT Driver
• Driver for Temperature Controller
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
HIP1031AS
-40°C
to +125°C
The HIP1031 is particularly well suited for driving lamps,
relays, and solenoids in automotive and industrial control
applications where voltage and current overload protection at
high temperatures is required. The HIP1031 is supplied in a 5
lead TS-OOl AA Power SIP package.
PACKAGE
5 Lead TS-001M SIP
Pinout
Functional Block Diagram
···.- --.., ......... -_ .... -- ....................... _........ _.. _......-..-...... -_ ..-.....-..... --..........
HIP1031 (SIP)
TOP VIEW
:J)iili ~~~t;;:~l)
f,1o~III
L
.. ::. _
1 vee (SUPPLY)
"'
~
Vee:
1
: Your
:
VBATT :
SUPPLY:
'
1""'""----. ..."--~~ 1""'"--"1 ..._J........
- -
:
:
: ~......
..... .... .....
.........................
:
·:________________________________
~
~.....,,.....
.Jri~N~:
~
CONTROL:
........................
~.;~;
.................
GND
CAUTION: These devices are sensttive to electrostatic discharge. Users should follow proper I.C. Handting Procedures.
Copyright © Harris Corporation 1994
3-10
~
GND
File Number
3596.2
Specifications HIP1031
Absolute Maximum Ratings
Thermal Information
Supply Voltage, Vcc ............ See O.V. Shutdown Limit, Vovso
Input Voltage, V1N (Note 1) .......•............•. -0.8V to +7V
Load Current, lOUT' . . • . . . . • . . . . . • . . . . . . . .. Internally Limiting
Load Dump (Survival) ...............•....••....... ±60VPK
Reverse Battery . . . . • . . . . . • . . . • • . . . • . • . . . . . . . . . . . • .. -16V
8JA
8JC
Maximum Thermal Resistance
Plastic SIP Package . . . . . . . . • . . • • . . • .. 500 CfW
4°CfW
Maximum Power Dissipation, (Note 2)
AtTA = +125°C,lnfinite Heat Sink ..•................. 6.25W
Maximum Junction Temperature, TJ ..........•.••...... 150°C
Ambient Operating Temperature .•..........•.• -40oC to + 125°C
Storage Temperature Range .•.•....•..••.••.• -40°C to +150°C
Lead Temperature (Soldering lOs max) •.••••..•..•..... 265°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at thess or any other conditions above those indicated in the opsrational sBc/ions of this specifICation is not implied.
Electrical Specifications
PARAMETERS
Operating Voltage Range
Over-Voltage Shutdown
TA = -4O"C to +125°C, V1N = 2V, vcc = +12V, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
Vce
Vovso
Rl = lKO, V1N = 2V
MIN
TVP
MAX
UNITS
4.5
-
25
V
26
33
38
V
150
-
°C
(Vce - 62)
(Vee - 37)
(Vee - 28)
V
0.7
1.1
1.7
A
Over-Temperature Limiting
Tso
Negative Pulse
Output Clamp Voltage
VCl
ICl = -100mA, Vcc = 4.5V to 25V,
V1N =0.8V
Short Circuit Current Limiting
Ise
Note 3
Input Control ON
VIH
Input Control OFF
Vil
Input Current High
IIH
VIN = 5.5V, Vcc = 6V to 24
10
Input Current Low
III
VIN = 0.8V, Vec = 6V to 24V
10
V
2.0
-
0.8
V
-
40
J.lA
30
J.lA
A
Supply Current, Full Load,
Input Control ON
leeMAX
VIN = 2V; lOUT = 0.55A
-
-
0.6
Supply Current, No Load,
Input Control OFF
ICCMIN
VIN = OV; lOUT = OA
-
55
100
J.lA
lOUT = 0.6A, Vee = 4.SV to 2SV
-
-
1.0
V
VIN = O.BV, Vee = 6V to 24V
-
-
SO
J.lA
ioN
Rl = 800, TA = +12SoC
-
6
20
!IS
loFF
Rl = BOO, TA = +125°C
-
17
65
!IS
Input-Output Forward Voltage
Drop (Vec - VOUT)
Output Leakage
Turn-On Time
Turn-OFF Time
VSAT
IOUT_lK
NOTES:
1. The Input Control Voltage, VIN may range from -0.85V to +7V for a Vcc supply voltage of OV to +25V.
2. The worst case thermal resistance,eJc for the SIP T0-220 S pin package is 4°CIW. The calculation for dissipation and junction temperature
rise due to diSSipation is:
Po = (Vce-VouT)(IOUT) + (VCc)(ICCMAX -lOUT) or (VCcl(lCCMAX) - (Vour)(IOUT)
TJ = TAMSIENT + (Po) (8Jcl for an infinite Heat Sink.
Refer to Figure 1 for Derating based on Dissipation and Thermal Resistance. Derating from 150°C is based on the reciprocal of thermal
resistance, 8Jc+8 HS' For example: Where 8JC = 4°CIW and given eHS = 6°1W as the thermal resistance of an external Heat Sink, the
junction-to-air thermal resistance, 9JA = 1OOCfW. Therefore, for the maximum allowed dissipation, derate 0.1 Wf'C for each degree from
TAMS to the maximum rated junction temperature of 150°C. If TAMS = 100°C, the maximum Po is (150 - 100) x O.IWf'C = 5W.
3. Short Circuit current will be reduced when Thermal Shutdown occurs. Testing of a short circuit current may require a short duration pulse.
3-11
HIP1031
Typical Application
HIP1031 HIGH SIDE DRIVER
.......
--- -_ ...... ---- -_ ........ -- --- -_ .... -_ ...... -_ .... _.... _.......................... -...... .,,
~----------~t---------------~~.,
:,,,,
LOADS:
RELAYS
SOLENOIDS
LAMPS
MOTORS
SVIN
5}-~------------------------------~
GND
GND
Typical Performance Curves
16
"
14
WITH EXT. &oCIW
r!!EATSINK
t\
0
~
I-
1\
I"
8
1\
2
a
-SO
-25
0
a:
,
I' I'-
4
0.6
r-
I
I
I
I
I
I
HIP1031 VSAT WITH
200 RESISTIVE LOAD
I
~
g
1
0.4
I
c
a: 0.3
~
~
"-
~
/
J
J...1-t""I
I--""
l I =I J I--'"
VSAT AT lOUT
0.2
VSAT AT lOUT
-50
~
..... i'"""
=0.25A
1 1
-25
0
25
50
75
FIGURE 2. TYPICAL V SAT CHARACTERISTIC
TEMPERATURE
3-12
~
0.5A
100
AMBIENT TEMPERATURE <"C)
FIGURE 1. DISSIPATION DERATING CURVES
'"
0.1
o
150
I
=
w 0.5
!:l
I
I
I
I
I
VSAT AT lOUT 0.75A
c
~
0
25
50
75
100
125
AMBIENT TEMPERATURE ("C)
--
~ 0.7
Q.
HEAT SINK)
1\
1\
6
0.8
WITH EXT.
OOCIW
HEAT SINK
(INFINITE
vs
125
HIP 1090
HARRIS
SEMICONDUCTOR
Protected High Side Power Switch
with Transient Suppression
April 1994
Features
Description
•
•
•
•
The HIP1090 is a Protected Power Interface Switch
designed to suppress potentially damaging overvoltage
transients with peak voltage source inputs ranging up to
±90V in amplitude. It is designed to be operated in a 'hardwired' pass-thru mode or as a high side power switch which
controls the current flow through a PNP pass transistor of
the IC. In either mode The HIP1090 has a low saturated
forward voltage drop. The protected load circuit is connected
to the output of the IC. As such. the HIP1090 operates as a
transient suppressor where the PNP drive transistor is
switched off when V IN is greater than the Overvoltage Shutdown range of 16V to 19V. Shutdown also occurs when VIN
is less than the forward turn-on threshold of approximately
2.5V. including the negative voltage range.
±90V Transient Suppression
4V to 16V Operating Voltage
1A Current Load Capability
Low Input-Output Voltage Drop With Controlled Saturation Detector for
- Fast Low Current Turn-OFF
- Reduced No-Load Idle Current
• Over-Voltage Shutdown Protection
• Short Circuit Current Limiting
• Over-Temperature Limiting Protected
• Thermal Limiting at TJ = +150°C
• -40°C to +105°C Operating Temperature Range
Applications
The merits of transient suppression depend on the required
integrity of the applications load elements. Instrument panel
Signal warning lights for critical functions such as over
temperature or low fluid levels can be protected by the
HIP1090 against high level transient voltages and double
battery conditions that may potentially cause bulb burnouts.
The HIP1090 may be used to protect the power supplies of
small signal or logic circuits with voltages ranging from 4V to
16V. effectively blocking higher peak voltages.
• Electronic Circuit Breaker
• Transient Suppressor
• Over-Voltage Monitor
• High Side Driver Switch for
- Relays
• Solenoids
- Heaters
- Motors
- Lamps
Ordering Information
PART
NUMBER
HIP1090AS
TEMPERATURE
RANGE
PACKAGE
-40°C to + 105°C
Pinout
TO-220AB SIP
Functional Block Diagram
". . . _.............. _1_ . . _______ ................ , .................................. ........ ____ . . . ___ .. __ ........ __ ,
HIP1090 (SIP)
TOP VIEW
,
1
NOTE:
HEAT SINK TAB -->
INTERNALLY
CONNECTED
TOPIN2
0
1 2 3
III
I
:
,
~
Rs
: 3
VIN
:
Your
(Vee OR
:
(TO LOAD)
VBATT)
I
The HIP1090 has internal current limiting protection in the
range of 1A to 2A for short circuit to ground conditions and
thermal shutdown protection when the junction temperature
is greater than 1500 C It is capable of driving resistive,
inductive or lamp loads (such as lamps No. 168 or 194) with
minimum risk of damage under harsh environmental stress
conditions. The HIP1090 is supplied in a 3 lead TO-220AB
package.
,,
,,
,,,
,,,
,,,
,',...... _ ............... __ .......... __ ........ __ ..................................................
I
,
.. ... __ ........... , __ ..... _ .......... J
VCON
I I I
(CONTROL OR GND)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-13
File Number
3398.2
wen
ow
-::r:
en()
::r:1-3=
::r:en
(!J-
Specifications HIP1090
Absolute Maximum Ratings
Thermal Information
Input (Supply) Voltage, VIN (Control Pin Reference)......... ±24V
Transient Max Voltage, VIN (15ms). • . . • . . . . . . . . • . . . . • .. ± 90V
Load Current, lOUT' ................... Short Circuit Protected
Thermal Resistance
9JA
Plastic SIP Package • . . . . • . . . . . . . . . .
500 C/W
Maximum Power Dissipation, (Note 4)
At TA = +105°C, Infinite Heat Sink ................... 11.25W
Junction Temperature .............................. +150°C
Ambient Temperature Range . . . . . . . . . . . . . . .. -40°C to +1 05°C
Storage Temperature Range ..•......•..•..... -400 C to + 150°C
Lead Temperature (Soldering During) ..•...•....•..•... +265°C
1/16 ± 1/32 inch (1.59 ± 0.79mm) from ease for lOs maximum
CAUTION: Stresses abo... those listed in "Absolute Maximum RaUngs" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other condffions abo... those indicated in the operational sections of this specification is not implied.
Electrical Specifications TA = -400C to +105°C; VIN = 4V to 16V; VeON = GND or OV, Unless Otherwise Specified
PARAMETERS
Input (Supply) Voltage Operatfng
Range
MIN
TYP
MAX
UNITS
(Note I); Also, see Figure 4 for
Expanding VIN Range
4
-
16
V
-
V
SYMBOL
VIN
TEST CONDITIONS
Input Voltage Threshold for Forward
Turn-On to Load
VTHO
Load = 1k.Q
-
2.5
-
Input Voltage for Output Shutdown
VSHSO
(Note 2)
16
Output Shutdown Leakage
IlEAK1
VIN = 19V and 24V; Load = I k!l
Output Cutoff Leakage
IlEAK2
VIN = 16V; Control Open; Load = I kQ
-
Thermal Shutdown Temperature
Tso
Maximum Output Transient Pulse
Current
lounTran)
VIN = ±90V for 15ms, VOUT = 14V
Maximum Control Transient Pulse
Current
IOON(Tran)
VIN = ±90Vfor 15ms, VOUT = 14V
Short Circuit Current
VIN = 4V, lOUT = 175mA
VIN = 9V, lOUT = 500mA
VIN = 16V, lOUT = SOOmA
VIN = 16V, lOUT = lA
Control Current
lOON
VIN = 16V,IOUT = 100mA
IlA
°C
-20
+20
mA
-50
+50
mA
-
-
-
-
-
Switch VIN 5.5V to OV(GND); Measure
VOUT (to 90%); Load = I k.Q (Note 3)
-
ioN
See Figure 3 and Figure 4 (Note 3)
IoFF
See Figure 3 and Figure 4 (Note 3)
ioN
Turn OFF (Fall Time);
'Pass-Thru· mode
IoFF
Turn ON (Rise Time);
High Pass Switch mode
Turn OFF (Fall Time);
High Pass Switch mode
2
A
0.25
V
0.65
V
1.05
V
25
mA
50
mA
O.S
-
Turn ON (Rise Time);
'Pass-Thru' mode
VIN = 16V, lOUT = IA
Switch VIN OV(GND) to 5.5V; Measure
VOUT(to 90%); Load = lk!l (Note 3)
V
I1A
-
-
VIN = 16V, lOUT = SOOmA
19
100
-
I
150
1
Isc
Input-to-Output Voltage Drop
-
V
50
mA
20
j!S
-
20
j!S
-
15
-
j!S
-
15
-
j!S
NOTES:
1. The Input Operating Voltage is not limited by the threshold of Shutdown. The VIN voltage may range to ±24V while the normal functional
switching range is typically +2.5V to +17 .5V (reference to VOON)'
2. The Output Drive is switched-off when the Input voltage(Supply pin), referenced to the Control pin exceeds the threshold shutdown
VSHSD or the input voltage Is less than the forward turn-on threshold (Including negative voltages within the transient peak ratings).
3. TON and TOFF times include Prop Delay and Rise/Fall time.
4. The worst case thermal resistance,9 JC for the SIP TO-220 is 4°CIW. The calculation for dissipation and junction temperature rise due to
dissipation is:
Po =(VIN -VOUT ) + (VIN)(l ooN )
TJ = TAMBIENT + (Po) (9Jclfor an Infinite Heat Sink.
Derating from 150°C is based on the reciprocal of thermal resistance, 9JC+8HS' For example: Where 9JC 4°C/W and given 9HS SOIW as
the thermal resistance of an external Heat Sink, the junction-te-air thermal resistance, 9JA = 100 CIW. Therefore, for the maximum allowed
dissipation, derate O.IWf'C for each degree from TAMB to the maximum rated junction temperature of 150°C. If TAMB = 1000C, the maximum
Po is (150 - 100) x O.IWI'C = 5W.
=
3-14
=
HIP1090
Applications
The HIP1090 may be used as a "hard-wired pass-thru"
device to protect the load from source voltage transients or
may be used as an active high side power interface switch
with up to 1A of Load current capability. An ON state
condition of (VIN - 4V) S; VCON S; (VIN - 16V) is the normal
range required to activate the high pass switch, allowing the
supply source to conduct through the PNP to the load. When
the control terminal, VCON is open, the high pass switch is
open (no conduction). Figure 2 shows an HIP1090
application example with a switch in the VCON terminal. In
comparison to the hard wired circuit of Figure 1 where pin 2
is fixed at ground, pin 2 in the circuit of Figure 2 is switched
from open to ground to turn-ON the high pass switch. Used
,;_ ... ----... --_ .......... -_ .... ., .................... -_ ........... -_ .......................................... '";,
: YIN
Rs
YOUT:
,,
INPUT 1
SWITCH
in this mode, the HIP1090 is both an effective transient
suppressor and a high pass switch. The switch in the VCON
terminal may be active or passive and conducts typically less
than SOmA of current. The HIP1090 used in the controlled
switching mode retains all of the protected features of the
device. In either circuit the output capacitor may be
increased in size to hold charge longer during transient
interruptions at the input. The charge duration for larger
capacitors or for lamp loads is tolerated because of the
internal short circuit current limiting protection. Sustained
short circuits may cause the junction temperature to reach
the thermal shutdown temperature (1500 C).
1 :,
,,:
,,
,
,,:
YSATT
r - - -..... p-Io--"",", ,.........-
..... _--1....._.
DASH PANEL LOAD
3
TO OTHER
UGHTS
AND
INSTRUMENTS
r - i - -.....
I...-~"" ....--r--ll...-~........-r-~ I...-~""
,
,
. . . . . . . . . . . . . . . _ _ .. _ _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ _ ..
. . . . _ _ _ . . . . _ _ .. _ _ _ _ . . . . . . . . 4
2
YCON
(CONTROL OR GND)
FIGURE 1. TYPICAL APPLICATION OF THE HIP1090 AS A TRANSIENT SUPPRESSOR IN A "PASS-THRU" MODE
,. .. -........... -.......... -- -_ ...................................... -....................................................,,
INPUT 1
YIN
Rs
VOUT: 3
VBATT--~-+----------~~~~------------~
,,
,,,
_ - - _ . p-Io--"",", ,.........-
.
L-....,._...
..... r - -..........
~-'T"'".............,._... I.~.....,r-"
................ ___ ............ _____ .. __ ........ ________ .... _ .. __
2
NOTE:
=
V LOAD VBATT - V SAT
VSAT TYP < O.BV allA
r - i - -.....
!,
:,,
,,
........,._.... :
,
....... _ ...... _______ ___ ... ,J
YCON
(CONTROL)
OFF~ ON
SWITCH"*"
FIGURE 2. TYPICAL APPLICATIONS OF THE HIP1090 AS A TRANSIENT SUPPRESSOR IN A HIGH PASS SWITCH MODE
3-15
HIP 1090
Figure 3 shows the pulsed output switching characteristics of
the HIP1090 as a high side driver. A small delay step is
noted on the rising edge due to the hold-off of a VCESAT
detector circuit. The VCESAT circuit senses the saturation
level of the PNP pass transistor and controls the drive as a
ratio of load current. As the load current is reduced, the drive
current to the output transistor is reduced. Under low current
operation, the saturation level is controlled and the turn-OFF
switching time js much faster. The control switching element
is shown as a 2N5320 NPN transistor but may be any open
collector or MOS gate. A pull-up resistor of 2k.Cl is used for a
slight improvement in the turnoff fall time but is not an
essential requirement. The VCON terminal may be controlled
with a mechanical switch or may be controlled from any
driver output that can sink the worst case condition of pin 2
current, ICON when the output load current is increased to 1A
(typically 50mA).
The circuit of Figure 4 shows how the HIP1090 transient
suppression voltage shutdown threshold may be increased
by using a zener diode from the VCON terminal to the collector terminal of the transistor switch. The preferred method is
to use a zener diode for a fixed level shift. While a resistor in
place of the zener diode having the same voltage drop will
work well, the parametric variation of the ICON current will
cause variations of the Over-Voltage Shutdown Threshold.
In this circuit, a 10V zener provides a typical overvoltage
threshold shift to -27V. The threshold for overvoltage shutdown is referenced to the (V IN - VCON ) voltage difference.
+24V
ON
+16V
(SUPPLY INPUT)
21<0
OPTIONAL
HIP1090
n
'------~ VeON
OFFJ
1kU
L-
.
15
10
--1----------,
Your
s!
o
I
_ _ _oJ
_ _ ~ ...... __ ......................
I
:
TON
,
,
:
-1-........ __ ...... ~I
I
:
:.......
~-15-f18-~..~:
::;J
:
I
, VB
I
TOFF
_
I ..:
I'
15f18
2N5320
OR EQUIVALENT
L-
Also, it is important to note that high peak current values
may be reached when driving nonlinear and inductive loads.
The peak output current of the HIP1090 is self limiting in the
1A to 2A range to protect against short circuit conditions.
Sustained high peak current may increase the junction temperature to 1500 C and cause thermal shutdown. When this
happens, the output current will fall off briefly before recovering, unless the over-temperature condition is sustained.
Internally, both input and output overvoltage conditions are
sensed to protect the circuit, making the high levels of transient voltage ratings possible. Sustained voltage ratings of
±24VDC with transient ratings to ±90V allow a wide variety
of applications in high stress environments.
:,
,:
10V
1kU
0-
FIGURE 4. A TYPICAL APPLICATION CIRCUIT THAT USES A
ZENER TO THE VeoN TRANSISTOR SWITCH TO
THE
OVERVOLTAGE
SHUTDOWN
RAISE
THRESHOLD
2N5320
OR EQUIVALENT
VB 0-
n
OFFJ
24Q
_
(CONTROL PIN)
ON
HIP1090
(SUPPLY INPUT)
21<0
OPTIONAL
'
.. :
1
FIGURE 3. TYPICAL ON-OFF SWITCHING CHARACTERISTIC
OF THE HIP1090 USING AN NPN TRANSISTOR TO
SWITCH THE VCON INPUT TERMINAL
Except for the VCESAT detector circuit, the HIP1090 is a
higher current version of the CA3273 high side driver, which
turns-on without the delayed step on the leading edge of the
output pulse; switching with a typical TON time of -O.5Ils.
The CA3273 has a higher transient suppression threshold.
3-16
HIP1090
Typical Performance Curves
60
Ci'
.E.
30
50
I-- I-
N
z
~
RLOAO= 16!l
VCON=GND
40
IZ
w
II:
II:
i3.....
0
30
20
II:
IZ
0
(.)
,
TA = +2S"C
---
1/
/
V
V
/
Ci'
.E.
25
N
VOUTOPEN
~ 20
I-
Z
w
II:
II:
15
~
(.)
..... 10
0
II:
I-
Z
0
(.)
5
o
5
TA = +2SoC
VCON-GND
z
10
00
I
I
r--
10
15
20
I
o
VIN SUPPLY VOLTAGE (V)
I
.E.
1000
~
800
-
w
CJ
600
~
z
400
"Ie
200
::l
~
II)
I
TA=+250C
II
RLOAO= 16!l
VCON=GND
V
L
........... ./'
>
o
o
15
20
FIGURE 6. CONTROL (QUIESCENT) CURRENT CHARACTER·
ISTIC WITH NO LOAD
g
.,
10
VIN SUPPLY VOLTAGE (V)
FIGURE 5. CONTROL (QUIESCENT) CURRENT CHARACTER·
ISTIC WITH LOAD
:;-
5
0.5
1.0
1.5
LOAD CURRENT (A)
FIGURE 7. SATURATION (VIN • VOUT) CHARACTERISTIC
3-17
HV400
High Current MOSFET Driver
April 1994
Features
Description
• Fast Fall Times •••••••••••••.••••• 16ns at 10,OOOpF
The HV400 is a single monolithic. non-inverting high current
driver deSigned to drive large capacitive loads at high slew
rates. The device is optimized for driving single or parallel
connected N-channel power MOSFETs with total gate
charge from 5nC to > 1OOOnC. It features two output stages
pinned out separately allowing independent control of the
MOSFET gate rise and fall times. The current sourcing output stage is an NPN capable of 6A. An SCR provides over
30A of current sinking. The HV400 achieves rise and fall
times of 54ns and 16ns respectively driving a 10.000pF load.
• No Supply Current in Quiescent State
• Peak Source Current ••••••••••••••••••••••••.• 6A
• Peak Sink Current ••••••••••.••••••••••••.••• 30A
• High Frequency Operation ••••••••••••.•••• 300kHz
Applications
• Switch Mode Power Supplies
Special features are included in this part to provide a simple.
high speed gate drive circuit for power MOSFETs. The
HV400 requires no quiescent supply current. however. the
input current is approximately 15mA while in the high state.
With the internal current steering diodes (pin 7) and an
external capacitor, both the timing and MOSFET gate power
come from the same pulse transformer; no special external
supply is required for high side switches. No high voltage
diode is required to charge the bootstrap capacitor.
• DCIDC Converters
• Motor Controllers
• Uninterruptible Power Supplies
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
The HV400 in combination with the MOSFET and pulse
transformer makes an isolated power switch building block
for applications such as high side switches. secondary side
regulation and synchronous rectification. The HV400 is also
suitable for driving IGBTs. MCTs. BJTs and small GTOs.
PACKAGE
HV400lP
8 Lead Plastic DIP
HV400lB
8 Lead Plastic sOle (N)
HV400MJ/BB3
-55°C to +125°C
The HV 400 is a type of buffer; it does not have input logic
level switching threshold voltages. This single stage design
achieves propagation delays of 20ns. The output NPN
begins to source current when the voltage on pin 2 is
approximately 2V more positive than the voltage at pin 8.
B Lead Ceramic SBDIP
The output SCR switches on when the input pin 2 voltage is
1V more negative than the voltage at pins 3/6. Due to the
use of the SCR for current sinking. once the output switches
low, the input must not go high again until all the internal
SCR charge has dissipated. 0.5J.ls - 1.5J.ls later.
Pinout
08
Schematic
HV400 (POIP, SBOIP, SOIC)
TOP VIEW
V+ SUPPLY
PIN 1
~1"111111"11""""'1"""""""'""""'1
PIN 2
,
•
~
~
!
03
D2
~
SOURCE OUTPUT
INPUT 2
7
DIODES
SINK OUTPUT 3
6
SINK OUTPUT
GND 4
5
GND
PIN3
. 1
yQ1
!1
v.. ~
Q2
!R3
R4
t~
~
R2
:
"
08
~"D6
"SCR
R1
~N7
~ PIN 6
~____~____-,7
;
•
:~ PIN 8
"".
:
~
~D4"
~
~~ D1~
~
07!
1•
,
•
PIN 4 ~",,,,,,,,,,,,,,,,,,,",",,","",,,,""",,r-o PIN 5
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
.
3-18
File Number
2850.1
Specifications HV400
Absolute Maximum Ratings
Thermal Information
Voltage Between Pin1 and Pin 4/5 . ...................... 35V
Input Voltage Pin 7 (Max) ........................ Pin 1 + 1.5V
Input Voltage Pin 7 (Min) ....................... Pin 415 -1.5V
Input Voltage Pin 2 to Pin 415 • ...................... .. +1- 35V
Input Voltage Pin 2 to Pin 6 ............................ -35V
Maximum Clamp Current (Pin 7) ....•.....•..•.......... ±300mA
Thermal Resistance
SJA
PDIP .•.•..•.••..•.•.•••.•.•...•• 1500 CNI
SOIC .•..•.••..............•••.•. 1700 CNI
91°CNI
25°CIW
SBDIP ..•........•.•..••.•••••.••
Power Dissipation at TA = +250 C
PDIP •....••...••..•..••..••••.••••.•..•..•..•.. 0.8W
SOIC •..•.•.....•.•••.••..••••.•.••..•..•..••.•. 0.7W
SBIP .......................................... 2.33W
Operating Temperature Range
HV400IPIIB ......•..••...••.•...•..•. -400C < TA < +85°C
HV400MJ/883 ....................... -55°C < TA < +125°C
Lead Temperature (Soldering lOS) .....•..•.......•... +265°C
Maximum Junction Temperature •••..•.•.•••••.•.••... + 150°C
Storage Temperature Range ...........•.. -65°C < TA < +150oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may CBuse permanent damage to the device. This is 8 stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VSUPPLY = 15V
SYMBOL
CONDITIONS
TEMPERATURE
MIN
TYP
Input High Differential Voltage
(Pin 2 - Pin 8)
VIH
Your = OV,l our HI = 10mA
+25°C
0.6
Full
0.5
Input Low Differential Voltage
(Pin 2 - Pin 3/6)
VIL
+25°C
Input High Current
IIH
PARAMETERS
MAX
UNITS
1.7
2.8
V
-
3.5
V
-1.1
-0.9
-0.8
V
Full
-1.26
-
-0.65
V
VPIN 1. 2 = 30V, I SOURCE = 0
+25°C
15
18
20
mA
Full
15
22
mA
I SOURCE = 6A, 1j.1S pulse,
VIN = 9V, Your = OV
+25OC
VPIN2 = -30V
+25OC
-80
Full
-120
INPUT (PIN 2)
Input High Current Peak
Input Low Current
IIHP
IlL
Your = 12V, lour LO = -3mA
700
mA
-50
IlA
IlA
SOURCE OUTPUT (PIN 8)
High Output Voltage
VOH
VIN = +V,lour = 150mA
+25°C
12.1
Full
12.0
Peak Output Current
IOP8
VIN = 9V, 1j.1S Pulse,
Vour = OV
+25°C
Output Low Leakage
10l
Your = OV, VIN = OV
+25°C
12.8
13.4
V
13.5
V
6
0
10
Full
A
50
IlA
55
pA
1.0
V
1.05
V
SINK OUTPUT (PIN 3/6)
Low Output Voltage
VOL
VIN = OV,lour = -150mA
+25°C
0.8
Full
0.8
Peak Output Current
loPs
VIN = OV, 5j.1S Pulse,
Vour=4V
+25°C
Output High Leakage
IOH
VIN = 15V
+25°C
0
Full
0
+25°C
0.8
Full
0.8
+25OC
0
Full
0
0.89
A
30
0.3
2
IlA
13.5
IlA
DIODES Dl AND 07 (PIN 7)
Forward Voltage
Reverse Leakage Current
Diode (Pin 7) Stored Charge
VF
IR
ORR
10 = l00mA
VR =30V
10 = l00mA
+25°C
NOTE: Umits are 100% tested at +25°C; limits over the full temperature range are guaranteed but not tested.
3-19
1.03
0.1
6.5
1.4
V
1.6
V
1
IlA
1
pA
nC
Specifications HV400
Switching Time Specifications
PARAMETERS
VSUPPlY
=15V
SYMBOL
CONDITIONS
TEMPERATURE
TR
See Switching Test Clrcuil
Full
Rise Time
MIN
TVP
MAX
UNITS
50
66
ns
Fall Time
TF
See Switching Test Circuit
Full
15
24
ns
Delay Time (Lo to Hi)
TOR
See Switching Test Circuit
Full
20
25
ns
Delay Time (Hi to Lo)
TOF
See Switching Test Circuit
Full
17
28
ns
Minimum Off Time
TOR
See Switching Test Circuit
Full
900
1500
ns
NOTES:
1. Switching times are guaranteed but not tested
2. Typical values are for +25°C
Switching Diagram and Test Circuit
INPUT
10%
10%
OV----"I
TOR
90%
OUTPUT
+V
C1
330l1F
T
SOV "
1N9l4
,,,
2 :
1sV -------~
GND --- - '
"-
INPUT
son SOURCE
(RISE & FAll nMES <10n8)
,,
,
,
,
,,,
•,
,,,
,,
··
·
..r-".:.:.. l2.8V
O.9V
RL
lOOK
3-20
OUTPUT
HV400
HV400 Switching Test Circuit
Parts List
Rl lOOn 1W Carbon Resistor
J1
R1
R2 Wire
RL 100Kn 1/8W Carbon Resistor
~
C2
C1 330f.1F. 50V Capacitor
C2 1f.1F, 50V Capacitor
U1
J3
CL O.Olf.1F, 50V Chip Capacitor
8
01
P~~~E
PULSE
IN
01 1N914 Diode
J1, J2 PC Mount Banana Jack Johnson 108-0740-001
J3, J4 PC Mount SMA Connector Johnson EFJ142
Ul Harris HV400 I.C.
J1
4.2 •
a
o
3.5 •
HV400
HV400
IN
Ui
GND
o
G)
HV400 AC TEST BOARD
3-21
OUT
[J
HV400
Pin Descriptions
SYMeOL
DESCRIPTION
DC INPUT PARAMETERS
VIH
The differential voltage between the input (Pin 2) to the output (Pin 8) required to source 10mA
VIL
The differential voltage between the input (Pin 2) to the output (Pins 3, 6) required to sink 3mA
IIH
The current required to maintain the input (Pin 2) high with lOUT = OA
IIHP
The Input (Pin 2) current for a given pulsed output current
IlL
The current require to maintain the input (Pin 2) low
DC OUTPUT PARAMETERS
=V+
VOH
The output (Pin 8) voltage with Input (Pin 2)
lops
The pulsed peak source current form output (Pin 8)
10L
The output (Pin 8) leakage current with the input (Pin 2)
VOL
The output (Pins 3, 6) voltage with the input (Pin 2)
lops
The pulsed peak sink current into output (Pins 3, 6)
10H
The output (Pins 3, 6) leakage current with the input (Pin 2)
VF
The forward voltage of diode Dl or D7
IR
The reverse leakage current of diode D1 or D7
ORR
=Ground
=Ground
=V+
The time integral of the reverse current at turn off
AC PARAMETERS (See Switching Time Specifications)
TR
The low to high transition of the output
TF
The high to low transition of the output
TOR
The output propagation delay from the input (Pin 2) rising edge
TOF
The output propagation delay from the input (Pin 2) falling edge
TOR
The minimum time required after an output high to low transition before the next Input low to high transition
3·22
HV400
Application Information
Circuit Operation
The HV400's operation is easily explained by referring to the
schematic. The control signal is applied to pin 2. If the
control signal is about 2V above pin 8, the output NPN 01
turns on charging the MOSFET gate from a capacitor
connected to pin 1. Resistor A4 helps keep the SCR off by
applying a reverse bias to the SCR anode gate.
When the control input drops about 1V below pin 3/6, PNP
02 turns on which triggers the SCR by driving both the
anode and cathode gates. The SCR discharges the
MOSFET gate and when its current becomes less than
10mA, it turns off. Transistor 02 conducts any gate leakage
currents, through resistors A 1 and R2, once the SCA turns
off. Figure 7 shows the output characteristics before the
SCR turns on and after it turns off. When the SCA turns on,
resistor A4 provides a path to remove 01 base charge.
Resistor R3 provides the base current for 02 to reduce the
turn off delay time. Resistors Rl and R2 reduce the SCA
recovery time.
The two diodes connected to the diode input pin 7 provide
some operation flexibility. With pins 2 and 7 connected
together, diode 01 provides a path to recharge the storage
capacitor once the MOSFET gate is pulled high and, along
with diodes 02 and 03, keeps 01 from going into hard
saturation which would increase delay times. Diode 07
would clamp the input near ground and provide a current
path if an input DC blocking capacitor is used.
Alternatively, pin 7 can be connected to pin 6 so that the
SCA and NPN 01 don't have to pass reverse current if the
output "rings" above the supply or below ground. When high
performance diodes are required, pin 7 can be left
disconnected and external diodes substituted.
The diodes in series with pin 2 decouple the input from the
output during negative going transitions. The absence of
input current turns off 01 and allows 02 to trigger the SCA.
Diode 08 turns off 02 once the SCA turns on pulling the output low, otherwise 02 would saturate and slow down circuit
operation. In addition, the diodes 02, 03 and 08 improve
noise immunity by adding about 2.5V of input hysteresis.
The HV400 is capable of large output currents but only for
brief durations due to power diSsipation.
Circuit Board Layout
PC board layout is very important. Pins 3 and 6 should be
connected together as should pins 4 and 5. Otherwise the
internal interconnect impedance is doubled and only half of
the bond wires are used which would degrade the reliability.
The bootstrap capacitor should hold at least lOx the charge
of the MOSFET and should be connected between pins 1
and 4/5 with minimum lead lengths and spaCings. Likewise,
the HV400 should be as close to the MOSFET as possible.
Any long PC traces (parasitic inductances) between the
MOSFET gate and pins 8 or 3/6 or between the source and
pins 4/5 should be avoided. Inductance between the HV400
and the MOSFET limit the MOSFET switching time. If they
are too large, the HV400 may operate erratically as
discussed below.
Cross Conduction Faults
It is possible to have both 01 and the SCR on at the same
time resulting in very large cross conduction currents. The
SCA has larger current capacity so the output goes low and
the storage capaCitor is discharged. The conditions that
cause cross conduction and precautions are discussed
below.
Minimum Off Time
The SCR requires a recovery time before voltage can be
reapplied without it switching back on. Figure 13 shows how
this SCR recovery time, called "minimum off time" (TOR)' is a
function of the load capacitance. If the input voltage goes
high before this recovery time is complete, the SCR will
switch back on.
Note that reverse current flowing through the SCR, for
example due to load inductance ringing, extends the
minimum off time. Since the minimum off time is really
dependent upon how much stored charge remains in the
SCA when the anode (pin 3/6) is taken pOSitive, it may vary
for different applications. Figure 13 indirectly shows that the
minimum off time increases with larger currents. It also
increases.at elevated temperatures as shown in Figure 14.
Excessive ringing increases the minimum off time since the
stored charge doesn't begin to dissipate until the current
drops below 10mA for the last time. Aising anode voltage
acts on the internal SCR capacitance to generate its own
triggering current. The excess stored charge increases this
capacitance. Faster rise times and/or higher voltages also
increase the amount of internal trigger current from the internal capaCitance so applications with larger dVidt require
longer minimum off times.
The minimum off time must be considered for all occurrences of SCA current. For example, in a half bridge switch
mode power supply, there are two MOSFET's connected to
the transformer primary. Assume that the high side MOSFET
switch is off. When the low side MOSFET switch is turned
on, the HV400 driving the high side MOSFET will have to
sink gate current from C gd and will have to source gate
current when the low side MOSFET switches back off. Both
of these current pulses will try to flow through pin 3/6 since
the pin 8 output is turned off. Sourcing current from pins 3/6
through the SCR is possible, the pin 3/6 voltage becoming
negative with respect to pins 4/5 (See Figure 8). But a better
practice would be to connect a Schottky diode between pins
4/5 (anode) and 3/6 (cathode) so reverse current does not
flow through the SCA.
False SeA Triggering
The SCR may be triggered inadvertently. The output may
overshoot the input due to inductive loading or over driving
the output NPN (allowing it to saturate). Whenever pin 6 is
more positive than pin 2 by lV, the SCR is triggered on. Also,
3-23
HV400
if the output rises too rapidly, greater than 0.5V/nS, the SCR
may self trigger. Both issues are resolved by minimizing the
load inductance and inserting sufficient resistance, usually
0.1 to 10 ohms. between pin 8 and the load.
be capable of dissipating the energy stored in the
transformer. The load may be connected to either the power
MOSFET drain or source.
7' .... •........................ •............11
Vs
A very fast negative going input voltage can result in
minimum off times of about 2.5I1s. If the output can not keep
up with the falling input, the stored charge 01 diode D4 is
transferred into the base of 02. This excess charge in 02
must have time to dissipate. Otherwise, when pin 3/6 goes
positive. 02 will turn on and trigger the SCA. An external
diode in series with pin 2, as shown in Figure 1, will prevent
D4 from discharging into the base of 02 but that will also
reduce the output voltage by the forward voltage of that
diode.
4· .......................................... ; 5 POWER
HV400
Internal Diodes
The internal diodes connected to pin 7 are provided for
convenience but may not be suitable for large currents.
Since they are part of the integrated circuit, they are
physically small, operate at high current densities, and have
long recovery times. Figure 15 shows that their forward
characteristics degrade above 100mA. In addition, Figure 16
shows their reverse recovery charge as a function of forward
current. The product of this charge, the applied reverse
voltage and the frequency is the additional power dissipation
due to the diodes. For stored charge calculations, use the
peak forward current within lOOns of the application of
reverse bias. In addition to the extra power dissipation, the
capacitance of Ihese diodes may extend the switching delay
times.
Power Dissipation Calculations
The power required to drive the MOSFET is the product of
its total gate charge times the gate supply voltage (maximum
voltage on HV400 pin 1, 2 or 7) times the frequency.
Assuming that the MOSFET gate resistance is negligible,
this power is dissipated within the HV400. If resistors are
placed between the HV400 and the MOSFET, then some of
the power is diSSipated in the resistors, the percentage
depending upon the ratio of resistors to HV400 output
impedance.
There are two other sources of power diSSipation to
consider. First there is the power in R3 which is the product
of the input pin 2 current and voltage (with no output current)
times the duty cycle. Second is the product of the pin 7 diode
stored charge, which is dependent upon the forward current,
times the applied diode reverse voltage times the frequency.
This information is available from figures 3 and 16 in this
data sheet.
MOSFET
FIGURE 1. UNIPOLAR DRIVE
A diode is added in series with pins 2 and 7 to allow the
transformer secondary to go negative. The charge storage of
the pin 7 diode may cause the turn off delay time to be too
long. Alternatively, pin 7 could be left disconnected and a
second external diode connected between the transformer
(anode) and pin 1 (cathode). In some applications the diode
in series with pin 2 may be unnecessary but the -35V input
to output or ground maximum rating should be observed.
Sometimes the volt-second balance is achieved by a pushpull drive on the pulse transformer primary. This is especially
useful if there are two secondary windings driving two
HV400's out of phase such as in a half-bridge configuration
Other times it is more convenient to achieve volt-second
balance by using capacitors to block DC in the primary and
secondary windings as shown in Figure 2. The pin 7 diodes
provide a path for discharging the secondary side DC blocking capaCitor. Both capacitors, CIN and Cs , should be at
least 10 times the equivalent MOSFET gate capacitance.
The HV400 can be used as a current booster for low side
switches by connecting directly to the PWM output. The
circuit would be similar to the switching time test circuit.
It is worth restating that some consideration (and experimentation) should be given to the choice of external components,
i.e. resistors, capaCitors and diodes, to optimize
performance in a given application.
.
.
7, ............ · .............. · .................. · ....,
cs
j(
Applications Circuits
T1
The HV400 was designed to interface a pulse transformer to
a power MOSFET. There must be some means to balance
the transformer volt-second product over a cycle. The
unipolar drive shown in Figure 1 lets the core magnetization
inductance reverse the primary and secondary voltages. The
zener diode on the primary side limits this voltage and must
4 t •••••••••••••••••••••.••••••••••••••.••••••••••••••t 5
HV400
FIGURE 2. BIPOLAR DRIVE WITH DC BLOCKING CAPACITOR
3-24
HV400
Typical Performance Curves
TA = +25°C Unless Otherwise Specified
15
20
,
c
!.
~ 10
J
IL
o
L
"
14
...- r-
".
13
I
12
€
"
~
,
-"":OH
11
1:
~HP7L
..........
8
7
J
6
5
o
800
10
20
30
40
600
500
/
~
400 ~
,
.......
C
!....
300
200
100
0
o
50
VIN - PIN 2 (V)
FIGURE 3. PIN 2 INPUT CURRENT VI INPUT VOLTAGE WITH
ZERO OUTPUT CURRENT
1,.....00'
V
/
700
234
10P8(A)
5
6
FIGURE 4. PIN 2 IIIIP & VOH VI OUTPUT SOURCE CURRENT
10
o
-20
l
/
/~
V
/
4
3
-40
/
/
J
-60
/
-80
/
I
I
-100
-50
-40
o
o
-30
-20
-10
INPUT VOLTAGE - PIN 2 (V)
VPIN2~12V
6
o
1J!A,
10
30
20
FIGURE 6. VOL VI lops (51LS PULSES)
-I
12
3
o
IOP6(A)
FIGURE 5_ PIN 2 IlL VI INPUT VOLTAGE
15
./'
SWEEP
-
-
o
-1
---r-
I""-
-
...... ~
-4
I
10J!A,
100J!A,
R
+2;(oC
SWEEP
VPIN2=OV -
~
,.".1mA
r--
10mA
-6
100mA
IoP6
FIGURE 7. PIN 316 ILLUSTRATING OUTPUT VOLTAGE VI SCR
OUTPUT SINK LATCHING AND HOLDING CURRENT
3-25
~OOC
~50C
I
o
1
lops (A)
2
FIGURE 8. PIN 316 VOLTAGE VI REVERSE CURRENT 300ILS
PULSES
HV400
Typical Performance Curves
+10
....
f
::>-
... >
~-
-V
J
0
f
+10
....
::>
TA = +2SoC Unless Otherwise Specified (Continued)
)
~~
0
/
0
10
50nsJDIV
100
CdnF)
FIGURE9. LOWTOHIGHTRANSIENTRESPONSEWAVEFORMS
(CL 10nF)
=
FIGURE 10. RISE AND FALL TIMES vs CL (V+ = 12V, 15V, 20V)
70
+10
~
....
::>s;-
~-
~
\
~~
0
0
--
1=
........
i!l
'\
+10
60
w
:Ii 50
\
0
....
::>
....E.
TR
40
~
30
V
TOR
~ 20
\
l.--""
•
ui
~
\V
10
TF
TOF
o
-40
·20
0
50nsJDIV
FIGURE 11. HIGH TO LOW TRANSIENT RESPONSE WAVEFORMS
(C L 10nF)
=
+25
+55
+85
TEMPERATURE (OC)
FIGURE 12. RISE, FALL AND DELAY TIMES VB TEMPERATURE
1.3
1.2
v~
...
~ 1.1
:Ii
w
)/
1=
~
1.0
:Ii
SlZ
0.9
:E
0.8
w 2.0
:Ii
"
~
I
I
I
.2_
1=
TOR~)
II:
TOR (+25°C)
o
~ 1.5
:Ii
V
./
!
Z
!i
c
./
~ 1.0
~
,,"'"
!!iz
V
./
V
/'
~
0.5
0.7
1
10
100
-50
CAPACITIVE LOAD (nF)
FIGURE 13. MINIMUM OFF TIME croAl vs CL AT +2SoC
0
+25
+50
+100
+150
JUNCTION TEMPERATURE rC)
FIGURE 14. NORMALIZED MINIMUM OFF TIME croAl vs TEMPERATURE (CL 10nF)
=
3·26
HV400
Typical Performance
~urves TA = +25°C Unless Otherwise Specified (Continued)
01
~ 10.2
....
Z
I
W
II:
II:
1/
~
10
...07
01,07
I'
/
I
::>
0
10~
- -
~
J
10-6
o
0.4
In
0.1
0.8
1.2
1.6
lN914
D4
IIJjI
1/'"
10
2.0
100
1000
FORWARD CURRENT (mA)
VF(V)
FIGURE 15. DIODE 01 AND 07 CURRENT V5 VF
FIGURE 16. DIODE ORR V5 FORWARD CURRENT
8
/
7
6
~ 5
~ 4
-
~
VIH
3
2
o
2
/
700
V /
600
/
/
3
1
400
j
200
/
4
500
300
/
-'
IIHP
o
V
I
100
o
5
6
ioP8(A)
Vertical
Horizontal
l00mAldlv
50nsldlv
FIGURE 17. DIODE 01 REVERSE RECOVERY WAVEFORM
IF = 200mA, 20V REVERSE BIAS
FIGURE 18. VIH AND IIHP V5 IOP8 [Vour (PIN 8)
1115 PULSE]
3·27
=0, V+ =15V,
HV400MJ/883
High Current MOSFET Driver
April 1994
Features
Description
• This Circuit Is Processed In Accordance to MII·Std883 and Is Fully Conformant Under the Provisions
of Paragraph 1.2.1.
The HV400MJ/883 is a Single monolithic, non-inverting high
current driver designed to drive large capacitive loads at high
slew rates. The device is optimized for driving single or parallel
connected N-channel power MOSFETs with total gate charge
from 5nC to >1000nC. It features two output stages pinned out
separately allowing independent control of the MOSFET gate
rise and fall times. The current sourcing output stage is an NPN
capable of 6A. An SCR provides over 30A of current sinking.
The HV400MJ/883 achieves rise and fall times of 54ns and
16ns respectively driving a 10,OOOpF load.
• Fast Fall Times .••••••••••••••• 16ns 811 O,OOOpF
• No Supply Current In Quiescent State
• Peak Source Current ••••.•••••••••••••••••• 6A
• Peak Sink Current ........................ 30A
• High Frequency Operation ....•......••• 300kHz
Special features are included in this part to provide a simple,
high speed gate drive circuit for power MOSFETs. The
HV400MJ/883 requires no quiescent supply current, however,
the input current is approximately 15mA while in the high state.
With the internal current steering diodes (Pin 7) and an external
capacitor, both the timing and MOSFET gate power come from
the same pulse transformer; no special external supply is
required for high side switches. No high voltage diode is
required to charge the bootstrap capacitor.
Applications
• Switch Mode Power Supplies
• DCIDC Converters
• Motor Controllers
• Unlnterruptible Power Supplies
The HV400MJ/883 in combination with the MOSFET and pulse
transformer makes an isolated power switch building block for
applications such as high side switches, secondary side regulation and synchronous rectification. The HV400MJ/883 is also
suitable for driving IGBTs, MCTs, BJTs and small GTOs.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
HV400MJ/883
-55°C to +125°C
The HV400MJ/883 is a type of buffer; it does not have input
logic level switching threshold voltages. This single stage
design achieves propagation delays of 20ns. The output NPN
begins to source current when the voltage on Pin 2 is approximately 2V more positive than the voltage at Pin 8.
PACKAGE
8 Lead Ceramic
SBDIP
The output SCR switches on when the input Pin 2V is 1V more
negative than the voltage at Pins 3/6. Due to the use of the SCR
for current sinking, once the output switches low, the input must
not go high again until all the internal SCR charge has dissipated, 0.51ls - 1.51ls later.
Pinout
OS
Schematic
HV400MJ1883 (SBDIP)
TOP VIEW
V+ SUPPLY
c>--_-~
"-~"~-_---_l(
.
-,J
PIN 2
03
0'1
INPUT 2
7
DIODES
6
SINK OUTPUT
~ 01
02
PIN 8
SOURCE OUTPUT
SINK OUTPUT 3
GNO 4
PIN 1
~ PIN7
PIN3
PIN 6
04
S GNO
~Ir
R4
.....
......
~
r.)Q2 os
r
R3
_II-
D6
fR2
SCR
_~
07
}
R1
PINS
PIN 4
CAUTION: These devices are sensitive to electrostatic discharge. Users should Iollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
3-28
File Number
3584.1
Specifications HV400MJ/883
Absolute Maximum Ratings
Thermal Information
Voltage Between Pin 1 and Pins 415 ..................... 35V
Input Voltage Pin 7 (Max) ......•..........••..... Pin 1 + 1.5V
Input Voltage Pin 7 (Min) ....................... Pin 4/5 -1.5V
Input Voltage Pin 2 to Pin 415 . ....................... .+1- 35V
Input Voltage Pin 2 to Pin 6 ............................ -35V
Maximum Clamp Current (Pin 7) ........•...............±300mA
Thermal Resistance
8JA
8JC
Sidebrazed DIP. . . . . . . . • . . . • . . . . . . .
91°CNI
25°CNI
Power Dissipation at TA = +25°C ........•......•....... 2.33W
Operating Temperature Range
HV400MJ/883 . . . . . . . . . . . . . . . . . . . • . . . -55°C < TA < +125°C
Maximum Junction Temperature .........•....•....... +200oC
Storage Temperature Range .......•...... -65°C < TA < + 150°C
CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions abo... those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Operating Temperature Range ........•.....•• -55°C to +125°C
Operating Supply Voltage •••••..•••...•••.•.•.• + 1OV to +35V
TABLE 1_ DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: Supply Voltage = + 15V, Unless Otherwise Specified
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
UNITS
Input High Differential Voltage (Pin 2 - Pin 8)
VIH
VOUT = OV, lOUT HI = 10mA
1
+25°C
0.6
2.8
V
2
+125°C
0.1
2.3
V
3
-55°C
1.0
3.2
V
1
+25OC
-1.1
-0.8
V
2
+125°C
-0.95
-0.6
V
3
-55°C
-1.2
-0.9
V
1
+25°C
15.0
20.0
rnA
2
+125°C
13.0
18.0
rnA
3
-55°C
18.0
25.0
rnA
1
+25°C
-80
0
I1A
2,3
+125°C, -55°C
-80
0
I1A
1
+25°C
12.1
13.4
V
2
+125°C
12.2
13.5
V
3
-55°C
11.0
13.0
V
1
+25°C
0
50
I1A
2,3
+125°C, -55°C
0
60
IIA
Input Low Differential Voltage (Pin 2 - Pin 3/6)
Input High Current
Input Low Current
High Output Voltage
Output Low Leakage
Low Output Voltage
Output High Leakage
Forward Voltage
Reverse Leakage Current
VIL
IIH
IlL
VOH
IOL
VOL
IOH
VF
IR
VOUT= 12V,
lOUT LO = -3mA
VPIN1.2=30V,
I SOURCE = 0
VPIN 2 = -30V
VIN = +V,IOUT = 150mA
VOUT = OV, VIN = OV
VIN = OV,louT = -150mA
VIN = 15V
10 = l00mA
VR =30V
3-29
1
+25OC
0.8
1.0
V
2
+125°C
0.65
0.85
V
3
-55°C
0.9
1.1
V
1
+25°C
0
2.0
I1A
2
+125°C
0
100
I1A
3
-55°C
0
2.0
I1A
1
+25°C
0.8
1.4
V
2
+125°C
0.8
1.25
V
3
-55°C
0.8
1.6
V
1
+25 C
-1.0
1.0
IIA
2,3
+125°C, -55°C
-1.0
1.0
I1A
O
Specifications HV400MJ/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
This Table Intentionally Left Blank. See AC Parameter on Table 3.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: Supply Voltage =±15V, Unless Otherwise Specified
PARAMETERS
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
Input High Current fPeak
IIHP
ISOURCE = 6A, 11lS Pulse, VIN = 9V,
VOUT=OV
+25°C
500
900
rnA
Peak Output Current
IOP8
VIN = 9V, 11lS Pulse, VOUT = 0
+25OC
4
8
A
Peak Output Current
loPa
VIN = 9V, 11lS Pulse, VOUT = 0
+25°C
25
35
A
ORR
10= 100rnA
+25°C
6
7
nC
See Switching Diagram and Test Circuit
+25°C
37
62
ns
21
ns
13
ns
Diode (Pin 7) Stored Charge
Rise Time
TR
Fall Time
TF
See Switching Diagram and Test Circuit
+25°C
14
Delay TIme (Lo to Hi)
TOR
See Switching Diagram and Test Circuit
+25°C
6
Delay Time (HI to Lo)
TOF
See Switching Diagram and Test Circuit
+25 C
7
16
ns
Minimum Off Time
TOR
See Switching Diagram and Test Clrcult
+25°C
400
1140
ns
O
NOTE:
1. Switching times are guaranteed but not tested.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-SS3 TEST REQUIREMENTS
SUBGROUPS (SEE TABLES 1 AND 2)
Interim Electrical Parameters (Pre Burn-IN)
1,
Final Electrical Test Parameters
1 (Note 1),2
Group A Test Requirements
1,2
Groups C and D Endpoints
1,
NOTE:
1. PDA applies to Subgroup 1 only. No other subgroups are Included In PDA.
3-30
Specifications HV400MJI883
Test Descriptions
SYMBOL
DESCRIPTION
DC INPUT PARAMETERS
VIH
The differential voltage between the input (pin 2) to the output (pin 8) required to source 10mA
Vil
The differential voltage between the input (pin 2) to the output (pins 3, 6) required to sink 3mA
IIH
The current required to maintain the input (pin 2) high with lOUT =OA
IIHP
The input (pin 2) current for a given pulsed output current
III
The current require to maintain the input (pin 2) low
DC OUTPUT PARAMETERS
=V+
VOH
The output (pin 8) voltage with input (pin 2)
IOP8
The pulsed peak source current form output (pin B)
10l
The output (pin 8) leakage current with Ihe input (pin 2)
VOL
The output (pins 3, 6) voltage with the input (pin 2)
IOP6
The pulsed peak sink current into output (pins 3, 6)
10H
The output (pins 3, 6) leakage current with the input (pin 2)
VF
The forward voltage of diode 01 or 07
IR
The reverse leakage current of diode 01 or 07
QRR
=Ground
=Ground
=V+
The time integral of the reverse current at turn off
AC PARAMETERS (See Switching Time Specifications)
TA
The low to high transition of the output
TF
The high to low transition of the output
TOR
The output propagation delay from the input (pin 2) rising edge
TOF
The output propagation delay from the input (pin 2) falling edge
TOA
The minimum time required after an output high to low transition before the next input low to high transition
3·31
HV400MJ/883
Switching Diagram and Test Circuit
INPUT
10%
OV _....;1.;,O%;;..J'r
VOUT
TOR
90%
OUTPUT
C1
330~F
SOV
T
V
r------------.-------------1
1N914
T C21.0~F
V SOV
7 :
··
·
2 :
•
••
15V -------~
GND --- - /
'-INPUT
SOOSOURCE
(RISE AND FALL TIMES <10na)
..r-\.: 12.8V
:
:
:
:
:
O.9V
RL
100K
•
OUTPUT
••
•
·
4 !.. ____________________________ .!
HV400MJ/883 Switching Test Circuit
J1
R1
~
flE-------
C2
4.2 •
U1
Parts List
T
1
R1 1000. 1W Carbon Resistor
C L O.Q1~F. 50V Chip Capacitor
o
o
PULSE
IN
3.5 •
J1
HV400
o
IN
'~"g@!!i!
Ui
HV400
OUT
GNDG)
HV400 AC TEST BOARD
o
R2 Wire
D1 1N914 Diode
RL 100ko, 1/8W Carbon Resistor
J1. J2 PC Mount Banana Jack Johnson 108-0740-001
C1 330~F, 50V Capacitor
J3. J4 PC Mount SMA Connector Johnson EFJ142
C2 1~F. 50V Capacitor
U1 Harris HV400MJ/8831.C.
3-32
HV400MJI883
Burn-In Circuit (Dynamic)
V3
0-_-..,..----1---1
Fx o--H~....I
V2
R1
R2
C1
O.01I'F
V1
O--;--;-~~-----T----~
NOTES:
1.
2.
3.
4.
5.
6.
7.
B.
9.
10.
11.
Rl = lOOn, 5%, 1/4W.
R2 = 50, 5%, 2W.
R3 = 1000, 5%, 2W.
Cl = O.OlJ.lF, 10%, 3OV.
C2 = O.OOlJ.lF, 10%, 30V.
C3, C4, C5 = O.lJ.lF, 20%, 50V.
Vl = -15.5V, ± 0.5V.
V2 = -5.5V, ± 0.5V.
V3 = +5.5V, ± 0.5V.
Ql, Q2 = SK9505 or Equivalent. (One Pair Per Board Column)
Fx= 12.5kHz, 50% Duty Cycle.
V 1L = O.BV (Max)
V1H = +4V (Min)
3-33
I. .'
C3
HV400MJ/883
Metallization Topology
DIE DIMENSIONS:
1700 x 1820 x 483ltm
GLASSIVATION:
Type: Silox
Thickness: 12kA ± 2kA
Type: Nitride
Thickness: 3.5kA ± 2.5kA
METALLIZATION:
Type: 1% Cu, 9!i1% AI
Thickness: 16kA ± 2kA
TRANSISTOR COUNT: 3
SUBSTRATE POTENTIAL (POWERED UP):
Unbiased
PROCESS: HFSB Linear Dielectric Isolation
WORST CASE CURRENT DENSITY:
8.2 x 104 Alcm 2 during 1its pulse with ·35A output current,
through 8~ wide line 14kA thick.
Metallization Mask Layout
HV400MJ1883
wI-
wI-
()::)
a:
()::)
a:
II.
II.
::)1-
::)1-
e:
e:
g8
0::)
",0
V+(1)
INPUT (2)
(7) DIODES
(6) SINK OUTPUT
SINK OUTPUT (3)
GROUND (4)
(5) GROUND
3·34
HV400MJ
I-IARRIS
SEMICONDUCTOR
DESIGN INFORMATION
High Current MOSFET Driver
April 1994
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied.
Circuit Operation
The HV400MJ/883s operation is easily explained by referring to the schematic. The control signal is applied to Pin 2. If
the control signal is about 2V above Pin 8, the output NPN
01 turns on charging the MOSFET gate from a capacitor
connected to Pin 1. Resistor R4 helps keep the SCR off by
applying a reverse bias to the SCR anode gate.
When the control input drops about 1V below Pin 3/6, PNP
02 turns on which triggers the SCR by driving both the
anode and cathode gates. The SCR discharges the
MOSFET gate and when its current becomes less than
10mA, it turns off. Transistor 02 conducts any gate leakage
currents, through resistors R1 and R2, once the SCR turns
off. Figure 7 shows the output characteristics before the
SCR turns on and after it turns off. When the SCR turns on,
resistor R4 provides a path to remove 01 base charge.
Resistor R3 provides the base current for 02 to reduce the
turn off delay time. Resistors R1 and R2 reduce the SCR
recovery time.
The two diodes connected to the diode input Pin 7 provide
some operation flexibility. With Pins 2 and 7 connected
together, diode D1 provides a path to recharge the storage
capacitor once the MOSFET gate is pulled high and, along
with diodes D2 and D3, keeps 01 from going into hard
saturation which would increase delay times. Diode D7
would clamp the input near ground and provide a current
path if an input DC blocking capacitor is used.
Alternatively, Pin 7 can be connected to Pin 6 so that the
SCR and NPN 01 don't have to pass reverse current if the
output "rings" above the supply or below ground. When high
performance diodes are required, Pin 7 can be left
disconnected and external diodes substituted.
The diodes in series with Pin 2 decouple the input from the
output during negative going transitions. The absence of
input current turns off 01 and allows 02 to trigger the SCA.
Diode D8 turns off 02 once the SCR turns on pulling the output low, otherwise 02 would saturate and slow down circuit
operation. In addition, the diodes D2, D3 and D8 improve
noise immunity by adding about 2.5V of input hysteresis.
The HV400MJ/883 is capable of large output currents but
only for brief durations due to power diSSipation.
Circuit Board Layout
PC board layout is very important. Pins 3 and 6 should be
connected together as should Pins 4 and 5. Otherwise the
internal interconnect impedance is doubled and only half of
the bond wires are used which would degrade the reliability.
The bootstrap capacitor should hold at least lOx the charge
of the MOSFET and should be connected between Pins 1
and 4/5 with minimum pin lengths and spacings. Likewise,
the HV400MJ/883 should be as close to the MOSFET as
possible. Any long PC traces (parasitic inductances)
between the MOSFET gate and Pins 8 or 3/6 or between the
source and Pins 4/5 should be avoided. Inductance between
the HV400MJ/883 and the MOSFET limit the MOSFET
switching time. If they are too large, the HV400MJ/883 may
operate erratically as discussed below.
Cross Conduction Faults
It is possible to have both 01 and the SCR on at the same
time resulting in very large cross conduction currents. The
SCR has larger current capacity so the output goes low and
the storage capacitor is discharged. The conditions that
cause cross conduction and precautions are discussed
below.
Minimum Off Time
The SCR requires a recovery time before voltage can be
reapplied without it switching back on. Figure 13 shows how
this SCR recovery time, called "minimum off time" (TOR)' is a
function of the load capacitance. If the input voltage goes
high before this recovery time is complete, the SCR will
switch back on.
Note that reverse current flowing through the SCR, for
example due to load inductance ringing, extends the
minimum off time. Since the minimum off time is really
dependent upon how much stored charge remains in the
SCR when the anode (Pin 3/6) is taken positive, it may vary
for different applications. Figure 13 indirectly shows that the
minimum off time increases with larger currents. It also
increases at elevated temperatures as shown in Figure 14.
Excessive ringing increases the minimum off time since the
stored charge doesn't begin to dissipate until the current
drops below 10mA for the last time. Rising anode voltage
acts on the internal SCR capacitance to generate its own
triggering current. The excess stored charge increases this
capacitance. Faster rise times and/or higher voltages also
increase the amount of internal trigger current from the internal capacitance so applications with larger dV/dt require
longer minimum off times.
The minimum off time must be considered for all occurrences of SCR current. For example, in a half bridge switch
mode power supply, there are two MOSFETs connected to
the transformer primary. Assume that the high side MOSFET
switch is off. When the low side MOSFET switch is turned
3-35
HV400MJ
DESIGN INFORMATION
(Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied.
on, the HV400MJ/883 driving the high side MOSFET will
have to sink gate current from C GO and will have to source
gate current when the low side MOSFET switches back off.
Both of these current pulses will try to flow through Pin 3/6
since the Pin 8 output is turned off. Sourcing current from
Pins 3/6 through the SCR is possible, the Pin 3/6 voltage
becoming negative with respect to Pins 4/5 (See Figure 8).
But a better practice would be to connect a Schottky diode
between Pins 4/5 (anode) and 3/6 (cathode) so reverse current does not flow through the SCR.
False SCR Triggering
The SCR may be triggered inadvertently. The output may
overshoot the input due to inductive loading or over driving
the output NPN (allowing it to saturate). Whenever Pin 6 is
more positive than Pin 2 by 1V, the SCR is triggered on.
Also, if the output rises too rapidly, greater than 0.5V/ns, the
SCR may self trigger. Both issues are resolved by minimizing the load inductance and inserting sufficient resistance,
usually 0.10 to 100, between Pin 8 and the load.
A very fast negative going input voltage can result in minimum
off times of about 2.5I1S. If the output can not keep up with the
falling input, the stored charge of diode D4 is transferred into
the base of 02. This excess charge in 02 must have time to
dissipate. Otherwise, when Pin 3/6 goes positive, Q2 will turn
on and trigger the SCR. An external diode in series with Pin 2,
as shown in Figure 1, will prevent D4 from discharging into the
base of 02 but that will also reduce the output voltage by the
forward voltage of that diode.
then some of the power is dissipated in the resistors, the percentage depending upon the ratio of resistors to HV400MJI
883 output impedance.
There are two other sources of power dissipation to
consider. First there is the power in R3 which is the product
of the input Pin 2 current and voltage (with no output current)
times the duty cycle. Second is the product of the Pin 7
diode stored charge, which is dependent upon the forward
current, times the applied diode reverse voltage times the
frequency. This information is available from Figure 3 and
Figure 16 in this data sheet.
Applications Circuits
The HV400MJ/883 was designed to interface a pulse transformer to a power MOSFET. There must be some means to
balance the transformer volt-second product over a cycle.
The unipolar drive shown in Figure 1 lets the core magnetization inductance reverse the primary and secondary voltages. The zener diode on the primary side limits this voltage
and must be capable of dissipating the energy stored in the
transformer. The load may be connected to either the power
MOSFET drain or source.
vs
7,·..···....·······..··..·..··..··..···....·11
cs
Internal Diodes
The internal diodes connected to Pin 7 are provided for
convenience but may not be suitable for large currents. Since
they are part of the integrated circuit, they are physically
small, operate at high current densities, and have long recovery times. Figure 15 shows that their forward characteristics
degrade above 100mA. In addition, Figure 16 shows their
reverse recovery charge as a function of forward current. The
product of this charge, the applied reverse voltage and the frequency is the additional power dissipation due to the diodes.
For stored charge calculations, use the peak forward current
within 100ns of the application of reverse bias. In addition to
the extra power dissipation, the capacitance of these diodes
may extend the switching delay times.
Power Dissipation Calculations
The power required to drive the MOSFET is the product of
its total gate charge times the gate supply voltage (maximum
voltage on HV400MJ/883 Pin 1, 2 or 7) times the frequency.
Assuming that the MOSFET gate resistance is negligible,
this power is dissipated within the HV400MJ/883. If resistors
are placed between the HV400MJ/883 and the MOSFET,
4 •...... •.. •.... •.. •............ •• .. •.. •....··5 POWER
HV400MJ/883
MOSFET
FIGURE 1. UNIPOLAR DRIVE
A diode is added in series with Pins 2 and 7 to allow the
transformer secondary to go negative. The charge storage of
the Pin 7 diode may cause the turn off delay time to be too
long. Alternatively, Pin 7 could be left disconnected and a
second external diode connected between the transformer
(anode) and Pin 1 (cathode). In some applications the diode
in series with Pin 2 may be unnecessary but the -35V input
to output or ground maximum rating should be observed.
Sometimes the volt-second balance is achieved by a push-pull
drive on the pulse transformer primary. This is especially useful
if there are two secondary windings driving two HV400MJ/883s
out of phase such as in a ha~-bridge configuration.
3-36
HV400MJ
DESIGN INFORMATION
(Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application
and design informiation only. No guarantee is implied.
Other times it is more convenient to achieve volt-second
balance by using capacitors to block DC in the primary and
secondary windings as shown in Figure 2. The Pin 7 diodes
provide a path for discharging the secondary side DC blocking capacitor. Both capacitors, CIN and Cs, should be at
least 10 times the equivalent MOSFET gate capacitance.
7
1
II
The HV400MJ/BB3 can be used as a current booster for low
side switches by connecting directly to the PWM output. The
circuit would be similar to the switching time test circuit.
It is worth restating that some consideration (and experimentation) should be given to the choice of external components,
i.e. resistors, capacitors and diodes, to optimize
performance In a given application.
r·················;,:····························..·t
T1
4 : •••••••••••••••••••••••••••••••••••••••••••••••••••; 5
HV400MJ/883
FIGURE 2. BIPOLAR DRIVE WITH DC BLOCKING CAPACITOR
3-37
ICL7667
Dual Power MOSFET Driver
April 1994
Features
Description
• Fast Rise and Fall nrnes
- 30ns with 1000pF Load
The ICL7667 is a dual monolithic high·speed driver
designed to convert TIL level signals into high current
outputs at voltages up to 15V. Its high speed and current
output enable it to drive large capacitive loads with high slew
rates and low propagation delays. With an output voltage
swing only millivolts less than the supply voltage and a
maximum supply voltage of 15V, the ICL7667 is well suited
for driving power MOSFETs in high frequency switchedmode power converters. The ICL7667s high current outputs
minimize power losses in the power MOSFETs by rapidly
charging and discharging the gate capacitance. The
ICL7667s input are TIL compatible and can be directly
driven by common pulse-width modulation controllCs.
• Wide Supply Voltage Range
- Vee = 4.SV to 15V
• Low Power Consumption
- 4mW with Inputs Low
- 20mW with Inputs High
• TIUCMOS Input Compatible Power Driver
- ROUT = 70 lYP
• Direct Interface with Common PWM ControllCs
• Pin Equivalent to DS00261OS0056; TSC426
Typical Applications
Order Information
• SwHchlng Power Supplies
• DCIDC Converters
• Motor Controllers
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
ICL7667CBA
O"C to +70"C
8 Lead SOIC (N)
ICL7667CPA
O"C to +70"C
8 Lead Plastic DIP
ICL7667CJA
O"C to +70"C
8 Lead Ceramic DIP
ICL7667CTV
O"C to +70"C
8 Pin Metal Can
ICL7667MTV (Note 1)
-55°C to +125°C
8 Pin Metal Can
ICL7667MJA (Note 1)
-55°C to +125°C
8 Lead CerDIP
NOTE: 1. Add 1883B to Part Number for 883B Processing
Pinouts
Functional Diagram
ICL7667 (CAN)
TOP VIEW
v~~
__
~~
______
~~
______
~
v+
OUT
ICL7667 (PDIP, SOIC, CERDIP)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994
3-38
File Number
2853.2
Specifications ICL7667
Absolute Maximum Ratings
Thermal Information
Supply Voltage v+ to v- ......•.......••.•.•.•......••. 15V
Input Voltage......•••....•••••..•.••••• v- -O.3V to v+ +O.3V
Package Dissipation. TA +25°C •....•.•••••...••••••• SOOmW
Thermal Resistance
8JA
8JC
PDIP Package. . . . . . . . . . . . . . . . . .. 15fiJCNI
sale Package................... 17fiJCIW
-
Metal Can Package. • • • • . • • . • • • • •. 156"CIW
68°CIW
CerDIP Package. . . . . . • . • . • • • . . •. 1150CJW
3O"CJW
Storage Temperature Range •..••••••.•••.•••• -65°C to + 15O"C
Lead Temperature (Soldering I Os) •.••.••.•....••••••• +300oC
(SOIC - Lead TIps Only)
CAUTION: Stresses above those listed in "'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational SlJCtions of this specification is not implied.
Operating Temperature Range
ICL7667C .....................•......•••.. O"C to +70°C
ICL7667M .•.....•••.....••••....••••.•• -55OC to +125°C
Electrical Specifications
PARAMETERS
SYMBOL
TEST CONDITIONS
ICL7667C. M
ICL7667M
T"= +25°C
-55°C:s; T,,:s; +125°C
MIN
TVP
MAX
MIN
-
2.0
TYP
MAX
UNrrS
-
-
V
0.5
V
0.5
V
0.1
IJA
Vee
-
V
-
0.1
V
12
13
n
n
DC SPECIFICATIONS
Logic I Input Voltage
V IH
Vee = 4.5V
2.0
Logic I Input Voltage
VIH
Vee = 15V
2.0
-
Logic 0 Input Voltage
V IL
Vcc= 4.5V
Logic 0 Input Voltage
VIL
Vee = 15V
Input Current
IlL
Vee = 15V. VIN = OV and 15V
-0.1
VOH
Vec=4.5Vand 15V
Vee
-0.05
VOL
Vee = 4.5V and 15V
Output Voltage High
Output Voltage Low
-
Output Resistance
RoUT
VIN = VIL.loUT = -IOmA. Vec = 15V
Output Resistance
RoUT
VIN = VIH • lOUT = 10mA. Vcc = 15V
Power Supply Current
Icc
Vee = 15V. VIN = 3V both inputs
Power Supply Current
Icc
Vcc = 15V. VIN = OV both inputs
-
-
0.8
2.0
-
0.8
-
0.1
-0.1
Vcc
-
0
0.05
7
10
8
12
5
7
150
400
35
50
20
30
20
30
20
30
Vee
-0.1
-
-
-
-
V
8
mA
400
IJA
60
ns
SWITCHING SPECIFICATIONS
Delay Time
T02
Figure 3
Rise Time
TR
Figure 3
FaUTIme
TF
Figure 3
Delay TIme
TOI
Figure 3
-
NOTE: All typical values have been characterized but are not tested.
Test Circuits
+5V
INPUT
-O.4V
15V
INPUT RISE AND
FALL TIMES ';IOna
OUTPUT
OV
3-39
-
-
40
ns
40
ns
40
ns
1&1(1)
01&1
-:e
~g
~~
:e(l)
ICL7667
Typical Performance Curves
100
iI'S
VCC=lSV
...S
.z
100
I-
0
~RISEI
~
.r:
10
./
I
I
I
I
/
I
I
...
.s
~
e
z
"~
80
Vcc=15YI
70
60
TD2
50
.-...r--
40
30
20
{FAI
10
I
CL=lnF -
90
~
100
1000
10K
o
lOOK
o
·55
+25
70
TEMPERATURE (oC)
FIGURE 1. RISE AND FALL TIMES vs CL
FIGURE 2. T Dl. T D2 vs TEMPERATURE
50
30
II
Vcc· 1SV
40
TR AND TF...............
.
e
30
.r:
20
l-
~
~
-
10
CL - (pF)
...S
TDI
~
-
~
v-----
200:~ V
10
r--
CL=lnF
Vec= 15V
I--"'"
~
+125
1I
~I'
20kHz
3.0
10
o
-55
0
+25
70
TEMPERATURE rC)
10
+125
:c
!.
I-_ _ _+
___
lK
10K
lOOK
CL(PF)
FIGURE3. T R• TFvsTEMPERATURE
100
100
FIGURE 4. Icc VS C L
100
-+_~--I
10 I-----+-..."....c..-f.~:..--_I
10
lOOI'A '--_ _ _-'-_ _ _-1.._ _ _---'
100mA
Jl
10k
lOOk
1M
10M
10k
FREQUENCY (Hz)
lOOk
1M
FREQUENCY (Hz)
FIGURE 5. Icc VS FREQUENCY
FIGURE 6. NO LOAD Icc vs FREQUENCY
3-40
10M
I
ICL7667
I
Typical Performance Curves (Continued)
50
50
....s
~
l-
40
30
ez
C
20
:P
10
"'- "-
...
.s
!o-
-
TF
~
e
30
C
20
z
-
TOI
Vee -(V)
..........
TR= T02
-
10
CL= 10pF
CL=1nF
10
~
~
0
0
5
40
5
15
FIGURE 7. DELAY AND FALL TIMES vs Vee
10 Vee (V)
15
FIGURE 8. RISE TIME vs Vee
Detailed Description
The ICL7667 is a dual high-power CMOS inverter whose inputs
respond to TTL levels while the outputs can swing as high as
15V. Its high output current enables ~ to rapidly charge and discharge the gate capacitance of power MOSFETs, minimizing
the switching losses in switchmode power supplies. Since the
output stage is CMOS, the output will swing to w~hin millivofis
of both ground and Vee without any external parts or extra
power supplies as required by the OSOO26156 family. Atthough
most specifications are at Vee = 15V, the propagation delays
and specifications are almost independent of Vee.
In addition to power MOS drivers, the ICL7667 is well suited
for other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where
the load capacitance is large and low propagation delays are
required. Other potential applications include peripheral
power drivers and charge-pump voltage inverters.
Input Stage
The input stage is a large N-channel FET with a P-channel constant-current source. This circuit has a threshold of about 1.5V,
relatively independent of the VCC vottage. This means that the
inputs will be directly compatible with TTL over the entire 4.5V 15V Vee range. Being CMOS, the inputs draw less than 11lA of
current over the entire input voltage range of ground to Vee.
The quiescent current or no load supply current of the ICL7667
is affected by the input voltage, going to nearly zero when the
inputs are at the 0 logic level and rising to 7mA maximum when
both inputs are at the 1 logic level. A small amount of hysteresis, about 50mV to 100mV at the input, is generated by positive
feedback around the second stage.
Output Stage
The ICL7667 output is a high-power CMOS inverter, swinging
between ground and VCC. At Vee = 15V, the output impedance of the inverter is typically 70.. The high peak current
capability of the ICL7667 enables it to drive a 1000pF load
with a rise time of only 40ns. Because the output stage impedance is very low, up to 300mA will flow through the series Nchannel and P-channel output devices (from Vee to ground)
during output transitions. This crossover current is responsible
for a significant portion of the internal power dissipation of the
ICL7667 at high frequencies. It can be minimized by keeping
the rise and fall times of the input to the ICL7667 below 11lS.
Application Notes
Atthough the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be paid.
Grounding
Since the input and the high current output current paths
both include the ground pin, it is very important to minimize
and common impedance in the ground return. Since the
ICL7667 is an inverter, any common impedance will
generate negative feedback, and will degrade the delay, rise
and fall times. Use a ground plane if possible, or use
separate ground returns for the input and output circuits. To
minimize any common inductance in the ground return,
separate the input and output circuit ground returns as close
10 the ICL7667 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.71lF
tantalum capacitor in parallel with a low inductance 0.11lF
capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
1. Reduce inductance by making printed circuit board traces
as short as possible.
2. Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3. Use a 100. to 300. resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly
increase the rise and fall times.
3-41
4. Use good bypassing techniques to prevent supply voltage
ringing.
ICL7667
Power Dissipation
The power dissipation of the ICL7667 has three main
components:
1. Input inverter current loss
significant amounts of power. The very high current output of
the ICL7667 is able to rapidly overcome this high capacitance and quickly turns the MOSFET fully on or off.
18
2. Output stage crossover current loss
16
3. Output stage 12R power loss
w
The sum of the above must stay within the specified limits for
reliable operation.
"~
14
As noted above, the input inverter current is input voltage
dependent, with an Icc of 0.1 mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.
w
(,)
ex:
10
I/)
6
The output stage crowbar current is the current that flows
through the series N-channel and P-channel devices that
form the output. This current, about 300m A, occurs only during output transitions. Caution: The inputs should never be
allowed to remain between V1L and V1H since this could leave
the output stage in a high current mode, rapidly leading to
destruction of the device. If only one of the drivers is being
used, be sure to tie the unused input to a ground. NEVER
leave an input floating. The average supply current drawn by
the output stage is frequency dependent, as can be seen in
Icc vs Frequency graph in the Typical Characteristics
Graphs.
The output stage 12R power dissipation is nothing more than
the product of the output current times the voltage drop
across the output device. In addition to the current drawn by
any resistive load, there will be an output current due to the
charging and discharging of the load capacitance. In most
high frequency circuits the current used to charge and
discharge capaCitance dominates. and the power dissipation
is approximately
where C
PAC =CVcc2f
=Load Capacitance, f =Frequency
In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
ICL7667 power dissipation will be
PAC = OGVCCf
=
where OG Charge required to switch the gate, in Coulombs,
f Frequency.
=
Power MOS Driver Circuits
Power MOS Driver Requirements
Because it has a very high peak current output, the ICL7667
the at driving the gate of power MOS devices. The high
current output is important since it minimizes the time the
power MOS device is in the linear region. Figure 9 is a
typical curve of charge vs gate voltage for a power MOSFET.
The flat region is caused by the Miller capacitance, where
the drain-ta-gate capaCitance is multiplied by the voltage
gain of the FET. This increase in capacitance occurs while
fhe power MOSFET is in the linear region and is dissipating
g
:::>
0
g
I I
Voo= sov
12
8
w
4
"
2
!C
r- 1O=1A
f-,-I I
0
-2
I/
V, V
L J
2
4
i/
j
.\
I I
VOO= 200V
oJ 630pF
I I
~ ~12pr
o
I
II J
VI VVoo= 37SV
LV
r- ,.- 680pF
/.
'I
6
8
10
12
14
16
18
20
GATE CHARGE - Qo (NANO-COULOMBS)
FIGURE 9. MOSFET GATE DYNAMIC CHARACTERISTICS
Direct Drive of MOSFETs
Figure 11 shows interfaces between the ICL7667 and typical
switching regulator ICs. Note that unlike the 080026. the
ICL7667 does not need a dropping resistor and speedup
capaCitor between it and the regulator IC. The ICL7667, with
its high slew rate and high voltage drive can directly drive the
gate of the M08FET. The SG1527 IC is the same as the
SG1525 IC. except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer.
Transformer Coupled Drive of MOSFETs
Transformers are often used for isolation between the logic
and control section and the power section of a switching
regulator. The high output drive capability of the ICL7667
enables it to directly drive such transformers. Figure 11
shows a typical transformer coupled drive circuit. PWM ICs
with either active high or active low output can be used in
this circuit, since any inversion required can be obtained by
reversing the windings on the secondaries.
Buffered Drivers for Multiple MOSFETs
In very high power applications which use a group of MOSFETs in parallel, the input capaCitance may be very large
and it can be difficult to charge and discharge quickly. Figure
13 shows a circuit which works very well with very large
capacitance loads. When the input of the driver is zero, 01 is
held in conduction by the lower half of the ICL7667 and 02 is
clamped off by 01. When the input goes positive, 01 is
turned off and a current pulse is applied to the gate of 02 by
the upper half of the ICL7667 through the transformer, T1.
After about 20ns, T1 saturates and 02 is held on by its own
CGS and the bootstrap circuit of C1, D1 and R1. This bootstrap circuit may not be needed at frequencies greater than
10kHz since the input capacitance of 02 discharges slowly.
3-42
ICL7667
l5V
.n~
+V
+VC
A
ICL7667
SG1527
1 - IRF730
B
GND
-V
-
FIGURE 10A_
l5V
lK
+Vc
"~q-
+V
Cl
E1
-
Tl494
1-IRF730
C2
GND
W(/)
OW
-::t:
(/)0
::t:~
VOUT
~
E2
-
-
-V
lK
-
+15V
FIGURE 108.
FIGURE 10. DIRECT DRIVE OF MOSFET GATES
lav
CA
CB
+V
VIN
EA
-
CA1524
'1. ·
~
470
IRF730
: ::65V
ICL7667
EB
-165V
470
-
-V
VOUT
FIGURE 11. TRANSFORMER COUPLED DRIVE CIRCUIT
3-43
- - - 2 4 AO
~25
BO
r-__N_M_O_S....,[:>o- 26 LO
r-______
~-r-21
pos
111 CPA
17 CPB
7
L 8
28 P+
23 GO
R 9
10
rr=;=~~~~= 20 REG
22 PO
15 REF
G 11
12
......___----.j__ 16 PCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
4-3
File Number
3691
Specifications HIP2030
Thermal Information
Absolute Maximum Ratings
Gate Channel Supply Voltage, VP+ to VPLogic Supply Voltage, VPO to VPAll Other Pin vottages
(A+, A-, Bl+, Bl-, 82+, 82-, L+, L-, R+, R-)
0
0
..
0
..
0
0
0
0
0
0
0
0
0
0
0
..
000
0
0
0
0
0
0
0
•••
0
-no5V to 32V
7V to 18V
..
(VP-)-Oo5 to {Vp+)+O.5
Thermal Resistance.
PLCC Package •••
Lead Temperature (Soldering 1Os)
Storage Temperature Range
Junction Temperature
0
..
0
..
0
0
0
0
000000000000000000
0
0
0
0
0
0
0
0
0
0
....
0
0
0
0
0
0
0
0
0
0
0
0
9JA
6O"CIW
+265°C
-4OOC to +15O"C
+125°C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
....
0
0
0
0
0
0
0
0
0
0
0
0
0
0
..
0
CAUTION: Stressss aboWI those listed in "Absolulll Maximum Ratings" may cause permanent damage to th8 daviee. This Is a stnJss only fflting and op6ff1tion
of the device at th8se or any other conditions abo... those Indicated in th8 op6ffItionai sections of this specification is not impHed.
Recommended Operating Conditions (TJ = -40"C to +125°C Unless Otherwise Noted, All Vollages Referenced to VP-)
Gate Channel Supply Voltage, VP+ to VP-0.5V to 30V
Logic Supply Voltage, VPO to VP- ..... .. .. .. .. .. .. .... 10 to 15V
All Other Pin Vottages
(A+, A-, Bl+, Bl-, 82+, 82-, L+, L-, R+, R-) .•• (VP-)+2V to (VPO)+2V
0
0
0
0
0
0
0
0
0
•
0
•
Max Output Source Current, Channels A, B • . • • • • • • . •. 10mA
Max Output Sink Current, Channels A, L•.•••
10mA
Min Load Current, Ref to P-..................
2mA
0
••••••••
0
••••••
I
Static Electrical Specifications VPO to VP- = 15V, VP+ to VP- = 30V, VP- = OV and TJ = +25°C, Unless Otherwise Specified
TJ
SYMBOL
PARAMETER
TEST CONDITIONS
=+25°C
MIN
TYP
MAX
UNITS
-
2.75
-
rnA
-
3.5
3.0
-
mA
-
525
-
IIA
30
35
V
5
-
10PO
QUiescent VPO Supply
lapp
Quiescent Vpp Supply
VPP to VP- = 30V
1000s
Quiescent VPOS Supply
Osc Freq = 100kHz
IsWPO
VPO Switching Current
A, B, and G Input
Freq = 10kHz
Iswpp
VPP Switching Current
A, B, and G Input
Freq = 10kHz
BVpp
VPP-VPM Breakdown Voltage
VREG
Regulator VOltage, PO to Ref
IREF=2mA
-
RREG
Regulator Impedance, PO to Ref
IREF =10mA, 30mA
-
5
-
n
VClMP
Clamp Vollage, REG to P-
ICLMP = 15mA
Clamp Impedance, REG to P-
ICLMP = 15mA, 30mA
FQPMP
Charge Pump Frequency
100
-
V
RCLMP
-
12
kHz
OOPMP
Charge Pump Duty Cycle
50
-
%
28.5
-
V
27.5
-
V
-
1.5
15
IIA
mA
V
n
V~P
Charge Pump Your. VP+ to VP-
IP+=500pA
VOQPMP
Charge Pump Vour. VP+ to VP-
IP+=5mA
IIN cMP
Comparator input Leakage
VINcMP = VPOI2
-
10
-
nA
VOSCMP
Comparator offset Voltage
Vcm=VPOI2
-
15
VCMcMP
Comparator Common Mode Voltage
Range
(VP-)+2
RDSSRC
AO, SO Output RDS, Sourcing
ISRC= 10mA
RDS SRC
GO Output RDS, Sourcing
ISRc=6A
RDSSNK
AO, LO Output RDS, Sinking
ISNK= 10mA
RDSSNK
GO Output RDs, Sinking
IsRc=6A
4-4
-
mV
VPO+2
V
-
75
-
n
2
-
75
-
n
1
-
n
n
Specifications HIP2030
Dynamic Electrical Specifications
VPO to VP- =15V, VP+ to VP- =30V, VP- =OV, VIN- =7.5V, VIN+ =(VIN-) ± 2V and
TJ = +25°C, Unless Otherwise Specified
TJ
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
=+25°C
TYP
MAX
UNITS
-
ns
-
ns
-
ns
TGOH M1N
Min GO Output High Duration
MHTOpen
-
750
TGOLM1N
Min GO Output Low Duration
MLTOpen
1200
TP LH
Prop Delay, Low To High, Channels A, B
CLOAD =300pF
TP LH
Prop Delay, Low To High, Channel L
CLOAD =300pF
TP HL
Prop Delay, Low To High, Channel A
CLOAD
TRAB
Rise TIme, Channels A, B
CLOAD =300pF
TFAL
Fall TIme Channels A, L
CLOAD =300pF
TPLH
Prop Delay, Low To High, Channel G
CLOAD =60nF
-
TP HL
Prop Delay, High To Low, Channel G
CLOAD =60nF
-
300
TRG
Rise Time, Channel G
CLOAD =60nF
Fall TIme Channel G
CLOAD =60nF
-
250
TFAL
=300pF
100
120
150
50
50
150
200
ns
ns
ns
ns
ns
ns
ns
-
ns
HIP2030 Application Information
The Harris Photo-Coupled Isolated Gate Drive (HPCIGD)
circuit, illustrated in Figure 1, contains four subcircuits: a Single
Supply DC bias, a Regulated voltage divider reference, a Local
Energy Source Capacitance, and a Photo-Couple Receiver.
The Single Supply DC Bias Circuit, shown in Figure 1,
consists of a single external dropping resistor (R1) connected between pins P+ (U1-28) and PO (U1-22). When an
input voltage of30V is applied across pins P+ and P- (U116), R1 forms a resistive divider network with the input
impedance located between pins PO and P- (RVPO). This
allows the circuit designer to adjust the value of R1 to obtain
a desired bias voltage between pins PO and P- (VPO.). The
value of RVPO can be calculated by evaluating the equivalent Quiescent Input Impedance (RQ) and the SV reference
impedance (RR) as parallel resistances. The values for R1,
RQ, RR, and RVPO can be determined by using equations
1(A, B, C, D) as shown in appendix A, exercise 1.1.
The Regulated Voltage Divider Reference is comprised of
two resistors (R3 and R4) connected in series and are
located across pins PO and REF. This voltage divider provides a stable voltage reference to all of the HIP2030 comparator inputs. Resistors R3 and R4 are selected equal in
value to create a midpoint bias reference between the peak
to peak input signal of U2. Also, the midpoint bias method
ensures that input signals generated from U2 and midpoint
bias reference voltages are within a safe common mode voltage range of the comparators.
The Local Energy Source Capacitances, C2 and C3, are
needed to supply the charge required to drive large capacitance loads at high dV/dts. The HPCIGD circuit uses low
cost 'oversized" tantalum capacitors (C
10I1F) that are
used for C2 and C3. If rise times and overshoot are critical,
=
ceramic capacitors with low ESL and ESR should be used to
improve gate drive signals. In a power circuit, where the gate
driver is exposed to high dV/dts, the network of C2 and C3
directs noise current away from the HIP2030. This allows the
HFOIGD circuit to operate well in half bridge power circuits
that use a transfonner coupled power source.
The Photo-Coupled Receiver subcircuit consists of U2, RS,
C4, and R6. U2 is a photocoupler which combines an infrared emitter diode (IRED)and a high speed photo detector to
translate light pulses to low voltage input signals. These signals are routed to the G channel and are used to control the
output GO. Component RS is used to limit the DC current
through the IRED when the input signal voltage switches to
its most positive level. A wide range of input voltages may be
accommodated by varying RS to limit the IRED current to
2SmA. C4 is a speed up capacitor and is selected to match
the forward bias capacitance of the IR diode. The last component, R6, is an optional part and is intended to be a tennination resistor with the value set by the user.
The Harris HIP2030 Driver Board (HIP2030DB) is a printed
circuit board (PCB) developed to help evaluate the performance of the HIP2030 MCTIIGBT Driver IC in power switching circuits. The component layout of the HIP2030DB circuit
enables the user to conveniently populate the PCB for either
Photo-Coupled or fiber-optic receivers. In addition, the PCB
layout has provisions for ·on board prototyping" and special
function components. This facilitates the gate drive circuit
design and allows the user to exercise the intemal architecture and special functions of the HIP2030. The schematic of
the HIP2030DB, illustrated in Figure 2, uses the basic
HPCIGD circuitry and has provisions for ·on board prototyping" and special function components.
4-S
HIP2030
TABLE 1. LOGIC
INPUTS
1
OUTPUTS
G
L
R
LO
GO
0
0
0
LS
H
0
0
1
H
H
0
1
0
L
H
0
1
1
L
H
1
0
0
LS
U
1
0
1
H
L
1
1
0
L
H
1
1
1
L
H
=Input True
U = Undefined
LS Last State
o= Input False
=
+30V
B1· A+
JB1
/
B2·
4
3
2
A·
1
p+/NcIOL
28
27
26
•
5
B2+
>-- 6
L·
7
L+
8
R·
9
PO
22 ; - POS
21
REG
20
CPA
19
rrr-
2:.. 10
~11
13
1J I~
14
I~
15 16
II.
w
II!
17 18
cL
C2
R1
MOSGATE
23
U1
HARRIS
HIP2030
28 LEAD PLCC
12
';
OB
-OA
24 GO
25
U2 TLP2601
C1
2
R3
I~ I ~
3
-
R4
8
-.!..
4
~~ .~
7
R2
;;
C3
6
5
30V
COM
R5
PHOTO
COUPLER
SUBCIRCUIT
I
C4
"
I
+
R6
FIGURE 1. HARRIS PHOTO-COUPLED ISOLATED GATE DRIVE
4·6
5V
IN PUT
SI GNAL
HIP2030
Jl
P+~t-________~Ryl~__-,
G
MOSGATE
R12
"
10
R8
RO
820
PS
"" B2+
5
P7
.!.P6 L~k!>-~.HI-----I 7
PO
~
8
+-..J
HIP2030
~P8R'i' R+ 10
~OS
21··
REG JP
20 CPA
,":,Pl0o~P11
11
191----,
12 13 14 15 16 17 18
.fi!
•
P12
30VDC
~
SVINPUT
+ SIGNAL
R13
,...
I
22 "P;;:O=--:=--.+----t--+--4>--h
+<.(i).~.*"+------i 0
~
10
PO
'\
GO
231-;;;.-______
Ul
P+
PO
P-
25 ~ BO
24~AO
•
6
L~
Rll
/4321282726
~ki).!;.~I---;:B::-2-~
GR
Rl0
Cl 10.0
A
l!I \!l.
R14
JP2
.@@..
R5
100
J3
R7
lK
::Ii
!:i
R3
C7
lK
C3
0.10
w
R2
R4
lK
g
a:til
u..
..J
<
:t:
'7
P-
FIGURE 2. HARRIS HIP2030 DRIVER BOARD
NOTES:
1. Capacitors C5 and C6 are special function components which control MLT and MHT.
2. Asymmetrical gate drive may be obtained by opening J2 and adjusting R1 and R2 for the desired voltage ratio.
3. Insert C7 for charge pump operation.
4. Open J3 to disable the charge pump oscillator.
5. Open Jl to disable the intemal12V regulator.
6. R5 is added for noise rejection at CdVldts.
7. The internal5V reference (REF) must be operational for MHT and MLT functions to work properly.
8. Pl • P12 are access pads for all comparitor inputs.
4·7
HIP2030
Printed Circuit Board
~
'-: : ;/
....
••
r-"--:1"'~'•• ~•
••
••••••
••••••
••••••
••••••
••••••
•••••
••••
••••
••••
•••••
•••
(0)
•••
©
FIGURE 3A. ASSEMBLY LAYER
FIGURE 3B. BOTTOM LAYER
© •• •
••
-0.
••••
••
••••••
••••••
••••••
•••••••
•••••
•••••
:~-r-.-4
•••
I ••••••
•
•
•
•
• • I---":=F-I-==:I
::::
©
,-/
--
i•
~~Hr!]
~~ lLiIlil.I~1
©
.--'--'----'
FIGURE 3C. TOP LAYER
4·8
HIP2030
Appendix A Exercises
Exercise 1.1
Q: How do I calculate the value of the series dropping resistor Rl. shown in Figure 1?
The maximum value of Rl can easily be determined in four
design steps:
A: The values for Rl. Ro. RR and Rvpo can be determined
by using equations 1 (A. B. C. D).
1. Assume the following values:
VPO
R
a
R
=--
IOPO
VPO
- ,----.,---:-7"-
R - IOPTO + IVDR + IRP
1
RVPO
V1N
loPO
EQ1(A)
= -1--1-
IOPTO
IVDR
IRP(ON)
EQ1(B)
EQ1(C)
Where:
VPO
lopo
IOPTO
IVDR
5mA
2.5mA
5mA. R2 = lK. VR2 = 5V
2. Select a usable value of V PO between 7V and 15V DC.
-+RQ
30V DC
2.75mAat Vpo = 15V
Use Vpo=15V
RR
Voltage between pins PO and p. (Ul • U22
and U1 • U16)
Quiescent current flowing into pin PO.
Quiescent current of the HBR·2521 fiberoptic receiver.
Current flowing through R3 and R4 (voltage divider reference).
Current flowing through pull up resistor R2
(in ·ON" or ·OFP· state)
3. Solve for Rvpo using EQ1(A. B. C):
15V
RQ
= 2.75mA = S.4SK
RR
lSV
= (SmA + 2.SmA
= 1.20K
+ SmA)
RVPO
w
= ----:1;----.1- = 984
g
a:III
--+-5.45K
1.20K
u..
4. Solve for Rl using EQl (D):
..J
EQ1(D)
4·9
<
::t:
HIP2500
Half Bridge 500V oc Driver
April 1994
Features
Description
• Maximum Rating •••.••..••..••.•••••••.• 500V
The HIP2500 is a high voltage integrated circuit (HVIC) optimized to drive N-Channel MOS gated power devices in half
bridge topologies. It provides the necessary control for PWM
motor drive, power supply, and UPS applications. The SO pin
allows external shutdown of gate drive to both upper and lower
gate outputs. Undervoltage lockout will not allow gating when
the bias voltage is too low to drive the external switches into
saturation.
• Ability to Interface and Drive N-Channel Power
Devices
• Floating Bootstrap Power Supply for Upper Rail
Drive
• CMOS Schmitt-Triggered Inputs with Hysteresis
and Pull-Down
• Up to 400kHz Operation
• Single Low Current Bias Supply
• Latch-Up Immune CMOS Logic
• Peak Drive•••••••••••••••••••.••.••. Up to 2.0A
• Gate Drive Rise Time (+1250 C) .•••••• < 25ns (Typ)
Applications
The HIP2500lP is pin and function compatible to the International Rectifier IR2110. The HIP2500 has superior ability to
accept negative voltages from the Vs pin to the COM pin due to
forward recovery of the lower flyback diode.
The HIP2500lB is a SOIC or small outline IC form of the
HIP2500. The HIP2500lB drives high side and low side referenced power switches just like the HIP25001P.
The HIP2500IP1 is a 16 pin Plastic DIP form of the HIP2500.
Pins 4 and 5 removed from lead frame to provide extra creepage and strike distances in high voltage applications.
• High Frequency Switch-Mode Power Supply
• Induction Heating and Welding
• Switch Mode Amplifiers
• AC and DC Motor Drives
Functional Block Diagram
• Electronic Lamp Ballasts
• Battery Chargers
• UPS Inverters
• Noise Cancellation In Amplifier Systems
Voo
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
<;>--..,._.....
HO
HIN
Vs
LO
PACKAGE
HIP2500lP
·40"C to +85°C
14 Lead Plastic DIP
HIP2500lPl
-4O"C to +85°C
16 Lead Plastic DIP
UN
HIP2500lB
-40oC to +85°C
16 Lead Plastic sOle rN)
Vss
.
,------ .. _------- ..... _......
.
COM
----------- .... _-------------,
Pinouts
HIP2500 (PDIP)
HIP2500 (SOIC)
HIP2500 (PDIP)
TOP VIEW
TOP VIEW
TOP VIEW
NC
NC
Vss
Vss
UN
UN
so
SO
HIN
HIN
veo
NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1gg4
4·10
File Number
2801.6
Specifications HIP2500
Absolute Maximum Ratings Full Temperature Range Unless
Otherwise Noted. All Voltages Referenced to Vss Unless Otherwise Noted.
Thermal Information
Floating Supply Voltage. Va .••...••...••.. Vs-0.5V to Vs+1B.OV
(Positive Terminal)
Floating Supply Voltage, Vs ........................... 500V
(Common Terminal)
High Side Channel Output Voltage, VHO ......•• -0.5V to Va+0.5V
Fixed Supply Voltage, Vee ..................... -o.5V to lB.OV
Low Side Channel Output Voltage, VLO ...•..•. -0.5V to Vec+0.5V
Logic Supply Voltage, Voo ••.....•........•..•• -o.5V to lB.OV
Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . -0.5V to Voo+0.5V
(HIN, LIN & SO (Shutdown)]
Thermal Resistance
OJA
75°CIW
HIP2500IP ••••...•..••.•••.•..•.•.••••.••.
BOoCIW
HIP2500IPI •••••••••.•••.••••••...•.•.••.•
900 CIW
HIP2500IB •..••..•••.•••••••.••.•••.•••..•
See Maximum Power Dissipation vs Temperature Curve
Junction Temperature Range •...••••••••.•••. -40oC to +125°C
Storage Temperature Range, Ts •••....•••••••• -40OC to +150oC
Operating Ambient Temperature Range, T" .•..••• -400C to +B5°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only raUng end operation
of the device at these or any other conditions above those indicated in the opera60na/ sections 01 this speciflca60n Is not implied.
Recommended DC Operating Conditions
Floating Supply Voltage, VB' ..............• Vs+l0V to Vs+15V
(Floating Terminal)
High Side Channel Output Voltage, VHO .....•..•.••.. 1OV to Va
(With Respect to Vs)
Fixed Supply Voltage, Vce ..•••....•......•......• 10V to 15V
Low Side Channel Output Voltage, VLO •..••.••.•••.. OV to Vcc
Logic Supply Voltage, Voo ........................ 4V to Vee
Floating Supply Voltage, Vs •••..•...•..•....... -4.0V to 500V
(Common Terminal)
Electrical Specifications vee = (Va-Vsl = Voo = 15V, COM = Vss = 0, Unless Otherwise Noted
TJ
= +25°C
TJ
= ·40·C TO +125"C
SYMBOL
MIN
TVP
MAX
MIN
TYP
MAX
UNITS
Quiescent Vee Current
lace
-
1.5
1.9
-
2.0
rnA
Quiescent Ves Current
laas
-
300
400
300
435
ItA
QUiescent Voo Current
laoo
-
0.1
1
-
I.B
ItA
-
ItA
22
ItA
PARAMETER
OC CHARACTERISTICS
Is (500V)
-
0.4
3.0
Logic Input Pulldown Current, VIN
(HIN, LIN, SO)
=Voo
IN+
-
12
20
-
Logic Input Leakage Current, VIN
(HIN, LIN, SO)
=Vss
IN-
-
0
1
-
0
1
ItA
Logic Input Positive Going Threshold
VTH+
7.5
B.O
B.5
7.5
B.O
B.6
V
Logic Input Negative Going Threshold
VrH-
5.5
5.9
6.3
5.5
5.9
6.4
V
Undervoltage Positive Going Threshold
UV+
B.O
9.35
9.99
7.B
V
UV-
7.7
9.05
9.69
7.5
9.69
V
Hysteresis (Ved
UVHYS (Ved
250
-
450
170
-
9.99
Undervoltage Negative Going Threshold
530
mV
Undervoltage Hysteresis (Vas)
UVHYS (Vas)
250
-
450
170
-
530
mV
Vour +
14.95
15
-
14.95
15
-
V
Output Low Open Circuit Voltage (HO, LO)
Your
-
-
0.05
-
-
0.05
V
Output High Short Circuit Current (Sourcing)
lour+
1.65
2.1
-
1.15
1.6
A
Output Low Short Circuit Current (Sinking)
lour-
I.B5
2.3
-
1.35
1.7
-
Quiescent Leakage Current
Undervo~age
Output High Open Circuit Voltage (HO, LO)
4-11
A
w
g
~
ID
U.
..oJ
4(
::t:
Specifications HIP2500
Switching Specifications
=
TJ -4O"C TO +125"C
TJ=+25"C
PARAMETER
SYMBOL
MIN
TVP
MAX
MIN
TVP
MAX
UNITS
-
725
ns
HIGH SIDE CHANNEL WITH 500V OFFSET, CL = 1000pF
High Side Tum-On Propagation Delay
toN
320
420
525
230
High Side Turn-Off Propagation Delay
-
625
ns
25
50
ns
25
50
ns
190
-
600
ns
175
-
475
ns
50
-
30
50
ns
25
50
-
30
50
ns
300
400
490
200
-
650
ns
240
320
400
180
-
500
ns
M\
0
-
125
0
-
185
ns
Minimum On OUtput Pulse Width (HO, LO)
PWOUT(MIN)
-
35
50
-
35
55
ns
Minimum Off OUtput Pulse Width (HO, LO)
PWl5ll'rMIN
275
440
640
250
440
650
ns
Minimum On Input Pulse Width (HIN, LIN)
PWON(MIN)
100
145
-
110
200
DHtoN
-
125
OLtoN
-
-20
-
dVsldt
-
-
50
toFF
300
385
450
230
High Side Rise Time
~
-
25
50
High Side Tum-Off Fall Time
IF
-
25
50
-
toN
250
365
450
toFF
225
295
370
Low Side Tum-On Rise Time
~
-
25
Low Side Tum-Off Fall Time
IF
-
High Side Shutdown
tsoHO
Low Side Shutdown
tsoLO
LOW SIDE CHANNEL, CL = l000pF
Low Side Tum-On Propagation Delay
Low Side Tum-Off Propagation Delay
Shutdown Propagation Delay
HIGH SIDE CHANNEL WITH 500V OFFSET, CL = l000pF
Turn-On Propagation Delay Matching
(Between HO and LO)
Minimum Off Input Pulse Width (HIN, LIN)
PWOFF(MIN)
Deadtime LO Tum-Off to HO Turn-On
Deadtime HO Turn-Off to LO Turn-On
-
100
175
ns
110
220
ns
125
-
ns
-
-20
-
-
ns
MAXIMUM TRANSIENT CONDITIONS
Offset Supply Oparatlng Transient
50
Logic Truth Table
HIN
LIN
UVH
UVL
SO
HO
LO
0
0
0
0
0
0
0
Normal Off
0
1
0
0
0
0
1
Lower On
1
0
0
0
0
1
0
Upper On
1
1
0
0
0
1
1
Both On
X
X
X
X
1
0
0
Chip Disabled
COMMENTS
X
X
1
1
X
0
0
Vee UV Lockout and Ves Lockout
X
1
1
0
0
0
1
Ves UV Lockout
1
X
0
1
0
1
0
Vcc UV Lockout
4-12
Vlns
HIP2500
Typical Performance Curves
2.5
~ 2.25
z
g
:
~
...... ;::::
2
1.75
iii
jg
1.5
ffi
1.25
~
::Ii
0.75
::>
::Ii
0.5
~
I I
V
HIP250()'IP
/ ' HIP250()'IPl
V
,/
~
...... ~ ~ , /
...... ~ ~
~
J
iii
jg
:II!!!!!
....
IIiIIII
... ~ ...
~
~
....
Vs .100V
:;,...r
;......r
0.01
.J;
...
~
S_
%
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90100110120130
AMBIENT TEMPERATURE (OC)
FIGURE 1. MAXIMUM POWER DISSIPATION vs TEMPERATURE
I I
0.001
10
IIII
1000
100
SWITCHING FREQUENCY (kHz)
FIGURE 2. HIGH VOLTAGE POWER DISSIPATION vs
SWITCHING FREQUENCY
10
6r---r-------,--------r----~
Vs=Vss = COM
Vas" Vee" 15Voc
TA=+250C
.... ~
1.0
!i!!:
In
In
"- o~
~
is
IX:
w
~~
I
0.1
~
--..
~
~
Vs ·400V
..... ...... Vs=300V
Vs·200V
IX:
o
z
VaIAS" 15V
CL" 100pF
TA,,+250C
!i...
HIP2500-IB
0.25
0
1.0
z
o
....'!lII~
0.1
...~
2100pF
907pF
l00pF
0.01
-4~
10
100
SWITCHING FREQUENCY (kHz)
__L __ _ _ _ _ _L __ _ _ _ _ _L __ _ _ _ _ _
1000
10
~~
16
12
14
SUPPLY VOLTAGE (V)
NOTE: All switching losses assumed to be in IC.
FIGURE 3. LOW VOLTAGE POWER DISSIPATION vs
FREQUENCY
FIGURE 4. Vss OFFSET vs V ee SUPPLY VOLTAGE
~ 10
10
~
200V
r-
I
~
'til""
I 5riOV
~
400V\
300V
~ ~ ~ ",
""'V-"
./
"
... 100V
~
i-"""
4
"...
~
o
~
20
40
60
80
100
TEMPERATURE (OC)
r--
6
5
0.1
I
8
7
i"""
Vee .15V AND 12V
TJ=+2SoC
9
120
140
FIGURE 5. OFFSET SUPPLY LEAKAGE vs TEMPERATURE
::
~
3
::Ii
2
I
II
Vee=15V~
......... ~~
.,.,...
....... "
"....
........... i-""'"
-I--
.........-
-
Vee = 12V
V
10
11
12
13
14
15
16
BOOTSTRAP SUPPLY VOLTAGE
17
18
FIGURES. MAXIMUMNEGATIVEVsOFFSETVOLTAGEvsVBS
VOLTAGE
4-13
HIP2500
Typical Performance Curves
8,35
~
8.3
5
11.25
g
9.2
~
w
CJ
9.15
8.1
~
g
.....
~
11.0
::I
8.95
10
,
TJ. _40°C TO +125oC
, '
"I~BSI
.........
" "-" "'
r-........ .........
~~
"l: .......
1""-00..
~VCCUV+
V
"" I"
VBS UV-
z
~
c
8
'"a:
6
w
UV+
./
()
§
-4~
-20
0
20
40
60
80
TEMPERATURE 1°C)
100
~
120
6
i:l
300
......~
250
ill
J 200
~
....
-
I
~14VIQBSI
~-
......
~
14VIQBSO
I
-
~.10VIQBSI
()
I::I
...
8
10
12
14
16
I
80
18
~
60
c
~
40
K!
20
-
IR
IF
o
I
o
50
100
JUNCTION TEMPERATURE 1°C)
100
150
~
~ ...
1000
lE4
LOAD CAPACITANCE IpF)
FIGURE 10. RISE AND FALL TIME va LOAD CAPACITANCE
3.0
zw
a:
a:
::I
~
100
w
/.10VIQBSO
FIGURE 9. QUIESCENT VBS SUPPLY CURRENT vs
TEMPERATURE
I-
VTH-
~
-'
I
-so
2.5
",.
FIGURE 8. INPUT LOGIC THRESHOLD va SUPPLY VOLTS
I
!!!'"
18VIQBSO
I
150
g
I"""
~
LOGIC SUPPLY VOLTAGE (V)
118VIQ~SI
350
~
~
~ liP""
120
450
Ii
~
2
140
FIGURE 7. UNDERVOLTAGE LOCKOUT va TEMPERATURE
1 400
./
4
U
L
I
./
VTH,,/
::c
l-
~CCU v-
./
I
5::c
.....
11.05
a:
w
c
(Continued)
30
·40
0
25
.....
"",U'
2.0
~
....... SOURCE DRIVER
SINK DRIVER
2
4
6
8
10
12
14
SOURCE/SINK DRAIN·SOURCE VOLTAGE
~
22
-'
50
...cw
28
w
::Ii
II"''''''
.............
1.5
....s
26
24
-'
~
20
cz
18
C
w
16
K!
14
-
-
- - ---
...-
~
......... r--
IF-
~-
12
10
-so
16
0
50
TEMPERATURE rC)
100
FIGURE 12. RISE AND FALL TIME va TEMPERATURE
FIGURE 11. DRIVER SINKISOURCE V-I CHARACTERISTIC
4-14
150
HIP2500
Typical Performance Curves
.
..s
w
:I
>=
oJ
~
30
~
26
~
22
20
'w"
16
tA
400
iii
!.i<:I
380
II.
12
11
12
13
14
SUPPLY VOLTAGE (V)
15
FIGURE 13. RISE AND FALL TIME va SUPPLY VOLTAGE
HtOFF
360
LioN
340
I I
320
lloF!
300
10
16
HlON
420
~
~
0
a:
14
10
10
440
!
24
18
~
460
28
0
z
(Continued)
12
13
14
SUPPLY VOLTAGE (V)
11
15
16
FIGURE 14. PROPAGATION DELAY va SUPPLY VOLTAGE
700
HtoN
!
600
~
z
500
LioN
11 V OC
floating power supply required to drive the upper rail external
power device is created and managed by the HVIC through
CF and DF This capacitor is refreshed from the Voo supply
each time VOUT goes low. If the upper channel is commanded on for a long period of time, the bootstrap capacitor
CF is automatically refreshed by bringing VOUT low. This is
accomplished by turning off the upper rail MOSFETIIGBT,
momentarily tuming on the lower rail output device, followed
by returning control back to the upper switch. Otherwise, C F
would gradually deplete its charge allowing the upper switch
to come out of saturation. The upper and lower gate drivers
allow for controlled charge and discharge rates as well as
facilitate the use of nearly lossless current sensing power
MaS devices. The over current trip level can be boosted
30% on a pulse by pulse basis by logic level '1' applied to
ITRIPSELECT. A FAULT output signal is generated when any
of the following occurs:
V bias is low
Over current is detected
V phase doesn't agree with the input signal
Reset of FAULT is provided by externally removing power or
by holding both TOP and BOT inputs low for the required
reset time (trtMAX).
Each application can be individually optimized by the selection of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (Rd and discharge
(Ro) impedance chosen per the load capacitance, frequency
of operation. and DVDT dependent recovery characteristics
of the associated FBDs. Ro should also be sized to prevent
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (tOFF MIN).
The selection of over current detection resistors (Rp). compatible with current sense MOSFETsllGBTs or shunt(s) may
be used.
For the floating bootstrap supply OF and CF must be determined. OF must support the worse case system bus voltage
and handle the charging currents of CF. Proper selection
should take into consideration T RR and T FR per the desired
operating frequency. Proper selection of CF is a trade off
between the minimum toN time of the lower rail to charge up
the capaCitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350~s TYP (or even sooner if input commands the TOP to switch at a faster repetition rate).
The local filter capacitor (Coo) should be sized sufficiently
large enough to transfer the charge to C F without causing a
significant droop in Voo. As a rule of thumb it should be at
least 10 times larger than C F and be located adjacent to the
Voo and Vss pins to minimize series resistance and
inductance.
Refer to Application Note AN8829 for more details about module operation and selection of external components.
4-22
SP601
HARRIS
SEMICONDUCTOR
Half Bridge 500V DC Driver
April 1994
Features
Description
• Maximum Rating •..••.••.•••••.•••••••••••• soov
The SP601 is a smart power high voltage integrated circuit
(HVIC) optimized to drive MOS gated power devices in halfbridge topologies. It provides the necessary control and
management for PWM motor drive, power supply, and UPS
applications.
• Ability to Interface and Drive Standard and Current
Sensing N-Channel Power MOSFETnGBT Devices
• Creation and Management of a Floating Power Supply
for Upper Rail Drive
• Simultaneous Conduction Lockout
Ordering Information
• Overcurrent Protection
• Single Low Current Bias Supply Operation
PART
• Latch Immune CMOS Logic
• Peak Drive in Excess of O.SA
Pinout
SP601
TEMPERATURE
RANGE
-40°C to +85°C
PACKAGE
22 Lead Plastic DIP
w
g
Functional Block Diagram
a:III
SP601 (PDIP)
TOP VIEW
u..
..J
2 UPI
DOWN
21
~LE
NC
VBIAS
I.
100RND
G~I:U} ~
L--_ _
3
Voo
G2U
1t:----~11
VDO'
c(
3.50R as
~
TRIPu
11
15
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
4-23
File Number
2429.4
J:
Specifications SP601
Thermal Information
Absolute Maximum Ratings Full Temperature Range. All
Voltage Referenced to Vss Unless Otherwise Noted. Note 1. Note 2.
Low Voltage Power Supply. VBIAS (Note 1) •.•••••••••••• 18VDC
Floating Low Voltage Boot Strap • • • • • • • • . • • • . . . . • • . • •• 18VDC
Power Supply to Phase. Ves
Low Voltage Signal Pins
Fault. ITRIPSEL. Voo. TRIP L• CL1. G2L .•••••-o.5Voc to Voo +0.5
G1L. D1L. VOF • TOP. BOT
CL2. TRIP u • G1U. G2U. D1U to Phase •..•• -0.5voc to VBs+O.5
High Voltage Pins
Phase. VPHASE •. • • • . • • • • • . • • • • • . • • • • • . . . • . . . • . • 500VDC
(VSS • VOUT. TRIP u• CL2. G2U and D1U: OV-18V Higher Than
Phase)
Dynamic High Voltage Rating Phase •.•..••••.••.• 10.000VlIJS
DVpHASEIDT
Thermal Resistance. Junction-to-Ambient
9JA
Plastic DIP Package • • • • • • • .. .. .. .. • .. . .. . • • 750 CIW
Maximum Package Power Dissipation at TA = +85OC. Po
Plastic DIP Package ............................. 500mW
Operating Ambient Temperature Range. TA .•.•.•• -25°C to +85°C
Storage Temperature Range. Ts ............... -40°C to +lSOOC
Lead Temperature (Soldering lOs) •.•..•....•..••..... +265°C
NOTES:
1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RNO)'
Prolonged high peak currents may resuR if +15Voc is applied abruptly and/or if the local bypess cspacitor COD is large. It is suggested that COD be:s 10MFD.
If it is desirable to switch the 15Voc source or if a COD is larger, add"ional series impedance may be required.
2. Consult factory for add"ional package offerings.
CAUTION: Stresses above those listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the Op6raUonal sections of this specificaUon is not implied.
Electrical Specifications (VBlAS = 15V. Pulsed <300ms). Unless Otherwise Noted. All Parameters Referenced to Vss Except
TRIP u • CL2. G1U. D1U. and Ves Referenced to PHASE. DF: VOF to Ves. CF: Ves to PHASE
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
20
30
jIA
30
33
jIA
1.7
2.05
rnA
-40°C to +95°C
-
1.7
2.1
rnA
+25°C
-
1.7
2.05
rnA
mA
DC CHARACTERISTICS
Input Current (5V < VTOP , VSOT • VTRIPSEL < 15V)
+25°C
liN
-40°C to +85°C
ISlAS Quiescent Current (All Inputs Low)
IBiASL
ISlAS Quiescent Current
(VOUT 2: VSIAS • and All Inputs Low)
ISI~
Iss Quiescent Current Bootstrap Supply
+25OC
-40°C to +95°C
+25°C
les
_40°C to +95OC
ENABLE Threshold Level
VTOP
UP/DN Threshold Level
VSOT
Current Trip Select Threshold Level
VTRIPSEL
Trip Lower and Upper Comparator Threshold
Level- Normal (ITRIPSEL Vss)
VTRIPLJUN
Trip Lower and Upper Comparator Threshold
Level - Boost (ITRIPSEL VDO) % of Measured
VTRIPLJUN
VTRIPLJUS
=
=
Under Voltage Lockout Thresholds (Voo and Ves)
Phase Out of Status Voltage Threshold (PHASE)
Faultbar Impedance at IFBAR
=1rnA
VLOCK
VOSVT
RF
4-24
-
1.7
2.1
875
1000
jIA
900
1060
I1A
+25OC
7
8
9
V
-40OC to +95°C
6.95
8
9.1
V
+25OC
7
8
9
V
-40oC to +85°C
6.95
8
9.1
V
+25°C
7
8
9
V
-400C to +95OC
6.95
8
9.1
V
+25°C
90
105
125
mV
-40oC to +95OC
90
105
127
mV
+25°C
110
130
150
%
-40°C to +9SOC
109
130
152
%
+25°C
9
10
11.5
V
-40°C to +8SOC
9.7
10.5
11.8
V
+25°C
5
7
9
V
-4OOC to +95°C
4.7
7
9.6
V
+25°C
500
760
1000
-40°C to +85°C
450
760
1100
n
n
Specifications SP601
Electrical Specifications
=
(ValAs 15V. Pulsed <300ms). Unless Otherwise Noted. All Parameters Referenced to Vss Except
TRIPu • CL2. G1U. Dl U. and Vas Referenced to PHASE. DF: VDF to Vas. C F: Vas to PHASE (Continued)
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
Rsouu
+25°C
12
17
23
-40oC to +85°C
7
17
29
+25°C
8
12
16
-40°C to +85°C
5
12
20
+25°C
2
3.5
5
-40oC to +85°C
1.4
3.5
5.6
+25°C
6
10
14
-40°C to +85°C
5.4
10
14.6
n
n
n
n
n
n
n
n
ILK
+25°C
-
1
3
JlA
V D1U/L
+25°C
0.4
0.9
1.4
V
VCL21HOW
+25°C
6.35
6.61
6.85
V
-40°C to +85°C
6.15
6.61
7.15
V
V CL2I1.HIGH
+25°C
7.0
8.5
8.0
V
Ra
+25°C
2
3.5
5
-40°C to +85°C
1.4
3.5
5.6
n
n
Upper/Lower Source Impedances (lsoURCE = lOrnA)
Upper/Lower Sink Impedances (ISINK = lOrnA)
Rsluu
Bootstrap Supply Current Limiting Impedance
Ras
Noise Dropping Resistor Impedance
RND
High Voltage Leakage (500V Vas. Your. PHASE.
TRIPu • CL2. G1U. G2U. and D1U to Vss.
All other Pins at V5S)
Miller Clamp Diodes; D1U and D1L (10 = lOrnA)
Noise Clamping Zeners; CL2 and CL 1 (I z = lOrnA)
Noise Clamping Zeners; CL2 and CL 1 (Iz = 50mA)
Your Limiting Resistance
NOTE: Maximum Steady State + 15Voc Supply Current = lalAsL + las
Switching SpeCifications
(All Referenced to Vss. Except: TRIP u • CI2. G1 U. G2U. and Dl U Referenced to PHASE.
DF: V DF to Vas. C F: Vas to PHASE)
PARAMETER
Refresh One Shot Timer
Delay Time of Trip I/U Voltage (IrRIPsEL low) to
G2U1G2L Low (SO% Overdrive
Delay Time of Trip I Voltage (lrRIPsEL low) to
Faultbar Low
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
tREF
+25°C
200
350
500
I1S
-40oC to +85°C
180
350
540
I1S
+25°C
2
3
4
I1S
-40oC to +85°C
1.85
3
4.35
I1S
+2SoC
2
3
4
I1S
-40oC to +85°C
1.85
3
4.35
I1S
+25°C
500
700
900
ns
-40oC to +85°C
400
700
1050
ns
+25°C
300
430
600
ns
-40oC to +85°C
275
430
660
ns
+25°C
1.6
2.3
3.1
I1S
-40oC to +85°C
1.5
2.4
3.4
I1S
+25°C
1.3
2.0
3.4
I1S
-40oC to +85°C
1.05
2.1
3.9
I1S
+25°C
2.5
3.2
4.5
I1S
-40oC to +85°C
2.1
3.3
5.2
I1S
+25°C
2.5
3.2
4.5
I1S
-40oC to +85°C
2.1
3.3
5.2
I1S
IoFFTN
tFN
Delay Time of Phase Out of Status to Faultbar
Low (TOP High)
IosvF
Minimum Logic Input Pulse Width: TOP and
BOTTOM
tMINIW
Minimum G1U1G1L On Time
ioN
Minimum Pulsed Off Time. G2U/G2L
IoFF
Turn On Delay Time ofG1U (BISTATE MODE)
Turn On Delay Time of G 1L (BISTATE MODE)
IoND
IoND
4-25
Specifications SP601
Switching Specifications (All Referenced to Vss , Except: TRIP u , CI2, G1U, G2U, and D1U Referenced to PHASE.
OF: VOF to Yes, CF: Ves to PHASE) (Continued)
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
Turn On Delay TIme of G 1U
(THREE·STATE MODE)
PARAMETER
laND
+25OC
0.75
1.0
1.5
lIS
-40°C to +8500
0.60
1.1
1.75
lIS
Turn On Delay TIme of Gl L
(THREE·STATE MODE)
laND
+25°C
0.75
1.0
1.5
lIS
-400 C to +85°C
0.60
1.1
1.75
lIS
Turn Off Delay Time of G2U and G2L
IaFFO
+25°C
0.75
1.0
1.45
lIS
-400 C to +65°C
0.60
1.1
1.75
lIS
+25°C
1.5
2.5
3.5
lIS
-400 C to +85OC
1.2
2.6
4
lIS
+25°C
3.4
4.5
6.6
lIS
-400 C to +85°C
3.15
4.8
7.4
lIS
+25°C
25
50
100
ns
-40°C to +85°C
15
50
115
ns
+25°C
25
50
100
ns
-400 C to +85°C
15
50
115
ns
Minimum Dead TIme: G 1U OFF to G1L ON, or
G1L off to G1U on (BISTATE MODE)
to.T.
Fault Reset Delay to Clear Faultbar
iR:r.
Rise TIme of Upper and Lower Driver
(Load =2000pF)
iR U/I.
Fall TIme of Upper and Lower Driver
(Load =2000pF)
tF Ull
Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to Vss, Unless
Otherwise Noted. See Figure 1)
PARAMETER
CONDITION
FAULTBAR
Open Drain Fault Indicator Output
ITRIPSELECT
Digital Input Command to Increase TRIP L and TRIPu Threshold by 30%
VB1AS
14.5V to 16.5V with 15V nominal, '" 1.5mA DC BIAS Current
Voo
Coo to Vss
Vss
COMMON
TRIPI
CLI
G2LandG1L
100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output
Lower Noise Clamp Zener
Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER)
VOF
Current Umiting Charging Resistor for Bootstrap Capacitor Power Supply
Ves
Bootstrap Supply, Normally a Diode Drop BelOW VOO Voltage with Respect to the Floating PHASE Reference
VOUT
Load Connection Node
PHASE
Floating Reference Point for High Side Control Circuitry: Vas, TRIPu, Cl2, Gl U, G2U and 01 U
TRIPu
100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive
Cl2
G2U andG1U
ENABLE
UP/ON
Upper Noise Clamp Zener
Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER)
Digital Input to ENABLE the UP/ON Command to Turn on Top/Botlom Devices
Digital Input to Top/Botlom Device (If ENABLE is High)
DIU
Miller Clamp UPPER to Vas
D1L
Miller Clamp LOWER to Voo
4-26
SP601
Timing Diagram
ENABLE
o
0
UPIDOWN
o
0
REFRESH
ONE SHOT
10NB
VAUDBOTON
10FFT
IoNT
IoF~
UPPER
LOWER
VOUT
1
0
1
0
1
U
--1l
1
o
1
o
1
0
o
0
0
o
1
10F~
0
0
UPPER
__________nl...-_
0
1
0
LOWER
0
0
C:~\J
-,}
VOUT
THREE·STATE MODE SLOWER THAN REFRESH ONE SHOT nMER
VOC
COM
BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER
NOTE: BOT switching not relevant.
Typical Circuit Configuration
TRUTH TABLE
Applicable to Typical Circuit Configuration (Figure 1)
OUTPUTS
INPUTS
UPIDN
ENABLE
TRIPL
TRIPU
PHASE
VB1AS
UPPER
LOWER
FAULT BAR
0
0
0
X
X
1
0
0
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
X
0
1
0
0
0
X
X
1
X
X
1
0
0
0
0
1
0
X
X
1
0
1
1
1
0
0
X
X
1
0
0
1
X
X
X
X
X
0
0
0
0
NOTE: 0 =False, 1 =True, X =Don't Care
4·27
SP601
25VOC;; VUNK ;; 5OOVOC
RCU ROU
RpU
19
18
17
D1U GW G2U TRIPU
....
21
8
22
i...
::I!
I!!
(I)
>(I)
2
14
15
PHASE
VOUT
13
12 CF
VBS
BOT
VOF
VOUT
11 OF
•••• J"f'N\. ••••
TOP
SP601
HVIC
Dll
mTCf
Gll
ITRIPSELECT
G2l
VBIAS VOO
Vss
TRIPL
10
lOAD
9
RCL
8
ROL
6
RpL
15V
COM
Coo
FIGURE 1. TYPICAL CIRCUIT CONFIGURATION
LEGEND
Application Specific
Rcu
Upper Gate Charging Resistor
Application Specific
Rou
Upper Gate Discharge Resistor
Application Specific
Rpu
Upper Current Pilot Resistor
Application SpecifIC
RCL
Lower Gate Charging Resistor
Application Specific
ROL
Lower Gate Discharging Resistor
Application Specific
RpL
Lower Current Pilot Resistor
311F at" 15DC
Coo
Local LV Filter Capacitor
O.2211F Ceramic X7R at" 15Voc
CF
Flying Capacitor for Bootstrap Supply
Harris PIN A114M or Equiv PRY " VL1NK
OF
Flying Diode for Bootstrap Supply
NOTE:
Refer to 'Additional Product Offerings' for information concerning power output devices.
4-28
SP601
Functional Description
The SP601 provides a flexible, digitally controlled power
function which is inte,nded to be used as PWM drivers of
N-Channel MOSFETs and/or IGBTs for up to 240VAC line
rectified totem-pole applications. The CMOS driveable
inputs are filtered and captured by the control logic to determine the output state. The logic includes fixed timing to prohibit simultaneous conduction of the external power switches
and, thru the VOUT sense detector, verifies the output voltage
state is in agreement with the controlled inputs. The> 11 VDC
floating power supply required to drive the upper rail external
power device is created and managed by the HVIC through
CF and Dp This capacitor is refreshed from the Voo supply
each time VOUT goes low. If the upper channel is commanded on for a long period of time, the bootstrap capacitor
CF is automatically refreshed by bringing VOUT low. This is
accomplished by turning off the upper rail MOSFETIIGBT,
momentarily turning on the lower rail output device, followed
by returning control back to the upper switch. Otherwise, CF
would gradually deplete its charge allowing the upper switch
to come out of saturation. The upper and lower gate drivers
allow for controlled charge and discharge rates as well as
facilitate the use of nearly lossless current sensing power
MOS devices. The over current trip level can be boosted
30% on a pulse by pulse basis by logic level '1' applied to
ITRIPSELECT' A FAULT output signal is generated when any
of the following occurs:
V bias is low
Over current is detected
V phase doesn't agree with the input signal
Reset of FAULT is provided by externally removing power or
by holding the ENABLE input low for the required reset time
(trtMAX)'
Each application can be individually optimized by the selection of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (Rd and discharge
(Ro) impedance chosen per the load capacitance, frequency
of operation, and D~T dependent recovery characteristics
of the associated FBDs. Ro should also be sized to prevent
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (toFF MIN)'
The selection of over current detection resistors (Rp), compatible with current sense MOSFETsllGBTs or shunt(s) may
be used.
For the floating bootstrap supply OF and CF must be determined. DF must support the worse case system bus voltage
and handle the charging currents of CF. Proper selection
should take into consideration T RR and TFR per the desired
operating frequency. Proper selection of C F is a trade off
between the minimum ioN time of the lower rail to charge up
the capacitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350jls TYP (or even sooner if the UPIDN
input switches at a faster repetition rate).
The local filter capacitor (Coo) should be sized sufficiently
large enough to transfer the charge to CF without causing a
significant droop in Voo. As a rule of thumb it should be at
least 10 times larger than CF and be located adjacent to the
Voo and Vss pins to minimize series resistance and
inductance.
Refer to Application Note AN8829 for more details about module operation and selection of external components.
4-29
INTELLIGENT 5
POWERICs
AC TO DC CONVERTERS
PAGE
AC TO DC CONVERTER SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
AC TO DC CONVERTER DATA SHEETS
CA3059. CA3079
Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . .
5-3
HV-2405E
World-Wide Single Chip Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15
5-1
AC to DC Converter Selection Guide
DEVICE
CA30S9
CA3079
DESCRIPTION
Zero Voltage Sw~ch
AC Power Control
System on a Chip
ACINPUT
VOLTAGE AT
S()'60HzAND
400Hz (VAC)
MAX
DC SUPPLY
VOLTAGE
(V)
MAX
OUTPUT
CURRENT
(rnA)
SENSOR
RANGE
(RX) (Kn)
24V
120V
14
124
2 to 100
208l230V
10
124
2to 50
Output
SVto 24V
50
-
2nV
HV-240SE
World Wide Single
Chip Power Supply
15Vto 275V
FEATURES
Contains, Power Supply Zero
Crossing Detector, External
Sensor Comparator and Triac
Driver. (Inhibit and Protection
Circuits on CA30S9 only)
UL Recognized EI30808
NOTE:
1. Electrical Characteristics at TA = +25°C, 14 Lead Dual-In-Une (E) Package
Operating Temperature Range (TA) -55°C to +125°C.
DEVICE
DESCRIPTION
HIP5600
High Vo~age
Linear Regulator
INPUT
VOLTAGE
RANGE
OUTPUT
VOLTAGE
RANGE
MAXIMUM
OUTPUT
CURRENT
BIAS
CURRENT
50Vto 400V
1.2V to
35mA
600llA
350V
5-2
TEMPERATURE RANGE
-400C to +100oC
Thermal Protection at 134°C
CA3059, CA3079
Zero-Voltage Switches for 50Hz-60Hz and
400Hz Thyristor Control Applications
PRELIMINARY
April 1994
Features
Description
• Relay Control
The CA3059 and CA3079 zero-voltage switches are monolithic silicon integrated circuits deSigned to control a thyristor
in a variety of AC power switching applications for AC input
voltages of 24V. 120V. 208l230V. and 277V at 50Hz-60Hz
and 400Hz. Each of the zero-voltage switches incorporates
4 functional blocks (see the Functional Block Diagram) as
follows:
• Valve Control
• Synchronous Switching of Flashing Lights
• On-Off Motor SwHchlng
• Differential Comparator with Self-Contained Power
Supply for Industrial Applications
• Photosensitive Control
1. Limiter-Power Supply - Permits operation directly from an
ACline.
• Power One-Shot Control
• Heater Control
2. Differential On/Off Sensing Amplifier - Tests the condition
of external sensors or command signals. Hysteresis or
proportional-control capability may easily be implemented in this section.
• Lamp Control
Type Features
CA3059 CA3079
• 24V, 120V, 208l230V, 277V at 50/60. . . .
or 400Hz Operation
X
X
• Differential Input • • . . . • • • • • • • • • • • . •
X
X
• Low Balance Input Currant (Max) - J.1A. • •
• Built-In Protection Circuit for. • • • • • • •
Opened or Shorted Sensor (Term 14)
1
X
2
X
• Sensor Range (Rlc) - kQ •••••.••••••• 2 -100 2 - 50
• DC Mode (Term 12) •••.••••••.•••••
X
• External Trigger (Term 6). . • • . • . • • • • •
X
• External Inhibit (Term 1) ••••••••••••
X
• DC Supply Volts (Max) •••••••••••••
• Operating Temperature Range (OC) • .•
14
3. Zero-Crossing Detector - Synchronizes the output pulses
of the circuit at the time when the AC cycle is at zero voltage point; thereby eliminating radio-frequency interference (RFI) when used with resistive loads.
4. Triac Gating Circuit - Provides high-current pulses to the
gate of the power contrOlling thyristor.
In addition. the CA3059 provides the following important
auxiliary functions (see the Functional Block Diagram).
1. A built-in protection circuit that may be actuated to remove
drive from the triac if the sensor opens or shorts.
10
2. Thyristor firing may be inhibited through the action of an
internal diode gate connected to Terminal 1.
-55 to +125
3. High-power dc comparator operation is provided byoverriding the action of the zero-crossing detector. This is accomplished by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous when Terminal
13 is positive with respect to Terminal 9.
Ordering Information
PART NUMBER
TEMPERATURE
PACKAGE
CA3059
-55°C to +125°C
14 Lead Plastic DIP
CA3079
-55°C to +125°C
14 Lead Plastic DIP
The CA3059 and CA3079 are supplied in 14 lead dual-inline plastic packages.
Pinouts
CA3079 (PDIP)
TOP VIEW
CA3059 (PDlP)
TOP VIEW
INHIBIT
DC SUPPLY
HIGH CURRENT
NEG. TRIGGER
TRIGGER OUT
ACIN
TRIGGER IN
COMMON
FAIL-SAFE
DONOTUSE 1
3 SENSE AMP IN
DCSUPPLY 2
H~~~5r~~:g~~
ZCD OVERRIDE
1 R DRIVER (COM)
3
TRIGGER OUT 4
o R DRIVER V·
1 DONOTUSE
1 SENSE AMP IN
1 DONOTUSE
11 R DRIVER (COM)
1 RDRIVERV·
SENSE AMP REF
DONOTUSE 6
COMMON 7
COMMON
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedure•.
Copyright © Harris Corporation 1994
5-3
9 SENSE AMP REF
8 COMMON
File Number
490.3
til
()a:
Q~
Oa:
t- W
(»
«~
()
CA3059, CA3079
Functional Block Diagram
• NEGATIVE TEMPERATURE COEFACIENT
AC INPUT VOLTAGE (50160 OR 400Hz)
VAC
INPUT SERIES RESISTOR (RS>
kO
DISSIPATION RATING FOR Rs
W
24
2
0.5
120
10
2
2081230
20
4
277
25
5
NOTE: Circuitry within shaded areas, not included In CA3079
• See chart
.& IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)
Rp
RSENSOR
Ra
15
Ra
25
FOR
INCREASED
GATEDRIYE
TO
THYRISTOR
GATE
All resistance values are in 0
NOTE: Circuitry within shaded areas
not Included In CA3079
INHIBIT
INPUT
.& IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)
FIGURE 1. SCHEMATIC DIAGRAM OF CA3059 AND CA3079
5-4
Specifications CA3059, CA3079
Absolute Maximum Ratings TA = +25°C
Thermal Information
DC Supply Voltage (Between Terminals 2 & 7)
CA3059 ...........................•.•............ 14V
CA3079 .•.••.••...••..••.•.••....•••••.....•.•.•• 10V
DC Supply Voltage (Between Terminals 2 & 8)
CA3059 .......................................... 14V
CA3079 ...••..•.•••••..•.•.•.......•••.........•. 10V
Peak Supply Current (Terminals 5 & 7) ................... ±50mA
Output Pulse Current (Terminal 4) •••...•.......•..••.. 1SOmA
Thermal Resistance
8JA
PDIP Package •.•..•...•.•...•.•...•..•.••.... 1000CIW
Power Dissipation
Up to TA = +55°C CA3059, CA3079 .••..••.•..•..•.. 9SOmW
Above TA = +55°C CA3059, CA3079 •. Derate Linearly 10mWf'C
Ambient Temperature
Operating .•...••.....•...•••..•.......•. -55°C to + 125°C
Storage ................................ -65°C to + 1SOoC
Lead Temperature (During Soldering) .•....•.....•.••.• +265°C
At distance 1/16" ± 1132" (1.59 ± 0.79) from case
for 10 seconds max
CAUTION: Stresses above thoselis/ed in "Absolute Maximum Ratings" may causa parmanant damaga to the daviea. This is a stress only ra~ng and operation
of the device sf these or any other conditions above those indicated in the op6rational sections of this specification is not implied.
Electrical Specifications
TA = +25°C, For all Types, Unless Otherwise SpecHied. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
6.1
6.5
7
V
DC SUPPLY VOLTAGE (Figure 2A, 2B, 2C)
Inhibit Mode
Pulse Mode
At SO/60Hz
Vs
Rs=8kn,IL=0
At 400Hz
Rs =10kn,I L =0
At 5OI60Hz
Rs =5k!l,I L =0
-
6.4
-
Rs = 8k!l, IL = 0
6
6.4
7
V
6.7
-
V
At So/60Hz
Vs
At 400Hz
Rs= 10kn,I L =0
At SO/60Hz
Rs = 5k!l, IL = 0
Gate Trigger Current (Figures 3, 4A)
IGT
Terminal 4
6.8
Terminals 3 and 2 Connected,
VOT = 1V
-
6.3
V
V
V
rnA
105
cl!:!
PEAK OUTPUT CURRENT (PULSED) (Figures 4, 5)
With Internal Power Supply
Figure 4a, 4b
Oa:
10M
Terminal 4
With External Power Supply
Figure Sa, 5b, 5c
10M
Terminal 4
Inhibit Input Ratio (Figure 6)
Vi'/2
Terminal 3 open, Gate Trigger
Voltage (VOT) = 0
50
84
Terminals 3 and 2 Connected, Gate
Trigger Voltage (VGT) = 0
90
124
Terminal 3 open, V+ = 12V, VOT = 0
-
For Negative dv/dt
SO-60Hz
tp
C eXT = 0
400Hz
C eXT = 0, ReXT =
SO-60Hz
C eXT = 0
tN
400Hz
C eXT = 0, ReXT =
00
00
rnA
170
-
rnA
-
rnA
0.465
0.485
0.520
-
70
100
140
j.1S
-
12
-
j.1S
70
100
140
j.1S
-
10
-
j.1S
-
PULSE DURATION AFTER ZERO CROSSING (50-60Hz) (Figure 7A)
For Positive dv/dt
\p,
50
-
j.1S
For Negative dv/dt
tN'
-
60
-
j.1S
I,
-
0.001
10
vA
-
220
1000
nA
220
2000
nA
-
V
C eXT = 0, ReXT =
00
OUTPUT LEAKAGE CURRENT (Figure 8)
Inhibit Mode
INPUT BIAS CURRENT (Figure 9)
CA3059
II
-
CA3079
Common-mode Input Voltage Range
VeMR
Terminals 9 and 13 Connected
5-5
-
1.5 to
5
t-W
(»
TERMINAL 3 OPEN..............
I
40
4
.....
I
I
FIGURE 4B. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059 AND CA3079
~ts
o
CA3059, CA3079
C
!.
c
Rs
10K
~:::I
A-
..
120VRMS, 5OI6OHz OPERATIoN
GATE TRIGGER, VGT. 0 M
300
1/
250
200
:::I
A-
150
0
~
w
A-
100
o
5
FIGURE SA. PEAK OUTPUT CURRENT (PULSED) WITH EXTERNAL POWER SUPPLY TEST CIRCUIT FOR CA3059
"
200
'. '.
'"
", '.'"
.......
C
'.".
!.
cw
...
Ul
:::I
A-
R~
'."
".
"
150
..
#.....
:::I
0
lI<:
cC
W
A-
100
50
'.
~
~ EXTERNAL
SUPPLY
V+",13V
~
'.'.
"
~
. .........
~
"
12V
......... '-..
.... .....
~
.......
13V
..::;;,; ·12V
8V
r-- r-- I-
"...,
-."
.""
....
....., .... '"''
ALL RESISTANCE
VALUESINO
10V
......
..... .....
...•..
..... .....
·10V
"
.....
• 8V
i""""'-oo.
.,., I". ,.,.
'",
~
120VRMS
60Hz
" '""" "
~
'."
I-"
:::I
A-
RS
10K
"~ "r':
'.
FIGURE 6(A). INPUT INHIBIT VOLTAGE RATIO TEST CIRCUIT
FOR CA30S9 AND CA3079
12OVRMS, 60160Hz OPERATION
0.60
5V
0.56
3V
", " '
'"
.so
-20
10
40
70
100
I--.---.-----.r---.---.-----,-+-+--I
I-+-+--If-+-+--I-+-+--I
·5V
0.45 I--+--I--+---If--+--I--+---If--i
·3V
0.40 I--+--I--+---If--+--I--+---If--i
120VRMS, 50160Hz OPERATION
GATE TRIGGER VOLTS (VGT) = 0
TERMINALS 2 AND 3 CONNECTED
" " , . TERMINAL 3 OPEN
o
20
FIGURE SB. PEAK OUTPUT CURRENT (PULSED) vs EXTER·
NAL POWER SUPPLY VOLTAGE FOR CA3059
~\~
-"-
15
10
EXTERNAL POWER SUPPLY, V+ M
ALL RESISTANCE VALUES ARE IN 0
250
I
,~V
50
o
I
V/
:::I
OSCILLOSCOPE
WITH
HIGH GAIN
INPUT
CONNECTED
/ ' TERMINAL 3 OPEN
/
I-"
120VRMS
60Hz
TERMINALS 2 AND 3
~
130
.so
AMBIENT TEMPERATURE ("C)
FIGURE SC. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA30S9
~~ r--+--r-+--If--+--r-+--If-~
~
-25
0
25
50
75
100 125
AMBIENT TEMPERATURE ("C)
FIGURE 6B. INPUT INHIBIT VOLTAGE RATIO va AMBIENT TEMPERATURE FOR CASOS9 AND CAS079
5-8
CA3059, CA3079
OV
:
"
tNt
~
Z
~tN
120VRMS, S0I60Hz OPERAnON
TA=+25oC
300
100'
IIp (P~SlTItE dvJdt)
I
I
J..
I
I
-
~
IN
0
!iII:
I
:>
0
w
~
120VRMS
60Hz
200
/
:>
....
w
~
CJ
100
IV
(NEGAn~E dV~dt)
...I
~
o
o
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
NOTE: Circuitry w~hin shaded area not included in CA3079.
All resistance values are in a
EXTERNAL CAPACITANCE (I'F)
FIGURE 7A. GATE PULSE DURATION TEST CIRCUIT WITH
ASSOCIATED WAVEFORM FOR CA3059 AND
CA3079
FIGURE 7B. TOTAL GATE PULSE DURATION vs EXTERNAL
CAPACITANCE FOR CA3059 AND CA3079
700
40
r---r--r--------------------r-;
120VRMS, SO/60Hz OPERAnON
TA=+2SoC
12OVRMS, S0I60Hz OPERATION
TA" +2SoC
600
I--+--+--I--+---+-
500
(/)
tNi (NEGAnVE dv/dt)
Oa:
c~
400 I--+--+--I--+--+--I--t--~~~~
Oa:
t-W
0>
c(~
o
10
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
EXTERNAL CAPACITANCE 6tF)
100
EXTERNAL RESISTANCE (lin)
FIGURE 7C. PULSE DURATION AFTER ZERO CROSSING vs
EXTERNAL CAPACITANCE FOR CA3059 AND
CA3079
FIGURE 70. TOTAL GATE PULSE DURATION vs EXTERNAL
RESISTANCE FOR CA3059
FIGURE 7.
100
120VRMS, SOI6OHz OPERAnON
INPUT RESISTANCE (Rs = 10011n
NO EXTERNAL LOAD
c-
.s
w
CJ
I
V+=6V
If
10
g
I
I
W
...I
!;
1=
:>
.,
0
)
+3V
0.1
-80 -60 -40 -20
0
20
40
60 80 100 120 140
AMBIENT TEMPERATURE ("C)
FIGURE 8. OUTPUT LEAKAGE CURRENT (INHIBIT MODE) vs
AMBIENT TEMPERATURE FOR CA3059 AND CA3079
5-9
FIGURE 9. INPUT BIAS CURRENT TEST CIRCUIT FOR CA3059
ANDCA3079
CA3059, CA3079
lz
I
~
a:
:::I
C
!l
:::I
(+ dv/cIt)
!C
CI
100
...
...g
-,4
...
...
0.08
~
o
0.1
--
.....l- !"-'
~
!"-'
~~
~
60Hz, IN
(-dy/cIt) -
50Hz, IN
(- ~V/dl) I
0.04
r-
1 "I
0.06
0.1
0.08
EXTERNAL CAPACITANCE (11F)
FIGURE lOB.
600 , - - - - - - - - - - - - - - , , - - - . - - . , - - - ,
220VRMS, 50160Hz OPERATION
50Hz, INI
INPUT RESISTANCE (RS) = 101dl
(- dv/cIt)
600
220VRMS, SO/60Hz OPERATION
INPUT RESISTANCE (Rs) = 201dl
I
0.06
0.08
_-+__""-"'"
60HZ,IN1"
1 (- dv/dl)
~HZ,tNl --~~~~~~~~~
(- dy/dl)
400
0.04
- --
\.
/
0.02
FIGURE lOA.
0.02
50Hz, Ip
(+ dy/dl)
0
EXTERNAL CAPACITANCE (11F)
I
:::::::
; ; ioo""""
g
I
'--
60Hz, Ip
(+dv/dl) \
-
200
W
!C
CI
0.06
-
!l:::I
j
0.04
0.02
400
I
w
60Hz,IN
(- dv/dl)
0
220VRMS, 50160Hz OPERATION
INPUT RESISTANCE (Rs) .20kO
I
5
;;...
~Z,IN/
(- dv/cIt)
o
-
/
~~.
...
w
o
~
a:
I
60Hz, Ip
(+ dv/dl)
50Hz, Ip
200
w
600
lz
220VRMS, 50160Hz OPERATION
INPUT RESISTANCE (Rs) = 101dl
300
0
O~--~----~----L-----'----~
o
0.1
EXTERNAL CAPACITANCE (I1F)
0.02
0.04
0.06
0.08
0.1
EXTERNAL CAPACITANCE (11F)
FIGURE 10C.
FIGURE10D.
FIGURE 10. RELATIVE PULSE WIDTH AND LOCATION OF ZERO CROSSING FOR 220V OPERATION FOR CA3059 AND CA3079
§:
"-
"-
rf
z
....-
rf
~~
o
FIGURE 15. ON/OFF TEMPERATURE CONTROL CIRCUIT WITH DELAYED TURN-ON
120VAC
-b
SKn
2W
10Kn
R1
NOTE:
Terminal 1 goes "High"
(Logic "1") after 2048
pulses are applied to
Terminal 10.
For 8 hour delay:
R1 = 12MQ
C 1 = 211F
FIGURE 16A. LINE-OPERATED Ie TIMER FOR LONG TIME PERIODS
5-11
CA3059, CA3079
SENSOR ILLUMINATION
COUNTER RESET
(TERMINAL 11 OF CD4040)
"CLOCK" PULSES
(TERMINAL 9 OF CA3097E)
COUNTER OUTPUT
(TERMINAL 1 OF CD4040)
TERMINAL 6 OF CA3059 AND
TERMINAL 5 OF CA3097E
TERMINAL 4 OF CA3059
AND POWER IN LOAD
FIGURE 16B. TIMING DIAGRAM FOR FIGURE 16A
T2302B
MAX LOAD. 2.5A
16
+Voo (E +6.5V)
COSIMOS CD4020A
14-STAGE BINARY
COUNTER
H
G
F
a
b
c
d
e
9
h
E
t'-___--'r ~
PROGRAMMING
INTERCONNECTIONS
B
A
FIGURE 17A. PROGRAMMABLE ULTRA-ACCURATE LINE-OPERATED TIMER.
5-12
CA3059, CA3079
TIME PERIODS (I
= 0.5333 s)
11
1281
a
h
CD4048A TERMINALS
A
B
C
D
E
F
G
H
C
NC
NC
NC
NC
NC
NC
NC
11
NC
C
NC
NC
NC
NC
NC
NC
21
C
C
NC
NC
NC
NC
NC
NC
31
NC
NC
C
NC
NC
NC
NC
NC
41
C
NC
C
NC
NC
NC
NC
NC
51
NC
C
C
NC
NC
NC
NC
NC
61
C
C
C
NC
NC
NC
NC
NC
71
NC
NC
NC
C
NC
NC
NC
NC
81
C
NC
NC
C
NC
NC
NC
NC
91
NC
C
NC
C
NC
NC
NC
NC
lOt
C
C
NC
C
NC
NC
NC
NC
111
NC
NC
C
C
NC
NC
NC
NC
121
C
NC
C
C
NC
NC
NC
NC
131
NC
C
C
C
NC
NC
NC
NC
141
C
C
C
C
NC
NC
NC
NC
151
C
C
C
C
NC
C
C
NC
1111
NC
NC
NC
NC
C
C
C
NC
112t
If)
C
NC
NC
NC
C
C
C
NC
113t
Oa:
C
C
C
C
C
C
C
C
255t
Oa:
t- W
to = Total time delay = n, 1+ n2 I + •.. nnt.
0
2. C = Connect. For example. interconnect lerminal a of the CD4020A and terminal A of the CD4048A.
3. NC = No Connection. For example. lerminal b of the CD4020A open and terminal B of the CD4048A connecled 10 +Voo bus.
AC
SUPPLY
VOLTAGE
CA3059
OUTPUT
(PIN 4 AND PIN 6)
CD4048A
OUTPUT
0>
<~
NOTES:
1.
C~
____________________~A
II
Ir------
I~
1IrvI
AC IN LOAD (R L)
FIGURE 17B. "PROGRAMMING" TABLE FOR FIGURE 17(A).
5·13
CA3059, CA3079
Operating Considerations
Power Supply Considerations for CA3059 and CA3079
The CA3059 and CA3079 are intended for operation as selfpowered circuits with the power supplied from and AC line
through a dropping resistor. The internal supply is designed
to allow for some current to be drawn by the auxiliary power
circuits. Typical power supply characteristics are given in
Figures 2(b) and 2(c).
Power Supply Considerations for CA3059
The output current available from the internal supply may not
be adequate for higher power applications. In such applications an external power supply with a higher voltage should
be used with a resulting increase in the output level. (See
Figure 4 for the peak output current characteristics.) When
an external power supply is used, Terminal 5 should be connected to Terminal 7 and the synchronizing voltage applied
to Terminal 12 as illustrated in Figure 5(a).
2. Set the value of Rp and sensor resistance (Rx) between
2kn and 100k(!
3. The ratiO of Rx to Rfl typically, should be greater than 0.33
and less than 3. If either of these ratios is not met with an
unmodified sensor over the entire anticipated temperature range, then either a series or shunt resistor must be
added to avoid undesired activation of the circuit.
If operation of the protection circuit is desired under conditions other than those specified above, then apply the data
given in Figure 12.
External Inhibit Function for the CA3059
A priority inhibit command may be applied to Terminal 1. The
presence of at least +1.2V at 1O~A will remove drive from
the thyristor. This required level is compatible with DTL or
T2L logic. A logical 1 activates the inhibit function.
DC Gate Current Mode for the CA3059
Operation of Built-In Protection fOr the CA3059
A special feature of the CA3059 is the inclusion of a protection circuit which, when connected, removes power from the
load if the sensor either shorts or opens. The protection circuit is activated by connecting Terminal 14 to Terminal 13 as
shown in the Functional Block Diagram. To assure proper
operation of the protection circuit the following conditions
should be observed:
1. Use the internal supply and limit the external load current
to 2mA with a 5kO dropping resistor.
Dimensions In parentheses are in millimeters and are derived from
the basic Inch dimensions as Indicated. Grid gradations are in mils
(10-3 Inch).
Connecting Terminals 7 and 12 disables the zero-crossing
detector and permits the flow of gate current on demand
from the differential sensing amplifier. This mode of operation is useful when comparator operation is desired or when
inductive loads are switched. Care must be exercised to
avoid overloading the internal power supply when operating
in this mode. A sensitive gate thyristor should be used with a
resistor placed between Terminal 4 and the gate in order to
limit the gate current.
The photographs and dimensions represent a chip when tt is par of
the wafer. When the wafer is cut Into chips, the cleavage angles are
57" instead of 90° with respect to the face of the chip. Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.
DtMENSIONS AND PAD LAYOUT FOR CA3059H AND CA3079H
5-14
HV-240SE
HARRIS
SEMICONDUCTOR
World-Wide
Single Chip Power Supply
April 1994
Features
Description
• Direc1 AC to DC Conversion
The HV-2405E is a single chip off line power supply that con:
verts world wide AC line voltages to a regulated DC voltage.
The output voltage is adjustable from 5V oc to 24Voc with an
output current of up to 50mA. The HV-2405E can operate
from input voltages between 15Vrms and 275Vrms as well
as input frequencies between 47Hz to 200Hz (see Table 1 in
section titled "Minimum Input Voltage vs Output Currenf' for
details).
• Wide Input Voltage Range •••••••••. 15Vrms-275Vrms
• Dual Output Voltages Available
• Output Current. .••••........•.....•.. up to 50mA
• Output Voltage .....•........• , ......... 5V to 24V
• Line and Load Regulation ....••.............. <2%
The wide input voltage range makes the HV-2405E an excellent choice for use in equipment which is required to operate
from either 240V or 120V. Unlike competitive AC-DC convertors, the HV-2405E can use the same external components
for operation from either voltage. This flexibility in input voltage, as well as frequency, enables a single design for a
world wide supply.
• UL Recognition, File # E130808
Applications
• Power Supply for Non-Isolated Applications
• Power Supply for Relay Control
• Dual Output Supply for OFF-LINE Motor Controls
The HV-2405E has a safety feature that monitors the incoming AC line for large dv/dt (Le. random noise spikes on AC
line, initial power applied at or near peak line voltage). This
inhibit function protects the HV-2405E, and subsequent circuitry, by turning off the HV-2405E during large dv/dt transients.This feature is utilized to ensure operation within the
SOA (Safe Operating Area) of the HV-2405E.
• Housekeeping Supply for Switch-Mode Power
Supplies
Ordering information
PART NUMBER
TEMPERATURE
RANGE
The HV-2405E can be configured to work directly from an
electrical outlet (see Figure 1) or imbedded in a larger system (see Figure 7). Both application circuits have components that will vary based on input voltage, output current
and output voltage. It is important to understand these values prior to beginning your design.
PACKAGE
HV3-2405E-5
OOC to +75°C
8 Lead Plastic DIP
HV3-2405E-9
-40oC to +85°C
8 Lead Plastic DIP
CAUTION: This Product Does Not Provide Isolation From The AC line. See "General Precautions". Failure to use a properly rated
fuse may cause R1 to reach dangerously High Temperature or Cause the HV-240SE to Crack or Explode.
Functional Diagram
Pinout
HV-240SE (PDIP)
TOP VIEW
I
ACRETURN 0 8 ACHIGH
PRE-REG 2
7 NC
CAP (C2)
GND 3
INHIBIT 4
SWITCHING
PRE-REGULATOR
UNEAR
POST-REGULATOR
I
:Ii. IE
~
I
DA1........ SM····DA2'" -.. -. --"Q;" --_.. _. -:
AC
;HIGH
R1
<>-F""U'\,S...EJVo.IIr--8-<:.....""'"---4~-
...t--.......---.
,,
,6
r - - - -....
: -0 VOUT
,,
I
6 VOUT
5 VSENSE
'IE
:
5
,..----0
, SENSE
,
C1
RB11 :
40--+--........
BANDGAP
REFERENCE
,,,
,
RB10:
,,
,,
,
,,
: (1,3)
AC
RETURN
AC
-2 -_•• _•.• -- -- -- -- -- .•, RETURN
(1,3)
C2
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright
© Harris Corporation 1992
5-15
File Number
2487.5
o
If)
II:
O~
o
II:
I-W
0>
c(~
o
Specifications HV-240SE
Absolute Maximum Ratings
Thermal Information
Voltage Between Pin 1 and 8, Peak ........................ ±SOOV
Voltage Between Pin 2 and 6 ........................... ISV
Input Current, Peak •••.•••••....••.....••...•••..•.... 2A
Output Current ..•••..••.•.••....••..•..•••.•.••... l00mA
Output Voltage ...................................... 34V
Thermal Resistance
9JA
Plastic DIP ................................... ISCf'CIW
Maximum Junction Temperature •••••••••••••••••••••• +15Cf'C
Storage Temperature Range .................. -65°C to +15Cf'C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only raUng and operation
01 the device at these or any other conditions above those indicated in the operaUonal sections 01 this specilicaUon Is not implied.
Electrical Specifications
Unless Otherwise Specilied: VIN =264Vms at 50Hz, Cl =0.05I1F, C2 =470IlF, C4 =l11F, VOUT =5V,
lOUT =SOmA, Source Impedance Rl =1500. Parameters are Guaranteed at the SpecifIC VIN and
Frequency Conditions, Unless Otherwise Specified. See test circuit lor Component Location.
HY-2405E-51-9
PARAMETER
CONDITIONS
Output Voltage (At Preset SV)
Output Voltage (At Preset 24V)
Line Regulation
VREF
=OVoc
VREF =19Voc
80Vrms to 264Vrms
(lOUT =SmA to SOmA)
Load Regulation
MIN
TYP
MAX
UNITS
+25°C
4.75
5.0
5.25
V
Full
4.65
S.O
S.35
Y
+2SoC
22.8
24.0
2S.2
V
Full
22.32
24.0
25.68
V
+2SoC
-
10
20
mV
Full
-
IS
40
mV
20
mV
TEMP
+2SoC
-
Full
-
Output Current
Full
50
Output Ripple (Vp-p)
Full
-
24
Short Circuit Current Limit
Full
-
70
Full
-
0.02
+2SoC
-
2
Output Voltage TC
Quiescent Current Post Regulator
11Voc to 30Voc on Pin 2
40
mV
-
rnA
-
mV
-
Test Circuit
+
I: I
r!-J ~ Fol ~
R1
1son
D
FILTER
NETWORK
AUTOMATIC
TEST
EQUIPMENT
TEST SIGNALS
SHOULD BE
FILTERED TO
PRECLUDE
TRANSIENTS
TO LESS THAN
C1
O.OsI'F
10Vl1'8
VREF
l
r
DUT
~=-ti_lC3
fC2 ~T1s0PF
470I'F
5-16
VOUT
C4
11'F
.
mA
%/'C
mA
HV-2405E
Application Information
OPERATING CONDITIONS
VIN • SOVrms TO 275Vrma
FREQUENCY" 50Hz to 60Hz
loUT. OmA to SOmA
Vour " SV + VZI
r-----II----t-JW~----.....-...;..."""'" AC HIGH
R2
·· -!:
220Kn:
AC RETURN
·· Vour
ril-...,..-......--.-,HI---I.---O
··•
··••
·
•
~--------""::"--!!---'"::------------------------- .. ---------- -.::.-----!·
R3 :
3.9Kn:
COMPONENT UST
C1 • 0.1 ~F, AC RATED
C2. 470~F,15V + Vour, ELECTROLYTIC
C3 " 20pF, CERAMIC
C4 =1 O~F, Vour + 10V, ELECTROLYTIC
C5 " 0.047~F, 10V
Z1 • Vour - 5V, 1/4W
Z2 = 5.W, 1N5231/A OR EQUIVALENT
Q1 ,,2N2222 OR EQUIVALENT
FUSE .1/4A
R1.100ll,SW
R2 " 220kll, 1W
R3 " 3.9kll, 1/4W
R4" S.6kll, 1/4W
RS " 3.3ll, 1/4W
R6 5.6kll, 1/4 W
=
FIGURE 1. OFF LINE WORLD-WIDE SUPPLY (loUT ~ 50mA)
Off line World Wide Supply (lOUT ~ SOmA)
Figure 1 shows the recommended application circuit for an
off line world wide supply. The circuit will deliver an output
voltage of 5V to 24V and an output current from 0 to 50mA.
The value of C2 can be reduced for applications requiring
less output current (see section titled "Optimizing Design" for
details). For a basic understanding of the internal operation
of the HV-2405E reference section titled "How the HV-2405E
Works".
The following is a detailed explanation of this application circuit:
Basic Operation
When the input voltage goes positive an internal switch
connects pin 8 to pin 2 allowing current to flow through R1 to
charge up C2. When the voltage on C2 reaches a
predetermined voltage the switch opens and the charging of
C2 stops. R1 limits the input current and along with C1
provides a snubber for the internal switch. A linear regulator
takes current from C2 further regulating the voltage and
limiting the ripple at pin 6. The voltage at pin 6 is equal to
VZ 1 +5V. The linear regulator also provides output current
limiting. The capacitor C4 on pin 6 is required for stability of
the output.
Input Current Umitlng Circuit
The external components in the shaded area of Figure 1 perform two functions. The first is to shut down the HV-2405E in
the presences of a large voltage transients and the second is
to provide input current limiting.
Resistors R2, R3 and capacitor C3 monitor the input voltage
and turn on 01 which shuts down the HV-2405E when the
input voltage or the dv/dt is too large. This network anticipates the voltage applied to pin 8, since R1 and C1 add
several micro seconds delay, and turns off the HV-2405E
when a predetermined input voltage is exceeded. The difference between R3/C3 and R1/C1 time constants ensures
that the HV-2405E internal switch opens before the voltage,
and thereby the input current, is allowed to rise to a dangerous level at pin 8.The input voltage at which the HV-2405E is
turned off, is dependent upon the voltage on C2. The higher
the voltage on C2 the larger the input current that the HV2405E can safely turn off. For a detailed explanation of why
the voltage on C2 determines the maximum input current
that the HV-2405E can safely turn off, reference "Start-up" in
section titled "How the HV-2405E Works".
Input current limiting is provided when the voltage at the
base of 01 forward biases the base to emitter junction, turning off the internal switch. The voltage required at the base
to turn on 01 increases as the voltage on C2 increases the
emitter voltage. When the voltage on C2 is >10V, the emitter
voltage is held constant by Z2 and the maximum input current is set by resistors R2, R3, R4 and R5 (see section titled
"Design Equations" for more details).
Operation
The circuit in Figure 1 ensures operation within the SOA of
the HV-2405E by limiting the input current to <500mA when
the voltage on C2 equals zero and <2A when the voltage on
5-17
HV-2405E
Application Information
(Continued)
C2 is greater than 10V. The circuits operation is illustrated in
Figure 2 and Figure 3. In Figure 2 the initial current pulse is
approximately 400mA when VC2 = OV and gradually
increases to approximately 1.SA when C2 = 10V. Also notice
that after the 17th line cycle the input current is approximately 1.4A. At this point C2 is fully charged. The input current required to maintain the voltage on C2 is less than the
current to charge it and the circuit has reached steady state
operation. Since the steady state current is less than the
input current limit. the circuit in the shaded area is off and no
longer has any effect.
Design Equations for Input Current Limiting
Initial Start-Up
Assume: VC2 = OV. Rl = 1000. R2 = 220kO. R3 = 3.9kO,
R4 = 5.6kO, R5 = 3.3kO, R6 = 5.6kO, VBE = 0.54V, ITRIG =
60llA, VPin 8 - VPin 2 = 3.5V at low inputs currents. VIN1 =
Voltage on AC high when input current limit circuit is invoked
(VC2 OV)
=
IIN(min)=
VIN' =
OFFUNE WORLD-SIDE SUPPLY
lOUT = 50mA
VIN' - VPin 8 - VPin 2
R1
R2 + R3
R3
R4 (R5 + R6)
(V BE + R4 + R5 + R6 x ITRIG )
VIN' = S7.41 (0.54 + 3.437kQ x 601lA) = 42.B4V
IIN(min) -
42.84-3.S
100
- 393mA
(EO 1)
(Ea. 2)
(Ea. 3)
(Ea. 4)
Equation 1 through Equation 4, for the given assumptions,
predict that the initial input current will be limited to 393mA.
The following equations can be used to predict the maximum
input current during start-up.
Assume: VC2 > 10V, Rl = 100n. R2 = 220kn. R3 = 3.9kn.
R4 = 5.6kO, R5 = 5.6kO, R6 = 3.3kO, VSE = 0.54V, ITRIG =
60llA, Vz = 5.1V, VPin 8 - VPin 2 = 6V at high inputs currents,
V Pin 2 - V Pin 6, V 1N2 = Voltage on AC high when input current
circuit is invoked (VC2 > 10V).
IIN(max) =
OFFLINE WORLD-WIDE SUPPLY
(500VIDIV)
Ii H~J~t\~Tn~~I\~E(A~J"'\M~Hf ~\~~
r~~·vlij.vV~tVr~ {lftVV ~:v(V~~hW~Ji
lI~lLi
,,,.,,'",..,
[, j! j 1· J I' J j
i " " " II I;
(1AIDIV) " ... W,or ,;, n _
. .~
Ip.O.8A :,H.
. . . ~: . . ; . . . . .•. . . . . . !
-
VC2"
(10VIDIV)
,
,.,........!'""
(Ea. 5)
J
R2+R3 [ R 4 R S
R4
VIN2 = ~ (Vse + R4 + RS x ITRIG + R4 + RS V12 (Ea. 6)
FIGURE 2. START UP OPERATION
Under short circuit operation the maximum voltage on pin 2
is less than 10V and the input current limiting circuit is
invoked. Figure 3 shows that under output short circuit conditions. the input current is limited to about SOOmA. The
effects on the output current when the input current limiting
circuit is invoked is illustrated in Figure 6.
VIN=264Vrms
VIN2 • Vour' (VPin 8 - VPin 2) - (VPin 2 - VPin .)
R1
:::!
~~
'i
:1
VOUT " I
(5VIDIV) i... ..................................................................................I!.M!L(§.Qm~!.Y.lj
FIGURE 3. SHORT CIRCUIT OPERATION
VIN2 = 57.41 [0.54+ (2.076kQx 601lA) + (0.6292 x S.1))
222 - VOUT -6 -6
= 2.0SA at VOUT = 5V
IIN(max) =
100
IIN(max) =
222 - VOUT -6-6
100
= 1.B6A at VOUT = 24V
(Ea. 7)
(Ea. B)
(Ea. 9)
Equation 5 through Equation 9 predict the maximum input
current will be limited to less than 2.05A. In practice at 5V
operation the current is less than predicted due to the low
bias current through Z2.
Setting The Output Voltage
The circuit shown in Figure 1 provides a regulated 5V to 24V
DC and is set by adjusting the value of Zl. The output voltage of the HV-2405E (pin 6) is set by feedback to the sense
pin (pin 5). The output will rise to the voltage necessary to
keep the sense pin at 5V. The output voltage is equal to the
Zener voltage (VZ1 ) plus the 5V on the sense pin. For a 5V
output, pin 5 and pin 6 would be shorted together. The output voltage has the accuracy and tolerance of both the Zener
diode and the band-gap of the HV-2405E (see Figure 16).
The maximum output voltage is limited by ZS2 to - 34V DC '
ZB2 protects the output by ensuring that an overvoltage condition does not exist. Note: the output voltage can also be set
by placing a resistor (1/4W) between pin 5 and pin 6. If a
resistor is placed between pin 5 and pin 6 an additional lV
per 1m (±10%) is added to the 5V output.
5-18
HV-240SE
Application Information
(Continued)
Optimizing Design (World-Wide Supply)
NOTE: Under short circuit conditions the Po in R1
decreases to 1.2W Due to fold back current limiting (lOUT
20mA, Reference Figure 6).
=
Selecting the Storage Capacitor C2
For applications requiring less than SOmA or the full input
voltage range, the value of C2 can be reduced for a more
cost effective solution. The minimum C2 capacitor value is
determined by the intersection between the maximum input
voltage and the output current curve in Figure 4. (Note, for
SOHz operation see Figure 19 in section titled "Typical Performance Curves".) Advantages of making C2 as small as
possible are:
OFFlINE WORLD-WIDE SUPPLY (R1 • 1000)
6
5
~
~
iii
• Reduced total size and cost of the circuit.
I
~
~
!:l
g
~
'""-i!!:
120
90
I
60
I
/
I
I
L
I
I
I.
V
I
0
0
75100
~
"-
~
1
~
0
0
~
10
~
V
120Vrm.-
20
30
40
LOAD CURRENT (mA)
50
FIGURE 5. POWER DISSIPATION IN R1 vs LOAD CURRENT
Operation Information
Effects of Temperature on Output Current:
Figure 6 shows the effects of temperature on the output
current for the circuit shown in Figure 1. Figure 6 illustrates
operation with the output configured for SV. Temperature
effects on the output current for VOUT
24V operation is
similar. The foldback current limiting is the result of reduced
voltage on C2. The circuit delivers SOmA output current
across the specified temperature range of -40°C to +8SoC
for all output voltages between SV and 24V. The effect of
decreasing the value of C2 (470I1F) reduces the maximum
output current (Le. moves curve to the left). For all C2 values
selected from Figure 4 (assuming tolerance and temperature
coefficient are taken into account) the circuit meets the
expected output current across the above mentioned
temperature range.
=
J
30
./V/V
is
a: 2
w
Consideration should be given to the tolerance and temperature coefficient of the C2 value selected. (Note; momentary
peak output current demands should be considered in the
sizing of C2. Increasing the output capacitor C4 is another
way to supply momentary peak current demands.)
OFFUNE WORLD-WIDE SUPPLY
275
--3SmA/I
240
--10mA
210
slomA
180
w 150
2SmA
./
./
3
III
• Reduced start up time.
.-
240vrm~
~ 4
220
330
470
C2{jtF)
FIGURE 4. MINIMUM C2 VALUE vs INPUT VOLTAGE
The following example illustrates the method for determining
the minimum C2 value required:
EXAMPLE
Requirements: VOUT
120Vrms, 60Hz.
= SV to 24V,
lOUT
OFFUNE WORLD-WIDE SUPPLY
= 3SmA, V1N(max) =
~ 4
CI
Circuit efficiency is limited by the power dissipation in R1.
The power dissipation for 240Vrms and 120Vrms is shown in
Figure S.
g
For input voltages other than 240Vrms or 120Vrms equation
10 can be used to determine the power dissipation in R1.
(Ea. 10)
Pd=2.B "Rl Vrms (IOUT)3
=
=
= 240Vrms,
+ssoc .......
.,. \
w
Determining the Power Dissipation In R1
Example: R,
100n, Input Voltage
SOmA, Po 4.8W
,
5
For the given conditions, the minimum C2 value (from Figure
4) is determined to be 22OIlF.
lOUT
=
~
3
./
~
'"
"~
2
/'
'"0
V
~
1
F
I
0
10
r
20
1\
+2SoC -
.J..o-"""
,
V
_40°C ~
.,. --I
1\
rl
~
~
I'
3D
40 50 60 70 so
OUTPUT CURRENT (mA)
9D
FIGURE 6. OUTPUT CURRENT vs TEMPERATURE
S-19
100
o
0"
O~
0"
.,.W
0>
cC~
o
HV-2405E
Application Information
(Continued)
Minimum Input Voltage vs lOUT
Table 1 shows the minimum input voltage range as a
function of output current. Notice that the HV-240SE can
deliver SV at 10mA from a source voltage as little as 1SVrms
and requires a minimum of SOVrms to deliver 24V at SOmA.
TABLE 1. MINIMUM INPUT VOLTAGE vs OUTPUT CURRENT
Recommended value = 470l'F electrolytic (±20%), unless
otherwise specified.
C3 Feed Forward Capacitor
C3 is part of the input Current limiting circuitry shown in
Figure 1. C3 detects large voltage transients on the AC line
and turns off the HV-240SE by turning 01 on.
C3 = 20pF (20%), breakdown voltage >SOOV.
10mA
loUT
2SmA
3SmA
SOmA
SV
ISVrms
21Vrms
2SVrms
30Vrms
24V
31Vrms
38Vrms
41Vrms
SOVrms
VOUT
C4 Output Filter Capacitor
C4 is required to maintain the stability of the output stage.
Larger values may help in supplying short momentary
current peaks to the load and improve output ripple during
start-up.
Component List (World Wide Supply 10V. This results in limiting the maximum input current
to less than 2A.
(EO. 10)
Pd=2.8 "Rl Vrms (loUT)3
Wirewound resistors are recommended due to their superior
temperature characteristics.
R1
= lOOn (±10%)
Z2
=S.1 V, 1N5231 A or equivalent
Q1 Input Current Limiting Transistor
01 shuts down the HV-2405E when the input voltage or dV/dt
is too large.
R2, R3, R4, RS and R6 Resistors
R2, R3, R4, RS and R6 set the bias level for 01 that
establishes the minimum and maximum input current limit
during start-up.
Resistor values (±S%):
R2 = 220k!l,1W
R3 = 3.9k!l, 1/4W
R4 = S.Sk!l,1/4W
Z2 Clamp Diode
V CEO
01
=40V min.
=2N2222 or equivalent
Imbedded Supply (lOUT ~OmA)
RS = 3.3k!l, 1/4W
RS = S.Sk!l, 1/4W
C1 Snubber Capacitor
C1 and R1 form a low pass filter that limits the voltage rate
of rise across SA 1 (the main current carrying SCR of the
HV-2405E) and therefore its power dissipation.
C1
=0.11'F (±10%) AC rated, metallized polyester.
C2 Pre-Regulator Capacitor
C2 is charged once each line cycle. The post regulator
section of the HV-2405E is powered by C2 for most of the
line cycle. If the application requires a smaller input voltage,
the value of C2 can be reduced from that shown in Figure 1
(see section on ·Optimizing Design" for details). Note:
capacitors with high ESR may not store enough charge to
maintain full load current. The voltage rating of C2 should be
about 10V greater than the selected Your.
5-20
COMPONENT UST
FUSE .1/4A
C2. 330fLF, 15V + VOUT, ELECTROLYTIC
R1 • 1500, 3W
C3 = 150pF, CERAMIC
R2.2.70,1/4W
C4 = 10..F, VOUT+ 10V, ELECTROLYTIC
C1 • 0.1fLF, AC RATED Z1 =VOUT -SV, 1/4W
FIGURE 7. IMBEDDED SUPPLY loUT';; 30mA
HV-2405E
Application Information
(Continued)
For applications requiring 30mA or less and not directly off
line (Le. filter network preceding supply), the external transistor and associated resistors in Figure 1 can be replaced
with a single 1/4W resistor R2 and capacitor C3 (Figure 7) if:
(1) The filter network reduces the input dvldt to less than
10V/I's (ensures sufficient pin 2 voltage at turn off), (2)
Source resistor Rl equals 150Q (limits the maximum input
current) and (3) Inhibit Capacitor C3 equals 150pF (turns off
the HV-2405E during large voltage tranSients).
For applications where EMI (conductive interference) is a
design requirement, the circuit shown in Figure 8 is the recommended application circuit. This circuit delivers an output
voltage of 5V to 24V with an output current from 0 to 30mA
and passes VDE 0871 class "S" test requirements for conductive interference with a resistive load.
Operation
The operation of the imbedded supply is illustrated in Figure 9
and Figure 10. Figure 9 shows operation wijh a 30mA load
and Figure 10 with the output short circuited. Notice that In
both cases, the inhibit function of the HV-2405E prevents the
circuit from turning on when the input vottage was applied
near the peak line voltage. Also notice the initial current pulse
(Figure 9) is approximately 1.6A and decreased to lA within
40ms. This decrease in the input current results when the
charging current required to maintain the vottage on C2
decreased. The effect of the series resistor (R2) is illustrated
by the small voltage spike on the Vpin 2 trace. This vottage
spike increases the voltage on pin 2 to the 10V trip point
sooner in the cycle, thereby limiting the input current.
+
ZI
~:~~~~PJV~MMt1~
i'
INPUT CURRENT
:
!
~
:
:
:
;uJ
..•
(IAIDIV):
10~F
.:!
.
".
.
...
loUT
ACRETURN
=30mA, VOUT =5V
COMPONENT UST
=
:
(SV~~~
t
,.."'"'"..."..._"'"".....".............."'" . .~.::· . :~.:."'" ...I'.M§.,{~.~m~lv.iJ
C3
150pF
FUSE = 1/4A
Rl.150Q,3W
R2 = 2.7Q, 1/4W
Cl 0.1 ~F, AC RATED
C2" 330~F,15V + VOUT,
ELECTROLYTIC
:
:~~~
C4
FILTER
NETWORK
.
FIGURE 9. START UP OPERATION
C3 = IS0pF, CERAMIC
C4 .10~F, VOUT + 10V,
ELECTROLYTIC
ZI " VOUT -SV, 1/4W
L1 " 2.2mh, ~" 2000
CO" 0.33"F, AC RATED
FIGURE 8. IMBEDDED SUPPLY WITH EMI FILTER (loUT ~ 30mA)
Basic Operation
When power is initially applied the filter network reduces the
magnitude of any transient noise spikes that might result in
operation outside the SOA of the HV-2405E (see Start-up in
section titled "How the HV-2405E Works" for and explanation
of the SOA). When the voltage on pin 8 goes positive an
internal switch connects pin 8 to pin 2 and C2 starts to
charge through Rl and R2. When the voltage on pin 2
reaches a predetermined voltage the switch opens and the
charging of C2 stops. Rl limits the input current and along
with Cl provides a snubber for the internal switch. R2 also
has the effect of limiting the input current by increasing the
voltage on pin 2 sooner in the cycle. A linear regulator takes
current from C2 and provides a DC voltage at pin 6. The voltage at pin 6 is equal to VZ1 + 5V. The inhibit capacitor (C3)
provides protection from large input voltage transients by
turning off the HV-2405E and the output capacitor C4 provides stabilization of the output stage.
5-21
OUTPUT SHORT CIRCUITED
FIGURE 10. SHORT CIRCUIT OPERATION
HV-240SE
Application Information
(Continued)
Setting The Output Voltage
Determining the Power Dissipation In R1
The circuits shown in Figure 7 and Figure 8 provide a regulated 5V to 24Voc output voltage that is set by adjusting the
value of Z1. The output voltage of the HV-2405E (pin 6) is
set by feedback to the sense pin (pin 5). The output will rise
to the voltage necessary to keep the sense pin at 5V. The
output voltage is equal to the Zener voltage (Vz 1) plus the 5V
on the sense pin. For a 5V output, pin 5 and pin 6 would be
shorted together. The output voltage has the accuracy and
tolerance of both the Zener diode and the band-gap of the
HV-2405E (see Figure 16). The maximum output voltage is
limited by ZS2to = 34V oc. ZS2 protects the output byensuring that an overvoltage condition does not exist. Note: the
output voltage can also be set by placing a resistor (1/4W)
between pin 5 and pin 6. If a resistor is placed between pin 5
and pin 6 an additional1V per ko (±100/0) is added to the 5V
output.
Circuit efficiency is limited by the power dissipation in R1.
The power dissipation for 240Vrms and 120Vrms is shown in
Figure 11.
For input voltages other than 240Vrms or 120Vrms Equation
10 can be used to determine the power dissipation in R1.
Pd=2.8 "R1 Vrms (IOUT)3
IMBEDDED SUPPLY (R1 ,,'500)
~
z
~
240V,/
Ilj
2
III
IS
a:
w
Optimizing Design (Imbedded Supply)
4
3
0
0
Selecting the storage capacitor C2
~
/
1
~
II.
For applications requiring less than 30mA, the value of C2
can be reduced for a more cost effective solution. The minimum C2 capacitor value vs. output current is presented in
Table 2. Advantages of making C2 as small as possible are:
(Ea. 10)
~~
120Vrms
30
10
20
LOAO CURRENT (mAl
FIGURE 11. POWER DISSIPATION IN R1 vs LOAD CURRENT
0
Operation information
Effects of Temperature on Output Current
• Reduced total size and cost of the circuit.
• Reduced start up time.
Consideration should be given to the tolerance and temperature coefficient of the C2 value selected. (Note: momentary
peak output current demands should be considered in the
sizing of C2. Increasing the output capacitor C4 is another
way to supply momentary peak current demands.)
TABLE 2. IMBEDDED SUPPLY
R1 -1500
VIN
264Vrms
R2=2.70
FREQ.
C2
50Hz
330(.tF
220(.tF
100(.tF
50(.tF
264Vrms
132Vrms
132Vrms
60Hz
50Hz
60Hz
330(.tF
220(.tF
100(.tF
50(.tF
330(.tF
220(.tF
100(.tF
5O(.tF
330(.tF
220(.tF
100(.tF
50(.tF
lOUT
30mA
24mA
14mA
Figure 12 and Figure 13 show the effects of temperature on
the output current for the imbedded supply (R2 = 2.70). Figure 12 illustrates VOUT = 5V operation and Figure 13 iIIustrates VOUT = 24V operation. The imbedded supply (R2
2.70) delivers 30mA output current across the specified temperature range of -40°C to +850 C for all output voltages
between 5V and 24V. The effect of decreasing the value of
C2 (330(.tF) reduces the maximum output current (i.e. moves
curve to the left). For all C2 values selected trom Table 2
(assuming tolerance and temperature coefficient are taken
into account) the circuit meets the expected output current
across the above mentioned temperature range.
IMBEDDED SUPPLY
=
6
SmA
30mA
5
27mA
16mA
9mA
30mA
w 4
~
~
+85OC, __
;.J
§! 3
I
l-
+2s0 C
::)
S2
30mA
16mA
1
0
,
~
~
'"
7
T
j
J~oc
0
SmA
30mA
30mA
16mA
9mA
~
~~
I
80
20
30
40
50
60
70
OUTPUT CURRENT (mA)
FIGURE 12. OUTPUT CURRENTvs TEMPERATURE (R1= 1500,
R2 = 2.70, C2 = 330(.tF)
5-22
0
10
HV-240SE
Application Information
(Continued)
IMBEDDED SUPPLY
;,,:o~o
25
~
w 20
~
g
...:>>
15
+SSoC
~
~ 10
:>
0
.... ~
o
o
10
20
30
40
50
~
60
C3 Inhibit Capacitor
C3 keeps the HV-2405E from turning on during large input
voltage transients.
C3 = 150pF (10%)
C4 Output Filter Capacitor
V
)
5
330IlF electrolytic (±20%),unless
Recommended value
otherwise specified.
30
C4 is required to maintain the stability of the output stage.
Larger values may help in supplying short momentary
current peaks to the load and improves output ripple during
start-up.
V
70
80
90
100
C4 = 10llF (±20%)
OUTPUT CURRENT (mAl
FIGURE13. OUTPUT CURRENT vs TEMPERATURE (R1 =1500,
R2 = 2.70, C2 = 33011F)
Z1 Output Voltage Adjust
Component List (Imbedded Supply ::;30mA)
Fuse
Z1 is used to set the output voltage above the 5V reference
on pin 5 (see section titled ·Setting The Output Voltage" for
more details).
Opens the connection to the power line should the system fail.
Z1 = VOUT - 5V,1/4W
Recommended value: 1/4AG
Note, the wattage rating is different when configured as a
dual supply (see dual supply section for on how to determine
wattage).
R1 Source Resistor
R1 limits the input current into the HV-2405E. Needs to be
large enough to limit inrush current when C2 is discharged
fully. The maximum inrush current needs to be limited to less
than 2A (Vpeak I R1 < 2A). The equation for power dissipation in R1 is:
Pd =2.8 ...J R1 Vrms (IOUT)3
Wirewound resistors are recommended due to their superior
temperature characteristics.
R1 = 1500 (±10%)
!/)
C~
An ideal application, taking advantage of the low voltage
operation, would be thermostat controls were 28Vrms is supplied via a transformer. In this application the HV-2405E
could deliver a regulated 5V at 40mA with a power dissipation in R1 (R1= 20n) equal to 530mw. The current limiting
components, in Figure 1, are not required at this low input
voltage level. See Figure 23 and Figure 24 for output vs temperature.
AC
HIGH
R2 Series Resistor
R2 limits the input current by boosting the voltage on pin 2
sooner in the cycle.
R2
00::
Low Input Voltage Supply (lOUT
c(ts
o
HV-240SE
Application Information
(Continued)
r--_ _-II-_ _~~INI,__-...~F"U.:;;SE~ AC HIGH
COMPONENT UST
~OKn
FUSE .1/2A
R1 .. 100n, 5W
R2 .. 220kn, 1W
R3 .. 3.9kn, 1W
R4 .. S.6kn, 1/4W
RS .. 3.30, 1/4W
R6 • 5.6kn, 1/4 W
C1 • O.1I'F, AC RATED
C2 .. 470I'F, 1SV + VOUT, ELECTROLYTIC
C3 • 20pF, CERAMiC
C4 -10I'F, VOUT+ 10V, ELECTROLYTIC
CS = O.047I'F, 10V
21 .. VOUT - SV, 1/4W
Z2. S.1V, 1NS231/A OR EQUIVALENT
Q1 • 2N2222 OR EQUIVALENT
-!-
1A1f-t_:_-_--I-----o
VOUT- SV + VZ1
-!'------+----0
R3
3.9Kn
AC RETURN
AC RETURN
VOUT- SV
-!-
AC RETURN
FIGURE 15. DUAL SUPPLY
Dual Supply (lOUT
S~r-;--+--r-4--+--r-4--+--r-;--+--r-,
w
./
7-
10mi_
1:25
./
~
I- \
I-
~ ~t:jt:l=~~::t==t=1~t==t=1r=r==r~
SOmA
~
~ 22r-;--+--r-;--+--r-;--+--r-;--+--r-,
I
\
25mA
~
i
1/
!: 60
30
o
21
r-4--+-t--+-+-+-1f-+--t--t--t-+--t
__L-~~__L-~~__L-~~__L-~
-40 -30 ·20 ·10 0 10 20 30 40 50 60 70 80 110
TEMPERATURE (OCI
20L-~~
o
75100
220
470
330
e2(1'F)
FIGURE 19. MINIMUM C2 VALUE vs INPUT VOLTAGE 50Hz
FIGURE 20. OUTPUT RIPPLE VOLTAGE vs TEMPERATURE
0.65
24
0.60
22
1:>
1 1
20
18
~
16
~ 14
w
......
12
if 10
8
1/
4
8
./
~
12
r--
~ 0.45
I---
V
20
24 28 32
loUT (mAl
40
36
44
48
~
FIGURE 21. OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT
o
/"'"
I~
~~~
~ .............. ~
0.25 / ' ~
0.15
~
1/ ~ ~
YOUT=24Y
YOUT,d5Y
/
0.30
0.20
16
_
~ 0.40
... 0.35
5
."..
'-'
0.50
......
."..'
w
..J
k'"
RIPPLE
S
./
". ......
0.55
5
../ : / V
~ V"
~
YOUTs5Y
'"
10
15
20
25
30
lOUT (mAl
35
40
45
50
FIGURE 22. CHIP POWER DISSIPATION vs OUTPUT CURRENT
30
6
~
5
~
\
,
+8r"
o
20
30
40
+250e
'.
IJ -
1\\
........
.40oe
e \
I+75O\
" +Sooe
~'
1
I
oOe
+250C
ooe - - .
-I
r50r~
6
l
\ \
-
+sooe
+750e
I
1 1
I
°ft
•25
o
50 60 70 80 90 100 110 120 130
OUTPUT CURRENT (mAl
20
30
40
50
60
70
I
i'+250e
·r
80
90 100 110 120 130
FIGURE 23. OUTPUT CURRENT LIMIT (5VOUT) 50Hz
FIGURE 24. OUTPUT CURRENT LIMIT (24VoUT) 50Hz
50mA is the Maximum Recommended Output Current
50mA is the Maximum Recommended Output Current
5·28
INTELLIGENT 6
POWERICs
FULL BRIDGES
PAGE
FULL BRIDGE SELECTION GUIDE .......................................................... .
6-2
FULL BRIDGE DATA SHEETS
CA3275
Dual Full Bridge Driver .................................•.••..............
6-3
HIP4010
Power Full Bridge Driver for Low Voltage Motor Drive with Direction and Brake Control ..... .
6-7
HIP4011
Three Phase Brushless DC Motor Controller ....•............•..•.............
6-11
HIP4080
80V/2.5A Peak, High Frequency Full Bridge FET Driver.....•. " ................ .
6-14
HIP4080A
8OV/2.5A Peak, High Frequency Full Bridge FET Driver......................... .
6-28
HIP4081
80V/2.5A Peak, High Frequency Full Bridge FET Driver....... " ...... " ........ .
6-41
HIP4081A
8OV/2.5A Peak, High Frequency Full Bridge FET Driver.......•..... , . " ...•.....
6-54
HIP4082
8OV/1.25A Peak, Current Full Bridge FET Driver .......•.......................
6-67
W
g
a:CD
oJ
oJ
!:)
11..
6-1
Full Bridges Selection Guide
PART
NUMBER
PEAK
OUTPUT
CURRENT
DESCRIPTION
NO LOAD
EACH DRIVE
SUPPLY
VOLTAGE
BIAS/BUS
MAXIMUM
SUPPLY
CURRENT
TARGETED
APPLICATIONS
CA327S
Dual Full Bridge Driver
1SOmA
8V to l6V
20mA
Instrumentation
HIP4Ol0
Low Voltage Motor Drive Power Full
Bridge Driver
O.S5A
3V to 7V
SjIA (Typ)
3V - SV Motors
HIP40ll
3 Phase Motor Controller
5A
10.4V to l3.2V
lSmA
Hall Effect Brushless
Motors
HIP4OSO
Full Bridge FET Driver With
Comparator, High Performance
2.5A
Bias
8V to l6V
l8mA
Class D Amplifiers,
Voice Coil, Motor Control
l8.5mA
Class D Amplifiers, Voice
Coil, Motor Control
Bus
W to SOV
HIP4OSOA
Full Bridge FET Driver UN,
Comparator
2.5A
Bias
9.SV to l6V
Bus
lV to SOV
HIP40Sl
Full Bridge FET Driver, High
Performance
2.5A
Bias
6V to l6V
l6mA
DC-DC Converters,
Motor Control, UPS
l6.SmA
DC-DC Converters,
Motor Control, UPS
6.5mA
UPS, Motor Control
Bus
lVt080V
HIP4OS1A
Full Bridge FET Driver With UN,
High Performance
2.5A
Bias
9.5Vto l6V
Bus
W to 80V
HIP4OS2
Full Bridge FET Driver With UN,
20kHZ-200kHz
1.25A
Bias
9.5V to l6V
Bus
Wto 80V
6-2
CA3275
Dual Full Bridge Driver
April 1994
Features
Description
• Two Full Bridge Drivers
The CA3275 Dual Full Bridge Driver is intended for generalpurpose applications requiring Dual Full Bridge drive or
switching, including direction and pulse-width modulation for
position control. While all features of the IC may not be utilized or required, they would normally be used in instrumentation systems with quadrature coils, such as air-core
gauges, where the coils would be driven at frequencies ranging from 200Hz to 400Hz. The coils are wrapped at 900
angles for independent direction control. Coils wound in this
physical configuration are controlled by pulse width modulation, where each coil drive is a function of the sine or cosine
versus degrees of movement. The direction control is used
to change the direction of the current in the H-Driver coil.
• ± 1S0mA Maximum Current
• Logic Controlled Switching
• Direction Control
• PWM lOUT Control
• 18V Over-Voltage Protection
• 300mA Short-Circuit Protection
• Nomlnal8V to 16V Operation
• Internal Voltage Regulation With Bandgap Reference
Applications
• Dual Full Bridge Driver For Air Core Gauge Instrumentation
• JlP Controlled Sensor Data Displays
The switch rate capability of the IC is typically 30kHz regardless of the inductive load. Over-current limiting is used to
limH short circuit current. Over-voltage protection (in the
range of 18V to 24V) causes the device to shut down the
output current drive. Thermal shutdown limits power dissipation on the chip. The CA3275 is supplied in a 14 lead dualin-line plastic package.
• Speedometer Displays
• Tachometer Displays
w
Ordering Information
• Stepper Motors
PACKAGE
TEMPERATURE
• Slave Position Indicators
-400C to +850C
14 Lead Plastic 01 P
g
a:m
...J
...J
Ii!
Pinout
Block Diagram
CA3275 (PDIP)
TOPVI'2N
•
LA
SENSOR &
CONVERTER
AID, VIF, ETC
MICROPROCESSOR
PHASE, DIRECTION
& PWM CONTROL
CA3275
DUAL·H
DRIVER
LB
CAUTION: These devices are sens~ive 10 electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6-3
SIN
B
.0
cos
File Number
2159.3
Specifications CA3275
Absolute Maximum Ratings
Thermal Information
Operating Vee ••••.•••••••..•••••••••••••••••.•••••• 16V
Transient Vce, 30 Seconds Maximum .••••••••••••••••••• 24V
Peak Vee, 0.4 Seconds Maximum ••••••••••.•••••••••.•• 40V
Maximum Continuous Output Current, .••..•.•••••.•••.•.±l00rnA
Each Drive
Maximum PWM Output Switching Current, •••.••.•.•••.•. ±l50rnA
Each Drive
Thermal Resistance
9JA
PDIP Package. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 10ff'CIW
Power Dissipation, Po
Up to +70oC •••••••.••••••••••••.••••••••••••••• 800mW
Above +70oC .•••••••••••••••••• Derate Unearly at 10mWf'C
Ambient Temperature Range
Operating .•••••••••••••••..••••••••••.••• -40"C to +85°C
Storage .••.•••••••.••.••..••••.•••••.•• -55°C to +150°C
Lead Temperature (During Soldering) •••••••••••••••••• +265°C
At distance 1/16± 1132' (1.59 ± 0.79mm) from case for lOs max
CAUTION: Stresses above those listed in "Absolute Maximum RaYngs" may cause permanent damage to the dsvice. This Is a strsss only mring and opemtlon
of the device at these or any other conditions above those indicated in the opemtionsl sections of this specification Is not implied.
Electrical Specifications TA = -400 C to +B5°C, vee = 16V Unless Otherwise Specified
SYMeOL
MIN
TYP
MAX
UNrrs
Oparating Supply Voltage Range
Vee
B
-
16
V
Supply Current (Note 1)
Ice
-
8
20
rnA
Logic Input, Low Voltage
VIL
-
V
VIH
3.5
-
0.8
Logic Input, High Voltage
V
IlL
-10
IIA
IIH
-
-
10
jIA
Maximum Source Saturated Voltage
VSAT - High
-
1.2
1.75
V
Maximum Sink Saturated Voltage
VSAT- Low
0.5
V
Diff - VSAT
-
0.25
Differential VSAT Voltage, Both Outputs Saturated
10
100
mV
SYMeOL
MIN
TYP
MAX
UNrrS
-
-
2
JlS
2.2
JlS
-
1
JlS
0.4
JlS
-
PARAMETERS
INPUT LEVELS
=OV
Logic Input, High Current, VIH =5V
OUTPUT: RLA =RLB =13BQ
Logic Input, Low Current, VIL
Switching Specifications
PARAMETERS
SOURCE CURRENT (See Figure 3)
Turn-Off Delay
TSC'()FF
Fall Time
TSC.f
Turn-On Time
TSC'()N
Rise Time
T5C-II
-
TSK.()fF
-
SINK CURRENT (See Figure 4)
Turn-Off Delay
Fall Time
TSK.f
Turn-On Time
TSK'()N
Rise Time
TSK-R
NOTE:
1. No load, PWMA
=PWMB =5V, DIR A =DIR B =OV
6-4
-
1.6
JlS
0.4
JlS
0.6
JlS
0.2
JlS
CA3275
Vee
DIRA>-+--I ;~+-------I-------+------'
PWMA>-~---~~~~
Vee
INTERNAL VOLTAGE
SUPPLY WITH
BANDGAP REFERENCE
OVERVOLTAGE PROTECTION
AND THERMAL SHUTDOWN
CIRCUITS
Vee
DIRB>-+--I
w
PWMB>--r--------~i__I
8
a:III
....I
....I
::I
II..
FIGURE 1. CA3275 DUAL FULL BRIDGE DRIVER SCHEMATIC
COILA+
GND
PWMA
PWMB
DIRB
DIRA
GND
GND
COILB+
•
LB
DIRA
_+-_-1____________....1
PWMA--~--------------------------------_J
FIGURE 2. QUADRATURE STEP·MOTOR APPUCATION SCHEMATIC
6-5
RB
CA3275
Vs
t-.....--.~D COIL
OIR
CL INCLUDES PROBE AND TEST CAPACITANCE
OUT
PWM
DIRPULSE
TEST CIRCUIT 1
TEST CONDITIONS: PWM .. OV, Vs .16V
DlR PULSE PARAMETERS:
F.lkHz, W :100"., TR .. TF .. l"., AMPL.4V
10%
TSC-ON
10%
10%
FIGURE 3. SOURCE SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
TEST CONDITIONS: Vs .. 16V
DIR • OV WHEN TESTING COIL· OUTPUT
DlR • 4V WHEN TESTING COIL + OUTPUT
Vs
t - -....--r> COIL
DIR
OUT
CL CL INCLUDES PROBE AND TEST FIXTURE CAPACITANCE
30pF
PWM
TEST CIRCUIT 2
PWMPULSE
PWM PULSE PARAMETERS:
F.lkHz, W .10OJL., TR. TF.l"., AMPL .. 4V
TSK-ON TSK.R
T SK-OFF
T SK.F
10%
FIGURE 4. SINK SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
6·6
HIP4010
ADVANCE INFORMATION
April 1994
Power Full Bridge Driver for Low Voltage Motor
Drive with Direction and Brake Control
Features
Description
• Two Independent Complementary MOS Output
Half Bridge Drivers for Operation with Low
Power Supply Voltages
In the Functional Block Diagram of the HIP4010 the four switches
and a load are arranged in an H-Configuration so that the drive
voltage from terminals OUTA and OUTB can be cross-switched to
change the direction of current flow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches 01 and 04 are conducting or in an ON state when current flows from VooA through 01, through the load, and then
through 04 to terminal Vsss; where load terminal OUTA is at a
positive potential with respect to OUTB. Switches 01 and 04 are
operated synchronously by the control logic. The control logic
switches 03 and 02 to an open or OFF state when 01 and 04 are
switched ON. To reverse the current flow in the load, the switch
states are reversed where 01 and 04 are OFF while 02 and 03
are ON. Consequently, current then flows from Voos through 03,
through the load, and through 02 to terminal VSSA ' and load terminal OUTB is then at a positive potential with respect to OUTA.
• Load Switching Capabilities ..••••••••. to O.SA
with +SV Power Supply
• Single Supply Range .•••.•.•••.•.. +3V to +7V
• Split Supply Option with a Negative Reference
for the H-Switch Power Drivers
• Low Standby Current
• CMOSITTL Compatible Input Logic
• Over-Temperature Protection
• Current-Overload Protection
• Over-Current Fault Flag Output
• Direction, Braking and PWM Control
Applications
• DC Motor Driver
• Relay Driver
• Solenoid Driver
• Stepper Motor Controller
The positive power supply terminals are VOOA and Voos and are
internally connected on the chip. Terminals ENA and ENB are
ENABLE Inputs for the Logic A and B Input Controls. The ILF output is an Over-Current Limit Fault Flag Output and indicates a fault
condition for either Output A or B or both. While VOOA Voos and
Vss are the Power Supply reference terminals for the A imd B Control Logic Inputs and ILF Output, the VssA and Vsss Power Supply
terminals are separate and independent from Vss and may be
more negative than the Vss ground reference terminal. This is
accomplished with the use of level shifting in the gate drive circuitry to the NMOS (low-side) output stages.
• Air Core Gauge Instrument Driver
..J
..J
:::I
Ordering Information
• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• +3V to +6V Battery Operated Switch Circuits
PART
NUMBER
HIP4010lB
TEMPERATURE
RANGE
.'!D°C to +8SoC
u..
PACKAGE
20 Lead Plastic sOle (W)
• Logic and Microcontroller Operated Switch
Pinout
Block Diagram
r •••••••••••• .,.,•••••••••••
HIP4010 (SOIC)
••
TOP VIEW
··•
··
VOOA
VDDB
•
i1
·
S2
ENS
Vss
VSSA
ENA
OUTA
A1
A2
ENA
ILF~---_I
Vss
CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6-7
w
g
a:
m
VSSB
File Number
3176.1
Specifications HIP4010
Absolute Maximum Ratings
Reliability Information
Supply Voltage; VOOA and Voos to Vss or VSSA or Vsss .•..•. +7V
Neg. Output Supply Voltage, (VSSA,Vsss) ••.•...•.•.•. (Note 1)
DC Logic Input Voltage (Each Input)
••.•••••••.•••.•..•••••••..•.. (Vss-o·5V) to (VOOA, Vooe -H).5V)
DC Logic Input Current (Each Input) .•...•.••.••.....•... ±20mA
ILF Fault Output Current .•.•••.•..••.•....•.••.•..••...• ±20rnA
Output Load Current, (Self Limiting, See Elec. Spec.) ••..• ±IO(LlMIT)
Thermal Resistance, OJA ••••••..••.•..••••••....•.•• 90oCIW
Power Dissipation
At +25OC (Free Air) •.••••••••••••••••••••••••.•... 1.39W
Above +250 C ••••••••••••••••• Derate Linearly at 11.1 mWf'C
Storage Temperature Range •••••••.•••••••••• -65OC to +lSOOC
Maximum Junction Temperature ••••••••••••••.•••...• +1 SOOC
Lead Temperature (Soldering lOs) •••••••.••••.••..••• +265°C
CAUTION: Strssses abO\18 those listed in 'Absolute Maximum Ratings' may cause permanent damage to the davice. This is a stress only IBting and opBlBtion
of the device at these or any other condiffons above those indicated in the operaffonal sections of this specification Is not implied.
Operating Conditions TA = +25°C, VSUPPly=VOOA = voos= +5V, VSSA = vsse = vss= OV; Unless Otherwise Specified
Input Low Voltage, Vil ••••.••.••••.•.•.••••.••••• OV to -H).8V
Input High Voltage, VIH •.••.•.••••••.•••••••.•• +2.0V to Voo
Input Resistance .••.••••••••..••...•.••••.••.•.•••• 0.5TO
Typical Operating Supply Voltage Range. • • • . • • . • . . .. +3 to +7V
Minimum Logic Supply Voltage (VOo-Vss) .•...••.•.••.•••• +2V
Typical NMOS Driver ROS(ON)' 0.5A Load •...•••••••.••••• 0.80
Typical PMOS Driver ROS(ON), 0.5A Load ..•..•••...••••.•• 1.00
Electrical Specifications
TA = +25°C; VSUPPl.y=VOOA =Vooe = +5V, VSSA = Vsss = Vss = OV; Unless Otherwise Specified
CHARACTERISTICS
Input Leakage Current
Input Voltage Range
SYMBOL
TEST CONDITIONS
ILEAK
VIN
MIN
TVP
MAX
UNITS
-
40
50
pA
0
-
5
V
-
0.8
V
-
V
Low Level Input Voltage
Vil
-
High Level Input Voltage
VIH
2
ILF Output Low, Sink Current
IOH
VOUT = O.4V
3
8
-
rnA
ILF Output High, Source Current
IOl
VOUT = 4.6V
-
-4.5
-1.5
rnA
ILF Output Low (Sink) Current;
IOH
VSUPPly=+3V, VOUT = 0.4V
1.5
3
-
rnA
ILF Output High (Source) Current);
IOl
VSUPPl.y=+3V, VOUT = 2.6V
-0.8
rnA
CIN
-
-1.6
Input Capacitance
TBE
-
pF
0.8
1.5
rnA
4.2
4.5
-
V
-
0.4
0.6
V
Idle Supply Current; No Load
OUTA, OUTB Voltage High
OUTA, OUTB Voltage Low
ISUPPlY
VOH
ISOURCE = 0.5A
VOL
ISINK = 0.5A
OUTA, OUTB Source Current limiting
10(LlMIT)
500
550
620
mA
OUTA, OUTB Sink Current Limiting
-lo(LlMIT)
500
550
620
mA
OUTA, OUTB Voltage High
VOH
2.25
2.5
-
V
OUTA, OUTB Voltage Low
VOL
-
0.5
0.65
V
-
lIS
Response Time: VEN to VOUT
Turn-on: Prop Delay
Rise Time
Turn-off: Prop Delay
Fal/Time
VSUPPly=+3V, ISOURCE = 0.3A
VSUPPly=+3V, ISINK = 0.3A
10 = 0.5A (Note 2)
~H
~
-
IpHl
IF
4
TBE
0.25
TBE
NOTES:
1. Vss Is the required common ground reference forthe logic input switching. The load currents may be switched near the common ground
reference by using a split supply for VOOA and Vooe to VSSA and Vsss. For an uneven split in the supply voltage, the Maximum Negative
Output Supply Voltage to VSSA and Vsse is limited by the Maximum VOOA and Voos to VSSA and Vsse ratings. For all operating conditions
the required positive voitages on VOOA and VDOS must be equal and common.
2. Refer to the TRUTH TABLE and the VEN to VOUT SWITCHING WAVEFORMS. Current, 10 refers to IOUTA or lOUTS as the Output Load
current. Note that ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1,
A2, ENA or 81, B2, ENB inputs. Refer to the TERMINAL INFORMATION TABLE for external pin connections to establish mode control
switching. Figure 1 shows a typical application circuit used to control a DC Motor.
6-8
Specifications HIP4010
TERMINAL INFORMATION TABLE
Positive Power Supply pins; internally connected and must be externally connect to the same Positive Supply (V+).
VOOA' VOOB
VSSA
Negative Power Supply pin; NegaHve or Ground return for Switch Driver A.
VSSB
Negative Power Supply pin; Negative or Ground return for Switch Driver B.
Vss
Common Ground pin for the Input Logic Control circuits.
A1, B1
Input pins used to control the direction of output load current totfrom OUTA and OUTS, respectively. When connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a motor.
A2,B2
Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be controlled from the same logic signal to activate Dynamic Braking of a motor.
ENA, ENB
Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective output is in a
high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and OUTS may be a separately PWM controlled as Half H-Switch Drivers.
OUTA,OUTB
Respectively, Switch Driver A and Switch Driver B Output pins.
ILF
Current limiting Fault Output Flag pin; when In a high logic state, signifies that Switch Driver A or B or both are In a
Current Limiting Fault Mode.
~--------~~----------"Y+
r' .......... __ .......................................................... .
BRAKE
I
OFF
.................................................
·:
··:!
·
CONTROL
LOGICB
ON
·!
:
i:
DIRECT;..;:IO;..:;N=--+-.....--t{
··
CONTROL
LOGIC A
··
·:
ENABLE
;---------------~~~-2----~~~-
..........
ILF
=
(LOGIC
GROUND)
Yo
FIGURE 1. TYPICAL HIP4010 MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
TRUTH TABLE
SWITCH DRIVER A
SWITCH DRIVER B
INPUTS
INPUTS
OUTPUT
OUTPUT
A1
A2
ENA
OUTA
B1
B2
ENB
OUTB
H
L
H
OH
L
L
H
OH
L
L
H
OL
H
L
H
OL
H
H
H
OL
L
H
H
OL
L
H
H
OL
H
H
H
OL
X
X
L
Z
X
X
L
Z
50%
Your
L = Low logiC level; H = High logiC level
Z =High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Don't Care
""""--9:::0%=-- 50%
SWITCHING WAVEFORMS
6-9
w
g
a:
m
..J
..J
::I
u.
HIP4010
Applications
The HIP4010 is designed to detect load current feedback
from sampling resistors of low lialue in the source connections of the output drivers to VooA, VOOB, VSSA and VSSB
(See Figure 1). When the sink or source current at OUTA or
OUTB exceeds the preset OC (Over-Current) limiting value
of 550mA typical, the current is held at the limiting value. If
the OT (Over-Temperature) Protection limit is exceeded,
temperature sensing BiMOS circuits limit the junction temperature to 150°C typical.
The circuit of Figure 1 shows a Low Voltage motor-driver
application for the HIP4010 as a Full H-Switch. The left (A)
and right (B) H-Switch's are controlled from the A and B
inputs via the A and B CONTROL LOGIC to the MOS output
transistors 01, 02, 03 and 04. The circuit is intended to
safely start, stop, and control rotational direction for a motor
requiring no more than O.SA of supply current. The stop
function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors 01 and
03 are OFF; which cuts-off supply current to OUTA and
OUTB. With the BRAKE terminal Low and ENABLE Inputs
High, either 01 and 04 or 03 and 02 will be driven into conduction by the DIRECTION Input Control terminal. The MOS
output transistor pair chosen for conduction is determined by
the logic level applied to the DIRECTION control; resulting in
either clockwise (CWl or counter-clockwise (CCW) shaft
rotation.
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through 04 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
04 to the VSSB and VssA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VODA and VOOB to Vss are the Power Supply reference terminals for the Control Logic, the lowest practical
supply voltage for proper logic control should be no less than
2.0V. The VSSA and VSSB terminals are separate and independent from Vss and may be more negative than the Vss
ground reference terminal. However, the maximum supply
level from VODA and VOOB to VSSA or VSSB must not be
greater than the Absolute Maximum Supply Voltage rating of
7V.
Terminals A1, 81, A2, B2, ENA and ENB are internally connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs EN A, ENB, A 1, 81 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level Converters for TIL or CMOS input Logic. These inputs are
designed to typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge.
Proper I.C. handling procedures should be followed.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both 02 and 04 are
driven high. Current flowing through 02 (from the motor terminal OUTA) at the moment of Dynamic Braking will continue'to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
A1
(DlR)
A2
(BRAKE)
ENA
(ENABLE)
t---OUTA
+-------~:::::t=t::~--_{
VSSA
lt~~
;s:-
B1
(DIR)
B2
(BRAKE)
(ENA:~:)
1-DJo.--~ tl~
_ - - - - - - -...
fD4
N·DR
UMIT
VSSB
FIGURE 2. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
6-10
HIP4011
Three Phase Brushless DC Motor Controller
April 1994
Features
Description
• 3A DC, SA Peak Output Current
The HIP4011 motor driver is intended for three phase Brushless motor control at continuous output currents up to 3A. It
accepts inputs from buffered Hall effect sensors and drives
three motor windings, regulating the current through an
external current sensing resistor, according to an analog
control input. Output "freewheeling" diodes are built in and
output dv/dt is limited to decrease the generated EMI.
Thermal and current limiting are used to protect the device
from locked rotor conditions. A brake control input forces all
outputs to ground simultaneously to provide dynamic
braking, and an internal voltage sensor does the same when
the supply drops below a predetermined switch point. Power
down braking energy is stored in an external capacitor.
• 16V Max. Rated Supply Voltage
• Built-In "Free-Wheeling" Diodes
• Output dv/dt Limited to Reduce EMI
• External Dynamic Brake Control Switch With
Undervoltage Sense
• Thermal and Current Limiting Protects Against
Locked Rotor Conditions
• Provides Analog Current Sense and Reference Inputs
• Decode logic with Illegal Code Rejection
Applications
Ordering Information
• Drive Spindle Motor Controller
PART
NUMBER
• 3 Phase Brushless DC Motor Controller
• Brushless DC Motor Driver for 12V Battery Powered
Appliances
TEMPERATURE
RANGE
HIP4011IS
PACKAGE
15 Pin Plastic SIP
Surface Mount
-400 C to +85°C
• Phased Driver for 12V DC Applications
• Logic Controlled Driver for Solenoids, Relays and
Lamps
Pinout
OUTPUT TRUTH TABLE
HIP4011 (SIP)
TOP VIEW
/'
PGNDPIN
(TAB) MUST BE
ELECTRICALLY
CONNECTED
0
... -$0
'"
,...
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
F== SGND .. SIGNAL GROUND
~
SPD
sv+
~ ISEN
~ OUTA
BCAP
PV+
OUTB
ISEN
~ FBRK
~ OUTC
PV+
SENC
i::::== SENB
SENA
~
§
§
§
FORCE
BRAKE
INPUT*
SENSOR
INPUTS
.. SPEED CONTROL
.. SIGNAL V+
.. ISENSE
.. OUTPUT A
• BRAKING CAPACITOR
.. POWER v+
=
OUTPUT B
=ISENSE
.. FORCED BRAKE
.. OUTPUT C
• POWER V+
.. SENSE INPUT C
.. SENSE INPUT B
.. SENSE INPUT A
FBRK
OUTPUTS
A
B
A
B
C
C
0
0
0
0
1
0
0
0
1
OFF
0
0
1
0
0
0
1
OFF
1
1
0
0
OFF
1
0
0
0
1
0
OFF
0
1
OFF OFF OFF
1
0
,
0
1
0
OFF
0
1
1
0
0
OFF
1
1
1
1
0
X
X
X
1
OFF OFF OFF
0
0
0
• Undervoltage and Force Brake logic truth table
entries are identical.
ox" =Don't Care
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procadures.
Copyright © Harris Corporation 1994
6-11
File Number
2939.3
Specifications HIP4011
Absolute Maximum Ratings
Thermal Information
Supply Voltage, sv+ or pv+ .•.•...•.•.....••.•.•• -1V to +16V
Referred to SGND or PGND (Note 1)
Output Current, Continuous ............................. 3A
Output Current, Peak (Note 2) ........................... 5A
Substrate (PGND) Current. ............................. 1A
Logic Input Current. ........................ -20rnA to +20rnA
(Clamped to SV+ and SGND)
Thermal Resistance
9JA
9JC
15 Lead SIP Power Package. . • • • • • • • • 45°CfW
3°CfW
Power Dissipation (Note 3) ............................ 25W
Junction Temperature Range, Operating ••••.••..•••••• +lSOOC
Storage Temperature Range •.•••••.••••••.••• -55°C to +150°C
Power Dissipation
Up to +125°C without heat sink. • • • • • • • • • • • • • • • • • • •• O.56W
Above +125°C without Heat Sink ••• Derate Linearly at 22mWfOC
Up to +125°C with Infinite Heat Sink. • • • • . . • • • • • • • • •• 9.33W
Above +125°C with Infinite Heat Sink .................... ..
• • • • • .. • • . • • • • • • .. • • • • • • • • .. •Derate Linearly at 333mWI"C
Lead Temperature (During Soldering)
At a Distance 1/16 inch ±1132 inch (1.59mm ±0.79mm)
from Case for lOs Max. • ......................... +265°C
NOTES:
1. PV+ and SV+ are to be tied together. as are PGND and SGND.
2. Operating above the continuous current rating causes a decrease In operating life.
3. Derate power diSSipation above case temperature of +750 C at 0.33 Watts,PC.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only mtlng and op9mtlon
of the device at these or any other conditions above those Indicated in the opemtlonal sections of this speclliestion is not impHed.
Electrical Specifications TA =+25°C and SV+ =PV+ =10.4V to 13.2V, Unless Otlherwise Specified
PARAMETERS
TEST CONDITION
MAX
UNITS
10
mA
15
rnA
-
-1.5
rnA
150
IIA
-
1.8
V
MIN
TYP
-
-
50
SUPPLY (SV+) CURRENT
No Drive
Outputs Off
With Drive
Outputs On
LOGIC INPUT CURRENT
Sensor Inputs
SENA, SENB & SENC
Brake Input
FBRK
=OV to 3V
=0.8V to 2.4V
-0.5
LOGIC INPUT THRESHOLDS
Sensor Inputs
Logic '0" Input Voltage
-
Sensor Inputs
Logic "1" Input Voltage
3
Brake Input
Logic "0" Input Voltage
Brake Input
Logic "1" Input Voltage
-
V
-
-
0.8
V
2.4
-
-
V
-
-
700
nA
3
mV
AMPLIFIER INPUT (SPD)
Bias Current
Offset Voltage
-
Input Range (Linear)
0
Input Impedance
1
-
-
35
-
System Bandwidtlh
(Note 1)
Current Limit
Rsense
=0.200
1
V
MO
kHz
5
-
155
-
·C
-
40
-
·C
-
-
2.2
V
0.44
V
-
1
mA
-
VlvS
A
THERMAL LIMIT
Threshold
Hysteresis
OUTPUT DRIVERS
=3A, VPMOS + VNMOS
On Saturation (See Note 5)
lOUT
On Saturation (See Note 5)
lOUT = 0.6A, VpMOS + VNMOS
Off Leakage
PV+ > VOUT > PGND or ISEN
Slew Rate
(See Note 2)
6-12
-
0.5
HIP4011
Electrical Specifications TA = +2SoC and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified (Continued)
PARAMETERS
TEST CONDITION
MIN
TYP
MAX
UNITS
-
1.5
V
-
3.3
V
60
%
0.4
V
5
IIA
FREEWHEEL DIODES
Forward Drop
lOUT = 1A
INTERNAL BRAKE DRIVER
Undervottage Trip Point, PV+
(See Note 3)
2.7
Hysteresis
(See Note 4)
40
On Saturation
Each NMOS, lOUT = 3A
BRAKE CAPACITOR (BCAP)
Discharge Leakage
SV+ = PV+ = 3V to 12V, BCAP = 10V
-
-
NOTES:
1. The system bandwidth Is fixed by an internal RC network around the amplifier.
2. Internal limiting of turn on and turn off drive is used to limit output dv/dt.
3. The braking action starts at the given trip point with a falling supply voltage.
4; Hysteresis causes the brake to be removed at a higher trip point with a rising supply voltage.
5. This value Includes the combined voltage drops of one upper plus one lower switch at the indicated current.
Functional Block Diagram
~GNALo-____~~~-_-_-_-_--_-_-_-~--~-_-_-_--_-_-_-_--_-_-_-_--_-_-~-~----.------.-~-~----~-----------------------_--_-_-_-_--_-_-~.B-C~A~P--,
V+
13
:10
··
BRAKE
~CAP.
:4PV+
w
8
a:
III
DECODE
LOGIC
..J
..J
:::>
WITH
u.
ILLEGAL
CODE
REJECTION
FORCEo-____+-~_i
BRAKE
SUBSTRATE
GND
SIGNAL
GND
THREE PHASE BRUSHLESS CONTROLLER
6-13
HIP40BO
80V/2.SA Peak, High Frequency
Full Bridge FET Driver
April 1994
Features
Description
• Drives N-Channel FET Full Bridge Including High Side
Chop Capability
The HIP4080 is a high frequency, medium voltage Full Bridge
N-Channel FET driver IC, available in 20 lead plastic SOIC
and DIP packages. The HIP4080 includes an input comparator, used to facilttate the "hysteresis" and PWM modes of
operation. Its HEN (high enable) lead can force current to
freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since n can swnch at
frequencies up to 1MHz, the HIP4080 is well suited for driving
Voice Coil Motors, switching amplifiers in class D high-frequency switching audio amplifiers and power supplies.
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz In Free Air at +50 oC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
HIP4080 can also drive medium voltage brush motors, and
two HIP4080s can be used to drive high performance step• Input Logic Thresholds Compatible with 5V to 15V per motors, since the short minimum 'on-time" can provide
fine micro-stepping capability.
Logic Levels
• DIS (Disable) Pin Pulls Gates Low
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.
• Very Low Power Consumption
Applications
• MedlumlLarge Voice Coil Motors
The similar HIP4081 IC allows independent control of all 4
FETs in an Full Bridge configuration.
• Full Bridge Power Supplies
• Class 0 Audio Power Amplifiers
Ordering Information
• High Performance Motor Controls
PART
NUMBER
• Noise Cancellation Systems
TEMPERATURE
RANGE
• Battery Powered Vehicles
HIP4080IP
-4O"e to +85°e
• Peripherals
HI P40801B
-40"e
to +85°e
PACKAGE
20 Lead Plastic DIP
20 Lead Plastic sOle (W)
• U.P.S.
Pinout
Application Block Diagram
BOV
HIP4080 (PDIP, SOIC)
TOP VIEW
1
L
BHS
HEN
BlO
DIS
HIP4080
LOEL~
~AHS
AHB 10
11 AHO
IN+
ALO
tiN-
AHS
AHO
I
T
GND
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6-14
File Number
3178.6
HIP4080
Functional Block Diagram
(1/2 HIP40BO)
HIGH VOLTAGE BUS :s; 80VDC
AHB
~------~-----+--~
AHO
CBS
AHS
TO VOO (PIN 16)
Des
..:.
+12VDC
BIAS
SUPPLY
CBF
Vss
ill
Typical Application (Hysteresis Mode Switching)
L
UJ
g
a:
CD
oJ
oJ
:::I
II.
6V--~r-~------~r-~
GND
GND
6-15
Specifications HIP40BO
Absolute Maximum Ratings
Thermal Information
Supply Voltage, Voo and Vcc .•.••.••...•••...••• -o.3V to 16V
Logic VO Voltages .••••.•.•••••••.••••••. -0.3V to Voo + IN-, 10H = -300~A
Voo
-0.4
Voo
-0.5
-
V
INPUT PINS: DIS
Low Level Input Voltage
High Level Input Voltage
Input Voili:tge Hysteresis
Low Level Input Current
IlL
High Level Input Current
IIH
VIN = OV, Full Operating Conditions
VIN = 5V, Full Operating Conditions
6-16
-
35
-
-130
-100
-75
-135
-65
-1
-
+1
-10
+10
2.7
-
-
-
V
mV
IIA
IIA
Specifications HIP40BO
Electrical Specifications
VDD = vee = VAHS = VSHS = 12V, vss = VAtS = VSLS = VAHS = VSHS = OV, RHDEL = RLOEL = lOOK, and
TA = +25°C, Unless Otherwise Specified (Continued)
PARAMETERS
TEST CONDITIONS
SYMBOL
TJ =-4DOC
TO+125°C
TJ =+25°C
MIN TYP MAX
MIN
-
2.7
MAX UNITS
INPUT PINS: HEN
Low Level Input Voltage
VIL
Full Operating Conditions
High Level Input Voltage
VIH
Full Operating Conditions
2.5
Input Voltage Hysteresis
-
1.0
-
-
35
0.8
V
-
-
mV
V
Low Level Input Current
IlL
VIN = DV, Full Operating Conditions
-260
-200
-150
-270
-130
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-1
-
+1
-10
+10
I!A
I!A
4.9
5.1
5.3
4.8
5.4
V
TURN-ON DELAY PINS: LDEL AND HDEL
I
LDEL, HDEL Voltage
IHDEL = ILDEL = -l00I1A
VHDEL,v
GATE DRIVER OUTPUT PINS: AlO, BlO, AHO, AND BHO
I
low level Output Voltage
VOL
lOUT = 100mA
.70
0.85
1.0
0.5
1.1
V
High level Output Voltage
Vee - VOH
lOUT = -100mA
0.8
0.95
1.1
0.5
1.2
V
Peak Pull-Up Current
10+
VOUT= OV
1.7
2.6
3.8
1.4
4.1
A
Peak Pull-down Current
10-
VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
Switching Specifications
VDD = vee = v AHS = VSHS = 12V, vss = VAtS = VSLS = v AHS = VSHS = OV, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25°C, Unless Otherwise Specified
TJ =-4DOC
TO+125°C
TJ = +25OC
PARAMETERS
SYMBOL
TEST CONDITIONS
TLPHL
Upper Turn-off Propagation Delay (IN+lIN- to AHOIBHO)
T HPHL
Lower Turn-on Propagation Delay (IN+lIN- to AlOIBLO)
TLPLH
RHDEL = RLOEL = 10K
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO)
THPLH
RHDEL = RLDEL = 10K
Rise Time
TR
Fall Time
TF
MIN
-
lower Turn-off Propagation Delay (IN+ilN- to ALOIBlO)
-
Turn-on Input Pulse Width
TPWlN.QN
RHDEL = RLOEL = 10K
50
Turn-off Input Pulse Width
TPWIN.QFF
RHDEL = RLOEL = 1OK
40
TYP MAX
40
70
SO
80
45
70
70
110
10
25
10
25
-
-
-
MIN MAX UNITS
-
50
40
90
ns
110
ns
90
ns
140
ns
35
ns
35
ns
-
ns
-
ns
95
ns
105
ns
90
ns
Disable Turn-off Propagation Delay
(DIS - lower Outputs)
TDISLOW
-
45
75
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDiSHIGH
-
55
85
Disable to lower Turn-on Propagation Delay
(DIS - ALO and BlO)
TDLPLH
-
35
70
Refresh Pulse Width (AlO and BlO)
TREF-PW
160
260
380
140
420
ns
-
335
SOO
-
550
ns
35
70
90
60
90
ns
ns
Disable to Upper Enable (DIS - AHO and BHO)
TUEN
HEN-AHO, BHO Turn-off, Propagation Delay
HEN-AHO, BHO Turn-on, Propagation Delay
THEN-PHL
RHDEL = RLOEL = 10K
THEN-PLH
RHDEL = RLDEL = 10K
-
-
TRUTH TABLE
IN+ > INX
1
0
1
0
INPUT
HEN
X
1
1
0
0
OUTPUT
DIS
ALO
AHO
BLO
BHO
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
0
6-17
110
HIP4080
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301tA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
HEN
High-side Enable input. logic level Input that when low overrides IN+lIN- (Pins 6 and 7) to put AHa and BHO
drivers (Pins 11 and 20) in low output state. When HEN is high AHa and BHO are controlled by IN+IIN- inputs.
The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001JA, pull-up to Voo will
hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+lINInputs.
3
DIS
DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other Inputs.
When DIS is taken low the outputs are controlled by the other Inputs. The pin can be driven by signal levels of
OV to 15V (no greater than Voo). An Internall001tA pull-up to Voo will hold DIS high if this pin is not driven.
4
Vss
Chip negative supply, generally will be ground.
5
OUT
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6
IN+
Non-Inverting input of control comparator. 11 IN+ is greater than IN- (Pin 7) then Ala and BHO are low level
outputs and BlO and AHa are high level outputs. 11 IN+ Is less than IN- then Ala and BHO are high level outputs and BlO and AHa are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs.
HEN (Pin 2) low level will override IN+IIN- control of AHa and BHO. When switching In four quadrant mode,
dead time in a half bridge leg is controlled by HDEl and lDEl (Pins 8 and 9).
7
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
8
HDEl
High-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage Is approximately 5.1 V.
9
lDEl
low-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. lDEL reference voltage is approximately 5.1 V.
10
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacnor to this pin. Internal charge pump supplies 301JA, out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
AHa
A High-side Output. Connect to gate of A High-side power MOSFET.
12
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13
Ala
A low-side Output. Connect to gate of A low-side power MOSFET.
14
AlS
A low-side Source connection. Connect to source of A low-side power MOSFET.
15
Vcc
Positive supply to gate drivers. Must be same potential as Voo (Pin 16). Connect to anodes of two bootstrap
diodes.
16
Voo
Positive supply to lower gate drivers. Must be same potential as Vce (Pin 15). De-couple this pin 10 Vss (Pin 4).
17
BlS
B low-side Source connection. Connect to source of B low-side power MOSFET.
18
BlO
B low-side Output. Connecl to gate of B low-side power MOSFET.
19
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
-,.tlHV
-
.. .... ,.. ..
I tI_....
Hlgn-sloe VUlpUl.
vonneCllO gale Of tI Hlgn-sloe power MU"r-c: I.
a • . - .... _ _ _
~
6-18
HIP40BO
Timing Diagrams
ms=o----~_+_+~~---------------------
HEN=l ----~_+_+---------------------------------IN+ > IN- - - - - ' \ J
ALO ______++.11
AHO
aLO
aHO ______~-+-'I
hPHL
TR
TF
(10%-iO%) (90%-10%)
FIGURE 1. BISTATE MODE
015=0
HEN
....
----.
--
....
-\.
/
\.
/
\.
\.
IN+> INALO
UI
/
g
a:ED
\
AHO
,~----------------1
aLO
aHO ____________________________________- J
',-_...,r
FIGURE 2. HIGH SIDE CHOP MODE
TOLPLH
DIS
~
--
TOIS
I-- TREF.PW
I
\.
HEN=l
\.
IN+ > IN-
/
ALO
AHO
I
alO
'\
/
BHO
~TUENFIGURE 3. DISABLE FUNCTION
6-19
..J
..J
:::I
\L.
HIP40BO
Typical Performance Curves
Voo =Vee
RHOEL
=VAHB =VSHS =12V. VSS =VALS =VSLS =VAHS =VSHS =OV.
=RLOEL= 100K. and TA =+25°C. Unless Otherwise Specified
13
14.0
i
!Z
l:!
a:
B
~
~
::)
1l
100 200 300
+750 C,::>
4.0
SWITCHING FREQUENCY (kHz)
~
800
FIGURE 5. loco. NO-LOAD 100 SUPPLY CURRENT vs FRE·
QUENCY (kHz)
",
a.
!Zw
Il!
B
(J
:::>
Q.
...w
...w>
~
1!E
·110
l.. ·190
zw
" "'- -
a:
a:
......
8 ·200
~
"r-....
~
...w
1!E .210
~ ·220
-SO
·25
0
25
50
75
100
·230
-40
125
·20
o
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IlL V8 TEMPERA·
TURE
~
~
100
120
80
15.0
'~"'
~ 14.0
~
13.0
is
c
~
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IlL VII TEMPER·
ATURE
w
li
!i
~
20
JUNCTION TEMPERATURE ("C)
JUNCTION TEMPERATURE (OC)
~
.... r-. ...
...
·120
~
......
>
~
--
12.0
.. 70
S.
-r-.
~w
C
11.0
60
z
--...
-r-._
0
!i
50
...a:
40
~
0
--- -
I- .....
~
..... ~
~
C§
~
30
10.0
-40
·20
020406080
100
120
-40
·20
JUNCTION TEMPERATURE ("C)
80
.. 380
.. 70
360
z
0
340
...
320
r-.
i!:0
a:
60
80
100
120
S.
S.
!iCI
40
FIGURE 13. UPPER DISABLE TURN·OFF PROPAGATION
DELAY T OISHIGH vs TEMPERATURE
400
~w
20
JUNCTION TEMPERATURE ("C)
FIGURE 12. AHB· AHS. BHB • BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
C
0
300
-40
-
~
..... ..... i"""
w 60
C
~
z
-
0
!i
~0
...a:
50
40
..... ..... .....
30
·20
020406080
100
-40
120
JUNCTION TEMPERATURE (OC)
·20
020406080
100
120
JUNCTION TEMPERATURE (OC)
FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION
DELAY vs TEMPERATURE
6·21
FIGURE 15. LOWER DISABLE TURN·OFF PROPAGATION
DELAY TOISLOW vs TEMPERATURE
HIP40BO
Typical Performance Curves
V DD =Vee
=VAHB =VBHB =12V, Vss =V/>J..S =VBLS =VAHS =VBHS =OV, RHDEL =RLDEL =
10K, TA =+25°C and RHDEL =RLDEL =10K, Unless Otherwise Specified
375
I
~
i
w
80
!
325
!l
:::>
275 1'-00
;
225
...
i"""
~
-
~
~
~
Ii!...
.s.
~
l!l
z
0
20
40
60
80
100
JUNCTION TEMPERATURE (OC)
...~
!
~
w
Q
--
- -
_r-
-40
-20
~
70.0
-
0
... ~ r-
~
60.0
...a:
50.0
~
0
20
40
60
80
100
0
20
40
60
80
100
JUNCTION TEMPERATURE ("C)
-
-40
120
..... ~
.,. ~ .,. ....
.... r-
f- ~
-20
0
20
40
60
80
100
FIGURE 19. UPPER TURN-ON PROPAGATION DELAYTHPLH
vsTEMPERATURE
..
80.0
Q
70.0
.s.
~w
90.0
z
~
0
Ii
~
0
60.0
...~ 50.0
~
-40
-20
o
~
f-
-
-~
~~
20
40
60
80
100
JUNCTION TEMPERATURE ("C)
120
JUNCTION TEMPERATURE ("C)
90.0
40.0
120
40.0
.s. 80.0
~
l!l 70.0
Ii
~
80.0
Z
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
..
o
FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE
70.0
40.0
-20
JUNCTION TEMPERATURE (OC)
80.0
50.0
30
90.0
60.0
-
40
-40
120
90.0
o
Ii
~
~
50
20
-20
FIGURE 16. TREF.PW REFRESH PULSE WIDTH vs TEMPERATURE
.
60
~
a:
175
-40
70
-
...a:
50.0
-~ ~
40.0
-40
120
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
60.0
-20
0
20
40
-
-r-
60
80
~
100
-
~
120
JUNCTION TEMPERATURE ("C)
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH
vs TEMPERATURE
6-22
HIP4080
Typical Performance Curves
Voo = Vee = VAHB = VBHB =12V. Vss =VALS = VBLS
=VAHS = VBHS = OV. RHOEL = RLOEL =
lOOK and TA =+25°C. Unless Otherwise Specified
13.5
r-r-r-r-T""T"".,.-.,.-..,.....,.....,......,......,...-...-...-...-r-.
13.5
r-r-r-.-.-,..-,..-..,,-,-,...,...,...-r-r.,..,....,
!1~5t:t:t:t:t:+=l=~~~~~:r:f:f:t=+~
! 12.5 I-f-f-f-+-+-+-++++++-I--I--I--I--I
w
:::E
w
~ 11.5 I-t-t-+-+-+-+-+++++-I--I--I--I--I--I
~ 11.51-f-+-+-+-+-+-++++++-I--I--+-+-I
oJ
~
~
W
q10.5 1-t-t-+-+-+-+-+-+++++-t-t-t-t-1
~ 10.5 I-f-f-+-+-+-++++++++-I--I--I--I
C
z
a:
w
~ BtE~±fffHH!tm
~
8.5
HH-+-+-+++-+-+-HH-+-+-+-t-i
9.5
8.5
-40
-20
o
~
~
~
~
100
8.5 '--L-'--L-L-L...-JL...-JL...-JL...-J'--'--'--'--''--'--''--'--'
-40
-20
0
20
40
60
80
100 120
1~
JUNCTION TEMPERATURE (OC)
JUNCTION TEMPERATURE (C)
FIGURE 22. GATE DRIVE FALL TIME T F vs TEMPERATURE
6.0
FIGURE 23. GATE DRIVE RISE TIME TR VB TEMPERATURE
r-r-r-T""T""-r--.--.--.-..,......,......,......,......,......,...-...-r....,
1500
~
~
~ 5.5
;!;
;; 1250
w
'-'
!;
g
...
iiE
5.0
"'-
CI
g1000 ""'"
t:t~;t;t~~~~~~~~t:t:t:t:t=J
""'"
w
~ 750
Ii,I
z
r-o
oJ
9 4.5 1-+-+-+-+-+-+-+--+--+-++-+--+--+--1--1-...,
... 500 r--
:r:
a: 250 r--
~
J
~
r--
~
4.0 L-L-L-L.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....J--1--1.....J
-40
-20
020406080
100 120
r-o
+750 C - V
+12SOC
./
-
10
12
14
BIAS SUPPLY VOLTAGE M
FIGURE 24. VLDEL• VHDEL VOLTAGE vs TEMPERATURE
FIGURE25. HIGH LEVEL OUTPUT VOLTAGE. Vee - VOHvs BIAS
SUPPLY AND TEMPERATURE AT 100mA
1500
3.5
:;-
g
E
;; 1250
3.0
z~
w
~
g1000
a: 2.5
a:
:::>
(.)
2.0
w
~
750
...
SOO I-
~
I- +2SOC
250 I- +750 C-
It
Z
I- -40o C
o
/" V V
OOcL L L V
+250 C ./ /' /'
8
6
JUNCTION TEMPERATURE (OC)
~
~
./
-40o c /
OOC
./
./
./
/'
/"
./
iii
w 1.5
;;:
a:
C 1.0
w
/'
Ii:CI
,.... +1250 C-'
6
~
""
V"
..... ~
......
~
~
0.5
0.0
10
12
6
14
BIAS SUPPLY VOLTAGE (V)
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL VB BIAS SUPPLY AND TEMPERATURE AT 100mA
7
8
10 11 12 13
Voo. Vee. VAHB. VBHB (V)
14
15
16
FIGURE 27. PEAK PULLDOWN CURRENT 10 VB BIAS SUPPLY
VOLTAGE
6-23
HIP4080
Typical Performance Curves
Voo = Vee = VAHB = VBHB = 12V, Vss = VI>J..S = VBLS = VAHS = VBHS = OV, RHoEL = RLoEL =
100K and TA = +25°C, Unless Otherwise Specified (Continued)
3.5
.,.,
~ 3.0
ffi
a:
2.5
i3
2.0
.., V
a:
~
iii 1.5
~
2i
w
!c
"
V
/"
500
~
i
I-
z
w
a:
a:
:::I
(J
.,., / " ~
Ul
~
0.5
0.0
7
8
8
3,000"
20 10 5
1,000 '\
~
'~"'
~
6
50 -
w
1.0
10
11
12
13
14
15
2
0.5
0.2
0.1
16
V
~
V V
. / V I~ V
I-
Ii:
~
w
>
w
100
~
50
5
..J
~
~
V
...... V
~
5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)
500 1000
FIGURE 29. LOW VOLTAGE BIAS CURRENT 100 AND Icc
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE
,..,..
120
V
~~
20
10
V
V V
,...-: "". / .., 10'
2
V
1200
i3
V
V
/' V
,/
500
a:
a:
V
.'\.
V
V
150
1000
zw
V
"- V
100" '\. l7 V
K: ~ /"
VO[)o Vee, VAHB. VBHB (V)
FIGURE 28. PEAK PULLUP CURRENT 10. vs SUPPLY VOLTAGE
V
200
100 -10,000,\
.-::::::::c ~ r<-~ ?<
-
r--- :-- 80V
60V
------ ---- t--. r--
1/
2
40V
./
30
~20V
2
5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)
o
500 1000
V
10
V
..V
v
V
50
100
150
200
HDELILDEL RESISTANCE (len)
250
FIGURE 31. MINIMUM DEAD-TIME VB DEL RESISTANCE
FIGURE 30. HIGH VOLTAGE LEVEL·SHIFT CURRENT VB
FREQUENCY AND BUS VOLTAGE
6·24
HIP4080
HIP4080 Power-up Application Information
The HIP4080 H-Bridge Driver Ie requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-Bridge power MOSFETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.
However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 32. Pulling
LDEL to VDO will indefinitely delay the lower turn-on delays
through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled,
i.e. DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+!lN- switch a full cycle while LDEL
is held high, to avoid Shoot-through. This start-up procedure
can be initiated by the supply voltage andlor the chip enable
command by the circuit in Figure 32.
g
FIGURE 32.
a:
m
..J
..J
;:)
u..
Voo
12V, FINAL VALUE
'8.3V TO 9.1 V (ASSUMING 5% ZENER TOLERANCE)
~-------5.1V
TIMING DIAGRAM FOR FIGURE 32
NOTE:
1. Between 11 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If
the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 1Oms time delay during which the IN+
and IN- pins must cycle at least once.
2. Another product, HIP4080A, incorporates undervoHage circuitry Which eliminates the need for the above power up circuitry.
6-25
l±;T
IN2 IN1
+12V
'":o.- ""-
1
U2
2
7-Ir·" ""'. ''''''~ ""
iii
L------' -
MPR1
... OUTIBU
-
...-_+--f___--:21HENlBHI
r~MPR2
W U2 12 .•• IN+lAU
L-------:
J~!'fl3HENlBHI
Q2
Vee 15
ALS 14
F
1
CWI'
ft
AHS 12
11
ALO
f~
L2
0000
=
3
0
B+
"'J
~ 0000 I
C1
2
R23
ALO 13
R34
=-
BHS 19
3 DIS
BLO>r<--18--t+-t--1
4 Vss
BLS 17
OUTIBU Veo 16
IN+lAU
7:"1 IN., IN-, 10H = -250~A
Voo
-0.4
-
Voo
- 0.5
V
INPUT PINS: DIS
Low Level Input Vottage
High Level Input Voltage
Input Voltage Hysteresis
Lew
La¥a~
6-30
-
0.8
V
2.7
-
V
35
-
-100
-75
-135
-65
-
+1
-10
+10
mV
IJA
IJA
Specifications HIP40BOA
Electrical Specifications
VDD =vee =VAHB =VBHB =12V, Vss =VALS =VBLS =VAHS =VBHS =OV, RHDEL =RLDEL =100K, and
TA =+25°C, Unless Otherwise Specified (Continued)
TJ =-400C
TO+125°C
TJ =+25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
I TYP
MIN
MAX
MIN
MAX UNITS
INPUT PINS: HEN
Low Level Input Vottage
VIL
VIH
Full Operating Conditions
-
Full Operating Conditions
2.5
-
-
0.8
V
-
-
mV
-150
-270
-130
+1
-10
+10
IlA
IlA
4.8
5.4
V
1.0
0.5
1.1
V
1.1
0.5
1.2
V
A
1.0
2.7
35
-
-260
-200
-1
-
LDEL, HDEL Voltage
VHDEl,V
IHDEL =ILDEL =-loollA
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
4.9
5.1
5.3
Low Level Output Voltage
VOL
IOUT-l00mA
0.7
0.85
High Level Output Voltage
Vee - VOH
lOUT - -100mA
0.8
0.95
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
IlL
VIN
High Level Input Current
IIH
VIN
=OV, Full Operating Conditions
=5V, Full Operating Conditions
V
TURN-ON DELAY PINS: LDEL AND HDEL
I
Peak Pullup Current
10+
VOUT-OV
1.7
2.6
3.8
1.4
4.1
Peak Pulldown Current
10 -
VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
8.1
8.8
9.4
8.0
9.5
V
Under Voltage, Rising Threshold
UV+
Under Voltage, Falling Threshold
UV-
7.6
8.3
8.9
7.5
9.0
V
Under Voltage, Hysteresis
HYS
0.25
0.4
0.65
0.2
0.7
V
Switching Specifications
VDD =vee =VAHB =VBHB =12V, vss =vAlS =VBLS =VAHS =VSHS =OV, RHDEL =RLDEL =10K,
CL =1000pF, and TA =+25°C, Unless Otherwise Specified
PARAMETERS
SYMBOL
Lower Turn-off Propagation Delay (IN+lIN- to ALOIBLO
Upper Turn-off Propagation Delay (IN+lIN- to AHO/BHO)
Lower Turn-on Propagation Delay (IN+lIN- to ALO/BLO)
Upper Turn-on Propagation Delay (IN+lIN- to AHO/BHO)
TJ =-400C
TJ = +25°C
TO+125°C
MIN TYP MAX MIN MAX UNITS
TEST CONDITIONS
-
TLPHL
THPHL
TLPLH
THPLH
-
Rise Time
TR
Fall Time
TF
-
Turn-on Input Pulse Width
TpWIN.QN
50
Turn-off Input Pulse Width
40
70
50
80
40
70
70
110
10
25
10
25
-
-
-
50
ns
ns
90
ns
140
ns
35
ns
35
ns
-
ns
ns
TpWIN.QFF
40
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
-
45
75
-
95
ns
Disable Turn-off Propagallon Delay
(DIS - Upper Outputs)
TDISHIGH
-
55
85
-
105
ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH
-
45
70
-
90
ns
Refresh Pulse Width (ALO and BLO)
TREF·PW
240
380
500
200
600
ns
-
480
630
-
750
ns
40
70
60
90
Disable to Upper Enable (DIS - AHO and BHO)
TUEN
HEN-AHO, BHO Turn-off, Propagation Delay
THEN·PHL
RHDEL - RLDEL =10K
HEN-AHO, BHO Turn-on, Propagation Delay
THEN·PLH
RHDEL =RLDEL =10K
40
90
110
-
90
ns
110
ns
TRUTH TABLE
INPUT
OUTPUT
IN+> IN-
HEN
UN
X
X
i<.
0
1
0
1
0
1
1
0
0
0
0
0
DIS
1
0
0
0
0
X
X
1
X
6-31
AlO
AHO
BlO
BHO
u
u
u
u
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
HIP40BOA
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3011A out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
HEN
High-side Enable input. logic level Input that when low overrides IN+IlN- (Pins 6 and 7) to put AHO and BHO
drivers (Pins 11 and 20) In low output state. When HEN Is high AHO and BHO are controlled by IN+IlN- inputs.
The pin can be driven by signal levels of OV to 15V (no greater than Voo ). An Internall0011A pull-up to Voo will
hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+IINinputs.
3
DIS
DISable Input. logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signalleveis of
OV to 15V (no greater than Voo ). An internal100llA pull-up to Voo will hold DIS high If this pin Is not driven.
4
Vss
Chip negative supply, generally will be ground.
5
OUT
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6
IN+
Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then AlO and BHO are low level outputs and BlO and AHO are high level outputs. If IN+ is less than IN- then AlO and BHO are high level outputs
and BlO and AHO are low level outputs. DIS (Pin 3) high level will override IN+IlN- control for all outputs. HEN
(Pin 2) low level will override IN+IlN- control of AHO and BHO. When switching in four quadrant mode, dead
time in a half bridge leg is controlled by HDEl and lDEl (Pins 8 and 9).
7
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
8
HDEl
High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage is approximately 5.1 V.
9
lDEl
low-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no Shoot-through by delaying the turn-on of the low-side drivers. lDEl reference voltage is approximately 5.W.
10
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3011A out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
12
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13
AlO
A low-side Output. Connect to gate of A low-side power MOSFET.
14
AlS
A low-side Source connection. Connect to source of A low-side power MOSFET.
15
Vcc
Positive supply to gate drivers. Must be same potential as Voo (Pin 16). Connect to anodes of two bootstrap
diodes.
16
Voo
Positive supply to lower gate drivers. Must be same potential as Vec (Pin 15). De-couple this pin to Vss (Pin 4).
17
BlS
B low-side Source connection. Connect to source of B low-side power MOSFET.
18
BlO
B low-side Output. Connect to gate of B Low-side power MOSFET.
19
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20
SHO
6 High-side Output. Connect to gate of B High-side power MOSFET.
6-32
HIP40BOA
Timing Diagrams
UN.~S O---------+-+~----------------------------------------------...
HEN 1---------+-+~----------------------------------------------...
IN+> INAlO ________++.11
AHO
BlO
-+-+-'1
BHO ________
TLPHL
TR
TF
(10% - 90%) (90% -10%)
FIGURE 1. BISTATE MODE
- - --
THEN-PHL
UN.~S
0
HEN
-~
'\.
/
IN+> IN-
/
'\.
'\.
'\.
w
/
AlO
g
a:m
'\.
AHO
\~--------------------------BHO __________________________________________-',
BlO
FIGURE 2. HIGH SIDE CHOP MODE
TDLPLH
UNor~S
~
~
.... TREF-PW
I
'\.
HEN
'\.
IN+ > IN-
/
AlO
AHO
/
BlO
'\.
/
BHO
~TUEN-FIGURE 3. DISABLE FUNCTION
6-33
::I
~
HIP4080A
Typical Performance Curves
=
=
=
=
=
=
Voo Vcc VAHB V BHB l2V. Vss VPLS V BLS
lOOK. and TA +250 C. Unless Otherwise Specified
=
=VAHS =VBHS =OV. RHOEL =RLOEL =
13
14.0
!
...z
12.0
w 10.0
a::
a::
:>
0
...~...
:>
'"
il
8.0
i---'""'"
---
---
12.5
!!E
:.,.....-
~
8
8::
~
6.0
10
12
VOO SUPPLY VOLTAGE (V)
10
14
FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE
~
FIGURE 5. 1000 NO-LOAD 100 SUPPLY CURRENT vs FREQUENCY (kHz)
+l25°C,-
C
V
15.0
./
~
V
10.0
o
:>
w
a:: 3.0
a::
-40oC .....
-~ X
2.0
/"
....-:: ~
---
0.0 ~
o 100
100 200 300 400 500 600 700 800 gOO 1000
SWITCHING FREQUENCY (kHz)
FIGURE 6. SIDE A. B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
-
~
. / '"'-...... ~ ~""
,./
V ........:: ~ ~
1.0
.......
/"
"-
+25OC
'"jl
/'
0.0
- ~ -...... . /
aOc ~ ~ / '
...z
......~
:>
/"
5.0
+750 C,::> ~
4.0
.§.
0
. . . . 1-'
~
it
1000
5.0
o
~
I
200
400
600
800
SWITCHING FREQUENCY (kHz)
20.0
w
~
V
/
I-'
/
V
/
10.5
8
!!i
11.0
il
2.0
~
a::
11.5
~
4.0
!
12.0
....
....
./
...",,;
~
200 300 400 500 600 700 800 gOO 1000
SWITCHING FREQUENCY (kHz)
FIGURE 7. Iceo. NO-LOAD Icc SUPPLY CURRENT vs FRE·
QUENCY (kHz) TEMPERATURE
2.5
!
~
w
2
/
a::
a::
8'" 1.5
'"
~
:>
1
'"~
~ 0.5
~
o
/
1\
/
iii
8::
V'
/
1\,
i"-.
/
200
400
600
800
-40
1000
SWITCHING FREQUENCY (kHz)
FIGURE 8. IAHB.IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY
6-34
·20
i' ......
...... ~
r- I-
....
i"'" l-
0
20
40
60
80
100
JUNCTION TEMPERATURE ("C)
I-
120
FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERA·
TUREATV CM =5V
HIP40BOA
Typical Performance Curves
Voo
=Vee =VAHB =VBHB =12V. Vas =VAiS =VBLS =VAHS =VBHS =OV. RHOEL =RLOEL =
lOOK. and TA =+250 C. Unlass Otherwise Specified (Continued)
·180
·110
...z~
w
a: ·100
a:
:>
u
"
.......
~'1110
~
"-
"- .........
...:>
...l!!
....
w
l:!a:
tl
~
~
"' ....... r-r--
l!! .210
Lrl
·110
>
"
·200
~
w
....
~
....
...~ ·220
·230
-40
·120
-SO
·25
0
25
50
75
100
125
·20
o
~
~
~
~
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IlL vs TEMPER·
ATURE
>'
;;; 15.0
~
14.0
~
~
13.0
~
«
r--
G
12.0
CJ
--
.s
i"""
r-.
--
~
~
~ 11.0
c
z
0
....
50
...~
40
~
~
I-
~
i:C
UI
;:)
30
·20
o
~
~
~
~
1~
100
U.
-40
-20
JUNCTION TEMPERATURE fC)
80
100
120
.s
""
5w 60
~
c
z
I;
0
/'
l.,.....--"
.............. ....
~...
...
II:
·25
o
.... .... ....
50
0
425
-SO
60
.. 70
.s 500
~
40
80
..
...~ 450
20
FIGURE 13. UPPER DISABLE TURN·OFF PROPAGATION
DELAY T OISHIGH vs TEMPERATURE
525
~
o
JUNCTION TEMPERATURE fC)
FIGURE 12. AHB· AHS. BHB· BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
~
~ 475
w
g
..J
..J
10.0-40
5
,
~
----
5w 60
~
z
!
,,
.. 70
....
1~
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IlL vs TEMPER·
ATURE
80
!j
§!
100
JUNCTION TEMPERATURE fC)
JUNCTION TEMPERATURE fC)
40
-I-
.... 1-1"""
.... ~ ....
-
30
25
50
75
100
125 150
-40
JUNCTION TEMPERATURE (OC)
FIGURE14. DISABLE TO UPPER ENABLE TUEN PROPAGATION
DELAYvsTEMPERATURE
·20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE fC)
FIGURE 15. LOWER DISABLE TURN·OFF PROPAGATION
DELAY TDlSLOW vs TEMPERATURE
6·35
HIP40BOA
Typical Performance Curves
..
VDD =Vee =VAHB =VBHB =12V, Vss =VALS =VBLS =VAHS = VBHS =OV, RHDEL =RLDEL =
10K, and TA = +25°C, Unless Otherwise Specified
450
80
.
.s
i
"'" i'.....
w
400
0-
i!!:
w
~ 750
s.o
~
It:
t--- -40oc /
/'/
Lv
t--ooc
SOO
V/
0
t--- +25 C ~ V
~
§ 2S0 I - - +7SOC; / '
t--- +1250 C/
o
10
12
....
w
0
....
.I 4.5
w
0
...
%
-40
·20
0
20
40
60
80
100
120
FIGURE 24. VLOEL• VHOEL VOLTAGE vs TEMPERATURE
FIGURE25. HIGHLEVELOUTPUTVOLTAGE.Vec·VoHvsBIAS
SUPPLY AND TEMPERATURE AT 100llA
1500
3.S
:;;-
.§. 1250
~
~
It:
3.0
ffi
2.5
a:
a:
1000
::>
(J
w
~
~
...
w
~
l<:
750
SOO
q
o
.,
V
~
2.0
~
Z
f-
-400 C
r-
o°e-
z
a: 2S0
i:!
14
BIAS SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE ("C)
!j
L
+2SoC
- +7SoC
- +12SoC
10
/'
L
~ 1.S
L
>
/ / /'/
/'/' /'
/'/
/'
2iw
1.0
~
O.S
0.0
12
14
BIAS SUPPLY VOLTAGE (V)
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100llA
V
6
7
8
~
k-"
~
""'"
II
10
11
12
13
14
15
16
Vcc. Veo. VAHG. VBHBM
FIGURE 27. PEAK PULLDOWN CURRENT I().. BIAS SUPPLY
VOLTAGE
6·37
HIP40BOA
Typical Performance Curves
Voo
=Vee =VAHB =VBHB =12V, Vss =V/>J..s =V BLS =VAHS =VBHS =OV, RHOEL =RLOEL =
lOOK, and TA = +25°C, Unless Otherwise Specified (Continued)
3.5
./
~ 3.0
...z
w 2.5
II:
II:
::0
U
~
.,- V . .
2.0
z
iii
w 1.5
V
>
a:c
w
!i(
..",-
500
..",-
1
...
~
100
50 t- 3,000
II:
II:
::0
20 t- 1,000
U
5
~
2
~
CI 0.5
g
1
~
0.5
0.1
6
7
8
II
10
11
12
13
14
15
./
V
w 200
i3
Ii:
%
~
w
>
w
....
100
50
20
10
V
10
V
20
V
""
""'-
~
L
V
V
",
2
5
10
20
50
100 200
500 1000
FIGURE 29. LOW VOLTAGE BIAS CURRENT 100 AND lee (LESS
QUIESCENT COMPONENT) va FREQUENCY AND
GATE LOAD CAPACITANCE
./
V
V
~
SWITCHING FREQUENCY (kHz)
1000
II:
II:
~
,/.
"" V "" i'
16
FIGURE 28. PEAK PULLUP CURRENT 10. va SUPPLY VOLTAGE
500
V ~~
/' V
Vee. Voo, VABH, VBHB (V)
i
...z
,"''\-
~
0.2
0.0
L
V ./
V V'" V"
100\ 1,\ ...,rV
. / V"
~~
~ ;~ V
10 t-
~w
1.0
t-l~,OOO
z
w
/ i---""
",
200
.,§
I
-
~
UV+
:::::"""
I""'"
8.8
ui
~
"'I'
!:j
g
8.6
~
-
t
::0
en 8.4
~
50
100
200
500
SWITCHING FREQUENCY (kHz)
uv-
r-- f"-.
8.2
1000
50
25
o
25
50
n
~I'
100
125
150
TEMPERATURE <"C)
FIGURE 30. HIGH VOLTAGE LEVEL·SHIFT CURRENT va
FREQUENCY AND BUS VOLTAGE
FIGURE 31. UNDERVOLTAGE LOCKOUT va TEMPERATURE
150
120
..
.s.
90
~
~
~
L
60
/'
lL
V
30
V
a
V,
10
50
./
I
I
I
100
150
200
HDEULDEL RESISTANCE (1Ul)
I
250
FIGURE 32. MINIMUM DEAD-TIME va DEL RESISTANCE
6·38
IN2 IN1
POWER SECnON
+12V
CONTROL lOGIC
SECTION
F
R29
~
I
~!
OUTIBU
~
-
L"":,""A,,1 .
6 IN+lAU
7 IN-IAHI
8 HDEl
• HENlBHI
r---1
J~~I'R4
•
.~ I~
3
IN-IAHI
,.1!!
3
2
CW
CD4069UB
BHO 20
~2
1
CW
1
~
LDEL
AHB
~~
2
1
T
~t-
"1
B+
~I-o
3
II
11r---i"
J~~:'R3
1
A
1 BHB
I
CD4069UB
R21
C~
2 HENlBHI BHS 19 . 1
BlO 18
3 DIS
VSS
BlS 17
OUTIBU Veo 16 +12V
J~~'!'2IN+lAU
~
DRIVER SECOON
+
~
,
JM~
~
-
flL
Vee
ALS
AlO 13
AHS 12
AH 11
1
~I-
l
'1-0
fli- t--
~
OOOOC11
2
~3
3
R24
1
~
Q4
OO~O 1-0
AO
BO
:h
cs-!-
I
(
ALS
lCY
CX
~
2
t1.,...
R30
R31
T
~~
,...
-=E"
BLS
NOTE:
DEVICE CD4069UB PIN 7 = COM. PIN 14 =+12V.
FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC
FULL BRIDGE
-
~
~
-!-C2
3
C3
~
COM
(;t
q>
.".
0
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
*
...... •••••• 1] ••••••
..•• •••• •••
GND
+12V
@
@
@
@
~
~
~
~
4••
~
~
•• ••
•• ••
•• ••
•• ••
•• ••
•• ••
••
•• ••
•• ••
•• •• ••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
D
..
~
4• •
4• •
4• •
4• •
4••
••
••
••
••
•
••
.. 1]
4• •
4• •
4• •
~
4• •
4••
~
•
••
••
••
••
••
•
••
••
••
••
~
••
••
••
•
~
•
n0
DIS
••
•• •
••
° [][]
:: ",8
••
••
~:
iil
•
J...@
@
ALS
ALO
@u@
R34
••
@
Q
R
Q1
Q3
~
~
~
•
.0.
Q2
c.:-=- ·
: ""
•
R33
'"
R21
• • BLS@
••
-
R22
BHO.~.
R24
BLO.~
• .JMPR1.
• • JMPR2e
• .JMPR_ •
• .JMPR4
•
• • '0 @ .
• • IN2 @ .
$
COM
C8
•••
U2
@~
B+
.::3
CR2
DO [;]QDDO:H~
•• d I @.
••
••
!E~~~
=i • • • ~+
13+
@~
$
$
@
o~ ~D ~
~
a:
@
FIGURE 34. HIP4080A EVALUATION BOARD SILKSCREEN
04
~
@
@
r--l r--l
0
@
"U'U08l
@
@
@
D·
@
m
*
~
~
0
Co
g
HIP4081
80V/2.5A Peak, High Frequency
Full Bridge FET Driver
April 1994
Features
Description
• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations
The HIP4081 is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastiC
SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a
shoot·through condition. The HIP4081 can switch at frequencies up to 1MHz and is well suited to driving Voice Coil
Motors, high-frequency Class D audio amplifiers, and power
supplies.
• Bootstrap Supply Max Voltage to 9SVDC
• Drives 1000pF Load at 1MHz in Free Air at +SOoC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with SV to 1SV
Logic Levels
• Very Low Power Consumption
Applications
• Medium/large Voice Coil Motors
• Full Bridge Power Supplies
• Class D Audio Power Amplifiers
For example, the HIP4081 can drive medium voltage brush
motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum "on·time"
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead·times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.
A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle
wave and to facilitate "hysteresis mode" switching.
Ordering Information
• High Performance Motor Controls
PART
NUMBER
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
TEMPERATURE
RANGE
PACKAGE
HIP40811P
-40oe to +85°e
20 Lead Plastic DIP
HIP40811B
-40oe to +85°e
20 Lead Plastic sOle (W)
• U.P.S.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6-41
File Number
3556.4
HIP4081
Functional Block Diagram
(112 HIP4081)
HIGH VOLTAGE BUS S 80VDC
CBS
TO Veo (PIN 16)
DBS
+12VDC
= SUPPLY
BIAS
Typical Application (PWM Mode Switching)
80V
1
L
PWM
INPUT
GND
ToopnONAL
CURRENT CONTROLLER
~-....---<
6V~
~
6-42
GND
Specifications HIP4081
Absolute Maximum and Thermal Ratings
Supply Voltage, Voo and Vee .•....•.....••••.... -o.3V to 16V
Logic VO Voltages .•..••.••.....•...••..• -0.3V to Voo +0.3V
Voltage on AHS, BHS .•••••.•.••••••.• -6.0V (Transient) to 88V
Voltage on ALS, BLS ....•.. -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB ......... VAHS. SHS -o.3V to VAHS, SHS +16V,
or 95V, whichever is less
Voltage on ALO, BLO •.••..•....•.. VALS. SLS -0.3V to Vee +O.3V
Voltage on AHO, BHO ......•. VAHS. SHS -0.3V to VAHS. SHS +0.3V
Input Current, HDEL and LDEL .••.•••••••••••.•. -5mA to OmA
Phase Slew Rate .•••••.••.....•..•...••.•...••.••. 20Vlns
NOTE: All voltages are relative to pin 4, VSS, unless otherwise specified.
Storage Temperature Range ••..••...•..••.... -65"0 to + lSOoC
Operating Max. Junction Temperature ..•.••.•.••.••.•• + 125°C
Lead Temperature (Soldering lOs) ••.•..•.•••••.•••••• +3OOoC
(For SOIC - Lead Tips Only)
Thermal Resistance, Junction-Ambient
SOIC Package •.•.•..••••••.•••••.•.•••...•.••.. 85°C/W
DIP Package .•••••.••.••••••.••..••.......•...• 75°CIW
Maximum Power Dissipation at +85°C
SOIC Package ••.....•••.•..••••..•••••.••...••• 470mW
DIP Package •••••..•.•••.•••..•..••••.•••••.••• 530mW
CAUTION: Str8Sses above /hose listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a str8Ss only mting and opemticn
of the device at these or any other conditions above those indicated in the opemtional sections of this specification is not implied.
Operating Conditions
Supply Voltage, Voo and Vee •••.•.•..•...•...••. +6V to +15V
Voltage on ALS, BLS .•..•...••............... -1.0V to +1.0V
Voltage on AHS, BHS •.....•.•••..••••..••••..... -1 V to 80V
Electrical SpeCifications
Voltage on AHB, BHB . . • . . . . • .• VAHS. SHS +5V to VAHS, SHS +15V
Input Current, HDEL and LDEL. ............... -5OOIlA to -50ItA
Operating Ambient Temperature Range .•..•.•.•. -400C to +85°C
v DO = vee = VAHS = VSHS = 12V, Vss = VALS = VSLS = VAHS = VSHS = OV, RHOEL = RLOEL =lOOK and
TA =+25°C, Unless Otherwise Specified
TJs='400C
TO +125°C
T J = +25°C
PARAMETER
TEST CONDITIONS
SYMBOL
MIN
TYP MAX MIN
MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
VDO Quiescent Current
100
All Inputs = OV
7
9
11
6
12
rnA
VDO Operating Current
1000
Outputs Switching f =SOOkHz
8
9.5
12
7
13
mA
Vcc Quiescent Current
Icc
All Inputs =OV, IALO = ISLO =0
-
0.1
10
-
20
IlA
Vee Operating Current
leco
f = 500kHz, No Load
1
1.25
2.0
0.8
3
rnA
All Inputs =OV, IAHO = ISHO = 0
Voo = Vee = VAHS = VSHS = 10V
-SO
-30
-15
-60
-10
IlA
f =500kHz, No Load
0.5
0.9
1.3
0.4
1.7
mA
10
IlA
AHB, BHB Quiescent Current Qpump Output Current
IAHS,lsHS
AHB, BHB Operating Current
IAHBO, ISHOO
-
0.02
1.0
VAHS-VAHS
VSHS-VSHS
IAHS =IAHS =0, No Load
11.5
12.6
14.0
Low Level Input Voltage
VIL
Full Operating Conditions
-
-
0.8
V
VIH
Full Operating Conditions
2.5
-
1.0
High Level Input Voltage
-
2.7
-
V
mV
Low Level Input Current
IlL
VIN =OV, Full Operating Conditions
-130 -100
High Level Input CUrrent
IIH
VIN =5V, Full Operating Conditions
AHS, BHS, AHB, BHB Leakage Current
IHLK
AHB-AHS, BHB-BHS Qpump
Output Voltage
VAHS = VSHS =VAHS =VSHS =95V
10.5 14.5
V
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS
Input Voltage Hysteresis
35
-
-
-
:~
-135
-65
IlA
-1
-
+1
-10
+10
IlA
4.9
5.1
5.3
4.8
5.4
V
lOUT = 100mA
0.7
0.85
1.0
0.5
1.1
V
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage
VHOEL, VLDEL IHDEL =ILDEL =-1 001lA
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage
VOL
High Level Output Voltage
Vce-VOH
lOUT = -100mA
0.8
.95
1.1
0.5
1.2
V
Peak Pullup Current
10+
VOUT=OV
1.7
2.6
3.8
1.4
4.1
A
Peak Pulldown CUrrent
10-
VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
6-43
Specifications HIP4081
Switching Specifications
=
=
voo vee VAHB
CL =1000pF
=VBHB = 12V, Vss = v AlS =VBLS =vAHS = VBHS =OV, RHOEL =RLDEL =10K,
TJS _-40oC
TO+125OC
TJ =+25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX.
MIN
MAX UNITS
Lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)
TLPHL
-
30
60
-
80
ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL
-
35
70
-
90
ns
lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)
TLPLH
-
45
70
-
90
ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
-
60
90
-
110
ns
10
25
ns
10
25
-
35
TF
-
35
ns
TpwlN-ON
50
50
TpwlN-OFF
-
-
40
-
40
45
75
-
95
ns
55
85
-
105
ns
35
70
-
90
ns
Rise Time
TR
Fall Time
Turn-on Input Pulse Width
Turn-off Input Pulse Width
-
ns
ns
Disable Turn-off Propagation Delay
(DIS - lower Outputs)
TOISLOW
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TOISHIGH
-
Disable to lower Turn-on Propagation Delay
(DIS - AlO and BlO)
TOlPLH
-
Refresh Pulse Width (AlO and BlO)
TREF.pW
160
260
380
140
420
ns
THEN
-
335
500
-
550
ns
Disable to Upper Enable (DIS - AHO and BHO)
TRUTH TABLE
INPUT
ALI, Bli
AHI,BHI
X
1
OUTPUT
DIS
AlO,BlO
X
1
0
0
X
0
1
0
0
1
0
0
1
0
0
0
0
0
NOTE: X signifies that input ean be either a "1" or -0",
6-44
AHO,BHO
HIP4081
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
BHI
B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent ha~-brldge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo ). An Internall001lA
pull-up to Voo will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.
3
DIS
DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signalleveis of
OV to 15V (no greater than VOO ). An internall00l1A pull-up to Voo will hold DIS high if this pin is not driven.
4
Vss
Chip negative supply, generally will be ground.
5
BU
B Low-side Input. logic level input that controls BlO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BlO and BHO drivers, with dead time set by delay currents at HDEl and lDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels
of OV to 15V (no greater than V OO ). An internall00l1A pull-up to Voo will hold BLI high if this pin is not driven.
6
ALI
A low-side Input. logic level inputthatcontrols AlO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both AlO and AHO drivers, with dead time set by delay currents at HDEl and lDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels
of OV to 15V (no greater than V oo). An internall001lA pull-up to Voo will hold ALI high if this pin is not driven.
7
AHI
A High-side Input. logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.
8
HDEl
High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage is approximately 5.1 V.
9
lDEl
low-side turn-on DElay. Connect resistor from this pin to V ss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. lDEl reference voltage is approximately 5.1 V.
10
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacHor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
12
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capaCitor to this pin.
13
AlO
A low-side Output. Connect to gate of A low-side power MOSFET.
14
AlS
A low-side Source connection. Connect to source of A low-side power MOSFET.
15
Vec
Positive supply to gate drivers. Must be same potential as V DO (Pin 16). Connect to anodes of two bootstrap
diodes.
16
Voo
Positive supply to lower gate drivers. Must be same potential as Vcc (Pin 15). De-couple this pin to Vss (Pin 4).
17
BlS
B low-side Source connection. Connect to source of B low-side power MOSFET.
18
BlO
B Low-side Output. Connect to gate of B Low-side power MOSFET.
19
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
6-45
w
g
a:ID
..J
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:::;)
II..
HIP4081
Timing Diagrams
x= A OR B. A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
DlS.O
-- --
-- --
--,
xu
\
XHI
XLO
XHO
--
I
-if--
-- --
'1--
TLPLH
~
FIGURE 1. INDEPENDENT MODE
,----, , J ,----,
,------, ' ___....,' ' ___---'1
DlS.O---------------------------------------------------------------------
xu
XHI
=HI OR NOT CONNECTED
XLO
XHO
, ______,
------'I
''-_ _....,1
'-
FIGURE 2. BISTATE MODE
--
--
TOLPLH
DlS
~
~TREF·PW-
I
\
xu
XHI
I
XLO
.J
==-~j
XHO --+-I--I.-=----THE-N
)-----------
~
FIGURE 3. DISABLE FUNCTION
6·46
HIP4081
Typical Performance Curves
Voo
=Vcc =VAHB =V BHB =l2V, Vss =VALS =V BLS =VAHS = V BHS =OV, RHOEL =R LOEL =
lOOK and TA =+25°C, Unless Otherwise Specified
11.0
14.0
i
...z
10.5
12.0
w 10.0
a:
a:
::>
0
~
......
::>
~ StO
",'"
20.0
0
15.0
,.,...
10.0
5.0
10-""'"
"",
"
",
400
+2SoC
ooC
3.0
o
~
It
l/
~
~~~
~
..... ......
o
a:aI
::::I
u.
100 200
300
400
500
600
700
800
1100 1000
SWITCHING FREQUENCY (kHz)
FIGURE 7. Iceo, NO-LOAD Icc SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE
-90
V
~ 1.0
...3!:
...
!!! -110
0.2
o
200
400
600
800
SWITCHING FREQUENCY (kHz)
-
~
./
-0.2
..........
~
..... ~
Z
~
!;
/'
/
...~
!5 0.6
........
~ -100
./'r'
SWITCHING FREQUENCY (kHz)
...z
800 1100 1000
- '-....,
.
-40oC,
::>
1/
0.0 I........
o 100 200 300
.§.
!Z
I:!
a:
"".
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT va
FREQUENCY (LOAD = 1000pF)
i
700
5.0
30.0
a:
a:
~
500 600
FIGURE 5. 1000 , NO-LOAD 100 SUPPLY CURRENT vs
FREQUENCY (kHz)
.§.
...z
400
SWITCHING FREQUENCY (kHz)
FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE
C
I'~
",,,,,,,
It
::>
./
4.0
9.5
B
~
Q
10-'1'
10-'1'
0
25
50
75
JUNCTION TEMPERATURE ("C)
100
125
FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IlL
vs TEMPERATURE
HIP4081
Typical Performance Curves
w
Voo =Vee =VAHS =VBHS =12V, Vss =V/oJ.s =VBLS = VAHS =VSHS = OV, RHOEL =RLOEL =
1OOK and TA = +25°C, Unless Otherwise Specified (Continued)
80
15.0
!.
;J
...:::E~
14.0
w
13.
~
I
CI
z
., 70
ot---
"""
~
12. 0
.s
-
~
~
"""
.... t---
0
"""
!i
~
!i
~0
t--- ~
...a:
~
11.0
!
10. 0
040
-20
o
~
60
~
M
~
100
~
40
30
040
1~
80
., 380
., 70
360
~w
Q
I-'"
~
!;( 340
r0- t---
60
0
1-0- i--"
!i
~
~
50
.... I-"" f--
...~ 40 ....
~
30
040
300
040
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE fC)
120
FIGURE 12. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE
-20
I---' I-"" I-""
~
0
~
40
60
80
JUNCTION TEMPERATURE fC)
100
120
FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDlSLO vs TEMPERATURE
80
375
70
325
i
w
~
~ 275
~
r--
.,w
%
~
1~
z
... 320
a:
0
20
40
60
80
100
JUNCTION TEMPERATURE fC)
.s
.s
~
-20
FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TOISHIGH vs TEMPERATURE
400
.,.s
~
~~
--
50
JUNCTION TEMPERATURE (OC)
FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
~~
.... I-"" f--
z
I-"" I--"
.... I-'"
-
225
30
I I I I I I I I I I I I I I I I I I
175
040
-20
0
20
40
60
80
100
20
JUNCTION TEMPERATURE (OC)
FIGURE 14. TREF.PW REFRESH PULSE WIDTH vs TEMPERATURE
I I I I I I I I I I I I I I I I I I
040
120
-~
0
20
40
60
80
100
JUNCTION TEMPERATURE (Oc)
120
FIGURE 15. DISABLE TO LOWER ENABLE TOLPLH PROPAGATION DELAY vs TEMPERATURE
6-48
HIP4081
Typical Performance Curves
Voo =Vee
=VAHB =VBHB =12V. Vss =VALS =VBLS =VAHS =VBHS =OV. RHoEL =RLOEL =
10K and TA =+25°C. Unless 01herwise Specified
so
80
.
70
~w
60
70
I!l
z
50
!;i
CI
:
30
l..- I--'
I--' I-
i!i
50
~
40
~
30
20
-40
·20
o
20
40
~
~
100
JUNCTION TEMPERATURE (OC)
20
-40
120
FIGURE 16. UPPER TURN·OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
70
~
60
100
120
..
70
~w
60
.5-
w
c
z
50
Ii
~
40
I..-
c
30
r-
z
0 50
~
"-
0
20
40
60
80
JUNCTION TEMPERATURE (OC)
so
.5-
0
·20
FIGURE 17. UPPER TURN·ON PROPAGATION DELAY THPLH VI
TEMPERATURE
so
..
..... ~
~
!;i
~I"'"
40
~
"-
_I--' ~
-
~
I-
~ 60
c
0
--
!
.5-
... --
l- I--' I-
r-
-
-~
Ii
~0
~ I""'"
"-
·20
020406080
100
30
20
-40
20
-40
40
cz:
120
·20
JUNCTION TEMPERATURE ('IC)
0204060
so
100
120
JUNCTION TEMPERATURE (OC)
FIGURE 18. LOWER TURN·OFF PROPAGATION DELAY T LPHL
vs TEMPERATURE
FIGURE 19. LOWER TURN·ON PROPAGATION DELAY T LPLH VI
TEMPERATURE
13.5 r-r-r-r-..................-....-....-,.-,.--,--,-.,-.,-""T""T-,
_1~5t:t:t:l:!=l=4=4=~~~~~~~:r:r~
!w
~ 11.5 t-t-t-t-+-+-+-+-+-++-+-+-+-+-t-t-1
~
a:
~ 10.5I-HHHH-i-i-i-i-i-i-t-t-t-t-+--1
z
cz:
j:!
8.5 L...-I....-I....-L....JL....JL.....JL.....J..............--<--<--<-L-L-L-L-I
-40
·20
0
20
40
60
80
100
JUNCTION TEMPERATURE ('IC)
9.5I-HHHH-iH-i-i-i-i-t-t-t-+-+--1
S.5 L...-I....-L....JL....JL.....JL.....JL.....J............................--<--<--<--<--<--'
120
-40
FIGURE 20. GATE DRIVE FALL TIME TFvs TEMPERATURE
·20
0
20
40
60
80
100
JUNCTION TEMPERATURE ('IC)
120
FIGURE 21. GATE DRIVE RISE TIME T R VB TEMPERATURE
6·49
HIP4081
Typical Performance Curves
Voo =Vee =VAHB =VBHB =12V, Vss = VALS =VBlS = VAHS =VSHS
lOOK and TA = +25°C, Unless Otherwise Specified
=OV, RHOEl =RLOEl =
1500
6.0
:;-
S
~
w
w
~
!j
!j
~
...~::.
...
1250
~
5.5
1000
w
tot
5.0
~
...0
==
oJ
9
qz
a:
::.
...
~
i'-.
V
750 I- -400 C
r
500
L-
L
I- +250 C'"
V
V
/'"
lL
V
L.
r
V
0
250 I- +75 C ~ ,......
r+1250C
4.0 L-L-L-L-L-L.....JL.....JL.....JL-JL-JL-JL-JL-JL-JL-J--I--I
-40
-20
o
20
40
60
80
100
120
.L.
L
lL
ooc-
I
o
6
8
JUNCTION TEMPERATURE ("C)
10
12
BIAS SUPPLY VOLTAGE
FIGURE 22. VLOEl.o VHDEl VOLTAGE vs TEMPERATURE
14
(~
FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE Vee - VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
1500
3.5
I
I-- -400C
S
1250 I-w
ooC
I--
,
:;-
~
...
"-
1"- '"
~ 1000
~
It
~
~
U
:.:
z
750
iii
500
250
o
rrrr-
1/
/
+25"C
+750 C
V
V
/
1.5
Q
1.0
~
/
w
!cCI
/'"
2.0
w
V
0.5
0.0
8
10
12
6
14
8
7
9
3.5
./
~ 3.0
...z
V
w 2.5
a:
a:
iii 1.5
w
~
Q
~CI
./
2.0
~
./
500
V
:('200
V
S
...
zw
100
50
a:
a: 20
::.
u
V
V
~
10
iii
5
~
2
w
!j
0.5
~oJ
~
0.5
0.2
0.0
7
8
8
10
11
12
13
12
13
14
15
16
FIGURE 25. PEAK PULLDOWN CURRENT 10 vs BIAS SUPPLY
VOLTAGE
1.0
6
11
10
VDO,VCC,VAHB,VBHB~)
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERTURE AT 100mA
:.:
z
~
~
BIAS SUPPLY VOLTAGE (V)
U
~
+125"C
6
::.
~
~
,. V
a:
a:
::.
w
tot
3.0
~
zw 2.5
14
15
0.1
16
',-"Ii
3,OOOpF
I,..;""
1\
V
'\
100pF
V
10-"""
/'
'""" V'
k-"'"',;\.,
'"......::V '" '"
'"
/'
L
V
V
/' V
VV
V
/'
I-""'"
~
L
V
~,""
./
./
2
VDO,VCC,VAHB,VBHB(~
FIGURE 26. PEAK PULLUP CURRENT 10+ vs BIAS SUPPLY
VOLTAGE
I
10,OOOpF :-,
5
10
20
50
100 200
500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 27. LOW VOLTAGE BIAS CURRENT leo (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE
LOAD CAPACITANCE
6-50
HIP4081
Typical Performance Curves
Voo
=Vcc =VAHB =V BHB =12V, Vss =VALS =VBLS =VAHS =V SHS =OV, RHOEL =RLOEL =
lOOK and TA = +25°C, Unlsss Otherwise Specified (Continued)
1000
...z~ 200
100
w
a:
a:
::>
SO
Ii:
20
~
10
>
w
5
w
...
."
V
120
fI'
~~
u
%
150
/'
500
~
V
I-'"
~ F--
~ r--
-.....
2
~
aov
r- : - 60V
-.....
r- t--
30
1-40V
-20V
2
5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)
o
500 1000
kC
/'
100
150
200
HDEULDEL RESISTANCE (kil)
50
10
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
V
./
V
L
250
FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE
HIP4081 Power-up Application Information
The HIP4081 H-Bridge Driver Ie requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4081 has four inputs, one for each output. Outputs
AlO and BlO are directly controlled by input AU and BU.
By holding AU and Bu low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 30. As the VoolVcc supply ramps from zero
up, the DIS voltage is below its input threshold of 1.7V due
to the R1/R2 resistor divider. When VoolVcc exceeds
approximately 9V to 10V, DIS becomes greater than the
input threshold and the chip disables all outputs. It is critical
that AU and Bu be held low prior to DIS reaching its threshold level of 1.7V while VoolV cc is ramping up, so that shoot
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
..J
..J
:I
u.
FIGURE 30.
Veo
1.. f" ,,~'"
AU, BUt
12V, ANAL VALUE
8.5V TO 10.5V (ASSUMES 5% RESISTORS)
., . . . . . UIlIl . . . . . . .I I I I . . . . . . . . . ..
!
--~-----------------------
DIS
1,,~
",
'1.7V
t1
TIMING DIAGRAM FOR FIGURE 30
NOTE:
1. AU and/or BU may be high after tl, whereupon the ENABLE pin
may also be brought high.
2. Another product, HIP4081 A, incorporates undervoltage circuitry
which eliminates the need for the above power up circuitry.
6-51
I
IN2 IN1
POWER SECTION
+12V
r--------1~_-___10 B+
CONTROL LOGIC
SECTION
1
R29~ ?
~C6
L--~--,I. I I HIP~1
+
II> -
-
DRIVER SECTION
~~-
SHB
~2 HENlBHI
.--_+-+___
R21
CR2
C4
I
~
BHOi20
R22
L....._ _--'3'1 DIS
>~~--~
L....._ _ _ _~SOUT~U
6
CD4069UB
0
AO
+--Xx-;x , 0
BO
xxxx
4 VSS
O-~~+--;
IN~AU
7 IN-IAHI
.--------------:1
::s
8 HDEL
.------::1
~
R33 I
R34
9 LDEL
10,AHB
i
R24
.....
eR1
cw
CD4069UB
CW
l....--jC3
CS.f.
ALS
15K
TO DIS PIN
3.3K
COM
BLS
NOTE:
DEVICE CD4069US PIN 7 = COM, PIN 14 = +12V.
CD4069UB
FIGURE 31. HIP4081 EVALUATION BOARD SCHEMATIC
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FIGURE 32. HIP4081 EVALUATION BOARD SILKSCREEN
0
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HIP4081A
80V/2.5A Peak, High Frequency
Full Bridge FET Driver
PRELIMINARY
April 1994
Features
Description
• Independently Drives 4 N-Channel FET In Half Bridge
or Full Bridge Configurations
The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency Class D audio amplifiers. and
power supplies.
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz In Free Air at +50 oC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chlp Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels
For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum "on-time"
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion. resulting
in rapid, precise control of the driven load.
• Very Low Power Consumption
• Undervoltage Protection
Applications
A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle
wave and to facilitate "hysteresis mode" switching.
• Medium/large Voice Coil Motors
• Full Bridge Power Supplies
Ordering Information
• Class D Audio Power Amplifiers
• High Performance Motor Controls
PART
NUMBER
• Noise Cancellation Systems
TEMP RANGE
PACKAGE
• Battery Powered Vehicles
HIP4081 AlP
-40·C to +85°C 20 Lead Plastic DIP
• Peripherals
HIP4081 AlB
-400C to +85°C 20 Lead Plastic SOIC (W)
• U.P.S.
Pinout
Application Block Diagram
80V
HIP4081A (PDIP. SOIC)
TOP VIEW
!
BHO
L
BHS
BlO
BlS
lDEl ~
AHB 10
~
Voo
BHI
Vee
AlS
BU
HIP4081A
ALO
AU
AHS
AHO
1AHI
BlO
AlO
I
:~I
T
GND
GND
CAUTION: These devices are sensftive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6-54
File Number
3659.1
HIP4081A
Functional Block Diagram
(112 HIP4081A)
HIGH VOLTAGE BUS S BOVDC
AHB
~----~----+---,
AHO
CBS
AHS
Voo
TO Voo (PIN 16)
DBS
ALO
=
+12VDC
BIAS
SUPPLY
ALS
Typical Application (PWM Mode Switching)
BOV
J
J
L
w
g
a:III
..J
..J
::::l
IL
PWM
INPUT
GND
TO OPTIONAL
CURRENT CONTROLLER
~--+---<
GND
6-55
Specifications HIP4081 A
Absolute Maximum and Thermal Ratings
Supply Voltage, Voo and Vee ....••••••....•...•• -o.3V to 16V
Logic 1/0 Voltages ....................... -0.3V to Voo +O.3V
Voltage on AHS, BHS .•..•••..•••••••• -6.0V (Transient) to 9SV
Voltage on ALS, BLS ..•.•.. -2.0V (Transient) to +2.0V (lI'ansient)
Voltage on AHB, BHB ..•..•... VAHS, SHS -o.3V to VAHS. SHS +16V,
or 9SV, whichever is less
Voltage on ALO, BLO ••••••..•••••. VALS. SLS -0.3V to Vee +0.3V
Voltage on AHO, BHO •••••.•• VAHS. BHS -0.3V to VAHS. SHS +0.3V
Input Current, HDEL and LDEL •.••••••..•••..•.• -SmA to OmA
Phase Slew Rate •....•........•..•...•••......•••. 20v/ns
NOTE: All voltages are relative to pin 4, VSSo unless otherwise specified.
Storage Temperature Range •••••......•.••.•. -6SoC to +150°C
Operating Max. Junction Temperature ..•••.•••••.••.•• +12SoC
Lead Temperature (Soldering lOs)
(For sOle - Lead TIps Only) ....................... +3000C
Thermal Resistance, Junction-Ambient
SOIC Package .................................. 8SoCm
DIP Package ••••••.••...••••....•••.•..•.••••.. 7SoCm
Maximum Power Dissipation at +8SoC
SOIC Package ................................. .470mW
DIP Package ................................... S30mW
CAUTION: Stresses above those listed In -Absolute Maximum Ratings· may cause permanent damage to the devlcB. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage, Voo and Vee •••••..••..••••••.. +9.SV to +15V
Voltage on ALS, BLS ..•••.•..•••.•••••••.••.• -1.0V to +1.0V
Voltage on AHS, BHS .••••••.•••...•••.......•... -1 V to 80V
Electrical Specifications
Voltage on AHB, BHB • • • • • • . . •• VAHS. SHS +SV to VAHS, SHS + 15V
Input Current, HDEL and LDEL. ....•.•...••.•. -SooIlA to -SOIlA
Operating Ambient Temperature Range •.•.••.••. -4O"C to +85°C
voo = vee = VAHS = VSHS = 12V, vss = VALS = VSLS = v AHS = VSHS = OV, RHOEL = RLOEL = lOOK and
TA = +25°C, Unless Otherwise Specified
TJ
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TJs =-400C
TO+125°C
=+25°C
TYP MAX MIN MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
Voo Quiescent Current
Voo Operating Current
100
All inputs = OV
8.5
10.S 14.S
7.5
14.S
rnA
9.5
12.5
8.5
IS.S
mA
1000
Outputs switching f = 500kHz
Vee Quiescent Current
Icc
All Inputs = OV, IALO = ISLO = 0
-
0.1
10
-
20
IlA
Vee Operating Current
leeo
f = SOOkHz, No Load
1
1.25
2.0
0.8
3
rnA
All Inputs = OV, IAHO = 'SHO = 0
Voo = Vee = VAHS = VSHB = 10V
-50
-30
-11
-60
-10
IlA
f = SookHz, No Load
0.6
1.2
1.5
0.5
1.9
mA
-
0.02
1.0
-
10
IlA
II.S
12.6
14.0
10.5
14.S
V
1.0
V
AHB, BHB Quiescent Current Qpump Output Current
IAHS,lsHS
AHB, BHB Operating Current
IAHBO, IsHBO
AHS, BHS, AHB, BHB Leakage Current
IHLK
AHB-AHS, BHB-BHS Qpump
Output Voltage
VAHS = VSHS = VAHS = VSHS = 9SV
VAHS-VAHS
VSHS-VSHS
IAHS = IAHS = 0, No Load
Low Level Input Voltage
VIL
Full Operating Conditions
-
High Level Input Voltage
VIH
Full Operating Conditions
2.5
-
-
35
15.5
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS
Input Voltage Hysteresis
Low Level Input Current
IlL
VIN = OV, Full Operating Conditions
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-130 -100
-
0.8
2.7
-
V
-
-
-
mV
-75
-135
-65
IlA
-1
-
+1
-10
+10
IlA
4.9
5.1
5.3
4.8
5.4
V
1.0
0.5
1.1
V
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage
VHOEL' VLDEL IHOEL = ILDEL = -1001lA
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND SHO
Low Level Output Voltage
VOL
lOUT = 100mA
0.7
0.85
High Level Output Voltage
Vee-VOH
lOUT = -100mA
0.8
0.9S
1.1
0.5
1.2
V
Peak Pullup Current
10+
VOUT=OV
1.7
2.6
3.8
1.4
4.1
A
Peak Pulldown Current
10-
VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
6-56
Specifications HIP4081A
Electrical Specifications
voo = vee = VAHB = VBHB = 12V, Vss = VALS = VBLS = VAHS = VBHS = OV, RHOEL = RLOEL = 100K and
TA =+25°C, Unless Otherwise Specified (Continued)
TJ = +2SoC
TJs=-40oC
TO+12SoC
MIN
TYP MAX MIN MAX UNITS
Undervoltage, Rising Threshold
UV+
8.1
8.8
9.4
8.0
9.5
V
Undervoltage, Falling Threshold
UV-
7.6
8.3
8.9
7.5
9.0
V
Undervoltage, Hysteresis
HYS
0.25
0.4
0.65
0.2
0.7
V
PARAMETER
SYMBOL
Switching Specifications
TEST CONDITIONS
voo = vee = VAHB = VBHB = 12V, vss = v ALS = v BLS = VAHS = VBHS = OV, RHDEL = RLOEL = 10K,
CL =1000pF.
TJS = -40°C
TO +12SoC
TJ = +2SoC
MAX UNITS
MIN
TYP
MAX
MIN
TLPHL
-
30
60
-
80
ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL
-
35
70
-
90
ns
lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)
TLPLH
RHDEL = RLDEL = 10K
-
45
70
-
90
ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
RHDEL = RLDEL = 10K
-
60
90
-
110
ns
PARAMETER
SYMBOL
lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)
TEST CONDITIONS
Rise Time
TR
25
-
35
ns
TF
-
10
Fall Time
10
25
-
35
ns
Turn-on Input Pulse Width
TPWIN.QN
RHOEL = RLDEL = 10K
50
50
-
ns
Turn-off Input Pulse Width
40
-
ns
ns
30
-
TPWIN.QFF
RHOEL = RLDEL = 10K
40
-
Turn-on Output Pulse Width
TpWOUT.QN
RHOEL = RLDEL = 10K
40
-
Turn-off Output Pulse Width
TPWOUT.QFF
RHOEL = RLDEL = 10K
30
-
-
40
ns
Disable Turn-off Propagation Delay
(DIS - lower Outputs)
TDISLOW
-
45
75
-
95
ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TOISHIGH
-
55
85
-
105
ns
Disable to lower Turn-on Propagation Delay
(DIS - ALO and BlO)
TDLPLH
-
35
70
-
90
ns
Refresh Pulse Width (AlO and BlO)
TREF.PW
240
380
500
200
600
ns
TUEN
-
335
500
-
550
ns
Disable to Upper Enable (DIS - AHO and BHO)
TRUTH TABLE
OUTPUT
INPUT
AHI,BHI
UN
X
X
1
X
0
0
X
X
ALI, Blf
DIS
AlO,BlO
X
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
X
0
0
NOTE: X signifies that input ean be either a -1" or -0".
6-57
AHO,BHO
w
g
a:ID
....I
....I
~
HIP4081A
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
BHI
B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels 01 OV to 15V (no greater than Voo). An Internall001lA
pull-up to Voo will hold BHI high, so no connection Is required if high-side and low-side outputs are to be controlled by the low-side input.
3
DIS
DISable Input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
OV to 15V (no greater than Voo ). An Internall001lA pull-up to Voo will hold DIS high if this pin is not driven.
4
Vss
Chip negative supply, generally will be ground.
5
BLI
B Low-side Input. Logic level input that controls BLO driver (Pin 18).11 BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, wtth dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level Input. The pin can be driven by signal levels
of OV to 15V (no greater than Voo ). An internall001lA pull-up to Voo will hold BLI high if this pin is not driven.
6
ALI
A Low-side Input. Logic level input that controls ALO driver (Pin 13). II AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level Input. The pin can be driven by signal levels
of OV to 15V (no greater than Voo ). An internal1001lA pull-up to Voo will hold ALI high if this pin is not driven.
7
AHI
A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level Input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An Internall00IlA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.
8
HDEL
High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage Is approximately 5.1 V.
9
LDEL
Low-side turn-on DELay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1 V.
10
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacttor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
12
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13
ALO
A Low-side Output. Connect to gate of A Low-side power MOSFET.
14
ALS
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15
Vee
Positive supply to gate drivers. Must be same potential as Voe (Pin 16). Connect to anodes of two bootstrap
diodes.
16
Veo
Positive supply to lower gate drivers. Must be same potential as Vee (Pin 15). De-couple this pin to Vss (Pin 4).
17
BLS
B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18
BLO
B Low-side Output. Connect to gate of B Low-side power MOSFET.
19
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
6-58
HIP4081A
Timing Diagrams
x " A OR B, A AND B HALVES OF BRIDGE CONTROllER ARE INDEPENDENT
---
--
....
TLPHL
o
THPHL
I--
xu
\
/
XHI
/
XLO
I
XHO
--- '1--
---
£
--
TLPLH
l-TF
(10%-90%)
FIGURE 1. INDEPENDENT MODE
UN" DIS ,,0
-----------------------------------------------------\~----II
xu
I
\
I
\
w
XHI = HI OR NOT CONNECTED
(J
~
8.0
~
CI.
CI.
:::>
6.0
In
II
~
"
~
10.5
!z
10.0
G
8.5
~
i-"~
~~
CI.
~
II
Q.O
..........
8
10
12
VOO SUPPLY VOLTAGE (V)
14
~~
..........
o
100 200 300 400 500 600 700 900 800 1000
SWITCHING FREQUENCY (kHz)
FIGURE 5. 1000 , NO-LOAD 100 SUPPLY CURRENT vs
FREQUENCY (kHz)
FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE
5.0
C
30.0
+1250 C
.§.
...z
C
25.0
w
II:
II:
:::> 20.0
(J
C
".....,
iii 15.0
~
CI.
CI.
CJ
Z
!z
oOC
:::>
-400 C
./
o
"
-
..........
1/
V k.::
In
.§
1.0
0.0
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
.......
...0lI:l IiiiiJII
~ iIII""""
o 100 200
""""
300 400
""""
:::>
~
'-,. K
./
~
"
./
5.0
0.0
+250 C
~
CI. 2.0
./
10.0
...9
+75OC
4.0
~ 3.0
(J
~
/
CI.
CI.
:::>
70
.s.
425
i
..
"-
0
"'
-25
50
fii
r---.....
o
...0~
...
.
............ r---
40
II:
30
20
25
50
75
100
125 150
-40
JUNCTION TEMPERATURE rC)
-20
o
20
40
60
80
100
JUNCTION TEMPERATURE rC)
120
FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGA·
TION DELAYvs TEMPERATURE
FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERA·
TURE
6-61
HIP4081A
Typical Performance Curves
!
~
=
=
70
70
....
40
-I-
l- I- i"""
30
--
....
~
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE <"C)
20
-40
1~
..
70
.s.
~
60
40
a:
.....
20
-40
-20
-
I- ~
.... i-
0
20
40
60
80
JUNCTION TEMPERATURE (OC)
-
~
~
80
80
JUNCTION TEMPERATURE (OC)
100
1~
70
....I-
60
100
~
40
0
...
a:
30
20
-40
1~
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE <"C)
120
FIGURE 19. LOWER TURN-ON PROPAGATION DELAYT LPLHvS
TEMPERATURE
13.5 r-,--,--,--,--,--,--.--.---r--r-,--,---r--r--r-.,-,
13.5 r-r-r-,--,--,--,--,--,--.--.--.--.--.---r--r--r--,
! 1~5
"1~5r-r-t-t-t-+-+-+-+-+-+-+-+-+-+-+-+-~
.s.
w
r-+-+-+-+-+-+-+-+-+-++~-r-r-r-r,
w
~ 11.51-1-1-1-1-1-1-+-+-+-+-+-+-+++-r~
11.5 r-t-t-+-+-+-+-+-+-+-+-+-+-+-+-+-+~
w
~
l!!
w
~ 10.5
CI SI.5m-mm=mmm
8.Jd= I: I I I I I I I I I I I I I I I
~
o
~
FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
~
....
-20
:z: 50
0
~
:::E
I- I-r-"
~
z 50
30
-- -
.... ....
80
Q
...
=OV, RHDEL =RLDEL =
FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH VS
TEMPERATURE
80
~
0
=
30
FIGURE 16. UPPER TURN-OFF PROPAGATION DELAYTHPHL
vs TEMPERATURE
.s.
~
w
=
-
20
-40
=
~
60
~ 50
..
=
80
Ii
...a:
=
80
~
~
=
VDD Vee VAHB VBHB 12V, Vss VALS VBLS VAHS VBHS
10K and TA = +250 C, Unless Otherwise Specified (Continued)
~-+-r~+-~~-+~~+-~-+-r~
-40
-~
0
20
40
60
80
100
JUNCTION TEMPERATURE (OC)
120
~
a:
~
10.5
r-t-t-t-+-+-+-+-+-+-+++~~-r-r~
9.5I-HHHH-l-l-+-+-+-+-+-+-+-+-+-1
1I I I I I I I I I I I I I I I I I
8.5
-40
_
0
~
~
60
80
100
1~
JUNCTION TEMPERATURE <"C)
FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE
FIGURE 20. GATE DRIVE FALL TIME TF VB TEMPERATURE
6-62
HIP4081A
Typical Performance Curves
Voo = Vee = VAHB = VBHB = l2V, Vss = VAJ,.S = VBLS = VAHS = VBHS = OV, RHOEL = RLOEL =
lOOK and TA = +25°C, Unless Otherwise Specified
1500
6.0
:;-
.sw 1250
~
~
5 1000
w
C! 5.5
i:!i
:..J
>
§!
....
::>
Do.
!;;:
~
5.0
:!:
""
~
L
750
-
500
oOC
+250c
12
10
.s
1250
w
g
w 2.5
a:
a:
>
::>
0
w
:.:
z
750
~
-
-40 oC
""
500 -
oOC
-
+250 C
250 -
+750 C
-
+12S oC
L
L
L
// //
~
.,...
// /
w 1.0
£C
C!
..J
..J
ID
!;;:
0.5
~
0.0
12
6
14
7
8
3.5
3.0
....
ffi
a:
a:
o
2.5
.., V
2.0
:.:
z
iii 1.5
~
~w
V
1.0
..,.,
500
. /V
-" V
./ ,/
V
""
~
-"
V
,/
/
V
'-...,
'-..., 0,..
/'
,/
V
V
'-...,
::>
0
11
14
I
3,000pF
z
w
10
13
10,000pF _
.s
100
....
-c
g
12
Veo, Vee. VAHB, VBHB (V)
"
7
11
FIGURE 25. PEAK PUlLDOWN CURRENT 10 vs BIAS SUPPLY
VOLTAGE
V V
6
10
G
BIAS SUPPLY VOLTAGE (V)
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERTURE AT 100mA
::>
w
g
0
//
/
10
g
......
..,.,. V
.,... V
2.0
iii
w 1.5
L
.,... V
3.0
....
z
5~ 1000
o
-
3.5
1500
~
14
FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE Vee· VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
:;-
~a:
V
BIAS SUPPLY VOLTAGE (V)
FIGURE 22. VLOEL' VHOEL VOLTAGE vs TEMPERATURE
!;;:
V/
+1250 C-
JUNCTION TEMPERATURE ("C)
Ii;
5
+75"C' /
-
o
// /
//
-40oC~
_
a:
250 ~
4.0 '--'--'--.l-.l--'--'--'--'--'-...L....L.-L....L....L.-L-L.....J
-40
·20
o
~
~
~
~
100
1~
~
L
w
""
10
20
SO
100 200
500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 27. LOW VOLTAGE BIAS CURRENT 100 (LESS QUIESCENT COMPOENT) vs FREQUENCY AND GATE
LOAD CAPACITANCE
6·63
HIP4081A
Typical Performance Curves
=
=
=
=
=
=
1000
...z~ 200
w
a:
a:
0
t:
:E
Ul
.:.
w
100
50
10
./
V
>
~
20
=
=OV, RHOEl =RlOEl =
/
500
::>
=
Voo Vee VAHB VSHS 12V, Vss VM.S VSLS VAHS VSHS
1OOK and TA = +25°C, Unless Otherwise Specified (Continued)
V
10
20
50
./
100
./
200
500
1000
SWITCHING FREQUENCY (kHz)
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT VI FREQUENCY AND BUS VOLTAGE
9.0
-
:E
~
I"'""
8.8
ui
~
g
I
-
Uv+
i'-.~
~
8.6
~
......
-
::>
Ul
Ul
.:
8.4
iii
UV-
--r-- I"- r.......~
8.2
50
o
25
25
n
~
100
125
1~
TEMPERATURE ("C)
FIGURE 29. UNDERVOLTAGE LOCKOUT VI TEMPERATURE
150
120
V
L
~
./
30
:/
/V
50
100
150
200
HDEULDEL RESISTANCE (kn)
250
FIGURE 30. MINIMUM DEAD-TIME VI DEL RESISTANCE
6-64
IN2 INl
POWER SEcnON
+12V
o
CONTROL LOGIC
SEcnON
oa~,____~
..,;_IL i
~------~~~--~o~
DRIVER SECTION
CR2
C6
1=
HIP4080AI81A
Ul
C4
jjij0120
llBHB
2 HENlBHI
Ir---t-tL---;]3 DIS
JMPR2IN~AU
~
CD4069UB
AO
4 Vss
5 OUTIBU
L---------~6~IN~AU
BO
7 IN-IAHI
11r-------Ala HDEL
3:
~
~ LDEL
~
!.!
-
AHB
2
~
CRl
CD4069UB
C3
'---II
cs-!-
COM
ALS
BLS
NOTES:
DEVICE CD4069UB PIN 7 .. COM, PIt! 14 .. +12V.
CD4069UB
FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC
$
m
~
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
$
GND
@
@
•••••••••
••••••
••••••
••••••
•••••
••••
•••
•••
••••
•••••
••
••
••
•
••
••
••
•
••
••
••
•
@
••
••
••
•
•••
•••
•
•••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
tJ
...'.'''.. 1]
@
~
f"'tl 8!.. ~
••
..O~
13
••
••
•• &(] ~DDOO+:H~
••
••
••
•
1] ......
•• ••
•• ••
•• ••
•• ••
•• ••
•• ••
••
• •
••• •••
•• ••
••
@~
$
+12V
a::
•••
to-
DO
••
ALS
ALO
3
~ •
.JMPR~
•
!!: •
1]~
.JMPR1.
~
••
I @.
•
•• _
•
•
•• o@.
•
• • IN2 @ .
•
••
••
..
DIS
U2
.JMPRle
.JMPR4e.
•
~
R21
•
:: ..... !l: : ~ O~ ~D
e@
••
• • BLS@
R33
RM
a:
••
-
@
g
••
...L@
.
@
@
$
@
FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN
@
~
~
0
1:1
0
!l
:i
Q4
Q2
• i i[][]
C;~--=- @•
i.
••
••
~
~
BHO.c:::Je
R24
BLO .c:::Je
%. .0.
•
•
U
@
Q3
Q1
R22
•
{fj
COM
CB
£J
CR2
• •
@~
B+
@
@
@
~
~
....
~
@
D~ m
:!:
*
HIP4082
80Vl1.25A Peak Current
Full Bridge FET Driver
ADVANCE INFORMATION
April 1994
Features
Description
• Independently Drives 4 N-Channel FET In Half Bridge
or Full Bridge Configurations
The HIP4082 is a medium frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 16 lead plastic
sOle and DIP packages.
• Bootstrap Supply Max Voltage to 9SVDC
• Drives 1000pF Load In Free Air at SOoC with Rise and
Fall Times of Typically 1Sns
• User-Programmable Dead Time (0.1 to 4.Sus)
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with SV to 1SV
Logic Levels
• Shoot-Through Protection
• Undervoltage Protection
Applications
Specifically targeted for PWM motor control and UPS applications, bridge based designs are made simple and flexible w~h
the HIP4082 Full Bridge Driver. With operation up to SOV, the
device is best suited to applications of moderate power levels.
Similar to the HIP4081, it has a flexible input protocol for
driving every possible switch combination except those
which would cause a shoot-through condition. The HIP4082
has reduced drive current compared to the HIP4081 (1.25 vs
2.5A) and a much wider range of programmable dead times
(0.1 to 4.5us) making it ideal for switching frequencies in the
20kHz to 200kHz range. Unlike the HIP4081 the HIP4082
does not contain an internal charge pump.
This set of features and specifications is optimized for applications where size and cost are important. For applications
needing higher drive capability the HIP4080A and HIP4081A
are recommended.
• UPS Systems
• DC Motor Controls
• Full Bridge Power Supplies
Ordering Information
• Class D Audio Power Amplifiers
• Noise Cancellation Systems
PART NUMBER
• Battery Powered Vehicles
• Peripherals
• MedlumlLarge Voice Coli Motors
Pinout
TEMPERATURE
RANGE
PACKAGE
HIP4082IP
-4O"C to +8SoC
16 Lead Plastic DIP
HIP4082IB
-4O"C to +85°C
16 Lead Plastic SOIC (N)
Applicationn Block Diagram
IOV
HIP4082 (PDIP, SOIC)
TOP VIEW
1
L
BHI
BU
HIP4082
t-----+-------t-----'
AU
ALO
AHI
AHs~----4_------_+----~
AHO~----4_-------_+-----~
GND
GND
CAUTION: These d9\lices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
6·67
File Number
3676
HIP4082
Functional Block Diagram
r------------------------------------------,
Voo
Vss
6~------------------------------------------~
Typical Application (PWM Mode Switching)
80V
1
TO OPTIONAL
CURRENT CONTROLLER OR
OVERCURRENT LATCH
GND
6-68
L
Specifications HIP4082
Absolute Maximum and Thermal Ratings
Thermal Information
Supply Voltage, Voo .•..•••.....••...••••..•..• -o.3V to 16V
Logic VO Voltages .•••...••••••••••••.••. -0.3V to Voo +0.3V
Vollage on AHS, BHS. • . . . . • . . . • • . • • .. -6.0V (Transient) to sav
Voltage on AHB, BHB ........ VAHS. VBHS -o.3V to VAHS. BHS +16V,
or 95V, whichever Is less
Voltage on ALO, BLO .••.••••..•••••••. Vss -0.3V to Vcc +O.3V
Voltage on AHO, BHO ..•••• VAH$, VBHS -0.3V to VAHB• VBHB +O.3V
Input Current, DEL .....•............••••.••••• -5mA to OrnA
Phase Slew Rate •••...•.•......•.....•••...••..... 20v/ns
Storage Temperature Range .••..••••.•.••.••. -65°C to + 1SOoC
Operating Max. Junction Temperature .••••••.•...•••.. +125°C
Lead Temperature (Soldering 10s) •••••••••.••.•••••.• +3000C
(For SOIC - Lead Tips Only)
Thermal Resistance, Junction-Ambient
SOIC Package ••.••••.•••....•.••.•••••••••..•• 1500c/w
DIP Package •••••••••••••.•••••.••••.•.••••.••. 90oC/W
Maximum Power Dissipation at +85°C
SOIC Package •••••.•.••••••.•...••••...•••••••• 266mW
DIP Package ..•.•••....•.•.•.••..........•..... 445mW
CAUTION: StrBSses above those listed in -Absolute Maximum Ratings' may cause permanent damage to the device. This is a strBSs only rating and operation
of the device at these or any other conditions above those Indicated in the operational sections of this specification is not Implied.
Operating Conditions
Supply Voltage, VDO ...••...........••.....••. +SV to +15V
Voltage on Vss .•.....•.•..........••....••.• -1.0V to + 1.0V
Voltage on AHS, BHS •.••••••••.••.....•.••....•. -1V to SOV
Electrical Specifications
Voltage on AHB, BHB ••..•••. VAHS, VBHS +7V to VAHS. VBHS +15V
Input Current, DEL ......................... -4rnA to -1 OCl\lA
Operating Ambient Temperature Range ••••••.••. -40"C to +85°C
voo = v AHB = VBHB = 12V, Vss = v AHS = v BHS = OV, ROEl = 100K
TJs=-400C
TO+125°C
T J = +2S0C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX MIN MAX UNITS
SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDO Quiescent Current
Voo Operating Current
100
All inputs = OV
-
2.25
-
-
1000
Outputs Switching f = 50kHz,
-
4.25
-
-
IAHBl,lSHBl
AHI =BHI =OV
AHB, BHB On Quiescent Current
IAHBH' ISHBH
AHI = BHI = Voo
-
AHB, BHB Operating Current
IAHBO,IBHBO
f = 50kHz, Cl=1000pF
-
AHB, BHB Off Quiescent Current
Voo Rising Undervoltage Threshold
Voo Falling Undervoltage Threshold
VDDUV+
UV-
Undervoltage Hysteresis
UVHYS
AHB, BHB Undervoltage Threshold
VHBUV
-
7.5
5.5
-
145
1.0
O.S
7.0
0.5
-
rnA
-
rnA
IIA
rnA
-
rnA
-
V
-
-
V
-
V
-
V
INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Vollage
V1l
Full Operating Conditions
-
-
1.0
-
O.S
V
High Level Input Voltage
VIH
Full Operating Conditions
2.5
35
-
-
V
-
-
2.7
mV
Low Level Input Current
III
VIN = OV, Full Operating Conditions
-130 -100
-75
-135
-65
IIA
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-1
-
+1
-10
+10
IIA
IOEl = -1 001lA
-
4.4
-
-
-
uS
VOL
lOUT = 50mA
0.7
0.S5
1.0
0.5
1.1
V
Vee-VoH
IOUT=-50mA
O.S
.95
1.1
0.5
1.2
V
VOUT=OV
-
1.3
-
-
-
A
VOUT = 12V
-
1.2
-
-
-
A
Input Vo~age Hysteresis
TURN-ON DELAY PIN DEL
Dead Time
TOEAO
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Vo~age
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
10+
10-
6-69
Specifications HIP4082
TJS= "",Ooc
TO+125°C
TJ =+2SOC
PARAMETER
TEST CONDITIONS
SYMBOL
MIN
TVP
MAX
MIN
MAX
UNITS
lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)
TLPHl
-
25
-
-
-
ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHl
-
30
-
-
-
ns
lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)
TLPLH
ROEl = 10K
-
35
-
-
-
ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
ROEl = 10K
-
50
-
-
-
ns
-
-
-
50
-
Rise lime
TR
Fall lime
TF
-
15
15
Turn-on Input Pulse Width
Tpw1N'()N
ROEl = 10K
50
-
Turn-off Input Pulse Width
TPW1N'()FF
ROEl = 10K
50
-
ns
ns
ns
Disable Turn-oil Propagation Delay
(DIS - lower Outputs)
TOISlOW
-
50
-
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TOISHIGH
-
60
-
-
-
ns
Disable to Lower Turn-on Propagation Delay
(DIS - AlO & BlO)
TOLPlH
-
50
-
-
-
ns
Disable to Upper Enable (DIS - AHO & BHO)
TOHPlH
-
620
-
ns
TREF•PW
-
580
-
-
Refresh Pulse Width (AlO & BLO)
-
-
ns
ns
-
-
50
ns
NOTE:
1. All vollages are relative to pin 6, VSS, unless otherwise specified.
TRUTH TABLE
INPUT
OUTPUT
ALI, Bli
AHI,BHI
VDDUV
VHBUV
DIS
AlO,BlO
AHO,BHO
X
X
X
X
1
0
0
X
X
1
X
X
0
0
0
X
0
1
0
0
0
1
X
0
X
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
NOTE: X signifies that input can be either a "I" or "0".
6-70
HIP4082
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin.
2
BHI
B High-side Input. logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.
3
BLI
B low-side Input. logic level input that controls BlO driver (Pin 14). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BlO and BHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of OV
to 15V (no greater than VDO). An internal 100llA pull-up to Voo will hold BLI high if this pin is not driven.
4
ALI
A low-side Input. logic level input that controls AlO driver (Pin 13). If AHI (Pin 7) Is driven high or not connected externally then ALI controls both AlO and AHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of OV
to 15V (no greater than Voo ). An internal 1OOIlA pull-up to Voo will hold ALI high if this pin is not driven.
5
DEL
Turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the dead time between
drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. The voltage across the DEL resistor Is approximately Voo -2V.
6
Vss
Chip negative supply, generally will be ground.
7
AHI
A High-side Input. logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI
high level Input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.
8
DIS
DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other Inputs. When DIS is taken low the outputs are controlled by the other Inputs. The pin can be driven by signal
levels of OV to 15V (no greater than VOO ). An internal 1OOIlA pull-up to Voo will hold DIS high if this pin is not
driven.
9
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin.
10
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
11
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
12
Voo
Positive supply to control logic and lower gate drivers. De-couple this pin to Vss (Pin 6).
13
AlO
A low-side Output. Connect to gate of A low-side power MOSFET.
14
BlO
B low-side Output. Connect to gate of B low-side power MOSFET.
15
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
16
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
6-71
HIP4082
Timing Diagrams
X. A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
-- --
-- -TLPHL
OIS.0
.ndUV
,
xu ~
,
/
XHI
/
/
XLO
XHO
--
I
--
'1--
-4-
I--
TLPLH
-l-
FIGURE 1. INDEPENDENT MODE
OIS.0----------------------------------------------------------------------1'
\""'---,
\""'---,
end:~ _ _ _"'\\"'_ _ _
XHI. HI OR NOT CONNECTED
\~---,'
XLO
XHO _ _ _ _ _ _,
\'-_ _..."
\""'-----,
\"-_ _...,1
\'-__--1'
'-
FIGURE 2. BISTATE MODE
TDLPLH
TOIS
-+__~--------~~------~--'
XU ____
XHI
XLO
XHO
----I-JI
--~I----TDH-Pl.H-::::::"-.j1
\~----------------------------FIGURE 3. DISABLE FUNCTION
6-72
INTELLIGEN
POWERICs
7
REGULATORS/POWER SUPPLIES
PAGE
REGULATORS/POWER SUPPUES SELECTION GUIDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2
REGULATORSIPOWER SUPPUES DATA SHEETS
CA723, CA723C
Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA
Without External Pass Transistors .........................................•
7-3
CA 1523
Voltage Regulator Control Circuit for Variable Switching Regulator ................ .
7-11
CA1524, CA2524,
CA3524
Regulating Pulse Width Modulator ...............................•..........
7-16
CA3085, CA3085A, Positive Voltage Regulators from 1.7V to 46Vat Currents Up to 100mA ............ .
CA3085B
7-31
CA3277
Dual 5V Regulator with Serial Data Buffer Interface for Microcontroller Applications ....
7-39
HIP5060
Power ControllC Single Chip Power Supply ...............••.....•............
7-47
HIP5061
7A, High Efficiency Current Mode Controlled PWM Regulator .......•..........•..
7-53
HIP5062
Power ControllC Single Chip Dual Switching Power Supply ..................... .
7-73
HIP5063
Power ControllC Single Chip Power Supply ............................•...•..
7-BO
HIP5500
High Voltage IC Half Bridge Gate Driver ..................................... .
7-84
HIP5600
Thermally Protected High Voltage Linear Regulator ...............•.............
7-94
ICL7660
CMOS Voltage Converter ................................................ .
7-109
ICL7660S
Super Voltage Converter ................................................. .
7-118
ICL7662
CMOS Voltage Converter ....•..............................•.........•...
7-128
ICL7663S
CMOS Programmable Micropower Positive Voltage Regulator.................... .
7-138
ICL7665S
CMOS Micropower Over/Under Voltage Detector ...........................•••.
7-145
ICL7673
Automatic Battery Back-Up Switch .....................•.................•••
7-155
ICL8211, ICL8212
Programmable Voltage Detectors .............................•.............
7-161
7-1
(/)
CiS~
a:..1
08:
S~
w:=
::la:
eJIII
a:O
Q.
Regulators/Power Supplies Selection Guides
POWER SUPPLY CIRCUITS
DEVICE
CA723
DESCRIPTION
Linear Voltage Regulators
INPUT
VOLTAGE
RANGE
OUTPUT
VOLTAGE
RANGE
MAXIMUM
OUTPUT
CURRENT
9.SVt040V
2V to 37V
150mA
SWITCHING
FREQUENCY
QUIESCENT TEMPERATURE
CURRENT
RANGE
-
CA723C
~
CAl 523
Variable Internal Pulse Regulator for
Switch Mode Power Supplies
lWto ISV
S.9Vt07.SV
(Note 1)
SOmA
CAl 524
Pulse Width Modulators
BVt040V
4.BVto S.2V
(Note 1)
l00mA Max Rating br
Each 0u1pul Driver
200kHz
1kHz to 300kHz
3.5mA
-s5"C to +125°C
4.0mA
OOCto +7COC
34mA
OOCto +7COC
IOmA
-S5"C to +125°C
CA2S24
4.BVto S.2V
(Note 1)
OOCto +7COC
CA3S24
4.6VtoS.4V
(Note 1)
OOCto +70oC
CA308S
Linear Voltage Regulators
-
7.SVto 30V
1.8Vt026V
12mA to l00mA
CA308SA
7.SVIo40V
1.7V10 36V
12mA 10 l00mA
S.OmAat
VIN=40V
CA308SB
7.SVIo SOV
1.7Vto 46V
12mA to l00mA
7.OmAat
VIN = SOV
-
-4COC to +SSoC
lMHz Intarnal,
External Input
20mA
OOCto+85"C
2S0kHz
25mA
OOCto ..a5"c
Therm. Protect.
Two Power DMOS
Transistors SOV - SA
lMHz Latched
External Loop
2SmA
OOC 10 +8SoC
PowerDMOS
Transistor 60V - lOA
External Clock
14mA
OOC to +8SoC
30kHz 10 300kHz
7mA
-4COC to + IS00C
-
6SIlA
-4COC to +1oCOC
Therm. Protect.
10kHz to 35kHz
2001lA
-s5"c to +12SoC
1BOllA
-40°C to +BSoC
Microprocessor Interlace Controller
Dual-Fixed 5V Regulator, Overvoltage Shutdown, Thermal Shutdown,
Current Limited
6.2Vto 18V
0u1pull - Full Time Oulput 1 - l00mA
SV±0.2SV
Oulput 2 - l00mA
0u1pul2 - Switched
SV±O.2SV
HIPS060
Single Chip, Low Side Switch,
Current Controlled PWM
27Vto 4SV
Determined by
External Circuitry
PowerDMOS
Transistor SOV -lOA
HIPS081
7A Current Mode PWM RegulatorT0220 Type Package
IO.8V Min
14V Zener
Determined by
External Circuitry
PowerDMOS
Transistor SOV-7A
HIPS062
Single Chip, Dual Low Side Switch
Current Controlled PWM
26V10 42V
Determined by
External Circuitry
HIPS083
Basic Single Chip, Low Side Switch
Current Controlled PWM
10Vto 60V
Determined by
External Circuitry
HIPS500
Halt Bridge Power Supply Regulator
10V to ISV
SOOV Peak
2.M Peak
HIPSSOO
High Voltage Linear Regulator
SOVto 400V
1.2Vto 350V
30mA
ICL7660SM
Super Voltage Converter (Charge
Pump Type)
I.SVlo 12V
-1.SV to ± 22.8V
45rnA
ICL7660SC
ICL7662M
ICL7662C
Voltage Converter (Charge Pump
Type)
4.5Vto 20V
-4.SV to ±38.8V
10kHz
90mA
ICL76621
ICL7663SA
Linear Voltage Regulalors
1.6Vto 16V
1.3Vto 16V
ICL7663S
-55°C to +12SoC
SOOIlA
CA3277
ICL7660S1
4.SmAat
VIN= 30V
40mA- VOUT2
RoN - lOon -VOUT2
1801lA
OOCto +70oC
2S01lA
-s5"c to +12SoC
2001lA
OOCto +70oC
2001lA
-4COC to +8SoC
101lA
-25"C 10 +8SoC
121lA
OOCto +7COC
Note 1. Reference vottagas - Output Voltage limited by External DeVice
VOLTAGE MONITORING CIRCUITS
DEVICE
ICL7665SAI
ICL7665SAC
DESCRIPTION
CMOS Micropower Overl
Under Voltage Deteclor
VOLTAGE
RANGE
QUIESCENT
CURRENT
OUTPUT
CURRENT
INPUT TRIP
VOLTAGE
TEMPERATURE
RANGE
1.8Vlo 16V
101lA
2mA
1.3±2%
-4COC to +8SoC
ICL7665S1
ICL8211C
-40oC to +8SoC
1.3±8%
OOCIo +70oC
2.SVto 15V
5~J\
38mA
50mV
(Nole2)
·2S>C to .BSoC
Programmable Voltage
Detectors
1.8Vt030V
3S01lA
3mA
1.15+3.5%
1.15 - 6.0%
-55°C to + 125°C
9mA
1.15+3.S%
1.15-13%
-55°C to + 12SoC
ICL7673C
ICL8211M
COCto +70oC
1.3±2%
Autornatic Bctlc:"j Sac!H:p S'.v:tch
ICL766SSC
,,..,., "7C7."
1.3±8%
ICL8212M
ICL8212C
Note 2. Primary to Back-up Source Voltage Differential
7-2
o"Clo +70oC
o"Cto +70oC
COCIo +70oC
HARRIS
SEMICONDUCTOR
CA723, CA 723C
Voltage Regulators Adjustable from 2V to 37V at Output
Currents Up to 150mA Without External Pass Transistors
April 1994
Features
Description
• Up to 150mA Output Current
• Positive and Negative Voltage Regulation
• Regulation in Excess of 10A with Suitable Pass
Transistors
• Input and Output Short-Circuit Protection
• Load and Line Regulation ••••••••••••••••••• 0.03%
• Direct Replacement for 723 and 723C Industry Types
• Adjustable Output Voltage ••••••••••••••• 2V to 37V
The CA723 and CA723C are silicon monolithic Integrated circuits designed for service as voltage regulators at output voltages ranging from 2V to 37V at currents up to 150mA.
Applications
•
•
•
•
•
The CA723 and CA723C may be used with positive and negative power supplies in a wide variety of series. shunt. switching.
and floating regulator applications. They can provide regulation
at load currents greater than 150mA and In excess of lOA with
the use of suitable n-p-n or p-n-p extemal pass transistors.
Series and Shunt Voltage Regulator
Floating Regulator
Switching Voltage Regulator
High-Current Voltage Regulator
Temperature Controller
The CA723 and CA723C are supplied In the 10 lead TO-100
metal can(T suffix). and the 14 lead dual-In-line plastic package
(E suffix). and are direct replacements for Industry types LM723.
LM723C In packages with similar terminal arrangements.
Ordering Information
PART
TEMPERATURE
CA723E
-55°C to +125°C
CA723T
-55°C to +125°C
Each type Includes a temperature-compensated reference
amplifier. an error amplifier. a power series pass transistor. and
a current-limiting circuit. They also provide Independently accessible inputs for adjustable current limiting and remote shutdown
and. in addition. feature low standby current drain. low temperature drift. and high ripple rejection.
PACKAGE
14Lead Plastic DIP
10 Pin Metal Can
CA723CE
OOC to +700 C
14 Lead Plastic DI P
CA723CT
OOC to +7000
10 Pin Metal Can
Pinouts
Functional Block Diagram
CA723 (PDIP)
TOP VIEW
CURRENT
UMIT
CU~~~~
INJ~¥
12
4
;t-p~~REG
Vc
-
NON·lNV
INPUT
Vo REGULATED
OUTPUT
V-
CA723C (CAN)
TOP VIEW
CURRENT
UMITER
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-3
File Number
788.3
Specifications CA723, CA723C
Absolute Maximum Ratings
Operating Conditions
DC Supply Voltage •••••••••••••••••••••••.•••••••• ~ •• 40V
(Between v+ and v- Tennlnals)
Pulse Voltage for SOms
Pulse Width (Between V+ and V- Terminals) ••••••••••••• SOV
Differentiallnput-Output Voltage •••••..••••••••.•••••••• 40V
Differential Input Voltage
Between Inverting and Noninvertlng Inputs •..••..••••••••• ±5V
Between Nonlnverting Input and V- ••••.•••••••••••••••• BV
Current From Zener Diode Terminal (Vzl ....•...........• 25mA
Thermal Resistance
Plastic DIP Package •••••.•••••••.••
MetalCen ••••••••••••••••••••••••
650C1W
Device DIssIpation
CA723T, CA723CT, Up to T" = +250 C .•••••••••..•••• 900mW
CA723E:, CA723CE, Up to T" = +2500 •••••••••••••• l000mW
CA723T, CA723CT, Above T" = +25°C •••.•••••.••• 7.4mWf'C
CA723E, CA723CE, Above T" = +25°C •••••.•••..• B.3mWf'C
Ambient Temperature Range
Operating Temperature Range •••••.•••••••• -55°C to +125°C
Storage Temperature Range •••••••••••••••• -65°C to +lSOoo
Lead Temperature, During Soldering •.•••••••.•••••.•• +265°C
At a distance 1/16" ± 1132" (l.59mm ±0.79mm) from case for lOs
max
CAurlON: Stress/JS abo... those Hsted in "Absolute Maximum RaUngs" may cause permanent damage to the davlee. This Is a strees only raUng and operaUon
of the device at these or any olhiJr conditions abo... those indicated In the operaUonal sections of this specllicaUon Is not Implied.
DC Electrical Specifications T" =+2500, V+ =Vc =VI =12V, V- = 0, Vo = 5V, IL = lmA, CI =l00pF, CREF = 0, Rscp = 0,
Unless Otherwise Specified. Divider Impedance RI R:! + RI + R:! at noninverting input, Tenninal 5 =
10kO. (Figure 20)
CA723
CA723C
MIN
TYP
3.5
-
2.3
4
mA
9.5
-
40
V
37
2
V
38
3
-
37
3
-
40
38
V
6.95
7.15
7.35
6.B
7.15
7.5
V
VI = 12V to 40V
-
0.02
0.2
-
0.1
0.5
%Vo
VI = 12V to 15V
-
0.01
0.1
0.1
%Vo
0.3
-
0.01
-
-
-
%Vo
VI = 12V to 15V,
T" = OOC to +7000
-
-
-
-
-
0.3
%Vo
IL = lmA to SOmA
-
0.03
0.15
0.2
%Vo
0.6
-
0.03
-
-
-
%Vo
IL = 1mA to SOmA,
T" = OOC to +700c
-
-
-
-
-
0.6
%Vo
Outpul-Voltage Temperature Coefficlenl,AVo
T" = -5500 to +125°C
-
0.002
0.015
T" = OoC 10 +7ooC
-
-
-
Ripple Rejection (Note 2)
f = 50Hz 1010kHz
-
74
-
PARAMETERS
TEST CONDITION
MIN
TYP
MAX
-
2.3
9.5
MAX IUNITS
DC CHARACTERISnCS
Quiescent Regulator Current, 10
IL =0, VI = 30V
Input Voltage Range, VI
OUtput Voltage Range, Vo
2
Differentiallnput-output Voltage, VI - Vo
Reference Voltage, VREF
Une Regulation (Note 1)
VI = 12V to 15V,
T" = -5500 to +125°C
Load Regulation (Note 1)
IL = lmA to SOmA,
T" = -5500 to +125OC
f = 50Hz to 10kHz,
CREF = 51lF
-
86
Short Circuit Umiting Current, ILiM
Rscp = 100, Vo = 0
Equivalent Noise RMS Output Voltage,
VN (Note 2)
BW = 100Hz to 10kHz,
CREF = 0
-
-20
BW = 100Hz to 10kHz,
-
2.5
-.
-
.
-
65
-
-
-
-
%f'C
0.003
0.015
%f'C
74
-
dB
86
-
65
20
-
-
2.5
-
dB
mA
IlV
IlV
NOTES:
1. Une and load regulation specificalions are given for condition of a constant chip temperature. For high dissipation condition, temperature
drifts must be separately taken into account.
2. For CREF (See Rgure 20)
7-4
CA723, CA723C
UNREGULATED
INPUT
D1
6.2V
Vo
Vz
FREQUENCY
COMPENSATION
CURRENT
UMIT
CURRENT
SENSE
NON-INVERTING VINPUT
VREF
INVERTING
INPUT
FIGURE 1. EQUIVALENT SCHEMATIC DIAGRAM OF THE CA723 AND CA723C
Typical Performance Curves (CA723)
r--
r
\1 AMEM~NT T!MPE~ATUR~
MAX JUNCTION TEMP (TJ) • +1 SO"c
THERMAL RESISTANCE • 150oC/W
QUIESCENT DISSIPATION (PQ) .60mW
(NO HEAT SINK)
(TAl
-
~ +2SO~
OUTPUT VOLTAGE ~o) = SV
INPUT VOLTAGE (VI .. 12V
SHORT CIRCUIT PROTECTION
RESISTANCE (RSCp) " 0
0.06
~
z
0
~
5
-
......
::I -0.05
CI
\
o
"-
" '"
..........
C
C
-
-0.15
+12SOC
~ -0.05
~
~
~~
o
-ss°C
z~
i
~:;.? ........
/~ ...........
~
100
a::
C
9
I
I
AMBIENT TEMPERATURE (TAl = -ss°C
~
-0.1
I
\'\ ~
1
\ I\,'\. I
w
0.2
\
~+25oC
\
-0.3
-0.2
-0.25
40
60
80
OUTPUT CURRENT (mA)
I
0
g
/'
+125oC
g
20
OUTPUT VOLTAGE ~o) .. SV
INPUT VOLTAGE (V .. 12V
SHORT CIRCUIT PR TECTION
RESISTANCE (Rscp)" 0
0.1
AMBIENT TEMP (TAl" +250C /
~ -0.15
N2SOC
FIGURE 3. LOAD REGULATION WITHOUT CURRENT LIMITING
---- -
...... ~
-0.1
~
~50C
-0.2
40
OUTPUT VOLTAGE ~o) .. 5V
INPUT VOLTAGE (VI .. 12V
SHORT CIRCUIT PROTECTION
RESISTANCE (Rscp) • 100
z
::I
-0.1
g
FIGURE 2. MAX LOAD CURRENT va DIFFERENTIAL INPUTOUTPUT VOLTAGE
o
"
t',
a::
10
20
30
DlFFERENllAL INPUT - OUTPUT VOLTAGE (V)
o
~ :--
w
o
0.05
-
I
AMBIENT TEMPERATURE
"'"'- (TAl = +2SOC
+125°C \
-0.4
o
5
10
15
20
OUTPUT CURRENT (mA)
25
30
FIGURE 4. LOAD REGULATION WITH CURRENT LIMITING
II \
o
20
40
60
80
100
OUTPUT CURRENT (mA)
FIGURE 5. LOAD REGULATION WITH CURRENT LIMITING
7-5
CA723, CA723C
Typical Performance Curves (CA723)
1- -
~- ~- -
1.0
"' .-
~- ~- ai- ~-
(Continued)
> llc:
I
-:i:4§~
_...-w·
OUTPUT VOlTAGE (Vo). REFERENCE
VOLTAGE (VREF)
LOAD CIRCUIT (ILl - 0
r
~!S"A:
w~!frl
~~t::U;
!:;c:)u
ol-UZ
> .... II:C
!;~g~
I
I
I
I
I
AMBIENT TEMPERATURE (TAl" -ss"c
ca. .... O:CI)
!;:)ow
"':1:11:
Oii!OCII
./
I-
!z
0.2
~ ~'+
u-
o
o
40
20
60
t:::::
~
~
a
80
100
o
--
+25°C
+l25°C
40
20
30
INPUT VOLTAGE M
10
OUTPUT CURRENT (mA)
FIGURE 7. QUIESCENT CURRENT vslNPUT VOLTAGE
FIGURE 6. CURRENT LIMITING CHARACTERISTICS
.
OUTPUT VOLTAGE (Vo)oo REFERENCE
VOLTAGE (VREF)
U»i==~
_INO·
..... w-
1.0
~15~
~
~
!:i
0
Ol-C)":
w
a: 4
a:
I::>
I- 0.4
::>
0
5g~!Il
i3
::>oa:
::>"':z:
~
O~UI
!3
8
0.2
o
10
\
\
2
~
:::::;;-
DoC
-
I--
+70oCI - -
o"c
+7o"C
0
I
AMBIENT TEMPERATURE (TAl"' +25°C
~ 3
~I-a:w
...
I
I I I I II
~
>..10: ....
0.6
>
.§.5
~~!::~
!:i..:::)z
w 0.8
(t)oo 0 I
LOA, CURjENT
C
w~g:e.
20
40
60
OUTPUT CURRENT (mA)
80
o
100
FIGURE 12. CURRENT LIMITING CHARACTERISTICS
o
10
20
INPUT VOLTAGE
30
40
M
FIGURE 13. QUIESCENT CURRENT vslNPUT VOLTAGE
Typical Performance Curves (CA723 and CA723C)
INPUT VOLTAGE (VI) .12V
OUTPUT VOLTAGE (Vo)"' 5V
LOAD CURRENT (Ill .1 TO SOmA
AMBIENT TEMPERATURE (TAl- +25oC
SHORT CIRCUIT PROTECTION
RESISTANCE (RSCp)" 0
0.2
~
~ 0.1
~
::>
0
w
a:
~ ·0.1
--
r- Ir- Ir- Ir- I-
OUTPUT VOLTAGE (Vo) "' 5V
LOAD CURRENT (Ill .1 mA
AMBIENT TEMPERATURE (TAl" +250 C
0.3
DIFFERENTIAL INPUT VOLTAGE ( 0.1
CI
w
a:
w
0
z
i'"
:::J
-D.1
-D.3
5
-6
15
25
35
-D.2
45
-6
5
15
25
35
45
DIFFERENTIAL INPUT· OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT· OUTPUT VOLTAGE (V)
FIGURE 14. LOAD REGULATION VB DIFFERENTIAL INPUT·
OUTPUT VOLTAGE
INPUT VOLTAGE (v~ _12Y, OUTPUT VOLTAGE (vol- 5'1
LOAD CURRENT (I,) _ 40mA
AMBIENT TEMPERA1\JRE (TAl _ ••SOC
SHORT ClReutT PROTECTION RESISTANCE IRscP). a
II
LOAD CURRENT (Ill
1\
In
-
-
~
10
0.8
.§.
C
g 0.7
~
UI
Z
w
~
I
"-
CI
z
·10 C
C
~ 0.5
g
..I
Iz
w
·20
:l!
0.4
::>
C)
-30
10
....... It
........
/
UI 0.6
~
SHORT CIRCUIT UMITING
CURRENT WITH Rscp • 50
WI~H R'
I
CURRENT UMITING
r',NSE V tTAGE
~ 1000..
W
>
w
OUTPUT VOLTAGE (Vo)
i\
I I I I I
~
0
I
,
FIGURE 15. LINE REGULATION vs DIFFERENTIAL INPUT·
OUTPUT VOLTAGE
~
~ i"""o
Jt-oi.I
~ 1c:a
liP,
,
1"-0
r-....
r- ....
0.3
oS
5
15
25
TIME (1"1)
35
45
-60
0
50
100
150
JUNCTION TEMPERATURE <"C)
FIGURE 16. LINE TRANSIENT RESPONSE
FIGURE 17. CURRENT LIMITING CHARACTERISTIC vs JUNCTION TEMPERATURE
7·7
CA723, CA723C
Typical Performance Curves (CA723 and CA723C)
10
C
•
.§.
~
~
4
INPUT VOLTAGE "II
II
4
>
w
Q
w
2
II
2
~
0
1/
0
>
"f I I I r-
-2
0
...
-I"""
..
=-NJ==~RE:'iANCE
16
26
nME lILa)
3S
ClI
ill
6
!;
-2
r46
I INPUT VOLTAGE (VII.12V
OUTPUT VOLTAGE (Vo). 5V
4 LOAD CURRENT (Ill- SOmA
2 AMBIENT TEMPERATURE ~. +25°C
SHORT CIRCUIT PROTEC11
RESISTANCE (Rscp) • 0
~
~ "46
w
Q
w
~
2
V
11'1'
LOAD CAPACITANCE (CLl- 0
1/
V
0.1
§
>
!;
...... ... !:...
1RscP)·o
6
i
~
~
~UTrOLrA~E (Yo)
INPUT VOLTAGE (V~. 12V
OUTPUT VOLTAGE (Vo). SV
LOAD CURRENT (ILl. 1m"
!;
S
0
.....
E
(Continued)
I
4
2
.
0.01
468
2 468
2 4.8
2
1k
100k
10k
FREQUENCY (Hz)
2
100
FIGURE 18. LOAD TRANSIENT RESPONSE
468
1M
FIGURE 19. OUTPUT IMPEDANCE va FREQUENCY
Typical Application Circuits
v,
VAEF
v+
Vc
I
I
v,
VAEF
~
v+
Vc
I
I
Vo
~
1
riRscp
CURRENT
UMIT
R1
NON
INV
INPUT
CREFF
=
REGULATED
OUTPUT
R3
~~:~iNTR3
>-
vl COMP
..~ =
R1
C1
F
_
Circuli Performance Data:
Regulated OUtput Voltage 5V
Une Regulation (toV,= 3V) 0.5mV
Load Regulation (AIL SOmA) 1.5mV
JINV.
INPUT
COMP
R2
'=.,E:'
Circuit Performance Data:
Une Regulation (toV, = 3V) t.5mV
Load Regulation (AIL SOmA) 4.5mV
=
=
Note: R3
REGULATED
OUTPUT15V
CURRENT
SENSE
vl- 1 "t.
NO':-INV
INPUT
INV. r+ C1
INPUT
100pF
Rscp
CURRENT
UMIT
Note: R3 =
= R1
.B1..B2.. For Minimum Temperature Drift
+R2
.
R3
FIGURE 20. LOW VOLTAGE REGULATOR CIRCUIT
(VO .. 2V TO 7V)
.B1..B2.
For Minimum Temperature Drift
Ma~~: &mlnated For Minimum Component Count
FIGURE 21. HIGH VOLTAGE REGULATOR CIRCUIT
(VO • 7V TO 37V}
7-8
CA723, CA723C
Typical Application Circuits
(Continued)
Vc
V+t-~f------,
Vo
VREF
CURRENT
UMiT
NON
INV
INPUT
REGULATED
OUTPUT·1SV
~~----~~----+-~-+
Circuit Performance Data:
Line Regulation (AV1 =3V) 1mV
Load Regulation (AIL = 100mA) 2mV
Note: For Applications Employing the TO·S Style Package
and Where Vz Is Required, An External; 6.2V Zener Diode
Should be Connected in Series with Vo (Terminal 6).
Circuit Performance Data:
Line Regulation (AV1 = 3V) 1.SmV
Load Regulation (AIL = lA) lSmV
FIGURE 23. POSITIVE VOLTAGE REGULATOR CIRCUIT (WITH
EXTERNAL n-p-n PASS TRANSISTOR)
FIGURE 22. NEGATIVE VOLTAGE REGULATOR CIRCUIT
R3
600
2NSJ156
HI-Q~-----"'~OR
r-.....iVc::.--o~VoL_~
R1
R2
CURRENT
UMIT
REGULATED
~-""'~_~~-=~~~O~U~TPUTSV
Rscp
1-_-0-""::;';';::;1 300
2N6108
Rscp
NON~---rl]~~-4--~~:REGULATED
I~~~T
V.
=
CURRENT
UMIT
R1
COMP
..T.. C1
0.001I'F
R4
5.6ka
NONL,...-..r=-:;;.......----....J
R2
OUTPUT SV
INV
INPUT
=
Circuit Performance Data:
Line Regulation (tN = 3V) O.SmV
Load Regulation (AIL = 10mA) lmV
Short Circuit Current 20mA
Circuit Performance Data:
Line Regulation (AV1= 3V) O.SmV
Load Regulation (AIL = 1A) SmV
FIGURE 24. POSITIVE VOLTRAGE REGULATOR CIRCUIT
(WITH EXTERNAL p-n-p PAS TRANSISTOR)
FIGURE 25. FOLDBACK CURRENT UMITING CIRCUIT
7-9
CA723, CA723C
Typical Application Circuits
(Continued)
R5
10110
RS
3.9110
V+
1
VC
-
~
Vz
VREF
VI
VI_'SV
n
R2
".I.2N3442
R4
3110
Rl
'"l'fJv
A~·SK3062
NON
INV.
~UT >--
R3
3110
R2
I
""-=-
~~sCP
10
8~~~ENT
D1
12V
SK3062
CURRENT
SENSE
V-
~.~OOl"F
INPUT
Rl
COMP
REGULATED
OUTPUT-l00V
REGULATED
OUTPUT~V
Circuit Performance Data:
Une Regulation (IN = 20V) 15mV
Load Regulation (1l.1l = 50mA) 20mV
NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode should
be connected in series with Vo (terminal 6)
Circuit Performance Data:
Une Regulation (Il.VI = 20V) 30mV
Load Regulation (1l.1 l =100mA) 20mV
NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode should
be connected in series with Vo (terminal 6)
FIGURE 26. POSITIVE FLOATING REGULATOR CIRCUIT
FIGURE 27. NEGATIVE FLOATING REGULATOR CIRCUIT
VI
NOTE 2
VREF
V+
VREF
Vc
Rl
Vo
R3
Vz loon
REGULATED
OUTPUTSV
C
Rl
CURRENT SENSE
L,.-...,..t--~N:O:;N:::IN:V::-.-"'"
R2
R2
2110
=
INV
INPUT
V-
COMP INPUT
.:f.
CCSL
LOGIC
INPUT
Circuit Performance Data: .
Line Regulation (Il.VI = 3V) O.5mV
Load Regulation (1l.1 l = 50mA) 1.5mV
Short Circuit Current 20mA
NOTE: 1. A current limiting transistor may be used for shutdown if
current limiting is not required.
2. Add a diode if Vo > 10V.
C1
O.OOS"F
Circuit Performance Data:
Line Regulation (Il.VI = 10V) O.5mV
Load Regulation
(~IL
= 100mA) 1.5mV
NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode
should be connected in series with Vo (terminal 6).
FIGURE 28. REMOTE SHUTDOWN REGULATOR CIRCUIT WITH
CURRENT LIMITING
7-10
FIGURE 29. SHUNT REGULATOR CIRCUIT
CA1523
Voltage Regulator Control Circuit
for Variable Switching Regulator
April 1994
Features
Description
• Operates up to 200kHz
The CA1523 monolithic silicon integrated circuit is a variable
interval pulse regulator designed to provide the control circuitry for use in switching regulator circuits. It operates from
11Vto15V.
• Pins ESO Protected
• Remote ON/OFF
• Slow Start with Reset
• Overcurrent Sensing
• Lower Peak Currents than PWM Regulator
• Less Prone to Magnetic Saturation
Ordering Information
PART
NUMBER
CA1523E
TEMPERATURE
RANGE
OOC to +70oC
PACKAGE
14 Lead Plastic DIP
The regulator provides a single output drive capable of
300mA sourcel200mA sink. The maximum operating frequency is better than 200kHz. An attractive feature of the
CA 1523 is that the timing capacitor charge and discharge
current is set up externally via a single resistor. The ratio of
charge to discharge current is internally set at a maximum of
2 to 1 allowing simultaneous change in output pulse width
with increased frequency at higher load. The pulse width
variation at higher frequencies effectively compensates for
the losses in magnetics and thereby increases the power
supply efficiency at higher load end by as much as 20
percent.
Pinout
CA1523 (PDIP)
TOP VIEW
ERROR
1
CURRENT SENSE
2
RISE TIME
4
11 OVER CURRENT
OUTPUTGND
5
10 SLOW START
8 LOGIC OUTPUT
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7·11
File Number
1785.2
Specifications CA 1523
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage •••••••••.•..••..••••.•••.•..••.••• 15V
Supply Current
16(MAX)' .•.•.••••.•.••..••••••...•...•••••.•..•..•..• ±SOmA
16(MAX)' 1l1S,l800pF Load •••••••••••••••••••. +300, -200mA
Device Dissipation
Up to TA = 7ff'C ••.•••.•••••.••••••••••••....••• 530mW
Above TA = 70°C ••....•.•••••••. Derate Unearly at 6.7mWf'C
Thermal Resistance
8JA
Plastic DIP Package. • • • • • • • • • • • • • • . • • . • . • . .
12ff'Cm
Device Dissipation
Up to TA = 7ff'C .•••••••••••••••••••••••••••••••• 665mW
Ambient Temperature Range
Operating .••••••••.•••.••••.•••••••.•.••.. ff'C to +70oC
Storage ...•••.•...•.••••••.•••••••••••• -55°C to +150°C
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±O.79mm)
from case for lOs Max •.••••.•.••••••••••.•....... +265°C
CAUTION: StressllS above those listed In 'Absolute Maximum RaUngs' mey cause permanent damage to the device. This is a stress only ra6ng and operation
of the device at these or any other conditions above those indicated in the opera60nal sections of this specifica60n is not Implied.
Electrical Specifications TA = +25°C, Refer to condition shown In test circuit; V7 = 13V, VI = 5.9V Unless Otherwise Specified
PARAMETERS
PIN
TEST CONDITIONS
MIN
TVP
MAX
UNITS
9.5
13
-
V
20
27
34
rnA
7.8
8.4
8.9
V
POWER SUPPLY, Vcc (PIN 7)
Supply Voltage
7
Supply Current
7
Zener Voltage
13
Vee = +13V
OUTPUT PULSE (PIN 6)
Maximum Pulse Width
6
Measured at 6V Threshold Level
5.5
6.5
7.5
I1S
Minimum Pulse Width
6
Measured at 6V Threshold Level
2
3
4
I1S
Output High Voltage
6
16=OmA, V4 =OV
11.1
12
12.6
V
Output Low Voltage
6
16 = SOmA, V12 = OV
0.6
1
1.3
V
Rise Time
6
Measured at 1.8V and 10V Threshold Levels
250
600
1250
ns
Fall Time
6
Measured at 1.8V and 10V Threshold Levels
50
200
350
ns
1
Adjust RT; Observe Pin 6 MInIMax
Frequency Range
5.9
6.8
7.5
V
Charge Current
14
Adjust RT, VI =7.5V; SetV14 =OV, Then VI4 =2.5V
190
220
250
I1A
Discharge Current
14
Adjust Rr = 5.9V; SetV14 = 5.5V, Then 5V
95
110
125
I1A
Slow Start Discharge Current
14
Maintain V14 = 5V, V10 = 5.5V
Set V10 = 5.5V, Measure 114 (HI)
Set V10 = 4V, Measure 114 (Lo)
Umits = 114 (Hi) - 114 (Lo)
1.5
20
30
40
/!AIV
Discharge Voltage
10
Pin 12 = 1kO to GND
1.7
2.4
3.2
V
Output Inhibit Vo!tag@
7
Increase V; Until V; ~ 2V
HI
M
R~
V
Overcurrent Trip Voltage
11
V12 = 5V; V10 = OV; Increase V11 Until Vi S 0.5V
1.1
1.25
1.4
V
ERROR VOLTAGE RANGE (PIN 1)
Error Voltage Reference
CHARGE CURRENT (PIN 14)
LOGIC TESTS
7-12
CA1523
Other Desirable Features
Other desirable features along with various circuit block
function explanations are listed below.
• The Oscillator is a sawtooth generator whose charge
(rise) cycle determines the output pulse width and discharge which is continuously variable from very low to
maximum of ICHARGE'
• Charge ICHARGE
control
=10 -IDISCHARGE giving 2 to 1 pulse-width
• Discharge IDISCHARGE = approximately 0 to 1/2 10 to
frequency control.
• Pulse Shaping: Applied to the oscillator output via RS
Flip-Flop with parallel inhibit controlled by slow-start overcurrent sense, supply voltage monitor and ON/OFF functions.
• Pulse Rise Time: Modified to meet RFI requirements by
external slow-down capacitor.
• Slow Start with Reset: Externally programmed against
internal 3V reference. Reset is initiated upon Inhibit ensuring soft start at power up and restart.
• Over Current Sense: Internal stable thresholds of 1.2V.
• Supply Voltage Monitors: Locks out the drive until
VSUPPLY has reached 8V-9V.
• ON/OFF: Activates regulator independent of raw DC.
• Error Amplifier: Compares output against a stable 6.8V
internal reference and controls the discharge current sink
on the timing capacitor.
• Band-Gap: Reference voltage (internal) provides temperature compensated 1.2V and 6.8V references.
• Separate GNO: The power GND is separated from circuit
ground for improved noise.
• ESO Protection: Pins are protected against ESD.
Block Diagram
CURRENT
SENSE
vee
ZENER
5V
REF.
~_--------t 4
RISE
TIME
··
···
·:
~
3
GND
OVER
CURRENT
(CONTROL
•
CIRCUIT
:
GND)
; "="
···
·
6. ____ -
_ _ _ _ _ ....
.. _ _ _ _ _ _ _ _ ..
10
SLOW
12
9
ON/OFF
LOGIC
OUT
START
7-13
CA1523
Vee
Rr
·:
·::
: (CONTRO
: CIRCUIT
~
:
:---_ ..._-- ...
220
~VCc
OFF~V
FIGURE 1. TEST CIRCUIT FOR TH ECA1523
----:7.1=----4-
1
CA1523
+150V
RECTIFIED AC UNE
INPUT
+150
TYP. INPUT USA
· -------------_-._-----".
TRANSFORMER
,......
TYPICAL
RECT.
OUTPUT
VOl +130V
~---+O V04 ·24V
30k
11k
••
.~
:~
10
ON/OFF
1.5k
----- ,
v~t:'lAGE.
:
:
NC
NC
NC
8
II
13
:!
,----+--00 V02
+16V
·
L---+--00 V03
+24V
....
.W
'W
7
CA1523
•
~
,-...J
.,-......J
:
0.15
!- ---........ -......... ...-
3W
OPT~OUPLER
FIGURE 2. TYPICAL APPLICATION CIRCUIT FOR THE CA1523
Vee
8.3K
UK
II
LOGIC OUT
FIGURE 3. TIMING CIRCUIT FOR THE CA1523
7-15
CA 1524, CA2524
CA3524
Regulating Pulse Width Modulator
April 1994
Features
Description
• Complete PWM Power Control Circuitry
The CA1524, CA2524, and CA3524 are silicon monolithic
integrated circuits designed to provide all the control circuitry
for use in a broad range of switching regulator circuits.
• Separate outputs for Single-Ended or Push·Pull
Operation
• LIne and Load Regulation •••••.••••••.•• O.2%{Typ)
• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range
• Standby Current of Less Than 10mA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.511S to 5JLS
• Low VCE(aal) Over the Temperature Range
Applications
The CA1524, CA2524, and CA3524 have all the features of
the industry types SG1524, SG2524, and SG3524,
respectively. A block diagram of the CA 1524 series is shown
in Figure 1. The circuit includes a zener voltage reference,
transconductance error amplifier, precision R-C oscillator,
pulse-width modulator, pulse-steering flip-flop, dual alternatIng output switches, and current-limiting and shutdown
circuitry. This device can be used for switching regulators of
either polarity, transformer-coupled dc-de converter,
transformerless voltage doublers, dc-ac power inverters,
highly efficient variable power supplies, and polarity
converter, as well as other power-control applications.
Ordering Information
• Positive and Negative Regulated Supplies
PART
NUMBER
• Dual-Output Regulators
TEMPERATURE
RANGE
PACKAGE
• Flyback Converters
CAl524E
-55°C to +125°C
16 Lead Plastic DIP
• DC-DC Transformer-Coupled Regulating Converters
CA1524F
-55°C to +125°C
16 Lead CerOIP
• Single-Ended DC-DC Converters
CA2524E
Ooc to+70oC
16 Lead Plastic 01 P
• Variable Power Supplies
CA2524F
OOC to +70oC
16 Lead CerOIP
CA3524E
OOC to+70oC
16 Lead Plastic DIP
CA3524F
OOC to +700C
16 Lead CerOIP
Pinout
CAl524, CA2524, CA3524
(PDIP, CERDIP)
TOP VIEW
INY.INPUT
VAEF
1
NON-
V+
INV.INPUT
OSCOUT
3
EMITTERS
(+)C.L
COLLECTORS
SENSE
(-)C.L
5
COLLECTOR A
SENSE
EMmER A
r_
G~~
7
7
~L..
5].1: :~~=:noN
_ _ _ _- - '
AND COMPARATOR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-16
File Number
1239.3
CA 1524, CA2524, CA3524
Functional Block Diagram
.SV TO ALL
INTERNAL CIRCUITS
VAEF
3r-------------------.---t
OSCOUT
• SENSE
• SENSE
1k!.!
10
L -__________________________-{
SHUTDOWN
8
COMPENSATION AND COMPARATOR
10k!.!
G)
GND
Test Circuit
8.40V
r-________________________________________--,1W
2k!.!
OUT A
OUT a
CA1524
0.1""
1k!.l
2k!.!
7·17
Specifications CA 1524, CA2524, CA3524
Absolute Maximum Ratings
Thermal Information
Input Voltage (Between VIN and GND Terminals) ••....••.•.. 40V
Operating Voltage Range (VIN to GND) ••.....•...•...• 8 to 40V
Output Current Each Output:
(Terminal 11, 12 or 13, 14) •...•.........•.•••••.••• 100mA
Output Current (Reference Regulator) ...••••...•••...... 50mA
Oscillator Charging Current •..•....•.•••••..••••.•••••• 5mA
Thermal Resistance
9JA
Plastic DIP Package ...•••.•...•..•.•••.•... 1000 CIW
Device Dissipation
Up to TA = +25°C ••••••••...••••.••••••.•.••...••• 1.25W
Above TA = +25°C •...•...•...... Derate Llnea~y at 10mWI"C
Operating Temperature Range •.•••••••••.•..• -55°C to +125°C
Storage Temperature Range ••...•.••.•••...•• -65°C to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max •.....••.....•...•.•..•...•• +265°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings· mey cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the operational sections of this specificaUon is not implied.
Electrical Specifications TA = -55°C to +125°C lor CA1524, oOC to +700C lor the CA2524 and CA3524; V+ = 20V and
I = 20kHz, Unless Otherwise Stated.
CA1524, CA2524
TEST CONDITIONS
PARAMETER
I
CA3524
TYP
MAX
MIN
4.8
5
5.2
-
10
20
20
50
66
MIN
TYP
MAX
UNITS
4.6
5
5.4
V
-
10
30
mV
20
50
mV
66
db
100
-
rnA
0.3
1
%
-
mVlkhr
-
kHz
REFERENCE SECTION
Output Voltage
Une Regulation
V+ = 8 to 40V
Load Regulation
'l = 0 to 20rnA
-
100
-
-
0.3
1
TA =2SoC
-
20
-
-
20
Maximum Frequency
CT = 0.00111F, RT = 2Kn
300
-
-
300
S
-
-
1
-
S
2
-
3.S
-
-
Ripple Rejection
f = 120Hz, TA = 25°C
Short Circuit Current Limit
VREF=O, TA=2SoC
Temperature Stability
Over Operating TemperabJre
Range
Long Term Stability
OSCILLATOR SECTION
Initial Accuracy
At and CT Constant
-
Voltage Stability
V+ = 8 to 40V, TA = 2SoC
-
Temperature Stability
Over Operating TemperabJre
Range
-
Output Amplitude
Terminal 3, TA = 2SoC
Output Pulse Width (Pin 3)
CT = 0.0111F, TA = 2SoC
Ramp Voltage Low (Note 1)
Pin 7
Ramp Voltage High (Note 1)
Pin 7
Capacitor Charging Current Range
Pin 7 (S-2 VsE)/RT
0.03
Timing Resistance Range
Pin 6
1.8
Charging Capacitor Range
Pin7
0.001
Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)
Pin 3
100
O.S
0.6
3.S
-
%
-
1
%
2
%
3.S
-
V
O.S
-
I1S
0.6
-
V
3.S
-
V
0.03
-
2
mA
120
1.8
kn
0.001
-
120
0.1
0.1
I1F
1000
100
-
1000
pF
2
ERROR AMPliFIER SECTION
-
O.S
S
-
2
10
mV
1
10
-
1
10
I1A
Open Loop Voltage Gain
72
80
60
80
Common Mode Voltage
TA = 25°C
1.8
-
3.4
1.8
Common Mode Rejection RatiO
TA =2SoC
-
Ay = OdB, TA = 2SoC
-
70
Small Signal Bandwidth
3
-
-
Input Offset Voltage
VCM=2.SV
Input Bias Current
VCM=2.SV
7-18
dB
-
3.4
V
70
-
MHz
3
dB
Specifications CA 1524, CA2524, CA3524
Electrical Specifications
TA = -550 C to +125"C lor CA1524, O"C to +70"C lor the CA2524 and CA3524; V+ = 20V and
I = 20kHz, Unless Otherwise Stated. (Continued)
CA1524. CA2524
MAX
MIN
0.5
·
3.8
2SO
External Sink
·
·
200
·
·
Duty Cycle
% Each Output On
0
·
45
Input Threshold
Zero Duty Cycle
·
·
Max. Duty Cycle
·
·
1
Input Threshold
3.5
·
·
1
·
·
·
190
200
210
Sense Voltage T.C.
·
0.2
Common Mode Yoltage
-1
Rolloff Pole of R51 C3 + Q64
·
Output Voltage
TEST CONDITIONS
TA = 25°C
Amplifier Pole
Pin 9 Shutdown Current
MIN
CA3524
TYP
PARAMETER
TYP
MAX
UNrrS
0.5
·
3.8
V
·
·
2SO
Hz
200
·
·
IIA
0
·
45
%
1
·
V
3.5
·
V
1
·
IIA
180
200
220
mY
·
·
0.2
·
mVf'C
·
+1
-1
·
+1
Y
300
·
·
300
·
Hz
COMPARATOR SECTION
Input Bias Current
CURRENT LIMITING SECTION
Sense Yoltage lor 25% Output Duty
Cycle
Terminal 9 = 2Y with Error
Amplilier Set lor Max Out,
TA=25°C
OUTPUT SECTION (EACH OUTUT)
40
·
·
40
·
·
V
Collector Leakage Current
VcE =4OY
·
0.1
50
·
0.1
50
IIA
Saturation Voltage
V+ = 40V, Ic = SOmA
·
0.8
2
·
0.8
2
Y
Emitter Output Yoltage
Y+=20Y
17
18
·
17
18
·
V
Rise TIme
Rc = 2K.Q, TA = 25°C
·
0.2
·
lIS
Rc = 2K.Q, TA = 25°C
·
0.1
Total Standby Current: (Note 2) Is
Y+=40Y
·
4
·
·
·
0.2
Fall TIme
·
·
Coliector·Emitter Voltage
10
NOTES:
0.1
·
lIS
4
10
rnA
Hi9hl!W
LOW.!!!.
where t = OSC period in microseconds
;t;
t ;: RrCr with C r in microfarads and RT in ohms.
Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.
1. Ramp vonage at Pin 7
2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.
7-19
CA 1524, CA2524, CA3524
Schematic Diagram
_--... -----..... ------------.-----... -... -----M---------------• _______ ... _______________ _
,,
,,,
,,,
,
,,,
,,
,,,
,,
,,
,,
,,,
,,,
,,,
,,
,
,,,
,,
,,,
,,
,
,,
:,,
,,,
,,
,,,
,,,
,
,,,
,
,,,
,
,,,
_... _--------------,
A
B
R13
RO
-------.
10K UK
6Q
f.
,,
;-------_.,
,
,,
,
,,,
,,
,,,
,,
,,,
,,
•,,,
,,,
01
,r---------,,,
,
,
,,,
PULSE
:,, STEERING
,, FUP-FLOP
,,,
,
,,,
c
o
E
, R9
:500
,
,
-------------------------------.------, r-
...--i,_-•••-.-!.-.-_-.-..-.-.-.-.-.-.-.-.-.'..
:',:,.,:,.,:,.:-::.-:.-:.-:.':i.r-.1---···~·~·:··:·~·~·:··:·~·~·:·~··~·~·:·:··~·~·~·;·02S~C~·!s·~Ec~nn·OQ·N~-~·~J~::~::::~::::~::=f~~~~~~~~i::::::
F
G
r
NON-INV.
INPUT
t-+---J
7
Cr
r-;,f---+-.....-4
,,:
,,
,,
,,,
,,
,,
,,
,
,,
R3g
1K
R47
1K
R40
560
,
' .... ____ • ___ .. ___ .. __ ..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • __ - - - - - - - - - _____ .. 4
7-20
R48
2K
K
~----------------~
L
CA 1524, CA2524, CA3524
Schematic Diagram (Continued)
,....................................... .. .................... -- -- ............... ----_ ........................................................:
."
."
A
OUTPUTB
OUTPUT A
~
:
,,,
,,
,,
,,,
B
,
RU
R34
R31
500
SOO
....-------+-t-..., -{14 EMIT B
11}--+:----+-~~--------------~
EMiTA
,,
,,
:,--------------_ ........ _------------ ..........
--
·~ I
C
..
NOR
F
G
•___________________________;
,,,
,
,,
=
---------
'
... ---- .. ----------..,----- .. -~
-----------------------.
NOR
·
0
E
R38
4.70
4.70
::~K
:
::
,
:
R28
:
8.7K
,,:
,,
:,
t ___________. ____ ...... ____ .. ___ .. ____l'
~ ::::::::::::::::::::::::~--_.----~;r:-:--:-:-:-~------------~~~:::~~~~--1
:
i:,
:,,
10
J
··
,,:1
,,
,,,
,
,,•
,
,,:I
K
L
,
,.-
I
R411
1K
:,
:,
:,,
:
:
:
:
:
··:
:
:,
··
,~
063 :
R50
10K
~---------~
:,
,
CURRENT
UMIT
SECTION
,,,
.:
I
I-
._-------------------------------_!
S
(-j C.L.
(+j C.L.
SENSE
SENSE
7-21
CA 1524, CA2524, CA3524
Circuit Description
Oscillator Section
Voltage Reference Section
Transistors 042, 043 and 044, in conjunction with an
external resistor AT, establishes a constant charging current
into an external capacitor CT to provide a linear ramp voltage
at terminal 7. The ramp voltage has a value that ranges from
O.SV to 3.SV and is used as the reference for the comparator
in the device. The charging current is equal to (S-2VBE)/AT or
approximately 3.6IRT and should be kept within the range of
30pA to 2mA by varying AT' The discharge time of CT determines the pulse width of the oscillator output pulse at terminal 3. This pulse has a practical range of O.S~s to S~s for a
capacitor range of 0.001 to 0.1 ~F. The pulse has two internal
uses: as a dead-time control of blanking pu lse to the output
stages to assure that both outputs cannot be on simultaneously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Figure 4. Pulse widths less than O.S~s may allow false triggering of one output by removing the blanking pulse prior to a
stable state in the flip-flop .
The CAIS24 series contains an internal series voltage regulator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
IS and is capable of supplying up to SOmA output current.
Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.
.1
5.02
w
~ 5.00
~
4.l1li
..
w
~
M!
~ i""'"
~
::... ~ FI": io-""
§!
~
v+-40Y.It.-OmA
v+.20V,~.omA
v+.40~ 1t.-2OmA
v +_8V.I•• omA
v+ • 2OY, ..... 20mA
v+.8V, IL _2OmA
_10-
~
4.96
~ 1,...0- io-""
100
f-
Io6Q
0040 -20 0
1
20 40 60 60 100 120 140
~
AMBIENT TEMPERATURE ("C)
FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
4.11
~
4.7
'-'
4.5
~
4.3
w
w
"w
4.1
~
Z
a:
~
W
6
!j
5
~
4
~
II!~
~
w
a:
0.1
1.0
FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A
FUNCTION OF TIMING CAPACITOR VALUE
o
8
16
24 32
40
48
56 64
72
80
FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF REFERENCE OUTPUT CURRENT
8
0.01
TIMING CAPACITOR, C'r (j1F)
REFERENCE OUTPUT CURRENT (mA)
~ 7
0.001
V+_8V'
3.7
3.S
0.1
0.0001
II
3.11
a:
/
1.0
1.;1'
~~
L ~l
V+_20V
~~
~~
TA_+25oC
V+_20V
10
~
V+_40V
w
V+.8V-40V
I!:
5.1
~
TA·+25oC
l-~h~50~
I
II
3
2
1
I
I
O~I~__L-~~~~~~~__L-~
o
10
20
30
40
SUPPLY VOLTAGE, V+ (V)
FIGURE3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE
If a small value of CT must be used, the pulse width can be
further expanded by the addition of a shunt capacitor in the
order of l00pF but no greater than 1000pF. from terminal 3
to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-Kn resistor at
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
maximum duty cycle acceptable.
The oscillator period is determined by AT and CT, with an
approximate value of t = ATCT, where AT is in ohms, CT is in
~F, and t is in ~. Excess lead lengths, which produce stray
capacitances, should be avoided in connecting AT and CT to
their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency ihe same as ine osciiiator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-4S%
and the overall frequency is half that of the oscillator. Curves
7-22
CA 1524, CA2524, CA3524
of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAI524's, one must be designated as master, with RT
CT set for the correct period. Each of the remaining units
(slaves) must have a CT of 1/2 the value used in the master
and approximately a 1010 longer RTCT period than the master. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.
TA-+25°C
v+_ 'V-40V
CT - 0.001 "F1
CT" 0.005)}.
L
VI
CT - 0.OO2"Ft
I
V
V
VI'
Cr"O.02"F
V
j
CT" O.OS"F
Vll'
CT= O.01"F
irrr"
The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated
amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.
Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good starting point to determine the external poles is a 1000-pF
capacitor and a variable series 50-Kn potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200~ can pull this point to ground and shut off
both output drivers.
While feedback is normally applied around the entire regulator, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure B. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
10
102
103
OSCILLATOR PERIOD, t (f'S)
FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION
OF RTAND CT
Error Amplifier Section
The error amplifier consists of a differential pair (056,057)
with an active load (061 and 062) forming a differential
transconductance amplifier. Since 061 is driven by a
constant· current source, 062, the output impedance ROUT,
terminal 9, is very high (= 5MQ).
l48
g
40 10-
The gain is:
~:
Av = gmR = Blc Rl2KT = 104 ,
~
where R=
Since RoUT is extremely high, the gain can be easily
reduced from a nominal 104 (BOdS) by the addition of an
external shunt resistor from terminal 9 to ground as shown in
Figure 6.
'0
""
RL=-
70
RL=3MO
60
RL=1Mn
<
I!I
50
RL=300j
I!I
40
0°
RL .1001<11
:!!.
z
w
~
g
r----..
,PEN
L~OP
~
102
103
104
FREQUENCY (Hz)
~
~
i.-":'"
--
P
~~
CT,,1000pF
RT'.5k
~
'osc = 20kHz
. / ./
o
...
". ,/
0.4 0.' 1.2 1.6 2 2.4 2.8 3.2 3.6
COMPARATOR VOLTAGE (V)
4
FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF
COMPARATOR VOLTAGE (AT TERMINAL 9).
E:
1.1
w
-"
lfPEN Loc;'f PHASE
10
o
~
CT_2700pF
RT-S.19k
'osc " 60kHz
~
GAIN
~
g
""" I"-
" ...........
10-
16
o ,
m-
TA- +2S0 C
v+_ 20V
;.J
1.0
J
~
~
5io.e
a:
./
::I
!c
~ 0.8
~
50
105
0.7
./
,..
V
~~~
0 25 ~ n 100n51~1n
AMBIENT TEMPERATURE rC)
FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE
CHARACTERISTICS.
FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF AMBIENT TEMPERATURE.
7-23
CA 1524, CA2524, CA3524
Output Section
The CA1524 series outputs are two identical n-p-n
transistors with both collectors and emitters uncommitted.
Each output transistor. has antisaturation circuitry that
enables a fast transient response for the wide range· of
oscillator frequencies. Current limiting of the output section
is set at 100mA for each output and 100mA total if both
outputs are paralleled. Having both emitters and collectors
available provides the versatility to drive either n-p-n or p-n-p
external transistors. Curves of the output saturation voltage
as a function of temperature and output current are shown in
Figures 8 and 9, respectively. There are a number of output
configurations possible in the application of the CA1524 to
voltage regulator circuits which fall into three basic
classifications:
The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 11. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
VREF
SK
€
2.0
~
'-'
g
R1
~
~
VREF
o
R1 +R2
L-~'Iv--_
GND
~
R2
NEGATIVE
OUTPUT
VOLTAGES
FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS
V
.,/
0.5
~o
Jlli!L. .2.SKW
5K
",
~
tc
-t-----,
R1
1/
1.0
II)
V 2.SV (Rl + R2)
o
Rl
GND
SK
T",,+250C
v+_eVto40V
1.5
a:
::)
posmVE
OUTPUT
VOLTAGES
5K
1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits
w
R2
r---4Ivv--....
~
o
40
60
eo
OUTPUT CURRENT, IL (mA)
20
CA1524
REFERENCE
SECTION
100
FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
V+CANNOT
EXCEED6V
Device Application Suggestions
For higher currents, the circuit of Figure 10 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed for operation from a fixed 5V
supply by connecting both terminals 15 and 16 to the input
voltage, which must not exceed 6V.
~-~~r-----------~
NOTE: V+ Should Be in the 5V Range
And Must Not Exceed 6V
FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE
REFERENCE REGULATION
To provide an expansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.
ILTOI"
DEPENDING
ON CHOICE
.V;+~1_0 _0
__________-+________
GND
-6-':~.J
J
FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE
CURRENT CAPABIUTY
FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITHOUT USING A CAPACITOR ON PIN 3 OR WHEN A
LOW VALUE OSCILLATOR CAPACITOR IS USED
7-24
CA1524, CA2524, CA3524
TABLE 1. INPUT vs. OUTPUT VOLTAGE. AND FEEDBACK
RESISTOR VALUES FOR IL ,", 40mA (FOR CAPACITOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)
RI
R2
- - -.....- I -....-JWI,.--..
RS
.----~4r-----.
-1... (VllI + ~)
RS
lac-
SENSE
+
IMAX.
"1 +""
~
WHERE
VllI- 2OOmV
FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED
TO REDUCE POWER DISSIPATION UNDER
SHORTED OUTPUT CONDITIONS
01
,. ~ ~Tf-(.i----·1f-
,. --0.1 r~t--.l___..t--
--
u
~
~
TEST
RL
IQUIESCENT
CI
w
a: 2
CONNECT TERM
NO.6
VIN
--
V REF
-
3
:::>
100pF
!zw
S
+1.6
Open
Open
+40
Open
Open
VOUT(MAX)
3650
+40
Ground
Closed
VOUT(MIN)
10k
+30
Terminal No.1
Open
U
~
z
-
"""- ~
C
I
I
I
I
I
INPUT VOLTS (V+jN) .15
OUTPUT VOLTS (V+ouT) .. 10
AMBIENT TEMPERATURE (TAl" +250 C ,
-0.4
125
o
20
150 100
40
60
eoan
80
60
100
LOAD CURRENT (rnA)
FIGURE 7. IUM va TA
FIGURE 8. LOAD REGULATION CHARACTERISTICS
7-35
CA30S5, CA30S5A, CA30S58
Test Circuits and Typical Performance Curves
I
f-
I
I
I
(Continued)
I
INPUT VOLTS (V.,w- 20
OUTPUT VOLTS (V+oUT) _10
o.os
~
0.04
~
~ 0.03
~
0.02
I"'"
w
~ 0.01
o
-75
-50
-
~
5.60
V
-'
VNOISE
8200
-25
0
25
50
75
100
AMBIENT TEMPERATURE ("C)
1000
l00pF
125
FIGURE 10. TEST CIRCUIT FOR NOISE VOLTAGE
FIGURE 9. LINE REGULATION TEMPERATURE
CHARACTERISTICS
TEST PROCEDURES FOR TEST CIRCUIT FOR RIPPLE
REJECTION AND OUTPUT RESISTANCE
Output Reslstancs
VOUT
j ) - -.......- - _ -
Condttions
1. VIN = +25V, CREF = 0, Short E,
2. Set ES2 at 1kHz so that E2 = 4VRMS
3. Read VOUT on a VTVM, such as a Hewlett-Packard, HP400D or
Equivalent
4. Calculate RoUT from RoUT VOUT(RL1E2)
=
Ripple ReJection· I
T" T2 .. STANCOR TP-3
-
T2
O-;S2------BLAC-K---~11
BLACK
AND
YEUOW
GREEN "="
Ripple ReJection· II
-
FIGURE 11. TEST CIRCUIT FOR RIPPLE REJECTION AND
OUTPUT RESISTANCE
10
a4
g
~
1
~
0·t.08
~
...
CondHions
1. Repeat Ripple Rejection I with C REF = 211F
~
I'
(.)
/
~
1.3
II:
1.2
IIIw
!;
V
§
\
1.1
"'- I--....
w
~
~
C
:& U
0.02
z~
4 68 1
2
4 6810 2
4 6'00 2
4 618000
0.8
I
I
-75
FREQUENCY (kHz)
I
I
I
I
I
-50 -25
0
25
50
75
AMBIENT TEMPERATURE I"C)
7-36
"
I
100
FIGURE 13. NORMALIZED ro vs TA
FIGURE 12. ro va'
-
,
Q
8 ~::
0.1 2
INPUT VOLTS (V+JN) .. ZlV
FREQUENCY (f) .. 1kHz
OUTPUT RESISTANCE (Flo) .. 0.0750
(AT TA .. +25OC)
w
./
II:
~
INPUT VOLTS (V+\Nl- ZlV
AMBIENT TEMPERATURE (TAl" +2S"C
2
0.8
0.6
0.4
0.2
Z
-
CondHions
1. VIN = +25V, C REF = 0, Short E2
2. Set Es, at 1kHz so that E, = 3VRMS
3. Read VOUT on a VTVM, such as a Hewlett-Packard, HP400D or
Equivalent
4. Calculate Ripple Rejection 'rom 20 log (E,NoUT)
I
125
I
CA308~CA3085A,CA3085B
Test Circuits and Typical Performance Curves
(Continued)
"-
II!
~~
> ..
REFERENCE VOLTS (VREF) _ +1.6V
(AT T" _ +25"<:)
LOAD CURRENT (IU- 0
0.3
~~
!jw 0.2
O~
~!j
o§!
/
0.1
~5
~~
0
-0.1
V
ww
filfil
:r:r
"''''
00
,
/
~
40V
-0.2
'. '. '.'..••.
'. ....
1\\ 2SV
-50
-25
OPERATION WITHOUT
HEAT SINK
-
OPERATION WITH
HEAT SINK
.•.....
".
...
/
I
:;.~'.:::: '.:::::
..
.......
'\"
"'-..15V
" "'--
0
25
SO
75
100
AMBIENT TEMPERATURE rC)
125
40
20
FIGURE 14. TEMPERATURE COEFFICIENT OF VREF AND VOUT
INPUT~OLTS
(VIN) '" 20V
40V
SOY
J
INPUT VOLTS (V!Nl.l0V
IIII!o..
V
<1<1 -0.3 -75
.- --
'.
\\
-~ ;~;
/
ffi~
ffit!:
\
~
60
80
OUTPUT (mA)
100
FIGURE 15. DISSIPATION LIMITATION (VIN - VOUT vs lOUT)
~~61
---11.:.-",
US!!!
51Gn
a:...I
08:
56
~~a:
::::I
QUIESCENT OUTPUT
CURRENT" 1.5mA
ow
w:=
a:O
Q.
I,(on)
VOUT
-1
"'-
~
VPULSE GEN
100mV/cm
50mA STEP (ILl
-
t(l~s/cm)
FIGURE 16. TURN-ON AND TURN-OFF RECOVERY TIME TEST CIRCUIT WITH ASSOCIATED WAVEFORMS
See Application Note AN6157 for further information
7-37
CA30S5, CA30S5A, CA30S5B
Typical Regulator Circuits
VOUT
(REGULATED
OUTPUT)
NOTE:
,. R, and R2 Selected for
Desired Output
R2
R,
VOUT
V REF ( - R - - )
=
+
0,: Any N·P·N Silicon Transistor that can handle a 2A Load
Current such as 2N3772 or Equivalent
NOTE
1. IL =1.6 + R,. 20(8)........- . . . - -
2KI
50
vJ'
""OUT
RL
..
50l'F
+-!-(50V)
lK
All Resistance Values are in Ohms
0,: 2N2102 or Equivalent
O2: Any P·N·P Silicon Transistor (2N5322 or Equivalent)
0 3 : Any N·P·N Silicon Transistor that can handle the desired
All Resistance Values are in Ohms
D,: 1N4001 or Equivalent
0,: 2N5322 or Equivalent
Load Current (2N3772 or Equivalent)
NOTE:
1. VOUT = (R, + ~) + R,
2. Rscp: Short Circuit Protection Resistance
NOTE:
1. R, = O.7IdMax)
FIGURE 19. TYPICAL SWITCHING REGULATOR CIRCUIT
FIGURE 20. COMBINATION POSITIVE AND NEGATIVE
VOLTAGE REGULATOR CIRCUIT
7·38
CA3277
Dual 5V Regulator with Serial Data Buffer
Interface for Microcontroller Applications
April 1994
Description
Features
o
Dual 5V Regulator
- Your 1 at 5V 100mA - Standby
- Vour2 at 5V 100mA - Enabled
- Regulation Range 6V to 18V
- Bandgap Voltage References
o
Low Quiescent Idle Current, 5001JA Typ.
o
Over-Voltage Shutdown Protection, 20.5V Typ.
o
Reverse Battery Protection, -26V Max.
o
Thermal Shutdown Protection
o
Short Circuit Current Limiting
o
Low Input P.S. Flag and Delayed Reset Control
o
Low Voltage Shutdown Control, Ouput1
o
Ignition Comparator Logic Level Control
o
Data Comparator and 100X Current Mult. Used
as Input/Output Buffers for Remote Serial Data
Communication
The Ignition Comparator senses the voltage level at the IGN IN input
and provides a 5V logic switched output (supply sourced from
OUT1). The Ign~ion Output, IGN OUT can be used to signal a system microcontroller which can respond with a logic switched output
to the CA32n ENABLE input control for OUT2. The OUT1 +5V
Standby Supply of the regulator is normally used as a power supply
for m icrocontroller/memory circuits to preserve stored data when in
the standby mode.To allow for maximum heat transfer from the chip,
the four center leads are directly connected to the die mounting pad.
Refer to AN9302 for further information on CA3277 circuit Applications.
Applications
o
Automotive 5V Regulators and Data Buffers
o
Industrial Controller Remote System
o
Mlcrocontroller and Memory Power Supply
o
Radio, TV, CATV, Consumer Applications
Pinout
The CA32n is a Dual 5V Voltage Regulator IC intended for microprocessor and logic controller applications. It is supplied with features that are commonly specified for sequentially controlled
shutdown and startup requirements of microcontrollers. Over-voltage shutdown, short circuit current limiting and thermal shutdown
features are provided for protection in the harsh environmental applications of industrial and automotive systems. The CA3277 functions
are complementary to the needs of microcontroller and memory circu~s. providing for sustained memory with a 5V standby output.
Ordering Information
TEMPERATURE RANGE
-400 C to +8SoC
PACKAGE
16 Lead Plastic DIP
Functional Block Diagram
CA3277 (PDIP)
TOP VIEW
2
OUT1
+5V
(STANDBY)
BATT
15
OUT2
+5V
(ENABLE)
DATA IN 3
IN
4,5AND
12, 13
=GND
CAUTION: These d9\lices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-39
File Number
2792.4
Specifications CA3277
Absolute Maximum Ratings
Thermal Information
Max. BATT, IGN IN Input Voltage (Note I ) • • • • • • • . • • • • • .. ±26V
Max. Operating Voltage; BATT, IGN IN ••..•••. VBATT(SO) (-20.5V)
Max. Positive Voltages: (For Negative VoRages, Note 2)
ENABLE Input. ...••..••.....•••••....••••••.•.••• VBATT
DATA IN Input •••.•.•••••••.••••.•••••••••.••••••• VBATT
CUR OUT, OUtput. ••••.••••••••••.•..•..•••.••••.• VBATT
RESET, Output ••••.••••••.•••••••.•••..••••••••.. VBATT
Max. Operating Load Current, OUTI ••••..••.•••••••••• lOOmA
Max. Operating Load Current, OUT2 ....•••••..••...... lOOmA
Max. Current Mull. Load Currents:
Min. Load Resistance, CUR OUT •. 2250 to BATT (75mA max)
Min. Load Resistance, CUR IN ...••• I Kn to GND (-5mA max)
Max. Load Current OUT1, OUT2 (Short Duration) ••• SeH-Limiting
Max. PIus/Minus Load Currents: (Note 3)
IGN OUT Output .•••.••••••.••••.••.•.•••••••SeH-Llmlting
DATA OUT Output •••••.•••.••.•...•.......•••SeH-Limiting
RESET Output ••••.••••••••••••.•.•••••...•• SeH-Limiting
Thermal Resistance
8JA
8JL
Plastfc DIP Package ••••••••.•.•. . • • 6O"C/W
12"C1W
(Temp. meas. on center lead next to case)
Power Dissipation, Po (Note 4):
Up to +6O"C (Free Air) ••••••••••••••••••••.••••••••• 1.5W
Above +6O"C: ••••••.••••••.•. Derate Linearly at 16.6mWt'C
Up to +85°C wlheat sink (PC Board): . • • • • • • • • • • • • • • •• 1.6 W
Operating Temperature Range •••••••••••.••••• -'lO"C to +85°C
Storage Temperature Range ••••••.••••.•..••• -55°C to +15O"C
Max. Junction Temperature ••.••••.••.••••........••. +150°C
Lead Temperature (During Solder) •....•••..•.......•. +265°C
1/16 ± 1/32" from case, lOs max
CAUTION: Slr6sses _
thoss listed in "Absolute Maximum Ra#ngs" may cs""e permanent damage to the davIcB. This is a slrBss only rating and opsratlon
of the dBV/ca at these or any other condnions abo... those Ina,c,ded In the operational secUons of this specification Is not Implied.
Electrical Specifications TA = -'10°C to +85"C, v BATT = 13.5V, ENABLE ON (VEN = 3.5V), IGN IN connected to BATT, OUTI and
OUT2 bypassed with 20JlF to GND, DATA IN connected through 2S00 to BATT, LOADS: OUTI = SOmA,
OUT2 = BOmA; Unless Otherwise Specified (Refer to Rgure 4 Test Circuit)
PARAMETERS
SYMBOL
CONOmONS
MIN
TYP
MAX
I UNITS
REGULATOR OUTPUT1
Output Voltage
VOUT1
VBATT = 9V to 16V
4.75
5
5.25
Dropout Voltage (Note 5)
VOO1
VBATT = 4.75V
4.15
4.6
V
-
-
9
40
mV
Line Reg
VBATT = 6.2V to 16V
Load Reg
ILOAD = 0.5mA to 50mA
30
60
mV
170
2SO
mA
-
3.5
-
V
V
-
Current Limiting
Low Voltage Shutdown
Ramp VBATT Down Until OUTI drops (PNP Driver Cutoff)
V
REGULATOR OUTPUT2
Output Voltage
VOUT2
VBATT = 9V to 16V
4.75
5
5.25
Dropout Voltage (Note 5)
VD02
VBATT =5.6V
4.6
5
-
V
7.5
40
mV
Line Reg
VBATT = 6.2V to 16V
Load Reg
ILOAD = O.SmA to BOmA
Current Limiting
ENABLE Input Current
lEN
ENABLE Input Sw. Thd.
VEN(THD)
VEN =5V
Ramp ENABLE Input Up Until OUT2 is
Switched ON
-
35
60
mV
190
250
rnA
SO
ISO
-
1.2
-
JlA
V
BO
100
-
CURRENT MULTIPLIER
ICIN ~ -200JlA
Current Mull. Gain, (lcou..-llcIN)
Gain
Ratio
Current Mull. Output Sal.
VCOUT(SAT)
ICIN = -200JlA, CUR OUT Load = 1Kn to VBATT
-
0.3
1
V
Current Mult., Max. Drive Cur.
ICOUT(MAX)
ICIN = -700JlA
35
SO
-
mA
Ramp VBATT Down, Measure VBATT when
RESET (V RST) goes low
3.B
4.2
4.5
V
CRST Cap. = 0.47JlF, VBATT = 6.BV
RESET Load = SKn to OUT1
50
150
250
rns
-
-
V
0.2
V
B
-
rnA
RESET
Reset, (RST) Threshold
Reset Delay Time (Note 6)
lAST
RESET Out High
VOH(RST)
47KntoOUTI
4
RESET Low
VOl(RST)
VBATT = 3.7SV, RST 47Kn to OUTI
-
RESET Output Sink Current
IOL
CRSTlo GND, VBATT = 6.BV
7-40
-
Specifications CA3277
Electrical Specifications TA =-40"C to +85°C, VBATT =13.5V, ENABLE ON (VEN =3.5V), IGN IN connected to BATT, oun and
OUT2 bypassed with 2O!LF to GND, DATA IN connected through 2500 to BATT, LOADS: OUTl = 50rnA,
OUT2 = 80rnA; Unless Otherwise Specified (Refer to Figure 4 Test Circuit) (Continued)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TVP
VBATT
-3.6
VBATT
-2.9
-
I MAX
UNITS
DATA COMPARATOR
Data Camp Thd
Data Camp Hysteresis
DATA OUTLaw
VOL
VSATT =16V, VOATAIN =(VBATT -5V)
DATA OUT High
VOH
VSATT =16V, VOATA IN =16V
DATA OUT Low Sink Current
IOL
VOATAIN Low
DATA OUT High Source Current
IOH
VOATA IN High
VBATT
-2.2
V
200
-
mV
-
0.15
V
5.25
V
1
-
mA
-50
5.5
6
6.5
V
-
200
-
mV
-
0.15
V
VOUT1
-0.15
-
IJA
IGNITION COMPARATOR
Ign CompThd
Ign Comp Hysteresis
IGN OUT Low
IGN OUT High
VOL
VOH
4.6
IGN OUT Low Sink Current
IOL
VIGNIN Low
IGN OUT High Source Current
IOH
VIGNIN High
Ie
VSATT =12.6V, No Loads, VEN =VIGN IN =OV
VBATT(OVSD)
Ramp VSATT Up Until oun and OUT2 Shutdown
1Vpp at 3kHz on BATT INPUT, Measure AC
Ripple on OUT1, OUT2
-
1
5.25
V
-
rnA
-70
.
-
500
800
IJA
19
20.5
23
V
-
150
45
55
-
dB
-
IJA
OTHER PARAMETERS
Idle Current
Over-Voltage Shutdown
Thermal Shutdown
Ripple Rejection
TJ
°C
NOTES:
1. For negative voltages on the BATT and IGN IN inputs, current drain is primarily reverse junction leakage, except when DATA IN, CUR
OUT, ENABLE and RESET are directly connected to BATT. (Note 2)
2. For negative voltage DATA IN, CUR OUT, ENABLE and RESET interlace to NPN or equivalent on~hip structures; providing a forward
junction for current conduction into the IC. Negative current must be limited by the impedance of the external connection. This is also the
case where these terminals are interconnected to BATT, Normal application does not require the BATT connection, except for DATA IN
where a series diode for reverse current blocking may be used. (see Description text information)
3. Refer to the Electrical Characteristic TABLE for all Self-Umiling values.
4. Dissipation, approximately equals: Po" [(VINIIN) + (VCUR OUrlCUR OUT) - 5(IOUT1+louw), where 'INV1N is IGN IN and BATT input dissipation and VOUT1-VOUT2-5V. This assumes neglibible dissipation for the Ignition Camp., Reset and Data Camp. Outputs.
5. Dropout Voltage is VOO1 = (VSATT - VOUT1) for REG. oun and VD02 = (VBATT - VOUT2) for REG. OUT2
6. Reset Delay Time, tRsT is the time period that the RESET (Pin 8) is low following the discharge of the CRST capacitor to ground. For test
evaluation, the CRST pin may be discharged repetitively with a transistor switch. The RESET pin switches from low to high when the
CRST pin is charged to approximately 3V. Normal ATE testing measures the source charging current which is typically 101JA. For any
other value of Capacitor the charge time, t for reset is determined as follows: t -308C, where C Is in I1F and t is In milliseconds.
(i.e. C = 0.4711F, t = 141ms)
7-41
CA3277
R1
IGNIN
2200
C1
~O.1111'
-=-
------ ---I---- ----- _______ J
-=-
EN
(OUT2)
C3
0.47111'
TO
r---_OUT2
+SV
DISPLAY OR VL.---I
CONTROL
OUTPUT
TOO
CRST
RESET
RDI SENSE CONTROL
IN
OUT
SV MlCROCONTROLLER
RS
47Kn
GND
.J.
FiEsET
VDD
+SV
CMOS
MEMORY
BUS
NOTE: DATA IN and CUR OUT are remote/host Serial Data Communication Buffers. lYplcal Remote Source
Impedance for DATA IN Is 1kO. Typical Remote Load for CUR OUT Is 2500.
FIGURE 1. TYPICAL APPLICATION CIRCUIT OF THE CA3277 DUAL 5V REGULATOR WITH MICROCONTROLLER AND SERIAL
DATA BUFFER INTERFACE TO A REMOTE HOST
Applications
Other functions of the CA3277 include a Data Comparator
and Current Multiplier for use as interface buffers to transfer
serial data at higher level logic to and from a remote host
microcontroller. The OUT1 5V Standby Supply provides
power to the local microcontroller which interfaces to the
CA3277 interface buffers at a 5V logic level. As shown in
Figure 1, the DATA IN input of the Data Comparator receives
serial data referenced to the BAn voltage level. The output
of the Data Comparator is 5V CMOS compatible logic and is
connected to the RDI (remote data input) terminal of the
microcontroller. The TOO (data out) output of the microcontroller is connected to the Current Multiplier input of the
CA3277.
Current Multiplier - The Current Multiplier, with internal circuitry shown in Figure 2, receives data from the
microcontroller in the form of an open drain or gate switched
output driving a 22KO resistor load in series to the Current
Input at pin 10 (CUR IN). The input stage of the Current Multiplier is a current mirror amplifier which is internally
connected to the 5V regulated OUT1 voltage source. The
output stage of the Current Multiplier is a current mirror
amplifier referenced to GND and has an open collector
Current Output at pin 9 (CUR OUn, with a minimum drive
capability of 35mA. The Current Multiplier output load is
normally connected via resistive loading to the BAn voltage
supply level. As such, the microcontroller transmits data out
(TOO output) to the input of the CA3277 Current Multiplier
which amplifies and translates the signal back to the voltage
reference level of the BAn power supply input. When
driving a similar remote CA3277, the voltage drop from the
BAn input line switches the Data Comparator which
provides serial data to the RDI input of the remote microcontroller. The nominal current gain of the Current Multiplier is
100X.
The application use of the Current Multiplier is not limited to
digital serial data transfer. The Current Multiplier is an
independent function and is open to use for other purposes,
including linear signal amplification, sensor output amplification and current controlled threshold switching. The current
output terminal, CUR OUT may be externally loadconnected to OUT1, OUT2, BAn or any other power supply
level up to the maximum ratings given for the BAn input
terminal. It is important to note that some applied uses of the
Current Multiplier may contribute Significant on-chip power
dissipation. A nominal current mirror input drive of 200f.l,A will
provide sufficient drive to switch a 2500 resistor load at the
input of the data comparator. As such, the quiescent OFF
condition of the Data comparator should be in the High state.
7-42
CA3277
r------------
CA3277
2500
DI ......CO-,'--£'
CUR
IN
10
l
ICIN
GND
,
,
Q103 ,:
,,
,
,,
,,
4,5AND
12,13 : _________________ : ___
5100
CUR
OUT
8
,,
,
,,
: CA32n
: REMOTE
:, SYSTEM
-----------_.
J
FIGURE 2. CURRENT MULTIPLIER DRIVING A REMOTE
CA3277 DATA COMPARATOR
Data Comparator - The Data Comparator provides a means
of translating serial data from a high to low voltage. The
DATA IN terminal of the Data Comparator is biased to
receive signal input that is source referenced to the BATT
supply voltage level. In normal use the signal input would be
supplied from a remote Current Multiplier having a resistor
load tied to the BATT voltage supply. The DATA OUT output
from the Data Comparator is CMOS compatible 5V noninverting logic data referenced to GND. The switching
threshold at the DATA IN input is bias stabilized by the bandgap voltage and is typically at (VSATT - 2.9V). The Data
Comparator is in a high state when DATA IN input is at the
BATT voltage level and is in a low state when DATA IN is at
(VBATT - 5V). The output stage of the Data Comparator is
internally supply biased from the Switched 5V Regulator
output to provide a high state of 5V and a low state of OV
(GND). The DATA OUT terminal can typically sink 1.2mA in a
low state or source 501lA in a high state.
In system applications the Data Comparator is used to
translate remote data at high voltage down to 5V logic levels.
The Current Multiplier is used to reverse the process by
translating 5V logic data back to the BATT voltage level
when sending data back to the remote system. The Data
Comparator and Current Multiplier are level matched for
remote communication between microcontroller systems
using the common BATT power supply voHage of the
CA3277. The current driven serial data from the Current
Multiplier is sent to a remote system by translating the signal
up to the BATT voltage level, or an external power supply
level that is compatible with the remote device. The Data
Comparator of the remote system receives the data,
interfaces to its microcontroller and responds with signal
drive from its Current Multiplier to translate the signal back to
the host. For best noise immunity the transmission in each
direction should be over a twisted pair or shielded line. As
such, two microcontrollers, each with the interface protection
of a CA3277, can provide intelligent master/slave system
communications under adverse environmental conditions.
Ignition Comparator - While the Ignition Comparator is provided as an essential part of the start-up control in automotive systems, this circuit function may be used as an
independent switching comparator. It Is Important to note
that the thermal shutdown feature on the chip Is disabled when the IGN IN Input Is low. Disabling of the onchip thermal protection is done to satisfy the requirement of
low idle current when the system is in a standby condition.
The non-inverting IGN IN input has a switching threshold of
typically 6V with 200mV of hysteresis and is switched with
logic levels reference to GND as the low state and BATT as
the high state. The IGN OUT output is 5V CMOS compatible
logic, equivalent to the Data Comparator output stage, but is
internally supply biased from the Standby 5V Regulator. As
such, the high state is level referenced to OUT1. The IGN
OUT output terminal can typically sink 1.2mA in a low state
or source 701lA in a high state.
Enable - A CMOS or TTL high at the ENABLE input
switches the regulated 5V1Switched Output ON at OUT2.
The ENABLE input has an internal pull-down of typically
501lA to ensure that OUT2 is OFF when the ENABLE input
is not connected. The input threshold level for switching is
the bandgap voltage reference of 1.2V. When the ENABLE
input is low, all drive current to the output pass transistor is
cutoff and OUT2 voHage drops to ground level. The ENABLE
input is normally switched from the interfacing microcontroller but may be activated from a remote source.
Reset - The purpose of the Low Voltage Reset function is to
flag a low voltage condition at OUT1. When the RESET output, pin 8 switches low, the voltage level at OUT1 has
dropped below the regulation level. The CRST and RESET
are high when OUTl is at 5V. When OUTl drops to less than
4.2V (typical), the CRST Capacitor at pin 7 is internally
discharged, causing the RESET pin to change from a high to
a low state, outputting a negative going pulse. The RESET
output is an NPN open collector driver requiring an external
load resistor, normally connected to OUT1. The RESET
output flag may be sent to a microcontroller to initiate a
power-down sequence. For any condition that causes OUT1
to drop below the reset threshold, such as undesired
transients, the RESET output is switched low for a delay
period, tRST determined by the value of the external
capacitor, CRST at CRST terminal. For a value of O.47~F the
delay period is typically 141ms. This correlates to approximately IOIlA of charging current sourced from the CRST
terminal to charge CRST'
Regulation - The regulated output stages of the CA3277
have similar circuits, each having an error amplifier to
compare the output voltage to the bandgap reference
voltage. The circuit of the 5V1Switched regulator is shown in
Figure 3. By feedback, the output voltage is differentially
compared to the bandgap reference voltage. The error signal
is then amplified to drive a PNP pass transistor and maintain
a stable 5V output with both line and load regulation over the
full operating temperature range. Except for the ENABLE
control of OUT2, the
drive circuit is similar to the
OUT2 circuit.
oun
7-43
CA3277
oun
Protection· Both
and OUT2 PNP output pass transistors are protected with Over-Voltage Shutdown and OverTemperature Shutdown. Current Limiting for each output is
independent and is accomplished by limited drive current
from the pre-drivers (Q135 for OUT2) to the PNP output
pass transistor (Q136). Over-Voltage is sensed as a threshold voltage level at the BATT input. Both output stages are
shutdown when the VBATI voltage level is typically greater
than 20.5V. When the Ignition voltage is high, the Over-Temperature level is sensed as VBE changes and compared to
the bandgap reference voltage. When the chip temperature
exceeds 150"C, both output stages are shutdown. When
Over-Voltage or Over-Temperature thresholds are exceeded,
the sensed states are ORd to switch OFF drive to the output
stages. The ENABLE control for OUT2 is added to the OR
control of the OUT2 drive circuit. The Low Voltage Shutdown
control is added to the OR control of the OUT1 drive circuit.
Low Voltage Shutdown occurs at approximately 3.5V as the
BATT supply input is ramped down, forcing cutoff of the PNP
output pass transistor. The external capacitor on OUT1
holds charge, with a long RC time constant delay to sustain
shutdown control in the microcontroller. The internal shunt
resistance at the OUT1 terminal is typically 148Kn.
Under conditions of reverse battery or negative supply
voltages on the BATT input, current in the IC is primarily
reverse junction leakage. The design of the CA3277 is
configured to prevent high current if the power supply is
reversed. Exceptions to this are preventable. One example is
current through the DATA IN input line terminating resistor,
normally connected directly to the BATT supply line. This
provides a path for current conduction into the IC through an
Internal diode junction. The current is limited by the external
resistor and may be as high as 100mA at -26V. Where
negative supply voltages are potentially a problem, the
resistive load from DATA IN to BATT can be in series with a
reverse voltage blocking diode, such as a 1N914. This input
diode-resistor circuit is shown in Figure 2 as the remote
interface and load to the Current Multiplier output.
Dissipation • The CA3277 device dissipation is the combined watts of input voltage times current less the external
watts of power supplied by the chip. For normal use, the
major contribution to on-Chip dissipation is primarily the
BATT input dissipation. The Current Multiplier output has a
potential to add significant dissipation. The open collector
driver of the Current Multiplier Output, pin 9 mayor may not
be in saturation when sinking current. Because it is a current
mirror output with a constant current drive, the voltage may
be increased on pin 9, with a significant increase in the
resulting dissipation. The chip dissipation is approximately
equal to:
where I,NV,N is IGN IN and BATT input dissipation, assuming
VBATI = V,GN IN, and VOUT1 - VOUT2 - 5V. This assumes
negligible dissipation for the Ignition Comparator, Data
Comparator and Reset outputs.
OUT2 PASS
TRANSISTOR "TOBATI+----~---------~r----------~~---------~------~~~
15 OUT2
'i-~p--o +5V
R32
6.4K
EN INPUT
7
R33
6.4K
OVER-VOLTAGE
SHUTDOWN
FIGURE 3. OUTPUT2 DRIVER AND ERROR AMPLIFIER WITH THE ENABLE CONTROL
7-44
CA3277
VSATT
-
c
J
15
INPUT VOLTAGE (V)
I
8
6
~
4
~
2
~\
o
2.5
20
TA ,,+250C, RL1
=1Don, RL2 =62n
Z
e.
I-
i3
0.2
... ::>
j:'U
8a:
3~~~~r--t--+--i--;--_t
::>
4
U
10
15
IGN IN INPUT VOLTAGE (V)
J-OVER-VOLTAGE
SHUTDOWN
TA" +250C, VSATT • 13.5V
30 CUR OUT THROUGH 250n TO BATT
ENABLE AND IGN IN TO BATT
-w
"'a:
:!:a: 15
2~--tr_-r-~~~+--i--;--_t
5
~I
NORMAL
OPERATING RANGE
~<" 25
I-E
=>- 20
01'Z
I- 0.3 t---'-::::::;o...,"'----1I::::;;00...'T---+--ff--.::-t--_t
::>
:!:
~ 0.1
I-
22.5
35
S2"
a:
...
20
FIGURE 4B. TYPICAL CHARACTERISTICS CURVES FOR NOLOAD BATT INPUT CURRENT vs BATT INPUT
VOLTAGE FOR OFF STATE IDLE CURRENTS
1) BATT TO 16V, ENABLE TO oun - r - - + - - + - - I
<" 0.5 2)
§.
BATT TO 11 V, ENABLE TO oun
3) BATT TO 16V, ENABLE TO GND
~
4) BATT TO 11V, ENABLE TO G~N~D~"'f-_-+_-If----1
~ 0.4
:
10
15
INPUT VOLTAGE (V)
5
~
LOW VOLTAGE
DROPOUT
FIGURE 4A. TYPICAL CHARACTERISTIC CURVES FOR OUT1
AND OUT2 OUTPUT VOLTAGE vs BATT VOLTAGE
INPUT
1-
1\ '--"
5
oV
lL
V
V
/
TEST NOTE:
MEASUREMENTS MADE
AS VOLTAGE ON son LOAD
FROM CUR OUT TO 5V
I
I
I
I
o
0.1
0.2
0.3
0.4
CUR IN (PIN 10) -INPUT (SOURCED) CURRENT (mA)
20
FIGURE 4C. TYPICAL IGN IN CURRENT vs IGN IN INPUT VOLTAGE
10
V
V
FIGURE 40. TYPICAL CURRENT MULTIPLIER CURRENT GAIN
CHARACTERISTIC
7-45
CA3277
TA. +25oC, ENABLE HIGH; IGN IN TO BATT
DATA IN THROUGH 2500 TO BATT
__
1) OUTl • OU12. 500
2) OUTl • 1000, OUT2 • S20
3) OUT2. 620, OUT1 OPEN
4) OUT1 • 11114!2: OU12 OPEN
!i 15
II! ,:;
1.00
--
ex: -
;\! ...
_E
-
~; 10
0.08
I
:>N
i:6
, - - - ............ - 2
0.84 I---il+---If---+--il""'c::+--+-+--I
I(
C
O~~---L~~
5
---
0." t--t-t;::::;t--=t=::-+-t--t--i
r~~ 5,=+=-n'l=l=~=l=*~
I-~-t--~
i
o
TA. +2rC, ENABLE HIGH
IGN IN TO BATT, VBATT.13.5V
DATA IN THROUGH 2500 TO BATT
1) Iourt VARIED, 0UT2 - NO LOAD
2) Ioun VARIED, OUT1 - NO LDAD
__~~~~---L~
10
15
INPUT VOLTAGE (V)
........
1
D.1121---,+-+-+-+--+--+--1-----I
0.00 O~.......'----:50~-'----:l'=00:--L--:l~50:-......-
20
......
OUTPUT CURRENT (rnA)
FIGURE 4E. TYPICAL CHARACTERISTIC CURVES FOR COMMON
(GROUND) CURRENT vs BATT VOLTAGE INPUT
WITH OUTPUT LOAD
FIGURE 4F. TYPICAL atARACTERIS11C CURVES FOR CURREN!"
TRANSFER EFFICIENCY OF Iourtl\N AND Iour.AN
WHERE Iw ~UDES (\aN IN + ioATA tJ BIAS CURRENTS
7-46
HIP5060
Power Control IC
Single Chip Power Supply
April 1994
Features
Description
• Single Chip Current Mode ControllC
The HIP5060 is a complete power control IC, incorporating both the high
power DMOS transistor, CMOS logic and low level analog circuitry on the
same Intelligent Power IC. Both the standard "Boost" and the "SEPIC"
(Single-Ended Primary Inductance Converter) power supply topologies
are easily implemented with this single controllC.
• GOV, 10A On-Chip DMOS Transistor
• Thermal Protection
• Over-Yoltage Protection
• On-Chlp Reference Voltage· 5.1V
Special power transistor current sensing circuitry is incorporated that
minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to
monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage.
• Output Rise and Fall Times - 3ns
As a result of the power DMOS transistor's current and voltage capability
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
(lOA and 60Y), power supplies with output power capability up to 100
watts are possible.
• Designed for 27V to 45V Operation
Applications
Ordering Information
• Single Chip Power Supplies
PART NUMBER
TEMPERATURE RANGE
PACKAGE
HIP5060DY
OOC to +85°C
37 Pad Chip
HIP5060DW
oOC to +85°C
Wafer
• Current Mode PWM Applications
• Distributed Power Supplies
• Multiple Output Converters
Chip
e
0
II.
li
:;
z
:;;II.
III
9:
5:
!2.
:!it.
z
~
(8) VDDA
FlTH (37)
VREG(36)
(9)V+
VCMP (35)
(10) SlCT
PSOK(34)
(ll)CKIO
SHRT(33)
(12) DGDl
PSEN (32)
(13) VooP
!!!!!!!J!!!!!!!I_lIiiiiiiiOl.~ (14) VOOP
TMON
(31)
.11 . . . . . . . . . . . . . . . . 11 •
NOTE: Unused pads are for trim and test.
153 mils x 165 mils (3.88mm x 4.19mm)
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-47
File Number
3207.1
HIP5060
Simplified Block Diagram
4,.H
4"H
1.1""
VIN
100""
V+
O.l"F
30.1K
4,.H
CLOCK
AND
CONTROL
LOGIC
VCUP
FlTN
PSOK
0.033"F
SHRT
VREG
AMP
PSEN
0.1"F
VOOP
mON
VOOP
0.1"F
VINP
DGD1
AGND
CKiO SLCT VDDA
VDDD
IRF1
IRFO
SFST
TYPICAL SEPIC CONFIGURATION
7·48
0.88"F
Specifications HIP5060
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, v+ •.••..........•.••.•••... ..().3V to 45V
DMOS Drain Voltage ••....••••..•••.••••••..•• ..().3V to 60V
DMOS Drain Current •.•.•••••••.••••••••••.••••..•••• 20A
DC Logic Supply ..•.•...•••••••••••••••••••••• ..().3V to 16V
Output Voltage, Logic Outputs .....•....••••••••. ..().3V to 16V
Input Voltage, Analog and Logic •••••.•.•.•••••••. ..().3V to 16V
Operating Junction Temperature Range •..•.••.••• O"C to + 110°C
Storage Temperature Range •••....•.•••••••. -55"C to +1 SOOC
Thermal Resistance
9JC
(Solder Mountad to . • • • • • • • • • • • . • . . • • • • • . . •• 3°CIW Max
0.050" Thick Copper Heat Sink)
Maximum Junction Temperature .•.•....•.••.......•.. +11 OOC
(Controlled By Thermal Shutdown Circuit)
CAUTION: S/rIlSSSS above those "sted in "Absolute Maximum Rafings" mey cause permanent damage to the device. This is a stress only ra6ng and op8ra6on
of the device at these or any other conditions above thoss Indicated in the op8ra60nal sections of this speciflca60n is not imp/ied.
Electrical Specifications v+ = 36V, TJ = OOC to +ll00C; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
Supply Current
PSEN= 12V
-
19.5
32
mA
Internal Regulator Output
Voltage
V+= 15Vto 45V, lOUT = 10mA
11.0
-
13.2
V
VINP
Reference Voltage
lylNP = OmA
5.01
5.1
5.19
V
RylNP
VINP Resistance
VINP=O
-
900
-
0
Input Offset Voltage
(VREG - VINP)
lycMP = OmA
-
-
10
mV
R1NVREG
Input Resistance to GND
VREG=5.1V
-
56
-
kO
Om (VREG)
VREG Transconductance
lyCMP"(VREG - VINP)
VCMP = 1V to SV, SFST = 11V
15
30
50
mS
gm (SFST)
SFST Transconductance
IYCMpI(VREG - SFST)
VSFST < 4.9V
O.S
-
6
mS
lyCMP
Maximum Source Current
VREG = 4.95V, VCMP = SV
-2.5
mA
Maximum Sink Current
VREG = 5.25V, VCMP = 0.4V
0.75
2.5
mA
OVTH
Over-Voltage Threshold
Voltage at VREG for FLTN to be
latched
6.2
-
.().75
lycMP
6.7
V
Internal Clock Frequency
SLCT = OV, Vooo = 12V
0.9
1.0
1.1
MHz
External Clock Input Threshold
Voltages
SLCT= 12V
33
-
66
%Vooo
1+
VOOA
ERROR AMPLIFIERS
IVIOI
CLOCK
fq
VTHCKIN
DMOS TRANSISTORS
roS(on)
loss
Drain-Source On-State
Resistance
I Drain = SA, TJ = +25°C
-
-
0.13
0
Drain-Source Leakage Current
Drain to Source Voltage = 60V
-
1
100
IIA
IRFO = OmA to -5mA,
VCMP = O.2V to 7.6V
-
-
125
mV
100
-
270
mV
CURRENT CONTROLLED PWM
IVIOIVCMP
Buffer Offset Voltage (VCMPV1RFO)
VTHIRFO
Voltage at IRFO that disables
PWM. This Is due to low load
current
7-49
Specifications HIP5060
Electrical Specifications V+ = 36V, TJ = oOC to +110oC; Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
7.4
-
8.0
V
-37
-
-17
J1A
4
6
8
V
-
4.9
AlmA
CURRENT CONTROLLED PWM (Continued)
ITHIRFO
Voltage at IRFO to enable SHRT
output current. This is due to
Regulator Over Current Condition
ISHRT
SHRT Output Current, During
Over-Current
VTH SHRT
Threshold voltage on SHRT to
set FLTN latch
IGAIN
RIRFI
tRs (Note 1)
VIRFO = 8.1V
IpEAK (DMOSORAlN)/IIRFI
al (DMOSORAlN)/at = 1Alms
3.8
IRFI Resistance to GND
IIRFI=2mA
150
-
360
Q
-
30
-
ns
Current Comparator Response
Time
dI (DMOSORAIN)/at> lA1I'S
MCPW
(Note 1)
Minimum Controllable Pulse
Width
25
50
100
ns
MCPI
(Note 1)
Minimum Controllable DMOS
Peak Current
200
400
800
rnA
V+
Rising V+ Power-On Reset
Voltage
22
-
27
V
V+
Falling V+ Power-Off Set
Voltage
-
15
-
V
V+
V+ Power-On Hysteresis
START-UP
VTH PSEN
Voltage at PSEN to Enable
Supply
rpSEN
Internal Pull-Up Resistance, to
5.1V
ISFST
Soft-Start Charging Current
VSFST = OV to 10V
IpSOK
PSOK High-State Leakage
Current
SFST = OV, PSOK = 12V
VpSOK
PSOK Low-State Voltage
SFST = l1V, IPSOK = lmA
VTHSFST
9
-
12
V
0.8
-
2.0
V
-
20
-
KQ
-1.0
-0.7
-0.4
J1A
-I
-
I
J1A
-
-
0.4
V
II
V
135
°C
9.4
PSOK Threshold, Rising VSFST
THERMAL MONITOR
TEMP
(Note 1)
Substrate Temperature for
Thermal Monitor to Trip
TMON pin open
NOTE:
1. Determined by design, not a measured parameter.
7-50
105
HIP5060
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1
AGNO
Analog ground.
2
VINP
Internal 5.1 V reference.
3
SFST
Controls the rate of rise of the output voltage. TIme Is determined by an internal 0.711A current
source and an external capacitor.
4
IRFO
A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current
sense comparator. The maximum current Is set by the value of the resistor, according to the
equation: IpEAK =321R. Where R Is the value of the external resistor in Kn and must be greater
than 1.5Kn but less than 10Kn. For example, If the resistor chosen is 1.8K, the peak current will
be 17.8A. This assumes VCMP Is 7.3V. Maximum output current should be kept below 20A.
5
IRFI
SeelRFO
6
DG02
Ground of the OMOS gate driver. This pad Is used for bypassing.
7
Vooo
Voltage Input for the chip's digital Circuits. This pad also allows decoupllng of this supply.
This is the analog supply and internal 12V regulator output.
8
VODA
9
V+
This is the main supply voRage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.711F capacitor and may be composed of seven,
single 0.111F chip capacitors.
10
SLCT
This pad provides for the option of using either internal 1MHz operation of for an external clock.
Floating or grounding this pad will place the Internal clock at the CKIO pad. Returning this terminal to Vooo or 12V will allow application of an external clock to the IC via the CKIO pad. There
Is an internal 50K pull down
11
CKIO
Clock output when SLCT is floated or grounded. External clock input when SLCT Is returned to
12V.
12
OG01
This pad Is the return for the digital supply.
13 & 14
Voop
These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a 0.111F chip capacitor placed close to this pad and the OMOS
source pads.
15,16, 19,20,
23,24,27,28
S
Source pads 01 the OMOS power transistor.
17,18,21,22,
25,26,29,30
0
Drain pads of the OMOS power transistor.
31
TMON
This Is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into
the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a
nominal junction temperature of +125"C.
32
PSEN
This terminal Is provided to activate the converter. This terminal may be left open or returned to
5V for normal operation. When the Input Is low, the OMOS driver is disabled.
33
SHRT
2511A is internally applied to this node when there is an over-current condition.
34
PSOK
This pad provides a delayed positive indication when the supply is enabled.
35
VCMP
OUtput of the transconductance amplifier. This node is used for both gain and frequency compensation of the loop.
36
VREG
Input to the transconductance error amplifier is available on this pad. The other input is internaliy
connected to the S.1V reference, VINP, Pad 2.
37
FLTN
This is an open draIn output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current Is experienced.
7-51
HIPS060
Functional Block Diagram
.--WIr-" VREF
13Kll
IRFO
VCMP
7-52
B
IRFI
HIP5061
7 A, High Efficiency Current
Mode Controlled PWM Regulator
April 1994
Features
Description
• Single Chip Current Mode ControllC
The HIP5061 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog Circuitry on the same Intelligent Power IC. The
standard "Boosr, "Buck-Boosf', "Cuk", "Forward", "Flyback"
and the "SEPIC" (Single-Ended Primary Inductance Con·
verter) power supply topologies may be implemented with
this single controllC.
• 60V, On-Chip DMOS Power Transistor
• Thermal Protection
• Over-Current Protection
• 250kHz Operation
Over·temperature and rapid short-circuit recovery circuitry is
incorporated within the IC. These protection circuits disable
the drive to the power transistor to protect the transistor and
insure rapid restarting of the supply after the short circuit is
removed.
• Output Rise and Fall Times -10ns
• On-Chlp Reference Voltage - 5.1V
• Slope Compensation
• Vee Clamp Allows 10.8V to 60V Supply
• Supply Current Does Not Increase When Power
Device Is On
Applications
As a result of the power DMOS transistors current (7A at 30%
duty cycle, 5A DC) and 60V capability, supplies with output
power over 50W are possible.
Ordering Information
• Distributed I Board Mounted Power Supplies
• DC - DC Converter Modules
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
HIP5061DS
OOC to+85OC
7 Lead Staggered 'Gullwing" SIP
• Voltage Inverters
• Small Uninterruptable Power Supplies
• Cascode Switching for Off Une SMPS
Simplified Functional Diagram
Pinout
HIP5061 (SIP)
TOP VIEW
VIN _-_-~rm"----_--~~-_~-+
Your
PIN 7 Voo
PIN6VG
o
PIN 5 DRAlN
'--~--'___--I-"""" E~ i~:RC~E
"
'"
SOURCE
(TAS)
DO NOT
USE
GND I-~>-'-'--+
~----------------------~~
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-53
File Number
3390.2
Specifications HIP5061
Absolute Maximum Ratings (Note 1)
Thermal Information
DC Supply Voltage, Voo •...•.••••••••••••.•.••• -O.3V to 16V
DC Supply Current, 100 .••..•.•.••..•..•.•..•.•••... 10SrnA
DMOS Drain Voltage ......•.•••.•...•...•••••• -O.3V to 60V
Average DMOS Drain Current .•••••..••••.•••.•••...•••. SA
DMOS Source Voltage, VSOURCE, TAB .••....•••... -O.W to 0.1 V
DC Supply Voltage, VG' ••..••.••••.•.•.••• -0.3V to Voo + 0.3V
Compensation Pin Current, Ivc ••••••••••••.•••• -5mA to 35rnA
Voltage at All Other Pins•.•.•••••••••••...• -0.3V to Voo + 0.3V
Op!lrating Junction Temperature Range•.•.•••••.• O"C to +1 O5°C
Storage Temperature Range •••..•.•••..•••.• _55°C to +150°C
ESD Classification .••.•••••••.•.••••.••.•••• , Class 2 - 2KV
Single Pulse Avalanche Energy Rating, lIS (Note 2) ••• EAS 100mJ
Thermal Resistance
9JC
Plastic SIP Package •••. • • • • • • • • • • . • • • . . . • • .
2"CIW
Maximum Package Power Dissipation at +850 C
(Depends Upon Mounting, Heat Sink and Application) •..•. 10W
Max. Junction Temperature •••••••••••.••.•••••..••.. +105°C
(Controlled By Thermal Shutdown Circuit)
Lead Temperature (Soldering 10s) •..•.•.•.•..••..••.. +265°C
CAUTION: Str8SSes above those Hsted in "Absolute Maximum RaOngs" may cause permanent damage to the device. This is a stress only rating and ""eraOon
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
voo = vG =12V, ve = 5V, VFS = 5.W, SOURCE = GND = DRAIN = OV, TJ = oOC to +1050 C,
Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
100
Quiescent Supply Current
Voo = VG = 13.2V, Vc = OV,
VFS =4V
6
12
18
rnA
rnA
100
Operating Supply Current
Voo=VG= 13.2V, Vc =8.5V, VFs =4V
-
24
31
IVG
Quiescent Current to Gate Driver
Voo = VG = 13.2V, Vc = OV
0
10
IlA
IVG
Operating Current to Gate Driver
Ve=3V
-
1
2
rnA
Vooc
Clamp Voltage
100 = 100rnA
13.3
14
15
V
VREF
Reference Voltage
Ive = 01lA, Ve = VFS
5.0
5.1
5.2
V
Input Current
VFB = VREF
AMPLIFIERS
IIFsl
gm (VFS)
VFS Transconductance
IVC/(VFB - VREF)
-
-0.85
0.5
IlA
/lvc / = 5001lA, Note 3
20
30
43
mS
IVCMAX
Maximum Source Current
VFB = 4.6V
-4
-1.8
-1
rnA
IVCMAX
Maximum Sink Current
VFB = 5.6V
1
1.8
4
rnA
Voltage Gain
/lvc / = SOOIlA, Note 3
44
50
-
dB
AoL
VCMAX
Short Circuit Recovery Comparator Rising Threshold VOltagB
S.4
6.6
8.9
V
VeHYS
Short Circuit Recovery
Comparator Hysteresis Voltage
0.7
1.1
1.8
V
0
10
25
rnA
210
250
290
kHz
-
0.15
0.22
Q
-
-
0.33
Q
0.5
10
IlA
-
5
A
200
-
pF
IVCOVER
Vc Over-Voltage Current
Voo = VG = 10.8V, Vc = VCIoW<
CLOCK
fq
Internal Clock Frequency
DMOS TRANSISTOR
rOS(ON)
Draln-Souree On-Stale
Resistance
lORAIN = SA, Voo = VG = 10.8V
TJ= +25°C
rOS(ON)
Drain-Source On-State
Resistance
lORAIN = SA, Voo = VG = 10.8V
TJ = +105°C
loss
Drain-source leakage Current
VORAIN = 60V
IOSH
Average Drain Short Circuit
Current
VORAIN = 5V, Note 4
-
Note 4
-
CORAIN
DRAIN Capacitance
7-54
Specifications HIP5061
Electrical Specifications
voo = vG =12V, ve = 5V, VF8 = 5.1V, SOURCE = GND = DRAIN = OV, TJ = OOC to +105°C,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TVP
MAX
UNITS
CURRENT CONTROLLED PWM
!Im(Vd
&IORAIN• PEAK I&Ve
Note 3
1.4
2.2
3.0
AN
VII REF
Voltage to Current Converter Reference Voltage
lORAIN = 0.2M, Note 3
2.4
2.8
3.1
V
Current Comparator Blanking
TIme
Note 3
40
100
175
ns
tBT
IoNMIN
Minimum DMOS "ON" TIme
Note 3
60
150
250
ns
IoFFMIN
Minimum DMOS "OFF" Time
Note 3
40
125
200
ns
MinCI
Minimum Controllable DMOS
Peak Current
Note 3
-
100
250
mA
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 6% to 30%, Note 3
7
9.5
12
A
MaxCl
Maximum Controllable DMOS
Peak Current
Duty Cycle = 30% to 96%, Note 3
5
8
12
A
CURRENT COMPENSATION RAMP
&1I&t
Compansation Ramp Rate
&IORAIN. PEAK/&TIrne, Note 3
-1.4
-0.85
-0.45
A/jJS
tRO
Compensation Ramp Delay
Note 3
1.3
1.5
1.8
jJS
START-UP
VOOMIN
Rising Voo Threshold Voltage
V FB =4V
9.3
10.3
10.8
V
VOOHYS
Power-On Hysteresis
VFB =4V
0.3
0.45
0.6
V
1.0
1.5
2.0
V
4V < Voo < 10.8V, Ve = 0.8V
50
500
3000
n
Substrate Temperature for
Thermal Monitor to Trip
Note 4
105
-
145
°C
Temperature Hysteresis
Note 4
-
5
-
°C
VeEN
Enable Comparator Threshold
Voltage
Rve
Power-Up Resistance
THERMAL MONITOR
TJ
TJHy
NOTES:
1. All Voltages relative to pin I, GND.
2. Vo = 10V, Starting TJ = +25°C, L = 4mH, IpEAK = 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
TABLE 1.
CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
VoM
IL
(PEAK AMPS)
L(mH)
EAS(mJ)
10
5
40
550
10
7
4TZ
120
6
10
0.33
18
6
12.5
0.14
12
NOTE:
7
0
HIP5061
~
1
VAFfY tp TO OBTAIN
REQUIRED PEAK IL
0000
- IL- -!,.+
- V
y_ D
*-
12~
tp
Device Selected to Obtain Peak Current without Clocking
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
7-55
HIP5061
Definitions of Electrical Specifications
Refer to the Functional Block Diagram of Figure 1 for locations of functional blocks and devices.
Device Parameters
100 • Quiescent Supply Current - Supply current with the
chip disabled. The Clock. Error Amplifier. Voltage-ta-Current
Converter. and Current Ramp circuits draw only quiescent
current. The supply voltage must be kept lower than the
turn-on voltage of the VDO clamp or else the supply current
increases dramatically.
100 • Operating Supply Current - Supply current with the
chip enabled. The Error Amplifier is drawing its maximum
current because VFB is less than its reference voltage. The
vOltage-to-current amplifier is drawing its maximum because
Ve is at its maximum. The ramp circuit is drawing its maximum because ~ is not being disabled by the DMOS transistor turning off.
IVQ • Quiescent Gate Driver Current - Gate Drivers supply
current with the IC disabled. The Gate Driver is not toggling
and so it draws only leakage current.
IVQ • Operating Gate Driver Current - Gate Drivers supply
current with the IC enabled. The DMOS transistor drain is
loaded with a large resistor tied to 60V so that ~ is swinging
from OV to 60V during each cycle.
VODC • Voo Clamp - Voo voltage at the maximum allowed
current through the Voo Clamp.
VREF • Reference Voltage - The voltage on FB that sets the
current on Veto zero. This is the reference voltage for the
DCIDC converter.
Amplifiers
IIFBI. Input Current - Current through FB pin when it is at its
normal operating voltage. This current must be considered
when connecting the output of a DC/DC convertor to the FB
pin via a resistor divider.
gm(VFB). Transconductance - The change in current
through the Ve pin divided by the change in voltage on FB.
The gm times the resistance between Ve and ground gives
the voltage gain of the Error Amplifier.
IVCMA)(. Maximum Source Current - The current on Ve
when FB is more than a few hundred millivolts less than
VREF •
IVCMA)(. Maximum Sink Current - The current on Ve when
FB is more than a few hundred millivolts more than VREF •
AoL' Voltage Gain - Change in the voltage on Ve divided by
the change in voltage on FB. There is no resistive load on
Ve. This is the voltage gain of the error amplifier when gm
times load resistance is larger than this gain.
VCMA)(. Vc Rising Threshold - The voltage on Vc that
causes ine Voiiage-ia-Curreni Ampiifier to reach full-scale.
When Ve reaches this voRage. the Ve NMOS transistor (transistor with ns drain connected to the Ve pin in the Functional
Block Diagram of Figure 2) turns on and tries to lower the voRage on Ve.
VCHYs • VCMA)( Hysteresis - The voRage on Ve that causes
the NMOS transistor to turnoff if n had been turned on by Ve
exceeding VCMAX' At this voltage the current out of the Voltageta-Current Converter is at roughly three quarters of full-scale.
IVCOVER. Vc Over-Voltage Current - The current drawn
through the Ve pin after the NMOS transistor is turned on
due to excessive voltage on Ve. The NMOS transistor connected to the Ve pin draws more than enough current to
overcome the full scale source current of the Error Amplifier.
Clock
fq. Frequency - The frequency of the DCIDC converter. The
Clock actually runs faster than this value so that various control signals can be internally generated.
DMOS Transistor
rOS(ON)' "On" Resistance - Resistance from DMOS transistor Drain to Source at maximum drain current and minimum
Gate Driver voltage. VG.
loss. Leakage Current - Current through DMOS transistor
at the Maximum Rated Voltage.
Current Controlled PWM
gm(Vd. Transconductance - The change in the DMOS transistor peak drain current divided by the change in voHage on
Ve. When analyzing DClDC converters the DMOS transistor
and the inductor tied to the drain are sometimes modelled as
a voltage-controlled current source and this parameter is the
gain of the voltage-controlled current source.
vnREF • Current Control Threshold - The voltage on Ve
that causes the DMOS transistor to shut off at the minimum
controllable current. This voltage is greater than the Enable
Comparator Threshold (VCEN) so that as Ve rises the IC
does not jump from the disabled state to the OM OS transistor conducting a large current.
t BT • Blanking TIme - At the beginning of each cycle there is
a blanking time that the DMOS transistor turns-on and stayson no matter how high drain the current. This blanking time
permits ringing in the external parasitic capacitances and
inductances to dampen and for the charging of the reverse
bias on the rectifier diode.
tONM1N. Minimum DMOS Transistor "On" TIme - The minimum on-time for the DMOS transistor where small changes
in the VC voltage make predictable changes in the DMOS
transistor peak current. Converters should be designed to
avoid requiring pulse widths less than the minimum on time.
tOFFMIN' Minimum DMOS Transistor "Off" TIme - The minimum off-time for the DMOS transistor that allows enough time
for the IC to get ready for the next cycle. Converters should be
designed to avoid requiring pulse widths so large that the minimum off time is violated. (However. zero off time is allowed. that
is. the DMOS transistor can stay on from one cycle to the next.)
'."nCI, t..1Jnlmum Controllable CUiient .. "·"hen the voitage
on Vc is below VIl REF • the peak current for the DMOS transistor is too small for the Current Comparator to operate reliably. Converters should be designed to avoid operating the
DMOS transistor at this low current.
7-56
HIP5061
MaxCI. Maximum Controllable Current - The peak current
for the DMOS transistor when the Voltage-ta-Current Converter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the. Current Ramp becoming active.
Current Compensation Ramp
AUAt. Compensation Ramp Rate - At a given voltage on Vc
the DMOS transistor will turn off at some current that stays
constant for about the first 1.51!s of the cycle. After 1.51!S. the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
tRo. Compensation Ramp Delay - The time into each cycle
that the compensation ramp turns on. The Current Compensation Ramp. used for Slope Compensation. is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
Start-Up
VOOMIN. Rising Voo Threshold Voltage - The minimum
voltage on Voo needed to enable the IC.
V CEN ' Enable Comparator Threshold Voltage - The minimum voltage on Vc needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the Vc pin to GND.
Avc. Power - Up Resistance - When Voo is below VOOMIN.
the NMOS transistor connected to the Vc pin is turned on to
make sure the Vc node is low. Thus the voltage on Vc can
gradually build up as will the trip current on the DMOS transistor. This is the only form of ·soft starr' included on the IC.
The resistance is measured between the Vc and GND pins.
Thermal Monitor
T J • Rising Temperature Threshold - The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions. especially during start-up when the DMOS transistor may stay on for a long time if an external soft-start circuit is not added.
TJHy • Temperature Hysteresis - The IC must cool down
this much after it is disabled by being too hot before it can
resume normal operation.
VOOHYS. Power - On Hysteresis Voltage - The difference
between the voltage on Voo that enables the IC and the voltage that disables the IC.
INTERNAL LEAD - INDUCTANCE
AND RESISTANCE ___
s.w
v.EF
HIP5061
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061
7-57
HIP5061
Pin Description
TERMINAL
NUMBER
DESIGNATION
1
GND
2
Vc
The output of the transconductance amplifier appears at this terminal. Input to the intemal
voltage to current convertar also appears at this node. Transconductance amplifier gain
and loop response are set at this terminal. When the VDO terminal voltage is below the
starting voltage, VOOMlN ' this terminal is held low. Whan the voltage at this terminal
exceeds VCM~' 7V typical, implying an over-<:urrent condition, a typical 10mA current,
IVCOVER pulls this terminal towards ground. This current remains "ON' until the voltage on
the Vc terminal falls by VCHYS, typically 1. W, below the upper threshold, VCM~. When the
voltage on this terminal falls below VCEN, typically 1.SV, the IC is disabled.
3
FB
Feedback from the regulator output is applied to this terminal. This terminal is the input to
the transconductance amplifier. The amplifier compares the internal S.W reference and
the feedback signal from the regulator output.
4
SOURCE
The terminal, labeled TAB, has a connection to this terminal, but because of the long lead
length and resuRlng high Inductance of this terminal, It shouid not be used as a means of
bypassing. Therefore, this terminal is labeled "Do Not Use."
S
DRAIN
Connection to the Drain of the Internal power DMOS transistor is made at this terminal.
6
VG
Gate drive supply voltage is provided at this terminal. A 10n to 150n resistor connected
between this terminal and the VDO terminal provides decoupling and the supply voltage
for the gate drivers.
7
Voo
External supply input to the IC. A nomlnal14V shunt regulator is connected between this
terminal and the TAB. A series resistor should be connected to this terminal from the
external voltage source to supply a minimum current of 33mA and a maximum current of
l05mA under the worst cast supply voltage. The series resistor is not required if the
supply voltage is 12V, ±10%.
TAB
SOURCE
This is the internal power DMOS transistor Source terminal. It should be used as the
ground return for the Voo bypass capacitor. In addition high frequency bypassing for both
the regulator output load voltage and supply Input voltage should be returned to this
terminal.
DESCRIPTION
This is the analog ground terminal of the IC.
For more Information refer to Application Notes AN9208, AN9212, AN9323.
Foot Print For Soldering
~~ 0.120 I--
IT
L
0.424
'
,,,
\
,,
0.523
r
UMIT OF SOLDER MASK
OPTIONAL iii 0.151
,
-
-[
1
1
1
1
1
1
-I
+
1_
\
--,
I
FOR HEADER
-EJ-Et-t50TYP
of
oo~
t
~ D-~
1
1
1
___I
lIE
-
0.575
.1
0.675
T0-220 STAGGERED GULL WING SIP
7-58
~
-I
L
0.080TYP
HIP5061
Typical Performance Curves
26
20
24
1.
I
I
I
16 I-- -
_22 OPERATING CURRENT, Voo. VG • 13.2V, Ve. 8.5V, VFB. 4V
'"
I
I
I
I I
I
I
VFB • Vc" OV, TA" +2Soe
S20
.., ,.,..
I-
ill 18
rr:
rr: 16
i3
...!!;~ 1412 -QUIESCENT CURRENT, Voo. Va • 13.2V, Ve. OV, VFB. 4VLYCURRENT vs SUPPLY VOLTAGE
1.2
1.1
Voo ,,12V, VFB" IV
C 1.0
TA"ooe
S
I-
zw 0.9
./
rr: 0.8
rr:
Co>
rr: 0.7
w
0.4
I--
8
0.3
8
0.2
4
\1
~
./
o
10
20
30
40
SO
60
70
80
00
100
....
o
2
3
AMBIENT TEMPERATURE re)
FIGURE 5. TYPICAL GATE DRIVER OPERATING
CURRENT va TEMPERATURE
4
5
6
7
8
VOLTAGE ATVe PIN (V)
0
10
11
5.20
14.8
5.18
I
~
w 5.16
14.6
~
loo,,100mA
~'4.4
w
~ 14.2
~
VOO" VG • 12V,Ive • 01lA, Ve" VFB_
5.14
~ 5.12
!:i
014.0
w
!E 13.8
w
13.6
II!
!il 5.10
>
~ 5.08
d
5.04
13.2
5.02
20
30
40
SO
60
70
80
00 100
AMBIENT TEMPERATURE rC)
FIGURE 7. TYPICAL CLAMP VOLTAGE VB TEMPERATURE
7-59
k
~
-
...-
5.06
13.4
10
12
FIGURE 6. TYPICAL SUPPLY CURRENT va VOLTAGE
AT PIN VePOR O"C AND +105°C
15.0
13.0 0
~"'050C
J'"
0.5
~CI
-
W
,
~~
0.6
~
C
/
Voo = Va" 12V, VFB" 5.1V, Ve" 5V
::>
5.00 0
30
40
so 60 70 80
AMBIENT TEMPERATURE rC)
FIGURE 8. TYPICAL REFERENCE VOLTAGE va
TEMPERATURE
10
20
90 100
HIP5061
Typical Performance Curves (Continued)
-so
5.20
5.18
I
~ 5.14
~ 5.12
I
I
w 5.10
..1-65
ffi
U-ao
!;
ffi 5.08
~ 5.06
~-85
a: 5.04
-ao
w
5.02
-85
5.00
10.8
-100
11.2
11.6
12.0
12.4
12.8
VOO(Y)
13.2
13.S
14.0
FIGURE 9. TYPICAL REFERENCE VOLTAGE vs SUPPLY
VOLTAGE FOR O"C AND +l05°C
0.5
a:
a:
::>
0.2 - I -
U
ffi~32
-0.3
e: 25
-0.4
24
23
-1
20
30
40
50
60
70
AMBIENT TEMPERATURE rC)
./
80
80
100
Voo" Va • 12V, IVc .. 500JlA
,...
./
-
i~27
w:i 26
K
E!: -0.2
0
1
2
3
220
4 5 S 7 8 8 10 11 12 13 14
VOLTAGE ON FB PIN (V)
FIGURE 11. TYPICAL INPUT CURRENT TO FB PIN VB VFB
10
20
30
40
50
SO
70
AMBIENT TEMPERATURE rC)
80
90 100
FIGURE 12. TYPICAL ERROR AMPLIFIER
TRANSCONDUCTANCE vs TEMPERATURE
2.5
2.5
2.0
2.0
VDD= Va
=12V, Vc-4V, TA-+250C",
_ 1.5
..ffi
~
-
C
.§. 1.0
V
~ 0.5
V
w
~ 0.0
a:
g;
/
8z -0.5
" -1.0
!;
!;
o
-1.5
""'"
._
Voo. Va • 12V, Vc = 5V
0.0
-0.5
-1.5
;;;;- -
-2.0
-2.5
-i75-i5o.i25..ioo-7ii -00 ..25 v 25 00 i5 lOG 125150 17G
VOLTAGE ON FB PIN (mY) CENTERED AROUND 5.W
FIGURE 13. TYPICAL Vc PIN CURRENT IVc PIN vs
VOLTAGE ON FB PIN (SHOWS ERROR
AMPLIFIER TRANSCONDUCTANCE)
I
0.5
... -1.0
V
>
SINKING CURRENT, VFB .. 5.6V
I
U
ii:
-2.0
r--
!33 r--
28
:15
a:z 28
.. -0.1
:q
.§. 1.0
10
~g30
0
1.5
~
It: z 31
0.1
-0.5
o
36
35
34
0.3
Voo - Va _12V, Vc _ 4V, TA _ +250C
r-
V
FIGURE 10. TYPICAL INPUT CURRENT TO FB PIN vs
TEMPERATURE
I
0.4
ffi
-
~ -75
::0
a:
"7
/
-70
I
TA- DoC
U
voo. va _12V, Vc. SV, VFB - VREF _
-so
TA=+1050C
!C
l
I
-55
Iyc - 01nA, Vc - VFB
~5.1S
-2.5 :
SOURCING CURRENT, VFB .. 4.SV
I
I
I
10
2C
SO
40
50
50
10
AMBIENT TEMPERATURE (OC)
80
90 ~oo
FIGURE 14. TYPICAL ERROR AMPLIFIER SINKING AND
SOURCING CURRENT VB TEMPERATURE
7-60
HIP5061
Typical Performance Curves (Continued)
12
2.5 , . . . . . . . - - - - - - - - - - - - . . - . . . . - . . . , . . . . . . ,
c
.5,
l-4V:eor·~V~a~.~1~2:Y,1V~C~·U..~Y,~T:A~·i+;25;O~e=+~=t::t:~
2.0
1.5
I
I
I
I
I
I
Veo • OV (UNDER VOLTAGE eONDmON)
10
I-"'"
TAsooer
1-+-+-+-4--!I-......+-+-4--!I-+-++~
!z 0.5 1--I-+-4-I--I-....-4-I-+-+......f-I-+-I
~ 0.0 1--I-+-4-I--I-..........f-I-+-+......f-I-+-I
B
z -0.5 1--I-+-4-I--I-.........f-I-+-+......f-I-+-I
~ -1.0 1-+-+--1-1-+-+--11-+-+-+--11-+-+-1
>
-1.5 I--+-+-+--I-f-+-+-+--I-f-t-+-+--I
1.0
V
2
I=j::::j~r=tr=t~~~-+-+-+-+-+--I
-2.0
o
-2.5 .......-'--'-......--'-'---'--'-......--'-'---'--'--'---'
-1 0 1 2 3 .. 5 6 7 8 0 10 11 12 13
VOLTAGE ON FB PIN M
-
€ 7.5
w 7.0
li 6.5
If. -
Veo = 12V, TA" +2SOe
FB.6V
....i
!:i
-
ill
6.0
~ 5.5
III 5.0
4.5
r' -
FB .. 4V
-4
o
2
~
o
23456
VOLTAGE ON Vc PIN (V)
7
8
~VCMAX
I""
Veo" VG .. 12V
3.0
2.5
c( 2.0
91.5
1•0
~ 0.5
I
3
IY
1;:
§l
VCHYS
en
51
FB .. 4V
-2
~
./
ffi4.0
Iii 3.5
FB=6V
I
"" /
J r--
FIGURE 16. TYPICAL VcPIN CURRENTvs VOLTAGE ON
Vc PIN FOR OOC AND+105°C
FIGURE 15. TYPICAL Vc PIN CURRENT vs
VOLTAGE ON FB PIN
o V
~
/
TA s +105oe
..
5
6
7
8
VOLTAGE ON Vc PIN (V)
10
0
11
12
FIGURE 17. TYPICALVc PIN CURRENTvs VOLTAGE ON Vc PIN
FOR VOLTAGES ABOVE AND BELOW VREF
i!:
Cis!:!:!
a:..J
0.0 0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE ("e)
80
90 100
08:
~:;)
...len
:;)a:
FIGURE 18. TYPICAL SHORT CIRCUIT COMPARATOR
THRESHOLD VOLTAGE vs TEMPERATURE
~w
w==
a:O
Q,
11.0
C
10.5
.....
I
............
.5,10.0
~
~
3.0
I_ t--
~ 2.5
~ 2.0
:z:
01.5
Veo. va .12Y, VF8" 5.W
~ 1.0
......
............
w 8.5
w
I
Veo" Va .. 10.8V, Vc .. VCMAJ(
............
0
!:i
I
~
zto 9.5
w
ex:
ex: 9.0
;:)
li
I
......
8.0
8
,,--
0•5
~ 0.0
......... ~
/'
to-O·5
""
z
~-1.0
7.5
ffi-1.5
7.0
... -2.0
6.5
-2.5
6.0
-3.0
o
10
20
30
40
50
60
70
AMBIENT TEMPERATURE ("e)
80
00 100
o
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE ("e)
FIGURE 19. TYPICAL OVER-VOLTAGE CURRENT vs
TEMPERATURE
FIGURE 20. TYPICAL CLOCK FREQUENCY PERCENT
CHANGEvsTEMPERATURE
7-61
90
100
HIP5061
Typical Performance Curves (Co"tlriued)
3.0
2.5
2.0
~
~
voo-Vcs12Y, VFB·5.1V
I
1.5
5
~
l..o!'"
...-
..".,...
e_ O•2S
.---
zS
'rA a OOC
1I:j$
elll
!l!i/i 0.15
~::;
IJI'"
I!:~ 0.10
~
---
.---
Voo. Vc .1 0.8V, lORAIN • 5A
~w
I!i!i! 0.20
/'"
-0.5
~ -1.5
I
[
~
0.5
0.0
!Z -1.0
0.30
I
TA·+100oC~
~ 1 •.0
iii
+
-
~
.--~
i~ 0.05
III... -2.0
C
-2.5
-3.0
10.8
11.2
11.8
12.0
12.4
VooM
12.8
13.2
13.8
14.0
FIGURE21. TYPICALCLOCKFREQUENCYPERCENTCHANGE
va SUPPLY VOLTAGE Voo AT COC AND + 100°C
0.30
I
0.28
ezOO.28
I
I
I
:~ 0.24
Cz
@i~ 0.22
I
-
TAs+1000C
!iii/i 0.20
i ::::
I
0.100
:::I
~
I
0.30
/
0.20
:i 2.2
-
2.0
81.8
~
2.86
~
2.84
w 2.12
!i!!!!_
~ 1.6
~
f!;
II:
2.80
w 2.78
1.4
1.2
2.7&
1.0
2.74
80
100
FIGURE 25. TYPICAL TRANSCONDUCTANCE FROM Vc PIN TO
DMOS TRANSISTOR DRAIN (PEAK CURRENT)
va TEMPERATURE
20
I
2.88 -
~ 2.6
30
40
SO
80
70
80
AMBIENT TEMPERATURE rCI
10
2."
I
w 2.4 ...........
U
~
20
-...-
./
30
40
so 80 70
AMBIENT TEMPERATURE (OC)
80
90
100
FIGURE 24. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
LEAKAGE CURRENT vs TEMPERATURE
2.8 -Voo- Vc- 12V
10
V
0.15
~ 0.00 0
FIGURE 23. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE va DRAIN CURRENT loRAIN AT
OOC AND +100°C
I
100
J
: 0.10
.. 0.05
I
2
3
4
5
6
DMOS TRANSISTOR DRAIN CURRENT (A)
I
"
I
I - - Voos80V
~ 0.35
~
0.12
o
30
40
SO
80
70
80
AMBIENT TEMPERATURE rC)
FIGURE 22. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE VS TEMPERATURE
i
TA·OoC
l!i III 0.14
~
20
~ 0.25
~::; 0.18
f!;~
f;!5 0•16
3.0
10
lO.50
Voo" Vo s10.8V, VFB s 5.1V
I
0.00 0
I
I
I
I
Voo. Vc .12V,IDRAIN. 0.25A
-
"...,
-- -o
10
20
I,...- ~
I-""""
..-
3D
40
SO
60
70
$0
AMBIENT TEMPERATURE rC)
i,.....--'
90 100
FIGURE 26. TYPICAL VOLTAGE TO CURRENT CONVERTER
REFERENCE VOLTAGE va TEMPERATURE
7-62
HIP5061
Typical Performance Curves (Continued)
,,180
!
I
.s
150
w
w 175 _ Voo" VG" 12V
~145
Z 170
P
Ii.
~
rill
z
....
65
160
--
~ 155
....
-
8150
!lz 145
:::>
~
-
~
0
10
20
30
40
50
..,..
./
II:
.....".
.... ~
UI
iii
"
:i
130
I!'
!l::Ii
i
70
I
Sl35
8 125
60
I
VOO"VG,,12V
? 140
::Ii
Z 140
:i
I
_
80
120
Z 115
80 100
:i
FIGURE 27. TYPICAL MINIMUM DMOS TRANSISTOR "ON"
TIME va TEMPERATURE
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE rC)
9.0
-0.50
!z
8.5
1-0·55 -
(J
I
I
..,.. ....
II:
~
~ -0.70
~
6.5
::Ii 4.0
/
~ -0.80
C
!:! -0.85
w
./
~ -0.80
VOO" VG • 12V, DUTY CYCLE" 96%_
~ 4.5
I
o
10
20
I
I
I
30
40
50
60
70
AMBIENT TEMPERATURE <"C)
I
I
80 100
FIGURE 29. TYPICAL MAXIMUM CONTROLLABLE PEAK
DMOS DRAIN CURRENT va TEMPERATURE
-1.00
,
.",
t/)
./
8 -0.95
80
~
".. i-""""
-0.75
CI
~ 6.0
I~:
100
Voo"VG=12V
:cw -0.65
...w 7.0
~
In
I
~ -0.60
-
7.5
90
FIGURE 28. TYPICAL MINIMUM DMOS TRANSISTOR "OFF"
TIME va TEMPERATURE
~
~ 8.0
:::>
V
",-
V
'"
/'
AMBIENT TEMPERATURE rC)
w
V
o
10
CiJ!:!:!
a:..J
20
40
SO
60
70
AMBIENT TEMPERATURE <"C)
30
80
80 100
O~
5~
:::;)a:
FIGURE 30. TYPICAL COMPENSATING RAMP RATE
va TEMPERATURE
CJW
W~
a:O
a..
1.80
~
1.75
~ 1.70
~
1.65
:5w
1.60
~ 1.55
~ 1.50
~ 1.45
~ 1.40
I
f-
I
11
Voo" VG" 12V
I
~10
-
~;
-
~
8>
1.35
~ 1.30
~
VFB=4V
5
3
!~
1.25
1.20
6
C 4
:iz
C
!:!
(J
VOOMIN
o
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE rC)
FIGURE 31. TYPICAL COMPENSATION RAMP DELAY
TIME va TEMPERATURE
80
o
100
VOOHYS
o
10
20
30
40
50
80
70
AMBIENT TEMPERATURE (OC)
80
90
100
FIGURE 32. TYPICAL RISING Voo COMPARATOR THRESHOLD
VOLTAGE va TEMPERATURE
7-63
HIP5061
Typical Application Circuit
Figure 33 shows a Simplified Block Diagram of the HIPS061 in a
typical Boost corwerter. A resistor connected from the VIN supply
to the VDD terminal of the IC powers the intemal 14V shunt
regulator. The Gate Driver supply is decoupled from the main
supply by a small external resistor connected between VDD and
the VG terminal. A bypass capacftor is connected between the
VDD terminal and ground to reduce coupling between analog and
digftal circuitry. A Schottky diode insures efficient energy transfer
from the DMOS drain circuit inductor to the load. To set the
output voltage. two resistors are used to scale the output supply
vo~age down to the S.1 V internal reference.
The heart of the IC is the high current DMOS power
transistor with its associated gate driver and high-speed
peak current control loop. A portion of the converters DC
output is applied to a transconductance error amplifier that
compares the fed back signal with the internal S.1V
reference. The output of this amplifier is brought out at
the Vc terminal to provide for soft start and frequency
compensation of the control loop. This same signal is also
applied internally to program the peak DMOS transistor
drain current. To assure precise current control. the
response time of this peak current control loop is less
than SOns.
A 2M Hz internal clock provides aU the timing signals for the
converter operating at 2S0kHz. A slope compensation circuit
is also incorporated wfthin the converter IC to eliminate subharmonic oscillation that occurs in continuous-current mode
converters operating with duty cycles greater than SO%.
HIP5061 Description of Operation
Figure 2 shows a more detailed Functional Block Diagram of
the HIP5061. An internal14V shunt regulator in conjunction
with an external series resistor provides internal operating
voltage to the IC in applications where no 12V auxiliary supply is available. Note that In applications where the input
voltage at V DD is 12V. +/-10%. the regulator is not used. This
regulator is shown as a zener diode on the diagrams of Figure 2 and Figure 33.
The 2MHz clock is processed in the Control Logic block to
provide various timing signals. A cycle of operation begins
when a 100ns pulse (which occurs at a 41ls interval) triggers
the latch that initiates the DMOS transistor on-time. This
pulse also provides a blanking interval in the Current Monitoring block to eliminate false turn-ofts caused by high transient pulse currents that occur during turn-on. The output of
VIN o-4_-.-_-J'Irrn_ _ _....._ _
-I~
_ _.....-.._ _...
VOUT
CND
FIGURE 33. StMPLlFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION
7-64
HIP5061
the Current Ramp block is summed with the sensed DMOS
transistor current (to provide slope compensation) before
being compared with the Error Current signal. The current
ramp, -0.45A1l1s, is inhibited for the first 1.511S (37.5%) of the
duty cycle by the Ramp Enable signal, since ramp is not
needed for slope compensation during this interval. Inhibiting of the compensating ramp has the effect of reducing the
peak short-circuit current.
The output of the power supply is divided down and
monitored at the FB terminal. A transconductance error
amplifier compares the DC level of the fed back voltage with
an internal bandgap reference, while providing voltage loop
compensation by means of external resistors and
capacitors. The Error Amplifier output (the error voltage) is
then converted into a current (the Error Current) that is used
to program the required peak DMOS transistor current that
produces the desired output voltage. When the sum of the
sensed DMOS transistor current and the compensating
ramp exceed the Error Current signal, the latch is reset and
the DMOS transistor is turned off. Current comparison
around this loop takes place in less than 50ns, allowing for
excellent 250kHz converter operation. The latch can also be
reset by an under-voltage (V DD < 10.3V typical), over
temperature (TJ > +125°C typical) or a shutdown signal
externally applied at the Vc terminal. See Figure 36.
Note that if the error voltage (at the Vc pin) is less that
2.55V, then the output of the VOltage-te-Current Converter
will be held at zero. This condition will produce the minimum
possible pulse width, typically 150ns (100ns blanking pulse
plus 50ns delay). Error voltages lower than this 2.55V level
will not produce shorter pulse widths. Under very light loads
(when Vc goes below 1.5V), the Enable Comparator will
temporarily hold-off the PWM latch (and the DMOS transistor) until the Vc voltages rises above 1.5V. This low Vc
inhibit circuit results in a burst-mode of operation that maintains regulation under light or no loads.
During an over-current condition, the output of the Error
Amplifier will attempt to exceed the 7.0V threshold. At this
pOint, the Short-Circuit Comparator will pull down on this signal and induce a low-level oscillation about the threshold,
serving to clamp the peak error voltage. This clamping
action, in turn, will limit the peak current in the DMOS transistor, redUCing the duty ratio of the switch as the demand for
current continues to increase. This action, in conjunction
with the Thermal Monitor, serves to protect the IC from overcurrent (short-circuit) conditions.
impedance, ideally infinity. The amplifier gain is typically
50dB and is not significantly altered when operating into the
stages that follow within the IC. To minimize the output stage
idling current, while providing high peak currents to insure
rapid response to load and input transients, a class B type of
output stage was used in the amplifier. Placing a 100k
resistor from the amplifier output terminal, V c, to ground will
bias the output stage to an active state and still minimize
power consumption. in all cases, the resistor shunting the
transconductance amplifier output must be greater than
10kO to insure that the output will rise suffiCiently high to
obtain the maximum DMOS transistor drain current.
Start-Up Sequence
Upon initial power up of the HIP5061 in a typical application
circuit, the voltage at Vc will be zero, and the DMOS transistor will be off. When the voltage at VDD rises above the
10.3V typical threshold, the error amplifier output is enabled
and the Vc voltage begins to rise in response to the low voltage at the FB terminal. When the Vc voltage rises above
1.5V the DMOS transistor begins to switch at the minimum
duty cycle, and when it rises above 2.55V the duty cycle
begins to increase. The Vc voltage (and peak DMOS transistor current) will then continue to rise until the voltage loop
gains control and establishes regulation. Note that the rate
of rise in the Vc voltage can be controlled by an external soft
start circuit (See Soft Start Implementation).
if the Vc voltage is unrestricted in its rate of rise. then it will
typically rise quickly to its maximum (peak current) value,
causing the DMOS transistor to turn-on and stay on until it
reaches the peak current value. At this point, the DMOS
transistor begins switching, and the Vc voltage (and peak
DMOS transistor current) will drop down to the level commanded by the voltage loop.
Using the Shunt Regulator
The internal 14V shunt regulator in conjunction with an
external series resistor allows the IC to operate from quite
high input voltages, limited only by power dissipation in the
external resistor. When only higher voltages are available, a
bootstrap or other 12V auxiliary supply can be used to eliminate this dissipation. The series resistor should be chosen to
be as large as possible to reduce power dissipation at high
line, while ensuring adequate V DD voltage at low line. The
maximum value for this resistor, R, is given by:
R
Using the Transconductance Error Amplifier
A transconductance amplifier with a typical gm of 30mS is
used as the input gain stage where the power supply output
voltage is compared with the internally generated 5.1V
reference voltage. A PNP transistor input structure allows
this amplifier to accommodate large negative going transient
voltages without causing amplifier phase reversal, often
associated with PNP input structures. Negative transients up
to 5V applied to the input though at least 5.1 k will not result
in phase reversal. The amplifier output stage has the
customary drain to drain output to help improve the output
_ V I. MIN -10.5
MAX (0) 0.033
Where VI is the input voltage to the power supply. The value
chosen for this resistor must also result in a current, I. into
the V DD clamp that is less than 105mA when the input voltage is at its maximum:
7-65
(VI. MAX -13.3)
RMAX
HIP5061
TABLE 2. MINIMUM INDUCTANCE FOR STABLE CCM
OPERATION ABOVE 50% DUTY CYCLE
Inductor Selection
The selection of the energy storage inductor(s) !..sTOR br a DC to
DC converter has tremendous influence on the behavior of the
converter. It is particularly important in light of the high level of
integration (and necessarily few degrees of freedom) achieved in
the HIP5061. There are several factors influencing the selection
of this inductor. Rrst, the inductance of !..sTOR will determine the
basic mode of operation for the converter: continuous or
discontinuous current. In order to maximize the output power
for the given maximum controllable DMOS transistor current, a
converter may be designed to operate in continuous current
mode (CCM). However, this tends to require a larger inductor,
and br many converter topologies resutts in a feedback loop
tha is difficult to stabilize. For these and other reasons, the
inductor !..sTOR may be chosen so as to operate the converter in
discontinuous current mode (DCM). The relative mer~s of
CCM and DCM operation for various topologies and the
corresponding selection of LSTOR is well documented and will not
be covered here.
A second factor influencing the selection of LSTOR is the
stability requirement for current-mode control. This constraint is
only applicable for converters operating in CCM, since openloop instabilities of this type are not observed in converters
operating in DCM. For marginal stability, the compensating
ramp (internal to the HIP5061) must have a slope that is
greater than one-half the difference between the inductor
current's down slope and up slope. (To ensure stability for duty
ratios D > 0.8, the slope of the compensating ramp should be
equal to the inductor current downslope.) A generally accepted
goal is to set the slope of the compensating ramp to be at least
one-half of the inductor current down slope. Since there is no
external control over the internal compensating ramp, one must
be sure that the inductor is large enough so that the down slope
of the inductor current is not too large. Table 2 summarizes this
requirement for minimum inductance for several common
topologies.
A third constraint on the size of the inductor is one that is
common among current-mode controlled PWM converters,
and applies to both DCM and CCM operation. The stable
generation of the desired DMOS transistor pulse width
depends on the accurate comparison of the error signal and
the peak LSTOR (DMOS) transistor drain current. Thus, as
the peak LSTOR ripple current becomes smaller, immunity
from noise on the error signal is eventually reduced until the
pulse width can no longer be adequately controlled. For the
HIP5061, the inductor current ripple must be at least 200mA
peak to peak to ensure proper control of the DMOS
transistor current. This effectively establishes a maximum
value for the inductor LSTOR, so as to maintain at least
200mA of ripple. Note that under extremely light or no load
conditions, all converters will eventually operate in DCM,
and the 200mA requirement will eventually be violated.
Under these conditions, the HIP5061 will continue to
regulate, although the switching of the DMOS transistor will
be in a burst-mode. controlled bv the Licht Load
Comparator. (See Figure 2.)
-
CONVERTER TYPE
MINIMUM INDUCTANCE
Vo + Vo - VI. MIN
Boost
L=
SEPIC (Note 1)
Vo+Vo
Ll~
-->--Ll + L2 2MR, MIN
Cuk (Note 2)
Vo-Vo
L1L2
-->--Ll + L2 2MR, MIN
Flyback
Lp> Cpfvo+vo)
--Ns 2MR,MIN
Forward
(NS) (Vo+Vo)
L> --Np 2M R,MIN
2MR,MIN
NOTES:
1. Assumes that Ll and
~
are both CCM.
2. L =Inductance in Henrys, Vo =Output Voltage,
Vo =Diode Voltage Drop, VI =Input Voltage.
MR MIN = (~V~t)MIN =O.45A1IlS, Ll = Drain Inductor,
~,;. Secondary Inductor, Np =Primary Turns,
Ns =Secondary Turns
DMOS Transistor Turn-Off Snubber
In order to reduce diSSipation in the DMOS transistor due to
turn-off losses, the turn-off time has been minimized.
However, the rapid reduction of current that occurs in the
drain of the DMOS transistor can result in large transient
voltages being induced across any parasitic inductance in
the drain path. For this reason, it is important that such
parasitic inductance be reduced by good, high frequency
layout practices. Nevertheless, there are many instances
(e.g., transformer isolated topologies) in which voltages in
excess of 60V may be developed at the DMOS transistor
drain. In some cases, a simple R-C snubber may be added
to reduce the overshoot of the drain voltage to a safe level.
It is also possible that the large amount of ringing that can
occur at the DMOS transistor drain at turn-off will induce
noise in the IC. This noise may result in false triggering of
the PWM latch, particularly at high peak DMOS transistor
drain currents. Noise related instability can also be eliminated by the addition of a snubber, which will rapidly damp
out such turn-off ringing. Good layout practices will reduce
the need for such protective measures, and ensure that the
DMOS transistor is not overstressed.
Under-Voltage Lockout
The V DD input voltage is monitored by a comparator that
holds off the DMOS transistor gate drive signal when the
V DD voltage is less that about 10.3V. The typical O.SV hyster-
7-66
HIP5061
esis of this comparator is intended to reduce oscillation
when the voltage at Voo is in the vicinity of 10V. Note, however, that when an external series resistor is used to feed the
shunt regulator, the voltage drop across this resistor (which
sharply decreases when the IC shuts down), effectively
reduces the hysteresis. To reduce the tendency for oscillation in the vicinity of the 10V threshold, the impedance of the
source that feeds the DC to DC converter input should be
minimized. The addition of a capacitor (1I!F-471!F) at the
Voo terminal can also help to provide smooth turn-on or turnoff of the converter if the input supply rises or falls gradually
through the V DO Comparator threshold.
Peak Controllable DMOS Transistor Current
Figure 34 shows the guaranteed minimum, peak controllable
DMOS transistor current versus duty cycle. This peak current value is established by the current limit circuitry, which
effectively clamps the voltage at Ve (the error voltage) to
perform current limiting. Since the sensed DMOS transistor
current is summed with a compensating current ramp that
begins its rise 1.51!s after the initiation of a cycle, current limiting will begin to occur at a peak DMOS transistor current
that varies with the operating duty cycle. The highest current
limit threshold occurs for D<0.375, where no ramp is added
to the sensed DMOS transistor current. At higher operating
duty ratios, the onset of current limit will occur at increasingly
lower currents, due to the effect of adding the compensating
ramp to the sensed current. Note that this curve represents
guaranteed minimum values. The guaranteed maximum values are considerable higher, although they are still limited to
levels that protect the IC.
7
DMOS Transistor Turn-On Noise
Although the large DMOS transistor turn-on current spikes are
"blanked over" by the control circuit, it is important to minimize
these current spikes, Since they often result in voltage spikes
considerably below the device substrate that can activate parasitic devices within the IC. Such activation of parasitic
devices will often result in improper operation of the IC. An
external terminal labeled VG brings out the power supply to
the gate drive circuitry. This allows for the control of the peak
current delivered to the gate of the DMOS transistor, which in
turn establishes the turn-on speed. The VG pin may be externally bypassed for the fastest possible turn-on, or series resistance may be added with no bypassing capacitor to slow
down the turn-on of the DMOS transistor. Depending upon the
actual layout of the supply, it Is generally recommended that a
series resistor be added (100-1500) so that the DMOS transistor turn-on speed is reduced. By properly adjusting the
turn-on speed, undershoot can be avoided while turn-on
switching losses are kept to a minimum.
Soft Start Implementation
It is often desirable to allow the regulator to start up slowly,
Figure 35 shows one means of implementing this action. The
normally high output current from the HIP5061 transconductance amplifier (when VFB 0 and VREF 5.W) is directed to
an external capacitor through a diode. This slows down the
rate of rise of the voltage at the Vc terminal. After the regulator starts, the external capacitor is charged to V DO and is
effectively removed from the frequency compensation network by a reverse biased diode. To ensure rapid recycling of
the capacitor voltage with removal of power, a diode is placed
across the 100k0 resistor. Logic Shutdown Input (Ve Pin).
=
i:
;
=
,r-----r--:;.;:-;.:;-=-j-i-----,
,
:1DDkn
Va
,,
:2mA, TYP Veo
,
H-..:'i-_t-I VC ....- - - -..
,,,
GATE DRIVER
,,
,,,
,
,,,
r------r·-----------·-----·
DRAIN
'7--
SOFT START
NETWORK
0.06
0.375
DUTY CYCLE
HIP5061
SOURCE
1.0
FIGURE 34. PEAK DMOS TRANSISTOR DRAIN CURRENT V8
DUTY CYCLE
FIGURE 35. SOFT START CIRCUIT FOR THE HIP5061
When the DMOS transistor first turns ON there may be substantial current spikes exceeding the normal maximum peak
current established by the current control stages within the
IC. To prevent these spurious spikes from conveying erroneous information to the Current Comparator, a 100ns blanking
signal is applied to the current monitoring circuitry. Thus,
there is no peak current protection during the first 6% of the
duty cycle (see Figure 36).
The DC to DC converter may be shut down by returning the
Vc output terminal to ground. A sinking current greater than
4mA will insure that this output is pulled to ground. It must be
remembered that once switching operation ceases, the drain
of the DMOS transistor is open. When the supply is in the
Boost configuration, the output voltage is not zero but the input
voltage less diode and inductor voltage drops. If the SEPIC
7-67
HIPS061
topology is used, this is not the case. Shutting down the regulator via the Vc terminal will cut off the output. Figure 36 shows
two methods of shutting down the IC. In each case the current
sinking circuit must be able to sink at least 4mA, the maximum
current from the HIP5061 Vc terminal.
FROM CD4049UB
U
OFF
n
OFF
··
·.
~----------
DRAIN
Voo
>--+1--14m~A~Vc
.,,
,
r--------,
GATE DRIVER
-,
Fe
,
!
J!
:__________ J
~
ALTERNATE METHOD
,--_G.,N_D_ _.;;;H;;;.IP.;;.S06;;..;.;..1_SO_U_RC_E+--,
NOTE: FREQUENCY
COMPENSATION NETWORK
NOT SHOWN
'--_-+
All the capacitors shown with values of 111F or less are of the
multilayer ceramic type with the X7R dielectric material. This
material has a fairly flat voltage and temperature coefficient
that assures that the capacitance remains comparatively constant at extreme operating temperatures and voltages. The
multilayer construction allows for comparatively large values
with good volumetric efficiency and low inductance. Capacitors around the power input and output circuits should be
returned to the device TAB via a low inductance ground plane.
This TAB is internally connected to the DMOS transistor
source. The schematic diagram of Figure 38 was drawn with
the diagonal leads to show the critical paths for the various
high frequency elements. These short interconnects assure
the lowest inductance around the output power circuit.
Design of a 28V, 1.8A Boost Converter
Figure 38 shows the schematic diagram and a parts list of a
50W supply designed with the HIP5061. Table 3 tabulates
the performance of the power supply.
TABLE 3. TYPICAL LABORATORY PERFORMANCE OF
SOW, 28VI1.BA REGULATOR
FIGURE 36. TWO METHODS OF SHUTTING DOWN THE HIP5061
Input Voltage ............................. l1V to l6V
Mounting, Layout and Component
Selection
Una Regulation............................ 12mVN
Output Voltage ........•................... 28.0V
Load Regulation ........................... 64mVlA
Output Ripple, FL. ......................... 600mV pop
(20MHzBW)
The TO-220 package with its gullwing leads was designed to
be surface mounted. To aid in the external reduction of lead
length and hence inductance and resistance. the IC leads
were staggered. To keep the inductance and resistance of
the critical drain terminal as low as possible. it is suggested
that the PC trace to the DMOS transistor drain terminal be
made as wide as possible. The adjacent source terminal is
not recommended to be used and therefore allows the metal
to the drain terminal to be widened beyond the normal
widths for these terminals. Figure 37 illustrates these points.
One of the most important aspects to the proper application
of this device is high frequency bypassing. In a Boost converter. for example. there should be a low-inductance interconnect from the DMOS transistor drain. through the output
diode and capaCitors, and returning to the TAB (source) of
the HIP5061. Inductance in this line results in large transient
voltages on the DMOS transistor drain terminal which can
result in voltages above the maximum DMOS transistor
drain voltage rating.
IC SOLDERED TO PC BOARD
Voo PC METAL
~
Output Ripple, after Filter, FL ................. BOmV pop
(20MHzBW)
EffICiency: VI =11 V, IL =O.lBA ..••••..•...... 90%
VI = llV, IL = 1.8A •••••••••••••••• 89%
VI = 16V, IL = O.lBA ............... 73%
VI = 16V, 'L = 1.8A ................ 93%
Inductor Selection
In order to maximize the output power for the given maximum controllable DMOS transistor current. this converter
has been designed to operate in continuous current mode
(CCM). In this mode. the inductor value will generally be
large. resulting in a lower inductor ripple current and a lower
peak DMOS current. To ensure that the converter operates
in CCM over the usable range of input voltage and output
current. the value of L2 must be greater than the "critical
inductance." given by
~DER
DRAIN
PC METAL
FOR LOWER
INDUCTANCE
--~~:~
FORFB
ANDVe
= 39I1H
FIGURE 37. SHOWING WIDER PC BOARD METAL FOR
CRITICAL
7-68
HIP5061
D.C. Gain: 20dB-40dB
Pole at 88Hz-880Hz
LHP Zero at 1MHz
RHP Zero at 11.OkHz-ll OkHz
Double Pole at 80kHz (from filter)
where PO.MIN has been arbitrarily chosen as 5.SW. corresponding to an output current of 0.2A. and V D is the forward
voltage of CR1. Thus, for L2 > 3911H, the converter will be in
CCM for VI 11V to 1SV and IL 0.2A to 1.8A.
=
=
A second factor influencing the selection of L2 is the stability
requirement for current-mode control. Using the above
equation for LMIN for the Boost converter:
28+0.5-11
------------=
1911H
2 x (0.45xl0S A/S)
Thus. L2 must be at least 1911H to ensure good stability of
the current loop. and a choice of L2
40l1H satisfies this
requirement, while maintaining CCM operation over an
extremely wide load range.
=
The chosen core material for L2 is Kool Mu ferrous alloy powder from Magnetics. Inc. This material was chosen because of
its relatively low cost. while its losses due to AC flux are five to
ten times less than conventional powdered iron.
Loop Compensation
The control to output transfer function for this current-mode
boost converter has the following characteristics over the
specified load and line conditions:
To stabilize the voltage loop, it is necessary to establish the
unity gain crossover frequency well below the RHP zero, since
this zero introduces positive gain and negative phase. A crossover of 4kHz is fairly conservative. and is achieved by adding a
ll1F capacitor at the VC pin. which provides near infinite DC
gain, and about -5dB of gain at 4kHz. This results in a phase
margin of about 15° at full load. Note that R4 is required for
proper operation of the transconductance amplifier, since it is
prOviding bias current for the output stage as discussed under
Using the Transconductance Error Amplifier section.
Output FiHer Design
Inductor L3 was chosen with C11 to provide at least 15dB of
ripple attenuation at the switching frequency. The corner frequency (80kHz) of this filter is well above the crossover frequency of the voltage loop (4kHz). and has no effect on
stability. This secondary LC filter was used to reduce output
ripple instead of a lower-cost, high-value. low ESR aluminum electrolytic capacitor to demonstrate the reduction in
volume possible at this switching frequency. A lower cost
solution could achieve the same output ripple by replacing
C9.10,12 and L3 with one or two large capacitors (e.g.,
,;......:.:.:.: ................. ;
INPUT
l1VDC -16VDC
: L3, 4~H
CRl
RA
......... ---,
20n,lW
C5
1
Rll
7.sn, 112W
RS
7 10n,l/4W
6
5
Rl
10K.
1%
~~:'~V~D~D---------V~G------~-D-R-A-IN--~
OUTPUT
28VDC
OA-l.8A
OPTIONAL
FILTER
j
GATE DRIVERS,
CONTROL CIRCUITRY
AND LOGIC
HIP5061
RA
R1
R2
R4
RS
Rll
PARTS LIST
200. lW, Wlrebound - Dale RWR81 S20ROFR or Equivalent
10K,1%
2.2K,1%
100K. 1/4W
100. 1/4W
7.So, 112W, Carbon - Allen Bradley EB7SGS
Cl,
ca. C4 and C11
1j1F, SOY. Ceramic - Murata Erie RPE113X7R1050SOY
4711F, SOY, Alum - United Chemicon SlSD476MOSO
6.BIIF, SOY. Ceramin - Mallory M60u6rBMSO
lnF, 100Y. Ceramin - Kemet C322Cl 02K1 GSCA
Schottky Diode - Motorola MBRD360
L2 40IIH at SA, Pulse Engineering PE - S3571
L3 411H atS.SA, Pulse Engineering PE - S3S70
CS and C12
C9 and C10
C13
CRl
FIGURE 38. HIP5061 SOW, 28Y BOOST REGULATOR SCHEMATIC AND PARTS LtST
7-S9
HIP5061
39011F. SOV, type 6730 from United Chemicon}. This change , Snubber Network
would also greatly improve load transient response, proA snubber network has been added to reduce the ringing at
vided that the loop compensation is appropriately adjusted.
the drain due to parasitic layout inductances. In particular,
Note that in the circuit of Figure 38, capacitor C12 does not
under severe load transient conditions, this snubber is necsignificantly affect output ripple, but is necessary to absorb
essary to protect the drain from voltage breakdown. A secthe energy stored in L2 during severe load transients. In the
ond benefit of reducing the noise and ringing at the drain is
event of a step change in load from 1.8A to OA, C12 will limit
that it reduces the tendency of the HIPS061 to exhibit noisethe output voltage overshoot to about 10V and protect the
related instabilities at high peak DMOS transistor currents
drain of the DMOS transistor from overvoltage breakdown.
(4A-6A). A value of l000pF was chosen for C13, since this
is adequate to dampen the ringing associated with the
Input and VDD Rlters
200pF drain capaCitance of the DMOS transistor. Rll was
Since the boost converter is current fed, input filtering is easchosen as 7.S0 to provide the best possible dampening
ily achieved by the addition of a small capacitor C4. This
given the parasitic inductances that exist in the layout. Note
capacitor provides nearly 40dB of ripple current attenuation
that this snubber may not be necessary if the layout of the
for the input, reducing the AC ripple current flowing into the
circuit were improved, or if the application did not push the
converter to less than 200mA.
envelope of DMOS transistor current.
RS and C3 have been chosen to provide good filtering of
Other Power Supply Topologies
high frequency pulse currents. RS provides isolation
between the analog VDD pin and the high pulse current VG Figure 39 shows three other topologies besides the Boost that
pin, and also provides a means to control the turn-on speed may be implemented with the grounded source DMOS power
of the DMOS transistor by limiting the peak current available transistor used in the HIP5061. Other, more complex power
to the internal gate drive circuitry. Thus the output transition supply topologies such as the Quadratic are also possible to
time may be increased to prevent drain voltage undershoot. implement with the HIPS061. One noteworthy feature of the
Undershoot may result in activation of device parasitics and Quadratic topology as shown in Figure 41 is the wide input to
improper circuit operation. For the two-layer board used for output voltage transfer ratio possible with reasonable duty
this design, C3 could be reduced to 0.2211F without affecting cycles. Duty cycles that are not near the Minimum DMOS trancircuit operation. CS was added to provide low-frequency fil- sistor ·ON" TlITle specification shown in the Data Sheet. This
tering at the V DD pin. This reduces the tendency of the circuit permits easier control at the extremes of the transfer ratios.
to oscillate off and on when the voltage at the V DD pin s in Compensating the control loop can pose challenges because
the vicinity of the under voltage lockout threshold, typically of the wider changes in the transfer ratio and hence loop gain.
10V, and the output power is high (30W - SOW).
The SEPIC tOpoiogylll,13) does not have quite as wide inputShunt Regulator Resistor
output voltage range with reasonably controlled duty cycles
as the Quadratic converter mentioned above, but it does
Resistor RA has been chosen to be as large as possible to
allow both voltage increase and decrease with the same cirreduce power dissipation at high line, while ensuring adecuit. This is particularly advantageous when a power supply
quate VDD voltage at low line. Note that the guaranteed
is being used in the stabilizing mode and isolation is not
range of input voltage for proper operation of this circuit is
required. For example, in an application where a regulated
11.2V to lS.3VDC, based upon data sheet limits. However,
24V output is required and the input voltage varies ±20%
the circuit was found to perform well at room temperature for
from a nominal 24V. The SEPIC supply can provide both the
VI 10.7VDC to 17VDC. The maximum value for RA is
Boost and Buck functions.
=
R MAX
=
V I• MIN -10.S
0.033
= 210
RA has been chosen as 200, which results in a current into
the Voo clamp that is less than 10SmA when the input voltage is at its maximum:
I MAX =
(VI MAX- 13.3 )
'20.0
Another outstanding advantage of the SEPIC topology is its
fauR isolation of the input and output voltage. All energy is
transferred via the coupling capacitor. Moreover if the clock
stops, voltage transfer stops. If the switching transistor shorts
there is no output. The Buck circuit will apply full input voltage
to the load with a shorted transistor. This is reason that the
SEPIC topology is referred to as the fail-safe Buck.
100mA< 10SmA
7-70
HIP5061
=
+
+
+
+
VOUT
II
v"
Vo
FB
----r-..I
t-+----I--t
SOURCE
Vo
.....
.....
....,~
GND
~-COU;UNG-·
:
MEANS
:
• ISOLATED'
:,__ORDIRECT
________ J•
SOURCE
FIGURE 39A. SEPIC (FAIL-SAFE BUCK) CONVERTER
.."
;;:;::;:;.
+
Voo
.
v
Vo
DRAIN
GATE DRIVER
AND CONTROL
Vo
CIRCUITRY
HIP5061
GND
FIGURE 40. FLYBACK CONVERTER
~
~
1
J
;;:;::;:;.
>r
FB
It should be noted that when the Cuk topology is implemented, a transistor current source is used to convert the
negative output voltage of the Cuk converter to a current that
is level shifted to the FB terminal on the HIP5061.
VOUT
Two other useful topologies that may be used are the Forward and the Flyback as shown in Figure 40 and Figure 41.
As shown. they may either be operated as an isolated or
non-isolated converter.
SOURCE
...L
FIGURE 39B. CUK CONVERTER
+
+
+
II
Y'N
FB 1-4---1--+
FIGURE 39C. QUADRATIC CONVERTER
FIGURE 41. FORWARD CONVERTER
FIGURE 39. THREE OTHER TOPOLOGIES
7-71
HIP5061
Both the SEPIC and the Boost topologies may be operated
at high voltages with the addition of a high voltage cascode .
Figure 42 shows the Cascode SEPIC converter that is
essentially limited by the selection of the external power
transistor. The burden of voltage, and power Is placed upon
the external transistor. The HIP5061 still performs the drain
current sampling and the control function is the same as the
non cascode configuration.
References
[1] Cassani, John C.; Hurd. Jonathan J. and Thomas, David
R., Wittlinger, H.A.; Hodgins, Robert G.; Sophisticated
Contro/IC Enhances 1MHz Current Controlled Regulator
Performance, High Frequency Power Conversion (HFPC)
conference proceedings, May 1992, pp. 167-173
[2] Smith, Craig D. and Cassani, Distributed Power Systems Via
ASICs Using SMT; Surface Mount Technology, October 1990
=
+
+
160V
VIN
[3] Maksimovic and Cuk, Switching Converters With Wide DC
Conversion Range, High Frequency Power Conversion
(HFPC) conference record, May 1989
VOUT
....i--=====::!
Vc
II
[6] Sokal and Sokal, Class E - A New Class of High EffiCiency
Tuned Single-Ended Switching Power Amplifiers. IEEE
Journal of Solid-State Circuits. June 1975. pp. 168-176
L-_,..........
GND
[7] Mansmann. Jeff; Shafer. Peter and Wildi, Eric, Maximizing
the Impact of Power ICs Via a Time-to-Market CAD Driven
Power ASIC Strategy. Applied Power and Electronics
Conference and Exposition (APEC) proceedings, February 1992. pp. 23-27
SOURCE
[8] Severns and Bloom. Modem DC-to-DC Switchmode
Power Converter Circuits, Van Nostrand Reinhold, 1985
FIGURE 42. OFF LINE CASCODE SEPIC
Figure 43 shows the voltage transfer as a function of duty
cycle for the power supply topologies discussed.
I
~5 1
F
-I
BUCK-BOVT, CUK AND SEPIC
1
.01(1-0)
~
I
~
>
"
I.JJII"
0.1
0.01
II
o
1/
M .. 1/(1 - D) BOOST
::I!
and Design. Marcel Dekker, In., 1984
[10] Pressman, A., Switching and Linear Power Supply.
Power Converter Design, Hayden Book Co., 1977
[12] Oarke, P., A New Switched-Mode Power Conversion
Topology Provides Inherently Stable Response. POWERCON 10 proceedings. March 1983, pp. E2-1 through E2-7
[13] Harris Application Notes AN9208 and AN9212.1
BuJ~
M=D
~
QUAD~~TI~11
' " M.02t1-D2
1/
~
[9] Sum, K, Switch Mode Power Conversion· Basic Theory
[11] Massey, R.P. and Snyder, E.C., High Voltage SingleEnded DC-DC Converter, IEEE Power Electronics Specialists Conference (PESC) record, 1977, pp. 156-159
100
10
[5] Maksimovic and Cuk, General Properties and Synthesis of
PWM DC-to-DC Converters, IEEE Power Electronics
Specialists Conference (PESC) record, June 1989
u
u
~
u
~
u
u
U
DUTY CYCLE (D)
FIGURE 43. VOLTAGE TRANSFER AS A FUNCTION OF DUTY
CYCLE FOR VARIOUS TOPOLOGIES
7-72
HIP5062
Power Control IC
Single Chip Dual Switching Power Supply
April 1994
Features
Description
• Two Current Mode Control Regulators
The HIP5062 is a complete power control IC, incorporating two high
power DMOS transistors, CMOS logic and two low level analog control
circuits on the same Intelligent Power IC. Both the standard "Boost" and
the "SEPIC" (Single· Ended Primary Inductance Converter) power supply
topologies are easily implemented with this single control IC.
• Two 60V, SA On-chip DMOS Transistors
• Thermal Protection
• Over-Voltage Protection
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
• On-Chip Reference Voltage - S.1V
• Output Rise and Fall Times - 3ns
• Designed for 26V to 42V Operation
Applications
Special power transistor current sensing circuitry is incorporated that
minimizes losses due to the monitoring circuitry. Moreover, over-temper·
ature and over-voltage detection circuitry is incorporated within the IC to
monitor the chip temperature and the actual power supply output voltage.
These circuits can disable the drive to the power transistor to protect
both the transistor and, most importantly, the load from over-voltage.
As a result of the power DMOS transistor's current and voltage capability
(5A and 60V), multiple output power supplies with total output power
capability up to 100W are possible.
Ordering Information
• Single Chip Power Supplies
TEMPERATURE RANGE
PACKAGE
• Distributed Power Supplies
HIPS062DY
OOC 10 +8SoC
40 Pad Chip
• Multiple Output Converters
HIPS062DW
OOClo +8SoC
Wafer
• Current Mode PWM Applications
PART NUMBER
Chip
V+(40)
TMON (39)
IRFI2 (38)
IRF02(37)
VINP (36)
AGND(35)
DGND(34)
XCKS (33)
CKIN (32)
IRFll (31)
IRFOI (30)
VCMPI (29)
VTCN (28)
(8) VOOP2
(V) VCMP2
(10) PSOK
(ll)VREG2
(12) FLTN
(13) PSEN
(14)SHRT
(15)SLRN
(16)SFST
(17)VDDO
(18)VOOA
(lV)VREGI
(20)VOOPI
175 mils x 175 mils (4.44mm x 4.44mm)
CAUTION: These devices are sensitive to electroslatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-73
File Number
3208.1
HIP5062
Simplified Block Diagram
v.. _ - - - - - - - - - - . . . ,
S"H
1.O!1F
11!1H
VOOD
12V
15
33
JtI:
"F
681
VINP 1-1(--+
TYPICAL SEPIC CONFIGURATION
7-74
S.1V
Specifications HIP5062
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+ ..•.•..•.••........•••••. -o.3V to 42V
DMOS Drain Voltage •••.•...•.•.•••••.•.•.•••• -o.3V to 60V
DMOS Drain Current • . . . • • . . • . . . • • • • . . • . • • • • • • • . • . • • • lOA
DC Logic Supply •.•...•..•.................•.. -o.3V to 16V
Output Voltage, Logic Outputs ......•••.....•.••• -o.3V to 16V
Input Voltage, Analog and Logic ...•.•••...••••••. -o.3V to 16V
Operating Junction Temperature Range.•..••..... OOC to +1100 C
Storage Temperature Range ......•...••..... -55°C to +150°C
Thermal Resistance
9JC
(Solder Mounted to . • • • • • • • • • . • • . • • . • • . . • • .• 3°CIW Max
0.050" thick Copper Heat Sink)
Maximum Junction Temperature .•.................... +110°C
(Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings'may cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the operaUonaf sections of this specificaUon is not implied.
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = OOC to +1100C; Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
1+
VOOA
Supply Current
V+ = 42V, PSEN = 12V
-
24.7
30
mA
Internal Regulator Output
Voltage
V+ = 30V to 42V, lOUT = OrnA
11.7
V
V+ = 30V to 42V, lOUT = 30rnA
11.5
-
13.3
13.3
V
SLRN = 12V, lOUT = OrnA
11.5
-
13.3
V
VINP
Reference Voltage
VDDA = SLRN = 12V, IvlNP = OrnA
5.01
5.1
5.19
V
RVlNP
VINP Resistance
VINP=O
-
900
-
n
Input Offset Voltage
(REG - VINP)
IVCMP=OrnA
-
-
10
mV
RIN VREG
Input ReSistance to GND
VREG= 5.1V
39
-
85
kn
gm (VREG)
VREG Transconductance
(IvcMP/(VREG - VINP)
VCMP = IV to BV, SFST = llV
15
30
50
mS
gm (SFST)
SFST Transconductance
IvcMp/(VREG - SFST)
VSFST <4.9V
O.B
-
6
mS
IVCMP
Maximum Source Current
VREG = 4.95V, VCMP = BV
-2.5
-
-0.75
rnA
Maximum Sink Current
VREG = 5.25V, VCMP = 0.4V
0.75
OVTH
Over-Voltage Threshold
Voltage at VREG for FLTN to be
latched
6.05
-
Internal Clock Frequency
XCKS = 12V, Vooo = 12V
0.9
ERROR AMPLIFIERS
IVIOI
2.5
rnA
6.5
V
1.0
1.1
MHz
33
-
66
%Vooo
CLOCK
fq
VTHCKIN
External Clock Input Threshold
Voltages
DMOS TRANSISTORS
rOS(on)
loss
Drain-Source On-State
Resistance
I Drain = 2.5A, Vooo = 11 V,
TJ=+25OC
-
-
0.22
n
Drain-Source Leakage Current
Drain to Source Voltage = 60V
-
1
100
IIA
CURRENT CONTROLED PWM
7-75
Specifications HIP5062
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = O"C to +1100C; Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
IVlolVCMP
Buffer Offset Voltage (VCOMP VIFRO)
TEST CONDITIONS
IFRO = OmA to -SmA,
VTCN = 0.2V to 7.6V,
VCMP2 = 0.2V to 7.6V
MtN
TYP
MAX
UNITS
-
-
125
mV
VTHIFRO
Voltage at IRFO that disables
PWM. This is due to low load
current
116
-
250
mV
ITHIFRO
Voltage at IRFO to enable SHRT
output current This is due to
Regulator Over Current Conditions
6.85
-
7.65
V
ISHRT
SHRT Output Current, During
Over-Current
VIRFO =7.7V
-75
-
-33
IIA
VTHSHRT
Threshold voltage on SHRT to
set FLTN latch
Vooo= llV
-
5
-
V
IGAIN
IpEAK (DMOSoRAIN)/IIRFI
41 (DMOSoRAIN)/4t = 1Alms
2.0
-
3.2
AlmA
RIRFI
IRFI Resistance to GND
IIRFI =2mA
150
-
360
(1
Current Comparator Response
Time (Note 1)
41 (DMOS oRAIN)/4t > lA1I1S
-
30
-
ns
~s
MCPW
Minimum Controllable Pulse
Width (Note 1)
25
50
100
ns
MCPI
Minimum Controllable DMOS
Peak Current (Note 1)
125
250
500
mA
Rising V+ Power-On Reset
Voltage
23
-
26.3
V
Falling V+ Power-Off Set
Voltage
-
IS
-
V
V+ Power-On Hysteresis
9.5
-
11.8
V
3.6
-
6.5
V
-
12
-
KO
-1.5
-1.0
-0.65
IIA
START-UP
V+
VTH PSEN
Voltage at PSEN to Enable
Supply
Vooo = ltv
rpSEN
Internal Pull-Up Resistance, to
Vooo
ISFST
Soft-Start Charging Current
VSFST = OV to llV
IpSOK
PSOK High-State Leakage
Current
SFST = ltv, PSOK = 12V
-I
-
I
IIA
VPSOK
PSOK Low-State Voltage
SFST = OV, IpSOK = lmA
-
0.4
V
PSOK Threshold, Rising VSFST
Vooo=IIV
8.1
-
9.9
V
TMON=OV
105
-
135
°C
VTHSFST
THERMAL MONITOR
TEMP
Substrate Temperature for
Thermal Monitor to Trip (Note 1)
NOTE:
1. Determined by design, not a measured parameter.
7-76
HIP5062
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1,4,7
S2
Source pads for the channel 2 regulator.
2,3,5,6
02
Drain pads for the channel 2 regulator.
8
VOOP2
This pad Is the power Input for the channel 2 DMOS gate driver and also Is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a O. ll1F chip capacitor placed close to this pad and the DMOS source pads.
9
VCMP2
Output of the second channel transconductance amplifier. This node is used for both gain and
frequency compensation of the loop.
10
PSOK
11
VREG2
12
FLTN
This Is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are usefUl in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current Is experienced. V+ must be powered down to reset.
13
PSEN
This terminal is provided to activate the converter. When the input is low, the DMOS drivers are
disabled. There Is an Internal 12K pull-up resistor on this terminal.
14
SHRT
501lA is internally applied to this node when there is an over-current condition.
15
SLRN
Control input to intemal regulator that Is used during the 'start-up' of the supply. In normal operation this terminal starts at OV and shuts down the Internal regulator at approximately 9V. This
pad is usually connected to SFST, pad 16.
16
SFST
Controls the rate of rise of both output voltages. Time is determined by an internal lIlA current
source and an external capacitor.
17
Vooo
Voltage input for the chip's digital circuits. This pad also allows decoupling of this supply.
18
VOOA
This Is the analog supply and Internal12V regulator output usually used only during the start-up
sequence. The internal regulator reduced to a nominal9.2V when SLRN is returned to 12V. Output current capability Is 30mA at both voltages.
19
VREGl
Input to channel one transconductance error amplifier. The other, common input for both amplifiers is VINP, pad 36.
20
VOOP1
This pad is the power input for the channell DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a O.lI1F chip capacitor placed close to this pad and the DMOS source pads.
22,23,25,26
01
Drain pads for the channel 1 regulator.
21,24,27
Sl
Source pads for the channell regulator.
28
VTCN
Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP 1,
pad 29.
29
VCMPl
Output of the first channel transconductance amplifier. This node Is used for both gain and frequency compensation of the loop.
30
IRFOl
A resistor placed between this pad and IRFll converts the VCMPl signal to a current for the current sense comparator. The rnaxlmum current is set by the value of the resistor, according to the
equation: IpEAK = 161R. Where R is the value of the extemal resistor in KO and must be greater
than 1.5KO but less than 10KO. For example, if the resistor chosen is 1.8K, the peak current will
be 8.SA. This assumes VCMPI Is 7.3V. Maximum output current should be kept below lOA.
This pad provides delayed positive Indication when both supplies are enabled.
Input to the transconductance error amplifier. The other common input for both amplifiers Is
VINP, Pad 36.
7-77
HIP5062
Pin Descriptions (Continued)
PAD NUMBER
DESIGNATION
31
IRFI1
SeeIRF01.
32
CKIN
Clock input when XCKS Is grounded.
33
XCKS
Grounding this terminal provides for the application of an external clock to CKIN input terminal.
For normal intemal clock operation, this terminal may be left floating or returned to 12V. There
Is an internal 30K pull-up resistor on this terminal.
34
DGND
Ground of the DMOS gate drivers. This pad Is used for bypassing.
35
AGND
Analog ground.
DESCRIPTION
36
VINP
Internal 5.1 V reference. This point Is usually bypassed.
37
IRF02
A resistor placed between this pad and IRFI2 converts the VCMP2 signal to a current for the current sense comparator. The maximum current set by the value of the resistor, according to the
equation: IpEAK =161R. Where R Is the value of the extemal resistor in Kn and must be greater
than 1.5Kn but less than 10Kn. For example, if the resistor chosen is 1.8K, the peak current will
be 8.SA. This assumes VCMP2 is 7.3V. Maximum output current should be kept beiow lOA.
38
IRFI2
SeeIRF02.
39
TMON
this Is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to VODA or 12V the function Is disabled. Returning this pad to ground will put
the IC into the thermal shutdown stete. Thermal shutdown occurs at a nominal junction temperature or +1200C. this terminal is normally retumed to ground.
40
V+
this is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.1 jlF capacitor.
7-78
HIP5062
Functional Block Diagram
- ..····..
r---~~
······~1:
,,,
,
.-----i-I:, VODP1
,
JiB
,,
,,
,
,,,
,,
,,
,
IVRE~n,,
,
,,
~---
----.---------_ ...... _- ... ------ _...... _......
E1
7-79
HIP5063
Power Control IC
Single Chip Power Supply
April 1994
Features
Description
• Single Chip Current Mode ControllC
The HIP5063 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC.
• 60V, lOA On·chlp DMOS Transistor
• Thermal Protection
This IC allows the user maximum flexibility in implementing
high frequency current controlled power supplies and other
power sources.
• 1MHz Operation. External Clock
• Output Rise and Fall Times - 3ns
• Simple Implementation of Hlgh·Speed Current Mode
Controlled Regulators and Power Amplifiers
• Designed for 10V to 45V Operation
Special power transistor current sensing circuitry is incorpo'
rated that minimizes losses due to the monitoring circuitry.
Over·temperature detection circuitry is incorporated within
the IC to monitor the chip temperature.
As a result of the power DMOS transistor's current and volt·
age capability (lOA and 60V) , power supplies with output
power capability up to 100 watts are possible.
Applications
• Single Chip Power Supplies
• Current Mode PWM Applications
Ordering Information
• Distributed Power Supplies
• Multiple Output Converters
PART NUMBER
TEMPERATURE RANGE
PACKAGE
• Wldeband Power Amplifiers for Motor
Control
HIP5063DY
O"C to +85°C
21 Pad Chip
HIP5063DW
O"C to +85°C
Wafer
Chip
1:t-l:afi::::,...tr1j~1
(12) VOOP
Voop (21)
Q
NOTE: Unused pads are for trim and test.
122 mils x 126 mils (3.1 mm x 3.2mm)
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.e. Handling Procedures.
Copyright © Harris Corporation 1994
7·80
File Number
3209.1
HIP5063
Simplified Block Diagram
0.66111'
12V o-~--~--~~--+-----,
5.1V
OUTPUT
0.88111'
S
COOL
AGND OGND
IRR
I R F O t - - - -....
TYPICAL SEPIC APPLICATION CONFIGURATION
Functional Block Diagram
(/)
Cis!!!
a:...1
08:
S~
~a:
CJW
W;::
a:O
Go
.
CONTROL
BLANKING
LOGIC
~------~~-~---~IRR
EXTERNAL CURRENT SCAUNG RESISTOR
IpEAKlDMOS DRAIN CURRENT). 4500 x IREF (mAl
7-81
Specifications HIP5063
Absolute Maximum Ratings
Thermal Information
DMOS Drain Voltage •••••.•••••••••••••..••..• -o.3V to SOV
DMOS Drain Current •••••••••••••••.••••.•••..••••••• 20A
DC Logic Supply •••••••••.•••••••••.••••.•••.• -o.3V to 16V
Output Voltage, Logic Outputs ••••..••.••••••••.• -o.3V to 16V
Input Voltage, Analog and Logic ••...••...•.•••..• -o.3V to 16V
Operating Junction Temperature Range ••......•.• 0oC to +110oC
Storage Temperature Range •..•••.••••.•.••• -55°C to + 150°C
Thermal Resistance
aJC
(Solder Mounted to . • • • • • • • • . • • • • • • • . • . • . . .. 3°CIW Max
0.050" Thick Copper Heat Sink)
Maximum Junction Temperature ..••••••••..•......... +11 O°C
(Controlled By Thermal Shutdown Circuit)
CAUTION: StressBS above those Usted In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only raUng and operation
of the device at thBSe or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications VOOA = vooo = voop = 12V, TJ = OOC to +110oC; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
External Clock Input = 1MHz
-
14
-
mA
DEVICE PARAMETERS
1+
Supply Current
DMOS TRANSISTORS
roS(on)
Drain-Source On-State Resistance
I Drain = SA, TJ = +25°C
-
-
0.13
Q
loss
Drain-Source Leakage Current
Drain to Source Voltage = sov
-
1
100
IlA
Buffer Offset Voltage
(VCMP - VIRFO)
IRFO = OmA to -5mA,
VCMP = 0.2V to 7.6V
-
-
125
mV
ICAIN
IpEAK (DMOSORAlN)/IIRFI
dI (DMOSORAlN)1At = 1Alms
3.B
-
4.9
AlmA
RIRFI
IRFI Resistance to GND
IRFI=2mA
150
-
360
Q
Current Comparator Response
Time (Note 1)
AI (DMOSORAIN)/At> lA1ms
-
30
-
ns
CURRENT CONTROLLED PWM
IVIOI
VCMP
IRs
MCPW
Minimum Controllable Pulse
Width (Note 1)
25
50
100
ns
MCPI
Minimum Controllable DMOS
Peak Current (Note 1)
200
400
BOO
mA
VTHCLCK
CLCK Input Threshold Voltage
4
-
B
V
VTH FLLN
FLLN Input Threshold Vottage
4
-
B
V
VFLLN=OV
-70
-50
-30
IlA
Substrate Temperature for
Thermal Monitor to Trip (Note 1)
TMON pin open
105
-
135
°C
COOL Leakage Current
VCOOL = 12V
-
-
1
IlA
COOL Low-State Voltag~
ICOOL = 2mA, TJ > +125OC
-
-
0.4
V
CLOCK
IFLLN
FLLN Pull-Up Current
THERMAL MONITOR
TEMP
ILEAKCOOL
VCOOL
1. Determined by design, not a measured parameter.
7-82
HIP5063
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1
VCMP
This is the input terminal from an extemal error amplifier. A MOS input voltage follower buffers
this terminal. The buffer output is the IRFO terminal. The extemal error amplifier may be either
an operational amplifier or a transconductance amplifier like the CA30BO. This node may be used
for both gain and frequency compensation of the control loop.
2
VODA
This Is the analog supply Input An external12V supply is required.
3
Vooo
Voltage input for the chip's digital circuits.
4
FLLN
One pad of two clocking terminals. This terminal has an extemal 50jJA pull-up current that allows
the terminal to be floated or be left open. With FLLN high, (open or tied to Vooo), the ON cycle
will start wiith the falling edge of the CLCK input With FLLN low or grounded, the DMOS ON
cycle will start on the rising edge of the CLCK input
5
CLCK
The other clock input pad. An external clock is applied to this terminal. This terminal has no pullup current or resistance. See FLLN above for phasing information.
6
COOL
Over-temperature indication is provided at this pad. When the chip temperature is below the thermal threshold, the open drain DMOS transistor is in the high impedance state. When the thermal
threshold is exceeded, COOL is held low.
7
TMON
This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to VODA or 12V the function is disabled. Returning this pad to ground will enable
the thermal monitor function. Thermal threshold occurs at a nominal Junction temperature of
+125°C.
B
IRFO
A resistor placed between this pad and IRFI converts the VCMP signal to a reference current for
the current sense comparator. The cycle by cycle peak current is set by the value to this resistor
according the the equation: IPEAK = 4500 x VCMP/R. Where IpEAK Is in amperes and R is the
value of the external resistor In ohms. A maximum VCMP of BV and a resistor of lBOOn will keep
the drain current below the absolute maximum specification of 20A.
SeeIRFO.
9
IRFI
10
AGND
11
Analog ground.
DGND
Digital ground.
12 &21
Voop
These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a O.lj!F chip capacitor placed close to this pad and the DMOS
source pads.
13,15, 17, 19
S
Source pads of the DMOS power transistor.
14,16,1B,20
0
Drain pads of the OMOS power transistor.
i
I
7-83
HIP5500
High Voltage Ie
Half Bridge Gate Driver
April 1994
Features
Description
• 500V Maximum Rating
The HIP5500. a high voltage integrated circuit (HVIC) halfbridge gate driver for standard power MOSFETs. IGBTs. and
the new Harris Buffered MOSFET (RFV10N50BE). can be
employed in a wide variety of switching regulator circuits.
• 2A Peak Gate Drive
• Ability to Interface and Drive N-Channel Power
Devices With Complimentary Outputs For Buffered
FETs
• Fault Output, Overcurrent Detection and Undervoltage
Holdoff
• Over 600kHz Sawtooth Oscillator Frequency
• Adjustable Deadtime Control
• Soft-Start capability
• Low Current Standby State
• Sleep Mode Reduces Bias Current When Not Enabled
Applications
• Switching and Distributed Power Supplies
The HIP5500 incorporates a precision oscillator. adjustable
using an external resistor and capacitor. The resistor sets
the capacitor charging current and the capacitor sets the
integration time of a triangle wave. Another resistor connected to the DIS pin adjusts the dead-time and can be tailored to the application. The oscillator switches at twice the
output waveform fundamental frequency. The result is an
output waveform whose positive and negative half-cycles are
near perfect balance (volt-second equalization).
Short-Detect (SO) and Soft-Start (SS) inputs provide alternative means for limiting and regulating respectively the
half-bridge output voltage. A capacitor on the SS input will
begin charging up once the EN input is made high and
causes the duty cycle of each half-cycle to "ramp" the duty
cycle of the output waveform.
• Electronic Lighting Supplies
Ordering Information
PART
NUMBER
The HIP5500 combines the functionality and flexibility of a
PWM IC with the convenience of a high voltage half-bridge
driver optimized for power supply inverters. It can be used
either open-loop or in closed-loop fashion using the SS input
for controlling the output waveform duty-cycle.
TEMPERATURE
RANGE
PACKAGE
HIP5500IP
-40"C to +85°C
20 Lead Plasijc DIP
HIP5500lB
-4O"C to +85°C
20 Lead Plastic
SOIC(W)
The SO input can sense a signal proportional to current. providing a means of shortening the conduction periods below
that imposed by the SS input.
Other circuits within the HIP5500 "match" upper and lower
turn-on and turn-off propagation times in order to minimize
flux imbalances when priving output transformer loads.
Pinout
HIP5500 (POIP, SOIC)
TOP VIEW
CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-84
File Number
3210.2
HIP5500
Typical Application Block Diagram
r -______________________
~~~A~~~~~FO~E:.UE~
I~'"
HO - -......--I,,~
OSC
m
SD
EN
DIS
CT
+ SOOVDC
Vee
15VDC
+
iiO-1
HO
iiO
BUFFERED
FEr.
VB
Vs
LO
m
ro
BUFFERED
FEr.
'.:,3
[0-1
Functional Block Diagram
m
~O
__________
~
SD~----------~~--------------~--~
Lvcc
VB
(/)
UJ!:!:!
a::~
ea-
:s~
~a::
CJW
OSC
w;=
a:: 0
a-
0----------< J----...,
HO
iiO
Vs
LO
m
SS ~-+--_1----_L;>--~\-----------~~
r
GND
EN
7·85
Specifications HIP5500
Absolute Maximum Ratings
Thermal Information
Offset Supply Voltage. Vs •••.•..••••••..•••..•. .ves to +500V
Floating Supply Voltage (VB to Vsl ••..•.•••••.••• -o.3V to +18V
High Side Channel Output Voltage, VHO • VNHO •.• Vs-o.5 to VB+O.5
Fixed Supply Voltage. Vee ••.••••.••••.•.••.••• -o.5V to +18V
Low Side Channel Output Voltage •••.•.•••.• -0.5V to Vee +O.5V
All Other Pin Voltages
(SO, Rr. CT. DIS. SS. EN and FLT) •.•...••. -o.5V to Vee +O.5V
Storage Temperature Range ••..••••...•••••• -40"C to +15O"C
Junction Temperature. . • • • . • • . . • • • • . • • • • • • . . • • • • • • . +125°C
Lead Temperature (Soldering lOs) ••••••••••.••••.•••• +3OQOC
(SOIC - Lead Tips Only)
, Offset Supply Maximum dv/dt, dVsId! ................•. 50Vlns
, ESD Classification •..••••.....•••..•.••••.••••••.. Class 1
Thermal Resistance
OJA
Plastic DIP Package •••••.•••••••.•••••.•.•.••• 75°CIW
Plastic SOIC Package •••••.•••..•.•••...••••... 800 CIW
See Maximum Power Dissipation vs Temperature Curve Figure 21
CAUTION: Stresses abOll8 thosB listed In 'Absolu/B MaJdll'NJlrl Ratings' may cause ".,."..,..nt dama". to the davfce. This is a stress only 186ng and ope1860n
of the device at th6se or any other conditions abow those Indicated In the op8f8t1onal sections of this specification is not impUed.
Recommended Operating Conditions (TJ = -40"C to +125°C Unless Otherwise Noted, All Voltages Referenced to Vss)
Offset Supply Voltage, vs ••.•••.•••...••.••••. -2.0V to +500V
Floating Supply Voltage. Ves (VB to Vsl. • • • . • . . • . . +1OV to +15V
High Side Channel Output Voltage, VHO,VNHO .•.•..••• OV to Ves
Fixed Supply Voltage, Vee •..•.••.•........•... +10Vto+15V
Low Side Channel Output Voltage. VLO'VNLO •.••....•. OV to Vee
All Other Pin Voltages (SO. Rr. CT. DIS, SS, FLT and EN) ... OV to Vee
Discharge Time Constant. .•••..•.••.•••..•.•••••• lOOns Min
Discharge Resistor Range. Ro1s ..•••••••••••••. 100kn to 50kn
Charging Resistor Range. RT .•..•••••.•...•••.6.8kn to 400kO
Oscillator Capacitor Range, CT' .••••••...•.•.•. 100pF to O.lI1F
Oscillator Frequency Range •.••••••••.•••••.•••• 300kHz Max
Oscillator Capacitor Charge Current Range. 'Ar' ..... 21 j1A to 5mA
Electrical Specifications vcc = Ves = +15V. Vs = GND = ov, Unless Otherwise Specified
TJ = _40°C
TO+125°C
TJ = +25°C
PARAMETER
SYMBOL
Quiescent Vee Current
lace
Quiescent Ves Current
loes
Quiescent Leakage Current
ILK
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
-
5.5
7.0
8.0
mA
300
400
435
j1A
0.4
3.0
3.5
-
(Vs - GND) = 5.0V
-
Rr=O
-
I1A
5.0
mA
-
2.0
ISFT/PWM
1/3V ce < VSFT < %Vee
70
110
145
60
160
I1A
Input Threshold
VEN
Low to High Transition
7.5
7.8
8.5
7.4
8.6
V
Input Hysteresis
VEN-HYS
-
2
-
-
-
V
Standby Vee Current
SS Current Source
ISTBY
Undervoltage Threshold
VUVHL
High to Low Transition
7.7
8.6
9.5
7.4
9.6
V
Undervoltage Threshold
VUVLH
Low to High Transition
7.9
8.8
9.7
7.6
9.8
V
Undervoltage HysteresiS
VUVHYS
0.08
0.3
0.7
0.05
0.75
V
Short Detect Threshold
VTHSD
3.5
4.0
4.5
3.4
4.6
V
CT/Rr Current Ratio
ICTRAT
0.9
1
1.1
0.85
1.15
j1A
'Ar = l00j1A.
Veel3 < VeT < %Vee
HO. LO Peak Output Current
IOUT+
Sourcing. LO, HO = GND
1.5
1.95
-
1.0
HO, LO Peak Output Current
lour
Sinking. LO. HO = Vec = Ves
1.5
2.0
1.0
IBUF+
Sourcing,
m, HO = Vss
Sinking, ro, HO = Vec = Ves
170
250
-
110
170
230
-
110
-
rnA
CT =7.5V
7.5
7.8
8.1
7.4
8.2
V
m. HO Peak Output Current
m, HO Peak Output Current
Soft-Start VTHRESH' Low to High
' SUF VrSSHL
7-86
A
-
A
mA
Specifications HIP5500
Electrical Specifications vcc = Vas = +15V, Vs = GND = OV, Unless Otherwise Specified (Continued)
TJ
PARAMETER
SYMBOL
Soft-Start VTHRESH, High to Low
TEST CONDITIONS
=
TJ .40oC
TO+12SoC
=+2SoC
MIN
TYP
MAX
MIN
MAX
UNITS
V~SLH
7.2
7.5
7.8
7.1
7.9
V
OSC Input Upper Threshold
V~TLH
9.8
10.4
11.0
9.7
11.1
V
OSC Input Upper Threshold
V~THL
CTto DIS
5.0
5.6
6.2
4.9
6.3
V
Oscillator Upper to Lower
Threshold Difference
VCTDIF
VTCTLH - VTCTHL
4.5
4.8
5.1
4.4
5.2
V
OSC_OUT RosON, Sinking
OSCRosL
losc_oUT = -SOmA
5
8.5
12
2
17
Q
OSC_OUT RosON, Sourcing
OSCRoH
losc_ouT = SOmA
14
19
30
9
40
Q
DIS Output On Resistance
RosDIS
lOIS = lOrnA
75
115
ISO
·
200
Q
m Output On Resistance
RosFLT
IFLT= SmA
100
165
230
40
320
Q
Dynamic Electrical Specifications vcc = vas = +15V, GND = OV, Unless Otherwise Specified
TJ = ·40OC
TO +12SoC
TJ =+25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
-
-
50
-
ns
25
35
-
ns
25
35
-
Tum-On Rise Time, HO, LO
loR
CL = 2000pF
Tum-Off Fall Time, HO, LO
IoF
CL =2000pF
RO, [Q
IoNR
CauF = 200pF
IoNF
CauF = 200pF
·
·
TpCTLH
CT=V~THL
-
475
700
·
925
ns
-
475
700
-
925
ns
TpCTLH and TpCTHL
-
60
-
-
-
ns
·
·
475
ns
825
ns
-
ns
1100
ns
775
ns
Tum-On Rise Time,
Tum-Off Fall Time, RO, [Q
CT Fall to Lo/HO Rise
Lo/HO LOAD = 200pF
CT Rise to Lo/HO Fall
TpCTHL
CT=V~TLH
LO/HO LOAD = 200pF
LO-HO Prop Delay Mismatch
Delmatch
50
CT Rise to DIS Fall
TpCTDISHL
CT=V~THL
·
300
4SO
CT Fall to DIS Rise
TpCTDISLH
CT=V~TLH
-
600
800
·
200
-
-
425
8SO
SOO
7SO
Minimum Dead Time
Short Detect Propagation Delay
Soft·Start Propagation Delay
Time
tOTMIN
tSOLO/HO
tSSOLY
SO = VTHSO , LO/HO = 200pF
SS = VTSSLH, LO/HO =
200pF
7·87
-
ns
ns
HIP5500
Typical Performance Curves
~
!Zw
100.0
50
20
10.0
5
:(6.4
::I
(J
w
!-&.2
, 1/
,
2
1.0
0.5
a:
a:
All Curves are Vcc" +lSV, TA = +2SoC, Unless Otherwise Specified
,
~
0.2
0.1
C
w
..J 0.05
!Z
B 5.4
~
~
L,;"
::I
o
~
~
!Z
",
0
::::: ""'-I.i
+20 +40 +60 +80
TEMPERATURE ("C)
I
+100 +120
I
I
l- i-
VBS-12V
r- r--
-
_2.8
---
12.6
~
+40 +60 +80
TEMPERATURE ("C)
+100 +120
Vcc· l5V
"-
'J I I
"""'l
~2.0
B1.8 .....
~ 1.&
§l1.4
j$1.2
r--.
1. 0
It~
Vcc· 12V
,...
l'oL.
r""" -..L I
+20 +40 +60 +60
TEMPERATURE ("C)
+100
0.4
+120
,/
,/
/
r-
I .,.......".,
0.8
Vcc· 1OV
-40
-20
o
......
-
.....
+20
+40
+60
TEMPERATURE ("C)
r-.
--
+80
+100
+120
FIGURE 4. QUIESCENT STANDBY CURRENT vs
TEMPERATURE AND Vcc SUPPLY VOLTAGE
I t I I
€ 2.0
, / Vcc· 1OV
Vcc· 12V
/. Vcc· 15V
w 1.8
65
55
+20
I I I
"-
0.6
o
-20
w
~
/
II
1.8
1.7
VCC· 15V -
-
~ 1.6
50
/" Vcc· 1OV
, / /~cc.12V
Vcc· 15V
,/
a:
~ 45
1.5
~
1.4
Vcc· 12V _
I
C 1.1
z
w
1.0
-20
0
+20 +40 +60 +80
TEMPERATURE ("C)
-40
+100 +120
FIGURES. ENABLEIDISABLE THRESHOLD (PERCENT Vccl va
TEMPERATURE AND Vcc SUPPLY VOLTAGE
7-88
I
-
1_ ,..-
Vcc· 1OV
!1.2
c 35
-40
~
~ 1.3
i~
iii
0
ih.2
0
~ 60
~
-20
;:2.4
r-- l- i-.
...>o
g
~
'"ow
'"
3.0
I
FIGURE 3. QUIESCENT FLOATING BIAS SUPPLY CURRENT
va TEMPERATURE AND VBS SUPPLY VOLTAGE
'8
Vcc" 10V
3.4
VBS,,10V
125
-40
I
Vcc" 12V
FIGURE 2. QUIESCENT Vcc CURRENT va TEMPERATURE
AND Vcc SUPPLY VOLTAGE
3.2
n--f... ....
I
........
.... ....
Vcc· 15V
r-
53.4-40
VBS_15V
;;;;;; -
--
!!! 3.6
I I I I
I
....
- -
4.6
4.4
4.2
~ 4.0
o 3.8
FIGURE 1. OFFSET SUPPLY LEAKAGE CURRENT va
TEMPERATURE AT 300VDC
-
5.2
5.0
4.8
t
,
325
"'"
a: 5.6
",
0.02
1/
0.01
0.005
-40
-20
.....
6.0
~5.8
-20
o
+20
+40
+60
+60
TEMPERATURE ("C)
+100
+120
FIGURE 6. ENABLEIDISABLE HYSTERESIS VOLTAGE
TEMPERATURE AND Vcc SUPPLY VOLTAGE
HIP5500
Typical Performance Curves
All Curves are Vcc = +lSV. TA = +2SoC. Unless Otherwise Specified (Continued)
12 0
1.8
iw
~ 11 0
£
!z
~ 100
a:
fo"'"
B
i
Iii
It
o
90
~ ::::
-~ ::::
.....
.....
i-""
I"
~
..... fo"'"
..... i--" fo"'"
..... i.-o" ~ .....
~
i!:i
..... i--" ri ..... ~ :::: ~
k ..... i--" ~
~
!;
~
~
I'-
-- r- --
\
Vcc .. 12V
Vcc.,10V
·20
o
+20
+40
+60
+80
TEMPERATURE ("e)
+100
~
'~
~CS+0.5CP
2.0
4.0
6.0
POWER DISSIPATION (W)
8.0
FIGURE 7. THERMAL CAPACITANCE MODEL OF HIP5600
Figure 7 shows the thermal capacitances of the TO-220
package, the integrated circuit and the heat sink, if used.
7-99
FIGURE 8. TIME TO THERMAL SHUTDOWN vs POWER
DISSIPATION (T0-220 PACKAGE ONLy)
10
HIP5600
= T A + T 1 + T2 + T 3
TJ (t)
Tl
(Ea. llA)
"'P9SA(1-e;~J
Thermal Shutdown Hysteresis
Figure 9 shows the HIPS600 thermal hysteresis curve with
VIN l00VDC, VOUT SV and lOUT 10mA. Hysteresis is
added to the thermal shutdown circuit to prevent oscillations
as the junction temperature approaches the thermal· shutdown limit. The thermal shutdown is reset when the input
voltage is removed, goes negative (i.e. AC operation) or
when the part cools down.
=
Where:
(Ea. 118)
'tl "'9 SA (Cp+C S)
=
=
10
(Ea. llC)
Where:
't2
T3
5
0.79JC
(
"'0.6P9Jc(1-e;~
O,SCp+Cs)O.SC p )
Cp+C S
J
8.0
1
6.0
j
4.0
\
2.0
(EO.l1D)
Where:
't3 '" 0.69 JCCD
0.0
118.0
HEATING
\
SHUTDOWN
REGION
~
\
105.0
COOUNG
......
113.0
120
127
CASE TEMPERATURE ("C)
135
142
Thermal Transient Operation (SOle Package)
Equation (11 A) can also be used for the SOIC package provided the following substitutions are made.
(l-e~
J
(Ea. 11E)
T2 '" P92 (1-e
;~
J
(Ea. llF)
T3 ",P93 (l-e
;~ J
(Ea. llG)
Tl ",P9 l
where
91
91
81
=160oc/W
=1OoC/W
=2.9°C/W
't1
t2
't3
=S.8s
=86ms
=7.Sms
For example, with the SOIC package mounted on a PC
board at +85°C in still air, the HIPS600 could dissipate 4W
for -70ms before going into thermal shutdown.
For start-up applications a more useful parameter is the total
charge delivered before thermal shutdown.
(TTS- T A )
0L -
V
IN
Cp
(Ea. 12)
Cp is about 3SmJf'C for the SOIC package and about
l000mJf'C for TO-220.
For example:
with TTS
VIN
=+12roC, TA =+8SOC
=400V and Cp =35mJf'C
OL := 3670f.lC
which is enough to charge a 24OJ!F capacitor to lSV.
FIGURE 9. THERMAL HYSTERESIS CURVE
AC to DC Operation
Since the HIPS600 has internal high voltage diodes in series
with its input, it can be connected directly to an AC power
line. This is an improvement over typical low current supplies
constructed from a high voltage diode and voltage dropping
resistor to bias a low voltage zener. The HIPS600 provides
better line and load regulation, better efficiency and heat
transfer. The latter because the TO-220 package permits
easy heat sinking.
The efficiency of either supply is approximately the DC
output voltage divided by the RMS input voltage. The
resistor value, in the typical low current supply, is chosen
such that for maximum load at minimum line voltage there is
some current flowing into the zener. This resistor value
results in excess power dissipation for lighter loads or higher
line voltages.
Using the circuit in Figure 3 with a 1000l1F output capacitor
the HIPS600 only takes as much current from the power line
as the load requires. For light loads, the HIPS600 is even
more efficient due to it's interaction with the output capacitor.
Immediately after the AC line goes positive, the HIPS600
tries to replace all the charge drained by the load during the
negative half cycle at a rate limited by the short circuit current limit (see "Al" and "81" Figure 10). Since most of this
charge is replaced before the input voltage reaches its RMS
value, the power dissipation for this charge is lower than it
would be if the charge were transferred at a uniform rate during the cycle. When the prOduct of the input voitage and current is averaged over a cycle, the average power is less than
if the input current were constant. Figure 11 shows the
HIPS600 efficiency as a function of load current for OOVRMS
and 132VRMS inputs for a 1S.6V output.
7-100
HIP5600
-
Do's And Don'ts
I
[\;.V
/
~N
±
I
120VRMS, 60Hz
I
r1 rl.
-~ r B1 tw1
\.. .... "
I
~IB2
J
1
..II
r-k
R
~\
t----i1--1
100mVIDIV
.........
1. Do not exceed the absolute maximum ratings.
'V
20mAIDIV
I
~
DC Operation
\.
-
,
-
/
2. The HIP5600 requires a minimum output current of 1mAo
Minimum output current includes current through RF1.
Warning: If there is less than 1mA load current, the output voltage will rise. If the possibility of no load exists,
RF1 should be sized to sink 1mA under these conditions .
RF1
-
23
'"
-
14
.............
12
-......
VOUT .. 15.6VDC
10
,.
0.0
I.
I'
•
I
I
I
5.0
I
I
I
I
I
I
I
I
I' I
10.0
LOAD CURRENT (mA)
= 1.07V = 1kil
1mA
Recommendation: Adequate protection means (such
as MOV, avalanche diode, surgector, etc.) may be
needed to clamp transients to within the ±650V input limit
of the HIP5600.
~
VIN" 132VRMS
'........ ............
V
REF
1mA
3. Do not "HOT' switch the input voltage without protecting
the input voltage from exceeding ±650V. Note: inductance from supplies and wires along with the 0.021lF
decoupling capacitor can form an under damped tank circuit that could result in voltages which exceed the maximum±650V input voltage rating. Switch arcing can
further aggravate the effects of the source inductance
creating an over voltage condition.
............. ~ VIN" 60VRMS
21
=
2msJDIV
FIGURE 10. AC OPERATION
25
MIN
I
I
,
I
I
I
15.0
FIGURE 11. EFFICIENCY AS A FUNCTION OF LOAD CURRENT
Referring again to Figure 10, Curve "Ai" shows the input
current for a 10mA output load and curve "B1" with a 3mA
output load. The input current spike just before the negative
going zero crossing occurs while the input voltage is less
than the minimum operating voltage but is so short it has no
detrimental effect. The input current also includes the charging current for the 0.02jlF input decoupling capacitor C1.
The maximum load current cannot be greater than 112 of the
short circuit current because the HIP5600 only conducts over
112 of the line cycle. The short circuit current limit (Figure 39)
depends on the case temperature, which is a function of the
power diSSipation. Figure 39 for a case temperature of
+100oC (Le. no heat sink) indicates for AC operation the
maximum available output current is 10mA (1/2 x 20mA).
Operation from full wave rectified input will increase the
maximum output current to 20mA for the same +100oC case
temperature.
As a reminder, since the HIP5600 is off during the negative
half cycle, the output capacitor must be large enough to supply the maximum load current during this time with some
acceptable level of droop. Figure 10 also shows the output
ripple voltage, for both a 10mA and 3mA output loads "A2"
and "82", respectively.
4. Do not operate the part with the input voltage below the
minimum 50VDC recommended. Low voltage operation: For input voltages between OVDC and +5VDC
nothing happens (lOUT = 0), for input voltages between
+5VDC and +35VDC there is not enough voltage for the
pass transistor to operate properly and therefore a high
frequency (2M Hz) oscillation occurs. For input voltages
+35VDC to +50VDC proper operation can occur with
some parts.
5. Warning: the output voltage will approach the input voltage if the adjust pin is disconnected, resulting in permanent damage to the low voltage output capacitor.
AC Operation
1. Do not exceed the absolute maximum ratings.
2. The HIP5600 requires a minimum output current of
0.5mA. Minimum output current includes current through
RF1. Warning: If there is less than 0.5mA output current,
the output voltage will rise. If the possibility of no load
exists, RF1 should be sized to sink 0.5mA under these
conditions.
RF1
MIN
=
V
REF
O.SmA
=
1.07V
0.5mA
= 2kil
3. If using a laboratory AC source (such as VARIACs or
step-up transformers, etc.) be aware that they contain
large inductances that can generate damaging high voltage transients when they are switched on or off.
7-101
Recommendations
(1) Preset VARIAC output voltage before applying power
to part.
(2) Adequate protection means (such as MOV, avalanche diode, surgector, etc.) may be needed to clamp
transients to within the ±650V input limit of the HIP5600.
HIP5600
4. Do not operate the part with the input voltage below the
minimum SOVRMS recommended. Low voltage operation similar to DC operation (reference step 4 under
DC operation).
A 10llF capaCitor (C2) provides stabilization of the output
stage. Heat sinking may be required depending upon the
power dissipation. Normally, choose RF1 «VREFII ADJ •
S. Warning: the output voltage will approach the input voltage if the adjust pin is disconnected, resulting in permanent damage to the low voltage output capacitor.
General Precautions
Instrumentation Effects
Background: Input to output parasitic impedances exist in
most test equipment power supplies. The inter-winding
capacitance of the transformer may result in substantial current flow (mA) from the equipment power lines to the DC
ground of the HIPS600. This "ground loop' current can result
in erroneous measurements of the circuits performance and
in some cases lead to overstress of the HIPS600.
Recommendations for Evaluation of the HIP5600
in the Lab
FIGURE 13. AC/DC CONVERTER
a) The use of battery powered DVMs and scopes will eliminate ground loops.
b) When connecting test equipment, locate grounds as
close to circuit ground as possible.
c) Input current measurements should be made with a noncontact current probe.
If AC powered test equipment is used, then the use of an
isolated plug is recommended. The isolated plug eliminates
any voltage difference between earth ground and AC
ground. However, even though the earth ground is disconnected, ground loop currents can still flow through transformer of the test equipment. Ground loops can be
minimized by connecting the test equipment ground as
close to the circuit ground as possible.
CAUTION:
Dangerous voltages may appear on exposed
metal surfaces of AC powered test equipment.
The HIPS600 can operate from an AC voltage between
SOVRMS to 280VRMS, see Figure 13. The combination of a
1kn (2W) input resistor and a V27SLA10B MOV provides
input surge protection up to 6kV 1.2 x SOilS oscillating and
pulse waveforms as defined in IEEElANSI C62.41.1980.
When operating from 120VAC, a V130LA10B MOV provides
protection without the 1kn resistor.
The output capaCitor is larger for operation from AC than DC
because the HIPS600 only conducts current during the positive half cycle of the AC line. The efficiency is approximately
equal to VOUT NIN (RMS), see Figure 11.
The HIPS600 provides an efficient and economical solution
as a start-up supply for applications operating from either AC
(SOVRMS to 280VRMS) or DC (SOVDC to 400VDC).
The HIPS600 has on chip thermal protection and output current limiting circuitry. These features eliminate the need for
an in-line fuse and a large heat sink.
Application Circuits
t -....-oVOUT
FIGURE 14.. START UP CIRCUIT
FIGURE 12. DC/DC CONVERTER
The HIP5600 can be configured in most common DC linear
regulator applications circuits with an input voltage between
SOVDC to 400VDC (above the output voKage) see Figure 12.
The HIPS600 can provide up to 40mA for short periods of time
to enable start up of a swHch mode power supply's control circuit. The length of time that the HIP5600 will be on, prior to
thermal shutdown, is a function of the power dissipation in the
7-102
HIP56DD
part, the amount of heat sinking (if any) and the ambient temperature. For example; at 400VDC with no heat sink, it will
provide 20mA for about 8s, see Figure 8.
Power supply efficiency is improved by turning off the
HIP5600 when the SMPS is up and running. In this application the output of the HIP5600 would be set via RF1 and RF2
to be about 9V. The tickler winding would be adjusted to about
12V to insure that the HIP5600 is kept off during normal operating conditions. The input current under these conditions is
approximately equal to ISlAS' (See Figure 28).
The HIP5600 can supply a 450J.lA (:l:20%) constant current.
(See Figure 15). It makes use of the internal bias network.
See Figure 28 for bias current versus input voltage.
With the addition of a potentiometer and a lOI!F capacitor the
HIP5600 will provide a constant current source. lOUT is given
by Equation 13 in Figure 16.
The HIP5600 can be operated as a self-oscillating buck regulator for increased output currents and circuit efficiencies
approaching 75%. The circun shown (Figure 17) is capable of
operating from enher DC (50VDC to 400VDC) or AC
(90VRMS to 264VRMS) and is optimized for a 24V 150mA
output. The output voltage is set by RF1 and RF2 resistor values and is slightly higher than the value predicted in Equation
1A. The frequency of operation for the circuit is around 16kHz.
The circun shown (Figure 18) is optimized for a 24V 250mA
output with a 90VRMS to 132VRMS input. Output short circun
protection is provided by adding a pnp transistor and a small
O.22Q sense resistor. A snubber circuit was also added to
reduce the power dissipation in the P-IGBT. The frequency of
operation for the circuit is around 18kHz.
+SOVDC TO +400VDC
+20VDC TO +400VDC
lOUT '" 1.21V
R1
NOTES:
(Ea. 13)
1. Your Floating
2. Fixed SOOItA Current Source
FIGURE 15. CONSTANT 450pA CURRENT SOURCE
90VRMS
FIGURE 16. ADJUSTABLE CURRENT SOURCE
TO 264VRMS
FIGURE 17. HIGH CURRENT "BUCK" REGULATOR
7-103
HIP5600
OUTPUT SHORT
CIRCUIT PROTECTION
..
~ ::~:;:;-t·-----··--·---
--..-----'"
SNUBBER CIRCUIT
HVRMS TO 132VRMS
AC
HI
24VDC, 0.25A
FIGURE 18. HIGH CURRENT "BUCK" REGULATOR WITH OUTPUT SHORT CIRCUIT PROTECTION AND SNUBBER
Typical Performance Curves
lz
-
-0.4
5i
:>
w
-0.8
0
CI -1.0
~
~ -1.2
-1.4
V
--
~
-1.6 -40
-20
0
25
,
1mAT020mA
.....
~
1mAT030mA
1mATOjOmA
1
---
~
1mATO 20mA
~
0
r--1mA TO 10mA
....
----
w
....
::>
0.
....
:>
- r--....
f--- 1mA TO 10mA
0 -0.6
VIN",50VDC
40
60
80
100
-20
VIN,,400VDC
0
25
40
CASE TEMPERATURE rC)
CASE TEMPERATURE (OC)
FIGURE 19. LOAD REGULATION vs TEMPERATURE
--
60
80
FIGURE 20. LOAD REGULATION VS. TEMPERATURE
85
VIN= 170VDC,IL" 10mA,h120Hz, TC-+25°C_
80
~
z
75
0
70
13w
65
....
w
II:
...w
60
a:
55
0.
0.
,
1\
-
I I
I 'I.
I
I
I I
1/
-- ........
NO BYPASS CAPACITOR
45 1
o
I
I
VIN '" 4ooVDC,IL",10mA, !-12OHz, Tc. +2S"C
r--
80
~ 70
~ I
I
I
I
I
1'\ I
I 11'F BYPASS CAPACITOR \10I'F BYPASS CAPACITOR
["') 1'-0..
50
I
10
20
30
-
lS
13
60
'\
~10JlF BYPASS
~
I" 11'F BYPASS CAPACITOR
CAPACITOR
~
II: 50
/
~
0.
~
1
40 50 60 70 80
OUTPUT VOLTAGE (V)
40 -
NO ~YPASS ~APACn:OR
---
""'"'-
3O~1~~~~~-=~~-=~~
Tj
110 100 110
o
FIGURE 21. RIPPLE REJECTION RATIO (OUTPUT VOLTAGE)
50
100
150
200
250
OUTPUT VOLTAGE (V)
300
350
FIGURE 22. RIPPLE REJECTION RATIO (OUTPUT VOLTAGE)
7-104
HIP56DD
Typical Performance Curves (Continued)
IS
80 10flFBYPASS
CAPACITOR
iii'
:!!. 75
"Y
z
0
~
70
..,ww
65
.".
(J
g.
g.
.".
55
J.
./
"\
/
~
~
50
t..,w
70
..J
60
a:
55
ir--
L y
w 65
a:
w
A
g.
g.
\ /\
AI
lflF BYPASS CAPACITOR
I~
0
I
I
10
100
lk
10k
lOOk
INPUT FREQUENCY (Hz)
1M
10M
"
...........
r\.
"-1
I
50
45
1
/
I....
1
10
~
'I
~.
"IIf
;1
_ 1flF BYPASS CAPACITOR
NO BYPASS CAPACITOR
45
,
VIN a 400VDC,IL.l0mA, VOUT a 15V, TCa +250 C
10 lOflFBYPASS
iii'
~
:!!. 75 CAPACITOR
z
'\.'\.
J .........
i"""J
/
a:
w
..J 60
a:
,
86
VIN a170VDC,ILal0mA, VOUTa15V, TCa+25oC
NO BYPAS·S CAPACITOR
100
lk
10k
lOOk
1M
10M
INPUT FREQUENCY (Hz)
FIGURE 23. RIPPLE REJECTION RATIO (INPUT FREQUENCy)
FIGURE 24. RIPPLE REJECTION RATIO (INPUT FREQUENCy)
85r---,---_T--~~--,---_T----~--,
VIN .400VDC, VOuT,,10mA, I" 120Hz, TC" +250 C
80
(REFERENCE FIGURE 3)
55
55
SOL----L--~L-
o
5
__
~
__
-..J~
__
~
__
10
15
20
25
OUTPUT CURRENT (mA)
~
_____'
50L---~--~----L---~--~----L---~
o
35
30
FIGURE 25. RIPPLE REJECTION RATIO (OUTPUT CURRENT)
5
10
15
20
25
OUTPUT CURRENT (mA)
30
35
FIGURE 26. RIPPLE REJECTION RATIO (OUTPUT CURRENT)
520
510
100~-----t----~r-----t-----+-.---;--;
500
4110
1!2 480
470
J
460
450
440
430
420
10
100
lK
10K
FREQUENCY (Hz)
lOOK
1M
FIGURE 27. OUTPUT IMPEDANCE
50
100
200
300
INPUT VOLTAGE (VDC)
FIGURE 28. IBIAS vs INPUT VOLTAGE
7-105
400
HIP5600
Typical Performance Curves
(Continued)
I I
VOUT
1\ 100mVIDIV
~
lih1il'F
15V
[72
IV
I
ChOI'F
5
~
1SV
I\(
~
II'
IDI
1r
t -f
OV
I
ffi
~
T = 100maJDIV
~
1.17
~ 1.16
w 1.15
~ 1.14
1
w 1.17
~ 1.16
!:i 1.15
gw
~
ll!
~
ll!
1.14
1.13
1.12
1.11
1.10
1.08
I-
NDI
T= 100msIDIV
~
1mA
~1.20rr-~~--~~·-+--+---~-~H
/
~ n~~:t::~~~f:::~~~::~
SmA
~ ~-.;;;s ~
~
~ 1.15
10mA
............ ~ ~
-30mA/
w
~ 1.10 I-I"-oo;:±---I=-....=~+---I....;;;:::II-t-I
~
""'/ '" i"""--.......
II!
~
20mA
II:
I
-40
o
25
40
60
CASE TEMPERATURE ("C)
·20
80
- --
CASE TEMPERATURE ("C)
FIGURE 32. REFERENCE VOLTAGE va TEMPERATURE
1.20
IoUT,,10mA
-
1.18
~
w 1.16
Tc=-4o"C
~
-- -- --r---
TC .. +2SOC
g'"'
U
Z
w 1.10
II:
~
w 1.08
TC=+100oC - - -
200
300
INPUT VOLTAGE (VDC)
1.14
w 1.12
I
100
1.05 t+--~t_--t---+_-_;_--+_-_+I
1.00 L-4~0--•.L20--.J0'---:25':---4~0--.J60---8UO
100
FIGURE 31. REFERENCE VOLTAGE va TEMPERATURE
~ 1.18
5j
1.2S ......- - , . . . . - -......- - - r - - - , - - - - r - - - . . ,
1mA
1.11
1.20
1.19
'-
VIN·400VDC:
VOUT,,1SV
:
TJ" +2SoC :
FIGURE 30. LOAD TRANSIENT RESPONSE
.
1•13
_ 1.12
1.10
C3r°l'~
~
VIN-50VDC
1.20
:> 1.18
;; 1.18
""'"
OmA
FIGURE 29. LINE TRANSIENT RESPONSE
1.21
~
~ 10mA
B
!:i SmA
VOUT" 15VDC::
IL,,5mA
TJ 1" +25 C
100V
...
r-
20mVIDIV
~
C3.101lf
/
400V
INPUT
VOLTAGE
rt
1\
I I
~
- -- .............--.
......
30m~
1.06
FIGURE 33. REFERENCE VOLTAGE va INPUT VOLTAGE
100
200
300
INPUT VOLTAGE (VDC)
FIGURE 34. REFERENCE VOLTAGE vs VIN ;
CASE TEMPERATURE OF +25"(:
7·106
SmA
10;:;;A"
' - ............. ...............
..... 20mA
II:
400
1mA
400
HIP5600
Typical Performance Curves
(Continued)
80
80
VIN-400VDC
VIN_50VDC
75
I1mA
~ 70
..
\
z
w 65
a:
a:
.. ~
:::> 60
(.)
~
55
~
~
10'"
/
75
.... ~
~ 70
I
...z
20mA
w 65
a:
a:
:::> 60
(.)
~
30mA
~
so
50
45
-40
55
45
o
25
40
60
CASE TEMPERATURE ("C)
·20
80
100
-40
775
2000
770
Tc oo +25":;'
765
!z
i
8
~
760
0
25
40
CASE TEMPERATURE ("C)
~
~
755
~
--
60
80
FIGURE 36. IAOJ vs TEMPERATURE
FIGURE 35. IAOJ vs TEMPERATURE
~
·20
-
VIN",100VDC
TC-25·C
1500
~
MINIMUM LOAD
CURRENT
ffi 1000
a:
a:
Tc _ +100·C
:::>
(.)
SOO
750
745
50
100
200
300
INPUT VOLTAGE (VDC)
01
400
FIGURE 37. MINIMUM LOAD CURRENT VS VIN
234
VOUT· VAOJ (VDC)
FIGURE 38. TERMINAL CURRENTS vs FORCED V REF
55
1 1-
-
TC·-4O"C
Tc-+1oo• C
25
20
Tc-+25oC
50
100
150
200
250
300
INPUT-OUTPUT (VDC)
350
FIGURE 39. CURRENT LIMIT vs TEMPERATURE
7·107
400
5
HIP5600
Evaluation Boards
o
VIN
.
VOUT
HIP5600 EVALUATION BOARD
3.25"
3.25" - - - - - - - ;..~
FIGURE 40. EVALUATION BOARD (TOP)
FIGURE 41. EVALUATION BOARD METAL MASK (BOTTOM)
lvlN
ADJ 1 • • •
VOUT·
•• • •
••
rn
VIN
• •
•
• •
" •
••
m+
L.!J .
VOUT
HIP5600 EVALUATION BDARD
~"E-------
3.25"
..
FIGURE 42. EVALUATION BOARD METAL MASK (TOP)
7-108
ICL7660
CMOS Voltage Converter
April 1994
Features
Description
• Simple Conversion of +5V Logic Supply to ±5V
Supplies
The Harris ICL7660 is a monolithic CMOS power supply
circuit which offers unique performance advantages over
previously available devices. The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of +1.5V to +10.0V, resulting in complemetary output
voltages of -1.5V to -10.0V. Only 2 non-critical external
capacitors are needed for the charge pump and charge
reservoir functions. The ICL7660 can also be connected to
function as a voltage doubler and will generate output
voltages up to + 18.6V with a +1 OV input.
• Simple Voltage Multiplication (Vour = (-) nVIN)
• Typical Open Circuit Voltage Conversion Efficiency
99.9%
• Typical Power Efficiency 98%
• Wide Operating Voltage Range 1.SV to 10.0V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• No External Diode Over Full Temperature and Voltage
Range
Applications
• On Board Negative Supply for Dynamic RAMs
• Localized ~Processor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
The oscillator, when unloaded, oscillates at a nominalfrequency of 10kHz for an input supply voltage of 5.0V. This
frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5V to + 1O.OV), the
LV pin is left floating to prevent device latchup.
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
Contained on the chip are a series DC supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output NChannel switch source-substrate junctions are not forward
biased. This assures latchup free operation.
PACKAGE
ICL7660C"TV
O"C to +70"C
ICL7660CBA
O"C to +70"C
8 Lead SOIC (N)
ICL7660CPA
O"C to +70"C
8 Lead Plastic 01 P
ICL7660M"TV (Note)
O"C to +70"C
8 Pin Metal Can
An enhanced direct replacement for this part, the ICL7660S,
is now available and should be used for all new deSigns.
8 Pin Metal Can
NOTE: Add 1883B to part number if 883B processing IS requIred.
Pinouts
ICL7660 (PDIP, SOIC)
ICL7660 (CAN)
TOP VIEW
TOP VIEW
V+ (AND CASE)
NCOsv+
CAP+
2
. 7 OSC
GND3
SLV
CAP·
5 VOUT
4
CAUTION: These devices are sensitive to electrostatic discharge. Users should lollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-109
File Number
3072.1
Specifications ICL7660
Absolute Maximum Ratings
Thermal Information
Supply Voltage •••••••••••••••••••.•••••••••••••••• +1 0.5V
LV and OSC Input Voltage •••••• -0.3V to (V+ +C.3Y) for V+ < 5.5V
(Note 1)
(V+ -5.5V) to (V+ +C.3V) for V+ > 5.5V
Current Into LV (Note 1) ••••••••••••.•••••• 201J.A for V+ > 3.5V
Output Short Duration (VSUPPl.y:S; 5.5V) .•••••••..••• Continuous
Thermal Resistance
°JA
°JC
Plastic DIP Package ••.••••.•.•••••• 150oCM'
Plastic SOIC Package .••••••.••••••• 170oCM'
Metal Can •••.•...•..•••••••.....• 156°CM' 68°CM'
Storage Temperature Range ...•••••....•...•• -65°C to +150°C
Lead Temperature (Soldering, 1Osec) •.••..••......•••.. 300°C
(SOIC - Lead lips Only)
-
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause pIlrmansnt dsmage to the dsvice. This is a stress only rating and operation
of the device at these or any other conditions above /hose indicated In the CpIlra60nai sections of this SpIlCifica60n is not Implied.
Operating Conditions
Operating Temperature Range
ICL7660M ••••••••••••••••••..•••••••••• -55°C to +125°C
Electrical Specifications
V· = 5V, TA = +25°C, cosc = 0, Test Circuit Figure 11 (Unless Otherwise Specified)
MIN
TVP
MAX
UNITS
-
170
500
IJ.A
MIN:s;TA:s; MAX, RL = 10kO, LV to GROUND
1.5
-
3.5
V
Supply Voltage Range - Hi
MIN:s; TA:s; MAX, RL = 10kO, LV to Open
3.0
-
10.0
V
Output Source Resistance
lOUT = 20mA, TA = +25OC
55
100
0
-
120
0
SYMBOL
PARAMETER
TEST CONDITIONS
Supply Current
RL=oo
VL+
Supply Voltage Range - Lo
VH+
ROUT
1+
ICL7660C •••••••••••.•••••••••.••.•••.••••• COC to +70OC
-
lOUT = 20mA, OoC :s; TA :s; +70oC
lOUT = 20mA, _55°C :s; T... :s; + 125°C
-
V· =.2V, lOUT = 3mA, LV to GROUND
COC:s; T... :S; +7COC
V+ = 2V, lOUT = 3mA, LV to GROUND,
-55°C:s; T... :S; +125OC
VOUTEF
Zosc
150
0
300
0
-
400
0
-
kHz
-
10
Power Efficiency
RL =5kO
95
98
Voltage Conversion Efficiency
RL=oo
97
99.9
Oscillator Impedance
V+ =2 Volts
-
1.0
Oscillator Frequency
fosc
PEF
-
V = 5 Volts
100
-
-
%
%
MO
kO
NOTES:
1. Connecting any input terminal to voltages greater than V+ or less than GROUND may cause destructive latchup. It is recommended that
no Inputs from sources operating from external supplies be applied prior to ·power up" of the ICL7660.
Functional Block Diagram
I
I
RC
OSCILLATOR
--0
+2
I
v+
-
1
CAP+
VOLTAGE
LEVEL
TRANSLATOR
CAP-
I
F~.....o VOUT
IrtOSC
LV
I
VOLTAGE
REGULATOR
I
Y :)--11
1
OJ"
7-110
Ir
.I
I
LOGIC
I
• 'LI........N_£nN
...._O_R_K........~
ICL7660
Typical Performance Curves
(Test Circuit of Figure 11)
10K
TAS+2S"C
8
r==
r--
~
~6h~6I'!:""""~~l---:rLl~'-Ir-71
1\
!:l
~
,
\.
~41'-~r--:r~<-:~-7IF-,79~~
0..
0..
::>
r-.....
~~=¢:z;~::j2=~ZI
'" 2
0'----l1----1_--L_-L._...l----l
-55
·25
0
25
50
100 125
TEMPERATURE ("C)
FIGURE 1. OPERATING VOLTAGE AS A FUNCTION
OF TEMPERATURE
2
!il
m 200
II:
100
5...0..
5
50
lIS r--
~
~ 250
6
7
8
I--""'"
i,......o- ~
-
o
-55
·25
0
25
50
75
TEMPERATURE ("C)
100
88
!U
86
84
II:
w
~
0..
I
-
IoUTs1SmA
80
w
>
r--
V+",.5V
I-
~
82
I
_I-'"
..... r-.
IoUTs1mA
84
IEw
k'"
~:a+2V
I
TAS+2S"C
88
tiz
;; 300
150
S
100
l
louTs1mA
!"'
4
FIGURE 2. OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF SUPPLY VOLTAGE
3SO
cr
3
SUPPLY VOLTAGE (V+)
82
V+s+5V
80
125
100
1k
10k
OSC. FREQUENCY lose (Hz)
FIGURE 3. OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE
FIGURE 4. POWER CONVERSION EFFICIENCY AS
A FUNCTION OF OSC. FREQUENCY
10K
to..
]
tz
1
1\
1K
w
5w
20
(,) 18
If
~
l1l
5
II:
o
~
~
V+s5V
TA,,+25°C
o
10
1.0
10
100
1000
16
1\,
14
"
i12
,
~ 100
~
J
r\
10K
Cosc(pF)
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSC. CAPACITANCE
10
8
V+s+5V
6
-50 -25
"
r'-...
r-.....
0 25 50 75 100 125
TEMPERATURE ("C)
FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS
A FUNCTION OF TEMPERATURE
7·111
ICL7660
Typical Performance Curves
5
~
2
6>
~
1
8
tiz
...~
70
...~
l.."..;' "
SLOPE55n
I\.
/
.I
/
u 20
a:
'" ,
1/
0
1/
1+- 00
!jI-'
/
50
>
z 30
-3
-5
::I&.."
w 60
z
-'
-4
~
")"
iii
a:
w 40
.2
100
~
PEFF ...
00
w 80
0
0
·1
I!:
g100
:
i
,
v+".sV
3
w
:
T",,+250C
4
(Conlinued)(Test Circuit of Figure 11) (Continued)
/
0
o
I
!i:
60
w
50 ~
40
i3
30
~
20 ~
T",,+25OC
V+=+5V
/
10
1
80
70 .:!:
10
I
10 20
30
40 50
LOAD CURRENT IL (mA)
60
til
o
LOAD CURRENT IL (mA)
FtGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS AFUNCTION OF LOAD CURRENT
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT
+2
~,
T,,=+250C
V+,,2V
g 100
\
+1
\
·2
,.. ~ ~ ~
o
SlO
w
80
W
70
60
~
\
,/
~
~
a:~
J
g!
8a:
~
~
SLOPE 1500
I I
i'-' r--I
~
.....
,
oC-o
./
L
16.0
14.0
10.0
6.0
I- 4.0
I- 2.0
T,,=+250C
V+.2V
~
o
18.0
8.0
./
20
10
20.0
12.0
./
2345678
LOAD CURRENT IL (rnA)
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
..........
PEFF
50
40
30
0
...-
OmA
1.5
3.0
4.5
6.0
7.5
~
w
15
1000pF) the values of C1 and C2 should be increased to 1001lF.
FIGURE 11. ICL7660 TEST CIRCUIT
7·112
ICL7660
Detailed Description
The ICL7660 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive lOI1F polarized electrolytic types. The mode of operation of the device may be
best understood by considering Figure 12, which shows an
idealized negative voltage converter. Capacitor C, is
charged to a voltage, V+, for the half cycle when switches S,
and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation,
switches S2 and S4 are closed, with S, and S3 open, thereby
shifting capacitor C, negatively by V+ volts. Charge is then
transferred from C, to C2 such that the voltage on C2 is
exactly V+, assuming ideal switches and no load on C2 . The
ICL7660 approaches this ideal situation more closely than
existing non-mechanical circuits.
In the ICL 7660, the 4 switches of Figure 12 are MOS power
switches; S, is a P-channel device and S2' S3 and S4 are Nchannel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 and S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit start-up, and under output short
circuit conditions (Vour V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latch up.
=
This problem is eliminated in the ICL7660 by a logic network
which senses the output voltage (Vour) together with the
level translators, and switches the substrates of S3 and S4 to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-latch up Circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5V the LV terminal must be left open to
insure latch up proof operation, and prevent device damage.
2
S,
8
0"0
VINO
3
!
i
i
I
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
A The driver circuitry consumes minimal power.
B The output switches have extremely low ON resistance and virtually no offset.
C The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative voltage conversion if large values of C, and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
E =1/2 C, (V, 2 - Vi)
where V, and V2 are the voltages on C, during the pump
and transfer cycles. If the impedances of C, and C2 are relatively high at the pump frequency (refer to Figure 12) compared to the value of RL, there will be a substantial difference
in the voltages V,and V2. Therefore it is not only desirable to
make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C,
in order to achieve maximum efficiency of operation.
Do's And Don'ts
1.
Do not exceed maximum supply voltages.
2.
Do not connect LV terminal to GROUND for supply voltages greater than 3.5V.
3.
Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
4.
When using polarized capaCitors, the + terminal of C 1
must be connected to pin 2 of the ICL7660 and the + terminal of C2 must be connected to GROUND.
5.
If the voltage supply driving the ICL7660 has a large
source impedance (250 - 300), then a 2.211F capaCitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V1I1S.
6.
User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions. A lN914 or similar diode
placed in parallel with C2 will prevent the device from
latching up under these conditions. (Anode pin 5, Cathode pin 3).
lit
'1-
C,
~!
3
t~
~
5
0
VOUT--V..
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
7-113
ICL7660
V+
FIGURE 13A. CONFIGURATION
FIGURE 13B. THEVENIN EQUIVALENT
FIGURE 13. SIMPLE NEGATIVE CONVERTER
f
V
t
.(V+)
FIGURE 14. OUTPUT RIPPLE
V+
FIGURE 15. PARALLELING DEVICES
V+
FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
7-114
ICL7660
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 for generation of negative supply voltages. Figure
13 shows typical connections to provide a negative supply
negative (GND) for supply voltages below 3.5V.
The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 138. The voltage source has
a value of -V+. The output impedance (Ro) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 12), the switching frequency, the value of C, and C2 ,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for Ro is:
Ro;;; 2(Rsw, + RSW3 + ESRc,) +
potentially swamp out a low 1/(fpUMP • C,) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and 8, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C2 at the instant it goes from being charged by C, (current
flow into C2 ) to being discharged through the load (current
flowing out of C2). The magnitude of this current change is
2. lOUT, hence the total drop is 2. lOUT • eSRC2 V. Segment 8
is the voltage change across C2 during time t2 , the half of the
cycle when C2 supplies current to the load. The drop at 8 is
lOUT. t21C2 V. The peak-to-peak ripple voltage is the sum of
these voltage drops:
2(RsW2 + RSW4 + ESRc,) +
V R1PPLE '"
1
- - - - - + E S RC2
(lpuMp) (Cl)
losc
--""2';;';;"-- , Rswx =MOSFET switch resistance)
[
2
(Ipu~p) (C2)
+ 2 (ESRC2)
]
lout
Again, a low ESR capacitor will reset in a higher performance output.
Paralleling Devices
Combining the lour Rswx terms as Rsw, we see that:
Ro =
2 (Rsw) +
1
- - - - + 4 (ESRc,) + ESRC2
(IPUMP) (Cl)
RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance
graphs), typically 230 at +25°C and 5V. Careful selection of
C, and C2 will reduce the remaining terms, minimizing the
output impedance. High value capacitors will reduce the
1/(fpUMP • C,) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fpUMP. C1) term, but may have the side effect
of a net increase in output impedance when C, > 10llF and
there is no longer enough time to fully charge the capacitors
every cycle. In a typical application where fosc = 10kHz and
C = C, = C2 = 101lF:
Ro = 2 (23) +
1
(5. 103) (10-5)
Any number of ICL7660 voltage converters may be paralleled to reduce output resistance. The reservoir capacitor,
C2 , serves all devices while each device requires its own
pump capacitor, C,. The resultant output resistance would
be approximately:
RouT =
RoUT (01 ICL7660)
n (number 01 devices)
Cascading Devices
The ICL7660 may be cascaded as shown to produced larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limit is
10 devices for light loads. The output voltage is defined by:
VOUT = -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individuallCL7660 RoUT values.
+ 4 (ESRc,) + ESRC2
Ro =46 +20+ 5 (ESRcl
Changing the ICL7660 Oscillator Frequency
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fpUMP • C,) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Ro;;; 2 (23) + (5.103) (10-5 ) + 4 (ESRc,) + ESRc2
Ro = 46 + 20 + 5 (ESRcl
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 17. In order to prevent possible
device latchup, a 1kn resistor must be used in series with
the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the
addition of a 10kn pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking, as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.
7-115
ICL7660
v+
v+
Combined Negative Voltage Conversion
and Positive Supply Doubling
CMOS
GATE
ICL7660
FIGURE 17. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7660 at low load levels by lowering the oscillator frequency. This reduces the switching losses. and is shown in
Figure 18. However. lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (G 1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C 1 and C2 by the same factor that
the frequency has been reduced. For example. the addition
of a l00pF capacitor between pin 7 (OSC) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10). and thereby necessitate a corresponding increase in the value of G1 and G2 (from 10llF to
100IlF).
Figure 20 combines the functions shown in Figures 13 and
Figure 19 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be. for example. suitable for generating +9V and -SV from an
existing +SV supply. In this instance capacitors C1 and C3
perform the pump and reservoir functions respectively for
the generation of the negative voltage. while capaCitors C2
and C4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions. however. in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
v+
L------"-i +
VOUT" (nVIN - VFDX)
VOUT = (2V+) "
(VFDll- (VFD2)
+
.J." c.
Cosc
FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
1--:-....- ... VOUT
+~ C:z
VoHage Splitting
FIGURE 18. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
The ICL7660 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 19. In this application. the pump inverter switches of the ICL7660 are used to
charge G1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage drop of diode 0 1).
On the transfer cycle. the voltage on C 1 plus the supply voltage (V+) is applied through diode O2 to capacitor C2 • The
voltage thus created on C2 becomes (2V+) - (2VF) or twice
the supply voltage minus the combined forward voltage
drops of diodes 0 1 and O2 .
The bidirectional characteristics can also be used to split a
higher supply in half. as shown in Figure 21. The combined
load will be evenly shared between the two sides. Because
the switches share the load in parallel. the output impedance
is much lower than in the standard circuits. and higher currents can be drawn from the device. By using this circuit. and
then the circuit of Figure 16. + 1SV can be converted (via
+7.S. and -7.S) to a nominal -1SV. although with rather high
series output resistance (-2S00).
The source impedance of the output (VOUT) will depend on
the output current. but for V+ = SV and an output current of
lOrnA it will be approximately 600.
vOUT-V+- v2
V+
L-_--L~======:::::.Lv"
VOUT(2V+) - (2VF)
1+
---lT" c
L - -_ _ _ _ _ _
1
FIGURE 19. POSITIVE VOLTAGE DOUBLER
7-116
FIGURE 21. SPLITTING A SUPPLY IN HALF
ICL7660
Regulated Negative Voltage Supply
+8V
50k
In some cases, the output impedance of the ICL7660 can be
a problem, particularly if the load current varies substantially.
The circuit of Figure 22 can be used to overcome this by
controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7660s output does not respond instantaneously to
change in input, but only after the switching delay. The circuit
shown supplies enough delay to accommodate the ICL7660,
while maintaining adequate feedback. An increase in pump
and storage capacitors is desirable, and the values shown
provides an output impedance of less than 50 to a load of
10mA.
Other Applications
Further information on the operation and use of the ICL7660
may be found in A051 ·Principals and Applications of the
ICL7660 CMOS Voltage Converter".
FIGURE 22. REGULATING THE OUTPUT VOLTAGE
+5V LOGIC SUPPLY
TTLI~~~
>----------..,h
18
RS232
DATA
+5V
OUTPUT
-5V
FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY
7-117
r-1
n
L....-I L.
I
ICL7660S
Super Voltage Converter
April 1994
Features
Description
• Guaranteed Lower Max Supply Current for All
Temperature Ranges
The ICL7660S Super Voltage Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry standard ICL7660 offering an extended operating supply voltage range up to 12V,
with lower supply current. No external diode is needed for
the ICL7660S. In addition, a Frequency Boost pin has
been incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section.
Critical parameters are guaranteed over the entire commercial, Industrial and military temperature ranges.
• Wide Operating Voltage Range 1.5V to 12V
• 100% Tested at 3V
• No External Diode Over Full Temperature and Voltage
Range
• Boost Pin (Pin 1) for Higher Switching Frequency
• Guaranteed Minimum Power Efficiency of 96%
• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%
• Improved SCR Latchup Protection
• Simple Conversion of +5V Logic Supply to ±5V
Supplies
• Simple Voltage Multiplication VOUT = (-)nVIN
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices
Applications
• Simple Conversion of +5V to ±5V Supplies
• Voltage Multiplication VOUT =±nviN
• Negative Supplies for Data AcquiSition Systems and
Instrumentation
• RS232 Power Supplies
The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V. Only
2 non-critical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7660S can be
connected to function as a voltage doubler and will generate
up to 22.8V with a 12V input. It can also be used as a voltage multiplier or voltage divider.
The chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of
5.0V. This frequency can be lowered by the addition of an
external capaCitor to the "OSC" terminal, or the oscillator
may be over-driven by an external clock.
The "LV" terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latch up.
• Supply Splitter, VOUT = ±Vsl2
Pinouts
De OSC ::SOO::
ICL7660S (PDIP, SOIC)
TOP VIEW
ICL7660S (CAN)
TOP VIEW
v+ (AND CASE)
BOOST
CAP+
v+
2
7
GND3
6LV
CAP- 4
5
VOUT
GND
Od
r ermg normat'lon
I "
PART NUMBER
TEMPERATURE
O"C to +70"C
8 Lead Plastic
SOIC(N)
ICL7660SCPA
O"C to +70"C
8 Lead Plastic DIP
ICL7660SCTV
O"C to +70"C
ICL7660SIBA
_40°C to +85°C
8 Lead Plastic
SOIC(N)
ICL7660SIPA
-40°C to +85OC
8 Lead Plastic DIP
ICL7660SITV
.40oC to +85°C
8 Pin Metal Can
ICL7660SMTV
(Note)
-55°C to +125°C
8 Pin Metal Can
VOUT
CAP-
PACKAGE
ICL7660SC9A
8 Pin Metal Can
NOTE: Add 18839 to part number If 8839 proceSSIng IS required.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-118
File Number
3179.1
Specifications ICL7660S
Thermal Information
Absolute Maximum Ratings
8JA
8JC
Supply Voltage .•••.•...••..•....••..•.•..•...•.•.. + 13.0V Thermal Resistance
Plastic DIP. . • • • . . . • • • • • • • • • • . . • . • • . 1500cfW
LV and OSC Input Voltage (Note 1)
Plastic SOIC . . . • . . • . . . • • . . • • . . • • . . • 1700cfW
V+ < 5.5V •..••..•.•.••....•..•••••.•.• -O.3V to V+ + O.3V
V+ > 5.5V .......................... V+ -5.5V to V+ +O.3V
Metal Can ••..•...••...•..••.......
155°CfW 700 CfW
Lead Temperature (Soldering 10s) .•••.•••..•.•.••...• +300oC
Current into LV (Note 1)
(SOIC - Lead "Tips Only)
V+ > 3.5V .•••••..•.......•••..••...•••..•.••••.. 2011A
Output Short Duration
VSUPPLY:S 5.5V ..•....••...........••..•.•••. Continuous
Storage Temperature Range ....•••...••..... -65°C to + 150°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a strsss only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range
ICL7660SM ..•..••.............•........ -55°C to +125°C
ICL7660SI •••.••••..•...••.•••.••••.••... -4COC to +85°C
ICL7660SC •.•.•.•••.......••........•...• COC to +70oC
=5V, TA =+25°C, OSC =Free running, Test Circuit Figure 12, Unless Otherwise Specified
Electrical Specifications
V+
Oscillator Frequency (Note 3)
losc
Power Efficiency
P EFF
NOTES:
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs
Irom sources operating Irom external supplies be applied prior to 'power up' of ICL7660S.
2. Derate linearly above +5COC by 5.5mWfC
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged Into a test socket, there is usually
a very small but finite stray capacitance present, 01 the order 01 5pF.
4. The Harris ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in
existing designs which incorporate an external diode with no degradation in overall circuit performance.
5. All significant improvements over the Industry standard ICL7660 are highlighted.
7-119
Specifications ICL7660S
Electrical Specifications
V+ = 3V, TA = +25"C, OSC = Free running, Test Circuit Rgure 12, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
V+ = 3V, RL = 00, +25°C
-
26
100
j1A
O"C < TA < +700 C
-
-
125
j1A
125
j1A
-
150
j1A
V+ = 3V, lOUT = 10mA
-
97
150
(1
O"C < TA < +7O"C
-
-
200
(1
-40"C < TA < +85°C
-
-
200
(1
250
SYMBOL
PARAMETER
Supply Current (Note 3)
1+
TEST CONDITIONS
-4O"C < TA < +85°C
-55°C < TA < + 125°C
OUtput Source Resistance
RoUT
-
-
V+ = 3V (same as 5V conditions)
2.5
4
OOC < TA < +7O"C
1.5
-
-40"C < TA < +85°C
1.5
-55°C < TA < + 125"C
1.0
V+=3V, RL=oo
99
TMIN
~O
80
w
.1
-3
.,. /
·4
·5
./
o
(j
70
IEw
60
~
SO
10
~
20
V
0
o
40
30
LOAD CURRENT (mol)
100
V+.2V
T",,+2SoC
90
~
~
w
-
o
".
~
l
ti
ffi
(j
80
60
so
40
-
30
I
I
40
50
~
w
a:
a:
:::I
U
~
30 a.
a.
V+=5V
20
T,,=+25°C _ 10
20
<
70 .§.
L
10
:::I
til
o
60
........
~
"""'"
/
/
20
~
1.5
B
V+=2V
T,,=+2SOC -
3
1
1
1-
4.5
6
7.5
4
2
~
:t
iii
o
9
FIGURE 1O. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
V+ .. 5V
T",,+2SoC
400 N·10mA
,
Cl-C1·
w
U
10I'F
z 300
g
;!
8
<
12 .§.
10 ~
w
8 fI!
6
........
LOAD CURRENT (mA)
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
a:
~
I"--..
./
40
o/
o
w
16 b
14 ~
~
LOAD CURRENT (mol)
IIIw
~
50
10
23456789
0;-
70
60
~ $ 30
~
5a.
""'[b.
/
80
§a:
V
V
~
80
/
FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
2
~
~
LOAD CURRENT (mA)
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
·2
V
20
w
-
1/
z
8a:
"
100
/
a: 40
~ 30
~
10
~
80
1JlF
C1 ·C2"
1OOl'F
200
100
118~.~~1
1\
0
100
, '\ ,
...
~
1k
10k
100k
OSCILLATOR FREQUENCY (Hz)
FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREOUENCY
NOTE 6. These curves Include in the supply current that current fed directly into the load AI from the V+ (See Figure 12). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half,-through the ICL7660S, to the negative side of
the load. Ideally, Your 2VIN, Is 21 l , so VIN X Is Your x Il •
=
=
=
7-122
ICL7660S
Detailed Description
A. The drive Circuitry consumes minimal power.
The ICL76605 contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
2 external capacitors which may be inexpensive 10llF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 13,
which shows an idealized negative voltage converter.
Capacitor C l is charged to a voltage, V+, for the half cycle
when switches 51 and 53 are closed. (Note: 5witches 52
and 54 are open during this half cycle.) During the second
half cycle of operation, switches 52 and 54 are closed, with
51 and 53 open, thereby shifting capacitor C l to C2 such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2 . The ICL76605 approaches this ideal situation
more closely than existing non-mechanical circuits.
B. The output switches have extremely low ON resistance
and virtually no offset.
v+
IS
v+
1------1r-~ (+5V)
C. The impedance of the pump and reservoir capaCitors are
negligible at the pump frequency.
The ICL76605 approaches these conditions for negative
voltage conversion· if large values of C l and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E
2
SI
3
-
NOTE: For large values of Cosc (> 1OOOpF) the values of C l
and C2 should be Increased to 100llF
FIGURE 12. ICL7660S TEST CIRCUIT
This problem is eliminated in the ICL76605 by a logiC
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of 53
and 54 to the correct level to maintain necessary reverse
bias.
The voltage regulator portion of the ICL76605 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation "LV" pin should be connected
to GND, disabling the regulator. For supply voltages greater
than 3.5V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.
Theoretical Power Efficiency Considerations
82
0':'
0/0
VINO
In the ICL76605, the 4 switches of Figure 13 are M05
power switches; 51 is a P-Channel devices and 52, 53 and
54 are N-Channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of
53 and 8 4 must always remain reverse biased with respect
to their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit start up, and under output
short circuit conditions (VOUT = V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latch up.
=1/2C l (V 12 - Vl)
where VI and V2 are the voltages on C l during the pump
and transfer cycles. If the impedances of C l and C2 are
relatively high at the pump frequency (refer to Figure 13)
compared to the value of RL' there will be substantial
difference in the voltages VI and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C l in order to achieve maximum efficiency of
operation.
·· I
··
~
S,!·
JUUL,
,,••
,,
,,
,,
CI
84
:
!
! ~.
5
)
VOUT=-VIN
FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER
Do's and Don'ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however. transient conditions including start-up are okay.
4. When using polarized capacitors. the + terminal of C l
must be connected to pin 2 of the ICL76605 and the +
terminal of C2 must be connected to GND.
5. If the voltage supply driving the ICL76605 has a large
source impedance (250 - 300). then a 2.21lF capacitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V1jlS.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.
In theory a voltage converter can approach 100% efficiency
if certain conditions are met:
7-123
A 1N914 or similar diode placed in parallel with C2 will
prevent the device from latching up under these conditions. (Anode pin 5. Cathode pin 3).
ICL7660S
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
14 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 12V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GNO)
for supply voltage below 3.5V.
r
Ro vour
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages. A and B. as shown
in Figure 15. Segment A is the voltage drop across the ESR
of C2 at the instant it goes from being charged by C 1 (current
flowing into C2 ) to being discharged through the load
(current flowing out of C2). The magnitude of this current
change is 2 x lOUT. hence the total drop is 2 x lOUT x
ESR C2 V. Segment B is the voltage change across C2 during
time t2 • the half of the cycle when C2 supplies current the
load. The drop at B is lOUT x t?!C2 V. The peak-to-peak ripple
voltage is the sum of these voltage drops:
(
14B.
14A.
FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT
EQUIVALENT
The output characteristics of the circuit in Figure 14 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (Ao) is a function of
the ON resistance of the intemal MaS switches (shown in
Figure 13). the switching frequency. the value of C 1 and C2 •
and the ESR (equivalent series resistance) of C1 and C2 . A
good first order approximation for Ao is:
Ro
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5. a high value could
potentially swamp out a low 1/fPUMP x C t ) term. rendering an
increase in switching frequency or filter capacitance ineffective. Typical electrolytiC capaCitors may have ESRs as high
as 10Q.
1
2 xfpuMpx C2
+2ESRC2 XloUT
)
Again. a low ESR capacitor will result in a higher· performance output.
Paralleling Devices
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
capacitor. C2 • serves all devices while each device requires
its own pump capacitor. C 1• The resultant output resistance
would be approximately:
RouT (of ICL7660S)
RoUT = -.,--'""'7'"-"--;--;--"",
n (number of devices)
=2(RSWt + RSW3 + ESRet) + 2(RsW2 + Rsw4 + ESRCt ) +
Cascading Devices
(fpUMP =
I
The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However.
due to the finite efficiency of each device. the practical limit
is 10 devices for light loads. The output voltage is defined
by:
~. Rswx = MOSFET switch resistance)
2
Combining the four Rswx terms as Rsw. we see that:
Ro =2 x Rsw +
1
fpuMPxC t
+ 4 X ESRet + ESAc20
VOUT
Rsw. the total switch reSistance. is a function of supply
voltage and temperature (See the Output Source
Resistance graphs). typically 230 at +250 C and 5V. Careful
selection of C t and C2 will reduce the remaining terms.
minimizing the output impedance. High value capacitors will
reduce the 1/(fpuMP x C t ) component. and low ESR capacitors will lower the ESR term. Increasing the oscillator
frequency will reduce the 1/(fpUMP x C 1) term. but may have
the side effect of a net increase in output impedance when
C t > 10j.1F and is not long enough to fully charge the capacitors every cycle. In a typical application where fose
10kHz and C C t C2 iOj.1F:
= = =
Ro
=2 x 23 +
(5 x 103 x 10 x 10-6) + 4 X ESRet + ESRc2
Ro =46 +20 + 5 x ESRcn
=
=-n(VIN).
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT
values.
Changing the ICL7660S Oscillator Frequency
It may be desirable in some applications. due to noise or
other considerations. to alter the oscillator frequency. This
can be achieved simply by one of several methods
described below.
By connecting the Boost Pin (Pin 1) to V+. the oscillator
charge and discharge current is increased and. hence. the
oscillator frequency is increased by approximately 31/ 2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller
7-124
ICL7660S
f
v
t
-(V+)
FIGURE 15. OUTPUT RIPPLE
V+
-------------------t-~....,
ICL7660S
"N"
FIGURE 16. PARALLELING DEVICES
10f1f
VOUT(NOTE)
NOTE:
Your = -nV for1.5V S V+ S 12V
FIGURE 17. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
7-125
ICL7660S
capacitors, e.g. 0.11lF, can be used in conjunction with the
Boost Pin in order to achieve similar output currents
compared to the device free running with C 1 C2 10llF or
1001lF. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
= =
Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latch up, a 1k.O resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10kO pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be 1/2 of the clock frequency. Output transitions occur on
the positive going edge of the clock.
v+
ply voltage (V+) is applied through diode O2 to capacitor C2 .
The voltage thus created on C2 becomes (2V+) - (2VF) or
twice the supply voltage minus the combined forward voltage drops of diodes 0 1 and O2 ,
The source impedance of the output (VOUT) will depend on
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 600.
VOUT-
......W-_-+
(2V+)' (2VF)
v+
NOTE: D1 and D2 can be any suitable diode
FIGURE 20. POSITIVE VOLTAGE DOUBLER
CMOS
GATE
Combined Negative Voltage Conversion and
Positive Supply Doubling
FIGURE 18. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C 1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C 1 and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C 1 and C2 (from 10llF
to 100IlF).
Figure 21 combines the functions shown in Figure 14 and
Figure 20 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from an
existing +5V supply. In this instance capacitors C1 and Ca
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
V+
V+
~
L-------ll-+-=------+-I~_~
VOUT = (2V+)'
(VFOd • (VF02I
FIGURE 21. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
FIGURE 19. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
Voltage Splitting
The ICL7660S may be employed to achieve positive voltage
doubiing using ine circuii snown in Figure 20. in inis appiication, the pump inverter switches of the ICL7660S are used to
charge C 1 to a voltage level of V+ -VF (where V+ is the supply voltage and V F is the forward voltage on C 1 plus the sup-
The bidirectional characteristics can also be used to split a
high supp!y in half, as shC\·':1 in Figure 22. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
7-126
ICL7660S
can be drawn from the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5,
and -7.5 to a nominal-15V, although with rather high series
output resistance (-2500).
increase in pump and storage capacitors is desirable, and
the values shown provides an output impedance of less than
50 to a load of 1OrnA.
+8V
SOk
r-~~------t-------------------~-oV+
56k
50k
100k
ICL8068
L-~------~----------------~~V_
FIGURE 22. SPLITTING A SUPPLY IN HALF
Regulated Negative Voltage Supply
In Some cases, the output impedance of the ICL7660S can
be a problem, particularly if the load current varies substantially. The circuit of Figure 23 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7660S's output does not respond instantaneously to
change in input, but only after the switching delay. The circuit
shown supplies enough delay to accommodate the
ICL7660S, while maintaining adequate feedback. An
FIGURE 23. REGULATING THE OUTPUT VOLTAGE
Other Applications
Further information on the operation and use of the
ICL7660S may be found in AN051 ·Principles and Applications of the ICL7660 CMOS Voltage Converter".
+5V LOGIC SUPPLY
TILI~:~~ >---------------~~
16
RS232
DATA
+5V
OUTPUT
-SV
FIGURE 24. RS232 LEVELS FROM A SINGLE 5V SUPPLY
7-127
r-1
n
I L..J L
ICL7662
CMOS Voltage Converter
April 1994
Features
Description
No External Diode Needed Over Entire Temperature
Range
• Pin Compatible With ICL7660
• Simple Conversion of +15V Supply to -15V Supply
• Simple Voltage Multiplication (YOUT = (-)nV,N)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 96% Typical Power Efficiency
• Wide Operating Voltage Range 4.5V to 2O.0V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
Applications
• On Board Negative Supply for Dynamic RAMs
• Localized ILProcessor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
• Up to -20V for Op Amps
The Harris ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance advantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative
for an input range of +4.5V to +20.0V, resulting in complementary output voltages of -4.5V to -20V. Only 2 noncritical
external capacitors are needed for the charge pump and
charge reservoir functions. The ICL7662 can also function
as a voltage doubler, and will generate output voltages up to
+38.6V with a +20V input.
Contained on chip are a series DC power supply regulator,
RC oscillator, voltage level translator, four output power MOS
switches. A unique logic element senses the most negative
voltage in the device and ensures that the output N-Channel
switch source-substrate junctions are not forward biased.
This assures latch up free operation.
The oscillator, when unloaded, oscillates at a nominal frequencyof 10kHz for an input supply voltage of 15.0V. This
frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10V to +20V), the LV pin
is left floating to prevent device latchup.
Pinouts
ICL7662 (PDIP)
TOP VIEW
ICL7662CBD AND IBD (SOIC)
TOP VIEW
~ST08 ~
CAP+
2
GND3
CAP-
4
7
ICL7662 (CAN)
TOP VIEW
V+
osc
6LV
5 VOUT
ICL7662CBD-O (SOIC)
TOP VIEW
NC
GNDU!NC
4
NC 6
CAP- 7
9 Ne
8 VOUT
CAUTION: These devices are sensitive to electrostatic discharge. User. should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-128
File Number
3181.2
ICL7662
Ordering Information
TEMPERATURE
RANGE
PART NUMBER
ICL7662CTV
OOC to +70"C
PACKAGE
8 Pin Metal Can
ICL7662CPA
8 Lead Plastic DI P
ICL7662CBD·O
14 Lead SOIC (N)
ICL7662CBD
14 Lead SOIC (N)
ICL7662ITV
8 Pin Metal Can
·40"C to +85°C
ICL7662IPA
8 Lead Plastic DIP
ICL7662IBD
14 Lead SOIC (N)
ICL7662MTV (Note 1)
·550 C to +125OC
8 Pin Metal Can
NOTE:
1. Add 1883 to part number if 1883B processing Is required.
Functional Block Diagram
V+
t/)
CAP+
RC
OSCILLATOR
VOLTAGE
LEVEL
TRANSLATOR
+2
CAP·
Cis!!!
0:-'
08:
S~
~o:
CJW
W:J:
0:0
Q.
VOUT
LV
LOGIC
NETWORK
VOLTAGE
REGULATOR
7·129
Specifications ICL7662
Absolute Maximum Ratings
Thermal Information
Supply Voltage. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • 22V
Oscillator Input Voltage ••••••.•• -0.3V to (V+ +0.3V) for V+ < 10V
...•.•.•••••..••..•..••• (V+-l0V)to(V++0.3V)forV+> 10V
(Note 1)
Currentlnto LV (Note 1) •••••..••••••••••••. 20j1A for V+ > 10V
Output Short Duration. . • • • . • • • • • • • • • • • . • • . • • • • • • Continuous
Thermal Resistance
9JA
9JC
Plastic DIP Package. • • • • • • • • • . . • • • • 150"C1W
Plastic SOIC Package. • • • • • • • • . • • . • • 1200 CIW
Metal Can. • • ••• • • • . • • • • • •• • • • . •• • 156"C1W SSOCIW
Lead Temperature (Soldering, lOS) .••••••••••.••••••••• 3000C
(SOIC - Lead lips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause p9rmanent damage to the device. This is a stress only raUng and operation
of the device at thess or any other conditions above those indicated in the operaUonal sections of this specifica50n is not implied.
Electrical Specifications
PARAMETER
v+ = 15V, TA = +25°C, c osc = 0, Unless Otherwise Specified. Refer to Figure 14.
SYMBOL
TEST CONDITIONS
MIN
TVP
MAX
UNITS
-
II
V
20
V
Supply Voltage Range - Lo
V+L
RL = 10kn, LV = GND
Min
I,)
2001
11
510
w
II
8
~ 7
6
5
4
3
2
0
80
~
FIGURE 11. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
/
J
,
o
1!!O
~
/
~
~
~
,.. t--
/
IE
II:
II:
120
LV=GND
iii
.:l:
160i
w
40
30 40 so 60 70 90
LOAD CURRENT IL (rnA)
>"
1+
RL- OO
z
60
>
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT
100
IS
g
",.
4
100
~~
II.
,.". "".
00
V+ .. 5V
T",,+2SOC
Ii:
V
80
FIGURE 8. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT
V+.5V
T,,_+250C
LV_GND
~
~
,...
+125
FIGURE 7. UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE
2
-V+_1SV
-T,,_+250C
-LV_OPEN
..
~ ..
'\.
OK
0
(Continued)
2
4
/
/
LV. OPEN
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
FIGURE 12. FREQUENCY OF OSCILLATION AS A
FUNCTION OF SUPPLY VOLTAGE
7·132
ICL7662
Performance Curves
(See Figure 14, Test Circuit)
(Continued)
ISO
140
130
120
110
.± 100
IZ
110
w
II:
80
II:
::>
()
70
~
60
Do
Do
50
::>
III
40
30
20
10
~
NOTE 4. These curves Include In the supply current that current fed
direcUy into the load RL from the V+ (See Figure 14). Thus, approximately half the supply current goes direcUy to the positive side of the
load, and the other half, through the ICL7662, to the negative side of
the load. Ideally, VOUT=2VIN,ls=2IL, so VIN X Is= VOUTx 'L.
j
L-~~~~~~~~
10
100
__~~~
lK
10K
OSCILLATOR FREQUENCY (Hz)
FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
Circuit Description
The ICL7662 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive 10J.t.F polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter. Capacitor C l
is charged to a voltage, V+, for the half cycle when switches
SI and S3 are closed. (Note: Switches S2 and S4 are open
during this half cycle.) During the second half cycle of
operation, switches ~ and S4 are closed, with SI and S3
open, thereby shifting capacitor C l negatively by V+ volts.
Charge is then transferred from C l to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and no
load on C2. The ICL7662 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7662, the 4 switches of Figure 15 are MOS power
switches; SI is a P-Channel device and ~, S3 and S4 are NChannel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 and S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON"
resistances. in addition, at circuit startup, and under output
short circuit conditions (VQUT V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
IT ~
C'+_~~~
-
The voltage regulator portion of the ICL7662 is an integral
part of the anti-latch up circuitry, however its inherent voltage
drop can degracle operation at low voltages. Therefore, to
improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 10V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.
IsV+
_ _ _~-o(+5V)
~~""'l
iCL7662
~
4
...Li
'"=":
~
cosc.l.
(NOTE),J.
t/)
c;,!!!
a:..J
NOTE: For large value of
Cose (> 1000pF)
the values of C, and C. should be
increased to 100!1F.
08::
j~
FIGURE 14. ICL7662 TEST CIRCUIT
::;)a:
ClW
W~
a:O
Q.
S,
8
VINO
i
3
!
:
:
:
~
I
r
So
2
0/0
=
This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (VQUT) together with the
level translators, and switches the substrates of S3 and S4 to
the correct level to maintain necessary reverse bias.
~1---
c,
3
~
JWLhJ"
7-133
FIGURE 15. IDEALIZED NEGATIVE CONVERTER
ICL7662
Theoretical Power Efficiency Considerations
In theory a voltage multiplier can approach 100% effICiency if
certain conditions are met:
A The drive circuitry consumes minimal power
B The output switches have extremely low ON resistance
and virtualiy no offset.
The output characteristics of the circuit in Figure 16A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 16B. The voltage source has
a value of -(V+). The output impedance (Ao) is a function of
the ON resistance of the internal MOS switches (shown in
Rgure 2). the switching frequency. the value of C, and C 2•
and the ESR (equivalent series resistance) of C, and C2 • A
good first order approximation for Ro is:
C The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
Ro .. 2(RSWI + RSW3 + ESRC, )
1
-;----:::-- + ESRC2
fpUMP xC,
The ICL7662 approaches these conditions for negative voltage multiplication if large values of C, and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
(fpUMP
=
fose •
2
Rswx
=MOSFET switch resistance)
Combining the four Rswx terms as Rsw. we see that
E =1/2C, (V, 2 - V22)
where V, and V2 are the voltages on C, during the pump
and transfer cycles. If the impedances of C, and C2 are relatively high at the pump frequency (refer to Figure 15) compared to the value of RL. there will be a substantial
difference in the voltages V, and V 2 • Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple. but also to employ a correspondingly large
value for C, in order to achieve maximum efficiency of operation.
Do's and Don'ta
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply voltages greater than 10V.
3. When using polarized capacitors. the + terminal of C,
must be connected to pin 2 of the ICL7662 and the + terminal of C2 must be connected to GROUND.
4. If the voltage supply driving the 7662 has a large source
impedance (250 - 300). then a 2.211F capacitor from pin
8 to ground may be required to limit rate of rise of input
voltage to less than 2VIllS.
5. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up wili occur
under these conditions.
Ro .. 2 x Rsw +
1
+ 4 X ESRC, + ESRC20
fpUMPXC,
Rsw. the total switch resistance. is a function of supply voltage and temperature (See the Output Source Resistance
graphs). typicaliy 240 at +250 C and 15V. and 530 at +250 C
and 5V. Careful selection of C, and C 2 will reduce the
remaining terms. minimizing the output impedance. High
value capacitors will reduce the 1/(fpUMP x C , ) component.
and low FSR capacitors will lower the ESR term. Increasing
the oscillator frequency will reduce the 1/(fpUMP x C, ) term.
but may have the side effect of a net increase in output
impedance when C, > 10!1F and there is no longer enough
time to fuliy charge the capacitors every cycle. In a typical
application where fose = 10kHz and C C , C2 = 1OI1F:
= =
Ao .. 2x23+
1
(5x103 x10x10.6) +4ESRC , +ESRC2
Ao .. 46 + 20 + 5 x ESReO
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5. a high value could
potentialiy swamp out a low 1/(fpUMP x C, ) term. rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Y+
A 1N914 or similar diode placed in paraliel with C2 will prevent the device from latching up under these conditions.
(Anode pin 5. Cathode pin 3).
Typical AppUcaUons
RO
Your
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Rgure
16 shows typical connections to provide a negative supply
where a positive supply of +4.5V to 20.0V is availab!e, Keep
16A.
168.
FlGYRE 11;' S!MPLE NEGATIVE CONVERTER AND ITS OUTPUT
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 10V.
7-134
eQUIVALENT
ICL7662
Output Ripple
ESA also affects the ripple voltage seen at the output. The
total ripple is determined by 2V. A and B. as shown in Figure
17. Segment A Is the voltage drop across the ESA of C 2 at
the instant it goes from being charged by C 1 (current flowing
into C2) to being discharged through the load (current flowing out of C2 ). The magnitude of this current change is 2 X
lOUT. hence the total drop is 2 x lOUT X ESAC2V. Segment B
is the voltage change across C2 during time t2' the half of
the cycle when C2 supplies current the load. The drop at B is
lOUT X t2/C2V. The peak-to-peak ripple voltage is the sum of
these voltage drops:
VRIPPLE '"
(
2
1
xfpuMP X C2
+2 ESRC2 x lOUT
ervoir capacitor. C2• serves all devices while each device
requires its own pump capacitor. C 1• The resultant output
resistance would be approximately:
RouT (of ICL7662)
RouT = -:-""7"-'-'--'---'n (number of devices)
Cascading Devices
The ICL7662 may be cascaded as shown in Figure 19 to
produce larger negative multiplication of the initial supply
voltage. However. due to the finite efficiency of each device.
the practical limit is 10 devices for light loads. The output
voltage is defined by:
)
VOUT = -n(VIN).
Again. a low ESA capacitor will result in a higher performance output.
Paralleling Devices
where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately
the weighted sum of the individuallCL7662 Rour values.
Any number of ICL7662 voltage converters may be
paralleled (Figure 18) to reduce output resistance. The res-
FIGURE 17. OUTPUT RIPPLE
FIGURE 18. PARALLELING DEVICES
FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
7-135
ICL7662
Changing the ICL7662 Oscillator Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 20. In order to prevent possible
device latchup, a 1kW resistor must be used in series with
the clock output. In the situation where the designer has
generated the external clock frequency using TTL logic, the
addition of a 10kW pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking., as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.
the supply voltage and V F is the forward voltage drop of
diode 0,). On the transfer cycle, the voltage on C, plus the
supply voltage (V+) is applied through diode C2 to capacitor
C 2• The voltage thus created on C2 becomes (2V+) (2V F) or
twice the supply voltage minus the combined forward voltage
drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend on
the output current, but for V+ 15V and an output current of
10mA it will be approximately 70Q.
=
It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, COSC, as shown in
Figure 21. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C,) and reservoir (C2 ) capacitors; this is overcome by
increasing the values of C, and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capaCitor between pin 7 (OSC) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and C2 (from 10mF to
100mF).
VOUT(2V+) - (2VF)
NOTE: 0, and O2 can be any suitable diode.
FIGURE 22. POSITIVE VOLTAGE DOUBLER
v+
VOUT'"
- (nVIN - VFDxl
CMOS
GATE
VOUT" (2V+)·
-
+
(VFDd - (VF02l
FIGURE 20. EXTERNAL CLOCKING
FIGURE 23. COMBINED NEGATIVE CONVERTER
AND POSITIVE DOUBLER
v·
Combined Negative Voltage Conversion and Positive
Supply Doubling
Case
c,
I--_--OVOUT
FIGURE 21. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C 1 to a voltage laval of V+ =VF (~lIhsrs V+ is
Figure 23 combines the functions shown in Figure 16 and
Figure 22 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from an
existing +5V supply. In this instance capacitors C, and C 3
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C 4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
7-136
ICL7662
Voltage Splitting
The bidirectional characteristics can also be used to split a
higher supply In half. as shown in Figure 24. The combined
load will be evenly shared between the two sides and. a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel. the output impedance is
much lower than in the standard circuits. and higher currents
can be drawn from the device. By using this circuit. and then
the circuit of Figure 19. +30V can be converted (via +15V.
and -15V) to a nominal -30V. although with rather high series
output resistance (-2500).
~~------~~-----------------.--v+
v0UT-v+-v2
SO!lF
RU
L-~
______
~
________________
~~v_
FIGURE 24. SPLITTING A SUPPLY IN HALF
Regulated Negative Voltage Supply
In some cases. the output impedance of the ICL7662 can be
a problem. particularly if the load current varies substantially.
The circuit of Figure 25 can be used to overcome this by
contrOlling the input voHage. via an ICL7611 low-power
CMOS op amp. in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable. since
the ICL7662s output does not respond instantaneously to a
change in input. but only after the switching delay. The circuit
shown supplies enough delay to accommodate the ICL7662.
while maintaining adequate feedback. An increase in pump
and storage capacitors is desirable. and the values shown
provides an output impedance of less than 50 to a load of
10mA.
+8V
SOk
56k
$Ok
100k
ICL80511
100""
Other Applications
Further information on the operation and use of the ICL7662
may be found in A051 'Principles and Applications of the
ICL7660 CMOS Voltage Converter".
2$Ok
VOLTAGE
ADJUST
FIGURE 25. REGULATING THE OUTPUT VOLTAGE
til
(is!:!:!
a:.J
08:
~;:)
.JtII
;:)a:
ow
w~
a:O
a..
7-137
ICL7663S
CMOS Programmable Micropower
Positive Voltage Regulator
April 1994
Features
Description
• Guaranteed 10J.tA Maximum Quiescent Current Over
All Temperature Ranges
The ICL7663S Super Programmable Micropower Voltage
Regulator is a low power. high efficiency positive voltage
regulator which accepts 1.6V to 16V inputs and provides
adjustable outputs from 1.3V to 16V at currents up to 4OmA.
• Wider Operating Voltage Range - 1.6V to 16V
• Guaranteed Una and Load Regulation Over Entlra
Operating Temperature Range Optional
• 1% Output Voltage Accuracy (ICL7663SA)
• Output Voltage Programmable from 1.3V to 16V
• Improved Temperature Coafflclent of Output Voltage
• 40mA Minimum Output Current with Current Umltlng
• Output Voltages with Programmable Negative Temperature Coafflclents
• Output Shutdown via Current-Umlt Sensing or External Logic Level
• Low Input-ta-Output Voltage Differential
• Improved Direct Replacement for Industry Standard
ICL7663B and Other Second-Source Products
Applications
• Low-Power Portable Instrumentation
• Pagers
It is a direct replacement for the industry standard ICL7663B
offering wlcklr operating voltage and temperature ranges,
Improved output accuracy (ICL7663SA), better temperature
coefficient, guaranteed maximum supply current, and
guaranteed line and load regulation. All improvements are
highlighted in the electrical characteristics section. Critical
parametera Bra guaranteed over the entlra commercial
and Industrial temperature ranges. The ICL7663S1SA
programmable output voltage is set by two external
resistors. The 1% reference accuracy of the ICL7663SA
eliminates the need for trimming the output voltage in most
applications.
The ICL7663S is well suited for battery powered supplies,
featuring 411ft. quiescent current, low VIN to Vour differential,
output current sensing and logic input level shutdown
control. In addition, the ICL7663S has a negative
temperature coefficient output suitable for generating a
temperature compensated display drive voltage for LCD
displays.
The ICL7663S is available in either an 8 lead Plastic DIP,
Ceramic DIP, or SOIC package.
• Handheld Instruments
• LCD Display Modules
• Remote Data Loggera
• Battery-Powered Systems
Pinout
O'
Ordering Information
ICL7663S (PDIP, CERDIP, SOIC)
TOP VIEW
SENSE
V0UT2
VOUT1
GND
PART NUMBER
ICL7663SCBA
TEMPERATURE
RANGE
O"C to +7O"C
PACKAGE
8 Lead SOIC (N)
ICL7663SCPA
8 Lead Plastic DIP
VTC
ICL7663SCJA
8 Lead CerDIP
•
VSET
ICL7663SACBA
8 Lead SOIC (N)
5
SHDN
ICL7663SACPA
8 Lead Plastic DIP
2
7
3
..
VIN>
ICL7663SACJA
ICL7663SIBA
8 Lead CerDIP
·25"0 to +850 C
8 Lead SOIC (N)
ICL7663SIPA
8 Lead Plastic 01 P
ICL7663SIJA
8 Lead CerDIP
ICL7663SAIBA
8 Lead SOIC (N)
ICL7663SAIPA
8 Lead Plastic DIP
ICL7663SAIJA
8 Lead CerDIP
CAUTION: These devices ara aansitiva to atactrastatic discharge. Uaars should lollow proper I.C. Handling Procedures.
Copyright @ Harris Corporation t 994
7-138
File Number
3180.2
Specifications ICL7663S
Absolute Maximum Ratings
Thermal Information
Input Supply Voltage.•..•••.•.••••..••••••••••••••••• +18V
Any Input or Output Voltage (Note 1)
Terminals 1, 2, 3, 5, 6, 7 •.•••••••••••• V1N+O.3V to GND-O.3V
Output Source Current
Terminal 2 .•••..•••••..••••••••••••.••.•••.•..•.. 50mA
Terminal 3 .•.......•...•••.••••••••••..•••••..••• 25mA
Output Sinking Current
Terminal 7 ......•••....•••.••••••••••..•••....•. ·10mA
Thermal Resistance
Ceramic DIP Package •••••••.•••••••
Plastic DIP Package ••••••••••••••••
Plastic SOIC Package •••••••••••..•.
Maximum Junction Temperature
Plastic DIP Package •••.•••.••••.•••••.•...•.... +15O"C
CerOlP Package •••.•••..•...••••••.•••.•.•••.• +175°C
Storage Temperature Range ••...•.•••.•.••••. ·65OC to +15O"C
Lead Temperature (Soldering 1Os) •••••••.••••.•••.... +3OQOC
(SOIC • Lead Tlps Only)
CAUTION: SIrBss.... abo... those listed In "Absolute Maximum Ratings" may cause p8mllJnent damage to the device. This is a stress only rating and operation
of /he devfc8 at l1186e or any o/hlll' conditions abo... thosa Indicated in the operational sections of /his specification Is not Implied.
Operating Conditions
Operating Temperature Range
ICL7663SC ••...••••..•••••.•••.••••••••••• O"C to +70"C
ICL7663SI. ••.•••••..•••••.....••..•.•••• ·250 C to +85°C
Electrical Specifications SpaclficaHons Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Spacifled.
V+1N = 9V, VOUT = 5V, TA = +25°C, Unless Otherwise Spaclfied. Notes 4,5. See Test Circuit, Figure 7
o
Us!!!
a:....I
olt
!c;:)
0
....1
;:)a:
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w:=
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Q,
Load Regulation
7·139
Specifications ICL7663S
Electrical Specifications Specifications Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Specified.
=
V+1N 9V, Your
(Continued)
=5V, TA =+25°C, Unless Otherwise Specified. Notes 4, 5. See Test Circuit, Figure 7
Minimum Load Current
NOTES:
1. Connecting any terminal to voltages greater than (V+IN + O.3V) or less than (GNO - O.3V) may cause destructive device latchoolJp. It Is
recommended that no InpulS from sources operating on external power supplies be applied prior to ICL7663S poweroolJp.
2. This parameter refers to the saturation resistance of the MaS pass transistor. The minimum Input-output voltage differential at low current
(under 5mA), can be determined by multiplying the load current (including set resistor current, but not quiescent current) by this
resistance.
3. This output has a positive temperature coefficient. Using It In combination with the Inverting Input of the regulator at VSET, a negative
coeffICient results In the output vottage. See Figure 9 for details. Pin will not source current.
4. All pins are designed to withstand electrostatic discharge (ESO) levels In excess of 2000V.
5. All significant ImprovemenlS over the Industry standard ICL7663 are highlighted.
Functional Diagram
3
8
V+IN o--....---.h ....---
4.875
-
4.870
4.865
-
-
-
;-
;-
100
~
1.4
§
1.2
.
>
z
~
;-
4.860
4.855
U
-
4.HO
I
1.0
V+IN·8V
.,. .,.......-
I
1/
0.4
o
_I
I
0.6
102
~ :;;....-
I
'-' P'"
o
2
4
6
§
>
1.0
f
>
0.8
.
12
14
16
10
....
70
iii'
:l!-
V...... 2V
II:
II:
Ie
v.l.8!7 -
0.4
50
40
.....
30
-
V+IN-15V
VIN-+8.0V
.....,1V1N·2V
60
20
.....
G.2
00
5
10
15
20
25
30
35
40
45
50
100
101
FREQUENCY (Hz)
IoUT2(mA)
FIGURE 3. VoUT2 INPUT-OUTPUT DIFFERENTIAL VB OUTPUT
CURRENT
5.0
I
4.5
.9
T".-~C
~
5.00
3.0
r,,-
2.5
---
~
I
4.75
-
4.50
4.25
~
T".-700C
.9
2.0
3.50
1.0
3.00
0.5
2.75
0
2.50
4
6
8
10
V+IN (V)
12
14
16
I I
I"""'-- b... V+~+15~
3.75 ~
3.25
2
7-141
r-.....
.........
f'"".
i"'-
t"--..
. . . r.......
V+.+8V
l"- f....
......... IJ.
V+_.:;,.............
i
-20
FIGURE 5. QUIESCENT CURRENT AS A FUNCTION OF INPUT
VOLTAGE
lk
I
4.00 ~
1.5
0
102
FIGURE 4. INPUT POWER SUPPLY REJECTION RATIO
I
T".-2OoC
4.0
~
20
80
T"~~OC
0.6
3.5
la
100
1.4
1.2
10
FIGURE 2. V0UT1INPUT-OUTPUT DIFFERENTIAL va OUTPUT
CURRENT
2.0
~
-
10UT1 (mA)
FIGURE 1. VOUT2 OUTPUT VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT
1.6
."
,. ,.,..... . /
V+IN·15V -
8
loUT (mA)
1.8
- -
V+JN·2V
0.8
0.2
1_
T".+~C
1.1
"
-
4.8115
~
2.0
o
1
20
40
TEMPERATURE ("C)
--r-
t'---
60
80
FIGURE 6. QUIESCENT CURRENT AS A FUNCTION OF TEMPERATURE
ICL7663S
Detailed Description
The ICL7663S Is a CMOS integrated circuit incorporating all
the functions of a voltage regulator plus protection circuitry
on a single monolithic chip. Aeferring to the Functional Diagram, the main blocks are a bandgap-type voltage reference,
an error amplifier, and an output driver with both PMOS and
NPN pass transistors.
The bandgap output voltage, trimmed to 1.29V ± 15mV for
the ICL7663SA, and the input voltage at the VSET terminal
are compared in amplifier A. Error amplifier A drives a
P-channel pass transistor which is sufficient for low (under
about 5mA) currents. The high current output is passed by
an NPN bipolar transistor connected as a follower. This
configuration gives more gain and lower output impedance.
Logic-controlled shutdown is implemented via aN-channel
MOS transistor. Current-sensing is achieved with
comparator C, which functions with the VOUT2 terminal. The
ICL7663S has an output (VTC> from a buffer amplifier (6),
which can be used in combination with amplifier A to
generate programmable-temperature-coefficient
output
voltages,
The amplifier, reference and comparator circuitry all operate
at bias levels well below 1jIA to achieve extremely low
quiescent current. This does limit the dynamic response of
the circuits, however, and transients are best dealt with
outside the regulator loop.
Basic Operation
4. IQ quiescent currents measured at GND pin by meter M.
5. S3 when ON, permits normal operation, when OFF, shuts
down both VOUT1 and VOUT2'
FIGURE 7. ICL7663S TEST CIRCUIT
Output Voltages - The resistor divider AiAl is used to
scale the reference voltage, VSET' to the desired output using
the formula VOUT (1 + AiAl) VSET' Suitable arrangements
of these resistors, using a potentiometer, enables exact
values for VOUT to be obtained. In most applications the
potentiometer may be eliminated by using the ICL7663SA.
The ICL7663SA has VSET voltage guaranteed to be 1.29V
±15mV and when used with ±1% tolerance resistors for Al
and A2 the initial output voltage will be within ±2.7% of ideal.
=
The ICL7663S is designed to regulate battery voltages in the
5V to 15V region at maximum load currents of about 5mA to
3OmA. Although intended as low power devices, power dissipation limits must be observed. For example, the power dissipation in the case of a 10V supply regulated down to 2V
with a load current of 30mA clearly exceeds the power dissipation rating of the Mini-DIP:
(10 - 2) (30) (10-3)
NOTES;
1. Sl when closed disables output current limiting.
2. Close S2 for VOUT1, open S2 for VOUT2 '
3.
R2+Rl
Vour= ~ VSET'
=240mW
The circuit of Figure 8 illustrates proper use of the device.
CMOS devices generally require two precautions: every
input pin must go somewhere, and maximum values of
applied voltages and current limits must be rigorously
observed. Neglecting these precautions may lead to, at the
least, incorrect or nonoperation, and at worst, destructive
device failure. To avoid the problem of latch up, do not apply
inputs to any pins before supply voltage is applied.
Input Voltages - The ICL7663S accepts working inputs of
1.5V to 16V. When power is applied, the rate-of-rise of the
input may be hundreds of volts per microsecond. This is
potentially harmful to the regulators, where intemal operating currents are in the nanoampere range. The 0.047IlF
capaCitor on the device side of the switch will limit inputs to a
safe level around 2V/!lS. Use of this capacitor is suggested in
aii applications. in severe rate-oi-rise cases, Ii may be advisable to use an AC network on the SHutDowN pin to delay
output tum-on. Battery charging surges, transients, and
assorted noise signals should be kept from the regulators by
AC filtering, zener protection, or even fusing.
The low leakage current of the VSET terminal allows Al and
A2 to be tens of megohms for minimum additional quiescent
drain current. However, some load current is required for
proper operation, so for extremely low-drain applications it is
necessary to draw at least 1jIA. This can include the current
for A2 and AI'
Output voltages up to nearly the Y,N supply may be obtained
at low load currents, while the low limit is the reference
voltage. The minimum input-output differential in each
regulator is obtained using the Voun, terminal. The inputoutput differential increases to 1.5V when using VOUT2 '
Output Currents - Low output currents of less than 5mA are
obtained with the least input-output differential from the
V0UT1 terminal (connect VOUT2 to Voun). Where higher currents are needed, use VOUT2 (Voun, should be left open in
this case).
High output currents can be obtained only as far as package
dissipation allows. It is strongly recqmmended that output
current-limit sensing be used in such cases.
Current-Umlt Sensing - The on-chip comparator (C in the
Functional Diagram) permits shutdown of the regulator
7-142
ICL7663S
output in the event of excessive current drain. As Figure 8
shows, a current-limiting resistor, RCl' is placed in series
with VOUT2 and the SENSE terminal is connected to the load
side of RCl ' When the current through RCl is high enough to
produce a voltage drop equal to VCl (0.5V) the voltage
feedback is by-passed and the regulator output will be
limited to this current. Therefore, when the maximum load
current (lLOAD) is determined, simply divide Vcl by ILOAD to
obtain the value for RCl'
v+1N SENSE
200
VOUT2
-
In addition, where such a capacitor is used, a current-limiting
resistor is also suggested (see ·Current-Limit Sensing").
Producing Output Voltages with Negative Temperature
Coefficients· The ICL7663S has an additional output which
is O.9V relative to GND and has a tempco of +2.5mVI"C. By
applying this voltage to the inverting input of amplifier A (i.e.,
the VSET pin), output voltages having negative TC may be
produced. The TC of the output voltage is controlled by the
RiR3 ratio (see Figure 9 and its design equations).
1
RCL
VOUT1
VIN
604kn
VTC i - -
0.047""
VSET
GND SHDN
R2
210kn
>--_-oVOUT
10"" VOUT
CL +5 V
.J:
+
Rt
VTC
1 1
-L
EO. l:VOUT = VSET
R2+Rl
Vour - - VSET = 5V
'" Rl
EO. 2:
VCl
ICl = - - = 25mA
RCl
TCVour=
Where: VSET = 1.3V
VTC= 0.9V
TCVTC = +2.5mVI"C
FIGURE 9. GENERATING NEGATIVE TEMPERATURE
COEFFICIENTS
FIGURE 8. POSITIVE REGULATOR WITH CURRENT LIMIT
Logic-Controllable Shutdown • When equipment is not
needed continuously (e.g., in remote data-acquisition
systems), it is desirable to eliminate its drain on the system
until it is required. This usually means switches, with their
unreliable contacts. Instead, the ICL7663S can be shut
down by a logic Signal, leaving only 10 (under 41lA) as a
drain on the power source. Since this pin must not be left
open, it should be tied to ground if not needed. A voltage of
less than 0.3V for the ICL7663S will keep the regulator ON,
and a voltage level of more than 1.4V but less than V+ IN will
turn the outputs OFF. If there is a possibility that the control
signal could exceed the regulator input (V+IN ) the current
from this signal should be limited to 1001lA maximum by a
high value (1 Mil) series resistor. This situation may occur
when the logic Signal originates from a system powered
separately from that of the regulator.
Additional Circuit Precautions • This regulator has poor
rejection of voltage fluctuations from AC sources above 10Hz
or so. To prevent the output from responding (where this might
be a problem), a reservoir capacitor across the load is advised.
The value of this capacitor is chosen so that the regulated output voltage reaches 90% of its final value in 2Oms. From:
IN
(20 x 10-3)
lOUT
1= C - , C = lOUT
= 0.022 - At
0.9VOUT
VOUT
Applications
(/)
Boosting Output Current with External Transistor
The maximum available output current from the ICL7663S is
40mA. To obtain output currents greater than 4OmA, an external NPN transistor is used connected as shown in Figure 10.
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..J(/)
;:)a:
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W:=
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V+IN VOUTI
EXTERNAL PIN
POWER
TRANSISTOR
voun
0.470
VIN
lC1!tF
SENSE
t
VSET
VOUT
+5V
GND SHDN
FIGURE 10. BOOSTING OUTPUT CURRENT WITH EXTERNAL
TRANSISTOR
7·143
0.
ICL7663S
Generating a Temperature Compensated Display Drive
VoHage
Temperature has an important effect in the variation of
threshold voltage in multiplexed LCD displays. As
temperature rises, the threshold voltage goes down. For
applications where the display temperature varies widely, a
+6V
temperature compensated display voltage, VDIS~ can be
generated using the ICL7663S. This is shown in Figure 11
for the ICM7233 triplexed LCD display driver.
I
v+1N
VOUYI
LOGIC
SYSTEM,
PROCESSOR,
ETC.
--
Voun
ICL7663S
J
V+
1.8MIl
VSET
300Kll
ICM7233
VTC
2.7110
GND
GND
~
1
VDISP
L
GND
DATA BUS
·11
FIGURE 11. GENERATING A MULTIPLEXED LCD DISPLAY DRIVE VOLTAGE
7-144
=>
ICL7665S
CMOS Micropower Over/Under
Voltage Detector
April 1994
Features
Description
• Guaranteed 101J.A Max.lmum Quiescent Current Over
Temperature
The ICL7665S Super CMOS Micropower OverlUnder
Voltage Detector contains two low power, individually
programmable Voltage detectors on a single CMOS Chip.
Requiring typically 3j.LA for operation, the device is intended
for battery-operated systems and instruments which require
high or low voltage wamings, settable trip points, or fault
monitoring and correction. The trip points and hysteresis of
the two voltage detectors are individually programmed via
extemal resistors. An internal bandgap-type reference
provides an accurate threshold voltage while operating from
any supply in the 1.6V to 16V range.
• Guaranteed Wider Operating Voltage Range Over
Entire Operating Temperature Range
• 2% Threshold Accuracy (ICL7665SA)
• Dual Comparator with Precision Internal Raferenee
• 100ppmi"C Temperature Coefficient of Threshold
VoHage
• 100% Tested at 2V
• Output Current Sinking Ability •••••••••• Up to 20mA
• Individually Programmable Upper end Lower Trip
VoHages and Hysteresis Levels
Applications
The ICL7665S, Super Programmable Over/Under Voltage
Detector is a direct replacement for the industry standard
ICL7665B offering wider operating voltage and temperature
ranges, Improved threshold accuracy (ICL7665SA), and
temperature coefficient, and guaranteed maximum supply
current. All improvements are highlighted in the electrical
characteristics section. All critical parameters are
guaranteed over the entire commercial and Industrial
temperature ranges.
• Pocket Pagera
• Portable Instrumantatlon
• Charging Systems
• Memory Power Back-Up
• Battery Operated Systems
• Portable Computera
• Level Detectors
Pinout
Ordering Information
ICL7665S (SOIC, PDIP, CerDlP)
TOP VIEW
PART NUMBER
ICL7665SCBA
OUT108V+
HYST1 2
7 OUT2
SET1
3
6 SET2
GND
4
5
HYST2
TEMPERATURE
RANGE
0010 +700C
PACKAGE
8 Lead SOIC (N)
ICL7665SCPA
8 Lead Plastic DIP
ICL7665SCJA
8 Lead CerDIP
ICL7665SACBA
8 Lead SOIC (N)
ICL7665SACPA
8 Lead Plastic DIP
ICL7665SACJA
ICL7665SIBA
8 Lead CarDIP
-40"C 10 +85"C
8 Lead SOIC (N)
ICL7665SIPA
8 Lead Plastic DIP
ICL7665SIJA
8 Lead CarDIP
ICL7665SAIBA
8 Lead SOIC (N)
ICL7665SAIPA
8 Lead Plastic DIP
ICL7665SAIJA
8 Lead CarDIP
CAUTION: These devices are sensitive to electrostatic discharge. Uaers ahould follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994
7-145
File Number
3182.3
Specifications ICL7665S
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Note 2) •••••••••••••••..•••••••• -0.3 to +18V
Output Voltages OUTI and OUT2 ••••••••.•••••.• -o.3V to 18V
(with respect to GND) (Note 2)
Output Voltages HYSTI and HYST2 ••••••••••••• -o.3V to + 18V
(with respect to V+) (Nota 2)
Input Voltages SETI and SET2 .••••. (GND-o.3V) to (V+ V- +O.3V)
(Note 2)
Maximum Sink Output OUTI and OUT2 ••••••.••••••.••• 25mA
Maximum Source Output Current
HYSTt and HYST2 •••••••••••.••••••.••••...••••• -25mA
Thermal Resistance
OJA
OJC
Ceramic DIP Package. • • • • • • • • • • • . • • 115°CM' aooGM'
Plastic DIP Package • • • • • . . • • • • • . • • • I SOOCM'
Plastic SOIC Package. • • • • • • . • • . • • • • 1800CM'
Maximum Junction Temperature (Plastic) •••.•.•...•••. +1500C
Maximum Junction Temperature (CerDI P) +I 75°CStorage Temperature Range ••••.•••••••••••.••••••••.••••• -65°C to +1 WOC
Lead Temperature (Soldering lOs) .••.••••..•••••....• +300oC
(SOIC - Lead lips Only)
CAUTION: Strssses above those Usted in "Absolute Maximum RaYnos" may cause permanent damage to the device. This is 8 stress only rating and cperaYon
of the device at these or any other conditions above those indicated in the operational s8Ctions of this specification Is not implied.
Operating Conditions
Operating Temperature Range
ICL7665SC ••••.••.•••••••••••••••••••••••• OOC to +700C
ICL7665S1. ••...••••••••••.•.••••••••.••••. - 1.3V, OUT1 SWitch ON, HYST1 SWitch ON
VSET1 < 1.3V, OUT1 Switch OFF, HYST1 Switch OFF
VSET2 > 1.3V, OUT2 Switch OFF, HYST2 Switch ON
VSET2 < 1.3V, OUT2 Switch ON, HYST2 Switch OFF
NOTE:
1. See Electrical Specificationsfor exact thresholds.
7·148
----_oGND
....
~~--------
ICL7665S
Typical Performance Curves
u
~Or-----r-----'-----~----~
~
£
1-----1-----+_----+-----.1
1.5
~
~
~
IX
IX
III
!c
III
~ 1.0~-_f--
~
~
1.0
W
:;I
~
~
1.5
a
r----,~+_~"=:oi"":;...._:::.....OC;;'---I
0.5
>
0.5
0
5
10
15
o
20
5
lou-rOUT1 (mAl
FIGURE1. OUT1 SATURATION VOLTAGEASA FUNCTION OF
OUTPUT CURRENT
-16
-20
.
-12
10
15
20
lou-rOUT2 (mAl
FIGURE 2. OUT2 SATURATION VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT
-&.0
004
-4.0
-3.0
-2.0
-1.0
£
£
w
w
c:I
-0.4 ~
-1.0
~
-0.8
~
~.O
I-
5
0
I!:
~
004.0 0~
~>-
~
-2.0 :z:
-5.0 :z:
HYST1 OUTPUT CURRENT (rnA)
HYST2 OUTPUT CURRENT (mAl
FIGURE3. HYST10UTPUTSATURATIONVOLTAGEvsHYST1
OUTPUT CURRENT
H--t
4.0
1 3.5
I-
zw
IX
II:
8
3.0
2.5
~
2.0
~
1.5
II.
II.
III
~
OV VSET1.
V+_16V
~SET2 ~ V+ _
FIGURE4. HYST20UTPUTSATURATIONVOLTAGEvsHYST2
OUTPUT CURRENT
5.0
4.5
f-
t--- t-- ov ~ VSETIo VSET2 ~ v~
V+~8V
1 3.5
!zw
II:
II:
8
V+_2V
~
II.
II.
~
III
1.0
0.5
--±:-
TA--200C
4.0
~ 1/
~ E==: ~
~~
~
3.0
2.5
U
TA-+70"C
1.5
1.0
0.5
o
-25
!c
III
l-
~
4.5
~
~
!c
III
~
5.0
~
IX
~
-1.6
a
>
-~O
IX
-1.2
~
o
0
+20
+40
+60
AMBIENT TEMPERATURE rCI
o
2
..
•
•
10
12
14
16
SUPPLY VOLTAGE (v+l
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF AMBIENT
TEMPERATURE
7-149
FIGURE 6. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
ICL7665S
Detailed Description
As shown in the Functional Diagram, the ICL7665S consists
of two comparators which compare input voltages on the
SEn and SET2 terminals to an intemal 1.3V bandgap
reference. The outputs from the two comparators drive opendrain N-channel transistors for OUT1 and OUT2, and opendrain P-channel transistors for HYST1 and HYST2 outputs.
Each section, the Under Voltage Detector and the Over
Voltage Detector, is independent of the other, although both
use the internal 1.3V reference. The offset voltages of the
two comparators will normally be unequal so VSETI will
generally not quite equal VSET2 '
The input impedance of the SEn and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting up
the hysteresis, and maximizes the output flexibility. The
operating currents of the bandgap reference and the
comparators are around 100nA each.
v+
between the V+ and GND pins of the ICL7665S can be used
to reduce the rate-of-rise of the supply voltage in battery
applications. In line operated systems, the rate-of-rise of the
supply is limited by other considerations, and is normally not
a problem.
If the SET voltages must be applied before the supply
voltage V+, the input current should be limited to less than
0.5mA by appropriate external resistors, usually required for
voltage setting anyway. A similar precaution should be taken
with the outputs if it is likely that they will be driven by other
circuits to levels outside the supplies at any time.
1.6V
INPUT
OUTI
I.OV
ISOID
tOIF
v+
(5V)
GND
IHIF
HYSTI
V+
(5V)
---+or
GND
V+
(5V)
GND
v+
(5V)
GND
HYST2
FIGURE 8. SWITCHING WAVEFORMS
Simple Threshold Detector
Figure 9 shows the simplest connection of the ICL7665S for
threshold detection. From the graph 98, it can be seen that
at low input voltage OUT1 is OFF, or high, while OUT2 is
ON, or low. As the input rises (e.g., at power-on) toward
VNOM (usually the eventual operating voltage), OUT2 goes
high on reaching VTR2 . If the voltage rises above VNOM as
much as VTR1, oun goes low. The equation giving VSETI
and VSET2 are from Figure 9A:
1.6V-::n...
I.OV ••••
FIGURE 7. TEST CIRCUITS
Precautions
Junction isolated CMOS devices like the ICL7665S have an
inherent SCR or 4-layer PNPN structure distributed throughout the die. Under certain circumstances, this can be
triggered into a potentially destructive high current mode.
This latchup can be triggered by forward-biasing an input or
output with respect to the power supply, or by applying
excess.ive supply voltages. In very low current analog circuits, such as the ICL7665S, this SCR can also be triggered
by applying the input power supply extremely rapidly
("instantaneously"), e.g. through a low impedance battery
and an ONIOFF switch with short lead lengths. The rate-ofrise of the supply voltage can exceed 100VlIlS in such a circuit. A low impedance capacitor (e.g., 0.051lF disc ceramic)
V
-V
SEll -
R11
IN (Ru
'V
-V
+ ~1) , SET2 -
R12
IN (R 12 + ~)
Since the voltage to trip each comparator is nominally 1.3V,
the value VIN for each trip point can be found from
for detector 1
and
7·150
v TR2
=vsm
(R 12 + R2:2l
R12
=1.3 (R12 + ~)
R12
for detector 2
ICL7665S
Either detector may be used alone. as well as both together.
in any of the circuits shown here.
VIN
1
I
RP2
OUTI
~1
OU12
SETI
Ru
SE12
1
RI1
When VIN is very close to one of the trip voltage. normal
variations and noise may cause it to wander back and forth
across this level. leading to erratic output ON and OFF
conditions. The addition of hysteresis. making the trip points
slightly different for rising and falling inputs. will avoid this
condition.
Rpl
v+
R12
Threshold Detector with Hysteresis
-I-
FIGURE 9A. CIRCUIT CONFIGURATION
VOUT
OFF
ON
r-
---l
DETECTOR 2 - / - - - DETECTOR 1
An altemative circuit for obtaining hysteresis is shown in
Figure 11. In this configuration. the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ. but the action is essentially the same.
The goveming equations are given in Table 1. These ignore
.the effects of the resistance of the HYST outputs. but these
can normally be neglected if the resistor values are above
about 100kCl.
FIGURE 9B. TRANSFER CHARACTERISTICS
FIGURE 9. SIMPLE THRESHOLD DETECTOR
VIN
···
·
1
I
I
~
I
R31
Ru
V+
r--
HYSTI
HYST2
R22
r--
I
I
·
SETI
SET2 l -
OUTI
OUT2
OVERVOLTAGE
··:·
I
I
I
r-----<
R21
Figure 10A shows how to set up such hysteresis. while
Figure 108 shows how the hysteresis around each trip point
produces switching action at different points depending on
whether VIN is rising or falling (the arrows indicated direction
of change. The HYST outputs are basically switches which
short out R31 or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value. the trip
point will be controlled by R 1N • R 2N • and R 3N • until the trip
point is reached. As this value is passed. the detector
changes state. R3N is shorted out. and the trip point
becomes controlled by only RIN and R 2N. a lower value. The
input will then have to fall to this new point to restore the
initial comparator state. but as soon as this occurs. the trip
point will be raised again.
VTR2 = VSET2 (R12 + %.l = 1.3 (R 12 + Ru)
~
R12
·
OVERVOLTAGE
RI1
1
1
R12
Rp
FIGURE IDA. CIRCUIT CONFIGURATION
I
Rp
v+
OUT1
R21
OUT
OUT2
HYSTI
HYST2
SET1
RI1
-OFF
VL2 VU2
L---i~~-----L-
I--
+
I
VLI VUl
_________
VIN
VNOU
DETECTOR 2
DETECTOR 1
----l
FIGURE lOB. TRANSFER CHARACTERISTICS
FIGURE 10. THRESHOLD DETECTOR WITH HYSTERESIS
7-151
R22
R32
R31
ON
for detector 2
R12
SE12
1
R12
-'-
FIGURE 11. AN ALTERNATIVE HYSTERESIS CIRCUIT
ICL7665S
TABLE 1. SET-POINT EQUATIONS
NO HYSTERESIS
Ru + R21
Over-Voltage VTR1P
= ---
xVseT1
R21
Ru
324Kn
V+
R22
248Kn
HYST1
HYST2
VSETI
VSET2
OUT1
OUT2
R,2 + R22
Over-Voltage VTR1P
= ---
XVSET2
L--'-'..--i
R'2
t-..-_-..J
~ 100Kn
HYSTERESIS PER FIGURE lOA
VU1
=
Ru +
~,
+ R31
XVSET1
Ru
Over'Voltage VTRIP
= ---
V+
Vu·s.ssv
1Mil
VL_S.45V
XVSET1
=
R'2+~+R32
The ICL7665S can simultaneously monitor several supplies
when connected as shown in Figure 13. The resistors are
chosen such that the sum of the currents through R21A •
R21B • and R31 is equal to the current through R" when the
two input voltage are at the desired low voltage detection
point. The current through R" at this point is equal to 1.3V/
R . The voltage at the VSET input depends on the voltage of
"
both supplies being monitored. The trip voltage of one
supply while the other supply is at the nominal voltage will be
different that the trip voltage when both supplies are below
their nominal voltages.
UnderNoltage VTR1P
R'2 + R22
= ---
X VSET2
R'2
HYSTERESIS PER FIGURE 11
Ru +~,
VU1
= ---
xVSET1
Rn
Over·Voltage VTR1P
VL1
=
Ru +
The other side of the ICL7665S can be used to detect the
absence of negative supplies. The trip points for OUT1
depend on both the negative supply voltages and the actual
voltage of the +5V supply.
~,R3'
--~,+~,
XVSETI
Ru
VU2
=
R'2+~
---
L -_ _ _--<~---.~~WER
Multiple Supply Fault Monitor
X VSET2
R'2
VL2
XVSET2
+IV
274k1l
R'2
V+
R21A
Over-Voltage VTR1P
HYST1
+5V
HYST2
22
~R32
VL2
=
R,2 +
R22 + R32
VL-4.45V
FIGURE 12. FAULT MONITOR FOR A SINGLE SUPPLY
R11
VU2
Vu - 4.SSV
OPEN VOLTAGE
DETECTOR
Ru +~,
VL1
OPEN VOLTAGE
DETECTOR
100kll
Mil
VSET2
X VSET2
R'2
301
kIl
+lSV
787
kIl
+SV
1.D2MIl
R218
Applications
Single Supply Fault Monitor
-6V
1
Mil
-lSV
POWER
OK
Figure 12 shows an over/under voltage fault monitor for a
single supply. The over voltage trip point is centered around
5.5V and the under voltage trip point is centered around
4.5V. Both have some hysteresis to prevent erratic output
ON and OFF conditions. The two outputs are connected in a
wired OR configuration with a pullup resistor to generate a
power OK signal.
7-152
FIGURE 13. MULTIPLE SUPPLY FAULT MONITOR
ICL7665S
Power Fall Warning and PowerupfPowerdown Reset
Combination Low Battery Warning and Low
Battery Disconnect
When using rechargeable batteries in a system, it is
important to keep the batteries from being overdischarged.
The circuit shown in Figure 14 provides a low battery warning and also disconnects the low battery from the rest of the
system to prevent damage to the battery. OUT1 is used to
shutdown the ICL7663S when the battery voltage drops to
the value where the load should be disconnected. As long as
VSET1 is greater than 1.3V, OUT1 is low, but when VSET1
drops below 1.3V, OUT1 goes high shutting off the
ICL7663S. OUT2 is used for low battery warning. When
VSET2 is greater than 1.3V, OUT2 is high and the low battery
warning is on. When VSET2 drops below 1.3V, OUT2 Is low
and the low battery warning goes off. The trip voltage for low
battery warning can be set higher than the trip voltage for
shutdown to give advance low battery waming before the
battery is disconnected.
1
R3t
Figure 15 shows a power fail waming circuit with powerupl
powerdown reset. When the unregulated DC input is above
the trip point, OUT1 Is low. When the DC input drops below
the trip point, OUT1 shuts OFF and the power fail warning
goes high. The voltage on the input of the 7805 will continue
to provide 5V out at 1A until VIN is less than 7.3V, this circuit
will provide a certain amount of warning before the 5V output
begins to drop.
The ICL7665S OUT2 is used to prevent a microprocessor
from writing spurious data to a CMOS battery backup memory by causing OUT2 to go low when the 7805 5V output
drops below the ICL7665S trip point.
v+
~
+
-
--
I
1Wl
HYST1
RZt
HYST2
r--
V+
Rzz
ICL7665S
SET1
SET2 r - - -
~
-
-
v+
Ru
RtZ
OUT1
GND
1
+6V
1A
1000
R32
OUT2
OUT2
ICL7653S
SENSE
SHUTDOWN
~
VSET
GND
~
1Wl
-:;:
I
OUT1
LOW BATTERY SHUTDOWN
-::~
LOW BATTERY WARNING
FIGURE 14. LOW BATTERY WARNING AND LOW BATTERY DISCONNECT
UNREGULATED
DC INPUT
.t
I
4700....
I
7806
SV REGULATOR
~
I
:t
I
470....
B ACKUP
BATTERY
I
v+
r--
HYST1
S.86tea
HYST2
22MO
ICL7665S
VSETt
VSET2
OUT1
OUT2
715tea
2.2Wl
130tea
I
-=.:
1Wl
---<
1MO
-=-=1MO
RESET OR
WRITE
ENABLE
POWER
FAIL
WARNING
FIGURE 15. POWER FAIL WARNING AND POWERUP/POWERDOWN RESET
7-153
ICL7665S
Simple High/Low Temperature Alarm
AC Power Fall and Brownout Detector
Figure 16 illustrates a simple high!low temperature alarm
which uses the ICL7665S with an NPN transistor. The
voltage at the top of Rl is determined by the VeE of the
transistor and the position of Rl'S wiper arm. This voltage
has a negative temperature coefficient. Rl is adjusted so
that VSET2 equals 1.3V when the NPN transistor's
temperature reaches the temperature selected for the high
temperature alarm. When this occurs, OUT2 goes low. R2 is
adjusted so that VSET1 equals 1.3V when the NPN
transistor's temperature reaches the temperature selected
for the low temperature alarm. When the temperature drops
below this limit, OUT1 goes low.
Figure 17 shows a circuit that detects AC undervoltage by
monitoring the secondary side of the transformer. The
capaCitor, C t , is charged through Rl when OUT1 is OFF.
With a normal 100 VAC input to the transformer, OUT1 will
discharge C 1 once every cycle, approximately every 16.7ms.
When the AC input voltage is reduced, OUT1 will stay OFF,
so that C1 does not discharge. When the voltage on C 1
reaches 1.3V, OUT2 turns OFF and the power fail warning
goes high. The time constant, R 1C 1, is chosen such that it
takes longer than 16.7ms to charge C 1 1.3V.
1111111-
+
l
SV
470kO
R3
TEMPERATURE
SENSOR
(GENERAL PURPOSE
NPN TRANSISTOR)
LOW TEMPERATURE
UMITAOJUST
V+
r--
HYST1
R4
22kO
HYST2
-
ICL766SS
27kO
VSETI
VETI
OUT1
OUT2
R6
22MIl
R7
1.SMIl
r:-
1Mil
RS
10Kll
HIGH
TEMPERATURE
UMITADJUST
V+
AI:ARM SIGNAL
1MIl
FORORIVING
LEOS, BELLS,
ETC.
FIGURE 16. SIMPLE HIGHJl..OW TEMPERATURE ALARM
~lII
..
I
I
7806
lhr------~~~·NTrE-R-Eo~~4-70-0~-F~~~--~1 6VRE1GU~TOR 1~--1----Jl~_--SV-'1-A------
11~~~
=-
~~~i~
-=-
..
I
r
HYST1
601kO
+SV
HYST2
ICL7666S
1OOkO
.... -....,
·
1----::'---+
:
R1
1MIl
t-------I
VSETI
VSET2
~ 1MIl
OUT1
OUT2 ~--r'--~r-~-------+
:
••
L-~
________~
••
',h
·!
•
}---~--l-~~-----------------]
FIGURE 17. AC POWER FAIL AND BROWNOUT DETECTOR
7-154
POWER FAIL
WARNING
ICL7673
Automatic Battery Back-Up Switch
April 1994
Features
Description
• Automatically Connects Output to the Greater of
Either Input Supply Voltage
The Harris ICL7673 is a monolithic CMOS battery backup
circuit that offers unique performance advantages over conventional means of switching to a backup supply. The
ICL7673 is intended as a low-cost solution for the switching
of systems between two power supplies; main and battery
backup. The main application is keep-alive-battery power
switching for use in volatile CMOS RAM memory systems
and real time clocks. In many applications this circuit will represent a low insertion voltage loss between the supplies and
load. This circuit features low current consumption, wide
operating voltage range, and exceptionally low leakage
between inputs. Logic outputs are provided that can be used
to indicate which supply is connected and can also be used
to increase the power switching capability of the circuit by
driving external PNP transistors.
• If Main Power to External Equipment Is Lost, Circuit
Will Automatically Connect Battery Backup
• Reconnects Main Power When Restored
• Logic Indicator Signaling Status of Main Power
• Low Impedance Connection Switches
• Low Internal Power Consumption
• Wide Supply Range: .••.•••.•••••••••. 2.SV to 15V
• Low Leakage Between Inputs
• External Transistors May Be Added If Very Large
Currents Need to Be Switched
Ordering Information
Applications
• On Board Battery Backup for Real-Tlma Clocks,
Tlmars, or Volatile RAMs
PART NUMBER
• OveriUnder Voltage Detector
ICL7673CPA
O"C to +7O"C
8 Lead Plastic DIP
ICL7673CBA
O"C to +7O"C
8 Lead SOIC (N)
ICL76731TV
-25°C to +85OC
8 Pin Metal Can
• Peak Voltage Detector
• Other Uses:
- Portable Instruments, Portable Telephones, Une
Operated Equipment
Pinouts
TEMPERATURE
RANGE
PACKAGE
Functional Block Diagram
ICL7673 (SOIC, PDIP)
TOP VIEW
voOav
Vs 2
SaAR
p
7 NC
3
6
GDN4
vP~~----------~~~------~--------~vo
vS~~~-----------r
____--'
PaAR
5NC
ICL7673 (CAN)
TOP VIEW
vp
GND~----------------------------4---~~
Vp> Vs , P1 SWITCH ON AND PaAR SWITCH ON
Vs> Vp, P2 SWITCH ON AND SBAR SWITCH ON
CAUTION: These devices are sensitive to electrostatic discharge. User. should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
7-155
File Number
3183.1
Specifications ICL7673
Absolute Maximum Ratings
Thermal Information
Input Supply (Vp or Vs) Voltage •.•.•.•••••• GND - 0.3V to +18V
Output Voltages PBAR and SBAR •.••.••..••• GND - 0.3V to + 18V
Peak Current
Input Vp (at Vp = 5V) See Note•••••••••..•.•••••••.•. 38mA
InputVs (atVs = 3V) ••.••••••.•••••.••••••••••••••• 30mA
PeAR or SaAR ...•.••...•.•••••••••.•••••••••••••• 150mA
Thermal Resistance
OJA
OJC
Plastic DIP Package • • • • • • • • • • • • • • • • 1500 CNt
Plastic SOIC Package. • . • • • • • • • . • • • . 1800 CNt
Metal Can •• • • • • • • • . • • • • • • • • • • • • • • 156°CNt 68°CNt
Lead Temperature (Soldering, 1Osee) ...••.........•.... 300°C
(SOIC - Lead lips Only)
NOTE: Derate above +250 C by O.38mA1"C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanant demage to the dsvice. This is a stress only rating and operation
of the device at these or any other conditions above those indicated In the operational sections of this specification is not implied.
Operating Conditions
Operafing Temperature Range:
ICL7673C •••••••••.•.•••••••••..••••••••••• OOC to +700C
ICL76731. •••.••••••••••••••••••.••••••••• -2SOC to +85°C
Electrical Specifications
Storage Temperature ••••••••••.•••••••••••• -65OC to +150°C
Lead Temperature (Soldering, 10s) ...•.••••••.•...•... +3OOoC
TA = +25°C Unless Otherwise Specified
PARAMETER
Input Voltage
Quiescent Supply Current
Switch Resistance P1 (Note 1)
SYMBOL
TEST CONDITIONS
V
2.5
-
15
V
1+
Vp = OV, Vs = 3V,I LOAD = OmA
-
1.5
5
IlA
Vp = 5V, Vs = 3V,I LOAD = 15mA
-
8
15
Q
16
-
Q
6
0.5
-
%I"C
40
100
Q
60
%l"C
ROS(ON)P1
TC(Pl)
Vp = 5V, Vs = 3v, ILOAD = 15mA
-
ROS(ON)P2
Vp = OV, Vs = 3V,I LOAD = 1mA
-
Temperature Coefficient of Switch
Resistance P2
TC(P2)
Leakage Current (Vp to Vs>
Il.(ps)
Il.(sp)
Vp = OV, Vs = 9V,I LOAD = 1mA
Vp = OV, Vs = 3V, ILOAD = 1mA
-
0.7
-
-
0.Q1
20
nA
AtTA =+85°C
35
nA
-
-
Vp = OV, Vs = 3V, ILOAD = 10mA
0.01
50
nA
-
120
-
nA
85
400
mV
120
mV
40
-
mV
Vp =5V, Vs = 3V, ILOAD = 10mA
Vp = 5V, Vs = 3V, ISINK = 3.2mA, ILOAD = 0mA
AtTA = +85°C
Vp = 9V, Vs = 3V, ISiNK = 3.2mA,I LOAD = OmA
Vp = 12V, Vs = 3V, ISINK = 3.2mA
ILOAD = OmA
VOSBAR
Q
26
atTA =+85°C
VOPBAR
5
Q
-
Vp = OV, Vs = 5V, ILOAO = 1mA
Open Drain Output Saturation
Voltages
15
2.5
Vp = OV, ILOAD = OmA
AtTA= +85°C
Open Drain Output Saturation
Voltages
UNITS
Vs = OV, ILOAD = OmA
Vp = 12V, Vs = 3V, ILOAD = 15mA
Leakage Current (Vp to Vs)
MAX
Vs
Vp = 9V, Vs = 3V, ILOAD = 15mA
Switch Resistance P2 (Note 1)
TYP
Vp
AtTA=+85°C
Temperature Coefficient of Switch
Resistance P1
MIN
-
16
50
Q
Q
Q
mV
mV
Vp = OV. Vs = 3V, ISiNK = 3.2mA, ILOAD = OmA
-
150
400
atTA =+85°C
-
210
-
mV
-
85
-
mV
50
-
mV
Vp = OV, Vs = 5V, ISINK =3.2mA ILOAD = 0mA
Vp = OV, Vs = 9V, ISiNK = 3.2mA ILOAD =0mA
7-156
Specifications ICL7673
Electrical Specifications
TA = +25"0 Unless Otherwise Specified
PARAMETER
SYMBOL
Output Leakage Currents of P BAR
andSBAR
ILPBAR
(Continued)
MIN
TYP
MAX
UNITS
Vp = OV. Vs = 15V. ILOAD = OmA
-
50
500
nA
atTA = + 85°C
-
900
-
nA
50
500
nA
TEST CONDITIONS
ILSBAR
-
Vp = 15V. Vs" OV. ILOAD " OmA
atTA=+85°C
Switchover Uncertainty for Complete Sw~ching of Inputs and Open
Drain Outputs
Vp- Vs
Vs = 3V. ISiNK = 3.2mA. ILOAD = 15mA
900
-
nA
±10
±50
mV
NOTE:
1. The Minimum Input to output voltage can be determined by muRlplylng the load current by the switch resistance.
Typical Performance Curves
100
100
ILOAD-1mA- I-- I--
ILOAD-15mA
9:
""
N
Do
UI
1\
1
z 10
c
Iii
13
za:0
1
o
2
......
0
4 6 8 10 12 14 1.
INPUT VOLTAGE Vp (V)
FIGURE 1. ON-RESISTANCE SWITCH P1 AS A FUNCTION OF
INPUT VOLTAGE Vp
o
-
246
8
INPUT VOLTAGE Vs
JVo"VV
If
Vo·SV
Vo -3V
0.8
t-"
Vo .12VL
...ffi~ 0.6
I
j
I
II:
II:
~
0.4
I
~
III
0.2
/
o
2
4
6
8 10 12 14 16
SUPPLY VOLTAGE (V)
I
V
/
~ ,/
V
/
1/
10'
Vo .. 15V
~..... ~
I
-400C
+2SOC
+8SOC
1£
10
FIGURE 2. ON·RESISTANCE SWITCH P2 AS A FUNCTION OF
INPUT VOLTAGE Vs
5
B
r- r-
J/~ ~ V
~ J""'"
I
o
FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
7·157
40
80
120
140
OUTPUT CURRENT (mA)
180
FIGURE 4. P BAR OR SBAR SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
ICL7673
P2 is O.5V, since above this voltage the body-drain parasitic
diode will become forward biased. Complete switching of the
inputs and open-drain outputs typically occurs in 50~s.
Input Voltage
The input operating voltage range for Vp or Vs is 2.5V to
15V. The input supply voltage 01 p or Vs) slew rate should be
limited to 2V per microsecond to avoid potential harm to the
circuit. In line-operated systems, the rate-of-rise (or fall) of
the supply is a function of power supply design. For battery
applications it may be necessary to use a capacitor between
the input and ground pins to limit the rate-of-rise of the supply voltage. A low-impedance capacitor such as a O.047~F
disc ceramic can be used to reduce the rate-of-rise.
Status Indicator Outputs
1pA~
o
FIGURE 5.
The N-Channel open drain output transistors can be used to
indicate which supply is connected, or can be used to drive
extemal PNP transistors to increase the power switching
capability of the circuit. When using external PNP power
transistors, the output current is limited by the beta and thermal characteristics of the power transistors. The application
section details the use of external PNP tranSistors.
__-L____~-L~____~____L -__~
:2
4
5 6
8
10
12
INPUTV,M
Applications
Is LEAKAGE CURRENT Vp TO Va AS A FUNCTION
OF INPUT VOLTAGE
Detailed Description
As shown in the Functional Diagram, the ICL7673 includes a
comparator which senses the input voltages Vp and Vs. The
output of the comparator drives the first inverter and the
open-drain N-Channel transistor PBAR .. The first inverter
drives a large P-Channel switch, P1, a second inverter, and
another open-drain N-Channel transistor, SBAR' The second
inverter drives another large P-Channel switch P2. The
ICL7673, connected to a main and a backup power supply,
will connect the supply of greater potential to its output. The
circuit provides break-before-make switch action as it
switches from main to backup power in the event of a main
power supply failure. For proper operation, inputs Vp and Vs
must not be allowed to float, and, the difference in the two
supplies must be greater than 5QmV. The leakage current
th rough the reverse biased parasitic diode of switch P2 is
very low.
A typical discrete battery backup circuit is illustrated in Figure 6. This approach requires several components, substantial printed circuit board space, and high labor cost. It also
consumes a fairly high quiescent current. The ICL7673 battery backup circuit, illustrated in Figure 7, will often replace
such discrete designs and offer much better performance,
higher reliability, and lower system manufacturing cost. A
trickle charge system could be implemented with an additional resistor and diode as shown in Figure 8. A complete
low power AC to regulated DC system can be implemented
using the ICL7673 and ICL7663S micropower voltage regulator as shown in Figure 9.
t--I---+------.....--t--o
=
STATUS
INDICATOR
NICAD
BATTERY ---Y"
STACK
~
Output Voltage
The output oparating voltage range is 2.5V to 15V. The
insertion loss betwean either input and the output is a function of load current, input voltage, and temperature. This is
due to the P-Channels being operated in their triode region,
and, the ON-resistance of the switches is a function of output
voltage Yo. The ON-resistance of the P-Channels have positive temperature coeffiCients, and therefore as temperature
increases the insertion loss also increases. At low load currents the output voltage is nearly equal to the greater of the
two inputs. The maximum voltage drop across switch P1 or
FIGURE 6. DISCRETE BATTERY BACKUP CIRCUIT
Applications for the ICL7673 include volatile semiconductor
memory storage systems, real-time clocks, timers, alarm
systems, and over/under the voltage detectors. Other systems requiring DC power when the master AC line supply
fails can also use the ICL7673.
7-158
ICL7673
8
+SV
PRIMARY
SUPPLY
2
Vp
Vs
Vo
Pbar
Vo
+SVOR+3V
6
RI
STATUS
INDICATOR
GND
UTHIUM
BATTERY
A typical application. as illustrated in Figure 12. would be a
microprocessor system requiring a 5V supply. In the event of
primary supply failure. the system is powered down. and a
3V battery is employed to maintain clock or volatile memory
data. The main and backup supplies are connected to Vp
and Vs. with the circuit output Vo supplying power to the
clock or volatile memory. The ICL7673 will sense the main
supply. when energized. to be of greater potential than Vs
and connect. via its intemal MOS switches. Vp to output Yo.
The backup input. Vs will be disconnected internally. In the
event of main supply failure. the circuit will sense that the
backup supply is now the greater potential. disconnect Vp
from Yo. and connect Vs.
1
4
GND
FIGURE 7. ICL7673 BATTERY BACKUP CIRCUIT
+SvO-.________J8~V~----~V~
PRIMARY
p
0
SUPPLY
Figure 11 illustrates the use of external PNP power transistors to increase the power switching capability of the circuit.
In this application the output current is limited by the beta
and thermal characteristics of the power transistors.
Vo
+SVOR +3V
If hysteresis is desired for a particular low power application.
positive feedback can be applied between the input Vp and
open drain output SBAR through a resistor as illustrated in
Figure 12. For high power applications hysteresis can be
applied as shown in Figure 13.
RC
2
RECHARGEABLE
BATTERY
=
4
GNDO-------~------~~----~
The ICL7673 can also be used as a clipping circuit as illustrated in Figure 14. With high impedance loads the circuit
output will be nearly equal to the greater of the two input sig~~
.
FIGURE B. APPLICATION REQUIRING RECHARGEABLE
BATTERY BACKUP
Vp
8
BRIDGE
RECTIFIER
ICL7663
REGULATOR
Cl
1201240
VAC
4
Vo
8
2
R2
R,
va
ICL7673
BATTERY
BACK-UP
6
4
GND
Rl
STEPDOWN
TRANSFORMER
FIGURE 9. POWER SUPPLY FOR LOW POWER PORTABLE AC TO DC SYSTEMS
+SV
MAIN
POWER
o--------.----------------------~--------------------~
Vp
ICL7673
BACKUP CIRCUIT
FIGURE 10. TYPICAL MICROPROCESSOR MEMORY APPLICATION
7-159
ICL7673
I
Vs
Vo f--NC
P-
ICL7673
&
2
3
GND
+
3V
BACKUP
SUPPLY
t:
1
•
-j
I
PNP
Ri
Vp
MAIN
SUPPLY
l
Rz
PNP
EXTERNAL
EQUIPMENT
Ra
(NOTE 1)
S-
I
I
1
NOTE 1.
>1Mw
FIGURE 11. HIGH CURRENT BATTERY BACKUP SYSTEM
RS
MAIN
SUPPLY 0
Vp
•
ICL7&73
Vs
S3
=
BATTERY +
BACKUP
GND
GND
o-------~-------+----------~
GND
FIGURE 12. LOW CURRENT BATTERY BACKUP SYSTEM WITH HYSTERESIS
I
J
RZ
PNP
J
1
PNP
RF
Ri
+V
Rs
MAIN
SUPPLY
Jvp
8
2
-f
_
MAIN
SUPPLY
GND
'-Ra
S-
Vs
+
1 f-- NC
PICL7&73 6
~
BACKUP
SUPPLY
4
3
I
FIGURE 13. HIGH CURRENT BACKUP SYSTEM WITH HYSTERESIS
Vp
Vo
ICL7673
Vs
GND
FIGURE 14. CLlPPLlNG CIRCUITS
7-160
EXTERNAL
EQUIPMENT
ICL8211,ICL8212
Programmable Voltage Detectors
April 1994
Features
Description
• High Accuracy Voltage Sensing and Generation
The Harris ICL8211/8212 are micropower bipolar monolithic
integrated circuits intended primarily for precise voltage
detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of
output buffer/drivers.
• Internal Reference 1.15VTyplcal
• Low Sensitivity to Supply Voltage and Temperature
Variations
• Wide Supply Voltage Range Typ. 1.8V to 30V
• Essentially Constant Supply Current Over Full Supply
VoHage Range
• Easy to Set Hysteresis Voltage Range
• Defined Output Current Umlt ICL8211
• High Output Current Capability ICL8212
Specifically, the ICL8211 provides a 7mA current limited output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15V (the internal reference). The
ICL8212 requires a voltage in excess of 1.15V to switch its
output on (no current limit). Both devices have a low current
output (HYSTERESIS) which is switched on for input
voltages in excess of 1.15V. The HYSTERESIS output may
be used to provide positive and noise free output switching
using a simple feedback network.
Applications
Ordering Information
• Low Voltage Sensornndlcator
• High Voltage Sensornndlcator
PART NUMBER
• Nonvolatile Out-of.Voltage Range Sensornndlcator
ICL8211CPA
• Programmable VoHage Reference or Zener Diode
TEMPERATURE
RANGE
PACKAGE
OOC to +70u C
8 Lead Plastic DIP
ICL8211CBA
OOC to +700 C
8 Lead SOIC (N)
• Series or Shunt Power Supply Regulator
ICL8211CTY
Ooc to +700 C
8 Pin Metal Can
• Fixed Value Constant Current Source
ICL8211MTY
(Note 1)
-5500 to +125°C
8 Pin Metal Can
ICL8212CPA
ooc to +7000
8 Lead Plastic DIP
ICL8212CBA
OOC to +700 C
Ooc to +7000
8 Lead SOIC (N)
08::
!i(::)
8 Pin Metal Can
::)a:
·55°C to +125°C
8 Pin Metal Can
ICL8212CTY
ICL8212MTY
(Note 1)
m
....1
w3:
a:o
a..
1. Add 18838 to part number if 8838 processing is required
Pinouts
ICL8211 (CAN)
TOP VIEW
HYSTERESIS
NCOev+
HYSTERESIS 2
7 NC
THRESHOLD 3
OUTPUT 4
6 NC
5 GROUND
4
GROUND
CAUTION: These devices are sensitive 10 electrostalic discharge. Users should lollow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1992
7·161
m
~w
NOTE.
ICL8211 (pDIp, SOIC)
TOP VIEW
asH:!
a:....I
File Number
3184.1
ICL8211,ICL8212
Functional Diagram
VOLTAGE REFERENCE
COMPARATOR
OUTPUT BUFFERS
..
.
8
~----~-------'----~-----------4~----------'------'-----------'-----------O v+
R5
4.51<0
2
HYST
------------1.15V
3
VREF
012
THRESHOLD
013
07
R1
20
,
i:
4
OUTPUT
'/~
~---~. 020
~
,,,
.~
,
,,,
,,
,,
,,
R2
301<0
R6
1001<0
5
GROUND
...."""""
ICL8211 OPTION
111111111111
ICL8212 OPTION
7-162
Specifications ICL8211, ICL8212
Absolute Maximum Ratings
Thermal Information
Supply Voltage •••••••••••••..•••••••••.••••• -O.5V to +30V
Output Voltage •••••••.••.•...••.•••••••.•••• -O.5V to +30V
Hysteresis Voltage • . • • • • • • • • • . • • • . • • • • • • . • • • • +O.5V to -1 OV
Threshold Input Voltage •••••••.•••.. +3OV to -5V with respect to
GROUND and +OV to -30V with respect to V+
Currentinto Any Terminal. .•..•••.......••.•...•..••••• ± 30mA
Thermal Resistance
OJ"
9JC
Plastic DIP Package. . • • • • •• • •• • • •. • 1500 CNI
Plastic SOIC Package. • • • • . • • • • • • • . • 18O"CNI
Metal Can • • • • • . . • • • • • • • • • • • • • • • . . 156°CNI 68"CNI
Lead Temperature (Soldering, lOs) ..•......••••••.•.... 300"C
(SOIC - Lead llps Only)
Currentinto Any Terminal .•..........••.•••..••.•.••... ± 30mA
CAUTION: Stresses .bo.... those Usted in "Absolute Maximum Ratings" may cause permanent dama(18 to the device. This Is a stress only ra6ng and operation
01 the device at these or any other condiUons abo.... those indicated In the opera60nalsections 01 this specification Is not implied.
Operating Conditions
Operating Temperature Range
ICL8211M18212M •••••••••.•••.•••••. " •• -55°C to +1250 C
ICL8211C/8212C ••••...••••..••...••....••. O"C to +70oC
Storage Temperature Range •.••••...•.••••.•• -65OC to +l50oC
Electrical Specifications V+ = 5V, T" = +25°C Unless Otherwise Specified
ICL8211
PARAMETER
Supply Current
Threshold Trip Voltage
Threshold Voltage
Disparity Between
Output & Hysteresis
Output
MIN
TVP
MAX
MIN
TYP
MAX
UNITS
VTH = 1.3V
10
22
40
50
110
250
j1A
VTH = 0.9V
50
140
250
10
20
40
j1A
V+=5V
0.98
1.15
1.19
1.00
1.15
1.19
V
V+=2V
0.98
1.145
1.19
1.00
1.145
1.19
V
V+=30V
1.00
1.165
1.20
1.05
1.165
1.20
V
-
-0.8
-
-
-0.5
-
mV
+25OC (Note 3)
2.0
2.0
V
30
2.2
-
30
2.2
-
30
O"C to +70"C (Note 3)
30
V
1.8
-
1.8
V
-
1.4
-
2.5
-
±2oo
-
ppmi"C
SYMBOL
1+
VTH
VTHP
Guaranteed Operating
Supply Voltage Range
VSUPPLY
Minimum Operating
Supply Voltage Range
VSUPPLY
ICL8212
TEST CONDITIONS
2.0
~~
r-
U
!;
...
§:z:
'"ex:w
a:
a: ·10
U
!;
ICL8211 OR 1CL8212
UJ
...
:z:
10
0.0
·25
iii
w
1/
a:
~
>-
ICL8211 OR ICL8212
I
I
L
-30
:z:
I
1.1 1.15 1.2 2.0 3.0 6.0 8.0 10.0
THRESHOLD VOLTAGE (vTHl
(IRREGULAR SCALE)
-40
Typical Performance Curves
o
·20
75
......~
::>
50
VTH"O.IIV
125
....::!.z
TA-+25oC
OUTPUTS OPEN CIRCUI
w
" - .........
\,
100
w
a:
a:
75
~
50
B
......
::>
25
L...--
25
o
VTH-l.3V
-I
o
10
0.0
20
30
SUPPLY VOLTAGE
FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
12
,.~
125
I
VTH-O.IIV
.......... i'oo..
.......
C
.§.
zw
a:
a:
100
...
a:
a:
75
::>
U
......
::>
UJ
8
6
u
::>
!;
50
25
VTH .. l.3V
f-- ~
o
..ss
-25
- ----
+5
+35
V
+65
......
",
--
8
o
+125
1.12
TEMPERATURE °c
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF TEMPERA·
TURE
7·165
0
TA,,+250C
V+.+5V
-5
Vo .. 0.5V
VHYS " v+ ·0.25V
·10
iii
HY!TEREJIS _
OUTPUT
.......c:c:
1.13
:z:
~
iil3J
m
'"
0
7~,
,~
~
-H
1.14
·15
....
·20
4 -OUTPUT
2
+115
4.0
-
10
....::!.z
~
1.0
1.1
1.15 1.2
2.0
THRESHOLD VOLTAGE (vTHl
(IRREGULAR SCALE)
FIGURE 4. SUPPLY CURRENT AS A FUNCTION OF THRESH·
OLD VOLTAGE
150
w
TA=+250C
V+.+5V
OUTPUTS OPEN
CIRCUIT
UJ
UJ
C
+80
(ICLB211 ONLY)
C
a:
ex:
u
+60
150
125
100
+40
FIGURE2. HYSTERESIS OUTPUT SATURATION CURRENT AS
A FUNCTION OF TEMPERATURE
150
...z~
+20
TEMPERATURE ("C)
FIGURE 1. THRESHOLD INPUT CURRENT AS A FUNCTION OF
THRESHOLD VOLTAGE
::>
.......
·20
~
I
I
100
-
::>
I
;E
V+_+5V
VTH _1.2V
VHYS-4.5V
(OR -O.5V WITH RESPECT
TO V+ SUPPLy)
..s
n
c:
3J
3J
m
·25
Z
....
'i?
~
1- 8mV
1.15
1.16
1.17
-30
1.18
THRESHOLD VOLTAGE
FIGURE 6. OUTPUT SATURATION CURRENTS AS A FUNCTION OF THRESHOLD VOLTAGE
ICL8211,ICL8212
Typical Performance Curves
(ICL8211 ONLY)
(Continued)
1.11
1.151--+--t--:::;o.....;;....t--t-~
1.17
CI
~
~ 1.1.
/
~
1.14 1--f----If-74--+--+--i
§:z:
I
~
/
w
IV
~
9
loa4mA, Voa1V
IHYI a .7"", VHY8 a (V+ -2) V
OUTPUT J1I ",
~
(I)
w
a:
:z:
1.13
-is
I-
V+_+SV
10 a1mA, VOUT a +5V
IHYS - .7"", VHST _ OV
·25
+5
+35
+55
TEMPERATURE (OC)
+IIS
./
1,.;'' '
1.14
V
./
1; ......
1.15
HYSTERESIS OUTPUT
II
"I'"
II
1.13
+125
1
FIGURE 7. THRESHOLD VOLTAGE TO TURN OUTPUTS "JUST
ON" AS A FUNCTION OF TEMPERATURE
2
3 4 5
10
20 304050
SUPPLY VOLTAGE
100
FIGURE 8. THRESHOLD VOLTAGE TO TURN OUTPUTS"JUST
ON" AS A FUNCTION OF SUPPLY VOLTAGE
a
12
TA-+2S0C
V+a+5V
,;
~
~ .....
/
VTH-1.0V
........
I~
V+_+5V
VTH-1.1VVo-1.0V
5
-is
it
-25
+5
+35
+55
+05
TEMPERATURE ~C)
o
+125
0
i
IZ
oS
w
a: ·10
a:
:::0
U
·15
5
-20
5
-25
I!=
!I.!
(I)
I
~
I
I
"!"T" ~I.
~ VT"l.l44V
~
II
~
VTH a1.152V
1.0
10.0
OUTPUT VOLTAGE
"i",.
//
I
II I
II!!!!.
"":'vT
:"'"a l.lav
~~
w
a: -30
I!!
VTHa1.147V
TAa+25OC-
fittl-
-35
-40
·10.00
100.0
FIGURE 10. OUTPUT CURRENT AS A FUNCTION OF OUTPUT
VOLTAGE
VT" 1.143V
I I
_..
IV
0.1
FIGURE 9. OUTPUT SATURATION CURRENT AS A FUNCTION
OF TEMPERATURE
II
·1.00
-0.10
-0.01
HYSTERESIS OUTPUT VOLTAGE
FIGURE 11. HYSTERESIS OUTPUT CURRENT AS A FUNCTION OF HYSTERESIS OUTPUT VOLTAGE
7-166
ICL8211,ICL8212
Typical Performance Curves
(ICL8212
ONLY)
150
150
TA- +2SOC
OUTPUTS OPEN CIRCUIT
125
125
~
~
j:
.a.
100
II:
II:
75
!iw
B
VTH-1.3V
II:
II:
75
~
50
/
I
B
......
50
::>
100
!iw
~
It
TA-·250C
V._.5V
OUTPUTS OPEN CIRCUIT
-
V
::>
1/1
1/1
25
25
VTH-0.8V
o
I
o
o
0.0
10
20
SUPPLY VOLTAGE
'" -
125
~
~ 100
!iw
II':
75
VTH-1.3V_
It
iil
!.
t-
/
20
w
II:
II:
B
...
8
.".,.
\ J
15
"
·25
.5
.35
+65
.05
II:
II:
·10
::>
0
!;
I!:
·15
8
!llw
·20
I
5
II:
w
·25
t1/1
>-
:z:
OUTPUT
1.14
.125
I
!iw
......... HYSTERESIS OUTPUT
10
o
o
I
~
-5
T,,_.2SOC
V._5V
VOUT-4V
VHYS - V. -CI.25V
Z
VTH_O.OV-
-55
4.0
0
[,..-r
25
!;
25
2.0
I
~
50
1.2
30
B
~
1.15
FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF THRESH·
OLD VOLTAGE
I I
V•• 5V
OUTPUTS
OPEN
CIRCUIT
1.1
THRESHOLD VOLTAGE (VTH)
(IRREGULAR SCALE)
FIGURE 12. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
150
1.0
30
1.15
1.16
~
1.17
1.18
1.111 1.20
THRESHOLD VOLTAGE
TEMPERATURE rC)
FIGURE 14. SUPPLY CURRENT AS A FUNCTION OF TEMPER·
ATURE
FIGURE 15. OUTPUT SATURATION CURRENTS AS A FUNCTION OF THRESHOLD VOLTAGE
1.18
1.17
10 ,"1mA, VOUT'" 5V
IHYS - .7"A, VHYS .. OV
1.17
w
w
"
~
1.16
;.J
0
>
90
V
:z:
1/1
w 1.15
V~
II:
j!:
~"
V
./
~
~
:z:
1/1
V
1.15
/V
w
""""'BOTH OUTPUT AND
HYSTERESIS OUTPUT
II:
1.14
1.13
·25
.5
+35
.65
.05
i/
/,
°ir'lL
BOTH OUTPUT ANDH1YSTERjSlj
j!:
V
1.14
-55
7
1.16
1
.125
TEMPERATURE rC)
FIGURE16. THRESHOLDVOLTAGETOTURNOUTPUTS"JUST
ON" AS A FUNCTION OF TEMPERATURE
2
TA-·25oC
loUT - 4mA, VOUT IHYS - ·7J1A, VHYS I
I
I
I
3 45
10
20 30
1V
(V. -2) V
I I
4050
100
SUPPLY VOLTAGE
FIGURE17. THRESHOLDVOLTAGETOTURNOUTPUTS"JUST
ON" AS A FUNCTION OF SUPPLY VOLTAGE
7·167
ICL8211,ICL8212
Typical Perfonnance Curves
Detailed Description
(ICL8212 ONLY) (Continued)
The ICL8211 and ICL8212 use standard linear bipolar
integrated circuit technology with high value thin film
resistors which defme extremely low value currents.
~&r---~--.-~.---.---~--'
~TSAT.
I
a
1__--+_-1
w
~
0.5
> 0.4
~
II:
0.3
01
0.2
~
~
§
CURRENT
(Vo·4.0V)
I
........
Components 0 1 through 0 10 and R 1, R2 and R3 set up an
accurate voltage reference of 1.15V. This reference voltage
is close to the value of the bandgap voltage for silicon and is
highly stable with respect to both temperature and supply
voltage. The deviation from the bandgap voltage is
necessary due to the negative temperature coefficient of the
thin film resistors (-5000 ppm per °C).
r-:.:;;;
V
hI~+--+--+---b,;t£~----1
~ ~LTAGESAT.
CURRENT
(10 a 10mA)
~~
I
1
0.1
Components O2 through Og and R2 make up a constant
current source; O2 and 0 3 are identical and form a current
has 7 times the emitter area of Og, and due to the
mirror.
and Og are forced
current mirror, the collector currents of
to be equal and it can be shown that the collector current in
and Og is
as
V+a+5V
OL-__
-55
~
__
~
__
VTH_1.2V
~
__-L__
~
__
+5
+35
+55
+05
TEMPERATURE <"C)
-25
~
as
as
+125
1
kT
IC(OeoraQ)= ~ x --- In7
q
FIGURE 18. OUTPUT SATURATION VOLTAGE AND CURRENT
AS A FUNCTION OF TEMPERATURE
or approximately 111A at +250 C
i
V
30
~
Where k = Boltzman's Constant
q = Charge on an Electron
and T = Absolute Temperature in OK
as,
Transistors
0 6 , and Or assure that the VCE of 0 3, 0 4 ,
and Og remain constant with supply voltage variations. This
ensures a constant current supply free from variations.
~~H-~++~4-~~~
~
I
20
u
1-+++-f,IHI--H-H--l-+.H+--l
i.-i.-' "1
f---HIJ~i.;'--!-~=FIIVTHr 1·Y8,
The base current of 0 1 provides sufficient start up current for
the constant source; there being two stable states for this
type of circuit - either ON as defined above, or OFF if no
start up current is provided. Leakage current in the transistors is not sufficient in itself to guarantee reliable startup.
I-
10~~HV~4-++H-+-~O~~
O~
0.1
1.0
10.0
OUTPUT VOLTAGE
0 4 is matched to 0 3 and O2; 0 10 is matched to Og. Thus the
IC and VeE of 0 10 are identical to that of Og or as. To
30.0 100.0
FIGURE 19. OUTPUT CURRENT AS A FUNCTION OF OUTPUT
VOLTAGE
0
1
-5
zw
-10
::>
-15
I-
II:
II:
u
,...
::>
S
-20
~w
-25
0
I
II:
-30
~
-3S
w
::c
~
I
which provides:
a10) +
R3
kT
~
q
-- x
R3
__ = 12 (approximately.)
~
The total supply current consumed by the voltage reference
section is approximately 6IIA at room temperature. A voltage
at the THRESHOLD input is compared to the reference 1.15V
by the comparator consisting of transistors all through 0 17.
The outputs from the comparator are limited to two diode
drops less than V+ or approximately 1.1V. Thus the base current into the hysteresis output transistor is limited to about
500nA and the collector current of 019 to 1ClOIlA.
......
I - VTa1.18V
T"a+2SOC _
V+a+10V
~OL-~~L-L-~~
-10.00
Thus 1.5 = V8E (Oe or
A
VT a 1.1S3V
I-
as
'!II
III
VTa1.152V
generate the bandgap voltage, it is necessary to sum a
voltage equal to the base emitter voltage of Og to a voltage
proportional to the difference of the base emitter voltages of
two transistors
and Og operating at two current densities.
__L-~~~
-1.00
-0.10
-0.01
HYSTERESIS OUTPUT VOLTAGE
FIGURE 20. HYSTERESIS OUTPUT CURRENT AS A FUNCTION
OF HYSTERESIS OUTPUT VOLTAGE
In the case of the ICL8211, 0 21 is proportioned to have 70
times the emitter area of 0 20 thereby limiting the output
current to approximately 7mA, whereas for the ICL8212
7-168
ICL8211,ICL8212
almost all the collector current of 0 19 is available for base
drive to 0 21 , resulting in a maximum available collector
current of the order of 30mA. It is advisable to extemally limit
this current to 25mA or less.
Applications
The ICL8211 and ICL8212 are similar in many respects, especially wnh regard to the setup of the input trip condnions and
hysteresis circunry. The following discussion describes both
devices, and where differences occur they are clearly noted.
General Information
Threshold Input Considerations
Although any voltage between -5V and V+ may be applied to
the THRESHOLD terminal, it is recommended that the
THRESHOLD voltage does not exceed about +6V since
above that voltage the threshold input current increases
sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.
The outputs change states with an input THRESHOLD
voltage of approximately 1.15V. Input and output waveforms
are shown in Figure 21 for a simple 1.15V level detector.
A principal application of the ICL8211 is voltage level
detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive supply without a series current
lim iting resistor.
On the other hand the ICL8212 is intended for applications
such as programmable zener references, and voltage
regulators where output currents well in excess of 7mA are
desirable. Therefore, the output of the ICL8212 is not current
limited, and if the output is used to drive an LED, a series
current limiting resistor must be used.
In most applications an input resistor divider network may be
used to generate the 1.15V required for VTH • For high accuracy, currents as large as 5011A may be used, however for
those applications where current limiting may be desirable,
(such as when operating from a battery) currents as low as
6mA may be considered without a great loss of accuracy.
6mA represents a practical minimum, since it is about this
level where the device's own input current becomes a significant percentage of that flowing in the divider network.
v+
INPUT VOLTAGE
(RECOMMENDED
RANGE -5 TO +5V)
VTH
as TTL or CMOS using a single pullup resistor. There is a
guaranteed TTL fanout of 2 for the ICL8211 and 4 for the
ICL8212.
(V+MUSTBE
I:QUALOR
EXCEED 1.8V)
0--+----1
PULLUP RESISTOR
Vo
RU
FIGURE 22. OUTPUT LOGIC INTERFACE
INPUT
"~ffvfM)
V+
OV
V+
ov
-n----n-nI
I
I
I
ICWll OUTPUT
~o-~~
___________
~
I
~ ICL8212 OUTPUT
FtGURE 21. VOLTAGE LEVEL DETECTION
FtGURE 23. INPUT RESISTOR NETWORK CONSIDERATIONS
The HYSTERESIS output is a low current output and is
intended primarily for input threshold voltage hysteresis
applications. If this output is used for other applications it is
suggested that output currents be limited to 1011A or less.
Case 1. High accuracy required, current in resistor network
unimportant Set I 5011A for VTH 1.15V :. Rl ~
20kn
The regular OUTPUT's from either the ICL8211 or ICL8212
may be used to drive most of the common logic families such
=
=
Case 2. Good accuracy required, current in resistor network
important Set I 7.511A for VTH 1.15V :. Rl ~
150kn
7-169
=
=
ICL8211,ICL8212
The disadvantage of the simple detection circuits is that
there is a small but finite input range where the outputs are
neither totally 'ON' nor totally 'OFP. The principle behind
hysteresis is to provide positive feedback to the input trip
point such that there is a voltage difference between the
input voltage necessary to tum the outputs ON and OFF.
INPUT
I
~
".rr
VOLTAGE
The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry. however, is
not limited to applications requiring better noise performance
but may be expanded into highly complex systems with
multiple voltage level detection and memory applicationsrefer to specific applications section.
RI
~~--~----------------------~
Input voltage to change to output states
= (R1;I R2) x 1.15V
-
FIGURE 24. RANGE OF INPUT VOLTAGE GREATER THAN
+1.15 VOLTS
There are two simple methods to apply hysteresis to a circuit
for use in supply voltage level detection. These are shown in
Figure 27.
Setup Procedures For Voltage Level Detection
Case 1. Simple voltage detection no hysteresis
Unless an input voltage of approximately 1.15V is to be
detected. resistor networks will be used to divide or multiply
the unknown voltage to be sensed. Figure 25 shows
procedures on how to set up resistor. networks to detect
INPUT VOLTAGES of any magnitude and polarity.
A third way to obtain hysteresis (ICL8211 only) is to connect
a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external resistance
between the THRESHOLD and GROUND when the
OUTPUT is switched on.
VREF(+YE)
V+
0-
r
The circuit of Figure 27A requires that the full current flowing
in the resistor network be sourced by the HYSTERESIS output. whereas for circuit Figure 27B the current to be sourced
by the HYSTERESIS output will be a function of the ratio of
the two trip points and their values. For low values of hysteresis. circuit Figure 27B is to be preferred due to the offset
voltage of the hysteresis output transistor.
RI
Practical Applications
Low Voltage Battery Indicator (Figure 28)
This application is particularly suitable for portable or remote
operated equipment which requires an indication of a depleted
or discharged battery. The quiescent current taken by the system will be typically 35~ which will increase to 7mA when the
lamp is turned on. R3 will provide hysteresis if required.
Range of input voltage less than +1. 15V
Input voltage to change the output states
(R 1 +~) x 1.15
R2V REF
Rl
. --R1-
Nonvolatile Low Voltage Detector (Figure 29)
FIGURE 25. INPUT RESISTOR NETWORK SETUP
PROCEDURES
For supply voltage level detection applications the input
resistor network is connected across the supply terminals as
shown in Figure 26.
,--_ _ _ _ _ _ _ _ _ _ _....._
.... V+
INPUT VOLTAGE
OR
SUPPLY VOLTAGE
~---------+_-~Vo
FIGURE 26. COMBINED INPUT AND SUPPLY VOLTAGES
Case 2. Use of the HYSTERESIS function
In this application the high trip voltage VTR2 is set to be
above the normal supply voltage range. On power up the
initial condition is A. On momentarily closing switch SI the
operating point changes to B and will remain at B until the
supply voltage drops below VTR1. at which time the output
will revert to condition A. Note that state A is always retained
if the supply voltage is reduced below VTRI (even to zero
volts) and then raised back to VNQM.
Nonvolatile Power Supply Malfunction Recorde
(Figure 30 and Figure 31)
In many systems a transient or an extended abnormal (or
absence of a) supply voltage will cause a system failure.
This failure may take the fonn of infonnation lost in a volatile
semiconductor memory stack. a loss of time in a timer or
even possible irreversible damage to components if a supply
voltage exceeds a certain value.
It is. therefore. necessary to be able to detect and store the
fact that an out-ol-operating range supply voltage condition
has occurred, even in the case where a supply voltage may
7-170
ICL8211,ICL8212
V+
r-----------------------~~--o
Ra
R2
150k0
'--__________________4 __- 0 va
NOTE 1. Ra OPnONAl
Low trip voltage
FIGURE 28. LOW VOLTAGE BATTERY INDICATOR
V _ [(R l +Rz)X1.1S+0.1V]
TRl Rl
volts
High trip voltage
VTR2 = (R l + Rz + Ra) x 1.1SV
Rl
FIGURE 27A.
~----------------------~~--o
V+
r---~------------------'-~----oV+
RQ
Rp
'----------------+--_--0 OUTPUT
'--------------------4---0 va
Low trip voltage
RaRs
[
+Rp] x
VTRl = (Ra + Rs)
~
FlGURE29A.
x1.1SV
High trip voltage
(Rp+ Ra)
VTR2 = - '- - x 1.1SV
Rp
FIGURE 27B.
~
w
..... ~ .......
ON
!c
ti
!;
ti
!;
··
·
: VTR1
________ ,..._..Br__---o...... _____
I~·····
§
-----.
OFF
....---------..
j
"·
•
••
ON
~
!;
ti
~!
•
:VNOM
: VlR2
SUPPLY VOLTAGE _ _
SUPPLY VOLTAGE _ _
FlGURE29B.
FIGURE 27C.
FIGURE 27. TWO ATERNATIVE VOLTAGE DETECTION
CIRCUITS EMPLOYING HYSTERESIS TO
PROVIDE PAIRS OF WELL DEFINED TRIP
VOLTAGES
FIGURE 29. NON·VOLATILE LOW VOLTAGE INDICATOR
7-171
ICL8211, ICL8212
have dropped to zero. Upon power up to the normal
operating voltage this record must have been retained and
easily interrogated. This could be important in the case of a
transient power failure due to a faulty component or
intermittent power supply. open circuit. etc.. where direct
observation of the failure is difficult.
A simple circuit to record an out of range voltage excursion
may be constructed using an ICL8211. an ICL8212 plus a
few resistors. This circuit will operate to 30V without exceeding the maximum ratings of the ICs. The two voltage limits
defining the in range supply voltage may be set to any value
between 2.0V and 30V.
The ICL8212 is used to detect a voltage. V2 • which is the
upper voltage limit to the operating voltage range. The
ICL8211 detects the lower voltage limit of the operating
voltage range. VI. HystereSis is used with the ICL8211 so
that the output can be stable in either state over the
operating voltage range VI to V2 by making V3 - the upper
trip point of the ICL8211 much higher in voltage than V2•
The output of the ICL8212 is used to force the output of the
ICL8211 into the ON state above V2 • Thus there is no value
of the supply voltage that will result in the output of the
ICL8211 changing from the ON state to the OFF state. This
may be achieved only by shorting out R3 for values of supply
voltage between V I and V2.
Constant Current Sources (Figure 32)
The ICL8212 may be used as a constant current source of
value of approximately 25J,1A by connecting the THRESHOLD terminal to GROUND. Similarly the ICL8211 will provide a 130J,1A constant current source. The equivalent
parallel resistance is in the tens of megohms over the supply
voltage range of 2V to 30V. These constant current sources
may be used to provide basing for various circuitry including
differential amplifiers and comparators. See Typical Operating Characteristics for complete information.
Programmable Zener Voltage Reference (Figure 33)
The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using
a resistor network connected to the THRESHOLD terminal
to program the zener voltage
VZENER =
(R I +R2)
RI
x 1.15V.
1-------------------------.----~----_4~--------------------~--1_----o
v+
SI
RESET
OUTPUT
FIGURE 30. NON-VOLATILE POWER SUPPLY MALFUNCTION RECORDER
OUTPUT ICL8211
ICL8212 DISCONNECTED
,
:
:
----r---+'::o--~'r",----,..--+1
:
ON ..-
i
'
: ..:
-----i I-
2
'-r--
I-
-=:!;:-
o
Ia)
CIRCUIT
BEING
PROTECTED
RI
V-
0.01
0.1
1.0
SUPPLY CURRENT (rnA)
100
10
v-
_L-----L~::::Jr-'
(b)
FIGURE 35. HIGH VOLTAGE DUMP CIRCUITS
FIGURE 33. PROGRAMMABLE ZENER VOLTAGE REFERENCE
Precision Voltage Regulator (Figure 34)
Frequency Limit Detector (Figure 36)
The ICL8212 may be used as the controller for a highly stable series voltage regulator. The output voltage is simply programmed, using a resistor divider network RI and R2. Two
capacitors C1 and C2 are required to ensure stability since
the ICL8212 is uncompensated internally.
Simple frequency limit detectors providing a GO/NO-GO output for use with varying amplitude input signals may be conveniently implemented with the ICL8211/8212. In the
application shown, the first ICL8212 is used as a zero crossing detector. The output circuit consisting of R3 , R4 and C2
results in a slow output positive ramp. The negative range is
much faster than the positive range. Rs and R6 provide hysteresis so that under all circumstances the second ICL8212
is turned on for sufficient time to discharge C3 . The time constant of R7 Ca Is much greater than R4 C2. Depending upon
the desired output polarities for low and high input frequencies, either an ICL8211 or an ICL8212 may be used as the
output driver.
V+
R2
This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the Input frequency.
R2+RI
VOUT " ~ x1.15V
FIGURE 34. PRECISION VOLTAGE REGULATOR
Switch Bounce Filter (Figure 37)
Single pole single throw (SPSl) sw~ches are less costly and
more available than single pole double throw (SPDl) switches.
7-173
ICL8211, ICL8212
SPST sw~ches range from push button and slide types to calculator keyboards. A major problem with the use 01 s~ches is
the mechanical bounce of the electrical contacts on closure.
Contact bounce times can range from a fraction of a millisecond to several tens of milliseconds depending upon the sw~ch
type. During this contact bounce time the s~ch may make and
break contact several times. The circu~ shown in Figure 37 provides a rapid charge up of C1 to close to the positive supply
voltage (VI) on a switch closure and a corresponding slow discharge of C1 on a switch break. By proportioning the time constant of Rl C1 to approximately the manufacturer's bounce time
the output as terminal #4 of the ICl821118212 will be a single
transition of state per desired s~ch closure
Low Voltage Power Disconnect (Figure 38)
There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
below a certain value. As an example, the National LMl99
precision reference has an on chip heater which malfunctions with supply voltages below 9V causing an excessive
device temperature. The ICL8212 may be used to detect a
power supply voltage of 9V and turn the power supply off to
the LM199 heater section below that voltage.
For further applications, see AN027 ·Power Supply Design
using the ICL8211 and ICL8212."
v+
OUTPUT
nME CONSTANT RA < ~~ s RM
VARY Rt FOR OPnON ZERO CROSSING DETECTION
VARY R4 TO SET DETEcnON FREQUENCY
.-:.......J INDETERMINATE
INPUT
-.BELOWFo
- - # - - - - - - ' ! I k - - - -.......IL---
OFF r----f~---I,......--··················· ON
1.:V --t+t--------~I-I---
ON~
_ _~ _ _~
FO
OFF
FREQUENCY_
FIGURE 36. FREQUENCY LIMIT DETECTOR
r--------------1--~--._~--O~
r--1r-----------------~--+_~V+
Ra
L------____
+-~__o
FIGURE 37. SWITCH BOUNCE FILTER
Vo
FIGURE 38. LOW VOLTAGE POWER SUPPLY DISCONNECT
7-174
INTELLIGEN- ~ 8
POWERICs
PROTECTION CIRCUITS
PAGE
PROTECTION CIRCUITS SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2
PROTECTION CIRCUITS DATA SHEETS
SP710
Protected Power Switch with Transient Suppression .......••..•................
8-3
SP720
Electronic Protection Array for ESD and Overvoltage Protection . . . . . . . . . . . . . . . . . . .
8-5
SP720MD-8,
SP720MD,
SP720MM-8,
SP720MM
High Reliability Electronic Protection Array for ESD and Overvoltage Protection. . . . . . .
8-8
SP721
Electronic Protection Array for ESD and Overvoltage Protection. . . . . . . . . . . . . • . . . . .
8-14
8-1
Protection Circuits Selection Guide
PART
NUMBER
DESCRIPTION
SUPPLY
VOLTAGE
RANGE
-4O"C to +1 05"C 3 LeadTO-220
Protected Power Switch
SP720
Protection Array
4.SVto 30V
+VBE Above Vee or -4O"C to + 105"C 16 Lead Plastic DIP and
SOIC
-VBE Below GND
SP720MD-8
Ceramlc Packaged Harris Class B
"Equivalent" SP720 Parts with BackEnd Conformance to MIL-STD-883
4.SVt030V
+VBE Above Vee or -55°C to +125"C 16 Lead Ceramic SBDIP
-VBE Below GND
20 Pad Ceramic LCC
High Reliability Ceramic Packaged
SP720 Parts
4.SVto 30V
+VBE Above Vee or -S5"C to + 125"C 16 Lead Ceramic SBDIP
-VBE Below GND
20 Pad Ceramic LCC
SP721
Protection Array
4.SVt030V
+VBE Above Vee or -40"C to +1 OSoC 8 Lead Plastic DIP and
SOIC
-VBE Below GND
HIP1090
Protected Power Switch
SP720MD
SP720MM
4V to 16V
8-2
16Vto 18.SV
PACKAGE
SP710
SP720MM-8
4Vto 16V
OVER-VOLTAGE
TURN-ON
TEMPERATURE
RANGE
THRESHOLD
16V to 19V
-40"C to +1 OSoC 3 Lead T0-220
SP710
Protected Power Switch
with Transient Suppression
April 1994
Features
Description
• ±90V Transient Suppression
The SP710 is a Power Integrated Circuit designed to
suppress potentially damaging overvoltage transients up to
±90V in amplitude. The device is designed to be operated in
a pass-thru mode which allows the current to flow through
the IC with minimal voltage drop. The protected load circuit
is connected to the output of the SP710. As such, the
protected power switch IC is designed to operate as a
transient suppressor which is capable of driving resistive,
inductive or lamp loads with minimum risk of damage under
stress conditions of over voltage or over current. The SP71 0
is supplied in a 3 lead T0-220AB package.
• 4V to 16V Operating Voltage
• O.SA Current Load Capability
• Over-Voltage Shutdown Protected
• Short-Circuit Current Umltlng
• Over-Temperature Protected Thermal Umltlng
at 150°C (TJ)
• -40°C to +1050 C Operating Temperature Range
Applications
Ordering Information
• Electronic Circuit Breaker
• Transient Suppressor
• Overvoltage Monitor
Pinout
PART NUMBER
TEMPERATURE
RANGE
SP710AS
-40°C to +1 05°C
PACKAGE
3 Lead Plastic
SIP
Functional Block Diagram
SP720(SIP)
,,.. _-_ ............ _-- ........................ __ ... _-_ ... _--_ ............ -.....
,
TOP VIEW
NOTE:
HEAT SINK TAB
INTERNALLY
CONNECTED
TO PIN 2
0
--0
VIN :
1
'
~
_-------.....----------------,,,
~
Rs
~
OR
III
I
I
I
I I I
,
3
:~
,
: LOAD)
VBATT):
1 2 3 [
: Vour
,,:
,,,
0..
VCOMMON
(GND)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1993
8-3
File Number
tls
W()
0
o::()
!_------_. . --------_ . .-----------.. . . _--_ . . . _---- --.. --.. --------.. ---~
2
-I-
1-0::
,,
,,,
,,
,,,
,,
,,,
,,
,
,,,
,,
,
,,
,,
,,,
,,,
,,
,,
,
,,,
,,
,,,
Z
0(1)
2789.6
Specifications SP710
Absolute Maximum Ratings
Thermal Information
Input Voltage, VIN •••••••••••••••••••••••••••••••••••• 24V
Load Current, lOUT' •••••••••••••••••••••••••••••••• 8OOmA
TransIent Max Voltage, VIN (ISms) ........................ ±90V
Thermal Resistance
9JA
9JC
Plastic SIP. • • • • • • • • • • • • • • • • • • • • • •• • 6O"C/W
4"C1W
Junction Temperature ••••••••••••••••••••••••••••••. 15O"C
Ambient Operallng Temperature ••••••••••••••• -4OOC to +1 05°C
Storage Temperature•••.•••••••••••••••••••• -40"C to +15O"C
Lead Temperatura (During Soldering) ••••••••••••••••••• 265°C
1/16in. ± 1/32ln. (1.59rnrn± 0.79rnrn) from case for lOs maximum
NOTE: Po = (VIN - Vol (10) + (VIN) (ICOMMON)
TJ = TA + (Po) (Thermal Resistance)
CAUTION: S _ abow those listed in 'Absolute Maximum Ratings" may cause perm_ damage to Ihe device. ThIs is 8 stress only ",ting and opfI",tion
of the dl!Jllic6 at thes6 or any other conditions abow those indicated in Ihe "",,,,tiona! ssctiona of this specification is not 1",,1Ied.
Electrical Specifications
PARAMETER
TA =-4OOC to +105°C, VIN
MIN
TYP
MAX
UNfTS
VIN
4
-
16
V
VSHSO
16
-
18.5
V
-
150
-
°C
-
+20
rnA
2
A
0.25
V
-
0.65
V
-
1.05
V
25
rnA
50
rnA
SYMBOL
Input Operating Voltage
Shutdown Voltage
=4V to 16V, Unless Otherwise Specified
CONDITIONS
Shutdown Temperature
Transient Pulse
lOUT
VIN =±90V for ISms Pin 3
=14V, Pin 2 =GND
Short Circuit Current
-20
1
VSAT (Input-ta-OUtput)
VIN
=4V, lOUT = 175rnA
VIN
=9V, lOUT =500rnA
-
VIN =16V, lOUT = 800rnA
Common Current
ICOM
=16V, lOUT =l00mA
VIN = 16V, lOUT =800mA
VIN
Typical Application
,,"..................... -_ ...................... -_ ................... -_ ......... -_ ......... -_ ...............
Vurr
As
: YIN
I
---- -_ ............... ..
VOUT
DASH PANEL LOAD
@~_~a:
--~--~~~~----~~?---------~--~ ~--------~~~--~--~--.--+
INPUT
1:
03
: 3
:
!
:I
:
~
i:
THERMAL
UMiT
I
CURRENT
UMiT
IIII V:i~E III C~iNT II
SHUTDOWN
AMPUFIER
J
:
~
Ii
i
I
.. -.- .... -.... -........-.. ---.--.--.- ..
~
:,
-.-~
VCOMMON
:
(GNO)
:
:(_._._._..... _.. _.
""...S="
INSTRUMENTS
DETECTOR:
,
:
VceSAT
.,b
O.47I'F~ _~
j - ~
:
TO OTHER
UGHTSANO
YLOAD· Yurr - YSAT
(VSAr TYP. < lY AT 8OOmA)
SP720
Electronic Protection Array for
ESD and Overvoltage Protection
April 1994
Features
Description
• ±2A Peak Current Capability
• Proven Interface for ESD
The SP720 is an array of SCRlOiode bipolar structures for
ESO and oller-voltage protection to sensitive input circuits.
The SP720 has 2 protection SCRlOiode device structures
per input. A total of 14 available inputs can be used to
protect up to 14 external signal or bus lines. Over voltage
protection is from the IN (pins 1-7 and 9-15) to V+ or V-. The
SCR structures are designed for fast triggering at a
threshold of one +VBE diode threshold above V+ (Pin 16) or
a -VBE diode threshold below V- (Pin 8). From an IN input, a
clamp to V+ Is activated if a transient pulse causes the input
to be increased to a voltage level greater than one VBE
above V+. A similar clamp to V- is activated if a negative
pulse, one VBE less than V-, is applied to an IN input.
• Oparatlng Temparature Range •••••• -40oC to +105°C
Refer to Application Note AN9304 for further information
• Single-Ended Voltage Range to • • • • • • • • • • • • •• +35V
• Differential Voltage Range to ••••••••••••••• +17.SV
• Designed to Provide OVer-Voltage Protection
• Fast Switching •••••••••••••••••••••• 6ns Rlaetlme
• Low Input Leakages of 1nA at +25°C Typical
• Low Input Capacitance of 3pF Typical
• An Array of 14 SCRIDlode Pelrs
Ordering Information
Applications
• MlcroprocessorlLoglc Input Protection
PART NUMBER
TEMPERATURE
SP720AP
-40°C to + 105°C
16 Lead Plastic DIP
PACKAGE
• Data Bus Protection
SP720AB
~to+105°C
16 Lead Plastic SOIC (N)
• Analog Device Input Protection
SP720ABT
-4QOC to +105°C
16 Lead Plastic SOIC
Tape and Reel
• Voltage Clamp
Pinout
Functional Block Diagram
Z
0(1)
SP720 (PDlP, SOIC)
i=!::
IN
v+
IN
IN
O~
wo
5 0g;
0:
c..
IN
IN
IN
IN
IN
IN
IN
v-
IN
CAUTION: These d""ic:es are sansnive to electrostatic: discharge. Users should Iollow proper I.C. Handling Procedures.
Copyright@Harrls Corporation 1993
8-5
File Number
2791.5
:
Specifications SP720
Absolute Maximum Ratings
Thermal Information
Continuous Supply Voltage, (V+) - (V-) ••••••••••••••••••• +35V
Input Peak Current, liN •••••••••••••••••••••••••••••••• ±2A
Transient Ratings - See Note 2, Figure 1, Table 1
Thermal Resistance
8JA
16 Lead PDIP Package ••••••••••••••••••••••••••• 90"CIW
16 Lead SOIC Package •••••••••••••••••••••••••• 170"CIW
Maximum Package Power Dissipation at +105"0:
Plastic DIP Package ••••••••••••••••••••••••••••• 500mW
Plastic SOIC Package •••••••••••••••••••••••••••• Z70mW
Storage Temperature Range •••••••••••••••••• -65"0 to +15O"C
Junction Temperature •••••••••••••••••••••••••••••• +15O"C
Lead Temperature (Soldering lOs) •••••••••••••••••••• +265°C
CAUTION: Str/lSSSS above those listed in "Absolulll Maximum RaUngs" may caUS6 permanent damage to the devIca. This is a str/lSS only raUng and operation
of the device at these or any other conditions above those indicated In the operational secUons of this specification Is not ImpHed.
Electrical Specifications
TA = -40°C to +105°C; VIN = 0.5Vcc Unless Otherwise SpecJfled
PARAMETER
SYMBOL
Operating Voltage Range,
VSUPPLY [(V+) - (V-)]
TEST CONDITIONS
VSUPPlY
=
=lA (Peak Pulse)
MIN
TYP
MAX
UNITS
-
4.5 to 30
-
V
2
2
-
V
V
Forward Voltage Drop:
IN to VIN toV+
VFWOL
VFWDH
--
Input Leakage Current
liN
-20
5
20
nA
IQUIESCENT
-
50
200
nA
Note 3
-
1.1
-
V
VFWrflFWD: Note 3
-
pF
liN
Quiescent Supply Current
Equivalent SCR ON Threshold
-
1
Input Capacitance
CIN
-
3
Input Switching Speed
IoN
-
6
Equivalent SCR ON Resistance
n
ns
NOTES:
1.
2.
3.
In automotive and battery operated systems, the power supply lines should be extemally protected for load dump and reverse battery.
When the V+ and V-pins are connected to the seme supply voltage source as the device or control line under protection, a current limiting
resistor should be connected in series between the supply and the SP720 pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically O.OlI1F or larger from the V+ and V- pins to ground are recommended.
For ESO testing of the SP720 to MIL-STO-3015.7 Human Body Model (HBM), the results are typically better than 6KV (Condfition 1)
(Figure 1, Table 1). Transient and ESO testing capability is highly dependent on the application. For conditions that are defined as an incircuit method of ESO testing where the V+ and V- pins have a return path to ground, the ESO capability Is typically greater than 15KV
from l00pF through 1.5Kn (Condition 2). For ESO testing of the SP720 to EIAJIC121 Machine Model (MM) standard, the results are
typically better than 1KV (Condition 4). These values were measured by AT&T ESO Lab using the component testing procedures of both
standards., Additional ESO testing for 200pF through 1.5Kn with 60s risetima was done with results better than 9KV (Condition 3).
Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance." These characteristics are given
here for thumb-rule information to determine peak current and dissipation under EOS conditions.
TABLE 1. ESD TEST CONDITIONS
RO
I
H.V.
SUPPLY
±Vo
;
TEST
1
IN
CD
±Vo
Ro
Co
Condition 1
6KV
1.5Kn
l00pF
(HBM)
Condition 2
15KV
1.5Kn
l00pF
(Mod.
HBM)
Condition 3
9KV
1.5Kn
200pF
(Mod.
HBM)
Condition 4
lKV
OKn
200pF
(MM)
OUT
-'-
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
MIL-STD-883D, METHOD 3015.7
8-6
SP720
100
80
1
....
zw
a:
a:
60
I
::>
0
a:
0
U'I
0
2.5
/
T,,_+2S"C
SINGLE PULSE
40
2
V
~
!Ew
a: 1.5
a:
::>
0
i
0
II.
20
o
800
_V
0
a:
I
EQUIV. SAT. ON
THRESHOLD -1.1V
II.
0.5
V
800
L
~
U'I
V
/
a:
T,,_+250C
SINGLE PULSE
1000
1200
o
o
lV
~
/
1 I
I
/
IFWD
VFWD
2
3
FORWARD SCR VOLTAGE DROP (V)
FORWARD SCR VOLTAGE DROP (mV )
FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE
INPUT
DRIVERS
OR
SIGNAL
SOURCES
Z
0(1)
i=!::
0::)
WO
I-a:
0a: 0
y
IN 8-15
IN 1-7
a..
V+
V-
SP720lNPUT
PROTECTION CIRCUIT
(1 OF 14 ON CHIP)
FIGURE 4. TYPICAL APPUCATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE Y+
OR LESS THAN -1VBE BELOW Y-
8-7
SP720MD-B, SP720MD
SP720MM-B, SP720MM
PRELIMINARY
High Reliability Electronic Protection Array
for ESD and Overvoltage Protection
April 1994
Features
Description
• The SP720MD-8 and SP720MM-8 are Harris Class B
"Equivalent" Parts with Back-End Conformance to
MII-Std-883 for Final Assembly, Electrical Testing,
Burn-In and QC Inspection
The SP720 is a High Reliability Array of SCRlDiode bipolar
structures for ESD and over-voltage protection to sensitive
input circuits. The SP720 has 2 protection SCA/Diode
device structures at each IN input. A total of 14 available IN
inputs can be used to protect up to 14 external signal or bus
lines. Over voltage protection is from the IN to V+ or V-. The
SeR structures are designed for fast triggering at a threshold of one +VeE diode threshold above V+ or at a -VeE diode
threshold below V-. From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to
a voltage level greater than one VeE above V+. A similar
clamp to V- is activated if a negative pulse, one VeE less
than V-, is applied to an IN input.
• ±2A Peak Current Capability
• Single-ended Voltage Range ••••••••••••••• to +35V
• Differential Voltage Range ••••••••••••••• to ±17.5V
• Designed to Provide Over-Voltage Protection
• Fast Switching •••••••••••••••••••••• 6ns Rlsetlme
• Low Input Leakages of 1nA at 25°C Typical
• Proven Interface for ESD
The SP720MD-8 and SP720MM-8 Class B "Equivalenr
Parts conform to Mil-Std-883 through final assembly, electrical test, burn-in and
Inspection. The SP720MD and
SP720MM are High Reliability Ceramic Packaged ICs.
• Military Temperature Range •••••••• -55°C to +125°C
Refer to Application Note AN9304 for further information.
Applications
Ordering Information
• Low Input Capacitance of 3pF Typical
ac
• An Array of 14 SCRlDlode Pairs
• Microprocessor/Logic Inpm Protection
PART
NUMBER
TEMPERATURE
RANGE
• Analog Device Input Protection
SP720MD-8
-55°C to +1250C
16 Lead Ceramic SBDIP
• Voltage Clamp
SP720MD
-5SOC to +125°C
16 Lead Ceramic SBDIP
SP720MM-8
-55°C to +125°C
20 Pad Ceramic LCC
SP720MM
-55°C to +1250C
20 Pad Ceramic LCC
• Data Bus Protection
Pinouts
PACKAGE
Functional Block Diagram
SP720MD (SBDIP)
SP720MM (CLCC)
TOP VIEW
TOP VIEW
IN
-., LiJ L~J L~j LtoJ LUlJ
~J
-.,
§J
-.,
!J
-,
IN !J
-,
v- !J
IN
(SP720MD)
IN
r-., r-, r-, r-., r-'
• II' '10' '11' '12' '13'
~
1i! 1i!
~
~
Copyright © Harris Corporation t994
File Number
8-8
3683
Specifications SP720MD-8, SP720MD, SP720MM-B, SP720MM
Absolute Maximum Ratings
Thermal Information
Continuous Supply Voltage, [(V+) - (V-)) .•••••••.••••••.•• +35V
Input Peak Current, liN (non-repetitive, < 1ms) ••.••••••.•••• ±2A
Max. DC Input Current, liN • . • . .. • • . . . .. • • .. .. • • • • ... t70mA
For ESD Transient Capability - See Note 2, Figure I, Table 1
Storage Temperature Range ..•.....••.••.••• -650 C to +15O"C
Junction Temperature •.••••..•.....•••••.•••••••. " +175°C
Lead Temperature (Soldering lOs). . . . • • . • . • • • • • . • • • • • +265°C
Thermal Resistance
9JC
14°CIW
Sidebraze DIP Package •••••••••••..•
19"CfN
Ceramic LCC ••••••••••••••••..••••
Package Power Dissipation:
Sidebraze DIP Package, up to +93"C .................. 1.0W
Ceramic LCC, up to +10500 ......................... 1.0W
Package Power Dissipation Derating Factor:
Sidebraze DIP Package, above +93°C ••••..•••••• 122mWI"C
Ceramic LCC, above +105°C ••••••...•••.••..•• 14.3mWI"C
CAUTION: Stresses abOIlll those listed In "Absolute Maximum Ratings" may cause permanent damage to the davies. This is • stress only lilting and opIIlIltion
of the device at these or any other condi/i""s aoollll those indicated in the opellltionai ssations of this specification is not irrfJlied.
Operating Conditions
Operating Voltage Range, Single Supply .•••••..•• +4.5V to +3OV
Operating Voltage Range, Split Supply ..•......•. ±225V to t15V
Typical Quiescent Supply Current ...................... 50nA
Operating Temperature Range ••••••.••••••••• -55°C to +125°C
Electrical Specifications TA = -55°C to +125°C; Unless Otherwise Specified
PARAMETER
SYMBOL
Operating Voltage Range
VSUPPlY
TEST CONDITIONS
MIN
TYP
MAX
UNITS
=[(V+) - (V-))
0
4.5
to 30
35
V
.
.
·2
-
V
+2
.
.
-
V
-
+1.5
V
-15
5
+15
nA
50
150
nA
1.1
-
VSUPPlY
Peak Forward/Reverse Voltage Drop
IN to V- (with V- Reference)
VIN • (V·)
liN
IN to V+ (with V+ Reference)
VIN • (V+)
liN
=-IA (Ims Peak Pulse)
=+IA (Ims Peak Pulse)
IN to V· (with V- Reference)
VIN • (V·)
liN
=·100mA to V·
IN to V+ (with V+ Reference)
VIN· (V+)
liN = +100mA to V+
DC Forward/Reverse Voltage Drop
Input Leakage Current
=30V
V- < VIN < V+, VSUPPlY =30V
V- < VIN < V+, VSUPPLY
liN
Quiescent Supply Current
IoUIESCENT
Equivalent SCR ON Threshold
Note 3
Equivalent SCR ON Resistance
VFWriIFWO (Note 3)
Input Capacitance
CIN
Input Switching Speed
ioN
·1.5
-
-
-
1
3
6
V
V
0
pF
nS
NOTE:
Z
0(1)
1. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery.
When the V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting
resistor should be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within
the rated maximum limits. Bypass capacitors of typically O.ot I1F or larger from the V+ and V- pins to ground are recommended.
2. For ESD testing of the SP720 to MIL·STD 883, Method 3015.7, Human Body Model (HBM), the results are typically better than 6KV (Con·
dltion 1). Transient and ESD capability Is highly dependent on the application. For conditions that are defined as an in-circuit method of
ESD testing where the V+ and V· pins have a return path to ground, the ESD capability Is typically greater than 15KV from 100pF through
1.5 KO (Condition 2). For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than
lKV (Condition 4). These values were measured by AT&T ESD Lab using the component testing procedures of both standards. Addl·
tional ESD testing for 200pF through 1.5 KO with 6ns risetime was done with results better than 9KV (Condition 3).
3. Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance". These characteristics are given
here for thumb-rule information to determine peak current and dissipation under EOS conditions.
-l-
t>w=>
1- 0
Oe:
a: 0
D.
TABLE 1. ESD TEST CONDITIONS
RO
TEST
1
I
H.V.
Co
SUPPLY
IN
OUT
±Vo
"':'
FIGURE 1_ ELECTROSTATIC DISCHARGE TEST
MIL-STD-BB3D, METHOD 3015.7
8-9
tVo
Ro
Condition 1
6KV
1.5KO
i
Co
l00pF
(HBM)
Condition 2
15KV
1.5KO
l00pF
(Mod. HBM)
Condition 3
9KV
1.5KO
200pF
(Mod. HBM)
Condition 4
lKV
OKO
200pF
(MM)
I
SP720MD-8. SP720MD. SP720MM-8. SP720MM
100
TA,,2S0C
SINGLE PULSE
80
/
C'
.5.
~
z
w 60
a:
a:
(.)
a:
(.)
Q
a:
i...
2
/
/
::>
-
w:::)
1- 0
Oe:;
a: 0
0.
I'
!.
I,
8-13
SP721
Electronic Protection Array
for ESD and Overvoltage Protection
April 1994
Features
Description
• ±2A Peak Current Capability
The SP721 is an array of SCA/Diode biploar structures for
ESD and Overvoltage protection to sensitive input circuits.
The SP721 has 2 protection SCRlDiode device structures
per input. There are a total of 6 available inputs that can be
used to protect up to 6 external signal or bus lines. Over
voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to
V+orV-.
• Single-Ended Voltage Range •••••••••••••• to +35V
• Differential Voltage Range ••••••••••••••• to ±17.5V
• Designed to Provide Overvoltage Protection
• Fast Switching •••••.••••••••••••.••• 6ns Risetime
• Low Input Leakages of 1nA at +2SoC Typical
• Low Input Capacitance of 3pF Typical
• An Array of 6 SCRlDlode Pairs
• Proven Interface for ESD
• Operating Temperature Range •••••• -400 Cto+10SoC
The SCR structures are designed for fast triggering at a
threshold of one +VBE diode threshold above V+ (Pin 8) or a
-VBE diode threshold below V- (Pin 4). From an IN input, a
clamp to V+ is activated if a transient pulse causes the input
to be increased to a voltage level greater than one VBE
above V+. A similar clamp to V- is activated if a negative
pulse, one VeE less than V-, is applied to an IN input.
Further information is available in Application Note AN9304.
AN9304 applies to both the SP720 and SP721
Applications
• Microprocessor/Logic Input Protection
Ordering Information
• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp
PART NUMBER
TEMPERATURE
RANGE
SP721AP
-40"C to +1 05°C
8 Lead Plastic DIP
SP721AB
-40"C to +1 05°C
8 Lead Plastic SOIC (N)
SP721ABT
-40"C to +1 050 C
8 Lead Plastic SOIC
Tape and Reel
PACKAGE
Functional Block Diagram
Pinout
SP121 (PDIP, SOIC)
TOP VIEW
,CAUTION: These devices are sensnlve to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @Harris Corporation t 994
8-14
File Number
3590.1
Specifications SP721
Absolute Maximum Ratings
Thermal Information
Continuous Supply Voltage. (V+) - (V-) ••••••.••••••••..•. +35V
Input Peak Current. liN •••••••.•.••••••.••••••••••••••• ±2A
ESD Transient Ratings - See Note 2. Figure 1. Table 1
8JA
Thermal Resistance.
8 Lead DIP Package •••••••••••••••••...••.•.••• 1300 em
8 Lead SOIC Package •••••••••••••••••••••••.••• 1700c1W
Maximum Package Power Dissipation
8 Lead Plastic DIP Package. Up to +l05°C ••••• " •••• 350mW
8 Lead Plastic SOIC Package. Up to +105°C
270mW
Storage Temperature Range •••••••••••••••.•• -65OC to +150°C
Junction Temperature •••••.••.•••••••••••••••••.••. +150°C
Lead Temperature (Soldering lOs) ••••••••••.••••••••• +265°C
CAUTION: Stress... abo"" Ihos8 listed In "'Abso/UIB Maximum Ratings' may cause permanent damage to the davies. This Is • stress only rating and operation
of /he device at /h...e or any other conditions abo"" /hose Indicated in the operational sections of /his specification Is not ImpDeti.
Electrical SpeCifications
TA = -40OC to +1050 C. VIN = 0.5Vcc Unless Otherwise Specified
PARAMETERS
SYMBOL
Operating Voltage Range.
VSUPPlY = [(V+) - (V-))
TEST CONDITIONS
VSUPPlY
Forward Voltage Drop
IN to VIN toV+
VFWDL
VFWDH
Input Leakage Current
IQUIESCENT
Equivalent SCR ON Threshold
Note 3
Equivalent SCR ON Resistance
VFWoliFWo ; Note 3
TYP
MAX
UNITS
-
4.5 to 30
-
V
-
V
-
liN = 1A (Peak Pulse)
liN
Quiescent Supply Current
MIN
2
2
-20
5
+20
nA
-
50
200
nA
1.1
-
V
1
-
n
Input Capacitance
CIN
-
3
-
pF
Input Switching Speed
IoN
-
6
-
ns
NOTES:
1. In automotive and battery operated systems. the power supply lines should be externally protected for load dump and reverse battery.
When the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection. a current limiting
resistor should be connected In series between the external supply and the SP721 supply pins to limit reverse battery current to within
the rated maximum limits. Bypass capacitors of typically O.OlI1F or larger from the V+ and V- Pins to ground are recommended.
2. For ESD testing of the SP721 to MIL-STD 883. Method 3015.7. Human Body Model (HBM). the results are typically better than SkV (Condition 1) (Figure 1. Table 1). Transient and ESD capability Is highly dependent on the application. For conditions that are defined as an
in~ircuit method of ESD testing where the V+ and V- Pins have a return path to ground. the ESD capability is typically greater than 15kV
from 100pF through 1.5kO (Condition 2) or 9kV from 200pF through 1.5kO (Condition 3). For ESD testing of the SP721 to EIAJ IC121
Machine Model (MM). the results are typically better than 1kV (Condition 4).
3. Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance". These characteristiCs are given
here for thumb-rule information to determine peak current and diSSipation under EOS conditions.
I
H.V.
SUPPLY
±Vo
...
TABLE 1. ESD TEST CONDITIONS
RO
rCo
1
TEST
±VO
Ro
Co
Condition 1
SkV
1.5kO
l00pF
(HBM)
Condition 2
15kV
1.5kO
100pF
(Mod.
HBM)
Condition 3
9kV
1.5kO
200pF
(Mod.
HBM)
Condition 4
lkV
OkO
200pF
(MM)
IN
DUT
-=:
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
MIL-STD-883D. METHOD 3015.7
8·15
Z
0(1)
-I-
tis
WO
I-a::
0a:: 0
Q.
SP721
100
80
C
.5.
...z
w
II:
II:
60
::>
()
II:
li!
Q
I...
40
/
/
20
o
600
-V
2.5
/
TA-+26°C
SINGLE PULSE
/
2
V
g
...z
w
II:
II:
1.5
..
II:
()
/
Q
II:
i...
1200
e-nm]bI
EQUIV. SAT. ON
0.5
1000
/1
U
/
800
TA-+2SOC
SINGLE PULSE
0
1/
IFWD
VFWD
1I
2
FORWARD SCR VOLTAGE DROP M
0
FORWARD SCR VOLTAGE DROP (mV)
FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
~
3
FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE
+Vcc
INPUT
DRIVERS
OR
SIGNAL
SOURCES
T
IN 1·3
IN5·7
V+
SP721
V·
SP721 INPUT PROTECTION CIRCUIT (1 OF 14 ON CHIP)
(PINOUT CONRGURATION SHOWN FOR 8 PIN PACKAGES)
FIGURE 4. TYPICAL APPUCATION OF THE SP721 AS AN INPUT CLAMP FOR OVERVOLTAGE, GREATER THAN W BE ABOVE V+
OR LESS THAN ,WBE BELOW V·
8·16
INTELLIGEN
I--
POWERICs
9
MULTIPLEX COMMUNICATION CIRCUITS
PAGE
MULTIPLEX COMMUNICATION CIRCUITS SELECTION GUIDE .............................. . . . . . .
9-2
MULTIPLEX COMMUNICATION CIRCUITS DATA SHEETS
CDP68HC68S1
Serial Bus Interface. . . . . . . . • . . . . . • . • . . . . • . • . • . . • • . . . . • • • • . . . . • . . . . . . . . . . .
9-3
HIP7010
J1850 Byte Level Interface Circuit. . . . . . • . . . . . . . . • . . . . . . . . . • . . • . . . . . . . . . . . • • .
9-17
HIP7020
J1850 Bus Transceiver I/O for Multiplex Wiring. . . • . . . . . • . . . • . . . • • . . . • . . . . . . . . . •
9-33
HIP7030AO
J1850 8-Bit 68HC05 Microcontroller Emulator Version. • . .. . • • .• . • • •. ••. . . • • . .. ••
9-40
HIP7030A2
J1850 8-Bit 68HC05 Microcontroller. . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . •
9-50
HIP7038A8
J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version. • • . . . • . . . . . . . . • . . . . . . .
9-99
~
)(-
w::::l
...1 0
e.g;
-0
~.
::::I::E
::E::E
o
o
9-1
Multiplex Communication Circuits Selection Guide
PART
NUMBER
DESCRIPTION
APPUCATIONS
SUPPLY
VOLTAGE
TEMPERATURE
PACKAGE
CDP68HC68S1
SPI Serial Bus Interface with
COllision Detection and Arbitration
CCD Bl16-Bit Serial
Bus
3Vt06V
-40"C to +1 OSoC
14 Lead PDIP
and 20 Lead
SOIC
HIP7010
J1850 Byte Level Interface Circuit
J18S0 Class B
Variable Pulse Width
(VPW)
3Vto 6V
-40"C to +12SoC
14 Lead PDIP
andSOIC
HIP7020
J18S0 Bus Transceiver VO for
Multiplex Wiring
J18S0 Class B
Variable Pulse Width
(VPW)
6Vt024V
-4O"C to +12SoC
8 Lead PDIP
and 8 Lead
SOIC
HIP7030AO
J 18S0 8-Bit 68HCOS
Mlcrocontroller Emulator Version
J18S0 Class B
Variable Pulse Width
(VPW)
3Vto 6V
-4OOC to +12SoC
68 Lead PLCC
HIP7030A2
J1850 8-Bit 68HCOS
Microcontroller
J18S0 Class B
Variable Pulse Width
(VPW)
3Vlo 6V
-4OOC to +12SoC
28 Lead PDIP
and 28 Lead
SOIC
HIP7038A8
J1850 8-Blt 68HCOS MicrocontroUer 8K EEPROM Version
J1850 Class B
Variable Pulse Width
(VPW)
SV
-4O"C to + 12SOC
28 Lead
Ceramic SOIC
Flatpack
9-2
CDP68HC68S1
HARRIS
SEMICONDUCTOR
Serial Bus Interface
April 1994
Features
Description
• Differential Bus for Minimal EMI
The CDP68HC6SS1 Serial Bus Inteiface Chip (SBIC) provides
a means of inteifacing in a Small Area Network configuration,
various microcomputers (MCU's) containing serial ports. Such
MCU's include the family of 68HC05 microcontrollers. The SBIC
provides a connection from an MCU's Serial Communication
Intertace (asynchronous UART type inteiface) or Serial Peripheral Intertace (synchronous) to a medium speed asynchronous
two wire differential Signal bus designed to minimize electromagnetic interference. This two wire bus forms the network bus
to which all MCU's are connected (through SBI chips). See Figure 1. Each MCU operates independently and may be added or
deleted from the bus with little or no impact on bus operation.
Such a bus is ideal for inter-microcomputer communication in
hazardous electrical environments such as automobiles, aircraft
or industrial control systems.
• High Common Mode Noise Rejection
• Ideal for Twisted Pair Wiring
• Data Collision Detection
• Bus Arbitration
• Idle Detection
• Programmable Clock Divider
• Power-On Reset
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
COP68HC68S1E
-40oC to +1OsoC
14 Lead POIP
COP68HC68S1M
-40OC to +1OSoC
20 Lead SOIC fY'J)
In addition to acting as bus arbitor and inteiface for microcomputer SCI port to differential bus communication, the
CDP68HC68S1 contains all the circuitry required to convert
and synchronize Non-Return-to-Zero (NRZ) 8-bit data received
on the differential bus and clock the data into a microcomputer's
SPI port. Likewise, data to be sent by a microcomputer's SPI
port is converted to asynchronous format by appending start
and stop bits before transmitting to other microcomputers.
Refer to the data sheet for the CDP68HC05C4 for additional
information regarding CDP68HC05 microcomputers and their
Serial Communications and Serial Peripheral Inteifaces.
The CDP68HC68S1 is supplied in a 14 lead dual-in-line plastic
package (E suffix), and in a 20 lead small outline plastic package (M suffix).
Operating voltage ranges from 4V to 7V and operating temperature ranges from -40°C to +105°C.
~
>
....1 0
-0
o..e:
~.
=>2
22
oo
HIP7010
For enhanced noise immunity, the ClK input is a CMOS Schmitt
trigger input. See Electrical Specifications for input levels.
VPWOUT (Variable Pulse Width Out· Output).
VPWiN (Variable Pulse Width In • Input)
These two lines are used to interface to a J1850 bus transceiver, such as the Harris HIP7020. VPWOUT is the variable
pulse width modulated output of the HIP7010's symbol
encoder circuit. VPWiN is the inverted input to the symbol
decoder of the HIP7010. VPWiN is a schmitt input.
SIN (Serial In • Input).
SOUT (Serial Out· Output).
SCK (Serial Clock· Output).
SACTIVE (Serial Bus Active· Output)
These four lines constitute the synchronous Serial Interface
(SERIAL) interface of the HIP7010. See the Serial Interface
(SERIAL) System for details. SIN, SOUT, and SCK provide
the three principal connections to the Host controller. SIN is a
CMOS input. SOUT and SCK are three-state outputs which
are only activated during serial transfers. The SIN, SOUr, and
SCK pins contain integrated pull-down load devices which
provide termination on the bus whenever it is in a high impedance state. The SACi'iVE pin is a CMOS output, which pulls
low when the HIP7010 is communicating on the serial bus.
See Serial Interface (SERIAL) System and Applications
Information for more details.
RDY (Byte Ready· Input)
The Byte Ready (ROY) line is a "handshaking" input from the
Host. Each rising edge on the ROY pin signifies that the Host has
loaded a byte into its SERIAL transmit register and the HIP7010
can retrieve it (by generating clocks on SCK) when the HIP7010
is ready for the data. See Serial Interface (SERIAL) System
and Applications Information for more details.
The ROY pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
ii5IE (Idle/Service Request - Output)
In general a Status/Control byte transfer should be performed
each time ii5"LE goes low. See Effects of Resets and Power·
Down and Applications Information for more details.
The i"i5"CE pin is an active low CMOS output. See Operation
of the HIP7010 for more details.
STAT (Request Status/Control - Input)
The Request Status/Control (STAT) input pin is used by the
Host microcontroller to inijiate an exchange of the Host's control byte and the HIP7010's status byte. A low to high transition on the STAT input signals the HIP7010 that the Host has
placed a control word in it's SERIAL output register and is
ready to exchange ij with the HIP7010's status word. The
HIP7010 controls the exchange by generating the 8 SCKs
required. See Serial Interface (SERIAL) System and Applications Information for more details.
The STAT pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
"Fi"Effi (Reset· Input)
The RESET input is a low level active input, which resets the
HIP7010. Resetting the HIP7010 forces SACTIVE high, disables the SOUT and SCK pins, forces the VPWOUT output
low, drives i"i5"CE high, and returns the internal state machine
to its initial state. Following reset, the HIP7010 is inhibited
from transmitting or receiving J1850 messages until a Status/Control Register transfer has been completed (see
Effects Of Resets And Power-Down for more details).
The HIP7010 is also reset during initial power-on, by an
internal power-on-reset (POR) circuit.
loss of a clock on the ClK input will cause a reset as
described previously under elK.
If not used, the"Fi"Effi pin should be tied to Voo.
For enhanced noise immunity. the ClK input is a CMOS Schmitt
trigger input. See Electrical Specifications for input levels.
TEST (Test Mode· Input)
The IDLE output pin indicates that the J1850 Bus has been
in a passive state for at least 300/ls and is now idle. If the
bus has been passive for a minimum of 239/ls and another
node initiates a new message, IDLE will pulse low for 1/ls.
In its role as a Service Request pin, a reset forces i"i5"CE
high. Following the reset, IDLE remains high for 17 ClK
cycles and is then driven low. IDLE will remain low until 40
ClK cycles +1.5/ls after completion of the first Status/Control byte transfer. The i"i5"CE pin will then resume its normal
role, remaining high until a 300J.ls lull (or 239J.ls plus a passive to active transition) has been detected on the J1850
bus. This provides a handshake mechanism to ensure the
Host will reinitialize the HIP7010 each time the HIP7010 is
reset via POR, RESET, or Slow Clock Detect.
If IDLE is low when an echo failure causes the ERR bit to be
set in the Status byte, the i"i5"CE pin will pulse high for 2/ls
and then return low (see Status/Control Register).
If IDLE is low when the host sets the NXT bit in the control
byte, the IDLE pin will pulse high for 2J.ls and then return low
(see Status/Control Register).
The TEST input provides a convenient method to test the
HIP7010 at the component level. Raising the TEST pin to a
high level causes the HIP7010 to enter a special TEST mode.
In the TEST mode, a special portion of the state machine is
activated which provides access to the Built~in-Test and diagnostic capabilities of the HIP7010 (see Test Mode for more
detailS).
The TEST pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected. In many
applications the TEST pin will be left unconnected, to allow
access via a board level ATE tester.
J1850 VPW Messaging
This section provides an introduction to J1850 multiplexed
communications. It is assumed that the user is or will
become familiar with the appropriate documents published
by the Society of Automotive Engineering (SAE). The following discussion is not comprehensive.
9-22
HIP7010
Overview
The SAE Recommended Practice J1850 (Note 1) (J1850)
establishes the requirements for communications on a Class
B multiplexed wiring network for automotive applications.
The J1850 document details the requirements in a three
layer description which separately specifies the characteristics of the physical layer, the data link layer, and the application layer. There are several options within each layer which
allows vehicle manufacturers to customize the network while
still maintaining a level of universality.
NOTE:
1. SAE Recommended Practice J1850. Class B Data CommunIcation Network Interface. September 1, 1993, Society of Automotive Engineers Inc.
The hardware of the Harris HIP7010 provides features which
facilitate implementation of the 10.4Kbps Variable Pulse
Width Modulated (VPW) physical layer option of J1850. In
combination with a bus transceiver, such as the Harris J 1850
Bus Transceiver HIP7020, and appropriate software algorithms the HIP7010 circuitry enables the designer to completely
implement
a
10.4Kbps VPW
Class
B
Communications Network Interiace per J1850. Features of
such an implementation include:
•
•
•
•
•
•
•
•
•
Single Wire 10.4Kbps Communications
Bit-by-Bit Bus Arbitration
Industry Standard Protocol
Message Acknowledgment ("In-Frame Response") Capabilities
Exceptionally Tolerant of Clock Skew, System Noise, and
Ground Offsets
Meets CARB and EPA Diagnostic Requirements
Supports up to 32 Nodes
Low Error Rates
Excellent EMC Levels (when Interfaced via Harris J1850
Bus Transceiver HIP7020)
nodes are connected to the bus as a "wired-OR" network in
which the bus is high if anyone (or more) node is generating
an active output. The bus is only low when no nodes are generating active outputs. It follows that, when no communications are taking place the bus will rest in the passive state. A
message begins when the bus is first driven to the high state.
Each succeeding state transition (i.e. - a change from active to
passive or passive to active) transfers one bit of information
(symbo~ until the message is complete and the bus once
again rests at the passive state. The interpretation of each
symbol in the message is dependent on its duration (and
state), hence the descriptor Variable Pulse Width (VPW).
Each message has a beginning and an end. the span of
which encompasses the entire message or frame (refer to
Figure 3). A frame consists of an active start of frame (SOF)
symbol and a passive end of frame (EOF) symbol sandwiched
around a series of byte sized (8-bit) groups of symbols. The
first byte of the frame contents is always a header byte, followed by possibly additional header bytes, followed by one or
more data bytes, followed by an integrity check byte (CRC
byte), followed by a passive end of data (EOD) symbol, followed by possibly one or more in-frame-response (IFR) bytes.
To keep waiting times low, messages are limited to 12 bytes
total (including header, data, check, and IFR bytes). All message bytes are transmitted most significant bit (MSB) first.
VPW Symbol Definitions
Within the J1850 scheme, symbols are defined in terms of both
duration and state (passive or active). The duration is measured as the time between successive transitions. There is one
transition per symbol and one symbol per transition. The end of
one symbol marks the beginning of the next. Since the bus is
passive when a message begins and must return to that same
state when the message completes, all frames have an even
number of transitions and hence an even number of symbols.
In addition to the standard J1850 features, the HIP7010 hardware provides a high speed mode, (intended for receive only
use) which can significantly enhance vehicle maintenance
capabilities. The high speed mode provides a 41.6Kbps communications path to any node built with the HIP7010.
Anatomy of a J1850 VPW Message
All messages in a J1850 VPW system are sent along a single
wire, shared bus. At any given moment the bus can be in
either of two states: active (high) or paSSive (low). Muttiple
There are unique definitions for data bit symbols (all the symbols which occur within the header, data, and check bytes) and
protocol symbols (including SOF. EOD, and EOF). The duration
of each symbol is expressed in terms of VPW Tuning Pulses
(TV values). Table 1 summarizes the TV definitions. Each TV is
specified in terms of a nominal (or ideal) duration and a minimum and maximum duration. The span between the minimum
and maximum limits accommodates system noise sources
such as node to node clock skew, ground offsets, clock jitter,
and electromechanical noise. There are no dead zones
between the maximum of one TV and the minimum of the next.
FIGURE 3. TYPICAL J1850 VPW MESSAGE FRAME
9-23
~
>239
280
NA
IFS (Inter-Frame Separation)
Passive TV6
TV5
>239
300
NA
IDLE (Idle Bus)
Passive>TV6 Nominal
TV6
>280
300
NA
NB (Normalization Bit)
ActiveTV1 or Active TV2
BRK(Break)
Active TV5
MINIMUM
NOMINAL
MAXIMUM
Illegal
0
NA
TV1
>34
64
TV2
>96
128
TV3
>163
TV4
VPW is a non-return-to-zero (NRZ) protocol in which each
transition represents a complete bit of information. Accordingly, a 0 data bit will sometimes be transmitted as a passive
pulse and sometimes as an active pulse. Similarly, a 1 data
bit will sometimes be transmitted as a passive pulse and
sometimes as an active pulse. In order to accommodate
arbitration (see Bus Arbitration) a long active pulse represents a 0 data bit and a short active pulse represents a 1
data bit. Complementing this fact, a short passive pulse represents a 0 and a long passive pulse represents a 1. Starting
from a transition to the active state, a 0 data bit will maintain
the active level longer than a 1. Similarly, starting from a
transition to the passive state, a 0 data bit will return to the
active level quicker than a 1. These facts give rise to the
dominance of O's over 1's on the J1850 bus as depicted in
Figure 4. See Bus Arbitration for additional details.
SYNCHRONIZED
t
o
DATA
1 DATA
BIT~FL
BIT~~
J1850 BUS ~
~
0
LONGER ACTIVE
~PULSE(O)
CONTROLS THE BUS
FIGURE 4A. DOMINANCE OF ACTIVE 0 DATA BIT
SYNCHRONIZED
o DATA
1
DEFINITION
o Data
TVID
DATA
BIT
BIT
J1850 BUS
t
IFRs can consist of multiple bytes from a single respondent,
one byte from a single respondent, or one byte from multiple
respondents. In all cases the first response byte must be preceded by a nonnalization bit (NS) which serves as a stan of
response symbol and places the bus in an active state so that
following the IFR byte(s) the bus will be left in the passive state.
The NB symbol is by definition active, but can be either TV1
or TV2 in duration. The long variety (TV2) signifies the IFR
contains a CRC byte. The short variety (TV 1) precedes an
IFR without CRC.
Messages are classified into one of four Types according to
whetherthe message has an IFR and what kind of IFR it is.
The definitions are:
~~
• Type 0 - No IFR
~~ SHORTER PASSIVE
~PULSE(O)
CONTROLS THE BUS
FIGURE 4B. DOMINANCE OF PASSIVE 0 DATA BIT
FIGURE 4.
The distinction between two of the passive symbols, EOD and
EOF, is subtle but important (refer to Figure 5). The EOD (TV3)
interval signifies that the originator of the message is done
broadcasting and any nodes which have been requested to
respond (I.e. - to acknowledge receipt of the message) can now
do so. The EOD interval begins when the transmitting node has
completed sending the eighth bit of the check byte. The transmitter simply releases the bus and allows it to revert to a passive state. In the course of normal messaging, no node can
seize the bus until an EOD time has been detected. Once an
EOD has elapsed, any nodes which are scheduled to produce
an IFR will arbitrate for control of the bus (see Bus Arbitration)
and respond appropriately. If no responses are forthcoming the
bus remains in the passiw state until an EOF (TV4) interval
has elapsed. After the EOF has been generated, the frame is
considered closed and the next communications on the bus will
represent a totally new message.
Message Types
~~
o
In Frame Response (IFR)
• Type 1 - One byte IFR from a single respondent
(no CRC byte)
• Type 2 - One byte IFRs from multiple respondents
(no CRC byte)
• Type 3 - Multiple byte IFR from a single respondent
(CRC appended)
9-24
HIP7010
Bus Arbitration
The nature of multiplexed communications leads to contention
issues when two or more nodes attempt to transmit on the bus
simultaneously. Within J1850 VPW systems, messages are
assigned varying levels of priority which allows implementation of an arbitration scheme to resolve potential contentions.
The specified arbitration is performed on a symbol by symbol
basis throughout the duration of every message.
Arbitration begins with the rising edge of the SOF pulse. No
node should altempt to issue an SOF until an Idle bus has
been detected (Le. - an Inter-Frame Separation (IFS) symbol
with a period of TVS has been received). If multiple nodes are
ready to access the bus and are all waiting for an IFS to
elapse, invariable skews in timing components will cause one
arbitrary node to detect the Idle condition before all others and
start transmission first. For this reason, all nodes waiting for
an IFS will consider an IFS to have occurred if either:
1. An IFS nominal period has elapsed
or
2. An EOF minimum period has elapsed anda rising edge
has been detected
Arbitrating devices will all be synchronized during the SOF.
Beginning with the first data bit and continuing to the EOF,
every transmitting device is responsible for verifying that the
symbol it sent was the symbol which appeared on the bus.
Each tranSition, every transmitting node must decode the
symbol, verify the received symbol matches the one sent, and
begin timing of the next symbol. Since timing of the next symbol begins with the last trans~ion detected on the bus, all
transm ilters are re-synchronized each symbol. When the
received symbol doesn't match the symbol sent, a conflict (bit
collision) occurs. Any device detecting a collision will assume
it has lost arbitration and immediately relinquish the bus. Typically, after losing arbitration, a device will attempt retransmission of the message when the bus once again becomes idle.
I SOF I
HEADER • • • • DATA N
The definition of 1 and 0 data bits (see Table 2 and discussion
under VPW Symbol Definitions) leads to O's having priority
over 1's in this arbitration scheme. Header bytes are generally
assigned such that arbitration is completed before the first
data byte is transmitted. Because of the dominance of 0 bits
and the MSB first bit order, a header with the hexadecimal
value $00 will have highest priority, then $01, $02, $03, etc.
An example of two nodes arb~rating for control of the bus is
shown in Figure S.
Arbitration also takes place during the IFR portion of a message, if more than one node is attempting to generate a
response. Arbitration begins with the NB symbol, which follows the EOD and precedes the first IFR byte.
For Type 1 and Type 3 messages only, the respondent which
successfully arbitrates for control of the bus produces an IFA.
All other respondents abort their IFRs.
For Type 2 messages, all respondents which lose arbitration
must count symbols and re-attempt transmission at the end of
each byte. Each node, which successfully responds, eliminates itself from the subsequent arbitration until all nodes
have responded. This arbitration scheme limits each respondent to a single byte during a Type 2 IFA.
Break
To force a message to be aborted before EOF is reached, a
break (BRK) symbol can be transmitted by any node. The
BRK symbol is an active pulse of duration TV5. Reception of a
break causes all nodes to reset to a ready-to-receive state
and to re-arbitrate for control following an IFS.
HIP7010 Architectural Overview
The HIP7010 consists of three major functional blocks: the
Serial Interface System (SERIAL) block; the State Machine
(STATE) block; and the Symbol Encoder/Decoder (SENDEC)
block. Transfers between the Host and the HIP7010 are controlled by the SERIAL block, while transfers between the
J1850 bus and the HIP7010 are handled by the SENDEe
I It
CRC
EOD
~
I II
liN FRAME RESPONSE
NB
EOD
EOF
FIGURE 5. J1850 MESSAGE WITH IN-FRAME-RESPONSE
TRANSMITTER
TRANSMITTER
A
--'S---~
B
--,.~s----~I
nor;1o~________________
-COWSION DETECTED BY B _____________________
~v~'I
~t;~s
J1850 BUS
IIFS
ISOFI
HEADER
I
DATA 1 • • • DATA N
I
FIGURE 6. TWO NODES ARBITRATING FOR CONTROL OF J1850 BUS
9-25
CRC
I EOF I
f!?
)(-
w::::l
..J~
0.._
-0
~.
::::I::!i
::!i::!i
oo
HIP7010
block. The STATE block controls the flow of all data between
the SERIAL and SENDEC blocks. The STATE block also controls HostIHIP7010 handshaking, automatic J1B50 bus arbitration, break recogn~ion, CRC checking, and many other
features. In addition to the three major blocks the HIP7010
includes CRC generator/checker hardware, a Status/Control
Register, and a Timing generator.
Timing Generator
The timing generator, as its name suggests, generates all
internal timing pulses required for the SERIAL, SENDEC,
STATE, and CRC circuits. The ClK input pin is appropriately
divided to produce an internal 2MHz clock which resuRs in a
lMHz SERIAL transfer rate and VPW J1BSO symbol timing
with 11ls accuracy. The ClK pin of the HIP7010 can be driven
with a variety of common microcontroller frequencies. Frequency selection is accomplished via three bits in the Status/
Control register. See Status/Control Register for more
details.
The Serial Interface (SERIAL) System
Overview
The SERIAL system handles all interface between the Host
microcontroller and the HIP7010. The SERIAL system is
designed to interface directly with the Serial Peripheral Interface (SPI) systems of the Harris CDP6BHC05 family of microcontrollers. Identical interfaces are found on the 6BHC11 and
HC16 families. Compatible systems are found on most popular microcontrollers.
Serial data words are simultaneously transmitted and
received over the SOUT/SIN lines, synchronized to the SCK
clock stream. The word size is fixed at B·bits. A series of
eight clocks is required to transfer one word. With the exception of Status/Control Register transfers (described later), all
SERIAL transfers use a single eight bit shift register within
the HIP7010. The serial bits are "shifted ouf' on the SOUT
pin, most significant bit (MSB) first, from the shift register. As
each bit shifts out one end of the shift register, the data on
the SIN input pin is, usually, shifted into the other end of the
same shift register. After eight clocks, the original contents of
the shift register have been entirely transmitted on the SOUT
pin and replaced by the byte received on the SIN pin.
Most Host micros which include a synchronous serial interface, operate their interface in a manner compatible with the
HIP7010s implementation. The resuR of each B-bit SERIAL
transfer is that the contents of the HIP7010s shift register
and the Host's shift register have effectively been "swapped".
SERIAL Bus nmlng
The SCK output of the HIP7010 is used to synchronize the
movement of data both into and out of the device on its SIN
and SOUT lines. As stated above, the Host and the HIP701 0
are capable of exchanging a byte of Information during a
sequence of eight clocks generated on the SCK pin. The
relationship between the clock signal on SCK and the data
on SIN and SOUT is shown in Figure 7.
Approximately 7500s prior to each series of eight clocks, the
SACTIVE output of the HIP7010 is driven low. SACTIVE
remains low until a minimum of 1200ns after the last clock
transition. When interfacing to a CDP6BHC05 SPI compatible
Host, the SACTIVE output would normally be connected to
the SS input of the Host. The trailing edge of the SACTIVE
Signal can also be used as a flag to Hosts which don't automatically recognize the transfer of a serial byte.
The quiescent state of SCK is low. Once a transfer is initiated, the
rising edge of each SCK pulse places the next b~ on the SOUT
line and the failing edge is used to latch the bit input on SIN.
The Host must adhere to this same timing, by meeting the input
setup time requirements of SIN valid before the trailing edge of
SCK (see Electrical Specification for details) and latching
the SOUT data on the same edge. When interfacing the
HIP7010 to a CDP6BHC05 SPI compatible Host, the SPlinterface should be programmed with CPHA 1 and CPOl o.
=
At all times, other than during an actual SERIAL transfer
between the HIP7010 and its Host, the SCK and SOUT pins
are held in a high impedance state. This allows other devices
connected to the Host via the SERIAL bus to be accessed
when the HIP7010 is not transferring data. Utilization of the
SERIAL bus by the HIP7010 is less than 5%, leaving signifIcant bandwidth for other transfers. When held in the high
impedance state, a pair of integrated pull-down devices on the
SCK and SOUT pull the pins to ground, if they are not driven
by another source. See Applications Information for a
detailed discussion of SERIAL bus utilization.
\~------------------~I
SCK
=
SCK NORMALLY LOW
SOUT
SIN
MSB
6
5
4
3
2
LSB
I
I
I
I
I
I
I
INTERNAL STROBE FOR LATCHING DATA IN HIP7010
FIGURE 7. SERIAL BUS TIMING
9-26
HIP7010
SERIAL Bus Transfers
The HIP7010 is always configured as a SERIAL "master". As
a master, the HIP7010 generates the transfer-synchronizing
clock on the SCK pin, transmits data on the SOUT pin, and
receives data on the SIN pin.
Whenever the HIP7010 receives a complete byte from the
J 1850 bus via the iJPWiiij line, it automatically initiates an
unsolicited SERIAL transfer. The unsolicited transfer transmits the received (or reflected) byte to the Host and, if in the
midst of transmitting a message, retrieves the next byte from
the Host. While these unsolicited transfers are, strictly
speaking, asynchronous to the Host's activities, there are
well defined rules which govern the minimum time between
unsolicited transfers (i.e. - no two unsoliCited transfers can
occur in less time than it takes to transfer one J 1850 byte (8
x 64
512f.1s). See Applications Information for more
details.
=
In addition to the unsolicited transfers which are based on
receipt of incoming J1850 messages, the Host can initiate
certain transfers in a more synchronous fashion. Handshaking between the Host and the HIP7010 is provided by the
8yte Ready (RDY) and Request Status (STAT) pins. These
two pins are driven by the Host and trigger the HIP7010 to
initiate one of the two, unique, solicited SERIAL transfers.
The 8yte Ready (RDY) line is the first of two handshaking
inputs from the Host. Each rising edge on the RDY pin signifies that the Host has loaded a byte into its serial transm it
register and the HIP7010 can retrieve it. If the J1850 bus is
available (i.e. - IFS has elapsed) the rising edge of ROY is
interpreted as signalling the first byte of a new message. The
HIP7010 immediately performs a solicited SERIAL transfer
to load the first byte. Prior to performing the transfer, the
HIP7010 drives the J1850 bus high to initiate an SOF symbol. The SOF is then followed by the eight symbols which
represent the translerred byte. If a J 1850 message is
already in progress, the rising edge of RDY is interpreted as
signalling that the next byte of the message or of an IFR is
ready to be transferred from the Host. The H IP701 0 will initiate the transfer, as an unsolicited transfer, when conditions
on the J 1850 bus warrant the transfer (i.e. - when the previously retrieved byte has been completely transmitted on the
J1850 bus or aiter EOD for an IFR).
While the rising edge of RDY is used to notify the HIP7010
that the Host is ready to supply the next byte, the level of
RDY following the actual serial transfer provides additional
information. Figure 1 depicts the use of RDY. 8y driving the
RDY line high and returning it low before the transfer has
been completed, the HIP7010 will detect a low. This is
referred to as a short ROY. If the RDY line is brought high
and held high until the transfer is complete, a high level is
detected by the HIP7010. This is referred to as a long ROY.
A short RDY signals a normal transfer, but a long ROY has
special significance. A long ROY indicates that the byte currently sitting within the Host is the last byte of a message or of
an IFR. When transmitting the body of a message or a Type 3
IFR the HIP7010 will automatically append the CRC aiter the
byte for which the long ROY was used. When responding with
a Type 1 or Type 2 IFR the response is a single byte, and as
such it is always the last byte. For sake of consistency the
HIP7010 requires a long ROY for Type 1 and Type 2 IFRs.
See Status/Control Register and Application Information
for more details.
The other handshaking input is the Request Status/Control
(STAT) input pin. STAT is used by the Host microcontroller to
initiate an exchange of the Host's control byte and the
HIP7010's ststus byte. A low to high transition on the STAT
input signals the HIP7010 that the Host has placed a control
word in it's serial output register and is ready to exchange it
with the HIP7010's status word. The HIP7010 will generate
the eight SCKs for the solicited transfer as soon as feasible.
To avoid confusion with the transfer of a received J 1850
byte, STAT should generally be pulsed shortly aiter receiving
each data byte from the HIP7010. This technique is safe,
because once a J1850 message byte has been received
from or sent to the HIP7010, another unsolicited transfer is
guaranteed not to happen for at least 500f.1s. A ControVStatus byte transfer should also be performed in response to
each high to low transition on the ii5tE line. See Application Information for more details.
Status/Control Register
The Status/Control Register is actually a pair of registers:
the Status Register and the Control Register. When the Host
initiates a Status/Control Register transfer by raising the
STAT input, the HIP7010 sends the contents of the Status
Register to the Host and simultaneously loads the Control
register with the byte received from the Host.
Status Register
The Status Register contains eight, read-only, status bits.
IE~D I I ~ I~u I 4~ I IE~R I I
M:CK
87, EOD
C:C
B:K
When an EOD symbol has been received on
VPWIN and an IFA byte is received from the
J 1850 bus, the End-of-Data flag (EOD) is set,
during the unsolicited transfer of the byte from the
HIP7010 to the Host. EOD remains set, until the
unsolicited transfer of the first byte of the next
frame.
EOD can be used to distinguish the IFR portion
of a frame from the message portion.
EOD is cleared by reset.
86, MACK If MACK (Multi-byte ACKnowledge) is high,
either the MACK control bit has been set during
a previous Status/Control Register transfer or a
long normalization bit has been received following an EOD. When both MACK is set and the
EOD flag (see 87, EOD) is set, the most recent
data byte transferred is part of a Type 3 IFR.
Mask remains set until the unsolicited transfer of
the first byte of the next frame.
MACK is cleared by reset.
B5, 0
9-27
8it 5 of the Status byte is not used and will
always read as a O.
J!!
Xw::::l
..J~
0.-
.
-(,)
~
::::I::::E
::::E::::E
o(,)
HIP7010
B4,FTU
When First Time Up (FTU) is high, it indicates
that a reset has occurred since the last Status/
Control Register transfer. FTU is high during the
first Status/Control Register transfer after a reset
and low thereafter.
FTU can be used to recognize that a Slow Clock
Detect reset has occurred or to insure that a
Status/Control Register transfer has been successfully completed since the last reset.
B3,4X
The 4X status flag indicates that the 4X mode bit
has been set in the Control Register. This bit
reflects the contents of the Control Register not
the current mode of the HIP7010's SEN DEC.
The SEN DEC only changes modes synchronously with an edge detected on the VPWIN pin.
B2, CRC
The CRC Error flag (CRC) is set when a CRC
error has been detected in the current frame.
Control Register
The Control Register contains eight, write-only, control bits.
The PD, NXT, MACK, and ACK bits can only be set high they
are cleared by hardware under specific conditions. The other
four bits can be both set and reset by the Host. All bits in the
Control Register are cleared by reset.
IA~K I IN~T Ip~ 14~ Io~ I0~1 I I
M:CK
B7, ACK
4X is cleared by reset.
CRC is cleared by reset and at the conclusion of
the Status/Control Register transfer.
B1, ERR
The Error flag (ERR) is set when an illegal symbol or other, non-CRC error has been detected on
the VPWIN pin. Following are some of the many
errors which will cause ERR to be set: 1. AIl illegal
symbol, (i.e. - a symbol other than a TV1, TV2, or
Break in the middle of a data byte); 2. Receipt of a
truncated byte (i.e. - less than 8 symbols); 3. The
Host attemptin~nitiate a message more than
96J.1s after the IDLE line goes high; 4. AIl improperly framed message (i.e. - SOF not equal to
TV3, wrong EOD, EOF, or NB widths); 5. Failure
by the Host to use the long form of RDY to indicate the last byte of a message; 6. AIl attempt by
the Host to transmit a single byte (Type 1 or Type
2) IFR by setting ACK but without using the long
form of RDY for the byte transfer; 7. Setting the
Host asserting STAT during a data byte transfer;
8. A transition has occurred on the VPWOUT pin
and the reflected transition has not been
detected on \iPWiN (echo fail).
ERR is cleared by a reset and at the conclusion
of the Status/Control Register transfer.
BO, BRK
The bre~J!~JBRK) is set on the first rising
edge of VPWIN after a BRK symbol has been
detected on the J1850 bus. If the Host was
transmitting or has a message to transmit, it
should re-arbitrate for the bus following an IFS
(IDLE goes low).
BRK automatically clears the 4X mode of the
SEN DEC and resets the 4X bit in the Status byte.
BRK is cleared by a reset or at the conclusion of
the Status/Control Register transfer.
9-28
0:0
Setting the Acknowledgment (ACK) bIt signals
the HIP7010 that, following the EOD, an IFR
response is to be sent. Once set, the ACK bit
cannot be cleared by the Host. ACK is cleared
upon successful transmission of the IFR or at
the next Idle.
The ACK bit can be set anytime prior to the final
byte of a message. The first IFR byte must be
loaded into the Host's serial output register, and
the RDY line set after the HIP7010 transfers the
next-te-Iast byte to the Host, and before the
HIP7010 transfers the last byte (CRC) of the
J1850 message to the Host. When the CRC
byte is sent to the Host from the HIP7010, the
IFR byte will be simultaneously loaded into the
HIP7010.
To send a single byte (Type 1 or Type 2) IFR the
Host must leave MACK (B6 of the Control Register) low and use the long ROY line format.
When sending a single byte (Type 1 or Type 2)
IFR, the possibility of losing arbitration exists. In
the case of a Type 1 IFR no further action should
be taken. The standard protocol lor handling
loss of arbitration during a Type 2 IFR is to reattempt the transmission until successful. To
ensure proper transmission of the IFR the Host
must repeatedly load it's serial output register
with the desired IFR byte, and set RDY (using
the short format), until the IFR has been properly received back. There is no danger of inadvertently sending the IFR byte twice. The
HIP7010 monitors the arbitration results and will
transmit the IFR byte only once. The ACK bit is
automatically cleared upon the first successful
transmission thus preventing a second transmission. The Host controls when the ACK bit is set.
During normal operation the Host must only set
ACK once per IFA.
To send a Type 3 IFR the Host must set MACK
high and use the short format of the RDY for all
bytes except the last, when the long format is
used. A CRC will automatically be appended to
the last byte of a Type 3 IFA. A Type 3 IFR, consisting of a Single byte plus CRC, can be created
by selting MACK high and using the long RDY
line format for loading the Single data byte.
HIP7010
When sending a Type 3 IFR, the possibility of
losing arbitration during the IFR also exists. In
the case of Type 3 IFRs, once arbitration has
been lost the Host no longer needs to continue
transmitting bytes. As in the case of Type 2
IFRs, the Host cannot know arbitration has been
lost until after the next byte to transmit has been
loaded. Again, there is no danger of sending
extra bytes because the HIP7010 automatically
suspends transmissions once arbitration is lost.
PD can only be set if the IDLE pin is low or during the first Status/Control Register transfer following a reset. The ClK input is internally gated
off at the end of the Status/Control Register
transfer.
There are two situations which can cause the
PD bit to be cleared prematurely: 1. The ROY
input Is high during the Status/Control Register
transfer (since this is under control of the Host it
should be avoided); 2. A noise pulse of less than
811S duration occurs on the VPWIN line.
B6, MACK The Multi-byte Acknowledge (MACK) bit, in conjunction with the ACK bit, signals the HIP7010
that, following the EOD, a Type 3 IFR with CRC
response is to be sent. Once set, the MACK bit
cannot be cleared by the Host. MACK is cleared
upon detection of an Idle following the transmission of the IFA. Setting MACK without also setting ACK will result in no IFR being transmitted.
The MACK bit can be set anytime prior to the
final byte of a message. The first IFR byte must
be loaded into the Host's serial output register,
and the ROY line set after the HIP7010 transfers
the next-to-Iast byte to the Host, and before the
HIP7010 transfers the last byte (CRC) of the
J1850 message to the Host. When the CRC
byte is sent to the Host from the HIP7010, the
first IFR byte will be simultaneously loaded into
the HIP7010. To send a Type 3 IFR the Host
uses the short format of the RDY for all bytes
except the last, when the long format is used.
B5, NXT
See Effects of Resets and Power-Down for a
detailed discussion of the Power-Down mode.
B3,4X
If the Wait for Next Idle (NXT) bit is asserted
high during a Status/Control Register transfer,
the HIP7010 State Machine is re-initialized to a
"wait for Idle" state. The VPWOUT pin is driven
low and the IDLE pin is reset high. Activity on
the VPWIN pin is ignored until a valid Idle is
detected. When NXT is asserted the IDLE pin
will go high for a minimum of 611S. If the bus is
Idle at the end of the 611S period, i15'LE will be
driven low and the HIP7010 will be ready to
transmit or receive a J1850 message. If the bus
is not Idle, current activity on the VPWIN pin is
ignored until a new Idle is detected.
The NXT bit enables the Host to ignore the balance of the current message. Unsolicited transfers from the HIP7010 are guaranteed not to
occur until the next Idle occurs. Transfers
resume following the first byte of the next message.
B4, PD
If either of these situations occur, the PD will be
cleared, the HIP7010 will awake and look for a
valid edge on VPWIN, RDY, or STAT. If no valid
edge has occurred the HIP7010 will recycle to
the top of the State Machine, pulsing IDLE high
for a minimum of 211S. It is the responsibility of
the Host to monitor the i15'LE pin after setting PD
to ensure that the POWER-DOWN mode has
been successfully entered.
Setting the High Speed Mode (4X) bit causes the
HIP7010's SEN DEC to decode symbols received
on the J1850 bus at 0.25X the normal durations.
The 4X mode is designed to allowed receipt of
messages at 4X the normal J1850 rate. It is
intended for manufacturing and diagnostic use, not
normal "down the road" vehicle communications.
Transmission is inhibited while the 4X bit Is sel
The 4X bit can only be written to when the i15'LE
pin is low or during the first Status/Control Register transfer following a reset. The SEN DEC
begins operating at the 4X rate upon receipt of
the next edge. The system must provide sufficient
time for all nodes to detect the Idle, interpret the
"shift to high speed" message, and change their
mode bits before issuing a high speed SOF.
4X is cleared by receipt of a Break symbol on
the J1850 bus and it can also be cleared by performing a Status/Control Register transfer with
the 4X bit low. When cleared via a Status/Control Register transfer, IDLE must be low. The
SENDEC reverts to operating at the normal rate
upon receipt of the next edge.
B2,DS2
B1, DS1
BO, DS1
The Power-Down (PD) bit is used to halt internal
clocks to the HIP7010 to minimize power. A low
level on the VPWIN, a low to high edge on the
STAT pin, or a high level on the ROY pin will clear
the PD bit and normal HIP7010 functions will
resume.
9-29
The three Divide Select bits (DS2-DSO) are
used to match the internal clock divider with the
input frequency on the ClK input to produce the
required 2MHz internal time base. Table 3
shows the clock divide values and nominal input
frequency for the eight combinations of DS2DSO.
HIP7010
During a HIP7010 reset caused by a POR, a
Slow Clock Detect, or a low on the RESET line,
the Clock Divider is inhibited and a fixed divide-by
sixteen clock divider is activated. This Is greater
than any selectable divide-by and guarantees
proper operation of the SERIAL interface for all
valid operating frequencies (although the transfer
rate will be below 1MHz). The ClK divide-by
remains at sixteen and operation of the HIP7010
is suspended until the Host performs a Status!
Control Register transfer to set the proper divide
value. The State Machine and SEN DEC are held
in a reset state (passive) until the first Status!
Control Register transfer has been completed.
This insu res proper setting of the divide selects
prior to generation or receipt of any symbols.
TABLE 3. DS2-DSO CLOCK DIVIDER SELECTIONS
INTERNAL
HIP7010 ClK
DIVIDE-BY
12
DS2
DS1
DSO
ClKINPUT
FREQ.(MHZ)
0
0
0
24 (Note 1)
0
0
1
12 (Note 1)
6
0
1
0
20
10
0
1
1
10
5
1
0
0
16 (Note 1)
8
1
0
1
8
4
1
1
0
4
2
1
1
1
2
1
the Harris J1850 Bus Transceiver HIP7020) to the single wire
J1850 bus. The transceiver is responsible for generating and
receiving waveforms consistent with the physical layer specifIcations of J1850. In addition, the transceiver is responsible for
providing isolation from bus transients.
Every symbol sent out on the VPWOUT is, in effect, inverted and
reflected back on the \ii5WiN pin after some finite delay through
the transceiver. In actuality. Only active symbols are guaranteed
to be rellected unchanged. If the transmitted symbol is passive
and another node is simultaneously sending an active symbol,
the active symbol will dominate and pull the bus to a high level.
The SEN DEC circuitry includes a 3-bit digital filter which ellee>
tively filters out noise pulses less than 81ls in duration.
The STATE logic transfers data bits between the SERIAL
system and the SEN DEC and handles addition of required
Irame elements such as the SOF symbol and the CRC byte.
When transmitting bytes, bits are taken Irom the SERIAL
shift register and translated into the required symbols, bit by
bit. Timing of each symbol Is calculated from the last
transition on the VPWIN line which keeps all nodes on the
J 1850 bus "in synch" during arbitration periods.
Decoding of received symbols is automatically performed by
the SENDEC. The decoded symbol is translated to a 0 or 1
value and transferred by the STATE logic into the SERIAL shift
register. As each symbol is decoded it is shifted into the
SERIAL shift register and, if transmitting, the next bit to transmit
on the J1850 bus Is shifted out. Once an entire byte has been
loaded into the SERIAL shift register the STATE logic automatically generates an unsolicited transler 01 the byte to the Host.
NOTE:
1. Objective Specification
Once DS2-DSO have been set following a reset,
they must not be altered. Each Status/Control
Register transfer must properly reassert the
same DS2-DSO values to maintain proper clocking. Selecting a DS2-DSO combination which is
too low for the given ClK frequency can result in
loss of SERIAL communications, due to excessive clocking rates. In such instances the only
recovery mechanism is to force a HIP7010 reset
by pulling the R'ESEi' input low, interrupting the
ClK input, or performing a power-on reset. A well
behaved Host will avoid changes to DS2-DSO.
System fault tolerance can be maximized by using
the lowest possible frequency at the CLK input.
Power-down does not reset DS2-DSO, allowing
rapid "wake-up" Irom the Power-down state.
Symbol Encoder/Decoder (SENDEe)
Operation
The Symbol Encoder/Decoder (SENDEC) hardware integrated in the HIP7010 handles generation and receplion of
J1850 messages on a symbol by symbol basis. Symbols are
output Irom the SENDEC, as a digital signal, on the VPWOUT
pin and input, as a digital signal, on the VPWIN pin. These two
lines must be connected through a bus transceiver (such as
Whenever the SEN DEC is transmitting, it is simultaneously
monitoring the "reflected" symbol on the ijj5VijjN line. At
each transition the reflected symbol is read and compared to
the sent one. II the rellected symbol doesn't match the symbol sent, a collision has occurred and the HIP7010 automatically disables transmissions until the next IdiellFR period. II
there was no collision, the HIP7010 continues transmitting
until the entire byte has been sent. Once the byte has been
sent, a full byte will also have been rellected and received by
the HIP7010. As discussed above, the HIP7010 initiates a
transler of the received byte to the Host, which allows the
Host the opportunity to compare the sent and reflected
bytes, and to transfer the next byte of the message.
In addition to features already discussed, the SEN DEC
includes, noise detection, Idle bus detection, a wake-up facility, "no echo" detection, and a high speed receive mode. Symbol timing is based on the main ClK input. The programmable
prescaler, controlled by the DSO-DS2 bits in the Control Register, allows proper SEN DEC operation with a variety of ClK
input frequencies (see OS2-0S0 under StatuslControl RegIster for prescaler details). The high speed mode is a J1850
extension which allows production and/or maintenance equipment to transmit messages at 4X the normal 10.4Kbps rate
(see 4X under StatuslControl Register for prescaler details).
Software algorithms can be implemented in the Host to provide message buffering and Iiltering and other needed features to create a complete J1850 VPW node. See the
Applications Information section for typical algorithms.
9-30
HIP7010
The State Machine Logic (STATE)
Effects of Resets and Power-Down
The State Machine logic (STATE) of the HIP7010, is a
sequential state machine implementation of the J1850 VPW
data link layer. STATE controls data flows within the HIP7010
and between the Host and the J 1850 bus.
Resets
When receiving messages, STATE monitors the input from
the SEN DEC, building byte sized chunks to send to the Host.
As each byte is assembled, STATE transfers the result to the
Host via the Serial interface, as an unsolicited transfer. Upon
receipt of a complete message (recognized by EOD), STATE
verifies both the CRC and bit counts and sets appropriate
Status Register flags.
When transmitting messages from the Host to the J1850
bus, STATE waits for the first ROY input transition, after
which it retrieves the first byte from the Host and initiates the
message with an SOF. Each bit of the Host's message byte
is transferred to the J1850 bus via the SENDEC. When the
transfer of a byte is complete, STATE checks for a new ROY
(if there is one), retrieves the associated byte, and again
transfers the byte via the SENDEC to the J1850 bus. After
retrieving each byte from the Host, STATE checks to see if
the long ROY format was used, which indicates this is the
end of the Host's message. If the message is complete,
STATE transfers the final byte to the J 1850 Bus and then,
automatically, sends the computed CRC to the J1850 bus.
Throughout the transmission of a message from the Host to
the J1850 bus, STATE monitors the symbols reflected back
via the SEN DEC and handles all bus conditions such as loss
of arbitration, illegal bits, Break, bad CRC, and missing bits.
STATE also catches Host errors including failure to set the
ROY line in time for the next byte transfer, attempting to initiate a new message more than 961ls after IDLE has gone
away, and inappropriate use of the STAT line (Le. - requesting a Status/Control Register transfer during an unsolicited
transfer of the reflected data).
The Control Register bits -influence STATE. If ACK is set,
STATE handles sequencing of the requested IFA. The flow
consists of waiting for an EOD, sending the appropriate Normalization Bit (Type 1/2 vs Type 3 IFR), transferring the IFR
byte(s) from the Host to the J1850 bus, handling arbitration,
and finally adding the CRC to Type 3 IFRs. As with normal
transmissions, STATE contains error handling to react appropriately to all J 1850 bus conditions.
m
Detection of an Idle on the bus causes STATE to set the
pin. STATE clears the
pin upon receipt of a transition on
the Vi5WiN line or when the Host initiates a new message.
m
Detection of a Break on the J1850 bus causes an interrupt
input to STATE which causes the HIP7010 to cease any current transmission and enter a wait for 7i5[E mode.
A Power-On reset, a Slow Clock Detect reset, and a low on
the RESET pin all have an Identical effect on the operation of
the HIP7010. All resets are asynchronous and immediately
do the following:
• VPWOUT is forced low.
• The HIP7010 is set to RESTART mode.
• The internal divide-by is set to sixteen and held at that
value until the RESTART mode ends.
• SACTIVE is forced high and SCK and SOUT are set to a
high impedance state.
• The ACK, MACK, NXT, PO, and 4X bits are cleared in the
Control Register.
• All Status Register bits are cleared (except bit 4, FTU,
which is set to a 1).
• iDLE is forced high and held high for 17 CLKs after the
source of the reset is removed. After 17 ClKs, IDLE is
forced low. iDLE Remains low until 40 ClKs +1.5Ils after
the first Status/Control Register transfer.
• The SEN DEC is reset, holding the symbol timer at a count
of 0 and clearing the 3-bit VPWIN filter to all O's, until the
RESTART mode ends.
• STATE Is held in a reset loop until the RESTART mode
ends. While STATE is in the reset loop, transitions on the
ROY pin are ignored.
The RESTART mode is entered by any reset and ends when
the first Status/Control Register transfer has been completed. Upon exiting the RESTART mode the HIP7010
enters its normal RUN mode. This is reflected in the clearing
of the FTU bit of the Status Register.
When the RESTART mode ends and the RUN mode begins,
the internal divide-by is set to the valu~grammed via
DS2-DSO in the Control Register. The IDLE ~in is driven
high after 40 ClKs, the SENDECs counter and VPWiN filter
begin operating, and STATE begins monitoring the outputs
of SEN DEC looking for an Idle.
The HIP7010 remains in RUN mode until another reset
occurs or the POWER-DOWN mode is entered.
Power-Down
The POWER-DOWN mode of the HIP7010 is entered by setting the PO bit in the Control Register (see Control Register
for more information). Setting the PO bit can only be done
when the HIP7010 is driving the
pin low. Once set, the
PO forces the HIP7010 to the POWER-DOWN mode 21ls
after the completion of the Status/Control Register transfer.
While in the POWER-DOWN mode the CLK input is internally
gated off, minimizing power dissipation. The Slow Clock
Detect is inhibited while in the POWER-DOWN mode.
9-31
m
~
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i
1:!1:!0..~
>0..
>
W
II:
CAUTION: These devices are sensHive to electrostatic discharge. Users should IoIIow proper I.C. Handling Procedure&.
Copyright © Harris Corporation 1994
9-40
File Number
3645
HIP7030AO
Block Diagram
TCAP
VI
w
z
:J
g
C
Ii:0
...
m{
~
PD1
'00
PD2, V2
~
IS
...
TIMER SYSTEM
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
g
INTERNAL
PROCESSOR
CLOCK
PORT
A
REG
DATA
DIR
REG
PORTO
SFR
REG
PD3, V3
PD4, VR
TCAP
PORTO
DIR
REG
38 _ _
RESET
39 iRci
SYMBOLINT
ACCUMULATOR
8
A
INDEX
REGISTER
5
CONDITION CODE
REGISTER
6
STACK
POINTER
CPU
CONTROL
CC
37
36
X
VPWOUT
VPWlN
CPU
S
5
PROGRAM
COUNTER HIGH PCH
8
PROGRAM
COUNTER LOW
SCK
ALU
MOSI
MISO
PCl
Ss
13
OS
WE
CE
FS
BUS
CONTROL
ii6
AlC
Vss 22
VOO
7
:i\
c ciii II!
c cIi! c~ c:a clB Iii
c
~
> -10mA
Voo -0.1
-
Output High Voltag~ _ _
AO-A12. 080-067. CEo RD. WE. FS
VOH
IlOAD
=O.SmA
V oo -o·8
-
-
OUtput Low Voltage.;... _ _
AO-A12. 080-067. CEo RD. WE. FS
VOH
ILOAD
=1.6mA
-
-
0.4
Input High Voltage: 060-067
VIH
-
O.50Voo
0.7·Voo
V
Input Low Voltage: 060-067
VIL
0.3-Voo
-
-
V
060-7 High Impedance Leakage
Current:
IlL
-10
-
+10
jIA
Input Current
liN
-1
+1
jIA
CapaCitance
COUT
12
pF
CIN
-
-
8
pF
IRUN
-
8
TBO
mA
Output Voltage
Supply Current: RUN
V
NOTES:
1. This device contains circuitry to protect the Inputs against demage due to high static voltages 01 electric fields; however. It Is advised that
normal precautions be taken to avoid application 01 any voltage higher than maximum rated voltages to this high impedance circuit. For
proper operation It is recommended that VIN and VOUT be constrained to the range Vss S (VIN or VOUT) S Voo- Reliability 01 operation is
enhanced il unused inputs are connected to an appropriate logic voltage level (e.g•• either Vss or VDO)
2. Characteristics are listed for the signals unique to the Emulator IC. For details on the other signal pins see the HIP7030A2 data sheet.
3. Minimum frequency applies when ALC is low.
9-42
Specifications HIP7030AO
Read Cycle Timing (ALC = 0) (See Figure 1) Voo = 5Voc ±100f0. Vss = OVoc • TA = -40"C to +125°C Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
1
10
MHz
fosc
OSCB Operating Frequency
(1)
Icvc
Read Cycle Time
200
2000
ns
(2)
tAVCEL
Address Setup Time Before CE
-10
-
ns
(3)
IovcEL
Access Time From CE
Icvc - 80
ns
(4)
tOVROL
Access Time From RD
0.751cvc - 80
ns
(5)
IovAv
Access Time From Address Change
-
Icvc - 80
ns
(6)
IeEHAX
Address Hold Time Alter CE
0
ns
(7)
IcEHAX
Data Hold Time Alter CE
0
(8)
~OLOX
Data Bus Driven From RD
(Time to Data Active from High Impedance
State)
0
-
(9)
~OHAX
Data Hold Time Alter RD
(Hold Time to High Impedance State)
0
-
ns
(10)
Ioscos
OSCB to OS Propagation Delay
5
25
ns
ns
ns
NOTE:
Minimum frequency applies when ALC Is low.
Write Cycle Timing (ALC = 0) (See Figure 2) Voo = 5Voc ±100f0. Vss = OVoc • TA = -40oC to +125°C Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
1
10
MHz
fosc
OSCB Operating Frequency
(1 )
Icvc
Write Cycle Time
200
2000
ns
(2)
tAvCEL
Address Setup Time Before CE
-10
-
ns
(3)
tAVWEL
Address Setup Time Before WE
0.251cvc - 25
-
-
)(w:;:)
(4)
tWEWE
WE Pulse Width
0.51evc -10
ns
(5)
IoVWEH
Data Set-up Time to WE Trailing Edge
O.751cvc - 75
-0
~.
:;:):!l
:!l:!l
(6)
tWEHOX
Data Hold Time Alter WE Trailing Edge
0.251evc - 20
(7)
tWEHAX
Address Hold Time Alter WE Trailing Edge
0.251cvc - 20
-
(8)
tascos
OSCB to OS Propagation Delay
5
25
ns
NOTE:
1. Minimum frequency applies when ALC is low.
9-43
ns
ns
ns
~
..JO
Q,!!:
oo
Specifications HIP7030AO
Read Cycle Timing (ALC
NUMBER
= 1) (See Figure 3) Voo = 5Voc t10%, Vss =OVoc, TA =-40"C to +125°C Unless Otherwise Specified.
PARAMETER
SYMBOL
MIN
MAX
UNITS
10
MHz
ns
0.5Ievc-25
-
fosc
OSCB Operating Frequency
(1)
levc
Read Cycle Time
(2)
iRoosc
RD, FS Setup Time Before OSCB
(3)
IovCEl
Access Time From CE
-
Ievc-80
ns
(4)
Iovosc
Access Time From OSCB
-
Ievc-7O
ns
(5)
IoSCAv
Address Setup Time Before OSCB
0.5Ievc-25
-
ns
(6)
IoscAX
Address Hold Time After OSCB
ns
(7)
IoscAX
Data Hold Time After OSCB
10
-
(8)
iROlOX
Data Bus Driven From CE
(Time to Data Active from High Impedance
State)
0
-
ns
(9)
IoscRo
RD, FS Hold Time After OSCB
0.51evc
-
ns
(10)
Ioscos
OSCB to DS Propagation Delay
5
25
ns
200
0.51evc
ns
ns
NOTE:
1. Minimum frequency applies when ALC Is high.
Write Cycle Timing (ALC = 1) (See Figure 4) Voo = 5Voc t10%. Vss = OVoc. TA = -40°C to +12SoC Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
fosc
OSCB Operating Frequency
(1)
levc
Write Cycle Time
(2)
iRoosc
RD. FS Setup Time Before OSCB
(3)
Iovosc
Data Setup Time Before OSCB
(4)
IoscAv
Address Setup Time Before OSCB
(5)
IoscAx
Address Hold Time After OSCB
(6)
IoscAx
Data Hold Time After OSCB
(7)
Ioscox
Data Bus Driven From OSCB
(Time to Data Active from High Impedance
State)
(8)
IoscRo
(9)
Ioscos
MIN
200
0.5Ievc-25
0.5Ievc-25
O.Slevc
10
MAX
UNITS
10
MHz
-
ns
0.75Ievc-95
ns
-
ns
-
ns
ns
ns
.2Slevc-2S
-
ns
RD. FS Hold Time After OSCB
o.Slevc
-
ns
OSCB to OS Propagation Delay
5
25
ns
NOTE:
. 1. Minimum frequency applies when ALC is high.
9-44
HIP7030AO
----.
\
OSCB
os
AO-A12
-
J
~10
W
w
----l~
J~
2-
,
r-
1-
6-
]r--V
,
-
1\
II
DB
j
1\
8-
1---
7-
t--
NOTE:
1. Measurement points are VOL.
V OH • V 1L
and
V 1H •
FIGURE 1. READ CYCLE TIMING DIAGRAM (ALC
=0)
OSCB
os
AO-A12
~
>-
....._ _ _~......_ _ _
DB
FETCH
READ (INTERNAL)
WRITE
FIGURE 5. SIGNAL TIMING DIAGRAM (ALC = 1)
Functional Pin Description
This section provides a brief description of each of the pins
of the H)P7030AO microcontroller. A more detailed discus·
sion is contained in the HIP7030A2 data sheet.
VDD and Vss (Power)
Power is supplied to the MCU using these two pins. Voo is
connected to the positive supply and Vss is connected to the
negative supply.
IRQ (Maskable Interrupt Request - Input)
The IRQ pin is negative edge· sensitive triggering. A high to
low transition on the input to the IRQ pin will produce an
interrupt.
In the event of an interrupt request. the MCU always completes the current instruction before it responds to the
request. An internal mask can be used to inhibit the MCU
from responding to IRQ interrupts.
An edge-sensitive IRQ interrupt is generated if the IRQ pin is
pulled low for at least one tILlH' The occurrence of the low
going pulse is registered in a flip-flop and the IRQ interrupt
will be recognized even if the IRQ pin has returned to a high
state before the interrupt can be serviced.
Once the edge-sensitive flip-flop is cleared (it is automatically cleared at the start of the interrupt service routine) the
interrupt request is removed until the IRQ pin retums to a
high level and once again goes low.
RESET (Master Reset - Input)
TCAP (TImer Capture· Input)
The TCAP input controls the input capture feature for the on·
chip programmable timer system. The TCAP input is also
used as the strobe signal to the Port D strobed outputs.
TCMP (TImer Compare - Output)
The TCMP pin provides an output for the output compare
feature of the on-chip timer system.
OSCIN (Oscillator Input - Input),
OSCOUT (Oscillator Output· Output),
OSCB (Oscillator Buffered Output - Output)
OSCIN is the input and OSCOUT is the output of an inverter!
amplifier which can be used to build either a quartz crystal or
ceramic resonator based clock oscillator. Alternatively the
OSCIN input can be driven from any external clock source
whiCh satisfies the CMOS schmitt trigger input level requirements of the OSCIN pin. OSCB is a squared, buffered version of the OSCIN signal. available for driving one external
CMOS load. See Electrical Specifications of the HIP7030A2
for output drive and input level specifications.
The fundamental internal clock is derived by a divide-by-two
of the external oscillator frequency (fOSC). All other internal
clocks are also derived from the external frequency. These
clocks include the input to the 16-bit Timer. the SPI Serial
Clock (SCK). and the VPW Symbol EncoderlDecoder (SENDEC).
PAO-PA7 (Port A - Input/Output)
The HIP7030A2 contains an integrated Power-On Reset (POR)
circuit and the RESET input is therefore not required for startup. It can be used to reset the MCU internal state and provides for an orderly re-start of the software after initial powerup. A low level on the RESET pin will reset the HIP7030AO.
These eight I/O lines comprise Port A. The mode (i.e. - input
or output) of each pin is software programmable. All Port A 1/
lines are configured as inputs during power-on or RESET.
o
9-47
><~
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-,0
Q,.!:E
-0
!:i.
;:)::::rE
::::rE::::rE
o
o
HIP7030AO
PDO-PD4 (Port D - Input/Output)
These five 1/0 lines comprise Port D. As with PAO-PA7, the
mode (i.e. - input or output) of each pin is software programmable. In addition a Special Function Register (SFRD)
allows configuring PD~ and POl as "strobed" outputs, and/or
PD2,PD3, and PD4 as inputs to an on-chip analog comparator.
All Port 0 VO lines are configured as inputs during power-on
or RESET.
VPWOUT (Variable Pulse Width Out - Output).
VPWIN (Variable Pulse Width In - Input)
These two lines are used to interface to the J 1B50 bus transceiver.
VPWOUT is the pulse width modulated output of the SENDEC encoder block.
VPWINis the inverted input to the SENDEC decoder block.
MISO (Master-lniSlave-out - Input/Output).
MOSI (Master-out/Slave-In - Input/Output).
SCK (Serial Clock -Input/Output).
55 (Slave Select - Input)
These four lines constitute the Serial Peripheral Interface
(SPI) communications port. The MCU can be configured as
a SPI "master" or as a SPI "slave". In master mode MOSI
and SCK function as outputs and MISO functions as an
input. In slave mode MOSI and SCK are inputs and MISO is
an output. SS is always an input.
Serial data words are transmitted and received over the
MISOIMOSI lines synchronously with the SCK clock stream.
The word size is fixed at B bits. Single buffering is used
which results in an Inherent inter-byte delay. The master
device always provides the synchronizing clock.
A low on the 55 line causes the MCU to Immediately
assume the role of slave, regardless of it's current mode.
This allows multi-master systems to be constructed with
appropriate arbitration protocols.
ALC (Address Latch Control - Input)
• The Internal RAM is disabled and accesses to RAM space
are mapped off-Chip.
• AQ-A12, FS, and Ro are produced Icvc cycle (i.e. lOOns
with a 10MHz clock) ahead of data bus transitions of the
HIP7030AO's machine cycle. The earlier availability of
these address and control lines facilitates implementation
of break detection and bus tracing logic. External latching
of the address and control signals is required for interfacl!la. to th!J!!emory of the development tool. The timing of
CE and WE are not affected by ALC, and remain synchronized with data bus transfers.
• The Ro signal is no longer gated with CE and is a full
cycle wide, when ALC is high. RD indicates whether the
ensuing data bus cycle will be a read of or write to l1)emory-I/O space. It can be viewed as a Rtw signal. Ro provides Rtw Information for all cycles, internal as well as
external.
• Resetting the HIP7030AO with ALC = 1 disables the Slow
Clock Detect circuits. The Watchdog can be disabled by
writing to the Watchdog Status Register (WSR - location
$1 E), which has special features when ALC is high. The
Slow Clock circuit is permanently disabled when ALC = 1.
If the Slow Clock detect circuitry were allowed to run, stopping the CPU clock during breakpoint servicing would not
be possible. The watchdog should be reset by the tool
while interrogating the CPU.
The ALC input has an integrated pull-down device which
allows floating this pin when interfacing to industry standard
memory devices.
Ao-A12
Address lines 0 through 12. When ALC = 0, AO-A12 are
coincident with data bus transfers. When ALC 1, AO-A12
change Icvc ahead of the data bus transfers and must be
externally latched. See the timing diagrams in the Electrical
Specifications section for more details.
=
DBo-OB7
Bidirectional B-bit non-multiplexed data bus lines. The data
bus is an input during all reads from external memory-VO
space and during the first tcvc of every machine cycle. At all
other times it is an output. See the timing diagrams in the
Electrical Specifications section for more details.
The ALC input controls the timinun.!..!unction of the
address and memory control lines (CE, RD, WE, and FS).
For more information on each of these lines refer to the
appropriate section.
CE (Chip Enable - Output)
When ALC is low the address and control lines are produced
coincident with data bus transitions of the HIP7030AO's
machine cycle. This mode allows direct interfacing to industry standard memory devices. Refer to the timing diagrams
in Electrical Specifications for more details.
Chip Enable is an output signal used for selecting external
memory or 1/0. A low level indicates when external memory
or 1/0 is being accessed. Note that the CE Signal will not go
true when addressing the unused locations of Page 0 1/0
space even though the address lines will be valid.
Driving ALC
the address
to facilitate
HIP7030A2.
R5 (Read - Output)
high causes several changes in the behavior of
and control lines. These changes are intended
design of development systems for the
When ALC is high the following occur:
RD is a status output signal which indicates direction of data
flow with respect to external or internal memory space (a low
level indicates a read from memory space). A read from
internal memory or 1/0 will place data on the external data
9-4B
HIP7030AO
bus. When ALC = 0, RD is internally gated with CE, and generated in synchronization with data bus cycles. With ALC
0, standard RAM, ROM, and EPROM devices can be directly
connected to the HIP7030AO with no additional components.
When ALC = 1, R5 is not gated by CE and is produced !eve
cycle (i.e. 100ns with a 10MHz clock) ahead of data bus
transitions of the HIP7030AO's machine cycle.
=
may want to intentionally clear this bit to eliminate the need
to insert watchdog handling routines. The clearing of the bit
must be done following every reset.
Reset presets the WOE bit of the WSR to enable the Watchdog Timer.
WE (Write Enable - Output)
Write Enable is an active low output pulse for use in writing
data to external RAM memory. A low level indicates valid
data on the data bus. WE is internally gated with CE for writing to external memory. Since, in most systems, external
memory is substituting for mask programmed ROM, WE is
frequently not used.
OS (Data Strobe - Output)
The Data Strobe output provides a pulse when address and
data are valid. OS can be used to transfer data to or from a
peripheral or memory and occurs every cycle and is also
used for synchronizing development tools to the oscillator
clock. OS is a continuous signal at fose + 2, except when the
Emulator is in the WAIT or STOP mode. See the timing diagrams in the Electrical Specifications section for more
details.
FS (Fetch Status - Output)
The FS output signal goes true to indicate an opcode fetch
cycle is in progress. When ALC 0, FS will be coincident
with the data transfer of the fetch. When ALC = 1, FS is produced tCYC cycle (i.e. 100ns with a 10MHz clock) ahead of
data bus transitions of the HIP7030AO's machine cycle. See
the timing diagrams in the Electrical Specifications section
for more details.
=
Watchdog Status Register
When ALC is high, the HIP7030AO's Watchdog Status Register (WSR - location $1 E) provides the ability to selectively
enable and disable the Watchdog Timer logic of the
HIP7030AO.
The user of a development tool should be cautioned against
accidently clearing the WOE bit of this register during final
code prove-out. During initial code development the user
WATCHDOG STATUS REGISTER
Bit 7,6,5,4,3,2 - Unused
Bit 1-WDE
When WOE (WatchDog Enable) is low, the Watchdog Timer is
disabled. When ALC is high, WOE is forced high by any reset.
The WOE bit should normally be cleared when servicing a
breakpoint (if OSCIN is being clocked), to avoid a Watchdog
Reset while interrogating the CPU.
The WOE bit controls the Watchdog Reset, but it doesn't
inhibit the Watchdog Timer from advancing. Prior to reenabling the WOE bit, the Watchdog Timer should normally
be reset by writing $55, $AA to the Watchdog Reset Register
(WDRR, location $10). This implies that each breakpoint
should generate a Watchdog Reset. To verify proper watchdog action the user should run final code with no breaks. In
some cases the number of CPU cycles utilized in the break
may be low enough to allow the watchdog to run without causing premature watchdog timeouts.
Bit O-WDF
The WatchDog flag (WDF), is set when a Watchdog timeout
causes a COP Reset. This flag is used to distinguish a Slow
Clock Detect from a Watchdog Timeout in the COP Reset service routine.
Writing a 0 to the Watchdog Reset Register (WDRR, location
$10) clears the WDF flag. WDF is cleared by Power-on
Reset, but unaffected by all other types of resets. For this reason, WDF should normally be cleared (by writing a 0 to the
WDRR) following each read of the WSR.
~
>I !
PORTO
SFR
REG
PORTO
DIR
REG
8
A
8
INDEX
REGISTER
S
CONDlnON CODE
REGISTER
6
STACK
POINTER
Vss 22
VOO 7
CPU
CONTROL
X
CC
6
RESET
nm
1
VPWSYMBOL
ENCODER I
~
DECODER AND
ARBITRAnON
CPU
S
5
PROGRAM
COUNTER HIGH PCH
8
PROGRAM
COUNTER LOW
2110 x 8
ROM
5
SYMBOLINT
ACCUMULATOR
,?
?
PA3
PA4
PAS
PA6
PA7
z
I
15
PA2.~
UI
W
~ j
nMERSYSTEM
OSCOUT
! 24
INTERNAL
PROCESSOR
~
176 x 8
STAnC RAM
VPWOUT
VPWIN
~ SCK
~ MOSI
MISO
SPI
SYSTEM
~
ALU
~ SS
f
PCL
I
r++
ro-L
INTERNAL PROCESSOR
II
j
CL;CK
WATCHDOG AND
SLOW CLOCK DETECT
I
242x8
BUILT-IN·TEST
ROM
J!?
XW::::l
..JO
Q.!!;;
-0
!:i.
::::1:5
:5:5
oo
9·51
Specifications HIP7030A2
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Voo) ......................... -o.3V to +7.0V
Input or Output Voltage
Pins with Voo Diode ..................... -o.3V to Voo+O.3V
Pins without Voo Diode ...................... -o.3V to +10V
Current Drain Per Pin, I (Excluding Voo and Vss) •••••.••• 2SmA
Lead Temperature (Soldering lOs) •.••••••••••••••••• +26SoC
ESD Classification ................................ Class 2
Gate Count. .................................. 9000 Gates
Thermal Resistance
9JA
Plastic DIP Package ............................ 60·CIW
Plastic SOIC Package ........................... 7S·CIW
Maximum Package Power Dissipation at +12SOC
DIP Package ................................... 41SmW
SOIC Package .................................. 32SmW
Operating Temperature Range (TAJ •.•••••.••••• -40·C to +12S·C
Storage Temperature Range (TSTG) •••••...•... -6S·C to +IS0·C
Junction Temperature .............................. +15O"C
CAUTION: Stresses above those listed in 'Absolute Maximum RaUngs' may cause psrmsnent damage to the device. This is a stress only IBting and opBIB/ion
of the device at these or any other condiUons above thoss Indicated in the opeIBtional secUons of this specification is not implied.
Operating Conditions
Operating Voltage Range ......••••.•••...••.• +3.0V to +S.SV
Operating Temperature Range .....•.•.....•.. -40·C to +12S·C
Input Low Voltage .............................. OV to +O.SV
DC Electrical Specifications
Input High Voltage •.•••.•••....•.....••.•...(O,S·Voo) to Voo
Input Rise and Fall Time
CMOS Inputs ................................ lOOns Max.
CMOS Schmitt Inputs ........................... Unlimited
voo = sVoc ±100/0, vss = oVoc , TA = -40·C to +12SOC Unless Otherwise Specified.
PARAMETER
Output Voltage
SYMBOL
VOL
CONDITIONS
ILOAO < ±1011A
VOH
Output High Voltage: PAO-7, PDO-4, VPWOUT,
TCMP
VOH
ILOAO = -O.SmA
MIN
TYP
MAX
UNITS
-
0.1
V
Voo -0.1
-
V
Voo -O.S
Voo -0.4
-
V
V
Output High Voltage: OSCOUT
VOH
ILOAD = TBD
TBD
TBD
Output High Voltage: MISO, MOSI, SCK, OSCB
VOH
ILOAD = -1.SmA
Voo -o.S
Voo -0.4
Output Low Voltage
VOL
ILOAD = 1.6mA
0.4
V
VIH
-
0.2
Input High Vol~e: PAO-7, PDO-4, VPWIN,
MISO, MOSI, SS, SCK
O.S-Voo
0.7·Voo
V
V
Input High Voltage: RESET, IRQ,TCAP, OSCIN
VIH
O.4S·Voo
0.6·Voo
o.a·voo
V
Input Low Vol~: PAO-7, PDO-4, VPWIN,
MISO, MOSI, SS, SCK
VIL
0.3·Voo
O.S·Voo
-
V
Input Low Voltage: RESET, IRQ, TCAP, OSCIN
VIL
0.2·Voo
O.40Voo
O.SS·Voo
V
Input Hysteresis Voltage: RESET, IRQ, TCAP,
OSCIN
VHYS
O.I·Voo
1.0
O.S-Voo
V
IRUN
-
Supply Current
RUN
WAIT
IWAIT
STOP
ISTOP
TA = 2S·C
TA = -40°C to +12SoC
a
TBD
mA
3.2
TBD
rnA
2
TBD
IIA
10
TBD
IIA
±D.Ol
+10
IIA
I/O Porls Hi-Z Leakage Current: PAO-7, PD0-4,
MISO, MOSI, SCK
IlL
-10
Input Cu~ESET, IRQ, TCAP,
OSCIN, VPWIN
liN
-1
.001
+1
IIA
Capacitance: (Note 2)
COOT
-
12
pF
a
pF
Powerdown Input Voltage: RESET, IRQ,
VPWIN, OSCIN
VINPO
-
7
V
-
CIN
Voo=O
9-52
-0.3
Specifications HIP7030A2
DC Electrical Specifications
voo
=sVoc ±10%. Vss =oVoc• TA =-4Q°C to +12S0C Unless Otherwise Specified. (Continued)
PARAMETER
Comparator:
Inpul Voltage: V2• V3• VREF
Input Current:
V2• Va. VREF
OIfsat Voltage
Response
MIN
TYP
MAX
VIN
Vss-O·2
V
-1
-
Voo+0.02
liN
+1
IIA
20
-
mV
2
-
lIS
SYMBOL
CONDITIONS
-
VOFF
IR
UNITS
NOTES:
1. This device contains circuitry to protect the Inputs against damage due to high static voltages 01 electric fields; however. It Is advised that
normal precautions be taken to avoid application 01 any voltage higher than maximum rated voltages to this high impedance circuit. For
proper operation it is recommended that YIN and VOUT be constrained to \he range VSS«V'N or VOUT)----1
ORR BIT - .......---1---1
J1850 BUS INTERFACE
DATA BIT -----1>----1
ORR BIT - .......---1---1
16-BITTIMER
The VPW Symbol Encoder/Decoder (SEN DEC) block provides the designed with all the features needed to send and
received properly timed messages on a J 1850 Class B Multiplexed Bus. Refer to VPW Symbol EncoderlDecoder (SENDEC) for detailed documentation on the use of the SENOEC.
The integrated 16-bit Timer includes both capture and compare features. External events can be timed, pulses generated, and periodic interrupts programmed. A sophisticated
set of control and status registers allows interrupt or polled
operation. For a detailed guide to the operation of the Timer
refer to Programmable Timer.
INTERNAL LOGIC
SERIAL PERIPHERAL INTERFACE(SPI)
FIGURE 7. ANALOG INPUT 110 PINS
The circuitry of the clocked comparator consists of a differential amplifier with requisite current sources, auto-zero storage elements, and multiplexing switches. It is convenient to
view it as a conventional differential comparator to which
P04 is connected as a "reference" at the negative input and
P02 and P03 are connected via a multiplexer at the positive
input. The comparator is enabled be setting the CMPE bit
(bit 5) of SFRO and disabled by clearing CMPE. To conserve
power the comparator should be disabled when not in use.
RESET clears the CMPE bit. The three analog inputs function properly with inputs from -0.3V to Voo +0.3V.
In order to use the comparator, P04 and either (or both) P02
or(and) P03 should be selected as inputs via the 002, 003,
and 004 bits in OORO. The results of the last comparison
are available each time the PortO register is read. The CMP2
bit of PortO is set if P02 was greater than P04 during the
last comparison and cleared otherwise. Similarly, the CMP3
bit of PortO is set if P03 was greater than P04 during the
last comparison and cleared otherwise. CMP2 and CMP3
are not affected by RESET.
The HIP7030A2 includes a hardware sequencer to control
the auto-zero function and input multiplexer of the comparator. Each complete compare cycle consists of a series of:
1. Auto Zero
2. Compare V2, write results to CMP2
The serial peripheral interface (SPI) is a synchronous serial
interface with separate input, output, and clock lines. The
SPI uses the MISO (serial data inputloutP!:!!1 MOSI (serial
data outputlinput), SCK (serial clock), and SS (slave select)
pins. Refer to Serial Peripheral Interface for a detailed discussion of the SPI system.
Memory Organization
The HIP7030A2 MCU is capable of addressing 8192 bytes
of memory and I/O registers with its program counter. The
MCU has implemented 2520 bytes of these locations as
shown in Figure 8. The first 256 bytes of memory (page
zero) include: 24 bytes of I/O features such as data ports,
the port OORs, Timer, serial peripheral interface (SPI), and
J 1850 VPW Registers; 48 bytes of user ROM, and 176 bytes
of RAM. The next 2048 bytes complete the user ROM. The
Built-In-Test ROM (228 bytes) and Built-In-Test vectors (14
bytes) are contained in memory locations $1FOO through
$1 FF1. The 14 highest address bytes contain the user
defined reset and the interrupt vectors. Eight bytes of the
lowest 32 memory locations are unused and the 176 bytes
of user RAM include up to 64 bytes for the stack. Since most
programs use only a small part of the' allocated stack locations for interrupts and/or subroutine stacking purposes, the
unused bytes are usable for program data storage.
CPU Registers
3. Auto Zero
4. Compare V3, write results to CMP3
The hardware sequencer is enabled via the CMPE bit. Once
enabled the compare cycling is performed continuously at a
1MHz step rate until CMPE is set low. A complete cycle
takes 41!s. It follows that, at any given time, the results read
in CMP2 or CMP3 of the PortO Data Register can be, at
most.4I!S old.
The CPU contains five registers, as shown in the programming model of Figure 9. The interrupt stacking order is
shown in Figure 10.
ACCUMULATOR (A)
The accumulator is an 8-Bit general purpose register used to
hold operands, results of the arithmetic calculations, and
data manipulations.
9-62
HIP7030A2
INDEX REGISTER (X)
Zero (Z)
The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index register is also used for data manipulations with the read-modify-write type of instructions and as a temporary storage
register when not performing addressing operations.
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation is zero.
PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the processor.
STACK POINTER (SP)
The stack pOinter is a 13-bit register containing the address
of the next free locations on the pushdown/popup stack.
When accessing memory, the most significant bits are permanently configured to 0000011. These bits are appended
to the six least significant register bits to produce an address
within the range of $OOFF to $OOCO. The stack area of RAM
is used to store the return address on subroutine calls and
the machine state during interrupts. During external or
power-on reset, and during a reset stack pointer (RSP)
instruction, the stack pointer is set to its upper limit ($OOFF).
Nested interrupt and/or subroutines may use up to 64 (decimal) locations. When the 64 locations are exceeded, the
stack pointer wraps around and pOints to its upper limit
($OOFF), thus, losing the previously stored information. A
subroutine call occupies two RAM bytes on the stack, while
an interrupt uses five RAM bytes.
CarrylBorrow (C)
Indicates that a carry or borrow out of the arithmetic logic
unit (AlU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions,
shifts, and rotates.
Built-In-Test (BIT)
The Built-In-Test (BIT) capability of the HIP7030A2 MCU
provides a simple, efficient means to test the device functionality. The BIT mode is entered ~pplying a 9V oc input
(through a 4.7KO resistor) to the IRQ pin and 5V oc input
(through a 4.7Kn resistor) to the TCAP pin and then
depressing the reset switch to execute a RESET. After
RESET, the MCU will begin executing the BIT code stored at
locations $lFOD-$lFF1. The COP system remains active
during BIT.
The BIT routines utilizes the SPI capability of the
HIP7030A2. When the BIT is initially accessed the SPI is
configured in slave mode and the routine waits for a command to be received via the SPI. There are five defined commands:
Download and Execute - Command 1($01)
The condition code register is a 5-bit register which indicates
the results of the instruction just executed as well as the
state of the processor. These bits can be individually tested
by a program and specified action taken as a result of their
state. Each bit is explained in the following paragraphs.
Fill RAM with data and begin execution at location $62. After
receiving a $01 command, the BIT routines read the next
176 bytes of data received via the SPI and place each byte
in successive RAM locations beginning at location $50. The
SPI master is responsible for pacing the transmission to
allow the HIP7030A2 to process each received byte. XXX
clocks are required between transfers. Once all 176 bytes
are received the HIP7030A2 jumps to location $62 and
begins execution. SP is cleared before jumping to $62.
Returning to the BIT routine can be accomplished by
branching to location $1 FOO.
Half Carry Bit (H)
Dump ROM - Command 2($02)
The H bit is set to a one when a carry occurs between bits 3
and 4 of the AlU during an ADD or ADC instruction. The H
bit is useful in binary coded decimal subroutines.
After receiving a $02 command, the BIT software "dumps"
the contents of ROM. Beginning with locations $0020
through $003F, followed by locations $0100 through $08FF,
and ending with locations $lFoo through $lFFF the ROM
contents are transferred byte by byte on the SPI bus. The
HIP7030A2 remains in slave mode, and the master is
responsible for pacing the transmission to allow the
HIP7030A2 to retrieve each ROM byte. XXX clocks are
required between transfers. After all bytes have been transferred the BIT software once again waits for a command.
Since the Stack Pointer decrements during pushes, the PCl
is stacked first, followed by PCH, etc. Pulling from the stack
is in the reverse order.
CONDITION CODE REGISTER (CC)
Interrupt Mask Bit (I)
When the I bit is set, all interrupts are disabled. Clearing this
bit enables the interrupts. If an external interrupt occurs
while the I bit is set, the interrupt is latched and processed
after the I bit is next cleared; therefore, no interrupts are lost
because of the I bit being set. An internal interrupt can be
lost if it is cleared while the I bit is set (refer to Programmable
Timer, Serial Communications Interface, and Serial Peripherallnterface Sections for more information).
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation is negative (bit 7 in the
result is a logic one).
Read Page 0 - Command 3($03)
After receiving a $03 command, the BIT software waits for
an address byte to be received. The address points to a
location on page 0, the contents of which are read and
placed in the SPI data register for transfer to the master.
After receiving the command and address bytes and placing
the value read in the SPI register, the BIT routines wait for
9-63
HIP7030A2
$0000
0000
VO
32 BYTES
$0011
$0020
0031
\
0079
0080
,,
,,
,
\
RAM
176 BYTES
SOOBF
$OOCO
"...............................................
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
USER
ROM
2048 BYTES
\
2303
2304
UNUSED
5632 BYTES
$1EFF
$1FOO
$04
UNUSED
2 BYTES
UNUSED
$06
UNUSED
$06
PORTS
2 BYTES
PORT D DATA DIRECTION REGISTER
$07
PORT D SPECIAL FUNCTION REGISTER
$08
7935
7936
$lFFF
$OB
$DC
UNUSED
$OD
UNUSED
$OE
$OF
SEN DEC STATUS REGISTER
$10
SENDEC DATA REGISTER
$11
UNUSED
1 BYTE
TIMER CONTROL REGISTER
$12
TEST
1 BYTE
TIMER STATUS REGISTER
S13
INPUT CAPTURE HIGH REGISTER
$14
INPUT CAPTURE LOW REGISTER
$15
0031
OUTPUT COMPARE HIGH REGISTER
$16
,,
,,
,,
,,
,,
,,
,
OUTPUT COMPARE LOW REGISTER
$17
COUNTER HIGH REGISTER
$18
COUNTER LOW REGISTER
$19
ALTERNATE COUNTER HIGH REGISTER
$lA
ALTERNATE COUNTER LOW REGISTER
$lB
UNUSED
$lC
WATCHDOG RESET REGISTER
$lD
WATCHDOG
2 BYTES
8177
\
\
\
8178
USER
VECTORS
14 BYTES
SERIAL PERIPHERAL STATUS REGISTER
SERIAL PERIPHERAL DATA VO REGISTER
SENDEC CONTROL REGISTER
256 BYTES
SlFF1
$1FF2
$OA
TIMER
10 BYTES
"",""........, ................""....,.......,
BUILT-IN-TEST
VECTORS
$OD
SERIAL PERIPHERAL CONTROL REGISTER
SENDEC INTERFACE
3 BYTES
BUILT-IN-TEST
SlFE1
SlFE2
UNUSED
UNUSED
2 BYTES
0255 ~
0256 ,
$08FF
$0900
$03
PORT A DATA DIRECTION REGISTER
SERIAL PERIPHERAL
INTERFACE
3 BYTES
\
$OOFF
$0100
$02
PORT D DATA REGISTER
UNUSED
1 BYTE
0191
0192,
STACK
64 BYTES
$01
UNUSED
PORTS
2 BYTES
,
$004F
$0050
$00
UNUSED
UNUSED
2 BYTES
,,0032
USER
ROM
48 BYTES
PORT A DATA REGISTER
0000
PORTS
1 BYTE
,
,,
\
8191
WATCHDOG STATUS REGISTER
$lE
TEST REGISTER (NOTE 1)
$lF
NOTE:
1. Accessible In Test Mode Only
FIGURE 8_ MEMORY MAP OF THE HIP7030A2
o
7
1
A
1 ACCUMULATOR
o
7
I
x
PC _ _ _ _. .JI
IL -_ _ _ _....:..;~
12
DECREASING
MEMORY
ADDRESS
1 INDEX REGISTER
o
12
7
,-,I0'-'1...;;0.....1..:..0....1 0~10'-'1....:.1.....1...;..1.....I __s;;;p_---'I
4
I
1 1111 1
CONDITION CODE REG
ACCUMULATOR (AI
STACK POINTER
INDEX REGISTER IX)
0
~
N Z C
o
7
PROGRAM COUNTER
0
o 1 0 1 0 1 PROGRAM COUNTER HIGH
CONDITION CODE REG
CARRYIBORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
PROGRAM COUNTER LOW
INCREASING
MEMORY
ADDRESS
FIGURE 10_ STACKING ORDER DURING INTERRUPTS
FIGURE 9_ CPU REGISTER SET
9-64
HIP7030A2
the data to be transferred and then resume looking for a
command. The master is responsible for pacing the transmission to allow the HIP7030A2 time to read the data byte.
XXX clocks are required between transfers.
ReadlWrlte Page 0 - Command 4($04)
After receiving a $04 command. the BIT software waits for
an address byte to be received. The address points to a
location on page O. the contents of which are read and
placed in the SPI data register for transfer to the master.
After receiving the command and address bytes and placing
the value read in the SPI register, the BIT routines wait for
the master to send a data byte (and to simultaneously
unload the data which was placed in the SPDR). Upon
receiving the new data byte. the BIT program writes the new
data to the selected page 0 location. After completing the
write. the BIT routines resume looking for a command. The
master is responsible for pacing the transmission to allow
the HIP7030A2 to properly process the address and data
bytes. XXX clocks are required between transfers. Writing to
the upper 20 bytes of RAM (subroutine stack) or to the SPI
registers can cause the BIT routine to malfunction.
Checksum - Command 5($05)
After receiving a $05 command. the BIT software calculates
the checksum of all bytes in ROM space and places the
result in the SPI data register for reading. The master is
responsible for pacing the transmissions to allow the
HIP7030A2 to properly calculate the checksum byte. XXX
clocks are required between issuing the command and reading the result.
Resets
The MCU has three reset modes: an active low external
reset pin (RESET). a power-on reset function. and a Computer Operating Properly (COP) reset function.
"Fi"ESE'f Pin
The RESET input pin is used to reset the MCU to provide an
orderly software sta!!:.!:!E..£!"ocedure. When using the external reset mode. the RESET pin must stay low for a minimum
of one and one half teye. The RESET pin contains an internal Schmitt Trigger as part of its input to improve noise
immunity.
Power-On Reset
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for a
4064 teye delay from the time that the oscillator becomes
active to allow for stabilization (see Figure 11). If the external
RESET pin is low at the end of the 4064 teye time out. the
processor remains in the reset condition until RESEi' goes
high. Table 3 shows the actions of the two resets on internal
circuits, but not necessarily in order of occurrence (X indicates that the condition occurs for the particular reset).
COP Reset
The COP reset is generated by either of two events: 1) the
Watchdog Timer reaches its maximum value prior to being
cleared. or 2) the Slow Clock Detect circuitry doesn't detect
a transition on the OSCIN pin during a period of approximately 2~s. The COP reset is identical to an external
RESET pin reset. except the Program Counter is loaded with
the address at $1 FFA-$l FFB instead of the address at
$lFFE-$lFFF and the Watchdog Flag (bit 0) is set in the
Watchdog Status Register (WSR. location $1 E). COP
Resets are discussed under Interrupts.
Interrupts
Systems often require that normal processing be interrupted
so that some external event may be serviced. The
HIP7030A2 may be interrupted by one of six different m~
ods: either one of four maskable hardware interrupts (IRQ.
SPI, SENDEC. or Timer). one non-maskable Watchdog!
Slow Clock Detect interrupt. and one non-maskable software
interrupt (SWI). Interrupts such as Timer. SPI. and SEN DEC
have several flags which will cause the interrupt. Generally.
interrupt flags are located in read-only status register.
whereas their equivalent enable bits are located in associated control registers. The interrupt flags and enable bits are
never contained in the same register. If the enable bit is a
logic zero it blocks the interrupt from occurring but does not
inhibit the flag from being set. Reset clears all enable bits to
preclude interrupts during the reset procedure. The general
sequence for clearing an interrupt is a software sequence of
first accessing the status register while the interrupt flag is
set. followed by a read or write of an associated register.
When any of these interrupts occur. and if the enable bit is a
logic one, normal processing is suspended at the end of the
current instruction execution. Interrupts cause the processor
registers to be saved on the stack (see Figure 12) and the
interrupt mask (I bit) set to prevent additional interrupts. The
appropriate interrupt vector then points to the starting
address of the interrupt service routine (refer to Table 4 for
vector location). Upon completion of the interrupt service
routine, the RTI instruction (which is normally a part of the
service routine) causes the register contents to be recovered
from the stack followed by a return to normal processing.
The stack order is shown in Figure 12.
NOTE: The interrupt mask bit (I bit) will be cleared if and only
if the corresponding bit stored in the stack is zero. A discussion of interrupts, plus a table listing vector addresses for all
interrupts including RESET. in the MCU is provided in Table 4.
Hardware Controlled Interrupt Sequence
The following three functions (RESET. STOP, and WAIT) are
not in the strictest sense an interrupt; however. they are
acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Figure 13. and for STOP and WAIT
are provided in Figure 14. A discussion is provided below.
(a) RESET - A low input on the RESET input pin causes the
program to vector to its starting address which is specified
by the contents of memory locations $lFFE and $lFFF. The
I bit in the condition code register is also set. Much of the
9-65
~
Xw:::l
....JO
a..!!:
-0
~
:::I:E
:E:E
.
oo
HIP7030A2
TABLE 3.
iiESEi' PIN, COP, AND POR ACTIONS ON INTERNAL CIRCUITRY
RESETPINI
COP RESET
POWER·ON
RESET
TImer Prescaler Reset to Zero State
X
X
TImer Counter Configure to $FFFC
X
X
TImer Output Compare (TCMP) Bit Reset to Zero
X
X
All TImer Interrupt Enable Bits Cleared (ICIE, OCIE, and TOlE) to Disable TImer Interrupts
X
X
TImer Output Level (OLVL) Bit is Cleared
X
X
Port A and Port D Data Direction Registers (DDRA and DDRD) Cleared to Zero, Placing
all Port Pins in Input Mode
X
X
CONDITION
Port D Special Function Register Bit CMPE is Cleared Disabling Comparator
X
X
Set Stack Pointer (SP) to $OOFF
X
X
Force Internal Address to RESET Vector ($1FFE)
X
X
Set I Bit In Condition Code Register (CC) to 1; Disabling all Maskable Interrupts
X
X
Clear STOP Latch
X
X
Clear WAIT Latch
X
X
(Note 1)
X
Reset Oscillator Stabilization Delay To 4064
Clear External Interrupt (Irq) Flip·flop
X
X
VPWOUT Set Low (passive state)
X
X
Slow Clock Detect Circuitry Reset
(Note 1)
X
X
X
(Note 2)
(Note 2)
Watchdog TImer Interrupt Latch Cleared
X
X
Serial Peripheral Interface (SPI) Control Bits SPIE, MSTR, SPIF, WCOL, and MODF
Cleared; Disabling SPI Interrupts and Setting to Slave Mode
X
X
Watchdog Timer Reset to Zero State
Watchdog Flag (WDF) Cleared/Set in Watchdog Stetus Register (WSR)
NOTES:
1. Only If MCU is In STOP state; If NDEL is set In the SENDEC Control Register a delay of 128 Is used for RESET/COP.
2. WDF Is cleared by POR and RESET and Is set by a Watchdog Reset.
Voo
OSCIN
(NOTE 2)
INTERNAL
PROCESSOR
CLOCK (NOTE 1)
INTERNAL
ADDRESS BUS
(NOTE 1)
INTERNAL
DATA BUS
(NOTE 3)
(NOTE 3)
NOTES:
1. Internal signal and bus Information Is not available externally.
2. OSCIN is not mean to represent frequency. It is only mean to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET Initiates the reset sequence.
FIGURE 11. POWER·ON RESET AND iiESEi'
9·66
HIP7030A2
TABLE 4. VECTOR ADDRESSES FOR INTERRUPTS AND RESETS
INTERRUPT NAME
INTERRUPTS SOURCE
VECTOR ADDRESS
REGISTER
FLAG NAME
NlA
NlA
RESET
RESET
$1 FFE-$l FFF
NlA
NlA
Software
SWI
$1 FFC-$l FFD
NlA
NlA
Watchdog Timeout
COP
$lFFA-$lFFB
SENDEC
$1 FFB-$l FF9
Slow Clock Detect
SEN DEC Status
(SEDSR)
TX
Transition Detected
BRK
Break Detected
NEW
IFS orSOF
NECHO
Echo Failure
NlA
NlA
External Interrupt
TIMER Status
(TSR)
ICF
Input Capture
OCF
Output Compare
TOF
Timer Overflow
SPIF
Transfer Complete
SPI Status
(SPSR)
MODF
IRQ
$1 FF6-$1 FF7
TIMER
$1 FF4-$1 FF5
SPI
$1 FF2-$1 FF3
Mode Fault
Voo- D
Q
-
EXTERNAL
~ INTERRUPT
REQUEST
INTERR~~
_
>C
I BIT (CC)
R
Q
POWER-ON RESET
EXTERNAL RESET
COP RESET
EXTERNAL
INTERRUPT
BEING SERVICED
(READ OF VECTORS)
FIGURE 12A. INTERRUPT FUNCTION DIAGRAM
iRQ
=::t....J:=
I..
U
tlLIH
..I
tlLlL
FIGURE 12B. INTERRUPT TIMING DIAGRAM
FIGURE 12. EXTERNAL INTERRUPT
9-67
HIP7030A2
FROM RESET
y
y
y
CLEAR iRc.i
EDGE TRIGGERED
FLIP·FLOP
y
LOAD PC FROM
SENDEC:$1FFS· $1FFg
IRQ: 51 FF6 • $1 FF7
TlMER:$1FF4- $1FFS
SPI: $1 FF2- $1 FF3
COMPLETE
INTERRUPT
ROUTINE
AND EXECUTE
RTI
y
FIGURE 13. HARDWARE INTERRUPT FLOW DIAGRAM
MCU is configured to a known state during this type of reset
as previously described in RESETS paragraph.
(b) STOP· The STOP instruction causes the oscillator to be
turned off and the processor to "sleep" until an external inter·
rupt (IRQ) or reset occurs. The VPWOUT pin is forced to a
low level, the SPI is set to slave mode, and all other pins
remain at their previously set levels.
(c) WAIT· The WAIT instruction causes all processor clocks
to stop, but leaves the Timer, the Watchdog, SEN DEC, and
SPI clocks running. This "rest" state of the processor can be
cleared by RESET, Slow Clock Detect, an external interrupt
(IRQ), Timer interrupt, SPI interrupt, or SEN DEC interrupt.
There are no special "wait mode" vectors for these interrupts.
Software Interrupt (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware inter·
rupts. The SWI is executed regardless of the state of the
interrupt mask (I bit) in the condition code register. The inter·
rupt service routine address is specified by the contents of
memory location $1FFC and $1FFD.
COP InterruptlReset
The Computer Operating Properly (COP) system consists of
two functions: 1) the Watchdog Timer, and 2) the Slow Clock
Detect Circuit. These interrupts cause a complete system
restart and the effect is identical in every respect to an exter·
nally generated RESET pin reset, except the restart address
is taken from locations $1 FFA and $1 FFB and the Watchdog
Flag (bit 0) is set in the Watchdog Status Register (WSR,
location $1 E) if the reset was the result of a Watchdog Timer
overflow. Starting the PC with an address different than the
standard RESET address allows the system to provide an
appropriate response to the situation.
Because the CPU is reset during a COP Interrupt, the COP
service routine must not exit with an RTI. Instead the routine
should branch to subsequent code.
Since the most likely cause of a Slow Clock Detect is a malfunctioning OSCillator, a COP Interrupt caused by a Slow
Clock Detect will generally reset the MCU per Table 3 and
remain in the RESET state.
9-68
HIP7030A2
SENDEe Interrupt
The VPW Symbol Encoder/Decoder (SEN DEC) system has
four different interrupt flags that will cause a SEN DEC interrupt whenever they are set and enabled. These four interrupt
flags are found in the SENDEC status register (SEDSR.
location $10) and all will vector to the same interrupt service
routine ($1 FFB - $1 FF9). One of the interrupt flags (TX transition) has a corresponding enable bit in the SENDEe
control register (SEDCR. location $OF). RESET clears the
enable bit. thus preventing a TX interrupt from occurring during the reset time period. The other three interrupts (BRK break. NECHO - no echo. and NEW - new frame) are nonmaskable at the SENDEe level. The processor responds to
all SEN DEC interrupts only if the I bit in the condition code
register is also cleared. When the interrupt is recognized. the
current machine state is pushed onto the stack and I bit is
set. This masks further interrupts until the present one is
serviced. The interrupt service routine address is specified
by the contents of memory location $1FFB and $lFF9. The
general sequence for clearing an interrupt is a software
sequence of accessing the status register while the flag is
set. followed by a read or write of an associated register.
Refer to VPW Symbol Encoder/Decoder (SENDEC) for additional information about the SEN DEC interrupts.
External Interrupt
If the interrupt mask (I bit) of the condition code register has
been cleared and the external interrupt pin (IRQ) has gone
low. then an external interrupt is recognized. When the interrupt is recognized. the current state of the CPU is pushed
onto the stack and the I bit is set. This masks further interrupts
until the present one is serviced. The interrupt service routine
address is specified by the contents of memory location
$lFF6 and $lFF7. Figure 12 shows both a functional and
mode timing diagram for the interrupt line. The timing diagram
shows treatment of the interrupt line (IRQ) for generating periodic interrupts to the processor. The figure shows single
pulses on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a function of the
number of cycles required to execute the interrupt service routine plus 21 cycles (for interrupt call and return delays). Once
a pulse occurs. the next pulse should not occur until the MCU
software has exited the routine (an RTI occurs).
The internal interrupt latch is cleared in the first part of the
service routine; therefore. one (and only one) external interrupt pulse can be latched during tlLlL and will be serviced as
soon as the I bit is cleared.
Timer Interrupt
set. This masks further interrupts until the present one is
serviced. The interrupt service routine address is specified
by the contents of memory location $1 FF4 and $1 FF5. The
general sequence for clearing an interrupt is a software
sequence of accessing the status register while the flag is
set. followed by a read or write of an associated register.
Refer to Programmable Timer for additional information
about the timer circuitry.
Serial Peripheral Interface (SPI) Interrupts
An interrupt In the serial peripheral Interface (SPI) occurs
when one of the interrupt flag bits in the serial peripheral status register (location SOB) is set. provided the I bit in the condition code register is clear and the enable bit in the serial
peripheral control register (location $OA) is enabled. When
the interrupt is recognized. the current state of the machine
is pushed onto the stack and the I bit in the condition code
register is set. This masks further interrupts until the present
one is serviced. The SPI interrupt causes the program
counter to vector to memory location $1 FF2 and $1 FF3
which contain the starting address of the interrupt service
routine. Software in the serial peripheral interrupt service
routine must determine the priority and cause of the SPI
interrupt by examining the interrupt flag bits located in the
SPI status register. The general sequence for clearing an
interrupt is a software sequence of accessing the status register while the flag is set. followed by a read or write of an
associated register. Refer to Serial Peripheral Interface for a
description of the SPI system and its interrupts.
Low Power Modes
STOP Instruction
The STOP instruction places the MCU in its lowest power consumption mode. In the STOP mode the internal oscillator is
turned off. causing all internal processing to be halted; refer to
Figure 14. During the STOP mode. the I bit in the condition
code register is automatically cleared to enable external and
SEN DEC interrupts. All other registers and memory remain
una~ered and all inpuVoutput lines remain unchanged. except
the VPWOUT line which is forced to a passive (low) state and
the SPI Master bit (MSTR) in the SPI Control Register (SpeR)
which is cleared placing the SPI pins into Slave mode. This
mode persists until an e~interrupt (IRQ). a low on the
VPWIN pin. or a low on RESET is sensed at which time the
internal oscillator is turned on. The interrupt or reset causes
the program counter to vector to the starting address of the
interrupt or reset service routine respectively.
WAIT Instruction
There are three different timer interrupt flags that will cause
a timer interrupt whenever they are set and enabled. These
three interrupt flags are found in the three most significant bits
of the timer status register (TSR. location $13) and all three will
vec.t0r to the same interrupt service routine ($1 FF4 - $1 FF5).
All Interrupt flags have corresponding enable bits (ICIE. OCIE.
and TOlE) in the timer control register (TCR. location $12).
Reset clears all enable bits. thus preventing an interrupt from
occurring during the reset time period. The actual processor
interrupt is generated only if the I bit in the condition code
register is also cleared. When the interrupt is recognized. the
current machine state is pushed onto the stack and I bit is
The WAIT instruction places the MCU in a low power consumption mode. but the WAIT mode consumes somewhat
more power than the STOP mode. In the WAIT mode the
internal clock remains active. and all CPU processi~g is
stopped; however. the programmable timer. serial peripheral
interface. Watchdog Timer. and SEN DEC systems remain
active. Refer to Figure 14. During the WAIT mode. the I bit in
the condition code register is cleared to enable all interrupts.
All other registers and memory remain unaltered and all parallel inpuVoutput lines remain unchanged. This continues
until any interrupt or reset is sensed. At this time the pro-
9-69
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HIP7030A2
OSCILLATOR ACTIVE,
TIMER, SCI, AND SPI
CLOCKS ACTIVE,
PROCESSOR CLOCKS STOPPED
STOP OSCILLATOR AND
CLOCKS, DISABLE COP,
FORCE VPWOUT. 0,
CLEAR I BIT
(1) FETCH RESETICOP VECTOR OR
(2) SERVICE INTERRUPT
A. STACK
B. SETIBIT
C. VECTOR TO INTERRUPT
ROUTINE
(1) FETCH RESETICOP VECTOR OR
(2) SERVICE INTERRUPT
A. STACK
B. SETIBIT
C. VECTOR TO INTERRUPT
ROUTINE
FIGURE 14. STOP AND WAIT FLOW DIAGRAM
gram counter vectors to the memory location ($1 FF2
through $1 FFF) which contains the starting address of the
interrupt or reset service routine.
Data Retention Mode
The contents of RAM and CPU registers are retained at supply voltages as low as 2Voc. This is referred to as the DATA
RETENTION mode, where the data is held, but the device is
not guaranteed to operate.
Programmable Timer
INTRODUCTION
The programmable timer, which is preceded by a fixed
divide-by-four prescaler, can be used for many purposes,
including input waveform measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds. A block
diagram of the timer is shown in Figure 15 and timing diagrams are shown in Figure 16 through 19. Because the timer
has a 16-bit architecture, each specific functional segment
(capability) is represented by two registers. These registers
contain the high and low byte of that functional segment.
Generally, accessing the low byte of a specific timer function
allows full control of that function; however, an access of the
high byte inhibits that specific timer function until the low
byte is also accessed.
The I bit in the condition code register should be set while
manipulating both the high and low byte register of a specific
timer function to ensure that an interrupt does not occur.
This prevents interrupts from occurring between the time
that the high and low bytes are accessed.
The programmable timer capabilities are provided by using
the following ten addressable 8-bit registers (note the high
and low represent the Significance of the byte). A description
of each register is provided below.
Timer Control Register (TCR) locations $12, Timer Status
Register (TSR) location $13, Input Capture High Register
location $14, Input Capture Low Register location $15, Output Compare High Register location $16, Output Compare
Low Register location $17, Counter High Register location
$18, Counter Low Register location $19, Alternate Counter
High Register location $lA, and Alternate Counter Low Register location $1 B.
COUNTER
The key element in the programmable timer is a 16-bit free running counter, or counter register, preceded by a prescaler which
divides the intemal processor clock by four. The prescaler
gives the timer a resolution of 800ns if the internal processor
clock is 5.0MHz. the counter is clocked to increasing values
during the low portion of the internal processor clock. Software
can read the counter at any time without affecting its value.
9-70
HIP7030A2
INTERNAL
PROCESSOR
CLOCK
HIGH
BYTE
LOW
BYTE
$16
$17
~
TIMER .......,..............,
STATUS~~~~~~~
REG.
HIGH
LOW
BYTE
BYTE
HIGH
BYTE
16riJ'~1~~E
$1.
COUNTER
$10
COUNTER
ALTERNATE
REGISTER
$lA
LOW
BYTE
$14
$15
$lB
........,r--....,r--....,.....
~r--.....,
OUTPUT
LEVEL
(TCMP
PIN 2)
EDGE
INPUT
(TCAP
PIN 1)
FIGURE 15. PROGRAMMABLE TIMER BLOCK DIAGRAM
INTERNAL PROCESSOR CLOCK
(INTERNAL RESET)
TOO
Jl..flBJl
n
n
T01 _ _ _ _ _;...._......
INTERNAL TIMER CLOCKS
n
n
T10 _________~--------~
X
COUNTER (16 - BIT)
RESET (EXTERNAL OR END OF PORI
r1
$FFFD
ll1ll1l
NOTE:
1. The Counter Register and the Timer Control Register are the only ones affected by reset.
FIGURE 16. TIMER STATE DIAGRAM FOR RESET
9-71
n
n
n
n
n
X
$FFFE
rL
X
$FFFF
HIP7030A2
INTERNAL PROCESSOR
CLOCK
__________~n
-fl___....rlL..__---'n
~rl. . ___ n
TOO __________
INTERNAL TIMER
CLOCKS
T01
T10 - - 1 1 1 . . . -_ _
...1
rl~----_fn
T11 - - -....
COUNTER (16. BIT)
3 . . __
$_F_F_EC
__
~X~-tj~----..,
$FFED
~!
INPUT EDGE
n
~rl~
INTERNAL CAPTURE LATCH
n
X
r
n
n
rL
X
$FFEE
$FFEF
,'-------
X,,________
INPUT CAPTURE REGISTER _ _ _ _ _ _$_?_??_?_ _ _ _ _
$_FF_E_D_ _ _ _ _ __
INPUT CAPTURE FLAG _ _ _ _---..J/
NOTE:
1. If the input edge occurs In the shaded area from one timer state T1 0 to the next, the input capture flag is set during the next T11.
FIGURE 17. TIMER STATE DIAGRAM FOR INPUT CAPTURE
INTERNAL PROCESSOR CLOCK
n
TOO
T01-fl
INTERNAL TIMER
n
T10--11
T11
COUNTER (16· BIT)
3
n
$FFEC
n
n
X
(NOTE 1)
COMPARE REGISTER
n
n
CPU WRITES $FFED
COMPARE REGISTER
LATCH
,
(NOTE 2)
OUTPUT COMPARE
FLAG (OCF) AND
TCMP (PIN 2)
$FFED
n
n
n
X
n
r
n
rL
$FFEE
X
$FFEF
$FFED
,1/1 \
,I
(NOTE 3)
NOTES:
1. The CPU write to the Compare Register may take place at any time, but a compare only occurs at timer state T01. Thus a 4 cycle differ·
ence may exist between the write to the Compare Register and the actual compare.
2. Internal compare takes place during timer state T01.
3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this example).
FIGURE 18. TIMER STATE DIAGRAM FOR OUTPUT COMPARE
9·72
HIP7030A2
INTERNAL PROCESSOR CLOCK
n
TOO
T01.-n
INTERNAL TIMER
T10~
T11
COUNTER(16-BIT)
3
n
n
n
n
n
X
$FFFF
$0000
n
n
n
n
X
$0001
n
r
n
rL
X
$0002
I
TIMER OVERFLOW
FLAG (TOF)
NOTE:
1. The TOF bit is set at timer state T11 (transition of the counter from $FFFF to $0000). It is cleared by a read of the Timer Status Register
during the internal processor clock high time followed by a read of the Counter Low Register.
FIGURE 19. TIMER STATE DIAGRAM FOR TIMER OVERFLOW
The double byte free running counter can be read from
either of two locations $1B - $19 (called counter register at
this location). or $1A - $1B (counter alternate register at this
location). A read of only the least significant byte (LSB) of
the free running counter ($19. $1B) retrieves the current
count value. If a read of the free running counter first
addresses the most significant byte ($1 B. $1A) the least significant byte is transferred to a buffer. This buffer value
remains fixed after the first most significant byte "read" even
if the user reads the most significant byte several times. This
buffer is accessed when reading the LSB of the free running
counter or counter alternate register ($19. $1B). if the most
significant byte is read. the least significant byte must also
be read in order to complete the sequence.
The free running counter is configured to $FFFC during reset
and is always a read-only register. During a power-on-reset
(POR). the counter is also configured to $FFFC and begins
running after the oscillator start-up delay. Because the free
running counter is 16 bits preceded by a fixed divide-by-four
prescaler. the value in the free running counter repeats every
262.144 MPU internal processor clock cycles. When the
counter rolls over from $FFFF to $0000. the timer overflow flag
(TOF) bit is set. An interrupt can also be enabled when counter
rollover occurs by setting its interrupt enable bit (TOlE).
OUTPUT COMPARE REGISTER
The output compare register is a 16-bit register. which is
made up of two B-bit registers at locations $16 (most significant byte) and $17 (least significant byte). The output compare register can be used for several purposes such as.
controlling an output waveform or indicating when a period of
time has elapsed. The output compare register is unique in
that all bits are readable and writable and are not altered by
the timer hardware. Reset does not affect the contents of
this register and if the compare function is not utilized. the
two bytes of the output compare register can be used as
storage locations.
The contents of the output compare register are compared
with the contents of the free running counter once during
every four internal processor clocks. If a match is found. the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) btt is clocked (by the output
compare circutt pulse) to an output level register. The values in
the output compare register and the output level btt should be
changed after each successful comparison in order to control
an output waveform or establish a new elapsed timeout. An
interrupt can also accompany a successful output compare
provided the corresponding interrupt enable bit. OCIE. is set.
After a processor write cycle to the output compare register
containing the most significant byte ($16). the output compare
function is inhibited until the least significant byte ($17) is also
written. The user must write both bytes (locations) if the most
significant byte is written first. A write made only to the least
significant byte ($17) will not inhibit the compare function. The
free running counter is updated every four internal processor
clock cycles due to the internal prescaler. The minimum time
required to update the output compare register is a function of
the software program rather than the internal hardware.
A processor write may be made to either byte of the output
compare register without affecting the other byte. The output
level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear.
Because neither the output compare flag (OCF bit) nor the
output compare register is affected by RESET. care must be
exercised when initializing the output compare function with
software. The following procedure is recommended:
9-73
1. Write the high byte of the output compare register to inhibit further compares until the low byte is written.
2. Read the timer status register to arm the OCF if it is already set.
3. Write the output compare register low byte to enable the
output compare function with the flag clear.
HIPl030A2
The advantage of this procedure is to prevent the OCF bit
from being set between the time it is read and the write to
the output compare register. A software example is shown
below.
B716 STA OCMPHI;
B613 LOA TSTAT;
BF17 STX OCMPLO;
INHIBIT OUTPUT COMPARE
ARM OCF BIT IF SET
READY FOR NEXT COMPARE
B7, ICIE
If the input capture interrupt enable (ICIE) bit is
set, a timer interrupt is enabled when the ICF
status flag (in the timer status register) is set. If
the ICIE bit is clear, the interrupt Is inhibited.
The ICIE bit is cleared by RESET.
B6, OCIE
If the output compare interrupt enable (OCIE)
bit is set, a timer interrupt is enabled whenever
the OCF status flag is set. If the OCIE bit is
clear, the interrupt is inhibited. The OCIE bit is
cleared by RESET.
B5, TOlE
If the timer overflow interrupt enable (TOlE) bit
is set, a timer interrupt is enabled whenever
the TOF status flag (in the timer status regiSter) is set. If the TOlE bit is clear, the interrupt
is inhibited. The TOlE bit is cleared by RESET.
B1,IEOG
The value of the input edge (IEOG) bit determines which level transition on pin 1 will trigger
a free running counter transfer to the input capture register. Reset does not affect the IEOG
bit.
INPUT CAPTURE REGISTER
The two S-bit registers which make up the 16-bit input capture register are read-only and are used to latch the value of
the free running counter after a defined transition is sensed
by the corresponding input capture edge detector. The level
transition which triggers the counter transfer is defined by
the corresponding input edge bit (IEOG). The selected edge
is also fed to the Port 0 strobed output pins (see Port 0
Strobed Output Mode). Reset does not affect the contents of
the input capture register.
The result obtained by an Input capture will be one more
than the value of the free running counter on the rising edge
of the internal processor clock preceding the external transition (refer to timing diagram shown in Figure 17). This delay
is required for internal synchronization. Resolution is
affected by the prescaler allowing the timer to only increment
every four internal processor clock cycles.
After a read of the most significant byte of the input capture
register ($14), counter transfer is inhibited until the least significant byte ($15) of the input capture register is also read.
This characteristic forces the minimum pulse period aHainable to be determined by the time used in the capture software routine and its interaction with the main program. The
free running counter increments every four internal processor clock cycles due to the prescaler.
A read of the least significant byte ($15) of the input capture
register does not inhibit the free running counter transfer. Again,
minimum pulse periods are ones which allow software to read
the least significant byte ($15) and perform needed operations. There is no conflict between the read of the input capture
register and the free running counter transfer since they occur
on opposite edges of the internal processor clock.
o=negative edge
1 = positive edge
BO, OLVL
o =low output
1 = high output
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) is an S-bit register of which
the three most significant bits contain read-only status information. These three bits indicate the following:
1. A proper transition has taken place at the TCAP pin with
an accompanying transfer of the free running counter
contents to the input capture register,
2.A match has been found between the free running
counter and the output compare register, and
TIMER CONTROL REGISTER (TCR)
The timer control register (TCR, location $12) is an S-bit
read/write register which contains five control bits. Three of
these bits control interrupts associated with each of the
three flag bits found in the timer status register (discussed
below). The other two bits control: 1) which edge is significant to the capture edge detector (I.e., negative or positive),
and 2) the next value to be clocked to the output level register in response to a successful output compare. The timer
control register and the free running counter are the only
sections of the timer affected by RESET. The TCMP pin is
forced low during external reset and stays low until a valid
compare changes it to a high. The timer control register is
illustrated below followed by a definition of each bit.
The value of the output level (OLVL) bit is
clocked into the output level register by the
next successful output compare and will
appear at pin 2. This bit and the output level
register are cleared by RESET.
3. A free running counter transition from $FFFF to $0000
has been sensed (timer overflow).
The timer status register is illustrated below followed by a definition of each bit. Refer to timing diagrams shown in Figures 13,
14, and 15 for timing relationship to the timer status register bits.
7
3
2
ICF
o
o
o
o
o
TSR (LOCATION $13)
B7, ICF
9-74
The input capture flag (ICF) is set when a
proper edge has been sensed by the input
capture edge detector. It is cleared by a processor access of the timer status register (with
ICF set) followed by accessing the low byte
($15) of the input capture register. Reset does
not affect the input compare flag.
HIP7030A2
B6. OCF
B5. TOF
Serial Peripheriallnteriace (SPI)
The output compare flag (OCF) is set when the
output compare register contents match the
contents of the free running counter. The OCF
is cleared by accessing the timer status register (with OCF set) and then accessing the low
byte ($17) of the output compare register.
Reset does not affect the output compare flag.
INTRODUCTION
The serial peripheral interface (SPI) is an interface buik into
the MCU which allows several MCUs. or one MCU plus
peripheral devices. to be interconnected within a single "black
box" or on the same printed circuit board. In a serial peripheral
interface (SPI). separate wires (signals) are required for data
and clock. In the SPI format. the clock is not included in the
data stream and must be furnished as a separate signal. An
SPI system may be configured as one containing one master
MCU and several slave MCUs. or in a system in which an
MCU is capable of being either a master or a slave.
The timer overflow flag (TOF) bit is set by a
transition of the free running counter from
$FFFF to $0000. It is cleared by accessing the
timer status register (with TOF set) followed by
an access of the free running counter least significant byte ($19). Reset does not affect the
TOFbit.
Accessing the timer status register satisfies the first condition required to clear any status bits which happen to be set
during the access. The only remaining step is to provide an
access of the register which is associated with the status bit.
Typically. this presents no problem for the input capture and
output compare functions.
Figure 20 illustrates a typical multi-computer system configuration. Figure 20 represents a system of five different MCUs
in which there are one master and four slave (0. 1. 2. 3). In
this system four basic line (signals) are required for the
MOSI (master out slave in). MISO (master in slave out). SCK
serial clock. and SS (slave select) lines.
FEATURES
A problem can occur when using the timer overflow function
and reading the free running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software. the timer overflow flag could
unintentionally be cleared if: 1) the timer status register is read
or written when TOF is set. and 2) the least significant byte of
the free running counter is read but not for the purpose of servicing the flag. The counter alternate register at address $1A
and $1 B contains the same value as the free running counter
(at address $18 and $19); therefore. this alternate register can
be read at any time without affecting the timer overflow flag in
the timer status register.
•
•
•
•
•
•
•
•
•
During STOP and WAIT instructions. the programmable
timer functions as follows: during the wait mode. the timer
continues to operate normally and may generate an interrupt
to trigger the CPU out of the wait state; during the stop
mode. the timer holds at its current state. retaining all data.
and resumes operation from this point when an external
interrupt is received.
The four basic signals (MOSI. MISO. SCK. SS) discussed
above are described in the following paragraphs. Each signal function is described for both the master and slave mode.
Full Duplex. Three-wire Synchronous Transfers
Master or Slave Operation
Master Bit Frequency - 2.5MHz Maximum
Slave Bit Frequency - 5.0MHz Maximum
Four Programmable Master Bit Rates
Programmable Clock Polarity And Phase
End Of Transmission Interrupt Flag
Write Collision Flag Protection
Master-master Mode Fault Protection Capability
SIGNAL DESCRIPTION
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MISO
MOSI
SCK
SS - V e o
HIP7030A2
MASTER
0
PORT
I
I
:E:E
I MISO
MOSI SCK SS
I MISO
MOSI SCK
~
3
I
I
IMISO MOSI SCK
HIP7030A2 SLAVE 3
Ss
IMlSO
MOSI SCK SS
HIP7030A2 SLAVE 2
HIP7030A2 SLAVE 1
FIGURE 20. MASTER-SLAVE SYSTEM CONFIGURATION (SINGLE MASTER. FOUR SLAVES)
9-75
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oo
HIP7030A2
Master Out Slave In (MOSI)
The MOSI pin Is configured as a data output in a master
(mode) device and as a data Input in a slave (mode) devies.
In this manner data is transferred serially from a master to a
slave on this line; most significant bit first, least significant bit
last. The timing diagrams of Figure 21 summarize the SPI
timing and show the relationship between data and clock
(SCK). As shown in Figure 21, four possible timing relationships may be chosen by using control bits CPOl and CPHA.
The master device always allows data to be applied on the
MOSI line a half-cycle before the clock edge (SCK) in order
for the slave device to latch the data.
NOTE: Both the slave devlce(s) and a master device must be programmed to similar timing modes for proper data transfer.
When the master device transmits data to a second (slave)
device via the MOSIline, the slave device responds by sending data to the master device via the MISO line. This implies
full duplex transmission with both data out and data In synchronized with the same clock signal (one which is provided
by the master device). Thus, the byte transmitted is replaced
by the byte received and eliminates the need for separate
transmit-empty and receiver-full status bits. A single status
bit (SPIF) is used to signify that the 1/0 operation is complete. Configuration of the MOSI pin is a function of the
MSTR bit in the serial peripheral control register (SPCR,
location $OA). When a device is operating as a master, the
MOSI pin is an output because the program in firmware sets
the MSTR bit to a logic one.
Master In Slave Out (MISO)
The MISO pin is configured as an input in a master (mode)
device and as an output in a slave (mode) device. In this
manner data is transferred serially from a slave to a master
on this line; most significant bit first, least significant bit last.
The MISO pin of a slave device is placed in the high-impedance state if it is not selected by the master; i.e., its SS pin is
a logic one. The timing diagram of Figure 21 shows the relationship between data and clock (SCK). As shown In Figure
21, four possible timing relationships may be chosen by
Ss
using control bits CPOl and CPHA The master device
always allows data to be applied on the MOSI line a halfcycle befOre the clock edge (SCK) in order for the slave
device to latch the data.
NOTE: The slave device(s) and a master device must be programmed to similar timing modes for proper data transfer.
When the master device transmits data to a slave device via
the MOSI line, the slave device responds by sending data to
the master device via the MISO line. This implies full duplex
transmission with both data out and data in synchronized
with the same clock signal (one which is provided by the
master device). Thus, the byte transmitted is replaced by the
byte received and eliminates the need for separate transmitempty and receiver-full status bits. A single status bit (SPIF)
in the serial peripheral status register (SPSR, location $08)
is used to signify that the 110 operation is complete.
In the master device, the MSTR control bit in the serial peripheral control register (SPCR, location $OA) is set to a logic one
(by the program) to allow the master device to receive data on
its MISO pin. In the slave device, its MISO pin is enable by the
logic level of the SS pin; i.e., if SS 1 then the MISO pin is
placed in the high-impedanes state, whereas, if SS 0 the
MISO pin is an output for the slave devies.
=
Slave Select (SS)
The slave select (SS) pin is a fixed input, which receives an
active low signal that is generated by the master device to
enable slave device(s) to accept data. To ensure that data
will be accepted by a slave device, the SS signal line must
be a logic low prior to occurrence of SCK (system clock) and
must remain low until after the last (eighth) SCK cycle. Figure 21 illustrates the relationship between SCK and the data
for two different level combinations of CPHA, when SS is
pulled low. These are: 1) with CPHA 1, the first bit of data
is applied to the MISO line for transfer (SS must go high
between successive Characters), and 2) when CPHA = 0 the
slave device is prevented from writing to its data register (SS
can remain low between characters). Refer to the WCOl
=
l
SCK
(CPOl • 0, CPHA. O)
SCK
(CPOl • 0, CPHA. 1)
SCK
(CPOl .,, CPHA. O)
SCK
(CPOl .1, CPHA.,)
MISOI
MOSI
~
MSB
6
5
=
4
3
2
I I I I I I
lSB
I
INTERNAL STROBE FOR DATA CAPTURE (All MODES)
FIGURE 21. DATA CLOCK TIMING DIAGRAM
9-76
HIP7030A2
status flag in the serial peripheral status register (location
$OBl..Eescription for further information on the effects that
the SS input and CPHA control bit have on the VO data register. A high level SS signal forces the MISO (master in slave
out) line to the high-impedance state. Also, SCK and the
MOSI (master out slave in) line are ignored by a slave device
when its SS signal is high.
When a device is a master, it constantly monitors its SS signal input for a logic low. The master device will become a
slave device any time its SS signal input is detected low. This
ensures that there is only one master controlling the SS line
for a particular system. When the SS line is detected low, it
clears the MSTR control bit (serial peripheral control register, location $OA). Also, control bit SPE in the serial peripheral control register is cleared which causes the serial
peripheral interface (SPI) to be disabled (port 0 SPI pins
become inputs). The MODF flag bit in the serial peripheral
status register (location $OB) is also set to indicate to the
master device that another device is attempting to become a
master. Two devices attempting to be outputs are normally
the result of a software error; however, a system could be
configured which would contain a default master which
would automatically "take-over" and restart the system.
Serial Clock (SCK)
The serial clock is used to synchronize the movement of data
both in and out of the device through its MOSI and MISO pins.
The master and slave devices are capable of exchanging a
data byte of information during a sequence of eight clock
pulses. Since the SCK is generated by the master device, the
SCK line becomes an input on all slave devices and synchronizes slave data transfer. The type of clock and it relationship
to data are controlled by the CPOL and CPHA bits in the
serial peripheral control register (location $OA) discussed
below. Refer to Figure 21 for timing.
The master device generates the SCK through a circuit
driven by the internal processor clock. Two bits (SPRO and
SPR 1) in the serial peripheral control register (location $OA)
of the master device select the clock rate. The master device
uses the SCK to latch incoming slave device data on the
MISO line and shifts out data to the slave device on the
MOSI line. Both master and slave devices must be operated
in the same timing mode as controlled by the CPOL and
CPHA bit in the serial peripheral control register. In the slave
device, SPRO, SPR1 have no effect on the operation of the
serial peripheral interface. Timing is shown in Figure 21.
Functional Description
A block diagram of the serial peripheral interface (SPI) is
shown in Figure 22. In a master configuration, the master
start logic receives an input from the CPU (in the form of a
write to the SPI rate generator) and originates the system
clock (SCK) based on the internal processor clock. This
clock is also used internally to control the .state controller as
well as the 8-bit shift register. As a master device, data is
parallel loaded into the 8-bit shift register (from the internal
bus) during a write cycle, data is applied serially from a slave
device via the MISO pin to the 8-bit shift register. After the 8bit shift register is loaded, its data is parallel transferred to
SEE NOTE
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SPCR
$OA
CONTROL
BITS
3
SPSR
SOB
7
FLAGS
NOTES: The SS, SCK, MOSI, and MISO are external pins which provide the following functions:
1. MOSI - Provides serial output to slave unit(s) when device Is configured as a master. Receives serial Input from master unit when device
is configured as a slave unit.
2. MISO - Provides serial inpu1 from slave unit(s) when device is configured as a master. Receives serial output to master unit when device
is configured as a slave unit.
3. SCK - Provides system clock when device is configured as a master. Receives system clock when device is configured as a slave unit.
4. SS - Provides a logic low to select device for a transfer with the master.
FIGURE 22. SERIAL PERIPHERAL INTERFACE (SPI) BLOCK DIAGRAM
9-77
HIP7030A2
the read buffer and then is made available to the internal
data bus during a CPU read cycle.
B6, SPE
FIGURE 23. SERIAL PERIPHERAL INTERFACE (SPI) MASTERSLAVE INTERCONNECTION
B4,MSTR The master bit determines whether the device
is a master or a slave. If the MSTR bit is a logic
zero it indicates a slave device and a logic one
denotes a master device. If the master mode is
selected, the function of the SCK pin changes
from an input to an output and the function of
the MISO and MOSI pins are reversed. This
allows the user to wire device pins MISO to
MISO, and MOSI to MOSI, and SCK to SCK
without incident. The MSTR bit is cleared by
RESET; therefore, the device is always placed
in the slave mode during RESET.
In a slave configuration, the slave start logic receives a logic
low (from a master device) at the SS pin and a system clock
input (from the same master device) at the SCK pin. Thus, the
slave is synchronized with the master. Data from the master is
received serially at the slave MOSI pin and loads the 8-bit shift
register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer and then is made available to
the internal data bus during a CPU read cycle. During a write
cycle, data is parallel loaded into the 8-bit shift register from
the internal data bus and then shifted out serially to the MISO
pin for application to the master device.
Figure 23 illustrates the MOSI, MISO, and SCK master-slave
interconnections. Note that in Fi9.!:!.!!l23 the master SS pin is
tied to a logic high and the slave SS pin is a logic low. Figure
20 provides a larger system...£!:!nnection for these same pins.
Note that in Figure 20, all SS pins are connected to a port
pin of a master/slave device. In this case any of the devices
can be a slave.
Registers
There are three register in the serial parallel interface which
provide control, status, and data storage functions. These
registers which include the serial peripheral control register
(SPCR, location $OA) , serial peripheral status register
(SPSR, location $OB), and serial peripheral data VO register
(SPDR, location $OC) are described below.
Serial Peripherai Control Register (SPCR)
The serial peripheral control register bits are defined as
follows:
SPCR (LOCATION $OA)
B7, SPIE
When the serial peripheral interrupt enable is
high, it allows the occurrence of a processor
interrupt, and forces the proper vector to be
loaded into the program counter if the serial
peripheral status register flag bit (SPIF and/or
MODE) is set to a logic one. It does not inhibit
the setting of a status bit. The SPIE bit is
cleared by RESET.
When the serial peripheral output enable control bit is set, aU output drive is applied to the
external pins and the system is enabled. When
the SPE bit is set, it enables the SPI system by
connecting it to the external pins thus allowing
it to interface with the external SPI bus. The
pins that are defined as output depend on
which mode (master or slave) the device is in.
When SPE is low all pins appear as inputs to
the external system. Because the SPE bit is
cleared by RESET, the SPI system is not connected to the external pins upon RESET.
B3, CPOL The clock polarity bit controls the normal or
steady state value of the clock when data is not
being transferred. The CPOL bit affects both the
master and slave modes. It must be used in c0njunction with the clock phase control bit (CPHA)
to produce the wanted clock-data relationship
between a master and a slave device. When the
CPOL bit is a logic zero, it produces a steady
state low value at the SCK pin of the master
device. If the CPOL bit is a logic one, a high value
is produced at the SCK pin of the master device
when data is not being transferred. The CPOL bit
is not affected by RESET. Refer to Figure 21.
B2, CPHA The clock phase bit controls the relationship
between the data on the MISO and MOSI pins
and the clock produced or received at the SCK
pin. This control has effect in both the master and
slave modes. It must be used in conjunction with
the clock polarity control bit (CPOL) to produce
the wanted clock-data relation. The CPHA bit in
general selects the clock edge which captures
data and allows it to change states. It has its
greatest impact on the first bit transmitted (MSB)
in that it does or does not allow a clock transition
before the first data capture edge. The CPHA bit
is not affected by RESET. Refer to Figure 21.
Bl, SPR1
BO, SPRO
9-78
These two serial peripheral rate bits select one
of four baud rates to used as SCK if the device
is a master; however they have no effect in the
slave mode. The slave device is capable of
shifting data in and out at a maximum rate
which is equal to the CPU clock. A rate table is
given below for the generation of the SCK from
the master. The SPR1 and SPRO bits are not
affected by RESET.
HIP7030A2
SPR1
SPRO
INTERNAL PROCESSOR
CLOCK DIVIDE BY
0
0
2
0
1
4
1
0
16
1
1
32
Serial Peripheral Status Register (SPSR)
The stalus flags which generate a serial peripheral interface
(SPI) interrupt may be blocked by the SPIE control bit in the
serial peripheral control register. The WCOl bit does not
cause an interrupt. The serial peripheral status register bits
are defined as follows:
I S;IF IW;OL I ~ IM;DF I ~ I ~ I ~ I ~ I
SPSR (LOCATION $OB)
87, SPIF
The serial peripheral data transfer flag b~ notifies
the user that a data transfer between the device
and an external device has been completed.
With the completion of the data transfer, SPIF is
set, and if SPIE is set, a serial peripheral interrupt (SPI) is generated. During the clock cycle
that SPIF is being set, a copy of the received
data byte in the shift register is moved to a buffer.
When the data register is read, ~ is the buffer that
is read. During an overrun condition, when the
master device has sent several bytes of data and
the slave device has not responded to the first
SPIF, only the first byte sent is contained in the
receiver buffer and all other bytes are lost.
The transfer of data is initiated by the master
device writing its serial peripheral data register.
Clearing the SPIF bit is accomplished by a
software sequence of accessing the serial
peripheral status register while SPIF is set and
followed by a write to or a read of the serial
peripheral data register. While SPIF is set, all
writes to the serial peripheral data register are
inhibited until the serial peripheral status register is read. This occurs in the master device. In
the slave device, SPIF can be cleared (using a
similar sequence) during a second transmission; however, it must be cleared before the
second SPIF in order to prevent an overrun
condition. The SPIF bit is cleared by RESET.
8
6
WCOl
Clearing Ihe WCOl bit is accomplished by a
software sequence of accessing the serial
peripheral status register while WeOl is set,
followed by 1) a read of the serial peripheral
data register prior to the SPIF bit being set, or 2)
a read or write of the serial peripheral data register after the SPIF bit is set. A write to the serial
peripheral data register (SPDR) prior to the SPIF
bit being set, will resuR in generation of another
WCOl status flag. 80th the SPIF and WCOl
bits will be cleared in the same sequence. If a
second transfer has started while trying to clear
(the previously set) SPIF and WCOl bits with a
clearing sequence containing a write to the
serial peripheral data register, only the SPIF bit
will be cleared.
A collision of a write to the serial peripheral data
register while an external data transfer is taking
place can occur in both the master mode and
the slave mode, although with proper programming the master device should have sufficient
information to preclude this collision.
Collision in Ihe master device is defined as a
write of the serial peripheral data register while
the internal rate clock (SCK) is in the process
of transfer. The Signal on the SS pin is always
high on the master device.
A collision in a slave device is defined in two
separate modes. One problem arises in a
slave device when the CPHA control bit is a
logic zero. When CPHA is a logic zero, data is
latched with the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs
when it attempts to write the serial peripheral
data register after its SS pin has been pulled
low. The SS pin of the slave device freezes the
data in its serial peripheral data register and
does not allow it to be altered if the CPHA bit is
a logic zero. The master device must raise the
Ss pin of the slave device high between each
byte it transfers to the slave device.
The second collision mode is defined for the
state of the CPHA control bit being a logic one.
With the CPHA bit set, the slave device will be
receiving a clock (SCI<) edge prior to the latch of
the first data transfer. This first clock edge will
freeze the data in the slave device I/O register
and allow the MS8 onto the external MISO pin
of the slave device. The Ss pin low state
enables the slave device but the drive onto the
MISO pin does not take place until the first
data transfer clock edge. The WeOl bit will
only be set if the 110 register is accessed while
a transfer is taking place. 8y definition of the
second collision mode, a master device might
hold a slave device SS pin low during a transfer of several bytes of data without a problem.
The function of the write collision status bit is to
notify the user that an attempt was made to
write the serial peripheral data register while a
data transfer was taking place with an external
device. The transfer continues uninterrupted;
therefore, a write will be unsuccessful. A "read
collision" will never occur since the received
data byte is placed in a buffer in which access
is always synchronous with the MCU operation. If a "write collision" occurs, WCOl is set
but no SPI interrupt is generated. The WCOl
bit is a status flag only.
9-79
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HIP7030A2
A special case of WCOl occurs in the slave
device. This happens when the master device
starts a transfer sequenc.!Jan edge on SCK for
CPHA 1; or an active SS transition for CPHA
0) at the same time the slave device CPU is
writing to its serial peripheral interface data register. In this case it is assumed that the data
byte written (in the slave device serial peripheral
interface) is lost and the contents of the slave
device read buffer becomes the byte that is
transferred. Because the master device receives
back the last byte transmitted, the master device
can detect that a fatal WCOl occurred.
=
Serial Peripheral Data 110 Register (SPDR)
6
=
Since the slave device is operating asynchronously with the master device, the WCOl bit
may be used as an indicator of a collision
occurrence. This helps alleviate the user from
a strict real-time programming effort. The
WCOl bit is cleared by RESET.
B4, MODF The function of the mode fault flag is defined
for the master mode (device). If the device is a
slave device the MODF bit will be prevented
from toggling from a logic zero to a logic one;
however, this does not prevent the device from
being in the slave mode with the MODF bit set.
The MODF bit is normally a logic zero and Is
set only when the master device has its SS pin
pulled low. Toggling the MODF bit to a logic
one affects the internal serial peripheral interface (SPI) system in the following ways:
1. MODF is set and SPI interrupt is generated
if SPIE = 1.
2. The SPE bit is forced to a logic zero. This
blocks all output drive from the device, disables the SPI system.
3. The MSTR bit is forced to a logic zero, thus
forcing the device into the slave mode.
Clearing the MODF is accomplished by a software sequence of accessing the serial peripheral status register while MODF is set followed
by a write to the serial peripheral control register. Control bit SPE and MSTR may be
restored to their original set state during this
cleared sequence or after the MODF bit has
been cleared. Hardware does not allow the
user to set the SPE and MSTR bit while MODF
is a logic one unless it is during the proper
clearing sequence. The MODF flag bit indio
cates that there might have been a multi·mas·
,ter conflict for system control and allows a
proper exit from system operation to a RESET
or default system state. The MODF bit is
cleared by RESET.
5
I
4
I
3
I
2
o
Serial Peripheral Data VO Register
SPDR (LOCATION $OC)
The serial peripheral data 110 register is used to transmit and
receive data on the serial bus. Only a write to this register
will initiate transmission/reception of another byte and this
will only occur in the master device. A slave device writing to
its data I/O register will not initiate a transmission. At the
completion of transmitting a byte of data, the SPIF status bit
is set in both the master and slave devices. A write or read of
the serial peripheral data I/O register, after accessing the
serial peripheral status register with SPIF set, will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy
of the received data byte in the shift register is being moved
to a buffer. When the user reads the serial peripheral data 1/
register, the buffer is actually being read. During an over·
run condition, when the master device has sent several
bytes of data and the slave device has not internally
responded to clear the first SPIF, only the first byte is contained in the receive buffer of the slave device; all others are
lost. The user may read the buffer at any time. The first SPIF
must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated or an overrun
condition will exist.
o
A write to the serial peripheral data I/O register is not buffered
and places data directly into the shift register for transmission.
The ability to access the serial peripheral data I/O register is
limited when a transmission is taking place. It is important to
read the discussion defining the WCOl and SPIF status bit to
understand the limits on using the serial peripheral data I/O
register.
Serial Peripherallnteriace (SPI)
System Considerations
There are two types of SPI systems; single master system
and multi-master systems. Figure 20 illustrates a single
master system and a discussion of both is provided below.
Figure 20 illustrates how a typical single master system may
be configured, using a CDP68HC05 family device as the
master and four CDP68HC05 family devices as slaves. As
shown, the MOSI, MISO, and SCK pins are all wired to
equivalent pins on each of the five devices. The master
device generates the SCK clock, the slave device all receive
it. Since the CDP68HC05 master device is the bus master, it
internally controls the function of its MOSI and MISO lines,
thus writing data to the slave devices on the MOSI and read·
ing data from the slave devices on the MISO lines. The mas·
ter device selects the individual slave devices by using four
pins of a parallel port to control the four SS pins of the slave
devices. A slave device is selected when the master device
pulls its SS pin low. The SS pins are pulled high during
9-80
HIP7030A2
I I
SOF
HEADER
DATA 1
DATA 2
CRC
FIGURE 24. TYPICAL J1850 VPW MESSAGE FRAME
RESET since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices. Note
that the slave devices do not have to be enabled in a mutually exclusive fashion except to prevent bus contention on
the MISO line. For example, three slave devices, enabled for
a transfer, are permissible if only one has the capability of
being read by the master. An example of this is a write to
several display drivers to clear a display with a single 1/0
operation. To ensure that proper data transmission is occurring between the master device and a slave device, the master device may have the slave device respond with a
previously received data byte (this data byte could be
inverted or at least be a byte that is different from the last
one sent by the master device). The master device will
always receive the previous byte back from the slave device
if all MISO and MOSI lines are connected and the slave has
not written its data 1/0 register. Other transmission security
methods might be defined using ports for handshake lines or
data bytes with command fields.
A multi-master system may also be configured by the user. An
exchange of master control could be implemented using a
handshake method through the VO ports or by an exchange
of code messages through the serial peripheral interface system. The major device control that plays a part in this system
is the MSTR bit in the serial peripheral control register and the
MODF bit in the serial peripheral status register.
J1850 VPW Messaging
This section provides an introduction to J1850 multiplexed
communications. It is assumed that the user is or will
become familiar with the appropriate documents published
by the Society of Automotive Engineering (SAE). The following discussion is not comprehensive.
Overview
The SAE Recommended Practice J1850 (Note 1) (J1850)
establishes the requirements for communications on a Class
B multiplexed wiring network for automotive applications.
The J 1850 document details the requirements in a three
layer description which separately specifies the characteristics of the physical layer, the data link layer, and the application layer. There are several options within each layer which
allows vehicle manufacturers to customize the network while
still maintaining a level of universality.
NOTE:
1. SAE Recommended Practice J1850, Class B Data CommunI-
cation Network Interface, September I, 1993, Society of Automotive Engineers Inc.
The hardware of the Harris HIP7030A2 provides features
which facilitate implementation of the 10.4Kbps Variable
Pulse Width Modulated (VPW) physical layer option of
J1850. In combination with a bus transceiver, such as the
Harris J1850 Bus Transceiver HIP7020, and appropriate
software algorithms the HIP7030A2 circuitry enables the
designer to completely implement a 10.4Kbps VPW Class B
Communications Network Interface per J1850. Features of
such an implementation include:
• Single Wire 10.4Kbps Communications
• Message Buffering and Message Filtering
• Bit-by-Bit Bus Arbitration
• Industry Standard Protocol
• Message Acknowledgment ("In-Frame Response") Capabilities
• Exceptionally Tolerant of Clock Skew, System Noise, and
Ground Offsets
• Meets CARB and EPA DiagnostiC Requirements
• Supports up to 32 Nodes
• Low Error Rates
• Excellent EMC Levels (when interfaced via Harris J1850
Bus Transceiver HIP7020)
In addition to the standard J1850 features, the HIP7030A2
hardware provides a high speed mode, (intended for receive
only use) which can significantly enhance vehicle maintenance capabilities. The high speed mode provides a
41.6Kbps communications path to any node built with the
HIP7030A2.
Anatomy of a J1850 VPW Message
All messages in a J1850 VPW system are sent along a single wire, shared bus. At any given moment the bus can be in
either of two states: active (high) or passive (low). Multiple
nodes are connected to the bus as a "wired-OR" network in
which the bus is high if anyone (or more) node is generating
an active output. The bus is only low when no nodes are generating active outputs. It follows that, when no communications are taking place the bus will rest in the passive state. A
message begins when the bus is first driven to the high state.
Each succeeding state transition (i.e. - a change from active to
passive or passive to active) transfers one bit of information
(symbo~ until the message is complete and the bus once
again rests at the passive state. The interpretation of each
symbol in the message is dependent on its duration (and
state), hence the descriptor Variable Pulse Width (VPW).
Each message has a beginning and an end, the span of
which encompasses the entire message or frame (refer to
Figure 24). A frame consists of an active start of frame
(SOF) symbol and a passive end of frame (EOF) symbol
sandwiched around a series of byte sized (B-bit) groups of
symbols. The first byte of the frame contents is always a
header byte, followed by possibly additional header bytes,
9-81
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followed by one or more data bytes, followed by an integrity
check byte (CRC byte), followed by a passive end of data
(EOD) symbol, followed by possibly one or more In-frameresponse (lFR) bytes. To keep waiting times low, messages
are limited to 12 bytes total (including header, data, check,
and IFR bytes). All message bytes are transmitted most significant bit (MSB) first.
VPW Symbol Definitions
transition to the passive state, a 0 data bit will return to the
active level quicker than a 1. These facts give rise to the
dominance of O's over l's on the J1850 bus as depicted in
Figure 25. See Bus Arbitration for additional details.
SYNCHRONIZED
t
o DATA
Within the J1850 scheme, symbols are defined in terms of
both duration and state (passive or active). The duration is
measured as the time between successive transitions. There
is one transition per symbol and one symbol per transition.
The end of one symbol marks the beginning of the next.
Since the bus is passive when a message begins and must
return to that same state when the message completes, all
frames have an even number of transitions and hence an
even number of symbols.
There are unique definitions for data bit symbols (all the
symbols which occur within the header, data, and check
bytes) and protocol symbols (including SOF, EOD, and
EOF). The duration of each symbol is expressed in terms of
VPW Timing Pulses (TV values). Table 5 summarizes the TV
definitions. Each TV is specified in terms of a nominal (or
ideal) duration and a minimum and maximum duration. The
span between the minimum and maximum limits accommodates system noise sources such as node to node clock
skew, ground offsets, clock jitter, and electromechanical
noise. There are no dead zones between the maximum of
one TV and the minimum of the next.
The terms short and long are often used to refer to pulses of
duration TVl and TV2 respectively.
TABLE 5. J1850 TV DEFINITIONS
1
J1850
MINIMUM
NOMINAL
MAXIMUM
Illegal
0
NA
:5:34
TV1
>34
64
S96
TV2
>96
128
:5:163
TV3
>163
200
:5:239
TV4
>239
280
TV5
>239
300
TV6
>280
300
NA
BIT
BUS
~R-
r--.
~S-I
LONGER ACTIVE
~~~~~~~lSTHEBUS
0
FIGURE 25A. DOMINANCE OF ACTIVE 0 DATA Brr
SYNCHRONIZED
t
o DATA BIT
1
DATA
BIT
J1850
BUS
~a,O
r--
L!J
L!...-Jr~a,
r--::::
~a,1
L!J
SHORTER PASSIVE
~ ~~~~ls THE BUS
FIGURE 25B. DOMINANCE OF PASSIVE 0 DATA Brr
FIGURE 25.
Table 6 summarizes the complete set of symbol definitions
based on duration and state.
TABLE 6. J1850 SYMBOL DEFINITIONS
SYMBOL
DURATION
(ALL TIMES IN MICROSECONDS)
TVID
DATA
BIT~FL
o Data
DEFINITION
Passive TV1 or Active TV2
1 Data
Active TV1 or Passive TV2
SOF (Start of Frame)
ActiveTV3
EOD (End of Data)
Passive TV3
EOF (End of Frame)
PassiveTV4
IFS (Inter·Frame Separation)
Passive TV6
IDLE (Idle Bus)
Passive>TV6 nom
NA
NB (Normalization Bit)
Active TVl or Active TV2
NA
BRK (Break)
ActiveTV5
In Frame Response (IFR)
VPW is a non-return-to-zero (NRZ) protocol in which each
transition represents a complete bit of information. Accordingly, a 0 data bit will sometimes be transmitted as a passive
pulse and sometimes as an active pulse. Similarly, a 1 data
bit will sometimes be transmitted as a passive pulse and
sometimes as an active pulse. In order to accommodate
arbitration (see Bus Arbitration) a long active pulse represents a 0 data bit and a short active pulse represents a 1
data bit. Complementing this fact, a short passive pulse represents a 0 and a long passive pulse represents a 1. Starting
from a transition to the active state, a 0 data bit will maintain
the active level· longer than a 1. Similarly, starting from a
The distinction between two of the passive symbols, EOD
and EOF, is subtle but important (reier to Figure 26). The
EOD (TV3) interval signifies that the originator of the message is done broadcasting and any nodes which have been
requested to respond (I.e. - to acknowledge receipt of the
message) can now do so. The EOD interval begins when the
transmitting node has completed sending the eighth bit of
the check byte. The transmitter simply releases the bus and
allows it to revert to a passive state. In the course of normal
messaging, no node can seize the bus until an EOD time
has been detected. Once an EOD has elapsed, any nodes
which are scheduled to produce an IFR will arbitrate for con-
9-82
HIP7030A2
~
SlJlJ1f
HEADER • • • • DATA N
'SOF ,
'EOD ','IN FRAME RESPONSE
CRC
I 'I
EOD
EOF
NB
fiGURE 26. J1850 MESSAGE WITH IN-fRAME-RESPONSE
TRANSMITTER
A
~t---""
TRANSMITTER
B
~,.....---'
~
J1850
BUS
CRC
fiGURE 27. TWO NODES ARBITRATING fOR CONTROL Of J1850 BUS
trol of the bus (see Bus Arbitration) and respond appropriately. If no responses are forthcoming the bus remains in the
passive state until an EOF (TV4) interval has elapsed. After
the EOF has been generated. the frame is considered closed
and the next communications on the bus will represent a
totally new message.
IFRs can consist of multiple bytes from a single respondent,
one byte from a single respondent, or one byte from multiple
respondents. In all cases the first response byte must be
preceded by a normalization bit (NB) which serves as a start of
response symbol and places the bus in an active state so that
following the IFR byte(s) the bus will be left in the passive state.
The NB symbol is by definition active, but can be either TV1
or TV2 in duration. The long variety (TV2) signifies the IFR
contains a CRC byte. The short variety (TV1) precedes an
IFR without CRC.
Message Types
Messages are classified into one of four Types according to
whether the message has an IFR and what kind of IFR it is.
The definitions are:
• Type 0 - No IFR
• Type 1 - One byte IFR from a single~respondent (no CRC
byte)
• Type 2 - One byte IFRs from multiple respondents (no
CRC byte)
• Type 3 - Multiple byte IFR from a single respondent (CRC
appended)
Bus Arbitration
The nature of multiplexed communications leads to contention
issues when two or more nodes attempt to transmit on the bus
simultaneously. Within J1850 VPW systems. messages are
assigned varying levels of priority which allows implementation of an arbitration scheme to resolve potential contentions.
The specified arbitration is performed on a symbol by symbol
basis throughout the duration of every message.
Arbitration begins with the rising edge of the SOF pulse. No
node should attempt to issue an SOF until an Idle bus has
been detected (i.e. - an Inter-Frame Separation (IFS) symbol
with a period of TV6 has been received). If multiple nodes are
ready to access the bus and are all waiting for an IFS to
elapse, invariable skews in timing components will cause one
arbitrary node to detect the Idle condition before all others and
start transmission first. For this reason, all nodes waiting for
an IFS will consider an IFS to have occurred if either:
- An IFS nominal period has elapsed
or
- An EOF minimum period has elapsed and a riSing edge
has been detected
Arbitrating devices will all be synchronized during the SOF.
Beginning with the first data bit and continuing to the EOF.
every transmitting device is responsible for verifying that the
symbol it sent was the symbol which appeared on the bus.
Each transition, every transmitting node must decode the
symbol, verify the received symbol matches the one sent, and
begin timing of the next symbol. Since timing of the next symbol begins with the last transition detected on the bus, all
transmitters are re-synchronized each symbol. When the
received symbol doesn't match the symbol sent, a conflict (bit
collision) occurs. Any device detecting a collision will assume
it has lost arbitration and immediately relinquish the bus. Typically, after lOSing arbitration, a device will attempt re-transmission of the message when the bus once again becomes Idle.
The definition of 1 and 0 data bits (see Table 6 and discussion under VPW Symbol Definitions) leads to O's having
priority over 1's in this arbitration scheme. Header bytes are
generally aSSigned such that arbitration is completed before
the first data byte is transmitted. Because of the dominance
of O-bits and the MSB first bit order, a header with the hexadecimal value $00 will have highest priority, then $01, $02,
$03, etc. An example of two nodes arbitrating for control of
the bus is shown in Figure 27.
Arbitration also takes place during the IFR portion of a message, if more than one node is attempting to generate a
response. Arbitration begins with the NB symbol, which follows the EOD and precedes the first IFR byte.
9-83
J!!
><~
w=>
0
CL,!!;
-0
~.
...1
=>:E
:E:E
o
o
HIP7030A2
NEW is set when either of these events is
detected. In the case of a transition following
an EOF, the TX bit is also set.
The time required to detect. an echo failure is
dependent on many factors. The minimum time
to detect a failure is 105j.lS (26j.Ls in 4X mode) and
the maximum time to detect a failure is 512J.LS.
When NEW goes from a 0 to aI, a SENDEC
interrupt will be generated if the I bit is cleared
in the CC register. The NEW interrupt can be
cleared under software control by reading the
SEDSR followed by writing the SEDCR. This
only removes the source of the interrupt and
does not clear the NEW bit.
The NEW flag cannot be cleared by software.
It is automatically cleared 128 (nominal) microseconds into the next (or current - if NEW was
set by a transition following EOF) symbol. This
is normally during the SOF of a new message.
If the symbol is less than 12811S in duration (an
illegal SOF symbol), the NEW flag is cleared
on the active to passive transition.
Polling NEW provides a convenient means for
software to determine that transmission of a
new message can be commenced.
NEW is cleared by all resets.
64, NOIZ
The noise (NOIZ) flag indicates that a symbol
shorter than a legal TVI has been received.
NOIZ is cleared by a sequence of first reading
the SEDSR followed by reading or writing the
SEDCR.
63, OVR
The overrun (OVR) flag is set if TALK is set in
the SEDSR and a minimum short symbol time
(34I1S) has elapsed since the last transition
and no write to the SEDOR has taken place.
An overrun condition is a serious error and the
user should treat it as such. When OVR is set it
automatically forces the VPWOUT pin to a low
level. OVR is cleared by a sequence of first
reading the SEDSR followed by reading or
writing the SEDCR.
When NECHO goes from a low to a high level,
a SEN DEC interrupt will be generated if the I
bit is cleared in the CC register. NECHO must
go low then high again to generate another
interrupt.
NECHO is cleared by a sequence of first reading the SEDSR followed by reading or writing
the SENDEC Data Register (SEDOR).
NECHO is cleared by all resets.
SENDEe Data Register
The SENDEC Data Register (SEDOR, location $11) is an 8bit read/wrHe register which contains one write-only bH, three
read/write bits, and four read-only bits. The write only bit triggers SOF symbols required to inHiate new transmissions, the
three read/write bits are used to specify transmitted symbol
durations, and the four read only bits uniquely identify the
received J1850 symbol. Reading the SEDOR at anytime provides the received symbol which resulted from the last transition of VPWiii. When writing data to the SEDOR, the value
represents the duration of the symbol currently being transmitted. The bit assignments are illustrated below, followed by a
detailed description.
NOIZ is cleared by RESET.
Setting of OVR is inhibited while NEW is true in
the SEDSR.
67, FSOF Writing a 1 to the Force Start of Frame (FSOF)
bit while simultaneously writing a non-zero
value to S2-0, causes the VPWOUT to immediately go active (high level). The low to high
transition will eventually be reflected on the
VJ5Wiji:j line causing a TX interrupt. Upon
receipt of the TX interrupt an SOF symbol (S2o = 3) must be written to the SEDOR to time
the high SOF.
Setting the FSOF bit can only be done when the
NEW flag Is set in the SEN DEC Status Register
(NEW is set when the J1850 bus is idle or during the first portion of an SOF symbol).
OVR is cleared by RESET.
62, TALK
The transmit (TALK) flag is set if the
HIP7030A2 is actively transinitting symbols via
the SEN DEC. TALK is set by writing a nonzero to the SEDOR (see SENDEe Data Registerfor details).
The TALK bit is cleared by writing a $00 to the
SEDOR, when NECHO is set, or when OVR is
set.
FSOF is a write only bit. Reading FSOF always
returns a O.
66,S2
65,SI
64, SO
TALK is cleared by RESET.
61,
NECHO
When writing to the SEDOR, the three bhs (82-0)
determine the transmitted symbol as shown in
Table 8. During a write to the SEDOR the 82-0bits are ignored except in three specific situations:
The NEW flag is high in the SEDSR)
The No Echo Received (NECHO) flag is set if,
during the process of transmitting a symbol,
the expected echo of the symbol is not
received. This event will cause the VPWOUT
pin to be forced to a 0 level. Setting of NECHO
automatically clears the TALK bit.
or
A transition has been received on the VJ5Wiji:j
pin, from the bus, within the past 34I1S
or
S2-0-bits
9-86
=0
HIP7030A2
In the first two cases, each write to the SEDOR
will produce one properly timed symbol on the
VPWOUT pin. The completion of the symbol is
reported to the controller, not at the end of the
transmitted symbol, but at the end of the symbol echoed back via the '\ii5Wi'N input. Writing
the FSOF bit, in conjunction with S2-0 = 3, produces the initial transition for the SOF symbol.
All timing for a message begins with the receipt
of that transition.
transmit time for a short symbol has elapsed (34(.1s). Failure
to write to the SEDOR in time will result in the OVR bit being
set and transmission aborted. This is a safety precaution to
prevent ·streaming" messages.
The control routines should verify that the symbol sent
matches the symbol received. A mismatch indicates the
device has lost control of the bus. It is up to the user code to
handle the colliSion, in terms of disabling the SEN DEC, requeueing of the message, filtering the incoming message, etc.
Writing a $00, at anytime, immediately disables transmissions (forcing the VPWOUT pin
low) and clears the TALK bit in the SEDSR.
This is the preferred method to end transmissions.
TABLE 9. R2-RO AND LEV SYMBOL DECODING
RESET doesn't affect S2-S0
TABLE 8. S2-S1 SYMBOL ENCODING
R2
Rl
RO
LEV
0
0
0
0
Receive Symbol
0
0
0
1
ActlveNoise
0
0
1
0
TVl Passive
0
0
1
1
TVl Active
Passive Noise
S2
S1
SO
TRANS9MIT SYMBOL
0
1
0
0
TV2 Passive
0
0
0
Disable Transmit
0
1
0
1
TV2 Active
TVl
0
1
1
0
EOD
1
1
1
SOF
0
0
1
0
1
0
TV2
0
0
1
1
TV3
1
0
0
0
EOF
1
0
0
1
BREAK
1
0
0
TV1
1
0
1
TVl
1
1
0
TVl
1
1
1
TVl
B3,LEV
B2,R2
B1, R1
BO,RO
These four bits un~dentify all symbols
received via the VPWIN pin. The symbol
decoding map is shown in Table 9. R2-0 represent the duration of the symbol and LEV represents the level of the symbol (active or
passive)
These bits are only updated upon detection of
a bus transition and therefore reflect the last
symbol received. An exception to this is for an
Idle bus. When an Idle has been detected the
values in R2-RO and LEV are immediately
updated - no bus transition is necessary.
R2-RO = 101 with LEV = 0 indicates that the
bus is currently Idle.
Note that R2-0 combinations of 110 and 111
will not be produced by the SENDEC. A value
of 101 represents all durations equal to and
beyond an IFs/IDLE (for the passive case) and
a BREAK (for the active case).
RESET does not affect LEV or R2-RO.
When a transition is detected on VPWIN, the received symbol is decoded and made available for reading via the
SEDOR. The TX bit is set in the SEDSR and, if TXIE is high
in the SEDCR, an interrupt will be generated. Once the transition is detected the next symbol begins timing out. A new
symbol must be written to the SEDOR, before the minimum
1
0
1
0
IFs/IDLE
1
0
1
1
BREAK
1
1
0
0
-
1
1
0
1
1
1
1
0
1
1
1
1
-
In the receive mode (i.e. - no writes to the SEDOR) the controller typically responds to the TX interrupts and reads the
incoming symbols as they become available, performing
necessary real-time operations such as filtering messages,
computing and verifying CRCs, and issuing IFRs.
computer Operating Properly
(COP) System
INTRODUCTION
The Computer Operating Properly (COP) system is comprised of two basic circuit components. One is a free running
watchdog timer which, left unattended, generates a periodic
MCU reset. The second is a Slow Clock Detect circuit which
constantly monitors the OSCIN line for activity. A lack of
activity on OSCIN will generate a reset.
Both circuits are capable of generating a COP interrupt
which forces an MCU reset and restarts operation at the vector specified by the contents of location $lFFA,$lFFB.
Because the COP interrupt behaves as a reset, the stack
pointer is cleared and exiting the COP interrupt software
handler must be done via a jump instruction as opposed to
an RTI or RTS.
9-87
HIP7030A2
The Watchdog Status Register (WSR, location $lE) contains a flag (Watchdog Flag, bit 0) which is set whenever a
Watchdog Timer overflow interrupt occurs. The flag is
cleared by 'RESE'f. POR, and Slow Clock Detect and can
therefore be used to distinguish the type of COP reset
(Watchdog timeout vs. Slow Clock Detect) which has
occurred.
Each time that the Watchdog Timer is successfully cleared
the Watchdog Flag in the WSR is also cleared. The Watchdog flag is also cleared by POR, RESET, and Slow Clock
Detect. It is set by a Watchdog Timer overflow and can be
used to distinguish a Slow Clock Detect reset from the
Watchdog reset, both of which share the COP reset vector
($1 FFA,$l FFB).
Operation of each of the two circuits is detailed in the following discussion.
SLOW CLOCK DETECT CIRCUIT
WSR (LOCATION $1 E)
The Slow Clock Detect Circuit consists of a reset-able timer
element. The timer is constructed with integrated resistive
and capacitive components. Each positive transition on the
OSCIN line reinitializes the timer. In the absence of frequent
enough transitions on the input, the timer will eventually
reach a preset limit at which point the MCU will be reset via a
COP interrupt.
Watchdog timeout periods for various OSCIN frequencies
are given in Table 10.
There is no mechanism to disable the Watchdog Timer.
RESET clears the Watchdog Timer to Its initial value.
TABLE 10. WATCHDOG TIMEOUTS FOR COMMON OSCIN
FREQUENCIES
When the frequency has dropped below the preset threshold
a COP reset will take place. A COP reset is identical to a
POR or RESET pin reset, except the restart vector is the
COP Vector. Following the COP reset the HIP7030A2 is held
reset until the start-up timeout of 4064 clocks has been
reached. During the 4064 clocks the Slow Clock Detect circuit is inhibited. If at the end of the 4064 clocks the frequency remains below the threshold, a COP reset will
immediately take place again.
The primary purpose of this circuit is to force the HIP7030A2
off of the J1850 and SPI busses should the oscillator circuit
fail. Due to variability of integrated resistors and capacitors
there is a non-critical spread in the timeout specification of
approximately 5: 1. Maximum frequency threshold is 500kHz.
Refer to Electrical Specifications for details.
There is no means to disable the Slow Clock Detect. RESET
resets the Slow Clock Detect circuit and holds it reset until
the start-up timeout of 4064 clocks has been reached and
the RESET pin has gone high.
WATCHDOG TIMER
The Watchdog Timer is a free-running 21 stage counter
which divides the OSCIN input by 2,097,152. The Timer is
software reset-able, and must be constantly reset before the
terminal count is reached. Failure to reset the Watchdog
Timer, in due time, results in a forced MCU RESET via a
COP interrupt.
7
6
5
4
3
2
Watchdog Reset Register
WRR (LOCATION $10)
Resetting the Watchdog Timer requires two distinct operations. A write of the value $55 to the Watchdog Reset Register (WRR, location $10) must be followed by a write of the
value $AA to the WRR. There is no limit on the time between
the writes, other than both must take place before the
Watchdog Timer has reached its limit. Typically the two
writes are placed in distinct sections of code, which can only
be reached by proper flow through the software.
WATCHDOG
TIMEOUT
OSCIN FREQUENCY
(MHz)
175ms
12
21 Oms
10
262ms
8
524ms
4
Effects of Stop and Wait Modes on the
Timer, COp, and Serial Systems
INTRODUCTION
The STOP and WAIT instructions have different effects on the
programmable timer, VPW Symbol EncoderlDecoder (SEN·
DEC), and serial peripheral interface (SPI) systems. These
effects are discussed separately below.
STOP MODE
When the processor executes the STOP instruction, the
internal oscillator is turned off. This halts all internal CPU
processing including the operation of the programmable
timer, serial communications interface, and serial peripheral
interface. The only way for the MCU to "wake up· from the
STOP mode is by receipt of an external interrupt (logic low
on IRQ pin), a negative edge on the VPWiN pin, or by the
detection of a RESET (logic low on RESET pin or a poweron reset). Execution will resume at the instruction immediately following the STOP instruction that caused the
HIP7030A2 to enter the STOP mode.
Normally a start-up delay of 4064 teve is inserted after exiting from STOP before fetching the first instruction. This delay
is intended to guarantee stability of a crystal clock source. If
it is known that the clock source will be stable prior to exiting
STOP, then the NOEL bit in the SEDCR can be set prior to
executing the STOP instruction. Setting NOEL has the effect
of shortening the start-up delay to 128 tCYC.
The effects of the STOP mode on each of the MCU systems
(COP, Timer, SENDEC, and SPI) are described separately in
the following sections.
9-88
HIP7030A2
COP During STOP Mode
When the MCU enters the STOP mode. the Watchdog Timer
and the Slow Clock Detect circuits are both inhibited.
Timer During STOP Mode
When the MCU enters the STOP mode. the timer counter
stops counting (the internal processor is stopped) and
remains at that particular count value until the STOP mode is
exited by an interrupt (if exited by RESET the counter is forced
to $FFFC). If the STOP mode is exited by an external low on
the IRQ pin. then the counter resumes from its stopped value
as if nothing had happened. Another feature of the programmable timer. in the STOP mode. is that if at least one valid
input capture edge occurs at the TCAP pin. the input capture
detect circuitry is armed. This action does not set any timer
flags or "wake up" the MCU. but when the MCU does "wake
up" there will be an active input capture flag (and data) from
that first valid edge which occurred during the STOP mode. If
the STOP mode is exited by an external reset (logic Iowan
RESET pin). then no such input capture flag or data action
takes place even if there was a valid input capture edge (at the
TCAP pin) during the MCU STOP mode.
SENDEC During STOP Mode
When the MCU enters the STOP mode. the absence 01 any
internal clocks causes all SENDEC functions. except Wake
Up to cease. If the SENDEC was currently being used to transmit a symbol. that symbol is truncated and the VPWOUT is
forced to a low (passive) state. For proper operation. a STOP
instruction should not be executed except when the bus is Idle.
Normally all transitions are first filtered through the SENDECs three bit digital filter. When in STOP mode the 3-bit filter is bypassed and any passive to active transition (high to
low) on VPWIN will cause a SEN DEC interrupt which will. in
turn. cause the processor to exit the STOP mode.
Upon exiting the STOP mode the processor will execute a
SENDEC interrupt. The setting of the TX bit in the SEDSR
does not bypass the 7J.ls filter and as such the TX bit will not
be set when first awakening from STOP. If the NDEL bit has
been set prior to entering STOp, software should delay 8J.ls
and check TX. If at that time TX has not been set. the
assumption can be made that a noise pulse caused the
wakeup and the STOP mode can be reentered. When NDEL
is not employed monitoring of TX must continue for several
hundred microseconds. as a complete message could have
transpired during the oscillator start-up time.
During handling of a SEN DEC interrupt following STOP. the
SEDSR must be read at least one time to remove the source
of the interrupt.
SPI During STOP Mode
When the MCU enters the STOP mode. the baud rate generator which drives the SPI shuts down. This essentially stops
all master mode SPI operation. To ensure the SPI bus
remains free for transfers. the MSTR bit in the SPCR is
cleared. configuring the SPI pins in slave mode. If the STOP
instruction is executed during an SPI transfer. in which the
HIP7030A2 was the master. that transfer is aborted. If the
STOP mode is exited by a RESET, then the appropriate con-
troVstatus bits are cleared and the SPI is disabled. If the
device is in the slave mode when the STOP instruction is
executed. the slave SPI will still operate. It can still accept
data and clock information in addition to transmitting its own
data back to a master device.
At the end of a possible transmission with a slave SPI in the
STOP mode. no flags are set until an IRQ or SEN DEC interrupt results in an MCU ·wake up". Caution should be
observed when operating the SPI (as a slave) during the
STOP mode because none of the protection circuitry (write
collision. mode fault. etc.) is active.
WAIT MODE
When the MCU enters the W/lJT mode. the CPU clock is
halted. All CPU action is suspended; however. the timer.
SENDEC. and SPI systems remain active. In fact an interrupt from the timer. SENDEC. or SPI (in addition to a logic
Iowan the IRQ or F'iESET pins) causes the processor to exit
the WAIT mode. Since the three systems mentioned above
operate as they do in the normal mode. only a general discussion of the WAIT mode is provided below.
Note that the Slow Clock Detect and Watchdog Timer circuitry continues to function during WAIT. It is requisite upon
the designed to ensure that the CPU is removed from WAIT
(via an external or TIMER or SEN DEC interrupt) frequently
enough to prevent a Watchdog Timer overflow.
The WAIT mode power consumption depends on how many
systems are active. The power consumption will be highest
when all the systems (timer. TCMP. SEN DEC. and SPI) are
active. The power consumption will be the least when the
SENDEC and SPI systems are disabled (timer operation
cannot be disabled in the WAIT mode). If a non-RESET exit
from the WAIT mode is performed (I.e .• timer overflow interrupt exit). the state of the remaining systems will be
unchanged. If a RESET exit from the WAIT mode is performed all the systems revert to the disabled reset state.
Instruction Set
The MCU has a set of 62 basic instructions. They can be
divided into five different types: register/memory. read- modify-write. branch. bit manipulation. and control. The following
paragraphs briefly explain each type. All the instructions
within a given type are presented in individual tables.
RegisterlMemory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the
addressing modes. The operand for the jump unconditional
(JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 11.
Read-Modify-Wrlte Instructions
These instructions read a memory location or a register. modify or test its contents. and write the modified value back to
memory or to the register. The test for negative or zero (TST)
instruction is an exception to the read-modify-write sequence
since it does not modify the value. Refer to Table 12.
9-89
TABLE 11. REGISTERIMEMORY INSTRUCTIONS
ADDRESSING MODES
IMMEDIATE
FUNCTION
~
OP
MNEM CODE
DIRECT
NO.
OP
NO.
BYTES CYCLES CODE
INDEXED
(NO OFFSET)
EXTENDED
NO.
NO.
OP
NO.
NO.
OP
BYTES CYCLES CODE BYTES CYCLES CODE
INDEXED
(S-BIT OFFSET)
INDEXED
(16-BIT OFFSET)
NO.
OP
OP
NO.
NO.
NO.
NO.
NO.
BYTES CYCLES CODE BYTES CYCLES CODE BYTES CYCLES
Load A from
Memory
LDA
A6
2
2
B6
2
3
C6
3
4
F6
1
3
E6
2
4
D6
3
5
Load X from
Memory
LDX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
Store A
in Memory
STA
·
·
·
B7
2
4
C7
3
5
F7
1
4
E7
2
5
07
3
6
Store X
in Memory
STX
·
·
·
BF
2
4
CF
3
5
FF
1
4
EF
2
5
DF
3
6
Add Memory
toA
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
3
EB
2
4
DB
3
5
Add Memory
and Carry to A
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract
Memory
SUB
AO
2
2
eo
2
3
CO
3
4
FO
1
3
EO
2
4
DO
3
5
Subtract
Memory From A
With Borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
02
3
5
AND Memory
toA
AND
A4
2
2
B4
2
3
C4
3
4
F4
1
3
E4
2
4
D4
3
5
OR Memory
With A
ORA
AA
2
2
BA
2
3
CA
3
4
FA
1
3
EA
2
4
DA
3
5
Exclusive OR
Memory With A
EOR
AS
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
D8
3
5
Arithmetic
Compere
A With Memory
CMP
A1
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
01
3
5
Arithmetic
Compere X
With Memory
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
03
3
5
Bit Test Memory
BIT
AS
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
05
3
5
·
·
Be
2
2
CC
3
3
FC
1
2
EC
2
3
DC
3
4
·
·
BO
2
2
CD
3
3
FD
1
5
ED
2
6
DD
3
~
'li
~
Co,)
~
I\)
With A (Logical
Compare)
Jump
Unconditional
JMP
Jump to
Subroutine
JSR
I
·
7J
TABLE 12. READ-MODlFY·WRITEINSTRUCTIONS
ADDRESSING MODES
INHERENT (A)
INHERENT (X)
OP
CODE
NO.
NO.
BYTES CYCLES
INDEXED
8-BIT OFFSET)
MNEM
OP
CODE
Increment
INC
4C
3
3C
2
5
7C
1
5
6C
2
6
-
-
.
-
Decrement
DEC
4A
1
3
5A
1
3
3A
2
5
7A
1
5
SA
2
6
Clear
CLR
4F
1
3
5F
1
3
3F
2
5
7F
1
5
6F
2
6
Complement
COM
43
1
3
53
1
3
33
2
5
73
1
5
63
2
6
Negate
(2'$ Complement)
NEG
40
1
3
50
1
3
30
2
5
70
1
5
60
2
6
Rotate Left Thru
Carry
ROL
49
1
3
59
1
3
39
2
5
79
1
5
69
2
6
Rotate Right Thru
Carry
ROR
46
1
3
56
1
3
36
2
5
76
1
5
66
2
6
Logical Shift Left
LSL
48
1
3
58
1
3
38
2
5
78
1
5
68
2
6
Logical Shift Righi
LSR
44
1
3
54
1
3
34
2
5
74
1
5
64
2
6
Arithmetic
Shift Right
ASR
47
1
3
57
1
3
37
2
5
77
1
5
67
2
6
Test for Negative or
Zero
TST
40
1
3
50
1
3
3D
2
4
70
1
4
60
2
5
Multiply
MUL
42
1
11
-
-
-
-
-
-
-
-
-
-
FUNCTION
NO.
NO.
BYTES CYCLES
INDEXED
(NO OFFSET)
DIRECT
OP
CODE
NO.
NO.
BYTES CYCLES
OP
CODE
NO.
NO.
BYTES CYCLES
OP
CODE
NO.
NO.
BYTES CYCLES
I
<0
~
MULTIPLEX
COMM. CIRCUITS
!
'b
==
~
Co)
~
I\)
HIP7030A2
Branch Instructions
Bit Manipulation Instructions
Most branch instructions test the state of the condition code
register and if certain criteria are met. a branch is executed.
This adds an offset between -127 and +128 to the current
program counter. Refer to Table 13.
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space except for
ROM. port 0 data location ($03). serial peripheral status register ($08). serial communications status register (10). timer
status register ($13). and timer input capture register ($14$15). All port registers. port OORs. timer. two serial systems.
on-chip RAM. and 48 bytes of ROM reside in the first 256
bytes (page zero). An additional feature allows the software
to test and branch on the state of any bit within the first 256
locations. The bit set. bit clear. and bit test and branch functions are all implemented with a single instruction. For the
test and branch instructions. the value of the bit tested is
automatically placed in the carry bit of the condition code
register. Refer to Table 14.
TABLE 13. BRANCH INSTRUCTIONS
RELATIVE ADDRESSING
MODE
MNEM
OP
CODE
NO.
BYTES
NO.
CYCLES
Branch Always
BRA
20
2
3
Branch Never
BRN
21
2
3
Branch IFF Higher
BHI
22
2
3
Branch IFF lower or
Same
BLS
23
2
3
Branch IFF Carry
Clear
BCC
(Branch IFF Higher or
Same)
(BHS)
Branch IFF Carry Set
BCS
25
2
3
(Branch IFF lower)
(BlO)
25
2
3
Branch IFF Not Equal
BNE
26
2
3
Branch IFF Equal
BEQ
27
2
3
Branch IFF Half Carry
Clear
BHCC
28
2
3
Branch IFF Half Carry
Set
BHCS
29
2
3
Branch IFF Plus
BPl
2A
2
3
Bitn~Set
Branch IFF Minus
BMI
2B
2
3
Branch IFF
Bit n is Clear
Branch IFF Interrupt
Mask Bit is Clear
BMC
2C
2
3
Branch IFF Interrupt
Mask Bit is Set
BMS
20
2
3
Branch IFF Interrupt
Line is low
Bil
2E
2
3
Branch IFF Interrupt
Line is High
BIH
2F
2
3
Branch to Subroutine
BSR
AD
2
6
FUNCTION
TABLE 14A. BIT MANIPULATION INSTRUCTIONS
BIT SET/CLEAR
24
2
3
FUNCTION
24
2
3
Set Bit n
MNEM
BSET
OP
CODE
NO.
BYTES
NO.
CYCLES
10 + 20n
2
5
11 +2on
2
5
n(n=0 ...7)
ClearBitn
BClR
n (n = 0 ...7)
TABLE 14A. BIT MANIPULATION INSTRUCTIONS
BIT TEST AND BRANCH
FUNCTION
Branch IFF
9-92
OP
CODE
NO.
BYTES
NO.
CYCLES
BRSET
n (n = 0 ... 7)
2-n
3
5
BRClR
n (n = 0 ... 7)
01 + 2-n
3
5
MNEM
HIP7030A2
Control Instructions
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 15.
TABLE 15. CONTROL INSTRUCTIONS
INHERENT
The term "effective address· (EA) is used in describing the various addressing modes, and is defined as the byte address to or
from which the argument for an instruction is fetched or stored.
The ten addressing modes of the processor are described
below. Parentheses are used to indicate "contents of" the location or register referred to; e.g., (PC) indicates the contents of
the location pointed to by the PC. An arrow indicates "is
replaced by", and a colon indicates concatenation of two bytes.
Inherent
MNEM
OP
CODE
NO.
BYTES
NO.
CYCLES
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
In inherent instructions, all the information necessary to execute the instruction is contained in the opcode. Operations
specifying only the index register or accumulator, and no
other arguments, are included in this mode.
Set Carry Bit
SEC
99
1
2
Immediate
Clear Carry Bit
CLC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask
Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No-Operation
NOP
90
1
2
EA= (PC +1); PC +- PC + 2
Address Bus High 0; Address Bus Low +- (PC + 1)
FUNCTION
In immediate addressing, the operand is contained in the byte
immediately following the opcode. Immediate addressing is
used to access constants which do not change during program
execution (e.g., a constant used to initialize a loop counter).
EA=PC+l;PC+-PC+2
Direct
Stop
STOP
8E
1
2
Wait
WAIT
8F
1
2
In the direct addressing mode, the effective address of the
argument is contained in a single byte follOWing the opcode
byte. Direct addressing allows the user to directly address the
lowest 256 bytes in memory with a single two byte instruction.
This includes most on-Chip RAM and all VO registers. Direct
addressing is efficient in both memory and time.
Extended
Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 16.
OpcodeMap
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the
opcode. instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three-byte instruction.
EA = (PC + 1): (PC + 2); PC +- PC + 3
Table 17 is an opcode map for the instructions used on the
MCU.
Address Bus High +- (PC + 1); Address Bus Low +- (PC + 2)
Indexed, No Offset
Addressing Modes
The MCU uses ten different addressing modes to provide the
programmer with an opportunHy to optimize the code to all sHuations. The various indexed addressing modes make Hpossible
to locate data tables, code conversion tables, and scaling tables
anywhere in the memory space. Short indexed accesses are
single byte instructions, while the longest instructions (three
bytes) permit accessing tables throughout memory. Short
absolute (direct) and long absolute (extended) addressing are
also included. One and two byte direct addressing instructions
access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory. Table 17
shows the addressing modes for each instruction, with the
effects each instruction has on the condition code register.
In the indexed, no offset addressing mode, the effective
address of the argument Is contained in the S-bit index register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or VO location.
EA = X; PC +- PC + 1
Address Bus High +- 0; Address Bus Low +- X
Indexed, 8-Bit Offset
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore,
the operand is located anywhere within the lowest 511 mem-
9-93
HIP7030A2
ory locations. For example, this mode of addressing is useful
for selecting the mth element in a n element table. All
instructions are two bytes. The content of the index register
(5) is not changed. The content of (PC + 1) is an unsigned Sbit integer. One byte offset indexing permits look-up tables to
be easily accessed in either RAM or ROM.
EA
=X + (PC + 1); PC +- PC + 2
EA1
=(PC +1)
Address Bus High
Address Bus High +- K; Address Bus Low +- X + (PC + 1)
where: K
opcode byte (EA1). The signed relative S-bit offset is in the
third byte (EA2) and is added to the PC if the specified bit is
set or cleared in the specified memory location. This single
three byte instruction allows the program to branch based on
the condition of any bit in the first 256 locations of memory.
a 0; Address Bus Low +- (PC + 1)
EA2 = PC + 3 + (PC + 2); PC +- EA2 if branch taken;
=the carry from the addition of x + (PC + 1).
otherwise, PC +- PC + 3.
Indexed, 16-Bit Offset
In the indexed, 16-bit offset addressing mode, the effective
address is the sum of the contents of the unsigned S-bit index
register and the two unsigned bytes following the opcode.
This addressing mode can be used in a manner similar to
indexed S-bit offset. except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). The content of the index register is not changed.
Power Considerations
The average chip-junction temperature, T J, in
obtained from:
TJ
= TA + (PD-eJM
Where:
TA
(Ea. 1)
=Ambient Temperature, °c
Junction-to-Ambient, °cm
Address Bus High +- (PC + 1) + K
= PINT + Pvo
Address Bus Low +- X + (PC + 2)
Po
where: K = The carry from the addition of X + (PC + 2).
PINT
Pvo
Relative
=Icc·Vcc , Watts - Chip Internal Power
=Power Dissipation on Input and Output
Pins - User Determined
Relative addressing is only used in branch instructions. In
relative addressing, the content of the S-bit signed byte following the opcode (the offset) is added to the PC if and only
if the branch condition is true. Otherwise, control proceeds to
the next instruction. The span of relative addressing is limited to the range of -126 to +129 bytes from the branch
instruction opcode location.
For most applications Pvo < PINT and can be neglected.
An approximate relationship between Po and TJ (if PlIO is
neglected) is:
Po = K I (TJ + 273°C)
(Ea. 2)
Solving equations 1 and 2 for K gives:
EA = PC + 2 + (PC + 1); PC +- EA if branch taken;
(Ea. 3)
=PC +- PC + 2.
Bit SettClear
Direct addressing and bit addressing are combined in
instructions which set and clear individual memory and I/O
bits. In the bit set and clear Instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified in the first three bits
of the opcode. The bit set and clear instructions occupy two
bytes, one for the opcode (including the bit number) and the
other to address the byte which contains the bit of interest.
EA
can be
9JA =Package Thermal Resistance
EA = X + [(PC + 1) : (PC + 2)]; PC +- PC + 3
otherwise, EA
°c
Where K is a constant pertaining to the particular part. Kcan
be determined from Equation 3 by measuring Po (at equilibrium) for a know TA. Using this value of K, the values of Po
and TJ can be obtained by solving Equation 1 and Equation
2 iteratively for any value of TA.
-d
Veo
TEST
POINT
e =
R2
RI
=(PC + 1); PC +- PC + 2
EQUIVALENT TEST LOAD
Address Bus High +- 0; Address Bus Low +- (PC + 1).
Bit Test and Branch
Bit test and branch is a combination of direct addressing, b~
setlclear addressing, and relative addressing. The actual bit to
be tested, within the byte, is specified within the low order nibble of the opcode. The address of the data byte to be tested is
located via a direct address in the location following the
9-94
(SEE TABLE FOR VALUES OF RI AND R2 )
PINS
RI
R2
C
V oo =4.5V
PAO - PA7, POO - P04
3.26kn
2.38kO
50pF
1.9kn
2.2kn
200pF
MISO, MOSI, SCK
HIP7030A2
TABLE 16. INSTRUCTION SET
CONDITION
CODES
ADDRESSING MODES
MNEM
INDEXED
BITTEST
(NO
INDEXED INDEXED BITSETI
AND
INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (8 BITS) (16 BITS) CLEAR BRANCH H I N Z C
·
·
·· ·
··
··
·····
·····
·····
·· ···
·····
·····
·····
·····
·····
·····
··
· · ···
·· ···
·····
·····
·····
·····
·· ···
·····
·····
····
····
·····
·····
····
· ···
·· ·
··
··
··
·· ·
··
··
ADC
X
X
X
X
X
X
A
A A A
ADD
X
X
X
X
X
X
A
A A A
AND
X
X
X
X
X
X
ASL
X
X
X
X
ASR
X
X
X
X
A
A A A
X
BCC
X
BCLR
BCS
X
BEQ
X
BHCC
X
BHCS
X
BHI
X
BHS
X
BIH
X
BIL
X
BIT
X
X
X
X
BLO
X
BLS
X
BMC
X
BMI
X
BMS
X
BNE
X
BPL
X
BRA
X
BRN
X
X
A A •
X
BRCLR
X
BRSET
X
BSET
X
BSR
X
CLC
X
CLI
X
CLR
X
CMP
COM
DEC
INC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
0
X
EOR
A
0
X
CPX
A
A A A
X
X
X
0 1
X
A A A
A A 1
X
A A
A A
X
A A •
A A •
9-95
~
><-
UJ::;)
..JO
o.!!:
-0
!:i.
::;):E
:E:E
o
o
HIP7030A2
TABLE 16. INSTRUCTION SET (Continued)
CONDITION
CODES
ADDRESSING MODES
MNEM
INDEXED
BITTEST
(NO
INDEXED INDEXED BITSETI
AND
INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (8 BITS) (16 BITS) CLEAR BRANCH H I N Z C
JMP
X
X
X
X
X
JSR
X
X
X
X
X
LOA
X
X
X
X
X
X
LOX
X
X
X
X
X
X
LSL
X
X
X
X
LSR
X
X
X
X
MUL
X
NEG
X
X
X
X
NOP
X
X
X
X
X
X
X
X
ROR
X
X
X
X
RSP
X
RTI
X
RTS
X
SBC
X
SEI
X
X
X
X
X
X
X
X
X
X
X
X
SWI
X
X
TST
X
TXA
X
WAIT
X
• A A A
1
X
X
X
A A •
0
STX
TAX
• A A •
• A A A
A A A
X
SUB
0
• A A A
1
STA
STOP
0 A A
? ? ? ? ?
X
SEC
• A A •
A •
• A
• A A A
0
ROL
ORA
·····
·····
·
·
·
··
···
·
·····
·
·
·· ·· · · ·
·····
·
····
· ···
·· · · · ·
·
·
· ···
·· ·· · · ·
·····
· ···
X
X
X
X
X
X
X
X
X
X
• A A •
• A A A
1
X
X
X
A A •
0
..
Condition Code Symbols:
H =Half Carry (from Bit 3)
A =Test and Set il True Cleared Otherwise
I =Interrupt Mask
• = Not Affected
N =Negate (Sign Bit)
?
Z = Zero 0 = Cleared
C =CarrylBorrow 1 =Set
=Load CC Register From Stack
9-96
TABLE 17. HCMOS INSTRUCTION SET OPCODE MAP
BIT
MANIPULATION
HI
LOW
~
!
BRANCH
READlMODlFYIWRITE
BTB
BSC
REL
DIR
0
0000
1
0001
2
0010
CONTROL
REGISTERIMEMORY
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
3
4
0110
7
0111
8
1000
9
0100
5
0101
6
0011
1001
A
1010
B
1011
C
1100
D
1101
E
1110
1111
HI
F
LOW
0
0000
5
5
3
5
3
3
6
5
9
BRSETO BSETO
BRA
NEG
NEGA
NEGX
NEG
NEG
RT!
INH 1
BTB 2 BSC 2
REL 2
DIR 1
NH 2
IXl 1
IX 1
INH
3
2
3
4
4
5
3
SUB
SUB
SUB
SUB
SUB
SUB
2
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
1
0001
5
5
3
BRCLRO BCLRO
BRN
BTB 2 BSC 2
REL
3
6
2
4
4
3
3
5
CMP
CMP
CMP
CMP
CMP
CMP
2
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
1
0001
2
0010
5
5
3
BRSET1 BSETl
BHI
BTB 2 BSC 2
REL
3
11
MUL
1
INH
4
2
4
5
3
3
SBC
SBC
SBC
SBC
SBC
SBC
IMM 2
2
DIR 3
EXT 3
1X2 2
IXl 1
IX
2
0010
3
0010
10
3
5
3
3
6
5
5
5
COMA
COMX
COM
SWI
BRCLRl BCLRl
BLS
COM
COM
INH 1
INH 2
IXl 1
INH
IX 1
BTB 2 BSC 2
REL 2
DIR 1
3
2
4
4
5
3
3
CPX
CPX
CPX
CPX
CPX
CPX
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
2
3
0010
4
0100
3
3
6
5
5
5
5
3
LSRA
LSRX
LSR
LSR
BRSET2
BSET2
BCC
LSR
INH 1
IXl 1
BTB 2 BSC 2
REL 2
DTR 1
INH 2
IX
3
5
0100
5
3
5
BRCLR2 BCLR2
BCS
BTB 2 BSC 2
REL
3
2
3
3
5
6
5
5
5
3
RORA
RORX
ROR
ROR
BRSET3 BSET3
BNE
ROR
DIR 1 INHY 1
INH 2
IXl 1
IX
BTB 2 BSC 2
REL 2
3
2
3
4
4
3
5
LOA
LOA
LOA
LOA
LOA
LOA
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
2
6
0110
7
0111
8
1000
9
1001
A
1010
RTS
1
INH
2
2
3
4
5
4
3
AND
AND
AND
AND
AND
AND
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
2
3
4
5
4
3
BIT
BIT
BIT
BIT
BIT
BIT
IMM 2
DIR 3
EXT 3
1X2 2
IXl 1
IX
4
4
5
6
5
STA
STA
STA
STA
STA
IXl 1
IX
2
DIR 3
EXT 3
1X2 2
3
3
6
5
5
3
5
5
ASRA
ASRX
ASR
ASR
BRCLR3 BCLR3
BEQ
ASR
INH 1
IXl 1
REL 2
DIR 1
INH 2
IX
BTB 2 BSC 2
3
2
TAX
1
INH
5
6
3
3
5
5
5
3
BHce
LSL
LSLA
LSLX
LSL
LSL
BRSET4 BSET4
1
IXl 1
IX
REL 2
DIR llNH
INH 2
BTB 2 BSC 2
3
4
4
2
2
3
5
3
EOR
EOR
EOR
EOR
EOR
EOR
CLC
IMM 2
IXl 1
IX
EXT 3
1
INH 2
DIR 3
1X2 2
6
5
3
3
5
5
3
5
ROL
ROL
ROLA
ROLX
ROL
BRCLR4 BCLR4
BHCS
INH 1
IXl 1
REL 2
DIR 1
INH 2
IX
BTB 2 BSC 2
3
3
2
4
4
2
3
5
ADC
ADC
ADC
ADC
ADC
ADC
SEC
IXl 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
1X2 2
5
3
3
3
6
5
5
5
DECA
DECX
DEC
DEC
BPL
DEC
BRSET5 BSET5
IX
INH 1
IXl 1
REL 2
DIR 1
INH 2
BTB 2 BSC 2
3
4
3
4
2
5
3
2
ORA
ORA
ORA
ORA
ORA
ORA
CLI
EXT 3
IXl 1
IX
1
INH 2
IMM 2
DIR 3
1X2 2
0
0000
4
0100
"
~
Co)
~
I\)
5
0100
6
0110
7
0111
8
1000
9
1001
A
1010
~-
MULTIPLEX
COMM. CIRCUITS
~
TABLE 17. HCMOS INSTRUCTION SET OPCODE MAP (ContInued)
BIT
MANIPULATION
LOW
HI
B
1011
C
1100
0
1101
E
1110
~
F
1111
BRANCH
BSC
REL
0
1
0001
2
3
0010
0011
0000
5
5
CONTROL
READlMODlFYIWRITE
BTB
DIR
INH
1X1
IX
INH
4
5
0100
0101
6
0110
7
0111
INH
REGISTERIMEMORY
INH
IMM
DlR
EXT
IX2
IX1
IX
8
9
1000
1001
A
1010
B
1011
C
1100
D
1101
E
1110
1111
3
2
8M1
BRCLR5 BCLR5
REL
3 BTB 2 BSC 2
1
F
HI
B
1011
2
3
4
3
2
JMP
JMP
JMP
JMP
JMP
2
DIR 3
EXT 3
1X2 2
IXl 1
IX
C
1100
ADD
SEI
ADD
INH 2
IMM 2
DIR
4
4
3
5
3
3
6
5
5
5
INC
INCA
INCX
INC
INC
BRSET6 BSET6
BMC
DIR 1
INH 1
INH 2
IXl 1
REL 2
IX
3 BTB 2 BSC 2
1
4
4
3
3
3
5
5
5
TSTA
TSTX
TST
TST
BRCLR6 BCLR6
BMS
TST
INH 1
IX1 1
REL 2
DIR 1
INH 2
IX
3 BTB 2 BSC 2
2
6
5
6
7
5
6
NOP
BSR
JSR
JSR
JSR
JSR
JSR
DIR 3
INH 2
REL 2
EXT 3
IXl 1
1
1X2 2
IX
5
5
3
BlL
BRSET1 BSET1
REL
3 BTB 2 BSCI2
5
5
3
2
ASP
INH
2
STOP
INH
1
5
3
3
6
5
2
3
2
LOX
IMM
2
LOX
2DIR
4
4
5
3
LOX
LOX
LOX
LOX
3
EXT 3
1X2 2
IXl 1
IX
5
4
2
WArT
CLRA
CLR
TXA
CLRX
BlH
CLR
CLR
BRCLR7 BCLR7
DIR 1
INH 1
INH 2
IXl 1
IX 1
INH 1
INH
REL 2
3 BTB 2· BSC 2
-
Abbreviations for Address Modes:
A = AcculTIJlator
X = Index Register
=
=
=
BTB =BIt Test end Brench
4
-
LEGEND
=Inherent
IMM .. Immediate
DIR= Direct
EXT Extended
REL Rela1lve
BSC BIt SetlClear
5
6
STX
STX
STX
STX
STX
2
DIR 3
EXT 3
1X2 2
IX
IXl 1
-
INH
LOwl
5
3
ADD
ADD
ADD
ADD
3 EXT 3
1X2 2
IX1 1
IX
3
2
..
=
70PCODE IN
HEXADECIMAL
I----II--s;t--;. OPCODE IN
BINARY
MNEMONIC
BYTES
CYCLES
"'
ADDRESS
MODE
0
1101
E
1110
F
1111
;s
"1:1
C:I
Ci.)
~
HIP703BAB
J1850 8-Bit 68HC05 Microcontroller
8K EEPROM Version
PRELIMINARY
April 1994
Features
Description
• Direct Replacement for HIP7030A2IA8 Mlcrocontrollers
- All Hardware and Software Features
The HIP7038A8 HCMOS Microcomputer is an EEPROM
version of the HIP7030A family of low-cost single-chip J1850
microcontrollers. These microcontrollers provide the system
designer with a complete set of building blocks for implementing a ·Class B" VPW multiplexed communications
network interface, which fully complies with SAE Recommended Practice J1850. The HIP7038A8 contains all hardware and software features of the HIP7030A21A8
microcontrollers with equivalent timing, performance characteristics, and an identical footprint.
- Equivalent Timing and Performance
• Memory
- 176 Bytes of RAM
- 7744 Byles of Programmable EEPROM
- 242 Bytes of Bootstrap Program
• Single 5V Supply
• 1OMHz Operating Frequency (5.0MHz Internal Bus
Frequency) at 5V.
• 28 Lead Small Outline Ceramic Package
- Same Terminal Assignment as HIP7030A2
and HIP7030A8
The device can be programmed using the HIP7038A8
EEPROM Programmer available from Harris. In-circuit Emulation Tools are also provided for system development.
Ordering Information
PART NUMBER
HIP7038A8F
TEMPERATURE
RANGE
PACKAGE
-400C to +8SoC
28 Lead Ceramic SOIC
Pinout
HIP7038A8 (SOIC FLATPACK)
TOP VIEW
f!?
)(-
w:::l
55
~o
Il..!!:
MlSO
VPWIN
3
-0
!:i
.
:::l:ii
:ii:ii
0
0
MOSI
SCK
VPWOUT
RESET
iRQ
OSCIN
OSCOUT
Voo
Vss
PA6
POI
POO
PAS
PD2, V2
PM
P03, V3
PA3
PD4, VREF
PA2
osce
PAl
PAO
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
9-99
File Number
3647.1
HIP703BAB
Block Diagram
OSCOUT
TCAP
III
zw
:l
nMERSYSTEM
__- - - - - 5 RESET
...--_ _ _
8
nm
PAO
PAt
PA2
PORT
A
REG
g
c
Ii:
DATA
DlR
REG
2
ACCUMULATOR
A
INDEX
REGISTER
8
X
CONDInON
CODE
REGISTER cc
8
5
UI
w
z
:::I
PORTO PORTO
SFR
DIR
REG
REG
g
c
~
8
STACK
POINTER
CPU
5
8
PROGRAM
COUNTER
LOW
PCL
7
7744x8
EEPROM
242x8
BUILT..JN·TEST
EEPROM
9·100
SCK
MOS!
MlSO
S
PROGRAM
COUNTER
HIGH PCH
Vss 22
VOO
CPU
CONTROL
is
ALU
INTERNAL
PROCESSOR
CLOCK
Specifications HIP703BAB
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Voo) •.....•....•••..••••.•••. -O.3V to +6.ov
Input or Output Voltage
Pins with Voo Diode ••...•..••..•••••••• -O.3V to Voo +O.3V
Pins without Voo Diode ..•..•....•..•••••.•• -o.3V to +10.0V
Current Drain Per Pin, I (Excluding Voo and Vss) ••...•••. 2SrnA
ESD Classification .••.••..•..••..••••••.•••...•••• Class 2
Gate Count. •.•......•..•••••..•••.••••.••••• 21000 Gates
Operating Temperature Range (TAl •............ -400C to +12SOC
Storage Temperature Range (TSTO) ..•..••••..• -6SoC to + 150°C
Junction Temperature ••••.•.•••••.•..••.••.•....••. + 150°C
Lead Temperature (During Soldering) •••..••••..••••.. +26SoC
1/16in. ± 11321n. (1.S9 ± O.79mm) from case for lOs Max.
CAUTION: Stresses above those listed in "AbsolufB Maximum Ratings' may cause permanent damage to IhfI device. This is a strBSS only rating and operation
01 the device at these or any other conditions above those indicated in thB operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. • . . . . . . . . . . • • . . . . • •• +4.SV to +S.5V
Operating Temperature Range .....••....••..•• -400C to +85°C
Input Low Voltage .•...•....•••.•....•.••.•.•.•. OV to +0.8V
DC Electrical Specifications
PARAMETERS
Input High Voltage •.•.•.•......•....••..•...(0.8o Voo ) to Voo
Input Rise and Fall TIme
CMOS Inputs ••••.....••..••••....••..•.•.... lOOns Max.
CMOS Schmitt Inputs .•••••••••••.•.•.••..•••••. Unlimited
voo = sVoc ±lO%, Vss = oVoc , TA = -4OOC to +85"C Unless Otherwise Specifled.
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
rnA
V
SUPPLY CURRENT
RUN
IRUN
-
50
WAIT
IWAIT
-
4
STOP
ISTOP
TA = +25°C
-
100
TA = -4Q°C to +85°C
-
100
-
-0.3
-
9
~o~nput
Voltage:
RESET, IRQ, VPWIN, OSCIN
VINPo
Voo=O
rnA
I1A
I1A
NOTE:
1. This device contains circuitry to protect the inputs against damage due to high static voltages of electriC fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maxlmum rated voltages to this high impedance circuit. For
proper operation it is recommended that VIN and VOUT be constrained to the range VSS«VIN or VOUT), permitting programmable
variation of the integrated circuit sensitivity with either digital
and/or analog programming signals. For example, at an IASC
of 100(.1A, a 1mV change at the input will change the output
from 0 to 10011A (typical).
The CA3094 is intended for operation up to 24V and is
especially useful for timing circuits, in automotive equipment,
and in other applications where operation up to 24V is a
primary design requirement (see Figures 28, 29 and 30 in
Typical Applications text). The CA3094A and CA30948 are
like the CA3094 but are intended for operation up to 36V and
44V, respectively (single or dual supply).
These types are available in 8 lead T0-99 Metal Cans ("1"
suffix). Type CA3094 is also available in an 8 lead dual-inline plastic DIP package ("E" suffix) and Small Outline Package ("M" suffix).
PACKAGE
CA3094T, AT, BT
·55°C to +1250C 8 Lead Metal Can
CA3094E, AE, BE
·55°C to +125°C
8 Lead Plastic DIP
CA3094M, AM. SA
·55°C to +1250C
8 Lead Plastic SOIC (N)
(/)
...IZ
<0
U~
WO
D.Z
Pinouts
(/);:)
u..
CA3094 (PDIP, SOIC)
TOP VIEW
EXT. FREQUENCY
COMPENSATION
OR INHIBIT INPUT
8
CA3094 (CAN)
TOP VIEW
SINK OUTPUT
(COUECTOR)
DRIVE OUTPUT
(EMITTER)
5
•
IABC CURRENT
DRIVE OUTPUT
(EMITTER)
PROGRAMMABLE ]
[ INPUT
(STROBE OR AGC)
NOTE: Pin 4 is connected to case
GND (V-IN DUAL
SUPPLY OPERATION)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
10-11
File Number
598.3
Specifications CA3094, CA3094A, CA3094B
Absolute Maximum Ratings
Thermal Information
Dual Supply Voltage
CA3094 .••.•••.•.•••.••••••.•.•.•••.••••••.••••.•••. ±12V
CA3094A ••••••.•.••••.••••••••.••••.•••••••••.•.•••. ±18V
CA3094B ...•••••.•.•..••••••.•.••.•.••••••..•....••. mv
Single Supply Voltage
CA3094 •.•...••.•.••••...••.•..•••••••••••••••••• 24V
CA3094A •••••••..•••••.•••••••••••••••••.•••••••• 36V
CA3094B •••••••••••.•••.•••••.••••••••••••••••••• 44V
Differential Input Voltage (Term. 2 and 3) Note 1 ••••..••••••• 5V
DC Input Voltage •.•••....•••..••••••••••••••••••• V+ to VInput Current (Term. 2 and 3) ••.•••••.•.•.••••••••••••••.. ±1mA
Amplilier Bias Current (Term. 5) •••••••••••••.••••••••••• 2mA
Average Output Current. •.•.•••...•••••••••.•••••••• 100mA
Peak Output Current. ••.••••••....•••.•••••••.•••••. 300mA
Thermal Resistance
9JA
9JC
Plastic DIP Package • • • • • • • • • • • • • • • • 151JOC1tN
Plastic SOIC Package. • • • • • • • • • • • • • • 17O"CNV
Metal Can ••••••••••••••••••••• • • • 156"CNV 68"CNV
Junction Temperature ••••••.••••.••.••••••••••••••• +175°C
Junction Temperature (Plastic Package) •••••••••••••••• +15O"C
Lead Temperature (Soldering 1Os) •••••.••••••••.•.•.• +300oC
(SOIC - Lead Tips Only)
Operating Temperature Range ••••••••.••••••• -55°C to +125°C
Storage Temperature Range ••••••••••••••••.• -65°C to + 15O"C
CAUTION: Stresses abo... those listed in "Abso/ul9 Maximum Ra6ngs' may cause permanent damage to ths device. This is a stress only rating and operation
of the dBvic8 at theSll or any other conditions abo... /hose Indicated in ths DperationsJ sections of /his specification Is not ImpUed.
Electrical Specifications
TA = +2500 lor Equipment Design. Single Supply v+ = 3OV. Dual Supplyv+ = 15V, V- = -15V,I ABC = 1C1011A
Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
-
-
MAX
UNITS
0.4
5.0
mV
-
7.0
mV
1
8.0
mV
0.02
0.2
-
0.3
0.70
IIA
IlA
IlA
IIA
INPUT PARAMETERS
Input Offset Voltage
TA=+25oo
VIO
TA = OOC to +7000
Input Offset Voltage Change
Input Offset Current
Change In VIO between IABC = 10011A
and IABC = 511A
14VIOI
110
TA = +2500
TA = OoC to +700C
Input Bias Current
Device Dissipation
Common Mode Rejection Ratio
Common Mode Input Voltage Range
II
Po
TA = +2500
-
TA = OOC to +700 C
-
0.50
8
10
12
mW
70
110
-
dB
V+ = 30V (High)
27
28.8
-
V
V- = OV (Low)
1.0
0.5
-
V
V+= 15V
12
13.8
V- = -15V
-14
-14.5
0.68
-
10UT=OmA
CMRR
VICR
0.2
30
-
MHz
4
-
kHz
V
V
Open Loop Bandwidth at -3dB Point
BWOL
Total Harmonic Distortion
(Class A Operation)
THO
Amplifier Bias Voltage
(Terminal 5 to Terminal 4)
VASe
-
Input Oflset Voltage Temperature
Coefficient
INtc!4T
-
4
-
Power Supply Rejection
4Vtc!4V
-
15
150
IlVN
18
-
nV/./Hz
Unity Gain Bandwidth
1/F Noise Voltage
Ic = 7.5mA, VCE = 15V, IABC = 50011A
'T
=
=15V,IASe =50011A
Po =220mW
Ic 7.5mA, Vee
PD=6OOmW
EN
I = 10Hz, IABC = 5011A
l/F Noise Current
IN
1= 10Hz, IABC = 501lA
Differential Input Resistance
RI
IABC = 2011A
Differential Input CapaCitance
CI
f = 1MHz, V+ = 30V
OUTPUT PARAMETERS (Differential Input Voltage
=1V)
10-12
0.4
1.4
-
1.8
0.50
1.0
-
2.6
-
%
%
V
IlVioo
pA/./Hz
MO
pF
Specifications CA3094, CA3094A, CA30948
Electrical Specifications
TA = +25"C for Equipment Design. Single SUpply V+ = 3OV, Dual Supply V+ .. 15V, V- .. -15V,IABC = l00!JA
Unless Otherwise Specified (Continued)
PARAMETERS
SYMBOL
Peak Output Voltage
(Terminal 6)
With a13 "ON"
V+OM
With a13 "OFF"
V-OM
Peak Output Voltage
(Terminal 6)
Positive
V+OM
Negative
V-OM
Peak Output Voltage
(Terminal 8)
With a13 'OFF"
V+OM
With a13 'ON"
V-OM
Peak Output Voltage
(Terminal 8)
Positive
V+OM
Negative
V-OM
Collector-to-Emitter Saturation Voltage
(Terminal 8)
VCE(SAT)
Output Leakage Current
(Terminal 6 to Terminal 4)
Composite Small Signal Current Transfer
Ratio (Beta) (a12 and a13)
Output Capacitance
Terminal 6
TEST CONDITIONS
MIN
TYP
MAX
UNITS
At. = 2kO to GND
26
27
-
V
-
0.01
0.05
V
11
12
-
V
V+ = 30V,
V+ = 15V, V- = -15V,
At. = 2kO to -15V
V+ = lOV, RL .. 2kO to 30V
V+= 15V, V- = -15V,
RL = 2kO to 15V
V+ = 30V, Ic = 50mA, Terminal 6
Grounded
V+=30V
-
-14.99
-14.95
V
29.95
29.99
-
V
-
0.040
V
14.95
14.99
-
-14.96
-
0.17
0.80
V
2
10
IIA
16,000
100,000
-
-
pF
VN
IImhos
hFE
V+ = 30V, VCE = 5V, Ic = 50mA
Co
f = 1MHz, All rernalnlng Terminals Tied
to Terminal 4
-
5.5
V+= 30V,IABC = l00IlA,4VOUT = 20V,
RL =2kO
20,000
100,000
Terminal 8
17
V
V
pF
TRANSFER PARAMETERS
Voltage Gain
A
Forward Transconductance to
Terminal 1
gM
Slew Rate (Open
Loop)
SR
Positive Slope
86
100
-
1650
2200
2750
-
IABC = 500llA, RL = 2kO
Negative Slope
Unity Gain (Non-Inverting Compensated)
-
IABC = 500llA, RL = 2kO
50
-
0.70
-
500
dB
VIlIS
VIlIS
VIlIS
NOTE:
1. Exceeding this voltage rating will not damage the device unless the peak Input signal current (1 mAl Is also exceeded.
Schematic Diagram
o
..JZ
<0
INPUTS
AMPLIFIER
BIAS INPUT 5 )---..--1::
IABC
10-13
OJ::
OUTPUT
MODE
OUTPUT
TERM
INV
NONINV
"Source"
6
2
3
"SInk"
8
3
2
wo
Q.Z
0::1
U.
CA3094, CA3094A, CA3094B
Typical Performance Curves
S
V+ .. +15V. V-. -15V
4
>"
g
3
2
I II
£:+2SOC
~ 1/-550C
~
Iii
~
~
i!:
0
-1
-2
II
V'
~
f'...:
-5
-6
I
0.1
102
~ ~
~
a:
a: 10'
u
Iw
+70"~ZV
-5SOC
Ie
+2SO~7'
II
-8
V+.+15V. V-.-15V
!zw
L
L
l!i
5
...
I I I
J
I
-7
C
.s.
V
::>
+70oC
+80oC
+12SoC
/~
...
-3
103
+1250~:~
+80oC-
-
w
!
II I _
II
i!:
I
....
""""
0.1
Ii'
0.01
1
10
100
AMPUAER BIAS CURRENT (IIA)
1000
L
-550C
+2SOC
' +12SoC
-1 -11
1.0
10
100
AMPUAER BIAS CURRENT (IIA)
0.1
FIGURE 1. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS
CURRENT (IABC' TERMINAL 5)
1/
....
1000
FIGURE 2. INPUT OFFSET CURRENT vs AMPLIFIER BIAS
CURRENT (IABc• TERMINAL 5)
105
v•• +1SV, y.. -15V
TA,"+25OC
~
~
;
;..-:;
Z
......
0
~
1
. --
--
~
:/
s:w
c 10 V
'
103
'"
102
V+ = +15V. V- .. -15V
15.0
TA" +12SOC
+250 C I--
€
A
w
q
a:
...
:i!
1.0
"""
~V+.+15V, V-.-15V
V+ • +BV. V-.-6V
V+ • +3V. V- .. -3V
1.0
10
100
AMPUAER BIAS CURRENT (IIA)
1000
I-
13.0
U
l.lV+CMR-tI
13.5
0
w
c -13.0
0
::E
1=+ 25°f
z -13.5
0
::E -14.0
.-.
~ ~+250C
8
f-- r--.-55OC
0.1
0.1
14.0
...i!:'"
......
w
ii:
:l
L
V+. +15V. V-. -15V
14.5 TA,"+25OC
!'-'
~
.L'
~
::> 10
"':
(J
"""
l
L
15 102
w
0.1
__
0.1 M81lA /T 1
10
100
AMPUAER BIAS CURRENT (IIA)
104
103
!Ii
40
w
35
""g
30
w
2S
.s.
~
~.§.
_w
~!;i
--
102
FREQUENCY (Hz)
FIGURE 7. 11F NOISE VOLTAGE VI FREQUENCY
10000
1.0
~
~
&OJ.IA
--
~
J' ~
~001lA
.....
10
""g
~
,~ r-.!ABcsSIIA
"
w
V+= +lSV, ¥-=·lSV
RssUID, TAs+2SOC
FOR TEST CIRCUIT, SEE FIGURE 20
.
·100
·150
·200
u
~
U
a:
CJ
w
e
::)
CJ
8
0
o'!l
103
z
~
z
----6
Eour
-!-CNOTE 1)
Where Eour = E'N L---~Mr--_.J
EOUT
(Z2)
Where -E-- '" 1 Z depends on the characteristics 01 Z1 and Z2
IN
1
FIGURE 26A.
FIGURE 26B.
NOTE: 1. In single-ended output operation, the CA3094 may require a puU up or pull down resistor
FIGURE 26. APPLICATION OF THE CA3094: (a) AS AN INVERTING OP AMP AND (b) IN A NON-INVERTING MODE, AS A FOLLOWER
V+_18V
~~~-~--~~--,
VOLTAGE A
:81
:
mv+ .------~
O~
,
Problem: To calculate the maximum value 01 R required to
switch a 100mA output current comparator
18V
2kn
A
PULL UP Given: I ABC '" 511 , RABC '" 3.6MO- 511A
R
I, = 500nA at IABC =lOO11A (from Figure 3)
I, = 51lA can be determined by drawing a line on Figure 3 through
IABC = l001lA and 18 = 500nA paraDe! to the typical TA = +25"<:
+1::rL
VOLTAGE AT
TERMINAL 8
A ~~+-{
lND14
curve.
Then: I, = 33nA at IABC = 51lA
EOUT
RMAX '"
c
j
RMAX '" 180MO x 2/3t '" 120MO at TA '" -55°C
t
=
TIME DELAY (SEC.). RC (APPROX.)
18V-12V
•
33nA
'" 180MO at T A '" +25 C
Ratio 01 I, at TA = +25"C to I, at TA = -55"C for any given
value 01 IABC
FIGURE 27. RC TIMER
A
V+-,
o
1..-_ _ _ _.1
B°-y------~l~---220kn
c
0 ~......- - - - - - - -
DO~
O.OI"F
INPUl >-1---:11--+
E~::r--l~------------_
Eour
On a negative going transient at Input (A), a negative
pulse at C will turn ·on· the CA3094, and the output (E)
wlU go from a low to a high level.
12VDC
j
At the end 01 the lima constant determined by Cl, Rl,
R2, R3, the CA3094 will return to the ·olr state and
the output wiD be puUed low by Rl.OAO- This condition
will be Independent 01 the Interval when Input (A)
returns to a high level.
FIGURE 28. RC TIMER TRIGGERED BY EXTERNAL NEGATIVE PULSE
1()"20
CA3094, CA3094A, CA3094B
Typical Applications (Continued)
+~~------------~~~-----------,
r---------------~--.,...---------o
I
I
5VDC
+15V
1110
1100
OUTPU1JU1.Il
EOUT
j
C
T
2ma
n
NOTES:
EOUTJ~L
1. R=lMO,C=lI1F
2. Time Constant: t - RC x 120
3. Pulse Width: CJ) - K(C 1/C)
LINU
FIGURE 29. FREE RUNNING PULSE GENERATOR
RGURE 30. CURRENT OR VOLTAGE CONTROLLED OSCIllATOR
15V
1110
300110
30V
5100
27110
300110
100110
LED
50110 ~~>------+
Rp
C
o
..JZ
ceo
27110
NOTE: 'OUT
=
2RC In ( R21
C
II:
FIGURE 31. SINGLE SUPPLY ASTABLE MULTIVIBRATOR
01=
w(,)
o..z
2R
FI:! = 3.08R h
+ 1)
1
'OUT
= RC
RGURE 32. DUAL SUPPLY ASTABLE MULTIVIBRATOR
MyiarTM is a trademark of E.I. Dupont de Nemours.
10-21
0:::1
LL.
CA3094, CA3094A, CA3094B
Typical Applications (Continued)
r-------~--------~~~~V
r-.....----~~-
2110
+1SV
1-_--+ OUTPUT
51110
300110
INPUT
2110
>-JVli'v-+--<
l-+-.....-+ OUTPUT
INPUT
>---''N\,---<
-1SV
NOTES:
1. Upper Threshold
NOTES:
=
[V+]
[
R RRS
J
(R1~~)+RS
R R
1 2
1. Rt = R +R
1
2
2. ±Threshold
R
= [±Supply] [R 1 +lR~
FIGURE 338. SINGLE SUPPLY
FIGURE 33A. DUAL SUPPLY
FIGURE 33. COMPARATORS (THRESHOLD DETECTORS) DUAL AND SINGLE SUPPLY TYPES
1Ng14
1.SMQ
117V
0.0111f
60Hz
FOR NTC SENSOR,INTERCHANGE POSITION OF SENSOR AND
(8).
NOTE: All Resistors are 112W.
FIGURE 34. TEMPERATURE CONTROLLER
10-22
CA3094, CA3094A, CA3094B
Typical Applications (Continued)
V+INPUT
(NOTE 1)
NOTES:
1. V+ Input Range = 19V to 30V for 15Voutput.
O.0056~F
2. V-Input Range = -lBV to -30V for -15V output.
3. Max lOUT = ±100mA.
4. Regulation:
Max Una '"
100n
l!.V
OUT
x 100 '" 0.075%/V
[V OUT (Initial) ll!.VIN
l!.V
Max. Load
OUT
VOUT(lnitial)
x 100 '" 0.075% V
OUT
(Il from lmA to 5OmA)
-15V REG.
OUTPUT
V-INPUT
(NOTE 2)
>--t-----'
10kO
±1%
FIGURE 35. DUAL VOLTAGE TRACKING REGULATOR
-
.
CIRCUIT TRIPS ON POSmVE
PEAKS WILL SWITCH WITHIN
36V
1mA
ILOAD
IABC
10""
3
1
1
1/1
i
llA
201lA
~
t
\
60 V
TYpmAL
l
R
47kO
(NOTE 3)
L
C
C2
~O.~F
= (N TE4)
""..".,
TERMINALS 3 AND 4
(ADJUSTABLE WITH
RlRIP)
GROUND FAULT
SIGNAL 60Hz
ceo
()~
WO
U.
NOTES:
1. Differential current sensor provides BOmV signal- 5mA of unbalance (Trip) current.
2. All Resistors are 112 Watt, ±10%.
3. RC selected for 3dB point at 200Hz.
6. Input impedance from 2 to 3 = 800kO.
0.001mF
(J)
..JZ
(J)~
4. Cz = AC by-pass.
5. Offset adj. included in RmIP'
1kW
.......
TERMINALS 2 AND 4
----- ---
o..z
CIRCUIT
BREAKER
CONTROL
SOLENOID
0.02~F
~'~'~ VOLTAGE BETWEEN
7. With no input signal Terminal 8 (output) at 36V.
FIGURE 36. GROUND FAULT INTERRUPTER (GFI) AND WAVEFORMS PERTINENT TO GROUND FAULT DETECTOR
10-23
CA3094, CA3094A, CA3094B
Typical Applications (Continued)
TREBLE
D1 • D4 1 NS3tl
STANCOR
NO. P·8600
OR EQUIVALENT
(120VACTO
26.8VCT AT lA)
3J111
tOPnONALTHERMAL
COMPENSAnON
NETWORK
"BOOSnOOkn
"CUT"
(CW)
(CCW)
10kn
JUMPER
BASS
TYPICAL PERFORMANCE DATA FOR 12W AUDIO AMPLIFIER CIRCUIT
Power Output (80 load, Tone Control set at "Aar)
Music (at 5% THD, regulated supply) ••••••••••••••••••• 15W
Continuous (at 0.2% IMD, 60Hz and 2kHz
mixed in a 4:1 ratio, unregulated supply)
See Figure 8 in AN6048 ••.•••••••••.•.•••••••••••••• 12W
Total Harmonic Distortion
At lW, unregulated supply •..••••••••••••••.••••••• 0.05%
At l2W, unregulated supply ....••..•••••.•..••••••• 0.57%
Voltage Gain .••••••.•••••••••••••••.••••••••••••••• 4OdB
Hum and Noise (below continuous power output) ••••••••••• 83dB
Input Resistance ••••••••••••••••••••••••••••••••••• 25OkO
Tone Control Range •.•.•••••••••••••• See Figure 9 in AN6048
FIGURE 37. 12W AUDIO AMPLIFIER CIRCUIT FEATURING TRUE COMPLEMENTARY SYMMETRY OUTPUT STAGE WITH CA3094
IN DRIVER STAGE
10·24
CA3165
Electronic Switching Circuit
April 1994
Features
Description
• Switching Initiated by Damping of Internal Oscillator
The CA3165 is a single chip electronic switching circuit
intended primarily for ignition applications. It includes an
oscillator that is amplitude-modulated by the rotor teeth of a
distributor, a detector that develops the positive going modulation envelope, a Schmitt trigger that eliminates switching
uncertainties. Both types include two complementary high
current switched outputs for driving power transistors requiring up to 120mA. The CA3165E also includes two complementary low current outputs that incorporate internal current
limiting and a non-inverting output amplifier with uncommitted input capable of switching 27mA.
• Proximity Sensing of Rotational Motion
• Repeatable Timing of Switching States
• Five Outputs - Two Complementary Pairs and One
Non-Inverting Output CA3165E1
• TWo Outputs - One Complementary Pair CA3165E
Ordering Information
PART
NUMBER
TEMPERATURE
PACKAGE
CA3165E
-4(J0C to +85"C
8 Lead Plastic DIP
CA3165E1
-4Q°C to +85°C
14 Lead Plastic DIP
The CA3165 is supplied in the 8 lead dual-in-line plastic
package (E suffix) and in the 14 lead dual-in-line plastiC
package (E1 suffix).
Pinouts
08
CA3165 (PDIP)
TOP VIEW
OSCFB
SENSE
GND
OUTPUT
3
CA3165 (PDIP)
TOP VIEW
r--v--
OSCFB
FB_RF
v+
U
11
GND Ii
SENSE
DET OUT
OUTPUT
INY_OUT
[!
INY_OUT
Ii
Ii
-SIGNAL
[1
+SIGNAL
~ NC
~
FB_RF
~ v+
Ii11 NC
~
DET_OUT
~ AMPL.JN
~ AMPL..OUT
C/)
-'Z
ceo
OJ::
w(,)
o..Z
C/):)
U.
CAUTION: These devices are sensillve to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporalion 1992
.
10-25
File Number
1278.2
CA3165
Functional Block Diagrams
DC SUPPLY 5V • 24V
2000
8470
FEEDBACK
RESISTOR
(6kn±O.5%)
13
OSCILLATOR
1
~
L" 100~H
a-53
OSCILLATOR
CONDITION
SWITCHING
10
2
1500
pF
=
O~T
OUTPUT
SCHMITT
TRIGGER
DET
•
.1-_. . .
OUTPUT
•
7
..::t. 0.01
REPRES;NTS
ROTOR LOADING
TERMINAL 10
TERMINAL 4
TERMINALS
TERMINAL 6
TERMINAL 7
Unloaded
Low
High
High
Low
Low
TERMINAL 8
Low
Loaded
High
Low
Low
High
High
High
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM FOR CA316SE1
DC SUPPLY 5V • 24V
200Q
2200
TO POWER
TRANSISTORS
3000
4
FEEDBACK
RESISTOR
INVERTED
OUTPUT
(6.49kn)
R~l
t
150:
..::t. 0.01
REPRES;NTS
ROTOR LOADING
pF
tVALUES OF RA AND Ra DETERMINED
BY CORRELATION.
OSCILLATOR
CONDITION
TERMINAL 4
TERMINALS
Unloaded
High
High
Low
Loaded
Low
Low
High
TERMINAL 6
FIGURE 2. FUNCnONAL BLOCK DIAGRAM FOR CA3165E
10·26
Specifications CA3165
Absolute Maximum Ratings
Thermal Information
DC Voltage (With Reference to Terminal 3)
CA3165E1
Terminals 4, 6, 8 ................................. 24V
Terminals 5, 7,12 .••...........•.•......•.••.•••• 18V
Terminal 9 ...................................... 1.5V
CA3165E
Terminals 4, 5 ................................... 24V
Terminal 7 ..•.....•..•..•.•..•..••...•••.•••••.• 18V
Current (At Terminals Indicated)
CA3165El
Terminals 4, 6 .....•...•.........••••....•...•. 120rnA
Terminals 5, 7 ......................... -0.1 rnA to 0.1 rnA
Terminal 8 •••.••.••....•.....••••..••.•.•••.•.• 30rnA
CA3165E
Terminals 4,5 •••.•..•.•••••••••..•.••••••••..• 120rnA
Thermal Resistance
9JA
Plastic DIP Package 8 Lead .............. . • • • • •• 15r:i'CIW
Plastic DIP Package 14 Lead •••••.....•....••..• 100000CIW
Operating Temperature Range .•••.••.••..•.•.. -4r:i'C to +85°C
Storage Temperature Range •••.•••••••••••••• -65OC to + 15r:f'C
Lead Temperature ................................. +265°C
At Distance 1/16" ±1132" (1.59 ±O.79mm) from Case
for lOs Maximum
Device Dissipation Plastic DIP Package 8 Lead
Up to TA = +550 C ................................ 600mW
Above TA = +55OC •••••••..•••. Derate Linearly at 6.67mWf'C
Device DiSSipation Plastic 01 P Package 14 Lead
Up to TA = +55°C ................................ 950mW
Above T" = +55°C ••••••••••••• , .Derate Linearly at 10mWf'C
CAUTION: Stresses above those listed In "Absolute Maximum RaUngs" may cause permanent damage to /he dallic9. This Is a stress only rating and operation
of ths devics at /hess or any othsr conditions abo... those Indica/ed In /he operational secUons of this specification Is no/ implied.
Electrical Specifications
At T"
=+25°C, V+ =13V, Measured In the circuit of Figure 5 (CA3165El) or Figure 6 (CA3165E)
CA3165El
PARAMETERS
SYMBOL
Input Current at Term. (Note 1)
A
Output Voltage at Term. 4
V.
CA3165E
MIN
TVP
MAX
MIN
TVP
MAX
18.4
-
Dwell
12.8
-
-
18.4
Spark
-
-
Spark
-
-
0.5
TEST CONDITIONS
Dwell
17.5
0.9
-
-
-
12.8
Output Volatge at Term. 7
V7
Dwell
-
Output Voltage at Term. 8
Va
Dwell
-
-
1.2
-
-
-
4.4
-
0.6
-
-
Portion of Spark
OSCillator Voltage at Term. 2
V2
-
Dwell
Spark
NOTE:
1. CA3165E atTerm. 7
CA3165El at Term. 12
17.5
I
4.4
0.6
0.5
-
-
UNITS
rnA
rnA
V
V
V
V
V
Vp-p
Vp-p
A
17
112
I/)
..JZ
~~~~~~L
OSCILLATOR
5
r:~~::r;::::::::~r-r-f1~~~~~t-------~19 gS~~n?LAM~
BRAKE INPUT 12
SPEED 8
SENSOR INPUT
Vs 11
A"";"'---!2,o
CONTROL AMP. (+)
"""-I1----(1R)
CONTROL AMP. (0)
> - - - - { 1 6 V ERROR
Vs
ANALOG TO
DIGITAL TO
ANALOG
CONVERTER
Viol
"A"
ACCELERATE
CAPACITOR
VMEMORY
ceo
6
AUGN
CURRENT
SENSE
r./)
..... Z
Viol
@AUGN
OJ::
WO
C.Z
7
r./):I
u..
10-33
CA3228
FIGURE 1. SPEED CONTROL FLOW CHART
10-34
CA3228
V30N
t
ON
···.-----------f..
· .
··
Vee
MOMENTARY
CONTACT
DRIVER
COMMAND
SWITCHES
,
~------~. SEEF~URE3:
51 0 ",
R3,2.2K
I-....;.,:~--~.-*----------~
52
RESUME
R4,680
Vee
-
53
SETfACCEL
o.oOlflF
UK
R5,120
54
COAST
10K
7
0.0471'F
8
10K
g
55
OFF
10
-
11
2.21'F
12
10K
51K
BRAKEUGHT
r-~I--"'" BRAKE SWITCH
SPEED INPUT
FREQUENCY, Is
2.22 HzlMPH
I
ALL RESISTANCE VALUES ARE IN OHMS
SWITCH
FUNCTION
VOLTAGE AT TERM. 3
RATIO TO Vee
MIN
VBRAKE
MAX
1.12
SI·0N
S6
S2- RESUME
0.725
0.8
S3-ACCEL
0.482
0.599
S4-COAST
0.148
0.272
o
0.094
0.93
0.96
S5-0FF
IDLE (Nole 1)
NOTE: 1. All Switches Open
FIGURE 2. TYPICAL AUTOMOTIVE SPEED CONTROL APPLICATION
0.221'F
.a.2V
~""""---t----..t--I
I.2K
1--1P'-- +14.4V
I.2K
Vee VACI-......--+i+-~
VENT
1-----.....+-1--1::'..
CA3228E
(SEE FIGURE 2)
!J)
...JZ
u.
SYSTEM MODE
ACCEL
CRUISE
COAST
VAC
Open
NC(Note 1)
NC
VENT
Close
Close (Note 1)
NC
VALVE
~----
POSITON
FEED BACK
(OPTIONAL
to PIN 20)
NOTE:
1. Open or Closed as Required to Maintain Set Speed Error
TOTHROTILE
ACCEL
CRUISE
COAST
BRAKE
REDUNDANT BRAKE
HI-SPEED DROPOUT
LD-SPEED DROPOUT
L
L
L
L
L
L
VENT (Pin 21)
H
H
H
L
L
L
L
L
GATE (pin 23)
L
L
L
H
H
H
H
VAC (Pin22)
FIGURE 3. SOLENOID DRIVERS AND SERVO VACUUM CONTROL MECHANISM TYPICAL APPLICATION
10-35
CA3228
Device Description and Operation
Memory Voltage, VM (Pin 6)
The functional block diagram and Figures 1. 2 show the
speed- control flow chart. and a typical automotive speedcontrol application. respectively.
Command Decoder and Delay logics (Pins 3,4)
Driver commands are input to pin 3 through the Driver
Command Line. These signals are encoded on a single line
as voltage levels selected by switches which adjust a resistor
divider network.
The voltage level established is compared to a reference
level which decodes the command. A command level greater
than Vcc + 0.8V turns the system On, enabling dynamic
control. Once the system is enabled. a voltage level of
0.88Vee• 0.66Vee• and 0.38Vee decodes the RESUME.
ACCEL. and COAST command. respectively. A driver
command of O.12Vcc or less turns the system Off.
The Driver Command Delay established by the current
sources and a capacitor at pin 4 assures that ON. OFF,
ACCEL. and COAST commands are considered valid only if
longer than 50ms. The time for RESUME is 330ms.
Upon release of the ACCEL or COAST switches the voltage.
representing vehicle speed Vs determined by the output
from the frequency-te-voltage converter. is stored as a
binary number in a 9 bit counter. A memory update comparator allows clocking of the counter until memory voltage VM
equals Vs. The output of the counter controls a ladder
network which provides memory voltage VM at pin 6.
Analog Accelerate and Resume Generator (Pins 14,15)
Numerous functions are combined in what is called the
Analog Accelerate and Resume Generator. The circuit
switches the signal output at pin 15 depending on the mode
of operation. In the Accelerate and Resume mode the
capacitor at pin 15 is charged at a fixed rate [450mVl(Roo)
(Coo)). In the Cruise mode pin 15 follows the memory
voltage (VM) and in the On. Off. Brake. Redundant Brake.
Minimum Speed Lockout. and Coast modes. pin 15 follows
the voltage representing vehicle speed (Vs).
I
I
-400C ~ :--
+wc
Control Logic
~
The Control Logic accepts signals from the command
decoder and other sensors. It causes the memory to be
updated when operating in ACCEL and COAST modes. It
will put the system in Standby mode if brakes are applied. if
the speed error exceeds 11 mph. or if the vehicle speed
drops below the minimum Speed Lockout (25mph). It will
return the vehicle to the previous set memory speed when a
RESUME command is given.
Frequency to Voltage Converter (Pins 8-11)
The speed sensor input fs at pin 8 is an AC signal whose
frequency is directly proportional to the vehicle speed at
approximately 2.22Hz/mph The current sources, capacitor
and comparators at pin 9 cause equal rise and fall times to
occur at pin 9 on the positive- and negative-going slopes of
the sensor input. Pulse currents of time duration equal to the
rise and fall times are used to charge the parallel resistor
capacilor combinalion at pin 10 to give a voltage (Vs) at pin
10 proportional to frequency at approximately 27mVlHz. The
fs frequency range may be altered by changing the values of
the filter capacitors at pins 8 and 9. However. the maximumto-minimum frequency ratio will remain fixed.
I
6
I
+2~C-
5
4
~
3
[...yl\
~
+8SOC
l.;'
2
o
t=:: f-
-400 C
10'"
o
50
100
150
200
FREQUENCY. Is (Hz)
FIGURE 4. TYPICAL DlA MEMORY VOLTAGE, Vu vs
FREQUENCY
~~
-, ~
o0
'f'
~
~'\
+8SOC
~
-400C
50
100
150
200
FREQUENCY. Is (Hz)
250
FIGURE 5. TYPICAL CHARACTERISTIC FN CONVERTER
OUTPU~VsvsFREQUENCY
Error Amplifier (Pin 16)
In the Cruise mode the Error Amplifier determines the
difference between the set memory speed (VM) and the
actual speed (Vs). This error signal is fed to the control
amplifier where it defines whether VAC or VENT is required.
The error signal represents deviation in vehicle speed from
the memory or set speed condition. The Error signal Is also
used to control the Redundant Brake feature.
Redundant Brake Comparator
When the error output drops below approximately O.42Vcc.
the Redundant Brake output Is activated. Redundant Brake
causes the chip to go into the Standby mode.
Control Amplifier (Pins 18, 20)
The Control Amplifier is an op amp using external
components to set the gain. Inputs to the Control Amplifier
are from the Error Amplifier output. servo position sensor
and align output. The output of the Control Amplifier controls
the VAC and VENT outputs.
VAC, VeNT and Gate-Driver Outputs (Pins 21, 22, 23)
The VAC, VENT and Gate Outputs are open collector
devices used to control the throttle poSition. For the system
to be able to supply vacuum. the gate output must be low. If
10-36
CA3228
the output from the Control Amplifier exceeds 0.573Vce,
vacuum is supplied to the servo unit. If the output of the
Control Amplifier is between 0.573Vce and 0.427Vce the
vacuum is held in the servo unit and vehicle speed is
maintained. If the output from the Control Amplifier drops
below 0.427Vce or if the gate output is high, the servo unit
vacuum is vented.
Activation of the RESUME switch causes a fixed acceleration rate from the lower speed until the capacitor voltage at
pin 15 is equal to the VM voltage. A filter circuit contained in
the output of the resume comparator insures that noise
doesn't reset the comparator until Vp1N actually equals V M•
Align Voltage Source (Pin 17)
The Align Voltage Source is a Xl buffer with an output of
0.5Vce·
Overspeed Detector Comparator
The Overspeed Detector circuit is used when the following
sequence of events occur: A speed is set in memory, the
vehicle is manually accelerated (foot pedal) to a higher
speed and then the ACCEL switch is activated.
During vehicle acceleration Vs voltage is greater than the VM
voltage into the memory update comparator. When the
ACCEL command is given, the capacitor at pin 15 rapidly
charges to within 60mV of Vs before switching the comparator output low and starting the fixed acceleration rate from
the present vehicle speed. The 60mV of offset is required to
insure that the output of the overspeed detector is low under
normal operating conditions. Hysteresis is also designed into
the comparator to eliminate noise problems which may
prevent the chip from going into the Acceleration mode.
End of Resume Comparator
The Resume Comparator is used when the following
sequence of events occurs: A speed is set in memory, the
brake applied, causing the vehicle to go to a lower speed,
and the RESUME switch is activated.
Brake Input Comparator (Pin 12)
When the Brake Input exceeds 0.55Vce, the chip will go into
the Standby mode from Cruise.
Minimum Speed Lockout
Assures that the system remains In a Standby mode if
vehicle speed Vs is below 0.183Vce. It causes the system to
revert to the Standby mode if Vs drops below 0.183Vce in
the Cruise mode.
Digital Filter for Redundant Brake and Minimum Speed
Lockout
A 4 bit shift register with an all '1 's output decode is used to
filter transients and electromagnetic interference. The filter
prevents false Signals from putting the system into Standby
from Cruise.
Ramp Oscillator (Pin 5)
The Ramp OSCillator at pin 5 nominally varies between
amplitudes of 4.1V and S.1V. The discharge rate is
approximately 4X the charge rate. With a capacitor of
O.OOl~F on pin 5, the nominal oscillator frequency is 50kHz.
t/)
...JZ
",,0
O~
w(,)
n.Z
t/);:)
u..
10-37
CA3228
3
DVR
CMD
A
RESUME
ONIOFF
Q4
ON ACTIVE HIGH
REDUNDANT
BRAKE
D
1146 ALL
COMMAND
DELAY
TIME GEN.
1'8
DE·
CODE
~::1!~t-~AC~C~E~L-1C:~~:::+
L-__________________~----~~~r_~-6-'S
COAST
FIGURE 6. FUNCTIONAL BLOCK DIAGRAM FOR SPEED CONTROL (Continued On Next Page)
10·38
____~E
AID
VII
A
f
Q276
V
i
LCYI:L::Jn'r'1
I
;nYM~===!:====~l1lll
'T
f:"b'~"
osc
...
B
I
~
\' --'!
15
c
:ll
m
!"
C
...
c
z
0
5
z
)00
raJ
r-
0
0
o
"
c
:;
~
'?
~
C)
:ll
)00
...;;:0
*ty.
:ll
III
~ ER
"U
m
m
c
0
~
-i
:ll
0
r-
()
0
~
III
G
I
a
:l
c
CD
.s
-=-
-:J
I
I
~
III ~~~L
II
-q.,
II
Vee 12 AcnVE ACCEL ClAMP
H
Vee
2
">-+-V
••
0271
SPECIAL
FUNCTIONS
I
II
~AUGN
CA3274
~HARRlS
~
SEMICONDUCTOR
Current Limiting Power Switch
with Current Limiter Sense Flag
April 1994
Features
Description
• Drive-Current Limiting at Output
The CA:32741s a controlled current switch and may be used in
general purpose switching applications that require specified
maximum levels of current. The functional block diagram of
the CA:3274 is shown and a typical application circuit is shown
in Figure 1. All intemal emitter follower has 200mA of source
drive output capability. The Control Input is a Schmitt trigger
buffer amplifier for noise immunity in the environments typical
of industrial and automotive control systems.
• Current-Sense Buffer and Reference
• 200mA Driver Current Capability
• Logic-level Control Input
• Current Limiting Flag Output
• SOdB Minimum PSRR
Current sensing in the emitter circuit of a power-darlington
output stage is fed back from a sampling resistor to the sense
input of the CA3274 which has a 335mV typical offset. For the
example shown in FlQure 1, a sampling resistor of 0.0560
permits 6.0A (0.33510.056) of current in the emitter of the output
driver. When the current limiter is activated, the flag output
changes state conditionally. If the control input is the "(1' state,
the flag output will remain in a "1" state. If the control input is in
the "1" state and the sense input is less than the voltage
reference level of 335mV, the flag output will remain in the "1"
state. If the control input is the "1" state and the sense input is
equal to or greater than the 335mV reference level, the flag
output goes to the "(1' state. The output flag switch may be used
to accurately establish dwell timing in automotive applications.
When the control input goes to "(1', the flag is reset to "1". Noiseimmunity holcl-off is used to prevent pre-triggering of the flag
output and is noted as to in the timing diagram of Figure 2.
• SIlS Typical Switch Time
• Separate Signal and Power Grounds
Applications
• Solenoid Switch Driver
• Relay Driver
• Lamp Control Switch
• Ignition Coli Pre-Driver
• Constant Current Driver
• Current Limiting Switch
• Fault Output Sense Appliance
• Power Supply Fault Mode Control
Ordering Information
PART NUMBER
CA3274E
TEMPERATURE
RANGE
-40°C to +85°C
PACKAGE
8 Lead Plastic DIP
The flag output may be used for diagnostic feedback via the
current sense input to detect a fault mode. In this case the
sampled drive current is either from the emitter of the CA:3274
intemal power transistor or an extemal output amplifier, such as
a darlington power transistor or power-FET output stage. The
CA3274 has separate power and signal grounds to minimize
transient-loop feedback to the input ground and thus prevent
false triggering of the output. Optionally, the output from the
CA:3274 may be taken from the open collector (DRIVE IN) at
pin 6. An extemal resistor at pin 6 may be used to set the level
at which 02 will saturate, providing additional limiting protection
for the maximum forward-drive from the CA3274.
Pinout
CA3274 (PDIP)
TOP VIEW
SENSE IN
8
VccSUPPLY
7
CONTROL IN
5
DRIVEOUT
POWERGND
SIGNALGND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
10-40
File Number
2222.2
CA3274
Block Diagram
Vee
8
RELAY OR
SOLENOID LOAD
D1
CONTROL
IN
R3
R2
FLAG
.. SENSE
t----+-~v...--
OUT
SIGNAL
GROUND
R1
~
-
POWER
GROUND
Vcc
VCC1
CONTROL
IN
o
..JZ
0(0
<:)j:::
wo
D.Z
0;:)
II.
FLAG
OUT
SIGNAL
GROUND
~
-
POWER
GROUND
- -=dA
SENSE LEVEL EQUALS
FIGURE 1. TYPICAL APPLICATION AS A POWER SWITCH PRE·DRIVER SWITCH
10·41
Specifications CA3274
Absolute Maximum Ratings
Thermal Information
Operating Drive Supply, Vee ........................... l6V
Maximum Output Current, 10 ••••••••••••••••••••••••• 200mA
Control, Sense Input................... Gnd - 0.5V, Vee + 0.5V
Signal, Power Differential Ground Voltage ..................• tW
Thermal Resistance
9JA
Plastic DIP Package 8 Lead .••••. • • • • • • • • • • • • • •• 13fi>CNi
Power Dissipation, Po
Up to 70"0 ..................................... 630mW
Above 70"0 •••••••••••••.•••... Derate linearly at 7.7mWf'C
Operating Temperature Range ••••••••••..••••• -4fi>C to +85°C
Storage Temperature Range ...••.••••••.•.••. -55°C to +loooC
Lead Temperature (During Soldering)
At distance 1/16in. (1.59mm t 0.79mm) from
case for lOs Max................................ +265°C
CAUTION: Stresses above those listed in "Absolute Maxinwm RaYngs" may cause permenent dsmege to the dsvice. This is a stress only rating and operation
of the device at these or any other conditions above those indicatad in the operational sections of this specificaYon is not impHed.
Electrical Specifications
PARAMETERS
Power Supply Current: Sl
At TA =-4fi>C to +650 C, Unless Otherwise Specified
SYMBOL
=2
Control Input: S1 =3
=2
Flag Output High: Sl =3
Flag Output Low: Sl
Prop. Delay: Sl
=1
Power Supply Rejection Ratio
UNITS
25
mA
5
mA
3.5
V
-
V
lecl
Control =Low (Output Off)
-
VTHOH
Thd. Voltage, High
-
VTHOl
Thd. Voltage, Low
0.9
-
Hysteresis
0.4
0.65
2.0
V
Leakage, 0.0 to 5.5V
-20
+20
IIA
-
-
0.5
V
=200mA,
VSAT
Output Saturation Voltage, lecl
VCONTROL =High
ILEAK
Collector Output Leakage. VCONTROl =
Low
-
-
100
IIA
VFSAT
VSENSE =Hlgh,IFLAG =3mA
V
Output Leakage, Vec
-
0.8
VFlEAK
10
IIA
IoN,IoFF
Control In to Drive Out
-
5
Drive Off to Flag Off
-
10
-
150
-
600
lIS
VSENTHO
310
335
360
mV
PSSR
50
-
-
dB
10
=1
MAX
-
"'LAG
Sense Input Thd. Level: Sl
TYP
Control =High (Output On)
IlL
=3
MIN
IccH
VTHOH"VTHOl
Driver In, Out (Pin 6, 5): Sl
TEST CONDITIONS
=VFLAG =10V
Flag Delay from Control In
NOTES:
1. Refer to Figure 3 Test Diagram for electrical test connections.
2. Refer to Figure 2 TIming Diagram for logic switching and prop delay.
3. Unless otherwise specified: Vec =VCC1 =VCC2 =7V to 10V;
VSENSE = "Low"; VCONTROL = "Low";
Control in levels are defined as "Low" equals O.OV and "High" equals 5.0V.
10-42
lIS
lIS
CA3274
tRISE
:
:
tFAU.
~~~
___-..."k
_ . . ry
...
0-
______________
!DE~Y
; ..
!oFF
~CO~N~T~R~O~L~IN~'P~I~N~7
__
.. '
DELAY~.: ~__________~______
i\..
DRIVE OUT· PIN 5
CURRENT
~I~.""'------OC-------...;-S
....
YSTEM
NOISE
3.35mV
SENSE
ON TIME
i
+--------- ~
:
I~A-: ~~~i:~------------------------~------------~""
----!!-NW--
i-tSENSE
-I
:
:
1 ..
(NOISE HOLD-OFF
DELAY)
.. 1
to (SEE NOTE) .
OUTPUT
LOAD CURRENT
I" . ._________________+ ________
..J
"'"
: ..
Y::.',.______F.LA.G
__O.U.T••P.IN
__
1_
,.Ii1
tFLAG
NOTE: For Vee = 7V to 10V; 10 (MAX) = 60DllS, If Control In = High,
Sense In = High; Pin I, Flag Out ean go low only if !seNSE ~ 10
SENSE IN • PIN 2
.. :
DELAY
FIGURE 2. CA3274 TIMING DIAGRAM
OUTPUT LOAD
POWER SUPPLY
+VCCl
POWER SUPPLY
+Vee
~""'
~
..' .....' ..........................'
8
.................................
""......... , ........... ,
!, 6 IN
~
IN VCONTROL
•
7 '
,
CONTROL
LOGIC
510
(ADJ. FOR 200mA
IN VSAT TEST)
tJ)
~ DRIVER
.JZ
, 5
II.
F~~o-_~..,
120
SIGNAL
GROUND
VSENSE
~
-
POWER
GROUND
FIGURE 3. CA3274 TEST CIRCUIT
10·43
=
HIP9010
Engine Knock Signal Processor
April 1994
Features
Description
• Two Sensor Inputs
The HIP9010 is used to provide a method of detecting premature detonation or "Knock" in automotive engines.
• Microprocessor Programmable
A block diagram of this Ie is shown in Figure 1. The chip
alternately selects one of the two sensors mounted on the
engine block. Two programmable bandpass filters process
the signal from both sensors, and divides the signal into two
channels. When the engine is not knocking, programmable
gain adjust stages are set to ensure that both the reference
channel and the knock channel contain similar energies.
This technique ensures that the detection system is comparatively immune to changes in the engine background noise
level. When the engine is knocking, the energy in the knock
channel increases.
• Accurate Filter Elements
• Digitally Programmable Gain
• Digitally Programmable Time Constants
• Stable Analog Filter Characteristics
• On-Chip Clock
• Operating Temperature Range -40°C to +12SoC
Applications
• Engine Knock Detector Processor
• Analog Signal Processing where Controllable Riter
Characteristics are Required
An active, full wave rectifier detects energy in each channel.
During integration, the energy from the reference channel is
subtracted from the energy in the knock channel. The result
is an analog voltage, whose output level is proportional to
the engine knock.
The chip is under microprocessor control via an SPI interface bus.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
HIP9010AB
-40°C to +125°C
20 Lead Plastic SOIC (W)
Pinout
HIP9010 (SOIC)
TOP VIEW
SOIN
1
VMIO
SOFB
3
INOUT
INTJiiO[!S 7
a.
OSCOUT 1
CAUTION: These devices are sensttive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright L
r--.....
(1t)SOFB
(20) 80IN
r~
~
~
+
PROGRAMMABLE
BANDPASS
FILTER
140kHz
14 STEPS
I---t
PROGRAMMABLE
GAIN
STAGE
1-0.133
14 STEPS
H
ACTIVE
FULL WAVE
RECTIFIER
I
1-_--,
~
...-
i
(18)
~
sm
(17)S1IN
~ L..... c!II
=I m ' - ' l: g
~ :;;
zi
~ §
;
+
I------....
POWER SUPPLY
BANDPASS
FILTER
140kHz
14 STEPS
....._ - - . . . ,
PROGRAMMABLE
INTEQRATDR
40-600....
i ~ .......-...
" - L..t
I
.~
---.
STAGE
GAIN
1-0.133
14 STEPS
-t
ACnvE
FULL WAVE
RECTIFIER
REGISTERS
AND
STATE MACHINE
.1
(14) TEST1
FIGURE 1. SIMPUFIED BLOCK DIAGRAM OF THIE HIP9010
SPECIAL
FUNCTIONS
OSClN(9)
----+
1
r:-..
V'--"
i'r-;'
SCI( 1131
CS(8)
SPI
INTERSPACE
Q
Q
OSCOUT(10)
TDSWlTCHED
CAPACITOR _ .....
BIAS CIRCUITS
KNOCK FREQUENCY CHANNEL
I
CLOCK
NETWORKS
(3) V..D (1) VDD (2) ONC
=s
;g
. . . . . . . . . . . . . . 3 2 STEPS
AND
i....--
INOUT (4)
SlNGLE-ENDED
CONVERTER
AND QUTPUT
DRIVER
MOSI (12)
__
"50(11)
INTIHOLD (7)
Specifications HIP9010
Absolute Maximum Ratings
Thermal Information
DC Logic Supply, Voo. • • • • • . • • • • • • • • • • . • • • • •• -0.5V to +7.OV
Output Voltage, Vo • • • • • • • • • • • • • • • • • • • • • • • • •• -0.5V to +7.OV
Input Voltage, VIN . . • • • • • • • • • • • • • • • • • • • • • • . • • • • •• +7V Max.
Thermal Resistance
9JA
Plastic SOIC Package. • • • • • • • • • • • • • • • • • • • • • • • •• 12fi'CNJ
Power Dissipation, Po
For T" = -400 C to +700 C ••••••••••••••••••••• 450mW Max.
ForT" = +700 C to +1250 C •••••••• Derate Linearly at 8.3mWI'C
Operating Temperature Range. • • • • • • • • • • • • •• -4000 to +125°C
Storage Temperature Range, TSTG •••.••••..• -6500 to +l50oC
Lead Temperature (During Soldering) •••••.•••.•••••••• +265°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to 1M dsvice. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in 1M operational sections of this specification Is not ImpUed.
Electrical Specifications voo = 5V, ±5%, GND = OV, Clock Frequency 4MHz, ±O.5%, T" = -4fi'C to +1250 C,
Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3
7.5
12
mA
DC ELECTRICAL CHARACTERISTICS
Quiescent Supply Current
100
Voo = 5.25V, GND = OV
Midpoint Voltage, Pin 3
VMIO
Voo = 5.0V, IL = 2mA Source
2.3
2.45
2.55
V
Midpoint Voltage, Pin 3
VMIO
Voo = 5.0V, IL = OmA
2.4
2.5
2.6
V
Input Leakage, Pin 14
ILlnT
Voo= 5.0V
Inlernal Pull-Up Resistor, Pin 14
Rim
Leakage of Pins 7, 8,12 and 13
IL
Low Input Voltage, Pins 7,8,12 and 13
VIL
High Input Voltage, Pins 7, 8,12 and 13
VIH
Measured at GND and Voo = 5V
-
-
3
IIA
30
100
200
KO
-
±3
IIA
-
-
30
%of
Voo
70
-
-
%of
Voo
Low Level Output, Pinll
VOL
ISOURCE = 4mA
0.01
-
0.30
V
High Level Output, Pinll
VOH
10011A
5.4
5.5
6.0
V
-
-
10
IIA
1.5
V
-
V
Leakage Pin 11
IL
Measured at GND and Voo = 5V
Low Level Output, Pin 10
VOL
ISOURCE = 5OO11A
High Level Output, Pin 10
VOH
ISINK = -8ool1A
4.4
-
INPUT AMPLIFIERS
SOFB and SI FB High Output Voltage
VouTHI
10011A ISINK
4.7
4.9
-
V
SOFB and SI FB Low Output Voltage
VouTLO
10011A ISINK
200
mV
-
15
SOFB and SI FB Closed Loop Gain -26dB
AcL
Input Resistor = 1Mo, Feedback
Resistor = 50KO, -26dB
-25
-26
-27
dB
SOFB and SI FB Closed Loop Gain 20dB
AcL
Input Resistor = 47.5MO, Feedback Resistor = 475Kn. 20dB
18
20
21
dB
BW
Test Mode, 70mVRMS Input to
SOFB or SI FB, Output Pin 4
-
-2
-
dB
ATEN
Test Mode, 70mVRMS Input to
SOFB or SIFB, Output Pin 4
-10
-15
-
dB
ANTIALIASING FILTER
Response 1kHz to 20kHz,
Referenced to 1kHz
Attenuation at 180kHz
Referenced to 1kHz
10-46
Specifications HIP9010
Electrical Specifications voo = 5V, ±5%, GND = OV, Clock Frequency 4MHz, to.5%, T" = -4O"C to +125°C,
Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOUTP•p
Test Mode, 330mVRMS, 1.22kHz
Input SOFB or S1 FB, Output Pin 4
3.0
3.5
·
Vp.p
a
Test Mode, 7OmVRMS , 1.22kHz to
19.98kHz, Input SOFB or Sl FB
Output Pin 4
·
2.5
·
Q
VN01SE
Test Mode, RMS Metering BW
50Hz to 200kHz, Open Input to
SOFB or S1 FB, Output Pin 4
·
0.4
1
mVRMS
%G
Test Mode, 1Vp.p Input SOFB or
S1FB, Output Pin 4
·
±5
·
%
Test Mode, 25mVRMS, TC = 6oo11S
Gain = 0.5,l.22kHz to 19.98kHz
·
.
±30
mV
520
590
660
mV
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output
a
Filters at 20% of Center
Frequency (Note 1)
Output Noise, Clock ON
PROGRAMMABLE GAIN AMPUFIERS
Percent Amplifier Gain Deviation
Per Table 1
INTEGRATOR
Integrator Offset VoHage
INTGV10
Integrator Reset Voltage
VRESET
Pin 4 Voltage at Initiation of
Integration Cycle
Integrator Droop after 5OO11S
VOROOP
Test Mode
·
±1
±3
mV
Differential to Single Ended
Converter Offset Voltage
DIFVIO
Pin 3 to 4, SOFB and Sl FB
Pins Open
·5
5
15
mV
Change in Converter Output
DIFOUT
Test Mode, 5OOmA, Sinking Load
to No Load
·
±1
±3
mV
DIFFERENTIAL CONVERTER
NOTE:
1. Q = folbBW, Where: fo
=Center Frequency, BW =3dB bandwidth.
HIPe010
C3, O.022I'F
MOSI~-------------,
C2,3.3nF
/
MiSci
~. '~.3""Vn~'VIr-"""_-I
n"...""'.. ~~
SCK
(f)
SPI BUS
Cs
~
INTIiiOL6 ~-------------,
..JZ
>-_-
' PIN 20 ~
VMlD~
PIN 18
1
1.....
t :;:>....-:-PIN 18
' PIN 17
VMID~
FIGURE 3, INPUT AMPLIFIER CONNECTIONS
A mid-voltage level is generated by the IC. This level is set to
be half way between Voo and ground. Throughout the IC this
level is used as a quiet, DC reference for the circuits within
the iC. This point is brought out for several reasons: it can be
used as a reference voltage, and it must be bypassed to
ensure that it is a quiet reference for the internal circuitry.
The input amplifiers are designed with power down capability, which, when activated disables their bias circuit and their
output goes into a tri-state condition. This is very important
during the test mode, in which the output terminals of the
amplifiers are driven by the outside world with test signals,
Antlallaslng Riter
A basic approach to engine pre-detonation systems is to
only observe engine background during the time interval that
noise is expected and if detected, retard timing. This
approach does not require the sensitivity and selectivity that
is needed for a continuously adjustable solution. Enhanced
fuel economy and performance is obtainable when this IC is
coupled with a microprocessor controlled fuel management
system.
The IC has a 3rd order Butterworth filter with a -3dB point at
70kHz. Double poly-silicon capacitors and implanted resistors are used to set poles in the filter. This filter is required to
have no more than 1dB attenuation at 20kHz (highest frequency off interest) and a minimum attenuation of 10dB at
180kHz. This filter precedes the switch capacitor filters
which run at 200kHz.
Circuit Block Description
Two identical programmable filters are used to detect the two
frequencies of interest. The Knock Frequency Filter is programmed to pass the frequency component of the engine
knock. The Reference Frequency Filter is used to detect
background noise at a second programmed frequency, The
filter frequency is established by the characteristics of the
particular engine and transducer. By subtracting the energy
component of these two filters, we can detect if a knock has
occurred.
Input Amplifiers
Two amplifiers are used to interface to the two engine sensors. These amplifiers have a typical open loop gain of
100dB, with a typical bandwidth of 2.6MHz. The common
mode input voltage range extends to within 0.5V of either
supply rail. The amplifier output has a similar output range.
Programmable Band Pass Switched Capacitor Filters
Sufficient gain, bandwidth and output swing capability was
provided to ensure that the amplifiers can handle attenuation
gain settings of 20 to 1 or -26dB. This would be needed
when high peak output signals, in the range of 8V RMS , are
obtained from the transducer. Gain settings of 10 times can
also be needed when the transducers have output levels of
5mVRMS'
The filters have a nominal differential gain of 4. Their frequency is set by program words (discussed in the Communications Protocol section). Center frequencies can be
programmed from 1.22kHz to 19.98kHz, in 64 steps. The filter Q's are typically 2.4.
In a typical application the input signal frequency may vary
from DC to 20kHz. External capacitors are used to decouple
the IC from the sensor (C1 and C2). A typical value of the
capacitors is 3.3nF. Series input resistors, R1 and R2, are
The gains from the Knock Frequency Filter and the Reference Frequency Filter can be adjusted with respect to one
another, so that the difference energies in the two bands can
be compensated. This balance is achieved by feeding one of
Balance/Gain Adjust Stage
10-49
U)
..JZ
<0
of
w(,)
Il..Z
U)::)
U.
HIP9010
=
the filters unattenuated (gain 1) and attenuating the other.
This can be adjusted with 64 different gain settings. ranging
between 1 and 0.133. The signals can swing between 20
and 80 percent of VooProgramming is discussed in the Communications Protocol
section. The test!channel attenuate word is used to determine which of the two channels is attenuated and which is
set to unity gain.
Active Full Wave Rectifier
The output of the filters are independently full wave rectified
using switch capacitor techniques. Each of two rectifier circuits provide both negative and positive values for the knock
frequency and reference frequency filter outputs. The output
is able to swing from 20 to BO percent of Voo- Care was
taken to minimize the RMS variations from input to output of
this section.
Integrator Stage
The signals from the two rectifiers are summed and integrated together. A differential system is used to reduce
noise. One system integrates the positive energy of the
Knock Frequency Rectifier with respect to the positive
energy of the Reference Frequency Rectifier. The second
system does the integration of the negative energy value of
the two rectifiers. The positive and negative energy signals
are opposite phase signals. USing this technique reduces
system noise.
The integrator time constant is software programmable by
the Integrator Time Constant discussed in the Communications Protocol section. The time constant can be programmed from 40llS to 6oo1lS. with a total of 32 steps. If for
example. we program a time constant to 2oo1lS. then with
one volt difference between each channel. the output of the
integrator will change by 1 volt in 200j.1S.
When integration is enabled by the rising edge of the INTI
H5i]5 input. the output of the integrator will fall to 0.5V.
within 20llS after the integrate line reaches the integrate
state. The output of the integrator is an analog Voltage.
Test Multiplexer
This circuit receives the pOSitive and negative outputs from
the two integrators. together with the outputs from different
parts of the IC. The output is controlled by the fifth programming word of the communications protocol. This multiplexes
the switch capacitor filter output. the gain control output and
the antialiasing filter output.
Differential to Single-Ended Converter
This signal takes the output of the two integrators (through
the test-multiplexer circuit) and provides a Signal that is the
sum of the two signals. This technique is used to improve the
noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the
input amplifier used to interlace with the sensors. When the
output of the antialiasing filter is tested. this amplifier is in the
power down mode.
Communications Protocol
The multiprocessor talks to the knock sensor via an SPI bus
(MOSI). A chip select pin (CS) is used to enable the chip.
which. in conjunction with the SPI clock (SCK). moves in the
eight bit programming word. Five different programming words
are used to set gains. frequency response. integrator constants. test mode. channel select and test mode conditions.
With chip select (CS) going low. on the next rising edge of
the SPI clock (SCK). data is latched into the IC. The data is
shifted with the most significant bit first and least significant
bit last. Each word is divided into two parts: first the address
and then the value. Depending on the function being controlled. the address is 2 or 3 bits. and the value is either 5 or
6 bits long. During the hold mode of operation. all five programming words can be entered into the IC. but during the
integrate time any single byte may be entered but will not be
acted upon until the start of the next hold period. The integration or hold mode of operation is controlled by the INTI
HOLD input signal.
Programming Words
1. Reference Filter Frequency: Defines the center frequency
of the Reference Filter in the system. The first 2 bits are
used for the address and the last 6 bits are used for its
value. 01FFFFFF Example: 01001010 would be the reference filter (01 for the first two bits) at a center frequency
of 1.7BkHz (bit value in Table 2 of 10).
2. Knock Filter Frequency: Defines the center frequency of
the Knock Filter in the system. The first 2 bits are used for
the address and the last 6 bits are used for its value.
OOFFFFFf Example: 00100111 would be the knock filter
frequency (00 for the first two bits) at a center frequency
of 6.37kHz (bit value in Table 2 of 39).
3. Balance Control: Defines the ratio of the gain of the knock
band center frequency to that of the reference band center frequency. This role can be reversed by the value of
C... in the fifth programming bit. as explained in 5. Test!
Channel Select/Channel Attenuate Control. The first 2
bits are used for the address and the last 6 bits for its
value. 10GGGGGG Example: 10010100 would be the
balance control (10 for the first two bits) with an attenuation of 0.514 (bit value in Table 2 of 20.) Depending on the
value of C... in the fifth word this would apply to the reference or the knock gain section.
4. Integrator Time Constant: Defines the Integration Time
Constant for the system. The first 3 bits are used for the
address and the last 5 bits for the value. 110TTTTT
Example: 11000011 would be the integrator time constant (110 on for the first 3 bits) and an integration constant of 551ls (bit value of 3 in Table 2).
5. Test!Channel Select/Channel Attenuate Control: This
word serves several purposes. By looking at the structure. 111T...TBTcCsC.... the first 3 bits are used for the
address. and the last 5 bits are used for the value. The
options are:
10-50
HIP9010
If CS is "0" channel ·0" is selected. If CS is "1" channel
"1" is selected.
if
- If C A is "a' attenuation applies to the knock filter. If CA is
"1" attenuation applies to the reference filter.
- During the test mode (i'ESi" input is a low level), if TA is
"a' all sections get their input from the output of the
antialiasing filter input. This input can come from either
the output of channel "0" amplifier or channel "1" output
depending upon the state of the C s bit. If TA is "0" the
input amplifiers are powered down. If TA is set to "1"
during the test mode the chip is configured in its normal
operating state, getting inputs to all sections from previous sections.
Combinations of TA, T Band Teare used to test the different analog parts of the circuit. Table 1 shows these
combinations. All blocks except for the antialiasing filter
are sampled via the ditterential to single ended converter in the test mode.
1 "-J
TO NEXT STAGE
~
FIGURE 4A. SOIN AND S11N INPUT CIRCUIT
TABLE 1. SHOWING PROGRAMMING IN THE TEST MODE
TEST
PIN 14
TA
Ta
0
0
0
0
0
~
ANALOG OUTPUT
FROM:
Tc
CHS
0
0
0
Knock Rectifier
0
0
1
Reference
0
0
1
0
Knock Filter
0
0
0
1
1
Reference Filter
0
0
1
0
0
Antialias Filter( 1)
0
0
1
0
1
AntiaJias Filter( 1)
0
0
1
1
0
Integrator
0
0
1
1
1
Integrator
0
1
0
0
0
Knock Rectifier
0
1
0
0
1
Reference
0
1
0
1
0
Knock Filter
0
1
0
1
1
Reference Filler
0
1
1
0
0
Antialias Filter( 1)
0
1
1
0
1
Antialias Filter( 1)
HALF OF
DIFFERENTIAL
AMPUAER
JL.!.....I
--.J1-
FIGURE 4B. Mi§O OUTPUT OF SPI DATA BUS IS
AN OPEN DRAIN TRANSISTOR
TO LOGIC
+---.
FIGURE 4C. TEST PMOS TRANSISTOR HAS EQUIVALENT
CURRENT PULLUP CAPABILITY OF A SOk TO
200k RESISTOR
o
...JZ
0
1
1
1
0
Integralor
0(0
C~
0
1
1
1
1
Integrator
0;:)
1
x
x
x
x
Integralor
W(J
Q,Z
II..
NOTE:
1. All Test function blocks have their outputs buffered by the differential to single ended converter. Their outputs are aVailable at
the INTOUT pin 4 of the chip. In the case of the antialias filter test
function, the outpul is taken directly to the INTOUT pin 4 of the
chip.
FIGURE 40. SOFB, S1FB AND INOUT EQUIVALENT OUTPUT
CIRCUITS
FIGURE 4. INTERFACE CIRCUITS
10-51
HIP9010
TABLE 2. FREQUENCY, BALANCE I GAIN AND INTEGRATOR TIME CONSTANT SEmNGS
BIT VALUE PER
FUNCTION
FREQUENCY
0
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
20
21
22
23
24
25
26
27
26
29
30
31
kHz
OUTPUT
LEVEL
TIME
CONSTANT liS
1.22
1.26
1.31
1.35
1.40
1.45
1.51
1.57
1.63
1.71
1.78
1.67
1.96
2.07
2.18
2.31
2.46
2.54
2.62
2.71
2.81
2.92
3.03
3.15
3.28
3.43
3.59
3.76
3.95
4.16
4.39
4.66
1.000
0.960
0.923
0.869
0.657
0.626
0.600
0.n4
0.750
0.727
0.706
0.666
0.667
0.649
0.632
0.615
0.600
0.576
0.554
0.533
0.514
0.497
0.480
0.465
0.450
0.436
0.424
0.411
0.400
0.369
0.379
0.369
40
45
50
55
60
65
70
75
60
90
100
110
120
130
140
150
160
180
200
220
240
260
260
300
320
360
400
440
460
520
560
600
BIT VALUE
PER
FUNCTION
32
33
34
35
36
37
3B
39
40
41
42
43
44
45
46
47
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
~ ADDRrS DECODER I
M~
-
SCK
~
r--:'....,
w
I----
REFERENCE FILTER
!-.... ,
J-t
KNOCK FILTER
....,~
it
'"
""--
~<>---i
I
BALANCE CONTROL
OSCIN
TESTI CHANNEL SELECT ATTENUATE
f---t ~c;
;:)
MOSl-
is
'i'Es'i'--I
COMPARATOR OUT(FROM RECTIFIER PHASE - - DETECTOR)
FIGURE 5. DIGITAL BLOCK DIAGRAM
10-52
4.95
5.12
5.29
5.46
5.66
5.90
6.12
6.37
6.64
6.94
7.27
7.63
8.02
8.46
8.95
9.50
10.12
10.46
10.83
11.22
11.65
12.10
12.60
13.14
13.72
14.36
15.07
15.64
16.71
17.67
18.76
19.98
0.360
0.346
0.333
0.320
0.309
0.298
0.268
0.279
0.270
0.262
0.254
0.247
0.240
0.234
0.228
0.222
0.217
0.208
0.200
0.193
0.166
0.179
0.173
0.166
0.163
0.158
0.153
0.149
0.144
0.141
0.137
0.133
a:
t---t 5::Ii
~ [] J OSCOUT
OUTPUT
LEVEL
-
INTEGRATOR TIME CONSTANT
OSCILLATOR
CIRCUIT
kHz
w
1-- ...g
(J
if
;---o-;'~
a:
w
~
~ ~.....
FREQUENCY
Mi'S'O
HIP9010
The digital block diagram shows the programming flow of the
chip. An eight bit word is received at the MISO port. Data is
shifted in by the SCK clock when the chip is enabled by the
CS pin. The word is decoded by the address decoding circuit, and the information is directed to one of 5 registers.
These registers control:
cs
INTIHOLD
1. Reference knock filter frequency.
2. Knock filter frequency.
3. Balance control or attenuation of one channel with respect to the other.
FIGURE 7. POWER UP SEQUENCE
1--
4. Integration time constant of the sum of the two channels.
5. One of 3 functions.
a) test conditions of the part.
b) channel select to one of two sensors.
c) channel to be attenuated.
13--1--
INTOUT
A crystal oscillator circuit is provided. The chip requires a 4MHz
crystal to be connected across OSCIN and OSCOUT pins.
FIGURE 8. INTEGRATOR TIMING
In the test mode, use the digital multiplexer to output one of
the following signals:
TABLE 4. INTERGRATE/H()[i) TIMING REQUIREMENTS
1. Contents of one of the five registers in the chip.
2. Inverted signal of the MOSI pin.
DESCRIPTION
3. Voltage of an intemal comparator used to rectify the analog signal.
INTIHOLD
UNITS
Tl max. rise time of the INT/HOLD signal.
45ns
T2 max. time after INT/HOLD rises for the INOUT 10
begin to Intergrate.
2D11S
T3 max. fall time of INTIHOLD signal.
45ns
T4 typical time after INT/HOLD goes high before chip
goes into hold state.
20115
Test Multiplexer
----~'~Lr-~'--U-~,--,~"""
__,~"""~·~
____~~J~~'--'~I~J~..Jl~'~J~~~
This circuit receives the positive and negative outputs out of
the two integrators, together with the outputs from different
parts of the chip. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capaCitor filter output, the gain control
output as well as the antialias output.
Differential to Single-ended Converter
FIGURE 6. SPI TIMtNG
Tl min. time from CS falling edge to SCK falling edge.
IOns
This Signal takes the output of the two integrators (through
the test multiplexer circuit) and provides a signal that is the
sum of the two signals. This technique is used to improve the
noise immunity of the system.
T2 min. time from CS falling edge .to SCK rising edge.
80ns
Output Buffer
This output amplifier is the same as the input amplifier used
to interface to the sensors. For test purposes when we look
at the output of the antialias filter, the input amplifiers are in
the power down mode.
TABLE 3. SPI TIMING REQUIREMENTS
DESCRIPTION
UNITS
T3 min. time for the SCK low.
60ns
T4 min. time for the SCK high.
60ns
T5 min. time from SCK rise after 8 bits to CS rising edge.
80ns
T6 min. time from data valid 10 rising edge of SCK.
60ns
T7 min. time for data valid after the rising edge of the
SCK.
IOns
T8 min. time after CS rises untiIINT/HOLO goes high.
8115
10-53
t/)
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eto
C3i=
wo
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t/);:)
II-
HIP9020
Programmable Quad Buffer with
Pre and Post Scaler Dividers
October 1993
Features
Description
• Sine Wave Speedometer Input
The HIP9020 is a Vehicle Speed Sensor (Vss) Buffer IC. It
receives sinusoidal vehicle speed information from a
speedometer signal source. The signal is amplified and
squared before frequency processing is done. The circuit
provides pin programmable integer prescaler and postscaler
dividers to scale the output frequencies. The prescaler
divider output of the frequency doubler is mode selected for
1 and 6 through 11. The postscaler mode is selected to the
Output 3 with a divide by 1 or 2. The four Vox outputs are
open collector drivers.
• Input Limiting ........... ±O.25V to ±100V (with 40kil)
• Over Voltage Protection
• Current Umltlng
• Programmable Prescaler 1, 6 - 11
• Post Scaler Frequency Divide by 1 or 2
• Drivers with 15mAl24V Capability
• Outputs 4 Separate Square Waves
Speed Sensor Input (SSI) - When current limited with a
40kil source impedance from the vehicle speed sensor, the
SSI input is capable of functioning over a wide range of input
signal. The limiter and squaring action is derived from the
zero crossing of the input signal. The signal is converted into
a square wave with a controlled hysteresis squaring
amplifier.
• Internal Regulator and Bias Source
• OkHz to 6kHz Input Signal Range
• -40°C to +125 0 C Operating Temperature Range
Applications.
• Prescaler
Power Supply - The power supply pin 2 input is intended to
operate from a 5.0V ± 0.3V source. The internal reference
sources are derived from a temperature stable bandgap;
including an optional 5.7V shunt regulator which may be
used as shown in Figure 2.
• Buffer/Umlter
• Signal Interface
• Automotive Speedometer
• Automotive Speed Control
Output Drivers - Each output driver is an open NPN collector
with a zener clamp level of typically 35V and short circuit
current limiting. Each output is capable of sinking 15mA of
current.
• Automotive Tachometer
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
HIP9020AP
-40·e to +12s·e
14 Lead Plastic DIP
HIP9020AB
-40·e to +12s·e
20 Lead Plastic sOle (W)
PACKAGE
Pinouts
HIP9020 (PDIP)
HIP9020 (SOIC)
TOP VIEW
TOP VIEW
GND
VOl
NC
poss
SSI
V03
V04
1 PRS5-A
NC
PRSO
PRSS-B
POSI - . _ _ _-r-"
1 PRSS-C
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993
10-54
File Number
2790.2
HIP9020
Programmable Quad Buffer Functional Block Diagram
BUF
(BUFFER OUTPUT)
SSI
POSI
}----I
DIY BY 2
1--+-1...:::.:.:~.t1'";;:--1
:::===::::
(POST SCALER INPUT)
OUTPUTS
YOLT. REG. &
CURRENT
SOURCE
POSS
(POST SCALER SELECT)
,....--~-o()
EACH OUTPUT
PROTECTED BY A
COLLECTOR·To-BASE
ZENER DIODE CLAMP
30Y
o
YOX
CIRCLED NUMBERS ARE 20 LEAD SOP PACKAGE
200
LOGIC SELECT FOR INPUT (SSI) TO OUTPUT (VOX) DIY·BY NUMBER
PRS5-A
PRS5-B
PRSS-C
VOt, V02, V03
(POSSHIGH)
DIY·BY
V04
(POSSHIGH)
DIV·BY
VOt, V02
(POSSLOW)
DIV·BY
V03,V04
(POSSLOW)
DIV·BY
0
0
0
2
1
2
1
0
0
1
12
6
12
6
0
1
0
14
7
14
7
0
1
1
16
8
16
8
1
0
0
18
9
18
9
1
0
1
20
10
20
10
1
1
0
22
11
22
11
o
...JZ
0(0
uj:
wo
n.z
0::1
II-
10·55
Specifications HIP9020
Absolute Maximum Ratings
Thermal Information
Supply Voltage to Pin 2. vee (Shunt Regulator) •••••• +24Voe Max
through 3000 and a Series Diode (1 N4005 or Equiv.) or +5.3V
Max Direct Voltage Supply Souree to Vee
Output Voltage (Sustained) to V01.V02.V03.V04 .••••••••• +24V
Output Load Current (Sink) . • . • • • • • • • • • • • • • • . • • • • . •• +15mA
Input Voltage (Through 401<0, See Figure 1) .•••.••••.••• ±100V
Thermal Resistance
9JA
Plastie DIP and SOIC Package •••••••••••••••••••••• 900 C/W
0
Maximum Package Power Dissipation up to +85 C ..••••• 720mW
Derate above 85°C •••.••...•..•........•....••. 11.1mWI"C
Operating Temperature Range •••••••••••••••• -4ooC to + 125°C
Storage Temperature Range •••••••••..•••••• -650 C to +ISOOC
Maximum Junction Temperature. • • • • • • • • • • • • • • • • • • • • • +150°C
Lead Temperature (Soldering lOs) •••••••••••••••••••• +265°C
CAUTION: Stresses above thoselistsd in "'Absolute Maximum RaUngs' may causa permanent damage to IhB dflVics. This is a stress only raUng and opsra60n 01
the device at these or any other conditions above those indicatsd in the opera60nsl sections of this spBCifica60n is not implisd.
Electrical Specifications
TA = -40"C to +125°C. vee = 5V ± 0.3V. Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
-
12
rnA
Power Supply (Vee)
Supply Current
Icc
SSllnput (Test Point - T.P.A.. See Figure 1)
4OkO Source. 0.01 j!F Input Shunt
-
6
kHz
Input Signal Range
4OkO Source. 0.01 j!F Input Shunt
±O.25
±100
V
Input HystereSiS
4OkO Source. O.OIIlF Input Shunt
0.15
0.45
V
Input Bias Current
4OkO Source. O.OIIlF Input Shunt
..(l.5
+0.5
IlA
1.5
V
Max. Operating Frequency
'S(MAX)
Other Inputs (PRSS. POSS. POSI - See Function Block Diagram)
Input Low Voltage
VIL
-
Input High Voltage
VIH
3.5
Input Current High
IIH
Vee = VIN = 4.7V
Input Current Low
IlL
Vee = 5.3; VIN = O.4V
-
-
V
10
-10
-
IlA
IlA
PRSOOutput
Output Voltage Low
VOL
Vcc=5V
-
0.4
V
Output Voltage High
VOH
Vcc=5V
4.6
-
V
OUtput Clamp Voltage
Icc = lrnA
24
45
V
OUtput Current Limit
Isc Current Pulsed
15
30
rnA
-
30
IlA
Driver Outputs (VOl. V02. V03. V04)
OUtput Leakage
VouT =24V
Output Saturation Voltage
VSAT
-
lOUT = 15rnA
lOUT
-
= 1rnA
VBATT
TYP. 5.7V -.""... 1N4~05 300
OUTPUT TO
SPEED ... -::b O.OII'F
SPEEDOMETER
I ....
SENSOR
~
ODOMETER.
lK
Vee
INPUT
SPEED
VOl
CONTROL, ETC.
40K
SSI
V02 rOUTPUTS
V03 I- (OPENNPN
PRSO
COLLECTORS)
IV04
POSI
Jill
-=-
[
opnONA~r
OUTPUT
BUF
GND
~} ""CMm
SELECT
A
B
C IPOSS I-
V
25
i
20
....
z
15
~
w
a:
a:
:)
...
0
I
'A
10
:)
\;
0
INPUTS
V
0.4
TA_+250C
C
..:
I
1
5
0
/
V
/
DRIL
UMITED
CURRENT
OUTPUT
r-r--
SATURAT~D
OUTPUT
·ON" CHARAC.
0.1
0.2
0.3
0
0.4
0.5
0.6
OUTPUT VOLTAGE VOX WITH Vee - 5 V. VSAT (V)
~
FIGURE 1. TYPICAL AUTOMOTIVE APPLICATION CIRCUIT
FIGURE 2. TYPICAL OUTPUT DRIVER SATURATED ·ON"
CHARACTERISTIC
10-56
INTELLIGEN 11
POWERICs
APPLICATION NOTES
APPUCATION NOTES
AN027.1
PAGE
Power Supply Design Using the ICL8211 and ICLB212 ................•.........
11-3
AN051.1
Principles and Applications of the ICL7660 CMOS Voltage Converter ....•.•.......
11-11
AN5766.1
Application of the CA3020 and CA3020A Multipurpose
Wide-Band Power Amplifiers .•......•....••...............•......•.•.......
11-21
AN6048.1
Some Applications of a Programmable Power Switch/Amplifier ........•..•........
11-29
AN6077.1
An IC Operational Transconductance Amplifier (OTA) with Power Capability ..•..•....
11-42
AN6157.1
Applications of the CA3085 Series Monolithic IC Voltage Regulators ..••...........
11-52
AN6182.1
Features and Applications of Integrated Circuit Zero-Voltage Switches
(CA3059 and CA3079) ...........•.........................•...•.........
11-63
AN6915.1
Application of the CA 1524 Series Pulse-Width Modulator ICs.............•.......
11-94
AN7174.1
The CA 1524 Pulse-Width Modulator-Driver for an Electronic Scale ...•............•
11-112
AN7244.2
Understanding Power MOSFETs ..••.•..••..••.•.....•..•....•...•.•...••..
11-114
AN7254.2
Switching Waveforms of the L2FET: A 5 Volt Gate-Drive Power MOSFET •..........•
11-118
AN7326.1
Applications olthe CA3228E Speed Control System ••.•.••••.•••.•••.....•..•..
11-126
AN8614.1
The CA1523 Variable Interval Pulse Regulator (VIPUR) for
Switch Mode Power Supplies •.••..........•.....•.••.••.••...••.......•..•
11-142
AN8829.2
SP600 and SP601 an HVIC MOSFETIIGT Driver for Half-Bridge Topologies ••......•
11-155
AN9010.4
HIP2500 High Voltage (500Vocl Half-Bridge Driver IC ..........•.•..•...••.....•
11-161
AN9105.1
HVICIIGBT Half-Bridge Converter Evaluation Circuit ..••.•.•.•...•...•••......•.
11-169
AN9201.1
Protection Circuits for Quad and Octal Low Side Power Drivers ....•.......•....••.
11-170
AN9208
High Frequency Power Converters .•••..•...•....•••..•....•.............••.
11-178
AN9209.1
A SPICE-2 Subcircuit Representation For Power MOSFETs,
Using Empirical Methods ..•......••.••.•.........••..•.•.••.•••...•••....
11-187
HIP5060 Family Of Current Mode ControllCs Enhance
1MHz Regulator Performance ......••..•............•....••................
11-191
AN9212.1
Z
-CI)
!ccUJ
01-
AN9217.1
High Current Off Line Power Supply .••.•..•...•..••.••.••........•....••.•..
11-198
AN9301
High Current Logic Level MOSFET Driver .•••.•.•........•......•••.....•....
11-209
AN9302.1
CA3277 Dual 5V Regulator Circuit Applications .•••...•.....••..•••.....•...•..
11-212
AN9304.3
ESD and Transient Protection Using the SP720 .•.••.....••........•....•..••..
11-221
AN9323.1
HIP5061 High Efficiency, High Performance, High Power Converter ...••.•..••••...
11-231
AN9324.1
HIP4080, 80V High Frequency H-Bridge Driver •..•.....••••.•...•...•.......•.
11-241
AN9325
HIP4081, 80V High Frequency H-Bridge Driver •..•.......•..•...•...•.......••
11-253
AN9404
HIP4080A, 80V High Frequency H-Bridge Driver .....••.•.•••••..••••....•....•
11-264
AN9405
HIP4081A, 80V High Frequency H-Bridge Driver .•••.•.......••..............•.
11-276
11-1
0
-0
~z
D..
~
Harris Semiconductor
-
----=-==- --- -====-= -==-----=
No. AN027.1
-;;
::.::
-=
=
~
Harris Intelligent Power
Apri11994
POWER SUPPLY DESIGN USING THE ICL8211 AND ICL8212
Introduction
The ICL8211 and ICL8212 are micropower bipolar monolithic integrated circuits intended primarily for precise voltage
detection and generation. These circuits consist of an accurate voltage reference, a comparator and a pair of output
buffer/drivers.
Specifically, the ICL8211 provides a 7mA current limited output sink when the voltage applied to the THRESHOLD input
is less than 1.15V. Figure 1 shows a simplified functional diagram of the ICL8211.
v+o----.------~~~--._-~
8
1.1SV
VOLTAGE
REFERENCE
For a detailed circuit description of the ICL821111CL8212
refer to the data sheet. For large volume applications the
ICL8211I1CL8212 may be customized by the use of metal
mask options to include setting resistors or to vary the output
options, or even to adapt the circuit as a temperature sensingelement.
Applications for the ICL821111CL8212 include a variety of
voltage detection circuits, power supply malfunction detectors, regulators, programmable zeners, and constant current
sources. In this discussion we will explore the uses of the
ICL821111CL8212 in power supply circuits of various types.
Their attractiveness to the power supply designer lies largely
in their ability to operate at low voltage and current levels
where standard power supply regulator. devices cannot be
used. In addition, the unique features of the ICL8211/
ICL8212 make them useful in many ancillary circuits such as
current sources, overvoltage crowbars, programmable zeners and power failure protection.
3
=:.---+----0 THRESHOLD
Positive Voltage Regulators
Using the ICL821111CL8212 it is possible to design a series
of power supply regulators having low minimum input voltage and small inpuVoutput differential. These are particularly
useful for local regulation in electronic systems as their small
inpuVoutput differential results in low power loss.
5
~o---~--------~-----+--~
FIGURE 1. 1CL8211 FUNCTIONAL DIAGRAM
The ICL8212 provides a saturated transistor output (no current
limit) whenever the input THRESHOLD voltage exceeds 1.15V.
Both circuits have a low current HYSTERESIS output which is
turned on when the THRESHOLD voltage exceeds 1.15V,
enabling the user to add controlled hysteresis to his design.
Figure 2 shows a simplified functional diagram of the ICL8212.
Q1
INPUT
2.2V-30V
+
ICL8211
R2
v+o---.----~~~--+_-~
TH
~
8
-tJ)
!;iw
~b
3
5
Z
0
R3
~Z
0C(
FIGURE 3. POSITIVE REGULATOR - PNP BOOST
4
OUTPUT
5
~~--~--------+---------~
FIGURE 2. 1CL8212 FUNCTIONAL DIAGRAM
The ICL8211 in Figure 3 provides the voltage reference and
regulator amplifter while 01 is the series pass transistor. R1
defines the output current of the ICL8211 while C1 and C2
provide loop stability and also act to suppress feed-through
of input transients to the output supply. R2 and R3 determine
the output voltage as follows:
V OUT
Copyright © Harris Corporation 1994
11-3
R2+R3
= 1.15X R
3
Application Note 027
In addition, the values of R2 and R3 are chosen to provide a
small amount of standing current in a1, which gives additional stability margin to the circuit. Where accurate setting
of the output voltage is required, either R2 or R3 can be
made adjustable. If R2 is made adjustable the output voltage
will vary linearly with shaft angle; however, if the potentIometer wiper were to open circuit, the output voltage would rise.
In general, therefore, it is better to make R3 adjustable as
this gives fail-safe operation.
The choice of al depends upon the output requirements.
The ICL8211 has a worst case maximum output current of
4mA, so with any reasonable device for al the circuit should
be capable of SOmA output current with an input to output
drop of O.5V. If larger output currents are required al could
be made into a complementary quasi-darlington, but the
input/output differential will then increase.
Note also that al provides an inversion within the loop so
the non-inverting ICL8211 must be used to give oll9rall negative feedback.
the ICL8212 and the absence of charge storage effects in the
FEr, these considerations are not particularly restrictive.
For higher current outputs the system could be further
boosted using a bipolar transistor. One attraction of using a
FET only output, howell9r, is that the loss of the FET gill9s a
measure of output short circuit protection. Should both the
low input/output differential of the circuit of Figure 3 plus the
extended input voltage capability of Figure 4 be required, the
circuit of Figure 5 may be used.
+
A1
R2 f C 1 )
D2
IN PUT
,.---
·l· ~
:~RS
One limitation of the above circuit is that input voltages must
be restricted to 30V due to the voltage rating of the ICLB211.
The circuit of Figure 4 avoids this problem.
Ie..... ~1
:., ...
v+
"j
i
+
R3:
ICl8211
: OUTP UT
C2
y.TH 3
··
+
Q2
~
4
OIP
~D1
... ...... _-_ .... _...
R4
15
I
FIGURE 5. POSITIVE REGULATOR - NPN + PNP BOOST
FIGURE 4. POSITIVE REGULATOR - JFET BOOST
In this circuit the input voltage is limited only by the voltage
rating of a 1. The input/output differential is now dependent
on the ROS(ON) of the JFET boost transistor. For instance, if
al were a 2N4391 the maximum output current would be
equal to IOSS(MIN) which is SOmA and the input! output differential would be:
RoS(ON) x 'LOAD
=300 x 50mA =1.5V
However, at lower load currents the input/output differential
will be proportionately lower.
This circuit is similar to that of Figure 3 except that a1 has
been added as a common base stage to buffer the output of
the ICL8211 from the input supply and Rl and 01 to protect
the input. Unfortunately, the ICL8211 cannot be supplied
from the regulated output as this would result in the power
supply being non seH-starting. The choice of values for R2.
R3, R4, Cl and C2 is identical to that of Figure 3, while 01
must be a voltage equal to or larger than the output voltage.
R1 must be chosen to provide the relatively low supply current requirement of the ICL8211. An alternatill9 arrangement
for starting the circuit is to replace 01 with R5 and add 02. In
this case the choice of Rl and R5 is such that once the output supply is established the ICL8211 is supplied through 02.
In the circuit of Figure 5, al and a2 are connected in the classic S.C.A. or Thyristor configuration. Where higher input voltages or minimum component count are required the circuit of
Figure 6 can be used. The thyristor is running in a linear mode
with its cathode as the control terminal and its gate as the output terminal. This is known as the remote base configuration.
A further consideration when choosing the FET boost transistor is that its pinch-off voltage must be less than the output voltage in order for the ICL8212 to be able to pull the
gate down far enough to turn the device off at no load.
The predominant loop time constant is provided by R2 and
Cl. This time constant should be chosen as small as possible commensurate with loop stabllny as it also affects load
transient response. After an abrupt change In load current Cl
must be charged to a new voltage level by R2 to regulate the
current in a1 to the new load IeIl9I and therefore the smaller
the R2 xCI product the better the load transient response.
The value of C2 should be chosen to maintain the output
within desired limits during the recovery period of the main
loop. Note, however, that because of the wide bandwidth of
11-4
+
~'Q1
R1
1\
Ie
v+
OIP
IN PUT
~~
+
t
R3 fC1
4
R3
ICW11
OUTPUT
D1
y.
1&
TH
3
T
C2
R4
FIGURE 6. POSITIVE REGULATOR - THYRISTOR BOOST
Application Note 027
A word of warning, however. Thyristor data sheets do not
generally specify individually the gain of the PNP portion of
the thyristor, on which the circuit relies. It must therefore
either be very conservatively deSigned or some screening or
guarantee of the PNP gain be provided.
Note that, with the exception of the loss limit of Figure 4,
none of the circuits so far provide output current limiting. In
general, they are intended for applications in which the extra
voltage drop of a current sensing resistor would be unacceptable. Where the circuits are used as local regulators and
the output supplies are only connected to local circuitry the
chance of output short circuits is relatively low and overcurrent protection is considered unnecessary. Where protection
is required it can be added by any of the standard techniques. Figure 7 shows the simplest possible constant current protection added to the circuit of Figure 3.
8
V+O/P
4
INPUT
2.2V -30V
IC18211
+
R3
V- TH 3
6
OUTPUT
1.1SV-28V
C2 SOj
R4
+
+
fa
v+
R1
IN PUT
~
R3
TH
O/P
;-
OUTPUT
1CL8211
R2
R4
C2
V-
-'T~c116
FIGURE 8. NEGATIVE REGULATOR - JFET BOOST
Figure 9 is the closest negative equivalent to the circuits of
Figures 5 and 6. In this case Rl, R2 and 01 ensure that the
circuit is seH starting. The divider Rl/R2 must be chosen to
ensure that sufficient voltage (say -1 V) is present at the base
of 01 to start the circuit under minimum output \/Oltage conditions, but once the circuit is running 01 must remain forward biased even at maximum input \/Oitage, otherwise the
output of the ICL8212 will be unable to pull the emitter of 01
low enough to turn it off under no load conditions. Thus for a
3V output supply which runs from a minimum 4V input the
ratio of Rl to (Rl + R2) must be one quarter. In order that
the base of 01 is not taken below ·3V once the circuit is running the maximum input voltage would therefore be ·12V. An
alternative arrangement which avoids this restriction is to
replace Rl with a zener diode, reduce the value of R2 and
delete 01.
In this case the only restriction is that the zener voltage shall
be less than or equal to the output voltage of the regulator.
FIGURE 7. POSITIVE REGULATOR· PNP BOOST CURRENT
LIMITED
In this circuit the current threshold is set by the base-emitter
voltage of 01 so that when the \/Oitage drop in R2, due to
load current, Is sufficient to turn on 01 base drive is removed
from 02 by 01 collector. Note that this circuit works only
because the output current of the IC18211 is current limited
so that there is no danger of 01 and the IC18211 blowing
each other up with unlimited current.
In the circuit of Figure 9, R3 must be chosen to provide sufficient base drive for 02 via 01 under maximum load conditions. The maximum value of the current in R3 which may be
tolerated is 12mA, the worst case sink current of the
ICLB212 output transistor.
,,,
,
"t;,
,,
Negative Voltage Regulators
RS
R1
.. .....
~ ~
Because the reference voltage of the ICL8211/1C18212 is
connected to the negative supply rail, and their output consists of the open collector of an NPN transistor, it is not possible to construct a negative equivalent of the circuit of
Figure 3. However, a negative equivalent of Figure 4 is eas·
ily constructed.
Of course the JFET must now be a P·channel device but
otherwise the design considerations are identical to those for
Figure 4. Should further boost of the output current level be
required, an NPN boost transistor, 02, (shown dotted) can
be added. However, the charge storage effects of the NPN
transistor will reduce the loop bandwidth so that R2 or CI
should be increased to maintain stability. Note also that in
the circuit of Figure 8 an ICL8211 is used instead of an
ICL8212 in order to maintain correct feedback polarity.
8
TH
INPUT
OUTPUT
3
C2
R4
5
Z
0
-(f)
~w
(.)~
-0
~z
Q.
~
R2
FIGURE 9. NEGATIVE REGULATOR - NPN + PNP BOOST
Current limit can be applied to the circuits of Figure 9 in an
analogous manner to Figure 7. In this case R3 is the current
source for the base of 02, ensuring that the current limit
transistor 03 has a defined maximum collector current.
11-5
Application Note 027
+
h
v+
~~
8
R3
v+
AI
D1
OIP
4
r;-
TH
ca
1CL8211
OUTPUT
OR
ICL8212
ICL8212
INPUT
.~
ICL8212 1-25!lA
ICL8211 1_130""
Is
.1 Q3l..'r
A2
A7
v-
~Q1
A1
3
C1
T
)02
FIGURE 12. CONSTANT CURRENT SOURCES
A4
AS
FIGURE 10. CURRENT UMITED NEGATIVE REGULATORNPN + PNP BOOST
Ancillary Power Supply Circuits
Figure 11 shows the ICL8212 connected as a programmable
zener diode. Zener voRages from 2V up to 3tN may be programmed by suitable selection of R2, the zener voRage being:
Vz
= 1.15x R1 +R2
R1
Iz
Ie
v+
OIP
Vz
J
AI
4
FIGURE 13. PROGRAMMABLE CURRENT SOURCE
C1
ICL8212
I
v-
TH
5
4
IE
~
3
In this case the output current is given by:
VeE 1.15
10 = 251lA+RT + R2 (1 +~)
A1
150k
15
•
5""
L
,
Where ~ is the forward current gain of 01 and VeE is its
emitter-base voltage. The principal cause of departure from
a true current source for this circuit will be the variations in ~
with collector voltage of 01. With the currenl settable anywhere in the range of about 3OO1lA to 50mA and an operating voltage range from 2V to 3OV, this circuit is particularly
suitable as the current source driving the base of an output
transistor in conventional series regulator power supplies.
Another useful application is as the current source feeding a
reference zener in highly stable reference supplies. Again,
because of the absence of internal compensation in the
ICL8212, C1 is provided to ensure loop stability. It also helps
to keep output current constant during voltage changes or
transients.
.J
I
2
o
0.01
0.1
1.0
10
100
Iz(mA)
FIGURE 11. PROGRAMMABLE ZENER
Because of the absence of internal compensation in the
ICL8212, C1 is necessary to ensure stability. Two points
worthy of note are the extremely low knee current (less than
3001lA) and the low dynamic impedance (typically 40 to 70)
over the operating current range of 3
§
a:
"
100
I-
~
~
82
v._.sv
10
100
lK
2
10K
The dependence of the frequency on this external capaci·
tance Is shown In Figure " . This can also be done to move
the frequency away from a band of undue sensitivity to EMI
in a system. However the output ripple will be increased, and
the output impedance also unless the pump and storage
capacitors are correspondingly increased.
1=
I--
10K
~w
8w
....
\
lK
,
z
o
-til
!cw
(.)1-
IE
I§
~100
13
~
0
1
3
4
5
~
FIGURE 10. EFFICIENCY CHANGE WITH OSCILLATOR
FREQUENCY
::lI
0
...a:
OSCILLATOR FREQUENCY (Hz)
\.
a:
-
tI4
...~
a:
w
is.
......... ~
w
8w
1ouy_I5mA
80
115
!
u
'ii'
82
z
0
lK
10
_
tI4
It
w
w
~
T . .2&"e
II
I
TA-+2SoC
w
.
..
l
~
w
FIGURE 7. OUTPUT CHARACTERISTICS
10K
~VOUT
50
LOAD CURRENT (mAl
~
Rl
~.:!:
I0!0F~
§
, . SLOPE 560
10
~-----~l
I
~=
1CL7880
...0
i...--'
-4
~
10~l£[i
a:
.
-2
G.
Cl·
w
.
...
-1
1i~[i}l.sV
~
:
:
0
-Ii
V+
:
:
TA-+2&"C
V+_.sV
4
6
7
!l
8
10
SUPPLY VOLTAGE (V.l
I'
-0
itz
,
a..
CC
V+_SV
TA-+2&OC
1.0
10
100
1000
10K
Cosc(pF)
FIGURE 8. OUTPUT RESISTANCE
Figure 9 also shows an external oscillator capacitor. This
can be used to reduce the oscillator frequency, giving a
slight improvement in efficiency; see Figure 10.
FIGURE 11. FREQUENCY VARIAnoN WITH OSCILLATOR
CAPACITANCE
11-15
Application Note 051
Synchronization to an external clock can be readily
achieved, as shown in Figure 12. A TIL device can be used
with the addition of a pull-up resistor (lOkn to V+ is suitable), as can any input swinging rail-to-rail on the positive
supply. The series resistor prevents problems with overdrive
on the internal logic. Output transitions occur on the positive
edge of the external input.
v+
to put two ICL7660s into antiphase by comparing the outputs
on pin 2, and clocking one to maintain near synchronization
with the basic oscillator of the other, as shown in Figure 14.
v+
CMOS
GATE
FIGURE 12. EXTERNAL CLOCKING
Wider (Parallel Connections)
For applications where the voltage drop due to load current is
excessive, several ICL7660s can be paralleled. Normally this
cannot be done efficiently with power supply circuits, since
each one has a different idea of where the "idear output voltage would be and they usually end up fighting each other.
However, here they see equal input voltages, and the virtually
perfect inversion assures that each one does have the same
idea of where the output should be so load sharing is assured.
Each device must have a separate pump capacitor, since the
oscillators cannot be synchronized except with an external
drive, and even then the -2 will be in a random condition. The
connections are shown in Figure 13. Naturally the output
capacitor is common to each device. Running independently,
the ripple content will include components at the difference
frequency as well as the individual pumping frequencies. If
this is undesirable, a single exclusive NOR gate can be used
FIGURE 14. SYNCHRONIZING TWO ICL7660s
The concept can be extended to drive four devices in four
separate phases, using a single extra logic-gate package, as
shown in Figure 15. The duty cycle of the oscillator is
reasonably close to 50%, so driving two pairs, each in the
configuration of Figure 14, from opposite phases of the
oscillator gives four separately-timed pumps per cycle. This
circuit will give about 75mA output before the voltage drops
by W, or an output impedance of under 14n The four phase
operation minimizes the ripple, while ensuring very even
load sharing. For even more parallel synchronous device, a
Johnson counter using a and a· outputs should be
considered.
FIGURE 13. PARALLEUNG DEVICES
11-16
Application Note 051
This technique can be extended to several multiplication levels. However. the basic limitations of this technique must be
recognized. In line with the Laws of Thermodynamics. the
input current required for each stage is twice the load current
on that stage. plus the quiescent current required to operate
that stage.
V+
1M
n
Thus the load current is rapidly multiplied down the chain. as
shown in Figure 17. Note also that the quiescent current
increases the load current on each stage. though not as fast
as the ultimate load itseH.
SUPPLY
31L+3Ig
LOAD.
31L+2Ia
I
Va
41L+~lt
VII
IIL+5!a
QND
OV
21L+2Ia
31L + 2Ia
VOUT
31L+3Ig
IL
VII
:!: Cl
LOAD.
21L + Ia
41L+31a
QND
IL+1a
VII
QND
1/4CD40n
RL
f CZ
LOAD.
IL
21L+1a
IL
VOUT
I
21L+1a
f
C3
I
Vel· Va' Ro (31L. 21a)
Va· Va - Ro (51L. 31a)
Va. Va - Ro (6IL. 310)
VOUT
"-
VOUT. -{3Va - Ro (14IL· 8Ig))
FIGURE 17. CURRENT FLOW FOR CASCADED DEVICES
FIGURE 15. SYNCHRONIZING A QUAD
Deeper (Series Connection)
It is also possible to connect ICL7660S in series. cascading
them to generate higher negative voltages. The basic connections are shown in Figure 16.
Furthermore. the loss in voltage in early stages due to series
resistance is multiplied through all subsequent stages. Thus
the effective output impedance mounts rapidly with the number of stages. (See Table 1) This effect can be reduced by
paralleling devices in the lowest stages (see above.) If the
weighting corresponds to the square of the position. the
effective resistance to load current goes up only linearly with
z
o-en
!ccw
~b
~z
I5l-lollH_
VOUT (SEE NOTES)
NOTES;
1. VOUT = -n+ for 1.5V S V+ S 6.5V.
2. VOUT = -n (V+ -VFOx) for 6.SV S V+ S 10.0V.
FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
11-17
~
Application Note 051
the number of stages. but the cost quickly becomes prohibitive. Nevertheless. for light loads and moderate multiplication. useful performance can be achieved.
TABLE 1
II STAGES
RESISTANCE
MULTIPLIERS
n
Ro(L)
Ro(Q)
1
1
0
2
5
2
3
14
8
4
30
20
5
55
40
two devices. The output impedance corresponds roughly to
n 2 in Table 1. much better than if the previous circuit were
used with n .. 3. In general. geometric increases. as in Figure 18. are better until the voltage limit is reached. at which
time arithmetic cascading as in Figure 16 must be utilized.
=
Upside Down (Positive Multiplication)
The ICL7660 may be employed to achieve positive voltage
multiplication using the circuit shown in Figure 19. In this
application. the pump inverter switches of the ICL7660 are
used to charge C, to a voltage level of V+ -VF (where V+ is
the supply voltage and V F is the forward voltage drop of
diode 0,) On the transfer cycle. the voltage on C, plus the
supply voltage (V+) is applied through diode 02 to capaCitor
C2 . The voltage thus created on C2 becomes (2V+) - (2VF)
or twice the supply voltage minus the combined forward voltage drops of diodes 0 , and 02'
A variation of this circuit. another form of series circuit. is
shown in Figure 18. This circuit can be used effectively to
generate -15V from +5V in light load applications using only
The source impedance of the output (Vour) will depend on
the output current. but for V+ 5V and an output current of
10mA it will be approximately
=
son
-15V
5 t---1~'" VOUT
FIGURE 18. GEnlNG -15V FROM +5V
V+
VOUT. - (nV.. - vFDxl
C,
L---------.u-.;+:;.....---.....- ...__04
YOUT- (2V+)-(VFDd'" (YFD2l
FIGURE 19. COMBINED NEGATIVE CONVERTER AND POSmVE MULTIPUER
11-18
Application Note 051
Divide and Conquer
The ICL7660 can be used to split a supply in haH. as shown
in Figure 20.
.. _-_ .. ,
-
One interesting combination of several preceding circuits is
shown in Figure 21. where a +15V supply is converted. via
+7.5V and· 7.5V, to-1 5V using three ICL7660s. The output
impedance of this circuit is about 250n
::: 1Ma OPTIONAL
.••.
,
±lour
'-------4--l:~_:
,.
_
~
-!-
Your-
For other division ratios. the series configurations of Figure
16 can be driven backwards. to generate VI~n. or even ml
n(VIN). for small values of m and n. Again. care must be
taken to ensure start up for each device.
!!:!:
2
100j1F
FIGURE 20. EFFICIENT SUPPLY SPLnTlNG
Here the "basic" output connection and the "basic" negative supply input are exchanged and the output wltage thus becomes
the midpoint. Start·up can be a problem. and although careful
capacitance and load balancing may frequently be adequate. a
Simple resistor to LV will always work. The circuk is useful for
series-fed line systems. where a heavy local load at low wltage
can be converted to a lighter current. at high wltage. Other useful applications are in driving low lIOItage (e.g. +7.5V) circuits
from 15V supplies. or low voltage logic from 9Vor 12V batter·
ies. The output impedance is extremely low; aU parts of the cir·
cul cooperate in sharing the current. and so act in parallel.
For cases where the output impedance of an ICL7660 circuit
is too high, obviously some form of output regulation can be
used. Howewr in most cases adequate regulation can be
achieved at high effICiency by pre-regulating the input. A
suitabla circuit is shown in Figure 22, using the ICL7611 low
power CMOS op amp. Because of the large source-current
capability of this op amp, even on its lowest bias current set·
ting, very efficient operation is possibla. An IClB069 bandgap device is used as the reference generator for the
regulator. The output impedance can be reduced to 40,
while maintaining a current capability of well over 1omA. In
designing circuits of this type, it is important to remember
that there is a switching delay averaging one oscillator cycie
between the output of the op amp and the actual output voit·
age. This can have substantial repercussions on the tran·
sient response if the time-constants in the circuit are not
+15Y
1Ma
20""
.:f!SO!LF
FIGURE 21. +15V TO -15V IN THREE EASY STAGES
FIGURE 22. REGULATED OUTPUT INVERTER
11-19
Application Note 051
adequate. If multiple voltage converters are used. synchronization schemes such as those of Figures 14 and 15 are
probably advisable.
Messing About
The applications shown so far have corresponded to the use
of the ICL7660 as a sort of equivalent of single turns on a
power transformer. with paralleled turns to get more current.
series turns for more voltage. etc. However. there are some
other possibilities. By looking again at the block diagram
(Figure 2). it is evident that the device could be used as a
50% duty cycle high power clock driver. using either the
internal oscillator or an external signal. as in Figure 23. An
antiphase clock can also be derived from the circuit. as
shown. but the pull-up on this output. being an N-channel
switch only, does not have as good a voltage swing. It is
adequate for TIC level operation. but for CMOS clocking
may require an external pull-up resistor or transistor.
v+
Another interesting class of applications comes from the
capability to synchronously detect the output of an AC driven
transducer. as shown in Figure 24. (This could be viewed as
a signal transformer application.) Although the circuit shown
utilizes a linear transformer type of transducer. any similar
device may be used. The output voltage. which is correctly
phased and of either polarity. may be fed into an AID
converter for display or microprocessor interface as desired.
y+
FIGURE 24. TRANSDUCER DRIVER AND DETECTOR
oIL
y+·--·~~=w
y+
FIGURE 23. HIGH POWER CLOCK DRIVE
11-20
Harris Semiconductor
--=
----===
-
-
- - ----- No. AN5766.1
-
--
---§
~
---
-= ~~
-~-
-
~-
--
----
Harris Intelligent Power
April1994
APPLICATION OF THE CA3020 AND CA3020A MULTIPURPOSE
WIDE-BAND POWER AMPLIFIERS
Authors: W.M. Austin and H.M. Kleinman
The discussions in this Note are applicable to both integrated circuit types. The CA3020A can operate in all circuits
shown for the CA3020. The CA3020, on the other hand, has
a lower voltage rating and must not be used in applications
which require \/Oitages on the output transistors greater than
1SV. The integrated circuit protects the output transistor by
limiting the drive to the output stages. The drive limited current capability of the CA3020 is less than that of the
CA3020A, but peak currents in excess of 1SQmA are an
assured characteristic of the CA3020.
The CA3020 and CA3020A integrated circuits are multipurpose, multifunction power amplifiers designed for use as
power output amplifiers and driver stages in portable and
fixed communications equipment and in AC servo control
systems. The flexibility of these circuits and the high frequency capabilities of the circuit components make these
types suitable for a wide variety of applications such as
broadband amplifiers, video amplifiers, and video line drivers. Voltage gains of 60dB or more are available with a 3dB
bandwidth of SMHz.
The discussions in this Note are applicable to both integrated circuit types. The CA3020A can operate in all circuits
shown for the CA3020. The CA3020, on the other hand, has
............,
VOLTAGE REGULATOR
("
:
I: •
••
•
more limited \/Oltage and current handling capability and
must not be used in applications which require \/Oltage
swings on the output transistors greater than 1SV or peak
currents in excess of 15OmA.
The CA3020 and CA3020A are designed to operate from a
single supply \IOItage which may be as low as +3V. The maximum supply \IOItage is dictated by the type of circuit operation.
For transformer loaded class B amplifl8r service, the maximum
supply \/Oltages are +9V and +12V for the CA3020 and the
CA3020A, respectively. When operated as a class B amplifier,
either circuit can deliver a typical output of 150mW from a +3V
supply or 400mW from a +SV supply. At +9V, the idling dissipation can be as low as 19OmW, and either circuit can deliver an
output of ssomw. All output of slightly more than 1W is available from the CA302QA when a + 12V supply is used.
Circuit Description and Operation
Figure 1 shows the schematic diagram of the CA3020 and
CA3020A. and indicates the five functional block into which
the circuit can be divided for understanding of its operation.
Figure 2 shows the relationship of these blocks in block diagram form.
RESISTOR VALUES IN kQ
11
1.5 :
OUTPUT
STAGE
j"""'''.
••
•••
•
0.3 lie! 4!
•
•
CIt:•
••
5 :
••
I :
•
••
. .
/II; INPUT TO
TERMINAL NO. 10
Lt~-r+--+-~~~:
•
:
O.3i
7
i•
ALTERNATE /II; INPUT
TO TERIoINAL NO. 3
l ........._..; ......................!~..............! .......!...................J..........;
FIGURE 1. SCHEMATIC DIAGRAM OF CA3020 AND CA3020A
INTEGRATED CIRCUIT AMPLIFIERS
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE CA3020 AND
CA3020A
Copyright @ Harris Corporation 1994
11-21
Application Note 5766
A key to the operation of the circuit is the voltage regulator
consisting of diodes 0 1, O2, and 0 3 and resistors RIO and
R11 • The three diodes are designed to provide accurately
controlled voltages to the differential amplifier so that the
proper idling current for class B operation is established in
the output stage. The characteristics of these monolithic
diodes closely match those of the driver and output stages
so that proper bias voltages are applied over the entire military temperature range of -55°C to + 125OC. The close thermal coupling of the circuit assures against thermal runaway
within the prescribed temperature and dissipation ratings of
the devices.
The differential amplifier operates in a class A mode to supply the power gain and phase inversion required for the
push-pull class B driver and output stages. In normal operation, an AC signal Is capacitively coupled to terminal 3, and
terminal 2 is AC grounded through a suitable capacitor.
When the signal becomes positive, transistor O2 is turned on
and its collector voltage changes in a negative direction. The
same current flows out of the emitter of O2 and tends to flow
to ground through resistor R2. However, the impedance of
R2 is high compared to the input impedance of the emitter of
Os' and an alternate path is available to ground through the
emitter-to-base junction of transistor 0 3 and then through
the bypass capacitor from terminal 2 to ground. Because this
path has a much lower impedance than R2, most of the current takes this alternate route. The signal current flowing into
the emitter of 0 3 reduces the magnitude of that current and,
because the collector current is nearly equal to the emitter
current, the collector current in 0 3 drops and the collector
voltage rises. Thus, a positive signal on terminal 3 causes a
negative AC voltage on the collector of transistor O2 and a
positive AC voltage on transistor 0 3 , and provides the outof-phase Signals required to drive the succeeding stages. It
should be noted that the differential amplifier is not balanced; resistor R3 is ten percent greater than R1• This unbalance is deliberately introduced to compensate for the fact
that all of the current in the emitter of O2 does not flow into
0 3. Use of a larger load resistor for transistor 0 3 compensates for the lower current so that the voltage swings on the
two collectors have nearly the same magnitude.
voltage at its base. This change is coupled to the input
through the appropriate resistor to correct for the increased
current.
A later section of this Note describes how stable class A
operation of the output stages may be obtained.
Operating Characteristics
Supply Voltage. and Derating
The CA3020 operates with any supply voltage between +3V
and +9V. The CA3020A can also be operated with supply
voltages up to +12V with inductive loads or +25V with resistive loads. Figure 3 shows the permissible dissipation rating
of the CA3020 and CA3020A as a function of case and
ambient temperatures. At supply voltages from +6V to + 12V,
a heat sink may be required for maximum power output
capability. The worst case dissipation Po MAX as a function of
power output can be calculated as follows:
Po MAX = (VCCI ICCI + VCC2 1CC2) + (VCC22/Rcc)
where VCCI and VCC2 are the supply voltages to the differential amplifier and output amplifier stages, respectively; ICCI
and 1CC2 are the corresponding idling currents; and Rcc is
the collector-to-collector load resistance of the output transformer. This equation is preferred to the conventional formula for the dissipation of a class B output transistor (i.e.,
0.84 times the maximum power output) because the Po MAX
equation accounts for the device standby power and device
variability.
...........
The driver stages (transistors ~ and Os) are emitter follower amplifiers which shift the voltage level between the
collectors of the differential-amplifier transistors and the
bases of the output transistors and provide the drive current
required by the output transistors.
The power transistors (Os and ~) are large, high current
devices capable of delivering peak currents greater than
0.25A. The emitters are made available to facilitate various
modes of operation or to permit the inclusion of emitter resistors for more complete stabilization of the idling current of
the amplifier. Inclusion of such resistors also reduces distortion by introducing negative feedback, but reduces the
power-output capability by limiting the available drive.
Inclusion of emitter resistors between terminals 5 and 6 and
ground also enhances the effectiveness of the internal OC
feedback supplied to the bases of transistors O2 and 0 3
through resistors Rs and R7. Any increase in the idling current in either output transistor is reflected as an increased
" '"
~ASE TEMPERATURE
o
25
~ !-- .w'BIENT TEMPERATURE
r-< r--
50
l..---'"
7&
~
-- r-- ~
100
125
150
17&
200
22&
TEMPERATURE ("el
FIGURE 3. DISSIPATION RATING OF THE CA3020 AND
CA3020A AS A FUNCTION OF CASE AND AMBIENT TEMPERATURES
Basic Class B Amplifier
Figure 4 shows a typical audio amplifier circuit in which the
CA3020 or CA3020A can provide a power output of 0.5W or
1W, respectively. Table 1 shows performance data for both
types in this amplifier. The circuit can be used at all voltage
and power output levels applicable to the CA3020 and
CA3020A.
11-22
Application Note 5766
The emitter-follower stage at the input of the amplifier in Figure 4 is used as a buffer amplifl8r to provide a high input
impedance. Although many variations of biasing may be
applied to this stage, the method shown is efficient and ec0nomical. The output of the buffer stage is applied to terminal
3 of the differential amplifl8r for proper balance of the pushpull drive to the output stages. Terminals 2 and 3 must be
bypassed for approximately 1000n at the desired low-frequency roll-off point.
, . - - - - - - - - - - - VCCI
Vccz
;,;;.;.;;.;;:+., (NOTE 1)
IO~UT
81N-
At low power 1eYe1s, the CI'OSSOY&r distortion of the class B
amplifier can be high if the idling current is low. For low crossover distortion, the idling current should be approximately
12mA to 24mA, depending on the effICiency, idling dissipation,
and distortion requirements of the particular application. The
idling current may be increased by connection of a jumper
between terminals 8 and 9. If higher levels of operating idling
current are desired, a resistor (R, ,) may be used to increase
the regulated voltage at terminal 11 by a slight amount with
additional current injection from the power supply VCC1 •
IflF
3V
NOTES:
1. Better coil and transformer OF108A, Thordarson TR-192, or
equivalent.
2. See text and tables.
In some applications, it may be desirable to use the input transistor
of the CA3020 or CA3020A for other purposes than
the basic buffer amplifier shown in Figure 4. In such cases,
the input }(; signal can be applied directly to terminal 3.
a,
FIGURE 4. BASIC CLASS B AUDIO AMPLIFIER CIRCUIT
USING THE CA3020 OR CA3020A.
TABLE 1. TYPICAL PERFORMANCE OF CA3020 AND
CA3020A IN CIRCUIT OF FIGURE 4 (NOTE)
CHARACTERISTIC
CA3020
CA3020A UNITS
Power Supply
Vcc,
9
9
V
Vccz
9
12
V
Zero-Signalldling Current
Icc,
15
15
rnA
Iccz
24
24
rnA
Icc,
16
16.6
rnA
Iccz
125
140
rnA
Maximum Power OUtput at
10%THD
550
1000
mW
Sensitivity
35
45
mV
Power Gain
75
75
dB
Input Resistance
55
55
kn
Efficiency
45
55
%
Signal-to-Noise Ratio
70
66
dB
% Total Harmonic Distortion at
3.1
3.3
%
The extended frequency range of the CA3020 and CA3020A
requires that a high-frequency }(; bypass capacitor be used
at the input terminal 3. Otherwise, oscillation could occur at
the stray resonant frequencies of the external components,
particularly those of the transformers. Lead inductance may
be sufficient to cause oscillation if long power-supply leads
are not properly }(; bypassed at the CA3020 or CA3020A
common ground point. Even the bypaSSing shown may be
insufficient unless good high-frequency construction practices are followed.
Figure 5 shows typical power output of the CA3020A at supply voltages of +3V, +6V, +9V, and +12V, and of the CA3020
at +6V and +9V, as measured in the basic class B amplifl8r
circuit of Figure 4. The CA3020A has higher power output
for all voltage supply conditions because of its higher peak
output current capability.
Maximum Signal Current
TA-+25"c
1200
/
#'
.....
150mW
Test Signal
1000Hzl6000 Generator
Equivalent CoJlector-to-Coilector
Load
130
200
0
Idling Current Adjust Resistor
(R,,)
1000
1000
0
o
NOTE: Integrated circuit mounted on a beat sink, Wakefield 209
Alum. or equivalent.
11-23
-
~~
B
-".., '"
~''''''''''' .....~
B'
.'....--- ..........
,
,
C'
200
o1/
-
z
I
~
o
-en
~w
r- ~
""
~~
D
100
200
300
400
COLLECTOR-TO-COLLECTOR LOAD RESISTANCE (Q)
FIGURE 5. POWER OUTPUT OF THE CA3020 AND CA3020A
AS A FUNCTION OF COLLECTOR-TO-COLLECTOR LOAD RESISTANCE Ace
~5
itz
Q.
c(
Application Note 5766
TABLE FOR FIGURE 5 CURVES
Vcc,- avo Yea - IV. RL _1000
IDLING
POWER SUPPLY
CURRENT (mA)
VOLTAGE (V)
CURVE
Icc:,
Iccz
Vcc,
Vea
(0)
-
A
9
10
9
12
00
B'
B
9
10
9
9
00
C'
C
7
6
6
6
00
-
0
8
8
3
3
220
CA3020 CA3020A
\
Ru
Figure 6 shows total harmonic distortion (THO) as a function
of power output for each of the voltage conditions shown in
Figure 5. The values of the collector-to-collector load resistance (Reel and the idling-current adjust resistor (R ll )
shown in the figure are given merely as a fixed reference;
they are not necessarily optimum values. Higher idling-current drain may be desired for low crossover distortion, or a
higher value of Rcc may be used for better sensitivity with
less power-output capability. Because the maximum power
output occurs at the same conditions of peak-current limitations, the sensitivities at maximum power output for the
curves of Figures 5 and 6 are approximately the same.
Increasing the idling current drain by reducing the value of
the resistor Rl1 also impro'l9s the sensitivity.
TA-+2Ii"C
I
B'
C' C
~
'\.
o
o
. /
J •••
l" ~
;
,.-
II
"
l"
'
B
.'
A
l
/
"
'/ l/ """.
"",
./
V
2
"4
"
8
•
.........
r-.....
10
..-.,
12
--- -
14
16
18
IDUNG CURRENT (mAl
FIGURE 7. TOTAL HARMONIC DISTORTION AS A FUNCTION
OF Iccz IDUNG CURRENT FOR A SUPPLY VOLTAGE OF 6V AND AN OUTPUT OF 100mW
Applications
Audio Amplifiers
The circuit shown in Figure 4 may be used as a highly efficient class B audio power output circuit in such applications
as communications systems. AM or FM radios, tape recorders, intercoms. and linear mixers. Figure 8 shows a modification of this circuit which may be used as a transformerless
audiO amplifier in any of these applications or in other portable instruments. The features of this circuit are a power output capability of 310mW for an input of 45mV. and a high
The idling-current drain of the
input impedance of
circuit is 24mA. The curves of Figure 5 may be used to
determine the value of the center-tapped resistive load
required for a specified power output level (the indicated
load resistance is divided by two).
so.ooon
./
100 200 300 400 500 800 700 800
POWER OUTPUT (mW)
o
o
Ru - VARIABLE, TA - +25"C
900 1000
FIGURE 6. TOTAL HARMONIC DISTORTION OF THE CA3020
OR CA3020A AS A FUNCTION OF POWER OUTPUT
500K
TABLE FOR FIGURE 6 CURVES
CURVE
CA3020 CA3020A
IDUNG
CURRENT
(mA)
POWER
SUPPLY
VOLTAGE (V)
5.1K
Rcc
Ru
(0)
(0)
1300 SPEAKER
OR EQUIVALENT
-
A
15
24
9
12
200
1000
B'
B
15
24
9
9
150
1000
C'
C
12
14
6
6
100
1000
-
0
9
9
3
3
50
220
FIGURE 8. 310mW AUDIO AMPUFIER WITHOUT TRANSFORMERS
Figure 7 illustrates the improvement in crossover distortion
at low power levels. Distortion at 100mW is shown as a function of idling current 1CC2 (output stages only). There is a
small improvement in total harmonic distortion for a large
increase in idling current as the current level exceeds 15mA.
The CA3020 or CA3020A provides several advantages
when used as a sound output stage or as a preamplifier
driver in communications equipment because each type is a
compact and low power drain circuit. The squelching
requirement in such applications is simple and economical.
11-24
Application Note 5766
...-----..
Figure 9 shows a practical method of providing squelch to
the CA3020 or CA3020A. When the squelch switching transistor
is in the "on" state, the CA3020 or CA3020A is 'off"
and draws only fractional idling dissipation. The only current
that flows is that of the buffer-amplifier transistor 0 1 in the
integrated circuit and the saturating current drain of
For
a circuit similar to that of Figure B, the squelched condition
requires an idling current of approximately 7mA, as compared to a normal idling-current drain of 24mA.
as
+8V
as.
5OOK=
".
T1: Primary 40, Secondary 25,0000;
Stancor A4744 or equivalent.
T2: Beller coil and transformer OF1084, Thordarson TR-192, or
equivalent
Speakers: 40
Os COLLECTOR
. / LOAD UNE RIO OR
•••••• ~
RIO + Ru OF CA3020
••••••• •••.·OFF"
FIGURE 10. INTERCOM USING CA3020 OR CA3020A
DlFF AMP TERMINAL 11
OPERATING VOLTAGE
Wide-Band Amplifiers
FIGURE9B.
FIGURE 9. METHOD OF APPlYING SQUELCH TO THE CA3020
OR CA3020A TO SAVE IDLING DISSIPATION
In applications requiring high gain and impedance matChing,
the CA3020 or CA3020A can be adapted for use without
complex circuit modifications. Detectors having low signal
outputs or high impedances can be easily matched to the
input of the CA3020 or CA3020A buffer amplifier. The typical
integrated circuit input impedance of 55kn may be too low
for crystal output devices, but the sensitivity may be sacrificed to impedance match at the input while still providing
adequate drive to the CA3020 or CA3020A. Both types may
be used in tape recorders as high-gain amplifiers, bias oscillators, or record and playback amplifiers. The availabil~y of
two input terminals permits the use of the CA3020 or
CA3020A as a linear mixer, and thus adds to its flexibility in
systems that require adaptation to multiple functions, such
as communications equipment and tape recorders.
Figure 10 illustrates the use of the audio amplifier shown in
Figure 4 in an intercom in which a listenltalk position switch
controls two or more remote poSitions. Only the speakers,
the switch, and the input transformer are added to the basic
audio amplifier circu~. A suitable power supply for the
intercom could be a 9V battery used intermittently rather
than continuously.
A major general-purpose application of the CA3020 and
CA3020A is to provide high gain and wide-band amplification. The CA3020 and CA3020A have typically flat gainbandwidth response to BMHz. Although the circuits are normally biased for class B operation, only the output stages
operate in this mode. If proper DC bias conditions are
applied, the output stages may be operated as linear class A
amplifiers.
Figure 11 shows the recommended method for achieving an
economical and stable class A bias. The differential amplifier
portion of the CA3020A is placed at a potential above
ground equal to the base-emitter voltage VeE of the integrated circu~ transistors (O.5V to O.7V). In this condition, the
output stages have an emitter-current bias approximately
equal to the base-to-emitter voltage divided by the emitterto-ground resistance. The circuit in Figure 11 is a wide-band
video amplifier that provides a gain of 38dB at each of the
push-pull outputs, or 44dB in a balanced output connection.
The adB bandwidth of the circuit is 30Hz to SMHz. Higher
gain-bandwidth performance can be achieved if the diodeto-ground voltage drop at terminal 12 is reduced. The lower
voltage drop permits the use of a higher ratio of output-stage
collector-to-emitter resistors without departure from the
desired portion of the class A load line. It is important to note
that the temperature coefficient of the terminal 12-to-ground
reference element should be sufficiently low to prevent a
large change in the current of the output stages.
11-25
Application Note 5766
output transistor Q 8 help to form an isolating shield between
the input at terminal 3 and the output at terminal 7. This cascade of amplifMlrS has a single phase inversion at the output
for much better stability than could be achieved if terminal 4
were used as the output and terminal 3· as the input.
,..-,....-,....,....--- +12V
771nA
INVERTED
.....+-'-oOUTPUT
38dB GAIN
PER SIDE
BW-8MHz
INPUT 0-:, +
Figure 13 illustrates the use of the CA3020 or CA3020A as a
class A linear amplifier. This circuit features a very low output
impedance and may be used as a line driver amplifier for wideband applications up to SMHz. The circuit requires a 0.12V
peak-te-peak input for a single ended output of 1V or a balanced peak-te-peak output of 2V from a 30 output impedance
at each emitter. The input impedance is specified as 78000,
but is primarily a function of the external 10,0000 resistor that
provides bias to Q1 from the regulating terminal 11.
_ s...,
-
---'===:::;-ir. .
r-
3V
+8V
SOmA
FIGURE 11. WIDE-BAND VIDEO AMPUFIER ILLUSTRATING
ECONOMICAL AND STABLE CLASS A BIAS OF
CA3020A
The same method for achieving class A bias is used in the
large signal swing output amplifier shown in Figure 12.
OUTPUT
+18V
30mA
t---'=-OUTPUT
FIGURE 13. CLASS A UNEAR AMPUFIER USING CA3020 OR
CA3020A
Figure 14 illustrates the practical use of the CA3020 or
CA3020A as a tuned amplifier. This circuit uses DC biasing
similar to that shown previously, and ha.s a gain of 70dB at a
frequency of 160kHz. The CA3020 or CA3020A can be used
as a tuned RF amplifier or oscillator at frequencies well
beyond the SMHz bandwidth of the basic circuit.
260tLF
3V
,..---1r-----+8V
r---r-,
FIGURE 12. LARGE SIGNAL SWING OUTPUT AMPUFIER USING CA3020 OR CA3020A
Either the CA3020 or the CA3020A may be used in this circuit
with power supplies below + 18V; the CA3020A can also be
used with B+ voltages up to 25V with non-inductive loads. The
circuit of Figure 12 provides a gain of SOdB and a bandwidth
of 3.2MHz if the output transistor ~ has a bypassed emitter
resistor. With an unbypassed output emitter resistor, the gain
is 40dB and the bandwidth is 8MHz. The output stage can
deliver a 5VRMS signal when a supply of +18V is used. For
better performance in this type of circuit, the input signal is
coupled from the buffer amplifier Q 1 to the input terminal 3 of
the differential amplifier. This arrangement provides higher
gain because the collector resistor of the differential-amplifier
transistor Q 3 is larger than that of Q2. (This difference results
from a requirement of differential drive balance that is not
used in this circuit.) In addition, the terminals of the unused
~mA
O.OOlI'F
+--+-oO OUTPUT
70dB GAIN
AT 160kHz
FIGURE 14. 160KHz TUNED AMPUFIER USING THE CA3020 OR
CA3020A
11-26
Application Note 5766
Driver Amplifiers
The high power-pin and power-output capabilities of the
CA3020 and CA3020A make these integrated circuits highly
suitable for use as drivers for higher power stages. In most
applications, the full power output capabilHy of the circuit is
not required, and large emitter resistors may be used in the
output stage to reduce distortion. The CA3020 and
CA3020A can drive any transformer coupled load within
their respective ratings. Sewral examples of typical applications are given below.
Figure 15 illustrates the use of the CA3020 or CA3020A to
drive a germanium power output transistor to a 2.5W level.
Because the integrated circuit is required to deliver a maximum power output of less than 5OmW, an unbypassed emHter
resistor can be used in the output stage to reduce distortion.
Sensitivity for an output of 2.5W is 3mV; this figure can be
improwd at a slight increase in distortion by reduction of the
4.70 resistors between terminals 5 and 6 and ground.
Because so little of the power output capability of the
CA3020 or CA3020A is used, higher power class B stages
can easily he accommodated by selection of suitable output
transistors and appropriate transformers.
Figure 16 shows a medium power class B audio amplifier in
which the CA3020 or CA3020A is used as a driver. The output stage uses a pair of TO-3-type germanium output transistors which must be mounted on a heat sink for reliable
operation. Idling current for the entire system is 70mA from
the 35V supply. Sensitivity Is 10m V for an output of lOW.
Motor Controller and Servo AmplHler
The CA3020 or CA3020A may he used as a 40Hz to 400Hz
motor controller and servo amplifier, as shown in Figure 17.
r - - - - 1 -___t--Nlf-t---....- -......- - +12V
600mA
3110
1.5
2N2868r.ZN301
ii@J
4.7K
4Q SPEAKER
Tl: primary impedance, 10,0000; center-tapped at 1600; primary direct current, 2mA; Thordarson TR-207 (entire secondary), or equivalent
T2: primary Impedance, 20Q;primary direct current, 0.6A; secondary, 405; Thordarson TR-304, Stancor TP62, or equivalent
FIGURE 15. 2.5W CLASS A AUDIO AMPLIFIER USING THE CA3020 OR CA3020A AS A DRIVER AMPLIFIER
z
o- I / )
!;(w
(,)1-
-0
~Z
~
11-27
Application Note 5766
2N2868/2N301
SOCIttF
25V
1 +
~
IClSPEAKER
4.7K
2N2868/2N301
=
T1: primary Impedance, 4,OOOQ; center-tapped; secondary Impedance, 6000; center-tapped, spilt; Thordarson TR-454 or equivalent.
FIGURE 16. 10W SINGLE·ENDED CLASS B AUDIO AMPUFIER USING THE CA3020 OR CA3020A AS A DRIVER AMPUFIER
'7mA IDUNG
+10Voc AT { 52mAFULLSIGNAL
100I'F
10V
r
_
+18VocAT
{20mA IDUNG
5.7AFULLSIGNAL
+S.SV
~+·
120V_
0.245A,2Wt
AT 4OHHOOHz
+IV
1001'f
10V
IIC~soon
+ •
0.18Vp.pAT
40Hz TO 400Hz
4.7K
0.1
1W
I'f
FIGURE 17. MOTOR CONTROUER AND SERVO AMPUFIERR USING CA3020 OR CA3020A
11-28
Harris Semiconductor
--
--
-- ----- ---- ----- --===:.
- -=- --- - - - -
.=-===-;;-===
No. AN6048.1
=
==
==
Harris Intelligent Power
Apri11994
SOME APPLICATIONS OF A PROGRAMMABLE
POWER SWITCH/AMPLIFIER
Authors:
LA. Campbell and H.A. Wittlinger
The CA3094 unique monolithic programmable power switch!
amplifier IC consists of a high-gain preamplifier driving a
power-output amplifier stage. It can deliver average power of 3
watts of peak power of 10W to an external load, and can be
operated from either a single or dual power supply. This Note
briefly describes the characteristics of the CA3094, and illustrates its use in the following circuit applications:
Circuit Description
The CA3094 series of devices offers a unique combination
of circuit flexibility and power-handling capability. Although
these monolithic ICs dissipate only a few microwatts when
quiescent, they have a high current-output capability (1 OOmA
average, 300mA peak) in the active state, and the premiumgrade devices can operate at supply voltages up to 44V.
• Class A Instrumentations and Power Amplifiers
• Class A Driver-Amplifier for Complementary Power Transistors
• Wide Frequency Range Power Multivibrators
• Current- or Voltage Controlled Oscillators
• Comparators (Threshold Detectors)
• Voltage Regulators
• Analog Timers (Long Time Delays)
• Alarm Systems
• Motor-Speed Controllers
• Thyristor Firing Circuits
• Battery Charger Regulator Circuit
• Ground Fault Interrupter Circuits
Figure 1 shows a scematic diagram of the CA3094. The portion of the circuit preceding transistors 012 and 013 is the
preamplifier section and is generically similar to that of the
CA3080 Operational Transconductance Amplifier (OTA) [1,21.
The CA3094 circuits can be gain-programmed by either digital and/or analog signals applied to a separate AmpliflerBias-Current (IABC) terminal (No.5 in Figure 1) to control circuit sensitivity. Response of the amplifier is essentially liner
as a function of the current at terminal 5. This additional signal input ·porf provides added flexibility in may applications.
Thus, the output of the amplifier is a function of input signals
applied differentially at terminals 2 and 3 and/or in a singlyended configuration at terminal 5. The output portion of the
monolithic circuit in the CA3094 consists of a Darling connected transistor pair with access provided to both the collector and emitter terminals to provide capability to ·sink"
and/or ·source" current.
INPUTS
OUTPUT
MODE
Rt
2110
AMPUFIER
6
2
3
8
3
2
}---_--I::"
"SOURCE"
(DRIVE)
OUTPUT
FIGURE 1. CA3094 CIRCUIT SCHEMATIC DIAGRAM
Copyrlght@Harris Corporation 1994
11-29
NONINY
"SInk"
2
BIAS INPUT 5
IASC
INY
"Source·
DlFF.
VOLTAGE
INPUT
OUTPUT
TERM
Application Note 6048
The CA3094 series of circuits consists of six types that differ
only in voltage-handling capability and package options, as
shown below; other electrical characteristics ar identical.
PACKAGE OPTIONS
MAXIMUM VOLTAGE RATING
CA3094S,CA3094T
24V
CA3094AS,CA3094AT
36V
CA3094BS, CA3094BT
44V
The suffix ·S· indicates circuits packaged in TO-5 enclosures
with leads formed to an 8 lead dual in line configuration (0.1
inch pin spacing). The suffix or indicates circuits packaged
in 8 lead TO-5 enclosures with straight leads. The generic
CA3094 type designation is used throughout the Note.
Class A Instrumentation Amplifiers
One of the more difficult instrumentation problems frequently
encountered is the conversion of a differential input signal to
a single-ended output signal. Although this conversion can
be accomplished in a straightforward design through the use
of classical op-amps, the stringent matching requirements of
resistor ratios in feedback networks make the conversion
particularly difficult from a practical standpoint. Because the
gain of the preamplifier section in the CA3094 can be
defined as the product of the transconductance and the load
resistance (gm RLl, feedback is not needed to obtain predictable open-loop gain performance. Figure 2 shows the
CA3094 in this basic type of circuit.
The gain of the preamplifier section (to terminal NO.1) is 9m
RL (5 x 10-3) (36 x 103) .. 180. The transconductande 9m is
a function of the current into terminal No.5, 1"80 the amplifier-bias-currenL In this circuit an I"BC of 260jJA results in a gm
of 5mS. The operating point of the output stage Is controlled
by the 2kO potentiometer. With no differential input signal
(eDiFF .. 0), this potentiometer is adjusted to obtain a quiescent output current 10 of 12mA. This output current is established by the 5600 emitter resistor, RE' as follows:
=
10""
(gmRL) (e DIFF)
RE
Under the conditions described, an input swing 90lFF of ±26mV
produces a variation in the output current 10 of ±8.35mA. The
nominal quiescent output voltage is 12mA times 560Q or 6.7V.
This output lewl drifts approximately -4mv, or -0.0595%, tor
each OC change in temperature. Output drift is caused by temperature induced variations in the base emitter IIOltage of the
two output transistors, 012 and 013.
DIFFERENTIAL
THERMOCOUPLE
,......---,
NOTE:
1. Set to optimize CMRR.
FIGURE 3. SINGLE SUPPLY DIFFERENTIAL BRIDGE AMPUFIER
36/en
40V
NOTES:
1. Preamp gain (Ay) = g", RL = (5) (10-3) (36) (10"') = 180
(OUtput at terminal 1).
2. For linear operation: Differential Input sl ±26mV I
(With approx. 1% deviation from linearity).
3. OUtput vottage (Eo) = Ay (±eOIFF) = (180) (±26mV) = ±4.7V
4.
4.7V
10 ""
5600
= 8.35mA
FIGURE 2. OPEN LOOP INSTRUMENTATION AMPLIFIER
WITH DIFFERENTIAL INPUT AND SINGLE ENDED
OUTPUT
11-30
FIGURE 4. SINGLE SUPPLY AMPLIFIER FOR THERMOCOUPLE SIGNALS
Application Note 6048
Figure 3 shows the CA3094 used in conjunction with a resistive-bridge input network; and Figure 4 shows a single-supply amplifier for thermocouple signals. The AC networks
connected between terminals 1 and 4 in Figure 3 and Figure
4 provide compensation to assure stable operation.
between terminals 8 and 3 the 1kO resistor connected to terminal 3. Phase compensation is provided by the 680pF
capacitor connected to terminal 1.
R
101cn
-v~+v
The components of the AC network are chosen so that
_1_=2MHz
2ltAC
OEN. RADIO
TYPE 184O-A
OUTPUT POWER
METER OR
EQUIVALENT
Class A Power Amplifiers
The CA3094 is attractive for power-amplifier service
because the output transistor can control current up to
100mA (300mA peak). the premium devices.
CA3094B can operate at supply voltages up to 44V. and the
TO-S package can dissipate power up to 1.6W when
equipped with a suitable heat sink that limits the case temperature to SsoC.
11cn
-v
Figure S shows a Class A amplifier circuit using the CA3094A
that is capable of delivering 280mW to a 3500 resistive load.
This circuit has a voltage gain of 60db and a 3db band width
of about SOkHz. Operation is stable without the use of a
phase-compensation network. Potentiometer A is used to
establish the quiescent operating point for class A operation.
TYPICAL DATA
R
-15V
~ +15V
+1SV
10kn
DEVICE
DISSIPATION
625MW
1.5W
R8
3OkO
4OkO
V+
+7.SV
+10V
V-
-7.SV
-10V
Re
SOO
450
600mW
Po
220mW
THO
0.4%
1.4%
RP
3100
1280
FIGURE 6. CLASS A AMPUFIER WITH TRANSFORMER
COUPLED LOAD
Class A Driver Amplifier for
Complementary Power Transistors
1000
-15V
FIGURE 5. CLASS A AMPLIFIER -280mW CAPABILITY INTO A
RESISTIVE LOAD
The circuit of Figure 6 illustrates the use of the CA3094 in a
class a power-amplifier circuit driving a transformer-coupled
load. With dual power supplies of +7.SV and -7.SV. a base
resistor AB of 301<0, and an emitter resistor AE of Son.
CA3094 dissipation is typically 62SmW. With supplies of
+ 1OV and -1 OV. AB of 401<0, and AE of 4SO, the dissipation is
1.SW. Total harmonic distortion is 0.4% at a power output
level of 220mW with a reflected load resistance Ap of 31 on.
and is 1.4% for an output of 600mW with an Rp of 128Q. The
setting of potentiometer A establishes the quiescent operating point for class A operation. The 1kn resistor connected
between terminals 6 and 2 provides DC feedback to stabilize
the collector current of the output transistor. The AC gain is
established bye the ratio of the 1MO resistor connected
The CA3094 configuration and characteristics are ideal for
driving complementary power-output transistorspl a typical
circuit is shown in Figure 7. This circuit can provide 12W of
audio power output into an 80 load with intermodulation distortion (IMO) of 0.2% when 60Hz and 2kHz signals are
mixed in a 4:1 ratio. Intermodulation distortion is shown as a
function of power output in Figure 8.
z
o
-0
!ccw
()I-
The large amount of loop gain and the flexibility of feedback
arrangements with the CA3094 make it possible to incorporate the tone controls into a feedback network that is closed
around the entire amplifier system. The tone controls in the
circuit of Figure 7 are part of the feedback network connected from the amplifier output ijunction of the 3300 and
470 resistors driven by the emitters of Q2 and Q3) to terminal 3 of the CA3094. Figure 9 shows voltage gain as a function of frequency with tone controls adjusted for "liar
response and for responses at the extremes of tone-control
rotation. The use of tone controls incorporated in the feedback network results in excellent signal to noise ratio. Hum
and noise are typically 700ILV (83db down) at the output.
11-31
-0
~z
Q.
ocr:
Application Note 6048
In addition to the savings resutting from reduced parts count
circuit size, the use of the CA3094 leads to further savings in
the power supply system. Typical values of power supply
rejection and common mode rejection are 90db and 100db,
respectively. An amplifier with 40db gain and 90db power supply rejection would require a 31 mV power-supply ripple to produce 1mV of hum at the output. Therefore, no fittering is
required other than that provided by the energy storage capacitors at the output of the rectifier system shown in Figure 7.
For application in which the operating temperature range is
limited (e.g., consumer service the thermal compensation
network (shaded area) can be replaced by a more economical configuration consisting of a resistor diode combination
(8.20 and 1N5391) as shown in Figure 7.
Power Multivibrators (Astable and
Monostable)
the CA3094 is suitable for use in power multivibrators
because its high current output transistor can drive low
impedance circuits while the input circuitry and the frequency determining elements are operating at micropower
levels. A typical example of an astable multivibrator using
the CA9034 with a dual power supply is shown in Figure 10.
The output frequency fOUT is determined as follows:
f
OUT
1
= 2RC IN [(2R1/R2)
+ 1]
If R2 is equal to 3.08 R1, then fOUT is simply the reciprocal of RC.
TREBLE
D1 - D4 1N5381
""."----_~
120V
60Hz
STANCOR
NO. P _
OR EQUIVALENT
(~~~T~~1A)
tOPTIONAL THERMAL
COMPENSATION
NETWORK
25""
Cz
1kn
0.47""
"BOOST"! 00k.Q
(CW)
"CUT"
(cCW)
10kn
JUMPER
BASS
} ••2n
f
1N5381
TYPICAL PERFORMANCE DATA FOR 12W AUDIO AMPUFIER CIRCUIT
Power Output (an load, Tone Control set at "Flar)
Musk: (at 5% THO, regulated supply) ••••••••••••••••••• 15W
Continuous (at 0.2% IMD, 60Hz and 2kHz
mixed In a 4:1 ratio, unregulated supply)
See Rgure 8 In AN6048 ••••.•••••••••••••••••••••.•• 12W
Totai Harmonic Distortion
At 1W, unregulated supply ......................... 0.05%
At 12W, unregulated supply ........................ 0.57%
Voltage Gain ....................................... 4OdB
Hum and Noise (below continuous power output) •••.••••••• 83dB
Input Resistance ................................... 2501<0
Tone Control Range .................. See Figure 9 In AN6048
NOTES:
1. For standard input Short ~ Rl = 25OkO, C1 = 0.04711f; rernow R.z.
2. For ceramic cartridge Input: C1 = 0.00471lF, Rl = 2.5Mn, remove jumper from ~; leave R2,
FIGURE 7. 12W AUDIO AMPUFIER CIRCUIT FEATURING TRUE COMPLEMENTARY SYMMETRY OUTPUT STAGE WITH CA3094
IN DRIVER STAGE
11-32
Application Note 6048
lz
~
~i!5
~
3
S
series of circuits can supply peak-power output in excess of
lOW when used in this type of circuit. The frequency of oscillation fose is determined by the resistor rations, as follows:
UNREGULATED SUPPLY LOAD IIQ
2.0
I
•
1.1
1.1
1.4
I
=
'OSC
(2RCln) [(2Rl/R2) + 1]
1.2
where:
1.0
"
0.1
I
10Hz AND 12kHz .......
10Hz AND 2kHz ~"
0.1 II: 0.4 _
:Ii
Rl
=
IIOHZ~D7kHz
I!!
~--------------~-'--------~+V
iii!: 0.2
NO. 57
o
2
4
&
10
8
12
14
POWER OUTPUT (W)
R2
lIMn
FIGURE 8. INTERMODULATION DISTORTION va POWER OUTPUT
&0
~
56
50
35
~
30
25
w
:.J
g
"
40
~
CI
./
TREBLE~I
,
L
12Mn
~
10
Rs
I
;I'
FLAT
r.....
~
~
NOTES:
"""'-I.
1. 1 RashISec.
,_
TREBLE CUT
20
15
I-
.......
:Ii" 45
~
BASS BOOST
~
OSC -
BASS CUT
II
I
(2RCln) [(2Rl/R2) + 1]
where:
RARe
2468
2468
2411
2468
10
100
1000
10K
lOOK
FREQUENCY (Hz)
Rl
FIGURE 9. VOLTAGE GAIN V8 FREQUENCY
= RA +Re
2. 25% Duty Cycle
0'
V+ from BV - 15V DC
FIGURE 11. ASTABLE MULTlVlBRATOR USING SINGLE SUPPLY
3. Frequency Independent
+15V
lkO
51kO
R2
43kO
Rl
OUTPUT
'OUT- 5kHz
-:!-
FIGURE 10. ASTABLE MULTlVlBRATOR USING DUAL SUPPLY
Figure 11 is a single supply astable multivibrator circuit
which illustrates the use of the CA3094 for flashing an incandescent lamp. With the component values shown, this circuit
produces one flash per second with a 25% 'on" time while
delivering output current in excess of l00mA. During the
75% ·off" time it idles with micropower consumption. The
flashing rate can be maintained with in ±2% of the nominal
value over a battery voltage range from 6V to 15V and a
temperature excursion from OOC to 7oDC. The CA3094
FIGURE 12_ ASTABLE POWER MULTIVIBRATOR WITH PROVISIONS FOR VARYING DUTY CYCLE
Provisions can easily be made in the circuit of Figure 11 to
vary the multivibrator pulse length while maintaining an
essentially constant pulse repetition rate. The circuit shown
11-33
Application Note 6048
in Figure 12 incorporates a potentiometer Rp for varying the
width of pulses generated by the astable multivibrator driving
light emitting diode (LED).
Figure 13 shows a circuit incorporating independent controls
(RoN and Rot=F) to establish the "on" and "off" periodS of the
current supplied to the LED. The network between points "A"
and "S" is analogous in function to that of the 1OOkn resistor R
in Figure 12.
+3OV
47kn
show oscillator frequency as a function of IABC for a current
controlled oscillator for two different values of capacitor C in
Figure 15. The addition of an appropriate resistor (R) in series
with terminal 5 in FlQure 15 convarts the circuit into a dage
controlled oscillator. Linearity with respect to either current or
vottage control is within 1% over the middle half of the characteristics. HoweII9r. variation in the symmetry of the output
pulses was a function of frequency is an inherent characteristic
of the circuit in FlQure 15. and leads to distortion when this circuit is used to drive the phase detector in phase-Iocked-Ioop
applications. This type distortion can be eliminated by interposing an appropriate flip-ffop between the output of the oscillator
and the phase locked discriminator circuits.
r - - - - - - - - - - - 1 P - - -.....-
.. +15V
47kn
OUTPUT
47kn
47kn
FIGURE 13. ASTABLE POWER MULTIVIBRATOR WITH PROVISIONS FOR INDEPENDENT CONTROL OF LED
"ON-OFF" PERIODS
The CA3094 is also suitable for use in monostable multivibrators as shown in Figure 14. In essence. this circuit is a
pulse counter in which the duration of the output pulses is
independent of trigger pulse duration. The meter reading is a
function of the pulse repetition rate which can be monitored
with the speaker.
OR
VOLTAGE INPUT
FIGURE 15. CURRENT OR VOLTAGE CONTROllED OSCIlLATOR
-
SUPPLY VOLTAGE V+ .15V
500 C • 1000pF TERMINAL NO. 3 TO GND IN FIGURE 15 _
AMBIENT TEMPERATURE TA • +25°C
1400
+5V
~
220kn
~
IE
~
/
./
300
1/
IL
200
./
./
100
./
,/
o
100
200
300
400
500
100
AMPUFIER BIAS CURRENT \ILAl
FIGURE 16. FREQUENCY AS A FUNCTION OF IABC FOR
C. 1000pF FOR CIRCUIT IN FIGURE 15
TRIGGER
INPUT
It;
>--l~_---J
100pF
1V
n
OV..J
L...
t Full Scale Dellection = 83P/s
SUPPLY VOLTAGE V+ .15V
I500 C.1 OOOpF TERMINAL NO. 3 TO GND IN FIGURE 15 I AMBIENT TEMPERATURE TA. ~c
-
400
zw 300
8w
FIGURE 14. POWER MONOSTABLE MULTIVIBRATOR
~
200
......
IE
./
100
Current or Voltage Controlled Oscillators
/
Because the transconductance of the CA9034 varies linearly
as a function of the amplifier bias current (IABC) supplied to terminal 5. the design of a current or vottage controlled oscillator is
straightforward. a shO'Nll in Figure 15. Figure 16 and Figure 17
o
100
200
300
400
500
AMPUFIER BIAS CURRENT \ILAl
100
FIGURE 17. FREQUENCY AS A FUNCTION OF IABC FOR
C. 100pF FOR CIRCUIT IN FIGURE 15
11-34
Application Note 6048
Comparators (Threshold Detectors)
Upper Trip Polot = 30 (
Comparator circuits are easily implemented with the
CA43094, as shown by the circuits in Figure 18. The circuit of
Figure 18A is arranged for dual supply operation; the input
vo~age exceeds the positive threshold, the output vo~age
swings essentially to the negative supply voHage rail (it is
assumed that there is negligible resistive loading on the out·
put terminal). an input vo~age that exceeds the negative
threshold value resuHs in a poSitive YOItage output essentially
equal to the positive supply vo~ge. The circuit in Figure 188,
connected for single supply operation, functions similarly.
r-.......- -.......-
Lower Trip Polot
==
R3
R1
+ R2 + R3 )
R3
(30 - D.026R 1) - - R2+R3
The circuit is applicable, for example, to automatic ranging.
With the values shown in Figure 20, the relay coil is energized
when the input exceeds approximately 5.9V and remains ener·
gized until the input signal drops below approximately 5.5V.
... +1SV
± THRESHOLD.
tSUPPLY)~R1 :1Ri)
1.51eO 51eO
-15V
+--'lM+-<
OUTPUT
INPuT>-1......
r!:
ELOW
FIGURE 18A. DUAL SUPPLY
10k0
J-.............-OUTPUT
FIGURE 19. DUAL UMIT THRESHOLD DETECTOR
[
]~
[R1
RB)
~R1+RB}
]
+3OV
R1
1000
12V
I2n
4500
COIL
6200
FIGURE 188. SINGE SUPPLY
FIGURE 18. COMPARATORS (THRESHOLD DETECTORS)
DUAL AND SINGLE SUPPLY TYPES
INPUT
-(J)
~w
(,,)1-
-0
KZ
Figure 19 shows a dual limit threshold detector circuit in
which the high level limit is established by potentiometer R1
and the low level limit is set by potentiometer R2 to actuate
the CA30SO low limit detector.[1, 2) A poSitive output signal
exceeds either the high limit or the low limit values established by the appropriate potentiometer settings. This output
voltage is approximately 12V with the circuit shown.
The high current handling capability of the CA3094 makes it
useful in Schmitt power trigger circuits such as that shown in
Figure 20. In this Circuit, a relay coil is switched whenever
the input signal traverses a prescribed upper or lower trip
point, as defined by the following expressions:
Z
0
R2
241eO
R3
5.e1eO
1001eO
FIGURE 20. PRECISION SCHMm POWER TRIGGER CIRCUIT
11-35
c..
---i==~=:';~~
10kn
±1%
NOTES:
Timers
The programmability feature inherent in the CA3094 (and
operational transconductance amplifiers in general) simplifies
the design of presettable timers such as the one shown in
Figure 23. Long timing intervals (e.g. up to 4hrs) are achieved
by discharging a timing capacitor C1 into the signal input
terminal (e.g. No.3) of the CA3094. This discharge current is
controlled precisely by the magnitude of the amplifier bias
current IABC programmed into terminal 5 through a resistor
selected by switch S2. Operation of the circuit is initiated by
charging capacitor C1 through the momentary closing of switch
S1. Capacitor C 1 starts discharging and continues discharging
until voltage E1 is less than voltage E2. The differential input
transistors in the CA3094 then change state, and terminal 2
draws sufficient current to reverse the polarity of the output
1. V+ Input range = 19V to aov lor 15V output
2. V-Input range = -16 to -30Vfor -15V output
3. REGULATION:
IN
MAX UNE
=
MAXUNE
=V
OUT
[VOUT (INITIAL)}WIN
x 100
4VOUT
(INITIAL) xloo
0.075% VOUT
OUT
(IL FROM 1rnA to SOmA)
=
FIGURE 21. DUAL VOLTAGE TRACKING REGULATOR
.
188Mn
(NINE 22MO RESISTORS IN SERIES)
+4V
FIGURE 22. REGULATED HIGH VOLTAGE SUPPLY
11-36
= 0.075%IV
.
........
=
RL
.
.-~--.
•
Application Note 6048
wltage (terminal 6). Thus, the CA3094 not only has provision
for readily presetting the time delay, but also provides
significant output current to drive control devices such as
thyristors. Resistor RS limits the initial charging current for C1.
Resistor RS limits the initial charging current for C1. Resistor
R7 establishes a minimum wltage of at least 1V at terrninal2 to
Insure operation within the common mode input range of the
device. The diode limits the maximum difl9rential input wltage to
Sv. Gross changes In time range selection are made with switch
52, and vernier trimming adjustments are made with
potentiometer R6.
+9-~-------1------~-----------,
120V
AI;
aov
DC
R7
40528 TURNS "OFP' AFTER
EXPIRATION OF TIME DELAY
TIME
3Min
30Min
2Hrs
4Hrs
RESISTOR VALUE
A1 =O.5MO
A5=2.7ka
R2=5.1MO
A6=50ka
A3=22MO
A7=2.7ka
R4=44MD
A8 = 1.5ka
Alarm Circuit
Figure 2S shows an alarm circuit utilizing two "senor" lines.
In the "no-alarm" state, the potential at terminal S (lASe) is
driven with sufficient current though resistor RS to keep the
output voltage "high". If either "sensor" line is opened,
shorted to ground, or shorted to the other sensor line, the
__________________
~
~
V
~
FIGURE 23. PRESETTABLE ANALOG TIMER
__________________
~
COMMON
In some timer applications, such as that shown in Figure 24,
a meter readout of the elapsed time is desirable. This circuit
uses the CA3094 and CA3083 transistor array/5) to control
the meter and a load switching triac. The timing cycle starts
with the momentary clOSing of the start switch to charge
capacitor C1 to an initial wltage determined by the 50kn
vernier timing adjustment. During the timing cycle the output
of the CA3094, which is also the collector voltage of 01, is
"high". The base drive for 01 is supplied from the positive
supply through a 91kn resistor. The emitter of 01, through
the 7SQ resistor, supplies gate-trigger current to the triac.
Diode connected transistors 04 and OS are connected so
that transistor 01 acts as a constant current source to drive
the triac. As capacitor C1 discharges, the CA3094 output
voltage at terminal 6 decreases until it becomes less than
the VCESAT of 01. At this point the flow of drive current to the
triac ceases and the timing cycle is ended. The 20kn resistor between terminals 2 and 6 of the CA3094 is a feedback
resistor. Diode connected transistor Q2 and 03 and their
associated networks serve to compensate for non-linearities
in the discharge circuit network by bleeding corrective current into the 20kn feedback resistor. Thus, current flow in
the meter is essentially linear with respect to the timing
period. The time periods as a function of R1 and indicated
on the Time-Range Selection Switch in Figure 24.
22MQ
5.1kn
TIME RANGE
SELECTION SWITCH
II1kn
~V
MT1
sakn
I.llcO
sakn
FIGURE 24. PRESETTABLE TIMER WITH UNEAR-READOUT
11-37
Application Note 6048
output goes "low" and activates some type of alarm system.
The back-to-back diodes connected between terminals 2
and 3 protect the CA3094 input terminals against excessive
differential voltages.
~------~------~~--1
RS
+12V
R4
100kO
100kO
_--
,....
.... -- ..
• L-...---li-t+-..,,,.,........-<
: SENSOR •
• UNES :
The seA conduction, in turn, is controlled by the time duration of the positill9 Signal supplied to the seA by the phase
comparator. The magnitude of the positill9 de voltage supplied to terminal 3 of the phase comparator depends on
motor-speed error as detected by a circuit such as that
shown in Figure 27. This de voltage is compared to that of a
fixed amplitude ramp wave generated synchronously with
the ac line voltage frequency. The comparator output at terminal 6 is "high" (to trigger the seA into conduction) during
the period when the ramp potential is less than that of the
error voltage on terminal 3. The motor current conduction
period is increased as the error voltage at terminal 3 is
increased in the positill9 direction. Moter-speed accuracy of
±1% is easily obtained with this system.
Motor-Speed Error Detector
R3
150kO
FIGURE 25. ALARM SYSTEM
Motor-Speed Control/er System
Figure 26 illustrates the use of the CA3094 in a motor-speed
controller system. Circuity associated with rectifiers 01 and D2
comprises a full wave rectifier which dewlops a train of halfsinusoid voltage pulse to power the de motor. The motor speed
depends on the peak value of the half-sinusoids and the period
of time (during each haif cycle) the SCA is conductive.
Figure 27A shows a motor-speed error detector suitable br use
with the circuit of FlQure 26. A CA3080 operational transconductance amplifier is used as a voltage comparator. The reference for the comparator is established by setting the
potentiometer A so that the voltage at terminal 3 is more positive than that at terminal 2 when the motor speed is too low. An
error voltage E1 is derived from a tachometer driven by the
motor. When the motor speed is too low, the voltage at terminal
2 of the voltage comparator is less positill9 than that at terminal
3, and the output voltage at terminal 6 goes "high". When the
motor speed is too high, the opposite input conditions exist, and
the output voltage at terminal 6 goes "Iow". Figure 27B also
shows these conditions graphically, with a linear transition
region between the "high" and "low" output lewis. This linear
OCMOTOR
~..am.
]1
~~ SPEED ....";;,;;;,;.;.;;.;,,,;;;;.;......
SIGNAL
D2
D1
FIGURE26A.
NOTE:
1. This 1!lYe1 will vary depending on
motor speed. (See Text).
FIGURE26B.
FIGURE 26. MOTOR SPEED CONTROLLER SYSTEM
11-38
Application Note 6048
transition region is known as "proportional bandwidth". The
slope of this region is detennined by the proportional bandwidth
control to establish the error correction response time.
PROPORTIONAL
BANDWIDTH CONTROL
than tenninal3, transistors 012 and 013 in the CA3094 (Figure 1) lose their base drive and become non-conductive.
Under these conditions, C1 discharges linearly through the
external diode D3 and 010, OS path in the CA3094 to produce the ramp wave. The Eour signal is supplied to the phase
comparator in Figure 26.
.---------~--~~
+1SV
C1
0.033
I1f
-15V
FIGURE 28A.
RECTIFIED AND FILTERED
SIGNAL DERIVED FROM
TACHOMETER DRIVEN BY
MOTOR BEING CONTROLLED
E~ ~0.vQc_~ :A:E~:~~LNO.3
FIGURE 27A. VOLTAGE COMPARATOR
~
+
BANDWIDTH
Eour HIGH
MOTOR SPEED
SLOW -
/rC1 DISCHARGING (RAMP)
~ ~~C1CHARGING
OPoRnONAL
MOTOR SPEED
FAST
EourLOW
FIGURE 28B.
FIGURE 28. SYNCHRONOUS RAMP GENERATOR WITH INPUT
AND OUTPUT WAVEFORMS
FIGURE 27B.
FIGURE 27. MOTOR SPEED ERROR DETECTOR
Thyristor Firing Circuits
Synchronoua Ramp Generator
Figure 28 shows a schematic diagram and signal waveforms
for a synchronous ramp generator suitable for use with the
motor controller circuit of Figure 26. Terminal 3 is biased at
approximately +2."N (above the negative supply voltage).
The input Signal EIN at terminal 2 is a sample of the half-sinusoids (at line frequency) used to power the motor in Figure 26.
A synchronous ramp signal is produced by using the CA3094
to charge and discharge capacitor C1 in response to the synchronous toggling of EIN• The charging current for C1 is supplied by terminal 6. When terminal 2 swings more positive
Temperature Controller
In the temperature control system shown in Figure 29, the
differential input of the CA3094 is connected across a bridge
circuit comprised of a PTC (positive temperature coefficient)
temperature sensor, two 75kn resistors, and an arm containing the temperature set control. When the temperature is
"low", the resistance of the PTC type sensor is also low;
therefore, terminal 3 is more positive than terminal 2 and an
output current from term inal 6 of the CA3094 drives the triac
into conduction. When the temperature is "high", the input
UlAn
1N814
z
o
-II)
tiw
(,)1-
1k1l
117V
60Hz
-0
~z
Il.
C(
0.0111f
II
NOTE: All Resistors are 112W.
FIGURE 29. TEMPERATURE CONTROllER
11-39
Application Note 6048
conditions are reversed and the triac is cut off. Feedback
from terminal B provides hysteresis to the control point to
prevent rapid cycling of the system. The 1.51<0 resistor
between terminal B and the positive supply limits the triac
gate current and develops the voHage for the hysteresis
feedback. The excellent power supply rejection and common
mode rejection ratios of the CA3094 permit accurate repeatability of control despite appreciable power supply ripple.
The circuit of Figure 29 is equally suitable for use with NTC
(negative temperature coefficient) sensors provided the
positions of the sensor and the associated resistor Rare
interchanged in the circuit. The diodes connected back to
back across the input terminals of the CA3094 protect the
device against excessive differential input signals.
thyristor Control from AC Bridge Sensor
Figure 30 shows a line operated thyristor firing circuit controlled by a CA3094 that operates from an AC Bridge sensor.
This circuit is particularly suited to certain classes of sensors
that cannot be operated from DC. The CA3094 is inoperative
when the high side of the AC line is negative because there
is no IABC supply to terminal 5. When the sensor bridge is
unbalanced so that terminal 2 is more positive than terminal
3, the output stage of the CA3094 is cut off when the AC line
swing s positive, and the output level at terminal B of the
CA3094 goes "high". Current from the line flows through the
IN3193 diode to charge the 100!LF reservoir capacitor, and
also provides current to driw the triac into conduction. During the succeeding negatiw swing of the AC line, there is
sufficient remanent energy in the reservoir capacitor to
maintain conduction in the triac.
Battery Charger Regulator Circuit
The circuit for battery charger regulator circuit using the
CA3094 is shown in Figure 31. This circuit accurately limits
the peak output voHage to 14V, as established by the zener
diode connected across terminals 3 and 4. When the output
voltage rises slightly above 14V, signal feedback through a
1001<0 resistor to terminal 2 reduces the current drive supplied to the 2N3054 pass transistor from terminal 6 of the
CA3094. An incandescent lamp serves as the indicator of
charging current flow. Adequate limiting provisions protect
the circuit against damage under load short conditions. The
advantage of the circuit over certain the types of regulator
circuits is that the reference voltage supply doesn't drain the
battery when the power supply is disconnected. This feature
is important in portable service applications, such as in a
trailer where a battery is kept "on-charge" when the trailer is
parked and power is provided from an AC line.
1Mn
R1
L111120
1000
100k0
When the bridge is unbalanced in the opposite direction so that
terminal 3 is more positive than terminal 2, the output of the
CA3094 at terminal B is driwn sufficiently "low" to "sink" the current supplied through the 1N4003 diode so that the triac gate
cannot be triggered. Resistor R1 supplies the hysteresis feedback to prewnt rapid cycling between tum on and tum off.
HIGH
MURAUTES
LAMP
os
680n
112W
FIGURE 31. BATTERY CHARGER REGULATOR CIRCUIT
180kn
330kn
1kn
2kn
5W
120V
ACUNE
1N4003
5100
10k0
+
-
100j1F
15V
FIGURE 30. UNE OPERATED THYRISTOR FIRING CIRCUIT CONTROLLED BY AC BRIDGE SENSOR
11-40
Application Note 6048
Ground Fault Interrupters (GFI)
+36V
_1mA
3V
RlRIP
1 1
1
1 Op.A
IABC
33K
200mV
RANGE
2011A
IA
ILOAD
200Q
3.3K
R
....
L 47KC
47K
100K
DIFFERENTIAL CURRENT
SENSOR PROVIDES
60mVSlGNAL
"'SmA
OF UNBALANCE
(TRIP) CURRENT
Ground fault interrupter systems are used to continuously
monitor the balance of current between the high and neutral
lines of power distribution networks. Power is interrupted
whenever the unbalance exceeds a preset value (e.g., SmA).
An unbalance of current can occur then, for example, defective insulation in the high side of the line permits leakage of
current to an earth ground. GFI systems can be used to
reduce the danger of electrocution from accidental contact
with "high" line because the unbalance caused by the leakage of current from the "high" line through a human body to
ground results in an interruption of current flow.
The CA3094 is ideally suited for GFI applications because it
can be operated from a single supply, has adequate sensitivity, and can drive a relay or thyristor directly to effect power
interruption. Figure 32 shows a typical GFI circuit. Vernier
adjustment of the trip point is made by the RTR1P potentiometer. When the differential current sensor supplies a signal
that exceeds the selected trip-point voltage level (e.g.,
SOmV), the CA3094 is toggled "on" and terminalS goes "low"
to energize the circuit breaker trip coil. Under quiescent conditions, the entire circuit consumes approximately 1mA. The
resistor R, connected to one leg of the current sensor, provides current limiting to protect the CA3094 against voltage
spikes as large as 100V. Figure 32 also shows the pertinent
waveform for the GFI circuit.
CIRCUIT
BREAKER
CONTROL
SOLENOID
NOTES:
1. All resistors in 0. 112W, 10%.
2. RC selected for 3db point at 200Hz.
3. C2 = AC by-pass.
4. Offset ADJ included In RmIP.
5. input impedance from 2 to 3 equals 8OOK.
6. With no input signal terminalS (Output) at +36V.
Because hazards of severe electrical shock are a potential
danger to the individual user in the event of malfunctions in
GFI apparatus, it is mandatory that the highest standard of
good engineering practice be employed in designing equipment for this service. Every consideration in design and
application must be given to the potentially serious consequences of component malfunction in such equipment. Use
of "reliability through redundancy" concepts and so called
"fail-safe" features is encouraged.
3 I -___d---->,~---VOLTAGE BETWEEN
TERMINALS 2 AND 4
References
~=~Er:g~
(ADJUSTABLE WITH RrAIP)
[1) Harris Published Data for CA3080 and CA3080A, File No.
475.
[2) Applications of the CA3000 and CA3080A High Performance
Operational Transconductance
Amplifiers,
AN6668.
t--
RGURE 32. GROUND FAULT INTERRUPTER (GFI) AND WAVEFORM PERTINENT TO GROUND FAULT DETECTOR
[3) L. Kaplan and H. A. Wittlinger, "An IC Operational
Transconductance Amplifier (OTA) with Power Capability". Paper originally presented at the IEEE Chicago
Springs Conference on Broadcast and TV Receivers,
June 1972. Reprinted as ANS077.
[4) Harris Published Data for CA3085, File No. 491.
[5) Harris Published Data lor CA3083, File No. 481.
11-41
Harris Semiconductor
-
--
--
--------- -= - - --
-
-
---
- -~-
-
No. AN60n.1
-~
--
~
--
- -
--===
--------- ---
~
--~-
-
_I
-~
Harris Intelligent Power
April1994
AN IC OPERATIONAL TRANSCONDUCTANCE
AMPLIFIER (OTA) WITH POWER CAPABILITY
Authors: L. Kaplan and H. Wlttlinger
In 1969, the first triple operational transconductance amplifier
or OTA was introduced. The wide acceptance of this new circuit concept prompted the dewlopment of the single, highly
linear operational transconductance amplifier, the CA3080.
Because of its extremely linear transconductance characteristics with respect to amplifier bias current, the CA3080 gained
wide acceptance as a gain control block. The CA3094
improved on the performance of the CA3080 through the
addition of a pair of tranSistors; these transistors extended the
current carrying capability to 300mA, peak. This new device,
the CA3094, is useful in an extremely broad range of circuits
in consumer and industrial applications; this paper describes
only a few of the many consumer applications.
INVERTING
INPUT
FIGURE 2. CURRENT MIRRORS W, X. Y AND Z USED IN THE OTA
What Is an OTA?
The OTA, operational transconductance amplifier, concept is as
basic as the transistor; once understood, it will broaden the
designer's horizons to new boundaries and make realizable
designs that were previously unobtainable. FlQure 1 shows an
equivalent diagram of the OTA. The differential input circuit is
the same as that found on many modem operational amplifl8rs.
The remainder of the OTA is composed of current mirrors as
shown in Figure 2. The geometry of these mirrors is such that
the current gain is unity. Thus, by highly degenerating the current mirrors, the output current is precisely defll1ed by the differential input amplifier. FlQure 3 shows the output current transfer
characteristic of the amplifier. The shape of this characteristic
remains constant and is independent of supply YOItage. Only
the maximum current is modified by the bias current.
1.0
Q
:i!l! o.a
~:::I
il
8~
~i
o.a
r-- ....
\
DlFFEREN11AL AMPURER
TRANSFER CHARACTERISTIC
, ,\ ,
~
1\
G.4
D.2
"-
0
81E .0.2
~
\
s~~ ::
-1110
1\
"
I!I .0..
-1.0
"
-100
010
0
50
1\
...... ~
100
150
,W... (mV)
FIGURE3.THEOUTPUTCURRENTTRANSFERCHARACTE~
ISTIC OF THE OTA IS THE SAME AS THAT OF AN
IDEALIZED DIFFERENTIAL AMPLIFIER
11m = 19.2 -IABC
(mA)
(mS)
Ro .. 7.5IIABC
(MO)
(mA)
±!our"'IABC
Max (mA)
(mA)
FIGURE 1. EQUIVALENT DIAGRAM OF THE OTA
The major controlling factor in the OTA is the input amplifier
bias current IABC; as explained in Figure 1, the total output
current and 9m are controlled by this current. In addition, the
input bias current, input resistance, total supply current, and
output resistance are all proportional to this amplifl8r bias
current. These factors provide the key to the performance of
this most flexible device, an idealized differential amplifier,
i.e., a circuit in which differential input to single ended output
conversion can be realized. With this knowledge of the
basics of the OTA, it is possible to explore some of the applications of the device.
Copyrlght@HarrisCorponotlon tll94
11-42
Application Note 6077
DC Gain Control
The methods of providing DC gain control functions are
numerous. Each has its advantage simplicity, low cost, high
level control, low distortion. Many manufacturers who have
nothing better to offer propose the use of a four quadrant
multiplier. This is analogous to using an elephant to carry a
twig. It may be elegant but it takes a lot to keep it goingl
When operatad in the gain control mode, one input of the
standard transconductance multiplier is offset so that only
one half of the differential input is used; thus, one half of the
multiplier is being thrown away.
was obtained with the circuit shown in Figure 6. Note the
improvement in linearity of the transfer characteristic.
Reduced input impedance does result from this shunt connection. Similar techniques could be used on the OTA output,
but then the output signal would be reduced and the correction circuitry further removed from the source of non linearity.
It must be emphasized that the input circuitry is differential.
The OTA, while providing excellent linear amplifier characteristics, does provide a simple means of gain control. For this
application the OTA may be considered the realization of the
ideal differential amplifier in which the full differential amplifier gm is converted to a single ended output Because the
differential amplifier is ideal, its gm is directly proportional to
the operating current of the differential amplifier; in the OTA
the maximum output current is equal to the amplifier bias
current IABC• Thus, by varying the amplifier bias current, the
amplifier gain may be varied: A gm RL where RL is the output load resistance. Figure 4 shows the basic configuration
of the OTA DC gain control circuit.
=
7
I
•
I III
I
I III
100 _
!i l
~
llli
DIODE CURRENT
IIII
m
li'::::
4
III
!:.3
o
..
j!: 2
~ ~J
}'ACA3080A
BC
...
11
o
0.1
1.0
80
SIN RATIO
10
IU
40
III
:!!.
~
i
20
ITh
0
1.0V
10
100
INPUT VOLTAGE (my)
FIGURE SA.
7
•
DIODE CURRENT. o.SmA
100 _
~~
VII
GAIN
CONTROL
~ ~r-
I
1C1!lA
10
-
100
40
tltD
1V
I
:~
10.".1'
o
1
CA3OIOA
FABC
SlNRATlCl
10V
i
o
INPUT VOLTAGE (mY)
FIGURE 4. BASIC CONFIGURATION OF THE OTA DC GAIN
CONTROL CIRCUIT
F1GURE5B.
As long as the differential input signal to the OTA remains
under 50mV peak-ta-peak, the deviation from a linear transfer will remain under 5 percent. Of course, the total harmonic
distortion will be considerably less than this value. Signal
excursions beyond this point only result in an undesired
'compressed" output. The reason for this compression can
be seen in the transfer characteristic of the diffarential amplifier in Figure 3. Also shown in Figure 3 is a curve depicting
the departure from a linear line of this transfer characteristic.
DIODE CURRENT .1mA
1r-r-+ttr-+-ti+r-r-+ttrtr-t+H
z
o
-en
~W
O~
-0
~Z
Q.
«
The actual performance of the circuit shown in Figure 4 is
plotted in Figure 5. Both signal to noise ratio and total harmonic distortion are shown as a function of signal input. Figures 5B and 5C show how the signal handling capability of
the circuit is extended through the connection of diodes on
the input as shown in Figure 6121 . Figure 7 shows total system
gain as a function of amplifier bias current for several values
of diode current. Figure 8 shows an oscillosoope reproduction of the CA3080 transfer characteristic as applied to the
circu~ of Figure 4. The oscilloscope reproduction of Figure 9
11-43
DISTORTION IS PRIMARILY
A FUNCTION OF SIGNAL INPUT
10
100
10V
INPUT VOLTAGE (mY)
10V
FlGURE5C.
FIGURE 5. PERFORMANCE CURVES FOR THE CIRCUIT OF
FIGURES 4 AND 6
Application Note 6077
100
.JI'
10
z
i
1.0
0.1
'f /
'F
I'
100
Transistors from CA3046 array
AGC System with extended Input range
FIGURE 6. A CIRCUIT SHOWING HOW THE SIGNAL HANDLING CAPABIUTY OF THE CIRCUIT OF
FIGURE 4 CAN BE EXTENDED THROUGH THE
CONNECTION OF DIODES ON THE INPUT
i""""-
'"
~
--- --
CURRE
O.&mA
......
I--"
2110
~
00!lA DIOOE NT
300
400
IABC",",)
==
500
FIGURE 7. TOTAL SYSTEM GAIN AS A FUNCTION OF AMPU·
FlER BIAS CURRENT FOR SEVERAL VALUES OF
DIODE CURRENT
,
N
-----
10,..\
~
....... .......
Horizontal: 25mVIDIv. Vertical: 5Oj1AID1v.
IABC = 100pA
i'o..
i'.
""'~ '"
:'"
......
,
-
Horizontal: O.5V/Dtv. Vertical: OOI1A/DIv.
IABC = 1001lA. Diode Current = 1mA
FIGURE 8. OSCILLOSCOPE REPRODUCTION OF THE CA3080
TRANSFER CHARACTERISTIC AS APPLIED TO
THE CIRCUIT OF FIGURE 4
FIGURE
e. OSCILLOSCOPE REPRODUCTION OF THE CA3080
TRANSFER CHARACTERISTIC AS APPLIED TO
THE CIRCUIT OF FIGURE 6
Simplified Differential Input to Single Ended Output
Conversion
One of the more exacting configurations for operational
amplifiers is the differential to single-ended conversion circuit. Figure 10 shows some of the basic circuits that are usually employed. The ratios of the resistors must be precisely
matched to assure the desired common mode rejection. Figure 11 shows another system using the CA3080 to obtain
this conversion without the use of precision resistors. Differential input signals must be kept under 126mV for better
than 5 percent nonlinearity. The common mode range is that
of the CA3080 differential amplifier. In addition. the gain
characteristic follows the standard differential amplifier gm temperature coeffICient of -O.3%I"C. Although the system of
Figure 11 does not provide the precise gain control obtained
with the standard operational amplifier approach. it does
provide a good simple compromise suitable for many differential transducer amplifier applications.
11-44
Application Note 6077
between wide limits. The device has a large reserve of output-current capabiIiIy, and breakdown and power dissipation
ratings suffICiently high to allow it to drive a complementary
pair of transistors. For example. a 12W power amplifier stage
(an load) can be driven with peak currents of 35mA (assuming a minimum Ou1put transistor beta of SO) and supply IIOltages of ±lSV. In this application. the CA3094A is operated
substantially below its supply voltage rating of 44V max. and
its dissipation rating of 1.6W max. Also in this application. a
high value of open-loop gain suggests the possibility of precise adjustment of frequency response characteristics by
adjustment of impedances in the teedback networks.
R1
DlFFERENlJAL >-~"r-""r...
INPUT
OUTPUT
>-~"r-+-I;.o'
R3
DIFFERENTIAL
OUTPUT
INPUT
Implicit Tone Controls
In addition to low distortion. the large amount of loop gain and
flexibility of feedback arrangements available when using the
CA3094 make it possible to incorporate the torl6 controls into
the feedback network that surrounds the entire amplifier system. Consider the gain requirements of a phonograph playback system that uses a typical high quality magnetic
cartridge)3] A desirable system gain would result in from 2W
to 5W of outpu1 at a recorded velocity of 1cm/s. Magnetic
pickups have outputs typically ranging from 4mV to 10mV at
Scm/s. To get the desired output. the total system needs
about 72dB of voltage gain at the reference frequency.
R1
DIFFERENTIAL
INPUT
.B1 • .!H.
A2
A3
Figure 12 Is a block diagram of a system that uses a passive or
of tone control circuit that Is inserted ahead of the
gain control. Figure 13 shows a system in which the torl6 controls are implicit in the feedback circuits of the power amplifier.
Both systems assUrr16 the same noise input voltage at the
equalizer and mai....amplifler inpu1S. The feedback system
shows a small improvement (3.8dB) in signal-ta-noise ratio at
maximum gain bu1 a dramatic improvement (2OdB) at the zero
gain position. For purposes 01 oomparison. the assumption Is
made that the torl6 controls are set "liar in both cases.
"Iosse(' type
A4
>---....-OUTPUT
FIGURE 10. SOME TYPICAL DIFFERENTIAL TO SINGLEENDED CONVERSION CIRCUITS
-
+V
IABC
Cost Advantages
In addition to the savings resulting from reduced parts count
and Circuit size. the use of the CA3094 leads to further savings in the power supply system. Typical values of power supply rejection and common-mode rejection are 90dB and
1COdB. respectively. An amplifier with 40dB of gain and 90dB
of power supply rejection would require 316mVof power supply ripple to produce 1mV of hum at the outpu1. Thus. no further filtering is required other than that given by the energy
storage capacitor at the output of the rectifier system.
2K
2K
NOTES:
1.A=gm Rl
AT SOOIJA. IABC
2. gm"'OmS
3.:. A = 1OmS x lOK= 100
FIGURE 11. A DIFFERENTIAL TO SINGLE ENDED CONVERSION CIRCUIT WITHOUT PRECISION RESISTORS
TheCA3094
The CA3094 offers a unique combination of characteristics
that suit it ideally to use as a programmable gain block for
audio power amplifiers. It is a transconductance amplifier in
which gain and open-loop bandwidth can be controlled
Power Amplifier Using the CA3094
A complete power amplifier using the CA3094 and three
additional transistors is shown schematically in Figure 14.
The amplifier is shown in a single-channel configuration. but
power supply values are deSigned to support a minimum of
two channels. The output section comprises 01 and 02.
complementary epitaxial units connected in the familiar
"bootstrap" arrangement. Capacitor C3 provides added base
drive for 01 during positive excursions of the output. The circuit can be operated from a single power supply as well as
from a split supply as shown in Figure 15. The changes
required for 14.4V operation with a 3.20 speaker are also
indicated in the diagram.
11-45
Application Note 6077
E SIG .. 40mV
PICKUP
ESIG=lmV
ESIG.4mV
E SIG=4mV
Eo=4V
-----'1
r---~E~Q~U~A~LI~Z~ER~--~
BUFFER STAGE
EN AT INPUT .. 5 x 10-6
A REF=32dB
EN AT INPUT = 1 x 10-6
EN = 4 x 10.6
TOTAL GAIN .. 72dB
EN = 6.23 x 10-6
Eo = _ _4_ _ = 640 AT MAX VOL
EN
6.23 x 10-3
EN = 4mV AT MIN VOL
FIGURE 12. BLOCK DIAGRAM OF A SYSTEM USING A "LOSSER" TYPE TONE CONTROL CIRCUIT
EO=4V
E SIG=40mV
EQUALIZER
AREF=32dB
EN ATiNPUT = 1 x 10.6
BUFFER STAGE
H - - i EN AT INPUT = 5 X 10-6 1-..........,
EN" 40 x 10.6
EN = 4.03 X 10-3
Eo = _ _4_ _ = 990 AT MAX VOL
EN
4.03 x 10-3
EN" O.SmV AT MIN VOL
FIGURE 13. A SYSTEM IN WHICH TONE CONTROLS ARE IMPLICIT IN THE FEEDBACK CIRCUIT OF THE POWER AMPLIFIER
The amplifier may also be modified to accept input from
ceramic phonograph cartridges. For standard inputs (equalizer
preamplifiers, tuners, etc.) Cl is O.047J.lF, Rl is 250kn, and R2
and C2 are omitted. For ceramic-cartridge inputs, Cl is
O.OO47J.lF, Rl is 2.5Mn. and the jumper across C2 is removed.
network includes R3, R4, R5, C4, and C5. C6 blocks the dc
from the feedback network so that the DC gain from input to
the feedback takeoff point is unity. The residual DC output
voltage at the speaker terminals is then
Rt Rl1 + R12
R12
Output Biasing
Instead of the usual two-diode arrangement for establishing
idling currents in 01 and 02, a "Vbe Multiplier", transistor 03,
is used. This method of biasing establishes the voltage
between the base of 01 and the base of 02 at a constant
multiple of the base to emitter voltage of a single transistor
while maintaining a low variational impedance between its
collector and emitter (see Appendix A). If transistor 03 is
mounted in intimate thermal contact with the output units,
the operating temperature of the heat sink forces the Vbe of
03 up and down inversely with heat-sink temperature. The
voltage bias between the bases of 01 and 02 varies
inversely with heat sink temperature and tends to keep the
idling current in 01 and 02 constant.
A bias arrangement that can be accomplished at lower cost
than those already described replaces the Vbe multiplier with
a 1N5391 diode in series with an S.20 resistor. This
arrangement does not provide the degree of bias stability of
the Vbe multiplier, but is adequate for many applications.
Tone-Controls
The tone controls, the essential elements of the feedback
system, are located in two sets of parallel paths. The bass
where Rl is the source resistance. The input bias current is
then
I ASC
(VCC+V SE )
~
2PR6
The treble network consists of R7, RS, R9, Rl0, C7, CS, C9,
and Cl0. Resistors R7 and R9 limit the maximum available
cut and boost, respectively. The boost limit is useful in curtailing heating due to finite tum-off time in the output units. The
limit is also desirable when there are tape recorders nearby.
The cut limit aids the stability of the amplifier by cutting the
loop gain at higher frequencies where phase shifts become
significant.
In cases in which absolute stability under all load conditions is
required, it may be necessary to insert a small inductor in the
output lead to isolate the circuit from capacitive loads. A 3J.lH
inductor (lA) in parallel with a 220 resistor is adequate. The
derivation of circu~ constants is shown in Appendix B. Curves
of control action versus electrical rotation are also given.
11-46
Application Note 6077
.f
"BOOST" R20
(ew) 15K
"CUT"
~ TREB~
1211f
(CCW)
r-~~--,
-IoII-_--.,T1
~.~~ ~ 1A
180(1()
2200
FIt
I8Q
=
...
r-_~---
At
C7
O.01I1f 82(1()
CII
1W
C3
1511f
+--+,..jE--+--.,
~
O.OO1I1f
R11
3300
R12
R2
470
1.'un
C5
O.2~F
C5
t-
2Sj1F
R5
1K
C4
O.02~F
"BOOST" R4
(CW)
100K
"CUT"
(CCW)
R3
10K
JUMPER
FIGURE 14. A COMPLETE POWER AMPLIFIER USING THE CA3094 AND THREE ADDITIONAL TRANSISTORS
+38V
Vee
220K
5%
o.1~F
~
=
TREBLE
15K
1.8K
-
15OC1!tF
'1
+
O~F
330
0
U70
220K
470
+ZSI1f
~112Vee
220K
2Sj1F
112Vee
5"
-
t
0.4711f
O.~F
1K
-
-
47K
FIGURE 15. A POWER AMPLIFIER OPERATED FROM A SINGLE SUPPLY
11-47
- -
Application Note 6077
Performance
Companion RIAA Preamplifier
Figure 16 is a plot of the measured response of the complete
amplifier at the extremes of tone control rotation. A comparison of Figure 16 with the computed curves of Figure B4
(Appendix B) shows good agreement. The total harmonic distortion of the amplifier with an unregulated power supply is
shown in Figure 17; 1M distortion is plotted in Figure 18. Hum
and noise are typically 700ILV at the output. or 83dB down.
Many available preamplifiers are capable of providing the
drive for the power amplifier of Figure 14. Yet the unique
characteristics of the amplifier. its power supply. input impedance. and gain make possible the design of an RIM preamplifier that can exploit these qualities. Since the input
impedance of the amplifier is essentially equal to the value of
the volume control resistance (250kn). the preamplifier need
not have high output current capability. Because the gain of
the power amplifier is high (40dB) the preamplifier gain only
has to be approximately 30dB at the reference frequency
(1kHz) to provide optimum system gain.
60
r-..
55
BASS BOOST
50
.,
w
~
35
0
"
"'"
30
w
TREBLE~J
I.......
4S
iii" 40
r-
1/
25
f""""o,.
r--.
JU
TREBLE CUT
I I
2
FLAT
..... 1"-
1/
.... VBASSCUT
10
II
[""000
l,..o
20
15
V
III
3 68
2 3 68
2 3 68
2
100
1000
10K
FREQUENCY (Hz)
10
3 68
lOOK
FIGURE 16. THE MEASURED RESPONSE OF THE AMPLIFIER
AT EXTREMES OF TONE CONTROL ROTATION
1.0
~!fl
-
1kHz -,..
~ 0.9
2kHz ..,.
z
0 0.8
N
1=
a: 0.7
~
--~Eo
>--~Eo
Es
A
= (Cl;4C4 ) [ l+SREFF
(Cl C4+C3 C4+Cl C3)J
(Cl+C4)
A
1 +SR EFF C3
= (C1;4C4 ) [ 1 +SREFF
.
(Cl C4+C2 C4+Cl C2)J
(Cl +C4)
1 + SR EFF (C1 + C2)
Cl+C4
ALOW FREQUENCY
Cl +C4
= ---c4
ALOW FREQUENCY
FIGURE B1 (C). TREBLE BOOST
= ---c4
FIGURE B1 (0). TREBLE CUT
FIGURE B1. FOUR OPERATIONAL AMPUFIER CIRCUIT CONFIGURATIONS ANO THE GAIN EXPRESSIONS FOR EACH
The unaffected portion of the gain (A high for the bass control and A low for the treble control) is 11 in each case.
To make the controls work in the circuit of Figure 14, breaks
were set at 1000Hz:
To make the controls work symmetrically, the low and high
frequency break points must be equal for both boost and cut.
for the base control O.1C1R1
Thus:
. Cl R3 (Rl+R2) _ C2R2R3
B
C
ass ontrol. Rl + R2 + R3 - R2 + R3
and for the treble control R1C3 = 2,.; x 1000
1
= 2,.; x 1000
1
Response and Control Rotation
and C1 R3
= C2 R3
(Rl + R2)
Rl +R2+R3
since R3::R2+ R3,
C2=1OC1
Tebl C
I R1 (Cl C4+C3 C4+Cl C3)
r e ontro:
Cl +C4
Rl R2
= Rl + R2 (Cl +C2)
Rl R2
and R2C3 = (R1+ R2)
(Cl C4+C2 C4+Cl C2)
(Cl + C4)
since Cl:: looC2,C2 = C3 and Cl = 10C4,Rl = 9R2
In a practical design, it is desirable to make "flat" response
correspond to the 50% rotation position of the control, and to
have an aural sensation of smooth variation of response on
either side of the mechanical center. It is easy to show that
the "flat" position of the bass control occurs when the wiper
are is advanced to 91% of its total resistance. The amplitude
response of the treble control is, however, never completely
"flat"; a computer was used to generate response curves as
controls were varied.
Figure B3 is a plot of the response with bass and treble tone
controls combined at various settings of both controls. The
values shown are the practical ones used in the actual
design. Figure B4 shows the Information of Figure B3 replot-
11-50
Application Note 6077
ted as a function 01 electrical rotation. The Ideal taper for
each control would be the complement of the 100Hz plot for
the bass control and the 10kHz response for the treble control. The mechanical center should occur at the crossover
point in each case.
R2
CW
A3
CCW
41
40
31
30
R1
IJ
iD
:l!.25
~
20
'--1000Hz~t-'"
11
100Hz
./
10
",""
1
o
""
~
CW
R1
-~IHz
I
..-- V
G.2
0.4
D.I
o.a
1.0
ELECTRICAL AOTAnON OF BASS CONTROL
FIGURE B2 (A). BASS CONTROL
C1
D
FIGURE 84 (A).
CCW
40
A2
31
30
C2
./l
1kHz
10kHz
10
FIGURE B2 (B). TREBLE CONTROL
5
FIGURE B2. CUT AND BOOST BASS AND TREBLE CONTROLS
THAT HAVE THE CHARACTERISTICS OF THE CIRCUITS IN FIGURE B1
o
~
...-
-I"'"
3UkHz
~
0.2
0.4
D.I
0..
1.0
ELECTRICAL AOTAnON OF TREBLE CONTROL
FIGURE 84 (B).
FIGURE 84. THE INFORMATION OF FIGURE B3 PLOTTED AS A
FUNCTION OF ELECTRICAL ROTATION
References
46
[1] AN6668, "Applications of the CA3080 and CA3080A
High Performance Operational Transconductance Amplifiers," H. A. Wlltlinger, Harris Semiconductor.
40
l3&
OJ
~3O
25
[2] "A New Wide-Band Amplifier Technique; B. Gilbert,
IEEE Journal of Solid State Circuits, Vol. SC-3, No.4,
December, 1968.
20
[3] "Trackability; James A. Kogar, Audio, December, 1966.
15
10
5
0
10
100
1000
FREQUENCY (Hz)
10K
100K
FIGURE 83. A PLOT OF THE RESPONSE OF THE CIRCUIT OF
FIGURE 14 WITH BASS AND TREBLE TONE CONTROLS COMBINED AT VARIOUS SEmNGS OF
BOTH CONTROLS
11-51
Harris Semiconductor
-
---=----====
- --- -
--
.
.=-==-=-- --=
~
-==- ===-==--- - --- --
--------
No. AN6157.1
Harris Intelligent Power
April1994
APPLICATIONS OF THE CA3085 SERIES MONOLITHIC
IC VOLTAGE REGULATORS
Authors: A.C.N. Sheng and L.R. Avery
The Harris CA3085, CA3085A, and CA3085B monolithic
IC's are positive-voltage regulators capable of providing output currents up to 100mA over the temperature range from 55°C to +125°C. They are supplied in 8 lead TO-5 type packages. The following tabulation shows some key characteristics and salient differences between devices in the CA3085
Series.
VOUT (Vo)
RANGE
louT (10)
TYPE
VIN (V~
RANGE
(V)
(V)
(mA)
MAX LOAD
REGULATION
(%Vo)
CA3085
7.5 - 30
1.8 - 26
12·
0.1
CA3085A
7.5 -40
1.7 - 36
100
0.15
CA3085B
7.5 - 50
1.7 - 46
100
0.15
MAX.
age stability. If necessary, filtering of the inherent noise of the
reference-YOItage circuit can be accomplished by oonnecting
a suitable bypass capacitor between terminals 5 and 4.
Terminal 6 (the "inverting input' in accordance with operational-amplifier terminology) is the input through which a
sample of the regulated output voltage is applied.
·This value may be extended to 100mA; however, regulation
is not specified beyond 12mA.
In addition to these differences, the range of some specified
performance parameters is more tightly controlled in the
CA3085B than in the CA3085A, and more in the CA3085A
than in the CA3085.
This note describes the basic circuit of the CA3085 series
devices and some typical applications that include a high
current regulator, constant current regulations, a switching
regulator, a negative-YOItage regulator, a dual-tracking regulator, high-voltage regulators, and various methods of providing current limiting, A circuit in which the CA3085 is used as
a general-purpose amplifier is also shown.
Circuit Description
The block diagram of the CA3085 series circuits is shown in
Figure 1. Fundamentally, the circuit consists of a frequency
compensated error-amplifier which compares an internally
generated reference voltage with a sample of the output voltage and controls a series-pass amplifier to regulate the output. The starting circuit assures stable latch-in of the
voltage-reference circuitry. The current-limiting portion of the
circuit is an optional ,feature that protects the IC in the event
of overload.
Terminal 5 provides a source of stable reference YOItage for
auxiliary use; a current of about 250tJA can be supplied to an
external circuit without Significantly disturbing reference-voIt-
FIGURE 1. BLOCK DIAGRAM OF CA30B5 SERIES
The collector of the series-pass output transistor is brought
out separately at terminal 2 ("current booster'1 to provide
base drive for an external p-n-p transistor; this approach is
one method of regulating currents greater than 100mA.
Because the voltage regulator is essentially an operational
amplifier having considerable feedback, frequency compensation is necessary in some circuits to prevent oscillations.
Terminal 7 is provided for if external frequency compensation is necessary. Terminal 7 can also be used to "inhibir
(strobe, squelch, pulse, key) the operation of the series-pass
amplifier.
Brief Description of CA3085 Schematic Diagram
The schematic diagram of the CA3085 series circuits Is
shown in Figure 2. The left-hand section Includes the starting circuit, the voltage reference circuit, and the constantcurrent circuit. The center section is basically an elementary
operational amplifier which serves as the voltage-error
Copyright @ Harris Corporation 1992
11-52
Application Note 6157
amplifier controlling the series-pass. Darlington pair (013.
014) shown in the right-hand section when controlled by an
appropriate external sensing network. transistor 015. serves
to provide protective current-limiting characteristics by
diverting base drive from the series pass circuit. For operation at the highest current levels. terminals 2 and 3 are tied
together to eliminate the voltage drop which would otherwise
be developed across resistor RS.
VOL~~~~:~~~NCE.
,
VOLTAGE-:
CONSTANT.cURRENT :
ERROR
: SERIES-PASS AND CURRENTCIRCUITS
: AMP (OP AMP) :
LIMITING CIRCUITS
~:,
...
...
:
drop between terminals 4 and 5 that results in the reference
voltage (- 1.6V) having an effective temperature coefficient
of about 0.OO350/0I"C.
The reference diode 03 receives a currant of approximately
6201JA from a constant-current circuit consisting of 03 and
the current-mirror' 06. 01. and 02. Current to start-up the
constant-current source initially is provided by auxiliary
zener diode 01 and R1. Diode 02 blocks current from the
R1-01 source after latch-in of the constant-current source
establishes a stable reference potential. and thereby prevents modulation of the reference voltage by ripple voltage
on the unregulated input voltage.
Voltage-Error Amplifier
V+IN
UNREG
INPUT
R.
500
COMPENSATION
AND EXTERNAL
INHIBIT
··:
·:
01
0,. CURRENT
BOOSTER
:
~
1.5k
.,Mt-JoIV.......--W
0,
:
··
·
015
REGULATED
OUTPUT
Series-Pass and Current-Limiting Circuits
.NY. : CURRENT
ALL RESISTANCE VALUES:
INPUT.
ARE IN II
: SUBSTRATE :
Transistors 05 and 06 comprise the basic differential amplifier that is used as a voltage-error amplifier to compare the
stable reference voltage applied at the base of 05 with a
sample of the regulator output voltage applied at terminal 6.
The 05-04 combination is a current-mirror which maintains
essentially constant-current flow to 05 and 06 despite variations in the unregulated input voltage. The 08. 09. and 07
network provides a "mirrored" active collector load for 05
and 06 and also provides a variable single-ended drive to
the 013 and 014 series-pass transistors in accordance with
the difference signal developed between the bases of 05
and 06. The open-loop gain of the error-amplifier is greater
than 1000.
LIMITING
FIGURE 2. SCHEMATIC DIAGRAM OF CA3085 SERIES
Voltage Reference Circuits
The basic voltage referenced element used in the CA3085 is
zener diode 03. It provides a nominal reference voltage of
5.5V and exhibits a positive temperature coefficient of
approximately 2.5mVI"C. If this reference voltage were used
directly in conjunction with the error-amplifier (05. 06. etc.).
the IC would exhibit two major undesirable characteristics:
(1) its performance with temperature variations would be
poor. and (2) its use as a regulator would be restricted to circuits in which the minimum regulated output voltages are in
excess of 5.5V. Consequently. it is necessary to provide
means of compensating for the positive temperature coefficient of 03 and at the same time provide for obtaining a stable source of lower reference voltage. Both temperature
compensation and the reduction of the reference voltage are
accomplished by means of the series divider network consisting of the base-emitter junction of 03. diode 04. resistors
R2 and R3. and diode 5.
The voltage developed across 03 drives the divider network
and a voltage of approximately 4V is developed between the
cathode of 04 and the cathode of 05 (terminal 4). The current through this divider network is held nearly constant with
temperature because of the combined temperature coefficients of the zener diode (03). 03 base-emitter junction. 04.
05. and the resistors R2 and R3. This constant current
through the diode 05 and the resistor A3 produces a voltage
In the normal mode of operation. or in the current-boost
mode when terminals 2 and 3 are tied together. the Darlington pair 013-014 performs the basic series-pass regulating
function between the unregulated input voltage and the regulated output voltage at terminal 1. In the current-limiting
mode transistor 015 provides current-limiting to protect the
CA3085 and/or limit the load current. To provide current-limiting protection. a resistor (e.g .• 50) is connected between
terminals 1 and 8; terminal 8 becomes the source of regulated output voltage. As the voltage drop across this resistor
increases. base drive is supplied to transistor 015 so that it
becomes increasingly conductive and diverts base drive
from the 013-014 pass transistor to reduce output current
accordingly. Resistor R4 is provided to protect 015 against
overdrive by limiting its base current under transient and
load-short conditions.
Because the CA3085 regulator is essentially an op-amp
having considerable feedback, frequency compensation
may be required to prevent oscillations. Stability must also
be maintained despite line and load transients. even during
operation into reactive loads (e.g .• filter capacitors). Provisions are included in the CA3085 so that a small-value
capacitor may be connected between terminals 6 and 7 to
compensate the regulator. when necessary. by "rolling-off"
the amplifier frequency-response. Terminal 7 is also used to
externally "inhibif' operation of the CA3085 by diverting base
current supplied to 013-014. thereby permitting the use of
keying. strobing. programming. and/or auxiliary overloadprotection circuits.
11-53
z
o
~w
(JI-(I)
-0
~z
Q.
- 1IV
OUTPUT VOLTAGE (V+o) _10V
AMBIENT TEMPERATURE (TAl- ZSOc
~
"l-
Rsc- O
0
~~
f\"
~g
'-
r\\
S~1
;
50
2000.2
n: STANCOR TP3
a:
Q
~000.2
VOUT
BLACK
WHITE
i
'1' ~ ii1lr
-0.4
~f~
o
20
40
10
10
100
LOAD CURRENT (ILl- mA
FIGURE 4. LOAD REGULATION CHARACTERISTICS FOR
CIRCUIT OF FIGURE 3
BLACK
RED
5"F
.". ........ --'.". .•....
~25V
OPERAnON WITHOUT
HEAT SINK
• OPERAnON WITH
lHEATSINK
\ 40V •
MV
f--
".
\\
~ 2~~--'\~
Because the open-loop gain of the error-amplifier is very
high (greater than 1000), the output voltage may be directly
calculated from the following expression:
(R2 + Ri)
R1
VREF
".-'-.--'::.1,r--"
.... ...:::..
...
••••
'"
~15V
.........
FIGURE 3. BASIC POWER SUPPLY
Vo=
~I
I'-~
20
(Ea. 1)
40
10
1
INPUT!m..TS
(v1Nl- 20V
40V
IOV
J
INPJ,.VOLTS _ (V!Nl-10V
10
OUTPUT(mA)
100
In the circuit shown in Figure 3, the output voltage can be
adjusted from 1.SV to 20V by varying R2. The maximum output current is determined by Rsc; ioad-regulation characteristics for various values of Rsc are shown in Figure 4.
High-Current Voltage Regulator
When this circuit is used to provide high output currents at
low output voltages, care must be exercised to avoid excessive IC diSSipation. In the circuit of Figure 3, this dissipation
control can be accomplished by increasing the primary-tosecondary transformer ratio (a reduction in VI) or by using a
dropping resistor between the rectifier and the CA3085 regulator. Figure 5 gives data on dissipation limitation (VI - VA VS.
10 ) for CA3085 series circuits. The short-circuit current is
determined as follows:
When regulated voltages at currents greater than 100mA are
required, the CA3085 can be used in conjunction with an
external n-p-n pass transistor as shown in the circuits of Figure 6. In these circuits the output current available from the
regulator is increased in accordance with the hFE of the
externaln-p-n pass transistor. Output currents up to SA can
be regulated with these circuits. A Darlington power transistor can be substituted for the 2N5497 transistor when currents greater than SA are to be regulated.
VBE
0.7
18 0 = - - - - - - - amperes
Rae
Rae
FIGURE 5. DISSIPATION UMITATION (VI - Vo YS Iol FOR
CA3085 SERIES CIRCUITS
(Ea. 2)
11-54
Application Note 6157
between the input and output voltages. In some applications
this requirement is prohibitive. The circuit shown in Figure 7
can deliver an output current in the order of 2A with a VI - Vo
difference of only one volt•
2N54I7
....----0.
•
>.----_----+_-0 .
2N4031
•
REG.
UNREO.
VI
Vo
10Kn
R2
REO.
Vo
FIGURE 6A. WITH SIMPUFIED SHORT-CIRCUIT PROTECTION
2N&4t7
R1
•
FIGURE 7. VOLTAGE REGULATOR FOR LOW V I - Vo
DIFFERENCE
UNREO.
VI
REO.
o-_ _ _~~--L-------__o.VO
FIGURE 68. WITH AUXIllIARY SHORT-CIRCUIT PROTEcnON
FIGURE 6. HIGH-CURRENT VOLTAGE REGULATOR USING
n-poon PASS TRANSISTOR
A simplified method of short circuit protection is used in connection with the circuit of Figure 6A. The variable resistor
Rscp serves two purposes: 1) it can be adjusted to optimize
the base drive requirements (hFE) of the particular 2N5497
transistor being used, and 2) in the event of a short circuit In
the regulated output voltage the base drive current in the
2N5497 will increase, thereby increasing the voltage drop
across Rscp. As this voltage drop increases the short circuit
protection system within the CA3085 correspondingly
reducas the output current available at terminal 8, as
described previously. It should be noted that the degree of
short circuit protection depends on the value of Rscp, i.e.,
design compromise is required in choosing the value of
Rscp to provide the desired base drive for the 2N5497 while
maintaining the desired short circuit protection. Figure 68
shows an alternate circuit in which an additional transistor
(2N2102) and two resistors have been added as an auxiliary
short circuit protection feature. Resistor R3 is used to establish the desired base drive for the 2N5497, as described
above. Resistor RUMIT now controls the short circuit output
current because, in the event of a short circuit, the voltage
drop developed across its terminals increases suffICiently to
increase the base drive to the 2N2102 transistor. This
increase in base drive results in reduced output from the
CA3085 because collector current flow in the 2N21 02 diverts
base drive from the Darlington output stage of the CA3085
(see Figure 2) through terminal 7. The load regulation of this
circuit is typically 0.025 per cent with 0 to 3A load-current
variation; line regulation is typically 0.025%IV change in
input voltage.
It employs a single external p-n-p transistor having its base
and emitter connected to terminals 2 and 3, respectively, of
the CA3085. In this circuit, the emitter of the output transistor
(Q14 in Figure 2) in the CA3085 is returned to the negative
supply rail through an external resistor (Rscp) and two
series-connected diodes (01, 02). These forward biased
diodes maintain
in the CA3085 within linear-mode operation. The choice of resistors R1 and R2 is made in accordance with Equation 1. Adequate frequency compensation
for this circuit is provided by the O.0111F capaCitor connected
between terminal 7 of the CA3085 and the negative supply
rail.
as
Figure 8 which shows the output impedance of the circuit of
Figure 7 as a function of frequency, illustrates the excellent
ripple-rejection characteristics of this circuit at frequencies
below 1kHz. Lower output impedances at the higher frequencies can be provided by connecting an appropriate
capacitor across the output voltage terminals. The addition
of a capacitor will, however, degrade the ability of the system
to react to transient-load conditions.
1000
INPUT VOLTAGE (V+i!-15V
OUTPUT VOLTAGE (V+ol _10V
AMBIENT TEMPERATURE (TAl- 2&"(
z
o
-0
ti:w
~~
crD. z
~
1/
0.1
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
Voltage Regulator with Low VI· Vo Difference
In the voltage regulators described in the previous section, it
is necessary to maintain a minimum difference of about 4V
11-55
FIGURE 8. OUTPUT RESISTANCE". FREQUENCY FOR
CIRCUIT OF FIGURE 7
Application Note 6157
High Voltage Regulator
Figure 9 shows a circuit that uses the CA3085 as a voltage
reference and regulator control device for high-voltage
power supplies in which the voltages to be regulated are well
above the input-voltage ratings of the CA3085 series circuits.
The external transistors Ql and Q2 reqUire voltage ratings in
excess of the maximum input voltage to be regulated.
Series-pass transistor Q2 is controlled by the collector current of Ql. which in turn is controlled by the normally regulated current output supplied by the CA3085. The input
voltage for the CA3085 regulator at terminal 3 is supplied
through dropping resistor R3 and the clamping zener diode
01. The values for resistor Rl and R2 are determined in
accordance with Equation 1.
+o-------~----------~--~
The circuit shown in Figure 11 is similar to that of Figure 10.
except for the addition of a constant-current limiting circuit
consisting of transistor Q4. a 1KO resistor. and resistor Rscp
When the load current increases above a particular design
value. the corresponding increase in the voltage drop across
resistor Rscp provides additional base drive to transistor Q4.
Thus. as transistor Q4 becomes increasingly conductive. its
collector current diverts sufficient base drive from Q3 to limit
the current in the pass transistor feeding the regulated load.
With the types of transistors shown in Figures 10 and 11.
maximum currents in the order of 5A can be regulated.
UN REG VI
R2
(e.g.120V)
Operation of the circuit is as follows: current through R3 and
01 provides bese drive tlr Ql. which In turn provides base
drive for the pass-transistor 03. By this means operating
potential for the CA3085 is developed between the collector of
Q3 (terminal 4 of the CA3085) and the positive supply-rail (terminal 3 of the CA3085). When the output voltage has risen
sufficiently to maintain operation of the CA3085 (approx.
7.5V). transistor Q2 is driven into conduction by the base drive
supplied from the 1KQ.12Kn voltage divider. As Q2 becomes
conductive. it diverts the base drive being supplied to Ql
through the RS-Ol path. and diode 01 ceases to conduct.
Under these conditions. base-current drive to Ql through terminal2 of the CA3085 regulates the base drive to Q3. Values
of Rl and R2 are determined in accordance with Equation 1.
REG
Vo
DI
10V-15V
+
R1
1Kn
FIGURE 9. HIGH VOL.TAGE REGULATOR
Negative Voltage Regulator
REG
The CA3085 is used as a negative-supply voltage regulator
in the circuit shown in Figure 10. Transistor Q3 is the series
pass transistor. It should be noted that the CA3085 is effec·
tively connected across the load side of the regulated system. Oiode 01 is used initially in a "circuit-starter" function;
transistor Q2 "latches' 01 out of its starter-circuit function so
that the CA3085 can assume its role in controlling the pass
transistor Q3 by means of Ql.
Vo
+o---.-------~----~~----.-~--~~~+
10Kn
1Kn
&!tF
UNREG
VI
121m
R3
4.7Kn
R2
22CKl
R1
FIGURE 10. NEGATIVE VOLTAGE REGULATOR
PASS TRANSISTOR
FIGURE 11. NEGATIVE VOLTAGE REGULATOR WITH
CONSTANT CURRENT LIMITING CIRCUIT
REG
Vo
Hlgh-Output-Current Voltage Regulator With "Foidback"
Current-Umltlng (Also known aa "Switch-Back"
Current-Umltlng)
In high-current voltage regulators employing constant current limiting (e.g .• Figures 6 and 7). it is possible to develop
excessive dissipation in the series-pass transistor when a
short circuit develops across the output terminals. This situation can be avoided by the use of the "foldbacl<" current-limiting circuitry as shown in Figure 12. In this circuit. terminal 8
of the CA3085 senses the output voltage. and terminal 1 ill
tied to a tap on a voltage-divider network connected
between the emitter of the pass-transistor (Q3) and ground.
The current-foidback trip-point is established by the value of
resistor Rsc.
II-56
Application Note 6157
The effective resistance between terminals 2 and 3 is 2500
because the extemal 5000 resistor A3 is in parallel with the
internal 5000 resistor A5. It should be understood that the
V 2-3 potential of 0.515V Is insuffICient to maintain the external p-n-p transistor Q2 In conduction, and, therefore, 03 has
no base drive. Thus the output current is reduced to zero by
the protective circuitry. Figure 13 shows the foldback characteristic typical of the circuit of Figure 12.
10
INPUT VOLTAGE
(V!l-15V
CURRENT TRIP
SET FOR 1A
£
+
i
+
UNREG
w
~
~
....
,.
REG
Va
VI
I!:,.
0
11m
0
OUTPUT CURRENT (101, (A)
FIGURE 12. HIGH OUTPUT CURRENT VOLTAGE REGULATOR
WITH "FOLDBACK" CURRENT LIMITING
The protective tripping action is accomplished by forward·
biasing 015 in the CA3085 (see Figure 2). Conditions for
tripping circuit operation are defined by the following expres·
sions:
VBE(QI5) = (voltage atterminall) • (output voltage)
Rl
~R::-'~+-R2~-
AI
Rl + R2
If
]
-Va
(Ea. 3)
= K, then
VSE(QI5) = (Vo + ILASe> K - Vo = KYo + KILASC - Vo
and therefore
Asc=
Va + VBE(015) - KYo
KIL
(Ea. 4)
Under load short-circuit conditions, terminal B is forced to
ground potential and current flows from the emitter of 014 in
the CA3OB5, establishing terminal 1 at one VsE-drop [=D.7V]
above ground and 015 in a partially conducting state. The
current through 014 necessary to establish this one V SE
condition is the sum of currents flowing to ground through Al
and [A2 + Asc]. Normally Asc is much smaller than A2 and
can be ignored; therefore, the equivalent resistance Aeq to
ground is the parallel combination of Al and A2.
FIGURE 13. TYPICAL "FOLDBACK" CURRENT-LIMITING
CHARACTERISTIC FOR CIRCUIT OF FIGURE 12
An alternative method of providing "fold back" current-limiting
is shown in Figure 14. The operation of this circuit is similar
to that of Figure 12 except that the foldback-control transistor
02 is external to the CA30B5 to permit added flexibility in
protection-circuit design.
Under low load conditions Q2 is effectively reverse-biased by
a small amount, depending upon the values of A3 and A4.
As the small amount, depending upon the values of A3 and
A4. As the load current increases the voltage drop across
Atrlp increases, thereby raising the voltage at the base of 01,
and Q2 starts to conduct. As Q2 becomes increasingly conductive it diverts base current from transistors 013 and 014
in the CA3085, and thus reduces base drive to the external
pass-transistor 01 with a consequent reduction in the output
voltage. The point at which current-limiting occurs, Imp. is
calculated as follows:
VBE(OI) = voltage at terminal 8 - Vo (assuming a low value for RrRIP)
+o-----.---------------------~
z
o
-en
tiw
u'-0
~Z
~
The 014 current is then given by:
1014
=
VBE(015)
Aeo
= VBE(OI5) = 0.7 [1.3 + 0.46]
A1R2
<
+
2.06mA
1.3 x 0.46
Rl +R2
(Ea. 5)
This current provides a IIOltage between terminals 2 and 3
as follows: n
V2-3 = IQ104 x 2500 = 2.06 x 10-3 x 250 = 0.515V
(Ea. 6)
R1
FIGURE 14.
11-57
REG
Va
HIGH-OUTPUT-CURRENT VOLTAGE REGULATOR USING AUXILIARY TRANSISTOR TO
PROVIDE "FOLDBACK" CURRENT LIMITING
Application Note 6157
VBE(Q2).
voltage at terminal B
(
= [Vo +IL RrRIP+VBE(QI)]
if K
The additional circuitry in the circuit of Figure 16 quickly
interrupts base drive to the pass transistor in event of load
fault. The point of current-trip is established as follows:
__R_4__ ) - Vo
R3+R4
VBE (OI)
I,rip=--";";;;,-"-,,--
[ __R_4__ ] -yo
R3+R4
(Ea. 9)
Rsc
R4
=-_----, then the trip current is given by:
R3+R4
QS
2N4036
VSE(Q2) - K[Vo + VsE(ol)l + Vo
+
n--'-VV~~-~~O
(Ea. 7)
KRTR1P
R2
In the circuit in Figure 12 the load current goes to zero when
a short circuit occurs. In the circuit of Figure 14 the load current is significantly reduced but does not go to zero. The
value for Ise is computed as follows:
REG
VSE(02) + [
VB~02)
+ 18(02) ] Rl
VBE(Q2)
]
VSE(02) + [ ~ + I8(Q2)
ISC.
Vo
=VSE(Ql) + IscRrRlP
Rl
R1 = VSE(Ql)
RTR1P
(Ea. B)
Figure 15 shows that the transfer characteristic of the load
current is essentially linear between the "trip-poinf' and the
·short-circuit" point.
Thus. when a sufficient voltage drop is developed across
Rse, transistor 01 becomes conductive and current flows
into the base of 02 so that it also becomes conductive. Transistor 03, in turn, is driven into conduction, thereby latching
the 02-03 combination (basic SCR action) so that it diverts
(through terminal 7) base drive from the output stage (013,
014) in the CA3085. By this means, base drive is diverted
from 04 and the pass transistor 05. To restore regulator
operation, normally closed switch Sl is momentarily opened
and unlatches 02-03.
10
~
w 8
CJ
~
..g~
o
6
4
INPUT VOLTAGE (VI) = 1SV
CURRENT TRIP SET FOR SOOmA
2
o
FIGURE 16. HIGH-VOLTAGE REGULATOR INCORPORATING
CURRENT ·SNAP-BACK" PROTECTION
Switching Regulator
100 200 300 400 500
OUTPUT CURRENT (mA)
FtGURE 15. TYPICAL FOLDBACK CURRENT-LIMITING CHARACTERISTIC FOR CIRCUIT OF FIGURE 14
High-Voltage Regulator Employing Current "Snap-Back"
Protection
In high-voltage regulators (e.g., see Figure 9), "foldback" current-limiting cannot be used safely because the high voltage
across the pass transistor can cause second breakdown
despite the reduction in current flow. To adequately protect
the pass transistor in this type of high-voltage regulator, the
so-called ·snap-back" method of current limiting can be
employed to reduce the current to zero in a few microseconds, and thus prevent second· breakdown destruction of the
device.
When large input-to-output voltage differences are necessary, the regulators described above are inefficient because
they dissipate significant power in the series-pass transistor.
Under these conditions, high-efficiency operation can be
achieved by using a switching-type regulator of the generic
type shown in Figure 17A. Transistor 01 acts as a keyed
switch and operates in either a saturated or cut-off condition
to minimize dissipation. When transistor 01 is conductive,
diode 01 is reversed-biased and current in the inductance
L1 increases in accordance with the following relationship:
'I
iL
The circuit diagram of a high-voltage regulator employing
current ·snap-back" protection is shown in Figure 16. The
basic regulator circuit is similar to that shown in Figure 9.
11·58
= VVdt
'0
(Ea. 10)
Application Note 6157
If it is assumed that transistor 01 is in steady·state saturated
operation with a low voltage-drop. the current in the inductor
is given by Eq.1 O. as follows:
&"':===.--+
+
t1
IL
V -V
= IIVdt = (T}ON
(EQ.11)
'0
When transistor 01 is off. the current In the inductor is given
C1
by:
(EQ.12)
FIGURE 17A. SELF-OSCILLATING SWITCHING REGULATOR
~"'I·Q·
From Equation 11.
L1 =
(VI· Vol
~
FORWARD DROP DF D1
Vo
f
VI
(EQ.13)
If imax is 1.3 Il. then during Ion the current in the inductor (il )
will be O.5A x 1.3 .. O.65A; therefore. Ail =O.15A.
FIGURE 178. VOLTAGE AT POINT Vx
:~.
Substitution in Equation 13 yields
(30·5)
0.15
Ll =
FIGURE 17C. INDUCTOR CURRENT IU
"~v. P+LO__"~""V
1
.-.--
1
. (20 x 10')
5
30
(EQ.14)
1.4mH
Current discharge from the capacitor C1 is given by:
dv
YAEF
Ic= C - dtAv
Thus. ll.lc = C --lJ.I- or C =
Since Ie = Itand At = !oFF. !hen
FIGURE 170. OUTPUT VOLTAGE
FIGURE 17. SWITCHING REGULATOR AND ASSOCIATED
WAVEFORMS
C=
Where V is the voltage across the inductance L1. The current
through the inductan09 charges the capacitor C1 and supplies
current to the load. The output voltage rises until it slightly
exceeds the reference voltage V,et- At this point the op-amp
removes base drive to 01 and the unregulated input voltage
V1 is 'switched off". The energy stored in the inductor L1 now
causes the voltage at Vx to swing in the negative direction and
current flows through diode 01. while continuing to supply
current into the load Rl . As the current in the inductor falls
below the load current. the capacitor C1 begins to discharge
and Vo decreases. When Vo falls slightly balow the value of
VREF • the op-amp turns on 01 and the cycle is repeated. It
should be apparent that the output voltage oscillates about
VREF with an amplitude determined by R1 and R2. Actually.
the value of VREF varies from being slightly more positive than
VREF when 01 is conducting. to being slightly more negative
than VREF when 01 is conducting. The voltage and current
waveforms are shown in Figure 178. C. and O.
ll.\.IoFF
(EQ.15)
Av
Substitution for the value of iL from Equation 13 yields
).+. (+).
V
( \ 1o
C= ______________
~
______loFF
_
(EQ.16)
Av
The total period T "'!oFF+ IoN. and T =
f
1
Therefore.
(EQ.17)
~w
For optimum effICiency Ion should be
!!!
(..:!2-) (..:!2-)
T!!!
VI
VI
_1
f
()I-
-0
~z
(EQ.18)
Substitution for Ion in Equation 18 yields
Design Example
The following specifications are used in decomputations for
a switching regulator:
VI
=3OV. Vo =5V. 10 =SOOmA.
switching frequency = 20kHz.
output ripple = 100mV
11·59
~
-U)
(EQ.19)
Q.
c(
Application Note 6157
Substitution for Ion in Equation 16 yields
C=
~.!~.!
( 1 -~)
L
·f· V ·f·
I
.
I
VI
(EQ.20)
I1v
Substitution of numerical values in Equation 20 produces the
following value for C:
30-5
1
5
1
(
5)
1.4xl0"'·2QxlOS·-ao· 20xlOS· 1-30"
C=
=63j1F
10.1
A switching-regulator circuit using the CA3085 is shown in
Figure 18. The values of Land C (1.5mH and 5OmF, respectively) are commercially available components having values
approximately equal to the computed values in the previous
design example.
1N4001
D1
1---00
---------1
FIGURE 19B. HIGH-CURRENT REGULATOR
FIGURE 19. CONSTANT CURRENT REGULATORS
The actual regulated current, reg IL is the sum of the quiescent regulator current and the current through R1, i.e.,
reg IL = IOUIESCENT + IRI
Figure 19B shows a high-current regulator using the CA3065
in conjunction with an external n-pon transistor to regulate
currents up to 3A. In this circuit the quiescent regulator current does not flow through the load and the output current
can be directly programmed by R1, i.e.,
Vo
Reg l
VREF
L=R1
With this regulator currents between 1mA and 3A can be
programmed directly. At currents below 1mA inaccuracies
may occur as a result of leakage in the external transistor.
O.01jW
40V
Rl +Rl
VO·VREF. (-R-l-)
A Dual-Tracking Voltage Regulator
FIGURE 18. TYPICAL SWITCHING REGULATOR CIRCUIT
Current Regulators
The CA3065 series of voltage regulators can be used to provide a constant source or sink current. A regulated-current
supply capable of delivering up to 100mA is shown in Figure
19A. The regulated load current is controlled by R1 because
the current flowing through this resistor must establish a voltage difference between terminals 6 and 4 that is equal to the
internal reference voltage developed between terminals 5
and 4.
REG.IL
AI
UNREG. _ ...
NEG. Vd-)
(8)
HlQH..CURRENT REGULATOR
A duai-tracking ldage regulator using a CA3085 and a
CA3094A is shown in Figure 20. The CA3094A is basically an
op-amp capable 0/ supplying 100mA of output current SpecifIcations for the CA3094A appear in datasheet file number 596.
The positive output Idage is regulated I7i a CA3085 operating
in a configuration essentially sinilar to thai described in connec>
tion with FIgUre 3. Resistor R is used as a vernier adjustment 0/
output voltage. The negative output voltage is regulated I7i the
CA3094A. Ylhich is "slaY9d" to the regulated positiYa voltage supplied I7i the CA3085. It should be noted that the non-irMIrting
input 0/ the CA3094A and the negative supply terminal of the
CA3085 are comected to a common ground reterenee. The
"slaving" potential for the CA3094A is deriYed from an accurate
1: 1 wltage-divider network comprised of two 10Kn resistors
connected between the +15V and the -15V output terminals. The
junction 0/ these two resistors is connected to the irMIrting input
of the CA3094A The voltage at this junction is compared with
the voltage at the non-inv8rting input. and the CA3094A then
automaticaUy adjusts the output current at the negatiYe terminal
to maintain a negatiYe regulated output IIOltage essentially aquaI
to the regulated positive output ldage. Typical parformance data
for this circuit are shown in FlQure 20.
-
FIGURE 19A. CURRENT REGULATOR
11-60
Application Note 6157
V+INPUT
(NOTE 1)
+15V
r-............--'OREG.
OUTPUT
1.50
RETURN
rt--~--;;~::;;~+-r-oCOMMON
200Kn
0.001"" IOcIB RIPPLE REJEC'TION
UNE REG. <0.0001%' VI
LOAD REG. <0.1% Vo FOR LOAD CURRENTS UP TO 50mA
Vo RANGE FROM 1.8V TO 30V
-
o.03tLF
0.001""
FIGURE 21A. VOLTAGE REGULATOR WITH HIGH RIPPLE
REJECTION
-+_......-..l
V-INPUT _ _
(NOTE 2)
REGULATION:
10Kn
±1%
MAX. UNE •
X 100 • 0.076'JfJV
[VOUT (INITIAL)]&VIN
MAX. LOAD.
[VOUT (INITIAL)] &VIN
X 100. 0.07S%1VOUT
ilL FROM 1fIA TO SOmA)
FIGURE21B. HIGH-CURRENTVOLTAGE REGULATOR WITH
HIGH RIPPLE REJECTION
NOTE:
The CA3085 As A Power Source For Sensors
1. V+ Input Range = 19V to 30V for 15V Output
2. V·lnput Range = -16V to ·30V for -15V Output
FIGURE 20. DUAL-VOLTAGE TRACKING REGULATOR
The basic circuit of Figure 20 can be modified to regulate dissimilar positill9 and negative voltages (e.g.. +15V. -5V) by
appropriate selection of resistor ratios in the voItage-divicier
network discussed previously. As an example. to provide
tracking of the -15V and -5V regulated voltages with the circuit
of Figure 20. it is only necessary to replace the 10KO resistor
connected between terminals 3 and 8 of the CA3094A with a
3.3K1l resistor.
Certain types of sensor applications require a regulated power
source. Additionally, Iow-impedance sensors can consume BignWicant power. An example of a circuit with these requirements.
in which a CA3085 provides regulated power for a Iow-impedance sensor and the CA3059 zero-voltage switch. is shown in
Figure 22. Terminal 12 on the CA3059 provides the ac triggersignal which actuates the zero-voltage switch synchronously
with the power line to control the load-switching triac. Specifications for the CA3059 appear in datasheet file number 490.
RL
Regulators With High Ripple Rejection
When the reference-voltage source in the CA3085 is adequately filtered. the typical ripple rejection provided by the circuit is 56dB. It is possible to achielle higher ripple-rejection
performance by cascading Mo stages of the CA3085. as
shown in FlQure 21. The voltage-regulator circuit in Figure 21A
provides 90dB of ripple rejection. The output voltage is adjustable oll9r the range fron11.8V to 30V by appropriate adjustment
of resistors R1 and R2. Higher regulated output currents up to
1A can be obtained with this circuit by adding an external n-p-n
transistor as shown in Figure 21 B.
1N4001
120V 1000
80"-
- - -....-<.
FIGURE 22. VOLTAGE REGULATOR FOR SENSOR AND ZEROVOLTAGE SWITCH
11-61
Application Note 6157
The CA3085 As A General-Purpose Amplifier
As described above. the CA3085 series regulators contain a
high-gain linear amplifier having a current-output capability
up to 100mA. The premium type (CA3085B) can operate at
supply voltages up to 50V. When equipped with an appropriate radiator or heat sink. the TO-5 package of these devices
can dissipate up to 1.6W at 55°C. A very stable internal voltage-reference source is used to bias the high-gain amplifier
and/or provide an external voltage-reference despite
extreme temperature or supply-voltage variations. These
factors. plus economics. prompt consideration of this circuit
for general-purpose uses. such as amplifiers. relay controls.
signal-lamp controls. and thyristor firing.
As an example. Figure 23 shows the application of the
CA3085 in a general-purpose amplifier. Under the conditions
shown. the circuit has a typical gain of 70bB with a flat
response to at least 100kHz without the RC network connected between terminals 6 and 7. The RC network is useful
as a tone control or to "roll-o"" the amplifier response for
other reasons. Current limiting is not used in this circuit. The
network connected between terminals 8 and 6 provides both
dc and 'ac feedback. This circuit is also applicable for directly
driving an external discrete n-pon power transistor.
OUTPUT
6800
1Kn
FIGURE 23, GENERAL-PURPOSE AMPLIFIER USING CA3085A
11-62
Harris Semiconductor
-
---
---- - - --- --=
--==
-- -.=::::::=.
=====
- -=
- --
.=-=-=-=-
No. AN6182.1
=
=
==
=
=
Harris Intelligent Power
April1994
FEATURES AND APPLICATIONS OF INTEGRATED CIRCUIT
ZERO-VOLTAGE SWITCHES (CA3059 AND CA3079)
Authors: A.C.N. Sheng, G.J. Granieri, J. Yellin, and T. McNulty
CA3059 and CA3079 zero-voltage switches are monolithic
integrated circuits designed primarily for use as trigger circuits for thyristors in many highly diverse AC power control
and power switching applications. These integrated circuit
switches operate from an AC input voltage of 24, 120,208 to
230, or 277V at 50, 50, or 400Hz.
The CA3059 and CA3079 are supplied in a 14 terminal dualin-line plastic package.
Zero-voltage switches (ZVS) are particularly well suited for
use as thyristor trigger circuits. These switches trigger the
thyristors at zero-voltage points in the supply voltage cycle.
Consequently, transient load current surges and radio
frequency interference (RFI) are substantially reduced. In
addition, use of the zero-voltage switches also reduces the
rate of change of on state current (di/dt) in the thyristor being
triggered, an important consideration in the operation of
thyristors. These switches can be adapted for use in a variety
of control functions by use of an internal differential
comparator to detect the difference between two externally
developed voltages. In addition, the availability of numerous
terminal connections to internal circuit points greatly
increases circuit flexibility and further expands the types of AC
power control applications to which these integrated circuits
may be adapted. The excellent versatility of the zero-voltage
switches is demonstrated by the fact that these circuits have
been used to provide transient free temperature control in self
cleaning ovens, to control gun muzzle temperature in low
temperature environments, to provide sequential switching of
heating elements in warm air furnaces, to switch traffic signal
lights at street intersections, and to effect other widely
different AC powar control functions.
that inhibits the application of these pulses to the thyristor in the
event that the external sensor should be inadvertently opened
or shorted. An external inhibit connection (terminal No. 1) is
also available so that an external signal can be used to inhibit
the output drive. This feature is no! included in the CA3079;
otherwise, the three integrated circuit Z8r0-\,()ltage switches are
electrically identical.
Overall Circuit Operation
Figure 1 shows the functional interrelation of the zero-voltage switch, the external sensor, the thyristor being triggered,
and the load elements in an on/off type of AC power control
system. As shown, each of the zero-voltage switches incorporates four functional blocks as follows:
Umlter Power Supply - Permits operation directly from an
ACline.
Differential ontOff SensIng Amplifier - Tests the condition of
external sensors or command signals. Hysteresis or proportional
control capab~ity may easily be implemented in this section.
Zero Crossing Detector - Synchronizes the output pulses
of the circuit at the time when the AC cycle is at a zero-voltage point and thereby eliminates radio frequency interference (RFI) when used with resistive loads.
Triac Gating ClrcuH - Provides high current pulses to the
gate of the power controlling thyristor.
In addition, the CA3059 provides the following important
auxiliary functions (shown in Figure 1):
z
1. A built-in protection circuit that may be actuated to remove
drive from the triac if the sensor opens or shorts.
o-cn
Functional-Description
2. Thyristor firing may be inhibited through the action of an
internal diode gate connected to terminal 1.
()~
Zero-voltage switches are multistage circuits that employ a
diode limiter, a zero crossing (threshold) detector, an onIoff
sensing amplifier (differential comparator), and a Darlington
output driver (thyristor gating circuit) to provide the basic
switching action. The DC operating voltages for these stages is
provided by an internal power supply that has sufficient current
capability to drive external circuit elements, such as transistors
and other integrated circuits. An important feature of the zerovoltage switches is that the output trigger pulses can be applied
directly to the gate of a triac or a silicon controlled rectifier
(SCR). The CA3059 features an interlock (protection) circuit
3. High power DC comparator operation is provided by overriding the action of the zero crossing detector. This override is accomplished by connecting terminal 12 to terminal
7. Gate current to the thyristor is continuous when terminal
13 is positive with respect to terminal 9.
Figure 2 shows the detailed circuit diagram for the integrated
circuit zero-voltage switches. (The diagrams shown in Figures
1 and 2 are representative of all three zero-voltage switches,
i.e., the CA3059 and CA3079; the shaded areas indicate the
circuitry that is not included in the CA3079.)
Copyright @ Harris Corporation 1992
11-63
~w
-0
ctz
~
Application Note 6182
ACINPUTVOLTAGE
• NEGAnVE TEMPERATURE COEFACIENT
AC INPUT VOLTAGE (50160 OR 400Hz)
(V AC)
INPUT SERIES RESISTOR (Rs)
(1Ul)
DISSIPATION RATING FOR Rs
24
2
0.5
120
10
2
2081230
20
4
277
25
5
..
(W)
NOTE: CircUitry Within shaded areas, not included In CA3079
• Seechart
£ IC = Internal connection· DO NOT USE (CA3079 only)
FIGURE 1. FUNCTIONAL BLOCK DIAGRAMS OF THE ZERO-VOLTAGE SWITCHES CA3059 AND CA3079
Rp
AI;
UNE
INPUT
Rse..-
··
··:
:
:
:
·:::
:
··:
··:-_ ........ -- ......... -_ .......... --_ ........ ........
·
FOR
INCREASED
GATE DRIVE
_
~
FAIL-SAFE INPUT
All resistance values are In a
NOTE: Circuitry within shaded areas
not included In CA3079
INHIBIT
INPUT
IC£
FOR
EXTERNAL
TRIGGER
£ IC = Internal connection· DO NOT USE (Terminal restriction applies only to CA3079)
FIGURE 2. SCHEMATIC DIAGRAM OF ZERO-VOLTAGE SWITCHES CA3059 AND CA3079
11-64
TO
THYRISTOR
GATE
Application Note 6182
The limiter stage of the zero-voltage switch clips the incoming PC line voltage to approximately ±BV. This signal is then
applied to the zero-voltage crossing detector, which generates an output pulse each time the line voltage passes
through zero. The limiter output is also applied to a rectifying
diode and an external capacitor, C" that comprise the DC
power supply. The power supply provides approximately 6V
as the Vcc supply to the other stages of the zero-voltage
switch. The on/off sensing amplifier is basically a differential
comparator. The thyristor gating circuit contains a driwr for
direct triac triggering. The gating circuit is enabled when all
the inputs are at a "high" voltage, i.e., the line voltage must
be approximately zero volts, the sensing amplifier output
must be "high", the external voltage to terminal 1 must be a
logical "(1', and, for the CA3059, the output of the fail-safe
circuit must be "high". Under these conditions, the thyristor
(triac or SCR) is triggered when the line voltage is essentially zero volts.
Thyristor Triggering Circuits
The diodes 01 and 02 in Figure 2 form a symmetrical clamp
that limits the voltages on the chip to ±8V; the diodes Dr and
0 13 form a half-wave rectifier that develops a positive voltage
on the external storage capacitor, C F
duction by current that flows Into its base through resistor R2
and diodes 0e and 0 9 when transistor 0 1 is off.
Transistor 0 1 is a portion of the zero crossing detector.
When the voltage at terminal 5 is greater than +3V, cur~ent
can flow through resistor R 1, diode Oe, the base-to-emltter
junction of transistor 0 1, and diode 04 to terminal 7 to turn
on 0 1, This action inhibits the deliwry of a gate-dr!W output
signal at terminal 4. For negative voltages at terminal 5 that
have magnitudes greater than 3V, the current flows through
diode Os, the emitter-to-base junction of transistor 0 1, diode
0 3 and resistor R1, and again turns on transistor 0 1, Transisior 0 1 Is off only when the voltage at terminal 5 is less
than the threshold voltage of approximately ±2V. When the
integrated circuit zero-voltage switch is connected as s~o~
in Figure 2, therefore, the output is a narrow pulse whICh IS
approximately centered about the zero-voltage time in the
cycle, as shown in Figure 3. In some applications, however,
particularly those that use either slightly inductive or low
power loads, the thyristor load current does not reach the
latching current valuet by the end of this pulse. An external
capacitor Cx connected between terminal 5 and 7, as shown
in Figure 4, can be used to delay the pule to accommodate
such loads. The amount of pulse stretching and delay is
shown in Figures 5(a) and 5(b).
The output pulses used to trigger the power switching thyristor are actually developed by the zero crossing detector and
the thyristor gating circuit. The zero crossing detector consists of diodes 02 and through 0e, transistor 0 1, and the
associated resistors shown in Figure 2. Transistors 0 1 and
0 6 through 0 9 and the associated resistors comprise the
thyristor gating circuit and output driver. These circuits generate the output pulses when the PC Input is at a zero-voltage point so that RFI is virtually eliminated when the zerovoltage switch and thyristor are used with resistiw loads.
FIGURE 3. WAVEFORM SHOWING OUTPUT PULSE
DURATION OF THE ZERO-VOLTAGE SWITCH.
The operation of the zero crossing detector and thyristor gating circuit can be explained more easily if the on state (i.e.,
the operating state in which current is being delivered to the
thyristor gate through terminal 4) is considered as the operating condition of the gating circuit. Other circuit elements in
the zero-voltage switch inhibit the gating circuit unless certain conditions are met, as explained later.
In the on state of the thyristor gating circuit, transistors Os
and 0 9 are conducting, transistor Or is off, and transistor 0 6
is on. Any action that turns on transistor Or removes the
driw from transistor Os and thereby turns off the thyristor.
Transistor Or may be turned on directly by application of a
minimum of ±1.2V at 10jJA to the external inhibit input, terminal1. (If a voltage of more than 1.5V is available, an external
resistance must be added in series with terminal 1 to limit
the current to 1mA.) ~iode 010 isolates the base of transistor
Or from other signals when an external inhibit signal is
applied so that this signal is the highest priority command for
normal operation. (Although grounding of terminal 6 creates
a higher priority inhibit function, this lewl is not compatible
with normal OTL or TTL logic lewis.) Transistor Or may also
be activated by turning off transistor 0 6 to allow current flow
from the power supply through resistor R7 and diode 010 into
the base of Or. Transistor 0 6 is normally maintained in con-
FIGURE 4. USE OF A CAPACITOR BETWEEN TERMINALS 5
AND 7 TO DELAY THE OUTPUT PULSE OF THE
ZERO-VOLTAGE SWITCH
t The latching current Is the minimum current required to sustain
11-65
conduction immediately after the thyristor Is switched from the off
to the on state and the gate signal Is removed.
Application Note 6182
120V_.lOHz OPERA11ON
1 300 t--t---fl_-tl_t-I-t---f-+--+--I
tp. (POSITIVE dv/dt)
~~,~C\
oL-~--~--~-L--~~~~~~~
o 0.01 0.02 0.03 0.04 0.06 o.OS 0.07 0.01 0.00
~JH
EXTERNAL CAPACITANCE (jlF)
FIGURE5A.
l2OV_1OHz OPERAnON
PULSESm
i
m
m
m
--jil-- t
i
i
FREQ.(Hz)
T(ma)
t (lIS)
100
60
400
oL--L~~~~
o
__~-L~~~~~
0.01 0.02 0.03 0.04 0.06 O.OS 0.07 0.00 0.00 0.1
EXTERNAL CAPACITANCE (jlF)
f
1.25
12
FIGURE 6. TIMING RELATIONSHIP BETWEEN THE OUTPUT
PULSES OF THE ZERO-VOLTAGE SWITCH AND
THE AC UNE VOLTAGE
On/Off Sen81ng Amplifier
FIGURE5B.
FIGURE 5. CURVES SHOWING EFFECT OF EXTERNAL CAPACITANCE ON A. THE TOTAL OUTPUT PULSE
DURATION. AND B. THE TIME FROM ZERO
CROSSING TO THE END OF THE PULSE
Continuous gate current can be obtained H terminal 12 is
connected to terminal 7 to disable the zero crossing detector. In this mode. transistor
is always off. This mode of
operation is useful when comparator operation is desired or
when inductive loads must be switched. (If the capacitance
in the load circuit is low. most RFI is eliminated.) Care must
be taken to avoid overloading of the internal power supply in
this mode. A sensitill9 gate thyristor should be used. and a
resistor should be placed between terminal 4 and the gate of
the thyristor to limit the current. as pointed out later under
Special Application Considerations.
a,
Special Application Considerations
The discussion thus far has considered only cases in which
pulses are present all the time or not at all. The differential
sense amplifier conSisting of transistors a2. a3• a4. and a5
(shown in Figure 2) makes the zero-voltage switch a flexible
power control circuit. The transistor pairs a2-a4 and a3"a5
form a high beta composite p-n-p transistors in which the
emitters of transistors ~ and 5 act as the collectors of the
composite devices. These two composite transistors are
connected as a differential amplifier with resistor R3 acting
as a constant current source. The relative current flow in the
two "collectors" is a function of the dHference in voltage
between the bases of transistors 2 and 3. Therefore.
when terminal 13 is more positive than terminal 9. little or no
current flows in the "collector" of the transistor pair a2~'
When terminal 13 is negatill9 with respect to terminal 9.
most of the current flows through that path. and none in terminal 8. When current flows in the transistor pair 2-04 •
through the base emitter junction of transistor
and finally
through the diode 0 4 to terminal 7. Therefore. when V'3 is
equal to or more negative than Vg• transistor 1 is on. and
the output is inhibited.
a
a
a
a,.
a
a
Figure 6 indicates the timing relationship between the line
voltage and the zero-voltage switch output pulses. At 60Hz.
the pulse is typically 1~ wide; at 400Hz. the pulse width
is typically 121J.$. In the basic circuit shown. when the DC
logic signal is "high". the output is disabled; when it is "low".
the gate pulses are enabled.
In the circuit shown in FlQIJre 1. the voltage at terminal 9 is
derived from the supply by connection of terminals 10 and 11 to
form a precision wltage divider. This divider forms one side of a
transducer bridge. and the potentiometer Rp and the negative
temperature coefficient (NTC) sensor form the other side. At
11-66
Application Note 6182
low temperatures, the high resistance of the sensor causes ter·
minal13 to be positive with respect to terminal 9 so that the thyristor fires on fN8ry half cycle, and power is applied to the load.
As the temperature Increases. the sensor resistance decreases
until a balance is reached, and V13 approaches Va- AI. this
point, the transistor pair QA tums 00 and inhibits any further
pulses. The controlled temperature is adjusted by wriation of
the wlue of the poIentiometer Rp For cooling service, either the
positions of Rp and the sensor may be re\l8rsed or terminals 9
and 13 may be interchanged.
The low bias current of the sensing amplifier parmits opera·
tion with sensor impedances of up to 0.1 MO at balance
without introduction of substantial error (i.e., greater than 5
percent). The error may be reduced if the internal bridge elements, resistors R4 and Rs, are not used, but are replaced
with resistances which equal the sensor impedance. The
minimum wlue of sensor impedance is restricted by the cur·
rent drain on the internal power supply. Operation of the
zero-voltage switch with low impedance sensors is discussed later under Special Application Considerations. The
voltage applied to terminal 13 must be greater than 1.8V at
all times to assure proper operation.
temperatures. As the sensor resistance increases, the volt·
aga at terminal 14 rises toward the supply voltage. At a
voltage of approximately BV, the zener diode 0 15 breeks
down and turns on transistor 10, which then turns off tran·
sistor Os and the thyristor. If the supply voltage is not at least
0.2 volt more positive than the breakdown voltage of diode
0 15, activatioo of the protection circuit is not possible. For
this reason, loading the internal supply may cause this circuit
to malfunction, as may the selection of the wrong external
supply voltage. Figure 7 shows a guide for the proper opera·
tion of the protection circuit when an external supply is used
with a typical integrated circuit zero-voltage switch.
a
Protection ClrcuH
A special feature of the CA3059 zero-voltage switch is the
inclusion of an interlock type of circuit. This circuit removes
power from the load by interrupting the thyristor gate driw if
the sensor either shorts or opens. Howewr, use of this cir·
cuit places certain constraints upon the user. Specifically,
effective protectioo circuit operation is dependent upon the
following conditions:
410255075
AMBIENT TEMPERATURE ("e)
FIGURE 7. OPERAllNG REGIONS FOR BUILT-IN PROTECTION
CIRCUITS OF A TYPICALZEROoVOLTAGE SWITCH.
1. The circuit configuration of Figure 1 is used, with an inter·
nal supply, no external load on the supply, and terminal 14
connected to terminal 13.
2. The value of potentiometer Rp and of the sensor resis·
tance must be between 20000 and 0.1 MO.
3. The ratio of sensor resistance and Rp must be greater
than 0.33 and less than 3.0 for all normal conditions. (If either of these ratios is not met with an unmodified sensor,
a series resistor or a shunt resistor must be added to avoid
undesired activation of the circuit.)
The protectiw feature may be applied to other systems
when operation of the circuit is understood. The protection
circuit consists of diodes 0 12 and 0 15 and transistor 10.
Diode 0 1 activates the protection circuit if the sensor shown
in Figure 1 shorts or its resistance drops too low in value, as
follows: Transistor 6 is 00 during an output pulse so that the
junction of diodes 0 8 and 0 12 is 3 diode drops (approximately 2V) above terminal 7. As long as V 14 is more positiw
or only 0.15 volt negative with respect to that point, diode
0 12 does not conduct, and the circuit operates normally. If
the voltage at terminal 14 drops to 1 volt, the anode of diode
0 8 can haw a potential of only 1.B to 1.7V, and current does
not flow through diodes 0 8 and 0 9 and transistor 8 . The
thyristor then turns off.
a
a
a
The actual threshold is approximately 1.2Vat room tempera·
ture, but decreases 4mV per degree C at higher
Special Application Considerations
As pointed out previously, the Harris integrated circuit zerovoltage switches (CA3059 and CA3079) are exceptionally
versatile units than can be adapted for use in a wide variety
of power control applications. Full advantage of this wrsatil·
ity .can be reafized. howewr, only if the user has a basic
understanding of sewral fundamental considerations that
apply to certain types of applications of the zero-voltage
switches.
Operating Power Options
Power to the zero-voltage switch may be deriwd directly
from the /IC, line, as shown in Figure 1, or from an external
DC power supply connected betwean terminals 2 and 7, as
shown in Figure 8. When the zero-voltage switch is operated
directly from the /IC, line, a dropping resistor Rs of 5,0000 to
10,0000 must be connected in series with terminal 5 to limit
the current in the switch circuit. The optimum value for this
resistor is a function of the average current drawn from the
internal DC power supply, either by external circuit elements
or by the thyristor trigger circuits, as shown in Figure 9. The
chart shown in Figure 1 indicates the value and dissipation
rating of the resistor Rs for AC line voltages 24, 120, 208 to
230, and 277V.
11-67
z
o
-tJ)
!;;":w
(.)~
-0
itz
a..
<
Application Note 6182
sufficient to trigger the triac on the positive going cycle, but
insufficient to trigger the device on the negative going cycle
of the triac supply voltage. This effect introduces a half
cycling phenomenon, i.e., the triac is turned on during the
positive half cycle and turned off during the negative half
cycle.
TRIGGER
>-+---{,4
8.3rns
~
PULSES
TO
THYRISTOR
GATE
~~o~: I-'-"""'-'"r'-...Lf'-+--'-r'-.Lf-+-...Lf'--'":'---',"--
Vl
LOAD
VOLTAGE
ALL RESISTANCE
VALUES ARE IN {1
FIGURE 8. OPERATION OF THE ZERO-VOLTAGE SWITCH
FROM AN EXTERNAL DC POWER SUPPLY CONNECTED BETWEEN TERMINALS 2 AND 7.
6.SF~~~f=F=f=~~~L
~ 6.0r--~~~-r-~r--r--~~r--r-~
"~
<5 5.5 r--r--I+-\r-~r--r--r--PrTr-~
>
~
:::>
5.0 1-_1-_1--\-1-\---11-_1-_1-_1--\-1--1
g
4.51--1--I-.....lHHI--I--I--r--I--I
II>
FIGURE 10. HALF CYCLING PHENOMENON IN THE ZEROVOLTAGE SWITCH
Several techniques may be used to cope with the half cycling
phenomenon. If the user can tolerate some hysteresis in the
control, then positive feedback can be added around the differential amplifier. Figure 11 illustrates this technique. The
tabular data in the figure lists the recommended values of
resistors Rl and R2 for different sensor impedances at the
control point. -
120VRMS, S0-60Hz OPERATION
~
f--t--f-.....,---t--t--f--.l-....._ + - j f -...
4.0 J--f--f--t-\,--r--r--r--+--t--I
3.5:'0--+--+2--+3--.l:---+--+--!o---!-8-...J
EXTERNAL LOAD CURRENT (rnA)
FIGURE 9. DC SUPPLY VOLTAGE AS A FUNCTION OF EXTERNAL LOAD CURRENT FOR SEVERAL VALUES
Half Cycling Effect
The method by which the zero-voltage switch senses the
zero crossing of the AC power results in a half cycling
phenomenon at the control point. Figure 10 illustrates this
phenomenon. The zero-voltage switch senses the zerovoltage crossing every half cycle, and an output, for example
pulse No.4, is produced to indicate the zero crossing.
During the remaining 8.3ms, however, the differential
amplifier in the zero-voltage switch may change state and
inhibit any further output pulses. The uncertainty region of
the differential amplifier, therefore, prevents pulse No.5 from
triggering the triac during the negative excursion of the AC
line voltage.
When a sensor with low sensitivity is used in the circuit, the
zero-voltage switch is very likely to operate in the linear
mode. In this mode, the output trigger current may be
THERMISTOR - - NTC
Rl
R2
5K 12K 12K
12K 68K 12K
lOOK 200K 18K
FIGURE 11. CA3059 ON-OFF CONTROLLER WITH HYSTERESIS
If a significant amount (greater than ±10%) of controlled
hysteresis is required, then the circuit shown in Figure 12
may be employed. In this configuration, external transistor
0 1 can be used to provide an auxiliary timed delay function.
11-68
Application Note 6182
For applications that require complete elimination of half
cycling without the addition of hysteresis, the circuit shown in
Figure 13 may be employed. This circuit uses a CA3098E
integrated circuit programmable comparator with a zerovoltage switch. A block diagram of CA3098E is shown in
Figure 14. Because the CA3098E contains an integral
flip-flop, its output will be in either a "0" or "1" state.
Consequently the zero-voltage switch cannot operate in the
linear mode, and spurious half cycling operation is
prevented. When the signal input voltage at terminal 8 of the
CA3098E is equal to or less than the "low" reference voltage
(LR), current flows from the power supply through resistor R1
and Rz, and a logic "0" is applied to terminal 13 of the
zero-voltage switch. This condition turns off the triac. The
triac remains off until the signal input voltage rises to or
exceeds the "high" reference voltage (HR), thereby effecting
a change in the state of the flip-flop so that a logic "1" is
applied to terminal 13 of the zero-voltage switch, and
triggers the triac on.
120VAC
60Hz
FIGURE 12. CA3059 ON/OFF CONTROLLER WITH CONTROLLED HYSTERESIS
~'-'.....- -.....- . ,
+
.::t: 10~F
120V
60Hz
100~F
+
SENSOR
62K
10K
FIGURE 13. SENSITIVE TEMPERATURE CONTROL
PROGRAMMABLE BIAS
CURRENT INPUT QBIAS)
::
'"""""'""'""'"""'""'"
"HIGH"
REFERENCE
(HR)
SIGNAL
'11111111111111111111
v+
OUTPUT
' " " ' " " " CURRENT
: CONTROL
l:
<£>'-+---+-1
,:
"SINK"
: OUTPUT
:
INPUT C8}++-+I
"LOW"
REFERENCE (1}++-+-~
(LR)
,
t. . . .
I '............. ,......,
~
CA3098E
.............'
',I ............................" ........................" .................., ...",.................., ........., ...
......
""'''''I~
FIGURE 14. BLOCK DIAGRAM OF CA3098 PROGRAMMABLE SCHMITT TRIGGER
11-69
::
Application Note 6182
"Proportional Control" Systems
15
CEXT" 10"F
The on/off nature of the control shown in Figure 1 causes
some overshoot that leads to a definite steady state error.
The addition of hysteresis adds further to this error factor.
However. the connections shown in Figure 1SA. can be used
to add proportional control to the system. In this circuit. the
sense amplifier is connecled as a free running multivibrator.
At balance. the voltage at terminal 13 is much less than the
voltage at terminal 9. The output will be inhibited at all times
until the voltage at term inal 13 rises to the design differential
voltage between terminals 13 and 9; then proportional con·
trol resumes. The voltage at terminal 13 is as shown in Fig·
ure 156). When this voltage is more positive than the
threshold. power is applied to the load so that the duty cycle
is approximately 50 percent. With a 0.1 Mn sensor and val·
ues of Rp
01.Mil, R2
10.000n. and C EXT
10IlF. a
period greater than 3 seconds is achieved. This period
should be much shorter than the thermal time constant of
the system. A change in the value of any of these elements
changes the period. as shown in Figure 16. As the resis·
tance of the sensor changes. the voltage on terminal 13
moves relative to Vg . A cooling sensor moves V'3 in a posi·
tive direction. The triac is on for a larger portion of the pulse
cycle and increases the average power to the load.
=
=
=
120 AC
60Hz
100~F
+ 15VOC
FIGURE 15A.
~
,f
12
RQ.
II
a:
g
!/l 5
U>
w
a:
3
00
~p .. 82~
~/
~
100K
g:
20
40
60
80
100
FIRING RATE (FLASHEDIMINUTE)
120
FIGURE 16. EFFECT OF VARIATIONS IN TIME CONSTANT ELE·
MENTS ON PERIOD
As in the case of the hysteresis circuitry described earlier.
some special applications may require more sophisticated
systems to achieve either very precise regions of control or
very long periods.
Zero-voltage switching control can be extended to applications
in which it is desirable to have constant control of the
temperature and a minimization of system hysteresis. A closed
loop top bumer control in which the temperature of the cooking
utensil is sensed and maintained at a particular value is a good
example of such an application; the circuit for this control is
shown in Figure 17. In this circuit. a unijunction oscillator is
outboarded from the basic control by means of the internal
power supply of the zero-voltage switch. The output of this
ramp generator is applied to terminal 9 of the zero-voltage
switch and establishes a varied reference to the differential
amplifier. Therefore. gate pulses are applied to the triac
whenever the voltage at terminal 13 is greater than the voltage
at terminal 9. A varying duty cycle is established in which the
load is predominantly on with a cold sensor and predominantly
off with a hot sensor. For precise temperature regulation. the
time base of the ramp should be shorter than the thermal time
constant of the system but longer than the period of the 60Hz
line. Figure 18. which contains various waveforms for the
system of Figure 17. indicates that a typical variance of iO.SoC
might be expected at the sensor contact to the utensil.
Overshoot of the set temperature is minimized with approach.
and scorching of any type is minimized.
v
TRIAC
OFF
TRIAC
ON
FIGURE 15B.
FIGURE 15. USE OF THE CA3059IN A TYPICAL HEATING CON·
TROL WITH PROPORTIONAL CONTROL: A.
SCHEMATIC DIAGRAM. AND B. WAVEFORM OF
VOLTAGE AT ERMINAL 13
FIGURE17. SCHEMATIC DIAGRAM OF PROPORTIONAL ZEROVOLTAGE SWITCHING CONTROL
11·70
Application Note 6182
power factors. however. it occurs as the current through the
load becomes zero and reverses.
There are several methods for switching an inductive load at
the proper time. If the power factor of the load is high (Le.• if
the load is only slightly inductive). the pulse may be delayed
by addition of a suitable capacitor between terminals 5 and
7. as described previously. For highly inductive loads. however. this method is not suitable. and different techniques
must be used.
FIGURE 18. WAVEFORMS FOR THE CIRCUIT OF FIGURE 17.
Effect of Thyristor Load Characteristics
The zero-voltage switch is designed primarily to gate a thyristor that switches a resistive load. Because the output
pulse supplied by the switch is of short duration. the latching
current of the triac becomes a significant factor in determining whether other types of loads can be switched. (The
latching current value determines whether the triac will
remain in conduction after the gate pulse is removed.) Provisions are included in the zero-voltage switch to
accommodate inductive loads and low power loads. For
example. for loads that are less than approximately 4A,rns or
that are slightly inductive. it is possible to retard the output
pulse with respect to the zero-voltage crossing by insertion
of the capacitor Cx from terminal 5 to terminal 7. The insertion of capacitor Cx permits switching of triac loads that have
a slight inductive component and that are greater than
approximately 200W (for operation from an AC line voltage
of 120V,rns)' However. for loads less than 200W (for example. 70W). it is recommended that the user employ sensitive
gate triacs with the zero-voltage switch because of the low
latching current requirement of this triac.
For loads that have a low power factor. such as a solenoid
valve. the user may operate the zero-voltage switch in the
OC mode. In this mode. terminal 12 is connected to terminal
7. and the zero crOSSing detector is inhibited. Whether a
"high" or "low" voltage is produced at terminal 4 is then
dependent only upon the state of the differential comparator
within the integrated circuit zero-voltage switch. and not
upon the zero crossing of the incoming line voltage. Of
course. in this mode of operation. the zero-voltage switch no
longer operates as a zero-voltage switch. However. for may
applications that involve the switching of low current inductive loads. the amount of RFI generated can frequently be
tolerated.
For SWitching of high current inductive loads. which must be
turned on at zero line current. the triggering technique
employed in the dual output over-under temperature controller and the transient free switch controller described
subsequently in this Note is recommended.
SwHchlng of Inductive Loads
For proper driving of a thyristor in full cycle operation. gate
drive must be applied soon after the voltage across the
device reverses. When resistive loads are used. this reversal
occurs as the line voltage reverses. With loads of other
If gate current is continuous. the triac automatically commutates because drive is always present when the voltage
reverses. This mode is established by connection of terminals 7 and 12. The zero crossing detector is then disabled so
that current is supplied to the triac gate whenever called for
by the sensing amplifier. Although the RFI eliminating function of the zero-voltage switch is inhibited when the zero
crossing detector is disabled. there is no problem if the load
is highly inductive because the current in the load cannot
change abruptly.
Circuits that use a sensitive gate triac to shift the firing point
of the power triac by approximately 90 degrees have been
designed. If the primary load is inductive. this phase shift
corresponds to firing at zero current in the load. However.
changes in the power factor of the load or tolerances of components will cause errors in this firing time.
The circuit shown in Figure 19 uses a CA3086 integrated
circuit transistor array to detect the absence of load current
by sensing the voltage across the triac. The internal zero
crossing detector Is disabled by connection of terminal 12 to
terminal 7. and control of the output is made through the
external inhibit input. terminal 1. The circuit permits an
output only when the voltage at point A exceeds two VBE
drops. or 1.3v' When A is positive. transistors 0 3 and 0 4
conduct and reduce the voltage at terminal 1 below the
inhibit state. When A is negative. transistors 0 1 and O2
conduct. When the voltage at point A is less than ±1.3V.
neither of the transistor pairs conducts; terminal 1 is then
pulled positive by the current in resistor R3 • and the output is
inhibited.
The circuit shown in Figure 19 forms a pulse of gate current
and can supply high peak drive to power triacs with low average current drain on the internal supply. The gate pulse will
always last just long enough 10 latch the thyristor so that
there is no problem with delaying the pulse to an optimum
time. As in other circuits of this type. RFI results if the load is
not suitable inductive because the zero crossing detector is
disabled and initial turn on occurs at random.
The gate pulse forms because the voltage at point A when
the thyristor is on is less than 1.3V; therefore. the output of
the zero-voltage switch is inhibited. as described above.
The resistor divider Rl and R2 should be selected to assure
this condition. When the triac is on. the voltage at point A is
approximately one third of the instantaneous on state
voltage (VT) of the thyristor. For most thyristors. VT (max) is
less than 2V. and the divider shown is a conservative one.
When the load current passes through zero. the triac
commutates and turns off. Because the circuit is still being
11-71
Application Note 6182
driven by the line voltage, the current in the load attempts to
reverse, and voltage increases rapidly across the "turnedoff" triac. When this voltage exceeds 4V, one portion of the
CA3086 conducts and removes the inhibit signal to permit
application of gate drive. Turning the triac on causes the
voltage across it to drop and thus ends the gate pulse. If the
latching current has not been attained, another gate pulse
forms, but no discontinuity in the load current occurs.
1=~
120VAC
50-60Hz
FlGURE20A.
40
NYC
SENSOR
:c
30
!.
!Zw
II:
II:
8
0
20
5
~
w
A.
1:t
10
0~0-------.~1-------~~~--~
QATE VOLTAGE (Va) M
FIGURE 19. USE OF THE CA3059 TOGETHER WITH 3086 FOR
SWITCHING INDUCTIVE LOADS
Provision of Negative Gate Current
Triacs trigger with optimum sensitivity when the polarity of
the gale voltage and the voltage at the main terminal 2 are
similar (1+ and II· modes). Sensitivity is degraded when the
polarities are opposite (I· and 111+ modes). Although Harris
triaes are deSigned and specified to have the same
sensitivity in both I· and 111+ modes, some other types have
very poor sensitivity in the 111+ condition. Because the
zero-voltage switch supplies positive gate pulses, it may
not directly drive some high current triacs of these other
types.
The circuit shown in Figure 20A. uses the negative going
voltage at terminal 3 of the zero-voltage switch to supply a
negative gate pulse through a capaCitor. The curve in Figure
206. shows the approximate peak gate current as a function
of gate voltage VG• Pulse width is approximately SOlIS.
FIGURE20B.
FIGURE 20. USE OF THE CA3059 TO PROVIDE NEGATIVE
GATE PULSES: A. SCHEMATIC DIAGRAM; B.
PEAK GATE CURRENT (FAT TERMINAL 3) AS A
FUNCTION OF GATE VOLTAGE
Operation with Low Impedance Sensors
Although the zero-YOItage switch can operate satisfactorily with
a wide range of sensors, sensitivity is reduced when sensors
with impedances greater than 2O,oooa are used. Typical sensitivity is one percent for a 5-E3-o
HEATERS
~
LAMPS
SOUDSTATE
POWER THYRISTORS
-+
-
-+
SENSORS
~
PHOTOCELLS
o-E3-o
PTCINTC
THERMISTORS
-0"'0UMIT SWITCHES
FIGURE 24. THE ZERO-VOLTAGE SWITCH AND THYRISTOR
AS AN INTERFACE
FIGURE 22. SCHEMATIC DIAGRAM OF CIRCUIT FOR USE
WITH LOW RESISTANCE SENSOR
When electrical isolation between the logic circuit and the load
is necessary, the Isolated-Input technique shown in Figure
258. is used. In the technique shown, optical coupling is used
11-73
z
o
-U)
!;i:w
()I-
-0
~z
0..
c(
Application Note 6182
to achieYe the necessary isolation. The logic output transistor
switches the light source portion of the isolator. The light sensor
portion changes from a high impedance to a low impedance
when the logic output transistor is switched from off to on. The
light sensor is connected to the differential amplifier Input of the
zero-voltage swMch, which senses the change of impedance at
a threshold IeIIeI and switches the load on as In FlQure 25A.
_
Sensor Isolation
In many applications, electrical isolation of the sensor from
the AC Input line is desirable. Several Isolation techniques
are shown in Figures 26, 27, and 28.
Transformer Isolation· In Figure 26, a pulse transformer is
used to provide electrical isolation of the sensor from incoming AC power lines. The pulse transformer T1 isolates the
sensor from terminal No. 1 of the triac Y l' and transformer
T2 isolates the CA3059 from the power lines. Capacitor C1
shifts the phase of the output pulse at terminal No.4 in order
to retard the gate pulse delivered to triac Y1 to compensate
for the small phase shift introduced by transformer T1.
Many applications require line isolation but not zero-voltage
switching. A line isolated temperature controller for use with
inductive or resistive loads that does not include zero-voltage switching is shown In Figure 27.
DIRECT INPUT
In temperature monitoring or control applications the sensor
may be a tamperature dependent element such as a resistor, thermistor, or diode. The load may be a lamp, bell, horn,
recorder or other appropriate device connected In a feedback relationship to the sensor.
+V
For the purpose of the following explanation, assume that
the sensor Is a resistor having a negative temperature coefficient and that the load is a heater thermally coupled to the
sensor, the object being to maintain the thermal coupling
medium at a desired reference temperature. Assume initially
that the temperature at the coupling medium is low.
FIGURE 25B.
FIGURE25. BASICINTERFACINGTECHNIQUES:A.DIRECTINPUT; B. ISOLATED INPUT
The operating potentials applied to the bridge circuit produce
a common mode potential, VCM ' at the Input terminals of the
CA3094. Assuming the bridge to have been initially balanced (by adjustment of R4 ), the potential at point A will
UK
1W
1:lOVAC
Hz
CJ.47JlF
100..F
15VDC -
KNGHT
54E-1421
(ORECM'L)
DC RESISTANCE 510
FIGURE 26. ZERO-VOLTAGE SWITCH, ONIOFF CONTROLLER WITH AN ISOLATED SENSOR
11-74
Application Note 6182
increase when temperature is low since it was assumed that
the sensor has a negative temperature coefficient. The
potential at the noninverting terminal, being greater than that
at the inverting terminal at the amplifier, causes the multivibrator to oscillate at approximately 10kHz. The oscillations
are transformer coupled through a current limiting resistor to
the gate of the thyristor, and trigger it into conduction.
When the thyristor conducts, the load receives AC input
power, which tends to increase the temperature of the sensor. This temperature increase decreases the potential at
point A to a value below that at point B and the multivibrator
is disabled, which action, in turn, turns off the thyristor. The
temperature is thus controlled in an ol/off fashion.
Capacitor C t is used to provide a low impedance path to
ground for feedback induced signals at terminal No. 5 while
blocking the direct current bias provided by resistor R t •
Resistor R2 provides current limiting. Resistor R3 limits the
secondary current of the transformer to prevent excessive
current flow to the control terminal of the CA3094.
Photocoupler Isolation· In Figure 28, a photocoupler provides electrical isolation of the sensor logic from the
incoming AC power lines. When a logic "1" is applied at the
input of the photocoupler, the triac controlling the load will be
turned on whenever the line voltage passes through zero.
When a Iogic"a" is applied to the photocoupler, the triac wiii
turn off and remain off until a logic "1" appears at the input of
the photocoupler.
(NOTE 2)
,---------:
: INPUT
6.8K
0.001
..,F
,:
!
:
NOTE:
1.
~
Determines Drive to TRIAC.
2. Snubber for Ught Inductive Loads.
FIGURE 27. A LINE ISOlATED TEMPERATURE CONTROLlER FOR USE WITH INDUCTIVE OR RESISTIVE LOADS; THIS CONTROLLER
DOES NOT INCLUDE ZERO-VOLTAGE SWITCHING.
Yt
120VAC
60Hz
z
o
-rn
~w
()~
-0
~z
INPUT
Q.
.-------- -. PHOTO
,
::.....
: COUPLED
], } "
, ISOLATOR
~ .. ------- )
FIGURE 28. ZERO-VOLTAGE SWITCH, 0NI0FF CONTROLLER WITH PHOTOCOUPLER
11-75
«
Application Note 6182
Temperature Control.....
Figure 29 shows a triac used in an ofIoff temperature controller
configuration. The triac is turned on at zero.voItage wI'leneIIer
the voltage Vs exceeds the reference YOItage VR' The transfer
characteristic of this system, shown in Figure 3OA, indicates
signifICant thermal OII9IShoots and undershoots, a well known
characteristic of such a system. The differential or hysteresis of
this system, howeIIer, can be further increased, if desired, by
the add~ion of POS~Ne feedback.
The ratio of the on-lo-off time of the triac within this time
interval depends on the thermal time constant of the system
and the selected temperature setting. Figure 31 illustrates
the principle of proportional control. For this operation,
power is supplied to the load until the ramp voltage reaches
a value greater than the DC control Signal supplied to the
oppos~e side of the differential amplifier. The triac then
remains off for the remainder of the time base period. As a
result, power is "proportioned' to the load in a direct relation
to the heat demanded by the system.
RAMP
SIGNAl..
...a'} IB
"-
LEVEL 2
LEVEL 3
8
50%
7ft.
POWER
POWER
OUTPUT
OUTPUT
llME-
FIGURE 31. PRINCIPLES OF PROPORTIONAL CONTROL
FIGURE 29. CA3058 ONIOFF TEMP. CONTROLLER
For precise temperature control applications, the proportional
control technique with synchronous switching is employed. The
transfer curve for this type of controller Is shown in Figure 306.
In this case, the duty cycte of the power supplied to the load Is
varied with the demand for heat required and the thermal time
constant (inertia) of the system. For example, when the temperature setting is increased in an ofIoff type of controller, full
power (100 percent duty cycle) Is supplied to the system This
effect results in sigliflCBnt temperature excursions because
there is no anticipatory circu~ to reduce the power gradually
before the actual set temperature Is achieved. However, in a
proportional control technique, less power Is supplied to the
load (reduced duty cycte) as the error signal is reduced (sensed
temperature approaches the set temperature).
For this application, a simple ramp generator can be realized
with a minimum number of actille and passille components.
A ramp having good linearity is not required for proportional
operation because of the nonlinearity of the thermal system
and the closed loop type of control. In the circuit shown in
Figure 32, the ramp voltage is generated when the capacitor
C1 charges through resistors Ro and R1• The time ~se of
the ramp is determined by resistors R2 and R3, capacitor C2,
and the breakover voltage of the Teccor HT-32 diac.
/II;
TYPE
1N3111S
1S01(
IN o--.t-",flI'r..,
1 MEG
Ro
TO PIN 2
YCC+lY
IN
120YAC
80Hz
TEMPERATURE
SETTING
TO PIN 7
·~""""""~~""~~""""~""""~~COOMMON
AU ReslstOlS 112 Walt
Unless 0Iherwt&e Specified
FIGURE 3OA.
FIGURE 30B.
FIGURE 30. TRANSFER CHARACTERISTICS OF A. ONIOFF
AND B. PROPORTIONAL CONTROL SYSTEMS
Pin Connections Refer to
the CA3059
FIGURE 32. RAMP GENERATOR
Before such a system is implemented, a time base is chosen
so that the on time of the triac is varied within this time base.
When the YOItage across ~ reaches approximately 32V, the diac
switches and turns on the 2N3904 transistor and 1N914 diodes.
The capacitor C1 then discharges through the ooIIector-to-emiller
11-76
Application Nots 6182
junction of the transistor. This discharge time is the retrace or flyback time of the ramp. The circuk shown can generate ramp
times ranging from 0.3 to 2.0 seconds througl adjustment of A2.
For precise temperature regulation. the time base 01 the ramp
should be shorter than the thermal time constant of the system.
but long with respect to the period 01 the 60Hz IN wltage. FIQure 33 shows a triac connected for the proportional mode.
incoming line voltage. The motors. howeYer. are switched by
the triaes at zero current, as shown in Figure 34(b).
The problem of driving inductive loads such as these motors
by the narrow pulses generated by the zero-voltage switch is
solved by use of the sensitiw gate triac. The high sensitivity
of this device (3mA maximum) and low latching current
(approximately 9mA) permit synchronous operation of the
temperature controller circuit. In Figure 34(a). it is apparent
that. though the gate pulse Va of triac VI has elapsed. triac
V2 Is switched on by the current through Au. The low latch·
ing current of the sensitiw gate triac results in dissipation of
only 2W in ALI. as opposed to 10 to 20W when devices that
have high latching currents are used.
Figure 34(a) shows a dual output temperature controller that
drives two triaes. When the voltage Vs developed across the
temperature sensing network exceeds the reference wltage
VRI. motor No.1 tums 011. When the voHage across the net·
work drops below the reference voltage VR2 • motor No. 2 tums
011. Because the motors are inductive. the currents 1M 1 lag the
120VAC
80Hz
111OJ1F
15VDC
+
FIGURE 33. CA3059 PROPORTIONAL TEMPERATURE CONTROLLER
OM
6W
120VAIC
80Hz
~
lK
z
o-en
6W
!;iw
~b
~z
~
lK
I,u -IGATE (Y21
(8)
(b)
FIGURE 34. DUAL OUTPUT, OVER.tJNDER TEMPERATURE CONTROLLER (8) CIRCUIT, (b) VOLTAGE AND CURRENT WAVEFORMS
11·77
Application Note 6182
Electric Heat Application
For electric heating applications, the 40A triac and the zerovoltage switch constitute an optimum pair. Such a C9f1lbination provides synchronous switching and effectively replaces
the heavy-duty contactors which easily degrade as a result
of pitting and wear-out from the switching transients. The
salient features of the 40A triac are as follows:
1. 300A single surge capability (for operation at 60Hz).
2. A typical gate sensitivity of 20mA in the 1(+) and 111(+) modes.
3. Low on state voltage of 1.5V maximum at 40A.
4. Available VOROM equal to 6OOV.
Figure 35 shows the circuit diagram of a synchronous
switching heat staging controller that is used for electric
heating systems. Loads as heavy as 5kW are switched
sequentially at zero-voltage to eliminate RFI and prevent a
dip in line voltage that would occur if the full 25kW were to be
switched simultaneously.
Transistor 0 1 and C4 are used as a constant current source
to charge capacitor C in a linear manner. Transistor O2 acts
as a buffer stage. When the thermostat is closed, a ramp
voltage is provided at output Eo At approximately 3 second
intervals, each SkW heating element is switched onto the
power system by its respective triac. When there is no further demand for heat, the thermostat opens, and capacitor C
discharges through R 1 and R2 to cause each triac to turn off
in the reverse heating sequence. It should be noted that
some hail cycling occurs before the heating element is
switched fully on. This condition can be attributed to the
inherent dissymmetry of the triac and is further aggravated
by the slow rising ramp voltage applied to one of the inputs.
The timing diagram in Figure 36 shows the turn-on and turnoff sequence of the heating system being controlled.
Seemingly, the basic method shown in Figure 35 could be
modified to provide proportional control in which the number
of heating elements switched into the system, under any
given thermal load, would be a function of the BTU's
required by the system or the temperature differential
between an indoor and outdoor sensor within the total system environment. That is, the closing of the thermostat
would not switch in all the heating elements within a short
time interval, which inevitable results in undesired temperature excursions, but would switch in only the number of
heating elements required to satisfy the actual heat load.
UK
~ ............:
51(
. .
THERMOSTAT OR :
MANUAl SWITCH ,
!.......
:
:
_.I
All Resistors 112W, Unless Otherwise Specified.
Transistors Q10 Q~ and
are Part of CA3096E
Integrated Circuit N-P-N/P-N-P Transistor Arr8fi.
a..
FIGURE 35. SYNCHRONOUS SWITCHING HEAT STAGING CONTROLLER USING A SERIES OF ZERO-VOLTAGE SWITCHES
11-78
Application Note 6182
incorporates solid-state reliability while being neater, more
easily calibrated, and containing less costly system wiring.
L'
~o---------------'-<
I
POFF
I
I
::
4
3
2
,
220 V
/Ie
FIGURE 36. RAMP VOLTAGE WAVEFORM FOR THE HEAT
STAGING CONTROLLER
:
:
I
~
.... -.
P1
NTC
SENSOR
Oven/Broiler Control
Zero-voltage switching is demonstrated in the OIIen control
circuit shown in Figure 37. In this circuit, a sensor element is
included in the 01lel1 to provide a closed loop system for
accurate control of the oven temperature.
As shown in Figure 37, the temperature of the oven can be
adjusted by means of potentiometer R" which acts, together
with the sensor, as a voltage divider at terminal 13. The voltage at terminal 13 is compared to the fixed bias at terminal 9
which is set by internal resistors R4 and Rs. When the oven
is cold and the resistance of the sensor is high, transistors
Q 2 and Q 4 are off, a pulse of gate current is applied to the
triac, and heat is applied to the oven. Conversely, as the
desired temperature is reached, the bias at terminal 13 turns
the triac off. The closed loop feature then cycles the 01lel1
element on and off to maintain the desired temperature to
approximately ±2"C of the set value. Also, as has been
noted, external resistors between terminals 13 and 8, and 7
and 8, can be used to vary this temperature and provide hysteresis. In Figure 11, a circuit that provides approximately 10
percent hysteresis is demonstrated.
In addition to allowing the selection of a hysteresis value, the
flexibility of the control circuit permits incorporation of other
features. A PTC sensor is readily used by interchanging terminals 9 and 13 of the circuit shown in Figure 37 and
substituting the PTC for the NTC sensor. In both cases, the
sensor element is directly returned to the system ground or
common, as is often desired. Terminal 9 can be connected
by external resistors to provide for a variety of biasing, e.g.,
to match a lower resistance sensor for which the switching
point voltage has been reduced to maintain the same sensor
current.
To accommodate the self-cleaning feature, external switching, which enables both broiler and oven units to be
paralleled, can easily be incorporated in the design. Of
course, the potentiometer must be capable of a setting such
that the sensor, which must be characterized for the high,
self-clean temperature, can monitor and establish control of
the high temperature, self-clean mode. The ease with which
this self-clean mode can be added makes the overall solid
state systems cost competitive with electromechanical systems of comparable capability. In addition, the system
uo---------+-----------------~
F1GURE37. SCHEMATIC DIAGRAM OF BASIC OVEN CONTROL
Integral Cycle Temperatura Controller (No half cycling)
If a temperature controller which is completely devoid of half
cycling and hysteresis is required, then the circuit shown in
Figure 38 may be used. This type of circuit is essential for
applications in which half cycling and the resultant DC component couid cause OIIerheating of a power transformer on
the utility lines.
In the integral cycle controller, when the temperature being
controlled is low, the resistance of the thermistor is high, and
an output signal at terminal 4 of zero volts is obtained. The
SCR (y,), therefore, is turned off. The triac (Y2) is then triggered directly from the line on positive cycles of the AC
voltage. When Y2 is triggered and supplies power to the load
RL, capacitor C is charged to the peak of the input voltage.
When the AC line swings negative, capacitor C discharges
through the triac gate to trigger the triac on the negative half
cycle. The dlode-resistor-capacitor 'slaving network" triggers
the triac on negative half cycle to provide only integral cycles
of AC power to the load.
When the temperature being controlled reaches the desired
value, as determined by the thermistor, then a positive voltage level appears at terminal 4 of the zero-voltage switch.
The SCR then starts to conduct at the beginning of the positive input cycle to shunt the trigger current away from the
gate of the triac. The triac is then turned off. The cycle
repeats when the SCR is again turned OFF by the zero-voltage switch.
The circuit shown in Figure 39 is similar to the configuration
in Figure 38 except that the protection circuit incorporated in
the zero-voltage switch can be used. In this new circuit, the
NTC sensor is connectectbetween terminals 7 and 13, and
transistor Co inverts the signal output at terminal 4 to nUllify
the phase reversal introduced by the SCR (Y,). The internal
power supply of the zero-voltage switch supplies bias current
to transistor Q()o
11-79
z
o- 0
!;(w
~b
~z
~
Application Note 6182
Of course, the circuit shown in Figure 39 can readily be converted to a true proportional Integral cycle temperature
controller simply by connection of a positive going ramp
voltage to terminal 9 (with terminals 10 and 11 open), as
previously discussed in this Note.
MYa
va
IN4OO3
......,.,._........- - ' . 0
120VAC
MYI
1N4003
80Hz
100!tF
1SVDc +
1N4003
1K
2W
(NOTE 1)
ISKW
LOAD
(HEATER)
~
C
D.5jIF
2OOVoc
NOTE:
1. For proportional operation open terminals 10, 11 and 13, and connect positive ramp voltage to terminal 13.
2. SCR selected for lOT = SmA maximum.
FIGURE 38. INTEGRAL CYCLE TEMPERATURE CONTROLLER IN WHICH HALF CYCLING EFFECT IS EUMINATED
Va
Va
IN4OO3
0
120VAC
MYI
1N4003
VI
60Hz
MYa
1~~+
IN4OO3
1K
'IN
2~
ISKW
LOAD
(HEATER)
C
"'-
NOTE:
1. For proportional operation open terminals 9, 10 and 11, and connect positiVe ramp voltage to terminal 9.
2. SCR selected for lOT = SmA maximum.
FIGURE 39. CA3058INTEGRAL CYCLE TEMPERATURE CONTROLLER THAT FEATURES A PROTECTION CIRCUrr AND NO HALF
CYCLING EFFECT
11-80
Application Note 6182
Thermocouple Temperature Control
Figure 40 shows the CA3080A operating as a preamplifier
for the zero-voltage switch to form a zero-voltage switching
circuit for use with thermocouple sensors.
ometer A, drives the voltage divider network A3 , ~ so that
reference voltages over the range of 0 to 20mV can be
applied to noninverting terminal 3 of the comparator. Whenever the voltage developed by the thermocouple at terminal
2 is more positive than the reference voltage applied at terminal 3, the comparator output is toggled so as to sink
current from terminal 9 of the ZVS; gate pulses are then no
longer applied to the triac. As shown in Figure 41, the circuit
is provided with a control point "hysteresis" of 1.25mV.
Nulling of the comparator is performed by means of the following procedure: Set R, at the low end of its range and
short the thermocouple output signal appropriately. If the
triac is in the conductive mode under these conditions,
adjust nulling potentiometer As to the point at which triac
conduction is interrupted. On the other hand, if the triac is in
the nonconductive mode under the conditions above, adjust
Rs to the point at which triac conduction commences. The
thermocouple output signal should then be unshorted, and
R, can be set to the voltage threshold desired for control circuit operation.
1l1li14
All Resistors 112W,
Unless Otherwise Specified
FIGURE 40. THERMOCOUPLE TEMPERATURE CONTROL
WITH ZERO-VOLTAGE SWITCHING
Machine Control and Automation
Thermocouple Temperature Control with Zero-Voltage
Load SWitching
Figure 41 shows the circuit diagram of a thermocouple temperature control system using zero-voltage load switching. It
should be noted that one terminal of the thermocouple is
connect to one leg of the supply line. Consequently, the thermocouple can be "ground referenced", provided the
appropriate leg of the AC line is maintained at ground. The
comparator, A, (a CA3130), is powered from a 6.4V source
of potential provided by the zero-voltage switch (ZVS) circuit
(a CA3079). The ZVS, in turn, is powered off-line through a
series dropping resistor R8 . Terminal 4 of the ZVS provides
trigger puises to the gate of the load switching triac in
response to an appropriate control signal at terminal 9.
The earlier section on interfacing techniques indicated several techniques of controlling AC loads through a logic
system. Many types of automatic equipment are not complex
enough or large enough to justify the cost of a flexible logic
system. A special circuit, deSigned only to meet the control
requirements of a particular machine, may prove more ec0nomical. For example, consider the simple machine shown
in Figure 42; for each revolution of the motor, the belt is
advanced a prescribed distance, and the strip is then
punched. The machine also has variable speed capability.
R,
10K
REF.~.i-Y~3)'I
z
VOLT.
o
-en
~w
(,)1-
ADJ
FIGURE 42. STEP-AND-PUNCH MACHINE
R.
lK
,..
5.111
Hysteresis = R31R4 x 6.4V = 1K/5.1 M x 6.4V = 1.25mV
FIGURE 41. THERMOCOUPLE TEMPERATURE CONTROL
WITH ZERO-VOLTAGE SWITCHING
The CA3130 is an ideal choice for the type of comparator circuit shown in Figure 41 because it can "compare" low
voltages (such as those generated by a thermocouple) in the
proximity of the negative supply rail. Adjustment of potenti-
The typical electromechanical control circuit for such a
machine might consist of a mechanical cambank driven by a
separate variable speed motor, a time delay relay, and a few
logic and power relays. Assuming use of industrial grade
controls, the control system could get Quite costly and large.
Of greater importance is the necessity to eliminate transients
generated each time a relay or switch energizes and deenergizes the solenoid and motor. Figure 43 shows such
transients, which might not affect the operation of this
machine, but could affect the more sensitive solid-state
equipment operating in the area.
11-81
-0
~z
CI..
;1JV ~ v
izzztstzzts#l
-,
r---17.~.
i i i
LAMP ~ IJIo I) '>
OUTPUT
W V '"
i
.a
~ IJIo
iVARIABLEi
$EFERENQE
I) '> i LEVELS io
wv
"'~
FIGURE 48. CIRCUIT DIAGRAM FOR 400Hz ZERO-VOLTAGE
SWITCHED LAMP DIMMER
Solid-State Traffic Flasher
Another application which illustrates the versatility of the zerovoitage switch. when used with Harris thyristors. involves
switching traffic control lamps. In this type of application. it is
essential that a triac withstand a current surge of the lamp load
on a continuous basis. This surge results from the difference
between the cold and hot resistance of the tungsten filament. If
it is assumed that triac turn-on is at 90 degrees from the zerovoitage crossing. the flf'St current surge peak is approximately
ten times the peak steady state rms value.
When the triac randomly switches the lamp. the rate of current
rise difdt is limited only by the source inductance. The triac difdt
rating may be exceeded in some power systems. In many
cases. exceeding the rating results in excessive current concentrations in a small area of the device which may produce a
hot spot and lead to device failure. Critical applications of this
nature require adequate drive to the triac gate for fast turn on.
In this case. some inductance may be required in the load circuit to reduce the initial magnitude of the load current when the
triac is passing through the active region. Another method may
be used which involves the switching of the triac at zero line
voltage. This method involves the supply of pulses to the triac
gate only during the presence of zero voltage on the N:; line.
FIGURE 46. WAVEFORMS FOR 60Hz PHASE CONTROLLED
LAMP DIMMER
400Hz UNE
VOLTAGE
UNE
SYNCED
RAMP
tJ
FIGURE 47. WAVEFORMS FOR 400Hz ZERO-VOLTAGE
SWITCHED LAMP DIMMER
In 400Hz applications it may be necessary to widen and shift
the zero-voltage switch output pulse (which is typically 12ms
wide and centered on zero-voltage crossing). to assure that
sufficient latching current is available. The 4K resistor (terminal
Figure 49 shows a Circuit in which the lamp loads are switched
at zero line voltage. This approach reduces the initial difdt.
decreases the required triac surge current ratings. increases
the operating lamp life. and eliminates RFI problems. This circuit consists of two triaes. a flip-flop (FF-1). the zero-voltage
switch. and a diac pulse generator. The flashing rate in this circuit is controlled by potentiometer R. which provides between
10 and 120 flashes per minute. The state of FF-1 determines
the triggering of trlacs Y, or Y2 by the output pulses at terminal
4 generated by the zero crossing circuit. Transistors 0, and O2
inhibit these pulses to the gates of the Iriaes until the triacs turn
on by the logical·1" Nee high) state of the flip-flop.
11-83
Application Note 6182
120VAC
60Hz
·
:~..
•
:
-iN4003---------..............:
•
270K
: 5MEG __ R
~
·
2W
Vee
.!
UK
5
:
18K CL
112W
:GENERAnON
Q
"1"
5-IIK
FF1
,
!DlACPULSE
14
+-__.....
3 _
L -_
•
,--------------.. ------. --.. -~
FIGURE 49. SYNCHRONOUS SWITCHING TRAFFIC FLASHER
The arrangement describe can also be used for a synchronous, sequential traffIC controller system by addition of one
triac, one gating transistor, a "divide-by-three" logic circuit,
and modification in the design of the diac pulse generator.
Such a system can control the familiar red, amber, and
green traffic signals that are found at many intersections.
previously may be used. In this circuit, ZVS 1 is the master
control unit and ZV~ is slawd to the output of ZVS 1 through
its inhibit terminal (terminal 1). When power is applied to
lamp No.1, the voltage of terminal 6 on ZVS 1 is high and
ZVS2 is inhibited by the current in Rx. When lamp No. 1 is
off, ZV~ is not inhibited, and triac Y2 can fire. The power
supplies operate in parallel. The on/off sensing amplifier in
ZV~ is not used.
Transient Free Switch Controllers
The zero-voltage switch can be used as a simple solid-state
switching device that permits AC currents to be turned on or
off with a minimum of electrical transients and circuit noise.
The circuit shown in Figure 51 is connected so that, after the
control terminal 14 is opened, the electronic logic waits until
the power line voltage reaches a zero crossing before power
is applied to the load Zt.. Conversely, when the control terminals are shorted, the load current continues until it reaches a
zero crossing. This circuit can switch a load at zero current
whether it is resistiw or inductive.
The circuit shown in Figure 52 is connected to provide the
opposite control logic to that of the circuit shown in Figure
51. That is, when the switch is closed, power is supplied to
the load, and when the switch is opened, power is removed
from the load.
FIGURE SO. SYNCHRONOUS LIGHT FLASHER
Synchronous Ught Flasher
Figure 50 shows a simplified version of the synchronous
switching traffic light flasher shown in Figure 49. Flash rate is
set by use of the curve shown in Figure 16. If a more precise
flash rate is required, the ramp generator described
In both configurations, the maximum rms load current that
can be switched depends on the rating of triac Y2'
11-84
Application Note 6182
O.1I'F
2SVDC
10K
2W
10K
2W
120VAC
60Hz
MT,
lool'F
1SVDC
O.1I'F
200VDC
o
ON
NOTE:
1. If Y2' For Example, is a 40A TRIAC, then R, must be Decreased to Supply Sufficient IGT lor Y2.
FIGURE 51. ZERO-VOLTAGE SWITCH TRANSIENT FREE SWITCH CONTROLLER IN WHICH POWER IS SUPPLIED TO THE LOAD
WHEN THE SWITCH IS OPEN
120VAC
60Hz
io.
100
SK
112W
Y,
(NOTE II
MT,
lool'F
1SVDC
S1
Z
0
10K
112W
-U)
lK
!20!1S
90ns
4.SV at S4rnA
(Note 1)
3.2V at :>5.0mA
NOTE:
1. Refer to Agure 20; Rx equals SOOI_..:.
12
8,13
s
113 CD4OO7'\
11.1 CDI013A
3
10K
'---"I
11.1 CDI013A
>...;:.;_....•~:.:...:~________... •FF-1
113 CD4OO7'\
FIGURE 54. BLOCK DIAGRAM OF A POWER ONE SHOT CONTROL USING A ZERO-VOLTAGE SWITCH
Z
o
-CI)
~w
(JI-
-0
KZ
a..
Vo
~~:::
Sa
CAN BE SA OR
CAN DRlVEQ2
HALF BRIDGE
z
o
+Vo
-tJ)
!;;(UJ
V+IVol
NOTE: Diode 01 Is Necessary To Prevent Reverse
Emllter-Base Breakdown of ThInsIstor Switch SA
FIGURE 17. CAPACITOR-DIODE COUPLED VOLTAGE
MULTlPUER OUTPUT STAGES
FIGURE 18. TRANSFORMER-COUPLED OUTPUTS
General Applications Considerations
The CA 1524, in addition to having all the control circuits for
switching regulator applications, employs two output NPN
transistors. These transistors are internally current limited
11-101
gb
~
Do
c(
Z
Application Note 6915
and can be used In a variety of switching regulator configurations.
Three such modes are:
1. Single-ended single stage configurations for forward and
flyback converters.
2. Single-ended parallel output stages for switching regulators
3. Dual or individual stage configurations for push-pull, 112
bridge circuits, etc.
Single-Ended Applications
The single-ended configuration provides for simple regulator
designs in which an LC and diode filter network provide the
DC output voltage. The PWM controlled duty cycle can vary
from 0% to 45%.
The duty cycle variation depends on the divided reference
voltage applied to the error amplifier terminals. This voltage,
in turn, adjusts the comparator's trip IeIl8I to control the ON
time. Figure 11 shows the duty cycle variation vs. the error
amplifier output voltage (pin 9) for the CA 1524.
If the outputs are connected In parallel, the duty cycle can
range from 0% to 90"4 a normal mode for switching regulators. For flyback operation, care must be taken to prevent the
on time from exceeding 45% to allow for retrace In the
flyback transformer.
Dual"En~ Applications
The dual-e~ded configuration can be used for the following
applicationf:
1.
The selection of components - capacitors, diodes, inductors,
transformer cores, atc., depends primarily on the operating
frequency of the switching regulator. It is important,
therefore, that care be elf8rcised in the selection of these
components. Capacitors should have low equivalent series
resistance (ESR) and low equivalent series inductance
(ESL), because high ESR is the principal cause of capaCitor
ripple, and high ESL causes high frequency ringing in the
MHz region. Most capacitor manufacturers rate capacitance
at 120Hz, a frequency quite different from the 20kHz 100kHz operating frequency of PWM regulator circuits.
Because the characteristics of capacitors may change with
change in frequency, the careful selection of close tolerance
capaCitors will tend to offset any degradation in PWM
regulator performance resulting from the difference in the
frequency rating of capacitor vs PWM regulator circuit
operating frequency.
Free-wheeling diode clamps must have fast tum on and low
distributed capacitance. The DC resistance of inductors
should be kept low to minimize the effects of added losses
that may occur at high load currents. In addition, the
selection of the size and type of transformer core will also
depend on the input voltage range and on the output voltage
and current requirements.
Basic Switching Regulators
Figure 20 shows the basic switching regulator, the Buck or
Step-Down type. In this type of regulator Vo is always S; V IN •
The simplified waveforms for this regulator are shown in
Figure 21.
PuSh-~UII circuits
2. Voltage Multipliers; (capacitor diode filters)
t
3. Half or full bridge circuits
A
+-
The oscillator has a dead band feature to ensure against
both output transistors conducting simultaneously. This dead
band applies not only to the intemal transistors, but for any
additional drill8rs used for push-pull applications.
When using push-pull and bridge circuits, the dead time
becomes important. Since the frequency of the oscillator is
1/RTCr, a good method for establishing dead band time is to
select f first, CT second, and then RT. The value of Cr
determines the dead time or discharging rate of CT. The
curvas in Figures 8 and 10 are used for this purpose. The
oscillator provides a ramp at the CT terminal with an
equivalent dead time pulse at Pin 3 for slaving multiple
units. This terminal can also be used as an oscilloscope
sync. With an output resistance of 2Kn at Pin 3, capacitive
loading of this terminal will be adequate for most
applications, but for larger systems some type of external
dead time adjustment must be employed. To provide an
expansion of the dead time without loading the oscillator,
the simple 5k.a potentiometer and diode arrangement
shown in Figure 9 can be used. The output frequency of
each individual output stage is approximately half that of the
oscillator frequency. When the stages are connected in
parallel, fose = fOUT.
VIN
'-!-
+
Q1
l
B
I
CA1524
I PWM
~
U
C
Ct •
... D1
I
1
VO.VINX~~
VINTON
VO·--TON + TOFF
,
FIGURE 20. BUCK (STEP,DOWN) REGULATOR
The Buck Regulator shown in Figure 20 operates by
chopping an unregulated DC voltage. The frequency of the
circuit waveforms remains constant but the duty cycle is
varied to effect regulation. The output LC filter, together with
the free-wheeling diode D1, smooths the chopped
waveform. With Vo set at some selected level by means of
the reference voltage, the sample of the output voltage
applied t the input of the CA 1524 error amplifier adjusts the
duty cycle in response to changes In load currents. When
transistor 01 is turned on diode D1 is nonconductive and
current flows from VIN through L 1 to +Vo- When 01 is off, the
reserile energy in C1 provides the necessary current to the
load. The overall output regulation depends primarily on the
characteristics of the CA1524 and on the design of the output filter.
11-102
Application Note 6915
Switching regulator circuits are categorized for single-ended
and dual-ended (bridge) applications. The basic circuits
shown in Figures 22 through 30 include an inductive
element. In these circuits SA represents transistor A, SB
transistor B, and SAlSB indicated that both transistors can
be connected in parallel. A description of the single-ended
and dual-ended bridge configuration is given in subsequent
pages.
VIN
WAVEFORM AT A
V...VSAT
WAVEFORM AT •
For low-power applications from 50 to 100 watts.
·V~~~
-~~FLYIlACK CONVERTER
V...V SAT
WAVEFORM AT C
VAK
T _ TLOW
10
INDUCTOR CURRENT
IDC
FLYBACK CONVERTER WITH CLAMP WINDING
nME
OUTPUT VOLTAGE
Vo
VIN
VSAT
V'(SAT)PASS
VAK
10
Vo
The clamp winding returns excess stored energy to the line,
thereby prlMlllting avalanche In the switching transistor.
FIGURE 25. FLYBACK CONVERTER (OPERATING MODEL FOR
THIS CONVERTER IS THE BOOST REGULATOR)
= Unregulated DC Voltage
=
=
=
=
=
Saturation Voltage of CA1524 Oulput li"ansistor
Saturation Voltage of SwItching Pass li"ansistor
DIode on Voltage
Output Inductor Current with Irs DC Component
Regulated OUtput Voltage
For Iow-to-medium-power applications from 100 to 200
watts.
FIGURE 21. SIMPLIFIED WAVEFORM FOR BUCK (STEPDOWN) REGULATOR
Single-Ended Application.
For low-power applications up to 100 watts.
FORWARD CONVERTER
FIGURE 22. BUCK OR STEP-DOWN REGULATOR
FORWARD CONVERTER WITH DIODE CLAMP
FIGURE 26. FORWARD CONVERTER (OPERATING MOOEL FOR
THIS CONVERTER IS THE BUCK REGULATOR)
Dual-Ended (Bridge) Applications
FIGURE 23. BOOST OR STEP-UP REGULATOR
For Iow-to-medium-power applications from 100 to 200
watts.
SIlfSa
0"'1
FIGURE 24. VARIATION OF THE BOOST OR STEP-UP REGULATOR RESEMBLES THE FLYBACK REGULATOR
AND CAN BE EITHER STEP-UP OR STEP-DOWN
FIGURE 27. FLYBACK OR FORWARD CONVERTER WITH A
CLAMP WINDING
11-103
Application Note 6915
For high-power applications from 500 to 2000 watts.
For Medium-power applications from 200 to 500 watts.
SA CAN DRIVE Q1 AND Q4
FIGURE 28. PUSH-PULL OR DC-T()'DC CONVERTER
L---lf----i SA CAN DRIVE 02 AND Q3
For medium-ta-high power applications from 200 to 1000
watts.
sa
Q4
+o-~------------------~
FIGURE 30. FULL-BRIDGE CIRCUIT
Capacitor Cc and diode clamps have same function as in the
half-bridge circuit. In the full-bridge circuit full line IIOltage
can be applied to the primary winding to approximately
double the power output of the half-bridge circuit.
Q1 (CAN BE SAl
(S" CAN DRIVE Q1)
Regulator Applications
02 (CAN BE Sa)
(Sa CAN DRIVE 02)
The Variable SwHcher
FIGURE 29. HALF-BRIDGE CIRCUIT
Capacitor Cc (l.O!1F to 5.OJ1F range) minimizes transformer
saturation problems. Diode clamps can be used across each
transistor to reduce the effects of destructive switching
transients.
36
Voc
The following review of some of the characteristics and
unique design features of a variable switching pulse-widthmodulated (PWM) circuit will provide the equipment
designer with some of the basic principles of a PWM circuit
and its associated circuitry, and a better understanding of
the CA1524 Series ICs intended for this type of application.
2N6388
(PNP DARUNGTON)
01 _ _--_...J'>1"YYI>--,....,
7Y - 3llV
OA-3A
r-----~--_~~v~
D1-D4
L-___+
A15A
___
--~
RETURN
C6
-!-2Si" even at slow switchingspeeds.
11-119
z
o
-Cf)
!ci:w
0'-0
~z
a..
c(
Application Note 7254
4. The 'dynamic V(SAT)" curves are symmetrical during the
low drain voltage portion of the turn on and turn off portion.
5. The "dynamic V(SATJ" curves are lower in amplitude by a
factor of approximately two for the L2FET.
OO~-J-=~~~3~~4~~5~~6~~7~~--JUb:!
10
nME (juI)
are schematically implied by the left half of Figure 6. The
right half indicates the edge of the depletion width for several
drain voltages. Note how the JFET pinches off. such that
increased drain IIOitage is supported predominately by the
JFET. This structure is schematically represented as shown
in Figure 7. Note that the third quadrant diode is caused by
the p-n junction associated with the gate and drain characteristic (common to all JFETs). A parasitic n-p-n transistor is
not shown. nor is it discussed in this Note. Voltage node (4)
is within the device. and is not precisely a single node. as
represented.
FIGURE 7. SCHEMATIC REPRESENTATION OF THE CROSS
SECTION OF FIGURE 6
Interelectrode Capacitance
FIGURE 5. CHARACTERIZATION CURVES FOR REPRESENTATIVE DEVICES DRIVEN FROM A CURRENT
GENERATOR
Large Signal Equivalent Circuit of the
MOSFET
If we are to understand the differences and similarities of the
L2FET relative to the conventional power MOSFET, the
conventional power MOSFET must first be understood. Figure 6 shows a properly proportioned cross sectional view of
the power MOSFET.
SOURCE METAL
~\t.§K
I..·····..
p BODY
P+
JFET,
!
'.
",
'._
The equivalent circuit of Figure 7 contains four voltage
nodes. Therefore. six capaCitors will exist to couple these
nodes. The switching waveforms are determined by these
capacitors and the small signal equivalent circuit of the MOS
and JFET. Of course, the MOS and JFET small signal equivalent circuits are nonlinear functions of voltage and current
and invariant with frequency. Similarly, the capacitors are
nonlinear with voltage and current.
Industry data sheets show three terminal characterization of
this four node network at zero drain current. Under this condition. the transconductance and output resistance are zero
and infinity for both the MOS and the JFET. This condition
reduces the power MOSFET to the capacitor network of Figure 8, which may be replaced by three capacitors. Note that
this situation is valid only when no MOSFET current flows.
---- OV
i · · · ·....
i
DEP~~~N EDGE
.....------ 40V
MORAIN
FIGURE 6. CROSS SECTION OF POWER MOSFET
When the drain voltage is very low and the gate is forward
biased. an accumulation layer exists for the n- region
beneath the gate. This layer may be thought of as serving
the function of the drain for the lateral MOS. In addition. it
serves as a source for a vertical depletion mode JFET. The
gate of the JFET is formed by the body diffusion. particularly
in the neck region. The JFET drain is the n+ region usually
though of as being the MOSFET drain. This situation is
shown in Figure 6. where the cross sectional view of the
MOSFET is shown. The lateral MOS and the vertical JFET
FIGURE 8. CAPACITOR NETWORK REPRESENTATION OF
THE POWER MOSFET
When current does flow. node (4) of Figure 7 is a low impedance node due to the source follower characteristic of the
JFET. Similarly. nodes (1) and (3) are generally low impedance nodes by virtue of the ground reference and the load
resistance. Therefore, capacitive currents will usually be significant only to the input node. (2). Capacitors C'2' C 23 • and
C24 are examined below over most of the switching regime
when current is flowing.
11-120
Application Note 7254
Gate to Source Capacitance, C 12
Gate Voltage Plateau
When all of the die except the actual MOSFET cells are
ignored, Figure 6 shows that the gate to source capacitance
(C I2) is that from the poly gate upward through the thick
oxide to the source metal. In addition, there is a contribution
from the poly gate to the n+ source through the thin gate
oxide. Additionally a fringing capacitance exists at the edge
of the polysil gate. These components of C 12 are invariant
with voltage and current. There is a fourth component from
the poly gate to a region about haH way along the MOS
channel through the gate oxide. This component is actually
distributed, and varies somewhat with current and voltage.
As the gate voltage decreases, the drain voltage will
increase imperceptibly at first until the gate voltage drops
enough to bias the MOS into its constant current mode. AI
this point, the very high transconductance of the MOS is
consistent with very little change in gate voItaga to reduce
the current by several percent. Several percent change in
drain current corresponds to many volts in drain voltage. As
a result, the gate current no longer flows from C12 during the
constant gate voltage plateau.
Gate to Drain Capacitance, C23
Since C23 is still zero, all gate current must flow from C24 •
Assuming that the gate voltage is plateaued and that the
JFET is still heavily forward biased, node 4 of Figure 7 must
ramp at linear rate. Therefore, the JFET must also ramp at
this same rate.
Capacitor C23 exists only when no accumulation layer is
present beneath the poly gate. Otherwise, the accumulation
layer acts as an electrostatic shield. This layer exists whenever the drain voltage immediately beneath the gate oxide is
essentially negative relative to the poly gate. In addition, the
capacitive coupling from drain to gate diminishes greatly
when the JFET is pinched off. Therefore, C23 exists for only
a small range of drain voltage. In addition, it should decrease
rapidly as the pinCh-off voltage level is approached because
the effective area of concern is closed off Similarly to the
aperture of a camera (for a hex cell).
Gate to Internal Electrode CapaCitance,
~
Capacitor C24 is rather large for positive gate voltages. It is
made up of that area between the poly gate and the accumulation layer, plus some of the area between the poly gate
and the middle of the MOS channel. In both cases, the
dielectric is the thin gate oxide. So long as the gate voltage
is positive relative to the n- layer beneath the poly gate, the
accumulation layer exists and C24 is invariant. This accumulation layer ceases to exist when the external drain voltage
minus the IR drop through the n- neck region approximately
equals the gate voltage. The area associated with the accumulation layer (JFET cathode) rapidly decreases with
increased drain voltage. In addition, a depletion layer may
now form, leading to a further reduction of C24 .
Waveforms Expected from the Model
The following discussion relates the prior model discussion
to the waveforms of Figure 5. The discussion begins with the
gate voltage at +5V or +1 OV and the gate current equal to
zero. This condition corresponds to saturated behavior,
where the drain current is approximately equal to lo(max)
and the drain voltage equals lo(max) times Ros(ON).
Gate Voltage Slope - tOFF Delay
As time progresses, IG = -5mA, which must flow through C12
+ C23 + C24 of Figure 8 because the MOS and JFET are
both heavily biased into conduction. Therefore, dVJdt dV:I
dt nearly O. With large positive gate bias and drain voltage
near zero, C23 is zero and C 12 and C24 are constant. As a
result, the gate voltage should be a straight line with a slope
equal to:
=
=
Drain Voltage Shallow Siopa
dVrfdt '" IQlC24
(2)
Again this curve will approximate a straight line.
Drain Transition Voltage
As mentioned above, C24 rapidly decreases once the drain
voltage is slightly greater than the gate voltage. (Actually,
this voltage is the n- voltage directly beneath the gate oxide,
and differs from the drain voltage by an amount nearly equal
to loros(on).)
Since the drain voltage is still fairly low and the drain currant
has not changed much, the gate plateau voltage still exists.
Equation 2 still applies except that the value of C24 has
materially decreased and C23 has become finite. This situation results in a substantial increase in dVrfdt.
JFET Pinch Off Voltage - Drain Voltage Steep Slope
As the drain voltage approaches the pinch off voltage of the
JFET, the JFET comes out of saturation and starts to support
MOSFET drain voltage. The voltage gain of the active JFET
permits large changes in the JFET drain voltage for small
changes in its source-to-gate voltage. But the JFET sour-tagate voltage is the lateral MOS drain-ta-source voltage, which
is dam inated by equation 2 (but for low values of C24).
Gate Voltage Curvature from Platesu
z
As the drain voltage increases, the drain current decreases.
This condition requires significant decrease in gate voltage
until the gate threshold is approached. A significant portion
of the gate current must now flow through C12• This flow produces a gradual transition in the gate voltage and some
slowing of the drain voltage waveform.
Gate Voltage Slope - 'tON) Delay
When the drain is totally off, most of the gate current flows
from C 12• Again, this capacitance is constant, so that the
waveform is a straight line with a slope equal to:
(1)
11-121
(3)
o
-0
!(w
(.)1-
-0
itz
0ct
Application Note 7254
+15V
+2V
...,
ov--l L..
2,5,7NC
>~1~3-+-_ _ _.. MOSFET GATE
2K
10K
FIGURE 9. TEST CIRCUIT
New Switching Characterization for
Power MOSFETs
The above discussion suggests that a new method of char·
acterization may be provided for resistive switching with
power MOSFETs, where constant current gate drive is
employed during the transition time.' The below method
bears some similarity to the gate charge concept. 2 The state
of the gate charge is a continuous plot in this work, however,
rather than a single point. This approach permits a knowledge of all waveforms with any drive circuitry, rather than just
the total elapsed time. In addition, the total elapsed time is
fixed (at just under SO microseconds) by choosing the
required value of constant gate current. Circuit designers are
usually more comfortable with milliamperes and microseconds (although the product is charged in nanocoulombs).
Test Circuit - Drive
A test circuit is shown in Figure 9. The heart of this circuit is
the Harris CA3280 integrated circuit. This is an operational
transconductance amplifier (OTA) operated as a comparator.
An OTA is a current output circuit where the output current
and output transconductance are programmed by the amplifier bias current (lABel. Internal chip circuit feedback assures
an extremely high output impedance within a compliance
range established by the supply voltages. The circuit of Figure 9 is actually two OTA's in parallel. The linearizing diodes
on this chip are not used.
A value of IABC is established from the collector of the
2N4036. The current into the load (the gate of the MOSFET
under test) may be varied between +IABC and -IABC times a
constant of proportionality (approximately 0.9). The actual
value depends upon the input differential input voltage. As a
comparator, the differential voltage is large resulting in saturated behavior of ±IABC. If the gate voltage comes within a
volt of the rail voltages, this current goes to zero, producing a
clamping voltage. For the purposes of this Note, these supply voltages are adjusted to clamp 0 volts and +10 volts for
the normal n-channel MOSFET. The behavior of this IC is
excellent from submicroamperes to about 2.SmA. Higher
current may be achieved by stacking many CA3280 pack-
ages one on top of another and soldering the leads parallel
to the chips rather than wiring many sockets. However, this
arrangement may require an increase in the bypass capacitor values.
A CA3240E MOS input op amp is used as a unity gain follower. Otherwise, the 1mCl or 10mCl shunting impedance of
the scope would load the high impedance circuitry associated with the MOSFET gate.
Testing Conditions
A pulse generator is set for SOlIS on time duration and
approximately 2Sms repetition rate (about 0.2% duty cycle).
The ± clamp voltages are set to the appropriate values. The
power MOSFET load resistor is chosen to equal the maximum rated voltage divided by the maximum rated current.
With a low value of drain supply voltage. observe the gate
voltage while adjusting IABC. A convenient set of conditions
occurs when a short dwell time of several I.IS exists at the
+10V level. Minor adjustments may be desired for IABC as
the drain supply voltage is increased to maximum rated
value. The L2FETs would be tested at +SV gate clamp.
Figure 10 exhibits the pertinent waveforms for an
RFM1SN1S. All power MOSFETs have similar waveforms.
Figure 10(a) is the 3V signal to the CA3280. Figure 10(b) is
the power MOSFET gate current. In this example, the amplitude is ±1mA with a third state of OmA. Figure 10(c) displays
the gate voltage and the drain voltage, 10V peak-ta-peak
and 1S0V peak-to-peak. Figure 10(d) is a piece wise linear
approximation of Figure 10(c). The datum line is zero volts
and applies to both waveforms. The time scale of the waveforms of Figure 10 is 100j.1s full scale.
There are some features of the gate and drain voltage waveforms that should be noted. These features are consistent
with the equivalent model discussion.
1. The waveforms during the positive gate current time are
symmetrical to those during the negative gate current
time. Exceptions will occur for very fast or very slow
switching, and for nonsymetrical current drive. These exceptions are discussed in the following.
11-122
Application Note 7254
2. The drain voltage waveform contains a rather steep slope
with a fairly constant dv/dt over most of the drain voltage
excursion.
3. The drain voltage contains a rather shallow slope with a
fairly constant dv/dt over the remainder of the drain voltage excursion.
predetermined gate current. ±IT' The abscissa is also normalized to 100 (ITIIG) microseconds full scale, where IG is
the actual gate drive current. With this characteristic curve,
switching behavior may be readily predicted for almost any
driving circuit. provided the load is resistive.
n
4. The drain transition voltage (defined as the intercept of the
above two near straight lines) typically occurs when the
drain voltage equals the sum of the gate voltage (at that
instant of time) plus the product of the drain current times
r08(on).
M
5. The gate voltage waveform contains three near straight
line segments during the positive gate current transition
time.
\
,
,
L -:::3
--
L.
1Ir
.,..
.I
L
,
\
r
- ,....
,r.\'I
~
-
//M
H\
rl
I , \\\
J
"' ......
~
-
~
........
-
l
(A)
j' ..
FIGURE 11. CURVES SIMILAR TO THOSE OF FIGURE 10(C)
WITH DRAIN SUPPLY VOLTAGE FIXED AT FOUR
VALUES
~...- ,.--_/
....
Symmetrical Current Drive
Waveforms of Figure 11 will scale in an inverse manner with
gate current. Driving current was varied from ±200mA to
±21!A for the device of Figure 11. Measurements of delay
time (on). rise time. delay time (off), and fall time are plotted
in Figure 12 and compared to the inverse scaling suggested
by Figure 11.
(B)
104
RFM15N15
1
101
:;t(0FF)
01.
• Id (ON)
(C)
:.
(D)
FIGURE 10. (A) 3V SIGNAL TO THE CA3280. (B) POWER MOSFET GATE CURRENT. (C) GATE AND DRAIN
VOLTAGE, (D) PIECE WISE LINEAR APPROXIMATION OF 10(C)
Application of the Switching Data
Figure 11 is a family of curves similar to Figure 10(C). where
the drain supply voltage is fixed at four values. Note that the
ordinate is 10V full scale for the gate voltage. while it is normalized to 100% of maximum-rated drain voltage for the
drain-voltage curves. All four sets of curves are taken with a
102
101
104
Ia - GATE CURRENT (mA)
10'
FIGURE 12. VARIOUS TIME MEASUREMENTS COMPARED TO
THE INVERSE SCALING SUGGESTED BY
FIGURE 11.
It is anticipated that very slow switching (in the millisecond
region) will result in the chip thermally tracking the power
dissipation. which would cause some deviation from the
11-123
Application Note 7254
inverse scaling. This condition was not noted on Figure 12
for gate currents as low as ±21JA.
Large gate currents result in very fast switching waveforms.
The gate of each hex cell is accessed through a gate pad
and gate runners. which are of a low resistivity metal
followed by buried polysilicon of a moderate resistivity. As a
result. the high gate currents cause a propagation delay to
exist for those cells far removed from the gate runners. This
effect is not seen in Figure 12. even though the gate current
was increased to ±200mA.
Asymmetrical Current Drive
The positive and negative gate drive will oiten be dissimilar.
Of course. the scaling must reflect this situation. At other
times the gate current varies with amplitude. This condition
is always true when driving from a pulse generator of fixed
resistance. Piecewise linear methods will yield the gate
current. which will permit the proper piecewise linear scaling.
This calculation could be done in the following manner:
1. Mark eleven small x's along the gate waveform of Figure
11 dividing it into 10 equal voltage segments; for example.
VG = 0.1.2 •... 9. 10V.
2. Draw a vertical line through each x the full height of the figure. creating 10 time segments.
3. If the driving-pulse amplitude is 0 to 10 volts with an internal resistance of 100 ohms. calculate the piecewise linear
gate current for each time segment. IGl (10 - 0.5)1100
95mA. IG2 (10 -1.5)/100 85mA. etc.
=
=
=
=
4. Then scale each waveform within the pertinent time segment by the proper gate current.
5. Smooth the curves.
output current loops. This voltage. L dVdt. may be
approximated and applied to the gate-voltage waveform aiter
scaling Figure 12 for the actual gate currents. Generally. this
effect is not appreciable for gate current small relative to
±100mA. A very loose circuit wiring arrangement with inches
of mutually common source wire will exaggerate this effect.
Gate Voltage Propagation Effects
Most power MOSFET applications need switch no faster
than tenths of a microsecond. but should faster switching be
required. this section will become important. It must be
understood that the power MOSFET appears as a
distributed network of many cells when used for very fast
switching.
The thousands of individual MOSFET cells are connected in
parallel with highly conductive metal for the sources and
drains. However. the gates are paralleled with a moderately
conductive film of doped polysilicon. As a result. a very steep
voltage waveform applied to the gate pad will bias those
cells close by. but a delay will occur for turn on or turn off.
Because of the nonlinear "input capacitance" of each cell.
the delay cannot be characterized by a pure number of so
many nanoseconds.
Presently. most manufacturers characterize typical switching
speed for a single test condition. The test conditions are
usually chosen to present the most favorable result. usually
near the upper limit of usefulness.
Figures 13(A). (B). and (C) show the increasing effect of gate
voltage propagation. The gate waveform is the only one
shown because the drain is not affected so drastically. This is
true because some cells are overdriven. offsetting the effect of
the starved cells. Care must be exercised when operating with
large gate effects similar to those of Figure 13(C).
6. Create 10 more time segments for the right half _of Figure
11 corresponding to an average gate voltage of 9.5.8.5 •.
. . 1.5. 0.5 volts. Call these segments 11.12.... 19.20.
7. In that the pulse-generator voltage is now zero volts. calculate IG as:
IGll (0-9.5)/100 -95mA. IG12 (0-8.5)/100 -85mA.
etc.
=
=
=
=
8. Repeat 4 and 5. L2FETs would be treated with smaller
voltage segments.
Generally. the gate-voltage plateau of Figure 11 will not be
located at the middle of the pulse-generator amplitude (5
volts). As a result. rise and fall times measured this way
experience differing gate currents and are "nonsymetricaf.
This type of measurement will also lead one to observe
temperature senSitivities. load-current senSitivities. and
device-ta-device variability. all of which are more circuit
dependent than device dependent.
Source-Lead Inductance
The gate-voltage waveforms may be corrected by the
voltage across the source-lead inductance and external
inductance. which may be mutually common to the input and
FIGURE 13. CURVES SHOWING THE INCREASING EFFECT OF
GATE VOLTAGE PROPAGATION
11-124
Application Note 7254
Gate-propagation effects may be reduced by the following
design methods:
1. Many gate runners.
Any of the previous methods require trade-offs which would
not be attractive to the needs of most components users.
These trade-offs are in the realm of:
1. Reduction of RoN per unit area.
2. More conductive polysilicon.
2. Decreased yield.
3. Silicide rather than polysilicon gates.
3. Added cost (beyond the cost of yield impact).
4. less cells (resulting in lower transconductance and higher
RoN)·
4. RFI, self-oscillation, and other problems characteristic of
very fast devices.
5. Substantially different lateral and vertical structure.
References
6. High-frequency packaging.
None of the above methods will yield "breakthrough" devices
unless used in combination.
1. "Power MOSFET Switching Waveforms - A New Insight;
H. R. Ronan, Jr., and C. F. Wheatley. Jr., Proc. Powercon
11, April 1984.
2. "Correlating the Charge-Transfer Characteristics of Power
MOSFETs with Switching Speed," E. Oxner, Proc.
Powercon 9, April 1982.
Z
o
-tf)
~w
()I-
-0
KZ
Dec
11-125
Harris Semiconductor
------ -----No. AN7326.1
~
--
---
-
---
=
-- -~
--===
--- ---
~
-= -
c:=.=
----
-
Harris Intelligent Power
April1994
APPLICATIONS OF THE CA3228E SPEED CONTROL SYSTEM
byW. Austin
The CA322BE Speed Control System is a monolithic
integrated circuit originally designed for automotive cruise
control systems; its block diagram is shown in Figure 1. The
completeness and self-contained nature of the circuit can be
appreciated by examination of the typical automotive
application shown in Figure 2. Both 12L logic and linear
circuit deSign are combined to provide the primary functions,
feature enhancements and safety backup necessary for a
high-performance cruise control system. But its fully
facilitated feedback system makes the CA322BE useful in a
wider range of applications. The information provided in this
Note will aid the user in applying the circuit to applications
such as electric motor speed controls, engine speed
vee@-l vee
. The abrupt change to a p0sitive voltage of approximately 2 VeE is normal.
INPUT SIGNAL FREQUENCY (Hz)
FIGURE 6. FN CONVERTER RANGE EXTENSION WITH
ADJUSTMENT OF C8 AND C9
It is possible to extend the frequency range of the FN converter to frequencies as low as 10Hz and as high as 500kHz.
However, the loop stability of the lower frequencies may be
difficult to control. Higher values become very dependent on
The requirements of this change of state have some Influence on the design of the source Input drive to pin 8. For the
FN converter input stage to switch properly, a current source
drive such as an inductive pickup device or a transformer
coupled signal source is preferred. In any case, it is important to note that the signal should swing negative to fully activate the change of state. It is also preferred that the input
signal be nearly centered with respect to the voltage zero
11-130
Application Note 7326
crossing. The external series 8.2kn resistor at pin 8 must be
used to limit peak currents. particularly when inductive
pickup sensors are used. Inductively coupled circuits may
produce transient pulses if any intermittent condition exists.
RC filter circuit of pin 10. Diode 0112 rectifies the currentdriven pulses developed at the collector of 0111.
Another important characteristic of the FN converter is the
absence of pulses from 0111 when no signal is present at
pin 8. Diode 0112 remains reversed biased by any positive
DC voltage applied to pin 10. Therefore. it is also possible to
use a DC voltage signal input at pin 10 to directly control the
servo feedback system. In many PLL control systems. a DC
voltage signal is easily generated from position indicators. In
the CA3228E. this capability provides the user with an alternative to some of the restrictions that apply to the use of the
FN converter. restrictions that may require frequency dividing to accommodate the desired frequency range and bandwidth limitations on the Chip.
.
~
.!
!.
.!
i . RAMP CHARGE AND
i i i
i
DISCHARGE PULSES
HJUU{
FIGURE 7. FN CONVERTER INPUT CHARACTERISTIC PIN 8
VOLTAGE va. CURRENT
As shown in the functional diagram of Figure 8. the second
stage of the FN converter is a pair of current generators that
are used to produce both positive and negative ramp slopes
when driven by the square-wave signal from the output of
the first stage (at the collector of 0101). As shown in Figure
9. the capaCitor at pin 9 is charged and discharged by the
fixed current sources which develop a truncated ramp signal
of approximately 4 Vpp. The ramping signal is applied to a
window comparator with reference points of 0.482 V cc at the
emitter of 0113 and 0.012VCC at the base of 0105 (see
Figure 5). When the ramp is in the transition range between
these voltage levels. a high output pulse (from an equivalent
2 input NAND gate) drives the base of 0111. The comparator levels are determined from a resistor divider: R61. R62.
and R63. The peak signal level is approximately 4V. while
the minimum signal swing is nearly at ground level. The
pulse width provided at the collector of 0111 is a function of
the ramp transition time.
..
PING-V.
PlN1~10
CURRENT CHARGE
PULSES 10 CAPACITOR
AT PIN 10
FIGURE 9. PIN 9 FN OUTPUT AND FN FILTER SIGNAL AT PIN 10
The range of the applied signal at pin 10 should be approximately 2V to 6V. The input impedance at pin 10 is quite high
due to the source follower stage that follows the pin 10 input
and drives Pin 11 plus the V s· output to the AID converter and
mode switch circuits. Pin 11 is a sample test point for the FN
converter output. Vs. The Vs·. signal is separately buffered
and output to the AID converter and mode switch circuits.
To provide a stable temperature characteristic for the FN
converter voltage. external control of the current-source generator has been provided. In the CA3228E. pin 7. Figure 10.
represents a temperature-stable external sensitivity control
point for the FN converter output voltage V s. The 43kn temperature-stable metal-film resistor used to bias pin 7 drives
the FN converter current sources. The current drive generated in the emitter of 092 by this resistor provides a mirrorcurrent bias to the FN converter current-ramp circuits.
AID Converter and Memory Update
Comparator
1&01(
The signal Vs·. derived from the FN converter output. Figure
5. and the D/A converter signal. VM• are internally fed to the
memory-update comparator circuit of Figure 11. The VM signal may be monitored at pin 6. As noted in Figure 5. the Vs'
signal is also fed to pin 11 through a buffer amplifier. The signal at pin 11 is the FN converter output. Vs. and has a close
tracking relation to Vs·. when pin 11 is biased with a 10kn
resistor to ground. In Figure 11. the VM and Vs' signals drive
respectively. From 0274
buffer amplifl8rs 0276 and
and 0271 the V s' signal is sent to the error amplifier. overspeed detector and mode switch. The VM signal is sent to
the mode switch via 0275 and 0269. The Vs' mode switch
input (Figure 13) is at 0231 and the V M input is at 0232.
Transistors 0269 and 0271 also drive 0266 and 0270. the
memory update comparator input transistors.
O2n.
FIGURE 8. FN CONVERTER COMPARATOR STAGE
Since a pulse of fixed width is generated on each positive
and negative transition of the input signal at pin 8. it remains
to integrate the pulses to produce a DC voltage proportional
to the input frequency. The integration is accomplished in the
11-131
z
o
-fJ)
!ciw
(.)1-0
iiz
D..
c(
Application Note 7326
DlACURRENT
SUM OUT
Rl2R
UNE
R22
11K
2K
R41
A
2K
B Q8I
QH
CURRENT BIAS
R54
R56
DRIVE TO
20K
10K
FN CONVERTER
R20 QII3
11K
QIO
a..
RSO
SOK
ClK
CLEAR __
2X
RS1
UK
--===~--1
FIGURE 10. 1 OF 9 RIPPLE COUNTERS AND 2 OF 9 DlA CURRENT SUM OUTPUT CIRCUITS SHOWN WITH THE R12R CURRENT
SINK BIAS AND FIV CONVERTER CURRENT BIAS CIRCUIT
+8.2V
TYPICAL
VS'TOERRDR
AM~OVERSPEED4---~---+-i~----~~
DET AND MODE SW
---~---1~~::::~~j--j!-~;;t-~~~
RESUME VIITO
COMp.
AND MODE SW
R137
420
V84
(0.183Vccl--W'r:::=t~
TO 110
MEMORY UPDATE_-----....
CMDlOGlC
UK
Ate
RIO
17K
17K
VI'
VII
FIGURE 11. Va' AND VII BUFFERS WITH MEMORY UPDATE COMPARATOR AND MINIMUM SPEED LOCKOUT COMPARATOR (MSLT)
11-132
Application Note 7326
The block diagram of Figure 12 provides a broader
perspective on the total operation of the D/A converter and
stored memory operation by showing the signal flow by
function. In Figure 12, the voltage developed by the FN
converter is Vs at the pin 11 monitor output, and is labeled
as Vs, at the internal input to the memory update
comparator. When, at a chosen speed, the acceVset or coast
switch is depressed and then released, the command logic
clears the register and initiates clocking in the ripple counter.
Clocking continues and successively increases the D/A
converter current output in increasing stair step increments
until the VM voltage resulting from the product of the current
and the R38 resistor value is equal to Vs'.
r-------
} TO ACCEL RATE AND
ERROR AMP
Mode Switch and Acceleration Control
The mode switch of Figure 13 is that portion of the CA3228E
whose inputs for Vs' and VM are 0231 and 0232, and
whose output is through pin 15. Logic commands control the
mode switch by controlling 0248, switch A; 0237, switch B;
and 0250, switch D. When switch A is activated, 0248 is off,
which allows 0232, 0240, 0241, and 0245 to conduct the
VM signal to pin 15 and the base of 0251. Similarly, Vs' is
conducted to pin 15 via 0231, 0233, 0234 and 0244 when
switch B (0237 off) is activated.
In the accel mode, switch D is open, allowing the acceleration-rate amplifier to dictate a controlled rate of acceleration.
A switch D open corresponds to an active high Signal from
1100, which causes 0250 to conduct, and which, in turn,
causes 0243 to conduct. The 0243 output to 0242 is then
at an emitter-base saturation level and 0242 is cut off, which
prevents 0244 and 0245 from conducting Vs', or VM to pin
15 and 0251.
Switch D is also open during resume ramp conditions. Note
that Vs', and VM are in tracking modes when 0250 is open
and 0242 is conducting. The VM tracking mode is the
closed-loop cruise mode. The Vs', tracking mode applies to
conditions other than cruise, accelerate, and resume. In the
Vs' or VM tracking modes, 0235 or 0246 supplies current to
the base of 0242. The 0242 collector output supplies the
current that charges the capacitor at pin 15.
FIGURE 12. MEMORY UPDATE COMPARATOR WITH MEMORY
AND DlA CIRCUITS
=
When VM Vs', the memory update comparator changes
state and sends a signal through output 1141 to the logic
circuit to stop the clocking of the 9-bit ripple counter. The
stored bits in the ripple counter continue to bias the DIA
converter to produce the memory set VM speed reference.
Any further changes in Vs', are compared to the VM output
of the D/A converter, which then provides the error signal for
the servo control. (Refer to the Command and Control
Functions section of this Note, above, for complete details of
the command inputs that affect the stored speed setting.)
The circuit of Figure 10 shows a portion of the 9-bit ripple
counter and the D/A circuit driven by the counter. Each cell
of the 9-bit counter has a Ox output that drives its respective
current source. When the counter is active, the summed outputs of the D/A converter driven current generators are
present on the VM line and at pin 6.
The acceleration-rate amplifier controls a fixed rate of acceleration by providing an internal charging voltage and an
external RC time constant at pins 14 and 15. When the
acceleration circuit is active, 0135 is off and current source
0261 conducts current through 0266. Current-mirror circuits
also control current through R132 and produce a fixed voltage offset in the signal path from pin 14 through 0266,
R132, and 0263. In the active accelerate mode, an offset
voltage is present at the bases of 0251 (pin 15) and 0257.
The offset signal that is present at the base of 0257 is also
the output of the acceleration rate unity gain source follower
amplifier. The voltage generated across resistor R132 is
approximately 0.45V, and is the charging voltage for the
external resistor and capacitor. The typical values of the
external Rand Care 2.4MC and 2.2J.lF. Since the acceleration voltage that charges the external circuit is constant, linear approximations to the rate of change may be used.
Using the equation:
V=IVC
Vlt = VC ;: 0.451RC
Since V in the equations represents a fixed velocity-error
voltage, VIt 0.45/RC represents a fixed rate of acceleration. It is therefore possible to change the acceleration rate
by adjusting the RC values. The desired rate of acceleration
is based on system factors associated with the servo feedback loop. The values shown in this Note are for a typical
automotive application. Since very low currents are used,
the capacitor must also have a low leakage. For the conditions shown in Figure 2, charging current is 0.188J.LA.
11-133
=
z
o
-CI)
!ccw
0'"
-0
~z
a..
<
Application Note 7326
R
VII
-t---t---,
R123
38K
Q23&
-- - -
BSW
FROM
!101,1102
ACCELRATE
AMP OUTPUT
10 THE ERROR
AMP. RESUME
COMP. AND OVERSPEEDDET.
ASW
.
FROM FROM
Hl8
1100
FROM
FROM113e
OF THE
REDUNDANT
BRAKE
COMPARAlOR
CMDLOGIC
FIGURE 13. MODE SWITCH AND ACCELERATION-RATE AMPLIFIER CIRCUIT
r---~------~--?-----------~----~~--'-~~Vcc
R103
42K
;t-t""Vw--......- - - 10 REDUNDANT
BRAKE
R107
43K
R104
288
R1o&
1012
L..-------~--V.·(Q271)
R106
7SO
FIGURE 14. ERROR AMPLIFIER SHOWN WITH BIAS "AUGN" SETUP QRCUIT
11-134
Application Note 7326
Error Amplifier
The output signal of the acceleration rate ampUfler is fed to the
error amplifier, the overspeed detector, and the resume comparator. Under normal cruise condRions, the error amplifier
continues to correct speed errors when Vs ' deviates from VIA'
The error amplifier, Figure 14, is a part of the signal flow path
of the feedback loop. The amplifier has an internal differential input and an output at pin 16. When the system is in a
V s ' tracking mode, V s ' is present at both Inputs. When the
system is in a VM tracking mode, the error signal Is present
at pin 16. The output signal of the error ampUfier is externally
coupled to the control amplifier at pin 18. Internally, the error
amplifier output is fed to the redundant brake comparator.
The error amplifier serves the error summing function of the
servo loop and, as such, is a unity gain source follower.
The bias "align" function circuH is shown with the error amplifier circuH in Figure 14. The output at pin 17 is 0.5 Vee and
may be used for bias and setup. Current drain at pin 17
should not exceed 1mA.
Control Amplifier
The control amplifier shown in Figure 15 receives the signal
from the error amplifier output at pin 16. Pin 18 is the negative input with respect to the control-amplifier output at pin
19, and pin 20 is the posHive input with respect to the same
output. The control amplifier may be regarded as a normal
op amp whose gain is controlled with external feedback.
However, the output signal is also internally coupled to the
output vent, vacuum, and gate driver circuits. The open-loop
gain, Acx., of the control amplifier is typically 800. Figure 16
shows the control-amplifier bias configuration with pin 20
connected to an external divider at approximately 0.5Vee
and a variable feedback to pin 18. In the normal input circuit
for pin 18, as noted in Figure 2, R16 and R19 are typically
1OkO and 1Me, respectively.
Because the vent and vacuum driver ampUfiers have a gain
dependent controlled deadband, the feedback versus gain
characteristic of the control amplifier is as shown in the
curve of Figure 16. The curve follows the classic feedback
gain equation and is approximately equal to R19/R16 for
ratios less than 50. However, the approximation Is less accurate for ratios In the 100 range where the error is 15%. The
feedback versus gain characteristic of the application circuit
of Figure 2 is typically centered al a ratio of 100. Figure 17
shows the deadband of the output vent and vacuum amplifIers as a function of the R191R16 ratio; the output drive eireuHs are discussed in further detail in the following.
1M
!Vcc+-__-,
ra-
+
10K
VERROR
FROM
PIN 1.
I-
OUTPUT DRIVE .............................
r-~~~~~==;===;=~+=~=--+==~~~vcc
z
RII5
75K
o
-(J)
~w
(,)1-
-0
~z
Q.
__--.:::cr'-CMD
LOGIC
FIGURE 15. CONTROL AMPLIFIER AND OUTPUT DRIVERS
11-135
Application Note 7326
140
1~
I
t:::c
~
~
100 VII
15K
~
~
~8
~+
20 18 ~
.o,:; 120 -===. 1
The aOO.e action assumes that the gate output is low, permitting
the external cIri\4e circuits 01 Figure 2 to function norma~ The
gate output remaIls low for acceleration, cruise, and coast functions. For brake, redundant brake, 0YeI'Speed and minimum
speed oonditions, the gate output is high, which prevents acceleration and forces the system into a noncontrollable state. The
gate output is forced higl, and the vacuum and vent outputs low,
by an Internal logic switch, 1103, that disables the output drivers.
RiI
APPROX. _
I
~
TOGAIN(1:1) ~
•..t.
~
-1--.1
,+ f"~ f:::;;P
~~~~
o eo J-+--+--+-+--t-t-::;t1:;I'F--tt--1
1,/ •••r.·
=
HI .A
ACTUAL
~"'f,•
II.
_
R18
..,Rii RAno
I ..tt(,. ,.",
i
a:a:
40
20
VERSUS GAIN
10'
~
TYPICAL GAIN
=
1\.1,...'
~8~'
l--r
::7t"-+-t--tFOR ~ •• 1oot-"~~""""-1
l......
I
00
I
I
I
~
10 20 30 40 eo eo 70 to 80
CONTROL AMPUFIER GAIN WITH FEEDBACK
100
FIGURE 16. CA3228E FEEDBACK RATIO VERSUS CONTROL
AMPUFIER GAIN (WITH FEEDBACK)
Output Drive Circuits
The deadband 01 the output drive circuit is fixed by resistor
ratio, but can be controlled through the gain of the control
amplifier. It should be noted that measurement of the deadband or tap ratio points requires forcing of the drive voltage to
the control amplifier and measuring of the voltage at pin 19
when the vacuum and vent outputs change state. The circuit
of Figure 2 was used to generate the curve in Figure 17,
which shows the variation of the deadband range when the
gain of the control amplifier is changed by changing external
feedback. The deadband range is shown in Figure 17 in a mV
spread as a Vs reading at pin 11. As the control amplifier gain
is made to approach unity, the deadband approaches the
actual tap voltage separation of 1.19V when Vee equals S.2V.
The nomenclature of the output-drive circuits has been chosen to represent a normal vacuum-controlled actuator. Vacuum control of the actuator is intended to provide
acceleration while vent control provides a relaxation or coast
function. The output-drive circuits consist of amplifier drivers
for the vent, vac (vacuum), and gate-output terminals at pins
21,22, and 23, respectively, as shown in Figure 15.
A single input from the control amplifier controls the vacuum
and vent outputs. The signal is passed through R91, a 30kll
resistor, and the base of 0171 to a differential amplifier that
controls the vacuum output. The base of 0171 is also common to the base of 0166, which is the differential-amplifier
input that controls the vent output. The differential amplifiers
for the vacuum and vent functions have reference inputs tied
to a resistor divider composed of R87, RSS, and R89.
The tap ratio for the 0168 input (comparator reference for
the vacuum output) is at 57%. The tap ratio for the 0167
input (comparator reference for the vent output) is at 43%.
When the control amplifier input is less than 0.43 Vee, both
vacuum and vent drivers are switched low or remain in a saturated on slate. They remain on as long as the divider lap
voltages are higher than the control amplifier input voltage.
This situation defines a relaxed servo or coast mode.
When the control amplifier input voltage exceeds the 0.43
Vee tap level, the 0166 differential input voltage forces the
base of 0160 and the collector of 0161 at the vent out put to
switch high. While the vent output is high and the vacuum
output low, the system is in the deadband, which is the normal cruise mode. However, as the control-amplifier input
voltage is further increased to the 0.57 Vee tap level, both
the vent and the vacuum outputs are switched high. The vacuum output switches to the high state when the base input of
0171 exceeds the 57% tap reference for 0168 and causes
0159 to switch off. When both the vent and vacuum outputs
are high, the system is in a state of acceleration. As noted
on Figure 2, the state of each mode is dependent on the
external normally open (N.C.) and normally closed (N.C.)
solenoid polarities.
0 1000
Eia:
,
~
~ww 100
II.
a:
1'-
w
Ii:
:::J
!
i
~
l!!1:!
a: a:
t"o10
'-
I'.
1L--L__~~~~__-L~~__L-~-L~
1
10
100
DEADBAND VOLTAGE RANGE (mY) AT PIN 11
1000
FIGURE 17. DEADBAND VOLTAGE RANGE IN OUTPUT CIRCUIT AS A FUNCTION OF CONTROL AMPUFIER
FEEDBACK RATIO (GAIN ADJUSTMENT) REFERENCED TO va AT PIN 11
Redundant Brake
When the speed-control system is in the cruise mode, the redundant brake comparator (shown in Figure 18) may become active
if SignifICant error voltage develops at the output 01 the error
amplifier. Specifical~ if loading or braking is causilg the speed 01
the system to be reduoed, the redundant brake comparator
senses that the speed is faHi1Q off. When the error d6veIoped
reaches a difference speed of 11 mph, the redundant brake comparator switches logic gate 1136, which causes the system to go
to the standby mode. More general~ when the voltage at pin 16
drops below 42% of the Vee supply voltage, 1136 sw~ches state.
There is an additional output from the redundant brake througl
1135; this output remains higl during cruise and acceleration
modes. 1136 inhibits the acceleration rate amplifier by controlling
the E switch. (Also see Figure 11.)
11·136
Application Note 7326
The conditions that determine the operation of the brake and
redundant brake can be determined from the acceleration
and sensitivity factors discussed above. The sensitivity of the
FN converter is approximately 27mVlHz. For the system of
Figure 2, the system magnetic speed sensor ratio is 2.22Hz!
mph. Multiplication of these factors yields a ratio of 59.94mVI
mph. Dividing this ratio into the 450mV offset designed into
the acceleration rate amplifl8r provides a result of 7.5mph.
Comparison of this result to the 11 mph error allowed before
the redundant brake becomes effective indicates that there
is a wide enough safety margin to prevent redundant braking
during acceleration.
A special feature of the CA3228E prevents extraneous noise
from switching the redundant brake output and causing the
system to go into standby. This feature is provided by a 4-bit
shift register that is used as a digital filter to clock all four outputs of the shift register to 1's before a 4-input AND gate can
switch the logic to standby.
Brake Input Comparator
The brake input comparator, also shown in Figure 18, is a
comparator amplifier driving an inverter logic gate (1142).
When the brake input is greater than 0.55 Vee, as determined by the resistor divider composed of A77 of 201<0 and
A75 of 24.5kO, the 1142 gate output changes state. The
brake input is normally connected through a current limiting
resistor to the brake switch, and is in parallel with the brake
light. The change of state at the output of the brake input
comparator drives the command decoder which places the
system in standby.
Minimum Speed Lockout
The minimum speed lockout (MSLn comparator shown in
Figure 11 senses the speed voItaga Vs', and compares it to
the output of a fixed resistor divider. When Vs' drops to less
than 1.5V, the comparator switches, which sends a signal to
the control logic that places the system in standby. If Vs' is
initially less than 1.5V, the system cannot be set in the cruise
mode. The divider ratio of 0.183Vcc is approximately 1.5 V
for a normal Vee of 8.2V. For a speed sensitivity factor of
59.94mVlmph, 1.5V is equivalent to 25mph.
Overspeed Detector and Resume
Comparator
The associated functions of over speed detector and resume
comparator are shown in Figure 19. From the normal condition, where a speed is set in memory and cruise is being
maintained, it may be desired to increase speed and then
return to the cruise mode. If the range of speed increase is
large, it is best not to use the a~el mode but to manually
accelerate to the higher speed and then press the set!accel
switch. An over speed detector comparator compares Vs'
and VIA and controls the logic to assure a smooth transition.
During acceleration, Vs' is greater than VIA' When the set!
accel command is given, the logic turns on 0250 (Figure 13)
and the capacitor at pin 15 is rapidly charged. When the voltage at pin 15 is within 60mV of Vs', the over speed detector
output is switched low. At that point, further Vs' correction is
assumed by the acceleration-rate amplifier under fixed-rate
conditions. The overspeed detector maintains the 60mV off-
10K
,..--J\I1I\r--TO PIN 18
BRAKE
REDUNDANT
BRAKE
--'--~--~---'---+-V~
R115
FfT7
20K
CIA2V~
_ _J\I\I\I"'_ Va
REF
FROM
ERROR AMP
BIAS
Va
-
-=-
FROM
MSLTI133
FIGURE 18. BRAKE AND REDUNDANT BRAKE
11-137
Z
0- t J )
BRAKE
SWITCH
!cw
BRAKE
KZ
a..
IJQHT
()~
-0
c(
Application Note 7326
set along with a sufficient amount of hysteresis to assure
noise immunity. When cruise conditions have been disrupted
by braking action, and it is desired to return to cruise, the
driver presses the switch for resume. The resume comparator samples Vs ' and VM and determines the fixed acceleration required for return to the speed previously stored in
memory. An internal filter is used at the output of the comparator to prevent noise from resetting the comparator
before Vs ' reaches VM.
Oscillator (Clock) Circuit
The circuit of Figure 20 shows the RC oscillator circuit used
for intemal clocking of the 9-bit ripple counter and the 4-bit
counter that serves as a digital filter for the redundant brake.
Various other elements of the command logic require oscillator control for the toggling of flip-flops. The oscillator frequency is an independent internal function on the chip, and
has no relation to the frequency of the FN converter input. A
single capacitor at pin 5 determines the oscillator frequency.
However, the fixed current source noted as VB5 also has an
effect. The Vas current source is derived from the same bias
line that controls the FN converter current sense drive from
a 43kn resistor at pin 7. While the oscillator frequency may
be changed by adjusting the resistor at pin 7, this adjustment
will also change the FN converter sensitivity. Since the volt-
age bias at pin 7 is approximately 5.5V, Ql30 and Q131 are
driven by 128jJA through Q92 in the FN converter (see Figure 5). The base bias line for Q131 is VB5, and is mirror connected to Q84 and 085 in the oscillator. A charge current of
128jJA goes to the O.OOlI1F capacitor at pin 5 from p-n-p
transistor 085. A 4x current mirror n-p-n transistor, 086, discharges current at 512j1A from the capacitor at pin 5. The
resistor divider at the base of Q81 switches between 4.1V
and 6.1V as 1144 and 085 are toggled on and off in the
return feedback loop. With a charge current of 128j1A and a
discharge current of 512j1A and using the equation:
t
=VCII
the clocking time, t. (and hence oscillator frequency) can be calculated using the 2V change for V. a O.OOlI1F capacitor value
for C, and the charge and discharge currents for I. The result is
15.6 plus 3.9j.Is or a frequency of approximately 51kHz.
Operation and Performance
Table 1 defines the wltage values for the pins of the
CA3228E IC. The annotations cover pins where conditions
may be expected to vary. For further detail on the functions
of the VM and Vs voltages at pins 6 and 11, respectively,
refer to the CA3228E data sheet.
OVERSPEED DETECTOR
RESUME COMPARATOR
-----------r--------.---.-----------------------~----------_1~--_1r_+-v~
R11a
II(
TO 188, 187, 188 AND 1111
CMDLOGIC
V.' (0271)
FROMACCEL
RATE AMP OUTPUT
FIGURE 19. OVERSPEED DETECTOR AND RESUME COMPARATOR
11-138
Application Note 7326
TABLE 1. NORMAL CRUISE-MODE PIN VOLTAGES FOR THE CA3228E (NOTE 1)
PIN NO.
VOLTAGE
VOLTAGE
PIN NO.
1
Ground
13
8.2V Normal Vee Supply Voltage
2
No ConnectIon
14
4.55V
3
7.76V (Idle)
15
4.W, 0.45 Less Than V 15 1n Accelerate Mode
4
O.OW
16
4.W
5
5.2Voc , VAC Sawtooth 4.1 t06.1V
17
4.W
6
1.5 to 6.5V, Speed Dependent (OV without Memory
Set)
18
4.1V
7
5.45V
19
4.1 V (Product of Error Voltage and Gain)
8
5
OVoc , 5 2.5VAC
20
4.W
9
4V Peak AC Signal
21
8.2V, Active Low
10
OV to 6.5V, sPeed Dependent, Equal to Ve In Cruise
Mode
22
O.OSV, Active High
11
SemeasV10
23
0.025V
12
O.OW with Brake Switch Open
24
Ground
NOTE:
1. Vrx; = 8.2V, speed set at BOmph (Ve = 3.6V).
FYCONV
r ______._------------~~~--------._~(RG~.~~ Vee
R46
500
R47
500
Q85
Q84
-+---- VBI
.:t-:::iII----.....
R43
25K
CHARGE
.._----_ . ..t
, , .....
128.....
"
•
I
~I
I
I
I
I
I
~ II
R41
:10K
I
I
I
+w
iii!
.",
~G
z
~~
R40
7.SK
o
-U)
~w
01-
-0
~z
~
R38
-
10K
OSCILLATOR
(CLOCK) OUTPUT
TO 181
--- ---
r--......L..._ _
Foac TYPICALLY 50kHz
~
I .. CHARGE.I n
I DISC
FIGURE 20. OSCILLATOR CIRCUIT USED FOR INTERNAL DlA CLOCK DRIVE
11-139
Application Note 7326
Note that the D/A converter cannot be set at low speeds and
will remain at or near OV until the frequency at pin 8 is near
50Hz (for the conditions of Figure 2). Dynamic signals are
present at pins 5, 8, and 9. Speed dependent voltages are
present at pins 6, 10, and 11. Error dependent signals have
a notable effect on control amplifier output at pin 6 and the
driver output pins 21 and 22. The command input at pin 3,
the brake input at pin 12, and the gate output at pin 23 are
mode dependent. The table does not reflect all of these
changes since the conditions are noted only for a normal
cruise setup at approximately OOmph. Again, the data sheet
has further details on the various mode and state changes.
voltages of 4.3 to 4.5 are 72 to 75mph, respectively. It should
be noted that Figure 22 is a measured curve from -55OC to
+90oC with an equivalent 73.5 ±1.5mph error. Over the
same range. the Vs and VM readings typically tracked within
130mV while maintaining a cruise mode.
It is important to remember that the mode inputs are
momentary touch switches except for the hold down
condition of the accel and the coast switches. If pin 4 is
monitored during the command input changes, it will be
noted that delay switching times noted in the data sheet will
be reflected at this pin.
Measures of the operating performance of the CA3228E are
the wide power supply and temperatur~rating ranges. The
curve of Figure 21 shows the dynamic range of the power
supply input Vcc at pin 13 over the temperature range of -4O"C
to +12CJ>C. The normal Vee specified is +8.2V ±O.8V or
approximately 10% tolerance. The curves of Figure 21 also
demonstrate a wide tolerance in the minimum to maximum
range over which the device functions. A failure. as noted in the
figure, is defined as a phase-Iocked-Ioop malfunction. Nole that
even with the wide range shown for power supply tolerance, it is
still recommended that an external zener regulator or
equivalent be used at the Vcc power supply input. Vehicular
power supply conditions typically range from 9V to 16V, a range
that exceeds the maximum range and rating for the operation of
the CA3228E. While some applications may work at lower
voltages than the recommended 7.4V minimum, operating
conditions should nol exceed the 9V power supply maximum
rating.
TYPICAL MAX. Vee TO FAlWRE
·;;~~~~~:::·:~:""r""""""""
€ 12
.,! ••• ,••
i
~~~:::;;t~~~~~~~'~~ee~
~ 10!
illII:
a
&
w
~
OPE~TING RANGE
4
~
81
··1......
:
...... .
I
:
2
! ~AX
:.'
NORMAL MIN. .. .... •....••....•..
OPERATING
RANGE
-20
0
20
···i·....···~~;~~ MAX.
i - OPERATING
!
TEMP
o i
-10
:eeiN
NORMAL Vee
..................... TYPICAL MIN: Vee TO FAILURE
i - OPERATING
!
t--
I
I
40
80
AMBIENT TEMPERATURE
Ii
80
I
TEMP
I
100
120
("C)
FIGURE 21. Vee OPERATING RANGE OF THE CA3228E
Figure 22 shows another wide-range capability of the
CA3228E when the temperature Is varied. The Va and VM
voltages are plotted versus temperature from -BO°C to
+100oC. Both the voltages for Vs and VM are shown along
with the equivalent speed condition for the typical application
of Figure 2. For the 59.94mV/mph quoted above, the
-60
-40
-20
0
+20
+40
TEMPERATURE ("C)
+60
+80
+100
FIGURE 22. TYPICAL CHARACTERISTIC OF THE FN C0NVERTER OUTPUT, Vs. AND DlA OUTPUT, VII>
TRACKING va TEMPERATURE IN THE CIRCUrr OF
FIGURE 2
General Applications
A CD4046 CMOS VCO (voltage controlled oscillator) may be
used in the external loop to drive the sensor input at pin 8. In
the closed-loop circuit shown in Figure 23, the CA3228E will
respond to the accelerate, cruise and coast conditions and
provide the appropriate drive at the vacuum and vent outputs.
From an idle mode after turn-on, the frequency may be
adjusted by the 1MO potentiometer. The adjustable range of
the potentiometer output to the VCO input at pin 9 is ground
on the low end to Vee on the high end. The 0.047I1F capacitor
between pins 6 and 7 and the 100k0 resistor at pin 1 were
chosen to accommodate a frequency range of 50 to 250Hz.
When a VCO frequency representing a given speed is set by
the frequency control and applied to the sensor input at pin
8, the set value may be entered into the CA3228E D/A memory with the set/accel command. Changing the switch at pin
9 of the CD4046 to the loop position then closes the servo
loop with the VCO set frequency retained in the D/A memory. The PLL of the CA3228E will maintain the frequency of
the VCO, and any conditions that force the VCO off frequency will be corrected by cruise or resume mode control.
While the VCO closed-loop circuit was used to demonstrate
the capability of the CA3228E, It is also apparent that many
applications of the referenced circuit or variations of this circuit may exist.
Sketches of various application possibilities for the speed control system are shown In the functional diagrams of Figure 24.
These applications have not been reduced to practice but are
only suggested possible circuits. Since the MSLT and redundant brake affect the low end settings, a diode bias clamp of
11-140
Application Note 7326
1.6V should be used at pin 11 to keep V s higher than the minimum speed lockout level. Pseudo DC IIORage levels can be
applied to pin 10 to set a Vs level for the D/A memory.
Further potential for use of the speed control system
includes its combination with the CDP68HC05 series microprocassor control systems with added memory and D/A control.
Vee
REFER TO THE
APPLICATION
aRCUIT OF FIG. 2
FORCA3228E
+
I.SV
1.SV
l.2K
10K
NOTE:
V.(10), PIN 11, IS SET TO DEFEAT THE
MSlT (AT1.SV). Va(10), PIN 10 IS SET AS
A PSUEDO DC VOLT. REF. LEVEL AS AN
FN SPEED EQUIVALENT.
FIGURE 24A.
V
VAl:.
8
VENT 1-----+.l\1li\,-1
1M
co
Voo
16
6
7
CD4046
1
lOOK
5
FN
SENSE t-.......J\II.fIr--+-+--<
INPUT
,,
.L__~~_~c0'2~_j
~
• -
r----------
AlT
aRculT
:
'
-
t
+Vcc
,,
FIGURE 24B.
:,
SOLENOID
VALVES
FIGURE 23. Pll OSCILLATOR FREQUENCY CONTROL CIRCUIT
References and Bibliography:
1. ·CA3228E Speed Control System: Harris Data Sheet, File
No. 1436.
FIGURE 24C.
2. "New Chips That Simplify Motor Control," L.J. Hadley, Machine DeSign, Feb. 12,1981.
CA3161112 H DRIVERS
3. "A Monolithic Speed-Control Micro-System For Automotive
Applications," A.B. Jarret and W.O. Pace, ISSCC, 1978.
Acknowledgments
The author acknowledges the work of Gregory Kubak in
engineering characterization, and T. DeShazo, A. Giordano,
and A. Rodriques in deSign, dewlopment, and circuit information, and in editing support.
PosmON
OR 55Hz TO 240Hz
APPUED TO PIN.
TRANSDUCER
F1QURE24D.
FIGURE 24. SUGGESTED APPUCATIONS OF THE CA3228E: ADC MOTOR SPEED CONTROL, B. MASTERISLAVE
ENGINE SPEED CONTROL. SWITCH TO SET/ACCEL
TO STORE MASTER SPEED IN SLAVE DlA MEMORY,
THEN SWITCH TO MRUN". C. AIR OR FLUID TEMPERATURE CONTROL. (SEE A- FOR V. SETUP CIRCUIT.) D. DC MOTOR POSITION CONTROLLER. (SEE
A. FOR V. SETUP CIRCUIT.)
11-141
Harris Semiconductor
-
- -- ---- -- ---=--=-=~
-==--===
--- - -
No. AN8614.1
===
-=
- - - - - ------=-
-~
-
~--
--~
Harris Intelligent Power
April1994
THE CA1523 VARIABLE INTERVAL PULSE REGULATOR
(VIPUR) FOR SWITCH MODE POWER SUPPLIES
Author: W. M. Austin
The CA1523. Variable Interval. Pulse Interval Regulator
(VIPUR) is a monolithic integrated circuit designed for use in
switch mode power supply (SMPS) systems. The
advantages of both pulse interval modulation (PIM) and
pulse width modulation (PWM) are combined in the VIPUR
circuit. Figure 1 shows the block diagram and external circuit
used in a typical CA1523 switching regulator circuit.
The special features of the CA1523. including a slow-start
controlled power-up and mode sensitive logic control of the
output pulse. provide several advantages in power supply
applications. Intrinsic controls for adjustment of the pulse
and frequency modulation range allow easy use of the
CA1523 in a variety of SMPS systems. but especially those
where line isolation is required.
VUNREG(RAW 8+)
INPUT
R1
VAEG
OUTPUT
+
'VB
Z1
START UP BIAS
SAWTOOTH
""
FIGURE 1. BLOCK DIAGRAM OF THE CA1523
Copyright 4) Harris Corporation 1994
11-142
Application Note 8614
Systems that require line-isolated power supply voltages
may be powered with the CA1523 regulator in a transformer
flyback-converter system like the one shown in Figure 2(a).
This system is particularly useful in meeting rigid safety standards when interiecing between workstation equipment or
modular consumer audio and video instruments is required.
Less stringent interiece requirements may permit the use of
regulators with a common ground for both the switching controller and power supply outputs; examples of these regulators are the flyback converter of Figure 2(b) or the buck
converter regulator of Figure 2(c). However, the application
of most interest is the line isolated type shown in Figure 2(a)
The PWM system is a popular mode of control in switching
power supplies, as noted in the wide use of the CA1524. The
counterpart of this mode of control, the PM system, was
used extensively in the early period of switching power
supply development. Both methods of control have their
advantages and disadvantages. PWM offers effective control
over a wide range of power supply loads. However, at the
lower end of the load range, the PWM becomes limited
because of the minimum pulse width, TON, required. In
addition, the rise and fall time of the drive pulse of the power
switching transistor must be slowed down to meet RFI and
EMI requirements. On the other hand, the PIM can handle
low loads better because the duty cycle is reduced by
increasing the pulse interval. However, the low range of the
operating frequency may cause filtering-related problems in
audio or other sensitive instruments. Another problem with
PIM at the low-frequency end is the related conversion
losses.
The CA1523 is primarily a PIM controller with built-in PWM
correction over a 2-t0-1 pulse width range. For a frequency f
and an associated period T, the pulse width reduces from a
maximum width of TI2 (50% duty cycle), corresponding to
the highest frequency at the maximum load limit, and
approaches T/4 at the lowest frequency and minimum load.
The combination of both PIM and PWM control effectively
compresses the operating frequency range over that of a
pure PIM control for a given range of load. The combined
CA 1523 VI PUR advantages at minimum frequency include
reduced losses and low ripple with improved efficiency and
regulation. Pulse-width correction done simultaneously with
pulse-interval correction produces an inherent gain magnitude of approximately 2 at 50% duty cycle under high-load
conditions. This feature helps in keeping the error-amplifier
gain low, and improves stability without the addition of
expensive external components.
•FIGURE 2A. LINE ISOLATED FLYBACK CONVERTER
VUNAEG
Features of the CA 1523
As shown in Figure 1, the output drive pulse of the CA1523
is modulated and mode-controlled by several system
features:
FIGURE 2B. NON-ISOLATED FLYBACK CONVERTER
1. The output drive pulse has a maximum continuous
±SOmA capability into an 1800pF load.
2. The peak transient load is +3OOmA and -200mA for a
maximum of 1118.
3. The maximum pulse width can be controlled by choice of
the timing capacitance at pin 14 and the current-sense
resistance at pin 2.
4. The output-pulse rise and fall time can be controlled by
choica of the rise/fall-time capacitor at pin 4.
5. The slow-start threshold of the pulse output is controlled
by choice of the resistance at pin 2.
FIGURE 2C. BUCK CONVERTER REGULATOR
FIGURE 2. THE CA1523 IN SWITCH MODE POWER SUPPLY
SYSTEMS
6. The output-pulse interval is rate controlled during powerup by the slow-start RC-charge time constant at pin 10.
7. Maximum output frequency is in excess of 200kHz, and is
11-143
user controlled.
z
o
-(f)
~w
01-
-0
~z
~
Application Note 8614
B. Output pulse Interval and width corrections are maIntained by the error voltage feedback to pin 1.
9. The standby on/of! switch between pins 7 (Vee> and 12
controls the output pulse. As an option, the on/off function
may be controlled by logic-level switching at pin 12 or by
line-isolated switching using an optical coupler.
10. Overcurrent shutdown may be controlled by using a
sense resistor in the load circuit to shut down the output
drive pulse.
Other Features of the CA1523 Include:
1. A substantial level of ESD (electrostatic discharge)
protection designed into the interfacing pin terminals of
the Chip.
2. An B.4V intemal zener voltage reference for the on-chip
bias circuits.
3. A 1.21 V bandgap that provides a stable voltage reference
for bias to the timing circuit and error amplifier.
4. NOR logic control of shutdown of the output pulse under
fault conditions for low Vee, on/off, and overcurrenl Pin
9 is a monitor or output indicator of a fault condition.
5. Availability in an economical 14 pin DIP package.
Control Structure of the CA1523
The differential emitter current is approximately equal to the
collector current of 017C; the collector currents of 017A and
017B are current mirrors to the collector current of 017C.
The currents 1d2 and Ie provide the PIFM charge and
discharge timing, and are, respectively, the collector currents
of 017A and 017B. The current ratio is 1/2-t0-1 to accommodate a 50% duty cycle at maximum frequency and load
conditions. When start-up conditions exist, and the pin 1
pesses all of the 1c/2 current to 011.
error voltage is low,
Since 011 and 01B are current mirrors, the collector of 01B
discharges the timing capacitor, Cr, at pin 14. The state of
the flip-flop, FF1, determines whether 015 will conduct
current Ie from 017B into the timing capacitor.
as
When 01B is discharging current from Cr at an Id2 rate,
and 015 is charging Cr at an Ie rate, the net charge current
is 1d2. This is an FF1 high state for the output, and 016
is cut of! while 015 is conducting current Ie. The positive
voltage ramp at pin 14 increases until the V H comparator
toggles at the 5V reference to the inverting input, resetting
FF1, with the output going low. When is low, 015 is cut
off, and no charge current passes to Cr. Timing capacitor
CT is then discharged by 01B at a maximum rate of 1d2.
The discharge ramp continues until the voltage at pin 14
reaches 2.5V, when the VL comparator toggles the S Input
of FF1 to a high state. The cycle of charge/discharge to timing capacitor CT is complete when the output of FF1 goes
high in response to the high at the 5 input.
a
a
a
a
The CA1523 has five primary circuit functions:
1. Error amplification
2. Pulselfrequency modulation
3. Pulse driver/output amplification
The above operation occurs when the error voltage is lower
than the 6.BV differential Input reference, a condition that
allows the full 1d2 discharge of Cr by the 011 and 01B
current mirror. After being turned on from the line power
source, the slow-start function shunts
collector current
through 02. As a result, the 011,01B current mirror initially
receives little or no forward bias current, and CT cannot ba
discharged. As the slow-start voltage increases, the current
in 02 decreases, allowing 011 and 01B to discharge Cr at
an increasing rate. As long as the error voltage at pin 1
remains below the 6.BV reference level, the charge and
discharge rate is at the 50% duty cycle condition.
as
4. Slow-start power-up control
5. System logic control
The block diagram of Figure 1 shows the interrelated
functions of the circuit. When the system raw B+ is switched
on, the slow-start function controls the pulselfrequency
modulator, P/FM, until the voltage at pin 10 Is greater than
7V.
Standby conditions then exist until switch 51 is closed. In the
standby mode, the PIFM maintains a maximum frequency
output with a 50% duty cycle. After switch 51 is turned on,
the output amplifier is enabled and the PIFM response is a
function of the error voltage at pin 1. The error amplifier
accepts error-correction inputs and controls the pulse and
frequency modulation. The PIFM output pulse is then
amplified in the driver and output stage.
Figure 3 shows the timing-circuit schematic of the CA1523.
For a given timing capacitance, Cr, the maximum frequency
of the PIFM circuit is determined by the current-sense bias
at pin 2. The current-sense level, Is, is set by the fixed
resistor at pin 2, Rs, which goes to ground. A resistor divider
reference at the base of 092 of differential amplifier 091,
092, is approximately Vccf2. The differential amplifier feeds
back, via 017C, any error In the balance of 091 and 092,
while holding the pin 2 voltage at the Vccf2 reference level.
The differential emitter current is supplied by 093, and is
determined by the bandgap bias voltage of 1.21V at the
base of 093.
In reference to the sJow..start circuit of Figure 3, an increase
of the slow-start bias on capacitor C2 at start-up exercises a
decreasing degree of control over the discharge timing. If the
current-sense adjustment at pin 2 is typically less than
100IlA, there will be a full frequency range of sJow..start
control, and the range of increasing pulse width will be 2 to
1. Higher pin 2 bias currents will reduce the range of
frequency control. The Input to pin 10 drives the base of
p-n-p transistor 034. A 30kn emitter resistor, R22, is
returned from 034 to an Internal 7.7V bias source. Transistors 01 and 02 mirror the 034 collector current and shunt
the
collector current away from 011, redUCing the discharge current in the timing control circuit. As an example,
with 4Vat pin 10, there are approximately 3V across emitter
resistor R22. This arrangement allows the discharge current
to be controlled over a range of 100jlA. A bias resistor In the
range of 561dl to 68kn between pin 2 and ground is suggested for a full range of slow-start control. Higher levels of
pin 2 sense current Increase the 10'2 current beyond the full
range of the slow-start bias control at pin 10.
11-144
as
Application Note 8614
When a power-on condition has been established, slow-start
completed, and S1 switched on, the CA1523 begins normal
regulation through error-voltage control as follows. When S1
is switched on, maximum energy conversion occurs in the
switched trensformer. The supply voltage approaches normal regulation level, and the error voltage increases toward
the a.8V reference level. The error voltage is set by a
resistive divider ratio determined from the rectified voltage of
the transformer sense winding. The 05, 06, 07, and 08
differential controls the 06 current to the 011, 018 current
mirror, decreasing
current as the error voltage increases.
A portion of the 10'2 current from 017A is passed by OS.
This current controls the PIFM output pulse and maintains
regulation at the desired level, as determined by adjustment
of the divider at pin 1. Pulse output continues from FF1
during regulation, but at a reduced rate and with reduced
pulse width. The 0 output of FF1 Is always high during the
positive ramp at pin 14, a condition of maximum charge
current to CT' At minimum load, the pin 1 voltage increases,
and the net charge current for the positive ramp is higher
because 018 is discharging less current. For example, if the
error voltage at pin 1 is forcing half of the Id2 current to 07,
the 06 current is Id4, and the net positive ramp charge
current at pin 14 is:
To generalize, we can establish the range of error correction
by assigning a k factor to the decimal portion of the 017A
collector current that is shifted from 06 to 07. Let k 0 when
VI (pin 1 voltage) is low and all 017A current (10'2) flows
through
to discharge pin 14. k = 1 when all 017A current
is shifted to 07 and there is no discharge current to pin 14.
The maximum rate of charge and discharge is established
by the sense current, Is at pin 2; Is is approximately 10'2.
=
as
Since:
as
le-le/4
=31e/4
The net negative-ramp discharge current is then Id4. What
had been a maximum charge and discharge rate of 10'2 at
start-up is now pulse-interval and pulse-width modulated to
provide a 3 to 1 charge/discharge ratio.
V
=(1/C) x lidt
For a constant rate of charge (or discharge) current:
V H - VL
=ICHARGE (or IDISCHARGE> X (T2 - T 1)1C.
And:
TON(MAX)
=(VH - VJCrlls·
From Figure 3, the range of (VH - VLl is approximately (5.02.5), or 2.5V, and Is is approximately equal to Vcd2 divided
byRs·
The above information is used to establish the pulse interval
or system frequency. The frequency is the reciprocal of
TON(charge) plus TOFF(discharge). As VI increases. k
increases. The positive ramp charge current to pin 14 and
Cris:
ICHARGE
=Ie - (10'2)(1 - k) =215 - 15(1 - k) = 15(1 + k).
~--------------~----~-.------~----.-~---+V~
II(
QOUTPUTTO
THE PULSE
DRIVER STAGE
z
o-en
Vs
!;(w
~15
~z
a.
~----------------~-
CC
+
__ (EXT)
C2
--
TIMING
UK
r-.·----.
14
~--II- TON
-- -!-~ -%-=::~~
: LOGIC:
..A,,""","Ir-t--~: ~~ :
..... -----'"
FIGURE 3. PULSEIFREQUENCY MODULATION AND TIMING CIRCUIT FOR THE CA1523
11-145
Application Note 8614
SLOW START
Since Ie is cut off during discharge:
r----::,.--------f""Q34 CURRENT CONTROL
Of TIMING
IDISCHARGE = lsI 1 - k)
Therefore, during charge:
=
[(VH - VL)CrVIJs(l + k)]
and, during discharge:
TON
HIGH 15
DISABLES
PULSE OUT
=TON(max)/(l + k)
TOFF =[(VH - VLlCT]/[l s (l - k)) =TON(max)/(l - k)
Note that TON approaches TON(max)12 as k approaches 1.
This is the condition of minimum power supply load. With the
time conditions for TON and TOF!" established, the frequency,
f, can be defined as:
f = l/(TON + TOFF) = (1 - t<2)I2TON(Max)
11}--......:I'-I
Since the maximum frequency occurs at k =0:
fMAX
(OVER- 1.21V
CURRENl) -
=112TON(Max) and
=(1 - t<2)12ToN(Max).
FIGURE 5. CA 1523 LOGIC CONTROL DIAGRAM
f = fMAX(l - t<2)
The duty cycle is TooI(TON + TOFF) which, by substitution, is:
D = (1 - k)/2
Since k is the current split ratio of the input differential
amplifier, the differential equation applies, that is:
k == 1/(1 + e AVIh)
where e is the natural log value of 2.718, h is KT/q (=26mV),
and fN is V1-VREF The equation for k is approximate, but
provides a reasonably accurate transfer function for the
CA1523 when output pulse width, frequency, and duty cycle
may be calculated for given values of (VI - VREF)'
As k goes to 1, the frequency goes to zero, implying a noload condition on the power supply. This is an improbable
condition; however, the lowest system frequency is always
determined by the minimum power supply load.
The test circuit of Figure 6 demonstrates the pin 2 current
sense (Is) range using timing capacitance values of 100pF.
240pF. and 470pF. Figure 7 shows the frequency versus's
current at pin 2. Figures 8 and 9 show the range of pin 6
pulse width and duty cycle. Since the curves of Figures 7, 8,
and 9 were determined with VI at approximately 5.9V (much
less than the 6.8V reference) maximum frequency conditions
apply to all Figure 6 curves. With the rise/fall-time capacitance of 68pF at pin 4, the rise/fall delay will affect the duty
cycle when the frequency is greater than 120kHz. Removing
the pin 4 capacitance will extend the maximum frequency to
well above 200kHz. However, use of the rise/fall-time delay
function is important to the control of EMI and RFI. The
optimum riselfall capacitance value is chosen to assure a
50% duty cycle at the maximum frequency with a reasonable
margin in design tolerance and, for the system requirements,
to ensure compliance with EMI and RFI requirements.
The timing circuit of the VIPUR is a stand-alone pulse
generator in which the 0 output of FF1 is amplifi9d by the driver
V.
(START-UP)
output circuit of Figure 4, subject to the logic control of transistor
033 and the proper logic-state control for the slow start (SSn,
ON, Vee, and overcurrent (OC) inputs shown in Figure 5.
+Vcc
13V
30K
+
+
. ; . 4.7""
11K
16K
68jJ.F
1
ERROR
220
7Vcc
47Q
riu~~~·
GND5
RISE
TIME
4
OUTPUT
TON-n-
-:1
FIGURE 4. CA1523 DRIVER AND OUTPUT STAGE
f1
CURRENT OVERSENSE CURRENT
2
11
_
a.....-.If..-TON+TOFF
FIGURE 6. VARIABLE-INTERVAL SWITCHING-REGULATOR
TEST CIRCUIT USED TO OBTAIN TIMING CURVES
OF FIGURES 7, 8, AND 9
11-146
Application Note 8614
Where there are no external system restrictions on the
operation of the CA1523, and the function is that of a pulse
generator, very large values of capacitance may be used at pin
14 to achieYe very low pulse frequencies. External resistor
loading at pin 14 will contribute a nonlinear slope to the otherwise linear sawtooth there. This nonlinear contribution can also
be noted in the waveform at pin 14 if the timing capacitor has
less than 1OMO leakage. Very low values of Is are not recommended because the balance of charge and discharge currents
is, to some degree, affected by base bias and junction leakage
currents. As noted by the degradation of duty cycle balance in
Figure 9, and for practical reasons, Is should be greater than
20!1A The upper limit for Is is determined by the maximum
available collector current from 017C, which is typically 35CJi,IA.
80
.. 70
z
~
TA-+2S"c
VI_s.ev
V._11V
Vcc· 13V
j:
.~
180
40
0
10
100
......
II:
80
:::)
80
S
0
40
20
0
0
50
100 150 200 250 300
SENSE CURRENT (I.. PIN 2) (J1A)
350
FIGURE 7. PULSeJFREQUENCY MODULATOR CHARACTERISTIC OF FREQUENCY va. TIMING CAPACITOR c,.
AND SENSE CURRENT Is (TA - +25"C. VI - 5.9V.
V5
•
..=.
=11V, Vcc" 13V.)
50
...
TA-+2&"C
VI _5.11V
...
iii: 40
Vs_11V
Vcc- 13V
~
!.30
~
~
20
j
w
!l
.p
...
:::)
10
z
200
250
300
The signal waveforms of the CA1523 are shown in Figure 10,
and are based on the test circuit of Figure 6, where Rs is
adjusted for a maximum frequency of 100kHz. Because the
sink and source current drivers of the timing capacitor, CT, are
constant current generators, the waveform at pin 14 is a very
linear sawtooth. As noted in Figure 4, the waveform at pin 4 is
derived from the 075 sink and 076 source drive currents, but
is normally clipped at the top and bottom. The positive tip of
the pin 4 signal Is set by a positive clamp from two series
diodes to an internal 3V bias source, providing a clamp level
of approximately 4.5V. The bottom, or negative, truncation is
the result of a current sink depletion of the charge on the rise!
fall·time capacitor at pin 4. The degree of waveform clipping is
determined by the maximum operating frequency and the
value of the riselfall time capacitor at pin 4.
In Figure 4, the rise, delay, and fall times of the input drive
Signal, 0, are controlled by the capacitance at pin 4, amplified, and output at pin 6. The 0 input, a square wave output
pulse from the timing generator (Figure 3), drives the riselfall
capacitor via the 073 buffer and the 074,075 current mir·
ror. Rise time is determined by the 076 constant current
source. As such, the sink and source currents control the
voltage at pin 4. Capacitance loading at pin 4 .provides a
controlled rise and fall delay time. With the 68pF capacitance
shown in Figure 6, plus 10.5pF probe capacitance, the
waveforms are as shown in Figure 10. A rise-time delay of
1.61J.S is noted at the 2.1V point on the pin 4 waveform. The
Signal at pin 4 drives the base of 078 and, through a resistor
divider, 079. Approximately 2.1 V is required at pin 4 to
switch 079 and set the delay, which can be calculated from
the rise time equation for constant currents. The source cur·
rent from 076 is approximately 100IlA, and the delay, TDo is:
0
0
150
CA 1523 Generated Waveforms And Delays
140
w
100
(pIN 2).
~ 120
8w
er-1oopF
§ao
FIGURE 9. PULSEJFREQUENCY MODULATOR CHARACTERISTIC MON" DUTY CYCLE (PIN 6)_ CURRENT SENSE
Z
tz
/."
SENSE CURRENT (I.. PIN 2) (J1A)
180
..
!
j,
gao
200
io!!.
i
TA-+2&-C
VI- LIV
V._11V
VCC- 13V
l
100
200
SENSE CURRENT (I.. PIN 2) IliA)
To
300
FIGURE 8. PULSeJFREQUENCY MODULATOR CHARACTERISTIC TON!MAX) OUTPUT PULSE WIDTH (PIN 6) ¥S.
CURRENT SENSE (pIN 2). (TA" 25"C, VI- uv,
V5 .. 11V, Vcc • 13V.)
=VC/I =[(2.1 V)(68 + 10.5pF)y(1 OOIlA) =1.6IJ.S
If the rise time capacitor at pin 4 is too large, the peak voltage will be reduced below the poSitive clamp level. This con·
dition will cause the on·time duty cycle at pin 6 to be
increased. The rise time capacitor at pin 4 must be adjusted
to restore the duty cycle to 50% at the maximum frequency
11·147
Application Note 8614
condition. When no external capacitor Is used at pin 4, maximum operating frequencies in excess of 300kHz are possible. An example of the typical CA1523 pulse output
capability at high frequency conditions is provided below.
Using the circuit conditions of Figure 6 with no pin 4 capacitor, Is = 160jJA, and CT =50pF, the pin 6 output pulse is:
tR = 250ns
f(MAX) = 312kHz
TON(Max) = 1.6j.1s
TON(Min)
=0.8j.ls
Additional delay in the pin 6 output drive pulse may result
from the conditions of loading. The normal specifications for
the CA1523 are given for a 68pF riselfall-time capaCitance at
pin 4 and an 1800pF output capacitance loading to reflect
typical drive requirements for a power-FET switch transistor.
The rise and fall times for 1.SV and 10V thresholds at the V6
output are typically tR = 600ns and tF =200ns.
12
8
10
5
~
;:
Q
.
i
w
::E
!
Z
~
•
~
c
4
!;
;e:
...... •
8
3
!l
::>
4
!!l.-1
2 a: i
Q
2
1 ::E
w
...
F=
~
~
:!
:i
CI
3!;
F=
I!
o
10
TIME (jIa)
20
FIGURE 10. SIGNAL WAVEFORMS OF lltE ClRCurr OF FIGURE 4
(WITH 10.5pF TEST-PROBE LOADING). (Or 240pF,
Rs APPROXIMATELY 391<0, FIMAXI 200kHz.)
=
=
Application Circuits
TV Monitor Flyback Converter
Figure 11 shows a typical television receiver application of
the CA1523. Une isolation permits use of the TV receiver as
an RGB or composite-video DC-coupled monitor. In this
system, the switching transformer isolates the power line
from the signal circuits of the TV receiver. As shown in the
block diagram of Figure 11, 120VAC is connected through a
fuse to the bridge rectifier and a step-down transformer, T2.
The rectified output of the step-down transformer is used as
a 16V standby power supply for the TV control module. The
control module, in response to the user input contrOl,
switches Q2 on and off to control turn-on of the VIPUR
regulator through the optoisolator. The bridge rectifier
supplies a +150V raw B+ to the VI PUR start-up circuit and to
the primary of the switching transformer, T1. After start-up,
the run supply provides a regulated +Vcc for the CA1523
from the sense feedback circuit. In normal regulation, the
VIPUR drives the 01 power MOSFET, which switches the
primary of n. T1 converts regulated power to the cold 20V,
25V, and 150V levels required for the power supply outputs
and the run-supply circuit.
Figure 12 explains the on/off operation of the switching
power-supply portion of the converter application. The logic
function maintains control of the on/off operation of the
system. In the off state, the system remains in a standby
mode as long as the 120VAC is connected. Standby power is
supplied via the start-up circuit, which consists of R2 and the
11V zener diode CR3. Continuous start-up bias is supplied
to the +Vcc function at pin 7, the on/off input at pin 12 via the
optoisolator, and the slow-start circuit at pin 10. The 11 V
source is connected to the pin 7 +Vcc function via the
forward biased diode, CR13. The logic function inputs (as
previously noted in Figure 5) are the B+ sense from pin 7,
the slow-start function at pin 10, the on/off function at pin 12,
and the overcurrent function at pin 11. The logic function
responds to a voltage level for each input and, if the voltage
range of a required input is not met, shuts down the output
amplifier, so that no pulses appear at pin 6. After start-up,
normal operation is resumed when the on/off input is greater
than 2.5V, the peak overcurrent input is less than 1.2V, and
the B+ sense has determined that +Vcc is greater than S.4V.
The slow-start function controls the gradual start-up of the
pulse and frequency modulation functions such that a slow
RC rise time at pin 10 is synonymous with a slow decrease
of the pulse interval. As the pin 10 voltage increases, the
slow-start allows a gradual increase of the 10'2 discharge
current. As the voltage at pin 10 increases from 3V to 7V, the
full range of slow-start control over the PIFM changes from
zero to maximum frequency. The RC time constant
consisting of R1, C7, and R3 controls the slow-rise voltage
at pin 10. The slow increase controls the power-up rate and
limits the start-up dissipation in power MOSFET 01.
The on/off function could be controlled by an insulated manual switch or a relay. However, the optoisolator has the
advantage in that it can be remotely controlled with low
standby power. The overcurrent shutdown voltage is sampled from the source terminal of the power MOSFET, 01, to
assure that peak currents in the transformer primary circuit
will be fault-mode limited. When start-up is complete, the run
B+ is greater than the start-up supply voltage from the 11V
zener diode, and CR13 is reverse biased. The on/off and
slow-start input circuits remain under the control of the 11V
start-up source, but the VIPUR power supply is transferred
to the well-regulated run B+ supply derived from the sense
winding of the transformer.
Figure 13 shows the VIPUR switching-regulator output operation as it functions in a normal feedback mode. As explained
above, the error amplifier at pin 1 is differentially compared to
a 6.SV internal reference. The error amplifier supplies the correction signal lor the PIFM. Pulse and frequency modulation is
11-148
Application Note 8614
~~h
.........-M"""""
+20V -.,;.---+-~TO VIDEO/AUDIO CIRCUITS
R11&
•
+20V~~""......J
STARTUP TO DEFLECTION IC
·•
:
CAl
+1---~~f-(-----1~-l4-'
+2SV
TO STEREO AMPL
•
••
•
••
•
···
TO DEFLECTIONAHVT CIRCUITS
+150VOC - ....--2.5V :
~ • HOT GROUND
OFF-OV •
R10
ON/OFF
··•••
CR13
STANDBY
+16V>-.....- - - ,
>-.....-tt:.
Q2 ON/OFF
SWITCH
R11
4~~--"""
J1 ~
i
:
•
If l ·
-!-.
COlD GROUND
•
, :--~--~~ L----lf--i--Tflm-::. ...~
CURRENT
FIGURE 12. SWITCHING POWER SUPPLY ONIOFF OPERATION
11·149
R18
o.1SCl
3W
Application Note 8614
controlled by timing-capacitor C15 and sense-current resistor
R9. The output amplifJer is controlled by \he logic input; its rise
time is controlled by capacitor C14. Zener--~------~~-------------------r~~~L
1~-~:OG1L
:
;
ell
...........1
.......1
FIGURE 3. POWER-OUTPUT SECTION INTERFACING WITH CURRENT SENSING MOSFET OF IGT.
11·157
Application Note 8829
DIL
GIL
"""-
"G2L
TRIPL
CLI
V..
FIGURE 4. POWER OUTPUT SECTION INTERFACING WITH NONCURRENT SENSING MOSFET OR IGT.
For ultimate switching speed. no additional series gate
impedances were used. Peak MOSFET gate charge and
discharge current waveforms of 400 and 510mADC. respectively. were observed. Figure 6.
The HVIC operated flawlessly while being subjected to output swings beyond 11.000V per 115. Figure 7 demonstrates
the HVIC's ability to sustain such dv/dt when driving IRF820
devices.
High frequency. high voltage operation requires that upper
rail drive and level translator circuitry be immune to high dvl
dt. as this section floats with respect to VOUTIPHASE. Interjunction capacitance can dynamically inject displacement
currents. raising havoc in circuit performance or even causing catastrophic failures. including the breakdown of voltage
isolation tubs or latch-up in adjacent four layer structures.
IRF 842s were driven at 130kHz in this same half-bridge circuit. Figure 8. The uHimate switching speed of the SP600
series HVIC will depend on gate capacitance and the duty
cycle limits dictated by the minimum ION and IOFF times. A
minimum ION time (1.~ to 3.1115) ensures time for refreSh.
while a minimum IOFF time (1.3115 to 3.4j.ls) prevents simultaneous conduction by allowing for gate discharge prior to an
opposite ION pulse. The same promising technology has
been shown to operate a half-bridge resonant converter at
frequencies up to 6OOkHz. 6
At rail voltages of 200VDC to 400VDC. rise and fall transitions
of VouTIPHASE were measured in the 20ns to 35ns region.
.------IV81A11
0.22
DIU
c.
GIU
2200
G2U
PHASE
Vou
SP600
HVIC
VOUT
TRIPU
DIL
33
K
GIL
G2L
COM
r
------I
J-....
J--+--.
FIGURE 5. HALF-BRIDGE TEST CIRCUIT
11-158
2200
Application Note 8829
Semicustom Capability
The SP600 family can be customized by inexpensive, final
metal mask alterations. Application specific designs are possible for variations in the following parameters:
o
o
o
o
Input signal conditioning filters
OC trip level
o
Inclusion of RcHARGEIDISCHARGE
o
ITRIP SELECT boost level
FAULT raset timer
o
o
Minimum IQNIIOFF pulses
OC trip response time
o
Other system related options include:
Top: Turn 011
Bottom: Tum On
Vertical: 100mA1dlv
Horizontal: 20ns1dlv
FIGURE 6. GATEoCURRENT WAVEFORMS DRIVING AN IRF820
o
Input protocol
o
Automatic FAULT reset
o
Ability to disable the automatic refresh algorithm
References
1. E. J. Wildi, et ai, "New High Voltage IC Technology," IEOM
84 Conference proc, pp 262-265.
2. E. J. Wild!, et ai, "500V BiMOS Technology and its Applications," Electro 85 paper 12412.
3. J. G. Mansmann, et ai, "ASIC Like HVIC for Interfacing to
HaH-Bridge Based Power Circuits," PESC March 88.
o
4. J. G. Mansmann, et al"A Flexible High Voltage Controller
Core for Half "He" N-Channel Bridge Operation," MOTORCON proc, Sept '87, pp 194-205.
5. O. J. Macintyre, "Motor Control Applications of Second
Generation IGT Power Transistors," GE PESO Application
Note 200.95.
Vertical: 5OV/dlv
Horizontal: 50nsldlv
FIGURE 7. VOUT TRANSIOON AT TURN ON OF LOWER IRF820
6. R. L. Steigerwald, et ai, "A High-Voltage Integrated Circuit
for Power Supply Applications", APEC proc, Mar '87, pp
221-229.
Appendix
Timing Waveforms (See page 6)
Although both SPSOO and SP601 timing diagrams are shown
the SP601 was chosen to provide further explanation.
o
10 < t < 11
Vertical: 5OV/dlv
Horizontal: 50nsIdiv
FIGURE 8. OUTPUT LOAD CURRENT AT 130kHz USING
IRF8428
to. wilh the enable high, the outputs are simultaneously commanded to swilch from lower to upper
which is also known as Bistate operation. After delay
IoFfI) the lower is turned off, followed by the uppers
turned on. Dead lime,lo.v the difference between the
lower off transition 10 the upper on transition is inlernalIy set Since this timing sels the margin of sefety for simultaneous conduction, Ifs the user's responsiblilly to
ensure thel proper external gate Impedance is selected
At
to ensure ample time for power transislor charging/discharging.
11 < t < ~
The lower Is turned on aliI and continues for a relatively long period, long anough thai at t2 an automatic refresh wiN be invoked.
11-159
Z
o
-til
~w
01-
-0
KZ
c..
c(
Application Note 8829
The HVIC has blinded Itself to the logic InpoIS during
this refresh mode. The upper Is turned off, with lIS associated turn off delay, loFFo- After the fixed dead lime,
Io.T., the lower is briefly turned on, lon, providing a
charge refresh path for the bootstrap capacitor, CF
Once agaln the dead lime Is observed before turning
the upper back on again and raslorlng control to the
user inpulS. This refresh cycle can be detecled as a few
lIS wide pulse of lower MOSFET/IGT currenl.
Ie < I < I"
The chip shuts off as the ENABLE line Is broughl low at
Ie, and Is enabled again at 1'0 as the UP/DOWN line
had remained high. Since the disable period was long
and the refresh one shol had limed out, the turn on delay, foNDTo is slow. Keep In mind thaI the delay time Includes the lime for automatic refresh. In anattempl to
not further complicale the drawing, the detailed refresh
cycle lsn'l actually shown.
111 < I < 1,3
80th Inputs ere brought low al 111 for a duration longer
than ~F AI 1'3 the ENABLE Is restored, initiating the
turn on sequence for the lower. This follows a long period
of lime where the one shol had timed ou~ but In this case
the lower Is c:onmanded on. SInce It doesn't need the refresh algorithm, the turn on delay, foNDS, Is fast.
I" < I < 113
This sequence of evenlS deplclS the delecllon of a lower overcurrenl trip. Between 1'3-1'4' the lower Is on. Beyond the filler delay, 1oFFrN, the overcurrenl bip shulS
off the lower driver. A fraction of a lIS laler,
the flag
report delay, FAULT goes low.
The upper remains commanded on for a period of time
less than ~F AI t., the UPIDOWN time is brought low,
commanding a lower turn on. Similar 10 the 10-1, Interval, the upper turns off after delay IoFFD and the lower
turns on after the dead time, Io.T.
The SP601 is disabled by the ENABLE line low al Is.
Previously conducting lower turns off after Its delay,
loF~1)o Since the ENABLE Hne was previously brought
low and neither outpul transistors ere conducting,
lermed as three-stale mode. The stale of the output
phase waveform remains unknown. AI Ie, the ENABLE
Is once again pulled high. The lower turns on after delay, foNDS'
AI 17 , the SP601 Is disabled and the UP/ DOWN Nne Is
toggled 10 the upper position. The lower turns off and the
power devices go Inlo a Ihree-stale mode. AI Ie, upper
turn on sequence begins. Since the auto one shol hasn'l
timed oul yel, the turn on delay, toNo", Is relatively short
"'N'
1'5 < I < I,e
1'8 < I < tit
By holding both ENABLE and UP/DOWN lines low for
the required fault filter resel time, "'.T., the faull Is
cleared.
1'6 < I < 1'7
The upper Is turned on and an overcurrenl trip begins.
Bayond the filter delay,loFFrN, lhe overcurrenl comparator shulS off the upper drive al 117 , Since the control
logic can oniy communicate upwards, there Is no direct
means of reporting an upper trip. As the fault has basn
remotely captured by the floaling upper section, shutdown has occurred. The Phase or VOUT node will quickly fall to a diode drop below corrvnon due to Inductive
ftyback current Via the VOu,NPHASE monitor this is detected as not being In agreemenl with the commanded
Input and reports the fault. Reporting this phase out of
slatuB delay Is IosVF
SP600 Series Timing Diagram
INTERVAL
SP600{TOP
to"
iI
!J
tz',...
'"
!l
Iele '7 ..
..
" ' ,-I_ _....,"
r
1...._ _ _.....
'10
'II
'12'"
,
II
'14'11'1.
'I.
I
Lr
'17'"
II.:...'_.-;'_1
L r I___--'r
r---Ul'--___-:---:-~-.....
I
1------------~~~------~-l ~F r ,~,----ENABLE 0
blflEF"9...F-l..J:blf!EF
L..J -L...J-'blflEF U
Lr
SP601 {
"'-T. ~ ..... "'-T.~
.....
upiDm ! J
'--__...JF1COUlomb recCMll"Ycharge and a leakage current of 2 micro-amps for the bootstrap diode with a
11-165
D-
C(
Application Note 9010
maximum bias current, Ices, of 400 micro-amps. The gate
charge, Ca, of 120 flIII"lOooOOUIobs required to drive the IRF450
was read from the data sheet (see FIgUre 7). The desired PWM
switching frequency will be 20KHz. Using (EO. 2), one 'MlU1d
need a bootstrap capackance of at least 0.31 microfarads. Since
0.33 microfarads Is the I18lCI larger standard capacitance availabIa, a oeramlc capacitor of this value will be chosen.
The length of the refresh time required to charge the bootstrap capacitor still needs to be evaluated. The refresh loop
Is comprised of the bootstrap capacitor, the bootstrap diode,
stray circuit board resistance (the designer has laid out his
circuit to minimize this and stray inductance) and the ROSON
of the power switch. The ROSON of the IRF450 is approximately 0.3 ohms at 10 amps. To the above must be added
the ro of the bootstrap diode, which is about 1.1 ohms max.
at 1.0 amp. Assuming another 0.1 ohm series resistance for
the capacitor and circuit board traces, then a total resistance
of about 1.5 ohms is in the bootstrap loop. The charge time
constant of the bootstrap capacitor is the product of the loop
resistance of 1.5 ohms and the bootstrap capacitance of
0.33 microfarads. This yields 0.5 seconds charging time constant. If 2 time constants are reserved for charging, then the
bootstrap capacitor will only charge to about 86% of the Vce
supply. In 3 time constants it will charge to 95% of the Vce
supply. Keep in mind that the UN circuit maximum trip level
is 9.99 volts. This fact will impact the choice of capacitor and
the allotted refresh time. If we assume 3 time constants are
sufficient, then to drive the IRF450 to 15 volts would require
a Vce voltage of 15195%, or 15.8 volts.
Propagation Delay Issues
The HIP2500 is designed to enhance rejection of noise from
external circuits. Several filters and signal integrators are
used to accomplish the noise rejection resulting in input to
output propagation delays on the order of 400 nanoseconds.
Much of the propagation delay associated with the upper
switch is a result of the level-shift circuit. To better match the
upper and lower propagation delays, additional delays were
inserted in the lower circuit. Filter and matching circuits were
designed to provide tracking of upper and lower propagation
delays over temperature and bias voltage changes. In practice very good tracking Is achievable, with the ·on-delays"
increasing approximately 150 nanoseoonds over temperature and the ·off-delays" increasing about 100 nanoseconds
over temperature. Because the absolute propagation delays
of the upper and lower circuits were not exactly matched, it is
necessary to call attention to them so that the circuit
deSigner can compensate for them.
The variation in propagation delays manifests itself in varying dead-times. Dead-time is defined as the time between
the fall of one of the gate voltage waveforms and the rise of
the other gate voltage waveform. The midpoints in the gate
voltage waveforms are used to time the measurement. A
1000 picofarad load Is used to simulate the "typicar power
device gate-source load. It is possible, when turning off the
upper and turning on the lower switch, to experience a
slightly negative dead-time of less than 50 nanoseconds.
The minimum dead-time experienced going the other way
(turning off the lower and turning on the upper switch) is 95
nanoseconda. The best way to guarantee that proper
dead-time always exists is to insure that the Signals driving
the UN and HIN inputs of the HIP2500 always include
dead-time. This will prevent shoot-through conduction and
possible power device destruction. Dead-time can be
enhanced by using the technique shown in Figure 4. With
proper choice of series gate resistance, it may be possible to
completely mask the effects of dead-time mismatch.
Power Dissipation and Thermal Design
The power dissipated in the HIP2500 can be lumped into
static and dynamic losses. The static losses are limited to
bias current losses for the upper and lower sections of the
IC. The lower bias current, lace, is typically 1.5 mA at +25OC.
The upper bias current, Ices, is typically 3OOjJA. At 15 volts
bias, the total power dissipation is less than 30 mUll-watts.
Since 1000 Is typically only 100 pica-amps, the losses associated with this bias current is insignificant.
The switching losses are those losses associated with turning on and off the upper and lower power devices. These are
the signifICant losses within the HIP2500. The switching
losses can be further broken down into the following components:
• Low Voltage Gate Drive Charge Transfer
• High Voltage Level-Shifter
• High Voltage Tub-Capacitance Charge Transfer
The low voltage gate drive charge transfer power loss is the
most significant of the 3 loss components above. (EO. 3)
describes the power loss attributable to the upper and lower
switch gate charge transfer as a function of bias supply, Vce,
switching frequency, fpWM, gate charge, OG' and the
HIP2500 internal CMOS charge transfer losses, Ointarnal, of
the driver stages. Unless the gate charge of the power
device is very small, O;nternal is not very significant.
PSWLO
=
2fpWM (QG
+ QINTERNAL) Vee
(EO. 3)
The high voltage level-shifter power dissipation, EO. 4, is
much more difficult to analyze. The reason that this equation
is hard to solve is that the level-shift current pulses, ion and
iolf> and the phase voltage, v.hilt' are all functions of time and
the phase voltage moves in response to power switch turnon
and turnOff, which is also dependent on the power MOSFET
or IGBT used. The ion pulse, for example, may come and go
before any movement in the phase voltage is evident and
therefore dissipate very little energy. The phase voltage usually will be a maximum when the ioft pulse comes, so the off
pulse may dissipate quite a bit of energy.
T
PSHIFT
= .!J
(I
+ IOFF ) vSHIFTdt
T
ON
(EO. 4)
o
Finally, the tub capacitance power dissipation can be calculated from EO. 5. The 'ub" is the p-n junction which isolates
all of the circuitry associated with the high side driver from all
11-166
Application Note 9010
of the low side circuits. The calculation is a charge transfer
energy calculation wry similar to that used for the gate
charge transfer, except that the charge is much smaller and
the voltage, vahlft, much larger. This capacitance unfortunately varies with voltage and it is difficult to measure. The
tub capacitance charge transfer losses are shared between
resistances both internal and external to the HIP2500. A
conservatiw approach, how8119r, assumes all of the losses
are dissipated within the HIP2500.
P
TUB
=c
y2
f
TUB SHIFT PWM
10
,. ...
2100pF
f--
~
1I07
r-
(EO. 5)
100pF
"
r--- v•• v... COM, vu. Vee .16V DC, TA. +26"C
f---
Power Dissipation The Easy Way
Fortunately there is a much easier method available for measuring power dissipation and none of the abow equations
ever need to be evaluated. Very simple lab equipment can
be used to obtain the measurements and simple calculations
can be used to obtain accurate results.
The simple method for evaluating power dissipation breaks
down the total power dissipation problem into high voltage
power dissipation and low voltage power dissipation.
Vcc
0.01
ALL SWITCHING LOSSES ASSUMED TO BE IN IC
10
100
1000
SWITCHING FREQUENCY (KHz)
FIGURE 8. LOW VOLTAGE POWER DISSIPATION va
FREQUENCY
If the quiescent bias current and CMOS switching losses are
subtracted from the above power calculation, what is left is
the power required to drive the gate-source capacitance of
the power switches. The power required from Vcc to drive
the gates can also be calculated by EO. 7, where CG is the
combined equivalent gate capacitance of both power
switches. HaH of this power is dissipated in the combined
source resistance of the driver and any external resistance
in the source circuit and the other haH of the power is dissipated in the sinking circuit, including any external resistance
in the sinking path.
PG
= y~CCGfpWM
(EO. 7)
High Voltage Power DiSSipation
FIGURE 8. LOW VOLTAGE POWER DISSIPATION TEST
CIRCUIT
Low Voltage Power Dissipation
The low voltage power dissipation includes low voltage leakage and switching losses associated with gating both of the
power switches. It also includes the CMOS switching losses
associated with both driwr stages. As shown in Figure 8, the
upper and lower bias supplies are tied together and supplied
by bias voltage Vce, while capacitors CL are tied to both of
the HIP2500 outputs. Both inputs are then pulsed at the frequency of interest and the awrage current, Ice is measured.
The total low voltage power dissipation is then simply the
product of Icc and V ce as shown in EO. 6 below:
The high voltage power dissipation component includes the
losses associated with the 18119I-shifter and the tub charge
transfer power losses. This component is not affected by the
size of the power device being switched. Figure 9 shows the
test circuit which is used to measure the high voltage
lewl-shifter and high voltage leakage power losses.
z
o
-CI)
!;i:w
2b
itz
a..
(EO. 6)
Plotting the results of EO. 6 as a function of switching frequency and the load capacitance of each of the power
switches yields a family of curws for the low voltage power
dissipation of the HIP2500 as shown in Figure 9.
c(
FIGURE 10. HIGH VOLTAGE POWER DISSIPATION TEST
CIRCUIT
11-167
Application Note 9010
By measuring Is and Veus and calculating the product of
these measurements, one can obtain the value for total high
voltage power loss for the HIP2500. The value derived will
include both reverse leakage power due to the isolation tub
and two level-shift events. Both the turnon level-shift and the
turnoff level-shift events are included. The high voltage
power dissipation will increase directly with both switching
frequency and bus YOItage level as shown in Figure 11.
~
1
-
~
Q;
~
To aid in locating possible solutions to problems which can
occur in applying the HIP2500 and similar high voltage Ie
gate-drivers, the following table is included.
General Problems end Effect.
PROBLEM
EFFECT
Low Voo and Vss
Low supply volteges can cause UN lockout and blocking of gate drive.
High Voo and Vss
Causes wasted biss supply power due to
overcharging the gates of the external
switches and can result In reduced reliability due to dacressed voltage margin to
Max. bles voltage rating and Incressed 0perating temperature of the IC.
CFtoosmall
Insufficient charge to drive external power
devicss and/or possible UN lockout can
occur.
CFtoolarge
The bootstrap capacitor may not charge
sufficiently to overcome UN lockout level
and gate drive never occurs. Either decrease CF or Increase the refresh time allotted to charge CF
RoATE too big
RoATE X CF time constant too long causing
excessive power device switching !oases.
Also RGATE too big may fail to hold gate
low when the opposing power d8\l1ce turns
on, tending to either turn on the device
prematurely or slow desired turn-off, due
to the Miller Effect May need to bypass
FIoATE with an anti-parallel signal diode.
RoATE too small
RoATE too small tends to reduce effective
dead time and Incresse shoot-through tendency. Also switching dv/dt Incresses EMI.
Negative or Insufficiant dead-time
Can cause external power devices and the
IC to fail, possibly destroying circuit board
traces also. This also tends to severely reduce "refresh" time (see CF too large,
above).
HIP2500 IC gets too
hot
Trying to drive too large an external power
d8\lice. Reduce the switching frequency,
the high voltage bus or lind a power device
with a lower equivalent gate capacitance.
You may also be able to Increase air flow
over the IC and/or add heat-sinklng.
Unexplained arcing In
vicinity of pins 3, 4
and50flC
Poorly cleaned, dirty or Improper attention
to strike and creepage distances for the
bus voltage l8\leI being used may cause
this damage or similar damage between
traces going to these points.
-:;.,.
~
Ii
Quick Help Table
~ ~~
0.1
II:
~
::; 0.01
...
L..o
",.
L,..o
.4ooy
I
.300Y
.my
~
~
~0.001
Y.~
10
"-
1:"'r
I YBIAI .1SV, CL .1ooopF, TA· +25"C
100
SWITCHING FREQUENCY (KHz)
1000
FIGURE11_ HIGHVOLTAGEPOWERDlSSIPATIONvsSWITCHING FREQUENCY
Layout Issues
While a lot of effort was spent in designing the HIP2500 to
be immune to noise, poor layout can cause problems.
Particular attention should be paid to keeping the distance
between the HIP2500 and the power switches as short as
possible. If your design is experiencing any of these effects,
it may be helpful to first look at the possible causes in the
table: Layout Problems and Effects.
Layout Problems and Effect.
PROBLEM
EFFECT
Bootstrapcircuit path
too long
Inductance can cause voHage on bootstrap capacitor to ring, slowing down refresh and/or causing an overvoltage on
bootstrap bias supply.
Lack of tight power
circuit layout (long
circuit path between
upperllower power
switches)
Can cause ringing on the phase lead (Vs)
causing Vs to ring excessively below the
COM terminal causing possible malfunction of the HIP2500 due to excessive
charge being pulled out of the substrate.
Excessive gate lead
lengths
Can cause gate voltage ringing and subsequent modulation of the drain current
and Impairs the effectiveness of the sink
driver from minimizing Miller Effect when
an opposing switch Is being rapidly turned
on.
Floating VSS oMth re-
Csn cause drive pulses to disappear or
excessive current flow between Vas and
COM.
spectto COM. These
shoIJd be tied togetOer.
11-168
Harris Semiconductor
--
--
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--
- .-=
--
--
.=
.=.
~-
-
==
--= --
=== =
- - - - - - - - - - - - - - - --
No. AN91 05.1
=
;;;;;
==
---
Harris Intelligent Power
May 1992
HVICIIGBT HALF-BRIDGE CONVERTER
EVALUATION CIRCUIT
Author: George Oanz
The HVIC high voltage integrated circuit is designed to drive
n-channellGBTs or MOSFETs in a half-bridge configuration
up to 5OOVoc. Power supply and motor control inverters can
be configured for voltages up to 230VAe using the HVIC,
IGBTs and a few other components.
A few precautions should be taken in using the circuit. Lead
lengths between the external power circuit (including gate
and pilot leads), the 15V bypass capacitor (Coo), the bootstrap diode (OF) and capacitor (C F) and the HVIC should be
minimized.
The basic components required to evaluate the features of
the SP601 are shown in the simplified schematic. The recommended load is largely resistive so that the largest current component will flow through the IGBTs, IGT1 and IGT2.
The flyback diodes, 01 and 02, rated SA, will carry a much
smaller flyback current component. A small amount of load
inductance will cause the switching waveforms to simulate
the conditions which would normally be observed with motor
or transformer loads, while limiting the current carried by the
lower rated flyback diodes in this circuit.
The values for Rpua, RpUbo etc., have been chosen to result
in overcurrent trip at approximately 25Apk. At this level of
current, heat sinking for the IGTs and flyback diodes is
required. The series resistance of the upper and lower pilot
resistor dividers would be approximately 11<0; the divider
ratio should cause O.W at the tap at the desired trip current.
When first energizing )'Our evaluation circuit, begin with a
reduced bus voltage of about 20Voc to 3OVoc to verify proper
circuit operation before proceeding to higher voltages.
More specific information can be found in File Number 2428
and File Number 2429 Half-Bridge 500V oc Driver data
sheets and in the Application Note, AN-8829.1.
Simplified Schematic
25voc S VLlNK 3 SOOVDC
D1
GIU
VB1A8
G2U
PULSE
GEN
+lSV
SOC!
R_
loon
V
..!Y!!!S..
2
PHASE
UPIDOWN
RPUb
VOUT
C1
CL2
D2
D1L
HVIC
+
RL
20Q
TRIPU
J!AIJlT
=
GIL
Z
3KW
0-CI)
lL
2b
tiw
lmH
son
~z
0.
CC
G2L loon
ENABLE
CLI
+
~-
TRlPL
2
HVIC - Harris Pan, SP601 (Formerly G8601)
01,2 - Harris Pan, RUR860
R_ RPLo -1I10Q, 1.8W
Cl - O.II1f. 600VDC
tGT1. 2 - Harris Part' HGTA24N6001C
OF - Harris Pan, A114M
RPIJbo RPLb - 68Q, 1.8W
RL - 2OCl, 3KW 13-50
Copyright
e Harris Corporation 1992
11-169
Harris Semiconductor
------ - --- ------- -~
-===
------- ---------------------- -- ---
--
=.-=-==-
No. AN9201.1
Harris Intelligent Power
April1994
PROTECTION CIRCUITS FOR QUAD AND OCTAL
LOW SIDE POWER DRIVERS
by Wayne Austin
Overview
Normally. the defined requirements for a Quad or Octal Driver
are llery much afleclecl by the type of protection circuits used on
the chip. Fau~ protection for an open or shorted load is an interactille function, making it important in the decision process of
specifying the proper IC for an application. The various types of
on-dlip features may include protection for over-current, 0IIerdage and Oller-temperature. The response action to a fauk
condition may be either limiting or shutdown. Shutdown methods
may include hysteresis and may require a logic reset. On-dlip
clamp diodes provide current steering to an external zener diode
clamp as OIIer-dage protection from incIuctiv9 switching pulses.
Internal Zener diodes are also used to limit the output dage on
the output driller of the IC. In addition, fault detection is available
with diagnostic feedback, including serial bus (SPI) control. All of
the protection features noted are represented in the Table 1 listing of Quad and OcteILow Side Drillers:
TABLE 1. QUAD. OCTAL LOW SIDE POWER DRIVERS
TYPE
CA3242
DESCRIPTION
Quad ~ated Inverting
Power Dr.
KEY FEATURES
Over-Current Latch..()ff, Fast
Fault Shut-Down, OUtput
Protectfon Diodes
CA3262 Quad Gated Inverting
Over-Current UmItlng, OverPower Dr.
Temperature Umiting, OUtput
Protection Diodes
CA3262A Quad Gated Inverting Same asCA3262 plus +125"C
Power Dr.
Max. TA Range.
CA3272 Quad Gated Inverting
Over-Currant and Temp. Urnand
Power Dr. with Fault
iting, Fault Rag Output,
CA3272A Mode Diag. Flag Output +125"C Max. TA Range.
CA3Z12A has Improved Fault
Rag OUtput Drive Capability.
CA3282 Octal DrIver with SPI
Over-Current and Over-VoItlogic Control
age Fault Mode Protection
with Fault Mode Feedback!
Control with -40"C to +125°C
Max. TA Range.
CA3292A Quad Gated Inverting Similar to CA3'Z72A with addPower Dr. with Fault
ed Intemal Over-Voltage OUtMode Diag. Flag Output put Clamp.
HIPOO80 1A and 2A Quad Gated Over-Currant (Latch-Qff),
and
Inverting Power Drs.
Over-Temperature (GatesHlP0081 with Multi-mode Diag. Off), Open Load and OUtput
Feedback
Ground Short Detection, OverVoltage Internal OUtput Clamp
Diodes, Fault Mode Feed.
backIControi and -40"C to
+125"C Max. TA Range.
While the CA3282 Octal Driller is quite different from the
quad drillers, it is included here because it is used in similar
applications. The CA3282, HIPOO80 and HIP0081 feature
Power BiMOS with MOSFET Output Drivers for higher current and voltage capability. Because of the additional
dissipation associated with these drivers, the CA3282 and
HIP0081 are provided in a 15 pin SIP power package. The
other Quad Drillers are available in the 16 pin DIP and/or 28
lead PLCC packages which halle special construction for
imprOlled heat diSSipation. All of these Low Side Switches
generally share a common characteristic of 5V input CMOS
or TTL logic 191181 control.
The Quad and Octal Power Drillers include a wide variation
of choice in selecting a device type. The available types are
listed in TABLE 1 which also highlights the key parameters
for most applications. By-type, the protection features of the
Quad and Octal Drivers are listed in the table and are
explained in the following detail of this IC Application Note to
assist the user in making an intelligent device selection for
the application of interest.
CA3242 Quad Power Driver
In normal use, the supply voltage is applied through a load to
an NPN open collector output of the CA3242 quad driller.
The functional block diagram is shown in Figure 1. The maximum current rating of 1A does not distinguish between
average and peak. Each output is independently protected
and latches "OFP when the load current exceeds the latchoff threshold in the "ON" state. The CA3242E feature of
short circuit protection is a responsive high-speed shutdown
of the output drive to a shorted load. Under worse-case
shorted load conditions, the supply voltage is applied direct
to the output device. The latch-off threshold is typically 1.3V
(lscRoN), where RoN is the saturated "ON" resistance of the
output. The CA3242 latches "OFP at a typical short circuit
current of 1.2A with 25118 nominal delay. The ENABLE or the
IN pin of the latch-tripped channel must be toggled to reset
the latch.
To better understand the mechanism of protection when the
CA3242 is subjected to a shorting condition, Figure 2 illustrates that part of the Figure 1 noted as the ·PROT"
functional block. When an over-load current is applied to an
output driver, the VSAT increases to a threshold Iell8I set in a
Copyright @Harrls Corporation 1992
11-170
Application Note 9201
TABLE 2. QUAD AND OCTAL DRIVER FEATURES
CA3272
CA3272A
60V
CA3282
(OCTAL
DR.)
32VTyp.
(Clamp)
1A
HIPOOao
HIPOO81
CA3242
CA3262A
CA3292A
CA3262
8(JVTyp.
36VTyp.
Max. Output Voltage,
50V
60V
60V
32VTyp.
(Clamp)
(Clamp)
No load
(Clamp)
1A
2A
Max. Output load
0.6A
O.7A
O.7A
O.SA
0.6A
Current
Max. VSAT Output Voltage 0.8Vat 0.6A 0.6VatO.6A 0.5Vat 0.6A 0.4Vat 0.5A 0.4VatO.5A
1.00 atO.5A 0.50 at 1A 10atO.5A
Max. RoN Output Reslatance
73V
30V
Max. load Switching
35V
40V
40V
40V
28V
27V
Voltage, VCE(SUS) or
VCLAMP Umltad
Typical Output Current
1.2A
1.8A
3.5A
1.5A
1.4A
1.6A
1.3A
12A
(Latches
(Latches
(Latches
Umlting and/or Shutdown
(Latches
011)
011)
011)
Protection
011)
Output Thermal Umltlng
None
165"C
15O"C
15O"C
None
155°C
155°C
165°C
and/or Shutdown Protec(Umits)
(Umits)
(15°C hys.) (15OC hys.) (15"C hys.) (15"C hys.)
lion (Temp. TJ )
Over-Voltage Protection
Current Steering Clamp Diode
None
Zener Diode Feedback Clamp
Fault Diagnostics
Fault Flag
Fault Mode Flag and Feedback
No
Temp. Range,
105"C
850C
125°C
-40"C to _ °C
Packages:
16 DIP Pwr WEB
4O"CIW
400CNI
4O"CIW
(PC Bd, 8J Al
28 PlCC Pwr WEB
3O"CNI
3O"CNI
3O"CNI
3O"CNI
(PC Bd, 8JAl
15 SIP (Tab H.S., 8J cl
30CNI
a"CIW
comparator circuit. The comparator outputs a switching signal to the protection latch and the input drive Is "latched-off".
The input may be reset with an INPUT or ENABLE toggle, or
by and ON-OFF toggle of the power supply to the control circuits.
:--··· . . . . . . . . . . ------.............. ----i
11 :
IN D"
•
ENABLE
lJ. ~ ,. ·
100 ~•
:•
:
•
10'
:i>
~-'''':8
PROT'
-=t..J
•
!
•••
•
=
••
••
•
••
··••• ...u
•
··•......-
OUTD
CLAMP
OUTC
~aJ. ~~
-=t..J
Oa r-t-J CLAMP
3
~''''1
PROT
18 •
PINS 4, 5, 12 AND 13
: GROUND
-..
~_
I'OC
14 :
15:
INB.
INA
:,
PROT.
•
INC
:
I~
Vcc o :
OUT A
OA
-
- -------...
................... ...... -...
OUTB
•
------~
FIGURE 1. CA3242 FUNCTIONAL BLOCK DIAGRAM
Proper application will protect the CA3242E during turn-off
under shorted load conditions. Observations of wide ranging
conditions have been done to test the shutdown behavior
and has revealed several pitfalls that should be addressed to
assure safe shutdown. One should be aware that a forced
short circuit test condition may be considerably more severe
than a normal application shorted load. In either case, two
problems arise that affect the severity of the overload during
shutdown. These are:
1. A shorted load is inductive and causes the generation of
\/Oltage spikes, exposing the output device to at least 2
times the value of the V+ supply voltage.
2. lack of bypassing can provoke severe oscillations during
the delay period before shutdown is complete. This is typically less than 25115.
The result 01 this oscillation with an inductive load is to alternately stress the output device in both a forward and reverse
direction at rates as high as 1mHz, lasting until shutdown
occurs. This problem is compounded in some applications
when 2 or more devices are used in parallel to increase drive
output. In this case, a short may now draw twice the current of
one driver which, in tum, results in almost twice the uncIamped
IIOItage spike developed across each output transistor.
To suppress oscillations during shutdown requires some
attention to the use of adequate bypassing of both the +5V
Vcc supply and the battery or output supply \/ORage.
Bypassing the output supply will minimize both the transient
oscillations and the voHage spike effects of lead inductance.
11-171
Application Note 9201
Then, the shorted output is stressed in the forward bias
mode with the shorted current determined by voltage
source, duration of short, line resistance and the resistance
of the saturated output. In a practical application, the load
and any potential short may occur in a remote location. As
such, bypassing the output supply may not be practical.
Bypassing the +5V supply with a O.lJ.lF capaCitor closely
wired to pins 11 and 12 of the CA3242E constitutes adequate bypassing of the +5V supply.
Because voltage spikes are normal to the application, a 30V
zener ·clamp· diode is needed to limit the device output voltage spikes to less than the maximum rating of 35V. The
zener clamp diode protection should be closely wired to pins
of the output divide in order to avoid any delay in the voltage
clamping action. Alternatively, the on-chip diodes may be
used in a free wheeling mode by connecting the CLAMP
pins to the supply voltage if it does not exceed 30V during
transients. Zener diode clamp protection is preferred over
the power supply clamp option, primarily because the power
supply may be subject to large transient changes.
FIGURE 2. CA3242 FUNCTIONAL DIAGRAM FOR EACH OUTPUT
CHANNEl.. SHOWN WITH PROTECTION CIRCUIT
CA3262 and CA3262A Quad Power
Drivers
The CA3262 is a quad-gated inverting low-side driver capable of switching 700mA load currents (at +25°C) in each
output without interaction between the outputs. Shown in
Figure 3, each output is independently protected with overcurrent limiting and Oller temperature limiting features. If an
output load is shorted, the remaining three outputs function
normally unless the junction temperature of their output
device exceeds the over temperature limiting threshold of
+ 155°C (typical). Current limiting prevents the output current
from exceeding a value determined by the design (1.2A typical), independent of the load condition. The power
dissipation of the shorted output driver is equal to the product of the limiting value of current and the applied output
collector voltage. If this value causes the junction temperature to exceed + 1550C (typical), the base driw to the output
transistor, and thereby it's collector current, is reduced until
the resulting power dissipation is equal to that value which
maintains the junction temperature at the thermal limit value.
The current which flows in the output transistor in a short circuit mode is therefore a function of the ambient temperature,
the thermal resistance of the package in the application, the
total pOWer dissipated in the package. If the short is
removed, normal operation resumes automatically.
In order to clamp high voltage pulses which may be generated by switching inductive energy in the load circuit, zener
diodes with a value not greater than 30V should be connected to the ClAMP pins. On-Chip diodes are connected
from each output to one of the two CLAMP pins and are
intended for use as steering diodes to provide a path for the
clamped pulse current to a CLAMP pin; allowing the use of
one zener diode to clamp all outputs. Alternatively, the onchip diodes may be used in a free-wheeling mode by connecting the CLAMP pins to the supply voltage if it does not
exceed 30V during transients. Zener diode clamp protection
is preferred Oller the power supply clamp option, primarily
because the power supply voltage may be subject to large
transient changes. Note that the rate of change of the output
current during switching is wry fast. Therefore, ewn small
values of inductance (such as the inductance of several
meters of wire) in the load circuit can generate voltage
spikes of considerable amplitude on the output terminals and
may require clamping to prevent damage.
The CA3262A is a IcMer VSAT wrsion of the CA3262 and is rated
for +1250C ambient temperature applications. The CA3262 is
limited to about +1000c (data sheet rating at +85OC) ambient
temperatures. Otherwise, the protection features described here
apply to both wrsions. FlQUre 3 shows a functional block diagram
for the CA3262 and CA3262A Each type has independent current limiing and !hermallimiting protection for each output driYer.
The maximum current rating of each output is typically greater
than 12.A Howewr, this is not a users choice rating, the current
limiting may range from 0.7A to as high as 2A
Typical applications of the CA3242 and CA3262 quad drivers with the recommended method for use of the current
steering diodes is shown in the circuit of Figure 4. Where
inductive loads are not used, the protective diodes need not
be externally connected. However, the user should be alert
to the potential for stored energy in long wire connections to
the load circuits.
11
r ... ----.. . --------...................................... --------,
Vee 0 :
• V+
(18)
• :•
IN D
•
(16) :
!
10
••
:
:
•• • OUTD
: (14)
• 7 CLAMP
! n~
•
INC(17) :
EN~
(i)lV
INB
15 :
•
(27) :
11
••
••
:
(28)
!
INA ~-r--rr")......;%~4~
•
:•"'--_............_-_...........__...._---_...................................
= .:
PINS 4, 5,12 AND 13 GROUND (PACKAGE E)
PINS 5-11 AND 11-21 GROUND (PACKAGE Q)
PIN "S IN PARENTHESIS APPLY TD PACKAGE Q
FIGURE 3. CA3262 AND CA3262A FUNCTIONAL BLOCK
DIAGRAM
11-172
Application Note 9201
+5V
11
,................................................................................................... -- ........ ----;
0
,
•
V+
·
P.S. (18) :
\I
••
(16)
10
TTL OR
CMOS
LOGIC
LEVEL
INPUTS
(2)
1&
LAMP
(28) :
·•••• ............................................................................................................
~-
FIGURE 4. TYPICAL APPUCATION CIRCUIT FOR THE CA3262 AND CA3262A QUAD POWER DRIVERS WITH PROTECTION DIODES EXTERNALLY CONNECTED TO A ZENER CLAMP DIODE FOR INDUCTIVE LOAD PROTECTION.
The CA3262 and CA3262A will typically survive when
shorted if the output supply voltage is less than 18V. This
potential for failure is flagged in the data sheet as a note
under the Electrical Characteristics table. It takes a few milliseconds to shutdown when the output is short circuited.
During shutdown the dissipation may be excessive and is
primarily determined by Isc which is the limiting current. The
short-circuit current will be limited but the voltage that the
shorted output sees may approach VSUPPly. Not considering
transient effects, the worst case dissipation would be Po
(VsUpPly)x(lsC>. Normally, a shorted solenoid or relay will
have a few ohms of impedance which should prevent catastrophic IC failure in 12V automotive applications. A typical
value for Isc is 1.3A. RoN is the saturated collector resistance of the output transistor with a typical value of U1
VSUPPlY is normally 9V to 16V in automotive applications.
The thermal shutdown could be made faster but the circuit
would not be able to effectively drive lamps which have a
very low resistance in a cold start-up. Lamp drive capability
is a common application use for the CA3262 and CA3262A.
down characteristics differ from the CA3262 by having
hysteresis, the same precaution applies for potential damage from high transient dissipation during thermal shutdown.
The CA3272Q, CA3272AQ and CA3292AO Quad Driver are
provided in the 28 pin web-leadframe PLCC package. This
package has slightly lower thermal resistance than the 16
lead DIP package with a web leadframe.
CA3272 and CA3292 Quad Power Drivers
with Fault Mode Flag
The FAULT DETECTOR circuit of the CA3272, CA3272A
and CA3292A is shown in Figure 6 as an equivalent logic
block diagram. Channel A is one of 4 power switching functions displayed in the diagram. Transistor QA is the protected
power transistor switch that drives the "OUT A" terminal. The
FAULT DETECTOR block illustrates the logic functions associated with FAULT DETECTION. The ENABLE input is
common to each of the 4 power switches and also disables
the FAULT output when it is low. From the "IN A" input to the
"OUT A" output, the switch condition is inverting (NAND).
When IN is high, OUT is low. The FAULT DETECTOR
senses the IN and OUT states and switches QF "ON" if a
fault is detected. Transistor QF activates a sink current
source to pull-down the FAULT pin to a 0 (low) state when
the fault is detected. Both shorted and open load conditions
are detected.
The CA3272 and CA3292 are quad-gated inverting low-side
power drivers with a fault diagnostic flag output. They are
rated for +1250 C ambient temperature applications and
have current limiting and thermal shutdown. As shown in
Figure 5, they differ from the CA3262A by not having output
clamp diodes but do have the diagnostic short-circuit flag
outputs. Each output driver is capable of switching 400mA
load currents at +125OC ambient without interaction between
the outputs. Current limiting functions in the same manner
as the CA3262 with a typical limit value of 1.2A. The current
limiting range is set for O.6A to 1.6A. While the thermal shut-
The CA3292A is equivalent to the CA3272A except that it
has internal clamp diodes on the outputs to handle inductive
switching pulses from the output load. The CA3272A and
CA3292A have significantly higher IOl FAULT output drive
than the CA3272. Expanded functional block diagram detail
of the fault logic is Similar to that of the CA3272 as shown in
Figure 6. The structure of each CA3292A output, shown in
Figure 68, includes a zener diode from collector-ta-base of
the output transistor. This is a different form of protection
than the CA3242 or CA3262 which have current steering
clamp diodes on each output, paired to one of two "CLAMP"
=
11-173
z
o
-0
!(w
()I-
-0
~z
Q.
ct
Application Note 9201
output pins. The CA3292A output transistor will turn-on at
the clamp voltage threshold which is typically 32V and the
output transistor will dump the pulse energy through the output driver to ground.
ENABLE
.--..... _--_...... _-------------_ _---------'"\'
....
:
'
•
' 18
', OUTD
,
26'!
·.
:
IND
-too vcc
:14
,
•
~:
00 :
:,•
:,•
,
8'
~
~
,
'
•
IN Co-t--~_+_I
17:,,
,,
,,
,
,,,
IN BO-;:---1-tH
27:,
,,
,,
·.
1I~~::::-~-1:~'20UTA
:
INA
,
,
ali
QA:
:
d:
FAULTO :
:
i:
1 :
'
•
:,••
.
,•
,,
•
;-_
...... __ .:::=: .... _--_ ..... _......... _------_ ........ __:•
FIGURE 5. CA3272 AND CA3272A FUNCTIONAL BLOCK
DIAGRAM
Each of the outputs are independently protected with overcurrent limiting and over-temperature shutdown with thermal
hysteresis. If an output is shorted, the remaining outputs
function normally unless the temperature rise of the other
output devices can be made to exceed their shutdown temperature of + 165°C (typical). When the junction temperature
of a driver exceeds the +165°C thermal shutdown value, that
output Is turned off. When and output is shutdown, the
resulting decrease in power dissipation allows the junction
temperature to decrease. When the junction temperature
decreases by approximately 15°C, the output is turned on.
The output will continue to turn on and off for as long as the
shorted condition exists or until shutdown by the input logic.
The resulting frequency and duty cycle of the output current
flow is determined by the ambient temperature, the thermal
resistance of the package in the application, the total power
dissipation in the package. Since each output is independently protected, the frequency and duty cycle of the current
flow into multiple shorted outputs will not be related in time.
Long lead lengths in the load circuit may lead to oscillatory
behavior if more than two output loads are shorted.
A diagnostic flag Indicates when an output is shorted. This
information can be used as input to a microprocessor or dedicated logic circuit to provide a fast switch-off when a short
occurs and also to determine by sequence action, which output is shorted. A fault condition in any output load will cause
the FAULT output to switch to a logic "low". Added detail of
the fault logic is shown in Figure SA. Since a fault condition
will be indicated during switching, use of an appropriate size
capacitor to filter the FAULT output is recommended (see
data sheet). This will prevent the FAULT output voltage from
reaching a logic level "(1' within the maximum switching time.
The FAULT detection circuitry compares the state of the Input
and the state of the output. The output is considered to be in
a high state if the voltage exceeds the typical FAULT threshold reference voltage, VTHD of 4V. If the output voltage is less
f------------------.. ------------------·
ENABLE
:
:
:,,
:,
,
,
.......................... _-----
TOB,C,D :
AND FAULT:
:,
--
OVER-VOLTAGE
ZENER CLAMP
DIODE
••
,
--------------_ .. _----- ---------_
... _...'
------------,..
,
:
!•
:
2
,:,
,
:,
,
OUTA
:
,:,
:..... _________ ............ _______
~:
.......... _.... .J
FIGURE 6A. FAULT DETECTOR SHOWN WITH THE CA3272 AND CA3272A
OUTPUT STAGE
,,,
2
TLII
,
,,: OUTA
!,,,
,
,,
,,:
:,
l!,,
lUll
..,,
..:,
:
!__ . ---------------.......:::-.......... --:
FIGURE 6B. CA3282A OUTPUT STAGE WITH
CLAMP DIODE
FIGURE 6. FAULT DETECTION FUNCTIONAL BLOCK DIAGRAM OF THE CA3272. CA3272A AND CA3292A
11-174
Application Note 9201
than VTH[) the output is considered to be in a low state. For
example, if the input is high and the output is less than VTH[)
a normal "ON" condition exists and the FAULT output is high.
If the input is high and the output is greater than VTH[) a
shorted load condition is indicated and the FAULT output is
low. When the input is low and the output is greater than
VTH[) a normal ·OFF" condition is indicated and the FAULT
output is high. If the input is low and the output is less than
VTH[) an open load condition exists and the FAULT output is
low. The FAULT output is disabled when the ENABLE input
logic level is low.
To detect an open load, each output has an internal low-level
current sink which acts as a pull-down under open load fault
conditions and is always active. The magnitude of this
current plus any leakage associated with the output
transistor will always be less than 1001JA. (The data sheet
specification for ICEX includes this internal low-level sink
current). The output load resistance must be chosen such
that the voltage at the output will not be less than VTHO
when the ICEX sink current flows through it under worse
case conditions with minimum supply voltage. For example,
assume a 6.5V minimum driver output supply voltage, a
maximum FAULT threshold reference voltage of VTHO 5.5V
and an output current sink of ICEX 1001JA. Calculate the
maximum load resistance that will not result in a FAULT
output low state when the output is OFF.
=
RLOAO(max)
=
=[VSUPPLY (min) - VTHO (max)] IICEX (max)
RLOAO(max)
=(6.5V - 5.5V) 11001JA =
10kn
Since the CA3272 and CA3272A do not have on-Chip diodes
to clamp voltage spikes which may be generated during
inductive switching of the load circuit, external zener diodes
(30V or less) should be connected between the output terminal and ground. Only those outputs used to switch inductive
loads require this protection. Note that since the rate of
change of output current is very high, even small values of
inductance can generate voltage spikes of considerable
amplitude on the output terminals which may require clamping. External free-wheeling diodes retumed to the supply
voltage are generally not acceptable as inductive clamps if
the supply voltage exceeds 3tJV during transients.
CA3282 Octal Power SiMOS Driver with
SPISus
The CA3282 is a logic controlled f> 1 or M < 1. The expressions In Table
3 assume that Ll and '-2 are large with only small current
ripple. For the case where the inductors are operating close
the CCM·DCM boundary. the current waveforms will be
triangular rather than rectangular and the RMS values will be
approximately 15% higher.
The boundary between CCM and DCM modes will depend
on several variables. For a given load resistance (RL=Vdlo).
fs and M. the values for the critical inductances of Ll and '-2
are:
A graph of Equation 4 is given in Figure 7 with comparisons
to the buck. boost. Cuk and buck·boost converters. The
large signal input·to-output voltage ratio for the SEPIC is
identical to the Cuk and buck boost circuits except that there
is no polarity inversion. Vo may be either less than or greater
than VI depending on O.
L
Vc/VI
0
M
M+l
M
0
1-0
(11)RMS
MIO
VLl
Vo. M ~ 1 and VdM. M S 1
VS1
[M+1]
--;;.1 Vo = VO+VI
(lSl)AVG
Mlo
(IS1)RMS
IOJM2+M
VCl
VdM=V,
JRL
Equation 5
~C = [2IS(~ + 1) JRL
TABLE 3. SEPIC CCM VOLTAGES AND CURRENTS
M
- [
1
1C- 2IS(M2+M)
Equation 6
If the inductor values are higher than critical. then the
converter will operate In CCM. If the values for the inductors
are less than critical then the converter will operate In DCM.
The ratio of '-2c to Ll cis:
L2C
-=M
L1C
Equation 7
A very important point here is that the currents in Ll and
constant and VI is varied then the CCM·DCM transition will
occur at some other point and will involve an intermediate
mode.
In distributed power systems VI is the DC bus and is
normally relatively well regulated so the M varies only over a
small range. In that type of an application. a smooth
transition from both Inductors in CCM to both in OCM will be
possible. If '-2/Ll does not equal M then the circuit behavior
will be quite different.
100
(IC1)RMS
VL2
(12)RMS
VOl
(I01)AVG
BUCK·BOOST. CUK AND SEPIC
11.01(1-0)
IOJM
Yo. M ~ 1 and VdM = Vb M S 1
10
[M+1]
--;;.1 Vo = VO+VI
l:!
go to zero simuHaneously only if '-2/Ll = MI If Vo is held
10
$•
~
-
,
~
~ -~
II. 11(1 • D) BOOST
"
lJ..,...-
1
,
::I
10
I
0.1
BUJ'
M.O
(I01)RMS
IOJM+1
0.01
VC2
{1C2)RMS
loJM
I
I
0
Vo
0.1
G.2
o.a
0.4 0.1 0.1
DUTY CYClE (D)
0.7
0..
0.1
1
FIGURE7. VOLTAGE TRANSFER AS FUNCTION OF DUTYCY·
CLE FOR VARIOUS TOPOLOGIES
11·182
Application Note 9208
If 12 reaches zero before II' 0 1 will still be conducting
because of the current in L 1• This means there will be a
voltage across l.:! which reverses 12• This leads to two
additional operating modes. Current waveforms for the case
where 11(T) > -1 2 (T) are shown in Figure 8. This mode
corresponds to the C, -C state in Table 2. Figure 9 shows the
waveforms for the case where 11 = -1 2 at t < T. In this mode,
when 11 = -1 2,0 1 drops out of conduction and a new operating state is introduced as shown. During this state (t2 to T)
the inductor currents are constant (ideally) because the
voltage across C 1 cancels the input voltage. The conduction
mode shown in Figure 8 is a continuous conduction mode
but different from the continuous conduction mode where the
current is unidirectional in both inductors. In the mode shown
in Figure 9 the inductor currents are continuous but because
of the period of time where di/dt = 0 (t2 to T) the circuit will
operate in a discontinuous mode. This mode corresponds to
the C, -0 mode in Table 2.
Both of these modes, C, -C and C, -0, have different
characteristics from those mentioned in the previous
discussion of continuous mode operation. The conditions
where the current in Ll reaches zero before the current in l.:!
will be similar.
CCM Circuit Example
The following numerical example is provided to give a feeling
for the component sizes and stresses in a typical application
for the SEPIC converter.
Let:
V 1 =35V
Vo= 12V
Po=50W
fs= 1MHz
From this it can be seen that:
10 = 4.2A
RL =2.BSn
M =0.34
From Equations 5 and 6:
L1C=3.2~H
L2C=1.1~H
To operate well within CCM and minimize the RMS currents
let:
Ll
= 5ILH
l.:! = 1.7~H
These inductors could be a single layer, wound on small
powdered iron or NiZn ferrite cores. From the equations in
Table 3:
V Sl =47V
(I S1 )RMS 2.8A RMS
=
A MOSFETwith BVoss = 60V would be appropriate for SI.
o
Vol =47V
(I 01 )AVG = 4.2A
r-----~--~-------
A 60V Schottky diode could be used for 0 1.
~
o
VCl =35V
(I C1 )RMS = 2.4A RMS
~~~~~~~~---
For C l a 50V, 0.47 to 1~F, multilayer, ceramic chip capaCitor
would be appropriate.
FIGURE 8. INDUCTOR CURRENTS FOR 11 > ~ AT t
=T
VC2 = 12V
(I C2 )RMS = 2.4A RMS
For ~ a 25V, 1~F, ceramic chip capacitor would be appropriate.
o .....------+-----!---.....---
ol-"7I',c...--+-~-+--~-
T
FIGURE 9. INDUCTOR CURRENTS AT 11
11-183
-It FOR t < T
Application Note 9208
OCM Circuit Operation
=
The following discussion assumes that liLl
M and that
both inductors go into discontinuous conduction simultaneously.
Operation in the DCM mode adds an additional circuit state
0, the point at which 8 1 is
as shown in Figure 10. At t
turned on, 11 and 12 O. The current in both inductors will rise
until 8 1 turns off (Figure 10A). At that point the energy in the
inductors is discharged into the output (Figure 106). When
the inductor currents reach zero, 0 1 stops conducting and
the final state is assumed (Figure 1OC). No current flows in
the inductors because the voltage on C 1 cancels VI'
=
=
referred to as a coupled inductor. A coupled inductor version
of the 8EPIC topology [14J is shown in Figure 13. This
topology has several advantages. The leakage inductance of
the coupled inductor can be arranged to effect zero current
ripple on the input with finite value of L. Because the turns
ratio between the windings is 1: 1, there cannot be two
different values for Ll and ~. This does not lead to multiple
modes however. Because they are wound on a common
core, both windings are either conducting or not depending
on whether there is energy In the core or not. The circuit
operates either CCM or DCM.
1.0
0=
Equation 8
B
0.7
tl
0.8
t
ISL 1
'C L
= RL
Equation 9
§
Values of 'CL greater than this limit mean that the converter is
operating in CCM for the particular value of M.
Graphs of Equation 8 is given in Figures 11 and 12. These
graphs illustrate the effect of varying load on the output
voltage for M > 1 and M < 1.
a
L.
~
SION,D.OFF
v.
0.5
V
V
0.4
'CL .o.Ol
0.3
V 1/ 't
/'C, / '
~
0.0
0.0
0.1
lb ." \
0.2
0.3
G.4
L .O.05
'::...... ~-t..- ~ ~ .-
0.5
0.8
0.7
0.8
0.8
1.0
M.VaN.
FIGURE 11. SEPIC CONVERTER IN THE DCM MODE FOR A
FAMILY OF LOAD PARAMETERS, 'C. WITH THE
VOLTAGE TRANSFER RATIO. M < 1
1.0
+v••
0.8
C~II 0
./
V'
./
\.. 10"'"
~'" \.0.1
'CL" .l.0
0.1
2M3
I
'CL .O.5
0.2
Equation 8 is only valid for 0 < 1. This sets an upper limit on
'CL of:
('C )
_ M+1
Equation 10
L MAX -
I
0.8
J'CL[M~J
Where:
,/
0.8
The expressions for 0 and Mare:
I
0.8
B
0.7
~
l
7'
1 t-L 'tL• 0.05
I I
/
7 :::::::::-'tL.O.l ./
~ -1-.
~ 0.&
§
I
1 I IL.o.si/'
0.&
L.. 0.01_
"'-·'C
77 'tL. l . 0 /
G.4
'/
II
rU7
0.3
0.2
0.1
./
;'
V
0.0
0
2
3
4
M.VoIY.
5
•
7
8
C. SI AND D. OFF
FIGURE 12. SEPIC CONVERTER IN THE DCM MODE FOR A
FAMILY OF LOAD PARAMETERS. 'C. WITH THE
VOLTAGE TRANSFER RATIO. M < 8
11. 12. 0
FIGURE 10. SEPIC DCM CIRCUIT STATES 411-1
=M
Coupled Inductor Operation
Referring to Figure 6, when 8 1 is closed, the voltage across
both Ll and ~ is equal to VI' From Figure 66 it can be seen
that for the remainder of the switching cycle the voltage
across Ll and ~ is equal to Vo 6ecause these two voltages
are equal and in phase, Ll and ~ may be integrated into a
Single magnetic structure with only one magnetic path, this is
11-184
FIGURE 13. COUPLED INDUCTOR SEPIC
Application Note 9208
References
Appendix
[1] Wittlinger, H.A.; Hodgins, Robert G.; Cassani, John C.;
Hurd, Jonathan J. and Thomas, David R. Sophisticated
Control IC Enhances 1MHz Current Controlled Regulator
Performance, High Frequency Power Conversion (HFPC)
conference proceedings, May 1992, pp. 167-173
SEPIC Equation Derivations
Operation CCM OperaUon
[2] Smith, Craig D. and Cassani, Distributed Power Systems
Via ASICs Using SMT, Surface Mount Technology,
October 1990
for
CCM
and
The following calculations are referenced to Figure 6.
For C1 and C2 large: VC1 = VI and VC2 = Vo
When S1 is closed: VL1 = VL2 = VI
[3} Maksimovic, D., Synthesis of PWM and Quasi-Resonant
DC-to-DC Power ConV8rters, California Institute of Technology Ph.D. thesis, Division of Engineering and Applied
Science, January 1989
When S1 is open: VL1 = VL2 = -Vo
[4} Maksimovic and Cuk, Switching ConV8rters With Wide DC
ConV8rsion Range, High Frequency Power Conversion
(HFPC) conference record, May 1989
For 0 = IotIT and M = Vr;jV1 Equation A1 reduces to:
[5}
Maksimovic and Cuk, General Properties and Synthesis of
PWM DC-to-DC ConV8rters, IEEE Power Electronics
Specialists Conference (PESC) record, June 1989
[6}
Liu, Oraganti and Lee, Resonant Switches - Topologies
and Characteristics, IEEE PESC record, 1985, pp. 106116
[7}
Zhang, Chen and Lee, Variations Of Quasi-Resonant DCDC ConV8rter Topologies, IEEE PESC record, 1986, pp.
381-392
[S}
Ngo, K, Generalization of Resonant Switch and QuasiResonant DC-DC ConV8rters, IEEE PESC record, 1987,
pp.395-403
[9}
Maksimovic and Cuk, Constant-Frequency Control of
Quasi-Resonant ConV8rters, HFPC record, May 1989
[10} Tabisz, and Lee, Zero-Voltage-Switching Multiresonant
Techniques - A N0V81 Approach to ImproV8 Performance of
High-Frequency Quasi-Resonant ConV8rters, IEEE PESC
record, 1988, pp. 917
DCM
By conservation of flux in the inductors:
VI IoN = Vo (T - IoN)
(A1)
M = D/{1- D)
(A2)
Equation A2 can be inV8rted:
0 = MI{M + 1)
(A3)
Assuming that L1 and 4 are sufficiently large that
the current ripple is small and substituting A3
10 = (11 + 12) (1 - 0) = (11 + 12){1/(M + 1»
(A4)
For Power In =Power Out:
VI11 = Volo M = Vr;jV1 = 11110
(AS)
Combining Equations A4 and AS:
12 = 10
(AS)
S1 Voltage and Current
ForS1open:
VS1 = VC1 + Vo= VI + Vo
(A7)
Restating in terms of M and Vo:
VS1 {1 + 1/M)Vo
(AS)
=
[11} Sokal and Sokal, Class E - A New Class of High Efficiency
Tuned Single-Ended Switching Power Amplifiers, IEEE
Journal of Solid-State Circuits, June 1975, pp. 168-176
For S1 closed:
(lS1) RMS = (1 1 + 12 )
[12] Mansmann, Jeff; Shafer, Peter and Wildi, Eric, Maximizing
the Impect of Power IC's Via a Time-to-Market CAD DriV8n
Power ASIC Strategy. Applied Power and Electronics
Conference and Exposition (APEC) proceedings, February
1992, pp. 23-27
Which reduces to:r-_-=-
[13} Severns and Bloom, Modern DC-to-DC Switchmode
Power ConV8rter Circuits, Van Nostrand Reinhold, 1985
By inspection:
{I 01 )AVG 10
(A11)
When S1 is closed:
V01 VI + Vo = {1 + 1/M)Vo
(A12)
[14} Sum, K, Switch Mode Power ConV8rsion - Basic Theory
and Design, Marcel Dekker, In., 1984
[15} Pressman, A., Switching and Unear Power Supply. Power
Converter Design, Hayden Book Co., 19n
[16} Massey, R.P. and Snyder, E.C., High Voltage Single-Ended
DC-DC ConV8rter, IEEE Power Electronics Specialists
Conference (PESC) record, 19n, pp. 156-159
[17] Clarke, P., A New Switched-Mode Power ConV8rsion
Topology Provides Inherently Stable Response, POWERCON 10 proceedings, March 1983, pp. E2-1 through E2-7
JD
(I S1 )RMS = IOJ(M+M2)
(A9)
(A10)
Z
D1 Voltage and Current
=
=
0
-en
~w
Go
Note the switch and diode have the same peak voltage.
Inductor Currents
(A13)
(12)RMS = 10
11-185
()I-
-0
~z
(A14)
c(
Application Note 9208
This assumes small current ripple. If smaller inductors are
used such that the inductor currents are nearly triangular
(near the OCM-CCM boundary) the RMS current values will
be approximately 15% higher.
CapaCitor Currenta
(I C1 )RMS
Combining Equations A 19 - A22:
LIe" (1I2fsM(M + 1»)RL
(A23)
A similar calculation for ~ yields:
~ '" RLI(2Is(M + 1))
(A24)
DCM Analysis
= Jll(1-0)+ll
(A15)
For this analysis it will be assumed that:
(A25)
(A16)
This means 11 and 12 go to zero simultaneously. The circuit
states shown in Figure 10 will be used for this analysis.
(A17)
tl = IoN = on time 01 51
t2
Which reduces to: (I C2 ) RMS
= lo./M
(A18)
=the current fall time in the inductors
From conservation 01 flux in Ll and
VitI =Vot2
~:
(A26)
From conservation of charge in Cl
11AVGt2 I2AVGtl
(A27)
For a given current. the critical inductance is the value for the
inductor that allows the current to just reach zero at the end
01 the switching cycle. This is a special case of CCM.
From conservation of power:
VlllAVG .. Volo
(A28)
~
Derivation of expressions for M and 0
Values for the Crltlcallnductancss of
~
and
lz
=
Critical
The input current will be triangular. lIP
current:
lIP = 211AVG = 2Mlo
=peak value 01 the
(A19)
(A20)
(A29)
11 +12
11AVG
J
(A30)
Combining Equation A27 through A30:
(A21)
Is =1rr
= '1P [ 2T
(A22)
11-186
(A31)
0=
Harris Semiconductor
--
--------- - --- - ---- -= -===- -- -- - ----- ------ ----
.=-=-=-=-
No. AN9209.1
Harris Power MOSFETs
April1994
A SPICE-2 SUBCIRCUIT REPRESENTATION FOR POWER
MOSFETs, USING EMPIRICAL METHODS
Author: C. Frank Wheatley Jr., and Harold R. Ronan, Jr.
Abstract
An accurate power-MOSFET model is not widely available
for CAD circuit simulation. This work provides a subcircuit
model which is compatible with SPICE-2 software and
MOSFET terminal measurements. SPICE-2 is the circuit
Simulation package of choice for this work because of its
universal availability, despite its inherent limitations. These
limitations are circumvented through circuit means.
This effort models power-MOSFET terminal behavior consistent with SPICE-2 limitations; hence it will differ from the
physical model as suggested by Wheatley, et all, Ronan
et atl! and others. We feel we have advanced prior efforts3
particularly in areas of third-quadrant operations, avalanchemode simulation, switching waveforms and diode recovery
waveforms.
Discussion
The subcircuit shown in Figure 1 is described in Table 1. All
passive circuit elements are constants. The very-high-gain
JFET is used to simulate the dual-slope drain voltage vs time
switching curve common to the power MOSFET. 1,2
NOTE: If the JFET source voltage, E1, is very low relative to
its VP1NCH IIOllage, the JFET is in a highly conductive state,
tightly coupling C2 to the JFET drain. However, as the vollage El approaches V p1NCH' the JFET operates In a constant-current mode, thereby permitting a much laster drain
slew rate, which is determined primarily by C3 .
If El exceeds VPINCH, errors will exist in the turn-on waveforms. The C2 discharge current-controlled current source
remedies this situation in conjunction with the subcircuit containing O2 , The O2 ideality factor was set at 0.03 to assure
that El minus VP1NCH does not exceed several millillOlts.
The body diode cannot be properly modeled by the JFET
gate-drain diode, hence OBOO¥ Conditions of Table 1 assure
that most third-quadrant current flow is via 0SOD'f' Avalanche
breakdown is more accurately modeled by the clamp circuit
containing 0,.
Table 1 in combination with Figures 2, 3, 4 and 5 provides
the required empirical inputs. Table 2 lists the preferred algorithm lor parameter extraction.
MOSFET
JFET
C3
BOOYDIOOE
ROAAIN
D
01
G
-+----IIi+-.
O2
Rs
RDRAIN
Ls
VptNCH
s
FIGURE 1. SPICE-2 SUBCIRCUIT FOR POWER MOSFET SIMULATION.
TABLE 1. EMPIRICAL INPUTS
Enhancement mode; W = L = 1jUTl; Kp (Rgure
2); VlO (Rgure 2); C's = 0; loso = IE -12
Depletion mode; areas factor = 1; B = 100Kp
(Rgure 2); VlO = VptNCH (Rgure 5); C's = diode
lifetime = RSERIES = 0; diode Ideality factor = 1.0,
1050= IE-2O
Is front Figure 4; Ideality Factor = 1.0; R from
Figure 4 (must be very much greater than Ra);
C (from Cosal; lifetime = best fit 10 TRR
Is ,. arbitrary; C ,. "fetlme .. 0; Ideality factor ,.
best Iow-current fil; R = best high-currenl fit
Is = 1E -8; C = lifetime = R = 0; Ideality factor =
0.03
Rgure2.
Rgure3.
Approximately (5L) In (4 IJd) nH; L and d are
source wire inches.
VlO ofJFET.
V SRK
Avalanche voltage.
C1
C2
C3
Front Figure 5.
Maximum front Rgure 5.
Minimum from Figure 5.
Copyright@Harris Corporation 1994
11-187
Z
0
-(J)
!;;iw
2b
iiz
Il.
c(
Application Note 9209
RFP11N11
•
RFP15N15
20
IJ
Vos>Vas
11
10
(SATURATED REGIME)
1
2
y'/
VTHAESHOLD
I
4.0
2
0
5.0
8.0
4
6
los (AMPERES)
7.0
Vas (VOLTS)
FIGURE 2. SQUARE ROOT OF DRAIN CURRENT va GATE
VOLTAGE DEFINES VTHRESHOLD, Kp, AND R••
FIGURE 3. DRAIN CURRENT va DRAIN VOLTAGE WITH CONSTANT GATE VOLTAGE DEFINES "ON" RESISTANCE.
RFP15N11
RawN-1C11l
to-1mA
TEST CIRCUIT
(SEE REF. 1)
135
11.0
,
SLOPE - 100(C, +
~+CaI
I
oR
§
3.0
46
.'.'
.-'.'
,---Is
o
VI]8(VOLTSI
7. Use trial VPlNCH
8. Use C2 (Maximum), C3 (Mlnumum) are curve-fit C's
9. Adjust VP1NCH to fix gate voltage plateau
40
nME (pal
FIGURE 4. THIRD-QUADRANT OPERATION DEFINES !sAND R
OF DIODE Daom.
TABLE 2. PREFERRED ALGORrrHM FOR PARAMETER
EXTRACTION
1. Determine Kp of lateral MOS
2. Determine VTH of lateral MOS
3. Determine C,
4. Determine C, + C2 + C3
5. Determine Ros
6. Assign B of JFET = 100 x Kp of lateral MOS
20
FIGURE 5. DRAIN AND GATE VOLTAGE va TIME DETERMINE
Ch Ct. Ca AND VPlNCII'
Results
Figure 6 and Figure 7 compare measured static data to
calculated transfer curves and output curves. Calculated
static-output curves are shown in Figure 8 and Figure 9 for
third-quadrant range, including avalanche.
Calculated switching data is compared to measured
switching curves 1,2 in Figure 10 and Figure 11. Calculated
body-diode recovery curves are shown in Figure 12.
11-188
I
20
r
•
-
I
,
I
MEASURED
CALCULATED
RFP15N16
j
0w 10
a:
w
Do
)
~
II
,
1.0
Application Note 9209
Hr-------r-------r-------r-------,
•
RFP15N15
MEASURED
21
V
2O~------r-~~~r-------r-------i
If
f
r
0.1
3.0
5.0
7.0
2
•
4
Vos(VOLTS)
VOS(VOLTS)
FIGURE 6. DRAIN CURRENT vs GATE VOLTAGE (NOTE
SQUARE ROOT SCALE) • MEASURED CURVE vs
CALCULATED POINTS.
I
FIGURE 7. DRAIN CURRENT vs DRAIN VOLTAGE FOR CON·
STANT VALUES OF GATE VOLTAGE· MEASURED
CURVES vs CALCULATED POINTS.
Vos(VOLTS)
·1
-0.8
RFP15N15
-06
-04
~
I
I
-0.2
0
40
0
RFP15N1
H
-Ii
0
w
a:
w
•,0
·16
0w
a:
w
I
1 1
J
20
J
10
0
-20
0
40
80
120
180
200
Vos(VOLTS)
FIGURE 8. THIRD-OUADRANT DRAIN CURRENT VI DRAIN
VOLTAGE WITH CONSTANT POSITIVE GATE
VOLTAGE (CALCULATED).
FIGURE 9. F1RST·QUADRANT DRAIN CURRENT vs DRAIN
VOLTAGE, Vas" CONSTANT. NOTE AVALANCHE
BREAKDOWN (CALCULATED).
10
75
10
8
80
I
'i
4~
0 45
·i
iJ30
2
4
15
~
2
o
FIGURE 10. DRAIN AND GATE VOLTAGE vsTIME FOR CON·
STANT GATE CIRCUIT· MEASURED CURVES VI
CALCULATED POINTS.
Z
0-tJ)
200
400
100
TIME (na)
100
1000
FIGURE 11. DRAIN AND GATE VOLTAGE vs TIME FOR STANDARD SWITCHING CIRCUIT • MEASURED
CURVES VI CALCULATED POINTS.
11·189
!ccUJ
~b
~Z
Q.
(J
III
"c
~
AA-
I-
~!
-'III
~~
0"
:I!~
ti5
1La::
!Z(/)
~a::
:EG
a::~
e!i
II
ifi"
15~
i~
~
19.5rnA
36V
30ns
".SA/rnA
30mS
26Vto
..2V
2".7rnA
36V
30ns
2.6A1mA
10Vto
45V
14mA
l2V
30ns
".5A1rnA
~
III
(Jill
a:c
!SKI
(Ja:
i
loI:
~5
6~
:EIII
a: AIII
ill
8
dli
-'ifi
~5
111111
~I-
~IE
5.W
l2O"C
lMHz or
External
30mS
5.1V
l2O"C
1MHzor
External
NlA
External
l2O"C
External
,...----+iVODP1
z
o
-",
tiw
()I-
-0
~z
Q.
cC
E1
FIGURE 7. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5062
11-195
Application Note 9212
v.. _ - - - - - - - - - - - ,
IttH
0."""
o.66tLF
-==
-
2.71'H
S.1Y
12V
15
0.88
"" ""
0.88
""
-12V
FIGURE 8. SCHEMATIC DIAGRAM OF THE HIP5062IN A TRIPLE OUTPUT POWER SUPPLY
stage to minimize large asymmetrical transient currents.
From the 12V output, a low current, -12V output may be
derived as shown In Figure 8.
The HIP5063, shown In block diagram of Figure 9, is the most
flexible of these devices. It is intended to be used In conjunotion wRh either of the other two devices as an added power
MOSFET with thermal monRoring and the basic current control circuitry. Its application can range from power supply functions to power amplifiers for both audio and servo amplifier.
An extemal op amp Is used to provide the error amplifier function. This allows the designer to optimize the control loop for
transient response In these varied applications.
performance in several ways. To minimize some of these
effects, 8 source leads are provided, again reducing lead
inductance and resistance. Resistance and inductance in
this lead would allow large voltages to be developed from the
MOS source to ground. This can result in an effective loss of
gate drive signal which appears as a loss of transconductance and an increase of ros (on). Voltage drop across the
device is also increased with resulting reduction in efficiency.
Succe88ful1MHz Operation and EMI
Another consideration is bypassing. High peak gate currents
exist around the output stage and the gate driver. On this chip
additional terminals are brought out to permit bypassing of the
positive supply voltage of the gate driver stage, returning the
current directly back to the DMOS source terminal. Internally,
the gate drive stage Is returned to the DMOS source.
Aside from an on-chip, high-speed, high-power DMOS tranSistor, external circuR techniques play the most important
role in the realization of excellent performance at higher freQuencies. Parasitic inductance must be minimized. This is
achieved at the chip level with 8 drain leads. Inductance at
this point can lead to extremely large transient voHages at
the MOS drain and reduction in supply effICiency. A secondary benefR to parallel contacts is the reduced resistive
losses. Voltage drops in the source terminal degenerate the
Surface mount capacitors are used to minimize lead inductance. Four O.22I4F capacitors are used in the drain connection to reduce series inductance. All components including
the inductors are surface mounted. These techniques that
are so essential to excellent high frequency performance
also help to minimize both radiated and conducted noise.
Short leads and low profile due to surface mounting and a
large ground plane all contribute to efficiency and minimal
interference.
11-196
Application Note 9212
8
FUP-R.OP
" ' - -.....
~AST RESETQ
11ION
CONTROL
L-------tBLA:K1NQ
LOGIC
--
IREF
~------~~--'----iIRR
IOONOI
EXTERNAL CURRENT SCAUNQ RESISTOR
IPEAJdOMOS DRAIN CURRENT). 4&00" ~F (mA)
FIGURE 9. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5063
Conclusions
A family of new 1MHz, current controlled switching regulators has been described that have many features that make
these devices especially attractive to distributed power
systems for both large main frame systems and the ever
expanding consumer and industrial markets.
References
(1). Cassani, John C., Hurd, Jonathan J., Thomas, David
R., Hodgins, Robert G. and Witt linger, H. A., Sophisticated Control IC Enhances 1MHz Current
Controlled Regulator Performance, 1992 HFPC
Proceedings, pp 167-173.
(2). Smith, Craig D. and Cassani, John, Distributed Power
Systems via ASICs Using SMT, Surface Mount
Technology, October 1990.
(3). laDuca, J. and Massey R. P., Improved Single-Ended
Regulated DCIDC, Converter Circuit, IEEE Power
Electronics Specialists Conference Record. June 1975,
pp 1n-187.
(4). Massey, R. P., High Voltage Single-ended DC-DC
Converter, 19n IEEE Power Electronics Specialists
Conference Record, pp 156-159.
(5). Goodenough, Frank, Design Custom BICMOS Power
IC., Electronic DeSign, July 12,1990.
(6). Davis, Sam, Cell-Baaed ASICs Allow Usar-Deslgned
Intelligent Power Devices, PCIM, July 1990.
(7). Mansmann, Jeff; Shafer, Peter and Wildi, Eric, MaximizIng the Impact of Power ICs via a Tlme-ta-Market
CAD Driven Power ASIC Strategy, 1992 APEC
Proceedings, pp 23-27.
(8). Harris Applicetion Note AN9208.
11-197
Harris Semiconductor
-~=-- --===
-
--------~
--- -~---===
---
--===--------- - -=- =-No. AN9217.1
Harris Intelligent Power
Apri11994
HIGH CURRENT OFF LINE POWER SUPPLY
Author: Don laFontaine
Introduction
Overview
Design Engineers are constantly pushed to reduce the
space and cost of the power supply in their systems. For
supplies between 2W and 6W that can operate over the
world wide range of input voltage and frequency the options
were f1yback switching power supply or a high voltage linear
regulator. The typical transformer supply requires AC
voltage sensing and active tap switching, which is not
common practice.
When configured as a control chip for a power MOSFET,
the HV-2405E provides AC to DC conversion over the
world wide range of input voltage and frequency. The circuit
shown below delivers an output voltage of 5 volts DC to 24
volts DC with output current from OmA to 250mA. The output voltage can be extended to 35V for input voltages of
120VRMS and output currents up to 150mA (see section
titled "Output Voltage >24V").
The flyback switching power supply is the most efficient, but
is costly, complex and requires special EMI filters for suppression. The high voltage linear regulator is simple in
deSign, cheap, but not practical at this power level. The
transformer supply offers isolation and better efficiency but is
limited to a small range of input voltage and frequency, is
bulky, costly, and can be acoustically noisy.
The intent of this application note is to offer a cost effective
solution at the expense of efficiency. The Harris IRF830
MOSFET was selected because of its relative low cost, low
Ron and current handling capabilities. Improvements to the
circuit performance illustrated in this application note can
be made by selecting a larger MOSFET (I.e. Harris
IRF840).
An alternative solution is to configure the HV-2405E as a
control chip to drive a MOSFET. This solution is not as efficient as the switching or transformer supplies and does not
provide isolation, but is a low cost, compact (no transformer)
2W to 6W power supply accepting the world wide range of
input voltage and frequency.
This circuit provides protection for the MOSFET by monitoring both its voltage and current with a resistor network. This
network disables the HV-2405E, through its inhibit pin, when
a predetermined voltage or current is exceeded.
R2
R3
Features
• Low Cost Direct AC to DC Conversion
+
• Operates from 30VAC to 280VAC Line 50Hz/60Hz
• Output Current from OmA to 250mA
r--~---~~J
• Output Short Circuit Protection
8
• Adjustable DC Output Voltage 5VDC to 24VDCt
tOutput Voltages up to 35V Possible
Applications
• Fan Power Supply
• Subfractional Horsepower Motor Drives
• Power Supply for Simple IndustriaVCommerciaVConsumer
Equipment Controls
CAUTION: This product does not provide iso/don from AC nne.
HIGH CURRENT APPLICATION CIRCUIT
The optimum values of the resistors in the protection circuit
(R2, R3, R4) are dependent upon the input voltage and output current. Thirteen circuit solutions are presented along
Copyright C Harris Corporation 1992
11-198
Application Note 9217
R2
R3
COMPONENT LIST
tDETERMINED BY APPLICATION
... +
~--t-
DCVOUT
01
IRF830
R3
t
Q2
2N2222
R4
t
01
1N4007
RS
10Kn,1/4W
02
1N914
Cl
to.022I1F, SOV
Zl
t
C2
tl00I1F, SOV
Z2
1SV
OBl
OB1M Bridge
R1
1Kn,112W
Fl
t2A, 2SOVAC Fuse
R2
S10Kn,1/4W
FIGURE 1. HIGH CURRENT APPLICATION CIRCUIT
ro---------------..... -------------.. --..... -----------j
:
..
.
.
DA1
,,
:
·
,
:
:
·:
·:
···
···
····
····
·····
··
···
····
·
RA1:
:
HIGH
SAl
,
: INHIBIT
··
··
·····
··,
···
DA2
CAP
RAG
2
-------.. -.. ---..... ------.. ----- ...... --- .... ---.. -- ..... -----------------.. ----t
RBl
l1VDC
RB1S
···:
·
!:
:
:
··:
TO
30VDC
ZBl
RB2
·:
··:
··:
:
AC
•
:~ _______
RETURN.. _____________
SWITCHING
VOLTAGE
REGULATOR...... _....... __ .... ____ . . ____ .... ____ . . __ J:
......PRE-REGULATOR
_____________ .. _____ .. __ ..•~ .. ___ .. ___ ....... _UNEAR
............ ____
........ __________
FIGURE 2. HV-2405E SCHEMATIC
11-199
Application Note 9217
with the MOSFET Power Dissipation and Circuit Efficiency; 5
for the World Wide Supply 01'N .. 30VRMS to 280VRMS. Table
2), 5 for the 120VRMS Supply 01'N 30V RMS to 120VRMS,
Table 3) and 3 for the 35 Volt output Supply 0I1N 30VRMS to
120VRMSo Table4).
=
=
Circuit Description of the High Current
Circuit
Typical waveforms of the MOSFET are illustrated in Figures
3 and <4 with output currents of SOmA and 250mA respectively. From these waveforms it can be seen that the circuit
supplies large current spikes (SA to 11.5A) to the output
capacitor for a short period of time (1201J.S-3OO!Is). The current spikes are suppiied to the output capacitor while the
input voltage is only a little larger than the desired output
voltage. This technique makes the efficiency higher than for
an equivalent linear regulator.
Figure 1 shows the schematic of the High Current Circuit. To
understand the circuits operation first look at the operation of
the HV-2405E as a control Chip. The basic operation of the
HV-2405E can be broken down into two functional sections
(see Figure 2): (1) Switching Pre-Regulator and (2) Linear
Voltage Regulator.
I
I--
SAlis turned OFF when either of the following two conditions exist:
(1) Under Normal Operation. Feedback from the linear
voltage regulator results in current flowing out of SA2's
anode gate and through the zener diode stack (ZA1,
DA3, DA4, DAS) when the output capacitor reaches full
charge.
(2) Under Fault Conditions (i.e. 02 gated on because
power dissipation limit exceeded). Current flows out of
SA2's anode gate and through the 2N2222 (NOTE; Pin 4
is higher than pin 5 or pin 6).
Output voltage regulation is achieved when the output voltage at pin 5 exceeds the reference voltage. This causes
more current to flow through NB6, which in tum decreases
the drive to the output darling pair (NB7, NBS), causing an
increase in the already increasing voltage on pin 2, resulting
in turning ON SA2 and turning OFF SAl.
In this application the HV-2S05E only has to supply gate
drive to the power MOSFET. This enables the value of the
input series resistor R1 to be 1kn
11-200
I
I
r
H¥-2406E TURN-oN
I'
I I I
•
The Pre-Regulator takes energy from an incoming AC line to
bias-up the Linear Voltage Regulator. The Linear Voltage
Regulator performs two functions. The first is to supply a
reference voltage at pin 5 that is temperature independent
and the second is to supply an output voltage on pin 6 that is
adjustable from 5 volts to 24 volts. To obtain higher output
voltages see section titled ·Output Voltages >24 volts". The
output voltage is adjusted from 5V to 24V by placing a Zener
diode (Zl) between pin 5 and the output capacitor (C2). The
5V reference is generated by the band-gap circuitry ensuring
that pin 5 will sink lmA through 51<0 of resistance (RB10 +
RBll).
The Linear Voltage Regulator provides gate drive to an
external power MOSFET (01) that charge pumps the output
capacitor. Gate drive to 01 occurs when current flows into
pin S and out of pin 6. The SWitching Pre-Regulator turns off
when current is pulled out of pin 4 (anode gate of SA2).
When SA2 turns ON, SAl turns OFF and the gate drive to
01 stops until the next half cycle on AC high. The gate to
source Zener diode (Z2) ensures that the maximum VGS is
not exceeded.
I
•
I
•
VD8oo20VIDIV. _ /
~
~
),..
vG8 • IVIDIV.
\
:J
"""
/
!,tit'
~
"
"- "-
d'\.
looo5A/DIv.
11 • HV-2406E TURNS ON
12 • HV-2406ETURNS OFF
t1
12
100
V
FIGURE 3. TYPICAL WAVEFORMS OF THE MOSFET
(Iooy .. 50mA)
I
-
I
I
I
HV-24OSE TURN-ON
I I I -rVD8oo20VIDIIL --...
1/
.. .. ..
VG8ooIIVIDIV.
/
./
r
V
r-.... V
,.-. ~
1'(
)
~
'Doo5A1D1IL
11 • HV-2406E TURNS ON
12 • HV-2405ETURNS OFF
i
"7
"-
f
11
"
1OO,.aIDIV
12
FIGURE 4. TYPICAL WAVEFORMS OF THE MOSFET
(lour .. 250mA)
Application Note 9217
The resistance values of R2, R3 and R4 for the circuit solu-
MOSFETnGBT Protection Circuit
The circuitry shown in Figure 5 protects the MOSFET during
fault conditions by limiting its maximum power dissipation.
Under normal operating conditions the protection circuit is
off. Three 1/4 watt resistors (R2, R3, R4), a diode (02), and
a transistor (01) form the protection circuit. Resistors R2 and
R3 monitor the drain to source voltage and resistor R4 the
drain current. When a predetermined voltage/current combination is exceeded the MOSFET is turned off via the HV2405E's inhibit pin.
R2
R3
tions presented in this application note were determined
from the Vos and 10 values in Table 1. A maximum peak
power load line for the MOSFET is determined by doubling
both the 10 peak and Vos values and setting the voltage
drop across R3 (EO 1) and the Voltage drop across R4
(EO 2) equal to WBE' One Be across R3 or R4 limits the
MOSFErs power by turning on the 2N2222. A graphical
representation of this load line is presented in Figure 6.
The protection circuit will remain off for any combination of
Vos and 10 below the load line, including the maximum
power diSSipation from which the line was derived.
R4
R3
:---r-o+
Vbe
= R2+R3'
Vbe
= (2) . (R4) . (10)
(E01)
(2VOS (max»
(E02)
. VOUT
C2
20A
MAXIMUM PEAK POWER
FIGURES.
11:;:.25=A::...-_ _,
10A 4-.:..:
......
/
Determining R2, R3 and R4
Optimi28tion of the resistor values for minimizing 01 power
during fault conditions is dependent upon the input voltage
and output current. Table 1 (A, B) gives the peak drain current (1 0 ) and the peak drain to source voltage (V os) for the
Harris IRF830 in this application for 240V RMS and 120VRM Brespectively during normal operating conditions.
TABLE 1A. WORLD WIDE SUPPLY (VIN'" 30VRMS to 280VRMSl
Vos(PEAK)
IoANN (PEAK)
50mA
1SV
7.60A
100mA
20V
11.ooA
150mA
31V
11.ooA
200mA
37V
11.25A
2SOmA
44V
11.SOA
louT
37V
o
20Y
40Y
SOmA
Vos (pEAK)
IoANN (PEAK)
12.SV
6.ooA
Example:
Assume: lOUT
=200mA, V1N =264VRMS
From Table 1(A): Vos" 37V,lo = 11.25A
Figure 6 shows the maximum power load line for an output
current of 200mA with V 1N = 264V RMS '
To limit the maximum Vos voltage to <74V (twice that of
Table 1) select the values of R2 and R3 so that with 74V
across them, there is a 0.6V potential drop across R3.
15.0V
9.ooA
150mA
18.0V
9.3OA
200mA
24.0V
9.SOA
2SOmA
27.0V
10.00A
z
o
~w
Assume R2 = 510kn
-tJ)
(E03)
~15
~z
Q.
c(
R3 =
100mA
SOY
FIGURE 6.
_
R3
(74)
0.6 - 510k+R3
louT
SOV
Yos
(0.6) (51 Ok)
74-0.6
(E04)
R3= 4.16kn
To limit the maximum 10 current to <22.5A select the value of
R4 so that with 22.5A there is a 0.6V potential drop across
R4. (NOTE: Although we've designed the circuit for a maximum of 22.5A, theory predicts that Vos would equal 0 volts
11-201
Application Note 9217
decreasing its sensitivity at lower output currents. (NOTE;
R4's calculated resistance is closer to 0.020 at the higher
currents.) R3's value was increased to maintain the same
trip point.
and therefore no power dissipation. Once again the maximum power dissipation would be in the middle of our 10 and
Vos ranges.
0.6
= (22.5A) (R4)
:. R4
(EQ5)
= 0.0260
The combination of IIOltage drops across R3 and R4 determine the trigger point of the protection circuit. The recommended resistor values of R3 in Tables 2 and 3 are higher
than predicted by the above calculation at the lower output
currents. This is because the value of R4 was set to 0.020
Tables 2 and 3 giYe the recommended resistor values for
both the World Wide Supply and the 120VRMS supply. Also
presented in both tables are the circuits MOSFET Pd, Peak
drain current and circuit effICiency under normal operation as
well as the MOSFET Pd under short circuit conditions. The
peak power is several hundred watts but because the MOSFET is on for such a short period of time the average power
is only a few watts. Reference Figures 9-12 for aYerage
power dissipation of the MOSFET.
TABLE 2. WORLDWIDE SUPPLY (VIN" 3OV_ TO 280V_)
Input Frequency =60Hz, VOUT = 24V
Input Voltage = 240VRMS (NOTE: Reduce the value of R310r VIN > 264)
OUTPUT SHORTE~
NORMAL OPERATION
lour
R2
(0)
(0)
R4
(0)
MOSFETPd
(IRF830) *
PEAK
(mA)
loRAIN
CIRCUIT
EFFlCIENCVt
(mA)
MOSFETPd
(IRF830)
50
510k
7.5k
0.03
O.99W
7.6OA
60.5%
57.4
4.49W
100
510k
9.Ok
0.02
2.19W
11.00A
47.9%
153.0
8.93W
150
510k
7.Ok
0.02
3.51W
11.00A
40.1%
212.0
11.35W
200
510k
4.7k
0.02
5.46W
11.25A
38.6%
350.0
15.16W
250
510k
3.9k
0.02
7.15W
11.50A
34.2%
420.0
17.74W
R3
lac
TABLE 3. 120V_ SUPPLV (VIN .. 3OV_ TO 120V-J
Input Frequency = 60Hz, VOUT = 24V Input Voltage = 120VRMS
OUTPUT SHORTE~
NORMAL OPERATION
R2
(0)
(0)
R4
(0)
MOSFETPd
(IRF830)
PEAK
(mA)
IoR.uN
CIRCUIT
EFFlCIENCVt
(mA)
MOSFETPd
(lRF830)
50
51 Ok
6.Ok
0.06
0.85W
6.0A
66.5%
94
2.13W
100
510k
13.Ok
0.02
1.88W
9.DA
57.3%
155
5.28W
150
51 Ok
10.Ok
0.02
2.89W
9.3A
49.8%
245
8.47W
200
510k
6.8k
0.02
4.05W
9.5A
48.9%
422
14.13W
250
510k
5.ak
0.02
5.25W
10;OA
44.8%
530
17.83W
lOUT
R3
*
lac
• Reference Figures 9, 10, 11 and 12 lor complete MOSFET Power Dissipation lor 24V 60Hz, 24V 50Hz, 5V 50Hz and 5V 60Hz operation
VS. OUtput Current
t Reference Agures 13, 14, 15 and 16 for complete Circuit Efficiency lor 24V 60Hz, 24V 50Hz, 5V 50Hz and 5V 60Hz operation vs.lnput
Voltage.
:I: See Fold-Back Current Umlting Section to reduce power dissipation in MOSFET.
11-202
Application Note 9217
Fold-Back Current Umltlng
Fold-back current limiting is a well known method of reducing power dissipation and nuisance fuse blowing under short
circuit conditions. This can be realized by adding a fraction
of the output voltage to the base of 02 in the protection circuit. By connecting a resistor (AF) (Figure 6A) from the base
of 02 to ground, an output-sensing voltage divider consisting
of A4, A3, and AF produces a IIOltage that offsets the current
sense (IA4) and SOA voltage (IA2 + IA3) so that a higher
MOSFET current is required to turn on 02 at full output voltage than that required at zero output IIOltage (i.e. short circuit). Therefore, at short circuit, the maximum available
current is determined by the IIOltage divider A2, A3 (for Vos)
and the current sense resistor A4. Under normal output conditions, the available output current is increased by the magnitude of the offset voltage produced by the output sensing
voltage divider, and foldback is achieved.
....LQ1
R2
RX
R3
I
1
0-02
Your
R4
+
One way to compensate for the addition of RF is to place a
resistor Rx in parallel with A2. The value is chosen to provide a compensating current equal to the current through RF
Therefore:
From Table 1 the Vos for the output current desired allows
the value of the Ax compensating resistor to be calculated.
Thus, foldback is added without changing the MOSFET protection load line under normal output conditions. Under short
circuit conditions, the line will shift to the left in an amount
proportional to the current through RF
Determining R2, R3 and R4 for a Different MOSFET
The first step is to determine the worse case peak Vos and
peak 10 values for the power MOSFET in this application.
Worse case Vos and 10 values occur when the AC input voltage, input frequency, output current and output voltage are
all at their maximum values for the application (i.e. 264V RMS,
60Hz, 250mA and 24V).
CAUTION: Referenctl SBCtion lilled "Genlll'S/ Precautions' before making the
following "",aeuremanfll.
~
NOTE: A DC meter only provides the average voltage, not the peak
and therefore not suitable for the following measurements.
RF
Measurement of the peak Vos, as shown in Figures 3 and 4,
requires an oscilloscope with isolated inputs. This allows the
measurement to be taken directly across the MOSFET.
FlGURE6A.
A measure of the degree of foldback is a ratio of the output
current at short circuit to the maximum current available at
normal output voltage, and ideally would range between
zero and 1 (assuming that the I-V characteristics of the supply were perfectly square). This ratio is determined by the
magnitude of the offset IIOltage introduced at the base of 02.
A practical range would be between 0.5 and 0.8, depending
on the type of load. Too much foldback «0.5) will produce a
soft-start response into a large capaCitive load, or no-start
into an incandescent, or constant current load.
The addition of foldback into the 02 circuit requires a review
of the values of the Vos sense resistors A2, R3, and peak
current sense resistor A4. For example, the effect of adding
a value of RF to produce a foldback ratio of 0.8, will introduce
an offset voltage that will require a higher Vos to turn on 02.
At normal output IIOllage, this has the effect of moving the
load line (Figure 6) to lhe right, increasing the stress on the
MOSFET. To compensate, equations 1 and 2 must be modified to include the offset voltage in the calculation of the
resistors A2, A3 and A4. At short circuit the offset IIOltage
disappears, moving the load line back to the left (in the direction of less stress on the MOSFET).
Measurement of the peak II) also shown in Figures 3 and 4,
requires a non-contact current probe that measures the
drain current only (cathode side of 01 is a good connection
point).
The above measurements will allow the values of A2, R3
and R4 to be sized such that under normal operating conditions the protection circuit is off (see following section on verification of resistor values).
Determining the MOSFET power dissipation or circuit efficiency requires an oscilloscope with isolated inputs and a
waveform processing capabilities to calculate the area of the
complex waveforms. The analysis for this application note
used the Gould 2608 Digital Storage Oscilloscope.
Verification of Correct R2, R3 and R4 Values
It is important to verify that the protection circuit is off under
normal operating conditions.
Monitor the output voltage with an oscilloscope to ensure
that the peak voltage is not dropping when the output current
is greater than that required by the application. If the peak
voltage decreases before lOUT (max) is reached, then the
11-203
z
o
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(.)1-
-0
~z
Q.
ct
Application Note 9217
value of R4 is too large. Once again, a DC meter will only
give the average output voltage and will not give any indication that the peak output voltage is dropping.
Once the value of R4 is set, the value of R3 is verified by setting the output current to IOUT(max) and monitoring the output
voltage with a scope (assuming R2 is selected). While monitoring the peak output voltage change R3's resistance value
above that calculated. Select the next lower standard value
that doesn't cause the output peak voltage to drop.
Output Short Circuit Protection
Output short circuit protection is provided by sensing the output current through resistor R4. Under shorted output conditions Q2 is tumed on. This results in tuming off the HV240SE sooner in the cycle via the inhibit pin. Maximum
power dissipation in the MOSFET is during output short circuit conditions. This should be considered when choosing
the heat sink.
Wave Shaping for EMI
EMI can be a problem for switch mode power supplies due
to the fast tum off times of the switch. The faster the dildtthe
higher the harmonic content of the signal fed back into the
power line. By wave shaping the input current pulse through
the power MOSFET the size of the EMI filter can be reduced
and in some cases is not required at all. (See Figure 7A).
graphical representation of the input current pulse w/wo C1.
Empirical tests have shown that longer RC time constants
result in lower EMI noise at a cost of higher power dissipation in the MOSFET. The optimum RC time constant is a
function of the input line voltage and output current and
determined on an application by application basis. RS also
prevents charge pumping of the gate during transient noise
spikes.
Setting the Output Voltage
The circuit shown in Figure 1 provides a regulated SV to 24V
DC and is set by adjusting the value of Z1. The output
voltage of the HV-240SE (pin 6) is set by feedback from the
sense pin (pinS). The output will rise to the voltage
necessary to keep the sense pin at SV. The output voltage is
equal to the Zener voltage (Vz1) plus the SV on the sense
pin. For a SV output, the sense pin would be tied directly to
the output. The output peak voltage has the accuracy and
tolerance of both the Zener diode and the band-gap of the
HV-240SE. The maximum value for VZ1 is 20V due to
maximum output voltage rating of the HV-240SE. This circuit
regulates the peak output capacitor voltage. The minimum
output voltage is determined from the output capacitor size
and the load current.
Output Voltages >24V
The output voltage can be extended to 35V for input voltages of 120VRMS and output currents up to 1S0mA by placing another zener diode between pins 1 and 3 to GND, as
illustrated in Figure 8.
CHARGING CURRENT
WAVEFORMS
WITHOUT
R2
R3
;
G~.---4-,,
,,,
,,
:'---+-0+
:i ...A.
VOUT
+
HV-2045E TURNS OFF
(8)
(A)
FIGURE 7.
Capacitor C1 is used to slowly turn off the power MOSFET
once the HV-240SE has turned off. This is illustrated in Figures 3 and 4, notice that the Vos voltage starts ramping
down after t2• The rate of this turn off is a function of the RC
time constant between RS and C1. Figure 7B shows a
11-204
FIGURE 8. OUTPUT VOLTAGE UP TO 35V
Application Note 9217
Table 4A gives the recommended resistor values lor output
voltages up to 35V. Table 4B gives the MOSFET Pd, Peak
drain current and circuits effICiency under normal operation
as well as the MOSFET Pd under short circuit conditions lor
output voltages 01 24V, 30V and 35V.
TABLE 4A. 35 VOLT OUTPUT SUPPLY (VIN =30V_ TO 120VRMSl
RESISTOR VALUES FOR INCREASED OUTPUT VOLTAGE UP TO 35V
lour
R2(n)
R3(n)
R4(n)
50mA
510k
6.Ok
0.06
100mA
510k
9.Ok
0.02
150mA
510k
7.5k
0.02
TABLE 4B. 35 VOLT OUTPUT SUPPLY(VIN. 3OV_ TO 120VRMSl
Input Frequency = 60Hz, Input Voltage = 120VRMS
OUTPUT SHORTE~
NORMAL OPERATION
VOUT = 24V
Z3=OV
Z, =20V
VOUT = 30V
Z,=6.8V
Z, =20V
VQUT=35V
Z, = 12V
Z, =20V
IoA.uN
CIRCUIT
EFFICIENCY
lac
VOUTM
MOSFETPd
(IRF830)
PEAK
lour (rnA)
(rnA)
MOSFETPd
(IRF830)
50
24.09
0.63W
6.5A
56.8%
84.9
1.26W
100
23.76
1.35W
9.0A
56.7%
222.0
4.OSW
150
23.45
2.44W
10.0A
50.0%
300.0
6.19W
50
30.65
0.71W
6.5A
59.6%
117.0
1.44W
100
30.33
1.5OW
9.0A
59.4%
235.0
4.27W
150
30.02
2.59W
10.OA
59.3%
308.0
6.27W
50
35.79
0.69W
6.5A
65.9%
680.0
11.47W
100
35.48
1.44W
9.0A
65.0%
600.0
14.62W
150
35.17
2.44W
10.0A
65.3%
640.0
17.3OW
:I: See Fold-Back Current Umiting Section to reduce power dissipation In MOSFET.
z
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<
11-205
Application Note 9217
Component List
Z2 Gate to Source Voltage Clamp
(tDetermlned by Application)
Z2 protects the Power Transistor's gate to source from being
overstressed.
Fuse
Opens the connection to the power line should the system
fail.
Value: = t. 2AG
Value
=1S\I, 1I2W
Z3 Output Voltage AdJust> 24V (See Figure 8)
Z3 is used to set the output voltage above 24V.
Bridge Rectifier
Value
OB1M or 4 diodes similar to 1N4007. Reduces power dissipation in the MOSFET by reducing the peak current for a
given output load.
=t. <12V.
Cl Input Current Wave Shaping Capacitor
C1 Is used to provide an RC time constant to wave shape
the input current.
Rl Source Resistor
C2 Output Storage Capacitor
R1 limns the input current into the HV-2405E.
C2 is charged twice each line cycle by the Power Transistor.
Value =t. 1()()Oj.lF.
Value: =1kn
01 Blocking Diode
General Precautions
01 prewnts current flow back into the input of the HV-240SE
through the MOSFET. This helps to reduce the iotal power in
the MOSFET.
Instrumentation Effects:
02 Blocking Diode
02 prevents overstress of the 2N2222 base collector junction. Without it current would flow through the HV-240SE
when SA2 turns on. which owr time could degrade the performance of the 2N2222.
01 Power Transistor
01 must have sufficient heat sink to dissipate the power.
Reference Figures 7 through 10 for MOSFET (IRF830)
power dissipation vs. input voltage and output current.
Recommendation = IRF830 or equivalent.
Background: Input to output parasitic exist in most test
equipment power supplies. The inter-winding capacitance of
the transformer may result in substantial current flow (rnA)
from the equipment ground wire to the AC and DC ground of
the HV-2405E. This current can induce instability in the
inhibit circuit of the HV-2405E resulting in erratic operation.
Recommendations for Evaluation of the HV·2405E In the
Lab:
a) The use of battery powered DVM's and scopes will eliminate ground loops.
b) When connecting test equipment. locate grounds as
close to pin 1 as possible.
c) Current measurements on the AC side of the HV-2405E
(Pin 8. 1 and 2) should be made with a non-contact current probe.
02 MOSFETIIGBT Power Umltlng Transistor
02 is a Bipolar Transistor that turns off the HV-240SE when
a predetermined 10 or VOS limit is exceeded.
Recommended transistor =2N2222 or equivalent.
R2,R3,R4 Power limiting Resistors
R2. R3. R4 set the maximum Power dissipation in the MOSFETIIGBT.
Values =t. 1/4W
If AC powered test equipment is used. then the use of an
isolated plug is recommended. The isolated plug eliminates
any voltage difference between earth ground and AC
ground. However. even though the earth ground is disconnected. ground loop currents can still flow through trans·
former of the test equipment. Ground loops can be
minimized by connecting the test equipment ground probe
as close to pin 1 as possible.
CAI/T/ON: /JengefDus voIta(I8B may tlppBlJr on 8KpOSed metal surlsces of
AC powered Ie/J/ equipment
R5 Input Current Wave Shaping Resistor
RS is used to provide an RC time constant to wave shape
the input current. RS also removes charge off the gate during
initial start-up.
AC Source Effeeta:
ZI Output Voltage Adjust
Background: Laboratory AC sources (such as VARIACs.
step-up transformers etc.) contain large inductances that
can generate damaging high voltage transients any time
they are switched on or off. Switch arcing can further aggravate the effects of source inductance.
Z1 is used to set the output voltage above the S volt reference on pin S (see section titled "setting the output voltage"
for more information).
Recommendation: Adequate protection means (such as
MOV. avalanche diode. surgector. etc.) may be needed to
clamp transients to within the ±500V Input limit of the HV2405E.
Value
Value
=10kn
=t. 112W
Preset VARIAC output voltage before applying power to part.
11-206
Application Note 9217
IRF830 MOSFET Power Dissipation vs Input Voltage and Output Current
•
~
I
~ I--
~ 5
i
,.
4
".. I--"'"
.,.,
~
...
:: -""
3! 3
l
•
I I....r-.
7
2
~
- ..... -
-~.
~
1ouT-1SO~
o
20
~
10
100
140
~I
E5
8:Ii
220
~
4
2
::
o
210
~
""
:.. ..... l"..-" t-'
l!E 3
louT-SOmA
180
20
-
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8
Iii
5
.,. .,.,
:: I-' ""
II.
~
/
4
~
-
3! 3
"...
2
~
I--"'"
I--
-
10-
T
20
10
1ouT-1&OmA
r
~..",..
I
I I I
10
100
140
180
220
•
l~-
-
t-1ouT - 200mA
1ouT-1~-f
210
L.-
IU
~
I
;
4
E5
......
----
.....-:: I"..-
2
~ I--
-.,.,-
i""""
I I
~ f-"T
1ouT-250mA
T .J-.I....... ~ i""""11ouT~2OO~
1ouT~1SO~
~1ouT·100mA
io""""
louT-SOmA
100
140
110
220
INPUT VOlTAGE (rna) AT 80Hz
,.""
, .,.,
3! 3
f'-.1ouT_100mA
r'-
o
1I1ouT dOOmA
i· ...&..--+-
VIouT _100.:A
7
k ~.~~
ioC'
...... ......
FIGURE 10. MOSFET POWER DISSIPATION SV
I ..J.-..-r
~ i-""'"
""
"..
INPUT VOlTAGE (....) AT 50Hz
FIGURE 9. MOSFET POWER DISSIPATION SV
•
~
I/~·~
INPUT VOlTAGE (....) AT 50Hz
7
~I
1ouT-25OmA
l
louT _100.,J -
~
-
1ouT-2OOmA
I I..J...
7
o
20
210
10
!'-1ouT - IOmA
100
140
110
220
210
INPUT VOlTAGE (rna) AT 50Hz
FIGURE 11. MOSFET POWER DISSIPATION 24V
FIGURE 12. MOSFET POWER DISSIPATION 24V
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0-
--
~
-.....,.,tv-+.....,.,tv-.....POLYR~..
~C
AI)
1""
lr
POSIllVE
:
PROTECTION
i
NEGA11VE
'PROTECTION
!
,,_ '
~-u:
"':"
INPUT
:
Rs!,
:
:J
SIGNAL
INPUT {
,,
-
~--.--- .
'
,
,,,
,,,
,,
,,
,
,
.
}fSs i ,,
: ACllVE
: CIRCUIT
,
Rs
:
:
:
,
,,,
,,,
-. -. --- . -...-. ~ ,_._----_.
FIGURE 3. ESD AND TRANSIENT PROTECTION CIRCUIT
~ ..
" - - < l -..... s
FIGURE2. ESDANDTRANSIENT PROTECTION EFFECTIVELY
USED IN MOS AND CMOS DEVICES
Oue to greater emphasis on Reliability under harsh application conditions, more ruggedized protection structure have
been developed. A variety of circuit configurations have
been evaluated and applied to use in production circuits. A
limited introduction to this work was published in various
papers by L. Avery (See Bibliography). To provide the best
protection possible within economic constraints, it was
determined that SCR latching structures could provide very
fast turn-ON, a low forward on resistance and a reliable
threshold of switching. Both positive and negative protection
structures were readily adapted to bipolar technology. Other
defining aspects of the protection network included the
capability to be self-protecting to a much higher level than
the signal input line being protected. Ideally, when a
protection circuit is not otherwise needed, it should have no
significant loading effect on the operating circuit. As such, it
should have very little shunt capacitance and require
minimal series resistance to be added to the signal line of
the active circuit. Also, where minimal capacitance loading is
essential for a fast turn-ON speed, the need for a simpler
structure is indicated.
Figure 4 shows the diagram of a positive and negative cell
protection circuit as it applies to the SP720. The PNP and
NPN transistor pairs are used as the equivalent seA
structures. Protection in this structure allows forward turnON to go marginally above the +V supply to turn-ON the
high-side seR or marginally below the -V supply to turn-ON
the low-side seA. The signal line to the active device is
protected in both directions and does not add series impedance to the signal input line. A shunt resistance is used to
forward bias· the PNP device for turn-ON but is not directly
connected to the signal line. As an on-chip protection cell,
this structure may be next to the input pad of the active
circuit; which is the best location for a protection device.
However, for many applications, the technology of the active
chip may not be compatible to structures of the type
indicated in Figure 4. This is particularly true in the high
speed CMOS where the substrates are commonly N type
and connected to the positive supply of the chip. The protection cell structure shown in Figure 4 is not required to be on
the active chip because it does not sense series input
current to the active device. The sense mechanism is
voltage threshold referenced to the V+ and V- bias voltages.
The cell structure of the seR pair of Figure 4 are shown in
the layout sketch and profile cutouts of Figure 5. It should be
noted that the layout and profiles shown here are equivalent
structures intended for tutorial information. The structures
are shown on opposite sides of the 'IN" chip bonding pad, as
is the case for the SP720. As needed for a preferred layout,
the structures are adjacent to the pad and as close to the
11-222
Application Note 9304
--_.,...,
- 1 -......---+v
positive and negative supply lines as possible. The common
and best choice for effective layout is to provide a ground
ring (V-) around the chip and to layout with minimum distance paths to the positive supply (V+). In the SP720 the Vline is common to the substrate and frame ground of the IC.
The equivalent circuit diagram of the SP720 is shown in
Figure 6. Each switch element is an equivalent SCR
structure where 14 positive and negative pairs as. shown in
Figure 4 are provided on a single chip. Each positive switching structure has a threshold reference to the V+ terminal,
plus one VBE (based-to-emitter voltage equal to one diode
: . - - EQUIVALENT
:
SCR CIRCUIT
:,
SIGNAL
;----------~
L _____ ~ ~
INPUT---.....-
.........:
,
ACllVE
:
CIRCUIT
,
:
~----------!
-----40--v
FIGURE 4. PROTECTION CELLS OF THE SP720 SCR ARRAY
METAL CONTACT
~
~
~N+)
v+
B
FIGURE SA.
B'
A
A'
HIGH AND LOW CELL PAIR LAYOUT; SHOWN WITHOUT PROTECT, METAL AND FIELD
OXIDE LEVELS (NOT TO SCALE)
Z
o
-tJ)
!;iw
S:!b
KZ
D..
-0.4
IU
II:
Given an ESO discharge of -15KV, neglecting inductive
effects and distributed capacitance, the peak current at time
t = 0 will be -lOA. And, with the SP720 latched on as shown
in Equation (3), the lOA peak current will result in an ESO
pulse at the input of the SP720 of -11V. For the HCU04 to
withstand this surge of voltage, it is required that the dropping resistor, RI attenuate the peak VOltage, Ves at the
HCU04 input to within acceptable ratings.
II:
The negative reverse current path is through RI, Rp and O2 ;
where Rp and O2 are part of the HCU04. For a negative ESO
discharge voltage, V 0 from capacitor Co. the equation for the
peak voltage, Ves at the input to the HCU04 is derived as follows:
FIGURE 14. MEASURED REVERSE CURRENT V8 VOLTAGE
CHARACTERISTIC OF THE SP7201HCU04 FOR
THE FIGURE 10 CIRCUIT PROTECTION MODE
Substituting Equation (5) into Equation (3), we have
(6)
Vs - (VoIRo)oRs- 1.1
and from equation (2) and (4a) , a general solution for the
Ves voltage is
(7)
Ves = [(Vs - VFWD2)1(RI + Rp)]oRp + VFW02
For a Simpler approach, one can work backwards to arrive at
the correct solution. The reverse CMOS voltage vs current
curve of Figure 11 indicates that a peak voltage, Ves of -3V
will produce a negative current of approximately -20mA
which is the rated absolute maximum limit. For a -15KV ESO
discharge and from Equation (6), the peak voltage, Vs is
Vs= (VoIRo)·Rs -1.1 = (-15/1500)-1.1 =-11.1V
The peak current, les from equation (4a) is
les = [(Vs - VFW02)/(RI + Rp))
=[(-11.1 -(-0.7))Y(RI + 1200)
~
-0.3
4
til
-0.2
-2
-0.1
§
%
-1
o~--~~~~
__
~
__
~
____L_J
o
-0.4
-0.8
-1.2
-1.8
-2.0
REVERSE VOLTAGE (Val TO THE SP7201HCU04INPUT M
Figure 14 shows the distribution of currents for the circuit of
Figure 10 given a specifIC value of RI. Curves are shown for
both Is (HCU04 + SP720) and Isp (SP720) versus a negative
input voltage, V s. The resistor, RI value of 100 is used here
primarily to sense the current flow into the HCU04. (This
data was taken with the unused inputs to the HCU04 connected to ground and the unused inputs to the SP720 biased
to Vcd2 on a resistive divider.) The Figure 14 curves verify
the model condition of Figure 13A with the exception that
resistive heating at higher currents increases the resistance
in the latched on SCA. This curve explains the ESO protection of the Harris High Speed Logic "HC· family and, in particular, demonstrates the value of the Rp internal resistor as
protection for the HCU04 gate input. Added series resistance external to a signal input is always recommended for
maximum ESO protection.
Range of Capability
While the SP720 has substantially greater ESO self protection
capability then small signal or logics circuits such as the
HCU04, It should be understood that it is not intended for
11-228
Application Note 9304
interlace protection beyond the limits implied in the data sheet
or the application note. The Mil-Std-883, Method 3015.7 condition noted here defines a human body model of l00pF and
15000 where the capacitor is charged to a specified level and
discharged through the series resistor into the circuit being
tested. The capability of the SP720 under this condition has
been noted as ±15KV. And, for a machine model where no
resistance is specified, a 200pF capacitor is discharged into
the input under test. For the machine model the level of capability is ±1 KV; again demonstrating that the series resistor
used in the test or as part of the application circuit has pr0nounced effect for improving the level of ESO protection.
While a series resistor at the input to a signal device can
greatly extend the level of ESO protection, a circuit application, for speed or other restrictions, may not be tolerant to
added series resistance. HOW6ll9r, even a few ohms of resistance can substantially improve ESO protection levels. Where
an ESO sensitive signal device to be protected has no internal
input series resistance and interlaces to a potentially damaging environment, added resistance between the SP720 and
the device is essential for added ESO protection. Circuits
often contain substrate or pocket diodes at the input to GNO
or Vee. and will shunt very high peak currents during an ESO
discharge. For example, if the HCU04 of Figure 14 is replaced
with device having a protection diode to ground and no series
resistor, the anticipated increase in input current is 10 times.
Shunt capacitance is sometimes added to a signal input for
added ESO protection but, for practical values of capacitance,
is much less effective in suppressing tranSients. For most
applications, added series resistance can substantially
improve ESO transient protection with less signal degradation.
A further concern for devices to be protected is forward or
reverse conduction thresholds within the power supply range
(not uncommon in analog circuits). Depending on the cost
considerations, the power supply V+ and V- levels for the
SP720 could be adjusted to match specific requirements.
This may not be practical unless the levels are also common
to an existing power supply. The solution of this problem
goes beyond added series resistance for improved protection. Each case must be treated with respect to the precise
V-I input characteristics of the device to be protected.
Interface and Power Supply Switching
Where separate system components with different power
supplies are used for the source signal output and the
receiving signal input, additional interlace protection circuitry
maybe needed. The SP720 would normally have the same
power supply levels as the receiving (input) device it is
intended to protect. When the SP720 with its receiving interface circuit is powered off, a remote source signal may be
activated from a separate supply (i.e., remote bus connected
systems). The user should be aware that the SP720 remains
active when powered down and may conduct current from
the IN input to the V+ (or V-) supply.
Within its own structure, any IN input of the SP720 will forward conduct to V+ when the input voltage increases to a
level greater than a Vee threshold above the V+ supply. Similarly, the SP720 will reverse conduct to V- when the input
voltage decreases to a level less than a VBe threshold below
the V- supply. Either condition will exist as the V+ or V- level
changes and will continue to exist as the V+ collapses to
ground (or V-) when the SP720 supply is switched off. If a
transient or power surge is provided from the source input to
the IN terminal of the SP720, after the V+ has been switched
off, forward current will be conducted to the V+Nee power
supply line. Without a power supply to clamp or limit the rising voltage, a power surge on the input line may damage
other signal devices common to the Vee power supply.
Bypassing the Vee line may not be adequate to protect for
large energy surges. The best choice for protection against
this type of damage is to add a zener diode clamp to the Vee
line. The zener voltage level should be greater than Vee but
within the absolute maximum ratings of ail devices powered
from the Vee supply line.
Power Supply Off Protection, RIse/Fail Speed
To illustrate the active switching of the SP720 and the speed
of the SCR for both tum on and tum off, oscilloscope traces
were taken for the circuit conditions of Figure 15. A pulse input
signal is applied with NO supply voltage applied to the SP720.
Figure 15 shows the positive and negative pulse conditions to
V+ and V- respectively. The trace scales for Figure 15 are
IOnsldivision horizontal and 1VIdivision vertical. Input and
output pulses are shown on each trace with the smaller pulse
being the output. The smaller output trace is due to an offset
resulting from the voltage dropped across the SCR in forward
conduction. The OUT+ and OUT- pulses quickly respond to
the rising edge of the input pulse, following within -2ns delay
from the start of the IN pulse and tracking the input signal. The
output falls with approximately the same delay.
Bibliography
1. L.R. AVfKY, ·Electrostatlc Discharge: Mechanisms, Protection
Techniques, and Effects on Integrated Circuit Reliability", RCA
Review, Vol. 45, No.2, June 1984, Pg. 291 - 302.
2. L.R. Avery, "Using SCR's as Transient Protection Structuras In
Integrated Circuits; EOSIESD Symp. Proc., 1983, Pg. 90 - 96.
3. MIL-STQ.883D, 15 Nov 91, Electrostatic DIscharge Sensitivity
Classification, Method 3015.7, 22 Mar 89.
4. Machine Model Standard (RD = 00), EIAJ IC121.
5. EOSIESO-DS5.2, Proposed Standard, ·EOSIESD Association
Standard for the DIscharge (ESD) SensItIvity Testing - Machine
Model (MM) - Component Level, Oct 92.
6. Harris Semiconductor, SP720, File No. 2791.5, Electronic Protection Array for ESD and Overvoltage Protection. (16 Lead
Plastic IC available In DIP and SOIC packages).
7. Harris Semiconductor, SP721 , Ale No. 3590, Electronic Protection Array for ESD and Ovarvoltage Protection (6 Lead Plastic IC
In the SP720 family avaQabIe In DIP and SOIC packages).
11-229
Application Note 9304
PO~TIV~ORWARDCONDUcnoN
HIGH SPEED ONIOFF PULSE (OUT+)
IN
(OUT+)
OUT+
FORWARD SCR CELL
PROTEcnON CIRCUIT
±VGEN (SOO)
---+.....~---'
REVERSE SCR CELL
PROTEcnON CIRCUIT
OUT-
GND
NEGATlVEIREVERSE CONDUCTION
HIGH SPEED ONIOFF PULSE (OUT·)
(OUT·)
IN
FIGURE 15. SP720 CIRCUIT WITH NO POWER SUPPLY INPUT PULSE TEST WITH SOo, (OV TO ±5V) INPUT. THE TRACE SCALES
FOR OUT+ AND OUT· ARE 1VIDIV VERTICAL AND 10ntIDIV HORIZONTAL
11·230
Harris Semiconductor
----====
-==
-- -- - - - - - -.= -==
===:
-=--===
- ----===----
------
No. AN9323.1
-- -
---
------
-
Harris Intelligent Power
Apri11994
HIP5061 HIGH EFFICIENCY, HIGH PERFORMANCE,
HIGH POWER CONVERTER
Authors: Charles Hawkes, Tom Jochum and Hal Wittlinger
Introduction
As the complexity of sophisticated, modern day equipment
grows, the need for high efficiency, high performance and
high power converters continues to expand_ Demand for
smaller, lighter, more efficient supplies for this equipment is
addressed by the HIP5061. The HIPS061 contains a SOV, SA
(7A minimum at <30% duty cycle, SA at DC) DMOS power
transistor with an rOS(ON) of approximately 0.180. This low
rOS(ON) of the switching device permits high rms currents
without excessive device dissipation. The IC is housed in a 7
lead, T0220 style package. By including a DMOS power
transistor with its associated driver and the current-mode
PWM control circuitry within a single package, simplification
and improved performance of many power supply systems
can be achieved. This note explains the operation and
proper application of the HIP5061 so that this high performance device can be utilized. A SOW, 28V boost converter
will be presented to demonstrate a typical application of the
IC. Supplies using an external high voltage, power MOSFET
transistor in a cascode configuration with the internal DMOS
transistor can have higher power outputs, many in excess of
200W.
Operation In a Typical Application ClrcuH
Figure 1 shows a Simplified Block Diagram of the HIP5061
in a typical Boost converter. A resistor connected from the
VIN supply to the Voo terminal of the IC powers the internal
14V shunt regulator. The Gate Driver supply is decoupled
from the main supply by a small external resistor connected
between Voo and the VG terminal. A bypass capaCitor is
connected between the Voo terminal and ground to reduce
coupling between analog and digital circuitry. A Schottky
diode insures efficient energy transfer from the DMOS drain
circuit inductor to the load. To set the output voltage, two
resistors are used to scale the output supply voltage down to
the S.1 V internal reference.
The heart of the IC is the high current DMOS power
transistor with its associated gate driver and high-speed
peak current control loop. A portion of the converter's DC
output is applied to a transconductance error amplifier that
compares the fed back signal with the internal S.W
reference. The output of this amplifier is brought out at the
Vc terminal to provide for soft start and frequency
z
o
-In
~w
~b
;rz
a..
c(
FIGURE 1. SIMPUFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION
Copyrlght@Harria Corporation 1994
11-231
Application Note 9323
INTERNAL LEAD . INDUCTANCE
AND RESISTANCE--..
.IV
:VAEF
HIP5061
FIGURE 2. FUNCIONAL BLOCK DIAGRAM OF THE HIP5061
compensation of the control loop. This same signal is also
applied internally to program the peak DMOS transistor drain
current. To assure precise current control, the response time
of this peak current control loop is less than 5Ons.
A 2MHz internal clock provides all the timing signals for the
converter operating at 250kHz. A slope compensation circuit
is also incorporated within the converter IC to eliminate subharmonic oscillation that occurs in continuous-current mode
converters operating with duty cycles greater than 5004.
tNP5061 Description of Operation
Figure 2 shows a more detailed Functional Block Diagram of
the HIP5061. An internal14V shunt regulator in conjunction
with an external series resistor provides internal operating
voltage to the IC in applications where no 12V auxiliary
supply is available. Note that in applicationS where the input
voltage at Voo is 12V. ±10%. the regulator is not used. This
regulator is shown as a zener diode on the diagrams of
Figure 1 and Figure 2.
The 2M Hz clock is processed in the Control Logic block to
provide various timing signals. A cycle of operation begins
when a 100ns pulse (which occurs at a 4~ interval) triggers
the latch that initiates the DMOS transistor on-time. This
pulse also provides a blanking interval in the Current Monitoring block to eliminate false turn-offs caused by high transient pulse currents that occur during turn-on. The output of
the Current Ramp block is summed with the sensed DMOS
transistor current (to provide slope compensation) before
being compared with the Error Current signal. The current
ramp. -0.45A1j.1s, is inhibited for the first 1.~ (37.5%) of the
duty cycle by the Ramp Enable signal, since ramp is not
needed for slope compensation during this interval. Inhibit·
ing of the compensating ramp has the effect of reducing the
peak short-circuit current.
The output of the power supply is divided down and monitored at the FB terminal. A transconductance error amplifier
compares the de level of the fed back voltage with an internal bandgap reference. while providing voltage loop compensation by means of external resistors and capaCitors.
The Error Amplifl8r output (the error voltage) is then converted into a current (the Error Current) that is used to program the required peak DMOS transistor curr.ent that
produces the desired output voltage. When the sum of the
sensed DMOS transistor current and the compensating Current Ramp exceed the Error Current signal, the latch is reset
and the DMOS transistor is turned off. Current comparison
around this loop takes place in less than SOns. allowing for
excellent 250kHz converter operation. The latch can also be
reset by an under-voltage (Voo < 10.3V typical). over-temperature (TJ > +125"C typical) or a shutdown signal externally applied at the Vc terminal. see Figure 5.
Note that if the error voltage (at the Vc pin) is less that 2.55V,
then the output of the Voltage-to-Current Converter will be
held at zero. This condition will produce the minimum possible pulse Width, typically 150ns (100ns blanking pulse plus
50ns delay). Error voltages lower than this 2.55V level will
not produce shorter pulse widths. Under very light loads
(when Vc goes below 1.5V). the Enable Comparator will
temporarily hold-off the PWM latch (and the DMOS transistor) until the Vc voltage rises above 1.5V. This low Vc inhibit
circuit results in a burst-mode of operation that maintains
regulation under light or no loads.
11-232
Application Note 9323
During an over-current condition, the output of the Error
Amplifier will attempt to exceed the 7.0V threshold. At this
point, the Short-Circuit Comparator will pull down on this
signal and induce a Iow-lewl oscillation about the threshold,
serving to clamp the peak error voltage. This clamping
action, in turn, will limit the peak current in the DMOS
transistor, reducing the duty ratio of the switch as the
demand for current continues to increase. This action, in
conjunction with the Thermal Monitor, serves to protect the
IC from over-current (short-circuit) conditions.
high input voltages, limited only by power dissipation in the
external resistor. When only higher voltages are available, a
bootstrap or other 12V auxiliary supply can be used to
eliminate this dissipation. The series resistor should be
chosen to be as large as possible to reduce power
dissipation at high line, while ensuring adequate Voo YOltage
at low line. The maximum value for this resistor, R, is given
by:
Using the Transconductance Error Amplifier
A transconductance amplifier with a typical gm of 30mS is
used as the input gain stage where the power supply output
voltage is compared with the internally generated S.W
reference voltage. A PNP transistor input structure allows
this amplifier to accommodate large negative going transient
voltages without causing amplifier phase reversal, often
associated with PNP input structures. Negative transients up
to SV applied to the input through at least S.1 K will not result
in phase reversal. The amplifier output stage has the
customary drain to drain output to help improve the output
impedance, ideally infinity. The amplifier gain is typically
SOdB and is not significantly aitered when operating into the
stages that follow within the IC. To minimize the output stage
idling current, while providing high peak currents to insure
rapid response to load and input transients, a class B type of
output stage was used in the amplifier. Placing a 100k
resistor from the amplifier output terminal, Vo to ground will
bias the output stage to an active state and still minimize
power consumption. In all cases, the reSistor shunting the
transconductance amplifier output must be greater than
10kn to insure that the output will rise sufficiently high to
obtain the maximum DMOS transistor drain current.
Start-Up Sequence
Upon initial power up of the HIP5061 in a typical application
circuit, the voltage at Vc will be zero, and the DMOS
transistor will be off. When the YOltage at Voo rises above
the 10.3V typical threshold, the error amplifier output is
enabled and the Vc YOltage begins to rise in response to the
low voltage at the FB terminal. When the Vc voltage rises
above 1.SV the DMOS transistor begins to switch at the
minimum duty cycle, and when it rises above 2.SSV the duty
cycle begins to increase. The Vc voltage (and peak DMOS
transistor current) will then continue to rise until the YOltage
loop gains control and establishes regulation. Note that the
rate of rise in the Vc voltage can be controlled by an external
soft start circuit (See Soft Start Implementation).
If the Vc voltage is unrestricted in its rate of rise, then it will
typically rise quickly to its maximum (peak current) value,
causing the DMOS transistor to turn-on and stay on until it
reaches the peak current value. At this point, the DMOS
transistor begins switching, and the Vc voltage (and peak
DMOS transistor current) will drop down to the level
commanded by the voltage loop.
Using the Shunt Regulator
The internal 14V shunt regulator in conjunction with an
external series resistor allows the IC to operate from quite
Where V, is the input YOltage to the power supply. The value
chosen for this resistor must also result in a current, I, into
the Voo clamp that is less than 10SmA when the input
voltage is at its maximum:
(VI, MAX -13.3)
R MAX
Inductor Selection
The selection of the energy storage inductor(s) t..- for a
DC to DC converter has tremendous influence on the
behavior of the converter. It is particularly important in light of
the high level of integration (and necessarily few degrees of
freedom) achieved in the HIPS061. There are several factors
influencing the selection of this inductor. First, the
inductance of LSTOR will determine the basic mode of
operation for the converter: continuous or discontinuous
current. In order to maximize the output power for the given
maximum controllable DMOS transistor current, a converter
may be designed to operate in continuous current mode
(CCM). However, this tends to require a larger inductor, and
for many converter topologies results in a feedback loop that
is diffICult to stabilize. For these and other reasons, the
inductor LSTOR may be chosen so as to operate the
converter in discontinuous current mode (DCM). The relative
merits of CCM and DCM operation for various topologies
and the corresponding selection of LSTOR is well
documented and will not be covered here.
A second factor influencing the selection of LSTOR is the
stability requirement for current-mode control. This
constraint is only applicable for converters operating in
CCM, since open-loop instabilities of this type are not
observed in converters operating in DCM. For marginal stability, the compensating ramp (internal to the HIPS061) must
have a slope that is greater than one-half the difference
between the inductor current's down slope and up slope. (To
ensure stability for duty ratios D > 0.8, the slope of the compensating ramp should be equal to the inductor current
downslope.) A generally accepted goal is to set the slope of
the compensating ramp to be at least one-half of the inductor
current down slope. Since there is no external control over
the internal compensating ramp, one must be sure that the
inductor is large enough so that the down slope of the
inductor current is not too large. Table 1 summarizes this
requirement for minimum inductance for several common
topologieS.
11-233
Application Nots 9323
TABLE 1. MINIMUM INDUCTANCE FOR STABLE CCM
OPERATION ABOVE 50% DUTY CYCLE
CONVERTER TYPE
the DMOS transistor can result in large transient voltages
being induced across any parasitic inductance in the drain
path. For this reason, It is important that such parasitic
inductance be reduced by good, high frequency layout
practiceS. Nevertheless, there are many instances (e.g.,
transformer isolated topologies) in which voltages in excess
of SOV may be developed at the OMOS transistor drain. In
some cases, a simple R-C snubber may be added to reduce
the overshoot of the drain voltage to a safe level.
MINIMUM INDUCTANCE
Boost
L,~
Vo+Vo
It is also possible that the large amount of ringing that can
occur at the OMOS transistor drain at turn-off will induce
noise in the IC. This noise may result in false triggering of
the PWM latch, particularly at high peak OMOS transistor
drain currents. Noise related instability can also be
eliminated by the addition of a snubber, which will rapidly
damp out such turn-off ringing. Good layout practiceS will
reduce the need for such protective measures, and ensure
that the OMOS transistor is not overstressed.
-->--L,
+ L2
L,~
2MR, MIN
Vo-Vo
-->--L,
+ L2
2MR, MIN
Under-Voltage Lockout
Ryback
Forward
1
Assumes that L1 and L2 are both In CCM.
NOTE:
L = Inductance In Henrys, Vo = Output Voltage,
Vo = Diode Voltage Drop, V, = Input Voltage,
M..- = (AIIAtl_ = O.45A111S
L, = Drain Inductor, Lo = Secondary Inductor,
Np = Primary Turns, N. = Secondary Turns
A third constraint on the size of the inductor is one that is
common among current-mode controlled PWM converters,
and applies to both OCM and CCM operation; The stable
generation of the desired OMOS transistor pulse width
depends on the accurate comparison of the error signal and
the peak LSTOR (OMOS) transistor drain current. Thus, as
the peak LSTOR ripple current becomes smaller, immunity
from noise on the error signal is eventually reduced until the
pulse width can no longer be adequately controlled. For the
HIP5061 , the inductor current ripple must be at least 200mA
peak to peak to ensure proper control of the OMOS
transistor current. This effectively establishes a maximum
value for the inductor LSTOR' so as to maintain at least
200mA of ripple. Note that under extremely light or no load
conditions, all converters will eventually operate in DCM, and
the 200mA requirement will eventually be violated. Under
these conditions, the HIP5061 will continue to regulate,
although the SWitching of the OMOS transistor will be in a
burst-mode, controlled by the Light Load Comparator. (See
Figure 2.)
DMOS Transistor TUrn-Off Snubber
In order to reduce dissipation in the OMOS transistor due to
turn-off losses, the turn-off time has been minimized. How·
ever, the rapid reduction of current that occurs in the drain of
The Voo input voltage is monitored by a comparator that
holds off the OMOS transistor gate drive signal when the
V DO voltage is less that about 10.3V. The typical 0.5V hysteresis of this comparator is intended to reduce oscillation
when the voltage at Voo is in the vicinity of 10V. Note,
however, that when an external series resistor is used to
feed the shunt regulator, the voltage drop across this resistor
(which sharply decreases when the IC shuts down), effectively reduces the hysteresis. To reduce the tendency for
oscillation in the vicinity of the 10V threshold, the impedance
of the source that feeds the DC to DC converter input should
be minimized. The addition of a capacitor (111F - 4711F) at the
Voo terminal can also help to provide smooth turn-on or
turn-off of the converter if the input supply rises or falls
gradually through the Voo Comparator threshold.
Peak Controllable DMOS Transistor Currant
Figure 3 shows the guaranteed minimum, peak controllable
OMOS transistor current versus duty cycle. This peak
current value is established by the current limit circuitry,
which effectively clamps the voltage at Vc (the error voltage)
to perform current limiting. Since the sensed OMOS transistor current is summed with a compensating current ramp
that begins its rise 1.511S aiter the initiation of a cycle, current
limiting will begin to occur at a peak OMOS transistor current
that varies with the operating duty cycle. The highest current
limit threshold occurs for 0 < 0.375, where no ramp is added
to the sensed OMOS transistor current. At higher operating
duty ratios, the onset of current limit will occur at increasingly
lower currents, due to the effect of adding the compensating
ramp to the sensed current. Note that this curve represents
guaranteed minimum values. The guaranteed maximum
values are considerably higher, although they are still limited
to levels that protect the IC.
When the OMOS transistor first turns ON there may be
substantial current spikes exceeding the normal maximum
peak current established by the current control stages within
the IC. To prevent these spurious spikes from conveying
erroneous information to the Current Comparator, a 100ns
11·234
Application Note 9323
blanking signal is applied to the current monitoring circuitry.
Thus, there is no peak current protection during the first 6%
of the duty cycle (see Figure 3).
7
!
~
I-
15
II:
a
i
5
··.e.························t··········..······..······..·...................
remembered that once switching operation ceases, the drain
of the DMOS transistor is open. When the supply is in the
Boost configuration, the output voltage is not zero but the
input voltage minus diode and inductor voltage drops. If the
SEPIC topology is used, this is not the case. Shutting down
the regulator via the V c terminal will cut off the output. Figure
5 shows two methods of shutting down the IC. In each case
the current sinking circuit must be able to sink at least 4mA,
the maximum current from the HIP5061 Vc terminal.
·
..•
.
,--------------
3
•:
100kn : 2mA
:
: TVP
·
,
!:I:
:
...w
----I
0.375
DUTY CYCLE
Va
DRAIN
,Vc
: 2D!LF
0.060
VDO
:
------~
FB
sOFT
START
1.000
NETWORK
HIPS061
SOURCE
FIGURE 3. PEAK DMOS TRANSISTOR DRAIN CURRENT VI
DUTY CYCLE
DMOS Transistor Turn-On Noise
Although the large DMOS transistor turn-on current spikes
are "blanked over" by the control circuit, it is important to
minimize these current spikes, since they often result in
voltage spikes considerably below the device substrate that
can activate parasitic devices within the IC. Such activation
of parasitic devices will often result in improper operation of
the IC. An external terminallabeied VG brings out the power
supply to the gate drive circuitry. This allows for the control of
the peak current delivered to the gate of the DMOS
transistor, which in turn establishes the turn-on speed. The
VG pin may be externally bypassed for the fastest possible
turn-on, or series resistance may be added with no bypassing capacitor to slow down the turn-on of the DMOS
transistor. Depending upon the actual layout of the supply, it
is generally recommended that a series resistor be added
(100 - 1500) so that the DMOS transistor turn-on speed is
reduced. By properly adjusting the turn-on speed, undershoot can be avoided while turn-on switching losses are kept
to a minimum.
FIGURE 4. SOFT START CIRCUIT FOR THE HIP5061
FROM
C04048UB
4mA
1I
VDO
Va
DRAIN
Vc
OFF
FB
OFF
Jl.
··••
.... -........
SOURCE
~
Soft Start Implementation
-
NOTE: Frequency Compensation Network Not Shown
It is often desirable to ailow the regulator to start up slowly,
Figure 4 shows one means of implementing this action. The
normally high output current from the HIP5061 transconductance amplifier (when VFB = 0 and VREF = 5.W) is directed
to an external capacitor through a diode. This slows down
the rate of rise of the voltage at the V c terminal. After the
regulator starts, the external capacitor is charged to Voo and
is effectively removed from the frequency compensation
network by a reverse biased diode. To ensure rapid recycling
of the capacitor voltage with removal of power, a diode is
placed across the 100kn resistor.
The DC to DC converter may be shut down by returning the
V c output terminal to ground. A sinking current greater than
4mA will insure that this output is pulled to ground. It must be
z
o
-(J)
FIGURE 5. TWO METHODS OF SHUTTING DOWN THE HIP5061
Mounting, LayOu1 and Component Selection
The T0220 package with its gullwing leads was designed to
be surface mounted. To aid in the external reduction of lead
length and hence inductance and resistance, the IC leads
were staggered. To keep the inductance and resistance of
the critical drain terminal as low as possible, it is suggested
that the PC trace to the DMOS transistor drain terminal be
made as wide as possible. The adjacent source terminal is
not recommended to be used and therefore allows the metal
to the drain terminal to be widened beyond the normal
widths for these term inals. Figure 6 illustrates these points.
11-235
!;iw
(.)1-
-0
~z
Q.
'"
Application Note 9323
ICSOLDERED
TO PC BOARD
VoPCMETAl
WIDER
...... DRAIN
PC METAL
FOR LOWER
INDUCTANCE
-
~g~~kL
FORFB
ANDVc
GROUND PC
METAL
values with good volumetric efficiency and low inductance.
Capacitors around the power input and output circuits should
be returned to the device TAB via a low inductance ground
plane. This TAB is intemally connected to the DMOS
transistor source. The schematic diagram of Figure 7 was
drawn with the diagonal leads to show the critical paths for
the various high frequency elements. These short
interconnects assure the lowest inductance around the
output power circuit.
Design of a 28V, 1.8A Boost Converter
Figure 7 shows the schematic diagram and a parts list of a
50W supply designed with the HIP5061. Table 2 tabulates
the performance of the power supply.
FIGURE 6. SHOWING WIDER PC BOARD METAL FOR
CRmCAL LEADS
One of the most important aspects to the proper application
of this device is high frequency bypassing. In a Boost
converter, for example, there should be a low-inductance
interconnect from the DMOS transistor drain, through the
output diode and capacitors, and retuming· to the TAB
(source) of the HIP5061. Inductance in this line results in
large transient voltages on the DMOS transistor drain terminal which can result in voltages above the maximum DMOS
transistor drain voltage rating.
All the capacitors shown with values of 1J.1F or less are of the
multilayer ceramic type with the X7R dielectric material. This
material has a fairly flat voltage and temperature coefficient
that assures that the capaCitance remains comparatively
constant at extreme operating temperatures and voltages.
The multilayer construction allows for comparatively large
RA
INPUT
II -16V DC
200, lW
.:f-'IisovF,
C4
TABLE2. TYPICALLABORATORYPERFORMANCEOF50W,
28V11.8A REGULATOR
Input Voltage ............................. 11 V to 16V
Une Regulation............................ 12mVN
Output Voltage ............................ 28.0V
Load Regulation ........................... 64mVlA
Output Ripple, FL. ......................... 600mV Pop
(20MHzBW)
Output Ripple, alter Filter, FL ................. 80mV Pop
(20MHzBW)
Efficiency: VI = 11V, IL = 0.18A .............. 90%
VI=IIV,IL=I.8A ...•........... 89%
VI = 16V, IL= 0.18A .............. 73%
VI = 16V, IL = 1.8A ............... 93%
j--:=---------j
,
,
CRI
1
C12
~tt,
C5
-
Rl
4711f,
10K,
1"-
SOV
OUTPUT
28VDC
OA-l.8A
OPTIONAL
FILTER
j
GATE DRIVERS,
CONTROL CIRCUITRY
AND lOGIC
HIP5061
RA
Rl
R2
R4
R5
Rll
PARTS LIST
200, lW, Wlrebound - Dele RWR81S20R0FR or Equivalent
10K,I%
2.2K,I%
l00K,1/4W
100, 1/4W
7.50, 1/2W, Carbon - Allen Bradley EB75G5
ll1F, SOV, Ceramic - Murata Erie RPEI13X7Rl05050V
4711F, 50V, Alum - United Chemlcon 515D476MOSO
6.8j1F, 50V, Ceramin - Mallory M60u6r8M50
lnF, l00V, Ceramln - Kemel C322Cl02K1GSCA
Schottky Diode - Motorola MBRD360
40j1H at 5A, Pulse Engineering PE - 53571
L3 411H at 5.5A, Pulse Engineering PE - 53570
Cl, C3, C4 and Cl1
C5 and C12
C9 and Cl0
C13
CRI
L2
FIGURE 7. HIP5061 SOW, 28V BOOST REGULATOR SCHEMATIC AND PARTS UST
11-236
Application Note 9323
Inductor Selection
In order to maximize the output power for the given maximum controllable DMOS transistor current, this converter
has been designed to operate in continuous current mode
(CCM). In this mode, the inductor value will generally be
large, resulting in a lower inductor ripple current and a lower
peak DMOS current. To ensure that the converter operates
in CCM over the usable range of input voltage and output
current, the value of L2 must be greater than the ·critical
inductance," given by:
(28) (1S)2(28+0.5-1S)4x 10-S
2 (5.S) (28 + 0.5) 2
where PO,MIN has been arbitrarily chosen as 5.SW, corresponding to an output current of O.2A, and Vo is the forward
voltage of CR1. Thus, for L2 > 39J.lH, the converter will be in
CCM for VI = l1V to lSV and IL = 0.2A to 1.8A.
A second factor influencing the selection of L2 is the stability
requirement for current-mode control. Using the above equation for ~IN for the Boost converter:
L>
VO+VD-V I MIN
'
2xMRAMP, MIN
28+0.5-11
2x (0.45xl0SA/S)
= 19J.lH
Thus, L2 must be at least 19J.lH to ensure good stability of
the current loop, and a choice of L2 = 4OJ.lH satisfies this
requirement, while maintaining CCM operation over a wide
load range.
The chosen core material lor L2 is Kool Mu ferrous alloy
powder from Magnetics, Inc. This material was chosen
because of its relatively low cost, while its losses due to /JC
flux are five to ten times less than conventional powdered iron.
Loop Compensation
The control to output transfer function for this current-mode
boost converter has the following characteristics over the
specified load and line conditions:
D.C. Gain: 20dB - 40dB
Pole at 88Hz - 880 Hz
LHP Zero at 1MHz
RHP Zero at 11.0kHz - 110kHz
Double Pole at 80kHz (from filter)
fier, since it is providing bias current for the output stage as
discussed under Using the Transconductance Error
Amplifier section.
Output Filter Design
Inductor L3 was chosen with Cllto provide atleastl5db of
ripple attenuation at the switching frequency. The corner
frequency (80kHz) of this filter is well above the crossover
frequency of the voltage loop (4kHz), and has no effect on
stability. This secondary LC filter was used to reduce output
ripple instead of a lower-cost, high-value, low ESR aluminum
electrolytic capacitor. This filter demonstrates the reduction
in volume possible at this switching frequency. A lower cost
solution could achieve the same output ripple by replacing
C9,10,12 and L3 with one or two large capacitors (e.g.,
390J.lF, 5OV, type S73D from United Chemicon). This change
would also greatly improve load transient response, provided that the loop compensation is appropriately adjusted.
Note that in the circuit of Figure 7, capacitor C12 does not
significanliy affect output ripple, but is necessary to absorb
the energy stored in L2 during severe load transients. In the
event of a step change in load from 1.8A to OA, C12 will limit
the output voltage overshoot to about 10V and protect the
drain of the DMOS transistor from overvoltage breakdown.
Input and Voo Filters
Since the boost converter is current led, input filtering is easily achieved by the addition of a small capacitor, C4. This
capacitor provides nearly 40db of ripple current attenuation
for the input, reducing the AC ripple current flowing into the
converter to less than 200mA.
R5 and C3 have been chosen to provide good filtering of
high frequency pulse currents. R5 provides isolation
between the analog Voo pin and the high pulse current VG
pin, and also provides a means to control the turn-on speed
of the DMOS transistor by limiting the peak current available
to the internal gate drive circuitry. Thus the output transition
time may be increased to prevent drain voltage undershoot.
Undershoot may result in activation of device parasitics and
improper circuit operation. For the two-layer board used for
this design, C3 could be reduced to O.22J.lF without affecting
circuit operation. C5 was added to provide low-frequency filtering at the V DO pin. This reduces the tendency of the circuit
to oscillate off and on when the voltage at the Voo pin in the
vicinity of the under voltage lockout threshold, typically 1Ov.
and the output power is high (30W - 5OW).
Shunt Regulator Resistor
To stabilize the voltage loop, it is necessery to establish the
unity gain crossover frequency well below the RHP zero,
since this zero introduces positive gain and negative phase.
A crossover of 4kHz is fairly conservative, and is achieved by
adding a lJ.lF capacitor at the Vc pin, which provides near
infinite DC gain, and about -5dB of gain at 4kHz. This results
in a phase margin of about 15° at full load. Note that R4 is
required for proper operation of the transconductance ampli-
Resistor RA has been chosen to be as large as possible to
reduce power dissipation at high line, while ensuring
adequate Voo voltage at low line. Note that the guaranteed
range of input voltage for proper operation of this circuit is
11.2V to 15.3V DC, based upon data sheet limits. However,
the circuit was found to perform well at room temperature for
VI 10.7 to 17VDC. The maximum value for RA is
=
RMAX =
VI, MIN -10.5
0.033
= 21 n
RA has been chosen as 200. which results in a current into
11-237
z
o
-0
~w
~b
~z
Q.
CC
Application Note 9323
the VDO clamp that is less than 105mA when the input
voltage is at its maximum:
I MAX
=
(V I,MAX- 13.3 )
20.0
+
+
=100mA< 10SmA
v..
.....-.,._...
Vc
Snubber Network
A snubber network has been added to reduce the ringing at
the drain due to parasitic layout inductances. In particular,
under severe load transient conditions, this snubber is
necessary to protect the drain from voltage breakdown. A
second benefit of reducing the noise and ringing at the drain
is that it reduces the tendency of the HIPS061 to exhibit
noise-related instabilities at high peak DMOS transistor
currents (4A - SA). A value of 1000pF was chosen for C13,
since this is adequate to dampen the ringing associated with
the 200pF drain capacitance of the DMOS transistor. R11
was chosen as 7.S0 to provide the best possible dampening
given the parasitiC inductances that exist in the layout. Note
that this snubber may not be necessary if the. layout of the
circuit were improved, or if the application did not push the
envelope of DMOS transistor current.
aND
FB I--t---+---.
SOURCE
SEPIC (FAIL-SAFE BUCK) CONVERTER
-
+
Voo
..
va
DRAIN
GATE DRIVER
v
Vc
ANDCONTROL~l
CIRCUITRY
FB
:~
aND
The SEPIC tOpoiogylll,13j does not have quite as wide inputoutput voltage range with reasonably controlled duty cycles
as the Quadratic converter mentioned above, but it does
allow both voltage increase and decrease with the same circuit. This is particularly advantageous when a power supply
is being used in the stabilizing mode and isolation is not
required. For example, in an application where a regulated
24V output is required and the input voltage varies ±20%
from a nominal 24V. The SEPIC supply can provide both the
Boost and Buck functions.
Another outstanding advantage of the SEPIC topology is
its fault Isolation of the input and output voltage. All energy
is transferred via the coupling capacitor. Moreover if the
clock stops, voltage transfer stops. If the switching transistor
shorts there is no output. The Buck circuit will apply full input
voltage to the load with a shorted transistor. This is
the reason that the SEPIC topology is referred to as the failsafe Buck.
'I" ~
>-
VOUT
~
HIP5061
Other Power Supply Topologies
Figure 8 shows three other topologies besides the Boost that
may be implemented with the grounded source DMOS
powertransistor used in the HIP5061. Other, more complex
power supply topologies such as the Quadratic are also possible to implement with the HIP5061. One noteworthy feature of the Quadratic topology as shown in Figure 8 is the
wide input to output voltage transfer ratio possible with reasonable duty cycles. This permits easier control at the
extremes of the transfer ratio. Compensating the control loop
can pose challenges because of the wider changes in the
transfer ratio and hence loop gain.
VOUT
SOURCE
...L
CUK CONVERTER
+
+
v..
Vc
...._ _ _...
FB t--t---t..--t
L..:a:;yN.:.D_ _ _....;;SO.:.U;;;R..:.;C:;:E+-I
QUADRATIC CONVERTER
FIGURE 8. THREE OTHER TOPOLOGIES
It should be noted that when the Cuk topology is
implemented, a transistor current source is used to convert
the negative output voltage of the Cuk converter to a current
that is level shifted to the FB terminal on the HIPS061.
11-238
Application Nots 9323
Two other useful topologies that may be used are the Forward
and the Flyback as shown in Figure 9 and Figure 10. As
shown, they may either be operated as an isolated or non-isolated converter.
power transistor. The burden of voltage, and power is placed
upon the external transistor. The HIP5061 still performs the
drain current sampling and the control function is the same
as the non cascode configuration.
+
+
+
II
v..
SOURCE
OND
FIGURE 9. FORWARD CONVERTER
FIGURE 11. OFF UNE CASCODE SEPIC
Figure 12 shows the voltage transfer as a function of duty
cycle for the power supply topologies discussed.
+
100
+
BUCK-BOOST, CUK AND SEPIC
j_DI(1-D)
L
10
v..
E
1
.L
1-
1£
M .11(1 - D) BOOST
II
Vc
.....--.,._....
GND
SOURCE
r.·.·.· . . ----,
)
, COUPUNG
, MEANS ,
: ISOLATED:
: OR DIRECT
'-
~,....
1.0
•
:Ii
--------~
"
o.1
LL
M.D
QUADRAT~~
M.02l{l-D
L
IL V
0.01
0.0
FIGURE 10. FLYBACKCONVERTER
Both the SEPIC and the Boost topologies may be operated
at high voltages with the addition of a high voltage cascode
transistor. Figure 11 shows the Cascode SEPIC converter
that is essentially limited by the selection of the external
0.1
BU~
~
0.2
0.3
G.4
0.5
o.s
0.7
0.8
0.'
1.0
DUTY CYCLE (D)
FIGURE 12. VOLTAGE TRANSFER AS A FUNCTION OF DUTY
CYCLE FOR VARIOUS TOPOLOGIES
Z
o
-fJ)
!;;:w
(,)~
-0
KZ
Q.
ee
11-239
Application Note 9323
References
[1] Cassani, John C. Hurd, Jonathan J. and Thomas, David
R., Wittlinger, H.A. Hodgins, Robert G. Sophisticated ControIlC Enhances 1MHz Current Controlled Regulator Per·
formance, High Frequency Power Conversion (HFPC)
conference proceedings, May 1992, pp. 167-173
and Bloom, Modern DC-ta-DC Switchmode
Power Converter Circuits, Van Nostrend Reinhold, 1985
[8] Severns
[9]
Sum, K., Switch Mode Power Conversion - Basic Theory
and Design, Marcel Dekker, In., 1984
[10)
Pressman, A., SWitching and Unear Power Supply. Power
Converter Design, Hayden Book Co., 1977
[2)
Smith, Craig D. and Cassani, Distributed Power Systems
Via ASICs Using SMT, Surface Mount Technology,
October 1990
[3)
Maksirnovic and Cuk, Switching Converters With Wide DC
Conversion Range, High Frequency Power Conversion
(HFPC) conference record, May 1989
[12] Clarke,
[5)
Maksimovic and CuI<, General Properties and Synthesis of
PWM DC-ta-DC Converters, IEEE Power Electronics
Specialists Conference (PESC) record, June 1989
[13] Harris Application Notes AN9208 and AN9212.1.
[6)
Sokal and Sokal, Class E . A New Class of High Efficiency
Tuned Single-Ended Switching Power Amplifiers. IEEE
Joumal of Solid-State Circuits, June 1975, pp. 168-176
[7)
Mansmann, Jeff; Shafer, Peter and Wildi, Eric, Maximizing
the Impact of Power IC's Via a Tlme-ta-Market CAD Driven
Power ASIC Strategy. Applied Power and Electronics
Conference and Exposition (APEC) proceedings, February 1992, pp. 23-27
R.P. and Snyder, E.C., High Voltage SingleEnded DC-DC Converter, IEEE Power Electronics Specialists Conference (PESC) record, 1977, pp. 156-159
[11] Massey,
P., A New SWitched-Mode Power Conversion
Topology Provides Inherently Stable Response, POWERCON 10 proceedings, March 1983, pp. E2-1 through E2-7
11-240
Harris Semiconductor
------
--
-
--
--- --- --- --.=-=-=:-=--
--=-====
- -=
----===.
- =
- -----
~
-
-----
No. AN9324.1
====
Harris Intelligent Power
Apr1l1994
HIP4080, 80V HIGH FREQUENCY H-BRIDGE DRIVER
Author: George E. Danz
Introduction
IOV
1
The HIP4080 is a member of the HIP408X family of High
Frequency H-Bridge Driver ICs. A simplified application diagram is shown in Figure 1. The HIP4080 H-Bridge driver IC
provides the ability to operate from 8VDC to 80VDC busses
for driving N-Channel MOSFET H-Brldges, The HIP4080
packaged in either 20 lead DIP or 20 lead SOIC, provides
peak gate current drive of 2.5A.
•
A combination of bootstrap and charge-pumping techniques
is used to power the circuitry which drives the upper MOSFETs of the H-Bridge. The bootstrap technique supplies the
high instantaneous current needed for turning on the power
devices, while the charge pump provides enough current to
maintain bias voltage on the upper driver sections and MOg.
FETs. Since voltages on the upper bias supply pin "fIoar'
with the source terminals of the upper power switches, the
design of this family provides voltage capability for the upper
bias supply terminals to 95VDC.
GND
GND
FIGURE 1. HIP4080 SIMPLIFIED APPUCATION DIAGRAM
The HIP4080 can drive lamp loads for automotive and industrial applications as shown in Figure 2. When inductive loads
are SWitched, flyback diodes must be placed around the
loads to protect the MOSFET switches.
+lOY
The HIP408X family of devices is fabricated using a proprietary Harris IC process which allows this family to switch at
frequencies of over 500kHz. Therefore the HIP408X family is
ideal for use in voice coil motor, class-D audio amplifier, DCDC converters and high performance AC, DC and stepmotor control applications.
Many applications utilize the full bridge topology. These are
voice coil motor drives, stepper and DC brush motors, audio
amplifiers and &Yen power supply inverters used in uninterruptable power supplies, just to name a lew. 01 the above, voice coil
motor drives and audio amplifiers can take advantage of the
buitt-in comparator available in the HIP4080. Using the output
of the comparator to add some positive feedback, a hysteresis
control, so popular with voice coil motor drivers, can be implemented as shown in FlQure 3. In the figure, R3 is fed back from
the comparator output, OUT, to the positive input of the comparator, IN+. Capacitor, C1, integrates in a direction to satisfy the
reference current signal at IN. The IN- input of the comparator
sums this current reference with a signal proportional to load
current through resistor, R4, which comes from a differential
amplifier, A1. A bias voltage of 6V (represents half of the bias
voltage and the maximl.m rail to rail voltage of the comparator
and amplifier, A1) biases the comparator's IN+ terminal through
R2 and the amplifier, A 1's, positive summing junction.
L
---,,
HIP408X
*
,
---~
z
o-en
tiUJ
GND
~15
~z
Q.
FIGURE 2. HIP4080 AS LAMP SWITCH DRIVER, DUAL HIGHt
LOW SWITCHES FOR AUTOMOTIVE AND INDUSTRIAL CONTROLS
When no current is flowing in either direction in the load, the
output of A1 is exactly 6V. The reference input, IN, would
also have to be 6V to requesl zero current from the bridge.
The bridge would stili switch in this case, because of the
positive feedback connection of the HIP4080 internal comparator. The frequency of oscillation of the output will be a
function of the amount of de hysteresis gain, R3IR1 and the
Copyright@Harrls Corporation 1994
11-241
ct
Application Note 9324
size of capacitor, Cl. As the capacitor, Cl, is made larger,
the steady-state frequency of the bridge will become smaller.
It is beyond the scope of this application note to provide a full
analysis. A valuable characteristic of hysteresis control is
that as the error becomes smaller (I.e. the reference and
feedback signals match) the frequency increases. Usually
this occurs when the load current is small or at a minimum.
When the error signal Is large, the frequency becomes very
small, perhaps even de. One advantage of this is that when
currents are largest, switching losses are a minimum, and
when switching losses are largest, the dc current component
is small.
To provide accurate dead-time control for the twin purposes
of shoot-through avoidance and duty-cycle maximization,
two resistors tied to pins HDEL and LDEL provide precise
delay matching of upper and lower propagation delays,
which are typically only 55ns. The HIP408X family of
H-Bridge drivers have enough voltage margin to be applied
to all SELV (UL classifICation for operation at :s; 42.0V) applications and most Automotive applications where "load
dump" capability over 65V is required. This capability makes
the HIP408X family a more cost-effective solution for driving
N-channel power MOSFETs than either discrete solutions or
other solutions relying on transformer or opto-coupling gatedrive techniques as shown in Figure 1.
The HIP4080 differs from the HIP4081 regarding the function of pins 2, 5, 6 and 7 of the IC and the truth table which
governs the switching· function of the two ICs. In the
HIP4080, pins 2, 5, 6 and 7 are labeled HEN, OUT, IN+ and
IN-, respectively. In the HIP4081, pins 2, 5, 6 and 7 are
labeled BHI (B-side high input), BLI (B-side low input), ALI
(A-Side low input) and AHI (A-side high Input), respectively.
The HIP4081's inputs individually control each of the four
power MOSFETs, or in pairs (excepting the Shoot-through
case). The HIP4060 provides an internal comparator and a
"HEN ...high enable" pin. The comparator can be used to provide a PWM logic signal to switch the appropriate MOSFETs
within the H-bridge, and can facilitate "Hysteresis· control to
be illustrated later. The HEN pin enables (when HEN is high)
or disables (when HEN is low) the upper MOSFETs. With
HEN held low, it is possible to switch only the lower H-bridge
MOSFETs. The HEN input can also be PWM-switched with
the IN+ and IN- inputs used only for direction control, thereby
minimizing switching losses.
Description of the HIP40S0
The block diagram of the HIP4080 relating to driving the
A-side of the H-Bridge is shown in Figure 4. The blocks
associated with each side of the H-Bridge are identical, so
the B-side is not shown for simplicity.
The two bias voltage terminals on the HIP408X H-Bridge
Drivers, Vee and Voo should be tied together. They were
separated within the HIP408X IC to avoid possible ground
loops internal to the IC. Tieing them together and providing a
decoupling capacitor from the common tie-point to Vss
greatly improves noise immunity.
Input logic
The HIP4080 accepts inputs which control the output state of
the power MOSFET H-brldge and provides a comparator output pin, OUT, which can provide compensation or hysteresis.
The DIS, "Disable,· pin disables gate drive to all H-bridge
MOSFETs regardless of the command states of the input
pins, IN+, IN- and HEN. The HEN, "High Enable," pin
enables and disables gate drive to the two high side MOSFETs. A high level on the HEN pin "enables· high side gate
drive as further determined by the states of the IN+ and INcomparator input pins, since the IN+ and IN- pins control
which diagonal pair of MOSFETs are gated. Upper drive can
be "modulated" through use of the HEN pin while drive to
diagonally opposing lower MOSFETs is continuous. To simultaneously modulate both upper and lower drivers, HEN is continuously held high while modulating the IN+ and IN- pins.
Modulating only the upper switches can nearly halve the
switching losses in both the driver IC and In the lower MOSFETs. The power dissipation saved at high switching frequencies can be signifICant. Table 1 summarizes the input
control logic.
TABLE 1. INPUT LOGIC TRUTH TABLE
IN+> IN-
DIS
HEN
ALO
AHO
BLO
BHO
X
1
X
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
X = DON'T CARE
1
1 = HIGH/ON
0 = LOW/OFF
The input sensitivity of the DIS and HEN input pins are best
described as "enhanced T'TC' levels. Inputs which fall below
1.0V or above 2.5V are recognized, respectively, as low level
or high level inputs. The IN+ and IN- comparator inputs have
a common mode input voltage range of 1.0V to Voo -1.5V,
whereas the offset voltage is less than 5mV. For more information on the comparator specifications, see Harris Data
Sheet HIP4Oao, File Number 3178.
Propagation Delay Control
Propagation delay control is a major feature of the HIP4080.
Two Identical sub-circuits within the IC delay the commutation of the power MOSFET gate turn-on signals for both
sides of the H-bridge. The gate turn-off signals are not
delayed. Propagation delays related to the level-translation
function (see section on Level-Translation) cause both upper
on/off propagation delays to be longer than the lower onIoff
propagation delays. Four delay sub-circuits are needed to
fully belance the H-bridge delays, two for upper delay control
and two for lower delay control.
Users can tailor the low side to high side commutation delay
times by placing a resistor from the HDEL pin to the Vss pin.
Similarly, a resistor connected from LDEL to Vss controls the
high side to low side commutation delay times of the lower
power switches. The HDEL resistor controls both upper commutation delays and the LDEL resistor controls the lower
commutation delays. Each of the resistors sets a current
11-242
Application Note 9324
IOV
1
•
RI
RI
Rsh
RO
Rsh
GND
FIGURE 3. HYSTERESIS MODE SWITCHING
HIGH VOLTAGE BUS s I5VDC
AHB
AHO
AHS
Z
TO VDD (PIN 18)
0
-II)
~W
~5
~Z
Q.
+12VDC
.::. BIAS
SUPPLY
ALO
ALS
FIGURE 4. HIP4080 BLOCK DIAGRAM (A SIDE ONLy)
11·243
CBF
c:c
Application Note 9324
which is inversely proportional to the created delay. The
delay is added to the falHng edge of the ·off" pulse associated with the MOSFET which is being commutated off.
When the delay is complete, the "on" pulse is initiated. This
has the effect of ·delaying" the commanded on pulse by the
amount set by the delay, thereby creating dead-time.
able operation can be obtained with pulse widths of approximately SOns. At a switching frequency of even 1.0MHz, with
an 80VDC bus potential, the power developed by the leveltranslation circuit will be less than O.08W.
Proper choice of resistor values connected from HDEL and
LDEL to Vss provides a means for matching the commutation dead times whether commutating high to low or low to
high. Values for the resistors ranging from lOkn to 200kO
are recommended. Figure 5 shows the delays obtainable as
a function of the resistor values used.
There are two charge pump circuits in the HIP4080, one for
each of the two upper logic and driver circuits. Each charge
pump uses a switched capacitor doubler to provide about
30jJ.A to 5OjJ.A of gate load current. The sourcing current
charging capability drops off as the floating supply voltage
increases. Eventually the gate voltage approaches the level
set by an internal zener clamp, which prevents the voltage
from exceeding about 15V, the safe gate voltage rating of
most commonly available MOSFETs.
150
Charge Pump Circuits
120
.I
30
o
V
10
V
50
/
V"
V
lL:::
100
150
200
HDELILDEL RESISTANCE IKn)
Driver Circuits
Each of the four output drivers are comprised of bipolar high
speed NPN transistors for both sourcing and sinking gate
charge to and from the MOSFET switches. In addition, the
sink driver incorporates a parallel-connected n-channel
MOSFET to enable the gate of the power switch gate-source
voltage to be brought completely to Ov.
250
FIGURE 5. MINIMUM DEAD-TIME VI DEL RESISTANCE
The propagation delays through the gate driller sub-circuits
while driving SOOpF loads is typically less than 10ns. Nevertheless, the gate driver design nearly eliminates all gate
driller shoot-through which significantly reduces IC power
dissipation.
Application Considerations
Level-Translation
The lower power MOSFET gate drille signals from the propagation delay and control circuits go to amplification circuits
which are described in more detail under the section "Driver
Circuits". The upper power MOSFET gate drive signals are
directed first to the Level-Translation circuits before gOing to
the upper power MOSFET "Driver Circuits".
The Level-Translation circuit communicate "on" and "off"
pulses from the Propagation Delay sub-circuit to the upper
logic and gate drive sub-circuits which "float" at the potential
of the upper power MOSFET source connections. This voltage can be as much as 85V when the bias supply voltage is
only 10V (the sum of the bias supply voltage and bus voltages must not exceed 95VDC).
In order to minimize power dissipation in the level-shifter circuit, it is important to minimize the width of the pulses translated because the power dissipation is proportional to the
product of switching frequency and pulse energy in joules.
The pulse energy in turn is equal to the product of the bus
voltage magnitude, translation pulse current and translation
pulse duration. To provide a reliable, noise free pulse
requires a nominal current pulse magnitude of approximately
3mA. The translated pulses are then "latched' to maintain
the ·on" or "off" state until another level-translation pulse
comes along to set the latch to the opposite state. Very rell-
To successfully apply the HIP4080 the designer should
address the following C9"cerns:
• General Bias Supply Design Issues
• Upper Bias Supply Circuit Design
• Bootstrap Bias Supply Circuit Design
General Bias Supply Design Issuea
The bias supply design is simple. The designer must first
establish the desired gate voltage for turning on the power
switches. For most power MOSFETs, increasing the gatesource voltage beyond 10V yields little reduction in switch
drain-source voltage drop.
Overcharging the power switch's gate-source capaCitance
also delays turn-off, increases MOSFET switching losses
and increases the energy to be switched by the gate driver of
the HIP4080, which increases the dissipation within the
HIP4080. Overcharging the MOSFET gate-source capacitance also can lead to "$hoot-through" where both upper and
lower MOSFETs in a single bridge leg find themselves on
simultaneously, thereby shorting out the high voltage DC bus
supply. Values close to 12V are optimum for supplying Voo
and Vee, although the HIP4080 will operate up to 15V.
11-244
Application Nots 9324
Lower Blaa Supply Design
Since most applications use identical MOSFETs for both
upper and lower power switches, the bias supply requirements with respect to driving the MOSFET gates will also be
identical. If switching frequencies for driving upper and lower
MOSFETs differ, two sets of calculations must be done; one
for the upper switches and one for the lower switches. The
bias current budget for upper and lower switches will be the
sum of each calculation.
Always keep in mind that the lower bias supply must supply
current to the upper gate drive and logic circuits as well as
the lower gate drive circuits and logic circuits. This is due to
the fact that the low side bias supplies IYcdVoo) charge the
bootstrap capaCitors and the charge pumps, which maintain
voltage across the upper power switch's gate-source terminals.
Good layout practice and capacitor bypassing technique
avoids transient voltage dips of the bias power supply to the
HIP4080. Always place a low ESR (equivalent series resistance) ceramic capacitor adjacent to the IC, connected
between the bias terminals Vee and Voo and the common
terminal, Vss of the IC. A value in the range of O.22I1F and
0.511F is usually sufficient.
Minimize the effects of Miller feedback by keeping the
source and gate return leads from the MOSFETs to the
HIP4080 short. This also reduces ringing, by minimizing the
length and the inductance of these connections. Another
way to minimize inductance in the gate charge/discharge
path, in addition to minimizing path length, is to run the outbound gate lead directly "over" the source return lead.
Sometimes the source return leads can be made into a small
"ground plane" on the back side of the PC board making it
possible to run the outbound gate lead "on top" of the board.
This minimizes the "enclosed area" of the loop, thus minimizing inductance in this loop. It also adds some capacitance
between gate and source which shunts out some of the
Miller feedback effect.
Upper Bias Supply Circuit Design
Before discussing bootstrap circuit design in detail, it is
worth mentioning that it is possible to operate the HIP4000
without a bootstrap circuit altogether. Even the bootstrap
capacitor, which functions to supply a reservoir of charge for
rapidly turning on the MOSFETs, is optional in some cases.
In situations where very slow turn-on of the MOSFETs is tolerable, one may consider omitting some or all bootstrap
components. Applications such as driving relays or lamp
loads, where the MOSFETs are switched infrequently and
switching losses are low, may provide opportunities for omit·
ting the boot strap operation. Generally, loads with a lot of
resistance and inductance are candidates.
Operating the HIP4080 without a bootstrap diode and/or
capacitor will severely slow gate turn-on. Without a boot·
strap capacitor, gate current only comes from the internal
charge pump. The peak charge pump current is only about
301lA to 501J.A. The gate voltage waveform, when operating
without a bootstrap capaCitor, will appear similar to the dot·
ted line shown in Figure 6.
If a bootstrap capacitor value approximately equal to the
equivalent MOSFET gate capaCitance is used, the upper
bias supply (labeled "bootstrap voltage" in Figure 6) will drop
approximately in half when the gate is turned on. The larger
the bootstrap capacitance used, the smaller is the instanta·
neous drop in bootstrap supply IIOltage when an upper
MOSFET is turned on.
INI~~OH
SIGNAL
BOOT STRAP
ci~~~:s)
GATE VOLTAGE
(XHO.XHS)
1_...I4-___
I
I
.....J. ._ _ __
...
'I1-_....,t::.........................
1 1-----.,
...._.._...._.
............ .... _
__
----1:::.:.....--4--FIGURE&.
Although not recommended, one may employ a bootstrap
capacitor without a bootstrap diode. In this case the charge
pump is used to charge up a capacitor whose value should
be much larger than the equivalent gate-source capacitance
of the driven MOSFET. A value of bootstrap capacitance
about 10 times greater than the equivalent MOSFET gate·
source capacitance is usually sufficient. Provided that suffi·
cient time elapses before turning on the MOSFET again, the
bootstrap capacitor will have a chance to recharge to the
voltage value that the bootstrap capaCitor had prior to turning on the MOSFET. Assuming 20 of series resistance is in
the bootstrap change path, an output frequency of up
to
1
should allow sufficient refresh time.
5 x20xC BS
A bootstrap capacitor 10 times larger than the equivalent
gate-source capacitance of the driven MOSFET prevents
the drop in bootstrap supply voltage from exceeding 10% of
the bias supply voltage during turn-on of the MOSFET.
When operating without the bootstrap diode the time
required to replenish the charge on the bootstrap capacitor
will be the same time as it would take to charge up the equiv·
alent gate capacitance from OV. This is because the charge
lost on the bootstrap capacitor is exactly equal to the charge
transferred to the gate capaCitance during turn-on. Note that
the very first time that the bootstrap capaCitor is charged up,
it takes much longer to do so, since the capacitor must be
charged from OV. With a bootstrap diode, the initial charging
of the bootstrap supply is almost instantaneous, since the
charge required comes from the Iow·side bias supply. therefore, before any upper MOSFETs can initially be gated, time
must be allowed for the upper bootstrap supply to reach full
voltage. Without a bootstrap diode, this initial "charge" time
can be excessive.
If the switching cycle is assumed to begin when an upper
MOSFET is gated on, then the bootstrap capacitor will
undergo a charge withdrawal when the source driver con·
nects it to the equivalent gate-source capacitance of the
MOSFET. After this initial "dump· of charge, the quiescent
11-245
z
o-en
~w
~b
iiz
Q.
cC
Application Note 9324
current drain experienced by the bootstrap supply is infinitesimal. In fact, the quiescent supply current is more than
offset by the charge pump current.
The charge pump continuously supplies current to the bootstrap supply and eventually would charge the bootstrap
capacitor and the MOSFET gate capaCitance back to its initial value prior to the beginning of the switching cycle. The
problem is that "eventually" may not be fast enough when the
switching frequency is greater than a few hundred Hz.
The off-time of the upper MOSFET is dependent on the gate
control input signals, but it can never be shorter than the
dead-time delay setting, which is set by the resistors connecting HDEL and LDEL to V ss. If the bootstrap capaCitor is
not fully charged by the time Ihe upper MOSFET turns on
again, incomplete refreshing occurs. The designer must
insure that the dead-time setting be consistent with the size
of the bootstrap capacitor in order to guarantee complete
refreshing. Figure 7 illustrates the circuit path for refreshing
the bootstrap capacitor.
Bootstrap Bias Supply Circuit Design
For high frequency applications all bootstrap components,
both diodes and capacitors, are required. Therefore, one
must be familiar with bootstrap capacitor sizing and proper
choice of bootstrap diode.
•!1!r..!P.f.9................. ,1I.,
i
ALO
0G = (VBS1-VSS2) xC BS
ALB
Vee
(EO.1)
TO "B-SlDE"
where:
Vss
V BS1 = Bootstrap voltage immediately before turn-on
VBS2= Bootstrap voitage immediately after turn-on
CBS = Bootstrap CapaCitance
OG • Gate charge transferred during turn-on
tI . . . . . .
In PWM switch-mode, the switching frequency is equal to the
reCiprocal of the period between successive turn-on (or turnoff) pulses. Between any two turn-on gate pulses exists one
turn-off pulse. Each time a turn-off pulse is issued to an
upper MOSFET, the bootstrap capacitor of that MOSFET
begins its "refresh" cycle. A refresh cycle ends when the
upper MOSFET is turned on again, which varies depending
on the PWM frequency and duty cycle. As the duty cycle
approaches 100%, the available "off-time", toFF approaches
zero. Equation 2 shows the relationship between IoFf' fPWM
and the duty cycle.
DC) IfpWM
SUPPLY
BYPASS
CAPACITOR
OFH-BRIDGE
NOTE: Only"A-sIde" of H-bridge Is Shown for Simplicity.
Arrows Show Bootstrap Charging Path.
Were it not for the internal charge pump, the voltage on the
bootstrap capacitor and the gate capaCitor (because an
upper MOSFET is now turned on) would eventually drain
down to zero due to bootstrap diode leakage current and the
very small supply current associated with the level-Shifters
and upper gate driver sub-circuits.
= (1 -
TOB-SlDE
OF
H-BRIDGE
AHB!
Just after the switch cycle begins and the charge transfer
from the bootstrap capaCitor to the gate capacitance is complete, the voltage on the bootstrap capacitor is the lowest
that it will ever be during the switch cycle. The charge lost on
the bootstrap capacitor will be very nearly equal to the
charge transferred to the equivalent gate-source capacitance of the MOSFET as shown in Equation ,.
tOFF
HIGH VOLTAGE BUS... ~!!!!!•
(EO.2)
As soon as the upper MOSFET is turned off, the voltage on
the phase terminal (the source terminal of the upper MOSFET) begins its descent toward the negative rail of the high
voltage bus. When the phase terminal voltage becomes less
than the Vee voltage, refreshing (charging) of the bootstrap
capaCitor begins. As long as the phase voltage is below Vee
refreshing continues until the bootstrap and Vee voltages
are equal.
FIGURE 7. BOOTSTRAP CAPACITOR CHARGING PATH
The bootstrap charging and discharging paths should be
kept short, minimizing the inductance of these loops as mentioned in the section, "Lower Bias Supply Design".
Bootstrap Circuit Design - An Example
Equation 1 describes the relationship between the gate
charge transferred to the MOSFET upon turn-on, the size of
the bootstrap capaCitor and the change in voltage across the
bootstrap capacitor which occurs as a result of turn-on
charge transfer.
The effects of reverse leakage current associated with the
bootstrap diode and the bias current associated with the
upper gate drive circuits also affect bootstrap capacitor sizing. At the instant that the upper MOSFET turns on and its
source voltage begins to rapidly rise, the bootstrap diode
becomes rapidly reverse biased resulting in a reverse recovery charge which further depletes the charge on the bootstrap capacitor. To completely model the total charge
transferred during turn-on of the upper MOSFETs, these
effects must be accounted for, as shown in Equation 3.
11-246
(EO.3)
Application Note 9324
where:
=
lOR Bootstrap diode reverse leakage current
laas Upper supply quiescent current
ORR Bootstrap diode reverse recovered charge
OG = Turn-on gate charge transferred
f pWM = PWM operating frequency
Vas1 = Bootstrap capacitor voltage just after refresh
VBS2 Bootstrap capacitor voltage just after upper turn on
Cas = Bootstrap capacitance
=
=
=
From a practical standpoint, the bootstrap diode reverse
leakage and the upper supply quiescent current are negligible, particularly since the HIP40s0's internal charge pump
continuously sources a minimum of about 301lA This current
more than offsets the leakage and supply current components, which are fixed and not a function of the switching frequency. The higher the switching frequency, the lower is the
charge effect contributed by these components and their
effect on bootstrap capacitor sizing is negligible, as shown in
Equation 3. Supply current due to the bootstrap diode recovery charge component increases with switching frequency
and generally is not negligible. Hence the need to use a fast
recovery diode. Diode recovery charge information can usually be found in most vendor data sheets.
For example, if we choose a Harris IRF520R power
MOSFET, the data book states a gate charge, Qg, of 12nC
typical and 18nC maximum, both at Vos 12V. Using the
maximum value of 18nC the maximum charge we should
have to transfer will be less than 18nC.
=
Suppose a General Instrument UF4002, 100V, fast recovery,
1A, miniature plastic rectifier is used. The data sheet gives a
reverse recovery time of 25ns. Since the recovery currenl
waveform is approximately triangular, the recovery charge can
be approximated by taking the product of half the peak reY9rse
current magnitude (1 A peak) and the recovery time duration
(25ns). In this case the recovery charge should be 12.5nC.
Since the internal charge pump offsets any possible diode
leakage and upper drive circuit bias currents, these sources
of discharge current for the bootstrap capacitor will be
ignored. The bootstrap capacitance required for the example
above can be calculated as shown in Equation 4, using
Equation 2.
C
- 18nC + 12.5nC
BS 12.0-11.0
(Ea. 4)
Therefore a bootstrap capaCitance of O.033I1F will result in
less than a 1.0V droop in the voltage across the bootstrap
capacitor during the turn-on period of either of the upper
MOSFETs. If typical values of gate charge and bootstrap
diode recovered charge are used rather than the maximum
value, the voltage droop on the bootstrap supply will be only
aboutO.5V
Power Dissipation and Thermal Design
One way to model the power dissipated in the HIP4080 is by
lumping the losses into static losses and dynamic (switching) losses. The static losses are due to bias current losses
for the upper and lower sections of the IC and include the
sum of the Icc and 100 currents when the IC Is not switching.
The quiescent current is approximately 9mA. Therefore with
a 12V bias supply, the static power dissipation in the IC is
slightly over 100mW.
The dynamic losses associated with switching the power
MOSFETs are much more signifICant and can be divided into
the following categories:
•
Low Voltage Gate Drive (charge transfer)
•
High Voltage Level-shifter (V-I) losses
•
High Voltage Level-shifter (charge transfer)
In practice, the high voltage level-shifter and charge transfer
losses are small compared to the gate drive charge transfer
losses.
The more significant low voltage gate drive charge transfer
losses are caused by the movement of charge in and out of
the equivalent gate-source capacitor of each of the 4 MOSFETs comprising the H-bridge. The loss is a function of
PWM (switching) frequency, the applied bias voltage, the
equivalent gate-source capaCitance and a minute amount of
CMOS gate charge internal to the HIP4080. The low voltage
charge transfer losses are given by Equation 5.
PSWLO
= fpWM x (OG + ale) x VBIAS
(Ea. 5)
The high voltage level-shifter power dissipation is much
more difficult to evaluate, although the equation which
defines it is simple as shown in Equation 6. The difficulty
arises from the fact that the level-shift current pulses, ION
and IOFF' are not perfectly in phase with the voltage at the
upper MOSFETsource terminals, VSH1FT due to propagation
delays within the IC. These time-dependent source voltages
(or "phase" voltages) are further dependent on the gate
capacitance of the driven MOSFETs and the type of load
(resistive, capacitive or inductive) which determines how
rapidly the MOSFETs turn on. For example, the level-shifter
ION and IOFF pulses may come and go and be latched by the
upper logic circuits before the phase voltage even moves.
As a result, little level-shift power dissipation may result from
the ioN pulse: whereas the IOFF pulse may have a Significant
power dissipation associated with it, since the phase voltage
generally remains high throughout the duration of the ioFF
pulse.
(Ea. 6)
Lastly, there is power dissipated within the IC due to charge
transfer in and out of the capacitance between the upper
driver circuits and Vss. Since it is a charge transfer phenomena, it closely resembles the form of Equation 5, except that
the capacitance is much smaller than the equivalent gatesource capaCitances associated with power MOSFETs. On
the other hand, the voltages associated with the level-shifting function are much higher than the voltage changes experienced at the gate of the MOSFETs. The relationship is
shown In Equation 7.
11-247
(Ea. 7)
Application Note 9324
The power associated with each of the two high voltage tubs
in the HIP4080 derived from Equation 7 is quite small, clue to
the extremely small capacitance associated with these tubs.
A "tub" is the Isolation area which surrounds and isolates /he
high side circuits from the ground referenced circuits of the
IC. The important point for users is that the power dissipated
is linearly related to switching frequency and the square of
the applied bus voltage.
The tub capacitance in Equation 7 varies with applied voltage, V SHIFT, making its solution difficult, and the phase shift
of the ION and IOFF pulses with respect to the phase voltage,
VSHIFT, in Equation 6 are difficult to measure. Even the ale in
Equation 5 is not easy to measure. Hence the use of Equation 5 through Equation 7 to calculate total power dissipation
is at best difficult. The equations do, however, allow users to
understand the Significance that MOSFET choice, switching
frequency and bus voltage play in determining power dissipation. This knowledge can lead to corrective action when
power dissipation becomes excessive.
Fortunately, there is an easy method which can be used to
measure the components of power dissipation rather than
calculating them, except for the tiny "tub capacitance" component.
Power Dissipation, the Easy Way
The average power dissipation associated with the IC and
the gate of the connected MOSFETs can easily be measured using a signal generator, an averaging milliameter and
a voltmeter.
Low Voltage Power Dissipation
HIP4OIO
CL - GATE LOAD CAPACITANCE
FIGURE 8. LOW VOLTAGE POWER DISSIPATION TEST
CIRCUIT
The low voltage charge transfer switching currents are
shown in Figure 9. Figure 9 does not include the quiescent
bias current component, which is the bias current which
flows in the IC when switching Is disabled. The quiescent
bias current component is approximately 1OmA. Therefore
the quiescent power loss at 12V would be 12OmW. Note that
the bias current at a given switching frequency grows almost
proportionally to the load capacitance, and the current is
directly proportional to switching frequency, as previously
suggested by Equation 5.
CL-
;C500
.! 200
100
l/
V ./
, / i./" V
!z
Two sets of measurements are required. The first set uses
the circuit of Figure 8 and evaluates all of the low voltage
power diSSipation components. These components include
the MOSFET gate charge and internal CMOS charge transfer losses shown in Equation 5 as well as the quiescent bias
current losses associated with the IC. The losses are calculated very simply by calculating the product of the bias voltage and current measurements as performed using the
circuit shown in Figure 8. For measurement purposes, the
phase terminals (AHS and BHS) for both A and B phases
are both tied to the chip common, Vss terminal, along with
the lower source terminals, AlS and BlS. Capacitors equal
to the equivalent gate-source capacitance of the MOSFETs
are connected from each gate terminal to Vss. The value of
the capacitance chosen comes from the MOSFET manufacturers data sheet. Notice that the MOSFET data sheet usually gives the value in units of charge (usually nanocoulombs) for different drain-source voltages. Choose the
drain-source voltage closest to the particular de bus voltage
of interest.
Simply substituting the actual MOSFETs for the capaCitors,
CL, doesn't yield the correct average current because the
Miller capaCitance will not be accounted for. This is because
the drains don't switch using the test circuit shown In Figure
8. Also the gate capacitance of the devices you are using
may not represent the maximum values which only the data
sheet will provide.
i
8
:!
50
20
10
iii
5
w
2
~
0.5
!
~ 0.2
0.1
V /: /:
V- V
V- , / V
V- , / , /
.....
V V, / V-
~
V
~.
1
""
""
2
V-
.,
,
1o,OOOpF
3,OOOpF
1,OOOpF
100pF
.....
"'"
.L
5
10 20 50 100 200 500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 9. LOW VOLTAGE BIAS CURRENT VI FREQUENCY
AND LOAD CAPACITANCE
High Voltage Power Dissipation
The high voltage power dissipation component is largely
comprised of the high voltage level-shifter component as
described by Equation 6. All of the difficulties associated
with the time variance of the ION and IOFF pulses and the
level shift voltage, VSHIFT, under the integrand in Equation 6
are avoided. For completeness, the total loss must include a
small leakage current component, although the laHer is usually smaller compared to the level-shifter component. The
high voltage power loss calculation is the product of the high
voltage bus voltage /evel, V sus, and the average high voltage bus current, lsus, as measured by the circuit shown in
Figure 10. Averaging meters should be used to make the
measurements.
11-248
Application Note 9324
Minimize the series inductance In the gate drive loop by running the lead going out to the gate of the MOSFETs from the
IC over the top of the return lead from the MOSFET sources
back to the IC by using a double-sided PCB if possible. The
PC board separates the traces and provides a small amount
of capacitance as well as reducing the loop inductance by
reducing the encircled area of the gale drive loop. The benefit Is that the gate drive currents and voltages are much less
prone to ringing which can similarly modulate the drain current of the MOSFET. The following table summarizes some
of the layout problems which can occur and the corrective
action to take.
n.rL.11
Layout Problems and Effects
The Bootstrap circuit path should also be short to minimize
series inductance that may cause the voltage on the bootstrap capacitor to ring, slowing down refresh or causing an
overvoltage on the bootstrap bias supply.
CL. GATE LOAD CAPACITANCE
FIGURE 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST
CIRCUIT
Figure 11 shows that the high voltage level-shift current varies directly with switching frequency. This result should not
be surprising, since Equation 6 can be re-arranged to show
the current as a function of frequency, which is the reciprocal
of the switching period, 1rr. The test circuit of Figure 10
measures quiescent leakage current as well as the switching
component. Notice that the current increases somewhat with
applied bus voltage. This is due to the finite output resistance of the level-shift transistors in the IC.
1000
500
~
~
V
v
f'
~~
---r- -?
V
~ r.....
i"'"
............
........
2
2
15
10
A compact power circuit layout (short circuit path between
upperl10wer power switches) minimizes ringing on the phase
lead(s) keeping BHS and AHS voltages from ringing excessively below the Vss terminal which can cause excessive
charge extraction from the substrate and possible malfunction of the IC.
Excessive gate lead lengths can cause gale voltage ringing
and subsequent modulation of the drain currenl, thereby
amplifying the Miller Effect.
PROBLEM
EFFECT
BooIstrap circuit path
too long
Inductance may cause voltage on bootstrap capacitor to ring, slowing down
refresh and/or causing an overvoltage
on the bootstrap bias supply.
Lack of tight power
circuit layout (long
circuit path belWean
upperllower
power
Switches)
Can cause ringing on the phase lead(s)
causing BHS and AHS to ring excesslvely below the V55 terminal causing
excessive charge extraction from the
substrata and possible malfunction of
theiC.
Excessive gate lead
lengths
Can cause gate voltage ringing and
subsequent modulation of the drain current and Impairs the effectiveness of the
sink driver from minimizing the miller effect when an opposing switch is being
rapidly tumed on.
80V
-- 80V
---- .cov
-aov
ao
50
100 200
1500 1000
SWITCHING FREQUENCY (KHz)
FIGURE 11. HIGH VOLTAGE LEVEL-SHIFT CURRENT VS
FREQUENCY AND BUS VOLTAGE
Layout Issues
In fast switching, high frequency systems, poor layout can
result in· problems. It is crucial to consider PCB layout. The
HIP4080 pinout configuration encourages tight layout by
placing the gate drive output terminals strategically along the
right side of the chip (pin 1 is in the upper left-hand corner).
This provides for short gate and source return leads connecting the IC with the power MOSFETs.
11-249
Application Note 9324
Quick Help Table
Application Demonstration PC Board
The quick help table has been included to help locate solutions to problems you may have in applying the HIP4080.
Harris has developed a demonstration PC board to allow
fast prototyping of numerous types of applications. The
board was also tailored to be used to aid in characterizing
the HIP4080 and HIP4081 devices under actual operating
conditions.
PROBLEM
EFFECT
Low chip bias voltages May cause power MOSFETs to exhibit ex(Vee and Voo)
cesslve ROSON , possibly overheatlng
them. below about 6V, the IC may not
functlon properly.
High chip bias voltag- At Voo voltages above about 12V, The
es (Vee and Voo)
charge pump Umiter will begin to operale,
In turn drawing heavier Voo currenl.
above 16V, Breakdown may occur.
Bootslrap capacRor(s)
100 smaU
May cause .Insufficient or soft charge delivery 10 MOSFETs al turn-on causing
MOSFET overheating. Charge pump wHl
pump charge, bul possibly not quickly
enough 10 avoid excessive switching losses.
Bootstrap capacRor(s)
Dead time may need to be Increased In order to allow sufficient bootstrap refresh
time. The alternative Is 10 decrease boolstrap capacitance.
100 large
RGATE 100 small
RaATE 100
large
SmaUer values of RaATE reduces turn-onl
off times and may cause excessive ami
problems. Incorporating a series gate
resistor wllh an anti-parallel diode can
solve EMI problem and add 10 the dead
lime, reducing shoot-through tendency.
Increases switching losses and MOSFET
healing. If anti-paraNel diode mentioned
above Is in backwards, turn-off time Is Increased, but tum-on time Is not, possibly
causing a shoot-through fault.
Dead time too smaU
Reduces "refresh" time as wen as dead
time, with Increased shoot-through
tandency. Try increaslng HDEL and LDEL
resislors (don'l exceed 1mo.)
HIP4080 IC gets 100
hoI
Reduce bus vottage, Switching frequency,
choose a MOSFET with lower gata capacItance or reduce bias vottage (If it Is nol
below 10V to 12V).
Shed some of the low voltage gata switching losses In the HIP4080 by placing a
smaU amounl of series resistance In lhe
leads going 10 the MOSFET gates, thereby transferring some of the IC losses 10
the resistors.
Lower MOSFETs tum
on, but upper
MOSFETs don'
Check thaI the HEN terminal Is nol tied
low inadvertently.
Figure 12 and Figure 13 show the schematic and the silkscreen Indicating component placement, respectively, for the
HIP408OI1 demo board. Note that the board can be used to
evaluate either the HIP4080 or the HIP4081 , simply by
changing a few jumpers.
The PC board incorporates a CD4069UB to "buffer" inputs to
the HIP4080 on input terminals IN1 and IN2. Normally the
polarities of IN1 and IN2 should be opposite in polarity to
obtain proper H-Bridge operation. If all 4 MOSFETs are to be
PWM-ed, then JMPR3 should be removed (or opened). Also
the OUT terminal of the IC should not be driven, so insure
JMPR1 is open. Specific recommendations for working with
the HIP4081 will be discussed in the corresponding section
of the application note for the HIP4081. JMPR5 should
always be removed in order to implement the power up reset
circuit described in data sheet HIP4080, File Number 3178.
Resistors R27 and R28 as well as capacitor, C7 are not
required.
Consistent with good design practice, the +12V bias supply
is bypassed by capacitorsCS and C5 (at the IC terminals
directly). Capacitor C6 is a 4.711F tantalum, designed to
bypass the whole PCB, whereas CS is a 0.2211F. designed to
bypass the HIP4080. The bootstrap capacitors, C3 and C4,
and the high voltage bus bypass capacitors are 0.111F, 100V
ceramic. Ceramic is used here because of the low inductance required of these capacitors in the application. The
bootstrap diodes are 1A. fast recovery (tRR 200ns), 100V.
to minimize the charge loss from the bootstrap capaCitors
when the diodes become reverse-biased.
=
The MOSFETs supplied with the demo board is a Harris
IRFS20, 100V, 9A device. Since it has a gate charge of
approximately 12nC, 100 gate resistors, R21 through R24,
have been employed to deliberately slow down turn-on and
turn-off of these switches. Finally, R33 and R34 provide
adjustment of the dead-time. These are SOOka normally set
for 100ka, which will result in a dead-time of approximately
sOns. Resistors, R30 and R31 are shunt resistors (0.10, 2W,
2%, wirewound) used to provide a current-limiting signal, if
desired. These may be replaced with wire jumpers if not
required.
Finally, space has been provided for filter reactors, L1 and
L2, and filter capaCitors, C 1 and C2, to provide filtering of
PWM switching components from appearing at output terminals AO and BO. To facilitate placement of user-defined ICs,
such as op-amps, comparators, etc., space for 3 fourteen
pin standard width ICs has been reserved at the far left side
of the demo board. The output terminations of the 3 optional
locations are wired to holes which can be used to mount
application-specific components, easing the process for
building up working amplifiers for motor controls and audio
amplifiers.
11-2S0
IN2 IN1
POWER SECTION
r---------~~-----O~
+12V
CONTROL LOGIC
SECTION
R2t~ ?---;r--I+
",~I
JMPR1'
12)0
A
,
6-L
OUTIBU
DRIVER SECTION
Ice
HlP4080181
U1
=
BHB
A
Cl
R21
CR2
R22
C4
----aHOl20
IHENlBHI BHS 18
~____~3~.~S
Jr,t~II~.JAU
12)0
6
CD4068UB
12)0
v
12)0 •w
I\:,
~
,
JUPR3
,;
HENlBHI
6
BLO~1~8______~~~
- Va
BLS~1~7_-..,.,...,
~ OUTIBU VDO 1.
~
R33 I
AM
cw
cw
• IN+lAU
7 lNo/Ali
Vee 15
ALS 14
8 HDEL
LDEL
10 AHB
ALO~1~3+-+-+....I
Jr,tPf14
66 IN-IAHI
CD4068UB
AHS~1~2-+--+-+~
AD
R23
Q2
BO
I
:g:b
R24
ALO 11
CAl
~
C3
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g
R31
C5~
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~
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~
FIGURE 12. HIP4080 EVALUATION PC BOARD SCHEMATIC
APPLICATION
NOTES
~
~
BLS
NOTE: Circuit Inside dashed area rrust be
hardwired and Is not included on the
demo board.
* ··0· ·
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FIGURE 13. EVALUATION BOARD SILKSCREEN
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*
Harris Semiconductor
--
--
~
--
--
-~
=
=
----- -
No. AN9325
~
---
Harris Intelligent Power
April1994
HIP4081, 80V HIGH FREQUENCY H-BRIDGE DRIVER
Author: George E. Danz
Introduction
The HIP4081 is a member of the HIP408X family of High
Frequency H-Bridge Driwr ICs. A simplified block diagram of
the HIP4081 application is shown in Figure 1. The HIP408X
family of H-Bridge driver ICs provide the ability to operate
from 8VDC to 80VDC busses for driving N-channel MOSFET H-Bridges, operating in class-D switch-mode. The
HIP408X family, packaged in both 20 pin DIP and 20 pin
SOIC DIPs, provide peak gate current drive of 2.5A.
The biggest difference between the HIP4080 and the
HIP4081 is that the HIP4081 allows separate and individual
control of the 4 MOSFET gates, whereas the HIP4080 does
not. Also the HIP4081 does not include an internal comparator which can create a PWM signal directly within the
HIP4080.
A combination of bootstrap and charge-pumping techniques
is used to power the circuitry which drives the upper halves
of the H-Bridge. The bootstrap technique supplies the high
instantaneous current needed for turning on the power
devices, while the charge pump provides enough current to
"maintain" bias voltage on the upper driver sections and
MOSFETs. Since voltages on the upper bias supply pin
"floaf along with the source terminals of the upper power
switches, the design of this family provides voltage capability
forlhe upper bias supply terminals to 95VDC.
The HIP4081 can drive lamp loads for automotiw and industrial applications as shown in Figure 2. When inductive loads
are switched, flyback diodes must be placed around the
loads to protect the MOSFET switches.
Many applications utilize the full bridge topology. These are
voice coil motor drives, stepper and DC brush motors, audio
amplifiers and ewn power supply inverters used in uninterruptable power supplies, just to name a few. The HIP408X
family of devices is fabricated using a proprietary Harris IC
process which allows this family to switch at frequencies up
to 1MHz. Therefore the HIP408X family is ideal for use in all
kinds of class-D high frequency conwrter applications.
Two resistors tied to pins HDEL and LDEL can provide precise delay matching of upper and lower propagation delays,
which are typically only 55ns. The result is accurate deadtime control for avoiding shoot-through and for maximizing
the duty-cycle. The HIP4081 H-Bridge driver has enough
voltage margin to meet all SELV (UL classification for operation at ~ 42.0V) applications and most Automotive applications where "load dump" capability OII9r 65V is required. The
HIP408X family is a cost-effective solution for driving Nchannel power MOSFETs, replacing discrete solutions or
other solutions relying on transformer- or opto-coupling gatedriw techniques, as shown in Figure 1.
Copyright @Harrls Corporation 1994
11-253
GND
GND
FIGURE 1. HIP4081 SlMPUFIEDAPPLlCATION DIAGRAM
. DUAl HIGHILOW SWITCHES FOR
AUTOMOTIVE AND INDUSTRIAL CONTROLS
HIP4081
FIGURE 2. HIP4081 AS LAMP SWITCH DRIVER
Application Note 9325
Description of the HIP4081
The block diagram of the HIP4081 relating to driving the
A-side of the H-Bridge is shown in Figure 3. The blocks
associated with each half of the H-Bridge are identical, so
the B-side is not shown for simplicity.
The Vee and Voo terminals on the HIP4081 should be tied
together. They were separated within the HIP4081 IC to
avoid possible ground loops internal to the IC. Tieing them
together and providing a cIecoupling capacitor from the common tie-point to Vss greatly improves noise immunity.
Input Logic
The HIP4081 has 4 inputs, AU, BU, AHI and BHI, which control the gate outputs of the H-bridge. In addition, the DIS, "Disable," pin disables gate drive to all H-bridge MOSFETs
regardless of the command states of the input pins above.
The HIP4081 has pullups on the high input terminals, AHI and
BHI, so that the bridge can be totally controlled using only the
lower input control pins, AU and BU, which can greatly simplifiy the external control circu~ry needed to control the
HIP4081. As Table 1 suggests, the lower inputs All and BU
dominate the upper inputs. That is, when one of the lower
nputs is high, ~ doesn't matter what the level of the upper
input is. because the lower will turn on and the upper will
remain off.
power switches. The HDEL resistor controls both upper commutation delays and the LDEL resistor controls the lower
commutation delays. Each of the resistors sets a current
which is inversely proportional to the created delay. The
delay is added to the falling edge of the "off" pulse associated with the MOSFET which is being commutated off.
When the delay is complete, the "on" pulse is initiated. This
has the effect of "delaying" the commanded on pulse by the
amount set by the delay, thereby creating dead-time.
Proper choice of resistor values connected from HDEL and
LDEL to Vss provides a means for matching the commutation dead times whether commutating high to low or low to
high. Values for the resistors ranging from 10kn to 200k1J
are recommended. Figure 4 shows the delays obtainable as
a function of the resistor values used.
150
120
L
30
TABLE 1. INPUT lOGIC TRUTH TABLE
AU,BU
AHI,BHI
DIS
X
X
1
AlO,BlO
AHO,BHO
0
0
1
X
0
1
0
0
1
0
0
1
0
0
0
0
0
X
=DON'T CARE
1
=HIGH/ON
0
o
V
10
./
50
V"
L
V
L
~
100
150
200
HDELILDEL RESISTANCE (lin)
250
FIGURE 4. MINIMUM DEAD-TIME VI DEL RESISTANCE
Level-Translat/on
=lOW/OFF
The input sens~iv~y of the DIS input pin is best described as
"enhanoed TIl: levels. Inputs which fall below 1.0V or rise
above 2.5V are recognized, respectively, as low level or high
level inputs.
Propagation Delay Control
Propagation delay control is a major feature of the HIP4081.
Two identical sub-circuits w~hin the IC delay the commutation of the power MOSFET gate turn-on signals for both A
and B sides of the H-bridge. The gate turn-off signals are not
delayed. Propagation delays related to the level-translation
function (see section on Level-Translation) cause both upper
on/off propagation delays to naturally be longer than the
lower onIoff propagation delays. Four delay trim sub-circu~s
are incorporated to better match the H-bridge delays, two for
upper delay control and two for lower gate control.
Users can tailor the low side to high side commutation delay
times by placing a resistor from the HDEL pin to the Vss pin.
Similarly, a resistor connected from LDEL to Vss controls the
high side to low side commutation delay times of the lower
The lower power MOSFET gate drive Signals from the propagation delay and control circuits go to amplification circuits
which are described in more detail under the section "Driver
Circuits". The upper power MOSFET gate drive signals are
directed first· to the Level-Translation circuits before going to
the upper power MOSFET "Driver Circuits".
The Level-Translation circuit communicate "on" and 'off"
pulses from the Propagation Delay sub-circuit to the upper
logic and gate drive sub-circuits which "float" at the potential
of the upper power MOSFET source connections. This voltage can be as much as 85V when the bias supply voltage is
only 10V (the sum of the bias supply voltage and bus voltages must not exceed 95VDC).
In order to minimize power dissipation in the level-shifter circuit, it is important to minimize the width of the pulses translated because the power dissipation is proportional to the
product of switching frequency and pulse energy in joules.
The pulse energy in turn is equal to the product of the bus
voltage magnitUde, translation pulse current and translation
pulse duration. To provide a reliable, noise free pulse
requires a nominal current pulse magnitude of approximately
3mA. The translated pulses are then "latched" to maintain
the "on" or ·off" state until another level-translation pulse
11-254
Application Note 9325
HIGH VOLTAGE BUS s IIVDC
TO YIlO (PIN 16)
=
+12YDC
BIAS
SUPPLY
FIGURE 3. HIP4081 FUNCTIONAL BLOCK DIAGRAM
comes along to set the latch to the opposite state. Very reliable operation can be obtained with pulse widths of approximately BOns. At a switching frequency of even 1.0MHz, with
an aoVDC bus potential, the power developed by the leveltranslation circuit will be less than O.08W.
Charge Pump Circuits
There are two charge pump circuits in the HIP4081, one for
each of the two upper logic and driver circuits. Each charge
pump uses a switched capacitor doubler to provide about
3011A to SOIlA of gate load current. The sourcing current
charging capability drops off as the floating supply voltage
increases. Eventually the gate voltage approaches the level
set by an internal zener clamp, which prevents the voHage
from exceeding about 15V, the safe gate voltage rating of
most commonly available MOSFETs.
Driver Circuits
Each of the four output drivers are comprised of bipolar high
speed NPN transistors for both sourcing and sinking gate
charge to and from the MOSFET switches. In addition, the
sink driver incorporates a parallel-connected n-chaMel
MOSFET to enable the gate of the power switch gate-source
voltage to be brought completely to OV.
The propagation delays through the gate driver sub-circuits
while driving 500pF loads is typically less than 1Ons. Nevertheless, the gate driver design nearly eliminates all gate
driver Shoot-through which SignifICantly reduces IC power
dissipation.
Application Considerations
To successfully apply the HIP4081 the deSigner should
address the following concerns:
• General Bias Supply Design Issues
•
Upper Bias Supply Circuit Design
•
Bootstrap Bias Supply Circuit Design
General Bias Supply Design Issues
The bias supply design is simple. The designer must first
establish the desired gate voltage for turning on the power
switches. For. most power MOSFETs, increasing the gatesource voltage beyond 10V yields little reduction in switch
drain-source voltage drop.
Overcharging the power switch's gate-source capacitance
also delays turn-off, increases MOSFET switching losses
and increases the power dissipation of the HIP4081. Overcharging the MOSFET gate-source capacitance also can
lead to "shoot-through" (both upper and lower. MOSFETs in
a single bridge leg find themselves conducting simultaneously), thereby shorting out the high voltage DC. Bias
supply voltages from 12V to 150V are optimum for Voo and
Vee·
Lower Bias Supply De81gn
Since most applications use identical MOSFETs for both
upper and lower power switches, the bias supply requirements with respect to driving the MOSFET gates will also be
identical. In case switching frequencies for driving upper and
11-255
z
o
-en
!;iw
()I-0
~z
0c:(
Application Note 9325
lower MOSFETs differ, two sets of calculations must be
done; one for the upper switches and one for the lower
switches. The bias current budget for upper and lower
switches will be the sum of each calculation. Keep in mind
that the lower bias supply must also supply current to the
upper gate driw and logic circuits. because the low side bias
supplies fYcdVoo) charge the bootstrap capacitors and the
charge pumps.
Capacitor bypassing of Vee and Voo avoids transient voltage dips of the bias power supply to the HIP4081. Always
place a low ESR (equivalent series resistance) ceramic
capacitor adjacent to the IC, connected between the bias
terminals Vee and Voo and the common terminal, Vss of the
IC. A value in the range of 0.221LF and 0.51LF is usually sufficient.
Minimize the effects of Miller feedback by keeping the source
and gate return leads from the MOSFETs to the HIP4081
short. This also reduces ringing, by minimizing the inductance of these connections. Another way to minimize inductance in the gate charge/discharge path, in addition to
minimizing path length, is to run the outbound gate lead
directly "over" the source return lead. Sometimes the source
return leads can form a small "ground plane" on the back
side of the PC board making it possible to run the outbound
gate lead "topside" on the pc board over this ground plane.
This minimizes the "enclosed area" of the loop, thus minimizing inductance in this loop. It also adds some capacitance
between gate and source which reduces the Miller feedback
effect.
Upper Bias Supply Circuit Design
Before discussing bootstrap circuit design in detail, it is
worth mentioning that it is possible to operate the HIP4081
without a bootstrap circuit altogether. Even the bootstrap
capacitor, which functions to supply a reservoir of charge for
rapidly turning on the MOSFETs is optional in some cases.
In situations where wry slow turn-on of the MOSFETs is tolerable, one may consider omitting some or all bootstrap
components. Applications such as driving relays or lamp
loads, where the MOSFETs are switched infrequently and
switching losses are low, may provide opportunities for boot
strapless operation. Generally, loads with lots of resistance
and inductance are possible candidates.
Operating the HIP4081 without a bootstrap diode andlor
capaCitor will severely slow gate turn-on. Without a bootstrap
capaCitor, gate current only comes from the internal charge
pump. The peak charge pump current is only about 301LA to
501LA. The gate voltage waveform, when operating without a
bootstrap capacitor, will appear similar to the dotted line
shown in Figure 6.
I! a bootstrap capaCitor value approximately equal to the
equivalent MOSFET gate capacitance is used, the upper
bias supply (labeled "bootstrap voltage" in Figure 5) will drop
approximately in half when the gate is turned on. The larger
the bootstrap capacitance used, the smaller is the instantaneous drop in bootstrap supply voltage when an upper
MOSFET is turned on.
'~~NI
SIGNAL
BOOT STRAP
(XV:-~~)
GATE VOLTAGE
(XHO-XHS)
I
I
---+----..J.I----I
-----------------
tl-_-I.
I
~---------
------------------~----~----...................-.....--
FIGURES.
Although not recommended, one may employ a bootstrap
capacitor without a bootstrap diode. In this case the charge
pump is used to charge up a capaCitor whose value should
be much larger than the equivalent gate-source capacitance
of the driven MOSFET. A value of bootstrap capacitance
about 10 times greater than the equivalent MOSFET gatesource capacitance is usually sufficient. Provided that sufficient time elapses before turning on the MOSFET again, the
bootstrap capacitor will have a chance to recharge to the
voltage value that the bootstrap capacitor had prior to turning on the MOSFET. Assuming 20 of series resistance is in
the bootstrap change path, an output frequency of up
to
1
should allow sufficient refresh time.
5 X2QXC sS
A bootstrap capaCitor 10 times larger than the equivalent
gate-source capacitance of the driven MOSFET prevents the
drop in bootstrap supply voltage from exceeding 10% of the
bias supply voltage during turn-on of the MOSFET. When
operating without the bootstrap diode the time required to
replenish the charge on the bootstrap capaCitor will be the
same time as it would take to charge up the equivalent gate
capacitance from OV. This is because the charge lost on the
bootstrap capacitor is exactly equal to the charge transferred
to the gate capacitance during turn-on. Note that the very
first time that the bootstrap capacitor is charged up, it takes
much longer to do so, since the capacitor must be charged
from OV. W~h a bootstrap diode, the initial charging of the
bootstrap supply is almost instantaneous, since the charge
required comes from the low-side bias supply. Therefore,
before any upper MOSFETs can initially be gated, time must
be allowed for the upper bootstrap supply to reach full voltage. Without a bootstrap diode, this initial "charge" time can
be excessive.
I! the switching cycle is assumed to begin when an upper
MOSFET is gated on, then the bootstrap capaCitor will
undergo a charge withdrawal when the source driver connects it to the equivalent gate-source capacitance of the
MOSFET. After this initial "dump" of charge, the quiescant
current drain experienced by the bootstrap supply is infinitesimal. In fact, the quiescent supply current is more than
offset by the charge pump current.
11-256
Application Note 9325
The charge pump continuously supplies current to the boot- not fully charged by the time the upper MOSFET turns on
strap supply and eventually would charge the bootstrap again, incomplete refreshing occurs. The designer must
capacitor and the MOSFET gate capacitance back to its ini- . insure that the dead-time setting be consistent with the size
tial value prior to the beginning of the switching cycle. The of the bootstrap capacitor in order to guarantee complete
problem is that 'eventually" may not be fast enough when the refreshing. Figure 6 illustrates the circuit path for refreshing
switching frequency is greater than a few hundred Hz.
the bootstrap capacitor.
HIGH VOLTAGE BU~•••~!!!!!,
Bootstrap Blaa Supply Circuit Design
TO "B-SlDe"
OF
H-BRIDGE
For high frequency applications all bootstrap components,
both diodes and capacitors, are required. Therefore, one
must be familiar with bootstrap capacitor sizing and proper
choice of bootstrap diode.
Just after the switch cycle begins and the charge transfer
from the bootstrap capacitor to the gate capacitance is complete, the voltage on the bootstrap capacitor is the lowest
that it will ever be during the switch cycle. The charge lost on
the bootstrap capacitor will be very nearly equal to the
charge transferred to the equivalent gate-source capacitance of the MOSFET as shown in Equation 1.
0G
= (VBS1 -
V BS2 ) X CBS
(EO.1)
TO "B-SlDe"
SUPPLY
BYPASS
CAPACITOR
where:
V BS1= Bootstrap capacitor \/Oitage just after refresh
VBS2= Bootstrap voltage immediately after upper turn-on
CBS = Bootstrap Capacitance
OG
In PWM switch-mode, the switching frequency is equal to the
reciprocal of the period between successive turn-on (or turnoff) pulses. Between any two turn-on gate pulses exists one
turn-off pulse. Each time a turn-off pulse is issued to an
upper MOSFET, the bootstrap capacitor of that MOSFET
begins its "refresh" cycle. A refresh cycle ends when the
upper MOSFET is turned on again, which varies depending
on the PWM frequency and duty cycle. As the duty cycle
approaches 100%, the available 'off-time", loFF approaches
zero. Equation 2 shows the relationship between IoFF> fPWM
and the duty cycle.
tOFF
NOTE: Only "A-side" 01 H-bridge Is Shown for Simplicity.
Arrows Show Bootstrap Charging Path.
= Gate charge transferred during turn-on
Were it not for the internal charge pump, the voltage on the
bootstrap capacitor and the gate capacitor (because an
upper MOSFET is now turned on) would eventually drain
down to zero due to bootstrap diode leakage current and the
very small supply current associated with the level-shifters
and upper gate driver sub-circuits.
= (1 -
DC) IfpWM
(EO.2)
As soon as the upper MOSFET is turned off, the voltage on
the phase terminal (the source terminal of the upper MOSFET) begins its descent toward the negative rail of the high
voltage bus. When the phase terminal \/Oltage becomes less
than the Vee \/Oltage, refreshing (charging) of the bootstrap
capaCitor begins. As long as the phase voltage is below Vee
refreshing continues until the bootstrap and Vee \/Oitages
are equal.
The off-time of the upper MOSFET is dependent on the gate
control input signals, but it can never be shorter than the
dead-time delay setting, which is set by the resistors connecting HDEL and LDEL to Vss. If the bootstrap capacitor is
OF
H-BRIDGE
FIGURE 6. BOOTSTRAP CAPACITOR CHARGING PATH
The bootstrap charging and discharging paths should be
kept short, minimizing the inductance of these loops as mentioned in the section, 'Lower Bias Supply Design".
Bootstrap Circuit Design· An Example
Equation 1 describes the relationship between the gate
charge transferred to the MOSFET upon turn-on, the size of
the bootstrap capacitor and the change in voltage across the
bootstrap capacitor which occurs as a result of turn-on
charge transfer.
The effects of reverse leakage current associated with the
bootstrap diode and the bias current associated with the
upper gate drive circuits also affect bootstrap capacitor sizing. At the instant that the upper MOSFET turns on and its
source \/Oltage begins to rapidly rise, the bootstrap diode
becomes rapidly reverse biased resulting in a reverse recovery charge which further depletes the charge on the bootstrap capacitor. To completely model the total charge
transferred during turn-on of the upper MOSFETs, these
effects must be accounted for, as shown in Equation 3.
z
o
-tJ)
t;cw
itz
ll.
(.)1-
-0
under the integrand in Equation 6
are avoided. For completeness, the total loss must include a
small leakage current component, although the latter is usu·
ally smaller compared to the level·shifter component. The
11-259
Application Note 9325
high voltage power loss calculation is the product of the high
voltage bus voltage level. VBUS• and the average high voltage bus current. IBUS• as measured by the circuit shown in
Figure 9. Averaging meters should be used to make the
measurements.
12V
Layout Problems and Effects
In fast switching. high frequency systems. proper PC board
layout is crucial. to consider PCB layout. The HIP4081
pinout configuration encourages tight layout by placing the
gate drive output terminals strategically along the right side
of the chip (pin 1 Is in the upper left-hand corner). This provides for short gate and source return leads connecting the
IC with the power MOSFETs.
Always minimize the series inductance in the gate drive loop
by running the gate leads to the MOSFETs over the top of
the source return leads of the MOSFETs. A double-sided
PCB makes this easy. The PC board separates the traces
and provides a small amount of capacitance as well as
reducing the loop inductance by redUCing the encircled area
of the gate drive loop. The result is reduced ringing which
can similarly reduce drain current modulate in the MOSFET.
The table below summarizes some layout problems which
can occur and the corrective action to take.
n.rt -"---+-f8l
Vaus
(OVDC TO 80VDC)
The Bootstrap circuit path should also be kept short. This
minimizes series inductance that may cause the voltage on
the boot-strap capacitor to ring. slowing down refresh or
causing an overvoltage on the bootstrap bias supply.
T
V
CL. GATE LOAD CAPACITANCE
FIGURE 9. HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST
CIRCUIT
Figure 10 shows that the high voltage level-shift current varIes directly with switching frequency. This result should not
be surprising. sinea Equation 6 can be re-arranged to show
the current as a function of frequency. which is the reciprocal
of the switching period. 1rr. Notice that the current increases
somewhat with applied bus voltage. This is due to the finite
output resistance of the level-shift transistors in the IC.
1000
A compact power circuit layout (short circuit path between
upperllower power switches) minimizes ringing on the phase
lead(s) keeping BHS and AHS voltages from ringing excessively below the Vss terminal which can cause excessive
charge extraction from the substrate and possible malfunction of the IC.
PROBLEM
EFFECT
Bootstrap clrcult path
too long
strap capacitor to ring. slowing down
refresh and/or causing an overvoltage
on the bootstrap bias supply.
~
500
/
~
~
~
~~
-- ----:;;.-
::::.--: '?<
---
'"
2
~
............
lOY
Lack of tight power
circuit layout (long
circuit path between
upperllo_
power
switches)
Can cause ringing on the phase lead(s)
causing BHS and AHS to ring excesslvely below the Vss terminal causing
excessive charge extraction from the
substrate and possible malfunction of
theiC.
Excessive gate lead
lengths
Can cause gate voltage ringing and
subsequent modulation of the drain cur·
rent and impairs the effectiveness of the
sink driver from minimizing the miller ef·
fect when an opposing switch Is being
rapidly tumed on.
lOY
-........ 40Y
-2OY
10 20
80 100 200
SWITCHING FREQUENCY (kHz)
Ii
Inductance may cause voltage on boot-
500 1000
FIGURE 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT va
FREQUENCY AND BUS VOLTAGE
11-260
Application Note 9325
Quick Help Tab/e
Application Demonstration PC Board
The quick help table has been included to help locate solutions to problems you may have in applying the HIP4081.
Harris has dell9loped a demonstration PC board to allow fast
prototyping of numerous types of applications. The board
was also tailored to be used to aid in characterizing the
HIP4081devica under actual operating conditions.
PROBLEM
EFFECT
Low chip bias voltages May cause power MOSFETs to exhibit excessive ROSON , possibly overheating
(Vcc and Voo)
them. Below 6V, the IC will not function
properly.
High chip bias voltag- At Voo voltages above about 12V. The
charge pump limiter will begin to operate,
es (Vee and Voo)
in turn drawing heavier Voo current.
Above 16V, breakdown may occur.
Bootstrap capacltor(s)
too small
May cause Insufficient or soft charge d&livery to MOSFETs at turn-on causing
MOSFET overheating. Charge pump will
pump charge, but possibly not quickly
enough to avoid excessive switching 1osses.
Bootstrap capacitor(s)
too large
Dead time may need to be lnereased In order to allow sufficient bootstrap refresh
time. The alternative is to dacrease bootstrap capacitance.
RelATE too small
Smaller values of RelATE reduces turn-oni
off times and may cause excessive ami
problems. Incorporating a series gate
resistor with an anti-parallel diode can
solve EMI problem and add to the dead
time, reducing shoot-through tendency.
RelATE too large
Increases switching losses and MOSFET
heating. II anti-parallel diode mentioned
above is In backwards, turn-off time is increased, but turn-on time is not, possibly
causing a shoot-through fault.
Dead time too small
Reduces 'Tefresh" time as weB as dead
time, with Increased shoot-through
tendency. Try increasing HDEL and LDEL
resistors (don't exceed 1mOl.
HIP4081 IC gets too
hot
Reduce bus voItaga, switching frequency,
choose a MOSFET with lower gate capacItanca or reduca bias voltage (lilt is not
below 6V to 12V). Shed some 01 the low
voltage gate switching losses In the
HIP4081 by placing a small amount of series resistance In the leads going to the
MOSFET gates, thereby transferring
some of the Ie losses to the resistors.
Lower MOSFETs turn
on, but upper
MOSFETs don'
Check that the HEN terminal is not tied
low Inadvertendy.
Figure 11 and Figure 12 show the schematic and the silkscreen Indicating component placement, respectively, for the
HIP408OI81 demo board. Note that the board can be used to
evaluate either the HIP4080 or the HIP4081 , simply by
changing a few jumpers. Refer to the appropriate application
note for instructions on jumber placement.
The PC board incorporates a CD4069UB to "buffer" inputs to
the HIP4081. JMPR5, reSistors R27 and R28, and capaCitor
C7 must be remoll9d in order to implement the power up
reset circuit described in this application note and in the
HIP4081 data sheet, File Number 355S.
Consistent with good design practice, the +12V bias supply
is bypassed by capaCitors CS and C5 (at the IC terminals
directly). Capacitor CS is a 4.711F tantalum, designed to
bypass the whole PCB, whereas C5 is a 0.22J!F. designed to
bypass the HIP4081. The bootstrap capacitors, C3 and C4,
and the high voltage bus bypass capacitors are O.I!!F, l00V
ceramic. Ceramic is used here because of the low inductance required of these capacitors in the application. The
bootstrap diodes are 1A, fast recoll9ry (tAR 200ns), l00V,
to minimize the charge loss from the bootstrap capacitors
when the diodes become reverse-biased.
=
The MOSFETs supplied with the demo board Is a Harris
IRF520, looV, 9A device. Since it has a gate charge of
approximately 12nC, Ion gate resistors, R21 through R24,
have been employed to deliberately slow down turn-on and
turn-off of these switches. Finally, R33 and R34 provide
adjustment of the dead-time. These are 5001<0 normally set
for lookn, which will result in a dead-time of approximately
5Ons. Resistors, R30 and R31 are shunt resistors (0.10, 2W,
2%, wirewound) used to provide a current-limiting signal, if
desired. These may be replaced with wire jumpers if not
required.
Finally, space has been provided for filter reactors, L 1 and
L2, and filter capacitors, Cl and C2, to provide filtering of
PWM switching components from appearing at output terminals N:) and BO. To facilitate placement of user-defined ICs,
such asop-amps, comparators, etc., space for 3 fourteen pin
standard width ICs has been reserved at the far left side of
the demo board. The output terminations of the 3 optional
locations are wired to holes which can be used to mount
application-specifIC components, easing the process for
building up working amplifiers for motor controls and audio
amplifiers.
11-2S1
1M2 IN1
PC7NER SEenON
+12V
CONTROL LOGIC
SEcnoN
~
-~~--IT-_-,--~~I
~~CI
_I
.. I 6'
r---------~~----O~
R21
DRIVER SEenON
CRZ
H1P408CII81
U1
C4
iiiOI20
R22
xxxx
t xxxx ,
0
NJ
0
BO
:to.
:g
~
Q)
-~
[
RZ4
~
Cit
CR1
CO
o........--iF
C04068UB
CY
cs~
BLS
NOTE:
DEVICE CD4on1JB PIN 7 • COM, PIN 14. +12V.
C04068UB
FIGURE 12. HIP4081 EVALUATION PC BOARD SCHEMATIC
~
R31
I'
ALS
TO DIS PIN
R30
eli
o COM
*......0...... . *
.. .... .... .. .
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--------
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Harris Intelligent Power
Aprill994
HIP4080A, 80V HIGH FREQUENCY H-BRIDGE DRIVER
Author: George E. Danz
Introduction
The HIP4080A is a member of the HIP408X family of High
Frequency H-Bridge Driver ICs. A simplified application diagram of the HIP4080A IC is shown in Figure 1. The HIP408X
family of H-Bridge driver ICs provide the ability to operate
from 10VDC to OOVDC busses for driving H-Bridges, operating in class-D switch-mode, whose switch elements are comprised of power N-channel MOSFETs. The HIP408X family,
packaged in both 20 pin DIP and 20 pin SOIC DIPs, provide
peak gate current drive of 2.5A. The HIP4000A includes
undervoltage protection, which sends a continuous gate
turn-off pulse to all gate outputs when the Voo voltage falls
below a nominal B.25 volts. The startup sequence of the
HIP4000A is initiated when the Voo voltage returns above a
nominalB.75 volts. Of course, the DIS pin must be in the low
state for the IC to be enabled. The startup sequence turns
on both low side outputs, ALO and BLO, so that the bootstrap capacitors for both sides of the H-bridge can be fully
charged. During this time the AHO and BHO gate outputs
are held low continuously to insure that no shoot-through
can occur during the nominal 400ns boot-strap refresh
period. At the end of the boot strap refresh period the outputs respond normally to the state of the input control signals.
A combination of bootstrap and charge-pumping techniques
is used to power the circuitry which drives the upper halves
of the H-Bridge. The bootstrap technique supplies the high
instantaneous current needed for turning on the power
devices, while the charge pump provides enough current to
"maintain" bias voltage on the upper driver sections and
MOSFETs. Since voltages on the upper bias supply pin
"floar along with the source terminals of the upper power
switches, the design of this family provides voltage capability
for the upper bias supply terminals to 95VDC.
motor drivers, can be implemented as shown in Figure 3. In
the figure, R3 is fed back from the comparator output, OUT,
to the positive input of the comparator, IN+. Capacitor, Cl,
integrates in a direction to satisfy the reference current signal at IN. The IN- input of the comparator sums this current
reference with a signal proportional to load current through
resistor, R4, which comes from a differential amplifier, A 1. A
bias voltage of 6V (represents half of the bias voltage and
the maximum rail to rail voltage of the comparator and amplifier, Al) biases the comparator's IN+ terminal through R2
and the amplifier, A l's, positive summing junction.
QND
FIGURE 1. HIP4080A SlMPUFIED APPUCATION DIAGRAM
+lOY
---.
The HIP4080A can drive lamp loads for automotive and
industrial applications as shown in Figure 2. When inductive
loads are switched, flyback diodes must be placed around
the loads to protect the MOSFET switches.
Many applications utilize the full bridge topology. These are
voice coil motor drives, stepper and DC brush motors, audio
amplifiers and even power supply inverters used In uninterruptable power supplies, just to name a few. Of the above,
voice coil motor drives and audio amplifiers can take advantage of the built-in comparator available in the HIP4080A.
Using the output of the comparator to add some positive
feedback, a hysteresis control, so popular with voice coil
GND
HIP408X
·•
••
-... _'
---.
••
•
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•
--,
••
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---'
--.
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--~
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FIGURE 2. HIP4080A AS LAMP SWITCH DRIVER, DUAL HIGHt
LOW SWITCHES FOR AUTOMOTIVE AND INDUS-
Copyright @ Harris Corporation 1994
11-264
Application Note 9404
When no current is flowing in either direction in the load, the
output of A 1 is exactly SY. The reference input, IN, would
also hall8 to be SV to request zero current from the bridge.
The bridge would still switch In this case, because of the
positive feedback connection of the HIP4080A internal comparator. The frequency of oscillation of the output will be a
function of the amount of de hysteresis gain, R3IR1 and the
size of capacitor, C1. As the capacitor, C1, is made larger,
the steady-state frequency of the bridge will become smaller.
It is beyond the scope of this application note to provide a full
analysis. A valuable characteristic of hysteresis control is
that as the error becomes smaller (i.e. the reference and
feedback signals match) the frequency increases. Usually
this occurs when the load current is small or at a minimum.
When the error Signal is large, the frequency becomes 118ry
small, perhaps ell8n de. One advantage of this is that when
currents are largest, switching losses are a minimum, and
when switching losses are largest, the de current component
issmall.
The HIP408X family of devices is fabricated using a proprietary Harris IC process which allows this family to switch at
frequencies of oll8r 500kHz. Therefore the HIP408X family Is
ideal for use in Voice coil motor, class-D audio amplifier, DCDC converters and high performance AG, DC and stepmotor control applications.
To provide accurate dead-time control for the twin purposes
of shoot-through avoidance and duty-cycle maximization,
two resistors tied to pins HDEL and LDEL provide precise
delay matching of upper and lower propagation delays,
which are typically only 55ns. The HIP408X family of
H-bridge drill8rs has enough voltage margin to be applied to
all SELV (UL classification for operation at S 42.0V) applications and most Automotlll8 applications where "load dump"
capability over 65V is required. This capability makes the
HIP408X family a more cost-effectill8 solution for driving Nchannel power MOSFETs than either discrete solutions or
other solutions relying on transformer- or apia-coupling gatedrill8 techniques as shown in Figure 1.
The HIP4080A differs from the HIP4081A regarding the
function of pins 2, 5, Sand 7 of the IC and the truth table
which governs the switching function of the two ICs. In the
HIP4080A, pins 2, 5, 6 and 7 are labeled HEN, OUT, IN+
and IN-, respectill8ly.ln the HIP4081A, pins 2,5,6 and 7 are
labeled BHI (B-side high input), BLI (B-side low input), ALI
(A-Side low input) and AHI (A-side high input), respectively.
The HIP4081A's inputs individually control each of the four
power MOSFETs, or in pairs (excepting the shoot-through
case). The HIP4080A provides an internal comparator and a
"high enable... HEN" pin. The comparator can be used to provide a PWM logic signal to switch the appropriate MOSFETs
within the H-bridge, and can facilitate "Hysteresis' control to
be illustrated later. The HEN pin enables (when HEN is high)
or disables (when HEN is low) the A-side and B-side upper
MOSFETs. With HEN held low, it is possible to switch only
the lower H-bridge MOSFETs. When HEN is high both upper
and lower MOSFETs of the H-brldge are switched. The HEN
input can also be PWM-switched with the IN+ and IN- inputs
used only for direction control, thereby minimizing switching
losses.
Description of the HIP4080A
The block diagram of the HIP4080A relating to driving the
A-side of the H-Bridge is shown in Figure 4. The blocks
associated with each side of the H-Bridge are identical, so
the B-side is not shown for simplicity.
The two bias voltage terminals, Vee and Voo , on the
HIP4080A should be tied together. They were separated
within the HIP4080A to avoid possible ground loops internal
to the IC. Tieing them together and providing a decoupling
capacitor from the common tie-point to Vss greatly improves
noise immunity.
Input Logic
The HIP4080A accepts inputs which control the output state
of the power MOSFET H-bridge and provides a comparator
output pin, OUT, which can provide compensation or hysteresis.
The DIS, "Disable; pin disables gate drill8 to all H-bridge
MOSFETs regardless of the command states of the Input
pins, IN+, IN- and HEN. The state of the bias voltage, VoOo
also can disable all gate drive as discussed in the introduction. The HEN, "High Enable; pin enables and disables gate
drill8 to the two high side MOSFETs. A high level on the
HEN pin "enables" high side gate drill8 as further determined by the states of the IN+ and IN- comparator input
pins, since the IN+ and IN- pins control which diagonal pair
of MOSFETs are gated. Upper drive can be "modulated"
through use of the HEN pin while drill8 to diagonally opposing lower MOSFETs is continuous. To simultaneously modulate both upper and lower drill8rs, HEN is continuously held
high while modulating the IN+ and IN- pins.
Modulating only the upper switches can nearly halve the
switching losses in both the driver IC and in the lower MOSFETs. The power dissipation saved at high switching frequencies can be signifICant. Table 1 summarizes the input
control logic.
The input sensitivity of the DIS and HEN input pins are best
described as "enhanced TTL.:' lell8ls. Inputs which fall below
1.0V or above 2.5V are recognized, respectively, as low level
or high level inputs. The IN+ and IN- comparator inputs have
a common mode input voltage range of 1.0V to Voo -1.5V,
whereas the offset voltage is less than 5mY. For more information on the comparator specifications, see Harris Data
Sheet HIP4080A, File Number 3658.
TABLE 1. INPUT lOGIC TRUTH TABLE
-0
~z
IN.>
IN-
UN
DIS
HEN
AlO
AHO
BlO
BHO
X
X
1
X
0
0
0
0
X
1
X
X
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
11-265
1
0
X =DON'T CARE
1 =HIGHION
0
0
=LON/OFF
z
o
~w
()I-
-0
D-
eC
Application Nots 9404
lOY
1
•
AI
AI
ASH
RO
ASH
GND
FIGURE 3. HYSTERESIS MODE SWITCHING
HIGH VOLTAGE BUS S HYDC
AHB
AHO
AHS
TO You (PIN 16)
+12YDC
= SUPPLY
BIAS
FIGURE 4. HIP4080A BLOCK DIAGRAM
11-266
Application Note 9404
Propagation Delay Control
Propagation delay control is a major feature of the
HIP4080A. Two identical sub-circuits within the IC delay the
commutation of the power MOSFET gate turn-on signals for
both A and B sides of the H-bridge. The gate turn-off signals
are not delayed. Propagation delays related to the leveltranslation function (see section on Level-Translation) cause
both upper onloff propagation delays to be longer than the
lower on/off propagation delays. Four delay sub-circuits are
needed to fully balance the H-bridge delays, two for upper
delay control and two for lower gate control.
Users can tailor the low side to high side commutation delay
times by placing a resistor from the HDEL pin to the Vss pin.
Similarly, a resistor connected from LDEL to Vss controls the
high side to low side commutation delay times of the lower
power switches. The HDEL resistor controls both uppar commutation delays and the LDEL resistor controls the lower
commutation delays. Each of the resistors sets a current
which is inversely proportional to the created delay. The
delay is added to the falling edge of the "off" pUise associated with the MOSFET which is being commutated off.
When the delay is complete, the "on" pulse is initiated. This
has the effect of "delaying" the commanded on pulse by the
amount set by the delay, thereby creating dead-time.
Proper choice of resistor values connected from HDEL and
LDEL to Vss provides a means for matching the commutation dead times whether commutating high to low or low to
high. Values for the resistors ranging from 10kn to 200kn
are recommended. Figure 5 shows the delays obtainable as
a function of the resistor values used.
150
of the upper power MOSFET source connections. This voltage can be as much as 85V when the bias supply voltage is
only 10V (the sum of the bias supply voltage and bus voltages must not exceed 95VDC).
In order to minimize power dissipation in the level-shifter circuit, it is important to minimize the width of the pulses translated because the power dissipation is proportional to the
product of switching frequency and pulse energy in joules.
The pulse energy in turn is equal to the product of the bus
voltage magnitude, translation pulse current and translation
pulse duration. To provide a reliable, noise free pulse
requires a nominal current pulse magnitude of approximately
3mA. The translated pulses are then "latched" to maintain
the "on" or "off" state until another level-translation pulse
comes along to set the latch to the opposite state. Very reliable operation can be obtained with pulse widths of approximately SOns. At a switching frequency of even 1.0MHz, with
an 80VDC bus potential, the power developed by the leveltranslation circuit will be less than O.08W.
Charge Pump Circuits
There are two charge pump circuits in the HIP4080A, one for
each of the two upper logic and driver circuits. Each charge
pump uses a switched capacitor doubler to provide about
301lA to 501lA of gate load current. The sourcing current
charging capability drops off as the floating supply voltage
increases. Eventually the gate voltage approaches the level
set by an internal zener clamp, which prevents the voltage
from exceeding about 15V, the safe gate voltage rating of
most commonly available MOSFETs.
Driver Circuits
Each of the four output drivers are comprised of bipolar high
speed NPN transistors for both sourcing and sinking gate
charge to and from the MOSFET switches. In addition, the
sink driver incorporates a parallel-connected n-channel
MOSFET to enable the gate of the power switch gate-source
voltage to be brought completely to OV.
120
.L
30
o/
10
V
50
/
/
The propagation delays through the gate driver sub-circuits
while driving SOOpF loads is typically less than 1Oos. Nevertheless, the gate driver design nearly eliminates all gate
driver shoot-through which significantly reduces IC power
dissipation.
./'
./
100
150
200
250
HDEUUlEL RESISTANCE (leO)
Application Considerations
To successfully apply the HIP4080A the designer should
address the following concerns:
FIGURE 5. MINIMUM DEAD-nME VI DEL RESISTANCE
Level-Translation
•
General Bias Supply Design Issues
The lower power MOSFET gate drive signals from the propagation delay and control circuits go to amplifICation circuits
which are described in more detail under the section "Driver
Circuits". The upper power MOSFET gate drive signals are
directed first to the Level-Translation circuits before going to
the upper power MOSFET "Driver Circuits".
•
Upper Bias Supply Circuit Design
•
Bootstrap Bias Supply Circuit Design
The Level-Translation circuit communicate "on" and "off"
pulses from the Propagation Delay sub-circuit to the upper
logic and gate drive sub-circuits which "floar at the potential
General Bias Supply Design Issu.s
The bias supply design is simple. The designer must first
establish the desired gate voltage for turning on the power
switches. For most power MOSFETs, increasing the gatesource voltage beyond 10V yields little reduction in switch
drain-source voltage drop.
11-267
Application Note 9404
Overcharging the power switch's gate-source capacitance
also delays tum-off, increases MOSFET switching losses
and increases the energy to be switched by the gate driver of
the HIP4080A, which increases the dissipation within the
HIP4080A. Overcharging the MOSFET gate-source capacitance also can lead to "shoot-through" where both upper and
lower MOSFETs in a single bridge leg roo themselves on
simukaneously. thereby shorting out the high voltage DC bus
supply. Values close to 12V are optimum for supplying Voo
and Vee, akhough the HIP4080A will operate up to 15V.
Lower Bias Supply Design
Since most applications use identical MOSFETs for both
upper and lower power switches, the bias supply requirements with respect to driving the MOSFET gates will also be
identical. In case switching frequencies for driving upper and
lower MOSFETs differ, two sets of calculations must be
done; one for the upper switches and one for the lower
switches. The bias current budget for upper and lower
switches will be the sum of each calculation.
loads, where the MOSFETs are switched infrequently and
switching losses are low, may provide opportunities for boot
strapless operation. Generally, loads with a lot of resistance
and inductance are possible candidates.
Operating the HIP4080A without a bootstrap diode and/or
capacitor will severely slow gate turn-on. Without a bootstrap
capacitor, gate current only comes from the internal charge
pump. The peak charge pump current is only about 30IlA to
501lA. The gete voitage waveform, when operating without a
bootstrap capacitor, will appear similar to the dotted line
shown in Figure 6.
I! a bootstrap capacitor value approximately equal to the
equivalent MOSFET gate capacitance is used, the upper
bias supply (labeled "bootstrap voltage" in Figure 6) will drop
approximately in half when the gate is turned on. The larger
the bootstrap capacitance used, the smaller is the instantaneous drop in bootstrap supply voltage when an upper
MOSFET is turned on.
Always keep in mind that the lower bias supply must supply
current to the upper gate drive and logic circuits as well as
the lower gate drive circuits and logic circuits. This is due to
the fact that the low side bias supplies (VccfV DO) charge the
bootstrap capacitors and the charge pumps, which maintain
voltage across the upper power switch's gate-source terminals.
Good layout practice and capacitor bypassing technique
avoids transient voitage dips of the bias power supply to the
HIP4080A. Always place a low ESR (equivelent series resistance) ceramic capacitor adjacent to the IC, connected
between the bias terminals Vee and Voo and the common
terminal, Vss of the IC. A value in the range of O.22IlF and
O.5IlF is usually SuffICient.
Minimize the effects of Miller feedback by keeping the source
and gate return leads from the MOSFETs to the HIP40BOA
short. This also reduces ringing, by minimizing the length
and the inductance of these connections. Another way to
minimize inductance in the gate charge/discharge path, in
addition to minimizing path length, is to run the outbound
gate lead directly "over" the source return lead. Sometimes
the source return leads can be made into a small "ground
plane" on the back side of the PC board making it possible to
run the outbound gate lead "on top" of the board. This minimizes the "enclosed area" of the loop, thus minimizing inductance in this loop. It also adds some capacitance between
gate and source which shunts out some of the Miller feedback effect.
Upper Bias Supply Circuit Design
Before discussing bootstrap circuit design in detail, it is
worth mentioning that it is possible to operate the HIP4080A
without a bootstrap circuit altogether. Even the bootstrap
capacitor, which functions to supply a raservoir of charge for
rapidly turning on the MOSFETs is optional in some cases.
In situations where wry slow turn-on of the MOSFETs is tolerable, one may consider omitting some or all bootstrap
components. Applications such as driving relays or lamp
INI~~
1
SIGNAL
BOOT STRAP
...-
(Xv:~~~)
I
I
~----ilt-----
...
t....._----l
~-------.
I
Q~!,~~::e 1
._- - ...-.-..-.................
----~----~----FIGURE&.
Although not recommended, one may employ a bootstrap
capacitor without a bootstrap diode. In this case the charge
pump is used to charge up a capacitor whose value should
be much larger than the equivalent gate-source capacitance
of the driven MOSFET. A value of bootstrap capacitance
about 10 times greater than the equivalent MOSFET gatesource capacitance is usually sufficient. Provided that sufficient time elapses before turning on the MOSFET again, the
bootstrap capacitor will have a chance to recharge to the
voltage value that the bootstrap capacitor had prior to turning on the MOSFET. Assuming 20 of series resistance is in
the bootstrap change path, an output frequency of up
to
1
should allow sufficient refresh time.
5 X20XC BS
A bootstrap capacitor 10 times larger than the equivalent
gate-source capacitance of the driven MOSFET prevents the
drop in bootstrap supply voltage from exceeding 100/0 of the
bias supply voltage during turn-on of the MOSFET. When
operating without the bootstrap diode the time required to
replenish the charge on the bootstrap capacitor will be the
same time as it would take to charge up the equivalent gate
capacitance from ov. This is because the charge lost on the
bootstrap capacitor is exactly equal to the charge transferred
to the gate capacitance during turn-on. Note that the wry
first time that the bootstrap capacitor is charged up, it takes
11-268
Application Nots 9404
much longer to do so, since the capacitor must be charged
from OV. With a bootstrap diode, the initial charging of the
bootstrap supply is almost instantaneous, since the charge
required comes from the low-side bias supply. Therefore,
before any upper MOSFETs can initially be gated, time must
be allowed for the upper bootstrap supply to reach full voltage. Without a bootstrap diode, this initial "charge" time can
be excessive.
I! the switching cycle is assumed to begin when an upper
MOSFET is gated on, then the bootstrap capacitor will
undergo a charge withdrawal when the source driver connects it to the equivalent gate-source capacitance of the
MOSFET. After this initial "dump' of charge, the quiescent
current drain experienced by the bootstrap supply is infinitesimal. In fact, the quiescent supply current is more than
offset by the charge pump current.
The charge pump continuously supplies current to the bootstrap supply and eventually would charge the bootstrap
capacitor and the MOSFET gate capacitance back to its initial value prior to the beginning of the switchirig cycle. The
problem is that "eventually" may not be fast enough when the
switching frequency is greater than a few hundred Hz.
tOFF
= (1 -
(EO.2)
DC) "PWM
As soon as the upper MOSFET is turned off, the voltage on
the phase terminal (the source terminal of the upper MOSFEn begins its descent toward the negative rail of the high
voltage bus. When the phase terminal voltage becomes less
than the Vee voltage, refreshing (charging) of the bootstrap
capacitor begins. As long as the phase voltage is below Vee
refreshing continues until the bootstrap and Vee voltages
are equal.
The off-time of the upper MOSFET is dependent on the gate
control input signals, but it can never be shorter than the
dead-time delay setting, which is set by the resistors connecting HDEL and LDEL to Vss. If the bootstrap capaCitor is
not fully charged by the time the upper MOSFET turns on
again, incomplete refreshing occurs. The designer must
insure that the dead-time setting be consistent with the size
of the bootstrap capacitor in order to guarantee complete
refreshing. Figure 7 illustrates the circuit path for refreshing
the bootstrap capaCitor.
HIGH VOLTAGE BUS...~!!!!.
HIP 4080
""",1"",',."
TO "B-SlDE"
~
OF
H-BRIDGE
AHB I
Bootstrap Bias Supply Circuit Design
For high frequency applications all bootstrap components,
both diodes and capaCitors, are required. Therefore, one
must be familiar with bootstrap capacitor sizing and proper
choice of bootstrap diode.
Just after the SWitch cycle begins and the charge transfer
from the bootstrap capacitor to the gate capaCitance is complete, the voltage on the bootstrap capacitor is the lowest
that it will ever be during the switch cycle. The charge lost on
the bootstrap capacitor will be very nearly equal to the
charge transferred to the equivalent gate-source capacitance of the MOSFET as shown in Equation ,.
QG
(VaS1 - Vas2 ) X Cas
(EO.1)
SUPPLY
BYPASS
where:
CAPACITOR
TO "B-SlDE"
=
Ves1= Bootstrap voltage immediately before turn-on
V882= Bootstrap voltage immediately after turn-on
Ces Bootstrap Capacitance
OG • Gate charge transferred during turn-on
OFK-BRIDGE
NOTE: Only "A-side" of H-bridge Is Shown for Simplicity.
Arrows Show Bootstrap Charging Path.
=
FIGURE 7. BOOTSTRAP CAPACITOR CHARGING PATH
Were it not for the internal charge pump, the voltage on the
bootstrap capaCitor and the gate capacitor (because an
upper MOSFET is now turned on) would eventually drain
down to zero due to bootstrap diode leakage current and the
very small supply current associated with the level-shifters
and upper gate driver sub-circuits.
In PWM switch-mode, the switching frequency is equal to the
reciprocal of the period between successive turn-on (or turnoff) pulses. Between any two turn-on gate pulses exists one
turn-off pulse. Each time a turn-off pulse is issued to an
upper MOSFET, the bootstrap capacitor of that MOSFET
begins its "refresh" cycle. A refresh cycle ends when the
upper MOSFET is turned on again, which varies depending
on the PWM frequency and duty cycle. As the duty cycle
approaches 100%, the available "off-time", IoFF approaches
zero. Equation 2 shows the relationship between IoFf; fPWM
and the du
cle.
The bootstrap charging and discharging paths should be
kept short, minimizing the inductance of these loops as mentioned in the section, "Lower Bias Supply Design".
Bootstrap Circuit Design· An Example
Equation 1 describes the relationship between the gate
charge transferred to the MOSFET upon turn-on, the size of
the bootstrap capacitor and the change in voltage across the
bootstrap capaCitor which occurs as a result of turn-on
charge transfer.
The effects of reverse leakage current associated with the
bootstrap diode and the bias current associated with the
upper gate driY8 circuits also affect bootstrap capacitor sizing. At the Instant that the upper MOSFET turns on and its
source wltage begins to rapidly rise, the bootstrap diode
becomes rapidly reverse biased resulting in a reverse recov-
11-269
z
o
-en
~w
O~
-0
~z
D..
cC
Application Note 9404
ery charge which further depletes the charge on the bootstrap capacitor. To completely model the total charge
transferred during turn-on of the upper MOSFETs, these
effects must be accounted for, as shown In Equation 3.
(IOR+loas)
0a + ORR + --:-,- - C _
PWM
as VaS1 - VaS2
Power Dissipation and Thermal Design
(EQ.3)
where:
lOR Bootstrap diode reverse leakage current
laBS Upper supply quiescent current
QRR = Bootstrap diode reverse recovered charge
QG Turn-on gate charge transferred
fPWM PWM operating frequency
VBSt Bootstrap capacitor voltage just after refresh
VBS2 Bootstrap capacitor voltage just after upper turn on
CBS Bootstrap capacitance
=
=
=
=
=
=
=
From a practical standpoint, the bootstrap diode reverse
leakage and the upper supply quiescent current are negligible, particularly since the HIP4080A's internal charge pump
continuously sources a minimum of about 30j1A. This current
more than offsets the leakage and supply current components, which are fixed and not a function of the switching frequency. The higher the switching frequency, the lower Is the
charge effect contributed by these components and their
effect on bootstrap capaCitor sizing is negligible, as shown in
Equation 3. Supply current due to the bootstrap diode recovery charge component increases with switching frequency
and generally is not negligible. Hence the need to use a fast
recovery diode. Diode recovery charge information can usually be found in most vendor data sheets.
For example, if we choose a Harris IRF520R power
MOSFET, the data book states a gate charge, QG' of 12nC
typical and lSnC maximum, both at Vos .. 12V. Using the
maximum value of lSnC the maximum charge we should
have to transfer will be less than 18nC.
Suppose a General Instrument UF4002, l00V, fast recovery,
1A. miniature plastic rectifl6r is used. The data sheet gives a
reverse recovery time of 25ns. Since the recovery current
waveform is approximately triangular, the recovery charge can
be approximated by taking the product of half the peak reverse
current magnitude (1 A peak) and the recovery time duration
(2508). In this case the recovery charge should be 12.5nC.
Since the internal charge pump offsets any possible diode
leakage and upper drive circuit bias currents, these sources
of discharge current for the bootstrap capacitor will be
ignored. The bootstrap capaCitance required for the example
above can be calculated as shown in Equation 4, using
Equation 2.
C
_ 18ne
as -
+ 12.5nC
12.0 -11.0
diode recovered charge are used rather than the maximum
value, the voltage droop on the bootstrap supply will be only
aboutO.5V
(EQ.4)
Therefore a bootstrap capaCitance of O.033I1F will result in
less than a 1.0V droop in the voltage across the bootstrap
capacitor during the turn-on period of either of the upper
MOSFETs. If typical values of gate charge and bootstrap
One way to model the power dissipated in the HIP4080A Is
by lumping the losses into static losses and dynamic (switching) losses. The static losses are due to bias current losses
for the upper and lower sections of the IC and include the
sum of the Icc and 100 currents when the IC is not switching.
The quiescent current is approximately 9mA. Therefore with
a 12V bias supply, the static power dissipation in the IC is
slightly over l00mW.
The dynamic losses associated with switching the power
MOSFETs are much more significant and can be divided
into the following categories:
•
Low Voltage Gate Drive (charge transfer)
•
High Voltage Level-shifter (V-I) Losses
•
High Voltage Level-shifter (charge transfer)
In practice, the high voltage level-shifter and charge transfer
losses are small compared to the gate drive charge transfer
losses.
The more significant low voltage gate drive charge transfer
losses are caused by the movement of charge In and out of
the equivalent gate-source capacitor of each of the 4 MOSFETs comprising the H-brldge. The loss is a function of
PWM (switching) frequency, the applied bias voltage, the
equivalent gate-source capacitance and a minute amount of
CMOS gate charge internal to the HIP4080A. The low voltage charge transfer losses are given by Equation 5.
PSWLO
= fpWM X (oa + O,C) X valAS
(EQ.5)
The high voltage level-shifter power dissipation is much
more difficult to evaluate, although the equation which
defines it is simple as shown in Equation 6. The diffICUlty
arises from the fact that the level-shift current pulses, ION
and IOFF' are not perfectly In phase with the voltage at the
upper MOSFET source terminals. VSHIFT due to propagation
delays within the IC. These time-dependent source voltages
(or "phese" voltages) are further dependent on the gate
capacitance of the driven MOSFETs and the type of load
(resistive, capacitive or Inductive) which determines how
rapidly the MOSFETs tum on. For example, the level-shifter
ION and IOFF pulses may come and go and be latched by the
upper logic circuits before the phase voltage even moves. As
a result, little level-shift power dissipation may result from the
ioN pulse, whereas the !oFF pulse may have a significant
power dissipation associated with It, since the phase voltage
generally remains high throughout the duration of the !oFF
pulse.
(EQ.6)
PSHIFT
11-270
=
~Ib (ION(t) +IOFF(t»
XVSHIFT(t) xdt
Application Note 9404
Lastly, there Is power dissipated within the IC due to charge
transfer in and out of the capacitance between the upper
driver circuits and Vss. Since it is a charge transfer phenomena, it closely resembles the form of Equation 5, except that
the capacitance is much smaller than the equivalent gatesource capacitances associated with power MOSFETs. On
the other hand, the \/Oltages associated with the level-shifting function are much higher than the \/Ollage changes experienced at the gate of the MOSFETs. The relationship is
shown in Equation 7.
PTUB
=
CTUB X
V~HIFT X
fpWM
(Ea. 7)
The power associated with each of the two high voltage tubs
in the HIP4080A derived from Equation 7 is quite small, due
to the extremely small capacitance associated with these
tubs. A 'ub" is the isolation area which surrounds and isolates the high side circuits from the ground referenced circuits of the IC. The important point for users is that the
power dissipated is linearly related to switching frequency
and the SQuare of the applied bus \/Ollage.
The tub capacitance in Equation 7 varies with applied volIage, VSHIFT, making its solution difficull, and the phase shift
of the ION and IOFF pulses with respect to the phase \/Oltage,
VSHIFT, in Equation 6 are difficult to measure. Even the ale in
Equation 5 is not easy to measure. Hence the use of Equation 5 through Equation 7 to calculate total power dissipation
is at best difficult. The equations do, however, allow users to
understand the significance that MOSFET choice, SWitching
frequency and bus \/Oltage play in determining power dissipation. This knowledge can lead to corrective action when
power diSSipation becomes excessive.
Fortunately, there is an easy method which can be used to
measure the components of power dissipation rather than
calculating them, except for the tiny 'ub capacitance" component.
Power Dissipation, the Easy Way
The average power dissipation associated with the IC and
the gale of the connected MOSFETs can easily be measured using a signal generator, an averaging millimeter and
a voltmeter.
Low Voltage Power Dlaslpatlon
Two sets of measurements are required. The first set uses
the circuit of Figure 8 and evaluates all of the low \/Oltage
power dissipation components. These components include
the MOSFET gate charge and internal CMOS charge transfer losses shown in Equation 5 as well as the quiescent bias
current losses associated with the IC. The losses are calculated very simply by calculating the product of the bias \/011age and current measurements as performed using the
circuit shown in Figure 8. For measurement purposes, the
phase terminals (AHS and BHS) for both A and B phases
are both tied to the chip common, Vss terminal, along with
the lower source terminals, ALS and BLS. Capacitors equal
to the equivalent gate-source capacitance of the MOSFETs
are connected from each gate terminal to Vss. The value of
the capacitance chosen comes from the MOSFET manufac-
turers data sheet. Notice that the MOSFET data sheet usually gives the value in units of charge (usually nanocoulombs) for different drain-source voltages. Choose the
drain-source lIOIIage closest to the particular DC bus \/Oltage
of interest_
Simply substituting the actual MOSFETs for the capacitors,
CL, doesn't yield the correct average current because the
Miller capacitance will not be accounted for. This is because
the drains don't switch using the test circuit shown in Figure
8. Also the gate capacitance of the devices you are using
may not represent the maximum values which only the data
sheet will provide.
I~
HIP4080A
CL. GATE LOAD CAPACITANCE
FIGURE 8. LOW VOLTAGE POWER DISSIPATION TEST
CIRCUIT
The low \/Oltage charge transfer switching currents are
shown in Figure 9. Figure 9 does not include the quiescent
bias current component, which is the bias current which
flows in the IC when switching is disabled. The quiescent
bias current component is approximately 1OmA. Therefore
the quiescent power loss at 12V would be 120mW. Note that
the bias current at a given switching frequency grows almost
proportionally to the load capacitance, and the current is
directly proportional to switching frequency, as previously
suggested by Equation 5.
500
1!Z
w
II:
II:
:I
u
:l
200
so
s
!
~
V
t- 3,000 \
0.&
CI.2
0.1
~
lL
~Y ~
v.: V. /
V
2
~ ~
10
ao
""
L
".,. I'"" " "
5
~
V- I"" I"""
~
Y' . /
I""
\
1\
V
. / V-
V ~~
l'\
t- 1,000 \
10 t100\
2
~
~
ao
ii
~
V
.!
100 t-10,OOO \
50
100 200
500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 9. LOW VOLTAGE BIAS CURRENT 100 AND lcc(LESS
QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE
11-271
Application Note 9404
High Voltage Power Dlsalpatlon
The high voltage power dissipation component is largely
comprised of the high voltage level-shifter component as
described by Equation 6. All of the diffICulties associated
with the time variance of the ION and IOFF pulses and the
level shift voltage. VSHIFT. under the integrand in Equation 6
are avoided. For completeness. the total loss must include a
small leakage current component. although the latter is usually smaller compared to the level-shifter component. The
high voltage power loss calculation is the product of the high
voltage bus voltage level. VBUS. and the average high voltage bus current. IBUS• as measured by the circuit shown in
Figure 10. Averaging meters should be used to make the
measurements.
12V;.....,~I-f21
n..n.n
measures quiescent leakage current as well as the switching
component. Notice that the current increases somewhat with
applied bus voltage. This is due to the finite output resistance of the level-shift transistors In the IC.
Layout Issues
In fast switching, high frequency systems. poor layout can
result in problems. It Is crucial to consider PCB layout. The
HIP4080A pinout configuration encourages tight layout by
placing the gate drive output terminals strategically along the
right side of the chip (pin 1 Is In the upper left-hand corner).
This provides for short gate and source return leads connecting the IC with the power MOSFETs.
Minimize the series inductance In the gate drive loop by running the lead going out to the gate of the MOSFETs from the
IC over the top of the return lead from the MOSFET sources
back to the IC by using a double-sided PCB if possible. The
PC board separates the traces and provides a small amount
of capacitance as well as reducing the loop Inductance by
reducing the erlCircled area of the gate drive loop. The benefit is that the gate drive currents and voltages are much less
prone to ringing which can similarly modulate the drain current of the MOSFET. The following table summarizes some
of the layout problems which can occur and the corrective
action to take.
Layout Problems and Effects
The Bootstrap circuit path should also be short to minimize
series inductance that may cause the voltage on the bootstrap capacitor to ring. slowing down refresh or causing an
overvoltage on the bootstrap bias supply.
CL_GATELOADCAPAaTANCE
A compact power circuit layout (short circuit path between
upperllower power switches) minimizes ringing on the phase
lead(s} keeping BHS and AHS voltages from ringing excessively below the Vss terminal which can cause excessive
charge extraction from the substrate and possible malfunction of the IC.
FIGURE 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST
CIRCUIT
1000
v
500
V
V
Excessive gate lead lengths can cause gate voltage ringing
and subsequent modulation of the drain current. thereby
amplifying the Miller Effect.
~~
~ tr
., '"'""-
~ p<: r- i--
--- r-- ---
~
2
PROBLEM
lOY
-
Inductance may cause voltage on bootstrap capacitor to ring. slowing down
refresh andIor causing an overvoltage
on the bootstrap bias supply.
Lack of tight power 00cult layout (long circuit
path be~ upperl
lower power switches)
Can cause ringing on the phase Iead(s)
causing BHS and AHS to ring excesslve/y below the Vas terminal causing
excessive charge extraction from the
substrate and possible malfunction of
theiC.
Excessive gate lead
lengths
Can cause gate voltage ringing and subsequent modulation of the drain current
and impairs the effectiveness of the sink
drIvar from minimizing the miller effect
when an opposing switch Is being rapid-
lOY
--- 40Y
--- 20V
5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)
500 1000
FIGURE 11. HIGH VOLTAGE LEVEL-SHIFT CURRENT VI
FREQUENCY AND BUS VOLTAGE
Figure 11 shows that the high voltage level-shift current varies directly with switching frequency. This result should not
be surprising. since Equation 6 can be rearranged to show
the current as a function of frequency. which is the reciprocal
of the switching period. 1fT. The test circuit of Figure 10
EFFECT
Bootstrap circuit path
too long
11-272
Iytumed on.
Application Not. 9404
Quick Help Table
Application Demonstration PC Board
The quick help table has been included to help locate solutions to problems you may have in applying the HIP4080A.
Harris hes deYeloped a demonstration PC board to allow fast
prototyping of numerous types of applications. The board
was also tailored to be used to aid in characterizing the
HIP4080A and HIP4081A devices under actual operating
conditions.
PROBLEM
EFFECT
Low chip bias voltages May cause power MOSFETs to exhibit excessive ROSON' possibiy overheating
(Vee and Voo)
them. Below about 6V, the IC may not
function properly.
High chip bias voltag- At Voo voltages above about l2V. The
es (Vee and Voo)
charge pump limiter will begin to operate,
In tum drawing heavier Voo current.
Above l6V, breakdown may occur.
Bootstrap capacitor(s)
too small
May cause Insufficient or soft charge delivery to MOSFETs at turn-on causing
MOSFET overheating. Charge pump will
pump charge, but possIbiy not quickly
enough to avoid excessive switching 1os&es.
Bootstrap capacitor(s)
too large
Dead time may need to be Increased In order to allow sufficient bootstrap refresh
time. The alternative Is to decrease bootstrap capacitance.
Ra,..lE too small
Smaller values of Ra,..lE reduces tum-ool
off times and may cause excessive ami
problems. Incorporating a series gate
resistor with an antI.parailel diode can
solve EMI problem and add to the dead
time, reducing shoot-through tendency.
RGAlE too large
Increases Switching losses and MOSFET
heating. If anti-parallel diode mentioned
above Is In backwards, tum-off time Is Increased, but tum-on time Is not, possibly
causing a shoot-through fault
Dead time too small
Reduces "refresh" time as weH as dead
time, with Increased shoot-through
tendency. Try increasing HDEL and LDEL
resistors (don't exceed 2501<0).
HIP4080A IC gets too
hot
Reduce bus voltage, switching frequency,
choose a MOSFETwith lower gate capacitanca or reduce bias voltage (It It Is not
below 10V to l2V). Shed some of the low
voltage gate switching losses In the
HIP4080A by placing a small amount of
series resistance In the leads going to the
MOSFET gates, thereby transferring
some of the IC losses to the resistors.
Lower MOSFETs tum
on, but uppar
MOSFETs don't
Chack that the HEN terminal Is not tied
low Inadvertently.
Figure 12 and Figure 13 show the schematic and the silkscreen indicating component placement, respectively, for the
HIP408X demo board. Note that the board can be used to
evaluate either the HIP4080A or the HIP4081A. simply by
changing a few jumpers.
The PC board incorporates a CD4069UB to "buffer" inputs to
the HIP4080A on input terminals INl and IN2. Normally the
polaritieS of INl and IN2 should be opposite in polarity to
obtain proper H-Bridge operation. If all 4 MOSFETs are to
be PWM-ed, then JMPR3 should be removed (or opened).
Also the OUT terminal of the IC should not be driven, so
insure JMPRl is open. Specific recommendations for working with the HIP4081A will be discussed in the corresponding section of the application note for the HIP4081A. JMPR5
should always be removed in order to implement the power
up reset circuit described in data sheet HIP4080A, File Number 3178. Resistors R27 and R28 as well as capacitor, C7
are not required.
Consistent with good design practice, the +12V bias supply
is bypassed by capacitors C6 and C5 (at the IC terminals
directly). Capacitor C6 is a 4.711F tantalum, designed to
bypass the whole PCB, whereas C5 is a 0.2211F. designed to
bypass the HIP4080A. The bootstrap capacitors, C3 and C4,
and the high voltage bus bypass capacitors are 0.111F. l00V
ceramic. Ceramic is used here because of the low inductance required of these capacitors in the application. The
bootstrap diodes are 1A. fast recovery (tRR 200ns), l00V,
to minimize the charge loss from the bootstrap capacitors
when the diodes become reverse-biased.
=
The MOSFETs supplied with the demo board is a Harris
IRF520, l00V, 9A device. Since it has a gate charge of
approximately 12nC, 10n gate resistors, R21 through R24,
have been employed to deliberately slow down turn-on and
turn-off of these switches. Finally, R33 and R34 provide
adjustment of the dead-time. These are 500k1l normally set
for l00k0, which will result in a dead-time of approximately
5Ons. Resistors, R30 and R31 are shunt resistors (0.10, 2W,
2%, wirewound) used to provide a current-limiting Signal, if
desired. These may be replaced with wire jumpers if not
required.
Finally, space has been provided for filter reactors, II and
l2, and filter capaCitors, Cl and C2, to provide filtering of
PWM switching components from appearing at output terminals N) and BO. To facilitate placement of user-defined ICs,
such as op-amps, comparators, etc., space for 3 fourteen pin
standard width ICs has been reserved at the far left side of
the demo board. The output terminations of the 3 optional
locations are wired to holes which can be used to mount
application-specifIC components, easing the process for
building up working amplifiers for motor controls and audio
amplifiers.
11-273
z
o- 0
~w
(.,)~
-0
~z
0.
c(
IN2 IN1
POWER SECTION
+12V
=r=CONTROL lOGIC
R28~
SECTION
DRIVER SECTION
JMPR1
BHB
JlM'
6 r
L------:i DlS
IM+lAU
C04011UB
~
v
,
JMPR3
HENlBHI
6-"
4 V
5
BlO 18
BLS ...
1.:..7--:::::-,
VDO 18
7 IN-IAHI
HDEl
ALS 14
ALO 13
o:./BU
'------:,i"WAU
...--------:.i
~
C04011UB
{It,
IN-IAHI
J
...
l1
-..nrX'X"...,-t-----1J NJ
.....
R23
Vee 15
SO
R24
CR1
1
Q4
g::!:.
I-
...
~
3
Cit
~
C3
L..-_-I
a
~
-!ALS
BLS
NOTE:
DEVICE CD406tUB PIN 7. COM. PIN 14 • +1ZV_
FIGURE 12_ HIP4080A EVALUATION PC BOARD SCHEMATIC
)a
:g
[
2,
AH011-l1~1+-t-t-t-'
~.w
-08+
3'
BHS 11
AHS 12
JMPR4
_I-
R22'
BHO 20
...-_+-+___-:-1 HENlBHI
.•
~
3'
HIP4080AI81A C4
U1
>-=-",-06- - OUTIBU
~
R21
CR2
eel
2
~
.. ... .0. ·.. ..
~ ~~~~
II:
II: II: II:
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li+ ~., •
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DD
FIGURE 13. HIP4080A EVALUATION BOARD SlLKSCREEN
APPLICATION
NOTES
~
R23
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~
g;;;
~
-
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• .JMPR3 • • !!: • ALS
•
••••
Q1
R22.
.BHO ~
•
•••
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CR2
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~
Harris Semiconductor
--
- - - -
-------
No. AN9405
----- -
=-==-=-
-- --===
--===
----- -- - - -----
Harris Intelligent Power
April1994
HIP4081A, 80V HIGH FREQUENCY H-BRIDGE DRIVER
Author: George E. Danz
Introduction
The HIP4081A is a member of the HIP408X family of High
Frequency H-Bridge Driver ICs. A simplified application diagram of the HIP4081A IC is shown in Figure 1. The HIP408X
family of H-Bridge driver ICs provide the ability to operate
from 10VDC to 80VDC busses for driving H-Bridges. operating in class-D switch-mode. whose switch elements are comprised of power N-channel MOSFETs. The HIP408X family.
packaged in both 20 pin DIP and 20 pin SOIC DIPs. provide
peak gate current drive of 2.5A. The HIP4081A includes
undervoltage protection. which sends a continuous gate
turn-off pulse to all gate outputs when the VDD voltage falls
below a nominal 8.25 volts. The startup sequence of the
HIP4081A is initiated when the VDD voltage returns above a
nominal 8.75 volts. Of course. the DIS pin must be in the low
state for the IC to be enabled. The startup sequence turns
on both low side outputs. AlO and BlO. so that the bootstrap capacitors for both sides of the H-bridge can be fully
charged. During this time the AHO and BHO gate outputs
are held low continuously to insure that no shoot-through
can occur during the nominal 400ns boot-strap refresh
period. At the end of the boot strap refresh period the outputs respond normally to the state of the input control signals.
in various high frequency converter applications. such as
class-D
audio
amplifiers.
and
motor
drives.
high-performance DC-DC converters. A typical application is
shown in Figure 5.
IOV
A combination of bootstrap and charge-pumping techniques
is used to power the circuitry which drives the upper halves
of the H-Bridge. The bootstrap technique supplies the high
instantaneous current needed for turning on the power
devices. while the charge pump provides enough current to
"maintain" bias voltage on the upper driver sections and
MOSFETs. Since voltages on the upper bias supply pin
"!Ioar along with the source terminals of the upper power
switches. the design of this family provides voltage capability
for the upper bias supply terminals to 95VDC.
DUAL HIGHILOW SWITCHES FOR
AUTOMOTIVE AND INDUSTRIAL CONTROLS
1
•
OND
FIGURE 1. HIP4081A SIMPUFIED APPLICATION DIAGRAM
"-- .
HIP4081A
The HIP4081A can drive lamp loads for automotive and
industrial applications as shown in Figure 2. When inductive
loads are switched. flyback diodes must be placed around
the loads to protect the MOSFET switches.
Many applications utilize the full bridge topology. These are
voice coil motor drives. stepper and DC brush motors. audio
amplifl9rs and even power supply inverters used in uninterruptable power supplies. just to name a few. The HIP408X
family of devices is fabricated using a proprietary Harris IC
process which allows this family to switch at frequencies
over 250kHz. Therefore the HIP408X family Is ideal for use
OND
i
,
... J
FIGURE 2. HIP40B1A AS LAMP SWITCH DRIVER
To provide accurate dead-time control for shoot-through
avoidance and duty-cycle maximization. two resistors tied to
Copyrlght@Harris Corponltlon 1994
11-276
Application Note 9405
upper and lower propagation delays, which are typically only
55ns. The HIP4081A H-Bridge driver has enough voltage
margin to meet all SELV (UL classifICation for operation at
s 42.0V) applications and most Automotive applications
where "load dump" capability Oller 65V is required. This
capability makes the HIP408X family a more cost-effective
solution for driving N-channel power MOSFETs than either
discrete solutions or other solutions relying on transformeror opta-coupling gate-drive techniques.
The biggest difference between the HIP4080A and the
HIP4081A is that the HIP4081A allows separate and individual control of the 4 MOSFET gates, whereas the HIP4080A
does not. Also the HIP4081A does not include an internal
comparator which can create a PWM signal directly within
the HIP4080A.
Description of the HIP4081 A
The block diagram of the HIP4081A relating to driving the
A-side of the H-Bridge is shown in Figure 4. The blocks
associated with each haH of the H-Bridge are identical, so
the B-side is not shown for simplicity.
The Vee and VDD terminals on the HIP4081A should be tied
together. They were separated within the HIP4081A Ie to
avoid possible ground loops internal to the Ie. Tieing them
together and providing a decoupling capacitor from the common tie-point to Vss greatly improves noise immunity.
Input Logic
The HIP4081A has 4 inputs, AU, BU, AHI and BHI, which
control the gate outputs of the H-bridge. The DIS, "Disable,"
pin disables gate drive to all H-bridge MOSFETs regardless of
the command states of the input pins above. The state of the
bias voltage, VDO. also can disable all gate drive as discussed in the introduction. The HIP4081A has pullups on the
high input terminals, AHI and BHI, so that the bridge can be
totally controlled using only the lower input control pins, AU
and BU, which can greatly simplify the external control circuitry needed to control the HIP4081A. As Table 1 suggests,
the lower inputs AU and BU dominate the upper inputs. That
is, when one of the lower inputs is high, it doesn't matter what
the level of the upper input is, because the lower will turn on
and the upper will remain off.
TABLE 1. INPUT LOGIC TRUTH TABLE
INPUT
Propagation Delay Control
Propagation delay control is a major feature of the
HIP4081A. Two identical sub-clrcuits within the Ie delay the
commutation of the power MOSFET gate turn-on signals for
both A and B sides of the H-bridge. The gate turn-off signals
are not delayed. Propagation delays related to the Ieveltranslation function (see section on Level-Translation) cause
both upper onIoff propagation delays to naturally be longer
than the lower onIoff propagation delays. Four delay trim
sub-circuits are incorporated to better match the H-bridge
delays, two for upper delay control and two for lower gate
control.
Users can tailor the low side to high side commutation delay
times by placing a resistor from the HDEL pin to the Vss pin.
Similarly, a resistor connected from LDEL to Vss controls the
high side to low side commutation delay times of the lower
power switches. The HDEL resistor controls both upper
commutation delays and the LDEl resistor controls the
lower commutation delays. Each of the resistors sets a current which is inversely proportional to the created delay. The
delay is added to the falling edge of the "off" pulse associated with the MOSFET which is being commutated off.
When the delay is complete, the "on" pulse is initiated. This
has the effect of "delaying" the commanded on pulse by the
amount set by the delay, thereby creating dead-time.
Proper choice of resistor values connected from HDEL and
LDEL to Vss provides a means for matching the commutation dead times whether commutating high to low or low to
high. Values for the resistors ranging from lOkn to 200kn
are recommended. Figure 3 shows the dead-time delays
obtainable as a function of the resistor values used.
1&0
./
120
/:
30
OUTPUT
/'
V"
V
/
/'
z
o
-tJ)
!ciw
AU, BLI
AHI,BHI
UN
DIS
ALO,
BLO
AHO,
BHO
X
X
X
1
0
0
1
X
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
Level-Translation
X
X
1
X
0
0
The lower power MOSFET gate drive signals from the propagation delay and control circuits go to amplification Circuits
which are described in more detail under the section "Driver
Circuits". The upper power MOSFET gate drive signals are
directed first to the Level-Translation circuits before going to
the upper power MOSFET "Driver Circuits".
NOTE: X SIgnifies that
o
10
so
()I-
100
1&0
200
2&0
HDELILDEL RESISTANCE (1Ul)
FIGURE 3. MINIMUM DEAD-TIME va DEL RESISTANCE
Input can be either a "1" or "0".
The input sensitivity of the DIS input pin is best described as
"enhanced TTL" levels. Inputs which fall below 1.0V or rise
above 2.5V are recognized, respectively, as low level or high
level inputs.
11-277
-0
~z
a..
<
Application Note 9405
HIGH VOLTAGE BUS s IIYDC
TO YIID (PIN 18)
+12YDC
= SUPPLY
BIAS
FIGURE 4. HIP4081A BLOCK DIAGRAM
pwy
INPUT
GND
TO OPTIONAL
CURRENT CONTROLLER
+---+----<
GND
FIGURE 5. TYPICAL APPLICATION (PWM MODE SWITCHING)
11·278
Application Note 9405
The Level-Translation circuit communicate "on" and "off"
pulses from the Propagation Delay sub-circuit to the upper
logic and gate drive sub-circuits which "fIoar at the potential
of the upper power MOSFET source connections. This voltage can be as much as 85V when the bias supply voltage is
only 10V (the sum of the bias supply voltage and bus voltages must not exceed 95VDC).
Gener.1 Bla. Supply Design I.sue.
In order to minimize power dissipation in the level-shifter circuit, it is important to minimize the width of the pulses translated because the power dissipation is proportional to the
product of switching frequency and pulse energy in joules.
The pulse energy in turn is equal to the product of the bus
voltage magnitude, translation pulse current and translation
pulse duration. To provide a reliable, noise free pulse
requires a nominal current pulse magnitude of approximately
3mA. The translated pulses are then "latched" to maintain
the "on" or "off" state until another level-translation pulse
comes along to set the latch to the opposite state. Very reliable operation can be obtained with pulse widths of approximately SOns. At a switching frequency of even 1.0MHz, with
an 80VDC bus potential, the power developed by the leveltranslation circuit will be less than O.08W.
Overcharging the power switch's gate-source capacitance
also delays turn-off, increases MOSFET gate switching
losses and increases the power dissipation 01 the
HIP4081A. Overcharging the MOSFET gate-source capacitance also can lead to 'shoot-through" (both upper and lower
MOSFETs in a single bridge leg find themselves conducting
simultaneously), thereby shorting out the high voltage DC.
Bias supply voltages close to 12V are optimum for Voo and
Vee although the HIP4081 A will operate up to 15V.
Charge Pump Circuits
There are two charge pump circuits in the HIP4081A, one for
each of the two upper logic and driver circuits. Each charge
pump uses a switched capacitor doubler to provide about
301JA to 501JA 01 gate load current. The sourcing current
charging capability drops off as the floating supply voltage
increases. Eventually the gate voltage approaches the level
set by an internal zener clamp, which prevents the voltage
from exceeding about 15V, the safe gate voltage rating of
most commonly available MOSFETs.
Driver Circuits
Each of the four output drivers are comprised of bipolar high
speed NPN transistors for both sourcing and sinking gate
charge to and from the MOSFET switches. In addition, the
sink driver incorporates a parallel-connected n-channel
MOSFET to enable the gate of the power switch gate-source
voltage to be brought completely to OV.
The propagation delays through the gate driver sub-circuits
while driving SOOpF loads is typically less than 1Ons. Nevertheless, the gate driver design nearly eliminates all gate
driver shoot-through which significantly reduces IC power
dissipation.
Application Considerations
To successfully apply the HIP4081A the designer should
address the following concerns:
• General Bias Supply DeSign Issues
• Upper Bias Supply Circuit Design
•
Bootstrap Bias Supply Circuit Design
The bias supply design is simple. The designer must first
establish the desired gate voltage for turning on the power
switches. For most power MOSFETs, Increasing the gatesource voltage beyond 10V yields little reduction in switch
drain-source voltage drop.
Lower BI•• Supply Design
Since most applications use identical MOSFETs for both
upper and lower power switches, the bias supply requirements with respect to driving the MOSFET gates will also be
identical. In case switching frequencies for driving upper and
lower MOSFETs differ, two sets of calculations must be
done; one for the upper switches and one for the lower
switches. The bias current budget for upper and lower
switches will be the sum of each calculation.
Always keep in mind that the lower bias supply must supply
current to the upper gate drive and logic circuits as well as
the lower gate drive circuits and logic circuits. This is due to
the fact that the low side bias supplies ry cdV DO} charge the
bootstrap capaCitors and the charge pumps, which maintain
voltage across the upper power switch's gate-source terminals.
Good layout practice and capacitor bypassing technique
avoids transient voltage dips of the bias power supply to the
HIP4081A. Always place a low ESR (equivalent series resistance) ceramic capacitor adjacent to the IC, connected
between the bias terminals Vee and Voo and the common
terminal, Vss of the IC. A value in the range 01 O.22I1F and
O.5I1F is usually suffICient.
Minimize the effacts of Miller feedback by keeping the
source and gate return leads from the MOSFETs to the
HIP4081A short. This also reduces ringing, by minimizing
the length and the inductance of these connections. Another
way to minimize inductance in the gate charge/discharge
path, in addition to minimizing path length, Is to run the outbound gate lead directly "over" the source retum lead.
Sometimes the source return leads can be made into a small
"ground plane" on the back side of the PC board making it
possible to run the outbound gate lead "on top" 01 the board.
This minimizes the "enclosed area" 01 the loop, thus minimizing inductance in this loop. It also adds some capacitance
between gate and source which shunts out some of the
Miller feedback effact.
Upper BI88 Supply Circuit Design
Before discussing bootstrap circuit design in detail, it is
worth mentioning that it is possible to operate the HIP4081A
without a bootstrap circuit altogether. Even the bootstrap
11-279
Application Note 9405
capacitor, which functions to supply a reservoir of charge for
rapidly turning on the MOSFETs is optional in some cases.
1n situations where wry slow tum-on of the MOSFETs is tolerable, one may consider omitting some or all bootstrap
components. Applications such as driving relays or lamp
loads, where the MOSFETs are switched infrequently and
switching losses are low, may provide opportunities for boot
strapless operation. Generally, loads with lots of resistance
and inductance are possible candidates.
Operating the HIP4081A without a bootstrap diode andlor
capacitor will severely slow gate turn-on. Without a bootstrap capacitor, gate current only comes from the internal
charge pump. The peak charge pump current is only about
30jJA to 5<¥A. The gate voltage waveform, when operating
without a bootstrap capaCitor, will appear similar to the dotted line shown in FigureS.
If a bootstrap capacitor value approximately equal to the
equivalent MOSFET gate capaCitance is used, the upper
bias supply (labeled "bootstrap voltage" in Figure 6) will drop
approximately in haH when the gate is turned on. The larger
the bootstrap capaCitance used, the smaller is the instantaneous drop in bootstrap supply voltage when an upper
MOSFET is turned on.
IN~~~
BOOr STRAP
;~~~~c:S)
G:~~~:.'::E
I
~-
If the switching cycle is assumed to begin when an upper
MOSFET is gated on, then the bootstrap capacitor will
undergo a charge withdrawal when the source driver connects it to the equivalent gate-source capacitance of the
MOSFET. After this initial ·dump" of charge, the quiescent
current drain experienced by the bootstrap supply is infinitesimal. In fact, the quiescent supply current is more than
offset by the charge pump current.
The charge pump continuously supplies current to the bootstrap supply and eventually would charge the bootstrap
capacitor and the MOSFET gate capacitance back to its initial value prior to the beginning of the switching cycle. The
problem is that "ewntuallY" may not be fast enough when
the switching frequency is greater than a few hundred Hz.
Bootstrap Bla8 Supply Circuit De81gn
I
I
----~----~----
tt-_-l
I
lost on the bootstrap capacitor is exactly equal to the charge
transferred to the gate capacitance during turn-on. Note that
the very first time that the bootstrap capacitor Is charged up,
it takes much longer to do so, since the capacitor must be
charged from OV. With a bootstrap diode, the initial charging
of the bootstrap supply is almost instantaneous, since the
charge required comes from the low-side bias supply. Therefore, before any upper MOSFETs can initially be gated,1ime
must be allowed for the upper bootstrap supply to reach full
voltage. Without a bootstrap diode, this initial "charge" time
can be excessiw.
.........................
I ...............................
----~----~----FIGURE 6.
Although nOl recommended, one may employ a bootstrap
capacitor without a bootstrap diode. In this case the charge
pump is used to charge up a capacitor whose value should
be much larger than the equivalent gate-source capacitance
of the driven MOSFET. A value of bootstrap capacitance
about 10 times greater than the equivalent MOSFET gatesource capacitance is usually sufficient. Provided that suffi·
cient time elapses before turning on the MOSFET again, the
bootstrap capacitor will have a chance to recharge to the
voltage value that the bootstrap capacitor had prior to turn·
ing on the MOSFET. Assuming 20 of series resistance is in
the bootstrap change path, an output frequency of up
to
1
should allow sufficient refresh time.
5 X20XC SS
A bootstrap capacitor 10 times larger than the equivalent
gate·source capacitance of the driven MOSFET prevents
the drop in bootstrap supply voltage from exceeding 10% of
the bias supply voltage during turn-on of the MOSFET.
When operating without the bootstrap diode the time
required to replenish the charge on the bootstrap capacitor
will be the same time as it would take to charge up the equiv·
alent gate capacitance from OV. This is because the charge
For high frequency applications all bootstrap components,
both diodes and capacitors, are required. Therefore, one
must be familiar with bootstrap capacitor sizing and proper
choica of bootstrap diode.
Just after the switch cycle begins and the charge transfer
from the bootstrap capacitor to the gate capacitance is complete, the voltage on the bootstrap capacitor Is the lowest
that it will ewr be during the switch cycle. The charge lost on
the bootstrap capacitor will be wry nearly equal to the
charge transferred to the equivalent gate-source capacitance of the MOSFET as shown in Equation 1.
(EQ.1)
where:
VBS1 = Bootstrap capacitor voltage just after refresh
V9S2 • Bootstrap voltage immediately after upper turn-on
CBS =Bootstrap Capacitance
Oa • Gate charge transferred during turn·on
Were it nOl for the internal charge pump, the voltage on the
bootstrap capacitor and the gate capacitor (because an
upper MOSFET is now turned on) would ewntually drain
down to zero due to bootstrap diode leakage current and the
very small supply current associated with the level·shifters
and upper gate driver sub-circuits.
In PWM switch-mode, the switching frequency is equal to
the reciprocal of the period between successlw turn-on (or
turn-off) pulses. Between any two turn·on gate pulses exists
one turn-off pulse. Each time a turn-off pulse is issued to an
upper MOSFET, the bootstrap capacitor of that MOSFET
begins its "refresh" cycle. A refresh cycle ends when the
11·280
Application Note 9405
upper MOSFET is turned on again, which varies depending
on the PWM frequency and duty cycle. As the duty cycle
approaches 100%, the available 'off-time", toFF approaches
zero. Equation 2 shows the relationship between !oFf; fPWM
and the duty cycle.
tOFF '" (1 - OC)/fpWM
(EO.2)
As soon as the upper MOSFET is turned off, the voltage on
the phase terminal (the source terminal of the upper MOSFET) begins its descent toward the negative rail of the high
voltage bus. When the phase terminal voltage becomes less
than the Vee voltage, refreshing (charging) of the bootstrap
capacitor begins. As long as the phase voltage is below Vee
refreshing continues until the bootstrap and Vee voltages
are equal.
The off-time of the upper MOSFET is dependent on the gate
control input signals, but it can never be shorter than the
dead-time delay setting, which is set by the resistors connecting HOEL and LOEL to Vss. If the bootstrap capacitor is
not fully charged by the time the upper MOSFET turns on
again, incomplete refreshing occurs. The designer must
insure that the dead-time setting be consistent with the size
of the bootstrap capacitor in order to guarantee complete
refreshing. Figure 7 illustrates the circuit path for refreshing
the bootstrap capacitor.
•tt1r..~9.f.l!"fI"'·""'·""1
AHB
ALS
Vss
HIGH VOLTAGE BUS••• ~!!!I!.
TO 11-510£
OF
I
H.aRIOOE
!
i
~
nIUII. .:
TO "11-510£"
SUPPLY
BYPASS
CAPACITOR
OFH.aRIDGE
NOTE: Only.A-side" of H-bridge Is Shown lor Simplicity.
Arrows Show Bootstrap Charging Path.
The effects of reverse leakage current associated with the
bootstrap diode and the bias current associated with the
upper gate driYe circuits also affect bootstrap capacitor sizing. AI. the instant that the upper MOSFET turns on and its
source voltage begins to rapidly rise, the bootstrap diode
becomes rapidly reverse biased resulting in a reverse recovery charge which further depletes the charge on the bootstrap capacitor. To completely model the total charge
transferred during turn-on of the upper MOSFETs, these
effects must be accounted for, as shown in Equation 3.
Q G + Q RR +
C
_
SS -
(IOR+IQSS)
--=--7,-:;;::..:;....
PWM
(EO.3)
VSS1 - VeS2
where:
lOR .. Bootstrap diode reverse leakage current
lass "" Upper supply quiescent current
ORR = Bootstrap diode reverse recovered charge
~ .. Turn-on gate charge transferred
fPWM .. PWM operating frequency
V as1 .. Bootstrap capacitor voltage just after refresh
VBS2 .. Bootstrap capacitor voltage just after upper turn on
Cas .. Bootstrap capacitance
From a practical standpoint, the bootstrap diode reverse
leakage and the upper supply quiescent current are negligible, particularly since the HIP4081 A's internal charge pump
continuously sources a minimum of about 3Oj.LA. This current
more than offsets the leakage and supply current components, which are fixed and not a function of the switching frequency. The higher the switching frequency, the lower is the
charge effect contributed by these components and their
effect on bootstrap capacitor sizing is negligible, as shown in
Equation 3. Supply current due to the bootstrap diode recovery charge component increases with switching frequency
and generally is not negligible. Hence the need to use a fast
recovery diode. Diode recovery charge information can usually be found in most vendor data sheets.
For example, if we choose a Harris IRF520R power
MOSFET, the data book states a gate charge, Qg, of 12nC
typical and 18nC maximum, both at Vos
12V. Using the
maximum value of lBnC the maximum charge we should
have to transfer will be less than 1BnC.
=
a Generailnstrument UF4002, l00V, fast recovery.
1A, miniature plastic rectifier is used. The data sheet giYes a
reverse recowry time of 25ns. SInce the recovery current
waveform is approximately triangular, the recovery charge can
be approximated by takilg the product of half the peak reverse
current magnitude (lA peak) and the recovery time duration
(25ns). In this case the I'8CO\'9ry charge should be 12.5nC.
Suppose
FIGURE 7. BOOTSTRAP CAPACITOR CHARGING PATH
The bootstrap charging and discharging paths should be
kept short, minimizing the inductance of these loops as mentioned in the section, "Lower Bias Supply Design".
Bootstrap Circuit Design - An Example
Equation 1 describes the relationship between the gate
charge transferred to the MOSFET upon turn-on, the size of
the bootstrap capacitor and the change in voltage across the
bootstrap capacitor which occurs as a result of turn-on
charge transfer.
Since the internal charge pump offsets any possible diode
leakage and upper drive circuit bias currents, these sources
of discharge current for the bootstrap capacitor will be
ignored. The bootstrap capacitance required for the example
above can be calculated as shown in Equation 4, using
Equation 2.
C
11-281
_ lBnC + 12.5nC
12.0-11.0
BS -
(EO. 4)
Application Note 9405
Therefore a bootstrap capacitance of O.033I1F will result in
less than a 1.0V droop in the voltage across the bootstrap
capacitor during the turn-on period of either of the upper
MOSFETs. If typical values of gate charge and bootstrap
diode recovered charge are used rather than the maximum
value, the voltage droop on the bootstrap supply will be only
aboutO.5V
Power Dissipation and Thermal Design
One way to model the power dissipated in the HIP4081A is
by lumping the losses into static losses and dynamic (switching) losses. The static losses are due to bias current losses
for the upper and lower sections of the IC and include the
sum of the Icc and 100 currents when the IC is not switching.
The quiescent current is approximately 9mA. Therefore with
a 12V bias supply, the static power dissipation in the IC is
slightly over 100mW.
The dynamic losses associated with SWitching the power
MOSFETs are much more significant and can be divided into
the following categories:
•
low Voltage Gate Driw (charge transfer)
•
High Voltage lewl-shifter (V-I) losses
•
High Voltage lewl-shifter (charge transfer)
In practice, the high IIOlIage level-shifter and charge transfer
losses are small compared to the gate drive charge transfer
losses.
The more significant low IIOltage gate drive charge transfer
losses are caused by the movement of charge in and out of
the equivalent gate-source capaCitor of each of the 4 MOSFETs comprising the H-bridge. The loss is a function of
PWM (switching) frequency, the applied bias IIOltage, the
equivalent gate-source capacitance and a minute amount of
CMOS gate charge internal to the HIP4081A. The low voltage charge transfer losses are given by Equation 5.
P SWlO
= fpWM x (OG + 0IC) x V BIAS
(Ea. 5)
The high IIOltage lewl-shifter power dissipation is much
more difficult to evaluate, although the equation which
defines it is simple as shown in Equation 6. The diffICUlty
arises from the fact that the level-shift current pulses, ION
and IOFF' are not perfectly in phase with the voltage at the
upper MOSFET source terminals, V SHIFT due to propagation
delays within the IC. These time-dependent source IIOltages
(or ·phase" voltages) are further dependent on the gate
capacitance of the driven MOSFETs and the type of load
(resistiw, capacitive or inductive) which determines how
rapidly the MOSFETs turn on. For example, the lewl-shifter
ION and IOFF pulses may come and go and be latched by the
upper logic circuits before the phase voltage even moves.
As a result, little lewl-shift power dissipation may result from
the ioN pulse, whereas the IOFF pulse may have a significant
power dissipation associated with it, since the phase IIOltage
generally remains high throughout the duration of the ioFF
pulse.
(Ea. 6)
P SHIFT
= TIJT0 (ION (t) + IOFF (I) ) x V SHIFT (I) x dt
Lastly, there is power dissipated within the IC due to charge
transfer in and out of the capacitance between the upper
driver circuits and Vss. Since it is a charge transfer phenomena, it closely resembles the form of Equation 5, except that
the capacitance is much smaller than the equivalent gatesource capacitances associated with power MOSFETs. On
the other hand, the IIOltageS associated with the lewl-shifting function are much higher than the IIOltage changes experienced at the gate of the MOSFETs. The relationship is
shown in Equation 7.
PTUB
=
CTUBxV~HIFTxfpWM
(Ea. 7)
The power associated with each of the two high voltage tubs
in the HIP4081A derlwd from Equation 7 is quite small, due
to the extremely small capacitance associated with these
tubs. A "tub" is the isolation area which surrounds and isolates the high side circuits from the ground referenced circuits of the IC. The important point for users is that the
power diSSipated is linearly related to switching frequency
and the square of the applied bus voltage.
The tub capacitance in Equation 7 varies with applied voltage, VSHIFT' making its solution difficult, and the phase shift
of the ION and IOFF pulses with respect to the phase IIOltage,
VSHIFT, In Equation 6 are difficult to measure. Even the ale in
Equation 5 is not easy to measure. Hence the use of Equation 5 through Equation 7 to calculate total power dissipation
is at best diffICUlt. The equationS do, howswr, allow users to
understand the significance that MOSFET choice, switching
frequency and bus voltage play in determining power dissipation. This knowledge can lead to corrective action when
power dissipation becomes excessive.
Fortunately, there is an easy method which can be used to
measure the components of power dissipation rather than
calculating them, except for the tiny "tub capacitance" component.
Power DiSSipation, the Easy Way
The average power dissipation associated with the IC and
the gate of the connected MOSFETs can easily be measured using a signal generator, an awraging milliameter and
a voltmeter.
Low Voltage Power DiSSipation
Two sets of measurements are required. The first set uses
the circuit of Figure 8 and evaluates all of the low IIOltage
power dissipation components. These components include
the MOSFET gate charge and internal CMOS charge transfer losses shown in Equation 5 as weH as the quiescent bias
current losses associated with the IC. The losses are calculated wry simply by calculating the product of the bias voltage and current measurements as performed using the
circuit shown in Figure 9. For measurement purposes, the
phase terminals (AHS and BHS) for both A and B phases
are both tied to the chip common, Vss terminal, along with
the tower source terminals, ALS and BlS. Capacitors equal
to the equivalent gate-source capacitance of the MOSFETs
11-282
Application Note 9405
are connected from each gate terminal to Vss. The value of
the capacitance chosen comes from the MOSFET manufacturers data sheet. Notice that the MOSFET data sheet usually gives the value in units of charge (usually nanacoulombs) for different drain-source voltages. Choose the
drain-source voltage closest to the particular dc bus voltage
of interest.
Simply substituting the actual MOSFETs for the capacitors,
CL , doesn't yield the correct average current because the
Miller capacitance will not be accounted lor. This is because
the drains don't switch using the test circuit shown in
Figure 8. Also the gate capacitance of the devices you are
using may not represent the maximum values which only the
data sheet will provide.
;;c500
l..,,;'"
!.2oo r- ~.
l..,,;'" I...........
!i: 100 r- 1O,OOO
1 / l...",..o' l..,,;'"
II! so r- 3,000 '\
1/ l...",..o' l..,,;'"
:3 20 r- 1,000, 1,\ \
I-'
1/ l..,,;'" 1 /
:! 10 rl..,,;'" 1/
I-'
'\
IV'
100
iii 5 r-
~
~
2
V
0.5
I-"" V
~ 0.2
0.1
~ V"'" l..,,;'"
",
~ l..,,;'"
",
1/\
V- I-"
......
1
.......
2
......
..... 11"""
5
10
20
so 100 200
SWITCHING FREQUENCY (kHz)
500 1000
FIGURE 9. LOW VOLTAGE BIAS CURRENT VI FREQUENCY
AND LOAD CAPACITANCE
12V
rL11J1 .......---+-i
CL • GATE LOAD CAPACITANCE
FIGURE 8. LOW VOLTAGE POWER DISSIPATION TEST
CIRCUIT
VBU8
(OVDC TO IOVDC)
The low voltage charge transler switching currents are
shown in Figure 9. Figure 9 does not include the quiescent
bias current component, which is the bias current which
flows in the IC when switching is disabled. The quiescent
bias current component is approximately lOrnA. Therefore
the quiescent power loss at 12V would be l2OmW. Note that
the bias current at a given switching frequency grows almost
proportionally to the load capacitance, and the current is
directly proportional to switching frequency, as previously
suggested by Equation 5.
High Voltage Power Dissipation
CL. GATE LOAD CAPACITANCE
T
V
FIGURE 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST
CIRCUIT
Figure 11 shows that the high voltage level-shift current varies directly with switching frequency. This result should not
be surprising, since Equation 6 can be re-arranged to show
the current as a function of frequency, which is the reciprocal
of the switching period, 1fT. Notice that the current increases
somewhat with applied bus voltage. This is due to the finite
output resistance of the level-shift transistors in the IC.
1000
The high voltage power dissipation component is largely
comprised of the high voltage level-shifter component as
described by Equation 6. All of the diffICulties associated
with the time variance of the ION and IOFF pulses and the
level shift voltage, VSHIFT, underthe integrand in Equation 6
are avoided. For completeness, the total loss must include a
small leakage current component, although the latter is usuaUy smaller compared to the level-shifter component. The
high voltage power loss calculation is the product of the high
voltage bus voltage level, VBUS, and the average high voltage bus current, leus, as measured by the circuit shown in
Figure 10. Averaging meters should be used to make the
measurements.
500
l200
if]
V
100
Ii so
i3
Ii;
~
§
~
I
2
r--- t-..
~ t?< =.....
r-- 1"--
--
2
~
-0
~z
~
Q.
«
IOV
IOV
r-40V
20Y
I
10 20
so 100 200
SWITCHING FREQUENCY (kHz)
SOO 1000
FIGURE 11. HIGH VOLTAGE LEVEL-SHIFT CURRENT YI
FREQUENCY AND BUS VOLTAGE
11-283
z
o
~w
-II)
()~
~~
20
10
V
v
Application Note 9405
Layout Problems and EHects
Quick Help Table
In fast switching, high frequency systems, proper PC board
layout is crucial. to consider PCB layout. The HIP4081A
pinout configuration encourages tight layout by placing the
gate drive output terminals strategically along the right side
of the chip (pin 1 is in the upper left-hand corner). This pr0vides for short gate and source return leads connecting the
IC with the power MOSFETs.
The quick help table has been included to help locate solutions to problems you may have In applying the HIP4081A.
Always minimize the series inductance in the gate drive loop
by running the gate leads to the MOSFETs over the top of
the source return leads of the MOSFETs. A double-sided
PCB makes this easy. The PC board separates the traces
and provides a small amount of capacitance as well as
reducing the loop inductance by reducing the encircled area
of the gate drive loop. The result is reduced ringing which
can similarly reduce drain current modulate in the MOSFET.
The table below summarizes some layout problems which
can occur and the correctill8 action to take.
PROBLEM
EFFECT
Low chip bias voltages May cause power MOSFETs to exhibit ex(Vee and Voo)
casslve ROSON' possibly overheating
them. Below 6 V, the IC will not function
proparly.
High chip bias voItag- At Voo voltages above about 12V, The
es (Vee and Voo)
charge pump HmIIer will begin to operate,
In tum drawing heavier Voo current
above 16V, Breakdown may occur.
Bootstrap capacltor(s)
too small
May cause Insufficient or soft charge d&livery to MOSFETs at turn-on causing
MOSFET overheating. Charge pump will
pump charge, but possIbiy not quickly
enough to avoid excessive switching 1osses.
The Bootstrap circuit path should also be kept short. This
minimizes series inductance that may cause the voltage on
the boot-strap capaCitor to ring, slowing down refresh or
causing an overvoltage on the bootstrap bias supply.
Bootstrap capacltor(s)
too large
Dead time may need 10 be Increased In order to allow sufficient bootstrap refresh
time. The alternative 18 to decrease bootstrap capacltanca.
A compact power circuit layout (short circuit path betwean
upperllower power switches) minimizes ringing on the phase
lead(s) keeping BHS and AHS voltages from ringing excessively below the Vss terminal which can cause excessive
charge extraction from the substrate and possible malfunction of the IC.
RoATE too small
Smaller values of RoATE reduces turn-onl
off times and may cause excessive em!
problems. Incorporating a series gate
resistor with an antl-parallel diode can
solve EMI problem and add 10 the dead
time, reducing shoot-through tendency.
RoATE too large
Increases switching losses and MOSFET
heating. If anll-parallel diode mentioned
above 18 In backwards, turn-off time Is increased, but tum-on time Is not, possibly
causing a shoot-through fault
Dead time too smaR
Reduces "refresh" time as well as dead
time, with Increased shoot-through
tendency. Try Increasing HDEL and LOEL
resistors (don't exceed 25OKn.)
PROBLEM
EFFECT
Bootstrap circuit path
too long
Inductance may cause voltage 011 bootstrap capacitor 10 ring, slowing down
refresh and/or causing an overvoltage
011 !he bootstrap bias supply.
Lack 01 tight power
circuit layout (long
circuit path between
upper/lower
power
swllches)
Can cause rInglng 011 the phase lead(s)
causing BHS and AHS 10 ring excessively below the Vss tsnnInaI causing
excessive charge extraction from the
substrate and possible mallunctlon 01
!heIC.
Excessive gate lead
lengths
Can cause gate voltage ringing and
subsequent modulation 01 tile drain current and impairs !he effec~ of !he
sink driver from minimizing !he miller effect when an opposing switch 18 being
rapidly turned 011.
HIP4081A IC gets too
Reduca bus voltage, switching frequency,
hot
choose a MOSFET with lower gate capacItanca or reduce bias voltage (If It 18 not
below 6 V 10 12V).
Shed some of the low voltage gate switchIng losses In !he HlP4081A by placing a
small amount of series reslslanca In the
leads going 10 !he MOSFET gates, thereby transferring some of the IC losses 10
!he resistors.
Lower MOSFETs tum
but upper
MOSFETs don't
Check that the HEN terminal Is not tied
low lnadvertenUy.
OIl,
11-284
Application Note 9405
Application Demonstration PC Board
Harris has developed a demonstration PC board to allow
fast prototyping of numerous types of applications. The
board can be used to aid in characterizing the HIP4081A
device under actual operating conditions.
Figure 12 and Figure 13 show the silkscreen and the schematic indicating component placement, respectively, for the
HIP4080AllA demo board. Note that the board can be used
to evaluate either the HIP4080A or the HIP4081A, simply by
changing a few jumpers. Refer to the appropriate application
note for instructions on jumper placement.
The PC board incorporates a CD4069UB to "buffer" inputs to
the HIP4081A. JMPR5, resistors R27 and R28, and capacitor, C7 must be removed in order to implement the power up
reset circuit described in this application note and in the
HIP4081A data sheet, File Number 3659. Depending on the
pOSitions of JMPRl-4, one can operate the driver as two
separate half-bridges or an H-bridge.
Consistent with good design practice, the +12V bias supply
is bypassed by capacitors C6 and C5 (at the IC terminals
directly). Capacitor C6 is a 4.711F tantalum, designed to
bypass the whole PCB, whereas C5 is a 0.2211F, deSigned to
bypass the HIP4081A. The bootstrap capacitors, C3 and C4,
and the high voltage bus bypass capacitors are O.lI1F, 100V
ceramic. Ceramic is used here because of the low inductance required of these capacitors in the application. The
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
@t
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
•••
•••
bootstrap diodes are lA, fast recovery (tAR = 200ns), 100V,
to minimize the charge loss from the bootstrap capacitors
when the diodes become reverse-biased.
The MOSFETs supplied with the demo board is a Harris
IRF520, 100V, 9A device. Since it has a gate charge of
approximately 12nC, 100 gate resistors, R21 through R24,
have been employed to deliberately slow down turn-on and
turn-off of these switches. Finally, R33 and R34 provide
adjustment of the dead-time. These are 500kn normally set
for 100kn, which will result in a dead-time of approximately
50ns. R30 and R31 provide space for optional shunt resistors (0.1 n, 2W, 2%, wirewound) which can be used to provide a current-limiting Signal, if desired. R30 and R31 should
be replaced with wire jumpers if resistors are not used.
Finally, space has been provided for filter reactors, L 1 and
L2, and filter capacitors, Cl and C2, to provide filtering of
PWM switching components from appearing at output terminals AO and BO. To facilitate placement of user-defined ICs,
such as op-amps, comparators, etc., space for 3 fourteen
pin standard width ICs has been reserved at the far left side
of the demo board. The output terminations of the 3 optional
locations are wired to holes which can be used to mount
application-specific components, easing the process for
building up working amplifiers for motor controls and audio
amplifiers .
••
••
••
••
••
••
••
••• •••
••
••••••
•• ••
••
••
••
••••
Z
o
-tI)
tcw
~15
KZ
Q.
cC
FIGURE 12. EVALUATION BOARD SILKSCREEN
11-285
IN2 IN1
PaNER SECTION
+12V
CONTROL LOGIC
SECTION
I
?-
,I
~I
R2t
r-------~--~---O~
--;r-!+
i
Jel
R21
DRIVER SECTION
CR2
HIP4080AI81 A
U1
C4
iiiOI 20
R22
0
xxxx
+---->r x n
,
;b,
AO
0 BO
:g
~
II)
go
::s
~
0>
a:2'
R24
~
~
CR1
C3
CD4068UB
CY
R30
R31
I ,
cs-!-
o
ALS
BLS
NOTES:
DEVICE CD4069UB PIN 7. COM, PIN 14- +12Y.
CD4068UB
FIGURE 13. HIP4081A EVALUATION PC BOARD SCHEMATIC
0
COM
INTELLIGEN 12
POWERICs
HARRIS QUALITY AND RELIABILITY
PAGE
HARRIS QUALITY ........................................................................ .
12-2
Introduction ...........................................................•.......•.....•...
12-2
The Role of The Quality Organization' ....................................•...................
12-2
The Improvement Process ................ '" ... '" , ....................•..........•.......
12-2
Designing for Manufacturability....•...............•......................•........•.........
12-2
Special Testing .•.•......................................................................
12-4
Harris Semiconductor Standard Processing Flows .......•..............................•....•••
12-5
Controlling and Improving the Manufacturing Process - SPC/DOX ...•.............................•
12-7
Average Outgoing Quality (AOQ) ..•...•........•..••......•.••........•...................••
12-8
Training .............................•.......................................•..........
12-8
Incoming Materials .........••.....•......................•.......•..........•...........•
12-8
Calibration Laboratory ••••.•....•..•...•..•..•.••.......•••......••...............••...•••
12-10
Manufacturing Science - CAM, JIT, TPM ........•.........•..•.....•••.•...........•..•.......
12-10
HARRIS RELIABILITY . .................................................................... .
12-11
Introduction ..........................•..............•..•........................•....•.•
12-11
Reliability Engineering ........••......•...............•.........••......•.•............•..
12-11
Design for Reliability (Wear-Out Characterization) ....................••......................•..
12-12
ProcesslProductlPacl$5k
D Failure Analysis
D Other
Impact of Failed Units on Customer's Situation:
Customer Contact with Specific Knowledge of Rejects
Name
Position
Phone
D DC Failure
D Short
DOpen
D Power Drain
D Input Level
Pin Number
D ACFailure
Power Supply Voltages = _ _V
Input Voltages VIH = _ _ _V
Pin Number_ _ _
Failing characteristics
D Leakage
D Output Level
VIL= _ _ _V
D RAM and ROM Failures (ROM failures must be
returned with a good master unit if failure
analysis is requested).
Address of Failing Location
Describe Pattern Used (If not standard
patterns, give very complete description
including address sequence).
Include timing diagrams and circuit schematic if available.
ROM Programmer Used (If purchased
unprogrammed)
Conformal Coating (MfgrlModel)
Additional Comments:
FIGURE 7. PFAST ACTION REQUEST
12·16
INSTRUCTIONS FOR COMPLETING PFAST ACTION REQUEST FORM
The purpose of this fonn is to help us provide you with a more accurate, complete, and timely response to failures which may occur. Accurate
and complete infonnation is essential to ensure that the appropriate corrective action can be implemented. Due to this need for accurate and
complete infonnation, requests without a completed PFAST Action Request fonn will be returned.
Source of Problem:
This section requests the product How leading to the failure. Mark an 'X' in the appropriate boxes up to and including the step which detected
the failure. Also mark an 'X' in the appropriate box under "ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS?' to indicate whether
this is a rare failure or a repeated problem.
Example 2. 100 out of the SOO units shipped were tested at incoming and all passed. The units were installed into boards and the
boards passed. The boards were installed into the system and the
system failed immediately when turned on. There were 3 system
failures due to this part. The customer frequently has failures of
this Harris device. The 3 units were not retested at incoming.
Example 1. No incoming electrical test was perfonned; the units
were installed onto boards; the boards functioned correctly for rvo
hours and then 1 unit failed. The customer rarely has a failure due
to the Harris device.
SOURCE OF PROBLEM
SOURCE OF PROBLEM
(I!otor ....oquw:oof .._a ... b.... "..u..t)
(I!otor .... oquw:ool ..... a",u... ,...w.ll
1. VIS\W.JMECIIANICAL
1. VISI1AI./.MBCllANlCAL
2. blcoMING 'Il!ST
II NOT PliRFORldllD
IJ 100% 'I'asTEI>
IJ SAMPlJ! 'I'asTEI>
No. 'I'asTEI> _ _ _ No. OF RliIBC13 _ __
2. INcoMING '!liST
IJ DIlSCRIBS _ _ _ _ _ _ _ _ _ _ __
IJDIlSCRIBS
No. 'I'asTEI> ...11111..-- No. OF Ri!Jl!cm---1l....-
ARE RIlSlILllI REPRESIiNl'A11VB OF PRBVIOlll LOlli?
IJ
ARE RIlSlILllI RliPRI!SENl'A11VB Of PRBVIOlll LOTS?
IJ m
\'ES
II YES
IJm
3. IN I'ROcIis!IIMANUJ\Cl'URINO F AlLIlIUI
III BOARD 'Il!sT
II SYmIM 'Il!ST
How MANY UNI1lI PAlLED? _ _3_ _
FAILED AfTER _ _
O_ HOUR3 01' TESTINO
WAS UNlT RETBSTBD AT INCOMING INSPEcnoN'l
3. IN I'RC<:ll9sJMANuJ\Cl'URlNO F AlLIlIUI
II BOARD 'Il!ST
IJ SYmIM 'Il!ST
How MANY UNI1lII'AILED? _ _1__
FAILED AfTER _ _
.2_ HOUR3 OF TESTINO
WAS UNlT l1Ii'IIiS1'ED AT INCOMING lNSI'EcnoN'l
IJ \'ES
II m
IJYES
II m
YES
II YES
4. FIELD F AlLIlIUI
FAILED AfTER _ _ HOUR3 OPERAllON
ESTIMATED FAILURE RATB _ _ _% PER _ __
END USER
MIN. _ _"C
~.O~ER
IJm
4. FIELD FAlLIlIUI
FAILED AfTER _ _ HOIJRllOPERAllON
ESTIMATED PAILIlIUI RATB _ _ _% PER _ _ _
ENDUSIiR
LocAllON_:_--::::,.-
AVE. _ _"C
11m
ARE RBSULTS RliPRI!SENl'AllVE 01' PRBVIOlll LOTS?
ARE RESULllI REPRESIiNl'A11VB Of PRBVIOlll LOD?
IJ
IJ NOT PERI'ORldllD
II SAMPIJ! 'I'asTEI>
IJ 100% 'I'asTEI>
MAx._ _"C
MIN. _ _"C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LocAllON
AVE. _ _"C
MAx._ _·C
'.O~
Action Requested by Customer:
Tbis section should be completed with the customer's expectations. This infonnation is essential for an appropriate response.
Reason for Electrical Reject:
This section should be completed if the type of failure could be identified. If this information is contained in attached customer correspondence
there is no need to transpose onto the PFAST Action Request form.
PFAST REQUIREMENTS
The value of returning failing products is in the corrective actions that are generated. Failure to meet the following requirements can cause erroneous conclusion and corrective action; therefore, failure to meet these requirements will result in the request being returned. Contact the local
PFAST Coordinator if you have any questions.
Units with conformal coating should include the coating manufacturer and model. This is requested since the coating must be removed in order
to perform electrical and hermeticity testing.
1. Units must be returned with proper ESD protection (ESD-safe shipping tubes within shielding boxlbag or inserted into conductive foam
within shielding boxlbag). No tape, paper hags, or plastic bags should be used. This requirement ensures that the devices are not damaged
during shipment back to Harris.
2. Units must be intact (lid not removed and at least part of each package lead present). This is a requirement since the parts must be intact in
order to perfonn electrical test. Also, opening the package can remove evidence of the cause of failure and lead to an incorrect conclusion.
3. Programmable parts (ROMs, PROMs, UVEPROMs, and EE PROMs) must include a master unit with the same pattern. This requirement is
to provide the pattern so all failing locations can be identified. A master unit is required if a failure analysis is requested.
FIGURE 7. PFAST ACTION REQUEST (Continued)
12-17
Q>
ZI-
va
1000ITABS
12-26
=
1 - exp - [8760110.399.591.9)
0.00084 or 0.084% per year
Reliability Report RR001
The improvement in the HVIC reliability when the operating
chip temperature is lowered in the application is shown in
Figure 6. For example, this shows that the annual reliability
is improved about 4 to 1 when the operating chip (die) tem·
perature is lowered to +750 C instead of +100oC. Similarly
there is an improvement of over 12 to 1 when the operating
chip temperature is lowered to +55 0 C.
Conclusions
1. The average failure rate during the first year is expected
to be 0.00962%11000 hours or 96.2 FITs when the appli·
cation operating chip temperature is at +1000C and 25.4
FITs at +75OC and 7.6 FITs at +550 C. Note: 1 FIT .. 1 Fail·
urel1011 hours.
2. Similarly, with continued favorable quarterly monitoring
test results, the expected average failure rate would decrease from 96.2 to 72.4 FITs after the second year and
to 58 FITs after the third year at a chip temperature of
+100OC.
.11
+1000 C
'\.
3. There is a good chance that the reliability could be better
than the predictions since short term evaluation tests
showed that samples of HVIC's are capable of withstand500V and
ing leakage current measurements at V
+150OC. This is 150 volts and +50oC above the applica·
tion operating conditions of 350V and +1000 C.
I\,
=
\
1\+7S0 C
Acknowledgment
\
The author wishes to acknowledge the analytical contribu·
tions and encouragement for this report from Pete Shafer,
Ray Dyer, and Jack Essom.
1\
,
References
I\:
8 I-- I- SCALE: 1 OOO/TASS
7
1. E.A. Herr et al "Techniques for the Control of Integrated
Circuit Quality and Reliability", Technical Report AFML·
TR-67-147, June 1967 Air Force Materials Laboratory,
Wright Patterson AFB, Ohio 45433.
r~
+5SOC
6
2.7
2.8
2.11
CHIP TEMPERATURE ("C)
3.0
3.1
FIGURE 6. REUABILITY IMPROVEMENT WITH A DECREASE
IN OPERATING CHIP TEMPERATURE
2. E.A. Herr, A. Poe and A. Fox "Reliability Evaluation and
Prediction for Discrete Semiconductors", IEEE Transactions on Reliability, August 1980, Volume R-29 Number
3, Catalogue No. ISSN-0018-9529, pp 208-216.
12-27
Intelligent Power Products
RR002
Reliability Report
April1992
CONCURRENT DESIGN, TEST AND RELIABILITY
ENGINEERING OF POWER ASICs
By Erwin A. Herr
Introduction
A program was initiated in July 1987 to develop a new Intelligent Power ASIC chip technology using state-of-thlrart type
components and processing. This process utilized mixed
signal technology that was optimized for motorl motion
control. power supply and interface applications. The first
application chosen was a DCIDC converter chip which was
mounted in a module with an output of 5 VDC and a current
of 10 amperes continuous and 20 amperes peak. The environment for this application was to be in office equipment. for
commercial and industrial usage.
The reliability objective of this product was very aggressive
in terms of both operating conditions and failure rate. Accelerated testing techniques were used to demonstrate that the
failure rate objective was achieved.
Technical Strategy for DeSign, Test and
Reliability Engineering
The Intelligent Power ASIC technology had to produce chips
which could be designed and developed in a minimum of
time. be cost effective. easily manufactured as well as being
very reliable. Normally this would be accomplished with
mature designs and products that had been manufactured
over a period of time with known capabilities and established
reliability. However. since this was to be a state-of-the-art
technology a new approach had to be taken in order to meet
the required time table. These requirements led to the concept of concurrent product. test and reliability development.
An overview of the major activities of this program is illustrated in Figure 1. It is to be noted that this starts with product concept phase and sequences through a number of the
major steps up tathe production phase. It can also be seen
that there were early and concurrent activities in Design.
Test and Reliability Engineering. This required the ultimate in
communication. cooperation. team work and leadership in
many technical areas. This resulted in parallel actions in several areas which traditionally were performed in series. The
concurrent action approach not only saved lime and cost but
it inspired commitment for success from the contributors.
PRODUCT CONCEPT AND APPLICATIONS
PRODUCT FUNCTIONAL SPECIFICATIONS
PROGRAM PLAN AND DEVELOPMENT SCHEDULE
TEST DEVELOPMENT
ENGINEERING
ADVANCED DESIGN AND DEVELOPMENT
ENGINEERING
ADVANCED RELIABILITY
ENGINEERING
• Accelerated reliability program plan
• Test methods & software
design
• Product and process development plan
• Test hardware design
• Mask design of WATs. TEGs and Macros
• Design and construct reliability test
equipment
• Characterization of WATs.
TEGs & Macros
• Process samples of TEGs and Macros
• Accelerated reliability testing of TEGs
and Macros
• Analysis of results
- Cerrective actions
• Analysis of results
- Design out defects If design related
- Process improvements where applicable
• Analysis of results
- Failure Analysis
- Recommend corrective action
• Characterization & eveluation
• Process samples of TEGs. Macros and prototype
ASICs with applicable Improvements
• Accelerated reliabUity testing and
Elll8luatlon of Improved TEGs, Macros
and prototype ASICs
• Characterization & evaluation
• Design of Relmon and production ASICs
• Accelerated reliability testing and
evaluation
• Characterization fer production
• Technical Review and approval production
• Accelerated testing 01 Relmon and
production ASICs
Copyright © Harris Corporation 1991
12-28
Reliability Report 002
HIGH
TEMPERATURE
BIAS
OPERATING
LIFE AND POWER
CYCLING
DAMP HEAT
BIAS
Die Bulk and Surface
Stability
X
X
X
Sealed Junction Integrity
X
X
X
X
Thermal. Mechanical
Environmental Stability
X
X
X
X
X
Long Term Reliability
X
X
X
X
X
DEVICE PROPERTIES
TEMPERATURE
CYCLE
ELECTROMIGRATION
FIGURE 2. TESTS REQUIRED TO ASSURE DEVICE PROPERTIES
This concept of Concurrent Engineering meant that. as the
building blocks of the Power ASIC technology were being
developed. they were independently characterized and
assessed for reliability under accelerated test conditions.
These building blocks included new component structures
as well as new Macro circuits for the primary functions of the
Chip. In order to evaluate these building blocks under accelerated test conditions an analysis was made of the desired
properties and the accelerated stresses that would assure
them. The test matrix in Figure 2 shows the stresses chosen
on this program. The objectives of each of the accelerated
stresses are shown in Figure 3. Based on this analysis and
previous experience the stresses chosen included High
Temperature Bias (HTB). Operating Life. Power Cycling.
Damp Heat Bias (DHB). Temperature Cycling and Electromigration testing. The overall objective of this early testing was
to provide rapid reliability information feed- back to the
designers so that they could select the most reliable struclures for the new Macro designs.
The approach taken was to use Test Element Groups
(TEGs)!1]. that were packaged in a manner similar to that
which was planned to be used in production. These TEGs
included structures of elements such as NPN & PNP bipolar
transistors. NMOS and PMOS transistors. LDMOS power
FET. zener diodes and electromigration test sites.
As the program progressed these elements were fabricated
on the same semiconductor wafers as the Macro and the
ASIC circuits. After packaging. the TEG devices were subjected to the same type of stresses that they would normally
see in the ASIC circuit. However. the stress levels were usually higher in order to obtain accelerated test results. For
example, samples of the components were subjected to
multi-level accelerated stresses of high temperature bias for
1000 to 2000 hours. High Humidity Bias or Damp Heat Bias
stresses for 1000 to 2000 hours were also used. Temperalure cycling was performed to 3000 cycles. Measurements
were made of the critical characteristics of the isolated structures initially and at several times after hours of stress. Analyses were made of the distribution of the characteristics and
the changes in critical characteristics with stress. The objective was to stress the TEGs to destruction so as to have suffieient failures for failure analysis. This allowed isolation and
identification of the failure modes and mechanisms which
suggested corrective actions. These led to improvements in
design and processing.
The Macros were similarly packaged as the TEGs and submitted to accelerated high temperature bias at +12SoC and
+ lS00C for 1000 to 2000 hours. Analysis of the failures from
these tests brought out any failure mechanisms that could
occur between the combination of structures in the functional
circuit. This allowed an in-depth evaluation of the building
block circuits for the final ASIC chip.
The production Intelligent Power ASIC chip was constructed
from the building block Macros and power switching lunctions. Samples of this type of chip were mounted in several
types of packages to evaluate the capability of the chip to
withstand electrical. temperature and environmental
stresses. One group of Power ASIC samples was subjected
to accelerated conditions of a dynamic operating life of Vin =
20VDC. Vout SV at 10 amperes DC. The junction temperature at the chip was + 12SoC and the duration of the test was
2000 hours. Another group was subjected to a power cycling
test for 2000 hours at maximum operating life conditions with
a 10 minute ·on" and a 10 minute ·off" cycle. In a third group
the chip was similarly packaged and these devices were
subjected to 1000 to 2000 hours of Damp Heat Bias at
=
ACCELERATED
STRESSES
STRESS OBJECTIVES
High Temperature Bias
(HTB)
Ole bulk and surface stability under
electrical bias and elevated temperature conditions
Operating life and Powercycling
Die bulk and surtace stability under
electrical operation and elevated temperature conditions
Demp Heat Bias (DHB)
Device physical and surface stability
and package material compatibility
under aocelerated electrical bias.
temperature and humidity.
Temperature Cycling
Device mechanical strength and durabllily under aocelerated conditions
of Ihermal expansion and contraction.
Electromlgration
Capability of metallization runs to
withstand current In power integrated
circuits
FIGURE 3. OBJECTIVES OF THE ACCELERATED STRESSES
12-29
Reliability Report 002
+850 C 81% RH and 45 volts. A fourth group was subjected
to a temperature cycle test of 3000 cycles. In a fifth case
samples were subjected to a high temperature bias test of
60 volts on the power section and 42 volts on the control
section at a junction temperature of + 150"C for 500 hours
duration. This series of multi-level stresses was used to evaluate the combined functions of the Macros and the power
switching sections of the final Power ASIC. Reliability predictions are made based on the HTB. operating life. power
cycling and DHB test results.
The process technologies used on this program included low
and high speed bipolar and complementary MOS signal processing designs as well as combinations of bipolar and MOS
power structures. The semiconductor chips were processed
with a two level metallization system that is compatible with
plastic packaging.
Accelerated Test Results on Components,
Macros and Power ASICs
Accelerated testing was used on this Concurrent Engineering Program in order to obtain an early reliability evaluation
of the building blocks to be used to construct the Power
ASIC chip. It was imperative to obtain this information in a
minimum time in order to have an efficient design cycle.
Care was taken to choose stress levels that would accelerate the changes in characteristics caused by failure mechanisms that exist at lower stress levels. Analysis was made of
the initial distribution of critical characteristics as well as
changes in the distribution with time under stress. Comparisons were made of the accelerated test results of the components and Macros to gain the maximum information. This
helped identify the failure mechanisms for a thorough analysis of any failures obtained. It also allowed the selection and
use of semiconductor structures and processes in the final
ASIC design that were free from these sensitive mechanisms. This enabled the accelerated reliability information
and corrective actions to be in phase with the normal test
characterization of the building blocks which resulted in an
optimized design and process development cycle.
A general summary of the accelerated constant stress-intime program conducted during the concurrent product.
process and reliability development cycle is given in Figure
4. This includes the number of units tested. the unit hours of
stress and the number of failures obtained each year for the
components. Macros and ASICs. The constant stress-intime tests included high temperature bias. operating life.
power cycling and a damp heat bias test. Some interesting
observations and conclusions can be drawn from this information. It pOints out the inherent advantages of this Concurrent Engineering Program in the development of a state-ofthe-art Power ASIC semiconductor chip.
• About 24% of all the test vehicles were stressed during
1988. In the traditional serial development cycle only minimal reliability tests would occur in the first year. This saved
at least a year of program time.
• Forty three percent of all the vehicles tested were the less
complex structures; namely. TEGs or Macros. This
allowed a more thorough and effective analysis of failures
which made it easier to isolate failure mechanisms and
implement corrective actions.
• Corrective actions were implemented in the first year
when the cost of making design changes and process
improvements was at a minimum.
• Test systems for the measurement of device parameters
and accelerated stress equipment were developed and
procured early in the cycle.
• The general testing trend showed that the majority of the
Components and Macros were tested during the first year.
Long term accelerated testing (2000 hours) of the Power
ASICTM chips was completed during the second year.
• A total of 11385 vehicles were tested under acclerated
conditions during the program. A distribution of the vehicles showed that there were 25% components. 18% Macros and 57% Power ASICs.
• The trend in failure occurrence was highest in the early
years of development. but decreased dramatically in subsequent years. This gave a favorable reliability growth pattern.
• This accelerated program enabled production ASICs to be
shipped during the second year.
The accelerated tests used to evaluate components or TEGs
included high temperature bias at +1250 C and +150OC.
damp heat bias and temperature cycling. The duration of the
high temperature and damp heat bias tests was 1000 to
2000 hours. The general plan for the evaluation of the semiconductor structures used was to stress the structures in the
components at the highest bias level (20V). in the Macros at
an intermediate level (16V) and in the ASIC circuits at the
use level (12.5V).
As previously mentioned the extensive unit hours of testing
during the initial evaluation phase are summarized in Figure
4. During the latter part of this evaluation qualification tests
were run. The criteria for qualification of components was to
pass the appropriate bias tests at the accelerated temperature of +1250 C for at least 1000 hours with zero failures out
of a sample of twenty. The results of these tests on bipolar
transistors. MOS transistors. the LDMOS power FET as well
as the zener diodes are summarized in Figure 5. Bias tests
at +150"C were also performed to assess the temperature
margin for reliability on these components.
Component sample groups of transistors. zeners and the
power FETs were subjected to the accelerated test of Damp
Heat Bias at +850 C. 81 % RH and the appropriate bias for
1000 to 2000 hours. Samples of these devices were also
subjected to temperature cycling for 1000 cycles at -40°C to
+150oC. Other general evaluation tests were conducted on
special structures to measure their capability to withstand
electromigration. ESD and latch up stresses.
12-30
Reliability Report 002
COMPONENTS
UNITS TESTED
COMPONENTS
NUMBER OF FAILURES
COMPONENTS
UNIT HOURS IN (ODD'.)
160
150
130
140
110
111120
100
3 .0
~ 80
~ 70
II: 60
60
::0 40
Z
30
20
10
0
2400
2200
2000
1800
'ii 1600
II!
l1400
iii: 1200
12 1000
8:z:
...
800
!Il
zt: 600
::0
400
200
0
188.
111811
ll1l1O
1l1li1
18..
18..
YEAR
ll1l1O
1l1li1
MACRO
UNITS TESTED
.00
800
i
1l1li1
160
150
140
130
120
110
13100
1000
~
1l1li0
MACRO
NUMBER OF FAILURES
MACRO
UNIT HOURS (OOO's)
1100
l!!
1888
YEAR
1200
Q
1888
YEAR
3 1080
700
600
~
70
~ 80
500
::0 400
...
II:
ID
80
::Ii 40
::0
300
z 30
200
20
10
0
100
0
1888
1l1li0
1888
1881
YEAR
ASIC
UNITS TESTED
18..
19..
1l1li0
YEAR
18..
1l1li1
18..
1880
1881
YEAR
ASIC
NUMBER OF FAILURES
ASIC
UNIT HOURS IN (ODD's)
180
150
140
130
120
110
13100
~~
~ ::70
CC:::J
~iii
...I:S
u;
~80
II:
III
18..
1888
1880
YEAR
1881
1888
18..
1880
1881
50
~ 40
Z 30
20
10
0
CC...l
Oa:
:;:)W
11188
YEAR
FIGURE 4. CONCURRENT PRODUCT, PROCESS AND RELIABILITY DEVELOPMENT
12-31
1888
1880
YEAR
1881
Reliability Report 002
1000 HOURS FAILURESISAMPLE
TEGs
PACKAGE
HIGH TEMPERATURE BIAS
(HTB)
HTBAT+l25°C
HTB AT +1500C
NPN
16 Lead DIP
HTB.20V
0139
0120
PNP
16 Lead DIP
HTB.20V
0120
0120
PMOS
16 Lead DIP
HTB.20V
0120
0120
16 Lead DIP
HTGB.25V
0120
0120
16 Lead DIP
HTB.20V
0140
3120
16 Lead DIP
HTGB.20V
-
0120
16 Lead DIP
HTGB.25V
0120
-
Zener-A
16 Lead DIP
0.5mA
-
0120
Zener-B
16 Lead DIP
1.0V
-
0120
Zener-C
16 Lead DIP
HTB.l00mA
0120
0120
16 Lead DIP
HTB.6.5V
0120
0120
16 Lead DIP
HTB.l00mA
0120
1120
TO 218
HTB.60V
0120
1120
TO 218
HTGB.20V
NMOS
Zener-D
SAlDMOS
TOTAL
0120
0120
01259
51260
FIGURE 5. COMPONENT TEG QUALIFICATION
1000 HOURS FAILURESISAMPLE
MACRO TYPES
PACKAGE
HIGH TEMPERATURE BIAS
(HTB)
HTBAT+l25°C
HTB AT +1500C
Bandgap Voltage
Reference
16 Lead DIP
16V.+125OCV+150OC
0160
0160
MOSOPAMPA
16 Lead DIP
16V.+125OCV+150OC
0120
0120
MOSOPAMPB
16 Lead DIP
16V. +125°C/+1500C
0120
0120
Reference Current
Generator
16 Lead DIP
16V.+125OCV+l5OOC
0120
0120
Comparator A
16 Lead DIP
16V. +125OC/+150OC
0120
0120
Comparator B
16 Lead DIP
16V.+125OCV+150OC
0120
1120
Transconductance
Amplifier
16 Lead DIP
16V.+125OC/+15OOC
0120
0120
Comparator C
16 Lead DIP
16V. +125°C/+150OC
0120
018
Gate Driver
16 Lead DIP
16V.+125OCV+l5OOC
0120
0120
Oscillator
16 Lead DIP
16V.+125OCV+l5OOC
0120
0120
Voltage Regulator
16 Lead DIP
45V151V. +1250 C/+ 150°C
0120
0120
01260
11248
TOTAL
FIGURE 6. MACRO QUALIFICATION
12-32
Reliability Report 002
The eleven Macro types listed in Figure 6 were also subjected to the same type of general bias tests at elevated
temperature and damp heat that were used on the components. These are summarized In Figure 4. They were also
subjected to temperature cycling for 1000 cycles at -40°C to
+ 150°C. Again the criteria for qualification was to pass the
appropriate bias tests at the accelerated temperature of
+1250 C for at least 1000 hours with zero failures out of a
sample of twenty. The elevated temperature margin for reliability was assessed at + 150°C. The results of these tests
are summarized in Figure 6.
The failures generated during the early phase of the accelerated tests on components and Macros were particularly
important for identifying failure mechanisms for product
design and process improvements. The corrective actions
included improvements in deSign resulting from the selection
of the most reliable structures based on test results. This
timely information was used to establish practical and robust
design rules. These rules, based on early component
results, were used to design the Macros. Progressively the
design rules were further improved from the results of accelerated testing of the Macros. These improvements were
implemented into the final ASIC design.
If the failure analysis indicated that the failure mechanisms
were process related then process improvements were
implemented. These were monitored by testing the Wafer
Acceptance Test (WAT) structures on subsequent wafers to
demonstrate the improvement. From this information control
limits were established on key parameters to maintain statistical process control.
YEAR
1989
STRESS
HTOP&HTBat
+125"C,
Power cycling up
to+125°C
732
2000
1 (100 Hrs)
Damp Heat Bias
+85°C, 81% RH
231
2000
1 (24 Hrs)
TOTAL
1990
3
963
HTB at +125°C
400
1020
HTB at +125OC
1450
143
0
HTB at +15OOC
217
190
1 (170Hrs)
HTB at +15OOC
494
505
1 (118 Hrs)
HTB at + 1500C
965
122
0
TOTAL
1991
HOURS
OF
SAMPLES STRESS FAILURES
1 (484Hrs)
3
3526
HTBat+12SOC
443
126
0
HTBat+12SOC
179
1010
1 (112 Hrs)
HTB at + 1500C
100
500
1 (182 Hrs)
HTBat+15OOC
248
126
0
TOTAL
Grand Total
970
2
5459
8
FIGURE 7. POWER ASIC- QUAUFICATION
The evaluation of the Power ASIC chips included tests on
high temperature bias and operating life at a chip temperature of +1250 C, damp heat bias at +85 0 C, 81% RH and temperature cycling of 3000 cycles to the package limits of -5°C
to +105°C. The results from high temperature bias, high
temperature operating life (HTOP), power cycling and damp
heat bias were considered the primary stresses the chip
would have to endure in the application. This testing is illustrated In Figure 7. Failure analysis was used to confirm any
failures that occurred. Corrective actions were determined,
implemented and demonstrated for most of the failures. The
remaining failures, for which corrective action had not been
determined, were used in the failure rate calculation. This
information, as shown in Figure 7, was used to assess the
reliability of the Power ASIC under the application conditions.
Power ASIC Reliability Assurance
A reliability database ages very rapidly unless it is kept current. Even if no known changes are made, the database
needs a continuous flow of current data. To meet this need,
a device called the Relmon (Reliability monitor) was
designed. This device is a functional part number which is
made part of every mask set. The Relmon is used to periodically sample the process and thus update the database with
data resulting from improvements such as design rules for
more efficient layout, circuit design innovations, and process
modifications. The library based Power ASIC design
approach enables these types of changes to be made and
the database to be maintained. The volume of new part
numbers, most containing both "old' Macros and components as well as some "new" Macros and components,
allows the qualification work on the new part number to
"bridge" the new elements to the existing database. The
need to merge data relating to changes such as design rules
and process improvements is met by utilizing the Relmon as
the vehicle to bridge the data.
Every Power ASIC part which is shipped is tied to the reliability database with four connections: The qualification testing was performed on the part number. This testing is
designed to address any aspects of the part number which
are outside the bounds of the existing reliability database, for
example:
• New components or Macros.
• Components or Macros applied in a new way.
• New packaging or environmental conditions.
• Process improvements. The part number testing is performed on every part. This testing is designed to address
three elements of reliability:
• Functional test coverage to assure that all customer specifications are guaranteed.
• Reliability test coverage to assure that aU accessible portions of the chip are tested and appropriate voltage margins are applied.
• Parameter limits All parameter limits are examined to
assure that limits reflect no more than expected variations.
12-33
c>
ZI-
c:(::::i
>-
I-ID
-c:(
...Jc:(...J
:::I w
Oa:
Reliability Report 002
The WAT (Wafer Acceptance Test) testing is performed on
ell9ry wafer. This is a set of tests which must be passed for a
wafer to be accepted for part number probing. This testing is
designed to address three elements related to reliability:
Process control monitors These structures assure that the
process is within acceptable bounds.
Representative devices These structures assure at the
device lell9l that the wafer has been appropriately processed.
Representative topology test elements These structures
assure that aspects such as step coverage are under control. The Relmon (present on every wafer) is used in two
ways to assure reliability:
Reliability monitoring Every week a sample of Relmons is
subjected to 100 hours of stress testing to continuously monitor the process. ElI9ry quarter a sample is subjected to 1000
hours of stress.
Yield analysis In an ASIC product line there can be a great
variety of part numbers in various stages of product life
cycle. The Relmon is a constant reference that can be used
to understand yield variations.
The reliability of the Power ASIC chip. operating at +90OC.
was determined from the test data gill9n in Figure 7. Since a
large part of the testing was performed at accelerated chip
temperatures of +1250 C and +150oC it was necessary to
transform this information to equivalent times at +90oC. This
was accomplished by using the Arrhenius model of
responsel21. The activation energy used in this model was
0.5425 electron-volts which is based in the Macro test data
in Figure 6. From this information a Weibull model was used
to calculate the expected failure rate at 60.000 operating
hours at a chip temperature of +90oC. This failure rate was
found to be 0.018% per thousand hours at a 50% confidence
lell9l. Also from the Weibull model it was found that beta was
about 0.5 which means that these devices had a decreasing
failure rate with time.
2
~
~
~
,
... ~ 0.01
::!IIIZ~
g; ~
...I
Ii:
8%
i
This was a program to develop state-of-the-art Intelligent
Power ASIC products. The concept of Concurrent Engineering proved to be very beneficial in the execution of this program. The following general observations and conclusions
can be made:
1. A complex power integrated circuit was fabricated in
record time on a semiconductor chip. which Included over
23 types of Macros and assemblies plus a power switching section.
2. Concurrent activities and communication in Test Development Engineering. Advanced Design and Development
Engineering and Advanced Reliability Engineering
assured a timely and successful product development
cycle.
3. Excellent teamwork that required the ultimate in communication. cooperation. commitment and leadership
enabled shipment of production chips in the second year.
4. Over 11.000 test I19hicles. which included TEGs or Components. Macros and ASIC circuits. were stressed under
accelerated conditions as the product was developed.
5. Reliability was designed into the product early and evaluated concurrently which enabled us to exceed the
expected reliability goal by a factor of about three to one.
6. The Relmon was d9119loped to monitor reliability and
update the data base.
Acknowledgment
The author wishes to acknowledge the analytical contributions and encouragement for this report from Peter Shafer.
Ray Dyer. Jack Essom and Paulette Gaillard.
(1) E.A. Herr et al "Techniques for the Control of Integrated
Circuit Quality and Reliability". Technical Report AFMLTR-67-147. June 1967 Air Force Materials Laboratory•
Wright Patterson AFB. Ohio 45433.
•
7
6
"- [""III
5
.......
4
III""
~:
a:
Conclusion
References
8
~8
!ia: ~..
~
The Improvement in reliability of the power ASIC chip. when
the operating chip temperature is lowered in the application.
is shown in Figure 8. For example. this shows that the reliability is improved 2 to 1 when using a chip temperature of
+750 C and 6 to 1 when using +55OC instead of +90oC.
3
.......
(2) E.A. Herr. A. Poe and A. Fox "Reliability Evaluation and
Prediction for Discrete Semiconductors," IEEE Transactions on Reliability. August 1980. Volume R-29 Number
3. Catalogue No. ISSN-OOl8-9529. pp 208-216. 7
~
2
0.001
~
_
~
n
n
_
"
U
CHIP TEMPERATURE ("C)
FIGURE 8. RELIABILITY OF POWER ASIC CHIP AT 60.000
OPERATING HOURS
12-34
INTELLIGEN 13
-
POWERICs
PACKAGING INFORMATION
PAGE
PART NUMBER· PACKAGE OUTLINE DESIGNATOR. . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-2
DUAL·IN·LlNE PLASTIC PACKAGES (PDIP)....................................................
13-5
SMALL OUTLINE PLASTIC PACKAGES (SOIC) . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-8
PLASTIC LEADED CHIP CARRIER PACKAGES (PLCC) ..........................................
13-11
SINGLE·IN·LlNE PLASTIC PACKAGES (SIP) ............................................ ~ . . . .. . .
13-12
CERAMIC DUAL·IN·LlNE METAL SEAL PACKAGES (SBDIP) .....••.......................... .....
13-16
CERAMIC DUAL·IN·LlNE FRIT SEAL PACKAGES (CERDIP).. . . . .. . . .. . . .. .. . . .. . . . . . . . . . . . . . . .. . .
13-18
CERAMIC LEADLESS CHIP CARRIER PACKAGES (CLCC) .......•...............................
13-20
CERAMIC SOIC FLATPACK PACKAGES (SOIC FLATPACK) . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-21
METAL CAN PACKAGES (CAN) .................................................... , .. .. . ... .
13-22
13-1
Part Number - Package Outline Designator
PART NUMBER
PACKAGE DESCRIPTION
PACKAGE OUTLINE
CA723E,CE
14 Lead Dual-In-Une Plastic Package
E14.3
CA723T,CT
10 Lead T0-100 Metal Can Package
T10.C
CA1523E
14 Lead Dual-In-Une Plastic Package
E14.3
E16.3
CA1524E
16 Lead Dual-In-Line Plastic Package
CA1524F
16 Lead Ceramic Dual-In-Line Frit Seal Package
F16.3
CA2524E
16 Lead Dual-In-Line Plastic Package
E16.3
CA2524F
16 Lead Ceramic Dual-In-Llne Frlt Seal Package
F16.3
CA3020,A
12 Lead TO-l0l Metal Can Package
T12.B
CA3059
14 Lead Dual-In-Llne Plastic Package
E14.3
CA3079
14 Lead Dual-In-Llne Plastic Package
E14.3
CA3085,A,B
8 Lead TO-99 Metal Can Package
T8.C
CA3085E, AE, BE
8 Lead Dual-In-Line Plastic Package
E8.3
CA3094T
8 Lead TO-99 Metal Can Package
T8.C
CA3094E
8 Lead Dual-In-Line Plastic Package
E8.3
CA3094M
8 Lead Small OuUlne Plastic Package
M8.15
CA3165E
8 Lead Dual-In-Une Plastic Package
E8.3
CA3165EI
14 Lead Dual-In-Line Plastic Package
E14.3
CA3228E
24 Lead Dual-In-Une Plastic Package
E24.6
CA3242E
16 Lead Dual-In-Une Plastic Package
E16.3
CA3262E,AE
16 Lead Dual-In-Une Plastic Package
E16.3
CA3262AQ
28 Lead Plastic Leaded Chip Carrier Package
N28.45
CA3272AQ, Q
28 Lead Plastic Leaded Chip Carrier Package
N28.45
CA3273
3 Lead Single-In-Une Plastic Package
Z3.1A
CA3274E
8 Lead Dual-in-Line Plastic Package
E8.3
CA3275E
14 Lead Dual-In-Llne Plastic Package
E14.3
CA32nE
16 Lead Dual-In-Llne Plastic Package
E16.3
CA3282AS1
15 Lead Plastic Single-In-Llne Package
(Staggered Vertical Lead Form)
Z15.05A
CA3282AS2
15 Lead Plastic Single-In-Llne Package
(Surface Mount "Gullwing" Lead Form)
Z15.05B
CA3292AQ
28 Lead Plastic Leaded Chip Carrier Package
N28.45
CA3524E
16 Lead Dual-In-Llne Plastic Package
E16.3
CA3524F
16 Lead Ceramic Dual-In-Une Frlt Seal Package
F16.3
CDP68HC68S1 E
14 Lead Dual-In-Une Plastic Package
E14.3
CDP68HC68S1M
20 Lead Small OuUine Plastic Package
M20.3
HIPOOBOAM
28 Lead Plastic Leaded Chip Carrier Package
N28.45
HlPOOB1ASl
15 Lead Plastic Single-In-Une Package
(Staggered Vertical Lead Form)
Z15.05A
HIPOOB1AS2
15 Lead PlastiC Single-in-Line Package
(Surface Mount "Gullwing" Lead Form)
ZI5.05B
13-2
Part Number - Package Outline Designator (Continued)
PART NUMBER
PACKAGE DESCRIPTION
PACKAGE OUTLINE
HIPOO82ASl
15 Lead Plastic Single-In-Une Package
(Staggered Vertical Lead Form)
ZI5.05A
HIPOO82AS2
15 Lead Plastic Single-in-Une Package
(Surface Mount "Gullwing" Lead Form)
ZI5.05B
HIP1030AS
5 Lead Plastic Single-In-Une Package
Z5.067
HIP1031AS
5 Lead Plastic Single-in-Une Package
Z5.067
HIP1090AS
3 Lead Plastic Single-In-Une Package
Z3.1B
HIP20301M
28 Lead Plastic Leaded Chip Carrier Package
N28.45
HIP2500lP
14 Lead Dual-In-Line Plastic Package
HIP2500lPI
16 Lead Dual-In-Une Plastic Package
E16.3
HIP2500lB
16 Lead Small OUtiine Plastic Package
M16.3
HIP40101B
20 Lead Small Outline Plastic Package
M20.3
HIP40111S
15 Lead Plastic Single-In-Line Package
(Surface Mount "Gullwing" Lead Form)
Z15.05B
HIP40801P, AlP
20 Lead Dual-In-Line Plastic Package
E20.3
HIP4080IB, AlB
20 Lead Small Outline Plastic Package
M20.3
E14.3
HIP4081IP, AlP
20 Lead Dual-In-Line Plastic Package
E20.3
HIP4081IB, AlB
20 Lead Small Outline Plastic Package
M20.3
HIP40821P
16 Lead Dual-In-Line Plastic Package
E16.3
HIP4082IB
16 Lead Small Outline Plastic Package
M16.15
HIP5061OS
7 Lead Plastic Single-in-Une Package
Staggered Surface Mount "Gullwing" Lead Form
Z7.05A
HIP5500lP
20 Lead Dual-In-Line Plastic Package
E20.3
HIP5500lB
20 Lead Small Outline Plastic Package
M20.3
HIP5600lS
3 Lead Plastic Single-In-Une Package
Z3.1B
HIP5600lB
8 Lead Small Outline Plastic Package
M8.15
HIP7010AP
14 Lead Dual-In-Line Plastic Package
E14.3
HIP7010AB
14 Lead Small Outline Plastic Package
M14.15
HIP7020AP
8 Lead Dual-In-Line Plastic Package
E8.3
HIP7020AB
8 Lead Small Outline Plastic Package
M8.15
N68.95
HIP7030AOAM
68 Lead Plastic Leaded Chip Carrier Package
HIP7030A2AP
28 Lead Dual-In-Line Plastic Package
E28.6
HIP7030A2AM
28 Lead Small OuUlne Plastic Package
M28.3
HIP7038A8IF
28 Lead Ceramic SOIC Flatpack Package
K28.E
HIP9010AB
20 Lead Small Outline Plastic Package
M20.3
HIP9020AP
14 Lead Dual-In-Line Plastic Package
E14.3
HIP9020AB
20 Lead Small Outiine Plastic Package
M20.3
HV3-2405E-5, -9
8 Lead Dual-In-Line Plastic Package
E8.3
HV400lB
8 Lead Small Outiine Plastic Package
M8.15
HV400lP
8 Lead Dual-In-Line Plastic Package
E8.3
HV400MJl883
8 Lead Ceramic Dual-In-Line Metal Seal Package
D8.3
ICL766OCTV, MTV
8 Lead TO-99 Metal Can Package
T8.C
13-3
Part Number - Package Outline Designator (Continued)
PART NUMBER
PACKAGE DESCRIPTION
PACKAGE OUTUNE
MB.15
ICL7660CBA
B Lead Small Oudine Plastic Package
ICL7660CPA
B Lead Dual-ln-Une Plasdc Package
EB.3
ICL7660SCBA, IBA
B Lead Small Oudine Plastic Package
MB.15
ICL7660SCPA, IPA
B Lead Dual-In-Line Plastic Package
EB.3
ICL7660SCTV, lTV, MTV
B Lead TO-99 Metal Can Package
TB.C
ICL7662CTV, MTV, lTV
B Lead TO-99 Metal Can Package
TB.C
ICL7662CPA, IPA
B Lead Dual-In-Line Plastic Package
ICL7662CBD, CBD-O, IBD
14 Lead Small Oudine Plastic Package
M14.15
ICL7663SCBA, IBA, ACBA, AlBA
B Lead Small OUUine Plastic Package
MB.15
EB.3
ICL7663SCPA,IPA
B Lead Dual-In-Une Plastic Package
EB.3
ICL7663SCJA, UA
B Lead Ceramic Dual-In-Une Frit Seal Package
FB.3A
ICL7663SACPA, AIPA
B Lead Dual-In-Une Plastic Package
ICL7663SACJA, AIJA
B Lead Ceramic Dual-In-Une Frit Seal Package
FB.3A
ICL7665SCBA, IBA, ACBA, AlBA
B Lead Small OUdine Plastic Package
MB.15
ICL7665SCPA, IPA
B Lead Dual-In-Une Plastic Package
EB.3
ICL7665SCJA, IJA
B Lead Ceramic Dual-In-Line Frit Seal Package
FB.3A
ICL7665SACPA, AIPA
B Lead Dual-In-Une Plastic Package
EB.3
ICL7665SACJA, AIJA
B Lead Ceramic Dual-In-Line Frit Seal Package
FB.3A
ICL7667CBA
B Lead Small Outline Plastic Package
MB.15
ICL7667CPA
B Lead Dual-In-Une Plastic Package
ICL7667CJA, MJA
B Lead Ceramic Dual-In-Line Frit Seal Package
FB.3A
ICL7667CTV, MTV
B Lead TO-99 Metal Can Package
TB.C
ICL7673CPA
B Lead Dual-In-Line Plastic Package
EB.3
ICL7673CBA
B Lead Small Oudine Plastic Package
MB.15
EB.3
EB.3
ICL76731TV
B Lead TO-99 Metal Can Package
TB.C
ICL8211CPA
B Lead Dual-In-Une Plastic Package
EB.3
ICL8211CBA
B Lead Small OUtline Plastic Package
MB.15
ICL8211CTY, MTY
B Lead TO-99 Metal Can Package
TB.C
ICLB212CPA
B Lead Dual-In-Une Plastic Package
EB.3
ICLB212CBA
B Lead Small Oudine Plastic Package
MB.15
TB.C
ICLB212CTY, MTY
B Lead TO-99 Metal Can Package
SP600
22 Lead Dual-In-Une Plastic Package
E22.4
SP601
22 Lead Dual-In-Line Plastic Package
E22.4
SP710AS
3 Lead Plastic Single-In-Line Package
Z3.1B
SP720AP
16 Lead Dual-In-Line Plastic Package
E16.3
SP720AB
16 Lead Small Oudlne Plastic Package
M16.15
SP720MD
16 Lead Ceramic Dual-In-Llne Metal Seal Package
016.3
SP720MM
20 Pad Leadless Ceramic Chip Carrier Package
J20.A
SP721AP
B Lead Dual-I n-Line Plastic Package
EB.3
SP721AB
B Lead Small OUtline Plastic Package
MB.15
13-4
Package Outlines
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MSo001·BA ISSUE D)
8 LEAD DUAL·IN·L1NE PLASTIC PACKAGE
~J-bJQT-'~
INCHES
SYMBOL
MIN
MAX
A
MILLIMETERS
MIN
0.210
MAX
NOTES
5.33
4
4
E1
e
0.240
0.280
6.10
7.11
0.100 BSC
2.54BSC
0.300BSC
7.62BSC
0.430
L
0.115
N
0.150
10.92
2.93
8
3.81
5
6
7
4
9
8
Rev. 0 12193
E14.3 (JEDEC MSo001·AA ISSUE D)
E16.3 (JEDEC MS·001-BB ISSUE D)
14 LEAD DUAL·IN·L1NE PLASTIC PACKAGE
16 LEAD DUAL·IN·L1NE PLASTIC PACKAGE
INCHES
SYMBOL
MIN
MAX
A
Al
MIN
0.210
MAX
NOTES
SYMBOL
5.33
4
A
4
Al
0.015
0.39
0.015
INCHES
MILLIMETERS
MAX
MIN
MILLIMETERS
MIN
MAX
5.33
0.210
0.115
0.195
2.93
4.95
A2
0.115
0.195
2.93
4.95
B
0.014
0.022
0.356
0.558
B
0.014
0.022
0.356
0.558
Bl
0.045
0.070
1.15
1.77
C
0.008
0.014
0.204
0.355
o
0.735
0.775
01
0.005
18.66
19.68
0.13
4
4
0.39
A2
Bl
0.045
0.070
1.15
1.77
C
0.008
0.014
0.204
0.355
5
o
0.735
0.775
5
01
0.005
8
NOTES
18.66
19.68
0.13
8,10
5
5
E
0.300
0.325
7.62
8.25
6
E
0.300
0.325
7.62
8.25
6
El
0.240
0.280
6.10
7.11
5
El
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54BSC
0.3OOBSC
7.62BSC
0.430
L
N
0.115
0.150
14
10.92
2.93
3.81
14
e
6
0.100 BSC
2.54BSC
0.300BSC
7.62BSC
0.430
7
4
L
9
N
Rev. 0 12193
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined In the "MO Series Symbol Usr in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
In JEDEC seating plane gauge GS-3.
5. 0, 01, and E1 dimensions do not Include mold flash or protrusions. Mold nash or protrusions shaH not exceed 0.010 Inch
(0.25mm).
0.115
0.150
16
10.92
2.93
3.81
16
6
7
4
9
Rev. 0 12193
6. E and re;:I are measured with the leads constrained to be per·
pendlclifaf'to datum ~.
7. es and Be are measured at the lead tips with the leads uncon·
strained. ec must be zero or greater.
8. B 1 maximum dimensions do not Include dambar protrusiOns.
Darnbar protrusions shall not exceed 0.010 Inch (0.25mm).
9. N Is the maxlmum number of terminal positions.
10. Comer leads (1, N, NI2 and NI2 + 1) for E8.3. E16.3. E18.3.
E28.3. E42.6 wIU have a B 1 dimension of 0.030 • 0.045 Inch
(0.76 • 1.14mm).
13-5
Package Outlines
Dual-In-Line Plastic Packages (PDIP) (Continued)
E20.3 (JEDEC MS.001-AD ISSUE D)
20 LEAD DUAL·IN·LINE PLASTIC PACKAGE
,=-CLJt
INCHES
SYMBOL
~~~~'m
~i~
'~~~
,"
B
e
C
c
.....
f$i0.010(0.25)®ICIAIB~1
MAX
lis
MILLIMETERS
MIN
0.210
A
SEATING\.
~
MIN
MAX
NOTES
5.33
4
4
Al
0.015
0.39
A2.
0.115
0.195
2.93
4.95
0.558
B
0.014
0.022
0.356
Bl
0.045
0.070
1.55
1.77
C
0.008
0.014
0.204
0.355
1.060
24.89
26.9
8
0
0.980
01
0.005
E
0.300
0.325
7.62
8.25
6
El
0.240
0.260
6.10
7.11
5
0.13
5
e
0.100 BSC
2.54BSC
eA
0.300BSC
7.62 BSC
ea
L
0.430
0.115
0.150
10.92
2.93
3.81
20
20
N
5
6
7
4
9
Rev. 0 12/93
E22.4 (JEDEC MS.01G-AA ISSUE C)
E24.6 (JEDEC MS.Oll-AA ISSUE B)
22 LEAD DUAL·IN·LlNE PLASTIC PACKAGE
24 LEAD DUAL·IN·LlNE PLASTIC PACKAGE
INCHES
SYMBOL
MIN
MAX
MILLIMETERS
MIN
0.210
A
Al
0.015
A2.
B
0.125
Bl
C
A2.
0.125
0.195
3.18
4.95
0.558
0.356
0.558
1.15
1.65
0.009
0.Q15
0.229
0.381
1.120
9.91
El
0.330
0.390
8.39
28.44
0.022
0.356
0.030
0.070
0.77
1.77
C
0.008
0.015
0.204
0.381
1.290
8
1.150
10.79
6
E
0.600
0.625
15.24
15.87
6
9.90
5
El
0.485
0.560
12.32
14.73
5
e
0.100 BSC
2.54BSC
6
7
4
eA
0.600BSC
15.24 BSC
ea
L
9
N
12.70
4.06
22
0.014
0.005
2.54BSC
2.93
B
Bl
0
10.16 esc
0.160
4
01
0.400 esc
22
0.39
5
0.100 BSC
0.115
8
0.250
5
0.13
0.500
L
0.015
0.022
0.425
N
Al
0.065
0.390
e
4
0.045
E
4
A
0.014
27.06
NOTES
4
4.95
1.065
MAX
6.35
5.33
3.18
0.005
MILLIMETERS
MIN
SYMBOL
0.195
D
MAX
NOTES
0.39
01
INCHES
MIN
MAX
Rev. 0 12/93
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the Inch dimensions control.
2. Dimensioning and toleranclng per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbollisr In Section
2.2 01 Publication No. 95.
4. Dimensions A, Aland L are measured with the package seated
In JEDEC seating plane gauge GS.3.
5. D, 01, and El dimensions do not Include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 Inch
(0.25mm).
29.3
32.7
0.13
5
0.700
0.115
0.200
24
5
17.78
2.93
5.08
24
6
7
4
9
Rev. 0 12/93
6. E and re,:J are measured with the leads constrained to be per·
pendicUlafto datum ~.
7. eB and ec are measured at the lead tips with the leads uncon·
strained. ec must be zero or greater.
8. B1 maximum dimensions do not Include dambar protrusions.
Dambar protrusions shall not exceed 0.Q1 0 Inch (0.25mm).
9. N Is the maximum number of terminal positions.
10. Comer leads (1, N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 • 0.045 Inch
(0.76-1.14mm).
13-6
Package Outlines
Dual-In-Line Plastic Packages (PDIP) (ContInued)
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.250
0.015
0.39
7. ee and ec are measured at the lead tips with the leads unconstrained. Be must be zero or greater.
8. B1 maximum dimensions do not Include darnbar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25nvn).
9. N is the maximum number of terminal positions.
10. Comer leads (1, N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
13-7
e
0.195
3.18
4.95
0.014
0.022
0.356
0.558
0.030
0.070
0.77
1.77
0.008
0.015
0.204
0.381
1.380
1.565
N
4
39.7
35.1
0.13
0.600
0.625
15.24
15.87
0.485
0.580
12.32
14.73
0.100BSC
2.54BSC
0.600BSC
1524 SSC
0.700
L
NOTES
4
0.125
0.005
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the ·MO Series Symbol Lisr in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold fiash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and Ie;] are measured with the leads constrained to be per·
pendicafaf'to datum @J.
6.35
0.115
0.200
28
17.78
2.93
5.08
28
6
7
4
9
Rev. 0 12/93
Package Outlines
Small Outline Plastic Packages (SOIC)
~~Fr T
N
1
M8.15 (JEDEC MS'()12·AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
!1+I-".i&I'i&1
( J3
VkJ
1~3~ Jtrn
MIN
A
L~I
SEATING PLANE
~D~
INCHES
SYMBOL
1 r-
Al
~~IB11
hX4SO
~L
/-j(
B~~ ~i~I~'004)1
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
·
Al
0.0040
0.0098
0.10
0.25
·
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
·
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
c.1
1M 0.25(0.010) ®I c IA®IBI
MILLIMETERS
MAX
O.050BSC
·
·
1.27 BSC
H
0.2284
0.2440
5.80
6.20
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8°
0"
N
a
8
7
8
0"
·
8°
Rev. 0 12193
M14.15 (JEDEC M9-012·AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
M16.15 (JEDEC M9-012·AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
SYMBOL
A
0.0532
0.0688
1.35
1.75
Al
0.0040
0.0098
0.10
0.25
·
·
A
Al
SYMBOL
MILLIMETERS
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
0.0040
0.0098
0.10
0.25
·
·
9
MIN
B
0.013
0.020
0.33
0.51
9
B
0.013
0.020
0.33
0.51
C
0.0075
0.0098
0.19
0.25
·
C
0.0075
0.0098
0..19
0.25
·
D
0.3367
0.3444
8.55
8.75
3
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
E
0.1497
0.1574
3.80
4.00
4
e
·
H
0.2284
0.2440
5.80
6.20
·
·
H
0.2284
0.2440
5.80
6.20
·
h
0.0099
0.0196
0.25
0.50
5
h
0.0099
0.0196
0.25
0.50
5
L
0.D16
0.050
0.40
0.016
0.050
0.40
e
O.050BSC
N
a
1.27 BSC
14
0°
1.27
14
8°
0"
8°
6
L
7
N
·
a
O.050BSC
1.27 BSC
16
0°
1.27
6
16
S"
0"
7
·
8°
Rev. 0 12193
Rev. 0 12193
NOTES:
1. Symbols are defined in the "MO Series Symbol Lisr in Section
2.2 of Publication Number 95.
6. "L" Is the length of terminal for soldering to a substrate.
7. "N" Is the number of terminal pOSitions.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
8. Terminal numbers are shown for reference only.
3. Dimension "0- does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 Inch) per side.
9. The lead width -S", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
4. Dimension "E" does not Include Interlead flash or protrusions. 10terlead nash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
10. Controlling dimension: MILLIMETER. Converted Inch dimeoslons are not necessarily exact.
5. The chamfer on the body Is optional. If it Is not present, a visual
index feature must be located within the crosshatched area.
13·8
Package Outlines
Small Outline Plastic Packages (SOIC) (Continued)
M16.3 (JEDEC Ms'()13-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
MILLIMETERS
INCHES
SYMBOL
f-IB-o--1
~{W~lli
B~ ~
1$'l0.25(0.010)®IC
IA®IB®I
NOTES
MAX
A
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
9
MIN
B
0.013
0.0200
0.33
0.51
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
02914
02992
7.40
7.60
4
e
1010.10(0.004) I
MAX
MIN
10.00
10.65
-
0.029
0.25
0.75
5
0.050
0.40
127
O.050BSC
H
0.394
h
0.010
L
0.Q16
N
0.419
1.27BSC
S"
0°
IX
6
16
16
CI'
7
-
8°
Rev. 0 12193
M20.3 (JEDEC Ms'()13-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
MILLIMETERS
INCHES
SYMBOL
M24.3 (JEDEC MS'()13-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
MIN
MAX
A
0.0926
A1
0.0040
INCHES
MIN
MAX
NOTES
0.1043
2.35
2.65
-
0.0118
0.10
0.30
-
SYMBOL
MILLIMETERS
MIN
MAX
0.1043
2.35
2.65
0.0118
0.10
0.30
9
MIN
MAX
A
0.0926
A1
0.0040
NOTES
-
B
0.013
0.0200
0.33
0.51
9
0.013
0.020
0.33
0.51
0.0091
0.0125
0.23
0.32
-
B
C
C
0.0091
0.0125
0.23
0.32
D
0.4961
0.5118
12.60
13.00
3
-
0
0.5985
0.6141
15.20
15.60
3
E
0.2914
02992
7.40
7.60
4
E
0.2914
0.2992
7.40
7.60
4
e
O.050BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
5
e
0.05BSC
1.27 BSC
H
0.394
0.419
10.00
10.65
h
0.010
0.029
0.25
0.75
5
h
0.010
0.029
0.25
0.75
L
0.016
0.050
0.40
1.27
6
L
0.016
0.050
0.40
127
7
N
20
N
IX
0°
20
8°
CI'
-
8°
IX
24
0°
6
24
8°
CI'
7
-
8°
Rev. 0 12193
Rev. 0 12193
NOTES:
1. Symbols are defined in the "MO Series Symbol Lisr in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing
6. "L"
Is the length of terminal for soldering to a substrate.
7. "N" Is the number of terminal positions.
per ANSI Y14.5M-1982.
8. Terminal numbers are shown for reference only.
3. Dimension "0" does not Include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include Interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted Inch dimensions are not necessarily exact.
5. The chamfer on the body Is optional. If it Is not present, a visual
index feature must be located within the crosshatched area.
13-9
Package Outlines
Small Outline Plastic Packages (SOIC) (Continued)
M2803 (JEDEC MS-OI3-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTUNE PLASTIC PACKAGE
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
AI
0.0040
0.0118
0.10
0.30
9
B
0.013
0.0200
0.33
0.51
C
0.0091
0.0125
0.23
0.32
-
0
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
0.419
10.00
10.65
-
0.01
0.029
0.25
0.75
5
0.016
0.050
0.40
1.27
0.05BSC
H
0.394
h
L
N
NOTES:
1. Symbols are defined in the "MO Series Symbol Lisr In Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D° does not Include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "EO does not Include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
Inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L"1s the length of terminal for soldering to a substrate.
7. "No Is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "8", as measured 0.36mm (0.014 Inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILliMETER. Converted inch dimensions are not necessarily exact.
13-10
IX
1.27BSC
28
0"
28
8°
0"
6
7
B"
Rev. 0 12193
Package Outlines
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
h
0.042 (1.07)
b:
Ie
O~)
IN (1) IDENnFlER 0.050 (1.27) TP
k- \
I
TIl'"
"l..!.,.,,.,,.,
'1;:!-~ ~O
___
+
N28.45 (JEDEC M5-018 ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.025 (0.64) R
k- 0.045 (1.14)
1.0::::: /
ITl~tL
~~
INCHES
SYMBOL
MIN
MAX
01
0.450
0.456
~::;:
El E _ _
~
~~?
~
~
~
ll C I
0.004 (o. lO
D21E2
,:
MIN
MAX
,~~
11.43
3
11.58
4,5
0.191
0.485
0219
0.495
4.86
12.32
5.56
12.57
VIEW "A"
El
0.450
0.456
11.43
11.58
3
0.191
0219
4.86
5.56
4,5
MIN
E2
N
'-' ':, l'
bl~_0'020(0'51)
-l~ _
28
6
28
A,.
o
NOTES
02
E
H-
--====1_
Dl-j
MILLIMETERS
Rev. 0 12/93
r::c:l SEAnNG
0.020 (0.51) MAX
...:...J PLANE
3PLCS
0.026 (0.66)
0.032 (0.81)
N68.95 (JEDEC M5-018 ISSUE A)
68 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.013 (0.33)
~c:!
INCHES
--± 0.021 (0.53)
0.045 (1.14)
MIN
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
·
AI
0.090
0.120
2.29
3.04
·
0
0.985
0.995
25.02
25.27
·
0.025 (0.64)
~
VIEW "A" TYP.
NOTES:
01
0.950
0.958
24.13
24.33
3
02
0.441
0.469
1121
11.91
4,5
2. Dimensions and toleranclng per ANSI YI4.5M·1982.
E
0.985
0.995
25.02
25.27
·
3. Dimensions 01 and El do not Include mold protrusions. Allowable mold protrusion Is 0.010 Inch (0.25mm) per side.
El
0.950
0.958
24.13
24.33
3
E2
0.441
0.469
1121
11.91
4,5
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
4. To be measured at seating plane ~ contact point.
5. Centerline to be determined where center leads exit plastic body.
6. ON" is the number of terminal pOsitions.
13·11
N
68
68
6
Rev. 0 12/93
Package Outlines
Single-In-Line Plastic Packages (SIP)
ACTIVE ELEMENT
Z3.1 A (JEDEC STYLE TO-202 MODIFIED)
3 LEAD SHORT TAB SINGLE-IN-L1NE PLASTIC PACKAGE
INCHES
iJi
MILLIMETERS
MIN
MAX
NOTES
SYMBOL
MIN
MAX
A
0.130
0.150
3.31
3.81
b
0.024
0.028
0.61
0.71
2,3
bl
0.045
0.055
1.15
1.39
1,2,3
·~l.
0.270
0.280
6.86
7.11
c
0.Q18
0.022
0.46
0.55
D
E
0.320
0.340
8.13
8.63
0.340
0.360
8.64
9.14
1,2,3
e
O.IOOTYP
2.54TYP
4
al
0.200 SSC
5.08BSC
4
2.54
HI
0.080
0.100
Jl
0.035
0.045
0.89
1.14
L
0.410
0.440
10.42
11.17
Ll
2.04
0.110
5
2.79
Rev. 02194
NOTES:
1. Lead dimension and finish uncontrolled in zone L1.
2. Lead dimension (without solder).
3. Add typically 0.002 Inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.250 Inches (6.35mm) from bottom
of dimension D.
5. Position of lead to be measured 0.1 00 Inches (2.54mm) from bottom
of dimension D.
6. ContrOlling dimension: INCH.
Z3.1 B (JEDEC T0-220AB ISSUE J)
3 LEAD PLASTIC SINGLE-IN-L1NE PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.140
0.190
3.56
4.62
1.02
cl_ ...
NOTES:
NOTES
b
0.015
0.040
0.38
bl
0.045
0.070
1.14
1.77
cl
0.014
0.022
0.36
0.56
o
0.560
0.650
14.23
16.51
E
0.380
0.420
9.66
10.66
e
0.090
0.110
2.29
2.79
2
el
0.190
0.210
4.83
5.33
2
F
0.020
0.055
0.51
1.39
HI
0.230
0.270
5.85
6.85
Jl
0.080
0.115
2.04
2.92
L
0.500
0.580
12.70
14.73
3
1. Lead dimension and finish uncontrolled In zone L1.
L1
6.35
1
2. Position of lead to be measured 0.250 Inches (6.35mm) from bottom of dimension D.
0P
0.139
0.161
3.53
4.08
..
Q
0.100
0.135
2.54
3.43
3. Position of lead to be measured 0.1 00 Inches (2.54mm) from bottom of dimension D.
4. Controlling dimension: INCH.
13-12
0.250
..
Rev. 02194
Package Outlines
Single-In-Line Plastic Packages (SIP) (Continued)
IE
L
L
L
234
5
INCHES
t
ti
MIN
MAX
MIN
A
0.165
0.190
4.19
4.82
AI
0.035
0.055
0.89
1.39
-
A2
0.085
0.115
2.16
2.92
3
b
0.020
0.040
0.51
1.01
1
C
0.012
0.025
0.31
0.63
1
0
0.570
0.625
14.48
15.87
-
01
0.330
0.370
8.39
9.39
01
L
e
~
liT
I I
e~t
o~
A2
b5PL_
MILLIMETERS
SYMBOL
A1
0
1
a_
.~
IIIP
[::tJ
0- ~
1
Z5.067 (JEDEC T5-001 AA ISSUE A)
5 LEAD PLASTIC SINGLE·IN-UNE PACKAGE
_
MAX
NOTES
-
1.70BSC
O.067BSC
E
0.390
0.415
9.91
10.54
L
0.945
1.045
24.00
26.54
Ll
0.465
0.539
11.81
13.69
0P
0.139
0.156
3.53
3.96
M
0.130
0.150
3.31
3.81
1-$-j0.014@>ITlvcgl
2
-
-
1
Rev. 02194
NOTES:
1. Lead dimension and finish uncontrolled in zone M.
2. Position of lead to be measured 0.250 Inches (6.35mm) from
bottom of dimension D.
3. Position of lead to be measured 0.100 inches (2.54mm) from
bottom of dimension D.
4. Dimensioning and toleranclng per ANSI YI4.5M, 1982.
5. Controlling dimension: INCH.
r16
l
D-
1.E2
-
r\
'\.. IIIP
STAGGEREDSURFACEMOUNTuGULL~NG"LEADFORM
INCHES
TB
.1
E
f
{t r
¥
I
'1:1
I [::!J
HEAOE~
- - BOTTOM
7 LEAD PLASTIC SINGLE-IN-UNE PACKAGE
;.t
lJ
r-
I---El,
11
!ill
Z7.05A
+
C
~~
/'
00_80
li.iO
°1"*1
~
L2.
.-
L
MIN
MAX
A
0.160
0.190
4.06
4.83
MAX
0.94
B
0.023
0.037
0.58
0.015
0.023
0.38
0.58
0
0.385
0.415
9.78
10.54
E
0.560
0.590
14.22
14.99
El
0.326
0.335
8.28
8.50
E2
0.103
0.113
2.62
2.87
e
0.045
0.055
1.14
1.40
e3
0.295
0.305
7.49
7.75
F
0.045
0.055
1.14
1.40
L
0.065
0.080
1.66
2.03
Ll
0.100
0.110
2.54
2.79
L2
0.200
0.210
5.08
5.33
0.156
3.68
0P
1. Dimensioning and tolerancing per ANSI YI4.5M, 1982.
MIN
C
N
NOTES:
MILLIMETERS
SYMBOL
7
0.145
7
3.98
Rev. 0 2194
2. N Is the number of leads.
3. Controlling dimension: INCH.
13-13
Package Outlines
Single-In-Line Plastic Packages (SIP) (Continued)
---D--~"I
t..
I
.irl
~
1
0.015
MECH.
INDEX
1 I)
--
r-
A
Z9.1
II LEAD SINGLE·IN·UNE PLASTIC PACKAGE
r-
INCHES
E1
1
81
-,r-
MIN
MAX
A
.
0.140
AI
0.090
0.120
0.035
8
0.045
8 LEADS
TYP
NOTE 2
2 LEADS
MILUMETERS
SYMBOL
'U~ -:rL
~
I~ ~ ~ _11_ U
I
0.060
T
~
NOTES
3.56
·
2.29
3.05
B
0.014
0.020
0.36
0.51
Bl
0.050
0.065
1.27
1.65
3
C
0.008
0.014
0.20
0.35
·
0
0.845
0.885
21.47
22.48
2
El
0.240
0.260
6.10
6.61
2
0.100 BSC
L
1. Lead within 0.01 0 inch radius of true position (TP) wfth maximum
material condition.
2. 0 and El dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010'inch (O.25mm).
MAX
.
·
·
e
NOTES:
MIN
0.125
N
·
2.54BSC
0.150
3.18
9
·
3.81
4
9
Rev. 02194
3. B 1 maximum dimensions do not Include dambar protruslO!lS.
Oambar protrusions shall not exceed 0.010 inch (0.25mm).
4. N is the maximum number of terminal positions.
5. ContrOlling dimension: INCH.
e~I~____~~
__ r-- B
I
f$i 0.010(0.25)@ z I X@
Y@
'
L
'1":'1:"
~
e2
cI$I0.024(0.61)®I Z I
TYP ALL LEADS
L
\flJP
E2
0.110BSC
2.79BSC
el
0.200 ~C
5.08 BSC
e2
0.169 ~C
4.29 ~C
~~~ ~__~e__~__~0~.0~50~~~C~~~__~I.~~B~S~C__~
e3
0.700~C
17.78~C
~--~--+-~=-~~=-~~=-~~~~
1.45
1.60
F
0.057
0.063
1$1 flJ 0.015(0.38) ® Iz Ix®1
--B-- ~
L
0.150
0.176
3.81
4.47
L,
0.690
0.710
17.53
18.03
N
15
15
0P
0.148
0.152
3.76
Rl
0.065
0.080
1.65
3.86
2.03
Rev. 0 2194
NOTES:
1. Refer to series symbol list, JEOEC Publication No. 95.
2. Dimensioning and Toleranclng per ANSI YI4.5M·1982.
3. N Is the number of terminals.
4. ContrOlling dimension: INCH.
13·14
Package Outlines
Single-In-Line Plastic Packages (SIP) (Continued)
Z15.05B
15 LEAD PLASTIC SINGLE·IN-LINE PACKAGE
SURFACE MOUNT 'GULLWlNG' LEAD FORM
INCHES
R1
MILUMETERS
SYMBOL
MIN
MAX
MIN
A
0.172
0.182
4.37
MAX
4.62
B
0.024
0.031
0.61
0.79
C
0.018
0.024
0.46
0.61
D
0.n8
0.798
19.76
2027
E
0.684
0.694
17.37
17.63
El
0.416
0.426
10.57
10.82
E2
0.110 BSC
a
0.050BSC
1.27BSC
a3
0.700BSC
17.78 BSC
2.79BSC
F
0.057
0.063
L
0.065
0.080
1.66
2.03
Ll
0.098
0.108
2.49
2.74
N
1.45
1.60
15
15
0P
0.148
0.152
3.76
3.86
Rl
0.065
O.OBO
1.65
2.03
Rev. 02194
HEADER
BOTTOM
NOTES:
1. Dimensioning and Tolerancing per ANSI Y14.5M· 1982.
2. N is the number of terminals.
3. All lead surfaces are within 0.004 inch of each other. No lead can
ba more than 0.004 inch above or balow the header plane,
(I:±] Datum).
4. Controlling dimension: INCH.
13·15
Package Outlines
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
.~
I
~
1i
~ ~~~Iii~~
.a-
:f.
t fi :t::.. ~ (e)
tTtb1~
@lbbb@lc IA.B@ID@I
'~~~
..
.dl-
~~~
"
~aaa
MIWMETERS
INCHES
MIN
MAX
MIN
MAX
A
·
0.200
·
5.08
·
(b)
b
0.014
0.026
0.36
0.66
2
SEcnONA-A
bl
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
·
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
cl
0.008
0.015
0.20
0.38
3
D
·
0.405
·
10.29
·
E
0.220
0.310
5.59
7.87
·
·
·
·
·
~
B@ID@I
08.3 MIL-sTl).l835 CDIP2-T8 (0-4, CONFIGURATION C)
a LEAD CERAMIC DUAL·IN-UNE METAL SEAL PACKAGE
SYMeOL
.1
[!J
~eecWICIA.
1
LEjFlNISH
ei
~
rt-
I
~'
eA
e __
r--
WICIA· B@ID@
e
0.100 BSC
2.54BSC
eA
0.300BSC
7.62 BSC
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat·
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identifICation shall not be used
as a pin one Identificallon mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish Is applied.
0.150 BSC
3.81 BSC
L
0.125
0.200
3.18
5.08
a
0.015
0.060
0.38
0.005
0.13
S2
0.005
.
.
1.52
SI
a
90"
105°
90°
105°
aaa
·
·
·
·
0.015
·
0.38
3. Dimensions bl and cl apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
4. Comer leads (I, N, N/2, and Nl2+ 1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
M
ccc
N
0.030
0.010
0.0015
8
.
.
0.13
·
6
5
6
7
0.25
·
·
·
·
0.038
2
0.76
·
·
NOTES
8
Rev. 04/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension SI at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N Is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and toleranclng per ANSI Y14.5M ·1982.
11. Controlling dimension: INCH.
13·16
Package Outlines
Ceramic Dual-In-Line Metal Seal Packages (SBDIP) (ContInued)
$f
@jbbb(!)lc IA-B
016.3 MIL-S'TD-1835 CDIP2·T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-UNE METAL SEAL PACKAGE
INCHES
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
3
(b)
ot
[!]
K&jaaa
ri~I
e_
~I C IA - B <
en~
-0::
O::w
0:::=
<
-0:
O:w
0:;:
c(t/)
z
c(
April 23. 1994
AnswerFAX
DOCUMENT
NUMBER
PART
NUMBER
99404
AN9404
99405
AnswerFAX Technical Support
Application Note Listing
AnswerFAX
DOCUMENT
NUMBER
PART
NUMBER
HIP40BOA. BOV High Frequency
H-Bridge Driver (12 pages)
662842
MM2B42
HA-2B42 Spice Operational Amplifier
Macro-Model (4 pages)
AN9405
HIP40B1A. BOV High Frequency
H-Bridge Driver (11 pages)
662850
MM2850
HA-2850 Spice Operational Amplifier
Macro-Model (4 pages)
660001
MMOO01
HFA-D001 Spice Operational Amplifier
Macro-Model (4 pages)
663046
MM3046
HFA304613096/3127/312B Transistor
Array Spice Models (4 pages)
660002
MMOO02
HFA-D002 Spice Operational Amplifier
Macro-Model (4 pages)
665002
MM5002
HA-5002 Spice Buffer Amplifier
Macro-Model (4 pages)
660005
MMOO05
HFA-D005 Spice Operational Amplifier
Marco-Model (4 pages)
665004
MM5004
HA-5004 Spice Current Feedback
Amplifier Macro-Model (4 pages)
662500
MM2500
HA2500/02 Spice Operational Amplifier
Macro-Model (5 pages)
665020
MM5020
662510
MM2510
HA-251 0/12 Spice Operational
Amplifier Macro-Model (4 pages)
HA-5020 Spice Current Feedback
Operational Amplifier Macro-Model
(4 pages)
665033
MM5033
662520
MM2520
HA-2520/22 Spice Operational
Amplifier Macro-Model (4 pages)
HA-5033 Spice Buffer Amplifier
Macro-Model (4 pages)
665101
MM5101
662539
MM2539
HA-2539 Spice Operational Amplifier
Macro-Model (4 pages)
HA-5101 Spice Operational Amplifier
Macro-Model (5 pages)
665102
MM5102
662540
MM2540
HA-2540 Spice Operational Amplifier
Macro-Model (4 pages)
HA-5102 Spice Operational Amplifier
Macro-Model (5 pages)
665104
MM5104
662541
MM2541
HA-2541 Spice Operational Amplifier
Macro-Model (5 pages)
HA-5104 Spice Operational Amplifier
Macro-Model (5 pages)
665112
MM5112
662542
MM2542
HA-2542 Spice Operational 'Amplifier
Macro-Model (5 pages)
HA-5112 Spice Operational Amplifier
Macro-Model (5 pages)
665114
MM5114
662544
MM2544
HA-2544 Spice Operational Amplifier
Macro-Model (5 pages)
HA-5114 Spice Operational Amplifier
Macro-Model (5 pages)
665127
MM5127
HA-5127 Spice Operational Amplifier
Macro-Model (4 pages)
DESCRIPTION
DESCRIPTION
662548
MM2548
HA-2548 Spice Operational Amplifier
Macro-Model (5 pages)
665137
MM5137
662600
MM2600
HA-2600/02 Spice Operational
Amplifier Macro-Model (5 pages)
HA-5137 Spice Operational Amplifier
Macro-Model (4 pages)
665147
MM5147
662620
MM2620
HA-2620/22 Spice Operational
Amplifier Macro-Model (5 pages)
HA-5147 Spice Operational Amplifier
Macro-Model (4 pages)
665190
MM5190
662839
MM2839
HA-2B39 Spice Operational Amplifier
Macro-Model (4 pages)
HA-5190 Spice Operational Amplifier
Macro-Model (4 pages)
665221
MM5221
662840
MM2840
HA-2B40 Spice Operational Amplifier
Macro-Model (4 pages)
HA-5221/22 Spice Operational
Amplifier Macro-Model (4 pages)
797338
662841
MM2841
HA-2841 Spice Operational Amplifier
Macro-Model (4 pages)
MM
PWRDEV
Harris Power MOSFET and MCT Spice
Model Library (16 pages)
14-8
INTELLIGEN 15
POWERICs
SALES OFFICES
HARRIS HEADQUARTER LOCATIONS BY COUNTRY:
U.S. HEADQUARTERS
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TEL: (407) 724-3000
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Mercure Centre
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(J)
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Singapore. . . . . . . • . . . . . . . . . . . 65-291-0203
o
UNITED KINGDOM
Camberley .........•....•... 44-2-766-86886
o
w
u::
u...
(J)
W
...I
~
15-1
North American Sales Offices and Representatives
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Vision Technical Sales, Inc.
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FAX: 818 5911403
CANADA
Blakewood Electronic
Systems, Inc.
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Canada V5A 2G9
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FAX: 604 4443303
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TEL: (317) 844-5222
FAX: 317 844 5861
78 Donegani, Suite 200
Pointe Claire, Quebec
Canada H9R 2V4
TEL: (514) 426-0453
FAX: 514 426 0455
May 1994
MICHIGAN
Harris Semiconductor
• Suite 460
27777 Franklin Rd.
Southfield, MI 48034
TEL: (810) 746-0800
FAX: 810 746 0516
Giestlng & Associates
Suite 113
34441 Eight Mile Rd.
Livonia, MI 48152
TEL: (810) 478-8106
FAX: 810 477 6908
1279 Skyhills N.E.
Comstock Park, MI 49321
TEL: (616) 784-9437
FAX: 616 784 9438
COLORADO
Compass Mktg. & Sales, Inc.
Suite 3500
5600 So. Quebec SI.
Greenwood Village, CO 80111
TEL: (303) 721-9663
FAX: 303 721 0195
IOWA
Oasis Sales
Suite 203
4905 Lakeside Dr., N E
Cedar Rapids, IA 52402
TEL: (319) 377-8738
FAX: 319 377 8803
MINNESOTA
Oasis Sales
SUite 210
7805 Telegraph Road
Bloomington, MN 55438
TEL: (612) 941-1917
FAX: 612 9415701
CONNECTICUT
Advanced Tech. Sales, Inc.
Westview Office Park
Bldg. 2, Suite lC
850 N. Main Street Extension
Wallingford, CT 06492
TEL: (508) 864-0888
FAX: 203 284 8232
KANSAS
Advanced Tech. Sales, Inc.
Suite 8
601 North Mur·Len
Olathe, KS 66062
TEL: (913) 782-8702
FAX: 913 782 8641
MISSOURI
Advanced Tech. Sales
13755 SI. Charles Rock Rd.
Bridgeton, MO 63044
TEL: (314) 291-5003
FAX: 314 291 7958
FLORIDA
Harris Semiconductor
• 1301 Woody Burke Rd.
Melbourne, FL 32901
TEL: (407) 724-3576
FAX 407 724 3130
Sun Marketing Group
SUite AS
1956 Dairy Rd.
West Melbourne, FL 32904
TEL: (407) 723-0501
FAX 407 723 3845
GEORGIA
Giestlng & Associates
• Suite 108
2434 Hwy. 120
Duluth, GA 30136
TEL: (404) 476-0025
FAX: 404 476 2405
KENTUCKY
Glesting & Associates
212 Grayhawk Court
Versailles, KY 40383
TEL: (606) 873-2330
FAX: 606 873 6233
MARYLAND
New Era Sales, Inc.
Suite 103
890 Airport Pk. Rd
Glen Burnie, MD 21061
TEl: (410) 761-4100
FAX: 410761-2981
MASSACHUSETTS
Harris Semiconductor
• Suite 240
3 Burlington Woods
Burlington, MA 01803
TEL: (617) 221-1850
FAX: 617 221 1866
Advanced Tech Sales, Inc.
Suite 102
348 Park Street
Park Place West
N. Reading, MA 01864
TEL: (508) 864-0888
FAX: 508 864 5503
ILLINOIS
Harris Semiconductor
• Suite 600
1101 Perimeter Dr.
Schaumburg, It 60173
TEL: (708) 240-3480
FAX: 708 6191511
• Field Application Assistance
Available
15-2
NEBRASKA
Advanced Tech. Sales
13755 SI. Charles Rock Rd.
Bridgeton, MO 63044
TEL: (314) 291-5003
FAX: 314 291 7958
NEW JERSEY
Harris Semiconductor
• Plaza 1000 at Main Street
SUite 104
Voorhees, NJ 08043
TEL: (609) 751-3425
FAX: 609 751 5911
Harris Semiconductor
724 Route 202
P.O. Box 591 MIS 13
Somerville, NJ 08876
TEL: (908) 685-6150
FAX: 908685-6140
Tritek Sales, Inc.
Suite 410, One Cherry Hill
Cherry Hili, NJ 08002
TEL: (609) 867-0200
FAX: 609 667 8741
NEW MEXICO
Compass Mktg. & Sales, Inc.
Suite 109
4100 Osuna Rd., NE
Albuquerque, NM 87109
TEL: (505) 344-9990
FAX: 505 345 4848
May 1994
North American Sales Offices and Representatives (Continued)
NEW YORK
Harris Semiconductor
Hampton Business Center
1611 RI. 9, Suite U3
Wappingers Falls, NY 12590
TEL: (914) 298-0413
FAX: 914 298 0425
Foster & Wager, Inc.
300 Main Street
Vestal, NY 13850
TEL: (607) 748-5963
FAX: 607 7485965
2511 Browncroft Blvd.
Rochester, NY 14625
TEL: (716) 385·n44
FAX: 716 5861359
7696 Mountain Ash
Liverpool, NY 13090
TEL: (315) 457-7954
FAX: 315 4577076
Trionlc Associates, Inc.
• 320 Northern Blvd.
Great Neck, NY 11021
TEL: (516) 466-2300
FAX: 516 466 2319
NORTH CAROLINA
Harris Semiconductor
4020 Stirrup Creek Dr.
Building 2A, MS/2T08
Durham, NC 2n03
TEL: (919) 549·3600
FAX: 919 549 3660
New Era Sales
Suite 203
1110 Navajo Dr.
Raleigh, NC 27609
TEL: (919) 878-0400
FAX: 919 878 8514
OHIO
Glestlng & Associates
P.O. Box 39398
2854 Blue Rock Rd.
Cincinnati, OH 45239
TEL: (513) 385-1105
FAX: 513 385 5069
Suite 521
26250 Euclid Avenue
Cleveland, OH 44132
TEL: (216) 261-9705
FAX: 216261 5624
6324 Tamworth CI.
Columbus, OH 43017
TEL: (614) 752-5900
FAX: 614 792-6601
OKLAHOMA
Nova Marketing
Suite 1339
8125D East 51st Street
Tulsa, OK 74145
TEL: (800) 626-8557
TEL: (918) 660-5105
FAX: 918 6653815
• Field Application Assistance
Available
Nova Marketing
Suite 180
8310 Capitol of Texas Hwy.
Austin, TX 78731
TEL: (512) 343-2321
FAX: 512 343·2487
OREGON
Northwest Marketing Assoc,
Suite 330
6975 SW Sandburg Road
Portland, OR 97223
TEL: (503) 620-0441
FAX: 503 684 2541
Suite 174
8350 Meadow Rd.
Dallas, TX 75231
TEL: (214) 265-4600
FAX: 214 265 4668
PENNSYLVANIA
Glestlng & Associates
471 Walnut Street
Pittsburgh, PA 15238
TEL: (412) 828-3553
FAX: 412 828 6160
Corporate Atrium II
Suite 140
10701 Corporate Dr.
Stafford, TX n4n
TEL: (713) 240-6082
FAX: 713 240 6094
TEXAS
Harris Semiconductor
• Sulte205
17000 Dallas Parkway
Dallas, TX 75248
TEL: (214) 733-0800
FAX: 214 733 0819
UTAH
Compass Mktg. & Sales, Inc.
Suite 320
5 Triad Center
Salt Lake City, UT 84180
TEL: (801) 322-0391
FAX: 801 322-0392
WASHINGTON
Northwest Marketi ng Assoc.
Suite330N
12835 Bel-Red Road
Bellevue, WA 98005
TEL: (206) 455-5846
FAX: 206 4511130
WISCONSIN
Oasis Sales
1305 N. Barker Rd.
Brookfield, WI 53005
TEL: (414) 782-6660
FAX: 414 782 7921
North American Authorized Distributors and Corporate Offices
Alliance Electronics
20 Custom House SI.
Boston, MA 02110
TEL: (617) 261-7988
FAX: (617) 261-7987
Newark Electronics
4801 N. Ravenswood
Chicago, IL 60640
TEL: (312) 784-5100
FAX: 312 275-9596
ArrowlSchweber
Electronics Group
25 Hub Dr.
Melville, NY 11747
TEL: (516) 391-1300
FAX: 5163911644
Wyle laboratories
(Commercial Products)
3000 Bowers Avenue
Santa Clara, CA 95051
TEL: (408) 727·2500
FAX: 408 988-2747
Electronics Marketing
Corporation (EMC)
1150 West Third Avenue
Columbus, OH 43212
TEL: (614) 299-4161
FAX: 614 299 4121
Rochester Electronic
10 Malcom Hoyt Drive
Newburyport, MA 01950
TEL: (508) 462-9332
FAX: 508 462 9512
North American Authorized Distributors
ALABAMA
ArrowlSchweber
Huntsville
TEL: (205) 837·6955
Hamilton Hallmark
Huntsville
TEL: (205) 837-8700
Zeus Electronics,
An Arrow Company
100 Midland Avenue
PI. Chester, NY 10573
TEL: (914) 937-7400
TEL: (800) 52-HI·REl
FAX: 914 937-2553
Hamilton Hallmark
10950 W. Washinglon Blvd.
Culver City, CA 90230
TEL: (310) 558-2000
FAX: 3105582809 (Mil)
FAX: 3105582076 (Com)
Obsolete Products:
Hamilton Hallmark and Zeus are the only authorized North American
distributors for stockJng and sale of Harris Rad Hard Space products.
FarneU Electronic Services
(Formerly ITT Multicornponents)
300 North Rivermede Rd.
Concord, Ontario
Canada L4K 3N6
TEL: (416) 798-4884
FAX: 416 798 4889
Gerber Electronics
128 Carnegie Row
Norwood, MA 02062
TEL: (617) 769-6000, x156
FAX: 617 762 8931
Alliance Electronics
20 Custom House SI.
Boston, MA 02110
TEL: (617) 261-7988
FAX: (617) 261-7987
Wyle laboratories
Huntsville
TEL: 205) 83D-1119
Zeus, An Arrow Company
Huntsville
TEL: (205) 837-6955
ARIZONA
Alliance Electronics, Inc.
Gilbert
TEL: (602) 813-0233
Scottsdale
TEL: (602) 483-9400
ArrowlSchweber
Tempa
TEL: (602) 431-0030
Hamilton Hallmark
Phoenix
TEL: (602) 437-1200
Wyle laboratories
Phoenix
TEL: (602) 437·2088
Zeus, An Arrow Company
Tempe
TEL: (602) 431-0030
CALIFORNIA
Alliance Electronics, Inc.
Santa Clarita
TEL: (805) 297-6204
ArrowlSchweber
Calabasas
TEL: (818) 880-9686
Irvine
TEL: (714) 587-0404
San Diego
TEL: (619) 565-4800
San Jose
TEL: (408) 441-9700
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15-3
North American Authorized Distributors (Continued)
Hamilton Hallmark
Costa Mesa
TEL: (714) 641-4100
Los Angeles
TEL: (818) 594-0404
COLORADO
Arrow/schweber
Englewood
TEL: (303) 799-0258
ILLINOIS
Alliance Electronics, Inc.
Vernon Hills
TEL: (708) 949-9890
Sacramento
TEL: (916) 624-9781
Hamilton Hallmark
Denver
TEL: (303) 790-1662
Arrow/Schweber
Itasca
TEL: (708) 250-0500
San Diego
TEL: (619) 571-7540
Colorado Springs
TEL: (719) 637-0055
San Jose
TEL: (408) 435-3500
Wyle Laboratories
Thornton
TEL: (303) 457-9953
Hamilton Hallmark
Chicago
TEL: (708) 860-n80
Wyle laboratories
Calabasas
TEL: (818) 880-9000
Irvine
TEL: (714) 863-9953
Rancho Cordova
TEL: (916) 638-5282
San Diego
TEL: (619) 565-9171
CONNECTICUT
Alliance Electronics, Inc.
Shelton
TEL: (203) 926-0087
Hamilton Hallmark
Danbury
TEL: (203) 271-2844
Zeus, An Arrow Company
Calabasas
TEL: (818) 880-9686
Zeus, An Arrow Company
Wallingford
TEL: (203) 265-n41
Yorba Linda
TElL: (714) 921-9000
TEL: (800) 52-HI-REL
CANADA
Arrow/Schweber
Burnaby, British Columbia
TEL: (604) 421-2333
Wyle Laboratories
Schaumburg
TEL: (708) 303-1040
Zeus, An Arrow Company
Itasca
TEL: 708) 250-0500
Arrow/schweber
Wallingford
TEL: (203) 265-n41
Santa Clara
TEL: (408) 727-2500
San Jose
TEL: (408) 629-4789
TEL: (800) 52-HI-REL
Newark Electronics, Inc.
Chicago
TEL: (312) 907-5436
FLORIDA
Alliance Electronics, Inc.
Tampa
TEL: (813) 831-7972
Arrow/schweber
Deerfield Beach
TEL: (305) 429-8200
INDIANA
Arrow/schweber
Indianapolis
TEL: (317) 299-2071
Hamilton Hallmark
Indianapolis
TEL: (317) 872-8875
IOWA
Arrow/schweber
Cedar Rapids
TEL: (319) 395-7230
Hamilton Hallmark
Cedar Rapids
TEL: (319) 362-4757
Lake Mary
TEL: (407) 333-9300
Zeus, An Arrow Company
Cedar Rapids
TEL: (319) 395-7230
Dorval, Quebec
TEL: (514) 421-7411
Hamilton Hallmark
Miami
TEL: (305) 484-5482
Nepan, Ontario
TEL: (613) 226-6903
Orlando
TEL: (407) 657-3300
Mississagua, Ontario
TEL: (416) 670-n69
SI. Petersburg
TEL: (813) 541-7440
KANSAS
Arrow/schweber
Lenexa
TEL: (913) 541-9542
Farnell Electronic Services
Burnaby, British Columbia
TEL: (604) 421-6222
Wyle Laboratories
Fort Lauderdale
TEL: (305) 420-0500
Hamilton Hallmark
Kansas City
TEL: (913) 888-4747
Calgary, Alberta
TEL: (403) 273-2780
SI. Petersburg
TEL: (813) 530-3400
Concord, OntariO
TEL: (416) 738-1071
Zeus, An Arrow Company
Lake Mary
TEL: (407) 333-3055
TEL: (800) 52-HI-REL
V. SI. Laurent, Quebec
TEL: (514) 335-7697
Napean, Ontario
TEL: (613) 596-6980
Winnipeg, Manitoba
TEL: (204) 786-2589
GEORGIA
Arrow/Schweber
Duluth
TEL: (404) 497-1300
Hamilton Hallmark
Montreal
TEL: (514) 335-1000
Hamilton Hallmark
Atlanta
TEL: (404) 623-5475
Ottawa
TEL: (613) 226-1700
Wyle laboratories
Duluth
TEL: (404) 414-9045
Vancouver, B.C.
TEL: (604) 420-4101
Toronto
TEL: (416) 795-3859
Zeus, An Arrow Company
Atlanta
TEL: (404) 497-1300
May 1994
Arrow/schweber
Wilmington
TEL: (508) 658-0900
Gerber
Norwood
TEL: (617) 769-6000
Hamilton Hallmark
Boston
TEL: (508) 532-9808
Wyle Laboratories
Burlington
(617) 272-7300
Zeus, An Arrow Company
Wilmington, MA
TEL: (508) 658-4n6
TEL: (800) HI-REL
MICHIGAN
Arrow/schweber
Livonia
TEL: (313) 462-2290
Hamilton Hallmark
Detroit
TEL: (810) 416-5800
Grandville
TEL: (616) 531-0345
MINNESOTA
Arrow/schweber
Eden Prarie
TEL: (612) 941-5280
Hamilton Hallmark
Minneapolis
TEL: (612) 881-2600
Wyle laboratories
Minneapolis
TEL: (612) 853-2280
MISSOURI
Arrow/schweber
SI. Louis
TEL: (314) 567-6888
Hamilton Hallmark
SI. Louis
TEL: (314) 291-5350
MARYLAND
Arrow/Schweber
Columbia
TEL: (301) 596-7800
NEW JERSEY
Arrow/schweber
Marlton
TEL: (609) 596-8000
Pinebrook
TEL: (201) 227-7880
Hamilton Hallmark
Baltimore
TEL: (410) 988-9800
Hamillon Hallmark
Cherry Hill
TEL: (609) 424-0110
Wyle laboratories
Columbia
TEL: (301) 490-2170
Parsippany
TEL: (201) 515-5300
Zeus, An Arrow Company
Columbia
TEL: (301) 596-7800
MASSACHUSETTS
Alliance Electronics, Inc.
Winchester
TEL: (617) 756-1910
15-4
Wyle laboratories
Marlton
TEL: (609) 985-7953
Mountain Lakes
TEL: (201) 822-8358
Zeus, An Arrow Company
Pine Brook
TEL: (201) 882-8780
North American Authorized Distributors (Continued)
NEW MEXICO
Alliance Electronics, Inc.
Albuquerque
TEL: (505) 292-3360
Hamilton Hallmark
Albuquerque
TEL: (505) 345-0001
NEW YORK
Alliance Electronics, Inc.
Binghamton
TEL: (607) 648-8833
Huntington
TEL: (516) 673-1900
ArrowlSchweber
Hauppauge
TEL: (516) 231-1000
Melville
TEL: (516) 391-1276
TEL: (516) 391-1300
TEL: (516) 391-1277
Rochester
TEL: (716) 427-0300
Hamilton Hallmark
Long Island
TEL: (516) 737-0600
Rochester
TEL: (716) 475-9130
Syracuse
TEL: (315) 453-4000
Zeus, An Arrow Company
Hauppauge
TEL: (516) 231-1175
Pt. Chester
TEL: (914) 937-7400
TEL: (800) 52-HI·REL
NORTH CAROLINA
ArrowlSchweber
Raleigh
TEL: (919) 876·3132
EMC
Charlotte
TEL: (704) 394·6195
Hamilton Hallmark
Raleigh
TEL: (919) 872-0712
OHIO
Alliance Electronics, Inc.
Dayton
TEL: (513) 433-7700
ArrowlSchweber
Solon
TEL: (216) 248·3990
Centerville
TEL: (513) 435-5563
EMC
Columbus
TEL: (614) 299-4161
Hamilton Hallmark
Cleveland
TEL: (216) 498-1100
Columbus
TEL: (614) 888-3313
May 1994
Toledo
TEL: (419) 242-6610
Dallas
TEL: (214) 380-6464
Zeus, An Arrow Company
Centerville
TEL: (513) 291-0276
Houston
TEL: (713) 530-4700
WISCONSIN
ArrowlSchweber
Brookfield
TEL: (414) 792·0150
Hamilton Hallmark
Austin
TEL: (512) 258-8848
Hamilton Hallmark
Milwaukee
TEL: (414) 797-7844
Dallas
TEL: (214) 553·4300
Wyle laboratories
Waukesha
TEL: (414) 521-9333
Solon
TEL: (216) 248·3990
OKLAHOMA
ArrowlSchweber
Tulsa
TEL: (918) 252·7537
Houston
TEL: (713) 781-6100
Wyle laboratories
Austin
TEL: (512) 345-8853
Houston
TEL: (713) 879-9953
Hamilton Hallmark
Tulsa
TEL: (918) 254-6100
Zeus, An Arrow Company
Tulsa
TEL: (918) 252·7537
Richardson
TEL: (214) 235-9953
OREGON
AlmaclArrow
Beaverton
TEL: (503) 629·8090
Zeus, An Arrow Company
Carrollton
TEL: (214) 380-4330
TEL: (800) 52-HI-REL
Hamilton Hallmark
Portland
TEL: (503) 526·6202
UTAH
ArrowlSchweber
Salt Lake City
TEL: (801) 973-6913
Wyle Laboratories
Beaverton
TEL: (503) 643·7900
Hamilton Hallmark
Salt Lake City
TEL: (801) 266-2022
PENNSYLVANIA
ArrowlSchweber
Pittsburgh
TEL: (412) 963·6807
Wyle laboratories
West Valley
TEL: (801) 974-9953
Hamilton Hallmark
Pittsburgh
TEL: (412) 281·4150
WASHINGTON
AlmaclArrow
Bellevue
TEL: (206) 643-9992
Zeus, An Arrow Company
Marlton
TEL: (609) 596-8000
Hamilton Hallmark
Seattle
TEL: (206) 881-6697
TEXAS
Alliance Electronics, Inc.
Carroliton
TEL: (214) 492-6700
Wyle laboratories
Redmond
TEL: (206) 881-1150
ArrowlSchweber
Austin
TEL: (512) 835·4180
Zeus, An Arrow Company
Bellevue
TEL: (206) 649-6265
Puerto Rican
Authorized Distributor
Hamilton Hallmark
TEL: (809) 731-1110
South American
Authorized Distributor
Graftec Electronic Sales Inc.
One Boca Place,
Suite 305 East
2255 Glades Road
Boca Raton, Florida 33431
TEL: (407) 994-0933
FAX: 407 994-5518
BRASIL
Graftec Electronics
Praca Lucelia, 21-Sumare
CEP 01256-120 - Sao PauloSP - Brasil
TEL: 55 872 0118
FAX: 55 871 1284
South African
Authorized Distributor
TRANSVAAL
Allied Electronic
Components
10, Skietlood Street
Isando, Ext. 3, 1600
P.O. Box 69
Isando16oo
TEL: 27 11 392 3804119
FAX: 27 11 9749625
FAX: 27 11 9749683
European Sales Offices and Representatives
European Sales Headquarters
Harris S.A.
Mercure Center
100 Rue de la Fusee
1130 Brussels, Belgium
TEL: 32 2 246 2111
FAX: 32 2 246 22 051...09
AUSTRIA
Eurodls Electronics AG
Lamezanstrasse 10
A - 1232 Vienna
TEL: 43 1 61 0 62 0
FAX: 43 1 61 062151
DENMARK
Delco AS
Titangade 15
OK - 2200 Copenhagen N
TEL: 45 35 821200
FAX: 45 35 82 1205
FINLAND
TeknokltOY
Reinikkalan Kartano
SF· 51200 Kangasnieml
TEL: 358 59 432031
FAX: 358 59 432367
FRANCE
Harris Semlconducteurs SARL
• 2-4, Avenue de l'Europe
F - 78140 Velizy
TEL: 33 1 34 65 40 80 (Dist)
TEL: 33 1 34 65 40 27 (Sales)
FAX: 33 1 39 46 40 54
TLX:697060
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Available
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15-5
May 1994
European Sales Offices and Representatives (Continued)
GERMANY
Harris Semiconductor GmbH
, Putzbrunnerstrasse 69
81739 Muenchen
TEL: 49 89 63813 0
FAX: 49 89 6376201
TWX: 529051
Harris Semiconductor GmbH
Kieler Strasse 55 - 59
25451 Ouickborn
TEL: 49 4106 5002 04
FAX: 49 4106 68850
TWX: 211582
Harris Semiconductor GmbH
Wegener Strasse, 511
71063 Sindelfingen
TEL: 49 7031 8694-0
FAX: 49 7031 873849
TWX: 7265431
Ecker Mlchelstadt GmbH
Koningsberger Strasse, 2
Postfach 3344
D - 64720 Michelstadt
TEL: 49 6061 2233
FAX: 49 6061 5039
TWX: 4191630
Erwin W_ Hildebrandt
Nieresch 32
D - 48301 Nottuln-Darup
TEL: 49 2502 6065
FAX: 49 2502 1889
TWX: 892565
Fink Handelsvertretung
Laurinweg, 1
D - 85521 Otlobrunn
TEL: 49 89 6097004
FAX: 49 89 6098170
Hartmut Welte
Rebweg,23A
D - 88677 Markdorf
TEL: 49 7544 72555
FAX: 49 7544 72555
ISRAEL
Aviv Electronics Ltd
Hayetzira Street, 4 Ind. Zone
IS - Ra'anana 43651
PO Box 2433
IS - Ra'anana 43100
TEL: 972 9 983232
FAX: 972 9916510
TWX: 33572
ITALY
HarrisSRL
, Viale Fulvio Testi, 126
20092 Cinisello Balsamo
TEL: 3922620761
(Disti & OEM ROSE)
TEL: 39 2 240 95 01
(Disti & OEM Italy)
FAX: 39 2 248 66 20
39226222158 (ROSE)
TWX: 324019
NETHERLANDS
Harris Semiconductor SA
Benelux OEM Sales Office
Mercuriusstraat 40
NL - 5345 LX Oss
TEL: 31 412038561
FAX: 31412034419
Aurlema Nederland BV
Beatrix de Rijkweg, 8
NL - 5657 EG Eindhoven
TEL: 31 40 502602
FAX: 3140510255
TWX: 51992
PORTUGAL
Crlstalonlca Componentes
De Radio E Televlsao Lda
Rua Bernardim Ribeiro, 25
P - 1100 Lisbon
TEL: 351 13534631
FAX: 351 13561755
TWX: 64119
SLOVENIA
Avtotehna
Celovska 175
P.O. Box 593
Ljubljana
TEL: 366 61 551 287
FAX: 386 61 1 594 112
SPAIN
Elcos S.L.
eI Avd. de Valladolid 55
2, inter. 1
SP - 26008 Madrid
TEL: 341 5417510
FAX:3415417511
SWEDEN
Delco AS
Kemistvagen, lOA
Box 516
S -183 25 Taby
TEL: 46 8 630 86 00
FAX: 46 8 732 49 20
TURKEY
EMPA
Elektronik Mamulleri
Pazarlama AS
Besyol Londra Aslalti
TK - 34630 Selakoy/lstanbul
TEL: 90 1 599 3050
FAX: 90 1 598 5353
TWX: 21137
UNITED KINGDOM
Harris Semiconductor Ltd
, Riverside Way
Camberley
Surrey GU15 3YO
TEL: 44 276 686 886
FAX: 44 276 682 323
Laser Electronics
Ballynamoney
Greenore
Co. Louth, Ireland
TEL: 353 4273165
FAX: 353 4273518
TWX: 43879
S.M.D.
182 Hall Lane
Aspull, Wigan Lancs WN2 2SS
TEL: 44 942 54867
FAX: 44 942 525317
Stuart Electronics Ltd.
Phoenix House
Bothwell Road
Castle hill, Carluke
Lanarkshire ML8 5U F
TEL: 44 555 51566
FAX: 44 555 51562
TWX: 777404
European Authorized Distributors
AUSTRIA
EBV Elektronl k
Diefenbachgasse 35/6
A - 1150 Vienna
TEL: 43 1 8941774
FAX: 43 1 894 17 75
Eurodls Electronics AG
Lamezanstrasse 10
A - 1232 Vienna
TEL: 43 1 61 062 0
FAX: 43 1 61 062 151
BELGIUM
Diode Belgium
, Keiberg II
Minervastraat, 14182
B-1930 Zaventem
TEL: 32 2 725 46 60
FAX: 32 2 725 45 11
TWX: 64475
EBV Elektronik
Excelsiorlaan 35
B - 1930 Zaventem
TEL: 32 2 7209936
FAX: 32 2 720 81 52
Eurodls Inelco SAINV
, Avenue des Croix de
Guerre,116
B - 1120 Brussels
TEL: 32 2 247 49 69
FAX: 32 2 215 81 02
TWX: 644'(5
DENMARK
Dltz Schweitzer AIS
Vallensbaekvej 41
Postboks5
OK - 2605 Brondby
TEL: 45 42 45 30 44
FAX: 45 42 45 92 06
TWX: 33257
FINLAND
Bexab Finland
Teollisuustie
SF - 65611 Mustasaari
TEL: 358 61 32 22 222
FAX: 358 61 32 22 962
Ylelselektronlikka OY
Telercas
P.O. Box 63
Luomannotko, 6
SF - 02201 Espoo
TEL: 358 0 4526 21
FAX: 358 0 45262231
FRANCE
3D ZI des Glalses
618 rue Ambroise Croizat
F - 91127 Palaiseau Cedex
TEL: 33 1 64 47 29 29
FAX: 33 1 64470084
TWX: 603341
Arrow Electronlque S.A.
73 - 79, Rue des Solets
Silic585
F - 94663 Rungis Cedex
TEL: 33 1 49 78 49 78
FAX: 33 1 4978 05 96
TLX:265185
'Field Application Assistance Available
15-6
Avnet EMGSA
• 81, Rue Pierre Semard
F-92320 Chatillon Sous Bagneux
TEL: 33 1 49 65 27 00
FAX: 33 1 49 65 27 38
TWX: 632247
CCI Electronique
, 5, Rue Marcelin Berthelot
Zone Industrielle D'Antony
BP92
F - 92164 Antony Cedex
TEL: 33 1 46744700
FAX: 33 1 40 96 92 26
TWX: 203881
Harris Semiconductor
Chip Distributors
Edgetek
Zai De Courtaboeul
Avenue Des Andes
91952 Les Ulis Cedex
TEL: 33 1 64 46 06 50
FAX: 33 1 69 28 43 96
TWX: 600333
Elmo
Z. A. De La Tuilerie
B. p. 1077
78204 Mantes-La-Jolie
TEL: 331 34 77 16 16
FAX: 33 1 34 77 95 79
TWX: 699737
European Authorized Distributors
Hybritech CM (HCM)
7, Avenue Juliot Curie
F - 17027 LA Rochelle Cedex
TEL: 33 46 45 1270
FAX: 33 46 45 04 44
TWX: 793034
EASTERN COUNTRIES
HEVGmbH
Halblelter-Electronlc
Vertriebs GmbH
AlexanderplalZ 6
0- 10178 Berlin
Postfach 90
o -10173 Berlin
TEL: 49 30 248 34 00
FAX: 49 30 248 34 24
TWX: 307011
GERMANY
Alfred Neye Enatechnik GmbH
Schillerstrasse 14
D - 25451 Quickborn
TEL: 49 4106 6120
FAX: 49 4106 61 2268
TWX: 213590
Avnet/E2000
Stahlgruberring, 12
D - 81829 Muenchen
TEL: 49 89 45 11 001
FAX: 49 89 45110129
TWX: 522561
EBV Elektronik
Hans-Pinsel-Strasse 4
D - 85540 HAAR-beiMuenchen
TEL: 49 89 456 10-0
FAX: 49 89 46 44 88
HED Heinrich Electronic
Distribution GmbH
Steeler Strasse 529
D - 45276 Essen
TEL: 49 201 5636225
FAX: 49 201 5636 268
Indeg Industrle Elektronik
GmbH
Postfach 1563
D - 66924 Pirmasens
Emil Kommerling Str. 5
D - 66954 Pirmasens
TEL: 49 6331 94 065
FAX: 49 6331 94064
TWX: 452269
SascoGmbH
Hermann-Oberth Strasse 16
D - 85640 PulZbrunnBei-Muenchen
TEL: 49 89 46110
FAX: 49 89 4611270
TWX: 529504
Spoerle Electronic KG
Max-Planck Strasse 1-3
D - 63303 Dreieich
Bei-Frankfurt
TEL: 49 6103 30 48
FAX: 49 6103 30 42 01
TWX: 417972
May 1994
(Continued)
GREECE
SemlconCo.
104 Aeolou Street
GR - 10564 Athens
TEL: 30 1 32 53 626
FAX: 30 13216063
TWX: 216684
NORWAY
Hans H. Schlve A/S
Undelstadlia 27
Postboks 185
N - 1371 Asker
TEL: 4766 900 900
FAX: 47 66 904 484
TWX: 19124
ISRAEL
Aviv Electronics Ltd
HayelZira Street 4, Ind. Zone
IS - 43651 Ra'anana
PO Box 2433
IS - 43100 Ra'anana
TEL: 972 9 983232
FAX: 9729916510
PORTUGAL
Crlstalonlca
Componentes De Radio E
Televlsao, Lda
Rua Bernardim Ribeiro, 25
P - 1100 Lisbon
TEL: 351 13534631
FAX: 351 1356 17 55
TWX: 64119
ITALY
Eurelettronlca SpA
Via Enrico Fermi, 8
I - 20090 Assago (MI)
TEL: 39 2 457 841
FAX: 39 2 488 02 75
SPAIN
Amltron-Arrow S.A_
Albasanz, 75
SP - 28037 Madrid
TEL: 34 1 304 30 40
FAX: 43 1 327 24 72
EBV Elektronlk SRL
Via C. Frova, 34
I - 20092 Cinisello Balsamo (MIl
TEL: 39 2 660 17111
FAX: 39 2 660 17020
EBV Elektronl k
Calle Maria Tubau, 6
SP - 28049 Madrid
TEL: 34 1 358 86 08
FAX: 34 1 358 85 60
Lasl Elettronlca SpA
Viale Fulvio Testi 280
I - 20126 Milano
TEL: 39 266 10 13 70
FAX: 39 2 66101385
TWX: 352040
SWEDEN
Bexab Sweden AB
P.O. Box 523
i
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2017:07:23 12:11:03-08:00
Modify Date : 2017:07:23 12:54:03-07:00
Metadata Date : 2017:07:23 12:54:03-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:a962a55c-7fff-294e-b6e9-3d9d481801c0
Instance ID : uuid:3c37a955-41c3-8d43-bf3a-e05625126c8b
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 946
EXIF Metadata provided by EXIF.tools