1994_Harris_Intelligent_Power_ICs 1994 Harris Intelligent Power ICs

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Ell ~!!
HARRIS SEMICONDUCTOR

This Intelligent Power ICs Databook represents the full line of Harris Semiconductor
Intelligent Power· products for commercial, industrial and automotive applications
and supersedes previously published Intelligent Power product databooks under the
Harris, GE, RCA or Intersil names. For a complete listing of all Harris Semiconductor
products, please refer to the Product Selection Guide (SPG-201 S; ordering information belOW).
For complete, current and detailed technical specifications on any Harris devices
please contact the nearest Harris sales, representative or distributor office; or direct
literature requests to:

Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-25
Melbourne, FL 32901
TEL: 1-800-442-7747
FAX: (407) 724-3937
See Section 14 for Data Sheets Available on AnswerFAX

U.S. HEADQUARTERS
Harris Semiconductor
1301 Woody Burke Road
Melboume, Florida 32902
TEL: (407) 724-3000

EUROPEAN HEADQUARTERS
Harris Semiconductor
Mercure Center
Rue de la Fusee, 100
1130 Brussels, Belgium
TEL: 32224621 11

SOUTH ASIA
Harris Semiconductor H.K. Ltd
13IF Fourseas Building
208-212 Nathan Road
Tsimshatsui, Kowloon Hong Kong
TEL: (852) 723-6339

NORTH ASIA
Harris KK
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-08 Japan
TEL: (81) 3-3345-8911

See our
specs in

CAPS

Copyright C Harris Corporation 1994
(AU Rights Reserved)
Printed in USA, 411994

INTELLIGENT POWER PRODUCTS
Harris Semiconductor is a pioneer in developing and producing advanced Intelligent
Power products for the most demanding commercial, industrial and automotive applications in this world -- and beyond.
This databook fully describes Harris Semiconductor's line of Intelligent Power products. It includes a complete set of data sheets for product specifications, application
notes with design details for specific applications of Harris products, and a description of the Harris quality and high reliability program.
Harris Semiconductor also offers an extensive line of power discrete components.
These devices (MOSFETs, MegaFETs, L2FETs, enhanced-mode insulated gate
bipolar transistors, ruggedized power MOSFETs and advanced discrete) can be
found in the Harris Power MOSFETs and Harris MCTIIGBT/Diodes catalogs.
This book is divided into 15 major sections. Section 1 contains general information.
Sections 2 through 10 cover each major category of devices offered by Harris Intelligent Power. Section 11 provides additional application notes to supplement the data
sheets. Harris Quality and Reliability, Packaging Information, AnswerFAX and Sales
Offices appear in Section 12, 13, 14 and 15, respectively.
It is our intention to provide you with the most up-to-date information on Intelligent
Power Products. For complete, current and detailed technical specifications on any
Harris devices please contact the nearest Harris sales, representative or distributor
office; or direct literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-25
Melbourne, FL 32902
1-800-442-7747
FAX 407-724-3937
See Section 14 for Data Sheets Available on AnswerFAX

Harris Semiconductor products are sold by description only. All specifications in this product guide are
applicable only to packaged products; specifications for die are available upon request. Harris reserves the
right to make changes in circuit design, specifications and other information at any time without prior
notice. Accordingly. the reader is cautioned to verify that Information In this publication Is current before
placing orders. Reference to products of other manufacturers are solely for convenience of comparison
and do not imply total equivalency of design, performance, or otherwise.

INTELLIGENT POWER
INTEGRATED CIRCUITS
FOR COMMERCIAL, INDUSTRIAL & AUTOMOTIVE APPLICATIONS
General Information
Low Side Switches
High Side Switches
Half Bridges
AC to DC Converters
Full Bridges
Regulators/Power Supplies
Protection Circuits
Multiplex Communication Circuits
Special Functions _
I

Application Notes _
Harris Quality and Reliability _
Packaging Information _
How To Use Harris AnswerFAX _
Sales Offices _ _

iii

TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook,
please contact the Field Applications Engineering staff available at one of the following Harris Sales Offices:
UNITED STATES
CALIFORNIA

Costa Mesa ........................ 714-433-0600
San Jose .......................... 408-985-7322
Woodland Hills .•.................... 818-992-0686

FLORIDA

Melbourne ......................... 407-724-3576

GEORGIA

Duluth ......................•...... 404-476-2035

ILLINOIS

Schaumburg ........................ 708-240-3480

MASSACHUSETTS

Burlington .......................... 617-221-1850

NEW JERSEY

Voorhees .......................... 609-751-3425

NEW YORK

Great Neck ......................... 516-829-9441

TEXAS

Dallas ............................. 214-733-0800

INTERNATIONAL
FRANCE

Paris. . . . . . • . . . . . . . . . . . . . . . . . . . .. 33-1-346-54046

GERMANY

Munich ...•....................•.. 49-8-963-8130

HONG KONG

Kowloon ........................... 852-723-6339

ITALY

Milano ............................ 39-2-262-0761

JAPAN

Tokyo ........................... 81-33-345-8911

KOREA

Seoul .....•...................... 82-2-551-0931

SINGAPORE

Singapore ........................... 65-291-0203

UNITED KINGDOM

Camberley ....................... 44-2-766-86886

For literature requests, please contact Harris at 1-800-442-7747 (1-SOO-4HARRIS)

iv

PRODUCT STATUS DEFINITIONS
DEFINITION OF TERMS
DATA SHEET
IDENTIFICATION

PRODUCT STATUS

DEFINITION

Advance Information

Formative or in Design

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

Preliminary

Pre Production Samples
Available

This datasheet contains preliminary data, and supplementary data will be published at a later date. Harris
Semiconductor Corporation reserves the right to
make changes at any time without notice in order to
improve design and supply the best possible product.

No Identification
Noted

Full Production

This data sheet contains final specifications. Harris
Semiconductor Corporation reserves the right to
make changes at any time without notice in order to
improve design and supply the best possible product.

v

INTELLIGEN
POWERICs

I

Ii.

1

GENERAL INFORMATION

PAGE
GENERAL ORDERING INFORMATION ....................................................... .

1-3

ALPHA NUMERIC PRODUCT INDEX ...................•......................................

1-4

PRODUCT INDEX BY FAMILY ............................................................... .

1-6

APPLICATION INDEX ..................................................................... .

1-9

INTELLIGENT POWER PRODUCTS CROSS REFERENCE LIST ..............................•.....

1-12

1-1

Z
.,JO

liHi

W::s
Za:
WO

CJu.
~

General Ordering Information - - - - - - - .
PRODUCT CODE EXAMPLE

PART NUMBER

2

HIP

TV

o

5

J

T

o

P

T

PACKAGE

VOLTAGE

PREFIX

FAMILY

H: Harris

IP: Intelligent Po_

V: High Voltage

P: PIastlc DIP

Multiply by 10 for C8pab1tity
(I.e. 50 = SOOV

B: SOIC

HNegative (-) Is Used for First
DIgit. Do Not Multiply by 10

M:

S: PowerSIP

(I.e. -6 .. 5V)

PLCC

J: Ceramic DIP
W:Wafer

TOPOLOGY

D: Die

0: Low Side SwItch

1: High Side Switch
2: HaH BrIdge

TEMPERATURE

3: AC/DC

Converters

A: Automotive
(-40"0 to +15O"C)
C: CommercIal
(O"C to +7O"C)

4: Full Bridge

5: RegulatorlPower
Supply

I: IndusIJIaI
(-40"0 to ..asoc)
M: MIDtary

7: Multiplex
Convnunlcatlon Clroult
9: Special Function

(-55"C to +1250 C)

D: EDP
(O"C to ..asoc)

SEQUENTIAL
NUMBER
Based on Order of
Development ()-9

1-3

Alpha Numeric Product Index
PAGE
CA723

Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 15DmA
Without Extemal Pass Transistors. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-3

CA723C

Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 15DmA
Without External Pass Transistors. . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . • . . . . . . . . . . . . .

7-3

CA1523

Voltage Regulator Control Circuit for Variable Switching Regulator ...• ,. . . . . . . . . . . . ..

7-11

CA1524

Regulating Pulse Width Modulator. . . . . . . .• .. . . . . .. . . .. . . . .. . . . . . . . . . . . . . . . .. .

7-16

CA2524

Regulating Pulse Width Modulator ........•....•..............• , . . . . . . . . . . . . . .

7-16

CA3020

Multipurpose Wide-Band Power Amps Military. Industrial and Commercial Equipment at
Frequency Up to 8MHz . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . • . . ..

10-3

CA3059

Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . . . .

5-3

CA3079

Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . . . .

5-3

CA3085

Positive Voltage Regulators from 1.7V to 46V at Currents Up to l00mA .. . . • .. . . . .. . . .

7-31

CA3085A

Positive Voltage Regulators from 1.7V to 46V at Currents Up to 100mA .• . . . .. . . . . . . . .

7-31

CA3085B

Positive Voltage Regulators from 1.7V to 46V at Currents Up to 100mA .. " . .. . . . .. . •.

7-31

CA3094

Programmable Power Switch/Amplifier for Control and General Purpose Applications . . ..

10-11

CA3165

Electronic Switching Circuit. • • • • • . . • • . . . . . • . • . . . . . • • . • . • • . . • • • . • . . . . . . . . . . . ..

10-25

CA3228

Speed Control System with Memory. .••. . . .•.•. . .. .••.••. ••• .•• ..•• .•. . . . .. . ..

10-31

CA3242

Quad-Gated Inverting Power Driver For Interfacing Low-Level Logic to High
Current Load. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . • . . • . . . . . . . . . . . . . . . . . . .

2-3

CA3262

Quad-Gated Inverting Power Drivers ................. , ......•..•......... ,. . . .

2-7

CA3262A

Quad-Gated Inverting Power Drivers. . . . . . .•. .. . .. . . . .. . . . .. . . . .• . . . .. . . . .. . . .

2-7

CA3272

Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output.. . . . .. . . .

2-13
2-13

CA3272A

Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output ..........

CA3273

High-Side Driver . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3

CA3274

Current Limiting Power Switch With Current Limiter Sense Flag ............ " . . .. . ..

10-40

CA3275

Dual Full Bridge Driver .. . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .

6-3

CA3277

Dual 5V Regulator with Serial Data Buffer Interface for Microcontroller
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . • . . .

7-39

CA3282

CMOS Octal Serial Solenoid Driver. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . .

2-20

CA3292A

Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output .... . . . . . .

2-13

CA3524

Regulating Pulse Width Modulator. •. . . . ••. •.. .• .. .. . .•. . . . . .. • .. ••• .. . . . .. . . .

7-16

CDP68HC68S1

Serial Bus Interface. . . • . . . • . . . . • . . . • . • • • • • • • . . • . . • • • • • . . . . • . . . . . . . . • . . . . . . .

9-3

HIP0080

Quad Inverting Power Drivers with Serial Diagnostic Interface. • . . . . . . . . . . . . . . . . • . . . .

2-28

HIP0081

Quad Inverting Power Drivers with Serial Diagnostic Interface. . . . . . . • . . • . . . . . . . . . . . .

2-28

HIP0082

Quad Power Driver with Serial Diagnostic Interface. . . . • . . . . . . . . . . • . . • • . . . . . . . . • • .

2-36

HIP1030

1A High Side Driver with Overload Protection. • . . . . . • . . . . . . . . . . . . . . . . . . . . • . . • . . . .

3-6

HIP1031

Half Amp High Side Driver with Overload Protection.. . . . .. . . . . . . . . .. •• . .. . . . .. . . .

3-10

HIP1090

Protected High Side Power Switch with Transient Suppression. . . . . . . .. . . . .. . . . .. . . .

3-13

HIP2030

30V MCTIIGBT Gate Driver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • • . . . .

4-3

HIP2500

Half Bridge 500V oc Driver. . . . . . .. . . . .. . . . .. . . . . . . . . . . . . . . . . . • .. • . . .. . . . . . . . .

4-10

1-4

Alpha Numeric Product Index

(Continued)

PAGE
HIP4010

Power Full Bridge Driver for Low Vohage Motor Drive with Direction and Brake Control ....... .

HIP4011

Three Phase Brushless DC Motor Controller ..............................•.....

6-7
6-11

HIP4080

80V/2.SA Peak, High Frequency Full Bridge FET Driver..•.••..•............•......

6-14

HIP4080A

80V/2.SA Peak, High Frequency Full Bridge FET Driver......•..........•.....•....

6-28

HIP4081

80V/2.5A Peak, High Frequency Full Bridge FET Driver........................... .

6-41

HIP4081A

80V/2.5A Peak, High Frequency Full Bridge FET Driver........................... .

6-54

HIP4082

80V/l.25A Peak Current Full Bridge FET Driver ................................. .

6-67

HIPS060

Power ControllC Single Chip Power Supply.................•...................

7-47

HIPS061

7 A, High Efficiency Current Mode Controlled PWM Regulator ..•....................

7-53

HIPS062

Power ControllC Single Chip Dual Switching Power Supply ....•......•......•.....

7-73

HIPS063

Power ControllC Single Chip Power Supply..............•.................•....

7-80

Z

...J

O

~~

HIPSSOO

High Voltage IC Half Bridge Gate Driver ...•.........•...••.......•••...........

7-84

HIPS600

Thermally Protected High Voltage Linear Regulator ..........••....••........•....

7-94

Za:

HIP7010

J1850 Byte Level Interface Circuit. ........................................... .

9-17

HIP7020

J1850 Bus Transceiver I/O for Multiplex Wiring .................................. .

--;-".

;,~t$6PS~~·I.1{,gra~~jh
;";: ... , ;...~;,

CA01i31'

Pin

Fairchild

USR712a;312

LM72;1H

Pin

Fairchild

U5R7123393

CA0723CT

Pin

Fairchild

U6A7123393

CA0723CE

Pin

Fairchild

Pin

Fairchild

.!-W23CN

,

CA1$91E

C;A30eeEPin,·.·· . Fairchild

1IA723CA

GA01~3CE

. LM723CN
.CA0723CT

l'

Pin

Signetics

Pin

Signeti(:S

.~in

Texas Instr.

1IA723C4

LM723CH

Pin

Texas I.nstr.

1IA723CN .

CA0723CE

Pin

Philips

CA07230e

Pin

Signetics

1IA723CN

NOtE:'1.-

.. (

COMPETITOR

1IA723CN

CA0723CE

Pin

Texas Instr.

1IA723CN

LM723CN

Pin

Philips

1IA723CN

LM723CN

Pin

Signetics

1IA723CN

LM723CN

Pin

Texas Instr.

J;lA723HC

CA0723CT

Pin

AMD

j)A723HC

LM723CH

Pin

Motorola

pA723HM

CA0723T

Pin

Fairchild

jJA123HM

LM723H

Pin

Fairchild

1IA123ML

CA0723T

Pin

Fairchild

J.lA723ML

LM723H

Pin

Texas Instr.

jJA723MN

CA0723E

Pin

Texas Instr.

j)A723PC

CA0723CE

Pin

Motorola

1IA723PC

LM723CN

Pin

Motorola

j)A780PC

CA3070

Upgrade

Fairchild

j)A787PC

CA3126E

Upgrade

Fairchild

UC1524AJ

CA1524F

Pin

Unitrode

UC1524N

CA1524E

Pin

Unitrode

UC3524N

CA3524E

Pin

Unitrode

UDN2541B

CA3262AE

Pin

Sprague

UDN2547EB

CA3272Q

Pin

Sprague

ULN·2111A

CA2111AE

Pin

Sprague

ULN-2.124A

CA3070

Pin

Sprague

ULNoo2287A

CA3088E

Pin

Sprague

ULN-2289A

CA3089E

Function

Sprague

ULN·2289A

CA3089E

Function

Sprague

ULN-2291M

CAt391E

Pin

Sprague

ULN2111N

CA2111AQ

Pin

Sprague

ULN2212

CA3012

Function

Sprague

ULN3889A

CA3189E

Upgrade

Sprague

VI·7660-2

ICL7660ClV

Pin

Datel

VH660-2

ICL7660SClV

UpgradelPin

Datel

.'.

...

Pin

j)A30891; .

'.'

PIN!
FUNCTION
UPGRADE

Teledyne

U5R1723312

U6A71233.93

HARRIS
PART
NUMBERS

I~~te$ SpecificatiQlls M&o/ Vary
1·16

INTELLIGEN
POWERICs

2

LOW SIDE SWITCHES

PAGE
LOW SIDE SWITCHES SELECTION GUIDE . ................................................... .

2-2

LOW SIDE SWITCHES DATA SHEETS

CA3242

w(I)

QW

Quad-Gated Inverting Power Driver For Interfacing Low-level logic to High
Current load ......................•..•...............•.••......•••.....

2-3

CA3262A, CA3262 Quad-Gated Inverting Power Drivers ...•....................•.........•.....

2-7

CA3272, CA3272A, Quad-Gated Inverting Power Drivers with Fault Mode Diagnostic Flag Output. ...•...•
CA3292A

2-13

CA3282

CMOS Octal Serial Solenoid Driver ........................................ .

2-20

HIP0080, HIPOO81

Quad Inverting Power Drivers with Serial Diagnostic Interface ....................•

2-28

HIP0082

Quad Power Driver with Serial Diagnostic Interface ............................ .

2-36

2-1

-:I:
(1)(.)

~1::
O~

..J(I)

Low Side Switches Selection Guide
,

TYPE NUMBERS
CA3242
QUAD

CA3262
QUAD

CA3262A
QUAD

CA32n
CA3212A
QUAD

Max. Output Voltage, No Load

50V

60V

60V

60V

32VTyp
(Clamp)

Max. Rated DC Load Current

0.6A

0.1A

0.1A

0.6A

0.6A

0.8Vat 0.6A

0.6Vat 0.6A

0.5Vat 0.6A

O.4Vat 0.5A

0.4VaI0.5A

35V

40V

40V

40V

28V

1.4A
(Latches-Off)

1.6A

1.3A

1.2A

1.2A

Output Thermal Limiting and/or"
Shutdown Protection (Temperature TJ )

No

+155°e

+155OC

+165°e

+165°C

Thermal Shutdown, Hysteresis

No

No

No

1SOC

15°C

Fault Indicator Flag

No

No

No

Yes

Yes

Diagnostic Feedback

No

No

No

No

No

Temperature Range
-400 C to +(Max) °e

105

85

125

125

125

16DIP

16DIP

16 DIP and
28PLCC

28PLCC

28PLCC

BIPOLAR TYPES

Max. VSAT OUtput Voltage
Max. Load Switching Voltage, VCESUS or
VCLAMP Limited
Output Current Limiting and/or
Shutdown Protection

Package

CA3292A
QUAD

TYPE NUMBERS
HIP0080 QUAD

HlPO081 QUAD

HIPOO82 QUAD

CA3282
OCTAL

Max. Oulput Voltage, No Load

36VTyp
(Clamp)

80VTyp
(Clamp)

80VTyp
(Clamp)

32VTyp
(Clamp)

Max. Rated DC Load Current

lA

2A

2A and 5A

lA

MOSFET TYPES

Max.

RoN Output Resistance

1.00 atO.5A

0.50 at lA

0.510 at 2A

1.0OatO.5A

Max. Load Switching Voltage (VCESUS or VCLAMP
Limited)

21V

13V

12V

30V

Output Current Limiting and/or Shutdown Proteclion

1.8A
(Latches-Qlf)

3.SA
(Latches-Off)

2.1A and 5.1A
(Latches-Off)

I.SA
(Latches-Off)

Output Thermal limiting and/or Shutdown Proteclion, TJ

+15000

+15O"C

+165°C (Aag)

No

Thermal Shutdown, Hysteresis

15°C

15°C

150 e

No

Fault Indicator Flag

Yes

Yes

Yes

Yes

Diagnostic Feedback

Yes

Yes

Yes

Yes

Temperature Range -40°e to +(Max) °C

125

125

125

125

28PLCe

15SIP

15 SIP

15SIP

Package

2-2

CA3242
Quad-Gated Inverting Power Driver For
Interfacing Low-Level Logic to High Current Load

April 1994

Features

Description

• Driven Outputs Capable of Switching 600mA Load
Currents Without Spurious Changes In Output State

The CA3242 quad-gated inverting power driver contains four
gate switches for interfacing low-level logic to inductive and
resistive loads such as: relays, solenoids, AC and DC
motors, heaters, incandescent displays, and vacuum fluorescent displays.

• Inputs Compatible with TTL or 5V CMOS Logic
• Suitable for Resistive or Inductive Loads

Output overload protection is provided when the load current
(approximately 1.2A) causes the output VCE(sat) to rise
above 1.3V. A built-in time delay, nominally 25J.!S, is provided
during output turn-on as output drops from Voo to VSAT' That
output will be shut down by its protection network without
affecting the other outputs. The corresponding Input or
Enable must be toggled to reset the output protection circuit.

• Output Overload Protection
• Power-Frame Construction for Good Heat Dissipation

Applications
• Relays
• Solenoids

Steering diodes in the outputs in conjunction with external
zener diodes protect the IC against voltage transients due to
switching inductive loads.

• AC and DC Motors
• Heaters

To allow for maximum heat transfer from the chip, the four
center leads are directly connected to the die mounting pad.
In free air, junction-to-air thermal resistance (ROJA) is SOoCI
W (typical). This coefficient can be lowered by suitable
design of the PC board to which the CA3242 is soldered.

• Incandescent Displays
• Vacuum Ruorescent Displays

Ordering Information
PART NUMBER

CA3242E

TEMPERATURE
RANGE

-40"C to +1 05°C

Pinout

PACKAGE
16 Lead Plastic DIP

Block Diagram
CA3242 (PDIP)

TOP VIEW

TRUTH TABLE

CAUTION: These devices are sensRlve to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

Copyright @ Harris Corporation 1994

2-3

ENABLE

IN

H

H

L

H

L

H

L

X

H

File Number

OUT

1561.2

wen
OW

-:x:
en(.)

~t::
O~

....len

Specifications CA3242
Absolute Maximum Ratings (Note 1)

Thermal Information

Logic Supply Voltage, Vcc ••••••••••••••••••••••••••••.• 7V
Logic Input Voltage, VIN • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • 15V
Output Voltage, VCEX •.••••••.••..••.••••.•••••••••• 50Voc
Output Sustaining Voltage, VCESUS .•.....•.•.....•.••• 35VDC
Output Current, 10 , •..••.......••..•.•....•.••....•.. 1Aoc

Thermal Resistance
8JA
8JL
Plastic DIP.. • •• • • • •• •• • • •• • •• • • . 600 eIW
Plastic DIP (to Pins 4,5,12,13) • • • • •
12°CIW
Power Dissipation, Po
Up to 60°C •••••••••••.•••••••••••.••••••••••••••• 1.5W
Above 60°C •••••••••••••••••• Derate Linearly at 16.6mWI"C
Up to 900C wlHeat Sink (pC Board) •.••••••••••••••••• 1.5W
Above 900C wlHeat Sink (PC Board) •• Derate Linearly at 25mWI"C
Ambient Temperature Range
Operating •••••••.•••••••••.••••••••••••• -40"C to +1 05°C
Storage ..•.....••.•.•••••.•.••.••••.... -55°C to +150°C
Maximum Junction Temperature, TJ ••••••••••••••••••• +l50oC
Lead Temperature (During Soldering)
At distance 1/16 inch ± 1/32 Inch (1.59 ± 0.79mm) from
case for lOs max ••••••••••••••••••••••••••.••••• +2650 C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications At TA = -400 C to +1 050 C, Vcc = 5V Unless Otherwise Specified
PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

ICEX

VCE = 50V, VIN = O.BV

-

100

IIA

Output Sustaining Voltage

VCE(SUS)

Ic = 100mA, VIN = O.BV

30

-

V

Collector Emitter Saturation Voltage

VCE(SAT)

Ic = 100mA, VIN = 2.4V

0.35

V

0.6

V

O.B

V

O.B

V

±10

IIA

Output Leakage Current

Input Low Voltage

VIL

Input Low Current

IlL

VIN=O.BV

-

Input High Voltage

VIH

Ic=600mA

2

-

V

Input High Current

IIH

Ic = 700mA, VIN = 4.5V

10

IIA

Supply Current ON

IcC(oN)

BO

mA

Supply Current OFF

ICC(OFF)

5

mA

100

IIA

1.B

V

Ic = 400mA, VIN = 2.4V
Ic = 6OOmA, VIN = 2.4V

Clamp Diode Leakage Current

IR

VR =50V

Clamp Diode Forward Voltage

VF

IF= 1A

-

IF= 1.5A

-

2.5

V

Ic = 700mA, Vcc = VIH = 5.5V

Turn-On Delay

\PHL

-

20

jlS

Turn-Off Delay

\PLH

-

30

jlS

NOTE:
1. TA = +25°C, Unless Otherwise Specified

2-4

~

~

f\1

"'"

1\)-

NO"[E:·Allf~stance

GND

values are ko, aU capacitors are in pF.

FtGlffllt,. ~ATlCDlAGRAM OF THECA3242 (SW\tetl.$ECtIONA)

LOW SIDE

SWITCHES

CA3242

CA3242

FIGURE 3. TYPICAL APPLICATIONS FOR THE CA3242 QUAD

FIGURE 2. LOGIC DIAGRAM FOR EACH OUTPUT

S1
R1

LATCH ·1

S2
R2

LATCH-2

S3
R3

LATCH-3

54
R4

LATCH -4

ENABLE
MISC. SWITCHING
APPUCATIONS

FIGURE 5. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER

FIGURE 4. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER

2-6

HARRIS
SEMICONDUCTOR

CA3262A,CA3262
Quad-Gated Inverting Power Drivers

April 1994

Features

Description

•
•
•
•
•
•
•

The CA3262 and CA3262A are used to interface low· level
logic to high current loads. Each Power Driver has four
inverting switches consisting of a non-inverting logic input
stage and an inverting low-side driver output stage. All input
stages have a common enable input. Each output device
has independent current limiting (I LIM) and thermal limiting
(TLIM) for protection from overload conditions. Steering
diodes connected from each output (in pairs) to the Clamp
pins may be used in conjunction with external zener diodes
to protect the IC against overvoltage transients that result
from inductive load switching. To allow for maximum heat
transfer from the chip, all ground pins on the DIP and PLCC
package are directly connected to the mounting pad of the
chip. An integral heat spreading lead frame directly connects
the bond pad and ground leads for good heat dissipation.

Independent Over-Current Umltlng on Each Output
Independent Over-Temperature Umltlng On Each Output
Output Drivers Capable of Switching 700mA Load
Inputs Compatible With TTL or SV CMOS Logic
Suitable For Resistive, Lamp or Inductive Loads
Power-Frame Construction for Good Heat Dissipation
Operational Temperature Ranges
- CA3262A •••••••••••••••••••••• -40oC to +12SoC
- CA3262 •••••••••••••••••••.•••• -40 oC to +8SoC

Applications

System Applications

•
•
•
•
•
•

•
•
•
•

Solenoid
Relay
Light
Steppers
Motors
Displays

Pinouts

Automotive
Appliance
Industrial Control
Robotics

The CA3262 and CA3262A can drive four incandescent
lamp loads without modulating their brilliance when the
·cold" lamps are energized. Outputs may be parallel connected to drive high current loads. The maximum output cur·
rent of each output is determined by the over-current limiting
threshold which is typically 1.2A but may be as low as 0.7A.

CA3262, CA3262A (PDIP)
TOP VIEW

Ordering Information
TEMP. RANGE

PACKAGE

CA3262E

PART NUMBER

-4O"C to +85°C

16 Lead Plastic DIP

CA3262AE

-40oC to +125°C

16 Lead Plastic DIP

CA3262AQ

-40oC to +125°C

28 Lead PLCC

Functional Block Diagram
"""""''''''''''''''''''''''''''''''''''1
Vcco-t-+
,
v+
:
TUM

CA3262A (PlCC)
TOP VIEW

~!i~~~j
GND

GND

OUT 0

IN 0

ot'----::fl~C;:.~

IN C

. - - - -......-+-0 OUT C
o-t----tr)..:l:::;::~

CLAMP

ENABLE

GND

..---_-+0 OUT B

GND
GND
GND

IN B 0-;:---+-1
CLAMP

r-----~~~OUTA

IN A <>i--tf"""""'l~I=:;:~

CAUTION: These devices are senshive to electrostatic discharge. Users should follOw proper I.C. Handling Procedures.
Copyright @Harris Corporation 1994

2-7

File Number

1836.4

CA3262A, CA3262
Vee - - -- - --- ______ -- - - --- -- -- --- -- - -- -- - ---- __
+5V P.S. o·
• v+
11 (18):

,

a. _____ --_

~

:
: OUTD

IND:

e (16)!

,,
,
INC:
TTL OR
CMOS
LOGIC
LEVEL
INPUTS

15 (27):
•

:

2(3)

IN A :

:

1 (2)

L~~i~_~TT

!
.
·
·:

16(28):

~

,,

..... -------- ... -- ... -... -- ..

:

- .. -... ---',
-...-... -... -... -.... -----....-... -------

TRUTH TABLE (Each Output)
ENABLE

IN

OUT

H

H

L

H

L

H

L

X

H

H = High, L = Low, X

LAMP

:,

PINS 4, 5,12 & 13 GROUND (PACKAGE E)
PINS 5-11 & 19-25 GROUND (PACKAGE Q)
PIN #'S IN PARENTHESIS APPLY TO PACKAGE Q

=Don't Care

FIGURE 1. QUAD INVERTING POWER DRIVER (QDR) SHOWN WITH TYPICAL APPLICATION LOADS

Vee

REFERENCE
VOLTAGE
1.2 VOLTS

ENABLE
TO SUBSEQUENT STAGES

FIGURE 2. CA3262A EQUIVALENT SCHEMATIC OF ONE INPUT STAGE

2-8

Specifications CA3262A, CA3262
Absolute Maximum Ratings

Thermal Information

Logic Supply Voltage, Vcc ••••••••••.•.••••••••..•••..• 7.0V
Logic Input Voltage, VIN .••••.••.•••.•...•••..•.....••• 15V
Output Voltage, VCEX •••.••••.•••••.•••.••••••.••••.•• BOV
Output Sustaining Voltage, VCE(SUS) •••.••••••••••.••••••• 40V
Output Transient Current . • • • • • • • • • • . . • • . . . . . . . . . •• (Note 1)
Output Load Current. . • • . . • • . • • . • . . . . • . . • • . • . • . . .• (Note 2)
Storage Temperature Range •.••.•••..••••••• -65°C to + 150°C
Operating Temperature Range
CA3262AE, CA3262AO •..•..••..•.•••••.• -40oC to +125°C
CA3262E •.............•....•....•....••. -400C to +S5°C

Thermal Resistance (Note 3)
CA3262AO •••••..•..•••••••••••••.••.•••••
CA3262E, CA3262AE •••••..•••••••.••••••••
Power Dissipation, Po
CA3262E,CA3262AE
Up to +SOoC (Free Air) .....•••••••••••••••••••••••• 1.5W
Above +BOoC •••.••••••..••.• Derate Linearly at 16.6mWI"C
Up to +90oC With Heat Sink (PC Board) ••••••..••••••• 1.5W
Above +90oC;
With Heat Sink (PC Board) •...••• Derate Linearly at 25mW/oC
CA3262AO
Up to +65°C (Free Air) •.•..••••••••.••••••••••••..• 1.5W
Above +65°C ...••.•••••••••••• Derate Linearly at 23mWI"C
Up to + 105°C with Heat Sink (PC Board) ..•..•••.••..• 1.5W
Above +1050 C;
With Heat Sink (PC Board) ••••••• Derate Linearly at 33mWI"C
Maximum Junction Temperature •••••••.•••.•.••.••••• +150°C
Lead Temperature (Soldering lOs) ••••.•••••••••.••••• +265°C

I

CAUTION: Stresses abo... those listed in 'Absolute Maximum RaUngs' may cause permanent damage to the device. This Is a stress only rating and operatkJn
01 the device at these or any other conditions abo... those indicated In the operaUonaJ secUons 01 this specilicatkJn is not implied.
Wt/)

Electrical Specifications

Output Leakage Current

SYMBOL
lcex

Output Sustaining
Voltage

Vce(SUS)

Collector Emitter
Saturation Voltage
(See Figures 4B & 5B)

VCE(SAl)

TEST CONDITIONS
VCE = 60V, VENABLE = 0.8V
Note 4
VIN = 2V, Vee = 4.75V
Ic = 100rnA
Ic=200mA
Ic=300rnA
Ic=400rnA
Ic=500rnA
Ic=600rnA
Ic = 700mA, TA =-4OOC

Input Low Voltage
Input High Voltage

VIL
VIH

Input Low Current

IlL

VIN =0.8V

Input High Current

IIH

VIN = VENABLE = 5.5V,
Ic=BOOmA

Supply Current,
All Outputs ON,
(See Figures 4A and 5A)

ICC(ON)

Supply Current, All
Outputs OFF,
(See Figures 4A and 5A)

ICC(OFF)

IR

Clamp Diode Forward
Voltage,
(See Figures 40 and 50)

VF

Over Current Limiting

-

VR =60V
IF =lA, VIN = OV

MAX

-

100

4>liLo Irui lour = 500rnA
IUM

VouT =2V,
VIN = 5.5V, VENABLE = 5.5V

2-9

MIN

TYP

MAX

UNrrs

-

lIA

0.6

50

-

-

40

-

-

-

-

0.25

-

0.05

0.15

V

-

0.2

V

0.25

V

02

0.3

V

-

0.4
0.5

V
V

0.75
-

0.5

V

0.8

V

-

-

-

0.4

0.6
0.6
0.8

-

-

2

V

-

V

10
10

lIA
lIA

(Note 4)

55

rnA

-

70

-

-

-

5

-

(Note 4)

5

rnA

-

-

100

-

-

50

IIA

1.7

-

10
10

-

2.1

-

-

-

8

-

0.7

-

(Note 1)

0.7

-

IF =1.5A, VIN = OV

:=1:
0:=

40

2

VIN = 2V, VENABLE = 5.5V,
IOUTA = 250rnA, IOUTB = 250rnA,
IOUTC = 250rnA, IOUTO = 250rnA

TYP

VIN=OV

Clamp Diode Leakage
Current

Turn-On Delay,
(See Figures 4C and 5C)

MIN

t/)CJ

CA3262A

CA3262
PARAMETERS

QW
-:1:

vcc = 5.5V, TA= _40°C to +125°C for CA3262A and Vcc = 5.5V, TA= _40°C to +S5°C for CA3262
Unless Otherwise Specified

-

-

1.7

V

2.1

V

8

115

(Note 1)

A

...It/)

Specifications CA3262A, CA3262
Electrical Specifications

Vcc =5.5V. TA=_40°C to +125°C for CA3262A and Vec =5.5V. TA=-40°C to +85°C for CA3262
Unless Otherwise Specified (Continued)

CA3262
CA3262A
I
PARAMETERS
SYMBOL
TEST CONDITIONS
I MIN TYP MAX I MIN TYP I MAX IUNrrs
DESIGN PARAMETERS
Over Temperature Limiting
155
155
°C
TUM
(Junction Temperature)
Input Capacitance. Input
pF
C1N
3
Enable Capacitance
4.4
pF
CEN
NOTES:
1. The CA3262 and CA3262A have on-chip limiting for transient peak currents. Under short-cIrcuit conditions with voltage applied to the collector
of the output transistor and with the output transistor turned ON. the current will Increase to 1.2A. typical. Over-Current Limiting protects a short
circuit condition for a normal operating range of output supply voltage. During a short cllCult condition. the output driver will shortiy thereafter
(approx. 5ms) go Into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than 2A, each output will
typically withstand a direct short circun up to supply voltage levels of 16V. Excessive dissipation before thermallirniting oocurs may cause darnage to the chip for supply voltages greater than 18V, The CA3262 and CA3262A are rated to withstand peak current cold turn-on conditions
of #168 or #194 lamp loads.
2. The total DC current for the CA3262 and CA3262A with all 4 outputs ON should not exceed the total of (4 X 0.7A + Max. Icc) - 2.85A. This
level of current will slgnificantiy increase the chip temperature due to Increased dissipation and may cause thermal shutdown In high ambient
temperature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed 0.7A but may be subject
to Over-Current Limiting above the IUM min. limn of 0.7A. As a practical limit, no single output should be loaded to more than lA max.
. 3. Normal applications require a surface mount of the 28 lead PLCC package on a PC Board. The package has a power lead frame construction
where ground pins 5 - 11 and 19 - 25 conduct heat from the frame to the PC Board. wnh approximately a 2 square Inch copper erea adjacent
to the ground pins. the thermal resistance on the mounted package may be as low as 3lY'CNV.
4. Icc varies with temperature. Typically, Icc(ON) Is 18mA at +125°C and 41 mA at -40"C. Typically, ICC(OFF) is 22mA at +125°C and 12mA at -40"C.
5. Tested with a switched-off 500mA Load (240 series resistanca). VBA1T = 12V and the outputs (Vcel clamped to +40V maximum with an external zener diode.

-

-

-

-

-

-

-

-

Applications
Typical circun configurations for applying the CA3262 and
CA3262A are shown in the application circuit of Figure 1. To
their rated capabilities. both circuits can be used to drive inductive. resistive and lamp loads. The CA3262A has a lower VSAT
than the CA3262 and is rated for +125OC ambient temperature
applications. The CA3262 data sheet rating is -+&i°C. Otherwise. the protection features described apply to both the
CA3262 and CA3262A
The maximum voltage for full load current switching is the output
sustaining voltage. VCE(SUS) which should not exceed 40 Volts.
To provide a means of over-voltage protection. on-chip steering
diodes are connected from each output to one of two CLAMP
pins. Over-voltage pulses may be generated from inductive load
switching and must be clamped or limited to a peak voltage less
than VCE(SUS). To limit an inductive voltage pulse. a zener diode
should be connected to the appropriate CLAMP pin. When the
voltage pulse exceeds the zener threshold. the excess energy is
dumped to ground via the on-chip steering diode and the external zener diode.

Note that the rate of change of the output current during load
switching is fast. Therefore. even small values of inductance.
including the inductance of a few meters of hook-up wire to
the load Circuit. can generate voltage spikes of considerable
amplitude at the output terminals and may require clamping
to protect the device ratings.
Current-limiting is provided as protection for shorted or overloaded output conditions. Voltage is sampled across a small
metal resistor in the emitter of each output stage. When the
voltage exceeds a preset comparator level. drive is reduced
to the output. Current limiting is sustained unless thermal
conditions exceed the preset thermal shutdown temperature
of +155OC.

If an output is shorted. the remaining three outputs will continue to function normally unless the continued heat spreading is sufficient to raise the junction temperature at any other
output to a level greater than +155OC. High ambient temperature conditions may allow this to happen. The degree of interaction is minimized at chip layout design by separating the
The on-Chip diodes may be used in a free-wheeling mode by output devices. each to a separate corner of the chip.
connecting the CLAMP pins to an external clamp supply
voltage. Zener diode clamp protection is preferred over the As noted. the thermal resistance values of both the DIP and
power supply clamp option. primarily because the power sup- PLCC packages are improved by direct connection of the
plies may be subject to large transient changes; including turn- leads to the chip mounting pad. In free air. the junction-to-air
ON and turn-OFF conditions where non-tracking conditions thermal resistance. 9JA is +60"CIW (typical) for the DIP packbetween supplies could allow forward conduction through the age and +42!>CIW (typical) for the PLCC package. This coeffisteering diodes. For all transient conditions of either method. the cient can be lowered to +40"CIW and +31f'CIW respectively
clamp voltage should greater than the maximum supply voltage by increasing ground copper area on the PC board next to
the ground pins of the IC.
of the switching outputs and less than VCE(SUS)'

2-10

CA3262A, CA3262

la

EACH OF THE ODR OUTPUTS SHOWN IN FIG 31S A
COMPOSITE CIRCUIT WITH OVER-TEMPERATURE
SENSE FOR THERMAL UMmNG " OVER-CURRENT
SENSE TO PROVIDE CURRENT UMlnNG

FIGURE 3. QUAD INVERTING POWER DRIVER (QDR) OUTPUT EQUIVALENT CIRCUIT

Typical Performance Curves
80

~
~ 0.7

SUPPLY VOLTAGE (Vcel- 5.5V
70

-

0.6

~

0.5

z

....... r---...

"'"
I

10

~

VIN - 2V,IoUT :J50mA (EACH)

..........

K

I

I

~

I:

~

I

0
20
40
60
80 100
AMBIENT TEMPERATURE ( °C)

~

:

120

0.3

f.-""

IC· 600mA -

~U

"-

~

,
-20

. ...- /',..
........

- -

IC- 7oomA

(I)

VIN - OV,IoUT- OmA

o

r

~0.4

15

THERMAL SHUTDOWN

-40

:!i
~

SUPPLY VOLTAGE (vccl- 4.7SV

140

FIGURE 4A. TYPICAL SUPPLY CURRENT (PIN 11)
CHARACTERISTICS

0.1

-40

o

20 40 60
80 100
AMBIENT TEMPERATURE ( °C)

-20

120 140

FIGURE 4B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUADGATED INVERTING POWER DRIVER OUTPUT

4

VIN
:t50%
8,10,15,16
(16)(17) (27)(28)
tPliL - VOUT _ _ _ _-,/

-

-

IF-1.5A

I

1,3,6,8
(2) (4) (12) (14)

I
IF-1A

tpLH

o
-40

-20

0

20
40
60
80 100 120
AMBIENT TEMPERATURE (GC)

-40

FIGURE 4C. TYPICAL PROPAGATION DELAY
TIME CHARACTERISTICS

-20

0

20
40
60
80 100 120
AMBIENT TEMPERATURE (GC)

140

FIGURE 4D. TYPICAL CLAMP-DIODE FORWARD
VOLTAGE CHARACTERISTICS

FIGURE 4. TYPICAL CHARACTERISTICS OF THE CA3262E

2-11

CA3262A, CA3262
Typical Performance Curves (Continued)
80
SUPPLY VOLTAGE (Vee)- 4.75
0.7 _ loUT" 600mA

SUPPLY VOLTAGE (Vee)" S.5V
70
a:~

C 60

.s

l-

Z

so

W

a:
a: 40

:::>
(.)

~ 30

Q.
Q.

:::> 20
()

0

11

··
- -_ ............ -_ .......... -..........................
- .·.
.,.................
-~

CAUTION: These devices are sensHive to electrostatic discharge. Users should 101l0w proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994.

2-13

File Number

2223.4

wen
QW
-x:

en"
~I::

O~
.....
en

CA3272, CA3272A, CA3292A
Block Diagram of the CA3272, CA3272A
18

26

ENABLE

1

--0

Vee

:--·,.· .....· .... --.... ---.. --------"".-..1;-..:
~---+'~
:
OUTD:

1.

·•••
.··:•
OUTC:
····•••••
.
.·•
·
···•:
·
•

IND

-

·

L..,;;;;;"r--tJ 0.020

, .... -_ ................ - - ..................................... f

~

12

17

INC

!

•

·

1I.,,;=.r--u 0.020

:

-_ .................. -_ ...................................... _,
2
~---1~~~D

OUlA

•

-

f ...... _ .. _ ...... _ .. _ .. _____ ._ .. ____ • _ .. __ .... .1

·
:

4

INB

!

-

·

........1"""""""1....1

0.020

.·
·
···
··.

··•
··•
•
:

•
•

:

1I.,,;;;;;;..r--u 0.020

OUTB:

27

:

:

:

·

... __ ...... -_ .. --- --.----- ..~--- .. "" .... --!

, ........ _- - - ...... - ... - . - - . - .. _ .......... - - - - - f

:

2

:

OUTA!

28

INA

·

-

NOTE:
THE CA3292A IS EQUIVALENT TO THE
CA3272 AND CA3272A EXCEPT FOR THE
COLLECTOR·TO·BASE ZENER
DIODE ON EACH OUTPUT (Z,J.
USED AS AN OVER·VOLTAGE CLAMP TO
PROTECT THE OUTPUT WHEN SWITCHING
INDUCTIVE LOADS

f __________________ .. ________ .. ____ ~

1

~

GROUND PINS
5·11.18·25

TRUTH TABLE

INPUT
27

1

ENABLE
28

1

ENABLE

IN

H

H

L

H

L

H

L

X

H

OUT

H =High, L =Low, X =Don't Care
TO PRE DRIVER
AND
OUTPUT STAGES

FAULT LOGIC TABLE
IN

NOTE:
1. INPUT AND ENABLE PULLDOINN SOURCES FORCE
OUTPUT TURN·OFF FOR UNTERMINATED INPUTS
FIGURE 1. SCHEMATIC OF ONE INPUT STAGE

2·14

OUT

FAULT

MODE

H

L

H

Normal

H

H

L

L

L

L

Over Current, Over Temperature
Open Load or Short to Power Supply

L

H

H

Normal

Specifications CA3272, CA3272A, CA3292A
Absolute Maximum Ratings

Thermal Information

output Voltage. Vo (CA3272. CA3272A) ••••••••••••••••• +SOV
Output Sustaining Voltage. VCE(SUS) (CA3272. CA3272A) ••••• 40V
Output Voltage. Vo (CA3292A) ••••••••••••••••••••••• VCLAMP
Output Clamp Energy. EOK (CA3292A) •••••••••••••••• TBDmJ
Output li"ansient Current, (Note 1) • • • • • • • • • • • • • • • • •• 1.6A Max.
Output Load Current, (Note 2) •••••••••••••••••••••••••• 0.7A
Supply Voltage. Vee .••••••••••••••••••••••••••••••••• +7V
Logic Input Voltage. VIN •.••••••••••••••••••••••••••••• 15V
FAULT Output Voltage. VF .•••••••••••••••••••••••••••• 16V
Operating Temperature Range •••••••••••••••• -4OOC to +125°C
Junction Temperature •••••••••••••••••••••••••••••• +lSOOC

Thermal Resistance .••••.••••••••••.•••••••••••••
8JA
PLCC ••••••••••••••••••••••••••••••••••••
45°CIW
PLCC (With PC Board Heat Sink) ••••••••••••••
3O"CIW
Power Dissipation (No Heat Sink)
Up to +85°C ••••••••••••••••••••.•••••••••••••••• 1.5W
Above +85°C •••••••••••••••••• Derate linearly at 23mWI"C
Power Dissipation: (WIth PC Board Heat Sink. Note 3)
Up to +85°C •••••••••••••.••••••.•••••••••••••••• 22.W
Above +85°C ••••••••••••.••••• Derate Unearly at 33mWI"C
Storage Temperature Range ••••••••••••••••.• -6500 to +1 SOOC
Lead Temperature (Soldering lOs) •••••.•••••••••••••• +265°C

CAUTION: SlressliS above thoss listed In 'Absolute Maximum Ratings' may cause permanent damage to the davies. This Is a stress only /Bting and opIJ/B/Jon
01 the device at thess Of any other conditions above those Indicated in the ops/B/Jonsl sections 01 this spsci/ica/Jon Is not Implied.

Electrical Specifications

TA = -400 C to +1250 C. vee = 5.5V. Unless Otherwise Specified
CA3272A. CA3292A

CA3272
PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ICEX

VIN = 0.8V; VEN = 5.5V; (Note 4)
Vee = 60V br CA3272. CA3272A;
Vee = 24V for CA3292A

·

30

100

·

30

100

j1A

40

·

·

40

·

.

V

·

·

·

28

32

36

V

Ic = 400rnA. T" = +12SOC

·

·

0.4

·

·

0.3

V

Ic = SOOrnA. TA = +2500

·

·

0.5

·

·

0.4

V

Ic = 6OOrnA. TA = -4ooC

·

·

·

·

·

0.5

V

Ic = SOOmA, TA = -4ooC

-

-

0.6

-

-

-

V

Vee =3.5V

-

0.8

-

0.8

V

OUTPUT PARAMETERS
Output (OFF) Current

Output Sustaining Voltage:
CA3272. CA3272A

VCE(SUS)

Note 7

Output Clamp Voltage:
CA3292A

VClAMP

Ic = 300j1A; VEN = 0.8V

Coliector·to·Emltter
Saturation Voltage

VCE(SAT)

VIN = 2V. Vee = 4.75V.

LOGIC INPUT THRESHOLDS
Input Low Voltage

VIL

Input High Voltage

V1H

2

-

-

2

-

-

V

Input Low Current

IlL

VIN = VEN = 0.8V; Vcc = 4.75V

10

45

70

10

45

70

j1A

Input High Current

IIH

VIN = VEN = 5.5V

10

45

70

10

45

70

j1A

VIN = VEN = 5.5V; IourA = IOUTB

-

-

65

-

-

65

rnA

VIN=OV

-

·

10

-

-

10

rnA

IpHL

ILOAD = SOOrnA

10

10

lIS

3

10

-

3

IpLH

-

3

ILOAD = 500rnA

3

10

lIS

Output Low Current.
IF(SINK) (with Fault)

IOL

VIN = 0.8V; VEN = 2.0V; VF = 4V
VOUT = Low = 1V; (Note 5)

0.04

0.09

0.12

1

2

4

rnA

Output High Current. IF(lK)

IOH

No Fau~ (Note 5)

-

-

2

-

-

20

j1A

SUPPLY CURRENT
All Outputs ON

ICC(ON)

= IOUTC = !aUTO = 400rnA
All Outputs OFF

ICC(OFF)

PROPAGATION DELAY
Turn-ON Delay
Turn-OFF Delay
FAULT PARAMETERS

2-15

Specifications CA3272, CA3272A, CA3292A
Electrical Specifications TA = -4O"C to +125°C, vcc = 5.5V, Unless Otherwise Specified (Continued)
CA3272A, CA3292A

CA3272
PARAMETERS

SYMBOL

Outpu1 Low Voltage

VOL

TEST CONDITIONS
External Load Equal Min. 10l

=0.8V; VEN =2V (Note 6)

Output Driver Fault Sense,
High Threshold (Open)

VHTHD

VIN

Output Driver Fault Sense,
Low Threshold (Short)

VlTHD

VIN =VEN

=2V (Note 6)

MtN

TYP

MAX

MIN

TYP

MAX

UNITS

-

0.2

0.4

-

0.2

0.4

V

3

4

5.5

3

4

5.5

V

3

4

5.5

3

4

5.5

V

0.6

-

Note 1

0.6

-

Note 1

A

PROTECnON PARAMETERS
VIN =VEN =2V, VOUT =40 to
16V

Over-Current Limiting

IUM

Over-Temperature
Limiting
(Junction Temperature)

TUM

-

165

-

-

165

-

OC

Over-Temperature
Limiting, Hysteresis

THyS

-

15

-

-

15

-

4°C

Input Capacitance

CIN

3

-

-

pF

CEN

-

3

Enable Capacitance

-

DESIGN PARAMETERS

4.6

4.6

pF

NOTES:
1. Ou1put Transient Currents are controlled by on-chlp limiting for each output Under short-circuit conditions with voltage applied 10 the
collector of the OUtpu1 transistor and with the ou1put transistor turned ON, the current will Increase to 1.2A, typical. Over-Current limIting protects a short circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output
driver will shortly thereafter (approx. 5ms) go into Over-Temperature Shutdown. While Over-Current Limiting may range to peak currents as high as 1.6A, each outpu1 will typically withstand a direct short circuit at normal single battery supply levels. Excessive dissipation before thermal shutdown occurs may cause damage to the chip for supply voltages greater than 16V. When sequentially
switched, the outputs are rated to withstand peak current, cold turn-on conditions of lamp loads such as #168 or #194 lamps.
2. The total DC current with all 4 ou1puts ON should not exceed the total of (4 X 0.7A + Max. IcC>- 2.85A This level of current will significantly
increase the chip temperature due to increased dissipation and may cause thermal shu1down in high ambient temperature conditions (See
Absolute Maximum Ratings for Dissipation). Anyone outpu1 may be allowed to exceed 0.7A but may be subject 10 Over-Current Limiting
above the IUM minimum limit of 0.7A. No single output should be loaded to more than Over-Current Limiting above the IUM minimum limit
ofO.7A. As a practical limit, no single outpu1 should be loaded to more than lA maximum.
3. Normal applications require a surtace mount of the 28 lead PLCC package on a PC Board. The package has a power lead frame construction where ground pins 5 - 11 and 19 - 25 conduct heat from the frame to the PC Board. With approximately a 2 square inch copper area
adjacent to the ground pins, the thermal resistance on the mounted package may be as low as 3OOCNi.
4. ICEX Is the static leakage current at each output when that output Is OFF (ENABLE Low). Refer to the Figure 3 illustration of an output
stage. The value of IcEX Is both the leakage into the output driver and a pull-down current sink, IO(SINK). The purpose of the current sink
is 10 detect open load conditions.
5. The IOl value of "Output Low Current, IF(SINK)" at the FAULT pin is both the static leakage of the ou1put driver QF and the current sink,
IF(SINK)· The current sink is active only when a fault exists. When no fault exists, the IOH current at the FAULT pin Is the maximum leakage
current, IF(lK). Refer to Figure 2 for an illustration of the FAULT ou1put and associated external components. Refer to FAULT LOGIC TABLE
for Fault Modes.
6. The Voltages, VHTHD, VlTHD are the comparator threshold reference values (Min. & Max. Range) sensed as a high and low state transitions for voltage forced at the outputs. VHTHD Indicates an open load fault when the output is decreased to less than the threshold.
VlTHD Indicates a shorted load when the Ou1put is Increased greater than the threshold. The output voltage is changed until the FAU LT
pin indicates a Low (Fault). Refer to Figure 2 for test value of external resistor. Refer to 10l and IOH FAULT PARAMETERS Test Limits
to determine VOL and VOH at the FAULT pin.
7. Tested with 120mA switched off In a Load of 70mH and 320 series reslsJence;
CA3272, CA3272A: Outputs clamped with an external zener diode, limiting VOUT to the VCE(SUS) maximum rating of +4OV.
CA3292A: Ou1puts limited to the VCLAMP voltage by the Internal collector-to-base zener diode and output transistor clamp.

2-16

CA3272, CA3272A, CA3292A

Applications
The CA3272, CA3272A and CA3292A are quad-gated inverting low-side power drivers with a fauR diagnostic flag output.
Both circuits are rated for +12SoC ambient temperature applications and have current limiting and thermal shutdown. While
functionally similar to the CA3262AO, they differ in the mode
of over-voRage protection and have the added feature of a
FAULT flag output. Also, inputs to channels A, B, C, D and
ENABLE have internal pulldowns to turn ·OFP' the outputs
when the inputs are floating.
As noted in the Block Diagrams, the CA3292A is equivalent to
the CA3272 and CA3272A except that it has internal clamp
diodes on the outputs to handle inductive switching pulses
from the output load. The structure of each CA3292A output
includes a zener diode from collector-ta-base of the output
transistor. This is a different form of protection from other quad
drivers with current steering clamp diodes on each output,
paired to one of two ·CLAMP" output pins. The CA3292A output transistor will turn-on at the zener diode clamp voRage
threshold which is typically 32V and the output transistor will
dump the pulse energy through the output driver to ground.

Block Diagram illustrates the logic functions associated with
Fault detection. The diagnostic output for each of the four
channels of switching is processed through the fault logic circuit associated with each channel. It is then passed to an OR
gate which controls the FAULT flag output transistor, OF thru a
2 input AND gate.
The ENABLE input is common to each of the 4 power switches
and also disables the FAULT flag output at the 2 input AND gate
when it is low. The FauR Logic circuit senses the IN and OUT
states and switches OF ·ON" if a fauR is detected. Transistor OF
activates a sink current source to pull-down the FAULT pin to a
(low) state when the fault is detected. Both shorted and open
load conditions are detected.

o

It is normal for thermal shutdown and current limiting to
occur sequentially during a short circuit fault condition. A
precaution applies for potential damage from high transient
dissipation during thermal shutdown. (See Note 1 following
the Electrical Characteristics Table).
FAULT SENSE

FAULT

FAULT FLAG
DIAGNOSTIC

~~~~ 3V

Turn-On Delay

~L

10 = 500mA, No Reactive Load

Turn-Off Delay

tpLH

10 = 500rnA, No Reactive Load

Fault Reference Voltage
Fault Reset Delay (After CE Low
to High Transition)
Output OFF Voltage

VOREF
iuD
VOFF

-

-

1.05

1.5

-

A

-

1

10

I1S

-

2

10

I1S
V

Output Programmed ON, Fault Detected
IfVO>VOREF

1.6

1.8

2.0

See Figure 1

50

80

250

I1S

-

0

1

V

Output Programmed OFF, Output Pin
Floating

LOGIC INPUTS (MOSI, CE, SCK and RESET)
Threshold Voltage at Falling
Edge

VT.

Voo = 5V ± 10010

0.2VOD

0.3Voo

-

V

Threshold Voltage at Rising
Edge

VT•

Voo=5V± 10%

-

0.6Voo

0.7VOD

V

Hysteresis Voltage

VH

VT.- VT•

0.85

1.4

2.25

V

-10

-

+10

JlA

20

pF

Input Current

II

VDD = 5.5V, 0 < VI < VOD

Input Capacitance

CI

O

~~

5~

Ow

3=1::
03=

....•.....

.Jrn

~

............. """
-.... -"

~

1.5

-"

-'0:
-'0:

e(:o
z-,
we( 1.0

OW
-x
rn(,)

-"

":0

MAX. ALL ON
CURRENT UMIT
(EaUAL CURRENT)

0::0

O:a

:Ow

Ox
w~

if!.
0

--4--(3)
--+-(4)

0.5

~

::Il

=

CURVE (3): ROS(ON) 1a
CURVE (4): ROS(ON) O.SQ
THERMAL RESISTANCE, 9JC = 30 CNi

=

0.0
50

75

100

125

150

CASE (HEAT SINK TAB) TEMPERATURE (OC)
FIGURE

5. HIPOOB1 CURRENT vs CASE (TAB) TEMPERATURE, ALL OUTPUTS ON WITH EQUAL CURRENT

16

HIP0081 WITH EXT.
6°CIW HEAT SINK
(9JA = gOCIW)

14

/'

2

-so

-25

o

25
50
AMBIENT TEMPERATURE ("C)

75

FIGURE 6. DISSIPATION DERATING CURVES

2-35

100

125

150

HIP0082
Quad Power Driver with
Serial Diagnostic Interface

PRELIMINARY
April 1994

Features

Description

• Low Side Power MOSFET Output Drivers
- Output Voltage Rating •••••••••••••••••••••• 7SV
- Maximum Output Current Switching ••••••••••• 2A
- Max. Output RDSON {TJ = +1S00C) •••••• 0.S7010.620

The HIP0082 Quad Power Driver contains four individually
protected NDMOS transistor switches to drive inductive and
resistive loads such as: fuel injectors. relays. solenoids. etc.
The outputs are low-side switches driven by active·low
CMOS logic inputs. Each output is protected against excessive current due to a short·circuit. Internal drain-to·gate
zener diodes provide output clamping for over·voltage. An
integrated charge pump allows operation from a single 5V
logic supply. Diagnostic circuits provide ground short (SG).
supply short (SC) and open load (Ol) detection for each of
the four output stages and indicate over-temperature. Diagnostic information may be read via a synchronous serial
interface. Six bits 01 write/store data controls the Ol fault
delay time or sets Outputs 3 and 4 to the 2A or 5A mode.

• Programmable Output Current Limiting
- Bit Select 2A or SA on Outputs 3 and 4
• Output Protection
- Output Over-Current Shutdown
- Output Over-Voltage Clamp
- Over-Temperature Diagnostic Feedback
• Diagnostics for Shorts, Opens and Over-Temperature
• Synchronous Serial Interface with
- 22-Blt Serial Diagnostic Register
- SPI Compatible Interface

• Low Icc Supply Current with Full Load •••••••• 10mA

The HIP0082 is fabricated in a Power SiMOS IC process and
is intended lor use in automotive and other applications with
a wide range of temperature and electrical stress. It is particularly suited for driving high-current inductive loads requiring
high breakdown voltage and high output current.

• Low 9JC Power SIP Package •••••.••••••.••• •3°CIW
• -40oC to +12SoC Operating Temperature

The HIP0082 is supplied in a 15 Lead Power SIP package
with lead form options for either vertical or surface mount.

Applications

Ordering Information

• Single SV Supply Operation with CMOS logic Inputs

• Drivers For
- Solenoids
- Relays
- Power Output
- Lamps

-

• System Use
- Automotive
- Appliances
- Industrial
- Robotics

Injectors
Steppers
Motors
Displays

Pinout

PART NUMBER

TEMPERATURE
RANGE

PACKAGE AND
LEAD FORM

HIPOO82AS1

-4Q°C to +125°C

15 lead Plastic SIP
Staggered Vertical Mount

HIPOO82AS2

-400 C to +125°C

15 Lead Plastic SIP
Surface Mount

Block Diagram
HlPO082 (SIP)
TOP VIEW

HEAT SINK TAB INTERNAllY CONNECTED
TO PIN 8 GROUND (vssl

:OUTx

I
o

o

TXD
ClK

CAUTION: These d9\lices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporetion 1994

2·36

File Number

3643

Specifications HIP0082
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Logic and Control), Vcc •..••..•.•.. -0.3V to 7V
Power MOSFET Drain Voltage, Vo (Note 1) .•....•• -0.7 to VClAMP
Output Clamp Energy, EoK •.••.....•••.•........•..• TBDmJ
Input Voltage (Logic and Driver Inputs), VIN •... -0.5V to Vcc +0.5V
Maximum Output Current, Outputs 1 and 2 ........••...... +2A
Maximum Output Current, Outputs 3 and 4 ....•.••••...••• +5A
Maximum Total Output Current, All Outputs ON ••••......... +8A
Maximum Peak Output Current, 10(MAX)' (Note 2) .••.•.. -SA to Isc
Operating Ambient Temperature Range ....••... -4lliOo-------;~~

_ _ _ _-:

tCLKL

Output Short-ta-Ground Detection
When the voltage on an output pin is below VSG and the output is off, a ground short is detected and stored in the diagnostic register after a delay tSG' The outputs of the short-toground (SG) comparators are also connected directly to the
diagnostic register so that they can be monitored via the
serial interface.

tCSHOZ

--.!,'
_m

__- - .

:,,

:
, -

HIP0082
TMP Bit - Indicates that the chip temperature has exceeded
the limit TTMP. The outputs are not switched off when this
occurs; the condition is indicated by the setting of the TMP
bit. Sensors for the TMP bit are located near the power drivers and are OR'd to provide a single bit for the chip.
SCx Bits - Indicate a short-circuit to battery or over-current
on the corresponding output.
OLx Bits - Indicate that no load (or a high resistance load) is
connected to the corresponding output.
SGx Bits - Indicate that the voltage on the corresponding
output is below the VSG limit.
The final 8 bits (most significant bits) of the diagnostic word
indicate the states of the open-load and Short-to-ground
comparators when the CS pin went from high to low. Using
this feature, an external microprocessor can monitor the status of the OL and SG comparators directly.
Diagnostic Write Operation
When the RiW pin is in the low state it is possible to write six
bits to the IC to influence its mode of operation. The write
operation is illustrated in Figure 3. The programmable bits
are as follows:
Test Bit - Used to put the IC in test mode (not recommended). This bit should be low for normal operation.
ISC Bit - This bit programs the short-circuit level for outputs
3 and 4. When this bit is set high the lower value for the current shutdown threshold is set.
Td_OLx Bits - These bits set the delay times for the openload measurements individually for each of the four outputs.
A logical high sets the open-load delay time to its shorter
value.

Pin Descriptions

vee

and GND • 5V Supply and Ground connections. A
charge pump is used to boost the Power MOSFET gate
drive. This allows a single 5V supply to satisfy all logic and
drive requirements.
OUT1 - OUT4 - Low-side output drivers with 0.620 (OUT1
and OUT2) or 0.570 (OUT3 and OUT4) on resistance. The
outputs are provided with over-current shutdown and overvoltage clamping. Additionally open-load and short-toground detection is carried out when the outputs are ON.
IN1 - iiii4 - Active-low CMOS logic inputs which control the
output stages OUT1 - OUT4. These inputs are provided with
pull-up resistors.

RS'i' - Active-low logic-level reset input with internal pull-up
resistor. When RS'f is in the low state all outputs are off and
all registers and counters are reset. When the reset pin is
taken high the IC remains in reset mode for a time tRST.
CLK - Clock input for synchronous serial interface with internal pull-up resistor. This input must be high when CS transitions from high to low.

es - Active-low chip select input for serial interface. This
input has an internal pull-up resistor.
R/Vi - Read/write control pin for serial interface. This input
controls whether the TXD pin is an input or output.
TXD - Bidirectional data pin for serial interface. When RiW is
high diagnostic data can be read from HIP0082. When RiW
is low, 6 bits may be written to the internal program register.

ClK

TXD

ZZ .. HIGH IMPEDANCE

DIRECT COMPA~TOR OUTPUTS
FIGURE 2. SERIAL INTERFACE READ OPERATION

ClK

_I=~~;-~~~~~r~~~

__~~__~~__~r
zzzz

TXD

ZZ .. HIGH IMPEDANCE
FIGURE 3. SERIAL INTERFACE WRITE OPERATION

2-40

INTELLIGEN

-

POWERICs

3

HIGH SIDE SWITCHES

PAGE
HIGH SIDE SWITCHES SELECTION GUIDE ................................................... .

3-2

HIGH SIDE SWITCHES DATA SHEETS

CA3273

High-Side Driver ....................................................... .

3-3

HIP1030

1A High Side Driver with Overload Protection ................................ .

3-6

HIP1031

Half Amp High Side Driver with Overload Protection ........................... .

3-10

HIP1090

Protected High Side Power Switch with Transient Suppression ................... .

3-13

HV400

High Current MOSFET Driver •.............................................

3-18

HV400MJ/883

High Current MOSFET Driver ............................................. .

3-28

ICL7667

Dual Power MOSFET Driver .............................................. .

3-38

3-1

wen
-J:
en(,)

OW

~t:::

-3:
J:en

High Side Switches Selection Guide
TYPE

FUNCTION

MAX
SUPPLY

DC SUPPLY
RANGE

PEAK MAX
CURRENT

DC MAX
CURRENT

PACKAGE

RECOMMENDED
APPLICATIONS

PROTECTED POWER SWITCHES
CA3273

Single
Power

40V

4V10 24V

1.2A

O.6A

3 Lead Mod.
TO-202

Solenoid, Relay,
Lamp and Molar

HIP1030

Single
Power

35V

4.5V10 25V

2.5A

1.lA

5 Lead
TS·OO1AA

Solenoid, Relay,
Lamp and Molar

HIP103l

Single
Power

35V

4.5V10 25V

1.7A

O.7A

5 Lead
TS·OO1AA

Solenoid, Relay,
Lamp and Molor

HIP1090

Single
Power

±90V,
l5ms

4Vlo l6V

2A

lA

3 Lead
TO-220

Solenoid, Relay,
Lamp and Molor

TYPE

FUNCTION

MAX
SUPPLY

DC
SUPPLY
RANGE

PEAK MAX
CURRENT

MAX
FREQUENCY

PACKAGE

RECOMMENDED
APPLICATIONS

MOSFET DRIVERS
HV400

Single
High Speed

35VDC

l5V 10 30V

6A (Source)
30ASink
(Pulsed)

20kHz (MC)
200kHz
(SMPS)

8 Lead PDIP
andSOIC

SMPS,
FET Drivers., and
Molar Conlrollers

ICL7667

Dual Power

l5V

4.5V 10 l5V

1.5A (Pulsed
Gale)

200kHz

8 Lead
TO-99,PDIP,
CerDIP, and
SOIC

SMPS,
FET Drivers, and
Molar Controllers

3-2

CA3273

HARRIS
S EM I CO N D U C TO R

High-Side Driver

April 1994

Features

Description

• Equivalent High Pass P-N-P Transistor

The CA3273 is a power IC equivalent of a P-N-P pass transistor operated as a high-side-driver current switch in either
the saturated (ON) or cutoff (OFF) modes. The CA3273
incorporates circuitry to protect the pass currents, excessive
input voltage, and thermal overstress. The high-side driver is
intended for general purpose, automotive and potentially
high-stress applications. If high-stress conditions exist, the
use of an external zener diode of 35V or less between supply and load terminals may be required to prevent damage
due to severe conditions (such as load dump, reverse battery and positive or negative transients). The CA3273 is
designed to withstand a nominal reverse-battery
(VBAT = 13V) condition without permanent damage to the
IC. The CA3273 is supplied in a modified 3-lead TO-202
plastic power package.

• Current Limiting •••••••••••••••••••••• O.SA to 1.2A
• Over-Voltage Shutdown ••••••••••••••• +25V to +40V
• Junction Temperature Thermal Limit ••••••••• +150 oC
• Equivalent Beta of 25•••••••••••••••••• 400mAlO.5V
• Internal Bandgap Voltage and Current Reference

Applications
• Fuel Pump Driver
• Relay Driver
• Solenoid Driver
• Stepper Motor Driver

Ordering Information

• Remote Power Switch

TEMPERATURE
RANGE

PART
NUMBER

• Logic Control Switch

-4O"C to +85°C

CA3273

Pinout

TO-202 Modified SIP

Block Diagram

en :

:. __ ._--------_ .... _-----_._--------.

CA3273 (SIP)

TOP VIEW

:====:

PACKAGE

vee

(3)Vo(LOAD)

PIN 1

(2) Vsw (CONTROL)

~:====. (1) vee (SUPPLY)

:

·
···: I
Icc

··: I

Rs

OUTPUT PASS
TRANSISTOR

I ¥ I

DRIVE AND UMlTlNG
CONTROL

[9_~~2JL

_____________
PIN2
Vsw

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

3-3

10

Vo
PIN 3

I

RL
LOAD

-=-=

t---------!

I

CONTROL
INPUT

File Number

2113.4

Specifications CA3273
Absolute Maximum Ratings

Thermal Information

Fault Max, Supply Voltage, Vee •.....•........•..•.•.••• 40V
Maximum Operating Vee:
At 10=400mA (-40"C to +85°C Ambient) ••••.•••••••••• l6V
At 10=60OmA (-40"C to +250 C Ambient) ••••..••••••••• 24V
Max. Positive Output Peak Pulse, Vsw Open •••..••••. Vcc+12V
Max. Operating Output load Current ••.••••••.••••••.. 600mA
Short Circuit load Current, Ise •.•••...••••.... Internal limiting
Reverse Battery • . • . • . . . . . . • . . • • • . . . • • . • . • . • • • • • • • •• -13V

Thermal Resistance
OJA
Plastic SIP Package •.•.......•...........•..... +700 C/W
Maximum Power Dissipation, Po
At +25°C Ambient, TA (Note 1) •••••••••••••....••••.. 1.8W
Derate above +25°C (No Heat Sink) ••••.•.•••••• 14.3mWI"C
Maximum Junction Temperature, TJ (Note 2) •.•••••.••••• 150°C
Ambient Operating Temperature Range •••.•••••• -4O"C to +85°C
Storage Temperature Range •••••.•.•••••••.•. -400 C to +150°C
lead Temperature (Soldering lOs max) .......•........ +265°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and oparation
of the device st these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

TA = -40°C to +850 C, Unless Otherwise Noted, See Block Diagram for Test Pin Reference

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

24

V

0.5

V

Operating Voltage Range

Vee

Vee Reference to Vsw

4

Saturation Voltage(Vcc - Vol

VSAT

10 = -400mA, Vsw = OV, Vee = 16V

-

Operating load

RL

Vsw = OV (Switeh ON)
TA = +85°C, Vee = 16V
TA =

Over-Voltage Shutdown Threshold
Over-Current limiting

+250 C,Vee

= 24V

25

33

40

V

10(UM)

Vee =16V,Vsw = IV (SWitch ON)

-

-

1.2

A

150

-

°C

-

-15

-

mA

-

-22

mA

-33

mA

Vee = 24V

-50
-50

-

-

rnA

Vee = 7V

Vee = 24V,Vsw = 23V

-200

-

+50

IIA

Vee = 7V, Vsw = 6V

-200

+50

IIA

Vsw =16V

-100

+100

IIA

Vsw =15V

-100

+100

IIA

TUM
Isw

Vee =16V, Vsw = OV
10=OmA
10 =-400mA

Control Current, Max. load,
Switch ON

Output Current leakage

0

Vsw = OV,R L = 1kQ,Increase Vee.
(Vo goes low)

Over-Temperature limiting

Min. Control Current, No Load,
SwitehOFF

40

Vee(THO)

Control Current, Switch ON

Max. Control Current,High and
low Vee

0

40

Vee = 24V,Vsw = OV,lo = -600mA
ISW(MAX)

ISW(NL)

IO(LEAK)

RL = 400, Vsw =1V

rnA

Va = Open,(Switeh OFF)

Va = OV, Vee = 16V, (Switch OFF)

-

NOTES:

1. The calculation for dissipation and junction temperature rise due to dissipation is: Po = (Vee - Vo)x 10 + Vee x Isw and
TJ = TA + Po x OJA where TJ is device Junction temperature, TA is ambient temperature and OJA is the junctlon-to-amblent
thermal resistance.
2. Therrnallimiting occurs at +150°C on the chip.

3-4

CA3273

,,r--'" -- --, .. --;- -_ ... --- -- ........ ---, --- .. -- ............... --... -_ ...... -- ......................... -- ................................. ..
:,,
,,
,,
,,
,,
,,,
,,
,
:,,
~-----r--*-----1---*-~ o~~~lg~~~E
,,
CONTROL CIRCUIT
,,,
~- ... ---- .. ..
............. -.. "' . .... .. -. --- . -....... ----- .... ----- .................... ---_ .... _-

Vee
INPUT

-- ----

Vo
OUTPUT

-- --

Vsw
CONTROL INPUT

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF CA3273

Vee

Vee

+4 TO+24V
(SUPPLY INPUT)

1Kn

-=-

OFF

OFF

2N5320
OR EQUIVALENT

FIGURE 2. TYPICAL APPLICATION WITH ZENER DIODE FOR
OVER-VOLTAGE PROTECTION WITH INDUCTIVE
LOAD SWITCHING. Vz SHOULD BE LESS THAN
35V. WHEN CURRENT IS SWITCHED OFF IN THE
OUTPUT LOAD (L), THE INDUCTIVE KICK PULSE
GOES NEGATIVE. THE CLAMPED CLAMP LEVEL
OF THE NEGATIVE GOING PULSE IS Vcc - VZ.

>-----~~r-----~~

-

"- ~

>-______-l(V"N)

"
o

25
50
75
TEMPERATURE (OC)

100

125

SOLENOID

....yC>J

>-______-l(V"N)

o
-25

2N5320
OR EQUIVALENT

RESISTIVE

DERATING 700 CIW

IVITH~UT HEAT SINK)

K

-=-

FIGURE 3. OPTIONAL RANGE SHIFTII'JG OF THE Vee INPUT
VOLTAGE USING A ZENER DIODE TO OFFSET
THE Vsw CONTROL PIN. (I.E.,THE OVER-VOLTAGE SHUTDOWN THRESHOLD WILL BE INCREASED TO VCC(THD) + Vz AND THE MINIMUM
Vcc OPERATING VOLTAGE IS Vz + 4V).

2

-50

Vz

ONITONTROL
INPUT o---v.rv-of:

ONITONTROL
INPUTo-WH!:::

RELAY

150

FIGURE 4. DISSIPATION DERATING CURVES

FIGURE 5. TYPICAL LOADS

3-5

HIP 1030

HARRIS
SEMICONDUCTOR

1A High Side Driver with
Overload Protection

PRELIMINARY
April 1994

Features

Description

• Over Operating Temperature Range
- 1V Max VSAT at 1A
- 1A Current Switching Capability
- 4.SV to 2SV Power Supply Range

-400 C

to +12SoC

• Over-Voltage Shutdown Protected
• Over-Current Limiting

The Functional Block Diagram for the HIP1030 shows the
protection control circuit functions of over-current, overvoltage
and over-temperature. A small metal resistor senses overcurrent in the power supply path of the pass transistor and
load. Overvoltage detection and shutdown of the output driver
occurs when a comparator determines that the supply voltage
has exceeded a comparator reference level. Overtemperature is sensed from a VSE differential sense element
that is thermally close to the output drive transistor. In addition
to the input detected overvoltage protection, negative peak
voltage of a switched inductive load is clamped with an internal zener diode. An internal bandgap voltage source provides
a stable voltage reference over the operating temperature
range, providing bias and reference control for the protection
circuits.

• Thermal Umlting Protection
• 60Vp K Load Dump
• Reverse Battery Protection to -16V

Applications
• Motor Driver/Controller
• Driver for Solenoids, Relays and Lamps
• MOSFET and IGBT Driver
• Driver for Temperature Controller

Ordering Information
PART
NUMBER
HIP1030AS

TEMPERATURE
RANGE

PACKAGE

-40°C to +125°C

5 Lead TS·001AA SIP

Pinout

The HIP1030 is a High Side Driver Power Integrated Circuit
designed to switch power supply voltage to an output load. It
is the equivalent of a PNP pass transistor operated as a
protected high side current switch in the saturated ON state
with low forward voltage drop at the maximum rated current.
The HIP1030 has low output leakage and low idle current in
the OFF state.

The HIP1030 is particularly well suited for driving lamps,
relays, and solenoids in automotive and industrial control
applications where voltage and current overload protection
at high temperatures is required. The HIP1030 is supplied in
a 5 lead TS-001AA Power SIP package.

Functional Block Diagram
HIP1030 (SIP)
TOP VIEW

1 : ~~g:ONTROL)
3TASGND
2 VOUT (LOAD)
1 Vee (SUPPLy)

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

3-6

GND

File Number

2788.5

Specifications HIP1030
Absolute Maximum Ratings

Thermal Information

Max. Supply Voltage Vcc ........ See O.V. Shutdown Limit, Vovso
Input Voltage, VIN (Note 1) ......•.••••...•..-w to (Vcc - 0.5V)
Load Current, lOUT' ........••....•..••••.... Internal Limiting
Load Dump (Survival) •........•.••...••.••.•.••••. ±60VPK
Reverse Battery . . . . . . . • . . . . . . . . . . . . . • • . . • . • • . . • . • .• -16V

Thermal Resistance
9JA
9JC
Plastic SIP Package ..••.......... " 500 CIW
4°CIW
Maximum Power Dissipation (Note 2)
At TA = +125°C, Infinite Heat Sink •••..••....••....... 6.25W
Maximum Junction Temperature, TJ ••••••••..••••...•.. 150°C
Ambient Operating Temperature .••...••••••••. -40oC to +125°C
Storage Temperature Range ••••..••...•.••.•• -400C to +150°C
Lead Temperature (Soldering 10s max) ..•.•..•...•.•.. +265°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not Implied.

Electrical Specifications
PARAMETERS
Operating Voltage Range
Over-Voltage Shutdown

TA =_40°C to +125°C, VIN
SYMBOL

=2V, Vcc =+12V, Unless Otherwise Specified.

TEST CONDITIONS

Vce
Vovso

Rl

=1Kn; VIN =2V

MIN

TYP

MAX

UNITS

4.5

-

25

V

26

33

38

V

Over-Temperature Limiting

Tso

Negative Pulse
Output Clamp Voltage

Vel

lel = -100mA; Vee

Short Circuit Current Limiting

Isc

(Note 4)

Input Control ON

VIH

Input Control OFF

Vil

-

Input Current High

IIH

VIN

=5.5V, Vec =6V to 24V

6

III

VIN = 0.8V, Vcc =6V to 24V

6

-

Input Current Low

150

=4.SV to 25V

Supply Current, Full Load
Input Control ON

ICCMAX

VIN = 2V; lOUT =1.0A;

Supply Current, No Load
Input Control OFF

ICCMIN

VIN

Input-Output Forward Voltage
Drop (VCC - VOUT)
Output Leakage
Turn ON Time
Turn OFF Time

=OV; lOUT =OA;

VSAT

lOUT =1A; Vcc =4.5V to 25V

IOUT_lK

VIN = 0.8V; Vee = 6V to 24V

ioN

Rl

=SOn; (Note 3)

IoFF

Rl

=SOO; (Note 3)

°C

(Vee - 3S)

(Vee - 30.5)

(V cc - 2S)

V

1.1

1.6

2.5

A

2.0

-

-

V

O.S

V

40

I1A

30

I1A

-

1.05

1.1

A

-

55

100

I1A

-

0.6

1

V

4

50

I1A

5

20

I1S

25

65

I1S

-

NOTES:
1. The Input Control Voltage, VIN shall not be greater than (Vee - 0.5V) and shall not exceed +7V when Vec is greater than 7.5V.
2. The worst case thermal resistance, 8JC for the SIP TS-001 AA 5 lead package is 4°CIW. The calculation for dissipation and junction temperature rise due to dissipation is:
Po = (VCC-VOUT)(IOUT) + (VCC)(lCCMAX - lour) or (VCC)('CCMAX) - (VOUT)(IOUT)
TJ = TAMBIENT + (Po) (8Jd for an Infinite Heat Sink.
Refer to Figure 2 for Derating based on Dissipation and Thermal Resistance. Derating from +150°C is based on the reciprocal of thermal
resistance, 8JC +8HS ' For example: Where 8JC = 4°CIW and given 9HS = ffCNoI as the thermal resistance of an eX1ernai Heat Sink, the
junction-to-air thermal reSistance, 8JA = 100CIW. Therefore, for the maximum allowed dissipation, derate 0.1Wf'C for each degree from
TAMB to the maximum rated junction temperature of +150oC. I!TAMB = +100oC, the maximum Po is (150 -100) x 0.1Wf'C = SW.
3. Refer to Figure 3A and 38 for typical switching speeds with a 200 Load.
4. Short circuit current will be reduced when thermal shutdown occurs. Testing of short circuit current may require a short duration pulse.
See Figure 7.

3-7

HIP 1030
Typical Application
-~o'-_--+ POWER

SUPPLY

LOADS:
RELAYS
SOLENOIDS
LAMPS
MOTORS

'.:=. . . . . . . . . . . . . . . :,.,~~.:;

-=- GND

TO VIN

-=- GND

Typical Performance Curves
16

"-

,

WITH EXT. "
6 0 CIW H. S.

1\
\

I"-

1.5

WITH EXT.
OOCIW H.S.
(INFINITE
HEAT SINK)

\

I'..

~

=lon, Vee = VSAT + IL RU VSAT =(Vee - VOUT)
=5V

DATA TAKEN USING 110CM x 110CM

>A:

,

""-

RL

INPUT: VIN

FLAT ALUM. HEAT SINK
1.0

I

§

IL

~

g

IL

.50

100

o

150

15

,,

TON

Vee = 12V, LOAD = 200 IN PARALLEL
WITH 2200pF; TA. +25OC
INPUT: VIN = 2V 10 OV STEp, lms PERIOD, 500~ PULSE-

r"-.. t"--,.

J

o
o

2

FIGURE 3A. OUTPUT TURN-ON TIME (liS)

..l

~

TOFF

1

150

'\.

I
o

100

1\

f'\~

o

50

FIGURE 2. TYPICAL FORWARD VOLTAGE DROP,VSAT
CHARACTERISTICS vs AMBIENT OPERATING
TEMPERATURE

Vee = 12V, LOAD 20n IN PARALLEL
WITH 2200pF; TA = +25 0 C
INPUT: VIN OV 10 2V STEp, 1ms PERIOD, 500~. PULSE

=

0

AMBIENT TEMPERATURE ("C)

FIGURE 1. DISSIPATION DERATING CURVES

=

V

J

-50

AMBIENT TEMPERATURE ("C)

15

~

= 1.0 A

IL = O.SA

~

~

0

V

I

"- c\
~

~

I

:!

~

o

=1.25A

I

I
10

20

FIGURE 3B. OUTPUT TURN-OFF TIME (liS)

FIGURE 3. TYPICAL RISE TIME AND FALL TIME CHARACTERISTICS OF THE HIP1030 WITH A RESISTIVE AND CAPACITIVE
LOAD. THE TURN-ON TIME OF APPROXIMATELY 1.1I1S IS PRIMARILY DETERMINED BY THE Vee SUPPLY. THE OUTPUT FALL TIME IS LIMITED BY RC TIME CONSTANT OF THE LOAD.

3-8

HIP1030

Typical Performance Curves (Continued)
15 ,---------------------------------,
Vee = 12V, LOAD .160; TA" +250 C

Vee. 15V, LOAD .. 70mH + 22.30 IN SERIES; TA=+2SOC
INPUT: VIN .. OV to 2V STEP, 50% DUTY CYCLE PULSE

INPUT: VIN = OV to 2V STEP, 50% DUTY CYCLE PULSE

~

:;;; 15

w

CI
~

g

CI

10 r__f---r--i---r__f---r--+-~r__f--~

g~

w

~

~~

Q.

Q.

~

~

5 r__f---r--i---r__f---r--+-~r__f--~

10

0

~

~

~~~:J~~~~NpDJt~~V~

~ -5

La
o

~

-15
0.4

0.8
1.2
SWITCHING TIME (ms)

1.6

o

2.0

FIGURE 4. TYPICAL SWITCHING CHARACTERISTIC OF THE
HIP1030 WITH AN OUTPUT RESISTIVE LOAD

6

2

4

5

INDUCTIVE PULSE SWITCHING TIME (ms)
FIGURE 5. TYPICAL OUTPUT INDUCTIVE LOAD SWITCHING
PULSE. THE NEGATIVE CLAMP VOLTAGE
(Vee -31V) FOR THE INDUCTIVE KICK PULSE IS
REFERENCED TO THE Vee SUPPLY INPUT

6

Vee=4.5V, LOAD = SO, TA = +250 C
INPUT: VIN" OV to 2V STEP, 1ms PERIOD, 500..s PULSE

Vee" 4.5V, LOAD. en, TA. +250 C
INPUT: VIN" OV to 2V STEP, 1m. PERIOD, 500.... PULSE

--TON~

4

~

"I'..

2

................
J

TOFF

o

o

2

3

4

o

5

I

o

FIGURE SA. TURN-ON TIME (Ils)

T

I

4

12

S

16

20

FIGURE S8. TURN-OFF TIME (IlS)

FIGURE S. TYPICAL LOW SUPPLY VOLTAGE SWITCHING CHARACTERISTICS OF THE HIP1030. THE TURN-ON AND TURN-OFF
CHARACTERISTICS ARE SHOWN FOR Vee = 4.5V.

3

Vee = 24V, LOAD = 10; TA = +25oC
INPUT: VIN = 2V, 1 ms PERIOD, 100..s PULSE

~

w

~

!j

g

Vee VARIED FROM 4V TO 36V, NO LOAD
INPUT: VIN" 2V (DC); TA. +2SOC

I I

2

-

--rl~~~~T

w
~

:::>

II.

~

:::>

I
~~

,-

I

I

OVER-VOLTAGE
/.SHUTDOWN

Q.

~

~

0

o

o

....

\.

40

so
120
160
OUTPUT PULSE TIME II's)

o

200

o

5

10

15

20

25

30

35

40

45

50

SUPPLY VOLTAGE (V)
FIGURE 7. TYPICAL OUTPUT CURRENT PULSE WHEN
SWITCHING INTO A LOW IMPEDANCE (10), OR
SHORTED LOAD. FOR THE CONDITIONS SHOWN,
OUTPUT CURRENT LIMITING IS -1.7A

3-9

FIGURE

8. TYPICAL IDLE CURRENT vs SUPPLY VOLTAGE
WITH NO LOAD

HIP 1031
Half Amp High Side Driver with
Overload Protection

PRELIMINARY
March 1994

Features

Description

• Over Operating Range: -40oC to +125 0 C
• 1.0V Max V SAT at O.6A
• 4.5V to 25V Power Supply Range

The HIP1031 is a High Side Driver Power Integrated CirCUIT
designed to switch power supply voltage to an output load. It
is the equivalent of a PNP pass transistor operated as a
protected high side current switch in the saturated ON state
with low forward voltage drop at the maximum rated current. It
has low output leakage and low idle current in the OFF state.

• Over·Voltage Shutdown Protected
• Over·Current Limiting

The Functional Block Diagram for the HIP1031 shows the
protection control cirCUIT functions of over-current. overvoltage
and over-temperature. A small metal· resistor senses
overcurrent in the power supply path of the pass transistor
and load. Overvoltage detection and shutdown of the output
driver occurs when a comparator determines that the supply
voltage has exceeded a comparator reference level. Overtemperature is sensed from a VSE differential sense element
that is thermally close to the output drive transistor. In addition
to the input detected overvoltage protection, negative peak
voltage of an inductive load is clamped with an internal zener
diode. An internal bandgap supply voltage source provides a
stable voltage reference over the chip operating temperature
range, providing bias and reference control for the protection
circuits.

• Thermal Limiting Protection
• 60VpK Load Dump
• Reverse Battery Protection to -16V

Applications
• Motor Driver/Controller
• Driver for Solenoids, Relays & Lamps
• MOSFET and IGBT Driver
• Driver for Temperature Controller

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

HIP1031AS

-40°C

to +125°C

The HIP1031 is particularly well suited for driving lamps,
relays, and solenoids in automotive and industrial control
applications where voltage and current overload protection at
high temperatures is required. The HIP1031 is supplied in a 5
lead TS-OOl AA Power SIP package.

PACKAGE
5 Lead TS-001M SIP

Pinout

Functional Block Diagram

···.- --.., ......... -_ .... -- ....................... _........ _.. _......-..-...... -_ ..-.....-..... --..........

HIP1031 (SIP)
TOP VIEW

:J)iili ~~~t;;:~l)

f,1o~III
L
.. ::. _

1 vee (SUPPLY)

"'

~

Vee:
1

: Your

:

VBATT :

SUPPLY:

'

1""'""----. ..."--~~ 1""'"--"1 ..._J........

- -

:
:
: ~......

..... .... .....
.........................
:
·:________________________________
~

~.....,,.....

.Jri~N~:

~

CONTROL:

........................

~.;~;

.................

GND

CAUTION: These devices are sensttive to electrostatic discharge. Users should follow proper I.C. Handting Procedures.
Copyright © Harris Corporation 1994

3-10

~

GND

File Number

3596.2

Specifications HIP1031
Absolute Maximum Ratings

Thermal Information

Supply Voltage, Vcc ............ See O.V. Shutdown Limit, Vovso
Input Voltage, V1N (Note 1) .......•............•. -0.8V to +7V
Load Current, lOUT' . . • . . . . • . . . . . • . . . . . . . .. Internally Limiting
Load Dump (Survival) ...............•....••....... ±60VPK
Reverse Battery . . . . • . . . . . • . . . • • . . . • . • . . . . . . . . . . . • .. -16V

8JA
8JC
Maximum Thermal Resistance
Plastic SIP Package . . . . . . . . • . . • • . . • .. 500 CfW
4°CfW
Maximum Power Dissipation, (Note 2)
AtTA = +125°C,lnfinite Heat Sink ..•................. 6.25W
Maximum Junction Temperature, TJ ..........•.••...... 150°C
Ambient Operating Temperature .•..........•.• -40oC to + 125°C
Storage Temperature Range .•.•....•..••.••.• -40°C to +150°C
Lead Temperature (Soldering lOs max) •.••••..•..•..... 265°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at thess or any other conditions above those indicated in the opsrational sBc/ions of this specifICation is not implied.

Electrical Specifications
PARAMETERS
Operating Voltage Range
Over-Voltage Shutdown

TA = -4O"C to +125°C, V1N = 2V, vcc = +12V, Unless Otherwise Specified

SYMBOL

TEST CONDITIONS

Vce
Vovso

Rl = lKO, V1N = 2V

MIN

TVP

MAX

UNITS

4.5

-

25

V

26

33

38

V

150

-

°C

(Vce - 62)

(Vee - 37)

(Vee - 28)

V

0.7

1.1

1.7

A

Over-Temperature Limiting

Tso

Negative Pulse
Output Clamp Voltage

VCl

ICl = -100mA, Vcc = 4.5V to 25V,
V1N =0.8V

Short Circuit Current Limiting

Ise

Note 3

Input Control ON

VIH

Input Control OFF

Vil

Input Current High

IIH

VIN = 5.5V, Vcc = 6V to 24

10

Input Current Low

III

VIN = 0.8V, Vec = 6V to 24V

10

V

2.0

-

0.8

V

-

40

J.lA

30

J.lA
A

Supply Current, Full Load,
Input Control ON

leeMAX

VIN = 2V; lOUT = 0.55A

-

-

0.6

Supply Current, No Load,
Input Control OFF

ICCMIN

VIN = OV; lOUT = OA

-

55

100

J.lA

lOUT = 0.6A, Vee = 4.SV to 2SV

-

-

1.0

V

VIN = O.BV, Vee = 6V to 24V

-

-

SO

J.lA

ioN

Rl = 800, TA = +12SoC

-

6

20

!IS

loFF

Rl = BOO, TA = +125°C

-

17

65

!IS

Input-Output Forward Voltage
Drop (Vec - VOUT)
Output Leakage
Turn-On Time
Turn-OFF Time

VSAT

IOUT_lK

NOTES:
1. The Input Control Voltage, VIN may range from -0.85V to +7V for a Vcc supply voltage of OV to +25V.
2. The worst case thermal resistance,eJc for the SIP T0-220 S pin package is 4°CIW. The calculation for dissipation and junction temperature
rise due to diSSipation is:
Po = (Vce-VouT)(IOUT) + (VCc)(ICCMAX -lOUT) or (VCcl(lCCMAX) - (Vour)(IOUT)
TJ = TAMSIENT + (Po) (8Jcl for an infinite Heat Sink.
Refer to Figure 1 for Derating based on Dissipation and Thermal Resistance. Derating from 150°C is based on the reciprocal of thermal
resistance, 8Jc+8 HS' For example: Where 8JC = 4°CIW and given eHS = 6°1W as the thermal resistance of an external Heat Sink, the
junction-to-air thermal resistance, 9JA = 1OOCfW. Therefore, for the maximum allowed dissipation, derate 0.1 Wf'C for each degree from
TAMS to the maximum rated junction temperature of 150°C. If TAMS = 100°C, the maximum Po is (150 - 100) x O.IWf'C = 5W.
3. Short Circuit current will be reduced when Thermal Shutdown occurs. Testing of a short circuit current may require a short duration pulse.

3-11

HIP1031
Typical Application
HIP1031 HIGH SIDE DRIVER

.......

--- -_ ...... ---- -_ ........ -- --- -_ .... -_ ...... -_ .... _.... _.......................... -...... .,,
~----------~t---------------~~.,

:,,,,

LOADS:
RELAYS
SOLENOIDS
LAMPS
MOTORS

SVIN

5}-~------------------------------~

GND

GND

Typical Performance Curves
16

"

14

WITH EXT. &oCIW
r!!EATSINK

t\

0

~

I-

1\

I"

8

1\

2

a

-SO

-25

0

a:

,

I' I'-

4

0.6

r-

I
I
I
I
I
I
HIP1031 VSAT WITH
200 RESISTIVE LOAD

I

~

g

1

0.4

I

c

a: 0.3

~
~

"-

~

/

J

J...1-t""I

I--""

l I =I J I--'"

VSAT AT lOUT

0.2

VSAT AT lOUT

-50

~

..... i'"""

=0.25A
1 1

-25

0

25

50

75

FIGURE 2. TYPICAL V SAT CHARACTERISTIC
TEMPERATURE

3-12

~

0.5A

100

AMBIENT TEMPERATURE <"C)

FIGURE 1. DISSIPATION DERATING CURVES

'"

0.1

o

150

I

=

w 0.5

!:l

I

I
I
I
I
VSAT AT lOUT 0.75A

c

~

0
25
50
75
100
125
AMBIENT TEMPERATURE ("C)

--

~ 0.7
Q.

HEAT SINK)

1\

1\

6

0.8

WITH EXT.
OOCIW
HEAT SINK
(INFINITE

vs

125

HIP 1090

HARRIS
SEMICONDUCTOR

Protected High Side Power Switch
with Transient Suppression

April 1994

Features

Description

•
•
•
•

The HIP1090 is a Protected Power Interface Switch
designed to suppress potentially damaging overvoltage
transients with peak voltage source inputs ranging up to
±90V in amplitude. It is designed to be operated in a 'hardwired' pass-thru mode or as a high side power switch which
controls the current flow through a PNP pass transistor of
the IC. In either mode The HIP1090 has a low saturated
forward voltage drop. The protected load circuit is connected
to the output of the IC. As such. the HIP1090 operates as a
transient suppressor where the PNP drive transistor is
switched off when V IN is greater than the Overvoltage Shutdown range of 16V to 19V. Shutdown also occurs when VIN
is less than the forward turn-on threshold of approximately
2.5V. including the negative voltage range.

±90V Transient Suppression
4V to 16V Operating Voltage
1A Current Load Capability
Low Input-Output Voltage Drop With Controlled Saturation Detector for
- Fast Low Current Turn-OFF
- Reduced No-Load Idle Current
• Over-Voltage Shutdown Protection
• Short Circuit Current Limiting
• Over-Temperature Limiting Protected

• Thermal Limiting at TJ = +150°C
• -40°C to +105°C Operating Temperature Range

Applications

The merits of transient suppression depend on the required
integrity of the applications load elements. Instrument panel
Signal warning lights for critical functions such as over
temperature or low fluid levels can be protected by the
HIP1090 against high level transient voltages and double
battery conditions that may potentially cause bulb burnouts.
The HIP1090 may be used to protect the power supplies of
small signal or logic circuits with voltages ranging from 4V to
16V. effectively blocking higher peak voltages.

• Electronic Circuit Breaker
• Transient Suppressor
• Over-Voltage Monitor
• High Side Driver Switch for
- Relays
• Solenoids
- Heaters
- Motors
- Lamps

Ordering Information
PART
NUMBER
HIP1090AS

TEMPERATURE
RANGE

PACKAGE

-40°C to + 105°C

Pinout

TO-220AB SIP

Functional Block Diagram
". . . _.............. _1_ . . _______ ................ , .................................. ........ ____ . . . ___ .. __ ........ __ ,

HIP1090 (SIP)
TOP VIEW

,

1
NOTE:
HEAT SINK TAB -->
INTERNALLY
CONNECTED
TOPIN2

0
1 2 3

III
I

:

,

~

Rs

: 3

VIN

:

Your

(Vee OR

:

(TO LOAD)

VBATT)

I

The HIP1090 has internal current limiting protection in the
range of 1A to 2A for short circuit to ground conditions and
thermal shutdown protection when the junction temperature
is greater than 1500 C It is capable of driving resistive,
inductive or lamp loads (such as lamps No. 168 or 194) with
minimum risk of damage under harsh environmental stress
conditions. The HIP1090 is supplied in a 3 lead TO-220AB
package.

,,
,,
,,,
,,,
,,,
,',...... _ ............... __ .......... __ ........ __ ..................................................

I

,

.. ... __ ........... , __ ..... _ .......... J

VCON

I I I

(CONTROL OR GND)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

3-13

File Number

3398.2

wen
ow
-::r:
en()

::r:1-3=
::r:en

(!J-

Specifications HIP1090
Absolute Maximum Ratings

Thermal Information

Input (Supply) Voltage, VIN (Control Pin Reference)......... ±24V
Transient Max Voltage, VIN (15ms). • . . • . . . . . . . . • . . . . • .. ± 90V
Load Current, lOUT' ................... Short Circuit Protected

Thermal Resistance
9JA
Plastic SIP Package • . . . . • . . . . . . . . . .
500 C/W
Maximum Power Dissipation, (Note 4)
At TA = +105°C, Infinite Heat Sink ................... 11.25W
Junction Temperature .............................. +150°C
Ambient Temperature Range . . . . . . . . . . . . . . .. -40°C to +1 05°C
Storage Temperature Range ..•......•..•..... -400 C to + 150°C
Lead Temperature (Soldering During) ..•...•....•..•... +265°C
1/16 ± 1/32 inch (1.59 ± 0.79mm) from ease for lOs maximum

CAUTION: Stresses abo... those listed in "Absolute Maximum RaUngs" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other condffions abo... those indicated in the operational sections of this specification is not implied.

Electrical Specifications TA = -400C to +105°C; VIN = 4V to 16V; VeON = GND or OV, Unless Otherwise Specified
PARAMETERS
Input (Supply) Voltage Operatfng
Range

MIN

TYP

MAX

UNITS

(Note I); Also, see Figure 4 for
Expanding VIN Range

4

-

16

V

-

V

SYMBOL
VIN

TEST CONDITIONS

Input Voltage Threshold for Forward
Turn-On to Load

VTHO

Load = 1k.Q

-

2.5

-

Input Voltage for Output Shutdown

VSHSO

(Note 2)

16

Output Shutdown Leakage

IlEAK1

VIN = 19V and 24V; Load = I k!l

Output Cutoff Leakage

IlEAK2

VIN = 16V; Control Open; Load = I kQ

-

Thermal Shutdown Temperature

Tso

Maximum Output Transient Pulse
Current

lounTran)

VIN = ±90V for 15ms, VOUT = 14V

Maximum Control Transient Pulse
Current

IOON(Tran)

VIN = ±90Vfor 15ms, VOUT = 14V

Short Circuit Current

VIN = 4V, lOUT = 175mA
VIN = 9V, lOUT = 500mA
VIN = 16V, lOUT = SOOmA
VIN = 16V, lOUT = lA

Control Current

lOON

VIN = 16V,IOUT = 100mA

IlA
°C

-20

+20

mA

-50

+50

mA

-

-

-

-

-

Switch VIN 5.5V to OV(GND); Measure
VOUT (to 90%); Load = I k.Q (Note 3)

-

ioN

See Figure 3 and Figure 4 (Note 3)

IoFF

See Figure 3 and Figure 4 (Note 3)

ioN

Turn OFF (Fall Time);
'Pass-Thru· mode

IoFF

Turn ON (Rise Time);
High Pass Switch mode
Turn OFF (Fall Time);
High Pass Switch mode

2

A

0.25

V

0.65

V

1.05

V

25

mA

50

mA

O.S

-

Turn ON (Rise Time);
'Pass-Thru' mode

VIN = 16V, lOUT = IA
Switch VIN OV(GND) to 5.5V; Measure
VOUT(to 90%); Load = lk!l (Note 3)

V

I1A

-

-

VIN = 16V, lOUT = SOOmA

19
100

-

I
150

1

Isc

Input-to-Output Voltage Drop

-

V

50

mA
20

j!S

-

20

j!S

-

15

-

j!S

-

15

-

j!S

NOTES:
1. The Input Operating Voltage is not limited by the threshold of Shutdown. The VIN voltage may range to ±24V while the normal functional
switching range is typically +2.5V to +17 .5V (reference to VOON)'
2. The Output Drive is switched-off when the Input voltage(Supply pin), referenced to the Control pin exceeds the threshold shutdown
VSHSD or the input voltage Is less than the forward turn-on threshold (Including negative voltages within the transient peak ratings).

3. TON and TOFF times include Prop Delay and Rise/Fall time.
4. The worst case thermal resistance,9 JC for the SIP TO-220 is 4°CIW. The calculation for dissipation and junction temperature rise due to
dissipation is:
Po =(VIN -VOUT ) + (VIN)(l ooN )
TJ = TAMBIENT + (Po) (9Jclfor an Infinite Heat Sink.
Derating from 150°C is based on the reciprocal of thermal resistance, 9JC+8HS' For example: Where 9JC 4°C/W and given 9HS SOIW as
the thermal resistance of an external Heat Sink, the junction-te-air thermal resistance, 9JA = 100 CIW. Therefore, for the maximum allowed
dissipation, derate O.IWf'C for each degree from TAMB to the maximum rated junction temperature of 150°C. If TAMB = 1000C, the maximum
Po is (150 - 100) x O.IWI'C = 5W.

=

3-14

=

HIP1090

Applications
The HIP1090 may be used as a "hard-wired pass-thru"
device to protect the load from source voltage transients or
may be used as an active high side power interface switch
with up to 1A of Load current capability. An ON state
condition of (VIN - 4V) S; VCON S; (VIN - 16V) is the normal
range required to activate the high pass switch, allowing the
supply source to conduct through the PNP to the load. When
the control terminal, VCON is open, the high pass switch is
open (no conduction). Figure 2 shows an HIP1090
application example with a switch in the VCON terminal. In
comparison to the hard wired circuit of Figure 1 where pin 2
is fixed at ground, pin 2 in the circuit of Figure 2 is switched
from open to ground to turn-ON the high pass switch. Used

,;_ ... ----... --_ .......... -_ .... ., .................... -_ ........... -_ .......................................... '";,
: YIN
Rs
YOUT:
,,

INPUT 1
SWITCH

in this mode, the HIP1090 is both an effective transient
suppressor and a high pass switch. The switch in the VCON
terminal may be active or passive and conducts typically less
than SOmA of current. The HIP1090 used in the controlled
switching mode retains all of the protected features of the
device. In either circuit the output capacitor may be
increased in size to hold charge longer during transient
interruptions at the input. The charge duration for larger
capacitors or for lamp loads is tolerated because of the
internal short circuit current limiting protection. Sustained
short circuits may cause the junction temperature to reach
the thermal shutdown temperature (1500 C).

1 :,
,,:
,,
,
,,:

YSATT

r - - -..... p-Io--"",", ,.........-

..... _--1....._.

DASH PANEL LOAD

3

TO OTHER
UGHTS
AND
INSTRUMENTS

r - i - -.....

I...-~"" ....--r--ll...-~........-r-~ I...-~""

,

,

. . . . . . . . . . . . . . . _ _ .. _ _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ _ ..

. . . . _ _ _ . . . . _ _ .. _ _ _ _ . . . . . . . . 4

2
YCON

(CONTROL OR GND)
FIGURE 1. TYPICAL APPLICATION OF THE HIP1090 AS A TRANSIENT SUPPRESSOR IN A "PASS-THRU" MODE

,. .. -........... -.......... -- -_ ...................................... -....................................................,,
INPUT 1

YIN

Rs

VOUT: 3

VBATT--~-+----------~~~~------------~

,,

,,,

_ - - _ . p-Io--"",", ,.........-

.

L-....,._...

..... r - -..........

~-'T"'".............,._... I.~.....,r-"

................ ___ ............ _____ .. __ ........ ________ .... _ .. __

2
NOTE:

=

V LOAD VBATT - V SAT
VSAT TYP < O.BV allA

r - i - -.....

!,
:,,
,,

........,._.... :

,

....... _ ...... _______ ___ ... ,J

YCON

(CONTROL)
OFF~ ON

SWITCH"*"

FIGURE 2. TYPICAL APPLICATIONS OF THE HIP1090 AS A TRANSIENT SUPPRESSOR IN A HIGH PASS SWITCH MODE

3-15

HIP 1090
Figure 3 shows the pulsed output switching characteristics of
the HIP1090 as a high side driver. A small delay step is
noted on the rising edge due to the hold-off of a VCESAT
detector circuit. The VCESAT circuit senses the saturation
level of the PNP pass transistor and controls the drive as a
ratio of load current. As the load current is reduced, the drive
current to the output transistor is reduced. Under low current
operation, the saturation level is controlled and the turn-OFF
switching time js much faster. The control switching element
is shown as a 2N5320 NPN transistor but may be any open
collector or MOS gate. A pull-up resistor of 2k.Cl is used for a
slight improvement in the turnoff fall time but is not an
essential requirement. The VCON terminal may be controlled
with a mechanical switch or may be controlled from any
driver output that can sink the worst case condition of pin 2
current, ICON when the output load current is increased to 1A
(typically 50mA).

The circuit of Figure 4 shows how the HIP1090 transient
suppression voltage shutdown threshold may be increased
by using a zener diode from the VCON terminal to the collector terminal of the transistor switch. The preferred method is
to use a zener diode for a fixed level shift. While a resistor in
place of the zener diode having the same voltage drop will
work well, the parametric variation of the ICON current will
cause variations of the Over-Voltage Shutdown Threshold.
In this circuit, a 10V zener provides a typical overvoltage
threshold shift to -27V. The threshold for overvoltage shutdown is referenced to the (V IN - VCON ) voltage difference.
+24V

ON

+16V
(SUPPLY INPUT)
21<0
OPTIONAL

HIP1090

n

'------~ VeON

OFFJ

1kU

L-

.

15
10

--1----------,
Your

s!
o

I

_ _ _oJ
_ _ ~ ...... __ ......................
I

:

TON

,

,

:

-1-........ __ ...... ~I

I

:

:.......
~-15-f18-~..~:

::;J

:

I

, VB

I

TOFF

_
I ..:

I'

15f18

2N5320
OR EQUIVALENT

L-

Also, it is important to note that high peak current values
may be reached when driving nonlinear and inductive loads.
The peak output current of the HIP1090 is self limiting in the
1A to 2A range to protect against short circuit conditions.
Sustained high peak current may increase the junction temperature to 1500 C and cause thermal shutdown. When this
happens, the output current will fall off briefly before recovering, unless the over-temperature condition is sustained.
Internally, both input and output overvoltage conditions are
sensed to protect the circuit, making the high levels of transient voltage ratings possible. Sustained voltage ratings of
±24VDC with transient ratings to ±90V allow a wide variety
of applications in high stress environments.

:,

,:

10V

1kU
0-

FIGURE 4. A TYPICAL APPLICATION CIRCUIT THAT USES A
ZENER TO THE VeoN TRANSISTOR SWITCH TO
THE
OVERVOLTAGE
SHUTDOWN
RAISE
THRESHOLD

2N5320
OR EQUIVALENT

VB 0-

n

OFFJ

24Q
_
(CONTROL PIN)

ON

HIP1090

(SUPPLY INPUT)
21<0
OPTIONAL

'
.. :

1

FIGURE 3. TYPICAL ON-OFF SWITCHING CHARACTERISTIC
OF THE HIP1090 USING AN NPN TRANSISTOR TO
SWITCH THE VCON INPUT TERMINAL

Except for the VCESAT detector circuit, the HIP1090 is a
higher current version of the CA3273 high side driver, which
turns-on without the delayed step on the leading edge of the
output pulse; switching with a typical TON time of -O.5Ils.
The CA3273 has a higher transient suppression threshold.

3-16

HIP1090

Typical Performance Curves
60

Ci'

.E.

30

50

I-- I-

N

z

~

RLOAO= 16!l
VCON=GND

40

IZ

w

II:
II:

i3.....
0

30
20

II:

IZ

0

(.)

,

TA = +2S"C

---

1/

/

V

V

/

Ci'

.E.

25

N

VOUTOPEN

~ 20

I-

Z

w

II:
II:

15

~

(.)

..... 10
0

II:

I-

Z

0

(.)

5

o
5

TA = +2SoC
VCON-GND

z

10

00

I

I

r--

10

15

20

I
o

VIN SUPPLY VOLTAGE (V)

I

.E.

1000

~

800

-

w
CJ

600

~
z

400

"Ie

200

::l

~

II)

I

TA=+250C

II

RLOAO= 16!l
VCON=GND

V

L

........... ./'

>

o

o

15

20

FIGURE 6. CONTROL (QUIESCENT) CURRENT CHARACTER·
ISTIC WITH NO LOAD

g

.,

10

VIN SUPPLY VOLTAGE (V)

FIGURE 5. CONTROL (QUIESCENT) CURRENT CHARACTER·
ISTIC WITH LOAD

:;-

5

0.5

1.0

1.5

LOAD CURRENT (A)

FIGURE 7. SATURATION (VIN • VOUT) CHARACTERISTIC

3-17

HV400
High Current MOSFET Driver

April 1994

Features

Description

• Fast Fall Times •••••••••••••.••••• 16ns at 10,OOOpF

The HV400 is a single monolithic. non-inverting high current
driver deSigned to drive large capacitive loads at high slew
rates. The device is optimized for driving single or parallel
connected N-channel power MOSFETs with total gate
charge from 5nC to > 1OOOnC. It features two output stages
pinned out separately allowing independent control of the
MOSFET gate rise and fall times. The current sourcing output stage is an NPN capable of 6A. An SCR provides over
30A of current sinking. The HV400 achieves rise and fall
times of 54ns and 16ns respectively driving a 10.000pF load.

• No Supply Current in Quiescent State
• Peak Source Current ••••••••••••••••••••••••.• 6A
• Peak Sink Current ••••••••••.••••••••••••.••• 30A
• High Frequency Operation ••••••••••••.•••• 300kHz

Applications
• Switch Mode Power Supplies

Special features are included in this part to provide a simple.
high speed gate drive circuit for power MOSFETs. The
HV400 requires no quiescent supply current. however. the
input current is approximately 15mA while in the high state.
With the internal current steering diodes (pin 7) and an
external capacitor, both the timing and MOSFET gate power
come from the same pulse transformer; no special external
supply is required for high side switches. No high voltage
diode is required to charge the bootstrap capacitor.

• DCIDC Converters
• Motor Controllers
• Uninterruptible Power Supplies

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

The HV400 in combination with the MOSFET and pulse
transformer makes an isolated power switch building block
for applications such as high side switches. secondary side
regulation and synchronous rectification. The HV400 is also
suitable for driving IGBTs. MCTs. BJTs and small GTOs.

PACKAGE

HV400lP

8 Lead Plastic DIP

HV400lB

8 Lead Plastic sOle (N)

HV400MJ/BB3

-55°C to +125°C

The HV 400 is a type of buffer; it does not have input logic
level switching threshold voltages. This single stage design
achieves propagation delays of 20ns. The output NPN
begins to source current when the voltage on pin 2 is
approximately 2V more positive than the voltage at pin 8.

B Lead Ceramic SBDIP

The output SCR switches on when the input pin 2 voltage is
1V more negative than the voltage at pins 3/6. Due to the
use of the SCR for current sinking. once the output switches
low, the input must not go high again until all the internal
SCR charge has dissipated. 0.5J.ls - 1.5J.ls later.

Pinout

08

Schematic

HV400 (POIP, SBOIP, SOIC)
TOP VIEW

V+ SUPPLY

PIN 1

~1"111111"11""""'1"""""""'""""'1

PIN 2

,
•

~

~

!

03

D2

~

SOURCE OUTPUT

INPUT 2

7

DIODES

SINK OUTPUT 3

6

SINK OUTPUT

GND 4

5

GND

PIN3

. 1

yQ1

!1

v.. ~
Q2

!R3

R4

t~

~

R2

:

"

08

~"D6

"SCR

R1

~N7

~ PIN 6

~____~____-,7

;

•

:~ PIN 8

"".

:

~

~D4"

~

~~ D1~

~

07!

1•
,

•

PIN 4 ~",,,,,,,,,,,,,,,,,,,",",,","",,,,""",,r-o PIN 5
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
.

3-18

File Number

2850.1

Specifications HV400
Absolute Maximum Ratings

Thermal Information

Voltage Between Pin1 and Pin 4/5 . ...................... 35V
Input Voltage Pin 7 (Max) ........................ Pin 1 + 1.5V
Input Voltage Pin 7 (Min) ....................... Pin 415 -1.5V
Input Voltage Pin 2 to Pin 415 • ...................... .. +1- 35V
Input Voltage Pin 2 to Pin 6 ............................ -35V
Maximum Clamp Current (Pin 7) ....•.....•..•.......... ±300mA

Thermal Resistance
SJA
PDIP .•.•..•.••..•.•.•••.•.•...•• 1500 CNI
SOIC .•..•.••..............•••.•. 1700 CNI
91°CNI
25°CIW
SBDIP ..•........•.•..••.•••••.••
Power Dissipation at TA = +250 C
PDIP •....••...••..•..••..••••.••••.•..•..•..•.. 0.8W
SOIC •..•.•.....•.•••.••..••••.•.••..•..•..••.•. 0.7W
SBIP .......................................... 2.33W
Operating Temperature Range
HV400IPIIB ......•..••...••.•...•..•. -400C < TA < +85°C
HV400MJ/883 ....................... -55°C < TA < +125°C
Lead Temperature (Soldering lOS) .....•..•.......•... +265°C
Maximum Junction Temperature •••..•.•.•••••.•.••... + 150°C
Storage Temperature Range ...........•.. -65°C < TA < +150oC

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may CBuse permanent damage to the device. This is 8 stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications

VSUPPLY = 15V

SYMBOL

CONDITIONS

TEMPERATURE

MIN

TYP

Input High Differential Voltage
(Pin 2 - Pin 8)

VIH

Your = OV,l our HI = 10mA

+25°C

0.6

Full

0.5

Input Low Differential Voltage
(Pin 2 - Pin 3/6)

VIL

+25°C

Input High Current

IIH

PARAMETERS

MAX

UNITS

1.7

2.8

V

-

3.5

V

-1.1

-0.9

-0.8

V

Full

-1.26

-

-0.65

V

VPIN 1. 2 = 30V, I SOURCE = 0

+25°C

15

18

20

mA

Full

15

22

mA

I SOURCE = 6A, 1j.1S pulse,
VIN = 9V, Your = OV

+25OC

VPIN2 = -30V

+25OC

-80

Full

-120

INPUT (PIN 2)

Input High Current Peak
Input Low Current

IIHP
IlL

Your = 12V, lour LO = -3mA

700

mA

-50

IlA
IlA

SOURCE OUTPUT (PIN 8)
High Output Voltage

VOH

VIN = +V,lour = 150mA

+25°C

12.1

Full

12.0

Peak Output Current

IOP8

VIN = 9V, 1j.1S Pulse,
Vour = OV

+25°C

Output Low Leakage

10l

Your = OV, VIN = OV

+25°C

12.8

13.4

V

13.5

V

6
0

10

Full

A
50

IlA

55

pA

1.0

V

1.05

V

SINK OUTPUT (PIN 3/6)
Low Output Voltage

VOL

VIN = OV,lour = -150mA

+25°C

0.8

Full

0.8

Peak Output Current

loPs

VIN = OV, 5j.1S Pulse,
Vour=4V

+25°C

Output High Leakage

IOH

VIN = 15V

+25°C

0

Full

0

+25°C

0.8

Full

0.8

+25OC

0

Full

0

0.89

A

30
0.3

2

IlA

13.5

IlA

DIODES Dl AND 07 (PIN 7)
Forward Voltage

Reverse Leakage Current

Diode (Pin 7) Stored Charge

VF

IR

ORR

10 = l00mA
VR =30V

10 = l00mA

+25°C

NOTE: Umits are 100% tested at +25°C; limits over the full temperature range are guaranteed but not tested.

3-19

1.03

0.1

6.5

1.4

V

1.6

V

1

IlA

1

pA

nC

Specifications HV400
Switching Time Specifications
PARAMETERS

VSUPPlY

=15V

SYMBOL

CONDITIONS

TEMPERATURE

TR

See Switching Test Clrcuil

Full

Rise Time

MIN

TVP

MAX

UNITS

50

66

ns

Fall Time

TF

See Switching Test Circuit

Full

15

24

ns

Delay Time (Lo to Hi)

TOR

See Switching Test Circuit

Full

20

25

ns

Delay Time (Hi to Lo)

TOF

See Switching Test Circuit

Full

17

28

ns

Minimum Off Time

TOR

See Switching Test Circuit

Full

900

1500

ns

NOTES:
1. Switching times are guaranteed but not tested
2. Typical values are for +25°C

Switching Diagram and Test Circuit

INPUT
10%

10%

OV----"I

TOR
90%

OUTPUT

+V
C1
330l1F

T

SOV "

1N9l4

,,,

2 :

1sV -------~
GND --- - '
"-

INPUT
son SOURCE
(RISE & FAll nMES <10n8)

,,
,
,
,
,,,
•,
,,,
,,

··
·

..r-".:.:.. l2.8V
O.9V

RL
lOOK

3-20

OUTPUT

HV400
HV400 Switching Test Circuit

Parts List
Rl lOOn 1W Carbon Resistor

J1

R1

R2 Wire
RL 100Kn 1/8W Carbon Resistor

~

C2

C1 330f.1F. 50V Capacitor
C2 1f.1F, 50V Capacitor

U1

J3

CL O.Olf.1F, 50V Chip Capacitor

8

01

P~~~E

PULSE

IN

01 1N914 Diode
J1, J2 PC Mount Banana Jack Johnson 108-0740-001
J3, J4 PC Mount SMA Connector Johnson EFJ142
Ul Harris HV400 I.C.

J1

4.2 •

a

o

3.5 •

HV400

HV400

IN

Ui

GND
o

G)

HV400 AC TEST BOARD

3-21

OUT

[J

HV400
Pin Descriptions
SYMeOL

DESCRIPTION

DC INPUT PARAMETERS
VIH

The differential voltage between the input (Pin 2) to the output (Pin 8) required to source 10mA

VIL

The differential voltage between the input (Pin 2) to the output (Pins 3, 6) required to sink 3mA

IIH

The current required to maintain the input (Pin 2) high with lOUT = OA

IIHP

The Input (Pin 2) current for a given pulsed output current

IlL

The current require to maintain the input (Pin 2) low

DC OUTPUT PARAMETERS

=V+

VOH

The output (Pin 8) voltage with Input (Pin 2)

lops

The pulsed peak source current form output (Pin 8)

10L

The output (Pin 8) leakage current with the input (Pin 2)

VOL

The output (Pins 3, 6) voltage with the input (Pin 2)

lops

The pulsed peak sink current into output (Pins 3, 6)

10H

The output (Pins 3, 6) leakage current with the input (Pin 2)

VF

The forward voltage of diode Dl or D7

IR

The reverse leakage current of diode D1 or D7

ORR

=Ground

=Ground
=V+

The time integral of the reverse current at turn off

AC PARAMETERS (See Switching Time Specifications)
TR

The low to high transition of the output

TF

The high to low transition of the output

TOR

The output propagation delay from the input (Pin 2) rising edge

TOF

The output propagation delay from the input (Pin 2) falling edge

TOR

The minimum time required after an output high to low transition before the next Input low to high transition

3·22

HV400
Application Information
Circuit Operation
The HV400's operation is easily explained by referring to the
schematic. The control signal is applied to pin 2. If the
control signal is about 2V above pin 8, the output NPN 01
turns on charging the MOSFET gate from a capacitor
connected to pin 1. Resistor A4 helps keep the SCR off by
applying a reverse bias to the SCR anode gate.
When the control input drops about 1V below pin 3/6, PNP
02 turns on which triggers the SCR by driving both the
anode and cathode gates. The SCR discharges the
MOSFET gate and when its current becomes less than
10mA, it turns off. Transistor 02 conducts any gate leakage
currents, through resistors A 1 and R2, once the SCA turns
off. Figure 7 shows the output characteristics before the
SCR turns on and after it turns off. When the SCA turns on,
resistor A4 provides a path to remove 01 base charge.
Resistor R3 provides the base current for 02 to reduce the
turn off delay time. Resistors Rl and R2 reduce the SCA
recovery time.
The two diodes connected to the diode input pin 7 provide
some operation flexibility. With pins 2 and 7 connected
together, diode 01 provides a path to recharge the storage
capacitor once the MOSFET gate is pulled high and, along
with diodes 02 and 03, keeps 01 from going into hard
saturation which would increase delay times. Diode 07
would clamp the input near ground and provide a current
path if an input DC blocking capacitor is used.
Alternatively, pin 7 can be connected to pin 6 so that the
SCA and NPN 01 don't have to pass reverse current if the
output "rings" above the supply or below ground. When high
performance diodes are required, pin 7 can be left
disconnected and external diodes substituted.
The diodes in series with pin 2 decouple the input from the
output during negative going transitions. The absence of
input current turns off 01 and allows 02 to trigger the SCA.
Diode 08 turns off 02 once the SCA turns on pulling the output low, otherwise 02 would saturate and slow down circuit
operation. In addition, the diodes 02, 03 and 08 improve
noise immunity by adding about 2.5V of input hysteresis.
The HV400 is capable of large output currents but only for
brief durations due to power diSsipation.

Circuit Board Layout
PC board layout is very important. Pins 3 and 6 should be
connected together as should pins 4 and 5. Otherwise the
internal interconnect impedance is doubled and only half of
the bond wires are used which would degrade the reliability.
The bootstrap capacitor should hold at least lOx the charge
of the MOSFET and should be connected between pins 1
and 4/5 with minimum lead lengths and spaCings. Likewise,
the HV400 should be as close to the MOSFET as possible.
Any long PC traces (parasitic inductances) between the
MOSFET gate and pins 8 or 3/6 or between the source and

pins 4/5 should be avoided. Inductance between the HV400
and the MOSFET limit the MOSFET switching time. If they
are too large, the HV400 may operate erratically as
discussed below.

Cross Conduction Faults
It is possible to have both 01 and the SCR on at the same
time resulting in very large cross conduction currents. The
SCA has larger current capacity so the output goes low and
the storage capaCitor is discharged. The conditions that
cause cross conduction and precautions are discussed
below.

Minimum Off Time
The SCR requires a recovery time before voltage can be
reapplied without it switching back on. Figure 13 shows how
this SCR recovery time, called "minimum off time" (TOR)' is a
function of the load capacitance. If the input voltage goes
high before this recovery time is complete, the SCR will
switch back on.
Note that reverse current flowing through the SCR, for
example due to load inductance ringing, extends the
minimum off time. Since the minimum off time is really
dependent upon how much stored charge remains in the
SCA when the anode (pin 3/6) is taken pOSitive, it may vary
for different applications. Figure 13 indirectly shows that the
minimum off time increases with larger currents. It also
increases.at elevated temperatures as shown in Figure 14.
Excessive ringing increases the minimum off time since the
stored charge doesn't begin to dissipate until the current
drops below 10mA for the last time. Aising anode voltage
acts on the internal SCR capacitance to generate its own
triggering current. The excess stored charge increases this
capacitance. Faster rise times and/or higher voltages also
increase the amount of internal trigger current from the internal capaCitance so applications with larger dVidt require
longer minimum off times.
The minimum off time must be considered for all occurrences of SCA current. For example, in a half bridge switch
mode power supply, there are two MOSFET's connected to
the transformer primary. Assume that the high side MOSFET
switch is off. When the low side MOSFET switch is turned
on, the HV400 driving the high side MOSFET will have to
sink gate current from C gd and will have to source gate
current when the low side MOSFET switches back off. Both
of these current pulses will try to flow through pin 3/6 since
the pin 8 output is turned off. Sourcing current from pins 3/6
through the SCR is possible, the pin 3/6 voltage becoming
negative with respect to pins 4/5 (See Figure 8). But a better
practice would be to connect a Schottky diode between pins
4/5 (anode) and 3/6 (cathode) so reverse current does not
flow through the SCA.
False SeA Triggering
The SCR may be triggered inadvertently. The output may
overshoot the input due to inductive loading or over driving
the output NPN (allowing it to saturate). Whenever pin 6 is
more positive than pin 2 by lV, the SCR is triggered on. Also,

3-23

HV400
if the output rises too rapidly, greater than 0.5V/nS, the SCR
may self trigger. Both issues are resolved by minimizing the
load inductance and inserting sufficient resistance, usually
0.1 to 10 ohms. between pin 8 and the load.

be capable of dissipating the energy stored in the
transformer. The load may be connected to either the power
MOSFET drain or source.
7' .... •........................ •............11

Vs

A very fast negative going input voltage can result in
minimum off times of about 2.5I1s. If the output can not keep
up with the falling input, the stored charge 01 diode D4 is
transferred into the base of 02. This excess charge in 02
must have time to dissipate. Otherwise, when pin 3/6 goes
positive. 02 will turn on and trigger the SCA. An external
diode in series with pin 2, as shown in Figure 1, will prevent
D4 from discharging into the base of 02 but that will also
reduce the output voltage by the forward voltage of that
diode.

4· .......................................... ; 5 POWER
HV400

Internal Diodes
The internal diodes connected to pin 7 are provided for
convenience but may not be suitable for large currents.
Since they are part of the integrated circuit, they are
physically small, operate at high current densities, and have
long recovery times. Figure 15 shows that their forward
characteristics degrade above 100mA. In addition, Figure 16
shows their reverse recovery charge as a function of forward
current. The product of this charge, the applied reverse
voltage and the frequency is the additional power dissipation
due to the diodes. For stored charge calculations, use the
peak forward current within lOOns of the application of
reverse bias. In addition to the extra power dissipation, the
capacitance of Ihese diodes may extend the switching delay
times.

Power Dissipation Calculations
The power required to drive the MOSFET is the product of
its total gate charge times the gate supply voltage (maximum
voltage on HV400 pin 1, 2 or 7) times the frequency.
Assuming that the MOSFET gate resistance is negligible,
this power is dissipated within the HV400. If resistors are
placed between the HV400 and the MOSFET, then some of
the power is diSSipated in the resistors, the percentage
depending upon the ratio of resistors to HV400 output
impedance.
There are two other sources of power diSSipation to
consider. First there is the power in R3 which is the product
of the input pin 2 current and voltage (with no output current)
times the duty cycle. Second is the product of the pin 7 diode
stored charge, which is dependent upon the forward current,
times the applied diode reverse voltage times the frequency.
This information is available from figures 3 and 16 in this
data sheet.

MOSFET

FIGURE 1. UNIPOLAR DRIVE
A diode is added in series with pins 2 and 7 to allow the
transformer secondary to go negative. The charge storage of
the pin 7 diode may cause the turn off delay time to be too
long. Alternatively, pin 7 could be left disconnected and a
second external diode connected between the transformer
(anode) and pin 1 (cathode). In some applications the diode
in series with pin 2 may be unnecessary but the -35V input
to output or ground maximum rating should be observed.
Sometimes the volt-second balance is achieved by a pushpull drive on the pulse transformer primary. This is especially
useful if there are two secondary windings driving two
HV400's out of phase such as in a half-bridge configuration
Other times it is more convenient to achieve volt-second
balance by using capacitors to block DC in the primary and
secondary windings as shown in Figure 2. The pin 7 diodes
provide a path for discharging the secondary side DC blocking capaCitor. Both capacitors, CIN and Cs , should be at
least 10 times the equivalent MOSFET gate capacitance.
The HV400 can be used as a current booster for low side
switches by connecting directly to the PWM output. The
circuit would be similar to the switching time test circuit.
It is worth restating that some consideration (and experimentation) should be given to the choice of external components,
i.e. resistors, capaCitors and diodes, to optimize
performance in a given application.

.

.

7, ............ · .............. · .................. · ....,

cs

j(

Applications Circuits

T1

The HV400 was designed to interface a pulse transformer to
a power MOSFET. There must be some means to balance
the transformer volt-second product over a cycle. The
unipolar drive shown in Figure 1 lets the core magnetization
inductance reverse the primary and secondary voltages. The
zener diode on the primary side limits this voltage and must

4 t •••••••••••••••••••••.••••••••••••••.••••••••••••••t 5
HV400

FIGURE 2. BIPOLAR DRIVE WITH DC BLOCKING CAPACITOR

3-24

HV400

Typical Performance Curves

TA = +25°C Unless Otherwise Specified
15

20

,

c

!.

~ 10

J

IL
o

L

"

14

...- r-

".

13

I

12

€

"

~

,

-"":OH

11

1:

~HP7L
..........

8
7

J

6
5

o

800

10

20

30

40

600
500

/
~

400 ~

,

.......

C

!....

300
200

100
0

o

50

VIN - PIN 2 (V)
FIGURE 3. PIN 2 INPUT CURRENT VI INPUT VOLTAGE WITH
ZERO OUTPUT CURRENT

1,.....00'

V

/

700

234
10P8(A)

5

6

FIGURE 4. PIN 2 IIIIP & VOH VI OUTPUT SOURCE CURRENT

10

o
-20

l

/

/~

V

/

4

3

-40

/

/
J

-60

/

-80

/

I

I

-100
-50

-40

o

o

-30
-20
-10
INPUT VOLTAGE - PIN 2 (V)

VPIN2~12V

6

o
1J!A,

10

30

20

FIGURE 6. VOL VI lops (51LS PULSES)

-I

12

3

o

IOP6(A)

FIGURE 5_ PIN 2 IlL VI INPUT VOLTAGE

15

./'

SWEEP

-

-

o
-1

---r-

I""-

-

...... ~

-4

I
10J!A,

100J!A,

R

+2;(oC

SWEEP

VPIN2=OV -

~

,.".1mA

r--

10mA

-6

100mA

IoP6
FIGURE 7. PIN 316 ILLUSTRATING OUTPUT VOLTAGE VI SCR
OUTPUT SINK LATCHING AND HOLDING CURRENT

3-25

~OOC

~50C
I

o

1
lops (A)

2

FIGURE 8. PIN 316 VOLTAGE VI REVERSE CURRENT 300ILS
PULSES

HV400
Typical Performance Curves

+10

....

f

::>-

... >

~-

-V

J

0

f

+10

....
::>

TA = +2SoC Unless Otherwise Specified (Continued)

)

~~
0

/

0

10

50nsJDIV

100

CdnF)

FIGURE9. LOWTOHIGHTRANSIENTRESPONSEWAVEFORMS
(CL 10nF)

=

FIGURE 10. RISE AND FALL TIMES vs CL (V+ = 12V, 15V, 20V)

70
+10

~

....

::>s;-

~-

~

\

~~

0

0

--

1=

........
i!l

'\

+10

60

w
:Ii 50

\

0

....
::>

....E.

TR

40

~

30

V

TOR

~ 20

\

l.--""

•

ui

~

\V

10

TF

TOF

o
-40

·20

0

50nsJDIV

FIGURE 11. HIGH TO LOW TRANSIENT RESPONSE WAVEFORMS
(C L 10nF)

=

+25

+55

+85

TEMPERATURE (OC)

FIGURE 12. RISE, FALL AND DELAY TIMES VB TEMPERATURE

1.3

1.2

v~

...

~ 1.1
:Ii

w

)/

1=

~

1.0

:Ii

SlZ

0.9

:E
0.8

w 2.0
:Ii

"

~

I
I

I
.2_

1=

TOR~)

II:

TOR (+25°C)

o

~ 1.5
:Ii

V

./
!

Z

!i
c

./

~ 1.0

~

,,"'"

!!iz

V

./

V

/'

~

0.5

0.7
1

10

100

-50

CAPACITIVE LOAD (nF)

FIGURE 13. MINIMUM OFF TIME croAl vs CL AT +2SoC

0

+25

+50

+100

+150

JUNCTION TEMPERATURE rC)

FIGURE 14. NORMALIZED MINIMUM OFF TIME croAl vs TEMPERATURE (CL 10nF)

=

3·26

HV400
Typical Performance

~urves TA = +25°C Unless Otherwise Specified (Continued)

01

~ 10.2

....
Z

I

W

II:
II:

1/

~

10

...07

01,07

I'

/

I

::>
0

10~

- -

~
J

10-6

o

0.4

In

0.1
0.8

1.2

1.6

lN914

D4
IIJjI

1/'"
10

2.0

100

1000

FORWARD CURRENT (mA)

VF(V)
FIGURE 15. DIODE 01 AND 07 CURRENT V5 VF

FIGURE 16. DIODE ORR V5 FORWARD CURRENT

8

/

7
6
~ 5

~ 4

-

~

VIH

3

2

o

2

/

700

V /

600

/

/

3

1

400

j

200

/

4

500

300

/

-'

IIHP

o

V

I

100

o
5

6

ioP8(A)
Vertical
Horizontal

l00mAldlv
50nsldlv

FIGURE 17. DIODE 01 REVERSE RECOVERY WAVEFORM
IF = 200mA, 20V REVERSE BIAS

FIGURE 18. VIH AND IIHP V5 IOP8 [Vour (PIN 8)
1115 PULSE]

3·27

=0, V+ =15V,

HV400MJ/883
High Current MOSFET Driver

April 1994

Features

Description

• This Circuit Is Processed In Accordance to MII·Std883 and Is Fully Conformant Under the Provisions
of Paragraph 1.2.1.

The HV400MJ/883 is a Single monolithic, non-inverting high
current driver designed to drive large capacitive loads at high
slew rates. The device is optimized for driving single or parallel
connected N-channel power MOSFETs with total gate charge
from 5nC to >1000nC. It features two output stages pinned out
separately allowing independent control of the MOSFET gate
rise and fall times. The current sourcing output stage is an NPN
capable of 6A. An SCR provides over 30A of current sinking.
The HV400MJ/883 achieves rise and fall times of 54ns and
16ns respectively driving a 10,OOOpF load.

• Fast Fall Times .••••••••••••••• 16ns 811 O,OOOpF
• No Supply Current In Quiescent State
• Peak Source Current ••••.•••••••••••••••••• 6A
• Peak Sink Current ........................ 30A
• High Frequency Operation ....•......••• 300kHz

Special features are included in this part to provide a simple,
high speed gate drive circuit for power MOSFETs. The
HV400MJ/883 requires no quiescent supply current, however,
the input current is approximately 15mA while in the high state.
With the internal current steering diodes (Pin 7) and an external
capacitor, both the timing and MOSFET gate power come from
the same pulse transformer; no special external supply is
required for high side switches. No high voltage diode is
required to charge the bootstrap capacitor.

Applications
• Switch Mode Power Supplies

• DCIDC Converters
• Motor Controllers
• Unlnterruptible Power Supplies

The HV400MJ/883 in combination with the MOSFET and pulse
transformer makes an isolated power switch building block for
applications such as high side switches, secondary side regulation and synchronous rectification. The HV400MJ/883 is also
suitable for driving IGBTs, MCTs, BJTs and small GTOs.

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

HV400MJ/883

-55°C to +125°C

The HV400MJ/883 is a type of buffer; it does not have input
logic level switching threshold voltages. This single stage
design achieves propagation delays of 20ns. The output NPN
begins to source current when the voltage on Pin 2 is approximately 2V more positive than the voltage at Pin 8.

PACKAGE
8 Lead Ceramic
SBDIP

The output SCR switches on when the input Pin 2V is 1V more
negative than the voltage at Pins 3/6. Due to the use of the SCR
for current sinking, once the output switches low, the input must
not go high again until all the internal SCR charge has dissipated, 0.51ls - 1.51ls later.

Pinout

OS

Schematic

HV400MJ1883 (SBDIP)
TOP VIEW

V+ SUPPLY

c>--_-~
"-~"~-_---_l(
.
-,J

PIN 2

03

0'1

INPUT 2

7

DIODES

6

SINK OUTPUT

~ 01

02

PIN 8

SOURCE OUTPUT

SINK OUTPUT 3
GNO 4

PIN 1

~ PIN7
PIN3

PIN 6
04

S GNO

~Ir

R4

.....

......

~

r.)Q2 os

r
R3

_II-

D6

fR2
SCR

_~

07

}
R1
PINS

PIN 4
CAUTION: These devices are sensitive to electrostatic discharge. Users should Iollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

3-28

File Number

3584.1

Specifications HV400MJ/883
Absolute Maximum Ratings

Thermal Information

Voltage Between Pin 1 and Pins 415 ..................... 35V
Input Voltage Pin 7 (Max) ......•..........••..... Pin 1 + 1.5V
Input Voltage Pin 7 (Min) ....................... Pin 4/5 -1.5V
Input Voltage Pin 2 to Pin 415 . ....................... .+1- 35V
Input Voltage Pin 2 to Pin 6 ............................ -35V
Maximum Clamp Current (Pin 7) ........•...............±300mA

Thermal Resistance
8JA
8JC
Sidebrazed DIP. . . . . . . . • . . . • . . . . . . .
91°CNI
25°CNI
Power Dissipation at TA = +25°C ........•......•....... 2.33W
Operating Temperature Range
HV400MJ/883 . . . . . . . . . . . . . . . . . . . • . . . -55°C < TA < +125°C
Maximum Junction Temperature .........•....•....... +200oC
Storage Temperature Range .......•...... -65°C < TA < + 150°C

CAUTION: Stresses abo... those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions abo... those indicated in the operational sections of this specification is not implied.

Recommended Operating Conditions
Operating Temperature Range ........•.....•• -55°C to +125°C
Operating Supply Voltage •••••..•••...•••.•.•.• + 1OV to +35V
TABLE 1_ DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: Supply Voltage = + 15V, Unless Otherwise Specified
GROUP A
PARAMETERS

SYMBOL

CONDITIONS

SUBGROUP

TEMPERATURE

MIN

MAX

UNITS

Input High Differential Voltage (Pin 2 - Pin 8)

VIH

VOUT = OV, lOUT HI = 10mA

1

+25°C

0.6

2.8

V

2

+125°C

0.1

2.3

V

3

-55°C

1.0

3.2

V

1

+25OC

-1.1

-0.8

V

2

+125°C

-0.95

-0.6

V

3

-55°C

-1.2

-0.9

V

1

+25°C

15.0

20.0

rnA

2

+125°C

13.0

18.0

rnA

3

-55°C

18.0

25.0

rnA

1

+25°C

-80

0

I1A

2,3

+125°C, -55°C

-80

0

I1A

1

+25°C

12.1

13.4

V

2

+125°C

12.2

13.5

V

3

-55°C

11.0

13.0

V

1

+25°C

0

50

I1A

2,3

+125°C, -55°C

0

60

IIA

Input Low Differential Voltage (Pin 2 - Pin 3/6)

Input High Current

Input Low Current

High Output Voltage

Output Low Leakage

Low Output Voltage

Output High Leakage

Forward Voltage

Reverse Leakage Current

VIL

IIH

IlL

VOH

IOL

VOL

IOH

VF

IR

VOUT= 12V,
lOUT LO = -3mA

VPIN1.2=30V,
I SOURCE = 0

VPIN 2 = -30V

VIN = +V,IOUT = 150mA

VOUT = OV, VIN = OV

VIN = OV,louT = -150mA

VIN = 15V

10 = l00mA

VR =30V

3-29

1

+25OC

0.8

1.0

V

2

+125°C

0.65

0.85

V

3

-55°C

0.9

1.1

V

1

+25°C

0

2.0

I1A

2

+125°C

0

100

I1A

3

-55°C

0

2.0

I1A

1

+25°C

0.8

1.4

V

2

+125°C

0.8

1.25

V

3

-55°C

0.8

1.6

V

1

+25 C

-1.0

1.0

IIA

2,3

+125°C, -55°C

-1.0

1.0

I1A

O

Specifications HV400MJ/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
This Table Intentionally Left Blank. See AC Parameter on Table 3.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: Supply Voltage =±15V, Unless Otherwise Specified
PARAMETERS

SYMBOL

CONDITIONS

TEMPERATURE

MIN

MAX

UNITS

Input High Current fPeak

IIHP

ISOURCE = 6A, 11lS Pulse, VIN = 9V,
VOUT=OV

+25°C

500

900

rnA

Peak Output Current

IOP8

VIN = 9V, 11lS Pulse, VOUT = 0

+25OC

4

8

A

Peak Output Current

loPa

VIN = 9V, 11lS Pulse, VOUT = 0

+25°C

25

35

A

ORR

10= 100rnA

+25°C

6

7

nC

See Switching Diagram and Test Circuit

+25°C

37

62

ns

21

ns

13

ns

Diode (Pin 7) Stored Charge
Rise Time

TR

Fall Time

TF

See Switching Diagram and Test Circuit

+25°C

14

Delay TIme (Lo to Hi)

TOR

See Switching Diagram and Test Circuit

+25°C

6

Delay Time (HI to Lo)

TOF

See Switching Diagram and Test Circuit

+25 C

7

16

ns

Minimum Off Time

TOR

See Switching Diagram and Test Clrcult

+25°C

400

1140

ns

O

NOTE:
1. Switching times are guaranteed but not tested.

TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-SS3 TEST REQUIREMENTS

SUBGROUPS (SEE TABLES 1 AND 2)

Interim Electrical Parameters (Pre Burn-IN)

1,

Final Electrical Test Parameters

1 (Note 1),2

Group A Test Requirements

1,2

Groups C and D Endpoints

1,

NOTE:
1. PDA applies to Subgroup 1 only. No other subgroups are Included In PDA.

3-30

Specifications HV400MJI883
Test Descriptions
SYMBOL

DESCRIPTION

DC INPUT PARAMETERS
VIH

The differential voltage between the input (pin 2) to the output (pin 8) required to source 10mA

Vil

The differential voltage between the input (pin 2) to the output (pins 3, 6) required to sink 3mA

IIH

The current required to maintain the input (pin 2) high with lOUT =OA

IIHP

The input (pin 2) current for a given pulsed output current

III

The current require to maintain the input (pin 2) low

DC OUTPUT PARAMETERS

=V+

VOH

The output (pin 8) voltage with input (pin 2)

IOP8

The pulsed peak source current form output (pin B)

10l

The output (pin 8) leakage current with Ihe input (pin 2)

VOL

The output (pins 3, 6) voltage with the input (pin 2)

IOP6

The pulsed peak sink current into output (pins 3, 6)

10H

The output (pins 3, 6) leakage current with the input (pin 2)

VF

The forward voltage of diode 01 or 07

IR

The reverse leakage current of diode 01 or 07

QRR

=Ground

=Ground
=V+

The time integral of the reverse current at turn off

AC PARAMETERS (See Switching Time Specifications)
TA

The low to high transition of the output

TF

The high to low transition of the output

TOR

The output propagation delay from the input (pin 2) rising edge

TOF

The output propagation delay from the input (pin 2) falling edge

TOA

The minimum time required after an output high to low transition before the next input low to high transition

3·31

HV400MJ/883
Switching Diagram and Test Circuit
INPUT

10%

OV _....;1.;,O%;;..J'r
VOUT

TOR
90%

OUTPUT

C1
330~F

SOV

T

V

r------------.-------------1

1N914

T C21.0~F
V SOV

7 :

··
·

2 :

•
••

15V -------~
GND --- - /
'-INPUT
SOOSOURCE
(RISE AND FALL TIMES <10na)

..r-\.: 12.8V

:
:
:
:
:

O.9V
RL
100K

•

OUTPUT

••
•

·

4 !.. ____________________________ .!

HV400MJ/883 Switching Test Circuit
J1

R1

~

flE-------

C2

4.2 •

U1

Parts List

T
1

R1 1000. 1W Carbon Resistor

C L O.Q1~F. 50V Chip Capacitor

o

o

PULSE
IN

3.5 •

J1

HV400

o

IN

'~"g@!!i!
Ui

HV400

OUT

GNDG)

HV400 AC TEST BOARD

o

R2 Wire

D1 1N914 Diode

RL 100ko, 1/8W Carbon Resistor

J1. J2 PC Mount Banana Jack Johnson 108-0740-001

C1 330~F, 50V Capacitor

J3. J4 PC Mount SMA Connector Johnson EFJ142

C2 1~F. 50V Capacitor

U1 Harris HV400MJ/8831.C.

3-32

HV400MJI883
Burn-In Circuit (Dynamic)
V3

0-_-..,..----1---1

Fx o--H~....I

V2

R1

R2
C1
O.01I'F

V1

O--;--;-~~-----T----~

NOTES:
1.
2.
3.
4.
5.
6.
7.
B.
9.
10.
11.

Rl = lOOn, 5%, 1/4W.
R2 = 50, 5%, 2W.
R3 = 1000, 5%, 2W.
Cl = O.OlJ.lF, 10%, 3OV.
C2 = O.OOlJ.lF, 10%, 30V.
C3, C4, C5 = O.lJ.lF, 20%, 50V.
Vl = -15.5V, ± 0.5V.
V2 = -5.5V, ± 0.5V.
V3 = +5.5V, ± 0.5V.
Ql, Q2 = SK9505 or Equivalent. (One Pair Per Board Column)
Fx= 12.5kHz, 50% Duty Cycle.
V 1L = O.BV (Max)
V1H = +4V (Min)

3-33

I. .'
C3

HV400MJ/883

Metallization Topology
DIE DIMENSIONS:
1700 x 1820 x 483ltm

GLASSIVATION:
Type: Silox
Thickness: 12kA ± 2kA
Type: Nitride
Thickness: 3.5kA ± 2.5kA

METALLIZATION:
Type: 1% Cu, 9!i1% AI
Thickness: 16kA ± 2kA

TRANSISTOR COUNT: 3

SUBSTRATE POTENTIAL (POWERED UP):
Unbiased

PROCESS: HFSB Linear Dielectric Isolation

WORST CASE CURRENT DENSITY:
8.2 x 104 Alcm 2 during 1its pulse with ·35A output current,
through 8~ wide line 14kA thick.

Metallization Mask Layout
HV400MJ1883

wI-

wI-

()::)

a:

()::)

a:

II.

II.

::)1-

::)1-

e:

e:

g8

0::)
",0

V+(1)

INPUT (2)

(7) DIODES

(6) SINK OUTPUT

SINK OUTPUT (3)

GROUND (4)

(5) GROUND

3·34

HV400MJ

I-IARRIS
SEMICONDUCTOR

DESIGN INFORMATION
High Current MOSFET Driver

April 1994

The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied.

Circuit Operation
The HV400MJ/883s operation is easily explained by referring to the schematic. The control signal is applied to Pin 2. If
the control signal is about 2V above Pin 8, the output NPN
01 turns on charging the MOSFET gate from a capacitor
connected to Pin 1. Resistor R4 helps keep the SCR off by
applying a reverse bias to the SCR anode gate.
When the control input drops about 1V below Pin 3/6, PNP
02 turns on which triggers the SCR by driving both the
anode and cathode gates. The SCR discharges the
MOSFET gate and when its current becomes less than
10mA, it turns off. Transistor 02 conducts any gate leakage
currents, through resistors R1 and R2, once the SCR turns
off. Figure 7 shows the output characteristics before the
SCR turns on and after it turns off. When the SCR turns on,
resistor R4 provides a path to remove 01 base charge.
Resistor R3 provides the base current for 02 to reduce the
turn off delay time. Resistors R1 and R2 reduce the SCR
recovery time.
The two diodes connected to the diode input Pin 7 provide
some operation flexibility. With Pins 2 and 7 connected
together, diode D1 provides a path to recharge the storage
capacitor once the MOSFET gate is pulled high and, along
with diodes D2 and D3, keeps 01 from going into hard
saturation which would increase delay times. Diode D7
would clamp the input near ground and provide a current
path if an input DC blocking capacitor is used.
Alternatively, Pin 7 can be connected to Pin 6 so that the
SCR and NPN 01 don't have to pass reverse current if the
output "rings" above the supply or below ground. When high
performance diodes are required, Pin 7 can be left
disconnected and external diodes substituted.
The diodes in series with Pin 2 decouple the input from the
output during negative going transitions. The absence of
input current turns off 01 and allows 02 to trigger the SCA.
Diode D8 turns off 02 once the SCR turns on pulling the output low, otherwise 02 would saturate and slow down circuit
operation. In addition, the diodes D2, D3 and D8 improve
noise immunity by adding about 2.5V of input hysteresis.
The HV400MJ/883 is capable of large output currents but
only for brief durations due to power diSSipation.
Circuit Board Layout
PC board layout is very important. Pins 3 and 6 should be
connected together as should Pins 4 and 5. Otherwise the
internal interconnect impedance is doubled and only half of
the bond wires are used which would degrade the reliability.

The bootstrap capacitor should hold at least lOx the charge
of the MOSFET and should be connected between Pins 1
and 4/5 with minimum pin lengths and spacings. Likewise,
the HV400MJ/883 should be as close to the MOSFET as
possible. Any long PC traces (parasitic inductances)
between the MOSFET gate and Pins 8 or 3/6 or between the
source and Pins 4/5 should be avoided. Inductance between
the HV400MJ/883 and the MOSFET limit the MOSFET
switching time. If they are too large, the HV400MJ/883 may
operate erratically as discussed below.
Cross Conduction Faults
It is possible to have both 01 and the SCR on at the same
time resulting in very large cross conduction currents. The
SCR has larger current capacity so the output goes low and
the storage capacitor is discharged. The conditions that
cause cross conduction and precautions are discussed
below.
Minimum Off Time
The SCR requires a recovery time before voltage can be
reapplied without it switching back on. Figure 13 shows how
this SCR recovery time, called "minimum off time" (TOR)' is a
function of the load capacitance. If the input voltage goes
high before this recovery time is complete, the SCR will
switch back on.
Note that reverse current flowing through the SCR, for
example due to load inductance ringing, extends the
minimum off time. Since the minimum off time is really
dependent upon how much stored charge remains in the
SCR when the anode (Pin 3/6) is taken positive, it may vary
for different applications. Figure 13 indirectly shows that the
minimum off time increases with larger currents. It also
increases at elevated temperatures as shown in Figure 14.
Excessive ringing increases the minimum off time since the
stored charge doesn't begin to dissipate until the current
drops below 10mA for the last time. Rising anode voltage
acts on the internal SCR capacitance to generate its own
triggering current. The excess stored charge increases this
capacitance. Faster rise times and/or higher voltages also
increase the amount of internal trigger current from the internal capacitance so applications with larger dV/dt require
longer minimum off times.
The minimum off time must be considered for all occurrences of SCR current. For example, in a half bridge switch
mode power supply, there are two MOSFETs connected to
the transformer primary. Assume that the high side MOSFET
switch is off. When the low side MOSFET switch is turned

3-35

HV400MJ

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design informiation only. No guarantee is implied.
on, the HV400MJ/883 driving the high side MOSFET will
have to sink gate current from C GO and will have to source
gate current when the low side MOSFET switches back off.
Both of these current pulses will try to flow through Pin 3/6
since the Pin 8 output is turned off. Sourcing current from
Pins 3/6 through the SCR is possible, the Pin 3/6 voltage
becoming negative with respect to Pins 4/5 (See Figure 8).
But a better practice would be to connect a Schottky diode
between Pins 4/5 (anode) and 3/6 (cathode) so reverse current does not flow through the SCR.
False SCR Triggering
The SCR may be triggered inadvertently. The output may
overshoot the input due to inductive loading or over driving
the output NPN (allowing it to saturate). Whenever Pin 6 is
more positive than Pin 2 by 1V, the SCR is triggered on.
Also, if the output rises too rapidly, greater than 0.5V/ns, the
SCR may self trigger. Both issues are resolved by minimizing the load inductance and inserting sufficient resistance,
usually 0.10 to 100, between Pin 8 and the load.
A very fast negative going input voltage can result in minimum
off times of about 2.5I1S. If the output can not keep up with the
falling input, the stored charge of diode D4 is transferred into
the base of 02. This excess charge in 02 must have time to
dissipate. Otherwise, when Pin 3/6 goes positive, Q2 will turn
on and trigger the SCR. An external diode in series with Pin 2,
as shown in Figure 1, will prevent D4 from discharging into the
base of 02 but that will also reduce the output voltage by the
forward voltage of that diode.

then some of the power is dissipated in the resistors, the percentage depending upon the ratio of resistors to HV400MJI
883 output impedance.
There are two other sources of power dissipation to
consider. First there is the power in R3 which is the product
of the input Pin 2 current and voltage (with no output current)
times the duty cycle. Second is the product of the Pin 7
diode stored charge, which is dependent upon the forward
current, times the applied diode reverse voltage times the
frequency. This information is available from Figure 3 and
Figure 16 in this data sheet.
Applications Circuits
The HV400MJ/883 was designed to interface a pulse transformer to a power MOSFET. There must be some means to
balance the transformer volt-second product over a cycle.
The unipolar drive shown in Figure 1 lets the core magnetization inductance reverse the primary and secondary voltages. The zener diode on the primary side limits this voltage
and must be capable of dissipating the energy stored in the
transformer. The load may be connected to either the power
MOSFET drain or source.

vs

7,·..···....·······..··..·..··..··..···....·11
cs

Internal Diodes
The internal diodes connected to Pin 7 are provided for
convenience but may not be suitable for large currents. Since
they are part of the integrated circuit, they are physically
small, operate at high current densities, and have long recovery times. Figure 15 shows that their forward characteristics
degrade above 100mA. In addition, Figure 16 shows their
reverse recovery charge as a function of forward current. The
product of this charge, the applied reverse voltage and the frequency is the additional power dissipation due to the diodes.
For stored charge calculations, use the peak forward current
within 100ns of the application of reverse bias. In addition to
the extra power dissipation, the capacitance of these diodes
may extend the switching delay times.
Power Dissipation Calculations
The power required to drive the MOSFET is the product of
its total gate charge times the gate supply voltage (maximum
voltage on HV400MJ/883 Pin 1, 2 or 7) times the frequency.
Assuming that the MOSFET gate resistance is negligible,
this power is dissipated within the HV400MJ/883. If resistors
are placed between the HV400MJ/883 and the MOSFET,

4 •...... •.. •.... •.. •............ •• .. •.. •....··5 POWER
HV400MJ/883
MOSFET

FIGURE 1. UNIPOLAR DRIVE
A diode is added in series with Pins 2 and 7 to allow the
transformer secondary to go negative. The charge storage of
the Pin 7 diode may cause the turn off delay time to be too
long. Alternatively, Pin 7 could be left disconnected and a
second external diode connected between the transformer
(anode) and Pin 1 (cathode). In some applications the diode
in series with Pin 2 may be unnecessary but the -35V input
to output or ground maximum rating should be observed.
Sometimes the volt-second balance is achieved by a push-pull
drive on the pulse transformer primary. This is especially useful
if there are two secondary windings driving two HV400MJ/883s
out of phase such as in a ha~-bridge configuration.

3-36

HV400MJ

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application
and design informiation only. No guarantee is implied.

Other times it is more convenient to achieve volt-second
balance by using capacitors to block DC in the primary and
secondary windings as shown in Figure 2. The Pin 7 diodes
provide a path for discharging the secondary side DC blocking capacitor. Both capacitors, CIN and Cs, should be at
least 10 times the equivalent MOSFET gate capacitance.

7

1

II

The HV400MJ/BB3 can be used as a current booster for low
side switches by connecting directly to the PWM output. The
circuit would be similar to the switching time test circuit.

It is worth restating that some consideration (and experimentation) should be given to the choice of external components,
i.e. resistors, capacitors and diodes, to optimize
performance In a given application.

r·················;,:····························..·t

T1

4 : •••••••••••••••••••••••••••••••••••••••••••••••••••; 5
HV400MJ/883

FIGURE 2. BIPOLAR DRIVE WITH DC BLOCKING CAPACITOR

3-37

ICL7667
Dual Power MOSFET Driver

April 1994

Features

Description

• Fast Rise and Fall nrnes
- 30ns with 1000pF Load

The ICL7667 is a dual monolithic high·speed driver
designed to convert TIL level signals into high current
outputs at voltages up to 15V. Its high speed and current
output enable it to drive large capacitive loads with high slew
rates and low propagation delays. With an output voltage
swing only millivolts less than the supply voltage and a
maximum supply voltage of 15V, the ICL7667 is well suited
for driving power MOSFETs in high frequency switchedmode power converters. The ICL7667s high current outputs
minimize power losses in the power MOSFETs by rapidly
charging and discharging the gate capacitance. The
ICL7667s input are TIL compatible and can be directly
driven by common pulse-width modulation controllCs.

• Wide Supply Voltage Range
- Vee = 4.SV to 15V
• Low Power Consumption
- 4mW with Inputs Low
- 20mW with Inputs High
• TIUCMOS Input Compatible Power Driver

- ROUT = 70 lYP
• Direct Interface with Common PWM ControllCs
• Pin Equivalent to DS00261OS0056; TSC426

Typical Applications

Order Information

• SwHchlng Power Supplies
• DCIDC Converters
• Motor Controllers

PART NUMBER

TEMPERATURE
RANGE

PACKAGE

ICL7667CBA

O"C to +70"C

8 Lead SOIC (N)

ICL7667CPA

O"C to +70"C

8 Lead Plastic DIP

ICL7667CJA

O"C to +70"C

8 Lead Ceramic DIP

ICL7667CTV

O"C to +70"C

8 Pin Metal Can

ICL7667MTV (Note 1)

-55°C to +125°C

8 Pin Metal Can

ICL7667MJA (Note 1)

-55°C to +125°C

8 Lead CerDIP

NOTE: 1. Add 1883B to Part Number for 883B Processing

Pinouts

Functional Diagram
ICL7667 (CAN)
TOP VIEW

v~~

__

~~

______

~~

______

~

v+

OUT

ICL7667 (PDIP, SOIC, CERDIP)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation t 994

3-38

File Number

2853.2

Specifications ICL7667
Absolute Maximum Ratings

Thermal Information

Supply Voltage v+ to v- ......•.......••.•.•.•......••. 15V
Input Voltage......•••....•••••..•.••••• v- -O.3V to v+ +O.3V
Package Dissipation. TA +25°C •....•.•••••...••••••• SOOmW

Thermal Resistance

8JA

8JC

PDIP Package. . . . . . . . . . . . . . . . . .. 15fiJCNI
sale Package................... 17fiJCIW

-

Metal Can Package. • • • • . • • . • • • • •. 156"CIW
68°CIW
CerDIP Package. . . . . . • . • . • • • . . •. 1150CJW
3O"CJW
Storage Temperature Range •..••••••.•••.•••• -65°C to + 15O"C
Lead Temperature (Soldering I Os) •.••.••.•....••••••• +300oC
(SOIC - Lead TIps Only)
CAUTION: Stresses above those listed in "'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational SlJCtions of this specification is not implied.

Operating Temperature Range
ICL7667C .....................•......•••.. O"C to +70°C

ICL7667M .•.....•••.....••••....••••.•• -55OC to +125°C

Electrical Specifications

PARAMETERS

SYMBOL

TEST CONDITIONS

ICL7667C. M

ICL7667M

T"= +25°C

-55°C:s; T,,:s; +125°C

MIN

TVP

MAX

MIN

-

2.0

TYP

MAX

UNrrS

-

-

V

0.5

V

0.5

V

0.1

IJA

Vee

-

V

-

0.1

V

12
13

n
n

DC SPECIFICATIONS
Logic I Input Voltage

V IH

Vee = 4.5V

2.0

Logic I Input Voltage

VIH

Vee = 15V

2.0

-

Logic 0 Input Voltage

V IL

Vcc= 4.5V

Logic 0 Input Voltage

VIL

Vee = 15V

Input Current

IlL

Vee = 15V. VIN = OV and 15V

-0.1

VOH

Vec=4.5Vand 15V

Vee
-0.05

VOL

Vee = 4.5V and 15V

Output Voltage High
Output Voltage Low

-

Output Resistance

RoUT

VIN = VIL.loUT = -IOmA. Vec = 15V

Output Resistance

RoUT

VIN = VIH • lOUT = 10mA. Vcc = 15V

Power Supply Current

Icc

Vee = 15V. VIN = 3V both inputs

Power Supply Current

Icc

Vcc = 15V. VIN = OV both inputs

-

-

0.8

2.0

-

0.8

-

0.1

-0.1

Vcc

-

0

0.05

7

10

8

12

5

7

150

400

35

50

20

30

20

30

20

30

Vee
-0.1

-

-

-

-

V

8

mA

400

IJA

60

ns

SWITCHING SPECIFICATIONS
Delay Time

T02

Figure 3

Rise Time

TR

Figure 3

FaUTIme

TF

Figure 3

Delay TIme

TOI

Figure 3

-

NOTE: All typical values have been characterized but are not tested.

Test Circuits
+5V

INPUT
-O.4V

15V

INPUT RISE AND
FALL TIMES ';IOna

OUTPUT
OV

3-39

-

-

40

ns

40

ns

40

ns

1&1(1)
01&1

-:e

~g

~~
:e(l)

ICL7667
Typical Performance Curves
100

iI'S
VCC=lSV

...S
.z

100

I-

0

~RISEI

~

.r:

10

./

I

I

I

I

/

I

I

...
.s

~
e
z

"~

80

Vcc=15YI

70
60

TD2

50

.-...r--

40
30
20

{FAI
10

I
CL=lnF -

90

~

100

1000

10K

o

lOOK

o

·55

+25
70
TEMPERATURE (oC)

FIGURE 1. RISE AND FALL TIMES vs CL

FIGURE 2. T Dl. T D2 vs TEMPERATURE

50

30

II

Vcc· 1SV
40
TR AND TF...............

.
e

30

.r:

20

l-

~

~

-

10

CL - (pF)

...S

TDI

~

-

~

v-----

200:~ V
10

r--

CL=lnF
Vec= 15V

I--"'"
~

+125

1I

~I'
20kHz

3.0
10

o
-55

0
+25
70
TEMPERATURE rC)

10

+125

:c

!.

I-_ _ _+

___

lK

10K

lOOK

CL(PF)

FIGURE3. T R• TFvsTEMPERATURE

100

100

FIGURE 4. Icc VS C L

100

-+_~--I

10 I-----+-..."....c..-f.~:..--_I

10

lOOI'A '--_ _ _-'-_ _ _-1.._ _ _---'

100mA

Jl

10k

lOOk

1M

10M

10k

FREQUENCY (Hz)

lOOk

1M

FREQUENCY (Hz)

FIGURE 5. Icc VS FREQUENCY

FIGURE 6. NO LOAD Icc vs FREQUENCY

3-40

10M

I

ICL7667

I

Typical Performance Curves (Continued)
50

50

....s

~
l-

40

30

ez

C

20

:P

10

"'- "-

...
.s
!o-

-

TF

~
e

30

C

20

z

-

TOI

Vee -(V)

..........

TR= T02

-

10
CL= 10pF

CL=1nF
10

~

~

0

0
5

40

5

15

FIGURE 7. DELAY AND FALL TIMES vs Vee

10 Vee (V)

15

FIGURE 8. RISE TIME vs Vee

Detailed Description
The ICL7667 is a dual high-power CMOS inverter whose inputs
respond to TTL levels while the outputs can swing as high as
15V. Its high output current enables ~ to rapidly charge and discharge the gate capacitance of power MOSFETs, minimizing
the switching losses in switchmode power supplies. Since the
output stage is CMOS, the output will swing to w~hin millivofis
of both ground and Vee without any external parts or extra
power supplies as required by the OSOO26156 family. Atthough
most specifications are at Vee = 15V, the propagation delays
and specifications are almost independent of Vee.
In addition to power MOS drivers, the ICL7667 is well suited
for other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where
the load capacitance is large and low propagation delays are
required. Other potential applications include peripheral
power drivers and charge-pump voltage inverters.
Input Stage
The input stage is a large N-channel FET with a P-channel constant-current source. This circuit has a threshold of about 1.5V,
relatively independent of the VCC vottage. This means that the
inputs will be directly compatible with TTL over the entire 4.5V 15V Vee range. Being CMOS, the inputs draw less than 11lA of
current over the entire input voltage range of ground to Vee.
The quiescent current or no load supply current of the ICL7667
is affected by the input voltage, going to nearly zero when the
inputs are at the 0 logic level and rising to 7mA maximum when
both inputs are at the 1 logic level. A small amount of hysteresis, about 50mV to 100mV at the input, is generated by positive
feedback around the second stage.
Output Stage
The ICL7667 output is a high-power CMOS inverter, swinging
between ground and VCC. At Vee = 15V, the output impedance of the inverter is typically 70.. The high peak current
capability of the ICL7667 enables it to drive a 1000pF load
with a rise time of only 40ns. Because the output stage impedance is very low, up to 300mA will flow through the series Nchannel and P-channel output devices (from Vee to ground)
during output transitions. This crossover current is responsible

for a significant portion of the internal power dissipation of the
ICL7667 at high frequencies. It can be minimized by keeping
the rise and fall times of the input to the ICL7667 below 11lS.

Application Notes
Atthough the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be paid.
Grounding
Since the input and the high current output current paths
both include the ground pin, it is very important to minimize
and common impedance in the ground return. Since the
ICL7667 is an inverter, any common impedance will
generate negative feedback, and will degrade the delay, rise
and fall times. Use a ground plane if possible, or use
separate ground returns for the input and output circuits. To
minimize any common inductance in the ground return,
separate the input and output circuit ground returns as close
10 the ICL7667 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.71lF
tantalum capacitor in parallel with a low inductance 0.11lF
capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
1. Reduce inductance by making printed circuit board traces
as short as possible.
2. Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3. Use a 100. to 300. resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly
increase the rise and fall times.

3-41

4. Use good bypassing techniques to prevent supply voltage
ringing.

ICL7667
Power Dissipation
The power dissipation of the ICL7667 has three main
components:
1. Input inverter current loss

significant amounts of power. The very high current output of
the ICL7667 is able to rapidly overcome this high capacitance and quickly turns the MOSFET fully on or off.
18

2. Output stage crossover current loss

16

3. Output stage 12R power loss

w

The sum of the above must stay within the specified limits for
reliable operation.

"~

14

As noted above, the input inverter current is input voltage
dependent, with an Icc of 0.1 mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.

w
(,)
ex:

10

I/)

6

The output stage crowbar current is the current that flows
through the series N-channel and P-channel devices that
form the output. This current, about 300m A, occurs only during output transitions. Caution: The inputs should never be
allowed to remain between V1L and V1H since this could leave
the output stage in a high current mode, rapidly leading to
destruction of the device. If only one of the drivers is being
used, be sure to tie the unused input to a ground. NEVER
leave an input floating. The average supply current drawn by
the output stage is frequency dependent, as can be seen in
Icc vs Frequency graph in the Typical Characteristics
Graphs.
The output stage 12R power dissipation is nothing more than
the product of the output current times the voltage drop
across the output device. In addition to the current drawn by
any resistive load, there will be an output current due to the
charging and discharging of the load capacitance. In most
high frequency circuits the current used to charge and
discharge capaCitance dominates. and the power dissipation
is approximately

where C

PAC =CVcc2f
=Load Capacitance, f =Frequency

In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
ICL7667 power dissipation will be
PAC = OGVCCf

=

where OG Charge required to switch the gate, in Coulombs,
f Frequency.

=

Power MOS Driver Circuits
Power MOS Driver Requirements
Because it has a very high peak current output, the ICL7667
the at driving the gate of power MOS devices. The high
current output is important since it minimizes the time the
power MOS device is in the linear region. Figure 9 is a
typical curve of charge vs gate voltage for a power MOSFET.
The flat region is caused by the Miller capacitance, where
the drain-ta-gate capaCitance is multiplied by the voltage
gain of the FET. This increase in capacitance occurs while
fhe power MOSFET is in the linear region and is dissipating

g
:::>
0

g

I I

Voo= sov

12

8

w

4

"

2

!C

r- 1O=1A
f-,-I I

0
-2

I/
V, V

L J

2

4

i/

j
.\

I I

VOO= 200V

oJ 630pF

I I

~ ~12pr
o

I

II J
VI VVoo= 37SV

LV

r- ,.- 680pF

/.

'I

6

8

10

12

14

16

18

20

GATE CHARGE - Qo (NANO-COULOMBS)

FIGURE 9. MOSFET GATE DYNAMIC CHARACTERISTICS

Direct Drive of MOSFETs
Figure 11 shows interfaces between the ICL7667 and typical
switching regulator ICs. Note that unlike the 080026. the
ICL7667 does not need a dropping resistor and speedup
capaCitor between it and the regulator IC. The ICL7667, with
its high slew rate and high voltage drive can directly drive the
gate of the M08FET. The SG1527 IC is the same as the
SG1525 IC. except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer.
Transformer Coupled Drive of MOSFETs
Transformers are often used for isolation between the logic
and control section and the power section of a switching
regulator. The high output drive capability of the ICL7667
enables it to directly drive such transformers. Figure 11
shows a typical transformer coupled drive circuit. PWM ICs
with either active high or active low output can be used in
this circuit, since any inversion required can be obtained by
reversing the windings on the secondaries.

Buffered Drivers for Multiple MOSFETs
In very high power applications which use a group of MOSFETs in parallel, the input capaCitance may be very large
and it can be difficult to charge and discharge quickly. Figure
13 shows a circuit which works very well with very large
capacitance loads. When the input of the driver is zero, 01 is
held in conduction by the lower half of the ICL7667 and 02 is
clamped off by 01. When the input goes positive, 01 is
turned off and a current pulse is applied to the gate of 02 by
the upper half of the ICL7667 through the transformer, T1.
After about 20ns, T1 saturates and 02 is held on by its own
CGS and the bootstrap circuit of C1, D1 and R1. This bootstrap circuit may not be needed at frequencies greater than
10kHz since the input capacitance of 02 discharges slowly.

3-42

ICL7667

l5V

.n~

+V

+VC
A

ICL7667

SG1527

1 - IRF730

B

GND

-V

-

FIGURE 10A_

l5V

lK

+Vc

"~q-

+V

Cl
E1

-

Tl494

1-IRF730

C2

GND

W(/)
OW

-::t:
(/)0
::t:~

VOUT

~

E2

-

-

-V

lK

-

+15V

FIGURE 108.

FIGURE 10. DIRECT DRIVE OF MOSFET GATES

lav

CA

CB

+V

VIN
EA

-

CA1524

'1. ·

~

470

IRF730
: ::65V

ICL7667

EB
-165V

470

-

-V
VOUT

FIGURE 11. TRANSFORMER COUPLED DRIVE CIRCUIT

3-43

 - - - 2 4 AO

~25

BO

r-__N_M_O_S....,[:>o- 26 LO

r-______

~-r-21

pos

111 CPA
17 CPB

7
L 8

28 P+

23 GO

R 9
10

rr=;=~~~~= 20 REG
22 PO

15 REF

G 11
12

......___----.j__ 16 PCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

4-3

File Number

3691

Specifications HIP2030
Thermal Information

Absolute Maximum Ratings
Gate Channel Supply Voltage, VP+ to VPLogic Supply Voltage, VPO to VPAll Other Pin vottages
(A+, A-, Bl+, Bl-, 82+, 82-, L+, L-, R+, R-)
0

0

..

0

..

0

0

0

0

0

0

0

0

0

0

0

..

000

0

0

0

0

0

0

0

•••

0

-no5V to 32V
7V to 18V

..

(VP-)-Oo5 to {Vp+)+O.5

Thermal Resistance.
PLCC Package •••
Lead Temperature (Soldering 1Os)
Storage Temperature Range
Junction Temperature
0

..

0

..

0

0

0

0

000000000000000000

0

0

0

0

0

0

0

0

0

0

....

0

0

0

0

0

0

0

0

0

0

0

0

9JA
6O"CIW
+265°C
-4OOC to +15O"C
+125°C

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

....

0

0

0

0

0

0

0

0

0

0

0

0

0

0

..

0

CAUTION: Stressss aboWI those listed in "Absolulll Maximum Ratings" may cause permanent damage to th8 daviee. This Is a stnJss only fflting and op6ff1tion
of the device at th8se or any other conditions abo... those Indicated in th8 op6ffItionai sections of this specification is not impHed.

Recommended Operating Conditions (TJ = -40"C to +125°C Unless Otherwise Noted, All Vollages Referenced to VP-)
Gate Channel Supply Voltage, VP+ to VP-0.5V to 30V
Logic Supply Voltage, VPO to VP- ..... .. .. .. .. .. .. .... 10 to 15V
All Other Pin Vottages
(A+, A-, Bl+, Bl-, 82+, 82-, L+, L-, R+, R-) .•• (VP-)+2V to (VPO)+2V
0

0

0

0

0

0

0

0

0

•

0

•

Max Output Source Current, Channels A, B • . • • • • • • . •. 10mA
Max Output Sink Current, Channels A, L•.•••
10mA
Min Load Current, Ref to P-..................
2mA
0

••••••••

0

••••••

I

Static Electrical Specifications VPO to VP- = 15V, VP+ to VP- = 30V, VP- = OV and TJ = +25°C, Unless Otherwise Specified
TJ
SYMBOL

PARAMETER

TEST CONDITIONS

=+25°C

MIN

TYP

MAX

UNITS

-

2.75

-

rnA

-

3.5
3.0

-

mA

-

525

-

IIA

30

35

V

5

-

10PO

QUiescent VPO Supply

lapp

Quiescent Vpp Supply

VPP to VP- = 30V

1000s

Quiescent VPOS Supply

Osc Freq = 100kHz

IsWPO

VPO Switching Current

A, B, and G Input
Freq = 10kHz

Iswpp

VPP Switching Current

A, B, and G Input
Freq = 10kHz

BVpp

VPP-VPM Breakdown Voltage

VREG

Regulator VOltage, PO to Ref

IREF=2mA

-

RREG

Regulator Impedance, PO to Ref

IREF =10mA, 30mA

-

5

-

n

VClMP

Clamp Vollage, REG to P-

ICLMP = 15mA

Clamp Impedance, REG to P-

ICLMP = 15mA, 30mA

FQPMP

Charge Pump Frequency

100

-

V

RCLMP

-

12

kHz

OOPMP

Charge Pump Duty Cycle

50

-

%

28.5

-

V

27.5

-

V

-

1.5

15

IIA
mA

V

n

V~P

Charge Pump Your. VP+ to VP-

IP+=500pA

VOQPMP

Charge Pump Vour. VP+ to VP-

IP+=5mA

IIN cMP

Comparator input Leakage

VINcMP = VPOI2

-

10

-

nA

VOSCMP

Comparator offset Voltage

Vcm=VPOI2

-

15

VCMcMP

Comparator Common Mode Voltage
Range

(VP-)+2

RDSSRC

AO, SO Output RDS, Sourcing

ISRC= 10mA

RDS SRC

GO Output RDS, Sourcing

ISRc=6A

RDSSNK

AO, LO Output RDS, Sinking

ISNK= 10mA

RDSSNK

GO Output RDs, Sinking

IsRc=6A

4-4

-

mV

VPO+2

V

-

75

-

n

2

-

75

-

n

1

-

n

n

Specifications HIP2030
Dynamic Electrical Specifications

VPO to VP- =15V, VP+ to VP- =30V, VP- =OV, VIN- =7.5V, VIN+ =(VIN-) ± 2V and
TJ = +25°C, Unless Otherwise Specified
TJ

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

=+25°C
TYP

MAX

UNITS

-

ns

-

ns

-

ns

TGOH M1N

Min GO Output High Duration

MHTOpen

-

750

TGOLM1N

Min GO Output Low Duration

MLTOpen

1200

TP LH

Prop Delay, Low To High, Channels A, B

CLOAD =300pF

TP LH

Prop Delay, Low To High, Channel L

CLOAD =300pF

TP HL

Prop Delay, Low To High, Channel A

CLOAD

TRAB

Rise TIme, Channels A, B

CLOAD =300pF

TFAL

Fall TIme Channels A, L

CLOAD =300pF

TPLH

Prop Delay, Low To High, Channel G

CLOAD =60nF

-

TP HL

Prop Delay, High To Low, Channel G

CLOAD =60nF

-

300

TRG

Rise Time, Channel G

CLOAD =60nF

Fall TIme Channel G

CLOAD =60nF

-

250

TFAL

=300pF

100
120
150
50
50

150

200

ns
ns
ns
ns
ns

ns
ns

-

ns

HIP2030 Application Information
The Harris Photo-Coupled Isolated Gate Drive (HPCIGD)
circuit, illustrated in Figure 1, contains four subcircuits: a Single
Supply DC bias, a Regulated voltage divider reference, a Local
Energy Source Capacitance, and a Photo-Couple Receiver.
The Single Supply DC Bias Circuit, shown in Figure 1,
consists of a single external dropping resistor (R1) connected between pins P+ (U1-28) and PO (U1-22). When an
input voltage of30V is applied across pins P+ and P- (U116), R1 forms a resistive divider network with the input
impedance located between pins PO and P- (RVPO). This
allows the circuit designer to adjust the value of R1 to obtain
a desired bias voltage between pins PO and P- (VPO.). The
value of RVPO can be calculated by evaluating the equivalent Quiescent Input Impedance (RQ) and the SV reference
impedance (RR) as parallel resistances. The values for R1,
RQ, RR, and RVPO can be determined by using equations
1(A, B, C, D) as shown in appendix A, exercise 1.1.
The Regulated Voltage Divider Reference is comprised of
two resistors (R3 and R4) connected in series and are
located across pins PO and REF. This voltage divider provides a stable voltage reference to all of the HIP2030 comparator inputs. Resistors R3 and R4 are selected equal in
value to create a midpoint bias reference between the peak
to peak input signal of U2. Also, the midpoint bias method
ensures that input signals generated from U2 and midpoint
bias reference voltages are within a safe common mode voltage range of the comparators.
The Local Energy Source Capacitances, C2 and C3, are
needed to supply the charge required to drive large capacitance loads at high dV/dts. The HPCIGD circuit uses low
cost 'oversized" tantalum capacitors (C
10I1F) that are
used for C2 and C3. If rise times and overshoot are critical,

=

ceramic capacitors with low ESL and ESR should be used to
improve gate drive signals. In a power circuit, where the gate
driver is exposed to high dV/dts, the network of C2 and C3
directs noise current away from the HIP2030. This allows the
HFOIGD circuit to operate well in half bridge power circuits
that use a transfonner coupled power source.
The Photo-Coupled Receiver subcircuit consists of U2, RS,
C4, and R6. U2 is a photocoupler which combines an infrared emitter diode (IRED)and a high speed photo detector to
translate light pulses to low voltage input signals. These signals are routed to the G channel and are used to control the
output GO. Component RS is used to limit the DC current
through the IRED when the input signal voltage switches to
its most positive level. A wide range of input voltages may be
accommodated by varying RS to limit the IRED current to
2SmA. C4 is a speed up capacitor and is selected to match
the forward bias capacitance of the IR diode. The last component, R6, is an optional part and is intended to be a tennination resistor with the value set by the user.
The Harris HIP2030 Driver Board (HIP2030DB) is a printed
circuit board (PCB) developed to help evaluate the performance of the HIP2030 MCTIIGBT Driver IC in power switching circuits. The component layout of the HIP2030DB circuit
enables the user to conveniently populate the PCB for either
Photo-Coupled or fiber-optic receivers. In addition, the PCB
layout has provisions for ·on board prototyping" and special
function components. This facilitates the gate drive circuit
design and allows the user to exercise the intemal architecture and special functions of the HIP2030. The schematic of
the HIP2030DB, illustrated in Figure 2, uses the basic
HPCIGD circuitry and has provisions for ·on board prototyping" and special function components.

4-S

HIP2030
TABLE 1. LOGIC
INPUTS

1

OUTPUTS

G

L

R

LO

GO

0

0

0

LS

H

0

0

1

H

H

0

1

0

L

H

0

1

1

L

H

1

0

0

LS

U

1

0

1

H

L

1

1

0

L

H

1

1

1

L

H

=Input True

U = Undefined
LS Last State

o= Input False

=

+30V

B1· A+

JB1

/
B2·

4

3

2

A·
1

p+/NcIOL

28

27

26

•

5

B2+
>-- 6
L·
7
L+
8
R·
9

PO
22 ; - POS
21
REG
20
CPA
19

rrr-

2:.. 10
~11
13

1J I~

14

I~

15 16
II.

w

II!

17 18

cL

C2

R1

MOSGATE

23

U1
HARRIS
HIP2030
28 LEAD PLCC

12

';

OB

-OA
24 GO

25

U2 TLP2601
C1

2

R3

I~ I ~

3

-

R4

8

-.!..

4

~~ .~

7

R2
;;

C3

6

5

30V
COM
R5
PHOTO
COUPLER
SUBCIRCUIT

I

C4

"

I

+
R6

FIGURE 1. HARRIS PHOTO-COUPLED ISOLATED GATE DRIVE

4·6

5V
IN PUT
SI GNAL

HIP2030
Jl

P+~t-________~Ryl~__-,

G
MOSGATE

R12

"

10
R8

RO
820
PS
"" B2+

5

P7
.!.P6 L~k!>-~.HI-----I 7
PO

~

8

+-..J

HIP2030

~P8R'i' R+ 10

~OS

21··
REG JP
20 CPA

,":,Pl0o~P11
11

191----,
12 13 14 15 16 17 18

.fi!
•

P12

30VDC

~

SVINPUT
+ SIGNAL

R13

,...

I

22 "P;;:O=--:=--.+----t--+--4>--h

+<.(i).~.*"+------i 0
~

10
PO
'\

GO
231-;;;.-______

Ul

P+
PO
P-

25 ~ BO
24~AO

•

6

L~

Rll

/4321282726

~ki).!;.~I---;:B::-2-~

GR

Rl0

Cl 10.0

A
l!I \!l.

R14

JP2

.@@..

R5
100

J3

R7

lK

::Ii

!:i

R3

C7

lK
C3
0.10

w

R2
R4

lK

g
a:til
u..

..J

<
:t:
'7

P-

FIGURE 2. HARRIS HIP2030 DRIVER BOARD
NOTES:
1. Capacitors C5 and C6 are special function components which control MLT and MHT.
2. Asymmetrical gate drive may be obtained by opening J2 and adjusting R1 and R2 for the desired voltage ratio.
3. Insert C7 for charge pump operation.
4. Open J3 to disable the charge pump oscillator.
5. Open Jl to disable the intemal12V regulator.
6. R5 is added for noise rejection at CdVldts.
7. The internal5V reference (REF) must be operational for MHT and MLT functions to work properly.
8. Pl • P12 are access pads for all comparitor inputs.

4·7

HIP2030

Printed Circuit Board
~

'-: : ;/

....
••

r-"--:1"'~'•• ~•
••
••••••
••••••
••••••
••••••
••••••
•••••
••••
••••
••••
•••••
•••
(0)

•••

©
FIGURE 3A. ASSEMBLY LAYER

FIGURE 3B. BOTTOM LAYER

© •• •
••
-0.

••••

••
••••••
••••••
••••••
•••••••
•••••
•••••
:~-r-.-4
•••

I ••••••

•

•

•

•

• • I---":=F-I-==:I

::::
©
,-/

--

i•

~~Hr!]

~~ lLiIlil.I~1

©

.--'--'----'

FIGURE 3C. TOP LAYER

4·8

HIP2030
Appendix A Exercises
Exercise 1.1
Q: How do I calculate the value of the series dropping resistor Rl. shown in Figure 1?

The maximum value of Rl can easily be determined in four
design steps:

A: The values for Rl. Ro. RR and Rvpo can be determined
by using equations 1 (A. B. C. D).

1. Assume the following values:

VPO

R

a

R

=--

IOPO
VPO

- ,----.,---:-7"-

R - IOPTO + IVDR + IRP
1

RVPO

V1N
loPO

EQ1(A)

= -1--1-

IOPTO
IVDR
IRP(ON)

EQ1(B)
EQ1(C)

Where:

VPO
lopo
IOPTO
IVDR

5mA
2.5mA
5mA. R2 = lK. VR2 = 5V

2. Select a usable value of V PO between 7V and 15V DC.

-+RQ

30V DC
2.75mAat Vpo = 15V

Use Vpo=15V

RR

Voltage between pins PO and p. (Ul • U22
and U1 • U16)
Quiescent current flowing into pin PO.
Quiescent current of the HBR·2521 fiberoptic receiver.
Current flowing through R3 and R4 (voltage divider reference).
Current flowing through pull up resistor R2
(in ·ON" or ·OFP· state)

3. Solve for Rvpo using EQ1(A. B. C):
15V

RQ

= 2.75mA = S.4SK

RR

lSV
= (SmA + 2.SmA
= 1.20K
+ SmA)

RVPO

w

= ----:1;----.1- = 984

g
a:III

--+-5.45K

1.20K

u..

4. Solve for Rl using EQl (D):

..J

EQ1(D)

4·9

<
::t:

HIP2500
Half Bridge 500V oc Driver

April 1994

Features

Description

• Maximum Rating •••.••..••..••.•••••••.• 500V

The HIP2500 is a high voltage integrated circuit (HVIC) optimized to drive N-Channel MOS gated power devices in half
bridge topologies. It provides the necessary control for PWM
motor drive, power supply, and UPS applications. The SO pin
allows external shutdown of gate drive to both upper and lower
gate outputs. Undervoltage lockout will not allow gating when
the bias voltage is too low to drive the external switches into
saturation.

• Ability to Interface and Drive N-Channel Power
Devices
• Floating Bootstrap Power Supply for Upper Rail
Drive
• CMOS Schmitt-Triggered Inputs with Hysteresis
and Pull-Down
• Up to 400kHz Operation
• Single Low Current Bias Supply
• Latch-Up Immune CMOS Logic
• Peak Drive•••••••••••••••••••.••.••. Up to 2.0A
• Gate Drive Rise Time (+1250 C) .•••••• < 25ns (Typ)

Applications

The HIP2500lP is pin and function compatible to the International Rectifier IR2110. The HIP2500 has superior ability to
accept negative voltages from the Vs pin to the COM pin due to
forward recovery of the lower flyback diode.
The HIP2500lB is a SOIC or small outline IC form of the
HIP2500. The HIP2500lB drives high side and low side referenced power switches just like the HIP25001P.
The HIP2500IP1 is a 16 pin Plastic DIP form of the HIP2500.
Pins 4 and 5 removed from lead frame to provide extra creepage and strike distances in high voltage applications.

• High Frequency Switch-Mode Power Supply
• Induction Heating and Welding
• Switch Mode Amplifiers
• AC and DC Motor Drives

Functional Block Diagram

• Electronic Lamp Ballasts
• Battery Chargers
• UPS Inverters
• Noise Cancellation In Amplifier Systems

Voo

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

<;>--..,._.....

HO

HIN

Vs

LO

PACKAGE

HIP2500lP

·40"C to +85°C

14 Lead Plastic DIP

HIP2500lPl

-4O"C to +85°C

16 Lead Plastic DIP

UN

HIP2500lB

-40oC to +85°C

16 Lead Plastic sOle rN)

Vss

.

,------ .. _------- ..... _......

.

COM

----------- .... _-------------,

Pinouts
HIP2500 (PDIP)

HIP2500 (SOIC)

HIP2500 (PDIP)

TOP VIEW

TOP VIEW

TOP VIEW
NC

NC

Vss

Vss

UN

UN

so

SO

HIN

HIN

veo
NC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1gg4

4·10

File Number

2801.6

Specifications HIP2500
Absolute Maximum Ratings Full Temperature Range Unless
Otherwise Noted. All Voltages Referenced to Vss Unless Otherwise Noted.

Thermal Information

Floating Supply Voltage. Va .••...••...••.. Vs-0.5V to Vs+1B.OV
(Positive Terminal)
Floating Supply Voltage, Vs ........................... 500V
(Common Terminal)
High Side Channel Output Voltage, VHO ......•• -0.5V to Va+0.5V
Fixed Supply Voltage, Vee ..................... -o.5V to lB.OV
Low Side Channel Output Voltage, VLO ...•..•. -0.5V to Vec+0.5V
Logic Supply Voltage, Voo ••.....•........•..•• -o.5V to lB.OV
Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . -0.5V to Voo+0.5V
(HIN, LIN & SO (Shutdown)]

Thermal Resistance
OJA
75°CIW
HIP2500IP ••••...•..••.•••.•..•.•.••••.••.
BOoCIW
HIP2500IPI •••••••••.•••.••••••...•.•.••.•
900 CIW
HIP2500IB •..••..•••.•••••••.••.•••.•••..•
See Maximum Power Dissipation vs Temperature Curve
Junction Temperature Range •...••••••••.•••. -40oC to +125°C
Storage Temperature Range, Ts •••....•••••••• -40OC to +150oC
Operating Ambient Temperature Range, T" .•..••• -400C to +B5°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only raUng end operation
of the device at these or any other conditions above those indicated in the opera60na/ sections 01 this speciflca60n Is not implied.

Recommended DC Operating Conditions
Floating Supply Voltage, VB' ..............• Vs+l0V to Vs+15V
(Floating Terminal)
High Side Channel Output Voltage, VHO .....•..•.••.. 1OV to Va
(With Respect to Vs)
Fixed Supply Voltage, Vce ..•••....•......•......• 10V to 15V

Low Side Channel Output Voltage, VLO •..••.••.•••.. OV to Vcc
Logic Supply Voltage, Voo ........................ 4V to Vee
Floating Supply Voltage, Vs •••..•...•..•....... -4.0V to 500V
(Common Terminal)

Electrical Specifications vee = (Va-Vsl = Voo = 15V, COM = Vss = 0, Unless Otherwise Noted
TJ

= +25°C

TJ

= ·40·C TO +125"C

SYMBOL

MIN

TVP

MAX

MIN

TYP

MAX

UNITS

Quiescent Vee Current

lace

-

1.5

1.9

-

2.0

rnA

Quiescent Ves Current

laas

-

300

400

300

435

ItA

QUiescent Voo Current

laoo

-

0.1

1

-

I.B

ItA

-

ItA

22

ItA

PARAMETER
OC CHARACTERISTICS

Is (500V)

-

0.4

3.0

Logic Input Pulldown Current, VIN
(HIN, LIN, SO)

=Voo

IN+

-

12

20

-

Logic Input Leakage Current, VIN
(HIN, LIN, SO)

=Vss

IN-

-

0

1

-

0

1

ItA

Logic Input Positive Going Threshold

VTH+

7.5

B.O

B.5

7.5

B.O

B.6

V

Logic Input Negative Going Threshold

VrH-

5.5

5.9

6.3

5.5

5.9

6.4

V

Undervoltage Positive Going Threshold

UV+

B.O

9.35

9.99

7.B

V

UV-

7.7

9.05

9.69

7.5

9.69

V

Hysteresis (Ved

UVHYS (Ved

250

-

450

170

-

9.99

Undervoltage Negative Going Threshold

530

mV

Undervoltage Hysteresis (Vas)

UVHYS (Vas)

250

-

450

170

-

530

mV

Vour +

14.95

15

-

14.95

15

-

V

Output Low Open Circuit Voltage (HO, LO)

Your

-

-

0.05

-

-

0.05

V

Output High Short Circuit Current (Sourcing)

lour+

1.65

2.1

-

1.15

1.6

A

Output Low Short Circuit Current (Sinking)

lour-

I.B5

2.3

-

1.35

1.7

-

Quiescent Leakage Current

Undervo~age

Output High Open Circuit Voltage (HO, LO)

4-11

A

w

g
~
ID
U.
..oJ
4(
::t:

Specifications HIP2500
Switching Specifications

=

TJ -4O"C TO +125"C

TJ=+25"C
PARAMETER

SYMBOL

MIN

TVP

MAX

MIN

TVP

MAX

UNITS

-

725

ns

HIGH SIDE CHANNEL WITH 500V OFFSET, CL = 1000pF
High Side Tum-On Propagation Delay

toN

320

420

525

230

High Side Turn-Off Propagation Delay

-

625

ns

25

50

ns

25

50

ns

190

-

600

ns

175

-

475

ns

50

-

30

50

ns

25

50

-

30

50

ns

300

400

490

200

-

650

ns

240

320

400

180

-

500

ns

M\

0

-

125

0

-

185

ns

Minimum On OUtput Pulse Width (HO, LO)

PWOUT(MIN)

-

35

50

-

35

55

ns

Minimum Off OUtput Pulse Width (HO, LO)

PWl5ll'rMIN

275

440

640

250

440

650

ns

Minimum On Input Pulse Width (HIN, LIN)

PWON(MIN)

100

145

-

110

200

DHtoN

-

125

OLtoN

-

-20

-

dVsldt

-

-

50

toFF

300

385

450

230

High Side Rise Time

~

-

25

50

High Side Tum-Off Fall Time

IF

-

25

50

-

toN

250

365

450

toFF

225

295

370

Low Side Tum-On Rise Time

~

-

25

Low Side Tum-Off Fall Time

IF

-

High Side Shutdown

tsoHO

Low Side Shutdown

tsoLO

LOW SIDE CHANNEL, CL = l000pF
Low Side Tum-On Propagation Delay
Low Side Tum-Off Propagation Delay

Shutdown Propagation Delay

HIGH SIDE CHANNEL WITH 500V OFFSET, CL = l000pF
Turn-On Propagation Delay Matching
(Between HO and LO)

Minimum Off Input Pulse Width (HIN, LIN)

PWOFF(MIN)

Deadtime LO Tum-Off to HO Turn-On
Deadtime HO Turn-Off to LO Turn-On

-

100

175

ns

110

220

ns

125

-

ns

-

-20

-

-

ns

MAXIMUM TRANSIENT CONDITIONS
Offset Supply Oparatlng Transient

50

Logic Truth Table
HIN

LIN

UVH

UVL

SO

HO

LO

0

0

0

0

0

0

0

Normal Off

0

1

0

0

0

0

1

Lower On

1

0

0

0

0

1

0

Upper On

1

1

0

0

0

1

1

Both On

X

X

X

X

1

0

0

Chip Disabled

COMMENTS

X

X

1

1

X

0

0

Vee UV Lockout and Ves Lockout

X

1

1

0

0

0

1

Ves UV Lockout

1

X

0

1

0

1

0

Vcc UV Lockout

4-12

Vlns

HIP2500
Typical Performance Curves
2.5

~ 2.25
z

g
:

~

...... ;::::

2
1.75

iii

jg

1.5

ffi

1.25

~
::Ii

0.75

::>
::Ii

0.5

~

I I

V

HIP250()'IP
/ ' HIP250()'IPl

V

,/

~
...... ~ ~ , /
...... ~ ~

~

J

iii

jg

:II!!!!!

....
IIiIIII

... ~ ...

~

~

....

Vs .100V

:;,...r

;......r

0.01

.J;

...

~
S_
%

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90100110120130
AMBIENT TEMPERATURE (OC)

FIGURE 1. MAXIMUM POWER DISSIPATION vs TEMPERATURE

I I

0.001
10

IIII
1000

100
SWITCHING FREQUENCY (kHz)

FIGURE 2. HIGH VOLTAGE POWER DISSIPATION vs
SWITCHING FREQUENCY

10

6r---r-------,--------r----~

Vs=Vss = COM
Vas" Vee" 15Voc
TA=+250C

.... ~

1.0

!i!!:
In
In

"- o~

~

is

IX:

w

~~

I

0.1

~

--..
~

~

Vs ·400V

..... ...... Vs=300V
Vs·200V

IX:

o

z

VaIAS" 15V
CL" 100pF
TA,,+250C

!i...

HIP2500-IB

0.25

0

1.0

z
o

....'!lII~

0.1

...~

2100pF
907pF

l00pF

0.01

-4~

10

100
SWITCHING FREQUENCY (kHz)

__L __ _ _ _ _ _L __ _ _ _ _ _L __ _ _ _ _ _

1000

10

~~

16

12
14
SUPPLY VOLTAGE (V)

NOTE: All switching losses assumed to be in IC.
FIGURE 3. LOW VOLTAGE POWER DISSIPATION vs
FREQUENCY

FIGURE 4. Vss OFFSET vs V ee SUPPLY VOLTAGE

~ 10

10

~

200V

r-

I

~

'til""

I 5riOV

~

400V\
300V

~ ~ ~ ",

""'V-"

./

"

... 100V

~

i-"""

4

"...
~

o

~
20

40

60
80
100
TEMPERATURE (OC)

r--

6
5

0.1

I

8
7

i"""

Vee .15V AND 12V
TJ=+2SoC

9

120

140

FIGURE 5. OFFSET SUPPLY LEAKAGE vs TEMPERATURE

::
~

3

::Ii

2

I

II

Vee=15V~

......... ~~

.,.,...

....... "
"....

........... i-""'"
-I--

.........-

-

Vee = 12V

V
10

11

12
13
14
15
16
BOOTSTRAP SUPPLY VOLTAGE

17

18

FIGURES. MAXIMUMNEGATIVEVsOFFSETVOLTAGEvsVBS
VOLTAGE

4-13

HIP2500

Typical Performance Curves
8,35

~

8.3

5

11.25

g

9.2

~

w

CJ

9.15
8.1

~
g

.....

~

11.0

::I

8.95

10

,

TJ. _40°C TO +125oC

, '
"I~BSI
.........
" "-" "'

r-........ .........

~~

"l: .......

1""-00..

~VCCUV+

V

"" I"

VBS UV-

z

~
c

8

'"a:

6

w

UV+

./

()

§

-4~

-20

0

20
40
60
80
TEMPERATURE 1°C)

100

~

120

6

i:l

300

......~

250

ill

J 200

~

....

-

I

~14VIQBSI

~-

......

~

14VIQBSO

I

-

~.10VIQBSI

()

I::I

...

8

10

12

14

16

I

80

18

~

60

c
~

40

K!

20

-

IR
IF

o

I

o

50
100
JUNCTION TEMPERATURE 1°C)

100

150

~

~ ...

1000

lE4

LOAD CAPACITANCE IpF)

FIGURE 10. RISE AND FALL TIME va LOAD CAPACITANCE

3.0

zw
a:
a:
::I

~

100

w

/.10VIQBSO

FIGURE 9. QUIESCENT VBS SUPPLY CURRENT vs
TEMPERATURE

I-

VTH-

~

-'

I

-so

2.5

",.

FIGURE 8. INPUT LOGIC THRESHOLD va SUPPLY VOLTS

I
!!!'"

18VIQBSO
I

150

g

I"""

~

LOGIC SUPPLY VOLTAGE (V)

118VIQ~SI

350

~

~

~ liP""

120

450

Ii

~

2

140

FIGURE 7. UNDERVOLTAGE LOCKOUT va TEMPERATURE

1 400

./

4

U

L

I
./
VTH,,/

::c
l-

~CCU v-

./

I

5::c

.....

11.05

a:
w
c

(Continued)

30
·40
0
25

.....
"",U'

2.0

~

....... SOURCE DRIVER
SINK DRIVER
2

4
6
8
10
12
14
SOURCE/SINK DRAIN·SOURCE VOLTAGE

~

22

-'

50

...cw

28

w
::Ii

II"''''''

.............

1.5

....s

26
24

-'

~

20

cz

18

C
w

16

K!

14

-

-

- - ---

...-

~

......... r--

IF-

~-

12
10

-so

16

0

50
TEMPERATURE rC)

100

FIGURE 12. RISE AND FALL TIME va TEMPERATURE

FIGURE 11. DRIVER SINKISOURCE V-I CHARACTERISTIC

4-14

150

HIP2500

Typical Performance Curves

.

..s
w

:I

>=
oJ

~

30

~

26

~

22

20

'w"

16

tA

400

iii
!.i<:I

380

II.

12
11

12
13
14
SUPPLY VOLTAGE (V)

15

FIGURE 13. RISE AND FALL TIME va SUPPLY VOLTAGE

HtOFF

360

LioN

340

I I

320

lloF!

300
10

16

HlON

420

~

~
0
a:

14
10
10

440

!

24

18

~

460

28

0

z

(Continued)

12
13
14
SUPPLY VOLTAGE (V)

11

15

16

FIGURE 14. PROPAGATION DELAY va SUPPLY VOLTAGE

700

HtoN

!

600

~
z

500

LioN

 11 V OC
floating power supply required to drive the upper rail external
power device is created and managed by the HVIC through
CF and DF This capacitor is refreshed from the Voo supply
each time VOUT goes low. If the upper channel is commanded on for a long period of time, the bootstrap capacitor
CF is automatically refreshed by bringing VOUT low. This is
accomplished by turning off the upper rail MOSFETIIGBT,
momentarily tuming on the lower rail output device, followed
by returning control back to the upper switch. Otherwise, C F
would gradually deplete its charge allowing the upper switch
to come out of saturation. The upper and lower gate drivers
allow for controlled charge and discharge rates as well as
facilitate the use of nearly lossless current sensing power
MaS devices. The over current trip level can be boosted
30% on a pulse by pulse basis by logic level '1' applied to
ITRIPSELECT. A FAULT output signal is generated when any
of the following occurs:
V bias is low
Over current is detected
V phase doesn't agree with the input signal
Reset of FAULT is provided by externally removing power or
by holding both TOP and BOT inputs low for the required
reset time (trtMAX).

Each application can be individually optimized by the selection of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (Rd and discharge
(Ro) impedance chosen per the load capacitance, frequency
of operation. and DVDT dependent recovery characteristics
of the associated FBDs. Ro should also be sized to prevent
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (tOFF MIN).
The selection of over current detection resistors (Rp). compatible with current sense MOSFETsllGBTs or shunt(s) may
be used.
For the floating bootstrap supply OF and CF must be determined. OF must support the worse case system bus voltage
and handle the charging currents of CF. Proper selection
should take into consideration T RR and T FR per the desired
operating frequency. Proper selection of CF is a trade off
between the minimum toN time of the lower rail to charge up
the capaCitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350~s TYP (or even sooner if input commands the TOP to switch at a faster repetition rate).
The local filter capacitor (Coo) should be sized sufficiently
large enough to transfer the charge to C F without causing a
significant droop in Voo. As a rule of thumb it should be at
least 10 times larger than C F and be located adjacent to the
Voo and Vss pins to minimize series resistance and
inductance.

Refer to Application Note AN8829 for more details about module operation and selection of external components.

4-22

SP601

HARRIS
SEMICONDUCTOR

Half Bridge 500V DC Driver

April 1994

Features

Description

• Maximum Rating •..••.••.•••••.•••••••••••• soov

The SP601 is a smart power high voltage integrated circuit
(HVIC) optimized to drive MOS gated power devices in halfbridge topologies. It provides the necessary control and
management for PWM motor drive, power supply, and UPS
applications.

• Ability to Interface and Drive Standard and Current
Sensing N-Channel Power MOSFETnGBT Devices
• Creation and Management of a Floating Power Supply
for Upper Rail Drive
• Simultaneous Conduction Lockout

Ordering Information

• Overcurrent Protection
• Single Low Current Bias Supply Operation

PART

• Latch Immune CMOS Logic
• Peak Drive in Excess of O.SA

Pinout

SP601

TEMPERATURE
RANGE
-40°C to +85°C

PACKAGE
22 Lead Plastic DIP

w

g

Functional Block Diagram

a:III

SP601 (PDIP)
TOP VIEW

u..

..J
2 UPI
DOWN
21

~LE
NC

VBIAS

I.

100RND

G~I:U} ~

L--_ _

3
Voo

G2U

1t:----~11
VDO'

c(

3.50R as

~

TRIPu

11

15

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

4-23

File Number

2429.4

J:

Specifications SP601
Thermal Information

Absolute Maximum Ratings Full Temperature Range. All
Voltage Referenced to Vss Unless Otherwise Noted. Note 1. Note 2.
Low Voltage Power Supply. VBIAS (Note 1) •.•••••••••••• 18VDC
Floating Low Voltage Boot Strap • • • • • • • • . • • • . . . . • • . • •• 18VDC
Power Supply to Phase. Ves
Low Voltage Signal Pins
Fault. ITRIPSEL. Voo. TRIP L• CL1. G2L .•••••-o.5Voc to Voo +0.5
G1L. D1L. VOF • TOP. BOT
CL2. TRIP u • G1U. G2U. D1U to Phase •..•• -0.5voc to VBs+O.5
High Voltage Pins
Phase. VPHASE •. • • • . • • • • • . • • • • • . • • • • • . . . • . . . • . • 500VDC
(VSS • VOUT. TRIP u• CL2. G2U and D1U: OV-18V Higher Than
Phase)
Dynamic High Voltage Rating Phase •.•..••••.••.• 10.000VlIJS
DVpHASEIDT

Thermal Resistance. Junction-to-Ambient
9JA
Plastic DIP Package • • • • • • • .. .. .. .. • .. . .. . • • 750 CIW
Maximum Package Power Dissipation at TA = +85OC. Po
Plastic DIP Package ............................. 500mW
Operating Ambient Temperature Range. TA .•.•.•• -25°C to +85°C
Storage Temperature Range. Ts ............... -40°C to +lSOOC
Lead Temperature (Soldering lOs) •.•..•....•..••..... +265°C

NOTES:

1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RNO)'
Prolonged high peak currents may resuR if +15Voc is applied abruptly and/or if the local bypess cspacitor COD is large. It is suggested that COD be:s 10MFD.
If it is desirable to switch the 15Voc source or if a COD is larger, add"ional series impedance may be required.
2. Consult factory for add"ional package offerings.
CAUTION: Stresses above those listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the Op6raUonal sections of this specificaUon is not implied.

Electrical Specifications (VBlAS = 15V. Pulsed <300ms). Unless Otherwise Noted. All Parameters Referenced to Vss Except
TRIP u • CL2. G1U. D1U. and Ves Referenced to PHASE. DF: VOF to Ves. CF: Ves to PHASE
PARAMETER

SYMBOL

TEMP

MIN

TYP

MAX

UNITS

20

30

jIA

30

33

jIA

1.7

2.05

rnA

-40°C to +95°C

-

1.7

2.1

rnA

+25°C

-

1.7

2.05

rnA
mA

DC CHARACTERISTICS
Input Current (5V < VTOP , VSOT • VTRIPSEL < 15V)

+25°C

liN

-40°C to +85°C
ISlAS Quiescent Current (All Inputs Low)

IBiASL

ISlAS Quiescent Current
(VOUT 2: VSIAS • and All Inputs Low)

ISI~

Iss Quiescent Current Bootstrap Supply

+25OC

-40°C to +95°C
+25°C

les

_40°C to +95OC
ENABLE Threshold Level

VTOP

UP/DN Threshold Level

VSOT

Current Trip Select Threshold Level

VTRIPSEL

Trip Lower and Upper Comparator Threshold
Level- Normal (ITRIPSEL Vss)

VTRIPLJUN

Trip Lower and Upper Comparator Threshold
Level - Boost (ITRIPSEL VDO) % of Measured
VTRIPLJUN

VTRIPLJUS

=

=

Under Voltage Lockout Thresholds (Voo and Ves)

Phase Out of Status Voltage Threshold (PHASE)

Faultbar Impedance at IFBAR

=1rnA

VLOCK
VOSVT
RF

4-24

-

1.7

2.1

875

1000

jIA

900

1060

I1A

+25OC

7

8

9

V

-40OC to +95°C

6.95

8

9.1

V

+25OC

7

8

9

V

-40oC to +85°C

6.95

8

9.1

V

+25°C

7

8

9

V

-400C to +95OC

6.95

8

9.1

V

+25°C

90

105

125

mV

-40oC to +95OC

90

105

127

mV

+25°C

110

130

150

%

-40°C to +9SOC

109

130

152

%

+25°C

9

10

11.5

V

-40°C to +8SOC

9.7

10.5

11.8

V

+25°C

5

7

9

V

-4OOC to +95°C

4.7

7

9.6

V

+25°C

500

760

1000

-40°C to +85°C

450

760

1100

n
n

Specifications SP601
Electrical Specifications

=

(ValAs 15V. Pulsed <300ms). Unless Otherwise Noted. All Parameters Referenced to Vss Except
TRIPu • CL2. G1U. Dl U. and Vas Referenced to PHASE. DF: VDF to Vas. C F: Vas to PHASE (Continued)

PARAMETER

SYMBOL

TEMP

MIN

TYP

MAX

UNITS

Rsouu

+25°C

12

17

23

-40oC to +85°C

7

17

29

+25°C

8

12

16

-40°C to +85°C

5

12

20

+25°C

2

3.5

5

-40oC to +85°C

1.4

3.5

5.6

+25°C

6

10

14

-40°C to +85°C

5.4

10

14.6

n
n
n
n
n
n
n
n

ILK

+25°C

-

1

3

JlA

V D1U/L

+25°C

0.4

0.9

1.4

V

VCL21HOW

+25°C

6.35

6.61

6.85

V

-40°C to +85°C

6.15

6.61

7.15

V

V CL2I1.HIGH

+25°C

7.0

8.5

8.0

V

Ra

+25°C

2

3.5

5

-40°C to +85°C

1.4

3.5

5.6

n
n

Upper/Lower Source Impedances (lsoURCE = lOrnA)

Upper/Lower Sink Impedances (ISINK = lOrnA)

Rsluu

Bootstrap Supply Current Limiting Impedance

Ras

Noise Dropping Resistor Impedance

RND

High Voltage Leakage (500V Vas. Your. PHASE.
TRIPu • CL2. G1U. G2U. and D1U to Vss.
All other Pins at V5S)
Miller Clamp Diodes; D1U and D1L (10 = lOrnA)
Noise Clamping Zeners; CL2 and CL 1 (I z = lOrnA)

Noise Clamping Zeners; CL2 and CL 1 (Iz = 50mA)
Your Limiting Resistance

NOTE: Maximum Steady State + 15Voc Supply Current = lalAsL + las

Switching SpeCifications

(All Referenced to Vss. Except: TRIP u • CI2. G1 U. G2U. and Dl U Referenced to PHASE.
DF: V DF to Vas. C F: Vas to PHASE)

PARAMETER
Refresh One Shot Timer

Delay Time of Trip I/U Voltage (IrRIPsEL low) to
G2U1G2L Low (SO% Overdrive
Delay Time of Trip I Voltage (lrRIPsEL low) to
Faultbar Low

SYMBOL

TEMP

MIN

TYP

MAX

UNITS

tREF

+25°C

200

350

500

I1S

-40oC to +85°C

180

350

540

I1S

+25°C

2

3

4

I1S

-40oC to +85°C

1.85

3

4.35

I1S

+2SoC

2

3

4

I1S

-40oC to +85°C

1.85

3

4.35

I1S

+25°C

500

700

900

ns

-40oC to +85°C

400

700

1050

ns

+25°C

300

430

600

ns

-40oC to +85°C

275

430

660

ns

+25°C

1.6

2.3

3.1

I1S

-40oC to +85°C

1.5

2.4

3.4

I1S

+25°C

1.3

2.0

3.4

I1S

-40oC to +85°C

1.05

2.1

3.9

I1S

+25°C

2.5

3.2

4.5

I1S

-40oC to +85°C

2.1

3.3

5.2

I1S

+25°C

2.5

3.2

4.5

I1S

-40oC to +85°C

2.1

3.3

5.2

I1S

IoFFTN

tFN

Delay Time of Phase Out of Status to Faultbar
Low (TOP High)

IosvF

Minimum Logic Input Pulse Width: TOP and
BOTTOM

tMINIW

Minimum G1U1G1L On Time

ioN

Minimum Pulsed Off Time. G2U/G2L

IoFF

Turn On Delay Time ofG1U (BISTATE MODE)

Turn On Delay Time of G 1L (BISTATE MODE)

IoND

IoND

4-25

Specifications SP601
Switching Specifications (All Referenced to Vss , Except: TRIP u , CI2, G1U, G2U, and D1U Referenced to PHASE.
OF: VOF to Yes, CF: Ves to PHASE) (Continued)
SYMBOL

TEMP

MIN

TYP

MAX

UNITS

Turn On Delay TIme of G 1U
(THREE·STATE MODE)

PARAMETER

laND

+25OC

0.75

1.0

1.5

lIS

-40°C to +8500

0.60

1.1

1.75

lIS

Turn On Delay TIme of Gl L
(THREE·STATE MODE)

laND

+25°C

0.75

1.0

1.5

lIS

-400 C to +85°C

0.60

1.1

1.75

lIS

Turn Off Delay Time of G2U and G2L

IaFFO

+25°C

0.75

1.0

1.45

lIS

-400 C to +65°C

0.60

1.1

1.75

lIS

+25°C

1.5

2.5

3.5

lIS

-400 C to +85OC

1.2

2.6

4

lIS

+25°C

3.4

4.5

6.6

lIS

-400 C to +85°C

3.15

4.8

7.4

lIS

+25°C

25

50

100

ns

-40°C to +85°C

15

50

115

ns

+25°C

25

50

100

ns

-400 C to +85°C

15

50

115

ns

Minimum Dead TIme: G 1U OFF to G1L ON, or
G1L off to G1U on (BISTATE MODE)

to.T.

Fault Reset Delay to Clear Faultbar

iR:r.

Rise TIme of Upper and Lower Driver
(Load =2000pF)

iR U/I.

Fall TIme of Upper and Lower Driver
(Load =2000pF)

tF Ull

Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to Vss, Unless
Otherwise Noted. See Figure 1)
PARAMETER

CONDITION

FAULTBAR

Open Drain Fault Indicator Output

ITRIPSELECT

Digital Input Command to Increase TRIP L and TRIPu Threshold by 30%

VB1AS

14.5V to 16.5V with 15V nominal, '" 1.5mA DC BIAS Current

Voo

Coo to Vss

Vss

COMMON

TRIPI
CLI
G2LandG1L

100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output
Lower Noise Clamp Zener
Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER)

VOF

Current Umiting Charging Resistor for Bootstrap Capacitor Power Supply

Ves

Bootstrap Supply, Normally a Diode Drop BelOW VOO Voltage with Respect to the Floating PHASE Reference

VOUT

Load Connection Node

PHASE

Floating Reference Point for High Side Control Circuitry: Vas, TRIPu, Cl2, Gl U, G2U and 01 U

TRIPu

100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive

Cl2
G2U andG1U
ENABLE
UP/ON

Upper Noise Clamp Zener
Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER)
Digital Input to ENABLE the UP/ON Command to Turn on Top/Botlom Devices
Digital Input to Top/Botlom Device (If ENABLE is High)

DIU

Miller Clamp UPPER to Vas

D1L

Miller Clamp LOWER to Voo

4-26

SP601
Timing Diagram
ENABLE

o

0

UPIDOWN

o

0

REFRESH
ONE SHOT
10NB
VAUDBOTON
10FFT
IoNT
IoF~

UPPER
LOWER
VOUT

1
0
1
0
1

U
--1l

1

o
1

o
1

0

o

0
0

o

1

10F~

0

0
UPPER

__________nl...-_

0
1

0
LOWER

0

0

C:~\J

-,}

VOUT

THREE·STATE MODE SLOWER THAN REFRESH ONE SHOT nMER

VOC
COM

BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER

NOTE: BOT switching not relevant.

Typical Circuit Configuration
TRUTH TABLE

Applicable to Typical Circuit Configuration (Figure 1)
OUTPUTS

INPUTS
UPIDN

ENABLE

TRIPL

TRIPU

PHASE

VB1AS

UPPER

LOWER

FAULT BAR

0

0

0

X

X

1

0

0

1

1

0

1

1

1

0

0

1

1

1

1

0

1

1

1

0

0

0

1

1

0

X

0

1

0

0

0

X

X

1

X

X

1

0

0

0

0

1

0

X

X

1

0

1

1

1

0

0

X

X

1

0

0

1

X

X

X

X

X

0

0

0

0

NOTE: 0 =False, 1 =True, X =Don't Care

4·27

SP601

25VOC;; VUNK ;; 5OOVOC

RCU ROU
RpU
19

18

17

D1U GW G2U TRIPU

....

21

8

22

i...
::I!

I!!

(I)

>(I)

2

14

15

PHASE

VOUT

13
12 CF

VBS

BOT

VOF

VOUT

11 OF

•••• J"f'N\. ••••

TOP

SP601
HVIC

Dll

mTCf

Gll

ITRIPSELECT

G2l

VBIAS VOO

Vss

TRIPL

10

lOAD

9

RCL

8

ROL

6
RpL

15V

COM

Coo

FIGURE 1. TYPICAL CIRCUIT CONFIGURATION

LEGEND
Application Specific

Rcu

Upper Gate Charging Resistor

Application Specific

Rou

Upper Gate Discharge Resistor

Application Specific

Rpu

Upper Current Pilot Resistor

Application SpecifIC

RCL

Lower Gate Charging Resistor

Application Specific

ROL

Lower Gate Discharging Resistor

Application Specific

RpL

Lower Current Pilot Resistor

311F at" 15DC

Coo

Local LV Filter Capacitor

O.2211F Ceramic X7R at" 15Voc

CF

Flying Capacitor for Bootstrap Supply

Harris PIN A114M or Equiv PRY " VL1NK

OF

Flying Diode for Bootstrap Supply

NOTE:

Refer to 'Additional Product Offerings' for information concerning power output devices.

4-28

SP601
Functional Description
The SP601 provides a flexible, digitally controlled power
function which is inte,nded to be used as PWM drivers of
N-Channel MOSFETs and/or IGBTs for up to 240VAC line
rectified totem-pole applications. The CMOS driveable
inputs are filtered and captured by the control logic to determine the output state. The logic includes fixed timing to prohibit simultaneous conduction of the external power switches
and, thru the VOUT sense detector, verifies the output voltage
state is in agreement with the controlled inputs. The> 11 VDC
floating power supply required to drive the upper rail external
power device is created and managed by the HVIC through
CF and Dp This capacitor is refreshed from the Voo supply
each time VOUT goes low. If the upper channel is commanded on for a long period of time, the bootstrap capacitor
CF is automatically refreshed by bringing VOUT low. This is
accomplished by turning off the upper rail MOSFETIIGBT,
momentarily turning on the lower rail output device, followed
by returning control back to the upper switch. Otherwise, CF
would gradually deplete its charge allowing the upper switch
to come out of saturation. The upper and lower gate drivers
allow for controlled charge and discharge rates as well as
facilitate the use of nearly lossless current sensing power
MOS devices. The over current trip level can be boosted
30% on a pulse by pulse basis by logic level '1' applied to
ITRIPSELECT' A FAULT output signal is generated when any
of the following occurs:
V bias is low
Over current is detected
V phase doesn't agree with the input signal
Reset of FAULT is provided by externally removing power or
by holding the ENABLE input low for the required reset time
(trtMAX)'

Each application can be individually optimized by the selection of external components tailored to ensure proper overall
system operation including:
Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).
The selection of separate gate charge (Rd and discharge
(Ro) impedance chosen per the load capacitance, frequency
of operation, and D~T dependent recovery characteristics
of the associated FBDs. Ro should also be sized to prevent
simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (toFF MIN)'
The selection of over current detection resistors (Rp), compatible with current sense MOSFETsllGBTs or shunt(s) may
be used.
For the floating bootstrap supply OF and CF must be determined. DF must support the worse case system bus voltage
and handle the charging currents of CF. Proper selection
should take into consideration T RR and TFR per the desired
operating frequency. Proper selection of C F is a trade off
between the minimum ioN time of the lower rail to charge up
the capacitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350jls TYP (or even sooner if the UPIDN
input switches at a faster repetition rate).
The local filter capacitor (Coo) should be sized sufficiently
large enough to transfer the charge to CF without causing a
significant droop in Voo. As a rule of thumb it should be at
least 10 times larger than CF and be located adjacent to the
Voo and Vss pins to minimize series resistance and
inductance.

Refer to Application Note AN8829 for more details about module operation and selection of external components.

4-29

INTELLIGENT 5
POWERICs

AC TO DC CONVERTERS

PAGE
AC TO DC CONVERTER SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2

AC TO DC CONVERTER DATA SHEETS

CA3059. CA3079

Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications. . . . . .

5-3

HV-2405E

World-Wide Single Chip Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-15

5-1

AC to DC Converter Selection Guide

DEVICE
CA30S9
CA3079

DESCRIPTION
Zero Voltage Sw~ch
AC Power Control
System on a Chip

ACINPUT
VOLTAGE AT
S()'60HzAND
400Hz (VAC)

MAX
DC SUPPLY
VOLTAGE
(V)

MAX
OUTPUT
CURRENT
(rnA)

SENSOR
RANGE
(RX) (Kn)

24V
120V

14

124

2 to 100

208l230V

10

124

2to 50

Output
SVto 24V

50

-

2nV
HV-240SE

World Wide Single
Chip Power Supply

15Vto 275V

FEATURES
Contains, Power Supply Zero
Crossing Detector, External
Sensor Comparator and Triac
Driver. (Inhibit and Protection
Circuits on CA30S9 only)
UL Recognized EI30808

NOTE:
1. Electrical Characteristics at TA = +25°C, 14 Lead Dual-In-Une (E) Package
Operating Temperature Range (TA) -55°C to +125°C.

DEVICE

DESCRIPTION

HIP5600

High Vo~age
Linear Regulator

INPUT
VOLTAGE
RANGE

OUTPUT
VOLTAGE
RANGE

MAXIMUM
OUTPUT
CURRENT

BIAS
CURRENT

50Vto 400V

1.2V to

35mA

600llA

350V

5-2

TEMPERATURE RANGE
-400C to +100oC
Thermal Protection at 134°C

CA3059, CA3079
Zero-Voltage Switches for 50Hz-60Hz and
400Hz Thyristor Control Applications

PRELIMINARY
April 1994

Features

Description

• Relay Control

The CA3059 and CA3079 zero-voltage switches are monolithic silicon integrated circuits deSigned to control a thyristor
in a variety of AC power switching applications for AC input
voltages of 24V. 120V. 208l230V. and 277V at 50Hz-60Hz
and 400Hz. Each of the zero-voltage switches incorporates
4 functional blocks (see the Functional Block Diagram) as
follows:

• Valve Control
• Synchronous Switching of Flashing Lights
• On-Off Motor SwHchlng
• Differential Comparator with Self-Contained Power
Supply for Industrial Applications
• Photosensitive Control

1. Limiter-Power Supply - Permits operation directly from an
ACline.

• Power One-Shot Control
• Heater Control

2. Differential On/Off Sensing Amplifier - Tests the condition
of external sensors or command signals. Hysteresis or
proportional-control capability may easily be implemented in this section.

• Lamp Control

Type Features

CA3059 CA3079

• 24V, 120V, 208l230V, 277V at 50/60. . . .
or 400Hz Operation

X

X

• Differential Input • • . . . • • • • • • • • • • • . •

X

X

• Low Balance Input Currant (Max) - J.1A. • •
• Built-In Protection Circuit for. • • • • • • •
Opened or Shorted Sensor (Term 14)

1
X

2
X

• Sensor Range (Rlc) - kQ •••••.••••••• 2 -100 2 - 50
• DC Mode (Term 12) •••.••••••.•••••

X

• External Trigger (Term 6). . • • . • . • • • • •

X

• External Inhibit (Term 1) ••••••••••••

X

• DC Supply Volts (Max) •••••••••••••
• Operating Temperature Range (OC) • .•

14

3. Zero-Crossing Detector - Synchronizes the output pulses
of the circuit at the time when the AC cycle is at zero voltage point; thereby eliminating radio-frequency interference (RFI) when used with resistive loads.
4. Triac Gating Circuit - Provides high-current pulses to the
gate of the power contrOlling thyristor.
In addition. the CA3059 provides the following important
auxiliary functions (see the Functional Block Diagram).
1. A built-in protection circuit that may be actuated to remove
drive from the triac if the sensor opens or shorts.

10

2. Thyristor firing may be inhibited through the action of an
internal diode gate connected to Terminal 1.

-55 to +125

3. High-power dc comparator operation is provided byoverriding the action of the zero-crossing detector. This is accomplished by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous when Terminal
13 is positive with respect to Terminal 9.

Ordering Information
PART NUMBER

TEMPERATURE

PACKAGE

CA3059

-55°C to +125°C

14 Lead Plastic DIP

CA3079

-55°C to +125°C

14 Lead Plastic DIP

The CA3059 and CA3079 are supplied in 14 lead dual-inline plastic packages.

Pinouts
CA3079 (PDIP)
TOP VIEW

CA3059 (PDlP)

TOP VIEW
INHIBIT
DC SUPPLY
HIGH CURRENT
NEG. TRIGGER
TRIGGER OUT
ACIN
TRIGGER IN
COMMON

FAIL-SAFE

DONOTUSE 1

3 SENSE AMP IN

DCSUPPLY 2

H~~~5r~~:g~~

ZCD OVERRIDE
1 R DRIVER (COM)

3

TRIGGER OUT 4

o R DRIVER V·

1 DONOTUSE
1 SENSE AMP IN

1 DONOTUSE
11 R DRIVER (COM)

1 RDRIVERV·

SENSE AMP REF

DONOTUSE 6
COMMON 7

COMMON

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedure•.
Copyright © Harris Corporation 1994

5-3

9 SENSE AMP REF
8 COMMON

File Number

490.3

til

()a:

Q~

Oa:

t- W

(»

«~

()

CA3059, CA3079
Functional Block Diagram

• NEGATIVE TEMPERATURE COEFACIENT

AC INPUT VOLTAGE (50160 OR 400Hz)
VAC

INPUT SERIES RESISTOR (RS>
kO

DISSIPATION RATING FOR Rs
W

24

2

0.5

120

10

2

2081230

20

4

277

25

5

NOTE: Circuitry within shaded areas, not included In CA3079
• See chart
.& IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)

Rp

RSENSOR

Ra

15
Ra
25

FOR
INCREASED
GATEDRIYE

TO
THYRISTOR
GATE

All resistance values are in 0
NOTE: Circuitry within shaded areas
not Included In CA3079

INHIBIT
INPUT

.& IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)

FIGURE 1. SCHEMATIC DIAGRAM OF CA3059 AND CA3079

5-4

Specifications CA3059, CA3079
Absolute Maximum Ratings TA = +25°C

Thermal Information

DC Supply Voltage (Between Terminals 2 & 7)
CA3059 ...........................•.•............ 14V
CA3079 .•.••.••...••..••.•.••....•••••.....•.•.•• 10V
DC Supply Voltage (Between Terminals 2 & 8)
CA3059 .......................................... 14V
CA3079 ...••..•.•••••..•.•.•.......•••.........•. 10V
Peak Supply Current (Terminals 5 & 7) ................... ±50mA
Output Pulse Current (Terminal 4) •••...•.......•..••.. 1SOmA

Thermal Resistance
8JA
PDIP Package •.•..•...•.•...•.•...•..•.••.... 1000CIW
Power Dissipation
Up to TA = +55°C CA3059, CA3079 .••..••.•..•..•.. 9SOmW
Above TA = +55°C CA3059, CA3079 •. Derate Linearly 10mWf'C
Ambient Temperature
Operating .•...••.....•...•••..•.......•. -55°C to + 125°C
Storage ................................ -65°C to + 1SOoC
Lead Temperature (During Soldering) .•....•.....•.••.• +265°C
At distance 1/16" ± 1132" (1.59 ± 0.79) from case
for 10 seconds max

CAUTION: Stresses above thoselis/ed in "Absolute Maximum Ratings" may causa parmanant damaga to the daviea. This is a stress only ra~ng and operation
of the device sf these or any other conditions above those indicated in the op6rational sections of this specification is not implied.

Electrical Specifications

TA = +25°C, For all Types, Unless Otherwise SpecHied. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1)

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

6.1

6.5

7

V

DC SUPPLY VOLTAGE (Figure 2A, 2B, 2C)
Inhibit Mode

Pulse Mode

At SO/60Hz

Vs

Rs=8kn,IL=0

At 400Hz

Rs =10kn,I L =0

At 5OI60Hz

Rs =5k!l,I L =0

-

6.4

-

Rs = 8k!l, IL = 0

6

6.4

7

V

6.7

-

V

At So/60Hz

Vs

At 400Hz

Rs= 10kn,I L =0

At SO/60Hz

Rs = 5k!l, IL = 0

Gate Trigger Current (Figures 3, 4A)

IGT
Terminal 4

6.8

Terminals 3 and 2 Connected,
VOT = 1V

-

6.3

V
V

V
rnA

105

cl!:!

PEAK OUTPUT CURRENT (PULSED) (Figures 4, 5)
With Internal Power Supply
Figure 4a, 4b

Oa:

10M
Terminal 4

With External Power Supply
Figure Sa, 5b, 5c

10M
Terminal 4

Inhibit Input Ratio (Figure 6)

Vi'/2

Terminal 3 open, Gate Trigger
Voltage (VOT) = 0

50

84

Terminals 3 and 2 Connected, Gate
Trigger Voltage (VGT) = 0

90

124

Terminal 3 open, V+ = 12V, VOT = 0

-

For Negative dv/dt

SO-60Hz

tp

C eXT = 0

400Hz

C eXT = 0, ReXT =

SO-60Hz

C eXT = 0

tN

400Hz

C eXT = 0, ReXT =

00

00

rnA

170

-

rnA

-

rnA

0.465

0.485

0.520

-

70

100

140

j.1S

-

12

-

j.1S

70

100

140

j.1S

-

10

-

j.1S

-

PULSE DURATION AFTER ZERO CROSSING (50-60Hz) (Figure 7A)
For Positive dv/dt

\p,

50

-

j.1S

For Negative dv/dt

tN'

-

60

-

j.1S

I,

-

0.001

10

vA

-

220

1000

nA

220

2000

nA

-

V

C eXT = 0, ReXT =

00

OUTPUT LEAKAGE CURRENT (Figure 8)
Inhibit Mode
INPUT BIAS CURRENT (Figure 9)
CA3059

II

-

CA3079
Common-mode Input Voltage Range

VeMR

Terminals 9 and 13 Connected

5-5

-

1.5 to
5

t-W

(»



TERMINAL 3 OPEN..............
I

40

4

.....

I
I

FIGURE 4B. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059 AND CA3079

~ts
o

CA3059, CA3079

C

!.
c

Rs
10K

~:::I

A-

..

120VRMS, 5OI6OHz OPERATIoN
GATE TRIGGER, VGT. 0 M

300

1/

250
200

:::I
A-

150

0

~
w

A-

100

o

5

FIGURE SA. PEAK OUTPUT CURRENT (PULSED) WITH EXTERNAL POWER SUPPLY TEST CIRCUIT FOR CA3059

"

200

'. '.

'"
", '.'"

.......
C

'.".

!.
cw

...
Ul

:::I
A-

R~
'."

".

"

150

..

#.....

:::I

0

lI<:

cC
W

A-

100

50

'.

~

~ EXTERNAL
SUPPLY
V+",13V

~

'.'.
"

~

. .........

~

"

12V

......... '-..
.... .....
~

.......

13V
..::;;,; ·12V
8V

r-- r-- I-

"...,

-."

.""

....

....., .... '"''

ALL RESISTANCE
VALUESINO

10V

......
..... .....
...•..
..... .....
·10V
"
.....
• 8V
i""""'-oo.
.,., I". ,.,.

'",

~

120VRMS
60Hz

" '""" "
~
'."

I-"
:::I
A-

RS
10K

"~ "r':

'.

FIGURE 6(A). INPUT INHIBIT VOLTAGE RATIO TEST CIRCUIT
FOR CA30S9 AND CA3079

12OVRMS, 60160Hz OPERATION

0.60

5V

0.56

3V

", " '

'"

.so

-20

10

40

70

100

I--.---.-----.r---.---.-----,-+-+--I
I-+-+--If-+-+--I-+-+--I

·5V

0.45 I--+--I--+---If--+--I--+---If--i

·3V

0.40 I--+--I--+---If--+--I--+---If--i

120VRMS, 50160Hz OPERATION
GATE TRIGGER VOLTS (VGT) = 0
TERMINALS 2 AND 3 CONNECTED
" " , . TERMINAL 3 OPEN

o

20

FIGURE SB. PEAK OUTPUT CURRENT (PULSED) vs EXTER·
NAL POWER SUPPLY VOLTAGE FOR CA3059

~\~

-"-

15

10

EXTERNAL POWER SUPPLY, V+ M

ALL RESISTANCE VALUES ARE IN 0

250

I

,~V

50

o

I

V/

:::I

OSCILLOSCOPE
WITH
HIGH GAIN
INPUT

CONNECTED

/ ' TERMINAL 3 OPEN

/

I-"

120VRMS
60Hz

TERMINALS 2 AND 3

~

130

.so

AMBIENT TEMPERATURE ("C)

FIGURE SC. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA30S9

~~ r--+--r-+--If--+--r-+--If-~

~

-25

0

25

50

75

100 125

AMBIENT TEMPERATURE ("C)

FIGURE 6B. INPUT INHIBIT VOLTAGE RATIO va AMBIENT TEMPERATURE FOR CASOS9 AND CAS079

5-8

CA3059, CA3079

OV
:

"

tNt

~
Z

~tN

120VRMS, S0I60Hz OPERAnON
TA=+25oC

300

100'

IIp (P~SlTItE dvJdt)
I
I
J..
I
I
-

~

IN

0

!iII:

I

:>
0

w
~

120VRMS
60Hz

200

/

:>

....

w
~

CJ

100

IV

(NEGAn~E dV~dt)

...I

~

o

o

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

NOTE: Circuitry w~hin shaded area not included in CA3079.
All resistance values are in a

EXTERNAL CAPACITANCE (I'F)

FIGURE 7A. GATE PULSE DURATION TEST CIRCUIT WITH
ASSOCIATED WAVEFORM FOR CA3059 AND
CA3079

FIGURE 7B. TOTAL GATE PULSE DURATION vs EXTERNAL
CAPACITANCE FOR CA3059 AND CA3079

700

40

r---r--r--------------------r-;
120VRMS, SO/60Hz OPERAnON
TA=+2SoC

12OVRMS, S0I60Hz OPERATION
TA" +2SoC

600

I--+--+--I--+---+-

500

(/)

tNi (NEGAnVE dv/dt)

Oa:

c~

400 I--+--+--I--+--+--I--t--~~~~

Oa:
t-W
0>

c(~
o

10

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
EXTERNAL CAPACITANCE 6tF)

100

EXTERNAL RESISTANCE (lin)

FIGURE 7C. PULSE DURATION AFTER ZERO CROSSING vs
EXTERNAL CAPACITANCE FOR CA3059 AND
CA3079

FIGURE 70. TOTAL GATE PULSE DURATION vs EXTERNAL
RESISTANCE FOR CA3059

FIGURE 7.
100
120VRMS, SOI6OHz OPERAnON
INPUT RESISTANCE (Rs = 10011n
NO EXTERNAL LOAD

c-

.s
w

CJ

I

V+=6V

If

10

g

I

I

W
...I

!;

1=
:>

.,

0

)
+3V

0.1
-80 -60 -40 -20

0

20

40

60 80 100 120 140

AMBIENT TEMPERATURE ("C)

FIGURE 8. OUTPUT LEAKAGE CURRENT (INHIBIT MODE) vs
AMBIENT TEMPERATURE FOR CA3059 AND CA3079

5-9

FIGURE 9. INPUT BIAS CURRENT TEST CIRCUIT FOR CA3059
ANDCA3079

CA3059, CA3079

lz

I

~

a:

:::I
C

!l
:::I

(+ dv/cIt)

!C
CI

100

...
...g

-,4

...

...
0.08

~

o

0.1

--

.....l- !"-'

~

!"-'
~~

~

60Hz, IN
(-dy/cIt) -

50Hz, IN
(- ~V/dl) I
0.04

r-

1 "I
0.06

0.1

0.08

EXTERNAL CAPACITANCE (11F)
FIGURE lOB.

600 , - - - - - - - - - - - - - - , , - - - . - - . , - - - ,
220VRMS, 50160Hz OPERATION
50Hz, INI
INPUT RESISTANCE (RS) = 101dl
(- dv/cIt)

600

220VRMS, SO/60Hz OPERATION
INPUT RESISTANCE (Rs) = 201dl

I

0.06

0.08

_-+__""-"'"

60HZ,IN1"
1 (- dv/dl)
~HZ,tNl --~~~~~~~~~
(- dy/dl)

400

0.04

- --

\.

/

0.02

FIGURE lOA.

0.02

50Hz, Ip
(+ dy/dl)

0

EXTERNAL CAPACITANCE (11F)

I

:::::::

; ; ioo""""

g

I
'--

60Hz, Ip
(+dv/dl) \

-

200

W

!C
CI

0.06

-

!l:::I

j

0.04

0.02

400

I

w

60Hz,IN
(- dv/dl)

0

220VRMS, 50160Hz OPERATION
INPUT RESISTANCE (Rs) .20kO
I

5

;;...

~Z,IN/
(- dv/cIt)
o

-

/

~~.

...
w

o
~
a:

I

60Hz, Ip
(+ dv/dl)

50Hz, Ip

200

w

600

lz

220VRMS, 50160Hz OPERATION
INPUT RESISTANCE (Rs) = 101dl

300

0

O~--~----~----L-----'----~

o

0.1

EXTERNAL CAPACITANCE (I1F)

0.02

0.04

0.06

0.08

0.1

EXTERNAL CAPACITANCE (11F)

FIGURE 10C.

FIGURE10D.

FIGURE 10. RELATIVE PULSE WIDTH AND LOCATION OF ZERO CROSSING FOR 220V OPERATION FOR CA3059 AND CA3079

§:
"-

"-

rf
z

....-

rf


~~

o

FIGURE 15. ON/OFF TEMPERATURE CONTROL CIRCUIT WITH DELAYED TURN-ON

120VAC

-b

SKn
2W

10Kn
R1

NOTE:
Terminal 1 goes "High"
(Logic "1") after 2048
pulses are applied to
Terminal 10.
For 8 hour delay:
R1 = 12MQ
C 1 = 211F

FIGURE 16A. LINE-OPERATED Ie TIMER FOR LONG TIME PERIODS

5-11

CA3059, CA3079

SENSOR ILLUMINATION

COUNTER RESET
(TERMINAL 11 OF CD4040)
"CLOCK" PULSES
(TERMINAL 9 OF CA3097E)
COUNTER OUTPUT
(TERMINAL 1 OF CD4040)
TERMINAL 6 OF CA3059 AND
TERMINAL 5 OF CA3097E
TERMINAL 4 OF CA3059
AND POWER IN LOAD

FIGURE 16B. TIMING DIAGRAM FOR FIGURE 16A

T2302B
MAX LOAD. 2.5A

16

+Voo (E +6.5V)

COSIMOS CD4020A
14-STAGE BINARY
COUNTER

H
G
F

a

b

c

d

e

9

h

E

t'-___--'r ~
PROGRAMMING
INTERCONNECTIONS

B

A

FIGURE 17A. PROGRAMMABLE ULTRA-ACCURATE LINE-OPERATED TIMER.

5-12

CA3059, CA3079
TIME PERIODS (I

= 0.5333 s)

11

1281

a

h
CD4048A TERMINALS

A

B

C

D

E

F

G

H

C

NC

NC

NC

NC

NC

NC

NC

11

NC

C

NC

NC

NC

NC

NC

NC

21

C

C

NC

NC

NC

NC

NC

NC

31

NC

NC

C

NC

NC

NC

NC

NC

41

C

NC

C

NC

NC

NC

NC

NC

51

NC

C

C

NC

NC

NC

NC

NC

61

C

C

C

NC

NC

NC

NC

NC

71

NC

NC

NC

C

NC

NC

NC

NC

81

C

NC

NC

C

NC

NC

NC

NC

91

NC

C

NC

C

NC

NC

NC

NC

lOt

C

C

NC

C

NC

NC

NC

NC

111

NC

NC

C

C

NC

NC

NC

NC

121

C

NC

C

C

NC

NC

NC

NC

131

NC

C

C

C

NC

NC

NC

NC

141

C

C

C

C

NC

NC

NC

NC

151

C

C

C

C

NC

C

C

NC

1111

NC

NC

NC

NC

C

C

C

NC

112t

If)

C

NC

NC

NC

C

C

C

NC

113t

Oa:

C

C

C

C

C

C

C

C

255t

Oa:
t- W

to = Total time delay = n, 1+ n2 I + •.. nnt.

0

2. C = Connect. For example. interconnect lerminal a of the CD4020A and terminal A of the CD4048A.
3. NC = No Connection. For example. lerminal b of the CD4020A open and terminal B of the CD4048A connecled 10 +Voo bus.

AC
SUPPLY
VOLTAGE

CA3059
OUTPUT
(PIN 4 AND PIN 6)

CD4048A
OUTPUT

0>

<~

NOTES:
1.

C~

____________________~A

II

Ir------

I~

1IrvI

AC IN LOAD (R L)

FIGURE 17B. "PROGRAMMING" TABLE FOR FIGURE 17(A).

5·13

CA3059, CA3079

Operating Considerations
Power Supply Considerations for CA3059 and CA3079
The CA3059 and CA3079 are intended for operation as selfpowered circuits with the power supplied from and AC line
through a dropping resistor. The internal supply is designed
to allow for some current to be drawn by the auxiliary power
circuits. Typical power supply characteristics are given in
Figures 2(b) and 2(c).
Power Supply Considerations for CA3059
The output current available from the internal supply may not
be adequate for higher power applications. In such applications an external power supply with a higher voltage should
be used with a resulting increase in the output level. (See
Figure 4 for the peak output current characteristics.) When
an external power supply is used, Terminal 5 should be connected to Terminal 7 and the synchronizing voltage applied
to Terminal 12 as illustrated in Figure 5(a).

2. Set the value of Rp and sensor resistance (Rx) between
2kn and 100k(!
3. The ratiO of Rx to Rfl typically, should be greater than 0.33
and less than 3. If either of these ratios is not met with an
unmodified sensor over the entire anticipated temperature range, then either a series or shunt resistor must be
added to avoid undesired activation of the circuit.
If operation of the protection circuit is desired under conditions other than those specified above, then apply the data
given in Figure 12.
External Inhibit Function for the CA3059
A priority inhibit command may be applied to Terminal 1. The
presence of at least +1.2V at 1O~A will remove drive from
the thyristor. This required level is compatible with DTL or
T2L logic. A logical 1 activates the inhibit function.
DC Gate Current Mode for the CA3059

Operation of Built-In Protection fOr the CA3059
A special feature of the CA3059 is the inclusion of a protection circuit which, when connected, removes power from the
load if the sensor either shorts or opens. The protection circuit is activated by connecting Terminal 14 to Terminal 13 as
shown in the Functional Block Diagram. To assure proper
operation of the protection circuit the following conditions
should be observed:
1. Use the internal supply and limit the external load current
to 2mA with a 5kO dropping resistor.

Dimensions In parentheses are in millimeters and are derived from
the basic Inch dimensions as Indicated. Grid gradations are in mils
(10-3 Inch).

Connecting Terminals 7 and 12 disables the zero-crossing
detector and permits the flow of gate current on demand
from the differential sensing amplifier. This mode of operation is useful when comparator operation is desired or when
inductive loads are switched. Care must be exercised to
avoid overloading the internal power supply when operating
in this mode. A sensitive gate thyristor should be used with a
resistor placed between Terminal 4 and the gate in order to
limit the gate current.

The photographs and dimensions represent a chip when tt is par of
the wafer. When the wafer is cut Into chips, the cleavage angles are
57" instead of 90° with respect to the face of the chip. Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

DtMENSIONS AND PAD LAYOUT FOR CA3059H AND CA3079H

5-14

HV-240SE

HARRIS
SEMICONDUCTOR

World-Wide
Single Chip Power Supply

April 1994

Features

Description

• Direc1 AC to DC Conversion

The HV-2405E is a single chip off line power supply that con:
verts world wide AC line voltages to a regulated DC voltage.
The output voltage is adjustable from 5V oc to 24Voc with an
output current of up to 50mA. The HV-2405E can operate
from input voltages between 15Vrms and 275Vrms as well
as input frequencies between 47Hz to 200Hz (see Table 1 in
section titled "Minimum Input Voltage vs Output Currenf' for
details).

• Wide Input Voltage Range •••••••••. 15Vrms-275Vrms
• Dual Output Voltages Available
• Output Current. .••••........•.....•.. up to 50mA
• Output Voltage .....•........• , ......... 5V to 24V
• Line and Load Regulation ....••.............. <2%

The wide input voltage range makes the HV-2405E an excellent choice for use in equipment which is required to operate
from either 240V or 120V. Unlike competitive AC-DC convertors, the HV-2405E can use the same external components
for operation from either voltage. This flexibility in input voltage, as well as frequency, enables a single design for a
world wide supply.

• UL Recognition, File # E130808

Applications
• Power Supply for Non-Isolated Applications
• Power Supply for Relay Control
• Dual Output Supply for OFF-LINE Motor Controls

The HV-2405E has a safety feature that monitors the incoming AC line for large dv/dt (Le. random noise spikes on AC
line, initial power applied at or near peak line voltage). This
inhibit function protects the HV-2405E, and subsequent circuitry, by turning off the HV-2405E during large dv/dt transients.This feature is utilized to ensure operation within the
SOA (Safe Operating Area) of the HV-2405E.

• Housekeeping Supply for Switch-Mode Power
Supplies

Ordering information
PART NUMBER

TEMPERATURE
RANGE

The HV-2405E can be configured to work directly from an
electrical outlet (see Figure 1) or imbedded in a larger system (see Figure 7). Both application circuits have components that will vary based on input voltage, output current
and output voltage. It is important to understand these values prior to beginning your design.

PACKAGE

HV3-2405E-5

OOC to +75°C

8 Lead Plastic DIP

HV3-2405E-9

-40oC to +85°C

8 Lead Plastic DIP

CAUTION: This Product Does Not Provide Isolation From The AC line. See "General Precautions". Failure to use a properly rated
fuse may cause R1 to reach dangerously High Temperature or Cause the HV-240SE to Crack or Explode.

Functional Diagram

Pinout
HV-240SE (PDIP)
TOP VIEW

I

ACRETURN 0 8 ACHIGH
PRE-REG 2
7 NC
CAP (C2)
GND 3
INHIBIT 4

SWITCHING
PRE-REGULATOR

UNEAR
POST-REGULATOR

I

:Ii. IE

~

I

DA1........ SM····DA2'" -.. -. --"Q;" --_.. _. -:

AC
;HIGH
R1
<>-F""U'\,S...EJVo.IIr--8-<:.....""'"---4~-

...t--.......---.

,,

,6
r - - - -....
: -0 VOUT

,,

I

6 VOUT

5 VSENSE

'IE

:

5

,..----0
, SENSE

,

C1

RB11 :

40--+--........
BANDGAP
REFERENCE

,,,
,
RB10:
,,
,,
,
,,
: (1,3)

AC
RETURN

AC
-2 -_•• _•.• -- -- -- -- -- .•, RETURN

(1,3)
C2

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright

© Harris Corporation 1992

5-15

File Number

2487.5

o

If)

II:

O~

o

II:
I-W

0>

c(~

o

Specifications HV-240SE
Absolute Maximum Ratings

Thermal Information

Voltage Between Pin 1 and 8, Peak ........................ ±SOOV
Voltage Between Pin 2 and 6 ........................... ISV
Input Current, Peak •••.•••••....••.....••...•••..•.... 2A
Output Current ..•••..••.•.••....••..•..•••.•.••... l00mA
Output Voltage ...................................... 34V

Thermal Resistance
9JA
Plastic DIP ................................... ISCf'CIW
Maximum Junction Temperature •••••••••••••••••••••• +15Cf'C
Storage Temperature Range .................. -65°C to +15Cf'C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only raUng and operation
01 the device at these or any other conditions above those indicated in the operaUonal sections 01 this specilicaUon Is not implied.

Electrical Specifications

Unless Otherwise Specilied: VIN =264Vms at 50Hz, Cl =0.05I1F, C2 =470IlF, C4 =l11F, VOUT =5V,
lOUT =SOmA, Source Impedance Rl =1500. Parameters are Guaranteed at the SpecifIC VIN and
Frequency Conditions, Unless Otherwise Specified. See test circuit lor Component Location.
HY-2405E-51-9

PARAMETER

CONDITIONS

Output Voltage (At Preset SV)

Output Voltage (At Preset 24V)

Line Regulation

VREF

=OVoc

VREF =19Voc

80Vrms to 264Vrms

(lOUT =SmA to SOmA)

Load Regulation

MIN

TYP

MAX

UNITS

+25°C

4.75

5.0

5.25

V

Full

4.65

S.O

S.35

Y

+2SoC

22.8

24.0

2S.2

V

Full

22.32

24.0

25.68

V

+2SoC

-

10

20

mV

Full

-

IS

40

mV

20

mV

TEMP

+2SoC

-

Full

-

Output Current

Full

50

Output Ripple (Vp-p)

Full

-

24

Short Circuit Current Limit

Full

-

70

Full

-

0.02

+2SoC

-

2

Output Voltage TC
Quiescent Current Post Regulator

11Voc to 30Voc on Pin 2

40

mV

-

rnA

-

mV

-

Test Circuit
+

I: I
r!-J ~ Fol ~

R1
1son

D

FILTER
NETWORK
AUTOMATIC
TEST
EQUIPMENT

TEST SIGNALS
SHOULD BE
FILTERED TO
PRECLUDE
TRANSIENTS
TO LESS THAN

C1
O.OsI'F

10Vl1'8

VREF

l
r

DUT

~=-ti_lC3
fC2 ~T1s0PF
470I'F

5-16

VOUT

C4

11'F

.

mA
%/'C
mA

HV-2405E

Application Information
OPERATING CONDITIONS
VIN • SOVrms TO 275Vrma
FREQUENCY" 50Hz to 60Hz
loUT. OmA to SOmA
Vour " SV + VZI

r-----II----t-JW~----.....-...;..."""'" AC HIGH

R2

·· -!:

220Kn:

AC RETURN

·· Vour
ril-...,..-......--.-,HI---I.---O

··•
··••
·
•
~--------""::"--!!---'"::------------------------- .. ---------- -.::.-----!·
R3 :
3.9Kn:

COMPONENT UST
C1 • 0.1 ~F, AC RATED
C2. 470~F,15V + Vour, ELECTROLYTIC
C3 " 20pF, CERAMIC
C4 =1 O~F, Vour + 10V, ELECTROLYTIC
C5 " 0.047~F, 10V
Z1 • Vour - 5V, 1/4W
Z2 = 5.W, 1N5231/A OR EQUIVALENT
Q1 ,,2N2222 OR EQUIVALENT

FUSE .1/4A
R1.100ll,SW
R2 " 220kll, 1W
R3 " 3.9kll, 1/4W
R4" S.6kll, 1/4W
RS " 3.3ll, 1/4W
R6 5.6kll, 1/4 W

=

FIGURE 1. OFF LINE WORLD-WIDE SUPPLY (loUT ~ 50mA)

Off line World Wide Supply (lOUT ~ SOmA)
Figure 1 shows the recommended application circuit for an
off line world wide supply. The circuit will deliver an output
voltage of 5V to 24V and an output current from 0 to 50mA.
The value of C2 can be reduced for applications requiring
less output current (see section titled "Optimizing Design" for
details). For a basic understanding of the internal operation
of the HV-2405E reference section titled "How the HV-2405E
Works".
The following is a detailed explanation of this application circuit:
Basic Operation
When the input voltage goes positive an internal switch
connects pin 8 to pin 2 allowing current to flow through R1 to
charge up C2. When the voltage on C2 reaches a
predetermined voltage the switch opens and the charging of
C2 stops. R1 limits the input current and along with C1
provides a snubber for the internal switch. A linear regulator
takes current from C2 further regulating the voltage and
limiting the ripple at pin 6. The voltage at pin 6 is equal to
VZ 1 +5V. The linear regulator also provides output current
limiting. The capacitor C4 on pin 6 is required for stability of
the output.
Input Current Umitlng Circuit
The external components in the shaded area of Figure 1 perform two functions. The first is to shut down the HV-2405E in
the presences of a large voltage transients and the second is
to provide input current limiting.

Resistors R2, R3 and capacitor C3 monitor the input voltage
and turn on 01 which shuts down the HV-2405E when the
input voltage or the dv/dt is too large. This network anticipates the voltage applied to pin 8, since R1 and C1 add
several micro seconds delay, and turns off the HV-2405E
when a predetermined input voltage is exceeded. The difference between R3/C3 and R1/C1 time constants ensures
that the HV-2405E internal switch opens before the voltage,
and thereby the input current, is allowed to rise to a dangerous level at pin 8.The input voltage at which the HV-2405E is
turned off, is dependent upon the voltage on C2. The higher
the voltage on C2 the larger the input current that the HV2405E can safely turn off. For a detailed explanation of why
the voltage on C2 determines the maximum input current
that the HV-2405E can safely turn off, reference "Start-up" in
section titled "How the HV-2405E Works".
Input current limiting is provided when the voltage at the
base of 01 forward biases the base to emitter junction, turning off the internal switch. The voltage required at the base
to turn on 01 increases as the voltage on C2 increases the
emitter voltage. When the voltage on C2 is >10V, the emitter
voltage is held constant by Z2 and the maximum input current is set by resistors R2, R3, R4 and R5 (see section titled
"Design Equations" for more details).
Operation
The circuit in Figure 1 ensures operation within the SOA of
the HV-2405E by limiting the input current to <500mA when
the voltage on C2 equals zero and <2A when the voltage on

5-17

HV-2405E
Application Information

(Continued)

C2 is greater than 10V. The circuits operation is illustrated in
Figure 2 and Figure 3. In Figure 2 the initial current pulse is
approximately 400mA when VC2 = OV and gradually
increases to approximately 1.SA when C2 = 10V. Also notice
that after the 17th line cycle the input current is approximately 1.4A. At this point C2 is fully charged. The input current required to maintain the voltage on C2 is less than the
current to charge it and the circuit has reached steady state
operation. Since the steady state current is less than the
input current limit. the circuit in the shaded area is off and no
longer has any effect.

Design Equations for Input Current Limiting
Initial Start-Up
Assume: VC2 = OV. Rl = 1000. R2 = 220kO. R3 = 3.9kO,
R4 = 5.6kO, R5 = 3.3kO, R6 = 5.6kO, VBE = 0.54V, ITRIG =
60llA, VPin 8 - VPin 2 = 3.5V at low inputs currents. VIN1 =
Voltage on AC high when input current limit circuit is invoked
(VC2 OV)

=

IIN(min)=
VIN' =

OFFUNE WORLD-SIDE SUPPLY
lOUT = 50mA

VIN' - VPin 8 - VPin 2
R1
R2 + R3
R3

R4 (R5 + R6)
(V BE + R4 + R5 + R6 x ITRIG )

VIN' = S7.41 (0.54 + 3.437kQ x 601lA) = 42.B4V
IIN(min) -

42.84-3.S
100
- 393mA

(EO 1)

(Ea. 2)
(Ea. 3)
(Ea. 4)

Equation 1 through Equation 4, for the given assumptions,
predict that the initial input current will be limited to 393mA.
The following equations can be used to predict the maximum
input current during start-up.
Assume: VC2 > 10V, Rl = 100n. R2 = 220kn. R3 = 3.9kn.
R4 = 5.6kO, R5 = 5.6kO, R6 = 3.3kO, VSE = 0.54V, ITRIG =
60llA, Vz = 5.1V, VPin 8 - VPin 2 = 6V at high inputs currents,
V Pin 2 - V Pin 6, V 1N2 = Voltage on AC high when input current
circuit is invoked (VC2 > 10V).
IIN(max) =

OFFLINE WORLD-WIDE SUPPLY

(500VIDIV)

Ii H~J~t\~Tn~~I\~E(A~J"'\M~Hf ~\~~

r~~·vlij.vV~tVr~ {lftVV ~:v(V~~hW~Ji

lI~lLi

,,,.,,'",..,
[, j! j 1· J I' J j
i " " " II I;
(1AIDIV) " ... W,or ,;, n _
. .~
Ip.O.8A :,H.
. . . ~: . . ; . . . . .•. . . . . . !
-

VC2"

(10VIDIV)

,

,.,........!'""

(Ea. 5)

J

R2+R3 [ R 4 R S
R4
VIN2 = ~ (Vse + R4 + RS x ITRIG + R4 + RS V12 (Ea. 6)

FIGURE 2. START UP OPERATION

Under short circuit operation the maximum voltage on pin 2
is less than 10V and the input current limiting circuit is
invoked. Figure 3 shows that under output short circuit conditions. the input current is limited to about SOOmA. The
effects on the output current when the input current limiting
circuit is invoked is illustrated in Figure 6.

VIN=264Vrms

VIN2 • Vour' (VPin 8 - VPin 2) - (VPin 2 - VPin .)
R1

:::!

~~

'i

:1

VOUT " I
(5VIDIV) i... ..................................................................................I!.M!L(§.Qm~!.Y.lj

FIGURE 3. SHORT CIRCUIT OPERATION

VIN2 = 57.41 [0.54+ (2.076kQx 601lA) + (0.6292 x S.1))
222 - VOUT -6 -6
= 2.0SA at VOUT = 5V
IIN(max) =
100
IIN(max) =

222 - VOUT -6-6
100

= 1.B6A at VOUT = 24V

(Ea. 7)
(Ea. B)
(Ea. 9)

Equation 5 through Equation 9 predict the maximum input
current will be limited to less than 2.05A. In practice at 5V
operation the current is less than predicted due to the low
bias current through Z2.
Setting The Output Voltage
The circuit shown in Figure 1 provides a regulated 5V to 24V
DC and is set by adjusting the value of Zl. The output voltage of the HV-2405E (pin 6) is set by feedback to the sense
pin (pin 5). The output will rise to the voltage necessary to
keep the sense pin at 5V. The output voltage is equal to the
Zener voltage (VZ1 ) plus the 5V on the sense pin. For a 5V
output, pin 5 and pin 6 would be shorted together. The output voltage has the accuracy and tolerance of both the Zener
diode and the band-gap of the HV-2405E (see Figure 16).
The maximum output voltage is limited by ZS2 to - 34V DC '
ZB2 protects the output by ensuring that an overvoltage condition does not exist. Note: the output voltage can also be set
by placing a resistor (1/4W) between pin 5 and pin 6. If a
resistor is placed between pin 5 and pin 6 an additional lV
per 1m (±10%) is added to the 5V output.

5-18

HV-240SE

Application Information

(Continued)

Optimizing Design (World-Wide Supply)

NOTE: Under short circuit conditions the Po in R1
decreases to 1.2W Due to fold back current limiting (lOUT
20mA, Reference Figure 6).

=

Selecting the Storage Capacitor C2
For applications requiring less than SOmA or the full input
voltage range, the value of C2 can be reduced for a more
cost effective solution. The minimum C2 capacitor value is
determined by the intersection between the maximum input
voltage and the output current curve in Figure 4. (Note, for
SOHz operation see Figure 19 in section titled "Typical Performance Curves".) Advantages of making C2 as small as
possible are:

OFFlINE WORLD-WIDE SUPPLY (R1 • 1000)
6
5

~

~
iii

• Reduced total size and cost of the circuit.

I

~
~

!:l

g

~

'""-i!!:

120
90

I

60

I

/

I

I
L

I

I

I.

V

I

0

0

75100

~
"-

~

1

~

0
0

~

10

~

V

120Vrm.-

20
30
40
LOAD CURRENT (mA)

50

FIGURE 5. POWER DISSIPATION IN R1 vs LOAD CURRENT

Operation Information
Effects of Temperature on Output Current:
Figure 6 shows the effects of temperature on the output
current for the circuit shown in Figure 1. Figure 6 illustrates
operation with the output configured for SV. Temperature
effects on the output current for VOUT
24V operation is
similar. The foldback current limiting is the result of reduced
voltage on C2. The circuit delivers SOmA output current
across the specified temperature range of -40°C to +8SoC
for all output voltages between SV and 24V. The effect of
decreasing the value of C2 (470I1F) reduces the maximum
output current (Le. moves curve to the left). For all C2 values
selected from Figure 4 (assuming tolerance and temperature
coefficient are taken into account) the circuit meets the
expected output current across the above mentioned
temperature range.

=

J

30

./V/V

is
a: 2
w

Consideration should be given to the tolerance and temperature coefficient of the C2 value selected. (Note; momentary
peak output current demands should be considered in the
sizing of C2. Increasing the output capacitor C4 is another
way to supply momentary peak current demands.)
OFFUNE WORLD-WIDE SUPPLY
275
--3SmA/I
240
--10mA
210
slomA
180
w 150
2SmA

./

./

3

III

• Reduced start up time.

.-

240vrm~

~ 4

220

330

470

C2{jtF)

FIGURE 4. MINIMUM C2 VALUE vs INPUT VOLTAGE
The following example illustrates the method for determining
the minimum C2 value required:
EXAMPLE
Requirements: VOUT
120Vrms, 60Hz.

= SV to 24V,

lOUT

OFFUNE WORLD-WIDE SUPPLY

= 3SmA, V1N(max) =
~ 4
CI

Circuit efficiency is limited by the power dissipation in R1.
The power dissipation for 240Vrms and 120Vrms is shown in
Figure S.

g

For input voltages other than 240Vrms or 120Vrms equation
10 can be used to determine the power dissipation in R1.
(Ea. 10)

Pd=2.B "Rl Vrms (IOUT)3

=

=

= 240Vrms,

+ssoc .......

.,. \

w

Determining the Power Dissipation In R1

Example: R,
100n, Input Voltage
SOmA, Po 4.8W

,

5

For the given conditions, the minimum C2 value (from Figure
4) is determined to be 22OIlF.

lOUT

=

~

3

./

~

'"
"~

2

/'

'"0

V

~

1

F
I
0

10

r
20

1\
+2SoC -

.J..o-"""

,

V

_40°C ~

.,. --I

1\

rl
~
~

I'
3D

40 50 60 70 so
OUTPUT CURRENT (mA)

9D

FIGURE 6. OUTPUT CURRENT vs TEMPERATURE

S-19

100

o
0"

O~
0"

.,.W

0>

cC~

o

HV-2405E

Application Information

(Continued)

Minimum Input Voltage vs lOUT
Table 1 shows the minimum input voltage range as a
function of output current. Notice that the HV-240SE can
deliver SV at 10mA from a source voltage as little as 1SVrms
and requires a minimum of SOVrms to deliver 24V at SOmA.
TABLE 1. MINIMUM INPUT VOLTAGE vs OUTPUT CURRENT

Recommended value = 470l'F electrolytic (±20%), unless
otherwise specified.
C3 Feed Forward Capacitor
C3 is part of the input Current limiting circuitry shown in
Figure 1. C3 detects large voltage transients on the AC line
and turns off the HV-240SE by turning 01 on.
C3 = 20pF (20%), breakdown voltage >SOOV.

10mA

loUT
2SmA

3SmA

SOmA

SV

ISVrms

21Vrms

2SVrms

30Vrms

24V

31Vrms

38Vrms

41Vrms

SOVrms

VOUT

C4 Output Filter Capacitor
C4 is required to maintain the stability of the output stage.
Larger values may help in supplying short momentary
current peaks to the load and improve output ripple during
start-up.

Component List (World Wide Supply 10V. This results in limiting the maximum input current
to less than 2A.

(EO. 10)

Pd=2.8 "Rl Vrms (loUT)3

Wirewound resistors are recommended due to their superior
temperature characteristics.
R1

= lOOn (±10%)

Z2

=S.1 V, 1N5231 A or equivalent

Q1 Input Current Limiting Transistor
01 shuts down the HV-2405E when the input voltage or dV/dt
is too large.

R2, R3, R4, RS and R6 Resistors
R2, R3, R4, RS and R6 set the bias level for 01 that
establishes the minimum and maximum input current limit
during start-up.
Resistor values (±S%):
R2 = 220k!l,1W
R3 = 3.9k!l, 1/4W
R4 = S.Sk!l,1/4W

Z2 Clamp Diode

V CEO
01

=40V min.

=2N2222 or equivalent

Imbedded Supply (lOUT ~OmA)

RS = 3.3k!l, 1/4W
RS = S.Sk!l, 1/4W

C1 Snubber Capacitor
C1 and R1 form a low pass filter that limits the voltage rate
of rise across SA 1 (the main current carrying SCR of the
HV-2405E) and therefore its power dissipation.
C1

=0.11'F (±10%) AC rated, metallized polyester.

C2 Pre-Regulator Capacitor
C2 is charged once each line cycle. The post regulator
section of the HV-2405E is powered by C2 for most of the
line cycle. If the application requires a smaller input voltage,
the value of C2 can be reduced from that shown in Figure 1
(see section on ·Optimizing Design" for details). Note:
capacitors with high ESR may not store enough charge to
maintain full load current. The voltage rating of C2 should be
about 10V greater than the selected Your.

5-20

COMPONENT UST
FUSE .1/4A
C2. 330fLF, 15V + VOUT, ELECTROLYTIC
R1 • 1500, 3W
C3 = 150pF, CERAMIC
R2.2.70,1/4W
C4 = 10..F, VOUT+ 10V, ELECTROLYTIC
C1 • 0.1fLF, AC RATED Z1 =VOUT -SV, 1/4W
FIGURE 7. IMBEDDED SUPPLY loUT';; 30mA

HV-2405E

Application Information

(Continued)

For applications requiring 30mA or less and not directly off
line (Le. filter network preceding supply), the external transistor and associated resistors in Figure 1 can be replaced
with a single 1/4W resistor R2 and capacitor C3 (Figure 7) if:
(1) The filter network reduces the input dvldt to less than
10V/I's (ensures sufficient pin 2 voltage at turn off), (2)
Source resistor Rl equals 150Q (limits the maximum input
current) and (3) Inhibit Capacitor C3 equals 150pF (turns off
the HV-2405E during large voltage tranSients).
For applications where EMI (conductive interference) is a
design requirement, the circuit shown in Figure 8 is the recommended application circuit. This circuit delivers an output
voltage of 5V to 24V with an output current from 0 to 30mA
and passes VDE 0871 class "S" test requirements for conductive interference with a resistive load.

Operation
The operation of the imbedded supply is illustrated in Figure 9
and Figure 10. Figure 9 shows operation wijh a 30mA load
and Figure 10 with the output short circuited. Notice that In
both cases, the inhibit function of the HV-2405E prevents the
circuit from turning on when the input vottage was applied
near the peak line voltage. Also notice the initial current pulse
(Figure 9) is approximately 1.6A and decreased to lA within
40ms. This decrease in the input current results when the
charging current required to maintain the vottage on C2
decreased. The effect of the series resistor (R2) is illustrated
by the small voltage spike on the Vpin 2 trace. This vottage
spike increases the voltage on pin 2 to the 10V trip point
sooner in the cycle, thereby limiting the input current.

+
ZI

~:~~~~PJV~MMt1~
i'

INPUT CURRENT

:

!

~

:

:

:

;uJ
..•

(IAIDIV):
10~F

.:!

.

".

.

...

loUT

ACRETURN

=30mA, VOUT =5V

COMPONENT UST

=

:

(SV~~~
t
,.."'"'"..."..._"'"".....".............."'" . .~.::· . :~.:."'" ...I'.M§.,{~.~m~lv.iJ

C3
150pF

FUSE = 1/4A
Rl.150Q,3W
R2 = 2.7Q, 1/4W
Cl 0.1 ~F, AC RATED
C2" 330~F,15V + VOUT,
ELECTROLYTIC

:

:~~~

C4

FILTER
NETWORK

.

FIGURE 9. START UP OPERATION

C3 = IS0pF, CERAMIC
C4 .10~F, VOUT + 10V,
ELECTROLYTIC
ZI " VOUT -SV, 1/4W

L1 " 2.2mh, ~" 2000
CO" 0.33"F, AC RATED

FIGURE 8. IMBEDDED SUPPLY WITH EMI FILTER (loUT ~ 30mA)

Basic Operation
When power is initially applied the filter network reduces the
magnitude of any transient noise spikes that might result in
operation outside the SOA of the HV-2405E (see Start-up in
section titled "How the HV-2405E Works" for and explanation
of the SOA). When the voltage on pin 8 goes positive an
internal switch connects pin 8 to pin 2 and C2 starts to
charge through Rl and R2. When the voltage on pin 2
reaches a predetermined voltage the switch opens and the
charging of C2 stops. Rl limits the input current and along
with Cl provides a snubber for the internal switch. R2 also
has the effect of limiting the input current by increasing the
voltage on pin 2 sooner in the cycle. A linear regulator takes
current from C2 and provides a DC voltage at pin 6. The voltage at pin 6 is equal to VZ1 + 5V. The inhibit capacitor (C3)
provides protection from large input voltage transients by
turning off the HV-2405E and the output capacitor C4 provides stabilization of the output stage.

5-21

OUTPUT SHORT CIRCUITED

FIGURE 10. SHORT CIRCUIT OPERATION

HV-240SE

Application Information

(Continued)

Setting The Output Voltage

Determining the Power Dissipation In R1

The circuits shown in Figure 7 and Figure 8 provide a regulated 5V to 24Voc output voltage that is set by adjusting the
value of Z1. The output voltage of the HV-2405E (pin 6) is
set by feedback to the sense pin (pin 5). The output will rise
to the voltage necessary to keep the sense pin at 5V. The
output voltage is equal to the Zener voltage (Vz 1) plus the 5V
on the sense pin. For a 5V output, pin 5 and pin 6 would be
shorted together. The output voltage has the accuracy and
tolerance of both the Zener diode and the band-gap of the
HV-2405E (see Figure 16). The maximum output voltage is
limited by ZS2to = 34V oc. ZS2 protects the output byensuring that an overvoltage condition does not exist. Note: the
output voltage can also be set by placing a resistor (1/4W)
between pin 5 and pin 6. If a resistor is placed between pin 5
and pin 6 an additional1V per ko (±100/0) is added to the 5V
output.

Circuit efficiency is limited by the power dissipation in R1.
The power dissipation for 240Vrms and 120Vrms is shown in
Figure 11.
For input voltages other than 240Vrms or 120Vrms Equation
10 can be used to determine the power dissipation in R1.
Pd=2.8 "R1 Vrms (IOUT)3
IMBEDDED SUPPLY (R1 ,,'500)

~

z

~

240V,/

Ilj

2

III

IS
a:
w

Optimizing Design (Imbedded Supply)

4
3

0

0

Selecting the storage capacitor C2

~

/

1

~
II.

For applications requiring less than 30mA, the value of C2
can be reduced for a more cost effective solution. The minimum C2 capacitor value vs. output current is presented in
Table 2. Advantages of making C2 as small as possible are:

(Ea. 10)

~~

120Vrms

30
10
20
LOAO CURRENT (mAl
FIGURE 11. POWER DISSIPATION IN R1 vs LOAD CURRENT
0

Operation information
Effects of Temperature on Output Current

• Reduced total size and cost of the circuit.
• Reduced start up time.
Consideration should be given to the tolerance and temperature coefficient of the C2 value selected. (Note: momentary
peak output current demands should be considered in the
sizing of C2. Increasing the output capacitor C4 is another
way to supply momentary peak current demands.)
TABLE 2. IMBEDDED SUPPLY
R1 -1500
VIN
264Vrms

R2=2.70

FREQ.

C2

50Hz

330(.tF
220(.tF
100(.tF
50(.tF

264Vrms

132Vrms

132Vrms

60Hz

50Hz

60Hz

330(.tF
220(.tF
100(.tF
50(.tF
330(.tF
220(.tF
100(.tF
5O(.tF
330(.tF
220(.tF
100(.tF
50(.tF

lOUT
30mA
24mA
14mA

Figure 12 and Figure 13 show the effects of temperature on
the output current for the imbedded supply (R2 = 2.70). Figure 12 illustrates VOUT = 5V operation and Figure 13 iIIustrates VOUT = 24V operation. The imbedded supply (R2
2.70) delivers 30mA output current across the specified temperature range of -40°C to +850 C for all output voltages
between 5V and 24V. The effect of decreasing the value of
C2 (330(.tF) reduces the maximum output current (i.e. moves
curve to the left). For all C2 values selected trom Table 2
(assuming tolerance and temperature coefficient are taken
into account) the circuit meets the expected output current
across the above mentioned temperature range.
IMBEDDED SUPPLY

=

6

SmA
30mA

5

27mA
16mA
9mA
30mA

w 4

~

~

+85OC, __

;.J

§! 3

I

l-

+2s0 C

::)

S2

30mA
16mA

1
0

,
~

~

'"
7

T

j

J~oc

0

SmA
30mA
30mA
16mA
9mA

~

~~

I

80
20
30
40
50
60
70
OUTPUT CURRENT (mA)
FIGURE 12. OUTPUT CURRENTvs TEMPERATURE (R1= 1500,
R2 = 2.70, C2 = 330(.tF)

5-22

0

10

HV-240SE
Application Information

(Continued)

IMBEDDED SUPPLY

;,,:o~o

25

~
w 20

~

g

...:>>

15

+SSoC

~

~ 10

:>
0

.... ~

o
o

10

20

30

40

50

~

60

C3 Inhibit Capacitor
C3 keeps the HV-2405E from turning on during large input
voltage transients.
C3 = 150pF (10%)
C4 Output Filter Capacitor

V

)

5

330IlF electrolytic (±20%),unless

Recommended value
otherwise specified.

30

C4 is required to maintain the stability of the output stage.
Larger values may help in supplying short momentary
current peaks to the load and improves output ripple during
start-up.

V

70

80

90

100

C4 = 10llF (±20%)

OUTPUT CURRENT (mAl

FIGURE13. OUTPUT CURRENT vs TEMPERATURE (R1 =1500,
R2 = 2.70, C2 = 33011F)

Z1 Output Voltage Adjust

Component List (Imbedded Supply ::;30mA)
Fuse

Z1 is used to set the output voltage above the 5V reference
on pin 5 (see section titled ·Setting The Output Voltage" for
more details).

Opens the connection to the power line should the system fail.

Z1 = VOUT - 5V,1/4W

Recommended value: 1/4AG

Note, the wattage rating is different when configured as a
dual supply (see dual supply section for on how to determine
wattage).

R1 Source Resistor
R1 limits the input current into the HV-2405E. Needs to be
large enough to limit inrush current when C2 is discharged
fully. The maximum inrush current needs to be limited to less
than 2A (Vpeak I R1 < 2A). The equation for power dissipation in R1 is:
Pd =2.8 ...J R1 Vrms (IOUT)3
Wirewound resistors are recommended due to their superior
temperature characteristics.
R1 = 1500 (±10%)

!/)

C~

An ideal application, taking advantage of the low voltage
operation, would be thermostat controls were 28Vrms is supplied via a transformer. In this application the HV-2405E
could deliver a regulated 5V at 40mA with a power dissipation in R1 (R1= 20n) equal to 530mw. The current limiting
components, in Figure 1, are not required at this low input
voltage level. See Figure 23 and Figure 24 for output vs temperature.
AC
HIGH

R2 Series Resistor
R2 limits the input current by boosting the voltage on pin 2
sooner in the cycle.

R2

00::

Low Input Voltage Supply (lOUT 

c(ts
o

HV-240SE
Application Information

(Continued)
r--_ _-II-_ _~~INI,__-...~F"U.:;;SE~ AC HIGH

COMPONENT UST

~OKn

FUSE .1/2A
R1 .. 100n, 5W
R2 .. 220kn, 1W
R3 .. 3.9kn, 1W
R4 .. S.6kn, 1/4W
RS .. 3.30, 1/4W
R6 • 5.6kn, 1/4 W
C1 • O.1I'F, AC RATED
C2 .. 470I'F, 1SV + VOUT, ELECTROLYTIC
C3 • 20pF, CERAMiC
C4 -10I'F, VOUT+ 10V, ELECTROLYTIC
CS = O.047I'F, 10V
21 .. VOUT - SV, 1/4W
Z2. S.1V, 1NS231/A OR EQUIVALENT
Q1 • 2N2222 OR EQUIVALENT

-!-

1A1f-t_:_-_--I-----o

VOUT- SV + VZ1

-!'------+----0
R3
3.9Kn

AC RETURN

AC RETURN

VOUT- SV

-!-

AC RETURN

FIGURE 15. DUAL SUPPLY

Dual Supply (lOUT 

S~r-;--+--r-4--+--r-4--+--r-;--+--r-,
w

./

7-

10mi_

1:25

./

~

I- \
I-

~ ~t:jt:l=~~::t==t=1~t==t=1r=r==r~

SOmA

~

~ 22r-;--+--r-;--+--r-;--+--r-;--+--r-,

I

\
25mA

~

i

1/

!: 60
30

o

21

r-4--+-t--+-+-+-1f-+--t--t--t-+--t

__L-~~__L-~~__L-~~__L-~
-40 -30 ·20 ·10 0 10 20 30 40 50 60 70 80 110
TEMPERATURE (OCI

20L-~~

o

75100

220

470

330

e2(1'F)
FIGURE 19. MINIMUM C2 VALUE vs INPUT VOLTAGE 50Hz

FIGURE 20. OUTPUT RIPPLE VOLTAGE vs TEMPERATURE

0.65

24

0.60
22

1:>

1 1

20
18

~

16

~ 14

w

......

12

if 10
8

1/
4

8

./

~

12

r--

~ 0.45

I---

V
20

24 28 32
loUT (mAl

40

36

44

48

~

FIGURE 21. OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT

o

/"'"

I~

~~~

~ .............. ~

0.25 / ' ~
0.15

~

1/ ~ ~

YOUT=24Y
YOUT,d5Y

/

0.30

0.20
16

_

~ 0.40

... 0.35
5

."..

'-'

0.50

......

."..'

w

..J

k'"

RIPPLE

S

./
". ......

0.55

5

../ : / V
~ V"

~

YOUTs5Y

'"

10

15

20

25
30
lOUT (mAl

35

40

45

50

FIGURE 22. CHIP POWER DISSIPATION vs OUTPUT CURRENT

30

6

~

5

~

\

,

+8r"

o

20

30

40

+250e

'.
IJ -

1\\

........

.40oe
e \
I+75O\

" +Sooe

~'

1

I

oOe

+250C
ooe - - .

-I

r50r~

6

l

\ \

-

+sooe

+750e

I

1 1

I

°ft

•25

o

50 60 70 80 90 100 110 120 130
OUTPUT CURRENT (mAl

20

30

40

50

60

70

I
i'+250e

·r

80

90 100 110 120 130

FIGURE 23. OUTPUT CURRENT LIMIT (5VOUT) 50Hz

FIGURE 24. OUTPUT CURRENT LIMIT (24VoUT) 50Hz

50mA is the Maximum Recommended Output Current

50mA is the Maximum Recommended Output Current

5·28

INTELLIGENT 6
POWERICs
FULL BRIDGES

PAGE
FULL BRIDGE SELECTION GUIDE .......................................................... .

6-2

FULL BRIDGE DATA SHEETS
CA3275

Dual Full Bridge Driver .................................•.••..............

6-3

HIP4010

Power Full Bridge Driver for Low Voltage Motor Drive with Direction and Brake Control ..... .

6-7

HIP4011

Three Phase Brushless DC Motor Controller ....•............•..•.............

6-11

HIP4080

80V/2.5A Peak, High Frequency Full Bridge FET Driver.....•. " ................ .

6-14

HIP4080A

8OV/2.5A Peak, High Frequency Full Bridge FET Driver......................... .

6-28

HIP4081

80V/2.5A Peak, High Frequency Full Bridge FET Driver....... " ...... " ........ .

6-41

HIP4081A

8OV/2.5A Peak, High Frequency Full Bridge FET Driver.......•..... , . " ...•.....

6-54

HIP4082

8OV/1.25A Peak, Current Full Bridge FET Driver .......•.......................

6-67

W

g
a:CD
oJ
oJ

!:)

11..

6-1

Full Bridges Selection Guide

PART
NUMBER

PEAK
OUTPUT
CURRENT
DESCRIPTION

NO LOAD

EACH DRIVE

SUPPLY
VOLTAGE
BIAS/BUS

MAXIMUM
SUPPLY
CURRENT

TARGETED
APPLICATIONS

CA327S

Dual Full Bridge Driver

1SOmA

8V to l6V

20mA

Instrumentation

HIP4Ol0

Low Voltage Motor Drive Power Full
Bridge Driver

O.S5A

3V to 7V

SjIA (Typ)

3V - SV Motors

HIP40ll

3 Phase Motor Controller

5A

10.4V to l3.2V

lSmA

Hall Effect Brushless
Motors

HIP4OSO

Full Bridge FET Driver With
Comparator, High Performance

2.5A

Bias
8V to l6V

l8mA

Class D Amplifiers,
Voice Coil, Motor Control

l8.5mA

Class D Amplifiers, Voice
Coil, Motor Control

Bus
W to SOV
HIP4OSOA

Full Bridge FET Driver UN,
Comparator

2.5A

Bias
9.SV to l6V
Bus
lV to SOV

HIP40Sl

Full Bridge FET Driver, High
Performance

2.5A

Bias
6V to l6V

l6mA

DC-DC Converters,
Motor Control, UPS

l6.SmA

DC-DC Converters,
Motor Control, UPS

6.5mA

UPS, Motor Control

Bus
lVt080V
HIP4OS1A

Full Bridge FET Driver With UN,
High Performance

2.5A

Bias
9.5Vto l6V
Bus
W to 80V

HIP4OS2

Full Bridge FET Driver With UN,
20kHZ-200kHz

1.25A

Bias
9.5V to l6V
Bus
Wto 80V

6-2

CA3275
Dual Full Bridge Driver

April 1994

Features

Description

• Two Full Bridge Drivers

The CA3275 Dual Full Bridge Driver is intended for generalpurpose applications requiring Dual Full Bridge drive or
switching, including direction and pulse-width modulation for
position control. While all features of the IC may not be utilized or required, they would normally be used in instrumentation systems with quadrature coils, such as air-core
gauges, where the coils would be driven at frequencies ranging from 200Hz to 400Hz. The coils are wrapped at 900
angles for independent direction control. Coils wound in this
physical configuration are controlled by pulse width modulation, where each coil drive is a function of the sine or cosine
versus degrees of movement. The direction control is used
to change the direction of the current in the H-Driver coil.

• ± 1S0mA Maximum Current
• Logic Controlled Switching
• Direction Control
• PWM lOUT Control
• 18V Over-Voltage Protection
• 300mA Short-Circuit Protection
• Nomlnal8V to 16V Operation
• Internal Voltage Regulation With Bandgap Reference

Applications
• Dual Full Bridge Driver For Air Core Gauge Instrumentation
• JlP Controlled Sensor Data Displays

The switch rate capability of the IC is typically 30kHz regardless of the inductive load. Over-current limiting is used to
limH short circuit current. Over-voltage protection (in the
range of 18V to 24V) causes the device to shut down the
output current drive. Thermal shutdown limits power dissipation on the chip. The CA3275 is supplied in a 14 lead dualin-line plastic package.

• Speedometer Displays
• Tachometer Displays

w

Ordering Information

• Stepper Motors

PACKAGE

TEMPERATURE

• Slave Position Indicators

-400C to +850C

14 Lead Plastic 01 P

g
a:m
...J
...J

Ii!
Pinout

Block Diagram
CA3275 (PDIP)
TOPVI'2N

•
LA
SENSOR &
CONVERTER
AID, VIF, ETC

MICROPROCESSOR
PHASE, DIRECTION
& PWM CONTROL

CA3275
DUAL·H
DRIVER
LB

CAUTION: These devices are sens~ive 10 electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6-3

SIN

B

.0
cos

File Number

2159.3

Specifications CA3275
Absolute Maximum Ratings

Thermal Information

Operating Vee ••••.•••••••..•••••••••••••••••.•••••• 16V
Transient Vce, 30 Seconds Maximum .••••••••••••••••••• 24V
Peak Vee, 0.4 Seconds Maximum ••••••••••.•••••••••.•• 40V
Maximum Continuous Output Current, .••..•.•••••.•••.•.±l00rnA
Each Drive
Maximum PWM Output Switching Current, •••.••.•.•••.•. ±l50rnA
Each Drive

Thermal Resistance
9JA
PDIP Package. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 10ff'CIW
Power Dissipation, Po
Up to +70oC •••••••.••••••••••••.••••••••••••••• 800mW
Above +70oC .•••••••••••••••••• Derate Unearly at 10mWf'C
Ambient Temperature Range
Operating .•••••••••••••••..••••••••••.••• -40"C to +85°C
Storage .••.•••••••.••.••..••••.•••••.•• -55°C to +150°C
Lead Temperature (During Soldering) •••••••••••••••••• +265°C
At distance 1/16± 1132' (1.59 ± 0.79mm) from case for lOs max
CAUTION: Stresses above those listed in "Absolute Maximum RaYngs" may cause permanent damage to the dsvice. This Is a strsss only mring and opemtlon
of the device at these or any other conditions above those indicated in the opemtionsl sections of this specification Is not implied.

Electrical Specifications TA = -400 C to +B5°C, vee = 16V Unless Otherwise Specified
SYMeOL

MIN

TYP

MAX

UNrrs

Oparating Supply Voltage Range

Vee

B

-

16

V

Supply Current (Note 1)

Ice

-

8

20

rnA

Logic Input, Low Voltage

VIL

-

V

VIH

3.5

-

0.8

Logic Input, High Voltage

V

IlL

-10

IIA

IIH

-

-

10

jIA

Maximum Source Saturated Voltage

VSAT - High

-

1.2

1.75

V

Maximum Sink Saturated Voltage

VSAT- Low

0.5

V

Diff - VSAT

-

0.25

Differential VSAT Voltage, Both Outputs Saturated

10

100

mV

SYMeOL

MIN

TYP

MAX

UNrrS

-

-

2

JlS

2.2

JlS

-

1

JlS

0.4

JlS

-

PARAMETERS

INPUT LEVELS

=OV
Logic Input, High Current, VIH =5V
OUTPUT: RLA =RLB =13BQ
Logic Input, Low Current, VIL

Switching Specifications
PARAMETERS
SOURCE CURRENT (See Figure 3)
Turn-Off Delay

TSC'()FF

Fall Time

TSC.f

Turn-On Time

TSC'()N

Rise Time

T5C-II

-

TSK.()fF

-

SINK CURRENT (See Figure 4)
Turn-Off Delay
Fall Time

TSK.f

Turn-On Time

TSK'()N

Rise Time

TSK-R

NOTE:
1. No load, PWMA

=PWMB =5V, DIR A =DIR B =OV

6-4

-

1.6

JlS

0.4

JlS

0.6

JlS

0.2

JlS

CA3275
Vee

DIRA>-+--I ;~+-------I-------+------'
PWMA>-~---~~~~

Vee

INTERNAL VOLTAGE
SUPPLY WITH
BANDGAP REFERENCE
OVERVOLTAGE PROTECTION
AND THERMAL SHUTDOWN
CIRCUITS

Vee

DIRB>-+--I

w

PWMB>--r--------~i__I

8
a:III
....I
....I

::I

II..

FIGURE 1. CA3275 DUAL FULL BRIDGE DRIVER SCHEMATIC

COILA+
GND
PWMA
PWMB
DIRB

DIRA
GND
GND
COILB+

•
LB

DIRA

_+-_-1____________....1

PWMA--~--------------------------------_J

FIGURE 2. QUADRATURE STEP·MOTOR APPUCATION SCHEMATIC

6-5

RB

CA3275
Vs

t-.....--.~D COIL

OIR

CL INCLUDES PROBE AND TEST CAPACITANCE

OUT
PWM

DIRPULSE

TEST CIRCUIT 1

TEST CONDITIONS: PWM .. OV, Vs .16V
DlR PULSE PARAMETERS:
F.lkHz, W :100"., TR .. TF .. l"., AMPL.4V

10%

TSC-ON

10%

10%

FIGURE 3. SOURCE SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS

TEST CONDITIONS: Vs .. 16V
DIR • OV WHEN TESTING COIL· OUTPUT
DlR • 4V WHEN TESTING COIL + OUTPUT

Vs

t - -....--r> COIL

DIR
OUT

CL CL INCLUDES PROBE AND TEST FIXTURE CAPACITANCE
30pF

PWM

TEST CIRCUIT 2

PWMPULSE
PWM PULSE PARAMETERS:
F.lkHz, W .10OJL., TR. TF.l"., AMPL .. 4V
TSK-ON TSK.R

T SK-OFF

T SK.F

10%

FIGURE 4. SINK SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS

6·6

HIP4010
ADVANCE INFORMATION
April 1994

Power Full Bridge Driver for Low Voltage Motor
Drive with Direction and Brake Control

Features

Description

• Two Independent Complementary MOS Output
Half Bridge Drivers for Operation with Low
Power Supply Voltages

In the Functional Block Diagram of the HIP4010 the four switches
and a load are arranged in an H-Configuration so that the drive
voltage from terminals OUTA and OUTB can be cross-switched to
change the direction of current flow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches 01 and 04 are conducting or in an ON state when current flows from VooA through 01, through the load, and then
through 04 to terminal Vsss; where load terminal OUTA is at a
positive potential with respect to OUTB. Switches 01 and 04 are
operated synchronously by the control logic. The control logic
switches 03 and 02 to an open or OFF state when 01 and 04 are
switched ON. To reverse the current flow in the load, the switch
states are reversed where 01 and 04 are OFF while 02 and 03
are ON. Consequently, current then flows from Voos through 03,
through the load, and through 02 to terminal VSSA ' and load terminal OUTB is then at a positive potential with respect to OUTA.

• Load Switching Capabilities ..••••••••. to O.SA
with +SV Power Supply
• Single Supply Range .•••.•.•••.•.. +3V to +7V
• Split Supply Option with a Negative Reference
for the H-Switch Power Drivers
• Low Standby Current
• CMOSITTL Compatible Input Logic
• Over-Temperature Protection
• Current-Overload Protection
• Over-Current Fault Flag Output
• Direction, Braking and PWM Control

Applications
• DC Motor Driver
• Relay Driver
• Solenoid Driver
• Stepper Motor Controller

The positive power supply terminals are VOOA and Voos and are
internally connected on the chip. Terminals ENA and ENB are
ENABLE Inputs for the Logic A and B Input Controls. The ILF output is an Over-Current Limit Fault Flag Output and indicates a fault
condition for either Output A or B or both. While VOOA Voos and
Vss are the Power Supply reference terminals for the A imd B Control Logic Inputs and ILF Output, the VssA and Vsss Power Supply
terminals are separate and independent from Vss and may be
more negative than the Vss ground reference terminal. This is
accomplished with the use of level shifting in the gate drive circuitry to the NMOS (low-side) output stages.

• Air Core Gauge Instrument Driver

..J
..J
:::I

Ordering Information

• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• +3V to +6V Battery Operated Switch Circuits

PART
NUMBER
HIP4010lB

TEMPERATURE
RANGE
.'!D°C to +8SoC

u..

PACKAGE
20 Lead Plastic sOle (W)

• Logic and Microcontroller Operated Switch

Pinout

Block Diagram
r •••••••••••• .,.,•••••••••••

HIP4010 (SOIC)

••

TOP VIEW

··•
··

VOOA

VDDB

•

i1

·

S2

ENS

Vss

VSSA

ENA

OUTA

A1

A2
ENA
ILF~---_I

Vss
CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6-7

w

g
a:
m

VSSB

File Number

3176.1

Specifications HIP4010
Absolute Maximum Ratings

Reliability Information

Supply Voltage; VOOA and Voos to Vss or VSSA or Vsss .•..•. +7V
Neg. Output Supply Voltage, (VSSA,Vsss) ••.•...•.•.•. (Note 1)
DC Logic Input Voltage (Each Input)
••.•••••••.•••.•..•••••••..•.. (Vss-o·5V) to (VOOA, Vooe -H).5V)
DC Logic Input Current (Each Input) .•...•.••.••.....•... ±20mA
ILF Fault Output Current .•.•••.•..••.•....•.••.•..••...• ±20rnA
Output Load Current, (Self Limiting, See Elec. Spec.) ••..• ±IO(LlMIT)

Thermal Resistance, OJA ••••••..••.•..••••••....•.•• 90oCIW
Power Dissipation
At +25OC (Free Air) •.••••••••••••••••••••••••.•... 1.39W
Above +250 C ••••••••••••••••• Derate Linearly at 11.1 mWf'C
Storage Temperature Range •••••••.•••••••••• -65OC to +lSOOC
Maximum Junction Temperature ••••••••••••••.•••...• +1 SOOC
Lead Temperature (Soldering lOs) •••••••.••••.••..••• +265°C

CAUTION: Strssses abO\18 those listed in 'Absolute Maximum Ratings' may cause permanent damage to the davice. This is a stress only IBting and opBlBtion
of the device at these or any other condiffons above those indicated in the operaffonal sections of this specification Is not implied.

Operating Conditions TA = +25°C, VSUPPly=VOOA = voos= +5V, VSSA = vsse = vss= OV; Unless Otherwise Specified
Input Low Voltage, Vil ••••.••.••••.•.•.••••.••••• OV to -H).8V
Input High Voltage, VIH •.••.•.••••••.•••••••.•• +2.0V to Voo
Input Resistance .••.••••••••..••...•.••••.••.•.•••• 0.5TO

Typical Operating Supply Voltage Range. • • • . • • . • . . .. +3 to +7V
Minimum Logic Supply Voltage (VOo-Vss) .•...••.•.••.•••• +2V
Typical NMOS Driver ROS(ON)' 0.5A Load •...•••••••.••••• 0.80
Typical PMOS Driver ROS(ON), 0.5A Load ..•..•••...••••.•• 1.00

Electrical Specifications

TA = +25°C; VSUPPl.y=VOOA =Vooe = +5V, VSSA = Vsss = Vss = OV; Unless Otherwise Specified

CHARACTERISTICS
Input Leakage Current
Input Voltage Range

SYMBOL

TEST CONDITIONS

ILEAK
VIN

MIN

TVP

MAX

UNITS

-

40

50

pA

0

-

5

V

-

0.8

V

-

V

Low Level Input Voltage

Vil

-

High Level Input Voltage

VIH

2

ILF Output Low, Sink Current

IOH

VOUT = O.4V

3

8

-

rnA

ILF Output High, Source Current

IOl

VOUT = 4.6V

-

-4.5

-1.5

rnA

ILF Output Low (Sink) Current;

IOH

VSUPPly=+3V, VOUT = 0.4V

1.5

3

-

rnA

ILF Output High (Source) Current);

IOl

VSUPPl.y=+3V, VOUT = 2.6V

-0.8

rnA

CIN

-

-1.6

Input Capacitance

TBE

-

pF

0.8

1.5

rnA

4.2

4.5

-

V

-

0.4

0.6

V

Idle Supply Current; No Load
OUTA, OUTB Voltage High
OUTA, OUTB Voltage Low

ISUPPlY
VOH

ISOURCE = 0.5A

VOL

ISINK = 0.5A

OUTA, OUTB Source Current limiting

10(LlMIT)

500

550

620

mA

OUTA, OUTB Sink Current Limiting

-lo(LlMIT)

500

550

620

mA

OUTA, OUTB Voltage High

VOH

2.25

2.5

-

V

OUTA, OUTB Voltage Low

VOL

-

0.5

0.65

V

-

lIS

Response Time: VEN to VOUT
Turn-on: Prop Delay
Rise Time
Turn-off: Prop Delay
Fal/Time

VSUPPly=+3V, ISOURCE = 0.3A
VSUPPly=+3V, ISINK = 0.3A
10 = 0.5A (Note 2)

~H
~

-

IpHl

IF

4
TBE
0.25
TBE

NOTES:
1. Vss Is the required common ground reference forthe logic input switching. The load currents may be switched near the common ground
reference by using a split supply for VOOA and Vooe to VSSA and Vsss. For an uneven split in the supply voltage, the Maximum Negative
Output Supply Voltage to VSSA and Vsse is limited by the Maximum VOOA and Voos to VSSA and Vsse ratings. For all operating conditions
the required positive voitages on VOOA and VDOS must be equal and common.
2. Refer to the TRUTH TABLE and the VEN to VOUT SWITCHING WAVEFORMS. Current, 10 refers to IOUTA or lOUTS as the Output Load
current. Note that ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1,
A2, ENA or 81, B2, ENB inputs. Refer to the TERMINAL INFORMATION TABLE for external pin connections to establish mode control
switching. Figure 1 shows a typical application circuit used to control a DC Motor.

6-8

Specifications HIP4010
TERMINAL INFORMATION TABLE
Positive Power Supply pins; internally connected and must be externally connect to the same Positive Supply (V+).

VOOA' VOOB
VSSA

Negative Power Supply pin; NegaHve or Ground return for Switch Driver A.

VSSB

Negative Power Supply pin; Negative or Ground return for Switch Driver B.

Vss

Common Ground pin for the Input Logic Control circuits.

A1, B1

Input pins used to control the direction of output load current totfrom OUTA and OUTS, respectively. When connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a motor.

A2,B2

Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be controlled from the same logic signal to activate Dynamic Braking of a motor.

ENA, ENB

Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective output is in a
high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and OUTS may be a separately PWM controlled as Half H-Switch Drivers.

OUTA,OUTB

Respectively, Switch Driver A and Switch Driver B Output pins.

ILF

Current limiting Fault Output Flag pin; when In a high logic state, signifies that Switch Driver A or B or both are In a
Current Limiting Fault Mode.
~--------~~----------"Y+

r' .......... __ .......................................................... .
BRAKE

I

OFF

.................................................

·:
··:!
·

CONTROL
LOGICB

ON

·!
:

i:

DIRECT;..;:IO;..:;N=--+-.....--t{

··

CONTROL
LOGIC A

··
·:

ENABLE

;---------------~~~-2----~~~-

..........
ILF

=

(LOGIC
GROUND)

Yo

FIGURE 1. TYPICAL HIP4010 MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL

TRUTH TABLE
SWITCH DRIVER A

SWITCH DRIVER B

INPUTS

INPUTS

OUTPUT

OUTPUT

A1

A2

ENA

OUTA

B1

B2

ENB

OUTB

H

L

H

OH

L

L

H

OH

L

L

H

OL

H

L

H

OL

H

H

H

OL

L

H

H

OL

L

H

H

OL

H

H

H

OL

X

X

L

Z

X

X

L

Z

50%

Your

L = Low logiC level; H = High logiC level
Z =High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Don't Care

""""--9:::0%=-- 50%

SWITCHING WAVEFORMS

6-9

w

g
a:
m
..J
..J

::I

u.

HIP4010

Applications
The HIP4010 is designed to detect load current feedback
from sampling resistors of low lialue in the source connections of the output drivers to VooA, VOOB, VSSA and VSSB
(See Figure 1). When the sink or source current at OUTA or
OUTB exceeds the preset OC (Over-Current) limiting value
of 550mA typical, the current is held at the limiting value. If
the OT (Over-Temperature) Protection limit is exceeded,
temperature sensing BiMOS circuits limit the junction temperature to 150°C typical.
The circuit of Figure 1 shows a Low Voltage motor-driver
application for the HIP4010 as a Full H-Switch. The left (A)
and right (B) H-Switch's are controlled from the A and B
inputs via the A and B CONTROL LOGIC to the MOS output
transistors 01, 02, 03 and 04. The circuit is intended to
safely start, stop, and control rotational direction for a motor
requiring no more than O.SA of supply current. The stop
function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors 01 and
03 are OFF; which cuts-off supply current to OUTA and
OUTB. With the BRAKE terminal Low and ENABLE Inputs
High, either 01 and 04 or 03 and 02 will be driven into conduction by the DIRECTION Input Control terminal. The MOS
output transistor pair chosen for conduction is determined by
the logic level applied to the DIRECTION control; resulting in
either clockwise (CWl or counter-clockwise (CCW) shaft
rotation.

(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through 04 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
04 to the VSSB and VssA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VODA and VOOB to Vss are the Power Supply reference terminals for the Control Logic, the lowest practical
supply voltage for proper logic control should be no less than
2.0V. The VSSA and VSSB terminals are separate and independent from Vss and may be more negative than the Vss
ground reference terminal. However, the maximum supply
level from VODA and VOOB to VSSA or VSSB must not be
greater than the Absolute Maximum Supply Voltage rating of

7V.
Terminals A1, 81, A2, B2, ENA and ENB are internally connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs EN A, ENB, A 1, 81 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level Converters for TIL or CMOS input Logic. These inputs are
designed to typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge.
Proper I.C. handling procedures should be followed.

When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both 02 and 04 are
driven high. Current flowing through 02 (from the motor terminal OUTA) at the moment of Dynamic Braking will continue'to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding

A1
(DlR)

A2
(BRAKE)

ENA
(ENABLE)

t---OUTA

+-------~:::::t=t::~--_{
VSSA

lt~~
;s:-

B1
(DIR)

B2
(BRAKE)

(ENA:~:)

1-DJo.--~ tl~

_ - - - - - - -...

fD4

N·DR

UMIT

VSSB

FIGURE 2. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS

6-10

HIP4011
Three Phase Brushless DC Motor Controller

April 1994

Features

Description

• 3A DC, SA Peak Output Current

The HIP4011 motor driver is intended for three phase Brushless motor control at continuous output currents up to 3A. It
accepts inputs from buffered Hall effect sensors and drives
three motor windings, regulating the current through an
external current sensing resistor, according to an analog
control input. Output "freewheeling" diodes are built in and
output dv/dt is limited to decrease the generated EMI.
Thermal and current limiting are used to protect the device
from locked rotor conditions. A brake control input forces all
outputs to ground simultaneously to provide dynamic
braking, and an internal voltage sensor does the same when
the supply drops below a predetermined switch point. Power
down braking energy is stored in an external capacitor.

• 16V Max. Rated Supply Voltage
• Built-In "Free-Wheeling" Diodes
• Output dv/dt Limited to Reduce EMI
• External Dynamic Brake Control Switch With
Undervoltage Sense
• Thermal and Current Limiting Protects Against
Locked Rotor Conditions
• Provides Analog Current Sense and Reference Inputs
• Decode logic with Illegal Code Rejection

Applications

Ordering Information

• Drive Spindle Motor Controller

PART
NUMBER

• 3 Phase Brushless DC Motor Controller
• Brushless DC Motor Driver for 12V Battery Powered
Appliances

TEMPERATURE
RANGE

HIP4011IS

PACKAGE
15 Pin Plastic SIP
Surface Mount

-400 C to +85°C

• Phased Driver for 12V DC Applications
• Logic Controlled Driver for Solenoids, Relays and
Lamps

Pinout

OUTPUT TRUTH TABLE
HIP4011 (SIP)
TOP VIEW

/'
PGNDPIN
(TAB) MUST BE
ELECTRICALLY
CONNECTED

0

... -$0

'"

,...

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

F== SGND .. SIGNAL GROUND
~

SPD
sv+
~ ISEN
~ OUTA
BCAP
PV+
OUTB
ISEN
~ FBRK
~ OUTC
PV+
SENC
i::::== SENB
SENA
~

§

§
§

FORCE
BRAKE
INPUT*

SENSOR
INPUTS
.. SPEED CONTROL
.. SIGNAL V+
.. ISENSE
.. OUTPUT A
• BRAKING CAPACITOR
.. POWER v+
=
OUTPUT B
=ISENSE
.. FORCED BRAKE
.. OUTPUT C
• POWER V+
.. SENSE INPUT C
.. SENSE INPUT B
.. SENSE INPUT A

FBRK

OUTPUTS
A

B

A

B

C

C

0

0

0

0

1

0

0

0

1

OFF

0

0

1

0

0

0

1

OFF

1

1

0

0

OFF

1

0

0

0

1

0

OFF

0

1

OFF OFF OFF

1

0

,

0

1

0

OFF

0

1

1

0

0

OFF

1

1

1

1

0

X

X

X

1

OFF OFF OFF
0

0

0

• Undervoltage and Force Brake logic truth table
entries are identical.
ox" =Don't Care

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procadures.
Copyright © Harris Corporation 1994
6-11

File Number

2939.3

Specifications HIP4011
Absolute Maximum Ratings

Thermal Information

Supply Voltage, sv+ or pv+ .•.•...•.•.....••.•.•• -1V to +16V
Referred to SGND or PGND (Note 1)
Output Current, Continuous ............................. 3A
Output Current, Peak (Note 2) ........................... 5A
Substrate (PGND) Current. ............................. 1A
Logic Input Current. ........................ -20rnA to +20rnA
(Clamped to SV+ and SGND)

Thermal Resistance
9JA
9JC
15 Lead SIP Power Package. . • • • • • • • • 45°CfW
3°CfW
Power Dissipation (Note 3) ............................ 25W
Junction Temperature Range, Operating ••••.••..•••••• +lSOOC
Storage Temperature Range •.•••••.••••••.••• -55°C to +150°C
Power Dissipation
Up to +125°C without heat sink. • • • • • • • • • • • • • • • • • • •• O.56W
Above +125°C without Heat Sink ••• Derate Linearly at 22mWfOC
Up to +125°C with Infinite Heat Sink. • • • • . . • • • • • • • • •• 9.33W
Above +125°C with Infinite Heat Sink .................... ..
• • • • • .. • • . • • • • • • .. • • • • • • • • .. •Derate Linearly at 333mWI"C
Lead Temperature (During Soldering)
At a Distance 1/16 inch ±1132 inch (1.59mm ±0.79mm)
from Case for lOs Max. • ......................... +265°C

NOTES:
1. PV+ and SV+ are to be tied together. as are PGND and SGND.
2. Operating above the continuous current rating causes a decrease In operating life.
3. Derate power diSSipation above case temperature of +750 C at 0.33 Watts,PC.

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only mtlng and op9mtlon
of the device at these or any other conditions above those Indicated in the opemtlonal sections of this speclliestion is not impHed.

Electrical Specifications TA =+25°C and SV+ =PV+ =10.4V to 13.2V, Unless Otlherwise Specified
PARAMETERS

TEST CONDITION

MAX

UNITS

10

mA

15

rnA

-

-1.5

rnA

150

IIA

-

1.8

V

MIN

TYP

-

-

50

SUPPLY (SV+) CURRENT
No Drive

Outputs Off

With Drive

Outputs On

LOGIC INPUT CURRENT
Sensor Inputs

SENA, SENB & SENC

Brake Input

FBRK

=OV to 3V

=0.8V to 2.4V

-0.5

LOGIC INPUT THRESHOLDS
Sensor Inputs

Logic '0" Input Voltage

-

Sensor Inputs

Logic "1" Input Voltage

3

Brake Input

Logic "0" Input Voltage

Brake Input

Logic "1" Input Voltage

-

V

-

-

0.8

V

2.4

-

-

V

-

-

700

nA

3

mV

AMPLIFIER INPUT (SPD)
Bias Current
Offset Voltage

-

Input Range (Linear)

0

Input Impedance

1

-

-

35

-

System Bandwidtlh

(Note 1)

Current Limit

Rsense

=0.200

1

V
MO
kHz

5

-

155

-

·C

-

40

-

·C

-

-

2.2

V

0.44

V

-

1

mA

-

VlvS

A

THERMAL LIMIT
Threshold
Hysteresis
OUTPUT DRIVERS

=3A, VPMOS + VNMOS

On Saturation (See Note 5)

lOUT

On Saturation (See Note 5)

lOUT = 0.6A, VpMOS + VNMOS

Off Leakage

PV+ > VOUT > PGND or ISEN

Slew Rate

(See Note 2)

6-12

-

0.5

HIP4011
Electrical Specifications TA = +2SoC and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified (Continued)
PARAMETERS

TEST CONDITION

MIN

TYP

MAX

UNITS

-

1.5

V

-

3.3

V

60

%

0.4

V

5

IIA

FREEWHEEL DIODES
Forward Drop

lOUT = 1A

INTERNAL BRAKE DRIVER
Undervottage Trip Point, PV+

(See Note 3)

2.7

Hysteresis

(See Note 4)

40

On Saturation

Each NMOS, lOUT = 3A

BRAKE CAPACITOR (BCAP)
Discharge Leakage

SV+ = PV+ = 3V to 12V, BCAP = 10V

-

-

NOTES:
1. The system bandwidth Is fixed by an internal RC network around the amplifier.
2. Internal limiting of turn on and turn off drive is used to limit output dv/dt.
3. The braking action starts at the given trip point with a falling supply voltage.
4; Hysteresis causes the brake to be removed at a higher trip point with a rising supply voltage.
5. This value Includes the combined voltage drops of one upper plus one lower switch at the indicated current.

Functional Block Diagram
~GNALo-____~~~-_-_-_-_--_-_-_-~--~-_-_-_--_-_-_-_--_-_-_-_--_-_-~-~----.------.-~-~----~-----------------------_--_-_-_-_--_-_-~.B-C~A~P--,

V+

13

:10

··

BRAKE

~CAP.

:4PV+

w

8
a:
III

DECODE
LOGIC

..J
..J

:::>

WITH

u.

ILLEGAL
CODE
REJECTION

FORCEo-____+-~_i
BRAKE

SUBSTRATE
GND

SIGNAL
GND

THREE PHASE BRUSHLESS CONTROLLER

6-13

HIP40BO
80V/2.SA Peak, High Frequency
Full Bridge FET Driver

April 1994

Features

Description

• Drives N-Channel FET Full Bridge Including High Side
Chop Capability

The HIP4080 is a high frequency, medium voltage Full Bridge
N-Channel FET driver IC, available in 20 lead plastic SOIC
and DIP packages. The HIP4080 includes an input comparator, used to facilttate the "hysteresis" and PWM modes of
operation. Its HEN (high enable) lead can force current to
freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since n can swnch at
frequencies up to 1MHz, the HIP4080 is well suited for driving
Voice Coil Motors, switching amplifiers in class D high-frequency switching audio amplifiers and power supplies.

• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz In Free Air at +50 oC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies

HIP4080 can also drive medium voltage brush motors, and
two HIP4080s can be used to drive high performance step• Input Logic Thresholds Compatible with 5V to 15V per motors, since the short minimum 'on-time" can provide
fine micro-stepping capability.
Logic Levels
• DIS (Disable) Pin Pulls Gates Low

Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.

• Very Low Power Consumption

Applications
• MedlumlLarge Voice Coil Motors

The similar HIP4081 IC allows independent control of all 4
FETs in an Full Bridge configuration.

• Full Bridge Power Supplies
• Class 0 Audio Power Amplifiers

Ordering Information

• High Performance Motor Controls

PART
NUMBER

• Noise Cancellation Systems

TEMPERATURE
RANGE

• Battery Powered Vehicles

HIP4080IP

-4O"e to +85°e

• Peripherals

HI P40801B

-40"e

to +85°e

PACKAGE
20 Lead Plastic DIP
20 Lead Plastic sOle (W)

• U.P.S.

Pinout

Application Block Diagram
BOV

HIP4080 (PDIP, SOIC)
TOP VIEW

1

L

BHS

HEN

BlO

DIS
HIP4080

LOEL~

~AHS

AHB 10

11 AHO

IN+

ALO

tiN-

AHS
AHO

I
T

GND

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6-14

File Number

3178.6

HIP4080
Functional Block Diagram

(1/2 HIP40BO)
HIGH VOLTAGE BUS :s; 80VDC

AHB

~------~-----+--~
AHO

CBS

AHS

TO VOO (PIN 16)

Des

..:.

+12VDC
BIAS
SUPPLY

CBF

Vss

ill

Typical Application (Hysteresis Mode Switching)

L

UJ

g
a:
CD
oJ
oJ
:::I

II.

6V--~r-~------~r-~

GND

GND

6-15

Specifications HIP40BO
Absolute Maximum Ratings

Thermal Information

Supply Voltage, Voo and Vcc .•.••.••...•••...••• -o.3V to 16V
Logic VO Voltages .••••.•.•••••••.••••••. -0.3V to Voo + IN-, 10H = -300~A

Voo
-0.4

Voo
-0.5

-

V

INPUT PINS: DIS
Low Level Input Voltage
High Level Input Voltage

Input Voili:tge Hysteresis
Low Level Input Current

IlL

High Level Input Current

IIH

VIN = OV, Full Operating Conditions
VIN = 5V, Full Operating Conditions

6-16

-

35

-

-130

-100

-75

-135

-65

-1

-

+1

-10

+10

2.7

-

-

-

V
mV

IIA
IIA

Specifications HIP40BO
Electrical Specifications

VDD = vee = VAHS = VSHS = 12V, vss = VAtS = VSLS = VAHS = VSHS = OV, RHDEL = RLOEL = lOOK, and
TA = +25°C, Unless Otherwise Specified (Continued)

PARAMETERS

TEST CONDITIONS

SYMBOL

TJ =-4DOC
TO+125°C

TJ =+25°C
MIN TYP MAX

MIN

-

2.7

MAX UNITS

INPUT PINS: HEN
Low Level Input Voltage

VIL

Full Operating Conditions

High Level Input Voltage

VIH

Full Operating Conditions

2.5

Input Voltage Hysteresis

-

1.0

-

-

35

0.8

V

-

-

mV

V

Low Level Input Current

IlL

VIN = DV, Full Operating Conditions

-260

-200

-150

-270

-130

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-1

-

+1

-10

+10

I!A
I!A

4.9

5.1

5.3

4.8

5.4

V

TURN-ON DELAY PINS: LDEL AND HDEL

I

LDEL, HDEL Voltage
IHDEL = ILDEL = -l00I1A
VHDEL,v
GATE DRIVER OUTPUT PINS: AlO, BlO, AHO, AND BHO

I

low level Output Voltage

VOL

lOUT = 100mA

.70

0.85

1.0

0.5

1.1

V

High level Output Voltage

Vee - VOH

lOUT = -100mA

0.8

0.95

1.1

0.5

1.2

V

Peak Pull-Up Current

10+

VOUT= OV

1.7

2.6

3.8

1.4

4.1

A

Peak Pull-down Current

10-

VOUT = 12V

1.7

2.4

3.3

1.3

3.6

A

Switching Specifications

VDD = vee = v AHS = VSHS = 12V, vss = VAtS = VSLS = v AHS = VSHS = OV, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25°C, Unless Otherwise Specified
TJ =-4DOC
TO+125°C

TJ = +25OC
PARAMETERS

SYMBOL

TEST CONDITIONS

TLPHL

Upper Turn-off Propagation Delay (IN+lIN- to AHOIBHO)

T HPHL

Lower Turn-on Propagation Delay (IN+lIN- to AlOIBLO)

TLPLH

RHDEL = RLOEL = 10K

Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO)

THPLH

RHDEL = RLDEL = 10K

Rise Time

TR

Fall Time

TF

MIN

-

lower Turn-off Propagation Delay (IN+ilN- to ALOIBlO)

-

Turn-on Input Pulse Width

TPWlN.QN

RHDEL = RLOEL = 10K

50

Turn-off Input Pulse Width

TPWIN.QFF

RHDEL = RLOEL = 1OK

40

TYP MAX
40

70

SO

80

45

70

70

110

10

25

10

25

-

-

-

MIN MAX UNITS

-

50
40

90

ns

110

ns

90

ns

140

ns

35

ns

35

ns

-

ns

-

ns

95

ns

105

ns

90

ns

Disable Turn-off Propagation Delay
(DIS - lower Outputs)

TDISLOW

-

45

75

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

TDiSHIGH

-

55

85

Disable to lower Turn-on Propagation Delay
(DIS - ALO and BlO)

TDLPLH

-

35

70

Refresh Pulse Width (AlO and BlO)

TREF-PW

160

260

380

140

420

ns

-

335

SOO

-

550

ns

35

70

90

60

90

ns
ns

Disable to Upper Enable (DIS - AHO and BHO)

TUEN

HEN-AHO, BHO Turn-off, Propagation Delay
HEN-AHO, BHO Turn-on, Propagation Delay

THEN-PHL

RHDEL = RLOEL = 10K

THEN-PLH

RHDEL = RLDEL = 10K

-

-

TRUTH TABLE
IN+ > INX
1

0
1
0

INPUT
HEN
X
1
1

0
0

OUTPUT
DIS

ALO

AHO

BLO

BHO

1
0

0
1

0
1

0
0

0
0

0
0
1
0

0

1

1

0

0

1

0
0
0

0

0

6-17

110

HIP4080
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301tA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

HEN

High-side Enable input. logic level Input that when low overrides IN+lIN- (Pins 6 and 7) to put AHa and BHO
drivers (Pins 11 and 20) in low output state. When HEN is high AHa and BHO are controlled by IN+IIN- inputs.
The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001JA, pull-up to Voo will
hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+lINInputs.

3

DIS

DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other Inputs.
When DIS is taken low the outputs are controlled by the other Inputs. The pin can be driven by signal levels of
OV to 15V (no greater than Voo). An Internall001tA pull-up to Voo will hold DIS high if this pin is not driven.

4

Vss

Chip negative supply, generally will be ground.

5

OUT

OUTput of the input control comparator. This output can be used for feedback and hysteresis.

6

IN+

Non-Inverting input of control comparator. 11 IN+ is greater than IN- (Pin 7) then Ala and BHO are low level
outputs and BlO and AHa are high level outputs. 11 IN+ Is less than IN- then Ala and BHO are high level outputs and BlO and AHa are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs.
HEN (Pin 2) low level will override IN+IIN- control of AHa and BHO. When switching In four quadrant mode,
dead time in a half bridge leg is controlled by HDEl and lDEl (Pins 8 and 9).

7

IN-

Inverting input of control comparator. See IN+ (Pin 6) description.

8

HDEl

High-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage Is approximately 5.1 V.

9

lDEl

low-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. lDEL reference voltage is approximately 5.1 V.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacnor to this pin. Internal charge pump supplies 301JA, out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHa

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

13

Ala

A low-side Output. Connect to gate of A low-side power MOSFET.

14

AlS

A low-side Source connection. Connect to source of A low-side power MOSFET.

15

Vcc

Positive supply to gate drivers. Must be same potential as Voo (Pin 16). Connect to anodes of two bootstrap
diodes.

16

Voo

Positive supply to lower gate drivers. Must be same potential as Vce (Pin 15). De-couple this pin 10 Vss (Pin 4).

17

BlS

B low-side Source connection. Connect to source of B low-side power MOSFET.

18

BlO

B low-side Output. Connecl to gate of B low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

-,.tlHV

-

.. .... ,.. ..
I tI_....
Hlgn-sloe VUlpUl.
vonneCllO gale Of tI Hlgn-sloe power MU"r-c: I.
a • . - .... _ _ _

~

6-18

HIP40BO
Timing Diagrams
ms=o----~_+_+~~---------------------­

HEN=l ----~_+_+---------------------------------IN+ > IN- - - - - ' \ J
ALO ______++.11
AHO
aLO
aHO ______~-+-'I
hPHL

TR

TF

(10%-iO%) (90%-10%)

FIGURE 1. BISTATE MODE

015=0

HEN

....

----.

--

....

-\.

/

\.

/

\.

\.

IN+> INALO

UI

/

g
a:ED

\

AHO

,~----------------1

aLO

aHO ____________________________________- J

',-_...,r

FIGURE 2. HIGH SIDE CHOP MODE

TOLPLH

DIS

~

--

TOIS

I-- TREF.PW

I

\.

HEN=l

\.

IN+ > IN-

/

ALO
AHO

I

alO

'\
/

BHO
~TUENFIGURE 3. DISABLE FUNCTION

6-19

..J
..J
:::I
\L.

HIP40BO

Typical Performance Curves

Voo =Vee
RHOEL

=VAHB =VSHS =12V. VSS =VALS =VSLS =VAHS =VSHS =OV.
=RLOEL= 100K. and TA =+25°C. Unless Otherwise Specified
13

14.0

i
!Z

l:!
a:
B
~

~

::)

1l

100 200 300

+750 C,::>

4.0

SWITCHING FREQUENCY (kHz)

~

800

FIGURE 5. loco. NO-LOAD 100 SUPPLY CURRENT vs FRE·
QUENCY (kHz)

",

a.

!Zw
Il!
B

(J

:::>
Q.

...w
...w>
~
1!E

·110

l.. ·190
zw

" "'- -

a:
a:

......

8 ·200
~

"r-....
~

...w

1!E .210

~ ·220

-SO

·25

0

25

50

75

100

·230
-40

125

·20

o

FIGURE 10. DIS LOW LEVEL INPUT CURRENT IlL V8 TEMPERA·
TURE

~

~

100

120

80

15.0

'~"'

~ 14.0

~
13.0

is

c

~

FIGURE 11. HEN LOW LEVEL INPUT CURRENT IlL VII TEMPER·
ATURE

w

li
!i
~

20

JUNCTION TEMPERATURE ("C)

JUNCTION TEMPERATURE (OC)

~

.... r-. ...

...
·120

~

......

>
~

--

12.0

.. 70

S.

-r-.

~w
C

11.0

60

z

--...

-r-._

0

!i

50

...a:

40

~
0

--- -

I- .....

~

..... ~
~

C§

~

30

10.0
-40

·20

020406080

100

120

-40

·20

JUNCTION TEMPERATURE ("C)

80

.. 380

.. 70

360

z

0

340

...

320

r-.

i!:0
a:

60

80

100

120

S.

S.

!iCI

40

FIGURE 13. UPPER DISABLE TURN·OFF PROPAGATION
DELAY T OISHIGH vs TEMPERATURE

400

~w

20

JUNCTION TEMPERATURE ("C)

FIGURE 12. AHB· AHS. BHB • BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE

C

0

300
-40

-

~

..... ..... i"""

w 60
C

~

z

-

0

!i
~0

...a:

50

40

..... ..... .....

30
·20

020406080

100

-40

120

JUNCTION TEMPERATURE (OC)

·20

020406080

100

120

JUNCTION TEMPERATURE (OC)

FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION
DELAY vs TEMPERATURE

6·21

FIGURE 15. LOWER DISABLE TURN·OFF PROPAGATION
DELAY TOISLOW vs TEMPERATURE

HIP40BO
Typical Performance Curves

V DD =Vee

=VAHB =VBHB =12V, Vss =V/>J..S =VBLS =VAHS =VBHS =OV, RHDEL =RLDEL =

10K, TA =+25°C and RHDEL =RLDEL =10K, Unless Otherwise Specified
375

I

~

i
w

80

!

325

!l
:::>

275 1'-00

;

225

...

i"""

~

-

~
~

~
Ii!...

.s.
~
l!l
z

0
20
40
60
80
100
JUNCTION TEMPERATURE (OC)

...~

!

~
w

Q

--

- -

_r-

-40

-20

~

70.0

-

0

... ~ r-

~

60.0

...a:

50.0

~
0

20

40

60

80

100

0
20
40
60
80
100
JUNCTION TEMPERATURE ("C)

-

-40

120

..... ~

.,. ~ .,. ....

.... r-

f- ~

-20

0

20

40

60

80

100

FIGURE 19. UPPER TURN-ON PROPAGATION DELAYTHPLH
vsTEMPERATURE

..

80.0

Q

70.0

.s.
~w

90.0

z

~

0

Ii
~
0

60.0

...~ 50.0
~

-40

-20

o

~

f-

-

-~

~~

20
40
60
80
100
JUNCTION TEMPERATURE ("C)

120

JUNCTION TEMPERATURE ("C)

90.0

40.0

120

40.0

.s. 80.0
~
l!l 70.0

Ii
~

80.0

Z

FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE

..

o

FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE

70.0

40.0

-20

JUNCTION TEMPERATURE (OC)

80.0

50.0

30

90.0

60.0

-

40

-40

120

90.0

o

Ii
~

~

50

20
-20

FIGURE 16. TREF.PW REFRESH PULSE WIDTH vs TEMPERATURE

.

60

~

a:
175
-40

70

-

...a:

50.0

-~ ~

40.0
-40

120

FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE

60.0

-20

0

20

40

-

-r-

60

80

~

100

-

~

120

JUNCTION TEMPERATURE ("C)

FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH
vs TEMPERATURE

6-22

HIP4080

Typical Performance Curves

Voo = Vee = VAHB = VBHB =12V. Vss =VALS = VBLS

=VAHS = VBHS = OV. RHOEL = RLOEL =

lOOK and TA =+25°C. Unless Otherwise Specified
13.5

r-r-r-r-T""T"".,.-.,.-..,.....,.....,......,......,...-...-...-...-r-.

13.5

r-r-r-.-.-,..-,..-..,,-,-,...,...,...-r-r.,..,....,

!1~5t:t:t:t:t:+=l=~~~~~:r:f:f:t=+~

! 12.5 I-f-f-f-+-+-+-++++++-I--I--I--I--I
w

:::E

w

~ 11.5 I-t-t-+-+-+-+-+++++-I--I--I--I--I--I

~ 11.51-f-+-+-+-+-+-++++++-I--I--+-+-I

oJ

~

~

W

q10.5 1-t-t-+-+-+-+-+-+++++-t-t-t-t-1

~ 10.5 I-f-f-+-+-+-++++++++-I--I--I--I

C

z

a:

w

~ BtE~±fffHH!tm

~

8.5

HH-+-+-+++-+-+-HH-+-+-+-t-i

9.5

8.5

-40

-20

o

~

~

~

~

100

8.5 '--L-'--L-L-L...-JL...-JL...-JL...-J'--'--'--'--''--'--''--'--'
-40
-20
0
20
40
60
80
100 120

1~

JUNCTION TEMPERATURE (OC)

JUNCTION TEMPERATURE (C)

FIGURE 22. GATE DRIVE FALL TIME T F vs TEMPERATURE
6.0

FIGURE 23. GATE DRIVE RISE TIME TR VB TEMPERATURE

r-r-r-T""T""-r--.--.--.-..,......,......,......,......,......,...-...-r....,

1500

~

~

~ 5.5

;!;

;; 1250

w

'-'

!;
g
...
iiE

5.0

"'-

CI

g1000 ""'"

t:t~;t;t~~~~~~~~t:t:t:t:t=J

""'"

w

~ 750
Ii,I
z
r-o

oJ

9 4.5 1-+-+-+-+-+-+-+--+--+-++-+--+--+--1--1-...,

... 500 r--

:r:

a: 250 r--

~

J

~

r--

~
4.0 L-L-L-L.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....JL.....J--1--1.....J
-40
-20
020406080
100 120

r-o

+750 C - V
+12SOC

./

-

10

12

14

BIAS SUPPLY VOLTAGE M

FIGURE 24. VLDEL• VHDEL VOLTAGE vs TEMPERATURE

FIGURE25. HIGH LEVEL OUTPUT VOLTAGE. Vee - VOHvs BIAS
SUPPLY AND TEMPERATURE AT 100mA

1500

3.5

:;-

g

E
;; 1250

3.0

z~
w

~

g1000

a: 2.5
a:
:::>
(.)
2.0

w

~

750

...

SOO I-

~

I- +2SOC
250 I- +750 C-

It
Z

I- -40o C

o

/" V V
OOcL L L V
+250 C ./ /' /'

8

6

JUNCTION TEMPERATURE (OC)

~
~

./

-40o c /

OOC

./

./

./

/'
/"

./

iii
w 1.5
;;:
a:
C 1.0
w

/'

Ii:CI

,.... +1250 C-'
6

~

""

V"

..... ~

......

~

~

0.5
0.0

10

12

6

14

BIAS SUPPLY VOLTAGE (V)

FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL VB BIAS SUPPLY AND TEMPERATURE AT 100mA

7

8
10 11 12 13
Voo. Vee. VAHB. VBHB (V)

14

15

16

FIGURE 27. PEAK PULLDOWN CURRENT 10 VB BIAS SUPPLY
VOLTAGE

6-23

HIP4080

Typical Performance Curves

Voo = Vee = VAHB = VBHB = 12V, Vss = VI>J..S = VBLS = VAHS = VBHS = OV, RHoEL = RLoEL =
100K and TA = +25°C, Unless Otherwise Specified (Continued)

3.5

.,.,

~ 3.0

ffi
a:

2.5

i3

2.0

.., V

a:

~

iii 1.5

~

2i
w

!c
"

V

/"

500

~

i

I-

z
w
a:
a:

:::I
(J

.,., / " ~

Ul

~

0.5
0.0
7

8

8

3,000"

20 10 5

1,000 '\

~

'~"'
~
6

50 -

w

1.0

10

11

12

13

14

15

2
0.5
0.2
0.1

16

V

~

V V
. / V I~ V

I-

Ii:

~
w

>
w

100
~

50

5

..J

~

~

V

...... V

~

5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)

500 1000

FIGURE 29. LOW VOLTAGE BIAS CURRENT 100 AND Icc
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE

,..,..

120

V

~~

20
10

V

V V

,...-: "". / .., 10'
2

V

1200

i3

V
V

/' V

,/

500

a:
a:

V

.'\.

V

V

150

1000

zw

V

"- V
100" '\. l7 V
K: ~ /"

VO[)o Vee, VAHB. VBHB (V)

FIGURE 28. PEAK PULLUP CURRENT 10. vs SUPPLY VOLTAGE

V

200
100 -10,000,\

.-::::::::c ~ r<-~ ?<

-

r--- :-- 80V
60V

------ ---- t--. r--

1/

2

40V

./

30

~20V

2

5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)

o

500 1000

V

10

V

..V

v

V
50

100
150
200
HDELILDEL RESISTANCE (len)

250

FIGURE 31. MINIMUM DEAD-TIME VB DEL RESISTANCE

FIGURE 30. HIGH VOLTAGE LEVEL·SHIFT CURRENT VB
FREQUENCY AND BUS VOLTAGE

6·24

HIP4080
HIP4080 Power-up Application Information
The HIP4080 H-Bridge Driver Ie requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-Bridge power MOSFETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4080 does not have an input protocol like the
HIP4081 that keeps both lower power MOSFETs off other
than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of
the lower power devices is on at a time, assuming DIS is low.

However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL,
while the chip is enabled, as shown in Figure 32. Pulling
LDEL to VDO will indefinitely delay the lower turn-on delays
through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled,
i.e. DIS = low, IN+ or IN- can be switched through a full
cycle, properly setting the upper driver outputs. Once this is
accomplished, LDEL is released to its normal operating
point. It is critical that IN+!lN- switch a full cycle while LDEL
is held high, to avoid Shoot-through. This start-up procedure
can be initiated by the supply voltage andlor the chip enable
command by the circuit in Figure 32.

g
FIGURE 32.

a:

m
..J
..J

;:)

u..

Voo

12V, FINAL VALUE
'8.3V TO 9.1 V (ASSUMING 5% ZENER TOLERANCE)

~-------5.1V

TIMING DIAGRAM FOR FIGURE 32

NOTE:
1. Between 11 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If
the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 1Oms time delay during which the IN+
and IN- pins must cycle at least once.
2. Another product, HIP4080A, incorporates undervoHage circuitry Which eliminates the need for the above power up circuitry.

6-25

l±;T

IN2 IN1

+12V

'":o.- ""-

1

U2

2

7-Ir·" ""'. ''''''~ ""
iii

L------' -

MPR1
... OUTIBU

-

...-_+--f___--:21HENlBHI

r~MPR2
W U2 12 .•• IN+lAU

L-------:
J~!'fl3HENlBHI

Q2

Vee 15
ALS 14

F
1

CWI'

ft

AHS 12
11
ALO

f~

L2
0000

=

3

0

B+

"'J

~ 0000 I
C1

2
R23

ALO 13
R34

=-

BHS 19

3 DIS
BLO>r<--18--t+-t--1
4 Vss
BLS 17
OUTIBU Veo 16
IN+lAU
7:"1 IN., IN-, 10H = -250~A

Voo
-0.4

-

Voo
- 0.5

V

INPUT PINS: DIS
Low Level Input Vottage
High Level Input Voltage
Input Voltage Hysteresis

Lew

La¥a~

6-30

-

0.8

V

2.7

-

V

35

-

-100

-75

-135

-65

-

+1

-10

+10

mV

IJA
IJA

Specifications HIP40BOA
Electrical Specifications

VDD =vee =VAHB =VBHB =12V, Vss =VALS =VBLS =VAHS =VBHS =OV, RHDEL =RLDEL =100K, and
TA =+25°C, Unless Otherwise Specified (Continued)
TJ =-400C
TO+125°C

TJ =+25°C
PARAMETERS

SYMBOL

TEST CONDITIONS

I TYP

MIN

MAX

MIN

MAX UNITS

INPUT PINS: HEN
Low Level Input Vottage

VIL
VIH

Full Operating Conditions

-

Full Operating Conditions

2.5

-

-

0.8

V

-

-

mV

-150

-270

-130

+1

-10

+10

IlA
IlA

4.8

5.4

V

1.0

0.5

1.1

V

1.1

0.5

1.2

V
A

1.0

2.7

35

-

-260

-200

-1

-

LDEL, HDEL Voltage
VHDEl,V
IHDEL =ILDEL =-loollA
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

4.9

5.1

5.3

Low Level Output Voltage

VOL

IOUT-l00mA

0.7

0.85

High Level Output Voltage

Vee - VOH

lOUT - -100mA

0.8

0.95

High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current

IlL

VIN

High Level Input Current

IIH

VIN

=OV, Full Operating Conditions
=5V, Full Operating Conditions

V

TURN-ON DELAY PINS: LDEL AND HDEL

I

Peak Pullup Current

10+

VOUT-OV

1.7

2.6

3.8

1.4

4.1

Peak Pulldown Current

10 -

VOUT = 12V

1.7

2.4

3.3

1.3

3.6

A

8.1

8.8

9.4

8.0

9.5

V

Under Voltage, Rising Threshold

UV+

Under Voltage, Falling Threshold

UV-

7.6

8.3

8.9

7.5

9.0

V

Under Voltage, Hysteresis

HYS

0.25

0.4

0.65

0.2

0.7

V

Switching Specifications

VDD =vee =VAHB =VBHB =12V, vss =vAlS =VBLS =VAHS =VSHS =OV, RHDEL =RLDEL =10K,
CL =1000pF, and TA =+25°C, Unless Otherwise Specified

PARAMETERS

SYMBOL

Lower Turn-off Propagation Delay (IN+lIN- to ALOIBLO
Upper Turn-off Propagation Delay (IN+lIN- to AHO/BHO)
Lower Turn-on Propagation Delay (IN+lIN- to ALO/BLO)
Upper Turn-on Propagation Delay (IN+lIN- to AHO/BHO)

TJ =-400C
TJ = +25°C
TO+125°C
MIN TYP MAX MIN MAX UNITS

TEST CONDITIONS

-

TLPHL
THPHL
TLPLH
THPLH

-

Rise Time

TR

Fall Time

TF

-

Turn-on Input Pulse Width

TpWIN.QN

50

Turn-off Input Pulse Width

40

70

50

80

40

70

70

110

10

25

10

25

-

-

-

50

ns
ns

90

ns

140

ns

35

ns

35

ns

-

ns
ns

TpWIN.QFF

40

Disable Turn-off Propagation Delay
(DIS - Lower Outputs)

TDISLOW

-

45

75

-

95

ns

Disable Turn-off Propagallon Delay
(DIS - Upper Outputs)

TDISHIGH

-

55

85

-

105

ns

Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)

TDLPLH

-

45

70

-

90

ns

Refresh Pulse Width (ALO and BLO)

TREF·PW

240

380

500

200

600

ns

-

480

630

-

750

ns

40

70

60

90

Disable to Upper Enable (DIS - AHO and BHO)

TUEN

HEN-AHO, BHO Turn-off, Propagation Delay

THEN·PHL

RHDEL - RLDEL =10K

HEN-AHO, BHO Turn-on, Propagation Delay

THEN·PLH

RHDEL =RLDEL =10K

40

90

110

-

90

ns

110

ns

TRUTH TABLE
INPUT

OUTPUT

IN+> IN-

HEN

UN

X

X

i<.

0
1
0
1

0
1
1
0

0
0
0

0

DIS
1
0
0
0
0

X

X

1

X

6-31

AlO

AHO

BlO

BHO

u

u

u

u

1
0
1
0
0

0
1
0
0
0

0
1
0
1

0
0
1
0
0

0

HIP40BOA
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3011A out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

HEN

High-side Enable input. logic level Input that when low overrides IN+IlN- (Pins 6 and 7) to put AHO and BHO
drivers (Pins 11 and 20) In low output state. When HEN Is high AHO and BHO are controlled by IN+IlN- inputs.
The pin can be driven by signal levels of OV to 15V (no greater than Voo ). An Internall0011A pull-up to Voo will
hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+IINinputs.

3

DIS

DISable Input. logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signalleveis of
OV to 15V (no greater than Voo ). An internal100llA pull-up to Voo will hold DIS high If this pin Is not driven.

4

Vss

Chip negative supply, generally will be ground.

5

OUT

OUTput of the input control comparator. This output can be used for feedback and hysteresis.

6

IN+

Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then AlO and BHO are low level outputs and BlO and AHO are high level outputs. If IN+ is less than IN- then AlO and BHO are high level outputs
and BlO and AHO are low level outputs. DIS (Pin 3) high level will override IN+IlN- control for all outputs. HEN
(Pin 2) low level will override IN+IlN- control of AHO and BHO. When switching in four quadrant mode, dead
time in a half bridge leg is controlled by HDEl and lDEl (Pins 8 and 9).

7

IN-

Inverting input of control comparator. See IN+ (Pin 6) description.

8

HDEl

High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage is approximately 5.1 V.

9

lDEl

low-side turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no Shoot-through by delaying the turn-on of the low-side drivers. lDEl reference voltage is approximately 5.W.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3011A out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

13

AlO

A low-side Output. Connect to gate of A low-side power MOSFET.

14

AlS

A low-side Source connection. Connect to source of A low-side power MOSFET.

15

Vcc

Positive supply to gate drivers. Must be same potential as Voo (Pin 16). Connect to anodes of two bootstrap
diodes.

16

Voo

Positive supply to lower gate drivers. Must be same potential as Vec (Pin 15). De-couple this pin to Vss (Pin 4).

17

BlS

B low-side Source connection. Connect to source of B low-side power MOSFET.

18

BlO

B low-side Output. Connect to gate of B Low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

20

SHO

6 High-side Output. Connect to gate of B High-side power MOSFET.

6-32

HIP40BOA
Timing Diagrams
UN.~S O---------+-+~----------------------------------------------...
HEN 1---------+-+~----------------------------------------------...

IN+> INAlO ________++.11
AHO
BlO

-+-+-'1

BHO ________
TLPHL

TR
TF
(10% - 90%) (90% -10%)
FIGURE 1. BISTATE MODE

- - --

THEN-PHL

UN.~S

0

HEN

-~

'\.

/

IN+> IN-

/

'\.

'\.

'\.

w

/

AlO

g

a:m

'\.

AHO

\~--------------------------BHO __________________________________________-',
BlO

FIGURE 2. HIGH SIDE CHOP MODE

TDLPLH
UNor~S

~

~

.... TREF-PW

I

'\.

HEN

'\.

IN+ > IN-

/

AlO
AHO

/

BlO

'\.

/

BHO
~TUEN-FIGURE 3. DISABLE FUNCTION

6-33

::I
~

HIP4080A

Typical Performance Curves

=

=

=

=

=

=

Voo Vcc VAHB V BHB l2V. Vss VPLS V BLS
lOOK. and TA +250 C. Unless Otherwise Specified

=

=VAHS =VBHS =OV. RHOEL =RLOEL =

13
14.0

!

...z

12.0

w 10.0

a::
a::

:>

0

...~...
:>

'"
il

8.0

i---'""'"

---

---

12.5

!!E

:.,.....-

~
8
8::
~

6.0

10
12
VOO SUPPLY VOLTAGE (V)

10

14

FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE

~

FIGURE 5. 1000 NO-LOAD 100 SUPPLY CURRENT vs FREQUENCY (kHz)
+l25°C,-

C

V

15.0

./

~

V

10.0

o

:>

w
a:: 3.0
a::

-40oC .....

-~ X

2.0

/"

....-:: ~

---

0.0 ~
o 100

100 200 300 400 500 600 700 800 gOO 1000
SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A. B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)

-

~

. / '"'-...... ~ ~""
,./

V ........:: ~ ~

1.0

.......

/"

"-

+25OC

'"jl

/'

0.0

- ~ -...... . /
aOc ~ ~ / '

...z

......~
:>

/"

5.0

+750 C,::> ~

4.0

.§.

0

. . . . 1-'

~

it

1000

5.0

o
~

I

200
400
600
800
SWITCHING FREQUENCY (kHz)

20.0

w

~

V

/

I-'

/

V

/

10.5

8

!!i

11.0

il
2.0

~
a::

11.5

~

4.0

!

12.0

....

....

./
...",,;

~

200 300 400 500 600 700 800 gOO 1000
SWITCHING FREQUENCY (kHz)

FIGURE 7. Iceo. NO-LOAD Icc SUPPLY CURRENT vs FRE·
QUENCY (kHz) TEMPERATURE

2.5

!

~
w

2

/

a::
a::

8'" 1.5

'"

~

:>

1

'"~

~ 0.5

~
o

/
1\

/

iii

8::

V'

/

1\,
i"-.

/
200

400

600

800

-40

1000

SWITCHING FREQUENCY (kHz)

FIGURE 8. IAHB.IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY

6-34

·20

i' ......

...... ~

r- I-

....

i"'" l-

0
20
40
60
80
100
JUNCTION TEMPERATURE ("C)

I-

120

FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERA·
TUREATV CM =5V

HIP40BOA

Typical Performance Curves

Voo

=Vee =VAHB =VBHB =12V. Vas =VAiS =VBLS =VAHS =VBHS =OV. RHOEL =RLOEL =

lOOK. and TA =+250 C. Unlass Otherwise Specified (Continued)
·180

·110

...z~
w

a: ·100
a:
:>
u

"

.......

~'1110
~

"-

"- .........

...:>

...l!!
....
w

l:!a:
tl

~

~

"' ....... r-r--

l!! .210

Lrl

·110

>

"

·200

~

w
....
~
....

...~ ·220
·230
-40

·120
-SO

·25

0

25

50

75

100

125

·20

o

~

~

~

~

FIGURE 10. DIS LOW LEVEL INPUT CURRENT IlL vs TEMPER·
ATURE

>'

;;; 15.0

~

14.0

~
~

13.0

~
«

r--

G
12.0
CJ

--

.s

i"""

r-.

--

~

~

~ 11.0

c
z
0

....

50

...~

40

~

~

I-

~

i:C

UI

;:)

30

·20

o

~

~

~

~

1~

100

U.
-40

-20

JUNCTION TEMPERATURE fC)

80

100

120

.s

""

5w 60

~

c
z

I;

0

/'
l.,.....--"

.............. ....

~...
...

II:

·25

o

.... .... ....

50

0

425
-SO

60

.. 70

.s 500

~

40

80

..

...~ 450

20

FIGURE 13. UPPER DISABLE TURN·OFF PROPAGATION
DELAY T OISHIGH vs TEMPERATURE

525

~

o

JUNCTION TEMPERATURE fC)

FIGURE 12. AHB· AHS. BHB· BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE

~
~ 475

w

g
..J
..J

10.0-40

5

,
~

----

5w 60
~

z

!

,,

.. 70

....

1~

FIGURE 11. HEN LOW LEVEL INPUT CURRENT IlL vs TEMPER·
ATURE
80

!j

§!

100

JUNCTION TEMPERATURE fC)

JUNCTION TEMPERATURE fC)

40

-I-

.... 1-1"""

.... ~ ....

-

30
25

50

75

100

125 150

-40

JUNCTION TEMPERATURE (OC)
FIGURE14. DISABLE TO UPPER ENABLE TUEN PROPAGATION
DELAYvsTEMPERATURE

·20

0

20

40

60

80

100

120

JUNCTION TEMPERATURE fC)
FIGURE 15. LOWER DISABLE TURN·OFF PROPAGATION
DELAY TDlSLOW vs TEMPERATURE

6·35

HIP40BOA
Typical Performance Curves

..

VDD =Vee =VAHB =VBHB =12V, Vss =VALS =VBLS =VAHS = VBHS =OV, RHDEL =RLDEL =
10K, and TA = +25°C, Unless Otherwise Specified

450

80

.

.s

i

"'" i'.....

w



400


0-

i!!:

w
~ 750

s.o

~
It:

t--- -40oc /
/'/
Lv
t--ooc
SOO
V/
0
t--- +25 C ~ V
~
§ 2S0 I - - +7SOC; / '
t--- +1250 C/
o
10
12

....
w
0
....
.I 4.5
w
0

...

%

-40

·20

0

20

40

60

80

100

120

FIGURE 24. VLOEL• VHOEL VOLTAGE vs TEMPERATURE

FIGURE25. HIGHLEVELOUTPUTVOLTAGE.Vec·VoHvsBIAS
SUPPLY AND TEMPERATURE AT 100llA

1500

3.S

:;;-

.§. 1250

~

~
It:

3.0

ffi

2.5

a:
a:

1000

::>
(J

w

~

~

...

w

~

l<:

750
SOO

q

o

.,
V
~

2.0

~

Z

f-

-400 C

r-

o°e-

z
a: 2S0

i:!

14

BIAS SUPPLY VOLTAGE (V)

JUNCTION TEMPERATURE ("C)

!j

L

+2SoC
- +7SoC
- +12SoC

10

/'

L

~ 1.S

L

>

/ / /'/
/'/' /'
/'/
/'

2iw

1.0

~

O.S

0.0
12

14

BIAS SUPPLY VOLTAGE (V)

FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100llA

V

6

7

8

~

k-"

~

""'"

II

10

11

12

13

14

15

16

Vcc. Veo. VAHG. VBHBM

FIGURE 27. PEAK PULLDOWN CURRENT I().. BIAS SUPPLY
VOLTAGE

6·37

HIP40BOA

Typical Performance Curves

Voo

=Vee =VAHB =VBHB =12V, Vss =V/>J..s =V BLS =VAHS =VBHS =OV, RHOEL =RLOEL =

lOOK, and TA = +25°C, Unless Otherwise Specified (Continued)
3.5

./

~ 3.0

...z

w 2.5

II:
II:
::0
U
~

.,- V . .

2.0

z

iii

w 1.5

V

>

a:c

w
!i(

..",-

500

..",-

1
...

~

100

50 t- 3,000

II:
II:
::0

20 t- 1,000

U

5

~

2

~

CI 0.5

g

1

~

0.5

0.1
6

7

8

II

10

11

12

13

14

15

./

V

w 200

i3
Ii:

%

~

w
>
w
....

100
50

20
10

V
10

V
20

V

""

""'-

~

L

V

V

",

2

5

10

20

50

100 200

500 1000

FIGURE 29. LOW VOLTAGE BIAS CURRENT 100 AND lee (LESS
QUIESCENT COMPONENT) va FREQUENCY AND
GATE LOAD CAPACITANCE

./

V

V

~

SWITCHING FREQUENCY (kHz)

1000

II:
II:

~

,/.
"" V "" i'

16

FIGURE 28. PEAK PULLUP CURRENT 10. va SUPPLY VOLTAGE

500

V ~~

/' V

Vee. Voo, VABH, VBHB (V)

i
...z

,"''\-

~

0.2

0.0

L
V ./

V V'" V"
100\ 1,\ ...,rV
. / V"
~~
~ ;~ V

10 t-

~w

1.0

t-l~,OOO

z

w

/ i---""

",

200

.,§

I

-

~

UV+

:::::"""

I""'"

8.8

ui

~

"'I'

!:j

g

8.6

~

-

t

::0

en 8.4

~

50
100
200
500
SWITCHING FREQUENCY (kHz)

uv-

r-- f"-.

8.2

1000

50

25

o

25

50

n

~I'

100

125

150

TEMPERATURE <"C)

FIGURE 30. HIGH VOLTAGE LEVEL·SHIFT CURRENT va
FREQUENCY AND BUS VOLTAGE

FIGURE 31. UNDERVOLTAGE LOCKOUT va TEMPERATURE

150

120

..
.s.

90

~

~
~

L

60

/'

lL

V

30

V

a

V,

10

50

./

I

I

I

100
150
200
HDEULDEL RESISTANCE (1Ul)

I

250

FIGURE 32. MINIMUM DEAD-TIME va DEL RESISTANCE

6·38

IN2 IN1

POWER SECnON

+12V

CONTROL lOGIC
SECTION

F
R29

~

I

~!
OUTIBU

~

-

L"":,""A,,1 .
6 IN+lAU

7 IN-IAHI
8 HDEl

• HENlBHI

r---1
J~~I'R4

•

.~ I~
3

IN-IAHI

,.1!!

3

2

CW

CD4069UB

BHO 20

~2

1

CW

1

~

LDEL
AHB

~~

2
1

T

~t-

"1

B+

~I-o

3
II

11r---i"

J~~:'R3

1

A

1 BHB

I

CD4069UB

R21

C~

2 HENlBHI BHS 19 . 1
BlO 18
3 DIS
VSS
BlS 17
OUTIBU Veo 16 +12V

J~~'!'2IN+lAU

~

DRIVER SECOON

+

~

,

JM~

~

-

flL

Vee
ALS
AlO 13
AHS 12
AH 11

1

~I-

l

'1-0

fli- t--

~

OOOOC11

2
~3

3
R24

1

~

Q4

OO~O 1-0

AO
BO

:h

cs-!-

I
(
ALS

lCY

CX

~

2

t1.,...

R30

R31

T
~~

,...
-=E"

BLS
NOTE:
DEVICE CD4069UB PIN 7 = COM. PIN 14 =+12V.

FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC

FULL BRIDGE

-

~
~

-!-C2

3

C3

~

COM

(;t

q>
.".
0

••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••

*

...... •••••• 1] ••••••
..•• •••• •••

GND

+12V

@

@

@

@

~
~
~
~

4••
~
~

•• ••
•• ••
•• ••
•• ••
•• ••
•• ••
••
•• ••
•• ••
•• •• ••

••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••

D
..

~

4• •
4• •
4• •
4• •
4••

••
••
••
••
•
••

.. 1]

4• •
4• •
4• •
~

4• •
4••
~

•
••

••
••
••
••
•

••
••
••
••
~
••
••
••
•

~
•

n0

DIS

••

•• •

••

° [][]

:: ",8
••
••

~:

iil

•

J...@

@

ALS
ALO

@u@

R34

••

@

Q

R

Q1

Q3

~

~

~
•

.0.

Q2

c.:-=- ·

: ""

•

R33

'"

R21

• • BLS@
••

-

R22
BHO.~.
R24
BLO.~

• .JMPR1.
• • JMPR2e
• .JMPR_ •
• .JMPR4

•
• • '0 @ .
• • IN2 @ .

$

COM

C8

•••
U2

@~

B+

.::3

CR2

DO [;]QDDO:H~

•• d I @.
••

••

!E~~~
=i • • • ~+

13+

@~

$

$

@
o~ ~D ~
~
a:

@

FIGURE 34. HIP4080A EVALUATION BOARD SILKSCREEN

04

~

@
@
r--l r--l

0

@

"U'U08l
@

@

@

D·
@

m

*

~

~
0
Co

g

HIP4081
80V/2.5A Peak, High Frequency
Full Bridge FET Driver

April 1994

Features

Description

• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations

The HIP4081 is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastiC
SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a
shoot·through condition. The HIP4081 can switch at frequencies up to 1MHz and is well suited to driving Voice Coil
Motors, high-frequency Class D audio amplifiers, and power
supplies.

• Bootstrap Supply Max Voltage to 9SVDC
• Drives 1000pF Load at 1MHz in Free Air at +SOoC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with SV to 1SV
Logic Levels
• Very Low Power Consumption

Applications
• Medium/large Voice Coil Motors
• Full Bridge Power Supplies
• Class D Audio Power Amplifiers

For example, the HIP4081 can drive medium voltage brush
motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum "on·time"
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead·times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.

A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle
wave and to facilitate "hysteresis mode" switching.

Ordering Information

• High Performance Motor Controls

PART
NUMBER

• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals

TEMPERATURE
RANGE

PACKAGE

HIP40811P

-40oe to +85°e

20 Lead Plastic DIP

HIP40811B

-40oe to +85°e

20 Lead Plastic sOle (W)

• U.P.S.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6-41

File Number

3556.4

HIP4081

Functional Block Diagram

(112 HIP4081)
HIGH VOLTAGE BUS S 80VDC

CBS

TO Veo (PIN 16)

DBS

+12VDC

= SUPPLY
BIAS

Typical Application (PWM Mode Switching)
80V

1

L

PWM
INPUT

GND
ToopnONAL
CURRENT CONTROLLER

~-....---<
6V~

~
6-42

GND

Specifications HIP4081
Absolute Maximum and Thermal Ratings
Supply Voltage, Voo and Vee .•....•.....••••.... -o.3V to 16V
Logic VO Voltages .•..••.••.....•...••..• -0.3V to Voo +0.3V
Voltage on AHS, BHS .•••••.•.••••••.• -6.0V (Transient) to 88V
Voltage on ALS, BLS ....•.. -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB ......... VAHS. SHS -o.3V to VAHS, SHS +16V,
or 95V, whichever is less
Voltage on ALO, BLO •.••..•....•.. VALS. SLS -0.3V to Vee +O.3V
Voltage on AHO, BHO ......•. VAHS. SHS -0.3V to VAHS. SHS +0.3V
Input Current, HDEL and LDEL .••.•••••••••••.•. -5mA to OmA
Phase Slew Rate .•••••.••.....•..•...••.•...••.••. 20Vlns
NOTE: All voltages are relative to pin 4, VSS, unless otherwise specified.

Storage Temperature Range ••..••...•..••.... -65"0 to + lSOoC
Operating Max. Junction Temperature ..•.••.•.••.••.•• + 125°C
Lead Temperature (Soldering lOs) ••.•..•.•••••.•••••• +3OOoC
(For SOIC - Lead Tips Only)
Thermal Resistance, Junction-Ambient
SOIC Package •.•.•..••••••.•••••.•.•••...•.••.. 85°C/W
DIP Package .•••••.••.••••••.••..••.......•...• 75°CIW
Maximum Power Dissipation at +85°C
SOIC Package ••.....•••.•..••••..•••••.••...••• 470mW
DIP Package •••••..•.•••.•••..•..••••.•••••.••• 530mW

CAUTION: Str8Sses above /hose listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a str8Ss only mting and opemticn
of the device at these or any other conditions above those indicated in the opemtional sections of this specification is not implied.

Operating Conditions
Supply Voltage, Voo and Vee •••.•.•..•...•...••. +6V to +15V
Voltage on ALS, BLS .•..•...••............... -1.0V to +1.0V
Voltage on AHS, BHS •.....•.•••..••••..••••..... -1 V to 80V

Electrical SpeCifications

Voltage on AHB, BHB . . • . . . . • .• VAHS. SHS +5V to VAHS, SHS +15V
Input Current, HDEL and LDEL. ............... -5OOIlA to -50ItA
Operating Ambient Temperature Range .•..•.•.•. -400C to +85°C

v DO = vee = VAHS = VSHS = 12V, Vss = VALS = VSLS = VAHS = VSHS = OV, RHOEL = RLOEL =lOOK and
TA =+25°C, Unless Otherwise Specified
TJs='400C
TO +125°C

T J = +25°C
PARAMETER

TEST CONDITIONS

SYMBOL

MIN

TYP MAX MIN

MAX UNITS

SUPPLY CURRENTS AND CHARGE PUMPS
VDO Quiescent Current

100

All Inputs = OV

7

9

11

6

12

rnA

VDO Operating Current

1000

Outputs Switching f =SOOkHz

8

9.5

12

7

13

mA

Vcc Quiescent Current

Icc

All Inputs =OV, IALO = ISLO =0

-

0.1

10

-

20

IlA

Vee Operating Current

leco

f = 500kHz, No Load

1

1.25

2.0

0.8

3

rnA

All Inputs =OV, IAHO = ISHO = 0
Voo = Vee = VAHS = VSHS = 10V

-SO

-30

-15

-60

-10

IlA

f =500kHz, No Load

0.5

0.9

1.3

0.4

1.7

mA

10

IlA

AHB, BHB Quiescent Current Qpump Output Current

IAHS,lsHS

AHB, BHB Operating Current

IAHBO, ISHOO

-

0.02

1.0

VAHS-VAHS
VSHS-VSHS

IAHS =IAHS =0, No Load

11.5

12.6

14.0

Low Level Input Voltage

VIL

Full Operating Conditions

-

-

0.8

V

VIH

Full Operating Conditions

2.5

-

1.0

High Level Input Voltage

-

2.7

-

V
mV

Low Level Input Current

IlL

VIN =OV, Full Operating Conditions

-130 -100

High Level Input CUrrent

IIH

VIN =5V, Full Operating Conditions

AHS, BHS, AHB, BHB Leakage Current

IHLK

AHB-AHS, BHB-BHS Qpump
Output Voltage

VAHS = VSHS =VAHS =VSHS =95V

10.5 14.5

V

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Input Voltage Hysteresis

35

-

-

-

:~

-135

-65

IlA

-1

-

+1

-10

+10

IlA

4.9

5.1

5.3

4.8

5.4

V

lOUT = 100mA

0.7

0.85

1.0

0.5

1.1

V

TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage

VHOEL, VLDEL IHDEL =ILDEL =-1 001lA

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage

VOL

High Level Output Voltage

Vce-VOH

lOUT = -100mA

0.8

.95

1.1

0.5

1.2

V

Peak Pullup Current

10+

VOUT=OV

1.7

2.6

3.8

1.4

4.1

A

Peak Pulldown CUrrent

10-

VOUT = 12V

1.7

2.4

3.3

1.3

3.6

A

6-43

Specifications HIP4081
Switching Specifications

=

=

voo vee VAHB
CL =1000pF

=VBHB = 12V, Vss = v AlS =VBLS =vAHS = VBHS =OV, RHOEL =RLDEL =10K,
TJS _-40oC
TO+125OC

TJ =+25°C
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX.

MIN

MAX UNITS

Lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)

TLPHL

-

30

60

-

80

ns

Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)

THPHL

-

35

70

-

90

ns

lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)

TLPLH

-

45

70

-

90

ns

Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)

THPLH

-

60

90

-

110

ns

10

25

ns

10

25

-

35

TF

-

35

ns

TpwlN-ON

50

50

TpwlN-OFF

-

-

40

-

40

45

75

-

95

ns

55

85

-

105

ns

35

70

-

90

ns

Rise Time

TR

Fall Time
Turn-on Input Pulse Width
Turn-off Input Pulse Width

-

ns
ns

Disable Turn-off Propagation Delay
(DIS - lower Outputs)

TOISLOW

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

TOISHIGH

-

Disable to lower Turn-on Propagation Delay
(DIS - AlO and BlO)

TOlPLH

-

Refresh Pulse Width (AlO and BlO)

TREF.pW

160

260

380

140

420

ns

THEN

-

335

500

-

550

ns

Disable to Upper Enable (DIS - AHO and BHO)

TRUTH TABLE
INPUT
ALI, Bli

AHI,BHI

X
1

OUTPUT
DIS

AlO,BlO

X

1

0

0

X

0

1

0

0

1

0

0

1

0

0

0

0

0

NOTE: X signifies that input ean be either a "1" or -0",

6-44

AHO,BHO

HIP4081
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

BHI

B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent ha~-brldge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo ). An Internall001lA
pull-up to Voo will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

3

DIS

DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signalleveis of
OV to 15V (no greater than VOO ). An internall00l1A pull-up to Voo will hold DIS high if this pin is not driven.

4

Vss

Chip negative supply, generally will be ground.

5

BU

B Low-side Input. logic level input that controls BlO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BlO and BHO drivers, with dead time set by delay currents at HDEl and lDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels
of OV to 15V (no greater than V OO ). An internall00l1A pull-up to Voo will hold BLI high if this pin is not driven.

6

ALI

A low-side Input. logic level inputthatcontrols AlO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both AlO and AHO drivers, with dead time set by delay currents at HDEl and lDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels
of OV to 15V (no greater than V oo). An internall001lA pull-up to Voo will hold ALI high if this pin is not driven.

7

AHI

A High-side Input. logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

8

HDEl

High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEl resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEl reference voltage is approximately 5.1 V.

9

lDEl

low-side turn-on DElay. Connect resistor from this pin to V ss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the lDEl resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. lDEl reference voltage is approximately 5.1 V.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacHor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capaCitor to this pin.

13

AlO

A low-side Output. Connect to gate of A low-side power MOSFET.

14

AlS

A low-side Source connection. Connect to source of A low-side power MOSFET.

15

Vec

Positive supply to gate drivers. Must be same potential as V DO (Pin 16). Connect to anodes of two bootstrap
diodes.

16

Voo

Positive supply to lower gate drivers. Must be same potential as Vcc (Pin 15). De-couple this pin to Vss (Pin 4).

17

BlS

B low-side Source connection. Connect to source of B low-side power MOSFET.

18

BlO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

20

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6-45

w

g
a:ID
..J
..J

:::;)

II..

HIP4081

Timing Diagrams
x= A OR B. A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
DlS.O

-- --

-- --

--,
xu

\

XHI

XLO

XHO

--

I

-if--

-- --

'1--

TLPLH

~

FIGURE 1. INDEPENDENT MODE

,----, , J ,----,
,------, ' ___....,' ' ___---'1

DlS.O---------------------------------------------------------------------

xu
XHI

=HI OR NOT CONNECTED

XLO

XHO

, ______,

------'I

''-_ _....,1

'-

FIGURE 2. BISTATE MODE

--

--

TOLPLH

DlS

~

~TREF·PW-

I

\

xu
XHI

I

XLO
.J

==-~j

XHO --+-I--I.-=----THE-N

)-----------

~

FIGURE 3. DISABLE FUNCTION

6·46

HIP4081

Typical Performance Curves

Voo

=Vcc =VAHB =V BHB =l2V, Vss =VALS =V BLS =VAHS = V BHS =OV, RHOEL =R LOEL =

lOOK and TA =+25°C, Unless Otherwise Specified
11.0

14.0

i

...z

10.5
12.0

w 10.0

a:
a:

::>
0

~

......
::>


~ StO

",'"

 20.0
0



15.0

,.,...

10.0
5.0

10-""'"

"",

"

",

400

+2SoC
ooC

3.0

o

~
It

l/



~
~~~

~

..... ......

o

a:aI

::::I

u.

100 200

300

400

500

600

700

800

1100 1000

SWITCHING FREQUENCY (kHz)

FIGURE 7. Iceo, NO-LOAD Icc SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE

-90

V

~ 1.0

...3!:
...
!!! -110

0.2

o

200

400
600
800
SWITCHING FREQUENCY (kHz)

-

~

./
-0.2

..........

~

..... ~

Z

~

!;

/'



/

...~
!5 0.6

........

~ -100

./'r'



SWITCHING FREQUENCY (kHz)

...z

800 1100 1000

- '-....,

.

-40oC,

::>

1/

0.0 I........
o 100 200 300

.§.

!Z
I:!
a:

"".

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT va
FREQUENCY (LOAD = 1000pF)

i

700

5.0

30.0

a:
a:

~

500 600

FIGURE 5. 1000 , NO-LOAD 100 SUPPLY CURRENT vs
FREQUENCY (kHz)

.§.

...z

400

SWITCHING FREQUENCY (kHz)

FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE

C

I'~

",,,,,,,

It
::>

./

4.0

9.5

B

~

Q

10-'1'
10-'1'

0
25
50
75
JUNCTION TEMPERATURE ("C)

100

125

FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IlL
vs TEMPERATURE

HIP4081
Typical Performance Curves
w

Voo =Vee =VAHS =VBHS =12V, Vss =V/oJ.s =VBLS = VAHS =VSHS = OV, RHOEL =RLOEL =
1OOK and TA = +25°C, Unless Otherwise Specified (Continued)
80

15.0

!.

;J

...:::E~

14.0

w

13.

~

I
CI

z

., 70

ot---

"""

~

12. 0

.s

-

~
~

"""

.... t---

0

"""

!i

~

!i
~0

t--- ~

...a:

~

11.0

!

10. 0
040

-20

o

~

60

~

M

~

100

~

40

30
040

1~

80

., 380

., 70

360

~w

Q

I-'"

~

!;( 340

r0- t---

60

0

1-0- i--"

!i
~

~

50

.... I-"" f--

...~ 40 ....

~

30
040

300

040

-20

0
20
40
60
80
100
JUNCTION TEMPERATURE fC)

120

FIGURE 12. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE

-20

I---' I-"" I-""
~

0
~
40
60
80
JUNCTION TEMPERATURE fC)

100

120

FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDlSLO vs TEMPERATURE

80

375

70
325

i

w
~
~ 275

~

r--

.,w

%

~

1~

z

... 320

a:

0
20
40
60
80
100
JUNCTION TEMPERATURE fC)

.s

.s

~

-20

FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TOISHIGH vs TEMPERATURE

400

.,.s

~

~~

--

50

JUNCTION TEMPERATURE (OC)

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE

~~

.... I-"" f--

z

I-"" I--"

.... I-'"

-

225
30

I I I I I I I I I I I I I I I I I I

175
040

-20

0

20

40

60

80

100

20

JUNCTION TEMPERATURE (OC)

FIGURE 14. TREF.PW REFRESH PULSE WIDTH vs TEMPERATURE

I I I I I I I I I I I I I I I I I I
040

120

-~

0
20
40
60
80
100
JUNCTION TEMPERATURE (Oc)

120

FIGURE 15. DISABLE TO LOWER ENABLE TOLPLH PROPAGATION DELAY vs TEMPERATURE

6-48

HIP4081
Typical Performance Curves

Voo =Vee

=VAHB =VBHB =12V. Vss =VALS =VBLS =VAHS =VBHS =OV. RHoEL =RLOEL =

10K and TA =+25°C. Unless 01herwise Specified

so

80

.

70

~w

60

70

I!l

z

50

!;i
CI

:

30

l..- I--'

I--' I-

i!i

50

~

40

~

30

20
-40

·20

o

20
40
~
~
100
JUNCTION TEMPERATURE (OC)

20
-40

120

FIGURE 16. UPPER TURN·OFF PROPAGATION DELAY THPHL
vs TEMPERATURE

70

~

60

100

120

..

70

~w

60

.5-

w

c
z

50

Ii
~

40

I..-

c

30

r-

z
0 50

~

"-

0
20
40
60
80
JUNCTION TEMPERATURE (OC)

so

.5-

0

·20

FIGURE 17. UPPER TURN·ON PROPAGATION DELAY THPLH VI
TEMPERATURE

so

..

..... ~

~

!;i

~I"'"

40

~

"-

_I--' ~

-

~

I-

~ 60

c
0

--

!

.5-

... --

l- I--' I-

r-

-

-~

Ii
~0

~ I""'"

"-

·20

020406080

100

30
20
-40

20
-40

40

cz:

120

·20

JUNCTION TEMPERATURE ('IC)

0204060

so

100

120

JUNCTION TEMPERATURE (OC)

FIGURE 18. LOWER TURN·OFF PROPAGATION DELAY T LPHL
vs TEMPERATURE

FIGURE 19. LOWER TURN·ON PROPAGATION DELAY T LPLH VI
TEMPERATURE
13.5 r-r-r-r-..................-....-....-,.-,.--,--,-.,-.,-""T""T-,

_1~5t:t:t:l:!=l=4=4=~~~~~~~:r:r~

!w

~ 11.5 t-t-t-t-+-+-+-+-+-++-+-+-+-+-t-t-1
~

a:

~ 10.5I-HHHH-i-i-i-i-i-i-t-t-t-t-+--1

z
cz:
j:!

8.5 L...-I....-I....-L....JL....JL.....JL.....J..............--<--<--<-L-L-L-L-I
-40

·20

0
20
40
60
80
100
JUNCTION TEMPERATURE ('IC)

9.5I-HHHH-iH-i-i-i-i-t-t-t-+-+--1
S.5 L...-I....-L....JL....JL.....JL.....JL.....J............................--<--<--<--<--<--'

120

-40

FIGURE 20. GATE DRIVE FALL TIME TFvs TEMPERATURE

·20

0
20
40
60
80
100
JUNCTION TEMPERATURE ('IC)

120

FIGURE 21. GATE DRIVE RISE TIME T R VB TEMPERATURE

6·49

HIP4081
Typical Performance Curves

Voo =Vee =VAHB =VBHB =12V, Vss = VALS =VBlS = VAHS =VSHS
lOOK and TA = +25°C, Unless Otherwise Specified

=OV, RHOEl =RLOEl =

1500

6.0

:;-

S

~

w

w

~

!j

!j

~

...~::.
...

1250

~

5.5

1000

w

tot

5.0

~
...0

==

oJ

9

qz
a:
::.
...

~

i'-.

V

750 I- -400 C
r
500

L-

L

I- +250 C'"

V
V

/'"

lL

V

L.

r

V

0
250 I- +75 C ~ ,......
r+1250C

4.0 L-L-L-L-L-L.....JL.....JL.....JL-JL-JL-JL-JL-JL-JL-J--I--I
-40
-20
o
20
40
60
80
100
120

.L.

L

lL
ooc-

I

o
6

8

JUNCTION TEMPERATURE ("C)

10

12

BIAS SUPPLY VOLTAGE

FIGURE 22. VLOEl.o VHDEl VOLTAGE vs TEMPERATURE

14

(~

FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE Vee - VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA

1500

3.5

I
I-- -400C
S
1250 I-w
ooC
I--

,

:;-

~

...

"-

1"- '"

~ 1000

~
It
~
~

U

:.:
z

750

iii

500
250

o

rrrr-

1/

/
+25"C
+750 C

V

V

/

1.5

Q

1.0

~

/

w

!cCI

/'"

2.0

w

V

0.5
0.0

8

10

12

6

14

8

7

9

3.5

./

~ 3.0

...z

V

w 2.5
a:
a:

iii 1.5
w

~

Q

~CI

./

2.0

~

./

500

V

:('200

V

S
...
zw

100
50

a:
a: 20
::.
u

V

V

~

10

iii

5

~

2

w

!j

0.5

~oJ

~

0.5
0.2

0.0
7

8

8

10

11

12

13

12

13

14

15

16

FIGURE 25. PEAK PULLDOWN CURRENT 10 vs BIAS SUPPLY
VOLTAGE

1.0

6

11

10

VDO,VCC,VAHB,VBHB~)

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERTURE AT 100mA

:.:
z

~

~

BIAS SUPPLY VOLTAGE (V)

U

~

+125"C

6

::.

~
~

,. V

a:
a:

::.

w

tot

3.0

~
zw 2.5

14

15

0.1

16

',-"Ii
3,OOOpF

I,..;""

1\

V

'\

100pF

V
10-"""

/'

'""" V'

k-"'"',;\.,

'"......::V '" '"
'"
/'

L

V
V

/' V

VV

V

/'

I-""'"

~

L

V

~,""

./

./

2

VDO,VCC,VAHB,VBHB(~

FIGURE 26. PEAK PULLUP CURRENT 10+ vs BIAS SUPPLY
VOLTAGE

I

10,OOOpF :-,

5

10

20

50

100 200

500 1000

SWITCHING FREQUENCY (kHz)

FIGURE 27. LOW VOLTAGE BIAS CURRENT leo (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE
LOAD CAPACITANCE

6-50

HIP4081
Typical Performance Curves

Voo

=Vcc =VAHB =V BHB =12V, Vss =VALS =VBLS =VAHS =V SHS =OV, RHOEL =RLOEL =

lOOK and TA = +25°C, Unlsss Otherwise Specified (Continued)
1000

...z~ 200
100
w

a:
a:

::>

SO

Ii:

20

~

10

>
w

5

w

...

."

V

120

fI'

~~

u

%

150

/'

500

~

V
I-'"

~ F--

~ r--

-.....

2

~

aov

r- : - 60V
-.....

r- t--

30

1-40V
-20V

2

5
10 20
50 100 200
SWITCHING FREQUENCY (kHz)

o

500 1000

kC

/'

100
150
200
HDEULDEL RESISTANCE (kil)

50

10

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE

V

./

V

L

250

FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE

HIP4081 Power-up Application Information
The HIP4081 H-Bridge Driver Ie requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4081 has four inputs, one for each output. Outputs
AlO and BlO are directly controlled by input AU and BU.
By holding AU and Bu low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 30. As the VoolVcc supply ramps from zero
up, the DIS voltage is below its input threshold of 1.7V due
to the R1/R2 resistor divider. When VoolVcc exceeds
approximately 9V to 10V, DIS becomes greater than the
input threshold and the chip disables all outputs. It is critical
that AU and Bu be held low prior to DIS reaching its threshold level of 1.7V while VoolV cc is ramping up, so that shoot
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.

..J
..J

:I

u.

FIGURE 30.

Veo

1.. f" ,,~'"

AU, BUt

12V, ANAL VALUE
8.5V TO 10.5V (ASSUMES 5% RESISTORS)

., . . . . . UIlIl . . . . . . .I I I I . . . . . . . . . ..

!

--~-----------------------

DIS

1,,~
",

'1.7V

t1
TIMING DIAGRAM FOR FIGURE 30

NOTE:
1. AU and/or BU may be high after tl, whereupon the ENABLE pin
may also be brought high.
2. Another product, HIP4081 A, incorporates undervoltage circuitry
which eliminates the need for the above power up circuitry.

6-51

I

IN2 IN1

POWER SECTION

+12V

r--------1~_-___10 B+

CONTROL LOGIC
SECTION

1

R29~ ?
~C6
L--~--,I. I I HIP~1
+

II> -

-

DRIVER SECTION

~~-

SHB
~2 HENlBHI

.--_+-+___

R21

CR2
C4

I

~

BHOi20

R22

L....._ _--'3'1 DIS

>~~--~

L....._ _ _ _~SOUT~U
6

CD4069UB

0

AO

+--Xx-;x , 0

BO

xxxx

4 VSS
O-~~+--;

IN~AU

7 IN-IAHI
.--------------:1

::s

8 HDEL
.------::1

~

R33 I

R34

9 LDEL
10,AHB

i

R24

.....

eR1

cw
CD4069UB

CW

l....--jC3

CS.f.
ALS

15K

TO DIS PIN
3.3K

COM

BLS
NOTE:
DEVICE CD4069US PIN 7 = COM, PIN 14 = +12V.

CD4069UB

FIGURE 31. HIP4081 EVALUATION BOARD SCHEMATIC

$

z:

Ul

••
••
••
••
••
••
••
••
••
••
••
••
••
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••
••
••
••
••
••
••

~

GND
@

@

••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
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••
••
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•
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•••
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••
••
••
•

@

orr

••
•••
•

••
••
••

••• •••
•• ••
••• •
•• ••

°u
••orr••
• •

••• •

••
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•
•••
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•

••
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••
••
••
••
••
••••

~

@~

B+

~~~~

• t; ~ • • • II

•

@~

$

+12V
@

01

~

••

~:

ul··@

::"-'@J
••

··B~@

R33

:

R34

•
ALS
• ALO
•

~

@

O·

R23

@

@

$

o

!::I

@B

Q4

Q2

~

R21

•

•

~D
@

a:

••
-

X

@

FIGURE 32. HIP4081 EVALUATION BOARD SILKSCREEN

0
!J

:.

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HIP4081A
80V/2.5A Peak, High Frequency
Full Bridge FET Driver

PRELIMINARY
April 1994

Features

Description

• Independently Drives 4 N-Channel FET In Half Bridge
or Full Bridge Configurations

The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency Class D audio amplifiers. and
power supplies.

• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz In Free Air at +50 oC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chlp Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels

For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum "on-time"
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion. resulting
in rapid, precise control of the driven load.

• Very Low Power Consumption
• Undervoltage Protection

Applications

A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle
wave and to facilitate "hysteresis mode" switching.

• Medium/large Voice Coil Motors
• Full Bridge Power Supplies

Ordering Information

• Class D Audio Power Amplifiers
• High Performance Motor Controls

PART
NUMBER

• Noise Cancellation Systems

TEMP RANGE

PACKAGE

• Battery Powered Vehicles

HIP4081 AlP

-40·C to +85°C 20 Lead Plastic DIP

• Peripherals

HIP4081 AlB

-400C to +85°C 20 Lead Plastic SOIC (W)

• U.P.S.

Pinout

Application Block Diagram
80V

HIP4081A (PDIP. SOIC)
TOP VIEW

!
BHO

L

BHS
BlO
BlS

lDEl ~
AHB 10

~

Voo

BHI

Vee

AlS

BU
HIP4081A

ALO

AU

AHS
AHO

1AHI

BlO

AlO

I

:~I
T

GND

GND

CAUTION: These devices are sensftive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6-54

File Number

3659.1

HIP4081A
Functional Block Diagram

(112 HIP4081A)
HIGH VOLTAGE BUS S BOVDC
AHB
~----~----+---,
AHO
CBS
AHS

Voo

TO Voo (PIN 16)

DBS

ALO

=

+12VDC
BIAS
SUPPLY

ALS

Typical Application (PWM Mode Switching)
BOV

J

J

L

w

g
a:III
..J
..J
::::l

IL

PWM
INPUT

GND
TO OPTIONAL
CURRENT CONTROLLER

~--+---<

GND

6-55

Specifications HIP4081 A
Absolute Maximum and Thermal Ratings
Supply Voltage, Voo and Vee ....••••••....•...•• -o.3V to 16V
Logic 1/0 Voltages ....................... -0.3V to Voo +O.3V
Voltage on AHS, BHS .•..•••..•••••••• -6.0V (Transient) to 9SV
Voltage on ALS, BLS ..•.•.. -2.0V (Transient) to +2.0V (lI'ansient)
Voltage on AHB, BHB ..•..•... VAHS, SHS -o.3V to VAHS. SHS +16V,
or 9SV, whichever is less
Voltage on ALO, BLO ••••••..•••••. VALS. SLS -0.3V to Vee +0.3V
Voltage on AHO, BHO •••••.•• VAHS. BHS -0.3V to VAHS. SHS +0.3V
Input Current, HDEL and LDEL •.••••••..•••..•.• -SmA to OmA
Phase Slew Rate •....•........•..•...•••......•••. 20v/ns
NOTE: All voltages are relative to pin 4, VSSo unless otherwise specified.

Storage Temperature Range •••••......•.••.•. -6SoC to +150°C
Operating Max. Junction Temperature ..•••.•••••.••.•• +12SoC
Lead Temperature (Soldering lOs)
(For sOle - Lead TIps Only) ....................... +3000C
Thermal Resistance, Junction-Ambient
SOIC Package .................................. 8SoCm
DIP Package ••••••.••...••••....•••.•..•.••••.. 7SoCm
Maximum Power Dissipation at +8SoC
SOIC Package ................................. .470mW
DIP Package ................................... S30mW

CAUTION: Stresses above those listed In -Absolute Maximum Ratings· may cause permanent damage to the devlcB. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Supply Voltage, Voo and Vee •••••..••..••••••.. +9.SV to +15V
Voltage on ALS, BLS ..•••.•..•••.•••••••.••.• -1.0V to +1.0V
Voltage on AHS, BHS .••••••.•••...•••.......•... -1 V to 80V

Electrical Specifications

Voltage on AHB, BHB • • • • • • . . •• VAHS. SHS +SV to VAHS, SHS + 15V
Input Current, HDEL and LDEL. ....•.•...••.•. -SooIlA to -SOIlA
Operating Ambient Temperature Range •.•.••.••. -4O"C to +85°C

voo = vee = VAHS = VSHS = 12V, vss = VALS = VSLS = v AHS = VSHS = OV, RHOEL = RLOEL = lOOK and
TA = +25°C, Unless Otherwise Specified
TJ

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TJs =-400C
TO+125°C

=+25°C

TYP MAX MIN MAX UNITS

SUPPLY CURRENTS AND CHARGE PUMPS
Voo Quiescent Current
Voo Operating Current

100

All inputs = OV

8.5

10.S 14.S

7.5

14.S

rnA

9.5

12.5

8.5

IS.S

mA

1000

Outputs switching f = 500kHz

Vee Quiescent Current

Icc

All Inputs = OV, IALO = ISLO = 0

-

0.1

10

-

20

IlA

Vee Operating Current

leeo

f = SOOkHz, No Load

1

1.25

2.0

0.8

3

rnA

All Inputs = OV, IAHO = 'SHO = 0
Voo = Vee = VAHS = VSHB = 10V

-50

-30

-11

-60

-10

IlA

f = SookHz, No Load

0.6

1.2

1.5

0.5

1.9

mA

-

0.02

1.0

-

10

IlA

II.S

12.6

14.0

10.5

14.S

V

1.0

V

AHB, BHB Quiescent Current Qpump Output Current

IAHS,lsHS

AHB, BHB Operating Current

IAHBO, IsHBO

AHS, BHS, AHB, BHB Leakage Current

IHLK

AHB-AHS, BHB-BHS Qpump
Output Voltage

VAHS = VSHS = VAHS = VSHS = 9SV

VAHS-VAHS
VSHS-VSHS

IAHS = IAHS = 0, No Load

Low Level Input Voltage

VIL

Full Operating Conditions

-

High Level Input Voltage

VIH

Full Operating Conditions

2.5

-

-

35

15.5

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Input Voltage Hysteresis
Low Level Input Current

IlL

VIN = OV, Full Operating Conditions

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-130 -100

-

0.8

2.7

-

V

-

-

-

mV

-75

-135

-65

IlA

-1

-

+1

-10

+10

IlA

4.9

5.1

5.3

4.8

5.4

V

1.0

0.5

1.1

V

TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage

VHOEL' VLDEL IHOEL = ILDEL = -1001lA

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND SHO
Low Level Output Voltage

VOL

lOUT = 100mA

0.7

0.85

High Level Output Voltage

Vee-VOH

lOUT = -100mA

0.8

0.9S

1.1

0.5

1.2

V

Peak Pullup Current

10+

VOUT=OV

1.7

2.6

3.8

1.4

4.1

A

Peak Pulldown Current

10-

VOUT = 12V

1.7

2.4

3.3

1.3

3.6

A

6-56

Specifications HIP4081A
Electrical Specifications

voo = vee = VAHB = VBHB = 12V, Vss = VALS = VBLS = VAHS = VBHS = OV, RHOEL = RLOEL = 100K and
TA =+25°C, Unless Otherwise Specified (Continued)
TJ = +2SoC

TJs=-40oC
TO+12SoC

MIN

TYP MAX MIN MAX UNITS

Undervoltage, Rising Threshold

UV+

8.1

8.8

9.4

8.0

9.5

V

Undervoltage, Falling Threshold

UV-

7.6

8.3

8.9

7.5

9.0

V

Undervoltage, Hysteresis

HYS

0.25

0.4

0.65

0.2

0.7

V

PARAMETER

SYMBOL

Switching Specifications

TEST CONDITIONS

voo = vee = VAHB = VBHB = 12V, vss = v ALS = v BLS = VAHS = VBHS = OV, RHDEL = RLOEL = 10K,
CL =1000pF.
TJS = -40°C
TO +12SoC

TJ = +2SoC

MAX UNITS

MIN

TYP

MAX

MIN

TLPHL

-

30

60

-

80

ns

Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)

THPHL

-

35

70

-

90

ns

lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)

TLPLH

RHDEL = RLDEL = 10K

-

45

70

-

90

ns

Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)

THPLH

RHDEL = RLDEL = 10K

-

60

90

-

110

ns

PARAMETER

SYMBOL

lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)

TEST CONDITIONS

Rise Time

TR

25

-

35

ns

TF

-

10

Fall Time

10

25

-

35

ns

Turn-on Input Pulse Width

TPWIN.QN

RHOEL = RLDEL = 10K

50

50

-

ns

Turn-off Input Pulse Width

40

-

ns
ns

30

-

TPWIN.QFF

RHOEL = RLDEL = 10K

40

-

Turn-on Output Pulse Width

TpWOUT.QN

RHOEL = RLDEL = 10K

40

-

Turn-off Output Pulse Width

TPWOUT.QFF

RHOEL = RLDEL = 10K

30

-

-

40

ns

Disable Turn-off Propagation Delay
(DIS - lower Outputs)

TDISLOW

-

45

75

-

95

ns

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

TOISHIGH

-

55

85

-

105

ns

Disable to lower Turn-on Propagation Delay
(DIS - ALO and BlO)

TDLPLH

-

35

70

-

90

ns

Refresh Pulse Width (AlO and BlO)

TREF.PW

240

380

500

200

600

ns

TUEN

-

335

500

-

550

ns

Disable to Upper Enable (DIS - AHO and BHO)

TRUTH TABLE
OUTPUT

INPUT
AHI,BHI

UN

X

X

1

X

0
0
X

X

ALI, Blf

DIS

AlO,BlO

X

1

0

0

0

0

1

0

1

0

0

0

1

0

0

0

0

0

1

X

0

0

NOTE: X signifies that input ean be either a -1" or -0".

6-57

AHO,BHO

w

g
a:ID
....I
....I

~

HIP4081A
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

BHI

B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels 01 OV to 15V (no greater than Voo). An Internall001lA
pull-up to Voo will hold BHI high, so no connection Is required if high-side and low-side outputs are to be controlled by the low-side input.

3

DIS

DISable Input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
OV to 15V (no greater than Voo ). An Internall001lA pull-up to Voo will hold DIS high if this pin is not driven.

4

Vss

Chip negative supply, generally will be ground.

5

BLI

B Low-side Input. Logic level input that controls BLO driver (Pin 18).11 BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, wtth dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level Input. The pin can be driven by signal levels
of OV to 15V (no greater than Voo ). An internall001lA pull-up to Voo will hold BLI high if this pin is not driven.

6

ALI

A Low-side Input. Logic level input that controls ALO driver (Pin 13). II AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL
(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level Input. The pin can be driven by signal levels
of OV to 15V (no greater than Voo ). An internal1001lA pull-up to Voo will hold ALI high if this pin is not driven.

7

AHI

A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI
high level Input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An Internall00IlA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

8

HDEL

High-side turn-on DElay. Connect resistor from this pin to Vss to set timing currentthat defines the turn-on delay
of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage Is approximately 5.1 V.

9

LDEL

Low-side turn-on DELay. Connect resistor from this pin to Vss to set timing current that defines the turn-on delay
of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1 V.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacttor to this pin. Internal charge pump supplies 301lA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

13

ALO

A Low-side Output. Connect to gate of A Low-side power MOSFET.

14

ALS

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

15

Vee

Positive supply to gate drivers. Must be same potential as Voe (Pin 16). Connect to anodes of two bootstrap
diodes.

16

Veo

Positive supply to lower gate drivers. Must be same potential as Vee (Pin 15). De-couple this pin to Vss (Pin 4).

17

BLS

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

18

BLO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

20

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6-58

HIP4081A
Timing Diagrams

x " A OR B, A AND B HALVES OF BRIDGE CONTROllER ARE INDEPENDENT
---

--

....

TLPHL

o

THPHL

I--

xu

\

/

XHI

/

XLO

I

XHO

--- '1--

---

£

--

TLPLH

l-TF

(10%-90%)

FIGURE 1. INDEPENDENT MODE

UN" DIS ,,0

-----------------------------------------------------\~----II

xu

I

\

I

\

w

XHI = HI OR NOT CONNECTED


(J

~

8.0

~

CI.
CI.

:::>

6.0

In

II

~

"

~

10.5

!z

10.0

G

8.5

~

i-"~

~~

CI.

~

II

Q.O

..........

8

10
12
VOO SUPPLY VOLTAGE (V)

14

~~

..........

o

100 200 300 400 500 600 700 900 800 1000
SWITCHING FREQUENCY (kHz)

FIGURE 5. 1000 , NO-LOAD 100 SUPPLY CURRENT vs
FREQUENCY (kHz)

FIGURE 4. QUIESCENT 100 SUPPLY CURRENT vs Voo
SUPPLY VOLTAGE

5.0

C

30.0

+1250 C

.§.

...z

C

25.0

w

II:
II:

:::> 20.0
(J
C

".....,

iii 15.0
~
CI.
CI.

CJ
Z

!z

oOC

:::>

-400 C

./

o

"

-

..........

1/
V k.::

In

.§

1.0

0.0

100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)

.......
...0lI:l IiiiiJII

~ iIII""""
o 100 200

""""

300 400

""""
:::>
~

'-,. K

./

~

"

./

5.0
0.0

+250 C

~
CI. 2.0

./

 10.0

...9

+75OC

4.0

~ 3.0


(J

~

/

CI.
CI.

:::>


70

.s.

425

i

..
"-

0

"'

-25

50

fii

r---.....
o

...0~
...

.

............ r---

40

II:

30
20

25

50

75

100

125 150

-40

JUNCTION TEMPERATURE rC)

-20

o

20
40
60
80
100
JUNCTION TEMPERATURE rC)

120

FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGA·
TION DELAYvs TEMPERATURE

FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERA·
TURE

6-61

HIP4081A
Typical Performance Curves

!

~

=

=

70

70

....

40

-I-

l- I- i"""

30

--

....

~

-20

0
20
40
60
80
100
JUNCTION TEMPERATURE <"C)

20
-40

1~

..

70

.s.
~

60

40

a:

.....

20
-40

-20

-

I- ~

.... i-

0
20
40
60
80
JUNCTION TEMPERATURE (OC)

-

~
~
80
80
JUNCTION TEMPERATURE (OC)

100

1~

70

....I-

60

100

~

40

0

...
a:

30
20
-40

1~

-20

0
20
40
60
80
100
JUNCTION TEMPERATURE <"C)

120

FIGURE 19. LOWER TURN-ON PROPAGATION DELAYT LPLHvS
TEMPERATURE
13.5 r-,--,--,--,--,--,--.--.---r--r-,--,---r--r--r-.,-,

13.5 r-r-r-,--,--,--,--,--,--.--.--.--.--.---r--r--r--,

! 1~5

"1~5r-r-t-t-t-+-+-+-+-+-+-+-+-+-+-+-+-~

.s.
w

r-+-+-+-+-+-+-+-+-+-++~-r-r-r-r,

w

~ 11.51-1-1-1-1-1-1-+-+-+-+-+-+-+++-r~

11.5 r-t-t-+-+-+-+-+-+-+-+-+-+-+-+-+-+~

w

~

l!!

w

~ 10.5

CI SI.5m-mm=mmm
8.Jd= I: I I I I I I I I I I I I I I I
~

o

~

FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE

~
....

-20

:z: 50
0

~

:::E

I- I-r-"

~

z 50

30

-- -

.... ....

80

Q

...

=OV, RHDEL =RLDEL =

FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH VS
TEMPERATURE

80

~
0

=

30

FIGURE 16. UPPER TURN-OFF PROPAGATION DELAYTHPHL
vs TEMPERATURE

.s.
~
w

=

-

20
-40

=

~

60

~ 50

..

=

80

Ii

...a:

=

80

~

~

=

VDD Vee VAHB VBHB 12V, Vss VALS VBLS VAHS VBHS
10K and TA = +250 C, Unless Otherwise Specified (Continued)

~-+-r~+-~~-+~~+-~-+-r~

-40

-~

0
20
40
60
80
100
JUNCTION TEMPERATURE (OC)

120

~

a:
~

10.5
r-t-t-t-+-+-+-+-+-+-+++~~-r-r~

9.5I-HHHH-l-l-+-+-+-+-+-+-+-+-+-1

1I I I I I I I I I I I I I I I I I

8.5
-40

_

0

~

~

60

80

100

1~

JUNCTION TEMPERATURE <"C)

FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE

FIGURE 20. GATE DRIVE FALL TIME TF VB TEMPERATURE

6-62

HIP4081A
Typical Performance Curves

Voo = Vee = VAHB = VBHB = l2V, Vss = VAJ,.S = VBLS = VAHS = VBHS = OV, RHOEL = RLOEL =
lOOK and TA = +25°C, Unless Otherwise Specified
1500

6.0

:;-

.sw 1250

~

~
5 1000

w
C! 5.5

i:!i

:..J

>

§!

....
::>
Do.

!;;:

~

5.0

:!:

""

~

L

750

-

500

oOC
+250c

12

10

.s
1250
w

g

w 2.5
a:
a:

>

::>
0

w

:.:
z

750

~

-

-40 oC

""

500 -

oOC

-

+250 C

250 -

+750 C

-

+12S oC

L

L

L

// //

~

.,...

// /

w 1.0

£C

C!

..J
..J

ID

!;;:

0.5

~

0.0

12

6

14

7

8

3.5

3.0

....

ffi

a:
a:

o

2.5

.., V

2.0

:.:
z
iii 1.5
~

~w

V

1.0

..,.,

500

. /V



-" V

./ ,/

V

""

~

-"

V

,/

/

V

'-...,
'-..., 0,..

/'
,/

V

V

'-...,

::>
0

11

14

I

3,000pF

z

w

10

13

10,000pF _

.s
100
....
-c

g

12

Veo, Vee. VAHB, VBHB (V)

"
7

11

FIGURE 25. PEAK PUlLDOWN CURRENT 10 vs BIAS SUPPLY
VOLTAGE

V V

6

10

G

BIAS SUPPLY VOLTAGE (V)

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERTURE AT 100mA

::>

w

g

0

//
/

10

g

......

..,.,. V

.,... V

2.0

iii
w 1.5

L

.,... V

3.0

....
z

5~ 1000

o

-

3.5

1500

~

14

FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE Vee· VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA

:;-

~a:

V

BIAS SUPPLY VOLTAGE (V)

FIGURE 22. VLOEL' VHOEL VOLTAGE vs TEMPERATURE

!;;:

V/

+1250 C-

JUNCTION TEMPERATURE ("C)

Ii;

5

+75"C' /

-

o

// /
//

-40oC~

_

a:
250 ~
4.0 '--'--'--.l-.l--'--'--'--'--'-...L....L.-L....L....L.-L-L.....J
-40
·20
o
~
~
~
~
100
1~

~

L

w

""

10

20

SO

100 200

500 1000

SWITCHING FREQUENCY (kHz)

FIGURE 27. LOW VOLTAGE BIAS CURRENT 100 (LESS QUIESCENT COMPOENT) vs FREQUENCY AND GATE
LOAD CAPACITANCE

6·63

HIP4081A

Typical Performance Curves

=

=

=

=

=

=

1000

...z~ 200
w
a:
a:
0

t:

:E
Ul

.:.
w

100
50

10

./

V

>
~

20

=

=OV, RHOEl =RlOEl =

/

500

::>

=

Voo Vee VAHB VSHS 12V, Vss VM.S VSLS VAHS VSHS
1OOK and TA = +25°C, Unless Otherwise Specified (Continued)

V
10

20

50

./

100

./

200

500

1000

SWITCHING FREQUENCY (kHz)

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT VI FREQUENCY AND BUS VOLTAGE

9.0

-

:E

~

I"'""

8.8

ui

~
g

I

-

Uv+

i'-.~

~

8.6

~

......

-

::>
Ul
Ul

.:

8.4

iii

UV-

--r-- I"- r.......~

8.2

50

o

25

25

n

~

100

125

1~

TEMPERATURE ("C)

FIGURE 29. UNDERVOLTAGE LOCKOUT VI TEMPERATURE
150

120

V

L

~

./

30

:/

/V
50

100
150
200
HDEULDEL RESISTANCE (kn)

250

FIGURE 30. MINIMUM DEAD-TIME VI DEL RESISTANCE

6-64

IN2 INl

POWER SEcnON

+12V

o

CONTROL LOGIC
SEcnON

oa~,____~
..,;_IL i

~------~~~--~o~
DRIVER SECTION
CR2
C6

1=

HIP4080AI81A
Ul
C4
jjij0120
llBHB
2 HENlBHI

Ir---t-tL---;]3 DIS
JMPR2IN~AU

~
CD4069UB

AO

4 Vss

5 OUTIBU
L---------~6~IN~AU

BO

7 IN-IAHI

11r-------Ala HDEL

3:
~

~ LDEL

~

!.!

-

AHB

2
~

CRl
CD4069UB

C3

'---II

cs-!-

COM

ALS

BLS
NOTES:
DEVICE CD4069UB PIN 7 .. COM, PIt! 14 .. +12V.

CD4069UB

FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC

$

m

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FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN

@

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HIP4082
80Vl1.25A Peak Current
Full Bridge FET Driver

ADVANCE INFORMATION
April 1994

Features

Description

• Independently Drives 4 N-Channel FET In Half Bridge
or Full Bridge Configurations

The HIP4082 is a medium frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 16 lead plastic
sOle and DIP packages.

• Bootstrap Supply Max Voltage to 9SVDC
• Drives 1000pF Load In Free Air at SOoC with Rise and
Fall Times of Typically 1Sns
• User-Programmable Dead Time (0.1 to 4.Sus)
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with SV to 1SV
Logic Levels
• Shoot-Through Protection
• Undervoltage Protection

Applications

Specifically targeted for PWM motor control and UPS applications, bridge based designs are made simple and flexible w~h
the HIP4082 Full Bridge Driver. With operation up to SOV, the
device is best suited to applications of moderate power levels.
Similar to the HIP4081, it has a flexible input protocol for
driving every possible switch combination except those
which would cause a shoot-through condition. The HIP4082
has reduced drive current compared to the HIP4081 (1.25 vs
2.5A) and a much wider range of programmable dead times
(0.1 to 4.5us) making it ideal for switching frequencies in the
20kHz to 200kHz range. Unlike the HIP4081 the HIP4082
does not contain an internal charge pump.
This set of features and specifications is optimized for applications where size and cost are important. For applications
needing higher drive capability the HIP4080A and HIP4081A
are recommended.

• UPS Systems
• DC Motor Controls
• Full Bridge Power Supplies

Ordering Information

• Class D Audio Power Amplifiers
• Noise Cancellation Systems

PART NUMBER

• Battery Powered Vehicles
• Peripherals
• MedlumlLarge Voice Coli Motors

Pinout

TEMPERATURE
RANGE

PACKAGE

HIP4082IP

-4O"C to +8SoC

16 Lead Plastic DIP

HIP4082IB

-4O"C to +85°C

16 Lead Plastic SOIC (N)

Applicationn Block Diagram
IOV

HIP4082 (PDIP, SOIC)
TOP VIEW

1

L

BHI
BU
HIP4082

t-----+-------t-----'

AU

ALO

AHI

AHs~----4_------_+----~

AHO~----4_-------_+-----~

GND

GND

CAUTION: These d9\lices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

6·67

File Number

3676

HIP4082

Functional Block Diagram

r------------------------------------------,

Voo

Vss

6~------------------------------------------~

Typical Application (PWM Mode Switching)
80V

1

TO OPTIONAL
CURRENT CONTROLLER OR
OVERCURRENT LATCH

GND

6-68

L

Specifications HIP4082
Absolute Maximum and Thermal Ratings

Thermal Information

Supply Voltage, Voo .•..•••.....••...••••..•..• -o.3V to 16V
Logic VO Voltages .•••...••••••••••••.••. -0.3V to Voo +0.3V
Vollage on AHS, BHS. • . . . . • . . . • • . • • .. -6.0V (Transient) to sav
Voltage on AHB, BHB ........ VAHS. VBHS -o.3V to VAHS. BHS +16V,
or 95V, whichever Is less
Voltage on ALO, BLO .••.••••..•••••••. Vss -0.3V to Vcc +O.3V
Voltage on AHO, BHO ..•••• VAH$, VBHS -0.3V to VAHB• VBHB +O.3V
Input Current, DEL .....•............••••.••••• -5mA to OrnA
Phase Slew Rate •••...•.•......•.....•••...••..... 20v/ns

Storage Temperature Range .••..••••.•.••.••. -65°C to + 1SOoC
Operating Max. Junction Temperature .••••••.•...•••.. +125°C
Lead Temperature (Soldering 10s) •••••••••.••.•••••.• +3000C
(For SOIC - Lead Tips Only)
Thermal Resistance, Junction-Ambient
SOIC Package ••.••••.•••....•.••.•••••••••..•• 1500c/w
DIP Package •••••••••••••.•••••.••••.•.••••.••. 90oC/W
Maximum Power Dissipation at +85°C
SOIC Package •••••.•.••••••.•...••••...•••••••• 266mW
DIP Package ..•.•••....•.•.•.••..........•..... 445mW

CAUTION: StrBSses above those listed in -Absolute Maximum Ratings' may cause permanent damage to the device. This is a strBSs only rating and operation
of the device at these or any other conditions above those Indicated in the operational sections of this specification is not Implied.

Operating Conditions
Supply Voltage, VDO ...••...........••.....••. +SV to +15V
Voltage on Vss .•.....•.•..........••....••.• -1.0V to + 1.0V
Voltage on AHS, BHS •.••••••••.••.....•.••....•. -1V to SOV

Electrical Specifications

Voltage on AHB, BHB ••..•••. VAHS, VBHS +7V to VAHS. VBHS +15V
Input Current, DEL ......................... -4rnA to -1 OCl\lA
Operating Ambient Temperature Range ••••••.••. -40"C to +85°C

voo = v AHB = VBHB = 12V, Vss = v AHS = v BHS = OV, ROEl = 100K
TJs=-400C
TO+125°C

T J = +2S0C
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP MAX MIN MAX UNITS

SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDO Quiescent Current
Voo Operating Current

100

All inputs = OV

-

2.25

-

-

1000

Outputs Switching f = 50kHz,

-

4.25

-

-

IAHBl,lSHBl

AHI =BHI =OV

AHB, BHB On Quiescent Current

IAHBH' ISHBH

AHI = BHI = Voo

-

AHB, BHB Operating Current

IAHBO,IBHBO

f = 50kHz, Cl=1000pF

-

AHB, BHB Off Quiescent Current

Voo Rising Undervoltage Threshold
Voo Falling Undervoltage Threshold

VDDUV+
UV-

Undervoltage Hysteresis

UVHYS

AHB, BHB Undervoltage Threshold

VHBUV

-

7.5

5.5

-

145
1.0
O.S

7.0
0.5

-

rnA

-

rnA

IIA
rnA

-

rnA

-

V

-

-

V

-

V

-

V

INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Vollage

V1l

Full Operating Conditions

-

-

1.0

-

O.S

V

High Level Input Voltage

VIH

Full Operating Conditions

2.5

35

-

-

V

-

-

2.7

mV

Low Level Input Current

III

VIN = OV, Full Operating Conditions

-130 -100

-75

-135

-65

IIA

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-1

-

+1

-10

+10

IIA

IOEl = -1 001lA

-

4.4

-

-

-

uS

VOL

lOUT = 50mA

0.7

0.S5

1.0

0.5

1.1

V

Vee-VoH

IOUT=-50mA

O.S

.95

1.1

0.5

1.2

V

VOUT=OV

-

1.3

-

-

-

A

VOUT = 12V

-

1.2

-

-

-

A

Input Vo~age Hysteresis

TURN-ON DELAY PIN DEL
Dead Time

TOEAO

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Vo~age
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current

10+
10-

6-69

Specifications HIP4082

TJS= "",Ooc
TO+125°C

TJ =+2SOC
PARAMETER

TEST CONDITIONS

SYMBOL

MIN

TVP

MAX

MIN

MAX

UNITS

lower Turn-off Propagation Delay
(ALI-AlO, BLI-BlO)

TLPHl

-

25

-

-

-

ns

Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)

THPHl

-

30

-

-

-

ns

lower Turn-on Propagation Delay
(ALI-AlO, BLI-BlO)

TLPLH

ROEl = 10K

-

35

-

-

-

ns

Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)

THPLH

ROEl = 10K

-

50

-

-

-

ns

-

-

-

50

-

Rise lime

TR

Fall lime

TF

-

15
15

Turn-on Input Pulse Width

Tpw1N'()N

ROEl = 10K

50

-

Turn-off Input Pulse Width

TPW1N'()FF

ROEl = 10K

50

-

ns
ns
ns

Disable Turn-oil Propagation Delay
(DIS - lower Outputs)

TOISlOW

-

50

-

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

TOISHIGH

-

60

-

-

-

ns

Disable to Lower Turn-on Propagation Delay
(DIS - AlO & BlO)

TOLPlH

-

50

-

-

-

ns

Disable to Upper Enable (DIS - AHO & BHO)

TOHPlH

-

620

-

ns

TREF•PW

-

580

-

-

Refresh Pulse Width (AlO & BLO)

-

-

ns

ns

-

-

50

ns

NOTE:
1. All vollages are relative to pin 6, VSS, unless otherwise specified.

TRUTH TABLE
INPUT

OUTPUT

ALI, Bli

AHI,BHI

VDDUV

VHBUV

DIS

AlO,BlO

AHO,BHO

X

X

X

X

1

0

0

X

X

1

X

X

0

0

0

X

0

1

0

0

0

1

X

0

X

0

1

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

NOTE: X signifies that input can be either a "I" or "0".

6-70

HIP4082
Pin Descriptions
PIN
NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin.

2

BHI

B High-side Input. logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI
high level input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

3

BLI

B low-side Input. logic level input that controls BlO driver (Pin 14). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BlO and BHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of OV
to 15V (no greater than VDO). An internal 100llA pull-up to Voo will hold BLI high if this pin is not driven.

4

ALI

A low-side Input. logic level input that controls AlO driver (Pin 13). If AHI (Pin 7) Is driven high or not connected externally then ALI controls both AlO and AHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of OV
to 15V (no greater than Voo ). An internal 1OOIlA pull-up to Voo will hold ALI high if this pin is not driven.

5

DEL

Turn-on DElay. Connect resistor from this pin to Vss to set timing current that defines the dead time between
drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. The voltage across the DEL resistor Is approximately Voo -2V.

6

Vss

Chip negative supply, generally will be ground.

7

AHI

A High-side Input. logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI
high level Input. The pin can be driven by signal levels of OV to 15V (no greater than Voo). An internall001lA
pull-up to Voo will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

8

DIS

DISable input. logic level input that when taken high sets all four outputs low. DIS high overrides all other Inputs. When DIS is taken low the outputs are controlled by the other Inputs. The pin can be driven by signal
levels of OV to 15V (no greater than VOO ). An internal 1OOIlA pull-up to Voo will hold DIS high if this pin is not
driven.

9

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin.

10

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

11

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

12

Voo

Positive supply to control logic and lower gate drivers. De-couple this pin to Vss (Pin 6).

13

AlO

A low-side Output. Connect to gate of A low-side power MOSFET.

14

BlO

B low-side Output. Connect to gate of B low-side power MOSFET.

15

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.

16

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6-71

HIP4082
Timing Diagrams
X. A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT

-- --

-- -TLPHL

OIS.0

.ndUV

,

xu ~

,

/

XHI

/

/

XLO

XHO

--

I

--

'1--

-4-

I--

TLPLH

-l-

FIGURE 1. INDEPENDENT MODE

OIS.0----------------------------------------------------------------------1'
\""'---,
\""'---,

end:~ _ _ _"'\\"'_ _ _
XHI. HI OR NOT CONNECTED

\~---,'

XLO

XHO _ _ _ _ _ _,

\'-_ _..."

\""'-----,

\"-_ _...,1

\'-__--1'

'-

FIGURE 2. BISTATE MODE

TDLPLH

TOIS

-+__~--------~~------~--'

XU ____
XHI

XLO

XHO

----I-JI

--~I----TDH-Pl.H-::::::"-.j1

\~----------------------------FIGURE 3. DISABLE FUNCTION

6-72

INTELLIGEN
POWERICs

7

REGULATORS/POWER SUPPLIES

PAGE
REGULATORS/POWER SUPPUES SELECTION GUIDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-2

REGULATORSIPOWER SUPPUES DATA SHEETS

CA723, CA723C

Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA
Without External Pass Transistors .........................................•

7-3

CA 1523

Voltage Regulator Control Circuit for Variable Switching Regulator ................ .

7-11

CA1524, CA2524,
CA3524

Regulating Pulse Width Modulator ...............................•..........

7-16

CA3085, CA3085A, Positive Voltage Regulators from 1.7V to 46Vat Currents Up to 100mA ............ .
CA3085B

7-31

CA3277

Dual 5V Regulator with Serial Data Buffer Interface for Microcontroller Applications ....

7-39

HIP5060

Power ControllC Single Chip Power Supply ...............••.....•............

7-47

HIP5061

7A, High Efficiency Current Mode Controlled PWM Regulator .......•..........•..

7-53

HIP5062

Power ControllC Single Chip Dual Switching Power Supply ..................... .

7-73

HIP5063

Power ControllC Single Chip Power Supply ............................•...•..

7-BO

HIP5500

High Voltage IC Half Bridge Gate Driver ..................................... .

7-84

HIP5600

Thermally Protected High Voltage Linear Regulator ...............•.............

7-94

ICL7660

CMOS Voltage Converter ................................................ .

7-109

ICL7660S

Super Voltage Converter ................................................. .

7-118

ICL7662

CMOS Voltage Converter ....•..............................•.........•...

7-128

ICL7663S

CMOS Programmable Micropower Positive Voltage Regulator.................... .

7-138

ICL7665S

CMOS Micropower Over/Under Voltage Detector ...........................•••.

7-145

ICL7673

Automatic Battery Back-Up Switch .....................•.................•••

7-155

ICL8211, ICL8212

Programmable Voltage Detectors .............................•.............

7-161

7-1

(/)

CiS~
a:..1

08:
S~
w:=

::la:
eJIII
a:O
Q.

Regulators/Power Supplies Selection Guides
POWER SUPPLY CIRCUITS

DEVICE
CA723

DESCRIPTION
Linear Voltage Regulators

INPUT
VOLTAGE
RANGE

OUTPUT
VOLTAGE
RANGE

MAXIMUM
OUTPUT
CURRENT

9.SVt040V

2V to 37V

150mA

SWITCHING
FREQUENCY

QUIESCENT TEMPERATURE
CURRENT
RANGE

-

CA723C
~

CAl 523

Variable Internal Pulse Regulator for
Switch Mode Power Supplies

lWto ISV

S.9Vt07.SV
(Note 1)

SOmA

CAl 524

Pulse Width Modulators

BVt040V

4.BVto S.2V
(Note 1)

l00mA Max Rating br
Each 0u1pul Driver

200kHz

1kHz to 300kHz

3.5mA

-s5"C to +125°C

4.0mA

OOCto +7COC

34mA

OOCto +7COC

IOmA

-S5"C to +125°C

CA2S24

4.BVto S.2V
(Note 1)

OOCto +7COC

CA3S24

4.6VtoS.4V
(Note 1)

OOCto +70oC

CA308S

Linear Voltage Regulators

-

7.SVto 30V

1.8Vt026V

12mA to l00mA

CA308SA

7.SVIo40V

1.7V10 36V

12mA 10 l00mA

S.OmAat
VIN=40V

CA308SB

7.SVIo SOV

1.7Vto 46V

12mA to l00mA

7.OmAat
VIN = SOV

-

-4COC to +SSoC

lMHz Intarnal,
External Input

20mA

OOCto+85"C

2S0kHz

25mA

OOCto ..a5"c
Therm. Protect.

Two Power DMOS
Transistors SOV - SA

lMHz Latched
External Loop

2SmA

OOC 10 +8SoC

PowerDMOS
Transistor 60V - lOA

External Clock

14mA

OOC to +8SoC

30kHz 10 300kHz

7mA

-4COC to + IS00C

-

6SIlA

-4COC to +1oCOC
Therm. Protect.

10kHz to 35kHz

2001lA

-s5"c to +12SoC

1BOllA

-40°C to +BSoC

Microprocessor Interlace Controller
Dual-Fixed 5V Regulator, Overvoltage Shutdown, Thermal Shutdown,
Current Limited

6.2Vto 18V

0u1pull - Full Time Oulput 1 - l00mA
SV±0.2SV
Oulput 2 - l00mA
0u1pul2 - Switched
SV±O.2SV

HIPS060

Single Chip, Low Side Switch,
Current Controlled PWM

27Vto 4SV

Determined by
External Circuitry

PowerDMOS
Transistor SOV -lOA

HIPS081

7A Current Mode PWM RegulatorT0220 Type Package

IO.8V Min
14V Zener

Determined by
External Circuitry

PowerDMOS
Transistor SOV-7A

HIPS062

Single Chip, Dual Low Side Switch
Current Controlled PWM

26V10 42V

Determined by
External Circuitry

HIPS083

Basic Single Chip, Low Side Switch
Current Controlled PWM

10Vto 60V

Determined by
External Circuitry

HIPS500

Halt Bridge Power Supply Regulator

10V to ISV

SOOV Peak

2.M Peak

HIPSSOO

High Voltage Linear Regulator

SOVto 400V

1.2Vto 350V

30mA

ICL7660SM

Super Voltage Converter (Charge
Pump Type)

I.SVlo 12V

-1.SV to ± 22.8V

45rnA

ICL7660SC
ICL7662M
ICL7662C

Voltage Converter (Charge Pump
Type)

4.5Vto 20V

-4.SV to ±38.8V

10kHz

90mA

ICL76621
ICL7663SA

Linear Voltage Regulalors

1.6Vto 16V

1.3Vto 16V

ICL7663S

-55°C to +12SoC

SOOIlA

CA3277

ICL7660S1

4.SmAat
VIN= 30V

40mA- VOUT2
RoN - lOon -VOUT2

1801lA

OOCto +70oC

2S01lA

-s5"c to +12SoC

2001lA

OOCto +70oC

2001lA

-4COC to +8SoC

101lA

-25"C 10 +8SoC

121lA

OOCto +7COC

Note 1. Reference vottagas - Output Voltage limited by External DeVice
VOLTAGE MONITORING CIRCUITS
DEVICE
ICL7665SAI
ICL7665SAC

DESCRIPTION
CMOS Micropower Overl
Under Voltage Deteclor

VOLTAGE
RANGE

QUIESCENT
CURRENT

OUTPUT
CURRENT

INPUT TRIP
VOLTAGE

TEMPERATURE
RANGE

1.8Vlo 16V

101lA

2mA

1.3±2%

-4COC to +8SoC

ICL7665S1

ICL8211C

-40oC to +8SoC

1.3±8%

OOCIo +70oC

2.SVto 15V

5~J\

38mA

50mV
(Nole2)

·2S>C to .BSoC

Programmable Voltage
Detectors

1.8Vt030V

3S01lA

3mA

1.15+3.5%
1.15 - 6.0%

-55°C to + 125°C

9mA

1.15+3.S%
1.15-13%

-55°C to + 12SoC

ICL7673C
ICL8211M

COCto +70oC

1.3±2%

Autornatic Bctlc:"j Sac!H:p S'.v:tch

ICL766SSC
,,..,., "7C7."

1.3±8%

ICL8212M
ICL8212C

Note 2. Primary to Back-up Source Voltage Differential

7-2

o"Clo +70oC

o"Cto +70oC

COCIo +70oC

HARRIS
SEMICONDUCTOR

CA723, CA 723C

Voltage Regulators Adjustable from 2V to 37V at Output
Currents Up to 150mA Without External Pass Transistors

April 1994

Features

Description

• Up to 150mA Output Current
• Positive and Negative Voltage Regulation
• Regulation in Excess of 10A with Suitable Pass
Transistors
• Input and Output Short-Circuit Protection
• Load and Line Regulation ••••••••••••••••••• 0.03%
• Direct Replacement for 723 and 723C Industry Types
• Adjustable Output Voltage ••••••••••••••• 2V to 37V

The CA723 and CA723C are silicon monolithic Integrated circuits designed for service as voltage regulators at output voltages ranging from 2V to 37V at currents up to 150mA.

Applications
•
•
•
•
•

The CA723 and CA723C may be used with positive and negative power supplies in a wide variety of series. shunt. switching.
and floating regulator applications. They can provide regulation
at load currents greater than 150mA and In excess of lOA with
the use of suitable n-p-n or p-n-p extemal pass transistors.

Series and Shunt Voltage Regulator
Floating Regulator
Switching Voltage Regulator
High-Current Voltage Regulator
Temperature Controller

The CA723 and CA723C are supplied In the 10 lead TO-100
metal can(T suffix). and the 14 lead dual-In-line plastic package
(E suffix). and are direct replacements for Industry types LM723.
LM723C In packages with similar terminal arrangements.

Ordering Information
PART

TEMPERATURE

CA723E

-55°C to +125°C

CA723T

-55°C to +125°C

Each type Includes a temperature-compensated reference
amplifier. an error amplifier. a power series pass transistor. and
a current-limiting circuit. They also provide Independently accessible inputs for adjustable current limiting and remote shutdown
and. in addition. feature low standby current drain. low temperature drift. and high ripple rejection.

PACKAGE
14Lead Plastic DIP
10 Pin Metal Can

CA723CE

OOC to +700 C

14 Lead Plastic DI P

CA723CT

OOC to +7000

10 Pin Metal Can

Pinouts

Functional Block Diagram
CA723 (PDIP)
TOP VIEW

CURRENT
UMIT

CU~~~~

INJ~¥

12
4

;t-p~~REG
Vc

-

NON·lNV
INPUT

Vo REGULATED
OUTPUT

V-

CA723C (CAN)
TOP VIEW

CURRENT

UMITER

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-3

File Number

788.3

Specifications CA723, CA723C
Absolute Maximum Ratings

Operating Conditions

DC Supply Voltage •••••••••••••••••••••••.•••••••• ~ •• 40V
(Between v+ and v- Tennlnals)
Pulse Voltage for SOms
Pulse Width (Between V+ and V- Terminals) ••••••••••••• SOV
Differentiallnput-Output Voltage •••••..••••••••.•••••••• 40V
Differential Input Voltage
Between Inverting and Noninvertlng Inputs •..••..••••••••• ±5V
Between Nonlnverting Input and V- ••••.•••••••••••••••• BV
Current From Zener Diode Terminal (Vzl ....•...........• 25mA

Thermal Resistance
Plastic DIP Package •••••.•••••••.••
MetalCen ••••••••••••••••••••••••
650C1W
Device DIssIpation
CA723T, CA723CT, Up to T" = +250 C .•••••••••..•••• 900mW
CA723E:, CA723CE, Up to T" = +2500 •••••••••••••• l000mW
CA723T, CA723CT, Above T" = +25°C •••.•••••.••• 7.4mWf'C
CA723E, CA723CE, Above T" = +25°C •••••.•••..• B.3mWf'C
Ambient Temperature Range
Operating Temperature Range •••••.•••••••• -55°C to +125°C
Storage Temperature Range •••••••••••••••• -65°C to +lSOoo
Lead Temperature, During Soldering •.•••••••.•••••.•• +265°C
At a distance 1/16" ± 1132" (l.59mm ±0.79mm) from case for lOs

max
CAurlON: Stress/JS abo... those Hsted in "Absolute Maximum RaUngs" may cause permanent damage to the davlee. This Is a strees only raUng and operaUon
of the device at these or any olhiJr conditions abo... those indicated In the operaUonal sections of this specllicaUon Is not Implied.

DC Electrical Specifications T" =+2500, V+ =Vc =VI =12V, V- = 0, Vo = 5V, IL = lmA, CI =l00pF, CREF = 0, Rscp = 0,
Unless Otherwise Specified. Divider Impedance RI R:! + RI + R:! at noninverting input, Tenninal 5 =
10kO. (Figure 20)
CA723

CA723C
MIN

TYP

3.5

-

2.3

4

mA

9.5

-

40

V

37

2

V

38

3

-

37

3

-

40

38

V

6.95

7.15

7.35

6.B

7.15

7.5

V

VI = 12V to 40V

-

0.02

0.2

-

0.1

0.5

%Vo

VI = 12V to 15V

-

0.01

0.1

0.1

%Vo

0.3

-

0.01

-

-

-

%Vo

VI = 12V to 15V,
T" = OOC to +7000

-

-

-

-

-

0.3

%Vo

IL = lmA to SOmA

-

0.03

0.15

0.2

%Vo

0.6

-

0.03

-

-

-

%Vo

IL = 1mA to SOmA,
T" = OOC to +700c

-

-

-

-

-

0.6

%Vo

Outpul-Voltage Temperature Coefficlenl,AVo

T" = -5500 to +125°C

-

0.002

0.015

T" = OoC 10 +7ooC

-

-

-

Ripple Rejection (Note 2)

f = 50Hz 1010kHz

-

74

-

PARAMETERS

TEST CONDITION

MIN

TYP

MAX

-

2.3

9.5

MAX IUNITS

DC CHARACTERISnCS
Quiescent Regulator Current, 10

IL =0, VI = 30V

Input Voltage Range, VI
OUtput Voltage Range, Vo

2

Differentiallnput-output Voltage, VI - Vo
Reference Voltage, VREF
Une Regulation (Note 1)

VI = 12V to 15V,
T" = -5500 to +125°C

Load Regulation (Note 1)

IL = lmA to SOmA,
T" = -5500 to +125OC

f = 50Hz to 10kHz,
CREF = 51lF

-

86

Short Circuit Umiting Current, ILiM

Rscp = 100, Vo = 0

Equivalent Noise RMS Output Voltage,
VN (Note 2)

BW = 100Hz to 10kHz,
CREF = 0

-

-20

BW = 100Hz to 10kHz,

-

2.5

-.

-

.

-

65

-

-

-

-

%f'C

0.003

0.015

%f'C

74

-

dB

86

-

65
20

-

-

2.5

-

dB

mA
IlV
IlV

NOTES:
1. Une and load regulation specificalions are given for condition of a constant chip temperature. For high dissipation condition, temperature
drifts must be separately taken into account.
2. For CREF (See Rgure 20)

7-4

CA723, CA723C

UNREGULATED
INPUT

D1
6.2V
Vo

Vz
FREQUENCY
COMPENSATION
CURRENT
UMIT
CURRENT
SENSE
NON-INVERTING VINPUT

VREF

INVERTING
INPUT

FIGURE 1. EQUIVALENT SCHEMATIC DIAGRAM OF THE CA723 AND CA723C

Typical Performance Curves (CA723)

r--

r
\1 AMEM~NT T!MPE~ATUR~

MAX JUNCTION TEMP (TJ) • +1 SO"c
THERMAL RESISTANCE • 150oC/W
QUIESCENT DISSIPATION (PQ) .60mW
(NO HEAT SINK)

(TAl

-

~ +2SO~

OUTPUT VOLTAGE ~o) = SV
INPUT VOLTAGE (VI .. 12V
SHORT CIRCUIT PROTECTION
RESISTANCE (RSCp) " 0

0.06

~

z

0

~

5

-

......

::I -0.05

CI

\
o

"-

" '"

..........

C
C

-

-0.15

+12SOC

~ -0.05

~
~

~~

o

-ss°C

z~

i

~:;.? ........
/~ ...........

~

100

a::
C

9

I

I

AMBIENT TEMPERATURE (TAl = -ss°C

~

-0.1

I

\'\ ~

1
\ I\,'\. I

w

0.2

\

~+25oC

\

-0.3

-0.2

-0.25

40
60
80
OUTPUT CURRENT (mA)

I

0

g

/'

+125oC

g

20

OUTPUT VOLTAGE ~o) .. SV
INPUT VOLTAGE (V .. 12V
SHORT CIRCUIT PR TECTION
RESISTANCE (Rscp)" 0

0.1

AMBIENT TEMP (TAl" +250C /

~ -0.15

N2SOC

FIGURE 3. LOAD REGULATION WITHOUT CURRENT LIMITING

---- -

...... ~

-0.1

~
~50C

-0.2
40

OUTPUT VOLTAGE ~o) .. 5V
INPUT VOLTAGE (VI .. 12V
SHORT CIRCUIT PROTECTION
RESISTANCE (Rscp) • 100

z

::I

-0.1

g

FIGURE 2. MAX LOAD CURRENT va DIFFERENTIAL INPUTOUTPUT VOLTAGE

o

"

t',

a::

10
20
30
DlFFERENllAL INPUT - OUTPUT VOLTAGE (V)

o

~ :--

w

o

0.05

-

I
AMBIENT TEMPERATURE
"'"'- (TAl = +2SOC

+125°C \
-0.4

o

5

10
15
20
OUTPUT CURRENT (mA)

25

30

FIGURE 4. LOAD REGULATION WITH CURRENT LIMITING

II \
o

20

40

60
80
100
OUTPUT CURRENT (mA)

FIGURE 5. LOAD REGULATION WITH CURRENT LIMITING

7-5

CA723, CA723C
Typical Performance Curves (CA723)
1- -

~- ~- -

1.0

"' .-

~- ~- ai- ~-

(Continued)

> llc:

I

-:i:4§~
_...-w·

OUTPUT VOlTAGE (Vo). REFERENCE
VOLTAGE (VREF)
LOAD CIRCUIT (ILl - 0

r

~!S"A:

w~!frl
~~t::U;

!:;c:)u

ol-UZ

> .... II:C

!;~g~

I
I
I
I
I
AMBIENT TEMPERATURE (TAl" -ss"c

ca. .... O:CI)
!;:)ow
"':1:11:
Oii!OCII

./

I-

!z

0.2

~ ~'+

u-

o
o

40

20

60

t:::::

~
~

a

80

100

o

--

+25°C

+l25°C

40

20
30
INPUT VOLTAGE M

10

OUTPUT CURRENT (mA)

FIGURE 7. QUIESCENT CURRENT vslNPUT VOLTAGE

FIGURE 6. CURRENT LIMITING CHARACTERISTICS

.



OUTPUT VOLTAGE (Vo)oo REFERENCE
VOLTAGE (VREF)

U»i==~

_INO·
..... w-

1.0

~15~

~

~

!:i
0

Ol-C)":

w
a: 4
a:

I::>
I- 0.4
::>
0

5g~!Il

i3

::>oa:
::>"':z:

~

O~UI

!3

8

0.2

o

10

\

\

2

~

:::::;;-

DoC

-

I--

+70oCI - -

o"c

+7o"C
0

I

AMBIENT TEMPERATURE (TAl"' +25°C

~ 3

~I-a:w

...

I

I I I I II

~

>..10: ....

0.6

>

.§.5

~~!::~
!:i..:::)z

w 0.8

(t)oo 0 I

LOA, CURjENT

C

w~g:e.

20
40
60
OUTPUT CURRENT (mA)

80

o

100

FIGURE 12. CURRENT LIMITING CHARACTERISTICS

o

10

20
INPUT VOLTAGE

30

40

M

FIGURE 13. QUIESCENT CURRENT vslNPUT VOLTAGE

Typical Performance Curves (CA723 and CA723C)
INPUT VOLTAGE (VI) .12V
OUTPUT VOLTAGE (Vo)"' 5V
LOAD CURRENT (Ill .1 TO SOmA
AMBIENT TEMPERATURE (TAl- +25oC
SHORT CIRCUIT PROTECTION
RESISTANCE (RSCp)" 0

0.2

~

~ 0.1

~
::>

0

w
a:
~ ·0.1

--

r- Ir- Ir- Ir- I-

OUTPUT VOLTAGE (Vo) "' 5V
LOAD CURRENT (Ill .1 mA
AMBIENT TEMPERATURE (TAl" +250 C
0.3
DIFFERENTIAL INPUT VOLTAGE ( 0.1
CI
w
a:
w
0

z

i'"

:::J
-D.1

-D.3

5

-6

15

25

35

-D.2

45

-6

5
15
25
35
45
DIFFERENTIAL INPUT· OUTPUT VOLTAGE (V)

DIFFERENTIAL INPUT· OUTPUT VOLTAGE (V)

FIGURE 14. LOAD REGULATION VB DIFFERENTIAL INPUT·
OUTPUT VOLTAGE

INPUT VOLTAGE (v~ _12Y, OUTPUT VOLTAGE (vol- 5'1
LOAD CURRENT (I,) _ 40mA
AMBIENT TEMPERA1\JRE (TAl _ ••SOC
SHORT ClReutT PROTECTION RESISTANCE IRscP). a

II

LOAD CURRENT (Ill

1\
In

-

-

~
10

0.8

.§.

C

g 0.7

~

UI
Z

w

~

I
"-

CI

z

·10 C
C

~ 0.5

g

..I

Iz
w

·20

:l!

0.4

::>
C)

-30

10

....... It
........

/

UI 0.6

~

SHORT CIRCUIT UMITING
CURRENT WITH Rscp • 50

WI~H R'

I

CURRENT UMITING
r',NSE V tTAGE

~ 1000..

W

>
w

OUTPUT VOLTAGE (Vo)

i\

I I I I I

~

0

I

,

FIGURE 15. LINE REGULATION vs DIFFERENTIAL INPUT·
OUTPUT VOLTAGE

~
~ i"""o

Jt-oi.I

~ 1c:a

liP,

,

1"-0

r-....

r- ....

0.3

oS

5

15

25
TIME (1"1)

35

45

-60
0
50
100
150
JUNCTION TEMPERATURE <"C)

FIGURE 16. LINE TRANSIENT RESPONSE

FIGURE 17. CURRENT LIMITING CHARACTERISTIC vs JUNCTION TEMPERATURE

7·7

CA723, CA723C
Typical Performance Curves (CA723 and CA723C)
10

C

•

.§.

~
~

4
INPUT VOLTAGE "II

II

4

>
w
Q
w

2

II

2

~

0

1/

0

>

"f I I I r-

-2

0

...

-I"""

..

=-NJ==~RE:'iANCE
16

26
nME lILa)

3S

ClI

ill

6

!;

-2

r46

I INPUT VOLTAGE (VII.12V

OUTPUT VOLTAGE (Vo). 5V
4 LOAD CURRENT (Ill- SOmA
2 AMBIENT TEMPERATURE ~. +25°C
SHORT CIRCUIT PROTEC11
RESISTANCE (Rscp) • 0

~

~ "46

w
Q
w

~

2

V
11'1'

LOAD CAPACITANCE (CLl- 0

1/

V

0.1

§

>

!;

...... ... !:...

1RscP)·o
6

i

~

~

~UTrOLrA~E (Yo)

INPUT VOLTAGE (V~. 12V
OUTPUT VOLTAGE (Vo). SV
LOAD CURRENT (ILl. 1m"

!;

S

0

.....

E

(Continued)

I
4
2

.

0.01

468
2 468
2 4.8
2
1k
100k
10k
FREQUENCY (Hz)

2
100

FIGURE 18. LOAD TRANSIENT RESPONSE

468
1M

FIGURE 19. OUTPUT IMPEDANCE va FREQUENCY

Typical Application Circuits

v,
VAEF

v+

Vc

I

I

v,
VAEF

~

v+

Vc

I

I

Vo

~

1

riRscp
CURRENT
UMIT

R1
NON
INV
INPUT
CREFF

=

REGULATED
OUTPUT

R3

~~:~iNTR3

>-

vl COMP

..~ =

R1

C1

F

_

Circuli Performance Data:
Regulated OUtput Voltage 5V
Une Regulation (toV,= 3V) 0.5mV
Load Regulation (AIL SOmA) 1.5mV

JINV.
INPUT

COMP

R2

'=.,E:'

Circuit Performance Data:
Une Regulation (toV, = 3V) t.5mV
Load Regulation (AIL SOmA) 4.5mV

=

=

Note: R3

REGULATED
OUTPUT15V

CURRENT
SENSE

vl- 1 "t.

NO':-INV
INPUT

INV. r+ C1
INPUT
100pF

Rscp

CURRENT
UMIT

Note: R3 =

= R1
.B1..B2.. For Minimum Temperature Drift
+R2
.

R3

FIGURE 20. LOW VOLTAGE REGULATOR CIRCUIT
(VO .. 2V TO 7V)

.B1..B2.

For Minimum Temperature Drift

Ma~~: &mlnated For Minimum Component Count

FIGURE 21. HIGH VOLTAGE REGULATOR CIRCUIT
(VO • 7V TO 37V}

7-8

CA723, CA723C
Typical Application Circuits

(Continued)

Vc

V+t-~f------,

Vo

VREF

CURRENT
UMiT

NON
INV
INPUT

REGULATED
OUTPUT·1SV

~~----~~----+-~-+

Circuit Performance Data:
Line Regulation (AV1 =3V) 1mV
Load Regulation (AIL = 100mA) 2mV
Note: For Applications Employing the TO·S Style Package
and Where Vz Is Required, An External; 6.2V Zener Diode
Should be Connected in Series with Vo (Terminal 6).

Circuit Performance Data:
Line Regulation (AV1 = 3V) 1.SmV
Load Regulation (AIL = lA) lSmV

FIGURE 23. POSITIVE VOLTAGE REGULATOR CIRCUIT (WITH
EXTERNAL n-p-n PASS TRANSISTOR)

FIGURE 22. NEGATIVE VOLTAGE REGULATOR CIRCUIT

R3

600

2NSJ156

HI-Q~-----"'~OR

r-.....iVc::.--o~VoL_~
R1

R2

CURRENT
UMIT

REGULATED

~-""'~_~~-=~~~O~U~TPUTSV
Rscp
1-_-0-""::;';';::;1 300

2N6108

Rscp

NON~---rl]~~-4--~~:REGULATED
I~~~T

V.

=

CURRENT
UMIT

R1

COMP
..T.. C1
0.001I'F

R4

5.6ka

NONL,...-..r=-:;;.......----....J

R2

OUTPUT SV

INV

INPUT

=

Circuit Performance Data:
Line Regulation (tN = 3V) O.SmV
Load Regulation (AIL = 10mA) lmV
Short Circuit Current 20mA

Circuit Performance Data:
Line Regulation (AV1= 3V) O.SmV
Load Regulation (AIL = 1A) SmV
FIGURE 24. POSITIVE VOLTRAGE REGULATOR CIRCUIT
(WITH EXTERNAL p-n-p PAS TRANSISTOR)

FIGURE 25. FOLDBACK CURRENT UMITING CIRCUIT

7-9

CA723, CA723C
Typical Application Circuits

(Continued)

R5
10110

RS
3.9110
V+

1

VC

-

~
Vz

VREF

VI

VI_'SV

n

R2

".I.2N3442

R4
3110

Rl

'"l'fJv
A~·SK3062

NON
INV.
~UT >--

R3
3110

R2
I

""-=-

~~sCP
10

8~~~ENT

D1

12V
SK3062

CURRENT
SENSE
V-

~.~OOl"F
INPUT

Rl

COMP

REGULATED
OUTPUT-l00V

REGULATED
OUTPUT~V

Circuit Performance Data:
Une Regulation (IN = 20V) 15mV
Load Regulation (1l.1l = 50mA) 20mV
NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode should
be connected in series with Vo (terminal 6)

Circuit Performance Data:
Une Regulation (Il.VI = 20V) 30mV
Load Regulation (1l.1 l =100mA) 20mV
NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode should
be connected in series with Vo (terminal 6)

FIGURE 26. POSITIVE FLOATING REGULATOR CIRCUIT

FIGURE 27. NEGATIVE FLOATING REGULATOR CIRCUIT

VI
NOTE 2

VREF

V+

VREF

Vc

Rl

Vo

R3
Vz loon

REGULATED
OUTPUTSV
C

Rl

CURRENT SENSE

L,.-...,..t--~N:O:;N:::IN:V::-.-"'"

R2

R2
2110

=

INV
INPUT

V-

COMP INPUT

.:f.

CCSL
LOGIC
INPUT

Circuit Performance Data: .
Line Regulation (Il.VI = 3V) O.5mV
Load Regulation (1l.1 l = 50mA) 1.5mV
Short Circuit Current 20mA
NOTE: 1. A current limiting transistor may be used for shutdown if
current limiting is not required.
2. Add a diode if Vo > 10V.

C1
O.OOS"F

Circuit Performance Data:
Line Regulation (Il.VI = 10V) O.5mV

Load Regulation

(~IL

= 100mA) 1.5mV

NOTE: For applications employing the TQ.5 Style Package and
where Vz is required. an external 6.2V zener diode
should be connected in series with Vo (terminal 6).

FIGURE 28. REMOTE SHUTDOWN REGULATOR CIRCUIT WITH
CURRENT LIMITING

7-10

FIGURE 29. SHUNT REGULATOR CIRCUIT

CA1523
Voltage Regulator Control Circuit
for Variable Switching Regulator

April 1994

Features

Description

• Operates up to 200kHz

The CA1523 monolithic silicon integrated circuit is a variable
interval pulse regulator designed to provide the control circuitry for use in switching regulator circuits. It operates from
11Vto15V.

• Pins ESO Protected
• Remote ON/OFF
• Slow Start with Reset
• Overcurrent Sensing
• Lower Peak Currents than PWM Regulator
• Less Prone to Magnetic Saturation

Ordering Information
PART
NUMBER
CA1523E

TEMPERATURE
RANGE
OOC to +70oC

PACKAGE
14 Lead Plastic DIP

The regulator provides a single output drive capable of
300mA sourcel200mA sink. The maximum operating frequency is better than 200kHz. An attractive feature of the
CA 1523 is that the timing capacitor charge and discharge
current is set up externally via a single resistor. The ratio of
charge to discharge current is internally set at a maximum of
2 to 1 allowing simultaneous change in output pulse width
with increased frequency at higher load. The pulse width
variation at higher frequencies effectively compensates for
the losses in magnetics and thereby increases the power
supply efficiency at higher load end by as much as 20
percent.

Pinout
CA1523 (PDIP)
TOP VIEW
ERROR

1

CURRENT SENSE

2

RISE TIME

4

11 OVER CURRENT

OUTPUTGND

5

10 SLOW START
8 LOGIC OUTPUT

CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7·11

File Number

1785.2

Specifications CA 1523
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage •••••••••.•..••..••••.•••.•..••.••• 15V
Supply Current
16(MAX)' .•.•.••••.•.••..••••••...•...•••••.•..•..•..• ±SOmA
16(MAX)' 1l1S,l800pF Load •••••••••••••••••••. +300, -200mA
Device Dissipation
Up to TA = 7ff'C ••.•••.•••••.••••••••••••....••• 530mW
Above TA = 70°C ••....•.•••••••. Derate Unearly at 6.7mWf'C

Thermal Resistance
8JA
Plastic DIP Package. • • • • • • • • • • • • • • . • • . • . • . .
12ff'Cm
Device Dissipation
Up to TA = 7ff'C .•••••••••••••••••••••••••••••••• 665mW
Ambient Temperature Range
Operating .••••••••.•••.••••.•••••••.•.••.. ff'C to +70oC
Storage ...•••.•...•.••••••.•••••••••••• -55°C to +150°C
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±O.79mm)
from case for lOs Max •.••••.•.••••••••••.•....... +265°C

CAUTION: StressllS above those listed In 'Absolute Maximum RaUngs' mey cause permanent damage to the device. This is a stress only ra6ng and operation
of the device at these or any other conditions above those indicated in the opera60nal sections of this specifica60n is not Implied.

Electrical Specifications TA = +25°C, Refer to condition shown In test circuit; V7 = 13V, VI = 5.9V Unless Otherwise Specified
PARAMETERS

PIN

TEST CONDITIONS

MIN

TVP

MAX

UNITS

9.5

13

-

V

20

27

34

rnA

7.8

8.4

8.9

V

POWER SUPPLY, Vcc (PIN 7)
Supply Voltage

7

Supply Current

7

Zener Voltage

13

Vee = +13V

OUTPUT PULSE (PIN 6)
Maximum Pulse Width

6

Measured at 6V Threshold Level

5.5

6.5

7.5

I1S

Minimum Pulse Width

6

Measured at 6V Threshold Level

2

3

4

I1S

Output High Voltage

6

16=OmA, V4 =OV

11.1

12

12.6

V

Output Low Voltage

6

16 = SOmA, V12 = OV

0.6

1

1.3

V

Rise Time

6

Measured at 1.8V and 10V Threshold Levels

250

600

1250

ns

Fall Time

6

Measured at 1.8V and 10V Threshold Levels

50

200

350

ns

1

Adjust RT; Observe Pin 6 MInIMax
Frequency Range

5.9

6.8

7.5

V

Charge Current

14

Adjust RT, VI =7.5V; SetV14 =OV, Then VI4 =2.5V

190

220

250

I1A

Discharge Current

14

Adjust Rr = 5.9V; SetV14 = 5.5V, Then 5V

95

110

125

I1A

Slow Start Discharge Current

14

Maintain V14 = 5V, V10 = 5.5V
Set V10 = 5.5V, Measure 114 (HI)
Set V10 = 4V, Measure 114 (Lo)
Umits = 114 (Hi) - 114 (Lo)
1.5

20

30

40

/!AIV

Discharge Voltage

10

Pin 12 = 1kO to GND

1.7

2.4

3.2

V

Output Inhibit Vo!tag@

7

Increase V; Until V; ~ 2V

HI

M

R~

V

Overcurrent Trip Voltage

11

V12 = 5V; V10 = OV; Increase V11 Until Vi S 0.5V

1.1

1.25

1.4

V

ERROR VOLTAGE RANGE (PIN 1)
Error Voltage Reference

CHARGE CURRENT (PIN 14)

LOGIC TESTS

7-12

CA1523
Other Desirable Features
Other desirable features along with various circuit block
function explanations are listed below.
• The Oscillator is a sawtooth generator whose charge
(rise) cycle determines the output pulse width and discharge which is continuously variable from very low to
maximum of ICHARGE'
• Charge ICHARGE
control

=10 -IDISCHARGE giving 2 to 1 pulse-width

• Discharge IDISCHARGE = approximately 0 to 1/2 10 to
frequency control.
• Pulse Shaping: Applied to the oscillator output via RS
Flip-Flop with parallel inhibit controlled by slow-start overcurrent sense, supply voltage monitor and ON/OFF functions.
• Pulse Rise Time: Modified to meet RFI requirements by
external slow-down capacitor.

• Slow Start with Reset: Externally programmed against
internal 3V reference. Reset is initiated upon Inhibit ensuring soft start at power up and restart.
• Over Current Sense: Internal stable thresholds of 1.2V.
• Supply Voltage Monitors: Locks out the drive until
VSUPPLY has reached 8V-9V.
• ON/OFF: Activates regulator independent of raw DC.
• Error Amplifier: Compares output against a stable 6.8V
internal reference and controls the discharge current sink
on the timing capacitor.
• Band-Gap: Reference voltage (internal) provides temperature compensated 1.2V and 6.8V references.
• Separate GNO: The power GND is separated from circuit
ground for improved noise.
• ESO Protection: Pins are protected against ESD.

Block Diagram
CURRENT
SENSE

vee

ZENER

5V
REF.

~_--------t 4

RISE
TIME

··
···
·:

~
3

GND

OVER
CURRENT

(CONTROL
•
CIRCUIT
:
GND)
; "="

···
·

6. ____ -

_ _ _ _ _ ....

.. _ _ _ _ _ _ _ _ ..

10

SLOW

12

9

ON/OFF

LOGIC
OUT

START

7-13

CA1523

Vee

Rr

·:
·::
: (CONTRO

: CIRCUIT

~
:

:---_ ..._-- ...
220

~VCc

OFF~V

FIGURE 1. TEST CIRCUIT FOR TH ECA1523

----:7.1=----4-

1

CA1523

+150V
RECTIFIED AC UNE
INPUT

+150
TYP. INPUT USA

· -------------_-._-----".
TRANSFORMER

,......

TYPICAL
RECT.
OUTPUT
VOl +130V

~---+O V04 ·24V

30k
11k

••

.~

:~

10

ON/OFF

1.5k

----- ,

v~t:'lAGE.
:
:

NC

NC

NC

8

II

13

:!

,----+--00 V02

+16V

·

L---+--00 V03

+24V

....

.W
'W

7

CA1523

•
~

,-...J
.,-......J

:

0.15

!- ---........ -......... ...-

3W

OPT~OUPLER

FIGURE 2. TYPICAL APPLICATION CIRCUIT FOR THE CA1523

Vee

8.3K

UK

II

LOGIC OUT

FIGURE 3. TIMING CIRCUIT FOR THE CA1523

7-15

CA 1524, CA2524
CA3524
Regulating Pulse Width Modulator

April 1994

Features

Description

• Complete PWM Power Control Circuitry

The CA1524, CA2524, and CA3524 are silicon monolithic
integrated circuits designed to provide all the control circuitry
for use in a broad range of switching regulator circuits.

• Separate outputs for Single-Ended or Push·Pull
Operation
• LIne and Load Regulation •••••.••••••.•• O.2%{Typ)
• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range
• Standby Current of Less Than 10mA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.511S to 5JLS
• Low VCE(aal) Over the Temperature Range

Applications

The CA1524, CA2524, and CA3524 have all the features of
the industry types SG1524, SG2524, and SG3524,
respectively. A block diagram of the CA 1524 series is shown
in Figure 1. The circuit includes a zener voltage reference,
transconductance error amplifier, precision R-C oscillator,
pulse-width modulator, pulse-steering flip-flop, dual alternatIng output switches, and current-limiting and shutdown
circuitry. This device can be used for switching regulators of
either polarity, transformer-coupled dc-de converter,
transformerless voltage doublers, dc-ac power inverters,
highly efficient variable power supplies, and polarity
converter, as well as other power-control applications.

Ordering Information

• Positive and Negative Regulated Supplies

PART
NUMBER

• Dual-Output Regulators

TEMPERATURE
RANGE

PACKAGE

• Flyback Converters

CAl524E

-55°C to +125°C

16 Lead Plastic DIP

• DC-DC Transformer-Coupled Regulating Converters

CA1524F

-55°C to +125°C

16 Lead CerOIP

• Single-Ended DC-DC Converters

CA2524E

Ooc to+70oC

16 Lead Plastic 01 P

• Variable Power Supplies

CA2524F

OOC to +70oC

16 Lead CerOIP

CA3524E

OOC to+70oC

16 Lead Plastic DIP

CA3524F

OOC to +700C

16 Lead CerOIP

Pinout
CAl524, CA2524, CA3524
(PDIP, CERDIP)
TOP VIEW
INY.INPUT

VAEF

1

NON-

V+

INV.INPUT
OSCOUT

3

EMITTERS

(+)C.L

COLLECTORS

SENSE

(-)C.L

5

COLLECTOR A

SENSE

EMmER A

r_
G~~

7
7
~L..

5].1: :~~=:noN

_ _ _ _- - '

AND COMPARATOR

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-16

File Number

1239.3

CA 1524, CA2524, CA3524
Functional Block Diagram
.SV TO ALL
INTERNAL CIRCUITS

VAEF

3r-------------------.---t
OSCOUT

• SENSE
• SENSE

1k!.!
10

L -__________________________-{

SHUTDOWN

8

COMPENSATION AND COMPARATOR
10k!.!

G)

GND

Test Circuit
8.40V

r-________________________________________--,1W
2k!.!
OUT A
OUT a

CA1524

0.1""
1k!.l
2k!.!

7·17

Specifications CA 1524, CA2524, CA3524
Absolute Maximum Ratings

Thermal Information

Input Voltage (Between VIN and GND Terminals) ••....••.•.. 40V
Operating Voltage Range (VIN to GND) ••.....•...•...• 8 to 40V
Output Current Each Output:
(Terminal 11, 12 or 13, 14) •...•.........•.•••••.••• 100mA
Output Current (Reference Regulator) ...••••...•••...... 50mA
Oscillator Charging Current •..•....•.•••••..••••.•••••• 5mA

Thermal Resistance
9JA
Plastic DIP Package ...•••.•...•..•.•••.•... 1000 CIW
Device Dissipation
Up to TA = +25°C ••••••••...••••.••••••.•.••...••• 1.25W
Above TA = +25°C •...•...•...... Derate Llnea~y at 10mWI"C
Operating Temperature Range •.•••••••••.•..• -55°C to +125°C
Storage Temperature Range ••...•.••.•••...•• -65°C to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max •.....••.....•...•.•..•...•• +265°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· mey cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the operational sections of this specificaUon is not implied.

Electrical Specifications TA = -55°C to +125°C lor CA1524, oOC to +700C lor the CA2524 and CA3524; V+ = 20V and
I = 20kHz, Unless Otherwise Stated.
CA1524, CA2524
TEST CONDITIONS

PARAMETER

I

CA3524

TYP

MAX

MIN

4.8

5

5.2

-

10

20

20

50

66

MIN

TYP

MAX

UNITS

4.6

5

5.4

V

-

10

30

mV

20

50

mV

66

db

100

-

rnA

0.3

1

%

-

mVlkhr

-

kHz

REFERENCE SECTION
Output Voltage
Une Regulation

V+ = 8 to 40V

Load Regulation

'l = 0 to 20rnA

-

100

-

-

0.3

1

TA =2SoC

-

20

-

-

20

Maximum Frequency

CT = 0.00111F, RT = 2Kn

300

-

-

300

S

-

-

1

-

S

2

-

3.S

-

-

Ripple Rejection

f = 120Hz, TA = 25°C

Short Circuit Current Limit

VREF=O, TA=2SoC

Temperature Stability

Over Operating TemperabJre
Range

Long Term Stability
OSCILLATOR SECTION

Initial Accuracy

At and CT Constant

-

Voltage Stability

V+ = 8 to 40V, TA = 2SoC

-

Temperature Stability

Over Operating TemperabJre
Range

-

Output Amplitude

Terminal 3, TA = 2SoC

Output Pulse Width (Pin 3)

CT = 0.0111F, TA = 2SoC

Ramp Voltage Low (Note 1)

Pin 7

Ramp Voltage High (Note 1)

Pin 7

Capacitor Charging Current Range

Pin 7 (S-2 VsE)/RT

0.03

Timing Resistance Range

Pin 6

1.8

Charging Capacitor Range

Pin7

0.001

Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)

Pin 3

100

O.S
0.6
3.S

-

%

-

1

%

2

%

3.S

-

V

O.S

-

I1S

0.6

-

V

3.S

-

V

0.03

-

2

mA

120

1.8

kn

0.001

-

120

0.1

0.1

I1F

1000

100

-

1000

pF

2

ERROR AMPliFIER SECTION

-

O.S

S

-

2

10

mV

1

10

-

1

10

I1A

Open Loop Voltage Gain

72

80

60

80

Common Mode Voltage

TA = 25°C

1.8

-

3.4

1.8

Common Mode Rejection RatiO

TA =2SoC

-

Ay = OdB, TA = 2SoC

-

70

Small Signal Bandwidth

3

-

-

Input Offset Voltage

VCM=2.SV

Input Bias Current

VCM=2.SV

7-18

dB

-

3.4

V

70

-

MHz

3

dB

Specifications CA 1524, CA2524, CA3524
Electrical Specifications

TA = -550 C to +125"C lor CA1524, O"C to +70"C lor the CA2524 and CA3524; V+ = 20V and
I = 20kHz, Unless Otherwise Stated. (Continued)
CA1524. CA2524
MAX

MIN

0.5

·

3.8

2SO

External Sink

·
·

200

·
·

Duty Cycle

% Each Output On

0

·

45

Input Threshold

Zero Duty Cycle

·

·

Max. Duty Cycle

·
·

1

Input Threshold

3.5

·

·

1

·
·

·

190

200

210

Sense Voltage T.C.

·

0.2

Common Mode Yoltage

-1

Rolloff Pole of R51 C3 + Q64

·

Output Voltage

TEST CONDITIONS
TA = 25°C

Amplifier Pole
Pin 9 Shutdown Current

MIN

CA3524

TYP

PARAMETER

TYP

MAX

UNrrS

0.5

·

3.8

V

·
·

2SO

Hz

200

·
·

IIA

0

·

45

%

1

·

V

3.5

·

V

1

·

IIA

180

200

220

mY

·

·

0.2

·

mVf'C

·

+1

-1

·

+1

Y

300

·

·

300

·

Hz

COMPARATOR SECTION

Input Bias Current
CURRENT LIMITING SECTION
Sense Yoltage lor 25% Output Duty
Cycle

Terminal 9 = 2Y with Error
Amplilier Set lor Max Out,
TA=25°C

OUTPUT SECTION (EACH OUTUT)

40

·

·

40

·

·

V

Collector Leakage Current

VcE =4OY

·

0.1

50

·

0.1

50

IIA

Saturation Voltage

V+ = 40V, Ic = SOmA

·

0.8

2

·

0.8

2

Y

Emitter Output Yoltage

Y+=20Y

17

18

·

17

18

·

V

Rise TIme

Rc = 2K.Q, TA = 25°C

·

0.2

·

lIS

Rc = 2K.Q, TA = 25°C

·

0.1

Total Standby Current: (Note 2) Is

Y+=40Y

·

4

·
·
·

0.2

Fall TIme

·
·

Coliector·Emitter Voltage

10

NOTES:

0.1

·

lIS

4

10

rnA

Hi9hl!W
LOW.!!!.
where t = OSC period in microseconds
;t;
t ;: RrCr with C r in microfarads and RT in ohms.
Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.

1. Ramp vonage at Pin 7

2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

7-19

CA 1524, CA2524, CA3524
Schematic Diagram
_--... -----..... ------------.-----... -... -----M---------------• _______ ... _______________ _

,,
,,,
,,,
,
,,,
,,
,,,
,,
,,
,,
,,,
,,,
,,,
,,
,
,,,
,,
,,,
,,
,
,,
:,,
,,,
,,
,,,
,,,
,
,,,
,
,,,
,
,,,

_... _--------------,
A

B

R13

RO
-------.
10K UK

6Q

f.

,,
;-------_.,

,
,,
,
,,,
,,
,,,
,,
,,,
,,
•,,,

,,,

01

,r---------,,,
,

,
,,,
PULSE
:,, STEERING
,, FUP-FLOP
,,,
,
,,,

c
o
E

, R9

:500
,

,

-------------------------------.------, r-

...--i,_-•••-.-!.-.-_-.-..-.-.-.-.-.-.-.-.-.'..
:',:,.,:,.,:,.:-::.-:.-:.-:.':i.r-.1---···~·~·:··:·~·~·:··:·~·~·:·~··~·~·:·:··~·~·~·;·02S~C~·!s·~Ec~nn·OQ·N~-~·~J~::~::::~::::~::=f~~~~~~~~i::::::

F
G

r

NON-INV.
INPUT

t-+---J
7
Cr

r-;,f---+-.....-4

,,:
,,
,,
,,,
,,
,,
,,
,
,,

R3g
1K

R47
1K

R40

560

,

' .... ____ • ___ .. ___ .. __ ..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • __ - - - - - - - - - _____ .. 4

7-20

R48
2K

K

~----------------~

L

CA 1524, CA2524, CA3524
Schematic Diagram (Continued)
,....................................... .. .................... -- -- ............... ----_ ........................................................:
."

."

A

OUTPUTB

OUTPUT A

~

:

,,,
,,
,,
,,,

B

,

RU

R34

R31

500

SOO

....-------+-t-..., -{14 EMIT B

11}--+:----+-~~--------------~

EMiTA

,,
,,

:,--------------_ ........ _------------ ..........
--

·~ I

C

..

NOR

F

G

•___________________________;

,,,
,
,,

=
---------

'

... ---- .. ----------..,----- .. -~
-----------------------.
NOR

·

0
E

R38

4.70

4.70

::~K

:
::
,
:

R28

:

8.7K

,,:
,,
:,

t ___________. ____ ...... ____ .. ___ .. ____l'

~ ::::::::::::::::::::::::~--_.----~;r:-:--:-:-:-~------------~~~:::~~~~--1

:

i:,

:,,

10

J

··
,,:1
,,

,,,
,
,,•

,
,,:I
K
L

,

,.-

I

R411

1K

:,
:,
:,,
:

:
:
:
:

··:
:
:,
··

,~

063 :

R50

10K

~---------~

:,
,

CURRENT
UMIT
SECTION

,,,

.:

I
I-

._-------------------------------_!
S

(-j C.L.

(+j C.L.

SENSE

SENSE

7-21

CA 1524, CA2524, CA3524

Circuit Description

Oscillator Section

Voltage Reference Section

Transistors 042, 043 and 044, in conjunction with an
external resistor AT, establishes a constant charging current
into an external capacitor CT to provide a linear ramp voltage
at terminal 7. The ramp voltage has a value that ranges from
O.SV to 3.SV and is used as the reference for the comparator
in the device. The charging current is equal to (S-2VBE)/AT or
approximately 3.6IRT and should be kept within the range of
30pA to 2mA by varying AT' The discharge time of CT determines the pulse width of the oscillator output pulse at terminal 3. This pulse has a practical range of O.S~s to S~s for a
capacitor range of 0.001 to 0.1 ~F. The pulse has two internal
uses: as a dead-time control of blanking pu lse to the output
stages to assure that both outputs cannot be on simultaneously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Figure 4. Pulse widths less than O.S~s may allow false triggering of one output by removing the blanking pulse prior to a
stable state in the flip-flop .

The CAIS24 series contains an internal series voltage regulator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
IS and is capable of supplying up to SOmA output current.
Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.

.1

5.02
w
~ 5.00
~
4.l1li

..

w

~

M!

~ i""'"

~

::... ~ FI": io-""

§!

~

v+-40Y.It.-OmA
v+.20V,~.omA
v+.40~ 1t.-2OmA
v +_8V.I•• omA
v+ • 2OY, ..... 20mA
v+.8V, IL _2OmA

_10-

~

4.96

~ 1,...0- io-""

100

f-

Io6Q

0040 -20 0

1

20 40 60 60 100 120 140

~

AMBIENT TEMPERATURE ("C)

FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE

4.11

~

4.7

'-'

4.5

~

4.3

w
w
"w

4.1

~

Z

a:

~

W

6

!j

5

~

4

~

II!~
~
w

a:

0.1

1.0

FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A
FUNCTION OF TIMING CAPACITOR VALUE

o

8

16

24 32

40

48

56 64

72

80

FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF REFERENCE OUTPUT CURRENT

8

0.01

TIMING CAPACITOR, C'r (j1F)

REFERENCE OUTPUT CURRENT (mA)

~ 7

0.001

V+_8V'

3.7

3.S

0.1
0.0001

II

3.11

a:

/
1.0

1.;1'

~~
L ~l
V+_20V
~~
~~

TA_+25oC
V+_20V

10

~

V+_40V

w

V+.8V-40V

I!:

5.1

~

TA·+25oC

l-~h~50~

I
II

3

2
1
I

I

O~I~__L-~~~~~~~__L-~

o

10

20

30

40

SUPPLY VOLTAGE, V+ (V)

FIGURE3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE

If a small value of CT must be used, the pulse width can be
further expanded by the addition of a shunt capacitor in the
order of l00pF but no greater than 1000pF. from terminal 3
to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-Kn resistor at
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
maximum duty cycle acceptable.
The oscillator period is determined by AT and CT, with an
approximate value of t = ATCT, where AT is in ohms, CT is in
~F, and t is in ~. Excess lead lengths, which produce stray
capacitances, should be avoided in connecting AT and CT to
their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency ihe same as ine osciiiator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-4S%
and the overall frequency is half that of the oscillator. Curves

7-22

CA 1524, CA2524, CA3524
of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAI524's, one must be designated as master, with RT
CT set for the correct period. Each of the remaining units
(slaves) must have a CT of 1/2 the value used in the master
and approximately a 1010 longer RTCT period than the master. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.
TA-+25°C
v+_ 'V-40V
CT - 0.001 "F1
CT" 0.005)}.

L

VI

CT - 0.OO2"Ft

I

V

V

VI'

Cr"O.02"F

V

j

CT" O.OS"F

Vll'
CT= O.01"F

irrr"

The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated
amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.
Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good starting point to determine the external poles is a 1000-pF
capacitor and a variable series 50-Kn potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200~ can pull this point to ground and shut off
both output drivers.
While feedback is normally applied around the entire regulator, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure B. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.

10
102
103
OSCILLATOR PERIOD, t (f'S)

FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION
OF RTAND CT

Error Amplifier Section
The error amplifier consists of a differential pair (056,057)
with an active load (061 and 062) forming a differential
transconductance amplifier. Since 061 is driven by a
constant· current source, 062, the output impedance ROUT,
terminal 9, is very high (= 5MQ).

l48

g

40 10-

The gain is:

~:

Av = gmR = Blc Rl2KT = 104 ,

~

where R=
Since RoUT is extremely high, the gain can be easily
reduced from a nominal 104 (BOdS) by the addition of an
external shunt resistor from terminal 9 to ground as shown in
Figure 6.
'0

""

RL=-

70

RL=3MO

60

RL=1Mn

<
I!I

50

RL=300j

I!I

40
0°

RL .1001<11

:!!.

z

w

~

g

r----..

,PEN

L~OP

~

102

103
104
FREQUENCY (Hz)

~

~

i.-":'"

--

P

~~
CT,,1000pF
RT'.5k

~

'osc = 20kHz

. / ./

o

...

". ,/

0.4 0.' 1.2 1.6 2 2.4 2.8 3.2 3.6
COMPARATOR VOLTAGE (V)

4

FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF
COMPARATOR VOLTAGE (AT TERMINAL 9).

E:

1.1

w

-"

lfPEN Loc;'f PHASE
10

o

~

CT_2700pF
RT-S.19k
'osc " 60kHz

~

GAIN

~
g

""" I"-

" ...........

10-

16

o ,

m-

TA- +2S0 C
v+_ 20V

;.J

1.0

J

~

~

5io.e
a:

./

::I

!c

~ 0.8

~

50

105

0.7

./

,..

V

~~~

0 25 ~ n 100n51~1n
AMBIENT TEMPERATURE rC)

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE
CHARACTERISTICS.

FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF AMBIENT TEMPERATURE.

7-23

CA 1524, CA2524, CA3524
Output Section
The CA1524 series outputs are two identical n-p-n
transistors with both collectors and emitters uncommitted.
Each output transistor. has antisaturation circuitry that
enables a fast transient response for the wide range· of
oscillator frequencies. Current limiting of the output section
is set at 100mA for each output and 100mA total if both
outputs are paralleled. Having both emitters and collectors
available provides the versatility to drive either n-p-n or p-n-p
external transistors. Curves of the output saturation voltage
as a function of temperature and output current are shown in
Figures 8 and 9, respectively. There are a number of output
configurations possible in the application of the CA1524 to
voltage regulator circuits which fall into three basic
classifications:

The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 11. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
VREF

SK

€

2.0

~
'-'
g

R1

~
~

VREF

o

R1 +R2

L-~'Iv--_

GND

~

R2

NEGATIVE
OUTPUT
VOLTAGES

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

V

.,/

0.5

~o

Jlli!L. .2.SKW

5K

",

~

tc

-t-----,
R1

1/

1.0

II)

V 2.SV (Rl + R2)
o
Rl

GND

SK

T",,+250C
v+_eVto40V

1.5

a:
::)

posmVE
OUTPUT
VOLTAGES

5K

1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits

w

R2

r---4Ivv--....

~

o

40
60
eo
OUTPUT CURRENT, IL (mA)

20

CA1524
REFERENCE
SECTION

100

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

V+CANNOT
EXCEED6V

Device Application Suggestions
For higher currents, the circuit of Figure 10 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed for operation from a fixed 5V
supply by connecting both terminals 15 and 16 to the input
voltage, which must not exceed 6V.

~-~~r-----------~

NOTE: V+ Should Be in the 5V Range
And Must Not Exceed 6V
FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE
REFERENCE REGULATION

To provide an expansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.

ILTOI"
DEPENDING
ON CHOICE

.V;+~1_0 _0

__________-+________

GND

-6-':~.J
J

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE
CURRENT CAPABIUTY

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITHOUT USING A CAPACITOR ON PIN 3 OR WHEN A
LOW VALUE OSCILLATOR CAPACITOR IS USED

7-24

CA1524, CA2524, CA3524
TABLE 1. INPUT vs. OUTPUT VOLTAGE. AND FEEDBACK
RESISTOR VALUES FOR IL ,", 40mA (FOR CAPACITOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)

RI

R2

- - -.....- I -....-JWI,.--..
RS

.----~4r-----.

-1... (VllI + ~)
RS

lac-

SENSE

+

IMAX.

"1 +""

~

WHERE

VllI- 2OOmV

FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED
TO REDUCE POWER DISSIPATION UNDER
SHORTED OUTPUT CONDITIONS
01

,. ~ ~Tf-(.i----·1f-

,. --0.1 r~t--.l___..t--

--

u

~

~

TEST

RL

IQUIESCENT

CI

w
a: 2

CONNECT TERM
NO.6

VIN

--

V REF

-

3

:::>

100pF

!zw

S

+1.6

Open

Open

+40

Open

Open

VOUT(MAX)

3650

+40

Ground

Closed

VOUT(MIN)

10k

+30

Terminal No.1

Open

U


~
z

-

"""- ~

C

I
I
I
I
I
INPUT VOLTS (V+jN) .15
OUTPUT VOLTS (V+ouT) .. 10
AMBIENT TEMPERATURE (TAl" +250 C ,

-0.4
125

o

20

150 100
40

60

eoan
80

60
100

LOAD CURRENT (rnA)

FIGURE 7. IUM va TA

FIGURE 8. LOAD REGULATION CHARACTERISTICS

7-35

CA30S5, CA30S5A, CA30S58

Test Circuits and Typical Performance Curves
I
f-

I

I

I

(Continued)

I

INPUT VOLTS (V.,w- 20
OUTPUT VOLTS (V+oUT) _10

o.os

~

0.04

~

~ 0.03

~

0.02

I"'"

w

~ 0.01

o

-75

-50

-

~

5.60

V

-'

VNOISE

8200

-25
0
25
50
75
100
AMBIENT TEMPERATURE ("C)

1000

l00pF

125

FIGURE 10. TEST CIRCUIT FOR NOISE VOLTAGE

FIGURE 9. LINE REGULATION TEMPERATURE
CHARACTERISTICS

TEST PROCEDURES FOR TEST CIRCUIT FOR RIPPLE
REJECTION AND OUTPUT RESISTANCE
Output Reslstancs
VOUT
j ) - -.......- - _ -

Condttions
1. VIN = +25V, CREF = 0, Short E,
2. Set ES2 at 1kHz so that E2 = 4VRMS
3. Read VOUT on a VTVM, such as a Hewlett-Packard, HP400D or
Equivalent
4. Calculate RoUT from RoUT VOUT(RL1E2)

=

Ripple ReJection· I

T" T2 .. STANCOR TP-3

-

T2

O-;S2------BLAC-K---~11

BLACK

AND
YEUOW

GREEN "="

Ripple ReJection· II

-

FIGURE 11. TEST CIRCUIT FOR RIPPLE REJECTION AND
OUTPUT RESISTANCE

10

a4

g
~

1

~

0·t.08

~

...

CondHions
1. Repeat Ripple Rejection I with C REF = 211F

~

I'

(.)

/

~

1.3

II:

1.2

IIIw
!;

V

§

\

1.1

"'- I--....

w

~

~

C

:& U

0.02

z~

4 68 1

2

4 6810 2

4 6'00 2

4 618000

0.8

I

I

-75

FREQUENCY (kHz)

I

I

I

I

I

-50 -25
0
25
50
75
AMBIENT TEMPERATURE I"C)

7-36

"
I

100

FIGURE 13. NORMALIZED ro vs TA

FIGURE 12. ro va'

-

,

Q

8 ~::
0.1 2

INPUT VOLTS (V+JN) .. ZlV
FREQUENCY (f) .. 1kHz
OUTPUT RESISTANCE (Flo) .. 0.0750
(AT TA .. +25OC)

w

./

II:

~

INPUT VOLTS (V+\Nl- ZlV
AMBIENT TEMPERATURE (TAl" +2S"C

2
0.8
0.6
0.4
0.2

Z

-

CondHions
1. VIN = +25V, C REF = 0, Short E2
2. Set Es, at 1kHz so that E, = 3VRMS
3. Read VOUT on a VTVM, such as a Hewlett-Packard, HP400D or
Equivalent
4. Calculate Ripple Rejection 'rom 20 log (E,NoUT)

I

125

I

CA308~CA3085A,CA3085B

Test Circuits and Typical Performance Curves

(Continued)

"-

II!
~~

> ..

REFERENCE VOLTS (VREF) _ +1.6V
(AT T" _ +25"<:)
LOAD CURRENT (IU- 0

0.3

~~

!jw 0.2

O~
~!j
o§!

/

0.1

~5
~~

0

-0.1

V

ww

filfil

:r:r
"''''
00

,

/

~

40V

-0.2

'. '. '.'..••.

'. ....

1\\ 2SV

-50

-25

OPERATION WITHOUT
HEAT SINK

-

OPERATION WITH
HEAT SINK

.•.....
".

...

/

I

:;.~'.:::: '.:::::

..
.......

'\"
"'-..15V

" "'--

0
25
SO
75
100
AMBIENT TEMPERATURE rC)

125

40

20

FIGURE 14. TEMPERATURE COEFFICIENT OF VREF AND VOUT

INPUT~OLTS

(VIN) '" 20V
40V
SOY

J

INPUT VOLTS (V!Nl.l0V

IIII!o..

V

<1<1 -0.3 -75

.- --

'.

\\
-~ ;~;

/

ffi~

ffit!:

\

~

60
80
OUTPUT (mA)

100

FIGURE 15. DISSIPATION LIMITATION (VIN - VOUT vs lOUT)

~~61

---11.:.-",

US!!!

51Gn

a:...I

08:

56

~~a:

::::I

QUIESCENT OUTPUT
CURRENT" 1.5mA

ow
w:=
a:O
Q.

I,(on)

VOUT

-1
"'-

~

VPULSE GEN

100mV/cm

50mA STEP (ILl
-

t(l~s/cm)

FIGURE 16. TURN-ON AND TURN-OFF RECOVERY TIME TEST CIRCUIT WITH ASSOCIATED WAVEFORMS

See Application Note AN6157 for further information

7-37

CA30S5, CA30S5A, CA30S5B
Typical Regulator Circuits

VOUT
(REGULATED
OUTPUT)

NOTE:
,. R, and R2 Selected for
Desired Output
R2
R,
VOUT
V REF ( - R - - )

=

+

0,: Any N·P·N Silicon Transistor that can handle a 2A Load
Current such as 2N3772 or Equivalent
NOTE
1. IL =1.6 + R,. 20(8)........- . . . - -

2KI

50

vJ'

""OUT

RL

..

50l'F

+-!-(50V)

lK
All Resistance Values are in Ohms

0,: 2N2102 or Equivalent

O2: Any P·N·P Silicon Transistor (2N5322 or Equivalent)

0 3 : Any N·P·N Silicon Transistor that can handle the desired

All Resistance Values are in Ohms
D,: 1N4001 or Equivalent
0,: 2N5322 or Equivalent

Load Current (2N3772 or Equivalent)
NOTE:
1. VOUT = (R, + ~) + R,
2. Rscp: Short Circuit Protection Resistance

NOTE:

1. R, = O.7IdMax)
FIGURE 19. TYPICAL SWITCHING REGULATOR CIRCUIT

FIGURE 20. COMBINATION POSITIVE AND NEGATIVE
VOLTAGE REGULATOR CIRCUIT

7·38

CA3277
Dual 5V Regulator with Serial Data Buffer
Interface for Microcontroller Applications

April 1994

Description

Features
o

Dual 5V Regulator
- Your 1 at 5V 100mA - Standby
- Vour2 at 5V 100mA - Enabled
- Regulation Range 6V to 18V
- Bandgap Voltage References

o

Low Quiescent Idle Current, 5001JA Typ.

o

Over-Voltage Shutdown Protection, 20.5V Typ.

o

Reverse Battery Protection, -26V Max.

o

Thermal Shutdown Protection

o

Short Circuit Current Limiting

o

Low Input P.S. Flag and Delayed Reset Control

o

Low Voltage Shutdown Control, Ouput1

o

Ignition Comparator Logic Level Control

o

Data Comparator and 100X Current Mult. Used
as Input/Output Buffers for Remote Serial Data
Communication

The Ignition Comparator senses the voltage level at the IGN IN input
and provides a 5V logic switched output (supply sourced from
OUT1). The Ign~ion Output, IGN OUT can be used to signal a system microcontroller which can respond with a logic switched output
to the CA32n ENABLE input control for OUT2. The OUT1 +5V
Standby Supply of the regulator is normally used as a power supply
for m icrocontroller/memory circuits to preserve stored data when in
the standby mode.To allow for maximum heat transfer from the chip,
the four center leads are directly connected to the die mounting pad.
Refer to AN9302 for further information on CA3277 circuit Applications.

Applications
o

Automotive 5V Regulators and Data Buffers

o

Industrial Controller Remote System

o

Mlcrocontroller and Memory Power Supply

o

Radio, TV, CATV, Consumer Applications

Pinout

The CA32n is a Dual 5V Voltage Regulator IC intended for microprocessor and logic controller applications. It is supplied with features that are commonly specified for sequentially controlled
shutdown and startup requirements of microcontrollers. Over-voltage shutdown, short circuit current limiting and thermal shutdown
features are provided for protection in the harsh environmental applications of industrial and automotive systems. The CA3277 functions
are complementary to the needs of microcontroller and memory circu~s. providing for sustained memory with a 5V standby output.

Ordering Information
TEMPERATURE RANGE
-400 C to +8SoC

PACKAGE
16 Lead Plastic DIP

Functional Block Diagram
CA3277 (PDIP)
TOP VIEW

2
OUT1
+5V
(STANDBY)

BATT

15
OUT2
+5V
(ENABLE)

DATA IN 3
IN
4,5AND

12, 13
=GND

CAUTION: These d9\lices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-39

File Number

2792.4

Specifications CA3277
Absolute Maximum Ratings

Thermal Information

Max. BATT, IGN IN Input Voltage (Note I ) • • • • • • • . • • • • • .. ±26V
Max. Operating Voltage; BATT, IGN IN ••..•••. VBATT(SO) (-20.5V)
Max. Positive Voltages: (For Negative VoRages, Note 2)
ENABLE Input. ...••..••.....•••••....••••••.•.••• VBATT
DATA IN Input •••.•.•••••••.••••.•••••••••.••••••• VBATT
CUR OUT, OUtput. ••••.••••••••••.•..•..•••.••••.• VBATT
RESET, Output ••••.••••••.•••••••.•••..••••••••.. VBATT
Max. Operating Load Current, OUTI ••••..••.•••••••••• lOOmA
Max. Operating Load Current, OUT2 ....•••••..••...... lOOmA
Max. Current Mull. Load Currents:
Min. Load Resistance, CUR OUT •. 2250 to BATT (75mA max)
Min. Load Resistance, CUR IN ...••• I Kn to GND (-5mA max)
Max. Load Current OUT1, OUT2 (Short Duration) ••• SeH-Limiting
Max. PIus/Minus Load Currents: (Note 3)
IGN OUT Output .•••.••••••.••••.••.•.•••••••SeH-Llmlting
DATA OUT Output •••••.•••.••.•...•.......•••SeH-Limiting
RESET Output ••••.••••••••••••.•.•••••...•• SeH-Limiting

Thermal Resistance
8JA
8JL
Plastfc DIP Package ••••••••.•.•. . • • 6O"C/W
12"C1W
(Temp. meas. on center lead next to case)
Power Dissipation, Po (Note 4):
Up to +6O"C (Free Air) ••••••••••••••••••••.••••••••• 1.5W
Above +6O"C: ••••••.••••••.•. Derate Linearly at 16.6mWt'C
Up to +85°C wlheat sink (PC Board): . • • • • • • • • • • • • • • •• 1.6 W
Operating Temperature Range •••••••••••.••••• -'lO"C to +85°C
Storage Temperature Range ••••••.••••.•..••• -55°C to +15O"C
Max. Junction Temperature ••.••••.••.••••........••. +150°C
Lead Temperature (During Solder) •....•••..•.......•. +265°C
1/16 ± 1/32" from case, lOs max

CAUTION: Slr6sses _
thoss listed in "Absolute Maximum Ra#ngs" may cs""e permanent damage to the davIcB. This is a slrBss only rating and opsratlon
of the dBV/ca at these or any other condnions abo... those Ina,c,ded In the operational secUons of this specification Is not Implied.

Electrical Specifications TA = -'10°C to +85"C, v BATT = 13.5V, ENABLE ON (VEN = 3.5V), IGN IN connected to BATT, OUTI and
OUT2 bypassed with 20JlF to GND, DATA IN connected through 2S00 to BATT, LOADS: OUTI = SOmA,
OUT2 = BOmA; Unless Otherwise Specified (Refer to Rgure 4 Test Circuit)
PARAMETERS

SYMBOL

CONOmONS

MIN

TYP

MAX

I UNITS

REGULATOR OUTPUT1
Output Voltage

VOUT1

VBATT = 9V to 16V

4.75

5

5.25

Dropout Voltage (Note 5)

VOO1

VBATT = 4.75V

4.15

4.6

V

-

-

9

40

mV

Line Reg

VBATT = 6.2V to 16V

Load Reg

ILOAD = 0.5mA to 50mA

30

60

mV

170

2SO

mA

-

3.5

-

V

V

-

Current Limiting
Low Voltage Shutdown

Ramp VBATT Down Until OUTI drops (PNP Driver Cutoff)

V

REGULATOR OUTPUT2
Output Voltage

VOUT2

VBATT = 9V to 16V

4.75

5

5.25

Dropout Voltage (Note 5)

VD02

VBATT =5.6V

4.6

5

-

V

7.5

40

mV

Line Reg

VBATT = 6.2V to 16V

Load Reg

ILOAD = O.SmA to BOmA

Current Limiting
ENABLE Input Current

lEN

ENABLE Input Sw. Thd.

VEN(THD)

VEN =5V
Ramp ENABLE Input Up Until OUT2 is
Switched ON

-

35

60

mV

190

250

rnA

SO

ISO

-

1.2

-

JlA
V

BO

100

-

CURRENT MULTIPLIER
ICIN ~ -200JlA

Current Mull. Gain, (lcou..-llcIN)

Gain
Ratio

Current Mull. Output Sal.

VCOUT(SAT)

ICIN = -200JlA, CUR OUT Load = 1Kn to VBATT

-

0.3

1

V

Current Mult., Max. Drive Cur.

ICOUT(MAX)

ICIN = -700JlA

35

SO

-

mA

Ramp VBATT Down, Measure VBATT when
RESET (V RST) goes low

3.B

4.2

4.5

V

CRST Cap. = 0.47JlF, VBATT = 6.BV
RESET Load = SKn to OUT1

50

150

250

rns

-

-

V

0.2

V

B

-

rnA

RESET
Reset, (RST) Threshold
Reset Delay Time (Note 6)

lAST

RESET Out High

VOH(RST)

47KntoOUTI

4

RESET Low

VOl(RST)

VBATT = 3.7SV, RST 47Kn to OUTI

-

RESET Output Sink Current

IOL

CRSTlo GND, VBATT = 6.BV

7-40

-

Specifications CA3277
Electrical Specifications TA =-40"C to +85°C, VBATT =13.5V, ENABLE ON (VEN =3.5V), IGN IN connected to BATT, oun and
OUT2 bypassed with 2O!LF to GND, DATA IN connected through 2500 to BATT, LOADS: OUTl = 50rnA,
OUT2 = 80rnA; Unless Otherwise Specified (Refer to Figure 4 Test Circuit) (Continued)
PARAMETERS

SYMBOL

CONDITIONS

MIN

TVP

VBATT
-3.6

VBATT
-2.9

-

I MAX

UNITS

DATA COMPARATOR
Data Camp Thd
Data Camp Hysteresis
DATA OUTLaw

VOL

VSATT =16V, VOATAIN =(VBATT -5V)

DATA OUT High

VOH

VSATT =16V, VOATA IN =16V

DATA OUT Low Sink Current

IOL

VOATAIN Low

DATA OUT High Source Current

IOH

VOATA IN High

VBATT
-2.2

V

200

-

mV

-

0.15

V

5.25

V

1

-

mA

-50

5.5

6

6.5

V

-

200

-

mV

-

0.15

V

VOUT1
-0.15

-

IJA

IGNITION COMPARATOR
Ign CompThd
Ign Comp Hysteresis
IGN OUT Low
IGN OUT High

VOL
VOH

4.6

IGN OUT Low Sink Current

IOL

VIGNIN Low

IGN OUT High Source Current

IOH

VIGNIN High

Ie

VSATT =12.6V, No Loads, VEN =VIGN IN =OV

VBATT(OVSD)

Ramp VSATT Up Until oun and OUT2 Shutdown

1Vpp at 3kHz on BATT INPUT, Measure AC
Ripple on OUT1, OUT2

-

1

5.25

V

-

rnA

-70

.

-

500

800

IJA

19

20.5

23

V

-

150

45

55

-

dB

-

IJA

OTHER PARAMETERS
Idle Current
Over-Voltage Shutdown
Thermal Shutdown
Ripple Rejection

TJ

°C

NOTES:
1. For negative voltages on the BATT and IGN IN inputs, current drain is primarily reverse junction leakage, except when DATA IN, CUR
OUT, ENABLE and RESET are directly connected to BATT. (Note 2)

2. For negative voltage DATA IN, CUR OUT, ENABLE and RESET interlace to NPN or equivalent on~hip structures; providing a forward
junction for current conduction into the IC. Negative current must be limited by the impedance of the external connection. This is also the
case where these terminals are interconnected to BATT, Normal application does not require the BATT connection, except for DATA IN
where a series diode for reverse current blocking may be used. (see Description text information)

3. Refer to the Electrical Characteristic TABLE for all Self-Umiling values.
4. Dissipation, approximately equals: Po" [(VINIIN) + (VCUR OUrlCUR OUT) - 5(IOUT1+louw), where 'INV1N is IGN IN and BATT input dissipation and VOUT1-VOUT2-5V. This assumes neglibible dissipation for the Ignition Camp., Reset and Data Camp. Outputs.
5. Dropout Voltage is VOO1 = (VSATT - VOUT1) for REG. oun and VD02 = (VBATT - VOUT2) for REG. OUT2
6. Reset Delay Time, tRsT is the time period that the RESET (Pin 8) is low following the discharge of the CRST capacitor to ground. For test
evaluation, the CRST pin may be discharged repetitively with a transistor switch. The RESET pin switches from low to high when the
CRST pin is charged to approximately 3V. Normal ATE testing measures the source charging current which is typically 101JA. For any
other value of Capacitor the charge time, t for reset is determined as follows: t -308C, where C Is in I1F and t is In milliseconds.
(i.e. C = 0.4711F, t = 141ms)

7-41

CA3277
R1

IGNIN

2200
C1

~O.1111'

-=-

------ ---I---- ----- _______ J
-=-

EN
(OUT2)

C3
0.47111'
TO
r---_OUT2
+SV
DISPLAY OR VL.---I
CONTROL
OUTPUT

TOO

CRST

RESET

RDI SENSE CONTROL
IN
OUT

SV MlCROCONTROLLER

RS

47Kn

GND

.J.
FiEsET

VDD

+SV
CMOS
MEMORY

BUS

NOTE: DATA IN and CUR OUT are remote/host Serial Data Communication Buffers. lYplcal Remote Source
Impedance for DATA IN Is 1kO. Typical Remote Load for CUR OUT Is 2500.
FIGURE 1. TYPICAL APPLICATION CIRCUIT OF THE CA3277 DUAL 5V REGULATOR WITH MICROCONTROLLER AND SERIAL
DATA BUFFER INTERFACE TO A REMOTE HOST

Applications
Other functions of the CA3277 include a Data Comparator
and Current Multiplier for use as interface buffers to transfer
serial data at higher level logic to and from a remote host
microcontroller. The OUT1 5V Standby Supply provides
power to the local microcontroller which interfaces to the
CA3277 interface buffers at a 5V logic level. As shown in
Figure 1, the DATA IN input of the Data Comparator receives
serial data referenced to the BAn voltage level. The output
of the Data Comparator is 5V CMOS compatible logic and is
connected to the RDI (remote data input) terminal of the
microcontroller. The TOO (data out) output of the microcontroller is connected to the Current Multiplier input of the
CA3277.
Current Multiplier - The Current Multiplier, with internal circuitry shown in Figure 2, receives data from the
microcontroller in the form of an open drain or gate switched
output driving a 22KO resistor load in series to the Current
Input at pin 10 (CUR IN). The input stage of the Current Multiplier is a current mirror amplifier which is internally
connected to the 5V regulated OUT1 voltage source. The
output stage of the Current Multiplier is a current mirror
amplifier referenced to GND and has an open collector
Current Output at pin 9 (CUR OUn, with a minimum drive
capability of 35mA. The Current Multiplier output load is

normally connected via resistive loading to the BAn voltage
supply level. As such, the microcontroller transmits data out
(TOO output) to the input of the CA3277 Current Multiplier
which amplifies and translates the signal back to the voltage
reference level of the BAn power supply input. When
driving a similar remote CA3277, the voltage drop from the
BAn input line switches the Data Comparator which
provides serial data to the RDI input of the remote microcontroller. The nominal current gain of the Current Multiplier is
100X.
The application use of the Current Multiplier is not limited to
digital serial data transfer. The Current Multiplier is an
independent function and is open to use for other purposes,
including linear signal amplification, sensor output amplification and current controlled threshold switching. The current
output terminal, CUR OUT may be externally loadconnected to OUT1, OUT2, BAn or any other power supply
level up to the maximum ratings given for the BAn input
terminal. It is important to note that some applied uses of the
Current Multiplier may contribute Significant on-chip power
dissipation. A nominal current mirror input drive of 200f.l,A will
provide sufficient drive to switch a 2500 resistor load at the
input of the data comparator. As such, the quiescent OFF
condition of the Data comparator should be in the High state.

7-42

CA3277

r------------

CA3277

2500
DI ......CO-,'--£'
CUR
IN
10

l
ICIN

GND

,
,
Q103 ,:
,,
,
,,
,,

4,5AND
12,13 : _________________ : ___

5100
CUR
OUT
8

,,
,

,,
: CA32n
: REMOTE

:, SYSTEM

-----------_.

J

FIGURE 2. CURRENT MULTIPLIER DRIVING A REMOTE
CA3277 DATA COMPARATOR

Data Comparator - The Data Comparator provides a means
of translating serial data from a high to low voltage. The
DATA IN terminal of the Data Comparator is biased to
receive signal input that is source referenced to the BATT
supply voltage level. In normal use the signal input would be
supplied from a remote Current Multiplier having a resistor
load tied to the BATT voltage supply. The DATA OUT output
from the Data Comparator is CMOS compatible 5V noninverting logic data referenced to GND. The switching
threshold at the DATA IN input is bias stabilized by the bandgap voltage and is typically at (VSATT - 2.9V). The Data
Comparator is in a high state when DATA IN input is at the
BATT voltage level and is in a low state when DATA IN is at
(VBATT - 5V). The output stage of the Data Comparator is
internally supply biased from the Switched 5V Regulator
output to provide a high state of 5V and a low state of OV
(GND). The DATA OUT terminal can typically sink 1.2mA in a
low state or source 501lA in a high state.
In system applications the Data Comparator is used to
translate remote data at high voltage down to 5V logic levels.
The Current Multiplier is used to reverse the process by
translating 5V logic data back to the BATT voltage level
when sending data back to the remote system. The Data
Comparator and Current Multiplier are level matched for
remote communication between microcontroller systems
using the common BATT power supply voHage of the
CA3277. The current driven serial data from the Current
Multiplier is sent to a remote system by translating the signal
up to the BATT voltage level, or an external power supply
level that is compatible with the remote device. The Data
Comparator of the remote system receives the data,
interfaces to its microcontroller and responds with signal
drive from its Current Multiplier to translate the signal back to
the host. For best noise immunity the transmission in each
direction should be over a twisted pair or shielded line. As
such, two microcontrollers, each with the interface protection
of a CA3277, can provide intelligent master/slave system
communications under adverse environmental conditions.

Ignition Comparator - While the Ignition Comparator is provided as an essential part of the start-up control in automotive systems, this circuit function may be used as an
independent switching comparator. It Is Important to note
that the thermal shutdown feature on the chip Is disabled when the IGN IN Input Is low. Disabling of the onchip thermal protection is done to satisfy the requirement of
low idle current when the system is in a standby condition.
The non-inverting IGN IN input has a switching threshold of
typically 6V with 200mV of hysteresis and is switched with
logic levels reference to GND as the low state and BATT as
the high state. The IGN OUT output is 5V CMOS compatible
logic, equivalent to the Data Comparator output stage, but is
internally supply biased from the Standby 5V Regulator. As
such, the high state is level referenced to OUT1. The IGN
OUT output terminal can typically sink 1.2mA in a low state
or source 701lA in a high state.
Enable - A CMOS or TTL high at the ENABLE input
switches the regulated 5V1Switched Output ON at OUT2.
The ENABLE input has an internal pull-down of typically
501lA to ensure that OUT2 is OFF when the ENABLE input
is not connected. The input threshold level for switching is
the bandgap voltage reference of 1.2V. When the ENABLE
input is low, all drive current to the output pass transistor is
cutoff and OUT2 voHage drops to ground level. The ENABLE
input is normally switched from the interfacing microcontroller but may be activated from a remote source.
Reset - The purpose of the Low Voltage Reset function is to
flag a low voltage condition at OUT1. When the RESET output, pin 8 switches low, the voltage level at OUT1 has
dropped below the regulation level. The CRST and RESET
are high when OUTl is at 5V. When OUTl drops to less than
4.2V (typical), the CRST Capacitor at pin 7 is internally
discharged, causing the RESET pin to change from a high to
a low state, outputting a negative going pulse. The RESET
output is an NPN open collector driver requiring an external
load resistor, normally connected to OUT1. The RESET
output flag may be sent to a microcontroller to initiate a
power-down sequence. For any condition that causes OUT1
to drop below the reset threshold, such as undesired
transients, the RESET output is switched low for a delay
period, tRST determined by the value of the external
capacitor, CRST at CRST terminal. For a value of O.47~F the
delay period is typically 141ms. This correlates to approximately IOIlA of charging current sourced from the CRST
terminal to charge CRST'
Regulation - The regulated output stages of the CA3277
have similar circuits, each having an error amplifier to
compare the output voltage to the bandgap reference
voltage. The circuit of the 5V1Switched regulator is shown in
Figure 3. By feedback, the output voltage is differentially
compared to the bandgap reference voltage. The error signal
is then amplified to drive a PNP pass transistor and maintain
a stable 5V output with both line and load regulation over the
full operating temperature range. Except for the ENABLE
control of OUT2, the
drive circuit is similar to the
OUT2 circuit.

oun

7-43

CA3277

oun

Protection· Both
and OUT2 PNP output pass transistors are protected with Over-Voltage Shutdown and OverTemperature Shutdown. Current Limiting for each output is
independent and is accomplished by limited drive current
from the pre-drivers (Q135 for OUT2) to the PNP output
pass transistor (Q136). Over-Voltage is sensed as a threshold voltage level at the BATT input. Both output stages are
shutdown when the VBATI voltage level is typically greater
than 20.5V. When the Ignition voltage is high, the Over-Temperature level is sensed as VBE changes and compared to
the bandgap reference voltage. When the chip temperature
exceeds 150"C, both output stages are shutdown. When
Over-Voltage or Over-Temperature thresholds are exceeded,
the sensed states are ORd to switch OFF drive to the output
stages. The ENABLE control for OUT2 is added to the OR
control of the OUT2 drive circuit. The Low Voltage Shutdown
control is added to the OR control of the OUT1 drive circuit.
Low Voltage Shutdown occurs at approximately 3.5V as the
BATT supply input is ramped down, forcing cutoff of the PNP
output pass transistor. The external capacitor on OUT1
holds charge, with a long RC time constant delay to sustain
shutdown control in the microcontroller. The internal shunt
resistance at the OUT1 terminal is typically 148Kn.
Under conditions of reverse battery or negative supply
voltages on the BATT input, current in the IC is primarily
reverse junction leakage. The design of the CA3277 is
configured to prevent high current if the power supply is
reversed. Exceptions to this are preventable. One example is
current through the DATA IN input line terminating resistor,

normally connected directly to the BATT supply line. This
provides a path for current conduction into the IC through an
Internal diode junction. The current is limited by the external
resistor and may be as high as 100mA at -26V. Where
negative supply voltages are potentially a problem, the
resistive load from DATA IN to BATT can be in series with a
reverse voltage blocking diode, such as a 1N914. This input
diode-resistor circuit is shown in Figure 2 as the remote
interface and load to the Current Multiplier output.
Dissipation • The CA3277 device dissipation is the combined watts of input voltage times current less the external
watts of power supplied by the chip. For normal use, the
major contribution to on-Chip dissipation is primarily the
BATT input dissipation. The Current Multiplier output has a
potential to add significant dissipation. The open collector
driver of the Current Multiplier Output, pin 9 mayor may not
be in saturation when sinking current. Because it is a current
mirror output with a constant current drive, the voltage may
be increased on pin 9, with a significant increase in the
resulting dissipation. The chip dissipation is approximately
equal to:

where I,NV,N is IGN IN and BATT input dissipation, assuming
VBATI = V,GN IN, and VOUT1 - VOUT2 - 5V. This assumes
negligible dissipation for the Ignition Comparator, Data
Comparator and Reset outputs.

OUT2 PASS
TRANSISTOR "TOBATI+----~---------~r----------~~---------~------~~~

15 OUT2
'i-~p--o +5V

R32

6.4K

EN INPUT

7
R33

6.4K

OVER-VOLTAGE
SHUTDOWN

FIGURE 3. OUTPUT2 DRIVER AND ERROR AMPLIFIER WITH THE ENABLE CONTROL

7-44

CA3277

VSATT



-

c

J
15
INPUT VOLTAGE (V)

I

8
6

~

4

~

2

~\

o

2.5

20

TA ,,+250C, RL1

=1Don, RL2 =62n

Z

e.
I-

i3

0.2

... ::>

j:'U

8a:

3~~~~r--t--+--i--;--_t

::>

4

U

10
15
IGN IN INPUT VOLTAGE (V)

J-OVER-VOLTAGE
SHUTDOWN

TA" +250C, VSATT • 13.5V
30 CUR OUT THROUGH 250n TO BATT
ENABLE AND IGN IN TO BATT

-w
"'a:
:!:a: 15

2~--tr_-r-~~~+--i--;--_t

5

~I

NORMAL
OPERATING RANGE

~<" 25
I-E
=>- 20
01'Z

I- 0.3 t---'-::::::;o...,"'----1I::::;;00...'T---+--ff--.::-t--_t
::>

:!:
~ 0.1

I-

22.5

35

S2"

a:

...

20

FIGURE 4B. TYPICAL CHARACTERISTICS CURVES FOR NOLOAD BATT INPUT CURRENT vs BATT INPUT
VOLTAGE FOR OFF STATE IDLE CURRENTS

1) BATT TO 16V, ENABLE TO oun - r - - + - - + - - I
<" 0.5 2)
§.
BATT TO 11 V, ENABLE TO oun
3) BATT TO 16V, ENABLE TO GND
~
4) BATT TO 11V, ENABLE TO G~N~D~"'f-_-+_-If----1
~ 0.4

:

10
15
INPUT VOLTAGE (V)

5

~
LOW VOLTAGE
DROPOUT

FIGURE 4A. TYPICAL CHARACTERISTIC CURVES FOR OUT1
AND OUT2 OUTPUT VOLTAGE vs BATT VOLTAGE
INPUT

1-

1\ '--"

5

oV

lL

V

V

/

TEST NOTE:
MEASUREMENTS MADE
AS VOLTAGE ON son LOAD
FROM CUR OUT TO 5V

I

I

I

I

o

0.1
0.2
0.3
0.4
CUR IN (PIN 10) -INPUT (SOURCED) CURRENT (mA)

20

FIGURE 4C. TYPICAL IGN IN CURRENT vs IGN IN INPUT VOLTAGE

10

V

V

FIGURE 40. TYPICAL CURRENT MULTIPLIER CURRENT GAIN
CHARACTERISTIC

7-45

CA3277
TA. +25oC, ENABLE HIGH; IGN IN TO BATT
DATA IN THROUGH 2500 TO BATT
__
1) OUTl • OU12. 500
2) OUTl • 1000, OUT2 • S20
3) OUT2. 620, OUT1 OPEN
4) OUT1 • 11114!2: OU12 OPEN

!i 15
II! ,:;

1.00

--

ex: -

;\! ...
_E
-

~; 10

0.08

I

:>N

i:6

, - - - ............ - 2

0.84 I---il+---If---+--il""'c::+--+-+--I
I(

C

O~~---L~~

5

---

0." t--t-t;::::;t--=t=::-+-t--t--i

r~~ 5,=+=-n'l=l=~=l=*~
I-~-t--~
i
o

TA. +2rC, ENABLE HIGH
IGN IN TO BATT, VBATT.13.5V
DATA IN THROUGH 2500 TO BATT
1) Iourt VARIED, 0UT2 - NO LOAD
2) Ioun VARIED, OUT1 - NO LDAD

__~~~~---L~

10
15
INPUT VOLTAGE (V)

........

1

D.1121---,+-+-+-+--+--+--1-----I
0.00 O~.......'----:50~-'----:l'=00:--L--:l~50:-......-

20

......

OUTPUT CURRENT (rnA)

FIGURE 4E. TYPICAL CHARACTERISTIC CURVES FOR COMMON
(GROUND) CURRENT vs BATT VOLTAGE INPUT
WITH OUTPUT LOAD

FIGURE 4F. TYPICAL atARACTERIS11C CURVES FOR CURREN!"
TRANSFER EFFICIENCY OF Iourtl\N AND Iour.AN
WHERE Iw ~UDES (\aN IN + ioATA tJ BIAS CURRENTS

7-46

HIP5060
Power Control IC
Single Chip Power Supply

April 1994

Features

Description

• Single Chip Current Mode ControllC

The HIP5060 is a complete power control IC, incorporating both the high
power DMOS transistor, CMOS logic and low level analog circuitry on the
same Intelligent Power IC. Both the standard "Boost" and the "SEPIC"
(Single-Ended Primary Inductance Converter) power supply topologies
are easily implemented with this single controllC.

• GOV, 10A On-Chip DMOS Transistor
• Thermal Protection
• Over-Yoltage Protection

• On-Chlp Reference Voltage· 5.1V

Special power transistor current sensing circuitry is incorporated that
minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to
monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage.

• Output Rise and Fall Times - 3ns

As a result of the power DMOS transistor's current and voltage capability

• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output

(lOA and 60Y), power supplies with output power capability up to 100
watts are possible.

• Designed for 27V to 45V Operation

Applications

Ordering Information

• Single Chip Power Supplies
PART NUMBER

TEMPERATURE RANGE

PACKAGE

HIP5060DY

OOC to +85°C

37 Pad Chip

HIP5060DW

oOC to +85°C

Wafer

• Current Mode PWM Applications
• Distributed Power Supplies
• Multiple Output Converters

Chip

e

0

II.

li

:;

z

:;;II.
III

9:

5:

!2.

:!it.

z

~

(8) VDDA

FlTH (37)
VREG(36)

(9)V+

VCMP (35)

(10) SlCT

PSOK(34)

(ll)CKIO

SHRT(33)

(12) DGDl

PSEN (32)

(13) VooP
!!!!!!!J!!!!!!!I_lIiiiiiiiOl.~ (14) VOOP

TMON

(31)

.11 . . . . . . . . . . . . . . . . 11 •

NOTE: Unused pads are for trim and test.

153 mils x 165 mils (3.88mm x 4.19mm)
CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-47

File Number

3207.1

HIP5060

Simplified Block Diagram
4,.H

4"H
1.1""
VIN

100""
V+

O.l"F

30.1K

4,.H

CLOCK
AND
CONTROL
LOGIC

VCUP
FlTN
PSOK
0.033"F
SHRT

VREG

AMP
PSEN

0.1"F

VOOP

mON

VOOP
0.1"F

VINP
DGD1

AGND
CKiO SLCT VDDA

VDDD

IRF1

IRFO

SFST

TYPICAL SEPIC CONFIGURATION

7·48

0.88"F

Specifications HIP5060
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, v+ •.••..........•.••.•••... ..().3V to 45V
DMOS Drain Voltage ••....••••..•••.••••••..•• ..().3V to 60V
DMOS Drain Current •.•.•••••••.••••••••••.••••..•••• 20A
DC Logic Supply ..•.•...•••••••••••••••••••••• ..().3V to 16V
Output Voltage, Logic Outputs .....•....••••••••. ..().3V to 16V
Input Voltage, Analog and Logic •••••.•.•.•••••••. ..().3V to 16V
Operating Junction Temperature Range •..•.••.••• O"C to + 110°C
Storage Temperature Range •••....•.•••••••. -55"C to +1 SOOC

Thermal Resistance
9JC
(Solder Mountad to . • • • • • • • • • • • . • . . • • • • • . . •• 3°CIW Max
0.050" Thick Copper Heat Sink)
Maximum Junction Temperature .•.•....•.••.......•.. +11 OOC
(Controlled By Thermal Shutdown Circuit)

CAUTION: S/rIlSSSS above those "sted in "Absolute Maximum Rafings" mey cause permanent damage to the device. This is a stress only ra6ng and op8ra6on
of the device at these or any other conditions above thoss Indicated in the op8ra60nal sections of this speciflca60n is not imp/ied.

Electrical Specifications v+ = 36V, TJ = OOC to +ll00C; Unless Otherwise Specified
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DEVICE PARAMETERS
Supply Current

PSEN= 12V

-

19.5

32

mA

Internal Regulator Output
Voltage

V+= 15Vto 45V, lOUT = 10mA

11.0

-

13.2

V

VINP

Reference Voltage

lylNP = OmA

5.01

5.1

5.19

V

RylNP

VINP Resistance

VINP=O

-

900

-

0

Input Offset Voltage
(VREG - VINP)

lycMP = OmA

-

-

10

mV

R1NVREG

Input Resistance to GND

VREG=5.1V

-

56

-

kO

Om (VREG)

VREG Transconductance
lyCMP"(VREG - VINP)

VCMP = 1V to SV, SFST = 11V

15

30

50

mS

gm (SFST)

SFST Transconductance
IYCMpI(VREG - SFST)

VSFST < 4.9V

O.S

-

6

mS

lyCMP

Maximum Source Current

VREG = 4.95V, VCMP = SV

-2.5

mA

Maximum Sink Current

VREG = 5.25V, VCMP = 0.4V

0.75

2.5

mA

OVTH

Over-Voltage Threshold

Voltage at VREG for FLTN to be
latched

6.2

-

.().75

lycMP

6.7

V

Internal Clock Frequency

SLCT = OV, Vooo = 12V

0.9

1.0

1.1

MHz

External Clock Input Threshold
Voltages

SLCT= 12V

33

-

66

%Vooo

1+
VOOA

ERROR AMPLIFIERS
IVIOI

CLOCK
fq
VTHCKIN

DMOS TRANSISTORS
roS(on)
loss

Drain-Source On-State
Resistance

I Drain = SA, TJ = +25°C

-

-

0.13

0

Drain-Source Leakage Current

Drain to Source Voltage = 60V

-

1

100

IIA

IRFO = OmA to -5mA,
VCMP = O.2V to 7.6V

-

-

125

mV

100

-

270

mV

CURRENT CONTROLLED PWM
IVIOIVCMP

Buffer Offset Voltage (VCMPV1RFO)

VTHIRFO

Voltage at IRFO that disables
PWM. This Is due to low load
current

7-49

Specifications HIP5060
Electrical Specifications V+ = 36V, TJ = oOC to +110oC; Unless Otherwise Specified (Continued)
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

7.4

-

8.0

V

-37

-

-17

J1A

4

6

8

V

-

4.9

AlmA

CURRENT CONTROLLED PWM (Continued)
ITHIRFO

Voltage at IRFO to enable SHRT
output current. This is due to
Regulator Over Current Condition

ISHRT

SHRT Output Current, During
Over-Current

VTH SHRT

Threshold voltage on SHRT to
set FLTN latch

IGAIN
RIRFI
tRs (Note 1)

VIRFO = 8.1V

IpEAK (DMOSORAlN)/IIRFI

al (DMOSORAlN)/at = 1Alms

3.8

IRFI Resistance to GND

IIRFI=2mA

150

-

360

Q

-

30

-

ns

Current Comparator Response
Time

dI (DMOSORAIN)/at> lA1I'S

MCPW
(Note 1)

Minimum Controllable Pulse
Width

25

50

100

ns

MCPI
(Note 1)

Minimum Controllable DMOS
Peak Current

200

400

800

rnA

V+

Rising V+ Power-On Reset
Voltage

22

-

27

V

V+

Falling V+ Power-Off Set
Voltage

-

15

-

V

V+

V+ Power-On Hysteresis

START-UP

VTH PSEN

Voltage at PSEN to Enable
Supply

rpSEN

Internal Pull-Up Resistance, to
5.1V

ISFST

Soft-Start Charging Current

VSFST = OV to 10V

IpSOK

PSOK High-State Leakage
Current

SFST = OV, PSOK = 12V

VpSOK

PSOK Low-State Voltage

SFST = l1V, IPSOK = lmA

VTHSFST

9

-

12

V

0.8

-

2.0

V

-

20

-

KQ

-1.0

-0.7

-0.4

J1A

-I

-

I

J1A

-

-

0.4

V

II

V

135

°C

9.4

PSOK Threshold, Rising VSFST

THERMAL MONITOR
TEMP
(Note 1)

Substrate Temperature for
Thermal Monitor to Trip

TMON pin open

NOTE:
1. Determined by design, not a measured parameter.

7-50

105

HIP5060
Pin Descriptions
PAD NUMBER

DESIGNATION

DESCRIPTION

1

AGNO

Analog ground.

2

VINP

Internal 5.1 V reference.

3

SFST

Controls the rate of rise of the output voltage. TIme Is determined by an internal 0.711A current
source and an external capacitor.

4

IRFO

A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current
sense comparator. The maximum current Is set by the value of the resistor, according to the
equation: IpEAK =321R. Where R Is the value of the external resistor in Kn and must be greater
than 1.5Kn but less than 10Kn. For example, If the resistor chosen is 1.8K, the peak current will
be 17.8A. This assumes VCMP Is 7.3V. Maximum output current should be kept below 20A.

5

IRFI

SeelRFO

6

DG02

Ground of the OMOS gate driver. This pad Is used for bypassing.

7

Vooo

Voltage Input for the chip's digital Circuits. This pad also allows decoupllng of this supply.
This is the analog supply and internal 12V regulator output.

8

VODA

9

V+

This is the main supply voRage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.711F capacitor and may be composed of seven,
single 0.111F chip capacitors.

10

SLCT

This pad provides for the option of using either internal 1MHz operation of for an external clock.
Floating or grounding this pad will place the Internal clock at the CKIO pad. Returning this terminal to Vooo or 12V will allow application of an external clock to the IC via the CKIO pad. There
Is an internal 50K pull down

11

CKIO

Clock output when SLCT is floated or grounded. External clock input when SLCT Is returned to
12V.

12

OG01

This pad Is the return for the digital supply.

13 & 14

Voop

These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a 0.111F chip capacitor placed close to this pad and the OMOS
source pads.

15,16, 19,20,
23,24,27,28

S

Source pads 01 the OMOS power transistor.

17,18,21,22,
25,26,29,30

0

Drain pads of the OMOS power transistor.

31

TMON

This Is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into
the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a
nominal junction temperature of +125"C.

32

PSEN

This terminal Is provided to activate the converter. This terminal may be left open or returned to
5V for normal operation. When the Input Is low, the OMOS driver is disabled.

33

SHRT

2511A is internally applied to this node when there is an over-current condition.

34

PSOK

This pad provides a delayed positive indication when the supply is enabled.

35

VCMP

OUtput of the transconductance amplifier. This node is used for both gain and frequency compensation of the loop.

36

VREG

Input to the transconductance error amplifier is available on this pad. The other input is internaliy
connected to the S.1V reference, VINP, Pad 2.

37

FLTN

This is an open draIn output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current Is experienced.

7-51

HIPS060
Functional Block Diagram

.--WIr-" VREF

13Kll

IRFO

VCMP

7-52

B

IRFI

HIP5061
7 A, High Efficiency Current
Mode Controlled PWM Regulator

April 1994

Features

Description

• Single Chip Current Mode ControllC

The HIP5061 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog Circuitry on the same Intelligent Power IC. The
standard "Boosr, "Buck-Boosf', "Cuk", "Forward", "Flyback"
and the "SEPIC" (Single-Ended Primary Inductance Con·
verter) power supply topologies may be implemented with
this single controllC.

• 60V, On-Chip DMOS Power Transistor
• Thermal Protection
• Over-Current Protection
• 250kHz Operation

Over·temperature and rapid short-circuit recovery circuitry is
incorporated within the IC. These protection circuits disable
the drive to the power transistor to protect the transistor and
insure rapid restarting of the supply after the short circuit is
removed.

• Output Rise and Fall Times -10ns
• On-Chlp Reference Voltage - 5.1V
• Slope Compensation
• Vee Clamp Allows 10.8V to 60V Supply
• Supply Current Does Not Increase When Power
Device Is On

Applications

As a result of the power DMOS transistors current (7A at 30%
duty cycle, 5A DC) and 60V capability, supplies with output
power over 50W are possible.

Ordering Information

• Distributed I Board Mounted Power Supplies
• DC - DC Converter Modules

PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

HIP5061DS

OOC to+85OC

7 Lead Staggered 'Gullwing" SIP

• Voltage Inverters
• Small Uninterruptable Power Supplies
• Cascode Switching for Off Une SMPS

Simplified Functional Diagram

Pinout
HIP5061 (SIP)
TOP VIEW

VIN _-_-~rm"----_--~~-_~-+

Your
PIN 7 Voo
PIN6VG

o

PIN 5 DRAlN

'--~--'___--I-"""" E~ i~:RC~E
"
'"
SOURCE
(TAS)

DO NOT
USE

GND I-~>-'-'--+

~----------------------~~
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-53

File Number

3390.2

Specifications HIP5061
Absolute Maximum Ratings (Note 1)

Thermal Information

DC Supply Voltage, Voo •...•.••••••••••••.•.••• -O.3V to 16V
DC Supply Current, 100 .••..•.•.••..•..•.•..•.•••... 10SrnA
DMOS Drain Voltage ......•.•••.•...•...•••••• -O.3V to 60V
Average DMOS Drain Current .•••••..••••.•••.•••...•••. SA
DMOS Source Voltage, VSOURCE, TAB .••....•••... -O.W to 0.1 V
DC Supply Voltage, VG' ••..••.••••.•.•.••• -0.3V to Voo + 0.3V
Compensation Pin Current, Ivc ••••••••••••.•••• -5mA to 35rnA
Voltage at All Other Pins•.•.•••••••••••...• -0.3V to Voo + 0.3V
Op!lrating Junction Temperature Range•.•.•••••.• O"C to +1 O5°C
Storage Temperature Range •••..•.•••..•••.• _55°C to +150°C
ESD Classification .••.•••••••.•.••••.••.•••• , Class 2 - 2KV
Single Pulse Avalanche Energy Rating, lIS (Note 2) ••• EAS 100mJ

Thermal Resistance
9JC
Plastic SIP Package •••. • • • • • • • • • • . • • • . . . • • .
2"CIW
Maximum Package Power Dissipation at +850 C
(Depends Upon Mounting, Heat Sink and Application) •..•. 10W
Max. Junction Temperature •••••••••••.••.•••••..••.. +105°C
(Controlled By Thermal Shutdown Circuit)
Lead Temperature (Soldering 10s) •..•.•.•.•..••..••.. +265°C

CAUTION: Str8SSes above those Hsted in "Absolute Maximum RaOngs" may cause permanent damage to the device. This is a stress only rating and ""eraOon
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

voo = vG =12V, ve = 5V, VFS = 5.W, SOURCE = GND = DRAIN = OV, TJ = oOC to +1050 C,
Unless Otherwise Specified

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DEVICE PARAMETERS
100

Quiescent Supply Current

Voo = VG = 13.2V, Vc = OV,
VFS =4V

6

12

18

rnA
rnA

100

Operating Supply Current

Voo=VG= 13.2V, Vc =8.5V, VFs =4V

-

24

31

IVG

Quiescent Current to Gate Driver

Voo = VG = 13.2V, Vc = OV

0

10

IlA

IVG

Operating Current to Gate Driver

Ve=3V

-

1

2

rnA

Vooc

Clamp Voltage

100 = 100rnA

13.3

14

15

V

VREF

Reference Voltage

Ive = 01lA, Ve = VFS

5.0

5.1

5.2

V

Input Current

VFB = VREF

AMPLIFIERS
IIFsl
gm (VFS)

VFS Transconductance
IVC/(VFB - VREF)

-

-0.85

0.5

IlA

/lvc / = 5001lA, Note 3

20

30

43

mS

IVCMAX

Maximum Source Current

VFB = 4.6V

-4

-1.8

-1

rnA

IVCMAX

Maximum Sink Current

VFB = 5.6V

1

1.8

4

rnA

Voltage Gain

/lvc / = SOOIlA, Note 3

44

50

-

dB

AoL
VCMAX

Short Circuit Recovery Comparator Rising Threshold VOltagB

S.4

6.6

8.9

V

VeHYS

Short Circuit Recovery
Comparator Hysteresis Voltage

0.7

1.1

1.8

V

0

10

25

rnA

210

250

290

kHz

-

0.15

0.22

Q

-

-

0.33

Q

0.5

10

IlA

-

5

A

200

-

pF

IVCOVER

Vc Over-Voltage Current

Voo = VG = 10.8V, Vc = VCIoW<

CLOCK
fq

Internal Clock Frequency

DMOS TRANSISTOR
rOS(ON)

Draln-Souree On-Stale
Resistance

lORAIN = SA, Voo = VG = 10.8V
TJ= +25°C

rOS(ON)

Drain-Source On-State
Resistance

lORAIN = SA, Voo = VG = 10.8V
TJ = +105°C

loss

Drain-source leakage Current

VORAIN = 60V

IOSH

Average Drain Short Circuit
Current

VORAIN = 5V, Note 4

-

Note 4

-

CORAIN

DRAIN Capacitance

7-54

Specifications HIP5061
Electrical Specifications

voo = vG =12V, ve = 5V, VF8 = 5.1V, SOURCE = GND = DRAIN = OV, TJ = OOC to +105°C,
Unless Otherwise Specified (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TVP

MAX

UNITS

CURRENT CONTROLLED PWM
!Im(Vd

&IORAIN• PEAK I&Ve

Note 3

1.4

2.2

3.0

AN

VII REF

Voltage to Current Converter Reference Voltage

lORAIN = 0.2M, Note 3

2.4

2.8

3.1

V

Current Comparator Blanking
TIme

Note 3

40

100

175

ns

tBT

IoNMIN

Minimum DMOS "ON" TIme

Note 3

60

150

250

ns

IoFFMIN

Minimum DMOS "OFF" Time

Note 3

40

125

200

ns

MinCI

Minimum Controllable DMOS
Peak Current

Note 3

-

100

250

mA

MaxCI

Maximum Controllable DMOS
Peak Current

Duty Cycle = 6% to 30%, Note 3

7

9.5

12

A

MaxCl

Maximum Controllable DMOS
Peak Current

Duty Cycle = 30% to 96%, Note 3

5

8

12

A

CURRENT COMPENSATION RAMP
&1I&t

Compansation Ramp Rate

&IORAIN. PEAK/&TIrne, Note 3

-1.4

-0.85

-0.45

A/jJS

tRO

Compensation Ramp Delay

Note 3

1.3

1.5

1.8

jJS

START-UP
VOOMIN

Rising Voo Threshold Voltage

V FB =4V

9.3

10.3

10.8

V

VOOHYS

Power-On Hysteresis

VFB =4V

0.3

0.45

0.6

V

1.0

1.5

2.0

V

4V < Voo < 10.8V, Ve = 0.8V

50

500

3000

n

Substrate Temperature for
Thermal Monitor to Trip

Note 4

105

-

145

°C

Temperature Hysteresis

Note 4

-

5

-

°C

VeEN

Enable Comparator Threshold
Voltage

Rve

Power-Up Resistance

THERMAL MONITOR
TJ
TJHy
NOTES:
1. All Voltages relative to pin I, GND.
2. Vo = 10V, Starting TJ = +25°C, L = 4mH, IpEAK = 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.

TABLE 1.

CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT

VoM

IL
(PEAK AMPS)

L(mH)

EAS(mJ)

10

5

40

550

10

7

4TZ

120

6

10

0.33

18

6

12.5

0.14

12

NOTE:

7

0

HIP5061

~

1
VAFfY tp TO OBTAIN
REQUIRED PEAK IL

0000
- IL- -!,.+
- V

y_ D

*-

12~
tp

Device Selected to Obtain Peak Current without Clocking

FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT

7-55

HIP5061

Definitions of Electrical Specifications
Refer to the Functional Block Diagram of Figure 1 for locations of functional blocks and devices.
Device Parameters
100 • Quiescent Supply Current - Supply current with the
chip disabled. The Clock. Error Amplifier. Voltage-ta-Current
Converter. and Current Ramp circuits draw only quiescent
current. The supply voltage must be kept lower than the
turn-on voltage of the VDO clamp or else the supply current
increases dramatically.
100 • Operating Supply Current - Supply current with the
chip enabled. The Error Amplifier is drawing its maximum
current because VFB is less than its reference voltage. The
vOltage-to-current amplifier is drawing its maximum because
Ve is at its maximum. The ramp circuit is drawing its maximum because ~ is not being disabled by the DMOS transistor turning off.
IVQ • Quiescent Gate Driver Current - Gate Drivers supply
current with the IC disabled. The Gate Driver is not toggling
and so it draws only leakage current.
IVQ • Operating Gate Driver Current - Gate Drivers supply
current with the IC enabled. The DMOS transistor drain is
loaded with a large resistor tied to 60V so that ~ is swinging
from OV to 60V during each cycle.
VODC • Voo Clamp - Voo voltage at the maximum allowed
current through the Voo Clamp.
VREF • Reference Voltage - The voltage on FB that sets the
current on Veto zero. This is the reference voltage for the
DCIDC converter.
Amplifiers
IIFBI. Input Current - Current through FB pin when it is at its
normal operating voltage. This current must be considered
when connecting the output of a DC/DC convertor to the FB
pin via a resistor divider.
gm(VFB). Transconductance - The change in current
through the Ve pin divided by the change in voltage on FB.
The gm times the resistance between Ve and ground gives
the voltage gain of the Error Amplifier.
IVCMA)(. Maximum Source Current - The current on Ve
when FB is more than a few hundred millivolts less than
VREF •
IVCMA)(. Maximum Sink Current - The current on Ve when
FB is more than a few hundred millivolts more than VREF •

AoL' Voltage Gain - Change in the voltage on Ve divided by
the change in voltage on FB. There is no resistive load on
Ve. This is the voltage gain of the error amplifier when gm
times load resistance is larger than this gain.
VCMA)(. Vc Rising Threshold - The voltage on Vc that
causes ine Voiiage-ia-Curreni Ampiifier to reach full-scale.
When Ve reaches this voRage. the Ve NMOS transistor (transistor with ns drain connected to the Ve pin in the Functional
Block Diagram of Figure 2) turns on and tries to lower the voRage on Ve.

VCHYs • VCMA)( Hysteresis - The voRage on Ve that causes
the NMOS transistor to turnoff if n had been turned on by Ve
exceeding VCMAX' At this voltage the current out of the Voltageta-Current Converter is at roughly three quarters of full-scale.
IVCOVER. Vc Over-Voltage Current - The current drawn
through the Ve pin after the NMOS transistor is turned on
due to excessive voltage on Ve. The NMOS transistor connected to the Ve pin draws more than enough current to
overcome the full scale source current of the Error Amplifier.
Clock
fq. Frequency - The frequency of the DCIDC converter. The
Clock actually runs faster than this value so that various control signals can be internally generated.
DMOS Transistor
rOS(ON)' "On" Resistance - Resistance from DMOS transistor Drain to Source at maximum drain current and minimum
Gate Driver voltage. VG.
loss. Leakage Current - Current through DMOS transistor
at the Maximum Rated Voltage.
Current Controlled PWM
gm(Vd. Transconductance - The change in the DMOS transistor peak drain current divided by the change in voHage on
Ve. When analyzing DClDC converters the DMOS transistor
and the inductor tied to the drain are sometimes modelled as
a voltage-controlled current source and this parameter is the
gain of the voltage-controlled current source.

vnREF • Current Control Threshold - The voltage on Ve
that causes the DMOS transistor to shut off at the minimum
controllable current. This voltage is greater than the Enable
Comparator Threshold (VCEN) so that as Ve rises the IC
does not jump from the disabled state to the OM OS transistor conducting a large current.
t BT • Blanking TIme - At the beginning of each cycle there is
a blanking time that the DMOS transistor turns-on and stayson no matter how high drain the current. This blanking time
permits ringing in the external parasitic capacitances and
inductances to dampen and for the charging of the reverse
bias on the rectifier diode.
tONM1N. Minimum DMOS Transistor "On" TIme - The minimum on-time for the DMOS transistor where small changes
in the VC voltage make predictable changes in the DMOS
transistor peak current. Converters should be designed to
avoid requiring pulse widths less than the minimum on time.
tOFFMIN' Minimum DMOS Transistor "Off" TIme - The minimum off-time for the DMOS transistor that allows enough time
for the IC to get ready for the next cycle. Converters should be
designed to avoid requiring pulse widths so large that the minimum off time is violated. (However. zero off time is allowed. that
is. the DMOS transistor can stay on from one cycle to the next.)

'."nCI, t..1Jnlmum Controllable CUiient .. "·"hen the voitage
on Vc is below VIl REF • the peak current for the DMOS transistor is too small for the Current Comparator to operate reliably. Converters should be designed to avoid operating the
DMOS transistor at this low current.

7-56

HIP5061
MaxCI. Maximum Controllable Current - The peak current
for the DMOS transistor when the Voltage-ta-Current Converter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the. Current Ramp becoming active.
Current Compensation Ramp
AUAt. Compensation Ramp Rate - At a given voltage on Vc
the DMOS transistor will turn off at some current that stays
constant for about the first 1.51!s of the cycle. After 1.51!S. the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
tRo. Compensation Ramp Delay - The time into each cycle
that the compensation ramp turns on. The Current Compensation Ramp. used for Slope Compensation. is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
Start-Up
VOOMIN. Rising Voo Threshold Voltage - The minimum
voltage on Voo needed to enable the IC.

V CEN ' Enable Comparator Threshold Voltage - The minimum voltage on Vc needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the Vc pin to GND.
Avc. Power - Up Resistance - When Voo is below VOOMIN.
the NMOS transistor connected to the Vc pin is turned on to
make sure the Vc node is low. Thus the voltage on Vc can
gradually build up as will the trip current on the DMOS transistor. This is the only form of ·soft starr' included on the IC.
The resistance is measured between the Vc and GND pins.
Thermal Monitor
T J • Rising Temperature Threshold - The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions. especially during start-up when the DMOS transistor may stay on for a long time if an external soft-start circuit is not added.
TJHy • Temperature Hysteresis - The IC must cool down
this much after it is disabled by being too hot before it can
resume normal operation.

VOOHYS. Power - On Hysteresis Voltage - The difference
between the voltage on Voo that enables the IC and the voltage that disables the IC.

INTERNAL LEAD - INDUCTANCE
AND RESISTANCE ___

s.w

v.EF
HIP5061

FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061

7-57

HIP5061
Pin Description
TERMINAL
NUMBER

DESIGNATION

1

GND

2

Vc

The output of the transconductance amplifier appears at this terminal. Input to the intemal
voltage to current convertar also appears at this node. Transconductance amplifier gain
and loop response are set at this terminal. When the VDO terminal voltage is below the
starting voltage, VOOMlN ' this terminal is held low. Whan the voltage at this terminal
exceeds VCM~' 7V typical, implying an over-<:urrent condition, a typical 10mA current,
IVCOVER pulls this terminal towards ground. This current remains "ON' until the voltage on
the Vc terminal falls by VCHYS, typically 1. W, below the upper threshold, VCM~. When the
voltage on this terminal falls below VCEN, typically 1.SV, the IC is disabled.

3

FB

Feedback from the regulator output is applied to this terminal. This terminal is the input to
the transconductance amplifier. The amplifier compares the internal S.W reference and
the feedback signal from the regulator output.

4

SOURCE

The terminal, labeled TAB, has a connection to this terminal, but because of the long lead
length and resuRlng high Inductance of this terminal, It shouid not be used as a means of
bypassing. Therefore, this terminal is labeled "Do Not Use."

S

DRAIN

Connection to the Drain of the Internal power DMOS transistor is made at this terminal.

6

VG

Gate drive supply voltage is provided at this terminal. A 10n to 150n resistor connected
between this terminal and the VDO terminal provides decoupling and the supply voltage
for the gate drivers.

7

Voo

External supply input to the IC. A nomlnal14V shunt regulator is connected between this
terminal and the TAB. A series resistor should be connected to this terminal from the
external voltage source to supply a minimum current of 33mA and a maximum current of
l05mA under the worst cast supply voltage. The series resistor is not required if the
supply voltage is 12V, ±10%.

TAB

SOURCE

This is the internal power DMOS transistor Source terminal. It should be used as the
ground return for the Voo bypass capacitor. In addition high frequency bypassing for both
the regulator output load voltage and supply Input voltage should be returned to this
terminal.

DESCRIPTION

This is the analog ground terminal of the IC.

For more Information refer to Application Notes AN9208, AN9212, AN9323.

Foot Print For Soldering

~~ 0.120 I--

IT
L

0.424

'

,,,
\

,,

0.523

r

UMIT OF SOLDER MASK

OPTIONAL iii 0.151

,

-

-[
1
1
1
1
1
1

-I

+

1_

\

--,

I

FOR HEADER

-EJ-Et-t50TYP

of

oo~
t
~ D-~
1
1
1

___I

lIE

-

0.575

.1

0.675

T0-220 STAGGERED GULL WING SIP

7-58

~

-I

L

0.080TYP

HIP5061

Typical Performance Curves
26

20

24

1.

I
I

I

16 I-- -

_22 OPERATING CURRENT, Voo. VG • 13.2V, Ve. 8.5V, VFB. 4V

'"

I

I

I

I I

I

I

VFB • Vc" OV, TA" +2Soe

S20

.., ,.,..

I-

ill 18

rr:
rr: 16

i3

...!!;~ 1412 -QUIESCENT CURRENT, Voo. Va • 13.2V, Ve. OV, VFB. 4VLYCURRENT vs SUPPLY VOLTAGE

1.2
1.1

Voo ,,12V, VFB" IV

C 1.0

TA"ooe

S

I-

zw 0.9

./

rr: 0.8
rr:
Co>
rr: 0.7

w

0.4

I--

8

0.3

8

0.2

4

\1

~

./

o

10

20

30

40

SO

60

70

80

00

100

....

o

2

3

AMBIENT TEMPERATURE re)

FIGURE 5. TYPICAL GATE DRIVER OPERATING
CURRENT va TEMPERATURE

4
5
6
7
8
VOLTAGE ATVe PIN (V)

0

10

11

5.20

14.8

5.18

I

~
w 5.16

14.6

~

loo,,100mA

~'4.4

w
~ 14.2

~

VOO" VG • 12V,Ive • 01lA, Ve" VFB_

5.14

~ 5.12

!:i
014.0

w

!E 13.8

w

13.6

II!

!il 5.10

>

~ 5.08

d

5.04

13.2

5.02
20

30
40
SO
60
70
80
00 100
AMBIENT TEMPERATURE rC)
FIGURE 7. TYPICAL CLAMP VOLTAGE VB TEMPERATURE

7-59

k

~

-

...-

5.06

13.4

10

12

FIGURE 6. TYPICAL SUPPLY CURRENT va VOLTAGE
AT PIN VePOR O"C AND +105°C

15.0

13.0 0

~"'050C

J'"

0.5

~CI

-

W

,

~~

0.6

~
C

/

Voo = Va" 12V, VFB" 5.1V, Ve" 5V

::>

5.00 0

30
40
so 60 70 80
AMBIENT TEMPERATURE rC)
FIGURE 8. TYPICAL REFERENCE VOLTAGE va
TEMPERATURE

10

20

90 100

HIP5061
Typical Performance Curves (Continued)
-so

5.20
5.18

I

~ 5.14

~ 5.12

I

I

w 5.10

..1-65
ffi
U-ao
!;

ffi 5.08
~ 5.06

~-85

a: 5.04

-ao

w

5.02

-85

5.00
10.8

-100

11.2

11.6

12.0

12.4
12.8
VOO(Y)

13.2

13.S

14.0

FIGURE 9. TYPICAL REFERENCE VOLTAGE vs SUPPLY
VOLTAGE FOR O"C AND +l05°C
0.5

a:
a:

::>

0.2 - I -

U

ffi~32

-0.3

e: 25

-0.4

24
23
-1

20

30
40
50
60
70
AMBIENT TEMPERATURE rC)

./

80

80

100

Voo" Va • 12V, IVc .. 500JlA

,...
./

-

i~27
w:i 26

K
E!: -0.2

0

1

2

3

220

4 5 S 7 8 8 10 11 12 13 14
VOLTAGE ON FB PIN (V)

FIGURE 11. TYPICAL INPUT CURRENT TO FB PIN VB VFB

10

20
30
40
50
SO
70
AMBIENT TEMPERATURE rC)

80

90 100

FIGURE 12. TYPICAL ERROR AMPLIFIER
TRANSCONDUCTANCE vs TEMPERATURE

2.5

2.5

2.0

2.0
VDD= Va

=12V, Vc-4V, TA-+250C",

_ 1.5

..ffi

~

-

C

.§. 1.0

V

~ 0.5

V

w

~ 0.0

a:

g;

/

8z -0.5
" -1.0

!;
!;

o

-1.5

""'"

._

Voo. Va • 12V, Vc = 5V

0.0
-0.5

-1.5

;;;;- -

-2.0

-2.5
-i75-i5o.i25..ioo-7ii -00 ..25 v 25 00 i5 lOG 125150 17G
VOLTAGE ON FB PIN (mY) CENTERED AROUND 5.W

FIGURE 13. TYPICAL Vc PIN CURRENT IVc PIN vs
VOLTAGE ON FB PIN (SHOWS ERROR
AMPLIFIER TRANSCONDUCTANCE)

I

0.5

... -1.0

V

>

SINKING CURRENT, VFB .. 5.6V
I

U

ii:

-2.0

r--

!33 r--

28
:15
a:z 28

.. -0.1

:q
.§. 1.0

10

~g30

0

1.5

~

It: z 31

0.1

-0.5

o

36
35
34

0.3
Voo - Va _12V, Vc _ 4V, TA _ +250C

r-

V

FIGURE 10. TYPICAL INPUT CURRENT TO FB PIN vs
TEMPERATURE

I

0.4

ffi

-

~ -75

::0

a:

"7
/

-70

I
TA- DoC

U

voo. va _12V, Vc. SV, VFB - VREF _

-so

TA=+1050C

!C

l

I

-55

Iyc - 01nA, Vc - VFB

~5.1S

-2.5 :

SOURCING CURRENT, VFB .. 4.SV
I
I

I
10

2C
SO
40
50
50
10
AMBIENT TEMPERATURE (OC)

80

90 ~oo

FIGURE 14. TYPICAL ERROR AMPLIFIER SINKING AND
SOURCING CURRENT VB TEMPERATURE

7-60

HIP5061

Typical Performance Curves (Continued)
12

2.5 , . . . . . . . - - - - - - - - - - - - . . - . . . . - . . . , . . . . . . ,

c
.5,

l-4V:eor·~V~a~.~1~2:Y,1V~C~·U..~Y,~T:A~·i+;25;O~e=+~=t::t:~

2.0
1.5

I

I

I

I

I

I

Veo • OV (UNDER VOLTAGE eONDmON)
10

I-"'"
TAsooer

1-+-+-+-4--!I-......+-+-4--!I-+-++~
!z 0.5 1--I-+-4-I--I-....-4-I-+-+......f-I-+-I
~ 0.0 1--I-+-4-I--I-..........f-I-+-+......f-I-+-I
B
z -0.5 1--I-+-4-I--I-.........f-I-+-+......f-I-+-I
~ -1.0 1-+-+--1-1-+-+--11-+-+-+--11-+-+-1
>
-1.5 I--+-+-+--I-f-+-+-+--I-f-t-+-+--I
1.0

V

2

I=j::::j~r=tr=t~~~-+-+-+-+-+--I

-2.0

o

-2.5 .......-'--'-......--'-'---'--'-......--'-'---'--'--'---'
-1 0 1 2 3 .. 5 6 7 8 0 10 11 12 13
VOLTAGE ON FB PIN M

-

€ 7.5
w 7.0
li 6.5

If. -

Veo = 12V, TA" +2SOe

FB.6V

....i

!:i

-

ill

6.0
~ 5.5
III 5.0
4.5

r' -

FB .. 4V

-4

o

2

~

o

23456
VOLTAGE ON Vc PIN (V)

7

8

~VCMAX
I""

Veo" VG .. 12V

3.0
2.5
c( 2.0
91.5
1•0
~ 0.5

I

3

IY

1;:
§l

VCHYS

en

51

FB .. 4V

-2

~

./

ffi4.0
Iii 3.5

FB=6V

I

"" /

J r--

FIGURE 16. TYPICAL VcPIN CURRENTvs VOLTAGE ON
Vc PIN FOR OOC AND+105°C

FIGURE 15. TYPICAL Vc PIN CURRENT vs
VOLTAGE ON FB PIN

o V

~

/

TA s +105oe

..
5
6
7
8
VOLTAGE ON Vc PIN (V)

10

0

11

12

FIGURE 17. TYPICALVc PIN CURRENTvs VOLTAGE ON Vc PIN
FOR VOLTAGES ABOVE AND BELOW VREF

i!:

Cis!:!:!
a:..J

0.0 0

10

20

30
40
50
60
70
AMBIENT TEMPERATURE ("e)

80

90 100

08:

~:;)
...len

:;)a:

FIGURE 18. TYPICAL SHORT CIRCUIT COMPARATOR
THRESHOLD VOLTAGE vs TEMPERATURE

~w

w==

a:O
Q,

11.0

C

10.5

.....

I
............

.5,10.0

~
~

3.0

I_ t--

~ 2.5
~ 2.0
:z:
01.5

Veo. va .12Y, VF8" 5.W

~ 1.0

......
............

w 8.5

w

I

Veo" Va .. 10.8V, Vc .. VCMAJ(

............

0

!:i

I

~

zto 9.5
w
ex:
ex: 9.0
;:)

li

I

......

8.0

8

,,--

0•5

~ 0.0

......... ~

/'

to-O·5

""

z

~-1.0

7.5

ffi-1.5

7.0

... -2.0

6.5

-2.5

6.0

-3.0

o

10

20

30
40
50
60
70
AMBIENT TEMPERATURE ("e)

80

00 100

o

10

20

30

40

50

60

70

80

AMBIENT TEMPERATURE ("e)

FIGURE 19. TYPICAL OVER-VOLTAGE CURRENT vs
TEMPERATURE

FIGURE 20. TYPICAL CLOCK FREQUENCY PERCENT
CHANGEvsTEMPERATURE

7-61

90

100

HIP5061

Typical Performance Curves (Co"tlriued)
3.0
2.5
2.0

~

~

voo-Vcs12Y, VFB·5.1V

I

1.5

5
~

l..o!'"

...-

..".,...

e_ O•2S

.---

zS

'rA a OOC

1I:j$

elll

!l!i/i 0.15

~::;

IJI'"

I!:~ 0.10

~

---

.---

Voo. Vc .1 0.8V, lORAIN • 5A

~w

I!i!i! 0.20

/'"

-0.5

~ -1.5

I
[

~

0.5
0.0

!Z -1.0

0.30

I

TA·+100oC~

~ 1 •.0

iii

+

-

~

.--~

i~ 0.05

III... -2.0

C

-2.5

-3.0
10.8

11.2

11.8

12.0

12.4
VooM

12.8

13.2

13.8

14.0

FIGURE21. TYPICALCLOCKFREQUENCYPERCENTCHANGE
va SUPPLY VOLTAGE Voo AT COC AND + 100°C

0.30

I

0.28

ezOO.28

I

I

I

:~ 0.24
Cz
@i~ 0.22

I

-

TAs+1000C

!iii/i 0.20

i ::::

I

0.100

:::I

~

I

0.30

/

0.20

:i 2.2

-

2.0

81.8

~

2.86

~

2.84

w 2.12

!i!!!!_

~ 1.6

~

f!;

II:

2.80

w 2.78

1.4
1.2

2.7&

1.0

2.74

80

100

FIGURE 25. TYPICAL TRANSCONDUCTANCE FROM Vc PIN TO
DMOS TRANSISTOR DRAIN (PEAK CURRENT)
va TEMPERATURE

20

I

2.88 -

~ 2.6

30
40
SO
80
70
80
AMBIENT TEMPERATURE rCI

10

2."

I

w 2.4 ...........
U
~

20

-...-

./

30
40
so 80 70
AMBIENT TEMPERATURE (OC)

80

90

100

FIGURE 24. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
LEAKAGE CURRENT vs TEMPERATURE

2.8 -Voo- Vc- 12V

10

V

0.15

~ 0.00 0

FIGURE 23. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE va DRAIN CURRENT loRAIN AT
OOC AND +100°C

I

100

J

: 0.10
.. 0.05

I

2
3
4
5
6
DMOS TRANSISTOR DRAIN CURRENT (A)

I

"

I

I - - Voos80V

~ 0.35

~

0.12

o

30
40
SO
80
70
80
AMBIENT TEMPERATURE rC)

FIGURE 22. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE
RESISTANCE VS TEMPERATURE

i

TA·OoC

l!i III 0.14

~

20

~ 0.25

~::; 0.18
f!;~
f;!5 0•16

3.0

10

lO.50

Voo" Vo s10.8V, VFB s 5.1V

I

0.00 0

I

I

I

I

Voo. Vc .12V,IDRAIN. 0.25A

-

"...,

-- -o

10

20

I,...- ~

I-""""

..-

3D
40
SO
60
70
$0
AMBIENT TEMPERATURE rC)

i,.....--'

90 100

FIGURE 26. TYPICAL VOLTAGE TO CURRENT CONVERTER
REFERENCE VOLTAGE va TEMPERATURE

7-62

HIP5061

Typical Performance Curves (Continued)
,,180

!

I

.s

150

w

w 175 _ Voo" VG" 12V

~145

Z 170
P

Ii.

~

rill
z

....

65
160

--

~ 155

....

-

8150

!lz 145
:::>

~

-

~

0

10

20

30

40

50

..,..

./

II:

.....".

.... ~

UI

iii

"

:i

130

I!'

!l::Ii
i
70

I

Sl35

8 125

60

I

VOO"VG,,12V

? 140

::Ii
Z 140

:i

I

_

80

120

Z 115

80 100

:i

FIGURE 27. TYPICAL MINIMUM DMOS TRANSISTOR "ON"
TIME va TEMPERATURE

0

10

20

30
40
50
60
70
80
AMBIENT TEMPERATURE rC)

9.0

-0.50

!z

8.5

1-0·55 -

(J

I

I

..,.. ....

II:

~

~ -0.70

~

6.5

::Ii 4.0

/

~ -0.80

C

!:! -0.85
w

./

~ -0.80

VOO" VG • 12V, DUTY CYCLE" 96%_

~ 4.5

I

o

10

20

I

I

I

30
40
50
60
70
AMBIENT TEMPERATURE <"C)

I

I
80 100

FIGURE 29. TYPICAL MAXIMUM CONTROLLABLE PEAK
DMOS DRAIN CURRENT va TEMPERATURE

-1.00

,

.",
t/)

./

8 -0.95

80

~

".. i-""""

-0.75

CI

~ 6.0

I~:

100

Voo"VG=12V

:cw -0.65

...w 7.0
~
In

I

~ -0.60

-

7.5

90

FIGURE 28. TYPICAL MINIMUM DMOS TRANSISTOR "OFF"
TIME va TEMPERATURE

~

~ 8.0
:::>

V

",-

V

'"
/'

AMBIENT TEMPERATURE rC)

w

V

o

10

CiJ!:!:!

a:..J
20

40
SO
60
70
AMBIENT TEMPERATURE <"C)
30

80

80 100

O~

5~

:::;)a:

FIGURE 30. TYPICAL COMPENSATING RAMP RATE
va TEMPERATURE

CJW
W~

a:O

a..

1.80

~

1.75

~ 1.70

~

1.65

:5w

1.60

~ 1.55
~ 1.50

~ 1.45
~ 1.40

I

f-

I

11

Voo" VG" 12V

I

~10

-

~;

-

~

8>

1.35
~ 1.30

~

VFB=4V

5

3

!~

1.25

1.20

6

C 4

:iz

C

!:!
(J

VOOMIN

o

10

20

30
40
50
60
70
80
AMBIENT TEMPERATURE rC)

FIGURE 31. TYPICAL COMPENSATION RAMP DELAY
TIME va TEMPERATURE

80

o

100

VOOHYS

o

10

20

30
40
50
80
70
AMBIENT TEMPERATURE (OC)

80

90

100

FIGURE 32. TYPICAL RISING Voo COMPARATOR THRESHOLD
VOLTAGE va TEMPERATURE

7-63

HIP5061
Typical Application Circuit
Figure 33 shows a Simplified Block Diagram of the HIPS061 in a
typical Boost corwerter. A resistor connected from the VIN supply
to the VDD terminal of the IC powers the intemal 14V shunt
regulator. The Gate Driver supply is decoupled from the main
supply by a small external resistor connected between VDD and
the VG terminal. A bypass capacftor is connected between the
VDD terminal and ground to reduce coupling between analog and
digftal circuitry. A Schottky diode insures efficient energy transfer
from the DMOS drain circuit inductor to the load. To set the
output voltage. two resistors are used to scale the output supply
vo~age down to the S.1 V internal reference.
The heart of the IC is the high current DMOS power
transistor with its associated gate driver and high-speed
peak current control loop. A portion of the converters DC
output is applied to a transconductance error amplifier that
compares the fed back signal with the internal S.1V
reference. The output of this amplifier is brought out at
the Vc terminal to provide for soft start and frequency
compensation of the control loop. This same signal is also
applied internally to program the peak DMOS transistor
drain current. To assure precise current control. the
response time of this peak current control loop is less
than SOns.

A 2M Hz internal clock provides aU the timing signals for the
converter operating at 2S0kHz. A slope compensation circuit
is also incorporated wfthin the converter IC to eliminate subharmonic oscillation that occurs in continuous-current mode
converters operating with duty cycles greater than SO%.

HIP5061 Description of Operation
Figure 2 shows a more detailed Functional Block Diagram of
the HIP5061. An internal14V shunt regulator in conjunction
with an external series resistor provides internal operating
voltage to the IC in applications where no 12V auxiliary supply is available. Note that In applications where the input
voltage at V DD is 12V. +/-10%. the regulator is not used. This
regulator is shown as a zener diode on the diagrams of Figure 2 and Figure 33.
The 2MHz clock is processed in the Control Logic block to
provide various timing signals. A cycle of operation begins
when a 100ns pulse (which occurs at a 41ls interval) triggers
the latch that initiates the DMOS transistor on-time. This
pulse also provides a blanking interval in the Current Monitoring block to eliminate false turn-ofts caused by high transient pulse currents that occur during turn-on. The output of

VIN o-4_-.-_-J'Irrn_ _ _....._ _

-I~

_ _.....-.._ _...

VOUT

CND

FIGURE 33. StMPLlFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION

7-64

HIP5061
the Current Ramp block is summed with the sensed DMOS
transistor current (to provide slope compensation) before
being compared with the Error Current signal. The current
ramp, -0.45A1l1s, is inhibited for the first 1.511S (37.5%) of the
duty cycle by the Ramp Enable signal, since ramp is not
needed for slope compensation during this interval. Inhibiting of the compensating ramp has the effect of reducing the
peak short-circuit current.
The output of the power supply is divided down and
monitored at the FB terminal. A transconductance error
amplifier compares the DC level of the fed back voltage with
an internal bandgap reference, while providing voltage loop
compensation by means of external resistors and
capacitors. The Error Amplifier output (the error voltage) is
then converted into a current (the Error Current) that is used
to program the required peak DMOS transistor current that
produces the desired output voltage. When the sum of the
sensed DMOS transistor current and the compensating
ramp exceed the Error Current signal, the latch is reset and
the DMOS transistor is turned off. Current comparison
around this loop takes place in less than 50ns, allowing for
excellent 250kHz converter operation. The latch can also be
reset by an under-voltage (V DD < 10.3V typical), over
temperature (TJ > +125°C typical) or a shutdown signal
externally applied at the Vc terminal. See Figure 36.
Note that if the error voltage (at the Vc pin) is less that
2.55V, then the output of the VOltage-te-Current Converter
will be held at zero. This condition will produce the minimum
possible pulse width, typically 150ns (100ns blanking pulse
plus 50ns delay). Error voltages lower than this 2.55V level
will not produce shorter pulse widths. Under very light loads
(when Vc goes below 1.5V), the Enable Comparator will
temporarily hold-off the PWM latch (and the DMOS transistor) until the Vc voltages rises above 1.5V. This low Vc
inhibit circuit results in a burst-mode of operation that maintains regulation under light or no loads.
During an over-current condition, the output of the Error
Amplifier will attempt to exceed the 7.0V threshold. At this
pOint, the Short-Circuit Comparator will pull down on this signal and induce a low-level oscillation about the threshold,
serving to clamp the peak error voltage. This clamping
action, in turn, will limit the peak current in the DMOS transistor, redUCing the duty ratio of the switch as the demand for
current continues to increase. This action, in conjunction
with the Thermal Monitor, serves to protect the IC from overcurrent (short-circuit) conditions.

impedance, ideally infinity. The amplifier gain is typically
50dB and is not significantly altered when operating into the
stages that follow within the IC. To minimize the output stage
idling current, while providing high peak currents to insure
rapid response to load and input transients, a class B type of
output stage was used in the amplifier. Placing a 100k
resistor from the amplifier output terminal, V c, to ground will
bias the output stage to an active state and still minimize
power consumption. in all cases, the resistor shunting the
transconductance amplifier output must be greater than
10kO to insure that the output will rise suffiCiently high to
obtain the maximum DMOS transistor drain current.
Start-Up Sequence
Upon initial power up of the HIP5061 in a typical application
circuit, the voltage at Vc will be zero, and the DMOS transistor will be off. When the voltage at VDD rises above the
10.3V typical threshold, the error amplifier output is enabled
and the Vc voltage begins to rise in response to the low voltage at the FB terminal. When the Vc voltage rises above
1.5V the DMOS transistor begins to switch at the minimum
duty cycle, and when it rises above 2.55V the duty cycle
begins to increase. The Vc voltage (and peak DMOS transistor current) will then continue to rise until the voltage loop
gains control and establishes regulation. Note that the rate
of rise in the Vc voltage can be controlled by an external soft
start circuit (See Soft Start Implementation).
if the Vc voltage is unrestricted in its rate of rise. then it will
typically rise quickly to its maximum (peak current) value,
causing the DMOS transistor to turn-on and stay on until it
reaches the peak current value. At this point, the DMOS
transistor begins switching, and the Vc voltage (and peak
DMOS transistor current) will drop down to the level commanded by the voltage loop.
Using the Shunt Regulator
The internal 14V shunt regulator in conjunction with an
external series resistor allows the IC to operate from quite
high input voltages, limited only by power dissipation in the
external resistor. When only higher voltages are available, a
bootstrap or other 12V auxiliary supply can be used to eliminate this dissipation. The series resistor should be chosen to
be as large as possible to reduce power dissipation at high
line, while ensuring adequate V DD voltage at low line. The
maximum value for this resistor, R, is given by:
R

Using the Transconductance Error Amplifier
A transconductance amplifier with a typical gm of 30mS is
used as the input gain stage where the power supply output
voltage is compared with the internally generated 5.1V
reference voltage. A PNP transistor input structure allows
this amplifier to accommodate large negative going transient
voltages without causing amplifier phase reversal, often
associated with PNP input structures. Negative transients up
to 5V applied to the input though at least 5.1 k will not result
in phase reversal. The amplifier output stage has the
customary drain to drain output to help improve the output

_ V I. MIN -10.5
MAX (0) 0.033

Where VI is the input voltage to the power supply. The value
chosen for this resistor must also result in a current, I. into
the V DD clamp that is less than 105mA when the input voltage is at its maximum:

7-65

(VI. MAX -13.3)

RMAX

HIP5061
TABLE 2. MINIMUM INDUCTANCE FOR STABLE CCM
OPERATION ABOVE 50% DUTY CYCLE

Inductor Selection
The selection of the energy storage inductor(s) !..sTOR br a DC to
DC converter has tremendous influence on the behavior of the
converter. It is particularly important in light of the high level of
integration (and necessarily few degrees of freedom) achieved in
the HIP5061. There are several factors influencing the selection
of this inductor. Rrst, the inductance of !..sTOR will determine the
basic mode of operation for the converter: continuous or
discontinuous current. In order to maximize the output power
for the given maximum controllable DMOS transistor current, a
converter may be designed to operate in continuous current
mode (CCM). However, this tends to require a larger inductor,
and br many converter topologies resutts in a feedback loop
tha is difficult to stabilize. For these and other reasons, the
inductor !..sTOR may be chosen so as to operate the converter in
discontinuous current mode (DCM). The relative mer~s of
CCM and DCM operation for various topologies and the
corresponding selection of LSTOR is well documented and will not
be covered here.
A second factor influencing the selection of LSTOR is the
stability requirement for current-mode control. This constraint is
only applicable for converters operating in CCM, since openloop instabilities of this type are not observed in converters
operating in DCM. For marginal stability, the compensating
ramp (internal to the HIP5061) must have a slope that is
greater than one-half the difference between the inductor
current's down slope and up slope. (To ensure stability for duty
ratios D > 0.8, the slope of the compensating ramp should be
equal to the inductor current downslope.) A generally accepted
goal is to set the slope of the compensating ramp to be at least
one-half of the inductor current down slope. Since there is no
external control over the internal compensating ramp, one must
be sure that the inductor is large enough so that the down slope
of the inductor current is not too large. Table 2 summarizes this
requirement for minimum inductance for several common
topologies.
A third constraint on the size of the inductor is one that is
common among current-mode controlled PWM converters,
and applies to both DCM and CCM operation. The stable
generation of the desired DMOS transistor pulse width
depends on the accurate comparison of the error signal and
the peak LSTOR (DMOS) transistor drain current. Thus, as
the peak LSTOR ripple current becomes smaller, immunity
from noise on the error signal is eventually reduced until the
pulse width can no longer be adequately controlled. For the
HIP5061, the inductor current ripple must be at least 200mA
peak to peak to ensure proper control of the DMOS
transistor current. This effectively establishes a maximum
value for the inductor LSTOR, so as to maintain at least
200mA of ripple. Note that under extremely light or no load
conditions, all converters will eventually operate in DCM,
and the 200mA requirement will eventually be violated.
Under these conditions, the HIP5061 will continue to
regulate, although the switching of the DMOS transistor will
be in a burst-mode. controlled bv the Licht Load
Comparator. (See Figure 2.)
-

CONVERTER TYPE

MINIMUM INDUCTANCE
Vo + Vo - VI. MIN

Boost

L=

SEPIC (Note 1)

Vo+Vo
Ll~
-->--Ll + L2 2MR, MIN

Cuk (Note 2)

Vo-Vo
L1L2
-->--Ll + L2 2MR, MIN

Flyback

Lp> Cpfvo+vo)
--Ns 2MR,MIN

Forward

(NS) (Vo+Vo)
L> --Np 2M R,MIN

2MR,MIN

NOTES:

1. Assumes that Ll and

~

are both CCM.

2. L =Inductance in Henrys, Vo =Output Voltage,
Vo =Diode Voltage Drop, VI =Input Voltage.
MR MIN = (~V~t)MIN =O.45A1IlS, Ll = Drain Inductor,
~,;. Secondary Inductor, Np =Primary Turns,
Ns =Secondary Turns
DMOS Transistor Turn-Off Snubber
In order to reduce diSSipation in the DMOS transistor due to
turn-off losses, the turn-off time has been minimized.
However, the rapid reduction of current that occurs in the
drain of the DMOS transistor can result in large transient
voltages being induced across any parasitic inductance in
the drain path. For this reason, it is important that such
parasitic inductance be reduced by good, high frequency
layout practices. Nevertheless, there are many instances
(e.g., transformer isolated topologies) in which voltages in
excess of 60V may be developed at the DMOS transistor
drain. In some cases, a simple R-C snubber may be added
to reduce the overshoot of the drain voltage to a safe level.

It is also possible that the large amount of ringing that can
occur at the DMOS transistor drain at turn-off will induce
noise in the IC. This noise may result in false triggering of
the PWM latch, particularly at high peak DMOS transistor
drain currents. Noise related instability can also be eliminated by the addition of a snubber, which will rapidly damp
out such turn-off ringing. Good layout practices will reduce
the need for such protective measures, and ensure that the
DMOS transistor is not overstressed.
Under-Voltage Lockout
The V DD input voltage is monitored by a comparator that
holds off the DMOS transistor gate drive signal when the
V DD voltage is less that about 10.3V. The typical O.SV hyster-

7-66

HIP5061
esis of this comparator is intended to reduce oscillation
when the voltage at Voo is in the vicinity of 10V. Note, however, that when an external series resistor is used to feed the
shunt regulator, the voltage drop across this resistor (which
sharply decreases when the IC shuts down), effectively
reduces the hysteresis. To reduce the tendency for oscillation in the vicinity of the 10V threshold, the impedance of the
source that feeds the DC to DC converter input should be
minimized. The addition of a capacitor (1I!F-471!F) at the
Voo terminal can also help to provide smooth turn-on or turnoff of the converter if the input supply rises or falls gradually
through the V DO Comparator threshold.
Peak Controllable DMOS Transistor Current
Figure 34 shows the guaranteed minimum, peak controllable
DMOS transistor current versus duty cycle. This peak current value is established by the current limit circuitry, which
effectively clamps the voltage at Ve (the error voltage) to
perform current limiting. Since the sensed DMOS transistor
current is summed with a compensating current ramp that
begins its rise 1.51!s after the initiation of a cycle, current limiting will begin to occur at a peak DMOS transistor current
that varies with the operating duty cycle. The highest current
limit threshold occurs for D<0.375, where no ramp is added
to the sensed DMOS transistor current. At higher operating
duty ratios, the onset of current limit will occur at increasingly
lower currents, due to the effect of adding the compensating
ramp to the sensed current. Note that this curve represents
guaranteed minimum values. The guaranteed maximum values are considerable higher, although they are still limited to
levels that protect the IC.

7

DMOS Transistor Turn-On Noise
Although the large DMOS transistor turn-on current spikes are
"blanked over" by the control circuit, it is important to minimize
these current spikes, Since they often result in voltage spikes
considerably below the device substrate that can activate parasitic devices within the IC. Such activation of parasitic
devices will often result in improper operation of the IC. An
external terminal labeled VG brings out the power supply to
the gate drive circuitry. This allows for the control of the peak
current delivered to the gate of the DMOS transistor, which in
turn establishes the turn-on speed. The VG pin may be externally bypassed for the fastest possible turn-on, or series resistance may be added with no bypassing capacitor to slow
down the turn-on of the DMOS transistor. Depending upon the
actual layout of the supply, it Is generally recommended that a
series resistor be added (100-1500) so that the DMOS transistor turn-on speed is reduced. By properly adjusting the
turn-on speed, undershoot can be avoided while turn-on
switching losses are kept to a minimum.
Soft Start Implementation
It is often desirable to allow the regulator to start up slowly,
Figure 35 shows one means of implementing this action. The
normally high output current from the HIP5061 transconductance amplifier (when VFB 0 and VREF 5.W) is directed to
an external capacitor through a diode. This slows down the
rate of rise of the voltage at the Vc terminal. After the regulator starts, the external capacitor is charged to V DO and is
effectively removed from the frequency compensation network by a reverse biased diode. To ensure rapid recycling of
the capacitor voltage with removal of power, a diode is placed
across the 100k0 resistor. Logic Shutdown Input (Ve Pin).

=

i:
;

=

,r-----r--:;.;:-;.:;-=-j-i-----,
,
:1DDkn
Va
,,
:2mA, TYP Veo
,
H-..:'i-_t-I VC ....- - - -..
,,,
GATE DRIVER
,,
,,,
,

,,,

r------r·-----------·-----·

DRAIN

'7--

SOFT START
NETWORK
0.06

0.375
DUTY CYCLE

HIP5061

SOURCE

1.0

FIGURE 34. PEAK DMOS TRANSISTOR DRAIN CURRENT V8
DUTY CYCLE

FIGURE 35. SOFT START CIRCUIT FOR THE HIP5061

When the DMOS transistor first turns ON there may be substantial current spikes exceeding the normal maximum peak
current established by the current control stages within the
IC. To prevent these spurious spikes from conveying erroneous information to the Current Comparator, a 100ns blanking
signal is applied to the current monitoring circuitry. Thus,
there is no peak current protection during the first 6% of the
duty cycle (see Figure 36).

The DC to DC converter may be shut down by returning the
Vc output terminal to ground. A sinking current greater than
4mA will insure that this output is pulled to ground. It must be
remembered that once switching operation ceases, the drain
of the DMOS transistor is open. When the supply is in the
Boost configuration, the output voltage is not zero but the input
voltage less diode and inductor voltage drops. If the SEPIC

7-67

HIPS061
topology is used, this is not the case. Shutting down the regulator via the Vc terminal will cut off the output. Figure 36 shows
two methods of shutting down the IC. In each case the current
sinking circuit must be able to sink at least 4mA, the maximum
current from the HIP5061 Vc terminal.

FROM CD4049UB

U
OFF

n
OFF

··
·.

~----------

DRAIN

Voo

>--+1--14m~A~Vc

.,,
,

r--------,
GATE DRIVER

-,

Fe

,

!

J!
:__________ J
~

ALTERNATE METHOD

,--_G.,N_D_ _.;;;H;;;.IP.;;.S06;;..;.;..1_SO_U_RC_E+--,
NOTE: FREQUENCY
COMPENSATION NETWORK
NOT SHOWN

'--_-+

All the capacitors shown with values of 111F or less are of the
multilayer ceramic type with the X7R dielectric material. This
material has a fairly flat voltage and temperature coefficient
that assures that the capacitance remains comparatively constant at extreme operating temperatures and voltages. The
multilayer construction allows for comparatively large values
with good volumetric efficiency and low inductance. Capacitors around the power input and output circuits should be
returned to the device TAB via a low inductance ground plane.
This TAB is internally connected to the DMOS transistor
source. The schematic diagram of Figure 38 was drawn with
the diagonal leads to show the critical paths for the various
high frequency elements. These short interconnects assure
the lowest inductance around the output power circuit.
Design of a 28V, 1.8A Boost Converter
Figure 38 shows the schematic diagram and a parts list of a
50W supply designed with the HIP5061. Table 3 tabulates
the performance of the power supply.
TABLE 3. TYPICAL LABORATORY PERFORMANCE OF
SOW, 28VI1.BA REGULATOR

FIGURE 36. TWO METHODS OF SHUTTING DOWN THE HIP5061

Input Voltage ............................. l1V to l6V

Mounting, Layout and Component
Selection

Una Regulation............................ 12mVN
Output Voltage ........•................... 28.0V
Load Regulation ........................... 64mVlA
Output Ripple, FL. ......................... 600mV pop
(20MHzBW)

The TO-220 package with its gullwing leads was designed to
be surface mounted. To aid in the external reduction of lead
length and hence inductance and resistance. the IC leads
were staggered. To keep the inductance and resistance of
the critical drain terminal as low as possible. it is suggested
that the PC trace to the DMOS transistor drain terminal be
made as wide as possible. The adjacent source terminal is
not recommended to be used and therefore allows the metal
to the drain terminal to be widened beyond the normal
widths for these terminals. Figure 37 illustrates these points.
One of the most important aspects to the proper application
of this device is high frequency bypassing. In a Boost converter. for example. there should be a low-inductance interconnect from the DMOS transistor drain. through the output
diode and capaCitors, and returning to the TAB (source) of
the HIP5061. Inductance in this line results in large transient
voltages on the DMOS transistor drain terminal which can
result in voltages above the maximum DMOS transistor
drain voltage rating.
IC SOLDERED TO PC BOARD
Voo PC METAL

~

Output Ripple, after Filter, FL ................. BOmV pop
(20MHzBW)
EffICiency: VI =11 V, IL =O.lBA ..••••..•...... 90%
VI = llV, IL = 1.8A •••••••••••••••• 89%
VI = 16V, IL = O.lBA ............... 73%
VI = 16V, 'L = 1.8A ................ 93%

Inductor Selection
In order to maximize the output power for the given maximum controllable DMOS transistor current. this converter
has been designed to operate in continuous current mode
(CCM). In this mode. the inductor value will generally be
large. resulting in a lower inductor ripple current and a lower
peak DMOS current. To ensure that the converter operates
in CCM over the usable range of input voltage and output
current. the value of L2 must be greater than the "critical
inductance." given by

~DER
DRAIN
PC METAL
FOR LOWER
INDUCTANCE

--~~:~
FORFB
ANDVe

= 39I1H
FIGURE 37. SHOWING WIDER PC BOARD METAL FOR
CRITICAL

7-68

HIP5061
D.C. Gain: 20dB-40dB
Pole at 88Hz-880Hz
LHP Zero at 1MHz
RHP Zero at 11.OkHz-ll OkHz
Double Pole at 80kHz (from filter)

where PO.MIN has been arbitrarily chosen as 5.SW. corresponding to an output current of 0.2A. and V D is the forward
voltage of CR1. Thus, for L2 > 3911H, the converter will be in
CCM for VI 11V to 1SV and IL 0.2A to 1.8A.

=

=

A second factor influencing the selection of L2 is the stability
requirement for current-mode control. Using the above
equation for LMIN for the Boost converter:
28+0.5-11
------------=

1911H

2 x (0.45xl0S A/S)

Thus. L2 must be at least 1911H to ensure good stability of
the current loop. and a choice of L2
40l1H satisfies this
requirement, while maintaining CCM operation over an
extremely wide load range.

=

The chosen core material for L2 is Kool Mu ferrous alloy powder from Magnetics. Inc. This material was chosen because of
its relatively low cost. while its losses due to AC flux are five to
ten times less than conventional powdered iron.

Loop Compensation
The control to output transfer function for this current-mode
boost converter has the following characteristics over the
specified load and line conditions:

To stabilize the voltage loop, it is necessary to establish the
unity gain crossover frequency well below the RHP zero, since
this zero introduces positive gain and negative phase. A crossover of 4kHz is fairly conservative. and is achieved by adding a
ll1F capacitor at the VC pin. which provides near infinite DC
gain, and about -5dB of gain at 4kHz. This results in a phase
margin of about 15° at full load. Note that R4 is required for
proper operation of the transconductance amplifier, since it is
prOviding bias current for the output stage as discussed under
Using the Transconductance Error Amplifier section.

Output FiHer Design
Inductor L3 was chosen with C11 to provide at least 15dB of
ripple attenuation at the switching frequency. The corner frequency (80kHz) of this filter is well above the crossover frequency of the voltage loop (4kHz). and has no effect on
stability. This secondary LC filter was used to reduce output
ripple instead of a lower-cost, high-value. low ESR aluminum electrolytic capacitor to demonstrate the reduction in
volume possible at this switching frequency. A lower cost
solution could achieve the same output ripple by replacing
C9.10,12 and L3 with one or two large capacitors (e.g.,

,;......:.:.:.: ................. ;
INPUT
l1VDC -16VDC

: L3, 4~H

CRl

RA

......... ---,

20n,lW

C5

1

Rll
7.sn, 112W

RS

7 10n,l/4W

6

5

Rl
10K.
1%

~~:'~V~D~D---------V~G------~-D-R-A-IN--~

OUTPUT
28VDC
OA-l.8A
OPTIONAL
FILTER

j

GATE DRIVERS,
CONTROL CIRCUITRY
AND LOGIC

HIP5061

RA
R1
R2
R4
RS
Rll

PARTS LIST
200. lW, Wlrebound - Dale RWR81 S20ROFR or Equivalent
10K,1%
2.2K,1%
100K. 1/4W
100. 1/4W
7.So, 112W, Carbon - Allen Bradley EB7SGS

Cl,

ca. C4 and C11

1j1F, SOY. Ceramic - Murata Erie RPE113X7R1050SOY
4711F, SOY, Alum - United Chemicon SlSD476MOSO
6.BIIF, SOY. Ceramin - Mallory M60u6rBMSO
lnF, 100Y. Ceramin - Kemet C322Cl 02K1 GSCA
Schottky Diode - Motorola MBRD360
L2 40IIH at SA, Pulse Engineering PE - S3571
L3 411H atS.SA, Pulse Engineering PE - S3S70

CS and C12
C9 and C10
C13
CRl

FIGURE 38. HIP5061 SOW, 28Y BOOST REGULATOR SCHEMATIC AND PARTS LtST

7-S9

HIP5061
39011F. SOV, type 6730 from United Chemicon}. This change , Snubber Network
would also greatly improve load transient response, proA snubber network has been added to reduce the ringing at
vided that the loop compensation is appropriately adjusted.
the drain due to parasitic layout inductances. In particular,
Note that in the circuit of Figure 38, capacitor C12 does not
under severe load transient conditions, this snubber is necsignificantly affect output ripple, but is necessary to absorb
essary to protect the drain from voltage breakdown. A secthe energy stored in L2 during severe load transients. In the
ond benefit of reducing the noise and ringing at the drain is
event of a step change in load from 1.8A to OA, C12 will limit
that it reduces the tendency of the HIPS061 to exhibit noisethe output voltage overshoot to about 10V and protect the
related instabilities at high peak DMOS transistor currents
drain of the DMOS transistor from overvoltage breakdown.
(4A-6A). A value of l000pF was chosen for C13, since this
is adequate to dampen the ringing associated with the
Input and VDD Rlters
200pF drain capaCitance of the DMOS transistor. Rll was
Since the boost converter is current fed, input filtering is easchosen as 7.S0 to provide the best possible dampening
ily achieved by the addition of a small capacitor C4. This
given the parasitic inductances that exist in the layout. Note
capacitor provides nearly 40dB of ripple current attenuation
that this snubber may not be necessary if the layout of the
for the input, reducing the AC ripple current flowing into the
circuit were improved, or if the application did not push the
converter to less than 200mA.
envelope of DMOS transistor current.
RS and C3 have been chosen to provide good filtering of
Other Power Supply Topologies
high frequency pulse currents. RS provides isolation
between the analog VDD pin and the high pulse current VG Figure 39 shows three other topologies besides the Boost that
pin, and also provides a means to control the turn-on speed may be implemented with the grounded source DMOS power
of the DMOS transistor by limiting the peak current available transistor used in the HIP5061. Other, more complex power
to the internal gate drive circuitry. Thus the output transition supply topologies such as the Quadratic are also possible to
time may be increased to prevent drain voltage undershoot. implement with the HIPS061. One noteworthy feature of the
Undershoot may result in activation of device parasitics and Quadratic topology as shown in Figure 41 is the wide input to
improper circuit operation. For the two-layer board used for output voltage transfer ratio possible with reasonable duty
this design, C3 could be reduced to 0.2211F without affecting cycles. Duty cycles that are not near the Minimum DMOS trancircuit operation. CS was added to provide low-frequency fil- sistor ·ON" TlITle specification shown in the Data Sheet. This
tering at the V DD pin. This reduces the tendency of the circuit permits easier control at the extremes of the transfer ratios.
to oscillate off and on when the voltage at the V DD pin s in Compensating the control loop can pose challenges because
the vicinity of the under voltage lockout threshold, typically of the wider changes in the transfer ratio and hence loop gain.
10V, and the output power is high (30W - SOW).
The SEPIC tOpoiogylll,13) does not have quite as wide inputShunt Regulator Resistor
output voltage range with reasonably controlled duty cycles
as the Quadratic converter mentioned above, but it does
Resistor RA has been chosen to be as large as possible to
allow both voltage increase and decrease with the same cirreduce power dissipation at high line, while ensuring adecuit. This is particularly advantageous when a power supply
quate VDD voltage at low line. Note that the guaranteed
is being used in the stabilizing mode and isolation is not
range of input voltage for proper operation of this circuit is
required. For example, in an application where a regulated
11.2V to lS.3VDC, based upon data sheet limits. However,
24V output is required and the input voltage varies ±20%
the circuit was found to perform well at room temperature for
from a nominal 24V. The SEPIC supply can provide both the
VI 10.7VDC to 17VDC. The maximum value for RA is
Boost and Buck functions.

=

R MAX

=

V I• MIN -10.S
0.033

= 210

RA has been chosen as 200, which results in a current into
the Voo clamp that is less than 10SmA when the input voltage is at its maximum:

I MAX =

(VI MAX- 13.3 )
'20.0

Another outstanding advantage of the SEPIC topology is its
fauR isolation of the input and output voltage. All energy is
transferred via the coupling capacitor. Moreover if the clock
stops, voltage transfer stops. If the switching transistor shorts
there is no output. The Buck circuit will apply full input voltage
to the load with a shorted transistor. This is reason that the
SEPIC topology is referred to as the fail-safe Buck.

100mA< 10SmA

7-70

HIP5061
=
+

+

+

+
VOUT

II
v"

Vo

FB

----r-..I

t-+----I--t

SOURCE
Vo

.....

.....

....,~

GND

~-COU;UNG-·
:
MEANS
:
• ISOLATED'
:,__ORDIRECT
________ J•

SOURCE

FIGURE 39A. SEPIC (FAIL-SAFE BUCK) CONVERTER

.."

;;:;::;:;.

+
Voo

.

v

Vo

DRAIN

GATE DRIVER
AND CONTROL
Vo
CIRCUITRY
HIP5061
GND

FIGURE 40. FLYBACK CONVERTER

~

~

1

J

;;:;::;:;.

>r

FB

It should be noted that when the Cuk topology is implemented, a transistor current source is used to convert the
negative output voltage of the Cuk converter to a current that
is level shifted to the FB terminal on the HIP5061.

VOUT

Two other useful topologies that may be used are the Forward and the Flyback as shown in Figure 40 and Figure 41.
As shown. they may either be operated as an isolated or
non-isolated converter.

SOURCE

...L
FIGURE 39B. CUK CONVERTER

+

+

+

II
Y'N

FB 1-4---1--+

FIGURE 39C. QUADRATIC CONVERTER
FIGURE 41. FORWARD CONVERTER

FIGURE 39. THREE OTHER TOPOLOGIES

7-71

HIP5061
Both the SEPIC and the Boost topologies may be operated
at high voltages with the addition of a high voltage cascode .
Figure 42 shows the Cascode SEPIC converter that is
essentially limited by the selection of the external power
transistor. The burden of voltage, and power Is placed upon
the external transistor. The HIP5061 still performs the drain
current sampling and the control function is the same as the
non cascode configuration.

References
[1] Cassani, John C.; Hurd. Jonathan J. and Thomas, David
R., Wittlinger, H.A.; Hodgins, Robert G.; Sophisticated
Contro/IC Enhances 1MHz Current Controlled Regulator
Performance, High Frequency Power Conversion (HFPC)
conference proceedings, May 1992, pp. 167-173

[2] Smith, Craig D. and Cassani, Distributed Power Systems Via
ASICs Using SMT; Surface Mount Technology, October 1990

=
+

+
160V
VIN

[3] Maksimovic and Cuk, Switching Converters With Wide DC
Conversion Range, High Frequency Power Conversion
(HFPC) conference record, May 1989

VOUT

....i--=====::!
Vc

II

[6] Sokal and Sokal, Class E - A New Class of High EffiCiency
Tuned Single-Ended Switching Power Amplifiers. IEEE
Journal of Solid-State Circuits. June 1975. pp. 168-176

L-_,..........

GND

[7] Mansmann. Jeff; Shafer. Peter and Wildi, Eric, Maximizing
the Impact of Power ICs Via a Time-to-Market CAD Driven
Power ASIC Strategy. Applied Power and Electronics
Conference and Exposition (APEC) proceedings, February 1992. pp. 23-27

SOURCE

[8] Severns and Bloom. Modem DC-to-DC Switchmode
Power Converter Circuits, Van Nostrand Reinhold, 1985

FIGURE 42. OFF LINE CASCODE SEPIC

Figure 43 shows the voltage transfer as a function of duty
cycle for the power supply topologies discussed.

I

~5 1

F

-I

BUCK-BOVT, CUK AND SEPIC
1
.01(1-0)
~

I

~

>

"
I.JJII"

0.1

0.01

II
o

1/

M .. 1/(1 - D) BOOST

::I!

and Design. Marcel Dekker, In., 1984
[10] Pressman, A., Switching and Linear Power Supply.
Power Converter Design, Hayden Book Co., 1977

[12] Oarke, P., A New Switched-Mode Power Conversion
Topology Provides Inherently Stable Response. POWERCON 10 proceedings. March 1983, pp. E2-1 through E2-7
[13] Harris Application Notes AN9208 and AN9212.1

BuJ~
M=D

~

QUAD~~TI~11

' " M.02t1-D2

1/
~

[9] Sum, K, Switch Mode Power Conversion· Basic Theory

[11] Massey, R.P. and Snyder, E.C., High Voltage SingleEnded DC-DC Converter, IEEE Power Electronics Specialists Conference (PESC) record, 1977, pp. 156-159

100

10

[5] Maksimovic and Cuk, General Properties and Synthesis of
PWM DC-to-DC Converters, IEEE Power Electronics
Specialists Conference (PESC) record, June 1989

u

u

~

u

~

u

u

U

DUTY CYCLE (D)

FIGURE 43. VOLTAGE TRANSFER AS A FUNCTION OF DUTY
CYCLE FOR VARIOUS TOPOLOGIES

7-72

HIP5062
Power Control IC
Single Chip Dual Switching Power Supply

April 1994

Features

Description

• Two Current Mode Control Regulators

The HIP5062 is a complete power control IC, incorporating two high
power DMOS transistors, CMOS logic and two low level analog control
circuits on the same Intelligent Power IC. Both the standard "Boost" and
the "SEPIC" (Single· Ended Primary Inductance Converter) power supply
topologies are easily implemented with this single control IC.

• Two 60V, SA On-chip DMOS Transistors
• Thermal Protection
• Over-Voltage Protection
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
• On-Chip Reference Voltage - S.1V
• Output Rise and Fall Times - 3ns
• Designed for 26V to 42V Operation

Applications

Special power transistor current sensing circuitry is incorporated that
minimizes losses due to the monitoring circuitry. Moreover, over-temper·
ature and over-voltage detection circuitry is incorporated within the IC to
monitor the chip temperature and the actual power supply output voltage.
These circuits can disable the drive to the power transistor to protect
both the transistor and, most importantly, the load from over-voltage.
As a result of the power DMOS transistor's current and voltage capability
(5A and 60V), multiple output power supplies with total output power
capability up to 100W are possible.

Ordering Information

• Single Chip Power Supplies
TEMPERATURE RANGE

PACKAGE

• Distributed Power Supplies

HIPS062DY

OOC 10 +8SoC

40 Pad Chip

• Multiple Output Converters

HIPS062DW

OOClo +8SoC

Wafer

• Current Mode PWM Applications

PART NUMBER

Chip

V+(40)
TMON (39)
IRFI2 (38)
IRF02(37)
VINP (36)
AGND(35)
DGND(34)
XCKS (33)
CKIN (32)
IRFll (31)
IRFOI (30)
VCMPI (29)
VTCN (28)

(8) VOOP2
(V) VCMP2
(10) PSOK
(ll)VREG2
(12) FLTN
(13) PSEN
(14)SHRT
(15)SLRN
(16)SFST
(17)VDDO
(18)VOOA
(lV)VREGI
(20)VOOPI

175 mils x 175 mils (4.44mm x 4.44mm)
CAUTION: These devices are sensitive to electroslatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-73

File Number

3208.1

HIP5062

Simplified Block Diagram
v.. _ - - - - - - - - - - . . . ,
S"H

1.O!1F

11!1H

VOOD

12V

15

33

JtI:

"F

681

VINP 1-1(--+

TYPICAL SEPIC CONFIGURATION

7-74

S.1V

Specifications HIP5062
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V+ ..•.•..•.••........•••••. -o.3V to 42V
DMOS Drain Voltage •••.•...•.•.•••••.•.•.•••• -o.3V to 60V
DMOS Drain Current • . . . • • . . • . . . • • • • . . • . • • • • • • • . • . • • • lOA
DC Logic Supply •.•...•..•.................•.. -o.3V to 16V
Output Voltage, Logic Outputs ......•••.....•.••• -o.3V to 16V
Input Voltage, Analog and Logic ...•.•••...••••••. -o.3V to 16V
Operating Junction Temperature Range.•..••..... OOC to +1100 C
Storage Temperature Range ......•...••..... -55°C to +150°C

Thermal Resistance
9JC
(Solder Mounted to . • • • • • • • • • . • • . • • . • • . . • • .• 3°CIW Max
0.050" thick Copper Heat Sink)
Maximum Junction Temperature .•.................... +110°C
(Controlled By Thermal Shutdown Circuit)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings'may cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other conditions above those indicated in the operaUonaf sections of this specificaUon is not implied.

Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = OOC to +1100C; Unless Otherwise Specified
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DEVICE PARAMETERS
1+
VOOA

Supply Current

V+ = 42V, PSEN = 12V

-

24.7

30

mA

Internal Regulator Output
Voltage

V+ = 30V to 42V, lOUT = OrnA

11.7

V

V+ = 30V to 42V, lOUT = 30rnA

11.5

-

13.3
13.3

V

SLRN = 12V, lOUT = OrnA

11.5

-

13.3

V

VINP

Reference Voltage

VDDA = SLRN = 12V, IvlNP = OrnA

5.01

5.1

5.19

V

RVlNP

VINP Resistance

VINP=O

-

900

-

n

Input Offset Voltage
(REG - VINP)

IVCMP=OrnA

-

-

10

mV

RIN VREG

Input ReSistance to GND

VREG= 5.1V

39

-

85

kn

gm (VREG)

VREG Transconductance
(IvcMP/(VREG - VINP)

VCMP = IV to BV, SFST = llV

15

30

50

mS

gm (SFST)

SFST Transconductance
IvcMp/(VREG - SFST)

VSFST <4.9V

O.B

-

6

mS

IVCMP

Maximum Source Current

VREG = 4.95V, VCMP = BV

-2.5

-

-0.75

rnA

Maximum Sink Current

VREG = 5.25V, VCMP = 0.4V

0.75

OVTH

Over-Voltage Threshold

Voltage at VREG for FLTN to be
latched

6.05

-

Internal Clock Frequency

XCKS = 12V, Vooo = 12V

0.9

ERROR AMPLIFIERS
IVIOI

2.5

rnA

6.5

V

1.0

1.1

MHz

33

-

66

%Vooo

CLOCK
fq
VTHCKIN

External Clock Input Threshold
Voltages

DMOS TRANSISTORS
rOS(on)
loss

Drain-Source On-State
Resistance

I Drain = 2.5A, Vooo = 11 V,
TJ=+25OC

-

-

0.22

n

Drain-Source Leakage Current

Drain to Source Voltage = 60V

-

1

100

IIA

CURRENT CONTROLED PWM

7-75

Specifications HIP5062
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = O"C to +1100C; Unless Otherwise Specified (Continued)
SYMBOL

PARAMETER

IVlolVCMP

Buffer Offset Voltage (VCOMP VIFRO)

TEST CONDITIONS
IFRO = OmA to -SmA,
VTCN = 0.2V to 7.6V,
VCMP2 = 0.2V to 7.6V

MtN

TYP

MAX

UNITS

-

-

125

mV

VTHIFRO

Voltage at IRFO that disables
PWM. This is due to low load
current

116

-

250

mV

ITHIFRO

Voltage at IRFO to enable SHRT
output current This is due to
Regulator Over Current Conditions

6.85

-

7.65

V

ISHRT

SHRT Output Current, During
Over-Current

VIRFO =7.7V

-75

-

-33

IIA

VTHSHRT

Threshold voltage on SHRT to
set FLTN latch

Vooo= llV

-

5

-

V

IGAIN

IpEAK (DMOSoRAIN)/IIRFI

41 (DMOSoRAIN)/4t = 1Alms

2.0

-

3.2

AlmA

RIRFI

IRFI Resistance to GND

IIRFI =2mA

150

-

360

(1

Current Comparator Response
Time (Note 1)

41 (DMOS oRAIN)/4t > lA1I1S

-

30

-

ns

~s

MCPW

Minimum Controllable Pulse
Width (Note 1)

25

50

100

ns

MCPI

Minimum Controllable DMOS
Peak Current (Note 1)

125

250

500

mA

Rising V+ Power-On Reset
Voltage

23

-

26.3

V

Falling V+ Power-Off Set
Voltage

-

IS

-

V

V+ Power-On Hysteresis

9.5

-

11.8

V

3.6

-

6.5

V

-

12

-

KO

-1.5

-1.0

-0.65

IIA

START-UP
V+

VTH PSEN

Voltage at PSEN to Enable
Supply

Vooo = ltv

rpSEN

Internal Pull-Up Resistance, to
Vooo

ISFST

Soft-Start Charging Current

VSFST = OV to llV

IpSOK

PSOK High-State Leakage
Current

SFST = ltv, PSOK = 12V

-I

-

I

IIA

VPSOK

PSOK Low-State Voltage

SFST = OV, IpSOK = lmA

-

0.4

V

PSOK Threshold, Rising VSFST

Vooo=IIV

8.1

-

9.9

V

TMON=OV

105

-

135

°C

VTHSFST

THERMAL MONITOR
TEMP

Substrate Temperature for
Thermal Monitor to Trip (Note 1)

NOTE:
1. Determined by design, not a measured parameter.

7-76

HIP5062
Pin Descriptions
PAD NUMBER

DESIGNATION

DESCRIPTION

1,4,7

S2

Source pads for the channel 2 regulator.

2,3,5,6

02

Drain pads for the channel 2 regulator.

8

VOOP2

This pad Is the power Input for the channel 2 DMOS gate driver and also Is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a O. ll1F chip capacitor placed close to this pad and the DMOS source pads.

9

VCMP2

Output of the second channel transconductance amplifier. This node is used for both gain and
frequency compensation of the loop.

10

PSOK

11

VREG2

12

FLTN

This Is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are usefUl in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current Is experienced. V+ must be powered down to reset.

13

PSEN

This terminal is provided to activate the converter. When the input is low, the DMOS drivers are
disabled. There Is an Internal 12K pull-up resistor on this terminal.

14

SHRT

501lA is internally applied to this node when there is an over-current condition.

15

SLRN

Control input to intemal regulator that Is used during the 'start-up' of the supply. In normal operation this terminal starts at OV and shuts down the Internal regulator at approximately 9V. This
pad is usually connected to SFST, pad 16.

16

SFST

Controls the rate of rise of both output voltages. Time is determined by an internal lIlA current
source and an external capacitor.

17

Vooo

Voltage input for the chip's digital circuits. This pad also allows decoupling of this supply.

18

VOOA

This Is the analog supply and Internal12V regulator output usually used only during the start-up
sequence. The internal regulator reduced to a nominal9.2V when SLRN is returned to 12V. Output current capability Is 30mA at both voltages.

19

VREGl

Input to channel one transconductance error amplifier. The other, common input for both amplifiers is VINP, pad 36.

20

VOOP1

This pad is the power input for the channell DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a O.lI1F chip capacitor placed close to this pad and the DMOS source pads.

22,23,25,26

01

Drain pads for the channel 1 regulator.

21,24,27

Sl

Source pads for the channell regulator.

28

VTCN

Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP 1,
pad 29.

29

VCMPl

Output of the first channel transconductance amplifier. This node Is used for both gain and frequency compensation of the loop.

30

IRFOl

A resistor placed between this pad and IRFll converts the VCMPl signal to a current for the current sense comparator. The rnaxlmum current is set by the value of the resistor, according to the
equation: IpEAK = 161R. Where R is the value of the extemal resistor in KO and must be greater
than 1.5KO but less than 10KO. For example, if the resistor chosen is 1.8K, the peak current will
be 8.SA. This assumes VCMPI Is 7.3V. Maximum output current should be kept below lOA.

This pad provides delayed positive Indication when both supplies are enabled.
Input to the transconductance error amplifier. The other common input for both amplifiers Is
VINP, Pad 36.

7-77

HIP5062
Pin Descriptions (Continued)
PAD NUMBER

DESIGNATION

31

IRFI1

SeeIRF01.

32

CKIN

Clock input when XCKS Is grounded.

33

XCKS

Grounding this terminal provides for the application of an external clock to CKIN input terminal.
For normal intemal clock operation, this terminal may be left floating or returned to 12V. There
Is an internal 30K pull-up resistor on this terminal.

34

DGND

Ground of the DMOS gate drivers. This pad Is used for bypassing.

35

AGND

Analog ground.

DESCRIPTION

36

VINP

Internal 5.1 V reference. This point Is usually bypassed.

37

IRF02

A resistor placed between this pad and IRFI2 converts the VCMP2 signal to a current for the current sense comparator. The maximum current set by the value of the resistor, according to the
equation: IpEAK =161R. Where R Is the value of the extemal resistor in Kn and must be greater
than 1.5Kn but less than 10Kn. For example, if the resistor chosen is 1.8K, the peak current will
be 8.SA. This assumes VCMP2 is 7.3V. Maximum output current should be kept beiow lOA.

38

IRFI2

SeeIRF02.

39

TMON

this Is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to VODA or 12V the function Is disabled. Returning this pad to ground will put
the IC into the thermal shutdown stete. Thermal shutdown occurs at a nominal junction temperature or +1200C. this terminal is normally retumed to ground.

40

V+

this is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.1 jlF capacitor.

7-78

HIP5062

Functional Block Diagram

- ..····..
r---~~

······~1:

,,,
,
.-----i-I:, VODP1
,

JiB
,,
,,
,
,,,
,,
,,
,

IVRE~n,,
,

,,

~---

----.---------_ ...... _- ... ------ _...... _......

E1

7-79

HIP5063
Power Control IC
Single Chip Power Supply

April 1994

Features

Description

• Single Chip Current Mode ControllC

The HIP5063 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC.

• 60V, lOA On·chlp DMOS Transistor
• Thermal Protection

This IC allows the user maximum flexibility in implementing
high frequency current controlled power supplies and other
power sources.

• 1MHz Operation. External Clock
• Output Rise and Fall Times - 3ns
• Simple Implementation of Hlgh·Speed Current Mode
Controlled Regulators and Power Amplifiers
• Designed for 10V to 45V Operation

Special power transistor current sensing circuitry is incorpo'
rated that minimizes losses due to the monitoring circuitry.
Over·temperature detection circuitry is incorporated within
the IC to monitor the chip temperature.
As a result of the power DMOS transistor's current and volt·
age capability (lOA and 60V) , power supplies with output
power capability up to 100 watts are possible.

Applications
• Single Chip Power Supplies
• Current Mode PWM Applications

Ordering Information

• Distributed Power Supplies
• Multiple Output Converters

PART NUMBER

TEMPERATURE RANGE

PACKAGE

• Wldeband Power Amplifiers for Motor
Control

HIP5063DY

O"C to +85°C

21 Pad Chip

HIP5063DW

O"C to +85°C

Wafer

Chip

1:t-l:afi::::,...tr1j~1

(12) VOOP

Voop (21)

Q

NOTE: Unused pads are for trim and test.
122 mils x 126 mils (3.1 mm x 3.2mm)

CAUTION: These devices are sensHive to electrostatic discharge. Users should follow proper I.e. Handling Procedures.
Copyright © Harris Corporation 1994

7·80

File Number

3209.1

HIP5063
Simplified Block Diagram
0.66111'

12V o-~--~--~~--+-----,
5.1V

OUTPUT

0.88111'
S

COOL
AGND OGND

IRR

I R F O t - - - -....

TYPICAL SEPIC APPLICATION CONFIGURATION

Functional Block Diagram

(/)

Cis!!!
a:...1

08:

S~
~a:

CJW

W;::

a:O
Go

.

CONTROL
BLANKING
LOGIC

~------~~-~---~IRR

EXTERNAL CURRENT SCAUNG RESISTOR
IpEAKlDMOS DRAIN CURRENT). 4500 x IREF (mAl

7-81

Specifications HIP5063
Absolute Maximum Ratings

Thermal Information

DMOS Drain Voltage •••••.•••••••••••••..••..• -o.3V to SOV
DMOS Drain Current •••••••••••••••.••••.•••..••••••• 20A
DC Logic Supply •••••••••.•••••••••.••••.•••.• -o.3V to 16V
Output Voltage, Logic Outputs ••••..••.••••••••.• -o.3V to 16V
Input Voltage, Analog and Logic ••...••...•.•••..• -o.3V to 16V
Operating Junction Temperature Range ••......•.• 0oC to +110oC
Storage Temperature Range •..•••.••••.•.••• -55°C to + 150°C

Thermal Resistance
aJC
(Solder Mounted to . • • • • • • • • . • • • • • • • . • . • . . .. 3°CIW Max
0.050" Thick Copper Heat Sink)
Maximum Junction Temperature ..••••••••..•......... +11 O°C
(Controlled By Thermal Shutdown Circuit)

CAUTION: StressBS above those Usted In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only raUng and operation
of the device at thBSe or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications VOOA = vooo = voop = 12V, TJ = OOC to +110oC; Unless Otherwise Specified
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

External Clock Input = 1MHz

-

14

-

mA

DEVICE PARAMETERS
1+

Supply Current

DMOS TRANSISTORS
roS(on)

Drain-Source On-State Resistance

I Drain = SA, TJ = +25°C

-

-

0.13

Q

loss

Drain-Source Leakage Current

Drain to Source Voltage = sov

-

1

100

IlA

Buffer Offset Voltage
(VCMP - VIRFO)

IRFO = OmA to -5mA,
VCMP = 0.2V to 7.6V

-

-

125

mV

ICAIN

IpEAK (DMOSORAlN)/IIRFI

dI (DMOSORAlN)1At = 1Alms

3.B

-

4.9

AlmA

RIRFI

IRFI Resistance to GND

IRFI=2mA

150

-

360

Q

Current Comparator Response
Time (Note 1)

AI (DMOSORAIN)/At> lA1ms

-

30

-

ns

CURRENT CONTROLLED PWM
IVIOI
VCMP

IRs
MCPW

Minimum Controllable Pulse
Width (Note 1)

25

50

100

ns

MCPI

Minimum Controllable DMOS
Peak Current (Note 1)

200

400

BOO

mA

VTHCLCK

CLCK Input Threshold Voltage

4

-

B

V

VTH FLLN

FLLN Input Threshold Vottage

4

-

B

V

VFLLN=OV

-70

-50

-30

IlA

Substrate Temperature for
Thermal Monitor to Trip (Note 1)

TMON pin open

105

-

135

°C

COOL Leakage Current

VCOOL = 12V

-

-

1

IlA

COOL Low-State Voltag~

ICOOL = 2mA, TJ > +125OC

-

-

0.4

V

CLOCK

IFLLN

FLLN Pull-Up Current

THERMAL MONITOR
TEMP

ILEAKCOOL
VCOOL

1. Determined by design, not a measured parameter.

7-82

HIP5063
Pin Descriptions
PAD NUMBER

DESIGNATION

DESCRIPTION

1

VCMP

This is the input terminal from an extemal error amplifier. A MOS input voltage follower buffers
this terminal. The buffer output is the IRFO terminal. The extemal error amplifier may be either
an operational amplifier or a transconductance amplifier like the CA30BO. This node may be used
for both gain and frequency compensation of the control loop.

2

VODA

This Is the analog supply Input An external12V supply is required.

3

Vooo

Voltage input for the chip's digital circuits.

4

FLLN

One pad of two clocking terminals. This terminal has an extemal 50jJA pull-up current that allows
the terminal to be floated or be left open. With FLLN high, (open or tied to Vooo), the ON cycle
will start wiith the falling edge of the CLCK input With FLLN low or grounded, the DMOS ON
cycle will start on the rising edge of the CLCK input

5

CLCK

The other clock input pad. An external clock is applied to this terminal. This terminal has no pullup current or resistance. See FLLN above for phasing information.

6

COOL

Over-temperature indication is provided at this pad. When the chip temperature is below the thermal threshold, the open drain DMOS transistor is in the high impedance state. When the thermal
threshold is exceeded, COOL is held low.

7

TMON

This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to VODA or 12V the function is disabled. Returning this pad to ground will enable
the thermal monitor function. Thermal threshold occurs at a nominal Junction temperature of
+125°C.

B

IRFO

A resistor placed between this pad and IRFI converts the VCMP signal to a reference current for
the current sense comparator. The cycle by cycle peak current is set by the value to this resistor
according the the equation: IPEAK = 4500 x VCMP/R. Where IpEAK Is in amperes and R is the
value of the external resistor In ohms. A maximum VCMP of BV and a resistor of lBOOn will keep
the drain current below the absolute maximum specification of 20A.
SeeIRFO.

9

IRFI

10

AGND

11

Analog ground.

DGND

Digital ground.

12 &21

Voop

These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a O.lj!F chip capacitor placed close to this pad and the DMOS
source pads.

13,15, 17, 19

S

Source pads of the DMOS power transistor.

14,16,1B,20

0

Drain pads of the OMOS power transistor.

i
I

7-83

HIP5500
High Voltage Ie
Half Bridge Gate Driver

April 1994

Features

Description

• 500V Maximum Rating

The HIP5500. a high voltage integrated circuit (HVIC) halfbridge gate driver for standard power MOSFETs. IGBTs. and
the new Harris Buffered MOSFET (RFV10N50BE). can be
employed in a wide variety of switching regulator circuits.

• 2A Peak Gate Drive
• Ability to Interface and Drive N-Channel Power
Devices With Complimentary Outputs For Buffered
FETs
• Fault Output, Overcurrent Detection and Undervoltage
Holdoff
• Over 600kHz Sawtooth Oscillator Frequency
• Adjustable Deadtime Control
• Soft-Start capability
• Low Current Standby State
• Sleep Mode Reduces Bias Current When Not Enabled

Applications
• Switching and Distributed Power Supplies

The HIP5500 incorporates a precision oscillator. adjustable
using an external resistor and capacitor. The resistor sets
the capacitor charging current and the capacitor sets the
integration time of a triangle wave. Another resistor connected to the DIS pin adjusts the dead-time and can be tailored to the application. The oscillator switches at twice the
output waveform fundamental frequency. The result is an
output waveform whose positive and negative half-cycles are
near perfect balance (volt-second equalization).
Short-Detect (SO) and Soft-Start (SS) inputs provide alternative means for limiting and regulating respectively the
half-bridge output voltage. A capacitor on the SS input will
begin charging up once the EN input is made high and
causes the duty cycle of each half-cycle to "ramp" the duty
cycle of the output waveform.

• Electronic Lighting Supplies

Ordering Information
PART
NUMBER

The HIP5500 combines the functionality and flexibility of a
PWM IC with the convenience of a high voltage half-bridge
driver optimized for power supply inverters. It can be used
either open-loop or in closed-loop fashion using the SS input
for controlling the output waveform duty-cycle.

TEMPERATURE
RANGE

PACKAGE

HIP5500IP

-40"C to +85°C

20 Lead Plasijc DIP

HIP5500lB

-4O"C to +85°C

20 Lead Plastic
SOIC(W)

The SO input can sense a signal proportional to current. providing a means of shortening the conduction periods below
that imposed by the SS input.
Other circuits within the HIP5500 "match" upper and lower
turn-on and turn-off propagation times in order to minimize
flux imbalances when priving output transformer loads.

Pinout
HIP5500 (POIP, SOIC)
TOP VIEW

CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-84

File Number

3210.2

HIP5500
Typical Application Block Diagram
r -______________________

~~~A~~~~~FO~E:.UE~

I~'"
HO - -......--I,,~

OSC

m
SD
EN
DIS
CT

+ SOOVDC

Vee

15VDC

+

iiO-1

HO

iiO
BUFFERED
FEr.

VB
Vs

LO

m

ro
BUFFERED
FEr.

'.:,3

[0-1

Functional Block Diagram

m

~O

__________

~

SD~----------~~--------------~--~

Lvcc
VB

(/)

UJ!:!:!

a::~
ea-

:s~
~a::

CJW
OSC

w;=
a:: 0
a-

0----------< J----...,
HO

iiO
Vs

LO

m
SS ~-+--_1----_L;>--~\-----------~~

r

GND

EN

7·85

Specifications HIP5500
Absolute Maximum Ratings

Thermal Information

Offset Supply Voltage. Vs •••.•..••••••..•••..•. .ves to +500V
Floating Supply Voltage (VB to Vsl ••..•.•••••.••• -o.3V to +18V
High Side Channel Output Voltage, VHO • VNHO •.• Vs-o.5 to VB+O.5
Fixed Supply Voltage. Vee ••.••••.••••.•.••.••• -o.5V to +18V
Low Side Channel Output Voltage •••.•.•••.• -0.5V to Vee +O.5V
All Other Pin Voltages
(SO, Rr. CT. DIS. SS. EN and FLT) •.•...••. -o.5V to Vee +O.5V
Storage Temperature Range ••..••••...•••••• -40"C to +15O"C
Junction Temperature. . • • • . • • . . • • • • . • • • • • • . . • • • • • • . +125°C
Lead Temperature (Soldering lOs) ••••••••••.••••.•••• +3OQOC
(SOIC - Lead Tips Only)
, Offset Supply Maximum dv/dt, dVsId! ................•. 50Vlns
, ESD Classification •..••••.....•••..•.••••.••••••.. Class 1

Thermal Resistance
OJA
Plastic DIP Package •••••.•••••••.•••••.•.•.••• 75°CIW
Plastic SOIC Package •••••.•••..•.•••...••••... 800 CIW
See Maximum Power Dissipation vs Temperature Curve Figure 21

CAUTION: Stresses abOll8 thosB listed In 'Absolu/B MaJdll'NJlrl Ratings' may cause ".,."..,..nt dama". to the davfce. This is a stress only 186ng and ope1860n
of the device at th6se or any other conditions abow those Indicated In the op8f8t1onal sections of this specification is not impUed.

Recommended Operating Conditions (TJ = -40"C to +125°C Unless Otherwise Noted, All Voltages Referenced to Vss)
Offset Supply Voltage, vs ••.•••.•••...••.••••. -2.0V to +500V
Floating Supply Voltage. Ves (VB to Vsl. • • • . • . . • . . +1OV to +15V
High Side Channel Output Voltage, VHO,VNHO .•.•..••• OV to Ves
Fixed Supply Voltage, Vee •..•.••.•........•... +10Vto+15V
Low Side Channel Output Voltage. VLO'VNLO •.••....•. OV to Vee
All Other Pin Voltages (SO. Rr. CT. DIS, SS, FLT and EN) ... OV to Vee

Discharge Time Constant. .•••..•.••.•••..•.•••••• lOOns Min
Discharge Resistor Range. Ro1s ..•••••••••••••. 100kn to 50kn
Charging Resistor Range. RT .•..•••••.•...•••.6.8kn to 400kO
Oscillator Capacitor Range, CT' .••••••...•.•.•. 100pF to O.lI1F
Oscillator Frequency Range •.••••••••.•••••.•••• 300kHz Max
Oscillator Capacitor Charge Current Range. 'Ar' ..... 21 j1A to 5mA

Electrical Specifications vcc = Ves = +15V. Vs = GND = ov, Unless Otherwise Specified
TJ = _40°C
TO+125°C

TJ = +25°C
PARAMETER

SYMBOL

Quiescent Vee Current

lace

Quiescent Ves Current

loes

Quiescent Leakage Current

ILK

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

-

5.5

7.0

8.0

mA

300

400

435

j1A

0.4

3.0
3.5

-

(Vs - GND) = 5.0V

-

Rr=O

-

I1A

5.0

mA

-

2.0

ISFT/PWM

1/3V ce < VSFT < %Vee

70

110

145

60

160

I1A

Input Threshold

VEN

Low to High Transition

7.5

7.8

8.5

7.4

8.6

V

Input Hysteresis

VEN-HYS

-

2

-

-

-

V

Standby Vee Current
SS Current Source

ISTBY

Undervoltage Threshold

VUVHL

High to Low Transition

7.7

8.6

9.5

7.4

9.6

V

Undervoltage Threshold

VUVLH

Low to High Transition

7.9

8.8

9.7

7.6

9.8

V

Undervoltage HysteresiS

VUVHYS

0.08

0.3

0.7

0.05

0.75

V

Short Detect Threshold

VTHSD

3.5

4.0

4.5

3.4

4.6

V

CT/Rr Current Ratio

ICTRAT

0.9

1

1.1

0.85

1.15

j1A

'Ar = l00j1A.
Veel3 < VeT < %Vee

HO. LO Peak Output Current

IOUT+

Sourcing. LO, HO = GND

1.5

1.95

-

1.0

HO, LO Peak Output Current

lour

Sinking. LO. HO = Vec = Ves

1.5

2.0

1.0

IBUF+

Sourcing,

m, HO = Vss
Sinking, ro, HO = Vec = Ves

170

250

-

110

170

230

-

110

-

rnA

CT =7.5V

7.5

7.8

8.1

7.4

8.2

V

m. HO Peak Output Current
m, HO Peak Output Current
Soft-Start VTHRESH' Low to High

' SUF VrSSHL

7-86

A

-

A
mA

Specifications HIP5500
Electrical Specifications vcc = Vas = +15V, Vs = GND = OV, Unless Otherwise Specified (Continued)
TJ
PARAMETER

SYMBOL

Soft-Start VTHRESH, High to Low

TEST CONDITIONS

=

TJ .40oC
TO+12SoC

=+2SoC

MIN

TYP

MAX

MIN

MAX

UNITS

V~SLH

7.2

7.5

7.8

7.1

7.9

V

OSC Input Upper Threshold

V~TLH

9.8

10.4

11.0

9.7

11.1

V

OSC Input Upper Threshold

V~THL

CTto DIS

5.0

5.6

6.2

4.9

6.3

V

Oscillator Upper to Lower
Threshold Difference

VCTDIF

VTCTLH - VTCTHL

4.5

4.8

5.1

4.4

5.2

V

OSC_OUT RosON, Sinking

OSCRosL

losc_oUT = -SOmA

5

8.5

12

2

17

Q

OSC_OUT RosON, Sourcing

OSCRoH

losc_ouT = SOmA

14

19

30

9

40

Q

DIS Output On Resistance

RosDIS

lOIS = lOrnA

75

115

ISO

·

200

Q

m Output On Resistance

RosFLT

IFLT= SmA

100

165

230

40

320

Q

Dynamic Electrical Specifications vcc = vas = +15V, GND = OV, Unless Otherwise Specified
TJ = ·40OC
TO +12SoC

TJ =+25°C
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

-

-

50

-

ns

25

35

-

ns

25

35

-

Tum-On Rise Time, HO, LO

loR

CL = 2000pF

Tum-Off Fall Time, HO, LO

IoF

CL =2000pF

RO, [Q

IoNR

CauF = 200pF

IoNF

CauF = 200pF

·
·

TpCTLH

CT=V~THL

-

475

700

·

925

ns

-

475

700

-

925

ns

TpCTLH and TpCTHL

-

60

-

-

-

ns

·
·

475

ns

825

ns

-

ns

1100

ns

775

ns

Tum-On Rise Time,

Tum-Off Fall Time, RO, [Q
CT Fall to Lo/HO Rise

Lo/HO LOAD = 200pF
CT Rise to Lo/HO Fall

TpCTHL

CT=V~TLH

LO/HO LOAD = 200pF
LO-HO Prop Delay Mismatch

Delmatch

50

CT Rise to DIS Fall

TpCTDISHL

CT=V~THL

·

300

4SO

CT Fall to DIS Rise

TpCTDISLH

CT=V~TLH

-

600

800

·

200

-

-

425

8SO

SOO

7SO

Minimum Dead Time
Short Detect Propagation Delay
Soft·Start Propagation Delay
Time

tOTMIN
tSOLO/HO
tSSOLY

SO = VTHSO , LO/HO = 200pF
SS = VTSSLH, LO/HO =
200pF

7·87

-

ns

ns

HIP5500

Typical Performance Curves

~
!Zw

100.0
50
20
10.0
5

:(6.4

::I
(J

w

!-&.2

, 1/
,

2
1.0
0.5

a:
a:

All Curves are Vcc" +lSV, TA = +2SoC, Unless Otherwise Specified

,

~

0.2
0.1
C
w
..J 0.05

!Z

B 5.4

~

~

L,;"

::I

o

~

~
!Z

",

0

::::: ""'-I.i

+20 +40 +60 +80
TEMPERATURE ("C)

I

+100 +120

I

I

l- i-

VBS-12V

r- r--

-

_2.8

---

12.6

~

+40 +60 +80
TEMPERATURE ("C)

+100 +120

Vcc· l5V

"-

'J I I
"""'l

~2.0

B1.8 .....
~ 1.&

§l1.4
j$1.2

r--.

1. 0

It~
Vcc· 12V

,...

l'oL.

r""" -..L I

+20 +40 +60 +60
TEMPERATURE ("C)

+100

0.4

+120

,/
,/

/

r-

I .,.......".,

0.8

Vcc· 1OV
-40

-20

o

......

-

.....

+20
+40
+60
TEMPERATURE ("C)

r-.

--

+80

+100

+120

FIGURE 4. QUIESCENT STANDBY CURRENT vs
TEMPERATURE AND Vcc SUPPLY VOLTAGE

I t I I

€ 2.0

, / Vcc· 1OV
Vcc· 12V
/. Vcc· 15V

w 1.8

65

55

+20

I I I

"-

0.6

o

-20

w

~

/

II

1.8
1.7

VCC· 15V -

-

~ 1.6

50

/" Vcc· 1OV
, / /~cc.12V
Vcc· 15V
,/

a:

~ 45

1.5

~

1.4

Vcc· 12V _
I

C 1.1
z
w
1.0

-20

0

+20 +40 +60 +80
TEMPERATURE ("C)

-40

+100 +120

FIGURES. ENABLEIDISABLE THRESHOLD (PERCENT Vccl va
TEMPERATURE AND Vcc SUPPLY VOLTAGE

7-88

I

-

1_ ,..-

Vcc· 1OV

!1.2

c 35
-40

~

~ 1.3

i~
iii

0

ih.2

0

~ 60

~

-20

;:2.4

r-- l- i-.

...>o

g
~
'"ow

'"

3.0

I

FIGURE 3. QUIESCENT FLOATING BIAS SUPPLY CURRENT
va TEMPERATURE AND VBS SUPPLY VOLTAGE

'8

Vcc" 10V

3.4

VBS,,10V
125
-40

I

Vcc" 12V

FIGURE 2. QUIESCENT Vcc CURRENT va TEMPERATURE
AND Vcc SUPPLY VOLTAGE

3.2

n--f... ....

I

........
.... ....

Vcc· 15V

r-

53.4-40

VBS_15V

;;;;;; -

--

!!! 3.6

I I I I

I

....

- -

4.6
4.4

4.2
~ 4.0
o 3.8

FIGURE 1. OFFSET SUPPLY LEAKAGE CURRENT va
TEMPERATURE AT 300VDC

-

5.2
5.0
4.8

t

,

325

"'"

a: 5.6

",

0.02
1/
0.01
0.005
-40
-20

.....

6.0

~5.8

-20

o

+20

+40
+60
+60
TEMPERATURE ("C)

+100

+120

FIGURE 6. ENABLEIDISABLE HYSTERESIS VOLTAGE
TEMPERATURE AND Vcc SUPPLY VOLTAGE

HIP5500
Typical Performance Curves

All Curves are Vcc = +lSV. TA = +2SoC. Unless Otherwise Specified (Continued)

12 0

1.8

iw

~ 11 0

£

!z

~ 100
a:
fo"'"

B

i

Iii
It
o

90

~ ::::
-~ ::::
.....

.....

i-""

I"

~
..... fo"'"

..... i--" fo"'"

..... i.-o" ~ .....

~
i!:i

..... i--" ri ..... ~ :::: ~
k ..... i--" ~

~

!;

~

~

I'-

-- r- --

\

Vcc .. 12V
Vcc.,10V

·20

o

+20

+40
+60
+80
TEMPERATURE ("e)

+100

~

'~

~CS+0.5CP

2.0

4.0
6.0
POWER DISSIPATION (W)

8.0

FIGURE 7. THERMAL CAPACITANCE MODEL OF HIP5600

Figure 7 shows the thermal capacitances of the TO-220
package, the integrated circuit and the heat sink, if used.

7-99

FIGURE 8. TIME TO THERMAL SHUTDOWN vs POWER
DISSIPATION (T0-220 PACKAGE ONLy)

10

HIP5600

= T A + T 1 + T2 + T 3

TJ (t)

Tl

(Ea. llA)

"'P9SA(1-e;~J

Thermal Shutdown Hysteresis
Figure 9 shows the HIPS600 thermal hysteresis curve with
VIN l00VDC, VOUT SV and lOUT 10mA. Hysteresis is
added to the thermal shutdown circuit to prevent oscillations
as the junction temperature approaches the thermal· shutdown limit. The thermal shutdown is reset when the input
voltage is removed, goes negative (i.e. AC operation) or
when the part cools down.

=

Where:

(Ea. 118)

'tl "'9 SA (Cp+C S)

=

=

10

(Ea. llC)
Where:
't2

T3

5

0.79JC

(

"'0.6P9Jc(1-e;~

O,SCp+Cs)O.SC p )
Cp+C S

J

8.0

1

6.0

j

4.0

\

2.0

(EO.l1D)

Where:
't3 '" 0.69 JCCD

0.0
118.0

HEATING

\

SHUTDOWN
REGION

~

\

105.0

COOUNG

......
113.0
120
127
CASE TEMPERATURE ("C)

135

142

Thermal Transient Operation (SOle Package)
Equation (11 A) can also be used for the SOIC package provided the following substitutions are made.

(l-e~

J

(Ea. 11E)

T2 '" P92 (1-e

;~

J

(Ea. llF)

T3 ",P93 (l-e

;~ J

(Ea. llG)

Tl ",P9 l

where
91
91
81

=160oc/W

=1OoC/W

=2.9°C/W

't1
t2
't3

=S.8s

=86ms

=7.Sms

For example, with the SOIC package mounted on a PC
board at +85°C in still air, the HIPS600 could dissipate 4W
for -70ms before going into thermal shutdown.
For start-up applications a more useful parameter is the total
charge delivered before thermal shutdown.
(TTS- T A )

0L -

V
IN

Cp

(Ea. 12)

Cp is about 3SmJf'C for the SOIC package and about
l000mJf'C for TO-220.
For example:
with TTS
VIN

=+12roC, TA =+8SOC

=400V and Cp =35mJf'C

OL := 3670f.lC
which is enough to charge a 24OJ!F capacitor to lSV.

FIGURE 9. THERMAL HYSTERESIS CURVE

AC to DC Operation
Since the HIPS600 has internal high voltage diodes in series
with its input, it can be connected directly to an AC power
line. This is an improvement over typical low current supplies
constructed from a high voltage diode and voltage dropping
resistor to bias a low voltage zener. The HIPS600 provides
better line and load regulation, better efficiency and heat
transfer. The latter because the TO-220 package permits
easy heat sinking.
The efficiency of either supply is approximately the DC
output voltage divided by the RMS input voltage. The
resistor value, in the typical low current supply, is chosen
such that for maximum load at minimum line voltage there is
some current flowing into the zener. This resistor value
results in excess power dissipation for lighter loads or higher
line voltages.
Using the circuit in Figure 3 with a 1000l1F output capacitor
the HIPS600 only takes as much current from the power line
as the load requires. For light loads, the HIPS600 is even
more efficient due to it's interaction with the output capacitor.
Immediately after the AC line goes positive, the HIPS600
tries to replace all the charge drained by the load during the
negative half cycle at a rate limited by the short circuit current limit (see "Al" and "81" Figure 10). Since most of this
charge is replaced before the input voltage reaches its RMS
value, the power dissipation for this charge is lower than it
would be if the charge were transferred at a uniform rate during the cycle. When the prOduct of the input voitage and current is averaged over a cycle, the average power is less than
if the input current were constant. Figure 11 shows the
HIPS600 efficiency as a function of load current for OOVRMS
and 132VRMS inputs for a 1S.6V output.

7-100

HIP5600

-

Do's And Don'ts

I

[\;.V

/

~N

±

I

120VRMS, 60Hz

I

r1 rl.
-~ r B1 tw1
\.. .... "

I

~IB2

J

1

..II

r-k

R

~\

t----i1--1
100mVIDIV

.........

1. Do not exceed the absolute maximum ratings.

'V

20mAIDIV

I

~

DC Operation

\.

-

,

-

/

2. The HIP5600 requires a minimum output current of 1mAo
Minimum output current includes current through RF1.
Warning: If there is less than 1mA load current, the output voltage will rise. If the possibility of no load exists,
RF1 should be sized to sink 1mA under these conditions .
RF1

-

23

'"

-

14

.............

12

-......

VOUT .. 15.6VDC
10

,.

0.0

I.

I'

•

I

I

I

5.0

I

I

I

I

I

I

I

I

I' I

10.0
LOAD CURRENT (mA)

= 1.07V = 1kil
1mA

Recommendation: Adequate protection means (such
as MOV, avalanche diode, surgector, etc.) may be
needed to clamp transients to within the ±650V input limit
of the HIP5600.

~

VIN" 132VRMS

'........ ............

V
REF
1mA

3. Do not "HOT' switch the input voltage without protecting
the input voltage from exceeding ±650V. Note: inductance from supplies and wires along with the 0.021lF
decoupling capacitor can form an under damped tank circuit that could result in voltages which exceed the maximum±650V input voltage rating. Switch arcing can
further aggravate the effects of the source inductance
creating an over voltage condition.

............. ~ VIN" 60VRMS

21

=

2msJDIV

FIGURE 10. AC OPERATION
25

MIN

I

I

,

I

I

I

15.0

FIGURE 11. EFFICIENCY AS A FUNCTION OF LOAD CURRENT

Referring again to Figure 10, Curve "Ai" shows the input
current for a 10mA output load and curve "B1" with a 3mA
output load. The input current spike just before the negative
going zero crossing occurs while the input voltage is less
than the minimum operating voltage but is so short it has no
detrimental effect. The input current also includes the charging current for the 0.02jlF input decoupling capacitor C1.
The maximum load current cannot be greater than 112 of the
short circuit current because the HIP5600 only conducts over
112 of the line cycle. The short circuit current limit (Figure 39)
depends on the case temperature, which is a function of the
power diSSipation. Figure 39 for a case temperature of
+100oC (Le. no heat sink) indicates for AC operation the
maximum available output current is 10mA (1/2 x 20mA).
Operation from full wave rectified input will increase the
maximum output current to 20mA for the same +100oC case
temperature.
As a reminder, since the HIP5600 is off during the negative
half cycle, the output capacitor must be large enough to supply the maximum load current during this time with some
acceptable level of droop. Figure 10 also shows the output
ripple voltage, for both a 10mA and 3mA output loads "A2"
and "82", respectively.

4. Do not operate the part with the input voltage below the
minimum 50VDC recommended. Low voltage operation: For input voltages between OVDC and +5VDC
nothing happens (lOUT = 0), for input voltages between
+5VDC and +35VDC there is not enough voltage for the
pass transistor to operate properly and therefore a high
frequency (2M Hz) oscillation occurs. For input voltages
+35VDC to +50VDC proper operation can occur with
some parts.
5. Warning: the output voltage will approach the input voltage if the adjust pin is disconnected, resulting in permanent damage to the low voltage output capacitor.
AC Operation
1. Do not exceed the absolute maximum ratings.
2. The HIP5600 requires a minimum output current of
0.5mA. Minimum output current includes current through
RF1. Warning: If there is less than 0.5mA output current,
the output voltage will rise. If the possibility of no load
exists, RF1 should be sized to sink 0.5mA under these
conditions.
RF1

MIN

=

V
REF
O.SmA

=

1.07V
0.5mA

= 2kil

3. If using a laboratory AC source (such as VARIACs or
step-up transformers, etc.) be aware that they contain
large inductances that can generate damaging high voltage transients when they are switched on or off.

7-101

Recommendations
(1) Preset VARIAC output voltage before applying power
to part.
(2) Adequate protection means (such as MOV, avalanche diode, surgector, etc.) may be needed to clamp
transients to within the ±650V input limit of the HIP5600.

HIP5600
4. Do not operate the part with the input voltage below the
minimum SOVRMS recommended. Low voltage operation similar to DC operation (reference step 4 under
DC operation).

A 10llF capaCitor (C2) provides stabilization of the output
stage. Heat sinking may be required depending upon the
power dissipation. Normally, choose RF1 «VREFII ADJ •

S. Warning: the output voltage will approach the input voltage if the adjust pin is disconnected, resulting in permanent damage to the low voltage output capacitor.

General Precautions
Instrumentation Effects
Background: Input to output parasitic impedances exist in
most test equipment power supplies. The inter-winding
capacitance of the transformer may result in substantial current flow (mA) from the equipment power lines to the DC
ground of the HIPS600. This "ground loop' current can result
in erroneous measurements of the circuits performance and
in some cases lead to overstress of the HIPS600.
Recommendations for Evaluation of the HIP5600
in the Lab

FIGURE 13. AC/DC CONVERTER

a) The use of battery powered DVMs and scopes will eliminate ground loops.
b) When connecting test equipment, locate grounds as
close to circuit ground as possible.
c) Input current measurements should be made with a noncontact current probe.
If AC powered test equipment is used, then the use of an
isolated plug is recommended. The isolated plug eliminates
any voltage difference between earth ground and AC
ground. However, even though the earth ground is disconnected, ground loop currents can still flow through transformer of the test equipment. Ground loops can be
minimized by connecting the test equipment ground as
close to the circuit ground as possible.
CAUTION:

Dangerous voltages may appear on exposed
metal surfaces of AC powered test equipment.

The HIPS600 can operate from an AC voltage between
SOVRMS to 280VRMS, see Figure 13. The combination of a
1kn (2W) input resistor and a V27SLA10B MOV provides
input surge protection up to 6kV 1.2 x SOilS oscillating and
pulse waveforms as defined in IEEElANSI C62.41.1980.
When operating from 120VAC, a V130LA10B MOV provides
protection without the 1kn resistor.
The output capaCitor is larger for operation from AC than DC
because the HIPS600 only conducts current during the positive half cycle of the AC line. The efficiency is approximately
equal to VOUT NIN (RMS), see Figure 11.
The HIPS600 provides an efficient and economical solution
as a start-up supply for applications operating from either AC
(SOVRMS to 280VRMS) or DC (SOVDC to 400VDC).
The HIPS600 has on chip thermal protection and output current limiting circuitry. These features eliminate the need for
an in-line fuse and a large heat sink.

Application Circuits

t -....-oVOUT

FIGURE 14.. START UP CIRCUIT

FIGURE 12. DC/DC CONVERTER
The HIP5600 can be configured in most common DC linear
regulator applications circuits with an input voltage between
SOVDC to 400VDC (above the output voKage) see Figure 12.

The HIPS600 can provide up to 40mA for short periods of time
to enable start up of a swHch mode power supply's control circuit. The length of time that the HIP5600 will be on, prior to
thermal shutdown, is a function of the power dissipation in the

7-102

HIP56DD
part, the amount of heat sinking (if any) and the ambient temperature. For example; at 400VDC with no heat sink, it will
provide 20mA for about 8s, see Figure 8.
Power supply efficiency is improved by turning off the
HIP5600 when the SMPS is up and running. In this application the output of the HIP5600 would be set via RF1 and RF2
to be about 9V. The tickler winding would be adjusted to about
12V to insure that the HIP5600 is kept off during normal operating conditions. The input current under these conditions is
approximately equal to ISlAS' (See Figure 28).
The HIP5600 can supply a 450J.lA (:l:20%) constant current.
(See Figure 15). It makes use of the internal bias network.
See Figure 28 for bias current versus input voltage.
With the addition of a potentiometer and a lOI!F capacitor the
HIP5600 will provide a constant current source. lOUT is given
by Equation 13 in Figure 16.

The HIP5600 can be operated as a self-oscillating buck regulator for increased output currents and circuit efficiencies
approaching 75%. The circun shown (Figure 17) is capable of
operating from enher DC (50VDC to 400VDC) or AC
(90VRMS to 264VRMS) and is optimized for a 24V 150mA
output. The output voltage is set by RF1 and RF2 resistor values and is slightly higher than the value predicted in Equation
1A. The frequency of operation for the circuit is around 16kHz.
The circun shown (Figure 18) is optimized for a 24V 250mA
output with a 90VRMS to 132VRMS input. Output short circun
protection is provided by adding a pnp transistor and a small
O.22Q sense resistor. A snubber circuit was also added to
reduce the power dissipation in the P-IGBT. The frequency of
operation for the circuit is around 18kHz.

+SOVDC TO +400VDC

+20VDC TO +400VDC

lOUT '" 1.21V
R1

NOTES:

(Ea. 13)

1. Your Floating
2. Fixed SOOItA Current Source

FIGURE 15. CONSTANT 450pA CURRENT SOURCE

90VRMS

FIGURE 16. ADJUSTABLE CURRENT SOURCE

TO 264VRMS

FIGURE 17. HIGH CURRENT "BUCK" REGULATOR

7-103

HIP5600

OUTPUT SHORT
CIRCUIT PROTECTION

..

~ ::~:;:;-t·-----··--·---

--..-----'"
SNUBBER CIRCUIT

HVRMS TO 132VRMS
AC
HI
24VDC, 0.25A

FIGURE 18. HIGH CURRENT "BUCK" REGULATOR WITH OUTPUT SHORT CIRCUIT PROTECTION AND SNUBBER

Typical Performance Curves

lz

-

-0.4

5i

:>
w

-0.8

0

CI -1.0

~

~ -1.2
-1.4

V

--

~

-1.6 -40

-20

0

25

,

1mAT020mA

.....
~

1mAT030mA

1mATOjOmA

1

---

~

1mATO 20mA

~

0

r--1mA TO 10mA

....

----

w

....
::>
0.
....
:>

- r--....

f--- 1mA TO 10mA

0 -0.6

VIN",50VDC
40

60

80

100

-20

VIN,,400VDC

0
25
40
CASE TEMPERATURE rC)

CASE TEMPERATURE (OC)
FIGURE 19. LOAD REGULATION vs TEMPERATURE

--

60

80

FIGURE 20. LOAD REGULATION VS. TEMPERATURE

85
VIN= 170VDC,IL" 10mA,h120Hz, TC-+25°C_

80

~
z

75

0

70

13w

65

....
w

II:

...w

60

a:

55

0.
0.

,

1\

-

I I
I 'I.

I
I

I I

1/

-- ........

NO BYPASS CAPACITOR

45 1
o

I

I

VIN '" 4ooVDC,IL",10mA, !-12OHz, Tc. +2S"C

r--

80

~ 70

~ I
I
I
I
I
1'\ I
I 11'F BYPASS CAPACITOR \10I'F BYPASS CAPACITOR

["') 1'-0..

50

I

10

20

30

-

lS
13

60

'\
~10JlF BYPASS

~

I" 11'F BYPASS CAPACITOR
CAPACITOR

~

II: 50

/

~

0.

~

1

40 50 60 70 80
OUTPUT VOLTAGE (V)

40 -

NO ~YPASS ~APACn:OR

---

""'"'-

3O~1~~~~~-=~~-=~~

Tj

110 100 110

o

FIGURE 21. RIPPLE REJECTION RATIO (OUTPUT VOLTAGE)

50

100
150
200
250
OUTPUT VOLTAGE (V)

300

350

FIGURE 22. RIPPLE REJECTION RATIO (OUTPUT VOLTAGE)

7-104

HIP56DD
Typical Performance Curves (Continued)
IS

80 10flFBYPASS
CAPACITOR
iii'
:!!. 75

"Y

z
0

~

70

..,ww

65

.".

(J

g.
g.

.".

55

J.

./

"\

/

~

~

50

t..,w

70

..J

60

a:

55

ir--

L y

w 65
a:
w

A

g.
g.

\ /\
AI

lflF BYPASS CAPACITOR

I~

0

I

I

10

100
lk
10k
lOOk
INPUT FREQUENCY (Hz)

1M

10M

"
...........

r\.

"-1
I

50
45

1

/

I....

1

10

~

'I
~.

"IIf
;1

_ 1flF BYPASS CAPACITOR

NO BYPASS CAPACITOR
45

,

VIN a 400VDC,IL.l0mA, VOUT a 15V, TCa +250 C
10 lOflFBYPASS
iii'
~
:!!. 75 CAPACITOR
z

'\.'\.

J .........

i"""J

/

a:
w
..J 60

a:

,

86

VIN a170VDC,ILal0mA, VOUTa15V, TCa+25oC

NO BYPAS·S CAPACITOR
100

lk

10k

lOOk

1M

10M

INPUT FREQUENCY (Hz)

FIGURE 23. RIPPLE REJECTION RATIO (INPUT FREQUENCy)

FIGURE 24. RIPPLE REJECTION RATIO (INPUT FREQUENCy)

85r---,---_T--~~--,---_T----~--,

VIN .400VDC, VOuT,,10mA, I" 120Hz, TC" +250 C
80

(REFERENCE FIGURE 3)

55

55
SOL----L--~L-

o

5

__

~

__

-..J~

__

~

__

10
15
20
25
OUTPUT CURRENT (mA)

~

_____'

50L---~--~----L---~--~----L---~

o

35

30

FIGURE 25. RIPPLE REJECTION RATIO (OUTPUT CURRENT)

5

10
15
20
25
OUTPUT CURRENT (mA)

30

35

FIGURE 26. RIPPLE REJECTION RATIO (OUTPUT CURRENT)

520
510
100~-----t----~r-----t-----+-.---;--;

500
4110

1!2 480
470
J

460

450
440
430
420
10

100

lK
10K
FREQUENCY (Hz)

lOOK

1M

FIGURE 27. OUTPUT IMPEDANCE

50

100

200
300
INPUT VOLTAGE (VDC)

FIGURE 28. IBIAS vs INPUT VOLTAGE

7-105

400

HIP5600

Typical Performance Curves

(Continued)

I I
VOUT

1\ 100mVIDIV

~

lih1il'F

15V

[72
IV

I
ChOI'F

5

~

1SV

I\(

~

II'

IDI
1r

t -f

OV

I

ffi

~

T = 100maJDIV

~

1.17

~ 1.16
w 1.15
~ 1.14

1

w 1.17
~ 1.16
!:i 1.15

gw
~

ll!
~

ll!

1.14
1.13
1.12
1.11
1.10
1.08

I-

NDI

T= 100msIDIV

~

1mA

~1.20rr-~~--~~·-+--+---~-~H

/

~ n~~:t::~~~f:::~~~::~

SmA

~ ~-.;;;s ~
~

~ 1.15

10mA

............ ~ ~

-30mA/

w

~ 1.10 I-I"-oo;:±---I=-....=~+---I....;;;:::II-t-I

~

""'/ '" i"""--.......

II!
~

20mA

II:

I
-40

o

25
40
60
CASE TEMPERATURE ("C)

·20

80

- --

CASE TEMPERATURE ("C)

FIGURE 32. REFERENCE VOLTAGE va TEMPERATURE

1.20
IoUT,,10mA

-

1.18

~
w 1.16

Tc=-4o"C

~

-- -- --r---

TC .. +2SOC

g'"'
U
Z

w 1.10

II:

~
w 1.08

TC=+100oC - - -

200
300
INPUT VOLTAGE (VDC)

1.14

w 1.12

I

100

1.05 t+--~t_--t---+_-_;_--+_-_+I
1.00 L-4~0--•.L20--.J0'---:25':---4~0--.J60---8UO

100

FIGURE 31. REFERENCE VOLTAGE va TEMPERATURE

~ 1.18

5j

1.2S ......- - , . . . . - -......- - - r - - - , - - - - r - - - . . ,

1mA

1.11

1.20
1.19

'-

VIN·400VDC:
VOUT,,1SV
:
TJ" +2SoC :

FIGURE 30. LOAD TRANSIENT RESPONSE

.

1•13
_ 1.12
1.10

C3r°l'~

~

VIN-50VDC

1.20

:> 1.18
;; 1.18

""'"

OmA

FIGURE 29. LINE TRANSIENT RESPONSE

1.21

~

~ 10mA

B
!:i SmA

VOUT" 15VDC::
IL,,5mA
TJ 1" +25 C

100V

...

r-

20mVIDIV

~

C3.101lf
/

400V
INPUT
VOLTAGE

rt

1\

I I

~

- -- .............--.
......

30m~

1.06

FIGURE 33. REFERENCE VOLTAGE va INPUT VOLTAGE

100

200
300
INPUT VOLTAGE (VDC)

FIGURE 34. REFERENCE VOLTAGE vs VIN ;
CASE TEMPERATURE OF +25"(:

7·106

SmA
10;:;;A"

' - ............. ...............
..... 20mA

II:

400

1mA

400

HIP5600

Typical Performance Curves

(Continued)

80

80
VIN-400VDC

VIN_50VDC
75

I1mA

~ 70

..

\

z
w 65

a:
a:

.. ~

:::> 60
(.)

~

55

~

~

10'"

/

75

.... ~

~ 70

I

...z

20mA

w 65

a:
a:

:::> 60
(.)

~

30mA

~

so

50

45

-40

55

45

o

25
40
60
CASE TEMPERATURE ("C)

·20

80

100

-40

775

2000

770
Tc oo +25":;'
765

!z

i

8
~

760

0
25
40
CASE TEMPERATURE ("C)

~
~

755

~

--

60

80

FIGURE 36. IAOJ vs TEMPERATURE

FIGURE 35. IAOJ vs TEMPERATURE

~

·20

-

VIN",100VDC
TC-25·C

1500

~

MINIMUM LOAD
CURRENT

ffi 1000

a:
a:

Tc _ +100·C

:::>
(.)

SOO

750
745

50

100

200
300
INPUT VOLTAGE (VDC)

01

400

FIGURE 37. MINIMUM LOAD CURRENT VS VIN

234
VOUT· VAOJ (VDC)

FIGURE 38. TERMINAL CURRENTS vs FORCED V REF

55

1 1-

-

TC·-4O"C

Tc-+1oo• C

25
20

Tc-+25oC

50

100

150
200
250
300
INPUT-OUTPUT (VDC)

350

FIGURE 39. CURRENT LIMIT vs TEMPERATURE

7·107

400

5

HIP5600

Evaluation Boards

o

VIN

.

VOUT
HIP5600 EVALUATION BOARD

3.25"

3.25" - - - - - - - ;..~

FIGURE 40. EVALUATION BOARD (TOP)

FIGURE 41. EVALUATION BOARD METAL MASK (BOTTOM)

lvlN

ADJ 1 • • •
VOUT·

•• • •
••

rn
VIN

• •

•
• •

" •

••

m+
L.!J .

VOUT
HIP5600 EVALUATION BDARD

~"E-------

3.25"

..

FIGURE 42. EVALUATION BOARD METAL MASK (TOP)

7-108

ICL7660
CMOS Voltage Converter

April 1994

Features

Description

• Simple Conversion of +5V Logic Supply to ±5V
Supplies

The Harris ICL7660 is a monolithic CMOS power supply
circuit which offers unique performance advantages over
previously available devices. The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of +1.5V to +10.0V, resulting in complemetary output
voltages of -1.5V to -10.0V. Only 2 non-critical external
capacitors are needed for the charge pump and charge
reservoir functions. The ICL7660 can also be connected to
function as a voltage doubler and will generate output
voltages up to + 18.6V with a +1 OV input.

• Simple Voltage Multiplication (Vour = (-) nVIN)
• Typical Open Circuit Voltage Conversion Efficiency
99.9%
• Typical Power Efficiency 98%
• Wide Operating Voltage Range 1.SV to 10.0V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• No External Diode Over Full Temperature and Voltage
Range

Applications
• On Board Negative Supply for Dynamic RAMs
• Localized ~Processor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems

The oscillator, when unloaded, oscillates at a nominalfrequency of 10kHz for an input supply voltage of 5.0V. This
frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5V to + 1O.OV), the
LV pin is left floating to prevent device latchup.

Ordering Information
TEMPERATURE
RANGE

PART NUMBER

Contained on the chip are a series DC supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output NChannel switch source-substrate junctions are not forward
biased. This assures latchup free operation.

PACKAGE

ICL7660C"TV

O"C to +70"C

ICL7660CBA

O"C to +70"C

8 Lead SOIC (N)

ICL7660CPA

O"C to +70"C

8 Lead Plastic 01 P

ICL7660M"TV (Note)

O"C to +70"C

8 Pin Metal Can

An enhanced direct replacement for this part, the ICL7660S,
is now available and should be used for all new deSigns.

8 Pin Metal Can

NOTE: Add 1883B to part number if 883B processing IS requIred.

Pinouts
ICL7660 (PDIP, SOIC)

ICL7660 (CAN)

TOP VIEW

TOP VIEW
V+ (AND CASE)

NCOsv+
CAP+

2

. 7 OSC

GND3

SLV

CAP·

5 VOUT

4

CAUTION: These devices are sensitive to electrostatic discharge. Users should lollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-109

File Number

3072.1

Specifications ICL7660
Absolute Maximum Ratings

Thermal Information

Supply Voltage •••••••••••••••••••.•••••••••••••••• +1 0.5V
LV and OSC Input Voltage •••••• -0.3V to (V+ +C.3Y) for V+ < 5.5V
(Note 1)
(V+ -5.5V) to (V+ +C.3V) for V+ > 5.5V
Current Into LV (Note 1) ••••••••••••.•••••• 201J.A for V+ > 3.5V
Output Short Duration (VSUPPl.y:S; 5.5V) .•••••••..••• Continuous

Thermal Resistance
°JA
°JC
Plastic DIP Package ••.••••.•.•••••• 150oCM'
Plastic SOIC Package .••••••.••••••• 170oCM'
Metal Can •••.•...•..•••••••.....• 156°CM' 68°CM'
Storage Temperature Range ...•••••....•...•• -65°C to +150°C
Lead Temperature (Soldering, 1Osec) •.••..••......•••.. 300°C
(SOIC - Lead lips Only)

-

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause pIlrmansnt dsmage to the dsvice. This is a stress only rating and operation
of the device at these or any other conditions above /hose indicated In the CpIlra60nai sections of this SpIlCifica60n is not Implied.

Operating Conditions
Operating Temperature Range
ICL7660M ••••••••••••••••••..•••••••••• -55°C to +125°C

Electrical Specifications

V· = 5V, TA = +25°C, cosc = 0, Test Circuit Figure 11 (Unless Otherwise Specified)
MIN

TVP

MAX

UNITS

-

170

500

IJ.A

MIN:s;TA:s; MAX, RL = 10kO, LV to GROUND

1.5

-

3.5

V

Supply Voltage Range - Hi

MIN:s; TA:s; MAX, RL = 10kO, LV to Open

3.0

-

10.0

V

Output Source Resistance

lOUT = 20mA, TA = +25OC

55

100

0

-

120

0

SYMBOL

PARAMETER

TEST CONDITIONS

Supply Current

RL=oo

VL+

Supply Voltage Range - Lo

VH+
ROUT

1+

ICL7660C •••••••••••.•••••••••.••.•••.••••• COC to +70OC

-

lOUT = 20mA, OoC :s; TA :s; +70oC
lOUT = 20mA, _55°C :s; T... :s; + 125°C

-

V· =.2V, lOUT = 3mA, LV to GROUND
COC:s; T... :S; +7COC
V+ = 2V, lOUT = 3mA, LV to GROUND,
-55°C:s; T... :S; +125OC

VOUTEF

Zosc

150

0

300

0

-

400

0

-

kHz

-

10

Power Efficiency

RL =5kO

95

98

Voltage Conversion Efficiency

RL=oo

97

99.9

Oscillator Impedance

V+ =2 Volts

-

1.0

Oscillator Frequency

fosc
PEF

-

V = 5 Volts

100

-

-

%
%

MO
kO

NOTES:
1. Connecting any input terminal to voltages greater than V+ or less than GROUND may cause destructive latchup. It is recommended that
no Inputs from sources operating from external supplies be applied prior to ·power up" of the ICL7660.

Functional Block Diagram

I

I

RC
OSCILLATOR

--0

+2

I

v+

-

1

CAP+

VOLTAGE
LEVEL
TRANSLATOR

CAP-

I

F~.....o VOUT

IrtOSC

LV

I

VOLTAGE
REGULATOR

I

Y :)--11

1

OJ"

7-110

Ir

.I

I
LOGIC

I

• 'LI........N_£nN
...._O_R_K........~

ICL7660

Typical Performance Curves

(Test Circuit of Figure 11)
10K
TAS+2S"C

8

r==
r--

~

~6h~6I'!:""""~~l---:rLl~'-Ir-71

1\

!:l
~

,

\.

~41'-~r--:r~<-:~-7IF-,79~~
0..
0..

::>

r-.....

~~=¢:z;~::j2=~ZI

'" 2

0'----l1----1_--L_-L._...l----l
-55
·25
0
25
50
100 125
TEMPERATURE ("C)
FIGURE 1. OPERATING VOLTAGE AS A FUNCTION
OF TEMPERATURE

2

!il

m 200

II:

100

5...0..
5

50

lIS r--

~

~ 250

6

7

8

I--""'"
i,......o- ~

-

o
-55

·25

0
25
50
75
TEMPERATURE ("C)

100

88

!U

86
84

II:

w

~
0..

I

-

IoUTs1SmA

80

w

>

r--

V+",.5V

I-

~

82

I

_I-'"

..... r-.

IoUTs1mA

84

IEw

k'"
~:a+2V
I

TAS+2S"C

88

tiz

;; 300

150

S

100

l

louTs1mA

!"'

4

FIGURE 2. OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF SUPPLY VOLTAGE

3SO

cr

3

SUPPLY VOLTAGE (V+)

82
V+s+5V

80

125

100

1k

10k

OSC. FREQUENCY lose (Hz)

FIGURE 3. OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

FIGURE 4. POWER CONVERSION EFFICIENCY AS
A FUNCTION OF OSC. FREQUENCY

10K

to..

]
tz

1
1\

1K

w

5w

20
(,) 18

If

~
l1l

5

II:

o

~
~

V+s5V
TA,,+25°C

o

10
1.0

10

100

1000

16

1\,

14

"

i12

,

~ 100

~

J

r\

10K

Cosc(pF)

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSC. CAPACITANCE

10
8

V+s+5V

6
-50 -25

"

r'-...

r-.....

0 25 50 75 100 125
TEMPERATURE ("C)

FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS
A FUNCTION OF TEMPERATURE

7·111

ICL7660
Typical Performance Curves
5

~

2

6>

~

1

8

tiz

...~

70

...~

l.."..;' "

SLOPE55n

I\.

/

.I
/

u 20

a:

'" ,

1/

0

1/

1+- 00

!jI-'

/

50

>
z 30

-3

-5

::I&.."

w 60

z

-'

-4

~

")"

iii
a:
w 40

.2

100

~
PEFF ...

00

w 80

0

0
·1

I!:

g100

:
i
,

v+".sV

3

w

:

T",,+250C

4

(Conlinued)(Test Circuit of Figure 11) (Continued)

/

0

o

I

!i:

60
w
50 ~
40

i3

30

~

20 ~

T",,+25OC
V+=+5V

/

10

1

80
70 .:!:

10

I

10 20
30
40 50
LOAD CURRENT IL (mA)

60

til

o

LOAD CURRENT IL (mA)

FtGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS AFUNCTION OF LOAD CURRENT

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT
+2

~,

T,,=+250C
V+,,2V

g 100

\

+1

\

·2

,.. ~ ~ ~

o

SlO

w

80

W

70
60

~

\

,/
~

~

a:~

J

g!

8a:

~

~

SLOPE 1500

I I

i'-' r--I

~

.....

,

oC-o

./
L

16.0
14.0
10.0
6.0

I- 4.0
I- 2.0

T,,=+250C
V+.2V

~

o

18.0

8.0

./

20
10

20.0

12.0

./

2345678
LOAD CURRENT IL (rnA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT

..........

PEFF

50
40
30

0

...-

OmA

1.5

3.0

4.5

6.0

7.5

~

w

15

1000pF) the values of C1 and C2 should be increased to 1001lF.
FIGURE 11. ICL7660 TEST CIRCUIT

7·112

ICL7660
Detailed Description
The ICL7660 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive lOI1F polarized electrolytic types. The mode of operation of the device may be
best understood by considering Figure 12, which shows an
idealized negative voltage converter. Capacitor C, is
charged to a voltage, V+, for the half cycle when switches S,
and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation,
switches S2 and S4 are closed, with S, and S3 open, thereby
shifting capacitor C, negatively by V+ volts. Charge is then
transferred from C, to C2 such that the voltage on C2 is
exactly V+, assuming ideal switches and no load on C2 . The
ICL7660 approaches this ideal situation more closely than
existing non-mechanical circuits.
In the ICL 7660, the 4 switches of Figure 12 are MOS power
switches; S, is a P-channel device and S2' S3 and S4 are Nchannel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 and S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit start-up, and under output short
circuit conditions (Vour V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latch up.

=

This problem is eliminated in the ICL7660 by a logic network
which senses the output voltage (Vour) together with the
level translators, and switches the substrates of S3 and S4 to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-latch up Circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5V the LV terminal must be left open to
insure latch up proof operation, and prevent device damage.
2

S,

8

0"0

VINO
3

!
i
i

I

Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
A The driver circuitry consumes minimal power.
B The output switches have extremely low ON resistance and virtually no offset.
C The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative voltage conversion if large values of C, and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:

E =1/2 C, (V, 2 - Vi)
where V, and V2 are the voltages on C, during the pump
and transfer cycles. If the impedances of C, and C2 are relatively high at the pump frequency (refer to Figure 12) compared to the value of RL, there will be a substantial difference
in the voltages V,and V2. Therefore it is not only desirable to
make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C,
in order to achieve maximum efficiency of operation.
Do's And Don'ts
1.

Do not exceed maximum supply voltages.

2.

Do not connect LV terminal to GROUND for supply voltages greater than 3.5V.

3.

Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.

4.

When using polarized capaCitors, the + terminal of C 1
must be connected to pin 2 of the ICL7660 and the + terminal of C2 must be connected to GROUND.

5.

If the voltage supply driving the ICL7660 has a large
source impedance (250 - 300), then a 2.211F capaCitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V1I1S.

6.

User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions. A lN914 or similar diode
placed in parallel with C2 will prevent the device from
latching up under these conditions. (Anode pin 5, Cathode pin 3).

lit

'1-

C,

~!

3

t~

~
5
0

VOUT--V..

FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER

7-113

ICL7660
V+

FIGURE 13A. CONFIGURATION

FIGURE 13B. THEVENIN EQUIVALENT

FIGURE 13. SIMPLE NEGATIVE CONVERTER

f
V

t

.(V+)

FIGURE 14. OUTPUT RIPPLE
V+

FIGURE 15. PARALLELING DEVICES

V+

FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

7-114

ICL7660

Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 for generation of negative supply voltages. Figure
13 shows typical connections to provide a negative supply
negative (GND) for supply voltages below 3.5V.
The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 138. The voltage source has
a value of -V+. The output impedance (Ro) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 12), the switching frequency, the value of C, and C2 ,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for Ro is:
Ro;;; 2(Rsw, + RSW3 + ESRc,) +

potentially swamp out a low 1/(fpUMP • C,) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and 8, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C2 at the instant it goes from being charged by C, (current
flow into C2 ) to being discharged through the load (current
flowing out of C2). The magnitude of this current change is
2. lOUT, hence the total drop is 2. lOUT • eSRC2 V. Segment 8
is the voltage change across C2 during time t2 , the half of the
cycle when C2 supplies current to the load. The drop at 8 is
lOUT. t21C2 V. The peak-to-peak ripple voltage is the sum of
these voltage drops:

2(RsW2 + RSW4 + ESRc,) +
V R1PPLE '"

1

- - - - - + E S RC2
(lpuMp) (Cl)
losc
--""2';;';;"-- , Rswx =MOSFET switch resistance)

[

2

(Ipu~p) (C2)

+ 2 (ESRC2)

]

lout

Again, a low ESR capacitor will reset in a higher performance output.
Paralleling Devices

Combining the lour Rswx terms as Rsw, we see that:
Ro =

2 (Rsw) +

1
- - - - + 4 (ESRc,) + ESRC2
(IPUMP) (Cl)

RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance
graphs), typically 230 at +25°C and 5V. Careful selection of
C, and C2 will reduce the remaining terms, minimizing the
output impedance. High value capacitors will reduce the
1/(fpUMP • C,) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fpUMP. C1) term, but may have the side effect
of a net increase in output impedance when C, > 10llF and
there is no longer enough time to fully charge the capacitors
every cycle. In a typical application where fosc = 10kHz and
C = C, = C2 = 101lF:

Ro = 2 (23) +

1

(5. 103) (10-5)

Any number of ICL7660 voltage converters may be paralleled to reduce output resistance. The reservoir capacitor,
C2 , serves all devices while each device requires its own
pump capacitor, C,. The resultant output resistance would
be approximately:

RouT =

RoUT (01 ICL7660)

n (number 01 devices)

Cascading Devices
The ICL7660 may be cascaded as shown to produced larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limit is
10 devices for light loads. The output voltage is defined by:
VOUT = -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individuallCL7660 RoUT values.

+ 4 (ESRc,) + ESRC2

Ro =46 +20+ 5 (ESRcl

Changing the ICL7660 Oscillator Frequency

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fpUMP • C,) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Ro;;; 2 (23) + (5.103) (10-5 ) + 4 (ESRc,) + ESRc2
Ro = 46 + 20 + 5 (ESRcl
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could

It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 17. In order to prevent possible
device latchup, a 1kn resistor must be used in series with
the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the
addition of a 10kn pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking, as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.

7-115

ICL7660
v+

v+

Combined Negative Voltage Conversion
and Positive Supply Doubling
CMOS

GATE

ICL7660

FIGURE 17. EXTERNAL CLOCKING

It is also possible to increase the conversion efficiency of the
ICL7660 at low load levels by lowering the oscillator frequency. This reduces the switching losses. and is shown in
Figure 18. However. lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (G 1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C 1 and C2 by the same factor that
the frequency has been reduced. For example. the addition
of a l00pF capacitor between pin 7 (OSC) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10). and thereby necessitate a corresponding increase in the value of G1 and G2 (from 10llF to
100IlF).

Figure 20 combines the functions shown in Figures 13 and
Figure 19 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be. for example. suitable for generating +9V and -SV from an
existing +SV supply. In this instance capacitors C1 and C3
perform the pump and reservoir functions respectively for
the generation of the negative voltage. while capaCitors C2
and C4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions. however. in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.

v+

L------"-i +

VOUT" (nVIN - VFDX)

VOUT = (2V+) "
(VFDll- (VFD2)

+

.J." c.

Cosc

FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER

1--:-....- ... VOUT

+~ C:z

VoHage Splitting

FIGURE 18. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling
The ICL7660 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 19. In this application. the pump inverter switches of the ICL7660 are used to
charge G1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage drop of diode 0 1).
On the transfer cycle. the voltage on C 1 plus the supply voltage (V+) is applied through diode O2 to capacitor C2 • The
voltage thus created on C2 becomes (2V+) - (2VF) or twice
the supply voltage minus the combined forward voltage
drops of diodes 0 1 and O2 .

The bidirectional characteristics can also be used to split a
higher supply in half. as shown in Figure 21. The combined
load will be evenly shared between the two sides. Because
the switches share the load in parallel. the output impedance
is much lower than in the standard circuits. and higher currents can be drawn from the device. By using this circuit. and
then the circuit of Figure 16. + 1SV can be converted (via
+7.S. and -7.S) to a nominal -1SV. although with rather high
series output resistance (-2S00).

The source impedance of the output (VOUT) will depend on
the output current. but for V+ = SV and an output current of
lOrnA it will be approximately 600.

vOUT-V+- v2

V+

L-_--L~======:::::.Lv"
VOUT(2V+) - (2VF)

1+

---lT" c

L - -_ _ _ _ _ _

1

FIGURE 19. POSITIVE VOLTAGE DOUBLER

7-116

FIGURE 21. SPLITTING A SUPPLY IN HALF

ICL7660
Regulated Negative Voltage Supply

+8V

50k

In some cases, the output impedance of the ICL7660 can be
a problem, particularly if the load current varies substantially.
The circuit of Figure 22 can be used to overcome this by
controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7660s output does not respond instantaneously to
change in input, but only after the switching delay. The circuit
shown supplies enough delay to accommodate the ICL7660,
while maintaining adequate feedback. An increase in pump
and storage capacitors is desirable, and the values shown
provides an output impedance of less than 50 to a load of
10mA.
Other Applications
Further information on the operation and use of the ICL7660
may be found in A051 ·Principals and Applications of the
ICL7660 CMOS Voltage Converter".

FIGURE 22. REGULATING THE OUTPUT VOLTAGE

+5V LOGIC SUPPLY

TTLI~~~

>----------..,h

18
RS232
DATA

+5V

OUTPUT

-5V

FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY

7-117

r-1
n
L....-I L.

I

ICL7660S
Super Voltage Converter

April 1994

Features

Description

• Guaranteed Lower Max Supply Current for All
Temperature Ranges

The ICL7660S Super Voltage Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry standard ICL7660 offering an extended operating supply voltage range up to 12V,
with lower supply current. No external diode is needed for
the ICL7660S. In addition, a Frequency Boost pin has
been incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section.
Critical parameters are guaranteed over the entire commercial, Industrial and military temperature ranges.

• Wide Operating Voltage Range 1.5V to 12V
• 100% Tested at 3V
• No External Diode Over Full Temperature and Voltage
Range
• Boost Pin (Pin 1) for Higher Switching Frequency
• Guaranteed Minimum Power Efficiency of 96%
• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%
• Improved SCR Latchup Protection
• Simple Conversion of +5V Logic Supply to ±5V
Supplies
• Simple Voltage Multiplication VOUT = (-)nVIN
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices

Applications
• Simple Conversion of +5V to ±5V Supplies
• Voltage Multiplication VOUT =±nviN
• Negative Supplies for Data AcquiSition Systems and
Instrumentation
• RS232 Power Supplies

The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V. Only
2 non-critical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7660S can be
connected to function as a voltage doubler and will generate
up to 22.8V with a 12V input. It can also be used as a voltage multiplier or voltage divider.
The chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of
5.0V. This frequency can be lowered by the addition of an
external capaCitor to the "OSC" terminal, or the oscillator
may be over-driven by an external clock.
The "LV" terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latch up.

• Supply Splitter, VOUT = ±Vsl2

Pinouts

De OSC ::SOO::

ICL7660S (PDIP, SOIC)
TOP VIEW

ICL7660S (CAN)
TOP VIEW
v+ (AND CASE)

BOOST

CAP+

v+

2

7

GND3

6LV

CAP- 4

5

VOUT

GND

Od
r ermg normat'lon
I "
PART NUMBER

TEMPERATURE
O"C to +70"C

8 Lead Plastic
SOIC(N)

ICL7660SCPA

O"C to +70"C

8 Lead Plastic DIP

ICL7660SCTV

O"C to +70"C

ICL7660SIBA

_40°C to +85°C

8 Lead Plastic
SOIC(N)

ICL7660SIPA

-40°C to +85OC

8 Lead Plastic DIP

ICL7660SITV

.40oC to +85°C

8 Pin Metal Can

ICL7660SMTV
(Note)

-55°C to +125°C

8 Pin Metal Can

VOUT
CAP-

PACKAGE

ICL7660SC9A

8 Pin Metal Can

NOTE: Add 18839 to part number If 8839 proceSSIng IS required.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-118

File Number

3179.1

Specifications ICL7660S
Thermal Information

Absolute Maximum Ratings

8JA
8JC
Supply Voltage .•••.•...••..•....••..•.•..•...•.•.. + 13.0V Thermal Resistance
Plastic DIP. . • • • . . . • • • • • • • • • • . . • . • • . 1500cfW
LV and OSC Input Voltage (Note 1)
Plastic SOIC . . . • . . • . . . • • . . • • . . • • . . • 1700cfW
V+ < 5.5V •..••..•.•.••....•..•••••.•.• -O.3V to V+ + O.3V
V+ > 5.5V .......................... V+ -5.5V to V+ +O.3V
Metal Can ••..•...••...•..••.......
155°CfW 700 CfW
Lead Temperature (Soldering 10s) .•••.•••..•.•.••...• +300oC
Current into LV (Note 1)
(SOIC - Lead "Tips Only)
V+ > 3.5V .•••••..•.......•••..••...•••..•.••••.. 2011A
Output Short Duration
VSUPPLY:S 5.5V ..•....••...........••..•.•••. Continuous
Storage Temperature Range ....•••...••..... -65°C to + 150°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a strsss only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range
ICL7660SM ..•..••.............•........ -55°C to +125°C

ICL7660SI •••.••••..•...••.•••.••••.••... -4COC to +85°C
ICL7660SC •.•.•.•••.......••........•...• COC to +70oC

=5V, TA =+25°C, OSC =Free running, Test Circuit Figure 12, Unless Otherwise Specified

Electrical Specifications

V+

Oscillator Frequency (Note 3)

losc

Power Efficiency

P EFF

NOTES:
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs
Irom sources operating Irom external supplies be applied prior to 'power up' of ICL7660S.
2. Derate linearly above +5COC by 5.5mWfC
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged Into a test socket, there is usually
a very small but finite stray capacitance present, 01 the order 01 5pF.
4. The Harris ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in
existing designs which incorporate an external diode with no degradation in overall circuit performance.
5. All significant improvements over the Industry standard ICL7660 are highlighted.

7-119

Specifications ICL7660S
Electrical Specifications

V+ = 3V, TA = +25"C, OSC = Free running, Test Circuit Rgure 12, Unless Otherwise Specified
MIN

TYP

MAX

UNITS

V+ = 3V, RL = 00, +25°C

-

26

100

j1A

O"C < TA < +700 C

-

-

125

j1A

125

j1A

-

150

j1A

V+ = 3V, lOUT = 10mA

-

97

150

(1

O"C < TA < +7O"C

-

-

200

(1

-40"C < TA < +85°C

-

-

200

(1

250

SYMBOL

PARAMETER
Supply Current (Note 3)

1+

TEST CONDITIONS

-4O"C < TA < +85°C
-55°C < TA < + 125°C
OUtput Source Resistance

RoUT

-

-

V+ = 3V (same as 5V conditions)

2.5

4

OOC < TA < +7O"C

1.5

-

-40"C < TA < +85°C

1.5

-55°C < TA < + 125"C

1.0

V+=3V, RL=oo

99

TMIN

~O

80

w

.1

-3

.,. /

·4

·5

./

o

(j

70

IEw

60

~

SO

10

~
20

V

0

o

40

30
LOAD CURRENT (mol)

100
V+.2V
T",,+2SoC

90
~

~
w

-

o

".

~

l

ti
ffi

(j

80

60

so
40

-

30

I

I

40

50

~
w
a:
a:

:::I

U

~
30 a.
a.

V+=5V
20
T,,=+25°C _ 10
20

<

70 .§.

L

10

:::I
til

o
60

........

~

"""'"

/
/

20
~

1.5

B

V+=2V
T,,=+2SOC -

3

1

1

1-

4.5

6

7.5

4
2

~

:t

iii

o
9

FIGURE 1O. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT

V+ .. 5V
T",,+2SoC
400 N·10mA
,
Cl-C1·
w
U
10I'F
z 300

g

;!

8

<

12 .§.
10 ~
w
8 fI!
6

........

LOAD CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT

a:

~

I"--..

./

40

o/
o

w
16 b
14 ~

~

LOAD CURRENT (mol)

IIIw

~

50

10

23456789

0;-

70
60

~ $ 30

~

5a.

""'[b.

/

80

§a:

V
V

~

80

/

FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT

2

~

~

LOAD CURRENT (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT

·2

V

20

w

-

1/

z

8a:

"

100

/

a: 40
~ 30

~

10

~

80

1JlF

C1 ·C2"
1OOl'F

200
100

118~.~~1

1\

0
100

, '\ ,
...

~

1k
10k
100k
OSCILLATOR FREQUENCY (Hz)

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREOUENCY

NOTE 6. These curves Include in the supply current that current fed directly into the load AI from the V+ (See Figure 12). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half,-through the ICL7660S, to the negative side of
the load. Ideally, Your 2VIN, Is 21 l , so VIN X Is Your x Il •

=

=

=

7-122

ICL7660S
Detailed Description

A. The drive Circuitry consumes minimal power.

The ICL76605 contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
2 external capacitors which may be inexpensive 10llF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 13,
which shows an idealized negative voltage converter.
Capacitor C l is charged to a voltage, V+, for the half cycle
when switches 51 and 53 are closed. (Note: 5witches 52
and 54 are open during this half cycle.) During the second
half cycle of operation, switches 52 and 54 are closed, with
51 and 53 open, thereby shifting capacitor C l to C2 such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2 . The ICL76605 approaches this ideal situation
more closely than existing non-mechanical circuits.

B. The output switches have extremely low ON resistance
and virtually no offset.

v+
IS

v+

1------1r-~ (+5V)

C. The impedance of the pump and reservoir capaCitors are
negligible at the pump frequency.
The ICL76605 approaches these conditions for negative
voltage conversion· if large values of C l and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E

2

SI

3

-

NOTE: For large values of Cosc (> 1OOOpF) the values of C l
and C2 should be Increased to 100llF
FIGURE 12. ICL7660S TEST CIRCUIT

This problem is eliminated in the ICL76605 by a logiC
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of 53
and 54 to the correct level to maintain necessary reverse
bias.
The voltage regulator portion of the ICL76605 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation "LV" pin should be connected
to GND, disabling the regulator. For supply voltages greater
than 3.5V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.

Theoretical Power Efficiency Considerations

82

0':'

0/0

VINO

In the ICL76605, the 4 switches of Figure 13 are M05
power switches; 51 is a P-Channel devices and 52, 53 and
54 are N-Channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of
53 and 8 4 must always remain reverse biased with respect
to their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit start up, and under output
short circuit conditions (VOUT = V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latch up.

=1/2C l (V 12 - Vl)

where VI and V2 are the voltages on C l during the pump
and transfer cycles. If the impedances of C l and C2 are
relatively high at the pump frequency (refer to Figure 13)
compared to the value of RL' there will be substantial
difference in the voltages VI and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C l in order to achieve maximum efficiency of
operation.

·· I
··
~
S,!·

JUUL,

,,••
,,
,,
,,

CI

84

:
!

! ~.

5
)

VOUT=-VIN

FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER

Do's and Don'ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however. transient conditions including start-up are okay.
4. When using polarized capacitors. the + terminal of C l
must be connected to pin 2 of the ICL76605 and the +
terminal of C2 must be connected to GND.
5. If the voltage supply driving the ICL76605 has a large
source impedance (250 - 300). then a 2.21lF capacitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V1jlS.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.

In theory a voltage converter can approach 100% efficiency
if certain conditions are met:

7-123

A 1N914 or similar diode placed in parallel with C2 will
prevent the device from latching up under these conditions. (Anode pin 5. Cathode pin 3).

ICL7660S

Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
14 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 12V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GNO)
for supply voltage below 3.5V.

r

Ro vour

Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages. A and B. as shown
in Figure 15. Segment A is the voltage drop across the ESR
of C2 at the instant it goes from being charged by C 1 (current
flowing into C2 ) to being discharged through the load
(current flowing out of C2). The magnitude of this current
change is 2 x lOUT. hence the total drop is 2 x lOUT x
ESR C2 V. Segment B is the voltage change across C2 during
time t2 • the half of the cycle when C2 supplies current the
load. The drop at B is lOUT x t?!C2 V. The peak-to-peak ripple
voltage is the sum of these voltage drops:
(

14B.

14A.

FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT
EQUIVALENT

The output characteristics of the circuit in Figure 14 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (Ao) is a function of
the ON resistance of the intemal MaS switches (shown in
Figure 13). the switching frequency. the value of C 1 and C2 •
and the ESR (equivalent series resistance) of C1 and C2 . A
good first order approximation for Ao is:
Ro

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5. a high value could
potentially swamp out a low 1/fPUMP x C t ) term. rendering an
increase in switching frequency or filter capacitance ineffective. Typical electrolytiC capaCitors may have ESRs as high
as 10Q.

1
2 xfpuMpx C2

+2ESRC2 XloUT

)

Again. a low ESR capacitor will result in a higher· performance output.
Paralleling Devices
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
capacitor. C2 • serves all devices while each device requires
its own pump capacitor. C 1• The resultant output resistance
would be approximately:
RouT (of ICL7660S)
RoUT = -.,--'""'7'"-"--;--;--"",
n (number of devices)

=2(RSWt + RSW3 + ESRet) + 2(RsW2 + Rsw4 + ESRCt ) +

Cascading Devices
(fpUMP =

I

The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However.
due to the finite efficiency of each device. the practical limit
is 10 devices for light loads. The output voltage is defined
by:

~. Rswx = MOSFET switch resistance)
2

Combining the four Rswx terms as Rsw. we see that:

Ro =2 x Rsw +

1

fpuMPxC t

+ 4 X ESRet + ESAc20

VOUT

Rsw. the total switch reSistance. is a function of supply
voltage and temperature (See the Output Source
Resistance graphs). typically 230 at +250 C and 5V. Careful
selection of C t and C2 will reduce the remaining terms.
minimizing the output impedance. High value capacitors will
reduce the 1/(fpuMP x C t ) component. and low ESR capacitors will lower the ESR term. Increasing the oscillator
frequency will reduce the 1/(fpUMP x C 1) term. but may have
the side effect of a net increase in output impedance when
C t > 10j.1F and is not long enough to fully charge the capacitors every cycle. In a typical application where fose
10kHz and C C t C2 iOj.1F:

= = =

Ro

=2 x 23 +

(5 x 103 x 10 x 10-6) + 4 X ESRet + ESRc2

Ro =46 +20 + 5 x ESRcn

=

=-n(VIN).

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT
values.
Changing the ICL7660S Oscillator Frequency

It may be desirable in some applications. due to noise or
other considerations. to alter the oscillator frequency. This
can be achieved simply by one of several methods
described below.
By connecting the Boost Pin (Pin 1) to V+. the oscillator
charge and discharge current is increased and. hence. the
oscillator frequency is increased by approximately 31/ 2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller

7-124

ICL7660S

f

v

t

-(V+)

FIGURE 15. OUTPUT RIPPLE

V+
-------------------t-~....,

ICL7660S
"N"

FIGURE 16. PARALLELING DEVICES

10f1f

VOUT(NOTE)

NOTE:

Your = -nV for1.5V S V+ S 12V
FIGURE 17. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

7-125

ICL7660S
capacitors, e.g. 0.11lF, can be used in conjunction with the
Boost Pin in order to achieve similar output currents
compared to the device free running with C 1 C2 10llF or
1001lF. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).

= =

Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latch up, a 1k.O resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10kO pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be 1/2 of the clock frequency. Output transitions occur on
the positive going edge of the clock.

v+

ply voltage (V+) is applied through diode O2 to capacitor C2 .
The voltage thus created on C2 becomes (2V+) - (2VF) or
twice the supply voltage minus the combined forward voltage drops of diodes 0 1 and O2 ,
The source impedance of the output (VOUT) will depend on
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 600.

VOUT-

......W-_-+

(2V+)' (2VF)

v+
NOTE: D1 and D2 can be any suitable diode
FIGURE 20. POSITIVE VOLTAGE DOUBLER

CMOS
GATE

Combined Negative Voltage Conversion and
Positive Supply Doubling

FIGURE 18. EXTERNAL CLOCKING

It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C 1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C 1 and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C 1 and C2 (from 10llF
to 100IlF).

Figure 21 combines the functions shown in Figure 14 and
Figure 20 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from an
existing +5V supply. In this instance capacitors C1 and Ca
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
V+

V+

~

L-------ll-+-=------+-I~_~

VOUT = (2V+)'

(VFOd • (VF02I

FIGURE 21. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER

FIGURE 19. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling

Voltage Splitting

The ICL7660S may be employed to achieve positive voltage
doubiing using ine circuii snown in Figure 20. in inis appiication, the pump inverter switches of the ICL7660S are used to
charge C 1 to a voltage level of V+ -VF (where V+ is the supply voltage and V F is the forward voltage on C 1 plus the sup-

The bidirectional characteristics can also be used to split a
high supp!y in half, as shC\·':1 in Figure 22. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents

7-126

ICL7660S
can be drawn from the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5,
and -7.5 to a nominal-15V, although with rather high series
output resistance (-2500).

increase in pump and storage capacitors is desirable, and
the values shown provides an output impedance of less than
50 to a load of 1OrnA.

+8V

SOk

r-~~------t-------------------~-oV+

56k
50k

100k

ICL8068

L-~------~----------------~~V_

FIGURE 22. SPLITTING A SUPPLY IN HALF

Regulated Negative Voltage Supply
In Some cases, the output impedance of the ICL7660S can
be a problem, particularly if the load current varies substantially. The circuit of Figure 23 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7660S's output does not respond instantaneously to
change in input, but only after the switching delay. The circuit
shown supplies enough delay to accommodate the
ICL7660S, while maintaining adequate feedback. An

FIGURE 23. REGULATING THE OUTPUT VOLTAGE

Other Applications
Further information on the operation and use of the
ICL7660S may be found in AN051 ·Principles and Applications of the ICL7660 CMOS Voltage Converter".

+5V LOGIC SUPPLY

TILI~:~~ >---------------~~

16
RS232

DATA

+5V

OUTPUT

-SV

FIGURE 24. RS232 LEVELS FROM A SINGLE 5V SUPPLY

7-127

r-1
n
I L..J L

ICL7662
CMOS Voltage Converter

April 1994

Features

Description

No External Diode Needed Over Entire Temperature
Range
• Pin Compatible With ICL7660
• Simple Conversion of +15V Supply to -15V Supply
• Simple Voltage Multiplication (YOUT = (-)nV,N)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 96% Typical Power Efficiency
• Wide Operating Voltage Range 4.5V to 2O.0V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components

Applications
• On Board Negative Supply for Dynamic RAMs
• Localized ILProcessor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
• Up to -20V for Op Amps

The Harris ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance advantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative
for an input range of +4.5V to +20.0V, resulting in complementary output voltages of -4.5V to -20V. Only 2 noncritical
external capacitors are needed for the charge pump and
charge reservoir functions. The ICL7662 can also function
as a voltage doubler, and will generate output voltages up to
+38.6V with a +20V input.
Contained on chip are a series DC power supply regulator,
RC oscillator, voltage level translator, four output power MOS
switches. A unique logic element senses the most negative
voltage in the device and ensures that the output N-Channel
switch source-substrate junctions are not forward biased.
This assures latch up free operation.
The oscillator, when unloaded, oscillates at a nominal frequencyof 10kHz for an input supply voltage of 15.0V. This
frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10V to +20V), the LV pin
is left floating to prevent device latchup.

Pinouts
ICL7662 (PDIP)
TOP VIEW

ICL7662CBD AND IBD (SOIC)
TOP VIEW

~ST08 ~

CAP+

2

GND3

CAP-

4

7

ICL7662 (CAN)
TOP VIEW
V+

osc

6LV
5 VOUT

ICL7662CBD-O (SOIC)
TOP VIEW

NC
GNDU!NC
4

NC 6

CAP- 7

9 Ne

8 VOUT

CAUTION: These devices are sensitive to electrostatic discharge. User. should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-128

File Number

3181.2

ICL7662
Ordering Information
TEMPERATURE
RANGE

PART NUMBER
ICL7662CTV

OOC to +70"C

PACKAGE

8 Pin Metal Can

ICL7662CPA

8 Lead Plastic DI P

ICL7662CBD·O

14 Lead SOIC (N)

ICL7662CBD

14 Lead SOIC (N)

ICL7662ITV

8 Pin Metal Can

·40"C to +85°C

ICL7662IPA

8 Lead Plastic DIP

ICL7662IBD

14 Lead SOIC (N)

ICL7662MTV (Note 1)

·550 C to +125OC

8 Pin Metal Can

NOTE:
1. Add 1883 to part number if 1883B processing Is required.

Functional Block Diagram

V+
t/)

CAP+
RC
OSCILLATOR

VOLTAGE
LEVEL
TRANSLATOR

+2

CAP·

Cis!!!
0:-'
08:

S~

~o:

CJW
W:J:

0:0
Q.

VOUT

LV

LOGIC
NETWORK

VOLTAGE
REGULATOR

7·129

Specifications ICL7662
Absolute Maximum Ratings

Thermal Information

Supply Voltage. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • 22V
Oscillator Input Voltage ••••••.•• -0.3V to (V+ +0.3V) for V+ < 10V
...•.•.•••••..••..•..••• (V+-l0V)to(V++0.3V)forV+> 10V
(Note 1)
Currentlnto LV (Note 1) •••••..••••••••••••. 20j1A for V+ > 10V
Output Short Duration. . • • • . • • • • • • • • • • • . • • . • • • • • • Continuous

Thermal Resistance
9JA
9JC
Plastic DIP Package. • • • • • • • • • . . • • • • 150"C1W
Plastic SOIC Package. • • • • • • • • . • • . • • 1200 CIW
Metal Can. • • ••• • • • . • • • • • •• • • • . •• • 156"C1W SSOCIW
Lead Temperature (Soldering, lOS) .••••••••••.••••••••• 3000C
(SOIC - Lead lips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause p9rmanent damage to the device. This is a stress only raUng and operation
of the device at thess or any other conditions above those indicated in the operaUonal sections of this specifica50n is not implied.

Electrical Specifications
PARAMETER

v+ = 15V, TA = +25°C, c osc = 0, Unless Otherwise Specified. Refer to Figure 14.
SYMBOL

TEST CONDITIONS

MIN

TVP

MAX

UNITS

-

II

V

20

V

Supply Voltage Range - Lo

V+L

RL = 10kn, LV = GND

Min 
I,)

2001

11
510
w
II
8
~ 7
6
5
4
3
2

0

80

~

FIGURE 11. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT

/

J

,
o

1!!O

~

/

~
~

~

,.. t--

/

IE

II:
II:

120

LV=GND

iii

.:l:
160i
w

40

30 40 so 60 70 90
LOAD CURRENT IL (rnA)

>"

1+

RL- OO


z

60

>

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT
100

IS

g

",.

4

100

~~

II.

,.". "".

00

V+ .. 5V
T",,+2SOC

Ii:

V

80

FIGURE 8. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT

V+.5V
T,,_+250C
LV_GND

~

~

,...

+125

FIGURE 7. UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE
2

-V+_1SV
-T,,_+250C
-LV_OPEN

..
~ ..

'\.

OK

0

(Continued)

2

4

/
/
LV. OPEN

6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)

FIGURE 12. FREQUENCY OF OSCILLATION AS A
FUNCTION OF SUPPLY VOLTAGE

7·132

ICL7662
Performance Curves

(See Figure 14, Test Circuit)

(Continued)

ISO
140
130
120
110
.± 100
IZ
110
w
II:
80
II:
::>
()
70
~
60
Do
Do
50
::>
III
40
30
20
10

~

NOTE 4. These curves Include In the supply current that current fed
direcUy into the load RL from the V+ (See Figure 14). Thus, approximately half the supply current goes direcUy to the positive side of the
load, and the other half, through the ICL7662, to the negative side of
the load. Ideally, VOUT=2VIN,ls=2IL, so VIN X Is= VOUTx 'L.

j

L-~~~~~~~~

10

100

__~~~

lK

10K

OSCILLATOR FREQUENCY (Hz)

FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY

Circuit Description
The ICL7662 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive 10J.t.F polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter. Capacitor C l
is charged to a voltage, V+, for the half cycle when switches
SI and S3 are closed. (Note: Switches S2 and S4 are open
during this half cycle.) During the second half cycle of
operation, switches ~ and S4 are closed, with SI and S3
open, thereby shifting capacitor C l negatively by V+ volts.
Charge is then transferred from C l to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and no
load on C2. The ICL7662 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7662, the 4 switches of Figure 15 are MOS power
switches; SI is a P-Channel device and ~, S3 and S4 are NChannel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 and S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON"
resistances. in addition, at circuit startup, and under output
short circuit conditions (VQUT V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.

IT ~

C'+_~~~
-

The voltage regulator portion of the ICL7662 is an integral
part of the anti-latch up circuitry, however its inherent voltage
drop can degracle operation at low voltages. Therefore, to
improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 10V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.

IsV+

_ _ _~-o(+5V)

~~""'l

iCL7662

~

4

...Li
'"=":

~

cosc.l.
(NOTE),J.
t/)

c;,!!!

a:..J

NOTE: For large value of
Cose (> 1000pF)
the values of C, and C. should be
increased to 100!1F.

08::

j~

FIGURE 14. ICL7662 TEST CIRCUIT

::;)a:
ClW
W~

a:O
Q.

S,

8
VINO

i
3

!
:
:

:

~

I

r

So

2

0/0

=

This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (VQUT) together with the
level translators, and switches the substrates of S3 and S4 to
the correct level to maintain necessary reverse bias.

~1---

c,

3

~

JWLhJ"

7-133

FIGURE 15. IDEALIZED NEGATIVE CONVERTER

ICL7662
Theoretical Power Efficiency Considerations
In theory a voltage multiplier can approach 100% effICiency if
certain conditions are met:
A The drive circuitry consumes minimal power

B The output switches have extremely low ON resistance
and virtualiy no offset.

The output characteristics of the circuit in Figure 16A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 16B. The voltage source has
a value of -(V+). The output impedance (Ao) is a function of
the ON resistance of the internal MOS switches (shown in
Rgure 2). the switching frequency. the value of C, and C 2•
and the ESR (equivalent series resistance) of C, and C2 • A
good first order approximation for Ro is:

C The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.

Ro .. 2(RSWI + RSW3 + ESRC, )

1

-;----:::-- + ESRC2
fpUMP xC,

The ICL7662 approaches these conditions for negative voltage multiplication if large values of C, and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:

(fpUMP

=

fose •

2

Rswx

=MOSFET switch resistance)

Combining the four Rswx terms as Rsw. we see that

E =1/2C, (V, 2 - V22)
where V, and V2 are the voltages on C, during the pump
and transfer cycles. If the impedances of C, and C2 are relatively high at the pump frequency (refer to Figure 15) compared to the value of RL. there will be a substantial
difference in the voltages V, and V 2 • Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple. but also to employ a correspondingly large
value for C, in order to achieve maximum efficiency of operation.
Do's and Don'ta
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply voltages greater than 10V.
3. When using polarized capacitors. the + terminal of C,
must be connected to pin 2 of the ICL7662 and the + terminal of C2 must be connected to GROUND.
4. If the voltage supply driving the 7662 has a large source
impedance (250 - 300). then a 2.211F capacitor from pin
8 to ground may be required to limit rate of rise of input
voltage to less than 2VIllS.
5. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up wili occur
under these conditions.

Ro .. 2 x Rsw +

1

+ 4 X ESRC, + ESRC20
fpUMPXC,
Rsw. the total switch resistance. is a function of supply voltage and temperature (See the Output Source Resistance
graphs). typicaliy 240 at +250 C and 15V. and 530 at +250 C
and 5V. Careful selection of C, and C 2 will reduce the
remaining terms. minimizing the output impedance. High
value capacitors will reduce the 1/(fpUMP x C , ) component.
and low FSR capacitors will lower the ESR term. Increasing
the oscillator frequency will reduce the 1/(fpUMP x C, ) term.
but may have the side effect of a net increase in output
impedance when C, > 10!1F and there is no longer enough
time to fuliy charge the capacitors every cycle. In a typical
application where fose = 10kHz and C C , C2 = 1OI1F:

= =

Ao .. 2x23+

1
(5x103 x10x10.6) +4ESRC , +ESRC2

Ao .. 46 + 20 + 5 x ESReO
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5. a high value could
potentialiy swamp out a low 1/(fpUMP x C, ) term. rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100.
Y+

A 1N914 or similar diode placed in paraliel with C2 will prevent the device from latching up under these conditions.
(Anode pin 5. Cathode pin 3).

Typical AppUcaUons

RO

Your

Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Rgure
16 shows typical connections to provide a negative supply

where a positive supply of +4.5V to 20.0V is availab!e, Keep

16A.

168.

FlGYRE 11;' S!MPLE NEGATIVE CONVERTER AND ITS OUTPUT

in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 10V.

7-134

eQUIVALENT

ICL7662
Output Ripple
ESA also affects the ripple voltage seen at the output. The
total ripple is determined by 2V. A and B. as shown in Figure
17. Segment A Is the voltage drop across the ESA of C 2 at
the instant it goes from being charged by C 1 (current flowing
into C2) to being discharged through the load (current flowing out of C2 ). The magnitude of this current change is 2 X
lOUT. hence the total drop is 2 x lOUT X ESAC2V. Segment B
is the voltage change across C2 during time t2' the half of
the cycle when C2 supplies current the load. The drop at B is
lOUT X t2/C2V. The peak-to-peak ripple voltage is the sum of
these voltage drops:
VRIPPLE '"

(

2

1
xfpuMP X C2

+2 ESRC2 x lOUT

ervoir capacitor. C2• serves all devices while each device
requires its own pump capacitor. C 1• The resultant output
resistance would be approximately:

RouT (of ICL7662)

RouT = -:-""7"-'-'--'---'n (number of devices)
Cascading Devices
The ICL7662 may be cascaded as shown in Figure 19 to
produce larger negative multiplication of the initial supply
voltage. However. due to the finite efficiency of each device.
the practical limit is 10 devices for light loads. The output
voltage is defined by:

)

VOUT = -n(VIN).

Again. a low ESA capacitor will result in a higher performance output.
Paralleling Devices

where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately
the weighted sum of the individuallCL7662 Rour values.

Any number of ICL7662 voltage converters may be
paralleled (Figure 18) to reduce output resistance. The res-

FIGURE 17. OUTPUT RIPPLE

FIGURE 18. PARALLELING DEVICES

FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

7-135

ICL7662
Changing the ICL7662 Oscillator Frequency

It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 20. In order to prevent possible
device latchup, a 1kW resistor must be used in series with
the clock output. In the situation where the designer has
generated the external clock frequency using TTL logic, the
addition of a 10kW pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking., as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.

the supply voltage and V F is the forward voltage drop of
diode 0,). On the transfer cycle, the voltage on C, plus the
supply voltage (V+) is applied through diode C2 to capacitor
C 2• The voltage thus created on C2 becomes (2V+) (2V F) or
twice the supply voltage minus the combined forward voltage
drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend on
the output current, but for V+ 15V and an output current of
10mA it will be approximately 70Q.

=

It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, COSC, as shown in
Figure 21. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C,) and reservoir (C2 ) capacitors; this is overcome by
increasing the values of C, and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capaCitor between pin 7 (OSC) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and C2 (from 10mF to
100mF).

VOUT(2V+) - (2VF)

NOTE: 0, and O2 can be any suitable diode.
FIGURE 22. POSITIVE VOLTAGE DOUBLER

v+

VOUT'"

- (nVIN - VFDxl

CMOS
GATE
VOUT" (2V+)·

-

+

(VFDd - (VF02l

FIGURE 20. EXTERNAL CLOCKING
FIGURE 23. COMBINED NEGATIVE CONVERTER
AND POSITIVE DOUBLER

v·

Combined Negative Voltage Conversion and Positive
Supply Doubling

Case

c,
I--_--OVOUT

FIGURE 21. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling
The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C 1 to a voltage laval of V+ =VF (~lIhsrs V+ is

Figure 23 combines the functions shown in Figure 16 and
Figure 22 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from an
existing +5V supply. In this instance capacitors C, and C 3
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C 4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge

pump driver at pin 2 of the device.

7-136

ICL7662
Voltage Splitting
The bidirectional characteristics can also be used to split a
higher supply In half. as shown in Figure 24. The combined
load will be evenly shared between the two sides and. a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel. the output impedance is
much lower than in the standard circuits. and higher currents
can be drawn from the device. By using this circuit. and then
the circuit of Figure 19. +30V can be converted (via +15V.
and -15V) to a nominal -30V. although with rather high series
output resistance (-2500).

~~------~~-----------------.--v+

v0UT-v+-v2

SO!lF

RU
L-~

______

~

________________

~~v_

FIGURE 24. SPLITTING A SUPPLY IN HALF

Regulated Negative Voltage Supply
In some cases. the output impedance of the ICL7662 can be
a problem. particularly if the load current varies substantially.
The circuit of Figure 25 can be used to overcome this by
contrOlling the input voHage. via an ICL7611 low-power
CMOS op amp. in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable. since
the ICL7662s output does not respond instantaneously to a
change in input. but only after the switching delay. The circuit
shown supplies enough delay to accommodate the ICL7662.
while maintaining adequate feedback. An increase in pump
and storage capacitors is desirable. and the values shown
provides an output impedance of less than 50 to a load of
10mA.

+8V

SOk

56k

$Ok

100k

ICL80511

100""

Other Applications
Further information on the operation and use of the ICL7662
may be found in A051 'Principles and Applications of the
ICL7660 CMOS Voltage Converter".

2$Ok
VOLTAGE
ADJUST

FIGURE 25. REGULATING THE OUTPUT VOLTAGE

til

(is!:!:!

a:.J

08:

~;:)
.JtII
;:)a:

ow
w~

a:O

a..

7-137

ICL7663S
CMOS Programmable Micropower
Positive Voltage Regulator

April 1994

Features

Description

• Guaranteed 10J.tA Maximum Quiescent Current Over
All Temperature Ranges

The ICL7663S Super Programmable Micropower Voltage
Regulator is a low power. high efficiency positive voltage
regulator which accepts 1.6V to 16V inputs and provides
adjustable outputs from 1.3V to 16V at currents up to 4OmA.

• Wider Operating Voltage Range - 1.6V to 16V
• Guaranteed Una and Load Regulation Over Entlra
Operating Temperature Range Optional
• 1% Output Voltage Accuracy (ICL7663SA)
• Output Voltage Programmable from 1.3V to 16V

• Improved Temperature Coafflclent of Output Voltage
• 40mA Minimum Output Current with Current Umltlng
• Output Voltages with Programmable Negative Temperature Coafflclents
• Output Shutdown via Current-Umlt Sensing or External Logic Level
• Low Input-ta-Output Voltage Differential
• Improved Direct Replacement for Industry Standard
ICL7663B and Other Second-Source Products

Applications
• Low-Power Portable Instrumentation
• Pagers

It is a direct replacement for the industry standard ICL7663B
offering wlcklr operating voltage and temperature ranges,
Improved output accuracy (ICL7663SA), better temperature
coefficient, guaranteed maximum supply current, and
guaranteed line and load regulation. All improvements are
highlighted in the electrical characteristics section. Critical

parametera Bra guaranteed over the entlra commercial
and Industrial temperature ranges. The ICL7663S1SA
programmable output voltage is set by two external
resistors. The 1% reference accuracy of the ICL7663SA
eliminates the need for trimming the output voltage in most
applications.
The ICL7663S is well suited for battery powered supplies,
featuring 411ft. quiescent current, low VIN to Vour differential,
output current sensing and logic input level shutdown
control. In addition, the ICL7663S has a negative
temperature coefficient output suitable for generating a
temperature compensated display drive voltage for LCD
displays.
The ICL7663S is available in either an 8 lead Plastic DIP,
Ceramic DIP, or SOIC package.

• Handheld Instruments
• LCD Display Modules
• Remote Data Loggera
• Battery-Powered Systems

Pinout

O'

Ordering Information

ICL7663S (PDIP, CERDIP, SOIC)
TOP VIEW

SENSE
V0UT2

VOUT1
GND

PART NUMBER
ICL7663SCBA

TEMPERATURE
RANGE
O"C to +7O"C

PACKAGE
8 Lead SOIC (N)

ICL7663SCPA

8 Lead Plastic DIP

VTC

ICL7663SCJA

8 Lead CerDIP

•

VSET

ICL7663SACBA

8 Lead SOIC (N)

5

SHDN

ICL7663SACPA

8 Lead Plastic DIP

2

7

3

..

VIN>

ICL7663SACJA
ICL7663SIBA

8 Lead CerDIP
·25"0 to +850 C

8 Lead SOIC (N)

ICL7663SIPA

8 Lead Plastic 01 P

ICL7663SIJA

8 Lead CerDIP

ICL7663SAIBA

8 Lead SOIC (N)

ICL7663SAIPA

8 Lead Plastic DIP

ICL7663SAIJA

8 Lead CerDIP

CAUTION: These devices ara aansitiva to atactrastatic discharge. Uaars should lollow proper I.C. Handling Procedures.
Copyright @ Harris Corporation t 994

7-138

File Number

3180.2

Specifications ICL7663S
Absolute Maximum Ratings

Thermal Information

Input Supply Voltage.•..•••.•.••••..••••••••••••••••• +18V
Any Input or Output Voltage (Note 1)
Terminals 1, 2, 3, 5, 6, 7 •.•••••••••••• V1N+O.3V to GND-O.3V
Output Source Current
Terminal 2 .•••..•••••..••••••••••••.••.•••.•..•.. 50mA
Terminal 3 .•.......•...•••.••••••••••..•••••..••• 25mA
Output Sinking Current
Terminal 7 ......•••....•••.••••••••••..•••....•. ·10mA

Thermal Resistance
Ceramic DIP Package •••••••.•••••••
Plastic DIP Package ••••••••••••••••
Plastic SOIC Package •••••••••••..•.
Maximum Junction Temperature
Plastic DIP Package •••.•••.••••.•••••.•...•.... +15O"C
CerOlP Package •••.•••..•...••••••.•••.•.•••.• +175°C
Storage Temperature Range ••...•.•••.•.••••. ·65OC to +15O"C
Lead Temperature (Soldering 1Os) •••••••.••••.•••.... +3OQOC
(SOIC • Lead Tlps Only)

CAUTION: SIrBss.... abo... those listed In "Absolute Maximum Ratings" may cause p8mllJnent damage to the device. This is a stress only rating and operation
of /he devfc8 at l1186e or any o/hlll' conditions abo... thosa Indicated in the operational sections of /his specification Is not Implied.

Operating Conditions
Operating Temperature Range
ICL7663SC ••...••••..•••••.•••.••••••••••• O"C to +70"C
ICL7663SI. ••.•••••..•••••.....••..•.•••• ·250 C to +85°C

Electrical Specifications SpaclficaHons Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Spacifled.
V+1N = 9V, VOUT = 5V, TA = +25°C, Unless Otherwise Spaclfied. Notes 4,5. See Test Circuit, Figure 7

o

Us!!!

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olt

!c;:)
0
....1

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w:=

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Q,

Load Regulation

7·139

Specifications ICL7663S
Electrical Specifications Specifications Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Specified.

=

V+1N 9V, Your
(Continued)

=5V, TA =+25°C, Unless Otherwise Specified. Notes 4, 5. See Test Circuit, Figure 7

Minimum Load Current

NOTES:
1. Connecting any terminal to voltages greater than (V+IN + O.3V) or less than (GNO - O.3V) may cause destructive device latchoolJp. It Is
recommended that no InpulS from sources operating on external power supplies be applied prior to ICL7663S poweroolJp.

2. This parameter refers to the saturation resistance of the MaS pass transistor. The minimum Input-output voltage differential at low current
(under 5mA), can be determined by multiplying the load current (including set resistor current, but not quiescent current) by this
resistance.

3. This output has a positive temperature coefficient. Using It In combination with the Inverting Input of the regulator at VSET, a negative
coeffICient results In the output vottage. See Figure 9 for details. Pin will not source current.
4. All pins are designed to withstand electrostatic discharge (ESO) levels In excess of 2000V.
5. All significant ImprovemenlS over the Industry standard ICL7663 are highlighted.

Functional Diagram

3

8

V+IN o--....---.h ....---

4.875

-

4.870
4.865

-

-

-

;-

;-

100

~

1.4

§

1.2

.

>
z

~

;-

4.860
4.855

U

-

4.HO

I

1.0

V+IN·8V

.,. .,.......-

I
1/

0.4

o

_I

I

0.6

102

~ :;;....-

I

'-' P'"

o

2

4

6

§

>

1.0

f
>

0.8

.

12

14

16

10

....

70

iii'
:l!-

V...... 2V

II:
II:

Ie

v.l.8!7 -

0.4

50
40

.....

30

-

V+IN-15V

VIN-+8.0V
.....,1V1N·2V

60

20

.....

G.2

00

5

10

15

20

25

30

35

40

45

50

100
101
FREQUENCY (Hz)

IoUT2(mA)

FIGURE 3. VoUT2 INPUT-OUTPUT DIFFERENTIAL VB OUTPUT
CURRENT

5.0

I

4.5

.9

T".-~C

~

5.00

3.0

r,,-

2.5

---

~

I

4.75

-

4.50

4.25

~

T".-700C

.9

2.0

3.50

1.0

3.00

0.5

2.75

0

2.50

4

6

8
10
V+IN (V)

12

14

16

I I
I"""'-- b... V+~+15~

3.75 ~

3.25

2

7-141

r-.....

.........

f'"".

i"'-

t"--..
. . . r.......

V+.+8V

l"- f....

......... IJ.

V+_.:;,.............

i
-20

FIGURE 5. QUIESCENT CURRENT AS A FUNCTION OF INPUT
VOLTAGE

lk

I

4.00 ~

1.5

0

102

FIGURE 4. INPUT POWER SUPPLY REJECTION RATIO

I

T".-2OoC

4.0

~

20

80

T"~~OC

0.6

3.5

la

100

1.4
1.2

10

FIGURE 2. V0UT1INPUT-OUTPUT DIFFERENTIAL va OUTPUT
CURRENT

2.0

~

-

10UT1 (mA)

FIGURE 1. VOUT2 OUTPUT VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT

1.6

."

,. ,.,..... . /

V+IN·15V -

8

loUT (mA)

1.8

- -

V+JN·2V

0.8

0.2

1_

T".+~C

1.1

"

-

4.8115

~

2.0

o

1

20
40
TEMPERATURE ("C)

--r-

t'---

60

80

FIGURE 6. QUIESCENT CURRENT AS A FUNCTION OF TEMPERATURE

ICL7663S

Detailed Description
The ICL7663S Is a CMOS integrated circuit incorporating all
the functions of a voltage regulator plus protection circuitry
on a single monolithic chip. Aeferring to the Functional Diagram, the main blocks are a bandgap-type voltage reference,
an error amplifier, and an output driver with both PMOS and
NPN pass transistors.
The bandgap output voltage, trimmed to 1.29V ± 15mV for
the ICL7663SA, and the input voltage at the VSET terminal
are compared in amplifier A. Error amplifier A drives a
P-channel pass transistor which is sufficient for low (under
about 5mA) currents. The high current output is passed by
an NPN bipolar transistor connected as a follower. This
configuration gives more gain and lower output impedance.
Logic-controlled shutdown is implemented via aN-channel
MOS transistor. Current-sensing is achieved with
comparator C, which functions with the VOUT2 terminal. The
ICL7663S has an output (VTC> from a buffer amplifier (6),
which can be used in combination with amplifier A to
generate programmable-temperature-coefficient
output
voltages,
The amplifier, reference and comparator circuitry all operate
at bias levels well below 1jIA to achieve extremely low
quiescent current. This does limit the dynamic response of
the circuits, however, and transients are best dealt with
outside the regulator loop.

Basic Operation

4. IQ quiescent currents measured at GND pin by meter M.
5. S3 when ON, permits normal operation, when OFF, shuts
down both VOUT1 and VOUT2'
FIGURE 7. ICL7663S TEST CIRCUIT

Output Voltages - The resistor divider AiAl is used to
scale the reference voltage, VSET' to the desired output using
the formula VOUT (1 + AiAl) VSET' Suitable arrangements
of these resistors, using a potentiometer, enables exact
values for VOUT to be obtained. In most applications the
potentiometer may be eliminated by using the ICL7663SA.
The ICL7663SA has VSET voltage guaranteed to be 1.29V
±15mV and when used with ±1% tolerance resistors for Al
and A2 the initial output voltage will be within ±2.7% of ideal.

=

The ICL7663S is designed to regulate battery voltages in the
5V to 15V region at maximum load currents of about 5mA to
3OmA. Although intended as low power devices, power dissipation limits must be observed. For example, the power dissipation in the case of a 10V supply regulated down to 2V
with a load current of 30mA clearly exceeds the power dissipation rating of the Mini-DIP:
(10 - 2) (30) (10-3)

NOTES;
1. Sl when closed disables output current limiting.
2. Close S2 for VOUT1, open S2 for VOUT2 '
3.
R2+Rl
Vour= ~ VSET'

=240mW

The circuit of Figure 8 illustrates proper use of the device.
CMOS devices generally require two precautions: every
input pin must go somewhere, and maximum values of
applied voltages and current limits must be rigorously
observed. Neglecting these precautions may lead to, at the
least, incorrect or nonoperation, and at worst, destructive
device failure. To avoid the problem of latch up, do not apply
inputs to any pins before supply voltage is applied.
Input Voltages - The ICL7663S accepts working inputs of
1.5V to 16V. When power is applied, the rate-of-rise of the
input may be hundreds of volts per microsecond. This is
potentially harmful to the regulators, where intemal operating currents are in the nanoampere range. The 0.047IlF
capaCitor on the device side of the switch will limit inputs to a
safe level around 2V/!lS. Use of this capacitor is suggested in
aii applications. in severe rate-oi-rise cases, Ii may be advisable to use an AC network on the SHutDowN pin to delay
output tum-on. Battery charging surges, transients, and
assorted noise signals should be kept from the regulators by
AC filtering, zener protection, or even fusing.

The low leakage current of the VSET terminal allows Al and
A2 to be tens of megohms for minimum additional quiescent
drain current. However, some load current is required for
proper operation, so for extremely low-drain applications it is
necessary to draw at least 1jIA. This can include the current
for A2 and AI'
Output voltages up to nearly the Y,N supply may be obtained
at low load currents, while the low limit is the reference
voltage. The minimum input-output differential in each
regulator is obtained using the Voun, terminal. The inputoutput differential increases to 1.5V when using VOUT2 '
Output Currents - Low output currents of less than 5mA are
obtained with the least input-output differential from the
V0UT1 terminal (connect VOUT2 to Voun). Where higher currents are needed, use VOUT2 (Voun, should be left open in
this case).
High output currents can be obtained only as far as package
dissipation allows. It is strongly recqmmended that output
current-limit sensing be used in such cases.
Current-Umlt Sensing - The on-chip comparator (C in the
Functional Diagram) permits shutdown of the regulator

7-142

ICL7663S
output in the event of excessive current drain. As Figure 8
shows, a current-limiting resistor, RCl' is placed in series
with VOUT2 and the SENSE terminal is connected to the load
side of RCl ' When the current through RCl is high enough to
produce a voltage drop equal to VCl (0.5V) the voltage
feedback is by-passed and the regulator output will be
limited to this current. Therefore, when the maximum load
current (lLOAD) is determined, simply divide Vcl by ILOAD to
obtain the value for RCl'
v+1N SENSE

200
VOUT2

-

In addition, where such a capacitor is used, a current-limiting
resistor is also suggested (see ·Current-Limit Sensing").
Producing Output Voltages with Negative Temperature
Coefficients· The ICL7663S has an additional output which
is O.9V relative to GND and has a tempco of +2.5mVI"C. By
applying this voltage to the inverting input of amplifier A (i.e.,
the VSET pin), output voltages having negative TC may be
produced. The TC of the output voltage is controlled by the
RiR3 ratio (see Figure 9 and its design equations).

1

RCL

VOUT1
VIN

604kn
VTC i - -

0.047""

VSET
GND SHDN

R2

210kn

>--_-oVOUT

10"" VOUT
CL +5 V

.J:

+

Rt

VTC

1 1

-L

EO. l:VOUT = VSET

R2+Rl
Vour - - VSET = 5V
'" Rl

EO. 2:

VCl
ICl = - - = 25mA
RCl

TCVour=

Where: VSET = 1.3V
VTC= 0.9V
TCVTC = +2.5mVI"C
FIGURE 9. GENERATING NEGATIVE TEMPERATURE
COEFFICIENTS

FIGURE 8. POSITIVE REGULATOR WITH CURRENT LIMIT

Logic-Controllable Shutdown • When equipment is not
needed continuously (e.g., in remote data-acquisition
systems), it is desirable to eliminate its drain on the system
until it is required. This usually means switches, with their
unreliable contacts. Instead, the ICL7663S can be shut
down by a logic Signal, leaving only 10 (under 41lA) as a
drain on the power source. Since this pin must not be left
open, it should be tied to ground if not needed. A voltage of
less than 0.3V for the ICL7663S will keep the regulator ON,
and a voltage level of more than 1.4V but less than V+ IN will
turn the outputs OFF. If there is a possibility that the control
signal could exceed the regulator input (V+IN ) the current
from this signal should be limited to 1001lA maximum by a
high value (1 Mil) series resistor. This situation may occur
when the logic Signal originates from a system powered
separately from that of the regulator.
Additional Circuit Precautions • This regulator has poor
rejection of voltage fluctuations from AC sources above 10Hz
or so. To prevent the output from responding (where this might
be a problem), a reservoir capacitor across the load is advised.
The value of this capacitor is chosen so that the regulated output voltage reaches 90% of its final value in 2Oms. From:
IN
(20 x 10-3)
lOUT
1= C - , C = lOUT
= 0.022 - At
0.9VOUT
VOUT

Applications

(/)

Boosting Output Current with External Transistor
The maximum available output current from the ICL7663S is
40mA. To obtain output currents greater than 4OmA, an external NPN transistor is used connected as shown in Figure 10.

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EXTERNAL PIN
POWER
TRANSISTOR

voun

0.470
VIN

lC1!tF

SENSE

t

VSET

VOUT
+5V

GND SHDN

FIGURE 10. BOOSTING OUTPUT CURRENT WITH EXTERNAL
TRANSISTOR

7·143

0.

ICL7663S
Generating a Temperature Compensated Display Drive
VoHage
Temperature has an important effect in the variation of
threshold voltage in multiplexed LCD displays. As
temperature rises, the threshold voltage goes down. For
applications where the display temperature varies widely, a

+6V

temperature compensated display voltage, VDIS~ can be
generated using the ICL7663S. This is shown in Figure 11
for the ICM7233 triplexed LCD display driver.

I
v+1N
VOUYI
LOGIC
SYSTEM,
PROCESSOR,
ETC.

--

Voun
ICL7663S

J

V+
1.8MIl

VSET
300Kll
ICM7233

VTC
2.7110

GND
GND

~

1

VDISP

L

GND

DATA BUS

·11

FIGURE 11. GENERATING A MULTIPLEXED LCD DISPLAY DRIVE VOLTAGE

7-144

=>

ICL7665S
CMOS Micropower Over/Under
Voltage Detector

April 1994

Features

Description

• Guaranteed 101J.A Max.lmum Quiescent Current Over
Temperature

The ICL7665S Super CMOS Micropower OverlUnder
Voltage Detector contains two low power, individually
programmable Voltage detectors on a single CMOS Chip.
Requiring typically 3j.LA for operation, the device is intended
for battery-operated systems and instruments which require
high or low voltage wamings, settable trip points, or fault
monitoring and correction. The trip points and hysteresis of
the two voltage detectors are individually programmed via
extemal resistors. An internal bandgap-type reference
provides an accurate threshold voltage while operating from
any supply in the 1.6V to 16V range.

• Guaranteed Wider Operating Voltage Range Over
Entire Operating Temperature Range

• 2% Threshold Accuracy (ICL7665SA)
• Dual Comparator with Precision Internal Raferenee
• 100ppmi"C Temperature Coefficient of Threshold
VoHage
• 100% Tested at 2V
• Output Current Sinking Ability •••••••••• Up to 20mA
• Individually Programmable Upper end Lower Trip
VoHages and Hysteresis Levels

Applications

The ICL7665S, Super Programmable Over/Under Voltage
Detector is a direct replacement for the industry standard
ICL7665B offering wider operating voltage and temperature
ranges, Improved threshold accuracy (ICL7665SA), and
temperature coefficient, and guaranteed maximum supply
current. All improvements are highlighted in the electrical
characteristics section. All critical parameters are

guaranteed over the entire commercial and Industrial
temperature ranges.

• Pocket Pagera
• Portable Instrumantatlon
• Charging Systems
• Memory Power Back-Up
• Battery Operated Systems
• Portable Computera
• Level Detectors

Pinout

Ordering Information
ICL7665S (SOIC, PDIP, CerDlP)
TOP VIEW
PART NUMBER
ICL7665SCBA
OUT108V+
HYST1 2
7 OUT2
SET1

3

6 SET2

GND

4

5

HYST2

TEMPERATURE
RANGE
0010 +700C

PACKAGE
8 Lead SOIC (N)

ICL7665SCPA

8 Lead Plastic DIP

ICL7665SCJA

8 Lead CerDIP

ICL7665SACBA

8 Lead SOIC (N)

ICL7665SACPA

8 Lead Plastic DIP

ICL7665SACJA
ICL7665SIBA

8 Lead CarDIP
-40"C 10 +85"C

8 Lead SOIC (N)

ICL7665SIPA

8 Lead Plastic DIP

ICL7665SIJA

8 Lead CarDIP

ICL7665SAIBA

8 Lead SOIC (N)

ICL7665SAIPA

8 Lead Plastic DIP

ICL7665SAIJA

8 Lead CarDIP

CAUTION: These devices are sensitive to electrostatic discharge. Uaers ahould follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1994

7-145

File Number

3182.3

Specifications ICL7665S
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Note 2) •••••••••••••••..•••••••• -0.3 to +18V
Output Voltages OUTI and OUT2 ••••••••.•••••.• -o.3V to 18V
(with respect to GND) (Note 2)
Output Voltages HYSTI and HYST2 ••••••••••••• -o.3V to + 18V
(with respect to V+) (Nota 2)
Input Voltages SETI and SET2 .••••. (GND-o.3V) to (V+ V- +O.3V)
(Note 2)
Maximum Sink Output OUTI and OUT2 ••••••.••••••.••• 25mA
Maximum Source Output Current
HYSTt and HYST2 •••••••••••.••••••.••••...••••• -25mA

Thermal Resistance
OJA
OJC
Ceramic DIP Package. • • • • • • • • • • • . • • 115°CM' aooGM'
Plastic DIP Package • • • • • . . • • • • • . • • • I SOOCM'
Plastic SOIC Package. • • • • • • . • • . • • • • 1800CM'
Maximum Junction Temperature (Plastic) •••.•.•...•••. +1500C
Maximum Junction Temperature (CerDI P) +I 75°CStorage Temperature Range ••••.•••••••••••.••••••••.••••• -65°C to +1 WOC
Lead Temperature (Soldering lOs) .••.••••..•••••....• +300oC
(SOIC - Lead lips Only)

CAUTION: Strssses above those Usted in "Absolute Maximum RaYnos" may cause permanent damage to the device. This is 8 stress only rating and cperaYon
of the device at these or any other conditions above those indicated in the operational s8Ctions of this specification Is not implied.

Operating Conditions
Operating Temperature Range
ICL7665SC ••••.••.•••••••••••••••••••••••• OOC to +700C

ICL7665S1. ••...••••••••••.•.••••••••.••••. - 1.3V, OUT1 SWitch ON, HYST1 SWitch ON
VSET1 < 1.3V, OUT1 Switch OFF, HYST1 Switch OFF
VSET2 > 1.3V, OUT2 Switch OFF, HYST2 Switch ON
VSET2 < 1.3V, OUT2 Switch ON, HYST2 Switch OFF
NOTE:
1. See Electrical Specificationsfor exact thresholds.

7·148

----_oGND

....

~~--------

ICL7665S
Typical Performance Curves
u

~Or-----r-----'-----~----~

~

£

1-----1-----+_----+-----.1

1.5

~

~

~

IX

IX

III

!c
III

~ 1.0~-_f--

~

~

1.0

W

:;I

~

~

1.5

a

r----,~+_~"=:oi"":;...._:::.....OC;;'---I

0.5

>

0.5

0
5

10

15

o

20

5

lou-rOUT1 (mAl
FIGURE1. OUT1 SATURATION VOLTAGEASA FUNCTION OF
OUTPUT CURRENT

-16

-20

.

-12

10

15

20

lou-rOUT2 (mAl
FIGURE 2. OUT2 SATURATION VOLTAGE AS A FUNCTION OF
OUTPUT CURRENT

-&.0

004

-4.0

-3.0

-2.0

-1.0

£

£

w

w

c:I

-0.4 ~

-1.0

~

-0.8

~

~.O

I-

5
0

I!:

~

004.0 0~

~>-

~

-2.0 :z:

-5.0 :z:

HYST1 OUTPUT CURRENT (rnA)

HYST2 OUTPUT CURRENT (mAl

FIGURE3. HYST10UTPUTSATURATIONVOLTAGEvsHYST1
OUTPUT CURRENT

H--t

4.0

1 3.5
I-

zw

IX
II:

8

3.0
2.5

~

2.0

~

1.5

II.
II.

III

~

OV VSET1.

V+_16V

~SET2 ~ V+ _

FIGURE4. HYST20UTPUTSATURATIONVOLTAGEvsHYST2
OUTPUT CURRENT
5.0
4.5

f-

t--- t-- ov ~ VSETIo VSET2 ~ v~

V+~8V

1 3.5
!zw
II:
II:

8

V+_2V

~

II.
II.
~

III

1.0
0.5

--±:-

TA--200C

4.0

~ 1/
~ E==: ~

~~

~

3.0
2.5

U

TA-+70"C

1.5
1.0
0.5

o
-25

!c
III

l-

~

4.5

~
~

!c
III
~

5.0

~

IX

~

-1.6

a
>

-~O

IX

-1.2

~

o

0
+20
+40
+60
AMBIENT TEMPERATURE rCI

o

2

..

•

•

10

12

14

16

SUPPLY VOLTAGE (v+l

FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF AMBIENT
TEMPERATURE

7-149

FIGURE 6. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

ICL7665S
Detailed Description
As shown in the Functional Diagram, the ICL7665S consists
of two comparators which compare input voltages on the
SEn and SET2 terminals to an intemal 1.3V bandgap
reference. The outputs from the two comparators drive opendrain N-channel transistors for OUT1 and OUT2, and opendrain P-channel transistors for HYST1 and HYST2 outputs.
Each section, the Under Voltage Detector and the Over
Voltage Detector, is independent of the other, although both
use the internal 1.3V reference. The offset voltages of the
two comparators will normally be unequal so VSETI will
generally not quite equal VSET2 '
The input impedance of the SEn and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting up
the hysteresis, and maximizes the output flexibility. The
operating currents of the bandgap reference and the
comparators are around 100nA each.

v+

between the V+ and GND pins of the ICL7665S can be used
to reduce the rate-of-rise of the supply voltage in battery
applications. In line operated systems, the rate-of-rise of the
supply is limited by other considerations, and is normally not
a problem.
If the SET voltages must be applied before the supply
voltage V+, the input current should be limited to less than
0.5mA by appropriate external resistors, usually required for
voltage setting anyway. A similar precaution should be taken
with the outputs if it is likely that they will be driven by other
circuits to levels outside the supplies at any time.
1.6V

INPUT
OUTI

I.OV
ISOID
tOIF

v+

(5V)

GND
IHIF

HYSTI

V+

(5V)

---+or

GND
V+

(5V)

GND

v+

(5V)

GND

HYST2

FIGURE 8. SWITCHING WAVEFORMS

Simple Threshold Detector
Figure 9 shows the simplest connection of the ICL7665S for
threshold detection. From the graph 98, it can be seen that
at low input voltage OUT1 is OFF, or high, while OUT2 is
ON, or low. As the input rises (e.g., at power-on) toward
VNOM (usually the eventual operating voltage), OUT2 goes
high on reaching VTR2 . If the voltage rises above VNOM as
much as VTR1, oun goes low. The equation giving VSETI
and VSET2 are from Figure 9A:

1.6V-::n...

I.OV ••••

FIGURE 7. TEST CIRCUITS

Precautions
Junction isolated CMOS devices like the ICL7665S have an
inherent SCR or 4-layer PNPN structure distributed throughout the die. Under certain circumstances, this can be
triggered into a potentially destructive high current mode.
This latchup can be triggered by forward-biasing an input or
output with respect to the power supply, or by applying
excess.ive supply voltages. In very low current analog circuits, such as the ICL7665S, this SCR can also be triggered
by applying the input power supply extremely rapidly
("instantaneously"), e.g. through a low impedance battery
and an ONIOFF switch with short lead lengths. The rate-ofrise of the supply voltage can exceed 100VlIlS in such a circuit. A low impedance capacitor (e.g., 0.051lF disc ceramic)

V

-V

SEll -

R11

IN (Ru

'V

-V

+ ~1) , SET2 -

R12

IN (R 12 + ~)

Since the voltage to trip each comparator is nominally 1.3V,
the value VIN for each trip point can be found from
for detector 1
and

7·150

v TR2

=vsm

(R 12 + R2:2l
R12

=1.3 (R12 + ~)
R12

for detector 2

ICL7665S
Either detector may be used alone. as well as both together.
in any of the circuits shown here.

VIN

1

I

RP2
OUTI

~1

OU12

SETI

Ru

SE12

1

RI1

When VIN is very close to one of the trip voltage. normal
variations and noise may cause it to wander back and forth
across this level. leading to erratic output ON and OFF
conditions. The addition of hysteresis. making the trip points
slightly different for rising and falling inputs. will avoid this
condition.

Rpl

v+

R12

Threshold Detector with Hysteresis

-I-

FIGURE 9A. CIRCUIT CONFIGURATION

VOUT
OFF

ON

r-

---l

DETECTOR 2 - / - - - DETECTOR 1

An altemative circuit for obtaining hysteresis is shown in
Figure 11. In this configuration. the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ. but the action is essentially the same.
The goveming equations are given in Table 1. These ignore
.the effects of the resistance of the HYST outputs. but these
can normally be neglected if the resistor values are above
about 100kCl.

FIGURE 9B. TRANSFER CHARACTERISTICS
FIGURE 9. SIMPLE THRESHOLD DETECTOR
VIN

···
·

1

I
I

~

I

R31

Ru

V+

r--

HYSTI

HYST2

R22

r--

I
I

·

SETI

SET2 l -

OUTI

OUT2

OVERVOLTAGE

··:·
I
I
I

r-----<

R21

Figure 10A shows how to set up such hysteresis. while
Figure 108 shows how the hysteresis around each trip point
produces switching action at different points depending on
whether VIN is rising or falling (the arrows indicated direction
of change. The HYST outputs are basically switches which
short out R31 or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value. the trip
point will be controlled by R 1N • R 2N • and R 3N • until the trip
point is reached. As this value is passed. the detector
changes state. R3N is shorted out. and the trip point
becomes controlled by only RIN and R 2N. a lower value. The
input will then have to fall to this new point to restore the
initial comparator state. but as soon as this occurs. the trip
point will be raised again.

VTR2 = VSET2 (R12 + %.l = 1.3 (R 12 + Ru)

~

R12

·

OVERVOLTAGE

RI1

1

1

R12
Rp

FIGURE IDA. CIRCUIT CONFIGURATION

I

Rp

v+
OUT1

R21

OUT

OUT2

HYSTI

HYST2

SET1
RI1

-OFF

VL2 VU2

L---i~~-----L-

I--

+

I

VLI VUl
_________
VIN

VNOU

DETECTOR 2

DETECTOR 1

----l

FIGURE lOB. TRANSFER CHARACTERISTICS
FIGURE 10. THRESHOLD DETECTOR WITH HYSTERESIS

7-151

R22
R32

R31

ON

for detector 2

R12

SE12

1

R12
-'-

FIGURE 11. AN ALTERNATIVE HYSTERESIS CIRCUIT

ICL7665S
TABLE 1. SET-POINT EQUATIONS

NO HYSTERESIS
Ru + R21

Over-Voltage VTR1P

= ---

xVseT1

R21

Ru

324Kn

V+

R22

248Kn

HYST1

HYST2

VSETI

VSET2

OUT1

OUT2

R,2 + R22

Over-Voltage VTR1P

= ---

XVSET2

L--'-'..--i

R'2

t-..-_-..J
~ 100Kn

HYSTERESIS PER FIGURE lOA
VU1

=

Ru +

~,

+ R31
XVSET1

Ru

Over'Voltage VTRIP

= ---

V+

Vu·s.ssv

1Mil

VL_S.45V

XVSET1

=

R'2+~+R32

The ICL7665S can simultaneously monitor several supplies
when connected as shown in Figure 13. The resistors are
chosen such that the sum of the currents through R21A •
R21B • and R31 is equal to the current through R" when the
two input voltage are at the desired low voltage detection
point. The current through R" at this point is equal to 1.3V/
R . The voltage at the VSET input depends on the voltage of
"
both supplies being monitored. The trip voltage of one
supply while the other supply is at the nominal voltage will be
different that the trip voltage when both supplies are below
their nominal voltages.

UnderNoltage VTR1P
R'2 + R22

= ---

X VSET2

R'2
HYSTERESIS PER FIGURE 11
Ru +~,

VU1

= ---

xVSET1

Rn

Over·Voltage VTR1P

VL1

=

Ru +

The other side of the ICL7665S can be used to detect the
absence of negative supplies. The trip points for OUT1
depend on both the negative supply voltages and the actual
voltage of the +5V supply.

~,R3'

--~,+~,

XVSETI

Ru

VU2

=

R'2+~

---

L -_ _ _--<~---.~~WER

Multiple Supply Fault Monitor

X VSET2

R'2

VL2

XVSET2

+IV

274k1l

R'2

V+

R21A

Over-Voltage VTR1P

HYST1

+5V

HYST2

22

~R32

VL2

=

R,2 +
R22 + R32

VL-4.45V

FIGURE 12. FAULT MONITOR FOR A SINGLE SUPPLY

R11

VU2

Vu - 4.SSV

OPEN VOLTAGE
DETECTOR

Ru +~,

VL1

OPEN VOLTAGE
DETECTOR

100kll

Mil

VSET2

X VSET2

R'2

301
kIl

+lSV

787
kIl

+SV

1.D2MIl

R218

Applications
Single Supply Fault Monitor

-6V

1
Mil

-lSV

POWER

OK

Figure 12 shows an over/under voltage fault monitor for a
single supply. The over voltage trip point is centered around
5.5V and the under voltage trip point is centered around
4.5V. Both have some hysteresis to prevent erratic output
ON and OFF conditions. The two outputs are connected in a
wired OR configuration with a pullup resistor to generate a
power OK signal.

7-152

FIGURE 13. MULTIPLE SUPPLY FAULT MONITOR

ICL7665S
Power Fall Warning and PowerupfPowerdown Reset

Combination Low Battery Warning and Low
Battery Disconnect
When using rechargeable batteries in a system, it is
important to keep the batteries from being overdischarged.
The circuit shown in Figure 14 provides a low battery warning and also disconnects the low battery from the rest of the
system to prevent damage to the battery. OUT1 is used to
shutdown the ICL7663S when the battery voltage drops to
the value where the load should be disconnected. As long as
VSET1 is greater than 1.3V, OUT1 is low, but when VSET1
drops below 1.3V, OUT1 goes high shutting off the
ICL7663S. OUT2 is used for low battery warning. When
VSET2 is greater than 1.3V, OUT2 is high and the low battery
warning is on. When VSET2 drops below 1.3V, OUT2 Is low
and the low battery warning goes off. The trip voltage for low
battery warning can be set higher than the trip voltage for
shutdown to give advance low battery waming before the
battery is disconnected.

1

R3t

Figure 15 shows a power fail waming circuit with powerupl
powerdown reset. When the unregulated DC input is above
the trip point, OUT1 Is low. When the DC input drops below
the trip point, OUT1 shuts OFF and the power fail warning
goes high. The voltage on the input of the 7805 will continue
to provide 5V out at 1A until VIN is less than 7.3V, this circuit
will provide a certain amount of warning before the 5V output
begins to drop.
The ICL7665S OUT2 is used to prevent a microprocessor
from writing spurious data to a CMOS battery backup memory by causing OUT2 to go low when the 7805 5V output
drops below the ICL7665S trip point.

v+
~

+

-

--

I

1Wl

HYST1

RZt

HYST2

r--

V+
Rzz

ICL7665S
SET1

SET2 r - - -

~

-

-

v+

Ru

RtZ
OUT1

GND

1

+6V
1A

1000

R32

OUT2

OUT2

ICL7653S

SENSE

SHUTDOWN

~

VSET
GND

~

1Wl

-:;:

I

OUT1

LOW BATTERY SHUTDOWN

-::~

LOW BATTERY WARNING

FIGURE 14. LOW BATTERY WARNING AND LOW BATTERY DISCONNECT

UNREGULATED
DC INPUT

.t

I
4700....

I

7806
SV REGULATOR

~

I

:t

I

470....
B ACKUP
BATTERY

I
v+

r--

HYST1

S.86tea

HYST2

22MO

ICL7665S
VSETt

VSET2

OUT1

OUT2

715tea

2.2Wl
130tea

I

-=.:

1Wl

---<
1MO

-=-=1MO

RESET OR
WRITE
ENABLE
POWER

FAIL
WARNING

FIGURE 15. POWER FAIL WARNING AND POWERUP/POWERDOWN RESET

7-153

ICL7665S
Simple High/Low Temperature Alarm

AC Power Fall and Brownout Detector

Figure 16 illustrates a simple high!low temperature alarm
which uses the ICL7665S with an NPN transistor. The
voltage at the top of Rl is determined by the VeE of the
transistor and the position of Rl'S wiper arm. This voltage
has a negative temperature coefficient. Rl is adjusted so
that VSET2 equals 1.3V when the NPN transistor's
temperature reaches the temperature selected for the high
temperature alarm. When this occurs, OUT2 goes low. R2 is
adjusted so that VSET1 equals 1.3V when the NPN
transistor's temperature reaches the temperature selected
for the low temperature alarm. When the temperature drops
below this limit, OUT1 goes low.

Figure 17 shows a circuit that detects AC undervoltage by
monitoring the secondary side of the transformer. The
capaCitor, C t , is charged through Rl when OUT1 is OFF.
With a normal 100 VAC input to the transformer, OUT1 will
discharge C 1 once every cycle, approximately every 16.7ms.
When the AC input voltage is reduced, OUT1 will stay OFF,
so that C1 does not discharge. When the voltage on C 1
reaches 1.3V, OUT2 turns OFF and the power fail warning
goes high. The time constant, R 1C 1, is chosen such that it
takes longer than 16.7ms to charge C 1 1.3V.

1111111-

+

l

SV

470kO
R3

TEMPERATURE
SENSOR
(GENERAL PURPOSE
NPN TRANSISTOR)

LOW TEMPERATURE
UMITAOJUST

V+
r--

HYST1

R4

22kO

HYST2

-

ICL766SS

27kO
VSETI

VETI

OUT1

OUT2

R6

22MIl

R7

1.SMIl

r:-

1Mil

RS
10Kll
HIGH
TEMPERATURE
UMITADJUST

V+

AI:ARM SIGNAL
1MIl

FORORIVING
LEOS, BELLS,
ETC.

FIGURE 16. SIMPLE HIGHJl..OW TEMPERATURE ALARM

~lII

..

I

I

7806

lhr------~~~·NTrE-R-Eo~~4-70-0~-F~~~--~1 6VRE1GU~TOR 1~--1----Jl~_--SV-'1-A------

11~~~

=-

~~~i~

-=-

..

I

r

HYST1

601kO

+SV

HYST2

ICL7666S

1OOkO

.... -....,

·
1----::'---+
:

R1

1MIl

t-------I

VSETI

VSET2

~ 1MIl

OUT1

OUT2 ~--r'--~r-~-------+

:

••

L-~

________~

••
',h

·!
•

}---~--l-~~-----------------]

FIGURE 17. AC POWER FAIL AND BROWNOUT DETECTOR

7-154

POWER FAIL
WARNING

ICL7673
Automatic Battery Back-Up Switch

April 1994

Features

Description

• Automatically Connects Output to the Greater of
Either Input Supply Voltage

The Harris ICL7673 is a monolithic CMOS battery backup
circuit that offers unique performance advantages over conventional means of switching to a backup supply. The
ICL7673 is intended as a low-cost solution for the switching
of systems between two power supplies; main and battery
backup. The main application is keep-alive-battery power
switching for use in volatile CMOS RAM memory systems
and real time clocks. In many applications this circuit will represent a low insertion voltage loss between the supplies and
load. This circuit features low current consumption, wide
operating voltage range, and exceptionally low leakage
between inputs. Logic outputs are provided that can be used
to indicate which supply is connected and can also be used
to increase the power switching capability of the circuit by
driving external PNP transistors.

• If Main Power to External Equipment Is Lost, Circuit
Will Automatically Connect Battery Backup
• Reconnects Main Power When Restored
• Logic Indicator Signaling Status of Main Power
• Low Impedance Connection Switches
• Low Internal Power Consumption
• Wide Supply Range: .••.•••.•••••••••. 2.SV to 15V
• Low Leakage Between Inputs
• External Transistors May Be Added If Very Large
Currents Need to Be Switched

Ordering Information

Applications
• On Board Battery Backup for Real-Tlma Clocks,
Tlmars, or Volatile RAMs

PART NUMBER

• OveriUnder Voltage Detector

ICL7673CPA

O"C to +7O"C

8 Lead Plastic DIP

ICL7673CBA

O"C to +7O"C

8 Lead SOIC (N)

ICL76731TV

-25°C to +85OC

8 Pin Metal Can

• Peak Voltage Detector
• Other Uses:
- Portable Instruments, Portable Telephones, Une
Operated Equipment

Pinouts

TEMPERATURE
RANGE

PACKAGE

Functional Block Diagram
ICL7673 (SOIC, PDIP)
TOP VIEW

voOav
Vs 2

SaAR

p

7 NC

3

6

GDN4

vP~~----------~~~------~--------~vo
vS~~~-----------r

____--'

PaAR

5NC
ICL7673 (CAN)
TOP VIEW

vp
GND~----------------------------4---~~

Vp> Vs , P1 SWITCH ON AND PaAR SWITCH ON
Vs> Vp, P2 SWITCH ON AND SBAR SWITCH ON

CAUTION: These devices are sensitive to electrostatic discharge. User. should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994

7-155

File Number

3183.1

Specifications ICL7673
Absolute Maximum Ratings

Thermal Information

Input Supply (Vp or Vs) Voltage •.•.•.•••••• GND - 0.3V to +18V
Output Voltages PBAR and SBAR •.••.••..••• GND - 0.3V to + 18V
Peak Current
Input Vp (at Vp = 5V) See Note•••••••••..•.•••••••.•. 38mA
InputVs (atVs = 3V) ••.••••••.•••••.••••••••••••••• 30mA
PeAR or SaAR ...•.••...•.•••••••••.•••••••••••••• 150mA

Thermal Resistance
OJA
OJC
Plastic DIP Package • • • • • • • • • • • • • • • • 1500 CNt
Plastic SOIC Package. • . • • • • • • • . • • • . 1800 CNt
Metal Can •• • • • • • • • . • • • • • • • • • • • • • • 156°CNt 68°CNt
Lead Temperature (Soldering, 1Osee) ...••.........•.... 300°C
(SOIC - Lead lips Only)

NOTE: Derate above +250 C by O.38mA1"C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanant demage to the dsvice. This is a stress only rating and operation
of the device at these or any other conditions above those indicated In the operational sections of this specification is not implied.

Operating Conditions
Operafing Temperature Range:
ICL7673C •••••••••.•.•••••••••..••••••••••• OOC to +700C
ICL76731. •••.••••••••••••••••••.••••••••• -2SOC to +85°C

Electrical Specifications

Storage Temperature ••••••••••.•••••••••••• -65OC to +150°C
Lead Temperature (Soldering, 10s) ...•.••••••.•...•... +3OOoC

TA = +25°C Unless Otherwise Specified

PARAMETER

Input Voltage

Quiescent Supply Current
Switch Resistance P1 (Note 1)

SYMBOL

TEST CONDITIONS

V

2.5

-

15

V

1+

Vp = OV, Vs = 3V,I LOAD = OmA

-

1.5

5

IlA

Vp = 5V, Vs = 3V,I LOAD = 15mA

-

8

15

Q

16

-

Q

6

0.5

-

%I"C

40

100

Q

60

%l"C

ROS(ON)P1

TC(Pl)

Vp = 5V, Vs = 3v, ILOAD = 15mA

-

ROS(ON)P2

Vp = OV, Vs = 3V,I LOAD = 1mA

-

Temperature Coefficient of Switch
Resistance P2

TC(P2)

Leakage Current (Vp to Vs>

Il.(ps)

Il.(sp)

Vp = OV, Vs = 9V,I LOAD = 1mA
Vp = OV, Vs = 3V, ILOAD = 1mA

-

0.7

-

-

0.Q1

20

nA

AtTA =+85°C

35

nA

-

-

Vp = OV, Vs = 3V, ILOAD = 10mA

0.01

50

nA

-

120

-

nA

85

400

mV

120

mV

40

-

mV

Vp =5V, Vs = 3V, ILOAD = 10mA

Vp = 5V, Vs = 3V, ISINK = 3.2mA, ILOAD = 0mA
AtTA = +85°C
Vp = 9V, Vs = 3V, ISiNK = 3.2mA,I LOAD = OmA
Vp = 12V, Vs = 3V, ISINK = 3.2mA
ILOAD = OmA

VOSBAR

Q

26

atTA =+85°C
VOPBAR

5

Q

-

Vp = OV, Vs = 5V, ILOAO = 1mA

Open Drain Output Saturation
Voltages

15

2.5

Vp = OV, ILOAD = OmA

AtTA= +85°C

Open Drain Output Saturation
Voltages

UNITS

Vs = OV, ILOAD = OmA

Vp = 12V, Vs = 3V, ILOAD = 15mA

Leakage Current (Vp to Vs)

MAX

Vs

Vp = 9V, Vs = 3V, ILOAD = 15mA

Switch Resistance P2 (Note 1)

TYP

Vp

AtTA=+85°C

Temperature Coefficient of Switch
Resistance P1

MIN

-

16

50

Q
Q
Q

mV
mV

Vp = OV. Vs = 3V, ISiNK = 3.2mA, ILOAD = OmA

-

150

400

atTA =+85°C

-

210

-

mV

-

85

-

mV

50

-

mV

Vp = OV, Vs = 5V, ISINK =3.2mA ILOAD = 0mA
Vp = OV, Vs = 9V, ISiNK = 3.2mA ILOAD =0mA

7-156

Specifications ICL7673
Electrical Specifications

TA = +25"0 Unless Otherwise Specified

PARAMETER

SYMBOL

Output Leakage Currents of P BAR
andSBAR

ILPBAR

(Continued)
MIN

TYP

MAX

UNITS

Vp = OV. Vs = 15V. ILOAD = OmA

-

50

500

nA

atTA = + 85°C

-

900

-

nA

50

500

nA

TEST CONDITIONS

ILSBAR

-

Vp = 15V. Vs" OV. ILOAD " OmA
atTA=+85°C

Switchover Uncertainty for Complete Sw~ching of Inputs and Open
Drain Outputs

Vp- Vs

Vs = 3V. ISiNK = 3.2mA. ILOAD = 15mA

900

-

nA

±10

±50

mV

NOTE:
1. The Minimum Input to output voltage can be determined by muRlplylng the load current by the switch resistance.

Typical Performance Curves
100

100
ILOAD-1mA- I-- I--

ILOAD-15mA

9:

""

N

Do
UI

1\
1

z 10

c

Iii
13
za:0
1

o

2

......

0

4 6 8 10 12 14 1.
INPUT VOLTAGE Vp (V)

FIGURE 1. ON-RESISTANCE SWITCH P1 AS A FUNCTION OF
INPUT VOLTAGE Vp

o

-

246
8
INPUT VOLTAGE Vs

JVo"VV
If

Vo·SV
Vo -3V

0.8

t-"

Vo .12VL

...ffi~ 0.6

I
j

I

II:
II:

~

0.4

I

~

III

0.2

/

o

2

4

6
8 10 12 14 16
SUPPLY VOLTAGE (V)

I

V

/

~ ,/

V
/

1/

10'

Vo .. 15V

~..... ~

I

-400C
+2SOC
+8SOC

1£

10

FIGURE 2. ON·RESISTANCE SWITCH P2 AS A FUNCTION OF
INPUT VOLTAGE Vs
5

B

r- r-

J/~ ~ V

~ J""'"

I

o

FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

7·157

40
80
120
140
OUTPUT CURRENT (mA)

180

FIGURE 4. P BAR OR SBAR SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

ICL7673
P2 is O.5V, since above this voltage the body-drain parasitic
diode will become forward biased. Complete switching of the
inputs and open-drain outputs typically occurs in 50~s.

Input Voltage
The input operating voltage range for Vp or Vs is 2.5V to
15V. The input supply voltage 01 p or Vs) slew rate should be
limited to 2V per microsecond to avoid potential harm to the
circuit. In line-operated systems, the rate-of-rise (or fall) of
the supply is a function of power supply design. For battery
applications it may be necessary to use a capacitor between
the input and ground pins to limit the rate-of-rise of the supply voltage. A low-impedance capacitor such as a O.047~F
disc ceramic can be used to reduce the rate-of-rise.

Status Indicator Outputs

1pA~

o
FIGURE 5.

The N-Channel open drain output transistors can be used to
indicate which supply is connected, or can be used to drive
extemal PNP transistors to increase the power switching
capability of the circuit. When using external PNP power
transistors, the output current is limited by the beta and thermal characteristics of the power transistors. The application
section details the use of external PNP tranSistors.

__-L____~-L~____~____L -__~
:2
4
5 6
8
10
12
INPUTV,M

Applications

Is LEAKAGE CURRENT Vp TO Va AS A FUNCTION
OF INPUT VOLTAGE

Detailed Description
As shown in the Functional Diagram, the ICL7673 includes a
comparator which senses the input voltages Vp and Vs. The
output of the comparator drives the first inverter and the
open-drain N-Channel transistor PBAR .. The first inverter
drives a large P-Channel switch, P1, a second inverter, and
another open-drain N-Channel transistor, SBAR' The second
inverter drives another large P-Channel switch P2. The
ICL7673, connected to a main and a backup power supply,
will connect the supply of greater potential to its output. The
circuit provides break-before-make switch action as it
switches from main to backup power in the event of a main
power supply failure. For proper operation, inputs Vp and Vs
must not be allowed to float, and, the difference in the two
supplies must be greater than 5QmV. The leakage current
th rough the reverse biased parasitic diode of switch P2 is
very low.

A typical discrete battery backup circuit is illustrated in Figure 6. This approach requires several components, substantial printed circuit board space, and high labor cost. It also
consumes a fairly high quiescent current. The ICL7673 battery backup circuit, illustrated in Figure 7, will often replace
such discrete designs and offer much better performance,
higher reliability, and lower system manufacturing cost. A
trickle charge system could be implemented with an additional resistor and diode as shown in Figure 8. A complete
low power AC to regulated DC system can be implemented
using the ICL7673 and ICL7663S micropower voltage regulator as shown in Figure 9.

t--I---+------.....--t--o

=

STATUS
INDICATOR

NICAD
BATTERY ---Y"
STACK
~

Output Voltage
The output oparating voltage range is 2.5V to 15V. The
insertion loss betwean either input and the output is a function of load current, input voltage, and temperature. This is
due to the P-Channels being operated in their triode region,
and, the ON-resistance of the switches is a function of output
voltage Yo. The ON-resistance of the P-Channels have positive temperature coeffiCients, and therefore as temperature
increases the insertion loss also increases. At low load currents the output voltage is nearly equal to the greater of the
two inputs. The maximum voltage drop across switch P1 or

FIGURE 6. DISCRETE BATTERY BACKUP CIRCUIT

Applications for the ICL7673 include volatile semiconductor
memory storage systems, real-time clocks, timers, alarm
systems, and over/under the voltage detectors. Other systems requiring DC power when the master AC line supply
fails can also use the ICL7673.

7-158

ICL7673
8

+SV
PRIMARY
SUPPLY

2

Vp

Vs

Vo

Pbar

Vo
+SVOR+3V

6

RI
STATUS
INDICATOR

GND

UTHIUM
BATTERY

A typical application. as illustrated in Figure 12. would be a
microprocessor system requiring a 5V supply. In the event of
primary supply failure. the system is powered down. and a
3V battery is employed to maintain clock or volatile memory
data. The main and backup supplies are connected to Vp
and Vs. with the circuit output Vo supplying power to the
clock or volatile memory. The ICL7673 will sense the main
supply. when energized. to be of greater potential than Vs
and connect. via its intemal MOS switches. Vp to output Yo.
The backup input. Vs will be disconnected internally. In the
event of main supply failure. the circuit will sense that the
backup supply is now the greater potential. disconnect Vp
from Yo. and connect Vs.

1

4

GND

FIGURE 7. ICL7673 BATTERY BACKUP CIRCUIT

+SvO-.________J8~V~----~V~
PRIMARY
p
0
SUPPLY

Figure 11 illustrates the use of external PNP power transistors to increase the power switching capability of the circuit.
In this application the output current is limited by the beta
and thermal characteristics of the power transistors.

Vo
+SVOR +3V

If hysteresis is desired for a particular low power application.
positive feedback can be applied between the input Vp and
open drain output SBAR through a resistor as illustrated in
Figure 12. For high power applications hysteresis can be
applied as shown in Figure 13.

RC

2
RECHARGEABLE
BATTERY

=

4

GNDO-------~------~~----~

The ICL7673 can also be used as a clipping circuit as illustrated in Figure 14. With high impedance loads the circuit
output will be nearly equal to the greater of the two input sig~~
.

FIGURE B. APPLICATION REQUIRING RECHARGEABLE
BATTERY BACKUP

Vp

8
BRIDGE
RECTIFIER

ICL7663
REGULATOR
Cl

1201240
VAC

4

Vo

8

2
R2

R,

va

ICL7673
BATTERY
BACK-UP

6

4
GND

Rl
STEPDOWN
TRANSFORMER

FIGURE 9. POWER SUPPLY FOR LOW POWER PORTABLE AC TO DC SYSTEMS

+SV
MAIN
POWER

o--------.----------------------~--------------------~
Vp

ICL7673
BACKUP CIRCUIT

FIGURE 10. TYPICAL MICROPROCESSOR MEMORY APPLICATION

7-159

ICL7673

I

Vs

Vo f--NC
P-

ICL7673

&

2

3

GND

+
3V
BACKUP
SUPPLY

t:

1

•

-j

I

PNP

Ri

Vp

MAIN
SUPPLY

l

Rz

PNP

EXTERNAL
EQUIPMENT

Ra
(NOTE 1)

S-

I

I

1
NOTE 1.

>1Mw

FIGURE 11. HIGH CURRENT BATTERY BACKUP SYSTEM

RS

MAIN
SUPPLY 0

Vp

•
ICL7&73

Vs

S3

=

BATTERY +
BACKUP
GND

GND

o-------~-------+----------~

GND

FIGURE 12. LOW CURRENT BATTERY BACKUP SYSTEM WITH HYSTERESIS

I

J

RZ

PNP

J

1

PNP

RF
Ri

+V

Rs

MAIN
SUPPLY

Jvp

8

2

-f
_

MAIN
SUPPLY
GND

'-Ra

S-

Vs

+

1 f-- NC
PICL7&73 6

~

BACKUP
SUPPLY

4

3

I

FIGURE 13. HIGH CURRENT BACKUP SYSTEM WITH HYSTERESIS

Vp

Vo
ICL7673

Vs
GND

FIGURE 14. CLlPPLlNG CIRCUITS

7-160

EXTERNAL
EQUIPMENT

ICL8211,ICL8212
Programmable Voltage Detectors

April 1994

Features

Description

• High Accuracy Voltage Sensing and Generation

The Harris ICL8211/8212 are micropower bipolar monolithic
integrated circuits intended primarily for precise voltage
detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of
output buffer/drivers.

• Internal Reference 1.15VTyplcal
• Low Sensitivity to Supply Voltage and Temperature
Variations
• Wide Supply Voltage Range Typ. 1.8V to 30V
• Essentially Constant Supply Current Over Full Supply
VoHage Range
• Easy to Set Hysteresis Voltage Range
• Defined Output Current Umlt ICL8211
• High Output Current Capability ICL8212

Specifically, the ICL8211 provides a 7mA current limited output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15V (the internal reference). The
ICL8212 requires a voltage in excess of 1.15V to switch its
output on (no current limit). Both devices have a low current
output (HYSTERESIS) which is switched on for input
voltages in excess of 1.15V. The HYSTERESIS output may
be used to provide positive and noise free output switching
using a simple feedback network.

Applications
Ordering Information

• Low Voltage Sensornndlcator
• High Voltage Sensornndlcator

PART NUMBER

• Nonvolatile Out-of.Voltage Range Sensornndlcator

ICL8211CPA

• Programmable VoHage Reference or Zener Diode

TEMPERATURE
RANGE

PACKAGE

OOC to +70u C

8 Lead Plastic DIP

ICL8211CBA

OOC to +700 C

8 Lead SOIC (N)

• Series or Shunt Power Supply Regulator

ICL8211CTY

Ooc to +700 C

8 Pin Metal Can

• Fixed Value Constant Current Source

ICL8211MTY
(Note 1)

-5500 to +125°C

8 Pin Metal Can

ICL8212CPA

ooc to +7000

8 Lead Plastic DIP

ICL8212CBA

OOC to +700 C
Ooc to +7000

8 Lead SOIC (N)

08::
!i(::)

8 Pin Metal Can

::)a:

·55°C to +125°C

8 Pin Metal Can

ICL8212CTY
ICL8212MTY
(Note 1)

m

....1

w3:

a:o
a..

1. Add 18838 to part number if 8838 processing is required

Pinouts
ICL8211 (CAN)
TOP VIEW
HYSTERESIS
NCOev+
HYSTERESIS 2
7 NC
THRESHOLD 3
OUTPUT 4

6 NC

5 GROUND

4

GROUND

CAUTION: These devices are sensitive 10 electrostalic discharge. Users should lollow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1992

7·161

m

~w

NOTE.

ICL8211 (pDIp, SOIC)
TOP VIEW

asH:!
a:....I

File Number

3184.1

ICL8211,ICL8212
Functional Diagram
VOLTAGE REFERENCE

COMPARATOR

OUTPUT BUFFERS

..

.

8

~----~-------'----~-----------4~----------'------'-----------'-----------O v+
R5
4.51<0
2
HYST

------------1.15V

3

VREF
012

THRESHOLD

013

07
R1
20

,

i:

4
OUTPUT

'/~
~---~. 020
~

,,,

.~

,
,,,
,,
,,
,,

R2
301<0

R6
1001<0

5
GROUND

...."""""

ICL8211 OPTION

111111111111

ICL8212 OPTION

7-162

Specifications ICL8211, ICL8212
Absolute Maximum Ratings

Thermal Information

Supply Voltage •••••••••••••..•••••••••.••••• -O.5V to +30V
Output Voltage •••••••.••.•...••.•••••••.•••• -O.5V to +30V
Hysteresis Voltage • . • • • • • • • • • . • • • . • • • • • • . • • • • +O.5V to -1 OV
Threshold Input Voltage •••••••.•••.. +3OV to -5V with respect to
GROUND and +OV to -30V with respect to V+
Currentinto Any Terminal. .•..•••.......••.•...•..••••• ± 30mA

Thermal Resistance
OJ"
9JC
Plastic DIP Package. . • • • • •• • •• • • •. • 1500 CNI
Plastic SOIC Package. • • • • . • • • • • • • . • 18O"CNI
Metal Can • • • • • . . • • • • • • • • • • • • • • • . . 156°CNI 68"CNI
Lead Temperature (Soldering, lOs) ..•......••••••.•.... 300"C
(SOIC - Lead llps Only)
Currentinto Any Terminal .•..........••.•••..••.•.••... ± 30mA

CAUTION: Stresses .bo.... those Usted in "Absolute Maximum Ratings" may cause permanent dama(18 to the device. This Is a stress only ra6ng and operation
01 the device at these or any other condiUons abo.... those indicated In the opera60nalsections 01 this specification Is not implied.

Operating Conditions
Operating Temperature Range
ICL8211M18212M •••••••••.•••.•••••. " •• -55°C to +1250 C
ICL8211C/8212C ••••...••••..••...••....••. O"C to +70oC

Storage Temperature Range •.••••...•.••••.•• -65OC to +l50oC

Electrical Specifications V+ = 5V, T" = +25°C Unless Otherwise Specified
ICL8211
PARAMETER
Supply Current

Threshold Trip Voltage

Threshold Voltage
Disparity Between
Output & Hysteresis
Output

MIN

TVP

MAX

MIN

TYP

MAX

UNITS

VTH = 1.3V

10

22

40

50

110

250

j1A

VTH = 0.9V

50

140

250

10

20

40

j1A

V+=5V

0.98

1.15

1.19

1.00

1.15

1.19

V

V+=2V

0.98

1.145

1.19

1.00

1.145

1.19

V

V+=30V

1.00

1.165

1.20

1.05

1.165

1.20

V

-

-0.8

-

-

-0.5

-

mV

+25OC (Note 3)

2.0

2.0

V

30

2.2

-

30

2.2

-

30

O"C to +70"C (Note 3)

30

V

1.8

-

1.8

V

-

1.4

-

2.5

-

±2oo

-

ppmi"C

SYMBOL
1+

VTH

VTHP

Guaranteed Operating
Supply Voltage Range

VSUPPLY

Minimum Operating
Supply Voltage Range

VSUPPLY

ICL8212

TEST CONDITIONS
2.0

~~
r-

U

!;

...

§:z:
'"ex:w

a:
a: ·10

U

!;

ICL8211 OR 1CL8212

UJ

...
:z:

10
0.0

·25

iii
w

1/

a:

~
>-

ICL8211 OR ICL8212
I
I
L

-30

:z:

I
1.1 1.15 1.2 2.0 3.0 6.0 8.0 10.0
THRESHOLD VOLTAGE (vTHl
(IRREGULAR SCALE)

-40

Typical Performance Curves

o

·20

75

......~
::>

50

VTH"O.IIV

125

....::!.z

TA-+25oC
OUTPUTS OPEN CIRCUI

w

" - .........

\,

100

w

a:
a:

75

~

50

B

......
::>

25

L...--

25

o

VTH-l.3V

-I

o

10

0.0

20

30

SUPPLY VOLTAGE
FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

12

,.~

125

I
VTH-O.IIV

.......... i'oo..

.......

C
.§.
zw
a:
a:

100

...

a:
a:

75

::>

U

......
::>
UJ

8
6

u

::>

!;

50
25

VTH .. l.3V

f-- ~

o
..ss

-25

- ----

+5

+35

V

+65

......

",

--

8
o
+125

1.12

TEMPERATURE °c
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF TEMPERA·
TURE

7·165

0
TA,,+250C
V+.+5V
-5
Vo .. 0.5V
VHYS " v+ ·0.25V
·10

iii

HY!TEREJIS _
OUTPUT

.......c:c:

1.13

:z:

~

iil3J

m

'"
0

7~,
,~
~
-H
1.14

·15

....

·20

4 -OUTPUT
2

+115

4.0

-

10

....::!.z
~

1.0
1.1
1.15 1.2
2.0
THRESHOLD VOLTAGE (vTHl
(IRREGULAR SCALE)

FIGURE 4. SUPPLY CURRENT AS A FUNCTION OF THRESH·
OLD VOLTAGE

150

w

TA=+250C
V+.+5V
OUTPUTS OPEN
CIRCUIT

UJ

UJ

C

+80

(ICLB211 ONLY)

C

a:
ex:
u

+60

150

125
100

+40

FIGURE2. HYSTERESIS OUTPUT SATURATION CURRENT AS
A FUNCTION OF TEMPERATURE

150

...z~

+20

TEMPERATURE ("C)

FIGURE 1. THRESHOLD INPUT CURRENT AS A FUNCTION OF
THRESHOLD VOLTAGE

::>

.......

·20

~

I

I

100

-

::>

I

;E

V+_+5V
VTH _1.2V
VHYS-4.5V
(OR -O.5V WITH RESPECT
TO V+ SUPPLy)

..s

n
c:

3J
3J

m

·25

Z
....

'i?

~

1- 8mV
1.15

1.16

1.17

-30
1.18

THRESHOLD VOLTAGE
FIGURE 6. OUTPUT SATURATION CURRENTS AS A FUNCTION OF THRESHOLD VOLTAGE

ICL8211,ICL8212
Typical Performance Curves

(ICL8211 ONLY)

(Continued)
1.11

1.151--+--t--:::;o.....;;....t--t-~

1.17
CI

~

~ 1.1.

/

~

1.14 1--f----If-74--+--+--i

§:z:

I
~

/

w

IV

~
9

loa4mA, Voa1V
IHYI a .7"", VHY8 a (V+ -2) V

OUTPUT J1I ",

~

(I)

w

a:

:z:

1.13

-is

I-

V+_+SV
10 a1mA, VOUT a +5V
IHYS - .7"", VHST _ OV
·25

+5
+35
+55
TEMPERATURE (OC)

+IIS

./

1,.;'' '

1.14

V

./

1; ......

1.15

HYSTERESIS OUTPUT

II

"I'"

II

1.13

+125

1

FIGURE 7. THRESHOLD VOLTAGE TO TURN OUTPUTS "JUST
ON" AS A FUNCTION OF TEMPERATURE

2

3 4 5
10
20 304050
SUPPLY VOLTAGE

100

FIGURE 8. THRESHOLD VOLTAGE TO TURN OUTPUTS"JUST
ON" AS A FUNCTION OF SUPPLY VOLTAGE

a

12

TA-+2S0C
V+a+5V

,;

~

~ .....

/

VTH-1.0V

........

I~

V+_+5V
VTH-1.1VVo-1.0V
5
-is

it
-25

+5
+35
+55
+05
TEMPERATURE ~C)

o

+125

0

i

IZ

oS

w
a: ·10
a:

:::0

U

·15

5

-20

5

-25

I!=

!I.!
(I)

I
~

I
I

"!"T" ~I.
~ VT"l.l44V

~

II

~

VTH a1.152V
1.0
10.0
OUTPUT VOLTAGE

"i",.
//

I

II I
II!!!!.

"":'vT
:"'"a l.lav
~~

w
a: -30

I!!

VTHa1.147V

TAa+25OC-

fittl-

-35
-40
·10.00

100.0

FIGURE 10. OUTPUT CURRENT AS A FUNCTION OF OUTPUT
VOLTAGE

VT" 1.143V

I I

_..

IV
0.1

FIGURE 9. OUTPUT SATURATION CURRENT AS A FUNCTION
OF TEMPERATURE

II

·1.00
-0.10
-0.01
HYSTERESIS OUTPUT VOLTAGE

FIGURE 11. HYSTERESIS OUTPUT CURRENT AS A FUNCTION OF HYSTERESIS OUTPUT VOLTAGE

7-166

ICL8211,ICL8212
Typical Performance Curves

(ICL8212

ONLY)
150

150
TA- +2SOC
OUTPUTS OPEN CIRCUIT

125

125

~

~

j:

.a.

100

II:
II:

75

!iw

B

VTH-1.3V

II:
II:

75

~

50

/
I

B

......

50

::>

100

!iw

~

It

TA-·250C
V._.5V
OUTPUTS OPEN CIRCUIT

-

V

::>

1/1

1/1

25

25
VTH-0.8V

o

I

o

o

0.0

10
20
SUPPLY VOLTAGE

'" -

125

~

~ 100

!iw
II':

75

VTH-1.3V_

It
iil

!.
t-

/

20

w

II:
II:

B

...

8

.".,.

\ J

15

"

·25

.5

.35

+65

.05

II:
II:

·10

::>
0

!;
I!:

·15

8
!llw

·20

I

5

II:

w

·25

t1/1

>-

:z:

OUTPUT

1.14

.125

I

!iw

......... HYSTERESIS OUTPUT

10

o

o

I

~

-5

T,,_.2SOC
V._5V
VOUT-4V
VHYS - V. -CI.25V

Z

VTH_O.OV-

-55

4.0

0

[,..-r

25

!;

25

2.0

I

~

50

1.2

30

B
~

1.15

FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF THRESH·
OLD VOLTAGE

I I

V•• 5V
OUTPUTS
OPEN
CIRCUIT

1.1

THRESHOLD VOLTAGE (VTH)
(IRREGULAR SCALE)

FIGURE 12. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

150

1.0

30

1.15

1.16

~

1.17

1.18

1.111 1.20

THRESHOLD VOLTAGE

TEMPERATURE rC)
FIGURE 14. SUPPLY CURRENT AS A FUNCTION OF TEMPER·
ATURE

FIGURE 15. OUTPUT SATURATION CURRENTS AS A FUNCTION OF THRESHOLD VOLTAGE

1.18

1.17

10 ,"1mA, VOUT'" 5V
IHYS - .7"A, VHYS .. OV
1.17
w

w

"

~

1.16

;.J

0

>

90

V

:z:

1/1

w 1.15

V~

II:

j!:

~"

V
./

~

~
:z:

1/1

V
1.15

/V

w

""""'BOTH OUTPUT AND
HYSTERESIS OUTPUT

II:

1.14

1.13
·25

.5

+35

.65

.05

i/

/,

°ir'lL

BOTH OUTPUT ANDH1YSTERjSlj

j!:

V

1.14
-55

7

1.16

1

.125

TEMPERATURE rC)
FIGURE16. THRESHOLDVOLTAGETOTURNOUTPUTS"JUST
ON" AS A FUNCTION OF TEMPERATURE

2

TA-·25oC
loUT - 4mA, VOUT IHYS - ·7J1A, VHYS I
I
I
I
3 45
10
20 30

1V
(V. -2) V
I I

4050

100

SUPPLY VOLTAGE
FIGURE17. THRESHOLDVOLTAGETOTURNOUTPUTS"JUST
ON" AS A FUNCTION OF SUPPLY VOLTAGE

7·167

ICL8211,ICL8212
Typical Perfonnance Curves

Detailed Description

(ICL8212 ONLY) (Continued)

The ICL8211 and ICL8212 use standard linear bipolar
integrated circuit technology with high value thin film
resistors which defme extremely low value currents.

~&r---~--.-~.---.---~--'

~TSAT.
I
a

1__--+_-1

w

~

0.5

> 0.4

~

II:

0.3

01

0.2

~

~

§

CURRENT
(Vo·4.0V)

I

........

Components 0 1 through 0 10 and R 1, R2 and R3 set up an
accurate voltage reference of 1.15V. This reference voltage
is close to the value of the bandgap voltage for silicon and is
highly stable with respect to both temperature and supply
voltage. The deviation from the bandgap voltage is
necessary due to the negative temperature coefficient of the
thin film resistors (-5000 ppm per °C).

r-:.:;;;
V

hI~+--+--+---b,;t£~----1

~ ~LTAGESAT.
CURRENT
(10 a 10mA)

~~

I

1

0.1

Components O2 through Og and R2 make up a constant
current source; O2 and 0 3 are identical and form a current
has 7 times the emitter area of Og, and due to the
mirror.
and Og are forced
current mirror, the collector currents of
to be equal and it can be shown that the collector current in
and Og is

as

V+a+5V

OL-__
-55

~

__

~

__

VTH_1.2V

~

__-L__

~

__

+5
+35
+55
+05
TEMPERATURE <"C)

-25

~

as

as

+125

1
kT
IC(OeoraQ)= ~ x --- In7
q

FIGURE 18. OUTPUT SATURATION VOLTAGE AND CURRENT
AS A FUNCTION OF TEMPERATURE

or approximately 111A at +250 C

i

V

30

~

Where k = Boltzman's Constant
q = Charge on an Electron
and T = Absolute Temperature in OK

as,

Transistors
0 6 , and Or assure that the VCE of 0 3, 0 4 ,
and Og remain constant with supply voltage variations. This
ensures a constant current supply free from variations.

~~H-~++~4-~~~

~

I

20

u

1-+++-f,IHI--H-H--l-+.H+--l
i.-i.-' "1

f---HIJ~i.;'--!-~=FIIVTHr 1·Y8,

The base current of 0 1 provides sufficient start up current for
the constant source; there being two stable states for this
type of circuit - either ON as defined above, or OFF if no
start up current is provided. Leakage current in the transistors is not sufficient in itself to guarantee reliable startup.

I-

10~~HV~4-++H-+-~O~~

O~
0.1

1.0
10.0
OUTPUT VOLTAGE

0 4 is matched to 0 3 and O2; 0 10 is matched to Og. Thus the
IC and VeE of 0 10 are identical to that of Og or as. To

30.0 100.0

FIGURE 19. OUTPUT CURRENT AS A FUNCTION OF OUTPUT
VOLTAGE
0

1

-5

zw

-10

::>

-15

I-

II:
II:

u

,...

::>

S

-20

~w

-25

0

I

II:

-30

~

-3S

w

::c

~

I

which provides:

a10) +

R3

kT

~

q

-- x

R3
__ = 12 (approximately.)
~

The total supply current consumed by the voltage reference
section is approximately 6IIA at room temperature. A voltage
at the THRESHOLD input is compared to the reference 1.15V
by the comparator consisting of transistors all through 0 17.
The outputs from the comparator are limited to two diode
drops less than V+ or approximately 1.1V. Thus the base current into the hysteresis output transistor is limited to about
500nA and the collector current of 019 to 1ClOIlA.

......

I - VTa1.18V

T"a+2SOC _
V+a+10V

~OL-~~L-L-~~

-10.00

Thus 1.5 = V8E (Oe or

A

VT a 1.1S3V

I-

as

'!II

III
VTa1.152V

generate the bandgap voltage, it is necessary to sum a
voltage equal to the base emitter voltage of Og to a voltage
proportional to the difference of the base emitter voltages of
two transistors
and Og operating at two current densities.

__L-~~~

-1.00
-0.10
-0.01
HYSTERESIS OUTPUT VOLTAGE

FIGURE 20. HYSTERESIS OUTPUT CURRENT AS A FUNCTION
OF HYSTERESIS OUTPUT VOLTAGE

In the case of the ICL8211, 0 21 is proportioned to have 70
times the emitter area of 0 20 thereby limiting the output
current to approximately 7mA, whereas for the ICL8212

7-168

ICL8211,ICL8212
almost all the collector current of 0 19 is available for base
drive to 0 21 , resulting in a maximum available collector
current of the order of 30mA. It is advisable to extemally limit
this current to 25mA or less.

Applications
The ICL8211 and ICL8212 are similar in many respects, especially wnh regard to the setup of the input trip condnions and
hysteresis circunry. The following discussion describes both
devices, and where differences occur they are clearly noted.

General Information
Threshold Input Considerations
Although any voltage between -5V and V+ may be applied to
the THRESHOLD terminal, it is recommended that the
THRESHOLD voltage does not exceed about +6V since
above that voltage the threshold input current increases
sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.
The outputs change states with an input THRESHOLD
voltage of approximately 1.15V. Input and output waveforms
are shown in Figure 21 for a simple 1.15V level detector.

A principal application of the ICL8211 is voltage level
detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive supply without a series current
lim iting resistor.
On the other hand the ICL8212 is intended for applications
such as programmable zener references, and voltage
regulators where output currents well in excess of 7mA are
desirable. Therefore, the output of the ICL8212 is not current
limited, and if the output is used to drive an LED, a series
current limiting resistor must be used.
In most applications an input resistor divider network may be
used to generate the 1.15V required for VTH • For high accuracy, currents as large as 5011A may be used, however for
those applications where current limiting may be desirable,
(such as when operating from a battery) currents as low as
6mA may be considered without a great loss of accuracy.
6mA represents a practical minimum, since it is about this
level where the device's own input current becomes a significant percentage of that flowing in the divider network.

v+

INPUT VOLTAGE
(RECOMMENDED
RANGE -5 TO +5V)

VTH

as TTL or CMOS using a single pullup resistor. There is a
guaranteed TTL fanout of 2 for the ICL8211 and 4 for the
ICL8212.

(V+MUSTBE
I:QUALOR
EXCEED 1.8V)

0--+----1
PULLUP RESISTOR

Vo

RU
FIGURE 22. OUTPUT LOGIC INTERFACE

INPUT

"~ffvfM)
V+
OV
V+

ov

-n----n-nI

I

I

I

ICWll OUTPUT

~o-~~

___________

~

I

~ ICL8212 OUTPUT
FtGURE 21. VOLTAGE LEVEL DETECTION

FtGURE 23. INPUT RESISTOR NETWORK CONSIDERATIONS

The HYSTERESIS output is a low current output and is
intended primarily for input threshold voltage hysteresis
applications. If this output is used for other applications it is
suggested that output currents be limited to 1011A or less.

Case 1. High accuracy required, current in resistor network
unimportant Set I 5011A for VTH 1.15V :. Rl ~
20kn

The regular OUTPUT's from either the ICL8211 or ICL8212
may be used to drive most of the common logic families such

=

=

Case 2. Good accuracy required, current in resistor network
important Set I 7.511A for VTH 1.15V :. Rl ~
150kn

7-169

=

=

ICL8211,ICL8212
The disadvantage of the simple detection circuits is that
there is a small but finite input range where the outputs are
neither totally 'ON' nor totally 'OFP. The principle behind
hysteresis is to provide positive feedback to the input trip
point such that there is a voltage difference between the
input voltage necessary to tum the outputs ON and OFF.

INPUT

I

~

".rr

VOLTAGE

The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry. however, is
not limited to applications requiring better noise performance
but may be expanded into highly complex systems with
multiple voltage level detection and memory applicationsrefer to specific applications section.

RI

~~--~----------------------~
Input voltage to change to output states
= (R1;I R2) x 1.15V

-

FIGURE 24. RANGE OF INPUT VOLTAGE GREATER THAN
+1.15 VOLTS

There are two simple methods to apply hysteresis to a circuit
for use in supply voltage level detection. These are shown in
Figure 27.

Setup Procedures For Voltage Level Detection
Case 1. Simple voltage detection no hysteresis
Unless an input voltage of approximately 1.15V is to be
detected. resistor networks will be used to divide or multiply
the unknown voltage to be sensed. Figure 25 shows
procedures on how to set up resistor. networks to detect
INPUT VOLTAGES of any magnitude and polarity.

A third way to obtain hysteresis (ICL8211 only) is to connect
a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external resistance
between the THRESHOLD and GROUND when the
OUTPUT is switched on.

VREF(+YE)
V+

0-

r

The circuit of Figure 27A requires that the full current flowing
in the resistor network be sourced by the HYSTERESIS output. whereas for circuit Figure 27B the current to be sourced
by the HYSTERESIS output will be a function of the ratio of
the two trip points and their values. For low values of hysteresis. circuit Figure 27B is to be preferred due to the offset
voltage of the hysteresis output transistor.

RI

Practical Applications
Low Voltage Battery Indicator (Figure 28)
This application is particularly suitable for portable or remote
operated equipment which requires an indication of a depleted
or discharged battery. The quiescent current taken by the system will be typically 35~ which will increase to 7mA when the
lamp is turned on. R3 will provide hysteresis if required.

Range of input voltage less than +1. 15V
Input voltage to change the output states
(R 1 +~) x 1.15
R2V REF
Rl
. --R1-

Nonvolatile Low Voltage Detector (Figure 29)

FIGURE 25. INPUT RESISTOR NETWORK SETUP
PROCEDURES
For supply voltage level detection applications the input
resistor network is connected across the supply terminals as
shown in Figure 26.
,--_ _ _ _ _ _ _ _ _ _ _....._

.... V+

INPUT VOLTAGE

OR

SUPPLY VOLTAGE

~---------+_-~Vo

FIGURE 26. COMBINED INPUT AND SUPPLY VOLTAGES
Case 2. Use of the HYSTERESIS function

In this application the high trip voltage VTR2 is set to be
above the normal supply voltage range. On power up the
initial condition is A. On momentarily closing switch SI the
operating point changes to B and will remain at B until the
supply voltage drops below VTR1. at which time the output
will revert to condition A. Note that state A is always retained
if the supply voltage is reduced below VTRI (even to zero
volts) and then raised back to VNQM.
Nonvolatile Power Supply Malfunction Recorde
(Figure 30 and Figure 31)
In many systems a transient or an extended abnormal (or
absence of a) supply voltage will cause a system failure.
This failure may take the fonn of infonnation lost in a volatile
semiconductor memory stack. a loss of time in a timer or
even possible irreversible damage to components if a supply
voltage exceeds a certain value.
It is. therefore. necessary to be able to detect and store the
fact that an out-ol-operating range supply voltage condition
has occurred, even in the case where a supply voltage may

7-170

ICL8211,ICL8212

V+

r-----------------------~~--o

Ra

R2

150k0

'--__________________4 __- 0 va
NOTE 1. Ra OPnONAl

Low trip voltage

FIGURE 28. LOW VOLTAGE BATTERY INDICATOR

V _ [(R l +Rz)X1.1S+0.1V]
TRl Rl
volts
High trip voltage

VTR2 = (R l + Rz + Ra) x 1.1SV
Rl
FIGURE 27A.
~----------------------~~--o

V+

r---~------------------'-~----oV+

RQ

Rp

'----------------+--_--0 OUTPUT

'--------------------4---0 va
Low trip voltage

RaRs
[
+Rp] x
VTRl = (Ra + Rs)

~

FlGURE29A.

x1.1SV

High trip voltage

(Rp+ Ra)
VTR2 = - '- - x 1.1SV
Rp

FIGURE 27B.

~

w

..... ~ .......

ON

!c
ti

!;
ti

!;

··
·

: VTR1

________ ,..._..Br__---o...... _____

I~·····

§
-----.

OFF

....---------..

j

"·
•

••

ON

~

!;
ti

~!

•

:VNOM

: VlR2

SUPPLY VOLTAGE _ _

SUPPLY VOLTAGE _ _

FlGURE29B.

FIGURE 27C.
FIGURE 27. TWO ATERNATIVE VOLTAGE DETECTION
CIRCUITS EMPLOYING HYSTERESIS TO
PROVIDE PAIRS OF WELL DEFINED TRIP
VOLTAGES

FIGURE 29. NON·VOLATILE LOW VOLTAGE INDICATOR

7-171

ICL8211, ICL8212
have dropped to zero. Upon power up to the normal
operating voltage this record must have been retained and
easily interrogated. This could be important in the case of a
transient power failure due to a faulty component or
intermittent power supply. open circuit. etc.. where direct
observation of the failure is difficult.
A simple circuit to record an out of range voltage excursion
may be constructed using an ICL8211. an ICL8212 plus a
few resistors. This circuit will operate to 30V without exceeding the maximum ratings of the ICs. The two voltage limits
defining the in range supply voltage may be set to any value
between 2.0V and 30V.
The ICL8212 is used to detect a voltage. V2 • which is the
upper voltage limit to the operating voltage range. The
ICL8211 detects the lower voltage limit of the operating
voltage range. VI. HystereSis is used with the ICL8211 so
that the output can be stable in either state over the
operating voltage range VI to V2 by making V3 - the upper
trip point of the ICL8211 much higher in voltage than V2•
The output of the ICL8212 is used to force the output of the
ICL8211 into the ON state above V2 • Thus there is no value

of the supply voltage that will result in the output of the
ICL8211 changing from the ON state to the OFF state. This
may be achieved only by shorting out R3 for values of supply
voltage between V I and V2.
Constant Current Sources (Figure 32)
The ICL8212 may be used as a constant current source of
value of approximately 25J,1A by connecting the THRESHOLD terminal to GROUND. Similarly the ICL8211 will provide a 130J,1A constant current source. The equivalent
parallel resistance is in the tens of megohms over the supply
voltage range of 2V to 30V. These constant current sources
may be used to provide basing for various circuitry including
differential amplifiers and comparators. See Typical Operating Characteristics for complete information.
Programmable Zener Voltage Reference (Figure 33)
The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using
a resistor network connected to the THRESHOLD terminal
to program the zener voltage
VZENER =

(R I +R2)

RI

x 1.15V.

1-------------------------.----~----_4~--------------------~--1_----o

v+

SI
RESET

OUTPUT

FIGURE 30. NON-VOLATILE POWER SUPPLY MALFUNCTION RECORDER

OUTPUT ICL8211
ICL8212 DISCONNECTED

,

:
:
----r---+'::o--~'r",----,..--+1
:

ON ..-

i
'

: ..:
-----i I-

2

'-r--

I-

-=:!;:-

o

Ia)

CIRCUIT
BEING
PROTECTED

RI

V-

0.01

0.1
1.0
SUPPLY CURRENT (rnA)

100

10

v-

_L-----L~::::Jr-'
(b)

FIGURE 35. HIGH VOLTAGE DUMP CIRCUITS

FIGURE 33. PROGRAMMABLE ZENER VOLTAGE REFERENCE

Precision Voltage Regulator (Figure 34)

Frequency Limit Detector (Figure 36)

The ICL8212 may be used as the controller for a highly stable series voltage regulator. The output voltage is simply programmed, using a resistor divider network RI and R2. Two
capacitors C1 and C2 are required to ensure stability since
the ICL8212 is uncompensated internally.

Simple frequency limit detectors providing a GO/NO-GO output for use with varying amplitude input signals may be conveniently implemented with the ICL8211/8212. In the
application shown, the first ICL8212 is used as a zero crossing detector. The output circuit consisting of R3 , R4 and C2
results in a slow output positive ramp. The negative range is
much faster than the positive range. Rs and R6 provide hysteresis so that under all circumstances the second ICL8212
is turned on for sufficient time to discharge C3 . The time constant of R7 Ca Is much greater than R4 C2. Depending upon
the desired output polarities for low and high input frequencies, either an ICL8211 or an ICL8212 may be used as the
output driver.

V+
R2

This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the Input frequency.
R2+RI

VOUT " ~ x1.15V
FIGURE 34. PRECISION VOLTAGE REGULATOR

Switch Bounce Filter (Figure 37)
Single pole single throw (SPSl) sw~ches are less costly and
more available than single pole double throw (SPDl) switches.

7-173

ICL8211, ICL8212
SPST sw~ches range from push button and slide types to calculator keyboards. A major problem with the use 01 s~ches is
the mechanical bounce of the electrical contacts on closure.
Contact bounce times can range from a fraction of a millisecond to several tens of milliseconds depending upon the sw~ch
type. During this contact bounce time the s~ch may make and
break contact several times. The circu~ shown in Figure 37 provides a rapid charge up of C1 to close to the positive supply
voltage (VI) on a switch closure and a corresponding slow discharge of C1 on a switch break. By proportioning the time constant of Rl C1 to approximately the manufacturer's bounce time
the output as terminal #4 of the ICl821118212 will be a single
transition of state per desired s~ch closure

Low Voltage Power Disconnect (Figure 38)
There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
below a certain value. As an example, the National LMl99
precision reference has an on chip heater which malfunctions with supply voltages below 9V causing an excessive
device temperature. The ICL8212 may be used to detect a
power supply voltage of 9V and turn the power supply off to
the LM199 heater section below that voltage.
For further applications, see AN027 ·Power Supply Design
using the ICL8211 and ICL8212."

v+

OUTPUT
nME CONSTANT RA < ~~ s RM
VARY Rt FOR OPnON ZERO CROSSING DETECTION
VARY R4 TO SET DETEcnON FREQUENCY

.-:.......J INDETERMINATE
INPUT

-.BELOWFo

- - # - - - - - - ' ! I k - - - -.......IL---

OFF r----f~---I,......--··················· ON

1.:V --t+t--------~I-I---

ON~

_ _~ _ _~

FO

OFF

FREQUENCY_

FIGURE 36. FREQUENCY LIMIT DETECTOR
r--------------1--~--._~--O~

r--1r-----------------~--+_~V+

Ra

L------____

+-~__o

FIGURE 37. SWITCH BOUNCE FILTER

Vo

FIGURE 38. LOW VOLTAGE POWER SUPPLY DISCONNECT

7-174

INTELLIGEN- ~ 8
POWERICs
PROTECTION CIRCUITS

PAGE
PROTECTION CIRCUITS SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-2

PROTECTION CIRCUITS DATA SHEETS

SP710

Protected Power Switch with Transient Suppression .......••..•................

8-3

SP720

Electronic Protection Array for ESD and Overvoltage Protection . . . . . . . . . . . . . . . . . . .

8-5

SP720MD-8,
SP720MD,
SP720MM-8,
SP720MM

High Reliability Electronic Protection Array for ESD and Overvoltage Protection. . . . . . .

8-8

SP721

Electronic Protection Array for ESD and Overvoltage Protection. . . . . . . . . . . . . • . . . . .

8-14

8-1

Protection Circuits Selection Guide
PART
NUMBER

DESCRIPTION

SUPPLY
VOLTAGE
RANGE

-4O"C to +1 05"C 3 LeadTO-220

Protected Power Switch

SP720

Protection Array

4.SVto 30V

+VBE Above Vee or -4O"C to + 105"C 16 Lead Plastic DIP and
SOIC
-VBE Below GND

SP720MD-8

Ceramlc Packaged Harris Class B
"Equivalent" SP720 Parts with BackEnd Conformance to MIL-STD-883

4.SVt030V

+VBE Above Vee or -55°C to +125"C 16 Lead Ceramic SBDIP
-VBE Below GND
20 Pad Ceramic LCC

High Reliability Ceramic Packaged
SP720 Parts

4.SVto 30V

+VBE Above Vee or -S5"C to + 125"C 16 Lead Ceramic SBDIP
-VBE Below GND
20 Pad Ceramic LCC

SP721

Protection Array

4.SVt030V

+VBE Above Vee or -40"C to +1 OSoC 8 Lead Plastic DIP and
SOIC
-VBE Below GND

HIP1090

Protected Power Switch

SP720MD
SP720MM

4V to 16V

8-2

16Vto 18.SV

PACKAGE

SP710

SP720MM-8

4Vto 16V

OVER-VOLTAGE
TURN-ON
TEMPERATURE
RANGE
THRESHOLD

16V to 19V

-40"C to +1 OSoC 3 Lead T0-220

SP710
Protected Power Switch
with Transient Suppression

April 1994

Features

Description

• ±90V Transient Suppression

The SP710 is a Power Integrated Circuit designed to
suppress potentially damaging overvoltage transients up to
±90V in amplitude. The device is designed to be operated in
a pass-thru mode which allows the current to flow through
the IC with minimal voltage drop. The protected load circuit
is connected to the output of the SP710. As such, the
protected power switch IC is designed to operate as a
transient suppressor which is capable of driving resistive,
inductive or lamp loads with minimum risk of damage under
stress conditions of over voltage or over current. The SP71 0
is supplied in a 3 lead T0-220AB package.

• 4V to 16V Operating Voltage

• O.SA Current Load Capability
• Over-Voltage Shutdown Protected
• Short-Circuit Current Umltlng
• Over-Temperature Protected Thermal Umltlng
at 150°C (TJ)
• -40°C to +1050 C Operating Temperature Range

Applications

Ordering Information

• Electronic Circuit Breaker
• Transient Suppressor
• Overvoltage Monitor

Pinout

PART NUMBER

TEMPERATURE
RANGE

SP710AS

-40°C to +1 05°C

PACKAGE
3 Lead Plastic
SIP

Functional Block Diagram
SP720(SIP)

,,.. _-_ ............ _-- ........................ __ ... _-_ ... _--_ ............ -.....
,

TOP VIEW
NOTE:
HEAT SINK TAB
INTERNALLY
CONNECTED
TO PIN 2

0

--0

VIN :
1
'

~

_-------.....----------------,,,
~

Rs

~
OR

III
I

I

I

I I I

,

3

:~
,

: LOAD)

VBATT):
1 2 3 [

: Vour

,,:

,,,

0..

VCOMMON
(GND)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @ Harris Corporation 1993

8-3

File Number

tls
W()

0
o::()

!_------_. . --------_ . .-----------.. . . _--_ . . . _---- --.. --.. --------.. ---~
2

-I-

1-0::

,,
,,,
,,
,,,
,,
,,,
,,
,
,,,
,,
,

,,
,,
,,,
,,,
,,
,,
,
,,,
,,
,,,

Z

0(1)

2789.6

Specifications SP710
Absolute Maximum Ratings

Thermal Information

Input Voltage, VIN •••••••••••••••••••••••••••••••••••• 24V
Load Current, lOUT' •••••••••••••••••••••••••••••••• 8OOmA
TransIent Max Voltage, VIN (ISms) ........................ ±90V

Thermal Resistance
9JA
9JC
Plastic SIP. • • • • • • • • • • • • • • • • • • • • • •• • 6O"C/W
4"C1W
Junction Temperature ••••••••••••••••••••••••••••••. 15O"C
Ambient Operallng Temperature ••••••••••••••• -4OOC to +1 05°C
Storage Temperature•••.•••••••••••••••••••• -40"C to +15O"C
Lead Temperatura (During Soldering) ••••••••••••••••••• 265°C
1/16in. ± 1/32ln. (1.59rnrn± 0.79rnrn) from case for lOs maximum

NOTE: Po = (VIN - Vol (10) + (VIN) (ICOMMON)

TJ = TA + (Po) (Thermal Resistance)

CAUTION: S _ abow those listed in 'Absolute Maximum Ratings" may cause perm_ damage to Ihe device. ThIs is 8 stress only ",ting and opfI",tion
of the dl!Jllic6 at thes6 or any other conditions abow those indicated in Ihe "",,,,tiona! ssctiona of this specification is not 1",,1Ied.

Electrical Specifications
PARAMETER

TA =-4OOC to +105°C, VIN

MIN

TYP

MAX

UNfTS

VIN

4

-

16

V

VSHSO

16

-

18.5

V

-

150

-

°C

-

+20

rnA

2

A

0.25

V

-

0.65

V

-

1.05

V

25

rnA

50

rnA

SYMBOL

Input Operating Voltage
Shutdown Voltage

=4V to 16V, Unless Otherwise Specified
CONDITIONS

Shutdown Temperature
Transient Pulse

lOUT

VIN =±90V for ISms Pin 3

=14V, Pin 2 =GND

Short Circuit Current

-20

1

VSAT (Input-ta-OUtput)

VIN

=4V, lOUT = 175rnA

VIN

=9V, lOUT =500rnA

-

VIN =16V, lOUT = 800rnA
Common Current

ICOM

=16V, lOUT =l00mA
VIN = 16V, lOUT =800mA
VIN

Typical Application

,,"..................... -_ ...................... -_ ................... -_ ......... -_ ......... -_ ...............
Vurr

As

: YIN

I

---- -_ ............... ..
VOUT

DASH PANEL LOAD

@~_~a:

--~--~~~~----~~?---------~--~ ~--------~~~--~--~--.--+
INPUT

1:

03

: 3

:

!
:I
:

~

i:

THERMAL
UMiT

I

CURRENT
UMiT

IIII V:i~E III C~iNT II
SHUTDOWN

AMPUFIER

J

:

~

Ii

i

I

.. -.- .... -.... -........-.. ---.--.--.- ..

~

:,
-.-~

VCOMMON

:

(GNO)

:

:(_._._._..... _.. _.

""...S="

INSTRUMENTS

DETECTOR:

,
:

VceSAT

.,b

O.47I'F~ _~
j - ~

:

TO OTHER
UGHTSANO

YLOAD· Yurr - YSAT
(VSAr TYP. < lY AT 8OOmA)

SP720
Electronic Protection Array for
ESD and Overvoltage Protection

April 1994

Features

Description

• ±2A Peak Current Capability

• Proven Interface for ESD

The SP720 is an array of SCRlOiode bipolar structures for
ESO and oller-voltage protection to sensitive input circuits.
The SP720 has 2 protection SCRlOiode device structures
per input. A total of 14 available inputs can be used to
protect up to 14 external signal or bus lines. Over voltage
protection is from the IN (pins 1-7 and 9-15) to V+ or V-. The
SCR structures are designed for fast triggering at a
threshold of one +VBE diode threshold above V+ (Pin 16) or
a -VBE diode threshold below V- (Pin 8). From an IN input, a
clamp to V+ Is activated if a transient pulse causes the input
to be increased to a voltage level greater than one VBE
above V+. A similar clamp to V- is activated if a negative
pulse, one VBE less than V-, is applied to an IN input.

• Oparatlng Temparature Range •••••• -40oC to +105°C

Refer to Application Note AN9304 for further information

• Single-Ended Voltage Range to • • • • • • • • • • • • •• +35V
• Differential Voltage Range to ••••••••••••••• +17.SV
• Designed to Provide OVer-Voltage Protection
• Fast Switching •••••••••••••••••••••• 6ns Rlaetlme
• Low Input Leakages of 1nA at +25°C Typical
• Low Input Capacitance of 3pF Typical
• An Array of 14 SCRIDlode Pelrs

Ordering Information

Applications
• MlcroprocessorlLoglc Input Protection

PART NUMBER

TEMPERATURE

SP720AP

-40°C to + 105°C

16 Lead Plastic DIP

PACKAGE

• Data Bus Protection

SP720AB

~to+105°C

16 Lead Plastic SOIC (N)

• Analog Device Input Protection

SP720ABT

-4QOC to +105°C

16 Lead Plastic SOIC
Tape and Reel

• Voltage Clamp

Pinout

Functional Block Diagram

Z
0(1)

SP720 (PDlP, SOIC)

i=!::

IN

v+

IN

IN

O~

wo

5 0g;
0:

c..

IN
IN

IN

IN

IN
IN

IN

v-

IN

CAUTION: These d""ic:es are sansnive to electrostatic: discharge. Users should Iollow proper I.C. Handling Procedures.
Copyright@Harrls Corporation 1993

8-5

File Number

2791.5

:

Specifications SP720
Absolute Maximum Ratings

Thermal Information

Continuous Supply Voltage, (V+) - (V-) ••••••••••••••••••• +35V
Input Peak Current, liN •••••••••••••••••••••••••••••••• ±2A
Transient Ratings - See Note 2, Figure 1, Table 1

Thermal Resistance
8JA
16 Lead PDIP Package ••••••••••••••••••••••••••• 90"CIW
16 Lead SOIC Package •••••••••••••••••••••••••• 170"CIW
Maximum Package Power Dissipation at +105"0:
Plastic DIP Package ••••••••••••••••••••••••••••• 500mW
Plastic SOIC Package •••••••••••••••••••••••••••• Z70mW
Storage Temperature Range •••••••••••••••••• -65"0 to +15O"C
Junction Temperature •••••••••••••••••••••••••••••• +15O"C
Lead Temperature (Soldering lOs) •••••••••••••••••••• +265°C

CAUTION: Str/lSSSS above those listed in "Absolulll Maximum RaUngs" may caUS6 permanent damage to the devIca. This is a str/lSS only raUng and operation
of the device at these or any other conditions above those indicated In the operational secUons of this specification Is not ImpHed.

Electrical Specifications

TA = -40°C to +105°C; VIN = 0.5Vcc Unless Otherwise SpecJfled

PARAMETER

SYMBOL

Operating Voltage Range,
VSUPPLY [(V+) - (V-)]

TEST CONDITIONS

VSUPPlY

=

=lA (Peak Pulse)

MIN

TYP

MAX

UNITS

-

4.5 to 30

-

V

2
2

-

V
V

Forward Voltage Drop:
IN to VIN toV+

VFWOL
VFWDH

--

Input Leakage Current

liN

-20

5

20

nA

IQUIESCENT

-

50

200

nA

Note 3

-

1.1

-

V

VFWrflFWD: Note 3

-

pF

liN

Quiescent Supply Current
Equivalent SCR ON Threshold

-

1

Input Capacitance

CIN

-

3

Input Switching Speed

IoN

-

6

Equivalent SCR ON Resistance

n
ns

NOTES:
1.

2.

3.

In automotive and battery operated systems, the power supply lines should be extemally protected for load dump and reverse battery.
When the V+ and V-pins are connected to the seme supply voltage source as the device or control line under protection, a current limiting
resistor should be connected in series between the supply and the SP720 pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically O.OlI1F or larger from the V+ and V- pins to ground are recommended.
For ESO testing of the SP720 to MIL-STO-3015.7 Human Body Model (HBM), the results are typically better than 6KV (Condfition 1)
(Figure 1, Table 1). Transient and ESO testing capability is highly dependent on the application. For conditions that are defined as an incircuit method of ESO testing where the V+ and V- pins have a return path to ground, the ESO capability Is typically greater than 15KV
from l00pF through 1.5Kn (Condition 2). For ESO testing of the SP720 to EIAJIC121 Machine Model (MM) standard, the results are
typically better than 1KV (Condition 4). These values were measured by AT&T ESO Lab using the component testing procedures of both
standards., Additional ESO testing for 200pF through 1.5Kn with 60s risetima was done with results better than 9KV (Condition 3).
Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance." These characteristics are given
here for thumb-rule information to determine peak current and dissipation under EOS conditions.

TABLE 1. ESD TEST CONDITIONS
RO

I
H.V.
SUPPLY
±Vo

;

TEST

1

IN

CD

±Vo

Ro

Co

Condition 1

6KV

1.5Kn

l00pF

(HBM)

Condition 2

15KV

1.5Kn

l00pF

(Mod.
HBM)

Condition 3

9KV

1.5Kn

200pF

(Mod.
HBM)

Condition 4

lKV

OKn

200pF

(MM)

OUT
-'-

FIGURE 1. ELECTROSTATIC DISCHARGE TEST
MIL-STD-883D, METHOD 3015.7

8-6

SP720
100

80

1
....
zw

a:
a:

60

I

::>
0

a:
0

U'I

0

2.5

/

T,,_+2S"C
SINGLE PULSE

40

2

V

~

!Ew

a: 1.5
a:

::>
0

i
0

II.

20

o

800

_V

0

a:

I

EQUIV. SAT. ON
THRESHOLD -1.1V

II.

0.5

V

800

L

~

U'I

V
/

a:

T,,_+250C
SINGLE PULSE

1000

1200

o

o

lV

~

/

1 I

I

/
IFWD

VFWD

2

3

FORWARD SCR VOLTAGE DROP (V)

FORWARD SCR VOLTAGE DROP (mV )

FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE

FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE

INPUT
DRIVERS
OR
SIGNAL
SOURCES

Z

0(1)

i=!::

0::)

WO
I-a:
0a: 0

y
IN 8-15

IN 1-7

a..

V+

V-

SP720lNPUT
PROTECTION CIRCUIT
(1 OF 14 ON CHIP)

FIGURE 4. TYPICAL APPUCATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE Y+
OR LESS THAN -1VBE BELOW Y-

8-7

SP720MD-B, SP720MD
SP720MM-B, SP720MM
PRELIMINARY

High Reliability Electronic Protection Array
for ESD and Overvoltage Protection

April 1994

Features

Description

• The SP720MD-8 and SP720MM-8 are Harris Class B
"Equivalent" Parts with Back-End Conformance to
MII-Std-883 for Final Assembly, Electrical Testing,
Burn-In and QC Inspection

The SP720 is a High Reliability Array of SCRlDiode bipolar
structures for ESD and over-voltage protection to sensitive
input circuits. The SP720 has 2 protection SCA/Diode
device structures at each IN input. A total of 14 available IN
inputs can be used to protect up to 14 external signal or bus
lines. Over voltage protection is from the IN to V+ or V-. The
SeR structures are designed for fast triggering at a threshold of one +VeE diode threshold above V+ or at a -VeE diode
threshold below V-. From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to
a voltage level greater than one VeE above V+. A similar
clamp to V- is activated if a negative pulse, one VeE less
than V-, is applied to an IN input.

• ±2A Peak Current Capability
• Single-ended Voltage Range ••••••••••••••• to +35V
• Differential Voltage Range ••••••••••••••• to ±17.5V
• Designed to Provide Over-Voltage Protection
• Fast Switching •••••••••••••••••••••• 6ns Rlsetlme
• Low Input Leakages of 1nA at 25°C Typical

• Proven Interface for ESD

The SP720MD-8 and SP720MM-8 Class B "Equivalenr
Parts conform to Mil-Std-883 through final assembly, electrical test, burn-in and
Inspection. The SP720MD and
SP720MM are High Reliability Ceramic Packaged ICs.

• Military Temperature Range •••••••• -55°C to +125°C

Refer to Application Note AN9304 for further information.

Applications

Ordering Information

• Low Input Capacitance of 3pF Typical

ac

• An Array of 14 SCRlDlode Pairs

• Microprocessor/Logic Inpm Protection

PART
NUMBER

TEMPERATURE
RANGE

• Analog Device Input Protection

SP720MD-8

-55°C to +1250C

16 Lead Ceramic SBDIP

• Voltage Clamp

SP720MD

-5SOC to +125°C

16 Lead Ceramic SBDIP

SP720MM-8

-55°C to +125°C

20 Pad Ceramic LCC

SP720MM

-55°C to +1250C

20 Pad Ceramic LCC

• Data Bus Protection

Pinouts

PACKAGE

Functional Block Diagram

SP720MD (SBDIP)

SP720MM (CLCC)

TOP VIEW

TOP VIEW

IN

-., LiJ L~J L~j LtoJ LUlJ
~J
-.,

§J
-.,
!J
-,
IN !J
-,
v- !J
IN

(SP720MD)

IN

r-., r-, r-, r-., r-'

• II' '10' '11' '12' '13'
~

1i! 1i!

~

~

Copyright © Harris Corporation t994

File Number
8-8

3683

Specifications SP720MD-8, SP720MD, SP720MM-B, SP720MM
Absolute Maximum Ratings

Thermal Information

Continuous Supply Voltage, [(V+) - (V-)) .•••••••.••••••.•• +35V
Input Peak Current, liN (non-repetitive, < 1ms) ••.••••••.•••• ±2A
Max. DC Input Current, liN • . • . .. • • . . . .. • • .. .. • • • • ... t70mA
For ESD Transient Capability - See Note 2, Figure I, Table 1
Storage Temperature Range ..•.....••.••.••• -650 C to +15O"C
Junction Temperature •.••••..•.....•••••.•••••••. " +175°C
Lead Temperature (Soldering lOs). . . . • • . • . • • • • • . • • • • • +265°C

Thermal Resistance
9JC
14°CIW
Sidebraze DIP Package •••••••••••..•
19"CfN
Ceramic LCC ••••••••••••••••..••••
Package Power Dissipation:
Sidebraze DIP Package, up to +93"C .................. 1.0W
Ceramic LCC, up to +10500 ......................... 1.0W
Package Power Dissipation Derating Factor:
Sidebraze DIP Package, above +93°C ••••..•••••• 122mWI"C
Ceramic LCC, above +105°C ••••••...•••.••..•• 14.3mWI"C

CAUTION: Stresses abOIlll those listed In "Absolute Maximum Ratings" may cause permanent damage to the davies. This is • stress only lilting and opIIlIltion
of the device at these or any other condi/i""s aoollll those indicated in the opellltionai ssations of this specification is not irrfJlied.

Operating Conditions
Operating Voltage Range, Single Supply .•••••..•• +4.5V to +3OV
Operating Voltage Range, Split Supply ..•......•. ±225V to t15V

Typical Quiescent Supply Current ...................... 50nA
Operating Temperature Range ••••••.••••••••• -55°C to +125°C

Electrical Specifications TA = -55°C to +125°C; Unless Otherwise Specified
PARAMETER

SYMBOL

Operating Voltage Range

VSUPPlY

TEST CONDITIONS

MIN

TYP

MAX

UNITS

=[(V+) - (V-))

0

4.5
to 30

35

V

.
.

·2

-

V

+2

.
.

-

V

-

+1.5

V

-15

5

+15

nA

50

150

nA

1.1

-

VSUPPlY

Peak Forward/Reverse Voltage Drop
IN to V- (with V- Reference)

VIN • (V·)

liN

IN to V+ (with V+ Reference)

VIN • (V+)

liN

=-IA (Ims Peak Pulse)
=+IA (Ims Peak Pulse)

IN to V· (with V- Reference)

VIN • (V·)

liN

=·100mA to V·

IN to V+ (with V+ Reference)

VIN· (V+)

liN = +100mA to V+

DC Forward/Reverse Voltage Drop

Input Leakage Current

=30V
V- < VIN < V+, VSUPPlY =30V
V- < VIN < V+, VSUPPLY

liN

Quiescent Supply Current

IoUIESCENT

Equivalent SCR ON Threshold

Note 3

Equivalent SCR ON Resistance

VFWriIFWO (Note 3)

Input Capacitance

CIN

Input Switching Speed

ioN

·1.5

-

-

-

1
3
6

V

V
0

pF
nS

NOTE:

Z

0(1)

1. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery.
When the V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting
resistor should be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within
the rated maximum limits. Bypass capacitors of typically O.ot I1F or larger from the V+ and V- pins to ground are recommended.
2. For ESD testing of the SP720 to MIL·STD 883, Method 3015.7, Human Body Model (HBM), the results are typically better than 6KV (Con·
dltion 1). Transient and ESD capability Is highly dependent on the application. For conditions that are defined as an in-circuit method of
ESD testing where the V+ and V· pins have a return path to ground, the ESD capability Is typically greater than 15KV from 100pF through
1.5 KO (Condition 2). For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than
lKV (Condition 4). These values were measured by AT&T ESD Lab using the component testing procedures of both standards. Addl·
tional ESD testing for 200pF through 1.5 KO with 6ns risetime was done with results better than 9KV (Condition 3).
3. Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance". These characteristics are given
here for thumb-rule information to determine peak current and dissipation under EOS conditions.

-l-

t>w=>
1- 0
Oe:
a: 0
D.

TABLE 1. ESD TEST CONDITIONS

RO

TEST

1

I
H.V.

Co

SUPPLY

IN
OUT

±Vo

"':'
FIGURE 1_ ELECTROSTATIC DISCHARGE TEST
MIL-STD-BB3D, METHOD 3015.7

8-9

tVo

Ro

Condition 1

6KV

1.5KO

i

Co
l00pF

(HBM)

Condition 2

15KV

1.5KO

l00pF

(Mod. HBM)

Condition 3

9KV

1.5KO

200pF

(Mod. HBM)

Condition 4

lKV

OKO

200pF

(MM)

I

SP720MD-8. SP720MD. SP720MM-8. SP720MM
100
TA,,2S0C
SINGLE PULSE
80

/

C'

.5.
~

z
w 60
a:
a:
(.)

a:
(.)
Q

a:

i...

2

/

/

::>
-

w:::)

1- 0
Oe:;

a: 0
0.

I'
!.

I,

8-13

SP721
Electronic Protection Array
for ESD and Overvoltage Protection

April 1994

Features

Description

• ±2A Peak Current Capability

The SP721 is an array of SCA/Diode biploar structures for
ESD and Overvoltage protection to sensitive input circuits.
The SP721 has 2 protection SCRlDiode device structures
per input. There are a total of 6 available inputs that can be
used to protect up to 6 external signal or bus lines. Over
voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to
V+orV-.

• Single-Ended Voltage Range •••••••••••••• to +35V
• Differential Voltage Range ••••••••••••••• to ±17.5V
• Designed to Provide Overvoltage Protection
• Fast Switching •••••.••••••••••••.••• 6ns Risetime
• Low Input Leakages of 1nA at +2SoC Typical
• Low Input Capacitance of 3pF Typical
• An Array of 6 SCRlDlode Pairs
• Proven Interface for ESD
• Operating Temperature Range •••••• -400 Cto+10SoC

The SCR structures are designed for fast triggering at a
threshold of one +VBE diode threshold above V+ (Pin 8) or a
-VBE diode threshold below V- (Pin 4). From an IN input, a
clamp to V+ is activated if a transient pulse causes the input
to be increased to a voltage level greater than one VBE
above V+. A similar clamp to V- is activated if a negative
pulse, one VeE less than V-, is applied to an IN input.
Further information is available in Application Note AN9304.
AN9304 applies to both the SP720 and SP721

Applications
• Microprocessor/Logic Input Protection

Ordering Information

• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp

PART NUMBER

TEMPERATURE
RANGE

SP721AP

-40"C to +1 05°C

8 Lead Plastic DIP

SP721AB

-40"C to +1 05°C

8 Lead Plastic SOIC (N)

SP721ABT

-40"C to +1 050 C

8 Lead Plastic SOIC
Tape and Reel

PACKAGE

Functional Block Diagram

Pinout
SP121 (PDIP, SOIC)
TOP VIEW

,CAUTION: These devices are sensnlve to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright @Harris Corporation t 994

8-14

File Number

3590.1

Specifications SP721
Absolute Maximum Ratings

Thermal Information

Continuous Supply Voltage. (V+) - (V-) ••••••.••••••••..•. +35V
Input Peak Current. liN •••••••.•.••••••.••••••••••••••• ±2A
ESD Transient Ratings - See Note 2. Figure 1. Table 1

8JA
Thermal Resistance.
8 Lead DIP Package •••••••••••••••••...••.•.••• 1300 em
8 Lead SOIC Package •••••••••••••••••••••••.••• 1700c1W
Maximum Package Power Dissipation
8 Lead Plastic DIP Package. Up to +l05°C ••••• " •••• 350mW
8 Lead Plastic SOIC Package. Up to +105°C
270mW
Storage Temperature Range •••••••••••••••.•• -65OC to +150°C
Junction Temperature •••••.••.•••••••••••••••••.••. +150°C
Lead Temperature (Soldering lOs) ••••••••••.••••••••• +265°C

CAUTION: Stress... abo"" Ihos8 listed In "'Abso/UIB Maximum Ratings' may cause permanent damage to the davies. This Is • stress only rating and operation
of /he device at /h...e or any other conditions abo"" /hose Indicated in the operational sections of /his specification Is not ImpDeti.

Electrical SpeCifications

TA = -40OC to +1050 C. VIN = 0.5Vcc Unless Otherwise Specified

PARAMETERS

SYMBOL

Operating Voltage Range.
VSUPPlY = [(V+) - (V-))

TEST CONDITIONS

VSUPPlY

Forward Voltage Drop
IN to VIN toV+

VFWDL
VFWDH

Input Leakage Current

IQUIESCENT

Equivalent SCR ON Threshold

Note 3

Equivalent SCR ON Resistance

VFWoliFWo ; Note 3

TYP

MAX

UNITS

-

4.5 to 30

-

V

-

V

-

liN = 1A (Peak Pulse)

liN

Quiescent Supply Current

MIN

2
2

-20

5

+20

nA

-

50

200

nA

1.1

-

V

1

-

n

Input Capacitance

CIN

-

3

-

pF

Input Switching Speed

IoN

-

6

-

ns

NOTES:
1. In automotive and battery operated systems. the power supply lines should be externally protected for load dump and reverse battery.
When the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection. a current limiting
resistor should be connected In series between the external supply and the SP721 supply pins to limit reverse battery current to within
the rated maximum limits. Bypass capacitors of typically O.OlI1F or larger from the V+ and V- Pins to ground are recommended.
2. For ESD testing of the SP721 to MIL-STD 883. Method 3015.7. Human Body Model (HBM). the results are typically better than SkV (Condition 1) (Figure 1. Table 1). Transient and ESD capability Is highly dependent on the application. For conditions that are defined as an
in~ircuit method of ESD testing where the V+ and V- Pins have a return path to ground. the ESD capability is typically greater than 15kV
from 100pF through 1.5kO (Condition 2) or 9kV from 200pF through 1.5kO (Condition 3). For ESD testing of the SP721 to EIAJ IC121
Machine Model (MM). the results are typically better than 1kV (Condition 4).
3. Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance". These characteristiCs are given
here for thumb-rule information to determine peak current and diSSipation under EOS conditions.

I
H.V.
SUPPLY
±Vo

...

TABLE 1. ESD TEST CONDITIONS

RO

rCo

1

TEST

±VO

Ro

Co

Condition 1

SkV

1.5kO

l00pF

(HBM)

Condition 2

15kV

1.5kO

100pF

(Mod.
HBM)

Condition 3

9kV

1.5kO

200pF

(Mod.
HBM)

Condition 4

lkV

OkO

200pF

(MM)

IN
DUT

-=:

FIGURE 1. ELECTROSTATIC DISCHARGE TEST
MIL-STD-883D. METHOD 3015.7

8·15

Z

0(1)

-I-

tis
WO
I-a::

0a:: 0
Q.

SP721
100

80

C

.5.

...z
w

II:
II:

60

::>
()

II:

li!
Q

I...

40

/
/

20

o

600

-V

2.5

/

TA-+26°C
SINGLE PULSE

/

2

V

g

...z
w

II:
II:

1.5

..

II:
()

/

Q

II:

i...
1200

e-nm]bI
EQUIV. SAT. ON

0.5

1000

/1

U

/
800

TA-+2SOC
SINGLE PULSE

0

1/

IFWD
VFWD

1I
2
FORWARD SCR VOLTAGE DROP M

0

FORWARD SCR VOLTAGE DROP (mV)

FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE

~

3

FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE

+Vcc

INPUT
DRIVERS
OR
SIGNAL
SOURCES

T

IN 1·3

IN5·7

V+

SP721
V·

SP721 INPUT PROTECTION CIRCUIT (1 OF 14 ON CHIP)
(PINOUT CONRGURATION SHOWN FOR 8 PIN PACKAGES)

FIGURE 4. TYPICAL APPUCATION OF THE SP721 AS AN INPUT CLAMP FOR OVERVOLTAGE, GREATER THAN W BE ABOVE V+
OR LESS THAN ,WBE BELOW V·

8·16

INTELLIGEN

I--

POWERICs

9

MULTIPLEX COMMUNICATION CIRCUITS

PAGE
MULTIPLEX COMMUNICATION CIRCUITS SELECTION GUIDE .............................. . . . . . .

9-2

MULTIPLEX COMMUNICATION CIRCUITS DATA SHEETS

CDP68HC68S1

Serial Bus Interface. . . . . . . . • . . . . . • . • . . . . • . • . • . . • • . . . . • • • • . . . . • . . . . . . . . . . .

9-3

HIP7010

J1850 Byte Level Interface Circuit. . . . . . • . . . . . . . . • . . . . . . . . . • . . • . . . . . . . . . . . • • .

9-17

HIP7020

J1850 Bus Transceiver I/O for Multiplex Wiring. . . • . . . . . • . . . • . . . • • . . . • . . . . . . . . . •

9-33

HIP7030AO

J1850 8-Bit 68HC05 Microcontroller Emulator Version. • . .. . • • .• . • • •. ••. . . • • . .. ••

9-40

HIP7030A2

J1850 8-Bit 68HC05 Microcontroller. . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . •

9-50

HIP7038A8

J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version. • • . . . • . . . . . . . . • . . . . . . .

9-99

~

)(-

w::::l

...1 0
e.g;
-0
~.

::::I::E
::E::E

o

o

9-1

Multiplex Communication Circuits Selection Guide
PART
NUMBER

DESCRIPTION

APPUCATIONS

SUPPLY
VOLTAGE

TEMPERATURE

PACKAGE

CDP68HC68S1

SPI Serial Bus Interface with
COllision Detection and Arbitration

CCD Bl16-Bit Serial
Bus

3Vt06V

-40"C to +1 OSoC

14 Lead PDIP
and 20 Lead
SOIC

HIP7010

J1850 Byte Level Interface Circuit

J18S0 Class B
Variable Pulse Width
(VPW)

3Vto 6V

-40"C to +12SoC

14 Lead PDIP
andSOIC

HIP7020

J18S0 Bus Transceiver VO for
Multiplex Wiring

J18S0 Class B
Variable Pulse Width
(VPW)

6Vt024V

-4O"C to +12SoC

8 Lead PDIP
and 8 Lead
SOIC

HIP7030AO

J 18S0 8-Bit 68HCOS
Mlcrocontroller Emulator Version

J18S0 Class B
Variable Pulse Width
(VPW)

3Vto 6V

-4OOC to +12SoC

68 Lead PLCC

HIP7030A2

J1850 8-Bit 68HCOS
Microcontroller

J18S0 Class B
Variable Pulse Width
(VPW)

3Vlo 6V

-4OOC to +12SoC

28 Lead PDIP
and 28 Lead
SOIC

HIP7038A8

J1850 8-Blt 68HCOS MicrocontroUer 8K EEPROM Version

J1850 Class B
Variable Pulse Width
(VPW)

SV

-4O"C to + 12SOC

28 Lead
Ceramic SOIC
Flatpack

9-2

CDP68HC68S1

HARRIS
SEMICONDUCTOR

Serial Bus Interface

April 1994

Features

Description

• Differential Bus for Minimal EMI

The CDP68HC6SS1 Serial Bus Inteiface Chip (SBIC) provides
a means of inteifacing in a Small Area Network configuration,
various microcomputers (MCU's) containing serial ports. Such
MCU's include the family of 68HC05 microcontrollers. The SBIC
provides a connection from an MCU's Serial Communication
Intertace (asynchronous UART type inteiface) or Serial Peripheral Intertace (synchronous) to a medium speed asynchronous
two wire differential Signal bus designed to minimize electromagnetic interference. This two wire bus forms the network bus
to which all MCU's are connected (through SBI chips). See Figure 1. Each MCU operates independently and may be added or
deleted from the bus with little or no impact on bus operation.
Such a bus is ideal for inter-microcomputer communication in
hazardous electrical environments such as automobiles, aircraft
or industrial control systems.

• High Common Mode Noise Rejection
• Ideal for Twisted Pair Wiring
• Data Collision Detection
• Bus Arbitration
• Idle Detection
• Programmable Clock Divider
• Power-On Reset

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

COP68HC68S1E

-40oC to +1OsoC

14 Lead POIP

COP68HC68S1M

-40OC to +1OSoC

20 Lead SOIC fY'J)

In addition to acting as bus arbitor and inteiface for microcomputer SCI port to differential bus communication, the
CDP68HC68S1 contains all the circuitry required to convert
and synchronize Non-Return-to-Zero (NRZ) 8-bit data received
on the differential bus and clock the data into a microcomputer's
SPI port. Likewise, data to be sent by a microcomputer's SPI
port is converted to asynchronous format by appending start
and stop bits before transmitting to other microcomputers.
Refer to the data sheet for the CDP68HC05C4 for additional
information regarding CDP68HC05 microcomputers and their
Serial Communications and Serial Peripheral Inteifaces.
The CDP68HC68S1 is supplied in a 14 lead dual-in-line plastic
package (E suffix), and in a 20 lead small outline plastic package (M suffix).
Operating voltage ranges from 4V to 7V and operating temperature ranges from -40°C to +105°C.

~
>

....1 0
-0

o..e:
~.

=>2
22
oo

HIP7010
For enhanced noise immunity, the ClK input is a CMOS Schmitt
trigger input. See Electrical Specifications for input levels.
VPWOUT (Variable Pulse Width Out· Output).

VPWiN (Variable Pulse Width In • Input)
These two lines are used to interface to a J1850 bus transceiver, such as the Harris HIP7020. VPWOUT is the variable
pulse width modulated output of the HIP7010's symbol
encoder circuit. VPWiN is the inverted input to the symbol
decoder of the HIP7010. VPWiN is a schmitt input.
SIN (Serial In • Input).
SOUT (Serial Out· Output).
SCK (Serial Clock· Output).
SACTIVE (Serial Bus Active· Output)
These four lines constitute the synchronous Serial Interface
(SERIAL) interface of the HIP7010. See the Serial Interface
(SERIAL) System for details. SIN, SOUT, and SCK provide
the three principal connections to the Host controller. SIN is a
CMOS input. SOUT and SCK are three-state outputs which
are only activated during serial transfers. The SIN, SOUr, and
SCK pins contain integrated pull-down load devices which
provide termination on the bus whenever it is in a high impedance state. The SACi'iVE pin is a CMOS output, which pulls
low when the HIP7010 is communicating on the serial bus.
See Serial Interface (SERIAL) System and Applications
Information for more details.
RDY (Byte Ready· Input)
The Byte Ready (ROY) line is a "handshaking" input from the
Host. Each rising edge on the ROY pin signifies that the Host has
loaded a byte into its SERIAL transmit register and the HIP7010
can retrieve it (by generating clocks on SCK) when the HIP7010
is ready for the data. See Serial Interface (SERIAL) System
and Applications Information for more details.
The ROY pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.

ii5IE (Idle/Service Request - Output)

In general a Status/Control byte transfer should be performed
each time ii5"LE goes l