1994_Hitachi_LCD_Controller_Driver_LSI_Data_Book 1994 Hitachi LCD Controller Driver LSI Data Book

User Manual: 1994_Hitachi_LCD_Controller_Driver_LSI_Data_Book

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LCD CONTROLLER/DRIVER LSI
DATA BOOK

HITACHI4D

M24T026

When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons
during operation of the user's unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of
Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other
problems that may result from Bi>p!ications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the
written consent of the approprtate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life
support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning
to use the products in MEDICAL APPLICATIONS.

INDEX
General Information

LCD Driver
Character Display
LCD Controller/Driver
Graphic Display LCD Driver
for Small System
Graphic Display LCD Driver 1
(Negative LCD Power Supply Type)
Graphic Display LCD Driver 2
(Positive LCD Power Supply Type)
Segment Display LCD Controller/Driver

LCD Controller

TFT Type LCD Driver

LCD Module Line Up

Contents
•

•

GENERAL INFORMATION

•
•
•

Quick Reference Guide·························································································· ............ ............ 9
Type Number Order ..................................................................................................................... 13
Selection Guide ............. ......... ....... ..... ......... ........... ...... ............ .......... ................ ....... ......... ..... .... 14

•

Differences Between Products ...................................................................................................... 17

•
•

Package Information··················································································································· .. 24
Notes on Mounting ..................................................................................................................... 31

•
•

The Information of TCP ............................................................................................................... 38
Chip Shipment Products ............................................................................................................... 100

•
•

Reliability and Quality Assurance············································· ...................................................... 123
Reliability Test Data of LCD Drivers ............................................................................................. 130

•
•

Flat Plastic Package (QFP) Mounting Methods .............................................................................. 134
Liquid Crystal Driving M€~hods················· ..................................................................................... 137

DATA SHEETS

•

•

•

LCD Driver
HD44100R
HD66100F
HD61100A
HD61200

........................................................................
........................................................................
........................................................................
........................................................................

151
161
174
186

Character Display LCD ControllerIDriver
HD43160AH Controller with Built·in Character Generator············································· ..................
HD44780U LCD· II Dot Matrix Liquid Crystal Display Controller/Driver ..........................................
HD66702 LCD·II/E20 Dot Matrix Liquid Crystal Display Controller/Driver ....................................
HD66710 LCD·II/F8 Dot Matrix Liquid Crystal Display Controller/Driver .......................................
HD66712 LCD·II/F12 Dot Matrix Liquid Crystal Display Controller/Driver ....................................

199
214
273
334
411

Graphic Display LCD Driver for Small System
HD44102
Dot Matrix Liquid Crystal Graphic
HD44103
Dot Matrix Liquid Crystal Graphic
HD44105
Dot Matrix Liquid Crystal Graphic
Dot Matrix Liquid Crystal Graphic
HD61102
Dot Matrix Liquid Crystal Graphic
HD61103A
HD61202
Dot Matrix Liquid Crystal Graphic
HD61203
Dot Matrix Liquid Crystal Graphic

489
511
519
528
556
580
612

HD66108
•

LCD
LCD
LCD
LCD

Driver
Driver
Driver
Driver

with
with
with
with

40·Channel
80·Channel
80·Channel
80·Channel

Outputs
Outputs
Outputs
Outputs

Display
Display
Display
Display
Display
Display
Display

Column Driver ..........................................
Common Driver .......................................
Common Driver .......................................
Column Driver ..........................................
Common Driver .......................................
Column Driver ..........................................
Common Driver .......................................

RAM· Provided 165·Channel LCD Driver for Liquid Crystal Dot Matrix Graphics············ 638

Graphic Display LCD Driver 1 (Negative LCD Power Supply Type)
HD66204
Dot Matrix Liquid Crystal Graphic Display Column Driver with 80·Channel Outputs ...... 691
HD66205
Dot Matrix Liquid Crystal Graphic Display Common Driver with 80·Channel Outputs ... 706
HD66214T
80·Channel Column Driver in Micro·TCP .................................................................. 722
HD66224T
HD66215T

Dot Matrix Liquid Crystal Graphic Display Column Driver with 80·Channel Outputs· ..... 737
Common Driver for a Dot Matrix Liquid Crystal Graphic Display with 100·Channel Outputs ...... 751

•

Graphic Display LCD Driver 2 (Positive LCD Power Supply Type)
HD66106F
LCD Driver for High Voltage···· ................................................................................ 772
HD66107T
LCD Driver for High Voltage" .................................................................................. 787
HD66110RT Column Driver···················· ..................................................................................... 807

•

Segment Display LCD ControllerIDriver
HD61602/HD61603 Segment Type LCD Driver .............................................................................. 841
HD61604/HD61605 Segment Type LCD Driver .............................................................................. 871

HD66115T

160·Channel Common Driver Packaged in a Slim Tape Carrier Package··· ..................... 824

• LCD Controller
HD61830/HD61830B LCD Timing Controller (LCDC) .................................................898
HD63645/HD64645/HD64646 LCD Timing Controller (LCTC) .........................................934
• Low Power LCD Chipset
HD66503 240 Channel Row Driver with Internal LCD Timing Circuit .....................................979
HD66520 4-Level Grayscale Display Column Driver with Internal Bit-map RAM ............................996
• TFfType LCD Driver
HD66300T Horizontal DriverforTFf-Type LCD Color TV ............................................ 1027
HD66310T TFT-Type LCD Driver for VDT ......................................................... 1088
HD66330T 64-Level Gray Scale Driver for TFT Uquid Crystal Display ................................... 1108
•

LCD MODULE liNE UP
Graphic Display LCD Module ..................................................................... 1129
Character Display LCD Module ................................................................... 1130
Graphic Display LCD Module (Reflection type) ...................................................... 1132
Graphic Display LCD Module (with EL backlight) .................................................... 1132
Graphic Display LCD Module (with CFL backlight) ................................................... 1132
Character Display LCD Module ................................................................... 1134
Character Display LCD Module (with LCD backlight) ................................................. 1134
Segment-Type LDC Module ...................................................................... 1134

HITACHI SALES OFFICE ..............................................................................1136

General
Information

Quick Reference Guide
Type

Extension Driver

Type Number

HD44100R

HD66100F

HD61100A

HD61200

Power supply for
internal circuits (V)

2.7 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

Power supply for
LCD driver circuits (V)

13

6

17

17

Power
dissipation (mW)

5

5

5

5

Operating
temperature (DC)

-20 to +75·'

-20 to +75·'

-20 to +75·'

-20 to +75

80

80

80

2.5

2.5

Memory

ROM (bit)

LCD driver

Common

20

Column

40 (20)

RAM (bit)

Instruction set
Operation
frequency (MHz)

0.4

Duty

Statio-ll33

Statio-1/16

Statio-1/100

1/32-1/128

Package

FP-60A
Chip

FP-100

FP-100

FP-100

Type

Column Driver

Type Number

HD66204

HD66214T

HD66224T

HD66106

HD66107T

HD66110RT

Power supply for
internal circuits (V)

2.7105.5

2.7105.5

2.5105.5

4.5105.5

4.5 10 5.5

2.7105.5

28

28

28

37

37

40

Power
dissipation (mW)

15

15

15

15

25

25

Operating
temperature (OC)

-2010 +75·'

-2010 +75

-2010 +75

-20 10 +75

-2010 +75

-2010 +75

80

80

80

80

160

160

8

8

8 MHz at5 V
6.5 MHz at3 V

6

8

12MHzat5V
10MHzat3V

Power supply for
. LCD driver circuits (V)

Memory

ROM (bit)
RAM (bit)

LCD driver

Common
Column

Instruction set
Opera~on

frequency (MHz)
Duty

1164-11240

1164-11240

1164-11240

1/100-1/480

1/100-1/480

11100-11480

Package

FP-l00
TFP100
Chip

TCP

SLiM-TCP

FP-l00
TFP100
Chip

TCP

SLiM-TCP

*1 -40 to +80°C (special request). Please contact Hitachi agents.
*2 Under development

HITACHI

9

Quick Reference Guide
1YfIe

Column Drive (within RAM)

1YfIe Number

HD44102CH
4.5105.5

HD81102
4.5105.5

HD61202
4.5105.5

HD86106T
2.7105.5

HD66300T
4.5105.5

HD66310T
4.5105.5

HD66330T
4.5105.5

11

15.5

17

15

15

23

5

5

5

5

5

160

100

100

-2010+75"

-2010 +75

-2010 +75"

-2010 +75

-2010+75

-2010 +75'3 -20 10 +75
(-2010+60)

RAM (bil)
LCD driver Common
Column
Instruclion set
Operalion
frequency (MHz)

200x8

512x8

512x8

165x65

50
6
0.28

64
7
0.4

64
7
0.4

100-165
7
4

120

160

192

4.8

12115

28

Duty

Slalic-1132

Statio-l/64

1132-1/128

1132,1134,

TCP

TCP

SUM-TCP

Power supply for
inlernal circuits (V)
Power supply for
LCD driver circuits (V)
Power
dissipalion (mW)
Operaling
temperature (OC)
Memory

TFT Column Driver

ROM (bil)
()...65

1136,1/48,
1150,1/64,
1/66

Package

FP-80
Chip

TYpe

FP-l00

FP-l00
TFP-l00
Chip

TCP

Segment Display

TYpe Number

HD61602

HD61603

HD61604

HD61605

Power supply for
internal circuits (V)

2.7 to 5.5

2.7 to 5.5

2.7 to 5.5

2.7 to 5.5

Power supply for
LCD driver circuits (V)

5

5

5

5

Power
dissipation (mW)

0.5

0.5

0.5

0.5

Operating
temperature (OC)

-20 to +75"

-20 to +75"

-20 to +75"

-20 to +75"

204

64

204

64

Memory

ROM (bit)
RAM (bit)

LCD driver

Common

4

1

4

Column

51

64

51

Instruction set

4

4

4

4

Operation
frequency (MHz)

0.52

0.52

0.52

0.52

Duty

Static, 112. 1/3, 1/4

Static

Static, 112, 1/3, 1/4

Static

Package

FP-80
FPBOA

FP-80

FP-80

FP-80

*1 -40 to +80°C (special request). Please contact Hitachi agents.
*2 Under development
*3 -20 to +75°C in 12 MHz version, -20 to +65°C in 15 MHz version

10

HITACHI

64

Quick Reference Guide
Type

Common Driver

Type Number

HD44103CH

HD44105H

HD61103A

HD61203

HD6620S

HD66215T

HD66115T

Power supply for
internal circuits (V)
Power supply for
LCD driver circuits (V)

4.5 to 5.5

4.5105.5

4.5105.5

'4.5 to 5.5

2.7105.5

2.5 to 5.5

2.5 to 5.5

11

11

17

17

28

28

40

Power
dissipation (mW)
Operaling
temperature (OC)
Memory
ROM (btt)
RAM (bit)
LCD driver Common
Column
Instruction set
Operation
frequency (MHz)
Duty

4.4

4.4

5

5

5

5

5

-2010 +75"

-2010 +75'1

-20 to +75"

-20 to +75"

-20 to +75"

-2010 +75

-20 to +75

20

32

64

64

80

1001101

160 (80 +80)

2.5

2.5

0.1

0.1

2.5

118. 1112.
1/32.1148

Slali0-1Il O.
1/64

1/32-1/64

1164-11240

1164-11240

11100-11480

FP-60
Chip

FP-l00

FP-l00
TFP100
Chip

FP-l00
TFP100
Chip

SuM-TCP

SuM-TCP

Package

118. 1112.
1116. 1124.
1/32
FP-60

1\'pe

Character Display Controller

1\'pe Number

HD43160AH

HD44780U
(LCD-II)

HD66702R
(LCD-IIIE20)

HD66710
(LCD-IIIFa)

HD66712'2
(LCD-II/F12)

Power supply for
internal circuits (V)

4.5 to 5.5

2.7 to 5.5

2.7 to 5.5

2.7 to 5.5

2.7 to 5.5

11

7

13

13

Power supply for
LCD driver circuits (V)
Power
dissipation (mW)

10

2

2

2

2

Operating
temperature (OC)

-20 to +75

-20 to +75'1

-20 to +75"

-20 to +75"

-20 to +75

ROM (bit)

6420

9920

7200

9600

9600

RAM (bit)

80x8

80 x8.64x8

80x8.64x8

80x8.64x8.
8x8

80x8.64x8
8x8

Memory

LCD driver

Common

16

16

33

33

Column

40

100

40

60

Instruction set

6

11

11

11

11

Operation
frequency (MHz)

0.2510.375

0.25

0.25

0.25

0.25

Duty

1/8. 1/12. 1/16

1/8. 1/11. 1/16

1/8. 1/11. 1/16

1117. 1/33

1/17. 11338

Package

FP-54

FP-80B
TFP-80
Chip

FP-144A
Chip

FP·100A
TFP-100
Chip

TCP

*1 -40 to +80°C (special request). Please contact Hitachi agents.
*2 Under development

HITACHI

11

Quick Reference Guide
~

Graphic Display Controller

HD61830
LCDC

HD61830B
LCDC

HD63645F
HD64645F
HD64646FS
LCTC

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

Power
dissipation (mW)

30

50

50

Operating
temperature eC)

-20 to +75

-20 to +75*1

-20 to +75

7360

7360

Instruction set

12

12

15

Operation
frequency (MHz)

1.1

2.4

10

Duty

Static-1/128

Static-1/128

Static-1/512

Package

FP-60

FP-60

FP-80
FP-80B

~Number

Power supply for
internal circuits M
Power supply for
LCD driver circuits (V)

Memory

ROM (bit)
RAM (bit)

LCD driver

Common
Column

*1
*2

-40 to +80°C (special request). Please contact Hitachi agents.
Under development

Type

Low-Power LCD Chipset

Type Number

HD66503

HD68520

Power supply for
internal circuits M

2.7-5.5

2.7-5.5

LCD driver circuits M

28

28

Power
dissipation (mW)

0.5

0.5

Operating
temperature (OC)

-20° to +75°

-20° to +75°

Memory

ROM (bit)

LCD driver

Common

RAM (bit)

76800
240

Column
Operation
frequency (MHz)

160
65KHz

65KHz

Duty

1/120,1/240

1/120, 11240

Package

TCP

TCP

12

HITACHI

Type Number Order
Sorted by Type Name
Reference Page

Type

Function

HD43160AH

LCD controller

199

HD44100RFS

4O-channel LCD driver

151

HD44102CH

5O-channel column driver within RAM

489

HD44103CH

20-channel common driver

511

HD44105H

32-channel common driver

519

HD44780UAOOFS/OOTF/Ol FS/
02FSlUB**FSfTF LCD-II

LCD controller/driver (8 x 2 character)

HD61100A

80-channel column driver

174

HD61102RH

64-channel column driver within RAM

528

HD61103A

64-channel common driver

556

HD61200

8o-channel column driver

186

HD61202fTFIA

64-channel column driver within RAM

5SO

HD61203fTFIA

64-channel common driver

612

HD61602R1RH

Segment display type LCD driver

841

HD61603R

Segment display type LCD driver

841

HD61604R

Segment display type LCD driver

871

HD61605R

Segment display type LCD driver

871

HD61830AOOH LCDC

LCD controller

898

HD61830BOOH LCDC

LCD controller

898

HD63645F LCTC

LCD timing controller (68 family)

934

HD64645F LCTC

LCD timing controller (80 family)

934

HD64646FS LCTC

LCD timing controller (SO family)

934

HD66100F/FH

80-channel LCD driver

161

HD66106FS

80-channel column/common driver

772

214

HD66107TOO/Ol/ll/12124/25

160-channel column/common driver

787

HD66108TOO

165-channel graphic LCD controller/driver

638

HD66110RTA8IRTBO/RTBlfTA4

160-channel column driver

807

HD66115TAO/l

160-channel common driver

824

HD66204F/FLfTFfTFL

8o-channel column driver

691

HD66205F/FLfTFfTFLfTAlfTA2I
TA3ITA6fTA7/TA9L

8o-channel common driver

HD66214TA 1I213/619L

80-channel column driver

722

HD66215TAO/l/2

l00-channel common driver

751

706

HD66224TA l/TA2ITBO

8O-channel column driver

737

HD66300TOO

120-channel TFT analog column driver

1027

HD66310TOOfT0015

160-channel TFT digital column driver (8 gray scale)

1088

HD66330TAO

192-channel TFT digital column driver (64 gray scale)

1108

HD66503

240-channel row driver with internal LCD timing circuit

979

HD66520

160-channel 4-level grayscale display column
with internal bit-map RAM

996

HD66702RAOOF/00FUOl F/02F/
RB**F/FL LCD-II/E20

LCD controller/driver (20

273

HD66710***F8 LCD-II/F8

LCD controller/driver (8

334

HD66712 LCD-II/F12

LCD controller/driver (12

x 2 character)
x 4 character)

x

4 character)

HITACHI

411
13

Selection Guide
Hitachi LCD Driver System
Type
TFT

Full Color
System

Reference
Figure

Screen
Size (maxi
(800x3)x520
dots

Application
Personal Computer
Terminal Workstation
Navigation System

Color
LCD-TV
System

720 x 480 dots

HD66300T(Drain)
HD66205(Gate)
HD66215T(Gate)

LCD-TV
Portable Video

Display
System
lor CRT
Compatible

640 x 400 dots

HD63645/64645/
64646(Controller)
HD66204(Column)/
66205(Common)
HD66224T(Column)/
HD66215T(Common)
HD66106F(Driver)

Personal Computer, Wordprocessor, Terminal

Graphic
Display
System

Character
80x16
Graphic
480 x 128 dots

HD61100A(Column).
HD61830B(Controller)
HD61200(Column)
HD611 03A(Common),
HD61203(Common)

Laptop Computer,
Facsimile, Telex,
Copy machine

Graphic
Display
System
(Bitmap)

480 x 128 dots

HD44102(Column)/
61102(Column)
HD44103(Common)
HD61202(Column)
HD44105(Common)/
61103A(Common)
HD61203(Common)
HD66108
(Column)/Common)

Laptop Computer,
Handy Wordprocessor, Toy

Character
Display
System

40 Characters
x2 Columns
80 Charac-

HD44780U(LCD- II )
(Controller/Driver)
(Controller/Driver)
HD44100R(Column)
HD66100F(Column)
HD66702(LCD- II /E20)
HD66710(LCD-1I /F8)
HD66712(LCD-1I /F12)
HD61602
(Controller/Driver)
HD61604
(Controller/Driver)
HD61603
(Controller/Driver)
HD61605
(Controller/Driver)

Electrical Typewriter, Multilunction Telephone,
Handy Terminal

ters

x 1 Column
Segment
Display
System

14

Lineup
HD66310T(Drain)
HD66330T(Drain)
HD66205(Gate)
HD66215T(Gate)

25 Digits
xl Column

HITACHI

ECR, Measurement System,
Telephone
Industrial Measurement System

HD66108

Driver Output

I

160
HD66702
(LCD-II/E20)

,

HD66712
(LCD-II/F12)

Cc~~U;;D?Wfl

I

80

HD61603
HD61605

I

HD61102

tD61202

I

60

HD61604

I

HD66710
HD61602
(LCD-II/F8) HD44780U H
I
(LCD-II)

I

I

[COI~mn Driver
(Built in RAM)

HD44102

40

I

20

I

J:

~
o

1/480
.1/200
Duty 1/240

I
1/128
1/64
1/100

I

I

1/32

1/16

I

HD44103

HD441 05

:!:

I
1/8

I

StStic

I HD61103A

I

I

HD61200

1/128
1/100

1/200
1/480
Duty 1/240

HD44100R

I HD66100F

rn

IHD61100A

CD

80
HD66204/HD66214T/HD66224T I

HD66106F
HD66107T/HD66115T

I

[5O;;;'onDriV~~

160
Driver Output

1.11

I
1/64

60

I

HD662~1~5T~I::::::::::~~

I

I
1/32

32

HD66205/

I

I
1/16

20

~40

I HD61203

I
1/8

[COtum~- Driver

.. _!6106F

n

C.

o

HD66107T/HD66110RT

I

CD

I

::s

~
....

~

Selection Guide
Application
Character and Graphic Display
1 character=7 X 8 dot (15 X 7 dot + cursor)
Character
Line

16

8

I

24

20

I

32

40

I

I

OverBO

1
HD66100F
2
3
HD44100R
4
6 to 8

I

12 to 15

HD61200 (Column)

+

HD61203 (Common)

HD66204 (Column) + HD66205 (Common)
HD66214T/HD66224T (Column) + HD66215T (Common)
HD66106F, HD66107T
HD66110T (Column) + HD66115T (Common)

16 to 25
26 to 50

Graphic Display
Horizontal
Vertical
16
32

48

I

96

I

120

I

180

HD61202 (Column)

+

I

240

I

480

Over 640

HD61203 (Common)

48
64
128
400
Over 400

HD66204 (Column) + HD66205 (Common)
HD66214T/HD66224T (Column) + HD66215T (Common)
HD66106F, HD66107T
HD66110T (Column) + HD66115T (Common)

Note: Applications on this page are only examples, and this combination of devices is not the best.

16

HITACHI

Differences Betwaen Products
1. HD66100F and, HD44100R
LCD drive circuits
Power supply for internal logic (V)
Display duty
Package

HD88100F
80
3 to 6
Static to 1/16
100 pin plastic OFP

HD44100H
20><2
3 to 13
Static t01 /33
60 pin plastic OFP

HD61100A

HD61200

80
static to 1/128
to 17

80
1/32 to 1/128
8 to 17
shown in figures below

2. HD61100A and HD61200
LCD drive circuits

common
column

Display duty
Power supply for LCD drive circuits (V)
Power supply limits of LCD driver
circuit voltage

o

VCC to Vee
(no limit)

Resistance between terminal Y and terminal
V (one ofV1L, V1R, V2L, V2R, V3L, V3R, V4L,
and V4R) when load current flows through
one of the terminals Yt to Yeo is specified

under the following conditions:
Vcc-VEE=17V
V1L=V1R, V3L=V3R=Vcc-2/7 (Vee-VEE)
V2L=V2R, V4L=V4R=VEE+2/7 (VCC~VEE)
A,rt;A

0

V1L.V1R

0

V3L.V3R
V4L.V4R

0

V2L.V2R

....

VV

-

AAA
v'V

.... Tenninal Y

-(Y, toY..)

AAA

vv

....

W

Figure 1 Resistance between Yard V Term1nals
The following is a des9Iiption of the range of
poWer supply voltage for liquid crystal display drives. Apply positive voltage to V1L=
V1R and V3L=V3R and negative voltage to

-r----==_=_=_=_="_=_
"-v

---

V2L::;V2R and V4L=V4R within the Il.V range. This range allows stable impedance on
driver output (RoN). Notice the Il.V depends
on power supply voltage Vee-VEE.

~f'(V1L=V1R)

The Range of P _ Supply
Voltaga for Uquid Crystal
Display Drive

V3 (V3L-V3R)

5.5

~

,,-v

- - - - - - - V4 (V4L=V4R)
________ V2 (V2L=V2R)
Correlation between Driver
Output Wavefonn and Power
supply Voltages for Uquid
Crystal Display Drive

~

3

-----

v..
8
Vee-V•• M
Correlation between Power
Supply Voitaga Vee-V.. and l>V

Figure 2 Power Supply Voltage Range

HITACHI

17

Differences Between Products
3. HD66100F and HD61100A
HD66100F
LCD driver circuits

HD61100A

=-co=m.:.:.m:.:..:.::.on~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

column
Power supply for LCD drive circuits (V)
Display duty
Operating frequency (MHz)
Data fetch method
Package

80
3 to 6
static to 1/16
1.0 MHz (max)
Shift
100 pin Plastic
OFP (FP-1 00)

80
5.5 to 17.0
static to 1/128
2.5 MHz (max)
Latch
100 pin plastic OFP
(FP-100)

HD61830
Internal
1.1 MHz
static to 1/128
64x240 dots
(1/64 duty)
pin 6:C
pin 7:R
pin g:CPO

HD61830B
External
2.4 MHz
static to 1/128
128 x 480 dots
(1/64 duty)
pin 6:CE
pin 7:0E
pin 9:NC
@

4. HD61830 and HD61830B
Oscillator
Operating frequency (MHz)
Display duty
Programmable screen size (Max)
Other

Package Marking

Lot No.

~3El

HD61830AOO
JAPAN
Type No.
Lot No.

®
~3El

HD61830BOO
JAPAN
Type No.

®
Figure 3 Package Marking
18

HITACHI

Differences Between Products
5. HD61102 and HD61202
HD81102

HD81202

Display duty

static to 1/64

1/32 to 1/64

Recommended voltage between
Vee and VEE (V)

4.5 to 15.5

8 to 17

Power supply limits of LCD driver
circuits voltage

Vee to VEE (no limit)

Pin 88

DY (output)

shown in following figures
NC (no connection)

Absolute maximum rating of VEE (V)

Vee-17.0to
Vee+O.3

Vee-19.0 to
Vee+O.3

Resistance between terminal V and terminal V (one of V1 L. V1 R. V2l. V2R. V3l. V3R. V4l and V4R)
when load current flows through one of the terminals VI to V64 is specified under the following
conditions:

Vee-VEE=i5V
ViL=ViR, V3L=V3R=Vee-2/7 (Vee-VEE)
V2L=V2R, V4L=V4R=VEE+2/7 (Vee-VEE)

V1L.V1R

-----0

V3L.V3R

-----<0

Terminal V
(V, to V84)

0

V4L.V4R
V2L.V2R

RON

.-----Q..--o-----...J\

Figure 4 Resistance between Y and V Terminals
The following is a description of the range of
power supply voltage for liquid crystal display drives. Apply positive voltage to ViL =
ViR and V3L=V3R and negative voltage to

V2L=V2R and V4L=V4R within the AV range. This range allows stable impedance on
driver output (RoN). Notice that A V depends
on power supply voltage Vee-VEE.
The Range of Power Supply
Voltage for Uquid Crystal
Display Drive

-,----,....,.-="=
eN

Vee
V1 (V1 L=V1 R)
V3 (V3L=V3R)

5.0

3
6V
Correlation between Driver
Output Waveform and Power
supply Voltages for Uquid
Crystal Display Drive

V4 (V4L=V4R)
V2 (V2L=V2R)
VEE
Correlation between Power
Supply Voltage Vee-VEE and 6V

Figure 5 Power Supply Voltage Range

HITACHI

19

Differences Between Products
6. HD61103A and HD61203
HD61103A

HD61203

Recommended voltage between
Vee and Vee (V)

4.5t017

8 to 17

Power supply limits of LCD drive
circuits voltage
Output terminal

Vee to Vee (no limit)

shown in figures below

shown in following figure 4

shown in following figure 5

Resistance between terminal Y and terminal
V (one of V1L, V1R, V2L, V2R, V5L, V5R, V6L
and V6R) when load current flows through
one of the terminals Xl to X64. This value is
specified under the following conditions:

Vee-VEE=17V
V1L=V1R, V6L=V6R=Vee-l/7 (Vee-VEE)
V2L=V2R, V5L=V5R=VEE+1/7 (Vee-VEE)

RON

V1l,V1R

0

V6l,V6R

0

V5l,V5R

0

Terminal V
(V, to V64)

V2l,V2R

Figure 6 Resistance between Y and V Terminals
Here is a <;I.eseription of the range of power
supply voltage for liquid crystal display drive.
Appiy postive voltage to V1L = V1R and V6L =
V6R and negative voltage to V2L = V2R and

V5L = V5R within the t:..V range.
This range allows stable impedance on driver

output (RON). Notice that t:..V depends on
power supply voltage Vee-VEE.
The Range of Power Supply
Voltage for Uquid Crystal
Display Drive

Vee

L>V

3.5---~------------

V1 (V1 l, =V1 R)
V6 (V6l=V6R)

~

>

2------

F(T)
om..

a
=Bt;2
P
2

F (T): Resin strength
p: Form coefficient

Figure 4 Package Crack Generation Mechanism

10

~

j
I!
1S
~

'8t<'

10

,

8
I

Ie

.~

1

8

I
I

6

I

6

/(OMLX)SAT

11 ~

~~
i-=

I

I
I

4

4

2

MOisture
absorption ratio
(85°C 85%RH)
0.3 wt 2

i

!~

ii
e=

1!!?

s:: ___

0.2wt

:i

0

100

150

200

0

Temperature (OC)

FigureS Temperature Dependence of Resin Adhesive Strength,
Mechanical Strength, and Generated Stress
34

HITACHI

Notes on Mounting
3. Recommended Soldering Conditions
sents Hitachi's recommended soldering conditions.

Soldering temperature stipu1ations must be followed and the moisture absorption states of plastic
packages must be carefully monitored to prevent
degradation of the reliability of surface mount
packages due to thermal shock. This section pre-

3.1 Recommended Soldering Temperatures
See table I.

18ble 1 Recommended Ie Soldering Temperatures
Method

Notes

Recommended Conditions

Vapor-phase reflow

30s,

~l!!
i1

:::J

GIl!

a'_t

~

~

' \ About 60 s

1 to 5°C/s
Time

Infrared reflow
Hot-air reflow

235OC,
maximum

10 s,

1 to 50Cts

Since TSOP, TQFP, and
packages whose body
thickness is less than
1.5 mm are especlally
vulnerable to thermal shock,
we recommend limiting the
soldering conditions to
a maximum temperature of
230°C for a maximum time
of 10 seconds for these
packages.

Time

HITACHI

35

Notes on Mounting
4. Moisture Absorption Prevention
Conditions
Plastic packages absorb moisture when stored in a
high humidity. If devices are mounted using solder
reflow techniques when they have absorbed moisture they are susceptible to reflow cracking.
Products that are particularly susceptible to the
influence of absorbed moisture are packed in
moisture-proof packing. These products should be
handled under the following conditions after
opening the moisture-proof packing.

4.2.1 Baking is Required in the Following
Situations
1. If the desiccant indicator has turned pink.
2. If the storage period following unpacking
exceeds the specifications for that period.
4.2.2 Recommended Baking Conditions

4.1 Storage and Handling after Opening
Moisture-Proof Packing

1. TSOP and TQFP: 12Soe for 4 hours

Storage temperature: SoC to 30°C
Storage humidity:

4.2 Baking

Under 60% relative humidity

Time between unpacking and reflow soldering:
1. If specified on the label attached to the
moisture-proof packing, or in the delivery
specifications: follow those specifications.

2. Packages other than TSOP and TQFP: 125°C
for 16 hours to 24 hours
3. If specified in the delivery specifications or
other documentation, follow those specifications.
4.2.3 Other Points
Use heat-proof trays in the baking operation.

2. If not specified on the label attached to the
moisture-proof packing or in the delivery specifications: perform reflow soldering within
168 hours (one week) with the product stored
under the conditions specified above.

36

HITACHI

Notes on Mounting
Surface Mounting Package Handling Precautions
1. Package temperature distribution
The most common method used for mounting
a surface mounting device is infrared reflow.
Since the package is made of a black epoxy
resin, the portion of the package directly
exposed to the infrared heat source will
absorb heat faster and thus rise in temperature more quickly than other parts of the
package unless precautions are taken. As
shown in the example in figure 6, the surface
directly facing the infrared heat source is 20'
to 30'C higher than the leads being soldered
and 40' to 50'C higher than the bottom of the
package. If soldering is performed under
these conditions, package cracks may occur.
To avoid this type of problem, it is recommended that an aluminum infrared heat
shield be placed over the resin surface of the
package. By using a 2-mm thick aluminum
heat shield, the top and bottom surfaces of
the resin can be held to 175'C when the peak
temperature of the leads is 240'C.

(Resin)

300
250

'TS

T,

(Solder)

200

::J

.,

~

Co

One method of soldering electrical parts is
the solder dip method, but compared to the
reflow method, the rate of heat transmission
is an order of magnitude higher. When this
method is used with plastic items, there is
thermal shock resulting in package cracks
and a deterioration of moisture-resistant
characteristics. Thus, it is recommended that
the solder dip method not be used.
Even with the reflow method, an excessive
rate of heating or cooliIig is undesirable. A
rate in temperature change of less than 4'C/
sec is recommended.

It is recommended that a resin-based flux be
used during soldering. Acid-based fluxes
have a tendency of leaving an acid residue
which adversely affects product reliability.
Thus, acid-based fluxes should not be used.
With resin-based fluxes as well, if a residue is
left behind, the leads and other package
parts will begin to corrode. Thus, the flux
must be thoroughly washed away. If cleansing solvents used to wash away the flux are
left on the package for an extended period of
time, package markings may fade, so care
must be taken.

U

E
$

3. Heating and cooling

4. Package contaminants

~

e

The epoxy resin used in plastic packages will
absorb moisture if stored in a high-humidity
environment. If this moisture absorption
becomes excessive, there will be sudden
vaporization during soldering, causing the
interface of the resin and lead frame to
spread apart. In extreme cases, package
cracks will occur. Therefore, especially for
thin packages, it is important that moistureproof storage be used.
To remove any moisture absorbed during
transportation, storage, or handling, it is
recommended that the package be baked at
125'C for 16 to 24 hours before soldering.

Infrared rays

~~SU~
T2

2. Package moisture absorption

150

100
time (sec)

Figure 6 Temperature Profile During
Infrared Heat Soldering
(Example)

The precautions mentioned above are general points to be observed for reflow. However, specific reflow conditions will depend
on such factors as the package shape, printed
circuit board type, reflow method, and device
type.
For details on surface mounting small thin
packages, please consult the separate manual available on mounting. If there are any
additional questions, please contact Hitachi,
Ltd.

HITACHI

37

The Information of Tep
Features of TCP (TAB Technology)

Flexible Design

The structure and materials used by Tape Carrier
Package (TCP) give it the following features as
compared with conventional packages:

The following can be tailored to the design of the
system (e.g. motherboard design):

Thin, Lightweight, and Fine Pitch

• Pattern layout
• TCPdesign

With thickness less than 1 mm and fme-pitch leads,
a reduced pad pitch on the device enables more
functionality in a package of equivalent size.
Specifically, these features enable:
• Thin and high defmition LCM (Liquid Crystal
display Module)
• Lightweight and ultra-high pin count systems

TCP Applications
Thinness, ultra-high pin count, and fme pitch open
up new possibilities of TCP applications for compact and highly functional systems. Figure 1 shows
some applications of TCP-packaged chips.

Personal computers;
word processors

LCO*driver

LCOmodules

Calculators and
organizers

Memory

Workstations

Computers

Figure 1 Examples of TCP.Packaged Chip Applications

38

HITACHI

TCP
Hitachi TCP Products
high voltages and provide high defmition with a
tape carrier package that promises excellent reliability, making possible applications that would not
be feasible with a conventional QFP. For material
specifications of the products in table 1, see
table 3.

TCP for Hitachi LCD Driver
Hitachi offers tape-carrier-packaged LCD drivers
for LCD modules ranging from miniature to large
sizes. Table 1 shows some examples of standard
tape carrier packages for LCD drivers. Hitachi
LCD drivers combine a device that can withstand

Table 1 TCPs for Hitachi LCD Drivers
Appearance

Function
Signal
Output

Application

Drive

TFT

Column
only

Analog

Mediumsize
liquid
crystal

Column
and
common

Digital

Product
Code

Total Pin
Count
(Output)

Outer
Lead
Pitch

HD66300TOO

156(120)

0.3mm
Built-in controller
(on-chip RAM)

HD6610STOO
Large
liquid
crystal

Column
and
common

20S (165)

0.4mm

Digital

Outer lead pitch:
O.OS-mm products
are also available
HD66110TAS

Large
liquid
crystal

Common
only

Digital

Large
liquid
crystal

Column
only

Digital

.•

HD66205TA9L

0.14mm

92 (SO)

HD66214TA9L
Column
only

Digital

If~m~

.•

9S (80)

Outer lead pitch:
0.1 S-mm, 0.20-mm,
products are also
available.

0.22 mm
Outer lead pitch:
0.20-mm products
are also available.

"\~,.

III

if.

III
"

HD66224TA1

Outer lead pitch:
0.1S-mm,O.1S-mm,
0.20-mm or 0.25-mm
products are also
available.

0.22 mm

"'

\'

W~}~~~I

Large
liquid
crystal

Remarks

10S (SO)

HITACHI

\~l

0.21 mm

39

TCP
TCP External View and Cross-Sectional Structure

YCP Components

Solder resist

Outer lead hole

User area

Outer lead for input

Cross-Sectional Structure

40

HITACHI

TCP
TCP Materials and Features

ordering manual [ADE-801-OO1 (0)].

TCP Material Specifications: Table 2 lists
Hitachi TCP material specifications. Ask us if you
require other materials. In this case, use TCP

Table 3 lists current material specifications for
various Hitachi products.

Table 2 Hitachi TCP Material Specifications

No.

Item

Specifications

Base film

UPILEX~ S-type: thickness 75 11m ±5 11m
KAPTON~ V-type: thickness 125 or 75 11m ±5 11m

2

Adhesive

Toray#5900

3

Copper foil

4

Resin

Epoxy resin

5

Outer lead plating

Tin

6

Solder resist

Epoxy solder resist

TOMOEGAWA E-type
Rolled copper: thickness 35 or 25 11m ±5 11m
Electro-deposited copper: thickness 35 or 25 11m ±5 11m

Cross-sectional view

4

Table 3 Material Specifications for Hitachi Products
Copper FOil

Outer Lead
Plating

Toray #5900

Rolled copper

Tin

Toray#5900

Rolled copper

Tin

UPILEX~S

TOMOEGAWA
E-type

Electro-deposited
copper

Tin

Large liquid
crystal·

UPILEX~S

Toray#5900

Rolled copper

Tin

HD66214TA9L

Large liquid
crystal

UPILEX~S

Toray#5900

Rolled copper

Tin

HD66224TA1

Large liquid
crystal

UPILEX~S

TOMOEGAWA
E-type

Electro-deposited
copper

Tin

Product Code

Application

Base Film

Adhesive

HD66300TOO

TFT

KAPTON~V

HD66108TOO

Large liquid
crystal

KAPTO~V

HD66110TA8

Large liquid
crystal

HD66205TA9L

HITACHI
--.~-.~--.

-

---,--~-

_..-

-----~---

- -- ..

~---.--=--=---------

41

TCP
Properties of Materials: Properties of Hitachi
TCP materials are as follows.

1. Base film
The properties of base mm are shown in table 4.
Hitachi currently adopts UPILEX@ S, which
exhibits high rigidity and super dimensional
stability with respect to temperature changes
compared with conventional KAPTON® V.

2. Copper foil (copper wiring)
The properties of rolled foil and electro-deposited foil are shown in table 5. Hitachi plans to
adopt electro-deposited foil due to its excellent
elongation properties at room temperature (RT)
compared with conventional rolled foil.

Table 4 Properties of Base Film (See references 1 and 2, page 28)

Coefficient of
linear expansion

x 1o-srC

KAPTON@V

UPILEX@S
(Ube Industries, Ltd.)

Property

(D-.! Pont-Toray Co., Ltd.)

To 100·C

0.8

T0200·C

1.0

2.6

900

355

Tensile modules (kgf/mm2)

Table 5 Properties of Copper Foil (See reference 3, page 28)
Sampling
Condition

Rolled Foil
(Hitachi Cable, Ltd.)
CF-W5-1 S-LP

Electro-Deposited Foil
(Mitsui Mining & Smelting Co., Ltd.)
3EC-VLP

Tensile strength at RT
(kgflmm2)

Raw foil

43.0

54.9

Elongation at RT

Raw foil

1.0

10.1

Tensile strength at 180·C
(kgf/mm 2)

Raw foil

23.4

25.4

Elongation at 180·C

Raw foil

7.7

7.0

Property

(%)

(%)

Note: Data from film suppliers.
Number of measured samples: 2 pieces each
1 kgf/mm 2 • 9.80665 MPa .

42

HITACHI

TCP
peeling strength.

3. Adhesive
The relationship between peeling strength
(adhesive/electro-deposited foil) and lead width
is shown in figure 2. Hitachi adopts the following two combinations because of their higher

-Adhesive TOMOEGAWA E-type/electrodeposited foil
- Adhesive Toray #5900/rolled foil

12

E
::I.
8

10

0

-

8

~e

6

; :,

Adhesive

Copper foil

Electro-deposlted
A TOMOEGAWA
E-type
foil
Toray#5900

o TOMOEGAWA
E-type

Rolled foil
Rolled foil

.9

1ii

8'

i*

4

2
0

40/40
(80J.1m)

60/60

80/80

100/100

(120 J.1m)

(160 J.1m)

(200 J.1m)

Line widthlspace (11m)
(pattern pitch)

"Peeling strength

- How to measure -

Copper foil

Measuring method: 90· peel
Measuring condition: 25°C
Number of measured samples:
Five p'ieces are measured for each
specification, and two leads are
measured for each piece.

1t'-.f--Adhesive

Figure 2 Relationship between Peeling Strength and Lead Width

HITACHI

43

TCP
Fine-Pitch Bump Formation

Bumps are essential in TCP products; they are the
foundation of TAB technology and have excellent
corrosion resistance in their slrUcture. When the
current trend toward high-performance chips with
ultta-large pin-out began .driving pad counts

upward (and reducing pad pitch), Hitachi was
quick to develop a volume production process for
forming fme-pitch bumps.
Figure 3. shows the Hitachi TCP bump SIl'Ucture.
Figure 4 shows a flowchart of the bump formation
process.

Straight-Wail Bumps (Fine-PItch)

Notes: 1. UBM: Under Bu"" Metal
2. Case of SO-I'm bump pilCh

Unit:mm

Figure 3 Hitachi TCP Bump Structure

AI photolithography
Passivation

Bump formation process

Remove resist
UBMetchlng

Figure 4 Bump Formation Flowchart

HITACHI

TCP
TCP Fabrication Flow
TCP Tape: TCP tapes are purchased from tape
manufacturers. In many cases, the quality of TCP
products depends critically on the quality of the
tape, so in addition to evaluating constituent materials, Hitachi strictly controls the stability of the
tape fabrication process.

TCP Fabrication Process: The TCP fabrication
process starts from wafers (or chips) with bumps,
and a patterned tape. After being bonded by a highprecision inner lead bonder, the chips are sealed in
resin. Figure 5 shows the standard fabrication pr0cess for TCPs used in Hitachi LCDs.

Bump (gold)

TCPtape

fonned

Inner Lead Bonding

This step bonds the bumps on the chips to the inner leads
by
patteming. Gang bonding has been adopted as a standard procedure at
Hitachi.
Sealing
Chips are sealed in resin to ensure inner lead bonding strength.
The standard bonding process employs a potting liquid resin which
seals the chip.
Inner lead

Iliii~~==Copperfoil

Base tape

Figure 5 Standard Fabrication Process for TCPs Used in Hitachi LeDs

HITACHI

45

TCP
Packing

the solderability of lead plating.

Packing Format: TCP products are packed in
moisture-proof packages. A reel wound with TCP
tape is sealed in an opaque antistatic sheet with N2
to protect the product from mechanical shock and
then packed into a carton before delivery to ensure

Labels which indicate the product name, quantity,
and so on are placed on the reel, antistatic sheet,
and carton. Figure 6 shows the TCP packing
format

Reel

Label

Separator
Lead ----"....
tape

Shock absorber

Figure 6 Packing Format

46

HITACHI

TCP
Tape Specification:
1. TCP tape - 40 m
2. Lead tape - 2 +1/4>.5 m added to both ends of
theTCP
3. Conductive tape - 40 m
4. Separator - 40 m
5. Width of tape - 35 mm

Note: The lengths of the TCP tape. conductive
tape. and separator may vary slightly
depending on the quantity of the product on
the tape.
Reel Specification: Figure 7 shows reel dimensions.
For recycling purpose. we would appreciate it if
you return the reel and separator to us after use.

Units: mm
Material: Styrene
Dimensions without tolerance

43

B

are design values.

-r-----il

Figure 7 Reel Dimensions

HITACHI

47

TCP
TCP Winding Direction: Figure 8 shows one way
of winding TCPs. The combination of two product
directions when pulling it. out from the reel and
placement of the patterned face on either the front
or back of the tape makes for four types of TCP
winding directions.

Note

The winding direction is an essential specification
which affects the chip punching machine and
assembly equipment during the packaging process.
As the wind direction differs according to the product, please check the delivery specifICation before
usingTCP.

Product direction (two types)

x
Pattemed face on either front or back (two types)

II
Four types of TCP winding direction

Figure 8 Example of TCPWinding Direction

48

HITACHI

TCP
TCP Mounting Methods
TCP Mounting Structure

Basic Mounting Process

'JYpical example of an LCM structure using TCPs
is illustrated in figure 9.

See figure 10.

Note: • PCB: Printed Circuit Board

Figure 9 LCM Structure

Repair

Note:

* ACF: Anisotropic Conductive Film
Figure 10 TCP OLB (Outer Lead Bonding) Basic Flowchart

HITACHI

49

TCP
Process Outline
An outline of LCM assembly process using TCPs
is given in fIgUre 11.

ACFapplied
Applies ACF on LCD glass panel
by thermal pressing.

TCP prepress

Aligns the LCD panel and TCP
patterns and temporarily
connects them by low
temperature and low pressure.

Thermocompresses multiple
TCPs to the LCD panel, which
have been temporarily
connected, by high temperature
and high pressure either
Individually or all together.

Soldering
Joins output leads of TCPs and
PCB patterns by soldering.

Figure 11 Outline of LCM Assembly Process
50

HITACHI

TCP
low connection resistance and high thermosta-

TCP Mounting Conditions

bility.

Mounting TCPs on LCD Panels (See reference 4,
page 28): ACF is an adhesive film that can connect
electrodes on an LCD glass panel with output leads
ofTCPs. There are two types of ACFs:
• One whose thermosetting and thermoplastic
properties make handling easier (such as in
repair) and reduces the sttesses caused by temperature changes.
• One whose thermosetting properties provide

Please select ACF depending on the type of application.
1. Selection of ACF thickness

An appropriate ACF thickness must be selected
depending on the height, line width and space
width of the circuit to be connected; a rough
calculation formula for obtaining a proper ACF
thickness is shown below.

~~~Glass substrate

S1 +S2

2

ACF thickness before connection to .. - - - x T + t1 + a
P
tl:
T:
P:
S1:
S2:
a:

ACF thickness after connection (2 Ilm)
Circuit height
Pitch
Space width (top)
Space width (bottom)
Correction value
AC-6073, AC-61 03 - 0.1ST
AC-71 04, AC-7144 - 0.2ST

Incomplete filling can occur in the space if ACF thickness is too thin, while if too thick, connection
reliability becomes poor since conductive particles are not flattened out. It is necessary to select an
appropriate ACF thickness. Some adjustment of ACF thickness can be controlled by bonding
conditions (especially pressure).

HITACHI

51

TCP
ANISOL~ (Hitachi Chemical Co•• Ltd.) are
shown in table 6 for reference. Please determine
your optimum bonding conditions based on the
following.

2. Laminating and bonding conditions
It is necessary to optimize bonding conditions
according to ACF. TCP and glass panel specifications. The bonding conditions adopted by

Table" Bonding Conditions of ANISOLM®

Item

Unit

Mixture of
thermosetting and
thermoplastic

thermosetting

Remarks

AC-6073 ACo61 03 ACo71 04 ACo7144

Standard
specillcatIons

Min. pitch ~ Resolution
Space

~10 ~10 ~14
~~nel
I'ITI mm ~7

Thickness

I'ITI

Widlh

mm

Length

m

Color
Core diameter
Bonding laminating Temperature
conditions

Bonding

22,18

22

16
3,2.5,2

50

50

Transparent (gray)

Transparent (gray)

mm

18.5

18.5

'C

80 to 100

701090

1

1

Temperature on
ANISO~

Pressure

MPa

Time

s

5

5

Temperature

'C

17010 190

16010180

Pressure

MPa*

2

Time

s

20

Note: *1 MPa .1.01972 x 10-1 kgflmm2

52

25

3,2.5,2

HITACHI

Temperature on
ANISO~

2

3
20

TCP
Measuring Method or ACF Temperature Profile (example)

~-:;;;;;;;;;;;

Silicone rubber (0.2 to 0.3mm)
Teflon film (25 to SOJun)
Base film

CO

Copper foil

4--+------Glass plate

E - - - - -.::..;;;..;:. . . .-----..,..-- - Final temperature
~

!

I
s

8

~

~
....

I

:
I
I

:

O'--;O----------------~20~s----~:7.~==~-~
TIme(s)
,.
Temperature after 5 sec should be over 90% of final
temperature (Oe)

Figure 12 Bonding Temperature Profile

HITACHI

53

TCP
Soldering Conditions: Solder TCPs on the PCB
under the following conditions. If soldering temperature is low, solder may not melt. However, if
soldering temperature is too high, solder may not
adequately spread over the leads owing to their
oxidized surfaces, and/or the leads plating may
become attached to the heating collet. In the latter

i

case, copper foil of leads may become exposed.
Please determine adequate soldering conditions for
mass production carefully.
• Soldering temperature (at solder joint): 230 to
260°C
• Soldering time: 10 seconds max.

230 to 260°C

~

1:
:§.

j
51
'tiS
!

10 seconds (max.)

:::J

1!
8.
E

{!.

Time (second)

>

Note 1: Temperature at solder joint is normally 30 to 50°C lower than the heating collet temperature. Soldering temperature has a great impact on the quality of the products. Operating
conditions should therefore be specified after examining the temperature relationship
between the tip of the heating collet and solder joint.

Heating collet

-::::==::3IE------ Outer lead
= = - - Footprint
f.f+--PCB

54

HITACHI

TCP
Note 2: In case of soldering quad type TCPs, please fix the TCPs using vacuum collets or equivalent to prevent base film warpage and circuit position misalignment

Heating collet

Base film

Vacuum collet
Heating collet

HITACHI

55

TCP
Storage Restrictions
1. Packed tcp products should be used within six

months.
2. TCP products removed from the antistatic sheet
should be stored in N2 having a dew point of
-30°C or lower. However, they should be used
as soon as possible after removal, because solderability of leads plated with Sn or solder
decreases with time.
Handling Precautions
Electrical Handling
1. Anti-electrostatic discharge measures

TCP products require the following care beyond
what is required for non-TCP products.
• Give special attention to ion-blow and
grounding especially when removing TCP
products from the reel, since they easily collect static electricity because of the base film.
If TCP products become charged, discharge
the electricity little by little using the ionblow; rapid discharge may damage the
devices.
• Handle the product so that static electricity is
not applied to outer leads. Depending on the
equipment used, this may require taking
proper anti-electrostatic discharge measures,
such as not allowing the tapeguide to contact
the outer leads.
2. Outer lead coating
Outer leads should be coated with resin or other

56

appropriate materials to prevent short-circuits
and disconnections due to corrosion. Conductive foreign particles can easily cause shortcircuits since lead spacing for TCP products is
much narrower than that for non-TCP products.
Disconnections from corrosion can also easily
occur due to solder flux or similar materials
adhering to leads while mounting the products
on a board. This is because TCP product leads
are formed by bonding very thin copper foil to
the base film in order to attain high-density
mounting.
3. To prevent electric breakdown when mounting
TCP products on a board, do not allow any electrical contact with the die's bottom surface.
These types of failures easily occur since TCP
products have a bare Si monocrystal on the die's
bottom surface in order to make the product as
thin as possible.
To prevent degradation of electrical characteristics, do not expose TCP products to sunlight.
Mechanical Handling
1. To prevent die cracks when mounting TCP
products on a board, do not allow any physical
contact with the die's bottom surface. These
types of failures easily occur since TCP products have a bare Si monocrystal on the die's bottom surface in order to make the product as thin
as possible.
2. Handle TCP products carefully to avoid bending
the leads from base film transformation.
3. Do not bend TCP products since this may cause
cracks in the solder resist.

HITACHI

TCP
4. Punching
Punching the continuous base film to extract
single TCP products requires the following care.
• Align each product correctly according to
tape perfomtions (sprocket holes).
• Use a metal punching die with pressing
installation to prevent resin cracks and
reduce cutting stresses in the outer leads.
(Refer to figure 13.)

• Determine the punching position so that the
cutting edge does not touch the molding area
based on the relationship between maximum
molding area (specified in the design drawing) and the punching die accumcy.
Punch TCP products in the section where outer
leads are straight (not slanted) to prevent shortcircuits caused by conductive particles. (Refer
to figure 14.)

Punching die without
pressing installation

Punching die with
pressing installation

Figure 13 Punching Die

No punching area
Margin area

"

Punching area

Figure 14 Punching Position

HITACHI

57

TCP
• Thermal stresses

5. Mounting structure
Copper foil can easily break even from a small
physical stress because of its thinness needed to
accommodate fine patterns. Large stresses
should therefore not be applied to the copper
foil when mounting TCP products on a board.

LCM consists of glass, TCPs and a glassepoxy substrate having their respective coefficients of thermal expansion (erE). This
difference in expansion effects may cause
"thermal stresses" that especially concentmte
in TCPs. The joining structure of LCMs is
roughly shown in figure 16. Before beginning mass production, investigate and determine a joining structure that reduces thermal
stresses so as to prevent contact and other
defects from occurring.

• Bending stresses
When the edges of a die and a PCB are
aligned, resin cmcks may occur due to bending stresses. To avoid this problem, locate the
board closer to the LCD panel so that it can
support the molded part of the package.
(Refer to figure 15)

6. Do not stack more than ten cartons of products.
7. Do not subject cartons to high physical impacL

_ LSI die

LCD

Move the PCB closer to the LCD panel
Bending Stresses Applied

No Bending Stresses Applied

Figure 15 Positioning of Mounting TCPs on a PCB

TCP
LCM is composed of
various materials having
their respective CTEs.

~~~··~~---PCB

Figure 16 Joining Structure of LCM

58

HITACHI

TCP
Correction 01 ITO (Indium TIn Oxide) Electrode
Pitch: TCP products expand by absorbing
moisture or heat during storage and assembly.
Pitch correction for the no electrode should be
performed based on the TCP dimensions after it is
mounted on a conductive film. However, if ITO
pitch correction is performed based on TCP dimensions before mounting, it must be based on data
measured after removing TCP products from the
package and storing at a temperature of 20 to 25"(;
and a humidity of 50 to 70% RH for 48 hours.
Correct the ITO electrode pitch depending on the
bonding equipment and conditions used.

Miscellaneous
1. Do not heat the lead tape and separator; they
have poor heat-resistivity and will expand.
2. Do not subject TCPs to high temperature for a
long period of time while cleaning or other
operations; copper foil may peel off due to the
rapid deterioration of adhesion between the copper foil and base film.
3. Carrier tapes have some waviness that may
cause problems in tape transport. Use a
tapeguide or equivalent to secure the tape.

18.751----------------~-----.

OUlput dimension after TCP Is joined to ACF

18.74

18.73

I

I

18.72

t
r

+0.15
+0.10

+0.05

l

18.71

J

18.70
18.69

Measured saqJIe: HD66214TA7 (Base film: 75 jIJTI UPILEXI S)
Number of measured &aqIIes: 5 places
Storage conditions: 25 ±SOC. 50 to 6O'YoRH

18.68 1o.-...J.-'O;--'--:-_--L_J........J~J...L~---1-.LLl..LULI.L-J
Before sealing
In a carton

1
Immediately
after unsealing

50
Storage time (hours)

Figure 17 Dimensional Cbange of Output

HITACHI

S9

TCP
TCP Standardization
The ''Tape Canier Package WIG" in the
Semiconductor External Standards Committee of
the EIAJ· (Electronics Industries Association of
Japan) has standardized TCPs having leads on four
sides (EIAJ ED-7431{'93.4». The standardization
WIG, which is composed of various semiconductor
manufllClurers including Hitachi, tape manufacturers, and socket manufacturers, is taking a comprehensive approach.
EIAl has adopted metric control standard against
JEDBC*'s inch control standards (UO-Ol7) and has
determined standards based on the following two
items:
• Fixed test pad layout, variable package size

• Fixed package size, variable terminal pitch
Accordingly, users can share the socket by deciding the width of tape and the test pad pitch. As
JEDEC has already agreed to the metric-control
TCP (UO-018), Hitachi is now making efforts to
produce metric-control TCPs.
The basic concept of TCP having leads on four
sides by EIAJ is shown below. Standardization of
TCP having leads on two sides is also under discussion.
Note: ... JEDEC:
Joint Electronic Device Engineering
Council.

Quad Tape Carrier Package (QTP) ................... EIAJ ED-7431

1. Tape width: 35, 48, 70 mm
2. Package size: 35 mm 14 x 14,16 x 16,18 x 18, 20 x 20
48 mm 16 x 16, 20 x 20, 24 x 24, 26 x 26, 28 x 28
70 mm 24 x 24, 28 x 28, 32 x 32, 36 x 36, 40 x 40
3. Test pad pitch: 0.5, 0.4, 0.3, 0.25 mm
4. Outer lead pitch: 0.5, 0.4, 0.3, 0.25, 0.2, 0.15 mm
5. Sprocket-hole type: 35 mm
Super
48 mm wide, Super
70 mm wide, Super
6. Number of test pads: FIXed maximum number of test pads, regardless of the outer lead

count.
For 35-mm tape: 196 for 0.5 pitch; 244 for 0.4 pitCh.

60

HITACHI

TCP
Reference Materials
TCP Mounting Equipment Manufacturer
Manufacturer: Hitachi Chemical Co., Ltd.
Area

Address

Tel No.

Fax No.

USA

Hitachi Chemical Co., America, Ltd.
4 International Drive, Rye Brook,
NY 10573, U.S.A.

(914) 934-2424

(914) 934-8991

Europe

Hitachi Chemical Europe Gm bH.
Immermmstr. 43, 0-4000
DOsseldorf 1, F. R. Germany

(211) 35-0366 to 9

(211) 16-1634

S.E. Asia

Hitachi Chemical Asia-Pacific Pte, Ltd.
51 Bras Basah Road, #08-04
Plaza By The Park. Singapore 0718

337-2408

337-7132

Taiwan

Hitachi Chemical Taipei Office
Room No. 1406, Chia Hsim Bldg.,
No. 96, Sec. 2, Chung Shang Road N,
Taipei. Taiwan

(2) 581-3632,
(2) 561-3810

(2) 521-7509

Beijing

Hitachi Chemical Beijing Office
Room No. 1207, Beijing Fortune Building,
5 Dong, San Huan Bei-Lu, Chao Yang
District, Beijing, China

(1) 501-4331 to 2

(1) 501-4333

Hong Kong

Hitachi Chemical Co. (Hong Kong) Ltd.
Room 912, Houston Centre, 63 Mady Road,
Tsimshatsui East, Kowloon, Hong Kong

(3) 66-9304 to 7

(3) 723-3549

HITACHI

61

TCP
Manufacturer: Matsushita Electric Industrial Co., Ltd.
Area

Address

Tel No.

USA
(Illinois)

panasonlc Factory Automation
Company

(708) 452-2500

Deutschland

Panasonic Factory Automation
Deutch land

(040) 8549-2628

Asia
(Japan)

Matsushita
Manufacturing Equipment D.

(0552) 75-6222

Fax No.

Manufacturer: Shinkawa Co., Ltd.
Area

Address

Tel No.

Fax No.

U.S.A.

MARUBENIINTERNATIONAL
ELECTRONICS CORP. U.S.A.
3285 Scott Blvd, Santa Clara,
CA. 95054

408-727-8447

408-727-8370

Singapore,
Malaysia,
Thailand

MARUBENIINTERNATIONAL
ELECTRONICS CORP. SINGAPORE
18 Tannery Lane #06-01102,
Uan Teng Building, SGB 1334

741-2300

741-4870

Korea,
Hong Kong,
China,
Taiwan,
Philippine,
Brazil

MARUBENI HYTECH CORP.
Japan
20·22, Koishikawa 4-chome,
Bunkyo·ku, Tokyo 112, Japan

(03)-3817-4952

(03)-3817-4959

Europe

MARUBENIINTERNATIONAL
ELECTRONICS EUROPE GMBH
Niederrhein STR, 42 4000
Dusseldorf 30 Federal Republic of Germany

0211-4376-00

0211-4332-85

62

HITACHI

TCP
Manufacturer: Kyushu Matsushita Electric Co., Ltd.
Area

Address

Tel No.

Fax No.

CHICAGO

1240 Landmeier Rd.
Elk Grove Village, IL 60007

(708) 822-7262

(708) 952-8079

ATLANTA

1080 Holcomb Bridge Rd.
Building 100, Suite 300
Roswell, Georgia 30076

(404) 906-1515

(404) 998-9830

San Jose

177 Bovet Road, Suite 600
San Mateo, CA 99402

(415) 608-0317

(415) 341-1395

LONDON

2381246 King Street, London W6 ORF
United Kingdom

(081) 748-2447

(081) 846-9580

SINGAPORE

1 Scotts Road, #21-10/13 Shaw Centre
Singapore 0922

7387681

7325238

SEOUL

2ND Floor, Oonghwa Bldg.
454-5, Dokok-1 Dong, Kangnam-Ku.
Seoul. Korea

(02) 571-2911

(02) 571-2910

TAIWAN

6TH, FL.. 360. FU HSING 1ST ROAD.
KWEISHAN. TAO YUAN HSIEN.
TAIWAN

(03) 328-7070

(03) 328-7080
(03) 328-7090

MALAYSIA

KUALALUMPUR BRANCH
8TH FLOOR. WISMA LEE RUBBER.
JAPAN MELAKA. 50100
KUALALUMPUR

(03) 291-0066

(03) 291-8002

BANGKOK

20TH FL.. Thaniya Plaza Bldg, 52
SUom Road, Bangrak. BANGKOK.
10500 THAILAND

(02) 231-2345

(02) 231-2342

Manufacturer: Japan Abionis Co., Ltd.
Area

Address

Tel No.

Fax No.

Worldwide

Overseas Department
Contact: Mr. K. Asami. or Mr. K. Ito

81-3-3501-7358

81-3-3504-2829

HITACHI

63

TCP
TCP Tape Manufacturers
Manufacturer: Hitachi Cable Ltd.
Area
. U.S.A.

Tel No.

Address

Fax No.

HITACHI CABLE AMERICA INC.

1-914-993-0991

001-1-914-993-0997

Europe

HITACHI CABLE
INTERNATIONAL, LTD. (LONDON)

001-44-71-439-7223

001-44-71-494-1956

Sigapore

HITACHI CABLE
INTERNATIONAL, LTD (SINGAPORE)

001-65-2681146

001-65-2680461

Hong Kong

HITACHI CABLE
INTERNATIONAL, LTD (HONG KONG)

001-852-721-2077

001-852-369-3472 .

Manufacturer: Mitsui Mining and Smelting Co.• Ltd.
Area

Address

Tel No.

Fax No.

U.S.A.

MITSUI MINING AND
SMELTING CO. (USA) INC.

212-679-9300 to 2

212-679-9303

Europe

MITSUI MINING AND
SMELTING CO., LTD.
London Office

71-405-7717 to 8

71-405-0227

Asia

MITSUI MINING AND
SMELTING CO., LTD.
MICROCIRCUIT DIVISION

03-3246-8079

03-3246-8063

Manufacturer: Shindo Company Ltd.
Area

Address

Tel No.

Fax No.

U.S.A.

SHINDO COMPANY LTD.,
U.S. BRANCH OFFICE
2635 NORTH FIRST ST., STE. 124
SAN JOSE, CA 95134 U.S.A.

408-435-0808

408-435-0809

64

HITACHI

TCP
Aeolotropy Conductive Film Manufacturers
Manufacturer: Hitachi Chemical Co., Ltd.
Area

Addre..

Tel No.

Fax No.

USA

Hitachi Chemical Co., America, Ltd.
4 International Drive, Rye Brook,
NY 10573, U.S.A.

(914) 934-2424

(914) 934-8991

Europe

Hitachi Chemical Europe GmbH.
Immermannstr. 43, D-4000
DOsseldorf 1, F. A. Germany

(211) 35-0366 to 9

(211) 16-1634

S.E.Asia

Hitachi Chemical Asia-Pacific Pte, Ltd.
51 Bras Basah Road, #08-04
Plaza By The Park, Singapore 0718

337-2408

337-7132

Taiwan

Hitachi Chemical Taipei Office
Room No. 1406, Chia Hsin Bldg.,
No. 96, Sec. 2, Chung Shang Road N,
Taipei, Taiwan

(2) 581-3632,
(2) 561-3810

(2) 521-7509

Beijing

Hitachi Chemical Beijing Office
Room No. 1207, Beijing Fortune Building,
5 Dong, San Huan Bei-Lu, Chao Yang
District, Beijing, China

(1) 501-4331 to 2

(1) 501-4333

Hong Kong

Hitachi Chemical Co. (Hong Kong) Ltd.
Room 912, Houston Centre, 63 Mady Road,
Tsimshatsui East, Kowloon, Hong Kong

(3) 66-9304 to 7

(3) 723-3549

Manufacturer: Sony Chemicals
Area

Address

Tel No.

Fax No.

U.S.A.

SONY CHEMICALS
CORPORATION OF AMERICA

1-(708) 616-0070

1-(708) 616-0073

Europe

SONY CHEMICALS
EUROPEB.V.

31-20-658-1850

31-20-659-8481

Southeast
Asia

SONY CHEMICALS
SINGAPORE PTE LTD.

65-382-1500

65-382-1750

References
1. KAPTON. V Catalog

Du Pont-Toray Co., Ltd.

2. UPILEX. S Catalog

Ube Industries, Ltd.

3. Electro-deposited Foil Comparison List

Mitsui Mining Smelting Co., Ltd.
Electronic Devices Group

4. Hitachi Anisotropic Discharge Film

Hitachi Chemical Co., Ltd.
1992.7.21

HITACHI

65

g:

u.r .........

OUtput um OUtput um Input um Input um
PItch
Length
PItcII
Length
Input um

~ Width

HD68107T00 LCD driver

180

280

2.5

800

2.0

Arrange'1
A

50.20

20.25

2
3

HD68107TOI
HD68107T11

LCD driver
LCDdriver

80
180

280

2.5

800

2.0

II

32.00

20.25

28.00

12

K

180

3.3

800

2.5

II

32.42

20.00

31.80

8

K

4

HD68107T12 LCD driver

180

250

3.3

800

2.5

A

43.50

20.00

42.40

10

K

180
80

180

3.3

800

2.5

II

32.52

20.00

31.80

8

U

8

HD68107T24 LCD driver
HD68107T25 LCD driver

Sn
Sn
Sn
Sn
Sn

280

2.5

800

2.0

A

32.00

20.25

28.00

8

K

Sn

7

HD68108T00 LCD driver

165

400

2.0

400

2.0

C

8

K

8
9

HD86300TOO ffi analog driver
HD8831OTOO ffie ......lgray.caIe

120
180

300

800

3.0
2.5

A
A

48.00
33.40

21.50
21.00

48.20
31.95

10
8

K

180

2.9
3.0

Sn
Sn

10

HD6833OTAO ffi84 ......lgray.caIe 192

180

3.5

1.5

II

35.30

11.70

33.60

4

11
12

HD88214Tlll Column LCD driver
HD88214TA2 Column LCD driver

80
80

150
180

3.0
3.0

800
800

2.2
2.2

II
II

15.75
18.30

10.50
10.50

13.60
18.40

... 13

HD88214TA3 Column LCD driver

80

200

2.5

800

2.2

II

20.00

9.80

... 14
15

HD88214TAS Column LCD driver
HD88214TA9l Column LCD driver

80
80

200

2.3
2.3

450
450

2.0
1.8

B

220

B

22.70
22.70

16

HD6620STlll Common LCD driver

80

150

3.0

800

2.0

II

17
18

HD68205TA2 Comman LCD driver
HD6620STA3 Common LCD driver

80
80

180
200

2.9
3.0

800
800

2.0
2.0
1.8

;t

l:>
O

3;;

No. 01
Function

OUIpuIa

(pml

~mml

("",I

(mml

650
650

X

Y

(mml

(mml

'·3 Plating

K
U

So

3
3

U
U

Sn
So

19.80

3

U

So

8.00
8.00

22.50
22.50

3
2

U

U

Sn
Sn

15.75

14.70

13.40

4

U

Sn

II
II

18.30
20.00

14.70
14.70

16.40
17.80

4
4

U
U

So
Sn

B
B
B

22.70

12.50

18.20

4

24.25
22.70

12.50
12.50

18.20
18.20

4
3

U
U
U

Sn

1.8
1.8

Sn
Sn

Sn

19

HD68205TAS Common LCD driver

80

220

2.8

20
21

HD68205TA7 Common LCD driver
HD68205TA9l Common LCD driver

80
80

250

220

2.8
2.8

700
700
700

22

HD88224Tlll Column LCD driver

80

210

3.2

800

1.2

II

20.30

8.20

18.00

2

U

23
24

HD88224TA2 Column LCD driver
HD68224TBO Column LCD driver

80
80

200
200

3.3
2.5

780

650

1.3
1.5

II
II

18.40
18.20

9.00
7.80

17.80
17.40

3
2

U
U

25

HD8821STAO Common LCD driver

100

230

2.0

1200

1.7

A

25.60

11.90

24.40

3

U

So

28
27

HD8821STlll Common LCD driver
HD8821STA2 Common LCD driver

101
100

220
180

3.0
4.0

1000
850

1.8
1.5

II
II

25.00
20.40

10.80
11.40

24.40
19.80

3
3

U
U

So
So

28

HD68110TM Column LCD driver

160

HD68110RTAS Column LCD driver

160

2.8
3.2

500
800

1.5
2.0

II
II

15.60
25.00

9.66
10.95

15.00
15.00

4
4

U

29

80
140

U

So
Sn

30

HD6811ORTBO Column LCD driver

160

92

3.8

500

2.0

II

15.60

11.90

15.10

4

U

Sn

31

HD68110RTBI Column LCD driver

160

92

2.4

500

1.2

A

15.60

9.00

15.10

4

U

So

32
33

HD68115TIIO Common LCD driver
HD68115TAI Common LCD driver

180
160

180

3.0

800

2.0

II

32.40

11.00

31

3

U

Sn

250

4.2

800

2.0

A

44.00

13.70

42.9

4

U

Sn

Noles: 1. Inp~ lead arrange: II. Slraighl. B. DivIded. C • Directions
2. Number of porIaations
3. Tape material: K. Kapton. U • Up'"
"Kap1cn' is a trademalk 01 Dupont. Ltd.
'\Jpilex' is a trademaIk 01 Ube Industries, Ltd.

til

~

5' •.

Solder
ANiet Width PnldUCI Tepe
(mml
Length'2 .......
48.80
12
K

No. Pnlduct

_. rs
[! -~~=
/r-!T!

Table 7 Hitachi Standard TCP Product Specifications

Sn
Sn

Sn

g.~

(i""SI
....:10

§.~
51

t.gs-'"
~g

:n~

1Q

-~I
co"='

o fir

f

g-

i
g,
~::r

Q

1-....
~

'"I
fD

til

S'

=

~

a
..,

n

"'CI

I

TCP

J }

I

IJ

I

... .
8 . -.--

"NDIM: 1.DimenllrlnltlOllra/ICII . . to.1IM1un.... OIMtWiNfICIIIld.

2. lMflgU,.be/ows/'lDwl.CftIIIMCtIafIII . . ot1MOUfHlMdbDndlnO .....
3. .......,." _1IamI*I on potting,...

,

u.nn:mm

Figure 18 Hitachi Standard TCP 1- HD61107TOO -

HITACHI

67

TCP

'"

0
0

[n:>1
50'01'

II

lijSl1'1

1'0'1' 5'SI

DO
0

0
(lP fOil (patlero)

Notes: I.Mat'kshallbeslampedonpoUingresm.
2. OimenSlOnal\Qlerancas are ±O.1 mml,ln!essotnllWisenoled.
3.ThehgurebeIoWSl'towsaCfOsssectionalviewollheouterleadbondinga,ea.

§

COPP".~

Adhesive agent
FIlm

unit :mm

Figure 19 Hitachi Standard TCP 2 - HD66107TOI 68

HITACHI

TCP

-.

NoIM:l,~"

:1::0.1 mm ...... 0IMrwtIt

2. n. ...... beIow ......
~ . . cf

...

- - .... bonding .....

~
t

.OL

--

....

RIm

Figure 20 Hitachi Standard TCP 3 - HD66107Tll-

HITACHI

69

TCP

-_...- ~-- r
...

~--

<-

-,................. -

-..................... ..

:1:0.1_ ..... .......

---...

_

2 ............... " - .

§

Figure 21 Hitachi Standard TCP 4 - HD66107Tl270

HITACHI

_. .

--

TCP

Notes: 1. Oimenslonallolerance. are :to.1 mm unles. oth4Irwi.. noted.
2. Theligura below showe a crcnos lectional view of lhe outer lead bonding area.

r § """"'"

AdhniYeaglint

Film

± .0

Figure 22 Hitachi Standard TCP 5 - HD66107T24-

HITACHI

71

TCP

{Paltern

CMf.SiSI

££L$j

,.,in.

Noles: 1. M.-k ehall be stamped on potIkIg
2. Dirnenllorlll toler..cH .r.:tO.1 mm unln. otherwise noted.
3. The figure below shows • em.. sectional view d the OWIr lead bonding ....

§

"-'.~
Adh'liYeagent

T...
un1t :fM\

Figure 23 Hitachi Standard TCP 6 - HD66107T25 72

HITACHI

TCP

COpper leaf (pattern)

(Soiderrasisl

(

t:

 Assembling

Assembling

pac level check
~ Inspection after assemblinf

Appearance after chip
bonding
Appearance after wire
bonding
Pull strength. Compression
width. Shear strength

Quality check of chip
Bonding
Quality check of wire
Bonding
Prevention of open and
short

Appearance after assembling

POC lot judgement
'----Packaga _ _

o

Sealing

(

Final electrical inspection

PQC level check

Failure analysis

[~

Sealing

Appearance after sealing
Outline,. Dimension

Marking

Marking strength

Analysis of failures. Failure
mode. Mechanism

Guarantee of appearance
and dimension

Feedback of analysis information

Appearance inspection
Sampling inspection of
products

9
~

Receiving
Shipment

Figure 3 Example of Inner Process Quality Control
128

HITACHI

Reliability and Quality Assurance

(Failures, Information)
Sales Dept.
Sales Engineering Dept.

r------------------- - - - - - - - - - -- - --- ----------..,
Failure Analysis

Quality Assurance Dept.

I
I
I
I
I

Countermeasure,
Execution of
Countermeasure

I
I

I
I

I
I
I

I
I
I

I
Follow-up and Confirmation of Countermeasure
Execution

L ___________________ _

I
I
I
I

Report
____________________________
JI

Sales Engineering Dept.
Reply

Customer

Figure 4 Process Flowchart of Field Failure

HITACHI

129

Reliability Test Data of LCD Drivers
based on test data and failure analysis
results.

1. Introduction
The use of liquid crystal displays with microcomputer application systems has been
increasing, because of their low power consumption, freedom in display pattern design,
and thin shape. Low power consumption and
high density packaging have been achieved
through the use of the CMOS process and the
flat plastic packages, respectively.
This chapter describes reliability and quality
assurance data for Hitachi LCD driver LSIs

PSG

2. Chip and Package Structure
The Hitachi LCD driver LSI family uses low
power CMOS technology and flat plastic
package. The Si-gate process is used for high
reliability and high density. Chip structure
and basic circuit are shown in figure 1, and
package structure is shown in figure 2.

Gate

Source

Drain

FET2

Figure 2
P-channel
EM OS

N-channel
EMOS

Figure 1 Chip Structure and Basic
Circuit

130

HITACHI

Package Structure

Reliability Test Data of LCD Drivers
3. Reliability Test Results

The test results of LCD driver LSI family are
shown in Tables 1, 2, and 3.

Table 1

Test Result I, High Temperature Operation
(Ta=125°C, Vcc=5.5V)

Device

Sample Size

Component Hour

Failure

HD44100H
HD44102H
HD44103H
HD44780
HD66100F
HD61100A
HD61102
HD61103A
HD61200
HD61202
HD61203
HD61830
HD61830B
HD63645
HD64645
HD61602
HD61603
HD61604
HD61605
HD66840

40
40
40
90
45
80
50
50
40
50
40
40
40
32
32
38
32
32
32
45

40.000
40.000
40.000
90.000
45.000
80.000
50.000
50.000
40.000
50.000
40.000
40.000
40.000
32.000
32.000
38.000
32.000
32.000
32.000
45.000

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Table 2

Test Result 2

Test Item

Test Condition

Sample
Size

Component
Hour

High temp. storage
Low temp. storage
Steady state humidity

Ta-150'C. 1000 h
Ta--55'C. 1000 h
65°C. 95% RH. 1000 h

180
140
860

180.000
140.000
860.000

0
0

Steady state humidity. biased

85'C. 90% RH. 1000 h

165

170.000

Pressure cooker

121'C. 2 atm.l 00 h

200

20.000

2*
0

Failure

1*

Note: * Aluminum corrosion

HITACHI

131

Reliability Test Data of LCD Drivers
Table 3 Test Results 3
Test Items
Thermal shock

Test Condition
o to 100'C
10 cycles
-ss'C to lS0'C
10 cycles
260'C, 10 seconds
21S'C, 30 seconds
230'C, S seconds

Temperature cycling
Soldering heat
Resistance to VPS
Solderability

4. Quality Data from Field Use
Field failure rate is estimated in advance
through production process evaluation and
reliability tests. Past field data on similar
devices provides the basis for this estimation.
Quality information from the users is indispensable to the improvement of product

Sample Size
108

o

678

o

283
88
140

o
o
o

quality. Therefore, field data on products
delivered to the users is followed up carefully.
On the basis of information furnished by the
user, failure analysis is conducted and the
results are quickly fed back to the design and
production divisions.
Failure analysis results on MaS LSls returned
to Hitachi is shown in figure 3.

Damaged by
excessive
voltage
and/or
Good

Assembly
(3.1%)
Poor functional
test pattern
(3.1%)

Figure 3 Failure Analysis Result

132

Failure

HITACHI

Reliability Test Data of LCD Drivers
5. Precautions
5.1 Storage
It is preferable to store semiconductor
devices in the following ways to prevent
deterioration in their electrical characteristics, solderability, and appearance, or breakage.
1. Store in an ambient temperature of 5 to 30'
C, and in a relative humidity of 40 to 60%.
2. Store in a clean air environment, free from
dust and reactive gas.
3. Store in a container that does not induce
static electricity.
4. Store without any physical load.
5. If semiconductor devices are stored for a
long time, store them in unfabricated form.
If their lead wires wires are formed
beforehand, bent parts may corrode during storage.
6. If the chips are unsealed, store them in a
cool, dry, dark, and dustless place.
Assemble them within 5 days after
unpacking. Storage in nitrogen gas is
desirable. They can be stored for 20 days
or less in dry nitrogen gas with a dew
point at -30'C or lower. Unpackaged
devices must not be stored for over 3
months.
7. Take care not to allow condensation during storage due to rapid temperature
changes.

5.2 Transportation
As with storage methods, general precautions for other electronic component parts are
applicable to the transportation of semiconductors, semiconductor-incorporating units
and other similar systems. In addition, the
following considerations must be taken, too:
1. Use containers or jigs whch will not induce
static electricity as the result of vibration
during transportation. It is desirable to use
an electrically conductive container or
aluminium foil.
2. Prevent device breakage from clothes-in-

duced static electricity.
3. When transporting the printed circuit
boards on which semiconductor devices
are mounted, suitable preventive measures against static electricity induction
must be taken; for example, voltage builtup is prevented by shorting terminal circuit. When a conveyor belt is used, prevent
the conveyor belt from being electrically
charged by applying some surface treatment.
4. When transporting semiconductor devices
or printed circuit boards, minimize
mechanical vibration and shock.

5.3 Handling for Measurement
Avoid static electricity, noise, and surge
voltage when measuring semiconductor
devices are measured. It is possible to prevent breakage by shorting their terminal
circuits to equalize electrical potential during
transportation. However, when the devices
are to be measured or mounted, their terminals are left open providing the possibility
that they may be accidentally touched by a
worker, measuring instrument, work bench,
soldering iron, conveyor belt, etc. The device
will fail if it touches something that leaks
current or has a static charge. Take care not
to allow curve tracers, synchroscopes, pulse
generators, D.C. stabilizing power supply
units, etc. to leak current through their terminals or housings.
Especially, while testing the devices, take
care not to apply surge voltage from the
tester, to attach a clamping circuit to the
tester, or not to apply any abnormal voltage
through a bad contact from a current source.
During measurement, avoid miswiring and
short-circuiting. When inspecting a printed
circuit board, make sure that there is no soldering bridge or foreign matter before turning on the power switch.
Since these precautions depend upon the
types of semiconductor devices, contact
Hitachi for further details.

HITACHI

133

Flat Plastic Package (QFP) Mounting Methods
Surface Mounting Package Handling Precautions
1. Package temperature distribution
The most common method used for mounting
a surface mounting device is infrared reflow.
Since the package is made of a black epoxy
resin, the portion of the package directly
exposed to the infrared heat source will
absorb heat faster and thus rise in temperature more quickly than other parts of the
package unless precautions are taken. As
shown in the example in figure 1, the surface
directly facing the infrared heat source is 20"
to 30·C higher than the leads being soldered
and 40"· to 50"C higher than the bottom of the
package. If soldering is performed under
these conditions, package cracks may occur.
To avoid this type of problem, it is recommended that an aluminum infrared heat
shield be placed over the resin surface of the
package. By using a 2-mm thick aluminum
heat shield, the top and bottom surfaces of
the resin can be held to 175"C when the peak
temperature of the leads is 240"C.

2. Package moisture absorption
The epoxy resin used in plastic packages will
absorb moisture if stored in a high-humidity
environment. If this moisture absorption
becomes excessive, there will be sudden
vaporization during soldering, causing the
interface of the resin and lead frame to
spread apart. In extreme cases, package
cracks will occur. Therefore, especially for
thin packages, it is important that moistureproof storage be used.
To remove any moisture absorbed during
transportation, storage, or handling, it is
recommended that the package be baked at
125"C for 16 to 24 hours before soldering.

3. Heating and cooling
One method of soldering electrical parts is
the solder dip method, but compared to the
reflow method, the rate of heat transmission
is an order of magnitude higher. When this

134

method is used with plastic items, there is
thermal shock resulting in package cracks
and a deterioration of moisture-resistant
characteristics. Thus, it is recommended that
the solder dip method not be used.
Even with the reflow method, an excessive
rate of heating or cooling is undesirable. A
rate in temperature change of less than 4"C/
sec is recommended.

4. Package contaminants
It is recommended that a resin-based flux be
used during soldering. Acid-based fluxes
have a tendency of leaving an acid residue
which adversely affects product reliability.
Thus, acid-based fluxes should not be used.
With resin-based fluxes as well, if a residue is
left behind, the leads and other package
parts will begin to corrode. Thus, the flux
must be thoroughly washed away. If cleansing solvents used to wash away the flux are
left on the package for an extended period of
time, paGkage markings may fade, so care
must be taken.
The precautions mentioned above are general points to be observed for reflow. However, specifiC reflow conditions will depend
on such factors as the package shape, printed
circuit board type, reflow method, and device
type. For reference purposes, an example of
reflow conditions for a GFP infrared reflow
furnace is given in figure 2. The values given
in the figure refer to the temperature of the
package resin, but the leads must also be
limited to a maximum of 260·C for 10 seconds
or less.
Of the reflow methods, infrared reflow is the
most common. In addition, there is also the
paper phase reflow method. The recommended conditions for a paper phase reflow
furnace are given in figure 3.
For details on surface mounting small thin
packages, please consult the separate manual available on mounting. If there are any
additional questions, please contact Hitachi,
Ltd.

HITACHI

Flat Plastic Package (OFP) Mounting Methods
30 sec. max.

(Resin)
300

250

'TS

Infrared rays

l&SU;
T2

21 5'C

'-.......r----I

T,

(Solder)

E
~

200

1-5'C/sec

"

i

E
$

time _ _

150

100

Figure 3 Example Vapor-phase Reflow
Conditions
time (sec)

Figure 1 Temperature Profile During
Infrared Heat Soldering
(Example)

140-160'C
~

i"
~

""I

235'C max-

~60sec

I~
1-4·C/sec.

1-5'C/sec
~-------------------------time---

Figure 2 Recommended Reflow
Conditions for QFP

HITACHI

135

Flat Plastic Package (OFP) Mounting Methods
Soldering iron method

Reflow method
(Spare solder)

Reflow method
(Solder paste)

Board

Board

Board
Solder paste

Spare
solder
parts
Soldering
-260'C
(10 seconds)

Preheating
100to 150'C
(20 seconds)

(Resin coating)

~

Preheating
100to 150'C
(20 seconds)
Reflow
235'C
( 10 seconds)
Reflow
235'C
(10 seconds)

(Resin coating)

~
Figure 4 Recommended Paper Phase Reflow Conditions

136

HITACHI

Liquid Crystal Driving Methods
1. Static Driving Method

Driving a liquid crystal at direct current triggers an electrode reaction inside the liquid
cell, degrading display quality rapidly. The
liquid crystal must be driven by alternating
current. The AC driving method includes the
static driving method and the multiplex driving method, each of which has features for
different applications. Hitachi has developed
different LCD driver devices corresponding to
the static driving method and the multiplex
driving method. The following sections
describe the features of each driving method,
the driving waveforms, and how to apply
bias.

Figure 1 shows the driving waveforms of the
static driving method and an example in
which "4" is displayed by the segment
method. The static driving method is the
most basic method by which good display
quality can be obtained. However, it is not
suitable for liquid displays with many segments because one liquid crystal driver circuit is required per segment.
The static driving method uses the frame
frequency (l/t!) of several tens to several
hundreds Hz.

Liquid Crystal Display
and Terminal Connection

Voo

V3

COMo

Voo

Voo

V3

SEG n + 1

r-

n=O. 1•.........• 5
(n=O. 1•.........• 7)

r-

r--

t-

-

r--

OV

COMo-SEGn+ 1
Selected waveform

-

- :-----i
1 frame

'--

'--

'--

---

-V3

tf

COMo-SEGn+ 1
Non-selected waveform - - - - - - - - - - - - - - -

Figure 1

OV

Example of Static Drive Waveforms (Example of HD61602/HD61603)

HITACHI

137

Liquid Crystal Driving Methods
2. Multiplex Driving Method
The multiplex driving method is effective in
reducing the number of driver circuits, the
number of connections between the circuit
and the display cell, and the cost when driving many display picture elements. Figure 2
shows a comparision of the static drive with
the multiplex drive (1/3 duty cycle) in an 8dight numeric display. The number of liquid
crystal driver circuits required is 65 for the
former and 27 for the latter. The multiplex

drive reduces the number of driver circuits.
However, greater multiplexing reduces the
driving voltage tolerance. Thus, there are
limits to the extent of multiplexing.
There are two types of multiplex drive
waveforms: A type and B type. A type, shown
in figure 3, is used for alternation in 1 frame. B
type is used for alternation in between 2
frames (figure 4). B type has better display
quality than A type in high multiplex drive.

c~moo !·1e!JJ~f··:Lb1f1

Static driving
method

••••

l··~·I~·I···········~·j··'
le

ld lc lO.P 2d 2c20.P

Se

Sd Se SO.P

Multiplex driving
method
(1/3 duty cycle)

Figure 2

Example of Comparlslon of Static Drive with Multiplex Drive

common~

common~

~m_ U1Jlfirmrul

,

Innhnnn
U U L

Common-segment j

u

~

,,

.

: 1 frame

Figure 3
138

Common-segment

UU

,,

!

A Type Waveforms
(1/3 duty cycle, 1/3 bias)

Figure 4

HITACHI

B Type Waveforms
(1/3 duty cycle, 1/3 bias)

Liquid Crystal Driving Methods
2.1. 1/2 Bias, 1/2 Duty Drive

pIe of the connection to display '4' on a liquid
crystal display of 7-segment type, and the
output waveforms.

In the 1/2 duty drive method, 1 driver circuit
drives 2 segments. Figure 5 shows an exam-

Uquid Crystal Display
and Terminal Connection

COMo

.:-. . . .~~--COM,

COM,
- - - - - _ - COMo

+,

SEGn

n=O. 1. ·········.11
COMo-SEGn----;_---r-T-i~~r_+_+_--;_­
(Selected waveform)

+,

COMo-SEGn

(Non-selected waveform)

,

I
I

~

v,
ov
v,

1 frame

Figure 5

Example of Waveforms in 1/2 Duty Cycle Drive (B type) (Example of
HD61602)

HITACHI

139

Liquid Crystal Driving Methods
2.2 1/3 Bias, 1/3 Duty Cycle Drive
In the 1/3 duty cycle drive, 3 segments are
driven by 1 segment output driver. Figure 6

Liquid Crystal Display
and Terminal Connection

shows an exampie of the connection to display '4' on a liquid crystal display of 7-segment type, and the output wavefonns.

COMo

Voo
V,

,
:
,

: :
LJi-f1hsV
I

V2

:

Va

'

I

!

COM,

:

:

I

-----COM,

I

i
I

:

:

I

:

I

I

I

----tl--COMo

~~D
V2

Va
VDO
V,
.

COM 2

V2

V3
Voo
V,

SEG n

Vi
I

,
,

I

I

!

:

S E G n, + , L fI u i 1 l 'h J : Voo
V,
,
V2
I

I

,

:,

II

:,

SEG n + 2

d
w

III

:;:

d
w

III

V3

Voo
V,

N

+

d
w

III

V3

n=O. 1. · .. ······.16

V2

V,

---4-----4-----4----0V
COMo-SEG n + 2
(Selected waveform)

,,
,
,

I

-J

Figure 6
140

-V,
-V2
-V3

I-I--~F ~~,

COMo-SEG n
(Non-selected waveform):..- -..........:

1

1 frame

'

Example of Waveforms In 1/3 Duty Cycle Drive (B type) (Example of
HD61602)

HITACHI

Liquid Crystal Driving Methods
2.31/3 Bias, 1/4 Duty Cycle Drive
In the 1/4 duty cucle drive, 4 segments are
driven by 1 segment output driver. Figure 7

shows an example of the connection to display '4' on a liquid crystal display of 7-se9ment type, and the output waveforms.

Voo
V,

COMo

V2

Liquid Crystal Display
and Terminal Connection

V3
I
I
I

a
-D;;j

~

COM 3

iJLflriJ
-LfLhsi-

COM,'

I

'

:

I

:

,'

I
I

I
I

COM 2

.

COM 2
COM,
COMo

'

I

,
I
I
I
I
I

I
I
I

,

COM 3

'

I
I
I

Vee
V,
V2
V3
Vee
V,
V2
V3
Vee
V,

SEGn

+,

SEGn

SEG n

+,

SEGn

V3

n=O, 1..........• 24

V2

V,
COM3-SEGn----+---~--~--_;----~-OV

(Selected waveform)
I

I
I
I

-V3

I

h

COMo-SEG n
(Non-selected waveform)..J
,

I

U

riW~
n r:~
_
I

V,

I

: 1 frame!

:

Figure 7

-j

Example of Waveforms in 1/4 Duty Cycle Drive (B type) (Example of
HD61602)

HITACHI

141

Liquid Crystal Driving Methods
2.41/4 Bias, 1/8 Duty Cycle Drive

VCC

Liquid Crystal Display

COM,
COM 2
COM3
COM4
COM5
COMs

~::

••••

-a.oo.-

;;;;t=
N

M

'o::t

10

(!l(!l(!l(!l(!l

wwwww

CflCflCflCflCfl

COM,

1

II

1

2

1 3 1 4 1···············1

V'~' i I III I
Vcc

G--

-a.oo.-a.oo.--a.tIIID-a.oo.-

....

COM,

I

II i

\

I

I

I

V5

I

I

III

m-31IE
SEG'~~ i IIIII11 uJ 1M
"G,

Vee

I

I

Vs

I

I

V'~I ! II
VLCD

I
:

I

-+ -II

-1

.~~~-_
.._
:

---r= -- -.-=

1

)4VLCD

V4 =VCC-%VLCD
Vs =VCC-VLCD

I

I

I I I I I
I I
I I I I I ______LL~-.--

1

-)4VLCD

COM,-SEG,
(Selected waveform)

1

I

I

I

-VLCD -+~....L

_________--+....L_ _

I

:

-+:- - - - - - - - - - . - 1 - - - - - -

* Example of LCD II.
V2 is same voltage as V3·

---+-:- - - - - - - - - - - . - ; - - - - -

~~~~~

COM 2 -SEG,
(Non-selected waveform) - J.(VLCD
- )4VLCD

:.,

IIII IIT _Ji-g',#
~~

..::

.

I

1

I

-+--

142

11 12

V'~I II III II I ---- II i ~

V, =VCC-J!,OVLCD
V2(V3) =Vcc- )4VLCD

Figure 8

un

8

-;

1 frame

'

Example of Waveforms in 1/8 Duty Cycle Drive (A type) (Example of LCDII)

HITACHI

Liquid Crystal Driving Methods
2.5 1/5 Bias, 1/8 Duty Cycle Drive

1/8 duty.
1/5 bias

45
Segment

~~
Common 1
Common 2

Segment 1

Segment 2

______________

__~II

~r-l~

____

IlL-

____~r-l~________~r_l
IlL~
L.Jl'---_

Common 1

Common 2

Segment 1

Between segment 1
and common 1
(Display off)

Between segment 1
and common 2
(Display on)

Figure 9

Example of Waveforms in 1/8 Duty Cycle Drive (A type) (bample of
HD44100R)

HITACHI

143

Liquid Crystal Driving Methods
2.6 1/5 Bias, 1/16 Duty Cycle Drive

I1I 2 I 3 I 4

Liquid Crystal Display

COM,
COM,
• • • • 0COM2
COM3
COM4~
COMs

I1

rtf III-II-1---'-1

1""""'-----1

VS

-a.oo.-a.oo.-a.oo.-

1~------116

----------l,!-1--

,

I

I

~c-~-_.~------~I~-~

tfIl
~~~: B-a.oo.COM,

III

11II

I

~ -+,-~L--------~~-l-.
I

COMs

I

II

~C_T'_.---------~~---

~; ~!lI~

COM g
COM,o~

SEG,

COM,,-----DOOOIICOM'2--DOO11OCOM'3 -----DDIIOD-

~:::=mw=
COM'6r999r

~ -+,~~--------T_L-~----

,,,

sro,

l#ff

11111____

,

I

,

VLCD

I

I
I

l-

,

I

COM,-SEG,

v, =Vcc- %VLCO
V2=VCC -%VLco
V3=VCC-%VLCO
V4=VCC -%VLco
Vs=VCC-VLCO

1

(Selected waveform) - %VLCO

-VLCO

III

I

I

I

+

!

.~_~,~-L~

I

I

-

I
I

,

,
I

,
I

I

I
I

vLCo-+i_ _ _ _ _ _ _ _ _ _+i_ ___
~----_ _ _ _ _~I_ _- -

Figure 10

144

Example of Waveforms In 1/16 Duty Cycle Drive (A type) (Example of LCDII)

HITACHI

Liquid Crystal Driving Methods
2.7 1/5 Bias, 1/32 Duty Cycle Drive

1321112131---~21112131---13~ 1121
V2

COM,

COM2

Vs
V4
V3
VB
V,
V2
Vs
V4
V3
Va
V,
V2

V5

Va
V1
V2

SEG 2

!:

...

...

,

%VLCD
YsVLCD
- YsVLCD

(Non-selected waveform)
-%VLCD

~
,,
,

~ ···it

I

--'1,

.--~

;

n

VLCD

COM, to SEG,

l~

~: =J,

SEG,

§~

E
'

I

II

,
,,
,,

,,

...

,,
,

I
J,
,
,,

I
L
,

._.l±:

:

--',

t--

I

-VLCD - - i - - - - f - - - - - VLCO ~----i--t-----

COM, to SEG a

YsVLCD ~--,---i--t---~----t-

(Selected waveform)

- YsVLco-;r+----i--J"---_··--1--

- VLCD -I'--'-----i-,_ _ _---L-L_

,

1 frame

Figure 11

II

Example of Waveforms in 1/32 Duty Cycle Drive (Example of HD44102CH,
HD44103CH)

HITACHI

145

Liquid Crystal Driving Methods
3. Power Supply Circuit for Liquid
Crystal Drive
Table 1 shows the relationship between the
number of driving biases and display duty
cycle ratios.

3.1 Resistive Dividing
Driving bias is generally generated by a
resistive divider (figure 12).
The resistance value settings are determined

Table 1

by considering operating margin and power
consumption. Since the liquid crystal display
load is capacitive, the drive waveform itself is
distorted due to charge/discharge current
when the liquid crystal display drive
waveform is applied. To reduce distortion, the
resistance value should be decreased but this
increases the power consumption because of
the increase of the current through the dividing resistors. Since larger liquid crystal display panels have larger capacitance,the
resistance value must be decreased proportionally.

Relationship between the Number of Display Duty Cycle Ratio and the
Number of Driving Biases

Display
duty ratio
Number of
driving biases

Static
2

1/2

1/3 1/4 1/7 1/8 1/11 1/12 1/14 1/16 1/24 1/32 1/64

344
(1 /2 bias) (1/3 bias)

5
5
(1/4 bias)

5

5

Vee

V2
Va

V,
R

~

R
V2
R

R

Va
R
V4

V4

R

R
Vs

Vs

,..),kVR
-5V

1/4 Bias (1 /B, 1/11 duty cycle)

Figure 12

146

-,
R

R
V,

6

VcC<+5V)

VcC< +5 V)
Vee

6
6
(1/5 bias)

.-'/tVR
-5V

1/5 Bias (1/16 duty cycle)

Example of Driving Voltage Supply

HITACHI

6

6

Liquid Crystal Driving Methods
It is efficient to connect a capacitor to the
resistors in parallel as shown in figure 13 in
order to improve charge/discharge distortion.
However, the effect is limited. Even if it is
attempted to reduce the power consumption
with a large resistor and improve waveform
distortion with a large capacitor, a level shift
occurs and the operating margin is not improved.
Since the liquid crystal display load is in a
matrix configuration, the path of the charge/
discharge current through the load is com-

plicated. Moreover, it varies depending on
display condition. Thus, a value of resistance
cannot be simply determined from the load
capacltance of liquid crystal display. It must
be experimentally determined according to
the demand for the power consumption of
the equipment in which the liquid crystal
display is incorporated.
Generally, R is 1 kO to 10 kO, and VR is 5kO to
50 kO. No capacitor is required. A capacitor of
0.1 uF is usually used if necessary.

Vcc (+5V)
Vee
R

Common/segment selected high level
C

R

Common non-selected high level
C

V,
V2

R

Segment non-selected high level
C
Segment non-selected low level
C

R

Common non-selected low level
C

R

V3
V.

Common/segment selected low level

V5
VR
-5V

For contrast adiustment

Large C and R cause
a level shift.

Figure 13

Example of Capacitor Connection for Improvement of Liquid Crystal
Display Drive Waveform Distortion (1/5 bias) (Example of LCD-II)

HITACHI

147

Liquid Crystal Driving Methods
3.2 Drive by Operational Amplifier
In graphic displays, the size of the liquid
crystal becomes larger and the display duty
ratio becomes smaller, so the stability of liquid crystal drive level is more important than
in small display system.
Since the liquid crystal for graphic displays is
large and has many picture elements, the
load capacitance becomes large. The high
impedance of the power supply for liquid
crystal drive produces distortion in the drive
waveforms, and degcades disiplay quality.
For this reason, the liquid crystal drive level
impedance should be reduced with operational amplifiers. Figure 14 shows an example
of an operational amplifier configuration.
No load current flows through the dividing
resistors because of the high input impedance of the operational amplifiers. A high resistance of R == 10 kO and VR == 50 kO can be
used.

3.3 Generation of Liquid Crystal Drive
Levels in LSI

drive level may be incorporated in the LSI,
such as one for a portable calculator with
liquid crystal display.
HD61602, HD61603 for small display systems
has a built-in power suply circuit for liquid
crystal drive levels.

3.4 Precaution on Power Supply Circuits
The LCD driver LSI has two types of power
supplies: the one for logical circuits and the
other for the liquid crystal display drive circuit. The power supply system is complicated
because of several liquid crystal drive levels.
For this reason, in the power supply design,
take care not to deviate from the voltage
range assured in the maximum rating at the
rise of power supply and from the potential
sequence of each power supply. If the input
terminal level is indefinite, through current
flows and the power consumption increases
because of the use of CMOS process in the
LCD driver.
Simultaneously, the potential sequence of
each power supply becomes wrong, which
may cause latch-up.

The power supply circuit for liquid crystal

Common/segment selected high level

( +5V)Vcc
R

"v

R
R
R
R
VR
(-5 V)VEE

....
....

Segment non-selected high level

~

Segment non-selected low level

l.-.{:>....

Common selected low level

~Contr~t

adiustment

-I>Figure 14

148

Common non-selected high level

Common/segment selected low level
For liquid crystal drive logic circuits
Operational amplifier voltage follower

Drive by Operational Amplifier (1/5 bias)

HITACHI

Data Sheets

HITACHI

HITACHI

HD44100R
(LCD Driver with 40-Channel Outputs)
- Preliminary Pin Arrangement

Description
The HD44100R has two sets of 20-bit bidirectional shift registers. 20 data latch flipflops
and 20 liquid crystal display driver circuits. It
receives serial display data from a display
control LSI. converts it into parallel data and
supplies liquid crystal display waveforms to
the liquid crystal.
The HD44100R is a highly general liquid
crystal display driver which can drive a static
drive liquid crystal and a dynamic drive liquid
crystal. and can be applied as a common
driver or segment driver.

~

::l ::I

;;; iii

»>->>-

~;II

1:0 ~ It; i

»»»
\!

e!

~:il

54 V6

V,

V.

v,
v,
..

V.
FC5
SHL2
SHLI
M
NC

Features
•
•
•

•
•

•
•

•

•

Liquid crystal display driver with serial/
parallel conversion function
Serial transfer facilitates board design
Capable of interfacing to liquid crystal
display controllers: HD43160AH. LCTC
(HD61830/61830B). LCD- II (HD44780S.
HD44780U). LCD-IIA (HD66780).
LCD-II/E (HD66702). LCD-IIi (HD44790).
HD66710
40 internal liquid crystal display drivers
Internal serial/parallel conversion circuits:
-20-bit shift register x 2
-20-bit data latch x 2
Display bias: Static to 1/5
Power supply:
-Internal logic: Vcc=2.7 to 5.5V
-Liquid crystal display driver circuit:
VCC-VEE=3 to 13V
Separation of internal logic from liquid
crystal display driver circuit increases
applicable controllers and liquid crystal
types
CMOS process

~~N

CIO~

.;. .;. .;...: .;

~

~r;~

~~

.;..;.;.;:..;.;.

(Top View)

Ordering Information
Type No.

Vee (VI

Vee-VEE (VI

Package

HD44100RFS

2.7 to 5.5
2.7 to 5.5

3 to 13
3 to 13

60-pin Plastic QFP (FP-60A)

HCD44100R

HITACHI

Chip

151

HD44100R
Block Diagram

v,

r-----------------;
I

Vl, V2

I

I

LCD Drivers

V3, V4

off'

Latch signal

CLl

I Shift

20-bit latch

direction

it

Data

DLl

Shift sIgnal

t

Data

.1
~gCircuit

CL2
~

DL2
FCS

Data

20-bit bidirectional shift register

1 Data

DR2

'-

~~

-~
tlD-t

SHL2

Shift

J direction

20-bit latch

SWitchi~9 circuit

M

,{}.

Vl, V2

LCD Drivers

V5, V6

SHLl

DRl

20-bit bidirectional shift register

I

I

I

~----------------i
v,o

Absolute Maximum Ratings
Symbol

Item
Supply

Logic

voltage

LCD drivers

Vee*'

Vr,

Input voltage

*,

Value
- 0.3 to + 7.0

Unit
V

Vee - 15.0 to Vee + 0.3

V

- 0.3 to Vee + 0.3

v

Input voltage

Vee + 0.3 to VEE - 0.3

V

Operating temperature

Topr

- 20 to + 75

'C

Storage temperature

Tstg

-

Notes:

152

*1
*2
*3

55 to + 125

All voltage values are referred to GND.
Connect a protection resistor of 220 {) ± 5 % to VEE power supply in series.
Applies to V,to Vs.

HITACHI

'C

HD44100R
Electrical Characteristics
(Vee

= 2.7 to 5.5 V. Vee

- Vo

= 3 to 13 V. GND = 0

Symbol Applicable Terminals

Item
Input voltage

Min

=-

Typ Max

V,H

CL1, CL2, DL1, DL2,

0.7 Vee

DR1, DR2, M, SHL1,
V,l

SHL2, FCS

DL1, DL2, DR1, DR2

Vee - 0.4-

Output voltage VOH

V. T.

20 to

+ 75°C)

Unit Teat Condition

Vee

V

Vee=4.5 to 5.5V

0.8 Vee

Vee

V

Vee=2.7 to 4.5V

0

0.3 Vee

V

Vee=4.5 to 5.5V

0

0.2 Vee

VOL

V

Vee=2.7 to 4.5V

V

10H = - 0.4 rnA

0.4

V

10l =

20

kn

±Id = 0.05 rnA, Vec-VEE=4V

+ 0.4 rnA

On resistance

RON

*1

Input leakage
current

I,l

CL 1, CL2, DL 1, DL2,
DR1, DR2, M, SHL1,
SHL2, FCS, NC

- 5.0

5.0

#A

Vi" = 0 to Vee

Vi leakage
current

IVl

*2

- 10.0

10.0

#A

Vi" = Vee to VEE

Power supply
current

Icc

*3

1.0

rnA

fcl2 = 400 kHz

10

#A

fel1 = 1 kHz

Notes: *1
*2
*3

lEE

Applies to the resistance between V; and Yj when a current ± Id = 0.05 rnA flows through
all of the Y pins.
Output Y1 to Y40 open.
Input/output current is excluded; when input is at the intermediate level with CMOS,
excessive current flows through the input circuit to the power supply. To avoid this, input
level must be fixed at high or low.

HITACHI

153

HD44100R
Timing Characteristics
(Vee

= 2.7 to 5.5 V, Vee

- VEE

=3

to 13 V, GND

=0

Min

V, Ta

=-

Typ Max

20 to
Unit

Item

Symbol

Applicable Terminals

Data shift
frequency

fel

CL2

Clock

high level

tCWH

CL1. CL2

800

ns

width

Low level

400

+

75'C)

Test Condition

kHz

tCWl

CL2

800

ns

Data set-up time

tsu

DL1. DL2. DRt. DR2.
FLM

300

ns

Clock set-up time

tSl

CL1. CL2

500

ns

(CL2---CL 1 )

Clock set-up time

tlS

CL1. CL2

500

ns

(CL 1---CL2)

Data delay time

tpd

Cl = 15 pF

DL1. DL2. DR1. DR2

500

ns

Clock rise/fall time tct

CL1. CL2

200

ns

Data hold time

DL1. DL2. DR1. DR2.
FLM

tOH

300

ns

\14-----tCWL----i)

CL2

t ct
1-------tDH

Data in
(DLI. DL2. DR\, DR2)
_ - - " ' _ _J

Data out
_ _ _- - J
(OLI. DL2. DRI. DR2)

~----t

SL----!-I

I - - - - t LS-----i

CLI
1----tCWH----I

FLM

Figure 1 Timing Waveform

154

HITACHI

HD44100R
Terminal Function
Table 1 Functional Description of Terminals
Signal
Name

Number
of Lines

Input/
Connected to

Function

Vee

power supply

Power supply for logical circuit

GND

Power supply

OV

VEE

Power supply

Power supply for liquid crystal display drive
Liquid crystal driver output (Channel 1)

Output

Y,-Y20

20

Output

Liquid crystal

Y21-Y40

20

Output

Liquid crystal

Liquid crystal driver output (Channel 2)

V" V2

2

Input

Power supply

Power supply for liquid crystal display drive (Select level)

V3, V4

2

Input

Power supply

Power supply for liquid crystal display drive (Non-select
level for channel 1)

V5, Va

2

Input

Power supply

Power supply for liquid crystal display drive (Non-select
level for channel 2)

Input

Vee or GND

Selection of the shift direction of channel 1 shift register

SHL1

Input

SHL2

DL1,DR1

Vee or GND

SHL1

DL1

Vee

Out

DR1
In

GND

In

Out

Selection of the shift direction of channel 2 shift register
SHL2

DL2

DR2

Vee

Out

In

GND

In

Out

2

Input/
output

Controller
or HD44100R

Data input!output of channel 1 shift register

DL2,DR2 2

Input/
output

Controller
or HD44100R

Data input!output of channel 2 shift register

M

Input

Controller

Alternated signal for liquid crystal driver output

CL1

Input

Controller

Latch signal for channel 1 (~)
1
Used for channel 2 when FCS is GND

CL2

Input

Controller

Shift signal for channel 1 (~)
1
Used for channel 2 when FCS is GND

FCS

Input

Vee or GND

Mode select signal of channel 2. FCS signal exchanges the
latch signal and the shift signal of channel 2 and inverts M
for channel 2. Thus, this signal exchanges the function of
channel 2.

*

*

Channel 2
FCS Level

NC

Notes:

Latch signal

Shift signal

M Polarity Function

Vee

CL2

-1

CL1

~

M

For common drive

GND

CL1

~ CL2

"-"L

M

For segment drive

Don't connect any wires to this terminal.

*1

-1

and ~ indicate the latches at rise and fall times, respectively.
*2 The output level relationship between channel 1 and channel 2 based on the FCS signal
level is as follows:
.

HITACHI

155

HD44100R
Output Level

Data

FCB

M

Channel 1 (Y,-Yzo)

Channel 2 (YZ,-Y40)

V,

V2

Vce

(Select)

0

V2

V,

(1 )

0

1

V3

Va

(Non-select)

0

V4

V5

V,

V,
V2

GND

(Select)

0

V2

(0)

0

1

V3

V5

(Non-select)

0

V4

Va

1 and 0 indicate high and low levels, respectively.

Applications
Segment Driver
When the HD44100R is used as a segment
driver, FCB is set to GND to transfer display
data with the timing shown in figure 2. In this

(FLM)

case, both channel 1 and channel 2 shift data
at the fall of CL2 and latch it at the fall of CLI.
V3 and V5, V4 and Va of the liquid crystal
display driver power supply are short-circuited, respectively.

81234567812
7
____
__________________
___
~.r_r~

~r_r~

M

eL1
Output of
latch
(V,-V40l

-------------------------J-Ir-------

M

________~rl~__

CL1

Shift

CL2
DL1/DR1

LIl.Sl.JtIl..j-----LIl.Sl.JtIl..j
----y--v--y---y--------v--v--v--v--

DL2/DR2~-----~

Figure 2

156

Segment Data Waveforms (A Type Waveforms, 1/8 Duty Cycle)

HITACHI

HD44100R
Common Driver

display data with the timing shown in figure

In this case, channel 1 is used as a segment

In this case, channel 2 shifts data at the rise of
CLl and latches it at the rise of CL2. Channel
1 shifts and latches as shown in figure 2.

3.

driver and channel 2 as common driver.
When channel 2 of HD44l00R is used as
common driver, FCS is set to Vcc to transfer

r-,-" 2

I
n
II n
Shift ....I - - - - - - - - - - - - '
I ~ ___U I
I
8

DL2/DR2(FLM),

3

4

5

6

7

8

1

2

L._ __

CL1

I

I

Non-select
~
Select.'------------:Select
Non-select
Select-Select
Non-select------n

!"

n

!

n

n

-lJI
I

\

Select

Select'-----

Enlarged view \
\

DL2/DR2(FLM) ' M
CL1

CL2

Figure 3

Common Data Waveforms (A Type Waveforms of Channel 2, 1/8 Duty
Cycle)

HITACHI

157

HD44100R
Both Channel 1 and Channel 2 Used
Common Drivers (FCS = GND)

8S

When both of channel 1 and channel 2 of
HD44100R are used common drivers, FCS is
set to GND and the signals (CL1, CL2, FLM)
from the controller are connected as shown in
figure 4.
In this case, connection of the liquid crystal
display driver power supply is different from
that of segment driver, so refer to figure 4.
e Vl, V2: Select level of segment and common
e V3, V4: Non-select level of segment
e· V5, V6: Non-select level of common

Static Drive
When the HD44100R is used in the static
drive method (figure 5), data is transferred at

-

...C.:cL
" '1'--_ _ _ _-iCL2
CL2

Controller
(HD43160AH)
etc.

CL1

~ :3 ~
u..1j51j5

the fall of CL2 and latched at the fall of CL1.
The frequency of CLl becomes the frame
frequency of the liquid crystal display driver.
The signal applied terminal M must have
twice the frequency of CLl and be synchronized at the fall of CL1. The power supply for
liquid crystal display driver is used by shortcirCuiting Vl, V4 and V6, and V2, V3, and V5
respectively.
One of the liquid crystal display driver output
terminals can pe used for a common output.
In this case, FCS is set to GND and data is
transferred so that 0 can be always latched in
the latch corresponding to the liquid crystal
display driver output terminal used as the
common output. If the latch signal corresponding to the segment output is 1, the
segments of LCD light. They also light for
common side = 1, and segment side O.

Y1 -Y40

I-F:...:L::::M"--_ _ _ _-IDL 1 Common
[

LCD

QR1 driver

DL2
DR2

,;,;,;»>

I

!Y1 -Y4Q

VZ
V5
V4
Cl a;
jg 1ii
Va
0 ~
> <.> >'O.!!2 VB
~ '5 a.
'i:: 0- .!!l
V1

"0

'"

HD44100R
Segment
driver

,I
I

>~>':>~~

1 I I I I

Y1 -Y4Q

HD44100R
Segment
driver

>~>':>~~

j

JJJJ

Cl~'O

Figure 4

158

Connection When Both Channels Are Common Drivers

HITACHI

HD44100R

First Second
Tenth
figure figure - - - - - - - - - - - - - - - - ---...,- - - - - - - - - figure

n

C

8c

COM signal

CMOS
~ ~ inverter

1-'

~ 40 -r-SEG,-SEG40

r:=rr-

Y,-Y40

DR,

HD44100R

DL2
DR2

DL,
FCS
SHL,
SHL2

VEE

.s » »
u u'2
~

....

N

(II')

.,.

...

>

. . , - 40 - r - SEG4,-SE Gao

~

,.-

..
>

Y,-Y40

DR,

HD44100R

DL2
DR2

DL,
FCS
SHL,
SHL2

VEE

]
-

dd'2»»»

I 1
1

I

I

Vee

GND

Figure 5

Static Drive Connection

Timing Chart of Input Waveforms

1

2

3

78

C L 2 - - - . l U U L •.•••.

o

79

80

~

~EG8*EG7~SEG78 ••.••..•

SEG3XSEG2XSEG1X= (Display Doff8ta)
1:on 0:

---IrL

CL, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Notes:
1. Input square waves of 50% duty cycle (about
30-500 Hz) to M. The frequency depends
on the specifications of LCD panels.
2. The drive waveforms corresponding to the
new displayed data are output at the fall of
CL 1 . Therefore. when the alternating signal
M and CL 1 do not fall synchronously. DC
elements are produced on the LCD drive
waveforms. These DC elements may shorten
the life span of the LCD. if the displayed data
frequently changes (e.g. display of hours.
minutes. and seconds of a clock). To avoid

(Shift Clock)

(Latch Clock)

this. have CL 1 fall synchronously with the
one edge of M.
3. In this example. the CMOS inverter is used as
a COM signal driver in consideration of the
large display area. (The load capacitance on
COM is large because it is common to all the
displayed segments.)
Usually. one of the HD44100R outputs can
be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in
that case.

HITACHI

159

HD44100R

39

COM
LCD

Y,

I}-Y~
SHL'.2

HD44100R

D~-----~
\.

~

y

Data transformed
to Y2 to Y40

)

~

Data 0 corresponding to
Y, (COM signal)

IL

Cl,

160

40

CL2SLrU--------~

r-

HITACHI

HD66100F-----------(LCD Driver with SO-Channel Outputs)
The HD66100 description segment driver
with 80 LCD drive circuits is the improved
version of the no longer current HD44100H
LCD driver with 40 circuits.
It is composed of a shift register, an 80-bit
latch circuit, and 80 LCD drive circuits. Its
interface is compatible with the HD44100H.
It reduces the number of LSI's and lowers the
cost of an LCD module.

Comparison with HD44100H
Table 1 shows the main differences between
HD66100 and HD44100H.

Table 1

Deffenee. between Products
HD66100 and HD44100H
HD881 00

Features
•
•

•
•

•
•

LCD driver with serial/parallel converting
function
Interface compatible with the HD44100H;
connectable with HD43160AH, HD61830,
HD61830B, LCD-U (HD44780), LCD-ill
(HD44790)
Internal output circuits for LCD drive: 80
Internal serial/parallel converting circuits:
-SO-bit bidirectional shift register
-SO-bit latch circuit
Power supply
-Intemallogic circuit: +5 V ±10%
-LCD drive circuit: 3.0 V to 6.0 V
CMOS process

LCD Drive Outputs 80 x 1 Channel
SupplV Voltage
3 to 6 V
for LCD Drive
Circuits
Multiplexing
Static to 1/16
duty
Duty Ratio
100-pin
Package
plastic OFP

HD44100H

20 x 2 channels
4.5 to 11 V
static to 1/32
duty
60-pin
plastic OFP

Ordering Information
No_
HD66100F
HD66100FH
HD66100D

Type

HITACHI

100-pin plastiC OFP (FP-100)
100-pin plastic OFP (FP-100B)
Chip

161

HD66100F
Pin Arrangement

~~~~~J~~;IIJJ~~J~~~~~Jil~

II

n n II n II

(Top View)

162

HITACHI

U • II II II II II II R II II

HD66100F
Pin Description
Vee. GND. VEE: Vec supplies power to the
internal logic circuit. GND is the logic and
drive ground. VEE supplies power to the LCD
drive circuit.
VI. Vz. V3. and Vc: VI to V4 supply power for
driving an LCD (figure 2).
CL1: HD66100 latches data at the negative
edge of CLl.
CL2: HD66100 receives shift data at the negative edge of CL2.

DI: Inputs data to the shift register.
DO: Output data from the shift register.
SHL: Selects a shift direction of serial data.
When the serial data is input in order of DI. D2.
.... D79. Dao. the relation between the data and
the output Y is shown in table 3.
YI-Y80: Each Y outputs one of the four voltage
levels-VI. V2. V3. or V4-according to the combination of M and display data (figure 2).

M: Changes LCD drive outputs to AC.

NC: Do not connect any wire to these terminals.

Table 2

Table 3

Pin Function

Symbol Pin No_

Pin Name

46
36
31
32
33
V2
34
V3
35
V4
CL1
37
CL2
40
M
44
01
41
DO
42
SHL
39
Y,-Yao 1-30.51-100
NC
38,43,45,47-50

Vee
Ground
Vee
V,

Vee
GNO
Vee
V,

Relation Between
Data Output

SHL

and

1/0

V2
V3
V4
Clock 1
Clock 2
M

Date In
Date Out
Shift Left
Y,-Yso
No Connection

I

SHL

V1

Vz

V3-..u. V7S

High

01

02

03 ...... 079 080

Low

080

079

078 .....

M~

V80

02

01

I

0

0

I
0

0
Y output

level

I_

V,

.. 1....1..
V3

V2

-I..

V4

..I

When used as a common driver
Figure 1 Selection of LCD Drive Output

~

.==~:
----V4
----V2

V,. V2 : Selected level
V3. V4: Non-selected level
Figure 2

Power Supply for Driving an LCD

HITACHI

163

HD66100F
Block Functions
LCD Drive Circuits

Bidirectional Shift Reigster

Select one of four levels of voltage V 1, V2, V3,
and V4 for driving a LCD and transfer it to the
output terminals according to the combination of M and the data in the latch circuit.

Shifts the serial data at the fall of CL2 and
transfers the output of each bit of the register
to the latch circuit. When SHL = GND, the
data input from DI shifts from bit 1 to bit 80 in
order of entry. On the other hand, when SHL
= Vee, the data shifts from bit 80 to bit-i. In
both cases, the data of the last bit of the
register is latched to be output from DO at
the rise of CL2.

Latch Circuit
Latches the data input from the bidirectional
shift register at the fall of CLl and tranSfer its
outputs to the LCD drive circuits.

SHL=GND

DI

00---------------------------------------------"
SHL=Vcc

CL2---.n"!'r-~-_;,:;;_:=:__---6~
OI-----r--------------------------------------~
DO

Figure 3 Relation between SHL and the Shift Direction

164

HITACHI

HD66100F

Yl Y2

'1'1

M
(altern ating signal)

1'1'1
cL1

LCD drive outputs

Y79Y'O

LCD drive circuit

r-

""

79 80

.. . . . . .... . . .. .. "1"'1
'1'1
. .. . . . . . . . . . .. . . "1"'1

"~ [-;:j'I'1
~ I

VI, V2, V3, V4

... . . . . .. . .. .. . . 1

(power supply for

LCDd rive circuit)

Level shifter

Latch circuit

(I.tch clock)

DI
(in put data)

. .... .. . . ... ....

Bidirectional shift register

I"I~

-

I-- Vee

-

r- GND
r- VEE

c-

.. ~
"~

DO
(output data)

.~

"Ii'

.l

.l

I"

T

cL2
( shift clock)

SHL
{selects
a shift direction)

Figure 4 Block Diagram

HITACHI

165

HD66100F
Primary Operations
Shifting Data
The input data DI shifts at the fall of CL2 and
the data delayed 80 bits by the shift register
is output from the DO terminal. The output of
DO changes synchronously with the rise of
CL2. This operation is completely unaffected
by the latch clock CL1.

Latching Data
The data of the shift register is latched at the

negative edge of the latch clock eLl. Thus,
the outputs Yt-Yso change synchronously
with the fall of CL1.

Switching Data Shift Direction
When the shift direction switching signal
SHL is connected with GND, the data D80,
immediately before the negative edge of CL1,
is output from the output terminal Yt. When
SHL is connected with Vcc, it is output from
Yeo.

Shift dock CL2

Input data

Output data

DI

DO

Figure 5 Timing of Receiving and Outputting Data

Shift c1.ck CL2

~ ........... ~

____rL

Latch dock eLl

Outputs

--'[

Yl· Y80

Figure 6 Timing of Latching Data

166

HITACHI

HD66100F

SHL=GND
Shift cloek

CL2

JUlJL. . . . . . . . . . . . ..JLJUL

Input data

Latch clock

CLI

YI
Outputs

- - - -......................... ~

- - - - - : ::: :
.... .••.•....•

.. .....•........ •... ----~

:::

to
Y80

SHL=Vcc
Yl
Outputs

- - - - -.. . . . . . . . . . . . ----v-;,- -_ _ _ _ ......................... _ _ _~A...:::...._

to
Y80

-----:::::::::::::::::::::::::____>e:::

Figure 7 SHL and Waveforms of Data Shift

HITACHI

167

HD66100F
Absolute Mazimum Ratings
Item

Supply
Voltage

Logic Circuits

Symbol

RatIngs

Unit

Note

Vee

-0.3 to +7.0

V

*1

-0.3 to +7.0

V

LCD Drive Circuits Vee-Vee
Input Voltage (1)

Vrl

-0.3 to Vee + 0.3

V

*1

Input Voltage (2)

Vr2

Vee + 0.3 to Vee - 0.3

V

*2

Operation Temperature

Topr

-20 to +75

·C

Storage Temperature

Tstg

-55 to +125

·C

* 1 A reference point is GND (= 0 V)
*2 Applies to Vl-V4.
Note: If used beyond the absolute maximum ratings, LSls may be permanently destroyed. It is best to
use them at the electrical characteristics for normal operations. If they are not used at these
conditions, it may affect the reliability of the devi~.

168

HITACHI

HD66100F
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, Vee-Va=3.0 to 6.0 V, GND = 0 V, T. = -20 to +75"C)
Item

Symbol

Termina'. Min.

Input High Voltage

VIH

CL1, Cl2

Typ.

Input low Voltage

Vil

0.8 x VccM, 01, SHl 0

Output High Voltage

VOH

DO

Output low Voltage

VOL

On Resistance
Vi-Vj

RONI

Max.

Unit

Vcc

V

0.2 x VccV
V

IOH = -0.4 rnA

0.4

V

IOl = +0.4 rnA

11

kO

ION = 0.1 rnA to
one Y terminal

VI-V4

30

kO

ION = 0.05 rnA to
each Y terminal

Cl1, Cl2, -5.0
M, 01, SHl
-5.0
VI-V4

5.0

J.lA

Vin = 0 V to Vec

5.0

J.lA

Output YI-Yeo open
Vin = Vec to Vee

rnA
rnA

Vcc-O. 4 -

YI-Yeo
RON2

Input leakage Current hl
Vi leakage Current

Ivl

Current Dissipation

IGND

2.0

lee

0.1

*1

Teat condition

fCL2 = 1.0 MHz

Nola

*1

fClI = 2.5 kHz

Input/output currents are excluded; when an input is at the intermediate level in CMOS, excessive
current flows from the power supply through the input circuit.
To avoid this, VIH and Vil must be fixed at Vcc and GND level respectively.

AC Characteristics
(Vee = 5 V ± 10%, Vee-Va = 3.0 to 6.0 V, GND = 0 V, T. = -20 to +75"C)
Item

Symbol

Termina'.

Data Shift Frequency

fCl

Cl2

Min.

Typ.

Max.

Unit

Note

MHz

Clock High level Width

tCWH

CL1 ,Cl2

450

ns

Clock low level Width

tcwl

Cl2

450

ns

Data Set-Up Time

fsu

01

100

ns

Clock Set-Up TIme (1)

tSl

Cl2

200

ns

*1

Clock Set-Up Time (2)

tLS

CL1

200

ns

*2

Output Delay Time

tpd

DO

ns

*3

Data Hold Time

tOH

01

Clock Rise/Fall Time

feT

CL1 ,Cl2

250
100

ns
50

ns

* 1 Set-up time from the fall of CL2 to that of CL 1 .
*2 Set-up time from the fall CL1 to that of CL2.
*3 Test terminal

CL (Load capacitance on outputs) = 30pF
(Including jig capacitance)

HITACHI

169

HD66100F

tCWL

CL2

tDH

DI

tSL

DO

CLI
tCWH

Figure 8 Timing Chart of HD66100F

170

HITACHI

HD66100F
Typical Applications
Connection with the LCD Controller H044780

COMICOM16

~l-

~

..............

~

....._.......

LCD

~

..

D1

D

I~

VI YIO

SHL

DO - D 1

HD66100F

SHL

dd::E~~::>:::>~

00----

YI YIII

HD66100F

R

ad::E~~:!>::>:>

TIn T

CLI
CL2

I~I

IIII I

M

Vo<

R
R

-------

v.

HD«780

v.
v,
v.
v,

R

Iir=
. "c
R

ontrast

GND

L...e -v

GND

Figure 9 Example of Connection (1/16 duty cycle, 1/5 bias)

...............

COMI-~
COMS

~l~

D

LCD

.

IJ~

{

D1

VI YIO

SHL

HD66100F

IJ~
DO

ad2~~:E»>:>
CLI
CL2
M

II "

I

f-

Dl

VI-YIII

SHL

HD66100F

DOr----

Vee

R

aa2~~~>:::»

IIII

Vee

V.

V.

HD«780

..............

v,

I

R

-----

---

Ir?,,;

ontrast

V.

v.

~ -V

GND

GND

•

wer

[rr

8

LCD'' .I':rve)

Figure 10 Example of Counection (1/8 duty cycle, 1/4 bias)

HITACHI

171

HD66100F
Connection with LCD

In (H044790)

..............

COMI-~
cOM3
3

LCD

f

SEGISEG32

32

Rn

Dl

SHL

I~I
VI Yeo

00 _

HD66100F

ddl!~~:!

I~I

>";0;;;:

00 _ _

YI-VIO

SHL

III

R"
Rn
R..

DI

...............

HD66100F

dd2~~:!>.,;::>

Vee

III

R

OND

y,
y.
y.

H044790

Vee

I

Ii:
J;"
GND

R
R

-v

( we.

f:r Lcn,:rve]

Figure 11 Example of Connection (1/3 duty cycle, 1/3 bias)

Static Drive

First
figure

COM 8qp.ol

4

Second
fipre.

•

•

••

n n
0 0

{:r

CMOS
inverter

D
;---

DI

YI-Y..

SHL

HD66100F

:J~::E

uu

Teath
figure

n
0
SEGl-SEGSO

DO

~~=»»
",:::a;:.

~

I

CLi
CL2
M
Vee

GND

Figure 12 Example of Connection (80-segment display)
172

HITACHI

HD66100F
• Timing Chart of Input Waveforms

78

79

80

Shift clock eL2

--.Jl..JlSL...... ~

[n,uldala

~

Latch clock

Dl

ell

••••••••

~

________________

~nL

Figure 13 Timing Chart of Input Waveforms
Notes:
1. Input square waves of 50% duty cycle (about
30-500Hz) to M. The frequency depends on
the specifications of LCD panels.
2. The drive waveforms corresponding to the
new displayed data are output at the fall of
Cl1 . Therefore, when the alternating signal M
and Cl1 do not fall synchronously, DC elements are produced on the LCD drive
waveforms. These DC elements may shorten
the life span of the lCD, if the displayed data
frequently changes (e.g. display of hours,

minutes, and seconds of a clock). To avoid
this, make Cl1 fall synchronously with the
'one edge of M.
3. In this example, the CMOS inverter is used as
a COM signal driver in consideration of the
large display area. (The load capacitance on
COM is large because it is common to all the
displayed segments.)
Usually, one of the HD66100F outputs can
be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in
that case.

Figure 14 Example of Connection

79

80

CL2

SLJLf·······~

Dl

~ .....~
~~-----~yr-----~I
Data transferred to YZ-Y80

CLl

+

da~ ~c~;;:~::::~ng

_______rL

to

Figure 15 Timing Chart (when Yl is used as a COM signal)

HITACHI

173

HD61100A-----(LCD Driver with SO-Channel Outputs)
Features

Description

Liquid crystal display driver with serial/parallel
conversion function
Internal liquid crystal display driver: 80 drivers
Display duty cycle
Any duty cycle is selectable according to
combination of transfer clock and latch clock
Data transfer rate: 2.5 MHz max.
Power supply
+5 V ± 10% (Internal logic)
Vee:
Vee-VEE: 5.5 to 1. 7 V (Liquid crystal
display driver circuit)
Liquid crystal driving level: 17.0 V max.
CMOS process

The HD61100A is a driver LSI for liquid crystal
display systems. It receives serial display data from
a display control LSI, HD61830, etc., and generates
liquid crystal driving signals.
It has liquid crystal driving outputs which
correspond to internal 80-bit flip/flops. Both static
drive and dynamic drive are possible according to
the combination of transfer clock frequency and
latch clock frequency.

Ordering Information
Type No.

Package

HD61100A

1~O-pin plastic QFP(FP-1 00)

Absolute Maximum Ratings
Item

Symbol

Value

Unit

Note

Supply voltage (1)

Vex

-0.3 to +7.0

V

2

Supply voltage (2)

VEE

Vee -19.0 to Vee + 0.3

V

Terminal voltage (1)

Vn

- 0:3 to Vee + 0.3

V

2,3

Terminal voltage (2)

Vr2

VEE - 0.3 to Vee + 0.3

V

4

Operating temperature

Topr

-20to+75

°C

Storage temperature

Tstg

-55 to +125

°C

Notes:

1.

2.
3.
4.

174

LSls may be permanently destroyed if used beyond the absolute maximum ratings. In ordinary
operation. it is desirable to use them within the limits of electrical characteristics. because
using it beyond these conditions may cause malfunction and poor reliability.
All voltage values are referred to GND =0 V.
Applies to input terminals. FCS. SHL. CL1. CL2. DL. DR. E. and M.
Applies to V1L. V1R. V2L. V2R. V3L. V3R. V4L and V4R. Must maintain:
Vee ~ V1L = V1R ~ V3L = V3R ~ V4l = V4R ~ V2L = V2R ~ VEE.
Connect a protection resistor of 15 n ± 10% to each terminals in series.

HITACHI

HD61100A
Pin Arrangement

V51
V52
V53

V54

V55
V56

V57
V58
V59
V60

V61
V62
V63
V64
V65

V16
V15
V14
V13
V12
V11
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1

V66
V67
V68
V69
V70
V71
V72
V73

V74
V75
V76
V77

V78
V79
V80

(Top view)

HITACHI

175

HD61100A
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, GND

=0

V, Vee-VEE
Min

= 5.5

to 17 V, Ta

= -20

Typ

Max

Unit Test Condition Note

to +75°C)

Item

Symbol

Input high voltage

VIH

0.7 x Vex;

Vex;

V

Input low voltage

VIL

0

0.3 x Vex;

V

Output high voltage

VOH

Vex; -0.4

V

IOH = - 400 IlA

2

Output low voltage

VOL

0.4

V

IOL .. +400 IlA

2

Driver resistance

fb.l

7.5

kn

VEE =-10 V,
Load current =
100).1A

3

Input leakage current

hll

-1

+1

VIN = 0 to Vex;

-2

Input leakage current

hL2

+2

IlA
IlA

Dissipation current (1)

IGNO

1.0

mA

5

Dissipation current (2)

lEE

0.1

mA

5

Notes:

1.

2.
3.
4.
5.

176

VIN =VEE to Vex;

Applies to CL1, CL2, FCS, SHL, E, M, DL, and DR.
Applies to DL, DR, and CAR.
Applies to Y1-Y80.
Applies to V1L, V1R, V2L, V2R, V3L, V3R, V4L, and V4R.
Specified when display data is transferred under following conditions:
CL2 frequency fCP2 = 2.5 MHz (data transfer rate)
CL 1 frequency fcPl = 4.48 kHz (data latch frequency)
M frequency fM = 35 Hz (frame frequency/2)
Specified when VIH = Vce, VIL = GND and no load on outputs.
IGNO: currents between Vee and GND.
lEE: currents between Vee and VEE.

HITACHI

4

HD61100A
AC Characteristics
5 V ± 10%. GND

= 0 V,

Item

Symbol

Min

Clock cycle time

tevc

400

ns

Clock high level width

tCWH

150

ns

Clock low level width

tCWl

150

ns

Clock setup time

tSCl

100

ns

Clock hold time

tHCl

100

Clock riselfall time

tct

Clock phase different time

tCl

100

ns

Data setup time

tDSU

80

ns

(Vee

=

Vee-VEE

= 5.5

Typ

to 17 V, Ta = -20 to +75°C)
Max

ns

30

ns

Data hold time

tDH

100

ns

E setup time

tESU

200

ns

Output delay time

tOCAR

300

ns

M phase difference time

tCM

300

ns

Note:

1.

Test Condition Note

Unit

The following load circuits are connected for specification:
test point

----'1

o-Q

J;. 30 pF
CL 1 - - - - - - - - "
CL2

DL(DR)

CL1

CL2

M

HITACHI

177

=
~ S
m

....,
00

I!I:"

V1l V2l V3l V4l

Y80

Y1 Y2

•.'='
=
~

V1RV2R'iaRV4R

M

±

Cl1

:I:

~0

:I:

vcc
GND
VEE

Dl
DR

SHl
CL2

E·
F C S J - L Test input

I
I
I
I

I,

I

:L________________________
I '
I
I l
Control circuit

• CAR

~
~

o
o

»

HD61100A
Block Function
Liquid Crystal Display Driver Circuit

Selector

The combination of the data from the latch circuit 2
and Msignal causes one of the 4 liquid crystal
driver levels, VI, V2, V3 and V4 to be output.

The selector decodes output signals from the
counter and generates latch clock.1 to .20. When
the LSI is not active, .1 to .20 are not generated,
so the data at latch circuit I is stored even if input
data (DL, DR) changes.

SO-bit Latch Circuit 1
The data from latch circuit I is latched at the fall of
CLI and output to liquid crystal display driver
circuit.

SIP
SeriaI/ParalIel conversion circuit which converts 1bit data into 4-bit data. When SHL is "L" level,
data from DL is converted into 4-bit data and
lransferred to the latch circuit I. In this case, don't
connect any lines to terminal DR which is in the
output status.
When SHL is "H" level, input data from terminal
DR without connecting any lines to terminal DL.

SO-bit Latch Circuit 1

Control Circuit
Controls operation: When E-F/F (enable FIP)
indicates " I", SIP conversion is started by
inputting "L" level to E. After 80-bit data has been
all converted, CAR output turns into "L" level and
E-F/F is reset to "0", and consequently the
conversion stops. E-F/F is RS flip-flop circuit
which gives priority to SET over RESET and is set
at "H" level of CLl.
Counter consists of 7 bits, and the output signals
of upper 5 bits are lransferred to the Selector. CAR
signal turns into "H" level at the rise of CLI and
the number of bit which can be SIP-converted
increases by connecting CAR terminal with E
terminal of the next HD61100A.

The 4-bit data is latched at.1 to.2O and output to
latch circuit 2. When SHL is "L" level, the data
from DL are latched one in order of 1-+2-+3 ... -+
80 of each latch. When SHL is "H" level, they are
latched in a reverse order (80-+79-+78 ... -+1).

HITACHI

179

HD61100A

Terminal Functions Description
Terminal
Name

Number of
Terminals

1/0

Vee
GND

Connected
to

Functions

Power
supply

Vee - GND: Power supply for internal logic
Vee - VEE: Power supply for LCD drive circuit

Power
supply

Power supply for liquid crystal drive.

VEE
Vll-V4l
V1R-V4R

8

Y1-Y80

80

0

LCD

Vll (VIR). V2L (V2R): Selection level
V31 (V3R). V4L (V4R): Non-selection level
Power supplies connected with VIL and VIR (V2L & V2R.
V3l & V3R. V4L & V4R) should have the same voltages.
Liquid crystal driver outputs.
Selects one of the 4 levels. V1. V2. V3. and V4.
Relation among output level. M and display data (D) is as
follows:

M

~

D

~

Output
level

0

I

I~V\ly3·ly2·IY11

M

Controller

Switch signal to convert liquid crystal drive waveform into
AC.

CL1

Controller

Latch clock of display data (fall edge trigger).
Liquid crystal driver signals corresponding to the display
data are output synchronized with the fall of CL 1.

CL2

Controller

Shift clock of display data (D).
Falling edge trigger.

DL.DR

2

1/0

Controller

Input of serial display data (D).
Liquid Crystal
Driver Output

Liquid Crystal
Display

1 (High)

Selection level

On

o {Low}

Non-selection level

Off

(D)

VO status of DL and DR terminals depends on SHL input
level.
SHL
High
Low

180

HITACHI

DL
0

[R

I

0

HD61100A
Terminal Functions Description (cont)
Terminal

Name

SHL

Number of
Terminals

1/0

Connected
to

I

Vccor GND

Functions
Selects a shift direction of serial data.
When the serial data (D) is Input in order of 01 -+ ... -+ 080.
the relations between the data (D) and output Yare as
follows.
SHL
Y1
Y2
V3
Y80

Low
High

01

D2

D3

D80

080

079

078

01

When SHL Is low. data is input from the terminal DL. No
lines should be connected to the terminal DR. as it is in the
output state.
When SHL is high. the relation between DL and DR
reverses.

E

GNDorthe
terminal
OAR of the
HD61100A

o

FCS

Controls the SIP conversion.
The operation stops when E is high. and the SIP
conversion starts when E is low.

Input
terminal E"
of the
HD61100A

Used for cascade connection with the HD611 OOA to
increase the number of bits which canbe SIP converted.

GND

Input terminal for test.
Connect to GND.

Operation of the HD61100A
The following describes an LCD panel with 64 x
240 dots on which characters are displayed with
1/64 duty cycle dynamic drive. Figure 1 is an

example of liquid crystal display and connection to
HD61100A's. Figure 2 is a time chart of
HD61100A I/O signals.

HITACHI

181

HD61100A

COM 1
COM2
COM3

-

-

1,
1

1,
2

1,
80

1,
81

1,
82

2,
1

2,
2

2,
80

2,
81

2,
82

3,
1

3,
2

3,
80

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

------

----

I
I
I

1,
160

1,
161

2,
160

2,
161

I
I
I

1,
240

I
I
I

I
I
I

I
I
I

I
I
I

---- t2,- 240
--3,
240
--I
I
I

LCD-PANEL (64 x240 Dots)

COM63
COM64

-

-

I
I
I

I
I
I

I
I
I

I
I
I

63,

63,

1

2

63,
80

64,

64,
2

64,
80

1

I
I
I

I
I
I

Y80

HD61100A (No.1)

:; ~ ..J a:1~

IWWU.::EOOcco

M ...

111

64,
81

64,
82

64,
240

64,
160

Y1

-----

Y2

Y80

Y1

HD61100A (No.2)

:E! ~

:; ~ ..J a: I~

IWWU.::EOOcco

Y80
HD61100A (No.3)

:E! ~

:; ~

CL2

a: I~

1 11
w

1 11
w

11

0

0

00

0..

0..

,...

Cascade three HD611 OOAs. Input data to the terminal DL of No.1, No 2, and
No.3. Connect Eof No.1 to GND. Don't connect any lines to CAR of No.3.
Connect common signal terminals (COM1-COM64) to X1-X64 of common driver
HD61103A. (m.n) in LCD panel is the address corresponding to each dot.

Figure 1 LCD driver with 64 x 240 dots
182

..J

IWWU.::EOOcco

CL1
DATE

t-63,
240

-----

Y2

:E! ~

--------

I
I
I

t--

----Y1

I
I
I

HITACHI

WW
0..0..

i

'

!
I.:
CL1.rt
:
:
~
CL2 L.fut.nn---.J"1IUlIU1Juuu---.n..n.rtrtILh.n---.
M.....J

~

I

I

I

I
I
,
I
I

I
:

DL~'---~---~---~

-

I

CAR(No. 1).J I ECNo. 2)
I
CAR(No. 2).J : ECNo. 3)
I
CAR(No.3)J I
Y1-Y80

:

rr
I

~

I

I
I
I

I

=l

~

:

II

I
I

I!:j

i...

I

Timing
chart
of
horizontal
direction

I
I
I

c:

:

_________________________________________________________ J

~

I

w

J:

~

0

=
...

MJ

CI

CL1
CL2

<=

DL

~

Y1-Y80

...<=
G\

~

:!: s·a·

~

~

L - --- ----II
n
'l----- J1.J1MJUUUl --- llUlJlJ1JUUU1. --- J1JUUUUU1. ----- 1I1JUlh.
I

~-----~----- ~--- ~--- ~-----IIIII:

=¥
I

*
I

c=: ---

I

:•

1:1"

I
CL1
Y1(No. 1) ~

Y2(No. 1)

~

II

-~8O~.1~.,~.1~12~.1~~~,...,.,...'V"""'V'~80

1

12

;l

I

Y80(No.1)~
I

1

I

Y80(NO.3)~

I

t::

x

::=J[.

_______________ J I

~

r
I

I

I

I

I

I

I

:::x::xx:x:x::x
------ :::x::xx:x:x::x
:::x::xx:x:x::x
:::x::xx:x:x::x

I
I

Timing chart for the example of connection in figure 1.
DL input (m, n) is the data that corresponds to each address (m. n) of LCD panel.
~

Timing
chart
of
vertical
direction

• ~-------------------

1 Frame

M~

n

-

~

~

.fUUL -----1ll1MfUU1.
I

CIQ

•...

11

I

:

Timing
chart
of
liquid
crystal
display
driver
output

8en
~
~

o
o

)-

HD61100A
Application Examples
An Example of 128 x 240 Dot Liquid Crystal Display (1/64 Duty Cycle)

/r---------

Yl-Y80

240 dots

\.

Yl-YSO

Yl-YSO

HD61100A No.1

HD61100A No.2

HD61100A No.3

....Iff) -~
III:
,wiJifl::EUoiS2i<3

IWff)fl::EOOOOO

,J,,J,,J,
DATE (1)

r

~ff)

::::;~....III:I~

' ,J,,J,

t

~ff)

::::; ~....III:I~

' ,J,,J,

t

I

IWff)~::EOOOOO

M
Cll
Cl2
DATE (2)

fff

IW ff)1L
~ l1 ::E

1 .ffl1

d~ is 2i1~0

1

o

IW ....I ::E - N ....I 11:111:
iJilL UU 0<3

ff

IW....I l1 ::E iJilL

....I
uuoo
o
N

II:I~

HD61100A No.4

HD61100A No.5

HD61100A No.6

YSO-Yl

Y80-Yl

YSO-Yl

Figure 3 128 x 240 Dot Liquid Crystal Display
The liquid crystal panel (figure 3) is divided into
upper and lower parts. These two parts are driven
separately. HD61100As No. I to No.3 drive the
upper half. Serial data, which are input from the
DATA(I) terminal, appear at YI -+ Yz -+ -- Yso
terminal of No. I, then at YI -+ Yz -+ -- Yso of
No.2 and then at Yl -+ Yz -+ -- Yso of No. 3 in
the order in which they were input (in the case of
SIR. = low). HD61100As No.4 to No.6 drive the

184

lower half. Serial data, which are input from the
DATA(2) tetminal, appear at Y80 -+ Y79 -+ -- Y1
of No.4, then at Y80 -+ Y79 -+ -- Y1 of No. 5 and
then Y80 -+ Y79 -+ -- Y1 of No. 6 in the order in
which they were input (in the case of SIR. = high).
As shown in this example, PC board for display
divided into upper and lower half can be easily
designed by using SIR. terminal effectively.

HITACHI

HD61100A
Example of 64 x 150 Dot Liquid Crystal Display (1/64 Duty Cycle, SHL = Low)
150 dots

Liquid crystal display panel

1 _ _ _ _ Y801

Y1

HD61100A No.1

1

64 dots

J

Y1 _____ Y70
HD61100A No.2

Figure 4 64 x 150 Dot Liquid Crystal Display
4-bit parallel process is used in this LSI to lessen the power dissipation.
Thus, the sum of the dots in horizontal direction should be multiple of 4.
If not, as this example (figure 4), consideration is needed for input signals (figure 5).

CL1
DATE

--.Il_____~------. . .n. . .--~

r.

-------Effeclive data-------f°IDUmmy f--data
I

Figure 5

Input Dots, 150 Horizontal Dots

As the sum of dots in lateral direction is ISO, 2 more dummy data bits are transferred (152 = 4 x 38).
Dummy data, which is output from Y71 and Y72 of No.2, can be either 0 or 1 because these terminals do
not connect with the liquid crystal display panel.

HITACHI

185

HD61200------'(LCD'Driver with SO-Channel Outputs)
Descri ption

Features

The HD61200 is a column driver LSI for a largearea dot matrix LCD. It employs 1/32 or more duty
cycle multiplexing method. It receives serial
display data from a micro controller or a display
contrql LSI, HD61830, etc., and generates liquid
crystal driving signals.

Ordering Information
Type No.

Package

HD61200

100-pin plastic QFP(FP-1 00)

Liquid crystal display driver with serial/parallel
conversion function
Internal liquid crystal display driver: 80 drivers
Drives liquid crystal panels with 1/32-1/128
duty cycle multiplexing
Can interface to LCD controllers, HD61830
andHD61830B
Data transfer rate: 2.5 MHz max
Power supply: Vee: 5 V ± 10% (Internal
logic)
Power supply voltage for liquid crystal display
drive: 8 V to 17 V
CMOS process

Absolute Maximum Ratings
Item

Symbol

Value

Unit

Note

Supply voltage (1)

Vee

-0.3 to +7.0

V

2

Supply voltage (2)

Vee

Vee - 19.0 to Vee + 0.3

V

Terminal voltage (1)

Vn

-0.3 to Vee + 0.3

V

2,3

4

Terminal voltage (2)

VT2

Vee - 0.3 to Vee + 0.3

V

Operating temperature

Topr

-20 to +75

°C

Storage temperature

Tstg

-55 to +125

°C

Notes: 1.

2.
3.
4.

186

LSls may be permanently destroyed if being used beyond the absolute maximum ratings. In
ordinary operation, it is desirable to use them within the limits of electrical characteristics,
because using them beyond these conditions may cause malfunction and poor reliability.
All voltage values are referenced to GND =0 V.
Applies to input terminals, FCS, SHL, CL1, CL2, DL, DR, E, and M.
Applies to V1L, V1R, V2L, V2R , V3L, V3R , V4L, and V4R. Must maintain
Vee?! V1L - V1R?! V3L = V3R?! V4L = V4R?! V2L = V2R?! Vee·
Connect a protection resistor of 15 n ± 10% to each terminal in series.

HITACHI

HD61200
Pin Arrangement

(Top View)

HITACHI

187

HD61200
Electrical Characteristics
DC Characteristics
(Vee = S V ± 10%, GND

= 0 V,

Vee - VEE

=8 V

Typ

to 17 V, Ta

Item

Symbol

Min

Max

Unit

Input high voltage

VIH

0.7xVCC

Vrx

V

Input low voltage

VIL

0

0.3 x
Vee

V

Output high voltage

VctI

Vee ~.4

Output low voltage

Va.

0.4

V

Driver on resistance

Ra-l

7.5

kO

Input leakage current

IJA
IJA

V

IlL 1

-1

1

Input leakage current

IIL2

-2

2

Dissipation current (1)

IGNO

1.0

Dissipation current (2)

lEE

0.1

Notes:

1.
2.
3.
4.

5.

= -20 to 7S°C)
Te.t Condition

Note

IoH -4001JA
lot. .4001JA

2

Load current 1001JA

5

VIN .. Otc Vex;
VIN .. VEE to Vex;

rnA
rnA

3
4
4

Applies to CL1. CL2. SHL. E. M. DL. and DR.
Applies to CAR.
Applies to V1l. V1R. V2l. V2R. V3l. V3R. V4l. and V4R.
Specified when display data is transferred under following conditions:
CL2 frequency fep2" 2.5 MHz (data transfer rate)
CL 1 frequency fep1 - 4.48 kHz (data latch frequency)
M frequency fM" 35 Hz (frame frequencyl2)
Specified at VIH" Vee (V). Vil" 0 V and load on outputs.
IGNo: currents between Vee and GND.
lEE: currents between Vee and VEE.
Resistance between terminal Yand terminal V (one of V1l. V1R. V2l. V2R. V3l. V3R. V4l. and
V4R when load current flows through one of the terminals Y1 to Y80. This value is specified
under the following condition:
Vee - VEE -17 V
V1l .. V1R, V3l .. V3R .. Vee -217 (Vce- VEE)
V2l .. V2R, V4l .. V4R .. VEE +217 (Vee- VEE)

V1L. V1R
V3L. ~R
V4L. V4R

-----0
-----0
-----0

~L.~R

188

2

HITACHI

RON

.---0 Terminal
Y
(Y1-Y80)

HD61200
The following here is a description of the range of power supply voltage for liquid crystal display drivers.
Apply positive voltage to VIL = VIR and V3L = V3R and negative voltage to V2L = V2R and V4L = V4R
within the L1V range. This range allows stable impedance on driver output (RON). Notice the L1V depends
on power supply voltage Vee-VEE.
---,..--_ _ _ _ _ _ _ _ Vee
-------- V1 (V1 L = V1 R )

IN

---- V3 (V3L

Range of Power Supply
Voltage for Liquid Crystal
Display Drive

= V3R )
~

~

5.5 ------------------------

>

A
01
to
05
ROMS

5

OSC1
OSC2

2

NC

3

o 0
o 1
0 0 1
1 0
1 0
o 1 1
1 1
1 0 0
1 0 0
101
1 0

1
1

"jtt

1
1
0
1

1 1

0

Clock signal for external character generator (dynamic ROM
etc.) if necessary
Dot data inputs from external character generator
1 (High): On
o (Low): Off
Select internal or external ROM
High: External ROM
Low: Internal ROM

(I)
(0)

Oscillator

ROM

GND orVcc

5 x 7 + Cursor: Rf = 200 kO (typ)
5 x 11 + Cursor: Rf = 130 kO (typ)

Don't connect any signal to these terminals

HITACHI

203

HD43160AH
Character Dot Patterns
5X7
The bottom lines of the English small characters "g, i, p, q, y," are on the cursor line (Figure
1).

5 X 11

Only the English small character "g, j, p, q, y,"
are displayed as below. The others are the
same as for 5 x 7 (Figure 2).

Cursor 5 dots: .....
Idot: •
The CUIsor is displayed on the 8th or 12th line.

3

Character code lower 4 bits (hexadecimal)
4
5
6
7
8
9
A

a •• .-:. :a •• ••
_. I.• ,I :t: + , - • ••.'
• l·.·
$
4+
•••
•
,. ••.) .••
..,
.."
..::;a
c·
•
•
...
30 1 .-;a
,
-=
._1
.J
-:.
• - • •
'-" •
-@t=I B..... [)4 E F 61 H
I .1 ~.'••.. L, r'1 .,~~.. IJ
..,!!
'
:
:
c T IJ 1•..1 I..J•••• 1••I 1 -='
QF!: -'
.:... [ ¥ ]
P
... ·EI 1::1 C I"~ .;;. f· I;' ~-I 1• • ~..•• 1 fal t1 '-I
. .1
8.
...
,t
....
..;..
" t:1 1:;1 t-· .:.
.t. I.J ..... 1.1.1 ..... --I.J z I J • +-•
8.
a r J ... • ::;a
• 7 ·1· ~ ::t: ::at t:a .:1 ::I III
..... t! ':.J
Y ·1·· I :::t :tl 1= .p]... -'I• :J -=J ..,
.~
.. f•• IIJ• T- ~. t - ,va. ~ ..I 1·1 t: ..•••. ;t;.... a-:,•
- I I ILl []
·0

2

1

2

I

II

B

C

0

-

w·

E

F

~

'i4

-

'~J

'"0

~ 5

:S

.!!!

~ 6

f---

CL

., 7

I•

, .,

.,

~

CIl

~A

m
.J:.
U

B-

C

o _

..1

-. '-I ••••

t 1-' .1 3 ..,
Figure 1

••

5 X 7 Characters

•

13 .J Pq !:I
Figure 2
204

L." IJ

Special 5 X 11 Characters

HITACHI

-

.1

HD43160AH
Application
Setting Up
1.
2.
3.
4.

Total character number: CNO-CN2
Cursor pattern: CURS
DiSplay line number: DLN
Font: FNTS

These terminals should be connected to Vcc
or GND according to the LCD display system.
RST and TEST should be connected to Vcc
and GND respectively.

Interface to the Controller
1. Example 1 Interface to HD6800
In this example (Figure 3). the addresses of
HD43160AH in the address area of the
HD6800 microcomputer are:
Instruction code register
#'E .. ••
(R/W=O)
#·F····
(R/W=O)
Character code register
#'E· .. • or #·F*··· (R/W=1)
Busy flag
.: don't care
#": hexadecimal

HOIIOO (MPU)

AB15

eS3

AB14
AB13
VMA

eS2
eSl
eso

AB12

RSO

R/W

R/W
E

~2

DBO

DBO

DBl

DBl
DB2

DB2
DB3

DB3

DB4

DB4

DB5
DB6

DB5
DB6

DB7

DB7

Figure 3

H048180AH

HD6800 Interface

HITACHI

205

HD43160AH
2. Example of display program

Read Busy flag
from :II: ·E· .. •
or # 'F····
Check Busy or Ready

Figure 4

Display Program Example

3. Time length of Busy
write Inst. or Charact. code

E

_Sl~_ __

Busy
(Internal)

-FT~.Y -----;l~L-.-d
Operation start

operation en

T busy
min

400

Display clear

1;-

Other function

1;-

10

Max

Unit

410

s

1;20

Figure 5
HD43160AH begins the operation from the
rising edge of E (Figure 5).
Instruction code register and character code
206

s

1;-

Busy timing
register iatch the data on DBO-DB7 at the
falling edge of E.

HITACHI

HD43160AH
4. Timing chart

Read sequence

Write sequence
(MPU--HD43160AH)
tCYC

11

1-

--I

PWEH

PWEl

(MPU+--HD43160AH)

01 '

tCYC

I

--I

I.

tAS

CSO
to

CS3
RSO

l

to

CS3
RSO

I
I

r

Write

1

CSO

----+------J[

I

-I
I

..

litH

II

---t--J
I

R/W

Itoowl

°1'''1

P WEH

E

1'-1--1

:.

01_

I

-/~L

E

PWEl

Read

I

DBO

DBl

to

DBl

Figure 6

~
~

HD6800 Interface Timing

5. Timing characteristics
Item

Symbol

Min

Cycle time of E

teye

1.0
0.45
0.45
140

Pulse width of E

High level

F\vEH

Low level

F\vEL

Set up time of CS

Write

tAS

Data delay time

Write

toow

Read

tOOR

Hold time

tH

Typ

Max

Unit
ps

25

ps
ps
ns

225
300
10

HITACHI

ns
ns
ns

207

HD43160AH
6. Example 2 Interface to 8085A (Intel)

Sl

R/W
CS3

loiM
RD
WR
A15
A14
A13
A12
8085A

-

]'

E
CS2
CS1
CSO
RSO

~D

(MPU)

ALE
ClK
READY
ADO

{::::n- ClK
ClR
..... .,.,.

...

o

r

HD43160AH

a

0lJ:D
ClK

°1

1

DBO

to

to

DB7

AD7

Figure 7

8085A Interface

7. Timing chart

I

I

ClK

I

I

'--

101M, Sl
A12A15
f--

ALE

-

\

,

READY

I
~

"---

\
T1

T2

Figure 8
Pulse widths of RD and WR signals of the
8085A are 400 ns min, while the pulse width
of the E signal of the HD43160AH is 450 ns

208

TWAIT

\

T4

8085A Timing
min (Figure 8).
Therefore, in this example, RD and WR signal
pulse widths are widened by the TWAIT cycle.

HITACHI

HD43160AH
Display Commands
Display Control Instructions
These instructions should be written into the
instruction register of HD43160AH by the
microcomputer. (RSO = Low, R/W = Low)
1. Display clear

Code:

MSB

LSB

I0 I0 I0 I0 I0 I0 I0

11

I

Operation: The screen is cleared and the
cursor returns to the 1st digit.

2. Cursor return

Display Character Command

MSB
Code:

Operation: The cursor moves to the Nth
(nth, mth) digit.
N ~ the total character number
n, m ~ 1/2 total character
number
ex 1: 1 line
Set the cursor at digit 55. The
code is 10110110.
ex 2: 2 lines
Set the cursor at digit 35 of
upper or lower line.
The code is 10100010 (upper).
11100010 (lower).

LSB

I0 I0 I0 I0 I0 I0

11

I0 I

Operation: The cursor returns to the 1st
digit and the characters being
displayed do not change.

When the character code is written into the
character register of HD43160AH, the character with thiscode appears where the cursor
wasdisplayed and the cursor moves to the
next digit. (RSO = High, R/W = Low)
MSB

code:
3. Cursor on/off

I

LSB
(Character code)

ex. 1
MSB
Code:

LSB

before

0

0

0

0

0

1

0

0

On)

0

0

0

0

0

1

0

1

Off)

after

A_B_C_D~~_--,

LI

I ABCDE

Read Busy Flag
Operation: The cursor appears (on) or disappears (off).
4. Set cursor position
MSB
Code: 1 line

LSB

1

(N - 1)

binar~

2 lines upper 1

0 (n - 1)

binar~

lower 1

When CSO-CS3 = High, R/W = High and E
= High (RSO = 'don't care'), the Busy/Ready
signal appears on DB7.
DB 7 High: Busy
Low: Ready

1 m - 1) binar~

N, n, m: digit number

Table 1

Time Length of Busy (oscillation frequency = 200 kHz)

Display clear
Other operations

Min
2.0
50

Max
2.05
100

Unit
ms
ps

(depends on the operating frequency)

HITACHI

209

HD43160AH
Interface to External ROM
1. Example

LSB XO
Xl
X2
Character
X3
code
X4
X5
HD43160AIX6
MSBX7
LSB YO
Row
Yl
code
Y2
MSBY3

M
01
02
03
04
05
ROMS

Address
ROMS
1: Ext.
0: Int.

External
ROM

is used as the
precharge signal for
dynamic ROM if nec-

.~A

------ *

]-

Figure 9

essary.

Interface to Extemal ROM

2. Row code
Row code
0102030405 Y3

Y2

Yl

YO

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
0
0

1
0
0

Row code
0102030405

Y3 Y2 Yl YO
0

0

0

0

0

0

0

0
0
0
0

0
0

1
0

0
0

0
1
0

0
0

(Cursor)

0
0

5x 11 + Cursor

5x7+ Cursor

Figure 10

210

Row Code

HITACHI

1
0
0

0
1
0
1
0
1
0
0

HD43160AH
3. Timing chart

CL2

t--:-t

1_1_1
1 fep

i

XO-X7
YO-Y3

I

I

1-

-I

r

2

if>A

To;;

I

01-05
ROMS

Effective data

.. I

MAX~
fep

Figure 11

Display Timing

Interface to LCD Drivers
1. Example

Yl-Y40

Vl-V6

SHL1
SHL2

HD44100H

FCS
SHL1
SHL2

HD44100H

Dll

DL2
DR2

CL1

CL2

M

FlM

o

HD43160AH

Cll ~----------~---+--~--------------~--+--+--­
CL2~--------------1-~~----------------+--+---

M~----------------~~-------------------+--

Figure 12

Interface to HD44100H

HITACHI

211

HD43160AH
2. Waveforms (5 x 7

8

+

Cursor 1 line)

2

3

4

5

6

7

8

2

FLM
CLl
M

FlM
Cll

I I I I I I I I I I I

~

-----'~--~_________________________

M

CL2

o
One row of a character
One row of 80 characters (400 dots)

Figure 13

212

Timing

HITACHI

L

HD43160AH
Dot Matrix Liquid Crystal Display
System

Figure 14

Typical Application 5 X 7

+ Cursor, 2 Lines, 40 Characters

HITACHI

213

HD44780U (LCD-II)--(Dot Matrix Liquid Crystal Display
Controller/Driver)
Description
The HD44780U dot-matrix liquid crystal display
controller and driver LSI displays alphanumerics,
Japanese kana characters, and symbols. It can be
configured to drive a dot-matrix liquid crystal
display under the control of a 4- or 8-bit
microprocessor. Since all the functions such as
display RAM, character generator, and liquid
crystal driver, required for driving a dot-matrix
liquid crystal display are internally provided on
one chip, a minimal system can be interfaced with
this controller/driver.

•
•

•

•

A single HD44780U can display up to, one
8-character line or two 8-character lines.
The HD44780U has pin function compatibility
with the HD44780S which allows the user to
easily replace an LCD-IT with an HD44780U. The
HD44780U character generator ROM is extended
to generate 208 5 x 8 dot character fonts and 32
5 x 10 dot character fonts for a total of 240
different character fonts.
The low power supply (2.7 V to 5.5 V) of the
HD44780U is suitable for any portable batterydriven product requiring low power dissipation.

•

•
•
•
•

80 x 8-bit display RAM (80 characters max.)
9,920-bit character generator ROM for a total
of 240 character fonts
- 208 character fonts (5 x 8 dot)
- 32 character fonts (5 x 10 dot)
64 x 8-bit character generator RAM
- 8 character fonts (5 x 8 dot)
- 4 character fonts (5 x 10 dot)
16-common x 40-segment liquid crystal
display driver
Programmable duty cycles
- 1/8 for one line of 5 x 8 dots with cursor
- 1/11 for one line of 5 x 10 dots with cursor
- 1/16 for two lines of 5 x 8 dots with cursor
Wide range of instruction functions:
- Display clear, cursor home, display on/off,
cursor on/off, display character blink,
cursor shift, display shift
Pin function compatibility with HD44780S
Automatic reset circuit that initializes the
controller/driver after power on
Internal oscillator with external resistors
Low power consumption

Ordering Information
Features
• 5 x 8 and 5 x 10 dot matrix possible
• Low power operation support
•

•
•
•

- 2.7 to 5.5 V
Wide range of liquid crystal display driver
power
- 3.0 to 11 V
Liquid crystal drive waveform
- A (One line frequency AC waveform)
Correspond to high Speed MPU bus interface
- 2 MHz (when Vee = 5 V)
4-bit or 8-bit MPU interface enabled

214

Type No.

Package

CGROM

HD44780UAOOFS
HCD44780UAOO
HD44780UAOOTF*
HD44780UA01 FS*
HD44780UA02FS*

FP-80B.
Chip
TFP-80
FP-80B
FP-80B

Japanese
standard font

HD44780UBxxFS
HCD44780UBxx
HD44780UBxxTF

FP-80B
Chip
TFp·80

Custom font

Note:

HITACHI

* Under development

Standard font
for communication, European
standard font

xx: ROM code No.

HD44780U
HD44780U Block Diagram

OSC1 OSC 2

M

Reset
circuit
ACL

r--MPU
interRS RNI- face

E

CL
CL2

I---

I CPG

Instruction
register (IR)

8

llnstruction
decoder

J

~

7

0

~

Display
data RAM
(DO RAM)
80 x 8 bits

.....

16-bit
shift
register

Input!
output
buffer

~

I

Address
counter

Data
register
(DR)

I

7

40-bit
shift
register

8

Common
signal
driver

tt

-

7

-

J

~+

-

DBo to
DB3

Timing
generator

40-bit
latch
circuit

Segment
signal
driver

COM 1 to
COM 16

r--

SEG 1 to
SEG40

r--

' 7

8
40

8

8

r r II
LCD drive
voltage
selector

-G;]
flag

'---

GND

~

Character
generator
RAM
(eG RAM)
64 bytes
5

L--.

Vee

~

Character
generator
ROM
(CGROM)
9,920 bits

Cursor
and
blink
controller

5

Parallel/serial converter
and
t-attribute circuit

~~b~~

HITACHI

215

HD44780U
LCD·H Family Comparison
HD66780

Item

HD44780S

(LCD-IliA)

HD44780U

Power supply voltage

5 V±10%

5V±10%

2.7 to 5.5 V

liquid crystal drive
voltage VleD

1/4 bias

3.0 to 11.0 V

3.0 VtoVee

3.0 to 11.0V

1/5 bias

4.6 to 11.0V

3.0 Vto Vee

3.0 to 11.0V

Maximum display
digits per chip

16 digits
(8 digits x 2 lines)

16 digits
(8 digits x 2 lines)

16 digits
(8 digits x 2 lines)

Display duty cycle

1/8, 1/11, and 1116

1/8, 1111, and 1116

1/8, 1/11, and 1/16

CGROM

7,200 bits
(160 character fonts
for 5 x 7 dot and
32 character fonts
for 5 x 10 dot)

12,000 bits
(240 character fonts
for 5 x 10 dot)

9,920 bits
(208 character fonts for
5x8dotand
32 character fonts for
5x10dot)

CGRAM

64 bytes

64 bytes

64 bytes

DDRAM

80 bytes

80 bytes

80 bytes

Segment signals

40

40

40

Common signals

16

16

16

Liquid crystal drive waveform

A

B

A

Oscillator

Clock source

External resistor,
external ceramic
filter, or external
clock

External resistor,
external ceramic
filter, or external
clock

External resistor or
external clock

RI oscillation
frequency (frame
frequency)

270 kHz±30%
(59 to 110 Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1111
duty cycle)

270kHz±30%
(59 to 110Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1/11
duty cycle)

270 kHz ±30%
(59 to 110 Hz for 1/8
and 1116 duty cycles;
43 to 80 Hz for 1/11
duty cycle)

RI resistance

91 kn±2%

82kn±2%

91 kn±2%
(when Vee - 5 V)
75kn±2%
(when Vee = 3 V)

Instructions

Fully compatible within the HD44780S

CPU bus timing

1 MHz

2 MHz

1 MHz (when Vee • 3 V)
2 MHz (when Vee • 5 V)

Package

FP-80

FP-80B

FP-80B

216

HITACHI

HD44780U
HD44780U Pin Arrangement

•

FP-80B
(top view)

OSC 1 24

HITACHI

217

HD44780U
HD44780U Pad Arrangement

Chip size:

4.90 x 4.90 mm 2

Coordinate: Pad center (IJm)

2

1.

Origin:

Chip center

Pad size:

114 x 114IJm2

63

80

\ I

tJtJ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

..

y

I

HD447~

42

23

X

218

o()'

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Type code
0
0
0
0
0
0
0
0
0
0
)Zl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OQ..

HITACHI

HD44780U
HCD44780U Pad Location Coordinates
Coordinate

Coordinate

Pad No.

Function

X (um)

Y (um)

Pad No.

Function

X (um)

Y (um)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

SEG22

2313
2313
2089
1833
1617
1401
1186
970
755
539
323
108
-108
c..323
-539
-755
-970
-1186
-1401
-1617
-1833
-2073
-2290
-2290
-2290

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67

DB:!
DB,

2070
2260

-2290
-2290

DB4

2290

'-2099

DBs

2290

DBa

2290

-1883
-1667
-1452
-1186
-970
-755
-539
c..323
-108
108
323
539
755
970
1186
1401
1617
1833
2095
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313

V4

-2100
-2280
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2313
-2280
-2080
-1749
-1550
-1268
-941
-523

30
31
32
33

Vs

~04

Cl1

34

M

35
36
37
38
39
40

0

-48
142
309
475
665
832
1022
1204
1454
1684

29

SEG21
SEG20
SEG 19
SEG 1e
SEG17
SEG16
SEG1S
SEG14
SEG13
SEG 12
SEG 11
SEG10
SEGg
SEGe
·SEG7
SEGa
SEG5
SEG4
SEG3
SEG2
SEG 1
GND

esc1
esc2
VI
V2
V3

Cl2
Vee

RS

RiW
E
DBa
OBI

-2290

-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290
-2290"

68

69
70
71
72
73
74
75
76

D~

2290

COM 1

2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2296
2100
1617
1401
1186
970
755
539
323
108
-108
-323
-539
-755
-970
-1186
-1401
-1617

COM2
COM3
CO~

COMs
COMe
COM7
COMe
COM9
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
COM16
SE~
SE~
SE~

SEGs-,
SE~

SE<3:Js
SE~

SEG33
SE~
SE~l
SE~

SE~

SEGa
SEGz,

77

SE~

78
79
80

SE~5

HITACHI

SE~
SE~

219

HD44780U
Pin· Functions
Signal

No. of
Line.

RS

I/O
I

Function

MPU

Selects registers.
0: Instruction register (for write)
Busy flag: address counter (for read)
1: Data register (for write and read)

MPU

Selects read or write.
0: Write
1: Read

I

MPU

Starts data readlwrite

ANI

E

Device
Interfaced wHh

DB4 to DB7

4

110

MPU

Four high order bidirectional tristate data bus
pins. Used for data transfer and receive
between the MPU and the HD44780U.
DB7 can be used as a busy flag.

DBoto DB3

4

I/O

MPU

Four tow order bidirectional tristate data bus
pins. Used for data transfer and receive
between the MPU and the HD44780U. These
pins are not used during 4-bit operation.

Cl1

0

HD441 00

Clock to latch serial data D sent to the
HD44100 driver

Cl2

0

HD441 00

Clock to shift serial data D

M

0

HD441 00

Switch signal for converting the liquid crystal
drive waveform to AC

D

0

HD44100

Character pattern data corresponding to each
segment signal

COM1 to COM 16

16

0

LCD

Common signals that are not used are
changed to non-selection waveforms. COMg
to COM 16 are non-selection waveforms at 118
duty faclor and COM 12 to COM 16 are nonselection waveforms at 1/11 duty factor.

SEG 1 to SEG40

40

()

LCD

Segment signals

V1 to Vs

5

Power supply

Power supply for LCD drive
Vee -Vs = 11 V (max)

Vee,GND

2

Power supply

Vee: 2.7 V to 5.5 V, GND: 0 V

OSC1.OSC2

2

Oscillation
resistor
clock

When crystal oscillation is performed. a
resistor must be connected externally. When
the pin input is an external clock, it must be
input to OSC1•

220

HITACHI

HD44780U
Function Description
Registers

Busy Flag (BF)

The HD44780U has two 8-bit registers, an
instruction register (IR) and a data register (DR).

When the busy flag is I, the HD44780U is in the
internal operation mode, and the next instruction
.will not be accepted. When RS =0 and R/W = 1
(table I), the busy flag is oulput to DB7. The next
instruction must be written after ensuring that the
busy flag is O.

The IR stores instruction codes, such as display
clear and cursor shift. and address information for
display data RAM (DD RAM) and character
generator RAM (00 RAM). The IR can only be
written from the MPU.
The DR temporarily stores data to be written into
DD RAM or CO RAM and temporarily stores data
to be read from DD RAM or CO RAM. Data
written into the DR from the MPU is automatically
written into DD RAM or CO RAM by an internal
operation. The DR is also used for data stomge
when reading data from DD RAM or CO RAM.
When address information is written into the IR,
data is read and then stored into the DR from DD
RAM or 00 RAM by an internal operation. Data
tmnsfer between the MPU is then completed when
the MPU reads the DR. Mter the read, data in DD
RAM or CO RAM at the next address is sent to
the DR for the next read from the MPU. By the
register selector (RS) signal, these two registers
can be selected (table 1).

Address Counter (AC)

The address counter (AC) assigns addresses to
both DD RAM and CO RAM. When an address
of an instruction is written into the IR, the address
information is sent from the IR to the AC.
Selection of either DD RAM or CO RAM is also
determined concurrently by the instruction.
Mter writing into (reading from) DD RAM or CO
RAM, the AC is automatically incremented by 1
(decremented by 1). The AC contents are then
oulput to DBo to DB6 when RS = 0 and R/W = 1
(table 1).

Table 1 Register Selection
Operation

RS

o
o

o

IR write as an internal operation (display clear, etc.)
Read busy flag (OB7 ) and address counter (OBo to OBs)

o

DR write as an internal operation (DR to DO RAM or CG RAM)
DR read as an internal operation (DO RAM or CG RAM to DR)

HITACHI

221

HD44780U
Display Data RAM (DD RAM)

-

Display data RAM (DD RAM) stores display data
represented in 8-bit character codes. Its extended
capacity is 80 x 8 bits. or 80 characters. The area
in display data RAM (DD RAM) that is not used
for display can be used as general data RAM. See
figure I for the relationships between DD RAM
addresses and positions on the liquid crystal
display.

When the display shift operation is
performed. the DD RAM address shifts.
See figure 4.
-

The DD RAM address (ADO> is set in the address
counter (AC) as hexadecimal.
•

Case 2: For a 16-character display. the
HD44780 can be extended using one
HD44100 and displayed. See figure 4.

Case 3: The relationship between the
display position and DD RAM address
when the number of display digits is
- increased through the use of two or more
HD44100s can be considered as an
extension of case #2.

I-line display (N = 0) (figure 2)
-

Since the increase can be eight digits per
additional HD44100. up to 80 digits can be
displayed by externally connecting nine
HD44100s. See figure 5.

Case 1: When there are fewer than 80
display characters. the display begins at the
head position. For example. if using only
the HD44780. 8 characters are displayed.
See figure 3.
When the display shift operation is
performed. the DD RAM address shifts.
See figUre 3.

High order

~ bits

.. I..

Low order
bits ----I

~~XadeCimal) IAc6~C5~c4IAC3IAc2IAc1IAc~

Example: DD RAM address 4E

1 10 10 1 1 1 1 0 1

Figure I DD RAM Address

Display position
(digit)

~:~

2

3

4

5

80

100 101 1021 031 041· . . . . . . . . . . . . . . ... 14E 14F 1

(hexadecimal)

Figure 2 I-Line Display

222

79

HITACHI

HD44780U
Display
postt~n

1

2

3

4

5

6

7

8

~~:~ 1001011021031041051061071
~~~Ieft

10110210310410510610710s1

~~~ right 14F I 00 I 01 I 021 031 041 osl Os I
Figure 3 I-Line by S-Character Display Example
Display
posttion

1

2

3

4 5 6

7

8 9 10 11 12 13 14 15 16

~~~: loolollo2Io3Io4Iosl06lo7108lo9Io4°'9°90EIOFI
,

y

Y

1\

HD447S0 display

I

HD441 00 display

For
shift left

Figure 4 I-Line by 16-Character Display Example

Display
position

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1& 17 18 19 20

73 74 75 76 77 78 79 60

~:~ loolollo3D304I03oaloj08HD3o+9o!f30310HI2H

E~+++f~4+3

'----y-----J'----y-----J'--_--..,yr-_____.J'----y-----J
HD44780 display

1st HD44100
display

2nd to 8th HD44100
display

9th HD44100
display

Figure 5 I-Line by SO-Character Display Example

HITACHI

223

HD44780U
2-line display (N = 1) (figure 6)

consecutive. For example. when just the
HD44780 is used. 8 characters x 2 lines are
displayed. See figure 7.

Case 1: When the number of display
characters is less than 40 x 2 lines, the two
lines are displayed from the head. Note
that the first line end address and the
second line start address are not

Display
pOSition

2

DDRAM
address
(hexadecimal)

3

4

When display shift operation is performed.
the DD RAM address shifts. See figure 7.

5

Figure 6 2-Line Display

Display
position
DDRAM
address

For
shift left

2345678

00 01 02 03 04 05 06 07
40 41 42 43 44 45 46 47

01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48

27 00 01 02 03 04 05 06
For
shift right

67 40 41 42 43 44 45 46

Figure 7 2·Line by 8·Character Display Example

224

39

40

00 01 02 03 04 .................. 26 27
40 41 42 43 44 .................. 66 67

HITACHI

HD44780U
-

Case 2: For a 16-character x 2-line display,
the HD44780 can be extended using one
HD44100. See figure 8.

when the number of display digits is
increased by using one HD44780U and
two or more HD44100s, can be considered
as an extension of case #2. See figure 9.

When display shift operation is performed,
the DD RAM address shifts. See figure 8.
-

Since the increase can be 8 digits x 2 lines
for each additional HD44100, up to
40 digits x 2 lines can be displayed by
externally connecting four HD44100s.

Case 3: The relationship between the
display position and DD RAM address

Display
position

1

2

3

4

5

6

7

8

9 10 11 1213 14 15 16

DDRAM 00 01 0203 04 0506 0708 090A OE OC OC OE OF
address
4041 4243 44 4546 4748 494A 4E 4C 4C 4E 4F

\

V

/'~----~y~-----)

HD44780U display

For
shift left

010~

HD44100 display

0304 0506 0708 090Jl OE OC OC OE OF10

4142 4344 4546 4748 494A 4B~C 4D 4E 4F 50

2700 0102 0304 0506 0708 09 OJi 08
For
shift right

pC OD OE

6740 4142 4344 4546 4748 49 4J148 4C 4D 4E

Figure 8 2-Line by 16-Character Display Example

Display
position

1 2 3 4 5 8 7 8 9 1011 121314151617181920

DDRAM 0001 020 04105 060 0809 0101 joe O[ 01 OF 1011 1213
address
4041 243 44145 4647 4849 4141 ~e~[ 414F 5051 5253

33 34 35 36 37 38 39 40

........

2021 ~2 23 242! 262

........

60 61 6263 64 65 666

'-----y------I'-----y------I....
HD44780U display

1st HD441 00
display

y
--"'-----y------I
2nd and 3rd HD44100
4th HD44100
display
display

Figure 9 2-Line by 4O-Character Display Example

HITACHI

225

HD44780U
Character Generator ROM (CG ROM)

Modirying Character Patterns

The character genemtor ROM genemtes 5 x 8 dot
or 5 x 10 dot character patterns from 8-bit
character codes (table 4). It can generate
208 5 x 8 dot chamcter patterns and 32 5 x 10 dot
chamcter patterns. User-defined chamcter patterns
are also available by mask-programmed ROM.

•

Character Generator RAM (CG RAM)
In the character genemtor RAM, the user can
rewrite chamcter patterns by progmm. For 5 x 8
dots, eight character patterns can be written, and
for 5 x 10 dots, four character patterns can be
written.
Write into DD RAM the character codes at the
addresses shown as the left column of table 4 to
show the chamcter patterns stored in CG RAM.
See table 5 for the relationship between CG RAM
addresses and data and display patterns.
Areas that are not used for display can be used as
geneml data RAM.

226

Chamcter pattern development procedure

The following operations correspond to the
numbers listed in figure 10:
1. Determine the correspondence between
character codes and chamcter patterns.

2. Create a listing indicating the correspondence
between EPROM addresses and data.
3. Program the character patterns into the
EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing on the EPROM is
performed at Hitachi to create a character
pattern listing, which is sent to the user.
6. If there are no problems within the chamcter
pattern listing, a trial LSI is created at Hitachi
and samples are sent to the user for evaluation.
When it is confirmed by the user that the
chamcter patterns are correctly written, mass
production of the LSI proceeds at Hitachi.

HITACHI

HD44780U

User

Hitachi

Determine
character patterns

®

 t·~ .- -. t-. .-.- ~.I ..--. rn.: ~.:I. ..I f- 1 1·••
... ... . rl .-1 0 :.--1- .. F: ....

~4
4Bh
BIts 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
xxxxoooo

CG
RAM

xxxxOO01

(2)

xxxx0010

(3)

xxxx0011

(4)

xxxx0100

(5)

xxxx0101

(6)

xxxx0110

(7)

xxxx0111

(8)

xxxx1000

(1 )

xxxx1001

(2)

xxxx1010

(3)

xxxx1011

(4)

xxxx1100

(5)

xxxx1101

(6)

xxxx1110

(7)

xxxx1111

(8)

(1)

I

;11

"

232

...
...

•

I

";

.-. .-.
.-.
'."

••••
I-:~

.

•••••

.J"

•

-.

fl

HITACHI

•• r

1

.

HD44780U
Table 5 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character
Patterns (CG RAM data)
For 5 x 8 dot character patterns

Character Codes
(DO RAM data)

7 6 5 4 3 2
High

o

0 0 0

o
Low

*

CG RAM Address

Character Patterns
(CG RAM data)

543 2 1 0

7 6 5 4 3 2 1 0

High

Low

High

Low

Character
pattern (1)

000

Cursor position

o

0 0 0 * 0 0 1

o

Character
pattern (2)

0 1

Cursor position

o

0 00* 1 1 1

1 1 1

Notes: 1. Character code bits 0 to 2 correspond to CG RAM address bits 3 to 5 (3 bits: s types).
2. CG RAM address bits 0 to 2 designate the character pattern line position. The Sth line is the
cursor position and its display is forrned by a logical OR with the cursor.
Maintain the Sth line data, corresponding to the cursor display position, at 0 as the cursor display.
If the Sth line data is 1, 1 bits will light up the Sth line regardless of the cursor presence.
3. Character pattern row positions correspond to CG RAM data bits 0 to 4 (bit 4 being at the left ).
4. As shown table 5, CG RAM character patterns are selected when character code bits 4 to 7
are all O. However, since character code bit 3 has no effect, the R display example above
can be selected by either character code OOH or OSH.
5. 1 for CG RAM data corresponds to display selection and 0 to non-selection.
• Indicates no effect.

HITACHI

233

HD44780U
Table 5 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character
Patterns (CG RAM data) (cont)
For 5 x 10 dot character patterns

Character Codes
(DO RAM data)

7 6 5 4 3 2
High

0
Low

CG RAM Address

Character Patterns
(CG RAM data)

5 4 3 2 1 0

7 6 5 4 3 2 1 0

High
:0 0
0
0
0
1

:0

lo
10

o

0 0 0 •

00·

High

Low

:0
:0
:0

0 0:0

Character
pattern

,: 1 0 0 0
,: 1 0 0

0 0 0 0 0
• . • -----------.. .. .. .. .. • • ..

0 1 0
------r,:1,--6--,--;:1

0 0

:1
:1

0 1
0

Low

.. .. ..

0 0
0
0
1 1
0 0
0
0

Cursor position

I I

.. .. • .. .. . . .

:1

,,

o

0 0 0 •

1 1 •

1 1

i1

------r,, --C--, --i
:1

0

1 0

:1

0 0
0 1

:1
:1

0

i1

* • * -r------- --- ----------.**:*****
I

,,
,,

I I
,,,

* " '" * * * * '"
I

Notes: 1. Character code bits 1 and 2 correspond to CG RAM address bits 4 and 5 (2 bits: 4 types).
2. CG RAM address bits 0 to 3 designate the character pattern line position. The 11th line is
the cursor position and its display is formed by a logical OR with the cursor.
Maintain the 11 th line data corresponding to the cursor display positon at 0 as the cursor display.
If the 11th line data is "1", "1" bits will light up the 11 th line regardless of the cursor presence.
Since lines 12 to 16 are not used for display, they can be used for general data RAM.
3. Character pattern row positions are the same as 5 x S dot character pattern positions.
4. CG RAM character patterns are selected when character code bits 4 to 7 are all O.
However, since character code bits 0 and 3 have no effect, the P display example above
can be selected by character codes OOH, 01H, OSH, and 09H.
5. 1 for CG RAM data corresponds to display selection and 0 to non-selection.
.. Indicates no effect.

234

HITACHI

HD44780U
arrived. The latched data then enables the driver
to generate drive waveform outputs. The serial
data can be sent to externally cascaded HD44100s
used for displaying extended digit numbers.

Timing Generation Circuit
The timing generation circuit generates timing
signals for the operation of internal circuits such as
DD RAM, CG ROM and CG RAM. RAM read
timing for display and internal operation timing by
MPU access are generated separately to avoid
interfering with each other. Therefore, when
writing data to DD RAM, for example, there will
be no undesirable interferences, such as flickering,
in areas other than the display area. This circuit
also generates timing signals for the operation of
the externally connected HD44100 driver.

Sending serial data always starts at the display
data character pattern corresponding to the last
address of the display data RAM (DD RAM).
Since serial data is latched when the display data
character pattern corresponding to the starting
address enters the internal shift register, the
HD447S0U drives from the head display. The rest
of the display, corresponding to latter addresses,
are added with each additional HD44100.

Liquid Crystal Display Driver Circuit

Cursor/Blink Control Circuit

The liquid crystal display driver circuit consists of
16 common signal drivers and 40 segment signal
drivers. When the character font and number of
lines are selected by a program, the required
common signal drivers automatically output drive
waveforms, while the other common signal drivers
continue to output non-selection waveforms.

The cursor/blink control circuit generates
cursor or character blinking. The cursor or
blinking will appear with the digit located at
display data RAM (DD RAM) address set in
address counter (AC).

the
the
the
the

For example (figure 11), when the address counter
is OSH, the cursor position is displayed at DD
RAM address OSH.

The segment signal driver has essentially the same
configuration as the HD44100 driver. Character
pattern data is sent serially through a 40-bit shift
register and latched when all needed data has

AC6 AC5 AC4 AC3 AC2 AC1 ACO
AC

0

0

1

0

0

0

0

5

6

7

04

05

I
For a 1-line display
Display position
DD RAM address
(hexadecimal)

{

00

2

3

01

02

I

4
I 03 I

8

9

10

11

07 10810910AI
I 06 I

f

~

cu rsor position

For a 2-line display
2

3

4

5

6

7

8

9

10

11

00

01

02

03

04

05

06

07

~

09

OA

40

41

42

43

44

45

46

47

\48

49

4A

Display position
DD RAM address {
(hexadecimal)

I
/

cursor position
Note:

* The cursor or blinking appears when the address counter (AC) selects the character
generator RAM (CG RAM). However. the cursor and blinking become meaningless.
The cursor or blinking is displayed in the meaningless position when the AC is a CG RAM address.

Figure 11 Cursor/Blink Display Example

HITACHI

235

HD44780U
Interfacing to the MPU

Reset Function

The HD44780U can send data in either two 4-bit
operations or one 8-bit operation, thus allowing
interfacing with 4- or 8-bit MPUs.

Initializing by Internal Reset Circuit

•

For 4-bit interface data, only four bus lines
(DB4 to DB7) are used for transfer. Bus lines
DBo to DB3 are disabled. The data transfer
between the HD44780U and the MPU is
completed after the 4-bit data has been
transferred twice. As for tlte order of data
transfer, the four high order bits (for 8-bit
operation, DB4 to DB7) are transferred before
the four low order bits (for 8-bit operation,
DBOto DB3).
The busy flag must be checked (one
instruction) after the 4-bit data has been
transferred twice. Two more 4-bit operations
then transfer the busy flag and address counter
data.

•

For 8-bit interface data, all eight bus lines
(DBo to DB7) are used.

An internal reset circuit automatically initializes
the HD44780U when the power is turned on. The
following instructions are executed during the
initialization. The busy flag (BF) is kept in the
busy state until the initialization ends (BF = 1).
Tlte busy state lasts for 10 ms after Vcc rises to
4.5V.
1. Display clear

2. Function set:
DL =1; 8-bit interface data
N = 0; I-line display
F = 0; 5 x 8 dot character font

3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
lID = 1; Increment by 1
S =0; No sltift
Note: If tlte electrical characteristics conditions
listed under the table Power Supply
Conditions Using Internal Reset Circuit are
not met, the internal reset circuit will not
operate normally and will fail to initialize
the HD44780U. For such a case, initialization must be performed by the MPU as
explained in the section, Initializing by
Instruction.

______________________

~I

RS

RIW
E

D~

DB.

Instruction register (IR)

wrhe

Busy flag (BF) and
address counter (AC)

Data register (DR)

read

read

Figure 12 4·Bit Transfer Example

236

HITACHI

HD44780U
Instructions
Outline

Only the instruction register (IR) and the data
register (DR) of the HD44780U can be controlled
by the MPU. Before starting the internal operation
of the HD44780U, control information is
temporarily stored into these registers to allow
interfacing with various MPUs, which operate at
different speeds, or various peripheral control
devices. The internal operation of the HD44780U
is determined by signals sent from the MPU.
These signals, which include register selection
signal (RS), read/write signal (R/W), and the data
bus (DBo to DB?), make up the HD44780U
instructions (table 6). There are four categories of
instructions that:
Designate HD44780U functions, such as
display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Perform miscellaneous functions
Normally, instructions that perform data transfer
with internal RAM are used the most. However,

auto-incrementation by I (or auto-decrementation
by I) of internal HD44780U RAM addresses after
each data write can lighten the program load of the
MPU. Since the display shift instruction (table 11)
can perform concurrently with display data write,
the user can minimize system development time
with maximum programming efficiency.
When an instruction is being executed for internal
operation, no instruction other than the busy
flag/address read instruction can be executed.
Because the busy flag is set to 1 while an
instruction is being executed, check it to make
sure it is 0 before sending another instruction from
theMPU.
Note: Be sure the HD44780U is not in the busy
state (BF = 0) before sending an instruction
from the MPU to the HD44780U. If an
instruction is sent without checking the
busy flag, the time between the first
instruction and next instruction will take
much longer than the instruction time itself.
Refer to table 6 for the list of each instruction execution time.

HITACHI

237

HD44780U
Table 6 Instructions
Code
Instruction

RS

RIW DB7 DBe DBs DB4 DB3 DB2 DB, DBo

Clear
display

0

0

0

0

0

0

0

0

Return
home

0

0

0

0

0

0

0

0

Entry
mode set

0

0

0

0

0

0

0

Display
on/off
control

0

0

0

0

0

0

Cursor or
display
shift

0

0

0

0

0

Function
set

0

0

0

0

SetCG
RAM
address

0

0

0

Set DO
RAM
address

0

0

Read busy
lIag&
address

0

238

BF

0

1

Description
Clears entire display and
sets DO RAM address 0 in
address counter.

Execution 11me
(max) (when fep or
fose I. 270 kHz)
15.2ms

Sets DO RAM address 0 in 15.2 ms
address counter. Also
returns display from being
shifted to original position.
DO RAM contents remain
unchanged.

110

S

Sets cursor move direction 371lS
and specifies display shift.
These operations are
performed during data
write and read.

C

B

Sets entire display (D)
ontoff. cursor on/off (C).
and blinking of cursor
position character (B).

371's

Moves cursor and shifts
display without changing
DO RAM contents.

371lS

Sets interface data length
(OL). number of display
lines (N). and character
font (F).

371lS

ACG ACG AcG ACG ACG ACG

Sets CG RAM address.
CG RAM data is sent and
received after this setting.

371lS

ADD ADD ADD ADD ADD ADD ADD

Sets DO RAM address.
DD RAM data is sent and
received after this setting.

371lS

AC

Reads busy flag (BF)
OIlS
indicating internal operation
is being performed and
reads address counter
contents.

SIC AIL

OL

AC

0

AC

N

-

F

AC

AC

AC

AC

HITACHI

HD44780U
Table 6 Instructions (cont)

Description

Execution Time
(mex) (when lep or
lose Is 270 kHz)

Writes data into DO RAM
orCG RAM.

37 115
tACO 4115*

Code
Instruction

o

Write data
to CGor
DO RAM

Write data

Read data

Read data
from CG or
DO RAM

Reads data from DO RAM 37 115
or CG RAM.
tACO = 4115*

110 = 1: Increment
110 = 0: Decrement
S

DO RAM: Display data
Execution time
RAM
changes when
CG RAM: Character
frequency changes
generator RAM Example:
ACG: CG RAM address
When f", or fosc
ADD: DD RAM address
is 250 kHz,
(corresponds to
270
37 115 x 250 = 40 I's
cursor address)
AC: Address counter
used for both DD and
CG RAM addresses

= 1: Accompanies display shift

SIC = 1: Display shift
SIC = 0: Cursor move
AIL
AIL
DL
N
F
SF
SF
Note: -

= 1:
= 0:
= 1:
= 1:
=1:
= 1:
= 0:

=

Shift to the right
Shift to the left
8 bits, DL = 0: 4 bits
2 lines, N = 0: 1 line
5x10dots,F=0: 5x8dots
Internally operating
Instructions acceptable

indicates no effect.

* After execution of the CG RAM/DO RAM data write or read instruction, the RAM address counter is
incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off.
In figure 13, tACO is the time elapsed after the busy flag turns off until the address counter is updated.

Busy signal
(D~ pin)

-

B",y'"''

41-,_______________
,

Address counter
(DBo to DB6 pins)

______A__-+'____

:..

~~~------A-+--1------..:

Note: tADD depends on the operation frequency
t ADD = 1.5/(f cp or f esc) seconds

Figure 13 Address Counter Update

HITACHI

239

HD44780U
Instruction Description
Clear Display
Clear display writes space code 20H (character
pattern for character code 20H must be a blank
pattern) into all DD RAM addresses. It then sets
DD RAM address 0 into the address counter, and
returns the display to its original status if it was
shifted. In other words, the display disappears and
the cursor or blinking goes to the left edge of the
display (in the first line if 2 lines are displayed). It
also sets lID to 1 (increment mode) in entry mode.
S of entry mode does not change.
Return Home
Return home sets DD RAM address 0 into the
address counter, and returns the display to its
original status if it was shifted. The DD RAM
contents do not change.
The cursor or blinking go to the left edge of the
display (in the first line if 2 lines are displayed).
Entry Mode Set
lID: Increments (lID = 1) or decrements (lID = 0)
the DD RAM address by 1 when a character code
is written into or read from DD RAM.
The cursor or blinking moves to the right when
incremented by 1 and to the left when
decremented by 1. The same applies to writing
and reading of CG RAM.
S: Shifts the entire display either to the right
(lID =0) or to the left (lID = 1) when S is 1. The
display does not shift if S is O.

If S is 1, it will seem as if the cursor does not
move but the display does. The display does not
shift when reading from DD RAM. Also, writing
into or reading out from CG RAM does not shift
the display.
Display On/Off Control
D: The display is on when D is 1 and off when D
is O. When off, the display data remains in DD
RAM, but can be displayed instantly by setting
Dto 1.

240

C: The cursor is displayed when C is 1 and not
displayed when C is O. Even if the cursor
disappears, the function of liD or other
specifications will not change during display data
write. The cursor is displayed using 5 dots in the
8th line for 5 X 8 dot character font selection and
in the 11 th line for the 5 x 10 dot character font
selection (figure 16).
B: The character indicated by the cursor blinks

when B is 1 (figure 16). The blinking is displayed
as switching between all blank dots and displayed
characters at a speed of 409.6-ms intervals when
fep or fose is 250 kHz. The cursor and blinking
can be set to display simultaneously. (The
blinking frequency changes according to fose or
the reciprocal of fep. For example, when fep is
270 kHz, 409.6 x 250/270 = 379.2 ms.)
Cursor or Display Shift
Cursor or display shift shifts the cursor position or
display to the right or left without writing or
reading display data (table 7). This function is
used to correct or search the display. In a 2-line
display, the cursor moves to the second line when
it passes the 40th digit of the first line. Note that
the first and second line displays will shift at the
same time.
When the displayed data is shifted repeatedly each
line moves only horizontally. The second line
display does not shift into the first line position.
The address counter (AC) contents will not change
if the only action performed is a display shift.
Function Set
DL: Sets the interface data length. Data is sent or
received in 8-bit lengths (DB7 to DBo) when
DL is 1, and in 4-bit lengths (DB7 to DB4) when
DL is O.
When 4-bit length is selected, data must be sent or
received twice.
N: Sets the number of display lines.

HITACHI

HD44780U
F: Sets the character font

Set CG RAM Address

Note: Perform the function at the head of the
program before executing any instructions
(except for the read busy flag arid address
instruction), From this point, the function
set instruction cannot be executed unless
the interface data length is changed,

Set CG RAM address sets the CO RAM address
binary AAAAAA into the address counter,

Code

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1

RIW DB7 DBa DBs DB4 DBa D~ DB, DBo

RS
Return
home

Code

1010101010101010111*1

Display

onloff control

Code

Cod

Note: * Don't care.

D~ DB, DBo

RIW DB7 DB6 DB5 DB4 DBa

RS
Entry
mode set

D~ DB, DBo

RIW DB7 DBa DB5 DB4 DBa

RS
Clear
display

Data is then written to or read from the MPU for
CORAM,

101010101010101111/DIsi
RS

RIW

o

0

e

D~ DBa DBr; D~ DBa

0

0

0

D~

0

DB, DBo

D

C

B

Figure 14

RS
Cursor or
display shift

Code

Code

SetCG
RAM address

Code

DB7 DBa DBs DB4 DB3 DB2 DB, DBo

1 0 1 0 1 0 1 0 1 0 1 1 1SIC 1 AIL 1 *
RS

Function set

RiW

ANI DB7 DB6 DB5 DB4 DB3 DB2 DB, DBo

1 0 1 0 1 0 1 0 1 1 1 DL 1 N 1 F 1 *

0

1 * 1 Note:· Don't care.

0

0

1
1

-

1 A 1 A 1

A

Higher
order bit

A

A

1 * 1 Note:· Don't care.

-

1 A 1
Lower
order bit

Figure 15

HITACHI

241

HD44780U
Set DD RAM Address

Read Busy Flag and Address

Set DD RAM address sets the DD RAM address
binary AAAAAAA into the address counter.

Read busy flag and address reads the busy flag
(BF) indicating that the system is now internally
operating on a previously received instruction. If
BF is 1, the internal operation is in progress. The
next instruction will not be accepted until BF is
reset to O. Check the BF status before the next
write operation. At the same time, the value of the
address counter in binary AAAAAAA is read ouL
This address counter is used by both CO and DD
RAM addresses, and its value is determined by the
previous instruction. The address contents are the
same as for instructions set CG RAM address and
set DD RAM address.

Data is then written to or read from the MPU for
DDRAM.
However, when N is 0 (I-line display),
AAAAAAA can be OOH to 4FH. When N is 1
(2-1ine display), AAAAAAA can be OOHto 27H
for the first line, and 40H to 67H for the second
line.

Table 7 Shift Function
SIC

R/L

o

o

Shifts the cursor position to the left. (AC is decremented by one.)

o

Shifts the cursor position to the right. (AC is incremented by one.)

o

Shifts the entire display to the left. The cursor follows the display shift.

1

Shifts the entire display to the right. The cursor follows the display shift.

Table 8 Function Set

N

F

0

0

0

No. of
Display
Lines

1

...

2

Character
Font

Duty
Factor

5x8dots

1/8

5x10dots

1/11

5x8dots

1/16

Remarks

Cannot display two lines for 5 x 10 dot character font

Not$: ... Indicates don't care.

242

HITACHI

HD44780U

Z

Cursor -----;.~• • •
5x10dot
character font

5x8dot
character font

Alternating display

Cursor display example

Blink display example

Figure 16 Cursor and Blinking

RS
Set DO
RAM address

Code

0

RiW DB7 DBa DB5 DB4 DB3 DB2 DB1 DBa

0

I1 IA IA IA

-

A

A

A

Higher
order bit

RS
Read busy flag
and address

Code

0

R/W

IA I

-

Lower
order bit

DB7 DBa DB5 DB4 DB3 DB2 DB1 DBa

I I I I
BF

-

A

A

Higher
order bit

A

A

A

A

IA I

-

Lower
order bit

Figure 17

HITACHI

243

HD44780U
Write Data to CG or DD RAM
Write data to CG or DD RAM writes 8-bit binary
data DDDDDDDD to CG or DD RAM.
To write into CG or DD RAM is determined by
the previous specification of the CG RAM or DD
RAM address setting. Mter a write, the address is
automatically incremented or decremented by 1
according to the entry mode. The entry mode also
determines the display shift.
Read Data from CG or DD RAM
Read data from CG or DD RAM reads 8-bit binary
data DDDDDDDD from CG or DD RAM.
The previous designation determines whether CG
or DD RAM is to be read. Before entering this
read instruction, either CG RAM or DD RAM
address set instruction must be executed. If not
executed, the first read data will be invalid. When
serially executing read instructions, the next
address data is normally read from the second
read. The address set instructions need not be

RS
Write data to
CGorDD RAM

Code

RiW

RS
Code

After a read, the entry mode automatically
increases or decreases the address by 1. However,
display shift is not executed regardless of the entry
mode.
Note: The address counter (AC) is automatically
incremented or decremented by 1 after the
write instructions to CG RAM or DD RAM
are executed. The RAM data selected by
the AC cannot be read out at this time even
if read instructions are executed. Therefore,
to correctly read data, execute either the
address set instruction or cursor shift
instruction (only with DD RAM), then just
before reading the desired data, execute the
read instruction from the second time the
read instruction is sent.

DBl DBa DB5 DB4 DB3 DB2 DB, DBa

I 0 I DID I D
-

Read data from
CGorDD RAM

executed just before this read instruction when
shifting the cursor by the cursor shift instruction
(when reading out DD RAM). The operation of
the cursor shift instruction is the same as the set
DD RAM address instruction.

RiW

Higher
order bits

Figure 18

244

DID I DID

I

Lower _
order bits

DB7 DBa DB5 DB4 DB3 DB2 DB, DBa

I 1 I DID I D
-

D

Higher
order bits

HITACHI

D

DID I DID
Lower _
order bits

I

HD44780U
Interfacing the HD44780U
In this example, PB o to PB7 are connected to
the data bus DBo to DB7, and PAn to PA2 are
connected to E, RIW, and RS, respectively.

Interface to MPUs

Interfacing to an 8-bit MPU through a PIA
See figure 20 for an example of using a PIA or
I/O port (for a single-chip microcomputer) as
an interface device. The input and output of
the device is TfL compatible.

Pay careful attention to the timing relationship
between E and the other signals when reading
or writing data using a PIA for the interface.

AS

RiW

______1

\'-----

E
Internal
operation

Instruction
write

Figure 19 Example of Busy Flag Check Timing Sequence

HD68BOO
(8-bit CPU)

HD68B21/HD63B21
(PIA)
A 15
A14
A13
A1
Ao

CS 2
CS 1
CS o
AS 1
RS o

RiW

RlW

VMA
,,2
DBo toDB7

t==D-

E

HD44780U

PA 2

AS

PA 1

RiW

PAo

E

PBo to PB7

8

COM1 to
COM 16

~
LCD

SEG 1 to
SEG4Q

~

DBoto DB7

8

Do to 0 7

Figure 20 Example ofInterface to HD68BOO Using PIA (HD68B21iHD63B21)

HITACHI

245

HD44780U
HD44780U

HD6800

VMA
82
A'5
Ao

......
I
I....

COM, to
COM,6

E

16

RS

RiW

LCD

RiW

SEG, to
DBato DB7 SEG 40

8

Doto 0 7

40

Figure 21 8·Bit MPU Interrace

H8I325

HD44780U

P30 to P37

8

COM, to
DBo to DB7 COM,6

P77
P76
P75

16

LCD

E
RS

SEG, to
SEG40

RiW

40

Figure 22 H8I325 Interrace (Single-Chip Mode)

HD6301

HD44780U

P34
P35
P36

RS

COM, to
COM,6

16

DBa to DB7 SEG, to
SEG40

40

RiW
E

LCD

P,o to P'7

8

Figure 23 HD6301 Interface

246

HITACHI

HD44780U
See figure 25 for an interface example to the
HMCS4019R.

Interfacing to a 4-bit MPU
The HD44780U can be connected to the I/O
port of a 4-bit MPU. If the I/O port has
enough bits, 8-bit data can be transferred.
Otherwise, one data transfer must be made in
two operations for 4-bit data. In this case, the
timing sequence becomes somewhat complex.
(See figure 24.)

Note that two cycles are needed for the busy
flag check as well as for the data transfer. The
4-bit operation is selected by the program.

RS

RIW

-------/

E

~'r----

Internal
operation

Instruction
write

\--------

Busy flag
check

Busy flag
check

Instruction
write

Note: ... IR7, IR3 are the 7th and 3rd bits of the instruction
AC3 is the 3rd bit of the address counter

Figure 24 Example of 4-Bit Data Transfer Timing Sequence

HMCS4019R

HD44780

0 15

RS

0 14

RIW

0 13

E
4

R10 to R13

COM1 to
COM 16

DB t DB SEG 1 to
7 SEG40
40

r!2LCD

~

Figure 25 Example ofInterface to HMCS4019R

HITACHI

247

HD44780U
Interface to Liquid Crystal Display

types of common signals are available (table 9).

Character Font and Number of Lines: The
HD44780U can perform two types of displays, 5 x
8 dot and 5 x 10 dot character fonts, each with a
cursor.

The number of lines and font types can be selected
by the program. (See table 6, Instructions.)

Up to two lines are displayed for 5 x 8 dots and
one line for 5 x 10 dots. Therefore, a total of three

Connection to HD44780 and Liquid Crystal
Display: See figure 26 for the connection
examples.

Table 9 Common Signals
Number of Lines

2

Character Font

Number of Common Signals

Duty Factor

5 x 8 dots + cursor

8

1/8

5 x 10 dots + cursor

11

1/11

5 x 8 dots + cursor

16

1/16

HD44780

COM1~_!!IJ

COM8~

S~G1 ~~~~~

_______________________________________ .

SEG~~------------------------------------~

Example of a 5x8 dot, 8-character x l-line display (1/4 bias, 118 duty cycle)
HD44780

COM1~_1I

COM11~

SEG4o~------------------------------------~

Example of a 5 xl0 dot, 8-character x l-line display (1/4 bias, 1111 duty cycle)

Figure 26 Liquid Crystal Display and HD44780 Connections

248

HITACHI

HD44780U
Since five segment signal lines can display one
digit, one HD44780U can display up to 8 digits for
a I-line display and 16 digits for a 2-line display.
The examples in figure 26 have unused common
signal pins, which always· output non-

selection waveforms. When the liquid crystal
display panel has unused extra scanning lines,
connect the extra scanning lines to these common
signal pins to avoid any undesirable effects due to
crosstalk during the floating state (figure 27).

HD44780

SEG111_~

________________________________ _

SEG40~------------------------------------~

Example of a 5x8 dot, 8-character x2-line display (1/5 bias, 1116 duty cycle)

Figure 26 Liquid Crystal Display and HD44780 Connections (cont)

HD44780

COM1~lliiiiiiiil

COMgf- J

COMaH

SEG1~
SEG40r-------------------------------------~
5 x 8 dot, 8-character x 1-line display (1/4 bias, 1/8 duty cycle)

Figure 27 Using COM9 to Avoid Crosstalk on Unneeded Scanning Line

HITACHI

249

HD44780U
Connection of Changed Matrix Layout: In. the
preceding examples, the number of lines
correspond to the scanning lines. However, the
following display examples (figure 28) are made
possible by altering the matrix layout of the liquid
crystal display panel. In either case, the only
change is the layout. The display characteristics

and the number of liquid crystal display characters
depend on the number of common signals or on
duty factor. Note that the display data RAM (DD
RAM) addresses for 4 characters x 2 lines and
for 16 characters x I line are the same as in
figure 26.

HD44780

COM8~---#~~~--------+-----~~---------+~~H+Hh

SEG

~~

__________________

~

________________-J

COM9~~~~~~~~~~~~~~~~~~~~~~~
COMI6~---------------------------------------------J

HD44780

5 x 8 dot, 16-character x Hine display
(1/5 bias, 1/16 duty cycle)

COM8h-+H~~--~~~r----------+-

SEG ~

1---------------------------'
5 x 8 dot, 4-c~aracter x 2-line display
(1/4 bias, 1/8 duty cycle)

Figure 28 Changed Matrix Layout Displays

250

HITACHI

HD44780U
Power Supply for Liquid Crystal
Display Drive
Various voltage levels must be applied to pins
V1 to V5 of the HD44 780U to obtain the liquid
crystal display drive waveforms. The voltages
must be changed according to the duty factor
(table 10).

VLCD is the peak value for the liquid crystal
display drive waveforms, and resistance dividing
provides voltages V 1 to V5 (figure 29).

Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive
Duty Factor
1/16

1/8, 1/11

Bias
Power Supply

1/4

1/5

V1

Vce-1/4 VLCD

VCc-1IS VLCD

V2

Vcc-1/2 VLCD

Vce-2/S VLCD

V3

Vcc-1/2 VLCD

VCc-3/S VLCD

V4

Vcc-3/4 VLCD

Vcc-4/S VLCD

Vs

VCC-VLCD

VCC-VLCD

vCC (5
+ V)

VCC (+S V)
VCC

Vcc

V1

V1

V2

V2

R
R

R

VLCD
V3
V4

V3

R

V4

Vs

R

Vs
.)

-/
VR

-5V

-SV
1/4 bias
(1/8, 1/11 duty cycle)

VLCD

1/5 bias

(1/16, duty cycle)

Figure 29 Drive Voltage Supply Example

HITACHI

251

HD44780U
Relationship between Oscillation
Frequency and Liquid Crystal Display
-Frame Frequency
The liquid crystal display frame frequencies of
figure 30 apply only when the oscillation

1/8 duty cycle

frequency is 270 kHz (one clock pulse of
3.7 JlS).

~ 400 clocks

COM1

Vet:;
V1
~(~) ----+---~~-+~~~--------~-+--~~--+------­

V4

Vs

1 - - - - - - - 1 frame -------------1

1 frame: 3.7 liS x 400 x 8: 11850 IJS : 11.9 ms
Frame frequency: _1- = 84.3 Hz
11.9 ms

1/11 duly cycle

~ 400 clocks

COMI

Vet:;
V1
V2(~)----+----r-+-+-1--~---------r-+--~~--+------­

V4

Vs

1 - - - - - - - - 1 frame -------------1

1 frame: 3.711$ x 400 x 11: 16300 liS: 16.3 ms
Frame frequency: ___
1 _ =61.4 Hz
16.3 ms
1/16 duty cycle
COMI

Vet:;

m

~

2

200 clocks

1

3

1

4

1 ---------116 1

L

V1
V3
V4

I

I

1,,0-------1
...
frame------·~I
1 frame: 3.7 liS x 200 x 16: 11850 lis: 11.9 ms
Frame frequency: _1- : 84.3 Hz
11.9 ms

Figure 30 Frame Frequency
252

2

l

V2

Vs

1

HITACHI

1

HD44780U
Connection with HD44100 Driver
By externally connecting an HD44100 liquid
crystal display driver to the HD44780U. the
number of display digits can be increased. The
HD44100 is used as a segment signal driver when
connected to the HD44780U. The HD44100 can
be directly connected to the HD44 780U since it
supplies CL I • CL2 • M. and D signals and power
for the liquid crystal display drive (figure 31).

Up to nine HD44100 units can be connected for a
I-line display (duty factor 1/8 or 1/11) and up to
four units for a 2-line display (duty factor 1/16).
The RAM size limits the HD44780U to a
maximum of 80 character display digits. The
connection method for both I-line and 2-line
displays or for 5 x 8 and 5 x 10 dot character fonts
can remain the same (figure 26).

Caution: The connection of voltage supply pins
V 1 through V6 for the liquid crystal
display drive is somewhat complicated.

HD44780

COM ,-COM,.
(COM ,-COM.>

UI~~
SEG,-8EG..

0

40

Ol,

y,-------y••
H044100

....... =-

~~

-I'40

Fes
SHl,
SHL.

40

OR.r-- Ol,
OlZO
DR,

Fes
SHl,
SHl.

y,-------y••
H044100

OR.r.--------- Ol,
OLzO
DR,

p~~ t~!"-:-:-:=~:-

PP;r: R~«««
-N

II

II

COl

el,
el.
M

.-

Dot-matrix liquid crystal display panel

1 16 (8);

Voo
V.
V.
V.

40

y,-------y..

FCS
SHl, H044100
SHL.

DR.

DL.]
DR,

COl

P£2~ t~~::~~:=:-

_"'W"'CII~

GNO

-I'-

--------------._---.-------

:dJ

Figure 31 Example of Connecting HD44100s to HD44780

HITACHI

253

HD44780U
Instruction and Display Correspondence
8-bit operation, 8-digit x I-line display with
internal reset

8-bit operation, 8-digit x 2-line display
For a 2-line display, the cursor automatically
moves from the first to the second line after
the 40th digit of the first line has been written.
Thus, if there are only 8 characters in the first
line, the DD RAM address must be again set
after the 8th character is completed. (See
table 13.) Note that the display shift operation
is performed for the first and second lines. In
the example of table 13, the display shift is
performed when the cursor is on the' second
line. However, if the shift operation is
performed when the cursor is on the first line,
both the first and second lines move together.
If the shift is repeated, the display of the
second line will not move to the first line. The
same display will only shift within its own line
for the number of times the shift is repeated.

Refer to table 11 for an example of an
8-digit x I-line display in 8-bit operation. The
HD44780U functions must be set by the
function set instruction prior to the display.
Since the display data RAM can store data for
80 characters, as explained before, the RAM
can be used for displays such as for advertising
when combined with the display shift
operation.
Since the display shift operation changes only
the display position with DD RAM contents
unchanged, the first display data entered into
DD RAM can be output when the return home
operation is performed.
•

4-bit operation, 8-digit x I-line display with
internal reset
The program must set all functions prior to the
4-bit operation (table 12). When the power is
turned on, 8-bit operation is automatically
selected and the first write is performed as an
8-bit operation. Since DBo to DB3 are not
connected, a rewrite is then required.
However, since one operation is completed in
two accesses for 4-bit operation, a rewrite is
needed to set the functions (see table 12).
Thus, DB4 to DB7 of the function set
instruction is written twice.

254

Note: When using the internal reset, the electrical
characteristics in the Power Supply
Conditions Using Internal Reset Circuit
table must be satisfied. If not, the
HD44780U must be initialized by
instructions. See the section, Initializing
by Instruction.

HITACHI

HD44780U
Table 11 8-Bit Operation, 8-Digit x I-Line Display Example with Internal Reset
Instruction
Step
No. RS RIW DB7 DBa DBs DB4 DB3 DB z DB1 DBo Display

2

3

4

5

6

Operation

Power supply on (the HD447aOU is initialized by
the internal reset circuit)

Initialized. No display.

Function set
0
0
0

Sets to a-bit operation and
selects 1-line display and 5 x a
dot character font. (Number of
display lines and character
fonts cannot be changed after
step #2.)

0

0

Display on/off control
0
0
0
0
0

0

Entry mode set
0
0
0
0

0

0

0

...

...

Turns on display and cursor.
Entire display is in space mode
because of initialization.

0

1

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CG RAM.
Display is not shifted.

0

0

Write data to CG RAM/DD RAM
1
1
0
0
1
0
0

0

0

Write data to CG RAMIDD RAM
0
0
1
0
0
1
1

0

0

Write data to CG RAMIDD RAM
1
1
0
0
1
0
0

0

0

0

lH

I HI

Writes H. DD RAM has
already been selected by
initialization when the power
was turned on.
The cursor is incremented by
one and shifted to the right.
Writes I.

7

a

9
10

Entry mode set
0
0
0
0

0

0

I HITACHI
I HITACHI

0

Write data to CG RAMIDD RAM
0
0
0
0
0
1
1

0

0

0

IITACHI

HITACHI

Writes I.
Sets mode to shift display at
the time of write.
Writes a space.

255

HD44780U
Table 11 8-Bit Operation, 8-Digit x I-Line Display Example with Internal Reset (cont)
Instruction
Step
No. RS RiWDB, DBa DBs DB4 DB3 DBz DB, DBo Display
Write data to CG RAMIDD RAM
11
ITACHI M_
1
0
0
1
0
0
1
0

Operation
WritesM.

12

13

Write data to CG RAMIDD RAM
1
0
0
1
0
0
1

14

Cursor or display shift
0
0
0
0
0

0

0

• •

IMICROK2

Shifts only the cursor position
to the left.

Cursor or display shift
0
0
0
0
0

0

0

• •

IMICROKO

Shifts only the cursor position
to the left.

Write data to CG RAMIDD RAM
1
0
0
0
0
0
1

0

IICROCO

Writes Cover K.
The display moves to the left.

• •

IMICROCQ

Shifts the display and cursor
position to the right.

• •

IMICROCO_

Shifts the display and cursor
position to the right.

0

IICROCOM

15
16
17

Cursor or display shift
0
0
0
0
0

18

Cursor or display shift
0
0
0
0
0

19

IMICROKO_

0

Write data to CG RAMIDD RAM
1
0
0
1
0
0
1

WritesO.

Writes M.

20

21

256

Return home
0
0
0
0

0

0

0

0

0

I HITACHI

HITACHI

Returns both display and cursor
to the original position
(address 0).

HD44780U
Table 12 4·Bit Operation, 8·Digit x I·Line Display Example with Internal Reset

~ep ____~~-----ln-s-t-ru-d--lo-n-------------No.

2

3

4

RS RIW DB7 DBs DBs DB4

Display

Operation

Power supply on (the HD44780U is initialized by
the internal reset circuit)

Initialized. No display.

Function set
o 000

0

Sets to 4·bit operation.
In this case, operation is
handled as 8 bits by initialization, and only this instruction
completes with one write.

Function set
000
0000*

0
*

o

Sets 4-bit operation and selects
1-line display and 5 x 8 dot
character font. 4-bit operation
starts from this step and
resetting is necessary.
(Number of display lines and
character fonts cannot be
changed after step #3.)

Display on/off control
000
000

o

0

1

1

1

Turns on display and cursor.
Entire display is in space mode
because of initialization.

0

5

Entry mode set
0
0
000
000
1
1
0

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CG RAM.
Display is not shifted.

6

Write data to CG RAMIDD RAM
100
1
0
0
101
000

Writes H.
The cursor is incremented by
one and shifts to the right.

o

Note: The control is the same as for 8-bit operation beyond step #6.

HITACHI

257

HD44780U
Table 13 8·Bit Operation, 8·Digit x 2·Line Display Example with Internal Reset
Instruction
Step
No. RS RIW DB7 DBs DB, DB4 DB3 DBz DB, DBa Display

2

3

4

5

Operation

Power supply on (the HD447aOU is initialized by
the internal reset circuit)

Initialized. No display.

Function set
0
0
0

...

Sets to a·bit operation and
selects 2-line display and
5 x a dot character font.

0

Turns on display and cursor.
All display is in space mode
because of initialization.

0

0

Display onloff control
0
0
0
0
0

0

Entry mode set
0
0
0
0

0

0

...

0

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DDICG RAM.
Display is not shifted.

0

Write data to CG RAMIDD RAM
1 0
0
1
0
0
1

0

0

Write data to CG RAMIDD RAM
1 0
0
1
0
0
1

0

0

Set DO RAM address
0
0
1
1
0

0

0

0

I

H_

Writes H. DO RAM has
already been selected by
initialization when the power
was turned on. The cursor is
incremented by one and shifted
to the right.

S

7

a

258

0

0

I

HITACHI

0

IHITACHI

HITACHI

Writes I.

Sets DO RAM address so that
the cursor is positioned at the
head of the second line.

HD44780U
Table 13 8·Bit Operation, 8·Digit x 2·Line Display Example with Internal Reset (cont)
Stap

No.
9

Instruction
RS RiW Dar DB, DBs DB4 DBs D~ DB, DBo Display
Write data to CG RAMJOD RAM
0
0
1
0
0
1
1

I~TACHI

0

Operation
WritesM.

10

11

12

Write data to CG RAMIDD RAM
1
0
0
1
0
1
0

WritesO.

Entry mode set

Sets mode to shift display at
the time of write.

0
13

0

0

0

0

0

0

Write data to CG RAM/DD RAM
1 0
0
1
0
1
0

Writes M. Display is shifted to
the left. The first and second
lines both shift at the same time.

0

14

15

Return home
0
0
0
0

0

0

0

0

0

HITACHI

Returns both display and cursor
to the original position
(address 0).

259

HD44780U
Initializing by Instruction
If the power supply conditions for correctly
operating the internal reset circuit are not met,
initialization by instructions becomes necessary.

(

Refer to figures 32 and 33 for the procedures on
8-bit and 4-bit initializations, respectively.

)

Power on

Wait for more than 15 ms
after Vee rises to 4.5 V

(

RS FWI DSr DBa DBs DB4 D~ DB:! DBl DBa
0 0 0 0 1 1

• • • •

Wait for more than 40 ms )
after Vee rises to 2.7 V

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS FWI DSr DBa DBs DB4 D~ DB:! DBl DBa
0 0 0 0 1 1
* * *

•

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 100 IJS

AS FWI DSr DBa DBs DB4 DB3 DB:! DBl DBa
0 0 0 0 1 1 * * * *

RS FWI DB7 DBa DBs DB4 DB3 DB:! DBl DBa
0 0 0 0 1 1 N F * *

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

~

1
0
0

0
0
1

0 0
0 1
liD S

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuclion
time. (See table 6.)
Function set (Interface is 8 bits long. Specify the
number of display lines and character font.)
The number of display lines and character font
cannot be changed after this point.
Display off
Display clear
Entry mode set

Initialization ends

Figure 32 8-Bit Interface

260

HITACHI

HD44780U

(

I

I
Wait for more than 15 ms
after Vee rises to 4.5 V

(

I

AS

0

I

)

Power on

( I BF cannot be checked before this instruction.

FWi D~ DBe DBs DB4
0

0

0

1

1

Function set (Interface is 8 bits long.)

J

I

Wait for more than 4.1 ms

I

( I BF cannot be checked before this instruction.

AS RW D~ DBe DBs DB4

0

0

0

0

1

Wait for more than 40 ms )
after Vee rises to 2.7 V

1

Function set (Interface is 8 bits long.)

I

I

I

Wait for more than 100 liS

I
AS RW D~ DBe DBs DB4

0

0

0

0

1

1

I
AS RW D~ DBe DBs DB4

1

0

0

1

0

F

*

*

0

0

0

0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
N
0
1
0
0
0
0

0 0 0
0 0 0
0 0 0
0 0 1
0 0 0
1 110 S

+

Initialization ends

I

( I BF cannot be checked before this instruction.
Function set (Interface is Ii bits long.)

BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See table 6.)
Function set (Set interface to be 4 bits long.)
Interface is 8 bits in length.
Function set (Interface is 4 bits long. Specify the
number of display lines and character font.)
The number of display lines and character font
cannot be changed after this point.
Display off
Display clear
Entry mode set

Figure 33 4·Bit Interface

HITACHI

261

HD44780U
Absolute Maximum Ratings·
Item

Symbol

Value

Unit

Power supply voltage (1)

Vcc-GNO

-0.3 to +7.0

V

Power supply voltage (2)

Vcc-Vs

-0.3 to +13.0

V

Input voltage

Notes

1,2

VI

-0.3 to Vee +0.3

V

Operating temperature

Toer

-20 to +75

·C

3

Storage temperature

TS!g

-55 to +125

·C

4

Note: Hthe LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limits is strongly recommended for normal
operation. Hthese electrical characteristic conditions are also exceeded, the LSI will malfunction and
.cause poor reliability.

DC Characteristics (Vee

=2.7 V to 4.5 V, Ta =-20 to +75°C·3)

Symbol

Item

Min

Typ

Max

Unit

Test Condition

6

Notes·

Input high voltage (1)
(except OSC,)

VIH,

0.7Vee

Vee

V

Input low voltage (1)
(except OSC,)

VIL1

-0.3

0.55

V

6

Input high voltage (2)
(OSC,)

VIH2

O· 7Vee

Vee

V

15

Input low voltage (2)
(OSC,)

VIL2

0. 2Vee

V

15

Output high voltage (1) VOH,
(OBo-087 )
Output low voltage (1)
(OBo-087 )

0.75Vee
0.2Vee

VOL1

Output high voltage (2) V0H2
(except OBo-D~)

O.SVee

V

-IoH= 0.1 mA

7

V

IOL" 0.1 mA

7

V

-IOH .. 0.04 mA

8

Output low voltage (2)
(except OBo-D~)

V0L2

0.2Vee

V

IOL • 0.04 mA

S

Oriver on resistance
(COM)

ReaM

20

kn

±Id .. 0.05 mA,
VLeo =4 V

13

Oriver on resistance
(SEG)

RSEG

30

kn

±Id - 0.05 mA,
VLco =4 V

13

Input leakage current

III

-1

~

VIN .. Oto Vee

9

Pull-up MOS current
(OBo-087 , RS, RIW)

-Ip

10

Power supply current

Icc

LCOvoltagl]l

VLCO,
VLC02

Note:

262

3.0
3.0

50

120

~

Vee =3 V

0.15

0.30

mA

Rf oscillation,
10,14
external clock
Vee - 3V, fosc .. 270 kHz

11.0

V

Vec-Vs, 115 bias

16

11.0

V

Vee-Vs, 1/4 bias

16

* Refer to the Electrical Characteristics Notes section following these tables.
HITACH~

HD44780U
AC Characteristics (VCC

=2.7 V to 4.5 V, Ta =-20 to +75°C*3)

Clock Characteristics
Symbol Min

Item
External
clock
operation

Max

Unit

External clock frequency

fcp

125

250

350

kHz

External clock duty

Duty

45

50

55

0/0

External clock rise time

trcp

0.2

I1S

tfcp

0.2

ItS

350

kHz

External clock fall time
R,
oscillation

Typ

Clock oscillation frequency fose

190

270

Test Condition

Not.·
11

R, =75kn.
Vee =3V

12

Note: • Refer to the Electrical Characteristics Notes section following these tables.

Bus Timing Characteristics
Write Operation
Item

Symbol

Min

Enable cycle time

tcycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr. tEl

Typ

Max

Unit

Test Condition

ns

Figure 34

Unit

Test Condition

ns

Figure 35

25

Address set-up time (RS. ANI to E) tAS

60

Address hold time

tAH

20

Data set-up time

tosw

195

Data hold time

tH

10

Item

Symbol

Min

Enable cycle time

Read Operation

tcycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr. tel

Typ

Max

25

Address set-up time (RS. RIW to E) tAS

60

Address hold time

tAH

20

Data delay time

tOOR

Data hold time

tOHR

360
5

HITACHI

263

HD44780U
Interface Timing Characteristics with External Driver
Symbol

Min

High level

tcWH

800

Low level

Item
Clock pulse width

tcWL

800

Clock set-up time

tcsu

500

Data set-up time

tsu

300

Data hold time

tOH

300

Mdelaytime

tOM

-1000

Clock riselfall time

'lYP

Max

Unit

Test Condition

ns

Figure 36

1000
200

let

Power Supply Conditions Using Internal Reset Circuit
Item
Power supply rise time
Power supply off time

264

Symbol

Min

tree
toFF

0.1

'iYP

HITACHI

Max

Unit

Test Condition

10

ms

Figure 37

HD44780U
DC Characteristics

(VCC

Item

=4.5 V to 5.5 V, Ta =-20 to +7soC*3)
Typ

Symbol

Min

Max

Unit

Input high voltage (1)
(except OSC1)

V'H1

2.2

Vcc

V

6

Input low voltage (1)
(except OSC1)

V'L1

-0.3

0.6

V

6

Input high voltage (2)
(OSC1)

V'H2

Vcc-1.0 -

Vcc

V

15

Input low voltage (2)
(OSC 1)

V'l2

1.0

V

15

Output high voltage (1)
(OBo-OB7)

VOH1

Output low voltage (1)
(OBo-OB7)

VOll

Output high voltage (2)
(except OBo-0B7)

VOH2

Output low voltage (2)
(except OBo-0B7)

VOl2

Driver on resistance
(COM)

2.4

Test Condition

Note.*

V

-IOH .. 0.205 rnA

7

V

IOL-1.2mA

7

V

-IOH .. 0.04 rnA

8

0.1 Vcc

V

IOL"' 0.04 rnA

8

RooM

20

kn

±Id = 0.05 rnA.
VLCO- 4 V

13

Driver on resistance
(SEG).

ASEG

30

kn

±Id .. 0.05 rnA.
VLCO= 4 V

13

Input leakage current

9

0.4
0.9Vcc

III

-1

Pull-up MOS current
(080-0B7' AS. AIW)

-Ip

50

Power supply current

Icc

LCD voltage

VLC01

3.0

VLCD2

3.0

~

V'N - Oto Vcc

125

250

~

VCC" 5 V

0.35

0.60

rnA

A, oscillation.
10.14
external clock
Vcc = 5 V. fosc .. 270 kHz

11.0

V

Vcc-Vs. 115 bias

16

11.0

V

Vcc-Vs. 1/4 bias

16

Note: * Aefer to the Electrical Characteristics Notes section following these tables.

AC Characteristics

(VCC

=4.5 V to 5.5 V, T a =-20 to +7soC*3)

Clock Characteristics
Item
External
clock
operation

R,
oscillation

Symbol Min

Typ

Max

Unit

Test Condition

Not.*

External clock frequency

fcp

125

250

350

kHz

11

External clock duty

Duty

45

50

55

%

11

External clock rise time

trcp

0.2

ILS

11

External clock fall time

tfcp

0.2

ILS

11

350

kHz

Clock oscillation frequency fosc

190

270

Rf" 91 kn
Vcc" 5.0 V

12

Note: * Refer to the Electrical Characteristics Notes section following these tables.

HITACHI

265

HD44780U
Bus Timing Characteristics
Write Operation

Item

Symbol

Min

Enable cycle time

fcycE

500

Enable pulse width (high level)

PWEH

230

Enable risellall time

ier' tEl

Max

Unit

Test Condition

ns

Figure 34

Unit

rest Condition

ns

Figure 35

20

Address set-up time (RS, RIW to E) tAS

40

Address hold time

tAH

Data set-up time

tosw
tH

10
80
10

Item

Symbol

Min

Enable cycle time

fcycE
PWEH

500
230

Data hold time

lYP

Read Operation

Enable pulse width (high level)

tooR

Data hold time

tDHR

Max

20

Enable risellall time
tEr> tEl
Address set-up time (RS, RIW to E) tAS
Address hold time
tAH
Data delay time

lYP

40
10
160
5

Interface Timing Characteristics with External Driver
Item
Clock pulse width

Symbol

Min

High level

IcWH

800

Low level

IcwL

800
500
300
300
-1000

Clock set-up time

Icsu

Data set-up time

tsu

Data hold time

tDH

M delay time

tOM

Clock riselfall time

1ct

lYP

Max

Unit

Test Condition

ns

Figure 36

1000
100

Power Supply Conditions Using Internal Reset Circuit
Item

Symbol

Power supply rise time

tree

Power supply off time

toFF

266

. Min

1YP

0.1

HITACHI

Max

Unit

Test Condition

10

ms

Figure 37

HD44780U
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0 v.
Vee - - , . - - - - - . - -

B
V1

--+-----''----A

Vs

_ - - L . _ _ _ __

The conditions of V1 and Vs voltages are for proper
operation of the LSI and not for the LCD output level.
The LCD drive voltage condition for the LCD output
level is specified as LCD voltage VLCD •

A = Vee-Vs
B -Vec-Vl

A ~ 1.5 V
B :s;O.25xA

2.

Vee ~ V 1 ~ V2 ~ V3 ~ V4 ~ V5 must be maintained.

3.

For die products, specified up to 75°C.

4.

For die products, specified by the die shipment specification.

5.

The following four circuits are I/O pin configurations except for liquid crystal display output.

Inpm pin
Pin: E (MaS without pull-up)

Vee

1/0 Pin
Pins: DBo-DB7
(MaS with pull-up)

Pins: RS,

RJW (MaS with pull-up)

Vee

Output pin
Pins: Cl l , Cl2, M, 0

Vee'

Vee
(input circuit)
PMOS

1-.,------

Input enable

Vee
I---~1--1~--+-

Output
enable data

NMOS

HITACHI

267

HD44780U
6.

Applies to input pins and I/O pins, excluding the OSCI pin.

7.

Applies to I/O pins.

8.

Applies to output pins.

9.

Current flowing through pull-up MOSs, excluding output drive MOSs.

10. Input/output current is excluded. When input is at an intennediate level with CMOS, the excessive
current flows through the input circuit to the power supply. To avoid this from happening, the input
level must be fixed high or low.
11. Applies only to external cloclc operation.

Th

Open

TI

0.7 Vee
0.5 Vee
0.3 Vee

OSC:!

trcp
Duty -

t,cp

ThT: TI x 100%

12. Applies only to the internal oscillator operation using oscillation resistor Re.
R t : 75 kn ± 2% (when Vee" 3 V)
R t : 91 kn ± 2% (when Vee" 5 V)
Since the oscillation frequency varies depending on the OSC 1 and
OSC 2 pin capacitance, the wiring length to these pins should be minimized.

Vee =5 V

......
N

500

500 ,---,--,.---,--,.....-,.--,

400

400

Hrt'~+--+-+---t--l

300

I-.lod-~+--''''ci--+---t--l

'

¥

:J:

~ 300

§

-

(270)

.lII:

----

~

--

~

_0

200
100

50

(91)100

100

150

I...---I..._..L---L_~=_.J

50

(75)

100

Rt (kn)

R, (kn)

268

(270) ----

HITACHI

HD44780U
13. ReoM is the resistance between the power supply pins (Vee. V 1. V 4. V 5) and each common
signal pin (COM1 to COM16)'
RSEG is the resistance between the power supply pins (Vee. V 2. V 3. V 5) and each segment signal pin

(SEG 1 to SEG40).
14. The following graphs show the relationship between opemtion frequency and current consumption.
Vee = 5 V

Vee =3 V

1.8

1.8

1.6

1.6

1.4

1.4

1.2

<"
.§.

1.0

8

0.8

..........- max.

0.6

...
...

0.4
0.2
0.0

o

.....~

100

.

V

........-- ----

-

200

300

~

400

t yp.

1

1.2
1 .0

8 0 .8
0.6
0.4

-

0.2
500

0.0

f esc or! cp (kHz)

o

100

-- -,..-

200

300

-

400

max.
typo

500

f osc or f cp (kHz)

15. Applies to the OSC 1 pin.
16. Each COM and SEG output voltage is within ±O.15 V of the LCD voltage (Vee. Vb V 2• V 3• V 4• Vs)
when there is no load.

HITACHI

269

HD44780U
Load Circuits
Data Bus DBo to DB,

VcC ·5V

For Vee - 4.5 to 5.5 V

For Vee - 2.7 to 4.5 V
3.9kn

Test
point

Test

point 0----5-0-P-F""'t
90pF

IS2074G:J)
diodes

External driver control signals: CLI, CLl, D, M
Test

point 0 - - -- P-F-'t
30

270

HITACHI

HD44780U
Timing Characteristics

AS

=><
~

'VIHI
VILI

VIHI
VILI
tAS

tAH

VILI

/vILl

-

PWEH

-

E

>(

I

tAH
r---tEf

VIHI '\
VIL1

VIHI
VILI

f4-- t Er

)<

V IL1
tH

tosw

VIHI
VILI

VIHI

Valid data

VIL1

>(

tCYCE

Figure 34 Write Operation
RS

=><
~

VIHI
Vil
tAS

VIHI

-

K

VIHI

'\.

tAH

PWEH

E

VIHI
VII

I

VIHI
VILI

-

tAH
r---tEf

VIHI '\
V IL1

V IL1

f4-tEr
tOOR

)<

tDHR

VOHI.
V0l1

Valid data

• VOHI
V0l1

K

tcycE

Note: • VOL1 is assumed to be 0.8 V at 2 MHz operation.

Figure 35 Read Operation

HITACHI

271

HD44780U

CL1

VOH2
V0l2

o
tOH

M
tOM

Figure 36 Interface Timing with External Driver

Vee

tOFF*1

0.1 ms:s; t rcc :s; 10 ms

tOFF ~1

ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power
supply oscillations.
2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation.
3. For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not
operate normally.
In this case, the LSI must be initialized by software. (Refer to the Initializing
by Instruction section.)

Figure 37 Internal Power Supply Reset

272

HITACHI

HD66702 (LCD-II/E20)-(Dot Matrix Liquid Crystal Display
Controller/Driver)
Description
The HD66702 LCD-II/E20 dot-matrix liquid
crystal display controller and driver LSI displays
alphanumerics, Japanese kana characters, and
symbols. It can be configured to drive a dotmatrix liquid crystal display under the control of a
4- or 8-bit microprocessor. Since all the functions
required for driving a dot-matrix liquid crystal
display are internally provided on one ChiP, a
minimal system can be interfaced with this
controller/driver.
A single LCD-II/E20 can display up to two
20-character lines. However, with the addition of
HD44100 drivers, a maximum of up to two
40-character lines can be displayed.
The low 3-V power supply of the LCD-II/E20 under
development is suitable for any portable batterydriven product requiring low power dissipation.

Features

•

5 x 7 and 5 x 10 dot matrix possible
80 x 8-bit display RAM (80 characters max.)
7,200-bit character generator ROM
- 160 character fonts (5 x 7 dot)
- 32 character fonts (5 x 10 dot)
64 x 8-bit character generator RAM
- 8 character fonts (5 x 7 dot)
- 4 characterfonts (5 x 10 dot)
16-common x 100-segment liquid crystal
display driver

Programmable duty cycles
- 1/8 for one line of 5 x 7 dots with cursor
- 1/11 for one line of 5 x 10 dots with cursor
- 1/16 for two lines of 5 x 7 dots with cursor
Maximum display characters
- One line:
1/8 duty cycle, 20-char. x I-line (no
extension), 28-char. x I-line (extended
with one HD44100), 80-char. x I-line
(max. extension with eight HD44100s).
1/11 duty cycle, 20-char. x I-line (no
extension), 28-char. x I-line (extended
with one HD44IOO), 80-char. x I-line
(max. extension with eight HD44IOOs)
- Two lines:
1/16 duty cycle, 20-char. x 2-line (no
extension), 28-char. x 2-line (extended
with one HD44100), 40-char. x 2-line
(max. extension with eight HD44100s)
Wide range of instruction functions:
- Display clear, cursor home, display on/off,
cursor on/off, display character blink,
cursor shift, display shift
Choice of power supply (Vcc>: 4.5 to 5.5 V
(standard), 2.7 to 5.5 V (low voltage)
Automatic reset circuit that initializes the
controller/driver after power on (standard
version only)
Independent LCD drive voltage driven off of
the logic power supply (Vce>: 3.0 to 7.0 V

Ordering Information
Type No.

Package

Operating Voltage

ROM Fonl

HCD66702RAOO

Chip'
Chip

4.5 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
4.5105.5 V
4.5 to 5.5 V
4.5105.5 V
2.7105.5 V
4.5105.5 V
2.7105.5 V

Standard Japanese fonl

HCD66702RAOOL
HD66702RAOOF
HD66702RAOOFL

144-pin plastic OFP (FP-144A)
144-pin plastic OFP (FP-144A)
144-pin plaslic OFP (FP-144A)
144-pin plastic OFP (FP-144A)

HD66702RAOl F
HD66702RA02F
HCD66702RBxx

Chip

HCD66702RBxxL
HD66702RBxxF

Chip
144-pin plastic OFP (FP-144A)

HD66702RBxxFL
144-pin plaslic OFP (FP-144A)
Note: xx: ROM code No.

HITACHI

Japanese font for comunication system
European font
Custom font

273

HD66702
LCD-II Family Comparison
Item

LCD-II
(HD44780)

LCD-lilA
(HD66780)

LCD-IIIE20
(HD66702)

Power supply voltage

5 V ±10%

5 V ±10%

5 V ±10% (standard)
3 V ±1 0% (low voltage)

Liquid crystal drive
voltage VlCD

1/4 bias

3.0 to 11 V

3.0 Vto Vcc

3.0 to 6.0 V

115 bias

4.6 to 11 V

3.0 Vto Vcc

3.0 to 6.0 V

Maximum display
digits per chip

16 digits
(8 digits x 2 lines)

16 digits
(8 digits x2 lines)

40 digits
(20 digits x 2 lines)

Display duty cycle

1/8,1/11, and 1116

1/8, 1/11, and 1/16

1/8,1/11, and 1/16

CGROM

7,200 bits
(160 character fonts
for 5 x 7 dot and
32 character fonts
for 5 x 10 dot)

12,000 bits
(240 character fonts
for 5 x 10 dot)

7,200 bits
(160 character fonts for
5x7dotand
32 character fonts for
5x10dot)

CGRAM

64 bytes

64 bytes

64 bytes

DDRAM

80 bytes

80 bytes

80 bytes

Segment signals

40

40

100

Common signals

16

16

16

Liquid crystal drive waveform

A

B

B

Ladder resistor for LCD
power supply

External

External

External

Clock source

External resistor,
external ceramic
filter, or external
clock

External resistor,
external ceramic
filter, or external
clock

External resistor or
external clock

Rt oscillation frequency
(frame frequency)

270 kHz ±30%
(59 to 110 Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1/11
duty cycle)

270 kHz ±30%
(59 to 110 Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1111
duty cycle)

320 kHz ±30%
(69 to 128 Hz for 1/8
and 1/16 duty cycles;
50 to 93 Hz for 1/11
duty cycle)

Rt resistance

91 kn±2%

83 kn±2%

68 kn ±2% (standard)
56 kn ±2% (low voltage)

Instructions

Fully compatible within the LCD-II family

CPU bus timing

1 MHz

2 MHz

1 MHz

Package

FP-80, FP-80A, and
80-pin bare chip
(no package)

FP-80B and FP-80A

144-pin bare chip
(no package) and
FP-144A

274

HITACHI

HD66702
LCD-IIlE20 Block Diagram

OSC

Reset
circuit
ACL

r--

RS

MPU
interface

-

Rm -

E

I~

Instruction
register (IR)

Input!
output
buffer

-'-

I

Address
counter

D

COM, to

.....

16-bit
shift
register

Common
signal
driver

1~O-bit
latch
circuit

Segment
signal
driver

11

Data
register
(DR)

I'

7
8

8

'00
8

8

_Busy
flag

~
~

1~O-bit
shift
register

7

Character
generator
RAM
(CG RAM)
64 bytes

5
~

Vee

I

.---

~.6
'6

SEG, to
SEG, 00

~

1111
LCD drive
voltage
selector

~

~

GND

Timing
generator

+

t
7

TEST

M

Display
data RAM
(DD RAM)
80 x 8 bits

Instruction
decoder

j

-

CL
CL2

~

t

-

DBo to
DB3

,

EXT

ill

r----

8

OSC

Character
generator
ROM
(CG ROM)
7,200 bits

Cursor
and
blink
controller

15
Parallel/serial converter
and
f-attribute circuit

!!!!!

HITACHI

275

HD66702
LCD-IIlE20 Pad Arrangement

.3

SEc;,.. . 1
SEGos . 2
SEGsa
SEGa,
4
SEG. . . 5
SEG. . . 6
SEGu
SEG27
SEG. . . 9
SEG. . . 10
SEG", .11
SEG. . . 12
SEGu .13
SEG., .14
SEGro .15
SEG,. .16
SEG,• • 17
SEG 17 .18
SEG,. .19
SEG,s
SEG,• • 21
SEG,• • 22
SEG,• • 23
SEG" .24
SEG,• • 25
SEG.
26
SEG • • 27
SEG7.28
SEGa .29
SEGs .30
SEG • • 31
SEG • • 32
SEG.
33
SEG, .34
GND .35
OSC• • 36

I III
I I
I
I
!~!~~~~~~~;~!~~~~~~~~~~§~~~~~~~~~~~~

.7.8

.20

No1e:'

o
•

FlI
•

18

276

~

Type coda

HD66702

Teat pins to be grounded
Power supply pins
Power supply pins (ground)
Input pins
OUtput pins
InpullOutput pins

~opview)

Minimum pad pitch - 130 ~m

HITACHI

HD66702
HCD66702 Pad Location Coordinates
Pad

Pad

Pad

Pad

No.

Name

X (!.Lm)

Y{!.Lm)

No.

Name

X (J.lm)

Y{!.Lm)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

SEGa.!

-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475

2350
2205.
2065
1925
1790
1655
1525
1395
1265
1135
1005
875
745
615
485
355
225
95
-35
-165
-295
-425
-555
-685
-815
-945
-1075
-1205
-1335
-1465

31
32
33
34
35
36
37
38
39
40
41
42

SEG4

asc2
asc,

43

V4

-2475
-2475
-2475
-2475
-2475
-2475
-2445
-2305
-2165
-2025
-1875
-1745
-1595
-1465
-1335
-1185
-1055
-905
-775
-625
-495
-345

-1600
-1735
-1870
-2010
-2180
-2325
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475

SEG33
SEG32
SEG3,
SEGal!
SEG29
SEG28
SEG27
SEG28
SEG25
SEG24
SEG23
SEG22
SEG2,
SEG20
SEG'9

17

SEG,8

18
19
20
21
22
23
24
25
26
27
28
29
30

SEG17
SEG'6
SEG,s
SEG'4
SEG'3
SEG'2
SEG"
SEG,o
SEGg
SEG8
SEG7
SEG6
SEGs

-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475

SEGa
SEG2
SEG,
GND

Vee
Vee
V,
V2
V3

44

Vs

45
46
47
48
49
50
51
52

CL,

53
54
55
56
57
58
59
60

HITACHI

CL2

M

0
EXT
TEST
GND
RS

FWI
E
DBo
DB,
DB2
DB3
DB4
DBs

-195
-45
85
235
365
515
645
795

-2475
-2475
-2475
-2475

HD66702
HCD66702 Pad Location Coordinates (cont)
Pad
No.

Pad
Name

61
62

DBa

63

COM 1

64

COM2

65
66
67
68
69
70
71
72
73
74
75
76

COM3

D~

COM 4
COMs
COM6
COM7
COMa
COM9
COM 10
COM 11
COM 12
COM 13
COM 14

77

COM 1S

78
79
80
81
82

COM 16

SEGg7

83

SEG96

84
85
86
87
88
89
90

SEG9s

278

SEG100
SEGgs
SEGss

SEG94
SEG93
SEGg2
SEGgl
SEGso
SEG89

X{Jl.m)

Y{Jl.m)

925
1075
1205
1335
1465
1595
1725
1855
1990
2125
2265
2410
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475

-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2475
-2290
-2145
-2005
-1865
-1730
-1595
-1465
-1335
-1205
-1075
-945

-815
-685
-555
-425
-295
-165
~

Pad
No.

Pad
Name

X{Jl.m)

Y{Jl.m)

91
92

SEG88

95

93

SEG86

94

SEG6S

95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

SEG84

2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2320
2175
2035
1895

615
745
875
1005
1135
1265
1395
1521)
1655
1790
1925
2065
2205
2350
2475
2475
2475
2475

1760
1625
1495
1365
1235
1105
975
845

2475
2475
2475
2475
2475
2475
2475
2475

HITACHI

SEG87

SEG63
SEG82
SEG81
SEG60
SEG79
SEG78
SEG77
SE~6

SEG7S
SEG74
SE~3

SE~2

SEG71
SE~o

SEG69
SEG68
SEG67
SEG66
SEG6S
SEG64
SEG63
SEG62
SEG6l
SEG60
SEGS9

225
355

485

HD66702
HCD66702 Pad Location Coordinates (cont)
Pad
Pad
Name
No.
Y (11m)
X(11m)
2475
133
SEG46
-845
121
SEGsa
2475
134
SEG4S
-975
SEGS7
122
455
2475
135
SEG44
-1105
123
SEGsa
325
2475
136
SEG43
-1235
124
SEGss
195
2475
137
SEG42
-1365
125
SEG54
2475
SEG53
65
138
SEG41
-1495
126
-65
2475
139
SEG40
-1625
127
SEG52
2475
140
SEG39
-1760
128
SEGS1
-195
-325
2475
141
SEG 38
-1895
129
SEG50
2475
142
130
SEG49
-455
SEG37
-2035
-585
2475
143
SEG38
131
SEG48
-2175
144
132
SEG47
-715
2475
SEG3S
-2320
Notes: 1. Coordinates originate from the chip center.
2. The above are preliminary specifications, and may be subject to change.
Pad

No.

Pad
Name

X(11m)
715
585

HITACHI

Y (11m)
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475
2475

279

HD66702
HD66702 Pin Arrangement

SEG".
SEG..
SEGs.
SEG3'
SEGs.
SEG..
SEG..
SEG.7
SEG..
SEG••
SEG••
SEG.,
SEG..
SEG.,
SEG..
SEG,.
SEG,.
SEG 17
SEG,.
SEG,.
SEG,.
SEG'3
SEG,.
SEG"
SEG,.
SEG •.
SEG.
SEG7
SEG.
SEG.
SEG.
SEG3
SEG.
SEG,
GND

SEG 7I
SEG 72
SEG,.
SEG ..
SEGn
SEG7•
SEG 77
SEG7I
SEG n
SEG..
SEG.,
SEG..
SEG u
SEG ••
SEG ••
SEG ••
SEG 87
SEG ••
SEG ••
SEG,.
SEG"
SEG..
SEG 13
SEG,.
SEG.,
SEG ••
SEG.7
SEG..
SEG..
SEG,oo
COM,.
COM,.
COM,.
COM'3
COM,.
COM"

0

18

OSC.

Note: • : Test pins to be grounded
Power supply pins
• : Power supply pins (ground)
Er:I : Input pins
I : Output pins
E:I : InpuVOutput pins

o:

280

FP-I44A
(top view)

HITACHI

OD66702
Pin Functions
Table 1 Pin Functional Description
Signal

110

Device
Interfaced with

Function

RS

MPU

Selects registers.
0: Instruction register (for write)
Busy flag: address counter (for read)
1: Data register (for write and read)

RIW

MPU

Selects read or write.
0: Write
1: Read

E

I

MPU

Starts data readlwrite

DB4 to DB7

va

MPU

Four high order bidirectional tristate data bus pins. Used
for data transfer between the MPU and the lCD-1I1E20.
DB7 can be used as a busy flag.

DBa to DB3

va

MPU

Four low order bidirectional tristate data bus pins. Used
for data transfer between the MPU and the lCD-1I1E20.
These pins are not used during 4-bit operation.

Cl1

0

HD441 00

Clock to latch serial data 0 sent to the HD44100H driver

Cl2

0

HD441 00

Clock to shift serial data 0

M

0

HD441 00

Switch signal for converting the liquid crystal drive
waveform to AC

0

0

HD44100

Character pattern data corresponding to each segment
signal

COM 1 to COM 16

0

LCD

Common signals that are not used are changed to nonselection waveforms.COMg to COM16 are nonselection waveforms at 1/8 duty factor and COM 12 to
COM16 are non-selection waveforms at 1/11 duty factor.

SEG1 to SEG 100

o

LCD

Segment signals

V1 to Vs

Power supply

Power supply for LCD drive

Vcc.GND

Power supply

Vee: +5 V or +3 V. GND: 0 V

TEST

Test pin. which must be grounded

EXT

0: Enables extension driver control signals Cl1• Cl2• M.
and 0 to be output from its corresponding pins.
1: Drives Cl1• Cl2• M. and 0 as tristate. lowering power
dissipation.

OSC1.OSC2

Pins for connecting the registers of the internal clock
oscillation. When the pin input is an external clock. it
must be input to OSC1 •

HITACHI

281

HD66702
Function Description
Registers

Busy Flag (BF)

The HD66702 has two 8-bit registers, an
instruction register (IR) and a data register (DR).

When the busy flag is I, the HD66702 is in the
internal operation mode, and the next instruction
will not be accepted. When RS 0 and R/W 1
(table 2), the busy flag is output to DB-r. The next
instruction must be written after ensuring that the
busy flag is O.

The IR stores instruction codes, such as display
clear and cursor shift, and address information for
display data RAM (DD RAM) and character
generator RAM (CG RAM). The IR can only be
written from the MPU.
The DR temporarily stores data to be. written into
DD RAM or CG RAM. Data written into the DR
from the MPU is automatically written into DD
RAM or CG RAM by an internal operation. The
DR is also used for data storage when reading data
from DD RAM or CG RAM. When address
information is written into the IR, data is read and
then stored into the DR from DD RAM or CG
RAM by an internal operation. Data transfer
between the MPU is then completed when the
MPU reads the DR. After the read, data in DD
RAM or CG RAM at the next address is sent to
the DR for the next read from the MPU. By the
register selector (RS) signal, these two registers
can be selected (table 2).

=

Address Counter (AC)
The address counter (Ae) assigns addresses to
both DD RAM and CG RAM. When an address
of an instruction is written into the IR, the address
information is sent from the IR to the AC.
Selection of either DD RAM or CG RAM is also
determined concurrently by the instruction.
After writing into (reading from) DD RAM or CG
RAM, the AC is automatically incremented by 1
(decremented by 1). The AC contents are then
output to DBo to DB6 when RS = 0 and R/W = 1
(table 2).

Table 2 Register Selection
RS

o
o

Operation

o

IR write as an internal operation (display clear, etc.)
Read busy flag (DB7) and address counter (DBa to DB6 )

o

DR write as an internal operation (DR to DO RAM or CG RAM)
DR read as an internal operation (DO RAM or CG RAM to DR)

282

=

HITACHI

HD66702
Display Data RAM (DD RAM)

-

Display data RAM (DD RAM) stores display data
represented in 8-bit character codes. Its extended
capacity is 80 x 8 bits. or 80 characters. The area
in display data RAM (DD RAM) that is not used
for display can be used as general data RAM. See
figure 1 for the relationships between DD RAM
addresses and positions on the liquid crystal
display.

Case 2: For a 28-character display. the
HD66702 can be extended using one
HD44100 and displayed. See figure 4.
When the display shift operation is
performed. the DD RAM address shifts.
See figure 4.

-

The DD RAM address (ADD) is set in the address
counter (AC) as hexadecimal.

Case 3: The relationship between the
display position and DD RAM address
when the number of display digits is
increased through the use of two or more
HD44100s can be considered as an
extension of case #2.

I-line display (N = 0) (figure 2)
-

Since the increase can be eight digits per
additional HD44100. up to 80 digits can be
displayed by externally connecting eight
HD44100s. See figure 5.

Case 1: When there are fewer than 80
display characters. the display begins at the
head position. For example. if using only
the HD66702. 20 characters are displayed.
See figure 3.
When the display shift operation is
perfonned. the DD RAM address shifts.
See figure 3.

High order

I--- bits

__ 14

Low order
bits ----I

~~xadeCimal) IAC6IAC5~C4IAC3IAC21 AC11Acoi

Example: DO RAM address 4E
1

10 10 1

1

1

79

80

10

Figure I DD RAM Address

Display position
(digit)

~~:~~

2

3

4

5

1 00 1 01 1 021 031 041 . . . . . . . . . . . . . . . . .. 14E 14F

I

(hexadecimal)

Figure 2 I-Line Display

HITACHI

283

HD66702
Display
position
DDRAM
address
For
shift left
For
shift right

L-...L--I----''-...L---'----I_-'----'---!._.l..--'--'-_'---'--I----''-...L---'----I----J

Figure 3 I·Line by 20·Character Display Example

1 2

3

4 5

6

7

8 9 10 11 12 13 14 15 16 17 18 1920 21 22232425 26 2728

y
LCD-II/E20 display

y
HD44100 display

For
shift left

Figure 4 I·Line by 28·Character Display Example

Display
position

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 1617 18 192021 22232425 26 2728

77 78 7980

DDRAM
address

y
LCD-II/E20 display

1st HD44100

8th HD44100

display

display

Figure 5 I·Line by 80·Character Display Example

284

HITACHI

HD66702
2-line display (N = 1) (figure 6)
-

consecutive. For example, when just the
HD66702 is used, 20 characters x 2 lines
are displayed. See figure 7.

Case 1: When the number of display
characters is less than 40 x 2 lines, the two
lines are displayed from the head. Note
that the first line end address and the
second line start address are not

Display
position

2

3

4

When display shift operation is perfonned,
the DD RAM address shifts. See figure 7.

5

39

40

.................. 26 27
41 42 43 44 .................. 66 67

00
DDRAM
address
(hexadecimal) 40

02

01

03 04

Figure 6 2-Line Display

Display
position
DDRAM
address

For
shift left

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54

27 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12
For
shift right
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

Figure 7 2-tine by 20-Character Display Example

HITACHI

285

HD66702
-

Case 2: For a 28-character x 2-line display,
the HD66702 can be extended using one
HD44100. See figure 8.
When display shift operation is performed,
the DD RAM address shifts. See figure 8.

-

Case 3: The relationship between the
display position and DD RAM address

Display
position

1 2

3

4 5

6

7

8

when the number of display digits is
increased by using two or more HD44100s.
can be considered as an extension of case
#2. See figure 9.
Since the increase can be 8 digits x 2 lines
for each additional HD44100. up to
40 digits X 2 lines can be displayed by
externally connecting three HD44100s.

9 10 11 12131415161718 192021 22232425262728

DDRAM 00 0102 03 0405 06 07 08 090A OEOC OC OE OF 1011 1213 14 1516 1718 19 lA 18
address
40 4142 43 4445 46 47 48 49 4A 4E 4C 40 4E 4F 50 51 52 53 54 55 56 57 58 59 ~A ~8
'--_ _ _ _ _ _ _ _y_----------'/''-~_---y~_--'I

LCD-II/E20 display

HD44100 display

010 03 04 05 06 01 08 09 OA OE OC 00 OE OF 1011 12 13 14 1516 1718 191A 18 lC

For
shift left

4142 4344 45 46 47 48 49 4A 48 ~C 40 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 58 5C

27 00 0102 03 04 05 06 07 08 09 OA OE pC 00 OE OF 1011 12 1314 15 1617 18 19 lA
For
shift right
67 40 4142 43 44 45 46 47 48 49 4A 4E ~C 40 4E 4F 50 5152 5354 55 56 57 58 59 5A

Figure 8 2-Line by 28-Character Display Example

Display
position
DO RAM
address

1 2 3 4 5 6 7 8 9 1011 1213141516171819'2021 22232425 26 2728

37 38 3940

00 01 0203 0405 060 0809 OJ OB ~c OC OE OF Ie 11 1213 1415 1617 1819 lA B

........ 2425 26 21

4041 4243 4445 464 4849 4J 4B ~C4C ~E 4F 5051 5253 5455 56 57 5659 5A5B

........

,

I

y

LCD-II/E20 display

'---y---/

1st HD44100
display

3rd HD44100
display

Figure 9 2·Line by 4O·Character Display Example

286

HITACHI

6465 6E 87

'---y-----'

HD66702
Character Generator ROM (CG ROM)

Modifying Character Patterns

The character generator ROM generates 5 x 7 dot.
or 5 x 10 dot character patterns from 8-bit
character codes (table 5). It can generate
160 5 x 7 dot character patterns and 32 5 x 10 dot
character patterns. User-defined character patterns
are also available by mask-programmed ROM.

•

Character Generator RAM (CG RAM)
In the character generator RAM, the user can
rewrite character patterns by program. For 5 x 7
dots, eight character patterns can be written, and
for 5 x 10 dots, four character patterns can be
written.
Write the character codes at the addresses shown
as the left column of table 5 to show the character
patterns stored in CG RAM.
See table 6 for the relationship between CG RAM
addresses and data and display patterns.

Areas that are not used for display can be used as
general data RAM.

Character pattern development procedure

The following operations correspond to the
numbers listed in figure 10:

1. Determine the correspondence between
character codes and character patterns.
2. Create a listing indicating the correspondence
between EPROM addresses and data.
3. Program the character patterns into the
EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing on the EPROM is
performed at Hitachi to create a character
pattern listing, which is sent to the user.
6. If there are no problems within the character
pattern listing, a trial LSI is created at Hitachi
and samples are sent to the user for evaluation.
When it is confirmed by the user that the
character patterns are correctly written, mass
production of the LSI proceeds at Hitachi.

HITACHI

287

HD66702
Hitachi

User

Determine
character patterns

®
@

®
No

Note: For a description of the numbers used in this figure, refer to the preceding page.

Figure 10 Character Pattern Development Procedure

288

HITACHI

HD66702
-

Programming character patterns
This section explains the correspondence
between addresses and data used to program
character patterns in EPROM.
The
LCD-II/E20 character generator ROM can
generate 160 5 x 7 dot character patterns and
32 5 x 10 dot character patterns for a total of
192 different character patterns.

5 x 7 dot character pattern
EPROM address data and character pattern
data correspond with each other to form a
5 x 7 dot character pattern (table 3).

Table 3 Example of Correspondence between EPROM Address Data and Character Pattern
(Sx 7 dots)

LSB
A,o Ag A8 A7 A6 As A4 A3 A2 A, Ao 0 4 0 3 0 2 0, 0 0
0

1

0

1

0

0

1

0

0

0

0

0

0

1

0

1

0

0

0

1

0

1

0

1
0

1
Character code
Notes: 1.
2.
3.
4.
5.
6.

Fill line 8 (cursor position)
with Os

Line
position

EPROM addresses A,o to A3 correspond to a character code.
EPROM addresses A2 to Ao specify a line position of the character pattern.
EPROM data 0 4 to 0 0 correspond to character pattern data.
A lit display position (black) corresponds to a 1.
Line 8 (cursor position) of the character pattern must be blanked with as.
EPROM data 05 to 0 7 are not used.

HITACHI

289

HD66702
-

5 x 10 dot character pattern

3. EPROM data used when the user does not
use any HD66702 character pattern:
According to the user application, handled in
one of the two ways listed as follows.

EPROM address data and character pattern
data correspond with each other to form a
5 x 10 dot character pattern (table 4).
-

i. When unused character patterns are not
programmed: If an unused character code
is written into DD RAM, all its dots are lit
By not programing a character pattern, all
of its bits become lit (This is due to the
EPROM being filled with Is after it is
emsed.)

Handling unused character patterns

1. EPROM data outside the character pattern
area: Ignored by the character genemtor ROM
for display operation so 0 or 1 is arbitrary.
2. EPROM data in CG RAM area: Ignored by
the character generator ROM for display
operation so 0 or 1 is arbitrary.

ii. When unused character patterns are
programmed as Os; Nothing is displayed
even if unused character codes are written
into DD RAM. (This is equivalent to a
space.)

Table 4 Example of Correspondence between EPROM Address Data and Character Pattern
(5 x 10 dots)
EPROM Address

Data

LSB
A 10 Ag As A7 A6 As A4 A3 A2 Al Ao 0 4 0 3 O 2 0 1 0 0

0

0 0

0

0

0

0

0

0

0

0

0

0

0

0

0

~1

I

0

0

0

1

0

1

0
1

0

0

0

1

0
1
0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

Character code

Fill line 11 (cursor position)
with Os

Line
position

Notes: 1. EPROM addresses A 10 to A3 correspond to a character code. Set As and Ag of character
pattern lines 9, 10. and 11 to Os.
2. EPROM addresses A2 to Ao specify a line position of the character pattern.
3. EPROM data 0 4 to 0 0 correspond to character pattern data.
4. A lit display position (black) corresponds to a 1.
5. Blank out line 11 (cursor position) of the character pattern with Os.
6. EPROM data 05 to 0 7 are not used.

290

HITACHI

HD66702
Table 5 Correspondence between Character Codes and Character Patterns (ROM code: AOO)

Note: The user can specify any pattern for character-generator RAM.

HITACHI

291

HD66702
Table 5 Correspondence between Character Codes and Character Patterns (ROM code: AOl)

292

HITACHI

HD66702
Table 5 Correspondence between Character Codes and Character Patterns (ROM code: A02)
0010 0011 0100

0110 0111 1010

1100 1101

1111

CG

xxxxOOOO

RAM
(1l

xxxxOOO1

(2)

xxxxOO10

(3)

xxxxOO11

(4)

xxxx0100

(5)

xxxx0101

(6)

xxxx0110

(7)

xxxx0111

(8)

xxxx1000

(1 )

xxxx1001

(2)

xxxx1010

(3)

xxxx1011

(4)

xxxx1100

(5)

xxxx1101

(6)

xxxx1110

(7)

xxxx1111

(8)

HITACHI

293

H066702
Table 6 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character
Patterns (CG RAM data)
For 5 x 7 dot character patterns
CG RAil Addr...

765 4 3 2 1 0
High

o

Low

0 0 0 * 001

543 2 1 0
High

Low

0 0 0
0 0
0
0
0
000
0 0
0 1
0
1 1
0 0 0
0 0
0
0
0
001
1 0 0
0 1
0
0

0000*111

o
o

765 432 1 0
High

I
I

Low

Character
pattern

Cursor position

0
1

o
* * *

Notes: 1. Character code bits 0 to 2 correspond to CG RAM address bits 3 to 5 (3 bits: 8 types).
2. CG RAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor.
Maintain the 8th line data, corresponding to the cursor display poSition, at 0 as the cursor display.
If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence.
3. Character pattern row positions correspond to CG RAM data bits 0 to 4 (bit 4 being at the left ).
Since CG RAM data bits 5 to 7 are not used for display, they can be used for general data RAM.
4. As shown tables 5 and 6, CG RAM character patterns are selected When character code bits
4 to 7 are all o. However, since character code bit 3 has no effect, the R display example above
can be selected by either character code OOH or 08H.
5. 1 for CG RAM data corresponds to display selection and 0 to non-selection.
• Indicates no effect.

294

HITACHI

HD66702
Table 6 Relationship between CG RAM Addresses, Character Codes (DD RAM) and Character
Patterns (CG RAM data) (cont)
For 5 x 10 dot character patterns
CG RAM Addr•••

76543 2 1 0
High

Low

5 4 3 2 1 0
High

Low
:0 0 0 0

io
io

lo

io
o

0

io

i0

:0

i1
i1

0

Low

0

0
Character
pattern

0 0

0
1 0
1
0 0 0

0 0

:1 0 1 1

,: 1

High

• • •

0 0 1

_____ ~LQ--L
~

'VIHI
VILI

VIHI
VILI
lAS

VILI

/vILl

-

PWEH

-

E

K

IAH

II

IAH
_lEI

~

VIH1,
VIL1

VIHI
VILI

~IE'

).

IH

IOSW

VIHI
VIL1

Valid data

VIHI
VIL1

~

VIHI
VILI

K

VIHI

"-

ICYCE

Figure 35 Write Operation

RS

RiW

=>
~

VIHI
VIL1
lAS

IAH

VIHI
PWEH

E

DBo 10 DB7

-

V

-

IAH
I---IEI

V1H1
VIL1

V 1H1
VIL1
-IE,

1\

IOOR

).

IOHR

VOHI
VOL1

Valid data
IcycE

Figure 36 Read Operation
332

V1L1

HITACHI

VOHI
VOL1

K

HD66702

VOH2
VOl2

D

tOH

M

Figure 37 Interface Timing with External Driver

Vee

tOFF·l
tOFF ~1 ms

0.1 ms s;t rcc S; 10 ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power
supply oscillations.
2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation.
3. When the above condition cannot be satisfied, the internal reset circuit
will not operate normally.
In this case, the LSI must be initialized by software. (Refer to the Initializing
by Instruction section.)

Figure 38 Internal Power Supply Reset

HITACHI

333

HD66710 (LCD-II/FS)--(Dot Matrix Liquid Crystal Display
Controller/Driver)
- PreliminaryDescription
The LCD-II/F8 (HD66710) dot-matrix liquid
crystal display controller and driver LSI displays
alphanumerics, numbers, and symbols. It can be
configured to drive a dot-matrix liquid crystal
display under the control of a 4- or 8-bit
microprocessor. Since all the functions such as
display RAM, character generator, and liquid
crystal driver, required for driving a dot-matrix
liquid crystal display are internally provided on
one chip, a minimum system can be interfaced
with this controller/driver.

•
•

Booster for liquid crystal voltage
- 1\vo/three times (13 V max.)
Wide range of liquid crystal display driver
voltage
- 3.0V to 13 V

•
•

Extension driver interface
High-speed MPU bus interface
(2 MHz at 5-V operation)

•

4-bit or 8-bit MPU interface capability

•

80 x 8-bit display RAM (SO characters max.)

A single LCD-II/F8 is capable of displaying a
singlel6-character line, two 16-character lines, or
up to four 8~character lines.

•

9,600-bit character generator ROM
- 240 characters (5 x 8 dot)

The LCD-II/F8 software is upwardly compatible
with the LCDII (HD44780) which allows the user
to easily replace an LCD-II with an HD66710. In
addition, the HD66710 is equipped with functions
such as segment displays for icon marks, a 4-line
display mode, and a horizontal smooth scroll, and
thus supports various display forms. This achieves
various display forms. The HD66710 character
generator ROM is extended to generate 240 5 x 8
dot characters.

•

• 64 x 8-bit character generator RAM
- 8 characters (5 x 8 dot)

•
•

Programmable duty cycle
(See list I)

•

Wide range of instruction functions:
- Functions compatible with LCD-II:
Display clear, cursor home, display on/off,
cursor on/off, display character blink,
cursor shift, display shift
- Additional functions: Icon mark control, 4line display, horizontal smooth scroll, 6-dot
character width control, white-black
inverting blinking cursor.

•
•

Software upwardly compatible with HD44780.
Automatic reset circuit that initializes the
controller/driver after power on

•
•

Internal oscillator with an external resistor
Low power consumption

The low voltage version (2.7 V) of the HD66710,
combined with a low power mode, is suitable for
any portable battery-driven product requiring low
power dissipation.

Features
•
•

5 x 8 dot matrix possible
Low power operation support:
2.7 V to 5.5 V (low voltage)

334

8 x 8-bit segment RAM
- 4O-segment icon mark
33-common x 40-segment liquid crystal
display driver

HITACHI

HD66710
List 1 Programmable Duty Cycles
Number of
Lines

Maximum Number of Displayed Characters

Duty Ratio

Displayed
Character

Single-chip Operation

With Extentlon Driver

1/17

5 x 8-dot

One 16-character
line + 40 segments

One 50-character
line + 40 segments

2

1/33

5 x 8-dot

Two 16-character
lines + 40 segments

Two 30-character
lines + 40 segments

4

1/33

5 x 8-dot

Four 8-character
lines + 40 segments

Four 20-character
lines + 40 segments

Ordering Information
'iYpeNo.

Package

HD66710***FS

1OO-pin plastic QFP (FP-100A)

HCD6671 0***

Chip

Note: ***

=ROM code No.

HITACHI

335

HD66710
LCD·II Family Comparison
Item

LCD·II
(HD44780U)

LCD-II/E20
(HD66702)

LCD·II/F8
(HD66710)

Power supply voltage

2.7VtoS.S V

S V±10%
(standard)

2.7 Vto S.S V

2.7 Vto S.S V
(low voltage)
Liquid crystal drive
voltageV lcD

3.0 Vto 11 V

3.0 Vto 7.0 V

3.0 Vto 13.0 V

Maximum display
digits per chip

8 characters
x2lines

20 characters
x2lines

16 characters x 2 lines/
8 characters x 4 lines

Segment display

None

None

40 segments

Display duty cycle

1/8, 1/11, and 1/16

1/8,1111, and 1/16

1/17 and 1/33

CGROM

9,920 bits
(208: S x 8 dot
characters and
32:Sx10dot
characters)

7,200 bits
(160: S x 7 dot
characters and
32:Sx10dot
characters)

9,600 bits
(240: S x 8 dot
characters)

CGRAM

64 bytes

64 bytes

64 bytes

DDRAM

80 bytes

80 bytes

80 bytes

SEGRAM

None

None

8 bytes

Segment signals

40

100

40

Common signals

16

16

33

Liquid crystal drive waveform

A

B

B

Bleeder resistor for LCD
power supply

External
(adjustable)

External
(adjustable)

External
(adjustable)

Clock source

External resistor,
or external clock

External resistor or
external clock

External resistor or
external clock

Rt oscillation frequency
(frame frequency)

270 kHz±30%
(59 to 110 Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1/11
duty cycle)

320 kHz±30%
(70 to 130 Hz for 1/8
and 1/16 duty cycles;
51 to 95 Hz for 1/11
duty cycle)

270kHz±30%
(S6 to 103 Hz for 1/17
duty cycle;
57to 106 Hz for 1/33
duty cycle)

Rt resistance

91 kn (S-V operation)
75 kn (3-V operation)

68 kn (S-V operation)
S6 kn (3-V operation)

91 kn (S-V operation)
75 kn (3-V operation)

Liquid crystal voltage
booster circuit

None

None

2-3 times step-up circuit

336

HITACHI

HD66710
LCD·D Family Comparison (cont) ,
LCD-II
(HD44780U)

LCD-II/E20
(HD66702)

LCD-II/F8
(HD66710)

Independent
control signal

Independent
control signal

Used in common with a
driver output pin

Instructions

LCD-II (HD447S0)

Fully compatible with
the LCD-II

Upper compatible with
the LCD-II

Number of displayed
lines

1 or 2

1 or 2

1,2, or 4

Hem
Extention driver
control signal

low power mode

None

None

Available

Horizontal scroll

Character unit

Character unit

Dot unit

CPU bus timing

2 MHz (5-V operation) 1 MHz
1 MHz (3-V operation)

2 MHz (5-Voperation)
1 MHz (3-Voperation)

Package

OFP1420-8Q
SO-pin bare chip

OFP1420-100
100-pln bare chip

LOFP2020-144
144-pin bare chip

HITACHI

337

HD66710
HD66710 Block Diagram

escl

OSC2

EXT

Vel - - - - - ,

Cl
C2

Voo

---~-------~--1r--~--_t--~r_--------------------------~

OND

---;1.VI

338

V2

V3

V4

VS

HITACHI

HD66710
HD66710 Pin Arrangement

SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37/CL1
SEG38/CL2
SEG39/D
SEG40/M
COM9
COM10
COMll
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32

80
79
78

77
76
75
74
73
72
71
70
69
68
67

LCD·II!F8

66

SEG6
SEG5
SE;G4
SEG3
SEG2
SEGl
VCC
TEST
EXT
DB7

DBS
DBS
DB4
DB3

65

DB2
DBl

64
63

E

62
61
60
59
58
57

56
55
54
53
52

~~3334~~UM~~~~~"~~O~~OO~

DBO
Rfii
AS
OSC2
OSCl
Vci
C2
Cl
GND

V50UT2
V50UT3
V5
V4

Top View

HITACHI

339

HD66710
HD66710 Pad Arrangement

Chip size (X xV):
Coordinate
:
Origin
:
Pad size (XxV) :
1

80

000000000000000000

79

I

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

/'

Type code

29

52

000000000000000000
30 31

340

81

100

2

V

5.63 mm x 6.06 mm
Pad center
Chip center
100 Ilm x 100 Ilm

X

HITACHI

50 51

HD66710
HD66710 Pad Location Coordinates
Pin No.

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45
46
47
48
49
50

Pad Name

x

SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
COM9
COM10
COMll
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM33

-2495
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2695
-2495
-2051
-1701
-1498
-1302
-1102
-899
-700

V1

V2
V3

-500
-301

-101
99
302
502
698
887
1077

1266
1488
1710
2063

y
2910
2730
2499
2300
2100
1901
1698
1498
1295
1099
900
700
501
301
98
-113
-302
-501

-701
-900
-1100
-1303
-1502
-1702
-1901
-2101
-2300
-2500
-2731
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910
-2910

Pin No.

Pad Name

x

51
52
53
54

V4
V5

V50UT3
V50UT2

55

GND

56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

Cl
C2

2458
2660
2660
2660
2640
2650
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2675
2695
2695
2695
2695
2695
2695
2495
2049
1699
1499
1300

77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

HITACHI

Vci

OSCl
OSC2
RS
RIW
E

DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
EXT
TEST

Vee
SEGl
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEGll
SEG12
SEG13.
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26

1100

901
701

502
299

99
-101
-301
-500

-700
-899
-1099

-1302
-1501
-1701
-2051

y
-2910
-2731
-2500
-2300
-2090
-1887
-1702
-1502
-1303
-1103
-900
-701
-501

-302
-99

98
301
501
700
900
1099
1299
1502
1698
1901

2104
2300
2503
2730
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910
2910

341

HD66710
Pin Functions
Thble 1 Pin Functional Description
Signal

110

Device
Interfaced with

Function

RS

MPU

Selects registers.
0: Instruction register (for write)
Busy flag: address counter (for read)
1: Data register (for write and read)

RIW

MPU

Selects read or write.
0: Write
1: Read

E

MPU

Starts data readlwrite

DB4to DB7

110

MPU

Four high order bidirectional tristate data bus pins. Used
for data transfer between the MPU and the HD66710.
DB7 can be used as a busy flag.

DBOto DB3

1/0

MPU

Four low order bidirectional tristate data bus pins. Used
for data transfer between the MPU and the HD66710.
These pins are not used during 4-bit operation.

COM1 to COM33

o

LCD

Common signals; those are not used become nonselected waveforms. At 1/17 duty rate, COM1 to
COM16 are used for character display, COM17 for icon
display, and COM18 to COM33 become non-selected
waveforms. At 1133 duty rate, COM1 to COM32 are
used for character display, and COM33 for icon display.

SEG1 to SEG35

0

LCD

Segment signals

SEG36

0

LCD

Segment signal. When EXT .. high, the same data as
that of the first dot of the extension driver is output.

SEG37/CL1

0

LCDI

Segment signal when EXT .. low. When EXT - high,
outputs the extension driver latch pulse.

Extension driver
SEG38/CL2

0

LCDI
Extension driver

SEG391D

SEG40/M
"

0

0

LCDI
Extension driver

Segment signal at EXT .. low. At EXT .. high, the
extension driver data. Data on and after the 36th
dot is output.

LCDI

Segment signal when EXT .. low. When EXT = high,
outputs the extension driver AC signal.

Extension driver

Extension driver enable signal. When EXT .. high,
SEG37 to SEG40 become extension driver interface
signals. At this time, make sure that V5 level is lower
than GND level (0 V). V5 (low) s GND (high).

EXT

V1 to V5

342

Segment signal when EXT .. low. When EXT .. high,
outputs the extension driver shift clock.

Power supply

Power supply for LCD drive
Vee - V5 .. 13 V (max)

HITACHI

HD66710
Table 1 Pin Functional Description (cont)
Device
Interfaced with

Function

Vee, GND

Power supply

Vee: +2.7 V to S.S V, GND: 0 V

05C1,05C2

Oscillation
resistor
clock

When CR oscillation is performed, a resistor must
be connected externally. When the pin input is an
external clock, it must be input to 05C1.

Signal

110

Input voltage to the booster, from which the liquid crystal
display drive voltage is generated.
Vci: 2.S V to 4.S V

Vci

VSOUT2

o

VS pinl
Booster
capacitance

Voltage input to the Vci pin is boosted twice and output
When the voltage is boosted three times, the same
capacity as that of C1-02 should be connected.

VSOUT3

o

VS pin

Voltage input to the Vci pin is boosted three times and
output.

Booster
capacitance

External capacitance should be connected when using
the booster.

C1/C2

TEST

Test pin. Should be wired to ground.

HITACHI

343

HD66710
Function Description
By the register selector (RS) signal, these two
registers can be selected (table 2).

Registers
The HD66710 has two 8-bit registers, an
instruction register (IR) and a data register (DR).

Busy Flag (BF)

The IR stores instruction codes, such as display
clear and cursor shift, and address infonnation for
the display data RAM (DD RAM), the character
generator RAM (CG RAM), and the segment
RAM (SEG RAM). The MPU can only write to
IR, and cannot be read from.

When the busy flag is I, the HD66710 is in the
internal opemtion mode, and the next instruction
will not be accepted. When RS 0 and R/W 1
(table 2), the busy flag is output from DB7• The
next instruction must be written after ensuring that
the busy flag is O.

The DR temporarily stores data to be written into
DD RAM, CG RAM, or SEG RAM. Data written
into the DR from the MPU is automatically written
into DD RAM, CG RAM, or SEG RAM by an
internal opemtion. The DR is also used for data
storage when reading data from DD RAM,
CG RAM, or SEG RAM. When address information is written into the IR, data is read and then
stored into the DR from DD RAM, CG RAM, or
SEG RAM by an internal operation. Data tmnsfer
between the MPU is then completed when the
MPU reads the DR. After the read, data in DD
RAM, CG RAM, or SEGRAM at the next address
is sent to the DR for the next read from the MPU.

Address Counter (AC)

=

The address counter (AC) assigns addresses to
DD RAM, CG RAM, or SEG RAM. When an
address of an instruction is written into the IR, the
address information is sent from the IR to the AC.
Selection of DD RAM, CG RAM, and SEG RAM
is also detennined concurrently by the instruction.
After writing into (reading from) DD RAM.
CG RAM, or SEG RAM, the AC is automatically
incremented by 1 (decremented by I). The AC
contents are then output to DBo to DB6 when
RS = 0 and R/W = 1 (table 2).

Table 2 Register Selection
RS

RIW

Operation

0

0

IR write as an internal operation (display clear, etc.)

0

1

Read busy flag (DB7 ) and address counter (DBo to DBs)

1

0

DR write as an internal operation (DR to DO RAM, CG RAM, or SEGRAM)

1

DR read as an internal operation (DO RAM, CG RAM, or SEGRAM to DR)

344

=

HITACHI

HD66710
Display Data RAM (DD RAM)

When the display shift operation is
performed, the DD RAM address shifts.
See figure 3.

Display data RAM (DD RAM) stores display data
represented in 8-bit character codes. Its· capacity is
80 x 8 bits, or 80 characters. The area in display
data RAM (DD RAM) that is not used for display
can be used as general data RAM. See figure 1 for
the relationships between DD RAM addresses and
positions on the liquid crystal display.

-

The DD RAM address (ADD) is set in the address
counter (AC) as hexadecimal.
•

I-line display (N = 0) (figure 2)
-

When a display shift operation is
performed, the DD RAM address shifts.
See figure 4.

Case 1: When there are fewer than 80
display characters, the display begins at the
head position. For example, if using only
the HD66710, 16 characters are displayed.
See figure 3.

High order

~ bits

Low order
bits----l

-I-

Case 2: Figure 4 shows the case where the
EXT pin is fixed high, and the HD66710
and the 4O-output extension driver are used
to extend the number of display characters.
In this case, the start address from COM9
to COM16 of the LCD-II/F8 is OAH.
To display 24 characters, addresses starting
at SEG 11 should be used.

~~xadeCimal) IAcsIACSIAC4IA9AC2IAC1IAcol

Example: DD RAM address 4E
I

I 0 I 0 I

0

Figure I DD RAM Address

Display position
(digit)

~c?ct~:~

1

2

3

4

5

79

80

I 00 I 01 I 021 031 041· . . . . . . . . . . . . . . . .. 14E 14F I

(hexadecimal)

Figure 2 I-Line Display

HITACHI

345

HD66710

1 2 3 4 5 6 7 8

910111213141516...

Display position

COM1 to 8

-++++++SI08lo71108IOBHOBloclooloeIOFI=

COM1 to 8

-1011021oo104105108lo7108IIOBHoBloclooloeIOFI10~

COM9 to 16 (Left shift display)

COM1 to 8

-14FlooI01102103104105108110710810B10A10BIoclooloer-

COM9 to 16 (Right shift display)

COM9 to 16
~ DRAM address

1 2 3 4 5 6 7 8

910111213141516

Figure 3 I-line by 16-Character Display Example

1 2 3 4 5 6 7 8 9 101112
oo
e-H++++eJ
COM1108-t I01
LCD-II/F8
Extension
SEG1 to 35
driver (1)
Seg11025

1++++

1314151617 18192021222324

~

Display position

(ocloolo++.Hu H++++7~ 10 16
LCD-II/F8
Extension
DDRAM address
SEG11 to 35
driver (1)
(SEG1 to 10: skip) Seg1 to 35

1 2 34 5 6 7 8 9101112 1314151617 18192021222324
COM1 to8++++I05loeI07H+++Blocl looIo+++H+++++++- COM9to 16 (Left shift display)

Figure 4 I-line by 24-Cbaracter Display Example

346

HITACHI

HD66710
•

2-line display (N = I, and NW =0)
-

Case 1: The first line is displayed from
COM! to COM16, and the second line is
displayed from COM17 to C0M32. Care is
required because the end address of the
fll'St line and the start address of the second

1 2 3 4 5 6 7 a

line are not consecutive. For example, the
case is shown in figure 6 where 16 x 2-line
display is performed using theHD66710.
When a display shift operation is
performed, the DD RAM address shifts.
See figure 5.

910111213141516...

-++ll o++++eH lo+++aloclooIOEIOFrCOM17 to 24 -++114+++++7114+++++014EI4FrCOM1 toa

Display position
COM9to 16
COM25 to 32

~ DDRAM address

-10+++++++l8llo++aloc looI0EIoFll0r- COM9 to 16 (Left shift display)
COM17 to 24 -141142143I44H48147148114++al4C14014EI4FI501- COM25 to 32
COM1 to a -+++110++++16II07I08I0910AIoal oc looI0E1- COM9 to 16 (Right shift display)
COM17 to 24 -187H4114214314414SI481147H4++al4C14014E1- COM25 to 32
COM1 to a

Figure 52-line by 16·Cbaracter Display Example

HITACHI

347

HD66710
-

Case 2: Figure 6 shows the case where the
EXT pin is fIXed to high, the HD66710 and
the 40-output extension driver are used to
extend the number of display characters.
In this case, the start address from COM9
to COM16 of the HD66710 is OAH, and
that from COM25 to COM32 of the

1234567

89101112

HD66710 is 4AH. To display 24 characters, the addresses starting at SEG 11
should be used.
When a display shift operation is performed, the DD RAM address shifts. See
figure 6.

1314151617 18192021222324 ........__Oisplayposition

to.,OOIO++3H I "Ho7Ioa1oe/oAloeJ
foclooloeloFI,oHul,zl,++5I,eH=
COM9 to COM16
,
. ~
" ,
, ~ OORAM address
LCO-IVF8
Extension
LCO-IVF8
Extension
SEGl to SEG35 driver (1)
SEGll to SEG35 driVer (1)

COMl
COM8,

05 06

Segl to Seg25 (SEGl to SEG10; Segl to 59g35
skip)

1 234 5 6 7

89101112

1314151617 18192021222324

.+ 1+++Ho7HoaIo++a\ocl 1++++ H,+++++++- ~~~6to
H++++1H+++ H+++++++- COM~~

~~!
to
OM
~OM!~ to., ++++++7

COM

to

Figure 6 2-Line by 24 Character Display Example

348

HITACHI

(Left shift display)

HD66710
•

4-line display (NW = I)
-

Case I: The first line is displayed from
COMI to COM8, the second line is
displayed from COM9 to COMI6, the
third line is displayed from COMI7 to
COM24, and the fourth line is displayed
from COM25 to COM32. Care is required

because the DD RAM addresses of each
line are not consecutive. For example, the
case is shown in figure 7 where 8 x 4-line
display is performed using the HD66710.
When a display shift operation is
performed, the DD RAM address shifts.
See figure 7.

1 2 3 4 5 6 7 8"
Display position
COM1 t08Ioolo1102I03H06I06lo71 ~
COM9t016120121122I23H251261271 _ _
DDRAM address
COM17t024140141142143H451461471--COM25t032160H62I63I641651661671"'---

12345678
COM1 t08 IOll02I03H05I06I,081
COM9 to 161211221 ~31241251261271281
(Left shift display)
COM17 to 241411421431441451461471481
COM25 to 32 1611621631641651661671681

12345678

[~lool~I02I03I~I06I061

I33 H21 I22H 24H26 1 . ..
1531401411421431441451461 (Right shift display)
1~1601~1621631641651661

Figure 7 4-Line Display

HITACHI

349

HD66710
-

Case 2: The case is shown in figure where
the EXT pin is fixed high, and the
HD66710 and the 40-output extension
driver are used to extend the number of
display characters.

When a display shift operation is
performed, the DD RAM address shifts.
See figure 8.

DDRAM address
COM17 to 24
COM25to 32
LCD-II/F8

Extension driver (1)

Extension driver (2)

1 2 3 4 5 6 7 8 91011121314151617181920

113 i00i 011 ++H osl +++AI OBlocloo10EIOFll01111121
133120121Iaal23la4125125I27H +++++EI 2F I30131I ul
153140I·ll++I.,I·eH+++BI+ol·EI4Flsolellu!
173Hellealeaje'Heele++++BleclsoleEH70171H
(Display shift left)

(Display shift right)

Figure 8 4-Line by 20·Character Display Example

350

HITACHI

HD66710
Character Generator ROM (CG ROM)

SEG RAM data is stored in eight bits. The lower
six bits control the display of each segment, and
the upper two bits control segment blinking.

The character generator ROM generates 5 x 8 dot
character patterns from 8-bit character codes
(table 3). It can generate 240 5 x 8 dot character
patterns. User-defined character patterns are also
available using a mask-programmed ROM.

Modifying Character Patterns

Character Generator RAM (CG RAM)

The following operations correspond to the
numbers listed in figure 9:

The character generator RAM allows the user to
redefine the character patterns. In the case of 5 x 8
characters, up to eight may be redefined.

1. Determine the correspondence between
character codes and character patterns.

Write the character codes at the addresses shown
as the left column of table 3 to show the character
patterns stored in CG RAM.
See table 5 for the relationship between CG RAM
addresses and data and display patterns.

Segment RAM (SEG RAM)
The segment RAM (SEG RAM) is used to enable
control of segments such as an icon and a mark by
the user program.
For a I-line display, SEG RAM is read from the
COMI7 output, and as for 2- or 4-line displays, it
is from the COM33 output, to performs
40-segment display.

Character pattern development procedure

2. Create a listing indicating the correspondence
between EPROM addresses and data.
3. Program the character patterns into an
EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing of the EPROM is
performed at Hitachi to create a character
pattern listing, which is sent to the user.
6. If there are no problems within the character
pattern listing, a trial LSI is created at Hitachi
and samples are sent to the user for evaluation.
When it is confirmed by the user that the
character patterns are correctly written, mass
production of the LSI will proceed at Hitachi.

As shown in table 6, bits in SEG RAM
corresponding to segments to be displayed are
directly set by the MPU, regardless of the contents
of DD RAM and CG RAM.

HITACHI

351

HD66710
Hitachi

User

"--'--~~~

m

HD6671 0

24 x 2·line display
SEG1SEQ35

SEG1SEG40

SEGl-5EG40

L----I
L -_ _-I

M
D

L===~CL2
Cll

SeglSeg35I-_ _ _...J

extension driver

Figure 23 HD66710 and the Extension Driver Connection

HITACHI

379

HD66710
When using one HD66710, the start address of
COM9-COM16/COM25-COM33 is calculated by
adding 8 to the start address of COM9-COM16
C0M25-COM32. When extending the address,

the start address is calculated by adding A(lO)
to COM9-COM16/COM25 to COM32. The
relationship betweenmodes and display start
addresses is shown below.

Table 13 Display Start Address in Each Mode
Number of Lines
1-Llne Mode

2-Llne Mode

4-Llne Mode

Output

EXT Low

EXT High

EXT Low

EXT High

EXT Low/High

COM1-COM8

DOO±1

DOO±1

DOO±1

DOO±1

DOO±1

COM9-COM16

D08±1

DOA±1

D08±1

DOA±1

D20±1

D40±1

D40±1

D40±1

D48±1

D4A±1

D60±1

SOO

SOO

Soo

COM17-COM24
COM2S-COM32
COM17
COM33

SOO

SOO

Notes: 1. When an EXT pin is low, the extension driver is not used; otherwise, the extension driver is
used.
2. D"" is the start address of display data RAM (DDRAM) for each display line.
3. S"" is the start address of segment RAM (SEGRAM).
4. ±1 following D"" indicates increment or decrement at display shift.

380

HITACHI

HD66710

a) 5-dot font width: 20 x 2-line display

HD6671 0
SEG1-5EG35

HD66710
Extension
SEG1-5EG35 driver (1)
Seg1-5eg15

Extension
driver (1)
Seg1-59g15

b) 6-dot font width: 20 x 2-line display
1 2 3 4 5 6

COM1-COM8
COM17--COM24

7 8 910

111213141516 17181920

-++H++'H06H08H Ho++++H,ol"H+- COM~COM16
+++I++.H+++.I H·sl++el·FH·++++-

COM25-COM32

..

f'~

" "

HD66710
SEG1-5EG36

Extension
driver (1)
Seg2-Seg25
(Seg1 is
skipped)

HD66710
Extension
SEG1-5EG36 driver (1)
Seg2-59g25
(Seg1 is skipped)

c) 5-dot font width: 24 x 2-line display
1314151617 18192021222324

COM1--COM8
COM 17--COM24

1=t==!=*=*=l==+==II=t==!=*=9=l

001 oel OFI H+++++++
H+el.FI"H.,H.+++++
"
,
loci

~~:!:::!::::J~-.:!;::::::J,
HD66710
SEG1-5EG35

Extension
driver (1)
Seg1-59g15

'0

HD66710
SEG11-5EG35
(SEG1-5EG10
are skipped)

COM9--COM 16
COM25-COM32

Extension
driver (1)
Seg1-59g35

d) 6-dot font width: 24 x 2-line display
123456

COM1-COM8
COM17-COM24

789101112

13141516 1718192021222324

++++++'H08lo /oa1ooHosllocI00IoeloFI H++31 1,+++ COM~M16
++++++.H" .. I.++++sll.++eH 1++++++++
7

14

COM25-COM32

"

"",

HD66710
SEG1-5EG36

Extension
driver (1)
Seg2-5eg37
(SEG1 is
skipped)

HD66710
Extension
SEG13-SEG36 driver (1)
(SEG1-5EG12 Seg2-5eg40
are skipped)
(SEG1 is
skipped)

"--/

Extension
driver (2)
Segl-5eg9

Figure 24 Correspondence between the Display Position at Extension Display and
the DDRAM Address

HITACHI

381

HD66710

e) 5-dot font width: 20 x 4-line display
1 2 3 4 5 6 7
COM1-COM8
COM9-COM16
COM17-COM24
COM25-COM32

8 91011121314151617181920

,001 0110210310410sI00 H07I08I09HoBl oc looIOEH 101111121131
,2012112212312++6 H2712sl2912AI2BI2CI2D12EI2F1soi61 1621631
,40141 14++++6 H4714+++BI4C14014EI4FI501 S1 1521631
, 60161162IS316416sl66 HS++++Bl sc lsoISEI6FI70171 1721731
...

/

...

~

A

Extension
driver (1)
Seg1-5eg40

HD66710
SEG1-SEG35

Extension
driver (2)
Seg1-5eg25

f) 6-dot font width: 20 x 4-line display

HD66710
SEG1-5EG36

Extension
Extension
driver (1)
Seg2-5eg40
(Seg1 is skipped)

Figure 24 Correspondence between the Display Position at Extension Display and
the DDRAM Address (cont)

382

HITACHI

HD66710
Interface to Liquid Crystal Display
Set the extended driver interface, the number of
display lines, and the font width with the EXT

pin, an extended register NW, and the FW bit,
respectively. The relationship between the EXT
pin, register set value, and the display lines are
given below.

Table 14 Relationship between EXT, Register Setting, and Display Lines
No of No. of
Line. Charactrer.

2

4

Note: -

EXT
Pin

6-Oot Font
5-Oot Font
Extended
EXT Extended
N RE NW FW Duty
Driver
N RE NW FW Pin Driver

16

L

0

0

0

0

H

0

0

20

H

0

0

0

0

H

0

0

1117

24

H

0

0

0

0

H

2

0

0

1/17

16

L

1

0

0

0

H

1

0

1/33

0

0

H

1

1

0

1133

0

0

H

2

1

0

H

0

H

2

0

H

3

20

H

0

24

H

0

16

H

1

20

H

2

24

H

2

...
...
...

0

...
...
...

1/17

1133
1133
1133
1133

means not required.

HITACHI

383

HD66710
Example of 5-dot font width connection

HD6671 0

1

..........................................

8

9

..---- .......... ---------

16

COllI
COM2

8811:
COMS

COM8
COM?
COlIS
COll17

SEGI
BEG2
SEGS
SEG4
SEGS
BEGS
SEG.a

~

EXT

COMS
COlll0
COMn
COM12
COM13
COM1_
COM15
COM16

a) 16 x 1-line + 40-segment display (5-dot font, 1/17 duty)

HD66710

1

..................

8

9 •••••••••••••••••• 16

COllI
COM2
COMs

COM4

COMS

COMe

COM7
COMe
COll17
COll18
COllIe
COIl20
COll21
COIl22
COIl23
COIl24
COIl33
BEGI
SEG2

~81

SEGS
SEGS
SEG.a
COMS

88tllf
COM12
COM13
COMI.
COllIS
COM16
COM25
COMa

COM27

["" EXT

COMa
COM29
COMSO
COM31
COM32

b) 16 x 2-line + 40-segment display (5-dotfont, 1133 duty)

Figure 2S Liquid Crystal Display and HD66710 Connections (Single-Chip Operation)

384

HITACHI

HD66710

........"

a)

~x

2-llno + 4O-sagmall1 display (5-do1lon~ 1133 duty)

H~I~lil=c_Il l1- !-!-·1I31 -!-!- 1·171 1 181 -!- !- !-I-1 121 1 '131-1-!- !- 1I1 71 1 '181- !-!- I-I~I -I- !- !-1 241 1 1 1 1!" lfith
=
.....
CQNS

88ft.

CDM17

COM1'
COM1'

C.....

....,

iE~
....
1-_ _-'

. ."Iiiiilllllillilll~~~~[~

SECI1!
SE01'

........
=11

.....
.....
~

.....

OOM1D
COM11

COM1I

caM"
caM"
caM"
c""'.

~

L-

iii

-.
EXT

8=
COMII

Extension

.........
..........."""

b) 24 x 2-lino + 4o-segmant dillplay (5-dot Io~ 1133 duty)

Figure 26 Liquid Crystal Display and HD66710 Connections (with the Extended Driver)

HITACHI

385

HD66710
1 .. _--------

HD6671 0

7

8

--------- -- - - - -- - --

15

16 ------------.

20

COMI

COM2
COt.\3
COM4
COMS
COMS
COM7
COMS
COMII
COM10
COMII
COM12
COM13
COM14
C0M23
COM16
COM17
COM18
COM19
COM2O
C0M21
C0M22
C0M23
C0M24
C0M25
C0M26
C0M27
C0M28
COM2G
COM3O
C0M31
C0M32
COM33

v

L

EXT

SEGI
SEG2
SEG3
SEG4
SEGS
SEG31
SEG32
SEG33
SEG34
SEG3S

Extension
driver
(1)

-

A

•

===-

SEGI
SEG2

~~~

SEGS

SEG36
SEG37
SEG38
SEG38
SEG40

SEGI

E~tension ~~~
dnver
SEG4
(2)
SEGS
SEG21
SEG22
SEG23
SEG24
SEG25

0) 20 x 4-line + 40-segment display (5-dot font, 1133 duty)

Figure 26 Liquid Crystal Display and HD66710 Connections (with the Extended Driver) (cont)

386

HITACHI

HD66710
Example of 6-dot font width connection
1

H066710

2 --------

7

6

8

--------

12

COM'

COIoI2

add.... _

Note: The OORAM
61h and 7th dlgila Is

nol contlguo".

COM3

=
COM<
COM7

couo

roM'7
roM,.
roM'.
roM..
roM"
roM..
roM..
roM..
roM»

SEa,

..'"

SEC32
SEQ3
SEGS

SEClO

SfG7

SEGB

SEGO

SE010

SEa,.
OOMO

roM'.
roM"

,COM12

roM"
roM"
COM"
COM'.
COM25
COM,.

,r

EXT

roM27
roM'"
roM..
roM"
roM.,
roM..

a) 12.2-11118 + 36-segment display (6-da1 font, 1133 duty)

1 --------- 6

H066710

7-------

10

11 --------

16

17 ------ 20

co."
COIoI2
~

=
COM5

COMB

roM"
roM'.
roM'.

COM. .

roM"
roM"
roM..
roM..

00''''
SEa,
SE<12

SEG>

SE'"

~=

SEG31

SEa..

SEa",
SEa..
SEa,.
SEa..
COMO

roM'.

COM"
COM,.

roM'"
roM"
roM"
roM,.

=
COM25

\cc

'--

roM..

EXT

COM..

roM,.
roM.,
roM,.

SEa..
SEa..
b) 20. 2-11118 + 36-segment display (6-dol font, 1133 duty)

Figure 27 Liquid Crystal Display and 8D66710 Connections (6-Dot Font Width)

HITACHI

387

HD66710
Instruction and Display Correspondence
8-bit operation, 16-digit x I-line display with
internal reset
Refer to table 16 for an example of an
16-digit x I-line display in 8-bit operation. The
HD66710 functions must be set by the
function set instruction prior to the display.
Since the display data RAM can store data for
80 characters, a character unit scroll can be
performed by a display shift instruction. A dot
unit smooth scroll can also be performed by a
horizontal scroll instruction. Since data of
display RAM (DDRAM) is not changed by a
display shift instruction, the display can be
returned to the first set display when the return
home operation.is performed.
•

4-bit operation, 16-digit x I-line display with
internal reset
The program must set all functions prior to the
4-bit operation (table 16). When the power is
turned on, 8-bit operation is automatically
selected and the first write is performed as an
8-bit operation. Since DBo to DB3 are not
connected, a rewrite is then required. However,
since one operation is completed in two
accesses for 4-bit operation, a rewrite is
needed to set the functions (see table 16).
Thus, DB4 to DB7 of the function set
instruction is written twice.
8-bit operation, 16-digit x 2-line display with
internal reset
For a 2-line display, the cursor automatically
moves from the first to the second line after
the 40th digit of the frrst line has been written.

388

Thus, if there are only 16 characters in the flTSt
line, the DD RAM address must be again set
after the 16th character is completed. (See
table 17.)
The display shift is performed for the flTSt and
second lines. If the shift is repeated, the
display of the second line will not move to the
first line. The same display will only shift
within its own line for the number of times the
shift is repeated.
8-bit operation, 8-digit x 4-line display with
internal reset
The RE bit must be set by the function set
instruction and then the NW bit must be set by
an extension function set instruction. In this
case, 4-line display is always performed
regardless of the N bit setting. (Table 18.)
In a 4-line display, the cursor automatically
moves from the first to the second line after
the 20th digit of the frrst line has been written.
Thus, if there are only 8 characters in the first
line, the DD RAM address must be set
again after the 8th character is completed.
Display shifts are performed on all lines
simultaneously.
Note: When using the internal reset, the electrical
characteristics in the Power Supply
Conditions Using Internal Reset Circuit
table must be satisfied. If not, the HD66710
must be initialized by instructions. See the
section, Initializing by Instruction.

HITACHI

HD66710
Table 15 8·Bit Operation, 16·Digit x I·Line Display Example with Internal Reset
Step
No. RS RIW~

2

3

4

5

6

Instruction
De

Ds

D4

D3

D2

D1

Do

Display

Operation

Power supply on (the HD66710 is initialized by
the internal reset circuit)

Initialized. No display.

Function set
0
0
0

...

Sets to 8-bit operation and
selects 1-line display.
Bit 2 must always be cleared.

0

Turns on display and cursor.
Entire display is in space mode
because of initialization.

0

0

Display on/off control
0
0
0
0
0

0

Entry mode set
0
0
0
0

0

0

0

...

0

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the RAM.
Display is 'not shifted.

0

Write data to CG RAM/DO RAM
1
0
0
1
0
0
1

0

0

Write data to CG RAMIDD RAM
1
0
0
1
0
0
1

0

0

Write data to CG RAM/DO RAM
0
0
1
0
0
1
1

0

0

0

Writes H. DO RAM has
already been selected by
initialization when the power
was turned on.

IH

Writes I.

I HI

7

8

9
10

Entry mode set
0
0
0
0

0

0

I HITACHL
I HITACHI

0

Write data to CG RAMIDD RAM
0
1
0
0
0
1
0

0

0

0

IITACHI

HITACHI
~----

--

Writes I.
Sets mode to shift display at
the time of write.
Writes a space.

389

-------------~---------

HD66710
Thble15 8-Bit Operation, 16-Digit x I-Line Display Example with Internal Reset (cont)
Instruction

Step
No.

RS RIW~

11

Write data to CG RAMIDD RAM
1 0 0 1 0 0 1

Da

Ds

Dc

D3

Dz

D,

Do

Display
ITACHIM_

0

Operation
WritesM.

12

13

Write data to CG RAMIDD RAM
1 0 0 1 0 0 1

14

Cursor or display shift
0
0
0
0
0

0

0

*

*

IMICROKO

Cursor or display shift
0
0
0
0
0

0

0

*

*

IMICROKO

Write data toCG RAMIDD RAM
1 0 0 1 0 0 0

0

15
16
17

IMICROKO

Cursor or display shift
0
0
0
0

0
18
19

Cursor or display shift
0
0 0 0 0

0

Write data to CG RAM/DO RAM
1 0 0 1 0 0 1

*

*

*

*

Shifts only the cursor position
to the left.
Shifts only the cursor position

to the left.

IICROCQ

Writes Cover K.
The display moves to the left.

IMICR~

Shifts the display and cursor
position to the right.

IMICROCO_

Shifts the display and cursor
position to the right.

IICROCOM=

0

WritesO.

WritesM.

20

21

390

Return home
0
0
0 0

0

0

0

0

0

I HITACHI

HITACHI

Returns both display and cursor
to the original position
(address 0).

HD66710
Table 16 4·Bit Operation, 16.Digit x I·Line Display Example with Internal Reset
Instruction
SWp ____~-----------------------No. RS RIW ~ Ds Ds D4 D3 Dz D, Do Display

2

3

4

5

6

Operation

Power supply on (the HD66710 is initialized by
the internal reset circuit)

Initialized. No display.
Sets to 4-bit operation.
Clear bit 2. In this case,
operation is handled as S bits
by initialization.

o

Function set
0
0

0

o

Function set
0
0
0
0
0
0

0
0

0

...

...

Display on/off control
0
0
0
0
0
0
0
1
1
1

0
0

Entry mode set
0
0
0
0
0
0
1
0

0
0

0
1

Sets 4-bit operation and selects
1-line display. Clear bit 2.
4-bit operation starts from
this step.
Turns on display and cursor.
Entire display is in space mode
because of initialization.
Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CG RAM.
Display is not shifted.

Write data to CG RAM/DO RAM
100 1 0
0
101
000

Writes H.
DDRAM has already been
selected by initialization.

Note: The control is the same as for S-bit operation beyond step #6.

HITACHI

391

HD66710
Table 17 8·Bit Operation, lti.Digit x 2-Line Display Example with Internal Reset
Instruction

Step

No.

2

3

4

5

RS RIW~

De De D. 0 3

O2 0, Do

Display

Operation

Power supply on (the HD66710 is initialized by
the internal reset circuit)

Initialized. No display.

Function set
0 0
0

1

Sets to 8-bit operation and
selects 1-line display.
Clear bit 2.

1=

Turns on display and cursor.
All display is in space mode
because of initialization.

0

0

Display on/off control
0 0
0 0
0

0

Entry mode set
0
0
0 0

0

0

• •
0

0

0

Write data to CG RAMIDD RAM
0
1 0
1
1 0 0

0

0

Write data to CG RAMIDD RAM
1 0
0
1 0 0
1

0

0

Set DD RAM address
0 0
1 1 0

0

0

0

1

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the RAM.
Display is not shifted.

IH

Writes H. DD RAM has
already been selected by
initialization when the power
was turned on.

6

7

8

392

0

0

1HITACHI

0

I~ITACHI

HITACHI

Writes I.

Sets RAM address so that the
cursor is positioned at the head
of the second line.

HD66710
Table 17 8-Bit Operation, 16-Digit x 2-Line Display Example with Internal Reset (cont)
Step
No. RS RIWD7

9

Instruction
D6

D5

D4

D3

D2

Write data to CG RAM/DO RAM
0
0
1
0
1
1
0

D1

Do

0

Display

Operation

I~TACHI

Writes a space.

10

11

Write data to CG RAM/DO RAM
0
0
0
0
1
1
1

WritesO.

12

Entry rrlode set
0
0
0
0

Sets mode to shift display at
the time of write.

13

0

0

0

Write data to CG RAM/DO RAM
1
0
0
1
0
0
1

Writes M.

0

14

15

Return home
0
0
0
0

0

0

0

0

0

HITACHI

Returns both display and cursor
to the original position
(address 0).

393

HD66710
Table 18 8·Bit Operation, 8·Digit x 4·Line Display Example with Internal Reset
Step
No. RS RIW

Instruction

0., Ds Ds D4 D3 D2 D1

Do

Power supply on (the HD6671 0 is initialized by
the internal reset circuit)

2

3

4

5

6

7

a

394

Function set
0
0
0

0

4·line mode set
0
0
0
0

*

0

0

0

0

Function set
Clear extended register enable bit
0
0
0
0
0
1
1
0

*

0

*

*

Display onloff control
0
0
0
0
0

0

1

0

Entry mode set
0
0
0
0

0

0

0

0

Write data to CGRAMIDDRAM
0
1
0
0
1
1
0

0

0

0

Display

Operation

~
~
~
~
~
~
~

Initialized. No display.

HITACHI

a

Sets to bit operation and the
extended register enable bit.

Sets 4-li:1e display.

Clears the extended register
enable bit. Setting the N bit is
"don't care".

Turn on display and cursor.
Entire display is in space mode
because of initialization.

Set mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the RAM. Display is not
shifted.
Write H. DDRAM has already
been selected by initialization
when the power was turned on.

HD66710
Table 18 8·Bit Operation, 8.Digit x 4·Line Display Example with Internal Reset (coot)
Step _ _ _ _ _ _ _
_ _ _ _ _ _ _ __
Instruction
No.

RS RIW ~

9

Write data to CGRAMIODRAM
100
1
001

10

11

De

Ds

Set DO RAM address
00101

D4

o

Ds

D2 D1

Do

Display

Write I.
0

0

Sets RAM address so that the
cursor is positioned at the head
of the second line.

o o o o

Write data to CGRAMIODRAM
1 000
1
1
0

Operation

0

0

0

~

~

HITACHI

WriteO.

395

HD66710
Initializing by Instruction
If the power supply conditions for correctly

initialization by instructions becomes necessary.

operating the internal reset circuit are not met,

(

Power on

• Wait for more than 15 ms
after Vcc rises to 4.5 V
(Vcc =5 V)
• Wait for more than 40 ms
after Vcc rises to 2.7 V
(Vcc =3 V)

RS RfIN DSr DBe DBs DB4 DB:! DB:! DB1 DBa
0 0 0 0 1 1

• • • •

( I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS RflNDSr DBa DBs DB4 DB:! DB:! DB1 DBa
0
0
0
0
1 1

• • • •

( I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 100 liS

RS RfIN DSr DBe DBs DB4 DB:! DB:! DB1 DBa
0 0 0 0 1 1

• • • •

( I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See table 7.)
RS RfIN DSr DBa DBs DB4 DB:! DB:! DB1 DBa
0 0 0 0 1 1 N 0

Function set.

0
0
0

Display off

• •

0

0
0

0
0
0

0

0
0

0
0
0

0
0
0

~

1
0
0

0 0 0
0 0 1
1 liD S

Display clear
Entry mode set

Initialization ends

Figure 28 8-Bit Interface

396

HITACHI

HD66710

(

Power on

)

• Wait for more than 15 ms
after Vee rises to 4.5 V
(Vee=5V)
• Wait for more than 40 ms
after Vee rises to 2.7 V
(Vee=3V)

I

( ISF cannot be checked before this instruction.

AS PIlI D~ Dee DBs DB..
0 0 0 0 1 1

Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

( ISF cannot be checked before this instruction.

AS RlWD~ Dee DBs DB..
0 0 0 0 1 1

Function set (Interface is 8 bits long.)

Wait for more than 100 liS

AS RIW D~ Dee DBs DB..
0 0 0 0 1 1

AS RlWD~ DBe DBs DB..
0 0 0 0 1 0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0

N
0
1
0
0
0
0

0 1
0 *
0 0
0 0
0 0
0 0
0 0
1 110

I

( I SF cannot be checked before this instruction.
Function set (Interface is 8 bits iong.)

SF can be checked after the following instructions.
When SF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See table 7.)
Function set (4-bit mode).

0

•
0
0
0
1
0

S

Function set (4-bit mode, N specification).
Display off
Display clear
Entry mode set (lID, S specification)

Initialization ends

Figure 29 4·Bit Interface

HITACHI

397

HD66710
Horizontal Dot Scroll
Dot unit shifts are performed by setting the
horizontal dot scroll bit (HDS) when the extension
register is enabled (RE = 1). By combining this

with character unit display shift instructions.
smooth horizontal scrolling can be performed on a
6-dot font width display as shown below.

6-dot font width (FW = 1)

5·dot font width (FW = 0)
Noshiftperformed
Shift to the left by one dot
Shift to the left by two dolS
Shift to the left by three dolS
Shift to the left by four dolS

IIII
IIII
IIII
IIII
IIII

No shift performed

Shift to the left by one dot
Shift to the left by two dolS
Shift to the left by three dolS
Shift to the left by four dolS
Shift to the left by five dolS

Figure 30 Shift in 5· and 6·Dot Font Width
(1) Method of smooth scroll to the left

•

RS RIW DB7DB6DB5 D84DB3 DB2DBI 080

1I 01010I 011 lOLl N I. . 1• I Enable the extension register
21 0 I 0 11 . . . • I. • I • 1 Shift the whole display to the left by one dot
31 0 I 0

I

CPU Wait
1_

•

I. • I • I

Shift the whole display to the left by two dots

I. • I • I

Shift the whole display to the left by three dots

I. • I • I

Shift the whole display to the left by lour dots

CPU Wait

1.....

41 0 I 0

1_

•

CPU Wait

51 0 I 0

CPU Wait

610\ 0 1. . . . 1.\.1 .1
CPU Wait

71010 1PM .\ .1 .1 .1
81 0\ 0 0\ 0I 0\1 . . • 1• \
I

CPU Wait

Shift the whole display to the left by five dots"

I

Perform no shift
Shift the whole display to the left by one character'2

I

I
Notes: 1. When the Iont width is live (FW • 0). this step is Skipped.
2. The extended register enable bit (RE) is cleared.

Figure 31 Smooth Scroll to the Left
398

HITACHI

HD66710
(2) Method of smooth scroll to the right

RS RIW DB7 DBS DB5 DB4 DB3 DB2 DBI

coo

11010010101,,,·1·1

Shift the whole display to the right by one
characlBr -2

210100101,loLINII·I·1

Enable the extansion regislBr

.•,CPU Wait

31

o

I 0

41

o

10

I
• I

• I • I • I

Shift the whole display to the left by fivedols- 1

CPU Wait

-I

I

• 1• 1

5

Shift the whole display to the left by four dots

Shift the whole display to the left by three dots

61

o

I0

71

0

10

-CPU Wait

•I •I •I

Shift the whole display to the left by two dols

1
• 1

• 1

I

1• 1

Shift the whole display to the left by one dot

Perform no shift

Notas: ,. When the Iont width is five (FW = 0). this step is skipped.
2. The extended register enable bit (RE) is cleared.

Figure 31 Smooth Scroll to the Left (cont)

HITACHI

399

HD66710
Low Power Mode
When LP bit is land the EXT pin is low (without
an extended driver). the HD66710 operates in low
power mode. In I-line display mode. the HD66710
operates on a 4-division clock. and in 2-line or 4-line
display mode. it operates on 2-division clock.

RS

Extended register enable

So. instruction execution takes four times or twice
as long. Notice that in this mode. display shift and
scroll cannot be performed. Clear display shift
with the return home instruction. and the
horizontal scroll quantity.

RiW DB7

DBS DBS DB4 DB3 DB2 DB1 DBO

10 10 10 10 11 1DL 1N •

BE

10 1

Clear horizontal scroll quantity
HDS ..

"000·

Set a low power mode

RS

Return home

RiW DB7

DBS DBS DB4 DB3 DB2 DB1 DBO

1010101010101010.01
Note: In this operation. instruction execution time
takes four times or twice as long.

Reset a power mode

Return home

RS

RiW DB7 DBS

DBS DB4 DB3 DB2 DB1 DBO

1010101010101010.01
Figure 32 Low Power Mode Operation

400

HITACHI

HD66710
Absolute Maximum Ratings
Item

Symbol

Value

Unit

Power supply voltage (1)

Vee

-0.3 to +7.0

V

Power supply voltage (2)

Vec-Vs

-0.3 to + 15.0

V

Input voltage

Vt

-0.3 to Vee +0.3

V

Operating temperature

Topr

-20 to +75

·C

3

T8t2

-55 to +125

·C

4

Storage temperature

Note.-

1,2

Notes: If the LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limits is strongly recommended for normal
operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction
and cause poor reliability.
... Refer to the Electrical Characteristics Notes section following these tables.

DC Characteristics (Vee

=2.7 V to 5.5 V, Ta =-20°C to +75°C*3)

Symbol

Min

Max

Unit

Input high voltage (1)
(except OSC,)

V1H'

0.7Vee

Vee

V

6

Input low voltage (1)
(except OSC,)

V1L ,

-0.3

0. 2Vee

V

6

-0.3

0.6

Input high voltage (2)
(OSC,)

V1H2

0.7Vee

Vee

V

15

Input low voltage (2)
(OSC,)

V1L2

0.2Vee

V

15

Output high voltage (1)

VOH ,

Item

Typ

0.75Vee

Test Condition

Note.-

V

-IOH" 0.1 mA

7

V

101.. -0.1 mA

7

V

-IOH .. 0.04 mA

a
a

(0 0-07)
Output low voltage (1)

VOl.,

0.2Vee

(0 0-0 7)
Output high voltage (2)
(except 0 0-0 7)

VOH2

Output low voltage (2)

V0I..2

0.2Vee

V

101.. =0.04 mA

Driver on resistance
(COM)

ReOM

20

kn

±Id

=0.05 mA (COM)

13

Driver on resistance
(SEG)

RSEG

30

kO

±Id .. 0.05 mA (SEG)

13

9

O.aVee

(0 0-07)

110 leakage current

III

-1

Pull-up MOS current
(0 0-07, RS, RIW)

-Ip

10

Power supply current

1ST

LCD voltage

1

ItA

VIN" 0 to Vee

50

120

!-LA

Vee -3 V

TSO

TSO

mA

R, oscillation,
10,14
external clock
Vee =3V, fosc = 270 kHz

VLeD,

3.0

13.0

V

Vee-Vs, 1/5 bias

16

VLeD2

3.0

13.0

V

Vee-Vs, 1/4 bias

16

Note: ... Refer to the Electrical Characteristics Notes section following these tables.

HITACHI

401

HD66710
Booster Characteristics
Item

Symbol

Output voltage
(VSOUT2 pin)

VUP2

Output voltage
(V50UT3 pin)

VUP3

Input voltage

VCi

Min

Max

Unit

Test Condition

TBD

V

Vci " 4.S V, 10 Ta" 2SoC

TBD

V

Vci '"' 3 V, 10 " 0.3 rnA,
Ta =25°C

'iYP

4.5

2.5

Note.*

o.s rnA,

V

18
18
18

Note: • Refer to the Electrical Characteristics Notes section following these tables.

AC Characteristics (VCC

= 2.7 V to 5.5 V, Ta = -20°C to +75°C*3)

Clock Characteristics
Symbol Min

Item
External
clock
operation

Rt
oscillation

'iYP

Max

Unit Test Condition

Note.·
11

External clock frequency

fcp

125

270

410

kHz

External clock duty

Duty

45

50

55

%

External clock rise time

t rcp

0.2

J.Ls

External clock fall time

ttcp

0.2

J.LS

Clock oscillation frequency

fosc

350

kHz

190

270

Rt .. 75 kn,
Vee -3 V

Note: • Refer to the Electrical Characteristics Notes section following these tables.

402

HITACHI

12

HD66710
Bus Timing Characteristics (1) (Vee = 2.7 V to 4.5 V, Ta = -20°C to +75°C*3)
Write Operation
Hem

Symbol

Enable cycle time

Min

tcycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr. tEl

lYP

Max

Unit

Test CondHlon

ns

Figure 33

UnH

Test CondHlon

ns

Figure 34

25

Address set-up time (AS. RIW to E) tAS

60

Address hold time

tAH

20

Data set-up time

tosw

195

Data hold time

tH

10

Item

Symbol

Min

Enable cycle time

teycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr. tEl

Read Operation

lYP

Max

25

Address set-up time (AS. RIW to E) tAS

60

Address hold time

tAH

20

Data delay time

tOOR

Data hold time

tOHR

360
5

HITACHI

403

HD66710
Bus Timing Characteristics (2) (Vee

=4.5 V to 5.5 V, Ta =-20°C to +7soC*3)

Write Operation
Hem

Symbol

Min

Enable cycle time

tcycE

500

Enable pulse width (high level)

PWEH

230

Enable riselfall time

tEr. tEl

~p

Max

Unit

Test CondHlon

ns

Figure 33

Unit

Test CondHlon

ns

Figure 34

20

Address set-up time (RS. RIW to E) tAS
Address hold time
tAH

40

Data set-up time

tosw

60

Data hold time

tH

10

10

Read Operation
Hem

Symbol

Min

Enable pulse width (high level)

tcvcE
PWEH

500

Enable riselfall time

ler. tEl

Enable cycle time

20
40
10
160

tOOR

Data hold time

Max

230

Address set-up time (RS. RIW to E) tAS
Address hold time
tAH
Data delay time

~p

5

tDHR

Segment Extension Signal Timing (Vee

=2.7 V to 5.5 V, T a =-20°C to +7soC*3)

H.m

Clock pulse width

Symbol

Min

High level

tcWH

800

Low level

tcwL

800

Clock set-up time

tcsu

500

Data set-up time

tsu

300

Data hold time

IQH

300

M delay time

tOM

-1000

Clock riselfall time

~p

Max

Unit

Test CondHlon

ns

Figure 35

1000
TBD

let

Power Supply Conditions Using Internal Reset Circuit
H.m

Symbol

Min

Power supply rise time

tree

0.1

Power supply off time

tOFF

1

404

HITACHI

~p

Max

Unit

"'st CondHlon

10

ms

Figure 36

HD66710
Electrical Characteristics Notes
1.

All voltage values are referred to GND = 0 V. If the LSI is used above these absolute maximum
ratings, it may become permanently damaged. Using the LSI within the following electrical
characteristic limits is strongly recommended for normal operation. If these electrical characteristic
conditions are also exceeded, the LSI will malfunction and cause poor reliability.

2.

Vee ~ VI ~ V2 ~ V3 ~ V4 ~ VS must be maintained. In addition, if the SEG37!CLl, SEG38/CL2,
SEG39/D, and SEG40/M are used as extension driver interface signals (EXT = high), GND ~ VS
must be maintained.

3.

For die products, specified up to 7SoC.

4.

For die products, specified by the die shipment specification.

S.

The following four circuits are I/O pin configurations except for liquid crystal display output.
Input pin
Pin: E (MOS without pull-up)

Pins: RS,

RiW (MOS with pull-up)

Vee

I/O pin
Pins: DBo-DB7
(MOS with pull-up)

(input circuit)
PMOS
I--~----

Input enable

Vee

i-----?-- Output
H - - - / - - enable data

NMOS

6.

Applies to input pins and I/O pins, excluding the OSCl pin.

7.

Applies to I/O pins.

HITACHI

405

HD66710
8. Applies to output pins.
9. Current flowing through pull-up MOSs, excluding output drive MOSs.
10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive
current flows through the input circuit to the power supply. Th avoid this from happening, the input
level must be fixed high or low.
11. Applies only to external clock operation.
Th

Open

TI

0.7 Vee
0.5 Vee

08C2

0.3 Vee

trcp

trcp

Th

Duty. Th + TI x 100%

12. Applies only to the internal oscillator operation using oscillation resistor Re.

tt=

RI : 75 kO ± 2% (when Vee - 3 V to 4 V)
RI: 91 kO ± 2% (when Vee - 4V to 5 V)

08C1

RI

8ince the oscillation frequency varies depending on the 08C1 and
08C2 pin capacitance, the wiring length to these pins should be minimized.

08C2

Vee -5 V
500

500
\

400

400

\
)

----

¥

.Y.

---- --~

:
I

200

I
I
I
I

:
I

100

50

J
~

'" ----

(91)100

.typ.

(270)

200

100

150

RI (kO)

406

300

\

\

"

--_. ---~

50

'"

(75)

"'- ~r-

100

RI (kO)

HITACHI

150

HD6671()
13. ReoM is the resistance between the power supply pins (Vee, VI, V4, V5) and each common
signal pin (COM1 to COM33).
RSEG is the resistance between the power supply pins (Vee, V2, V3, V5) and each segment signal pin
(SEGl to SEG40).
14. The following graphs show the relationship between operation frequency and current consumption.

~

1
~

-1.
1.
1.
1.
1.

o.
o.
o.
o.
o.

Voo=4V

-1.8
1.6
1.4
E 1.2
1.0
~ 0.8
0.6
0.4
0.2

Voo=3V

<
V"
~

0

100

-

typo

200 300 400 500

105C or 1cp (kHz)

<

S
...

0.00

-

100

~

---

typo

200 300 400 500

1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.00

typo
100

200 300 400 500

105C or 1cp (kHz)

105C or 1cp (kHz)

15. Applies to the OSC1 pin.
16. Each COM and SEG output voltage is within ±O.15 V of the LCD voltage (Vee, VI, V2, V3, V4, V5)
when there is no load.
17. The TEST pin must be fixed to the ground, and the EXT or Vcc pin must also be connected to the
ground.
18. Booster characteristics test circuits are shown below.
Boosting twice

Boosting three times

Vee

Vee
Vcl~

Vci

C1

C1

C2

C2

V50UT21-r-_..,.10_I~

'V'HI
V'LI

V'HI
V'LI
tAS

Vv'L1

V'LI
PWEH

E

-

K

tAH

1/

-tEl

Vv:

V'HI '\
V'LI

V'HI
V'LI
04-tEr

)<

-

tAH

tH

tosw

,,'HI
V'LI

Valid data

V'HI
V'LI

K

V'HI
V'LI

)(

V'HI

'\.

tcycE

Figure 33 Write Operation

RS

=>~

V'HI
VILI
tAS

tAH

V'HI
PWEH

E

-

I

V'HI
V'LI

-

tAH
i+--tEI

V'HI
V'LI

1\
V'LI

~tEr

tOOR

)<

tOHR

VOHI
VOLI

Valid data
tcycE

Figure 34 Read Operation

HITACHI

VOHI
VOLI

K

HD66710

ell

o

M

Figure 35 Interface Timing with External Driver

Vee

tOFF·l
0.1 ms strcc S 10 ms

tOFF

~1

ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power
supply oscillations.
2. Specified at 4.5 V for standard voltage operation, and at 2.7 V for low voltage operation.
3. If the above electrical conditions are not satisfied, the internal reset circuit will not
operate normally. In this case, the lSI must be initialized by software. (Refer to the
Initializing by Instruction section.)

Figure 36 Power Supply Sequemce

410

HITACHI

HD66712(LCD-II/F12)-(Dot Matrix Liquid Crystal Display
Controller/Driver)
Description

-

The HD66712 dot-matrix liquid crystal display
controller and driver LSI displays alphanumerics,
numbers, and symbols. It can be configured to
drive a dot-matrix liquid crystal disptay under the
control of a serial or a 4- or 8-bit microprocessor.
Since all the functions such as display RAM,
character generator, and liquid crystal driver,
required for driving a dot-matrix liquid crystal
display are internally provided on one chip, a
minimum system can be interfaced with this
controller/driver.
A single HD66712 is capable of displaying a
single 24-character line, two 24-character lines, or
four 12-character lines.
The HD66712 software is upwardly compatible
with the LCDII (HD44780) which allows the user
to easily replace an LCD-II with an HD66712. In
addition, the HD66712 is equipped with functions
such as segment displays for icon marks, a 4-line
display mode, and a horizontal smooth scroll, and
thus supports various display forms. This achieves
various display forms. The HD66712 character
generator ROM is extended to generate 240 5 x 8
dot characters.

•
•
•

•
•

•
•
•

The low-voltage operation (2.7 V) of the
HD66712, combined with a low-power mode, is
suitable for any portable battery-driven product
requiring low power consumption.

Features
•
•
•

5 x 8 dot matrix possible
Clock-synchronized serial interface capability;
can interface with 4- or 8-bit MPU
Low-power operation support:

•

2.7 to 5.5 V (low voltage)
Wide liquid-crystal voltage range: 3.0 to
13.0 V max.
Booster for liquid crystal voltage
- Two/three times (13 V max.)
High-speed MPU bus interface
(2MHz at 5-V operation)
Extension driver interface
Character display and independent 6O-icon
mark display possible
Horizontal smooth scroll by 6-dot font width
display possible
80 x 8-bit display RAM (80 characters max.)
9,600-bit character generator ROM
- 240 characters (5 x 8 dot)
64 x 8-bit character generator RAM
- 8 characters (5 x 8 dot)
16 x 8-bit segment icon mark
- 96-segment icon mark
34-common x 6O-segment liquid crystal
display driver
Programmable duty cycle
(See list 1)
Software upwardly compatible with HD44780.
Wide range of instruction functions:
- Functions compatible with LCD-II:
Display clear, cursor home, display on/off,
cursor on/off, display character blink,
cursor shift, display shift
- Additional functions: Icon mark control, 4line display, horizontal smooth scroll, 6-dot
character width control, white-black
inverting blinking cursor.
Automatic reset circuit that initializes the
controller/driver after power on (standard
version only)
Internal oscillator with an external resistor

HITACHI

411

HD66712
Low power consumption
•

QFP 1420-128 pin, TCP-128 pin, bare-chip.

LIst 1 Programmable duty cyc~es

Number of
Lines
Duty Ratio
1

1/17

2

1/33

4

1/33

Numb,er of
Lines
Duty Ratio
1

1/17

2

1/33

4

1/33

412

S-dot font width
With Extension Driver
Single-chip Operation
Displayed
Displayed
Characters
Icons
Icons
Characters
One 24One
5280
60
character line
character line
Two 32Two 2460
80
character lines
character lines
Four 24Four 2080
60
character lines
character lines

6-dot, font width
Single-chip Operation
With Extension Driver
Displayed
Displayed
Characters
Icons
Characters
Icons
One 20One 5096
60
character line
character line
Two 20Two 3096
60
character lines
character lines
Four 10Four 2060
96
character lines
character lines

HITACHI

HD66712
LCD-ll Family Comparison
Item

LCD-II
(HD44780U)

LCD-IIIE20
(HD66702)

LCD-II/F8
(HD66710)

LCD-IIIF12
HD66712

Power supply voltage

2.7 Vt05.5 V

5 V ±10 %
(standard)
2.7 Vt05.5 V
(low voltage)

2.7 V to 5.5 V

2.7 Vto 5.5 V

Liquid crystal drive
voltage

3.0 to 11 V

3.0 Vto 7.0 V

3.0 to 13.0 V

3.0 to 13.0 V

Maximum display
digits per chip

8 characters
x2lines

20 characters
x 2 lines

16 characters x
2 lines/
8 characters x 4
lines

24 characters x
2 lines/
12 characters x 4
lines

Segment display

None

None

40 segments

60 segments

Display duty cycle

1/8, 1/11, and
1/16

1/8,1/11, and
1/16

1/17 and 1/33

1117 and 1/33

CGROM

9,920 bits
(2085 x 8 dot
characters and
325 x 10 dot
characters)

7,200 bits
(1605x7dot
characters and
325x10dot
characters)

9,600 bits
(2405 x 8 dot
characters)

9,600 bits
(2405 x 8 dot
characters)

CGRAM

64 bytes

64 bytes

64 bytes

64 bytes

DDRAM

80 bytes

80 bytes

80 bytes

80 bytes

SEGRAM

None

None

8 bytes

16 bytes

Segment signals

40

100

40

60

Common signals

16

16

33

34

Liquid crystal drive waveform

A

B

B

B

Bleeder resistor for LCD
power supply

External
(adjustable)

External
(adjustable)

External
(adjustable)

External
(adjustable)

Clock source

External resistor External resistor External resistor External resistor
or external clock or external clock or external clock or external clock

RI oscillation frequency
(frame frequency)

270 kHz ±30%
(59 to 110Hz for
1/8 and 1/16 duty
cycle; 43 to 80
Hz for 1/11 duty
cycle}

320 kHz ±30%
270 kHz ±30%
(70 to 130 Hz for (56 to 103 Hz for
1/8 and 1/16 duty 1/17 duty cycle;
cycle; 51 to 95
57 to 106 Hz for
Hz ·for 1/11 duty 1/33 duty cycle)
cycle}

270 kHz ±30%
(56 to 103 Hz for
1/17 duty cycle;
57 to 106 Hz for
1/33 duty cycle)

RI resistance

91 kn:5-V
operation;
75 kn:3-V
operation

68 kO: 5-V
operation·
56 kO: (3-V
operation)

91 kO: 5-V
operation;
75 kO:3-V
operation

HITACHI

91 kO: 5-V
operation;
75 kO: 3·V
operation

413

HD66712
LCD·U Family Comparison (cont)
LCD-II
(HD44780U)

LCD-II/E20
(HD66702)

LCD-II/Fa
(HD66710)

LCD-IIIF12
HD66712

Liquid crystal voltage
booster circuit

None

None

2-3 times stepup circuit

2-3 times stepup circuit

Extension driver control signal

Independent
control signal

Independent
control signal

Used in common Independent
with a driver
control signal
output pin

Reset function

Power on
automatic
reset

Power on
automatic
reset

Power on
automatic
reset

Instructions

LCD-II
(HD44780)

Fully compatible Upper
Upper compatible
with the LCD-II compatible with with the LCD-II
the LCD-II

Number of displayed
lines

1 or 2

1 or 2

1.2. or 4

1.2. or 4

Low power mode

None

. None

Available

Available

Item

Power on
automatic reset
or Reset input

Horizontal scroll

Character unit

Character unit

Dot unit

Dot unit

Bus interface

4 bitsl8 bits

4 bitsl8 bits

4 bitsl8 bits

Serial;
4 bitsl8 bits

CPU bus timing

2 MHz: 5-V
operation;
1 MHz: 3-V
operation

1 MHz

2 MHz:5-V
operation;
1 MHz: 3-V
operation

2 MHz: 5-V
operation;
1 MHz: 3-V
operation

Package

QFP-1420-80
LQFP-2020-144 QFP-1420-100 QFP-1420-128
80-pin bare chip 144-pin bare chip 100-pin bare chipTCP-128
128-pin bare chip

414

HITACHI

HD66712
HD66712 Block Diagram

OSCl

0SC2

EXT

Cll
CL2
M

REser

6O-b1
shit
register

Character
generator ROM

SogmentRAM
($GRAM)

(CGROM)
9.600byIos

l6bytoo

V1

112

V4

6().b~

IItch
clmult

Segment
signal
drIYor

CUreoranc::l
bllng

controtler

V5

HITACHI

415

HD66712
HD66712 Pin Arrangement

SEG44

SEG17

SEG45
SEG46
SEG47
SEG48
SEG49
SEGSO

SEG16
SEG15
SEG14
SEG13
SEG12
SEG11

SEG51

SEG10
SEG9
SEGS
SEG7
SEG6
SEGS

SEG52
SEG53
SEGM
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
COM9
COM10
COM11
COM12

SEG4
SEG3
SEG2
SEG1

LCO-II/F12

COMO
COM1
C0M2

(Top view)

COMa

COM13
COM14
COM15
COM16
COM25

C0M4
COMS
COMa

COM26
C0M27
COM28

COM17
COM18
COM19

COM7
COMB

COM2O

COM29
COM3O

COM21
COM22

COM31
COM32

COM23
COM24

COM33
Vee
0SC2
OSC1
CL1

416

V1

V2
~

HITACHI

V3
V4

~
ry
~

• O_• •

I:'

i"
!eo

~

Vee

OSC2

___

M_

0001

CL1_
CL2_

=

=

RESET" _

I

~

cdM9
SEG60

IM_
EXT_

.=

TEST_i
GNO_

RSlCS"_ .

J:

o~J:

-

~

.....

E/SCLK _
RW/sIO_~
OBOISOO_ 0
OB1 . . . en
0 B 2 _ <{I

0B3_ 3

0B4_ 3
0 B 5 _ "2.

OB6_ (;
OB7 I!Ii!II!!lIIII ::T
Vci_
C2 IiiIiiiaI
C1 tl
GNO ~
V50UT2
V50UT3
V5
V4
V3
V2
V1

•••

L

ff ===
p

~=

3=
3

" ====
g

::T

=== 88H~
SEGI

rmP7
c6M24

::=
o

~
~

.....:I

~

~

HD66712
HD66712 Pad Arrangement

IIl!lI SEG17

SEG

I!IDI
IiOO
!SID
mID

SEG16

mzJ
IlIlD

SEG12

SEG15
SEG14
SEG13
SEG11

[95J SEG10
Iij) SEG9

mID SEG8
~SEG7

[9]] SEG6
lmD SEG5

WID

SEG4

[8iiJ SEG3

rnz.J

SEG5
SEG
COM9

COM10
COMll
COM12

LCD-II/F12

am
I2iiJ
I2iJ

(Top view)

SEG2

[I!BJ SEGl

nm:J COMO
[SJ COMl

[iia] C0M2

!ii2J

COMa

COM13 ~

mn COM4

COM14 ~
COM15 I2!l

rn!!.l

COM5

I.Zm

C0M6

COM25

[ZID COM7
[llI COMB

COM27~

1m COM18

COM28~

[!!J COM19

COM16 ~

I2W
coM2612Z1

[lID

COM17

rml

COM30

cmJ
mIl

COMal
COM32

I32l

IZII

COM22

m;!]

I1QJ

COM33 @!I
Vee cmJ

~

COM23
C0M24

IBBl
IBZJ

Vl
V2

COM29

OSC2

418

cmJ

OSCl

mzJ

Cl1

[3jj]

COM20

~ COM21

[§ID V3
1]51 V4

HITACHI

HD66712
Pin ·Functions
Table 1 Pin Functional Description

Signal

Number
of pins

110

Device
Interfaced with

1M

1

I

RS/CS·

1

MPU

Selects registers during bus mode:
Low: Instruction register (write);
Busy flag, address counter (read)
High: Data register (write/read)
Acts as chip-select during serial mode:
Low: Select (access enable)
High: Not selected (access disable)

RW/SID 1

MPU

Selects read/write during bus mode;
Low: Write
High: Read
Inputs serial data during serial mode.

ElSCLK

MPU

Starts data readlwrite during bus mode;
Inputs (Receives) serial clock during serial mode.

Function
Selects interface mode with the MPU;
Low: Serial mode
High: 4-bitl8-bit bus mode
(Bus width is specified by instruction.)

DB4 to
DB7

4

110

MPU

Four high-order bidirectional tristate data bus pins. Used
for data transfer between the MPU and the HD66712.
DB7 can be used as a busy flag. Open these pins during
serial mode since these signals 'are not used.

DBl to
DB3

3

I/O

MPU

Three low order bidirectional tristate data bus pins.
Used for data transfer between the MPU and the
HD66712; Open these pins during'4-bit operation or
serial mode since they are not used.

DBO/
SOD

110
/0

MPU

The lowest bidirectional data bit (DBO) during a-bit bus
mode. Open these pins during 4-bit mode since they are
not used.
Outputs (transfers) serial data during serial mode. Open
this ~in if readins {transferl is not ~erformed.

COMoto 34
COM33

0

LCD

Common signals; those that are not used become nonselected waveforms. At 1117 duty rate, COMl to COM16
are used for character display, COMo and COM17 for
icon display, and COM18 to C0M33 become nonselected waveforms. At 1/33 duty rate, COMl to COM32
are used for character display, and COMo and COM33 for
icon display. Because two COM signals output the same
level simultaneously, apply them according to the wiring
pattern of the display device.

SEGl to 60
SEGso

0

LCD

Segment output signals

HITACHI

419

HD66712
Table 1 Pin Functional Description (cont)

Signal

Number
of pins 110

CL1

1

Device
Interfaced with

Function

0

Extension driver

When EXT - high. outputs the extension driver latch
pulse.

CL2

0

Extension driver

When EXT .. high. outputs the extension driver shift
clock.

0

0

Extension driver

When EXT .. high. outputs extension driver data; data
from the 61 st dot on is output.

M

0

Extension driver

When EXT .. high. outputs the extension driver AC
signal.
When EXT .. high. outputs the extension driver control
signal. When EXT - low. the signal becomes tristate
and can suppress consumption current.

EXT

V1 to Vs

5

Vcc/GNO

2

Power supply

OSClI'OSC2 2

Power supply for LCD drive
Vee -Vs .. 13 V (max)

Power supply

Vee: +5 V or +3 V. GNO: 0 V

Oscillation
resistor
clock

When crystal oscillation is performed. an external
resistor must be connected. When the pin input is an
external clock. it must be input to OSC1.
Inputs voltage to the booster to generate the liquid
crystal display drive Voltage. .
Vci:2.5 V to 4.5 V

Vci

VSOUT2

o

Vs pint
Booster
capacitance

Voltage input to the Vci pin is boosted twice and output.
When the voltage is boosted three times. the same
capacitance as that of C1-C2 should be connected here.

VSO!JT3

o

Vspin

Voltage input to the Vci pin is boosted three times and
output.

Booster
capacitance

External capacitance should be connected here when
using the booster.

C1tC2

2

RESET"

Reset pin. Initialized to "low".

TEST

Test pin. Should be wired to ground.

HITACHI

HD66712
Fuhction Description
System Interface

Busy Flag (UF)

The HD66712 has three types of system interfaces:
synchronized serial, 4-bit bus, and 8-bit bus. The
serial interface is selected by the 1M-pin, and the
4/8-bit bus interface is selected by the DL bit in
the instruction register.

When the busy flag is I, the HD66712 is in the
internal operation mode, and the next instruction
will not be accepted. When RS = 0 and R/W = 1
(table 2), the busy flag is output from DB7. The
next instruction must be written after ensuring that
the busy flag is O.

The HD66712 has two 8-bit registers: an
instruction register (IR) and a data register (DR).

Address Counter (AC)

The IR stores instruction codes, such as display
clear and cursor shift, and address information for
the display data RAM (DD RAM), the character
generator RAM (CG RAM), and the segment
RAM (SEG RAM). The MPU can only write to
IR, and cannot be read from.

The address counter (AC) assigns addresses to DD
RAM, CG RAM, or SEG RAM. When an address
of an instruction is written into the IR, the address
information is sent from the IR to the AC.
Selection of DD RAM, CG RAM, and SEG RAM
is also determined concurrently by the instruction.

The DR temporarily stores data to be written into
DD RAM, CG RAM, or SEG RAM. Data written
into the DR from the MPU is automatically written
into DD RAM, CG RAM, or SEG RAM by an
internal operation. The DR is also used for data
storage when reading data from DD RAM, CG
RAM, or SEG RAM. When address information
is written into the IR, data is read and then stored
into the DR from DD RAM, CG RAM or SEG
RAM by an internal operation. Data transfer
between the MPU is then completed when the
MPU reads the DR. After the read, data in DD
RAM, CG RAM, or SEG RAM at the next address
is sent to the DR for the next read from the MPU.

After writing into (reading from) DD RAM, CG
RAM, or SEG RAM, the AC is automatically
incremented by 1 (decremented by 1). The AC
contents are then output to DBo to DB6 when RS =
oand R/W = 1 (table 2).

These two registers can be selected by the regis tor
selector (RS) signal in the 4/8 bit bus interface,
and by the RS bit in start byte data in synchronized
serial interface (table 2).
Table 2 Resistor Selection

RS

RfW

Operation

o
o

o

IR write as an internal operation (display clear, etc.)
Read busy flag (OB7) and address counter (OBo to OB6)

o

DR write as an internal operation (DR to DO RAM, CG RAM, or SEGRAM)
DR read as an internal operation (DO RAM, CG RAM, or SEGRAM to DR)

HITACHI

421

8D66712
Display Data RAM (DD RAM)

Display data RAM (DD RAM) stores display data
represented in 8-bit character codes. Its capacity is
80 x 8 bits, or 80 characters. The area in display
data RAM (DD RAM) that is not used for display
can be used as general data RAM.

The relationship between DD RAM addresses and
positions on the liquid crystal display is described
and shown on the following pages for a variety of
cases.

The DD RAM address (ADD) is set in the address
counter (AC) as a hexadecimal number, as shown
in figure 1.

MSB

Example: DO RAM address 4E

LSB

AC IAcsIAC5fC4IAC3IAC2IAC1IAcol
Figure

422

o

0

DD RAM Address

HITACHI

0

HD66712
• I-line display (N =0, and NW =0)
-

Case I: When there are fewer than 80
display characters, the display begins at the
beginning of DD RAM. For example, when
24 5-dot font-width characters are displayed
using one HD66712. the display is generated
as shown in figure 2.
When a display shift is performed, the DD
RAM addresses shift as well as shown in the
figure.

When a display shift is performed. the DD
RAM addresses shift as well as shown in the
figure.
- Case 2: Figure 4 shows the case where the
EXT pin is fixed high and the HD66712 and
the 40-output extension driver are used to
display 24 6-dot font-width characters.
In this case, COM9 to COMl6 begins at
(OA)H.

When 20 6-dot font-width characters are
displayed using one HD66712, the display is
generated as shown in figure 3. Note that
COM9 to COMl6 begins at address (OA)H
in this case.20 characters are displayed.

When a display shift is performed, the DD
RAM addresses shift as well as shown in the
figure.

13141516171819 20212223

24~

Display position

locloDloeloFI'ol"I'21'31'4BI61'7~mv19 to 16
DDRAM address

Figure 2 l·line by 24-Character Display (S-dot font width)

Figure 3 I-line by 20-Character Display (6-dot font width)

HITACHI

423

HD66712
1 2 3 4 5 6 7 8 910

COM1 to 8-fH 1 111oel07EEJ
02 03 04 05

'ceD=1i1F12
SEG1 to SEG60

'

11121314151617181920

21222324...-

,

LCO-IiIFi 2
SEG1 to SEG60

I

\

,

~

ExtenSion dnver
SEG1 10 SEG24

Figure 4 I·line by 24·Character Display (6·dot font width)

424

Displayposition

1'08ElooloeloFH~EEJ-~~COM9to16

HITACHI

DDRAM address

HD66712
• 2-line display (N = I, and NW =0)
-

Case 1: The first line is displayed from
COMI to COM16, and the second line is
displayed from COM17 to C0M32. Note
that the last address of the fust line and the
first address of the second line are not
consecutive. Figure 5 shows an example
where a 5-dot font-width 24 x 2-line
display.is performed using one HD66712.

Here, COM9 to COM16 begins at (OC)H,
and COM25 to C0M32 at (4C)H. When a
display shift is performed, the DD RAM
addresses shift as shown. Figure 6 shows
an example where a 6-dot font-width 20 x
2-line display is performed using one
HD66712. COM9 to COM16 begins at
(OA)H, and C0M25 to C0M32 at (4A)H.

1 2 3 4 5 6 7 8 9 101112

~~- -ELo{~}I051 08 107 108loDIOAl ce locl
COM17-

(Left shift display)

"'41]42143H4514814714814D[4A14B~cl

COM24

gg:- .., 271 001 01 1021031041051081071081 og El
gg~~-"'8714014114214314414514814714814Dh
Figure 5 2-lme by 24- haracter Display (5-dot font width)

11121314151617181920...

Display poSition

EJ oeloc loola:IOFI 101"112[j-- COM9-COM16
El4BI4C14014E14FH51E[3-:

COM25-COM32
~ DDRAMaddress

Figure 6 2-line by 20-Character Display (6-dot font width)

HITACHI

425

HD66712
-

Case 2: Figure 7 shows the case where the
EXT pin is fIXed high and the HD66712 and the
40-output extension driver are used to extend
the number of display characters to 32 S-dot
font-width characters.

When a display shift is performed. the DD
RAM addresses shift as shown.

In this case. COM9 to COM16 begins at
(OC)H. and COM2S to C0M32 at (4C)H.

2526272829 303132 (Left shUt display)

Figure 7 2-Line by 32 Character Display (S-dot font width)

426

HITACHI

HD66712
• 4·line display (NW = 1)
When a display shift is performed, the DD

- Case 1: The first line is displayed from COMI
to COM8, the second line is displayed from
COM9 to COM16, the third line is displayed
from COM17 to COM24, and ~e fourth line is
displayed from C0M25 to COM32.
Note that the DD RAM addresses of each line
are not consecutive.
Figure 8 shows an example where a 12 x 4·line
display is performed using one HD66712.

RAM addresses shift as shown.

1 234 5 6 7 8 9 101112 . .
COM1 t08

I

ioo.I 01:02 10sHos 106103 OBI 09 IOA oel ~

COM17 to 24

120121]221231241251~12712BI29I2A~ ~
140141]421 4 4 sl4614+++fBl'--

COM25to32

16016116211641651636716B1691~ ~

COM9to 16

(Left shift display)

3+

1 2 3 4 5 6 7 B9 10 11 12
COM1108 101102103 Hosl oslo+~ 091OAloel 09
COM91016 121 122123124125126 127 I2BI 29 12A 12B12CI
COM111D 24 1411421431 ~ 451461471481491 ~14814~
COM25I032 1611621631~6516B16716B169IM lealecl

Display position

DDRAM address

(Right shift display)

1 2 3 4 5 6 7 8 9 10 11 12
113109°110210310410sl06107108HOAI
13312~ 21 122 123 1241 25126 127 128129 12A1
15314~ 411421431441451461471481491~1

1731~6116216316416516616716B169IMI

Figure 8 4·Line Display

_----HFTACHI

- ---------------

427

-----------------

----

HD66712
-

When a display shift is performed, the DD
RAM addresses shift as shown.

Case 2: Figure 9 shows the case where the
EXT pin is fixed high and the HD66712 and
the 4O-output extension driver are used to
extend the number of display characters.

1 2345878 9 10 11 12 13 14 15 16 17 1819 20 _____ Display position
COMl108 -Ioo! O~ 02!03! 04! 051081 071 08109!0AIcs~~oclooI0E1 OFll0 ~ ~
COM91018 -§0221231 241 2'lal 271 28!a!:lA!21!-:2CI20!a:1 2F!30 I31132133 I~
COM17 10 24 -Ei3 42I431 441 43481 414814914A148i-:4cI4oIE14FI SO I511521531'-- DDRAM address
COM25 10 32 -lfj 82183184185166187166169IMI~r~8Cleol6El8F1 70 171172[73 ...-Extension driver

LCD·II/F12

1 2 3 4 5 8 7 8 9 10.11 12 13.14 15 1817 18 1920
1 2 3 4 5 6 7 8 9 10 11 12 13 1415.16 171819 20
., oi 0210313030610~ O~09I~cslO~O~OEIOFll~ 1111211; 001 .., 11 OOl011 021031O4~,csl o~oofiEl OFI 101111 121

~~3~33~~333~~3~~3~~~~

., 4~4343134346H 4~491348]4CH4~EI4FI3 '~521 ~401
-i ai3 6313 36618~ 38913eal8CH36ElaFI7~ 7~72171601

-13 2012112212312412512E127128lal:lAI~21I2CI20I~ 2F1301~11321

-1 ~ 40]411421431 441451 4E1 4714814914A:,48I4CI4DIEI3 1511 1
-173 8Olalla2Ia3184la516E167~,eal8Cleol6E161'1 7Ol711 721

(Left shift display)

50

(Right shift display)

Figure 9 4-Line by 20-Character Display

428

HITACHI

52

HD66712
Character Generator ROM (CG ROM)

Character Generator RAM (CG RAM)

The character generator ROM generates 5 x 8 dot
character patterns from 8-bit character codes
(table 3). It can generate 240 5 x 8 dot character
patterns. User-defined character patterns are also
available using a mask-programmed ROM (see
"Modifying Character Patterns").

The character generator RAM allows the user to
redefine the character patterns. In the case of 5 x
8 dot character, up to eight character patterns may
be redefined.
Write the character codes at the addresses shown
as the left column of table 3 to show the character
patterns stored in CG RAM.
See table 4 for the relationship between CO RAM
addresses and data and display patterns.

HITACHI

429

HD66712
Segment RAM (SEGRAM)
The segment RAM (SEORAM) is used to enable
control of segments such as an icon and a mark by
the user program.
For a I-line display. SEORAM is read from the
COMO and the COMl7 output. and for 2- or 4-line
displays. it is read from the COMO and the
COM33 output. to perform 6O-segment display
(SO-segment display when using the extension
driver).
As shown in table 7. bits in SEORAM
corresponding to segments to be displayed are
directly set by the MPU. regardless of the contents
of DDRAM and CORAM.
SEGRAM data is stored in eight bits. The lower
six bits control the display of each segment. and
the upper two bits control segment blinking.

lines are selected by a program. the required
common signal drivers automatically output drive
waveforms. while the other, common signal
drivers continue to output non-selection
wavefor,ms.
Character pattern data is sent serially through a
6O-bit shift register and latched when all needed
data has arrived. The latched data then enables
the driver to generate drive wavefor,m outputs.
Sending serial data always starts at the display
data character pattern corresponding to the last
address of the display data RAM (DD RAM).
Since serial data is latched when the display data
character pattern corresponding to the starting
address enters the internal shift register. the
HD66712 drives from the head display.
Cursor/Blink Control Circuit

Timing Generation Circuit
The timing generation circuit generates timing
signals for the operation of internal circuits such
as DDRAM. CGROM. CORAM. and SEORAM.
RAM read timing for display and internal
operation timing by MPU access are generated
separately to avoid interfering with each other.
Therefore. when writing data to DD RAM. for
example. there will be no undesirable
interferences. such as flickering. in areas other
than the display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of
34 common signal drivers and 60 segment signal
drivers. When the character font and number of

The cursor/blink (or white-black inversion)
control is used to produce a cursor or a flashing
area on the display at a position corresponding to
the location in stored in the address counter (AC).
For example (figure 11). when the address counter
is (08)H. a cursor is displayed at a position
corresponding to DDRAM address (08)H.
Scroll Control Circuit
The scroll control circuit is used to perform a
smooth-scroll in the unit of dot. When the
number of characters to be displayed is greater
than that possible at one time on the liquid crystal
module. this horizontal smooth scroll can be used
to display all characters.

AC. (08)16
1 2

3 4 5 6 7 8

Display
9 10 11-4-position

1"1 0'11 ~ 04J o!j "l 07~ o~ 1· =:
Cursor position

Figure 10 Cursor/Blink Display Example

430

HITACHI

HD66712
Table 3 Relationship between Character Codes and Character Patterns (ROM code: AOO)

HITACHI

--~-----.--

431

.."-.-- ..-.--,,-..- - - - . - - - - - -

HD66712
Table 4 Relationship between Character Codes and Character Pattern (ROM code: AOl)

432

HITACHI

HD66712
Table 5 Relationship between Character Codes and Character Patterns (ROM code: A02)
owe
~
xxxx

oooc



Alternating
1r1iil...1iI\1
display

i) Cursor display example

ii) Blink display example

B~I
display

1.''''? " i '

iii) White-black inverting

display example
a) Cursor Blink Width Control

i) 5-dot character width

ii) 6-dot character width

b) Font Width Control

Figure 16 Example of Display Control

HITACHI

447

HD66712
Cursor or Display Shift
Cursor or display shift shifts the cursor position or
display to the right or left without writing or
reading display data (table 9). This function is
used to correct or search the display. In a 2-line
display. the cursor moves to the second line when
it passes the 40th digit of the first line. In a 4-line
display. the cursor moves to the second line when
it passes the 20th character of the line. Note that.
all line displays will shift at the same time.
When the displayed data is shifted repeatedly each
line moves only horizontally. The second line
display does not shift into the first line position.
When this instruction is executed, extended
register enable bit (RE) is reset.
The address counter (AC) contents will not change
if the only action performed is a displ~y shift.
In low power mode (LP = I), whole-display shift
cannot be normally performed.
Scroll Enable
When extended register enable bit (RE) is I,
scroll enable bits can be set
Function Set

DL: Sets the interface data length. Data is sent or
received in 8-bit lengths (DB7 to DBo) when
DL is I, and in 4-bit lengths (DB7 to DB4) when
DL is O. When 4-bit length is selected. data must
be sent or received twice.
N: When bit NW in the extended function set is O.
a 1- or a 2-line display is set. When N is 0, I-line
display is selected; when N is 1. 2-line display is
selected. When NW is I, a 4-line display is set.
At this time. N is "Don't care" .
RE: When bit RE is 1. bit BE in the extended
function set register, the SEGRAM address set
register. and the function set register can be
accessed. When bit RE is O. the registers
described above cannot be accessed. and the data
in these registers is held.
To maintain compatibility with the HD44780. the
RE bit should be fixed to O.
BE: When the RE bit is 1. this bit can be
rewritten. When this bit is 1, the user font in
CGRAM and the segment in SEGRAM can be
blinked according to the upper two bits of
CGRAM and SEGRAM.

Only when the extended register enable bit (RE) is
1. the BE and the LP bits shown below can be
accessed. Bits DL and N can be accessed
regardless of RE .

. Table 9 Shift Function
SIC

RlL

o
o

o

Shilts the cursor position to the lefl. (AC is.decremented by one.)
Shifts the cursor poSition to the right. (AC is incremented by one.)

o

Shifts the entire display to the left. The cursor follows the display shifl.
Shifts the entire display to the right. The cursor follows the display shift.

448

HITACHI

HD66712
LP~ When bit RE is I, this bit can be rewritten.
When LP is set to 1 and the EXT pin is low
(without an extended driver), the HD66712
operates in low power mode. In I-line display
mode, the HD66712 operates on a 4-division
clock, and in a 2-line or a 4-line display mode, the
HD66712 operates on a 2-division clock.
According to these operations, instruction
execution takes four times or twice as long. Note
that in low power mode, display shift cannot be
performed. The frame frequency is reduced to 5/6
that of normal operation. See "Oscillator Circuit"
for details.
Note: Perform the DL, N, NW, and FW fucntions
at the head of the program before executing any
instructions (except for the read busy flag and
address instruction). From this point, if bits N,
NW, or FW are change4 after other instructions
are executed, RAM contents may be broken.

Set DD RAM Address
A DD RAM address can be set while the RE bit is
cleared to O. Set DD RAM address sets the DD
RAM address binary AAAAAAA into the address
counter.
After this address set, data is written to or read
from the MPU for DD RAM.
However, when Nand NW is 0 (I-line display),
AAAAAAA can be (OO)H to (4F)H. When N is 1
and NW is 0 (2-line display), AAAAAAA is (00)
H to (27)H for the first line, and (40)H to (67)H
for the second line. When NW is 1 (4-line
display), AAAAAAA is (OO)H to (13)H for the
first line, (20)H to (33)H for the second line, (40)H
to (53)H for the third line, and (60)H to (73)H for
the fourth line.

Set CG RAM Address
A CO RAM address can be set while the RE bit is
cleared to O.
Set CO RAM address into the address counter
displayed by binary AAAAAA. After this address
set, data is written to or read from the MPU for
CORAM.
Set SEGRAM Address
Only when the extended register enable (RE) bit is
I, HS2 to HSO and the SEORAM address can be
set.
The SEORAM address in the binary form AAAA
is set to the address counter. After this address set,
SEORAM can be written to or read from by the
MPU.

Set Scroll Quantity

When extended registor enable bit (RE) is I,
HDSS to HDSO cim be set.
HDS5 to HDSO specifies horizontal scroll quantity
to the left of the display in dot units. The
HD66712 uses the unused DDRAM area to
execute a desired horizontal smooth scroll from 1
to 48 dots.
Note: When performing a horizontal scroll as
described above by connecting an extended driver,
the maximum number of characters per line
decreases by the quantity set by the above
horizontal scroll. For example, when the
maximum 24-dot scroll quantity (4 characters) is
used with 6-dot font width and 4-line display, the
maximum numbers of characters is 20 - 4 = 16.
Notice that in low power mode (LP = I), display
shift and scroll cannot be performed.

HITACHI

449

HD66712
Read Busy Flag and Address
Read busy flag and address reads the busy flag
(BF) indicating that the system is now internally
operating on a previously received instruction. If
BF is I, the internal operation is in progress. The
next instruction will not be accepted until BF is
reset to O. Check the BF status before the next
write operation. At the same time, the value of the
address counter in binary AAAAAAA is read ouL
This address coun~r is used by both CO, DD, and
SEO RAM addresses, and its value is determined
by the previous instruction. The address contents
are the same as for CO RAM, DD RAM, and SEO
RAM address set instructions.
Write Data to CG, DD, or SEG RAM
This instruction writes 8-bit binary data
DDDDDDDD to CO, DD or SEO RAM. CO, DD
or SEO RAM is selected by the previous
specification of the address set instruction (CO
RAM address set I DD RAM address set I SEO
RAM address set). Mter a write, the address is
automatically incremented or decremented by 1
according to the entry mode. The entry mode also
determines the display shift direction.

the next address is normally read from the next
address. An address set instruction need not be
executed just before this read instruction when
shifting the cursor by a cursor shift instruction
(when reading from DD RAM). A cursor shift
instruction is the same as a set DD RAM address
instruction.
After a read, the entry mode automatically
increases or decreases the address by 1. However,
a display shift is not executed regardless of the
entry mode.
Note: The address counter (AC) is automatically
incremented or decremented after write
instructions to CO, DD or SEO RAM. The
RAM data selected by the AC cannot be
read out at this time even if read
instructions are executed. Therefore, to
read data correctly, execute either an
address set instruction or a cursor shift
instruction (only with DD RAM), or
alternatively, execute a preliminary read
instruction to ensure the address is correctly
set up before accessing the data.

Read Data from CG, DD, or SEG RAM
This instruction reads 8-bit binary data
DDDDDDDD from CO, DD, or SEO RAM. CO,
DD or SEO RAM is selected by the previous
specification of the address set instruction: If no
address is specified, the first data read will be
invalid. When executing serial read instructions,
Table 10 HS5 to HSO Settings
HDSS HDS4 HDS3 HDS2 HDS1 HDSO Descrll!!lon
0
0
0
0
0
0
No shift
Shift the display position 10 the
0
0
0
0
0
left !!l one dOl.
Shift the display poSition 10 the
0
0
0
0
0
left !!l1WO dots.
Shift the display position 10 the
0
0
0
0
left !!l three dolS.

.

0

Shift the display posilion 10 the
left bll fo!:!ll-seven dolS.
Shift the display position 10 the
left by forty-eighl dolS.

HITACHI

HD66712
Table 11 Instructions

Inatructlon

RE
Code
bit RS RIW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Deacrlptlon

Clear
display

011

Return
home

011

Entry
mode set

011

o

Display
on/off
control

0

0

0

0

0

o

o o

0

o

o

o

0

0

o

o

0

0

o

o

0

0

o

0

0

0

0

Clears entire display and
sets DD RAM address 0
in address counter.

0

o

o

Sets DD RAM address 0
IN address counter. Also
returns display from
being shifted to original
position. DDRAM contents remain unchanged.

liD S

D

Execution Time
(max) (when 'ep or
fosc la 270 kHz)

C

B

Sets cursor move
direction and specifies
display shih. These
operations are performed
during data write and read.
Sets entire display (D)
on/off. cursor on/off (C).
and blinking of cursor
position character (B).

1.52 ms

1.52ms

371ls

371lS

-------------------------------------------------------------------------------------Extension
o 0 o 0 0 0
FW BlW NW Sets a font width. a blackfunction
set

white inverting cursor
(B/W). and a 4-line
display (NW).

Cursor or
display
shift

0

0

0

0

0

0

SIC RIL -

-

Moves cursor and shifts
display without changing
DD RAM contents.

371lS

-------------------------------------------------------------------------------------Scroll enable 1
0
0
0
0
0
HSE HSE HSE HSE Specifies which display
lines to undergo horizontal smooth scroll.
Function
set

0

0

0

0

0

Dl

N

RE

-

-

Sets interface data length
(Dl). number of display
lines (l). and extension
register write enable (RE)).

37 Ils

37 IlS

----------------------------------------------------------------------_._------------o 0 0 0
Dl N
RE BE lP
Sets CGRAMISEGRAM
blinking enable (BE). and
power-down mode (lP).
lP is available when the
EXT pin is low.
Set
CGRAM
~~~f!!~

o

0

0

o

371ls

ACG ACG AcG ACG AcG ACG Sets CG RAM address.
CG RAM data is sent and

________________________________________________ !~~i~~~~r:.r_'.!:'~_s_e!~n_g.: ____________ _

Set
SEGRAM
address set

0

0

0

••

ASEGAsEGAsEG ASEG Sets SEGRAM address.
DDRAM data is sent and
received aher this selling.
Also sets a horizontal dot
scroll quantity (HDS).

37 Ils

Set DDRAM 0
0
0
ADD ADD ADD ADD ADD ADD ADD Sets DD RAM address.
DD RAM data is sent and
37 Ils
address
______________________________________________________ !!~i~~~!~~r_'~~_s_e!~n_g.: ____________ _
Set scroll
quantity

o o

.

HDS HDSHDSHDS HDS HDS Sets horizontal dot scroll
quantity.

HITACHI

451

HD66712
Table 11 Instructions (cont)
RE
Instruction

bit

RS

Read busy
lIag&
address

011

0

Write data
to RAM

011

Read data
from RAM

011

110
110
S

o
C
B
FW
BIW
NW
NW
SIC
SIC
AIL
RIL
DL
N
RE
BE
LP
BF
BF
Note:

Code
RIW DB7 DB6 DB5 DB4 DB3 DB2 DBl DBO Description
BF

o

AC

AC

AC

AC AC

AC

AC

Execution TIme
(max) (when lop or
lose Is 270 kHz)

Reads busy flag (BF)
indicating internal operation is being performed
and reads address
counter contents.

o J1s

Write data

Writes data into DO RAM, 37 J1S
CG RAM, or SEGRAM.
tADD 5.5 J1s·

Read data

Reads data from DO RAM, 37 J1S
CG RAM, or SEGRAM.
tADD 5.5 J1s·

= 1: Increment
= 0: Decrement
= 1: Accompanies display shift
= 1: Display on
= 1: Cursor on
= 1: Blinkon
= 1: 6-dot font width
= 1: Black-white inverting cursor on
1: Four lines
= 0: One or two lines
= 1: Display shift
0: Cursor move
= 1: Shift to the right
= 0: Shiflto the left
= 1: 8 bits, DL = 0: 4 bits
= 1: 2 lines, N = 0: 1 line
= 1: Extension register access enable
= 1: CGRAMISEGRAM blinking enable
= 1: Low-power mode
1: Internally operating
= 0: InstrUctions acceptable

=

=

=

=

DO RAM: Display data RAM
ADD: DO RAM address (corresponds to
cursor address)
CG RAM: Character generator RAM
ACG: CG RAM address:
SEGRAM: Segment RAM
ASEG: Segment RAM address
HSE: Specifies horizontal scroll lines
HDS: Horizontal dot scroll quantity
AC: Address counter used for both DO, CG,
and SEG RAM addresses.

=

1. - indicates no effect.
*After execution of the CG RAMIDD RAM data write or read instruction, the RAM address counter is
incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off.
In figure 18, tADD is the time elapsed after the busy nag turns off until the address counter is updated.
2. Extension time changes as frequency changes. For example, when f is 300 kHz, the execution time is:
37 J1s x 270/300 33 J1s.

=

3. Execution time in a low-power mode (LP
twice for a 2- or 4-line mode.

452

= 1 & EXT =low) becomes four times for a l-line mode, and

HITACHI

HD66712

Busy state
(O~ pin)

-

Boo, .lale

4

-------------------------------A--':----~~~------A-+-1------~,

Address counter
(OBo to OBs pins)

..:

:..
tADD
t ADD depends on the operation frequency.
t ADD - 1.5/(1 cp or losc) seconds

Figure 18 Address Counter Update

HITACHI

453

HD66712
Interfacing the H066712
- Interface with 8·Bit MPUs

When the number of I/O ports in the MCU, or the
interfacing bus width, if limited, a 4-bit interface
function is used.

The HD66712 can interface directly with an 8·bit
MPU using the E clock, or with an 8·bit MCU
through an I/O port.

AS

RIW

E
Internal
signal

DB7

Internal operation

!llX

Data

Instruction
write

YJllllJ
I

Busy

'---___--1/

Vllllll/ BusX/jl/A ~~~~

Busy flag check

I

I

Busy flag check Busy flag check

Figure 19 Example of 8·Bit Data Transfer Timing Sequence

454

HITACHI

I~~:~uction

HD66712

i) Bus line interface
VMA
1IJ2
A15

HD6800
AO

R-J

E
LCD·II/F12

AS
AfiR

AfiR
00-07

DBO-DB7

8
ii) 110 port interface

..

co
H8/325

AO-A7

E

AS
AfiR

C1
C2

...

~

.

LCD·II/F12

DBO-DB7

Figure 20 8·Bit MPU Interface

HITACHI

455

HD66712
- Interface with 4·Bit MPUs
The HD66712 can interface with a 4-bit MCU
through an 1/0 port. 4·bit data representing high
and low order bits must be transferred sequentially.

The DL bit in function-set selects 4-bit or 8-bit
interface data length.

AS
RIW

E
Internal
signal

__----II
Instruction
write

\'--_ _--JI

Internal operation

I

Busy flag check

Busy flag check

Figure 21 Example of 4-Bit Data Transfer Timing Sequence

HMCS4019R

LCO·IIIF12

RS
RFIl

015
014
013
R1o-R13

E

4

OB4-0B7

.Figure 22 4·bit MPU Interface

456

HITACHI

I

ln~truction
write

HD66712
Oscillator Circuit
1) When an external clock is used

Clock -

2) When an internal oscillator is used

aSCl

Af=e=

aSCl
aSC2

The oscillator frequency can be
adjusted by oscillator resistance
(Af). If Af Is increased or power
supply voltage Is decreased, the
oscillator frequency decreases.
The recommended oscillator
resistor is as follows.

LCO-IVF12

LCO-IVF12

• Af = 91 kn ± 2% (Vee = 5 V)
• Af = 75 kCl ± 2% (Vee = 3 V)

Figure 23 Oscillator Circuit
(I) I N7dutycyde
1~Ine ••I&C1lon period

13141-------11611711 1 2131-------1161171
VOO---------------------------,~~r_-------------------

COMI VI

----~--------------------~-+I------------------­

____________________________________________ __
V4~1r_~----------------------~--------------~LV5~~~

~

...
I'II(E----I frame-----~~~Io(o(---I frame---.....,:.:.II

Item

Norma. Display Mode (LP = 0)
5-Dot Font Width 6-Dot Font Width

Low Po_r Mode (LP =1)
5·Dot Font Width 6·Dot Font Width

Une saledlon period
Frame frequency

200 clocks
79.4 Hz

60 clocks
86.2 Hz

240 docks
68.2 Hz

72 docks
55.1 Hz

Note: At the ceJculatlon example above for displayed frame frequency, ali oscillator frequencies are 270 kHz
(I dock. 3.7 fIS).
(2) I /33 duty cycle
I·lino ..IOCIIo" period

Vee
VI

r.i

2

1

3 1 4 1-------1 3213311 1 2

I
I'll(

5-001 Font Width 6-Dot Font Width
100 clocks
120 clocks

Une seledlon period
Frame frequency
81.8 Hz

I

:.1"'"

I frame

llrame

68.2 Hz

.. I

Low Power Mode (LP = 1)

Normal Display Mode (LP = 0)
.am

3 1-------1 32 1 331

I

COMI
V4
V5

1

5-Dot Font Width 6-Dot Font Width
60 docks
72 clocks

68.2 Hz

56.8 Hz

Note: Attha calculation example above for displayed frame frequency, 81i osclilator frequendes are 270 kHz
(I dock. 3.7 fIS).

Figure 24 Frame Frequency

HITACHI

457

HD66712
Power Supply for Liquid Crystal
Display Drive
1) When an external power supply is used

-.--IVcx;
V1
"----'V2
----'V3
"----'V4
"----'V5

VEE
2) When an internal boo~ter is used

(Boosting three times)

(Boosting twiee)
Vee

Vee
Vel
GND

Vee
V1
V2

::-

C1

1J.1F

C2

+

-

V3

V4
V50UT2
V50UT3 V5

R

Vel

R

GND

-=-

FlO

1J.1F

+

R

R

1J.1F.:tI:.

Vee
V1
V2

C1
C2

V50UT2
V50UT3

V3
V4
V5

R
R
RD
R
R

=1J.1F~

1J.1F ~

Notes 1. Boosted output voltage should not exceed the maximum value (13 V) of the liquid crystal
power supply voltage. Especially. a voltage of over 4.3 V should not be input to the reference
voltage (Vci) when boosting three times.
2. A voltage of over 5.5 V should not be input to the reference voltage (Vci) when boosting twice.

Figure 25 Example of Power Supply for Liquid Crystal Display Drive
Table 12 Duty Factor and Power Supply for Liquid Crystal Display Drive
Data

Item
Number of Lines

2/4

Duty factor
Bias
Divided resistance

1117

1133

115

1/6.7

A

A

A

AO

A

2.7A

Note: A changes depending on the size of liquid crystal penel. Normally. A must be 2 kn to 10 kn.

458

HITACHI

HD66712
Ext~nsion

Driver LSI Interface

By bringing the EXT pin high, extended driver
interface signals (CLl, CL2, D, and M) are output.

b) When using the extension driver
(EXT = High, S-dot font Width)

a) l-ehip operation
(EXT - Low, S-dot font width)

Vee

T
EXT
LCD-II/F12
::; ~
o OO::l!

LCD-I11F12
SEG1SEG60

SEG1SEG60

~

32 x 2-line display

FV

I

A

{

I
M
0
Cl2
CL1

SeglSeg40

Extension driver

Figure 26 HD66712 and the Extension Driver Connection
Table 13 Relationships between the Number of Display Lines and 40·0utput Extension Driver
Controller
LCD·IIIF12

HD44780

LCD·II/F8

HD66702

Display Lines

5·OotWldth

6·Dot Width 5·Dot Width

6·Dot Width

5-Dot Width 5·Oot Width

16x2lines

Not required

Not required Not required

1

1

Not required

2

Not required

20 x 2 lines

Not required

Not required 1

24x 2 lines

Not required

1

40 x 2 lines

Disabled

Disabled

12x 4 lines

Not required

16 x 4 lines

1

20 x 4 lines

1

2

Disabled

2

2

2

1

Disabled

4

3

Disabled

Disabled

2

Disabled

Disabled

3

Disabled

Disabled

Note: The number of display lines can be extended to 32 x 2 lines or 20 x 4 lines in the LCD·lltF12.
The number of display lines can be extended to 30 x 2 lines or 20 x 4 lines in the LCD-II/Fa.

HITACHI

459

HD66712
Table 14 Display Start Address in Each Mode
Number of Lines
1-Llne Mode

2-Llne Mode

4-Llne Mode

Output

5 dot

6 dot

5 dot

6 dot

COM1-COM8

D00±1

D00±1

DOO±1

D00±1

DOO±1

COM9-COM16

DOC±1

DOA±1

DOC±1

DOA±1

D20±1

D40±1

D40±1

D4O±1

D4C±1

D4A±1

D60±1

SOO

500

500

COM17-COM24
COM25-COM32
COMO/COM17
COMO/COM33

sOO

5 dotl6 dot

sOO

Notes: 1. The number of display lines is determined by setting the N/NW bit. The font width is
determined by the FW bit.

2. 0"" is the start address of display data RAM (DDRAM).
3.

S"" is the start address of segment RAM (SEGRAM).

4. ±1 following D"" indicates increment or decrement at display shift.

460

HITACHI

HD66712
a) 5-dot font width: 32 x 2-llne display

LCD-11IF12
SEGI-SEG80

Extension
driver
Sogl-Seg40

LCO·11IF12
SEGI-SEG60

b) &-dot font wldlh: 24 x 2-line display

Extension

LCO·IUFI2
SEG1-SEG60

driver
Sogl-Sog24

c) 5-dot font wldlh: 20 x 4-lIne display

LCO·11IF12
SEGI-SEG60

Extension
drive,
Segl-Seg40

d) 6-dot font width: 20 x 4-llne display

1234567891011121314151617181920
COM1-alM8-i +"3",13..1..1.,13 3++·1ocI33++H3
COM~16-i 3·'1,"'11·1 ..133 arEl-l ocl2iJ iii "1"1"1"1"3
COM17-G0M24-[+'I' 13..1..1"1·1"1-ffi·3·i,"I"I·'I"I,
~32-1... , "i "'1"11-1"1"13 -H"I-11"'J
, . . . . 1I!"6 "1 1'1
41

72

,~

LCD-IIIF 12
SEGI-SEG80

Ex1enlion
dri...r (I)
SegI-Seg40

Exlen.ion
driver (2)
Segl-Sog2O

Figure 27 Correspondence between the Display Position at Extension Display and the DDRAM
Address

HITACHI

461

HD66712
Interrace to Liquid Crystal Display

the number of display lines, EXT pin, and register
value is given below.

Set the extended driver control signal output, the
number of display lines, and the font width with
the EXT pin, an extended register NW, and the
FW bit, respectively. The relationship between the
Table IS Relationship between Display Lines, EXT Pin, and Register Setting
No of No. of
Lines Character

2

4

Note: -

462

20
24
40
20
24
32
12
16
20

5 Dot Font
6 Dot Font
EXT Extended Reglstor SeUlng EXT Extended Reglstor Setting
Pin Driver
N RE NW FW Pin Driver
N RE NW FW Duty
l
l
H
l

2

l
H
l
H
H

0
0
0
1

0
0
0
0
0
0
1

0
0
0
0
0
0
1

0
0
0
0
0
0
0
0

0

l
H
H
l
H
H
H
H
H

means not required.

HITACHI

0
0

3

0

1
1
2

0
0
0

1/17

0

1133
1133
1133
1133
1133
1133

0
0

1
2

1/17
1/17

HD66712
• Example of 5-dot font width connection

LCO-U/F12

1 .... -- ... ------_ .. -.

12

13- -- --- -- - --- --. 24

COM.

~

g

COM7
COMa

-

COM17
(COM.

UBI
~E8:

SEG.
SEG'
. Note: COMO and
COM17 output the
same signals.
Apply them
according to the
wiring pattern.

SEGIO
COlAO

COM'.

ggjU
COM13

r-

EXT

~!i

Figure 28 24 x I-Line + 60-Segment Display (S-dot font, 1/17 Duty)

LCO-U/F12

1 --------------

12

1~------------"·

24

COM'

ggjJ
CCM4

~j

COMa
COM17

Note: COMO and
C0M33 output the
same signals.
Apply them
according to the
wiring pattern.

88IJ1:

at

(=
COM23

COM24

-'-

-

SEG1

SEG2

B~8J

SEGS
SEGS
SEGeO
COMt

COM'.

ggjg

..

~IJ

COM"
COM25
COM26

~ii

r-

S8WY
COM32
EXT

Figure 29 24 X I-Line + 60-Segment Display (S-dot font, 1/33 Duty)

HITACHI

463

HD66712
1

LCD-UIF12

2

_______________ --- - __ --- ___ - -- - - _ - - - -_ - --- -_.

12

I
I

COM8

OOM16

I
I

Note: COM) and COM33
output the same signals.
Apply them according to the
wiring pattern.

COM33
(COMO)

I

~~!U

~~eI I

1110
,r- ElIT

1111
Figure 30 12 x 4·Lme + 60 Segment Display (5·Dot Font, 1/33 Duty)

lCD-WF12

1 -- -_ .. --- .... - -_ .. --- -_ ........ -_. 12

13 -------------- 20

~

=
COM3
COMe

~

~o

COM"
COM"
COMI'
COM"
00M23
COMI.
OOMI7
COMI.

~

COU2I

IBHi!

COU24
COU2.
OOM2.

!Btm
00M2I

i,1l¥.
COM33
(COMO)

......

"., ::::::::::::..
•• ::::::::::::...

Note: COMO and COM33
output the same signals.
Apply them according to the
wiring pattern.

-

~

...L-

EXT

se
...
II:::Q57
se
...

se...
"".00

i§

Extension
driver
seg

..........
.....
SEQ

Figure 31 20 x 4·Line + 80 Segment Display (5-Dot Font, 1/33 Duty)

464

HITACHI

HD66712

LCO-WF12

1 -----------------.

10

11 ------------------- 20

lm1
CX>I3

~

N08:
I COMO and C0M33
output the same signals.
Apply tham acco rdlng lolh.
wiring pallarn.

e,.

g:"

E!IIl8
COM2,
lBJ!J

""""'
!O!til
1iEG,

...."GOI~

ft8l:

~~

SEOH

BEGI.
COMO
0001"

!BIll!
&lII13

"

0001"
000111
0001..
000120
00M21

"L

EXT

=

1m!
000131

Figure 32 20 x 2-Line + 60 Segment Display (6-Dot Font, 1/33 Duty)

HITACHI

465

HD66712
Instruction and Display Correspondence
The display shift is performed for the fust and
second lines. If the shift is repeated, the
display of the second line will not move to the
first line. The same display will only shift
within its own line for the number of times the
shift is repeated.

8-bit operation, 24-digit x I-line display with
internal reset
Refer to table 16 for an example of an
24-digit x I-line display in 8-bit operation.
The LCD-II/F12 functions must be set by the
function set instruction prior to the display.
Since the display data RAM can store data for
80 characters, a character unit scroll can be
performed by a display shift instruction. A dot
unit smooth scroll can also be performed by a
horizontal scroll instruction. Since data of
display RAM (DDRAM) is not changed by a
display shift instruction, the display can be
returned to the first set display when the return
home operation is performed.

S-bit operation, I2-digit x 4-line display with
in terna) reset
The RE bit must be set by the function set
instruction and then the NW bit must be set by
an extension function set instruction. In this
case, 4-line display is always performed
regardless of the N bit setting (see table 19).

4-bit operation, 24-digit x I-line display with
internal reset
The program must set all functions prior to the
4-bit operation (see table 17). When the power
is turned on, 8-bit operation is automatically
selected and the first write is performed as an
8-bit operation. Since DBo to DB3 are not
connected, a rewrite is then required.
However, since one operation is completed in
two accesses for 4-bit operation, a rewrite is
needed to set the functions. Thus, DB4 to DB7
of the function set instruction is written twice.

In a 4-line display, the cursor automatically
moves from the first to the second line after
the 20th digit of the first line has been written.
Thus, if lhere are only 8 characlers in the first
line, the DD RAM address must be set again
afler the 8th character is completed. Display
shifts are performed on all lines
simultaneously.
NOle:

S-bit operation, 24-digit x 2-line display with
internal reset
For a 2-line display, the cursor automatically
moves from the first to the second line after
the 40th digit of the first line has been written.
Thus, if there are only 16 characters in the firSl
line, the DD RAM address must be again sel
after the 16th character is completed. (See
table IS.)

466

HITACHI

When using the internal reset, the
electrical characteristics in the Power
Supply Conditions Using Internal Reset
Circuit table must be satisfied. If not, the
LCD-II/F12 must be initialized by
instructions. See the section, Initializing
by Inslruction.

HD66712
Table 16 8·Bit Operation, 24-Digit x I·Line Display Example with Internal Reset
Step Instruction
RS RlW07

No.

2

3

Operation

Function set
RS RNJD7

08 Os 04 03 02 01

Do

0

0

Sets to a-bit operation and
selects 1·line display.
Bit 2 must always be cleared.

0

Turns on display and cursor.
Entire display is in space mode
because of initialization.

0

0

1

1

0

0

• •

Display onloff control

0

0

0

0

0

0

0

Entry mode set

0

0

0

0

0

1-

0

IH

Write data to CG RAMIDD RAM

1

6

Display

Initialized. No display.

0

5

OS 04 D3 02 01 DO

Power supply on (the HD66712 is initialized by
the internal reset circuit)

0

4

D6

0

0

1

0

0

1

0

0

1

0

0

Write data to CG RAMIDD RAM
1
0
0
1
0
0
1

0

0

Write data to CG RAMIDD RAM

1

0

0

1

0

0

IHL

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the RAM.
Display is not shifted.
Writes H. DO RAM has
already been selected by
initialization when the power
was turned on.
Writes I.

7

a

9

Entry mode set

0
10

I HITACHI

0

0

0

0

0

I HITACHI

0

Write data to CG RAMIDD RAM

1

0

0

0

1

0

0

0

0

0

IITACHI

HITACHI

Writes I.
Sets mode to shift display at
the time of write.
Writes a space.

467

HD66712
Table 16 8·Bit Operation, 24·Digit x I·Line Display Example with Internal Reset (cont)
Step Instruction
No. RS RlWD7 D6 D5
11

D4

D3 D2 D1 DO

Write data to CG RAMIDD RAM
1
0 0
1
0
0
1

Display
ITACHI M_

0

Operation
Writes M.

12

13

Write data to CG RAMIDD RAM
0
0
1
0
0
1
1

14

Cursor or display shift
0
0
0
0
0

0

0

Cursor or display shift
0
0
0
0
0

0

0

Write data to CG RAMIDD RAM
0
0
1
0
0
1
0

0

15
16
17

Cursor or display shift
0
0
0
0
0

18

Cursor or display shift
0
0
0
0
0

19

IMICROKO=

0

Write data to CG RAMIDD RAM
0
0
1 '0
1
1
0

'"
'"

'"

'"

IMICROKO

Shifts only the cursor position
to the left.

IMICROKO

Shifts only the cursor position
to the left.

IICROC~

Writes Cover K.
The display moves to the left.
Shifts the display and cursor
poSition to the right.
Shifts the display and cursor
position to the right.

'"

'"

IMICROCQ

'"

'"

IMICROCO
IICROCOM

0

WritesO.

Writes M.

20

21

468

Return home
0
0
0
0

0

0

0

0

0

I HITACHI

HITACHI

Returns both display and cursor
to the original position
(address 0).

HD66712
Table 17 4-Bit Operation, 24-Digit x I-Line Display Example with Internal Reset
Step Instruction
RS R/WD7

No.

2

3

4

D1

DO

Display

Operation
Initialized. No display.

Function set
RS RlW07
0
0
0

08 05 04
0
1
0

Sets to 4-bit operation.
Clear bit 2. In this case,
operation is handled as S bits
by initialization.

Function set
0
0
0
0
0
0

0
0

03

02

D1

Do

Sets 4-bit operation and selects
I-line display. Clear bit 2.
4·bit operation starts from
this step.

0
>I<

>I<

Turns on display and cursor.
Entire display is in space mode
because of initialization.

Display on/off control

0
0

0
1

0
1

0
1

0
0

0
1

0
1

0
0

Entry mode set

0
0

6

D2

Power supply on (the H066712 is initialized by
the internal reset circuit)

0
0

5

D6 D5 D4 D3

0
0

0
0

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DO/CG RAM.
Display is not shifted.

Write data to CG RAM/DO RAM

1
1

0
0

0
1

1
0

0
0

Writes H.
OORAM has already been
selected by initialization.

0
0

7

Based on S-bit operation after
this instruction.

Note: The control is the same as for S-bit operation beyond step #6.

HITACHI

469

HD66712
Table 18 8-Bit Operation, 24-Digit x 2-Line Display Example with Internal Reset
Step Instruction
No. RS RIW 07 D6

2

05 D4 03 02 01

DO

Olselax

Power supply on (the HD66712 is initialized by
the internal reset circuit)

Initialized. No display.

Function set
RS RIW DB7 DBs DBs DB4 DB3 DB2 DB1 DBo
0
0
0
0
0
1
1
1

Sets to a-bit operation and
selects 2-line display.
Clear bit 2.

Display onloff control

Turns on display and cursor.
All display is in space mode
because of initialization.

• •

3

0

4

0

0

0

0

0

0

0

0

Entry mode set

0

5

Oeeratlon

0

0

0

0

Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the RAM.
Display is not shifted.

0

Write data to CG RAM/DO RAM
1
0
1
0
0
1
0

0

0

Write data to CG RAMIDD RAM
1
0
0
1
0
0
1

0

0

Set DO RAM address
0
0
1
1
0

0

0

0

IH

Writes "H". DO RAM has
already been selected by
initialization at power-on.

6

7

a

470

0

0

I HITACHI

0

I HITACHI

HITACHI

Writes I.

Sets DO RAM address so that
the cursor is positioned at the
head of the second line.

HD66712
Table 18 S-Bit Operation, 24-Digit x 2-Line Display Example with Internal Reset (cont)
Step Instruction
No. RS RJWD7 D6 D5 D4 D3 D2 D1

9

Write data to CG RAMIOD RAM
100
1
001

DO

Display

Operation
Writes a space.

o

10

11

Write data to CG RAMIDD RAM
1001001

Writes O.

12

Entry mode set
000
000

Sets mode to shift display at
the time of write.

13

0

Write data to CG RAM/DO RAM
1001001

Writes M.

o

14

17

Return home
000
0

0

0

0

0

o

HITACHI

Returns both display and cursor
to the original position
(address 0).

471

HD66712
Table 19 8·Bit Operation, 12.Digit x 4-Line Display Example with Internal Reset
Step Instruction
No. RS RlW07 D6 05 D4 D3 02 01

DO

Power supply on (the HD66712 is initialized by
the internal reset circuit)

2

3

4

5

6

7

Function set
0
0
0

0

4-line mode set
0
0
0
0

0

0

0

0

Function set
Inhibit write to extension register
0
0
0
0
1
1 0

Display on/off control
0
0
0
0
0

0

Entry mode set
0
0
0
0

0

0

0

0

0

0

0

Write data to CG RAMIDD RAM
1 0
1 0
0
0
1

0

0

Write data to CG RAMIDD RAM
1 0
0
1 0
0
1

0

0

S

9

472

0

OlsE!la~

~
~
~
~

8
8

°e8tatlon
Initialized. No display.

Sets Sobit operation and
enables write to the extension
register.

Sets 4-line operation.

Inhibits write to extension
register. Invalidates selection
of 1-linel2-line by bit 3.

Turns on display and cursor.
Entire display is cleared
because of initialization.

Sets mode to increment the
address by one and to shift the
cursor to the right when writing
to RAM. Display Is not shifted.

~

Writes H. DDRAM has already
been selected by initialization.

IHIT~H'- I

Writes I.

HITACHI

HD66712
Tallie 19 8-Bit Operation, 12-Digit x 4-Line Display Example with Internal Reset (cont)
Step Instruction
No. RS RIW D7
10

D6

D5

Set DD RAM address
0
1
0
1
0

D4 D3

D2 D1

DO

Display

0

0

0

l~rrACHI

0

0

Operation
Sets DD RAM address to (20)H

the cursor is positioned
I atsothethatbeginning
of the second
line.

11

Write data to CG RAM
1
0
0
0
1

0

0

0

0

I~~ACHI

HITACHI

I

Writes O.

473

HD66712
Initializing by Instruction
initialization by instructions becomes necessary.

If the power supply conditions for correctly

operating the internal reset circuit are not met,
• Initializing when a length of interface is 8-bit system

C

Power on

• Wait for more than 15 ms
after Vee rises to 4.5 V
(Vee .. 5 V during operation)
• Wait for more than 40 ms
after Vee rises to 2.7 V
(Vee = 3 V during operation)

RS PIlI DB-, DBa DBs Os.. DB, DB:! DB, DBa
0 0 0 0 1 1 •

• • •

(I

BF cannot be checked before this instruction.

I

Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS PIlI DB-, DEle DBs Os.. DB, DBz DB, DBa
0 0 0 0 1 1

• • • •

(I

BF cannot be checked before this instruction.

I

Function set (Interface is 8 bits long.)

Wait for more than 100 liS

RS RIW DB7 DEle DB5 Os.. DB, DB:! DB, DBa
0 0 0 0 1 1 • •

• •

(I

BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See table 7.)
RS RIW DB-, DEle DBs Os.. DB, DB:! DB, DBa
0 0 0 0 1 1 N 0 • •

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

1
0
0

0 0 0
0 0 1
1 110 S

Function set.
Display off
Display clear
Entry mode set.

t

,

Initialization ends

Figure 33 Initializing Flow of 8-Bit Interface

474

HITACHI

I

HD66712
• Initializing when a length of interface is 4-bit system.

(

Power on

• Wait for more than 15 ms
after Vee rises to 4.5 V
(Vee = 5 V during operation)
• Wait for more than 40 ms
after Vee rises to 2.7 V
(Vcc = 3 V during operation)

I
RS IWJD~ DBe DBs D~
0

0

0

0

1

1

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS RIW D~ DBe DB5 DB4
0

0

0

0

1

1

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait for more than 100 liS

AS RIW D~ DBa DBs D~
0

0

0

0

1

1

AS RIW D~ DBs DBs DB4
0

0

0

0

1

0

0

0

0

0

1

0

0

0

N

0

• •

0

0

0

0

0

0

0

0

1

0

0

0

0
0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
1
0

0

0

1

110 S

[ I BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See table 7.)
Function set (4-bit mode).
Function set (4-bit mode, N specification).
Display off
Display clear
Entry mode set (lID, S specification)

Initialization ends

Figure 34 Imtlalizing Flow of 4-nit Interface

HITACHI

475

HD66712
Low Power Mode
When the extension driver is not used (EXT =
Low) with extension register enabled (RE = I), the
HD66712 enters low power mode by setting the
low-power mode bit (LP) to 1. During low-power
mode, as the internal operation clock is divided by
2 (2-line/4-line display mode) or by 4 (I-line
display mode), the execution time of each
instruction becomes two times or four times longer
than normal. In addition, as the frame frequency
decreases to 5/6, display quality might be affected.

In addition, since the display is not shifted in low
power mode, display shift must be cleared with the
return home instruction before setting low power
mode. The amount of horizontal scroll must also
be cleared (HDS = 000000). Moreover, because
the display enters a shift state after clearing lowpower mode, the home return instruction must be
used to clear display shift at that time.

RS ANI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
Enable extension register

Clear horizontal scroll quantity

HDS.OOOOOO

Set a low power mode

RS ANI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

Return home

1010101010101010.01
Note: The execution time of an instruction in low-power
mode becomes two times or four times longer than normal.
The frame frequency also decreases by 5/6.

RS ANI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

Clear low power mode

1010I 01011 I DL 0 it>1"'tl BE I;i~q
Note: Up until this instruction, execution time is two times or
four times longer than normal.
RS ANI DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO

Return home

10 1oli]

ololololoWifiir:~

Note: Because the display enters a shift state, be sure to
execute this instruction.

Figure 38 Usage of Low Power Mode

476

HITACHI

HD66712
Absolute Maximum Ratings·
Item

Symbol

Unit

Value

Power supply voltage (1)

Vec

V

-0.3 to +7.0

Power supply voltage (2)

Vcc--Vs

V

-0.3 to +15.0

Input voltage

Vt

V

-0.3 to Vee +0.3

1
3
4

Operating temperature

Topr

°C

-20 to +75

Storage temperature

Tstg

°C

-55 to +125

Note.
1,2

Note: Hthe LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limits is strongly recommended for normal
operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and
cause poor reliability.

DC Characteristics (Vee = 2.7 V to 5.5 V, T a = -20 to +7soC·3)
0.7Vee

Vee

V

VILl

-0.3
-0.3

0.2Vee
0.6

V
V

VIH2

0.7Vee

Vee

V

15

0.2Vec

V

15

Min

Input high voltage (1)
(except OSC1)

VIHl

Input low voltage (1)
(except OSC,)
Input high voltage (2)
(OSC1)
Input low voltage (2)
(OSC1)

lYP

VIL2

Output high voltage (1 ) VOHl
(00-07)

0.75Vee
0.2Vee

VOLl

Output high voltage (2) VOH2
(except 00-07)

0.8Vec

6
Vee = 2.7 to 3.0 V·
Vee - 3.0 to 4.5 V

6

V

-IOH" 0.1 mA

7

V

IOL= 0.1 mA

7

V

-IOH .. 0.04 mA

8

Output low voltage (2)
(except 00-07)

VOl2

0.2Vee

V

IOL" 0.04 mA

8

Driver ON resistance
(COM)

ROOM

20

kn

±Id - 0.05 mA (COM)

13

Driver ON resistance
(SEG)

RSE(3

30

kn

±Id .. 0.05 mA (SEG)

13

I/O leakage current

III
-Ip

9

~

VIN- Oto Vee

50

120

~

Vee = 3 V

T.B.D.

T.B.D.

mA

RI oscillation,
10,14
external clock
Vr;,e .. 3V, fQ§r;, = 270 kHz

13.0

V

Vec-Vs, 115 bias

16

3.0
13.0
V
Vee-Vs, 1/4 bias
VLeD2
Note: • Refer to Electrical Characteristics Notes following these tables.

16

Pull-up MOS current
(RESET" pin)
Power supply current

Icc

LCD voltage

VLeDl

-1
10

3.0

HITACHI

---~.

Note.·

Unit

Symbol

Output low voltage (1)
(00-07)

Test Condition

Max

Item

- - - - - - - - ---

--_._----------

477

HD66712
BooSter Characteristics

Item

Symbol

Output voltage
(V50UT2 pin)

VUP2

Output voltage
(V50UT3 pin)

VUP3

Input voltage

Vel

478

Min

2.5

lYP

Max

Unit

Test Ccindltlon

Notes·

TBD

V

VeI- 4.5 V, 10 _ 0.5 mA,
Ta·25°C

18

TBD

V

Vel = 3 V, 10 = 0.3 mA,
Ta =25°C

18

4.5

HITACHI

V

18

HD66712
AC Characteristics

(VCC = 2.7 V to 5.5 V, T a = -20 to + 75°C*3)

Clock Characteristics (V CC

= 2.7 V to 5.5 V, Ta = -20 to + 7so C*3)
Symbol MIn

Typ

Max

UnIt

External clock frequency

fcp

125

270

410

kHz

External clock duty

Duty

45

50

55

%

External clock rise time

trcp

0.2

Ils

trcp

0.2

Ils

350

kHz

Item
External
clock
operation

External clock fall time
At
oscillation
Note:

Clock oscillation frequency lose

190

270

Test CondItIon

Notes*
11

At= 75kn,
Vcc=3 V

12

* Aefer to the Electrical Characteristics Notes section following these tables.

System Interface Timing Characteristics
C*3)

(1) (V cc = 2.7 V to 4.5 V, T a = -20

to +75°

Bus Write Operation
Symbol

MIn

tCycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr, tEt

Item
Enable cycle time

Typ

Max

Unit

Test Condition

ns

Figure 39

Unit

Test Condition

ns

Figure 40

25

Address set-up time (AS, Am to E) tAS

T.B.D

Address hold time

tAH

20

Data set-up time

tosw

195

Data hold time

tH

10

Item

Symbol

Min

Enable cycle time

Bus Read Operation

tcycE

1000

Enable pulse width (high level)

PWEH

450

Enable riselfall time

tEr, tEt
T.B.D

Address hold time

20

Data delay time

tOOR

Data hold time

tOHR

Max

25

Address set-up time (AS, RIV'I to E) tAS
tAH

Typ

360
5

HITACHI

479

HD66712
Serial Interface Operation
Item

Symbol

Serial clock cycle time

tscvc

Min

Serial clock (high level width)

tscH

400

Serial clock (low level width)

tSCl

400

Serial clock riselfall time

tSCr. tSCI

Chip select set-up time

tcsu

T.8.0

Chip select hold time

tCH

T.8.0

Serial input data set-up time

Max

Unit

Test Condition

20

Ils

Figure 41

ns

50

tSISU

200

Serial input data hold time

tSIH

200

Serial output data delay time

tSOD

Serial output data hold time

Typ

360
5

tSOH

System Interface Timing Characteristics (2) (Vee =4.5 V to 5.5 V, T a =-20 to +75°
C*3)
Bus Write Operation
Symbol

Min

Enable cycle time

tcycE

500

Enable pulse width (high level)

PWEH

230

Enable riselfall time

tEr. tEl

Item

Typ

Max

Unit

Test Condition

ns

Figure 39

Unit

Test Condition

ns

Figure 40

20

Address set-up time (RS. Rm to E) lAs

T.8.0

Address hold time

tAH

10

Data set-up time

tosw

60

Data hold time

tH

10

Item

Symbol

Min

Enable cycle time

IcycE

500

Enable pulse width (high level)

PWEH

230

Enable riselfall time

tEr. tEl

Bus Read Operation
Max

20

Address set-up time (RS. Rm to E) tAS

T.8.0

Address hold time

tAH

10

Data delay time

tOOR

Data hold time

tOHR

480

Typ

160
5

HITACHI

HD66712
Serilll Interrace Sequence
Item

Symbol

Min

Serial clock cycle time

tSCYC

0.5

Serial clock (high level width)

tSCH

200

Serial clock (low level width)

tSCL

200

Serial clock riseltal! time

tscr. tSCI
tcsu

T.B.D

Chip select hold time

tcH

T.B.D

Serial input data set-up time

tSISU

100

Serial input data hold time

tSIH

100

tsoo

Serial output data hold time

tSOH

Max

Unit

Test Condition

20

ILS

Figure 41

ns

50

Chip select set-up time

Serial output data delay time

Typ

160
5

Segment Extension Signal Timing (Vee =2.7 V to 5.5 V, Ta =-20 to +75°C*3)
Item
Clock pulse width

High level

Symbol

Min

tcWH

800

tcWL

Clock set-up time

tcsu

800
500

Data set-up time

tsu

300

Data hold time

Low level

tOH

300

Mdelaytime

tOM

-1000

Clock riseltal! time

fcI

Reset Timing (Vee

Typ

Max

Unit

Test Condition

ns

Figure 42

1000
100

=2.7 V to 5.5 V, T a =-20 to +7soC*3)

Item

Symbol

Min

Reset low-level width

tRES

10

Typ

Max

Unit

Test Condition

ms

Figure 43

Max

Unit

Test Condition

10

ms

Figure 44

Power Supply Conditions Using Internal Reset Circuit
Item

Symbol

Min

Power supply rise time

trec

0.1

Power supply off time

tOFF

1

Typ

HITACHI

481

HD66712
Electrical Characteristics Notes
1.

All voltage values are referred to GND = 0 V. If the LSI is used above the absolute maximum ratings.
it may become permanently damaged. Using the LSI within the following electrical characteristic is
strongly recommended to ensure normal operation. If these electrical characteristic are also exceeded.
the LSI may malfunction or exhibit poor reliability.
.

2.

Vee ~ VI ~ V2 ~ V3 ~ V4 ~ Vs must be maintained.

3.

For die products. specified up to 75°C.

4.

For die products. specified by the die shipment specification.

5.

The following four circuits are I/O pin configurations except for liquid crystal display output.

Input pin
Pin: ElSClK. Rs/CS", RW/SID,IM,
Pins: RESET" (MOSwith pull-up)
EXT, TEST (MOS without pull-up)

Vee

Vee

Output pin
Pins: ell, Cl2, M, 0

Vee

Vce

110 Pin
Pins: DBo/SOD-D~
(MOS with pull-up)

Vee

(pull-up MOS)

Vec
(input circuit)
PMOS

1 - . , - - - - - - Input enable

1--------..- Output
1--1~--+-

6.

Applies to input pins and I/O pins. excluding the OSCI pin.

7.

Applies to I/O pins.

8.

Applies to output pins.

482

HITACHI

enable data

HD66712
9.

Current flowing through pull-up MOSs, excluding output drive MOSs.

10. Input/output current is excluded. When input is at an intennediate level with CMOS, the excessive
current flows through the input circuit to the power supply. To avoid this from happening, the input
level must be fixed high or low.
11. Applies only to external clock operation.

Og".7~VVVC~~T~TI
1~ J.: I

r---

Oscillatorf- OSC1
Open- OSC2

trep

Doty=

-ri.~TI

' 100%

kp

12. Applies only to the internal oscillator operation using oscillation resistor Re.

R.r~1

~2

Rf: 75 kn ± 2% (when Vce = 3 V to 4 V)
Rf:.91 kn ± 2% (when Vcc = 4 V to 5 V)
Since the oscillation frequency varies depending on the OSC1 and
OSC2 pin capacitance, the wiring length to these pins should be
minimized.

Referential data

Vee = 5V

500
400

N

::I:

e.
(.)

l3

300
27'(

Vee = 3V

500

\

1\

.... - ......

200

400

N

::I:

~,, '-!!P.
,,,
,
,,

100
50

91 100

e.
(.)

300

rn

...... ~
150

.Q

27'(

1\

\

i'\.

.... .. ~ I'Typ.

'"

200
100
50

Rf (kn)

HITACHI

'5

100
Rf (kn)

r-....
150

483

HD66712
13.. ReOM is the resistance between the power supply pins (Vee. VI. V4. Vs) and each common
signal pin (COMo to COM33).
RSBG is the resistance between the power supply pins (Vee. V2. V3. Vs) and each segment signal pin
(SEOI to SEOw).
14. The following graphs show the relationship between operation frequency and current consumption.

1.,g
1.6
1.4
~ 1.2
"'-"" t ~0
~ o.8
o.6
o.4
o.2
o.0

o

VCc=5V

typo

....-

~

i"'"

Vcc=3V
1.8r---r--.--.--"-T--.
1.61--+--t--1--+--I
<' 1.4
§. 1.21--+--1----1---+----1
1.01--+--1----1---+----1
~ 0.81---+---+-+--+---1
0.61--+--1----1---+----1
0.41--+--t--1--+--I

0.2t~==:t::::I::j::::::1 typo

<#'

100 200 300 400 500

fOSe or fcp (kHz)

0.0

o

100 200 300 400 500
fOSe or fcp (kHz)

15. Applies to the ascI pin.
16. Each COM and SE~ output voltage is within ±O.15 V of the LCD voltage (Vee. VI. V2. V3. V4. Vs)
when there is no load.
17. The TEST pin must be fIXed to ground. and the 1M or EXT pin must also be connected to Vee or
ground.
18. Booster characteristics test circuits are shown below.
Boosting twice

Boosting three times

Vee

Vee
111 F

+

10k0

.I:+

t

V50UT3

GND

484

HITACHI

HD66712
Load Circuits
AC Characteristics Test Load Circuits

Data bus: OBO-OB7, SOD

1
I

Segment extension signals: CL 1, CL2, 0, M.

1
I

Test 0 - - - - - - ,

Test 0--------.

Point

Point

50pF

30pF

HITACHI

485

HD66712
Timing Characteristics

AS

~:~l

)( .~~11

RIW

"

V1Ll

¥VILl

..

PWEH

;.

VIHt'

VIHl
VILl

"

->

~

~

DBO

)(

to DB?

'~:Hl
'Ill

I

VILl

IDsw

tE,

..

fAH

J

~tEf

~

E

K

tAH

tAS

VILl

'"'
~:~11

Valid data

K

tYeE

Figure 39 8us Write Operation

AS

tAS

RIW

,} r-VIHl

VILl
1E,~

to DB?

~

.

"-

i+tEf

VIHl ~

VIHl

VILl

VILl

4

)(

IDHR

VaLl

Valid data
teyeE

Figure 40 8us Read Operation
486

VIHl
tAH

~

DBO

K

tAH

PWEH

E

~irll

~ r-~irll

HITACHI

VaLl

K

HD66712
tsCYC

CS*

.,.._ _ _ _ _ _-t-_ _ _ _ _ _ _+--:-_...."...VIL1
tCH

IHl

SCLK

SID
tSOH

SOD
Figure 41 Serial Interface Timing

tet

CL1 _ _ _ _-'

CL2

o

VOH2
VOL2
tOH

M
tOM

Figure 42 Interface Timing with Extension Driver

HITACHI

487

HD66712

tRES
RESET*

/

\

~~

VIL1 ";r-

VIL1

I

\

Note: When power is supplied, initializing by the internal reset circuit has priority. Accordingly,
the above RESET* input is ignored during internal reset period.

Figure 43 Reset Timing

Vee

tOFF·1

0.1 ms st rcc S 10 ms

tOFF

~1

ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power
supply oscillations.
2. Specified at 4.5 V for 5-volt operation, and at 2.7 V for 3-volt operation.
3. If the above electrical conditions are not satisfied, the internal reset circuit will not
operate normally. In this case, initialize by instruction. (Refer to Initializing by
Instruction.)

Figure 44 Power Supply Sequemce .

488

HITACHI

HD441 02------------(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Description

Pin Arrangement

The HD44102CH is a column (segment) driver for
dot matrix liquid crystal graphic display systems,
storing the display data transferred from a 4-bit or 8bit microcomputer in the intemal display RAM and
generating dot matrix liquid crystal driving signals.

V.

GND
M

~

Vu

He

~:4
v..

Each bit data of display RAM corresponds to on/off

t:~

a.

V.
V,.

state of each dot of a liquid crystal display to provide
more flexible than character display.

FIlM
DB7

V.,

DBo
DBa
DBa
DI.
DBa

Vao'
Va

V.
YI1

Va

TheHD44102CH is produced by the CMOS process.
Therefore, the combination of HD44102CH with a
CMOS microcontroller can complete portable batterydriven unit ntilizing the liquid crystal display's low
power dissipation.

14

t DBt

Va'
V.. 11

OlIo
OIl

YIt

VD 1

RIW
E

VI'
YIo
Yti

CSs
CSs

CSt

VI?

Vee

Vy
NC

~

as

~~!DlillIiII!IIlg-r~~Hl!.i.h~~::~)!~f!>

The combination of HD44102CH with the row

(common) driver HD44103CH facilitates dot matrix
liquid crystal graphic display system configuration.

Features

(Top-View)

Ordering Information

• Dot matrix liquid crystal graphic display
column driver incorporating display RAM
• Interfaces with 4-bit or 8-bit MPU
• RAM data directly displayed by internal display
RAM
RAM bit data 1: On
RAM bit data 0: Off
• Display RAM capacity: 50 x 8 x 4 (1600 bits)
• Intemalliquid crystal display driver circuit
(segment output): 50 segment signal drivers
• Duty factor (can be controlled by extemal input
waveform)
- Selectable duty factors: 1/8, 1/12, 1/16,
1124,1/32
• Wide range of instruction functions
- Display Data Read/Write, Display On/Off,
Set Address, Set Display
- Start Page, Set Up/Down, Read Status
• Low power dissipation
• Power supplies: Vcc 5 V ± 10%, VBE 0 to -5 V
• CMOS process

Type No.
HD44102CH
HD44102D

HITACHI
---

-----

Package
8O-pln plasHe OFP(FP-80)

chip

489

= 8
i

8

s·t:I

1
RST

--0_---------,

as

%

j

VIIIJVFIJ

I:: ~-,. _:_::I
Latch (SO clrculls)

E. RIW, DII
CSI-CSa
080-087

o

DIsplay data RAM

%

SOx4x 8 bit

.1.2VccGND_.

VEE-

VIV2VaV4

'III

.M

r - - - - ' CL
.....---. FRM

:t
....

o
N

HD44102
Absolute Maximum Ratings
Item

Symbol

Unit

-0.3 to +7.0

V

Vcc -13.5 to Vcc + 0.3

V

Vn
VT2

-0.3 to Vcc + 0.3

V

1,2

Vee -0.3 to Vee + 0.3

V

3

TC!f!!
Tstg

-20 to +75

°C

-55 to +125

°C

Vcc

Supply voltage (2)

VEE

Input voltage (1)
Input voltage (2)
Operating temperature
Storage temperature

Notes

Value

Supply voltage (1)

Notes: 1. Referenced to GND = O.
2. Applied to input terminals (except V1, V2, V3, and V4), and I/O common terminals.
3. Applied to terminals V1, V2, V3, and V4.

Electrical Characteristics
(Vee = +5 V ±10%, GND

= 0 V, VEE = 0 to -5.5 V, Ta = -20 to 75 °C) (Note4)

Item

Symbol

Min

Input high voltage (CMOS)

VIHC

0.7 x Vcc

-

Input low voltage (CMOS)

0
2.0

Input low voltage (TTL)

VIIJ;
VIHT
VILT

0

-

Output high voltage

VOH

+3.5

Output low voltage
Vi-Xj ON resistance

Input high voltage (TTL)

Typ Max

Unit Test condition
V

Notes

Vcc
0.3 x Vee V

5

Vcc
+0.8

V

6

V

VOL

- ..,
- +0.4

RON

- 7.5

5

V

6
IOH =-250 J,1A

7

V

IOL =+1.6mA

7

kn

VEE = -5 V ± 10%,
Load current 100 itA

Dissipation current (1)

Iccl

-

Dissipation current (2)

Icc2

- 500

IILl

-1

Input leakage current (2)

Input leakage current (1)

1112

-2

Operating frequency

feu<

25

1

itA

2

J,1A

280

VIN = Vee to GND

8

kHz

VIN = Vcc to VEE
«111, «112 frequency

9

100

J,1A

fel< = 200 kHz frame = 11

itA

10

65 Hz during display
Access cycle 1 MHz

12

at access

HITACHI

491

HD441 02
Notes: 4.
5.
6.
7.
8.

Specified within this range unless otherwise noted.
Applied to M, FRM, Cl, BS, RST,~1, +2.
Applied to CS1 to CS3, E, 011, RIW and OBO to OB7.
Applied to OBC to OB7.
Applied to input terminals, M, FRM,Cl, BS, RST, ~1, ~2, CS1 to CS3, E, 011 and RIW,
and 1/0 common terminals OBC to OB7 at high impedance.
9, Applied to V1, V2, V3, and V4.
1C. ~1 and +2 AC characteristics.

Duty factor

Symbol

Min

Duty

20

Typ
25

Fall time
Rise time
~hase

difference time

0.8

Phase difference time

0.8

Max

Unit

30

%

100

ns

100

ns
J.1S
J.1S

40

~
1

~1

O.7Vee
O.SVee
O.3Vee
II

~2

J.1S

Th~
t21
T l - l b -__

112

Ir

O.7Vee
O.SVee
O.3Vee

feLK ..

1
"i'i"'+'i'h

DUTY ..

Tl~ lb

O.SVee
Ir

x 100 (%)

II

11. Measured by Vee terminal at no output load, at 1/32 dury factor, and frame frequency
of 65 Hz, in checker pattern display. Access from the CPU is stopped.
12. Measured by Vee terminal at no output load, 1132 duty factor and frame frequency of
65Hz.

492

HITACHI

HD441 02
Interface AC Characteristics
Rem

Symbol

Ecycletime

fcvc

E high level width

PWEH
Pwa

E low level width

UnR

Notes

1000

ns

13,14

450

ns

13,14

~

E fall time
Address setup time

~
tAS

140

Address hold time

tAlI

10

Data setup time

Iosw

200

Data hold time at write
Data hold time at read

Max

ns

13,14

25

ns

13,14

25

ns

13,14

ns

13,14

ns

13,14

ns

13

ns

14,15

450

E rise time

Data delay time

Typ

Min

320

IooR
\-

10

ns

13

IoHA

20

ns

14

Notes:

13. At CPU write

14. At CPU read
+----~~====~

E

E

RIW

RIW

C$.I-CSs
011

CS1-CS3

OBo-DB7

OBo...,OB7

011

15. DBO to DB7 load circuits

1fi
l

Test Point.

Cr

RL

02

R

03
04

f\

-2.4kQ

R

=11 kQ

C = 130 pF (including jig capacitance)
Diodes 0 1 to D. are all 182074 2
Do
to

07
RES

OBo

i

to

i

r

OB7
vcc

6

RST

Figure 7 Example of Connection to HD6800 Series

504

HITACHI

HD44102
2. Example of connection to HD6801
• J'heH0680l issettomode5. PIO-P14areusedas
output pons, and P30-P37 are used as the data bus.
• The 74LSl54 is a 4-10-16 decoder that decodes 4
bits ofPlO-P13 to select the chips.
• Therefore, the HD44102CH can be controlled by
selecting the chips through PIO-P13 and specifying
the 0/1 signal through P14 in advance, and later

conducting memory read or write for external
memory space $0100 to $OIFF of H06801. The
lOS signal is output to SCI, and the R/W signal is
output to SC2.
• For further details on HD6800 and HD680l, refer
to their manuals.

74LS154
Pl0
Pll
P12
PI3
(lOS) SC1

Vo
VI
B
i
C
VIS ....!..
0
G1G2
A

!

I

.s;- CSI
CS2
- CS3

f J.
RIW

(RIW)SC2

HD6801

P14

011

E

P30
P31
(Data Bus)

i

P37

HD44102CH
No.1

E

I

DBo
OBI

D~7

Figure 8 Example of Connection to HD6801

HITACHI

505

HD44102
Connection to Liquid Crystal Display

7

Q-C-

~§~
~::2

1-0-

J:

1
2

X1

r- J:

!1
1

X20~

!

120

J:
X1
galX2

21
,22

0>

l

Liquid crystal display panel
32 x 150 dots

'

:;~
I
~~X12~
J:
132

1------------1
Y1

1------------1

~Y50

Y1

HD44102CH
No.1

1------------1

~Y50

HD44102CH
No.2

Y1~Y50

HD44102CH
No.3

Figure 9 Example of Connection to 1/32 Duty Factor, I-Screen Display

1

-

--

J:

X1
~ X2

Q~

C?

0
.... _
UJ

v<1l

1

~~X15
J:

X16

2
1
15

Liquid crystal display panel
16 x 100 dots

16

1------------1

1------------1

Y1~Y50

Y1~Y50

HD44102CH
No.1

HD44102CH
No.2

Figure 10 Example of Connection to 1/16 Duty Factor, l-Screen Display

506

HITACHI

HD44102

HD44102CH
No.6

Y1

______

Yso

1------------1

HD44102CH
No.7

---------_....-

Y 1 ______ Yso

1------------1

HD44102CH
No. 10

Y1

______

Y40

1------------1

1
2
3

-

J:
Xl
~"C' X2oS X3 -;-

- ~eX
.... fd I
I
::t

20

~\~
I '

0
.... >
1\1

!

~- X12-'I
o~

J:

I
i

I

20
21

22

Liquid crystal display panel

I

32

64

~
34

X

240 dots

'--fs"

'----7

1
53

54

~

1------------1
Y1

______

Yso

HD44102CH
No.1

1------------1
Y1

______

Yso

1------------1
Y1

______

Y40

HD44102CH ..................._....... HD44102CH
No.2

No.5

Figure 11 Example of Connection to 1/32 Duty Factor, 2-Sc:reen Display

HITACHI

507

HD44102
Limitations on Using 4·Bit Interface Function
The H044102 usual\ly transfers display control data
and display data via 8-bit data bus. It also has the 4bit interface function in which the HD441 02 transfers
8-bit data by dividing it into the high-order 4 bits and
the low-order 4-bits in order to reduce the number of
wires to be connected. You should take an extra care
in using the application with the 4-bit interface function
since it has the following limitations.

Limitations
The H0441 02 is designed to transfer the highorder 4-bits and the low-order 4-bits of data in
that order after busy check. The LSI does not
work normalIy if the signals are in the folIowing

state for the time period (indicated with (*) in
fifure 11) from when the high-order 4 bits are written
(or read) to when the low-order 4 bits are written (or
read); R/W = high and 0/1 = low while the chip is
being selected (CSt = high and CS2 = CS3 = don't
care. or CS t low and CS2 CS3 high).

=

=

If the signals are in the limited state mentioned before
for the time period indicated with (*) the LSI does not
work normally. Please do not make the signals
indicated with dotted lines simultaneously. As far as
the time period indicated with (**). there is no problem.
The foIlowing explains how the malfunction is caused
and gives the measures in application.

E

CS

RIW
011

--1----tJ

OBo-OB7

,

I

* :

~~

usy
check

Writes high·
order bits

Writes low·
order b~s

Figure 12 Example of Writing Display Control Instructions

508

=

HITACHI

HD44102
Cause

Measures in Application

Busy check checks if the LSI is ready to accept the
next instruction or display data by reading the status
register to the HD44102. And at the same time, it
resets the internal counter counting the order of highorder data and low-order data. This function makes
the LSI ready to accept only the high-order data after
busy check. Strictly speaking, if R/W = high and Df
I = low while the chip is being selected, the internal
counter is reset and the LSI gets ready to accept highorder bits. Therefore, the LSI takes low-order data for
high-order data if the state mentioned above exist in
the interval between transferring high-order data and
transferring low-order data.

I. HD44102 Controlled Via Port
When you control the HD44102 with the port of a
single-chip microcomputer, you should take care of
the software and observe the limitations strictly.
2. HD44\o2 Controlled Via Bus
a. Malfunction Caused by Hazard
Hazard of input signals may also cause the
phenomenon mentioned before. The phase shift at
transition of the input signals may cause the
malfunction and so the AC characteristics must be
carefully studied.

E~
CS~

Rm~
U

~azard
---..; I+-

Example
Writing High-Order Data

Figure 13 Input Hazard
b. Using 2-Byte Instruction

ELI"LJL
CS~

~
Address~
(011)
OBo- OB7

--0-0
High-order Law-order

data

data

Last 2 Machine Cycles

of 2-Byte Instruction

Figure 14 2.Byte Instruction

HITACHI

509

HD44102
In an application with the H06303, you can prevent
malfunction by using 2-byte instructions such as STD
and STX. This is because the high-order and loworder data are accessed in that order without a break
in the last machine cycle of the instruction and R/W
and 0/1 do not change in the meantime. However, you
cannot use the least significant bit of the address
signals as the 0/1 signal since the address for the

second byte has an added 1. Design the CS decoder
so that the addresses for the HD441 02 should be 2N
and 2N + I, and that those addresses should be
accessed when using 2-byte instructions. Forexample,
in figure 14 the address signal AI is used as 0/1 signal
and Al -AI, are used for the CS decoder. Addresses
4N and 4N + I are for instruction access and addresses
4N + 2 and 4N + 3 are for display data access.

HD6303

HD44102CH

Figure 15 HD6303 Interface

510

HITACHI

HD441 03------------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Description

Pin Arrangement

The HD44103CH is a common signal driver for dot
matrix liquid crystal graphic display systems. It
generates the timing signals required for display with
its internal oscillator and supplies them to the column
driver (HD44102CH) to control display, also
automatically scanning the common signals of the
liquid crystal according to the display duty. It can
selectS types of display duty ratio: 1/8,1/12,1/16,1/
24, and 1/32. 20 driver output lines are provided, and
the impedance is low (500 n max.) to enable a large
screen to be driven.

Features
• Dot matrix liquid crystal graphic display common
driver incorporating the timing generation circuit
• Internal oscillator (Oscillation frequency can be
selected by attaching an oscillation resistor and an
oscillation capacity)
• Generates display timing signals
• 20-bit bidirectional shift register for generating
common signals
• 20 liquid crystal driver circuits with low output
impedance
• Selectable display duty ratio: 1/8, 1/12, 1/16, 1/24,
1/32
• Low power dissipation
• Power supplies: Vcc: S V ±10%,
VES: 0 to-S.S V
• CMOS process

.. =. . () ~!

> > >

Q

(Top View)

Ordering Information
Type No.
HD44103CH

Package
SD-pin plastic QFP(FP-SO)

HITACHI

511

=
f

...~

II:"

t=
So

1
V, V2V3V4

V
Vee
GNO
VEE

~

-

OL

20 output terminal

X

X'S X,9 X

I
~

L-

Liquid crystal display
driver circuits

'---

I~
~

l

r--

%

~

'~

X,

1

r!

Bidirectional shift
register

2

18

19

20

.~

DR

~~
.--J

SHL
Timing generation circuit

Oscillator
r'

R CR
Rf

C
Cf

MIS

Fs

OS2
OSI
053

.1 .2

M
CL
~ I - FRM

I....
o

CAl

HD44103
Absolute Maximum Ratings
Item

Symbol

Rated Value

Unit

Supply voltage (1)

Vee

-0.3 to +7.0

V

1

Supply voltage (2)

Vu

Vee -13.5 to Vee + 0.3

V

4

Terminal voltage (1)

Vn
VT2

-0.3 to Vee + 0.3

V

1,2

V

3

°C

Terminal voltage (2)
Operating temperature

Tapr

Vu -0.3 to Vee + 0.3
-20 to +75

Storage temperature

TOlD

-55 to +125

Notes: 1.
2.
3.
4.

Note

°C

Referenced to GND = O.
Applied to input terminals (except V1, V2, V5, and V6) and 1/0 common terminals.
Applied to terminals V1, V2, V5, and V6.
Connect a protection resistor of 220 n ± 5% to VEE power supply in series.

Electrical Characteristics
(Vee = +5 V ±10%, GND

= 0 V, VEE =0 to -5.5 V, Ta =...,.20 to +75 °C) (NoleS)

Item

Symbol Min

Input high voltage

V'H

Input low voltage
Output high voltage

V'L
VOH

TypMax

0.7 x Vee
0
Vee- 0.4

-

lOll - -400 J.lA

7

V

101. - +400 J.lA

7

n

Vu =-5±10%,
Load current ±150 J.lA

J.lA

VIN - Vee to GND

VOl.

0.4

Vi-Xj on resistance

RON

500

Input leakage current (1)

1'L1
IILI

Input leakage current (2)
Oscillation frequency

f8FT
fose:

-1
-2

2
50

300

Note

V
Vee
0.3 x Vee V
V

Output low voltage

Shift frequency

Unit Test condition

430 560

6
6

8.

J.lA VII!! = Vr;t;. to VEE
kHz In slave mode

9

kHz R,=68kn±2%

11

10

C,.10pF±5%
Extemal clock operating

fcp

50

Extemal clock dutY

DutY

45

Extemal clock rise time

t.a.

Extemal ciock fall time

t,..,

Dissipation power (master)

Pool
Pw2

1.1

mW Frame frequency .. 70 Hz14

560

kHz

frequency

Dissipation power (slave)

50 55

%

12

50

ns

12

50

ns

12

4.4

mW CR oscillation =430 kHz 13

HITACHI

513

HD44103
Notes: 5.
S.
7.
8.

Specified within this range unless otherwise noted.
Applied to CR. FS. DS1 to DS3. M. SHl. MIS. Cl. DR. and DL.
Applied to Dl. DR. M. FRM. Cl. «1>1 and «1>2.
Applied to input terminals CR. FS. OS1 to OS3. SHl and MIS. and 110 common terminals
Ol. DR. M. and Cl at high impedance.
9. Applied to V1. V2. V5. and VS.
10. Shift operation timing

Min

0.7Vcc
0.3Vec

DLlDR

tau

Max

5
5

Unit
JlS

0.7Vcc

t,

100

JlS
ns

0.3Vec

~

100

ns

tH
CL

Typ

I,

Ir

11. Relationship between oscillation frequency and RIC,

The values of R, and C, are typical values.
The oscillation frequency varies with the mounting
condition. Adjust oscillation frequency to the
required value.

,

5V

500
400

""'-"
...........

300

"'--

~

fose 200
(kHz) 100
50

514

T~=:25'C

,'"

100

HITACHI

Cf= 6pF
Cf=1 OpF

150 (kG)

HD44103
12.

DlJTY =_T_h_
Th + Tl
trcp

tlcp

open~

Open

R

External Clock -

CR

13. Measured by Vcc terminal at output non-load of RI = 68 k.Q ± 2% and CI = 1OpF ± 5%, 1/
32 duty factor in the master mode. Input terminals must be fixed at Vee or GND whil€!
measuring.
14. Measured by Vcc terminal at output non-load, 1/32 duty factor, frame frequency of 70 Hz
in the slave mode. Input terminals must be fixed at Vee or GND while measuring.

Pin Description
Pin Name

Pin
Number

110

Function

X1-X20

20

0

Liquid crystal display driver output.
Relationship among output Irel, M, and data (0) in shift register:

J

M

1

_

r

0

D~
Output

I I I I I

level-

CR,R,C

M

3

Oscillator

1/0

RI

V2

• -

Va

• -

VI

••

Vs

•

CI

fF1CR-

Signal for converting liquid crystal display driver signal into AC.
Master: Output terminal
Slave: Input terminal

HITACHI

515

HD44103
Pin
Number

1/0

Function

CL

1/0

Shift register shift clock.
Master: Output terminal
Slave: Input terminal

FRM

o

Frame signal, Display synchronous signal.

Pin Name

DS1-DS3

Display duty ratio select.

3

Display
Duty Ratio

1124

1/12

X

DS1

L

H L

DS2

L

DS3

L

L

1/32

1/16

H

L

H L H

L H H

L

L H H

H

H H H

L

L

Frequency select.
The relationship between the frame frequency fFRM and the
oscillation frequency fose is as follows:

FS

FS = High: fose =6144 X fFPM
FS = Low: fose = 3072 X fFRM

DL,DR
SHL

516

1/8

2

1/0

(1)
(2)

Example (1)

When FS = high, adjust Rf and Cf so that the
oscillation frequency is approx.
430 kHz if the frame frequency is 70 Hz.

Example (2)

When FS = low, adjust Rf and Cf so that the
oscillation is approx. 215 kHz, in order to obtain the
same display waveforms as example 1. When
compared with example 1, the power dissipation is
reduced because of operation at lower frequency.
However, the operating clocks cjl1 and cjl2 supplied to
the column driver have lower frequencies. Therefore,
the access time of the column driver HD44102CH
becomes longer.

Data 1/0 terminals of bidirectional shift register.
Shift direction select of bidirectional shift register.

SHL

Shift Direction

H

DL -+ DR

L

DL~DR

HITACHI

HD44103
Pin Name

Pin
Number

1/0

Function
Masterlslave select.

MIS

MIS = High: Master mode
The oscillator and timing generation circuit supply display
timing signals to the display system. Each of 1/0 common
terminals, DL, DR, M, and CL is placed in the output state.
MIS '" Low: Slave mode
The timing generation circuit stops operating. The oscillator is
not required. Connect terminal CR to Vcc.
Open terminals C and R. One (determined by SHL) of DL and
DR, and terminals M and CI are placed in the input state.
Connect M, CL and one of DL and DR of the master to the
respective terminals.
Connect FD, DS1, DS2, and DS3 to Vcc.
When display duty ratio is 1/8, 1/12, or 1/16, one HD44103CH is
required. Use it in the master mode.
When display duty ratio is 1/24 or 1/32, two HD44103CHs are
required. Use the one in the master mode to drive common signals 1
to 20, and the other in the slave mode to drive common signals 21 to
24 (32).
,1,,2

2

0

Operating clock output terminals for HD44102CH.
The frequencies of ,1 and ,2 become half of oscillation frequency.

V1, V2,
V5, V6

4

Vcc
GND
VEE

3

Liquid crystal display driver level power supply.
V1 and V2: Selected level
V5 and V6: Non-selected level
Power supply.
Vcc-GND:Power supply for internal logic
VCC-VEE: Power supply for driver circuit logic

HITACHI

517

HD44103
Block Functions

Bidirectional Shift Register

Oscillator

20-bit bidirectional shift register. The shift direction
is determined by SHL. The data input from DL or DR
performs a shift operation at the rise of shift clock CL.

The oscillator is a CR oscillator attached to an
oscillation resistor Rf ans osckllation capacity Cf.
The oscillation frequency varies with the values ofRf
and a and the mounting conditions. Refer to Electrical
Characteristics (Note 10) to make proper adjustment.
Timing Genaration Circuit
The timing generation circuit divides the signals from
the oscillator and generates display timing signals (M,
CL, and FRM) and operating clock (cpl and cp2) for
HD44102CH according to the display duty ratio set
by OS I to DS3. In the slave mode, this block stops
operating. It is meaningless to set FS, DSI to DS3.
However, connect them to Vcc to prevent floating
current.

518

Liquid Crystal Display Driver Circuit
Each of 20 driver circuits is a multiplex circuit
composed of four CMOS switches. The combination
of the data from the shift register with M signal allows
one of the four liquid crystal display driver levels V I,
V2, V5,andV6tobetransferredtotheoutputterminals.

Applications
Refer to the applications of the HD44102CH.

HITACHI

HD441 05------------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Description

Features

The HD44105H is a common signal driver for
LCD dot matrix graphic display systems. It
generates the timing signals required for display
with its internal oscillator and supplies them to the
column driver (HD44102H) to control display, also
automatically scanning the common signals of the
liquid crystal according to the display duty cycle.
It can select 7 types of display duty cycle 1/8, 1/12,
1/16, 1/24,1/32, 1/48, and 1/64. It provides 32
driver output lines and the impedance is low (1 kQ
max) enough to drive a large screen.

Dot matrix graphic display common driver
including the timing generation circuit
Internal oscillator (Oscillation frequency is
selectable by attaching an oscillation resistor
and an oscillation capacitor)
Generates display timing signals
32-bit bidirectional shift register for generating
common signals
32 liquid crystal driver circuits with low
impedance
Selectable display duty ratio: 1/8, 1/12, 1/16,
1/24, 1/32, 1/48, 1/64
Low power dissipation
Power supplies:
Vee = +5 V ± 10%
VEE =0 to -5.5 V
CMOS process

Ordering Information
Type No.

Package

HD44105H

SO-pin plastic QFP(FP-SO)

HD44105D

Chip

Absolute Maximum Rating (Ta =2S 0 C)
Item

Symbol

Ratings

Unit

Note

Supply voltage (1)

Vcr;

-0.3 to +7.0

V

Supply voltage (2)

VEE

Vcr;-13.5 to Vcr; +0.3

V

Terminal voltage (1)

Vn

-0.3 to Vee +0.3

V

1,2

Terminal voltage (2)

VT2

VEE -0.3 to Vcr; +0.3

V

3

Operating temperature

Topr

-20 to +75

·C

Storage temperature

Tstg

-55 to +125

·C

Notes:

1.
2.
3.

Referred to GND = 0 V.
Applied to input terminals (except for V1, V2. V5, and VS) and 1/0 common terminals.
Applied to terminals V1, V2, V5, and VS. Connect a protection resistor of 47 n ± 10% to each
terminal in series.

HITACHI

519

HD44105
Pin Arrangement

co

0)

0

C\I

x x X X X

('I)

.....

II)

...co

..... co

X X X x X X
X19
X20

X7
X6

X21

X5

X22

X4

X23

X3

X24

X2

X25

X1

X26

DL

X27

GND

X28

FS1

X29

FS2

X30

DS1

X31

DS2

X32

DS3

V6

0

V5

R
OR

V1

STB

VEE

V2

...J

::t:

en

~

C\I

.....

::e
a:

0

-e--e-u. ~

0

Z

::e

0

Z

...J

0

a:
0

(Top View)

Note:

520

NCs show unused terminals.
Don' connect any lines to
them in using this LSI.

HITACHI

0

Z

t:I:I

~
~

o....
iii)

V1V2V5V6

x;
I

VCC
GND
VEE

,...-

•
I

J:

~
0

J:

I

i

i

Liquid crystal display
driver circuits

'"--

DL

~

32 output terminals
X2 ----

f

f - - - Log

1

r-

2

r--"

Bidirectional shift
register

30

31

32

r""""- f4 rLogic

DR

SHL
r---

Oscillator

Timing generation circuit

r--RCR
STB

if \.if

B

M
CL
FRM

C
MIS

FS1 FS2

DS2
DS1 DS3

,1,2

s
~
~

t-Io

VI
t-J

o

CTI

HD44105
Electrical Characteristics
(Note 4)
(V CC = +5 V ± 10%, GND = 0 V, VEE = 0 to -5.5 V, Ta = -20 to +75°C)
Item

Symbol Min

Input high voltage

VIH

Typ

0.7 x Vec

Input low voltage
VOH

Output high voltage

Test Condition

Note

Max

Unit

Vec

V

5

0.3XVec V

5

V

Vec-Q·4

Output low voltage

0.4

V

Vi-Xj On resistance

1000

n

IOH - -400 J.LA

S
S

VEE - -5 V ± 10"10,
load current
±15 J.LA

Input leakage current(1)

IILl

-1

-5

J.LA

VIN-VectoGND

7

5

J.LA

VIN - Vec to VEE

8

50

kHz

In slave mode

9

5S0

kHz

Rf-68kn±2%,
Cf.10pF±5%

10

5S0

kHz

11

55

%

11

50

ns

11

11

~----~------~--~----------------------~~-

Input leakage current (2)

IIL2

Shift frequency

FSFT

Oscillation frequency

fosc

300

External clock operating
frequency

fcp

50

External clock duty cycle

Duty

45

External clock rise time

trcp

External clock fall time

430

50

tfcp

50

ns

Dissipation power
(Master)

4.4

mW

Dissipation power
(Slave)

1.1

Notes: 4.
5.
S.
7.

8.
9.

12

Frame 70 kHz

13

Specified within this range unless otherwise noted.
Applied to CR, FS1, FS2, DS1 to DS3, M, SHl, MIS, Cl, DR, Dl, and STB.
Applied to Dl, DR, M, FRM, Cl, 1111, and 1112.
Applied to input terminals CR, FS1, FS2, DS1 to DS3, SHl, MIS, and STB and 110 common
terminals Dl, DR, M, and Cl at high impedance.
Applied to V1, V2, V5, and VS.
Shift operation timing.
Min

DlDR
tsu
Cl

Typ

Max

5

Unit

IJS
IJS

O.7Vec
0.3Vec
tr

522

CR oscillation,
430 kHz

tf

HITACHI

tr

100

ns

tf

100

ns

HD44105
Notes: 10. Relation between oscillation frequency and Rf, Cf.
Connection

Rf~

The values of Rf and Cf are typical
values. The oscillation frequency
varies with the mounting condition.
Adjust oscillation frequency to a
required value.

~

(kHz)

fose

Vcc-5V

500
400
300
200
100
0
0

Cf-6pF
Cf-10pF
50

100
Rf

11.

150 (kO)

n

Th

Tb

Duty-Th_TI
trep

tfcp

ope~n
R

open
External clock

CR

12. Measured by Vee terminal at output non-load of Rf • 68 kn ± 2% and Cf - 10 pF ± 5%, and 1132
duty cycle in the master mode.
Input terminals are connected to Vee or GND.
13. Measured by Vee terminal at output non-load, 1132 duty cycle, and frame frequency of 70 Hz
in the slave mode.
Input terminals are connected to Vee or GND.

HITACHI

523

HD44105
Pin Description
Pin Name Pin Number 1/0
X1-X32

32

0

Function
Liquid crystal display driver outpu1.
Relation among output level, M, and data (D) in shHt register.

M

J

o

J

Rf

I
1/0

110

R

CR

FS1-FS2

524

2

V1

_I

V5

C

I

CROsclliator

Signal for converting liquid crystal display driver signal into AC.
Output terminal
Input terminal

Shift register shift clock.
Master:
Slave:

3

V6

Cf

Master:
Slave:

DS1-DS3

+++

V2

~

FRM

0

Oscillator.

3

a.

r
r

0
0

I_

Output level
CR,R,C

1

Output terminal
Input terminal

0

Frame signal, Display synchronous signal.

I

Display duty ratio select.
Display Duty
Ratio
1/8
1116

1132

1/64

-

1/12

1124

1/48

DS1

L

L

H

H

L

L

H

H

DS2

L

H

L

H

L

H

L

H

DS3

l

l

l

l

H

H

H

H

Selects frequency.
The relation between the frame frequency fFRM and the oscillation
frequency fose is as follows:
FS1

FS2

fose(kHz)

fFRM(Hz)

fM(Hz)

fcp(kHz)

l

l

107.5

70

35

53.8

H

l

107.5

70

35

53.8

l

H

215.0

70

35

107.5

H

H

430.0

70

35

215.0

fosc:
fFRM:
fM:
fcp:

Oscillation frequency
Frame frequency
M signal frequency
Frequencies of.1 and t2

HITACHI

HD44105
Pin Description (cont)
Pin Name Pin Number 110

Function

STB

1

I

Input terminal for testing.

DL,DR

2

110

Connect this terminal to Vee.

SHL

Data 110 terminals of bidirectional shift register.
Selects shift direction of bidirectional shift register.
SHL

Shift Direction

H

DL -+DR

L

DL+-DR

Selects MasterlSlave.
MIS - High: Master mode
The oscillator and timing generation circuit operate to supply
display timing signals to the display system. Each of 110 common
terminals, DL, DR, M, and CL is in the output state.
MIS - Low: Slave mode
The timing generation circuit stop operating. The oscillator is not
required. Connect terminal CR to Vee. Open terminals C and R.
One (determined by SHL) of DL and DR, and terminals M and CL
are in the input state. Connect M, CL and one of DL and DR of the
master to the respective terminals. Connect FS1, FS2, DS1, DS2,
DS3, STB to Vee. When display duty ratio is 1/8, 1/12, 1116, 1124,
1132, one HD44105H is required. Use it in the master mode. When
display duty ratio is 1/48, 1/64, two HD44105Hs are required. Use
one in the master mode to drive common signals 1 to 32, and
another in the slave mode to drive common signals 33 to 48(64) .
• 1,.2

2

V1, V2,
V5, V6

4

Vcc,GND
VEE

3

o

Operating clock output terminals for HD441 02CH. The frequencies of
.1 and.2 are half of oscillation frequency.
Liquid crystal display driver level power supply.
V1 and V2:
V5 and V6:

Selected level
Non-selected level

Power supply.
Vcc-GND:
Vee-VEE:

Power supply for internal logic
Power supply for driver circuit logic

HITACHI

525

HD44105
Block Functions
Oscillator

Bidirectional Shift Register

A CR oscillator attached to an oscillation resistor
Rf and an oscillation capacitor Cf. The oscillation
frequency varies with the values of Rf and Cf and
the mounting conditions. Refer to electrical
characteristics (note 10) to make proper adjustment.

A 32-bit bidirectional shift register. The shift
direction is determined by the SHL. The data input
from OL or OR performs a shift opemtion at the
rise of shift clock CL.

Liquid Crystal Display Driver Circuit
Timing Generation Circuit
This circuit divides the signals from the oscillator
and genemtes display timing signals (M, CL, and
FRM) and operating clock (,1 and ,2) for
HD44102CH according to the display duty mtio set
by DSI to OS3. In the slave mode, this block
stops opemting. It is meaningless to set FS I, FS2
and OSI to OS3. However, connect them to Vee
to prevent floating current.

526

Each of 32 driver circuits is a multiplex circuit
composed of four CMOS switches. The
combination of the data from the shift register with
the M signal allows one of the four liquid crystal
display driver levels VI, V2, V5, and V6 to be
tmnsferred to the output terminals.

HITACHI

n

g
1:1

as·

(10 pF) (68 kO)

At;",

Cf

I

-

J......... I

C CR

COM1

X1

I
I
I
I

I
I
I

:z:

II

tg

.-

~

o
:z:

go

R

~

g

I
I
I

I
I

X32

~

f,

t

l:

V2

-

VS
V4
V3

V4

" III Ia. ~? ~ g-g~~
82eWITO
iii

V6
V1
(200)
VEE

VI,

Y1 - - - - - - - - - Y50
H044102CH
(1)
~

VCC (470)

l:

TO~P{

~

COM32
SEG1 ------- SEGSO - - - - - - - - - - - - - - - - - - - - - SEG201·----- SEG250

F

~
o

..==

32K250Dots
1132 Duty Cycle

I

73as

iii

i

~

V4

:.

f

til

=

t

VI,VI

Y1 - - - - - - - - - Y50
H044102CH
(5)
.~

~

V4

V4

~

~RM

i~

cC:

R D R D D
I I S B - B Sca
82eWITO
73as
81

~
Va!

~

c:a..

=
~

e
n
=

E
RIW

DII
RST
DBO

•

DB?

CS1

•

CS5

6

:t
~

~

o

C1I

HD61102------------(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Description

Features

HD61102 is a column (segment) driver for dot
matrix liquid crystal graphic display systems. It
stores the display data transferred from a 8-bit
micro-controller in internal display RAM and
generates dot matrix liquid crystal driving signals.

Dot matrix liquid crystal graphic display
column driver incorporating display RAM
RAM data direct display by internal display
RAM
RAM bit data 1: On
RAM bit data 0: Off
Internal display RAM address counter:
Preset, increment
Display RAM capacity: 512 bytes (4096 bits)
8-bit parallel interface
Internal liquid crystal display driver circuit: 64
Display duty:
Combination of frame contro.l signal and
data latch synchronization signal make it
possible to select static or optional duty
cycle
Wide range of instruction function:
Display Data Read/Write, Display OnlOff,
Set Address, Set Display Start Line,
Read Status
Lower power dissipation: during display 2mW

Each data bit of display RAM corresponds to the
onloff state of a dot of the liquid crystal display.
As it is internally equipped with 64 output drivers
for display, it is available for liquid crystal graphic
displays with many dots.
The HD61 102, which is produced by the CMOS
process, can complete a portable battery drive
equipment in combination with a CMOS microcontroller, utilizing the liquid crystal display's low
power dissipation.
Moreover it can facilitate dot matrix liquid crystal
graphic display system configuration in
combination with the row (common) driver
HD61103A.

max
Power supply:

Vee: +5 V ± 10%
VEE: 0 V to -10 V

Liquid crystal display driving level: 15.5 V

max
CMOS process

Ordering Information

528

Type No.

Package

HD61102RH

100-pin plastic QFP(FP-1 00)

HITACHI

HD61102
Pin Arrangement

ADC
M

vee

V4R
V3R
V2R
V1R
VEE2

Y64
Y63
Y62
Y61

YSO

Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52

Y51
YSO

Y49
Y48

Y47
Y46
Y45
Y44
Y43

(Top view)

HITACHI

529

HD61102
Absolute Maximum Ratings
Item

Symbol

Value

Unit

Note

Supply voltage

Vee

-0.3 to +7.0

V

2

VEE

Vcc -16.5 to Vee + 0.3

V

3

Terminal voltage (1)

VTl

VEE - 0.3 to Vee + 0.3

V

4
2,5

Terminal voltage (2)

VT2

-0.3 to Vcc+ 0.3

V

Operating temperature

Topr

-20 to +75

°C

Storage temperature

Tstg

-55 to +125

°C

Notes: 1.
2.
3.
4.

5.

530

L51s may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended operating conditions.
Use beyond these conditions may cause malfunction and poor reliability.
All voltage values are referenced to GND - 0 V.
Apply the same supply voltage to VEE1 and VEE2.
Applies to V1 L, V2L, V3L, V4L, V1 R, V2R, V3R, and V4R.
Maintain
Vee ~ V1 L - V1 R ~ V3L - V3R ~ V4L - V4R ~ V2L - V2R ~ VEE
Applies to M, FRM, CL, R5T, ADC, +1, +2, C51, C52, CS3, E, RNI, Oil, ADC, and DBO-DB7.

HITACHI

HD61102
Electrical Characteristics
(GND = 0 V, Vee = 4.5 to 5.5 V, VEE = 0 to -IOV, Ta = -20 to +75°C)
Limit
Item

Symbol Min

Input high voltage

VIHC

0.7 x Vee

VIHT

2.0

Vee

V

VILC

0

0.3 x Vee

V

0.8

V

2

V

IOH - -2051!A

3

V

IOL-1.6mA

3

Vin - GND-Vee

4

Vin - GND-Vee

5

Input low voltage

Typ

Max

Unit

Vee

V

Test Condition

Note

2

VILT

0

Output high voltage

VOH

2.4

Output low voltage

Va.

Input leakage current

IlL

-1.0

+1.0

High impedance off
input current

ITSL

-5.0

+5.0

I!A
I!A

Liquid crystal supply
leakage current

bL

-2.0

+2.0

I!A

Vin - VEE -Vee

6

Driver on resistance

~

7.5

Kn

Vee- VEE -15 V
±ILOAD - 0.1 mA

7

ICC(1)

100

lee(2)

500

I!A
I!A

Dissipation current

Notes:

1.
2.
3.
4.
5.
6.
7.
8.

0.4

During display

8

During Access
access cycle 1 MHz

8

Applies to M, FRM, CL, RST, ADC, ~1, and ~.
Applies to CS1, CS2, CS3, E, ANI, Oil, and DBO-OB7.
Applies to DBO-OB7.
Applies to terminals except for DBa-DB7.
Applies to DBa-DB7 at high impedance.
Applies to V1 L-V4L and V1 R-V4R.
Applies to Y1-Y64.
Specified when liquid crystal display is in 1/64 duty.
fCLK - 250 kHz (~1 and ~ frequency)
Operation frequency:
Frame frequency:
fM - 70 Hz (FRM frequency)
Specified in the state of
Output terminal: Not loaded
Input level:
VIH • VCC (V)
VIL-GND(V)
Measured at Vce terminal

HITACHI

531

HD61102
Interface AC Characteristics
MPU Interlace
(GND= 0 V, Vee = 4.5 to 5.5 V, VEE = 0 to -10 V, Ta = -10 to +75°C)
Unit

Note

1000

ns

1,2

PweH

450

ns

1,2

E low level width

PWEL

450

E rise time

tr

E fall time

If

Item

Symbol

Ecycletlme

Icvc

E high level width

Address setup time

tAS

Address hold time

Min

Typ

Max

ns

1,2

25

ns

1,2

25

ns

1,2

140

ns

1,2
1,2

tAH

10

ns

Data setup time

tosw

200

ns

Data delay time

IoOR

Data hold time (Write)
Data hold time (Read)

ns

2,3

IoHw

10

ns

1

IoHR

20

ns

2

320

NOles: 1.

tcvc
E

PWEH

PWEL

If
Ir

ANI

CS1-CS3
DII

2.0 V

2.0 V
O.SV
2.0 V

DSo-DS7

O.SV
Figure 1

532

CPU Write Timing

HITACHI

HD61102
2.
~----------tc~yC~========~
E

V----PWEl--41""o----PWEH

--"1\

0.8 V

CS1-CS3

2.0 V

011

0.8 V

OBO-OB7
0.4V

Figure:2
3.

CPU Read Timing

OBO-OB7: load circuit

RL-2.4kn
R -11kn
C - 130 pF (including jig capacitance)
Diodes 01 to 04 are alllS2074

HITACHI

®.

533

HD61102
Clock Timinl
(GND = 0 V, Vee = 4.5 to 5.5 V, VEE = 0 to -IOV, Ta = -20 to +75°C)
Limit
Item

Symbol

.1, +2 cycle time

Min

Typ

Max

Unit

20

~s

Te.t Condition

rig. 3
rig. 3
rig. 3

tcyc

2.5

.1 low level width

tWL+1

625

ns

+2 low level width

tWL+2

625

ns

.1 high level width

tVJH+1

1875

ns

Fig. 3

+2 high level width

tWH+2

1875

ns

rig. 3

.1-+2 phase difference

t012

625

ns

Fig. 3

+2~1

t021

625

ns

Fig. 3

rig. 3
rig. 3

phase difference

.1, +2 rise time

tr

150

ns

.1, +2falltime

tf

150

ns

81

82

tWHa2

Figure 3 External Clock Waverorm

534

HITACHI

HD61102
Display Control Timing
(GND
0 V, Vee 4.5 to 5.5 V, VEE

=

=

= 0 to -IOV, Ta = -20

to +75°C)

Limit
Item

Symbol

Min

FRM delay time

toFRM
toM

-2

+2

M delay time

+2

Cllow revel width

tWLCl

-2
35

Cl high level width

tWHCl

35

CL

Typ

Max

Unit

..,.
..,.
..,.
..,.

Te.t Condition
Fig. 4
Fig. 4
Fig. 4
Fig. 4

O.7Vcc " ...---..1-1

FRM

M

Figure 4

Display Control Signal Waveform

HITACHI

535

-"=

II>
W
0.

«,..,

mm'''~
mmZer
1\) ....

e

»

;I';"

g

00

3:

t::I

I I I I
Interface control

-------------------

ir
crQ

I I I I

r---

r--r--3

eS1. eS2. eS3

:I

~
o

-

ANI
011
E
OBo-DB7

:I

OY

+--+-i!.....

i_

t-----t....,

C5

cr

a

~
~

~

... 9
~ ~ ~~~~

f9

!e: 2

1I)!l
~ 5' .......

r!. !e:~ I

-

go

-r-0
§: ~

4096 bit

r

-;;-;--'\
My

al
t6

~s.
_0

;. I

~

l6

DISpi ay start
o

ON~OFF I

/

t t

I I

I\)
lSI ....
lSI

""I3:
JJ

i

iii

:

E
allllE
III 'Iii :J
a:'l:I~

Z

~~

:J.£:

!DU

III

!!!~
•.: '"C
3:alz

~~

:J.£:

!Du

a

~

w

III
III
! 'S

,...

S 06
!D

~ ~.~
0 ...

Figure 5

!D

0

CPU Read Timing

Busy Flag
Busy flag = 1 indicates that HD61102 is operating
and no instructions except status read can be
accepted (figure 6). The value of the busy flag is

540

read out on DB7 by the Status Read instruction.
Make sure that the busy flag is reset (0) before
issuing an instruction.

HITACHI

HD61102

E _ _....

-!I

Busy _ _ _ _

flag

I--

TBusy

1IfCLK~T Busy ~3/fCLK

f CLK is 81, 82 frequency

Figure 6

Busy Flag

Display On/Orr Flip/Flop

x,

The display On/off flip/flop selects one of two
states, on state and off state of segments YI to
Y64. In on state, the display data corresponding to
that in RAM is output to the segments. On the
other hand, the display data at all segments
disappear in off state independent of the data in
RAM. It is controlled by the display on/off
instruction. 1ST signal = 0 sets the segments in
off state. The status of the flip/flop is output to
DBS by the status read instruction. The display
on/off instruction does not influence data in RAM.
To control display data latch by this flip/flop, Cl
signal (display synchronous signal) should be input

A 9-bit counter that designates addresses of internal
display data RAM. X address counter (upper 3 bits)
and Y address counter (lower 6 bits) should be set
by the respective instructions.

Y Address Counter

1. X address counter
Ordinary register with no count functions. An
address is set by instruction.

2. Y address counter

correctly.

An address is set by instruction and it is increased
by I automatically by display data R/W operations.
The Y address counter loops the values of 0 to 63
to count.

Display Start Line Register

Display Data RAM

The register specifies a line in RAM that
corresponds to the top line of the LCD panel, when
displaying contents in display data RAM on the
LCD panel. It is used for scrolling the screen.

Dot data for display is stored in this RAM. I-bit
data of this RAM corresponds to light on (data = I)
and light off (data 0) of I dot in the display panel.
The correspondence between Y addresses of RAM
and segment PINs can be reversed by ADC signal.

6-bit display start line information is written into
this register by the display start line set instruction,
with high level of FRM signal signalling the start
of the display, the information in this register is
ttansferred to the Z address counter, which controls
the display address, and the Z addr:ss counter is
preset

=

As the ADC signal controls the Y address counter,
a reverse of the signal during the operation causes
malfunction and destruction of the contents of
register and data of RAM. Therefore, always
connect ADC pin to Vcc or GND when using.
Figure 7 shows the relations between Y address of
RAM and segment pins in the cases of ADC 1
and ADC 0 (display start line 0, 1/64 duty

=

=

=

cycle).

HITACHI

541

HD61102

-r--r-

-1-11-1-

LCD
display pattern

-1-1-

i---COM1
f----COM2
1---- COM3
1---- COM4
i---COM5
1---- COM6
1-----'_ COM7

-==±-I-JI-=11===
_

COM8
COM9

(HD61103AX1)
(HD61103A X2)
(HD61103A X3)
(HD61103A X4)
(HD61103A X5)
(HD61103A X6)
(HD61103A X7)
(HD61103A X8)
(HD61103A X9)

COM62
COM63
COM64

(HD61103A X62)
(HD61103A X63)
(HD61103A X64)

~ HD611 02 Pin Name I

Line 0
Line 1
Line 2

DBO(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MSB)

Display

RAM data

I

I I
I I
I I

I I

r::::
X. 7 ~r""" [l
1 0 0 0 0
Line 62 ---- - 1 1 1 1 1 0
Line 63 ----,- 0
0
0 0

o

o

o

I I I I I I

o

1 2 3 4 5

RAM Y Address

ADC • 1 (Connected to Vcc )

Figure 7 Relation between RAM Data and Display
542

HITACHI

HD61102

LCD
display pattern

,- ,.-....:
1
1
Y1

Display
RAUdata

_L- L.-'-'""

. . . ,.-n
I'
o1 o0 o0

(HD61103AX1)
(HD61103A X2)
(HD61103AX3)
(HD61103A X4)
(HD61103A XS)
(HD61103A X6)
(HD61103A X7)
(HD61103A X8)
(HD61103A X9)

COM62
COU63
COM64

(HD611 03AX62)
(HD611 03AX63)
(HD61103AX64)

.....fHD61102 Pin Namel
DBO(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MSB)

o0 o1
o0 o1
1 0 o 1
o1 o1
o0 1 1
o0 o1
o0 o1
o0 o0
o0 o0

UneO
Une 1
Une2

COM1
COt.12
COU3
COtM
COUS
COM6
COM7
COM8
COM9

I

I
I
I
I

I
I
I
I

I
I
I
I

Une62 ----- 1 1 1 1 1 0
Une63 ----0
0
0

o
I
o

o

o

I I I I I

1 2 345

616263

RAM Y Address

ADC • 1 (Connected to GND)

Figure 7 Relation between RAM Data and Display (cont)

HITACHI

543

HD61102
Z Address Counter

Liquid Crystal Display Driver Circuit

The Z address counter generates addresses for
outputting the display data synchronized with the
common signal. This coun~r consists of 6 bits and
counts up at the fall of the CL signal. At FRM
high, the contents of the display start line register
are preset in the Z counter.

The combination of latched display data and M
signal causes one of the 4 liquid crystal driver
levels, VI, V2, V3, and V4 to be output

Display Data Latch

Reset
The system can be initialized by setting RSf
terminal to low when turning power on.

1.
2•

The display data latch stores the display data
temporarily that is output from display data RAM
to the liquid crystal driving circuit
Data is latched at the rise of the CL signal. The
display on/off instruction controls the data in this
latch and does not influence data in display data
RAM.

Table 2

Itam
Reset time

Display off
Set display start line register
line 0

While RST is low level, no instruction except
status read can be accepted. Therefore, carry out
other instructions after making sure that DB4 = 0
(clear RESEn and DB? = 0 (ready) by status read
instruction.
The conditions of the power supply at initial power
up are as in table 2.

Power Supply Initial Conditions
Symbol

Min

Typ

Max

1.0

Unit
~s

Rise time

200

ns

Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off register and in RAM.
Vee

RST

544

HITACHI

----'.

HD61102
Display Control Instructions
Outline
Table 3 shows the instructions. Read/write (R/W)
signal, data/instruction (Off) signal and data bus
signals (DBO to DB7) are also called instructions
because the internal operation depends on the
signals from MPU.
These explanations are detailed in the following
pages. Generally. there are the following three
kinds of instructions.
1. Instruction to set addresses in the internal
RAM
2. Instruction to transfer data from/to the
intemalRAM
3. Other instructions

In general use, the second type of instruction are
used most frequently. Since Y address of the
internal RAM is increased by I automatically after
writing (reading) data, the program can be
shortened. During the execution of an instruction,
the system cannot accept instructions other than the
status read instruction. Send instructions from
MPU after making sure that the busy flag is 0,
which is the proof that an instruction is not being
excuted.

HITACHI

545

ISm

u.

....

0-

~
~

12

Code

::I

DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO

Fun~~ns

0

Controls display on/off. RAM data and internal
status are not affected. 1: on, 0: off.

Instructions

R/W D/I

Display on/off

0

0

Display start line

0

0

Set page (X address)

0

0

Set Y address

0

0

0

Y address (0-63)

Status read

1

0

Busy 0

ON/
OFF

0

1/0
Display start line (0-63)
Page (0-7)

0

~

RE- O
SET

0

-

::I

Write display data

Read display data

0

Specifies the RAM line displayed at the top of the
screen.

Write data

Read data

Note: 1. Busy time varies with the frequency (felK) of ,1, and ,2.
(1IfCLK ~ TBUSY ~ 31 fcLK>

Sets the page (X address) of RAM in the page (X
address) register.
Sets the Y address in the Y address counter.

0

0

0

;'

Reads the status.
RESET

!M

1: Reset
0: Normal

1>0<

1:11

ON.OFF

1: Display off
0: Display on

Busy

1: Executing internal operation
0: Ready

Writes data DBO (LSB)
to DB7 (MSB) on the
data bus into display
RAM.
Reads data DBO (LSB)
to DB7 (MSB) from the
display RAM to the data
bus.

~
III

cr

Has access to the

address of the display
RAM specified in
advance. After the
access, Y address is
increased by
1.

!

-="
5"

5l

HD61102
Detailed Explanation
1.

Display onloff
RIW
Code

011

OBO

OB7 - - - - - .........

o

o
-

high-order bit

Iow-order bit -

The display data appears when D is 1 and disappears when D is O. Though the data is not on the screen
when D =0, it remains in the display data RAM. Therefore, you can make it appear by changing D =0 into
D=1.

2.

Display start line
RIW
Code

o

011

OB7 - - - - - - -.........

o
-

A
high-order bit

A

low-order bit -

Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed at
the top of the screen.
Figure 7 shows examples of display (1/64 duty cycle) when the start line = 0-3. When the display duty
cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCD screen, from the line
specified by display start line instruction, is displayed.

HITACHI

547

HD61102

COM1

COM1
COM2
COM3
COM4
COM5
COM6
COM7
COMa
COM9

COM3
COM4
COM5
COM6
COM7
COMS
COM9

COM60
COM61
COM62
COM63
COM64

COM60
COM61
COM62
COM63
COM64

COM2

Start line. 0

Start line - 1

COM1
COM2
COM3
COM4
COMS
COM6
COM7
COMS
COU9

COM1
COM2
COM3
COM4
COM5
COM6
COM7
COMS
COM9

COM60
COM61
COM62
COM63
COM64

COM60
COM61
COM62
COM63
COM64
Start line-3

Start line. 2

Figure 7
548

Relation Between Start Line and Display

HITACHI

HD61102
3. Set page (X address)
RIW
Code

I

011

-

------

DBO

................

o

0

1

0

DB7

A

A

Iow-order bit -

high-order bit

X address AAA (binary) of the display data RAM is set in the X address register. After that, writing or
reading to or from MPU is executed in this specified page until the next page is set. See figure 8.
4. Set Y address

Code

RIW

011

DB7

-------.

0

0

o

A

I

-

...........

A

DBO
A

A

A

low-order bit -

high-order bit

Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Yaddress
counter is increased by 1 every time the data is written or read to or from MPU.

o1

Yaddress
2 ------------------------ 61 62 63

DBO

~~______p_ag_e_o________~
r

DB7
DBO
DB7

Page 1

1

X.O

1

X.1

r=~==~--------~

..--

,-DBO
DB7
DBO

..........
Page 6

Page 7

DB7

Figure 8

1X.,
1

X.7

Address Configuration of Display Data RAM

HITACHI

549

HD61102
5.

Status Read
FWI

Code

I

ON/OFF:
RESET:

6.

OB7

0

IBusy I

I
-

Busy:

Oil

.........
0

I

g~ IRESETI

high-order bit

OBO
0

I

0

I

0

I

0

low-order bit -

When Busy is 1, the LSI is executing internal operations. No instructions are accepted while
Busy is 1, so you should make sure that Busy is 0 before writing the next instruction.
Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is 1, the display is in off condition.
When ON/OFF is 0, the display is in on condition.
RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation
condition.

Write Display Data
FWI

Oil

...........

OBO

10101010101010

Codelol
-

OB7

high-order bit

°

low-order bit -

Writes 8-bit data 00000000 (binary) into the display data RAM. Then Y address is increased by 1
automatically.
7.

Read Display Data
011

ANI

Code

I
-

OB7

...........

OBO

101010101010101
high-order bit

°

low-order bit -

Reads out 8-bit data 00000000 (binary) from the display data RAM. Then Y address is increased by 1
automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of output
register in "FUNCTION OF EACH BLOCK".

550

HITACHI

HD61102
Use of HD61102
Interface with HD61103A (1/64 duty cycle)

At

Cf

1---------tCOM1
Vee
V1
V6
VS
V2
VEE

Vee
V1L, V1R
V6L,V6R
VSl, VSR
V21, V2R
VEE
GND
Vee

X1

)

Power supply circuit

)"

i

r-------~COM~m

0

~--~~----~--~

X~

HD61103A
SHL
DL
DS1
DR
DS2
TH
Cl1
M
FS
Cl2
MIS
FRM
FCS
111
112
STa

- :;:s-V- (V~)" - - -- - - - --

)

LCD panel

Open
Open
Y1 ----..,

M
CL
FRM

HD61102

V

External CR

Y~

Vee
V1L,V1R
V2L, V2R
V3L,V3R
V4L,V4R
VEE1, VEE2
GN

Vee
V1
V2
V3
V4
VEE

\~------------~I
CPU

R3=1sn

-10V

HITACHI

551

HD61102

~-----~

,,2

'\
\

Input

FAM

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I
11

I
I

I

I

I
I
I
I

.1
I
I
I

I
I
I
I
I
I

I
I
I
I
I

I
I
I

I
I
I

I
I
I
I

I
I
I
I

V5

I

-+.r1 ! ! ------+.r1 ! ! ------W1I I '. I I -----=rT9.
frame
~
-+-+-I
frame
.
I I -----==l"'4
I

!

X1

,

~ _____ ~ _____ ~

Cl

M

-------------------------

COM X2
(
)

X64

!

V
I

I

~

I

I
I

1

I
I
I
I
IV61

I

I

I

I

_____

-----

V2

I

.m
I
!i
IV1

I

~

I

I

I

I

I

I

I

I

IV11

)

I

Y64

i

IIII
I I I
I
I
I I I
I
I
I
I V1 I
II
I
I
V41 I
V3

I

I

I

I
I

I
I
I

I
I
I
I
I
I
I

I
I
I
I
I
I
I

i
I
I
I
I
I
I
I

I
I

I
I

I
I V1

!

!n

I
I
I

I

I

I
I

------t-H
! I Y~----L!...J
il~'I'
I
I
I
I
I

I

I
I
I
I

I
I

I

I
I !

SleJe<:!T~

rTl..'lL
------I!

I
IV5

I i .1l.n.L-

SEG

II

I

V61

I

-H-fl

I

V1

~

~
I
I
IV6

I

I
Y1

I

I

V5
I

I

_____ ~I
I

II

I
I
!V6

~
I

I
I
I
I
I

I
I
I
I
I
I

YL__

Non-selected

.1

.

!

I
I

The waveforms of Y1 to Y64 outputs vary with the display date. In this
example. the top line of the panel lights up and other dots do not.

Figure 9
552

LCD Driver Timing Chart (1164 duty cycle)

HITACHI

I
I
I V1

Jlrll
I
I

I

I
I

I

I

!

HD61102
Interrace with CPU
1.

Example or connection with HD6800

Decoder
A15
I

A1

t--r- I"\.

.,r;-

I

1_

J

VMA r--

~

CS2

Vcc .........

CS3

011

AO
ANI

ANI

H06800

H061102

1IJ2

E

DO
I

07

I
I
I

OBO
I

OB7

fVCC
RES

Figure 10

t

RST

Example or Connection with HD6800 Series

In this decoder (figure 10), addresses of HD61102 in the address area of HD6800 are:
Read/write of the display data
$FFFF
Write of display inslruction
$FFFE
Read out of status
$FFFE
Therefore, you can control HD61102 by reading/writing the data at these addresses.

HITACHI

553

HD61102
2.

Example of connection with 8D6801
74LS154
P10
P11
P12
P13
(lOS) SC1
(RIW) SC2

YO
A
V;1 I-r
B
I
I
I
C
I
Y15 ~
0
G1 G2
t J,

I

rII
..-

C§'i
~

Vr;c- CS3

RIW

P14

011

HD61102
No.1

HD6801
E

E

P30
P31
(Oat. bus)

OBO
OB1
I
I
I

I
I

P37

Figure 11
•

•

Example of Connection with 8D6801

Set HD6801 to mode S. PIO to Pl4 are used as
the output port and P30 to P37 as the data bus
74LSlS4 4-to-16 decoder generates chip select
signal to make specified HD61102 active after
decoding 4 bits of PIO to P13.
Therefore, after enabling the operation by PIO
to Pl3 and specifying D/I signal by Pl4,
read/write from/to the external memory area
($0100 to $OIFE) to control HD61102. In this
case, lOS signal is output from SCI and RIW
signal from SC2.
For details of HD6800 and HD6801, refer to
their manuals.

554

I

OB7

(table 11).

•

I
I

HITACHI

HD61102
Example or Application

H061102
No.9

HD61102
No. 10

-----------

HD61102
No. 16

LCD Panel
128 x480 dots

HD61102
No.2

Figure 12
Note:

HD61102
No.8

Application Example

In this example (figure 12), two HD611 03As output the equivalent waveforms. So, stand-alone
operation is possible. In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ... ,
and COM64 and COM128 to X64. However, for the large screen display, it is better to drive in 2
rows as in this example to guarantee the display quality.

HITACHI

555

HD61103A-----------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Description

Features
Dot matrix liquid crystal graphic display
common driver with low impedance
Low impedance: 1.5 ill max
Intemalliquid crystal display driver circuit: 64
circuits
Internal dynamic display timing generator
circuit
Selectable display duty ratio factor 1/48, 1/64,
1/96, 1/128
Can be used as a column driver transferring data
serially
Low power dissipation: During display: 5 mW
Power supplies:
Vee: +5 V ± 10%
VEE: 0 to -11.5 V
LCD driver level:
17.0 V max
CMOS process

The HD61103A is a common signal driver for dot
matrix liquid crystal graphic display systems. It
generates the timing signals (switch signal to
convert LCD waveform to AC, frame synchronous
signal) and supplies them to the column driver to
control display. It provides 64 driver output lines
and the impedance is low enough to drive a large

screen.
As the HD61103A is produced by a CMOS
process, it is fit for use in portable battery drive
equipments utilizing the liquid crystal display's low
power consumption. The user can easily construct a
dot matrix liquid crystal graphic display system by
combining the HD61103A and the column
(segment) driver HD61102.

Ordering Information
Type No.

Package

HD61103A

100-pin plastic QFP(FP-1 00)

Absolute Maximum Ratings
Item

Symbol

Limit

Unit

Note

Power supply voltage (1)

Va:;

-o.3.to +7.0

V

2

Power supply voltage (2)

VEE

Vee-19.O to Vee + 0.3

V

5

VTl

-0.3 to Vee + 0.3

V

2,3
4,5

Terminal voltage (1)
Terminal voltage (2)

VT2

VEE - 0.3 to Vee + 0.3

V

Operating temperature

Topr

-20 to +75

Storage temperature

Tstg

-55 to 125

°C
°C

Notes: 1.
2.
3.
4.
5.

556

If LSls are used beyond absolute maximum ratings, they may be permanently destroyed. We
strongly recommend you to use the lSI within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
Based on GND .. 0 V.
Applies to input terminals (except V1 l, V1 R, V2l, V2R, V5l, V5R, V6l, and V6R) and I/O
common terminals at high impedance.
Applies to V1l, V1R, V2l, V2R, V5l, V5R, V6l, and V6A.
Apply the same value of voltages to V1 land V1 R, V2l and V2R, V5L and V5R, V6l and V6R,
VEE (23 pin) and VEE (58 pin) respectively.
Maintain Vee ~ V1 l =V1 R ~ V6l =V6R ~ V5l = V5R ~ V2l = V2R ~ VEE

HITACHI

HD61103A
Pin Arrangement

X22
X21
X20

X19
X18
X17

X16
X15
X14
X13
X12
X11
X10

X9
X8
X7

X6
X5
X4
X3
X2

X1

VeE
V6L
V5L
V2L
V1L
Vee
DL
FS

(Top view)

HITACHI

557

HD61103A
Electrical Characteristics
DC Characteristics (Vee
Ta =-20 to +7S0 C)

=+5 V ± 10%, GND =0 V, VEE =0 to -11.5 V,
Specifications

Test Item

Symbol Min

Input high voltage

VIH

0.7 x VCC

Vee
0.3 x Vee

Typ Max

Input low voltage

VIL

GND

Output high voltage

VQi

Vee- 0•4

Output low voltage

VOL

Vi-Xj on resistance

~

Input leakage current

IILl

Input leakage current

IIL2

Operating frequency

Unit

Test Conditions Note

V
1

V
V

1ai--o·4mA

2

+0.4

V

1oJ-+O·4mA

2

1.5

kn

Vee- VEE-10V
load current
±150JAA

3

-1.0

+1.0

JAA

Vin - Oto Vee

4

-2.0

+2.0

5

fopr1

50

600

JAA
kHz

Vin - VEE to Vee
In master mode
External clock
operation

6

Operating frequency

fopr2

50

1500

kHz

In slave mode
Shift register

7

Oscillation frequency

fosc

315

585

kHz

cr-20pF'±5% .

8, 13

450

Rf-47kn±~

Dissipation current (1)

IGGl

1.0

mA

In master mode

9, 10

1/128 duty cycle

cr-20pF
Rf-47kn
Dissipation current (2)

IQG2

200

JAA

In slave mode
11128 duty cycle

9,11

Dissipation current

leE

100

JAA

In master mode
11128 duty cycle

9,12

Notes: 1.
2.
3.

558

Applies to input terminals FS, OS1, OS2, CR,"STIr, SHl, MIS, FCS, Cl1, and TH and 110
common terminals Dl, M, DR and CL2 in the Input state.
Applies to output terminals, .1, .2, and FRM and
common terminals DL, M, DR, and CL2 in
the output status.
Resistance value between terminal X (one of X1 to X64) and terminal V (one of V1 l, V1 R, V2l,
V2R, V5L, V5R, V6l, and V6R) when load current is applied to each terminal X.
Equivalent circuit between terminal X and terminal V.

va

HITACHI

HD61103A
RON

V1L, V1R
\2L,\2R

~L'~R

_____~§ __-+~

Te..'''''' X (Xl-X")

VsL,VsR

t

Connect one of the lines
4.
S.
6.

Applies to input terminals FS, OSl, OS2, CR, STB, SHL, MIS, FCS, CL1, and TH, VO common
terminals OL, M, DR and CL2 in the input status and NC terminals.
Applies to Vl L, Vl R, V2L, V2R, VSL, VSR, V6L, and V6R.
Don't connect any lines to Xl to X64.
External clock is as follows.
TH

TL
TH
Duty cycle. TH + TL x 100%

External clock
waveform

trcp
External

tfcp

I -, ~"I'"I
CR R

7.
8.

out
f!tc

Min

Typ

Max

Unit

45

so

SS

%

trcp

SO

ns

tfcp

SO

ns

C

Applies to the shift register in the slave mode. For details, refer to AC Characteristics.
Connect oscillation resistor (Rf) and oscillation capacitance (Cf) as shown in this figure.
Oscillation frequency (fosd is twice as much as the frequency (f+) at +1 or +2.

Cf.20pF
Rf .. 47kO

fosc-2 xfliJ

9.

No lines are connected to output terminals and current flowing through the input circuit is
excluded. This value is specified at VIH - Vee and VIL - GNO.
10. This value is specified for current flowing through GNO in the following conditions: Internal
oscillation circuit is used. Each terminal of OSl, OS2, FS, SHL, MIS, sm, and FCS is
connected to Vee and each of CL1 and TH to GNO. Oscillator is set as described in note 8.
11. This value is specified for current flowing through GNO under the following conditions: Each
terminals of OSl, OS2, FS, SHL, sm, FCS and CR is connected to Vee, CL1, TH, and MIS to
GNO and the terminals CL2, M, and OL are respectively connected to terminals CL2, M, and OL
of the H0611 03A under the conditions doscribed in note 10.

HITACHI

559

HD61103A
12. This value Is specified for current flowing through VEE under the condition described in note
10. Don't connect any lines to terminal V.
13. This figure shows a typical relation among oscillation frequency, At and ct. Oscillation
frequency may vary with the mounting conditions.

i
J

I
I

I
I

600

-----

400

-------- --------+----

I

I

--~--------~---I
I

I

Cf .20pF

I
I
I

I

I

I
I
I

I
I
I

I

200 --------~-------I
I

o

50 .

100

Rf (kn)

S60

HITACHI

HD61103A
AC Characteristics

(V cc = +5 V ± 10%, GND = 0 V, VEE = 0 to -11.5 V, Ta = -20 to +75°C)
1.

Slave Mode (MIS

= GND)

CL2
(FCS .GND)
(Shift clock)
CL2
(FCS. Vee)
(Shift clock)

DL (SHL • Vee)
DR (SHL • GND)
Input data

DR (SHL - Vee)
DL (SHL • GND)
Output data

Item

Min

Symbol

Typ

Max

Unit

CL2 low level width (FCS - GND)

tWLCL2L

450

ns

CL2 high level width (FCS - GND)

tWHCL2L

150

ns

CL2 low level width (FCS - Vee)

tWLCL2H

ns

CL2 high level width (FCS - VCC)

tWHCL2H

150
450

Data setup time

tos

100

ns

Data hold time

tOH

100

ns

Data delay time

too

Data hold time

tOHW

CL2 rise time

tr

30

ns

CL2falitime

tf

30

ns

Note

ns

200

ns
ns

10

Note: 1. The following load circuit is connected for specification.
Output O------~
Terminal

l
;J;:

30 pF (Includes jig capacitance)

HITACHI

561

HD61103A
1. Master Mode (MIS

= Vee, FCS = Vee. Cf =10 pF, Rf =47 W)

CL2
IOH

DL (SHL - Vee)
DR (SHL - GND)

DR (SHL - \be)
DL (SHL • GND)
IOFRM -+-ir;:=---=~-r--IOFRM
FRM

O.7Vee

M

O.3Vee

II

Ir

IWH81

,,1

,,2
II tWl.82 tr

562

HITACHI

HD61103A
Item

Symbol

Min

Data setup time

tos

20
40
5

Data hold time

tOH

Data delay time

too

Typ

Max

Unit
ILs
ILs

FRM delay time

toFRM

Mdelaytime

tOM

CL2 low level width

tWLCL2

35

ILs

CL2 high level width

tWHCL2

ILs

+2
+2

-2
-2

ILS
ILs

.1 low level width

tWL.1

35
700

~

tWL.2

700

ns

.1 high level width

twH+1

2100

ns

.2 high level width

twH+2

2100

ns

.1-.2 phase difference

t012

700

ns

.2-.1 phase difference

t021

700

ns

.1, ~ rise time

tr

150

ns

.1,.2 fall time

tf

150

ns

low level width

Note

ILs

HITACHI

ns

563

= S
~ en
...=t:=' o
»

~
V2L V6L
V1L V5L
X1

Vee
VEE

rr-

CL1

r-

TH

r-

GND

J:

~o
J:

-

r-

-

X2 ----

-

64 outDut terminal

~----

~

~

DL

...

r--- Logic
~

1

2

Bidirectional shift
register

62

63

64

Logic f-+-

DR

1--1-

-r
~

SHL
STB

i

I

Liquid crystal display
driver circuits

'---

~
~

V2R V6R
X62 X63 X64 V1R V5R

Oscillator

R

g~

if I.If

...........

Timing generation circuit

8-

C

MIS

FS

DS1DS2

01

FCS

02

M
CL2
FRM

CAl

HD61103A
Block Functions
Oscillator
The CR oscillator genemtes display timing signals and opemting clocks for the HD61102. It is required
when the HD61103A is used with the HD61102. An oscillation resistor Rf and an oscUlation capacitor Cf
are attached as shown in figure 1 and tenninal
is connected to the high level. When using an external
clock. input the clock into terminal CR and don't connect any lines to tenninal R and C.

m

R

CR

C

L:I:J
At

Figure 1

II

R

I
Open

CR

ci

I
f
External Open
clock

Cf

Oscillator Connection with HD61102

The oscillator is not required when the H06l103A is used with the HD61830. Connect terminal CR to the
high level and don't connect any lines to terminals R and C (figure 2).

CR

Figure 2

I

I

Open

Vee

I
Open

Oscillator Connection with HD61830

Timing Generator Circuit
The timing genemtor circuit genemtes display timing and opemting clock for the HD61102. This circuit is
required when the HD61103A is used with the H061102. Connect terminal MIS to high level (master
mode). It is not necessary when the display timing signal is supplied from other circuits. for example. from
HD61830. In this case connect the terminals FS. DSI. and DS2 to high level and MIS to low level (slave
mode).

Bidirectional Shift Register
A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from
DR to DL when SHL is at low level. In this case. CL2 is used as shift clock. The lowest order bit of the
bidirectional shift register. which is on the DL side. corresponds to Xl and the highest order bit on the DR
side corresponds to X64.

HITACHI

565

HD61103A
Liquid Crystal Display Driver Circuit
The combination of the data from tbeshift register with the M signal allows one of the four liquid crystal
display driver levels VI, V2, VS and V6 to be II'8IISferred to the OUIput tenninals (table I).

Table 1 Output Levels
Data from the

Shift Reglater

M

Output Leve.

V2

o
o

566

V6

o
o

HITACHI

V1
VS

HD61103A
HD61103A Terminal Functions
Terminal
Name

Number of
Terminals 110

Connected
Function
to

Voo
GND
VEE

1
1
2

Power
supply

V1L, V2L,
V5L, V6L,
V1R, V2R,
V5R,V6R

8

Power
supply

Vee - GND: Power supply for internal logic.
Vee - VEE: Power supply for driver circuit logic.
Liquid crystal display driver level power supply.
V1 L (V1 R), V2L (V2R):
V5L (V5R), V6L (V6R):

Selected level
Non-selected level

Voltages of the level power supplies connected to V1 L
and V1 R should be the same.
(This applies to the combination of V2L & V2R, V5L &
V5R and V6L & V6R respectively)

MIS

Vee or GND

Selects master/slave.
MIS • Vee: Master mode
When the H0611 03A is used with the HD611 02, timing
generation circuit operates to supply display timing
signals and operation clock to the HD611 02. Each of
110 common terminals DL, DR, CL2, and M is in the
output state.
MIS - GND: Slave mode
The timing operation circuit stops operating. The
H061103A is used in this mode when combined with the
HD61830. Even if combined with the HD61102, this
mode is used when display timing signals (M, data, CL2,
etc.) are supplied by another HD61103A in the master
mode.
Terminals M and Cl2 are in the input state.
When SHL is Vee, DL is in the input state and DR is in
the output state.
When SHL is GND, DL is in the output state and DR is in
the input state.

FCS

Vee or GND

Selects shift clock phase.
FCS • Vee: Shift register operates at the rising
edge of CL2. Select this condition
when HD611 03A is used with HD611 02
or when MA of the HD61830 connects
to CL2 in combination with the
HD61830.

FCS. GND: Shift register operates at the fall of
CL2. Select this condition when CL1 of
HD61830 connects to Cl2 in
combination with the HD61830.

HITACHI

567

HD61103A
HD61103A Terminal Functions (cont)
Terminal
Name

Number of
Terminals 110

FS

I

Connected
to
Function
VeeorGND

Selects frequency.
When the frame frequency is 70 Hz, the oscillation
frequency should be:
fosc - 430 kHz at FCS - Vee
fose - 215 kHz at FCS - GND
This terminal is active only in the master mode. Connect
it to Vee in the slave mode.

DS1,DS2

Vee or GND

2

Selects display duty factor.
Display Duty Factor

1/48

1/64

1196

1/128

DS1

GND

GND

Vee

Vee

DS2

GND

Vee

GND

Vee

These terminals are valid only in the master mode.
Connect them to Vee in the slave mode.

STB
lH

Vee or GND

CL1

CR,R,C

Input terminal for testing.
Connect STB to Vee.
Connect TH and CL1 to GND.

3

Oscillator.
In the master mode, use these terminals as shown
below.
Usage of these terminals in the master mode:
Internal oscillation

Rf

External clock
External

Cf

C"=t~
R

CR

,..o....r_n__c..I.'i_k_o_p...l.le..,n

cliR

CR

CI

In the slave mode, stop the oscillator as shown below:
Open

Vee

I

I

IR
2

°

HD61102

I
CI

Operating clock output terminals for the HD611 02.
Master mode: Connect these termi!1a1s to terminals
,1 and +2 of the HD611 02
respectively.
Slave mode:

568

CR

Open

HITACHI

Don't connect any lines to these
terminals.

HD61103A
HD61l03A Terminal Functions (cont)
Terminal
Name

Number of
Terminals 110

Connected
to
Function

FfN

0

HD61102

M

110

MBof
Signal to convert LCD driver signal into AC.
HD618300r
Master mode: Output terminal
MofHD61102
Connect this terminal to terminal M of

Frame signal.
Master mode: Connect this terminal to terminal FRM
of the HD61102.
Slave mode: Don' connect any lines to this
terminal.

the HD61102.
Slave mode: Input terminal.
Connect this terminal to terminal MB
of the HD61830.
CL2

110

CL10rMA
ofHD61830
orCLof
HD61102

Shift clock.
Master mode: Output terminal
Connect this terminal to terminal CL of
the HD61102.
Slave mode: Input terminal
Connect this terminal to terminal CL1
or MA of the HD61830.

DL,DR

2

110

OpenorFLM
of HD61830

Data JK) terminals of bidirectional shift register.
DL corresponds to X1's side and DR to X64's side.
Master mode: Output common scanning signal.
Don' connect any lines to these
terminals normally.
Slave mode: Connect terminal FLM of the HD61830
to DL (when SHL • Vee) or DR (when
SHL.GND)
MIS
GND
Vee

N}

SHL

5

SHL

Vee

GND

Vee

GND

DL

Output

Output.

Input

Output

m

Out(!ut

Out(!ut

Out(!ut

In(!ut

Open

Not used.
Don' connect any lines to this terminal.

VeeorGND

Selects shift direction of bidirectional shift register.
SHL

Shift Direction

Common Scanning Direction

Vee

DL-+DR

X1-+X64

GND

DL4-DR

X14-X64

HITACHI

569

HD61103A
HD61103A Terminal Functions (cont)
Terminal
Name

Number of
Terminals 1/0

X1-X64

64

o

Connected
to
Function
Liq uid crystal Liquid crystal display driver output.
display
Output one of the four liquid crystal display driver levels
V1. V2. V5. and V6 with the combination of the dat from
the shift register and M signal.

M

..J

L--..:.0---lr

Data~

~~~ut

\. V2 .\.V6 .\.V1 .\..V5 .\

Data 1: Selected level
0: Non-selected level
When SHL is Vee. X1 corresponds to COM1 and X64
corresponds to COM64.
When SHL is GND. X64 corresponds to COM1 and X1
corresponds to COM64.

570

H1TACHI

H: Vee

}~~

"-" means "open".

L: GNO
)

~

i!:

en

....

C\I

1m

'-~ fi> ~ ~ ~ t;

5 . .: '-

+1

9

Af: Oscillation resister

==

Cf: Oscillation capacitor
+2

FAM

M

CL2

SHL

OL

DR

Xl-X64

oomF~
ALL L L H H H H H -

B

J:
-

~

C

-

L L L H °H H H H H _ _

f
MB f
MA H
ro'!!f
ro'!!f
HD61830 H061830
L

L L L H H H H H H -

from MB
of

-

o

a

=
~;'
"CI

~

from MB from CLl H
HD60 1f830
COM1-COM64
of
of
-------------HD61830 H061830
from F~
L
of
COM64-COMl
HD61830

~

~

8

~

>

=
~

"CI

8

~

••

from F~
to OUOA
r"'
of
of HD61103A COM1-COM64
;.
HD61830
No.2"
to OUOA of from F~
HD61103A
of
COM64-COMl
No.2
HD61830

"5!.

n'

S'
:I

fromOUORof
from MA H HD61103A
COM65-COM128
of
___N_o_._l_ _ _ _ _ _ _ _ __

~830~830

~~

L

of HD61103A COM128-C0M65

~

·~1

o

HLLHH

LL
or
LH

At
H

Cf

RfCf

to +1
to +2
to FRM
to M
to CL
H
of
of
of
of
of
H061102 H061102 H061102 HD61102 H061102
L

COM1-COM64
COM64-COMl

toOUOR
to 1
to +2
to FRM
toM
to CL of H
of HD61103A COM1-COM64
H
Rf Cf
ot
of
of
of
H061102
No.2
Cf
. H061102 H061102 HD61102HHD6D611110302AHtoD6C1L210of3A
toOUOR
L of HD61103A
COM64-COMl

At

E

H L L H H

LL

~

No.2

from OUDR
H of HD61103A
N~l

F

~

L L L H H H H H H -

-

from M from CL2
of
of
HD61103AHD61103A
No.1
No.1
L

COM1-COM64

from OUOR
of HD61103A COM64-OOMl
No.1

::r:
0

m
:::

0

~

HD61103A
Outline of HD61103A System Configuration
1.

Use with HD61830

a. When display duty ratio of LCD is more than 1/64
HD61830
COM 1
COM64

HD61830

LCD

One HD611 03A drives
common signals.

Referte
Connection list A

One HD61103Adrives
common signals for
upper and lower
panels.

Refer to
Connection list A

Two HD61103As drive
upper and lower
panel separately
to ensure the
quality of display.
No. 1 and No.2
operate in parallel.

For both of No. 1
and No.2, refer to
Connection list A

LCD
Upper
Lower

HD61830

--t----.
LCD
Upper
Lower

b. When display duty ratio of LCD is from 1/65 to 1/128

572

Two HD611 03As
connected serially
drive common signals.

Refer to
Connection list B
for No.1.
Refer to Connection
list C for No.2.

Two HD61103As
connected serially
drive upper and
lower panels in
parallel.

Refer to
Connection list B
for No.1.
Refer to Connection
list C for No.2.

Two sets of
HD61103As connected
serially drive upper
and lower panels in
parallel to ensure
the quality of display.

Referte
Connection list B
for No. 1 and 3.
Referte
Connection list C
for No.2 and 4.

HITACHI

HD61103A
2.

Use with HD61l02 (1164 duty ratio)
COM1
COM64

LCD

One H061103A drives
common signals and
supplies timing
signals to the
H061102s.

Refer to
Connection list 0

One H0611 03A drives
upper and lower
panels and supplies
timing signals to
the H061102s.

Refer to
Connection list 0

H061102
Upper
Lower

Upper
Lower

Two H061103As drive
upper and lower
panels in parallel
to ensure the
quality of display.
No. 1 supplies
timing signals to
No.2 and the
H061102s.

HITACHI

Refer to
Connection list E
for No.1
Refer to
Connection list F
for No.2

573

HD61103A
Connection Example 1
Use with HD61102 (RAM type segment driver).

a. 1/64 duty ratio (See Connection List D)

Cf

~

Rf
+5Vj\l e)

Rl

R
Vee
R3 Vl
V1L, V1R
Q;OR3 V6
V6L,V6R
'---

Rl

R3V5
R3V2
VEE

-10 V ....

oV

.9

X64
(Xl)

COM64

M
CL
FRM
01
02

M
CL
FRM
01
02

•

..J

""
~

V5L, V5R
V2L, V2R
VEE

neontrast

J,.

c(
M

0
,...

co

GND
Open- DL
Open- DR

0

::t:

Vee
SHL I - DSl rDS2 r- I TH fCLl
FS r- I MIS r- I FCS r- l Sle l- I -

--

R3.150

The values of R1 and R2 vary with the LCD panel used.
When bias factor is 1/9, the values of Rl and R2 should satisfy
Rl
1
4R1 + R2-9
For example,

574

HITACHI

>~~~

J J J J 8~ w

>~~~>CJ~

b

>CJ>

Figure 1 Example 1
1.

HD61102

a: a: a: a:

v~v1vlJ k~

I

Note:

LCD panel

::t:

1ii

~V4

.

~

.!!I

R3

Rl

) )

en

~V3

R2

COMl

)

CR

:~R3

Rl

Xl
(X64)

r-- C

C
"!!J
dij'

c:

;:
N

~

S
'a
;"

...
~
~

..
......
r:a::
8

:I

j

0

;

;a

rtfUUlJUU1J JU1JUlJUl

B1 UlIlJ---lflIlJ
B2 TIT~~~11l[Y
,,
-- -47

,

I

~

-null

JttlL

--------------M1l
Ll
LJ ' -----------1L1

I

&.-

I
I

I

I
I

...0\

M

I

II

'

II

I

i
I

D-

c:

Xl
(X64)

I

X2

I

~
w w
w

~~

INoIe I Note
1 I
I

___

----------1 frame

I

V6 I Vl

-----------

I

I

V61

I
I

I
I

V2

I

:

II

~6
V6 -----------

V1

-----------

( ): at SHL - Low

I
I

I...J

I

II

I

I
I
I

I

___________

I

I

'-'

-----------

____ J.!I!!!'!__

I

'OIl!

I
I

&.-

I...J

INote I Nole
I I
I

'a
~

~

CL2

1JlflJ
L

I

DR
(OL)

n
n
;"

B2lflJl-1
I L
roLRJ-

n 'rn m--ril--CL2-1 ~ 1 ~ 2 ~13 L-~~~~~~~~~~~------~~~--~-----flJU1-J
FRM
I II I
II
~
---------------------

0;-

0;-

49

....

>

EI

....

48

Note: Phase difference between OL (DR) and CL2

~

•

I
I

I

I

-tJ1
I

w

:r:t:J

0)
~

~

oCo)

>

HD61103A
Connection Example 2
Use with HD61830 (Display controller).
a. 1/64 duty ratio (See Connection list A)

Open
Vee
Open

C
CR
R

X1
(X64)

Vee

Vee

X64
(X1)

V1

V1L, V1R

V6

V6L, V6R

1\1

\ic:
c:
8

~

COM64

~

.!!!

V5

V5L,V5R

V2

V2L, V2R ~
0

C\I

U;

QI
QI
CI)

M
CL2
DL(DR)
DR(DL)

0

VEE

GND

GND

Open
Open
Open

FRM
,,1
,,2

MB
CL1
FLM
Open
Vee

J:

VEE

SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STB

Figure 3

576

LCD panel

J:

lii

)(

w
.2

) )

)
CI)

E

c:

COM1

Example 2 (1/64 duty ratio)

HITACHI

HD61830
(Display Controller)

HD61103A

1~
~

~ ¢ ~~
>

>

>

----- --------------------------- ---------- ------------

_______ .1...-_.,.

~

.9

•

...J

J:

en

C\I

1ii

------- ---------- ------------T"'==---'
~~

~

,~

--------

>

x~ ~
__

_______________J/
oes~9aH WOJ:I

Figure 4 Example 1 Waveform (1/64 duty ratio)

HITACHI

577

HD61103A
b. 1/100 duty rati.o (See Connection list B, C)

torn

Vee

~n
~Vee - - - - - - - - - , , - f V ee

a::

50

V1
CD

1

V1L,V1R
....----.....,;I+IV6L, V6R
V6 _ _ _...J .---t-HI-HV5L, V5R
r--.-t-Ht-HV2L, V2R

r+t-t-t-H~~b

c

V5-----'

c

V2-----l

t

SHLI-r
OS11-rOS21-1THICL11-

I

~ ~:= r

~

t/)

~

.....f!!

~ s:!

1ii

o

8

"Vee

FCSrSTBrX1 .t---,

o 0 - (X64

l

:I:Z~

VEE-----+
GN""D------H

00

X64
(X1)

C\I ~ ~

"

d5~

2

1+

2~C?::::;

FLMMAMB-

}

f[::J

oe.e.
...Ja::

"--- COM1

r
LCD
L---~COM64 Panel
r-------i COM65

X1
(X64

W (

} r
i

Vee 0 0
V1L. V1R
X36.t-_.....
V6L.V6R
(X29
~ V5L.V5R
SHLI-' - - -..... V2l. V2R
4 - - - - 1 VEE
'G ~ OS11-'-----tGNO
~
-; OS21-~

e.

Open- C
Vee- CR
Open- R

S
....

...J

TH I-

t/)

Cl11-

:I:

1ii FS I-r
CD N .!!
0 0 - MlSI:I: Z ~ FCS I-r
STBI-r

Vee

Figure 5
578

Example 2 (VIOO duty ratio)

HITACHI

(

i

COM100

MB

I

~

•

""'IFLM

~

:z:

:3!

:

01

%

i0

~

";r
N

......

...=
=
~

....

~
•

~

:z:

!l

,

DR(DL) A'
H08"03 I
No. ,

X,

(X64)

(II

'I (X64)
X1

~

s
.,...

""'1
~

___

X36
(X29)

rlvs
'I
'I' V,S

M
II

~

V6 V2 IV5
I

( ): SHL - Low laval

: : M J l•l I3,---

,"
'
"
,
'' "
"
"I ,
"
,

'"

I

'I

vs I,

--

__

VS

U
__ , ,
I

I

!I

UVi
--,I ',
, ,'va
II

'~

In [.
I

Lj

Y

",

I

I

I

I

I I I

I

---,

mm
I

I

J'L' ,
II

IOl

----,

I

I

I

I

,

I

, I ,I ---Ik! V5
l

V6

I

--

I

'"
, I,
'"
," I , "
___,, I
"
-, I
n_-,
,,"
,II ,I"" ,I
I
I

---,
'
" I
I
,I"" ,,I
I I

I I ,!
!!

V6

I

___

I

--h::-fVil
!Vi! Ivs
'

CI

"'II!

0
.....

I

n

X64
(X1)

Do

•=:

'
•
'
""" I
i I
, ,

----=t~I
,

1 frama

n

1lFlM

fD

•ClEI

1frama

rp
---.JiL-'--

MA

1

---

~m
-- MJU
fl.!L.rL_~
-- =:::I..,

V2

I

I

I

I.

I

I

mir-I, ___,I,ik - I
I

V&

W

n_

~I
,I ,I

___

W

I V&

•

8
en
.....
.....
o

w

~

>

HD61202------------(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Description

Features

HD61202 is a column (segment) driver for dot
matrix liquid crystal graphic display systems. It
stores the display data transferred from a 8-bit
micro controller in the internal display RAM and
generates dot matrix liquid crystal driving signals.

Dot matrix liquid crystal graphic display
column driver incorporating display RAM
RAM data direct display by internal display
RAM
RAM bit data 1: On
RAM bit data 1: Off
Internal display RAM address counter preset,
increment
Display RAM capacity: 512 bytes (4096 bits)
8-bit parallel interface
lnternalliquid crystal display driver circuit: 64
Display duty cycle:
Drives liquid crystal panels with 1132-1/64
duty cycle multiplexing
Wide range of instruction function:
Display Data ReadlWrite, Display On/Off, Set
Address, Set Display Start Line, Read Status
Lower power dissipation: during display 2 mW

Each bit data of display RAM corresponds to the
on/off state of a dot of a liquid crystal display to
provide more flexible than character display.

As it is internally equipped with 64 output drivers
for display, it is available for liquid crystal graphic
display with many dots.
The HD61202, which is produced in the CMOS
process, can complete portab!e battery drive
equipment in combination with a CMOS microcontroller, utilizing the liquid crystal display's low
power dissipation.

max
Power supply: Vee: 5 V ± 10%
Liquid crystal display driving voltage: 8 V to
17.0 V
CMOS process

Moreover it can facilitate dot matrix liquid crystal
graphic display system configuration in
combination with the row (common) driver
HD61203.

Ordering Information

580

Type No.

Package

HD61202

100-pin plastic OFP(FP-1 00)

HD61202TFIA

100-pin thin plastic OFP(TFP-60)

HD61202D

Chip

HITACHI

HD61202
Absolute Maximum Ratings
Item

Symbol

Value

Unit

Note

Supply voltage

Vet;

-0.3 to +7.0

V

2

VEE1
VEE2

Vet; -19.0 to Vet; + 0.3

V

3

Terminal voltage (1)

Vn

VEE - 0.3 to Vet; + 0.3

V

4

Terminla voltage (2)

VT2

-0.3 to Vet; + 0.3

V

2,5

Operating temperature

Topr

-20 to +75

°C

Storage temperature

Tstg

~5to+125

°C

Notes:

1.

2.
3.
4.

5.

lSls may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended operation
conditions.
Using them beyond these conditions may cause malfunction and poor reliability.
All voltage values are referenced to GNO - 0 V.
Apply the same supply voltage to VEE1 and VEE2.
Applies to V1 l, V2l, V3l, V4l, V1 R, V2R, V3R, and V4R.
Maintain
Vet; ~ V1 l '" V1 R ~ V3l '" V3R ~ V4l • V4R ~ V2l '" V2R ~ VEE
Applies to M, FRM, Cl, RST, ADC, +1,1112, CS1, CS2, CS3, E, FWI, OIl, and 080-087.

HITACHI

581

HD61202
Pin Arrangement

ADC
M
Vee

V4R
V3R
V2R
V1R
VEE2

Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47

HD61202
(FP-100)

Y46

Y45
Y44

Y43

(Top View)

582

HITACHI

HD61202

V2R
V1R
VEE2
Y64

HD61202TFIA
(TFP-100)

(Top View)

HITACHI

583

HD61202
Electrical Characteristics
(GND 0 V, Vee 4.5 to 5.5 V, Vee - VEE
+75°C)

=

=

=8 to 17.0 V, Ta =-20 to

Limit
Item

Symbol Min

Input high voltage

VIHC

0.7 x Vee

Typ

Max

Unit

Vee

V

VIHT

2.0

Vee

V

Input low voltage

VILC

0

0.3 x Vee

V

VILT

0

0.8

V

Output high voltage

Vat

2.4

Output low voltage

VOl.

V
0.4

V

IoH - -20511A
lot. .. 1.6 mA

3
3
4
5

+2.0

IIA

Vin. Vee-Vee

6

7.5

kn

Vee- VEE-15V
±ILOAO. 0.1 mA

8

Icc (1)

100

7

500

IIA
IIA

During display

Icc (2)

During access
access cycle - 1 MHz

7

+1.0

-5.0

+5.0

liquid crystal supply
leakage current

ILsL

-2.0

Driver on resistance

~

Dissipation current

584

2

Vin .. GND-Vee

-1.0

ITSL

8.

2

IIA
IIA

IlL

Three-state (off)
input current

1.
2.
3.
4.
5.
6.
7.

Note

Vin - GND-Vee

Input leakage current

Notes:

Te8t Condition

Applies to M, FRM, Cl, RST, ~1, and +2.
Applies to CS1, CS2, CS3, E, AIW, OIl, and DBO-DB7.
Applies to DBO-DB7.
Applies to terminals except for DBO-DB7.
Applies to DBO-DB7 at high impedance.
Applies to V1 l-V4l and V1 R-V4R.
Specified when liquid crystal display is in 1/64 duty cycle mode.
Operation frequency
fCLK - 250 kHz (~1 and +2 frequency)
fM _ 70 Hz (FRM frequency)
Frame frequency
Specified in the state of
Output terminal: not loaded
Input level:
VI-! '" Vee (V)
VIL-GND(V)
Measured at Vee terminal
Resistance between terminal Y and terminal V (one of V1 l, V1 R, V2l, V2R, V3l, V3R, V4l,
and V4R) when load current flows through one of the terminals Y1 to Y64. This value is
specified under the following condition:

HITACHI

HD61202

V1L "
V2L =

Vee - VEP 15.5 V
V1R. V3L:< V3R'" Vee - 217 (Vee - VEE)
V2R • V4L .. V4R" Vee + 2/7 (Vee - VEE)

RON

V1L • V1R

0

V3L. V3 R

0

V4L. V4R

0

"---0 Terminal Y
(Y1-Y64)

V2L. V2R

The following is a description of the range of power supply voltage for liquid crystal display drive. Apply·
positive voltage to VIL = VIR and V3L = V3R and negative voltage to V2L = V2R and V4L = V4R
within the flY range. This range allows stable impedance on driver output (RON). Notice that tlV depends
on power supply voltage Vee - VEE.

_r---------- Vee

-------- V1 (V1 L = V1 R )

AV

Range of Power Supply
Voltage for Liquid Crystal
Display Drive

---- V3 (V3L = V3R)
~5.0

~

~
3 ---------AV

------------ V4 (V4L = V4R )
-------------- V2 (V2L = V2R )
VEE

Correlation between Driver
Output Waveform and Power
Supply Voltages for Liquid
Crystal Display Drive

8
Vee - VEE (V)

17.0

Correlation between Power
Supply Voltage Vee- V EE and AV

HITACHI

585

HD61202
Terminal Configuration
Input Terminal
Applicable terminals:
__
M, FRM, Cl, RST, .1, .2, CS1, CS2, CS3,

Vee

E, RIW, on, ADC

~t---PMOS

~

NMOS

InputOutput Terminal
Applicable terminals: DBo-DB7

r'~~J
PMOS

NMOS

Vee

,------ ---I
I
r--Enable

,,IpMOS
,

jt-'
,,

,: Data
'NMOS
I
~------------~,,
,L _________1,, (Output circuit)
[three state))

Output Terminal
Applicable Terminals:
Y1-Y64
V1l, V1R
Vee

..r=-

PMOS

V3l,V3R

Vee

..r=-

NMOS
NMOS

VEE

S86

HITACHI

V4l,V4R
V2l, V2R

HD61202
Interface AC Characteristics
MPU Interface
(GND = 0 V, Vee = 4.5 to 5.5 V, Ta = -20 to +75°C)
Unit

Note

1000

ns

1,2

PWEH

450

ns

1,2

E low level width

PWEL

450

ns

1,2

Item

Symbol

Min

E cycle time

tcvc

E high level width

Typ

Max

E rise time

tr

25

ns

1,2

E fall time

tf

25

ns

1,2

Address setup time

tAS

140

ns

1,2

Address hold time

tAH

10

ns

1,2

Data setup time

tosw

200

Data delay time

tooR

Data hold time (Write)

tCHW

10

ns

1

Data hold time (Read)

tOHR

20

ns

2

320

ns

1

ns

2,3

Notes: 1.
tCYC

E

PWEH

PWEL

It
tr

tAH

RIW

CS1-CS3
011

2.0V
0.8 V
tosw

2.0V

DSo-DS7

0.8 V

Figure 1

CPU Write Timing

HITACHI

587

HD61202
Notes: 2.

~----------tc~yC~========~
E

....--- PWEL.-_....--PWEH-

ANI

CS1-cs3

2.0 V

011

0.8 V

OBO-OB7
0.4 V '--_ _- J

Figure 2 CPU Read Timing
3.

OBO-OB7: load circuit

RL.2.4k n

Test
point

01
o-.......--.--HI---.....

R

588

RL

R -11 kn
C - 130 pF (including jig capacitance)

02
03
D4

HITACHI

Oiodes 01-D4 are all 182074

®.

HD61202
Clock Timing
(GND = 0 V, Vee = 4.5 to 5.5 V, Ta = -20 to +75 D C)
Limit
Item

Symbol

Min

.1, t2 cycle time

tcyc

2.5

.1 low level width

tWl.1

t2 low level width

tWl.2

Typ

Max

Unit

Teat Condition

20

~s

Fig. 3

625

ns

Fig. 3

625

ns

Fig. 3

.1 high level width

t\VHt1

1875

ns

Fig. 3

.2 high level width

t\VHt2

1875

ns

Fig. 3

.1--.2 phase difference

t012

625

ns

Fig. 3

t2--.1 phase difference

t021

625

ns

Fig. 3

.1, .2 rise time

tr

150

ns

Fig. 3

.1, t2 fall time

tf

150

ns

Fig. 3

tWHa2

Figure 3

External Clock Waveform

HITACHI

589

HD61202
Display Control Timing
(GND = OV, Vee = 4.5 to 5.5 V, Ta = -20 to +75 °C)
Limit
Item

Symbol

Min

Max

Unit

Te" Condition

FRM delay time

foFRM

-2

+2

Fig. 4

Mdelaytlme

toM
twLa.

-2

'+2

Cl. low level width

35

JUI
JUI
JUI

Cl. high level width

tWHCl,

35

1'.

Fig. 4

CL

Typ

O. 7VCC "'14'---11

FRM

Figure 4

590

Display Control Signal Waveform

HITACHI

Fig. 4
Fig. 4

HD61202
Block Diagram

a: a: a: a:
>~~~

------------------I ....

1(\II (") I driver
Li~uid ~rys~al display
CircUit

M

~

. .1(\It (")1
~:J

ADC

~

'"

.D
CD

~

:i.

01
0
"It

!

11

Vee,- t-GND - t-VEE1 - f0-

~

1;j
-0

~

111

!

-0

1-----

I
I
I
I
_I

el
81
8",I1

-I
C: I

III
III

!

11

L

VEE2,- t--

8
-0

is

Ol

..

~:J

~

8

~ ~I~t-

Display date latch

I~I -

-.

~ f31~t--

co

CL
FRM

~
1: ..

'" CD
1ii1ii

N

~.~

'-

lil-CD
.c:

1""""-

1;-

~~
.- c: ~--

c=

Co

co

":r T
-- ----- ------ ----------

Instruction
register

,

Input
register

co~
OCI
SI
I
I
I
1______ - - - - - -

.51

(")

Output
register
co~

110 buffer
~--

- co-r----------- J

HITACHI

~
flag

i

:

......

RST

r-- 1/J1
r-- 1/J2

591

HD61202
Terminal Functions
Terminal Number of
Connected
Name
Terminal. 110 to
Function.
Vcc
GNO

2

Power
supply

Power supply for internal logic.
Recommended voltage is:
GND-OV
Vcc· SV ±10%

VEE1
VEE2

2

Power
supply

V1L. V1R
V2L. V2R
V3L. V3R
V4L.V4R

8

Power
supply

Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is Vcc - VEE - 8 to 17.0
V. Connect the same power supply to VEE1 and VEE2· VEE1
and VEE2 are not connected each other in the LSI.
Power supply for liquid crystal display drive.
Apply the voltage specified depending on liquid crystals
within the limit of VEE through Vcc.
V1L (V1R). V2L (V2R): Selection level
V3L (V3R). V4L (V4R): Non-selection level
Power supplies connected with V1 Land V1 R (V2L & V2R.
V3L & V3R. V4L & V4R) should have the same voltages.

3

MPU

Chip selection.
Data can be input or output when the terminals are in the
following conditions:
Terminal Name
CS3
Condition

E

MPU

L

Enable.
At. write(RIW • Low):
At. read(RIW • High):

MPU

Oil

592

MPU

L

H

Data of DBO to DB7 is latched at
the fall of E.
Data appears at DBO to DB7 while
E is at high level.

Read/write.
RIW. High:

Data appears at DBO to DB7 and can be
read by the CPU.
When E • high. CS1. CS2 • low and CS3 high.

RIW - Low:

DBO to DB7 can accept at fall of E when
CS1. CS2 - low and CS3 - high.

Data/instruction.

011 = High:

Indicates that the data of DBO to DB7 is
display data.

011. Low:

Indicates that the data of DBO to DB7 is
display control data.

HITACHI

HD61202
Terminal Functions (cont)
Terminal Number of
Connected
Name
Terminals 1/0 to
Functions
AOO

I

Vco'GND

Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.

ADC • High:
ADC. Low:
DB1-DB7

8

M

Y1: SO, Y64: $63
Y64: $0, Y1: $63

va common terminal.

1/0

t.RJ

Data bus, three-state

I

HD61203

Switch signal to convert liquid crystal drive waveform into
AC.

HD61203

Display synchronous signal (frame signal).

FRM

Presets the 6-bit display line counter and synchronizes the
common signal with the frame timing when the FRM signal
becomes high.
CL

HD61203

2

HD61203

Synchronous signal to latch display data. The rising CL
signal increments the display output address counter and
latches the display data.
2-phase clock signal for internal operation.
The.1 and .2 clocks are used to preform operations (1,0 of
display data and execution of instructions) other than
display.

Y1-Y64

64

o

Liquid
crystal
display

Liquid crystal display column (segment) drive output.
These pins outputs light on level when 1 is in the display
RAM, and light off level when 0 is it.
Relation among output level, M, and display data (D) is as
follows:

M

J

D~

~~:ut
RST

CPU or
external CR

IYtly3.IY~IY11

The following registers can be initialized by setting the RST
signal to low level.
1.

Onloff register 0 set (display off)

2.

Display start line register line 0 set (displays from
line 0)

After releasing reset, this condition can be changed only by
instruction.

3
Note:

Open

Unused terminals. Don't connect any lines to these
terminals.

1 corresponds to high level in positive logic.

HITACHI

593

HD61202
Function of Each Block
Interface Control

1. VO burrer
Data is transferred through 8 data bus lines (D~
DB7).
DB7: MSB (Most significant bit)
DBO: LSB (Least significant bit)
Data can neither be input nor output unless esT to
CS3 are in the active mode. Therefore, when esT
to CS3 are not in active mode it is useless to
switch the signals of input terminals except m
and ADC; that is namely, the internal state is
maintained and no inslruCtion excutes. Besides, pay
attention to 1ST and ADC which operate
irrespectively of m to CS3.
2.

b. Output register
The output regist« is used to store data temporarily
that is read from display data RAM. To read out the
to CS3 should be in
data from output regista",
the active mode and both D/I and RIW should be 1.
With the read display data instruction, data stored in
the output register is output while E is high level.
Then, at the fall ofE, the display data at the
indicated address is latched into the output register
and the address is increased by 1.

m

The contents in the output register are rewritten by
the read display data inslruCtion, but are held by
address set instruction, etc.

Register

Both input regist« and output register are provided

to interface to an MPU whose speed is different
from that of internal operation. The selection of
these registers depend on the combination of RIW
and D/I signals (table 1).

Therefore, the data of the specified address cannot
be output with the read display data instruction
right aft« the address is set, but can be output at
the second read of data. That is to say, one dummy
read is necessary. Figure 5 shows the CPU read
timing.

a. Input register

The input regist« is used to store data temporarily
before writing it into display data RAM.
The data from MPU is written into the input
register, then into display data RAM automatically
by internal operation. When m to CS3 are in the
active mode and D/I and RIW select the input
register as shown in table I, data is latched at the
fall of the E signal.

Table 1
D/I

Register Selection
R/W

Operation
Reads data out of output register as internal operation (display data RAM .... output
register)

o
o
o

594

Writes data into input register as internal operation (input register .... display data RAM)
Busy check.. Read of status data.

o

Instruction

HITACHI

011

~I
..

ANI

val

E

c:

_ _ _ _ _ _ _---11-

--- 1

1 - 1 ' - - _.....

!II

:I

~
0

::I:

n
"'II
c:::

".,
!II

51"
;.
IIQ

N

OBO-OB7

N+ 1
[ Dataaladdress N

register

Q.

~

r

Address

Output

I Busy
I check

Write
address
N

Busy

check

Read
data
(dummy)

I

Busy

check

I

Read
data at
address
N

N+2
Data at address N + 1
Busy

check

I

Data read
address
N+ 1

::r:

o

0)
~

~

~

o

~

HD61202
Busy Flag
Busy flag = I indicates that HD61202 is operating
and no instructions except status read instruction
can be accepted. The value of the busy flag is read

out on DB? by the status read instruction. Make
sure that the busy flag is reset (0) before issuing
instructions.

E _ _....
BUSy _ _ _ _.....1

I..-

flag

1IfClx:5T Busy:53IfCLK

TBusy

f CLI( is" 1, ,,2 frequency

Figure 6
Display On/Orr Flip/Flop
The display on/off flip/flop selects one of two
states, on state and off state of segments YI to
Y64. In on state, the display data corresponding to
that in RAM is output to the segments. On the
other hand, the display data at all segments
disappear in off state independent of the data in
RAM. It is controlled by display on/off
instruction. R]'f signal = 0 sets the segments in
off state. The status of the flip/flop is output to
DB5 by status read instruction. Display on/off
instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL
signal (display synchronous signal) should be input
correctly.

Busy Flag
transferred to the Z address counter, which controls
the display address, presetting the Z address
counter.

x,

Y Address Counter

A 9-bit counter which designates addresses of the
internal display data RAM. X address counter
(upper 3 bits) and Y address counter (lower 6 bits)
should be set to each address by the respective
instructions.
1. X address counter
Ordinary register with no count functions. An
address is set by instruction.

2. Y address counter

Display Start Line Register

An address is set by instruction and is increased by

The display start line register specifies the line in
RAM which corresponds to the top line of LCD
panel, when displaying contents in display data
RAM on the LCD panel. It is used for scrolling of
the screen.
6-bit display start line information is written into
this register by the display start line set
instruction. When high level of the FRM signal
starts the display, the information in this register is
596

I automatically by R/W operations of display data.
The Y address counter loops the values of 0 to 63
to count.

Display Data RAM
Stores dot data for display. I-bit data of this RAM
corresponds to light on (data = I) and light off (data
= 0) of I dot in the display panel. The
correspondence between Y addresses of RAM and
segment pins can be reversed by ADC signal.

HITACHI

HD61202
As the ADC signal controls the Y address cOWlter,
reversing of the signal during the operation causes
malfunction and destruction of the contents of
register and data of RAM. Therefore, never fail to
connect ADC pin to Vcc or GND when using.

Figure 7 shows the relations between Y address of
RAM and segment pins in the cases of ADC = 1
and ADC 0 (display start line 0, 1/64 duty
cycle).

=

=

HITACHI

597

HD61202

--COM1
--COM2
:""'---COM3
'----COM4
---COMS.
---COM6
---COM7

LCD
display pattern

-l--:ti~==COM8
COM9

~4-~r~-___

• • !-----'

~

_____ I

L,-L,..-I--rL,-L............' - - - - - -

I

COM62
COM63
COM64

(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203

(HD61203 X62)
(HD61203 X63)
(HD61203 X64)

yy
1
Line 0 ----- o 1
Une 1 ----- 1 0
0
Une2 ----- 1 0
0
1 0 o 0 1 0
X.O 1 1 1 1 1 0
1 0 o 0 1 0
Display
1
0 o 0 1 0
RAM data
o0 0 0 0 0
o0 0 0 0 0

I

2 3 Y64 --4HD61202 Pin Name
DBO(LSB)
000 1
000 1
DB1
1 0 0 1
DB2

o1 0 1
o0 1 1

DB3
D84
DBS
DB6
DB7(MSB)

000 1
000 1
o0 0 0
o 000
::::: _____ I.--"'"

X.7

...o

I
I
I
I

-

n

1 o 0 0 0
Une62 ----- 1 1 1 1 1 0
Une63 ----- o 0 o 0 o 0

I I I I I I

o

1 2 3 4 S

ADC -

I
I
I
I

I
I
I
I

r--

616263

RAM Y Address

1 (Connected to Vee>

Figure 7 Relation between RAM Data and Display
598

X1)
X2)
X3)
X4)
XS)
X6)
X7)
X8)
X9)

HITACHI

HD61202

--COM1
--COM2

(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203

--CQM3

--C0M4

LCD
display pattern

--CQM5

--COM6
--COM7
~
COM9
~:±:ti:tjt===~=t:ti:t====COM8

----- -,----- II
----::=: ..... _--

-

COM62
COM63
COM64

(HD61203 X62)
(HD61203 X63)
(HD61203 X64)

VVVV
Line 0 ---Line 1 ---Line 2 ---x.O
Display
RAM date

o1

_____0
o 0 -----

1
1
1
1
1
1
0
0

0
0
0
0
0
0
0
0

Line 62 ---Line 63 ----

_____0

1
----_____0
_____0
_____0
_____0
_____0

-----0

::::::::

X.1

X.7

~ ~

1

1 1
1 000
1 000
1 000
1 1 1 1
1 000
1 000
00 0 0
o0 0 0

...
.... -rr
o 1 o 0 o 0 '-

001
001
001
1 o 1
o1 1
001
001
000
000

-I..-

--

X1)
X2)
X3)
X4)
X5)
X6)
X7)
X8)
X9)

I

--1HD61202 Pin Name
DBO(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MSB)

I
I
I
I

I
I
I
I

I
I
I
I

- 1 1 1 1 1 0 --:::::Iffi=~
- o0 o0 o0
I I I I I I
1 2 3 4 5

o

616263

RAM VAddress

ADC • 0 (Connected to GND)

Figure 7

Relation between RAM Data and Display (cont)

HITACHI

599

HD61202
Z Address Counter

Reset

The Z address counter generates addresses for
outputting the display data synchronized with the
common signal. This coonlei' consists of 6 bits and
counts up at the fall of the CL signal. At the high
level of FRM, the contents of the display start line
register is preset at the Z counter.

The system can be initialiZed by setting 1ST
tecminal at low level when turning power on.

Display Data Latch

status read can be accepted. Therefore, execute other
instructions after making sure that DB4 =0 (clear

1. Display off
2. Set display start line regiSleI' line O.
While

The display data latch stores the display data
temporarily that is output from display data RAM
to the liquid crystal driving circuit. Data is latched
at the rise of the CL signal. The display· on/off
instruction conuols the data in this latch and does
not influence data in display data RAM.

m

is low level, no instruction except

=

RESET) and DB7
0 (Ready) by status read
instruction. The conditions of power supply at
initial power up are shown in table 1.

Liquid Crystal Display Driver Circuit
The combination of latched display data and M
signal causes one of the 4 liquid crystal driver
levels, VI, V2, V3, and V4 to be output

Table 1
Item
Reset time

Power Supply Initial Conditions
Symbol

Min

Typ

Max

Unit

200

ns

1.0

Rise time

Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off regislei' and in RAM.
.
Vec

0.3Vec

600

HITACHI

HD61202
Display Control Instructions
Outline
Table 2 shows the instructions. Readlwrite (RIW) signal, data/instruction (0/1) signal, and data bus signals
(OBO to DB7) are also called instructions because the internal opemtion depends on the signals from the
MPU.
These explanations are detailed in the following pages. Generally, there are following three kinds of
instructions:
1. Instruction to set addresses in the internal RAM
2. Instruction to transfer data from/to the internal RAM
3. Other instructions
In general use, the second type of instruction is used most frequently. Since Y address of the internal RAM
is increased by 1 automatically after writing (reading) data, the progmm can be shortened. During the
execution of an instruction, the system cannot accept instructions other than status read instruction. Send
instructions from MPU after making sure that the busy flag is 0, which is proof that an instruction is not
being excuted.

HITACHI

601

s

S
en

..

Table 2 Instructions

N

o
N

Cod.

l:

~o

Instructions

R/W DII

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Functions

Display on/Off

o

o

o

Display start line

o

o

Set page (X address)

0

o

Set address

o

o
o

Status read

o

1/0

Display start line (0-63)

o

Specifies the RAM line displayed at the top of the
screen.
Sets the page (X address) of RAM at the page (X
address) register.

Page (G-7)

o

Y address (0-63)

Busy 0

ONI

Reset 0

Sets the Y address in the

0

OFF

Controls display onloff. RAM data and internal
status are not affected. 1: on. 0: off.

o

o

Y address counter.

Reads the status.
RESET

1: Reset
0: Normal

:I:

ON.OFF
Busy

1: Display off
0: Display on

1: Internal operation
0: Ready

Write display data

o

Write data

Writes data DBO (lSB)
to DB7 (MSB) on the
data bus into display

Read data

Reads data DBO (LSB)
to DB7 (MSB) from the
display RAM to the data
bus.

RAM.
Read display data

Note: 1.

Busy time varies with the frequency (fCUQ of +1. and

(1IfCLK S TBUSY S 3IfCU<>

+2.

Has access to the
address of the display
RAM specified in
advance. After the
access. Y address is
increased by 1.

HD61202
Detailed Explanation
Display on/orr
RIW

011

OBO

OB7 - - - - - - -.........

I I

Code
-

o
low-order bit -

high-order bit

The display data appem when D is·l and disappears when D is O. Though the data is not on the scnien
with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D= 0 into

D=1.

Display start line
RIW
Code

o

011

OB7

OBO

"

o
-

high-order bit

Iow-order bit -

Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed
the top of the screen. Figure 8 shows examples of display (1/64 duty cycle) when the start line =0-3.
When the display duty cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCD
screen, from the line specified by display start line inslruction, is displayed.

at

HITACHI

603

HD61202

COM1
COM2
COM3
COM4
COMS
COM6
COM7
COM8
COM9

COM1
COM2
COMa
COM4
COMS
COM6
COM7
COMS
COM9

I

I

I

I

I
I

I

I

I

I

I
I

COM60
COM61
COM62
COM63--I.
COM64

COM60
COM61
COM62--I.
COM63
COM64

Start line. 1

Start line - 0

COM1
COM2
COMa
COM4
COMS
COM6
COM7
COM8
COM9

COM1
COM2
COMa
COM4
COMS
COM6
COM7
COM8
COM9

I

I

I
I

I

I

I

I

I
I

I
I

I

I

COM60
COM61--I.
COM62
COM63
COM64---I.

COM60
COM61
COM62
COM63
COM64

Start line - 3

Start line - 2

Figure 8

Relation Between Start Line and Display

HITACHI

HD61202
Set page (X address)

Code

ANI

011

0

0

I

-

DB7

---------------"

DBO

o

A

A

Iow-order bit -

high-order bit

X address AAA (binary) of the display data:{tAM is set in the X address register. After that, writing or
reading to or from MPU is executed in this specified page until the next page is set. See figure 9.

Set Y address

Code

ANI

011

DB7

0

0

o

I

-

--------------"
A

A

DBO

A

A

A

low-order bit -

high-order bit

Yaddress AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Y address
counter is increased by 1 every time the data is written or read to or from MPU.

o1

Yaddress
2 -------------------------- 61 6263

DBO
Page 0

} X-o

Page 1

} X-1

DB7
DBO
DB7
~

..-DBO
DB7
DBO

Page 6

} X-6

Page 7

} X-7

DB7

Figure 9

Address Configuration of Display Data RAM

HITACHI

605

HD61202
Status Read

011

RIW
Code

0

I

I
-

.........

OB7

I Busy I 0

I

g~~ IRESETI

OBO

0

0

I

0

I

0

I

low-order bit -

high-order bit

Busy:

When Busy is I, the LSI is executing internal operations. No instructions are accepted while
Busy is I, so you should make sure that Busy is 0 before writing the next instruction.

ON/OFF:

Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is I, the display is in off condition.
When ON/OFF is 0, the display is in on condition.

RESET:

RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation
condition.

Write Display Data
RIW

011

OB7

-------

..........

OBO

o
-

high-order bit

low-order bit -

Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1
automatically.

Read Display Data
RIW

011

OB7

..........

OBO

11010101010101010

Code
-

high-order bit

Iow-order bit -

Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1
automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of output
register in "FUNCTION OF EACH BLOCK".

606

HITACHI

HD61202
Use of HD61202
Interlace with HD61203 (1/64 duty cycle)

X1

Vee >----1 Vee
V1
V1L,V1R
V6
V6L, V6R
VS
VSL, VSR
V2
V2L, V2R
VEE
VEE
,.....---IGND
VCC

COM1
LCD Panel
64 x 64 dots
~

X64 1 - - - - - - - - ' COM64 .,...

(!)

fa

w
U)

U)

HD61203
SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STe

DL
DR

Open
Open

~
Y1 ~Y64

M t-----o..., M
CL2
CL
FRM
FRM
91
91
92
92

Power supply circuit
----------,
+S V Vee)
I

R1

t------~

R3V1

I

R3 V6

I

Vee

ADC
RST

HD61202

Vee
V1L, V1R
V2L,V2R
V3L, V3R
V4L, V4R
VEEloVEE2
GND

Vee
V1
V2
V3
V4
VEE

R1

HITACHI

607

HD61202

-u--u--tr---------u--

81

~-----~
\

Input

\

----------

\

CL

FRM

M

------------------

~-----~-----_R_fil_
I
I
I
I
I
I
I
II

I

--W1

I

!Tl

r-r-

X64

'l2f I i

r-----

,m

rTLYL
Ii

I
I
I

I
I
I

I
I
I
I
I

~

SEG

I
I
I,
I

I

I

I

~-----+H ! I

!

Selected

I- "I-

~

YL--JJJl

ii~11
I
I
I
I
I

IIII
I
I
I
I
I
I
I
I
I
I
I V1 I
I
II
I V~
Y64 V41
I I
I
I

I!

I
I
I
I

I
I
II
I
V2
I
,!

!

Non.selected

•

I
I
II
I

lLn
I
I

Figure 10

I

LCD Driver Timing Chart (1/64 duty cycle)

HITACHI

I
I V1

I

y~___ I

I I I

! I !

The waveforms of V1 to Y64 outputs vary with the display date. In this
example, the top line of the panel lights up and other dots do not.

608

I

I
I
I
I I I
I
I I I
I
I
I I I
! I II
I
11 frame
I
-+-+-i
I 1 frame
I·
II II -----=+=1I II
I I I
I
I I
I I I
I
I I
I
I
I I
I
I I
I I I
I
I I V1 I
I
I I
V6
t-rU----- - t , 1 _____
III III
Il II
I
I I
I I
V2
I
I
I
I
'"i""'T"1
V2 I
II
I
I
I
I
ii~
I I I
I
I
I
I V1
I I
1V6
IIIv61
I
+H1116
~
V5
V5
I
~
I
----- I I I
I
I I I
I I
I
I I
I
I
I I I
I
I
I V1 I
I V'1
V61
I
I V5
-----~

X2

Y1

I

------+-r1-

-------W1
-----=rT9"

I
I
I
I
I
I
I
I

ffidT

X1

COM

\

HD61202
Interface with CPU
1.

Example 01 connection with HD6800

Decoder
A15

r--r

"-J
A1 UI

.;;-

I

VMA f----

Vcc -

AO

~

CS2
CS3
011
ANI

ANI

H06800

H061202
62

E

DO
I

07

I
I
I

OBO
I

OB7

fVCC

RES

Figure 11

~

'RST

Example 01 Connection with HD6800 Series

In this decoder, addresses of HD61202 in the address area of HD6800 are:
Read/write of the display data
$FFFF

write of display instruction
Read out of status

$FFFE
$FFFE

Therefore, you can control HD61202 by reading/writing the data at these addresses.

HITACHI

609

HD61202
2.

Example or connection with HD6801

P10
P11
P12
P13
(lOS) (SC1)

74LS154
YO
A
~1
B
I
I
I
C
I
Y15
r-!...
0
G1 G2
, ,J,

r.-

(RIW) (SC2)

I

.-

CST
CS2

Vcc- CS3

RIW

P14

011

H061202
No.1

H06801
E

E

P30
P31

OBO
OB1
I
I
I

(Date bus) :
I

P37

I

OB7

Set HD680I to mode S. PIO to P14 are used
as the output port and P30 to P37 as the data
bus.
74LSl54 4-to-16 decoder generates chip select
signal to make specified HD61202 active after
decoding 4 bits of PIO to P13.

610

I
I

HITACHI

Therefore, after enabling the operation by PIO
to PI3 and specifying D/I signal by PI4,
read/write from/to the external memory area
($0100 to $OIFE) to conttol HD61202. In this
case, lOS signal is output from SCI and RIW
signal from SC2.
For details of HD6800 and HD68OI, refer to
their manuals.

HD61202
Example or Application

HD61202
No.9

HD61202
No. 10

HD61202
No. 16

LCD Panel
128 )( 480 dots

Note:

In this example. two HD61203s output the equivalent waveforms. So. stand-alone operation is
possible. In this case. connect COM1 and COM6S to X1. COM2 and COM66 to X2 •...• and COM64
and COM128 to X64. However. for the large screen display. it is better to drive in 2 rows as in this
example to guarantee the display quality.

HITACHI

611

HD61203------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Description

Features

The HD61203 is a common signal driver for dot
matrix liquid crystal graphic display systems. It
generates the timing signals (switch signal to
convert LCD waveform to AC, frame synchronous
signal) and supplies them to the column driver to
control display. It provides 64 driver output lines
and the impedance is low enough to drive a large

Dot matrix liquid crystal graphic display
common driver with low impedance
Low impedance: 1.5 kO max
Internal liquid crystal display driver circuit: 64
circuits
Internal dynamic display timing generator
circuit
Display duty cycle
When used with the column driver HD61202:
1/48, 1/64, 1/96, 1/128
When used with the column driver HD61200:
Selectable out of 1/32 to 1/128
Low power dissipation: During display: 5 mW
Power supplies: Vee: 5 V ± 10%
Power supply voltage for liquid crystal display
drive: 8 V to 17 V
CMOS process

screen.
As the HD61203 is produced by a CMOS process,
it is fit for use in portable battery-driven equipment
utilizing the liquid crystal display's low power
consumption. The user can easily construct a dot
matrix liquid crystal graphic display system by
combining the HD61203 and the column (segment)
driver HD61202.

Ordering Information

612

Type No.

Package

HD61203

100-pin plastic OFP(FP-1 00)

HD61203TFIA

100-pin thin plastic OFP(TFP-60)

HD61203D

Chip

HITACHI

HD61203
Absolute Maximum Ratings
Item

Symbol

Limit

Unit

Note

Power supply voltage (1)

Vee

-0.3 to +7.0

V

2

Power supply voltage (2)

VEE

Vee -19.0 to Vee + 0.3

V

S

Terminal voltage (1)

Vn

- 0.3 to Vee + 0.3

V

2,3

Terminal voltage (2)

VT2

VEE - 0.3 to Vee + 0.3

V

4,S

Operating temperature

Topr

-2Oto+7S

'C

Storage temperature

Tstg

-55to+12S

'C

Notes:

1.

2.
3.
4.
S.

If lSls are used beyond absolute maximum ratings, they may be permanently destroyed. We
strongly recommend you to use the lSI within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
Based on GND • 0 V.
Applies to input terminals (except V1 l, V1 R, V2l, V2R, VSl, VSR, V6l, and V6R) and 110
terminals at high impedance.
Applies to V1 l, V1 R, V2l, V2R, VSl, V5R, V6l, and V6R.
Apply the same value of voltages to V1 land V1 R, V2l and V2R, VSl and VSR, V6l and V6R,
VEE (23 pin) and VEE (S8 pin) respectively.
Maintain Vee~ V1l - V1R ~ V6l - V6R ~ VSl .. VSR ~ V2l- V2R~VEE

HITACHI

613

HD61203
Pin Arrangement

X22
X21
X20
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1

HD61203
(FP-100)

VEE

V6l
V5l
V2l
V1l
Vee

Dl
FS

(Top View)

614

HITACHI

HD61203

X19
X18
X16
X15

X12

HD61203TFIA
(TFP-100)

(Top View)

HITACHI

615

HD61203
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, GND

= 0 V, Vee -

VEE

= 8.0

to 17.0 V, Ta

= -20

to +75"C)

Specifications
Test Item

Symbol Min

Max

Unit

Input high voltage

V..

0.7xVcc

Vee

V

Input low voltage

VIL

GND

0.3 x Vee

V

Vee- 0.4

Typ

Test Conditions Nota

Output high voltage

V~

V

1oH--o·4mA

2

Output low voltage

Va.

0.4

V

1a.-0.4mA

2

Vi-Xj on resistance

Ra.!

1.5

kO

Vee- VEE-17V
Load current
±150 JI.A

13

Input leakage current

Vin-OtoVee

3

IIL1

-1.0

1.0

Input leakage current

11L2

-2.0

2.0

JI.A
JI.A

Yin - VEE to Vee

4

Operating frequency

f Opr1

50

600

kHz

In master mode
external clock
operation

5

Operating frequency

f opr2

0.5

1500

kHz

In slave mode
shift register

6

Oscillation frequency

fosc

315

585

kHz

cr-20pF±5%
Rf.47kn±2'Yo

7, 12

Dissipation current
(1)

IGG1

1.0

rnA

In master mode
1/128 duty cycle
cr.20pF
Rf-47kn

8,9

Dissipation current
(2)

IGG2

200

JI.A

In slave mode
11128 duty cycle

8, 10

DiSSipation current

lEE

100

JI.A

In master mode
1/128 duty cycle

8,11

Notes:

1.
2.
3.
4.
5.

616

450

Applies to input terminals F8, 081, DS2, CR, 8Hl, MIS, and FCS and I/O terminals Dl, M, DR,
and Cl2 in the input state.
Applies to output terminals, 81, 82, and FRM and I/O common terminals Dl, M, DR, and Cl2 in
the output state.
Applies to input terminals F8, 081, 082, CR,
8Hl, MIS, FCS, Cl1, and TH, I/O terminals
Dl, M, DR, and Cl2 in the input state and NC terminals.
Applies to V1 L. V1 R, V2l, V2R, V5l, V5R, V6l, and V6A. Don'l connect any lines to X1 to
X64.
External clock is as follows.

m,

HITACHI

HD61203
TH

Tl

TH

Outy Cycle - TH + Tl x 100%

External clock
waveform

oUc%

e
t rcp
~

trcp

tfcp

External

ck>d<

6.
7.

I "] ""r 'f"i
CR R

t,cp

Min

Typ

Max

Unit

45

50

55

%

50

ns

50

ns

C

Applies to the shift register in the slave mode. For details, refer to AC Characteristics.
Connect oscillation resister (Rf) and oscillation capacitance (Cf) as shown in this figure.
Oscillation frequency (fose> is twice as much as the frequency (f,,) at ,,1 or "2.

Cf.20pF
Rf -47kn
No lines are connected to output terminals and current flowing through the input circuit is
excluded. This value is specified at VIH - Vee and VIL - GNO.
9. This value is specified for current flowing through GNO in the following conditions: Internal
oscillation circuit is used. Each terminal of OS1, OS2, FS, SHL, MIS, 'STB, and FCS is
connected to Vee and each of CL 1 and TH to GNO. Oscillator is set as described in note 7.
10. This value is specified for current flowing through GNO under the following conditions: Each
terminals of OS1, OS2, FS, SHL, 'STB, FCS, and CR is connected to Vee, CL1, TH, and MIS to
GNO and the terminals CL2, M, and OL are respectively connected to terminals CL2, M, and
OL of the H061203 under the condition described in note 9.
11. This value is specified for current flowing through VEE under the condition described in note 9.
Don't connect any lines to terminal V.
12. This figure shows a typical relation among oscillation frequency, Rf and Cf. Oscillation
frequency may vary with the mounting conditions.

8.

600

¥ 400
J 200
-

I
I
I

I

--~--------T---I
I

I

Cf - 20 pF

-------- --------t---I

I
I

--------~-------I
I
I
I

o

I

I

I
I
I

I

I

50

100

Rf (kn)

HITACHI

617

HD61203
13. Resistance between terminal X and terminal V (one of V1 L. V1 R. V2L. V2R. VSL. VSR. VSL,
and VSR) when load current flows through one of the terminals X1 to X64. This value is
specified under the following conditions:
Vee - VEE -17V
V,L - ~R' V6L- V6R - Vee -1n (Vee- VEE)
V2L - V2R. V5L- V5R- VEE +1n (Vee- VEE)

V1L. \ltR

0

VeL.VeR

0

VsL.~R

0

t---o Terminal X

""'O--~.I\r---4

(X1 to X64)

~L.\2R

The following is a description of the range of power supply voltage for liquid crystal display drive. Apply
positive voltage to VIL = VIR and V6L = V6R and negative voltage to V2L = V2R and V5L = VSR
within the AV range. This range allows stable impedance on driver output (RON). Notice that AV depends
on power supply voltage Vee-VEE.
~~

_ _ _ _ _ _ _ Vee
-------- V1 (V1 L - V1 R )

AV

RangeofPowerSupp~

Voltage for Liquid Crystal
Display Drive

---- V6 (VSL - VSR)
...... 3.S

~

~
2 ---------AV

------------ VS ('lsL - VSR )
-------------- ~ (V2L - V2R )
EE

Correlation between Driver
Output Waveform and Power
Supply Voltages for Liquid
Crystal Display Drive

618

8
Vee - VEE (V)
Correlation between Power
Supp~ Voltage Vee - VEe and AV

HITACHI

HD61203
Terminal Configuration
Input Terminal

Applicable Terminals:
CR, MIS, SHL, FCS, OS1, OS2, FS

~t---PMOS
~

---~

NMOS

Applicable Terminals: OL, DR, CL2, M

VOTerminal
Vee

Input circuit)

~

. PMOS
NMOS

,-----~~---1

:

I
:PMOS

I

:

:--Enable

Jt-'
I

,

:

I

I

:NMOS

:

~----------':

Data

: Output circuit
(tristate)

'--________ J

Output Terminal
Applicable Terminals; "1, "2, FRM
PMOS

NMOS

Output Terminal
..I::""

Vee
..I::""

PMOS
PMOS
NMOS
NMOS

V1L, V1R

Applicable Terminals;
X1 toX64

V6L,V6R
VSL, VSR
V2L, V2R

VEE

HITACHI

619

HD61203
AC Characteristics (Vee = 5 V ± 10%, GND = 0 V, Ta = -20 to +7S°C)
In the slave mode (MIS = GND)

CL2
(FCS -GND)
(Shift clock)

CL2
(FCS - Vcc)
(Shift clock)

DL (SHL. Vcc)
DR (SHL = GND)
Input data

DR (SHL - Vcc)
DL (SHL • GND)
Output data

Item

Symbol

Min

Typ

Max

Unit

CL2 low level width (FCS-GND)

tWlCl2l

450

ns

CL2 high level width (FCS-GND)

tWlCl2H

150

ns

CL2low level width (FCS.Vcc)

tWHCl2l

150

CL2 high level width (FCS.VcC>

tWHCl2H

450

Data setup time

tos

100

ns

Data hold time

tOH

100

ns

ns

-

ns

200

Data delay time

too

Output data hold time

tOHW

CL2 rise time

tr

30

ns

CL2falitime

tf

30

ns

Notes:

1.

10

l

;J;

620

ns

The following load circuit is connected for specification:
Output
0
Terminal

30 pF (Includes jig capacitance)

HITACHI

ns

Note

HD61203
2.

CL2

In the master mode (MIS - Va;. FCS - Vee. Cf - 20 pF. Rf. 47 kil)

O.7Vee
0.3 Vcc

tOH

tOH

tos
0. 7Vcc

DL (SHL - Vee)
DR (SHL - GND)

I

0.3 Vcc

too
O· 7Vee

DR (SHL - Vee)
DL (SHL - GND)

tOFRM

tOFRM

FRM

0. 7Vee

M

0.3Vcc

tl

tr

tWIJ1H

,,1

,,2
tl tWIJ2l tr

HITACHI

621

HD61203
Item

Symbol

Data setup time

Min

Typ

Max

Unit

los

20

Jl.s

Data hold time

toH

40

Jl.S

Data delay time

too

5

FRM delay time

toFRM

-2

2

Jl.s

Mdelaytime

tOM

-2

2

JI.S
Jl.s

Jl.S

Cu low level width
Cu high level width

tWCL2L

35

tWCL2H

35

Jl.S

91 low level width

tW81L

700

ns

92 low level width

tW82L

700

ns

91 high level width

tW81H

2100

ns

92 high level width

tW82H

2100

ns
ns

91..;J2 phase difference

t012

700

92..;J1 phase difference

t021

700

91, 92 rise time

tr

150

ns

91, 92 fall time

tf

150

ns

622

HITACHI

ns

-==

~
V2l V6l
V1l V5l
X1

-

CL1

-

TH

-

-

Dl

0

-

::I

64 outDut terminal s

-----

X62 X63 X64

-----

1

Logic

2

~

--

Bidirectional shift
register

62

63

64

logic

~-

DR

1---

.,-

-r

~

SHl
STB

'='
ilr

a

Liquid crystal display
driver circuits

'---

-

:I

~

-

VCC
GND
VEE

X2 ----

V2R V6R
V1R V5R

Oscillator

R~"!IRI

r--

Timing generation circuit

S--

C

Cf

MIS

FS

DS1DS2

1111

FCS

1112

M
CL2
FRM

s
0)
~

N
0-

t:l

o

eN

HD61203
Block Functions
Oscillator
The CR oscillator generates display timing signals and operating clocks for the HD61202.1t is required
when the HD61203 is used with the HD61202. An oscillation resister Rf and an oscillation capacitor Cf
are attached as shown in figure I and terminal
is connected to the high level. When using an external
clock, input the clock into terminal CR and don't connect any lines to tenninals R and C.

m

~~__~____~1~~R~___CrR____rc~1
I

Open

At

Figure 1

Cf

f

I

External Open
clock

Oscillator Connection with HD61202

The oscillator is not required when the HD61203 is used with the HD61830. Then, connect terminal CR to
the high level and don't connect any lines to tenninals R and C (figure 2).

I
Open

Figure 2

CR

,

ciI

Vee

Open

Oscillator Connection with HD61830

Timing Generator Circuit
The timing generator circuit generates display timing and operating clock for the HD61202. This circuit is
required when the HD61203 is used with the HD61202. Connect tenninal MIS to high level (master
mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from
HD61830. In this case connect the tenninals Fs, DSI, and DS2 to high level and MIS to low level (slave
mode).

Bidirectional Shift Register
A 64-bit bidirectional shift register. The data is shifted from DL to DR when Sm. is at high level and from
DR to DL when Sm. is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the
bidirectional shift register, which is on the DL side, corresponds to XI and the highest order bit on the DR
side corresponds to X64.

624

HITACHI

HD61203
Liquid Crystal Display Driver Circuit
The combination of the data from the shift register with the M signal allows one of the four liquid crystal
display driver levels VI, V2, V5 and V6 to be transferred to the output terminals (table 1).

Table 1 Output Levels
Data from the
Shift Register

Output Level

M

V2

va

o
o

o
o

V1
V5

HITACHI

625

HD61203
HD61203 Terminal Functions
Terminal Number of 110 Connected
Name
Terminals
to
Function
Vcc-GND: Power supply for intemallogic.
Vee
1
Power
GNO
1
supply
Vee-VEE: Power supply for driver circuit logic.
VEE
2
V1L, V2l
V5L, V6l
V1R,V2R
V5R,V6R

8

Power
supply

liquid crystal display driver level power supply.
V1 l (V1 R), V2l (V2R): Selected level
V5l (V5R). V6l (V6R): Non-selected level
Voltages of the level power supplies connected to V1 l and
V1 R should be the same. (This applies to the combination
of V2l & V2R. V5l & VSR and V6l & V6R respectively)

MIS

Vee or GND

Selects master/slave.
MIS - Vee: Master mode
When the HD61203 is used with the HD61202. timing
generation circuit operates to supply display timing signals
and operation clock to the HD61202. Each of 110 common
terminals Dl. DR, Cl2. and M is in the output state.
MIS - GND: Slave mode
The timing operation circuit stops operating. The HD61203
is used in this mode when combined with the HD61830.
Even if combined with the HD61202. this mode is used
when display timing signals (M. data, Cl2. etc.) are
supplied by another HD61203 in the master mode.
Terminals M and Cl2 are in the input state.
When SHl is Vee. Dl is in the input state and DR is in the
output state.
When SHl is GND, Dl is in the output state and DR is in
the input state.

FCS

1

Vee or GND

Selects shift clock phase.
FCS - Vee: Shift register operates at the rising edge
of Cl2. Select this condition when
HD61203 is used with HD61202 or when
MA of the HD61830 connects to Cl2 in
combination with the HD61830.
FCS - GND: Shift register operates at the fall of Cl2.
Select this condition when Cl1 of
HD61830 connects to Cl2 in combination
with the HD61830.

FS

Vee orGND

Selects frequency.
When the frame frequency is 70 Hz, the oscillation
frequency should be:
fose - 430 kHz at FCS - Vee
fose • 215 kHz at FCS - GND
This terminal is active only in the master mode. Connect it
to Vee in the slave mode.

626

HITACHI

HD61203
HD61203 Terminal Functions (cont)
Terminal Number of 1/ 0
Name
Terminals
DS1, DS2

2

Connected
to
Function
VeeorGND Selects display duty factor
Display Duty Factor
1/48
DS1
GND
DS2

1/96

1/128

GND

Vee

Vee

Vee

GND

Vee

1/64

GND

These terminals are valid only in the master mode.
Connect them to Vee in the slave mode.

S1B

1

1H

1

CL1

1

Input terminal tor testing.
Connect to STB Vee.
Connect TH and CL1 to GND.

CR,R,C

3

Oscillator.

Vee or GND

In the master mode, use these terminals as shown below:
Internal oscillation
Rf

External clock

Cf

Open

~, I~
R

CR

C

II

I

R

External
Clock Open

I

CR

I
CI

In the slave mode, stop the oscillator as shown below:
Open

Vee

I

I

I
"1, ,,2

2

o

HD61202

R

CR

Open

I

ci

Operating clock output terminals for the HD61202.
Master mode: Connect these terminals to terminals ,,1
and ,,2 of the HD61202 respectively.
Slave mode:

o

HD61202

Don' connect any lines to these
terminals.

Frame signal.
Master mode: Connect this terminal to terminal FRM of
the HD61202.
Slave mode:

1/0

MBof
HD61830
orMof
HD61202

Don' connect any lines to this terminal.

Signal to convert LCD driver signal into AC.
Master mode: Output terminal.
Connect this terminal to terminal M of the
HD61202.
Slave mode: Input terminal.
Connect this terminal to terminal MB of
the HD61830.

HITACHI

627

HD61203
HD61203 Terminal Functions (cont)
Terminal Number of 1/0 Connected
Name
Terminals
to
Function
CL2

110

Cl1 orMAof
HD618300r
CLof
HD61202

Shift clock
Master mode: Output terminal
Connect this terminal to terminal CL of
the HD61202.
Slave mode:

DL,DR

2

110

Open or FLM
of HD61830

Input terminal
Connect this terminal to terminal CL1 or
MA of the HD61830.

Data I/O terminals of bidirectional shift register.
DL corresponds to X1's side and DR to X64's side.
Master mode: Output common scanning signal. Don't
connect any lines to these terminals
normally.
Slave mode:

Vex;

MIS

5

Open

Connect terminal FLM of the HD61830 to
DL (when SHL .. Va;) or DR (when SHL ..
GND)
GND

SHL

Va;

GND

Va;

GND

DL

Output

DR

Output

Output

Input

Output

Output

Output

Input

Not used.
Ocn't connect any lines to this terminal.

SHL

Va; or GND

Selects shift direction of bidirectional shift register.
SHL

X1-X64

64

o

Liquid
crystal
display

Shift Direction

Common Scanning Direction

Va;

X1 --t X64

GND

X1 E-X64

Liquid crystal display driver output.
Output one of the four liquid crystal display driver levels
V1, V2, V5, and V6 with the combination of the data from
the shift register and M signal.

M

.J

r

L.-.....;O;..-.......

Data~

When SHL is Va;, X1 corresponds to COM1 and X64
corresponds to COM64.
When SHL is GND, X64 corresponds to COM1 and X1
corresponds to COM64.

628

HITACHI

H: V
L:
MlSTH CL1FCSFSDS1DS2STBCR R

A

B

:I

~o
:I

-

LLLLHHHHH--

LLLHHHHHH--

C

LLLHHHHHH--

o

HLLHH

E

F

~

C

LL
or

L H

H

Rf Rf
Cf

,1

G~D}

"0" means ·open".

Fixed

.2

0\

Cf: Oscillation capacitor

FRM

M

CL2

from MB from CL1
of
of
HD61830 HD61830

fr~MB fr~fMA
HD61830 HD61830

SHL

H

DL
from FLM
of
HD61830

from FLM
of
HD61830

X1-X64
COM1-COM64

=

"c::I

n

e

~

ID

n

from FLM
of
HD61830

L
H

N

DR

COM64-COM1

to DUDR
of HD61203 COM1-COM64
No.2

~
a

-...
=
=
-i" -[>
I-'

r'

~

-

tD

"c::I
"c::I

8"

to DUDR
from FLM
of HD61203
of
COM64-COM1
No.2
HD61830
from DUDR
COM65-COM128
from MB from MA H of HD61203
of
of
No.1
HD61830 HD61830 ---~--;:-:----=-:-:::-=-----from DUDR
of HD61203 COM128-COM65
L
No.1

to '2
to FRM
to M
to CL
to '1
of
of
of
of
of
Cf HD61202 HD61202 HD61202 HD61202 HD61202

to,1
to,2
to FRM
toM
H L L H H L L
RfRf
of
of
of
of
or H
Cf HD61202 HD61202 HD61202 HD61202
LH
Cf
HD61203

LLLHHHHHH--

:=t::I

Rf: Oscillation resister

to CLof
HD61202
toCL2of
HD61203

L

H

COM1-COM64

L

COM64-COM1

H

toDUDR
of HD61203 COM1-COM64
No.2

L

from M from CL2 H
of
of
HD61203 HD61203
No.1
No.1
L

toDUDR
of HD61203
No.2

COM64-COM1

from DUDR
of HD61203
No.1

COM1-COM64
from DUDR
of HD61203 COM64-COM1
No.1

e
en
~

N

o

W

HD61203
Outline of HD61203 System Configuration
1. Use with 8D61830
a. When display duty ratio of LCD is 1/64

HD61830~
No. 1

HD61830

I

COM1
LCD
CO
L:::
=M:;;:;64;;...._.......

One HD61203 drives
oommon signals.

Refer to
Connection list A.

One HD61203 drives
oommon signals for
upper and lower
panels.

Refer to
Connection list A.

Two HD61203s drive
upper and lower
panels separately
to ensure the
quality of display.
No. 1 and No.2
operate in parallel.

For both of No. 1
and No.2, refer to
Connection list A.

LCD

Upper
Lower
HD61830

----.
LCD

Upper
Lower

b. When display duty ratio of LCD is from 1/65 to 1/128

630

Two HD61203s
oonnected serially
drive oommon signals.

Refer to Connection
list B for No.1.
Refer to Connection
list C for No.2.

Two HD61203s
oonnected serially
drive upper and
lower panels in
parallel.

Refer to Connection
list B for No.1.
Refer to Connection
list C for No.2.

Two sets of
HD61203s oonnected
serially drive upper
and lower panels in
parallel to ensure
the quality of
display.

Refer to Connection
list B for No. 1
and 3.
Refer to Connection
list C for No.2
and 4.

HITACHI

HD61203
2.

Use with HD61202 (1/64 duty ratio)
COM1
COM64

HD61202

LCD

LCD
Upper
lower

LCD
COM1
Upper
COM64
COM1
lower
COM64

One HD61203 drives
common signals and
supplies timing
signals to the
HD61202s.

Refer to
Connection list D.

One HD61203 drives
upper and lower
panels and supplies
timing signals to
the HD61202s.

Refer to
Connection list D.

Two HD61203s drive
upper and lower
panels in parallel
to ensure the
quality of display.
No. 1 supplies
timing signals to
No.2 and the
HD61202s.

HITACHI

Refer to
Connection list E
for No.1.
Refer to
Connection list F
for No.2.

631

HD61203
Connection Example 1
Use with HD61201 (RAM type segment driver)
a. 1/64 duty ratio (See Connection List D)

X1
(X64)

COM1

) )

)

CR

X64
(X1)

COM64

M
CL2
FRM
&1
&2

M
CL
FRM
&1
&2

LCD panel

~

•

..J

:I:

C/)

tii
.!!!

S
C\I
R3V2
VEE
-10V
OV

...

V2L,V2R
VEE

GND

Open
Open

VCC


~ co -------- co X
~
x~
~

,~----------~/
O&8~9aH WOJj

Figure 4

Example 2 Waveform (1164 Duty Ratio)

HITACHI

635

HD61203
b. 1/100 duty ratio (See Connection List B, C)

VCC

o,n toren

Vee 1l:5°

I' Vcc

J
c

.Q

i
8
!

V1
V6

SHL IDS1 IDS2 ITH
CL1 " ~
..9 FS f1\1
• MIS r-I
~ J: FCS ~
aN rn'Iii STB r - - ;D.-.!II X1
C 0 ~ (X64
J:Z __ )

I

V2

VEE
,GND

i3i
;D8

~t
.!!!
C

~

~

~

---

Cf::J'

:::E

..

~

V1L, V1R
V6L.V6R
VSL. VSR
V2L. V2R
VEE 'C
GND !

I

VS

.J!

",Vcc

~

°

CC

-- --

a~

X64
(X1)

-

fro
:::E~Cf::J'

FLM MA MB

-

oBB
-Ill:

X1 -.J
(X64

)

VCC cc
" - V1L. V1R
i . . . - V6L.V6R
X36
(X29
' - - - VSL. VSR
SHL
V2L.V2R
~ DS1
VEE
..9 DS2
GND
-I
TH
~ J:
rn CL1 ,.....
aN 'Iii FS ,..... IOpen- C
... N.f!
Vcc- CR
~o~MIS " Open- R
J:Z--FCS ISTB r- f-

I...--.

) )
~

--

~

~

"\I

Figure 5
636

ee

Example 2 (1/100 Duty Ratio)

HITACHI

LCD
COM64 Panel
COM65

~

rCOM100

-

I •

COM1

HD61203

_

e\! ------1-£ ~ ~
9~
_____

'r'"

_____

>

_

_______

~ ___
>

j

~ ______>
>
_

------ -- ------- ------- ---------

~

------_........- - - ,
-------......_-,
--------.---'

C')

~O

...Je\!

o ..- .... .... ;;;:.q- ;::~ o· xeD
----- eDx
~
x~
__z_________________

~~o_~

0E:8~90H

Figure {)

/~

~

·ON E:O~~90H

.... ;t

x~

----

coS

~~

/
~

·ON E:O~~90H

Example 2 Waveform (1/100 Duty Ratio)

HITACHI

637

HD661 0 8 - - - - - - (RAM-Provided 165-Channel LCD Driver
for Liquid Crystal Dot Matrix Graphics)
Description
The HD6610ST under control of an 8-bit MPU
can drive a dot matrix graphic LCD (liquid-crystal
display) employing bit-mapped display with support
of an 8-bit MPU.
Use of the HD661 08T enables a simple LCD system
to be configured with only a small number of chips,
since it has all the functions required for driving the
display.
The HD6610ST also enables highly-flexible display
selection due to the bit-mapped method, in which one
bit of data in a display RAM turns one dot of an LCD
panel on or off. A single HD66108T can display a
maximum of 100 x 65 dots by using its on-chip 165
x 65-bit RAM. Also, by using several HD66108T's,
a display can be further expanded.
The HD66108T employs the CMOS process and
TAB package. Thus, if used together with an MPU, it
can provide the means for a battery-driven pocketsize graphic display device utilizing the low cwrent
consumption of LCDs.

Features

• Seven types of multiplexing duty ratios can be
selected: 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, 1/66
Notes: The maximum number of row outputs is 65.
• Built-in bit-mapped display RAM: 10 kbits (165 x
65 bits)
• The word length of display data can be selected
according to the character font: 8-bit or 6-bit
• A standby operation is available
• The display can be extended through a multi-chip
operation
• A built-in CR oscillator
• An 80-system CPU interface: ~ =4 MHz
• Power supply voltage for operation: 2.7 V to 6.0 V
• LCD driving voltage: 6.0 V to 15.0 V
• Low cwrent consumption: 400 JIA max (at fose =
500 kHz, fose is external clock frequency)

Ordering Information
Type No.

Package

HD66108TOO

208 pin Tep

Note: The details of TCP pattern are shown in
"The Information of TCP"

• Four types of LCD driving circuit configurations
can be selected:
No. of
Column No. of Row
Configuration Type

Outputs Outputs

Column outputs only

165

0

Row outputs from the
left and right sides

100

65 (from left: 32,
from right: 33)

Row outputs from the
right side 1

100

65

Row outputs from the
right side '2

132

33

638

HITACHI

C"':l

:r

z

-a-

~

;..,

a
.-

-I

;:r
CD

~------

g<
CD

a.
en
c:

.lIS. 24

~.

iii"

en

CD
CD

-a
:::J

3

;:r
CD

:I

~
0

-

:I


GND1-GND3 -----.~

M
CL1
FLM·
MS

RESET

..

..

CO
OSC2
OSC1
TEST1
TEST2

..
CS WRRD RS

HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _..

_--

DB7-DBO

641

HD66108
Register List
~ Reg.

_

CS RS 2

1

ata
B_It _AssI
Register Rea",,__-,-_-,-_D_
--r--,-:9=-n_ment-,-_--,-_----._----I
0 Symbol Name
Invalid

o

0 -

-

-

o

1

0

0 DRAM Display
Memory

0

AR

01001XAR

o

1

0

1

0 VAR

Address -l,l:-J,.-'~7-I

8 clocks max
None

X
address

1.5 clocks max

None

VAD

V

1.5 clocks max

address

o

1

0

1

1 FCR

Mode

o

Cselect

1

0

1 CSR

DUTY

Control

01100MDR
1

time

-

01110-

Invalid

01111-

Invalid

DWS

None
None
None

Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Readin!
these bits returns O.
2. DRAM is not actually a register but can be handled as one.
3. Setting the WLS bit of control register to 1 invalidates 07 and 06 bits ofthe display memor:
register.
4. DRAM must not be written to or read from until a time period Ofiell has elapsed rewritin!
the DUTY bit of FCR or the FFS bit of MDR. ~1 can be obtained from the followin!
equation; in general, a time period of 1.... or greater is sufficient if the frame frequency i
6Q-90Hz.

~1

'"

Ni.fc~~kHZ) (ms) --- Equation 1

02 (duty correction value 2) : 192 (duty = 1132, 1134, or 1136)
128 (duty '" 1/48 or 1/50)
96 (duty = 1/64 or 1/66)

Ni (frequency-division ratio specified by the mode register's FFS bits)
2, 1, 112, 113, 1/4, 1/6, or 1/8
Refer to "6. Clock and Frame Frequency..
fClJ(:
Input clock frequency (kHz)

642

HITACHI

HD66108
System Description
The HD66108T can assign a maximum of 65 out
of 165 channels to row outputs for LCD driving
. It also incorporates a timing generator and display
memory, which are necessary to drive an LCD.
If connected to an MPU and supplied with LCD
driving voltage, one HD66108T chip can be used
to configure an LCD system with a 100 x 65 dot
panel (figure 1). In this case, clock pulses should
be supplied by the internal CR oscillator or the
MPU.

Using LCD expansion signals CLl, FLM, and M
enables the display size to be expanded. In this case,
LCD expansion signal pins output corresponding
signals when pin MIS is set low for master mode
and conversely input corresponding signals when
pin MIS is set high for slave mode; LCD expansion
signal pins of both master chip and slave chips must
be mutually connected. Figure 2 shows a basic
system configuration using two HD66 108T chips.

100 x 65-dot LCD

MPU

HD66108T

LCD driving
power supply

Figure 1 Basic System Configuration (1)

HITACHI

643

HD66108

265 x 65-dot LCD

MPU

Figure 2 Basic System Configuration (2)

HITACHI

HD66108
Functional Description
1. Display Size Programming
A variety of display sizes can be programmed by
changing the system configuration and internal
register settings.
(1) System Configuration Using 1 HD66108T
Chip
When the 65-row-output mode is selected by internal
register settings, a maximum of 100 dots in the X
direction can be displayed (figure 3 (a». Display
size in the Y direction can be selected from 32 ,
34, 36, 48, 50, 64 , and 65 dots according to display
duty setting. Note that Y direction settings does not
affect those in the X direction (100 dots).
When the 33-row-output mode is selected by internal
register settings, a maximum of 132 dots in the X
direction can be displayed (figure 3 (b».

sizes and the control register's (FCR) ROS and
DUTY bits. ROS and DUTY bit settings determine
the function of X pins. For more details, refer to
" 4.1 Row Output Pin Selection."
(2) System Configuration Using 1 HD66108T
Chip and 1 HD61203 Chip as Row Driver
A maximum of 64 dots in the Y direction and 165
dots in the X direction can be displayed. 48 or 64
dots in the Y direction can be selected by HD61203
pin settings (figure 3 (c».
(3) System Configuration Using 2 or more
HD66108T Chips
X direction size can be expanded by 165 dots per
chip. Figure 3 (d) shows a 265 x 65-dot display.
Y direction size can be expanded up to 130 dots
with 2 chips; a 100 x 130-dot display provided by
2 chips is shown in figure 3 (e).

Table 1 shows the relationship between display

Table 1 Relationship between Display Size and Register Settings (No. of Dots)
ROS Bit Setting
(Xo.X164 Pin Function)

165-column-output
65-row-output from the
right side
65-row-output from the
left and right sides
33-row-output from the
right side

Duty BH Setting (Multiplexing Duty Ratio)

1/32
1/34
1/36
Specified by a row driver
X: 100
X: 100
X: 100
Y:32
Y:34
Y:36
X: 100
X: 100
X: 100
Y:32
Y:34
Y:36
X: 132
X: 132
X: 132
Y: 32
Y:33
Y:33

1/48

1750

1/64

1/66

X: 100
Y:48

X: 100
Y:50

X: 100
Y: 64

X: 100
Y:65

X: 100
Y:48

X:100
Y:50

X: 100
Y: 64

X: 100
Y:65

X: 132
Y:33

X: 132
Y:33

X: 132
Y: 33

X: 132
Y:33

HITACHI

645

HD66108
IE--- X:

100 dots ~

IE-~- - - X : 132 dots---'---il~

T

I..J..

L--_ _ _ _ _ _ _ _- l.

Y: 65

~____________~ Jl dots

(b) Configuration Using 1 HD6610ST Chip (2) .
(33-Row Output from the Right Side)

(a) Configuration Using 1 HD6610ST Chip (1)
(65-Row Output from the Right Side)
~Ir----- X: 165 dots ---~~

T

Y: 64

Jl

dots

~------------------------~

(c) Configuration Using 1 HD6610ST Chip and 1 HD61203 as Row Driver
(165-Column Output)
~~- - - - - - - - X : 265 dots -------~~

:
I

Area displayed by
C_h_iP_1________· ________

L--_ _ _ _

Area displayed by

T

Y: 65

~I:___C_h_iP_2~______~ ldots

(d) Configuration Using 2 HD6610ST Chips (1)

Ir---X: 100dots~

Area displayed by
chip 1

I

______________ Y: 130

~l

dOts

Area displayed
by chip 2

(e) Configuration Using 2 HD661 OST Chips (2)

Figure 3 Relationship between System Configurations and Display Sizes
646

J33
dots

HITACHI

HD66108
2. Display Memory Construction and Word
Length Setting

the right side, and is X32 in the 65-row-output mode
from the left and right sides.

The HD66108T has a bit-mapped display memory
of 165 x 65 bits. As shown in figure 4, data from
the MPU is stored in the display memory, with the
MSB (most significant bit) on the left and the LSB
(least significant bit) on the right.

Each display area contains the nurnberof dots shown
in table 1, beginning from each start address.

The sections on the LCD panel corresponding to
the display memory bits in which 1's are written
will be displayed as on (black).

In the display memory, one X address is assigned
to each word of 8 or 6 bits long in X direction.
(Either 8 or 6 bits can be selected as word length
of display data.) Similarly, one Y address is assigned
to each row in Y direction.

Display area size of the internal RAM is determined
by control register (FCR) settings (refer to table 1).
The start address in the Y direction for the display
area is always YO, independent of the register setting.
In contrast, the start address in the X direction is
XO in the modes for 165-column-output, 65 -rowoutput from the right side, and 33-row-output from

For more detail, refer to .. 4.2 Row Output Data
Setting, .. figures 15 to 19.

Accordingly, X address 20 in the case of 8-bit word
and X address 27 in the case of 6-bit word have
5 and 3 bits of display data, respectively.
Nevertheless, data is also stored here with the MSB
on the left (figure 5).

HITACHI

647

HD66108

1
COM1

COM65

fIIII!--fIII't-+-fII~1-65'1-X-+6-5
1

- dot LCD

..... ..
···· .....
.....
.
. . . . ..
•

•••

•

• • • •

I

••
I

•

X164

YO 1101110101110111

D87

D80

(Mssj ...... •· .......... (LS8)

~.: .: :

165 x 65
- bit
display
memory

;

YM~

__________________________

~

Figure 4 Relationship between Memory Construction and Display

($00) ($01) ($02)
012

~ ~r8~1I~:"~II~~==:;I=~::~I=:::::::::::::::::

=1111

Yaddress

($12)
18

!

! 1""1

I I II

(a) Address Assignment When 1 Word is 8 Bits Long

($00) ($01) ($02) ($03)

rT'I'i-0TTl""...:.1--,-..::2'-r....;3~_.•.......•••.•.•.

X address
($18) ($19) ($1 A)($1 B)

~=: H:L:L!:I ~IW,+- !

1M I~!$ 11

:=1 I I I I

I II

-+-1--+-1-+-1:::::::::::::::::

Yaddress

(b) Address Assignment When 1 Word is 6 Bits Long

Figure 5 Display Memory Addresses
648

X address
($13) ($14)
19
20

HITACHI

1

HD66108
3. Display Data Write
3.1 Display Memory and Data Register Accesses
(1) Access
Figure 6 shows the relationship between the
address register (AR) and internal registers
and display memory in the HD661 08T. Display
memory shall be referred to as a data register
since it can be handled as other registers.
To access a data register, the register address
assigned to the desired register must be written
into the address register's Register No.bits.
The MPU will access only that register until
the register address is updated.
(2)

(3)

Busy Check
A busy time period appears after display
memory read/write or X or Y address register
write, since post-access processing is
performed synchronously with internal clock
pulses. Updating data in registers other than
the address register is disabled during this
time. Subsequent data must be input after
confirming ready mode by reading the address
register. The busy time period is a maximum
of 8 clock pulses after display memory read!
write and a maximum of 1.5 clock pulses after
X or Y address register write (figure 7).

(4) Limitations on Access
As shown in figure 9, the display memory must not
be rewritten until a time period of tCLI or longer
has elapsed after rewriting the control register's
DUTY bits or the mode register's FFS bits. However,
display memory and registers other than the control
register and mode register can be accessed even
during this time period. tCLI can be obtained from
the following equation. If using an LSI with a frame
frequency of 60 Hz or greater, a time period of 1
. ms should be sufficient.

=

D2
Ni'fCl,K (kHz)

(ms) '"

D2 ( duty correction
192 ( duty
128 (duty
96 ( duty

value 2 ) :

t

CLI

Equation 1

= 1/32, 1/34, or 1/36)

=1/48 or 1/50 )
= 1/64 or 1/66 )

Ni ( frequency-division ratio specified by the mode
register's FFS bits)
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
fCl,K
: Input clock frequency (kHz)

Dummy Read
When reading out display data, the data which
is read out immediately after setting the X and
Y addresses is invalid. Valid data can be read
out after one dummy read, which is performed
after setting the X and Y addresses desired
(figure 8).

HITACHI

649

HD66108
Registers accessible with pin RS .. 0
Address register
Bit

o

2
Register No.

Registers accessible with pin RS = 1
Data r isters

.. 5

Figure 6 Relationship between Address Register and Register No.
HD66108T

asc
BUSY FLAG

i--_....jl
Ready

:

~:

...

~:

~~ ______ ;;;~~~~~J-- ______ l_-ioI. . .

~*! ___

I-_Ope_r_a_te_s_in_te_m_a_lIy______

CPU

I

WR:I

...

: Ready

Busy 8 clock pluses max

m

_________ •

::

- i i - - - - - - - - + - ·- - - - -

Ui-:

:

U

u

u

u

RS

!I
DB7

n

n~~n~__~n~~_______

Figure 7 Relationship between Clock Pulses and Busy Time ( Updating Display Data )
650

HITACHI

CS

il
~
co

-~

J:

Ifl
1"""

~

o i

3;; ~
~

I-5·

RS
WR

I~----------------------------------

____----'II
ULJ

1

ULJ

r---

II

1

U

RD

DB
(Accessed
register)
output data

Sets a Y address Yn

Display memory
dummy read

- - - - - - - - - - - - - - - - - - - - - - I [ . --I

(Xm,Vn)

(_,.Vn)

110

XandY
addresses

---------«

(Xm.-)

X

(Xm.Vn)

X

(lCm+l.Vn)

X

(Xnwa,Vn)

1

(XnM2.Vn)

X

s
0')
0')

.....,a.

~

o

(Xl

HD66108

Rewriting DUTY or FFS bits
Accessing other registers
Rewriting display memory

Figure 9 Rewriting Display Memory after Rewriting Registers
3.2 X and Y Address Counter Auto-Incrementing

Function
As described in "2. Display Memory Construction
and Word Length Setting, "the HD66108T display
memory has X and Y addresses. Internal X address
counter and Y address counter both employ an autoincrementing function. After display data is read or
written, the X or Y address is incremented according
to the address increment direction selected by internal
register.

652

Although X addresses up to 20 are valid when 8 bits
make up one word ( up to 27 when 6 bits make up one
word ), the X address counter can count up to 31 since
it is a 5-bitfree counter. Similarly,although Yaddresses
up to 64 are valid, the Yaddress counter can count up
to 127. Consequently, X or Y address must be re-set
at an appropriate point as shown in figure 10.

HITACHI

HD66108

.'----------------_.--

X address counted

o
+
1

Set address

I'--

Write display data

+

2

Valid addresses

+
20--1

Re-set X address

+
21

Dummy read/write

Invalid addresses

31~------------------~V
(1) Example of X Address Counter Increment
(Word Length: 8 bits)

Y address counted

~

Set address

+
1

Write display data

+
2

Valid display area

+
31--1

+

32

Re-set Y address
Dummy reacllwrite

I
I
I

I
I

I
I
I

Invalid display area

I
I
I

I

+

1~7

~

~------------------~

(2) Example of Y Address Counter Increment
(Multiplexing duty ratio: 1/32)

Figure 10 XIY Address Counter Increment

HITACHI

653

HD66108
4. Selectionfor LCD Driving Circuit Configuration
4.1 Row Output Pin Selection
The HD 661 08T can assign a maximum of 65 pins for·
row outputs among the 165 pins named XO-XI64.
The XO-XI64 pins can be classified into four blocks
labeled A, B, C, and D (figure 11 (a». Blocks A, C,
and D consist of row/column common pins and block
B consists of column pins only. The output function
of the LCD driving pins and the combination of
blocks can be selected by internal registers.
Figure 11 shows an example of 165-column-output
mode. This configuration is useful when using more
than 1 HD66108T chip or using the HD66108T as a
slave chip of the HD61203.
Figure 12 shows an example of 65-row-output mode
from the right side. Blocks A and B are used for
column output and blocks C andD (Xl00-XI64 pins)
for row output. This configuration offers an easy way

654

of connecting row output lines in the case of using one
or more HD66108T chips.
Figure 13 shows an example of 65-row..output mode
from the left and right sides. 32 pins of XO-X31 and
33 pins ofX132-XI64 are used for row output here.
This configuration offers an easy way of connecting
row output lines in the case of using only one
HD66I08T chip.
Figure 14 shows an example of33-row-output mode
from the rightside. Block D, i.e., XI32-XI64 pins, is
used for row outputs. This configuration provides a
means for assigning many pins to column outputs
when 1/32 or 1/34 multiplexing duty ratio is desired.
In all modes, it is row data and multiplexing duty ratio
that determine which pins are actually used among the
pins assigned to row output. YValues shown in table
1 indicate the numbers of pins that are actually used.
Pins not used must be left disconnected.

HITACHI

HD66108

( ------------ X3i

X32 ------------------. X99

:100------------ X13f

Xl32------------ Xl84

Column driver

Column driver

Column driver

Column driver

Block A

BlockB

BlockC

Block 0

(a) LCD Driving Circuit Configuration

r - - - - - - - - -.
I
II

I
I, ___ I,
I \

I

:
:
I
I
I
I

I

Row
driver

\

:

'-

I

,

I
I

r- - ... ,
II

LCD

,
,

•

~---------

HD66108T

(b) System Configuration

Figure 11 165-Column-Output Mode

HITACHI

655

HD66108

f ------------

X~ ------------------. ~

X3t

Xl~ ------------ Xl64

Xl00 ------------ X131

4

t

Column driver

Column driver

Row driver

Row driver

Block A

BlockB

BlockC

Block D

(a) LCD Driving Circuit Configuration

LCD

HD66108T

(b) System Configuration

Figure 12 65-Row-Output Mode from the Right Side

656

HITACHI

HD66108

XI32-- ---- ------XI64

~2------------------'~
XO

------------~1

t

Xl00 ------------ X131

•

t

t

Row driver

Column driver

Column driver

Row driver

Block A

Block B

BlockC

Block 0

(a) LCD Driving Circuit Configuration

LCD

HD66108T

(b) System Configuration

Figure 13 65.Row.Output Mode from the Left and Right Sides

HITACHI

657

HD66108

t

XO ------------X31

t

~------------------.~

r

X132-- - - - - -- - --- X184

O------------ X13

4

Column driver

Column driver

Column driver

Row driver

Block A

Block B

BlockC

Block D

(a) LCD Driving Circuit Configuration

LCD

HD66108T

(b) System Configuration

Figure 14 33·Row·Output.Mode from the Right Side

658

HITACHI

HD66108
4.1 Row Output Data Setting
If certain LCD driving output pins are assigned to row
output, data must be written to display memory for
row output. The specific area to which this data must
be written depends on the row-output mode and the
procedure of writing row data to the display memory
(0 or 1 to which bits?) depends on which X pin drives
which line of the LCD. Row data area is determined
by the control register's (FCR) ROS and DUTY bits
and is identical to the protected area, which will be
described below. (165-column-output mode has no
protected area, thus requiring no row data to be
written (figure 15).)
Procedure of writing row data to the display memory
is as follows. First, I must be written to the bit at the
intersection between line Yj and line (column) Xi
(column). Line Yj is filled with data to be displayed
on the first line of the LCD and line Xi is connected to
pin Xn, which drives the first line of the LCD.
Following· this, Os must be written to the remaining
bits on line Yj in the row data area. This rule applies
to subsequent lines on the LCD.

and protected areas.
Figure 16 shows the relationship between row data
and display. Here the mode is 65-row output from the
right side. Display data on YO is displayed on the first
line of the LCD and data on Y64 is displayed on the
65th line of the LCD. IfXI64 is connected to the first
line of the LCD and XI 00 is connected to the 65th line
of the LCD, Is must be written to the bits on the
diagonal line between coordinates (XI64, YO) and
(Xl00, Y64) and Os to the remaining bits. Row data
protect function must be turned off before writing row
data and be tumed on after writing row data. Turning
on the row data protect function disables read/write of
display memory area corresponding to the row output
pins, i.e., prevents row data from being destroyed. In
figure 16, display memory area corresponding to pins
XlOO to XI64 is protected.
Figures 17 to 19 show examples of row data settings.
Some multiplexing duty ratios result in invalid display
areas. Although an invalid display area can be read
from or written to, it will not be displayed.

Table 2 shows the relationship between FCR settings

Table 1 Relationship between FeR Settings and Protected Areas
Control Register (FCR)
PON

ROS

LCD Driving Signal Output Pins Connected to

4 3 Mode

Protected Area of Display Memory

Figures

0

165-column

No area protected

15

0

0
1

65-row (R)

X100-X164

16,19

0

65-row.(UR)

XO-X31 and X132-X164

17

1

33-row (R)

X132-X164

18

65-row (R)
: 65-row-output mode from the right side
65-row (UR) : 65-row-output mode from the left and right sides
33-row (R)
: 33-row-output mode from the right side

HITACHI
----~~~-----~-

- - - - - - - - - - - - - ------------

659

HD66108

Control register ROS bit = 00
DUTY bit = 101
LCD driving voltages:

VMH1
VMH2
VMH3

= V3, VML 1 =V4,
= V3, VML2 =V4,
= V3, VML3 =V4

X~ ••

X31~••

•• :<99 Xl00•••

Column driver

,:

Block A (32 bits)

Column driver
:,

---X131 X132
-....

Column driver

Block B (68 bits)

I
I
I

,

Block C (32 bits)

Column driver

,
I
I
I
I
I
I
I

Block D (33 bits)

I
I

,

4 bits + 3 bytes +
4 bits + 3 bytes + II
I
X address:
:
I
I
I
I
I
I
:
4 bytes
:
4 bits
8 bytes + 4 bits
5 bits
8bitsl1wordl 0 11 1 2 1 3 1 4
I 11 I 1;2 I 13 I 14 I 15 I 6 I 17 I 18 I 19 I ~o
I
5 words + 2 bits : 4 bits + 10 words + 4 bits II 2 bits + 5 words II 5 words + 3 bits II
6bitsl1 word 0 I 1 121 31 41 ' 5 I 6 I
I 15 I 161 171 18 I 19 I 20 I 21 22 I 23 I 24 I 25 I 26 1'27 I

1

i

I

165 x 64·dot LCD

--------------------------H-+_+_
--------------------------1-11-+-100.

1

~ :1 1-: :+~: 1 ~~~:t==--------------------------+-:-+-:+-:1-=11-:-1
=== ==== ==== ===== ==== ====t~t~~~~~oo~oo~
I-:Io-:tll

--------------------------ht--;;l-.,.t--,;h-I

1-+-+-+-+-+--------------------------1---'1-+-+-+-1
Display data

Y62

~+-::+-::i-::ir-:-;

Y63 I-::-HI-:I-:t-:-lY64L..-_ _ _ _ _ _ _;;.:..:..='-'='=;:;L..="'-_ _ _ _ _ _---'

Figure 15 Relationship between Row Data and Display
(165-Column Output, 1/64 Multiplexing Duty Ratio)
660

HITACHI

Valid

j" ~~
Invalid
display area

HD66108

Control register ROS bit = 01
DUTY bit - 110
LCD driving voltages:
VMH1 • V3, VML1 = V4,
VMH2 .. V2, VML2 = V5,
VMH3 .. V2, VMl3 = V5

xo•••

•• l<99Xl00•••

•••X31X32. ••

Column driver

i

Block A (32 bits)

o I

8 bitsl1 word
,

6 bitsJ1 word

4~
1 j2 I

5 words + 2 bits

I0 I1 I2 I 3 I

Row driver

Column driver
Block B (68 bits)

,,

X address
3

I:
:

4 1'5

: Block C (32 bits)

I __

n____

I

'

11

4 bits + 10 words + 4 bits

I

8

I

========

••11:164

Row driver
: Block 0 (33 bits)

:

!-Row data protctea blocks
--!:
: 4blts+3bytes+
: 4 bits +3 bytes +

l!9ne.!l_+_i.blts

4

..)(131 XI32

115

4bits

I 1~ I
:

13

I

14

I

:

15

2 bits + 5 words

I 16 I 17 118

119

I I.e I
:

I 20 I 2,1

5blts
17 118

I

:

19

5 words + 3 bits
22

123 I 241

I ~
:

251 261 '271

100 x 65-dot LCD

--------------------+-1-1--1-

f.!4-4-4-~4- - - - - - - - - - - - - - - - - - -- - +'-+-'-1-'+"+''+'''+''-1-''+

1-'-f-"-1f-"'I-'-i-"+ -- - - - - - - - - - - - - - - - - - - +'-+"-+"-+-'-I-"-""""f-"-l-"+
V2 f-!-!-!..if-l-lf-!-l4 - - - - - - - - - - - - - - - - - - - - +'-+'-+'-+-"-I-"-""""f-"-l-"+
Y3 I-'-I-"-If-"'I-'-i-"+ - - - - - - - - - - - - --- - -- -- +'-+"'+"-t-"-I-"-I-"-II-"-I-"+

Y4

I-'-!-"+-"+'+"+ ________ ---- ________ +'-+"-......,1-"-+-><+......."+"+

i""'-II-'-t''+''+''-i Display
memory

Display data

H-;.-+--i-+--------------------+-li-+++-i-+-++
Y82

~..::...r..:..r::..r:+--------------------.j::-~~!:.f-!-j.::.¥-f_!+

Y83 j.::...MMf-!-I-=4------- - ------- -- ---- -F--ro-¥-i-'-I-'-I-"-'H...;..r

Accessible area

Area protected with PON .. 1

Figure 16 Relationship between Row Data and Display
(65~Row Output from the Right Side, 1/66 Multiplexing Duty Ratio)

HITACHI

661

HD66108

Control register ROS bit .. 10
DUTY bit = 110
LCD driving voltages:
VMH1 - V2, VML1 .. V5,
VMH2 .. V3, VML2 ... V4,
VMH3 - V2, VML3 - V5

i

XO...

•••)(31X32...

iti

Row driver

: Block A (32 bits)
X address! Row d a I a ,
:

8 bitsI1 word
.

proteclad blocks

I

Column driver

tt

Column driver

Block B (68 bits)

I

Block C (32 bits)

,

:

:

-;;--r-r4..;;.bytesF.~-;--'I,...-r-!l-~-+-1bltsI

1--"o........I_l.:......TI1.-:2........I...;3::-.1-..;;4........1_________

"' 5 words+ 2 bits

'

•.'..<131 Xl~.

X89 Xl00

Row driver

i

Block D (33 bits)

:

115

:

2 blts + 5 worda

11~ 117 118

:

5 words+ 3 bits

119 120 121 122 123 124 125 1281

:I ________________
100 x 65-d0t LCD :1

,,
- - - - - - - - - - ______ 1

Xl64.
Xl27T Xl28T X131 Xl33
xl~1
1)(311 X331 X35
0111110101 _______________ -' 1 11 11 10 I 0 o I 0 I __
1010 110101110/ _______________ J 1 10 I 0 J 1 10 0101 ___ 0 0
1 ---10l0

XO
1 Xl

YO
Yl

T

ffit
o

'Rowdata '

Y2
Y3
Y4

Y82

to ~ --- 1 0
to ~
0 1
to '0 --- 0 0
to
'0 --- 0 0
f'- ,"'-,
, , ,, ,,

---

m:::

Y83
Y64 a

,~

0

1010
1010

______

I

, , , ,, ,

, , ,, ,, ,

0
0
0
0

0
0
1
0

1
1
0
0

I

I

I

I

0
0
0
1

I

__J/,~

Area protected
with PON=1

::ttjt

Display data
,, ,, , ,
---------------- 1 0 0 0 0 0 0 --- ''0''0
---------------- 1 0 0 0 0 0 0 --- fo '0
---------------- 0 0 0 0 1 0 0 --- ro rr
---------------- 0 0 1 0 0 o 0 --- '1ro
, ,, ,, ,, ---------------- ,, ,, ,, ,, , R~-ci~:, , , ,
, , , ,
o 11 (011 10 ---------------- 010101111 0111 :::fm
1 10 0 0 1 ---------------- 0 0 l~o_Lo Hal.
0 0
____________________________
______

1
1
0
1

_'/,~

Accessible area

J/

Area protected
with PON=1

Figure 17 Relationship between Row Data and Display
(6S-Row Output from the Left and Right Sides, 1/66 Multiplexing Duty Ratio)
662

:

!-Row daIa
--!
:
protecIad blocks :

" 4blts
'I 4blts +3 bytes +5b1ts !'
11 I 12 I 13 I 14 I 15 I 16 I 17 I 18 I 18· I 20

4 bits + 10 words+ 4 blts

6 bitsl1 word ~i0::-11-=1-'1~2-1r-:3:-T1-=4...,..,5~''1-:8:-0-::::::::

4 bits + 3 bytes +

tl

.~J64

HITACHI

:

iU

I

HD66108

Control register ROS bit = 11
DUTY bit", 001
LCD driving voltages:
VMH 1 = V3, VML 1 .. V4,
VMH 2 .. V3, VML 2 = V4,
VMH 3 = V2, VML 3 .. V5

xo.•

... X99 X100...

••.X31 X32..•

... X131 X132...

... X164

Column driver
: Block A (32 bits) :
Block B (68 bits)
: Block C (32 bits) : Block 0 (33 bits) :
X address ------+!---------!!--.-----+!---;R""o:-w-d.".a"'"ta:---~--ll
: 4 bytes
:
8 bytes + 4 bits
' 4 b!ts + 3 bytes +, protected block'
" bits + 3 bytes+ Sbils
,
,
: 4 bits
I-!

8 bitsl1 word

I: 50words
1 1 1 2 1 3 I 4 1 ======== 1 11 11~ 1 13 1 14 1 15 1 1:6 117 118 119 1~. 1
+ 2 bits : 4 bits + 10 words + 4 bits: 2 bits + 5 words : 5 words + 3 bits :

6bits/1wordl

0111213141'5161 ________ 11511~11711811912012112212312412512612-,1

132 x 33-dot LCD

----------------------------1--i-r--i-

Figure 18 Relationship between Row Data and Display
(33-Row Output from the Right Side, 1/34 Multiplexing Duty Ratio)
663

HITACHI

HD66108

Control register ROS bit =01
DUTY bit =011
LCD driving voltages:
VMH 1 =V3, VML 1 =V4,
VMH 2 = V2, VML 2 = V5,
VMH 3 =V2, VML 3 =V5
... X31 X32...

XO•••

Column driver

8 bits/l word

:
:
,

4 bytes

... X99 Xl00...

Block B (68 bits)

!

8 bytes+ 4 bits

I

1---:-0-'1r-1-'1r"-:-2""1-3-11-4'1-========

o

I 1I2 I3 I

... XI64

41' 51 6

I

========

Block C (32 bits)

!

Block D (33 bits) :,

:.-- Row data prqtected blocks ----+l
: 4 biis+ 3 bytes+ : 4 bits + 3 bytes + :
'4bits
'5 bits
'
11

I 1:2 I

5 words + 2 bits : 4 bits + 10 words + 4 bits:

6 bits/l word

...XI31 XI32...

Column driver

Block A (32 bits) :I

X address

48-row
driver used

13

I 14 I

15

I

161 17

2 bits + 5 words:

1151 161 171 18119120

I 211

I

18

I 19 I ~ I

5 words + 3 bits :
221 23124125/261271

,

,

: 100 x 48-dot LCD :

-------------------+-1--1-+--'

I ~1 I X3 I
0

Yl

1 0 0 1 0

Y45
Y46
Y47
Y48
Y49

Y63

Y64

I x971

X99 I

Xl161 X1181

Xl62 X164
x1631

I

T

--- 0 0 0 0 ----- o~!...
--- 0 0 0 0 ------ Or!-.£.
1 1 1 1 0
,, ,, ,, ,, ,,
,, ,, ,, ,, ,, , --- , Row data , 1~.2..
,,
Display data
Valid
, , ,,,
, , , , , ,, ,, 'Valid row data , display area
-I--- 0 0 0 1 ----- -E.~ --E.
0 0 1 0 0 ------------------- 0 0 0 0 1 0
------0 1 0 1 0 ------------------- 0 0 0 1 1 0
...Q.
------------------- 0 0 1 0 0 0 --- 00 01 01 00 ------ ...Q.~
1 0 0 0 1
0 0 0
---_ .. ----_ .. _- ---------- -I- --,, ,, ,, ,, ,, ---------- .. -- .. ----- ,, ,, ,, ,, ,, ,, ,, --- ,, ,, ,, ,, ,,------,,- I,,- ,,- Invalid
, , ,,,
, , , , , ,, , , ,,
display area
--~~::::::::::::::::: I I I I I I --- I I '----~ffi
-----

YO

Y2

X95

1 1 0 0

-------------------------------------

1 1 1 0 0 0

0 0 0 0

1 0 0 1 0 0
1 1 1 0 0 0

+

,~

1111111
____________________________
_JI'
Accessible area

I

I

Area protected with PON

I

~

=1

Note: Pins Xl OO-Xl16 are left disconnected here.

664

Figure 19 Relationship between Row Data and Display
(65·Row Output from the Right Side, 1/48 Multiplexing Duty Ratio)

HITACHI

HD66108
4.3 LCD Driving Voltage Setting
There are 6 levels of LCD driving voltages ranging
from VI to V6; VI is the highest and V6 is the lowest.
As shown in figure 20, column output wavefonn is
made up of a combination of VI, V3, V4, and V6
while row outputwavefonn is made up of VI, V2, V5,
and V6. This means that VI and V6 are common to
both wavefonns while mid-voltages are different.
To accommodate this situation, each block of the
HD66108T is provided with power supply pins for

mid-voltages as shown in figure 21. Each pair of VIR
and VIL and V6R and V6L are internally connected
and must be applied the same level of voltage. Block
B is fixed for column output and must be applied V3
and V4 as mid-voltages. The other blocks must be
applied different levels of voltages according to the
function of their LCD driving output pins; if the LCD
driving output pins are set for row output, VMHn and
VMLn must be applied V2 and V5, respectively,
while they must be applied V3 and V4, respectively,
if the pins are set for column output (n = I to 3).

Table 3 Relationship between FCR settings and LCD Driving Voltages
Control Register (FCR)

LCD Driving Voltage Pins

ROS4 ROS3 Mode

VIRNIL

V3 V4

VMH1 VML1 VMH2

VML2 VMH3 VML3 V6RN6L

0

0

165-column

V1

V3 V4

V3

V4

V3

V4

V3

V4

0

1

65-row (R)

V1

V3 V4

V3

V4

V2

V5

V2

V5

V6

0

65-row (UR)

V1

V3 V4

V2

V5

V3

V4

V2

V5

V6

33-row (R)
V1
V3 V4 V3
V4
V3
65-row (R)
: 65-row-output mode from the right side
65-row (UR) : 65-row-output mode from the left and right sides
33-row (R)
: 33-row-output mode from the right side

V4

V2

V5

V6

HITACHI

V6

665

HD66108

,

,

,2,3,4:

234

------------- :.- ..:.. ....:. - - - - ~

~-~~-~~4----

V2 - -'OO~

•..••..•..•.

-f--+-+----~

V3
:
W-~
V5
V6

_____

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- :- -r- i ,- -

I

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,

-

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I

,-~T~----

,

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_ _ _ _

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:

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+4---~4---~~====....:.~=:._~....:.:.:=~=_

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I

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••••••••••••

r ====IIT
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t "1 :':=:::.:~'

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--:-i-:--:-i----

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I

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...............

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___ _

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SEG2

+~--------­
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:
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w-~~-:.-..:..4----~~-~+4---------

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I

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from

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l:::: ± =± = = = = - - = = = 719VLCD

............

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,

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I

±=±====::±
:=l::::±::±=====-........,r-=VLCD
-1--..L _ _ _ _
...J----L _ _ _ _

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____ _

--L.-t_L..-...L--L _ _ _ _ _

--'-

...I....--I. _ _ _ _ -.1..--'_L.-...&.--..I. _ _ _ _ _
-&.-......l. _ _ _ _ .....L.-'_L...-...L---I. _ _ _ _ _
....L... -oJ. _ _ _ _
......L. _ , _ L.- - ' - ---L _ _ _ _ _
--L _ _ _ _ --1. _ , _ 1....-...L- --L _ _ _ _ _

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--1.

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±::±=========

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-

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L-

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--

±::±=~=======

>;:

Figure 20 LCD Driving Voltage Waveforms
666

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:= =F =:: = = = = -r : = l:::: ± =± = = = = = = = = =-7/9VLCD
-=l=~-:==F=::----=l=~-~+~---------~~
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=

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~e

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=::±
_-.1..
_
--'-

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HITACHI

HD66108
LCD driving output pins

1L

6L

xo ----- X31

X32- - - - - X99

X100- - - - - X131

X132- - - - - X164

Block A

BlockB

Block C

Block D

MH1

ML1

MH2

ML2

MH3

ML3

6R

1R

LCD driving power supply pins

Figure 21 Relationship between Blocks and LCD Driving Voltages

S_ Multiplexing Duty Ratio and LCD Driving
Waveform Settings
A mUltiplexing duty ratio and LCD driving waveform
can be selected via internal registers.

A multiplexing duty ratio of 1/32, 1/34, 1/36, 1/48, 1/
50, 1/64, or 1/66 can be selected according to the LCD
panel used. However, since there are only 65 rowoutput pins, only 65 lines will be displayed even if 1/
66 multiplexing duty ratio is selected.
There are three types of LCD driving waveforms, as
shown in figure 22: A-type waveform, B-type
waveform, and C-type waveform.
TheA-type waveform is called per-half-line inversion.
Here, the waveforms ofM signal and CLI signal are
the same and alternate every LCD line.
The B-type waveform is called per-frame inversion;
in this caSe, the M signal inverts its polarity every

frame so as to alternate every two LCD frames. This
is the most cornmon type.
The C-type waveform is called peron-line inversion
and inverts its polarity every n lines (n can be set as
needed within 1 to 31 via the internal registers). The
C-type waveform combines the advantages of the Aand B-types of waveforms. However, some lines will
not be alternated depending on the multiplexing duty
ratio and n. To avoid this, another C-type waveform
is available which is generated from theEOR ofthC Ctype waveform M signal mentioned above and the Btype waveform M signal. Since the relationship
between n and display quality usually depends on the
LCD panel, n must be determined by observing actual
display results.
The B-type waveform should be used if the LCD
panel specifies no particular type of waveform.
However, in some caSes, the C-type waveform may
create a better display.

HITACHI

667

HD66108

Q)

E

e:!

...-

II)

---:!:
---~
N

Tc------,
I I I

I I I

I I I

c:

:E

E
SQ)..-..
Q)Et:

in tU.2
::. .... 00

E
....
0

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t:

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HITACHI

t:

0

t:

0

in~ =7.2
13
t: ~ t:
Q)~Q)

o.Q»

~e:..=
I

()

Figure 22 LCD Driving Waveforms
(Row Output with a 1/32 Multiplexing Duty Ratio)
668

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a:

II

w_

0t:

HD66108
6.

Clock and Frame Frequency

7.

Display OtT function

An input clock with a 200-kHz to 4-MHz frequency
can be used for the HD66108T. Note that raising clock
frequency increases current consumption although it
reduces busy time and enables high-speed operations.
An optimum system clock frequency should thus be
selected within 200 kHz to 4 MHz.

The HD6610SThas a display offfunction which turns
off display by rewriting the contents of the internal
register. This prevents random display at power-on
until display memory is initialized.

The clock frequency driving the LCD panel (= frame
frequency) is usually 70 Hz to 90 Hz. Accordingly,
the HD6610ST is so designed that the frequencydivision ratio of the input clock can be selected. The
HD6610ST generates around SO-Hz LCD frame
frequency if the frequency-division ratio is 1. The
frequency-division ratio can be obtained from the
following equation.

The HD6610ST has a standby function provinding
low.:power dissipation. Writing a 1 to bit 6 of the
address register starts up the standby function.

~ x

500 x D1
fCLK
SO
Ni : Frequency-division ratio
fF
: Frame frequency required for the LCD
panel (Hz)
fCLK : Input clock frequency (kHz)
D1 : Duty correction value 1
D1 = 1 when multiplexing duty ratio is 1/32,
1/4S or 1/64
D1 = 32/34 when multiplexing duty ratio is
1/34
D1 = 32/36 when multiplexing duty ratio is
1/36
D 1 4S/50 when multiplexing duty ratio is
1/50
D1 = 64/66 when multiplexing duty ratio is
1/66
Ni =

=

The frequency-division ratio nearest the value obtained
from the above equation must be selected; selectable
frequency-division ratios by internal registers are 2,
1, 1/2, 1/3, 1/4, 1/6, and l/S.

8. Standby Function

The LCD driving voltages, ranking from VI to V6,
must be set to Vee to prevent DC voltage from beging
applied to an LCD panel during standby state.
The HD661 OST operates as follows in standby mode.
(1)
(2)

Stops oscillation and external clock input
Resets all registers to O's except the STBY bit

Here, note that the display memory will not preserve
data if the standby function is turned on; the display
memory as well as registers must be set again after the
standby function is terminated.
Table 4 shows the standby status of pins and table 5
shows the status of registers after standby function
termination.
Writing a 0 to bit 6 of the address register terminates
the standby function. Writing values into the DISP
and Register No. bits at this time is ignored; these bits
need to be set after the standby function has been
completely terminated.
Figure 23 shows the flow for start-up and termination
of the standby function and related operations.

Table 4 Standby Status of Pins
Pin

Status

OSC2

High

co

Low

CL1

Low (master chip) or high-impedance (slave chip)

FLM

Low (master chip) or high-impedance (slave chip)

M

Low (master chip) or high-impedance (slave chip)

Xn (column output pins)

V4

Xn' (row output pins)

V5

HITACHI

669

HD66108
Table 5 Register Status after Standby Function Termination
Register Name

Status after Standby Function Termination

Address register

Reset to O's except for the STBY bit

X address register

Reset to O's

Y address register

Reset to O's

Control register

Reset to O's

Mode register

Reset to O's

C select register

Reset to O's

Display memory

Data not preserved

Set the LCD driving voltages to Vee level

Start-up

j
j

'"

Set the STBY bit to 1
(turn on the standby function)

'"

'"

Termination

Set the STBY bit to 0
(turn off the standby function)

'"

)

'"

)

(

Supply the LCD driving voltages

(

Set registers again

(

Wait for a time period of tCL1 or longer

(

Set the display memory again

(

Set the DISP bit to 1 (turn on LCD)

'"
+

'"

Notes: 1. Not necessary in the case of using internal oscillation
2. Refer to equation 1 (section 3.1).

Figure 23 Start.Up and Termination of Standby Function and Related Operations
670

*1

Wait until external clock pulses stabilize

HITACHI

) *2
)
)

HD66108
9.

Multi-Chip Operation

(5)

Using multiple HD66I08T chips (= multi-chip
operation) provides the means for extending the
number of disply dots. Note the following items when
using the multi-chip operation.
(I)

(2)

(3)

(4)

The master chip and the slave chips must be
detennined; the MIS pin of the master chip must
be set low and the MIS pin of the slave chips
must be set high.
All the HD66I08T chips will be slave chips if
HD61203 or its equivalent is used as a row
driver.
The master chip supplies the FLM, CL I, and M
signals to the slave chips via the corresponding
pins, which synchronizes the slave chips with
the master chip.
Since a master chip outputs synchronization
signals, all data registers must be set.

(6)
(7)

The following bits for slave chips must always
be set:
INC, WLS, PON, and ROS (control register)
FFS (mode register)
It is not necessary to set the control register's
DUTY bits, the mode register's DWS bits, or
the C select register. Forotherregisters' settings,
refer to table 6.
All chips must be setto LCD off in order to tum
off the display.
The standby function of slave chips must be
started up first while that of the master chip
must be tenninated first.

Figure 24 to 26 show the connections of the
synchronization signals for different system
configurations and table 6 lists the differences between
master mode and slave mode.

Row
output

LCD

r--

Column
output

Column
output

HD66108T
Slave mode

HD66108T
Master mode
M

-

M

p5c1 FLM Cll

OSCI FLM Cll

t t

I

I

Clock
Note:

Clock pulses for the slave chip can be supplied from the master chip CO pin.
Figure 24 Configuration Using 2 HD6610ST Chips (I)

HITACHI

671

HD66108
Row
output
LCD

f---

Column
output

Column
output
lf--

HD66108T
Master mode

HD66108T
Slave mode
M

IoSCl FlM CL1

M
OSCI FLM CLI

J

J
I

r

Clock

Note: Clock pulses for the slave chip can be supplied from the master chip CO pin.
Figure 25 Configuration Using 2 HD66108T Chips (2)

672

HITACHI

HD66108
Table (;. Comparison between Master and Slave Mode
~rMode

Hem
Pin:

Slave Mode

MIS

Must be set low

Must be set high

OSC1,OSC2

Oscillation is possible

Oscillation is possible

CO

.OSC1

.. OCS1

FLM, CL1, M

Output signals

Input signals

Valid

Valid

Register:

AR
XAR
YAR

Valid

Valid

Valid

Valid

FCR

Valid

Valid except for the DUTY bits

MDR

Valid

Valid except for the DWS bits

CSR

Valid (only if the DWS bits are
set for the C-tye waveform)

Invalid

Notes
- Valid
: Needs to be set
- Invald: Need not be set

674

HITACHI

HD66108

LCD

Row output

Column output

HD61203
Row driver

HD66108T
Slave mode
M

M

OSCI FLM

CR FRM CL2

I

f

I

ell

1

Clock

Note: 1. The slave chip can oscillate CR clock pulses. In this case, the clock pulses must be
supplied to the HD61203 from the HD6610ST's CO pin.
2. The HD61203's control pins must be set in accordance with the type of RAMs.
Figure 26 Configuration Using 1 HD6610ST Chip with Another Row Driver (HD61203)

HrtAcH'

673

HD66108
Internal Registers
All HD66108T's registers can be read frQm and
written into. However,the BUSY FLAG imd invalid
bits cannot be written to and reading invalid bits or
registers returns O's.

1. Address Register (AR) (Accessed with RS =0)

BUSY FLAG bit, STBY bit, and DISP bit. Register
No. bits select one of the data registers according to
the register number written. The BUSY FLAG bit
indicates the internal operation state if read. The
STBY bit activates the standby function. The DISP
bit turns the display on or off. This register is selected
when RS pin is O.

This register (figure 27) contains Register No. bits,
Bits D4 and D3 are invalid.

07

06

05

BUSY
FLAG

STBY

DISP

(1)

D4

D3

02

01
Register No.

DO

I

STBY
- 1: Standby function on
- 0: Normal (standby function off)
• When standby function is on. all registers are reset to O's

(2) OISP
-1: LCDon
-0: LCD off
(3) Register No.
Bit

No.

2 1 0

0

0
0
0
0
1
1

1

2
3
4

5
(4)

0 0
0 1
1 0
1 1

0 0
0 1

Register
Display memory
X address register
Y address reQister
Control register
Mode register
C select register

BUSY FLAG (Can be read only)
- 1: Busy state
- 0: Ready state

Figure 27 Address Register

HITACHI

675

HD66108
2. Display Memory (DRAM) (Accessed with RS
= 1, register number = (OOO)J

This register (figure 29) contains 3 invalid bits (07 to
05)and 5 valid bits (D4 to DO). It sets X addresses and
confirms X addresses after writing or reading to or
from the display memory.

Although display memory (figure 28) is not a register,
it can be handled as one. 8- or 6-bit data can be
selected by the control register WLS bit according to
the character font in use. If 6-bit data is selected, 07
and D6 bits are invalid.

4. Y Address Register (yAR) (Accessed with RS
1, register number (OI0)J

=

This register (figure 30) contains 1 invalid bit (07) and
7 valid bits (06 to DO). It sets Y addresses and
comnms Y addresses after writing or reading to or
from the display memory.

3. X Address Register (XAR) (Accessed with RS
1, register number (OOI)J

=

=

07

D6

05

D4

03

02

01

DO

8-Bit Data

*

6-BitOata

*

Reading bits marked with • return Os and writing them is invalid.

Figure 28 Display Memory
07

06

05

D4

03

02

01

DO

XAO

XAO: 0 to 20 ($00 to $14) when display data is 8 bits long and 0 to 27 ($00 to $1 B) when display data
is 6 bits long. A maximum of $1 F is programmable.

Figure 29 X Address Register
07

06

05

04

I I

03

02

01

DO

VAD

YAO: 0 to 128 ($00 to $7F)

Figure 30 Y Address Register

676

=

HITACHI

HD66108
5. Control Register (FCR) (Accessed with RS =
1, register number =(011»))
This register (figure 31), containing eight bits, has a
variety of functions such as specifying the method for
accessing RAM, determining RAM valid area, and
selecting the function of the LCD driving signal
output pins. It must be initialized as soon as possible

07

06

05

04

03

02

01

(1)

INC (Address increment direction select)
- 1: X address is incremented
- 0: Y address is incremented

(2)

WLS (Word length (of display data) select)
- 1: 6-bit word
- 0: 8-bit word

(3)

PON (Row data protect on)
- 1: Protect function on
- 0: Pretect function off

afterpower-on since it determines the overall operation
oftheHD66108T. The PON bit may have to be re-set
afterwards. If the DUTY bits are rewritten after
initialization at power-on (if values other than the
initial values are desired), the display memory will
not preserve data; the display memory must be set
again after a time period of to-lor longer. For
determining to-\' refer to equation 1 (section 3.1).

00

(4) ROS (Row output (function of LCO driving output pins) select)

Bit
No.

43

Contents

o

00
01
10

65 row outputs from the right side
65 row outputs from the left and right sides

11

33 row outputs from the right side

1

2
3
(5)

165 column outputs

OUTY (Multiplexing duty ratiO)
Bit

Multiplexing

No.

2 1 0 DU!l Ratio

0
1
2
3

0
0
0
0
1
1

4
5
6
7

0
0
1
1
0
0
1 1

0
1
0
1
0

1
0

1/32
1/34
1/36
1/48
1/50
1/64
1/66

1 1 1 Testing mode

Figure 31 Control Register

HITACHI

677

HD66108

=

6. Mode Register (MDR) (Accessed with RS 1,
register number (lOO)Z>

=

the FFS bits are rewritten after initialization at poweron (if values other than the initial values are desired),
the display memory will not preserve data; the display
memory must be set again after a time period of ta.l or
longer. For determining ta.I' refer to equation 1
(section 3.1).

This register (figure 32), containing 3 invalid bits (07
to D5) and 5 valid bits (04 to DO), selects a system
clock and type of LCD driving waveform. It must
also be initialized after power-on since it determines
overall HD66108Toperation like the FeR register. If

07

06

D4

05

01-

00

OWS

FFS (Frame frequency select)
Bit

Frequency2 Division Ratio

No.

4 3

0

0
0
0
0

0 0 1
0 1 112
1 0 1/3

1
1
1
1

0 0 1/6
0 1 1/8
1 0 2
1 1

1

2
3
4
5
6
7
(2)

02

FFS

I
(1 )

03

1 1 1/4

OWS (LCO driving waveform select)
Bit
No.

1 0

Driving Waveform

0

0 0
0 1
1 0
1 1

A-type waveform
B-type waveform
C-type waveform

1

2
3

Figure 32 Mode Register

678

HITACHI

HD66108
7. C Select Register (CSR) (Accessed with RS
1, register numbef (lOl)J

=

=

This register (figure 33) contains 2 invalid bits (D7

07

06

05

D4

03

02

01

andD6) and 5 valid bits (05 to DO). It controls C-type
wavefonns and is activated only whenMDR register's
DWS bits are set for this type of wavefonn.

DO

(1)

EaR (B-type waveform M signal ® no. of counting lines on/off)
- 1: EaR function on
- 0: EaR function off

(2)

CLN (No. of counting lines in C-type waveform)
1 to 31 should be set in these bits; 0 must not be set.

Figure 33 C Select Register

HITACHI

679

HD66108
Reset Function
The RESET pin starts the HD66108T after poweron. A RESET signal must be input via this pin for
at least 20 Ils to prevent system failure due to
excessive current created after power-on. Figure 34
shows the reset definition.

or register bits except for the address register's
STBY bit and the X and Y address registers,
which are reset to O's by the signal. Table 8
shows the reset status of registers.
(3)

(1)

Reset Status of Pins
Table 7 shows the reset status of output pins.
The pins retum to normal operation after reset.

(2)

Reset Status of Registers
The RESET signal has no effect on registers

Status after Reset
The display memory does not preserve data
which has been written to it before reset; it
must be set again after reset.
A RESET signal terminates the standby mode.

Table 7 Reset Status of Pins

Pin

Status

OSC2

Outputs clock pulses or oscillates

CO

Outputs clock pulses

CL1

Low (master chip) or high-impedance (slave chip)

FLM

Low (master Chip) or high-impedance (slave Chip)

M

Low (master chip) or high-impedance (slave chip)

Xn(column output pins)

V4

Xn' (Row output pins)

V5

Table 8 Reset Status of Registers
Register

Status

Address register

Pre-reset status with the STBY bit reset to 0

X address register

Reset to O's

Y address register

Reset to O's

Control register

Pre-reset status

Mode register

Pre-reset status

C select register

Pre-reset status

Display memory

Preserves no pre-reset data

RESET

hOfi)'

0.15 x Vcc_
During reset
(Reset status)

./

0.15 x Vcc
After reset

Figure 34 Reset Definition
680

HITACHI

HD66108
Precautionary Notes When Using the HD66108T
(1)

(2)

(3)

(4)
(5)

Install a 0: 1-IlF bypass capacitor as close to
the LSI as possible to reduce power supply
impedance (Vee-GND and Vee-VEE)'
Do not leave input pins open since the
HD66108T is a CMOS LSI; refer to "Pin
Functions" on how to deal with each pin.
When using the internal oscillation clock,
attach an oscillation resistor as close to the
LSI as possible to reduce coupling capacitance.
Make sure to input the reset signal at poweron so that internal units operate as specified.
Maintain the LCD driving power at Vccduring
standby state so that DC is not applied to an
LCD, in which Xn pins are fixed at V4 or V5
level.

(2)

(3)
Programming Restrictions
(I)

address is not incremented until 0.5-clock
time has passed. If an X or Y address is read
during this time period, non-updated data will
be read. (The addresses are incremented even
in this case.) In addition, the address increment
direction should not be changed during this
time since it will cause malfunctions.
Although the maximum output rows is 33
when 33-row-output mode from the right side
is specified, any multiplexing duty ratio can
be specified. Therefore, row output data
sufficient to fill the specified duty must be
input in the Y direction. Figure 35 shows how
to set row data in the case of 1/34 multiplexing
duty ratio. In this case, Os must be set in Y33
since data for the 34th row (Y33) are not
output.
Do not set the C select register's CLN bits
to 0 for the M signal of C-type waveform.

After busy time is terminated, an X or Y

X132
X131 X133

o
oo
o

YO
Y1
Y2
Y3

0 __________

r!LrJ.

----------J-J
0 0

0
0
0

----------roro

-I--l-=+--=+ - - - - - - - - - 1
1
1

Y30
Y31
Y32
Y33

X164
X163

1
1
1

1--"'::"

1
1
1

1
1
1

--(\') >'V W::::E...-o LL. 0....1 0 0 0 (\') (\1"'- 0(\1
>
W
Z LL.O:I:ZZZ 0 0 0 0 d

>

c3 (!)

~

>

CI)

CI)

is
(Top View)

692

Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17

HITACHI

10:
~
'-'

HD66204

Y27
Y26
Y25
Y24
Y23

Y53

Y54
Y55
Y56
Y57

Y22

Y58

Y59
Y60
Y61
Y62
Y63

Y64
Y65
Y66
Y67
Y6B
Y69

HD66204TF
HD66204TFL
(TFP-100)

Y70

Y71
Y72
Y73
Y74
Y75
Y76

Y21
Y20
Y19
Y1B
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
YB
Y7

Y6
Y5
Y4
Y3

Y77

(Top View)

HITACHI

693

HD66204
Pin Description
Symbol

vee
GND

VEE
V1
V3
V4
CL1
CL2
M

0 0-03
SHL
E
CAR
DISPOFF

Y1-Y80
NC

694

Pin No. (FP-10orrFP·100)
40/38

38/36
35/33
32130
33/31
34132

Pin Name

Input/OUtput

Classification

Vee

Power supply

GND

Power supply

VEE
V1
V3
V4

Power supply
Input

Power supply

Input

Power supply

Input

Power supply

37/35
49/44
36/34
48-45/43-40
41/39
31129
50/48
39/37

Clock 1

Input

Control signal

Clock 2

Input

Control signal

M

Input

Control signal

Data o-data 3

Input

Control signal

51-100, 1-30/49-100, 1-28
42,43,44145,46,47

Shift left

Input

Control signal

Enable

Input

Control signal

Carry

Output

Control signal

Display off

Input

Control signal

Y1-Y80

Output

LCD drive output

No connection

HITACHI

HD66204
Pin Functions
Power Supply
Vee, VEE, GND: Vcc-GND supplies power to
the internal logic circuits. Vee-VEE supplies
power to the LCD drive circuits.
VI, V3, V4: Supply different levels of power to
drive the LCD. VI and VEE are selected levels,
and V3 and V4 are non-selected levels. See figure
1.

Do-D3: Input display data. High-voltage level of
data corresponds to a selected level and turns an
LCD pixel on, and low-voltage level data
corresponds to a non-selected level and turns an
LCD pixel off.
SHL: Shifts the destinations of display data
output See figure 2.

E: A low E enables the chip, and a high E disables
the chip.
CAR: Outputs theE signal to the next HD66204 if
HD66204s are connected in cascade.

Control Signal
CLl: Inputs display data latch pulses for the line
data latch circuit. The line data latch circuit
latches display data input from the 4-bit latch
circuit, and outputs LCD drive signals
corresponding to the latched data, both at the
falling edge of each CLl pulse.
CLl: Inputs display data latch pulses for the 4-bit
latch circuit. The 4-bit latch circuit latches display
data input via Do-D3 at the falling edge of each
CL2pulse.

DISPOFF: A low DISP sets LCD drive outputs
Y,-YgO to VI level.
LCD Drive Output
Y1-Ygo: Each Y outputs one of the four voltage
levels VI, V3, V4, or VEE, depending on a
combination of the M signal and display data
levels. See figure 3.

NC: Must be open.

M: Changes LCD drive outputs to AC.

V1

V3
V4

VEE
Figure I Different Power Supply Voltage Levels for LCD Drive Circuits

HITACHI

695

HD66204

~~~~~~~~

~D3t-r=--------------~
:::::::::::~

SHL=low

SHL = high

Figure 2 Selection of Destinations of Display Data Output

M~

1

r

L-....:;O_....I

D~
Youtput level

v:1

rvE~~v:~V1)~

Figure 3 Selection of LCD Drive Output Level

696

HITACHI

HD66204
Block Functions

Level Shifter

LCD Drive Circuit

The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.

Controller: The controller generates the latch
signal at the falling edge of each CL2 pulse for the
4-bit latch circuit

LCD Drive Circuit

4·Bit Latch Circuit
The 4-bit latch circuit latches 4-bit parallel data
input via the Do to D3 pins at the timing generated
by the control circuit.

The SO-bit LCD drive circuit generates four
voltage levels VI, V3, V4, and VEE, for driving
an LCD panel. One of the four levels is output to
the corresponding Y pin, depending on a
combination of the M signal and the data in the
line data latch circuit.

Line Data Latch Circuit
The SO-bit line data latch circuit latches data input
from the 4-bit latch circuit, and outputs the latched
data to the level shifter, both at the falling edge of
each clock I (CLl) pulse.

Block Diagram
Y1-Y80

DISPOFF _ _ _--J~4~r-.L..---_;_;:::_:;:::_;:;:;:;:;:=:;;:_--...L.-__,
CL1-----~>~L-~~--~-----~~-~

SHl-----------.~

Controller

CL2-----------.~
E~--------~>·L-----

________________________

~

CAR~----------------------------------------------~

HITACHI

697

HD66204
Comparison of the HD66204 with the HD61104
Hem

HD66204

HD61104

Clock speed

8.0 MHz max.

3.5 MHz max.

Display off function

Provided

Not provided

LCD drive voltage range

10-28 V

10-26 V

Relation between SHL and
LCD output destinations

See figure 4

See figure 4

Relation between LCD output
levels, M, and data

See figure 5

See figure 5

LCD drive V pins

V1, V3, V4
(V2 level is the same as VEE level)

V1,V2,V3,V4

2nd

1st

IM""\----,-------U
. 2nd
SHL.1ow

>~~~~~>~

Last

~~~~~~~~

~m!'I~·~p~~~~~1

In;~-:=1LJJ
Last

2nd

SHL. high

SHL. high

HD66204

HD61104

1st

Note the exact reverse relation for the two devices.

Figure 4 Relation between SHL and LCD Output Destinations for the HD66204 and H061104

M-.J:--:;-1-"L.....:!OL...Jr

O
L ...J.
M-II ----.;--"1-..J
1
.

D~

D~

Youtput level IYE'\joIIV4 .joIIV1.joIIV3 .1

HD66204

HD61104

Figure 5 Relation between LCD Output Levels, M, and Data for tbe HD66204 and H061104
698

HITACHI

HD66204
Operation Timing

Line

CL2

Data 0

Data 3
CL1

CAR
(No.1)

HD66204 no. 1 latChes data

CAR
(No.2)

HD66204 no. 2
latches data

CAR
(No.3)

HD66204 no. 3
latches data

CAR
(No. n)

Y1-Y80

HD66204 no. n
latches data

-~--------------------1'--

HITACHI

699

HD66204
Application Example

-

CAR

=}-

I

GND Vee

Notes:

R1

R1

R2

R1

R1

VEE

1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kO and 33 kO, respectively. That
is, R1/(4· R1 + R2) should be 1/15.
2. To stabilize the power supply, place two O.1-ILF capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.

700

HITACHI

HD66204
Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Power supply voltage for logic circuits

Vee

-0.3 to +7.0

V

Note.

Power supply voltage for LCD drive circuits

Vcc - 30.0 to Vee + 0.3 V

Input voltage 1

-0.3 to Vee + 0.3

V

1,2

Input voltage 2

VEE - 0.3 to Vee + 0.3

V

1,3

Operating temperature

Topr

-20 to +75

·C

Storage temperature

Tatg

-55 to + 125

Notes:

1. The reference point is GNO (0 V).
2. Applies to pins CL1, CL2, M, SHL, E, 0 0-03, DlSPOFF.
3. Applies to pins V1, V3, and V4.
4. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.

Electrical Characteristics
DC Characteristics ror the HD66204F/HD66204TF (Vee = S V ± 10%, GND = 0 V, Vee - VEE = 10
to 28 V, and Ta = -20 to + 7SoC, unless otherwise noted.)
Item

Symbol

Pins

Input high voltage

VIH

f

Input low voltage

Vil

2

Output high voltage

VOH

Output low voltage

VOL

2

Vi-Yj on resistance

RoN

3

Input leakage current 1

IIl1

Input leakage current 2

1112

Current consumption 1

IGND

Current consumption 2

lEE

Current consumption 3

1ST

4

Typ. Max.

Min.

Unit Condition

0.7 x Vcc

V

0

0.3 x Vee V

Note.

V

V

100--0.4 mA

0.4

V

iol- 0.4mA

4.0

kn

1oN-100~

-1.0

1.0

~

VIN. Vee to GNO

-25

25

~

VIN • Vcc to VEE

3.0

mA

fCl2 • 8.0 MHz
fCl1 -20 kHz
Vee- VEE. 28 V

2

500

~

Same as above

2

200

~

Same as above

2,3

Vcc- O•4

150

Pins and notes on next page.

HITACHI

701

HD66204
DC Characteristics lor the HD66204FUi1D66204TFL (Vee = 2.7 to S.s V, GND = 0 V, Vee - VEE =
10 to 28 V, and Ta = -20 to +7SoC, unless otherwise noted.)
Hem

Symbol

Pins

Min.

Max.

Unit
V

Input high voltage

VIH

0.7xVee

Vee

Input low voltage

Vil

1

0

0.3 x Vcc V

Output high voltage

Vcc-0.4

VOH

2

Output low voltage

VOL

2

Vi-Yj on resistance

RoN

3

Input leakage current 1

'll,

Input leakage current 2

IIL2

4

CondHlon

V

IOH--O·4mA

0.4

V

IOL-0.4mA

Note.

4.0

kn

IoN·100~

-1.0

1.0

~

VIN • Vee to GNO

-25

25

~

VIN - Vee to VEE

mA

fCl2 - 4.0 MHz
fCl' -16.8 kHz
fM - 35 Hz
VCC. 3.0 V
Vee - VEE. 28 V
Checker-board
pattern

2

Current consumption 1

IGND

1.0

Current consumption 2

lEE

500

~

Same as above

2

Current consumption 3

1ST

50

~

Same as above

2.3

Pins:

1.

CL 1. CL2. M. SHL. E. 00-03. OISPOFF

2. CAR
3. Y,-Y80 • V1, V3, V4
4. V1, V3, V4
Notes:

1. Indicates the resistance between one pin from Y,-Yeo and another pin from V1, V3, V4, and
VEE. when load current is applied to the Y pin; defined under the following conditions.
Vee-GNO. 28 V
V1. V3 = Vee - (211 O(Vcc - VEE)}
V4 - VEE + (211 O(Vee - VEE)}
V1 and V3 should be near Vee level, and V4 should be near VEE level (figure 6). All voltage
must be within AV. AV is the range within which RON, the LCO drive circuits' output
impedance, is stable. Note that AV depends on power supply voltage Vcr;-VEE (figure 7).
2. Input and output current is excluded. When a CMOS input is floating. excess current flows
from the power supply through the input circuit. To avoid this, VIH and VIL must be held to Vee
and GNO levels, respectively.
3. Applies to standby mode.

702

HITACHI

HD66204
Vee
---------. V1

IN

-----. V3

-------------- V4

IN

-L-----~~---------------------VEE

Figure 6 Relation between Driver Output Waveform and Level Voltages

5.6

-------------------

2.0

--------

INM
level vohage range

28

Vee-VEE (V)
Figure 7 Relation between Vee - VEE and AV

/

HITACHI

703

HD66204
AC Characteristics for the HD66204F/HD66204TF (Vee
+7SoC, unless otherwise noted.)
Item

Symbol

Pins

Clock cycle time

=S V ± 10%, GND = 0 V, and Ta =-20 to
Min.

Max.

Unit

tevc

Cl2

125

ns

Clock high-level width 1

teWH

CU. Cl2

45

ns

Clock low-level width

teWL

Cl2

45

ns

Clock setup time

tSCL

CL1. Cl2

80

ns

Clock hold time

tHCL

CU. Cl2

80

Clock rise time

tr

CL1. CL2

Clock fall time

tf

CU. CL2

Data setup time

tos

0 0-03 • CL2

ns
Note 1
Note 1

ns
ns

20

ns

Data hold time

tOH

0 0-03• CL2

20

ns

Enable (E) setup time

tEsu

E. Cl2

30

ns

Carry (CAR) output delay time

teAR

CAR. CL2

80

ns

M phase difference time

teM

M.CL2

300

ns

CL 1 cycle time

tell

CL1

AC Characteristics for the HD66204FLIHD66204TFL (Vee
to +7SoC, unless otherwise noted.)

=2.7 to S.Sv, GND =0 V, and Ta = -20

Symbol

Pins

Min.

Clock cycle time

Max.

Unit

tevc

Cl2

250

ns

Clock high-level width 1

teWH

CU. CL2

95

ns

Clock low-level width

teWL

CL2

95

ns

tSCL

CU. Cl2

80

ns

Clock hold time

tHCL

CL1. CL2

80

Clock rise time

tr

CU. CL2

Clock fall time

Note 1

ns

tf

CL1. CL2

tos

0 0-03• CL2

50

ns

Oata hold time

ns

tOH

0 0-03 • CL2

50

ns

Enable (E) setup time

tEsu

E. Cl2

65

ns

Carry (CAR) output delay time

teAR

CAR. CL2

155

ns

M phase difference time

teM

M. CL2

300

ns

CL 1 cycle time

tell

CL1

1. tr• tf < (tevc - tCWH - tewLlI2 and t r• tf ~ 50 ns
2. The load circuit shown in figure 8 is connected.

704

HITACHI

tcvc x50

Notes

ns
Note 1

Data setup time

Notes:

2

ns

tcvc x50

Item

Clock setup time

Notes

ns

2

HD66204

Test point 0---...,

~30PF

Figure 8 Load Circuit

tr

tCWH

tf

tCWL

tCVC

Cl2

O.7Vec

00-03

O.3Vec
tCWH

CL1

Cl2

14---....;;I~

tCM

O.7Vec
O.3Vec

M

Figure 9 LCD Controller Interface Timing

HITACHI
- - - -

------------

--

------

705

HD66205------------(Dot Matrix Uquid Crystal Graphic Display
Common Driver with SO-Channel Outputs)
Description
The HD66205F/HD66205FL/HD66205TF/HD
66205TFL1HD66205T1HD66205TL, the row LCD
driver, features low output impedance and as many
as 80 LCD outputs powered by 80 internal LCD
drive circuits, and can drive a large liquid crystal
graphic display. Because this device is fabricated
by the CMOS process, it is suitable for batterydriven portable equipment, which fully utilizes the
low power dissipation of liquid crystal elements.
The HD66205 has a complete line-up: the
HD66205F, a standard device powered by 5 V ±
10%; the HD66205FL, a 2.7-5.5 V, low power
dissipation device; the HD66205TF and
HD66205TFL, thin film package devices each
powered by 5 V ± 10% and 2.7-5.5 V; and the

706

HD66205T, tape carrier package (TCP) devices
powered by 2.7-5.5 V, respectively.

Features
•
•
•

HITACHI

Duty cycle: 1/64 to 1/240
High voltage
- LCD drive: 10-28 V
Display off function
Internal SO-bit shift register
Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD66850

HD66205
Ordering Information 1 (Flat package and die shipment)
Packase

Tyee No.

VoHase Ranse

HD6620SF

S V± 10%

100-pin ~Iastic OFP (FP-100)

HD6620SFL

2.7-5.S V

100-pin plastic OFP (FP-100)

HD6620STF

SV±10%

1OO-~in thin plastic OFP (TFP-100)

HD6620STFL

2.7-5.S V

100-~in

HCD6620S

S V± 10%

Chip

HCD6620SL

2.7-5.S V

Chi~

thin ~Iastic OFP (!FP-100)

Ordering Information 2 (tape carrier package)
Tyee No.

Voltase Ranse

Outer Lead Pitch 1

Outer Lead PHch 2

Device Lensth

HD6620STA1

2.7-S.5V

0.1Smm

0.80mm

4 serocket holes

HD6620STA2

2.7-S.SV

0.18mm

0.80mm

4 serocket holes

HD6620STA3

2.7-S.SV

0.20mm

0.80mm

4 serocket holes

HD6620STA6

2.7-S.SV

O.22mm

0.70mm

4 sprocket holes

HD6620STA7

2.7-S.SV

0.2Smm

0.70mm

4 sprocket holes

HD6620STA9L

2.7-S.SV

O.22mm

0.70mm

3 sprocket holes

Notes:

1.
2.
3.
4.

Outer lead pitch 1 is for LCD drive output pins, and outer lead pitch 2 for the other pins.
Device length includes test pad areas.
Spacing between two sprocket holes is 4.7Smm.
Tape film is Upirex (a trademark of Ube industries, Ltd.).
5. 3S-mm-wide tape is used.
6. Leads are plated with Sn.
7. The details of TCP pattern are shown in • The Information of TCP.•

HITACHI

707

HD6620S
Pin Arrangement

X51
X52
X53
X54
X55

X56
X57
X58
X59
X60
X61
X62
X63

HD66205F
HD66205Fl
(FP-100)

X64
X65

X66
X67
X68
X69
X70
X71
X72
X73
X74
X75
X76

xn
X78
X79
X80

51
M~~~~~~~~~~~~~~~~~~~
o
Z

00 0z W
W

>

>11) cD>

>~ 0

LL. O...J 0 0 ::!! 0
ZLL.OZzz
Z
~>enC)

en
Ci
(Top View)

708

HITACHI

...J
O 0
Z

15

°

0
Zz

X30
X29
X28
X27
X26
X25
X24
X23
X22
X21
X20
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1

HD66205

X53
X54
X55
X56
X57
X58
X59
X60
X61
X62
X63
X64
X65
X66
X67
X68
X69

8m~~~~~~~mgm~~~~~~~~~~~~~

75
74
73
72
71
70
69
68

HD6620STF
HD6620STFL
(TFP-100)

67
66
65
64
63

62
61
60
59

X70

58

X71
X72
X73
X74

57
56

X75
X76
X77

53

55

54
52

X27
X26
X25
X24
X23
X22

X21
X20
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3

(Top View)

HITACHI

709

HD6620S
Pin Description
Symbol

Pin No.
(FP-100 I TFP-100}
40/38

Vee

Power supply

GND

42140

GNO

Power supply

VeE
V1
V5

34/32

Power supply

37135

Vee

Pin Name

Input/Output

Classification

va

36/34

VEE
V1
V5
V6

Input

Power supply

CL

46/44

Clock

Input

Control signal

M

44142

M

Input

Control signal

01

48/46

Data in

Input

Control signal

DO

32131

Data out

Output

Control signal

SHL

41/39

Shift left

Input

Control signal

35/33

Input

Power supply

Input

Power supply

OISPOFF

39/37

Display off

Input

Control signal

X1-Xao

51-100,1-301
1-28,49-100

X1-X80

Output

LCD drive output

NC

31,33,38,43,
45, 47, 49, 501

No connection

29,30,36,41,

43,45,47,48

710

HITACHI

HD66205
Pin Functions

DO: Outputs display data. DO of the last
HD66205 must be open, and those of the other
HD66205s must be connected to DI of the next
HD66205.

Power Supply
Vee, VEE, GND: Vec-GND supplies power to the
internal logic circuits. Vcc-VEE supplies power to
the LCD drive circuits.
VI, V5, V6: Supply different levels of power to
drive the LCD. VI and VEE are selected levels,
and V5 and V6 are non-selected levels. See figure
1.
Control Signal
CL: Inputs data shift clock pulses for the shift
register. At the falling edge of each CL pulse, the
shift register shifts display data input via the DI
pin.

SHL: Selects the data shiftt direction for the shift
register. See figure 2.
DISPOFF: A low DISP sets LCD drive outputs
X1-X go to VI level.
LCD Drive Output
X1-X go: Each X outputs one of the four voltage
levels VI. V5. V6. or VEE. depending on a
combination of the M signal and display data
levels. See figure 3.

Other
NC: Must be open.

M: Changes LCD drive outputs to AC.
01: Inputs display data. DI of the first HD66205
must be connected to an LCD controller, and those
of the other HD66205s must be connected to DI of
the previous HD66205.

V1
V6

V5

VEE
Figure I Different Power Supply Voltage Levels for LCD Drive Circuits

HITACHI

711

HD6620S

Common signal
scan direction

SHL level

Data shift direction

Low

Il ~SR1 .SR2 .SR80

X1

High

Il • SR80~ SR79 • SR1

X80~X1

~

Figure 1 Selection of Display Data Shift Direction

M.-J

1

0.-

D~
X output level

rvtrvt~E~rvtl

Figure 3 Selection of LCD Drive Output Level

712

HITACHI

X80

HD6620S
Block Functions

Shift Register

LCD Drive Circuit

The SO-bit shift register shifts data input via the DI
pin by one bit, and the one bit of shifted-out data is
output from the DO pin. Both actions occur
simultaneously at the falling edge of each shift
clock (CL) pulse

The SO-bit LCD drive circuit generates four
voltage levels VI, V5, V6, and VEE, for driving an
LCD panel. One of the four levels is output to the
corresponding Y pin, depending on a combination
of the M signal and the data in the shift register
Level Shifter
The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.

Block Diagram
X1-X80

V1,VEE
V5
V6,
M

~~~~~~~:=:===]~~~~c===::~
=

DISPOFF
CL

Shift register

DI
SHL

DO~----------------------------------------------~

HITACHI

713

HD66205
Comparison of the HD66205 with the 8D61105
Item

HD66205

HD61105

Display off function

Provided

Not provided

LCD drive voltage range

10-28 V

10-26 V

Shift clock phase selection function

Not provided

Provided (FCS pin)

Relation between SHL and
LCD output destinations

See figure 4

See figure 4

Relation between LCD output
levels, M, and data

See figure 5

See figure 5

LCD drive V pins

V1,V5, V6
(V2 level is the same as VEE level)

V1, V2, V5,V6

SHL level

Data shift direction

Common signal
scan direction

SR1 ~ SR2 ~ SR80

Low

OJ •

High

OJ • SR80. SR79 • SR1

X1 -> X80
X80->X1

HD66205

SHL level

Data shift direction

Common signal
scan direction

Low

OJ • SR80. SR79 • SR1

X80->X1

High

OJ • SR1

~ SR2 ~ SR80

X1. X80

HD61105
Note the exact reverse relation for the two devices.

Figure 4 Relation between SHL and LCD Output Destinations for the HD6620S and HD61l0S

M-.J

1

0

r

M.....J

D~
X output level

~V1 ~~VS ~1¥E'iI.V6 ~I

1

0

r

D~
X output level

HD6620S

~V2 .~V6 .~V1.~ VS ~
HD6110S

Figure 5 Relation between LCD Output Levels, M, and Data for the HD6620S and HD61l0S
714

HITACHI

M--.J...
From
LCD
controller
"Ij

dei'
c

:if

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II)

8

co

!!.
D)

eo
r:I'

~

~

o

:I:

i

~
0

-

:I

80 1 2 3

X79 (COM2)

~~ ... _ __

;
X1 (dOM80)

~ .....

V6

V1

:I
til

DO

t""
==

1601 2 3

t""

~
t;:j

V1

c

V6
X1 (COM160) ~......

t;:j

240 1 2 3

- _...... -%

-_...... -LJv1
V2

.....

..... --1V6 ..... 1JV6 .... .

~

1Y.§........
V1
lY.!i....

V1

~

.. .... V1 V5

. ....

----1'V6 ..... UVS·····

. ....

----1'V6 ..... --, roEI'"

.....

----1'V6 .....

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V2

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!So

~
....
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0

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.,flo'

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I'D

eo
§
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a

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g

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s·
8'
..,

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g-

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io·

L ...... ___ __ ..... IL ..... __.
n

--

160 1 2 3

~.

......

V6
X79 (~OM82)~ ..... ~

a'
oS'

80 1 2 3

V2

.Jl.YL-......

V6
X80 (C0M81) ~ •...• ........J

:I
CI.

2401 2 3

- - ..... ~ .....
--QJVs....

n .. _

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~I

1 frame

.....

240 1 2 3

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:I

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JL.....
...... JL
cLmlliIt ..... ftJffi1t .... ..rtftHft ..... _ ..... R .....•......•

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1 frame

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...... "I..YL.
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ttl
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~

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.. ... ~
...... "I..YL.

~

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00 _ _ _ ,

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eo
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~~

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II)

o

:I:

::::!

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:

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----[jw...... ~
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t..r's.... i.YL
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o

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t,,)

c:>

(II

HD6620S
Application Example

OND Vee

Notes:

lit

At

AI

At

lit

1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1115 bias, R1 and R2 must be 3 kn and 33 kn, respectively. That
is, R1/(4' R1 + R2) should be 1/15.
2. To stabilize the power supply, place two O.1"I1F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.

716

HITACHI

HD6620S
Absolute Maximum Ratings
Hem

Symbol

Rating

Unit

Power supply voltage for logic circuits

Vee

-0.3 to +7.0

V

Power supply voltage for LCD drive circuits

VEE

Vee - 30.0 to Vee + 0.3 V

Notes

Input voltage 1

-0.3 to Vee + 0.3

V

1.2

Input voltage 2

VEE - 0.3 to Vee + 0.3

V

1.3

Operating temperature

Topr

-20 to +75

·C

Storage temperature

Tstg

-55 to +125

·C

Notes:

4

1. The reference point is GND (0 V).
2. Applies to pins CL. M. SHL. DI.-::D~IS=-=P:-::O:-::F=F.
3. Applies to pins V1. V5. and VS.
4. -40 to + 125·C for TCP devices.
5. If the LSI is used beyond its absolute maximum ratings. it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
.
degradation of reliability.

Electrical Characteristics
DC Characteristics for the HD6620SF/HD6620STF (Vee
to 28 V, and Ta = -20 to +7SoC, unless otherwise noted.)
Item

Symbol

Input high voltage

VIH

Pins

=5 V ± 10%, GND =0 V, Vee -

Typ. Max.

Min.

Unit Condition

0.7 x Vee

Vee

0.3 x Vee V

Input low voltage

Vil

1

0

Output high voltage

VOH

2

Vec- O.4

Output low voltage

V

IOH=-o·4mA

VOL

2

0.4

V

IOL .. 0.4 mA

RoN

3

2.0

kn

ioN .. 100 JJ.A

VIN .. Vee to VEE

100

JJ.A
JJ.A
JJ.A

500

JJ.A

Input leakage current 1

Illl

1

-1.0

1.0

11L2

4

-25

25

Current consumption 1

IGND

Current consumption 2

lEE

150

=10

Notes

V

Vi-Vj on resistance

Input leakage current 2

VEE

VIN .. Vee to GND
fel .. 20 kHz
Vee - VEE" 28 V

2

Same as above

2

Pins and notes on next page.

HITACHI

717

HD6620S
DC Characteristics for the HD66204FLIHD66204TFL/HD66204T (Vee =2.7 to S.s V, GND
Vee - VEE = 10 to 28 V, and Ta = -20 to +7SoC, unless otherwise noted.)
Item

Symbol

Input high voltage

VIH

Input low voltage

VIL

Output high voltage

VOH

Pins

2

Output low voltage

VOL

2

Vi-Yj on resistance

RON

3

Input leakage current 1

IlL'

Input leakage current 2

11L2

Current consumption 1

Min.

Max.

Unit

0.7 x Vee

Vee

V

0

0.3 x Vee V
V

IOH--Q.4 mA

0.4

V

IOL .0.4 mA

2.0

k.Q

ioN - 100 mA

-1.0

1.0

~

VIN - Vee to GNO

-25

25

~

VIN - Veeo to VEE

100

~

Vee- 0.4

4

Condition

IGND

leL -16.8 kHz

=0 V,
Notes

2

1M - 35 Hz
Vee ·3.0V
Vee - VEE - 28 V
Current consumption 2
Pins:

lEE

250

Same as above

2

1. CL, M, SHL, 01, OISPOFF

2. DO
3. X,-Xso, V1, V5, V6
4. V1, V5, V6
Notes:

1. Indicates the resistance between one pin from X,-Xso and another pin from V1, V5, V6, and
VEE, when load current is applied to the X pin; defined under the following conditions.
Vee - VEE" 28 V
V1, V6 .. Vee - (1/1 O(Vee - VEE)}
V5 .. VEE + (1/1 O(Vee - VEE)}
V1 and V6 should be near Vee level, and V5 should be near VEE level (figure 7). All voltage
must be within AV. AV is the range within which RON, the LCD drive circuits' output
impedance, is stable. Note that AV depends on power supply voltage Vcc;-VEE (figure 8).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows
from the power supply through the input circuit. To avoid this, VIH and VIL must be held to Vee
and GNO levels, respectively.
3. Applies to standby mode.

718

HITACHI

HD66205
Vee
V1

tN

V6

-------------- V5

I!N

VEE

Figure 7 Relation between Driver Output Waveform and Level Voltages

2.8
tN(V)

Level voltage range

1.0 --------

28
Vee-VEE (V)

Figure 8 Relation between Vee - VEE and t:.V

HITACHI

719

HD6620S
AC Characteristics for the HD66205F/HD6620SfF (Vee = 5 V ± 10%, GND = 0 V, and Ta = -20 to
+75°C, unless otherwise noted.)
Item

Symbol

Pins

Clock cycle time

Min.

Max.

Unit

tcvc

CL

10

J.1s

Clock high-level width 1

tcWH

CL

50

ns

Clock low-level width

tcWl

CL

1.0

Clock rise time

tr

CL

Clock fall time

tf

CL

Data setup time

tDS

DI,CL

100
100

Data hold time

tDH

01, CL

Data output delay time

tDD

DO,CL

Data output hold time

tDHW

DO,CL

Note

J.1s

30
30

ns
ns
ns
ns

3.0
100

J.1s
ns

AC Characteristics for the HD66205FL/HD6620SfFL/HD6620Sf (Vee = 2.7 to 5.5 V, GND = 0 V,
and Ta = -20 to +75°C, unless otherwise noted.)
Item

Symbol

Pins

Clock cycle time

Min.

Max.

Unit

tcvc

CL

10

J.1s

Clock high-level width 1

tcwH

CL

80

ns

Clock low-level width

tcWl

CL

1.0

Clock rise time

tr

CL

30

Clock fall time

tf

CL

Data setup time

tDS

01, CL

100

Data hold time

tDH

DI,CL

100

Data output delay time

tDD

DO,CL

Data output hold time

tDHW

DO,CL

Notes:

100

O---l'"
;1;

30 pF

Figure 9 Load Circuit

720

HITACHI

ns
ns
ns
ns

7.0

1. The load circuit shown in figure 9 is connected.

test point

J.1s

30

J.1s
ns

Note

HD6620S

ill
CL

tCWL

O.7VCC",,\

tCWH

III

tOO

tOS

IX

DI

\~

"'\...

I

O.3Vcc -'['-

tCYC

O.7Vec
O.3Vcc

tOH

=K

tOHW

DO

O.BVec "I
O.2VCC7

g~

Figure 10 LCD Controller Interrace Timing

HITACHI

721

HD66214T (Micro-TAB)-(SO-Channel Column Driver
in Micro-YCP)
Description

Features

The HD66214T, the column driver for a large
liquid crystal graphic display, features as many as
80 LCD outputs powered by 80 internal LCD
drive circuits. This device latches 4-bit parallel
data sent from an LCD controller, and generates
LCD drive signals. In standby mode provided by
its internal standby function, only one drive circuit
operates, lowering power dissipation. The
HD66214, packaged in an 8-mm-wide micro-tape
carrier package (micro-TCP) , enables a compact
LCD system with a narrower frame (peripheral
areas for LCD drivers) -about half as large as
that os an existing system. The HD66214T is a
low power dissipation device powered by 2.7-5.5
V suitable for battery-driven portable equipment
such as notebook personal computers and palmtop personal computers.

•
•

Duty cycle: 1/64 to 1/240
High voltage
- LCD drive: 10--28 V
• High clock speed
- 8 MHz max under 5-V operation
(HD66214T)
- 4 MHz max under 3-V operation
(HD66214lL)
• Display off function
• Internal automatic chip enable signal generator
• Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD66850
• 98-pinTCP

Ordering Information
Type No.

VoHage Range

Outer Lead Pitch 1

Outer Lead Pitch 2

Device I;-ength

HD66214TAl

2.7-5.5 V

0.15 mm

0.80mm

3 sprocket holes

HD66214TA2

2.7-5.5 V

0.18 mm

0.80mm

3 sprocket holes

HD66214TA3

2.7-5.5 V

0.20 mm

0.80 mm

3 sprocket holes

HD66214TA6

2.7-5.5 V

0.20 mm

0.45 mm

3 sprocket holes

HD66214TA9L

2.7-5.5 V

0.22 mm

0.45 mm

2 sprocket holes

Notes:

1. Outer lead pitch 1 is for LCD drive output pins, and outer lead pitch 2 for the other pins.
2. Device length includes test pad areas.
3. Spacing between two sprocket holes is 4.75 mm.
4. Tape film is Upirex (a trademark of Ube Industries, Ltd.).
5. 35-mm-wide tape is used.
6. Leads are plated with Sn.
7. The details of TCP pattern are shown in • The Information of TCP.•

722

HITACHI

HD66214T
Pin Arrangement

Vee
E
DO
01
02
03
CL2
CL1
M

DISPOFF

,

1
2
3

Dummy

J

4

5
6
7
8

98
97
96

Y1
Y2
Y3

21
20
19

Y78

9

CAR

10
11

Vee
SHL
GND
VEE
V4
V3
V1

12
13
14
15
16
17
18

Y79
Y80

,

Dummy

J
Top view

HITACHI

723

HD66214T
Pin Description
Symbol

Pin No.

Pin Name

Vee
GND

1.12

Vee
GND

Power supply

VEE
V1

15

Power supply

18

VEE
V1

Input

Power supply

V3

17

V3

Input

Power supply

14

Input/Output

Classification
Power supply

V4

16

V4

Input

Power supply

CL1

8

Clock 1

Input

Control signal

Cl2

7

Clock 2

Input

Control signal

M

9

M

Input

Control signal

0 0-0 3

3-6

Data Iklata 3

Input

Control signal

SHL

13

Shift left

Input

Control signal

E

2

Enable

Input

Control signal

CAR

11

Carry

Output

Control signal

DISPOFF

10

Display off

Input

Control signal

Y1-Yeo

19-98

Y1-Y80

Output

LCD drive output

724

HITACHI

HD66214T
Pin Functions

M: Changes LCD drive outputs to AC.

Power Supply

Do-D3: Input display data. High-voltage level of
data corresponds to a selected level and turns an
LCD pixel on, and low-voltage level data
corresponds to a non-selected level and turns an
LCD pixel off.

Vee, VEE, GND: Vcc-GND supplies power to the
internal logic circuits. Vcc-VEE supplies power
to the LCD drive circuits.
VI, V3, V4: Supply different levels of power to
drive the LCD. Vl and VEE are selected levels,
and V3 and V4 are non-selected levels. See figure
1.

SHL: Shifts the destinations of display data
output See figure 2.
E: A low E enables the chip, and a highE disables
the chip.

Control Signal
CAR: Outputs theE signal to the next HD662l4 if
HD662l4s are connected in cascade.

CLI: Inputs display data latch pulses for the line
data latch circuit. The line data latch circuit
latches display data input from the 4-bit latch
circuit, and outputs LCD drive signals
corresponding to the latched data, both at the
falling edge of each CLl pulse.

LCD Drive Output

CL2: Inputs display data latch pulses for the 4-bit
latch circuit. The 4-bit latch circuit latches display
data input via Do-D3 at the falling edge of each
CL2pulse.

Y1-YSO: Each Y outputs one of the four voltage
levels Vl, V3, V4, or VEE, depending on a
combination of the M signal and display data
levels. See figure 3.

DlSPOFF: A low DISP sets LCD drive outputs
y 1-Y 80 to Vllevel.

V1
V3

V4
VEE

Figure I Different Power Supply Voltage Levels for LCD Drive Circuits

HITACHI

725

HD66214T

>~~~~~!;:~

~~~ ~~~~ ~

:::::::::::~
D2
. -----------.
.
03 .......=-------------st

C1
SHL=low

SHL = high

Figure 2 Selection 01 Destinations 01 Display Data Output

M

-1

1

'---o"--.....r

D~

Youtput level· rvE:rV4tV1tv:1

Figure 3 Selection 01 LCD Drive Output Level

726

HITACHI

HD66214T
Block Functions

Level Shifter

Controller: The controller generates the latch
signal at the falling edge of each CL2 pulse for the
4-bit latch circuit

The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit

4·Bit Latch Circuit
The 4-bit latch circuit latches 4-bit parallel data
input via the 00 to D3 pins at the timing generated
by the control circuit.
Line Data Latch Circuit

LCD Drive Circuit
The SO-bit LCD drive circuit generates four
voltage levels VI, V3, V4, and VEE, for driving
an LCD panel. One of the four levels is Oiltput to
the corresponding Y pin, depending on a
combination of the M signal and the data in the
line data latch circuit.

The SO-bit line data latch circuit latches data input
from the 4-bit latch circuit, and outputs the latched
data to the level shifter, both at the falling edge of
each clock I (CLl) pulse.

Block Diagram
Y1-Y80

DISPOFF--------~~~r--~----~~~~~~------~--,
CL1

>

SHl------------~

Controller

CL2 ------------~

E

CAR~------------------------------------------~

HITACHI

727

HD66214T
Comparison of the H066214 with the HD61104
Item

HD66214

HD611 04

Clock speed

8.0 MHz max.

3.5 MHz max.

Display off function

Provided

Not provided

LCD drive voltage range

10-28 V

10-26 V

Relation between SHL and
LCD output destinations

See figure 4

See figure 4

Relation between LCD output
levels, M, and data

See figure 5

See figure 5

LCD drive V pins

V1,V3,V4
(V2 level is the same as VEE level)

V1,V2,V3,V4

Storage temperature

-40 to 125°C

-55 to 125°C

Package

TCP (tape carrier package)

QFP (quad flat package)

2nd

1st

1st

SHL-Iow

2nd
SHL-Iow

>~~~~~~~

Last

~~~~~~~!

~m!~:~~]g~~~~~~~1

JLJJ

IMI----::
Last
2nd
SHL. high

SHL. high

1st

HD61104

HD66214

Note the exact reverse relation for the two devices.

Figure 4 Relation between SHL and LCD Output Destinations for the 8D66214 and 8D61104

728

HITACHI

HD66214T
M ---Ir-:;-L_..QO:"'-Jr

M .....Ir-:;-L_..QO_Jr

D~

D~

Y output level

~EE.~V4 .,/1 .~V3.,

Y output level

HD66214

V1

~

V3

.~

V2

.~

V4

.~

.,

HD61104

Figure 5 Relation between LCD Output Levels, M, and Data for the HD66214 and HD61104

HITACHI

729

HD66214T
Operation Timing

i

r

Cl2

~
I1 2 3

________•

19 201

I

~~~ 1)

::.pc:x:::x:: --------. ::::x:::::xJX:: -----. ::::x::::xrx:::
-Ii
!
---f<
I

I

(No.2)

----Ii
:

CAR
(No.3)

CAR
(No. n)

Y1-Y80

--.J!
I

HD66214 no. 1 latches data

I
I
I

I
~I

'"

'"

rLl-II
I

rI

>1

HD66214 no. 2
latches data

r-

I

>1

HD66214 no. 3
latches data

I

l---

.....
0111(:-~;!1..._--11
HD66214 no. n
i

---I
i

iI

latches data

II

C
.

==:]
I
:
:

I
I
I

.

730

I

I

I

CAR

____ roL_
--X..J.-U-

i
! !

•

CL1

I

21

=PCX=X=
-------. :x::nx:= - - - .
I i ·
I

Data 3

~

1
JUl:fi- _______ ~

i

Data 0

I

UM

k

HITACHI

HD66214T
Application Example

--

=11141-----,

~I

\-

i~:":§fi~x-.....,

v.....

L.:Sr=HL_j-E

! L==::i

CAR

l5iSi'Ofi!~lmlffm
DO-03

II

HO&I214

CL2

(11

Cll

I

R1
GND Vee

Notes:

R1

R2

R1

R1

VEE

1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1115 bias, R1 and R2 must be 3 kn and 33 kn, respectively. That
is, R1/(4 • R1 + R2) should be 1/15.
2. To stabilize the power supply, place two O.1-~F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.

HITACHI

731

HD66214T
Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Power supply voltage for logic circuits

Vee

-0.3 to +7.0

V

Power supply voltage for LCD drive circuits

VEE

Vee - 30.0 to Vee + 0.3

V

Input voltage 1

VT1

-0.3 to Vee + 0.3

V

Input voltage 2

VT2

1,2
1,3

Operating temperature

Topr

-20 to +75

Storage temperature

Tstg

-40 to +125

Notes:

Notes

1. The reference point is GNO (0 V).
2. Applies to pins CL 1, CL2, M, SHL, E, 0 0-03 , OISPOFF.
3. Applies to pins V1, V3, and V4.
4. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.

Electrical Characteristics
DC Characteristics for the HD66214T (Vee

=S V ± 10%, GND =0 V, Vee -

VEE

=10 to 28 V, and

Ta = -20 to +7SoC, unless otherwise noted.)
Item

Typ. Max.

Unit Condition

Symbol Pins

Min.

Input high voltage

V1H

0.7 x Vee

Vee

Input low voltage

VIL

0

0.3 x Vee V

Output high voltage

VOH

2

Output low voltage

VOL

2

Vi-Vj on resistance

RON

3

~nput

leakage current 1

lilt

Input leakage current 2

IIL2

Current consumption 1

4

Current consumption 2

lEE
1ST

IOH--o·4mA

V

IOL - 0.4mA

4.0

kn

ION-100~

1.0

~

VIN .. Vee to GNO

-25

25

~

VIN .. Vee to VEE

3.0

mA

feL2 ,. 8.0 MHz
feL1 .. 20 kHz
Vee - VEE -28 V

2

500

~

Same as above

2

200

~

Same as above

2,3

150

Pins and notes on next page.

732

V

-1.0

IGND

Current consumption 3

V

0.4

Vee- O•4

Notes

HITACHI

HD66214T
DC Characteristics for the HD66214T (Vee = 2.7 to S.s V, GND = 0 V, Vee - VEE = 10 to 28 V, and
Ta = -20 to +7SoC, unless otherwise noted.)
Pins

Max.

Unit

0.7xVee

Vcc

V

0

0.3 xVcc V

Item

Symbol

Input high voltage

VIH

Min.

Input low voltage

VIL

1

Output high voltage

VOH

2

Vcc- 0.4

Output low voltage

VOL

2

Vt-Yj on resistance

RoN

3

Input leakage current 1

1111

Condition

V

IOH--o·4mA

0.4

V

IOL-0.4mA

4.0

k.Q

ION .. 100

-1.0

1.0
25

IJ.A
IJ.A

VIN - Vee to GNO

-25

Notes

IJ.A

Input leakage current 2

11L2

Current consumption 1

IGND

1.0

mA

fCL2 .. 4.0 MHz
fCl1 - 16.8 kHz
f M -35 Hz
Vee - 3.0 V
Vcc - VEE" 28 V
Checker-board
pattern

Current consumption 2

lEE

500

2

1ST

50

IJ.A
IJ.A

Same as above

Current consumption 3

Same as above

2,3

Pins:

1. CL1, CL2, M, SHL,

4

VIN .. Vee to VEE
2

E, Do-Os, DISPOFF

2. CAR
3. Y1-Y80, V1, V3, V4
4. V1, V3, V4
Notes:

1. Indicates the resistance between one pin from Y 1-Yao and another pin from V1, V3, V4, and
VEE, when load current is applied to the Y pin; defined under the following conditions.
Vee-GNO= 28 V
V1, V3 = Vee - (211 O(Vee - VEE)}
V4

=VEE + (2110(Vcc -

VEE)}

V1 and V3 should be near Vee level, and V4 should be near VEE level (figure 6). All voltage
must be within IN. AV is the range within which RON, the LCD drive circuits' output
impedance, is stable. Note that AV depends on power supply voltage Vee-VEE (figure 7).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows
from the power supply through the input circuit. To avoid this, VIH and VIL must be held to Vee
and GNO levels, respectively.
.
3. Applies to standby mode.

HITACHI

733

HD66214T
Vee

•••••••••. V1

IN

••••• , V3

•••••••••••••• V4

tN
-L--~~---------VEE

Figure 6 Relation between Driver Output Waveform and Level Voltages

5.6

.•.••....••.••.•. _--

2.0

........

tN(V)

Level voltage range

28

Vee-VEE (V)
Figure 7 Relation between Vee - VEE and !J.V

734

HITACHI

HD66214T
AC Characteristics for the HD66214T (Vee
otherwise noted.)

=5 V ± 10%, GND =0 V, and Ta =-20 to +7SoC, unless
Max.

Symbol

Pin.

Min.

Clock cycle time

tevc

CL2

125

ns

Clock high-level width 1

tcwH

CL1, CL2

45

ns

tcwL

CL2

45

ns

Clock setup time

tSCL

CL1, CL2

80

ns

Clock hold time

tHCL

CL1, CL2

80

ns

Clock rise time

1,

CL1, CL2

*1

ns

Clock fall time

t,

CL1, CL2

*1

ns

Hem

Clock low-level width

Unit

20

ns

Data setup time

tos

Data hold time

tOH

00-03, CL2

20

ns

Enable (E) setup time

~su

E,CL2

30

ns

Carry (CAR) output delay time

00-03' CL2

teAR

CAR, CL2

80

ns

M phase difference time

teM

M,CL2

300

ns

CL1 cycle time

tel1

CL1

AC Characteristics for the HD66214T (Vee
otherwise noted.)

=2.7 to 5.5 V, GND =0 V, and Ta =-20 to +7SOC, unless

Symbol

Pins

Min.

tevc

CL2

250

Clock high-level width 1

Max.

Unit

teWH

CL1, CL2

95

ns

teWL

CL2

95

ns

Clock setup time

tSCL

CL1, CL2

80

ns

Clock hold time

tHCL

CL1, CL2

120

ns

Clock rise time

1,

CL1, CL2

*1

ns

Clock fall time

t,

CL1, CL2

*1

ns

Data setup time

tos

00-03, CL2

50

ns

Data hold time

tOH

00-03, CL2

50

ns

Enable (E) setup time

65

tESU

E,CL2

Carry (CAR) output delay time

1cAR

CAR, CL2

M phase difference time

teM

M,CL2

tel1

CL1

Notes:

1.

1"

t, < (tevc -

tevc x50

Note.

ns

Clock low-level width

CL1 cycle time

2

ns

tcvc x50

Clock cycle time

Hem

Note.

ns
155

ns

300

ns

2

ns

tcWH - tewdl2 and t r, t, S 50 ns

2. The load circuit shown in figure 8 is connected.

HITACHI

735

HD66214T

Test point Of----..,

±30 PF

Figure 8 Load Circuit

Ir

ICWH

If

ICWL

ICYC

CL2

O.7Vee

00-03

O.3Vcc

ICWH

tCL1

CL1

CL2

CAR

O.8Vec

E

tCM
M

O.7Vee
O.3Vcc

Figure 9 LCD Controller Interface Timing

736

HITACHI

HD66224T-----(Dot Matrix Liquid Crystal Graphic Display
Column Driver with SO-Channel Outputs)
Description

Features

The HD66224T is a column driver for dot matrix
liquid crystal graphic display ststem. It has 80
liquid crystal drive circuits and can drive large
LCDs. The column driver latches parallel data for
display (4/8 bit parallel) from the controller. then
generates a drive signal and selects the proper LCD
drive voltage. A built-in standby function that
allows all internal drivers except one to be placed
in standby mode (1ST) lowers device power
consumption. The column driver package is a 7.5mm wide ultra-small tape carrier package (TCP).
allowing designs using half the frame area of
conventional displays.

•
•
•
•

The column driver can be used in a wide range of
battery-powered designs because its logic power
supply can operate with an input voltage ranging
from 2.5 to 5.5 V.

Display duty cycle: 1/64 to 1/240
Number of liquid crystal drive circuits: 80
Parallel data transfer: 4/8 bits
High voltage: Drive voltage 10-28 V (absolute
maximum rating 30 V)
• High-speed operation: Maximum clock speed 8
MHz (for 5 V) or 6.5 MHz (for 2.5 V)

• Logic power supply voltage: 2.5-5.5 V
• Built-in display off function
• Built-in automatic generation function for chipenable signal
• Built-in standby function
• 107-pin TCP

Ordering Information
Type No.

Data Input

Input Format

Outer Lead Pitch (Jlm)

HD66224TA1

4-bit input

Straight

210

HD66224TA2

4-bit input

Straight

200

HD66224TBO

a-bit input

Straight

200

Note: The details of TCP pattern are shown in "The Information of TCP."

HITACHI

737

HD66224T
Internal Block Diagram
Figure 1 is a block diagram of the HD66224T.

circuit 1 on the falling edge of clock CLl and
outputs the data to the level shifter circuit.

Liquid-Crystal Drive Circuit
The LCD drive circuit selects from four available
voltage levels (VI. V3. V4. and VEE) based on the
combination of the data of latch circuit 2 and input
to pin M. The circuit outputs the selected voltage to
the LCDs.

Latch Circuit 1
Latch circuit 1 consists of 4/8-bit parallel data
latches that store input data Do to 0-, when signaled
by the shift register.
Control Circuit

Level Shifter
The level shifter circuit raises the voltage of the
logic power-supply voltage to the level used for
driving the LCDs.

The control circuit generates signals that fetch the
data for input to latch circuit 1.
Data Rearrange Circuit
The data rearrange circuit performs left to right
(Sill.) inversion on data Do to 0-,.

Latch Circuit 2
The 80-bit latch circuit 2 latches data from latch

738

HITACHI

HD66224T
Pin Arrangement

~~~~180W~-12~~8~8~d~d~.~~~~~

~>~>m~m~~

~Im»>~

00

is
Note: This illustration does not correspond to the external shape of the TCP package.

Pin Description
Table 1
Type

Power
supply

Pin Description
Symbol
Vcc1
Vcc2
GND
VEEL '
VEER
V1L
VIR
V3L
V3R
V4L
V4R

Pin
Number

89
102
86
107
81
104
84
105
83
106
82

Pin Nam.IIO Function

Vcc 1

Vcc- GND: Connect to logic power supply.

Vcc2
GND

Vcc- VEE:

Connect to power supply for liquid-crystal
drive circuit.

VEEL
VEER
V1L
VIR
V3L
V3R
V4L
V4R

Liquid crystal drive level power supply
---------. VI

----- - V3
~
-- V

4

----. VEl:
VI. VEE: selected level
V3. V4: nonselected level
The power supply should maintain the condition Vee;;: VI >
V3> V4 > VEE. The Land R sides of V1.V3• and V4 are
separated within the device. so the potentials externally
supplied to them must be identical.

HITACHI
- - - - --------- -

739

HD66224T
Pin Description (cont)

Table 1
Type

Symbol

Pin
Number

Pin Name 1/0 Function

Control
signal

CL1

92

Clock 1

CL2

93

Clock 2

Synchronizes the drive signal that latches display data into
latch circuit 1.

I

Synchronizes the drive signal that latches display data into
latch circuit 2.

M

91

M

Converts the liquid crystal drive output to AC.

0 0-07

94 to 101

Data 0-7

Display Data

LCD Drive Output

High

Selected level

On

Low

Nonselected level

Off

SHL

88

Shift left

Inverts the data output destination.
4-bit input mode:
SHL

Input data and latch address

Low

High

t--'..,........

....L-........,~-J..

""";:0-0

0,
02r-------~~--

03

a-bit input mode:
SHL

Input data and latch address

Low

High

1"10;::-0-t-........,~-'--'-..L.-J-J..

0,

1--'----07

740

HITACHI

LCD

HD66224T
Pin Description (cont)

Table 1
Type

Symbol

Pin
Number

Pin Name I/O

Function

Control
Signal
(cont)

'iJSi5CfF

90

Display off I

When the liqtlid crystal output nonselected level control input
pin drives IlSPCfFlow. the liquid crystal drive output (Y1 to
Yso) is set to the V1 level.

801

103

Enable

110

"1101
EJa!

85

1/0 pins for chip selection. Input/output is controlled by SHL
input.

Enable

1102

SHL

EnableI/O 1

Enable 110 2

o

Output

Input

Input

Output

When the enable input signal goes low. data fetch begins.
When all data has been fetched. the enable output changes
from high to low and the next stage IC starts up.

Liquid
crystal
drive
output

BS

87

Y 1 to Yso

1 to 80

Bus select I

Switches the number of input bits for the display data. When
high. places the device in 8-bit input mode; when low.
changes the device to the 4-bit input mode.
Outputs one of the four voltage levels V1. V3• V4. or VEE.
based on the combination of the M signal and the display
data.
AC signal M

.-J

lor

Displaydata ~
Output level

1111

~IIII ~I" ~IIII ~I

VEE V4

V1

V3

Note: 0 and low levels inCJicate ground level. High levels indicate Vee level.

HITACHI

741

HD66224T
Sample Application
Figure 2 shows an example of an LCD panel
comprised of 640 x 200 dots. using the HD66224T.
The recommended common driver is HD66215.
For 640 x 400 dots. extend the configuration shown
to configure two screens.

When designing a board locate bypass capacitors as
close to each device as possible. to stabilize the
power supply. We recommend that two capacitors
(of about 0.1 pF) be used with each HD66224T.
One capacitor should be connected between Vee
and GND. and one between Vee and VEE'

R 1 and R2 differ depending on the LCD panel
used. For a 1/15 bias. for example. Rl = 3 k.Q and
R2 = 33k.Qare used so that Rl(4Rl + R2) = 1/15.

742

HITACHI

HD66224T

LCD panel

640 x 200
11200 duty cycle

--

---

I I

Figure 2 Application Example

HITACHI

743

HD66224T
Absolute Maximum Ratings
Parameters
Power supply voltage

Logic circuit

Symbol

Rating

Unit

Notes

Vee

-0.3 to +7.0

V

*1

------------------~~------------------------------

Liquid crystal drive circuit

VEE

Vee - 30.0 to Vee + 0.3

Input voltage (1)

Vn

-0.3 to Vee + 0.3

V

*1, *2

Input voltage (2)

VT2

VEE - 0.3 to Vee + 0.3

V

*1, *3

Operating temperature

Topr

-20 to + 75

·C

Storage temperature

Tstg

-40 to + 125

·C

Notes: 1.
2.
3.
4.

Indicates the potential from GNO.
Applies to the CL1, CL2, M, SHL, 00f, EI02, Do to 0 7 , and DISPOFF pins.
Applies to the V1 , V3 , and V4 pins.
When a device is used outside of the absolute maximum ratings, it may suffer permanent
damage. Exceeding the limits may cause malfunctions and have negative effects on device
reliability. We recommend that device operating parameters be kept within these limits.

Electrical Characteristics
Table 2

DC Characteristics (1) (Unless otherwise specified, Vee
Vcc - VEE = 10 to 28 V, Ta = -20 to +75°C)

Parameter

Symbol

Pin

Min

Input high
VIH
level voltage

CL1, CL2, M,
SHL, Do to 0 7

Input low
Vil
level voltage

Max

Unit

0.8x Vee

Vee

V

801, EI02,
1lSPaT, BS

0

0.2 x Vee

V

Output high VOH
level voltage

801,~

Vee- O.4

Output low VOL
level voltage

801,802

Resistance
between Vi
andYj

RON

Y1 to Yao, V1,
V3, V4

Input
leakage
current 1

11L1

Input
leakage
current 2

IIl2

744

Typ

= 5 V ± 10%, GND = 0 V,
Measurement
CondHlons

V

IOH =-0.4mA

0.4

V

IOl = 0.4 mA

1.5

kn

ION = 100 I1A

CL1, CL2, M,
-1.0
SHL, DO to 07,
801, EI02,
1lSPaT, BS

1.0

I1A

VIN = Vee to GNO

V1, V3 , V4

25

I1A

VIN = Vee to VEE

0.6

-25

HITACHI

Notes

*1, *2

HD66224T
Table 2

DC Characteristics (1) (cont)

Parameter

Symbol

Current
consumption 1

IGND

Current
consumption 2

lEE

Current
consumption 3

1ST

Pin

Min

Typ

150

Measurement
Conditions

Max

Unit

3.0

mA

feL2 = 8.0 MHz
feu" 20 kHz

500

!LA

Vee-VEE =28V

200

!LA

Notes
*3

*3. *4

Notes: 1. This is the resistance value between the Y pin and V pin (V1. V3• V4. or VEE) when a load current
flows to one of the pins Y1 to Yeo. Set with the following conditions:
Vee-VEE = 28V
V1• V3 = Vee - 2110(Vee - VEE)
V4 = VEE + 2110(Vee - VEE)
2. Describes the voltage range for the liquid-crystal drive level power supply. A voltage near Vee is
supplied to V1 and V3. A voltage near VEE is supplied to V4. Use within the range of 6V for each.
These ranges should be set so that the impedance ROM of the driver output obtained is stable.
Note also that 6V depends on the power supply voltage (Vee - VEE). See figure 3.
3. Excluding the current flowing to the input area and output area. When the driver uses an
intermediate level for input. a through current flows to the input circuit and the power supply
current increases. so be sure that VIH = Vee and VIL .. GND.
4. Current during standby.

6V

6V

~

vee

--- V1
- V3

~ 5.6

>

 11 ns

HITACHI

747

...

-_.._ - - - - - - - - -

HD66224T
AC Characteristic Test Waveforms

-mor

Figure 4 shows test point loading and test
waveforms. Connect test points through a 15-pF
capacitor to ground. as shown at the top of figure 4.

automatically halted (standby). If the
pin is .
connected to the mo2 pin of the next stage. the
next device will begin 4-bit fetch operation.

BS = GND (4-Bit Fetch Mode)

The data output changes when CLl falls. The
output destination for the fetched data when Sill.
GND is output pin YSO for d 1. and Y1 for dso.

=

When the data fetch operation enable signal goes
low (with SHL = GND and 'Bm1 = GND). data
standby is cleared. On the next rising edge of clock
CL2. the standby is cleared. Figure 5 shows timing
for 4-bit fetch mode operation. When CL2 falls. the
fIrSt 4-bit data fetch is performed. The 4-bit fetches
continue on each subsequent falling edge of CL2
until 76 bits have been fetched. The enable signal
(when SHL = GND. BIOI) then goes to GND
level. When 80 bits have been fetched. fetch is

Test point

When SHL = Vee. the destinations are reversed;
dso is output to Yso and dl is output to YI. The
output level (V I through V4) is actually selected by
the combination of the display data and AC signal
M.

0----.
j.15 PF
tcWHl

Clock 1

0.8 Vec
0.2 Vcc
tSCL

Clock 2

Data 0 to 7

0.8 Vcc Final data
0.2 Vcc

Priority data

tcvc - tCWH2 - tCWl2

2

Figure 4 AC Characteristic Waveforms
748

HITACHI

HD66224T
1
1

Line

1
I~

1
1
1
1

CL2

1
1
1

---D--D--CU1- ---

~

191 20 1 21

1

1
1

---1101
:

1
1

1
1

1
1
1

Fetch period for
IC (No.1) data

EI02
(No.3)
EI02
(No.4)
Y1 toYao

1
1

1
1
1

i
rL
1

r-

1

1

~i

:

1

EI02
(No.2)

1
1

=xbcbc i

i i

11

1
1

EI02
(No.1)

1
1

SW1flJlln

~---=x:bcbc
1
1

D7~
1
CL1

1

~
--1
1

DO~
1
to

1

22

1

~

Fetch period for IC (No.2) data ....~I---tl~~---~~-+-----ll
:
:

~r---FF;~~chhPp;erricio~d~f~or~I~C~(NNbO.~3ij)dd~~~a~~~=1I~~~-J-JL---Jr-:

~

:

~I--t::~~il__~r-

Fetch period for IC (No.4) data ....

:

:

1

1

C

~
1

1

Figure 5 Operation Timing (4-Bit Fetch Mode)

HITACHI

749

HD66224T
BS = v cc (8~Bit Fetch Mode)
The 8-bit data fetch basic functions are the same as
in the 4-bit fetch mode. Figure 6 shows timing for
8-bit fetch mode operation.

1

1

:

Line

:..

:

.:

1
1
1

OL2

1
1

1

JlDlJ-D--- JJ-OJJ-O--- .Jl-llJl-I4Jl
1 2 3
9 10 11 12
1
1

00

~
1

07

~

J1

I..
--.,
(No.1)
:
EI02
(No.2)
EI02
(No.3)
EI02
(No.4)

j

1
1

1

1

1
1

---

1
1

1
1

=xbcDc

!

=xtx:tx=

!

1
1
1

---

1
1
1

1

rL

! !

1
1

EI02

1
1

~

1

0L1

1
1

~
1
1

1
1

to

1
1

Fetch period for
10 (No.1) data

1
1

1
1

1

.:

Fetch period for 10 (No.2) data..

1
1

I:

r-:

I.

:

1

:

~rl---FF:;e;tc;t;h~p;;;eririo;;;d~ffoo;riCIO~{~Nk;o~.33i)~d~a~ta~"-====1I~.~J_J1L_-Jr:

~

:

:

--It-

Fetch period for 10 (No.4) data ......I--"t=::!.i.:__

:

:

1

1

-v

-rI

Y1 to Y80 -.Ji\

""--

I~-------------------------------------------I

1

1

Figure 6 Operation Timing (8-Bit Fetch Mode)

750

HITACHI

HD66215T-----(Common Driver for a Dot Matrix Uquid
Crystal Graphic Display with 100-Channel Outputs)·
Description

Features

The HD662IST is a common driver for a large dot
matrix liquid crystal graphic display (LCD). The
driver's 100 channels can be divided into two
groups of SO channels by selecting data input/
output pins. Outputs Xl to X 10 and X91 to X 100 can
be disabled by mode selection. Unused output pins
can be equally distributed above and below the
pins used for the LCD panel so that the panel can
be neatly centered on the LCD board. A 101channel output mode can also be selected for an
application to various display panels. The driver is
powered by about 3 V, making it suitable for
battery-driven portable equipment featuring the
low power dissipation of liquid crystal elements.

•

The HD662IST, packaged in a micro-tape carrier
package (micro-TCP), allows design of a compact
LCD system with a frame (an area peripheral to the
LCD panel) about half the width of conventional
systems.

•
•

•
•
•

•
•

Duty cycle: About 1/64 to 1/240
100 internal LCD drive circuits (101-channel
mode can be selected for a WI-output version)
High output voltage for driving the LCD:
10-28 V
Output division function (SO x 2-output)
IO-output through modes
WI-output mode
Display off function
Internal lOO-bit shift register
Various LCD controller interfaces
- LCTC series: HD6364S, HD6464S,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD668S0
Micro-TCP with 3-sprocket-hole width
Operating voltage: 2.5-S.S V

Ordering Information
Type No.

Outer Lead Pitch 1

Outer Lead Pitch 2

Device Length

HD66215TAO

0.23 mm

1.20 mm

3 sprocket holes

HD66215TA1

0.22 mm

1.00 mm

3 sprocket holes

HD66215TA2

0.18 mm

0.85mm

3 sprocket holes

Notes: 1.
2.
3.
4.
5.
6.
7.

Outer lead pitch 1 is for LCD drive output pins, and outer lead pitch 2 for the other pins.
Device length includes test pad areas.
Spacing between two sprocket holes is 4.75 mm.
Tape film is Upirex (a trademark of Ube Industries, Ltd.).
35-mm-wide tape is used.
Leads are plated with Sn.
The details of TCP pattern are shown in "The Information of TCP:

HITACHI

751

HD66215T
Tape Carrier Package

000000000000000000000

x

E
E
~

8

x

00000000000000000000000

Pin Arrangement

> ~ ~
...I

...

752

N

('I)

...I

w

~

"It

...

W

i

II)

Q
0

~
!a

a~

...

0

~

>

ell

... ...... ... ... ... ... ... ....... ... ...

~

U)

0

0

Z

::i

...I

0

(!)

Q 0~
0

0

CQ

....

a: a: a: a:

~ :t:~

GI

0

HITACHI

N

('I)

"It

II)

i

CQ

~

~

ell

GI

HD6621ST
Pin Description
Symbol

Pin No.

Vee
GNO

8

Pin Name

12

Vee
GNO

V1l. V1R

1.20

V1l. V1R

Vel. VeR

2. 19

Vel. VeR

Vsl. VsR

3. 18

Vsl. VsR

Veel.VEeR

4.17

Veel. VeeR

Cl

14

Clock

InpuUOutput

Input

Control signal

M

13

M

SHLIR

9

ShHt left/right

0101

15

Data

InpUUoutput

0102

11

Input

0103

10

0104

6

Classification
Power supply

DISj5CFF

7

Display off

MOOE1. MOOE2

5. 16

Mode1. Mode2

Xl-Xl!!!!

21-120

Xl-X l00

Output

HITACHI

lCO drive output

753

HD66215T
Pin Functions
Power Supply

DI02 are data input/output pins for X1-Xso, and
DI03 and DI04 are input/output pins for XSI-XIOO
(XlOl) in 50 x 2-output modes. In a lOO-output
mode, DI02 and DI03 must be short-circuited, and
DI01 and DI04 are used as data input/output pins.

Vee, GND: Supply power to the internal logic
circuits.

VIL, VIR, VsL, VsR,

V~, V~,

VEEL, VEER:

Supply different levels of power to drive the LCD.
V 1 and VEE are selected levels, and V5 and V6 are
non-selected levels. See figure I.

DISPOFF: Controls LCD output level. A low

Control Signals
CL: Inputs data shift clock pulses for the shift
register. At the falling edge of each CL pulse, the
shift register shifts data input via the DIO pins.

MODEl, MODE2: Select an LCD output mode
(table 1). In lO-output through modes, ten unused
output pins are made invalid. These ten pins must
be open in these modes since they output M
signals.

M: Changes LCD drive outputs to AC.

LCD Drive Outputs

DISPOFF sets LCD drive outputs XI-X IOO (XIOl)
to VI level.

SHLIR: Selects the data shift direction for the shift
register and the common signal scan direction
(figure 2).

Xr-X Ioo: Each X outputs one of the four voltage
levels, VI. Vs. V6 , or VEE. depending on a
combination of the M signal and data levels. See
figure 3.

Dl01-Dl04: Input or output data. DI01 and

Table 1 Selection of LCD Output
MODE1

MODE2

Selected Mode

0

0

Normal (100-output)

0

1O-output through

1

(X 1-X 10)
(X91 -X 100)

0
101-output

----- --- --- --- --- ------ --- --- --- --- --- V1
------------ Vs
----------------- Vs
----------------------

VEE

Figure 1 DiITerent Power Supply Voltage Levels for LCD Drive Circuits

754

HITACHI

HD6621ST

SHUR

0101

0102

0103

Data shift direction and common
signal scan direction

0104

In 100 x 1-output mode

I

Input

I

I

Low

X,-X,oo

Output

Short-circuited

In 50 x 2-output mode
Input

Input

Output

X,-X50
Xs,-X,oo

Output

In 100 x 1-output mode
Output

I

I

I

High

X,oo-X,

Input

Short-circuited

In 50 x 2-output mode
Output

Input

Output

X50- X,
X,oo-Xs,

Input

For 10-outputthrough modes and 101-output mode, see Selection of Data Shift Direction
and Common Signal Scan Direction by SHUR and 010 Pins in Each Mode.

Figure 2 Selection or Data Shift Direction and Common Signal Scan Direction by SHLIR
and DIO Pins in Normal Mode (IOO·Output Mode)

M

~

0

~

X output level

0

I

0

0

I
I

I. -I" -I" -I" -I
V,

VS

VEE

Ve

Figure 3 Selection or LCD Drive Output Level

HITACHI

755

HD66215T
Block Diagram

V,l
Vel
OISPOFF

~~~~~ll-U~~~l

Vsl
VEEl=

~.r----,

i'.....lI_ _ _ _....IL_ _ _ _...JL_ _ _ _- - - I L -_ _ _....I

M

Cl
0101 ___r---,"-I

0102
0103
0104
SHUR----~~~;-~~-~~~---~~+H---+;-~+r--_+~

MOOE1
MOOE2

756

logic 3

HITACHI

HD66215T
Block Functions
LCD Drive Circuits

Shift Registers

The lOO-bit LCD drive circuits generate four
voltage levels. VI. Vs. V6• and VEE. which drive
an LCD panel. One of the four levels is output to
the corresponding X pin. depending on a
combination of the M signal and the data in the
shift register.

The lOO-bit shift registers shift data input via the
010 pin by one bit The bit that is shifted out is
output from the 010 pin to the next driver IC. Both
shifting and output occur simultaneously at the
falling edge of each shift clock (CL) pulse. The
SlU../R pin selects the data shift direction.

Level Sbifters

Logic 3

The level shifters change logic control signals
(2.5-5.5 V) into high-voltage signals for the LCD
drive circuit

Logic 3 selects which shift register operates depending on the settings of MODEl and MODE2.

HITACHI

757

HD66215T
Data Shift and Common Signal Scan
Direction
Figure 4-7 show the data shift direction and
common signal scan direction selected by SHLIR

SHUR

0101

0102

0103

and DIO pins in each mode.

0104

Oata shift direction and common
signal scan direction

In 100 x 1-output mode
Input

I

I

I

Output

Short-circuited

Low

X1-X 100

In 50 x 2-output mode
Input

Output

Input

I

I

X1-XSO

Output

XS1-X100

In 100 x 1-output mode
Output

I

Input

Short-circuited

High

X1OO -X 1

In 50 x 2-output mode
Output

Input

Output

XSO-X1

Input

X100-XS1

Figure 4 Selection of Data Shift Direction and Common Signal Scan Direction by SHUR
and DIO Pins in 100-Output Mode (MODEl 0 and MODE2 0)

=

758

HITACHI

=

HD66215T

SHLIR

0101

0102

0103

I

I

0104

Data shift direction and common
signal scan direction

In 90-output mode
Input

I

Short-circuited

Low

Output

X11 -X100

In 40- and 50-output mode
Input

Output

Input

I

I

X11 -X50

Output

XS1 -X 100 '

In 90-output mode
Output
High

I

Short-circuited

Input

X1OO -X 11

In 40- and 50-output mode
Output

Input

Output

X50 -X 11

Input

X1OO -XS1

Figure 5 Selection of Data Shift Direction and Common Signal Scan Direction by SHLIR
and DIO pins in IO-Output (X1-X10) Through Mode
(MODEl 0 and MODE 2 1)

=

HITACHI

=

759

HD6621ST

SHUR

0101

0102

0103

0104

Data shift direction and common
signal scan direction

In gO-output mode
Input

I

I

I

Short-circuited

Low

X1 -X90

Output

In so- and 40-output mode
Input

Output

Input

X1 -X50

Output

XS1 -X90

In gO-output mode
Output

I

I

I

Short-circuited

High

X90 -X 1

Input

In 50- and 40-output mode
Output

Input

Output

X50 -X 1

Input

X90 -XS1

Figure 6 Selection of Data Shift Direction and Common Signal Scan Direction by SHLIR and
DIO Pins in 10·Output (X91-X 1OO) Through Mode
(MODEl I and MODE2 0)

=

760

HITACHI

=

HD66215T

SHUR

0101

0102

0103

0104

Data shift direction and common
signal scan direction

In 101-output mode
Input

I

I

I
Short-circuited

Low

Output

X 1 - X 101

In 50- and 51-output mode
Input

Output

Input

X1 - X50

Output

XS1-X101

In 101-output mode
Output

I

I

I
Short-circuited

Input

X 101 - X1

High
In 50- and 51-output mode
Output

Input

Output

X50 ---X 1

Input

X101-XS1

In 101-output mode, any 10-output through mode cannot be used.

Figure 7 Selection of Data Shift Direction and Common Signal Scan Direction by SHLIR and
010 Pins in lOl·Output Mode (MODEl 1 and MODE2 1)

=

HITACHI

=

761

HD66215T
Application Examples

:=

!-

CAR

~
DiiPofF~~~ll

I( J

i:-

HD&e2.4T

!-

CAR

LCD,*", or 840 x 400 doll;
.1200dutr cydo

CII

eL.

V,I-+++++-+

v,
o v,

\-

:.jHL=--iE'-i;~tiiiRii.J~-W

V"--'':--::!::-'=
I::::'<=-~fl

-n

CAR

&oa>1HCl1 ! (

in· _.. -_. _.. _.. _. --. -_.. _.. _.. _.

~X,-x,..:'r(GNO,~X,-X",::'r
~ SHL

GNO- SHL
-

010. HD002.5T 0104 - - - 010. Hoaea.5T 0104
C'I
i r 0102
C41
[ 0102
01011
MODE2
I ' 0I0Il
1A00E2
~
MODE.. __ •
~
IAODEt

r;f ::DI~>::~='d2 ! ::D~>::':Jtf2

~

\->

~: I-H-HH-+
oV,
H.J
~~

E

JGNO

;JSHL~~~:H
v", --'

I-'

....:-

---

III

r. r.

~

r:

R1

R2

At

GND Vt;t;

R1

A1

v..

I

Notes: 1. The resistances of R1 and R2 depend on the type of LCD panel used. For example. for an LCD panel with a 1115 bias. R1
and R2 must be 3 knand 33 kg. respectively. ThaI is. Rlf(4'Rl + R2) should be 1.115.
2. To stabilize the power supply. place two O.I-1'f capacilors near each LCD driver: one between the Vee and GND pins. and
lhe other between the Vee and Vee pins.

Figure 8 LCD Panel of 640 x 400 Dots, 1/200 Duty Cycle
762

HITACHI

HD66215T

1
~
FI.M
CL
M

6fiIIar!/!

LCD "",II '" 840 • ..0 dolo;
11240 dutr cycle

v..

Notes: 1. The tesistances of R1 and R2 depend on the type of LCD panel used. For example, for an LCD panel whh a 1/15 bias, R1
and R2 must be 3 kn and 33 kn, respectively. That is, R1/(4' R1 + R2) should be 1/15.
2. To stabilize the power supply, place two O.1·JlF capacitors near each LCD driver: One between the Vee and GND pins, and
the other between the Vee and VEE pins.

Figure 9 LCD Panel of 640 x 480 Dots, 1/240 Duty Cycle

HITACHI

763

HD66215T
From
HD66215T (2)

/

HD66215T(1)

"
...

-r
-x
8 ······82

-x
0_

!

-

...

!!:

!!:

~

LCD
controller

Og

~

0

/

C

0

!

"...

-)(

-J<-x

...

~

88
····8!!:!!:8!!:

.§

/

c

0

r-

(5

"

!!:

5'

§

...

i

~ , ~ ~ ~~ ~~
:

:

:

:

:

:

~::
I
.I
•

:•
:
•

::

:
::
'"
:::
• • •

...

i

,::.

CD

~,

:

f ~ ~ ~~;:~
:

::

I
••

I
.
••

I

I .
• •

:: :

:

I
••
I
. ••

••I

I
"

.

I

I

Figure 10 Operational Timing in Normal Mode (lOO·Output Mode, 1/200 Duty Cycle)
764

HITACHI

HD66215T
HD6621ST Connection Examples
Figure 11 shows an example of an HD66215T
driving a 480-line LCD panel with a 1/240 to 1/250
duty cycle. Here, selecting MODEl and MODE2
disables outputs X1-X lO of driver IC1 and outputs
X 91 -X lOO of driver IC5. As a result, unused driver
output pins can be equally distributed above and
below the pins used for the LCD panel so that the
panel can be neatly centered on the LCD board. In

addition, since the 100 channels of the driver can
be divided into two groups of 50 channels by
selecting data input/output pins, data input is
divided at the center of the panel (IC3).
Figure 12 shows an example of an HD66215T
driving a 400-line LCD panel with a 1/200 to 1/210
duty cycle.

HITACHI

765

HD66215T

LCD panel

IC1

·::,,
X100

f-+

Line 90

IC2
Line 190

X1
IC3
Data - - - . I

IC4

••• ~5;!l...

Line 191

XS1

f-+ . ..l:I~.!~.~.................... .
f-+ Line 1

X100

f-+

Line 50

X1

-..

Line 51

X100

-..

Line150

X1

-..

Line 151

···:
:
I

·,

1

Upper panel display
•
Division
Lower panel display

1

IC5
-.. Line240
-..,.. _ ... __ .. ___ ....
X ___
(not..........
output)
!
_____ .... __ .. __ .. I

Figure 11 Connection Example for 480·Line LCD Panel with a 1/140-1/250 Duty Cycle

766

HITACHI

HD66215T

SHLIR is low

+ rXl
,,

Data

LCD panel
Une 1

,,,
,,
,,

IC1

,
X l00

r-

Une 100

Xl

t-

Une 101

X l00

r-

Une200

t
,,
,,,
,
:,
,

IC2

t
Data

---------- --- -_. -------------

Xl

r-

Une 1

X l00

:--

Une 100

Xl

t-

Une 101

Xl 00

t-

Une200

1

Upper panel display

I
Lower panel display

IC3

•
IC4

,,
,
:,
,,,
,

1

Figure 12 Connection Example for 400-Line LCD Panel with a 1/200-11210 Duty Cycle

HITACHI

767

HD66215T
Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Note

Power supply voltage
for logic circuits

Vee

-0.3 to +7.0

V

2

Power supply voltage
for LCD drive circuits

VEE

Vee - 30.0 to Vee + 0.3

Input voltage 1

Vn

-0.3 to Vee + 0.3

2,3

VT2

VEE - 0.3 to Vee + 0.3

2,4

Topr

-20 to +75

2
Operating temperature
Storage temperature

-40 to +125
Tatg
Notes: 1. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunction or
unreliability.
2. The reference point is GNO (0 V).
3. Applies to pins CL, M, SHLlR, 0101-0104 (input), OISPOFF.
4. Applies to pins V1, Vs, and Va.

768

HITACHI

HD6621ST
Electrical Characteristics

=

=

=

DC Characteristics (Vee 2.5 to 5.5 V, GND 0 V, and T. -20 to +75°C, unless otherwise noted)

Max

UnH Condition

0.7 x Vcc

Vee

V

0

0.3 x Vee

'iYP

Symbol Pins Min

Hem
Input high voltage

VIH

Input low voltage

Vil

1

Output high voltage

VOH

2

Output low voltage

Va.

2

Vi-Xj on resistance

RON

3

1.0

kn

ION .100 IIA

Input leakage current 1

Illl

4

-1.0

1.0

IIA

VIN .. Vee to GND

2

11L2

5

-25

25

VIN = Vee to Vee

3

1113

2

-5.0

5.0

VIN - Vee to GND

100

fCl - 19.2 kHz

250

Vcc - Vee· 28 V

Vcc- 0.4

IOH--o·4mA
0.4
0.5

Current consumption (5 V) IGND
lee

Nota

10l- 0.4mA

2

fFlM" 80 Hz
Vcc -GND.5 V
(3 V) IGND
lee

50

fCl" 19.2 kHz

250

Vcc - Vee - 28 V
f FlM • 80 Hz

2

Vcc-GND.3V
Pins: 1.
2.
3.
4.
5.

Cl. M. SHUR. DISPOFF.DI01-DI04 (input)
0101-0104 (input)
Xl -Xl00• Vl • Vs. Va
CL, M. SHUR. MODE1. MODE2. DISPOFF
Vl • Vs. Va

Notes: 1. Indicates the resistance between one pin from Xl -Xl00 and another pin from Vl • Vs. Va. and
Vee. when load current is applied to the X pin. Defined under the following conditions:
Vee - Vee· 28 V
Vl • Va" Vee -{1110 (Vcc-Vee)}
Vs - Vee + {1110 (Vee -Vee)}
Vl and Va should be near Vee level. and Vs should be near Vee level (figure 4). All voltage must
be within t:. V. t:. V is the range within which RON. the LCD drive circuits' output impedance. is
stable. Note that t:. V depends on power supply voltages Vee - Vee (figure 5).
2. Excludes input and output current. When a CMOS input is floating. excess current flows from the
power supply through the input circuit. To avoid this. VIH and Vil must be held to Vee and GND
levels. respectively.

HITACHI

769

HD66215T

IL-----

~v

.---.

~v

I 1--------------

Vee
VI
Vs

Vs
VEE

Figure 13 Relation between Driver Output Waveform and Level Voltages

2.8 ------.. ------------~V(V)

1.0 --------

10

Level voltage range

28

Vee - VEE (V)

Figure 14 Relation between Vee - VEE and ~ V

770

HITACHI

HD66215T
AC Characteristics (Vee =2.5 to 5.5 V, GND =0 V, and T. =-20 to +7S oC, unless otherwise noted)

Max

Symbol

Pins

Min

Clock cycle time

tcvc

CL

10

I1s

Clock high-level width

ns

Item

tcWH

65

Clock low-level width

tcWL

1.0

Clock rise time

tr

Clock fall time

tf

Data setup tirne

tos

Data hold time

tOH

Data output delay time"

too

0101-0104, CL

50

IJ.S
ns

7.0

I1s

100

Data output hold time

100

tOHW
Note: "The load circuit is shown in figure 15 is connected.

±

Test point 0 - - - - ,

Unit

ns

.

30pF

Figure 15 Load Circuit

Ir

CL

O. 7V cc \
O.3Vcc r

ICYC

~r

/
too

los

\

X

F-o.7Vcc

0101-0104
(Input)

'--

IOH

~O.3Vcc

X

IOHW

0101-0104
(output)

O.75Vcc
O.25Vcc

~

'-'

Figure 16 LCD Controller Interrace Timing

HITACHI

771

HD66106F-----(LCD Driver for High Voltage)
Description

Pin Arrangement

The HD66106F LCD driver has a high duty ratio
and many outputs for driving a large capacity dot
matrix LCD panel.
It includes 80 LCD drive circuits and can drive at up
to 1/480 duty cycle. For example, only 14 drivers
are enough to drive an LCD panel of 640 x 480 dots.
It also easily interfaces with various LCD control·
lers because of its internal automatic chip enable
signal generator.
Using this LSI sharply lowers the cost of an LCD
system.

Features
Column and row driver
80 LCD drive circuits
Multiplexing duty ratios: 1/100 to 1/480
4·bit parallel data transfer
Internal automatic chip enable signal generator
Internal standby function
Recommended LCD controller LSIs:
HD63645F and HD64645F (LCTC)
Power supply: +5 V ± 10% for the internal logic,
and 14.0 V to 37.0 V for LCD drive circuits
• Operation frequency: 6.0 MHz (max.)
CMOS process

Ordering Iuformation
Typ No.

Package

H066106FS

100-Pin Plastic QFP

H0661 060

Chip

(FP-100A)

HITACHI

II I II II II II II II II II II U H II U II II II •

!~~~;!Ra~a§~888d~~'~
(Top view)

HD66106F
Pin Description
Power supply

Control signals

Vee. GND: Vee supplies power to the internal
logic circuit. GND is the logic and drive ground.

CLl: The LSI latches data at the negative edge of
CLl when the LSI is used as a column driver. Fix
to GND when the LSI is used as a row driver.

VLCD : VLCD supplies power to the LCD drive circuit.

CL2: The LSI latches display data at the negative
edge of CL2 when the LSI is used as a column
driver. and shifts line select data at the negative
edge when it is used as a row driver.

VI, V2, Va, and V,: VI'V, supply power for driving
LCD (figure 1).

M: M changes LCD drive outputs to AC.

Do-D3: Do-D3 input display data for the column
driver (table 2).

Table 1 Pin Function
Symbol

Pin No.

Pin Name

Vee

49

Vee

GND

37·

Ground

VLCO
V,
V.
V,
V.

31.36

VLCO

32

LCD voltage 1

33
35

V.
V,
V4

CL1

38

Clock 1

CL2

40

Clock 2

M

42

M

0.-0,

46-43

Data 0 to data 3

SHL

39

Shift laft

E

47

Enable

CAR

48

Carry

CH1

41

Channel 1

Y,-Y ••

30-1.100-51

Drive outputs 1-80

NC

50

No connection

34

.

-----------------v.

~------v.

I/O

LCD voltage 2
LCD voltage 3
LCD voltage 4

o
o

Table 2 Relation between Display Data and
LCD State

----Va

----------v.

Display Data

LCD Outputs

LCD

1 1= high level)

Selected level

On

01= low level)

Nonselected level

Off

V" V.: Selected level
V•• V 4: Nonselected level

Figure 1 Power Supply for Driving LCD

HITACHI

n3

HD66106F
LSI is used as a column driver (CHI = Vcd. CAR
outputs scan data when the LSI is used as a row
driver (CHI = GND). When HD66106Fs are con·
nected in cascade, CAR connects with E of the next
LSI.

SHL: SHL controls the shift direction of display
data and line select data (figure 2, table 3).

E: 13 inputs the enable signal when the LSI is used
as a column driver (CHI =Vcd. The LSI is dis·
abled when 13 is high and enabled when low. 13 in·
puts scan data when the LSI is used as a row driver
(CHI = GND). When HD66I06Fs are connected in
cascade, E connects with CAR of the preceding LSI.

CHt: CHI selects the driver function. The chip
drives columns when CHI = Vcc, and rows when
CHI =GND.
Y 1 .y80: Each Y outputs one of the four voltage
levels-VI, V2, V 3, or V4 -according to the com·
bination of M and display data (figure 3).

CAR: CAR outputs the enable signal when the

NC: NC is not used. Do not connect any wire.

Table 3 Relation between SHL and Sean DireetiOn of Selected Line (When LSI is Used as a Row Driver)
SHL

GND

Shift Direction of Shift Register

Seen Direction of Selectad Line

E

... 1

- 2

- 3 .............. _ 80

E

-80

-79

-78··············... 1

V, -V. "'V. ·············:······_V•.•
v•• -V,. -V.. ····················... V,

F
"DD
D1

--···M
_._-

D2
D3

When SHL = Vee

When SHL = GND

Figure 2 Relation between SHL and Data Output (When LSI is Used as a Column Driver)

D~
Y outputleveq. v, j. v, .j. v•• j v•• j

D~
Y output levelj v•• j. vI.j

Whan Used as a Column Driver

When Used as a Row Driver

Figure 3 Se1eetion of LCD Drive Output Level

774

HITACHI

v, .j. v.

HD66106F
Internal Block Diagram
LCD Drive Circuits

Latch Circuit 1

The HD66106F (figure 4) begins latching data when
E goes low, which enables the data latching operation. It latches 4 bits of data simultaneously at the
fall of CL2 and stops automatically (= standby
state) when it has latched 80 bits.

Latch circuit I is composed of twenty 4-bit parallel
data latches. It latches the display data Do -D3 at
the fall of eL2 when the LSI is used as a column
driver. The signals sent from the selector determine which 4-bit latch should latch the data.

Latch Circuit 2

Selector

When the LSI is used as a column driver, latch
circuit 2 functions as an 80-bit latch circuit. It
latches the data sent from latch circuit I at the
fall of eLl and transfers its outputs to the LeD
drive circuits.

The selector is composed of a 5-bit up and down
counter and a decoder. When the LSI is used as a
column driver, it generates the latch signal to be
sent to latch circuit I, incrementing the counter at
the negative edge of eL2.

When the LSI is used as a row driver, this circuit
functions as an 80-bit bidirectional shift register.
The data sent from the E pin shifts at the fall of
eL2. When SHL = VCC, the data shifts from bit 1
to bit 80 in order of entry. When SHL =GND, the
data shifts from bit 80 to bit 1.

lli'i

II
CHI

~
! ..l::::::o

The controller operates when the LSI is used as a
column driver. It stops data latching when twenty
pulses of eL2 have been input (= power-down
function) and automatically generates the chip
enable signal announcing the start of data latching
into the next LSI.

Y,Y,Y,Y,

"1i
M

Controller

II11
11 213141

IJ

II

II

Logic

11 21+1

SHL

.

CL2

YLogiC
CLl

1,2,3,4
I", , ,'~

SO-bit latch circuit and bidirectional
shift register (Latch circuit 2)

ILogic
~

~~
l

r-- Vee

r - GND

+++~ r -

-(,

17178j19l80

...5~

D,D,

r - V LCD

.~

lr
Latch circuit 1 (4-bit x 20)

-

17178119180

LCD drive circuits

I I

I

Selector
\

Controller

I

Figure 4 Block Diagram

HITACHI

775

HD66106F
Functional Description
Data outputs change at the fall of CLI. Latched
data d l is transferred to the output pin Y I and
d so to Y80 when SHL =GND. Conversely, d 80 is
transferred to Y I and d I to Y 80 when SHL =Vee.
The output level is selected out of V I-V4 according to the combination of display data and the
alternating signal M (figure 5).

When Used as a Column Driver
The HD66106F begins latching data when E goes
low, which enables the data latching operation. It
latches 4 bits of data simultaneously at the fall of
CL2 and stops automatically (= standby state)
when it has latched 80 bits.

CL2

3

2

D.

~

d,

D,

~

d,

X

d7

X

D.

~

d.

X

d.

X

D,

~

d,

X

d,

X

E

I

X

da

X

-----"'j

19

20

d"

X

daD

_____'l

d"

X

d7•

X

_____ "'1.

d"

X

d71

X

-----y,

d"

X

d77

X

X

n

CLl

When SHL = GND

______________________________
Y..

~X~

___

d, _ _

______________________________ ___
~x~

da.___

When SHL =Voc

Y,
Y"

______________________________________
________________________________________
Figure 5 Column Driver Timing Chart

776

HITACHI

~x

~

~x

d,

HD66106F
When Used as a Row Driver
The HD66106F shifts the line scan data sent from
the pin E in order at the fall of CL2. When SHL =
Va;, data is shifted from Yl to Yso and Yso to Yl
when SHL = GND.

In both cases, the data delayed for 80 bits by the
shift register is output from the CAR pin to become the line scan data for the next LSI (figure 6).

HD66106F
near GND (figure 7). Each voltage must be within
determines the range within which RoN,
impedance of driver's output, is stable. Note that
~V depends on power supply voltage VLCO-GND
(figure 8) ..

LCD Power Supply

~ V. ~V

This section explains the range of power supply
voltage for driving LCD. VI and V3 voltages
should be near V LCO, and V2 and V 4 should be

-,-------- ~~"

:;.v

L------va

t>vl-, r------------ v.
~

LJ _______________ VI

~~---------------GND

Figure 7 Driver's Output Waveform and Each Level of Voltage

Range of power supply voltage
62

----------------------

2.3 - - - - - - - - - - -

14

37.

V",,-GND (V)

Figure 8 Power Supply Voltage VLCD-GND and

778

HITACHI

~V

HD66106F
Application Example
of 640 x 400 dots driven by HD66106Fs.

Application Diagram
Figure 9 shows an example of an LCD panel

15 D.-D.I---~

••0640
••,.639

j'-- •
CL~ 'i HD66106F (13) CLI _>
v._
\
v.1-..J-

e IoI~VI~

" ilio ",,>,>,ih.

LCD panel
640 x 400 dots
1/400 duty ratio

II

-

It:::..-

I

Controller

r~t~~

-

.r

R.

R.

R,

R.

R•

.~

Notes: 1. R, and R. depend on the LCD panel in use. When using an LCD panel with 1/20 bi_, R,II4R, +
R. ) should be 1120. For example, R, = 3kQ and Rz = 48kQ.
2. Use bypass capacitors to stabilize power supplV when designing a board. It II desirable to UIII two
capacitors with some 0.1 "F per LSI, putting one between VLCD and GND, and the other be_en VCC and GND.

Figure 9 Application Example

HITACHI

779

----

-----------------

g

if J
i

..

Line

It

s

l

~~
t!".e
g 15.
~11>....
....

20

40

160

CL2

aq

~~

CAR(LSI6)

%~
-a

dgo

CAR(LSI7)

5;;

%2.

CAR(LSI8)-.J

-fj

1:1

CAR(LSI 9)..J

t:::I
:! CAR(LSI 10)--.1

§ CAR(LSI 1l)J

~
~
~

;

XXXXX

0.-0 3

CAR(LSI12>J
CAR(LSI 13)J

y,-Y.~

Latches LSI 6 data

Latches LSI 8 data

,

) XXXX

I

Latches LSI 9 data

I

Latches LSI 10 data

I

Latches LSI 11 data

I

I

Latches LSI 12 data

I
Latches LSI 13 data

iii

go
~
It

..
.[ g- ~
.. Horizontal retrace period 1'rg.D:oJg-. .gIi'
o

CLl

~

I

X'

~

I'D

t!".

::s~·i•

,:oJ
I'D

~

~f
e.

::r:
om
m
o
~

m
tzj

HD66106F

~:>

~

~:>

~~IO::

::;;;;::

~


;;::

Figure 11 Timing Waveform for Row Drivers (LSI I-LSI 5)

HITACHI

781

HD66106F
Absolute Maximum Ratings

Supply
Voltage

Item

Symbol

Rating

Unit

Logic circuits

Vee

-0.3 to +7.0

V

LCD driva circuits

V

Not..

VLCD

-0.3 to +38

Input voltage (Logicl

VTl

-0.3 to Vee + 0.3

V

1,2

Input voltage (LCD drivel

VT2

-0.3 to VLCD + 0.3

V

1,3

Operation temperature

Topr

-20 to +75

·C

Tstg

-55 to +125

·C

Storage temperature

Notes: 1. Reference point is GND (= 0 VI.
2. Appli.. to the input pins for logic circuits.
3. Appli.. to the input pins for LCD drive circuits.
4. Using an LSI beyond its maximum rating may r.. ult in its permanent dastruction. LSls should usually be used
under electrical characteristics for normal operations. Exceeding any of these limits may adversely affect reliability.

782

HITACHI

HD66106F
Electrical Characteristics
DC Characteristics (Vee

=S V ± 10 %, VLCD =14 V to 37 V, Ta =_20°C to 7SoC unless otherwise noted)

Itam

Symbol

Input high voltage

V IH

CL1, CL2, M,SHL, 0.8 x Vee-

Pin

Input low voltage

VI!.

00-03, E, CH1

Output high voltage

VOH

CAR

Output low voltage

VOL

Min

Typ

0

Max

Unit

Vcc

V

Tast Condition

0.2 x VCC V

VCC - 0.40.4

V

IOH = -0.4 mA

V

IOl = 0.4 mA

Y1-YaO, V,-V4

3.0

kO

ION = 100 JlA

CL 1, CL2, M, SH L, -5.0

5.0

,.A

VIN = VCC to GNO

50.0
3.0

"A
mA

fCL2 = 6 MHz,

(2) ILCD'
(3) 1ST

0.5

mA

fCL1 = 28 kHz

0.2

mA

At the standby state
fCL2 = 6 MHz,
fCL1 =28 kHz

(4) ICC2

0.2

mA

fCll = 28 kHz,

(5) ILCD2

0.1

mA

fm = 35 Hz

Vi-Yj on resistance

RON
Input leakage current (1) IlL'

Notes

4

00-03, E, CH1
Input leakage current (2) IIL2

V,-V4

-50.0

Current consumption (,) Icc,

VIN = VlCD to GNO

2

3

Notes: 1. Input and output current is excluded. When the input is at the intermediate level in CMOS, excessive current
flows from the power supply through the input circuit. VIH and VIL must be fixed at VCC and GND respectively
to avoid it.
2. Applies when the LSI is used as a column driver.
3. Applies when the LSI is used as a row driver.
4. Indicates the resistance between Y pin and V pin (one of V" V2, V3, and V 4) when it supplies load current to
one of Y,-Yao pins.
Conditions: VlCD - GND = 37 V
V" Va = VlCD - 2/20 (VlCD - GND)
V2' V4 = GND + 2/20 (VlCD - GND)

~

v,----~o

ON

v,-----o
v · - -_ _ _o

Y pin (Y,-Yao)

v. _ _ _ __

HITACHI

783

HD66106F
AC Characteristics (Vee = S V ± 10 %, VLCD = 14 V to 37 V, Ta = _20°(: to +7SoC unless otherwise noted)
Column Driver
Item

Symbol

Pin

Min

Clock cycle time

t cvc

CL2

166

ns

Clock high level width

tCWH

CL2

50

ns

Clock low level width

tCWL

CL2

50

ns

Clock setup time

tscL

CL2

200

ns

tHCL

CL2

200

tct

CL1, CL2

Clock hold time
Clock rise/fall time
Data setup time
Data hold time

Max

Unit

ns

tosu

00-0 3

tOH

00- 0 3

30

ns

50

ns

tESU

E

tOCAR

CAR

M phase difference

tCM

M,CL1

Not.

ns
30

30

Output delay time

E setup time

Typ

ns

80

ns

300

ns

Row Driver
Symbol

Pin

Min

Clock low level width

tWL1

CL2

5

/.IS

Clock high level width

tWH1

CL2

125

ns

Data setup time

tos

E

100

ns

30

Item

Data hold time

tOH

E

Data output delay time

too

CAR

Data output hold time

tOHW

CAR

Clock rise/fall time

tct

CL2

Typ

784

30

O----l--.

HITACHI

/.IS

ns

30

l30

Unit

ns
3

Note: 1. Values when the following load circuit is connected:

Test point

Max

P

F

ns

Notes

HD66106F
Column Driver

CLl

-1

lew.

\~
VI.
..;.V!:;IL_ _ _ _ __

CLZ
to.

0.-0,

Horizontal retrace period
CLI

CL2

M

Figure 12 Controller Interface of Column Driver

HITACHI

785

- - - - - - - - ----_.

HD66106F
Row Driver

CL2

tot

tot

tDS

E

tDR

VIR
VIL

tDD

CAR

VIR
V IL
tDHW

Figure 13 Controller Interface of Row Driver

786

HITACHI

HD66107T-----------(LCD Driver for High Voltage)
Description

Features

The HD66107T is a multi-output, high duty
ratio LCD driver used for large capacity dot
matrix LCD panels. It consists of 160 LCD
drive circuits with a display duty ratio up to
1/480: the seven HD66107Ts can drive a 640 x
480 dots LCD panel. Moreover, the LCD driver
enables interfaces with various LCD controllers due to a built-in automatic generator of
chip enable signals. Use of the HD66107T can
help reduce the cost of an LCD-panel configuration, since it reduces the number of LCD
drivers, compared with use of the HD61104
and HD61105.

•
•
•
•
•
•
•

•
•
•
•

Column and row driver
160 LCD drive circuits
Multiplexing duty ratios: 1/100 to 1/480
4-bit and 8-bit parallel data transfer
Internal automatic chip enable signal
generator
Internal standby mode
Recommended LCD controller LSIs:
HD63645F, HD64645F, and HD64646FS
(LCTC), HD66840/HD66841 (LVIC),
HD66850 (CLINE)
Power supply voltage
-internal logic: +5 V ± 10%
-LCD drive circuit: 14.0 to 37.0 V
Operation frequency: 8.0 MHz (max.)
CMOS Process
192-pin TCP

Ordering Information
Type No.
HD66107T11
HD66107T24
HD66107T12
HD66107TOO
HD66107T01
HD66107T25

Number of

Outer lead

outputs

pitch (pm)

160
160
160
160
80
80

180
180
250
280
280
280

Material of tape*Z Nota
Kapton
Upilex
Kapton
Kapton
Kapton
12 perforated holes
Kapton
8 perforated holes

Note: * 1 "Kapton" is a trademark of Dupont, Ltd.
"Upilex· is a trademark of Ube Industries, Ltd.
*2The details of TCP pattern are shown in "The Information of TCp·.

HITACHI

787

HD66107T
Pin Description
Power Supply

Control Signal

Vee. GND: Vcc supplies power to the internal
logic circuits. GND is the logic and drive
ground.

CLI: The LSI latches data at the negative
edge of CL1 when the LSI is used as a column
driver. Fix to GND when the LSI is used as a
row driver.

VLCD.: VLCD supplies power to the LCD drive
circuit.

CL2: The LSI latches display data at the
negative edge of CL2 when the LSI is used as
a column driver, and shifts line select data at
the negative edge when it is used as a row
driver.

VIL. VIR. V2L. VaR. V3L. V3R. V4L. Va: VI to V4
supply power for driving an LCD (figure 1).

Tablet Pin Function
Pin_

Pin No.
167

Symbol
Vee
GNO

161. 186.187
166.192

VLCD
V1l. R
V2l. R
V3l.R
V4l. R
Cl1
CL2

M
00-07

191.165
188.162
190.164
189.163
183
184
182
174-181

SHl
CH2
BS
TEST
Y1-Y160
E
CAR
CHl

172
171
173
185
1-160
169
168
170

Input/output

Vcc
Ground
VLCD
V1l. V1R
V2l.V2R
V3l. V3R
V4l. V4R
Clock 1
Clock 2
DATAO-DATA7

Input
Input
Input
Input

Shift left
Channel 2
Bus Select
TEST
Y1-Y160
Enable
Carry
Channell

Input
Input
Input
Input
Output
Input
Output
Input

M

:
~-=----V2
----V1

~-r=_.

~

V1, V2: selected level
V3, V4:nonselected level

Figure t

788

Power Supply for Driving an LCD

HITACHI

HD66107T
M: M changes LCD drive outputs to AC.

CAR outputs scan data when the LSI is used
as a row driver (CH1 =GND). When
HD66107Ts are connected in cascade, CAR
connects with E of the next LSI.

Do-D7: Do-D, input display data for the column driver (table 2).
SHL: SHL controls the shift direction of dis-

CHI: CH1 selects the driver function. The chip
devices are columns when CH1 = Vee, and
rows when CH1 = GND.

play data and line select data (figure 2, table
3).

E: E inputs the enable signal when the LSI is

CH2: CH2 selects the number of output data
bits. The number of output data bits is 160
when CH2 = GND, and SO when CH2 = Vee.

used as a column driver (CH1 = Vee).
The LSI is disabled when E is high and enabled when low. E inputs scan data when the
LSI is used as a row driver (CH1 = GND).
When HD66107Ts are connected in cascade,
E connects with CAR of the preceding LSI.

BS: BS selects the number of input data bits.
When BS = Vee, the chip latches S-bits data.
When BS = GND, the chip latches 4-bits data
via Do to D3. Fix D4 through D, to GND.

CAR: CAR outputs the enable signal when
the LSI is used as a column driver (CH1 = V
cc).

Table 2

Table 3
SHL
Vee
GND

wise.

Relation between Display data
and LCD state

Dlllplay Data
1 (=high level)
(=Iow levell

o

TEST: Used for testing. Fixed to GND, other

LCD Output

LCD

V1 L. R/V2L. R
Nonselected level

On
Off

Relation between SHL and Scan Direction of Selected Line (When LSI is Used
as Row Driver)

Shift Direction of Shift Regiatar
E- 1234------ - 160
E- 160- 159- 15S:- 157------ - 1

Scan Direcdon of Selected Line
Y1Y2Y3Y4-------Y160

Y160- Y159- Y15S- Y157 - - - - - --Y1

_

("II

C")-.q- Ln

CQ

....

»»»»

co

"--v--'

"--v--'

"--v--'

lMLiL ___ ~~ F
~n_;JLjf
O

rnJ

01
02
03

02
03

When SHL=GNO

When SHL=Vcc

Figure 2 Relation between SHL and Data Output

HITACHI

789

.... - - _ . _ - - - - - _ . _ - - - -

HD66107T
LCD Drive Interface
Yl-Y180: Each Y outputs one of the four voltage levels-VI. V2. V3. V4-according to the
combination of M and display data (figure 3).

,--.....:o::"'-....JI
o
Youtput levell- V1 .. I-V3 ..

1· v2 .. I· v4 -I

Youtputl

1

1

I

level"V2 • .. V3· .. V1 .... V4 ..
When used as a row driver

When used as a column driver

Figure 3 Selection of LCD Driver Output Level

790

HITACHI

1

IZ'

V2l
V3l
V4l

V'58 V'60
. V'57 V'69

V, V2 V3 V.

!c

V.R
V3R
V2R
V,R

{
B
VLCO

M

E
CH

~

.u ?-El .~I
V..n.,

L';J. ;,.

1 234

.....

LCD drive circuit

1 2 3 4l

0)

0';::::::::-

Vee

GNO

t

II

Latch circuit 2

CQ

~~~~

lBO-bit latch and bidirectional
shift register

CH2
.... co

"''''
~

~

~~~ i:P r---

CAR

SH

l:

~

~

CL2

J

, ,3:'I

CL

1: 2

1

,,~ :.i:~:

B

00,....0

y

Ii

Logic

)I Logic

lb~r1

4

Latch circuit 1

"I}

LJL

I
(4-bit x 40)
(S-bit x 20)

.... co en

~I

~~~~

t

II

ii
I
I

Selector

'--

TEST -'-

Teat
circuit
'--

Controller

I

s
C»
C»
~

o
~

.....:J
~

HD66107T
Function
LCD Drive Circuits
The LCD drive circuits generate four levels of
voltages-VI, V2, V3, and V4-for driving an LCD.
They select and transfer one of the four levels
to the output circuit according to the combination of M and the data in the latch circuit 2 ..

Latch Circuit 2
Latch circuit 2 is used as a l60-bit latch circuit during column driving. Latch circuit 2
latches data input from latch circuit 1 at the
falling edge of CLl and outputs latched data
to the drive circuits.
In the case of row driving, latch circuit 2 is
used as a l60-bit bidirectional shift register.
Data input from E is shifted at the falling
edge of CL2. When SHL = Vec, data is shifted
in input order from bit 1 to bit 160 of the shift
register. When SHL = GND, data is shifted
from bit 160 to bit 1 of the reister. Moreover,
this latch circuit can be used as an 80-bit shift
register. In this case, Y41 through YI20 are
enabled, while the other bits remain unchanged.

column driving. The selector signals specify
which 8-biJ: circuit latches data. Moreover,
this circuit can be used as forty 4-bit parallel
data latch circuits by switching BS, in whieh
case the circuit latches data Do through D3.
Moreover, this latch circuit can be used as an
80-bit shift register. In this case Y41 through
YI20 are enabled, while the other bits remain
unchanged.

Selector
The selector consists of a 6-bit up and down
counter and a decoder. During column driving it generates a latch signal for latch circuit
1, incrementing the counter at the falling
edge of CL2.

Controller
This controller is enabled during column
driving. It provides a power-down function
which detects completion of data latch and
stops LSI operations.
Moreover, the controller automatically generates a chip enable signal (CAR) which
starts next-stage data latching.

Latch Circuit 1
Test Circuit
Latch circuit 1 consists of twenty 8-bit parallel data latch circuits. It latches data Do
through D7 at the falling edge of CL2 during

792

The test circuit divides the external clock and
generates test signals.

HITACHI

HD66107T
Fundamental Operations
nected with E of the next-stage LSI, this nextstage LSI is activated when CAR of the previous LSI goes low.

Column Driving (1)
• CH2 = GND (160-bit data output mode)
. BS = Vee (a-bit data latch mode)
The HD66107T starts data latch when E is at
low level. In this case, a-bit parallel data is
latched at the falling edge of CL2. When 160bit data latch is completed, the HD66107T
automatically stops and enters standby mode
and CAR is goes to low level. If CAR is con-

1

2

3

E\'--_____

Data is output at the falling edge of CL1.
When SHL = GND, data dl is output to pin Yl
and d160 to Y160. On the other hand, when SHL
= Vee, data d160 is output to pin Yl and dl to
Y160. The output level is selected from among
Vl-V4 according to the combination of display
data and alternating signal M. See figure 4.

19

20

---------------------

DO~---------~------

\ ~~~~~~~~~~~~~~~~------

D7~ _________ ~ ____________

___________~r_\'_____

ell

,\. .-__-----Ir-

CAR ----------------SHl

= GND

v, ________________________________________________________~

y,l--------------------------------------------------------~
SHl

= Vee

v, ______________________________________________________~~

\

V,ro ________________________________________________________~

Figure 4 Column Driver Timing Chart (1)

HITACHI

793

HD66107T
Column Driving (2)
. CH2 = GND (lSO-bit data output mode)
. BS = GND (4-bit data latch mode)

4-bit display data (Do-D3) is latched at the
falling edge of CL2. Other operations are
performed in the same way as described in
"Column Driving (1)". See figure 5 .

C~ ~ _________ ~ ___ _
E,

1

2

3

39

40

41

______________________

Cll
CAR - - - - - - - - -

_______~r_l~___

,'--___r--

SHl = GND

y1 __________________________________________ ~

J-------------~
SHl = Vee
y1 ______________________________________________~~

j-------------~
Figure 5 Column Driver Timing Chart (2)

794

HITACHI

HD66107T
Column Driving (3)

Yt through Y40 and Y121 through Yl60 remain
unchanged .

• CH2 = Vee (SO-bit data output mode)
• BS = Vee (S-bit data latch mode)
When CH2 is high (Vee). the HD66107T can be
used as an SO-bit column driver. In this case.
Y41 through Y120 are enabled. the states of

CU

When SHL = GND. data dl is output to pin
Y41 and dso is output to Y120. Conversely. when
SHL = Vee. data dso is output to Y41 and dl is
output to Y120. See figure 6.

~ _________ ~ ____ _

E\1

2

3

9

10

11

i~~~~~~~~~~~~~~===---

D7~ _________ ~ ____ _

-Inl.-__

CLl _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

CAR

------

--'r-

,'--_ _ _

SHL= GND

y41 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

~

yl~ _____________________________________~~

SHL = Vee
y41 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

\

Y120 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

Figure 6 Column DrIver Timing Chart (3)

HITACHI

795

HD66107T
Column Driving (4)
• CH2 = Vcc (SO-bit data output mode)
. BS = GND (4-bit data latch mode)

CL2

When CH2 = Vcc and BS = GND, 4-bit parallel data is latched, while SO-bit data is output.
The output of latched data is performed in
described in "Column Driving (3)". See figure
7.

~ _________

JL5"UL ________
19

123

E\'-_____

CLl
CAR - - - - - - - - -

20

21

-----------------------

____________--'n'-__
\'--_____r-

SHL=GND

y41 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

y,~--------------------~
SHL=Vcc

T--------------~
y,20 ___________________________________________________~

Figure 7 Column Driver Timing Chart (4)

796

HITACHI

HD66107T
Row Driving (1)
. CH2 = GND (160-bit data output mode)
The HD66107T shifts line scan data input
through E at the falling edge of CL2.

When SHL = Vee. 160-bit data is shifted from
YI to Y160. whereas when SHL = GND. data is
shifted from YI60 to YI. In both cases the
HD66107T outputs the data delayed for 160
bits by the shift register through CAR.
becoming line scan data for the next IC
driver. See figure 8.

(next stage)

SHL=Vcc

2

4

3

158

159

160

158

159

160

1

CL2

~~_____________

V1

II

V2

~

~

V 160

-----------------------

SHL=GND

(next stage)

2

3

4

1

CL2

~-----------------------------------------V160

V159

V1

CAR

11. . . ______
~L_ _ _ __

--------------------------------------------

.___-----JIL

Figure 8 Row Driver Timing Chart (1)

HITACHI

797

HD66107T
Row Driving (2)
. CH2

= Vcc (80-bit data output mode)

When CH2 is high. the HD66107T can be used
as an 80-bit row driver. In this case. Y41 to
Y120 are enabled. while the other bits remain
unchanged.

Line scan data input through E is shifted at
the falling edge of CL2. When SHL = Vcc.
data is shifted from Y41 to Y120. Conversely•
when SHL = GND, data is shifted from Y120 to
Y41. In both cases the HD66107T outputs the
data delayed for 80 bits by the shift register
through CAR. becoming line scan data for the
next LSI. See figure 9.

~

....

~

~~.;
~
_ 1».... 'CI

lil"'
S.S·s
n
O

CQ ....

~.

S-~CQ

Jmm

controller

~~

~21{g:~mI2Q ~
V3
V.
CLl
CL2
M

Cll

~;""
~
"'!11

C

HD66l07T
ICIl)

0 0 -0,

mt

HD66l07T
ICI3)

~
n
:I

-

+37V~

i'

-.Jl»fIl

~I»

-<

- - - -____ u

_OJ

icam3992'2'
com400 ;s: ;s:

v~eii)i

{)
Yl-Yl60

'1-'160

SHl. TEST. CH2
I- CH1. as
_
HD66l07T _
~ ~LCD
ICI4)
CARI---

tl_N~.::;::J
Vee
GNO

...

~

0

»»uu~c

"',Jl

TTl

~fIl

~~
Po ...

I
~h)

Ia

Rl

~~

r--

~

Rl

~mtT

LCD panel
400 x 640 dots
1/400 duty ratio

Vee

Rl
Rl.
R2

::s

S·

,om 2

{

g

:I

com 1

nl~

CL2

00-:

CD§:CD
:z:tI . e!~
m
i3
m .... ~
b~ CD

-

a0-

SHl. TEST. CH2
CH1. as
_
HD66l01T_
~LCa
ICI5)
CAR

B ~_N~.::;::J

Vee"
GND
0
, » » oulEc

9

n

Vre~
L

~8

t"'o
no

til;'

Yl-V l60

d

SHl. TEST. CH2
CH1. as
_
HD66l01T
~LCD
Icm
CAR

90
~-N~.::;::J
»» uu:Eo
Vee"
GND

111\

II

Notes 1. Rl and R2 are specified depending on the type of LCD panel. When using an LCD panel with 1/20 bias. Rl/(4Rl + R2)
must be 1/20. i.e .• Rl = 3kO and R2 = 48kQ.
Notes 2. When designing a board. place capacitors close to each LSI in order to stabilize power supply. It is recommended to use
two 0.1 /IF capacitors per LSI; one is connected between Vcc and GND. and the other between VLCD and GND.

s
0)
0)
~

~

o
Figure 10 Application Example

....:J
~

HD66107T
Waveform Examples
Column Driving

....

C
I

8
Figure 11 Column Driver Timing Chart
800

HITACHI

HD66107T
Row Driving

<0

0

~

Q)

E

e

IL

en
~

co
~

§
I

-

§

I
I

I

~

u

Iw

:;

I

-> ->

I

I
I
I

I

I

I
I

I
I

I
I

» -> »>

I

I
I
I

I
I

I
I

I

I~
~

fi
!::!

I

I

-

I
CO)

.,

N

> > > >
.,:

Figure 12 Row Driver Timing Chart

HITACHI

801

HD66107T
Absolute Maximum Rating
Item
Power supply voltage

Logic circuit
LCD drive circuit

Input voltage (1)

Symbol
Vcc
VLCO

Rating

Unit

Note

-0.3-+7.0
-0.3-+38

1

Vn

-0.3-Vcc+0.3
-0.3-VLCO+ 0 .3
-20-+75
-40-+125

V
V
V

Input voltage (2)
Operation temperature
Storage temperature

Top.
Tstg

v

1,2
1,3

·C
·C

No1es:1. Reference point is GND (= OV).

2. Applies to input pins for logic circuit.
3. Applies to input pins for LCD drive circuits.
4. If the LSI is used beyond absolute maximum ratings, it may be permanently damaged. It
should always be used within the above electrical characteristics to prevent malfunction or
degradation of the LSI's reliability.

802

HITACHI

HD66107T
Electrical Characteristics
DC Characteristics (Vee
Item
Input high voltage
Input low voltage
Output high voltage

=SV

± 10%, VLCD

Symbol Pin.
CL1, CL2, M
VIH
SHL, BS, CH2,
TEST, 00-07,
VIL
E, CH1
CAR
VOH

Output low voltage

VOL

Vi - Yj on resistance

RON

Input leak current (1 )

IlL,

Input leak current (2)

11L2

= 14 to 37 V, Ta = -20 to 7S"C)

Min.
0.8 x Vcc

Vcc

Max.

0

0.2 x Vcc V

Note

Condition

V

IOH=-0.4 mA

0.4

V

IOL=0.4 mA

3.0

kO

ION= 150 p.A

5.0

p.A

VIN=Vcc-GNO

Vcc-0.4

Y1-Y160,
V1-V4
CL1, CL2, M
-5.0
SHL, BS, CH2,
TEST, 00-07,
E, CH1
V1-V4
-100

Unit
V

4

100

p.A

VIN=VLCO-GND

Icc,

5.0

mA

fCL2=8 MHz

1

Power dissipation (2)

ILco,

2.0

mA

2

Power dissipation (3)

1ST

0.5

mA

fCL1 =28 kHz
In standby
mode:
fCL2=8 MHz,
fCl' =28 kHz
ffcL1 = 28 kHz
fm=35 Hz

Power dissipation (1)

Power dissipation (4)
Power dissipation (5)

IeC2
ILco2

1.0

mA

0.5

mA

1
2
3

Notes: 1. Input and output current is excluded. When an input is at the intermediate level is CMOS,
excessive current flows from the power supply though the input circuit. To avoid it, VIH and
VIL must be fixed to Vcc and GND respectively.
2. Applies to column driving.
3. Applies to row driving.
4. Indicates the resistance between one pin from Y 1-Y160 and another pin from V1-V4 when
load current is applied to the Y Pin; defined under the following conditions.
VLco-GND=370
V1, V3=VLCO- {2/20(VLco-GND)}
V2, V4=VLCO+ {2/20(VLco-GND)}
This section explains the range of power supply voltage for driving LCD. V 1 and V3 voltage
should be near VLCO, and V2 and V4 should be near GND (figure 13).
Each voltage must be within t::.V. t::.V determines the range within which RoN, impedance of
driver's output, is stable. Note thatt::.V depends on power supply voltage VLco-GND (figure
14).

iT------- t~"
L------ V3

I!.V

Range of power supply voltage

!

I!.V - ,

r------------ v ,

14

L-J _______________ VI
GND

Figure 13 Driver's Output Waveform
and Each Level of Voltage

37.

V",,-GND (V)

Figure 14 Power Supply Voltage
VLCD-GND and d V

HITACHI

803

HD66107T
AC Characteristics (Vcc = 5 V ± 10%, VLCD = 14 to 37 V, Ta = -20 to 75'C)

Column Driving
Symbol

Pin name

Min.

Clock cycle time

tcvc

Cl2

125

ns

Clock high-level width (1)

tCWHl

CL2

30

ns

Clock high-level width (2)

tCWH2

Cl1

60

ns

Clock low-level width

tCWL

Cl2

30

ns

Clock setup time

tsCL

CL2

200

ns

Clock hold time

tHCL
tet

CL2

200

ns

CL1. Cl2

tosu

00-07

30

ns
ns

tOH

30

ns

tE5U

00-07
E

25

tOCARl

CAR

70

ns

tOCAR2

CAR

200

ns

tcM

M. CL1

300

ns

Item

Clock rising/falling time
Data setup time
Data hold time
E setup time
Output delay time (1)
Output delay time (2)
M phase difference

Max.

30

ns

Notes:1. Specified when connecting the load circuit shown in figure 15.

Test point

O----i'

30 pF

Figure 15 Test Circuit

804

HITACHI

Unit

Note

HD66107T

I..J~'~~t------,::==--

Cll _ _ _ _ _ _ _

CL2

DO_7

Cll

CL2

CAR ______________

~-JI

M

Figure 16 Controller Interface of Column Driver

HITACHI

805

HD66107T
Row DrlvlDg
ltam

Symbol

Pin nama

Clock low-level width

lWLl

CL2

Clock high-level width

lWHl

CL2

Data setup time

toS2

E

Data hold time

tOH2

E

Data output delay time

too

CAR

Data output hold time

toHW

CAR

Clock rising/falling time

let

CL2

Min.
5
60
100
30

Max.

ns

ns
ns

3
30

__--+----J

CAR
Output data

0.85 x Vee
0. 15xVee

----1-----'

Figure 17 ControUer Interface of Row Driver

806

HITACHI

pS

ns

30

eL2

Input data

Unit
pS

ns

Note

HD66110RT
(Column Driver)
Description

Features

The HD661l0RT, the column driver for a large
liquid crystal display (LCD) panel, features as
many as 160 LCD outputs powered by 160
internal LCD drive circuits, and a high duty cycle.
This device can interface to various LCD
controllers by using an internal automatic chip
enable signal generator. Its strip shape enables a
slim tape carrier package (TCP).

•
•
•
•

•
•
•
•

191-pin TCP
CMOS fabrication process
High voltage
- LCD drive: 28 to 40 V
High speed
- Maximum clock speed :
12 MHz (Vee = 4.5 to 5.5 V)
10 MHz (Vee = 2.7 to 5.5 V)
4- and 8-bit data bus interface
Display off function
Standby function
Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD66850

Ordering Information
Type No.

Outer lead pHch(f.Lm)

User Area (mm)

HD66110RTA8

140

10.85

HD66110RTBO
HD66110RTB1

92
92

9.0

HD66110TA4

80

9.66

Note:

11.9

The details of TCP pattern are shown in • The Information of TCP.•

HITACHI

807

i

....1:1

."
Z

s~

Y1
Y2

=t

CD

a

-I

0

:I

~
0

:I:

~

S
::I"

1:1

va

V4l
V3I..
V1L
VLco1
GNO
'TEST!!

I&~
01S~

811

0

m

en

D6

CD
~

-I
"'C

::I"

ien

III

CiJ

Vee
07
OS

D4

D3
D2

01
DO
V1R
V3R

!!.
en

VLCD2

"8en

Y160

0

en
B'
~

1:1

51fD

'2sa.°
3
"2-

0;

IJQ
fD

(ji0
(ji0

III
::I
CD
)(
III

.,.,>

~

191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161

"

°°1°°

Y159
Y160

=

10
~
~

"""'

"""'

~

HD66110RT
Pin Description
Input/Output

Classification

Symbol

Pin No.

Pin Name

Vee

175

Vee

GND

186

GND

VlCD1

187

VlCD1

Input

VlCD2

164

V1R

166

VlCD2
V1R

Input

V2R

162

V2R

Input

Power supply

V3R

165

V3R

Input

Power supply

V4R

163

V4R

Input

Power supply

V1L

188

V1L

Input

Power supply

V2L

191

V2L

Input

Power supply

V3L

189

V3L

Input

Power supply

Power supply
Power supply
Power supply
Power supply
Power supply

V4L

190

V4L

Input

Power supply

CL1

179

Clock 1

Input

Control signal

CL2

178

Clock 2

Input

Control signal

M

180

M

Input

Control signal

00-0 7

167-174

Data O-~ V3 >~ V2 >~ V4 ~

Figure 3 Selection of LCD Drive Output Level

812

HITACHI

HD66110RT
Block Functions

Latch Circuit 1
160-bit latch circuit I latches 4-bit or 8-bit parallel
data input via the Do to D7 pins at the timing
generated by the shift register.

LCD Drive Circuit
The 160-bit LCD drive circuit generates four
voltage levels VI, V2, V3, and V4, for driving an
LCD panel. One of the four levels is output to the
corresponding Y pin, depending on a combination
of the M signal and the data in the latch circuit 2.

Shift Register
The 4O-bit shift register generates and outputs data
latch signals for latch circuit I at the falling edge
of each clock 2 (CL2) pulse.

Level Shifter
Data Shifter
The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.

The data shifter shifts the destinations of display
data output, when necessary.

Latch Circuit 2
Test Circuit
160-bit latch circuit 2 latches data input from latch
circuit I, and outputs the latched data to the level
shifter, both at the falling edge of each clock I
(CLI) pulse.

The test circuit divides the external clock pulses
and generates test signals (lESTl and TEST2).

Block Diagram
Y1-Y160

V1R-V4L

M _ _ _ _ _ _-:.J"
VLCD1,
VLCD2--->
Vcc--->
GND--->
CL1

SHIL-------~----~Lr--~------~S~h~~~~9~iS~m~r------~--~JIT..

j"".1

C~!--------------~--~------------------~--~

lESTf,
TEm"

HITACHI

813

HD66110RT
Comparison of the HD66110RT with the HD66107T
Hem

HD66110RT

Common LCD drive circuits

Not provided

160

Column LCD drive circuits

160

160 or 80

LCD drive voltage range

28 to 40 V

14to 37 V

Speed

12 MHz

8 MHz

Vee - 4.5 to 5.5 V

HD66107T

10MHz

Vee - 2.7 to 4.5 V
Clock hold time (tHCL> definition

From the falling edge of CL 1 to
the rising edge of CL2 (figure 1)

From the falling edge of CL 1 to
the falling edge of CL2 (figure 1)

Test pin level at normal operation

Vee

GND

Display off function

Provided

Not provided

TCPshape

Can be thin

Cannot be thin

CL1

~}---:-"'"-::---­

CL2~
HD66110RT

CL1
CL2

HD66107T

Figure 4 tHCL Definitions of the HD661l0RT and HD66107T

814

HITACHI

HD66110RT
Operation Timing
4-Blt Bus Mode (BS = GND)

Figure 5 shows 4-bit data latch timing when SIR..
= GND, that is, the EIIOI pin is a chip enable
input and El/02l!!!l!..a chip enable output When
SIR.. = Vee, the EI/Ol pin is a chip enable output

It simultaneously latches 4 bits of data at the
falling edge of each CL2 pulse. When it has
latched 156 bits of data, it sets the EII02 signal
low. When it has latched 160 bi~ of data, it
automatically stops and enters standby state,
initiating the next HD66110RT, as long as its
EI/02 pin is connected to the EI/O 1 pin of the next

HD66110RT.

and EII02 pin is a chip enable input
When a low chip enable signal is input via the
EI/Ol pin, the HD66110RT is first released from
data standby state, and, at the falling edge of the
following CL2 pulse, it is released entirely from
. standby state and starts latching data.

The HD6611OR'IS output one line of data from the
YI-YI60 pins at the falling edge of each CLI
pulse. Data dl is output from Y I , and dl60 from
Y 160 when SIR.. = GND, and d l is output from
Y160, and d l60 from YI when SIR.. Vce.

HITACHI

=

815

HD66110RT
1 line

CL2

DO
03
CL1

Eii52
HD66110RT

(No.1

no.

1

latches data
EII02
(No.2)

HD66110RT no. 2

latches data
EII02
(No.3

HD66110RT no. 3

latches data

Eii52
(No.4)

HD66110RT

no. 4

latches data
Y1-Y160 __

Note:

~~

__________________________________________

SHL • GND

Figure 5 4·Bit Data Latch Timing (SHL = GND)

816

HITACHI

~,~_

HD66110RT
When SHL = Vce. the EJ70l pin is a chip enable
output and EI/02 pin is a chip enable input

8·Bit Bus Mode (BS = VCC)
Figure 6 shows 8-bit data latch timing when SHL
= GND. that is. the EI/OI pin is a chip enable
input and EI/02 pin is a chip enable output

The operation is the same as that in 4-bit bus mode
except that 8 bits of data are latched
simultaneously.

11109

CL2

DO

~
I

- Q - O20i
-O21O - 1
221 ,

•••-•••'

~

,
I

I
I
I

I
I
I

I
I
I

I

I

I

I

II

I

I

I

~

~.-.-,=xmx=

.~

:xbkx=---- ~
~

i

07

I

I

II

!I

CL1

I
I

Eii62
HD66110RTno.1
latches data

(No.1)

EV02
(No.2)

I
I

HD66110RT no. 2
latches data

Eii62 ----I
(No.3)

Eii62
(No.4)

Y1-Y160

•

I

I>

I

r-

31 ~I'
l~i________________________~la~tc~he~S~da~ta~~~_
I
---Ji
~<~1=~----~Ir--I:
HD66110RT no.

I

----J

I

HD66110RTno.4
latches data

~~~----------------------------------------------------t=

I

Note:

I

!

I

SHL • GND

Figure 6 8-Bit Data Latch Tuning (SHL

HITACHI

=GND)

817

HD66110RT
Application Example

III
Notes:

1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1120 bias, R1 and R2 must be 3 kn and 48 kn, respectively. That
is, R1/(4 • R1 + R2) should be 1120.
2. To stabilize the power supply, place two 0.1-fJ.F capacitors near each LCD driver: one
between the Voo and GND pins, and the other between the VLCD and GND pins.
3. The load must be less than 30 pF between the EII02 and EII01 connections of
HD66110RTs.

818

HITACHI

HD66110RT
Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Notes

Power supply voltage for logic circuits

Vcc

-0.3 to +7.0

V

1,5

Power supply voltage for LCD drive circuits

VLco

-0.3 to +42

V

1,2,5

Input voltage 1

VT1

-0.3 to Vcc + 0.3

V

1,3

Input voltage 2

VT2

-0.3 to VLCO + 0.3

V

1,4

Operating temperature

Topr

-20 to +75

·C

Storage temperature

TSla

-40 to +125

·C

Notes:

1. The reference point is GND (0 V).
2. Indicates the voltage between GND and VLCO.
3. Applies to input pins for logic circuits, that is, control signal pins.
4. Applies to input pins for LCD drive level voltages, that is, V1-V4 pins.
5. Power should be applied to Vcc-GND first, and then VLco-GND. It should be disconnected in
the reverse order.
S. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.

Electrical Characteristics
DC Characteristicsl (Vcc

= 2.7

to 4.5V, VLCD - GND

= 28

to 40 V, and Ta

= -20 to

+75°C, unless

otherwise noted.)
Hem

Symbol

Pins

Min.

Max.

Input high voltage

VIH

1

0.8 xVcc

Vcc

V

Input low voltage

VIL

1

0

0.2 xVcc

V

Output high voltage

Vcc -0.4

VOH

2

Output low voltage

VOL

2

Vi-Yj on resistance

0.4

RON

3

Input leakage current 1

liLt

1

-5.0

Input leakage current 2

IIL2

4

-100

Current consumption 1

Icc

Unit

Condition

V

IOH= -0.4 mA

V

IOL ",0.4 mA

3.0

kG

ION '" 150 j.iA

5.0

J.l.A

VIN - Vcc to GND

100

J.l.A

V IN ", VLCO to GND

2.2

mA

fCL2 =10 MHz
fcLt '" 28 kHz

Notes

2

~66-30~

Current consumetion 2

QUrI!mt ~!l~urnRtiQ!l 3

1":0
llii

3.0

03

mA

Same as above

2

rnA

Same a~ abolle

23

Pins and notes on next page.

HITACHI

819

HD66110RT
DC Characteristics2 (Vee = 5 V ± 10%, VLCD - GND = 28 to 40 V, and T. = -20 to +7SoC, unless
otherwise noted.)
Item

Symbol

Max.

Unit

Input high voltage

VIH

0.8 x VCC

VCC

V

Input low voltage

VIL

o

0.2xVcC

Output high voltage

VOH

Output low voltage

Pins

2

Min.

Vee- 0.4

VOL

2

0.4

RON

3

3.0

Input leakage current 1

111l

Notes

V

V

IoH ... -0.4 mA
Iot. ... 0.4 mA

VIN .. VLCD to GND

V

Vi-Yj on resistance

Condition

-5.0

5.0

-100

100

IlA
IlA

Icc

5.0

mA

fCL2'" 12 MHz
fcll '" 28 kHz

2

Current consumption 2

ILCD

3.0

mA

Same as above

2

Current consumption 3

1ST

0.7

mA

Same as above

2, 3

Input leakage current 2

IIL2

Current consumption 1

Pins:

4

1. CL 1, Cl2, M, SHL, BS, 1:17Of, E1102,
~ TErn, iEm, DO~7

2. "ETi01,"E1702
3. Y1-Y160, V1-V4
4. V1-V4
Notes:

1. Indicates the resistance between one
pin from Y1-Y160 and another pin from
V1-V4 when load current is applied to
the Y pin; defined under the following
conditions.
VLCD-GND
V1, V3

=40 V

= VLCD -{1/20(VLCD -GND)}

V2, V4 = VLCD + {1/20(VLCD - GND)}

820

HITACHI

VIN - Vee to GND

V1 and V3 should be near VLCD level,
and V2 and V4 should be near GND
level (figure 7). All voltage must be
within IN. !N is the range within
which RON, the LCD drive circuits'
output impedance, is stable. Note that
~ V depends on power supply voltage
VLCD - GND (figure 8).
2. Input and output current is excluded.
When a CMOS input is floating,
excess current flows from the power
supply through the input circuit. To
avoid this, VIH and VIL must be held to
Vee and GND levels, respectively.
3. Applies to standby mode.

HD66110RT

. . . . ----==-=-=-=--":":"V1'VLCD
llV

V3

llV

--------. V4

~---=----------------V~2GND

Figure 7 Relation between Driver Output Waveform and Level Voltages

llV (V)

6.21--·---·----------~

4.0

Level voltage range

28

40

VLCD-GND (V)
Figure 8 Relation between VLCD - GND and llV

HITACHI

821

HD66110RT

=

AC Characteristics1 (Vee 1.7 t04.5V, VLCO -GND
otherwise noted.)
Item

Symbol

Pins

Clock cycle time

=28 to 40 V, and T. =-20 to +7SoC, unless
Min.

Max.

Unit

tCYC

CL2

100

ns

Clock high-level width 1

tCWH2

CL2

37

ns

Clock low-level width

Notes

tCWL2

CL2

37

ns

Clock high-level width 2

tCWHl

CL1

50

ns

Clock setup time

tSCl

CL1. CL2

100

ns

Clock hold time

tHCl

CL1. CL2

100

ns

Clock rise time

tr

CL1. CL2

50

ns

2

Clock fall time

t,

CL1. CL2

50

ns

2

Oata setup time

tos

0 0-07• CL2

35

ns

Oata hold time

tOH

00-07. CL2

35

ns

M phase difference time

tCM

M.CL1

300

ns

Notes: 1. The load must be less than 30 pF between the E 1102 and EI/01 connections of H06611 ORTs.
2. tr• t, < (tcyc-tcWH2-tcWl2) I 2 and t r• t, S SOns

AC Characteristics1 (Vee
otherwise noted.)
Item

=5 V ± 10%, VLCO - GND =18 to 40 V, and T. =-10 to +7SOC, unless
Max.

Symbol

Pins

Min.

Clock cycle time

tCYC

CL2

83

ns

Unit

Clock high-level width 1

tCWH2

CL2

20

ns

Clock low-level width

tcWL2

CL2

20

ns

Clock high-level width 2

tCWHl

CL1

50

ns

Clock setup time

tSCl

CL1. CL2

100

ns

Clock hold time

100

tHCl

CL1. CL2

Clock rise time

tr

CL1. CL2

Clock fall time

t,

CL1. CL2

Oata setup time

tos

0 0-07• CL2

10

Oata hold time

tOH

0 0-07• CL2

10

tCM

M. CL1

M phase difference time

Notes

ns
50

ns

2

50

ns

2

ns
ns
300

ns

Notes: 1. The load must be less than 30 pF between the EII02 and EII01 connections of H066110RTs.
2.

822

tr. t, < (tcyc-tCWH2-tcWl2) I 2 and t r• t, S SOns

HITACHI

HD6611 ORT
tr

tCWH2

tf

tCYC

tCWL2

CL2
tOH

00-07

o.avec
O.2Vec

CL1

CL2

o.avec
O.2Vec

M

tCM

Figure 9 LCD Controller Interrace Timing

HITACHI

823

,HD66115T-----(160-Channel Common Driver Packaged
in a Slim Tape Carrier Package) - PreliminaryDescription

Features

The HD66115T is a common driver for large dot
matrix liquid crystal graphics displays. It features
160 channels which can be divided into two groups
of 80 channels by selecting data input/output pins.
The driver is powered by about 3 V. making it suitable for the design of portable equipment which
fully utilizes the low power dissipation of liquid
crystal elements. The HD66115T. packaged in a
slim tape carrier package (slim-TCP). makes it
possible to reduce the size of the user area (wiring
area).

•
•
•
•
•
•
•
•

Duty cycle: About 1/100 to 1/480
160 LCD drive circuits
High LCD driving voltage: 14 V to 40 V
Output division function (2 x 8O-channel
outputs)
Display off function
Operating voltage: 2.5 V to 5.5 V
Slim-TCP
Low output impedance: 0.5 ill (typ)

Ordering Information
'lYpeNo.

Outer Lead Pitch (J.lI11)

HD66115TAO

180

HD66115TA1

250

Note: The details of TCP pattern are shown in "The Information of TCP.·

824

HITACHI

HD66115T
Pin Arrangement

Top view

Note: This figure does not specify the tape carrier package dimensions.

Pin Assignments
..:I

N

:>

..:I

LO

:>

..:I

\D

:>

..:I

.....

:>

.....0

u

...:I

:>

.....

~

::r:

()

..:I

::r:
CI)



IX:
.....

:>

IX:

\D

:>

N

0

u

...:I

:>

IX:

LO

:>

IX:

N

:>

-M

Cl
I

181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161

HITACHI

825

HD66115T
Pin Descriptions
Symbol

Pin No.

Pin Name

Input/Output

Classification

VLCo1,2

177,163

VLCO

Power supply

Vee
GND1,2

'166

Power supply

176.170

VCC
GND

V1L, V1R

165.178

V1L, V1R

Input

Power supply

V2L. V2R

161.181

V2L. V2R

Input

Power supply

VsL, VsR

162. 180

VsL. VsR

Input

Power supply

V6L, V6R

164.179

V6L. V6R

Input

Power supply

CL

171

Clock

Input

Control signal

M

172

M

Input

Control signal

CH

175

CH

Input

Control signal

SHL

174

Shift left

Input

Control signal

Power supply

0101

169

Data

Input/output

Control signal

0102

167

Data

Input/output

Control signal

01

168

Data

Input

Control signal

Dispoff

173

Display off

Input

Control signal

X1-X160

1-160

X1-X160

Output

LCD drive output

826

HITACHI

HD66115T
Pin Functions
Power Supply

Vee, GND: Supply power to the internal logic
circuits.
VLCD' GND: Supply power to the LCD drive circuits (figure 1).

VIL, VIR, VzL, VzR, VsL, VsR, V6L, V6R:
Supply different power levels to drive the LCD. VI
and Vz are selected levels, and Vs and V6 are nonselected levels.
Control Signals

SHL: Selects the data shift direction for the shift
register and .the common signal scan direction
(figure 2).

DIOl, DI02: Input or output data. DIOI is input
and DI02 is output when SHL is high. DIOI is
output and DI02 is input when SHL is low.
DI: Input data. DI is input to XSI-XI60 when CH
and SHL are high, and to XSI-Xl when SHL is
low.
Dispoff: Controls LCD output level. A low Dispoff
sets the LCD drive outputs XI-Xl60 to the Vz
level. A high Dispoff is normally used.

CL: Inputs data shift clock pulses for the shift
register. At the falling edge of each CL pulse, the
shift register shifts data input via the DIO pins.

LCD Drive Outputs

M: Changes the LCD drive outputs to AC.

XI-X160: Each X outputs one of four voltage
levels VI> Vz. VS. or V6, depending on the combination of the M signal and the data level (figure 3).

CH: Selects the data shift mode. (CH = high: 2 x
SO-output mode, CH =low: 160-output mode)

HITACHI

827

HD66UST

1T
Figure 1 Power Supply for LCD Driver

SHL

Data shift direction

High

Shift to right
0101 -+ SR1 -+ SR2 -+ SR3 ••• -+ SR160 -+ 0102

Low

Shift to left
0102 -+ SR160 -+ SR159··· -+ SR1 -+ 0101

Note: SR1 to SR160 correspond to the outputs of X1 to X160, respectively.

Figure 2 Selection of Data Shift Direction and Common Signal Scan Direction by SHL

M

o
X output level

I. V2.1. V6.1. V1.1 .. V5.1

Figure 3 Selection or LCD Drive Output Level

828

. HITACHI

HD66115T
Block Diagram

X1-X160

Vcc

Oispoff
CL

GN01,2

VLco1,2

0102

0101

HITACHI

829

HD66115T
Block Functions
LCD Drive Circuit

Shift Register

The 160-bit LCD drive circuit generates four
voltage levels V 1. V2. V5. and V6. which drive the
LCD pane\. One of these four levels is output to
the corresponding X pin. depending on the combination of the M signal and the data in the shift
register.

The 160-bit shift register shifts the data input via
the DIO pin by one bit at a time. The one bit of
shifted-out data is output from the DIO pin to the
next driver IC. Both actions occur simultaneously
at the falling edge of each shift clock (CL) pulse.
The SHL pin selects the data shift direction.

Level Shifter
The level shifter changes logic control signals
(2.5 V-5.5 V) into high-voltage signals for the
LCD drive circuit.

830

HITACHI

HD66115T
Absolute Maximum Ratings
Hem

Symbol

Rating

Unit

Notes

Vcc
VLCD

-0.3 to +7.0

V

1,5

-0.3 to +42

V

1,5

Vn

-0.3 to Vee + 0.3

V

1,2

Input voltage 2

VT2

-0.3 to VLCD + 0.3

V

1,3

Input voltage 3

VT3

-0.3 to +7.0

V

1,4

Operating temperature

Topr

-20 to +75

°C

Storage temperature

Tsto

-40 to +125

°C

Power supply voltage for logic circuits
Power supply voltage for LCD drive circuits
Input voltage 1

Notes: 1.
2.
3.
4.
5.

The reference point is GND (0 V).
Applies to pins CL. M, SHL, 01, Dispolf, and CH.
Applies to pins V1 and Va.
Applies to pins V2 and Vs.
Power should be applied to Vcc-GND first, and then VLco-GND. It should be disconnected in
the reverse order.
S. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged.
It should always be used within its specified operating range in order to prevent malfunctions or
loss of reliability.

HITACHI

831

HD66115T
Electrical Characteristics
DC Characteristics (Vee =2.5 V to 5.5 V, GND =0 V, and Ta =-20°C to +75°C, unless otherwise stated)
Hem

Symbol

Max.

Unit

Input high
voltage

V,H

0.8 x Vee

Vee

V

Input low
voltage

V,l

0

0.2 x Vee V

Output high
voltage

VOH

2

Output low
voltage

VOL

2

Vi-Xj on
resistance

RON

3

Input leakage
current 1

I'Ll

Input leakage
current 2

l'l2

Current
consumption 1

Pins

Typ.

Min.

Test Condition

V

IOH .. -o.4mA

0.4

V

IOl" 0.4 mA

1.0

kn

ION -150 IlA

-5

5

IlA

V,N .. Vee to GND

-25

25

IlA

V,N .. VLCO to GND

IGNO

T.B.O

IlA

Current
consumption 2

Ileo

T.B.O

IlA

Current
consumption 3

IGNO

T.B.O

IlA

Current
consumption 4

ILCO

T.B.O

IlA

4

. Vee- 0.4

0.5

Note: Pins: 1. CL, M, SHL, CH, 01, 0101, 0102, Oispoff
2. 0101, 0102
3. X1-X160, V
4. VI' V2, Vs, V6

832

HITACHI

Notes

2

2

HD66115T
Notes: 1. Indicates the resistance between one of the pins X1-X160 and one of the voltage supply pins
V,. V2 • Vs. or Vs. when load current is applied to the X pin; defined under the following
conditions:
VLco-GND = 40 V
V,. Vs" Vcc - {1120 (VLco-GND)}
Vs. V2 - GND+ {1120 (VLco-GND)}
All voltages must be within tN. VLco ~ V, ~ Vs ~ VLCO - 7.0 V. and 7.0 V ~ Vs ~ V2 ~ GND.
Note that tN depends on the power supply voltage VLco-GND (figure 5).
2. Input and output currents are excluded. When a CMOS input is left floating. excess current flows
from the power supply through the input circuit. To avoid this. V 1H and V 1L must be held at Vee
and GND. respectively.

--r------------------------VLCD
----------- V,
tN

------- Vs

IN

-------------------. Vs

------------------------ V2

~L----------------------GND

Figure 4 Relation between Driver Output Waveform and Voltage Levels

6.4
t. V (V)
Voltage level range

2.3

40

14
V Lco-GND (V)

Figure 5 Relation between VLCD-GND and,;\V

HITACHI

833

HD661lST
AC Characteristics (Vee

=2.S V to S.S V, GND =0 V, and Ta =-20°C to +7SoC, unless otherwise stated)
Symbol

Pins

Min

Clock cycle time

tCYC

CL

400

ns

Clock high-level width

tcwH

CL

30

ns

Clock low-level width

tCWL

CL

370

ns

Clock rise time

Item

Max

Unit

tr

CL

30

ns

Clock fall time

tf

CL

30

ns

Data setup time

tos

01, 0101, 0102, CL

100

ns

Data hold time

tOH

01, 0101, 0102, CL

30

ns

Data output delay time

too

0101, 0102, CL

M phase difference

tM

M,CL

Output delay time 1

tpdl
tpd2

Output delay time 2

AC Characteristics (Vee

350

ns

300

ns

X (n), CL

1.2

Ils

2

X (n), M

1.2

J.lS

2

-300

=S.O V ± 10%, GND =0 V, and Ta =-20°C to +7SoC, unless otherwise stated)
Symbol

Pins

Min

Clock cycle time

tCYC

CL

400

ns

Clock high-level width

Item

Max

Unit

tCWH

CL

30

ns

Clock low-level width

tCWL

CL

370

ns

Clock rise time

tr

CL

30

ns

Clock fall time

tf

CL

30

ns

Data setup time

tos

01, 0101, 0102, CL

100

ns

Data hold time

tOH

01, 0101, 0102, CL

30

ns

Data output delay time

too

0101, 0102, CL

M phase difference

tM

M,CL

Output delay time 1

tpdl

Output delay time 2

tpd2

Notes

90

ns

300

ns

X (n), CL

0.7

IlS

2

X (n), M

0.7

J.lS

2

Note: 1, 2 The load circuit shown in figure 6 is connected.

834

Notes

HITACHI

-300

HD66115T

Of------,

Test point

.L
..J;

"'1: 30 pF
"'2: 100 pF

Figure 6 Load Circuit

-.Ij

CL

I,

IcW\.

0. 8xV cc \

los

100

l-

0101.01021
01
(inpuI)

0101. 0102
(OUlpul)

:x

\

1\

V

0.2 x Vcc

ICYC

tcWH

0.8 x Vce
0.2 x Vec

IOH

K

0.8 xVcc
0.2 xVcc

1M

M

~
~

~

X (n)
Ipdf

Figure 7 LCD Controller Interface Timing

HITACHI

835

o

co

W

'g

0-

-=
~

r.=----

"TI

0
3

r
0
0

M

010 (input)

-----.J

1 frame

0

4801

:::>

Cl

:c

Xl
(COM1)
X2
(C,?M 2)

~

0

~

J:

-:::

~

X160
(COMl60)

0

0

Xl
(COM161)
X2

~

(CO~162)

:c
."

!!l
§

~
~

§

cr
~

3

JlJlJlJl_____JlJlJlJl _____JlJlJlJl_____JlJlJlJl_____JlJlJlJl_____JlJlJlJl_

(JQ

160161162163

320 321322 323

--

4801 2 3

160161162163

320321322323

480 1 2 3

----~-------

.----------,WV6-

---------~--------

.--------~-

~---­

~-----

X160
(COM32O)

~-----," ... ~---V6
~

----~

----

~

----

~---V6

--------~--------. .--------~----.----.
V5~----_____,,,
... r_-----=.JV6
IY&

-------W5
f\i1I'~___
a.=.....-____ ------I.

--=.JV6
V5~----

------.V5

V5r-;;p;-------=.Jv6

1Ygf----V2

~____

IVil_____

----_,,,
... ~------.V5
~
a.=.....-____

~____----JV6

_______N6
~-

f\i1I' L -____----JV6
m;;--____ ----1.

-------~--------. .--------~----.----.

010 (output)

:c

____:=:::!:Jr--

,

010 (OU1put)

:E

1 frame

:r

...

,,-..

~

U1

-l

2 3

~ _____

~ ____

.-------~----.---. .------~-

~ ____._ _ __

0

a

----

Xl
(COM 321)
X2
(COr 322)

V5m;;-------=.JV6

X160
(COM 480)

~----

--=.JV6
V5~----

----_____",
... r_------.V5
IY&
a.=.....-____
1Ygf--------,V5
V

~____

~ _..

_-----

rv1I~____ ------I.
'L-____ ----JV6

1Vil~____
~V6

~-

~
t:l
c

~

Ci
~

~

9
C'\
C'\

~
~

U'I

~

HD66115T
Connection Examples
Figures S and 9 show examples of how HD66115Ts
can be configured to drive a 4S0-liile LCD panel
with a 1/240 duty cycle. Figures 10 and 11 show
examples of how HD66115Ts can be configured to
drive a 4S0-line LCD panel with a 1/480 duty

cycle. The HD66115T's 160 channels can be divided into two groups of SO channels, and its data shift
direction can be changed by selecting the data output mode pin (CH) and data shift pin (Sm.),
respectively.

LCD panel

DATA --.. 0101
(Data of lines 1 to 240 )
IC1
(SHL =high. CH

=low)

X1

Line 1

II

I

I
I

I

,
I
I

I

,,
,,

I
I

,,
I

I
I

I
I

0102 X160

Line 160

0101

X1

Line 161

X80

Line 240
Line 241

.1.xr

IC2
(SHL • high. CH - low)
DATA --.. 01
(Data of lines 241 to 480)

I

IC3
(SHL - high, CH - low)

0102 X160

Line 320

0101

Line 321

l

X1

,

I
I
I
I
I
I
I
I
I
I
I
I
I

0102 X160 -+

Line 480

t

------------------------------ t
Segment driver

Figure 8 Dual-Screen Configuration of a 480-Line LCD Panel with a 1/240 Duty Cycle (1)

HITACHI

837

HD6611ST
LCD panel
0101

Line 1

X1 -+
I
I
I
I
I

IC1
(SHL • low, CH .. low)

t
IC2

JI

0102 X160 -+

Line 160

0101

X1 -+

Line 161

X80 -+
-+

Line 240
Line 241

~j

(SHL - low, CH .. high)
DATA - . 01
(Data of lines 1 to 240)

~xr
I

t
103
(SHL .. low, CH .. low)

0102 X160 -+

Line 320

X1 -+

Line 321

0101

I
I
I
I
I

JI

DATA - . 0102 X1.60 -+
(Data of lines 241 to 480)

Line 480

l' ------------------------------ l'
Segment driver

Figure 9 Dual·Screen Configuration of a 480·Line LCD Panel with a 1/240 Duty Cycle (2)

838

HITACHI

HD6611ST

LCD panel
DATA - + 0101
(Data of lines 1 to 48 0)
IC1

(SHL

=high. CH = low)

Line 1

X1

l!
I
I
I
I

:

IC2
(SHL = high. CH = low)

0102 X160

Line 160

0101

Line 161

X1

II
I
I
I
I
I

Line 320

0102 X160

0101

IC3
(SHL - high. CH

= low)

X1

-+

Line 321

l!
I
I
I
I
I

0102 X160 -+

Line 480

i

------------------------------ i
Segment driver

Figure 10 Single-Screen Configuration of a 480-Line LCD Panel with a 1/480 Duty Cycle (1)

HITACHI

839

HD66115T

lCOpanel
0101

X1

,

~

line 1

,,
I

I

JI

IC1
(SHl-low, CH '" low)

t

0102 X160

line 160

0101

line 161

X1
I
I
I

IC2
(SHl - low, CH '" low)

I

J

t
IC3
(SHl-low, CH '" low)

,
,
,,,
,,
,,
I

~

0102 X160

line 320

0101

line 321

X1

,,

J

,,
,I

,,
,
I

I

,
,
I
I

DATA - + 0102 X160
(Data of lines 1 to 480)

~

line 480

t

------------------------------ t
Segment driver

Figure 11 Single-Screen Contiguration of a 480-Line LCD Panel with a 1/480 Duty Cycle (2)

840

HITACHI

HD61602/HD61603--(Segment Type LCD Driver)
Descripition

Features

The HD61602 and the HD61603 are liquid
crystal display driver LSIs with a 'I"I'L and
CMOS compatible interface. Each of the LSIs
can be connected to various microprocessors
such as the HMCS6800 series.

•

•
The HD61602 incorporates the power supply
circuit for the liquid crystal display driver.
Using the software-controlled liquid crystal
driving method. several types of liquid crystals can be connected according to the
applications.
The HD61603 is a liquid crystal display driver
LSI only for static drive and has 64 segment
outputs that can display 8 digits per chip.

•

Wide-range operating voltage
-Operates in a wide range of supply
voltage: 2.2 V to 5.5 V
--Compatible with TIL interface at 4.5 V
to 5.5 V
Low current consumption
--Can run from a battery power supply
(100 J,lA max. at 5 V)
-Standby input enables standby operation at lower current consumption (5
J,lA max. on 5 V)
Internal power supply circuit for liquid
crystal display driver (HD61602)
-Internal power supply circuit for liquid
crystal display driver facilitates the
connection to a microprocessor system

Frame Freq. IHzl
at f ... = 100 kHz

Package
80-pin
--:-----,----------=-----=----------::6-=5----Plastic
QFP
~----~~~~----------~--------~----------2-0-8------- FP-SO

33

~--~--------~--------=----------22~3-------(~~~~~)
33

80-pin
Plastic
QFP
(FP-80)

Ordering Information
Type No.

HD61602R
HD61602RH
HD61603R

80-pin plastic QFP(FP-SO)
SO-pin plaatic QFP(FP-80A)
SO-pin plastic QFP(FP-80)

HITACHI

841

HD61602/HD61603
Pin Arrangement (Top View)
HD61602R

HD61603R

(Top View)

JJJJJJJJJJJJJJJJ
wwwwwwwwwwwwwwww
en
en en
en en
tJ)

(I) CI) (/)(1.)(1)

(FP-80)

HD61602RH

i~:'!!::::e~;!::?~:::l2mf&iQ:S181ld&l;o

~
~
58
07

:F ~~~::
•

~n

111

SEGIs
SEG'9
SEG20
~~
SEG22
SEG2:!

.

06
~
04

63

VSS

03
02

0,
00

&1
50

13
I.

47

~~~2r= ::

r=:

SEG28

: ~~~:

~~' ~ ::
~:

SEG24
SEG26

SEG2S
SEG27

12

VAE"Fl~

~::I~~:!;l~i;~~!il;:;J:lR~lI;=r;;I!IJli

...JL

...JL

(FP-80A)
(Top View)

842

CI) U)(I) ClHJ)

(FP-80)

HITACHI

:F ~~~:;
:F ~~~!:

HD61602/HD61603
Block Diagram
HD61602
SYNC

,-------------------------,
Common output
(4Iine5)

Segment output
(51 lines)

HD61603

LCD driving
tlmmg
generator

.cs..

~

Do-D.

S8

Common
output

RAM write
timing generator

Paraliel/se",1
converter

Segment
output
(64Iin88)

Address
decoder

HITACHI

843

HD61602/HD61603
Absolute Mazlmum Ratings
Symbol

Limit

Unit

Voo, V1, V2, V3

0.3 to + 7.0

V

Vr

0.3 to Voo - 0.3

V

Operating temperature

Topr

-20 to +75

·C

Storage temperature

Tstg

-55 to +125

·C

Item
Power supply voltage
Terminal voltage

*

*

*

Value referenced to Vss = 0 V.
Note: If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using
them within electrical characteristics limits is strongly recommended for normal operation. Use
beyond these conditions will cause malfunction and poor reliability.

Recommended Operating Conditions
limit
Max

Unit

2.2

5.5

V

V1, V2, V3

0

Voo

V

Vr

0

Voo

V

'Topr

-20

75

·c

Item

Symbol

Min

Power supply voltage

Voo

Terminal voltage

*

Operating temperature

* Value referenced to Vss =

844

0 V,

HITACHI

Typ

HD61602/HD61603
Electrical Characteristics
DC Characteristics (1)
(Vss

= 0 V, VDD = 4.5 to 5.5 V, Ta = -20 to

+75'C, unless otherwise noted)
Limit

Item
Input high voltage

OSC,
Others

Input low voltage

OSC,

Output leakage
current
Output low
voltage
Input leakage
current
*1

*
*1

Unit
V

Teat Condition

V
Voo
0.2Voo V
0.8
V

Others
READY

IOH

5

pA

Vo = Voo

READY

VOL

0.4

V

IOL = 0.4 mA

Input
terminal

IlL'

-1.0

1.0

pA

V,

hL2

-20

20

pA

IIL3

-5.0

5.0

pA
V

± Id = 3 pA for each
COM, V3 = Voo-3 V

0

COMo-COM3

Vd'

0.3

SEGo-SEG50

Vd2

0.6

V

± Id = 3 pA for each
SEG, V3 = Voo-3 V

100

100

pA

100

5

pA

During display*
Rose = 360 kO
At standby

VrR

0.4

V

Power supply current

Internal driving
voltage drop

0

Max
Voo

VIL'
VIL2

V2, V3
LCD driver voltage
drop

Typ
Symbol Min
0.8Voo VIH'
2.0
VIH2

V" V2, V3

VREF2 = Voo-1 V,
C,-C4 = 0.3 pF,
RL = 3 MO

Except the transfer operation of display data and bit data.
V" V2: apply only to HD61602.

HITACHI

845

HD61602/HD61603
DC Characteristics (2)

(V.

= 0 V, VDD = 2.2 to 3.8 V, Ta = -20 to +7S"C, unless otherwise Doted)

Item
Input high voltage
Input low voltage
Output leakage
current
Output low
voltage
Input leakage
current

.;

LCD driver voltage
drop

Limit
Symbol Min
Typ
0.8Voo VIH
0
VIL

Teet ConcItion

10H

0.1Voo V
pA
5

VIN

= Voo

READY

VOL

0.1Voo V

10L

= 0.04 rnA

Input
terminal

hL!

-1.0

Vl

hL2

V2. V3

hL3

COMo-COM3
SEGo-SEG50

Vl. V2. V3

1.0

pA

VIN

= O-Voo

-20

20

pA

YiN

= 0-V3

-5.0

5.0

pA

Vdl

0.3

V

Vd2

0.6

V

Iss

50

pA

Iss

5

pA

Vm

0.4

V

0

* Except the transfer operation of display data and bit data.
*1 Vl. V2: apply only to HD61602.

846

Unit
V

READY

Power supply current

Internal driving
voltage drop

Max
Voo

HITACHI

±Id = 3 pA for each
COM. V3 = Voo-3 V
±Id = 3 pA for each
SEG. V3 = Voo-3 V
During display·
Rose = 330 kO
At standby
VREF2 = Voo-1 V.
Cl-C4 = 0.3 pF
RL = 3 MO.
Voo = 3-3.8 V

HD61602/HD61603
AC Characteristics (1)
(Vss

= 0 V, Voo = 4.5 to 5.5 V, Ta = -20 to+75'C, unless otherwise noted)
Symbol Min

Item

Limit
Typ

Max

Unit

Test Condition

Oscillation frequency

OSC2

fosc

70

100

130

kHz

Rosc=360 kO

External clock
frequency
External clock duty

OSC1

fosc

70

100

130

kHz

50

60

%

OSC1

I/O signal timing

Duty

40

ts

400

tH

10

ns

twH

300

ns

twL

400

ns

twR

400

ns

ns
1.0

tOL

Input signal rise time and fall time

JlS

tEN

400

tOP1

9.5

10.5

Clock

toP2

2.5

3.5

Clock

25

ns

Figure 5

ns

t r • tf

For display
data transfer
For bit and mode
data transfer

AC Characteristics (2)
(Vss

= 0 V, Voo = 2.2 to 3.8 V, Ta = -20 to+75'C, unless otherwise noted)
Symbol Min

Item
Oscillation frequency

OSC2

External clock
frequency
External clock duty

OSC1

Limit
Typ

Max

Unit

Test Condition

fosc

70

100

130

kHz

Rosc=330 kO

fosc

70

100

130

kHz

50

60

%

Duty

40

I/O signal timing

ts

1.5

Jls

(Voo = 3.0-3.8 V)

tH

1.0

Jls

twH

1.5

JlS

tWL

1.5

OSC1

Input signal rise time and fall time

JlS
2.0

tOL
twR

1.5

JlS

tEN

2.0

tOP1

9.5

10.5

Clock

tOP2

2.5

3.5

Clock

25

ns

t r • tf

HITACHI

Figure 6

JlS
JlS
For display
data transfer
For bit and mode
data transfer

847

HD61602/HD61603

00- 0 7

)-----------------~

Figure 1

Write Timing
(RE Is fixed at high level, and SYNC at low level)

READY

Figure 2

Figure 3

848

Reset/Read Timing
(CS and SYNC are fixed at low level)

READY Timing
(When the READY output is always available)

HITACHI

HD61602/HD61603

ReADY

t: F=-=-~~~-~~~--W-ith-in-lO"
_
V1H

SYNC

ViL

Figure 4

1 clock

ViH
~.______________________

SYNC Timing

Voo

Voo

47kQ

470kQ

10kQ

Measurement
terminal

Measurement
terminal
0----1

(READY)

(READY)

30pF

120kQ!1S2074H

'----+_ _- 4 - _ Vss

Figure 5

Bus Timing Load Circuit
(LS-TTL Load)

Figure 6

HITACHI

Bus Timing Load Circuit
(CMOS Load)

849

HD61602/HD61603
Terminal Functions
HD61602 Terminal Functions
Terminal
Name

No. of
U ....

Input/Output

Connected
to

Function

Voo

Power supply

READY

NMOS open
drain output

MCU

While data is being set in the display data RAM and
mode setting latch in the LSI after data transfer. low
is output from the READY tarminal to inhibit the
next data input.
There are two modes: one in which low is output
only when both of CS and RE are low. and the other
in which low is output regardless of CS and RE.

CS

Input

MCU

Chip select input. Data can be written only when
this terminal is low.

WE

Input

MCU

Write enable input. Input data of DO to 07 is latched at the rising edge of WE.

RE

Input

MCU

Resets the input data byte counter. After both CS
and RE are low. the first data is recognized as the
1st byte data.

S8

Input

MCU

High level input stops LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.

Input

MCU

Data input terminal for 8-bit x 2-byte data.

00-07

8

Positive power supply.

Vss

Power supply

Negative power supply.

VREFI

Output

Extemal
R

Reference voltage output. Generates LCD driving
voltage.

VREF2

Input

Extemal
R

Divides the reference voltage of VREFI with external
R to determine LCD driving voltage. VREF2 ~ VI.

VCI. VC2

2

Output

External
C

Connection terminals for boosting C of LCD driving
voltage generator. An external C is connected
between VCI and VC2.

VI. V2. V3

3

Output
(Input)

External
C

LCD driving voltage outputs. An external C is connected to each terminal.

COMo-COM3 4

Output

LCD

LCD common (backplate) driving output.

Output

LCD

LCD segment driving output.

Input

MCU

Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high
input. LCD is off.

Input
Output

External
R

Attach external R to these terminals for oscillation.
An external clock (100kHz) can be input to OSC1 .

SEGo-SEG50

51

SYNC

OSCI
OSC2

2

Note: Logic polarity is positive. 1 = high = active.

850

HITACHI

HD61602/HD61603
HD61603 Terminal Functions
Terminal

Name

No. of
Lin..

Connected
Input/Output

Function

to

Voo

Power supply

READY

NMOS open
drain output

MCU

While data is being set in the display data RAM and
mode setting latch in the LSI after data transfer, low
is output from the READY terminal to inhibit the
next data input.
There are two modes: one in which low is output
only when both of CS and RE are low, and the other
in which low is output regardless of CS and RE.

CS

Input

MCU

Chip select input. Data can be written only when
this terminal is low.

WE

Input

MCU

Write enable input. Input data of Do to 03 is latched
at the rising edge of WE.

RE

hlput

MCU

Reset the input data byte counter. After both of CS
and RE are low, the first data is recognized as the
1st byte data.

S8

Input

MCU

High level input stops the LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.

Input

MCU

Data input terminal from where 4-bit x 4 data are
input.

00-03

4

Positive power supply.

Vss

Power supply

V3

Input

Power
supply

Power supply input for LCD drive. Voltage between
Voo and V3 is used as driving voltage.

COMo

Output

LCD

LCD common (backplate) driving output.

Output

LCD

LCD segment driving output.

Input

MCU

Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high
input. LCD is off.

Input
Output

External
R

Attach external R to these terminals for oscillation.
An external clock (1 00 kHz) can be input to OSC, .

SEGo-SEG63

64

SYNC

OSC,
OSC2

2

Note: Logic polarity is positive. 1

Negative power supply.

= high = active.

HITACHI

851

HD61602/HD61603
Display RAM
HD61602 Display RAM
The HD61602 has an: internal display RAM
shown in figure 7. Display data is stored in
the RAM. or is read according to the LCD

driving timing to display on the LCD. One bit
of the RAM corresponds to 1 segment of the
LCD. Note that some bits of the RAM cannot
be displayed depending on LCD driving
mode.

Common address

(COM o-COM 3 )

)! {L---I

_DisPlaY_RAM

_I

~~---------------------Vy--------------------~I
51 bits

Segment address (SEGo-SEGso)

Figure 7

852

Display RAM

HITACHI

HD61602/HD61603
is reproduced on the LCD panel.
When a 7-segment type LCD driver is connected, for example, the correspondence
between the display RAM and the display
pattern in each mode is as follows:

Reading Data from Display RAM: A display RAM segment address corresponds to a
segment output. The data at segment
address SEGn is output to segment output
SEGn terminal.

1.

A common address corresponds to the output
timing of a common output and a segment
output. The same common address data is
simultaneously read. The data of display RAM

Static drive
In the static drive, only the column of
COMo of display RAM is output. COMl to
COMa are not displayed.

LCD connection
Display RAM

COM.
COM.
COM,
e

d

c

DP

9

b

SEG.

SEG lO

SEG"

SEG,.

SEG,.

SEG,.

COMo

.

(!)

(!)

'"

J

(!)

Ul

Ul

Ul

Ul

w w

2.

w

W

r5c5JJ
wwww

SEG.

SEG,.

Ul Ul Ul Ul

1/2 duty cycle drive

COMo and COMl of display RAM are output in time sharing. The columns of COM2
and COM3 are not displayed.

In the 1/2 duty cycle drive, the columns of
LCD connection

a
Display RAM

COM 3

a

COM,
COMo

Jw cE
w
Ul

Ul

~
w
Ul

tE'
w
Ul

SEG.

3. 1/3 duty cycle drive
In the 1/3 duty cycle drive, the columns of
COMo to COM2 are output in time sharing.
No column of COMa is displayed.

9

c

b

e

d

DP

SEG s

SEG s

SEG 7

SEG s

SEG g

"Y" cannot be rewritten by display data
(input on an 8-segment basis). Please use
bit manipulation to turn onloff the display of "Y".

HITACHI

853

HD61602/HD61603
LCD connection

Display RAM

COM 3

..

c£
w
4.

(!J

c§

rn

rn

w

rn

/

/
y

a

b

COM 1

f

9

c

COMo

e

d

DP

w

1/4 duty cycle drive
In the 1/4 duty cycle drive. all the col-

umns of COMo to COM3 are displayed.

LCD connection
Display RAM

N
(!)

w
rn

854

1/ /

/

COM 2

COM 3

f

a

COM 2

9

b

COM 1

e

c

COMo

d

DP

'"
(!)

w
rn

HITACHI

HD61602/HD61603
Writing Data into Display RAM: Data is

a-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/4 duty cycle drive.

written into the display RAM in the following
five methods:
1. Bit manipulation
Data is written into any bit of RAM on a
bit basis.
2. Static display mode
a-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of static drive.
3. 1/2 duty cycle display mode
a-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/2 duty cycle drive.
4. 1/3 duty cycle display mode
a-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/3 duty cycle drive.
5. 1/4 duty cycle display mode

(1)

(2)

Static

COMoCOM,COM2

The RAM area and the alocation of the segment data for i-digit display depend on the
driving methods as described in "Reading
Data from Display RAM".
a-bit data is written on a digit basis corresponding to the above duty cycle driving
methods. The digits are allocated as shown
figure a (allocation of digits). As the data can
be transferred on a digit basis from a microprocessor, transfer efficiency is improved by
allocating the LCD pattern according to the
allocation of each bit data of the digit in the
data RAM.
Figure a shows the digit address (displayed

1/2 duty cycle
display

(3)

(4)

1/3 duty cycle
display

COMoCOM ,COM 2 COM3

COMoCOM,COM 2

SEGo

SEGo

SEGo

SEG,

SEG,

SEG,

SEG2

SEG2

SEG2

SEG3

SEG3

SEG3

SEG4

SEG4

SEG4

Ad1

SEG4

SEGs

SEGs

1--+--+"'-'

SEGs

SEGs

SEG6

SEG s
SEGs

SEG7
SEG s
SEGg

SEG7

SEG7

Ad2

SEG"

SEGs

SEGs

SEGg

SEGg

SEG,o

SEG,o

SEG"

SEG"

SEG'2

SEG'2

SEG 12

SEG'3

SEG'3

SEG'3

SEG'4

SEG'4

SEG'4

SEG'6

SEG,s

SEG,s

SEG'6

SEG,s

SEG 17

SEG 17

SEG,s

SEG,a

SEG 17

SEG so

Figure 8

1/4 duty cycle
display

SEG 50

SEGo
AdO

SEG,

AdO

SEG2

~-I--+--V

SEG3

SEG s
SEG7
SEGa

I-+--+--f

SEGg
SEG 10

Ad3

Ad1
Ad2

Ad3
Ad4
AdS

SEG"

I-+--+--t-

SEG'2
Ad4

Ad6

SEG'3
SEG'4

1-+--+--1

Ad7

SEG'6
SEG'6

AdS

1-+--+--1

SEG,s

Ad6
Ad16

Ada

SEG'7
Ad24

.....

'-----'-

SEG 50

Ad2S

Allocation of Digit (HD61602)

HITACHI

855

HD61602/HD61603
as Adn) to specify the store address of the
transferred 8-bit data on a digit basis.
Figure 9 shows the correspondence between
each segment in an Adn and the 8-bit input
data.
When data is transferred on a digit basis, 8bit display data and digit address should be
specified as described above.

In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, 1-bit display data, a segment address (6 bits) and a common address
(2 bits) should be specified.
HD61603 Display RAM
The HD61603 has an internal display RAM an
shown in figure 10. Display data is stored in·
the RAM and output to the segment output
terminal.

However, when the digit address is Ad6 for
static, Ad12 for 1/2 duty cycle, or Ad25 for 1/
4 duty cycle, display RAM does not have
enough bits for the data.
Thus the extra bits of the input 8-bit data are
ignored.

(1 )

(2)

Static display

1/2 duty display

COMo
SEGs

(3)

1/3 duty display

COM o COM 1

Bit

Bit

SEGln

7

7

6

COMo COM 1 COM2
Bit

7

6

SEGSn +1

6

SEG4n+l

5

4

SEG3n+l

5

4

3

SEGSn +2

5

SEG4n+2

3

2

SEG3n + 2

2

1

Bit

SEG4n +3

1

Bit

SEG 8n +3

0

0

SEGSn +4

(4)

1/4 duty display

SEGsn+s
COMo COM 1 COM2 COM 3

SEGSn+6
SEGSn +7

SEG2n

Bit

0

SEG2n+l

Figure 9

Bit

7

6

5

4

3

2

1

Bit

0

Bit Assignment in an Adn (HD61602)

1 bit

(COMo){tl====================D=isP=la~~=R=A=M======================:1J
64 bits
Segment address (SEGo-SEG 63)

Figure 10

856

Display RAM (HD61603)

HITACHI

HD61602/HD61603
Reading Data from Display RAM: Each
bit of the display RAM corresponds to an LCD
segment. The data at segment address SEGn
is output to segment output SEGn terminal.
Figure 11 shows an example of the correspondence between the display RAM bit and
the display pattern when a 7-segment type
LCD is connected.

Writing Data into Display RAM: Data is
written into the display RAM in the following
two methods:
1. Bit manipulation
Data is written into any bit of RAM on a

2.

bit basis.
Static display mode
a-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of static drive.

The a-bit data is written on a digit basis into
the digit address (displayed as Adn) shown in
figure 12. When data is transferred from a
microprocessor, four 4-bit data are needed to
specify the digit address and an a-bit display
data. Figure 13 shows the correspondence
between each segment in an Adn and the
transferred a-bit data.

LCD connection

Display RAM

SEGs SEGg SEG,o SEG ll SEG'2 SEG'3 SEG'4 SEG'5 SEG'6

Figure 11 Example of Correspondence between Display RAM Bit and Display Pattern
(8061603)

HITACHI

857

HD61602/HD61603
In bit manipulation, anyone bit of display
RAM can be written. When data is transfer-

red on a bit basis, l-bit display data and a
segment address (6 bits) should be specified.

COMo
SEGo
SEG1
SEG2

COMo

SEG3 AdO
SEG4
SEG5
SEGe
SEG7
SEG 8
SEG g

SEGsn
SEG45
SEG48
SEG47
SEG 48
SEG49

SEG 10
SEG~
SEG11 Ad1 SEG51 Ad6
SEG 52
SEG 12
SEG13
SEG14
SEG15
SEG18
SEG17
SEG18

Bit
7

SEG8n+l

6

SEG8n +2

5

SEG8n +3

4

SEG 53
SEG 54
SEG55
SEG 58

SEG S7
SEG58
SEG19 Ad2 SEGS9 Ad7
SEG 20
SEG 80
SEGel
SEG21
SEG 82
SEG 22
SEG83
SEG23
SEG24

Figure 12 Allocation of
(H061603)

858

~igits

Figure 13 Bit Assignment in an Adn
(H061603)

HITACHI

HD61602/HD61603
OPERATING MODES
HD61602 Operating Modes
The HD61602 has the following operating
modes:
1. LCD drive mode
Determines the LCD driving method.
a. Static drive mode
LCD is driven statically.
b. 1/2 duty cycle drive mode
LCD is driven at 1/2 duty cycle and 1/
2 bias.
c. 1/3 duty cycle drive mode
LCD is driven at 1/3 duty cycle and 1/
3 bias.
d. 1/4 duty cycle drive mode
LCD is driven at 1/4 duty cycle and 1/
3 bias.
2.

b.

c.

d.

3.

READY output mode
Determines the READY output timing.
After a data set is transferred, the data is
processed internally. The next data cannot be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
the READY is output can be selected from
the following two modes:

Data display mode
Determines how to write display data
into the data RAM.
a. Static display mode
a-bit data is written into the display
RAM according to the digit in static

a.

drive.
1/2 duty cycle display mode
a-bit data is written into the display
RAM according to the digit in 1/2
duty cycle drive.
1/3 duty cycle display mode
a-bit data is written into the display
RAM according to the digit in 1/3
duty cycle drive.
1/4 duty cycle display mode
a-bit data is written into the display
RAM according to the digit in 1/4
duty cycle drive.

READY is mode always available.

, _.......
r

--------'/

I

WE~

'~----------------,/I
I
I

READY
Data transfer
period

b.

:'---/
I

- - - _....;'..._ - - - - - - - I n p u t i n h i b i t - - - - - -.....
--!'
period
:

I

I

I

I--- Next data

I

transfer

READY is mode available by CS and
RE.

).

/

cs
I

RE

I

,
,,
I

READY
Data transfer
'period

I

.. ,-

/

,
I

~

WE

4.

I

I

\.

I
I
I
I
I
I

,

'\
~

;(
I

I

'-----.V
Input inhibit
period

LCD OFF mode
In this mode, the HD61602 stops driving
LCD and turns it off.

5.

\I
I
,
"---./1I

-,

I
I
I

I

,,

I

I-- Next data
transfer

External driving voltage mode
A mode for using external driving voltage
(Vl, V2, and V3).

HITACHI

859

HD61602/HD61603
The above 5 modes are specified by mode
setting data. The modes are independent of
each other and can be used in any combina-

tion. Bit manipulation is independent of data
display mode and can be used regardless of it.

HD61603 Operating Modes
not be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:

The HD61603 has the following modes:
1. READY output mode
Determines the READY output timing.
After a data set is transferred, the data is
processed internally. The next data cana.

READY is always available.

\'1--

--------'/

I

./1

READY - - - - - - - - . "

~I------------------------~

I

I
Data transfer----~Iioo..- - - - - - - I n p u t i n h i b i t - - - - - -.....-II
period
period
I

b.

/

~I

WE

,

'At
READY

Data transfer
period

860

I
I

' - -Next data
transfer

READY is mode available by CS and
RE.

cs

2.

I

1
1
1
I
I

-, ..

/

\.I
I

"

I
I
I
I

,
1

"1'I

'---Y
Input inhibit
period

LCD OFF mode
In this mode, the HD61603 stops driving
the LCD and turns it off.

HITACHI

"

f'-/

I III

).
I
I

'---/l

I

"I

1
I
I

I-- Next data
transfer

HD61602/HD61603
INPUT DATA FORMATS
HD61602 Input Data Formats
Input data is composed of 8 bits x 2. Input
them as 2-byte data after READY output
changes fro~ow to high or low pulse is
entered into RE terminal.
1.

3.

Mode setting data

1st byte

Display data (Updates display on an 8segment basis)

o
7

1st byte

~~Plat
add~SS ;
(Digit address Adn)
7

6

4

5

3

2

1

765

2.

JI~I:::-""I
3
2 1
0

x

x

x

x

1~/1 :!::':I..

x

7654321'0

432

Display mode bits:
00: Static display mode
01: 1/2 duty cycle display mode
10: 1/3 duty cycle display mode
11: 1/4 duty cycle display mode
b. OFF/ON bit:
1: LCD off (set to 1 when SYNC is
entered.)
0: LCD on
c. Drive mode bits:
00: Static drive
01: 1/2 duty cycle drive
10: 1/3 duty cycle drive
11: 1/4 duty cycle drive
d. READY bit:
0: READY bus mode; READY outputs 0 only while CS and RE are
O. (reset to 0 when SYNC is
entered.)
1: READY port mode; READY
outputs 0 regardless of CS and
RE.
e. External power supply bit:
0: Driving voltage is generated
internally.
1: Driving voltage is supplied
externally. (set to 1 when SYNC
is entered.)

o

Bit manipulation data (Updates display
on a segment basis)
1st byte

6

4

I I I I I

o

Display address: Digit address Adn in
accordance with
display mode
Display data:
Pattern data that is
written into the
display
RAM
according to display
mode and the
address

7

5

a.

I : :
b.

6

2nd byte

2nd byte

a.

External
power
supply

5

4

3

2

o

2nd byte

6
5
432
o
Display data:
Data that is written
into 1 bit of the
specified display
RAM
b. COM address:
Common address of
display RAM
c. SEG address:
Segment address of
display RAM
7

a.

4.

1-byte instruction
l.st byte

III I II
7

1

x

x

x

x

6

5

4

3

2

x

I

x
0

The first data (first byte) is ignored when
bit 6 and bit 7 in the byte are 1.

HITACHI

861

HD61602/HD61603
HD61603 Input Data Formats
Input data is composed of 4 bits x 4. Input
them as four 4-bit data after READY output
changes from low to high or low pulse is
entered into RE terminaL

Mode setting data
1st byte

I :

Display data (Updates display on an 8segment basis.)

1.

I

0
3

:

0

x

b.

Display address
(Digit address Ad"1

x
0

2

3rd byte
Display data
4
5
Bitl7 6
0
2
3
a.

I : 1~!~~lavl x0
2

1

2
3
a. Display data:

862

x 1 0 1 r--I
x ;....-....,1~~ADYI.-x:'------'x
o

Bit3
3

3

Display data
1
0
2

b.

0

2

SEG address:

II

x: x
3

2

I

0

4th byte
X

a.

4.

0
0

SEG address
Bit3
2
1
0
3
2
0
Data that is written
into 1 bit of the
specified display
RAM.
Segment address of
display RAM (segment output).

HITACHI

o

2

3

II..--<~x:L---J x II

Display address: Digit address Adn
shown in figure 12.
Display data:
Pattern data that is
written into the
display RAM as
shown in figure 13.

0

b.

0

2

3

0

2

3

Bit manipulation data (Updates display
on a segment basis.)
2nd byte
1st byte

3

2 nd byte

3rd byte

1st byte

2.

3.

2

L...-......I

0

x ~~F/DNI
3

2

0

o
o

OFF/ON bit:
1: LCD off (set to 1 when SYNC is
entered.)
0: LCD on
READY bits:
0: READY bus mode; READY outputs 0 only while CS and RE are
O. (reset to 0 when SYNC is
entered.)
1: READY port mode; READY
outputs 0 regardless of CS and
RE.

1-byte instruction
1st byte

1

1
3

: Ix
1

2

>
0

The first data (4.bits) is ignored when bit
3 and 2 in the data are 1.

HD61602/HD61603
How To Input Data
How to Input HD61602 Data
Input data is composed of 8 bits x 2. Take
care that the data transfer is not interrupted,
because the first 8-bit data is distinguished
from the second one by the sequence only.
If data transfer is interrupted, or at power on,

the following two methods can be used to
reset the count of the number of bytes (count
of the first and second bytes):
1. Set CS and RE inputs low (no display data

changes).
Input 2 or more "l-byte instruction" data
in which bit 7 and 6 are 1 (display data
may change).
The data !!!E..ut method via data input terminals (CS, WE, Do to 07) is similar to that of
static RAM such as HM6116. An access of the
LSI can be made through the same bus line as
ROM and RAM. When output ports of a
microprocessor are used for an access, refer to
the timing specifications and figure 14.
2.

Power on

-~~----I~
__~'----~__-r--~__~
CS,
WE' *6

RE~'-\J*4
READY L:.::-"';~~:;·"'~-3--"\'------..J"'----""'~

*5

SYNC----------~~---------------Jr--\

*5

*2

SB----------~~---------------------------------------Do-D7~~Gl~.tCX~2n~d]X::::::::::JXCi~st~XOZ~d~Ir:::::::JIC1~'t~X~2~nldlr:::

Mode setting data

*1:
*2:
*3:
*4:

* 5:

*6:

* 7:

Mode setting data

Display data

READY output is indefinite during 12 clocks after the oscillation start
at power on (clock: OSC z clock).
High pulse should be applied to SYNC terminal when using two or more
chips synchronously.
In the mode in which READY is always available, READY output is
in definite while SYNC is high.
Reset the byte counter after power on.
READY output period is within 3.5 clocks in the mode setting operation
and bit manipulation or within 10.5 clocks when the display data (8
bits) is updated.
Connect a pull-up resister if WE or RE may be floating.
It is not always necessary to follow this example.

Figure 14

Example of Data Transfer Sequence

HITACHI

863

HD61602/HD61603
How to Input HD61603 Data
Input data is composed of 4 bits X 4. Take
care that data transfer is not interrupted,
because the first 4-bit data to the fourth 4-bit
data are distinguished from each other by the
sequence only.

Set CS and RE low.
Input 4 or more "i-byte instruction" data
(4-bit data) in which bit 3 and 2 are 1
(display data may change).
The data ~ut method via data input terminals (CS, WE, DO to D3) is similar to that of
static RAM such as HM6116. An access of the
LSI can be made through the same bus line as
ROM and RAM. When output ports of a
microprocessor are used for an access, refer to
the timing specifications and .figur.e 15.

1.
2.

If data transfer is interrupted, or at power on,

the following two methods can be used to
reset the count of the number of data (count
of the first 4-bit data to the fourth 4-bit data):

Power on
CS

j/r------~\~~_______Jlr------~\~____~/r----~\~____~,__

WE

1*6

RE~*4

. .L

READY L~:::-.;r--~:I-I-----....,LJ"'-:::j,..------~\...___1r----*1

*5

*3

*5

*5

SYNC _______~fI.---------------Jr\~*~2~--------------------

SB-------~~-------------------------------------

Do-D3~r--<~b~'X~,=M~X~3~~X~,,~bXB_

_______X~1=,,~X~~~X~~~X~·~~4X_______AX~1"~X~'M~X~,~~X~.=~4X__

Mode setting data

* 1:
*2:
* 3:
*4:
*5:

* 6:
* 7:

Display data

READY output is indefinite during 12 clocks after the oscillation start
at power on (clock: OSC 2 clock).
High pulse should be applied to SYNC terminal when using two or more
chips synchronously.
In the mode in which READY is always available, READY output is indefinite while SYNC is high.
Reset the 4-bit data counter after power on.
READY output period is within 3.5 clocks in the mode setting operation
and bit manipulation or within 10.5 clocks when the display data (8
bits) is updated.
Connect a pull-up resister if WE or RE may be floating.
It is not always necessary to follow this example.

Figure 15

864

Mode setting data

Example of Data Transfer Sequence

HITACHI

HD61602/HD61603
Notes on READY Output
Note that the READY output will be unsettled during 1.5 clocks (max) after inputting
the first 2-byte data for setting the mode
after turning the power on. This is because
the READY bit data of mode setting latches
and the mode of READY pin (READY bus or
port mode) are unsettled until the completion
of mode setting.
There are two kinds of the READY output
waveforms depending of the modes:

1.

READY bus mode (READY bit == 0)

2.

READY port mode (READY bit == 1)

However, if you input SYNC before mode
setting, waveform will be determined; when
you choose READY bus mode, (1) a in figure
16 will be output, and when you choose
READY port mode, (2) a will be output. The
figures can be applied both to HD61602 and
HD61603.

,

Power on

Do-D7~------------------------~r-l1:~~"' '--2n-d---}~~------------------

WA.V

READY output is unsettled.
/,It
Mode setting data
(2 -byte data) ~ 1 .5 .clocks (max)
Mode setting latch is unsettled.
Mode setting data are
latched.

Power on

+

'---_-II
READYr-----------------------------~----~----,_--~
Note: CS
Power on

(1)

~

~

\

= low

_______ J

b

"

READY Bus Mode .1.5 clocks (max)

/
a

READY

\

Note: CS

= low,

RE
(2)

Figure 16

= high

----""\

\

b
.. ------1
\

/

1 .5 clocks (max)

READY Port Mode

3.5 clocks (max)

READY Output According to Modes

HITACHI

865

HD61602/HD61603
Standby Operation
Standby operation with low power consumption can be activated when pin SB is
used. Normal operation of the LSI is activated
when pin SB is low level, and the LSI goes
into the standby state when pin SB'is high
level. The standby state of the LSI is as follows:
1.
2.

LCD driver is stopped (LCD is off).
Display data and operating mode are
held.

3.

4.

The operation is suspended while display
changes (while READY is outputting
low.) In this case, READY outputs high
within 10.5 clocks or 3.5 clocks after
release from the standby mode.
Oscillation is stopped.

When this mode is not used, connect pin SB to
Vss.

Multichip Operation
When an LCD is driven with two or more
chips, the driving timing of the LCD must be
synchronized. In this case, the chips are
synchronized with each other by using SYNC
input. If SYNC input is high, the LCD driver
timing circuit is reset. Apply high pulse to the
SYNC input after the operating mode is set.
A high pulse to the SYNC input changes the
mode setting data. (The OFF ION bit is set
and the READY bit is reset. See 3. Mode
Setting Data in "Input Data Formats".) Transfer the mode setting data into the LSI after

every SYNC operation.
If a power on reset signal is applied to the
SYNC pin, the LCD can be off-state when the
power is turned on.

When SYNC input is not used, connect pin
SYNC to Vss.
When SB input is used, after standby mode is
released, a high pulse must be applied to the
SYNC input, and mode setting data must be
set again.

Restriction on Usage
Minimize the noise by inserting a noise bypass capacitor (;E; 1 pF) between VDD and
Vss pins. (Insert one as near chip as possible.)

Liquid Crystal Display Drive Voltage Circuit (HD61602)
What is LCD Voltage?
HD61602 drives liquid crystal display using
four levels of voltages (figure 17); VDD, Vl, V2;
and V3 (VDD is the highest and Va is the
lowest). The voltage between VDD and V3 is
called VLCD and it is necessary to apply the
appropriate VLCD according to the liquid
crystal display. V3 always needs to be supplied regardless of the display duty ratio since it supplies the voltage to the LCD drive
circuit of HD61602.

Voo

Figure 17

866

HITACHI

LCD Output Waveform and
Output Levels

HD61602/HD61603
When Internal Drive Power Supply
is Used
When the internal drive power supply is
used, attach Cl-C4 for charge pump circuits
and variable resistance Rl for deciding display drive voltage to HD61602 as shown in
figure 18.
Internal voltage is available by setting
external voltage switching bits of mode setting data O.
Figure 19 shows voltage characteristics
between Voo and VREFI. Voltage is divided at
Rl, and then input into VREF2. Voltage
between Voo and VREF2 is equivalent to Il.V in

figure 19, and so VLCD can be changed by
regulating the voltage.
VREF2 is usually regulated by variable resistance, but when replacing Rl with two
nonvariable resistances take VREFI between
max and 'min into consideration as shown in
figure 19.
Internal drive power supply is generated by
using capacitance, and so large current cannot flow. When large liquid crystal display
panel is used, examine the extemal drive
power supply.
.

Power

___I

_ _---I

Regulator

-----,L-_~

Voltage follower

19 VC2
20 V,
C3
21
"2
C4
22
V3
23-26 COM
C2

77
76
LCD

75

Charge
pump

3X(V,-V oo )

circuit

SEGo
HD61602

SEG,
SEG2

R, = 1 MO Variable
c,=0.3pF
C2-C4=0.3pF
C5=0.1 to 0.3pF
CsO!; 1 pF

Figure 18

Example

HITACHI

867

HD61602/HD61603
When External Drive Power Supply is Used
An external power supply can be used by
setting external voltage switching bits of
mode setting· data to 1. When a large liquid
crystal display panel is used. in multichip
designs. which need accurate liquid crystal
drive voltage. use the external power supply.
See figure 20.
.

and Vss. and by these resistance ratio each
voltage of t:.V and VLCD is generated and then
supplied to Vl. V2. and V3. C2-C4 are smoothing capacitors.
When regulating brightness. change the
resistance value by setting R5 variable resistance.

R2-Rs is connected in series between VDD

Voo-Vss (V)

r

S

0

>

5

"!

6
I

:
-----~~__+.-min

i1.7

~

3 4

'.

~ 1.6

> 1.8

2
'

\

1.9
2 .0
2.1

'-=

nn",\~

\

I

i -

typ

:
:

\

2.2

!

------ .!!::~"'L.---_max

2.3

Figure 19

Voltage Characteristics
between VDD and Vrefl

Positive

Voo
Vss

C.

power

supply

Positive
power
supply

Vcc
V••

C.

VAEF1

VREF2
Vc,
Vcz
V,
Vz

Rz

C.

Rz
Cz

V3

NC
NC

Positive

Vcc
Vss

C.

power

supply

V REF1

V REF1
V REF2
Vc ,

Vcz
V,

Cz Rz

NC
NC

C3

R3

C.

R.

V REF2
Vc,
Vcz
V,
Vz

Vz

R.
V3

V3

Ce ~ 1 JlF

R.

58
58

58

(1 )

Stetic Drive

(2)

1/2 Duty Cycle Drive

(3)

1/3 and 1/4 Duty Cycle Drive

Note: 1. When standby l]Iode is used, a transistor is required.
2. R2-R5 should be some kQ -some tens of kQ, and C2-C4 should be 0.1 JlF-0.3 JlF.
868

Figure 20

Example when External Drive Voltage is Used

HITACHI

HD61602/HD61603
Liquid Crystal Display Drive Voltage (HD61603)
As shown in figure 21, apply LCD drive voltage from the external power supply.

Oscillation Circuit
When Internal Osclllation Circuit is Used

When External Clock is Used

When the internal oscillation circuit is used,
attach an external resister Rosc as shown in
figure 22. (Insert Rosc as near chip as possible,
and make the OSCl side shorter.)

When an external clock of 100 kHz with
CMOS level is provided, pin OSCI can be used
for the input pin. In this case, open pin OSC2.

c. 1
Positive power ----1~.......-1-11 VDO
supply
Vss

SB

Note: When standby mode is used, a transistor is required.

Figure 21

Example of Drive Voltage Generator

801
OSC,

....

Rose

Rose
791
OSC2

801
OSC,

791
OSC2

HD14049UB
etc.

801
OSC,

~IC

79

osc 2

Multichip operation

Figure 22

Example of Osclllation Circuit

HITACHI

869

HD61602/HD61603
Applications

+ 5V

lll HD~3:

A"

~::

A
Address bus

0,"

r.:L>

::

&.......:!:

Data bus

Do

:;

~

f

Do

I

E
BA

R/W

©

~ / I~ II:! I~ ~~
W

if

Vee :-- +5V

v..

II

+5V

~

I
0 0 -0, u OSC2

~

Voo

VAEF1

VREF2

READY
SB

HD61602

Vss

Vel

+5V

HV

-.

I

---- SEGso

V_-

Voo

HD61602

Vss

+5V

~

V"EF2 _

(I)

f~~DY

V2
V3

I

~

CPU

~l
I
:-t
'"
"'~/ ~ •• >~.-",~'=

Vt

COMo
VC2 COM, SEGo

HD6B09

I

v,

II-

V,

V"
Va

5EG,--------- - SEG50

--------

---------

--------

---------

:t

V,

"
)

Uquid crystal

Figure 23

Example (1)

HD74LS138
5Vl11

r-A
B

3

,

C

Address bus
0,"

Data bus

Do
BA
R/W

[bJ

Vcc V..

I1r-

HD6809
CPU

F;
E;
C--

-p
t

Do

rl/ I~I I I~ ~ I
+5V

rf

II:!

Voo

U)

~~

0

0

lr=

V,

HD61603

'"

.':"':
+5V
HDl404BI'

r

~

SEGo - - - - - - SEG o

r

~

f

I I

V eo

~~

I

I~II:! lu ~
'

iii

,....,
0 0 -0,

~~

DY
HD61603

-------.

-------

---------

Example (2)

HITACHI

V,

SEGo - - - - - - - SEG"

------

Figure 24

870

~ '"~

READY

COM
+5V

0 0 -0,

)

HD61604/HD61605--(Segment Type LCD Driver)
Description

Features

The HD61604 and the HD61605 are liquid
crystal display driver LSIs with TTL and
CMOS compatible interface. E:ach of the LSIs
can be connected to various microprocessors
such as the HMCS6800 series.

•

Low current consumption
-Can drive from a battery power supply
(100 J.lA max on 5 V).
-Standby input enables a standby operation at lower current consumption (5
J.lA max on 5 V).

Several types of liquid crystal displays can be
connected to the HD61604 according to the
applications because of the softwarecontrolled liquid crystal dispay drive method.
The HD61605 is a liquid crystal display driver
LSI only for static drive and has 64 segment
outputs that can display 8 digits per chip.

Ordering Information
Type No.

Package

HD61604R
HD61605R

80-pin plastic QFP(FP-80)

VersatUe Segment Driving Capacity
Type No.

Drive Method

Display
Segments

HD61604R Static
51
1/2 bias 1/2 duty cycle 102
1/3 bias 1/3 duty cycle 153
1/4 duty cycle 204
HD61605R Static
64

Example of U.
8 segments x 6 digits + 3 marks
8 segments x 12 digits + 6 marks
9 segments x 1 7 digits
8 segments x 25 digits + 4 marks
8 segments x 8 digits

HITACHI

F_FNqIHI)
atfoM=100kHI

98
195
521
781
98

871

HD61604/HD61605
Pin Arrangement
HD61605R

HD61604R
-N,ucB _NC't.,ut.,,.. ••

2::~

~~~~~~~~~~~~~~~~
" " II II II II " II II II II

n ILlLJL

v•• ='

REA~=:
WE ::.

'RE"

58=="
03 7
02
0,1",
Do ~,o
V.. I- "

E.

V3~12

~~~~F= ::

C"
c:

5EG82
5EG81
5EG.. '
5EG..
5EG ••
SEG.,
5EG ..
5EG ..
5EG ..
5EG.3

18

"
18

II " II " II II H II "

(Top View)

JJJJJJJJJJJJJJJJ
WWWWWUlwwwwwwwwww
en
menU') en
uun en en
(I) (I) U')

872

HITACHI

Cf)

C/)CI)

C/)

HD61604/HD61605
Block Diagram
HD61604
SYNC~

________________________________,

LCD drive
timing
generator
READY_....q.._--,

Common output
(4 lines)

RAM write
timing generator

Parallel/serial
converter

Segment output
(51 lines)

Address
decoder

LCD drive
voltage

Drive
voltage
selection

Figure 1 HD61604 Block Diagram
HD61605

LCD drive
timing
generator

Common
output

RAM write
timing generator

Parallel/serial
converter

SB-~--<-

Address
decoder

Segment
output
(64 lines)

Figure 2 HD61605 Block Diagram

HITACHI

873

HD61604/HD61605
Pin Functions
Table 1 shows the HD61604 pin description.
Table 2 shows the HD61605 pin description.

Von: Positive power supply.
Vss: Negative power supply.

HD61604 Pin Function
HD61605 Pin Function
READY (Ready): During data setting in the
display data RAM and mode setting latch in
the LSI after data transfer, low is output to
the READY pin to inhibit the next data input.
There are two modes: one in which low is
output only when both of CS and RE are low,
and the other in which low is output regardless of CS and RE.
CS (Chip Select): Chip select input. Data can
be written only when this pin is low.

READY (Ready): During data setting in the
. display data RAM and mode setting latch in
the LSI after data transfer, low is output to
the READY pin to inhibit the next data input.
There are two modes: one in which low is
output only when both of CS and RE are low,
and the other in which low is output regardless of CS and RE.

CS (Chip Select): Chip select input. Data can
be written only when this pin is low.

WE (Write Enable): Write enable input.
Input data of Do to D, is latched at the positive

WE (Write Enable): Write enable input.

edge of WE.

Input data of Do to D3 is latched at the positive edge of WE.

RI!: (Reset): Resets the input data byte
counter. After both of CS and RE are low, the
first data is recognized as the 1st byte data.
SB (Standby): High level input stops the LSI
operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
Do-D7 (Data Bus): Data input pin from
which 8-bit x 2-byte data is input.
SYNC (Synchronous): Synchronous input
for 2 or more chip applications. LCD drive
timing generator is reset by high input. LCD
is off.

COMo-COlllh(Common): LCD common
(backplate) drive output.
SEoo -SEollO (Segment): LCD segment
drive output.
VI, V2, V3 (LCD Voltage): Power supply for
LCD drive.
OS01, OSC2 (Oscillator): Attach external R
to these pins for oscillation. An external clock
(100.kHz) Oan be input from OSC1.

RE (Reset): Resets the input data byte
counter. After both of CS and RE are low, the
first data is recognized as the first byte data.
SB (Standby): High level input stops the LSI
operations.
Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.

1.

Do-D3: Data input pin from which 4-bit x 4byte data is input.
SYNC (Synchronous): Synchronous input
for 2 or more chips application. LCD drive
timing generator is reset by high input. LCD
is off.
COMo (Common): LCD common (backplate)
drive output.
SEoo -SEoa (Segment): LCD segment
drive output.
OSC1, OSC2 (Oscillator): Attach external R
to these pins for oscillation. An external clock
(100 kHz) can be input from OSC1.
V3 (LCD Voltage): Power supply input for
LCD drive.

Vet, Vea: Do not connect any wire.
VIIBPI.: Connect this pin to Vl pin.

Voltage between Voo and V3 is used as drive
voltage.

Vaua: Hold at Voo level.

Vss: Negative power supply.

874

HITACHI

HD61604/HD61605
VDD: Positive power supply.

Table 1

Table 2

HD61604 Pin Description

HD61605 Pin Description

Pin

No.of

Connected

Pin

No.of

Connected

Name

Lines Input/Output
NMOS open
drain output
Input
Input
Input
Input
Input
8

to
MCU

Name

to
MCU

MCU
MCU
MCU
MCU
MCU

CS
WE
RE
SB

Lines Input/Output
NMOS open
drain output
Input
Input
Input
Input
Input
4

MCU
LCD

SYNC

MCU
LCD

READY
CS
WE
RE
SB

Do-I>]
COMoCOMa

4

Input
Output

SEGoSEGso

51

Output

Vl,V2,V3
OSC1,
OSC2

3
2

VC1, VC2

2

Output

SYNC

READY

Do-D3

MCU
MCU
MCU
MCU
MCU

COMo

1

Input
Output

SEGo-SEG63
OSC1,
OSC2

64

Output

LCD

LCD

2

Input, output

External R

Power supply

External R

V3

Input

Input, output

External R

Power
supply

Vss

Power supply

Voo

Power supply

VREFl

Input

Vl

VREF2

Input

Voo

Voo

Power supply

Vss

Power supply

Note: Logic polarity is positive.
1 = high = active.

Note: Logic polarity is positive.
1 = high = active.

HITACHI

875

HD61604/HD61605
Display RAM
timings of a common output and a segment
output. The same common address data is
simultaneously read. The data of display RAM
is reproduced on the LCD panel.

HD61604 Display RAM
The HD61604 has an internal display RAM
shown in figure 3. Display data is stored in
the RAM, or is read according to the LCD
drive timing to display on the LCD. One bit of
the RAM corresponds to 1 segment of LCD.
Note that some bits of the RAM cannot be
displayed depending on LCD drive modes.

The following shows the correspondence
between the 7-segment type LCD connection and the display RAM in each mode.
1.

Static Drive: In static drive, only the
column of COMo of display RAM is output.
COMl to COM3 are not displayed (figure

Reading Data from HD61604 Display
RAM

4).

A display RAM segment address corresponds
to a segment output. The data at segment
address SEGn is output to segment output
SEGn pin.

2.

A common address corresponds to the output

1/2 Duty Cycle Drive: In the 1/2 duty
cycle drive, the columns of COMo and
COM 1 of display RAM are output in time
sharing. The columns of COM2 and
COM3 are not displayed (figure 5).

Common address
(COM o-COM 3 )

I! {!L..---_ _

D_iSPlay_RAM_ _- - - J

,

J
T

51 bits
Segment address (SEGo-SEGso)

Figure 3

Display RAM (HD61604)

LCD connection
Display RAM
COM3
COM2
COM,
COMo

Figure 4
876

f

e

d

c

DP

g

b

a

Example of Correspondence between LCD Connection and Display RAM
(Static Drive, HD61604)

HITACHI

HD61604/HD61605
3.

1/3 Duty Cycle Drive: In the 1/3 duty
cycle drive, the columns of COMo to COM
2 are output in time sharing. No column of
COM3 is displayed. "y" cannot be rewritten by display data (input on an B-segment basis). Please use bit manipulation

in turning on/off the display of "y" cycle
(figure 6).
4.

1/4 Duty Cycle Drive: In the 1/4 duty
cycle drive, all the columns of COMo to
COM3 are displayed (figure 7).

LCD connection

a

Display RAM

COM,

a

COMo

9

c

b

e

d

DP

... (!l"'
w
w
(/)
(/)

(!l

Figure 5

Example of Correspondence between LCD Connection and Display RAM
(1/2 Duty Cycle, HD61604)
LCD connection
Display RAM
COM 3

..,

...

(!l

(!l

(/)

(/)

Figure 6

Y

a

b

COM,

f

9

c

COMo

e

d

DP

c5
w

w

w

/ V/

COM 2

(/)

Example of Correspondence between LCD Connection and Display RAM
(1/3 Duty Cycle, HD61604)
LCD connection
a

N

..,

(!l

(!l

w
(/)

Figure 7

~-------COM3

Display RAM
COM 3

f

a

COM 2

9

b

COM,

e

c

COMo

d

DP

w
(/)

Example of Correspondence between LCD Connection and Display RAM
(1/4 Duty Cycle, HD61604)

HITACHI

877

HD61604/HD61605
Writing Data Into 8D61604 Display RAM

4. 1/3 Duty Cycle Display Mode: S-bit
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/3
duty cycle drive.

Data is written into the display RAM in the
following five methods:
1.

Bit Manipulation: Data is written into
any bit of RAM on a bit basis.

2.

Static Display lIIIode: S-bit data is written on a digit basis according to the 7segment type LCD pattern of static drive.

3.

S. 1/4 Duty Cycle Display Mode: S-bit
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/4
duty cycle drive.
The RAM area and the allocation of the segment data for 1-digit display depend on the
drive methods as described in the section of
"Reading Data from Display RAM".

1/2 Duty Cycle Display Mode: S-bit
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/2
duty cycle drive.

(1)

(2)

Static

COMoCOM,COM2

S-bit data is written on a digit basis corresponding to the above duty drive methods.
The digits are allocated as shown in figure S.

(3)

1/2 Duty Cycle
Display

COMoCOM ,COM2

SEG o

SEGo

SEG,

SEG,

SEG,

SEG2

SEG2

SEG2

SEG 3

SEG3

SEG3

SEG4

SEG4

SEG4

SEGs

SEGs

SEG6

SEG e

SEG e

SEGe

SEG 7
SEGs

SEG 7

SEG7

SEG s

SEGs

SEGg

SEGg

SEGg

SEG,o

SEG,o

SEG"

SEG"

SEG12

SEG12

SEG 13

SEG'3

SEG'4

SEG'4

SEG'4

SEG'6

SEG'6

SEG'5

SEG'7

SEG'7

SEG17

AdO

1--+--+--1/
Ad1

1-+--+---1
Ad2

1-+--+--1'
Ad3

1--+--+---1/

SEG,s

~--"-""""

Figure 8
878

AdO

SEG,
SEG2

Ad1

SEG3
SEG4

Ad2

SEG6
SEG6

Ad3

SEG7
SEGs

Ad4

SEGg
SEG,o

AdS

SEG"
SEG'2

Ad4

1-+--+--1
AdS

I---il--l--t

SEG60

Ad6
Ad16

Ad6

SEG'3
SEG'4

Ad7

SEG'6
SEG,e

AdS

SEG17
SEG'8

SEG60

Allocation of Digits (8D61604)

HITACHI

1/4 Duty Cycle
Display

COMoCOM ,COM2COM3

SEGo

SEG'6

SEG60

(4)

COMoCOM ,COM2COM 3

SEGo

SEG"

1/3 Duty Cycle
Display

"-

Ad24
Ad2S

HD61604/HD61605
As the data can be transferred on a digit basis
from a microprocessor, transfer efficiency is
improved by allocating the LCD pattern
according to the allocation of each bit data of
the digit in the data RAM.

However, when the digit address is Ad6 of
static, Ad12 of 1/2 duty cycle, or Ad25 of 1/4
duty cycle, display RAM does not have
enough bits for the data. Thus the extra bits
of the input 8-bit data are ignored.

Figure 8 shows the digit address (displayed
as Adn) to specify the store address of the
transferred 8-bit data on a digit basis.

In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, 1-bit display data, a segment address (6 bits)s and a common address
(2 bits) should be specified.

Figure 9 shows the correspondence between
each segment in an Adn and the 8-bit input
data.

HD61605 Display RAM

When data is transferred on a digit basis, 8bit display data and digit address should be
specified as desCribed above.

(1 ) Static Display

(2)

1/2

Duty Display

COMo
SEGs

Bit
7

SEGsn+,

6

SEG8n+2

5

SEG8n+3

4

SEGSn +4

3

SEG8n+s

2

The HD61605 has an internal display RAM as
shown in figure 10. Display data is stored in
the RAM and output to the segment output
pin.

(3)

1/3

COMo COM,COM2

COMo COM,
SEG 4n

SEG4n+2

Bit
7

6

SEG3n

5

4

3

2

1

Bit
0

(4)

1/4

Duty Display
8it
7

6

SEG3n+'

5

4

3

SEG3n+2

2

1

Bit
0

Duty Display

COMo COM, COM2 COM 3

SEG8n+6
SEGSn+7
SEG2n+,

Figure 9

Bit
7

6

5

4

3

2

1

Bit
0

Bit Assignment in an Adn (HD61604)

1 b·t

.

(C~M~{tt::::::::::::::::::::D:i:sP:la~~:R=A=M==::::::::::::::::::::~J
64 bits
Segment address (SEGo-SEG83)

Figure 10

Display RAM (HD61605)

HITACHI

879

HD61604/HD61605
Reading Data from H061606 Display
RAM
Each bit of the display RAM corresponds to
an LCD segment. The data at segment
address SEGn is output to segment output
SEGn pin. Figure 11 shows the correspondence between the 7-segment type LCD
connection and the display RAM .

Writing Data Into H061606 Display RAM
Data is written into the display RAM in the
following two methods:
1.

Bit lIIan1pulatlon: Data is written into
any bit of RAM on a bit basis.

2. Static Display Mode: 8-bit data is written on a digit basis according to the 7segment type LCD pattern of static drive.
The 8-bit data is written on a digit basis into
the digit address (displayed as Adn) shown in
figure 12. When data is transferred from a
microprocessor, four 4-bit data are needed to
specify the digit address and an 8-bit display
data. Figure 13 shows the correspondence
between each segment in an .Adn and the
transferred 8-bit data.
In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, 1-bit display data and a
segment address (6 bits) should be specified.

LCD connection

Display RAM

Figure 11

980

Example of Correspondence between LCD Connection and Display RAM
(H061606)

HITACHI

HD61604/HD61605

COMo
SEG o
SEG,

COMo

SEG2
SEGsn

SEG3 AdO

Bit
7

SEG4
SEG6
SEG6
SEG 7
SEG s

SEG46
SEG46
SEG47
SEG4S

SEG9

SEG 49

SEG60
SEG,o
SEG I1 Ad1 SEG 6, Ad6
SEGs2
SEG'2
SEG63
SEG'3
SEG'4

SEGS4

SEG'5
SEG'6
SEG 17
SEG,s

SEGS6
SEG 66
SEG67
SEGss

SEGsn+,

6

SEGSn+2

5

SEGSn+3

4

SEGsn+4

3

SEGsn +s

2

SEGSn +6

SEG'9 Ad2 SEG69 Ad7
SEG 60
SEG20
SEG 6,
SEG2,
SEG62
SEG22
SEGS3
SEG23
SEG24

Figure 12 Allocation of Digits
(HD61605)

Figure 13 Bit Assignment in an Adn
(HD 61605)

HITACHI

881

HD61604/HD61605
Operating Modes
HD61604 Operating Modes

• 1/2 duty cycle display mode: 8-bit data
is written into the display RAM according to the digit in 1/2 duty cycle drive.

The HD61604 has the following operating
modes:

• 1/3 duty cycle display mode: 8-bit data
is written into the display RAM according to the digit in 1/3 duty cycle drive.

LCD Drive Mode: Determines the LCD

1.

drive method.

· 1/4 duty cycle display mode: 8-bit data
is written into the display RAM according to the digit in 1/4 duty cycle display
drive.

· Static drive mode: LCD is driven
statically.
• 1/2 duty cycle drive model LCD is driven
with 1/2 duty cycle and 1/2 bias.

READY Output Mode: Determines the

3.

READY output timing.

· 1/3 duty cycle drive mode: LCD is driven
with 1/3 duty cycle and 1/3 bias.

After a data set is transferred. the data is
processed internally. The next data cannot be aclmowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:

• 1/4 duty cycle drive mode: LCD is driven
with 1/4 duty cycle and 1/3 bias.

Data Display Mode: Determines how to
write display data into the data RAM.

2.

• Static display mode: 8-bit data is written into the display RAM according to
the digit in static drive.

• READY is always available (figure 14).
• READY is made available by CS and RE
(figure 15).

,'----

______-.J/

II

WE~
"~

READY

:'-./
I

__________________________-.J11

I

I
I
I

I

I

____
....
I . _ - - - - - - - ' n p u t i n h i b i t - - - - -..........
-!I

Data transfer

I

period

I

.od

~ Next data
I
transfer

Figure 14 READY Output Timing (When It Is Always Available)

-------/
\.

,-....

"--/

A

"--/ i

~

/

I

II

I

,I

I

":

READY-------------+I----------~~

f

/1

,'------,--\.

I'

"-./
I
/1
I

~--~I----~
I
'----Y
~,
I
I
I
Data transfer - -..."'I...I - - - - - - - - ' n p u t i n h i b i t - - - - - -...-+I----1'I"'-- Next data
period

: ~r--------~I

period

Figure 15 READY Output Timing (When It Is Made Available by
882

HITACHI

transfer
~

and 1m)

HD61604/HD61605
4.

After a data set is transferred, the data is
processed internally. The next data cannot be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:

LCD Off Mode: In this mode, the
HD61604 stops driving the LCD and turns
it off.

The above 4 modes are specified by mode
setting data. The modes are independent of
each other and can be used in any combination. The bit manipulation is independent of
data display mode and can be used regardless of it.

. READY is always available (figure 16).
. READY is made available by CS and RE
(figure 17).

HD61605 Operating Modes
The HD61605 has the following operating
modes:
1.

2. LCD Off Mode: In this mode, the
HD61605 stops driving the LCD and turns
it off.

READY Output Mode: Determines the
READY output timing.

\'1--

--------'/

I

~

1
I

/1

READY - - - - -....,

I

~I-------------~

1
I
I
Data transfer-----ili"'---------Input i n h i b i t - - - - - -....ooIl
period
period

I
I

I - - Next data
transfer

Figure 16 READY Output Timing (When It is Always Available)

cs

r-

/

~I

WE

RE

I
I

READY

I
I
I
I

Data transfer
period

-I"

\,

/

I

~

I
1

"

I

I

I

1

I

1

/

\I

I

I

"----Y

'--./1

Input inhibit
period

I

"I

I

1
I
I

I
I
I
I

t-- Next data
transfer

Figure 17 READY Output Timing (When It is Made Available by CS and RE.)

HITACHI
-----

883

------.----_._--- - - - - -

HD61604/HD61605
Input Data Formats
3.

HD61604 Input Data Formats
Input data is composed of 8 bits x 2 bytes.
Input them as 2-byte data after READY output changes from low to high or low pulse
enters into RE pin.

Mode Setting Data:
1st byte

7

1.

Display Data: Updates display on an 8segment basis.

5

4

3

2

1

7

o

7

6

5

o

432

· Display address: Digit address Adn in
accordance with display mode
· Display data: Pattem data written into
the display RAM according to display
mode and the address
2.

Bit Manipulation Data: Updates display
on a segment basis.
1st byte

I~=ayl x x x ;~~I

0

I I
7

6

5

4

5

4

3

2

1

0

2nd byte

S~G ad~ress :

IxI xI
7

6

3

2

4

3

2

1

0

6

5

4

3

2

1

0

Note: Input the same data to display mode bits
and drive mode bits.
4.

o

• Display data: Data written into 1 bit of
the specified display RAM
• COM address: Common address of display RAM
· SEG address: Segment address of display RAM
.

884

5

· Display mode bits:
00: Static display mode
01: 1/2 duty cycle display mode
10: 1/3 duty cycle display mode
11: 1/4 duty cycle display mode
• OFF/ON bit:
1: LCD off (set to 1 when SYNC is
entered)
0: LCD on
· Drive mode bits:
00: Static drive
01: 1/2 duty cycle drive
10: 1/3 duty cycle drive
11: 1/4 duty cycle drive
· READY bit:
0: READY bus mode: READY outputs 0
only while CS and RE are 0 (reset to
o when SYNC is entered)
1: READY port mode: READY outputs
o regardless of CS and RE

2nd byte

I :

6

I~EADY~~ve :model

xl x I x x I x ~:F/OJ ~:~bQ I

~~Pla~ add~ ;
(Digit address Adn!
6

xI0

2nd byte

1st byte

7

0

HITACHI

I-Byte Instruction: The first data (first
byte) is ignored when the bit 6 and bit 7
in the data are 1.
tst byte

HD61604/HD61605
HD61605 Input Data Formats

3.

I :
3

Display Data: Updates display on an 8-

0

3

2

x

x

x

0

3

4

Bit3

Display address
(Digit address Adn)

Display data

6

3

2

o

o

2.

5

0

3

o

Display data
1
0
2

2

x

l~i~DYI

0

3

2

o

0

Display address: Digit address Adn
shown in figure 12.
Display data: Pattern data written into
the display RAM as shown in figure 13.

Bit Manipulation Data: Updates display

4.

x : x
0

4th byte

x : x : x

3rc! byte
Bitl7

2

0

I II
II

320

0

2

x

<

I

1st byte

0

0

3rd byte

segment basis.

I :

2nd byte

1st byte

Input data is composed of 4 bits x 4 bytes.
Input them as four 4-bit data after READY
output changes from low to high or low pulse
enters into RE pin.

1.

Mode Setting Data:

x

~~F/ONI

3

2

0

o
o

OFF ION bit:
1: LCD off (It is set to 1 when SYNC is
entered)
0: LCD on
READY bit:
0: READY bus mode: READY outputs 0
only while CS and RE are 0 (reset to 0
when SYNC is entered)
1: READY port mode: READY outputs 0
regardless of CS and RE

1- Byte Instruction: The first data (4
bits) is ignored when the bit 3 and bit 2 in
the data are 1.

on a segment basis.
1st byte

I : I
3

2

o

3

Bit3

3
o

o

2

o

3

3

o

2

2

x

>I
0

SEG address
2
1
0

2

1

0

Display data: Data written into the 1 bit
of the specified display RAM.
SEG address: Segment address of display RAM (segment output).

HITACHI

885

HD61604/HD61605
How to Input Data
How to Input Data into HD61604

1.

Input data is composed of 8 bits x 2 bytes.
Take care that the data transfer is n:ot interrupted because the first 8-:bit data is distinguished from the second one by the sequence
only.
When data transfer is interrupted, or at
power on; the following two methods can be
used to reset the count of the number of
bytes (count of the first and second bytes):

Set CS and RE to low (no display data
changes).
2. Input 2 or more 1-byte instruction data
whose bit 7 and 6 are high (display data
may change).

The data input method via data input pins
(CS, WE, Do to D7) is similar to that of static
RAM such as HM6116. Access to the LSI can
be made through the same bus line as ROM
and RAM. When output ports of a microprocessor are used for access, refer to the
timing specifications and figure 18.

Power on

~

,r----------~~~

______

WE

,r-*-6--------~~--~

RE

~~*4

-Jlr---------~\____~'r------~\~

_____J,___

READY f'::::::J'''''-*-1--~li~~:Jr.*~3~--"'"\L-.Jr--------"'"\~
*5
*5
SYNC

__________~n~---------------Jr-\~*-2---------------------1/

58

1st 2nd
1st 2nd
1st 2nd
00-0 7 ~~C::x[::JxC::::::::::Xx::]x::jX(:::::::Jxt::xx::ix::=
Mode setting data
Mode setting data
'Display data

*1 : READY output is indefinite during 12 clocks after the oscillation starts at power on (clock:
OSC2 clock).

*2: High pulse should be applied to SYNC pin when using two or more chips simultaneously.

*3: In the mode in which READY is always available, READY output is indefinite while high
is being applied to SYNC.
*4: Reset the byte counter after power on.
5: READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated.
6: Connect a pull-up resistor if WE or RE is floating.
*7: It is not always necessary to follow this example.

*

*

Figure 18 Example of Data Transfer Sequence

886

HITACHI

HD61604/HD61605
How to Input Data into HD61605

1.

Input data is composed of 4 bits x 4 bytes.
Take care that the data transfer is not interrupted because the first 4-bit data to the
fourth 4-bit data are distinguished from each
other by the sequence only.

2.

When data transfer is interrupted, or at
power on, the following two methods can be
used to reset the count of the number of data
(count of the first 4-bit data to the fourth 4bit data):

Set CS and RE to low (no display data
changes.)
Input 4 or more 1-byte instruction data
(4-bit data) whose bit 3 and 2 are high
(display data may change).

The data input method via data input pins
(CS, WE Do to D3) is similar to that of static
RAM such as HM6116. Access to the LSI can
be made through the same bus line as ROM
and RAM. When output ports of a microprocessor are used for access, refer to the
timing specifications and figure 19.

Power on

~r------~I~~________Jfr------~\~____-Jfr----~\~____-JrWE

'*6

RE

~~*-4----------------------------------------

----r-----f5
~\' __7
READY [ ___
J
..
*1
*5
*3
SYNC ________~1~!~--------------~{\~*~2~----------------------

S8

f)

1st 2nd 3rd 4th

0 0 -0 3 -Q-sr---<'-....e.X~X~X~X"--

Mode setting data

1st 2nd 3rd 4th

1st 2nd 3rd 4th

__....e.X~X~X:.....LlX.....cX'--_---LXll.......cXIo......cX~Xo.....oXo....
Mode setting data

Display data

* 1 : READY output is indefinite during 12 clocks after the oscillation starts at power on (clock:
OSC2 clock).
* 2: High pulse should be applied to SYNC pin when using two or more chips simultaneously.
3: In the mode in which READY is always available, READY output is indefinite while high
is being applied to SYNC.
*4: Reset the 4-bit data counter after power on.
* 5: READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated.
* 6: Connect a pull-up resistor if WE or RE is floating.
* 7: It is not always necessary to follow this example.

*

Figure 19 Example of Data Transfer Sequence

HITACHI

887

HD61604/HD61605
Notes on READY Output
Note that the READY output will be unsettled during 1.5 clocks (max) after inputting
the first 2-byte data for setting the mode
after turning the power on. This is because
the READY bit data of mode setting latches
and the mode of READY pin (READY bus or
port mode) are unsettled untill the completion of mode setting.
There are two kinds of the READY output
waveforms depending on the modes.

1.

READY bus mode (READY bit = 0)

2.

READY port mode (READY bit = 1)

However, if you input SYNC before mode
setting, waveform will be determined; when
you choose READY bus mode, (1) a in figure
20 will be output, and when .you choose
READY port mode, (2) a will be output. The
figures can be applied both to HD61604 and
HD61605.

Power on,

~
DO-D7r-------------------------<==1~s~t==><=~2~nd~~~~~~~=:::~~:::

~, READY output is unsettled.
Mode setting data
/Jl
(2 -byte data) ~ 1 . 5 .clocks (max)

V

Mode setting latch is unsattled.
Mode setting data
are latched .

Power on

•

/
\

a

\.--------___L __ J

READY

Note; CS = low
(1)

/

--

READY Bus Mode .1.5 clocks (max)

Power on

~
I
a
\ __b____

READY

Nota; CS

= low,

RE
(2)

----"'\
I

= high

1 .5 clocks (max)

READY Port Mode

3.5 clocks (max)

Figure 20 READY Output According to Modes
888

HITACHI

I

HD61604/HD61605
Standby Operation
Standby operation with low power consumption can be activated when pin SB is
used. Normal operation of the LSI is activated
when pin SB is low level, and the LSI goes
into the standby state when pin SB is high
level. The standby state of the LSI is as follows:
1.
2.

LCD driver is stopped (LCD is off).
Display data and operating mode are

3.

4.

held.
The operation is suspended while display
changes (while READY is outputting
low.) In this case, READY outputs high
within 10.5 clocks or 3.5 clocks after
release from the standby mode.
Oscillation is stopped.

When this mode is not used, connect pin SB to
Vss.

Multi Chip Operation
When an LCD is driven with the two or more
chips, the driving timing of LCD must be
synchronized. In this case, the chips are
synchronized with each other by using SYNC
input. If SYNC input is high, the LCD driver
timing circuit is reset. Apply high pulse to the
SYNC input after the operating mode is set.
A high pulse to the SYNC input changes the
mode setting data. (The OFF ION bit is set
and the READY bit is reset. See (3) Mode
Setting Data in "Input Data Formats".) Transfer the mode setting data into the LSI after

every SYNC operation.
If a power on reset signal is applied to the
SYNC pin, the LCD can be off-state when the
power is turned on.

When SYNC input is not used, connect pin
SYNC to Vss.
When SB input is used, after standby mode is
released, high pulse must be applied to the
SYNC input, and mode setting data must be
set again.

Restriction on Usage
Minimize the noise by inserting a noise bypass capacitor (G 1 pF) between Voo and
Vss pins. (Insert one as near chip as possible.)

Liquid Crystal Display Drive Voltage CirCUIt (HD61604)
What is LCD Voltage?

ce it supplies the voltage to the LCD drive
circuit of HD61604.

HD61604 drives liquid crystal display using
four levels of voltages (figure 21); Voo, Vl, V2,
and V3 (Voo is the highest and V3 is the
lowest). The voltage between Voo and V3 is
called VLCO and it is necessary to apply the
appropriate VLCO according to the liquid
crystal display. V3 always needs to be supplied regardless of the display duty ratio sin-

Connecting R2 - R5 in series between Voo
and Vss (figure 22) generates Il.V or VLCO by
using the resistance ratio to supply these
voltage to pins VI, V2, V3. C2-C4 are the
smoothing capacitors. Connect a trimmer
potentiometer for R5 and change its resistance value to control the contrast.

HITACHI

889

HD61604/HD61605

Voo

Figure 21

LCD Output Waveform and
Output Levels (1/3 Duty
Cycle, 1/3 Bias)

Positive

Voo
Vss

C.

power

supply

Positive

Vee
Vss

C,

power

supply

VREF2
Ve ,
Ve,
V,
V,
V,

C.

Vee
Vss

C.

V REF1
V REF2

V REF l

R,

Positive
power

supply

R,
C,

NC
NC

VREFl

Ve,
Ve,

NC
C, R,

NC

V,
Ra

Ca

Ra

C.

R,

V,

R,

VAEF2
Ve ,
Ve ,
V,
V2

Ca
Va

Va

Cs ;;: 1pF

R.

SB
SB

SB

(1)

Static Drive

(2)

1/2 Duty Cycle Drive

(3)

1/3 and 1/4 Duty Cycle Drive

Note: 1 When standby mode is used, a transistor is required.
2 R2-R5 should be some kO-some tens of kO, and C2-C4 should be 0.1 )iF-0.3 )iF.

Figure 22 Example when External Drive Voltage is Used

890

HITACHI

HD61604/HD61605
Liquid Crystal Display Drive Voltage (HD61605)
As shown in figure 23, apply LCD drive voltage from the external power supply.

Oscillation Circuit
When Internal Oscillation Circuit is
Used

When External Clock is Used
When an external clock of 100 kHz with
CMOS level is provided, pin aSCl can be used
for the input pin. In this case, open pin OSC2.

When the internal oscillation circuit is used,
attach an external resistor Rose as shown in
figure 24. (Insert Rose as near ehip as possible,
and make the OSCl side shorter.)

Cs
1
Positive power - - - - - - 1 - 1
1 Voo
supply
Vss

12 V3

SB

Note: When standby mode is used, a transistor is reauired.

Figure 23 Example of Drive Voltage Generator

Rose

Rose

v

ascI

aSC2

801 79[ HD14049UB
"--";;'a';'S~C:-:l-';"a;;JSL...C""'2-etc.

NC

ascI

79J

aSC2

Multichip operation

Figure 24 Example of Oscillation Circuit

HITACHI

891

HD61604/HD61605
Applications
+6V

-rn

A"

'"

:::

Add_bua

0,Do
E
SA

RNi

HD74LS138

r--_

A::

__

~::.-I~

G

Data bua

Qo

~bJ *.Lr
+5V

I

II

I' I~ I:I! I~ fi

1

Vee - + 5 V
V..

i,),

SB

V... ,

VREf'2

HD61604

C~Mo

V"COM,SEGo
HD6SOS

:g

CIJ

~ VU
Vel

...

00-0, ..,OSC2

>

VDO
Hr----iREADY

I

I

----SEG..

1/

HD14D49UB
+5V

I -

"1" f

LI
V1r- l-

SB
Vss
Vel

iI-~v

V3

>

IS

Voo
READY

v.

i'"

I I
I
II!' I:I! I~ fi Do -o,osc, osc.

Vo>

V .." [

en

VR£F2

HD616D4

VI

SEG,----------SEG..

v,
v,

.;sv

+6V

CPU

Uquid crysUIl

Figure 26 Example (1)
HD74LS13B

.,

5VID

Add_bus

-

Deblbuo

Do

SA

RNi
Vee

V..

~
I-

=rD

-

,.../

Do

~ rt (. I~

II

+5V

-....

:~

HD6809
CPU I

~

A
B
C

4

0,

r--

+6V

f

READY
SB'

v"
Ve,
Vo>
COM

r-;

I:I! If!

~

I
0 0 -0,

~ ~

HD61605

...

+6V

_~

HDI4D4~ /

r

v,

SEGo------ SEG,.

I

-------------

Figure 26 Example (2)

892

J

/'

HITACHI

v..

f~~

Ve,
Vo>

I~I:I!
Y

~

00 -

3

~
H061605

~~
v,

SEGo-- - - - - - SEG..

----------_ ... _---

)

HD61604/HD61605
Absolute Maximum Ratings
Item

Symbol

Power supply voltage *

Voo,

Pin voltage *

Limit

Unit

-0.3 to + 7.0

V

VT

-0.3 to Voo + 0.3

V

Operating temperature

Topr

-20 to +75

°C

Storage temperature

Tstg

-55 to +125

°C

v"

V2, V3

*Value referenced to Vss=O V.
Note: If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using
them within electrical characteristics limits is strongly recommended for normal operation. Use
beyond these conditions will cause malfunction and poor reliability.

Recommended Operating Conditions
Limit
Item

Symbol

Min

Power supply voltage *

Voo

Pin voltage *
Operating temperature

Topr

Typ

Max

Unit

4.5

5.5

V

0

Voo

V

0

Voo

V

-20

+75

°C

*Value referenced to Vss=O V.

HITACHI

893

HD61604/HD61605
Electrical Characteristics
DC Characteristics
(Vss = 0 V, VDD = 4.5 V to 5.5 V, Ta= -20 °C to +75 °C, unless otherwise noted)
Item
Input high voltage
Input low voltage
Output leakage
current
Output low
voltage
Input leakage
current
*1

LCD driver voltage
drop

Symbol Min
OSC1

VIHl

Others

VIH2

0.8Voo
2.0

OSC1

Limit
Typ

Max

Unit

-

Voo

V

Voo

V

Test Condition

0.2Voo V
0.8
V

VILl

0

Others

VIL2

0

READY

IOH

5

Il A

Pull up the pin to Voo

READY

VOL

0.4

V

IOL""O.4 mA

Input
pin

ItLl

-1.0

1.0

Il A

VIN=O to Voo

Vl

VIN=VOO to V3

ItL2

-20

20

Il A

V2, V3

IIL3

-5.0

5.0

COMo-COM3

Vdl

0.3

Il A
V

SEGo- SEG 5o

Vd2

0.6

V

100

100

"A

100

5

"A

Current consumption * 2

±ld=3 "A for each
COM, V3=VOO to 3 V
± Id = 3 "A for each
SEG, V3=VOO to 3 V
During display *
Rosc=360 kO
At standby

* Except the transfer operation of display data and bit data.
*1 Vl, V2: applied only to HD61604.
*2 Do not connect any wire to the output pins and connect the input pins to Voo or Vss.

894

HITACHI

HD61604/HD61605
AC Characteristics

= 0 V, VDD = 4.5 V to 5.5 V, Ta = -20'C to

(Vss

Symbol Min

+75 'C, unless otherwise noted)

Limit
Typ

Max

Unit

Teat Condition

Oscillation frequency

OSC2

fosc

70

100

130

kHz

Rosc=360 kO

External clock
frequency
External clock duty
I/O signal timing

aSC1

fosc

70

100

130

kHz

Duty

40
400

50

60

%
ns

Item

aSC1

ts
tH

10

ns

twH

300

ns

twL

400

ns

twR

400

ns
1.0

tOL

Input signal rise time and faU time

Figure 31

ps

ns

tEN

400

toP1

9.5

10.5

Clock

toP2

2.5

3.5

Clock

25

ns

tr. tf

For display
data transfer
For bit and mode
data transfer

CS
tWH

WE

V1H
V 1L
tWL

VIH

00-07

V 1L

ts

Figure 27

Write Timing (HE Is fixed high and SYNC low)

HITACHI

895

HD61604/HD61605

READY

Figure 28 Reset/Read Timing (CS and SYNC are fixed low)

READY
t------------tOP1,

tOP2--------~

Figure 29 READY Timing (When the READY Output is Always Available)

READY

_
SYNC

=1

t~]. ---~~~---~~~~~-Wit-h;"
V 1H

V1L

1 clock
V 1H

....- - - - - - - - - - - -

Figure 30 SYNC Timing

896

V
'"

HITACHI

HD61604/HD61605

.

VDD

47 kQ

10 kQ

Measurement
pin

(READY)
30 PFr

120 kQ

1S2074H

Vss

Figure 31 Bus Timing Load Circuit (LS-TTL Load)

HITACHI

897

HD61830/HD61830B--LCDC(LCD Timing Controller)
Description
The HD61830/HD61830B is a dot matrix liquid
crystal graphic display controller LSI that stores
the display data sent from an 8-bit microcontroller
in the external RAM to generate dot matrix liquid
crystal driving signals.

It has a graphic mode in which I-bit data in the
external RAM corresponds to the on/off state of 1
dot on liquid crystal display and a character mode
in which characters are displayed by storing character codes in the external RAM and developing
them into the dot patterns with the internal character generator ROM. Both modes can be provided
for various applications.
The HD61830/HD61830B is produced by the
CMOS process. Thus, combined with a CMOS
microcontroller it can complete a liquid crystal
display device with lower power dissipation.

• Operating frequency: 1.1 MHz HD61830
2.4 MHz HD61830B
• Low power dissipation
• Power supply: Single +5 V ±10%
• CMOS process

Differences between Products
HD61830 and HD61830B
HD61830
Internal or external

External only

Operating frequency

1.1 MHz

2.4 MHz

Pin arrangement
and signal name

Pin6:C
Pin 7: R
Pin 9: CPO

Pin6:CE
Pin 7:OE
Pin9:NC

Package marking
to see figure

®

@

Package Marking

o~

Features

3013 ----I1I-J:l:!?ot!..!N~o!:..
HD61830AOO

®

• Dot matrix liquid crystal graphic display controller
• Display control capacity
- Graphic mode: 512k dots (2 16 bytes)
-Character mode: 4096 characters (212 characters)
• Internal character generator ROM: 7360 bits
-160 types of 5 x 7 dot characters
- 32 types of 5 x 11 dot characters
Total 192 characters
-Can be extended to 256 characters (4 kbytes
max.) by external ROM
• Interfaces to 8-bit MPU
• Display duty cycle (can be selected by a program)
Static to 1/128 duty cycle
• Various instruction functions
- Scroll, cursor on/off/blink, character blink,
bit manipulation
• Display method: Selectable A or B types
• Internal oscillator (with external resistor and
capacitor) HD61830

898

HD61830B

Oscillator

JAPAN

o

o
®

•

3013

---~--IlI-J:l£ot!..!N~o!:..

H061830BOO
JAPAN

o

Ordering Information
Type No.

Package

HD61830AOOH

60-pin plastic QFP (FP-60)

------HD61830BOOH

HITACHI

HD61830/HD61830B
Pin Arrangement

CD

.,f

:!E

:!E

III

..,.

<
:!E
('t)

..r

~
:!E :!E

<.,f./f .(
:!E

:!E

:!E

N

0

01
III

CD
III

CD

:!E

,...
III

~~
:!E :!E

CD
III

III
. III

54

MAlO

(CE) C

53

MAll

(OE)R

52

MA12

CR

51

MA13

(NC) CPO

50

MA14

FLM

49

MA1S

eLI

48

O2

SYNC

47

01

46

CL2

WE

FP-60

RES

45

ROo

CS

44

RDl

E

43

RD2

RIW

42

RD3

RS

41

RD4

(top view)

MA

40

RDs

GND

39

RDs

DB7

38

RD7

DBs

37

MOo

DBs

MOl

...

CD

0

. rB m r3 ~

CD

0

0

0

0

0 r:!! rS 0 cS
:!E

:!E

:!E

:!E

:!E

N

0

:!E

( ) is for HD61830B

HITACHI
._------

---------------

899

- - - - - - - - - - - -

HD61830/HD61830B
Terminal Functions
Symbol

Pin Number

110

Function

DBo-DB7

2B-21

110

Data bus: Three-state 110 common terminal
Data is transferred to MPU through DBo to DB7"

OS
RtN

15

Chip select: Selected state with CS ... 0

17

ReadlWrite: RIW - 1: MPU 4- HD61830B
RIW. 0: MPU --+ HD61830B

RS

18

Register select: RS - 1: Instruction register
RS • 0: Data register

E

16

Enable: Data is written at the fall cif E
Data can be read while E is 1

CR

8

CR oscillator (HD61830), External clock input (HD61830B)

C

6

CR oscillator to capacitor (HD61830 only)

R

7

CR oscillator to resistor (HD61830 only)

CPO

9

0

Clock signal for HD61830 in slave mode (HD61830 only)

CE

6

0

Chip enable (HD61830B only)
CE .. 0: Chip enables make external RAM in active

OE

7

0

Output enable (HD61830B only)
OE .. 1: Output enable informs external RAM that HD61830B
requires data bus

NC

9

Open

Unused terminal. Don't connect any wires to this terminal
(HD61830B only)

MAo-MA15

4-1,
60-49

0

External RAM address output
In character mode, the lane code for external CG is output
through MA12 to MA15 (0: Character 1st line, F: Character 16th
line)

MDo~~

37~0

110

Display data bus: Three-state 110 common terminal

RDo-RD7

45-38

I

ROM data input: Dot data from external character generator is
input

WE

13

0

Write enable: Write signal for external RAM

Cl2

46

0

Display data shift clock for LCD drivers

Cl1

11

0

Display data latch signal for LCD drivers

FlM

10

0

Frame signal for display synchronization

MA

19

0

Signal for converting liquid crystal driving signal into AC, A type

MB

5

0

Signal for converting liquid crystal driving signal into AC, B type

Dl

47

0

D2

48

Display data serial output
D1: For upper half of screen
D2: For lower half of screen

~

12

110

Synchronous signal for parallel operation
Three-state I/O common terminal·(with pull-up MOS)
Master: Synchronous signal is output
Slave: Synchronous signal is input

RES

14

900

Reset: Reset

=0 results in display off, slave mode and Hp -

HITACHI

6

SYNC CLi MAMB FLM

(CE)

I
r---

n-

Dot counter
(DC)

Data

DBa-DB7 - + - I
CS

}

~~

RES

~

"0

~!!

::E:

f----

Data

hl~~

-l

.-+--i---.--+!---+ MDo-MD7
V

I ;=une address
6

~

I BU~Y I
flag

~

rl

4
Character
generator
ROM
(CGROM)

I

L---y

I

Instructionh

------- ------_ ..
:
_.:

counter

8

1

register
(IR)

;

RAM

Dot registers
(DR)

register
(DOR)

L..--

I

·L_. . . . ___

t

8

~

S2

I»

IrQ

I

J

.5

::E:

~
CO)

register I-(DIR)

;e II

(OE)

Refesh address 116
counter (1) if.""'-(RAC1)

f----

-=~

!

Cursor
signal
generator

I

IJ.

!

Extended
external
ROM

·------1--------

···
··
r-r-------RD~D7

Multiplexer

Control
signal

Control
signal

• 01

(

Oscillator
circuit

.~

s
~

I-'

e

LtC~
CL2

~

4Nv~

(CL2)
CPO

(CR)

• When extended external ROM is used, MAo-MA11
are applied to RAM, MA1rMA15 are applied to
extended external ROM.
( ) is for HD61830B

~

1:1
~

I-'

e

=
t:=

HD61830/HD61830B
Block Functions
Registers

Dot Counters (DC)

The HD61830/HD61830B has the five types of
registers: instruction register (IR), data input register (DIR), data output register (DOR), dot registers
(DR), and mode control register (MCR).

The dot counters are counters that generate liquid
crystal display timing according to the contents of
DR.
Refresh Address Counters (RACIIRAC2)

The IR is a 4-bitregister that stores the instruction
codes for specifying MCR, DR, a start address register, a cursor address register, and so on. The
lower order 4 bits DBo to DB3 of data buses are
written in it.
The DIR is an 8-bit register used to temporarily
store the data written into the external RAM, DR,
MCR, and so on.
The DOR is an 8-bit register used to temporarily
store the data read from the external RAM. Cursor
address information is written into the cursor
address counter (CAC) through the DIR. When the
memory read instruction is set in the IR (latched at
the falling edge of E signal), the data of external
RAM is read to DOR by an internal operation. The
data is transferred to the MPU by reading the DOR
with the next instruction (the contents of DOR are
output to the data bus when E is at the high level).
The DR are registers used to store dot information
such as character pitches and the number of vertical dots, and so on. The information sent from the
MPU is written into the DR via the DIR.
The MCR is a 6-bit register used to store the data
which specifies states of display such as display
on/off and cursor on/off/blink. The information
sent from the MPU is written in it via the DIR.
Busy Flag (BF)

The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot
be accepted. As shown in Control Instruction, read
busy flag, the busy flag is output on DB7 under the
conditions of RS = 1, R/W = 1, and E = 1. Make
sure the busy flag is 0 before writing the next
instruction.

902

The refresh address counters, RACI and RAC2,
control the addresses of external RAM, character
generator ROM (COROM), and extended external
ROM. The RACI is used for the upper half of the
screen and the RAC2 for the lower half. In the
graphic mode, 16-bit data is output and used as the
address signal of exterIlal RAM. In the character
mode, the high ordeJ;' 4 bits (MAlz-MA IS) are
ignored. The 4 bits of line address counter are output instead and used as the address of extended
ROM.
Character Generator ROM
The character generator ROM has 7360 bits in total
and stores 192 types of character data. A character
code (8 bits) from the external RAM and a line
code (4 bits) from the line address counter are
applied to its address signals, and it outputs 5-bit
dot data.
The character font is 5 x 7 (160 characters) or 5 x
11 (32 characters). The use of extended ROM
allows 8 x 16 (256 characters max.) to be used.
Cursor Address Counter
The cursor address counter is a 16-bit counter that
can be preset by instruction. It holds an address
when the data of external RAM is read or written
(when display dot data or a character code is read
or written). The value of the cursor address counter
is automatically increased by 1 after the display
data is read or written and after the set/clear bit
instruction is executed.

HITACHI

HD61830IHD61830B
Cursor Signal Generator

Parallel/Serial Conversion

The cursor can be displayed by instruction in
character mode. The cursor is automatically generated on the display specified by the cursor address
and cursor position.

The parallel data sent from the external RAM,
character generator ROM, or extended ROM is
converted into serial data by two paralleVserial
conversion circuits and transferred to the liquid
crystal driver circuits for upper screen and lower
screen simultaneously.

HITACHI

903

HD61830/HD61830B
Display Control Instructions
During the execution of the instruction, no new
instruction can be accepted. Since the busy flag is
set during this, read the busy flag and make sure it
is 0 before writing the next instruction.

Display is controlled by writing data into the
instruction register and 13 data registers. The RS
signal distinguishes the instruction register from
the data registers. 8-bit data is written into the
instruction register with RS = 1, and the data register code is specified. After that, the 8-bit data is
written in the data register and the specified
instruction is executed with RS =O.

Register

RIW

1. Mode Control: Code $"00" (hexadecimal)
written into the instruction register specifies the
mode control register.

RS

DB7

DBS

DBS

0

I DB4
I

DB3

Instruction reg.

0

1

0

0

Mode control reg.

0

0

0

0

Mode data

Cursorlblink

CG

DBS

DB4

DB3

DB2

DB1

DBO

1/0

VO

0

0

0

0

0

0

DB2fDB1

Cursor off
(!)

0

1

Cursor on

()

1

0

Cursor off. character blink

~

1

1

Cursor blink

0

0

0

1

Cursor on

1

0

Cursor off. character blink

1

1

Cursor blink

0

0

0

ru
c..

.!Il

0

1

0

~

u..
u..

Q
z

1

i

!2111

";;:
(I)

~

::E

I

111

(!)

~

()

..e

iii
.>J!

.5

as

0

2!

::J

()

..e(l)
Q.-o

!!!

0
(!)E

I

0

Character display
(Character mode)

iii

E

------

E
~
w

1: Master mode

1: Dis p lay ON
0: Display OFF

HITACHI

8
iii

E

~
w

/

I

0

Graphic/character
display

Cursor off

0: Slave mode

904

0

1 DBO

Graphic mode

HD61830IHD61830B
2. Set Character Pitch: Vp indicates the number
of vertical dots per character. The space between
the vertically-displayed characters is included in
the determination. This value is meaningful only
during character display (in the character mode)
and becomes invalid in the graphic mode.

FWJ

Register

RS

DB7
0

Instruction reg.

0

1

Character pitch reg.

0

0

IIp indicates the number of horizontal dots per
character in display, including the space between
horizontally-displayed characters. In the graphic
mode, the IIp indicates the number of bits of
I-byte display data 10 be displayed.
There are three IIp values (table 1).

I DB6

lOBS

I DB4

I o I o I
(Vp-1) binary

0

DB3

DB2

0

0

0

I DBl lOBO
I o I 1

(Hp - 1) binary

Table 1 Hp Values
Hp
6

7
8

DB2

DBl
0

DBO

Horizontal Character Pitch

1

6

0

7
8

HITACHI

905

---

~-~-------.~~

HD61830/HD61830B
3. Set Number of Characters: HN indicates the
number of horizontal characters in the character
mode or the number of horizontal bytes in the
graphic mode. If the total sum of horizontal dots on
the screen is taken as n,
Register

RNI

RS

DB6

o

Instruction reg.

0

1

0

0

0

0

Number-of-time-divisions
reg.

RS

DB7

DB6

1

0

o

0

0

0

c;,

Register

ANI

o

I

o

I

o

DB7

DB6

DB5

DB4

DB3

0

1

0

0

0

0

0

0

0

0

0

0

RS

DB7

0

Instruction reg.

0

1

Display start address reg.
(low order byte)

0

0

0

I

0

I

1

lOBO

I

1

of 1 to 16 (decimal) can be set to Cpo If a smaller
value than the vertical character pitch Vp is set (Cp
::;; V~, and a character overlaps with the cursor, the
cursor has higher priority of display (at cursor display on). If C p is greater than Vp' no cursor is displayed. The cursor horizontal length is equal to lip.

RS

6. Set Display Start Low Order Address: Cause
display start addresses to be written in the display
start address registers. The display start address
indicates a RAM address at which the data displayed at the top left end on the screen is stored. In

I

(N x - 1) binary

0

906

I

0

Instruction reg.

ANI

o

I DB5 I DB4 I DB3 I DB2 I DB1

I

Cursor position reg.

Register

I

0

J DB1 lOBO
I 1 I 0

A value of I to 128 (decimal) can be set to Nx.

0

c;,

I

DB2

IlNx is the display duty ratio.

ANI

S. Set Cursor Position:
indicates the position
in a character where the cursor is displayed in the
character mode. For example, in 5 x 7 dot font, the
cursor is displayed under a character by specifying
= 8 (decimal). The cursor horizontal length is
equal to the horizontal character pitch Hp. A value

I DB5 I DB4 I DB31

(HN - 1) binary

4. Set Number of Time Divisions (Inverse of
Display Duty Ratio): Nx indicates the number of
time divisions in multiplex display.

Instruction reg.

HN can be set to an even number from 2 to 128
(decimal).

DB7

Number-of-characters reg.

Register

n = lIpXHN

I DB2 I DB1 lOBO
I 1 I 0 I 0
(Cp - 1) binary

the graphic mode, the start address is composed of
high/low order 16 bits. In the character display, it is
composed of the lower 4 bits of high order address
(DB3-DBo) and 8 bits of low order address. The
upper 4 bits of high order address are ignored.

I DB6 I DB5 I DB4 I DB3 I DB2 I DB1 lOBO
I 0 I o I o I 1 I oI o I 0
(Start low order address) binary

HITACHI

HD61830/HD61830B
Set Display Start High Order Address
RIW

RS

DB?

Instruction reg.

0

1

0

Display start address reg.
(high order byte)

0

0

Register

I DB6 I DB5 I DB4 I DB3 I DB2 I DB1 I DBO

I

o

I

0

I

o

I

1

I

0

I

o

I

1

(Start high order address) binary

7. Set Cursor Address (Low Order) (RAM
Write Low Order Address): Cause cursor
addresses to be written in the cursor address counters. The cursor address indicates an address for
sending or receiving display data and character
codes to or from the RAM.
That is, data at the address specified by the cursor
address are read/written. In the character mode, the
cursor is displayed at the character specified by the
cursor address.

(8 bits) and the high-order address (8 bits). Satisfy
the following requirements setting the cursor
address (table 2).
The cursor address counter is a 16-bit up-counter
with set and reset functions. When bit N changes
from 1 to 0, bit N + 1 is incremented by 1. When
setting the low order address, the LSB (bit 1) of the
high order address is incremented by 1 if the MSB
(bit 8) of the low order address changes from 1 to
O. Therefore, set both the low order address and the
high order address as shown in the table 2.

A cursor address consists of the low-order address
RIW

Register

RS

DB?

o

Instruction reg.

0

1

Cursor address counter
(low order byte)

0

0

I DB6 I DB5 I DB4 I DB3 I DB2 I DB1 I DBO
I 0 I o I o I 1 I o I 1 I 0
(Cursor low order address) binary

Set Cursor Address (High Order) (RAM Write High Order Address)
Register

~

RIW

RS

DB?

0

Instruction reg.

0

1

Cursor address counter
(high order byte)

0

0

I DB6 I DB5 I DB4 I DB3 I DB2 I DB1 I DBO
I 0 I o I o I 1 I 0 I 1 I 1
(Cursor high order address) binary

Table 2 Cursor Address Setting
Condition

Requirement

When you want to rewrite (set) both the low order
address and the high order address.

Set the low order address and then set the high
order address.

When you want to rewrite only the low order
address.

Don't fail to set the high order address again after
setting the low order address.

When you want to rewrite only the high order
address.

Set the high order address. Vou don't have to set
the low order address again.

HITACHI

907

HD61830/HD61830B
8. Write Display Data: After the code $"OC" is
written into the instruction register with RS = 1.
8-bit data with RS = 0 should be written into the
data register. This data is transferred to the RAM
ANI

Register

RS

DB7

o

Instruction reg.

0

1

RAM

0

0

J DBS I DBS I DB4 I DB3 I DB2 I DB1 lOBO
I o I o I o I 1 I 1 I 010
MSB (pattern data, character code) LSB

9. Read Display Data: Data can be read from the
RAM with RS = 0 after writing code $"OD" into
the instruction register. Figure 1 shows the read
procedure.

transfers RAM data specifled by the cursor address
to the data output register. also increasing the cursor address by 1. After setting the cursor address.
correct data is not output at the fmt read but at the
second one. Thus. make one dummy read when
reading data after setting the cursor address..

This instruction outputs the contents of data output
register on the data bus (DBo to DB?) and then
ANI

RS

DB7

Instruction reg.

0

1

o

RAM

1

0

Register

CS-'~

specified by the cursor address as display data or
character code. The cursor address is increased by
1 after this opemtion.

I DBS lOBS I DB4 I DB3 I DB2 I DB1 lOBO
I o I o I o I 1 I 1 I o I 1
MSB (pattern data, character code) LSB

____________________~____________________

E

R/W
~,---_--,n,--_-----,ILJ
RS
DB
Busy Curaor CurSor Busy Cu.....
chock addrlllS
check addrlllS low
sat
set
order
mod.
mode addrlllS

Cursor

address
Data

-

Cursor
high
order

_ .....

Busy

check.

Data Dummy Busy N
read read
check address
mode
data
read

data
read

write

·NL

N

output
register

Figure 1 Read Procedure

908

Busy N + 1
check address

HITACHI

N+1

N+2

HD61830IHD61830B
10. Clear Bit: The clear/set bit instruction sets 1
bit in a byte of display data RAM to 0 or 1, respectively. The position of the bit in a byte is specified
by NB and RAM address is specified by cursor

address. After the execution of the instruction, the
cursor address is automatically increased by l. NB
is a value from 1 to 8. NB = 1 and NB =8 indicates
LSB and MSB, respectively.

RIW

RS

DB7

DB6

DB5

DB4

DB3

DB2

Instruction reg.

0

1

0

0

0

0

1

1

Bit clear reg.

0

0

0

0

0

0

0

Register

I DB1

lOBO

I

I

1

0

(NB - 1) binary

Set Bit
RIW

RS

DB?

DB6

DB5

DB4

DB3

DB2

Instruction reg.

0

1

0

0

0

0

1

1

Bit set reg.

0

0

0

0

0

0

0

Register

11. Read Busy Flag: When the read mode is set
with RS = 1, the busy flag is output to DB7. The
busy flag is set to 1 during the execution of any of
the other instructions. After the execution, it is set
to O. The next instruction can be accepted. No
instruction can be accepted when busy flag = l.
Before executing an instruction or writing data,
perform a busy flag check to make sure the busy
Register

RIW

RS

DB?

Busy flag

1

1

110

I DB1

lOBO

I

I

1

1

(NB - 1) binary

flag is O. When data is written in the register (RS =
1), no busy flag changes. Thus, no busy flag check
is required just after the write operation into the
instruction register with RS = 1.
The busy flag can be read without specifying any
instruction register.

DB6 lOBS

HITACHI

I DB4 I DB3 I DB2 I DB1
.

lOBO

I

I

909

HD61830/HD61830B

Il.

>

x

z

~-------------HN------------~

(digit)

Symbol

Nx

Name

Meaning

Value

Horizontal character pitch

Horizontal character pitch

6 to 8 dots

Number of horizontal
characters

Number of horizontal characters per line
(number of digits) in the character mode
or number of bytes per line in the graphic
mode

2 to 128 digits
(an even number)

Vertical character pitch

Vertical character pitch

1 to 16 dots

Cursor position

Une number on which the cursor can be
displayed

1 to 16 lines

Number of time divisions

Inverse of display duty ratio

1 to 128 lines

Note: "the number of vertical dots on the screen is m. and the number of horizontal dots is n.
11m = l/N x = display duty ratio
n =Hp x HN• mNp =Number of display lines
Cp !OVp

Figure 2 Display Variables
910

HITACHI

Display Mode
Character
display

Display Data
fromMPU

Liquid Crystal
Display Panel

RAM

...
t='

i

~

Character code
(8 bits)

bo

~bsb5b4bab2b1
I
I
I
I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I

I

I

I

I

I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

I
I
I

I
I
I

I
I
I
I
I

I
I
I
I
I

: : : : : :
: : : : : : :
Start
~
address

,

,

I

I

I" HI!

f--A

B

i

C

011101010101011
011101010101110
:,
:,
:,

:, : :, : : :
: : :, : :, :
:, :, :, :, :, :,

I

I

I

, ,

I

I

I

I

,
I

,
I

,
I

I

I

I

Hp: 6, 7, or 8 dots

, ,

I

I

::J:

~
n
::J:

-

Graphic

Display pattern
(8 bits)

~bsb5b4ba~b1 bo

.. · · · ::,,
· , , , ·,
,
,
, ,, ,
·
011101110111011
~ 111111111111111
··: ..:, :,,, ·: ··,,,, ·:, ··,
··,• , ··, ··, ·:, ··, :
· ·· ·
I
I

,
,
,

•

I

I

,

,

Start
address

I
,

,,,
,
,
,
,'

I

I

,
,

I
I
I

,,
,
I

I

I
I

I
I

,
I
I
I
I

,,
,,
,
I

I
I

I
I
I

I
I

I
I

,
,
,,
,,
,

,,
,

,,
,,

bo

Hp

~I

•••

I

8 dots

8 dots

I

....
0\
QC

toN

I

I

I

I
I
I
I

I
I

:!l

8

Hp: 8 dots

2
o
....

0\

f3

~

HD61830/HD61830B
Internal Character Generator Patterns and Character Codes

912

HITACHI

HD61830IHD61830B
Example of Correspondence between External CG ROM Address Data and
Character Pattern
8x8 Dot Font

o

0

0

0

0

0

0

0

0

0

A 9

0

0

0

AS

0

0

A 7

0

o

0

0

1 0

0

1

0

1

1

1

o

0

1 0

1

1

o

Al0

1 0

1

1

0

o

0

o

0

1

0

1 0

0

1

1

1

o

1

000

o

0

1 0

8 x 16 Dot Font

~

All
Al0
A 9
AS
A7 AS A5 A4 A3A2Al AO
o 0 o 0
0 o 0 1
0 0 1 0
0 o 1 1
0 1 0 0
0 1 o 1
o 1 1 0
0 1 1 1
0 0 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 o 0
1 1 0 1
1 1 1 0
1 1 1 1
0 o 0 0

0
0
0
0
0

0

~~
0
0

o
0

o
o
o
o
o
o

0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0

O. 05 o.
0 o 0
, o 0
0 0
0 o 0
0 0 0
0 0 0
WE o 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 o 0
0 0 0
0 0 0
0 o 0
0 o 0

m
0
0
0
0
0
0
0
0
0
0
0

0
0
0
1
O. O.
0 0
0 0
0 0

0
0
1
0
Os o.
0 0
0 0
0 0

07
0
0
0

00.0000
000
0
00
0000
·000
000
0000
00
00000

0
0
0
0
0
0
0
0
0
0
0
0
0

0 7 00
o 0
o 0
o 0

01
0
0
0

O2
0
0
0

'II'
oWEoooooo
o 0 0 0 0 0 0 0
o 0 0 0 0 0 0 0
o 0 0 0 0 0 0 0
o 0 0 0 0 0 0 0
o 0 0 0 0 0 0 0

0 0
0 0

0
0

0
0

HITACHI

0
0

0
0

0
0

0
0

913

HD61830/HD61830B
Example of Configuration
Graphic Mode or Character Mode (I) (Internal Character Generator)
HD61830

14----1 HD61830B

,..-I---lr...,

Liquid crystal
display module

MAo-MA1S at graphic mode,
MAo-MAll at character mode

Character Mode (2) (External Character Generator)
HD61830
HD61830B

Uquld crystal
display module

Parallel Operation (HD61830)

Uquid crystal
Uquid crystal
display module (1) display module (2)
Driving both of two
module by same
common signal

Parallel Operation (HD61830B)
Uquid crystal
Uquld crystal
display module (1) display module (2)
Driving both of two
module by same
common signal

914

HITACHI

HD61830/HD61830B
HD61830 Application (Character Mode, External CG, Character Font 8 x 8)

HD6800

~!:

WE

RS

p-

MAo
10

CS

MA tO

112

DB.
to
DB7
E

RIW

RIW

MA'2
to
MA,.
MAIO
MOo
to
MD,

A14
A..
VMA
D.
to

D,

lS

~

HD61830

A"

WE

r------v

Ao
to

A '0

~

CS

R

C

9i

OE

-;J,.

<:=-

CS

f

D.

'\)
Ao-A,

A,-A,.

ROM
HN462716

~

OE

CE
0,
FLM
MB
Cl,
CL,
O2
+5V
GND

CR

lCDmodule
LM200

~V5V

~

+5V
GND
-5V

RAM (2)
HM6116

r---

0,

'-

_

......

FlM
MB
Cl,
CL,
O2
MA -Open

Open- SYNC
CPO
Ve<;- RES

WE
A
to·
AtO

,....,

f

MAl1

RD.
to
RD,

OE
RAM (1)
HM6116

HD61830 Application (Graphic Mode)

i-------------------- l
HD6800
MPU

DB.-DB,
CSE
RSRIW
RES

MAoMA"

J

MD.-MD,

• J

i

0
HD61830
controller

,

O2
Cl, Cl2
MB, FLM

IHD44100H

I
I ~T~
~
I ~ c...:..
I

r--1

I

RAM
16 kbits
CMOS

i

IHD44100H - - - - - - - - - - - - - -I HD44100H 1

I

I
I

t t

I

GND
Voo (5 V)
V.d-5V)

$ i
I

I

++
HD44100HI

LCD

I

WE

-------------

I V -V.
-' Power supply lor
liquid crystal
display drive

L

ri

I_ _ _ _ _ _

HITACHI

f

f

J

----------------~~~
lM

915

HD61830/HD61830B
HD61830B Application (Character Mode, External CG, Character Font 8 x 8)

HD61830B

HD6303
A.

~

A,.

=U-

RS

WE

es

MAo
to
MA,.

E

DB.
to
OB7
E

RIW

RIW

0.

lS~E

OE
RAM(1) D.
HM6116
A,.
CS

6'! <-

r----v' :;:.

l
OE
RAM (2) D.
to
HM6118

0.

es

A,.

OE

Decoder

D.
10

~WE

CE
MA"
MA,.
to
MA,.
MO.
to
Me.
RD.
10
R07
0,
FlM
MB
Cl,
Cl.

Open-- SYNC
V----,
point

1

I
928

Cl

Cl = 30pF
(C l includes jig capacitance)

HITACHI

Notes

ns

2,3

ns

2,3

ns

2

ns

2

HD61830/HD61830B
8D61830B MPU Interface
(Vee = 5 V±10%, GND =0 V, T. =-20 to +75°C)
Item
Enable cycle time
Enable pulse width

Symbol

Min

tcvc

1.0
0.45
0.45

High level

tWEH

Low level

tWEL

Enable rise time

Typ

Max

Unit
~
~
~

25
25

tEr

ns

Enable fall time

tEt

Setup time

tAS

140

Data setup time

tosw

225

Data delay time

tOOR

Data hold time

tOHW

10

ns

Address hold time

tAH

10
20

ns

ns

225

Data hold time

ns
ns
ns·

ns

tOH
Note: • The following load circuit is connected for specification:
evc
tWEH

tWEl
~

2.2V

E

tAS"'

~

CS.RIW.RS

V

~

0.8V "
tEf-

I--tEr

-tAH

2.2V

>(

0.8V

~

tDHW

~

X

K

2.2V

OB o-087

(MPU-H061830B)

0.8V

tDDR

)

OBo-OB7

(MPU-H061830B)

~

K

2.4V
0.4V

Vcc

Test
point

0----..---..*-1
R

04

C = 130 pF (C includes iig capacitance)
Diodes 0, to 0 4 : 152074(8)

HITACHI

929

HD61830/HD61830B
HD61830B External RAM and ROM Interface
(Vee 5 V ±10%, GND 0 V, Ta -20 to +75°C)

=

=

=

Item

Symbol

MAo-MAts delay time

tDMA

MAo-MAts hold time

tHMA

CE delay time

tOCE

CEhold time

tHeE

C5E delay time
C5E hold time

tooE

MD output delay time

tDMD

Min

Typ

Max

Unit

Notes

300

ns

1,2,3

ns

1,2,3

ns

1,2,3

ns

1,2,3

ns

1,3

ns

1,3

ns

1,3

ns

1,3

40
300
40
300
40

tHoE

150

MD output hold time

tHMDW

WE delay time

tDWE

10

ns

1,3

twwE

150

ns

1,3

tZMDF

10

ns

1,3

MD output high impedance
time (2)

tZMDR

50

ns

1,3

WE clock pulse width
MD output high impedance
time (1)

150

RD data set-up time

tSRD

50

ns

2

RD data hold time

tHRD

40

ns

2

MD data set-up time

tSMD

50

ns

2

MD data hold time

tHMD

40

ns

2

Notes: 1. RAM write timing
T,

T,

T2

CR
tHeE

O.6V
tOMA
tHMA

tOMA
tHMA

2.4V
O.6V
tOOE
tHOE

tOOE
tHOE

2.4V
O.6V
tOWE tOWE
tZMOR

MDO-MD7 ____________~(H~ig~h_i_m~p_ed_a_n_ce~)________~~
~=-+--'r

(Output)

Tl: Memory data refresh timing for upper screen
T2: Memory data refresh timing for lower screen
T3: Memory read/write timing

930

HITACHI

HD61830/HD61830B
2. ROM/RAM read timing
T,

T,

CR

('2)

('2)

~~----~------~--------

0.6V-+---------------------+~--------~~~------H_-------tOMA

tOMA

tHMA

tHMA

. Address for
the lower
screen

Address for upper screen

2.2V
O.SV

Data for the upper screen
tSRO

2.2V
O.SV

*1 This figures shows the timing for Hp 8.
For Hp .. 7, time shown by "b" becomes zero. For Hp _ 6, time shown by "a" and "b" become
zero.
Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of Hp • 8,
Hp = 7, or Hp =6 respectively.
*2 The waveform for instructions with memory read is shown with a dash line. In other cases,
the waveform shown with a solid line is generated.
*3 When an instruction with RAM read/write is executed, the value of cursor address is output.
In other cases, invalid data is output.
*4 When an instruction with RAM read is executed, HD61830B latches the data at this timing. In
other cases, this data is invalid.
0=

3. Test load circuit
Vee

Test
point
R

RL =2.4kO
R =llkO
C = 50 pF (C includes iig capacitance)
Diodes D, to D4 : 152074(8)

HITACHI

931

HD61830/HD61830B
HD61830B LCD Driver Interface
(Vee = 5 V ±10%, GND = 0 V, Ta = -20 to +75°C)

Typ

Max

Symbol

Min

Unit

Notes

Clock cycle time

twcL2

ns

Clock pulse width
(high level)

tWCH

416
150

ns

1,3
1,3

Clock pulse width
(low level)

tWCL

150

ns

1,3

Data delay time

too

ns

Data hold time

tOH

100

ns

1,3
1,3

Clock phase difference (1)

tCL1

100
100
100
-200
400
1000

ns

Item

Clock phase difference (2)

tcL2

Clock phase difference (3)

tcL3

MA, MB delay time

tOM

FLM set-up time

tSF

FLM hold time

tHF

MA set-up time

tSMA

MAhold time

tHMA

932

·50

400
1000

HITACHI

ns
ns

200

ns

1,3
1,3
1,3
1,3

ns

2,3
2,3
2,3

ns

2,3

ns
ns

HD61830/HD61830B
Notes:

1.
tWC12

tWCH

,

tWCL

.1

J

0.7Vcc
0.3Vcc
tCL1

....

~

[O.7VCC
0.3Vcc

Cl1

tWCH
tOH

too

).

tCL3

tC12

0.7Vcc
0.3Vcc
tOM

).

MA,MB

0.7Vcc
0.3Vcc

2.
0.7Vcc

Cl1

\'0.3Vcc

I

tSF

FlM

)

tHF
~

0.7Vcc
0. 3VCC

~
tSMA

tHMA

I

MA

~

ff"

0.7Vcc
0. 3VCC

3. Test load circuit
TaM
point

O~-------~

.1.

;J;

Cl

Cl = 100 F (CL inc!udes ii9 )·
P

HITACHI

capacitance

933

H D63645/H D64645/H D64646
LCTC (LCD Timing Controller)
Description

•

The HD63645/HD64645/HD64646 LCTC is a
control LSI for large size dot matrix liquid
crystal displays. The LCTC is software compatible with the HD6845 CRTC, since its
programming method of internal registers
and memory addresses is based on the CRTC.
A display system can be easily converted
from a CRT to an LCD.

•

The HD64646 LCTC is a modified version of
the HD64645 LCTC with different LCD interface timing.

•

The LCTC offers a variety of functions and
performance features such. as vertical and
horizontal scrolling, and various types of
character attribute functions such as reverse
video, blinking, nondisplay (white or black),
and an OR function for simple superiinposition of character and graphic displays. The
LCTC also provides DRAM refresh address
output.
A compact LCD system with a large screen
can be configured by connecting the LCTC
with the HD66204 (column driver) and the
HD66205 (common driver) by utilizing 4-bit
x 2 data outputs. Power dissipation has been
lowered by adopting the CMOS process.

•

•
•

•
•
•

Cursor with programmable height, blink
rate, display position, and on/off switch
Vertical Smooth Scrolling and horizontal
scrolling by the character
Versatile display modes programmable
by mode register or external pins: display
on/off, graphic or character, normal or
wide, attributes, and blink enable
Refresh address output for dynamic RAM
4- or 8-bit parallel data transfer between
LCTC and LCD driver
Recommended LCD driver:
HD66204, HD66214T and HD66224T
(column)
HD66205 and HD66215T (common)
HD66106F and HD66107T (column/
common)
HD66110RT (column)
CPU interface:
68 family HD63645
Z80 family HD64645, HD64646
CMOS process
Single +5 V ±10%

Differences Between Products

HD63645, HD64645 and HD64646
HD6364&

HD6464&

HD64646

68 family

Z80 family

Z80family

Bus Timing

2MHz

4MHz

4MHz

Pin
Arrengement
and Signal
name

Pin 41: R/W Pin 41: RD
Pin 42: E
Pin 42: WR

CPU
Interface

Features
•
•
•
•
•
•
•
•

Software compatible with the HD6845
CRTC
Programmable screen size:
-Up to 1024 dots (height)
-Up to 4096 dots (width)
High-speed data transfer:
-Up to 20 Mbits/s in character mode
-Up to 40 Mbits/s in graphic mode
Selectable single or dual screen configuration
Programmable multiplexing duty ratio:
static to 1/512 duty cycle
Programmable character font:
-1-32 dots (height)
-8 dots (width)
Versatile character attributes: reverse
video, blinking, nondisplay (white),
nondisplay (black)
OR function: superimposing characters
and graphics display

934

Other

Pin41:RD
Pin 42: WR

modified

LCD driver
interface
timing

Ordering Infomation
Type No.

CPUlntarface

Package

HD63645F

68 family 2 M Hz bus

BO-pin plastic

HD64645F

Z80 family 4 MHz bus

OFP IFP-BOB)

HD64646FS

zao family 4

BO-pin plastic
QFP IFP-BOB)

HITACHI

M Hz bus

HD63645/HD64645/HD64646
Pin Arrangement

~c~~~ ~~< ~ ~

O_NM~1t)

ecce cc

~~~~~~~~~ ~ ~~~~~~
1i1l~1I' ~II~ .1I~1I.1I.1I< ~

•••

MOl
M02
M03
M04
M05
M06
M07

,
•
•
•
•
,
•

•
RAO

ru

RA1

f'ii

RA3

~RA2

~ RA4

~GNOl

~G~
'" AT

"LS

MOB'

~O~

M09
MOlD"
M011 12
M012 "
M01'3"
M014 "
M015 "
V ee 1 11
L03 '1
L02 "
LOl ..
LOO "
LU3 "
LU2 "
LUl ..

( ) is for HD64645 and HD64646

~

~

MOO'

~WIOE

'" ON/OFI'

.. MODE
, BLE
DB7
'" DB.

50

.. DB6
q DB4
... DB3
..., DB2

... DB,

43DBo

.. RiW(RDI

4'

E(WR)

(Top View)

HITACHI

935

HD63645/HD64645/HD64646
Pin Description
Symbol

I/O

Name

Vee 1, Vee2

Pin Number
17,32

GND1,GND2

37,59

LUO-LU3

22-25

0

LDO-LD3

18-21

CL1

28

CL2

29

FLM

27

M

26

MAo-MA15

65-80

RAO-RA4

60-64

0
0
0
0
0
0
0

MDo-MD7

1-8

MD8-MD15

9-16

I

Memory Data 8-1 5

DBo-OB7

43-50

I/O

Data BusO-7

Vee
Ground
LCD Up Panel Data 0-3
LCD Down Panel Data 0-3
Clock One
Clock Two
First Une Marker
M
Memory Address 0-15
Raster Address 0-4
Memory Data 0-7

CS

39

Chip Select

E

41

Enable (HD63645 Only)

R!W

42

Read!Write (HD63645 Only)

WR

41

Write (HD64645 and HD64646)

RD

42

Read (HD64645 and HD64646)

RS

40

Register Select

RES

38

DCLK

33

I

D Clock

MCLK

34

DISPTMG

35

0
0
0

Display Timing

Reset
M Clock

CUDISP

36

SKO

30

Cursor Display

SK1

31

Skew 1

ON!OFF

53

On/Off

Skew 0

BLE

51

Blink Enable

AT

57

Attribute

G!C

58

Graphic/Character

WIDE

54

Wide

LS

56

I

Large Screen

DIS

55

I

Dual/Single

MODE

52

936

Mode

HITACHI

HD63645/HD64645/HD64646
Pin Functions
Power Supply (Veel, Vee2, GND)
Power Supply Pin (+5 V): Connect V..,1
and V..,2 with +5 V power supply circuit.
Ground Pin (0 V): Connect GND1 and
GND2 with 0 V.
LCD Interface
LCD Up Panel Data (LUG-LU3), LCD
Down Panel Data (LDG-LD3): LUO-LU3
and LDO.-LD3 output LCD data as shown in
table 1.

Cblp Select (CS): CS selects a chip. Low
level enables MPU read/write of the LCTC
internal registers.
Enable (E): E receives an enable clock.
(HD63645 only).
Read/Write (R/W): R/W enables MPU read
of the LCTC internal registers when R/W is
high, and MPU write when low (HD63645
only).
Write (WR): WR receives MPU write signal
(HD64645 and HD64646).

Clock One (CLI): CL1 supplies timing clocks
for display data latch.

Read (RD): 1m receives MPU read signal
(HD64645 and HD64646).

Clock Two (CL2): CL2 supplies timing clock
for display data shift.

Register Select (RS): RSselects registers.
(Refer to table 5.)

Firat Line Marker (FLM): FLM supplies

Reaet (RES): RES performs external reset of
the LCTC. Low level of RES stops and zeroclears the LCTC internal counter. No register
contents are affected.

first line marker.

1111 (1111): M converts liquid crystal drive output
toAC.

Ttming Signal

lIIIemory Interface

o

lIIIemory Addreaa (lIIIAG-lIIIAI5): MAOMA15 supply the display memory address.

Clock (DCLK): DCLK inputs the system

clock.

1111 Clock (IIIICLK): MCLl{ indicates memory
cycle; DCLl{ is divided by four.

Raster Addreaa (RAO-RA4): RAO-RA4
supply the raster address.

Display Timing (DISPTlIIIG): DISPTMG
high indicates that the LCTC is reading display data.

lIIIemory Data (lIIIDO-MD7) : MDO-MD7
receive the character dot data and bitmapped data.

Cursor Dlaplay (CUDISP): CUDISP supplies cursor display timing; connect with
MD12 in character mode.

lIIIemory Data (lIIID8-lIIIDI&): MD8-MD15
receive attribute code data and bit-mapped
data.
MPU Interface

Skew 0 (SKO)/Skew I (SKI): SKO and SK1
control skew timing. Refer to table 2.

Data Bus (DBO-DB7): DBO-DB7 sendl
receive data as a three-state I/O common

lIIIode Select

bus.

The mode select pins ON!OPF, BLE, AT, G/C,

Table I

LCD Up Panel Data and LCD Down Panel Data
SlngleS_

PIn name

4-Bit Data

8-BIt Data

DuaIS_

LUo-LU3
LDO-LD3

Data output
Disconnected

Data output
Data output

Data output for upper screen
Data output for lower screen

HITACHI

937

HD63645/HD64645/HD64646
and WIDE are ORad with the mode register
(R22) to determine the mode.

On/Off (ON/OFF): ON/OFF switches display on and off (High = display on).
Blink Enable (BLE): BLE high level enables
attribute code "blinking" (MD13) and provides normal/blank blinking of specified
characters for 32 frames each.
Attribute (AT): AT controls character
attribute functions.

Graphic/Character (G/C): G/C switches
between graphic and character display mode
(graphic display when high).

Wide (WIDE): WIDE switches between
normal and wide display mode (high = wide
display, low = normal display).
Large Screen (LS): LS controls a large
screen. LS high provides a data transfer rate
of 40 Mbits/s for a graphic display. Also used
to specify 8-bit LCD interface mode. For more
details, refer to table 10.
Dual/Single (D/S): DIS switches between
single and dual screen display (dual screen
display when high).
Mode (MODE): MODE controls easy mode.
MODE high sets duty ratio, maximum number of rasters, cursor start/end rasters, etc.
(Refer to table 9.)

Table 2 Skew Signals
SKO

SK1

Skew Function

o

o
o

No skew
1 -character time skew
2-character time skew
Prohibited combination

1

o

938

HITACHI

HD63645/HD64645/HD64646
Function Overview
Main Features of HD63645/HD64645/
HD64646

LCD and CRT Display Systems
Figure 1 shows a system using both LCD and
CRT displays.

Main features of the LCTC are:
High-resolution liquid crystal display
screen control (up to 720 x 512 dots)
Software compatible with HD6845
(CRTC)
Built-in character attribute control circuit
Table 3 shows how the LCTC can be used.

Table 3 Functions, Application, and Configuration
Claaaification

Item

Description

Functions

Screen Format

• Programmable horizontal scanning cycle by the character clock
period
• Programmable multiplexing duty ratio from static up to 1/512
• Programmable number of vertical displayed characters
• Programmable number of rasters per character row (number of
vertical dots within a character row + space between character
rows)

Cursor Control

• Programmable cursor display pOSition, corresponding to RAM
address
• Programmable cursor height by setting display start/end rasters
• Programmable blink rate, 1/32 or 1/64 frame rate

Memory Rewriting

• Time for rewriting memory set either by specifying number of
horizontal total characters or by cycle steal utilizing MCLK

--------------------------------------------------------------------------------------------------._--------------------------Memory Addressing

• 16-bit memory address output, up to 64 kbytes x 2 memory accessible
• DRAM refresh address output

Paging and ScrOlling

• Paging by updating start address
• Horizontal scrolling by the character, by setting horizontal virtual
screen width
• Vertical smooth scrolling by updating display start raster

---------_.-._-----------_.-._--------------------------------.---_.----------------------------------------------------------Character Attributes

Application

Configuration

• Reverse video, blinking, nordisplay (white or black), display ON/
OFF

CRTC Compatible

• Facilitates system replacement of CRT display with LCD

OR Function

• Enables superimposing display of character screen and graphic
screen

LCTC Configuration

• Single 5 V power supply
.1/0 TTL compatible except RES, MODE, SKO, SKl
.Bus connectable with HMCS 6800 family (HD63645)
.Bus connectable with 80family (HD64645 and HD64646)
.CMOS process
• Internal logiC fully static
.80-pin flat plastic package

HITACHI

939

HD63645/HD64645/HD64646

Uquid crystal
display

CRT
(monochrome)

LCD display signals

I I

MPU
6301

Figure 1

940

LCD and CRT Displays

HITACHI

HD63645/HD64645/HD64646
Differences Between HD64645 and
HD64646
Figure 2 and figure 3 show the relation
between display data transfer period, when
display data shift clock CL2 changes, and
display data latch clock CL1. Figure 2 shows
the case without skew function and figure 3
shows the case with skew function.
In figure 2, high period between CL2 and CLl

of HD64645 overlap. HD64646 has no overlap

like HD64645, and except for this overlap.
HD64646 is the same as HD64645 functionally.
Also for the skew function, phase relation
between CLl and CL2 changes. As figure 3
shows, data transfer period and CLl high
period of HD64646 never overlap with the
skew function.

MClK

DISPTMG

~~

CLl
(HD64645)

~

Cll
(HD64646)

________________ ______________
~~

MClK x 16

~r--

Jl

_____________....Jr

MClK x 11

~---------»~-----------------nnnnnnnn

CL2
(fcl2 = 2fMcLK ).J
Notes: f McLK
fCl2

U U U U U U U I'--------~l}---------------

= Output frequency of MClK
= Output frequency of CL2
Figure 2 Differences between HD64645 and HD64646 (no skew)

HITACHI

941

HD63645/HD64645/HD64646

MClK

~--------------~flr----------------~r-­

DISPTMG

Cll
(HD64645)
CLl
(HD64646)

S5

MClK x 16

___________r5

MClK x 11

CL2

'(fcl2 = 2fMcLKl.
1 character skew

MClK

DISPTMG

Cll
(HD64645)

CLl
(HD64646)

~------------f~f----------------~r--MClK x 16

_______-----'r

f

MClK x 11

2 character skew

Figure 3 Differences between HD64645 and HD64646 (skew)

942

HITACHI

HD63645/HD64645/HD64646
Internal Block Diagram
Figure 4 is a block diagram of the LCTC.

M

if:

AT

~

~~

MODE
LE

_1-- _ - - - - I t CUDISP

SKO SK 1

) is for HD64645 and HD64646 (ZSO types bus interface)

Figure 4 LCTC Block Diagram

HITACHI

943

HD63645/HD64645/HD64646
System Block Configuration
Examples
Figure 5 is a block diagram of a character /
graphic display system. Figure 5 shows two
examples using LCD drivers.

HD63645/H D64645/H 064646
MPU Bus

r1=fI:::rl=====================d(WR) (RD)
E,R/W

.

"
iii
.0

c

.i'

K=============:jjDBO-DB7

.

.--_ _ _ _....jMAO-MA 15

::l

.0

~

""«

G/C
AT

I====~CS, RS

.
::l

.0

~

LS
D/S

WIDE
MODE
ON/OFF

,-----"'.&----'''"''---,

F::::;'~:::::jMCLK

2

DISPTMG

[MOO._
Display On/off
Blink enable

C

Reset

LUO-3
LDO-LD3

CL2!----JJ
CL1~-_,/I

~=~~=:::IRAO-MD4

M
FLM

LCD
Module

( ) is for HD64645 and HD64646 (ZaO type bus interface)

Figure 5 Character/Graphic Display System Example

944

HITACHI

HD63645/HD64645/HD64646
Interface to MPU

RS

P10-P17

I

it
Decoder

t-----c

SC2 (R/W)

CS

R/W

HD6301
MPU

HD63645
LCTC
E

E

P3o-P37

DBo-DB7

RES

RES

RESET
Note: HD6301 is set in mode 5. P1 0-P17 are used as output ports, and
P30-P37 as data buses. SC2 outputs RM here.
Interface between HD6301 and HD63645

RS

Ao-A15

IDE

r---

RD
HD64180
MPU

iNA

I

1l

Decoder

~

CS

5'--

RD

D-

WR

Do-D7

HD64645
HD64646
LCTC

DBo-DB7

RES

RES

RESET
Note: In 80 family MPUs. I/O space is separate from memory space in
software. Thus the LCTC, a part of I/O, needs the ORed signals
of the interface signals and IDE. So IDE and RD, and IDE and
WR should be ORed to satisfy tAS, the timing of CS. RD, and
WR.
Interface between HD64180, HD64645 and HD64646

Figure 6 Interface to MPU

HITACHI

945

HD63645/HD64645/HD64646

I

Dual scraen

I

LUOLU3

LCTC

I

Single screen

I

LUOLU3

LCD panal 240 x 640 dots
1/240 duty ratio

LCTC

Figure 7 LCD Driver Examples

946

HITACHI

HD63645/HD64645/HD64646
Registers
Table 4 shows the register mapping. Table 5
describes their function. Table 6 shows the

differences between CRTC and LCTC registers.

Table 4 Registers Mapping
Addr-.
Regiater Reg.

Data Bit

CS RS 43210 110.

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1

----00000
00001
01001
01010
0101 1
01100
01101
01 1 1 0
01 1 1 1
10010
10011
10100
10101
1011 0

Name

AR
RO
Rl
R9
RIO
R11
R12
R13
R14
R15
R18
R19
R20
R21
R22

Program Unit

Invalid
Address Register
Horizontal Total Characters
Character3
Horizontal Displayed Char.s Character
Maximum Raster Address
Raster
Cursor Start Raster
Raster!
Cursor End Raster
Raster
Start Address (H)
Memory Address
Start Address (L)
Memory Address
Cursor Address (H)
Memory Address
Cursor Address (L)
Memory Address
Horizontal Virtual Screen WidthCharacter
Multiplexing Duty Ratio (H) Raster3
Multiplexing Duty Ratio (L)
Raster3
Display Start Raster
Raster
Mode Register
-Note5

SymboIR/W

Nht
Nhd
Nr
Ncs
Nee
Nir
Ndh
Ndl
Nsr

W
W
W
W
W
W
R/W
R/W
R/W
R/W
W
W
W
W
W

7

6

5

4

3

ON/ G/C
OFF

2

0

BLE

AT

Notes: 1.
: Invalid data bits
2. R/W indicates whether write access or read access is enabled to/from each register.
W:
Only write accessible
R/W: Both read and write accessible
3. The Hvalue to be specified minus 1 should be programmed in these registers: RO, R1 and
R20.
4. Data bits 5 and 6 of cursor start register control the cursor status as shown below.
(For more details, refer to page 27) .
H

B

o

o
1
1

P

Cursor Blink Mode

0
1
0
1

Cursor on; without blinking
Cursor off
Blinking once every 32 frames
Blinking once every 64 frames

5. The OR of mode pin status and mode register data determines the mode.
6. Registers R2-R8, R16, and R17 are not assigned for the LCTC. Programming to these
registers will be ignored.

HITACHI

947

HD63645/HD64645/HD64646
Table 5 Internal Register Description
Reg.
No.

Register Name

Size(Bita)

Description

AR

Address Register

5

Specifies the internlll control registers (RO, R1,
RS-R 15, R1a-R22) address to be accessed

RO

Horizontal Total Characters

a

Specifies the horizontal scanning period

R1

Horizontal Displayed Characters

a

Specifies the number of displayed characters per
character row

RS

Maximum Raster Address

5

Specifies the number of rasters per character row,
including the space between character rows

R10

Cursor Start Raster

5+2

Specifies the cursor start raster address and its
blink mode

R1l

Cursor End Raster

5

Specifies the cursor end raster address

R12
R13.

Start Address (H)
Start Address (l)

16

Specify the display start address

R14
R15

Cursor Address (H)
Cursor Address (l)

16

Specify the cursor display address

R1a

Horizontal Virtual Screen Width

a

Specifies the length of one row in memory space
for horizontal scrolling

R19
R20

Multiplexing Duty Ratio (H)
Multiplexing Duty Ratio (l)

9

Specify the number of rasters for one screen

R2l

Display Start Raster

5

Specifies the display start raster within a character
row for smooth scrolling

R22

Mode Register

5

Controls the display mode

Note: For more details of registers, refer to "Internal Registers·.

948

HITACHI

HD63645/HD64645/HD64646
Table 6 Internal Register Comparison between LCTC and CRTC
Reg.
No.

LCTC HD83645/HD64845/HD64846 Comparison

CRTC HD6845

AR

Address Register

Address Register

RO

Horizontal Total Characters

R1

Horizontal Displayed Characters

Equivalent to CRTC

Horizontal Total Characters
Horizontal Displayed Characters

R2

Particular to CRTC ;

Horizontal Sync Position

R3

unnecessary for LCTC

Sync Width

R4

Vertical Total Characters

R5

Vertical Total Adjust

R6

Vertical Displayed Characters

R7

Vertical Sync Position
Interlace and Skew

R8
R9

Maximum Raster Address

Equivalent to CRTC

-----------------------------R10
Cursor Start Raster

Maximum Raster Address
Cursor Start Raster

R11

Cursor End Raster

Cursor End Raster

R12

Start Address (H)

Start Address (H)

R13

Start Address (L)

Start Address (L)

R14

Cursor Address (H)

Cursor (H)

R15

Cursor Address (L)

Cursor (L)

R16

Particular to CRTC ;

Light Pen (H)

R17

unnecessary for LCTC

Light Pen (L)

R18

Horizontal Virtual Screen Width

R19

Multiplexing Duty Ratio (H)

R20

Multiplexing Duty Ratio (L)

R21

Display Start Raster

R22

Mode Register

Additional registers for LCTC

HITACHI

949

HD63645/HD64645/HD64646
Functional Description
Programmable Screen Format
Figure 8 illustrates the relation between LCD

display screen and registers. Figure 9 shows a
timing chart of signals output from the LCTC
in mode 5 as an example.

i - - - - - - - - - - - H o r i z o n t a l Total Characters ( R O ) - - - - - - - - - - - - - + I

(R2l)
Start
Raster

Horizontal Displayed Chars. (Rl) - - - - - - 1

~=~~t-

Start Address (R12)

CPU
Memory Write Time

Display Period

, ,,....,Display
Start
Raster
Raster
Address

Address

(R2l)

(R9)

(1 Character)

Figure 8 Relation between Display Screen and Registers

950

HITACHI

HD63645/HD64645/HD64646

MCLK

DISPTMG

CUDISP

(Timing
latCh)
MAO-MA15

RAO-RA4

lJlJ1JlJlJ1Jl._____ JlJU1J1J1J1JUl __ J1JlJlJl __ JUlJ1J1JlJLJ
J
JIl~______________________________________________~~

=
0

1

2

3

4

5

~~~

~_

______________________________ ___________
_Jx~

FLM

_ _ _ _ _ _ _ _ _ _ _ _ _ _......., - ~~L~:l~-IL__ _ _ _ _ _ __

M

____________________________ ___________
~x~

CLl

fif

CL2

~ ____ JlfUl1UUUl__
* ______

LUO

____

LUl

_ _ _ _ _ _~ ____ ~w.l_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

LU2

_ _ _~~ ____ ~"_2_ _ _ _ _ _ _ _ _ _ _ _ _ _

LU3

_ _ _---'~ ____ ..MJ\iv.MA3"-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _M

LDO

-----'YJ'1'fJJ1'fJJJJ~~~~JJJIID_ _ _ _~XX

LDl

_YJJJJJJJJJJJ1 ~~~~JJJIID

YJ

LD2

_YJ'1'fJJ1'fJJJJ~~~~JJJIID

XX

LD3

_YJJJJJJJJJJJ1 ~~~~JJJIID

YJ

~~~~~~~_~_-l_ _ _ _ _ _ _ _ _ _ _ _ __JXX

~-----vvvvvvv

-----vvvvvvv

-----vvvvvvv

\IV
M

'fV
___'AJ..
'IV

Note' : Relation between CL 1 and CL2 in the case of HD64646 is differene from
one shown in this chart. Refer to "Difference between HD64645 and
HD64646".

Figure 9

LCTC Timing Chart (In Mode 5: Single Screen, 4·Bit Transfer, Normal
Character Display)

HITACHI

951

HD63645/HD64645/HD64646
Cursor Control

Cursor height
Cursor blink mode

The following cursor functions (figure 10) can
be controlled by programming specific registeJS.
•

A cursor can be displayed only in character
mode. Also, CUDISP Pin must be connected to
MD12 pin to display a cursor.

Cursor display position

Cursor
Start Raster

Cursor
Height

Cursor
End Raster

Figure 10 Cursor Display

952

HITACHI

HD63645/HD64645/HD64646
Character lIIIode and Graphic Mode

The LCTC supports two types of display
modes; character mode and graphic mode.
Graphic mode 2 is provided to utilize software for a system using the CRTC (HD6845).
The display mode is controlled by an OR
between the mode select pins (DIS, G/C, LS,
WIDE, AT) and mode register (R22).
Character lIIIode: Character mode displays
characters by using CG-ROM. The display
data supplied from memory is accessed in 8bit units. A variety of character attribute
functions are provided, such as reverse video,
blinking, nondisplay (white or black) ,by storing the attribute data in attribute RAM (ARAM).

Graphic lIIIode 1: Graphic mode 1 directly
displays data stored in a graphic memory
buffer. The display data supplied from memory is accessed in 16-bit units. Character
attribute functions or wide mode are not
provided. Figure 12 illustrates the relation
between graphic display screen and memory
contents.
Graphic lIIIode 2: Graphic mode 2 utilizes
software for a system using the CRTC
(HD6845). The display data supplied from
memory is accessed in 16-bit units. Character
attribute functions or wide mode are not
provided. The same memory addresses are
output repeatedly the number of times specified by maximum raster register (R9). The
raster address is output in the same way as in
character mode.

Figure 11 illustrates the relation between
character display screen and memory contents.

Reverse
Video

Blinking

+

+

Start

VRAM
ARAM
(Char.
(Attr.
code)
code)
.... 8-bit .... i.,..8-bit ....

7

42

08
20

I

43

00

address --

1st
1st

Row

Row

41

Reverse Video

Blinking

I'

2nd
Row

I

\

1

I

44

2nd
Row

\

I

00

45

00

46

00

1
I

1
1

I
1

I
I
I
I

Figure 1.1 Relation between Character Screen and Memory Contents

HITACHI
- - - - - - - - - - - - - _ ...

_

.. _--_.

__._._.-

953

HD63645/HD64645/HD64646
direction by the character, by setting the
horizontal virtual screen width and updating
the start address. This function is enabled by
programming the horizontal virtual screen
width register (R18).

Horizontal Virtual Screen Width
Horizontal virtual screen width can be specified by the character in addition to the number of horizontal displayed characters (figure
13).

Figure 14 shows an example.
The display screen can be scrolled in any

M
D
1st Line
2nd !Jne

MM
D D ARAM
015

7
I

I

I

I I
I I
I I I
I I I
I I
I
I I
I
I I I I
I
I
I I

M

.

VRAM

(

I

I
I
I
I
I
I
I

I

I
I
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I
I
I

,

I
I
I
I

I
I
I
I

I
I
I

I

I
I
I
I

I

I
I
I
I
I
I

I

I
I

I
I
I
I

I
I
I
I

I I
I I
I

I

I
I
I
I

I
I

I
I

I
I
I I'
I I I
I
I
I I I

I
I
I
I
I
I
I

I
I
I
I
I

I
I
I
I

I
I

1st
Line

\
(
2nd
Line

\

VRAM

ARAM

.... 8-bit ,

8-dit

FF

55

33
I
I
I
I
I
I

I

00

AA

I
I
I
I

CC
I

I

I
I

I
I

Display Screen

I

I
I
I

Figure 12 Relation between Graphic Screen and Memory Contents

i+---Hori;zorltal virtual screen width(R18)

Figure 13 Horizontal Virtual Screen Width

954

HITACHI

I
I

I
I
I
I
I
I
I
I

HD63645/HD64645/HD64646

R1a
Example:
R18 (Horizontal Virtual Screen Width) = 10
R1 (Horizontal Displayed Characters) = 5

5

6

7

a

9

Displayed Ares

u

Perfonning horizontal
scroll by updating
the start address'
Oto4

o
10

11

2

3

12

13

9

New

leT

Figure 14 Ezample of Horizontal Scroll by Setting

HITACHI

Horlzon~l

Virtual Screen Width

955

HD63645/HD64645/HD64646
Smooth Scroll

Wide Display

Vertical smooth scrolling (figure 15) is performed by updating the display start raster,
as specified by the start raster register (R21).
This function is offered only in character
mode.

The character to be displayed can be doubled
in width; by supplying the same data twice
(figure 16). This function is offered only in
character mode, and controlled either by bit 2
of the mode register (R22) or by the WIDE
pin.

Raster
0 ....._ . .- - - 1
Address 1 ....._ . ._ _-1
2 .....- _ - - - 1
31-_. ._ _---1

1

2
3
4

5

4 \ - _. ._ _-1
5 ....._ . .__- - 1

6

61----------;

7

7

Displav start raster address
(R21) = 0

(R21) = 2

(R21) = 1

Figure 15 Example of Smooth Scroll by Setting Display Start Raster Address

4455667788
WIDE

= low

WIDE = High

Figure 16 Example of Wide Display

956

HITACHI

HD63645/HD64645/HD64646
Attribute Functions

The attribute functions are offered only in
character mode, and controlled either by bit 0
of the mode register (R22) or the AT pin. As
shown in figure 18, a character attribute can
be specified by placing the character code on
MDO-MD7, and the attribute code on MDllMD15. MD8-MDlO are invalid.

A variety of character attribute functions
such as reverse video, blinking, nondisplay
(white) or nondisplay (black) can be implemented by storing the attribute data in ARAM (attribute RAM). Figure 17 shows a
display example using each attribute function.

1. Black

2. White

D
3. Blinking

4. Cursor

5. Reverse Video

m

Figure 17 Display Example Using Attribute Functions

MD Input

15

14

13

12

11

10-8

7-0

Function

Nondisplay
(black)

Nondisplay
(white)

Blinking

Cursor

Reverse
video

***

Character Code
': Invalid-

Figure 18 Attribute Code

HITACHI

957

HD63645/HD64645/HD64646
OR Funct10n -Superimposing Charac-

this data as 1 byte.

ters and. Graphics
This function is offered only in character

mode, and controlled by bit 0 of the mode
register (R22) or by the AT pin. Any attribute
functions are disabled when using the OR
function.

The OR function (figure 19) generates the OR
of the data entered into MDO-MD7 (e.g.
character data) and the data into MD8-MD1S
(e.g. graphic data) in the LCTC and transfers

Graphic data
(Charactar data)
j M015

Character data
(Graphic data)

M014 - - - -

M09

r - - - - - - - - - - - -

-

- -

- - - -

-

-

-

-

-

-

- -

- -

-

-

'M07

M06 - - - -

MOl

MOO

1

-

- -

-

-

-

-

-

-

-

-

-

-

-

-

Figure 19 OR Function

958

I

-1-------------- -L --~ ---MOIl

HITACHI

-

-

-

-

-

-

-

-

-

- -

-

- - -

-

_I

HD63645/HD64645/HD64646
DRAM Refresh Address Output Function
The LCTC outputs the address for DRAM
refresh while CLl is high, as shown in figure
20. The 16 refresh addresses per scanned line
are output 16 times, from $OO-$FF.

zontal character display period, the access is
retarded to the next cycle by inserting a latch
to memory address output and buffer memory output. The skew function retards the
CUDISP, DISPTMG, CL2 outputs, and MD
inputs in the LCTC to match phase with the
display data signal.

Skew Function
The LCTC can specify the skew (delay) for
CUDISP, DISPTMG, CL2 outputs and MD
inputs.
If buffer memory and character generator

By utilizing this function, a low-speed memory can be used as a buffer RAM or a character generator ROM.
This function is controlled by pins SKO and
SKl as shown in table 7.

ROM cannot be accessed within one hori-

Table 7 Skew Function
SKO

SK1

Skew Function

0

0
0

No skew
1 character time skew
2 character time skew
Inhibited combination

1

0

DISPTMG

L

CLl

MCLK

MAO-MA7

Display
Memory

Address

.1.

~~:r:SRefreSh

.1. I~:~~~
,Address

Figure 20 DRAM Refresh Address Output

HITACHI

959

HD63645/HD64645/HD64646
Automatic Correction of Down Panel
Raster Address

Easy Mode
This mode utilizes software for systems using
the CRTC (HD6845). By setting MODE pin to
high, the display mode and screen format are
fixed as shown in table 8, With this mode,
software for a CRT screen can be utilized in a
system using the LCTC, without changing
the BIOS.

When the LCTC mode is set for character
display and dual screen, memory addresses
(MA) and raster addresses (RA) are output in
such a way as to keep continuity of a display
spread over the two panels. Therefore users
can use the LCTC without considering the
multiplexing duty ratio (the number of vertical dots of a screen) or the character font.
(See figure 21.)

Table 8 Fixed Values in Easy Mode
Reg. No.

Register Name

Fixed Value (decimal)

R9

Maximum raster address
Cursor start raster
Cursor end raster
Horizontal virtual screen width
Multiplexing duty ratio (H)
Multiplexing duty ratio (l)
Display start raster
Mode register

7
6
7
Same value as (R 1)
99 (in dual screen mode)
199 (in single screen mode)

R10
R11
R18
R19

R20
R21
R22

o
o

Up panel

r----AB8------

Characters are continuous in spite of
the break of a screen.

Down panel

Figure 21 Example of the Display in the Character Mode

960

HITACHI

HD63645/HD64645/HD64646
3Ystem Configuration and Mode
setting
LCD System Configuration

Hardware Configuration and Mode Setting

The SCIeen configuration, single or dual, must
be specified when using the LCD system
(figure 22).
Using the single screen configuration, you
can construct an LCD system with lower cost
than a dual SCIeen system, since the required
number of column drivers is smaller and the
manufacturing process for mounting them is
simpler. However, there are some limitations,
such as duty ratio, breakdown voltage of a
driver, and display quality of the liquid crystal, in single screen configuration. Thus, a
dual screen configuration may be more suitable to an application.
The LCTC also offers an 8-bit LCD data
transfer function to support an LCD screen
with a smaller interval of signal input terminals. For a general size LCD screen, such as
640 x 200 single, or 640 x 400 dual, the usual
4-bit LCD data transfer is satisfactory.

The LCTC supports the following hardware
configurations:
Single or dual screen configuration
4-or 8-bit LCD data transfer
and the following screen format:
Character, graphic 1, or graphic 2 display
Normal or wide display (only in character
mode)
OR or attribute display (only in character
mode)
Also, the LCTC supports up to 40 Mbits/s of
large screeen mode (mode 13) for large
screen display. This mode is provided only in
graphic 1 mode.
Table 9 shows the mode selection method
according to hardware configuration and
screen format. Table 10 shows how they are
specified.

4
Data

Column Driver (Upper psnel)

[L~@
."c~

LCD Upper Panel

c::

0

Data

E

§

Column Driver

LCD Lower Panel

u
Single screen

4

Data --7''--'' Column Driver (Lower psnel)
Dual screen

Figure 22 Hardware Configuration According to Screen Format

HITACHI

961

HD63645/HD64645/HD64646
Table 9 Mode Selection
Hardware Configuration

Screen Format

Screen

LCD Data
Trensfer

Configu-

4-bit

Single

ration

Screen
Size
Normal

Character!
Graphic
Character

Normal!
Wide
Normal

Attribute!
OR

AT

OR
Wide

AT

Maximum
data transfer
apeecI(Mbpa) Mode No.
20
5
10

6

20
20
20

8

10

2

AT

20
20
40
20

3
4
13
9

AT

10

10

20
20

11
12

OR

Dual

Normal

Graphic 1
Graphic 2
Character

Normal

AT

7

OR

Wide

AT
OR

8-bit

Single

Large
Normal

Graphic 1
Graphic 2
Graphic 1
Character

Normal
Wide

OR
OR

Graphic 1
Graphic 2
Note:

962

Maximum data transfer speed indicates amount of the data read out of a memory. Thus. the
data transfer speed sent to the LCD driver in wide function is 20 Mbps.

HITACHI

HD63645/HD64645/HD64646
Mode List
Table 10 Mode List
Pin Name
No. Mocla Name

1

Dual-screen
character

2

Dual-screen
wide character

3
4

Dual-screen graphic 1
Dual-screen graphic 2
Single-screen
character

5
6

Single-screen
wide character

7

Single-screen
graphic 1
Single-screen
graphic 2
8-bit character

8

9

10 8-bit wide
character
11 8-bit graphic 1
12 8-bit graphic 2
13 Large screen

DIS G/C LS WIDE AT
0 0 0 0
0 0 0
0 0
0
0 0 1 1
1 1 0 0 1
1 1 0 0 0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1
0
0 0

0
0
0
0
0
0
0

0
0
0
0
0

0

0

0
0

0
1
0

1
0
0
0

Scram

ConI'g.

Dual
screen

Graphic/
ChIIracter
Character

Data
T......
4-bit
x2

WIde

DiIpIay

Attribute

Normal

OR

Wide

OR

AT
AT

Graphic
Single
screen

Character

4-bit

Normal

OR

Wide

OR

AT
AT
Graphic

Single
screen

Character

8-bit

Normal

OR

Wide

OR

AT
AT

1
0

Graphic
Dual
screen

4-bit
x2

The LCTC display mode is determined' by pins DIS (pin 55), G/C (pin 58), LS (pin 56) , WIDE (pin 54) ,
and AT (pin 57). As for G/C, WIDE, and AT, the OR is taken between data bits 0,2, and 3 ofthe mode
register (R22). The display mode can be controlled by either one of the external pins or the data bits of
R22.
Note:

The above 5 pins have 32 status combinations (high and low) . Any combinations other than the
above are prohibited, because they may cause malfunctions. If you set an prohibited combination, set the right combination again.

HITACHI

963

HD63645/HD64645/HD64646
Internal Registers
The HD63645/HD64645/HD64646 has one
address register and fourteen data registers.
In order to select one out of fourteen data
registers, the address of the data register to
be selected must be written into the address
register. The MPU can transfer data to/from
the data register corresponding to the written address.
To be software compatible with the CRTC
(HD6845), registers R2-R8, R16, and R17,
which are not necessary for an LCD are
defined as invalid for the LCTC.

Address Register (AR)
AR register (figure 23) specifies one out of 14
data registers. Address data is written into
the address register when RS is low. If no
register corresponding to a specified address
exists, the address data is invalid.

Horizontal Total Characters Register
(RO)
RO register (figure 24) specifies a horizontal
scanning period. The total number of horizontal characters less 1 must be programmed
into this 8-bit register in character units. Nht
indicates the horizontal scanning period including the period when the CPU occupies
memory (total number of horizontal characters minus the number of horizontal
displayed characters). Its units are, then,
converted from time into the number of
characters. This value should be specified
according to the specification of the LCD
system to be used.

Data Bit

716151413121110
-I - 1- 1Register address

Note the following restrictions
Nhd + ~

Data Bit

1, 6, 7, 8, 10, 11, 12, 13

2

2,3,4

4

Horizontal Displayed Characters Register (R1)
R1 register (figure 25) specifies the number of
characters displayed per row. The horizontal
character pitches are 8 bits for normal character display and 16 dots for wide character
display and graphic display.
Nhd must be less than the total number of
horizontal characters.

Maximum Raster Address Register (R9)
R9 register (figure 26) specifies the number
of rasters per row in characters mode, consisting of 5 bits. The programmable range is 0 (1
raster/row) to 31 (32 rasters/row).

Cursor Start Raster Register (R10)
R10 register (figure 27) specifies the cursor
start raster address and its blink mode. Refer
to table 11.

Data Bit

Program Unit R/W

716151413121110

W

Nhd (Displayed characters)

Character

W

Figure 25 Horizontal Displayed
Characters Register

Program Unit R/W

Data Bit

71 61514131211 10
Nr
-1-1-1

W

Figure 24 Horizontal Total
Characters Register
964

m

5,9

Program Unit R/W

Character

Nht + 1

Mode No.

Figure 23 Address Register

716151413121110
Nht (Total characters - 1)

;:iii

Program Unit R/W

Raster

W

Figure 26 Maximum Raster Address
Register

HITACHI

HD63645/HD64645/HD64646

< ..... >

Horizontal Virtual Screen Width Register (R1B)

32- or 64-frame

R18 register (figure 31) specifies the memory
width to determine the start address of the
next row. By using this register, memory
width can be specified larger than the number of horizontal displayed characters. Updating the display start address facilitates
scrolling in any direction within a memory
space.

Cursor End Raster Register (R11)
Rll register (figure 28) specifies the cursor
end raster address.

Start Address Register (H/L)(R12/R13)
R12/R13 register (figure 29) specifies a buffer
memory read start address. Updating this
register facilitates paging and scrolling. R14/
R15 register can be read and written to/from
theMPU.

Cursor Address Register (H/L) (R14/R15)
R14/R15 register (figure 30) specifies a cursor
display address. Cusor display requires setting R10 and Rll, and CUDISP should be
connected with MD12 (in character mode).
This register can be read from and written to
the MPU.

The start address of the next row is that of
the previous row plus Nir. If a larger memory
width than display width is unnecessary, Nir
should be set equal to the number of horizontal displayed characters.

Multiplexing Duty Ratio Register (H/L)
(R19/R20)
R19/R20 register (figure 32) specifies the
number of vertical dots of the display screen.
The programmed value differs according to
the LCD screen configuration.
In single screen configuration:
(Programmed value) = (Number of vertical
dots)-l.

Table 11 Cursor Blink Mode
B

P

Cursor blink mode

o
o

0
1
0
1

Cursor on; without blinking
Cursor off
Blinking once every 32 frames
Blinking once every 64 frames

1
1

Data Bit

Program Unit R/W

716151413121 1 10
Memory address (H) (R12)
Memory address (L) (R13)

Memory
address

R/W

Figure 29 Start Address Register
Data Bit

Program Unit R/W

716151413121110

-I B 1 P 1Ncs (Raster address)

Data Bit
Raster

716151413121110

Figure 27 Cursor Start Raster Register

Memory address (H) (R14)
Memory address (L) (R 15)

Data Bit

Program Unit R/W

W

Memory
address

R/W

Figure 30 Cursor Address Register

Program Unit R/W

716151413121110
- 1

-I - 1Nee (Raster address)

Raster

W

Figure 2B Cursor End Raster Register

HITACHI

965

HD63645/HD64645/HD64646
In dual screen configuration:
(Programmed value) =
(Number of vertical dots)
2

should be equal or less than the maximum
raster address. Updating this register allows
smooth scrolling in character mode.
1.

Mode Register (R22)

DIsplay s~ Raster Register (R21)
R21 register (figure 33) specifies the start
raster of the character row displayed on the
top of the screen. The programmed value

Data Bit

Program Unit

The Or of the data bits of R22 (figure 34)
register and the external terminals of the
same name determines a particular mode.
(figure 35)

RtN

Data Bit

Program Unit

RtN

W

716151413121'10
- 1- 1- 1 Raster address

Raster

W

716151413121'10
Nir (No. of chars. of virtual width)

Character

Figure 31 Horizontal Virtual Screen
Wklth Register

Data Bit

Program Unit

RtN

Raster

w

Figure 33

Display Start Raster Register

Program Un~

w

NcI (Number of .-s - 1) (R20)

Figure 34 Mode Register

• : Number of rasters

Figure 32

966

Multiplexing
Register

Duty

Ratio

HITACHI

RtN

HD63645/HD64645/HD64646

~

AT

6

)

~

(data bit 0)

~

BlE
(data bit 1)

WIDE
(data bit 2)

G/C
(data bit 3)

ON/OFF
(data bit 4)

Mode Register
(R22)

Notes: 1.

ON/OFF
(Pin 53)

G/C"
(Pin 58)

WIDE
(Pin 54)

BlE

AT

(Pin 51)

(Pin 57)

AT (valid only when G/e is low (character mode»
AT = High: Attribute functions enabled, OR function disabled.
AT = low: OR function enabled, attribute functions disabled.

2.

BLE (valid only when G/e is low (character mode»
BlE = High: Blinking enable on the character specified by attribute RAM
BlE = low: No blinking

3.

WIOE (valid only when G/e is low (character mode»
WIDE = High: Wide display enabled
WIDE = low: Normal display

4.

G/e
G/C
G/C

5.

= High:

Graphic 1 display (when AT

= low) or Graphic 2 display (when AT = High)

= low: Character display

ON/OFF
ON/OFF = High: Display on state
ON/OFF = low: Display off state

Figure 35 Correspondence between Mode Register and External Pins

HITACHI

967

HD63645/HD64645/HD64646
Restrictions on Programming Internal
Registers
Note when programming that the values you
can write into the internal registers are
restricted as shown in Table 12.

Table 12 Restrictions on Writing Values into the Internal Registers
Function

Restrictiona

Display Format

1

<

Nhd

Nhd +

<

Register

Nht + 1 :iii 256

16

m *1

RO, Rl

:iii Nht + 1

(No. of vertical dots) x (no. of horizontal dots) x
(frame frequency;fFRM) :iii (data transfer speed; V)

{i} *2 x (Nd + 1) x Nhd x
Nhd:iii Nir

{

1~}

. _ • • ow _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ •

Cursor Control

*3 fFRM

________ •

Rl, R19, R20

:iii V
Rl, R18

_________________________________________________________________ _

O:iii Nd:iii 511

R19,R20

O:iii Ncs :iii Nce

Rl0, Rll

Nee:iii Nr

Rl0, R9

Smooth Scroll

Nsr :iii Nr

R21, R9

Memory Width Set

O;'iii Nir :iii255

R18

Notes' * 1 m varies according to the modes. See the following table.
Mode No.

m

5,9
1,6,7,8,10,11,12,13

2

2,3,4

4

*2 Set 1 when an LCD screen is a single screen, and set 2 when dual. Modes are classified as
shown in the following table.
Mode No.

Value

5,6,7,8,9,10,11,12
1,2,3,4,13

2

* 3 Set 8 when a character is constructed with 8 dots, and set 16 when with 16 dots. Modes
are classified as shown in the following table.

1,5,9

Value
8

2,3,4,6,7,8,10,11,12,13

16

Mode No.

968

HITACHI

HD63645/HD64645/HD64646
Reset

2.

RES pin determines the internal state of LSI
counters and the like. This pin does not affect
register contents nor does it basically control
output terminals.

3.

Fixed at high level:

MLCK

4.
Reset is defined as follows (Figure 36):
5.
•
•
•
•

At reset: the time when RES goes low
During reset: the period while RES
remains low
After reset: the period on and after the
RES transition from low to high
Make'sure to hold the reset signal low for
at least 1 Jls

RES pin should be pulled high by users during operation.

Preserve states before reset or fixed at
low level according to the timing when
the reset signal is input:
DISPTMG, CUDISP, MAO-MA15
Fixed at high or low according to mode:
CL2
Unaffected:
DBo-DB7

Reset State of Registers
RES pin does not affect register contents.
Therefore, registers can be read or written
even during a reset state; their contents will
be preserved regardless of reset until they
are rewritten to.

Notes for H063645/H064645/H064646
Reset State of Pins
1.
RES pin does not basically control output
pins, and operates regardless of other input
pins.
2.
1.

Preserve states before reset:
LUO-LU3, LDO-LD3, FLM, CL1, RAO-RA4

The HD63645/HD64645/HD64646 are
CMOS LSIs, and it should be noted that
input pins must not be left disconnected,
etc.
At power-on, the state of internal registers becomes undefined. The LSI operation is undefined until all internal registers have been programmed.

IL

RES - - - - - - - - . .

,\

I

;"",1'-

Vee - O.5V

O.8V~ K:~_-=--=-=~_
__

,_ ~_

l/ls min
During reset

After reset

At reset

Figure 36 Reset Oefinition

HITACHI

969

HD63645/HD64645/HD64646
Absolute Mazimum Ratings
Item

Symbol

Supply voltage

Vee

Value
-0.3 to +7.0V

Terminal voltage

Yin

-0.3 to Vee +0.3 V

Operating temperature

Topr

-20·C to +75·C

Storage temperature

Tstg

- 55·C to + 125·C

Note

2

2

Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation
should be under recommended operating conditions (Vee = 5.0 V ± 10%. GND = 0 V. Ta
= - 20·C to + 75·C). If these conditions are exceeded. it could affect reliability of LSI.
2. With respect to ground (GND = 0 V)

Electrical Characteristics
DC Characteristics (Vce
otherwise noted)

= 5.0V ±10%,

Item
Input high voltage

GND

= OV,

Symbol Min
RES.
SK1

MODE.

SKO,VIH

Vee-0.5

Typ

= -20·C

to +75·C, unless

Max

Unit

Vee+0.3

V

DCLK. ON/OF'F

2.2

Vee+0.3

V

All others

2.0

Vee+0.3

V

-0.3

O.B

Input low voltage

All others

Output high voltage

TTL interface 1

VOH

Output low voltage

CMOS interface 1
TTL interface

VOL

2.4

All inputs except
DBo-DB7

Three state (off-state) DBo- DB7
leakage current

irSL

Current dissipation 2

lee

T8IIt
Condition

V
V

V

Vee-O.B

CMOS interface
Input leakage current

Ta

0.4

V

O.B

V

-2.5

+2.5

-10

+10
10

rnA

Notes: 1. TIL Interface; MAO-MA15. RAO-RA4. DISPTMG. CUDISP. DBO-DB7. MCLK
C-MOS Interface; LUO-LU3. LDO-LD3. CL 1. CL2. M. FLM
2. Input/output current is excluded. When input is at the intermediate level with CMOS.
excessive current flows through the input circuit to power supply. Input level must be fixed
at high or low to avoid this condition.
3. If the capacitive loads of LUO-LU3 and LDO-LD3 exceed the rating. noise over 0.8 V may
be produced on CUDISP. DISPTMG. MCLK. FLM and M. In case the loads of LUO-LU3 and
LDO-LD3 are larger than the ratings. supply signals to the LCD module through buffers.

970

HITACHI

HD63645/HD64645/HD64646
AC Characteristics
CPU Interface (HD63645 68 family)
(Vee = 5.0V ± 10%, GND = OV, T. =-20'C to

+

7S'C, unless otherwise noted)

Item

Symbol

Min

Unit

Figure

Enable cycle time

tevcE

500

ns

37

Enable pulse width (high)

Typ

Max

PwEH

220

ns

Enable pulse width (low)

PwEL

220

ns

Enable rise time

tEr

25

ns

Enable fall time

tEl

25

ns

es,
es,

RS, R/W setup time

tAS

RS, R/W hold time

70

ns

tAH

10

ns

DBo-DB7 setup time

tos

60

ns

DBo-DB7 hold time

tOHW

10

DBo-DB7 output delay time

tOOR

DBo-DB7 output hold time

tOHR

ns

150
20

ns
ns

1 4 - - - - - - - t C Y C E --------i~
tEl

E

2.0 V "l"'---I
,0.8V

CS
RS

R/W

DB o-DB 7
(input)

D80 - DB 7
(output)

2.4V
Data Valid
0.8V

Figure 37 CPU Interface (HD63645)

HITACHI

971

HD63645/HD64645/HD64646
CPU Interface (HD64645 and HD64646-80famlly)
(Vee = 5.0V ± 10%, GND = OV, T. =-20·C to + 75·C, unless otherwise noted)
Item

Symbol

Min

RD high level width

twROH

190

ns

RD low level width

twROL

190

ns

WR high level width

twwRH

190

ns

WR low level width

twwRL

190

ns

es,
es,

RS setup time

tAS

ns

RS hold time

tAH

ns

DBo-DB7 setup time

tosw

0
0
100

DBo-DB7 hold time

tOHW

0

DBo-DB7 output delay time

tOOR

DBo-DB7 output hold time

tOHR

CS

2.0V

1\

ns

ns
ns

If
f-

...;

~

t-

-

I

~

Figure
38

ns

,

...;

tWROL

Unit

150

~ IIf-

tAs

Max

20

O.8V'j r-

RS

Typ

,

:.-.

tAS

~

tAH

2.0V
tWROH

1\

O.8V
twwRH

-,

J
B7

twwRL

,

II

2.0V

-

O.8V

.. --

tOOR

2.4V

I

\

r--

Output

O.4V

I

\

tOHR

\

I

tosw

~
O.8V

If

-,

Input

~

j

Figure 38 CPU Interface (HD64645 and HD64646)

972

HITACHI

toHW

HD63645/HD64645/HD64646
AC Characteristics (Cont)
Memory Interface
(Vee = B.OV ± 10%, GND = OV, T. =-20·C to

+ 7B·C, unless otherwise noted)
Typ

ltam

Symbol

Min

DCLK cycle time

tcvco

100

DCLK high level width

twOH

30

DCLK low level width

twOL

30

DCLK rise time

to,

DCLK fall time

tOf

20

MCLK delay time

Max

20

toMO

60

MCLK rise time

tM,

30

MCLK fall time

tMf

30

MAO-MA 15 delay time

tMAo

MAO-MA 15 hold time

tMAH

RAQ-RA4 delay time

tRAO

RAQ-RA4 hold time

tRAH

DISPTMG delay time

tOTO

150
10
150
10
150.

DISPTMG hold time

tOTH

CUDISP delay time

teoo

CUDISP hold time

teOH

CL1 delay time

tCL10

CL1 hold time

tCL1H

CL1 rise time

tCL1,

CL1 fall time

teLIf

10
150
10
150
10
50
50

MDO-MD15 setup time

tMOS

30

MDO-MD15 hold time

tMOH

15

HITACHI

Unit

Figure

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

39

973

HD63645/HD64645/HD64646

tCYCD

DClK

MCLK

CL1

MDO-MD15
(input)

Figure 39 Memory Interface

974

HITACHI

HD63645/HD64645/HD64646
AC Characteristics (Cont)
LCD Interface t (8D63646 and 8D64646)
(Vee == 5.0 V ± to%, GND == OV, T. ==-20'C to

+ 7S'C)
Typ

ltam

Symbol

Min

Unit

Figure

Display data setup time

tlDS

50

ns

40

Display data hold time

tLDH

100

ns

CL2 high level width

twCUH

100

ns

CL2 low level width

twCUl

100

ns

FlM setup time

tFS

500

ns

tFH

300

ns

FlM hold time

Max

Cl1 rise time

tClI,

50

ns

Cll fall time

tellf

50

ns

CL2 rise time

teu,

50

ns

teUf

50

ns

CL2 fall time
Note: At fCL2

= 3 MHz

I

LUO-LU3
LDO-L03

~I

Vcc-O.8V

,\

O.8V

I---\.os-

I

O.8V

~

1\

twcL2L

twcL2H
tCL2,

tCL2f

,

If
CL1

..

V~-O.8V

O.8V
tFS

4-

tFH

tc:;----+

tclk

FLM

tlDH

Vcc-O.8V

CL2

f

Vcc-O.8V
O.8V

~

~

Figure 40 LCD Interface

HITACHI

975

HD63645/HD64645/HD64646
AC Characteristics (Cont)
LCD Interface 2 (H064646 at fCL2 = 3 MHz)
(Vee = 5.0V ± 10%, aND = OV, T. =-20'C to

+ 7S'C)

Symbol

Min

tFs

500

FLM hold time

tFH

300

M delay time

tOM

Item
FLM stetup time

CL1 high level width

Typ

Max

Unit

Figure

ns

41

ns

200

ns

tCL1H

300

ns

Clock setup time

tsCL

500

ns

Clock hold time

tHCL

100

ns

Phase difference 1

tpOl

100

ns

Phase difference 2

tp02

500

ns

CL2 high level width

tcL2H

100

ns

CL2 low level width

tcL2L

100

ns

tcL2r

50

CL2 fall time

tcL2f

50

Display data setup time

tLOS

80

Display data hold time

tLOH

100

CL2 rise time

Display data delay time

ns
ns
ns

30

tLOO

LCD Interface 3 (H064646 at fCL2 = 5 MHz)
(Vee = 5.0 V ± 10%, aND = OV, T. =-20'C to

ns

ns

+ 7S'C)

Item

Symbol

Min

Unit

Figure

FLM setup time

tFo

500

ns

41

FLM hold time

tFH

500

ns

M delay time

tOM

CL 1 high level width

tCL1H

300

ns
ns

Typ

Max

200

ns

tsCL

500

Clock hold time

tHCL

100

ns

Phase difference 1

tpOl

70

ns

Phase difference 2

tp02

500

ns
ns
ns

Clock setup time

. tcL2H

50

CL2 low level width

tcL2L

50

CL2 rise time

tCL2r

50

ns

CL2 fall time

tCL2f

50

ns

CL2 high level width

Display data setup time

tLOS

30

Display data hold time

tLOH

30

Display data delay time

tLOO

976

HITACHI

ns
ns

30

ns

HD63645/HD64645/HD64646

FlM

-------L:~-O.8V. "'~~;~8Y

Cll

_____. . ./

O.8V ____________

M

___________________ .O_.8_V________

tDM)(~V~cc--~O~.=8~V-----------.~

tCL1H---.-.i
Cll

----------------t---"i~~~tSCL_---+l 11----1-----------

i----'tpD2---.J
CL2

lUO- lU4 -------.. Jt-"'---""'"""ll ,----------------,..,..-....,..--"\ , - - - " "
lDO-lD4 - - - - - - ' 1'-----'1

Figure 41 LCD Interface

HITACHI

977

HD63645/HD64645/HD64646.
AC Characteristics
TTL Load
Terminel

RL

R

C

Remarks

DBo-DB7

2.4kO

11 kO

130pF

tr, tf: Not specified

MAO-MA15, RAO-RAA, DISPTMG, CUDISP

2.4kO

11kO

40pF

MCLK

2.4kO

11 kO

30pF

tr, tf: Specified

All diodes: 1S2074@

Capacitive Load
Terminal

C

Remarks

_C_L2_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_5_0.:..pF
_ _ _ _ _ _ _ tr, tf: Specified
CL1

200pF

_LU_O_-_LU_3_,_L_D_o-_L_D_3_,_M_ _ _ _ _ _ _ _ _ _1_5_0.:..pF
_ _ _ _ _ _ _ tr, tf: Not specified
~

~~

o

Refer to user's manual (No. 68-1-160) and application note (No. ADE-502-OO3) for detail of this
product.

978

HITACHI

HD66503------------(240-Channel Row Driver with Internal
LCD Timing Circuit)
-PreliminaryDescription
The HD66503 is a row driver for liquid
crystal dot-matrix graphic display systems.
This device incorporates 240 liquid crystal
driver and an oscillator, and generates
timing signals (AC switching signals and
frame synchronizing signals) required for
the liquid crystal display. Combined with
the HD66520, a 160-channel column driver
with an internal RAM, the HD66503 is
optimal for use in displays for portable
information tools.

Features
•
•
•
•
•
•
•
•
•

LCD timing generator: 11120, 11240 duty
cycle internal generator/external input
switching
AC signal waveform generator: Pin
programmable 1-63 line inversion
Recommended display duty cycle:
1/120, 1/240
Number of LCD driver: 240
High voltage: 8-V to 28-V LCD drive
voltage
Low power consumption: 100 /LA
(during display)
Internal display off function
Oscillator circuit with standby function:
130 kHz (max)
Display timing operation clock: 65 kHz
(max) (operating at 1/2 system clock)

HITACHI
979

HD66503
Intemal Block Diagram
X1-X240

-

VSLVSLV'L~~~~3[===I.---~::::---..I::==1~~~~~~~V1RVSRVSR
~
VEEL
VEER
LCD driver (LO)

vee

GNJ

CUP

DUTYS

RESET

osc,

LCD timing
generator
CL1M

MSS

TEST

CR C

R

Cll

FLM

M

DOC

1. LCD driver

3. Bidirectional shift register (240 bits)

Selects one of four LCD drive voltage levels
(Vi, V2, V5, and V6) depending on a
combination of shift register data and the
value of M, the AC switching signal, and
transfers that voltage to the output circuit.

Shifts internally generated data or data
input from the FLM pin at each falling edge
of the data transfer clock CLl. Shift direction
can be switched using SHL signals.

2. Level shifter
Boosts 5-V signals to high voltage signals
for the LCD drive.

980

HITACHI

HD66503
Pin Description
Classification
Power supply

Control signals

Pin Name

I/O

Number
of Pins

VCC1.
VCC2
GND

Power supply

2

Power supply

1

LCD drive
level power
supply

Power supply

2

VCe-VEE: LCD
drive circuits
power supply

244
269

LCD select
high-level
voltage

Input

2

LCD drive level
power supply
See figure 1.

V2L. V2R

241
272

LCD select
low-level
voltage

Input

2

V5L. V5R

242
271

LCD deselect
low-level
voltage

Input

2

V6L. V6R

243
270

LCD deselect
high-level
voltage

Input

2

M/S

266

Master/slave
switching

Input

Control signal
enabling/disabling
LCD timing
generator operation.
Timing generator
halts at low level.
Timing generator
operates at high
level. (Refer to Pin
Functions for details.)

DUTY

259

Display duty
ratio select

Input

Low level: 1/120
display duty ratio
High level: 1/240
display duty ratio

MWSoto
MWS5

257
256
255
254
253
252

AC switching
signal cycle
select

Input

MEOR

258

AC switching
signal EOR

Input

CR.C.R

247
248
249

Oscillator

Symbol

Pin No.

VCC1.
VCC2
GND

246
267

VEEL.
VEER

245
268

V1L. V1R

250

HITACHI
- - --------

6

Functions
VCe-GND:
logic power supply

Sets cycle for AC
switching signal M
in a line unit (1 to
63). The term 0 is
for external input.
(Refer to Pin
Functions for
details.)
Selects EOR
processing for
frame inversion
waveform and AC
signal M.

3

These pins are
used as shown in
figure 2 in master
mode. and as
shown in figure 3
in slave mode.

981

---------

HD66503
Pin Description (Cont'd.)
Number
of Pins

Classification

Symbol

Pin No.

Pin Name

I/O

Control signals

RESET

261

Reset

Input

Stops oscillator
circuits, initializes
internal counter,
and switches
display off. (Refer
to Pin Functions
for details.)

LCD timing

Cl1

263

Display data
transfer

I/O

Display-data
transfer clock 1/0
pin. (Refer to Pin
Functions for
details.)

FLM

264

First line
marker

1/0

Functions

First line marker

1/0 pin. (Refer
to Pin Functions
for details.)

LCD drive output

M

262

AC switching
signal

1/0

AC control 1/0
pin for LCD drive
output.

SHL

251

Shift direction
select

Input

FLM -> X1 -> X240
at low, and FLM ->
X240 -> X1 at high.

DISPOFF

260

Display off
signal

Output

Fixes LCD drive
output to select
high level. When
low level, LCD
drive outputs X1
to X240 are set to
V1, the LCD select
high level. Display
can be tu rned off
by setting a segment
driver to level V1.

DOC

265

Display off
control
signal

I/O

Inputs and outputs
a display-off control
signal in response
to the DISPOFF
signal and oscillator
startup sequence.
(Refer to Pin
Functions for details.

X1 to
X240

240
1

LCD drive
output

Output

Note: 30 input/outputs (excluding driver block)

982

HITACHI

240

Selects one from
among four levels
(V1, V2, V5, and V6)
depending on the
combination of M
signal and display
data. See figure 4.

HD66503
_______________ \I1

_______ ____ ys
~
__

_ ______V5

_________ Y2

Figure 1

LCD Drive Levels

or

~':l

~

'--po

i01

OscUlator Connection in Master Mode

1

Figure 3

R

External clock

Internal oscillation

Figure 2

"j

OR

vee

Open

!

!

OR

R

OscUlator Connection in Slave Mode

o

Msignall

Displaydata~
Oulputlevel! (V2) I(V6) I (Vl) I (V5)!

Figure 4

LCD Drive Output

HITACHI

983

----------------------

HD66503
Pin Functions
MIS (Input): Starts and stops the LCD
timing generator. Also determines 110 of
the following four signal pins: CLl (display
data transfer clock), FLM (first line marker),
M (AC switching signal), and DOC (display
off control), depending on whether the LCD
timing generator is operating or not. See
table 1.
MWSO to MWS5, MEOR (Input): AC
switching signal M, in synchronization
with CL 1, is generated according to the
value (an integer 1 to 63) selected by 6-bit
MWSO to MWS5, where MWSO takes the
LSB and MWS5 takes the MSB.
When the AC switching signal EOR
(ME OR) is high, M is exclusively ORed with
the B-waveform AC signal synchronized
with the first line marker (FLM) before
being output from the M pin.

Table 1

When the MWSO to MWS5 bits are all set
to 0 (low), the AC switching signal (M) pin
goes into the input state, and becomes the
input pin for AC signals from an external
controller.

RESET (Input): The following initializatio.n
operations are performed when RESET IS
low:
1. Stops internal oscillator or external
oscillator clock input.
2. Initializes counters for the LCD timing
generator and the AC switching signal
(M) generator.
3. Switches off the display by driving
display-off control output (DOC) low.
After reset release, the display off
control (DOC) is held low for four frame
cycles (four FLM clock cycles) to prevent
erroneous display during startup.

MIS Function

M/S

Mode

LCD Timing Generator

Low

Slave

Stop

Input

High

Master

1/120 or 1/240 duty cycle control

Output

984

HITACHI

CL 1. FLM. M. and DOC I/O State

HD66503
DOC (Input/Output): Outputs the AND of

FLM (Input/Output): In master mode,

the display-off control status after reset
release and the display-off signal
(DISPOFF) in master mode. The pin is
connected to the DISPOFF pin of the
HD66520, which is normally paired with
the HD66503. The pin inputs an external
display-off control signal from the outside
in slave mode.

FLM outputs the first line marker. In slave
mode, FLM inputs the first line marker. The
shift direction of the FLM can be selected
according to the DUTY and SHL signals, as
shown in table 2.

CLI (Input/Output): In master mode, eLl

Table 2

outputs a 50% duty-ratio data-transfer
clock with double cycles of an internal
oscillator or external clock input cycles.
In slave mode, eLl operates as the input
pin for the external data-transfer clock.

In slave mode, use the DUTY signal at high
level in normal.

DUTY

SHL

High

High

X240 to Xl

Low

Xl to X240

High

X120 to Xl, and X240 to X12l

Low

Xl to X120, and X12l to X240

Low

In bidirectional shift-register timing, data is
shifted at the rising edge of eLl in
accordance with the specifications of the
HD66520 with built-in RAM when used in a
paired configuration. As this is the
opposite of the standard common driver
arrangement, the transfer clock must be in
an inverse phase when paired with
general-purpose column drivers such as
HD66240 and HD66224 T.

Selection of FLM Shift
Direction
Shift Direction of FLM

DUTY (Input): Selects display duty cycle.

The pin selects a 11120 duty cycle at low
level, and a 1/240 duty cycle at high level.

HITACHI

985

HD66503
Liquid Crystal Display Timing

Reset State

TimiDg Generator

The reset state fixes all clocks at low and
clears the internal counter to O. After reset
release, the display-off function continues
for four frame cycles even when the DISP
pin is high.

CLl is a 50% duty-ratio clock that changes
at the falling edge of oscillator clock aSC1.
FLM is a clock signal output once every 240
CLl clock cycles at the rising edge of CR
when the DUTY signal is high, and every
120 CL 1 clock cycles at the rising edge of
CR when the DUTY signal is low.

OSC1
CL1

--------------~)

FLM

Figure 5

FLM

LCD Timing Signals

________ ___ ___ ____ ____

DISpOFF

~n~

2~n~

4~n.

=high
Figure 6

986

3~n~

Reset Timing

HITACHI

5~n,~

__

6~~

HD66503
EB8mpie of System Configuration
Figure 7 shows a system configuration for
a 240 x 320-dot LCD panel using segment
driver HD66520 with internal bit-map RAM.
All required functions can be prepared for
liquid crystal display with just three chips
except for liquid crystal display power
supply circuit functions.

HITACHI

987

HD66503

,,;,

1!J
~~~

240
\
1

=

0-

(\II:!

I"Q

I)
- 0-1\
lSZ
=
~ ~ I)
~

CC
--.- $:!!
J::'::"

-

--- --. ----- ... - ------------ ------ --- -----

=
N

I"')

(\Ie\!
Lno

CC

I"Q

~

J::'::"

-:;

-'

Line scan Direction

=-

w
-' -'

=--

V(~~:~

3 FLM,CL1,M

I

I

LCD driver

HD66503

1

DOC

_, LCD display timing control

D1SPOFF circuit
CR

R

C

,

DUTY SHL

~~

5
f4-tMEOR,MWSO7 _
_
~RESET
1

MIS

I 1 1
V1,V2,V5,V6

V1,V2,V3,V4

I
16

D1SPOFF

AO - A15

8 DBO - DB7
3

CS,WE,m:

I

Power supply circuit

Figure 7

988

System Configuration

HITACHI

vfc

HD66503
Absolute Maximum Ratings
Item
Power voltage

Symbol

Ratings

Unit

Logic circuit

Vee

-0.3 to +7.0

V

2

Leo drive circuit

VEE

Vee-30.0to
Vee +0.3

V

5

VT1

-0.3 to Vee +0.3

V

2.3
4.5

Input voltage
Input voltage

VT2

VEE-o·3to
Vee +0.3

V

Operating
temperature

Topr

-20 to +75

·e

Storage
temperature

Tstg

-40 to +125

·e

Notes:

1.

Notes

If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should
always be used within the limits of its electrical characteristics in order to prevent malfunction or
unreliability.

2.

Measured relative to GND (0 V).

3.

Applies to all input pins except for V1L. V1 R. V2L. V2R. V5L. V5R. V6L. and V6R. and to input/output
pins in high-impedance state.

4.

Applies to pins V 1L. V1R. V2L' V2R. V5L. V5R. V6L. and V6R'

5.

Apply the same voltage to pairs V1L and V1R. V2L and V2R. V5L and V5R. V6L and V6R. and
VEELand VEER'
It is important to preserve the relationships Vee;;' VIL =V 1R ;;, V6L =V6R ;;, V5L =V5R ;;, V2L
V2R;;' VEE'

HITACHI

=

989

HD66503
Electrical Characteristics
DC Characteristics (VCC
Ta -20°C to +75°C)

=

=2.7 V

to 5.5 V, VEE

Measurement
Condition

=8 V

to 28 V, GND

Item

Symbol

Input high
level voltage

VIH

Input low
level voltage

VIL

Output high
level voltage

VOH

IOH =-O.4mA

Output low
level voltage

VOL

IOL= +0.4 mA

0.4

V

2

Driver "on"
resistance

RON

VCC- VEE=2BV,
load current: :t 150 IJA

2.0

kG

7

I nput leakage
current (1)

11L1

VIN=OtoVCC

-1.0

1.0

!IA

I nput leakage
current (2)

IIL2

VIN = VEE to VCC

-25

25

!IA

:3

Operating
freq uency (1)

fopr1

Master mode (external
clock operation)

10

200

kHz

4

Operating
frequency (2)

f opr2

Slave mode
(shift register)

0.5

500

kHz

Oscillation
frequency (1)

fOSC1

Cf = 100 pf :t5%,
Rf = 47 kG :t2%

70

100

130

kHz

5

Oscillation
frequency (2)

fOSC2

Cf = 220 pf :t5%,
Rf = 51 kG :t2%

21

30

39

kHz

5

Power
consumption (1)

IGND1

Master mode
1/240 duty cycle,
Cf=220pF,Rf=51 kG

BO

,...A

6

Power
consumption (2)

IGND2

Master mode
1/240 duty cycle
external clock
f opr2 = 30 kHz

10

!IA

6

Power
consumption (3)

IGND3

Slave mode
1/240 duty cycle
during operation

10

6

Power
consumption

lEE

Master mode
1/240 duty cycle,
Cf=220pF,Rf=51 kG

20

6

990

Max

Unit

O.B
VCC

VCC

V

0

0.2
VCC

V

=0 V,

Min

Typ

V

VCC
-0.4

HITACHI

Notes

HD66503
Notes:

1.

Applies to input pins TEST, MEOR, MWSO to MWS5, DUTY, SHL, DISP, MS, RESET, and OSC1, and
when inputting to input/output pins CL1, FLM, DOC, and M.

2.

Applies when outputting from input/output pins CL 1, FLM DOC, and M.

3.

Applies to V1LJV1R, V2LJV2R, V5LJV5R, and V6LJV6R. Xl to X240 are open.

4.

Figure 5 shows the external clock specifications.

'Ill

Duty_~' 100%
Exl8n18l
clock

~

OPEN OPEN

I I
OSC1 c OSC21

Min.
Duty
!rep
!fcp

Figure 8
5.

45

Typ. ·Max. Unit
55
%
50
ns
50
ns
50

- - -

Extemal Clock

Connect resistance Rf and capacitance Cf as follows:

~~

~
Figure 9

TlmlDg Components

6.

Input and output currents are excluded. When a CMOS input is floating, excess current flows from
the power supply through to the input circuit. To avoid this, VIH and VIL must be held to VCC and
GND levels, respectively.

7.

Indicates the resistance between one pin from Xl to X240 and another pin from the V pins V1LJV1R,
V2LJV2R, V5LJV5R, and V6LJV6R, when a load current is applied to the X pin; defined under the
following conditions:
VCC-VEE=28V
V1LJV1R, V6LJV6R = VCC-lIl0 (VCC-VEE)
V5LJV5R, V2LJV2R = VEE + 1/10 (VCC - VEE)
V1LJV1R and V6LJV6R should be near the VCC level, and V5LJV5R and V2LJV2R should be near the
VEE level. All these voltage pairs should be separated by less than
which is the range within
which RON, the LCD drive circuits' output impedance, is stable. Note that
depends on power
supply voltages VCC - VEE' See figure 7.

av,

HITACHI

av

991

HD66503
-r---------------V~

············V1LN1R

tN

······V6UR

~2.8

•••••••••••••.••••

~ 0.8 ••••••••
•••• , •••••••••••. VSLN5R
••••••••••••••••••••••. V2LN2R

VEE

Figure 10

992

RelatioDShip between Driver Output WavefonD
aDd Level Voltage.

HITACHI

HD66503
AC Characteristics (VCC
-20°C to +75°C)

=2.7 V to 5.5 V, VEE =8 V to 28 V, GND =0 V, Ta =

Slave Mode (MIS = GND)
Item

Symbol

Min

CL 1 high-level width

tCWH

500

ns

CL 1 low-level width

tCWL

500

ns

tFS

100

ns

rFH

100

FLM setup time
FLM hold time
CL 1 rise time
CL 1 fall line
Note:

1.

Typ

Max

Unit

Notes

ns

tr

50

ns

tf

50

ns

Based on the load circuit shown in figure 8.

Outputpin~

T

30 pF (including probe cap2C"ance)

r.r

CWH

CL1

FLM

Figure 11

Slave Mode Timing

HITACHI

993

HD66503
Master Mode (MIS = V CCI Cf = 100 pF, Rf = 47 kO)
Item

Max

Unit

tOFLM

500

n5

tOM

500

n5

Symbol

FLM delay time
M delay time
CL 1 high-level width

tCWH

CL 1 low-level width

tCWL

Min

Typ

5
5

Notes

115
115

Master Mode (MIS = V CCI Cf = 220 pF, Rf = 51 kO)
Item

Symbol

FLM delay time

tOFLM

M delay time

tOM

CL 1 high-level width

tCWH

CL 1 low-level width

tCWL

Min

Typ

Max

Unit

500
500

n5

20
20

CL1

FLM

M

Figure 12

994

Master Mode Timing

HITACHI

n5
115
115

Notes

HD66503
Pin Arrangement
272

V2R

X239

2

271

VSR

X238

3

270

VSR

X237

4

269

V1R

X236

5

268

VEER

X235

6

267

Vccca

X234

7

266

MIS

X233

8

265

OOC

X232

9

264

FLM

X231

10

263

CL1

X240

262

M

261

RESET

260
259

NSPOFF
DUTY

258

MEOR

257

MWSO

256

MWS1

255

MWS2

254

MWS3

253

MWS4

252

MWS5

251

SHl
GND

X10

231

250

X9

232

249c:==jC

X8

233

X7

234

247

CR

X6

235

'~IR
246

.vCC1

X5

236

245

VEEl

X,I!----l237

244

J

X3\
X2
X1!

.

V1L

_~Vfil

238

243C

239

242c=:jVSL

1240

241 c=:jV2L

Top view (n01 a TCP view)

HITACHI

995

HD66520------------(160-Channel4-Level Grayscale Display
Column Driver with Internal Bit-Map RAM)
-PreliminaryDescription
The HD66520 is a column driver for liquid
crystal dot-matrix graphic display systems.
This LSI incorporates 160 liquid crystal drive
circuits and a 160 x 240 x 2-bit bit-map
RAM, which is suitable for LCDs in portable
information devices. It als.o includes a
general-purpose SRAM interface so that
draw access can be easily implemented
from a general-purpose CPU. The on-chip
display RAM greatly decreases power
consumption compared to previous liquid
crystal display systems. The chip also
incorporates a four-level grayscale controller
for enhanced graphics capabilities, such as
icons on a screen.

Features

•
•

•
•
•
•
••
•
•
•

996

Duty cycle: 1/64 to 1/240
Liquid crystal drive circuits: 160
High voltage: 8 to 28-V liquid crystal
drive voltage
Grayscale display: FRC Four-level
grayscale display
Grayscale memory management:
Packed pixel
Internal bit-map display RAM: 76800
bits (160 X 240 lines X two planes)
Access time: 80 ns
Low power consumption:
-100 j.LAduringdisplay
-20 mA during RAM access (RAM
access time 250 ns)
On-chip memory management function
Refresh unnecessary
Internal display off function

HITACHI

HD66520
Pin Description
Number
of Pins

Classification

Symbol

Power supply

VCC1
VCC2
GND

VCC
VCC
GND

Input

VEE1.
VEE2

LCD drive
circuit power
supply

Input

V1L. V1R

LCD select
high-level
voltage

Input

2

V2L.V2R

LCD select
low-level
voltage

Input

2

V3L. V3R

LCD deselect
high-level
voltage

Input

2

V4L. V4R

LCD deselect
low-level
voltage

Input

2

LSO.LS1

LSI 10 select
switch pin
o and 1

Input

2

SHL

Shift direction Input
control signal

Reverses the
relationship
between LCD drive
output pins Y and
addresses.

FLM

First line
marker

Input

First line select
signal

CL1

Data transfer
clock

Input

Clock signal to
transfer the line
data to an LCD
display driver
block.

M

AC switching
signal

Input

Switching signal
to convert LCD
drive output to AC

DISPOFF

Display off
signal

Input

Control signal to fix
LCD driver outputs
to LCD select high
level. When low.
LCD drive outputs
Y1 to Y1S0 set to
V1. or LCD select
high level. Display
can be turned off by
setting a common
driver to V1.

TEST

Test pin

Input

LSI test pin (refer
to Pin Functions
for details).

Control signals

Pin No.

Pin Name

110

Function
VCe-GND:
logic power supply

HITACHI

VCe-VEE: LCD
drive circuit
power supply
LCD drive level
power supplies
See figure 1.

Pins for setting LSI
10 no. (refer to
Pin Functions for
details).

997

HD66520
Pin Description (Cont"d.)
Pin Name

1/0

Number
of Pins

AOtoA15

Address
Input

Input

16

Upper 9 bits
(Al5-A7) are used
for the dutydirectional
addresses, and
lower 7 bits (A6-AO)
for the output-pin
directional
addresses (refer to
Pin Functions for
details).

DBOto DB7

Data input!
output

I/O

8

Packed-pixel 2-bit!
pixel display data
transfer (refer to
Pin Functions for
details.)

CS

Chip select
signal

Input

LSI select signal
during draw access
(refer to Pin
Functions for
details.)

WE

Write signal

Input

Write-enable
signal during draw
access (refer to Pin
Functions for
details).

OE

Output enable
signal

Input

Output-enable
signal during draw
access (refer to Pin
Functions for
details).

Yl to
Y160

LCD drive
output

Output

Classification

Symbol

Bus interface

LCD drive output

Pin No.

Note: The number of input outer leads: 47

-

~

--- - - --- -- - -- - - V1
----------·V3
--

- - - - - - - V4

---------- V2

Figure 1

998

LCD Drive Levels

HITACHI

160

Functions

Each Y outputs
one of the four
voltage levels Vl,
V2, V3, or V4,
depending on the
combination of the
M signal and data
levels.

HD66520
Pin Functions
• Control Signals
LSO and LSI (Input): The LS pins can
assign four (0 to 3) ID numbers to four LSIs,
thus making it possible to connect a
maximum of four HD66520s sharing the
same CS pin to the same bus.
Various memory maps can be configured
by combining the LS pins with the SHL pin.

CLI (Input): At each rising edge of data
transfer clock pulses input to this pin, the
latch circuits latch horizontal-line RAM
data and transfers it to the liquid crystal
display driver section.
M (Input): AC voltage needs to be applied
to liquid crystals to prevent deterioration
due to DC voltage application. The M pin is
a switch signal for liquid crystal drive
voltage and determines the AC cycle.

SHL (Input): This pin reverses the
relationship between LCD drive output
pins Y and addresses. When the pin is low,
output pins Yl to Y160 correspond to the
direction from start data to end data in the
display lines, and when the pin is high,
from end data to start data.

DISPOFF (Input): A control signal to fix
liquid crystal driver output to liquid crystal
select high level. When this pin is low,
liquid crystal drive outputs Yl to Y160 are
set to liquid crystal select high level Vl. If
Y pins of the paired common driver are also
set to Vl level, the display can be deleted.
When DISP becomes high, display returns
to normal state.

FLM (Input): When the pin is high, it resets
the display line counter, returns the display
line to the start line, and synchronizes
common signals with frame timing.

TEST (Input): An LSI test pin. Use GND
level for normal operations.

HITACHI

999

HD66520
• Bus Interface

OE (Input): OE, an active low signal, is

CS (InRut): A basic signal of the RAM area.
When CS is low (active), the system can
access the on-chip RAM of the LSI whose
address space, set by LSO, LSi, and SHL
pins, contains the input address. When CS
is high, RAM is in standby.
AO to A15 (Input): A bus to transfer

addresses during RAM access. Upper nine
bits (A15 to A7) are duty-direction
addresses, and lower seven bits (A6 to AO)
are output pin direction addresses.

used to read display data from the RAM.
Only the LSI whose address space, set by
pins LSO, LSi, and SHL, containlLthe input
address can be read from when CS is low.
DBO to DB7 (Input/Output): The pins
function as data input/output pins. They
can accommodate to a data format with 2
bits/pixel, which implement packed-pixel
four-level grayscale display.

WE (Input): WE, an active low signal, is

used to write display data to the RAM. Only
the LSI whose address spaoe, set by pins
LSO, LSi, and SHL, contains the input
address can be written to when CS is low.

1000

HITACHI

HD66520
Block Dlagl'am

SHl
lSI, lSO
AI5-AO

'1

Address I
management
circuit

A

I

DB7-OBO

j

•

,

OE

CL1

r:-\ :r

~-,

r

7

I

.g

!J

~ -d

CS
WE

I ! a selector

Bidirectional
buffer

~~
7r'X....\

FLM

Data line decoder

)

I

RAM
160.240 .2b~s

'-

Timing
control
circuit

J

FRC control circuit

..J

Data latch circuit (1)

'-

Data latch circuit (2)

I

~

-L.

M

J

V4l, V3l
V2l, Vll

i J ~ -------------VI V2 V3

Figul'e 2

1=

LCD drive circuit

I - - OISPOFF

f-- V4R,V3fI
V2R,V1R

~

Vl60

Block Diagl'am

Address management circuit: Converts
the addresses input via A15-AO from the
system to .the addresses for a memory map
of the on-chip RAM. When several LSIs
(HD66520s) are used, only the LSI whose
address space, set by pins LSO, LS1, and
SHL, contains the input address accepts
the access from the system and enables
the inside. The address management
circuit enables configuration of the LCD
display system with memory addresses not
affected by the connection direction, and
reduces burdens of software and hardware
in the system.

Timing control c:lrcuit: Inputs signals FLM
and CLl for refresh operation to transfer the
line data to the LCD drive circuit and signals
CS, WE, and OE for display data access
(draw operation) of the on-chip RAM by the
system, while arbitrating refresh and draw
operations. This circuit enables the system
to access the display data of the on-chip
RAM independent of refresh operation.
Moveover, this circuit generates a timing
signal for the FRC control circuit to
implement four-level grayscale display.

HITACHI

1001

HD66520
Scan counter: Operates refresh functions.
When FLM is high, the counter clears the
count value and generates an address to
select the first line in the RAM section. The
counter increments its value whenever CL 1
is valid and generates an address to select
subsequent lines in the RAM section.
Bidlrec:tional buHer: Controls the transfer
direction of the display data according to
signals WE and OE in draw operation from
the system

Word line decoder: Decodes input
addresses and selects a one of 240 lines in
the RAM section, and activates one-line
memory cells in the RAM section.
Data line decoder: Decodes input
addresses and selects data line in the RAM
section for the 8-bit memory cells in oneline memory cells activated by the word
line decoder.
1/0 selector: Reads and writes 8-bit

display data for the memory cells in the
RAM section.

1002

RAM: 160 X 240 X 2-bit memory cell array.
Since the memory is static, display data
can be held without refresh operation
during power supply.

FRC c:irc:uit: Implements FRC (frame rate
control) function for four-level grayscale
display. For details, refer to Half Tone
Display.

Data latch circuit (1): Latches 160-pixel
grayscale display data processed by the
FRC control circuit after being read from
the RAM section by refresh operation.
Data latch circuit (2): Latches 160-pixel
grayscale display data synchronously with
CLl.
LCD drive circuit: Selects one of LCD
select/deselect power levels V4R to V1R
and V4L to V1L according to the grayscale
display data, AC signal M, and display-off
signal DISPOFF. The circuit is configured
with 160 circuits each generating LCD
voltage to turn on/off the display.

HITACHI

HD66520
Driver Layout and Address
Management
The Y lines on a liquid crystal panel and
memory data in a driver are inverted
horizontally depending on the connection
direction of the liquid crystal panel and the
driver. When several drivers are connected,
address management is needed for each
driver. Although reinverted bit-m~
plotting or address management by the CS
pin in each driver are possible by using
special write addressing, the load on the

software is significantly increased. To
avoid this, the HD66520 provides memory
addresses independent of connection
direction, but responds to the setting of
pins LSO, LS1, and SHL.
How to Use the SIB. Pin: It is possible to
invert the relationship between the
addresses and output pins Yl to Y160 by
setting the SHL pin. If the HD66520 is
placed on any side of the LCD panel, the
upper left section on the screen can be
assigned to address HOOOO.

HITACHI

1003

HD66520
Yl

Y1

~

Y160

~n direction

Y5
Y4
Y8
11 i 0000 I 00011
l2 loOiio 001111
01001 01011
L3

r

l238
l239
l240

~

- --

- --

Y153 Y157
Yl56 Y160
0026 nQ?7
00A6 nnA
0126 0127

===I===~=== - -- ~==:
===,===1====
368013681 I
36A6 36A7
370013701 I === 13726 -m7
378013781 I
137A6 37A7
SHL= low

Y157 Y153
Y160 Y156
00001 00011
11
00801 00811 l2
0100 0101
L3

~

~n direction

Y160/E1Y1

l238
l239
l240

l>o

Y5
Yl
Y8
Y4
0026 0027
00A6 00A7

- --- -~~~~~~~~~~ === F==
- -- 36A6 36A7
3680 3681
3700137011 === 3726 3727
3780 3781
37A6 37A7
n.')1\

"'"

SHL= high

Y1

Y160

=>

=;

m

Scan direction

Scan direction

~

~

Y1

SHL = high

Figure 3

Address Assignment and SHL Pin Setting

How to Use the LSi and LSO pins
The memory map of the HD66520 can be
most efficiently used in three display sizes:
a 240-dot-wide by l60-dot-Iong display; a
320-dot-wide by 240-dot-Iong display; and

1004

m

Y160
SHL = low

a 480-dot-wide by 320-dot-Iong display, all
of them are standard sizes for portable
information devices.
Therefore, up to four HD66520s can be
connected to the same bus or with the CS pin.

HITACHI

HD66520
LSIs can be mapped as shown in figure 4
by assigning ID numbers D to 3 to· each
HD6652D by using pins LSD and LS1.

Y1

UI

Q>

.§

..

c:

Y5
Y4
Y8
0000
0001
L1
L2
0080 I 00811
L::< t.0 1001 01011

~

~
0-

::l

3680 3681
370013701
378013781

- -- -- -I

-- §~g~

36A6 36A7
3726 3727
37A6 37A7

JJ
II

S
.
.
IDNa.1
can directIOn LSD. high

Y160

::l

~
-

Figure 4

Y157 Y153
Y160 Y156
3800 3801
L1
L2
3880 3881
3900 3901
L3

LS1.low
SHL.low

Y1

Y5
Y1
Y8
Y4
3826 3827
38A6 38A7
3926 3927

- --- ---- - -- - - -- -- - -- -- -- - -- -- -- - -- - - --

L238
L239
L240

EE80 EE81
EFOO EF 1
EF80 EF81

L238
L239
L240

Y5
Y4
Y8
0026L 002a/.
00A81 oOA9I _
012Sl 012a/.

EEA6 EEA7
EF26 IEF27
EFA6 EFA7

372813729 I
37A8137A91

- --

- --

374E 374F
37CE 37CF

Y160

10 No. 2
LSO_low
LS1 = high
SHL= low
IDNo.3
LSO = high
LS1 = high
SHL.1ow

~-

Y160

Y1

Y157 Y153
Y160 Y156
3828 3828 L1
38A8 3828
L2
39?B 3B28_
L3

L238
L239
L240

==.

Y153 Y157
Y156 Y160
' 004E 004F
OOCE OOCF
014E 014F

§~~~~~~n~~ - -- ~~~~
- - 36CE 36CF
36AS136A91

Y160 Y1

Y1

Scan direction 10 No. 0
LSD. low
LS, = low
SHL.1ow

,§
;
I!!
~

L1
L2
L3

===

t===I===~===
.- == =,= = =;: === L238
L239
L240

Y1

Y153 Y157
Y156 Y160
0026 0027
00A6 OOA7
0126 0127
--

--

Y5
Y1
Y8
Y4
384E 384F
38CE 38CF
394E 394F

- -- ~~~~

- ---- - -- - - -- -- - - --

EEA8 EEA9
EF28 EF29
EFA8 EFA9

EECE EECF
EF4E EF4F
EFCE EFCF

LSO and LS1 Pin Setting and Intemal Memory Map (SHL

HITACHI

=Low)

1005

HD66520

§!i! ~

11111
11111

orB 8

11111
11111

",,,,

~

0

....

CO

>

10 No. 0
LSO • low
LS1.1ow
SHL.high

....

>
0

=l =I

....

CO

> 10 No.2

LSO. high
LS1.low
SHL. high

....

>

11111

~~~

,111111
1111111

1111111

:::-1:::' ,.. ,..

,, ,,
,,

u;

CD!!(l 1111' ~!(l ~
~ '" 11111
'"''
u; u;
C")(")C')
ww

.... '!S'i;:::' 'ii,r~~~

iI! i

....

CO

Sl
"'"
C') 11111

ffi

u.
W

>
....
>

....

>

0(

480 lines

Table 1

, ,
,, ,,

~~ W
~

W

10 No. 3
LSO. high
LSl • high
SHL. high O
CO

>

Figure 5

~(')('I)

....

10 No. 1
LSO • low
LSl • high
SHL.highO

Scan direction

'"

>

LSO and LS1 Pin Setting and Intemal Memory Map (SHL

=High)

Pin Setting and Memory Map

SHL

LS1

LSO

10 No.

Memory Map

Low

Low

Low

0

LSls placed on the top of the LCD panel

Low

Low

High

Low

High

Low

2

LSls placed on the top of the LCD panel

Low

High

High

3

LSls placed on the bottom of the LCD panel

High

Low

Low

0

LSls placed on the left of the LCD panel

High

Low

High

High

High

Low

2

LSls placed on the left of the LCD panel

High

High

High

3

LSls placed on the right of the LCD panel

1006

LSls placed on the bottom of the LCD panel

LSls placed on the right of the LCD panel

HITACHI

HD66520
Application Example for System-Driver Arrangement

240

480

240

Some means is needed to
manage memory
addresses in the horizontal
direction

10 No. 0

o

~ Extended

~~ ~

horizontally

IONo.2

~-{~
==:i
r=:
H066SXY
I

1/240 duty cycle
Standard size portable information device

Wide portable information device size (latitudinal)

320

240

I ~
~~

I'l"IH""O"'6""'6S""2"'0-'1 "'"IH"'D6=6S""2""0""1

240

10 No. 0

~~

I

--,

r-

H066SXY

~

I

1/240 duty cycle
Small size portable information device

.....LJ-~

: ~ c:z
1~O·

~
~i ~~n- I;
e
:s

C.Q
:J:
"&l

~

I

c

!

~0!i
eZ ..

480

c

1;;

160

-rr- -rr-

1/240 Duty
cycle
I HD66520 I I HD66520 I
With portable information device size (longitudinal)

HITACHI

1007

HD66520
Display-Data Transfer
RAM data is transferred to a 160-bit liquid
crystal data register at each rising edge of
the CLl clock pulse. Since display data
transfer and RAM access to draw data is
completely synchronous-separated in the
LSI, there is no draw data loss or display
flickering from display data transfer timing.
The first line data transfer involves the first
line marker (FLM), which initializes a line
counter, and transfers the first line to a data
register in the LCD driver. Subsequent line

X+1

Latch1 Data Xth + 1 line

•
~

1st line

Xth line

Figure 6

1008

The line counter is initialized synchronously
with an FLM signal in the first line data
transfer by the FLM signal and the CL 1
signal. The first line is transferred to the
data register in the LCD driver at the rising
edge of the CLl (figure 6).

),

FLM

Y1-Y160

First LIne Data Transfer

,

CL1

Line Counter

data transfer involves transferring the second
and the subsequent line data to a data
register in the LCD driver while incrementing
the line counter value.

~
X

~
2
2nd line
1st line

First Line Data Transfer

HITACHI

HD66520
Subsequent Line Data Transfer
In display access 2, the second and the
subsequent line data are transferred to the
data register in the LCD driver at the rising
edge of the CL 1 to update the line counter
value (figure 7).

':

CL1
Line Counter

n

Latch1 Data

nth line

Y1-Y160

nth - 1 line

Figure 7

,

"•
X

n+1
nth + 1 line
nth line

Subsequent Line Data Transfer

HITACHI

1009

HD66520
Display-Data Transfer Method
The liquid crystal panel display needs to
repeatedly execute first line data transfers
and successive line data transfers based on a
regular cycle to achieve continuous operation.
The FLM signal cycle is determined by a
frame frequency value which is required by
a liquid crystal panel. Generally, the value
is 70 to 90 Hz.
Data-transfer clock CL 1 frequency is
determined by the number of lines that
must be transferred during one frame
period, in other words, a frequency should
be the product of the FLM signal frequency
multiplied by the number of lines. For
example, to transfer 240 lines during one
frame period (11240 duty cycle) at a frame
frequency of aO-Hz, an approximate 19.2kHz data transfer clock is needed.
The M signal, which converts a liquid
crystal drive waveform to an AC signal,

1010

should be either a frame-reverse waveform
synchronized with the FLM signal or an nline reverse waveform synchronized with
the n count of CL 1. The latter should be
initialized by FLM. Since the M cycle is
closely related to optical characteristics
and the display quality of the liquid crystal
panel, it should be determined through
actually verifying the display.
Although the above control signals should
be repeatedly input to display the contents
of the internal memory on the liquid crystal
display panel, power consumption in the
display control part can be reduced to 1150
to 1/100 of that of the currently-used CRTbased control system mainly displaying
still pictures with a long MPU idling state.
This is because a considerably low-speed
operating clock (about 20 kHz to 30 kHz) is
used while in the range from 10 MHz to
about 50 MHz are used for a liquid crystal
controller based on existing CRT display
control techniques.

HITACHI

HD66520
80 Hz (12.5 ms)

FLM
CL1

$J

1$

~

~~~~~~~~~~I~I~I~~~ I I I 1

V1-Y160

M
(Frame
reverse)
M
(n-line

reverse)

Figure 8

LCD Display Data Timing

HITACHI

1011

HD66520
Draw Access
Draw data access sequence is the same as
for a general-purpose SRAM interface. It
can easily be connected to a CPU address
bus and data bus.

A15-AO

CS
OE

I

\

WE
1107-1/00 out

Valid

Dout

1107-1/00 In

Figure 9

Read Cycle

A15-AO

CS
OE
WE

\~

____________-JI
(

1107-1/00 In

Figure 10

1012

Valid pip

Write Cycle

HITACHI

HD66520
Configuration of Display Data Bit
Packed Plxe. Method
For grayscale display, multiple bits are
needed for one pixel. In the HD66520, two
bits are assigned to one pixel, enabling a
four-level grayscale display.

One address (eight bits) specifies four
pixels, and pixel bits 0 and 1 are managed
as consecutive bits. When grayscale
display data is manipulated in bit units,
one memory access is sufficient, which
enables smooth high-speed data rewriting.

LCD display state
Grayscale level

FRC control circuit

Physical memory

Figure 11

Packed Pixel System

HITACHI

1013

HD66520
Half Tone Display (FRC: Frame Rate
Control Function)

each frame and half brightness is
expressed in addition to display onloff.

The HD66520 incorporates an FRC function
to display four-level grayscale half tone.

Since the HD66520 has two-bit gray-scale
data per one pixel, it can display four-level
grayscale and improve user interface
(figure 12). Figure 13 shows the
relationships between voltage patterns
applied to each frame, the effective voltage
value, and brightness obtained.

The FRC function utilizes liquid crystal
characteristics whose brightness is
changed by an effective value of applied
voltage. Different voltages are applied to

a) Display with !Wo values

Figure 12

1014

b) Display with four values

Example of User Interface Improvement

HITACHI

HD66520
Applied voltage pattern
1st trame

2nd frame

3rd frame

Effective voltage

e;
DO.
DO.
e;
•••
e; •••
•••
••••
••
•••
••• •••
e;
•••
•••
•••
••• ••• ••• •••

Display on
(wMe) (1, 1)

ODD
ODD
ODD

DOD
DOD
DOD

.00

.00
D.D

E]E]E]
E]E]E]
lliUlTI!lill

.0.
•• 0

• •0

DOD
DOD
DOD

DOD
DOD
DOD

.00
0.0
DO.
D••

0.0

(VrmO)

Halftone 1
(1,0)

.0.
• •0

Han tone 2
(0,1)

Display off
(black) (0, 0)

D••
D•• .0•

(Vrm1)

(Vrm2)

(Vrm3)

Brightness

,

-~

,

-. -_..,, ----- ---- -.--,,

------j----------j----+----------VrmO

Vrml Vrm2

Vrm3

Effective vollage

Figure 13

Effective Voltage Values vs. Brightness

HITACHI

1015

HD66520
Example of System Configuration

liquid crystal display timing control
circuits. All required functions can be
prepared for liquid crystal display with just
three chips except for liquid crystal display
power supply circuit functions.

Figure 14 shows a system configuration for
a 240 X 320-dot LCD panel using HD66520s
and common driver HD66503 with internal

Vex;

CS";WE; OE

240

3

-~8--1rt-------1

DB()-()B7 -+':,6:-11"+r----1
AI5-AO

---- --- --- --------- --_.- ----.-- --- --- ---

= --

Line scan direction

3 FLM. CLl. M

LCD driver

HD66503
Powersupply
circuit

I-........_ _ _ _ _ _ _~

Figure 14

1016

LCD display timing control circuit

System Configuration

HITACHI

'"

()
C')

HD66520
Absolute IVIaximum Ratings
Item

Symbol

Ratings

Unit

Notes

logic circuit

Vee

-0.3 to +7.0

V

1

leo drive circuit

VEE

Vee-30.0to
Vee +0.3

V

Input voltage (1)

VTl

-0.3 to Vee +0.3

V

1.2

Input voltage (2)

VT2

VEE -0.3 to
Vee +0.3

V

1.3

Allowable output
current

liol



mA

Allowable total
output current

IIlol



mA

Operating
temperature

Topr

-20 to +75

°e

Storage
temperature

T stg

-40 to +125

°e

Power voltage

Notes:

1.

The reference point is GND (0 V).

2.

Applies to pins lSO' lSl. SHl. FlM. ell' M. AO to A15. DBO to DB7' DISP. es. WE. and OE.

3.

Applies to pins V 1• V2. V3' and V4'

4.

If the lSI is used beyond its absolute maximum rating. it may be permanently damaged. It should
always be used within the limits of its electrical characteristics in order to prevent malfunction or
unreliability.

HITACHI

1017

HD66520
Recommended Operating Conditions 1
Item
Power voltage

Symbol

Min

Typ

Max

Unit

Logic circuit

Vee

2.7

3.3

3.6

V

Leo drive circuit

VEE

Vee -10

Vee -28

V

Input high voltage
for logic circuit

VIH

0.7 x Vee

Vee

V

Input low voltage
for logic circuit

VIL

0

0.3 x Vee

V

Operating
temperature

Topr

-20

75

°e

Notes:

25

1.

Max value is Vee + 1 V when the pulse width is 10 ns or less.

2.

Min value is - 1 V when the pulse width is 10 ns or less.

Notes

2

Recommended Operating Conditions2
Item
Power voltage

Symbol

Min

Typ

Max

Unit

Logic circuit

Vee

4.5

5.0

5.5

V

Leo drive circuit

VEE

Vee -10

Vee - 28

V

Input high voltage
for logic circuit

VIH

0.7 x Vee

Vee

V

Input low voltage
for logic circuit

VIL

0

0.3 x Vee

V

Operating
temperature

Topr

-20

75

°e

Notes:

1018

25

1.

Max value is Vee + 1 V when the pulse width is 10 ns or less.

2.

Min value is - 1 V when the pulse width is 10 ns or less.

HITACHI

Notes

2

HD66520
Capacitance
Unit

ein



pF

Vin = 0 V

CliO



pF

Ta = 25°C
f = 1 MHz

Symbol

Input capacitance
I/O capacitance

Measuring
Condition

Max

Item

Typ

Min

All these parameters are not measured but are sample values.

Electrical Characteristics
DC Characteristics 1 (VCC
28 V, Ta = -zooC to +75°C)
Symbol

Item

Applicable
Pins

=2.7 V to 5.5 V, GND =0 V, VCC Min

Typ

Max

Unit

Input high
level voltage

0.7 x Vee

Vee

V

Input low
level voltage

o

0.3 x Vee

V

Output high
level voltage

Vee- 0.4

Output low
level voltage
Vi-Vj on
resistance

Notes:

1.

RON

V1 to V160
V1L/V1R,
V2L/V2R,
V3L/V3R,
and V4L/V4R

1.0

VEE

=8 V to

Measurement
Condition

V

10H =-0.4mA

0.4

V

10L =-0.4mA

2.0

kll

ION = 100 !LA

Notes

Indicates the resistance between one pin from V1 to V160 and another pin from V2L/V2R, V3L/V3R,
V4L/V4R, and VEE, when load current is applied to the V pin; defined under the following conditions:
Vee - VLeD = 28 V
V1L/V1R, V3L/V3R = Vee - 2/10 (Vee - VEE)
V4L/V4R, V2L/V2R = VEE + 2/10 (Vee - VEE)
V1L/V1R and V3L/V3R should be near the Vee level, and V2L/V2R and V4L/V4R should be near the VEE
level. All voltage must be within AV. AV is the range within which RON, the LCD drive circuits' output
impedance, is stable. Note that AV depends on power supply voltages Vee - VEE. See figure 15.

HITACHI

1019

HD66520

--r-------

vee

n·········- V1LN1R
I

L ..... V3LN3R

1u__""_--"_.._"._."_"_."_"'_"'_.Ve~2R
1

r·········,""

5.6 ••••.•••.•..•..••••.

~
~ 2.0 ••••••••

V4LN4R

tN_L-_

Figure 15 Relationship between Driver Output Wavefonn and Level Voltages
DC Characteristics2 (Vec = 2.7 V to 3.6 V, GND = 0 V, VCC - VEE = 10 V to
28 V, Ta = -20°C to +75°C)
Applicable
Pins

Max

Unit

Measurement
Condition

1.0

Jl.A

VIN

=Vee to GND

25

Jl.A

VIN

=Vee to VEE

TBD

TBD

mA

tcyc = 150 ns
Vee -VEE
= 28V

lEE

TBD

TBD

Jl.A

lOIS

TBD

TBD

IloA

Item

Symbol

Input leakage
current (1)

IILl

-1.0

Input leakage
current (2)

IIL2

V1LJV1R,
-25
V2LJV2R,
V3LJV3R,
and V4LJV4R

Power
consumption
during RAM
access

loe

Power
consumption
in LCD drive
part
Power
consumption
during display
operation
Notes:

1020

Min

Typ

Tcyc

=500 ms

Notes

1,2

1.

Input and output currents are excluded. When a eMOS input is floating, excess current flows from
the power supply through to the input circuit. To avoid this, VIH and VIL must be held to Vee and
GND levels, respectively.

2.

Indicates the current when the display'operation memory access is idling.

HITACHI

HD66520
DC Cbaracterlstics3 (VCC = 4.5 V to 5.5 V, GND = 0 V, V CC - VEE = 8 V to
28 V, Ta -2C)°C to +75°C)

=

Applicable
Pins

Measurement

hem

Symbol

Input leakage
current (1)

1111

-1.0

Input leakage
current (2)

IIL2

V1LJV1R,
-25
V2LJV2R,
V3LJV3R,
and V4LJV4R

Power
consumption
during RAM
access

IOC

Power
consumption
in LCD drive
part
Power
consumption
during display
operation
Notes:

Typ

Max

Unit

1.0

I1A

VIN = VCC to GNO

25

I1A

VIN=VCCtoVEE

TBO

TBO

mA

tcyc = 150 ns
VCC -VEE
=28V

ILCO

TBO

TBO

IJ.A

lOIS

TBO

TBO

I1A

Min

Notes

Tcyc = 500 ms

1,2

1.

Input and output currents are excluded. When a CMOS input is floating, excess current flows from
thl1 power supply through to the input circuit. To avoid this, VIH' and VIL must be held to VCC and
GNO levels, respectively.

2.

Indicates the current when the display-operation memory access is idling.

HITACHI

1021

HD66520
AC Characteristics 1 (VCC = 2.7 V to 5.5 V, GND = 0 V, VCC - VEE = 8 V to
28 V. T a = -20°C to +75°C)
DisplaY"Data Transfer TIming
No.

Item

Symbol

Applicable
- Pins

Min

Max

Unit

tCYC

CL1

10

tCWH

CL1



I1s
ns

CL 1 low-level
width

tCWL

CL1

1.0

I1s

Clock cycle time

2

CL 1 high-level
width

3
4

CL 1 rise time

tr

CL1

50

5

CL 1 fall time

tf

CL1

50

6

FLM setup time

tFS

FLM. CL1



7

FLM hold time

rFH

FLM. CL1



,

ns
ns
ns
ns

fCYC=1ItCYC
Max:100kHz

Q) tCYC

CL1

@1FS

OJ 1FH

O.7Voo
FLM

O.3Voo

Figure 16

Display Data Transfer Timing

Notes

HD66520
AC Characteristics 1 (VCC
28 V, Ta -20°C to +75°C)

=

=4.5 V to 5.5 V, GND =0 V, VCC -

VEE

=8 V to

Draw Access Timing 1

Common Items
No.

Item

Symbol

Min

Address setup time

tAS

20

Max

Unit

Notes

ns

2

Address hold time

tAH

0

3

Chip select time

tcw

40

tCYC-50

ns

Item

Symbol

Min

Max

Unit

Read cycle time

tRC

60

ns

ReadCycle
No.
2

Address access time

tAA

20

ns

3

Chip select access time

tACS

20

ns

4

CS output set time

tCLl

0

ns

5

CS setup time

tcss

0

ns

6

CS hold time

tCSH

0

ns

7

OE low level width

tOLW

40

8

Delay time from outputenable to output

tOE

0

9

Delay time from outputenable to output (low
impedance)

tOLZ

0

ns
20

ns
ns

10

CS and output floating

tCHZ

0

10

ns

11

Delay time from outputdisable to output

to HZ

0

10

ns

12

Output hold time

tOH

5

13

Output voltage riselfall
time

tT

ns
50

HITACHI

Notes

ns

ns

1023

HD66520
WriteCycle
No.

Item

Symbol

Min

1
2

Write cycle time

twc

Address valid time

tAW

3

Write pulse width

twp

60
60
40

4

Oelay time from outputdisable to output

tOHZ

0

5

Input data set time

tow

.30

ns

6

Input data hold time

tOH

5

ns

1024

HITACHI

Max

Unit
ns
ns

20
10

ns
ns

Notes

HD66520

Address

WE

OE

110 out

1/0 In

Figure 17

Read Cycle

HITACHI

1025

HD66520

Address

WE

UOout

1/0 In

Figure 18

1026

Write Cycle

HITACHI

HD66300T-----------(Horizontal Driver for TFT -Type LCD
Color TV)
The HD66300T is a horizontal driver used for TFTtype (Thin Film Transistor) LCD color TVs. Specifically, it drives the drain bus signals of a TFT-type LCD
panel.

Features

The HD66300T receives as input~~ video..Jiignals R,
G, B, and their inverted signals R, G and B. Internal
sample and hold circuitry then samples and holds
these signals before outputting them via voltage followers to drive a TFT-type LCD panel.

•

•
•

•

•
The HD66300T can drive LCD panels from 480 x 240
pixels middle-resolution up to 720 x 480 pixels highresolution. It has 120 LCD drive outputs and enables
design ofa compact LCD TV duetoTCP (Tape Carrier
Package) technology.

•
•

Ordering Information

•
•
•

Type No.

Package

HD66300TOO

1S6-pin Tep

Note:

LCD drive outputs: 120
Internal sample and hold circuits: 480 (4 circuits
per output)
Support of single-rate sequential drive mode and
double-rate sequential drive mode
Support of various types of color filter arrangements through an internal color sequence controller
Vertical pixels: 240 (middle-resolution) or 480
(high-resolution)
Horizontal pixels: 480 to 720
Support of monodirectional connection mode and
interleaved connection mode through a bidirectional shift register
Dynamic range: 15 Vpp
Power supply: +5 V and -15 V
CMOS process

The details of Tep pattern are shown in
"The Information of Tep."

Pin Arrangement
omOO ...... CDl.Oor:tMN..-

~::::::::::::::::::::::::

occcccocoo

•••••••••••••••••••••••••••••••••••••••••••

~mcor-CDl.l'IqMN ...
0000000000

_..... ..-- .............. •••.••.....••...••......•..•••...•••.....•. ~moor-CDLnor:rMN 1

~~~~~~:!~~::

...-

.........

(Top View)

Note: This does not apply to Tep dimensions.

HITACHI

1027

HD66300T
Pin Description
Pin List
Pin Name

Number of Pins

Input/Output

Connected to

Functions (Refer to)

01 - 0120

120

0

LCD panel

1.

HCK1, HCK2,

3

Controller

2.

Controller or

3.

HCK3
DL, DR

2

1/0

next HD66300T
FD

Controller

4.

RS

GND

5.

OE

Controller

6.

SHL

Vcc orGND

7.

DIS

Vcc orGND

8.

LIF

Vccor GND

9.

MSF1, MSF2

2

VeeorGND

10.

TEST1, TEST2

2

GND

11.

Vxl, Vx2, Vx3,

6

Inverter

12.

Power source

13.

Vyl, Vy2, Vy3
Vbo
Vbse' VbsH

2

Power source

14.

VLc l, VLc 2,
VLc3, VLc 4

4

Power source

15.

Vcc l, Vcc2,
Vee3

3

Power source

16.

Power source

17.

Power source

18.

GND
Vee l, Vee2,
Vee3, Vee4

1028

4

HITACHI

HD66300T
Pin Functions
1. 01 - 0120: These pins output LCD drive signals.
2. HCK1, HCK2, HCK3:Thesepins input three-phase
clock pulses, which determine the signal sampling
timing for sample and hold circuits.

6. OE: This pin inputs the signal which controls the
controller of the shift matrix circuit; it changes the
selection of a sample and hold circuit and the shift
matrix (combination of color data), at its rising edge.
It also switches the bias current of the output buffer, as
shown in the following table.

3. DL, DR: These pins input or output data into or
from the internal bidirectional shift register. The state
of pin SHL determines whether these pins input or
output data.

OE

Bias Current of OUtput Buffer

High

Large current (determined by VbsB)

Low

Small current (determined by VbsH)

SHL

DL

7. SHL: This pin selects the shift direction of the shift
register.

Vee

Output

Input

GND

Input

Output

DR

4. FD: This pin inputs the fJ.eld determination Signal,
which allows the sample and hold circuitry and the
shift matrix circuit to operate synchronously with TV
signals, at its rising and falling edge.

SHL

Shift Direction

High

DL+- DR

Low

DL -+ DR

8. DIS: This pin selects the LCD drive mode.

FD =high: First field
DIS

Mode

High

Double-rate sequential drive mode

When a non-interlace signal is applied, it must be
inverted every field.

Low

Single-rate sequential drive mode

When an interlace signal is applied in double-rate
sequential drive mode with per-line inversion (mode
1, 2, 3), the signal must be set high in both fields. The
signal must be set low, however, in each field's horizontal retrace period.

9. UP: This pin selects the inversion mode of LCD
drive signals.

FD =low: Second field

S. RS: This pin inputs a test signal and should be
connected to pin GND.

UF

Mode

High

Per-line inversion mode

Low

Per-field inversion mode

HITACHI

1029

HD66300T
10. MSFl, MSF2: These pins select the function of the shift matrix circuit; they should be set according to both the
type of color filter arrangement on a TFT-type LCD panel and the drive mode.
Filter Arrangement

Drive Mode

MSF1

MSF2

Diagonal mosaic

Single-rate

GND

Vee/GND*

pattern

Double-rate

GND

VedGND *

Vertical stripe

Single-rate

Vee

Vee

pattern

Double-rate

Vee

Vee

Unicolor triangular

Single-rate

Vee

Vee

pattern

Double-rate

Vee

GND

Sicolor triangular

Single-rate

Vee

GND

pattern

Double-rate

Vee

GND

Single-rate: Single-rate sequential drive mode
Double-rate: Double-rate sequential drive mode
Note'" Refer to table2 and timing charts of each mode
11. TESTl, TEST2: These pins input test signals and
should be connected to pin GND.
12. VX1, Vx2, Vx3, Vyl, Vy2, Vy3: Video signals are
applied to these pins; in general, positive video signals are connected to pins Vxi and negative video
signals to pins Vyi.

15. V LeI, VL~' V L~' V Le4: +5 V LCD drive voltage
is applied to these pins.
16. V ee1, V e~' V e~' Vee4: +5 V is applied to these
pins for the logic and the analog units.
17. GND: 0 V is applied to this pin for the logic unit.

13. Vbo: Bias voltage is applied to this pin for the
differential amplifier in the sample and hold circuitry.

18. VBB1, VBB2: -15 V is applied to these pins for the

14. VbsB' VbsH: Bias voltage is applied to this pin for
the two power sources of the output buffer.
VbsB: The voltage for driving a capacitive load
VbsH: The voltage for holding the output voltage

19. VBB3, VBB4: -15 V is applied to these pins for the
LCD drive unit.

1030

LCD drive unit.

HITACHI

1-4

='

til

-S

III

QI:j

~:~II:l

0

n

~

Bidirectional shift register

RSD-------I>O

d

ro

Vxl

Q2

Q3

Q118

Q119

d

d

d

d

~

r--t;1

~

V

V

J..-,r-+---,...

Y

OOR

Q120

Y

~

--aGNO

J-oV

~

I~

~ Sam~e and hold circuit

Y

Y selection gate

1

--a v••

Internal signal bus

V,ID--++--I

io

I ~.

cc

Vx3

J:

0

V,2

.

~

O/S
L/F
MSFI
MSF2
FO

Sample and hold
circuitry

OEU--Cif:Iil::

VflSB

TEsn-

~

TEST2~
IS : level shifter

01

J

02

J

03

'"

'"

0118

0119

[

~

Output buffer (amp.)

~

0120

::r:
t1

m
m
c..>

8

o
o

t-3

HD66300T
Block Functions
Shift Register: The shift register generates the sampling timing for video signals. It is driven by threephase clocks HCK1, HCK2, and HCK3, whose phases
are different from each other by 120"j each clock
determines the sampling timing for one color signal so
that three clocks support the three color signals R, G,
and B. The shift direction of this registercanbe changed.
Level Shifter: The level shifter changes 5-V signals
into 20,V signals.
Sample and Hold Circuitry: In double-rate sequential drive mode, two sample and hold circuits are
selected to sample video signals during one horizontal scanning period out of the four circuits attached to
one LCD drive signal. One of the two selected circuits
is read out in the first half of the following horizontal

1032

scanning period, and the other selected circuit is read
out in the second half. While the two circuits are being
read out, the other two circuits sample signals and are
alternately read out in the same procedure mentioned
above.
In single-rate sequential drive mode, one sample and
hold circuit samples a signal during one horizontal
scanning period, and is read out in the following
horizontal scanning period. While it is being read out,
one circuit out of the other three samples a signal.
Shift Matrix Circuit: The shift matrix circuit, a color
sequence controller, changes over the sampled video
signal every horizontal scanning period.
Output Buffer: The output buffer consists of a source
follower circuit and can change the through-rate of an
output signal by changing the external bias voltage.

HITACHI

HD66300T
System Block Configuration Example

Antenna

Video
input 0---0-0

R,G, B

if,G, B

TFT-type color LCD panel
720 x 480 pixels

HITACHI

1033

HD66300T
Example of HD66300T Connection to LCD Panel
>

~i
!
0

>:
U

CD :I:

uU

0'"

.Q

.Q

III
.CI

m

~-::

»>

>

"'"

-

FO
r - - - DE
HCK3
, - HCK2
ro-- HCKl
Vy3
Vy2
Vyl
Vx3
Vx2
Vxl

r-

0120
0119 r -

-

t--

g~

M'"

~~

I-

'"

"'~
M<"l

~:l!

o~

:J:

o~

:J:

"'"

02f-01f--

-

0120- '"
0119-

HCK3
HCK2
t-- HCKl
*-HfH-I++H--l Vy3

0119
0120

'"

"'"

N

'"Z

1.1.1"'1.1.1
Z
Z

:J

:J

"

0

~

~

FO
DE

~

'"z

I-

:J

:J

'"M.-,
"'~
~~

o~

Vyl
Vy2
Vx3

:J:

II"n:tf:m~ Vx2
Vxl
0119
0120

~ .. ·······~I
x·········~
HD6ll05
(Nol)
is

);il

1Sound
1 IF
1 Tuner

x .. ·······~
HD6ll05
(No.2)

g~ 0

~

!

Video
input

(\J

iPUlxl>
Synchronizing
isolator

HCK3
HCK2
HCKl
Vy3
Vy2
Vyl
Vx3
Vx2
Vxl

"'"

~

~I""""'~

w

"13 233"2
M:I:
~ ~ ~ ti
.-

0;1

t ......... ~

w

HCK31HCK2
HCKl
Vy3
Vy2
Vyl
Vx3
Vx2
Vxl

..J

-01
-02

i5

~

f--

Ifm1:ttm~

"
FOr-DEI--

t:~~~
I- Co <_____

X'-__A_ _....X'-___D _ _><==

D
_ _.....

Figure 9 Sampling Timing charts of Single-Rate Sequential Drive Mode

/.

lH

·1

OE
SAMPLING

A

Sample
and
hold
circuits

B

c

°

~

~~iff~

~ff~

SAMPLING

SAMPLING

~~~

SAMPLING

SAMPLING

SAMPLING

OUTPUT

Figure 10 Sampling Timing charts of Double-Rate Sequential Drive Mode
1048

HITACHI

HD66300T
Sampling Operation

register activates in tum the sample and hold circuits
corresponding to each LCD drive signal output pin.

The HD66300T has a bidirectional shift register composed of 120 bits and each bit of the shift register
generates the sampling pulses to control the sampling
operation of the four sample and hold circuits connected to each LCD drive signal output pin. When a
bit of the shift register is 1, the corresponding sample
and hold circuits are in the sampling state; when it is
0, the corresponding sample and hold circuits are in
the hold state. Consequently, shifting a 1 into the shift

01

02

03

04

Figure 11 is a shift register sketch illustrating the
relationship between the shift register and the shift
clocks HCK1, HCK2, and HCI<3. Note that the order
of sampling pulse generation depends on the state of
pin SHL. D1 corresponds to DL and D120 to DR.
Figure 12 is a timing chart of sampling pulses generated by the shift register.

0117 0118 0119 0120

Output pins

Sample and hold circuitry

OL

DR shift register

SHL

HCK1

0--.....-+-+-+--'

HCK2

0----11--'

HCK3

0----_--'

Figure 11 Shift Register Sketch

HITACHI

1049

HD66300T

::::~\~

JlJUL ULJL

HCK3

(oBipUT)----))~
SRI

--))~

SR2

--)~~

SR3

--))~

SR118

~~)I---­

SR119

~))----

SR120

--'L-)) ____

(IN~~T) n

)),---(a)

HCKI

SHL=High

Jl..JLr~JLJL.J'
.-n..ru

HCK2

~

HCK3

JlJUL ULJL

OL
(INPUT)

n ' - - - _ ( , _ __

SRI
SR2
SR3
SR118
SR119
SR120

DR
(OUTPUT)

"))

~))--~S)---~)).----------'S)~
----S)~
----))~
--(~
'))

(b)

SHL=Low

Figure 12 Sampling Pulse Timing Chart
1050

HITACHI

HD66300T
Three-Phase Shift Clocks

operation starts when 1 is input from pin DL or DR at
a rising edge of the HCK1 clock pulse.

Three-Phase Shift Clocks and Sample Start Signal
Shift clocks HCK1, HCI<2,and HCI<3, which are
operation clocks for the shift register, must be threephase clocks with SO-percent duty. The HCK2 clock
must be generated 1200 after the HCK1 clock, and the
HCI<3 clock 240" after the HCK1 clock. Sampling

HCKI

In monodirectional connection mode,' all the
HD66300T chips must be supplied with the same
three-phase shift clock pulses. In interleaved connection mode, the frequency of the three-phase shift
clocks must be halfof that in monodirectional connection mode, and the phase shift between the upper
drivers clocks and the lower drivers clocks must be
one pixel.

~:
I

:

HCK2

I
I
I

HCK3

il
I
I

DL/DR

11
(8)

HCKI

-1!
:
I

HCK2

For upper
drivers

II
I

,I
I
I

__--,I

Jtl
I
I

II ~

HCKI

HCK2

~

,,

HCK3

DL/DR

For lower
drivers

In Monodirectional Connection Mode

I

pixe!
I

L

!
I

I
I

HCK3

DL/DR

i

~

The lower driver clock pulses follow the upper driver clock pulses by one pixel.
(b)

In Interleaved Connection Mode

Figure 13 Three-Phase Shift Oocks and Sample Start Signal
HITACHI

1051

HD66300T
Some position shift exists between the pixels of even
number lines and those of odd number lines for LCD
panels having triangular patterns. This requires generating a phase shift' between the three-phase clocks

1st line

2nd line

HCKI

1lE
::I

HCK2

~!!!

HCK3

I:
'tI

01:

3rd line

for even number lines and those for odd number lines.
The required phase shift is 1.5 pixels for LCD panels
having a unicolor triangular pattern, while it is 0.5
pixels for those having a bicolor triangular pattern.

u-=
OLloR

I

I
I
I

JTl
: O.5-pixel delay
-001---;.....
I

4th line
HCKI
II)

CO>

.,

I:

~

E

c::=

HCK2

~

~1l

0::1
11.1:

HCK3
OLloR

(bl

--Il

Bicolor Triangular Pattern

Figure 14
1052

HITACHI

HD66300T
How to Generate Three-Phase Shift Clocks
Three-phase shift clocks can be generated by dividing
the base clock, which is generated from a horizontal
synchronizing clock, through the use of a frequency
multiplier such as a PLL circuit.
The number of horizontal pixels of the LCD panel and
the valid display ratio determines the base clock
frequency f.
If the number of horizontal pixels is 480 and the

valid display ratio is 95% in the NTSC system, the
base clock frequency f is about 9.59 MHz according
to the following equation.
f - (1lValid display period) x (no. of horizontal
pixelslValid display ratio)
- 480/(52.7 ~sec x 0.95)
- 9.59 (MHz)

The three-phase clocks can be generated by dividing f by 3 (in the monodirectional connection mode)
or 6 (in the interleaved connection mode).

480 pixels (95%)

Video
signals

Horizontal
r:etrace peri~.

Valid display period

Figure 15 Base Dock

HITACHI

1053

HD66300T

HCK1

HCK2

HCK3
(a)

HCK1
For upper
drivers

For lower
drivers

In Mor'lodirectional Connection Mode

J
L

HCK2

HCK3

I

HCK1

~

HCK2

~~________~

HCK3
(b)

In Interleaved Connection Mode

Figure 16 Three-Phase Shift Docks

1054

HITACHI

HD66300T
Bias Voltage

The rise time (tODR) and the fall time (loOF) of the
output buffer depend on the input level of VbeB'

Voltages VbeB' VbsH' and Vbo control the drive capability of the output buffer and differential amplifier.
Here the LSI must be used in the range of

Figure 19 shows the relationship between tOOR' tOOF
and VbeB .
Vbo controls the bias current of the differential amplifier (IVbo)'
Figure 20 shows the relationship between the rise and

V beB controls the drive current capability of the output

fall times (tOOR'tooP> of the output buffer and Vbo'

buffer when OE is high (lVsB) and VbsH controls the
leakage correction current of when OE is low (IVsH),
Figure 17 and figure 18 show the relationship between
IV5B and VbeB and the relationship between IVsH and

Vbo should be adjusted to an appropriate level for the
electrical characteristics of the LCD panel used.
The increase of total current consumption is 120 times
larger than that of IVbeB' IVbsH and IVbo' because
figure 17, 18 and 21 each shows the case of one output
and HD66300T has 120 outputs.
Figure 17, 18, 19,20and21 are just for reference and do
not guarantee the characteristics.

V bsH ' respectively,
VbeB and VbsH should be to an appropriate level for
the electrical characteristics of the LCD panel used.

IVbSH
(IlA)

1.000
800

80

600

60

400

40

200

20
5

Figure 17

IVbsB

Vee -VbS8 (V)

/,

vs V CC-VbSB

HITACHI

1055

HD66300T

tDDF

(ps)
10

V.,=Va;-3V
Cl=100pF

V.. =Vcc-3V
CL =100pF

3

3 V••• (V)

V••• (V)

tDDR

(Ps)
5

/

V.sB=Va;-3V
Cl=100pF

2

3 V•• (V)

3 V•• (V)

Figure 20

1056

VbS .=Vcc -3V
CL =100pF

looK' loop VS

HITACHI

Vbo

HD66300T

IVbO
("A)

50
40

30
20
10
1

2

3

4

5 Vee-V•• (V)

OE

tOOR

90%(Vin=Vee -3.5V)
01-0120
10%(Vin=V•• +1.5V)
tOOF

Figure 22 Definition of looR and looF

HITACHI

1057

HD66300T

=

OE Signal

OE high: Drives with large current (300I1A. typ)
OE .. low: Drives with small current (20 ILA. typ)

The OE signal has the following functions:
Clock for internal circuits: Controls the sample and
hold circuitry and the controller of the shift matrix
circuit, and switches the output signal at the OE signal
rising edge.
Switching of drive capability of the output buffer:
Determines the current drive capability of the output
buffer;

This function allows the output buffer to operate with
large current during the transition of an output Signal,
thus shortening its falling time. At the same time it
allows the output buffer to operate with small current
while an output signal is stable, lowering current consumption.
The drive current is controlled by bias voltages VbsB
(large current) and VbsH (small current).

~:nal~,
,

: i
~

'/
' + - - - ;-----1'i

.__'_"__""___'_'~"V:.<.y;;/3 Vx3

Ga-l

--------------~II~---------------------s\~\-------------

Ga-Z

-----------~~~..~~-----------------~(~h-----------

G~-480

Vy2 Vx

Vy3 VII3 Vy3 Vx3 Vy3 Vx3 Vy3 Vx3

--~--------------------------~·s~

HITACHI

1063

HD66300T

MODE 5
DIS

Vee

L/F

GND

MSFI

GND

MSF2

Vee

Video

DL/DR

OE
FD

-~f

I SAMPlE

U

hold circuits C

..,
;;
'"Ii!

D

Ii:

I

I SAMPLE

10UTI

AMPlE

SAMPl

lOUT I SAMPlE

x3 Vx2

I

10UTI

V,2 V,l

D3k+3

Yx3 Vx2 V,l

Vx3 V,l

Pl
lOUT I SAMPLE I

SAMPLE I

,3

VxZ

xl V,3 V,2 V,l

Vx3

,3 Vx2 Yxl V,3

,3 V,2 V,l Yx3 Vx2

D3k+Z

au

OUT SAMPLE
SAMPLE OUT

,2 V,l

V,l V,3

I SAMPLE lourl

IOUTI

OUT SAMPLE
SAMPLE OUT

SAMPLE I

V,l

D3k+l

I SAMPLE

loutl

SAMPLE

,1

x3 VxZ

xl Vx3 Yx2 V,l Vx3 Yx2

,2 V,l

xl V,3 V,l V,l

Ga-l

________~!lL__________________________~~~------------

Gr Z

____________~!lL___~~~------------------_;~.~-------------

Ga-480

------------------------------··~··s~

Video

DL/DR

OE
FD

---,

.m"~f

I SAMPLE
SAMPLE

hold circuits

D

'"

I

OUT

I SAMPlE I

lour! SAMPLE

SAMPLE

SAMPLE OUT
lour! SAMPLE

I

if

lOUT I

UT SAMPLE

SAMPLE

I

I

SAMPLE 10UTI

SAMPlE OUT

C

~

lOUT I

lourl

I

~\

lOUT I

~ I
SAMPLE UT ~ I
SAMPLE I
I S~ I

a

T

10UTI
SAMPlE

lour!

SAMPlE

I

1
Jl D3k+l

xX

D3k+Z

Vy2 Vyl

D3k+3

Vy3 Vyl

Ga-l
Ga-Z

XX
XX

--------------~IIL---------------------~S~S-----------------------------~rJ~_.~----------------~~~~-------------

G~-480

1064

I

ss··--·····

HITACHI

11<----

HD66300T

MOOE 6

DIS

Vee

L/F

GND

MSFI

GND

MSF2

GND

Video

DL/DR

_..[:
OE

FD

~
I SAMPLE loufl
SAMPLE

hold circuits C

~

VII'

xl

D3k+Z

x2 Yd Yal

xZ

d

I

ou

AMPLE OUT
IOUTI SAMPLE I

Val VI(

Vx3 Yll

x3 Vxl VxZ Vx3 Val Yd 'lx3 Val

Va3 Yal YaZ Vxl V.,

D3k+3

Ga-l

lour! SAMPLE I

I SAMPLE IOUTI
OUT SAMPLE

PLE OUT

I SAMPLE I

D3k+l

I SAMPlE IOUTI
OUT SAMPLE

SAMPL

0
l!
~

I SAMPLE IOUTI
OUT SAMPLE

x2 Yx3 VII

x2

x2 Va

x2

x3 Val

IOUTI

I

~H

SAMPLE I

IOUTI

Vx

x3 Yx1

Vxl V.

IOUTI
I

~ I SAMPLE I OUTI

UT
lOUT I SAMPLE I

S~
~

x2

Vx3

Va3 Val

-------IIlL..---------------\S)-S--------

Gf-Z ____________~r_1~____~~----------------------~%)---------------G~-480

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _·_'j···S~

Video

DL/DR ____________J -___ L_ _ _ _L____ L_ _~_ _ _ _~_ __ L_ _ _ _L_~~-L-------------

OE

~il~~~~~~5Iii~lf~Ir-

I.

::~~= [ CB
FD

~

]

D3k+Z
D3k+3

Ga-l

PLE

------'A

0
D3k+l

I SAMPLE lour!

I SAMPLE I

XX XXXXX
XXXXXXX
X X X XX XX

I SAMPLE lOUT I

I SAMPLE lour!

OUT
PLE
T SAMPLE
SAMPLE OUT
SAMPLE OUT

louT! SAMPLE I

IOUTI SAMPLE I

I

I

IOUTI SAMPLE I

Sf-~"Io""'ufn-I--.-----,

~

0 T
SAMPLE OUT

~

I

SS

I
IOUTI
I SAMPLE louT!
I SAMPLE I

I

-~ X X
-~ X X
-~
X X

--------------~r-1L----------------·

__--~~~S------_______

GrZ ---------~I]~..~..~.. -~-------~~~~--------'l.~~

GIi-480 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . ..

HITACHI
..- ...

--~~

..•- .

--~.

1065
._--

._-_ _.._ - - ..

HD66300T

MODE 7

Dis

Vee

L/F

GND

MSFI

Vee

MSF2

Vee

Video

DL/DR

DE
FD

Sample and
hold circuits

"
""i1
a;

u::

['
8

~

I SAMPLE lOUT I I SAMPLE IOUTI I SAMPLE lourl I SAMPLE IOUTI
I S~
I SAMPLE I IOUTI SAMPLE I lourl SAMPLE I IOUTI SAMPLE I IOUTI .=n~
I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE IOUTI
SAMPLE loUT I ~\
I SAMPLE I lourl SAMPLE I IOUTI SAMPLE r IOUTI SAMPLE I I)~
Vxl

Vxl

D3k+l

Vxl

D3k+Z

Vx2 VxZ VxZ Vx2

G~-Z

Ga-480

Vxl Vxl

Vxl

Vxl Vxl

Vxl

Vxl

Vx2 Vx2

VKJ Vx3 VxJ Vx3 VxJ VxJ VxJ VxJ Vx3

D3k+3

Ga-l

Vxl Vxl Vxl

Vxl

IOUTI
I IOUTI
I SAMPLE lourl
I SAMPLE I IOUTI

Vxl

Vx2 Vx2

VxJ Vx3 VxJ VxJ

------~!lL------------------------~~~S-----------------~~L--~~~~----------~~~S---------

------------------------------4--S~

Video

DL/DR

OE
FD

~

['

Sample and B
hold circuits ~
:Jl

"
"'"c

\~
I ~~ lOUT I
SAMPLE
OUT SAMPLE
UT SAMPLE
OUT
~ I lourl
SAMPLE OUT
SAMPLE OUT
SAMPLE OUT
\ I SAMPLE Iourl
I SAMPLE I lOUT I SAMPLE I IOUTI SAMPLE I lourl SAMPLE I I SS I SAMPLE I I
I SAMPLE lourl

I SAMPLE lOUT I

I SAMPLE lourl

0

""

--'-"~>-J V'll

Vx2

D3k+2

--,"--..00--<':"--'",,-,/ Vy2

Vx3 Vyl Vx

.D3k+3

Vxl Vy2 Vx3 V l' VxZ

Vy3 Vxl Vy2

Vy3 Vxl V Z Vxl Vyl Vx2 Vy3
Vy3 Vxl

Vx3

Vxl VyZ

VyZ Vx3 Vyl "-Vx::.::Z"V,-,-y,,,3 ""","-'-'"

Ga-l

______~rlL________________________~II~I------------

Ga-2

__________

G~-480

1068

Vy3

lour!
I 10UTI
I SAMPLE lourl
I SAMPLE I 10UTI

~rtL

____-=____________________
-------------

_;I~I-------------

--------------------------------------~-~~.
HITACHI

HD66300T

MOOE10

Dis

Vee

L/F

Vee

MSFl

Vee

MSF2

Vee

~

Video

OL/OR

I

DE

FO
I SAMPLE IOUTI
Sample and [ :
hold circuits C

I SAMPLE I

I SAMPLE IOUTI

IOUTI SAMPLE I

I SAMPLE IOUTI

o

I SAMPLE I
V,l

Vyl

I SAMPLE lour!

IOUTI SAMPLE I

I SAMPLE IOUTI

lourl SAMPLE I

V,1

Vyl

Yxl Vyl

I SAMPLE-loUTI

lourl SAMPLE I

I SAMPLE IOUTI

IOUTI SAMPLE I

IOUTI

I

S~

I

S\ I

IOUTI
IOUTI

I SAMPLE IOUTI S~ I SAMPLE IOUTI

lOUT I SAMPLE I

I S~ I SAMPLE I

IOUTI

V,1

Y,Z VyZ

y,Z YyZ Yx2 vy2 vxZ

Vx3 Vy3

v,3

Vy3 VK3 VyJ vx3 Vy3 Vxl Vy3 Vx3

y3

,3 Vy3

____________________________~~~------------

Ga-l

________~IlL_

Ga-2

__________--'!lL__~=:------------.,S~I_-------

Ga-480

--------------------------------------------------\--i:~

Video

OL/OR
DE

FO

~~~~~~~~~~~~~~~~~~;~~~~--I SAMPLE IOUTI
I SAMPLE IOUTI
I SAMPLE IOUTI
I SAMPLE IOUTI
I ~\ lourl
A

Sample and

[B

hold circuits Co

I SAMPLE I
I

IOUTI SAMPLE I

I SAMPLE lOUT!

I SAMPLE I

03k+l

Vyl

V.I

IOUTI SAMPLE I

I SAMPLE IOUTI

lourl SAMPLE I

Vy.

V)(, Yr'

IOUTI SAMPLE I

I SAMPLE

lOUT!

IOUTI SAMPLE I

Viti Vy'

Viti

Vyl

Vxl

I

IOUTI

IOUTI SAMPLE I

Yy.

I

SAMPLE IOUTI

I

S\

I

~t I

S\

IOUTI
SAMPLE IOUTI

I SAMPLE I

IOUTI

"V::.;'I",-,YY",I.=J\:.~

Ga-l

________~!lL-__________________~____~II~\------------

Ga-2

_____----~!lL----~~------------------~III--------------

Ga-480

---------------------------------------.-----4--\~

HITACHI

1069

HD66300T

MODEll

Dis

Vee

L/F

Vec/GND

MSFI

Vee

MSF2

GND

~

Video

DL/DR

I

OE
FD

---1

r

Sample and B
hold circuits ~

~

'"
~

D3k+l

I SAMPLE lour! I SAMPLE lOUT I I SAMPLE IOUTI I SAMPLE IOUTI
I S~
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I IOUTI I S\
I I SAMPLE IOUTI I SAMPLE lour! I SAMPLE loun I SAMPLE IOUTI S\
I I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I I S~
Vxl

Vyl

Vxl Vyl

D3k+2

Vxl Vyl Vxl Vyl Vxl

D3k+3

Vx3 Vy3

Ga-l
Ga-2
Ga-480

Vxl Vyl

Vxl

Vyl

Vxl

IOUTI
I IOUTI
I SAMPLE IOUTI
I SAMPLE I IOUTI

Vyl

Vxl Vyl Vxl Vyl

~

Vx3 Vy3 Vx3 Vy3 Vx3 Vy3 Vx3 VyJ YxJ Vy3 Vxl Vy3 Vx3

--------~,,~--------------------------~~~---------------------~,,~--~==------------------~~~----------------------------------------------~--S~

Video

DL/DR

OE
FD

I

['

Sample and B
hold circuits ~

~

'"
'0
C

I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE lour! I SAMPLE IOUTI
I ~\
I SAMPLE I lOUT I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I loun I ~\
I I SAMPLE lour! I SAMPLE IOUTI I SAMPLE louT! I SAMPLE lou" S\
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I I S\

IOUTI
I IOUTI
I SAMPLE IOUTI
I SAMPLE I lour!

8
Jl D3k+l ~v-~-,r-"-v~VX~I~Vy~I~V~x~I'~y~lhV~xl~Vy~I~Vx~I~V~y~I~V~x~I~V~yl~VX~I~Vy~I~V~X~I~y~I~~
D3k+2

--''''-..L>.-L",,-~.J VxJ Vy3

Ga-l

--------~rtL

Ga-480

=1V':"'y-::2v.;:Vx::;-2~:;v:~'

VyZ

D3k+3

Ga-2

1070

VxZ

VxJ VyJ Vxl Vy3 "Vx;;.:3,,-,,,-,,=,,,,-,,,,,==,,,-,=

____________________________I~~-----------__________~rtL____~~___________________;I\I-------------------------

------------------~------------~-,~
HITACHI

HD66300T

MODE12

Dis

Vee

L/F

GND

MSFI

GND

MSF2

Vee

Video

DL/DR

DE
FD

-.~~

hold circuits

C

0

I SAMPLE lour I I SAMPLE lourl I SAMPLE lourl I SAMPLE lourl
I ~E-\r.lo"'u"'rlr--,---,
I SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I lour! I ~\ I lourl
I I SAMPLE lourl I SAMPLE lour I I SAMPLE lourl I SAMPLE lourl SI I SAMPLE lourl
I SAMPLE I lour I SAMPLE I lour I SAMPLE I lour I SAMPLE I I S~ I SAMPLE I lour I

D3k+l

Y,1

Y,3 Y,2

D3k+2

Y,2

v"

D3k+3

Y,3 V,2

Ga-l
Ga-2

v"

Y,3 V,2

YxJ VxZ

v"

v"

Y,3 Y,2

Vx3 VXZ Vxl

v"

Y,3 Y,2

v"

Yx3 Yx2 V.' Y,3 Y,2

Yx3 Yx

v,,

Y,3

______~!lL------------------------~S~\-----------________~!lL__~__=__ =
___~__-___-_..-..-.--------------~~----------------.- -------.-

G~-480

----------------------~------------~--S~

Video

DL/DR

DE
FD

I

~-·t
hold circuits

C

l!
G

'"

0

S~
I \S
I S\
lourl I SAMPLE lourl ~\
I lourl SAMPLE I I S\

I SAMPLE lourl I SAMPLE lourl I SAMPLE lourl I SAMPLE lourl
I SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl

I

I SAMPLE lourl I SAMPLE lourl I SAMPLE
I SAMPLE I lourl SAMPLE I lourl SAMPLE

lourl
I lourl
I SAMPLE lourl I
I SAMPLE I lourl

."
C

8 D3k+l

Vyl Vy3 Vy2 Yyl Vy3 Vy2 V 1 Vy3 VyZ Yyl Yy3 VyZ

c1l

D3k+2

--"C>o.-.L>.-~-L"--"

D3k+3 --"-'--D..-..£>.---L"--"

V 2 Vyl

Yy3 Yy2 Vyl

Vy3 VyZ

Vyl Vy

yl

Yy3

Vy2 Vyl Yyl Yy2

Vy3 Vy2 Yyl Vy3 Vy2 Vyl Vy3 V'l2 Vyl Vy3 V 2 Vyl. Yyl VyZ

__________________~!~l------------

Ga-l

--------~rlL------

Ga-2

__________~!lL____~~------------------*«-------------

G~-480

------------------------------·----4-~~

---- -. --. - ------

HITACHI

1071

HD66300T

MODEI3

DIS

Vee

L/F

GND

MSFI

GND

MSF2

GND

Video
DL/DR

OE
FD

Sample and

I SAMPLE
I SAMPLE
I
I

[
B

hold circuits ~

lour I I SAMPLE lourl I SAMPLE lourl I SAMPLE lourl
I Sf-\r.lo"'u'01r1r--.,.----,
I lourl SAMPLE I lourl SAMPLE I lour! SAMPLE I lourl I ~~ I lourl
I SAMPLE lour! I SAMPLE lour! I SAMPLE lourl I SAMPLE lourl ~~ I SAMPLE lourl
I SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I I S~ I SAMPLE I lourl

D3k+l

Vx 1 Vx2

Vx

Vx 1 VxZ Vx3 Vx 1 V"Al Vx3

D3k+Z
D3k+3

Ga-l

___---In

~\

Ga-Z

_ _ _ _--'11

SS

Ga-480

-----------------------------------------4----S~

Video

283

284

DL/DR

OE
FD

I
I SAMPLE

['

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hold circuits ~

il

"'"8c:

.

en

lour! I SAMPLE lour! I SAMPLE lourl I.SAMPLE lourl
I S\ lourl
lour! SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl I S\ I lourl
I SAMPLE lour! I SAMPLE lour! I SAMPLE lour! I SAMPLE lourl S\ I SAMPLE lour!
I SAMPLE I
lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I I S\ I SAMPLE I lourl

I SAMPLE I

D3k+l

Vyl

D3k+Z

VyZ VyJ Vyl VyZ Vy3 Vyl

V 2 Vy3 Vyl VyZ Vy3 Vyl

VyZ Vy3 yyl Vy2 "V,-"y3"",yCJ'''''-''''=~

D3k+3

Ga-l

1072

________~rlL____________________________~!~I-------------

Ga-Z

----------~n~--~~=_------------------11~1-------------

Ga-480

-------------------------------------~i~

~-------------

HITACHI

HD66300T

MOOEI4

Video

21

0/5

Vee

L/F

GNO

MSFI

Vee

MSF2

Vee

22

DL/DR
DE

FD

~

Sample and B
hold circuits ~

:!"

~

D3k+l

I SAMPLE lOUT I I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE IOUTI
I S~
I SAMPLE I lOUT I SAMPLE I IOUTI SAMPLE I lOUT I SAMPLE I lOUT I I ~\
I I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE IOUTI ~\
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE! IOUTI SAMPLE I I SS
V,1

V,1 V,1

V,3

V,3

V,1

V,1

V,1

V,1

IOUTI
I IOUTI
I SAMPLE IOUTI
I SAMPLE I lourl

V,1

~

D3k+2
D3k+3

V,3 'VI(3 VxJ

Vx3 V.3 Vxl Vxl Vxl Vxl Vxl Vxl

Ga-l

------~!I~--------------------------'\rl-----------­

Ga-2

________~!IL__~~------------------~~------------

G~-480

-------------------------------------~---~----S~

Video

DL/DR
OE
FD

I

Sample and

['

B
hold circuits ~

I SAMPLE lourl I SAMPLE lour! I SAMPLE lourl I SAMPLE lourl
I S~
I SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl I \\
I I SAMPLE lourl I SAMPLE lourl I SAMPLE lOUr! I SAMPLE lourl ~\
I SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl SAMPLE I I S\

D3k+l

Vy1

V'II

V'll

D3k+2

VyZ

Vy2

V 2 Vy2

Vyl

IOUTI
I lourl
I SAMPLE lourl
I SAMPLE I lourl

V 1 Vyl V 1 vyl V 1

D3k+3

-<'",,-L.>--<->"--"'--' V 3 V 3 V 3 Vy3

Ga-l

--------~!I~----------------------------~lIr-------------

Ga-2

__________~rJL____~~------------------~III-------------------------

G~-480

-----------------------------------~-i~

Vy3 Vy3

HITACHI

1073

HD66300T

MODElS
D/S

GND

L/F

Vee

MSFI

GND

MSF2

Vee

20

Video

DL/DR
OE
FD

-[:

ISAMPlEI OUT ISAMPlE lOUT I SAMPlE! OUT I SAMPlE lOUT I SAMPlE lOUT I SAMPlE I

hold

C

Not used

circuits 0

I SAMPI.E lOUT I SAMPI.E lOUT I SAMPlE lOUT I SAMPlE lOUT I SAMPI.E I but I

i

'"
~

D3k+l

Vxl

Yy2

Vx3

V.I

Vx2

V.3

Vxl

Yy2

¥x3

VI

D3k+l

Vx2

V.3

Vxl

Yy2

Vx3

V.I

Vx2

Yy3

Vxl

Yy2

D3k+3

Vx3

V.I

Vx2

V.3

Vxl

V.2

Vd

V.I

Vx2

Ga-l
Gail
Ga:Z40

SSI OUT I

Not used

and

__________~r--1L________________----------------~!~~------------__________~r--1~__~~-_..-_....-..-.. _-..-.. _-.._-..-___-..-.__-..-...-__-_..~~~~
...-._--.------

I SAMPlE lOUT I SAMPlE lOUT I SAMPlE lOUT I SAMPlE I

\\ I SAMPI.E lOUT I

Not used
Not used

I

I

X

X

X

X

X

X

X

X

X

X

I SAMPI.E lOUT I SAMPlE! OUT ISAMPlE lOUT ISAMPU lOUT I

X X X X X
________

~r_,

\~ lOUT I

S\

.--..Q.------...-.... ---....... ----.... ---.~~

1074

HITACHI

HD66300T

MODEI6

Dis

GND

L/F

Vee

MSFI

GND

MSF2

GND

Video

DL/DR

DE

FD
rSAMPLE!

A
Sample

and

[8

Not used

hold

C

Not used

circuits

0

OUT rSAMPLE

rSAMPLE!

D3k+l

Vxl

OUT

rOUT rSAMPLE!

OUT

rSAMPLE!

r SAMPLE rOUT rSAMPLE!

Vy3

Vx2

Vyl

Vx3

OUT

OUT

rSAMPLE(

Vy2

Vxl

SS rOUT r

rSAMPLE rOUT rSAMPLE!

OUT

Vy3

rSAMPLE rOUT
Vx2

~\ rSAMPLE! OUT

r

r

Vyl

D3k+2
D3k+3
Ga~l

____________~r__lL______________________________________~~,~\---------------

Ga-2

________________~r__l~____~------------------------~~&~--------------

Ga~240

-------------------------------------------------------------------~--~~

Video

DL/DR

I

tf1-SLIL-J1

DE

FD

~

j

(,I

~L-

____________________________________~\~I

A
=~;ple B
[

Not used

hold

C

Not used

circuits

0

rSAMPLEr OUT rSAMPLEr OUT rSAMPLEr OUT rSAMPLEr

I SAMPLE lOUT

I SAMPLE lOUT

(SAMPLE

lour ISAMPLll

OUT

I

___________

\\ rSAMPLE! OUT r

t\
~)

lOUT

I

D3k+l

~

X

~

~

~

~

~

D3k+2

~

X

~

X

~

Z

~

~

X X

~

~

Z

~

D3k+3
Ga-l

__________________________~r__lL__________________________~%\~--------------

Ga-2

________________________-=__ ~__~_~L-------------------~~\r-------------

Ga~240

-------------------------------,)~

HITACHI

1075

HD66300T

MOOE17

DIs

GND

L/F

Vee

MoFI

Vee

MSF2

Vee

'-----.

20

Video

Dl/DR

OE
FD

Not used

hold

Not used

circuits

il

'"

~

I SAMPlE lOUT ISAMPlE lOUT ISAMPlE lOUT I SAMPlE lOUT I SAMPlE lOUT I SAMPlE I

~~;Ple B

r
C

0

I SAMPLE lOUT I SAMPLE! OUT I SAMPlE ! OUT I SAMPlE! OUT I SAMPlE I OUT

I

SS lOUT

I

S~ !SAMPlE! OUT !

D3k+l

D3k+Z
D3k+3

Vlt3

Vy3

__________________~~~\r_----------------------~r--lL--~.. ~
.._~..~...~..-..-._-__----------------~~r--------___
--.. n---·-.. -.. ····--·---..

----------~r--lL--------------

Ga-l
Ga-;-Z
Ga~Z40

······V~

Video

".-

Lr--·-ur---u.~
! S~

Dl/DR

!

OE
FD

:2

o!l

"8

r

~

"

(J)

\\ I SAMPlE I OUT I

Not used
Not used

! SAMPLE! OUT ! SAMPLE! OUT ISAMPLE! OUT !SAMPLE! OUT !

S~

! OUT !

D3k+l

X

X

X

X

X

X

~

D3k+2

X

X

X

X

X

X

~

D3k+3

X

X

X

X X X

~

Ga-l
Ga-2
Ga~240

1076

ISAMPlE! OUT !SAMPlE! OUT ISAMPLEI OUT !SAMPlEI

Sample
and
B
hold
C
circuits 0

------------------------~r--o~------------------------~~~s-------------------------------~.•~
•• _~L
__ -_--------------~~r----------

---·---.. · .. ·---------.. --..S~

HITACHI

HD66300T

MODEl8

DIS

GND

L/F

GND

MSFI

GND

MSF2

Vee

Video

DL/DR

OE
FD
A
[B

Not used

hold
C
circuits 0

Not used

and

S~ lOUT I

I SAMPLE lOUT ISAMPlE lOUT ISAMPlE lOUT I SAMPlE! OUT I SAMPLE lOUT I SAMPlE I

Sample

S~ I SAMPlE lOUT I

I SAMPlE lOUT I SAMPLE lOUT I SAMPLEj OUT I SAMPLE lOUT I SAMPlE lOUT I

D3k+l

D3k+2
D3k+3
.Ga-l

____________

Ga-2

----------------~r--r~----~------------------------~~~S--------------

~r--lL_

____________________________________

~\'~~--------------

________________________________

-_--_---_--_---_--_--_--_--_--~-hl~

Ga:240

Video

DL/DR

OE
FD

:2

'"•

Not used

hold
circuits

Not used

'C
C

8

c1l

~

I SAMPlE lOUT ISAMPlEI OUT ISAMPlE! OUT I SAMPlE I

:~~Ple 8

C

0

I SAMPLE I OUT

I !j,\MPlE lOUT

ISAMPLE lOUT ISAMPlE

I

OUT

I

\\ ISAMPLE! OUT I

S~ I

OUT

I

D3k+l

X

X

X

X

X

X

~

D3k+2

X

X

X

X

X

X

XSifX:ii£l3iIXJifX3iIX31IXSfY::S)::13IXJiIX::::r..

D3k+3
Ga-l
Ga-2
Ga-240

X X X X X X ~~
________________________
________________________ ______________
~r__r~

~~~\

~-----------------h __ h __ h _____ h __ ~~
HITACHI

1077

HD66300T

MODEl 9

Dis

GND

L/F

GND

MSFI

GND

MSF2

GND

Lr--'l."~

Video

,

DL/DR

DE
FD

SS ,

, SAMPLE! OUT 'SAMPLE , OUT , SAMPlE , OUT , SAMPlE , OUT , SAMPLE , OUT , SAMPlE'
Sample [:.

and
hold

Not used

C

Not used

circuits

0

OUT ,

~~ !SAMPLE! OUT !

'SAMPlE! OUT , SAMPLE! OUT !SAMPLE! OUT !SAMPLE! OUT !SAMPLE! OUT!

D3k+l
D3k+Z
D3k+3
Ga-l

__________-Jr--lL-______________________________

Ga;Z

____________~r-!~__~...~._-.__-._.._-_.-__-__-__-__-__-__-__-__ -__ -__ -.. _-__-__-__-__-_.-..-__~:~r-----.----------

Ga~Z40

~~\\-------------

~

Video

!

DL/DR

DE
FD
Sample

and
hold

.
'"..,
.8
31

circuits

c

~

\\ !SAMPLE! OUT'

Not used

0

I SAMPlE I OUT IW!!PlEI OUT ISAMPLEI OUT ISAMPLEI OUT I

~~

I OUT I

D3k+l

X

X

X

X

X

X

~~

D3k+Z

X

X

X

X

X

X

lGDGillGillGDCEDGDGDC$X]!DC:yrDC::::X:

X

X

X

X

X

X

Ul

D3k+3
Ga-l
Ga-Z
Ga-240

1078

!SAMPlE! OUT !SAMPLE! OUT !SAMPLE! OUT !SAMPLE!
Not used

B
C

__________________

~~
~r-J~

__________________

~~~

___________

------------------------~_.~._~_~~------~------------~~r-------------

--n---------·--------------·------·--S~

HITACHI

HD66300T

MODE20

Dis

GND

L/F

GND

MSFI

Vee

MSF2

Vee

Video

DL/DR

DE
FD

I SAMPlE!

A

~~;ple B

Not used

hold

C

Not used

circuits

0

[

OUT ISAMPlE

I SAMPLE I OUT

D3k+l

V,I

V,1

D3k+Z

V,2

V,2

D3k+3

V,3

V,3

I

OUT

ISAMPLE I

I SAMPlE I
V,1

V,3

OUT

I SAMPLE lOUT I SAMPLE I

OUT ISAMPLE I OUT
V,1

Vd

V,1

V,3

I SAMPLE I

OUT

ISAMPLE lOUT ISAMPLE I

V,1

V,1

V,1

V,1

V,2

V,2

V,2

V,2

V,3

V,3

V>3

V,3

OUT

I

SSIOUTI

S~ I SAMPLE lOUT

I

V,1

V,3

Ga-l

__________~r__lL________________________________~~\\r_-----------

Ga-Z

----------------~r--lL----~~------------------------~V~i----~----------n--------_n ___ n __
h

Ga~Z40

_ _ _ _ _ _ _ n_~

Video

DL/DR

DE
~

FD
Sample
and

hold
circuits

~

I SAMPLE I OUT ISAMPLE! OUT ISAMPLEI OUT ISAMPLEl

\\ ISAMPLE lOUT

I

Not used

B
C

Not used

0

ISAMPLE lOUT

D3k+l

X

X

X

D3k+Z

X

X

X

D3k+3·

X

X

X

I SAMPLE lOUT ISAMPLE! OUT I SAMPLE lOUT

1

S~ lOUT

I

Ga-l

______________________~r__lL________________________~~r-------------

Ga-Z

____________________~r--l~----------------~~----------_

Ga~Z40

------------------------------------------------------~---S~

HITACHI

1079

HD66300T
NTSC System TV Signals and LCD
A TV screen display, which is updated 30 times per
second, is called a "frame" and is composed of 525
scanning lines. One frame contains two fieldsi scanning lines 1 to 262.5 scanthe display in the first field,
and scanning lines 262.5 to 525 scan the display in the
second field to fill the gaps which are left unscanned
in the first field. This scanning mode is called an
"interlace scan."
The time period in which one scanning line scans the
display is called a "horizontal scanning period" and is
about 63.5 f.Ls. Within the horizontal scanning period,
the time period that display operation is actually
performed is called the "valid display period". The
other period is called the "horizontal retrace period".
There are two modes for displaying a TV screen image
on an LCD panel. In the first mode, each scanning line
in the two fields is assigned to one line of the LCD
panelithus, each of the 240 lines of the panel are driven
by the positive signal in the first field and by the
negative signal inthe second field. Here, 3D-Hz alternating frequency is available, but the number of vertical pixels is limited to 240.
(Single-rate sequential drive mode)

can be driven likewise by the second field. In this case,
if one pixel of the LCD panel is considered, it is recognized that the pixel is driven by signals with opposite
polarity every frame. This lowers the alternating frequency to 15 MHz, which is only half of the frame
frequency. Driving LCD elements with signals of such
low alternating frequency causes flickering and degrades display quality. To raise the alternating frequency to 30 MHz, a method can be employed in
which LCD elements are driven once every field instead of once every frame.
Specifically, in the first field, the first and second lines
of the LCD panel are driven respectively during the
first half and second half of the complete horizontal
scanning period. The same rule is repeated for the
following lines. In the second field, on the other hand,
the combination of two lines is different. The first line
is driven during the second half of the horizontal
scanning period, and then the second and third lines
are driven respectively during the first and second
half of the following horizontal scanning period. The
same rule is repeated for the following lines.
Employing this method enables the implementation
of 480 vertical pixels.
(Double-rate sequential drive mode)

In the second mode, every other line of the LCD panel
can be driven by the first field and the remaining lines

---

--

---------

23

-- -- ---------

24

----25

286

------- --- ---

287

I
I
I
I

I

:

!

:
!
1

:

!

262
263

285

I

!

----- -------

i

523

------- ------

524

------ ------- -- ----

Scanning line No.
in the 1st field

525

Scanning line No.
in the 2nd field

Figure 24 Example of NTSC System TV Signals Scanning
1080

HITACHI

HD66300T

,-

23 A

1st line

,-

24 D1 -

2nd line

25 A

3rd line

---

260 D

,238th line

261 A

239111 Une

262 D

240th line

Scanning line No.
in the 1st field

I-- D
I-- A
I-- D

-,

A

286
287
288

523

_ ID 524

1-,A

525

Scanning line No.
in the 2nd field

Figure 25 Middle-Resolution Display by Single-Rate Sequential Drive Mode

C
23

A

1st line

o

B

2nd line

A

C

3rd lin8

B

: 0

4th line

C

24

285

286

o

287

C

: A
261

262

237th line

o

B

2381/1 line

A

C

239th line

B

o

240th line

524

C

o

Scanning line No.
in the 1st field

523

S25

Scanning line No.
in the 2nd field

Figure 26 High-Resolution Display by Double-Rate Sequential Drive Mode

HITACHI

"

--'-------------------------

1081

HD66300T
Absolute Maximum Ratings
Item

Symbol

Ratings

Unit

Remarks

Power supply for

Vee

-0.3 to +7.0

V

VBB

VCC- 23 to Vee+ 0.3

V

VTC

-0.3 to Vcc+ 0.3

V

3

VTB

VBB- 0.3 to Vcc+ 0.3

V

4

Note

logic unit
Power supply for
analog unit
Input voltage for
logic unit
Input voltage for
analog unit
Operating

~to+75

'C

Applies to logic circuit

-10 to +60

'C

Applies to analog circuit

TSIg

-40 to +125

°C

VLCD

VBBto Vee+ 0.3

V

Topr

temperature
Storage
temperature
LCD level voltage

Notes:

1.
2.

3.
4.

1082

Value referred to GND =0 V.
If LSIs are used above absolute maximum ratings, they maybe permanently destroyed. Using them
within electrical characteristics limits is strongly recommended for normal operation. Use beyond
these conditions will cause malfunction and poor reliability.
Applies to pins HCK1, HCK2, HCK3, DL"DR, FO, RS, OE,SHL, 0/5, L/F, MSFl, MSF2, TESfl,
TEST2, Vbo, VbsH, and VbsB.
Applies to pins Vxl, Vx2, Vx3, Vyl, Vy2, and Vy3.

til1r~~til

Electrical Characteristics
DC Characteristics (VLCO = Vcc=5V ±10%,GND=OV, Vcc - V BB = 16 to 20 V, Ta =-20 to +75 °C)
hem

Symbol

Min

Input high-level voltage
Input low-level voltage

VIH
Vil

0.7 Vee
GND

Output high-level voltage

VOH

Vee -0.4

Output low-level voltage

VOL

V

4

-l oH =0.3rnA
IOl =0.3 mA

1

+10
-150

IIA

-10

IIA

VI = VBB ' Vee
Vee - VBB = 20 V
Apply Vin to Vx and Vy.

2

+150

IIA

Vin = (Vee - VBB)12
Voo =Vee -3V

+10

IIA

IU2
lOUT

~

3

V

VI = 0 V, Vee

Output current (1 )

:E Current consumption

V

IIA

-10

liN

Vee
O.3Vee

Notes

Test Conditions

V

IUl

;t Output current (2)

Unit

0.4

Input leakage current (2)

l:

Max

+10

-10

Input leakage current (1)

Typ

IGNO
15

IBB

IIA

3.0

rnA

30

iliA

Ok = Vin - 0.5 V

OE = Vee 5
OE=GND

OK = Vin + 0.5 V

VbsH =Vee -3V
VbSB = Vee - 3 V
= 2.5 MHz, Voo = Vee - 3 V
VbSH = Vee -3 V, VbSB = Vee -3 V
fCk

OE= Vee
OE=GND
6

OE = 33kHz,
FD= 30 Hz
OE duty = 7/32
Bias voltage

Vb

Vee -4.0

Dynamic range

VOY

VBB + 1.5

Vee -3.0

V
Vee -3.5

V

Voo = VbSH = VbSB,
Cl = 100 pF, tOOR ~ 6.3 lis
Vee -VBB =20V,

Ta = -10 to +60°C
-0.5 V < VOlt < +0.5 V
Voo = VbSH = VbSB = Vee - 3 V
0

co
w

::r:
5,7,9

0
en
en
W
0
0

t-3

g DC Characteristics (VLCD = Vee = 5 V ±10%, GND = 0 V, vee -

VBB = 16 to 20 V, Ta = -20 to +75 °C) (Cont.)

l>-

Hem
Offset voltage

Symbol

Min

VOff(L)

-5-180

VOff(H)

+55-180

Typ

Max

Test CondHlons

-5 + 180

Un"
mV

+55 + 180

mV

fCk

Vee - VBB =20 V

Notes
Yin

=-11 V

Yin

=-1 V

Ta = -10 to + 60°C
= 2.5 MHz

= Vee -3 V

J:

o~

1.

2.
3.
4.
5.
6.

Applies to pins HCK1, HCK2, HCK3, DL, DR, FD, RS, OE, SHL, DIS, L/F, MSFl, MSF2, TESTl, TEST2, Vho' VbsH' and VbsB'
Applies to pins Vx1, Vx2, Vx3, Vy1, Vy2, and Vy3.
Applies to pins HCK1, HCK2, HCK3, DL, DR, FD, RS, OE, SHL, DIS, L/F, MSF1, MSF2, TESTl, and TEST2.
Applies to pins DL and DR.
Applies to pins 01 - 0120.
The shift register is constantly shifting one 1.
Mode setting: L/F = VCC' DIS = VCC' MSFl = GND, MSF2 = VCC

-J:
7.
8.
9.

(The other jnput pins must be Vcc or GND level.)
The operations are the same as those when offset voltage is measured.
Definition of "offset voltage" is shown figure 27.
These characteristics are defined within the temperature which is shown in the test condition.

m

w
o
o

~

Voo = VbsH = VbSB

Notes:

5,8,9

S
m

HD66300T
AC Characteristics t HLI)

HITACHI

1085

HD66300T

OE

::

~"::~!l,----

~ ~ ~)-----1 ! 10jts
"

I

I

I

.. ,

:

:

'

I
I

60t's
1•

:
-lV

Dout

•

59t's

I

~

r:

•

I

I.

I

:

I

60t's
I

SS~
: 59t's

----------------1--------

I

-------------------- --------------

Voff(H)

-l1V ----------------------------

)5

Voff(L)
------------ ---------------

t

Figure 27 Offset Voltage

HCKl

HCK2

HCK3

Figure 28 Three-Phase Clock Timing

1086

HITACHI

HD66300T

0.7Vcc
0.3V cc

HCK1

HCK2

HCK3

0.7V cc
0. 3V cc

OL
DR
(OUTPUT)

"----t-------------

OL
DR
(INPUT)

tsu

Figure 29 Input and Output Timing

-

~

tOWH

0.7Vcc

OE
.....J

0.3VCC
t ..

t'H

}~ r

J

'- 0.7V CC

FO

O.3Vcc

tDDR

~90%(Vin-Vcc-3.5V)

01-0120

X

10%(Vin=V •• +1.5V)

Figure 30 OE, FD Input Timing, Driver Output Timing
HITACHI

1087

HD66310T-----------(TFT -Type LCD Driver for VDT)
Description
The HD66310T is a drain bus driver for TFr-type
(thin film ttansistor) LCDs. It receives 3-bit digital
data for one dot, selects a level from eight voltage
levels, and outputs the level to an LCD.
The HD66310T can drive an LCD panel with an
RGBW filter to display a maximum of 4096
colors.

Features
•

•

•
•
•
•
•

High-speed operation
Number of input data bits: 3 bits x 4
Maximum operation clock frequency:
- l2MHz(HD66310TOO)
- 15 MHz (HD6631OTOOI5)
Maximum pixels: 480 x 640 dots
160 internal driver circuits
Bidirectional shift
Internal chip enable signal generator
Stand-by function
LCD driving voltage: 15 V to 23 V
CMOS process

Full color display: a maximum of 4096 colors
RGB color filter: 512 colors, 8 gray scales
RGBW color fIlter: 4096 colors, 8 gray scales

Ordering Information
TYpe No.

Max. Operating
Clock Frequency

Power Supply
for Logic Unit

Operating
Temperature

Package

_H_D_6_63_1_0_T_00_ _ _ _1_2_M_H_z_ _ _ _ _ _5_V_±_1_0_%_ _ _ _
-2_0_t_o_+_7_5_oC_ _ 203-pin TCP
HD66310T0015

15 MHz

5 V ± 5%

-20 to +65°C

Note: The details of TCP pattern are shown in "The Information of TCP:

1088

HITACHI

HD66310T
Pin Arrangement

Yl54 Yl56 Yl58 Yl60
Yl!B Yl55 Yl57 Yl59

(Top view)

1
2
3
4
5
6
7

VOL

Vll
V2l
Wl
V4l
V5l
V6l
8 V7l
9 Vee,
10 VCC2
11 EI01
12 RVS
13 DOO
14 DOl
15 D02
16 D03
17 DMYO
18010
19011
20 012
21 013

22 DMYl
23 D20

24021
25 D22
26 D23

'Z1 DMY2
28 CL1
29 CL2
30BS

31 SHl
32 EI02
33 TEST
34GND
35 VEE
36 V7R
37 V6R
38 V5R
39 V4R
40 V3R
41 V2R
42 V1R
43 VOR

Note: This does not apply to TCP dimensions.

Pin Description
Pin List
Pin Name

Number of Pins

Input/Output

Functions (Refer to)

Vcc1, Vcc2
GNO

2

Power supply

1.

1

Power supply

16

Power supply

2.

Input

3.

Power supply

VEE
VOL-V7L,
VOR-V7R
CL1
CL2
000, 010, 020,
to
003,013,023

12

RVS

Input

4.

Input

5.

Input

6.

1

Input

7.

EI01, EI02

2

Input/output

8.

TEST, BS

2

Input

9.

Y1-Y160

160

Output

10.

OMYO-OMY2

3

SHL

11.

HITACHI

1089

HD66310T
Pin Functions
1. Vee l, Vee 2, GND, VEE: These pins are used
for the power supply.
Vcc-GND: Power supply of low voltage
Vee-VEE: Power supply of high voltage
2. VOL-V7L, VOR-V7R: 8-level LCD driving
voltage is applied to these pins. One of the eight
levels is selected according to the value of the 3-bit
input display data. The L and R pins of the same

voltage level are connected in the driver.
3. CLl: Inputs clock pulses, which determine the
output timing of the LCD driving voltage. The
output changes at the CLl rising edge.
4. eL2: Inputs clock pulses, which detennine the
input timing of display data. The driver samples
data at the CL2 falling edge.

Table 1 Voltage Level Selection According to Display Data Value
Display Data

Voltage Level

02J

D1J

DOJ

RVS=1

RVS=O

0

0

0

0

0

1

0

1

0

VO
V1
V2
V3
V4
VS
V6
V7

V7
V6
VS
V4
V3
V2
V1
VO

1

0
0

0

0
0

1

Vee

GND

.1+
J-

+

_10..

VEE

Figure 1 Power Supply for the Device

1090

HITACHI

HD66310T

s. Doo-003, DlO-Dl3, D20-»23:

Input display

data. See table 1 for the voltage level selection by
the display data.

or output When the chip enable input signal is
low, data input starts. When display data corresponding to 160 outputs are input, the chip enable
output signal changes from high to low.

6. RVS": Determines if logical I/O display data is
reversed. Display data is reversed when R.VS is
low.

9. TEST, BS: Used for test purposes only.
Connect to a low level for nonnal operation.

7. SHL: Selects the shift direction of display data.

10. Yl-Y160: Output LCD driving signals.

8. EIOI, EI02: Inputs/outputs chip enable signals. The SHL signal selects which pin is for input

11. DMYO-DMY2: Reserved pins that should be
left open.

Table 2 Input/Output Selection for EIOI and
EI02
SHL

EI01

El02

GND

Input
Output

Output
Input

Vee

Output Direction

SHL

GND

Vee

i-o-2
DiO
Di1
Di2
Di3
(12 bits)

i .. o-2
DiO
Di1
Di2
Di3
(12 bits)

d03,d13,d23
d02,d12,d22
d01,d11,d21
dOO,d10,d20

5

Y1
Y2
Y3
Y4

d03,d13,d23
d02,d12,d22
d01,d11,d21
dOO,d10,d20

Y157
Y158
Y159
Y160

dOO,d10,d20
d01,d11,d21
d02,d12,d22
d03,d13,d23

Y1
Y2
Y3
Y4

5

dOO, d10, d20
d01,d11,d21
d02,d12,d22
d03,d13,d23

Y157
Y158
Y1.59
Y160

Figure.2 Display Data and Output Direction

HITACHI

1091

HD66310T
Internal Block Diagram

Y156 Y158 Y160
Y157 Y159

Y1 Y2Y3Y4 Y5
VOL, V1L
V2L, V3L _ _ _ _ _ _ _~
V4L, V5L
VSL, V7L

--------,.1

LCO driving circuit

Vcc1,Vcc 2 _
GNO
VEE
~ Test circuit
TEST

.1 r

Level shifter

1

RVS-----,
CL1
BS
Oata reverse
circuit
000,010,020
001,011,021
002,012,022
003,013,023

---===il

SHL
CL2-----,

EI01
EI02

1092

Latch address selector

":~~===:~::::::::::::::::::::::::::::::::::~J
11.

HITACHI

VOR,V1R
V2R,V3R
V4R,V5R
V6R,V7R

HD66310T
Block Functions
Latch Address Selector: Contains a 6-bit upl
down counter and a decoder, and sends the latch
signals to latch circuit (1) at the CL2 falling edge.

Latch Circuit (2): Consists of three planes of
160-bit latch circuit, which latches the data from
latch circuit (1) at the timing determined by CLl,
and holds the data for one line scanning period.

Data Reverse Circuit: Reverses the input display
data when RVS = 0, and does not reverse data
whenRVS= 1.

Level Shifter: Raises the driving voltage of 5 V
to the appropriate LCD driving voltage.

Latch Circuit (1): Consists of three planes of
160-bit latch circuit. Each bit of 3-bit data is separately latched in its corresponding plane depending
on its significance. Each plane is divided into
forty 4-bit blocks, and all four bits are latched into
the block at once, as specified by the latch signal
from the address selector. In total, the 3-plane circuit latches 12 bits of data at one time.

LCD Driving Circuit: Outputs an 8-level LCD
driving voltage. This circuit receives 3-bit data for
one dot from latch circuit (2) and selects one level
from eight voltage levels.
Test Circuit: Generates test signals.

HITACHI

1093

HD66310T
System Configuration
A block configuration of the TFf-typecolor display system using the HD66310 is shown in figure

3.
The HD66310 receives 3-bit data for one pixel and
selects one of the eight LCD driving voltage levels
to send to the LCD. The LCD driving output

circuit, which is produced by the CMOS Slructure,
can use any LCD driving voltage level from Vcc
to VEE' When the LCD panel uses an ROB color
filter (the Triad arrangement), 512 (83) colors can
be displayed. When using an ROBW color filter
(the Quad arrangement), 4096 (84) colors can be
displayed.

CPU
Une synchronization signal, data sampling signal,
3 alternating signal

Controller
12

3
2
Frame synchronization signal,
line synchronization signal
HD61105
No.1
TFT-type color LCD panel
Triad arrangement
512 colors
640 x 480 pixels
HD61105
No.6

12

Figure 3 TFT-Type Multiple Color Display System

1094

HITACHI

HD66310T
Internal Operation
signal. At the CL2 falling edge, 12 bits of data,
which are for four outputs (3 bits for gray scales x
4 outputs), are input together. When the data input
corresponding to 160 outputs are completed, the
HD66310 automatically enters the stand-by mode,
and the EI02 signal changes to low.

8 Levei Output
0

The HD66310 internal circuit unit for one data output is shown in figure 4. The circuit receives 3-bit
data (DOj, Dlj, D2j) and selects one of eight voltage levels (V~V7) to output to the LCD.
The· transfer gates of the output circuit are produced by the CMOS structure. Therefore, any
voltage level between Vcc to VEE can be applied
to lines VO to V7.

The LCD driving output changes at the CLI rising
edge. The voltage level selected by data dl is output from pin Yl, and the level selected by dl60 is
output from YI60. See table 1 for the voltage
level selection by the input data.

The HD66310 has 160 of the above circuits.
When the SHL signal is at the Vee level, data
input is started by a low EI02 signal. When the
data input for 160 outputs are completed, the EIOI
signal changes to low. The voltage level selected
by data dl is output from pin YI60, and the level
selected by dl60 is output from Yl.

Operation Timing
The HD66310 operation timing is shown in figure

5.
When the SHL signal is at the GND level, data
input is started by a low EIOI (data input enable)

Yn

p. P-MOS
N: N-MOS

Vl
V3 V2

V7 V6

vo

V'" V4

I

~~~~~~,-J~~~ __~~~~~
~

f
CL1

~

Latch circuit (2)

f

f

f

Latch circuit (1 )

CL2

RVS

I

Voltage level selector

A

A

I

Display data

(DOi)

I

Display data
(Dli)

A

I

J

I

Display data
(D2j)

Figure 4 LCD Driving Circuit

HITACHI

1095

HD66310T

~

CL1

Jl.SLfl..nSL ___ Jl.SLfl..nSL

CL2

12345

3637383940

~

000

to
003
(Lower bit)

~

011

~

to

~

013

~

020
to

~

023
(Upper bit)

~

SHL=GNO
EI01 '

...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

EI02

Y1
to

Y160

--------------------------------~~
------------------------------------~

SHL=Vcc
EI02

'

...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

EI01

Y1
to

Y160

--------------------------------------------~~

--------------------------~
Figure 5 Basic Operation Timing Chart

1096

HITACHI

HD66310T
Cascade Connection

the next HD66310. Figure 6 shows a connection
example.

When the SHL signal is at the GND level, the
HD66310 begins to input data when the BIOI signal goes low. When the data input is completed,
the ElQ2 signal changes to low. By connecting the
ElQ2 pin of the first HD66310 to the BIOI pin of
the next HD66310, the low EIQ2 signal activates

When the SHL signal is at the Vee level, the EIQ2
pin of the fJI'St HD66310 is connected to GND, and
the EIOI pin is connected to the next HD66310
EI02pin.

DATA----~~._------------._------~----~----­

c~--------~~----------_r_.----------_+~~-----

SHL
Driver 1

SHL
Driver 2

EI01

EI01

EI02

Driver 3

EI01

EI02

EI01 ~'--____________

------...fl..I"lSlJ"l

C~

}
Driver 2
signals

EI02

A

Driver 2 input enabled

B

Figure 6 Chip Enable Operation (SHL = GND)

HITACHI

---

--------------------------------

1097

HD66310T
LCD Driving Power Supply Circuitry
Multiple-Level Driving Voltage Method
AC voltage must be applied to the LCD, since DC
voltage deteriomtes the LCD. To display eight
gmy scales, 16 voltage levels, shown in figure 7,
must be applied.
Although the HD66310 has eight LCD driving
voltage input levels, it can output 16 driving voltage levels using the level selector shown in figure
8, since the tmnsfer gates of the output circuit are
produced by the CMOS structure.
External Power Supply Circuitry
Figures 8 and 9 show the external power supply
circuit when displaying 512 colors in the Triad

armngement, and figure 10 shows the circuit for
displaying 64 colors in the Triad armngement
Table 3 shows the specifications of the LCD panel
and the HD66310 pins for each power supply circuit.
The circuit shown in figure 8 is the basic one used
when displaying 512 colors in the Triad armngement. However, the HD66310 can dispense with
the level selector, as shown in figure 9, using the
internal RVS (output reverse) pin. See table 1 for
detailed RVS functions.
When displaying 64 colors in the Triad armngement, the RVS pin functions as the alternating signal input pin, as shown in figure 10.

Vee
V1

V2
V3
V4
V5
V6

V7

va

V9
V10
V11

V12
V13
V14
V15
V16

-------------------------------------------- VEE

Figure 7 HD66310 Output Waveform
1098

HITACHI

HD66310T
Table 3 Color Display and Pin Specifications
Output
Level

8x2
(AC)

8x2
(AC)

4x2
(AC)

Display Data
Panel Spec.

DI2

DI1

Quad: 4096 colors
Triad: 512 colors

1/0

1/0

(upper bit)

Quad: 4096 colors
Triad: 512 colors

1/0
(upper bit)

Quad: 256 colors
Triad: 64 colors

DIO

RVSpln

Power Supply
(Refer to}

1/0

1

Fig. 8

Alternating
signal

Fig. 9

Alternating
signal

Fig. 10

(lower bit)

1/0

1/0
(lower bit)

1/0

1/0

(upper bit)

(lower bit)

1: Vee level voltage
0: GND level voltage

Alternating
signal

Vee

Vee

Level
selector

V1
V2
V3
V4
V5
V6
V7

V16
V15
V14
V13
V12
V11
V10

va, V9

V7
V6
V5
V4
V3
V2
V1
VO

lW§
I/O
I/O

110

Figure 8 ExternalPower Supply Example 1

HITACHI

1099

HD66310T
Alternating
signal-_-------------.

V7
V6
V5
V4
V3
V2
V1
VO

RVS
110

va
va

VEE

Figure 9 External Power Supply Example 2

Alternating
signal
Vee

Vee
V1
V2
V3
V4
V5
V6
V7

va

V7

V6
V5
V4
V3

V2
V1

RVS

Di2
Di1
DiO

vo

VEE\.~--

Figure 10 External Power Supply Example 3

1100

HITACHI

I/O
I/O

HD66310T
Design for Timing
11. However, the power supply lines immediately reverses polarity after a transition of the
RVS signal, as shown in figures 9 and 10.
Therefore, the HD66310 outputs invalid data
during the last CL 1 of a frame period.

When using the RVS pins to simplify the power
source, as shown in figures 9 and 10, it is recommended to add a vertical retrace period, (a scanning period in which no scan electrode is selected)
at the end of a frame scanning period, as shown in
figure 12, for the following two reasons.

In the power supply circuits shown ill figures 9
and 10, voltage temporarily becomes unstable
just after the RVS transition, causing the LCD
display to become jumbled.

As shown in figure 4, the data reverse circuit is
before the latch circuit (1). The LCD driving
output is reversed one CLl period after a
transition of the RVS signal, as shown in figure

CL1

-IlL--__---InL-____fL

(+---_

:x_____

RVS

_ x'----

LCD output

Figure 11

IlVS" and LCD Driving Signals Timing

_ - - - - - - - - O n e f r a m e period _ _ _ _ _ _ __

Frame synchronization signal

--fl

Line synchronization signal (ell)

~

Alternating signal

~-----------------------------

••

__ _

.' '.

-------~

~

~~~i~5ilectrodes

XI
X2
I
I

,:

{.J. ~~~
,

L...---~
--------~--~---

J480 ------~.--- ---~

HD66310T

Vl-VI60

Figure 12 Vertical Retrace Period

HITACHI

1101

~:!1

s

"g.

§':r

ag. ....

~OW
I

I

'"

r~

UI'"

t;:)!

51e.~
t""'"

()~

t1~

Frame synchronizalion s~naJ
line synchronization signal
Data fetch signal
Display data (even number)
Display data (odd number)
Alernating signal

J:

~
0

;

't:l

o _
!:g
r- o.
'I1

LCDpanei

Controller

Number of colors: 512
Color arrangement: Triad type
Display capacity: 480 x 640 dots
IC for scanning: HD61105

(r~

I»
a.

~'o

~~

-

" "'I»

[go
~

V5

'"g-

V4

U

V3

.--oGND
Ih'
(0 V)

~;;!

a.

g

a.

e.
el

(JQ

0

[

Vee 0 - NoI.. : 1. An operational aIIl>Iifier should be installed on each I_I of the power supply line (VO-V7) to lower the il'l'l'8danoe.
2. Condensers should be installed nesr the ICs to stabnize the power supply voltage.
Two O.I-~F condensers are recommended to be installed on one IC: one ~n Vco and GND. and one ~n Vee and VEE'
a This system uses 12 HD66310T chips and 12 HD61105 chips.

Figure 13 App6cation System Connection Example

> ==
~

~~

~

eo
~

~

"CI

;:;.

eI\
eI\

(M

~

~

X1
Scanning
electrodes
(HD61105)

X2

X3
__~____~______~______~______~

X~O

l:

~

i

iiiJ' - ._

HD66310T Y1-Y160

U

~,

~ One line period

~~

----------1-1-----______________

_n_ - - , . - -

A

~
----~========~\~

n

L!ne synchronization . ,
signal
..J I

,

L."_ __

........ .JlJ1JlIU1J1JL-

Data fetch signal

DOO

TITUTTI I I I I I I I 1 I I I I I

fl] frl I f - I [ I J

Display data
{ 001
12 bit

IIIIIIIIIIIIIIIIIIIII

IIIIIIII IIII

I I I I I I II I I I I I I I I I I I I I

III I I I II

023

S

I I JI

i
~

8

Figure 14 Timing Chart

=>
~

HD66310T
Absolute Maximum Ratings
Item

Symbol

Ratings

Unit

Note.

Power supply for
logic unit

Vee

-0.3 to +7.0

V

2

Power supply for
LCD driving unit

VEE

Vee -25 to Vee + 0.3

V

Input voltage (1)

Vn

-0.3 to Vee + 0.3

V

Input voltage (2)

VT2

VEE - 0.3 to Vee + 0.3

V

Operating temperature

Topr

-20 to +75 (H06631 OTOO)
-20 to +65 (H066310T0015)

°C

Storage temperature

TslO

-40 to +125

°C

2,3

Notes: 1. Exceeding the absolute maximum ratings could result in permanent damage to the LSI. The
recommended operating conditions are within the electrical characteristic limits listed on the
following pages. Exceeding these limits may cause malfunctions and affect reliability.
2. Values are in reference to GNO .. 0 V.
3. Applies to input pins SHL, CL 1, CL2, as, RVS, TEST, and 000-023. Also applies to input!
output pins EI01 and EI02 when these pins function as input pins.

1104

HITACHI

HD66310T
Electrical Characteristics
DC Characteristics
(Vee = +5V ±lO%, GND =0 V, V ee - VEE = 15 to 23 V, T. =-20 to +75°C in 12 MHz version)
(Vee = +5V±5%, GND =0 V, Vee - VEE = 15 to 23 V, T. =-20 to +6SOC in 15 MHz version)

TYP.

Hem

Symbol

Min.

Max.

Unit

LCD driving power
supply voltage

VCC-VEE

15

23

V

Test CondHlons

Not..

Input high· level
voltage (1)

V1H1

0.8 x VCC

VCC

V

2

Input low-level
voltage (1)

V1L1

0

0.2 x Vee V

2

Input high-level
voltage (2)

V1H2

0.75 x
Vee

Vee

V

3

Input low-level
voltage (2)

V1L2

0

0.25 x
Vee

V

3

Output high-level
voltage

VOH

Vee- 0.4

Output lOW-level
voltage

VOL

Input leakage
current (1)

III

Input leakage
current (2)

V

IOH =-0.4 rnA

4

0.4

V

lot. = 0.4 rnA

4

-5.0

+5.0

I1A

V1N = Vcc to GND

5

IL2

-10

+10

I1A

V1N - Vee to GND

6

Input leakage
current (3)

b

-100

+100

I1A

V1N .. Vee to VEE

7

LCD driver on
resistance

RON

2.5

kn

Vcc - VEE - 20 V

8

Current
consumption (1)

-I P1

25
30

rnA
rnA

Data fetch 12 MHz
Data fetch 15 MHz

9, 11

Current
consumption (2)

-lp2

2
2.5

rnA
rnA

Stand-by 12 MHz
Stand-by 15 MHz

9, 11

Current
consumption (3)

-1P3

3
3.7

rnA
rnA

12 MHz
15MHz

10, 11

Notes: 1.
2.
3.
4.
5.
6.
7.
8.

Voltage between Vcc and VEE.
Applies to CL1, CL2, SHl, Dij, RVS, TEST, and B5.
Applies to EI01. (input) and EI02 (input).
Applies to EI01 (output) and EI02 (output).
Applies to CL1, CL2, SHL, RVS, Dij, TEST, and BS.
Applies to EI01 (input) and EI02 (input).
Applies to VOL to V7L and VOR to V7R.
Applies to Y1 to Y160.
9. Current between Vee and GND under the conditions of V1H - Vee, V1L - 0 V, and no load on the
output pins.
10. Current between Vce and VEE under the conditions of V1H = Vee, VIL - 0 V, and no load on the
output pins.
11. fCL2 and fCLl are 15 MHz, 37.5 kHz respectively in 15 MHz version.

HITACHI

1105

HD66310T
AC Characteristics
(Vee = +5 V±10%, GND = 0 V, Ta = -20 to +75°C in 12 MHz version)
(Vee = +5 V ±5%, GND = 0 V, T a = -20 to +65°C in 15 MHz version)
Min.

tcvc

83 (66)

ns

Clock high·level
pulse width

tcwH

30 (23)

ns

Clock low-level
pulse width

tcwL

30 (23)

ns

Clock rise time

tR

Clock fall time

tF

Clock setup time

tsu

Clock hold time

Typ.

Max.

Unit

Symbol

Clock period

Item

Test Conditions

Notes

10 (10)

ns

2

10 (10)

ns

2

100 (100)

ns

2

tH

100 (100)

ns

2

Data setup time

tosu

20 (10)

ns

3

Data hold time

tOH

30 (25)

ns

3

Enable input
setup time

tEsU

20 (10)

ns

4

Enable output
delay time

tED

CL 1 high-level
pulse width

tWH

100(100)

ns

RVS setup time

tRsu

50 (50)

ns

6

tRH

50 (50)

ns

6

RVS hold time

53 (46)

Data in ( ) is the characteristics in 15 MHz version.
Notes: 1.
2.
3.
4.
5.
6.

1106

Applies to
Applies to
Applies to
Applies to
Applies to
Applies to

CL2.
CL1 and CL2.
Dij and CL2.
EI01, EI02, and CL2.
CL1.
RVS and CL2.

HITACHI

ns

See figure 16
for test load

4
5

HD66310T

Cl2

Dij

Cl1
Cl2
Enable output
Enable input

LCD output

Figure 15 Timing Chart

Chip enable
output

:-:l

30 PF:;:

Figure 16 Test Load

HITACHI

1107

HD66330T (TFT Driver)-(64- Level Gray Scale Driver
for TFT Liquid Crystal Display)
- Preliminary Description

Features

The HD66330T, a signal driver LSI, drives an
active ma1rix LCD panel having TFrs (thin fllm
transistor) in the picture element (pixel) area. The
LSI receives 6-bit digital display data per dot and
outputs corresponding gray scale voltage. This LSI
easily achieves multicoloring of a VGA-sized color
TFr LCD anlt is suitable for applications such as
multimedia.

• Multicolor display
The HD66330T receives 6-bit digital display
data per dot, and selects and outputs an LCD
drive voltage among 64-level gray scale voltages. When R, G, and B color fllters are added
to the LCD panel, a maximum of 260,000 colors
can be displayed.
• High-speed operation
Operating clock: 28 MHz maximum
Amount of input data: 3 dots x 6 bits (gray scale
data)
• Applicable systems
PC (640 x 480/400 dots) systems
• Internal I92-bit drive function
• Internal standby function
• Internal chip-enable signal generation circuit
• Supply voltage: 4.5 V to 5.5 V
• Bidirectional shift

Ordering Information
lYpe No.

Outer lead pitch (1Lf11)

Package

HD66330TAO

160

236-pinTCP

Note: The details of TCP pattern are shown in "The Information of TCP."

1108

HITACHI

HD66330T
Pin Arrangement

Note: This figure does not specify the tape carrier package dimensions.

1
2
3
4
5
6
7
8
9
10

V8L
V7L
V6L
V5L
V4L
V3L
V2L
V1L
VOL
000

11
12
13
14
15
16
17
18
19
20

001
002
003
004
005
EI01
CL4
CL2
CL1
Vee

21
22
23
24
25
26
27
28
29
30

SHL
GNO

EI02
010
011
012
013
014
015
020

HITACHI

31
32
33
34
35
36
37
38
39
40

021
022
023
024
025
VOR
V1R
V2R
V3R
V4R

41
42
43
44

V5R
V6R
V7R
V8R

1109

HD66330T
Internal Block Diagram

CL2

EI02~--~~---L~~+---J-------------------------~
~.---t.--r--~

Latch address selector

SHL - - - - - - ' - - - - - t - - '

02S-020
01S-010
005-000

••••••••

~Ianes

192-bit latch circuit 2

CL1

~~======~>
CL4

192-bit decoder

•••••••••••

vaL, V7L,
V6L, VSL,
V4L, V3L,
V2L, V1L,
VOL

V6R,

VSR,
V4R,

•••••••••••
Y1 Y2 Y3 Y4 YS

1110

VaR,
V7R,

HITACHI

V3R,
V2R,
Y192

V1R,
VOR

HD66330T
Block Functions
Clock Controller: Generates chip enable signals
(ElO2 and mol) and controls the internal timing
signals.

Decoder: Generates a decode signal per pixel for
the LCD drive voltage generation circuit using an
upper 3-bit decoder and a lower 3-bit decoder.

Latch Address Selector: Generates latch signals.
which sequentially trigger latch operation of input
display data.

LCD Drive Voltage Generation Circuit: Generates
LCD drive voltages from LCD drive power supply
voltages according to the decode signals generated
by the decoder.

Latch Circuit 1: Latches 3-pixel x 6-bit sequentially input display data; composed of 192 x 6 bits.
Latch Circuit 2: Latches 192 x 6-bit data latched
in latch circuit 1 synchronously with the CLl
signal.

HITACHI

'111

Functions

Supplies power to the LCD drive voltage generation circuit.
The same voltage must be applied to corresponding L- and
R-power pins within a range of Vee to GNO.
Inputs display data latch pulses for latch circuit 2. At the
rising edge of each CL1 pulse, latch circuit 2 latches display
data input from latch circuit 1 and outputs LCD drive
voltages corresponding to the latched data.
CL2

025-020,
015-010,
005-000
SHL

18

Input

Inputs display data latch pulses for latch circuit 1. At the
falling edge of each CL2 pulse, latch circuit 1 latches display
data input via 025-000 and outputs the latched data to latch
circuit 2.

Input

Inputs 6-bit (gray scale data) x 3-pixel display data.

Input

Selects the shift direction of the display data.

~ 025-020

GNO

025-020
015-010
005-000

~:
,,
,,,

~
Last

025-020 Y190
015-010 Y191
005-000 Y192

~

CL4

1112

Input

025-020
015-010
005-000

~,,,

,,

:

025-020 Y192
015-010 Y191
005-000 Yl90

,

~

Y1
Y2
Y3

is

,,

V

Vee

015-010
005-D00

025-020
Last-V 015-010
005-000

is

Y3
Y2
Y1

Controls the 2-phase function. A high level period of this
signal specifies the first phase period that performs high
output current operation, and a low level specifies the
second phase period that outputs the voltage corresponding
to the display daia.

HITACHI

HD66330T
Pin Functions (cont)
Signal Name

Y1-Y192

Numbers

110

2

Input/output Provides chip-enable signals. Input or output depends on
the SHL signal, as shown below. At anyone time. the signal
being used for input must go low to enable the LSI to latch
display data, and the signal being used for output will be
driven low after 192 pixels of display data have been read.

192

Output

Functions

SHL Level

EI01

EI02

GND

Input

Output

Vee

Output

Input

Outputs LCD drive voltages.

HITACHI

1113

HD66330T
System Overview
The following shows a block diagram of a TFf
color LCD system configured with multiple
HD66330Ts. The HD66330Ts latch 6-bit data per
dot, and selects and outputs one level among

64 internally generated LCD drive voltage levels.
When the pixels are structured using R, G, and B
color filters, a maximum of 260,000 colors can be
displayed.

SJlllem black diagram

nmlng chait 'example 01 the common· voltage AC·drlve method)
CL1

CL2

FLM

vo-va
VO
Common

electrode
(OVI5 V)

~

vo

va

va

I

Y1-Y192

54·leval gray scala

1114

HITACHI

VO

vo

vo

HD66330T
Timing Chart for Display Data
the panel and alternately connected to the panel
pins. In such a configuration, the ROB data and the
system dot clock (DCLK) should be divided
between the upper and lower drivers. Here, DCLK
should be divided into two by the controller.

The following figures show the display data timing
and hardware configuration for the TFT color LCD
system configured with HD66330Ts. Since color
panels usually have a narrow connection pitch with
driver LSIs, the HD66330Ts should be located
above (upper drivers) and below (lower drivers)

R5-RO,
Gs-<30,

18 (6 bilS x 3 pixels)

FLM
TFT color panel
260,000 colors,
640 x 480 dolS

Timing chart
OTMG

~f.o..t - - - - - - v a l i d display period------t...

OCLK

Upper driver display data

/"'.../

CL2U

R5-Ro (odd pixel) 025-020
Bs-<30 (odd pixel) 015-010
G5-BO (even pixel)_ 005-000

Lower driver display data

CL2L

/"'.../

Gs-<30 (odd pixel) _
025-020D-::t~,..~:,..l::!r..t:~;~'~~r':::~~'~
R5-RO (even pixel)_ 015-010
/"'.../
B5-BO (even pixel) _
005-000

,
I
I

I
,

I
I

,
I

I
I

HITACHI

I
I

I
I

Numbers in the figure indicate
pixels.

1115

HD66330T
Power Supply Circuit Example
The figures below show an example of a circuit
used to generate LCD drive power supply voltages
VO to V8. In this example, 18 levels of voltage are
generated by divided resistance to alternate the current for the LCD panel, and either positive or nega-

tive voltages are selected and supplied to the
HD66330T. To stabilize voltage, an operational
amplifier should be connected to each selector
output.

+5V
+5V

V8+N8-

V8

V7+N7-

V7
HD66330T

Selector

t--'--'---t--*--'

18 to 9 VO+No-

VO
Maximum ±10 mA direct current
(maximum ±5 mA for each of the L- and
R-pins) flows in the LCD drive power
supply voltage pins Vo to V8 of one
HD66330T. When 10 ICs are used, the
current amounts to ±100 mA maximum.
The direct current changes within 0 to
±100 mA depending on the display data.

+Vs

..

o to ±100 mA

..

-Vs
LCD drive power supply circuit example
(per one voltage level)

1116

HITACHI

The LCD drive power supply circuit must
be able to provide stable voltage despite
the change in the current input to the IC.
The following shows a circuit example:

HD66330T
Power Supply Voltage Examples
Voltage levels to be input to LCD drive power supply pins VO to V8 should be determined according
to panel specifications such as voltage intensity

Voltage (V)

characteristics. The table below lists voltage level
examples for reference:

VO

V1

V2

V3

V4

V5

V6

V7

V8

Counter Electrode

o

1.0

1.5

2.0

2.5

3.0

3.5

4.0

5.0

0

5.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0

5.0

HITACHI

1117

HD66330T
Relationship between Display Data and Output Voltage
The HD66330T outputs 64-level gray scale voltage
generated by 9 levels of LCD drive power supply
voltage and 6-bit digital data. The figure below

D'se'a:t Data
DIS 014 013 012011
0 0 0 0 0
0 0 0 0 0
I
0
0
0
0
0 0 0
I
0
0
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0

0
0
0

0

0
0

I
0

I
0

0
0
0
0

0
0
0
0
0
0
0
0

010

I
I
0
0
0
0

I

I

0
0

0

I
0

I

I

0
0

0

I
0

I

I

0
0

0

I
0

1
0
0

1

1

0
0
0
0

0
0

I
0
0

I
0
I
0
1
0
I
0
1
0
I
0

Outeut Voltas·
1st Phase 2nd Phase
VI
VO + 1/8)( 1Y,-VOI
VI
VO + 218)( lVI-VOl
VI
VO + 318)( lVI-VOl
VI
VO + 4/8)( lVI-VOl
VI
VO + 518 )( lVI-VOl
VI
VO + 6/8)( lVI-VOl
VI
VO + 7/8 )( lVI-VOl
VI
VI
V2
VI + 1/8)( IV2-Vl1
V2
VI + 218 )( IV2-Vl I
V2
VI + 318 )( IV2-Vl I
V2
VI + 418 )( IV2-Vl I
V2
VI + 518)( IV2-Vl1
V2
VI + 6/8 x IV2-Vl1
V2
VI + 7/8 )( IV2-Vl I
V2
V2
V3
V2 + 1/8 " IV3-V21
V3
V2 + 218 )( IV3-V21
V3
V2 + 318 " IV3-V21
V3
V2 + 418 )( IV3-V21
V3
V2 + 518 x IV3-V21
V3
V2 + 6/8 x IV3-V21
V3
V2 + 7/8 )( IV3-V21
V3
V3
V4
V3 + 1/8 x IV4-V31
V4
V3 + 218 x (V4-V31
V4
V3 + 318)( (V4-V31
V4
V3 + 418 x (V4-V31
V4
V3 + 518 )( (V4-V31
V4
V3 + 6/8 )( (V 4-V31
V4
V3 + 7/8 )( (V4-V31
V4
V4

shows the relationship among the input voltages
from the LCD drive power supply circuit, digital
codes, and output voltages.

D'se'a:t Data
DIS 014 013 012 011 010
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

0
0

0
0
0
0
0

0
0
0
0

I
I
0
0
0
0

0
0

0

I
0

I

I

0
0

0

I
0

I

I

0
0

0

I
0

I

I

0
0

0

I
0

I

I

I

0
0
0
0
0
0
0
0

0
0
0
0

0
0

I
0
0

I

I

0
0
0
0

0
0

0

1
0
1
0
1
0
0

I
0

I
0
0

I
0

I
0

Outeut Vohell!
1st Phase 2nd Ph •••
V5
V4 + 118)( IVs.-V41
V5
V4 + 218 )( IVs.-V41
VS
V4 + 318 )( IVs.-V41
VS
V4 + 418 )( IVs.-V41
V5
V4 + 518 )( IVs.-V41
V5
V4 + 6/8 )( IVs.-V41
V5
V4 + 7/8)( IVs.-V41
V5
VS
V6
V5 + 118)( IV6-V51
V6
V5 + 2/8 )( IV6-V51
VB
VS + 318 )( IV6-V51
VB
V5 + 418 )( IV6-V51
V6
V5 + 518 )( IV6-V51
V6
V5 + 6/8 " IV6-V51
V6
V5 + 7/8)( IV6-V51
V6
V6
V7
V6 + 118" IV7-V61
V7
V6 + 218 )( IV7-V61
V7
V6 + 318 " IV7-V61
V7
V6 + 418 x IV7-V61
V7
V6 + 518 " IV7-V61
V7
V6 + 6/8 x IV7-V61
V7
V6 + 718 " IV7-V61
V7
V7
V8
V7 + 1/8" IV6-V71
V8
V7 + 218 " IV6-V71
V8
V7 + 3/8 )( IV6-V71
V8
V7 + 418 )( (V6-V71
V8
V7 + 518 " IV6-V71
V8
V7 + 618 )( (V6-lm
V8
V7 + 718 )( IV6-V71
V8
V8

Note: 1st phase: The period in which 2-phase control signal CL4 is high and high output current operation is performed.
2nd phase: The period in which 2-phase control signal CL4 is low and low output current operation is performed (see p. 1199 for
details).

va
Power
supply
circuit

Y1

) H066330T

vo

~

Display data
(6-bit digital data)

1118

HITACHI

64 levels

HD66330T
Output Offset Voltage
The HD66330T has an internal DA converter per
output The upper three bits of 6-bit display data
select and apply the LCD drive power supply voltage level to the DA converter, and the lower three
bits select and output one analog voltage level.

that caused by concentrated current in a LSI due to
a particular display pattern.
The figure below shows the characteristics of output voltage with respect to LCD drive power supply voltages. Since output offset voltage Voff
depends on the difference between adjoining LCD
drive power supply voltages IVn - Vn + 11 (n = 0 to
7) output offset voltage will also decrease when the
power supply voltage difference IVn - Vn + 11 is
decreased.

Output offset voltage Vocc is defined as the difference between the actual output voltage and the
ideal output voltage expected from the LCD drive
power supply voltage and digital display data. The
Voff can be considered as the total output voltage
differences including the differences between LSIs,
between different output pins of the same LSI, and

LCD Drive Power Supply Voltage Examples

Voltage (V)

Vo
o

V1

V2

V3

V4

V5

V6

V7

va

1.0

1.5

2.0

2.5

3.0

3.5

4.0

5.0

(VO < Vl < ... < Va)
Ideal output voltage

!itA Output voltage dispersion range

va -------------------------------------------------------"~"~I --OJ voH = 60 mV
,

V7

....

V5
V4

III

::ft r

~~~~~~~~~~~~:~~~~~~~~~~;, ;;;:-:--~i
.

V3

l V5 -

I:

V4

i
'" (mV)
~

:

Jg

:,
,'

Voff = 60 mV

l ' r---f1

l

=0.5 V l

,,

V1 -.-------~ ---

mV

=

'
:
"

V2

Voff =60mV

...:

,lVa-V7 = 1,v
,

V6 ------------------------------------- -

~o

:

:

:

::

,

I~
MSB

;:;
0
0

,

;:

g

30

:

f~o~i~----~'---'--~--~--~-+---'~----4V,2
va
~1
, V3 V,4 1./.5 V6 V,7
,

LSB 8o~

60

~

~

;:;

;:;

;:;

;:

;:

;:

0

§

~

;:;
~

;:;

oL--";"-~'---

0.5

1.0

(V)

IVn-Vn+ 11

;:
;:

LCD drive power supply voltage

HITACHI

1119

HD66330T
LCD Drive Power Supply Voltage Examples

VoHage (V)

va

V7

V6

V5

V4

V3

V2

V1

Vo

o

1.0

1.5

2.0

2.5

3.0

3.5

4.0

5.0

(va < V7 < .•. < YO)
Ideal output voltage

til Output voltage dispersion range
VO """" """"""""""""."""""""""""""""""""""."""" """""""""""""

,
,
,,

"L

"~9" l!I..y"

VI

""""""""""""""""""".""""""""ypg. ':'

V2

""""""""""""""""""".""""""""""""""""

V3

""""""""""""""""""""""·t""""""~ ,~: ::YOff = ~O mV

V4

"""""""""""Voff",:"~QJrtY: ::

VS

,,
,

V7
:"

I

:

I

V7

'1,6

1

LSB

0

::

::
0

t::
::
I

I

::
::

::
I

:

I

I

I

,

I

I

I

I

I

I

I

I

I

I

:
:

1
1

I

I

I

I

::

, I

::
::

::

I

:

:

•

I

I

I

I

I

I/.S

V4

v.3

V2

V,l

,
,

::
0

I

,

0
0

,

::
00

8
0

LCD drive power supply voltage

1120

i:

•

I

'

~

r;v

:

:

0

~

:
:
:

I

'V~f = 60 mV

L"t'
:
:,
:
:
,

MSB

:

,V3 - V4 = O.S V:

::

.0,

V6

"L"

I

.~

:..

lve-vl =

HITACHI

:
:
:
I

I

:
:

:
I
,

iVO

§
0

8

o '--~0~.5::----:-1.'::-0--:(V~)
IVn-Vn + 11

HD66330T
2·Phase Operation
A high-speed low-power output switching function
is provided by dividing the horizontal period into
1st-and 2nd-phase periods. where high output current operation and low output current operation are
alternately performed.
During the 1st-phase period. the specified voltage
is applied to the LCD panel quickly with a low output impedance of about 215 kQ (high output
current operation). Here. the applied voltage is
selected by the upper three bits of display data
(see p. 1196).
During the 2nd-phase period. a voltage is applied

,,

i"
,,
:..

corresponding to the display data with an output
impedance of about 17 ill (low output current
operation).
In general. since it is not required to secure the 1st
phase in a 640 x 480-dot color panel (see the figure
below for assumed load condition). CL4 can be
fixed low.
This function is effective when the panel load is
large or when a horizontal period is short and gray
scale voltage must be applied quickly. For settings
in the 1st-phase period. see note 4 in Electrical
Characteristics.

Horizontal period
1st phase

2nd phase

L

CL4
Output resistance

Output resistance

2.Skn

17kn

r - - Assumed load condition - - - - - - .

Skn
LCD load:

~200PF

HITACHI

1121

HD66330T
Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Power supply voltage

Vee

-0.3 to +7.0

V

Input voltage (1)

Vt1

-0.3 to +Vee + 0.3

V

1,2

Input voltage (2)

Vt2

-0.3 to +Vee + 0.3

V

1,3,4

LCD power supply input current

II

±20

mA

5

Operating temperature

Topr

-20 to +75

·C

Storage temperature

TSI9

-40 to + 125

·C

Notes

If the LSI is used beyond the above maximum ratings, it may be permanently damaged. It should always be
used within its specified operating range for normal operation to prevent malfunction or degraded reliability.
Notes: 1. Assuming GND

= 0 V.

2. Applies to input pins CL 1, CL2, CL4, SHL, and Dij, and I/O pins EI01 and EI02 when used as
input.
3. Specifies voltage to be input to the LCD drive power supply pins.
Either of the following relationships must hold:

va ~ V7 ~ V6 ~ V5 ~ V4 ~ V3 ~ V2 ~ V1 ~ VO ~ GND or
~ V1 ~ V2 ~ V3 ~ V4 ~ V5 ~ V6 ~ V7 ~ va ~ GND
The following relationship must hold for VO to va potentials:
VleD ~
VleD ~ VO

4.

IVn - Vn + 11 :s; 2 V (n '" 0 to 7)
5. Specifies the maximum ratings for current in the LCD drive power supply input pins Vo to
(total current for both Land R pins).

1122

HITACHI

va

HD66330T
Electrical Characteristics
DC Characteristics (Vee - GND = 4.5 to 5.5 V, and Ta = 20 to 75°C, unless otherwise Doted)
Applicable
Pins

Item

Symbol

Input high-level
voltage

V1H

Input low-level
voltage

V1L

Output high-level
voltage

VOH

Output low-level
voltage

VOL

Input leakage
current (1)

lu

-5
CU. C12.
SHL. Dii. CL4

input leakage
current (2)

IL2

EI01 (I).
EI02(1)

LCD drive power
supply input
current

II

VOL-VaL.
VOR-VaR

Output offset
voltage

Voll

Y1-Y192

Difference
between
output pins

Driver output
ON resistance

Vref

Min

Typ

CL1. C12.
o.a x Vee
SHL. Dii. CL4.
EI01 (I).
0
EI02(1)
EI01(O).
EI02(O)

Y1-Y192

Max

Unit Test Conditions

Vee

V

Notes

0.2 x Vee V
V

IOH=-O.4 mA

0.4

V

101." 0.4 mA

+5

IlA

-10

+10

IlA

-10

+10

mA

Total of Land
Rpins
IVn - Vn + 11 .. 1 V
(n = 0 to 7)

60

mV

Vee - GND =5V
IVn - Vn + 11 .. 1 V
(n .. Oto 7)

30

mV

Vee -GND.5 V
IVn - Vn + 11 • 0.5 V
(n =0 to 7)

±30

mV

Vee-GND .5V
2
IVn - Vn + 11 .. 1 V
(n .. 0 to 7)

±15

mV

Vee-GND.5 V
IVn - Vn + 11 .. 0.5 V
(n =0 to 7)

Vee- 0.4

Ronl

Y1-Y192

2.5

kn

1st phase
Vee-GND -5 V

Ron2

Y1-Y192

17

kn

2nd phase
Vee-GND -5 V

Current
consumption (1)

IPl

Between
Vee and
GND

20

mA

Data latch
feL2 = 15 MHz.
fcu .. 33 kHz

Current
consumption (2)

Ip2

Between
Vec and
GND

4

mA

Standby
fCL2 = 15 MHz.
fell = 33 kHz

HITACHI

3

1123

HD66330T
Notes: 1. Output offset voltage Volt is defined as difference between the actual output voltage and output
voltage expected from the LCD drive power supply voltage and digital display data.
Volt shows the following characteristics with respect to voltage difference between adjoining LCD
drive power supply pins IVn - Vn + 11.
Q)

~
§2

(mV)

~

Q;

~

'5
a.
'5
0

(V)

(n

=0 to 7)

IVn - Vn + 11
2. Vref can be considered as the maximum total output voltage differences including the differences
between LSls, between output pins of the same LSI, and that caused by concentrated current in
an LSI due to a particular display pattern.
3. Except for the current flowing in VO to V8; outputs are unloaded.

1124

HITACHI

HD66330T
AC Characteristics (Vcc- GND

=4.5 to 5.5 V, and T. =-20 to +75°C, unless otherwJsenoted)
~

Max

Unit

28

MHz

Item

Symbol

Applicable Pin

Clock cycle time

f max

CL2

Clock high-level
width

TOII/h

CL2

10

ns

Clock high-level
width

Tc:wI

CL2

10

ns

Clock rise time

Tr

CL1, CL2

6

ns

Clock fall time

T,

CL1, CL2

6

ns

Clock setup time

Tau

CL1, CL2

50

ns

Clock hold time

Th

CL1, CL2

70

ns

Data setup time

Tdau

Dij,CL2

10

ns

Tdh

Dij,CL2

10

ns

7

Data hold time

Min

Enable setup time

Tesu

EI01, EI02, CL2

Enable output
delay time

Ted

EI01, EI02, CL2

CL1 high-level
width

Tcl1Wh

CL1

Driver output
delay time

Tdd

CL1, Y1-Y192

Test Condition

Nota.

ns
20

56

ns
ns

22

2,3,4

J1S

CL2

0.8 Vee

Dij

0.2 Vee

CL1

Last

First

CL2

Notes: 1. The figure below shows the load condition
for the enable output pins.
Enable output

....
-L

Enable output

o~--

~

30pF

Enable input

HITACHI

1125

HD66330T
2. Specified by the following load condition and timing.
load condition - - - - - - - - - - ,
load resistance

5kn

Y1-192

~ load capacnance

~200PF

(Cl4 is fixed at low level.)
Cl1

T

---;~------=::======:::!~SP'ecified output voltage -

Volt

Y1-192
- - -_ _ _ _ _ _ _~S:fpecified output voltage + Volt

3. Driver output delay time Tdd has the following characteristics with respect to the load condition.

load resistance 10 kn

40

load resistance 5 kn
Ii)

30

.,:,
."

~

20
10[
0

{Cl4 is fixed low.)
100

200

300

load capacitance (pF)
4. Driver output delay time Tdd has the following characteristics with respect to the Cl4 high-level
width.

20
Ii)

.,:,

~

10
load resistance 5 kn
load capacnance 200 pF

5
Cl4 high-level width (J,ls)
1126

HITACHI

LCD Module Line Up

HITACHI
-----------

1127

1128

HITACHI

LCD Module Line Up
Graphic Display LCD Module

eLM258XB

eLM213XB

eLM721XBNP

eLMG63900HGR

eLM246X
eLMG6471XTFC

eLM238XB

eLMG6400PLGR

eLMG5040XUFC
eLM215XB

eLM266XW

eLMG6151XUFE

eLMG6281XNGE

eLM300XM
eLMG9040ZZFC

HITACHI

1129

LCD Module Line Up
Character Display LCD Module
1-line Series

eH2570

eLM070L

eLM015

eLM020L

eLM568F

eLM027

eH2571

eLM038

eH2572

eLM058

2-line Series

"i..M107XML
eLM052L

eLM017L
eLM016L, LM016XML

eLM018L
eLM032L, LM032XML

1130

HITACHI

LCD Module Line Up
4-line Series

Segment-type LCD module

eLM041L

eLM044L

LED with backlight

eLM087LN

eLM088ALN

eLM091LN

eLM092LN

eLM093LN

HITACHI

1131

LCD Module Line Up
Graphic Display LCD Module (Reflection type)

...--.-

Type
~tYPe

On-1IIIp tYPe

wxhl......)

M_ _
wxhxtlnun)

-ERectIve

wXhlmm)

Dot_ Duty
wXhlmm) Cycle

LM258X8

-

.1

240x64

Color
Yellow-green

117x41

0.47xO.47 1/64

LM300XM

-

240x64

New gray

160x76xllmax.

132x39

0.63xO.63 1/32

-

*1

LM213X6

*1

266)(64

YeIIow-green

184)(75)(10max.

149.6)(43

0.66)(0.66 1/64

LMG6390QHGR

LMG63800HGR

.1

256)(64

New gray

160)(68)(9.5max. *4

126.3)(37

0.47)(0.47 1/64

LMG63920HFR

LMG63820HFR

*1

256)(84

Black Ik White

160)(68)(9.6max.$4

126.3)(37

0.47)(0.47 1/64

LM221XB

LM23BX8

*1

240)(128

Yellow-green

160)(120)(13.8max.

148)(76

0.55)(0.66 1/64

LMG6410PLGR

LMG6400PLGR

*1

240)(128

New gray

169.4)( 101 )(9.6max. *4

126)(71

0.60)(0.60 1/128

LMG6412PLFR

LMG8402PLFR

*1

240)(128

8lack Ik White

159.4)(101 )(9.5max.*4

126)(71

0.50)(0.50 1/128

*2

320><266

YeIIow-green

168>< 150)( 13.6max.

142)(116

0.43)(0.43 1/128

*1

460)(64

New gray

270)(82)(13max.

240)(38

0.49)(0.49 1/64

*1

480)(64

New gray

270)( 82)( 13max.

240)(38

0.49)(0.49 1/84

*1

480)(128

Yellow-green

270)( 110)(11.5max.

242)(69

0.48><0.48 1/84

*3

480><128

New gray

270>< 110>< 11.5max.

242><69

0.48><0.48 1/128

LM260X

-

LMG6270XNGR

-

LM246X
LM211X8
LM211XMC
LM216XB
LMG6250ULGR
LMG6252ULFR
LM266XW

LMG6272XNFR
LMG6273XNFR
LMG6280XNGR
LMG6282XNFR
LMG6283XNFR
LMG6111XTFR
LMG6160XUFR

-

149 x 67 x 13max.

*3

480><128

Black Ik White

270)( 110>< 11.6max.

242><89

0.48><0.48 1/128

*2

840><100

New gray

287.6)(71.6><11.6max.

243><42

0.36><0.36 1/100

*3

840><200

Yellow-graen

270>< 104)( 11 max.

236.4)(78

0.38><0.36 1/200

*3

640><200

New gray

266 >< 90>< 8max.

221.2)(73

0.33><0.33 1/200

•3

840><200

81ack IkWhite

265)(90)(8max .

221.2><73

0.33><0.33 1/200

*3

640><200

Black &. White
antI-glare

265>(90)(8max.

221.2><73

0.33xO.33 1/200

*3

840><200

New gray

270>< 116)( 8max.

217.2><96

0.33)(0.45 1/200

*3

840)(200

Black Ik White

270>< 116><8max.

217.2><96

0.33)(0.46 1/200

*3

840><200

stack&. White
antl-gla...

270>< 116><8max.

217.2><96

0.33xO.46 1/200

*3

840)(400

Black &. White
anti-glare

288>< 173><7.5max.

223.17x 143.97

0.33><0.33 1/200

*3

840><480

Black &. White
anti-glare

272>< 178><9max.

202.37xI62.77

0.31)(0.31

1/240

U64

Graphic Display LCD Module (with EL backlight)
LMG63910HGE

LMG63810HGE

*1

268><64

Newgrav

180>< S8 ><37

0.47)(0.47

LMG6411 PLGE

LMG8401 PLGE

*1

240x128

New gray

169.4><101 ><9.5max.*4

126><71

0.50><0.50 1/128

LMG6251 ULGE

-

*3

460><128

New gray

270>< 110>< 11.5max.

242><69

0.48)(0.48 1/128

LMG8271 XNGE

-

*3

840><200

New gray

266><90><9max.

221.2><73

0.33)(0.33 1/200

LMG6281XNGE

-.

.*3

640x2oo

New gray

270>< 116><9max .

217.2)(96

0.33><0.45 1/200

*3

640)(400

Blue
anti-glare

256)( 148 >< 9max.

197><126

0.30><0.30 1/200

*3

840)(400

Black 6. White
anti-glare

258)( 148 >< 9max.

197><125

0.30><0.30 1/200

*3

640)(480

Black &. White
anti-glare

272 >< 178><9max.

202.37><152

0.31 ><0.31

*3

640)(480

Black &. White
anti-glare

260>< 180>< 9max.

183><138.4

0.28><0.28 1/240

LMG6171XTBE
LMG6173XTFE
LMG6151XUFE
LMG6221 XUFE

-

1/240

Graphic Display LCD Module (with CFL baCklight)
LM721XBNP
LMG6160XTFC
LMG~71XT8C

LMG8471XTFC
LMG6040XUFC
LMG5060XUFC
LMG9050ZZFC
LMG904022FC

1132

-

-

*3

320)(200

Yellow

142>< 103 >< 30max.

113><77

0.33><0.35 1/200

*3

640)(400

Black&. White
anti-glare

325>< 191.8><28max.

238)(152

0.38><0.36 1/200

*3

840x400

antI-glare

250>< 145>< 10.8max.

196><124

0.30><0.30 1/200

250X 145><10.6max.

196)(124

0.30><0.30 1/200
0.28><0.28 1/242

Blue
Black &. White

*3

640)(400

sntt-gla,.

*3

640X480

anti-glare

256.6>< 160>< lOmax.

183)(137

*3

640)(480

Black&. White
.nti-glare

250>< 172 >< 10.5max.

196><150

0.30)(0.30 1/240

-

1024)(768

Black & White
anti-glare

300><234>< 17max.

231><175

0.22><0.22 1/387

-

1120)(780

Black &Whlta
anti-glere

316><230><31max.

236)(166

0.206)(0.206

Black &. White

HITACHI

1/390

_v. . .

(N<*)

VDD-VaS

~f

I&f"ss

LCD Module Line Up

--

o~

storage

T_ _

--

s~

Driver (on-chip)

Type

+5

-12

66

0-+40

-20-+60

120

2 Double

LC7940 /7941/7942

LM258XB

+5

-9

33

0-+40

-20-+60

150

2 Double

LC7940 /7941/7942

LM300XM

+5

-10.5

250

0-+40

-20-+60

150

2 Double

MSM5839/5238

LM213XB

+5

-13

90

0-+40

-20-+60

160

2 Double

LC7940/7941/7942

LMC'6390QHGR

+5

-13

90

0-+40

-20-+60

160

2 Double

LC7940/7941/7942

LMG6392QHFR

+5

-13.5

210

0-+40

-20-+60

220

2 Double

HD612oo/61203

LM238XB

+5

-15

90

0-+40

-20-+60

160

2 Double

LC7940/7942

LMG6410PLGR

CanoumptIon

T_

Weight

+5

-15

90

0-+40

-20-+60

160

2 Double

LC7940/7942

LMG6412PLFR

+5

-20

76

0-+40

-20-+60

265

2 Double

HD61104/61105

LM246X

+5

-10.5

130

0-+40

-20-+60

180

2 Double

MSM5839/5238

LM211XB

+5

-13

90

0-+40

-20-+60

210

2 Double

LC7940/7942

LM211XMC

+5

-13.5

100

0-+40

-20-+60

320.

2 Double

HD611oo/61103

LM2115XB

+5

-13

100

0-+40

-20-+60

320

2 Double

LC7940/7942

LMG6250ULGR

+5

-13

100

0-+40

-20-+60

320

2 Double

LC794O/7942

LMG6252ULFR

+5

-19

154

0-+50

-20-+60

200

2 Double

HD611 04/611 05

LM266XW

+5

-20.5

180

0-+40

-20-+60

290

2 Double

MSM5298/5299

LM280X

+5

-22

115

0-+40

-20-+60

230

2 Double

MSM5298/5299

LMG6270XNGR

+5

-22

115

0-+40

-20-+60

230

2 Double

MSM5298/5299

LMG6272XNFR

+5

-22

115

0-+40

-20-+60

230

2 Double

MSM5298/5299

LMG6273XNFR

+5

-22

115

0-+40

-20-+60

275

2 Double

MSM5298/5299

LMG6280XNGR

+5

-22

115

0-+40

-20-+60

275

2 Double

MSM5298/5299

·LMG6282XNFR

+5

-22

115

0-+40

-20-+60

275

2 Double

MSM5298/5299

LMG6283XNFR

+5

-20.5

200

0-+40

-20-+60

420

2 Double

MSM5298/5299

LMG6111 XTFR

+5

-21.5

200

0-+40

-20-+60

420

2 Double

MSM5298/5299

LMG6150XUFR

+5

-13

90

0-+40

-20-+60

190

2 Double

LC7940/7942

LMG6391QHGE

+5

-15

90

0-+40

-20-+60

200

2 Double

LC7940/7942

LMG6411 PLGE

+5

-13

100
1500*6

0-+40

-20-+60

380

2 Double

LC7940/7942

LMG6251 ULGE

+5

-22

116
1500*6

0-+40

-20-+60

280

2 Double

MSM5298/5299

LMG6271 XNGE

+5

-22

116

0-+40

-20-+60

340

2 Double

MSM 5298/5299

LMG6281XNGE

+5

-22

200

0-+40

-20-+60

360

2 Double

MSM5298/5299

LMG6171XTBE

+5

-22

360

0-+40

-20-+60

350

2 Double

MSM5298/5299

LMG6173XTFE

200

LMG6151XUFE

1000*5
1000*5

1500*6
2000*5
2000*5

+5

-22

+5

-22

+5

-21~.5

2000*6

400
2000*5

+5

-20.5

230
1000*6
360

+5

-22

360

+5

-22

+5

-22

400

+5

-20.5

360

+5

+34

+5

2000*6

360
2000*6
1800*6
2500*6

1700
6000*6

+38

1700

(+12)*7

Note: Contolier LSI

6000*6

6000

* 1: HD61830

0-+40

-20-+60

480

2 Double

MSM5298/5299

0-+40

-20-+60

450

2 Double

MSM5298/5299

LMG6221 XUFE

0-+40

-20<--+00

340

2 Double

MSMS298/5299

LM721X8NP

+10-+40

-20-+60

950

2 Double

MSM 5298/5299

LMG6160XTFC

+10-+40

-20-+60

400

2 Double

MSM5298/5299

LMG6371 XTBC

+10-+40

-20-+60

400

2 Double

MSM5298/5299

LMG6471 XTFC

+5--40

-10-+60

430

2 Double

MSM5298/5299

LMG5040XUFC

+10-+40

-20-+60

460

2 Double

MSM5298/5299

LMG5060XUFC

+5-+40

-10-+60

1100

2 Double

HD66107T

LMG9050ZZFC

+5-+40

-10-+60

1400

3 Double

HD66107T

LMG9040ZZFC

*2: HD63645F/64645F

• 5: EL power consumption

* 3: HD66841

*6: CFl power consumption

*4: External-type contoller maximum thickne.. is 9.0 mm .

*7: VFC-VSS

HITACHI

1133

LCD Module Line Up

-

Character Display LCD Module

-.......- -

a--

Type

.......

1~.xUneI

Cob

Module ....
wxhxtlmml

LM054

8xl

Gray

88X44x12max.

LM015

16xl

Gray

-.cIed
Voltage

wXhlmml

wXhlmml

Duty Cycle

61 x15.8

6.45X9.4

1/8

+5

80x36x12max.

64.5x13.8

3.15x5.5

1/8

+5

IIDD-Vas IV)

H2570

16xl

Gray

80x36x 12max.

64.5x13.8

3.15x7.9

1/11

+5

LM020L

18xl

·Gray

80x36x 12max.

64.5x13.8

3.07x5.73

1/16

+5

LM020XM8L

16xl

New gray

8Ox36x12max.

64.5x13.8

3.07X5.73

1/16

+5

LM070L

20Xl

Gray

105x39.0xllmax.

84.0x13.0

3.2x5.2

1/8

+5

LM038

20Xl

Gray

182x35.5x13max.

154.0X15.3

6.7x9.4

1/8

+5

LM027

24Xl

Gray

126x36x12max.

100x13.8

3.15x7.9

1/11

+5

H2571

32xl

Gray

174.5x33x 13.4max.

132.5X14

3.15x7.9

1/11

+5

H2572

40xl

Gray

182x35.5x13max.

154.0X15.3

3.15x7.9

1/11

+5

LM058

40xl

Gray

280 x 80 x 13max.

245x19

4.82x8.18

1/8

+5

LM052L

16x2

Gray

80x36xllmax.

64.5x13.8

2.95x3.8

1/16

+5

LM016L

16x2

Gray

84x44x 12max.

61 X15.8

2.96x4.86

1/16

+5

LM016XMBL

16x2

New gray

64x44x 12max.

61 X15.B

2.96x4.86

1/16

+5

LM032L

20x2

Gray

116x39x13max.

83x18.6

3.2x4.85

1/16

+6

LM032XMBL

20x2

New gray

116x37xl0.5max.

B3x18.6

3.2x4.86

1/16

+6

LM080L

24x2

Gray

116x39x13mox.

B3x18.6

2.7x4.85

1/16

+5

LM017L

32x2

Gray

174.5x33x 13.4max.

141.19x 16.75

3.45x4.85

1/16

+6

LM018L

40x2

Gray

182x35.5x13max.

154X 15.3

3.2x4.85

1/16

+5

LM018XMBL

4Ox2

Now gray

182x35.5x 13max.

154x15.5

3.2x4.85

1/16

+5

LM041L

16x4

Gray

87x60x 12max.

61.8x25.2

2.95x4.15

1/16

+5

LM044L

20X4

Gray

98x60x 12max.

76x25.2

2.95x4.15

1/16

+5

3.071<6.56

1/16

+5, (+5)
+5, (-)

Character Display LCD Module (with LCD backlight)
LM087LN

16xl

LM086ALN

16x2

LM093LN

16x2

LM091LN

20x2

LM092LN

4Ox2

Gray

90x36x14max.

64.5x13.8

Gray

90x36xl4max.

64.5x13.8

2.95x3.8

1/16

Gray

90x44x 13.8max.

61.0xI5.3

2.96x4.86

1/16

+6, (+5)

Gray

126x39x 14max.

83x 18.6

3.2x4.85

1/16

+5, (+5)

Gray

192x36.6x14max.

154x15.3

3.2x4.85

1/16

+5, (+5)

Note: Parentheses indicate VLEO.

Segment-Type LCD Module
87X27.5xllmax.

1134

HITACHI

LCD Module Line Up

Po_

1

__

8_ _

r ............

Weight

Controller (on-chlpl

Type

10

0-+50

-20-+70

35

HD44780

LM054

10

0-+50

-20-+70

25

HD44780

LM015

10

0-+50

-20-+70

25

HD44780

H2570

10

0-+50

-20-+70

25

HD44780

LM020L

10

0-+50

-20-+70

25

HD44780

LM020XMBL

10

0-+50

-20-+70

40

HD44780

LM070L

25

0-+50

-20-+70

65

HD44780

LM038

10

0-+50

-20-+70

40

HD44780

LM027

10

0-+50

-20-+70

60

HD44780

H2571

10

0-+50

-20-+70

65

HD44780

H2572

15

0-+50

-20-+70

150

HD44780

LM058

15

0-+50

-20-+70

25

HD44780

LM052L

15

0-+50

-20-+70

35

HD44780

LM016L

15

0-+40

-20-+60

35

HD44780

LM016XMBL

15

0-+50

-20-+70

50

HD44780

LM032L

15

0-+40

-20-+60

50

HD44780

LM032XMBL

15

0-+50

-20-+70

60

HD44780

LM060L

15

0-+50

-20-+70

60

HD44780

LM017L

15

0-+50

-20-+70

65

HD44780

LM018L

15

0-+50

-20-+70

65

HD44780

LM018XMBL

15

0-+50

-20-+70

60

HD44780

LM041L

HD44780

LM044L

Con8umptlon

~r

17.5

0-+50

-20-+70

65

155

0-+50

-20-+70

40

HD44780

LM087LN

150

0-+50

-20-+70

40

HD44780

LM086ALN

405

0-+50

-20-+70

50

HD44780

LM093LN

555

0-+50

-20-+70

70

HD44780

LM091LN

855

0-+50

-20-+70

100

HD44780

LM092LN

1 .05

1 0 -+ 50

1-

1 "PD7225G

20 -+ 70

HITACHI

1 LM039

1135

HITACHI®
. . HITACHI AMERICA, LTD.
Semiconductor & I.C.Division

Engineering Facility

Manufacturing Facility

San Francisco Center
2000 Sierra Point Parkway
Brisbane, CA 94005-1835
(415) 589-8300

Hitachi Micro Systems, Inc.
179 East Tasman Drive
San Jose, CA 95134

Hitachi Semiconductor (America) Inc.
6321 Longhorn Drive
Irving, TX 75063-2712

REGIONAL OFFICES - - - - - - - - Northeast Region
Northwest Region

DISTRICT OFFICES - - - - - - Florida
Texas

Hitachi America, Ltd.
77 South Bedford Street
Burlington, MA 01803
(617) 229-2150

Hitachi America, Ltd.
1740 Technology Drive
Suite 500
San Jose, CA 95110
(408) 451-9570

Hitachi America, Ltd.
4901 N.W. 17th Way
Suite 302
Fort Lauderdale, FL 33309
(305) 491-6154

Hitachi America, Ltd.
10777 Westheimer Drive
Suite 1040
Houston, TX 77042
(713) 974-0534

Mountain Pacific Region

Mid-Atlantic

Hitachi America, Ltd.
Metropoint
4600 S. Ulster Street
Suite 690
Denver, CO 80237
(303) 779-5535

Hitachi America, Ltd.
325 Columbia Turnpike
Suite 203
Florham Park, NJ 07932
(201) 514-2100

Hitachi America, Ltd.
9600 Great Hills Trail
Suite 150W
Austin, TX 78759
(512) 502-3033

Southeast Region
. Hitachi America, Ltd.
5511 Capital Center Drive
Suite 204
Raleigh, NC 27606
(919) 233-0800

North Central Region
Hitachi America, Ltd.
500 Park Boulevard
Suite 415
Itasca, IL 60143
(708) 773-4864

South Central Region
Hitachi America, Ltd.
Two Lincoln Centre
5420 LBJ Freeway
Dallas, TX 75240
(214) 991-4510

Southwest Region

Canada
Minnesota

IBM Region

Hitachi America, Ltd.
3800 W. 80th Street
Suite 1050
Bloomington, MN 55431
(612) 896-3444

Hitachi America, Ltd.
21 Old Main Street
Suite 104
Fishkill, NY 12524
(914) 897-3000

Automotive Region

Hitachi (Canadian) Ltd.
320 March Road
Suite 602
Kanata, OntariO,
Canada K2K2E3
(613) 591-1990

REPRESENTAT!VE OFFICES I!!!!!!l!!!!!!l!!!!!!gl!!!!!!l!!!!!!l!!!!!!

Hitachi America, Ltd.
290 Town Center Drive
Suite 311
Dearborn, MI48126
(313) 271-4410

Electri-Rep • Electronic Sales & Engineering • EIR, Inc.
M. Gottlieb AsSOCiates, Inc.• Jay Marketing Associates
Longman Sales, Inc.• Mycros Electronica • The Novus Group, Inc.
Parker-Webster Company • QuadRep Inc.• QuadRep/Crown, Inc.
QuadRep Southern, Inc.• Robert Electronic Sales
Strategic Sales, Inc. • Sumer Inc. • System Sales of Arizona
System Sales of New Mexico • Technology Sales, Inc.
TekRep, Inc.• Thompson & Associates, Inc .• West Associates
Was Tech Associates

Hitachi America, Ltd.
2030 Main Street
Suite 450
Irvine, CA 92714
(714) 553-8500

DISTRIBUTORS-----------

THIRD-PARTY ASIC DESIGN CENTERS-

Cronin Electronics, Inc. 0 ITT Multicomponents-Canada
Marsh Electronics, Inc. 0 Marshall Industries
Milgray Electronics, Inc. 0 Reptron Electronics
Sterling Electronics 0 Vantage Components Inc.
Western Micro Technology

Locus 0 Indiana Microelectronics Centero Digital
Equipment Corporation 0 Micral 0 Intronics

©1994 Hitachi America, Ltd.
Printed in U.SA

e

1136
Printed on recycled paper.

HITACHI

69417M/GI/MFM
Order Number: M24T026
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