1994_Integrated_Circuit_Systems_Data_Book 1994 Integrated Circuit Systems Data Book

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les Product Data Book

Ies reserves the right to make changes in the device data identified in this publication without further notice. IeS advises
its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer
is current and accurate.

Ies does

not assume any liability arising out of or associated with the application or use of any product or integrated circuit
or component described herein. Ies does not convey any license under its patent rights or the patent rights of others
described herein. In the absence of a written or prior stated agreement to the contrary, the terms and conditions stated on
the back of the IeS order acknowledgment obtain.

Ies makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.

Ies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into
the body, or other applications intended to support or sustain life, or for any nuclear facility application, or for any other
application in which the failure of the IeS product(s) could create a situation where personal injury or death may occur.
IeS will not knowingly sell its products for use in such applications, and the buyer shall indemnify and hold harmless IeS
and its officers, employees, subsidiaries, affiliates, representatives and distributors against all claims, costs, damages,
expenses, tort and attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Ies was negligent regarding the design or manufacture
of the part.

Copyright © 1993 Integrated Circuit Systems, Inc.

ii
--------------------

Introduction
Integrated Circuit Systems, Inc, designs, develops and markets standard and application
specific integrated circuits utilizing mixed analog/digital technology. Founded in 1976 to
provide custom IC designs and product sourcing services to OEMs, rcs created its own
sophisticated design tools, analog and digital cell libranes and quality assurance testing
methods. In 1988, these unique tools and mixed signal design capabilities enabled ICS to
create the first commercially viable video timing generator using ad vanced freq uency synthesis
technology. The ICS 1394 pioneered the transition from multiple crystal oscillators to a single
IC and emerged as the industry standard for producing the high frequency video dot timmg
function in IBM-compatible personal computers.
Integrated Circuit Systems merged with Avasem Corporation in November, 1992. Avasem
was founded in 1980 to provide custom MOS integrated circuits and became a market leader
in Phase Locked Loop (PLL) as well as mixed analog/digital integrated circuits. As individual
companies, ICS and Avasem competed for market share in frequency timing generators.
Today, as one company, ICS dominates the frequency synthesis market for CPU motherboards,
workstations and PC graphics.
lCS has extended its knowledge of frequency timing into new products for PC multimedia
sound and video. These include products that synchronize PC video images with live or
recorded television video, and products that create real, digitized sound. To expand the
capabilities of its PC sound/video design expertise, rcs formed the Multimedia Components
Division in July, 1993 and merged with Turtle Beach Systems, Inc., a provider of PC-based
hardware and software products for professional-quality sound generation and editing in
multimedia applications.
Additionally, ICS is meeting the increasing demand for controlled, rapid NiCd or NiMH
battery recharging for laptop and notebook computers with a family of power management
integrated circuits.
ICS controls every phase of manufacturing and quality assurance at both locations. Our
unique partnerships with international experts in wafer fabrication and assembly provide our
customers with the highest quality and performance in each integrated circuit chip. We
routinely produce both application specific integrated circuits (ASICs) and customized
versions of our standard masks.
We are confident that rcs can provide you with the optimum IC solutions, outstanding
customer service and dedication to quality to suit your needs.

Integrated Circuit Systems . .. Where the Digital World Meets the Real World.

iii

ICS: Committed to Quality and Reliability
At Integrated Circuit Systems, our goal is to produce and deliver products of exceptional quality and reliability.
To achieve that goal, we dedicate our efforts to meeting your technical expectations, your delivery deadlines and
your competitive pricing needs. We set our standards high. We take our commitment to you very seriously. At
ICS we consistently strive:

•

to maintain our world-class quality performance in the integrated circuit industry for both products and
services;

•

to establish a culture that focuses on continuous improvement and accepts the challenge for instituting
ever higher levels of quality and reliability;

•

to continue an effective total quality process that provides customers with products and services that meet
or exceed:
specification requirements
performance requirements
quality expectations
support needs before and after delivery;

•

to delegate the responsibility for quality to all ICS employees, with the emphasis on preventive actions.

In addition, we expect the same kind of quality and reliability from the wafer foundries and assembly sources we
select. We constantly monitor their performance to ensure continued conformance to our standards.
ICS' ongoing commitment to quality and reliability is a company-wide policy that originates with management. It
starts with your first phone call to ICS and is pursued through the design, production and delivery of your product.

Founder and Chairman, Edward Arnold,
in front of ICS Production Facility.

iv

_________________ Multimedia

SECTION

A

____________ Video Timing Generators

SECTION

B

____________________________ GENDACS™

SECTION

C

_______ Motherboard Video Timing Generators

SECTION

0

_____ High-Performance Video Timing Generators

SECTION

E

______________ Power Management

SECTION

F

_______________ Communications

SECTION

G

______________ General Information

SECTION

H

__________ Standard Package Information

SECTION

I

v

Contents
Page
Master Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

Multimedia Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
GSP500........... ...............................
9
GSP600 .......................................... 23
ICS2001 . ..... . . . . . ... .. . ... . . . .... .. . . ... . ... . .. 37
ICS2002 .. .. .. . ... .. . .. . . ... . .. . . .. . . .. .. . . ... ... 43
ICS2008 .... .. . . . . ... . .. . . .. . ..... . . . . . .... .. . . .. 61
ICS2008A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 79
ICS2101 ......................................... 81
ICS2102 ...................................
89
ChIp Set.. .. .. . ... .. . .. . . ... . .... . . . . . . .... ... . .. 91
ICS2115...................................... 93
ICS2116 ...................................... 94
ICS2122................................... ... 95
ICS2124-00L ICS2124-002...................... 95
Multimedia Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 97
GSP500 ApplIcations. . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 99
GSP600 ApplIcations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 131
Video Timing Generator Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 151
ICSI394 ......................................... 153
ICSI494 ......................................... 155
ICS2494/2494A ................................... 161
ICS2495 ........................................ , 167
ICS2496 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 173
ICS2595 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 179
ICS82C404 . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 189
ICS90C61A ..................................... , 193
ICS90C64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 203
ICS90C65 ........................................ 213
ICS9161 ......................................... 223
AV9194 .......................................... 237
Video Timing Generator Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 245
Video Timing Generator Standard Frequency Patterns. . . . . . . . . . . . .. 263
GENDAC,\I Products . .......................................... 273
ICS5300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 275
OC~~I

.........................................

~3

ICS5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 331

.........................................

3~

Motherboard Timing Generator Products . . . . . . . . . . . . . . . . . . . . . . . ..
ICS2407/ICS2409/ICS 1439 .......... . . . . . . . . . . . . . ..
ICS2492 . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . ..
ICS2694 .........................................
AV9107 ......................................... ,
ICS9108 ........................................ ,

367
369
375
381
387
395

OC~~I

GENDAC

IS

a trademark of Integrated CirCUit Systems, Inc

1

Contents (continued)
Page
AV9128/9 ........................................
ICS9131 .........................................
ICS9132 .........................................
ICS9133 .........................................
AV9140 ..........................................
AV9154 ..........................................
AV9154-06/60 ....................................
AV9155 ..........................................
ICS9158 .........................................

403
417
425
435
441
445
455
461
473

Special Purpose ICs (Disk Drive, Low Skew Pentium™) .............
ICSI694A ........................................
AV911O ..........................................
ICS9123 .........................................
AV9170 ..........................................
AV9172 ..........................................
AV9173 ..........................................
ICS9175 .........................................
ICS9176 .........................................
Special Purpose IC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

479
481
485
495
497
511
519
523
529
535

High-Performance Video Timing Generator Products. . . . . . . . . . . . . ..
ICS1522 .........................................
ICS1561 .........................................
ICSI561A ........................................
ICS 1562 .........................................
ICS 1567 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICSI572 .........................................
ICS2572 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

539
541
549
551
557
575
585
603

Power Management Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICS1700 .........................................
ICSI700A ........................................
ICS 1702 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICS 1705 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AV9304/9504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AV9312/9512 .....................................
Power Management Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

613
615
617
633
653
655
659
663

Communications Products ...................................... , 685
ICS1660 ......................................... 687
ICS ASIC Capabilities .......................................... 697
Quality and Reliability Information ............................... 703
Standard Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 709
ICS Sales Offices and Sales Representatives . . . . . . . . . . . . . . . . . . . . . .. 721
Pentium

IS

a trademark of Intel Corporation.

2

les Product Selection Guide
Multimedia Products
PRODUCT
APPLICATION

ICS
DEVICE TYPE

FEATURES

PACKAGE
TYPES

GSP500

VGAINTSC Genlock.

68PinPLCC

PAGE
9

GSP500 Application Notes
Video
Gmphics

99
VGAIPAL Genlock.

GSP600

68PinPLCC

23

GSP600 Application Notes

SoundlVideo
Synchronization

Sound

131

ICSI522

See High-Performance section.

ICS2008

SMPTE-MIDI Peripheral

ICS2008A

Improved SMPTE-MIDI Peripheral

ICS2001

Sound Output Circuit, Parallel Port.

16 Pin DIP,SOIC

37

ICS2002

Business Audio Codec

44PinPLCC

43

ICS2101

5 Channel Digitally
Controlled Audio Mixer.

28 Pin DIP,SOIC

ICS2102

Sound Blaster™Compatible Mixer.

28PinSOIC

89

ICS2115

WaveFront Synthesizer

84PinPLCC

93

I SET I ICS2116

541
44PinPLCC

61
79

81

WaveFront Interface

100 Pin QFP

94

ICS2122

2-Megabyte Gen-Midi Sound ROM

44PinSSOP

95

ICS2124-00I,
ICS2124-002

4-Megabyte General Midi
Sound ROM Set

44 Pin SSOP

95

CHIP

Sound Blaster IS a trademark of Creative Technologtes, Inc.

Video Timing Generator Products
PRODUCT
APPLICATION

P.C.Clock
Genemtors

Western Digital
Com patible Clock
Genemtors

MAX
FREQUENCY

CLOCK
OUTPUTS

External Loop Filter.
For New Designs Use ICS1494.

85 MHz

I TTL

20 Pin
DIP,SOIC

153

ICSI494

Buffered Xtal Out, Lock Detect Output.

135 MHz

I TTL

20 Pin
DIP,SOIC

ISS

ICS2494/
ICS2494A

Dual Video Memory Clock Generator
with 16 Preprogrammed Video and
4 Preprogrammed Memory Frequencies.

135 MHz

2 TTL

20 Pin
DIP,SOIC

161

ICS2495

Small Footprint, Narrow Body
SO Package.

135 MHz

2 TTL

16 Pin
DIP,SOIC

167

ICS2496

Low Voltage, 3/5 Volt Operation for
Laptop/Notebook Applications.
Power-down Mode.

851135 MHz

2 TTL

16 Pin
DIP,SOIC

173

ICS2595

Programmable Dual
ICS2494 Pin Compatible.

135 MHz

2 TTL

20 Pin
DIP,SOIC

179

ICS82C404

Dual Programmable Graphics Clock
Generator. ICD82C404 Compatible.

120 MHz

2 TTL

16 Pin
DIP,SOIC

189

ICS9161

Dual Programmable Graphics
Clock Generator. ICD2061 Compatible.

135 MHz

3 TTL

16 Pin
DIP,SOIC

223

AV9194

Dual Video Memory Clock Generator
with 16 Preprogrammed Video and
4 Preprogrammed Memory Frequencies.

135 MHz

2 TTL

20 Pin
DIP,SOIC

237

ICS9OC61A

Drop-in upgrade for the WD9OC6 1.
Integral Loop Filters.

80 MHz

2 TTL

20 Pin
DIP,SOIC
PLCC

193

ICS9OC64A

WD9OC31 VGA Controller Compatible.
Enhanced Version. Integral Loop Filter.
(Replaces ICS9OC63, ICS9OC64.)

135 MHz

2 TTL

20 Pin
DIP,SOIC
PLeC

203

Low Voltage, 3/5 Volt.Powerdown Mode.
WD9OC26 VGA Controller Compatible.

135 MHz

20 Pin
DIP,SOIC
PLCC

213

ICS
DEVICE TYPE

FEATURES

ICS1394

ICS9OC65

3

2 TTL

PACKAGE
TYPES
PAGE

GENDACTM Products
PRODUCT
APPLICATION
Personal Computer and
Engineering Work
Station Com puter
Graphics

ICS
DEVICE TYPE

FEATURES

PACKAGE
TYPES

PAGE

ICS5300

Integrated Dual Clock. 8-bit Generic.

44 Pin PLCC

275

ICS5301

Integrated Dual Clock. 8-bit Tseng Compatible.

44PinPLCC

303

ICS5340

Integrated Dual Clock. 16-bit Generic.

68 Pin PLCC

331

ICS5341

Integrated Dual Clock.l6-bit Tseng Compatible.

68 Pin PLCC

363

GENDAC is a trademark ofIntegrated Circuit Systems, Inc.

Motherboard Timing Generator Products
PRODUCT
APPLICATION

ICS
DEVICE TYPE

NUMBER NUMBER
OF
OF
OUTPUTS
PLL.

FEATURES

PACXAGE
TYPES

IMI407, IMI409 and IMI439
Compatible.

6
9
9

2
2
2

18PinDIP,SOIC
24 Pin DIP,SSOP
24PinDIP,SSOP

369

ICS2492

Buffered XTAL Out.
Tristate PLL Output •.

3

2

20 Pin
DIP,SOIC

375

ICS2494-244
ICS2494A-317

Buffered XTAL Out.
Note: See Video Dot Clock Section
for Data.

3

2

20 Pin
DIP,SOIC

161

9 Fixed, CPU-CPUI2 Selectable

11

2

24 Pin
DIP,SOIC

381

ICS2694

Provides CPU, Co-Processor, Hard

and Floppy Disk, Kbd, Ser. Port, Bu.
Clk Function.

Motherboard

PAGE

ICS2407
ICS2409
ICS2439

AV9107

CPU Clock Generator.

2

1

80rl4Pin
DIP,SOIC

387

ICS9108

3 Volt CPU Clock Generator.

2

1

80rl4Pin
DIP,SOIC

395

AV9128/9

Motherboard Frequency Generator
Outputs KBD Clock, System Clock,
I/O Clock, Comm. Clock and
CPU Clock.

8/11

4

16 or 20 Pin
DIP,SOIC

32 kHz Input Generates CPU Clocks.

3

ICS9132

ICS9131

403

2

16 Pin
SOIC,PDIP

417

32 kHz Input Generates all
Motherboard Clocks.

6

4

20 Pin
DIP,SOIC

425

ICS9133

32 kHz Input Generate. CPU Clock
and
System Clock and Two Fixed Clock•.

6

3

20 Pin
SOIC,PDIP

435

AV9140

R4000 Processor Series Ma.ter
Clock Generator.

1

1

8 Pin
DIP,SOIC

441

AV9154

Low Cost 16 Pin Clock Generator.
Generates CPU Clock,
Ke)board Clock,
System Clock and I/O Clock.

7

2

16 Pin
DIP,SOIC

445

Motherboard Clock Generator.
Produce. CPU Clock,
Ke)board Clock,
System Clock and I/O Clock.

8

20 Pin
DIP,SOIC

461

ICS9158

Clock Generator with Integrated
Buffers.

11

2

24 Pin
SOIC

473

ICS2496-4S6

3V Operation, Buffered XTAL Out.
Note: See Video Dot Clock Section
for Data.

3

2

20 Pin
DIP,SOIC

173

AV9154-06/60

Clock Generator Designed
Specifically for U so with
OPTI Chipset.

4

2

16 Pin
DIP,SOIC

455

AV9155

Laptop/Notebook

4

2

Special Purpose ICs (Disk Drive, Low Skew (Pentium™)
PRODUCT
APPLICATION

Motherboard

FEATURES

NUMBER
OF
OUTPUTS

NUMBER
OF
PLLs

ICSI694A

Single Crystal Generates Three Low-Htter Clocks.

3

AV9110

User-Programmable "On-the-Fly"; Low-litter makes it
Ideal for Disk Drive or Video Applications.

ICS9123

ICS
DEVICE TYPE

PACKAGE
TYPES

PAGE

I

8 Pin
DIP,SOIC

481

I

I

14 Pin
DIP,SOIC

485

High Resolution Clock Generator; One Channel has
Accuracy to within 50 PPM making it Ideal for
Modem, Ethernet and AD 1848 Applications.

6

3

16 or 20
Pin
DIP,SOIC

495

AV9170

Clock Synchronizer and Multiplier.

2

I

8 Pin
DIP,SOIC

497

AV9172

Low Skew Output Buffer. Low Skew and litter make
. it Ideal for Pentium Applications.

6

I

16 Pin
DIP,SOIC

511

AV9173

Lost Cost Video Genlock PLL.

2

I

8 Pin
DIP,SOIC

519

ICS9175

Low Skew Output Buffer Crystal Generates Six
Low Skew, Low-litter Clocks.

6

I

16 Pin
DIP,SOIC

523

ICS9176

Input Clock Generates 10 Low Skew, Low-litter
Outputs. Ideal for Pentium or PLI Applications.

11

I

28 Pin
PLCC

529

Pentium is a trademark ofIntel Corporation.

High-Performance Video Timing Generator Products
PRODUCT
APPLICATION

ICS
DEVICE TYPE

FEATURES

MAX
FREQUENCY

CLOCK
OUTPUTS

ICSI522

U set-Programmable Frequencies;

230 MHz

DiffECL

24 Pin
SOIC

541

180 MHz

DiffECL

20 Pin
DIP,SOIC

549

180 MHz

DiffECL

20 Pin
DIP,SOIC

551

230 MHz
[320+ MHz]
[Special Pin]

DiffECL

RAMDACnlReset Logic (Brooklree
Compatible).
ICSI567

32 FrequencyROM-based RAMDAC
Reset Logic (Brooklree Compatible).

180MHz

DiffECL

20 Pin
DIP,SOIC

575

ICSI572

User-Programmable Frequencies.
RAMDAC Reset Logic (Brooklree
Compatible) .

180 MHz

DiffECL

20 Pin
SOIC

585

User-Programmable Dual PLL
16V + 4M Locations.

185 MHz

20 Pin
DIP,SOIC

603

'Line Lock' Capability.
ICSI561

+ 2,4,8 TTL Out. Integral Loop Filter.

I NOTRECOMMENDEDFORNEWDESIGN I
ICS1561A

+ 2,4,8 TTL Out. Integral Loop Filter.
Replaces ICSI561.

WOrl.

ICSI660

FSK Signal Interface Device.

6

18 Pin DIP
2OPinSOIC

687

I
ICS

Multimedia
Products

At ICS, the digital world meets the real world with multimedia products for adding audio and motion
video to computer and consumer electronics products. We combine our experience in phase-lockedloop, digital signal processing, and mixed-signal design to product multimedia ICs for OEMs around
the world. Our solutions in audio and video are matched to OEM requirements for cost-effective products.

In video, ICS offers the GSP and 2008 product lines. The GSP family offers Genlocking to enable
full-motion, computer-generated text and graphics to be overlayed on any standard video signal, such
as TV, camcorder, VCR, or video disc. It also supports easy recording of the enhanced video image
onto videotape. The 2008 production line implements VITC and LTC read and write of the standard
SMPTE Time Code data, synchronized with MTC (midi time code) output.
In audio, ICS offers Wavedec™ and WaveFront. ™ Wavedec, our digital audio codec for computer
and consumer electronics products, records and plays 16 bit compatible files for applications running
in MS DOS or MS Windows platforms. WaveFront, our wavetable synthesizer, creates the audio
subsystem required for producing the full General MIDI patch set on next-generation, 16 bit sound
cards and consumer electronics products.
Most importantly, we understand the systems-integration challenges of adding multimedia capabilities to your products. Our applications engineering team includes engineers responsible for the
Multisound product from our Turtle Beach Systems division and for the Sensation™ multimedia
computer from Tandy. ICS views our multimedia IC business as a systems business and we can assist
you with your systems-integrations needs. We look forward to partnering with you and making you
and your new products succeed in the marketplace.

Wavedec and WaveFront are trademarks of Integrated C,rcu,t Systems. Inc

7

les Multimedia Product Selection Guide
Product
Applications

ICS
Device Type

Features

Package Types

GSPSOO

NTSC Genlock.

68 Pin PLCC

9

GSP600

PAL Genlock.

68 Pin PLCC

23

44PinPLCC

61

Video Graphics

SoundlVideo
Synchronization

Sound

ICHl
PI
SET

Page

ICS2008

SMPTE-MIDI Peripheral.

ICS2008A

Improved SMPTE-MIDI
Peripheral.

ICS2001

Sound Output Circuit,
Parallel Port.

16 Pin
DIP,SorC

37

ICS2002

Business Audio Codec.

44PinPLCC

43

ICS2101

S Channel Digitally
Controlled Audio Mixer.

28 Pin
DIP, SOIC

81

ICS2102

Sound Blaster Compatible
Mixer.

28 Pin
sorc

89

ICS2llS

Wavetable Synthesis.

84PinPLCC

93

79

ICS2116

Wavetable Interface.

100 Pin QFP

94

ICS2l22

2-Megabyte Gen-Midi
Sound ROM.

44 Pin SSOP

95

ICS2l24-001,
ICS2l24-002

4-Megabyte General Midi
Sound ROM Set.

44 Pin SSOP

95

ADVANCE INFORMATION documents contam 1OformatlOn on new products 10 the sampling or preproductIon phase of development CharacteristIc
data and other speClflcatlOns are subject to change WIthout notice.
PRODUCT PREVIEW documents contam mformatIon on products m the formatIve or desIgn phase of development CharactenstIc data and other
specIfIcatIons are desIgn goals. ICS reserves the nght to change or dlscontmue these products WIthout notIce.

8
------~.---

--

~-

-"~-----

---~----~-.

---~-----

--- -----

•

GSP500

Integrated
Circuit
Systems, Inc.

VGAlNTSC Video Genlock Processor with Overlay
Overview

Features

The GSPSOO allows the text and graphic images ofVGA and
Super VGA controllers to be displayed on standard NTSC
televisions or recorded on a VCR.
Additionally, the
GSPSOO accepts external video input from a camcorder or a
VCR and will synchronize (genlock) the VGA or Super
VGA controller to the external video. The GSPSOO also
allows VGA and video images to be overlaid on the same
television screen. The GSPSOO meets or exceeds all RS-170A
broadcast standards for timing accuracy and allows the
VGA controller to maintain true NTSC compatibility at all
times. The GSPSOO is compatible with virtually all VGA
controllers. Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR already have full BIOS support available for the GSPSOO.

•
•
•

•
•
•
•
•
•

PC B"B

Direct input of NTSC or S-Video (S-VHS and Hi-8
video).
On board NTSC/S-Video sync and black burst generation for local video operation. Video chroma burst separate with 3.579545 MHz and 14.31818 MHz phase
locked outputs.
Meets or exceeds alltiming specifications for studio and
broadcast television.
High efficiency NTSC/S-Video conversion that maintains VGA performance.
Dynamic overscan and underscan adjustment of
NTSC/S-Video modes under BIOS and/or software
control.
Software selection between all VGA and NTSC/SVideo modes.
NTSC/S-Video conversion support for all VGA and
Extended VGA modes with 480 or fewer lines.
Built-in dot clock circuitry to eliminate crystal oscillators for VGA, plus extended VGA operation up to 135
Mhz.
Low power consumption, ideal for laptop computers.

FIGEl

VlGIA
C(Q)i1J~I1"@~~®~

9

I

GSP500
Internal Block Diagram

VIDEO INPUT 1

I+---------------------------~ ~

VIDEO INPUT 2

ENCODER

LOGIC

GEN.OCK
TIMING

CONTROL
AND
CLOCK

PIXB.

SWITCH

REGULA110N

MODE
SELECT
LOGIC

VGA

8VNC

(O\IENASLE)

1).15
8VNC CKEY
OUTPUT INPUT

Theory of Operation
The GSP500 can be thought of as an extremely sophisticated
dot clock generator. In its simplest form, the GSP500 will
generate all of the dot clock frequencies necessary to drive
VGA and Super VGA controllers. The different frequencies are selected with the MODE SELECT LOGIC from the
VGA chip. Selection is similar to selecting frequencies on
any of the ICS dot clock generators (i.e., ICS1394, ICS1494,
ICS1561, ICS2494, etc.). Additionally, there are four reserved frequency addresses. These are labeled GL (genlock), OV (overlay), va (video only), and GO (graphics
only). Choosing any of these addresses will switch the
GSP500 from VGA mode to NTSC mode. Under NTSC
mode, the GSP500 accepts vertical and horizontal VGA
SYNC from the VGA controller and uses the sync to generate and adjust the VGA DOT CLOCK. The GSP500 will
automatically vary the frequency of the dot clock in order to
synchronize the VGA sync signals with an NTSC reference
signal. This reference signal can be derived from a video
device (such as a camcorder) connected to VIDEO INPUT
lor VIDEO INPUT 2. The GSP500 provides an RGB-toNTSC encoder with the VIDEO OUTPUT signal which is
either VIDEO INPUT 1, VIDEO INPUT 2, or an internally
generated black burst signal. All of the necessary ENCODER LOGIC signals to properly drive the encoder are
provided by the GSP500. During NTSC modes the GSP500
also creates the D-15 SYNC OUTPUT for the monitor con-

nection to allow for TV projection output of the VGA
images. The PIXEL SWITCH information derived from
external CKEYINPUT tells the encoder whether to display
the VGA image or external video for each pixel. Assuming
the images are genlocked, this creates the overlay effect.

Block definition
Video Input Switch
The Video Input Switch selects whether the GSP500 uses
VIDEO INPUT lor VIDEO INPUT 2 as the external video
source. It is controlled by an external pin of the GSP500.

NTSC Sync Separator
The GSP500 contains a high quality sync separator to allow
direct input of NTSC, S-VHS, or HI-8 video signals from
camcorders, VCRs, and other video products. The GSP500
utilizes a differential video input circuitry for maximum
noise immunity. It also employs digital noise filtering and
enhanced digital signal tracking technology to ensure maximum compatibility with consumer, industrial, and broadcast
video signals. Although low cost video sync separator products are commonly available, they are primarily designed for
television and video monitor use. The simple diode clamping
circuit used in these devices does not have the accuracy or
noise immunity required for genlocking.

10

GSPSOO
Sync Correction

RS-170A Sync and Black Burst Generator
RS170A Sync Generator

The Sync Correction circuitry looks for missing sync pulses,
block sync, single field video, and phase shift errors caused
by the head switching zone of a VCR. It assures proper
genlock during all of these problems common in consumer
video products.

The studio quality bUilt-in video sync generator allows the
GSPSOO to operate without an external video input and still
maintain broadcast video timing. This assures NTSC compatibility at all times. When external video is present. the
sync generator works in conjunction with the sync separator
to isolate sync from noisy video signals.

Genlock Timing Control and Clock Regulation
The GSPSOO looks at the input sync from the VGA controller and determines how to alter the dot clock to create
RS-170A timing. Both the frequency and the method can
change with different VGA modes. The GSPSOO enables
virtually any VG A controller capable of interlacing to create
RS-170A timing. The GSPSOO's unique architecture provides ultra-high efficiency and flexibility and allows the frequency of the dot clock to be controlled totally under BIOS
or software control. Screen attributes such as horizontal
width and position can be individually programmed for each
mode while maintaining genlock integrity. This circuit will
modify the timing of virtually any mode, with 480 or fewer
lines, to meet RS-170A NTSC specifications. The GSPSOO
genlock timing control and clock regulation design is awaiting patent approval.

Black Burst Generation
Most RG B-to-NTSC encoders synchronize a crystal oscillator to the chroma burst signal of the external video signal.
This provides the color reference portIOn of the video signal.
If an external video signal is not available, the crystal oscillator will free run, creating screen artifacts such as 45 degree
moving lines in constant color portions of the screen. To
eliminate this problem, the GSPSOO generates a black burst
video signal. Black burst video is an analog signal containing
both sync and a correctly phased chroma burst signal. This
ensures proper color reference generation at all times. The
GSPSOO provides black burst output to the encoder when
external video is either missing or not selected (non-genlock
mode).

INT/EXT Video Switch

Precision Dot Clock Generator

The Internal/External Video Switch determines whether the
encoder uses external video or the black burst signal. If
external video is chosen, the GSPSOO will simply pass the
external video signal through to the encoder, unaffected.
Black burst is used when external video is not present. The
switch is controlled by the Video Signal Processing and Sync
Correction circuitry.

The GSPSOO uses the same state-of-the-art dot clock technologythat has made ICS the premier suppber ofVGA dot
clock generators. ICS offers the highest accuracy and lowest
jitter products available.

CKEY
The ckey (or color-key) circuitry creates the pixel switch for
the encoder. This signal determines whether the VGA image or external video is displayed for each pixel. Ckey is
modified by the GSPSOOto ensure that the pixel switch signal
IS delayed (to make up for delays in the RAMDAC) and that
it has proper levels during sync and blanking. If the VGA
and external signals are genlocked, this pixel switch will
create an overlay effect.

Video Signal Processing and Correction
Video Signal Processing
The Video Signal Processing circuitry of the GSPSOO measures the incoming video signal for basic timmg accuracy and
signal noise. It contains intelligent circuitry to remove extraneous portions of the video signal that would normally be
incorrectly categorized as sync. This is extremely important
when using a VCR as a video input. If there is an interruption of the external video signal, this cirCUit Will automatically switch inputs from the external video signal to the
internal sync generator. When the external video signal
resumes, the circuit will automatically switch back to the
external video. The Video Signal Processing accepts the
MODE SELECT LOGIC from the VGA chip. This logic
chooses either VGA or NTSC operation and selects
whether genlock to external video is to be enabled.

11

I

II

GSP500
PIN
NUMBER

DESCRIPTION
VERTICAL LOCK ENABLE. HIGH for VGA controllers.
LOW disables vertical lock feature. may be useful for Non-VGA Operation.
ODD/EVEN
ODD/EVEN FIELD IDENTIFICATION. HIGH indicates odd numbered
field, LOW indicates even numbered field.
BP
BACK PORCH PULSE. Negative polarity TTL level signal used by some
RGB-to-NTSC encoders.
DATAIN
Data input for inserting SMPTE time code in video signal.
CB
COMPOSITE BLANKING OUTPUT. Indicates non-screen data portions
of NTSC signal.
CS
COMPOSITE SYNC. NTSC Composite sync output for RGB-to-NTSC
encoders. Gated offduringVGA modes.
CKEY
COLOR KEY. Resultant input from the 8-bit compare of digital RGB
(PO-P7) and a software selectable byte. This color key determines which pixels
displayVGA and which display external video in overlay mode. See Hardware
Interface Manual for more details.
TEST
For ICS use only.
VSYNCOUT
VERTICAL SYNC OUTPUT. Vsync output for DB-IS connector.
DATAFRAME TTL level framing signal active during lines 10-20. For use in time code
applications.
OVENABLE
OVERLA Y ENABLE. Fast pixel rate switch. HIGH displays NTSC output,
LOW displayRGB output. Used for overiayencoders. See Application
Notes for wiring details.
I/ES
INT.lEXT. SYNC. Determines sync selection in OVENABLE signal.
Tie LOW normally.
LOC/REM
LOCAL/REMOTE. A LOW output state signifies REMOTE status indicating
that external video is present and a genlock mode has been selected. If external
video goes away or a non-genlock mode is selected, LOCAL/REMOTE will
go HIGH.
BRSTACT
For ICS use only.
FRTSTOUT
For rcs use only, wire to pin 37.
HORIZONTAL SYNC. For some RGB-to-NTSC encoders.
HS
Gated off during VG A modes.
HRSTOUT
For ICS use only.
HORIZONT AL SYNC OUTPUT. Hsync output for DB-IS connector.
HSYNCOUT
VSS
Digital ground. We strongly recommend the use of a multilayer board and a
ground plane.
S Volt digital power. We strongly recommend the use ofa multilayer board
VDD
and a power plane.
VDD
S Volt digital power. We strongly recommend the use ofa multilayer board
and a power plane.
Digital ground. We strongly recommend the use of a multilayer board and a
VSS
ground plane.
Frequency Select S. Selects between multiple VG A Dot Clock frequencies,
FSS
Genlock modes and NTSC frequencies. See Dot Clock Generation and
NTSC Mode Selection sections for a more detailed description.
Also see Application Notes for wiring diagrams and BIOS Interface Manual
for details.
VLE

2
3
4
S
6
7

8
9
IO
II

12
13

14
15
16
17
18
19

20
21
22

23

12

GSPSOO
PIN
NUMBER

DESCRIPTION

NAME

24

FS4

25

FS3

26

FS2

27

FSI

28

FSO

29
30
31

EXTSYNC
VCRI
CLAMPLEV

32

Y2

33

Yl

34
35
36

C2
Cl
3.58SC

37
38

FRSTIN
AVDD

39
40

GFF
VCOLF

41
42

SYNCTHRS
VGAO/E

43
44

COUT
RST

45

YOUT

46
47

HAUGNOUT
SYSLF

48

XTALI

49

XTALO

Frequency Select 4. Selects between VGA Dot Clock frequencies and
NTSC modes.
Frequency Select 3. Selects between VGA Dol Clock frequencies and
NTSC modes.
Frequency Select 2. Selection between VG A Dot Clock frequencies and
NTSC modes.
Frequency Select I. Selects betweenVGA Dot Clock frequencles and
NTSC modes.
Frequency Select O. Selects between VG A Dot Clock frequencies and
NTSC modes.
For ICS use only.
HIGH permits using VCRs as an input.
Clamping level adjustment for video mput. See Application Notes for
more details.
NTSC video input number 2. Note: This is also the Y (luminance) input for
S-Video systems.
NTSC video input number I. Note: This is also the Y (luminance) input for
S-Video systems.
C (Chrominance) input number 2 for S-Video systems.
C (Chrominance) input number I for S-Video systems.
3.579545 MHz SUBCARRIER OUTPUT. Phase-locked to the chroma burst
signal to allow encoders to maintain proper SCH phasmg.
For ICS use only, wire to pin 15.
5 Volt analog power. We strongly recommend the use of a multilayer board
and a power plane.
Inverts field 1 and field 2 of VGA sync. Normally tied HIGH.
VCO LOOP FILTER CIRCUIT. External RC circuit used in VCO circuitry.
See Application Notes for component values.
Sync threshold adjustment for video input. See Application Notes.
VGA ODD/EVEN FIELD IDENTIFICATION. HIGH indicates odd
numbered field, LOW indlcates even numbered field.
C (Chrominance) OUTPUT. C output for S-Video systems.
Chip reset pulse. This to be tied high through a resistor.
Do not tie to the computer reset line.
Y (Luminance) OUTPUT. NTSC video output when the NTSC/SVID
input is in the HIGH state. Y output for S-Video systems when the
NTSC/SVID input is in the LOW state.
For rcs use only, wire to pin 62.
SYSTEM CLOCK LOOP FILTER CIRCUIT. External RC circuit used in
the chroma burst phase locking circuit. See Application Notes for
component values.
14.31818 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.
14.31818 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.

13

I

II

GSP500
PIN
NUMBER

NAME

50

AVSS

51
52
53
54
55
56
57

VID1I2
VCOOUT
FILTSEL
DOTCLOCK
VFF
VCR2
VGA/NTSC

58

BG

59
60

LOC/REM IN
VGAHSYNC

61

VGAVSYNC

62
63

HALIGNIN
NTSC/SVID

64

VS

65

4XSC

66
67

PCLK
DATAOUT

68

SCH

DESCRIPTION
Analog ground. We strongly recommend the use of a multilayer board and a
ground plane.
Input selector. High for YIIC1, Low for Y2/C2.
For ICS use only, do not wire.
For ICS use only, wire to pin 57.
Clock signal input for VGA chip.
Inverts field 1 and field 2 ofNTSC sync. Normally tied HIGH.
LOW modifies sync characteristics to permit operation with VCR input.
Mode identification output signal. HIGH indicates a VGA mode, LOW
indicates an NTSC mode.
BURST GATE PULSE. Negative polarity TTL level signal used by
RGB-to-NTSC encoders.
For ICS use only, wire to pin 13.
VGA HORIZONTAL SYNC. HSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
VGA VERTICAL SYNC. VSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
For ICS use only, wire to pin 46.
NTSC/S-VIDEO. Selects between NTSC and S-Video output. HIGH= NTSC;
Low= S-Video.
VERTICAL SYNC. NTSC Vsync output for RGB-to-NTSC encoders.
Gated off during VGA modes.
4 TIMES SUBCARRIER OUTPUT. 14.31818 MHz signal phase-locked to
the chroma burst signal.
PCLK from VGA chip.
TTL level output. This reads data during lines 10-20 and outputs it as a
digital signal. For use in time code applications.
SCH PULSE. Positive polarity TTL level signal to distinguish between
fields 1 and 3 or 2 and 4. Not necessary for most encoders.

14

GSPSOO
BIOS Programming Example
BIOS support is currently available from Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR. Other VGA
manufacturers have support programs underway. If you use one of these VGA controllers that have completed BIOS
support, you can ignore this section. The following information may be helpful to VGA manufacturers and software
developers. These tables represent register settings one particular VGA controller. Others are listed in the BIOS Interface
Manual. This particular controller does not interlace text modes and uses an 8 x 8 font for modes 0, 1,2,3, and 7. The
horizontal registers are adjusted to produce underscan for text modes and overscan for graphics modes.

Horizontal CRTC Registers
CRTC
REGISTER

Modes:
00,01,04, OS, OD

Modes:
02, 03, 06, 07, OE, OF, 10

00

HT

35

6B

66

01

HDE

27

4F

4F

CRTC
INDEX

Modes:
11, 12, 13

02

SHB

2A

53

52

03

EHB

96

8B

87

04

SHR

30

5B

58

05

EHR

92

83

80

CRTC
REGISTER

200 Line Modes:
(N on-Interlaced)
00,01,02,03,07,04,
05,06, OD, OE, 13

350 Line Modes:
(Interlaced)
OF, 10

480 Line Modes:
(Interlaced)
12, 13
05

~-

Vertical CRTC Registers
CRTC
INDEX

06

VT

05

05

07

OVERFLOW

11

11

11

10

VRS

EO

D3

F4

11

VRE

84

87

88

12

VDE

C7

AE

EF

IS

SVB

DC

CF

FO

16

EVB

F2

E5

06

-_.-

Note: The MSB of the MSL register (INDEX 09) must be turned OFF in 200 line NTSC modes. When using an 8 x 8 font
for text (modes 00, 01, 02, 03, 07) the 4 LSB of this register will change from F to 7.

Miscellaneous Output Register
NTSC mode
- _..

1----

-

f-

Color Modes:
00,01,02,03,04,05,06,
_ _ OD, OE, 10,11, 12, 13

Monochrome Modes:
07, OF

Genlock (GL)

23

Overlay (OV)

27

26

Video Only (VO)

2B

2A

Graphics Only (GO)

2F

2E

Extended Registers
Turn OFF all DOTCLOCKl2 bits.

15

22

l

GSP500
NTSC vs. VGA Horizontal Timing
I r
E

L

"

___

Safe Act"n Area

Safe Tltle Area-------;i

pl~------1~f------1------'

I .. . .

Q10.9uS

63.556uS

II

II

II

II

1J-"L---------~U,--LL------------'..J

r----

'"orlZOntal OlSplay End

~l P

j

81anklng

-,----Horlzontal T o t a l - - - - - - 1

NTSC Vs. VGA Vertical Timing (200 line mode)
241

242

243

244

VGA Hsync
VGAVsync _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

~------

Nfl'SC sync
Z31

VGA

232

233

234

235

236

Hsync

VGA Vsync _ _ _--"

260

VGA

261

262

263

Hsync

VGAVsync _ _ _ _ _ _ _ _ _ _ _ _ _ _~I---------------

16

GSP500
Electrical Specifications
Operating temperature range o°c to 70°C

Electrical Characteristics

r

SYMBOL

I

PARAMETER

I
AVOOt-Analog Supply
\~ Dvoo
Digital Supplv
LIDO (VG A) I
Operating Current - VG A Mode

MIN
4.5
4.5
I

~(NTS<::LL~erating Current - NTSC Mode

TYP

MAX

5.0
5.0

5.5
5.5

UNITS
Volts

35

Volts
rnA

50

rnA

Input Signals
SIGNAL TITLE

PIN #

TYPICAL VALUE
I Vp_p

OPERATING CONDITIONS

33
35

IVp_p

75 Ohm load

32

IVp_p

75 Ohm load

Ir - - ~2-------t

34

IVp_p

VID 112

51

f-- _____ yl

CI
Y2

,

75 Ohm load

75 Ohm load

-------------G
______NTSC/SVID. _ _ _ ,__~L+

TTL/CMOS . _
TTL/CMOS

High = NTSC; Low = S-Video

r-----. .-----YGA VSYNC___
VGAHSYNC

TTL/CMOS

Positive IJolarity

,

61'
60

FSO-5
CKEY
PCLK
IJES

28-23
7
1-66
I

High = YI,CI;Low= Y2,C2

TTL/CMOS

Positive polarity

TTL/CMOS

Address/mode select

TTL/CMOS

High= RGB;Low= NTSC

TTL/CMOS

Pixel (DAC) Clock from VGA

12

TTL/CMOS

High = Internal sync
Low = External sync
Active during DATAFRAME

I

DATAIN

4

TTL/CMOS

CLAMPLEV

31

1-1.5 V

SYNCTHRS

41

CLAMPLEV + 0.1 V

VLE

I

TTL/CMOS

Tie to Voo through resistor

RST/

44

TTL/CMOS

Tie to Voo through resistor

17

I

GSPSOO
Output Signals
SIGNAL TITLE
VSYNCOUT
HSYNCOUT
VS
c------HS
CS
DOTCLOCK
YOUT
COUT
3.58SC
4XSC
LOC/REM
OVENABLE
!--------VGA/NTSC
CB
ODD/EVEN
VGAO/E

1-----

Ir-

c---------

---

BG/
FP/
SCH
DATAFRAME
DATAOUT

PIN#

TYPICAL VALUE

9
18
64
16

TTL
TTL
IVp_p
IVp_p
IVp_p

6
54
45
43
36
65
13

-

lVp-p
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

I
,

57
25
2
42
58
3
68
10
67

i

TTL
IVp_p

11

I

OPERATING CONDITIONS
Positive polarity during NTSC modes
Composite sync during NTSC modes

1--

,

!

I

TTL
TTL
TTL
TTL

Positive polarity
Positive polarity
Positive polarity
75 Ohm load
75 Ohm load
3.579545 MHz
14.31818 MHz
High = local; Low = re~
High = NTSC; Low = RGB
High= VGA;Low= NTSC
Positive polarity
High = odd field; Low = even field
High = VGA odd field
Low = VGA even field
Negative polarity
Negative polarity
Positive polarity
Lines 10-20
Active duringDATAFRAME

TTL

18

I
I

~i

jI

~

--1

I

,

I

GSPSOO
Dot Clock Selection
The following charts represent two of the many dot clock frequency selection tables supported by GSPSOO. See the BIOS
manual or contact ICS applications engineering for additional information.

IQUENCY (MHz)
50.350
56.644
65.028

FS5

FS4FS3 FS2

FSI

FSO

.. r----. O

I

0

0

0

1

0

1

0

I

I

0

0

I

1

I

72.000
t---.
I
I

I

1

0

0

0

80.000

1

0

0

1

75.000
89.800

1

110.000

I

GenLock

I

OVerlay

I

t---~eo

Only.
GraphIcs
Only
..

I

FREQUENCY (MHz)

I

0
0

,
I

I

1

I

I
I

I

rl

FS3

1

i

i

I

0

0

0
1

FS4 FS2

FSI

1
j

I

i

0
I~

FSO

25.175

0

1

0

0

28.322

0

I

0

I
0

40.000

I

0

1

I

44.900

I

0

I

I

1

GenLock

1

1

0

0

OVerlay

I

I

0

Video Only

I

I

I

1

1

I

Graphics Only

I

19

I

I

0

I

I
[

,

I

--I

I

i

0
I

,

I

GSPSOO Frequently Asked Technical Questions.
1. What will the GSP500 do for me?
The GSP500 adjusts the timing of a VGA controller to conform to RS-170A NTSC (television) specifications. The
GSP500 accepts direct video Input from video cameras, videodisc players or other video sources and will synchronize
(genlock) a VGA controller to either the external video input or an internal NTSC sync generator. The GSP500 also
contains a dot clock generator to eliminate the need for crystal oscillators or other dot clock generators.

2.

How does the GSP500 differ from other genlock devices?

Other genlock devices, such as the Motorola MC1378, are very effective at genlocking two NTSC signals together
and are generally used in consumer electronics products such as video window-in-a-window devices. The GSP500
is specifically designed to genlock a computer graphics controller to NTSC video and overcomes all of the
incompatibilities between VGA and NTSC. Additionally, the GSP500 contains an NTSC sync generator and maintains
chrominance phase lock in local modes. This allows the GSP500 to maintain RS-170A NTSC timing without an external
video input. Furthermore, the sync separator circuit of the GSP500 is designed to satisfy the low jitter tolerances
demanded by discriminating VGA customers.

3.

Isn't genlock simply a phased-lock loop?

Phase locking two similar signals is fairly straightforward as long as phase jitter is not critical. As an example, ICS is
one of the few companies able to successfully build phase-locked loop dot clock generators with low enough phase
jitter for computer graphics display. Additionally, the differences between VGA and NTSC signals further complicate
the genlock procedure. The GSP500 has patents applied for for the most advanced computer video genlock methods
in the industry. These methods assure you of the highest possible quality product.

4.

Most Genlock and Overlay products have a lot of discrete components with trimmer
capacitors and potentiometers. All these adjustments can become very expensive in
a mass production environment. How much external circuitry does the GSP500
require?

Although the GSP500 can be run with no trimmer capacitors or potentiometers, one trimmer capacitor should be used
to meet the NTSC frequency tolerance of the chroma burst. This is a free running frequency and is very simple (and
fast) to adjust. Additionally, the GSP500 uses high speed digital circuitry to eliminate virtually all discrete components.
Only a few external components are needed for full operation.

5.

Do I need an RGB-to-NTSC encoder with the GSP500?

Yes, an external RG8-to-NTSC encoder is needed. The encoder must be matched to the target audience. The GSP500
can be used under broadcast television scrutiny and most broadcast video equipment perform the encoding entirely
with discrete components. As this may prove too costly and/or may use too much board space, the GSP500 contains
all of the necessary signals to drive virtually any encoder. The GSP500's generous supply of timing signals will also
drive external circuitry to turn off the encoder for laptop applications.

6. Why do I need the GSP500. Can't I program a VGA controller for NTSC sync and just
drive an RGB-to-NTSC encoder?
NTSC sync contains equalizing pulses, blanking signals and pulse widths that are impossible to create under normal
VGA control. Although marginal display quality is achievable on a television without adhering to the RS-170A standard,
compatibility with other NTSC equipment is compromised. As an example, depending on which edge of horizontal
sync the monitor triggers on will determine how far an incorrect width horizontal sync pulse will skew the screen.
Additionally, it becomes virtually impossible to assure proper chroma burst (SCH) phasing. The GSP500 sync
generator meets or exceeds all NTSC RS-170A broadcast standards for timing accuracy assuring you of maximum
compatibility and ultimate quality.

20

7.

National sells a sync separator for less than $2 while the Brooktree part costs over
$50. What is the difference and how does the sync separator in the GSP500 compare?

The sync separation circuitry in the National part is a simple diode clamp. Although this may be adequate for driving
a picture tube, the lack of noise and jitter immunity make it unsuitable for genlock applications. Additionally, the analog
vertical sync detection circuit of these type of devices will not accurately track a VCR signal. The Brooktree device
represents a mixed-mode approach to sync separation. By utilizing a fast analog circuitry coupled with high speed
digital logic, nOise and jitter immunity can be optimized. The GSP500 also uses a mixed mode approach specifically
optimized for genlock operation yet the incorporation of a sync generator allows signal analysis not possible with
other devices.

8. Is the GSP500 compatible with any VGA controller?
VGA controllers need to have two features to work with the GSP500. First, they need to be able to interlace - if your
controller can display 1024 x 768 resolution, then it can probably interlace (the additional 256K memory is not
necessary). Second, the controller must have at least three clock select lines for external dot clock generator support.
Virtually all current VGA controllers have this feature. Check with your VGA controller manufacturer or ICS if you are
unsure.

9.

How do I turn the NTSC on and off and control it?

The GSP500 uses the three clock select lines to support 4 VGA clocks and 4 NTSC modes. The VGA clocks are
available in 7 different patterns (i.e. 25.175, 28.322, 40.000, 65.000 is one pattern). The 4 NTSC modes are Genlock,
Overlay, Graphics Only, and Video Only. The selection between any NTSC mode or between NTSC and VGA is done
entirely under BIOS or software control.

10. Why did you incorporate a dot clock generator in the GSP500?
The GSP500 works by modifying the dot clock input for the VGA controller. It essentially is a dot clock generator
designed for NTSC genlock. The dot clock generator is not so much of an extra feature as it is a subset of the genlock
design. Consequently, this unity design assures you of a reliable glitch-free solution.

11. When the GSP500 displays an Overlay, how do I determine which part of the screen
displays graphics and which is VGA?
The GSP500 uses a technique called Color-Key to determine where to display the external video. This Color-Key color
is based on the VGA color number. Therefore, no colors are actually lost. As an example, the background color is
always Color O. When Color-Keying on Color 0, the screen will appear to have a background of the external video.
The actual color that the VGA assigns to Color 0 does not matter. Any of the 256 color numbers can be assigned to
be a Color-Key. Although the GSP500 modifies the Color-Key input, the Color-Key selection is done by an external 8
bit digital compare.

12. Why is the Color-Key selection external to the GSP500?
Color-Key selection is done with an 8 bit compare of the digital RGB signals with a preassigned byte. The digital RGB
data comes from the VGA controller and the preassigned byte normally comes from the IBM bus via a port selection.
The output of this comparison is fed into the CKEY (Color-Key) input of the GSP500. Although this Color-Key method
will satisfy 95% of all customers, the external design allows other schemes with multiple or different comparison
options. Additionally, since all of these signals are already available inside the VGA controller, many manufacturers
have announced plans to incorporate the Color-Key function inside the VGA controller.

13. What about PAL and/or SECAM compatibility?
ICS is presently working on a PAL version of the GSP500. In its current implementation, it will be pin compatible with
the GSP500 but require different values for the discrete cornponents and will also need a different crystal oscillator.
Although a SECAM version is technically possible, due to the uncertain market potential product development is not
currently underway.

14. Can I look forward to a combination PAL and NTSC product?
Unfortunately, the amount of circuitry common to both a PAL and an NTSC version is minimal. Separate versions are
currently the lowest cost solution. Although the crystal frequency, some discrete components and the Bios would
have to change, the same board layout could support both standards by simply changing the parts list.

21

A

15. Does the GSP500 accept multiple video inputs? What about an S-Video input?
The GSP500 has two independent video inputs. Either input can be used or they can both be disabled. Either input
can be wired to accept either S-Video or NTSC. Selection between the two inputs is performed under hardware control.

16. Why doesn't the GSP500 incorporate audio?
The NTSC and S-Video baseband signals do not have a provision for audio. This means that the video and audio
signals are completely separate signals at all times. ICS offers audio products for the multimedia market that can be
incorporated into the design but allows the designer maximum flexibility by keeping them separate products.

17. Can I use the GSP500 with an RF modulator?
Yes, but the quality of the image may suffer. When NTSC is modulated up to RF frequencies, audio is modulated onto
a 4.5 MHz carrier and the video is limited to a maximum frequency of 4.2 MHz. Although 4.2 MHz may be sufficient
for moving images it can be limiting for high resolution computer graphics. This problem is magnified because the
majority of RF modulators are very low quality devices. Additionally, even if a high quality RF modulation is obtained,
the signal may still be degraded by the RF demodulator inside the television set. ICS does recognize the these
limitations may be outweighed by the user..friendliness and compatibility of the RF standard. High quality RF
modulators are available and the GSP500 does have the necessary signals for support but these issues should be
carefully weighed before implementation.

18. Can the GSP500 display NTSC video on my VGA screen?
No, in order to display NTSC video at 31.5 KHz, it is necessary to convert NTSC into component form, digitize it in
real time, and store at least one frame of video. Although technology exists to accomplish this, the price-to-performance ratio of these products is too high for mass market acceptance at this time.

19. Is there any question that I forgot to ask?
Yes, when I use a graphics program, I find the borders very distracting yet I need the borders in text modes to
insure that I can read the DOS prompt. Can the GSP500 help me with this problem? The GSP500 has the ability
to adjust the width of the screen totally under Bios control. This means that you can have limited overscan in
mode 13, minor underscan in mode 3 and generous overscan in mode 12. Software drivers can even be written
to dynamically change the screen width with the cursor keys.

20.

Does this mean I can change the height of the screen also?

NTSC has a fixed number of lines. In order to change the vertical size, the screen data must be compressed or
expanded into fewer or greater lines. This can be accomplished in a text mode by changing the font size or in a
graphics mode with linear interpolation. The GSP500 always maintains an exact one-to- one correlation between the
NTSC and VGA line position and therefore does not support vertical sizing.

21. Where do I get a development kit for the GSP500?
Call1CS at (800) 220-3366 for more information. We will put you in touch with a local rep. who will be more than happy
to supply you with a full GSP500 development kit. The ICS full service support organization is always ready to help
you with the latest in Multimedia solutions.

22

II

GSP600

Integrated
Circuit
Systems, Inc.

VGAlPAL Video Genlock Processor with Overlay
Overview

Features
• Direct input

The GSP600 allows the text and graphic images ofVG A and
Super VGA controllers to be displayed on standard PAL
televisions or recorded on a VCR.
Additionally, the
GSP600 accepts external video input from a camcorder or a
VCR and will synchronize (genlock) the VGA or Super
VGA controller to the external video. The GSP600 also
allows VGA and video images to be overlaid on the same
television screen. The GSP600 meets or exceeds all PAL
broadcast standards for timing accuracy and allows the
VGA controller to maintain true PAL compatibility at all
times. The GSP600 is compatible with virtually all VGA
controllers. Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR have BIOS support available for the
GSP family of products.
9

10

1

•

•
•
•

61

iSO[OOOOOOsO:O~OOOJOOOOOiS== 60
=
=
=
=
=
=
=
23
GSP600
is
=
=
=
=
~
§
=
=
=
=

•

=

26

-1.

Input 1

•

iSOOOOOOOOOOOOOOOOOiS44
27

VIdeo

•

of PAL or S-Video (S-VHS and Hi-8
video).
On board PALlS-Video sync and black burst generation
for local video operation. Video chroma burst separate
with 4.433618 MHz and 17.734475 MHz phase locked
outputs.
Meets or exceeds all timing specifications for studio and
broadcast television.
High efficiency PALlS-Video conversion that maintains
VGA performance.
Dynamic overscan and underscan adjustment of PALlSVideo modes under BIOS and/or software control.
Software selection between all VGA and PALlS-Video
modes.
PALlS-Video conversion support for all VGA and Extended VGA modes with 600 or fewer lines.
Built-in dot clock circuitry to eliminate crystal oscillators for VGA, plus extended VGA operation up to
135 Mhz.
Low power consumption, ideal for laptop computers.

~

YIPfU.

~

C

43

~

-H

YIPfU.1-<

GSP600

~

~OO~

~.

Video
0uIput/
ConlrOl

t--------'

s~_

RGB-to-PAL

~

encoder
CI-<

YIPfU.

~

Input 2

~

~.

C

VGNPfU.
Sync

Dot

Ck>ck

I?~I
'i.~":

II

t81 D-15
~

Mode

Select

'roA
Sync

~
PC Bus

-

'---'

~

VGA
Controller

'=

IGSP600RevA0893 I
23

RAMDAC

I

GSP600
Internal Block Diagram

VIDEO INPUT 1
VIDEO
OUTPUT

VIDEO INPUT 2

ENCODER
LOGIC
VIDEO

GENLOCK

SIGNAL
PROCESSING
AND
SYNC
CORRECTION

TIMING
CONTROL
AND
CLOCK
REGULATION

MODE
SELECT
LOGIC

VGA
SYNC

VGA
DDT
CLOCK

PIXEL
SWITCH
(OVENABLE)

-II~

0-15

SYNC
OUTPUT

CKEY
INPUT

D-IS SYNC OUTPUT for the monitor connection Lo allow
for TV projection output of the VGA images. The PIXEL
SWITCH information derived from external CKEY INPUT
tells the encoder whether to display the VGA image or
external video for each pixel. Assuming the images are
genlocked, this creates the overlay effect.

Theory of Operation
The GSP600 can be thought of as an extremely sophisticated
dot clock generator. In its simp lest form, the GSP600 will
generate all of the dot clock frequencies necessary to drive
VGA and Super VGA controllers. The different frequencies are selected with the MODE SELECT LOGIC from the
VGA chip. Selection is similar to selecting frequencies on
any of the ICS dot clock generators (i.e., ICS1394, ICS 1494,
ICS1561, ICS2494, etc.). Additionally, there are four reserved frequency addresses. These are labeled GL (genlock), OV (overlay), VO (video only), and GO (graphics
only). Choosing any of these addresses will switch the
GSP600 from VG A mode to PAL mode. Under PAL mode,
the GSP600 accepts vertical and horizontal VGA SYNC
from the VGA controller and uses the sync to generate and
adjust the VGA DOT CLOCK. The GSP600 will automaticallyvarythe frequency of the dot clock in order to synchronize the VGA sync signals with a PAL reference signal. This
reference signal can be derived from a video device (such as
a camcorder) connected to VIDEO INPUT 1 or VIDEO
INPUT 2. The GSP600 provides an RGB-to-PAL encoder
with the VIDEO OUTPUT signal which is either VIDEO
INPUT I, VIDEO INPUT 2, or an internally generated black
burst signal. All of the necessary ENCODER LOGIC signals to properly drive the encoder are provided by the
GSP600. During PAL modes the GSP600 also creates the

Block definition
Video Input Switch
The Video Input Switch selects whether the GSP600 uses
VIDEO INPUT lor VIDEO INPUT 2as the external video
source. It is controlled by an external pin of the GSP600.

PAL Sync Separator
The GSP600 contains a high quality sync separator to allow
direct input of PAL, S-VHS, or HI-8 video signals from
camcorders, VCRs, and other video products. The GSP600
utilizes a differential video input circuitry for maximum
noise immunity. It also employs digital noise filtering and
enhanced digital signal tracking technology to ensure maximum compatibility with consumer, industrial, and broadcast
video signals. Although low cost video sync separator products are commonly available, they are primarily designed for
television and video monitor use. The simple diode clamping
circuit used in these devices does not have the accuracy or
noise immunity required for genlocking.

24

GSP600
Sync Correction

PAL Sync and Black Burst Generator
PAL Sync Generator

The Sync Correction circuitry looks for missing sync pulses,
block sync, single field video, and phase shift errors caused
by the head switching zone of a VCR. It assures proper
genlock during all of these problems common in consumer
video products.

The studio quality built-in video sync generator allows the
GSP600 to operate without an external video input and still
maintain broadcast video timing. This assures PAL compatibility at all times. When external video is present, the
sync generator works in conjunction with the sync separator
to isolate sync from noisy video signals.

Genlock Timing Control and Clock Regulation
The GSP600 looks at the input sync from the VGA controller and determines how to alter the dot clock to create PAL
timing. Both the freq uency and the method can change with
different VGA modes. The GSP600 enables virtually any
VGA controller capable of interlacing to create PAL timing.
The GSP600's umque architecture provides ultra-high efficiency and flexibility and allows the frequency of the dot
clock to be controlled totally under BIOS or software control. Screen attributes such as horizontal width and position
can be individually programmed for each mode while maintaining genlock integrity. This circuit will modify the timmg
of virtually any mode, with 600 or fewer lines, to meet PAL
specifications. The GSP600 genlock timing control and
clock regulation design is awaiting patent approval.

Black Burst Generation
Most RGB-to-PAL encoders synchronize a crystal oscillator to the chroma burst signal of the external VIdeo signal.
This provides the color reference portion of the video signal.
If an external video signal is not available, the crystal oscillator will free run, creating screen artifacts such as 45 degree
moving lines in constant color portions of the screen. To
eliminate this problem, the GSP600 generates a black burst
video signal. Black burst video is an analog signal containing
both sync and a correctly phased chroma burst signal. This
ensures proper color reference generation at allumes. The
GSP600 provides black burst output to the encoder when
external video is either missing or not selected (non-genlock
mode).

Precision Dot Clock Generator

INT/EXT Video Switch

The GSP600 uses the same state-of-the-art dot clock technologythat has made ICS the premier supplier ofVGA dot
clock generators. ICS offers the highest accuracy and lowest
jitter products available.

The Internal/External Video Switch determines whether the
encoder uses external video or the black burst signal. If
external video is chosen, the GSP600 will simply pass the
external video signal through to the encoder, unaffected.
Black burst is used when external video is not present. The
switch is controlled by the Video Signal Processing and Sync
Correction circuitry.

CKEY
The ckey (or color-key) circuitry creates the pixel switch for
the encoder. This signal determmes whether the VGA image or external video is displayed for each pixel. Ckey is
modified by the GSP600 to ensure that the pixel switch signal
is delayed (to make up for delays in the RAMDAC) and that
it has proper levels during sync and blanking. If the VG A
and external signals are genlocked, this pixel switch will
create an overlay effect.

Video Signal Processing and Correction
Video Signal Processing
The Video Signal Processing circuitry of the GSP600 measures the incommg video signal for basic timing accuracy and
signal noise. It contains intelligent circuitry to remove extraneous portions of the video signal that would normally be
incorrectly categorized as sync. This is extremely important
when using a VCR as a video input. If there is an mterruption of the external video signal, this circuit Will automatically switch inputs from the external video signal to the
internal sync generator. When the external video signal
resumes, the circuit will automatically switch back to the
external video. The Video Signal Processing accepts the
MODE SELECT LOGIC from the VGA chip. This logic
chooses eithcr VGA or PAL operation and selects whether
genlock to external video is to be enabled.

25

GSP600
PIN
NUMBER

DESCRIPTION
VLE

2
3
4
5
6
7

8
9
10
II

12
13

14
15
16
17
18
19

20
21
22
23

VERTICAL LOCK ENABLE. HIGH for VGA controllers.
LOW disables vertical lock feature, may be useful for Non-VGA Operation.
ODD/EVEN
ODD/EVEN FIELD IDENTIFICATION. HIGH indicates odd numbered
field, LOW indicates even numbered field.
BP
BACK PORCH PULSE. Negative polarity TTL level signal used by some
RGB-to-PAL encoders.
DATAIN
Data input for inserting SMPTE time code in video signal.
COMPOSITE BLANKING OUTPUT. Indicates non-screen data portions
CB
of PAL signal.
COMPOSITE SYNC. PAL composite sync output for RGB-to-PAL
CS
encoders. Gated off during VGA modes.
CKEY
COLOR KEY. Resultant input from the 8-bit compare of digital RGB
(PO-P7) and a software selectable byte. This color key determines which pixels
display VGA and which display external video in overlay mode. See Hardware
Interface Manual for more details.
TEST
For ICS use only.
VSYNCOUT
VERTICAL SYNC OUTPUT. Vsync output for DB-15 connector.
DAT AFRAME TTL level framing signal active during lines 10-20. For use in time code
applications.
OVENABLE
OVERLAY ENABLE. Fast pixel rate switch. HIGH displays PAL output,
LOW display RGB output. Used for overlay encoders. See Application
Notes for wiring details.
IIES
INT.lEXT. SYNC. Determines sync selection in OVENABLE signal.
Tie LOW normally.
LOC/REM
LOCAL/REMOTE. A LOW output state signifies REMOTE status indicating
that external video is present and a genlock mode has been selected. If external
video goes away or a non-genlock mode is selected, LOCAL/REMOTE will
go HIGH.
BRSTACT
For ICS use only.
FRTSTOUT
For ICS use only.
HS
HORIZONTAL SYNC. For some RGB-to-PAL encoders.
Gated off during VGA modes.
HRSTOUT
For ICS use only.
HSYNCOUT
HORIZONTAL SYNC OUTPUT. Hsync output for DB-15 connector.
Digital ground. We strongly recommend the use of a multilayer board and a
VSS
ground plane.
VDD
5 Volt digital power. We strongly recommend the use of a multilayer board
and a power plane.
5 Volt digital power. We strongly recommend the use of a multilayer board
VDD
and a power plane.
VSS
Digital ground. We strongly recommend the use of a multilayer board and a
ground plane.
FS5
Frequency Select 5. Selects between multiple VGA Dot Clock frequencies,
Genlock modes and PAL frequencies. See Dot Clock Generation and
PAL Mode Selection sections for a more detailed description.
Also see Application Notes for wiring diagrams and BIOS Interface Manual
for details.

26

II
PIN
NUMBER

GSP600
NAME

24

FS4

25

FS3

26

FS2

27

FSI

28

FSO

29
30
31

EXTSYNC
VCRI
CLAMPLEV

32

Y2

33

YI

34
35
36

C2
CI
4.43SC

37
38

FRSTIN
AVDD

39
40

GFF
VCOLF

41
42

SYNCTHRS
VGAOIE

43
44

COUT
RST

45

YOUT

46
47

HALIGNOUT
SYSLF

48

XTALI

49

XTALO

DESCRIPTION
Frequency Select 4. Selects between VGA Dot Clock frequencies and
PAL modes.
Frequency Select 3. Selects between VGA Dot Clock frequencies and
PAL modes.
Frequency Select 2. Selection between VGA Dot Clock frequencies and
PAL modes.
Frequency Select I. Selects betweenVGA Dot Clock frequencies and
PAL modes.
Frequency Select O. Selects between VGA Dot Clock frequencies and
PAL modes.
For ICS use only.
HIGH permits using VCRs as an input.
Clamping level adjustment for video input. See Application Notes for
more details.
PAL video input number 2. Note: This is also the Y (luminance) input for
S-Video systems.
PAL video input number I. Note: This is also the Y (luminance) input for
S-Video systems.
C (Chrominance) input number 2 for S-Video systems.
C (Chrominance) input number I for S-Video systems.
4.433618 MHz SUBCARRIER OUTPUT. Phase-locked to the chroma burst
signal to allow encoders to maintain proper SCH phasing.
For ICS use only.
5 Volt analog power. We strongly recommend the use ofa multilayer board
and a power plane.
Inverts field I and field 2 ofVGA sync. Normally tied HIGH.
VCO LOOP FILTER CIRCUIT. External RC circuit used in VCO circuitry.
See Application Notes for component values.
Sync threshold adjustment for video input. See Application Notes.
VGA ODDIEVEN FIELD IDENTIFICATION. HIGH indicates odd
numbered field, LOW indicates even numbered field.
C (Chrominance) OUTPUT. C output for S-Video systems.
Chip reset pulse. This to be tied high through a resistor.
Do not tie to the computer reset line.
Y (Luminance) OUTPUT. PAL video output when the PALISVID
input is in the HIGH state. Y output for S-Video systems when the
PALISVID input is in the LOW state.
For ICS use only, wire to pin 62.
SYSTEM CLOCK LOOP FILTER CIRCUIT. External RC circuit used in
the chroma burst phase locking circuit. See Application Notes for
component values.
17.734475 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.
17.734475 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.

27

I

L.

GSP600
PIN
NUMBER

NAME

50

AVSS

51
52
53
54
55
56
57

VID1I2
VCOOUT
FILTSEL
DOTCLOCK
VFF
VCR2
VGA/PAL

58

BG

59
60

LOC/REMIN
VGAHSYNC

61

VGAVSYNC

62
63

HALIGNIN
PALISVID

64

VS

65

4XSC

66
67

PCLK
DATAOUT

68

SCH

DESCRIPTION
Analog ground. We strongly recommend the use ofa multilayer board and a
ground plane.
Input selector. High for YlIC1, Low for Y2/C2.
For ICS use only, do not wire.
For ICS use only, wire to pin 57.
Clock signal input for VGA chip.
Inverts field 1 and field 2 of PAL sync. Normally tied HIGH.
LOW modifies sync characteristics to permit operation with VCR input.
Mode identification output signal. HIGH indicates a VGA mode, LOW
indicates a PAL mode.
BURST GATE PULSE. Negative polarity TTL level signal used by
R G B-to-P AL encoders.
For ICS use only, wire to pin 13.
VGA HORIZONTAL SYNC. HSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
VGA VERTICAL SYNC. VSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
For ICS use only, wire to pin 46.
PALlS-VIDEO. Selects between PAL and S-Video output. HIGH= PAL;
Low: S-Video.
VERTICAL SYNC. PAL Vsync output for RGB-to-PAL encoders.
Gated off during VGA modes.
4 TIMES SUBCARRIER OUTPUT. 17.734475 MHz signal phase-locked to
the chroma burst signal.
PCLK from VGA chip.
TTL level output. This reads data during lines 10-20 and outputs it as a
digital signal. For use in time code applications.
SCH PULSE. Positive polarity TTL level signal to distinguish between
fields 1 and 3 or 2 and 4. Not necessary for most encoders.

28

GSP600
BIOS Programming Example
BIOS support is currently available from Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR. Other VGA
manufacturers have support programs underway. If you use one of these VG A controllers that have completed BIOS
support, you can ignore this section. The following information may be helpful to VGA manufacturers and software
developers. These tables represent register settings one particular VGA controller. Others are listed in the BIOS Interface
Manual. This particular controller does not interlace text modes and uses an 8 x 8 font for modes 0, 1, 2 , 3, and 7. The
horizontal registers are adjusted to produce underscan for text modes and overscan for graphics modes.

Horizontal CRTC Registers
CRTC
INDEX
!I

I

CRTC
REGISTER

Modes:

I

I 00, 01, 04, 05, OD

Modes:
02, 03,06,07, OE, OF, 10

Modes:
11,12,13

6B

66

4F

4F

53

52

00

HT

35

01

HDE

27

02

SHB

2A

03

EHB

96

8B

87

04

SHR

30

5B

58

05

EHR

92

CRTC
REGISTER

200 Line Modes:
(Non-Interlaced)
00,01,02,03,07,04,
05,06, OD, OE, 13

350 Line Modes:
(Interlaced)
OF, 10

480 Line Modes:
(Interlaced)
12,13

06

VT

05

05

05

07

OVERFLOW

11

11

11

10

VRS

EO

D3

F4

11

VRE

84

87

88

12

VDE

C7

AE

EF

15

SVB

DC

CF

FO

16

EVB

F2

E5

06

!

I

83

,

80

I

I

iiiertlcaI CRTC Reglsters
CRTC
INDEX

Note: The MSB ofthe MSL register (INDEX 09) must be turned OFF in 200 line NTSC modes. When using an 8 x 8 font
for text (modes 00, 01, 02, 03, 07) the 4 LSB of this register will change from F to 7.

Miscellaneous Output Register
NTSC mode
Genlock (GL)

Color Modes:
00,01,02,03,04,05,06,
. _ _()D, OE, 10, II, 12, 13
23

Monochrome Modes:
--.Sl7, OF
22

-------

Overlay (OV)

27

26

Video Only (VO)

2B

2A

Graphics Only (GO)

2F

2E

Extended Registers
Turn OFF all DOTCLOCKl2 bits.

29

- - -I

I

II

GSP600
PAL vs. VGA Horizontal Timing
~

I

~r---

Safe Act lOn Area
Safe Tltle Area

lYf---1---------1~f---1

L

u

3

64uS

II

--

4M

12uS

II ,---LL-II_ _-------.WII

u

----1~

~-- Honzontal Olsplay End

Blanklng

r-----

HOrlzonlal Total

PAL vs. VGA vertical timing (200 line mode)
219

?20

221

222

223

224

225

226

227

228

141

229

242

?43

244

PAL sync
VGA Hsync
VGA Vsync

624

625

10

11

12

13

PAL sync
VGA Hsync
VGA Vsync

_ _ _ _~

260

261

262

263

20

21

??

23

24

25

26

27

PAL sync
VGA Hsync
VGA Vsync

- - - - - - - - - - - - - - - - 1 1_ _ _ _ _ _ _ _ _ _ _ _ __

30

II

GSP600

Electrical Specifications
Operating temperature range o°c to 70°C

Electrical Characteristics
SYMBOL

PARAMETER
Analog Supply
Digital Supply
Operating Current - VGA Mode

AVDD
DVDD
IDD (VGA)
IDD (PAL)

MIN

TYP

4.5
4.5

5.0
5.0
35
50

I

Operating Current - PAL Mode

MAX
5.5
5.5

UNITS
Volts
Volts
rnA
rnA

Input Signals
SIGNAL TITLE

PIN #
33

TYPICAL VALUE
1 Vp_p

OPERATING CONDITIONS

Yl
Cl

35

IVp_p

750hrnload

Y2

32

C2
VIDlI2

34

lVp_p
IVp_p

75 Ohm load
75 Ohm load

51

TTL/CMOS

High = Yl,Cl; Low = Y2,C2

PAL/SVID

63

TTL/CMOS

High = PAL; Low = S-Video

VGAVSYNC

61

TTL/CMOS

VGAHSYNC

TTL/CMOS

Positive polarity
Positive polarity

FSO-5

60
28-23

TTL/CMOS

Address/mode select

CKEY

7

TTL/CMOS

High= RGB;Low= PAL

PCLK

66

TTL/CMOS

Pixel (DAC) Clock from VGA

liES

12

TTL/CMOS

High = Internal sync
Low = External SynC
Active during D A T AFRAME

DATAIN

4

TTL/CMOS

CLAMPLEV

31

1-1.5 V

SYNCTHRS

41

CLAMPLEV + 0.1 V

VLE

1

TTL/CMOS

RSTI

44

TTL/CMOS

31

750hrnload

Tie to VDD through resistor
Tie to VDD through resistor

I

II

GSP600
Output Signals
SIGNAL TITLE

PIN#

TYPICAL VALUE

VSYNCOUT
HSYNCOUT

9
18
64
16
6
54
45
43
36
65

TTL
TTL
lVp_p
1Vp_p
1Vp_p

VS
HS
CS
DOTCLOCK
YOUT
COUT
4.43SC
4XSC
LOCIREM
OVENABLE
VGAIPAL
CB
ODDIEVEN
VGAOIE
BGI
FPI

SCH
DATAFRAME
DATAOUT

13
11

57
25
2
42
58
3
68
10
67

TTL
1Vp_p
1Vp_p
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

32

OPERATING CONDITIONS
Positive polaritv during PAL modes
Composite sync during PAL modes
Positive polaritv
Positive polaritv
Positive polaritv
75 Ohm load
75 Ohm load
4.433618 MHz
17.734475 MHz
High = local; Low = remote
High= PAL;Low= RGB
High= VGA;Low= PAL
Positive polarity
High = odd field' Low = even field
High = VGA odd field
Low = VGA even field
Negative polaritv
Negative polarity
Positive po1aritv
Lines 10-20
Active during D A T AFRAME

GSP600
Dot Clock Selection
The following charts represent two of the many dot clock frequency selection tables supported by GSP600. See the BIOS
manual or contact ICS applications engineering for additional information.

!

FREQUENCY (MHz)

FS5

FS4 FS3 FS2

FSI

FSO

50.350

0

I

0

0

56.644

0

I

0

65.028

0

I

I

72.000

0

1

1

1

75.000

1

0

0

0

80.000

I

0

0

1

89.800

I

0

1

0

1
!
I

0

110.000

I

0

1

1

GenLock

I

1

0

0

OVerlay

1

1

Video Only

1

1

Graphics Only

I

FREQUENCY (MHz)
25.175
28.322

0

1

1

0

I

I

1

FS5 FS3

FS4 FS2

FSI

FSO

0

1

0

0

0

I

0

1
0

I

40.000

0

1

1

44.900

0

1

1

1

GenLock

I

I

0

0

OVerlay

I

I

0

1

Video Only

I

I

I

0

Graphics Only

I

I

1

1

33

I

GSP600 Frequently Asked Technical Questions.
1. What will the GSP600 do for me?
The GSP600 adjusts the timing of a VGA controller to conform to PAL (television) specifications. The GSP600 accepts
direct video input from video cameras, videodisc players or other video sources and will synchronize (genlock) a VGA
controller to either the external video input or an internal PAL sync generator. The GSP600 also contains a dot clock
generator to eliminate the need for crystal oscillators or other dot clock generators.

2. How does the GSP600 differ from other genlock devices?
Other genlock devices, such as the Motorola MC1378, are very effective at genlocking two PAL signals together and
are generally used in consumer electronics products such as video window-in-a-window devices. The GSP600 is
specifically designed to genlock a computer graphics controller to PAL video and overcomes all of the incompatibilities
between VGA and PAL. Additionally, the GSP600 contains an PAL sync generator and maintains chrominance phase
lock in local modes. This allows the GSP600 to maintain PAL timing without an external video input. Furthermore, the
sync separator circuit of the GSP600 is designed to satisfy the low jitter tolerances demanded by discriminating VGA
customers.

3.

Isn't genlock simply a phased-lock loop?

Phase locking two similar signals is fairly straightforward as long as phase jitter is not critical. As an example, ICS is
one of the few companies able to successfully build phase-locked loop dot clock generators with low enough phase
jitter for computer graphics display. Additionally, the differences between VGA and PAL signals further complicate the
genlock procedure. The GSP600 has patents applied for for the most advanced computer video genlock methods in
the industry. These methods assure you of the highest possible quality product.

4.

Most Genlock and Overlay products have a lot of discrete components with trimmer
capacitors and potentiometers. All these adjustments can become very expensive in
a mass production environment. How much external circuitry does the GSP600
require?

Although the GSP600 can be run with no trimmer capacitors or potentiometers, one trimmer capacitor should be used
to meet the PAL frequency tolerance of the chroma burst. This is a free running frequency and is very simple (and
fast) to adjust. Additionally, the GSP600 uses high speed digital circuitry to eliminate virtually all discrete components.
Only a few external components are needed for full operation.

5.

Do I need an RGB-to-PAL encoder with the GSP600?

Yes, an external RGB-to-PAL encoder is needed. The encoder must be matched to the target audience. The GSP600
can be used under broadcast television scrutiny and most broadcast video equipment perform the encoding entirely
with discrete components. As this may prove too costly and/or may use too much board space, the GSP600 contains
all of the necessary signals to drive virtually any encoder. The GSP600's generous supply of timing signals will also
drive external circuitry to turn off the encoder for laptop applications.

6. Why do I need the GSP600. Can't I program a VGA controller for PAL sync and just
drive an RGB-to-PAL encoder?
PAL sync contains equalizing pulses, blanking signals and pulse widths that are impossible to create under normal
VGA control. Although marginal display quality is achievable on a television without adhering to the PAL standard,
compatibility with other PAL equipment is compromised. As an example, depending on which edge of horizontal sync
the monitor triggers on will determine how far an incorrect width horizontal sync pulse will skew the screen. Additionally,
it becomes virtually impossible to assure proper chroma burst (SCH) phasing. The GSP600 sync generator meets or
exceeds all PAL broadcast standards for timing accuracy assuring you of maximum compatibility and ultimate quality.

34

7.

National sells a sync separator for less than $2 while the Brooktree part costs over
$50. What is the difference and how does the sync separator in the GSP600 compare?

The sync separation circuitry in the National part is a simple diode clamp. Although this may be adequate for driving
a picture tube, the lack of noise and jitter immunity make it unsuitable for genlock applications. Additionally, the analog
vertical sync detection circuit of these type of devices will not accurately track a VCR signal. The Brooktree device
represents a mixed-mode approach to sync separation. By utilizing a fast analog circuitry coupled with high speed
digital logic, noise and jitter immunity can be optimized. The GSP600 also uses a mixed mode approach specifically
optimized for genlock operation yet the incorporation of a sync generator allows signal analysis not possible with
other devices.

8.

Is the GSP600 compatible with any VGA controller?

VGA controllers need to have two features to work with the GSP600. First, they need to be able to interlace - if your
controller can display 1024 x 768 resolution, then it can probably interlace (the additional 256K memory is not
necessary). Second, the controller must have at least three clock select lines for external dot clock generator support.
Virtually all current VGA controllers have this feature. Check with your VGA controller manufacturer or ICS if you are
unsure.

9.

How do I turn the PAL on and off and control it?

The GSP600 uses the three clock select lines to support 4 VGA clocks and 4 PAL modes. The VGA clocks are available
in 7 different patterns (Le. 25.175, 28.322, 40.000, 65.000 is one pattern). The 4 PAL modes are Genlock, Overlay,
Graphics Only, and Video Only. The selection between any PAL mode or between PAL and VGA is done entirely under
BIOS or software control.

10. Why did you incorporate a dot clock generator in the GSP600?
The GSP600 works by modifying the dot clock input for the VGA controller. It essentially is a dot clock generator
designed for PAL genlock. The dot clock generator is not so much of an extra feature as it is a subset of the genlock
design. Consequently, this unity design assures you of a reliable glitch-free solution.

11. When the GSP600 displays an Overlay, how do I determine which part of the screen
displays graphics and which is VGA?
The GSP600 uses a technique called Color-Key to determine where to display the external video. This Color-Key color
is based on the VGA color number. Therefore, no colors are actually lost. As an example, the background color is
always Color O. When Color-Keying on Color 0, the screen will appear to have a background of the external video.
The actual color that the VGA assigns to Color 0 does not matter. Any of the 256 color numbers can be assigned to
be a Color-Key. Although the GSP600 modifies the Color-Key Input, the Color-Key selection is done by an external 8
bit digital compare.

12. Why is the Color-Key selection external to the GSP600?
Color-Key selection is done with an 8 bit compare of the digital RGB signals with a preassigned byte. The digital RGB
data comes from the VGA controller and the preassigned byte normally comes from the IBM bus via a port selection.
The output of this comparison is fed into the CKEY (Color-Key) input of the GSP600. Although this Color-Key method
will satisfy 95% of all customers, the external design allows other schemes with multiple or different comparison
options. Additionally, since all of these signals are already available inside the VGA controller, many manufacturers
have announced plans to incorporate the Color-Key function inside the VGA controller.

13. What about NTSC and/or SECAM compatibility?
ICS has an NTSC version of the GSP600 (the GSP500). In its current implementation, it is pin compatible with the
GSP600 but require different values for the discrete components and will also need a different crystal oscillator.
Although a SECAM version is technically possible, due to the uncertain market potential product development is not
currently underway.

14. Can I look forward to a combination PAL and NTSC product?
Unfortunately, the amount of circuitry common to both a PAL and an NTSC version is minimal. Separate versions are
currently the lowest cost solution. Although the crystal frequency, some discrete components and the Bios would
have to change, the same board layout could support both standards by simply changing the parts list.

35

A

15. Does the GSP600 accept multiple video inputs? What about an S-Video input?
The GSP600 has two independent video inputs. Either input can be used or they can both be disabled. Either input
can be wired to accept either S-Video or PAL. Selection between the two inputs is performed under hardware control.

16. Why doesn't the GSP600 incorporate audio?
The PAL and S-Video baseband signals do not have a provision for audio. This means that the video and audio signals
are completely separate signals at all times. ICS offers audio products for the multimedia market that can be
incorporated into the design but allows the designer maximum flexibility by keeping them separate products.

17. Can I use the GSP600 with an RF modulator?
Yes, but the quality of the image may suffer. When PAL is modulated up to RF frequencies, audio is modulated onto
a 4.5 MHz carrier and the video is limited to a maximum frequency of 4.2 MHz. Although 4.2 MHz may be sufficient
for moving images it can be limiting for high resolution computer graphics. This problem is magnified because the
majority of RF modulators are very low quality devices. Additionally, even if a high quality RF modulation is obtained,
the signal may still be degraded by the RF demodulator inside the television set. ICS does recognize that these
limitations may be outweighed by the user-friendliness and compatibility of the RF standard. High quality RF
modulators are available and the GSP600 does have the necessary signals for support but these issues should be
carefully weighed before implementation.

18. Can the GSP600 display PAL video on my VGA screen?
No, in order to display PAL video at 31.25 KHz, it is necessary to convert PAL into component form, digitize it in real
time, and store at least one frame of video. Although technology exists to accomplish this, the price-to-performance
ratio of these products is too high for mass market acceptance at this time.

19. Is there any question that I forgot to ask?
Yes, when I use a graphics program, I find the borders very distracting yet I need the borders in text modes to
insure that I can read the DOS prompt. Can the GSP600 help me with this problem? The GSP600 has the ability
to adjust the width of the screen totally under Bios control. This means that you can have limited overscan in
mode 13, minor underscan in mode 3 and generous overscan in mode 12. Software drivers can even be written
to dynamically change the screen width with the cursor keys.

20.

Does this mean I can change the height of the screen also?

PAL has a fixed number of lines. In orderto change the vertical size, the screen data must be compressed or expanded
into fewer or greater lines. This can be accomplished in a text mode by changing the font size or in a graphics mode
with linear interpolation. The GSP600 always maintains an exact one-to- one correlation between the PAL and VGA
line position and therefore does not support vertical sizing.

21. Where do I get a development kit for the GSP600?
Call1CS at (800) 220-3366 for more information. We will put you in touch with a local rep. who will be more than happy
to supply you with a full GSP600 development kit. The ICS full service support organization is always ready to help
you with the latest in Multimedia solutions.

36

II

ICS2001

Integrated
Circuit
Systems, Inc.

I

Sound Output Circuit
General Description

Features

The ICS2001 is a CMOS integrated circuit containing an 8·bit
digital to analog converter fed by a l6·byte FIFO memory
array. This device is intended to form the nucleus of a low· cost
audio·output subsystem for personal computers, workstations,
games, and talking books. The ICS2001 is the core of the
Disney Sound Source.™

•
•
•
•
•
•

8·bit DIA converter
l6·byte FIFO
5V and 9V operation
TTL· level inputs with hysteresis
RC clock oscillator
Software drivers for DOS and Windows

Block Diagram
RC
OSCILLATOR
INIT*

"T'~
~
200K 5,'.

SELECT

RC

dV--[>o~~Ir------

~~I

rb'>~ ~~
I

~:

~ 200K

c.=i-=

110K

BUSY* n-r--''-e'\!V'-

1 lOOK

I

RESET

D5
D4
D3
D2

7KHz

!

8 BIT
DAC

Li>l

DAC
OUT

I

I

D1

D

~RO:: ~~'> l>~

.

14KHz I

~ ~~

D5
_ _I
D4 ~-+~@>----D3 ~~.~----ce>
I
D2 o-----l
c;;-------I
D1

c

:~~ IN

I

I--------i.

~

I

I

'RESET
DATA READY

VREF
GEN

~l~l
I

Ordering Information
*Sound Source

IS

ICS200lM (SO Package)
ICS2001N (DIP Package)

a trademark of Walt Disney Computer Software Incorporated

37

ICS2001
Pin Configuration

VDD

16

VSS

STROBE

2

15

DACOUT

DO

3

14

RC

Dl

4

13

INIT*

D2

5

12

SELECT

D3

6

11

D6

D4

7

10

D7

D5

8

9

BUSY*

Pin Descriptions
PIN NUMBER
1

PIN NAME

TYPE

DESCRIPTION

VDD

Power

Positive power supply

2

STROBE

Input

Data strobe

3

DO

Input

Data input

4

Dl

Input

Data input

5

D2

Input

Data input

6

D3

Input

Data input

7

D4

Input

Data input

Input

Data input

8

D5

9

BUSY*

10

D7

Input

Data input
Data input

Output

11

D6

Input

12

SELECT

Input

13

INIT*

14

RC

15
16

Input

Busy (Active Low)

Initialization (Active Low)

Oscillator

One-pin oscillator

DACOUT

Output

Converter output

VSS

Power

Negative power supply/ground

~---

38

ICS2001
Absolute Maximum Ratings
Storage temperature .......................... -65°C to ISO °C
Voltage on any pin with respect to ground ......... -0.5V to VDD+0.5V
Maximum VDD .............................. 1O.6V

Standard Test Conditions
Operating Temperature Range .................. 0 °C to 70°C
Power Supply Voltage ........................ 4.5 to 1O.0V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

DC Characteristics
PARAMETER

SYMBOL

NOTES

MIN

Logical I Input Voltage

VIH

2.0

Logical 0 Input Voltage

VIL

0

Input Leakage Current

II

TYP

i

MAX

UNITS

VDD
0.8

V

V

Any input

-1.0

Any input

20

50

Pull down resistors

INIT*, SELECT

100

200

300

Kohm

Pull down resistor

BUSY*

50

100

200

Kohm

5.0

rnA

Input Hysteresis

Supply Current
DAC output voltage

IDD
VDACOUT Data=$OO
Data=$FF

V

VDDI2
-I

DAC Output Current

IDACOUT

VDD=4.5

DAC Output Current

IDACOUT
CL

VDD=9

uA
mV

VDD/6

DAC Differential Linearity

DAC Capacitive Load

1.0

+1

200

LSB

500

uA

I

rnA
20

pF

Output Current High

IOH

VDD=4.5V
VOH=2.0V

200

400

itA

Output Current Low

IOL

VDD=4.5V
VOL=.8V

200

400

itA

AC Characteristics
PARAMETER

SYMBOL

CONDITIONS

MIN

R=160K; C=1000pF

12.6

,

TYP

MAX

UNITS

14.0

15.4

kHz

Oscillator Frequency

Fosc

Data Setup

TDS

0

Data Hold

TDH

100

ns

STROBE Width Low

TSL

50

ns

STROBE Recovery High

TSR

50

BUSY* Delay

TBD

CL=50pF

ns

-

ns
750

39

ns

I

ICS2001
Timing Diagram

D7-DO

!--tDH
VALID

STROBE _ _ _t-tSL~--1tSR---z~_~rr-t_BD-"1t--------_
BUSY*

\_----------'

40

II

ICS2001
In order to minimize unwanted current flow through the inputs
of the ICS2001 when the battery is disconnected or dead, all
chip inputs should be connected to the printer port via series
resistors with a nominal value of 10K ohms, and the power
connection to the VOO pin should include a blocking diode.
The BUSY* output, which normally drives an external NPN
transistor, is provided with an internal lOOK pull-down resistor
to keep the transistor turned off when the ICS2001 is not
powered up.

Function Description
The overall operational status of the ICS2001 is controlled by
the INIT* and SELECT inputs. If either INIT* or SELECT is low,
the chip is held in the "reset" condition: The BUSY* output is
asserted, the STROBE input is ignored, and OAC OUT is
forced to VOO/6 (minimum value). When INIT* and SELECT
become high, the device enters the "run" condition, and BUSY*
goes high indicating the FIFO is "ready for data."

The oscillator frequency is set by an external resistor and
capacitor. The design center values are 160K ohms (from the
RC pin to VOO) and 1000pF (from the RC pin to VSS). This
results in a nominal clock frequency of 14 kHz plus or minus
5 percent. This signal is internally divided by two to yield an
output sampling frequency of 7 kHz.

Binary data IS fed to the ICS2001 via the 00-07 pins and
latched into the FIFO buffer by the rising edge of STROBE.
Input data flow is controlled by the B USY* output. Data in the
FIFO is shifted out to the 01 A converter at a rate established by
the RC oscillator, typically 7 kHz. A data value of $00 will
generate nominal output of VOO/6 volts, while a value of $FF
will result in an output of VOO/2 volts.
The following steps represent a typical sound-playback sequence: SELECT is asserted causing BUSY* to go high indicating buffer ready for data. Data applied to pins 00-07 are
latched into the FIFO on the rising edge of STROBE. Additional bytes of data may be strobed in as long as BUSY*
remains high. Thus, BUSY* is used to control the flow of data
into the FIFO. SELECT is de-asserted after the last data byte
has been written and sufficient time allowed for it to be reproduced.
Note that the first data byte strobed in under a "ready," i.e.
BUSY*=I, status will ripple through to the O/A converter and
its analog value appears on OAC OUT asynchronously. Subsequent bytes will be output at the data rate established by the
RC clock as long as there is data in the FIFO. Therefore, it is
recommended that sound samples be padded with a $00 leading
byte to avoid time distortion between the first and second
sample. Similar glitches may occur in the middle of sound
sequences if the FIFO is allowed to empty.
Also note, that if the device is enabled (INIT* and SELECT=!)
while the STROBE input is high, the current value of the data
bus will be shifted into the FIFO. Therefore, during initialization for operation with STROBE pUlsing low (statically high),
valid data (usually $00) should be placed on the data inputs
before the reset condition is removed.
In a typical application, the ICS2001 shares a standard personal
computer (Centronics) printer port with the system printer, and
is powered by the same 9V source that supplies the external
low-pass filter and speaker driver that comprise the balance of
the sound subsystem. In the interest of simplicity and minimal
cost, this power source is usually a battery.

41

I

42

•

ICS2002

Integrated
Circuit
Systems, Inc.

I

Wavedec™ Digital Audio Codec
Description

Features:
•
•

Digital audio 8116 bit record/playback
Fully programmable sample rates including industry
standards:
44.1 kHz
22.050 kHz
11.025 kHz
8.00 kHz
5.513 kHz

•
•

DAC output oversampled to simplify external filtering.
Four data formats:
16 bit linear
- 8 bit linear
- 8 bit u-Iaw
- 8 bit a-law

•
•
•

16 step analog output level control, -1.5dB/step
8 bit log scale digital volume control
Oversampling ADC with input filter.
Programmable IIR filters for input antialiasing and output reconstruction.
ISA bus interface
8116 bit DMA and I/O transfer modes
Input/output FIFO buffer
Power down mode
44 pin PLCC package

•
•
•
•
•

The ICS2002 is a mixed-signal integrated circuit providing a
low-cost recording and playback solution for multimedia
audio applications. These applications include document
annotation, voice mail, interactive games, multimedia sound
record/playback, and Windows™ sound production. The
ICS2002 supports the record and playback of 16-bit audio
data, and provides a 8116-bit parallel interface to the industry
standard PC bus.

Block Diagram
G
A
I
N

Audio
In

DSP
(Filters,
IlLaw,
A Law)

ADC

DAC

DAC
Out

But In

ADCIN+---....I
XTLI
XTLO

But
Out

Select

PWRDN

ISA INTERFACE

It!

IQ I~ I~

Wavedec IS a trademark of Integrated elf CUlt Systems, Inc.

43

Is

II

ICS2002
Pin Descriptions
PIN
SD15 - SDO
SA1- SAO
CS*
10W*
IOR*
SBHE*
IOCSI6*
DRQP
DRQR
DACKP*
DACKR*
TC
IRQ
RESET
XTLI
XTLO
PWRDN*
AUDIOIN
ADCIN
DACOUT
BUFIN
BUFOUT
VDD
VDDA
VDDP
VSS
VSSA
VSSP

DESCRIPTION

TYPE
I/O
I
I
I
I
I
OC
0
0
I
I
I
0
I
I
0
I
AI
AO
AO
AI
AO
P
P
P
P
P
P

Data bus
Address
Chip select (active low)
Write strobe (active low)
Read strobe (active low)
System High Byte Enable (active low)
Indicates that the access register can sUJl£ort 16 bit transfer.
DMA Request (play channel)
DMA Request (record channel)
DMA Acknowledge (play channel)
DMA Acknowledge (record channel)
DMA terminal count
Interrupt request (active high, open drain)
Reset (active high)
Crystal oscillator
Crystal oscillator
Power down (active low)
Audio buffer input
Audio buffer output/input to ADC
DAC audio output
Uncommitted audio buffer input
U ncommited audio buffer output
Digital + 5V supply
Analog + 5V supply
Digital + 5V supply
DigitalGND
AnalogGND
DigitalGND

Package Pinout
44PinPLCC
lOW.
lOR.

6 5 4 3 2 0 oW 43 -42 41 40
7
1
3.

IOCS16.
IRQ

10

g~g~:~

S015
SOH
S013
S012
S011

ICS2002

13
15

,.
17

29
18192021 22232425262728

44

OACOUT
BUFIN
BUFOUT
RESET
VSS

S07
S06
S05
S04
S03
S02

Ordering Information
ICS2002V
ICS devices in PLCC packages
carry a 'V" designation.

ICS2002
Absolute Maximum Ratings
Supply Voltage ...................... -0.5V to 7.0V
Logic Inputs .................. -0.5V to VDD + 0.5V
Ambient Operating Temperature ....... 0° C to 70° C
Storage Temperature ............... _65° C to 150° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

Electrical Characteristics
VDD= 5.0V± lO%;GND= OV;TA= 0°Cto+70°C

DC/STATIC
PARAMETER
Digital Inputs
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Digital Outputs
Output Low Voltage (IOL = 4.0mA)
Output High Voltage (IOH = O.4mA)
Tri-State Current
Output Capacitance
Bi-directional Capacitance
Analog Inputs
Audio Input Voltage
Audio Input Impedance
Buffer Input Impedance
Audio Outputs
Audio Output Voltage
DACOUT, BUFOUT Output Impedance
Digital Supply Current
Analog Supply Current
Power Down Mode
Play Only Mode
II
Record Mode

SYMBOL

MIN

VIL
VIH
ILl
CIN

-0.3
2.0

VOL
VOH
Ioz

TYP

MAX

UNITS

0.8
VDD + 0.3
1
7

V
V

0.4

V
V

10
10
10

IlA
pF
pF

2.4

0.7

Vrms
ohm
ohm

500K
500K
0.7
lK
1
35
1
15
30

Icc 1
IDD2

45

IlA
pF

Vrms
ohm
rnA
rnA
rnA
rnA
rnA

I

II

ICS2002
Electrical Characteristics
VDD= S.OV± lO%;GND= OV;TA= O°C to+ 70°C

ACIDYNAMIC
PARAMETER
Address setup to command
Address hold from command
Command cycle time
Address valid to IIOCSI6 delay
IOCS16 hold from address invalid
Data valid to /lOW
/lOR active to valid data
Data hold after lIaR
Data hold after /lOW
IDACK setup to liaR
IDACK setup to IIOW
IDACK hold from command
ICS setup to command
ICS hold from command
TC setup to command inactive
TC hold from command

SYMBOL
tAS
tAH
tCCY
tAID
tm
tDS
tDAC
tDHR
tDHW
tDAR
tDAW
tDAH
tcs
tCH
tTS
tTH

MIN
10
10
100

TYP

MAX

SO
0
SO
60
0
10
30
SO
SO
10
10
2S
0

46

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

(I

ICS2002

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47

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o
en
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Timing Diagrams

DR Q

/0 A C K

/ lOR

/ lOW

~
/ CS

SO

SO

(READ)

(WRITE)

m=L

TC

DMA Cycle Timing

II

ICS2002
Power Management:
The POWERDN* input can be programmed to act as an
immediate hardware power control, or as an interrupt
source for a software driven power management routine.
The software driven option allows the driver to cleanly shut
down to chip, thus preventing unwanted noise. When active,
the power down function disables all analog components
including the oscillator, and causes the chip to enter a low
power mode.

Digital Audio Playback:
To play digital audio files, the chip is programmed for the
desired sample rate, data type, DMA channel width, and
output volume.
For DMA mode playback, DRQ generation is programmable for servicing the FIFO at several levels. This allows
optimal performance with a variety of hosts. When TC is
received, the chip will optionally generate an interrupt to
the host to indicate the need to service the D MA controller.

Miscellaneous Functions:
The chip has a full complement of status and control functions. All significant functions are capable of generating
interrupts and/or being polled.

For 110 Mode playback, data is written to the FIFO until it
is full. This is determined by polling the 'DIR" bit of the
status register. Once the FIFO is full, an interrupt will be
generated optionally at one of several selectable points: 114,
112, or 3/4 full. The host can then burst a predetermined
amount of data to the FIFO and wait for the next interrupt.

The DMA can be run in single or demand mode (for bursts
of data in programmed sizes).

Digital Audio Recording:
Audio recording operates in a DMA or 110 mode similarly
to audio playback with the audio input programmable as a
line or microphone level input. Simultaneous record and
playback is supported and permits the recorded file to be
synchronized to an existing file. The new and existing file
can then be mixed digitally for high quality results.
Data Processing:
To simplify the external circuitry associated with the analog
input and output signals of the chip, input and output sample
rates are oversampled. This allows simple RC filters to be
used.
For playback, the output data is oversampled, interpolated,
filtered and scaled. Since the DSP is fully programmable,
various sample rates and filter shapes can be implemented.
The processed data is then output to the DAC. The DAC
output passes through an analog volume control (4 bits,
1.5dB steps) before being passed to the analog filter stage.
For recording, the input data is first filtered, removing most
of the frequency content above the Nyquist frequency. The
resulting data stream is then undersampled to the desired
sample rate and fed into the FIFO for transfer to the host.

49

The FIFO has programmable interrupt and DMA request
capacities, and also indicates when overflow or underflow
conditions occur.
The processor interface is designed for simple connection to
the ISA bus. For best noise performance, isolating the data
lines from the ISA bus is recommended. In general, feed
through of digital noise is reduced by minimizing the load
which the digital outputs are driving.

I

ICS2002
Direct Register Descriptions
The base address is determined externally by an address
decoder which selects the chip via the CS* input.

Note that this register can only be read in STAND ALONE
mode. Hence, indirect access to this register has been provided at RA= 83h for use in COMPANION mode.
Register Address (RA) (Base + 1)
76543210

Status (Base + 0 read)

I I I I I I I I I

76543210

I I I I I I I I I

~~~
I

~ClearPlaylRQ

L - Clear Record IRQ
reserved
Power Down Mode IRQ
FIFO Overflow/Underflow IRQ
Sample Rate IRQ
FIFO Ready
IRQ (same as Pin)

This register is the indirect pointer to direct data transfers
to and from the data registers. It is a read/write register.
Note that this register can only be read if the chip is in
STAND ALONE mode.
Data Low Byte/Word (DLW)
76543210

I I I I I I I I I

IRQ Reset (Base + 0 write)
Data High Byte (DH) (Base + 3)

76543210

I I I I I I I I I

76543210

Lg:::;~~~~~~Q

~~~
~

reserved
Clear PDM IRQ
Clear FOU IRQ
ClearSR IRQ
reserved
reserved

This register provides the driver software easy access to the
interrupt source when read. Note that bit 7 indicates the
state of the IRQ pin, and hence will be zero when the MIE
bit is zero (see 'lnterrupt Enable" register).

I I I I "

I I I

These two addresses are used to accomplish all internal
register reading and writing. Most internal registers are
8-bit or less. These are accessed by fust writing the appropriate value to the DW, then writing (reading) the data byte
to (from) DLW.
I/O Mode FIFO data (RA= OBh), Algorithm RAM, and
Coefficient RAM are always treated as 16-bit entities, and
can be transferred in two ways:
a single operation to/from DLW with SBHE* = 0

A write to the register is performed to clear interrupts.
Writing a one to a given bit will cause the associated interrupt
to be cleared. To release the clear interrupt bit and allow
further interrupts to occur, a zero must be written back to
the bit of interest (some bits have alternate methods of
clearing described later). This feature ensures that if the
interrupt condition still exists, an edge will be generated on
the IRQ pin, thus ensuring recognition on platforms that are
edge sensitive. This also allows for a return from interrupt
instruction to be executed on the platform while the IR Q line
is inactive.

two successive operations, low byte to/from DLW
with SBHE* = 1, then high byte to/from DH.

Bit 6 is a special case. There is no IRQ associated with this
bit. It is located here for use in Sound Source Emulation
Mode, and represents the BUSY status of a Sound Source.
When the STATUS is read and tested with 40h, a zero result
indicates that the play FIFO is full.

50

(I

ICS2002

Indirect Register Map
Indirect
Address

Indirect
Address

Register

4E

Companion Select Register (write only)

80
81
82
83

Chip Control
Interrupt Enables
reserved
Interrupt status

84
85
86
87

Sample Rate Low 8 bits
Sample Rate High 4 bits
Sample Rate Control/Status
reserved

88
89
8A
8B

PlayDMA Control
PlayDMA Burst Count
PlayDMA Mode
DMA IO Mode Data Port

8C
8D
8E
8F

FIFO Enable/Status
FIFO IRQ Mode
reserved
reserved

90
91
92
93

Power Enable/Status
Power Mode
reserved
reserved

94
95
96
97

DSP Control/Status
DSP RAM Address Latch
Code RAM Data Port (8/l6 bit)
Data RAM Data Port (8/16 bit)

98
99
9A
9B

Record DMA Control
Record DMA Burst Count
Record DMA Mode
reserved
--

51

Register

9C
9D
9E
9F

Record FIFO Enable/Status
Record FIFO IRQ Mode
reserved
reserved

AO
Al
A2
A3

Digital Master Volume
DAC Deglitcher Control
reserved
reserved

A4
A5
A6
A7

ADC Control
Analog Volume/Mute
ADC Timing Control
reserved

I

ICS2002
Indirect Register Definitions
All writable bits/registers are also readable. In addition,
there are some read only bits/registers, which are noted
where appropriate.
Reserved bits should be written to zero, and read back
zeroes. Reserved registers should not be written or read.

Bit 1 - Chip STAND ALONE Mode
This bit sets the chip to operate in STAND ALONE
mode. In STAND ALONE mode, the STATUS and
RA registers are accessible at BASE+ 0 and
BASE+ 1. This mode should be used to speed register access when the IC2002 is being used by itself,
without other ICS chips sharing resources (such as
address decodes, interrupts, DMA channels, bus
buffers, etc.).

Except where noted, registers should be accessed as 8 bit
registers via address BASE+ 2.

When bit 1 is zero, the IC2002 will operate in COMPANION mode. In this mode, the STATUS register
is mapped only to indirect address 83h. This is done
to avoid conflict with other ICS chips that will provide
STATUS and RA read back at the first two base
addresses.

General Purpose Registers
IR4E Register Access Mode Select
This register must be written to Olh for any other
indirect (or direct) accesses to occur, except for RA
writes, which always occur based on chip select. This
indirect address allows multiple companion chips to
share resources in a system (such as bus buffers,
address decodes, interrupts, and DMA channels).

In addition, STAND ALONE mode configures the
DRQP, DRQR, and IRQ pins to operate as outputs,
with both one and zero levels being actively driven.
When in COMPANION mode, these pins have a
strong source for the high state and a weak sink for
the low state to allow wire-and connections to other
ICS chips.

This register is cleared only by hardware reset, and
in unaffected by MCR (see below).

This bit is reset by hardware reset only, not byMCR.

IR80 Chip Control
Bits 7:3 - reserved

Bit 0 - Master Chip Reset (MCR)
0- Hold chip in reset
1 - Remove reset
This bit is cleared to zero by a hardware reset. Thus,
any functions reset by MCR are also reset by the
RESET pin.

Bit 2 - Sound Source Emulation Mode (SSMODE)
This bit sets the chip to operate in Sound Source
Emulation mode. In Sound Source Emulation
Mode, the two address pins (SAl, SAO) are mapped
to match the PC parallel port as used by the Sound
Source as follows:
Chip Address
0
1
2
3

Sound Source
Data
Status
Control
unused

IC2002
DH
Status
DL
RA

To use this mode, the chip must be configured before
the Sound Source compatible application is run (lIO
Mode DMA, DSP loaded and running, SR running,
etc.) Then, the IC2002 is put in SSMODE and RA
(now at address 3) is written to 8Bh. In the PC, the
BIOS pointer to the parallel port is changed to the
base address of the IC2002 chip, and the application
can then be started.
This bit is reset by MCR. Hence, it must be set after
MCR is set, on a second write to this register.

52

II

ICS2002

IR81 Interrupt Enables
Bit 7 - Master Interrupt Enable (MIE)
In the zero state, this bit prevents the IR Q pin from
going active (high) regardless of the state of any of
the individual interrupt sources. It is cleared to zero
by MCR. A zero in this bit does not prevent an
individual interrupt source from being active in the
STATU S register. This allows interrupts to be
masked while allowing their status to be polled.
Bit 6 - reserved

Sample Rate Generator Registers
IR84 Sample Rate Low 8 bits (SRL)
Bits 7:0 - Sample Rate Bits 7:0
IR8S Sample Rate High 4 bits (SRH)
Bits 3:0 - Sample Rate Bits 11:8
Together, these two registers define the record and
playback sample rate. Based on the crystal frequency FXtal, and a 12 bit value SR (the concatenation of the two registers), the sample rate will be:

Bit 5 - Sample Rate Interrupt Enable (SRIE)
Sample Rate

Bit 4 - FIFO Overflow/U nderflow Interrupt
Enable (FOurE)

=

FXtal

* SR 1524288

These registers are not initialized by anyofthe reset
mechanisms. Note that the Sample Rate Counter
should always be stopped via SRCS bit 0 when these
two registers are changed.

Bit 3 - Power-down Mode Change Interrupt
Enable (PMCIE)
Bit 2 - reserved

IR8S Sample Rate Control/Status (SRCS)
Bits 7:2 - reserved

Bit 1 - Record FIFO Interrupt Enable (RFIE)
Bit 0 - Play FIFO Interrupt Enable (PFIE)
Each of these bits individually enables, one, or disables, zero, their respective interrupt sources from
being active in the STATUS register. In addition,
there will be no IRQ generated if MIE is one when
an individual enable bit is zero. The state of this bit
does not affect the source of these interrupts in any
way, and they may be polled for activity in the appropriate register for each interrupt type. These bits are
all cleared to zero by MCR.

Bit I - Sample Rate Interrupt (SRIRQ) - Read Only
This is set by the hard ware whenever the sample rate
counter overflows, indicating that a new sample is
being input or generated. This bit is cleared by any
of the following actions:
- Master Chip Reset
- Sample Rate Run = 0 (SRR bit 0)
- a write to STATUS with bit 5 = 1
- any write to SRCS

IR83 Status
This register is the same as the direct access status register,
except that it can be read in COMPANION mode.

Bit 0 - Sample Rate Run (SRR)
This bit resets the Sample Rate Counter, the SRIR Q
bit, and shuts down the sampling and playback processes when written to a zero. When written to a one,
the sample rate generator runs at the programmed
rate. SRR is internally synchronized to the master
clock to provide clean starts and stops of the counter.
MCR clears this bit.

53

I

ICS2002
Play DMA Control and Status Registers
IR88 Play DMA Control (DMACTL)
Bits 7 - reserved
Bit 6 - TC Reset Mask
When sct to I, this bit masks the 'DMA Run'bit reset
upon receipt of TC, terminal count, signal from the
ISA bus. When reset to 0, the 'D MA Run' bit will be
reset upon receipt of TC.
Bits 5: I - reserved
Bit 0 - DMA Run
This bit enables the DMA hardware to begin transferring data when set to one. It is cleared by either
MCR or receipt of a TC when 'TC Reset Mask' is a
zero (see the DMAMODE register for details).

IR89 Play DMA Burst Count (DMABC)
Bits 7:6 - reserved
Bits 5:0 - DMA Burst Count
This value determines the number ofDMA transfers
that take place for each DMA request issued to the
host. The actual number of transfers will be
DMABC+ I. Thus, for single transfer mode, program this register to zero. The burst counter is automatically preset to the burst count whenever the
DACKP* input is high. Thus, there is no need to
reprogram the count value after TC, since the next
transfer will use the full programmed count value.
This register has no affect on I/O Mode data transfers, since its only influence is over the DR QP output.
This register is not initialized by any means other than
a direct write, and hence must be written to before
DMA is enabled.

Bit 4 - I/O Mode Transfer (IOXFER)
When this bit isaone, the DMA hardware (DRQP and
TCIRQ) is disabled. Data transfers take place via
IR8Bh, and are required to be treated as 16 bit transfers. Thus, data should be written to DLW (with
SBHE* = low, 16 bit data) or to DLW (with SBHE*
= high, 8 bit data low byte) followed byDH (8 bit data,
high byte). It is also the programmers responsibility to
ensure that D MAM 0 DEbit 2 (D MA 16) is set to a one
for all I/O mode transfers.
Bit 3 - Unsigned Data (USIGN)
When set to a one, this bit expects to receive (and will
generate) unsigned data. The native data format is
Signed Binary Twos Complement. This bit will invert
the most significant bit of each data byte (or word,
depending on the state of DATATYPE). Note that
this bit should be zero when the DATATYPE indicates u-law or A- law data formats.
Bit 2 - 16 Bit Data (DMAI6)
When set to a one, this bit causes the hardware to
expect data to be sent in 16 bit words. When low, the
hardware expects 8 bit bytes. This bit must be set to
one when performing 110 mode transfers, as all I/O
transfers are treated as 16 bit values.
Bit 1:0 - Data Type (DATATYPE)
These bits direct the hardware how to interpret the
outgoing data. This is independent of the DMA or
I/O data width. It effects how data is signed and how
data is packed to and unpacked from the Play FIFO.
The DATATYPE field selects the format of data for
playback.
Value
00
OJ

IR8A Play DMA Mode (DMAMODE)
All bits in this register are cleared by MCR.

10
II

Data Type
8 bit linear
16 bit linear
8 bit 11256 Law
8 bit A-Law

Bits 7:6 - reserved
Bit 5 - Terminal Count Interrupt (TCIRQ) - (read only)
This bit indicates that a Terminal Count has been
received on the last DMA operation. If the PFIE and
PLAYIRQ bits have been programmed to a one, an
interrupt will be generated at the end of the last
DMA operation. This bit is cleared by MCR or a
write to STATU S with bit 0 = one. The reset state is
then removed by either writing the STATUS bit 0 to
zero.

IR8B DMA 1/0 Mode Data Port (DMADATA) (8/16 bit)
This register address is used to trap 110 mode data
to and from the FIFOs. It is only used in I/O mode.
See the description of the 10XFER bits for more
details.
When DMAI6 is one, this register MUST be accessed as a sixteen bit value. Note that this can be
done from either an eight or sixteen bit ISA slot, since
the chip used SBHE * to determine the proper byte
swapping.

54

II

ICS2002
IR8D FIFO IRQ Mode
This register must never be written to when the FIFO is
enabled. Invalid interrupts and DMA requests could be
generated as a result.

FIFO ControVStatus Registers
IR8C FIFO Enable/Status (FES)
Bit 0 - FIFO Enable (FE)
This bit holds the FIFO in a reset state when low, and
enables the FIFO to operate when high. This bit is
reset by MCR. This bit, when low, also resets all
FIFO related conditions (see the following bits) and
prevents DMA start requests from being issued. It
does not reset the FIFO IRQ Mode register.

Bits 7:4 - reserved
Bit 3 - FIFO IRQ Enable (FIE)
This bit enables the various FIFO capacitythresholds
to generate interrupts (as PLAYIRQ) when one.
When zero, this bit prevents FIFO capacity IRQ
generation when operating in DMA mode, which
only needs TCIRQ.

Bit I - FIFO Overflow (read only)
This bit is set when a FIFO shift in command is
generated (byeither DMA, 110, or the DSP) with the
FIFO full, and indicates an error condition. This bit
will cause the FOUIRQ bit to go active, generating
an IRQ if enabled. This bit is reset by writing to
STATUS with bit 4= I, and re-enabled by writing to
STATUS with bit 4 = ,0. FE low also resets this bit.

Bits 2:0 - FIFO Ready IRQ Mode Selection
This field defines FIFO utilization for both DMA and
110 mode data transfers. In 1/0 mode, it is used to
generate interrupts (FRDYIRQ) when the FIFO capacrtyreaches a predefmed point. For DMA transfers, it signals the DMA logic to request a transfer at
those same predefined points. By programming the
DMA Burst Count appropriately, the FIFO may be
easily kept near the desired capacity.

Bit 2 - FIFO Underflow (read only)
This bit is set when a FIFO shift out command is
generated (by either DMA, 1/0, or the DSP) with the
FIFO empty, and indicates an error condition. This
bit will cause the FOUIRQ bit to go active, generating an IRQ if enabled. This bit is reset by writing to
STATUS with bit 4= 1, and re-enabled by writing to
STATUS with bit 4 = O. FE low also resets this bit.

The following table describes the selections available:

Bit 3 - FIFO 25% Full (read only)
This bit goes high after 4 words (or 8 bytes) have been
loaded into the FIFO, and low again when 13 words
(or 26 bytes) maybe loaded into the FIFO. There is
no interrupt associated with this bit directly.
Bit 4 - FIFO 50% Full (read only)
This bit goes high after 8 words (or 16 bytes) have
been loaded into the FIFO, and low again when 9
words (or 18 bytes) may be loaded into the FIFO.
There is no interrupt associated with this bit directly.

IRQIDRQ
Source

000
001

DIR
EMPTY 75%

010

EMPTY 50%

011

EMPTY 25%

100

DOR
FULL 25%
FULL 50%
FULL 75%

101
110
111

Bit 5 - FIFO 75% Full (read only)
This bit goes high after 12 words (or 24 bytes) have
been loaded into the FIFO, and low again when 5
words (or 10 bytes) may be loaded into the FIFO.
There is no interrupt associated with this bit directly.
Bit 6 - FIFO DIR (read only)
This bit goes high when a single word (or two bytes)
may be written to the FIFO. There is no interrupt
associated with this bit directly. Note that this bit
resets to a one because when the FIFO is reset it is
forced to be empty, and hence is ready to accept data.

Bits
2:0

Notes
Ready to take I word from HOST
Ready to take 13 words from
HOST
Ready to take 9 words from
HOST
Ready to take 5 words from
HOST
Ready to provide 1 word to DSP
Ready to provide 4 words to DSP
Ready to provide 8 words to DSP
Ready to provide 12 words to
DSP

Note that for byte transfers (D MA 16= 0), the numbers listed
above should be doubled.
This must be programmed before the FIFO is enabled. It
may be changed while the FIFO is enabled, ifnecessary. This
register is cleared by MCR, but not by FE low.

Bit 7 - FIFO DOR (read only)
This bit goes high when a single word (or two bytes)
may be read from the FIFO. There is no interrupt
associated with this bit directly.

ss

I

ICS2002
IRSE reserved
IRSF Play FIFO Output Data Read Back (8116 bit)
This register is provided for test use only, although it may
fmd system level use as a diagnostic tool.

Bit 1 - RISEIRQ (read only)
This bit is set when the PWRDN* pin makes a transition from low to high. If PWRMODE bit 1
(RISElE) is one, this will cause PWRIRQ to go high
as well. This bit is reset by one of the following:
-MCR
- any write to PEST
- a write to STATUS with bit 3 set to one. This will
hold the bit reset until released by a write to
STATUS with bit 3 cleared to zero.

Power Control and Status
IR90 Power Enable/Status (PEST)
Bit 7 - PWRIRQ (read only)
This bit is a one when either edge has occurred on
the PWRDN* pin, and the edge enable in the Power
Mode register is set. If bit 3 of the MIE is one, this
will also generate an external interrupt. In any case,
this bit is also visible as STATUS register bit 3.
PWRIRQ is reset by disabling both edge enable bits
or resetting the edge interrupts (see below).

Bits 6:5 - reserved
Bit 4 - ADCPWR Disable
This bit controls the power state ofthe ADC analog
circuitry. When 0, ADC analog power is controlled
by the SOFTPWR bit the same as the DAC analog
power is. When this bit is set to a 1, the ADC analog
power is turned off independent of the state of
SOFTPWR.
This feature is included for advanced power management routines, as chip power dissipation can be reduced by almost halfby turning ADC power off when
not in use. Note, however, that several milliseconds
of settling time is required after power is turned on
before the ADC functions properly.
Bit 3 - PWRDN* Pin Value (read only)
This bit indicates the state of the PWRDN* pin.
Bit 2 - FALLIRQ (read only)
This bit is set when the PWRDN* pin makes a transition from high to low. IfPWRMODE bit 2 (FALLIE) is one, this will cause PWRIRQ to go high as
well. This bit is reset by one ofthe following:
-MCR
- any write to PEST
- a write to STATU S with bit 3 set to one. This will
hold the bit reset until released by a write to
STATUS with bit 3 cleared to zero.
Note that FALLIE does not mask this bit, allowing
polling to be performed.

Note that RISEIE does not mask this bit, allowing
polling to be performed.
Bit 0 - Soft Power (SOFTPWR)
The function of this bit depends on the status of the
"SWMODE" bit (bit 0 of PWRMODE). When
SWMODE is zero, writes to this bit have no affect.
Reads will return the state of the PWRDN* pin,
which is also the state ofthe on chip PWR 0 N control
signal. When SWMODE is a one, a write of one to
this bit turns on power to the chip analog circuitry,
while a zero clears this bit and puts the chip in a low
power mode. Reads will return the last value written.
IR91 Power Mode (PWRMODE)
All bits in this register are cleared byMCR.

Bits 7:3 - reserved
Bit 2 - Fall IRQ Enable (FALLIE)
When set to one, this bit allows a falling edge on
PWRDN* to cause PWRIRQ to go high. It does not
mask PEST bit 2.
Bit 1 - Rise IRQ Enable (RISEIE)
When set to one, this bit allows a rising edge on
PWRDN* to cause PWRIRQ to go high. It does not
mask PEST bit 1.
Bit 0 - Software Mode (SWMODE)
When cleared to zero, this bit causes the chip to
operate in a ''hardware driven" mode; that is, the
PWRDN* pin directly controls the chip analog
power (for low power consumption). In this mode, a
low on PWRDN* puts the chip in low power mode,
while a high enables normal operation. When set to
a one, this bit causes the chip to operate in a "software
driven" mode. In this mode, changes on the
PWRDN* pin only generate interrupts. The hardware low power mode is then controlled (via software) by SOFTPWR (bit oof PEST). This function
allows "clean" software controlled turn on and off of
the analog circuitry power.

56

II

ICS2002

IR92 reserved

ICS will provide algorithm and constants data supporting
filtering functions for various sample rates.

IR93 reserved

Note that when the DSP is running, it is forbidden to read or
write either the Code or Data RAMs (except when halted in
STEP mode, see above). Also, after writing to the Code or
Data RAMs to load them, and before starting the DSP, you
must reset the RAM load hardware by writing to the DSPRA
re gister (the value written is ignored).

IR94 DSP Control/Status (DSPCS)
Bits 7:4 - Index Counter Value (Read Only)
This value indicates the current contents of the DSP
address Index Counter, and is provided as a code
debug aid for use in Step Mode. In normal operation
it should be ignored. It is reset to zero when the DSP
is not running, and increments by one at the completion of each "pass" of the DSP engine.

IR95 DSP RAM Address Latch (DSPRA) (write only)
Bit 7 - Read
When one, this bit indicates that the next DSP RAM
operation is a read. Zero indicates a write operation.

Bit 3 - DSP Sequence Complete (Read only)
This bit is set each time the DSP completes its sequence and restarts. It is reset to zero when the
DSPR UN bit is zero or after a read of this register.

Bits 5:0 - DSP RAM Address
These bits are the address for the next DSP RAM
data transfer. Note that the Code RAM address can
be $00 through $3f, and the Data RAM address can
be $00 through $IF.

Bit 2 - DSP Output Saturation Detect
This bit is set to one whenever the DSP output value
written to any output destination (DATA RAM,
DAC, or Record FIFO) exceeds a sixteen bit signed
range. In these cases, the D SP output saturates to
$7FFF or $8000 (for positive or negative values)
rather than overflowing. It is reset to zero when the
DSPRUN bit is zero or after a read ofthis register.

IR96 Code RAM Data Port (8/16 bit)
Bits B:O - Code RAM Data
This 8116 bit port is data to be read from/written to
the DSP Code RAM. The data is the low 12 bits of
the word.

Bit I - DSP Step Mode
This bit is intended as a DSP code debug aid only.
When set to a one, this bit halts the DSP microcode
sequencer at the end of each "pass" of code. This
enables the host to read the DATA RAM contents to
check the results of the previous calculations. Note
that writes to the Record FIFO and DAC will be
captured by the DATA RAM "under"them to aid with
debug efforts. For normal operation, this bit MUST
be set to a zero.

IR97 Data RAM Data Port (8/16 bit)
Bits F:O - Data RAM Data
This 8116 bit port is the data to be read from/written
to the DSP Data RAM. The data is a full 16 bit word.

Record DMA Control and Status Registers
IR98 Record DMA Control (DMACTL)
Bits 7 - reserved

Bit 0 - DSP Run
When written to one, this bit starts the DSP engine
running. A zero stops and resets the DSP engine
execution. This bit is reset by MCR.
Before running the DSP, the Code and Data RAMs must be
loaded. To do this, perform the following:

Bit 6 - TC Reset Mask
When set to 1, this bit masks the 'D MA Run' bit reset
upon receipt of TC, terminal count, signal from the
ISA bus. When reset to 0, the 'DMA Run' bit will be
reset upon receipt ofTC.

I) write 95h (DSPRA) to the desired address
2) write 96h (Code Ram data) or 97h (Data RAM data) to
the desired 16 bit value.
3) repeat 1 and 2 for all RAM locations of both RAMs.
4) when done, write any data to DSPRA to reset the load
logic.

Bit 0 - DMA Run
This bit enables the DMA hardware to begin transferring data when set to one. It is cleared by either
MCR or receipt of a TC when 'TC Reset Mask' is a
zero (see the DMAMODE register for details).

Bits 5: 1 - reserved

57

11

ICS2002
IR99 Record DMA Burst Count (RDMABC)
Bits 7:6 - reserved

Bit 2 - 16 Bit DMA (RDMAI6)
When set to a one, this bit causes the hardware to
expect data to be sent in 16 bit words. When low, the
hardware expects 8 bit bytes. This bit must be set to
one when performing I/O mode transfers, as all I/O
transfers are treated as 16 bit entities.

Bits 5:0 - Record DMA Burst Count
This value determines the number ofDMA transfers
that take place for each DMA request issued to the
host. The actual number of transfers will be
RDMABC + 1. Thus, for single transfer mode,
program this register to zero. The burst counter is
automatically preset to the burst count whenever the
DACKR * input is high. Thus, there is no need to
reprogram the count value after TC, since the next
transfer will use the full programmed count value.
This register has no affect on I/O Mode data transfers, since its only influence is over the DRQR output. This register is not initialized by any means other
than a direct write, and hence must be written to
before DMA is enabled.

Bits 1:0 - Record Data Type (RDATATYPE)
These bits direct the hardware how to interpret the
incoming data. Note that this is independent of the
DMA or I/O data width. It effects how data is
"signed" and how data is packed to/unpacked from
the Record FIFO.
Value
00
01
10
11

IR9A Record DMA Mode (RDMAMODE)
All bits in this register are cleared by MCR.

Data Type
8 bit linear
16 bit linear
reserved
reserved

IR9B reserved

Bits 7:6 - reserved
Bit 5 - Terminal Count Interrupt (RTCIRQ) (read only)
This bit indicates that a Terminal Count has been
received on the last DMA operation. If the RECIE
bit has been programmed to a one, an interrupt will
be generated at the end of the last D MA operation.
This bit is cleared byMCR or a write to STATUS with
bit I = I. The reset state is then removed by either
writing the STATUS bit 0 to 0, or by the next DMA
operation. Hence, there is no need to "remove" this
reset as there is for other IR Q reset operations.

Record FIFO Control/Status Registers
IR9C Record FIFO Enable/Status (RFES)
Bit 0 - Record FIFO Enable (RFE)
This bit holds the record FIFO in a reset state when
low, and enables the FIFO to operate when high.
This bit is reset by MCR. This bit, when low, also
resets all FIFO related conditions (see the following
bits) and prevents DMA start requests from being
issued. It does not reset the Record FIFO IRQ Mode
register.

Bit 4 - Record I/O Mode Transfer (RIOXFER)
When this bit is a one, the DMA hardware (DRQR
and RTCIRQ) is disabled. Data transfers take place
via RA $8B (NOT $9B), and are required to be
treated as 16 bit transfers. Thus, data should be read
from DLW (with SBHE* = 0, 16 bit data) or from
DLW (with SBHE* = 1,8 bit data low byte) followed
by DH (8 bit data, high byte). It is also the programmers responsibility to ensure that RDMAMODE bit
I (RDMAI6) is set to a one for all I/O mode transfers.

Bit 1 - FIFO Overflow (read only)
This bit is set when a FIFO shift in command is
generated (by either DMA, I/O, or the DSP) with the
FIFO full, and indicates an error condition. This bit
will cause the FOUIRQ bit to go active, generating
an IRQ if enabled. This bit is reset by writing to
STATU S with bit 4 = I, and re-enabled by writing to
STATU S with bit 4 = O. FE low also resets this bit.
Bit 2 - FIFO Underflow (read only)
This bit is set when a FIFO shift out command is
generated (byeither DMA, I/O, or the DSP) with the
FIFO empty, and indicates an error condition. This
bit will cause the FOUIRQ bit to go active, generating an IRQ if enabled. This bit is reset by writing to
STATUS with bit 4 = 1, and re-enabled by writing to
STATUS with bit 4 = O. FE low also resets this bit.

Bit 3 - Unsigned Data (RUSION)
When set to a one, the record FIFO will generate
unsigned data. The native data format is Signed
Binary Twos Complement. This bit will invert the
most significant bit of each data byte (or word, depending on the state ofRDATATYPE).

58

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ICS2002

Bit 3 - FIFO 25% Full (read only)
This bit goes high after 4 words (or 8 bytes) have been
loaded into the FIFO, and low again when 5 words
(or 10 bytes) maybe loaded into the FIFO. There is
no interrupt associated with this bit directly.

The following table describes the selections available:

Bits
2:0
000
001
010
Oil

Bit 4 - FIFO 50% Full (read only)
This bit goes high after 8 words (or 16 bytes) have
been loaded into the FIFO, and low again when 9
words (or 18 bytes) may be loaded into the FIFO.
There is no interrupt associated with this bit directly.
Bit 5 - FIFO 75% Full (read only)
This bit goes high after 12 words (or 24 bytes) have
been loaded into the FIFO, and low again when 13
words (or 26 bytes) may be loaded into the FIFO.
There is no interrupt associated with this bit directly.
Bit 6 - FIFO DIR (read only)
This bit goes high when a single word (or two bytes)
may be written to the FIFO. There is no interrupt
associated with this bit directly. Note that this bit
resets to a one because when the FIFO is reset it is
forced to be "empty", and hence is read y to accept data.

100
101

Source
DIR
EMPTY 75%
EMPTY 50%
EMPTY 25%
DOR
FULL 25%

110

FULL 50%

III

FULL 75%

Notes
Ready to take 1 word from DSP
Ready to take 13 words from DSP
Ready to take 9 words from DSP
Ready to take 5 words from DSP
Ready to provide I word to HOST
Ready to provide 4 words to
HOST
Ready to provide 8 words to
HOST
Ready to provide 12 words

Note that for byte transfers (RDMAI6= 0), the numbers
listed above should be doubled.
This must be programmed before the FIFO is enabled. It
may be changed while the FIFO is enabled if necessary. This
register is cleared by MCR, but not by RFE low.

Bit 7 - FIFO DOR (read only)
This bit goes high when a single word (or two bytes)
may be read from the FIFO. There is no interrupt
associated with this bit directly.

IR9E reserved
IR9F reserved

IR9D Record FIFO IRQ Mode
Bits 7:4 - reserved

Miscellaneous Registers

Bit 3 - FIFO IRQ Enable (RFIE)
This bit enables the various FIFO capacity thresholds
to generate interrupts (as RECIRQ) when one.
When zero, this bit prevents FIFO capacity IRQ
generation when operating in DMA mode, which
only needs RTCIRQ.

IRAO Digital Master Volume
Bits 7:0 - Volume
This value is used to scale all values that are output
from the DSP to the DAC. It may be written while
the DSP is running.

Bits 2:0 - FIFO Ready IRQ Mode Selection
This register defines FIFO utilization for both DMA
and I/O mode data transfers. In 110 mode, it is used
to generate interrupts (RECIRQ) when the FIFO
capacity reaches a predefined point. For DMA
transfers, it signals the DMA logic to request a transfer at those same predefined points. By programming the Record DMA Burst Count appropriately,
the FIFO maybe easilykept near the desired capacity.

The value written is interpreted as to give a log scale
output response of 0.1 875dB per step. The value for
nominal (OdB attenuation) is EOh. A value of FFh
gives 5.8125dB of gain. Note that any value above
EOh may result in digital saturation ofthe internal 16
bit data value.

59

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ICS2002
IRA1 DAC Deglitcher Control
Bits 7:3 - Volume bits 7:3 (read only)

Note that this bit, when 0, shuts down the successive
approximation logic, the dynamic comparators and
various logic functions. When the ADC is not being
used, disabling it via this bit reduces background
noise in the playback section and power consumption, and thus is recommended.

Bit 2 - DAC Enable Bit (read only, for test)
Bits 1:0 - DAC Deglitch Width

Code
00
01
10
II

Notes
.Deglitcher disabled
I

II

IRAS Analog Volume/Mute
Bits 7:5 - reserved

~

Bits 4: 1 - Analog Volume
These bits set the analog output level, in 1.5dB steps.
All bits one gives OdB attenuation of the DAC output
signal, and all bits zero gives full attenuation. These
bits are unaffected by any reset mechanism.

This value is determined by the clock rate at which
the chip is run, ICS will provide the proper value for
an application. This register is also used for test
purposes.

Bit 0 - Audio Enable
This bit disconnects the audio output of the output
buffer amp and sets the BUFOUT pin to the nominal
bias voltage when cleared to zero. When set to one,
it passes the output of the output buffer amp to the
BUFOUTpin.

Minimum deglitch width
Nominal de glitch width
Maximum de glitch width

-

This register is not initialized in any way and should
be programmed before muting is removed.

The main function ofthis bit is to prevent sudden DC
offset changes on the BUFOUT pin when entering
and leaving power-down mode. Byproper software
procedure, noiseless transitions can be made.

IRA2 reserved
IRA3 reserved

This bit is cleared to zero by MCR.

ADC and Analog Control Registers
IRA4 ADC Control
Bits 7:3 - reserved
Bit 2 - ADC Test Mode
This bit is for factory testing use only, and must always
be programmed to zero by an application. It is reset
to zero by a zero in ADCRUN, and hence takes two
writes of $05 to this register to activate for safety.
Bit 1 - reserved
Bit 0 - ADC Run
When written to a one, this bit enables the ADC
hardware to run. Note that the ADC Timing Control
register should be programmed appropriately first.
Also note that the D SP must be running (and programmed properly) for the conversion results to be
retrieved. The Sample Rate Generator determines
the rate at which the conversion data is loaded into
the Record FIFO.

IRA6 ADC Timing Control
This register is used to control the ADC internal
operation timing.
Bits 7:4 - Comparator Timing Control
These bits control the time of comparator input
switching. Bits 7:5 are the count, and bit 4 is 0 for half
cycle and 1 full cycle delays.
Bits 3: 1 - Cycle Timing Control
These bits control the number of clocks used for each
step of the successive approximation process. For
the full 64 step D SP cycle, the value of these bits
should be 7. For a 40 step cycle, the value should be 4.
Bit 0 - reserved

IRA7 reserved

This bit is cleared to zero byMCR.

60

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ICS2008

Integrated
Circuit
Systems, Inc.

SM PTE Time Code Receiver/Generator
General Description

Features

The ICS2008, SMPTE Time Code Receiver/Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the ICS2008 is easily integrated into products requiring SMPTE time code generation and/or reception in LTC (Longitudinal Time Code)
and/or VITC (Vertical Interval Time Code) formats and
MTC (MIDI Time Code) translation.

•

Internal and external sync sources
Genlock to video or house sync inputs
- internally generated timing from oscillator input
- external click input

•

LTC and VITC Generators
- Real Time SMPTE Rates
• 30 Hz (B&W, some audio)
• 29.97 Hz (NTSC)
• 25 Hz (PAL)
• 24 Hz (film)
- Time Code Modes
• Drop Frame
• Color Frame
- VITC can be inserted on two lines from 10-40
(SMPTE specifies lines 10-20)

Taking its input from composite video, S-Video, or an audio
track, the ICS2008 can read SMPTE time code in VITC and
LTC formats. Time code output formats are LTC and
VITC. All are available sImultaneously. A UART is provided for the user to support MTC or tape transport control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors.

- Update all data (time code, user data, and flag bits)
on a frame-by-frame basis. This allows for
"Jam Sync," "freewheeling," error bypass/correction,
plus-one-frame, and other intelligent generator
functions.

Block Diagram

•

LTC Receiver
- Meets SMPTE and EBU LTC specifications including drop frame, color frame, time data, user data
and status bits.
- Synchronize bit rates from 1/30th nominal to 80X
nominal playback speed.

VIDEO IN1
VIDEO IN2
VIDEO OUT

•

VITC OUT
LTC IN
LTC OUT
TACH IN
PC
BUS

VITC reader
- Reads code from any or all selected scan lines.
- Meets SMPTE VITC specifications including drop
frame, color frame, time data, user data and status
bits

MIDI

•

61

Time Code Burn-in Window selectable to overlay
video with programmable screen position

I

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ICS2008
Package Pinout

LTCOUT
LFC
XTAL2
XTAL1
AVDD
AVSS
COUT
YOUT
C2
Y2
C1

6 5

4

3

2

D2
01

7
8

D0

9

IOW*
VDD
VSS
IOR*
UARTSC*
SMPTECS*
A1
A0

Ordering Information:
All ICS devices in PLCC packages carry a "V" designation.
Example: ICS2008V

62

ICS2008
Pin Description
PIN

TYPE

Yl, Y2

AI

Video inputs from camera or other NTSC source. NOTE: This is also the Y (Luma)
input for S-VHS and HI-8 systems.

Cl,C

AI

C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this pin should be
tied to its respective Y input.

DTHRESH
STHRESH
CTHRESH

AI
AI
AI

Data Threshold bypass input.
SYNC Threshold bypass input.
Clamp Threshold bypass input.

DESCRIPTION

YOUT
COUT

AO
AO

NTSC video output. This is also the Y (Luma) output in S-Video mode.
C (Chroma) output for S-VHS and HI-8 systems.

FRAME
CLICK
LTCIN+
LTCINLTCOUT

AI
AI
AI
AI
AO

Color Frame AlB input. This input is self biased. (See Applications section.)
LTC SYNC input. This input is self biased. (See Applications section.)
SMPTE LTC inpuH . This input is self biased. (See Applications section.)
SMPTE LTC input-. This input is self biased. (See Applications section.)
SMPTE LTC output.

LRCLK

0

SMPTE LTC receive clock output.

VITC
VITCGATE

0
0

SMPTE VITC output to video mixer circuit.
VITC gate indicates VITC code is being output for video overlay.

TxD
RxD
CTS*
RTS*

0
I
I
0

UART Transmit Data.
UART Receive Data.
Clear to Send.
Ready to Send.

XTALl
XTAL2
LFC

I
0
AI

AI-AO
IOR*
IOW*
SMPTEC*
UARTCS*
RESET
D7-DO
INTR

I
I
I
I
I
I

A -Analog
P -Power

0

Address bus
Read Enable (active low)
Write Enable (active low)
SMPTE port chip select (active low)
UART chip select (active low)
Master reset (active high)
Bi-directional data bus
Interrupt Request (active high)

P
P
P
P

AnalogVDD
Analog Ground
Digital VDD
Digital Ground

1/0

AVDD
AGND
VDD
GND

14.318 MHz crystal input. This pin maybe driven directly from a TTL 14.318 MHz source.
14.318 MHz crystal scillator output.
External RC circuit.

I-Input

o -Output

63

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ICS2008
Video Output
The video output combines the selected video input with the
outputs from the VITC generator and the character generator. It can be a composite or an S-Video output as selected
by the SVID bit in the SMPTE control registers.

Functional Description
The following is a functional description of the hardware
registers in the ICS2008 chip. It also describes how those
registers can be utilized by the software to facilitate specific
application services.

VITC code is generated from data in the VITC generator
buffer and output during the selected line time( s). The CRC
and synchronizing bits are automatically generated by the
VITC generator, but all of the data fields are sent directly
from the buffer with no modification.

Hardware Environments
The ICS2008 operates as a peripheral to a processor such
as a PC or a single chip microprocessor. Many of the real
time requirements are satisfied by double buffering both
incoming and outgoing time codes.

A character generator is provided to insert the time code in
a burn-in window which overlays the incoming video. The
vertical and horizontal position of the burn-in window is
programmable.

LTC Input
LTCIN is a differential analog input feeding a comparator
with hysteresis. It requires capacitive coupling to the LTC
source. The output of the comparator goes to the LTC
receiver, which is capable of receiving LTC in a forward or
backward direction at a rate from 1/30th to SOx nominal
frame rates. The incoming LTC data is sampled with a
phase-locked clock and loaded into the receive buffer following the receipt of a valid LTC SYNC pattern. When a
complete frame has been received, an interrupt is generated.

MIDI Port
A UART is provided for a MIDI port. It can function as a
MIDI IN and a MIDI OUT. It can generate an interrupt on
receiver full and/or transmitter empty to the processor via
the INTR pin. CTS and RTS modem controls are provided
so that it can be used as a generic serial control port.
SM PTE SYNC Sources
A time code generator must have a SYNC input from a
stable source in order to position the LTC code properly on
a audio track of video tape or film. Three SYNC sources,
video, click input, and free running, are available. In the
case of a video tape, LTC code must start within plus or
minus one line of the beginning of line 5. This requires
"Genlocking" to the incoming video. The video timing section locks to the video's horizontal and vertical SYNC signal
and generates a SMPTE SYNC. If some external SYNC
source is available it can be input on the CLICK input.
Otherwise, a free running SMPTE SYNC is generated from
the oscillator at the selected frame rate.

LTC Output
The LTC output can be analog or digital. When set up as an
analog output, it can drive a high impedance load.

The LTC generator outputs a LTC frame at the selected
frame rate, such as 24Hz, 25Hz, 29.97Hz or 30Hz, and starts
the frame based on a start time generated by the selected
LTC SYNC source.
Video Inputs
There are two sets of video inputs. In a composite NTSC or
PAL system, the Y input is the only one used. It is capacitively coupled to the source. In S-Video systems, capacitively couple Y and C to their respective sources. Proper
termination of the source should be observed. One of the
two video sources is selected by the VIDSEL bit in the
SMPTE control registers as the video SYNC source. Internal timers are synchronized with the incoming video to
extract timing information used to receive and generate

Video Timing Generator
The video timing generator is "Genlocked" to the video
input's SYNC separator. It extracts NTSC or PAL timing
information from the video input and generates line and
pixel rate timing for the VITC receiver, VITC generator,
LTC generator and character generator. If no video input
is present, it generates free running timing.

VITe.

The VITC receiver samples the incoming video looking for
a valid VITC code on selected scan lines. When a valid code
is received it is written to a VITC receive buffer. More than
one line can contain VITC code, and the codes can be
different. For this reason, VITC codes from selected lines
of a frame are written to separate VITC buffers.

64

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ICS2008

Overlay Character Generator
It is sometimes desireable to display the time code on a video
display along with the picture. A character generator is
provided for that purpose. The time code display, or burnin window, can be positioned anywhere on the screen.
INTR Output
The INTR output pin is the interrupt source from ICS2008
to the processor. Each interrupt source has its own interrupt enable and interrupt status.

The SMPTEO Register contains the SMPTE interrupt controls and status and the VITC read status. The three interrupt bits, LRI, LXI, VLI and TMI reflect the status of the
potential interrupt sources to the processor. When a bit is
set to one and the corresponding enable bit, LRIEN,
LXIEN or VLIEN, is also set, the INTR output will be
activated. Interrupts are cleared by reading SMPTEO. Bits
6 and 7 indicate a VITC read error. Further clarifIcation of
the error can be accomplished by reading the VITC Read
Line registers, IR 30 and IR 31.

Processor Interface

I I I I I I I I I

76543210

~

The ICS2008 supports standard microprocessor interfaces
and busses, such as the PC bus, to allow access of six
control/status and data registers. These six registers are
organized into two groups, one set of four for SMPTE
control and the other set of two for direct UART port
control. Each set of registers is selected with its own chip
select, SMPTECS* and UARTCS*.

SMPTE Registers
The SMPTE register set allows access to 59 available registers. The fIrst two are direct access registers addressed at
locations 0 and 1. The remaining 64 registers are accessed
by writing an indirect register address into location 2 and
reading from or writing to location 3. If the AUTOINC bit
in SMPTE2 is set to I, the indirect register address is
automatically incremented after an access to location 3.
This eases the task of reading or writing sequential indirect
locations.

SMPTECS*
0

Al
0

0
0

0

0

I

I

SMPTEO
Interrupt Control/Status
LRI (LTC RCV Interrupt)
LXI (LTC XMT Interrupt)
VLI (Video line Interrupt)
LRIEN (I-enable, a-disable)
LXIEN (I-enable, a-disable)
VLlEN (I-enable, a-disable)
reserved
reserved

LRI - This bit indicates that a LTC receive interrupt has
occurred. In order for an actual processor interrupt to
occur, the LRIEN bit must also be set. An LRI interrupt
occurs upon reception of the last byte of LTC receive data
which was preceded by a valid LTC SYNC pattern. That is
after the 64th LTC receive bit time in the forward direction.
At normal frame rates, if the LTC transmitter is synchronized with the LTC receiver, there is about 3 milliseconds
after this interrupt before the LTC transmit data for the next
output frame is transferred to the output buffer.
LXI - This bit indicates that a LTC transmit interrupt has
occurred. When this bit is set, and the corresponding
LXIEN bit has been set, the INTR output will be activated.
The LTC transmit interrupt is activated after the transfer of
LTC transmit data to the output buffer. This occurs after
LTXEN is set to one and after the nnd LTC transmits bit
time ofthe current frame, 'N." Data loaded after this interrupt will appear in output frame 'N+ 2"since the transmitter
is double buffered.

AO
REGISTER
0 SMPTEO Interrupt
Control/Status
I SMPTE I SMPTE Status
0 SMPTE2 Indirect Register
Address
I SMPTE3 Indirect Register
Data

VLI - This is a status bit that indicates that the video line
selected via the Video Interrupt Line Register, VR9, has
passed. When the VLIEN bit is also set, the processor will
be interrupted. This interrupt can be used by the processor
to determine when to sample the VITC time code when time
locked to a video source. It will also be used to facilitate
detection of LTC time code dropout and off speed LTC
code, e.g. shuttling operations.

65

I

ICS2008
The SMPTE Status Register is a read only register which
contains video and LTC status.
7 6 5 4 3 2 I 0

I I I I I I I I I

SMPTE1

FRAME & FIELD - The hardware SYNC separator detects
the field and frame from the selected video input. The
even/odd fields are identified by a 110 in bit 6. Bit 7,
FRAME, is valid for PAL video after line 6. Bit 6, FIELD,
is valid after line 5 in NTSC mode or line 2 in PAL mode.

SMPTE Status Register

IIIII [ , ~ -~('"P"' '.,g".~~

L - CLICK (Input = l-hlgh,O-low)
LTCLOCK (I-locked, O-not locked)
CODEDIR (I-bkwd, O-fwd)
reserved
VLOCK (I-locked, O-not locked)
FIELD
FRAME (PAL only)

FRAMEIN - This bit indicates the state of the FRAME
input pin. It is used as an alternate source for B/A frame
status. This is useful when the quality of the video signal is
not good enough to extract the B/A frame status.

The SMPTE2 register is the register which points to the 57
indirect registers. When reading or writing an indirect register, the value in the ADDRESS pointer, SMPTE2 bits 5 to
0, is the address ofthe register accessed through SMPTE3.
If the AUTO INC bit is set to one, at the end of an access
cycle to SMPTE3, ADDRESS will automatically increment.
Otherwise, ADDRESS holds its value.
76543210

I I I I I I I I I

II

CLICK - This bit indicates the state of the CLICK input pin.
It can be used as a synchronization source for the LTC
transmitter.
LTCLOCK - When a valid forward or backward LTC sync
pattern is detected, this bit is set to one. It is reset to zero
when an expected LTC sync pattern is missed or an invalid
LTC bit is detected.
CODEDIR - The code direction bit works in conjunction
with the LTCLOCK bit. When the LTCLOCK bit is set to
one, the CODEDIR bit is valid. Otherwise, it is not. See the
table below.

~

SMPTE2
Indirect Address Register
ADDRESS
reserved
AUTOINC (I-Increment, O-hold)

SMPTE3 is the data register through which all of the indirect
registers are accessed. The address for a given register must
first be set in SMPTE2 before accessing that register.
7 6 5 4 3 2 I 0

I I I I I I I I I

LTCLOCK CODEDIR LTC RECEIVER STATUS
Looking for SYNC pattern
0
X
receiving LTC (FORWARD)
1
0
receiving LTC (BACKWARD)
1
1

VLOCK - This is a hardware driven bit which indicates that
genlock has been achieved with the selected video SYNC
source.

66

SMPTE3
Indirect Address Register

ICS2008
Indirect Registers
The following describes the functions controlled by the
indirect registers. A map of the indirect registers follows
this section.

IR29 selects the video line which starts the SMPTE video
display window in the video output. When this register is set
to 0, there will be no Burn-In Window displayed in the video
output.

LTC Read Registers IRO-IR7 (read-only)
These read only registers contain the LTC data as received.
Both forward and backward frames are stored with LTC bit
oin the LSB ofIRO and LTC bit 63 in the MSB ofIR 7.

I I I IIIII I

LTC Write Registers IRS-IRf
These registers contain the data to be sent by the LTC
transmitter. The LSB of IR8 is sent as LTC bit 0, and the
MSB ofIRf is sent as LTC bit 63. The data is transmitted as
it is stored in IR8-IRf.

These registers contain the character codes used for the
SMPTE time code in the burn-in window which overlays the
source in the video output. An internal character generator
converts the BCD nibbles to display characters.

7 6 5 4 3 2 1 0

Lme (00 - disable)

7 6 5 4 3 2 1 0 IR2a (Frame),

I I I I I I I I II'IR2c
R2b (Mmutes),
(Seconds),
~~~~~~~~.

VITC Read 1 Registers IRIO-IR17 (read-only)
These read only registers contain the VITC data as received
from the video line selected in IR30. The frame is stored
with VITC bit 2 in the LSB of IR 10 and VITC bit 80 in the
MSB ofIR17. Note that a binary 10 sync pattern precedes
every eight data bits of the VITC frame. The 10 sync pattern
is not stored. The CRC is checked by the VITC receiver,
and the result is reported in IR30.

lb.

'--------,---'
Tens

CODE
0

VITC Read 2 Registers IRIS-IRIf (read-only)
As with the VITC Read 1 registers, these read only registers
contain the VITC data as received from the video line
selected in IR31. The frame is stored with VITC bit 2 in the
LSB ofIR18 and VITC bit 80in the MSB ofIRlf. The result
of the CRC check is reported in IR31.
VITC Write Registers IR20-IR27
These registers contain the data to be output by the VITC
generator. The VITC frame is output with the LSB ifIR20
in VITC bit 2 and the MSB of IR27 in VITC bit 80. Note
that the binary 10 sync pattern which precedes every eight
data bits of the VITC frame is automatically generated by
the VITC generator. The CRC is also automatically generated by the VITC generator.
The next two registers control the position of the SMPTE
video display, burn-in, window within the video raster. The
window size is about one third the width of the screen and
32 lines high. IR28 selects the video column in which the
burn-in window starts.
7 6 5 4 3 2 1 0

I IIIIIII I

IR29
Burn-In Wmdow Lme

'--------,---' IR2d (Hours)
Ones
Burn-In Window Registers

CHARACTER
0

I

1

2
3

2
3

4

4

5
6
7

5
6
7

CODE
8
9
A
B
C
D
E
F

CHARACTER
8
9
Do Not Use
?
-

D

•

Blank

VITC code is normally output on two separate video lines
in each field for redundancy. These two registers allow the
individual line selection and output enables for the two
VITC lines.
7 6 5 4 3 2 1 0

IR2e

[ITT I [ L I I VITC Write Line 1
y'-____c:::::...
__'_
\ L
7 6 5 4 3 2 1 0

Write Lme# 10-40 (N+ 10)
reserved
VITC Write Enable (i-enable)

IR2f

I I I I I I I I I VITC Write Line 2
y'-____c:::::...
__'
\'' - -L
_______

Write Lme # 10-40 (N+ 10)
reserved
VITC Write Enable (i-enable)

IR28
Burn-In Wmdow Column
Column

Write Line - Selects the video line on which the VITC code
will be output. The video line on which the code is output
will be the number in this register plus 10; e.g. writing a 1 to
this register will cause the code to be output on line 11.
VITC Write Enable - Enables the output ofVITC code on
the specified line.

67

ICS2008
76543210

I I I I I I I I I

==-

I [I

76543210

I I I I I I I I I

I [,-----I_c::::""-

VTRES - When set, this bit clears the video timing counters
to dot zero ofline I of field I. This is useful when the video
is free running, not genlocked and LTC sync needs to be
synchronized to an event such as the CLICK input.

IR30
VITC Read II ne 1
Read Line 10-40 (N+ 10)
CRCERR (1-error, O-OK) (rio)
NOCODE (1-no code, O-code) (rio)
VITC Read Enable (1-enable)

VSYNCSEL - When set to I, this bit selects the video input
source from Video 2 (Y2) to be the SYNC source for the
internal video timing. Otherwise, when reset to 0, Video 1
(Yl) is selected.

IR31
VITC Read Lme 2

VITCSEL - When set to 1, this bit selects the video input
source from Video 2 (Y2) to be the VITC time code source
for the VITC receiver. Otherwise, when reset to 0, Video 1
(Yl) is selected.

Read Line 10-40 (N+ 10)
CRCERR (1-error, O-OK) (rio)
NOCODE (1-no code, O-code) (rio)
VITC Read Enable (1-enable)

As with the VITC Write Line Register, these registers allow
control of the individual redundant VITC read lines. The
processor can also reprogram these dynamically to allow for
scanning ofVITC code when the source lines are unknown.

VOUTSEL - When set to I, this bit selects the video input
source from Video 2 (Y2, C2) to be output on the video
outputs (YOUT, COUT). When reset to Video 1 (Yl, Cl)
are selected.

Read Line - Selects the line from which VITC code is to be
read within each field. It works identically to the Write Line
in that the video line selected is the number in this register
plus 10.

VID LS - When set to 1, this bit causes the Video 1 source
to be treated as S-Video. Otherwise, when cleared to 0, the
Video 1 source is treated as composite video.

°

VID2_S - When set to I, this bit causes the video 2 source
to be treated as S-Video. Otherwise, when cleared to 0, the
Video 2 source is treated as composite video.

CRCERR - This bit is reset to zero when a valid VITC code
has been received. It is valid from the end of the selected
video line until the end of the selected line in the next field.

PALINTSC - When set to 1, this bit causes the video to be
synchronized with PAL timing. Otherwise, when cleared to
0, video is synchronized with NTSC timing.

NOCODE - This bit is set when a framing error occurs in
the VITC code, i.e. not all the bits of the code were received
by the time the end of the video line occurred. Both CRCOK
and NOCODE must be zero to qualify a VITC code.
7 6 5 4 3 2 1 0

Video Interrupt Line - This register selects the video line
after which the Video Line Interrupt will occur. The actual
video line number is the number in the register plus one.

IR32 Video Control Register

I I I I I I I I I
IIII

[

IL

76543210

G,"'OC"'~" ,Hoc' .,-"~"

I I I I I I I I I

VTRES - Video Tim Ing Reset (1-reset)
VSYNCEL - Video SYNC Source Select
VITCSEL - VITC Source Select
VOUTSEL - Video Output Select
VID1_S - Video 1 S-vldeo Select
VID2_S - Video 2 S-Vldeo Select
PAUNTSC (1-PAL, O-NTSC)

I

--C===--

LI

IR33
Video Interrupt line Register
Video Interrupt Line (1 to 64)

_L-_ _ _ _ _ _ _ reserved

GENLOCK ENABLE - When set, this bit enables the
genlock circuits to sync to the selected video input signal.
When reset to 0, the video sync will "freewheel," generating
video timing from the internal oscillator. The freewheel
mode would be selected when striping LTC to allow synchronization with a MIDI sequencer or other strictly timed
audio source.

68

ICS2008

r[

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

IR34

L

I I I

I I I I I I I I I LTC Control Register 1

I

I'

2 LXCLKSEL
__ (~'o"rol
- (O-Internal clock)
(1-LTC receive clock)
LTXEN - LTC Transrn It Enable
LTC SYNC (~O-video, 01-CLlCK)
(10-LTC RCV, 11-Software)
LTCOUTSEL (1-dlgltal, O-analog)

i

IR35

I I I I I LTC Control ReQister 2
I

I

I

LTCGAIN - LTC Output Gain
O. off
4' -24dB 8' -12dB
5. -21dB 9 -9dB
1
2
6: -18dB A. -6dB
3.
7' -15dB B' -3dB
reserved

C'
D:
E'
F

OdB
3dB
6dB
9dB

LTCOUTSEL - This bit, when set to 1, causes the LTCOUT
pin to be a digital output. When cleared to 0, the LTCOUT
pin is an analog output with gain control.

LXCLKSEL - This bit controls the source for the LTC
transmit clock divider input. A 0 selects the internal
14.318MHz clock and a 1 selects the LTC receive clock.
When the LTC receive clock is selected as the source to the
LTC transmit clock divider, the clock rate is fust doubled
before being input to the divider so that loading a divider
value of 001 will result in the LTC transmit clock running at
the exact same rate as the LTC receive clock.

LTCGAIN - This bit sets the signal gain on the LTC audio
output. The output gain is selectable in 3dB increments
from -24dB to + 9dB referenced to OVU = -iOdbY. When
this register is set to 0, there is no LTC audio output.
These next two write only registers control the LTC transmit
bit rate. The transmit clock generator is a 12-bit divider.
The upper four bits ofIR37 are not used. Each bit requires
two clocks. Therefore, the LTC transmit bit rate is the input
clock divided by the divider value + I, then divided by two.
Since there are 80 bit times for each LTC frame, the LTC
frame rate is the bit rate divided by 80.

LTXEN - This bit, when set to 1, enables output of LTC code
on the LTCOUT output pin. LTXEN is synchronized with
the selected LTC SYNC source to ensure that only complete
LTC frames are transmitted. The data to be sent by the LTC
transmitter should be loaded into the associated RAM buffer before the LTCEN bit is set.

LTC Tx Clock = Clock/(Divider Value + 1)
LTC Bit Rate = LTC Tx Clock/2
LTC Frame Rate = LTC Bit Rate/80

LTC SYNC - These bits select the LTC transmit sync source.
Values 00, 01, lO and 11 select start of video line 5, rising
edge of CLICK, LTC receive sync pattern detect and write
to IR3f respectively as the sync event. Care should be taken
to disable LTXEN before changing the LTC SYNC select.
Otherwise, an erroneous sync may be generated.

76543210

I I I I I I I I I

IR36 [low byte]
IR37 [high byte]
LTC BltTlme (w/o)

IR3f is not a register at all. It is simply an address which,
when written and the LTC SYNC select is set for Soft SYNC,
generates LTC SYNC for the LTC transmitter.
76543210

I I I I I I I I I

69

IR3f

LTC Soft SYNC (w/o, no data)

I

ICS2008
7
LTC
Read

6

Write

BINARY GROUP 1

01

BINARY GROUP 2

02

BINARY GROUP 3

03

BINARY GROUP 4

04

BINARY GROUP 5

05

BINARY GROUP 6

06

BINARY GROUP 7

READ1

VITC
Read2

...

I

Write
Regs

1
BINARY GROUP 1

1

11

BINARY GROUP 2

12

BINARY GROUP 3

13

BINARY GROUP 4

14

BINARY GROUP 5

15

BINARY GROUP 6

16

BINARY GROUP 7

17

BINARY GROUP 8

I

18

...

I

I

...
28
2A
2B
2C
2D

COLR FRAME 1DROP FRAME 1

0

FRAMES TENS

SECONDS TENS

PHASE CORR 1

MINUTES UNITS
MINUTES TENS

BG FLAG 551

HOURS UNITS

I
I

I
I

HOURS TENS

1
FRAME UNITS

I

BG FLAG 75 UNASSIGNED

I

COLR FRAME 1DROP FRAME 1

FRAMES TENS

SECONDS UNITS
SECONDS TENS

FIELD MARK 1

MINUTES UNITS
MINUTES TENS

BG FLAG 551

HOURS UNITS

I
I

BG FLAG 75 UNASSIGNED

I
I

HOURS TENS

I
I

I
I

I

I
I

1

I

SAME BIT DEFINITION AS VITC READ1 BUFFER

I
I
I
I
I
J
1
-_ .. -_ .. --- -_ .. -_ .. --- -- -_ .... -_ .. --_ .... BURN-IN WINDOW COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --_ .. -- ---- --_ ...... -_ .. --- -- .. -_ .......... --- BURN-IN WINDOW LINE ------_ .... -_ ...... -_ .. -_ .......... -- --_ .. ---.... --- --- --_ .. -- -_ .. --_ ........ -_ ........ -_ ....
FRAMES
--- -- -- ---- ----- -_ ...... -- -- --- .. -----_ .. -_ .... -_ .. -_ .. -_ ........ -- -_ ................ --.. ------_ .. -_ ...... -_ .. -_ .. _ .... --- --_ .. ---SECONDS
.... --- --- --- --- -_ .. --_ ........ -_ ...... ---_ ..
.. _- -- -- ---- ----- --_ ........ -- -_ .. --_ .. _MINUTES
-_ .. ---- -.... -_ .. -_ .. -- .. -_ .. -- .............. ------------_ .... --_ .. -_ .. _ .... -_ .. --- ----HOURS
~

~

VITC1WE

0

0

VITC2WE

0

0

30

VITC1RE

NOCODE1

CRCERR1

31

VITC2RE

NOCODE2

CRCERR2

32

PAL

VID2_S

VID1_S

33

0

34

LTCOUTSEL

35

0

----------------------------------------I

VITC WRITE LINE 1
VITC WRITE LINE 2
VITC WRITE LINE 1
VITC READ LINE 2

-----------------------------------------

1 VITCSEL 1 VSYNCSEL 1 VTRES
1 GEN_EN
- - - - - - - - - - - - - - - - - - - - - - VIDEO LINE INTERRUPT (LlNE#) - - - - - - - - - - - - - - - --

0

VOUTSEL

I

I

I

LTXEN
I LXCLKSEL
0
0
0
0
- - - - - - - - - - - - - - - - - - LTC GAIN - - - - - - - - - - - - - - - -1
I
- - -- -- - -- - - - -- -- -- -- - - - - - -- --- - FRAME RATE (low byte, write only) - -- - - - - -- --- -- -- -- -- - - - - -- -- - --

o

- - - - LTCSYNCSEL - - -0

1

0

1

0

I

0

I ------- FRAME RATE (high byte, write only) - - - - - - -

38

reserved

39

reserved

3A

reserved

3B

reserved

3C

reserved

3D

reserved

3E
3F

I

SECONDS UNITS

I
I

I

2F

36

1

FRAME UNITS

I

2E

37

I

2

SAME BIT DEFINITION AS VITC READ1 BUFFER

20

29

I

SAME BiT DEFINITION AS LTC READ IBUFFER

10

27

3

I

1F
VITC

4

BINARY GROUP 8

I

08
OF

VITC

5

00

07
LTC

II

Indirect Register Map

reserved

-----------

- - SOFT LTC SYNC (write only, no data) - - - - - - - - - - - - 70

ICS2008
UART Registers
The DART emulates a 6850. Since the UART is tailored to
MIDI applications, some of the generic 6850 functions have
been omitted. The registers described below reflect that.

RBF - Bit 0, Receive Buffer Full, is set to I when read data
is available in the DART data register. It is cleared to 0
when the UART data register is read.
TBE - Bit I, Transmit Buffer Empty, is cleared to 0 when
data is written to the DART data register. It is set to I when
the DART transfers that data to its output shift register.

The two DART registers, Command/Status and Data, are
accessible to the processor as shown in the following map.

DARTCS*
0

Al

0

X

X

CTS - Bit 3, Clear-to-Send, is an active low status bit indicatingthe state of the CTS* input pin. A Oin this bit position
indicates that the modem or receiving device is ready to
receive characters. A I indicates not ready. When CTS is
inactive, I, TBE is held at 0, the not-empty state.

AO
REGISTER
0 DART Command/Status
Register
I UART Data Register

FE - Bit 4, Framing Error, when set to 1, indicates that the
receive character was improperly framed by the start and
stop bits. It is detected by the absence of the first stop bit.
This indicator is valid as long as the character data is valid.

DART Command/Status Register
7 6 5 4 3 2

1 0

UARTO (write)

I I I I I I I I I UARTCommand Register

T' I '

'l:' '" ",,,

100 - 0000, "

-

OV - Bit 5, Receiver Overrun, is an error flag indicating that
one or more characters in the data stream has been lost. It
is set to 1 when a new character overwrites an old character
which has not been read. The overrun error is cleared to 0
when a character is read from the DART data register.

=-1

(10·31 25K, 11 - Reset)
reserved
TC1, TCO - Transmit Control
00 - RTS* - low, Tx IRQ disabled
01 - RTS* - low, Tx IRQ enabled
10 - RTS* - high, Tx IRQ disabled
11 - RTS* - low, Transm It BREAK,
Tx IRQ disabled
RIE - Receive Interrupt Enable

IRQ - Bit 7, Interrupt Request, is a status bit which reflects
the state of the interrupt request from the DART to the
processor. When IRQ is I, an interrupt is pending. Otherwise, no interrupt is pending.

Bit Rate - This field selects the bit rate for data transmit and
receive. After a master reset, its value is II. One ofthe three
bit rates must be selected in order to start the DART's
operation. Writing a 11 will reset the DART.

The DART data register is actually two registers, a transmit
buffer and a receive buffer. Writing to the data register
causes the transmit buffer to be written. Reading from the
data register causes the receive buffer to be read.

TCI,TCO - Bits 6 and 5, Transmit Control, provide control
for transmit interrupt (when TBE is true), RTS control, and
transmit BREAK level.

I I I I I I I I I

76543210

RIE - Bit 7, Receive interrupt enable, when set to one,
enables the DART to interrupt the processor when the
receive buffer is full or a receive overrun has occurred.
76543210

I I I I I I I I I

~

UARTO (read)

UART2 Status Reg Ister
RBF - Receive Buffer Full (1-Full)
TBE - Transmit Buffer Empty (1-Empty)
reserved
CTS - Clear-to-Send (O-Actlve)
FE - Fram Ing Error (1-Error)
OV - Receiver Overrun (1-0verrun)
reserved
IRQ - Interrupt Request (1-Actlve)

71

UART1

UART Data Register

I

II

ICS2008
Absolute Maximum Ratings

Note: Stress above that listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only. Operating the device at these levels
is not recommended, and specifications are not implied.

Operating Temperature .............. O°C to + 70°C
Storage Temperature ............. -65°C to + ISO °c
Voltage on any pin to GND ..... -0.5V to VDD + 0.5V
Voltage on VDD to GND ............ -0.5V to + 7.0V
Power Dissipation ......................... 1.0 watt

DC Characteristics

TA= O°C to + 70°C; VDD = 5V± 10%; GND = OV

PARAMETER
Digital Inputs
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Digital Outputs
Output Low Voltage (IOL = 4.OmA)
Output High Voltage (lOH = O.4mA)
Tri-State Current
Output Capacitance
Bi-Directional Capacitance
Analog Inputs
Video Input Voltage (YI, Y2, Cl, C2)
LTC Differential Input Voltage
LTCIN+ , LTCIN-, CLICK, FRAME input voltage
CLICK and FRAME bias voltage
Analog Outputs
Video output Voltage (YOUT, COUT)
LTC Output Voltage (Volume set at max.; lout = 35mA)
LTC Output Voltage Amplitude Control Step
LTC Output Voltage Amplitude Range
Analog VDD Supply Current
I Digital VDD Supply Current

AC Characteristics

SYMBOL

MIN

VrL
VlH
ILl
CrN

-0.5
2.0

VOL
VOH
loz

TYP

MAX

UNITS

0.8
VDD+ 0.5
10
7

V
V
uA
pF

0.4

V
V
uA
pF
pF

2.4
10
10
10
1.0
0.1
-0.3

VDD+ 0.3
VDD/3

1.0
2.0
3
33
IDDI
IDD2

50
5

Vp _p
Vp _p
V
V
Vp _p
Vp _p
dB
dB
rnA
rnA

TA= O°C to + 70°C; VDD = 5V± 10%; GND = OV

PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Address setup to lOR * or IOW* command
20
ns
tACS
Address hold from lOR * or IOW* command
ns
10
tAH
Read pulse width
50
ns
tRD
ns
Access time
150
tACC
ns
Output enable access time
50
tOE
Data hold from lOR * high
ns
10
tRDH
ns
Read command inactive time
210
tRHRL
ns
Write pulse width
50
tWR
Write data setup to IOW* high
20
ns
tWDS
Write data hold from IOW* high
ns
10
tWDH
Write command inactive time
210
ns
tWHWL
CS* inactive time (Note I)
20
ns
tCHCL
kHz
UART Port Bit Rate (Command Register [1:0]= 00)
9.6
kHz
(Command Register [1:0]= 01)
31.3
(Command Register [1:0]= 10)
reserved
kHz
Note I: ThIS ummg parameter must be met for proper operatIOn ofmdlrect register access usmg auto-mcrement.

72

II

ICS2008

A1-A0

D7-D0~~~DC:w~~~~~:t}-~~~
SMPTECS*

IOR*
IOW*

Figure 3 - Host Processor Bus Timing

73

I

ICS2008
Video Inputs
IN
-----.lil Y1
Yl, Y2, Cl and C2 pins COMPlCOSITE
1uF
must be capacitively coupled to the terminated
video source(s). These inC1
puts are clamped to the
CTHRESH level. A typicalcoupling capacitance is
.1 uFo
'-;F;;;;i-g-ure-6::---::C:-o-m-p-o-s""'iC"te-'-ln.Lp-u...Jt

Applications
Crystal Oscillator
This oscillator will oper10
ate properly with either a
XTAL1
27pF
serial or parallel resonant
crystal. If frequency ac~D
curacy is critical, a paral9
lel resonant crystal is
XTAL2
f
recommended. In this
27pF
case the load capacitance
is the series eq uivalent of
,Ir
the two capacitors connected
Figure 4 - Crystal OSCillator
from the crystal to ground.
Typical capacitance values of 27pF will produce a loading
capacitance of about 15pF (with stray capacitance figured
in).

r--11

~

~1

t-- ~T

YIN

18 Yl
1 cF

r
c

17

IN

Cl

1 cF

r
I---

Threshold Bypass Inputs
These inputs are used to ,------:+""5V,----,------;
~ DTHRESH
set the clamping, SYNC
extraction and data extraction threshold volt,-----1--+---,1"j9 STHRESH
ages. The values shown
in Figure 5 are selected
for a nominal RS-170 siglff-g-~+-~2"'0 CTHRESH
nal of IVp-p.
If there are problems
locking the ICS2008 to

;~

Figure 7 - S-Vldeo Input
Video Outputs
Y IN
18 Y1
YOUT and COUT are
,'~F
outputs of analog multi~
plexers which select the
17
C
IN
C1
video source from Yl, C 1
"
-;'~F
or Y2, C2. These outputs
if>
r-are not buffered. This
minimizes signal distorI--tion. It is, therefore, important to keep the
capacitive and resistive load Figure 8 - Video Output
on the YOUT and COUT
pins to a minimum. A video output buffer is shown in Figure
8. T~e plus input of the opamp should be high impedance,
and ItS output should be able to drive a 75 ohm load with an
appropriate video bandwidth. In general, composite NTSC
and S-video signals have a bandwidth of 4.2MHz. A minimum output buffer bandwidth of lOMHz is recommended.
Care should be taken in board layout to minimize stray
capacItance on the YOUT and COUT pins. Otherwise,
there could be high frequencyrolloff. This could result in a
loss of chrominance amplitude.

I---

Figure 5 - Threshold Bias
incoming video, check the
video on Yl or Y2 with respect to CTHRESH and
STHRESH.

~THRESH is the threshold to which the input video sync
lipS are clamped. The CTHRESH level is nominally 1.3Y.
With the incoming video riding on this 1.3V DC level, the
internal SYNC separator sizes the video at 20 IRE up from
the SYNC tips. This level, STHRESH, is nominally l.44V.
The SYNC separator ignores short pulses which fall below
the STHRESH level such as these that come from the
chroma component ofthe video.

Care should be taken to keep lead to these pins short and
clear of any digital signal traces.

74

II

ICS2008

Self Biased Inputs
The
CLICK
and
FRAME inputs are biased to 112 VDD and
connected to plus inputs
of two comparators. The
minus inputs are internallybiased to 112 VDD.
When
CLICK
or
FRAME sources are
analog, they should be caFigure 9 - Self Biased
pacitively coupled to the inInputs
put pin. However, ifthe sources are digital, theymaybe tied
to the pins directly. It is important to make sure that the
digital levels into these pins swing above and below the 112
VDD threshold of the comparators. This is not a problem
with digital CMOS sources, but it could be with TTL
sources.

Programming
The ICS2008 is a SMPTE time code input/output device
with a UART which can be used as a MIDI UART or
transport control UART. All of the time critical functions
to read and generate time code are performed by the chip's
hardware, but all of the intelligence for processing time
codes and generating the time code values are performed
via an external processor. This makes the ICS2008 flexible
enough for a broad range of applications without making the
processing requirements on the host system too great.
In the case ofthe LTC receiver, LTC data is received into a
temporary buffer and transferred into the LTC read register
(IRO to IR 7) when the last bit of LTC data has been received.
It should be noted that the data is transferred before the
SYNC pattern has been received. Once the data is in the
LTC receive buffer, the LRI bit is set to one in the SMPTEO
register. If the LRIEN bit (SMPTEO) is set to a one, an
interrupt will be generated. The interrupt is cleared when
the SMPTEO register is read. The data in the LTC receive
buffer remains valid until the next LTC frame has been
completely received.

LTCIN+ and LTCIN- are comparator inputs for the LTC
input. This differential input is provided to maximize noise
immunity. If the LTC source is single ended, the LTCINshould be capacitively coupled to the ground reference of
that source. If the LTC source is digital, set the LTCIN- to
the desired threshold, and connect the digital source to
LTCIN+ .

The LTC generator transfers data from the LTC Write
registers (IR8 to IRf) to the output buffer when the LTC
generator is enabled; LTCEN is set to one. Data transfers
for subsequent LTC frames occur eight bit times before the
end ofthe LTC frame being output. Remember that a LTC
frame ends with a 16 bit SYNC pattern. The LXI interrupt
bit in SMPTEO is set to one when LTC Write register data
is transferred to the output buffer.

LFC Pin
This pin should be tied to VDD.

The UART has a four deep FIFO for its receive buffer. This
allows for relaxed interrupt latency requirements. In the
case of MIDI bit rates, the receiver will not overflow even if
the interrupt response delay is Imsec.

75

I

ICS2008
Indirect Register Access
Indirect registers are accessed via the SMPTE2 (address)
and SMPTE3 (data) registers. To read an indirect register,
the program must first write its address to SMPTE2. Then
the data is read from SMPTE3. Writing to an indirect
register is similar. First, the address is written to SMPTE2.
Then the data is written to SMPTE3.

Generating LTC
A typical program for generating LTC output would first
setup the LTC control registers and the LTC bit time registers. Then time code data would be written to the LTC Write
register. Once this setup is done the LTC output would be
enabled by setting LTCEN to a one. LTC output starts when
a LTC SYNC is received. The LTC SYNC source is selected
as part ofthe setup. While the LTC generator is waiting for
SYNC, the data in the LTC Write register is transferred to
the output buffer. When the transfer is complete the LXI
status but is set to a one. The data for the next LTC output
frame can then be loaded. The LXI status bit will be set to
a one after the data transfer at the end of the first LTC output
frame. At this point the LTC Write register is ready to
receive data for the third LTC output frame.

In order to minimize the number of accesses required to
read or write a block of registers, an auto-increment function is provided. Ifthe MSB of SMPTE2 is written to a one
with the address, the address is incremented after each read
or write access to SMPTE3. For example, if one wants to
read the LTC Read registers, IROto IR 7, SMPTE2is written
to a 80h. Then SMPTE3 is read eight times. The first byte
read is from IRO followed by IR I, etc. The auto increment
feature will not operate properly if CS* is not returned to
the inactive state between accesses. See the AC timing
section.

The SMPTE 1 register contains two status bits which indicate whether LTC data is being received and if so which
direction. LTCLOCK is set to one when the LTC receiver
has received a valid LTC SYNC pattern and data is still
coming in. CODEDIR indicates the direction of the LTC
SYNC pattern. This is useful to tell whether a tape with LTC
is shuttling forwards or backwards.

Interrupt Processing
Interrupts can be generated from four sources, LTC receiver, LTC generator, video line count and UART. The
interrupt status of the first three interrupts, LR I, LXI, and
VLI are in the SMPTEO register. After this register is read,
all three interrupts are cleared. It is, therefore, necessary to
save the state of the interrupt status and process all active
interrupts.

Reading VITC
To read VITC code one must first setup IR30thru IR33. The
VITC Read Line registers, IR30 and IR31, select the video
line from which VITC code is to be read. The MSB is the
enable for VITC reading. The Read Line field, bits 4 to 0,
should be programmed with the desired line number minus
ten. So, if line 15 is desired, a 5 should be programmed in
the Read Line field. IR32 selects the source and type of
video. The GENLOCK ENABLE bit must be set to a one,
and the VTRES bit must be set to a zero. The Video
Interrupt Line register, IR33 should be set to a line after all
VITC read and write lines. This allows all of the VITC
receive and generate operations to be complete before processing VTTC.

The UART interrupt status is in the UARTO register. The
receive interrupt is cleared by reading the receive data
register, UARTl. The transmit interrupt is cleared by writing data to the transmit data register, UARTI.
Reading LTC
LTC input data in available in the LTC Read registers after
the last LTC data bit has been received. It is not necessary
to wait for the LTC SYNC pattern to be complete. When
LTC read data is available the LRI bit in SMPTEO is set to
one. IfLRIEN is set to one, an interrupt is generated. LRI
and the interrupt are cleared by reading SMPTEO. Data will
remain valid until the last LTC data bit of the next frame has
been received.

The VLOCK bit in the SMPTE 1 register indicates whether
the ICS2008 is genlocked to the selected video source.
Without the VLOCK status set to one, no VITC read will
occur.
With VLOCK set to one and the control registers properly
initialized VITC data is received a byte at a time from the
video signal and written to the VITC Read registers. At the
end of the VITC data frame the CRC byte is checked, and
the result reported in bit 5 oflR30 and IR3l. In addition to
the CRC check, if a full VITC data frame is not received, the
NOCODE bit, bit 6, is set to a one.

76

II

ICS2008

Generating VITC
Like reading VITC, IR2e, IR2f, IR32 and IR33 must be
setup in order to generate VITC. The VITC Write Line
registers, IR2e and IR2f, select the video line to which VITC
code is to be written. The MSB is the enable for VITC
generation. The Write Line field, bits 4 to 0, should be
programmed with the desired line number minus ten. So, if
line 12 is desired, a 2 should be programmed in the Write
Line field. IR32 selects the source and type of video. The
GENLOCK ENABLE bit must be set to a one, and the
VTRES bit must be set to a zero. The Video Interrupt Line
register, IR33 should be set to a line after all VITC read and
write lines. This allows all of the VITC receive and generate
operations to be complete before processing VITC.

With the VITC generator setup properly, when the selected
video line starts, the VITC data in the VITC Write buffer,
IR20 to IR27, is output. The video line interrupt, VLI in
SMPTEO, is provided to allow ample processing time for
VITC generation.
Burn-in Window
The burn-in window can be placed anywhere on the video
display. The position of the upper left corner ofthe window
is selected by the values written in IR28 and IR29. IR28
controls the horizontal position. Values from OOh to 71h put
the corner in the first half of a video line (starting from the
falling edge of HSYNC). Values from 80h to fIh put the
corner in the second half of a video line. Any other values
will not display the window. Care should be taken not to
choose values which put the window in any part of the
blanking area. IR29 controls the vertical position. The value
written here is the video line number divided by 2.

IR2a to IR2d, are the registers which control the characters
displayed in the burn-in window.

77

I

78

ICS2008A

Integrated
Circuit
Systems, Inc.

Product Preview

SMPTE Time Code Receiver/Generator
General Description

Features

The ICS2008A, SMPTE Time Code Receiver/Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the ICS2008Ais easilyintegrated into products requiring SMPTE time code generation and/or reception in LTC (Longitudinal Time Code)
and/or VITC (Vertical Interval Time Code) formats and
MTC (MIDI Time Code) translation.

•

Internal and external sync sources
- Genlock to video or house sync inputs
- Internally generated timing from oscillator input
- External click input

•

LTC and VITC Generators
- Real Time SMPTE Rates: 30Hz, 29.97Hz, 25Hz,
24Hz
- Time Code Modes: Drop Frame and Color Frame
- VITC can be inserted on two lines from 10-40
(SMPTE specifies lines 10-20)
- "Jam Sync,· "free-Mleeling,· error bypass/correction,
and plus-one-frame capability

•

LTC Receiver
- Meets SMPTE and EBU LTC specifications
- Synchronize bit rates from 1130th nominal to SOX
nominal playback speed

•

VITC reader
- Reads code from any or all selected scan lines
- Meets SMPTE VITC specifications

Thking its input from composite video, S-Video, or an audio
track, the ICS200SA can read SMPTE time code in VITC
and LTC formats. Time code output formats are LTC and
VITC. All are available simultaneously. A UART is provided for the user to support MTC or tape transport control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors.
The ICS2008A is an improved version of the ICS2008, with
additional features and capabilities.

Block Diagram

New, Improved Features

•

Time Code Bum-in Window selectable to overlay
video with programmable screen position, size and
blackl-Mlite polarity

VITCOUT
LTC IN
LTC OUT

•

Internal Timer, allows 114 Frame MIDI Time Code
Messages

TACH IN

•

LTC edge rate control, conforms to EBU Tr and Tf
specification

•

Improved video timing lock during VCR pause and
shuttle modes

•

VITC search mode, will search through VBr lines until
VITC is found

•

New U ART frequency of 3S.4 Kbaud for tape transport control

•

Improved video output performance

VIDEO IN 1
VIDEOIN2
VIDEO OUT

PC

BUS

MIDI

79

I

80

1\;

ICS2101

Integrated

Circuit
Systems, Inc.

Digitally Controlled Audio Mixer
Description

Features

The ICS2101 is a CMOS monolithic integrated circuit that
fills the need for a digitally-controlled multi-channel linelevel stereo audio mixer. The ten input channels may be
treated as separate mono inputs, as stereo pairs or as a
combination of mono and stereo inputs. High-performance
attenuators provide accurate gain control with a minimum
of noise. Stereo balance and mono panning functions are
supported. The primary application for this part is in audio
cards for multi-media personal computers.

•
•
•
•
•
•
•

5 Stereo Input Pairs
I Stereo Output Pair
Logarithmic Attenuation: 7-Bit Resolution-0.5 dB per step
Separate Attenuation and Balance Control for each
Input Pair
Mono Input Mode with Panning
Master Attenuation and Balance Control for Output
Low Noise, Low Distortion

Architecture
lL
lR

2L

2R
3L

~

~
~

~

3R

~

4L

~

4R
5L
5R

~

~

~

~
~
Figure 1 - Basic Block Diagram

81

LOUT

ROUT

ICS2101
The audio inputs are logically grouped into five stereo pairs.
Each input passes through a digitally controlled attenuator
and a buffer amplifier. The output of the buffer may be
connected to either or both of the stereo summing buses.
On-chip logic manages the two attenuators to achieve both
level and balance control.
The outputs of the sum amps are applied to the master
attenuationlbalance controls and then to the buffer amps to
deliver the signals to the outside world.

Absolute Maximum Ratings
Storage Temperature
Voltage on any pin with
respect to ground
Maximum VDD
Power Dissipation

-65 ° C to 150°C
-0.3V to VDD+ 0.3V
7V
lW

Standard Test Conditions
Operating Temperature Range O°C to 70°C
Power Supply Voltage
4.75 to 5.25 Volts

DC Characteristics
VDD = 5V± 5%, Vss= OV
SYMBOL
VIH

PARAMETER
Logical I Input Voltage

MIN

TYP

2.4

MAX

UNITS
V
uA

0< VIN< VDDD

rnA

VOUT = VREF + IV
Master alternators off

100

rnA

VOUT = VREF - IV
Master alternators off

VIL

Logical 0 Input Voltage

0

VDDD
0.8

IIL
IOH

Input Leakage Current

-I

I

Output Source Current

-100

IOL

Output Sink Current

VREF

Internal Reference V

IADD

Analog Supply Current

7

10

rnA

IDDD

Digital Supply Current

10

100

~A

82

V

V

.44 VDD

CONDITIONS

II

ICS2101

AC Characteristics
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

3
20,000

Vpp

CONDITIONS

ANALOG
VAl
AF

Analog Input Voltage
Analog Frequency Range

20
20

RlN

Attenuator Input Resistance

32

Kohm

THD

Total Harmonic Distortion

0.2

%

SNR

Signal to Noise Ratio

86

dB

100

200

AC coupled

Hz

400

Gain= OdB
2Vp-p, 1 KHz,
Gain= OdB
Gain= OdB
BW= 20t020KHz

ohms

RMONO

Mono Switch Resistance

NCR

Crosstalk - LlR Channel

78

db

:1 KHz, 2 VPP
Gain = Odb

L'lG

Analog Output Step

0.5

dB

Atten. value
127 through 16

DIGITAL
TRESET

Reset Pulse Width

200

TlOWL

lOW Pulse Width Low

80

ns
ns

TrowH

lOW Pulse Width High

120

ns

Tcss

Chip Select Setup Time

25

ns

TCSH

Chip Select Hold Time

25

ns

TDS

Data Setup Time

25

ns

TDH

Data Hold Time

25

ns

Timing Waveforms
RESET

T RESET

TIOwL--1r------""-1
lOW -

TIOWH
CS - ,A

DO - D6
~TDH

Figure 2 - Timing Diagram

83

I

(I

ICS2101
Pin Descriptions
PIN NUMBER

PIN SYMBOL

PIN NUMBER

PIN SYMBOL

IL

15

RESET

I

IR

16

5L

CS-

17

5R
VDDA

2

-

,

3
4

VDDD

18

5

IOW-

19

4L

6

00

20

4R

7

01

21

ROUT

8

02

22

LOUT

9

03

23

VREF

10

04

24

VSSA

11

05

25

3L

12

06

26

3R

13

VSSD

27

2L

14

A

28

2R

f----------.

Reset: Active high. All control, pan, and attenuation registers are set to zeros.
Chip Select (CS-): Active low input. Chip select must be
low at the trailing edge of the -lOW pulse to select the
device.
Input Output Write (IOW-): Active low input. When the
chip is enabled, it latches data from the bus on the rising
edge ofIOW.
Address/Data (A): Input. When this input is high, the
address register is selected; when low, the data register
associated with the contents of the address register is selected.
Data bus (DO - D6): Active high input.
Audio Inputs (lL-5L, lR-5R): Audio connections to the
input attenuators. These inputs are internally referenced to
VREF and are normally fed via an external coupling capacitor.
Audio Outputs (L OUT, R OUT): Line level audio outputs.
Reference Voltage (VREF): Internally generated reference
voltage of approximately 0.44 VDDA. A lOOOpf capacitor
should be connected between this pin and VSSA.

84

II

ICS2101

DQ-D6

LOUT

IOWRESET
A
CS ROUT

+-.....

DO-D6 _ _

~

VDDA - - - - +
VSSA - - - - +
VDDD----+
VSSD - - - - +
V REF _ _ _ _ _ _ _ _,

Figure 3 - Block Diagram

L L

:~----.---

LEFT SUMMER

L
L R

/'----t----,

MONO

\:

R L

.r.. >---------'
R
R R

~~---~-

RIGHT SUMMER

Figure 4 - Attenuator Pair Detail

85

I

ICS2101
·10

Attenuation Control

·20

Each attenuator is controlled by a 7-bit value written into its
control register. Values of 127 through 16 increase the attenuation in one-half dB steps. Values of 15 through cause
the attenuation to approach infinity in increasingly coarser
steps. This ensures that the channel is completely off when
the control is at minimum value.

a:r.

"z

°

..:c

-30
·40
-50

·60
·70

·80
·90 -1-+-_-+--1--+--+-_<---<--+-+---+--1
127

11Q

90

70

SO

30

10

0

CONTROL VALUE

Figure 5 - Attenuation vs. Control Value
Registers and Modes of Operation

Address Register
BITS: XX543210

Address Register

BITS 5, 4,3

The address register is used to point to the internal registers
per the table listed at right:

Control Registers / Modes of Operation
Each attenuator pair maybe operated in one of three modes
and is controlled by five registers:

I BITS 2,1,

°

Left Control and Left Attenuation Register
Right Control and Right Attenuation Register
(Normal Mode only)
Pan-Balance Position Register (Pan/Balance
Mode only)

0,0,0=
0,0,1=
0,1,0=
0,1,1=
1,0,0=
1,0,1=

Pair I
Pair 2
Pair 3
Pair 4
Pair 5
Master

0,0,0=
0,0,1=
0,1,0=
0,1,1=
1,0,X=

Control Left
Control Right
Attenuator Left
Attenuator Right
Pan

NonnalMode
In the normal mode, both the left and right control and
attenuation registers are active, and the Land R inputs to
an attenuator pair may be separately controlled. The mono·
switch is always open.

L CONTROL REG
3210

SWITCH
LL

SWITCH
LR

R CONTROL REG
3210

SWITCH
RL

0000

off

off

0000

off

0001

on

off

0001

on

0010

off

on

0010

off

on

0011

on

on

0011

on

on

I

I

I

86

SWITCH
RR

I

off
off

ICS2101

I

Stereo Mode
In the stereo mode the left control register controls the
mode of the attenuator pair, and values written to the left
attenuation register are sent to both the left and right channels. The gain of both channels is always equal. However,
right control and attenuation registers are not inactive in this
mode. Therefore, the host software must be careful not to
write to the right control and attenuation registers while in
the stereo mode. The master attenuator pair does not have
a mono switch.
L CONTROL REG
3210

SWITCH
LL

0100

on

SWITCH I SWITCH I SWITCH
LR
RL.
RR
I
off
on

.--;;rr

I

I

MONO
SWITCH
OPERATION
off
Stereo - Normal

off

on

on

off

I

off

0110

on

off

off

on

I

on

Mono

0111

off

on

on

off

i

on

'Mono (Reserved)

0101

i

I

Balance/Pan Mode

I

Stereo - Reversed Channels

0

In the balance/pan mode, the left control register controls
the mode of the attenuator pair, and the left attenuation
register controls the overall gain of both channels. The
balance/pan register controls the differential gain of the two
attenuators, thereby regulating the balance of stereo signals
and the panoramic position of mono signals in the stereo
output of the mixer. The right control and attenuation registers are not inactive in this mode. Therefore, the host
software must be careful not to write to the right control and
attenuation registers while in the balance/pan mode. The
pan mode does not apply to the master attenuator pair, as it
does not have a mono switch.

-1

.."

-2

~

-5

z

-3
-4
-6

-7
-8
-9
1 2

3

4

5

6

7 8

9 1011 12131415

CONTROL VALUE

Figure 6
L CONTROL REG
3210

SWITCH
LL

SWITCH
LR

SWITCH
RL

SWITCH
RR

MONO
SWITCH

1000

on

off

off

on

off

Balance - Normal

OPERATION

1001

off

on

on

off

off

Balance - Reversed Channels

1010

on

off

off

on

on

Pan - Normal

1011

off

on

on

off

on

Pan - Reversed

i

!

In the pan/balance mode, two separate attenuator registers
are being internally managed to control an attenuator pair.
The attenuation value directed to the left attenuation register gets modified by the contents ofthe pan/balance register,
and the appropriate values are written into both the left and
right attenuation registers. Note that when a channel's
pan/balance register is modified, it has no effect on the
attenuator settings until a subsequent value is written to the
left attenuation register.

Programming Considerations
From the host processor perspective, the mixer chip consists
of two write-only registers: the address register and the data
register. The host first writes a value to the address register,
which selects the appropriate data register for subsequent
data-write operations. If a series of values are to be written
to a single register, as when gradually fading one attenuator,
the address register need only be written with the appropriate value once at the beginning of the operation.

Package Information
The ICS2101 is available in 28-pin DIP and SO packages.

87

88

ICS2102

Integrated
Circuit
Systems, Inc.

I

Sound Blaster™ Compatible Mixer
General Description

Features

The ICS2102 is a CMOS integrated circuit that provides
mixing of 4 stereo and I monaural audio signals as well as
master volume control. These functions are digitally controlled through Sound Blaster compatible mIxer registers, an 8
bit parallel interface. The monaural microphone input has
4 levels of attenuation. The remaining 8 input channels have
8 levels of attenuation. The four stereo channels and one
monaural channel are summed to form a composite signal
before global volume controls are added. The master volume maybe programmed with one of8levels of attenuation.
This component performs all the necessary audio mixing for
a product that is compatIble with Sound Blaster Pro.™

•
•

LFM -

j

rl-r:>---------,

~

,

ill f>~l~It-v-

LPCM -

l
>-

-lI}-{>---4 \

LLNE

•
•
•
•

4 channel stereo and I monaural mixing
8 levels of independent channel Input attenuation
control, except microphone (4 levels)
8 level master volume control
Separate digital and analog supplies
5V CMOS process
28 pIn SOle package

I

/

~ ~>

'CO

'~

LOUT

::;l,",c

MIC~__
RCD

>eN'
RPCM

RFM

0(7'0)

-1t ->-j= ~~
-~~

RREC

.::> ;~

--If}-.'~

-ill {>-

l' -

L

ROUT

j

+-~------,

4

RST"
Digital Control
WR" ~'
__
Interface

CEO .
AD

I·

'
_ _ _ -.-J

Sound Blaster and Sound Blaster Pro are trademarks of Creative Technologies, Inc

89

90

II

WaveFront

Integrated
Circuit
Systems, Inc.

Chip Set

WaveFront™:General M 101 Wavetable Synthesis System
General Description

Features

The WaveFront chip set provides professional quality music
through wavetable synthesis. This form of synthesis achieves
its startling realism by playing back short digital recordings
of real instruments. With WaveFront, a simple design can
sound like a full range of musical instruments at a cost that
rivals artificial sounding FM synthesis.

•
•
•

The primary component is the WaveFront Synthesizer,
ICS2115, which has the ability to play 32 voices simultaneously. As a source for sound data, ICS offers WaveFront
Sounds: ICS2122, ICS2124-001 and ICS2124-002. These
ROMs contain all the instruments in the extended version
of the GeneralMIDI specification (a standard developed by
the IMA, International MIDI Association).

•

•
•

The WaveFront Interface, ICS2116, handles most of the
support functions that a synthesizer requires. It allows
WaveFront to communicate through a serial, parallel or port
as well as the MPU -401 standard for the ISA bus. The
ICS2116 permits the WaveFront chip set to be a highly
integrated system at a surprisingly low cost.

•
•
•
•

Complete system for wave table synthesis of General
MIDI sounds
Minimum of external components due to highly integrated design
24 voice polyphony using an output sample rate of
44. 1kHz, or 32 voices at 33 kHz
Serial and parallel port input provides interface with
self contained unit
MPU -401 emulation, for compatibility with thousands
of DOS programs and the generic MPU -401 driver
supplied with Microsoft Windows 3.1
Two MIDI inputs and one output
Well suited for both a ISA peripheral and a free standing unit
No burden on host CPU for synthesis functions
Option for 2MB or 4MB patch set
Optional Wavetable DRAM for user samples
Optional digital effects with free-standing unit

Block Diagram: WaveFront as an ISA Peripheral
WaveFront
Sounds
ICS2122 or
ICS2124-001 &
ICS2124-G02

Motorola
68ECOOO
Microprocessor

J
MPU-401ISA ~
Interface
Serial Port ------>
or MIDI Port

.I.

1CS2116
WaveFront
Interface
~

1

I

,

ICS2115
WaveFront
Synthesizer

------

t

I

Wavetable
DRAM
(Optional)
I

L

I

_ _ _ _ ..J

WaveFront IS a trademark of Integrated CIrcuit Systems, Inc.

91

Stereo

r---- Audio
Output

Serial MIDI Output

- - _t_ -

256Kx 4
DRAM

16 Bit
Stereo DAC

Chip Set
Block Diagram: WaveFront as a Free-Standing Unit
WaV$Front
0§'yeratlng
stem
ROM

Sounds

Motorola
68ECOOO
Microprocessor

1~122or
1~124-001 &

1CS2124-002

T

Parallel Port
Serial Port-----cl
or MIDI Port

I

i.
1CS2116

1CS2115

waveFront
Interface

I

•
•
•

1

waveFront
Synthesizer

<-

T

r

256Kx4

1

DRAM

1

L

-I

__ L_....,

Wavetable
DRAM
(Optional)

1

I

L ____ J

Motorola

reduced function

~1

1

1------->
For Global
Digital Effects
(Optional)

-- - - -

J

16 Bit
StereoDAC

Stereo
Audio
Output

Ordering Information

Components for WaveFront
Development
•

r - - - --,

To construct one system using WaveFront, the following ICS
parts are required:

WaveFront Operating System in two forms:
- A binary file for an EPROM (for a free-standing
unit)
- A DOS executable that configures the system and
downloads the code (for an ISA peripheral)
Circuit Schematics of both the ISA peripheral and the
free-standing design (OrCAD format)
Gerber files ofthe two designs
WaveFront Demo Board
- ISA version
- Free-standing version

•
•
•

•

92

ICS2115 WaveFront Synthesizer (S4-pin PLCC or SOpin PQFP package)
ICS2116 WaveFront Interface (IOO-pin PQFP package)
WaveFront Sounds. Pick one of these three options:
- ICS2122 for a 2MB patch set (44-pin SO package)
- ICS2124-001 and ICS2124-002 for a 4MB patch set
(each is a 44-pin SO package)
- Obtain the mask file(s) for either the 2MB or 4MB
patch sets and fabricate the masked ROMs.
ICS2495-337 WaveFront Clock (This can be replaced
by two crystal oscillators if desired)
- ICS2495A-337 (20-pin DIP package)
- ICS2495K-337 (20-pin SO package)

ICS2115

Integrated
Circuit
Systems, Inc.

•

WaveFront Component

WaveFrontTM Synthesizer
General Description

Features

The WaveFront Synthesizer, ICS2115, is an audio synthesis
chip which utilizes wavetable lookup to produce l6-bit, CD
quality sound. The internal memory management unit allows both ROM, for standard samples, and low cost DRAM,
for soft load able samples, to be connected directly to the
ICS2115. The WaveFront Synthesizer presents the audio
output in l6-bit linear form for conversion by a low cost
CD-type DAC.

•
•
•

Capable of addressing up to 32MB of wavetable ROM
and up to 16MB of wave table DRAM
Variable Polyphony Rates: 24 voices at 44.1KHz
through 32 voices at 33 kHz
Uses l6bit linear, 8 bit linear, and 8bit u-Lawwavetable
data.
Serial output for a CD player-type DAC

Block Diagram
r-------------------------------------------.
I
I
I
I
I
I

RAMREQ"
DD(7:0)

SD(l5:0)

SA(l:O)
lOR"
lOW'
CS"
CSMM"
DACK"
TC
RESET"
SHBE'

XTU

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Wave Table
Memory
Interface

I
I
I
I
I
I
I
I
I
I
I
I

Synthesis
Engine

I
I

I~

DAC
Interface

I
I

I
I

I
I
I
I
I
I

I
I

I
I

I
I

I
I
I
I
I
I
I
I
I
IL

Synthesizer
Processor
Interface

---_.

I-

J

. .-

CLOCK

I

---.

--------

I
I

___________________________________________

93

I
I
I
I
I
I
I
I
~

J

•
••
•

•

••
•

ROMA(l7:9)

MA(lO:O)
ROMEN
BYTE
RAMACK
RAS"
CAS"(3:0)
WE"

SERDATA
LRCLK
BCK
WDCLK

DRQ
IOCS16"
MMIRQ
IRQ
...----> IOCHRDY
XTLO

I

ICS2116

Integrated
Circuit
Systems, Inc.

•

WaveFront Component

WaveFront Interface
General Description

Features

The WaveFront Interface is essential for a highly integrated
design using the WaveFront Synthesizer. It incorporates an
inexpensive Motorola 68ECOOOmicroprocessor into the system. It also provides system RAM, address decoding, and
data buffering to and from the input source. The input
source can be a serial stream (including MIDI), a parallel
port, or a set of registers on the ISA bus emulating MPU -401
or 6850 UART standards.

•
•
•
•

Provides the majority of system "glue" logic, for high
integration and low cost.
Uses a single inexpensive 256K x 4 D RAM as system
memory
Contains small code ROM, which eliminates the code
ROM in an ISA design
Soft select of 4 different IRQs on the ISA bus

For systems not using the ISA bus, the WaveFront Interface
can convert the serial output of the synthesizer into a form
that a reduced-function Motorola 56001 DSP can read. This
allows for global digital effects (such as reverb and chorus)
to enhance the audio signal.

Block Diagram
r--

A(l?:l)
UDS*
LDS*
AS*
RW
BG*

ClKIN

SD(?:O)
SA(2:0)
IOR*
IOW*
CS*
RESET
ICIRQ
ICDRQ
ICIOCHRDY

MIDIINl
MIDIIN2

-

---------

I
I
I
I
I
I
I
I
I

.-

68ECOOO
Interface
& BootROM

-1

I
I
I
I
I
I
I
I
I
I

~
~

----+----.---.

I
I
I

Internal
Registers
& Core
Logic
ISA
Interface

~

Address
Decode

~

~

~
I
I
I
I

D(15:0)
DTACK*
BR*
IPL(2: 1)
ROMCS*
DSPCS"
MA(8:0)
DRD{3:0)
RAS"
CAS"
CLKOUT
RESET"

I

=t:

I
I
I
I

I
I
I
I

I
I
I
I

~

~

I

System
Memory
Interface

~

WaveFront
Synthesizer
Interface

I

~
I
I
I

,

~'_'-=--_-_-_-_-_-_-_-_-_-_-'~:~-LI-~U-;-~A~~R;:;:T:c:_o::;::n:t_r':::o~lsJI--------------c_~
L _________________________________________

94

~

IOCHRDY
IRQ(3:0)
ICIOR"
ICIOW"
ICCS"
ICDACK"
ICTC
MIDIOUT

•

ICS2122
ICS2124-001
ICS2124-002

Integrated
Circuit
Systems, Inc.

WaveFront Components

WaveFront Sounds
Description

Features

The WaveFront Sounds, ICS2122 and ICS2124.0011.002, are
the sound material that comprises the wavetable for the
WaveFront Synthesizer. Each part, a 2M x 8 masked ROM,
contains all the information (digital recordings, loop points,
volume contours, etc.) necessary to produce all the sounds
in the General MID I specification. For a 2MB sound set use
the ICS2122, for a 4MB set use both the ICS2124·001 and
ICS2124·002.

•
•

16 bit linear wavetable (ICS2124.0011.002) or compressed wave table (ICS2122) of General MIDI sounds
Contains 128 instruments and 69 drum sounds

Instrument List
Acoustic Grand Piano
Bright Acoustic Piano
Electric Grand Piano
Honky-Tonk Piano
Electric Piano 1
Electric Piano 2
Harpsichord
Clavi
Celesta
Glockenspiel
Music Box
Vibraphone
Marimba
Xylophone
Tubular Bells
Dulcimer
Drawbar Organ
Percussive Organ
Rock Organ
Church Organ
Reed Organ
Accordian
Harmonica
Tango Accordian
Acoustic Guitar (nylon)
Acoustic Guitar (steel)
Electric Guitar (jazz)
Electric Guitar (clean)
Electric Guitar (muted)
Overdriven Guitar
Distortion Guitar
Guitar Harmonics
Acoustic Bass

Electric Bass (finger)
Electric Bass (pick)
Fretless Bass
Slap Bass 1
Slap Bass 2
Synth Bass 1
Synth Bass 2
Violin
Viola
Cello
Contrabass
Tremolo Strings
Pizzicato Strings
Orchestral Harp
Timpani
String Ensemble 1
String Ensemble 2
SynthStrings 1
SynthStrings 2
Choir Aahs
Voice Oohs
Synth Voice
Orchestra Hit
Trumpet
Trombone
Tuba
Muted Trumpet
French Horn
Brass Section
SynthBrass 1
SynthBrass 2
Soprano Sax
Alto Sax

Tenor Sax
Baritone Sax
Oboe
English Horn
Bassoon
Clarinet
Piccolo
Flute
Recorder
Pan Flute
Blown Bottle
Shakuhachi
Whistle
Ocarina
Lead 1 (square)
Lead 2 (sawtooth)
Lead 3 (calliope)
Lead 4 ( chiff)
Lead 5 (charang)
Lead 6 (voice)
Lead 7 (fifths)
Lead 8 (bass + lead)
Pad 1 (new age)
Pad 2 (warm)
Pad 3 (polysynth)
Pad 4 (choir)
Pad 5 (bowed)
Pad 6 (metallic)
Pad 7 (halo)
Pad 8 (sweep)
FX 1 (rain)
FX 2 (soundtrack)
FX 3 (crystal)

95

FX 4 (atmosphere)
FX 5 (brightness)
FX 6 (goblins)
FX 7 (echoes)
FX 8 (sci-fi)
Sitar
Banjo
Shamisen
Koto
Kalimba
BagPipe
Fiddle
Shanai
Tinkle Bell
Agogo
Steel Drums
WoodBlock
Taiko Drum
Melodic Tom
Synth Drum
Reverse Cymbal
Guitar Fret Noise
Breath Noise
Seashore
Bird Tweet
Telephone Ring
Helicopter
Applause
Gunshot
69 drum sounds

I

WaveFront Software

Integrated
Circuit
Systems, Inc.

•

WaveFront Operating System Software
Description

Features

The WaveFront Operating System software realizes the
complete potential of the hardware. It manages a complex
voice architecture where each voice has two envelopes with
6 segments. two LFOs and a modulation matrix. As shown
in the chart below, the operating system responds to a
comprehensive set ofreal time MIDI messages.

•
•
•

Full-featured implementation of a wavetable synthesizer
Meets the synthesizer requirements of the MPC specification
Selectable polyphony: 24 voices at 44. 1kHz through 32
voices at 33 kHz

MIDI Implementation Chart
FUNCTION
Default
Change
Default
Messages
Altered

Basic
Channel
Mode

TRANSMITTED

X
X
X
X

After
Touch
Pitch Bend

Sound Range
Note On
Note Off
Key's
Ch's

1
2
4
7
10
11
64
100,101
120
121

Control
Change

Program
Change
System Exclusive
System
Common
System
Real Time
Local ON/OFF
All Notes Off
Active Sensing
Reset

Aux
Messages

*********
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

Omni Off, Poly
*(see Notes)

0-127
0-127
0
X
X
0
0

Resolution:

0

0
0
0
0
0
0
0
0
0
0
0
0-127
0

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
0(123 - 127)
0
X

*********
SongPos
Song Sel
Tune

REMARKS

*********
X

Note
Number
Velocity

RECOGNIZED
1-16
1 - 16
Mode 3
Mode 3,4 (m= I)

0: Yes

X. No

NOTES:

* Mode 4 (Omm Off, Mono) 15 recognized as m =

I regardless of the value ofm.

96

All 14 bits
Modulation Wheel
Breath Controller
Foot Controller
Volume
Pan
Expression Controller
Sustain Pedal
RPNLSB,MSB
All Sounds Off
Reset All Controllers

Dump & Receive
Program Data

I
ICS

Multimedia Applications

97

98

ANS01

Integrated
Circuit
Systems, Inc.

Application Note

Using the GSP500 with a Rohm BA7230LS Encoder
Contents
Page
Schematics
GSP500

99

PAL equations - expanded product terms

101
102
103

PAL equations - symbol table

104

BA7230LS ..
Port Selection

105
106
106
107

Critical layout areas .
GSP500 pin names . . . . . . .
BA7230lS pin names . . . . . .
Suggested layout for BA7230LS

~~Y11N

=

VIdoo

1~~Y21N

8Ig....

PC IIuI

99

RGB-to-MrSC
encoder
(BA7230LS)

~

\/Ideo

_ ~ ~

I

GSP500 Schematic, page 1 of 3: GSP500 Wiring
VDD
AVOO

VOD

I

T

CSEL~

~

~

III
I

t...9 H :
l£?flO
~Y~r.

"
"
27

O.luF

7

"

..

,
"
""

STllFRtJ

>

39

vee
r--

;

17

ill

11

,,

3

vee

10

•
,
\

7

~
3.3K

100

iOOOpF

~~

=

.

1.21<

f

330pF
1000pF

-

""

6

~:~~c

0',.

VSYNCO

VGAOIE

2

COOl

r'EY
LK

ATA1N
YNCTHRES

-~

T

1-SpF

15PF

1
~'1

""

~

,4

vee au ~
5)

VGM/TS

~

33

¥CANlsr

;'

l',

f-!L-

"6
4-

H<;YNCOUT

.

V<';VN(OUI

(
11.0uF

(

,

B

MPLEV

"

;S

3

kST/A
YNCSLP
V
F

eVENAB
LA< 0
lJR I

FF
ALIGNIN

46
44

AUGNOUT
T

E

"
"
F~

OOPFlLT

SS

DA!~

DF~~
«TIl

11

""
~

f-#-

~
-~ ~
FASTOUT

~

FASTI'

e#-

~~~t~ ~
10

SnCT:)L

VIOEO INI
~

~; f4~
ODDIEV~~ f-L.-

GSPSOO

AVDO
Note Vldref connects
10 Iround at ground
;md of connector

,,

.,
27

FOURXS
THAEE5BS

DOTCL

-#--P>
" "'.

3.

75

'CIHEf

b.

....!....-

Y21npul

XTA'
SL

HSVNC
GAVSVNC

32

~

PCl-k

"
14.31818MHz

S,
0

33

O.luF

II

[QFV

i

XTAl1

18

-P---,.

'1T1ll/?

75

VOO

""

II

I

0
0

38

"

VSYNC

Y1 input

III

2.
20

Il

l

l
O'.JfNA'\1 F

<=0

GSP500 Schematic, page 2 of 3: BA7230LS Wiring
470

4oon5 delay

~

74AlS04
12K

r

1.f1uF

22uH

vee

'"
VIDEO OUT

-C>

'"

~D[!I1\

~

rr::=>

.70

56D

~
os

r~F

:& B2pF

III

GSP500 Schematic, page 3 of 3: Port Selection Wiring
SA11
SA10

1
2

SAl
7

•,

SA5

7

•

SA3

,

1

10
11

"

0
SA 0 •• 11

....... m

10WI

lOR!

14
23

II

11
12
13

~

"

001
1102

16

14

15
18
17

18

19

110
111
112
113
114

22

~

~
1m H!-tg r1r

vrDlll

..:]gC
HDMsmE

,

CSEL3

...
Ol

OJ

.

so
Dl
D2
D3
D4
D6
De

J

•

,•
14
17

7

..ro .. 71

11

..,

...S

~"'....--.

C

PAl.2OL8
SIlO

•• 7

SYIICTOL

~

,-Lc

Q1

t-+-

§i *"101
,

os
os
~ ~
cue

"
16

HOP
IOCT
tLU

,
•••

1
13
1

2A2
2A3
2M

7

±

CLR

'----

....."

...

.OJ

•••
•

SCI 0 •• 7

..ro .. "

D1

D2

Q1
Q2

7

\ICC

13

11
1

~ ~
cue
CLR

rpop;;Q

It

my

~
~

P6
P8
P7

,

•

CO

5

5
7

lZ

12

16
1

" IJ

at
• g:
•
OS
De OS
• D6
7

17
1

SYSIST

14
lZ

n•

1
13
1
17
SOl

"

7-4lS2«

74LS273

"
,"
"

SIlO

,.

lB
2B

..

, 0•• 7

1Vl
1V2
1V3
1V4
2Vl
2V2
2V3
2V4

lAl
lA2
1A3
1M
2A1

0 •• 7

•

&

8!

1

~B
74A1..SS22

74LS273

••

••
"

lAl
1A2
lA3
1M
2Al

2A2

2A3

17

2M

1

16
2B

"

7-4lS2«

lV1
lV2
lV3
1V4

2V1
2V2
2V3
2V4

SD 0•• 7

..,."
1

7

,•

PAL Equations - Expanded Product terms
HOLD1 =

SA11
NSAlO
N!SA9
N!SAS
NSA7
NSA6
NSAS

HOLD2 =

SA4
NSA3
N!SA2

R306 =

AEN & HOLD! & HOLD2 & lOR & !lOW & !SAO & SAl

R307 =

AEN & HOLDI & HOLD2 & lOR & !lOW & SAO & SAl

W306 =

AEN & HOLDI & HOLD2 & !lOR & lOW & !SAO & SAl

W307 =

AEN & HOLD 1 & HOLD2 & !IOR & lOW & SAO & SAl

AEN.oe =

0

HOLD1.oe
HOLD2.oe

=I
=I

R306.oe =

1

=

I

W306.oe =

1

W307.oe =

1

R307.oe

103

I

PAL Equations - Symbol Table
Pin
Polarity

Variable
Name

!

AEN
HOLD 1
HOLD2
lOR
lOW
R306

I
!
!

Ext

!

!

LEGEND F: field
N: node
V: variable

Type

Ptenns

MaxPtenns Min Level

used

R307
SAO
SAl
SA2
SA3
SA4
SAS
SA6
SA7
SA8
SA9
SAlO
SAll
W306
W307
AEN
HOLD 1
HOLD2
R306
R307
W306
W307

!

Pin

oe
oe
oe
oe
oe
oe
oe

21
18
19
23
14
22
15
13

V

-

-

-

V

7
3

7
7

1
1

-

-

-

1
1

7
7

1
1

V

10
9
8
7
6
5
4
3
2
1
17
16
21
18
19
22
15
17
16

V

-

V

-

-

11

V

-

V
V
V
V
V
V

V
V
V
V

X:

-

V

-

-

1
1
1
1
1
1
1
1
1

7
7
1
1
1
1
1
1
1

1
1
0
0
0
0
0
0
0

V

D
D
D
D
D
D
D

104

-

-

V

V

extended variable

-

-

V

D: default variable
I: intermediate variable

-

-

-

M: extended node
T: function
U: undefined

-

Critical Layout Areas
A)

GSP500 vexo input (pins 48 and 49 of GSP500)
Keep etches as short as possible. Keep all etches, especially high speed digital, away from circuit area.

B)

GSP500 vexo loop fIlter (pin 47 of GSP500)
Try to keep components near GSP500. Keep all etches, especially high speed digital, away from circuit area.

C)

VeLK dotclock connection (pin 54 of GSPSOO)
Keep etch as short as possible. Keep all etches, especially high speed digital, away from connection.

0)

GSPSOO veo loop r.Jter (pin 40 of GSP500)
Try to keep components near GSP500. Keep all etches, especially high speed digital, away from circuit area.

E)

GSP500 Video input ground connection
Connect one of the video input jack pins to the ground plane. Connect all VIDREF connections to this point with at
least a 20 mil etch. Keep 75 Ohm resistors close to the connectors.

F)

GSP500 Video inputs (pins 32 and 33 of GSPSOO)
Try to guard band video inputs to GSP500. Signal etches should be at least 20 mil thick.

G)

Encoder vexo loop fIlter (pin 12 ofBA7230LS)

H)

Lumirtance delay (pins 16 and 3 ofBA7230LS)

Try to keep components near encoder. Keep all etches, especially high speed digital, away from circuit area.
Keep etches as short as possible. Keep all etches, especially high speed digital, away from circuit area.
l)

Encoder vexo crystal (Pins 7 and 8ofBA7230LS)

J)

Power supply and loop fIlter pull-up voltage for GSPSOO and encoder (pins 20, 21, 38, 40, and 47 of
GSP500, pins 12 and 24 of BA7230LS)

Keep etches as short as possible. Keep all etches, especially high speed digital, away from circuit area.

Regulate all power supply and loop fIlter voltages.

105

G5P500 Pin Names
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

VLE
ODDIEVEN
FPI
DATAIN
CB
CS
CKEY
TEST
VSYNCOUT
DATAFRAME
OVENABLE
lIES
L/ROUT

BRSTACT
FRTSTOUTI

HS
HRSTOUTI
HSYNCOUT
VSS
VDD
VDD
VSS

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

FSO
FSI
FS2
FS3
FS4
FSS
EXTSYNC
SYNCTOL
CLAMPLEV
Y2
YI
C2
CI
3.5SSC
FRSTIN
AVDD
GFF
VCOLF
SYNCTHRS
VGAO/E
COUT
RSTI

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

YOUT
HALIGNOUTI
SYSLF
XTALI
XTALO
AVSS
VID1I2
VCOOUT
FILTSEL
DOTCLOCK
VFF
STILLFRAME
VGA/NTSC
BGI
LIRIN
VGAHSYNC
VGAVSYNC
HALIGNINI
NTSC/SVID
VS
4XSC
PCLK

8A 7230L5 Pin Names
1
2
3
4
5
6
7
8
9
10
11
12

VIDEO OUT
SYNC IN
YIN
B-YIN
R-YIN
BURST LEVEL ADJ.
VC
VB
VA
BPFIN (BGI)
APC PHASE ADJ.
PD

13
14
15
16
17
18
19
20
21
22
23
24

106

RED
GREEN
BLUE
YOUT
B-YOUT
R-YOUT
GND
VIDEO IN
PCP IN (FPI)
HDPIN
YSIN(OVENABLEI)
VCC

I
•

•

0

BA7230LS Test Layout
Component Side

o

o

r~~

0
•••

~.;.

o
_VIDEDDUI

o

•

...... 0

•
•

•

•

0 0

'----. '-

.00

• •

BA7230LS Test Layout
Solder Side

107

•

.04 )( 45

m
950 9BS

~ill

)t

OO0
,070
100

.172

t':urnl1lll1lll1lll1lll1lll1lllll1tT~ 010

,

45

GSP500 Physical Specifications
(All dimensions are in inches)

,.----220----;

2.

BA7230LS Physical Specifications
(All dimensions are in millimeters)

108

Adjustment Features
BA7230LS

GSP500
Set the GSP500 for non-NTSC operation(any
VGA mode). Alljust the variable capacitor (between pins 48 and 49 of the GSP500) until pin 65
of the GSP500 reads 14.31818 MHz. If you are
unable to adjust it far enough, you may have to
increase or decrease the size of the capacitor parallel to the variable capacitor.

Step 1
Adjust the variable resistor (pin 11 of the
BA7230LS) until pin 11 reads 3.9 volts DC.
Step 2
Place GSP500 in genlock mode. Attach a vectorscope to the video output connector. Create a
colorbar pattern on the computer screen (available
from ICS). Adjust the variable capacitor until the
vectorscope displays the proper phase.

Sources for Specialized Components
Encoders:

Phono Connectors:

BA7230LS
ROHM Corporation
USA Headquarters
8 Watney
Irvine CA 92718
(714)855-2131 FAX:(714)855-1669

901
Keystone Manufacturers
31"()7 20th Road
Astoria, NY 11105-2017
(718)956-8900 FAX:(718)956-9040

Delay lines:
H321lNP-1436PBAB (400nsec)
TaKa America, Inc.
Corporate Headquarters
1250 Feehanville Drive
Mount Prospect, IL 60056
(708)297"()070 FAX: (708)699-7864

Inductors:
RC-875/122J-50 (1 .2mH)
Sumida Electric Co., Ltd.
USA Head Office
637 East Golf Road
Suite 209
Arlington Heights, IL 60005
(708)956"()666 FAX: (708)956-0702
B230-52 (22uH)
J.W. Miller
306 E. Alondra Blvd.
Gardena, CA 90247-1059
(213)515-1720 FAX:(213)515-1962

Crystals:
143-20 (14.31818 MHz!. 0365 (3.579545 MHz)
Fox Electronics
5570 Enterprise Parkway
Fort Myers, FL 33905
(813)693..Q099 FAX: (813)693-1554

Variable Capacitors:
GKG7R011 (2-5pf)
Sprague/Goodman
134 Fulton Ave.
Garden City Pk, NY 11040
(516)746-1385 FAX:(516)746-1396

Potentiometers:
3321 + R (10K)
Murata-Erie
2200 Lake Park
Smyrna, GA 30080
(404)436-1300 FAX:(404)436-3030
EVM-SOGA01B14 (10K)
Panasonic
Box 511
Secaucus, NJ 07096
(201)348-5266 FAX:(201)392-4782

Distributors:
Digi-Key
701 Brook Ave South
Thief River Falls, MN 56701
(800)344-4539

109

I

110

AN502

Integrated
Circuit
Systems, Inc.

Application Note

Theory of Operation for a GSP500 Circuit Operating
the VGA display at 2xNTSC Frequency
Introduction
In its minimal configuration the GSP500 with a VGA controller chip puts out both RGB to a VGA monitor and composite
video in the NTSC format. However, due to the fact that NTSC
video is interlaced, the minimal configuration requires that the
VGA controller be programmed for interlaced operation; this
allows the same RAMDAC to be used for both the VGA and
the NTSC outputs (of course the NTSC output also must be
encoded). Unfortunately, the VGA picture is somewhat degraded by interlacing - and even worse, some VGA monitors
won't lock up to the interlaced signal. If this situation is not
acceptable, a solution is available that only requires a few
additional parts at minimal cost.

The solution is to run the VGA circuitry at exactly twice the
NTSC rate and in a non-interlaced mode. This preserves the
full quality of the VGA display while the VGA is still being
gen-Iocked to an external NTSC signal. Of course, now that
the VGA RAMDAC is running at a higher speed, another
RAMDAC will be required which runs at the NTSC rate. Also,
some means will be required to accept the fast data rate VGA
output and put out the slower rate NTSC data. Under these
circumstances, the VGA circuitry will be producing twice as
much data as can be displayed in NTSC and therefore some of
it will have to be discarded. All of the VGA lines are used in
the NTSC frame, but each line is only used for every other
NTSC field. In other words all the odd numbered VGA lines
may be output to NTSC field I and all the even numbered VGA
lines may be output to NTSC field 2 while both odd and even
numbered lines are put out to the VGA display in every vertical
period. The VGA frame rate is then the same as the NTSC field
rate; the NTSC field simply has half as many horizontal lines.

Application Circuit
Block Diagram
r-----I---------------~R
1-----------3> G

L-____r-------------7 B
ToVGA
monitor

R

8

A
Read Clock

Video
Data

M

D

~

GSP500
NTSC
Rate
HSYNC
(15.734 KHz)

R/W

'------t-----+-------,

Cont.

3

Dot Clock

2X
VGA
Controller

NTSC

VGAH SYN
31.468 KHz

Logic

111

Composite
Video
Output

I

(I

AN502
One possible implementation of this idea is shown in the
accompanying schematic. Only the additional circuitry required for the 2 x NTSC enhancement is shown. Following is
a detailed description of the operation of the circuit; please
refer to the schematic as you read it.

V5B divides the frequency of the VGA HSync signal VHS by
two, producing a 50% duty cycle square wave with a frequency
of 15.734 kHz. This signal essentially becomes the Write
Enable signal at V4 pin 22 and is also sent to the GSP500 pin
60 as the Horizontal Sync signal. Note that the addition of a
divide by 2 in the overall loop which the GSP500 controls
forces the VGA chip to clock at twice the rate that it otherwise
would, producing a VGA HSync frequency of 31.468 kHz.
V7 is a line buffer memory which can hold up to 910 pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device
V4 provides a write enable and pointer reset signals to the line
memory. Note that the write clock to V7 (pin 17) is the same
rate as the VGA pixel clock; therefore every VGA pixel will
be written in to the memory when write enable (pin 20) is active
(low). The write enable is only active for every other line,
however, since it is frequency divided by 2 from the VGA
HSync as previously noted. This essentially discards half the
VGA lines each NTSC field, by virtue of the fact that they are
not written into memory. The time to write a complete line
into memory is 1 VGA line time or 31.778~s. The read clock
for V7 is simply the write clock frequency divided by 2 by
V5A. Thus to read all the pixels out of the memory will require
twice as long as to write them, or 63.557~s. This is the length
of an NTSC line. Therefore, over the span of 2 VGA lines, 1
VGA line is written and I NTSC line is read, although the
writing takes place at twice the NTSC rate.

respect to the NTSC picture quality. It is probably intuitively
obvious to most people that throwing away half the VGA data
will result in a loss of picture quality on the NTSC output. The
practically observed result of this is what is generally known
as "flicker", and it should be noted that this problem plagues
all scan converters and VGA-to-NTSC boards. It is worst
when there is a lot of detail along the vertical axis of the VGA
image. The most annoying example is probably a thin, bright
white horizontal line made up of a single line on the VGA
display. For an example case, imagine that line 100 of the
VGA display contains the white line and the rest of the display
is black. Then the white line would appear somewhere around
line 50 of field 2 in the NTSC output, but not at all on field 1.
The result will be a flashing of the line with a period of 33.33
ms (due to 30Hz frame rate). This is visually very noticeable
and irritating. Because of this, many scan converters and
VGA-to-NTSC boards have a "flicker filter." Interestingly,
most flicker filters can be turned off, indicating that they are
less than desirable in some situations.
A discussion of flicker filtering and how to implement it with
the GSP500 will be the subject of another application note.

Data read out from V7 at NTSC rate is fed to RAMDAC VI,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to +5V. In this way anything
written to the VGA RAMDAC (such as changes to the palette)
will also be written to V I, but any reads will not cause a conflict
with the main VGA RAMDAC. The analog RGB outputs of
V I are sent to the NTSC encoder to produce a composite video
output. V3 provides a reference for the RAMDAC. Instead of
a reference for each RAMDAC, it may be possible to use 1
voltage reference for both RAMDACs in the system if they can
be configured to use a voltage reference as shown in the
schematic.

Further Enhancement
Although the VGA at 2xNTSC enhancement is better than the
minimal GSP500 configuration, it is still less than ideal with

112

II
To noy Compor
DATOO - DATOl
Q

RAMD[OO 07]

To VGA Chip

PolotQ Data
U7

'5V

UPD42101

U6A

~_~,,2

~
74HC04
VGA Harlz Sync

U6D

From,~ChIP __ ~

~~811
74HC04

....
....
c.-

- - . - -~ To Encodor

To

GSP600

Pin 60

'5V
C4
1 cF

D

V~oL
74HC04

U6E

74HC04

U6F

-1>
013

74HC04

Pin 14 vee
Pin 7 GND

74HC04

o1L
To Dolo Bus
+808<0> Thru +8D8<7>

cPu[oa 12J

»
z

CJ1

o

N

II

II

AN502
CRTC Registers
VIDEO MODES
INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

DE

OF

10

11

12

13

**

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

04_ ~

00

HT

01

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F_

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54

57

58

57

05

EHR

AD

AD

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

VT

DB

OB

DB

OB

DB

OB

DB

DB

DB

DB

OB

OB

OB

OB

OB

OB

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

4F

4F

4F

4F

C1

C1

C1

4F

CO

CO

40

40

40

40

CO

40

00

01

02

03

04

05

06

07

00

OE

OF

10

11

12

13

**

CS

OD

OD

OD

OD

00

00

00

OD

00

00

00

00

00

00

00

00

DB

CE

OE

DE

OE

DE

00

00

00

DE

00

00

00

00

00

00

00

00

DC

SAH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OD

SAL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OE

CLH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OF

CLL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

DE

OF

10

11

12

13

**

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

06
07
08

- OVERFLOW
PRS

09

MSL

INDEX

REGISTER

i

VIDEO MODES

OA

--

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

SD

SD

DF

DF

8F

DF
50

13

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

00

00

00

IF

00

00

OF

OF

00

00

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

CA

DC

DC

05

OC

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

*

INTERLACE

* = Interlace Bit must be turned off for all modes

General Register
VIDEO MODES
INDEX

REGISTER

I 01 I 02 I 03 I 04 I 05 I 06 I 07 I OD I DE I OF I 10 I 11 I 12 I 13 I **
#I#I#I#I#I#I#I@I#I#I@I#I#I#I#I#

00
00

MISCOUT

#
23 = GenLock (GL)
27 =OVerlay (OV)
2B = Video Only (VO)
2F =Graphics Only (GO)

@

22 =GenLock (GL)
26 = OVerlay (OV)
2A =Video Only (VO)
2E = Graphics Only (GO)

114

II

AN502

Sequence Registers
VIDEO MODES
INDEX

REGISTER
DO

DO

CLKMODE

09

I
I

01
09

I
I

02
01

I
I

03
01

I
I

04
09

I
I

05
09

I
I

06
01

I
I

07
00

I
I

00
09

I
I

OE
01

I
I

OF
01

** =640 x 480 x 256 colors
Source Code for PLD U4 (GAL20V8) in CUPLTM Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

2ntsc;
XXXXX;
12/07/92 02:12pm;
02;
Todd K. Moyer;
Integrated Circuit Systems;
XXXXX;
XXXXX;

/*********************************************************************** /

1*
1* VGA
1*
1*

*/
*/
*/
*/

@ 2xNTSC rate controller

/*********************************************************************** /

1*

*/

/* Allowable Target Device Types: g20v8
/*

*/

/***********************************************************************/

/** Inputs **/
Pin 1
Pin 2

clock
h_sync_NTSC ;

Pin 12
Pm 13
Pin 24

GND
!OE
VCC

1* VGA p-clock
1*

*/
*/

1* used by state machine

*/
*/
*/
*/
*/

1** Outputs **/
Pin
Pin
Pin
Pin
Pin

[15 .. 18]
19
20
21
22

[HSN_SO .. 3];
!line_start;
!write_enable_B;
!write_enable_A;
!write_enable;

/* pointer reset line mem, act 10
/* not used by 2xNTSC
/* not used by 2xNTSC

1*

/** Declarations and Intermediate Variable Definitions **/
Field

State_HSync

= [HSN_SO .. 3];

/** Logic Equations **/

115

L 10 I
I 01 I

11

J 12 I

13

01

I

01

01

I

I **
I 01

I

II

AN502
/** State machine definition **/
Sequence State_HSync
{
present 0
if h_sync_NTSC next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0
out write_enable;
present 1
if h_sync_NTSC next 2
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0;
present 2
if h_sync_NTSC next 3
out line_start out line_startAB
out write_enable out write_en able_A;
if !h_synch_NTSC next 0;
present 3
if !h_sync_NTSC next 4;
/* out write_enable; */
if h_sync_NTSC next 3
out write_enable_A;
present 4
if !h_sync_NTSC next A;
if h_sync_NTSC next 3;
present A
if !h_sync_NTSC next 5;
if h_sync_NTSC next 3;
present 5
if h_sync_NTSC next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5
out write_enable;
present 6
if h_sync_NTSC next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 7
if h_sync_NTSC next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 8
if !h_sync_NTSC next 9;
/* out write_enable; */
if h_sync_NTSC next 8
out write_enable_B;

116

II

ANS02

present 9

if !h_sync_NTSC next B;
if h_sync_NTSC next 8;
present B

if !h_sync_NTSC next 0;
if h_sync_NTSC next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials for 2xNTSC
Item

Qty

1

1

74HC04

HEX INVERTER

Motorola

2

1

74HC74

DUAL D FLIP FLOP

Motorola

3

1

SCl1483CV

RAM-DAC

Sierra

4

1

GAL20V8

PLD

Lattice

5

1

LM317

Adjustable Regulator

National

6

1

UPD42101

91Ox8 FIFO

NEC

7

7

CAP

.11lF Cap

8

1

R1I4W

240 ohm

9

1

R1I4W

150 ohm

10

3

R1I4W

24 ohm

Part Name

Description

117

Manufacturer

I

118

AN503

Integrated

Circuit
Application Note

Systems, Inc.

Flicker Reduction Circuit for use with the GSP500
Introduction
Although a minimal configuration G SP500 VG A/NTSC system uses all of the lines of the graphics image to generate
the NTSC picture, the resulting NTSC display is not (and
cannot be) as good as the original VGA display. Despite the
fact that all the lines are used, on the standard non-interlaced VG A display every line is used for every vertical period
of about 16.7 ms, while it takes twice as long to put out all
the lines to the NTSC picture (33.33 ms). This is accomplished in practice by one of two ways: I) interlacing the
VGA (slowing it down to NTSC rates), or 2) using odd
numbered lines for odd NTSC fields and even numbered
lines for even fields, essentially discarding halfthe lines that
are output from the VGA (see the Application Note,
AN502: The?ryojOpemtionjora GSP500 Circuit Opemting
~he ~~A Dlsp~ay at 2 x NTSC Frequency). It is probably
mtUltIvely ObVIOUS that either slowing the VGA down or
throwing away half the VGA data will result in the NTSC
output loo~g less pleasing than the standard VG A display.
The pract!c~lly o~ser~d result of this is what is generally
known as flicker, and It should be noted that this problem
plagues all scan converters and VGA-to-NTSC boards; it is
a fundamental limitation ofthe NTSC standard. It is worst
when there is a lot of detail along the vertical axis of the VG A
ima:!le. Th~ most annoying example is a thin, bright white
honzontalline made up of a single line on the VGA display.
For an example case, imagine that line 100 of the VGA
display contains the white line and the rest of the display is
black. Then the white line would appear somewhere around
line 50 of field 2 in the NTSC output, but not at all on field
1. The result will be a flashing of the line with a period of
33.~3 ms (reciprocal of the 30 Hz frame rate). This is very
noticeable and quite irritating to the eye.
Knowing that displaying a VGA image on an NTSC monitor
is at best a compromise, we would at least like to achieve the
best possible performance from the conversion. Because of
this, most scan converters and VGA-to-NTSC boards have
a "flicker filter". It is enlightening to note that most flicker
filters can be turned off, indicating that they are less than
desirable in some situations. In fact they reduce the spatial
'bandwidth" in the vertical direction, or in other words
reduce the vertical resolution. A particularly simple and
effective flicker reduction scheme (which can be implemented in software) is to repeat every other VGA line in
both fields of the NTSC signal. This method however
requires that half the VGA lines never get to ~he NTSC
display, in other words the vertical resolution is cut in half.

A single horizontal line in the VG A image has only a 50/50
chance of being displayed in NTSC, depending on which line
number it appears on. Obviously, this method leaves a lot
to be desired, since some details in the VGA image can be
~ompl~telyabsent from the NTSC signal; most people would
Judge It unacceptable.
You can get a feel for how a better typical flicker filter works
by thinking about the example above of a single white hori~ontalline on scan line 50 of field 2. Imagine "spreading" the
Ime so that some of it spills into the scan lines adjacent to
the original line. In an interlaced system such as NTSC this
mea?s r~ducing the brig~tness of line 50 offield 2 (thereby
~akmg It gray), and puttmg some darker shade of gray into
lines 50 and 51 offield I, which are above and below line 50
of field 2, respectively, once the complete frame has been
s~anned. If done properly, in the right proportions, and
VIewed from a sufficient distance, the new wide line looks to
be of the same brightness as the original single white line.
This can significantly reduce the flicker, since there is no
longer the situation of black on field I and white on field 2
rapidly alternating. However, as you can imagine, any rapid
vertical transitions would also become smeared or blurred
with such a scheme. The typical complaint is that when
trying to display text on an NTSC display, a flicker filter will
ma~e the text ~ess readable (if it remains readable at all).
ThiS type of flicker reduction works best if only the luminance portion of the signal is filtered, since the mixing of
several VGA lines .to make one NTSC line can significantly
change the saturatIOn and hue of the color displayed, seriously altering the picture when compared with the VGA
display. It is primarily changes in luminance level that cause
flicker, so that leaving the chrominance portion of the signal
unchanged does not seriously degrade the flicker reduction
that is achieved, while it does tend to preserve the look of
the image.
To boil all this down, there is a trade-off between flicker
~e~uction and vertical resolution, and it bears repeating that
~t IS a practical impossibility to make an NTSC image look
Just as good as a high resolution VGA image. To try and
work around this trade-off, some sophisticated flicker filters
are :'adaptive", which essentially means that they will dynamically turn themselves on when especially needed to
reduce flicker and off when the loss of vertical resolution is
especially detrimental. Predictably, this approach is rather
exp~nsive ~nd takes up a lot of circuit board space, at least
until the t1ffie when this function is incorporated into a
monolithic integrated circuit. At any rate, a flicker filter of
the more basic varietyis presented here for use with GSP500
applications.

119

I

II

ANS03
Application Circuit
In the accompanying schematic and block diagram an implementation of a simple luminance-only flicker filter which
works with the GSPSOOin a VGA-to-NTSC system is shown.
The schematic details only the portion of the system specific
to the flicker filter function, since the VG A portion will vary
depending on the VGA chip used. Please refer to the
schematic when reading the following detailed circuit description.
USB divides the frequency of the VGA_HSYNC signal VHS
by two, producing a 50% duty cycle square wave with a
frequency of 15.734 kHz. This signal essentially becomes
the Write Enable signal at U 5 pin 22 and is also sent to the
GSP500 pin 60 as the Horizontal Sync signal
NTSC_RATE_HS. Note that the addition of a divide by 2
in the overall loop which the GSP500 controls forces the
VGA chip to clock at twice the rate that it otherwise would,
producing a VGA HSync frequency of 31.46S kHz.
U2 is a line buffer memory which can hold up to 910 pixels
with a width of S bits; it has individual write and read clocks
with associated address pointers. Programmable logic device US provides a write enable and pointer reset signals to
the line memory. Note that the write clock to U2 (pin 17) is
the same rate as the VGA pixel clock; therefore every VGA
pixel will be written in to the memory when write enable (pin
20) is active (low). The write enable is only active for every
other line, however, since it is frequency divided by 2 from
the VGA HSync as previously noted. This essentially discards half the VGA lines each NTSC field, by virtue of the
fact that they are not written into memory. The time to
write a complete line into memory is 1 VGA line time or
31.778~s. The read clock for U2 is simply the write clock
frequency divided by 2 byUSA. Thus, to read all the pixels
out of the memory will require twice as long as to write them,
or 63.SS7~s. This is the length of an NTSC line. Therefore,
over the span of 2 VGA lines, 1 VGA line is written and 1
NTSC line is read, although the writing takes place at twice
the rate.

Data read out from U2 at NTSC rate is fed to RAMDAC
U9, which has its control lines paralleled across the main
VGA RAMDAC, except that the active low read enable
(pin 6) is permanently disabled by tying it to + 5V. In this
way anything written to the VGA RAMDAC (such as
changes to the palette) will also be written to U 9, but any
reads will not cause a conflict with the main VGA RAMDAC. The analog RGB outputs ofU9 are sent to the NTSC
encoder to produce the chrominance component of the
composite video output. U 6 provides the required voltage
reference to U9. Also, the RGB outputs from U9 are
combined by resistor matrix in the right proportions to
create a luminance signal which can be summed with the
adjacent lines' luminance signals, thereby spatially lowpass
filtering the luminance signal in the vertical dimension.
Up to this point the circuitry described is basically the same
as is required to make the VGA run at 2 xNTSC rates (see
the Application Note AN502: Theory of Operation for a
GSP500 Circuit Operating the VGA Display at 2 x NTSC
Frequency). Note that there are an additional 2 line buffers
(U3 and U4), 2 RAMDACs (UIO and Ul), and 2 current
references (U7 A, Q 1, and Q2). The additional 2 line buffers
store the VGA lines before and after the current line being
output via U2 and U9. The RGB current outputs from the
RAMDACs U 10 and U 1 are connected together, summing
the two sets ofRGB currents together. The combined RGB
signals from U 10 and U 1 are then matrixed together in the
proper proportions to produce an adjacent-lines luminance
signal. This signal amplitude is independent of the main
luminance signal so that the ratio of adjacent line to main
line luminance can be set to any desired value, primarily by
adjusting R 1, which controls the reference currents into U 10
and U 1.

120

AN503
r

-

VGAHORIZSYN
(31 468kHz)

--

I

Icor-Yr~~LLER

VY6i~j,"A'iA

--"-r =1
8/

_____

~
DOTCLOCK

RAMDAC

--

,---------.RGB TO VGA MONITOR

J-~

I

PCLKI

1rDiV'{~j
l
5
~

~-.~_~~_~C-:::"'"~

NTSC HORIZ SYNC
(15734kHZ)

.

1J"[---{c-N-C-OD-ER
YIN

8'

I

,_,l' ~

LINE BUFFER

I I

WRITE
CONTROL

I

~LOGIC

~- ~iMATRIX/ I iN~~\ LJ~~~1fcE
RA.MDAC ,

S.UM... MER

M"~~~

---+

I

I

--f

1--------" AMPLIFIER

,READ
CLOCK

Figure 1
The two luminance signals are connected together, summing
them at the input to amplifier U II. U II then makes up for
the resistive losses in the RGB matrices and drives the
luminance delay line, whose output is the luminance component of the encoded composite signal. Most encoders
have a luminance output and input which allows for an
external delay line; not using the output provided while
driving the input with an alternate luminance signal of the
right amplitude, delay, and polarity allows convenient summing with the chrominance signal generated by the encoder
to create the composite video signal.

WE-U2 _JI~

Programmable logic chip U 5 controls the writing of VGA
lines into the line buffers such that U2 receives every other
line, U3 receives every fourth line, and U 4 receives every
fourth line, as shown by the timing diagram in Figure 2. Note
that only one line buffer is write enabled at a time and every
line is written to a line buffer. With this scheme U2 always
contains the main VGA line which is going out to the NTSC
encoder, while U3 and U4 contain the lines adjacent to the
main line. The CUPLTM language source code for PLD U 5
is included later in this note.

__I
L

WE-U3
WE-U4

L_._J

31.778uS
1 VGA LINE

63.556 uS
1 NTSC LINE

I

~I

Figure 2
121

I

AN503
All of the line buffers are continuously read enabled, such
that the ROB signal output to the encoder is a combination
of the main line and the 2 adjacent line signals. U7 A, Q 1,
and Q2 make up a dual matched current reference for
RAMDACs U 10 and U 1. The amplitude of the adjacent
line video signals summed in with the main line is adjustable
with R 1; the optimum value could be determined so that R 1
could be replaced with a fixed divider to save the cost ofthe
trimmer. The amplitude of the main line video signal is
controllable by the value ofR6 if it is necessary to adjust the
proportion of the main line signal that gets summed into the
final output. The relative weight of the 2 adjacent line signals
in the output is the same due to the matching of the current
references into U 10 and U 1; this should be best for most
applications since it is symmetrical about the main line.

BIOS
The video BIOS for the circuit presented here will have to
be modified from the typical OSP500 VOA/NTSC system;
therefore, register setups for various video modes are given
in several tables later in this note.

The luminance amplitude is controllable by varying the gain
ofU 11 (set by the value ofR22); this should normally be set
so that luminance levels on any given line are somewhat
lower than they would be without filtering. An optional
feature shown in the schematic is the ability to switch off the
flicker filtering with an I/O bit. Switches Q3 and Q4 turn on
when the filter is disabled. In this state Q3 cuts the reference
current into U 10 and U 1, thereby turning off the adjacent
line luminance; while Q4 boosts the gain of U 11 (by an
amount set by R23) to what it should normally be without
flicker reduction.
Since when a large area of high luminance level occurs, the
video output could exceed the maximum allowed voltage, Q 5
and Q6 are used as a positive luminance peak clipper. R27
can be set so that the peak luminance level at the final video
output is 714 mY.

122

,,~~,~

~,.~~~~

..

,~,

,,~

___

~

_

II

. . . _ _ . . . . . . . u . _ _ _. _ . ___

RED
GREEN

BLUE

ANALOG PROCESSING

LINE BUFFERING/RAMDACS

~

FROM VGA

~>-

VG~VID(O 7)

:>-

COLO~KEY(O

PARALLEL ACROSS MAIlN --

FILl_LUM·

BLU-.ADJAC

BLU...,ADJAC

,-----

/FFEN

Flicker Filter Circuit for GSP500

Figure 3 - Flicker Filter Top Level Schematic
~

Z

(J1

o

w

1m

II

AN503

iRAMDACfU

III

'"

!Pc LK

,t:

.

, ,,
"e,'Q'

[C,b
12

It

Q

UPD42101

""
n
"'
"

."'"'. .
Q'
Q'

H

"t ~ "'
" "'"

8

""

74HC74

,,, '"
,

QQ

KEY!

KE Y2

~iH

'"

~~~~

"
"' "

I

:ll'.',~;
::}

r
0

I

~

cu

2

G

7
~

Q

II

I

-H-------4

6

USA
7~HC74

'r:

" ""
n
"'
"'
"!!" "'~ :

"

UP042101

,,
"'"'"' ,

."' .
QQ

~~

Q'

"'

RSTR

'"g

b-J---.----

1

*"

'f'.:
IA

"
n

~

21

02

16

D3

15

04

14

~

13

L.....!.L
L

~~

05

~~

'

'

"'"'

''~
H :!
Q4

1

IICK

1-

_ _ _ _ _ 1 _-,',.9.1:: RSTII
20

UPD42101
QQ

Q'

RS T R

p..-.!--

WE

Figure 4124

AN503

RRRRRRRR
DoODOOCD

8 9

1±:

ij

I~ ~ l

~

DOOOOoCD

01234567
PO

1+

~~

...i..Q....

PCLK

·""·,,
• «

01234567

• 00

11
N

I
C

"

..."" ,,

*ftn~~
VREF

0000

GGGG
NNNN

AAAA

DODD

AAAA

RRRRRRRR
00000000

RRR
ODD

·

01234567

....

891

....

RRRRR
00000
34567

""
" """
'"
, 11111 II
,
"' ", ,
01234567
, ""
"
'"
'" ""
"""'
'"
"'

".

123451

00000000

#=

*±t#= ..."

·
.... .... le i

3

RLNK

SYNC

"

-"'--

r-ll--f----------"

VVVV

LLLL

0123

~

-'-'--

PCLK

-'-'0000

LlLL

0123

SGGG

NNNN

0000

If' nr
l
1234

VVVV

AAAA
AAAA

'jgtjl

",

n.
,

T

Flicker Filter Line Buffering/Ramdacs
125

AN503

..
...
58.
R23

..

II.

FE.

Q'
YIIZ222

-*

..

...

R. .
••FOR •

+lZY

DELAY

"

YALU ES

LIIE OLl

1

>---1~

:t

OL1

7

R15

I

8.ZIC

RZI

•

-1~'

4 .31t

R17

4OOn.

Del., Lf lie
FI LT LU.

Ull
A0811

• C12
>---1q

RU

•

."

1. II:

T

R"

1.21

-,?-

RIO
B.ZIC
.lI
~

4.31

"0

• IV

22 •

...

20.

LUNIIUIlICE
THlESHO LO

CLIP

SET

R27

rlQ!

•• 0

2113906
Lo<

~

.1

Q'

213106

...

C1'I

OEPEtlD
IMPIDAlC!

PROPER TERNIIATIOR

4.71

-IV

Figure 5 - Flicker Filter Analog Processing

126

II

AN503

CRTC Registers
VIDEO MODES
INDEX

REGISTER

••

fY7

00

OE

OF

10

11

12

13

00

HT

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

01

HOE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

4F

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

%

8B

8B

96

%

85

8B

96

85

85

85

84

84

85

84
57

00

01

02

03

04

05

06

04

SHR

2E

2E

50

50

2F

2F

58

50

2F

58

58

58

54

57

58

05

EHR

AO

AO

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

fY7

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

09

MSL

4F

4F

4F

4F

CI

CI

CI

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER
00

01

02

03

04

05

06

VIDEO MODES
07

00

OE

OF

10

11

12

13

**

OA

CS

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OB

CE

OE

OE

OE

OE

00

00

00

OE

00

00

00

00

00

00

00

00

oc

SAH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

SAL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OE

CLH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OF

CLL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

INDEX

REGISTER
00

01

02

03

04

05

06

07

00

OE

OF

10

11

12

13

••

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VOE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

50

50

OF

OF

8F

OF
50

13

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

00

00

00

IF

00

00

OF

OF

00

00

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

CA

oc

oc

05

oc

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

*

INTERLACE

*=

Interlace Bit must be turned off for all modes

General Register
VIDEO MODES
INDEX

REGISTER

1 01 1 02 1 03 1 04 1 05 1 06 1 07 1 00 1 OE 1 OF 1 10 1 11 1 12 I 13 I ••
# 1# 1# 1# 1# 1# 1# I@I# 1# I@I# 1# 1# 1# 1#

00
00

MISCOUT

23 =
27 =
2B =
2F =

#
GenLock (GL)
OVerlay (OV)
Video Only (VO)
Graphics Only (GO)

@

22 =
26=
2A =
2E =

GenLock (GL)
OVerlay(OV)
Video Only (VO)
Graphics Only (GO)

127

II

II

AN503
Sequence Registers
VIDEO MODES
INDEX

REGISTER

I 01 I 02 I 03 I 04 I 05 I 06 I 07 I OD I OE I OF I 10 I 11 I 12 I 13 I ••
wlwlOlIOllwlwlOlloolwlOlIOlIOlIOlIOlIOlIOl

00
CLKMODE

00

** =

640 x 480 x 256 colors

Source Code for PLD US (GAL20V8) in CUPLTM Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

fl·,
fl01 ;

1/20193;
01;
Todd K. Moyer;
Integrated Circuit Systems;
Flicker Filter;

U5;

/***********************************************************************/

/*
/* VGA @ 2xNTSC rate controller with basic line flicker filtering
/*
/*

*/
*/
*/
*/

/***********************************************************************/

*/
*/
*/

/*
/* Allowable Target Device Types: g2Ov8
/*

/***********************************************************************/

/** Inputs **/
clock
;
h_sync_NTSC ;
GND
!OE
VCC

/* VGA PCLK signal
/*

*/
*/

Pin [15 .. 18]
Pin 19

[HSN_SO.. 3] ;
!line_start;

/* used by state machine
/* pointer reset line mem, act 10

*/
*/

Pin 20
Pin 21
Pin 22

!write_enable_B;
!write_enable_A;
!write_enable;

/*
/*
/*

*/

Pin
Pin
Pin
Pin
Pin

1
2
12
13
24

/* * Outputs * */

*/

*/

/* * Declarations and Intermediate Variable Definitions * * /
Field

State_HSync

= [HSN_SO.. 3];

/** Logic Equations **/

128

AN503
/* * State machine definition * * /
Sequence State_HSync
{
present 0
if h_sync_NTSC next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0
out write_enable;
present 1
if h_sync_NTSC next 2
out line start out line startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0;
present 2
if h_sync_NTSC next 3
out line start out line startAB
out write_enable out write_enable_A;
if !h_synch_NTSC next 0;
present 3
if !h_sync_NTSC next 4;
1* out write_enable; * /
if h_sync_NTSC next 3
out write_enable_A;
present 4
if !h_sync_NTSC next A;
if h_sync_NTSC next 3;
present A
if !h_sync_NTSC next 5;
if h_sync_NTSC next 3;
present 5
if h_sync_NTSC next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5
out write_enable;
present 6
if h_sync_NTSC next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 7
if h_sync_NTSC next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 8
if !h_sync_NTSC next 9;
1* out write_enable; * /
if h_sync_NTSC next 8
out write_enable_B;

129

I

AN503
present 9

if !h_sync_NTSC next B;
if h_sync_NTSC next 8;
present B

if !h_sync_NTSC next 0;
if h_sync_NTSC next 8;
present C
next 0;
present 0
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Item

Qty

1

15

Reference
CI, C2, C3, C5, C6, C7,
C8, C9, CIO, Cll, C12,
C13, C14, C15, C16

Part

Item

Qty

.1~F

15

2

R15, R18

8.2K

16

2
2

R16, R19
R17, R20

4.3K

17
18

1

R22
R25,R26

680

2

1

C4

3

1
2

DLl

10uP
400ns

IQ1,Q2

2N3904

IQ3,Q4

VN2222
2N3906

4
5
6

2
2

7

5

105,06
Rl, R14, R21, R23, R24

8

1

R2

120

9
10

1

R3

100

2

R4,R5

121

lK

11

I

3

R6
R7,R8,R9

~50

12
13

3

RIO, Rll, R12

33

14

3

R13, R27 R28

200

47

130

19

2

20

1

21
22

Reference

Part

22K
I.2K

3

R29
Ul, U9, UIO

4.7K
SC1l483CV

3

U2, U3, U4

UPD42101

23

1

U5

GAL20V8

24

1

U6

LM317

25

1

U7

TLOn

26

1

U8

74HC74

27

1

Ull

AD8ll

AN602

Integrated
Circuit
Systems, Inc.

Application Note

Theory of Operation for a GSP600 Circuit Operating
the VGA Display at 2xPAL Frequency
The solution is to run the VGA circuitry at exactly twice the
PAL rate and in a non-interlaced mode. This preserves the
full quality ofthe VGA display while the VGA is still being
gen-locked to an external PAL signal. Of course, now that
the VGA RAMDAC is running at a higher speed, another
RAMDAC will be required which runs at the PAL rate.
Also, some means will be required to accept the fast data
rate VGA output and put out the slower rate PAL data.
Under these circumstances, the VG A circuitry will be producing twice as much data as can be displayed in PAL and
therefore some of it will have to be discarded. All of the
VGA lines are used in the PAL frame, but each line is only
used for every other PAL field. In other words all the odd
numbered VGA lines may be output to PAL field I and all
the even numbered VGA lines maybe output to PAL Held
2 while both odd and even numbered lines are put out to the
VGA display in every vertical period. The VGA frame rate
is then the same as the PAL field rate; the PAL field simply
has half as many horizontal lines.

I ntrod uction
In its minimal configuration the GSP600 with a VGA controller chip puts out both RGB to a VGA monitor and
composite video in the PAL format. However, due to the
fact that PAL video is interlaced, the minimal configuration
requires that the VGA controller be programmed for interlaced operation; this allows the same RAMDACTM to be
used for both the VGA and the PAL outputs (of course the
PAL output also must be encoded). Unfortunately, the
VGA picture is somewhat degraded by interlacing - and
even worse, some VGA monitors won't lock up to the interlaced signal. Ifthis situation is not acceptable, a solution is
available that only requires a few additional parts at minimal
cost.

Block Diagram
-

._----------------+
)

1 - --I-

----.~

VGA V SYNC

'''I

VGAHSYNC

TOVGA
MONITOR

1

I
VIDEODATA
~ ------~

I

' - - - - - - - - .--+ RED
RAMDAC

"____

VGA V SYNC

.-

DATA

DAT~_

IN

OUT

"-1

1.,
1- -I DOTCUJC~~.OLLEI~Gl~~.".
L
L
t31250.mL- i I
I

I

J

k-

~

'RAMDAC

II

~-~
GREEN

~

BLUE

---r---,
I-~

ENCODER

COMPOSITE

L~o OUT
I
I

.~
I
'/I RJW CONI'ROL

I

I

~ .. - -

)

GREEN

1

GSP600

I

--+

-

BLUE

T

I

50c.=HZ'--------------.t

-

LINEBUFFEi

~

h--+-- - -

,-------=.

-

~.. -oL_ . . ~

I

\

f - I-

2xPAL
LOGIC

I

L.PCLK

J

-

_ . _ . _ . _ -.. _ . _ .
PAL RATE H SYNC
15.625 KHZ

RAMDAC

131

IS

a trademark of Brooktree Corporation

11

II

AN602
Application Circuit

Further Enhancement

One possible implementation of this idea is shown in the
accompanying schematic. Only the additional circuitry required for the 2xP AL enhancement is shown. Following is a
detailed description of the operation of the circuit; please
refer to the schematic as you read It.

Although the VGA at 2xPAL enhancement is better than
the minimal GSP600 configuration, it is still less than ideal
with respect to the PAL picture quality. It is probably
intuitively obvious to most people that throwing away half
the VGA data will result in a loss of picture quality on the
PAL output. The practically observed result ofthis is what
is generally known as "flicker", and it should be noted that
this problem plagues all scan converters and VGA-to-PAL
boards. It is worst when there is a lot of detail along the
vertical axis of the VGA image. The most annoying example
is probably a thin, bright white horizontal line made up of a
single line on the VGA display. For an example case, imagine that line 100 of the VGA display contains the white line
and the rest of the display is black. Then the white line would
appear somewhere around line SO of field 2 in the PAL
output, but not at all on field 1. The result will be a flashing
of the line with a period of 40.0 ms (due to 2SHz frame rate).
This is visually very noticeable and irritating. Because of
this, many scan converters and VGA-to-PAL boards have a
"flicker filter." Interestingly, most flicker filters can be
turned off, indicating that they are less than desirable in
some situations.

USB divides the frequency of the VGA HSync signal VHS
by two, producing a SO% duty cycle square wave with a
frequency of IS.62S kHz. This signal essentially becomes the
Write Enable signal at U 4 pin 22 and is also sent to the
GSP600 pin 60 as the Horizontal Sync signal. Note that the
addition ofa divide by2in the overallloop which the GSP600
controls forces the VGA chip to clock at twice the rate that
it otherwise would, producing a VG A H Sync frequency of
31.6S0 kHz.
U7 is a line buffer memory which can hold up to 910 pIxels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device U 4 provides a write enable and pointer reset signals to
the line memory. Note that the write clock to U7 (pin 17) is
the same rate as the VGA pixel clock; therefore everyVGA
pixel will be written in to the memory when write enable (pin
20) is active (low). The write enable is only active for every
other line, however, since it is frequency divided by 2 from
the VGA HSync as previously noted. This essentially discards half the VGA lines each PAL field, by virtue of the
fact that they are not written into memory. The time to write
a complete line into memory is I VGA line time or 32.0~s.
The read clock for U7 is simply the write clock frequency
divided by 2 by U SA. Thus to read all the pixels out of the
memory will req uire twice as long as to write them, or 64.0~s.
This is the length of a PAL line. Therefore, over the span of
2 VGA lines, I VGA line is written and I PAL line is read,
although the writing takes place at twice the PAL rate.
Data read out from U7 at PAL rate is fed to RAMDAC U I,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to + SV. In this way anything written to the VGA RAMDAC (such as changes to
the palette) will also be written to U I, but any reads will not
cause a conflict with the main VGA RAMDAC. The analog
RGB outputs ofU I are sent to the PAL encoder to produce
a composite video output. U 3 provides a reference for the
RAMDAC. Instead of a reference for each RAMDAC, it
may be possible to use I voltage reference for both RAMDACs in the system if they can be configured to use a voltage
reference as shown in the schematic.

132

A discussion offlicker filtering and howto implement it with
the GSP600 is the subject of Application Note AN603.

(I
TQ Ck·y Compa,OATOO - OAT07
To VGA Chip

RAWofoo 07]
0

Polol- Dolo
U7

~

UP0.42101

U6A

+5Y
OA1[00-071

~o1

~

74HC04

K

'"

VG'" Ha'll Sync

r.om

--L

VGA ChIp

,--

....
~

~ To

SClt.46JCV

!N/C
To GSPWO

RAM-OAe

~so
p 0
18 51

P,II 60

PUIO

v~rt:
OPA 30

52

7

.5V

", "
.r1

10

["cod"',

U6B

74HC04
Pin 1. vee

P,,, 7 GND

U6C

7

74HC04
To Dolo Bus

CPU(OO 12)

+808<0> Thru +808<7>

l>
z
m

oI\)

-

AN602
CRTC Registers
VIDEO MODES
INDEX

REGISTER
00

OJ

02

03

04

05

06

07

OD

DE

OF

10

II

12

13

HT

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

4F

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84
57

00
01

- - ,

**

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54

57

58

05

EHR

AD

AO

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

07

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

09

MSL

4F

4F

4F

4F

C1

Cl

C1

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

DE

OF

10

11

12

13

**

CS

OD

OD

OD

OD

00

00

00

OD

00

00

00

00

00

00

00

00

OB

CE

OE

OE

OE

OE

00

00

00

DE

00

00

00

00

00

00

00

00

oc

SAH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OD

SAL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OE

CLH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OF

CLL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

**

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

VIDEO MODES

OA

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

5D

5D

DF

DF

8F

DF
50

13

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

00

00

00

IF

00

00

OF

OF

00

00

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

DC

oc

05

OC

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

*

INTERLACE

DE

I OF I
I @ I

10

13

I **
I #

*=

~

Interlace Bit must be turned off for all modes

General Register
VIDEO MODES
INDEX

REGISTER
00

00

MISCOUT

23 =
27 =
2B =
2F =

#

I
I

#
GenLock (GL)
OVerlay (OV)
Video Only (VO)
Graphics Only (GO)

01
#

I
I

I
I

02
#

03
#

I
I

04
#

I
I

05
#

I
I

06
#

@

22 =
26=
2A =
2E =

GenLock (GL)
OVerlay(OV)
Video Only(VO)
Graphics Only (GO)

134

I 07 I
I @ I

OD
#

I
I

#

#

I
I

11
#

I
I

12
#

I
I

#

II

AN602

Sequence Registers
VIDEO MODES
INDEXI

REGISTER

001

CLKMODE

I

00

09

J 01 I 02 1 03 I 04 I 05 I 06 1 07 1 OD
I 09 I 01 J 01 1 09 1 09 1 01 1 00 1 09

1 OE

1 OF

1 \0

1 11

1 12

1 01

1 01

1 01

1 01

1 01

** = 640 x 480 x 256 colors

Source Code for PLD U4 (GAL20V8) in CUPLTM Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

2PAL;

XXXXX;
12107/92 02:12pm;
02;
Todd K. Moyer;
Integrated Circuit Systems;

XXXXX;
XXXXX'

j***********************************************************************j

/*
/* VGA
/*
/*

*1
@

2xPAL rate controller

*1
*1
*I

j***************************************************** ******************/

1*
1* Allowable Target Device Types: g20v8

*1
*1
*1

/*

j***********************************************************************j

/** Inputs **1
Pin 1
Pin 2

clock
h_sync_PAL;

Pin 12
Pin 13
Pin 24

GND
JOE
VCC

/* VGA p-clock

*1

/*

*I

/* used by state machine

*1

1* * Outputs * * I
Pin
Pin
Pin
Pin
Pin

[15 .. 18]
19
20
21
22

[HSN_SO .. 3];
!line_start;
!write_enable_B;
!write_enable_A;
!write_enable;

/* pointer reset line mem, act 10
/* not used by 2xPAL
/* not used by 2xPAL
/*

/* * Declarations and Intermediate Variable Definitions * * I
Field

State_HSync

/* * Logic Equations * * I

135

*1

*1
*1

*1

1 13

I

**

J 01 I 01

I

AN602
1* * State machine definition * * /
Sequence State_HSync
{
present 0
if h_sync_PAL next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_PAL next 0
out write_enable;
present 1
if h_sync_PAL next 2
out line_start out line_startAB
out write_enable out write_en able_A;
if !h_sync_PAL next 0;
present 2
if h_sync_PAL next 3
out line_start out line_startAB
out write_enable out write_en able_A;
if !h_synch_PAL next 0;
present 3
if !h_sync_PAL next 4;
1* out write_enable; * /
if h_sync_PAL next 3
out write_en able_A;
present 4
if !h_sync_PAL next A;
if h_sync_PAL next 3;
present A
if !h_sync_PAL next 5;
if h_sync_PAL next 3;
present 5
if h_sync_PAL next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5
out write_enable;
present 6
if h_sync_PAL next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 7
if h_sync_PAL next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 8
if !h_sync_PAL next 9;
1* out write_enable; * /
if h_sync_PAL next 8
out write_enable_B;

136

AN602
present 9

if !h_sync_PAL next B;
if h_sync_PAL next 8;
present B

if !h_sync_PAL next 0;
if h_sync_PAL next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Part Name

Description

Manufacturer

Item

Qty

1
2

1

74HC04

HEX INVERTER

Motorola

I

74HC74

Motorola

3

1

SC1l483CV

DUAL D FLIP FLOP
RAM-DAC

4

I

GAL20V8

PLD

Lattice

5

I

LM317

Adiustable ReRulator

National

6

I

UPD42101

9lOx8 FIFO

NEC

7

CAP

.1uF Cap

8

7
1

R1I4W

240 ohm

9

1

R1I4W

150 ohm

10

3

R1I4W

24 ohm

137

Sierra

I

138

AN603

Integrated
Circuit
Systems, Inc.

Application Note

Flicker Reduction Circuit for use with the GSP600
A single horizontal line in the VGA image has only a 50/50
chance of being displayed in PAL, depending on which line
number it appears on. Obviously, this method leaves a lot
to be desired, since some details in the VGA image can be
completely absent from the PAL signal; most people would
judge it unacceptable.

Introd uction
Although a minimal configuration GSP600 VGA/PAL system uses all of the lines of the graphics image to generate
the PAL picture, the resulting PAL display is not (and
cannot be) as good as the original VGA display. Despite the
fact that all the lines are used, on the standard non-interlaced VG A display every line is used for every vertical period
of about 20.0 ms, while it takes twice as long to put out all
the lines to the PAL picture (40 ms). This is accomplished
in practice by one of two ways: 1) interlacing the VGA
(slowing it down to PAL rates), or 2) using odd numbered
lines for odd PAL fields and even numbered lines for even
fields, essentially discarding half the lines that are output
from the VGA (see the Application Note AN602, Theory of
Opemtion for a GSP600 Circuit Opemting the VGA Display
at 2 x PAL Frequency). It is probably intuitively obvious that
either slowing the VGA down or throwing away half the
VGA data will result in the PAL output looking less pleasing
than the standard VGA display. The practically observed
result of this is what is generally known as "flicker", and it
should be noted that this problem plagues all scan converters and VGA-to-PAL boards; it is a fundamental limitation
of the PAL standard. It is worst when there is a lot of detail
along the vertical axis of the VGA image. The most annoying example is a thin, bright white horizontal line made up
of a single line on the VGA display. For an example case,
imagine that line 100 of the VGA display contains the white
line and the rest of the display is black. Then the white line
would appear somewhere around line 50 of field 2 in the
PAL output, but not at all on field 1. The result will be a
flashing of the line with a period of 40.0 ms (reciprocal of
the 25 Hz frame rate). This is very noticeable and quite
irritating to the eye.
Knowing that displaying a VGA image on an PAL monitor
is at best a compromise, we would at least like to achieve the
best possible performance from the conversion. Because of
this, most scan converters and VGA-to-PAL boards have a
"flicker filter." It is enlightening to note that most flicker
filters can be turned off, indicating that they are less than
desirable in some situations. In fact they reduce the spatial
'bandwidth" in the vertical direction, or in other words
reduce the vertical resolution. A particularly simple and
effective flicker reduction scheme (which can be implemented in software) is to repeat every other VGA line in
both fields of the PAL signal. This method, however, requires that halfthe VGA lines never get to the PAL display;
in other words, the vertical resolution is cut in half.

You can get a feel for how a better typical flicker filter works
by thinking about the example above of a single white horizontalline on scan line 50 offield 2. Imagine "spreading" the
line so that some of it spills into the scan lines adjacent to
the original line. In an interlaced system such as PAL this
means reducing the brightness ofline 50 offield 2 (thereby
making it gray), and putting some darker shade of gray into
lines 50 and 51 offield I, which are above and below line 50
of field 2, respectively, once the complete frame has been
scanned. If done properly, in the right proportions, and
viewed from a sufficient distance, the new wide line looks to
be of the same brightness as the original single white line.
This can significantly reduce the flicker, since there is no
longer the situation of black on field I and white on field 2
rapidly alternating. However, as you can imagine, anyrapid
vertical transitions would also become smeared or blurred
with such a scheme. The typical complaint is that when
trying to display text on an PAL display, a flicker filter will
make the text less readable (if it remains readable at all).
This type of flicker reduction works best if only the luminance portion of the signal is filtered, since the mixing of
several VGA lines to make one PAL line can significantly
change the saturation and hue of the color displayed, seriously altering the picture when compared with the VGA
display. It is primarily changes in luminance level that cause
flicker, so that leaving the chrominance portion of the signal
unchanged does not seriously degrade the flicker reduction
that is achieved, while it does tend to preserve the look of
the image.
To boil all this down, there is a trade-off between flicker
reduction and vertical resolution, and it bears repeating that
it is a practical impossibility to make an PAL image look just
as good as a high resolution VGA image. To try and work
around this trade-off, some sophisticated flicker filters are
"adaptive", which essentially means that they will dynamically turn themselves on when especially needed to reduce
flicker and off when the loss of vertical resolution is especially detrimental. Predictably, this approach is rather expensive and takes up a lot of circuit board space, at least
until the time when this function is incorporated into a
monolithic integrated circuit. At any rate, a flicker filter of
the more basic varietyis presented here for use with GSP600
applications.

139

I

II

AN603
Application Circuit
In the accompanying schematic and block diagram an implementation of a simple luminance-only flicker filter which
works with the GSP600 in a VGA-to-PAL system is shown.
The schematic details only the portion of the system specific
to the flicker filter function, since the VGA portion will vary
depending on the VGA chip used. Please refer to the
schematic when reading the following detailed circuit description.
U8B divides the frequencyofthe VGA_HSYNC signal VHS
by two, producing a 50% duty cycle square wave with a
frequency of 15.625 kHz. This signal essentially becomes
the Write Enable signal at U 5 pin 22 and is also sent to the
GSP600 pin 60 as the Horizontal Sync signal
PAL_RATE_HS. Note that the addition of a divide by 2 in
the overall loop which the GSP600 controls forces the VGA
chip to clock at twice the rate that it otherwise would,
producing a VGA HSync frequency of31.25 kHz.
U2 is a line buffer memory which can hold up to 910 pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device US provides a write enable and pointer reset signals to
the line memory. Note that the write clock to U2 (pin 17) is
the same rate as the VGA pixel clock; therefore, everyVGA
pixel will be written in to the memory when write enable (pin
20) is active (low). The write enable is only active for every
other line, however, since it is frequency divided by 2 from
the VGA HSync as previously noted. This essentially discards half the VGA lines each PAL field, by virtue of the
fact that they are not written into memory. The time to
write a complete line into memory is 1 VG A line time or 32.0
Ils. The read clock for U2 is simply the write clock freq uency divided by 2 by U 8A. Thus, to read all the pixels out
ofthe memory will require twice as long as to write them, or
64.lls. This is the length of a PAL line. Therefore, over the
span of 2 VG A lines, 1 VG A line is written and 1 PAL line
is read, although the writing takes place at twice the rate.

Data read out from U2 at PAL rate is fed to RAMDAC U9,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to + 5V. In this way anything written to the VGA RAMDAC (such as changes to
the palette) will also be written to U9, but any reads will not
cause a conflict with the main VGA RAMDAC. The analog
RGB outputs ofU9 are sent to the PAL encoder to produce
the chrominance component of the composite video output.
U 6 provides the required voltage reference to U9. Also, the
RGB outputs from U9 are combined by resistor matrix in
the right proportions to create a luminance signal which can
be summed with the adjacent lines' luminance signals,
thereby spatially lowpass filtering the luminance signal in the
vertical dimension.
Up to this point the circuitry described is basically the same
as is required to make the VGA run at 2 x PAL rates (see
the Application Note AN602, Theory of Operation for a
GSP600 Circuit Operating the VGA Display at 2 x PAL
Frequency). Note that there are an additional 2 line buffers
(U3 and U4), 2 RAMDACs (UIO and UI), and 2 current
references (U7 A, Q 1, and Q2). The additional 2 line buffers
store the VGA lines before and after the current line being
output via U2 and U9. The RGB current outputs from the
RAMDACs U 10 and U 1 are connected together, summing
the two sets ofRGB currents together. The combined RGB
signals from U 10 and U 1 are then matrixed together in the
proper proportions to produce an adjacent-lines luminance
signal. This signal amplitude is independent of the main
luminance signal so that the ratio of adjacent line to main
line luminance can be set to any desired value, primarily by
adjusting R 1, which controls the reference currents into U 10
and U 1.

140

AN603
1----

VGA

--lr--"VYD;.:.Gto",~;...A}T...
EA_+_......~

ICONTROLL~

VGA HORIZ SYNC

I

___

i-

f- DOTCLOCK

~

I

.
!

:

RGB TO VGA MONITOR

L--t:BUFF~R~ R-AM-D-A-~

GSP600

PAL HORIZSYNC

L_

J____---!

PCLKI

1~·8
~I
BY2

__~:_~_~_~

I

--I ___

r----I

---

8

J

~
1
~--+- -L
4 Ce~J~gL~- -I-·'=------.--~

I

LINE BUFFER

/

RAMDAC

--..

-1

--W-R-ITEl-..

-

LINE

-- . I

I

I

BUFF~

\'1

-1 ~

RAMDAC

~~IY~N

I

-~--~J

I

-------'- - - - - -

I

,i '''OC-E-R-~~~~!~T

.-];

~

-

MA TRIX!

~~

f--AMPLlFIE~

LU~~~lfE
FILTERED

SUMMER

]

~J

I,,"

Lfl"'2J
Figure 1

The two luminance signals are connected together, summing
them at the input to amplifier U 11. U II then makes up for
the resistive losses in the R G B matrices and drives the
luminance delay line, whose output is the luminance component of the encoded composite signal. Most encoders
have a luminance output and input which allows for an
extcrnal delay line; not using the output provided while
driving the input with an alternate luminance signal of the
right amplitude, delay, and polarity allows convenient summing with the chrominance signal generated by the encoder
to create the composite video signal.

Programmable logic chip US controls the writing of VGA
lines into the line buffers such that U2 receives every other
line, U 3 receives every fourth line, and U 4 receives every
fourth line, as shown by the timing diagram in Figure 2. Note
that only one line buffer is write enabled at a time and every
line is written to a line buffer. With this scheme U 2 always
contains the main VGA line which is going out to the PAL
encoder, while U3 and U4 contain the lines adjacent to the
main line. The CUPUMlanguage source code for PLD US
is included later in this note.

AN603
All of the line buffers are continuously read enabled, such
that the RG B signal output to the encoder is a combination
of the main line and the 2 adjacent line signals. U7A, Ql,
and Q2 make up a dual matched current reference for
RAMDACs U 10 and U 1. The amplitude of the adjacent
line video signals summed in with the main line is adjustable
with R 1; the optimum value could be determined so that R 1
could be replaced with a fixed divider to save the cost of the
trimmer. The amplitude of the main line video signal is
controllable by the value ofR6 ifit is necessary to adjust the
proportion of the main line signal that gets summed into the
final output. The relative weight of the 2 adjacent line signals
in the output is the same due to the matching of the current
references into U 10 and U I; this should be best for most
applications since it is symmetrical about the main line.

BIOS
The video BIOS for the circuit presented here will have to
be modified from the typical GSP600 VGA/PAL system;
therefore, register setups for various video modes are given
in several tables later in this note.

The luminance amplitude is controllable by varying the gain
of U 11 (set by the value of R22); this should normally be set
so that luminance levels on any given line are somewhat
lower than they would be without filtering. An optional
feature shown in the schematic is the ability to switch off the
flicker filtering with an 110 bit. Switches Q3 and Q4 turn on
when the filter is disabled. In this state Q3 cuts the reference
current into U 10 and U 1, thereby turning off the adjacent
line luminance; while Q4 boosts the gain of U 11 (by an
amount set by R23) to what it should normally be without
flicker reduction.
Since when a large area of high luminance level occurs, the
video output could exceed the maximum allowed voltage, Q5
and Q6 are used as a positive luminance peak clipper. R27
can be set so that the peak luminance level at the final video
output is 714 mY.

142

RG~JO EN~ODER - TO PROD~CE CHROMINANCE S~

II

i

,-- - - - - -----(ilLuEJ

'''>"""-""1
~R8gtXI8~~DATA L:::G~VGA_VID(O
7l

GREEN-rBLUE-+-

C~~~~~M~~'l~D~~AIN~~C(O

...

11)

_

GREEN

l

..

BLUE

FILT_LUM

FI~ ~g~~~oL~~IN:~r?pEU~IGNAL

7)

COLOR_KEY[O 7)

TO GENERATE KEY SIGNAL

T~~S~~ ~I~Y~OC (HALF VGA RATE) [PAL_RA~-

------

I

REOi"

VGA HSVNC

~~~8~~~~~~~~~JgU'T _~6R_KEY(O

ANALOG PROCESSING

1=ti:jRED

PCLK

FROMVGA

r-

RAMDAC(O 11)

RED

ADJACE

GRN_ADJAC

PALRATUIS

e

tRED-ADJAC
---

ElLU_ADJAC

GRN_ADJAC
IlLU_ADJAC

I
FLICKER FILTER ENABLE
BIT FROM OUTPUT PORT
(LO", FLICKER FlilER ENABLE)

IFFEN;

~ /FFEN

__d""
Flicker Filter Circuit for GSP 600

Figure 3 - Flicker Filter Top Level Schematic

l>

z

0')

o
w

•

II

AN603
•

In YlDEO

DATA flOlI

WlA

II

He

'-t-rt----4--~....J-"Li,

".

UTII

I
1

C~K IQ~~-----H--t--~~-----------1
•

1

I

I

Q

I

I

7 74Ht74
'I'

'r:

::
I~~~~~::[D[:!-rll,',:m··,:~~~~~~~
~'

lh.u

101

~~l

,,ou~' r'-.-I

""'"

J,.

IS

11

?+--

~

~__lf_--.l-L.!.tLi

.e,'f---::L

TLOU

~

•

..

::

07

FH"
'
: 1 .: :::.-':,,~""'"
fl'

::

'EE

f---::L

~~

-:::-

II

100

ICC----L

UTII

I

UTI

lIE

0

lE

\>-t--

os

r ...
I'

11

Q7

1~IfCK

nU04

11.
E"

~

nuzz
II

111

"

.. . 'II: ,...... .:
. .." ......" .

UPD41l01

DO
D1

1

L.u...

os

It 14--"'---.l

lit I[

L _ _ _ _ _I-'_...1'",'( U TIl •
10

IIIIE

I

un :r-1-RE

I

Figure 4144

AN603

.....

17

I'

47

47

110
!II

Flicker Filter Line Buffering/Ramdacs
145

Illl
!IS

AN603

...
"
...

Q4

.24

'112222

FE

"

-!

•• 0

.....
+ 12 y

f-H-'i

...
...

~
'1;Y

7

•

8.21:

U11
AD811

•• 3 K

~~

4

e12

-12 ,

."

..5 & 126 VALUES DEPEND
O. PROPER TERIIIIIA.TIDII IMPEDANCE
FOR DELAY LINE DLl

ell

...
1.211:

DLl

s
Dal., L tn,
40 Oft

FIL T LU'

T
+

22<

...
...
...

8.21:

4.3 K

"0

... ...
2 DO

LUMI.AII( E eLI P
THRESHOLD

SET

0"

zoo
r l Q 52113'01

""$c

r

.1

Q5
2113'01

...

=
Cl'I

.2 •
1. 2 K

4.7 K

-5Y

Figure 5 - Flicker Filter Analog Processing
146

AN603
CRTC Registers

..

VIDEO MODES
INDEX

REGISTER
07

OD

OE

OF

10

11

12

13

00

HT

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

01

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

4F

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84
57

()()

01

02

03

04

05

06

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54

57

58

05

EHR

AO

AO

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

07

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

09

MSL

4F

4F

4F

4F

C1

C1

C1

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER
()()

01

02

03

04

05

06

..

VIDEO MODES
07

OD

OE

OF

10

11

12

13

OA

CS

OD

OD

OD

OD

()()

()()

()()

OD

()()

()()

()()

()()

()()

()()

()()

()()

OB

CE

OE

OE

OE

OE

()()

()()

()()

OE

00

()()

()()

()()

()()

()()

()()

()()

DC

SAH

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

00

()()

()()

()()

()()

OD

SAL

()()

()()

()()

00

()()

()()

00

()()

()()

()()

()()

()()

()()

()()

()()

()()

OE

CLH

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

OF

CLL

()()

()()

()()

()()

00

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

()()

INDEX

REGISTER
()()

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

..

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

5D

5D

DF

DF

8F

DF
50

13

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

()()

()()

()()

IF

()()

()()

OF

OF

()()

()()

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

CA

DC

DC

05

DC

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

•

INTERLACE

* = Interlace Bit must be turned off for all modes

General Register
VIDEO MODES
INDEX
()()

REGISTER
MISCOUT

23 =
27 =
2B =
2F =

()() I
# I

#
GenLock (GL)
OVerlay (OV)
Video Only (VO)
Graphics Only(GO)

01

#

I
I

I
I

02

#

03

#

I
I

04

#

I
I

05

#

I
I

06

#

@

22 =
26=
2A =
2E =

GenLock (GL)
OVerlay(OV)
Video Only (VO)
Graphics Only (GO)

147

I
I

07

@

I
I

OD

#

I
I

OE

#

I
I

OF

@

I
I

10

#

I
I

11

#

I
I

12

#

I
I

13

#

I
I

*.
#

I

II

AN603
Sequence Registers
VIDEO MODES
INDEX

REGISTER
00

00

** =

CLKMODE

09

I
I

01
09

I
I

02
01

I
I

03
01

I
I

04
09

I
I

05
09

I
I

06
01

I
I

07
00

I
I

OD
09

I
I

OE
01

I
I

OF
01

640 x 480 x 256 colors

Source Code for PLD US (GAL20V8) in CUPLTM Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

ff·,
ff01 ;

1/20/93;
01;
Todd K. Moyer;
Integrated Circuit Systems;
Flicker Filter;
U5;

/***********************************************************************/

1*
1* VGA
1*
/*

@ 2xPAL rate controller with basic line flicker filtering

*1
*1
*1
*1

/***********************************************************************/

*1
*1
*1

/*
/* Allowable Target Device Types: g2Ov8
/*

j***************************************************** ******************/

/** Inputs **1

clock
;
h_sync_PAL ;
GND
!OE
VCC

/* VGA PCLK signal
/*

*1
*1

Pin [15 .. 18]
Pin 19

[HSN_SO .. 3];
!Iine_start;

1* used by state machine
/* pointer reset line mem, act 10

*1
*1

Pin 20
Pin 21
Pin 22

!write_enable_B;
!write_enable_A;
!write_enable;

1*
1*
1*

*1
*1
*1

Pin
Pin
Pin
Pin
Pin

1
2
12
13
24

/* * Outputs * * 1

1* * Declarations and Intermediate Variable Definitions * * 1
Field

State_HSync

=

[HSN_SO.. 3);

/** Logic Equations **1

148

I
I

10
01

I
I

11
01

I
I

12
01

I
I

13
01

I "
I 01

AN603
/* * State machine definition * * /
Sequence State_HSync
{
present 0
if h_sync_PAL next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_PAL next 0
out write_enable;
present 1
if h_sync_PAL next 2
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_PAL next 0;
present 2
if h_sync_PAL next 3
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_synch_PAL next 0;
present 3
if !h_sync_PAL next 4;
/* out write_enable; * /
if h_sync_PAL next 3
out write_enable_A;
present 4
if !h_sync_PAL next A;
if h_sync_PAL next 3;
present A
if !h_sync_PAL next 5;
if h_sync_PAL next 3;
present 5
if h_sync_PAL next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5
out write_enable;
present 6
if h_sync_PAL next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 7
if h_sync_PAL next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 8
if !h_sync_PAL next 9;
1* out write_enable; * /
if h_sync_PAL next 8
out write_enable_B;

149

I

AN603
present 9

if !h_sync_PAL next B;
if h_sync_PAL next 8;
present B

if !h_sync_PAL next 0;
if h_sync_PAL next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Item

Qty

1

15

Reference
Cl, C2, C3, C5, C6, C7,
CS, C9, ClO, Cll, C12,
C13, C14, C15, C16

Part

.l1JF

2

1

C4

3

1

DLl

4

2

IQl,Q2

2N3904

5

2

IQ3.Q4

VN2222

105,06
Rl, R14, R21, R23, R24

2N3906

lOuF
40008

6

2

7

5

S

1

R2

120

9

1

R3

100

10

2

R4,R5
R6
R7, RS, R9

121
150

lK

11

1

12

3

13

3

RlO,Rll,R12

33

14

3

R13, R27 R2S

200

47

156

Qty

15

2

R15, RlS

S.2K

16

R16, R19

4.3K

17

2
2

R17, R20

22K

IS

1

19

2

R22
R25,R26

l.2K

20

1

21
22

3

Reference

Part

Item

6S0

R29
Ul,U9,UlO

SC1l4S3CV

4.7K

3
1

U2, U3, U4

UPD42101

23

U5

GAL20VS

24

1

U6

LM317

25
26

1
1

U7
US

TLOn
74HC74

27

1

Ull

ADSll

ICS

Video Timing Generator
Products

As the recognized world leader in frequency synthesis technology, ICS continues to build on its solid
foundation, bringing the most requested features to market.

In particular, ICS has expanded video clock product offerings to provide a truly complete selection
unequaled in performance, breadth and value. These new products are available now.
New products in this edition offer advanced features like full user-programmability to offer you the
maximum in design flexibility.
As a market-oriented company, ICS welcomes inquiries concerning our new product areas or other
frequency synthesis applications.

151

I

les Video Timing Generator Selection Guide
Product
Application

P.e.
Clocks

ICS
Device Type

I

Max
Frequency

Clock
Outputs

Package
Types

Page

ICS1394

External Loop Filter.
For New Designs. Use ICSI494A.

85MHz

I TTL

20 Pin
DIP, sorc

153

ICSl494A

Buffereq Xtal Out, Lock Detect
Output.

135 MHz

I TTL

20 Pin
DIP, sorc

155

ICS2494/94A

Buffered Xtal Out, Lock
DetectOutput.

l35 MHz

2TTL

20 Pin
DIP, SOIC

161

ICS2495

Small Footprint, Narrow Body
sorc Package.

135 MHz I 2TTL

16 Pin
DIP, sorc

167

ICS2496

Low Voltage, 3/5 Volt Operation
for Laptop/Notebook
Applications. Powerdown Mode.

85/135
MHz

2TTL

16Pin
DIP, sorc

173

ICS2595

Programmable Dual
ICS2494 Pin Compatible.

135 MHz

2TTL

20 Pin
DIP, SOIC

179

ICS82C404

Dual Programmable Graphics
Clock Generator. ICS82C404
Compatible.

120MHz

2TTL

Dual Programmable Graphics
Clock Generator. ICD2061
Compatible

135 MHz

Dual Video memory Clock
Generator with 16
Preprogrammed Video and 4
Preprogrammed Memory
Frequencies.

135 MHz

Drop-in upgrade for the
WD90C6l.
Integral Loop Filters.

80MHz

WD90C31 VGA Controller
Compatible. Enhanced Version.
Integral Loop Filter.
(Replaces ICS90C63, ICS9OC64.)

80MHz

Low Voltage, 3/5 Volt.
Powerdown Mode.
WD 90C26 VGA Controller
Compatible.

80MHz

ICS9161

AV9194

ICS90C61A

Western Digital
Compatible
Clock
Generators

Features

ICS9OC64A

ICS90C65

--

3TTL

2TTL

16Pin

i DIP, SOIC
l6Pin
DIP, sorc

I

189

223

20 Pin
DIP, SOIC
237

2 TTL

2TTL

2TTL

20 Pin
DIP, sorc,
PLCC

193

20 Pin
DIP, sorc,
PLCC

203

20 Pin
DIP, sorc,
PLCC

213

Notes:
l. All products have internal loop filters except as noted.
2. All products operate at 5 volts typo except as noted.

ADVANCE INFORMATION documentscontam mformatIOn on new products In the samphngor preproductIOn phase of development. CharacterIstIc
data and other speclficatJOns are subject to change Without noHee
PRODUCT PREVIEW documents contam mformatlOn on products In the formative or deSIgn phase of development Charactenstlc data and other
specifICatlOTIS are deSign goals. res reserves the fIght to change or dlscontmue these products WIthout notice

152

•

ICS1394

Integrated
Circuit
Systems, Inc.

Video Dot Clock Generator
Features

Applications

Low cost - eliminates need for multiple crystal clock
oscillators in video display subsystems

85 MHz Guaranteed Performance
EGA - VGA - Super VGA XGA video adapters

Strobed itransparent frequency select options

High resolution MAC II displays

Mask-programmable frequencies

Workstations

Glitch-free frequency transitions
Compatible with Industry STD VG A Controllers
Provision for two external frequency inputs
Low power CMOS device technology
Small footprint - 20 pin DIP or SO

Introduction
FS2

Principal applications for these products include generating
dot clock frequencies for EGA, VGA, Super VGA, and
XGA graphics products in the IBM-compatible world, as
well as for high resolution MAC II and workstations. Applications utilizing 8514A and TMS 34010 and TMS 34020
benefit as well, with significant performance improvements
and cost reductions in all of these applications.

STROBE

2

19

FSI

VDD

3

18

FSO

FS4IFREQI

4

17

AVSS

XTALl

5

16

OP(+)

XTAL2

6

15

OP(-)

FREQO

7

14

OP(OUT)

VSS

8

13

VCO(IN)

FOUT

9

12

AVDD

CPSEL

10

11

POUT

Ordering Infonnation
ICS1394NXXX (DIP Package)
ICS1394MXXX (SO Package)
(XXX = Pattern number)

153

154

ICS1494

Integrated
Circuit
Systems, Inc.

Enhanced Video Dot Clock Generator
Features

Features

• Low cost - elimmates need for multiple crystal clock
oscillators in video display subsystems

•
•
•
•
•
•
•

• Mask-programmable frequencies
• Pre-programmed versions for Industry Standard VGA
chips
• Glitch-free frequency transitions
• Provision for external frequency input
• Excellent power supply rejection

135 MHz Guaranteed Performance
Fast acq uisition of selected freq uencies
Internal loop filter eliminates noise pickup
Advanced PLL for low phase-jitter
Improved loop stability over entire frequency range
Frequency change synchronized to vertical retrace
Frequency change-detection circuitry enhances new frequencyacquisition

Applications

• Lock Detect Output
• Buffered XT AL Out

•
•
•
•
•
•

Pin Configuration

Higher Frequency applications
EGA - VGA - Super VGA-XGA video adapters
High resolution MAC II displays
Workstations
LCD and other flat panel display systems
8514A - TMS 34010 - TMS 34020

Description

FS3

The ICS1494 Dot Clock Generator is an integrated circuit
capable of generating up to 32 video dot clock frequencies
for use with high performance video display systems. Utilizing CMOS technology to implement all linear, digital and
memory functions, the ICS1494 provides a low power, small
footprint, low cost solution to the generation of video dot
clocks. Outputs are compatible with VGA, EGA, XGA,
MCGA, CGA, MDA, as well as the higher frequencies
needed for advanced applications in desktop publishing and
workstation graphics. ProvisIOn is made via a single-level
custom mask to implement customer-specific frequency
sets. Phase-locked loop circuitry permits rapid glitch-free
transitions between clock frequencies.
In addition to providing 32 clock rates, the ICS1494 has
provisions to multiplex an externally-generated signal
source into the FOUT signal path. The ICS1494 can also be
programmed to select the crystal oscillator signal as the
FOUT output. Internal phase-locked frequencies continue
to remam locked at their preset values when these modes
are selected. This feature permits instantaneous transition
from an external frequency to an internally-generated frequency. Printed circuit board testing is simplified by the use
of these modes, as an external clock generated by the ATE
tester can be fed through, permitting synchronous testing of
the entire graphics system.

20

FS2

STROBE

2

19

FSI

VDD

3

18

FSO

FS4

4

17

VSS

XTALl

5

16

LOCK

XTAL2

6

15

XTALOUT

EXTFREQ

7

14

N.C.

VSS

8

13

N.C.

FOUT

9

12

AVDD

10

II

VSS

VERTBLANK

Notes:
1. In applicatIOns where the external frequency mput IS not specIfIed,
EXTFREQ must be tIed to VDD.
2. ICS 1494M( SO) plllout IS IdentIcal to ICS I 494N (D IP).

155

Ordering Information
ICS1494NXXX (DIP Package)
ICS1494MXXX (SO Package)
(XXX = Pattern number)

ICS1494
Circuit and Application Options

Power Supply Conditioning

The ICS1494 will typically derive its frequency reference
from a series-resonant crystal connected between pins 5 and
6. Where a high quality reference signal is available, such as
in an application where the graphics subsystem is resident
on the motherboard, this reference may directly replace the
crystal. This signal should be coupled to pin I. lethe reference signal amplitude is less than 3.5 volts, a .047 microfarad
capacitor should be used to couple the reference signal into
XTALI. Pin 6 must be left open.

The ICSI494 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and
noise-free power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figures 1 or
2. Figure I is the normal configuration for 5 Volt only
applications. Which of the two provides superior performance depends on the noise content of the power supplies.
In general, the configuration of Figure I is satisfactory.
Figure 2 is the more conventional if a 12 Volt analog supply
is available, although the improved performance comes at a
cost of an extra component. The cost of the discretes used
in Figure 2 is less than the cost of Figure I's discrete components.

The ICSI494 is capable of multiplexing an externally generated frequency source of FOUT via a mask option, in addition to its internally generated clock.
This is input via EXTFREQ (7). When an external source is
selected the PLL remains locked to the value specified in the
selected address. This provision facilitates the ability to
rapidly change frequencies. When this option is not specified
in the ROM pattern, pin 7 is internally tied to Voo and
should be connected to Voo on the PCB.

Figure 1

The number and differentiation of the analog and digital
supply pins are intended for maximum performance products. In most applications, all Voos may be tied together.
The function of the multiple pins is to allow the user to
realize the maximum performance from the silicon with a
minimum degradation due to the package and PCB. At the
frequencies of interest, the effects of the inductance of the
bond wires and package lead frame are non-trivial. By using
the multiple pins, ICS minimized the effect of packaging and
minimized the interaction of the digital and analog supply
currents.

22

+5V

Rl.,b2 -11

~ ~2
FS3
STROBE
FS4

1
2

~

~
4

~

~OIl4.318M 5
JI

EXTFREQ
FOUT
VERTICAL
BLANKING
PULSE

6

ICS1494

20
19
18
17
16
15

7

r1-1

~

~

~

~

9

v

to

~

11

_L

156

FS2
~

FS1

FSO

~

LOCK
XTALOUT

II

ICS1494
the graphics adapter board. XTAL2 (6) must be left open in
this configuration.

Applications

LOCK

Layout Considerations
Utilizing the ICSI494 in video graphics adapter cards or on
PS2 motherboards is simple but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components not related to the ICSI494 do not share its ground. In
applications utilizing a multi-layer board, Vss should be
directly connected to the ground plane. Multiple pins are
utilized for all analog and digital Vss and Vdd connections
to permit extended frequency VCLK operation to 135 MHz.
However, in all cases, all Vss and VDD pins should be
connected.

Figure 2
+5V

WCK(16) is an output signal which may be monitored to
indicate when the ICSI494 has achieved phase lock after a
change in frequency has been selected. In systems where it
is used, it is tied to an interrupt input to the microprocessor.
When high, it indicates phase lock has been achieved.

Buffered XTALOUT
In motherboard applications, it may be desirable to have the
ICSI494 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
To do this, the XTALOUT (15) output should be buffered
with a CMOS driver.

Output Circuit Considerations

,Jg.

1

,r--2<1

F53
STROBE

,.

2

I.

L.......l.

7

4

ICS
1494

~""'
••" 5
~
7

EXTFREO

---..!l

•

FOUT
VERTICAL
BUNKING
PULSE

10

'--

~

•

,.

FS2
F51
FSO

LOCK
XTALOU

13

leaf

.,.

.

12.0\

-

As the dot clock is usually the highest frequency present in
a video graphics system, consideration should be given to
EM!. To minimize problems with meeting FCC EMI requirements, the trace which connects FOUT(9) and other
components in the system should be kept as short as possible. The ICSI494 outputs have been designed to minimize
overshoot. In addition it may be helpful to place a ferrite
bead in this signal path to limit the propagation of high
order harmonics ofthis signal. A suitable device would be a
Ferroxcube 56-590-65/4B or equivalent. This device should
be placed physically close to the ICS1494. A 33 to 47 Ohm
series resistor, sometimes called source termination, in this
path may be necessary to reduce ringing and reflection of
the signal and may reduce phase-jitter as well as EM!.

External Frequency Sources
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal should be connected between XTALI (5) and XTAL2 (6).
In IBM -compatible applications this will typically be a
14.31818 MHz crystal, but fundamental mode crystals between lOMHz and 25MHzhave been tested. Maintain short
lead lengths between the crystal and the ICS1494. In some
applications, it may be desirable to utilize the bus clock. If
the signal amplitude is equal to or greater than 3.5 volts, it
maybe connected directly to XTALI (5). If the signal amplitude is less than 3.5 volts, connect the clock through a .047
microfarad capacitor to XTALI (5), and keep the lead length
of the capacitor to XTALI (5) to a minimum to reduce nOIse
susceptibility. This input is internally biased at VDD/2. Since
TTL compatible clocks typically exhibit a VOH of 3.5Y,
capacitivelycoupling the input restores noise immunity. The
ICS1494 is not sensitive to the duty cycle of the bus clock;
however, the quality of this signal varies considerably with
different motherboard designs. As the quality of this signal
is typically outside of the control of the graphics adapter card
manufacturer, it is suggested that this signal be buffered on

EXTFREQ (7), on versions so equipped by the programming, is an input to a digital multiplexer. When this input is
enabled, signals driving the input will appear at FOUT(9)
instead of the PLL output. Internally, the PLL will remain
in lock at the frequency selected by the ROM code. If this
option is not specified. pin (7) is connected to VDD internail); and MUST be connected to VDD or left open, not
grounded!

Digital Inputs
FSO (18), FSI (19), FS2 (20),FS3(1), and FS4 (4), are the
TTL compatible frequency select inputs for the binary code
corresponding to the frequency desired. STROBE (2), when
high, allows new data into the frequency select latches; and
when low, prevents address changes per Figure 3. The internal power-on -clear signal will force an initial frequency code
corresponding to an all zeros input state. VERTBLANK
(10), when low, inhibits the transfer of new frequency select
information. Enabling this pin during the vertical blanking
interval causes the change in frequency to happen at this
time and prevents any visible glitch when a new frequency is
selected. If this feature is not required, this pin may be left
open.

157

ICS1494
Absolute Maximum Ratings
Supply Voltage ............
Input Voltage .............
Output Voltage ............
Clamp Diode Current ......
Output Current per Pin .....
Operating Temperature .....
Storage Temperature .......
Power Dissipation .........

VDD ......
VIN .......
VOUT .....
VIK & 10K.
lOUT .....
To ........
Ts ........
PD .......

-0.5V to + 7V
-0.5V to VDD+ 0.5V
-0.5V to VDD+ 0.5V
+ 1-30mA
+ I-SOmA
0 DC to 70 DC
-85 DC to + 150 DC
500mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and
VOUT be constrained to > = Vss and < = VDD.

DC Characteristics (0 °C to 70°C)
SYMBOL
Vdd
VII
Vlh
Ilh
Vol
Voh
Idda
Idda
Iddd
I--Iddd
Ruo *
CIn
C OU !

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
OUlp_ut High Voltage
Analog Supply Current
Analog Supplv Current
Digital Supply Current
Digital~y Current
Internal Pullup Resistors
Input Pin Capacitance
Output Pin Capacitance

MIN
4.0
Vss
2.0

MAX
5.5
0.8
Vdd

-

10

2.4

0.4
5
7
12
25
200
8
12

-

50
-

-

UNITS
V
V
V
uA
V
V
mA
mA
mA
mA
KOhm
pF
pF

CONDITIONS
Vdd = 5V
Vdd = 5V
YIn = Vee
10 1= 4.0mA
Ioh = 4.0mA
Vdd = 5.0V,FOUT =
'Vdd = 5.0V, FOUT =
Vdd = 5.0V,FOUT =
Vdd = 5.0V,FOUT =
V dd = 5V, YIn = OV
Fe= IMHz
Fe= IMHz

* The following inputs have pull-ups: FSO-4, STROBE, EXTFREQ, VERTBLANK.

158

25 MHz
110MHz
25 MHz
110 MHz

ICS1494
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
I. Xtal Frequency = 14.31818 MHz

2.
3.
4.
5.
6.
7.

All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = 15pF
Duty cycle is measured at 1.4Y.
Supply Voltage Range = 4.75 to 5.25 Volts
Temperature Range = O°C to 70°C

PARAMETER

SYMBOL
Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
Duty Cycle

-

-

MIN
STROBE TIMING
20
10
10
I
FOUTTIMING

40%

60%

Tpw

STROBE
FSO- FS]

-

-

-

!

~

'}

*
t-

Tsu

-+- Thd

Figure 3

159

NOTES

-

3
3
0.5
135
15

I

MAX

>K
--t

I

%
MHz
ns
110 MHz or less

160

ICS2494
ICS2494A

Integrated
Circuit
Systems, Inc.

Dual Video/Memory Clock Generator
Features

New Features

•

•
•
•

Buffered Xtal Out
Integral loop filter components
Fast acquisition of selected frequencies, strobed or nonstrobed

•
•
•
•

Guaranteed performance up to 135 MHz
Excellent power supply rejection
Advanced PLL for low phase-jitter
Frequency change detection circuitry which enhances
new frequency acquisition and eliminates problems
caused by programs that rewrite frequency information.
Improved pinout - easier board layout.

•
•
•
•
•
•
•

World standard ICS2494A has been reconfigured to allow
8 memory frequencies.
Mask-programmable frequencies
Pre-programmed versions for Industry Standard VGA
chips
Glitch-free frequency transitions
Provision for external frequency input
Internal clock remains locked when the external frequency input is selected
Low power CMOS device technology
Small footprint - 20 pin DIP or SO

•

Applications
•

VGA-Super VGA-XGA video adapters

•
•
•

Workstations
8514A-TMS34010-TMS34020
Motherboard

XTALI

Description
The Dot Clock Generator is an integrated circuit dual phaselocked loop frequency synthesizer capable of generating sixteen video dot clock frequencies and eight memory clock
frequencies fur use with high performance video display
systems. Utilizing CMOS technology to implement all linear,
digital and memory functions, the ICS2494/94A provides a
low-power, small-fuotprint, low-cost solution to the generation
of video dot clocks. Outputs are compatible with XGA, VGA,
EGA, MCGA, CGA, MDA, as well as the higher frequencies
needed fur advanced applications in desktop publishing and
workstation graphics. Provision is made via a single-level
custom mask to implement customer-specific frequency sets.
Phase-locked loop circuitry permits rapid glitch-free transitions between clock frequencies.

DVDD

XTAL2

2

19

VCLK

EXTFREQ

3

18

XTALOUT

FSO

4

17

VSS

FSI

5

16

VSS

STROBE

6

15

AVDD

FS2

7

14

VSS

FS3

8

13

DVDD

MSO

9

12

MCLK

VSS

10

11

MSI

Notes:
1. In applications where the external frequency input is not specified,
EXTFRBQ must be tied to v.s.
2. ICS2494/94AM(SO) pinout i. identical to ICS2494/94AN(DIP).

Ordering Infonnation
ICS2494NXXX, ICS2494ANXXX (DIP Package)
ICS2494MXXX, ICS2494AMXXX (SO Package)
(XXX = Pattern number)

161

ICS2494
ICS2494A
Circuit and Application Options
The ICS2494/94A will typically derive its frequency reference
from a series-resonant crystal connected between pins 1 and
2. Where a high quality reference signal is available, such as
in an application where the graphics subsystem is resident on
the motherboard, this reference may directly replace the
crystal. Tills signal should be coupled to pin 1. If the reference
signal amplitude is less than 3.5 volts, a .047 microfilrad
capacitor should be used to couple the reference signal into
XTALI. Pin 2 must be left open.

.RJwer Supply Conditioning
The ICS2494/94A is a member of the second generation of
dot clock products. By incorporating the loop filter on chip
and upgrading the VCO, the ease of application has been
substantially improved CNer earlier products. If a stable and
noise-free power supply is available, no external components
are required. However, in most applications it is judicious to
decouple the power supply as shown in Figures 1 or 2. Figure
1 is the normal configuration for 5 volt only applications.
Wnich of the two provides superior performance depends on
the noise content of the power supplies. In general, the
configuration of Figure 1 is satisfilctory. Figure 2 is the more
conventional if a 12 volt analog supply is available, although
the improved performance comes at a cost of an extra component. The cost of the discretes used in Figure 2, however, are
less than the cost of Figure 1's discrete components.
The number and differentiation of the analog and digital supply
pins are intended for maximum performance products. In most
applications, all VDDs may be tied together. The function of
the multiple pins is to allow the user to realize the maximum
performance from the silicon with a minimum degradstion due
to the package and PCB. At the frequencies of interest, the
effects of the inductance of the bond wires and package lead
frame are non-trivial. By using the multiple pins, ICS minimized the effect of packaging and minimized the interaction of
the digital and analog supply currents.

Figure 1
22
A

~3];2

r-1IH

20
19

~

18

4

17

FSO ......
......
FS1 .....
,.,
STROBE ....,
,.,
....,

-

y

Rl

TJ,-J22
~

YCLK

.., XTALO UT

5
ICS2494 16
6 ICS2494A 15
14
7

FS2
FS3 "....,
......
MSO .....

8

13

9

12

]0

11

- ....
162

'" 5.0V

.., MCLK
::) MS1

ICS2494
ICS2494A
Applications
Layout Considerations
Utilizing the ICS2494/94A in video graphics adapter cards or
on PS2 motherboards is simple but does require precautions
in board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the ICS2494/94A do not share its ground. In
applications utilizing a multi-layer board, VSS should be
directly connected to the ground plane. Multiple pins are
utilized for all analog and digital VSS and VDD connections
to permit extended frequency VCLK operation to 135 MHz.
However, in all cases, all VSS and VDD pins should be
connected.

The ICS2494/94A is not sensitive to the duty cycle of the bus
clock; however, the quality of this signal varies considerably
with different motherboard designs. As the quality of this
signal is typically outside of the control of the graphics adapter
card manufucturer, it is suggested that this signal be buffered
on the graphics adapter board. XTAL2 (2) must be left open
in this configuration.

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2494/94A provide the bus clock for the rest of the system.
This eliminates the need for an additional 14.31818 MHz
crystal oscillator in the system, saving money as well as board
space. To do this, the XTALOUT (18) output should be
buffered with a CMOS driver.

Figure 2

Output Circuit Considerations
S.OV

~I

r-11~

1L,

~

19
18

~

17

rso

:; ICS2494

FSl
STROBE

6
7

rS2

CS2494Jl

8

rS3
MSO

9

.---1l1-

16
15
14

1L12

11

As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EM!.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK (19) or MCLK (12) and
other components in the system should be kept as short as
possible. The ICS2494/94A outputs have been designed to
minimize overshoot. In addition it may be helpful to place a
ferrite bead in these signal paths to limit the propagation of
high order harmonics of this signal. A suitable device would
be a Ferroxcube 56-590-65/4B or eqnivalent. This device
should be placed physically close to the ICS2494/94A. A 33
to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary to reduce ringing and
reflection of the signal and may reduce phase-jitter as well as
EM!.

1

VCLK
XTALOU T

.1~f21~':7V

470

-"
01

12.0V

MCLK
MSl

-

Digital Inputs
Frequency Reference

FSO (4), FSI (5), FS2 (7), andFS3 (8) are the TTL compatible

The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTALI (1) and XTAL2 (2). In
IBM-compatible applications this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the ICS2494/94A. In some applications, it may be desirable to utilize the bus clock. If the signal
amplitude is equal to or greater than 3.5 volts, it may be
connected directly to XTALI (1). If the signal amplitude is
less than 3.5 volts, connect the clock through a .047 microfurad
capacitor to XTALI (1), and keep the lead length of the
capacitor to XTALI (1) to a minimum to reduce noise susceptibility. This input is internally biased at VDD/2. Since TTL
compatible clocks typically exhibit a VOH of 3.5V, capacitively coupling the input restores noise inununity.

frequency select inputs for the bioary code corresponding to
the frequency desired. STROBE (6), when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 3. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MSO (9), MSI (11) and MS2 (3) are the
corresponding memory select inputs and are not strobed.

163

II

ICS2494
ICS2494A
Absolute Maximum Ratings
Supply Voltage ............. VDD . . . . . . . ••
Input Voltage .....•...•.•.. VIN . • • . • • • • •.
Oulput Voltage ..•••••.•.••• Your •••••.•.•
Clamp Diode Current .••..•... VII( & 10K . . . ..
Oulput Current per Pin ........ lour .........
Operating Temperature ••••••.. To. . . . . . . . . ..
Storage Temperature ......... Ts •....•.•.•
Power Dissipation .•..••.•.•. PD ••.•••.••.•

-C.5V to + 7V
-C.5V to VDD+O.5V
-C.SV to VDD+O.SV
+ / -30mA
+/-SOmA
0 °c to 70 °C
-85°C to + 150 °c
SoomW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and oulputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and Vour be constrained
to> = Vss and < =VDD.

DC Characteristics (0 °C to 70°C)
SYMBOL
Vnn
Va
Vm
1m
VOL
VOH
Inn
Rup •
Cin

Cout

PARAMETER
Ooeratiru!: Voltal!e Ranl!e
Input Low Voltal!e
Inout High Voltage
Inout Leakage Current
Outout Low Voltal!e
Outout Hil!h Voltal!e
SUDDlv Current
Internal Pullup Resistors
Input Pin Capacitance
Outout Pin Capacitance

MIN
4.0
V..
2.0

MAX
5.5
0.8
Vdd
10
0.4

2.4
SO
-

-

35
200
8
12

-

• The following inputs have pullups: FSO-3, MSO-l, STROBE.

Frequency Pattern Availability
ICS offers the largest variety of standard frequency patterns in
the industry, supporting all popular VGA controller devices.
The attached listing provides the selection as of this publication date. Contact your local ICS sales office for latest
frequency pattern availability.

164

UNITS
V
V
V
uA
V
V
mA
KOhm
pF
pF

CONDmONS
Vdd = SV
Vdd = SV
V;n = Von
101 = 4.0mA
loh = 4.0mA
Vdd = sv. VCLK = 80 MHz
Vdd = sv. Yin = OV
Fc = 1 MHz
Fc = 1 MHz

ICS2494
ICS2494A
AC Timing Characteristics
The following notes apply to all parameters presented in this section:

1.
2.
3.
4.
5.
6.
7.
8.

Xtal Frequency = 14.31818 MHz
Te = 11 Fe
All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = 25pF
Duty cycle is measured at 1AV.
Supply Voltage Range = 4.0 to 5.5 Volts
Temperature Range = 0 °c to 70°C
SYMBOL

I

PARAMETER

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strooo

Tr
Tf

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency

-

MIN
I
STROBE TIMING
20
10
10
MCLK AND VCLK TIMINGS

-

STROBE

FSO-FS]

I

~

~
I

~

*
I-

iI
!

!
Tsu

-+-

Figure 3

165

Thd

NarES

3
3
0.5
135
15

-

Tpw

MAX

>K
--;

Duty Cycle 40 % min. to
60% max.
%
MHz
ns

166

•

ICS2495

Integrated
Circuit
Systems, Inc.

Dual Video/Memory Clock Generator

Features
•
•

Low cost - eliminates need for multiple crystal clock
oscillators in video display subsystems
Mask-programmable frequencies

•

Pre-programmed versions for Industry Standard VGA
chips

•
•

Glitch-free frequency transitions
Internal clock remams locked when the external frequency input is selected

•

Low power CMOS device technology

•

Small footprint - 16 pin DIP or SO

Description

Buffered Xtal Out
Integral Loop Filter components

•

Fast acquisition of selected frequencies, strobed or nonstrobed

•

Guaranteed performance up to 135 MHz

•
•

Excellent power supply rejection
Advanced PLL for low phase-jitter

•

Frequency change detection circuitry enhances new frequency acquisition and elimmates problems caused by
programs that rewrite frequency information

Pin Configuration

Thc ICS2495 Clock Generator is an integrated circuit dual
phase-locked loop frequency synthesizer capable of generating
16 video frequencies and 4 memory clock frequencies for use
with high performance video display systems. Utilizing
CMOS technology to implement all linear, digital and memory
functions, the ICS2495 provides a low-power, small-footprint,
low-cost solution to the generation of video dot clocks. Outputs are compatible with XGA, VGA, EGA, MCGA, CGA,
MDA, as well as the higher frequencies needed for advanced
applications in desktop publishing and workstation graphics.
Provision is made via a single level custom mask to implement
customer specific frequency sets. Phase-locked loop circuitry
permits rapid glitch-free transitions between clock frequencies.
In addition to providing 16 clock rates, the ICS2495 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits mstantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit board testing is simplified by the use of these
modes as an external clock generated by the ATE tester can be
fed through, permitting synchronous testing of the entire system.

•
•

XTAL2

16

XTALl

EXTFREQ

2

15

VCLK

FSO

3

14

XTALOUT

FSI

4

13

VSS

STROBE

5

12

VDD

FS2

6

11

N/C

FS3

7

10

MCLK

MSO

8

9

Notes:
I ICS2495M(SO) pmout IS Identical to ICS2495N(DIP).

Ordering Information
ICS2495N-XXX (DIP Package)
ICS2495M-XXX (SO Package)
(XXX = Pattern number)

167

MSI

ICS2495
Reference Oscillator & Crystal Selection

Layout Considerations

In cases where the on-chip crystal oscillator is used to generate
the reference frequency, the accuracy of the crystal oscillation
frequency will have a very small effect on output accuracy.

Utilizing the ICS2495 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised to ensure that components
not related to the ICS2495 do not share its ground. In applications utilizing a multi-layer board, Vss should be directly
connected to the ground plane.

The external crystal and the on-chip circuit implement a Pierce
oscillator. In a Pierce oscillator, the crystal is operated in its
parallel-resonant (also called anti-resonant mode). This means
that its actual frequency of oscillation depends on the effective
capacitance that appears across the terminals of the quartz
crystal. Use of a crystal that is characterized for use in a
series-resonant circuit is fine, although the actual oscillation
frequency will be slightly higher than the value stamped on the
crystal can (typically 0.025%-0.05% or so). Normally, this
error is not significant in video graphics applications, which is
why the ICS2495 will typically derive its frequency reference
from a series resonant crystal connected between pins I and
16.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, the crystal should be
mounted as close as possible to the package. Avoid routing
digital signals or the ICS2495 outputs underneath or near these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.

Power Supply Conditioning
The ICS2495 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figure I.

Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be connected between XTAL1 (16) and XTAL2 (1). In IBM compatible applications this will typically be a 14.31818 MHz crystal,
but fundamental mode crystals between lOMHz and 25MHz
have been tested. Maintain short lead lengths between the
crystal and the ICS2495. In some applications, it may be
desirable to utilize the bus clock. If the signal amplitude is
equal to or greater than 3.5 volts, it may be connected directly
to XTAL1 (16). If the signal amplitude is less than 3.5 volts,
connect the clock through a .047 microfarad capacitor to
XTAL1 (16), and keep the lead length of the capacitor to
XTAL1 (16) to a minimum to reduce noise susceptibility. This
input is internally biased at VDDI 2. Since TTL compatible
clocks typically guarantee a VOH of only 2.8V, capacitively
coupling the input restores noise immunity. The ICS2495 is
not sensitive to the duty cycle of the bus clock; however, the
quality of this signal varies considerably with different motherboard designs. As the quality of this signal is typically outside
of the control of the graphics adapter card manufacturer, it is
suggested that this signal be buffered on the graphics adapter
board. XTAL2 (1) must be left open in this configuration.

Buffered XTALOUT

10
5.0V

EXTFREQ
14

FSO
4

STROBE

5

FS2

6

1l

N/C

7

10

MCLK

FS3
MSO

NOTES:

XTALOUT

FS1

13

ICS2495

12

8

MS1

FS3-FSO, MS l-MSO, EXTFREQ, and STROBE mputs are all eqUIpped WIth pullups and need not be tIed hIgh.
Mount decouphng capacitors as close as possIble to the deVIce and connect deVIce ground to the ground plane where avmlable.
Mount crystal and Its mCUlt traces away from sWItchmg dIgItal hnes and the VCLK, MCLK and XTALOUT hnes.

Figure 1
168

II

ICS2495

In motherboard applications it may be desirable to have the
ICS2495 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer XTALOUT when using it to provide the system clock.

Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EM!.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK or MCLK and other components in the system should be kept as short as possible. The
ICS2495 outputs have been designed to minimize overshoot.
In addition, it may be helpful to place a ferrite bead in these
signal paths to limit the propagation of high-order harmonics
of this signal. A suitable device would be a Ferroxcube 56-59065!4B or equivalent. This device should be placed physically
close to the ICS2495. A 33 to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary
to reduce ringing and reflection of the signal and may thereby
reduce phase jitter as well as EM!.

External Frequency Sources
EXTFREQ on versions so equipped by the programming, is
an input to a digital multiplexer. When this input is enabled by
the FSO-3 selection, the signal driving pin 2 will appear at
VCLK (15) instead of the PLL output. Internally, the PLL will
remain in lock at the frequency selected by the ROM code.
The programming option also exists to output the crystal oscillator output on VCLK. In the case where XTALI is being
driven by au external oscillator, then this frequency would
appear on VCLK if so programmed.

Digital Inputs
FSO (3), FSI (4), FS2 (6), andFS3 (7), are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (5) when high, allows new
data into the frequency select latches; and when low, prevents
address chauges per Figure 2. The internal power-an-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MSO (8) and MSI (9) are the corresponding memory select inputs and are not strobed.

169

ICS2495
Pin Descriptions
The following table provides the pin description for the 16-pin ICS2495 packages.
PIN NUMBER
I
2

1-------- 3
4
c---5
6
1-----7
8
9
10
11
12

PIN SYMBOL
XTAL2
EXTFREQ
FSO
FSI
STROBE
FS2
FS3
MSO
MSI
MCLK
N/C
VDD

13~VSS

_---.li..
IS
16

TYPE
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT

---------

XTALOUT
VCLK
XTALl

I

OUT
OUT
IN

DESCRIPTION
Crystal interface
External clock input (if so programmed)
Control input for VCLK selection
Control input for VCLK selection
Strobe for latching FS (0-3) (HiRh enable)
Control input for VCLK selection
Control inlJUt for VCLK selection
'Select input for MCLK selection
Select input for MCLK selection
Memory Clock Output
Not Connected
Power

r9 round - - - - - - - -

Buffered Crystal Output
Video Clock Output
Reference input clock from system

Absolute Maximum Ratings
Ambient Temperature
under bias
Storage temperature

10°Ct070°C

Voltage on all inputs
and outputs with
respect to Vss

0.3 to 7 Volts

-

Standard Test Conditions
The charactenstics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to V ss COV Ground). Positive current flows into the referenced
pin.

_40°C to 125 °c

Operating Temperature
e

Note: Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

170

4.75 to 5.25 Volts

ICS2495
DC Characteristics at 5 Volts Voo
SYMBOL
VDD
VIL
VIH
IIH
VOL
VOH
IDD
Rup

Cn
C OU!

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
VCLK, MCLK
XTALOUT
VCLK,MCLK
Output High Voltage:
XTALOUT
Supply Current
Internal Pullup Resistors
Input Pm Capacitance
Output Pin Capacitance

MIN
4.75
Vss
2.0

-

Output Low Voltage:

-

2.4
2.4
50
-

i

-

171

MAX
5.25
0.8
VDD
10

UNITS
V
V
V
~A

VDD-5V
VDD= 5V
Vm = Vee

0.4
0.4

V
V
V
V
rnA
Kohrns
pF
pF

IOL= 8.0 rnA
IOL=4.0rnA
IOH= 8.0 rnA
IOH =4.0 rnA
VDD=5V
VIN = O.OV
Fe= I MHz
Fe= 1 MHz

-

30
-

8
12

,

I

CONDITIONS

ICS2495
AC Timing Characteristics
The following notes apply to all of the parameters presented in this section.

1.
2.

Te = lIFe

3.
4.
5.
6.
7.

All units are in nanoseconds (ns).
Maximum jitter within a range of 30 ~s after triggering on a 400 MHz scope.
Rise and fall time between 0.8 and 2.0 VDC unless otherwise stated.
Output pin loading = 15pF.
Duty cycle measured at 1.4 volts.

REFCLK = 14.318 MHz

SYMBOL

PARAMETER

MIN
STROBE TIMING
20
10
10
MCLK and VCLK TIMINGS

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf
-

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
Output Enable to Tri-State
(into and out of) time

-

-

-

-

MAX

NOTES

-

2
2
0.5
135
20

Duty Cycle 40% min. to
60% max.
%
MHz
ns

15

ns

Tpw

STROBE

FSO-FS3

------J*'--------"---~>K'--__
-+t-

Tsu

Figure 2

172

Thd

--I

~~ Integrated
Circuit

ICS2496

Systems, Inc.

Dual Voltage Video/Memory Clock Generator
•
Features
• Specified for dual voltage operation (VDD = 3.3V or 5V) •
but operates continuously from 3.0V to 5.25V
•
• Powerdown input for extended battery life in portable
•
•

•
•
•
•
•

applications
Guaranteed performance up to 110 MHz (at 3.3V)
or 135 MHz (at 5V)
Advanced PLL for low phase-jitter
Low power CMOS device technology
Excellent power supply rejection
Integral Loop Filter components
Mask-programmable frequencies
Small footprint - 16 pin DIP or SO

•
•
•
•

Generates 16 video clock frequencies derived from a
14.318 MHz system clock reference frequency
Provision for external frequency input
Video clock is selectable among the 16 internally generated clocks, one external clock, or the buffered crystal
oscillator
Internal clock remains locked when the external frequency
input is selected
On-chip generation of four memory clock frequencies
Patented technique eliminates cross-interference between
video and memory clocks
Fast acquisition of selected frequencies, strobed or nonstrobed

Pin Configuration

Description
The ICS2496 has been specifically designed to serve the portable PC market with operation at either 3.3V or 5V with a
comprehensive power-saving shut down mode.
The ICS2496 Clock Generator is a dual phase-locked loop
frequency synthesizer capable of generating 16 video frequencies and four memory clock frequencies for use with high
performance video display systems. Utilizing CMOS technology to implement all linear, digital and memory functions, the
ICS2496 provides a low power, small footprint, low cost
solution to the generation of video dot clocks. Provision is
made via a single level custom mask to implement customer
specific frequency sets. Phase-locked loop circuitry permits
rapid glitch-free transitions between clock frequencies.
In addition to providing 16 clock rates, the ICS2496 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits instantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit board testing is simplified by the use of these
modes, as an external clock generated by the ATE tester can be
fed through, permitting synchronous testing of the entire system.

XTAL2

16

XTALl

EXTFREQ

2

15

VCLK

FSO

3

14

XTALOUT

FSI

4

13

VSS

STROBE

5

12

VDD

FS2

6

11

PWRDN

FS3

7

10

MCLK

MSO

8

9

Notes:
1. ICS2496M(SO) Pillout IS IdentICal to ICS2496N(DIP).

Ordering Information
ICS2496N-XXX (DIP Package)
ICS2496M-XXX (SO Package)
(XXX = Pattern number)

173

MSI

II

ICS2496
Circuit Function and Application

Reference Oscillator and Crystal Selection

"Powerdown"

In cases where the on-chip crystal oscillator is used to generate
the reference frequency, the accuracy of the crystal oscillation
frequency will have a very small effect on output accuracy.

The ICS2496 has been optimized for use in battery operated
portables. It can be placed in a powerdown mode which drops
its supply current requirement below 1 microamp. When
placed in this mode, the digital inputs FSO-3, STROBE, MSO1, and EXTFREQ may be either high or low or floating without
causing an increase in the ICS2496 sup-ply current.
The PWRDN pin must be low (It has an internal pull-down.)
in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high and XTALOUT is
driven low by the ICS2496 when it is in its low power state.
If a crystal is being used, nothing needs to be done to achieve
low power. If XTALI is being driven by an external source, it
may be driven low or high without a power penalty. If XTALl
is at an intermediate voltage (Vss +0.5V < VIN < VDD -0.5),
there will be a small increase in supply current. If XTALl is
driven at 14.318 MHz while the chip is in powerdown, the
ICS2496 supply current will increase to approximately 1.2
mAo

The external crystal and the on-chip circuit implement a Pierce
oscillator. In a Pierce oscillator, the crystal is operated in its
parallel-resonant (also called anti-resonant) mode. This means
that its actual frequency of oscillation depends on the effective
capacitance that appears across the terminals of the quartz
crystal. Use of a crystal that is characterized for use in a
series-resonant circuit is fine, although the actual oscillation
frequency will be slightly higher than the value stamped on the
crystal can (typically 0.025%-0.05% or so). Normally, this
error is not significant in video graphics applications, which is
why the ICS2496 will typically derive its frequency reference
from a series-resonant crystal connected between pins 1 and
16.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, the crystal should be
mounted as close as possible to the package. Avoid routing
digital signals or the ICS2496 outputs underneath ornear these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.

The STROBE (pin 5) may be used to guard against inadvertent frequency changes during powerdownlpower-up sequences. By holding the STROBE low during powerdown and
power-up sequences, the ICS2496 will retain the most recent
video frequency selection.

The ICS2496 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figure 1.

10
~~---".,-VV'V'---

VSEL1

;'

g z
w '"

VSELO and VSELl are latched by the SELEN signal.
VSEL2 and VSEL3 are used as direct inputs to the VCLK
selection. Table I-I is the truth table for VCLK selection.

~

<.>

CLK1
NSEL2
EXTCLK
VSEL1
VSELO
SELEN
VSEL2
VSELJ
MSELO
DONO

[
[

g

::

~

w

'" tiz
d
::;

rn

"

0

[
[

VCLKE

17

N.C.

16

AGND

::'

DVCC
VCLK
VCLKE
N.C.
AGNO

ICS90C64A
[

18

AIICC
NCLKE
N.C.
NCLK
t.ASEL1

Note'ICS90C64AN (DIP) pmout IS IdentIcal to ICS90C64AM (SO) pmout.

Ordering Information
ICS90C64AV-XXX (PLCC Package)
ICS9OC64AM-XXX (SO Package)
(DIP Package)
ICS9OC64AN-XX
XXX = (Pattern number)

ICS90C64A
ICS90C64A VGA Interface
The ICS90C64A has two system interfaces: System Bus and
VGA Controller, as well as analog filters and seven user
programmable inputs. Figure 2-1 shows how the Integrated
Circuit Systems VGA Clock ICS90C64A is connected to a
VGA controller. Western Digital Imaging VGA controllers

vee

normally have a status bit that indicates to the VGA controller that it is working with a clock chip, When working with a
clock chip the VGA controller changes two of its clock
inputs, VCLKI and VCLK2, to outputs. These outputs are
used to select the required video frequency.

10
v

gl

R1

f2ur

dJe

TUF
DVDD

I

DSC

I

AVDD

EXTClK

I

'-

MSELO

~=
~=

MSELl
MSEl2

f-J-

VSEl3

~

ClK

VCLKE
MClKE

r-~Et~ r--

ICS90C64A
elKl
VSElO

D2
D3

VSELl

r-- VSEL2

SELEN

2:
W
I(/)(/)

>-:=J
~

(/)P=1

'--~

VCLKI
VCLK2

]2
D3

VClKO t-

MCLK

VGA
FIGURE 2-1

ICS90C64A INTERFACE

Note:

C2 should be placed as close as possible to the ICS90C64A A VDD pin.

204

-

II

ICS90C64A

System Bus Inputs

Analog Filters

The system bus inputs are:

The analog filters are integral to the ICS90C64A device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter IS reduced as externally-generated noise cannot easily
influence the phase-locked loop filter.

•
•
•

CLKI
VSELO
VSELI

The ICS90C64A uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used
as inputs to VSELO and VSEL I for video frequency selection.

Inputs from VGA Controller

User-Definable Inputs
The user-definable inputs are:
•
•
•
•

EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3

The VGA controller input to the ICS90C64A is:
•

SELEN

The ICS90C64A is programmed to generate different video
clock frequencies using the inputs of VSELO, VSELI,
VSEL2, and VSEL3. The signals VSEL2 and VSEL3 may
be supplied by the VGA controller as is the case in Western
Digital Imaging VGA controllers. The inputs VSELO-I are
latched with the signal SELEN. The SELEN input should
be an active low pulse. This active low pulse is generated in
Western Digital Imaging VG A controllers during I/O writes
to internal register 3C2h.
Note: Only VSELO and VSELI are latched with signal
SELEN.

EXTCLK is an additional input that may be internally
routed to the VCLK output. This additional input is useful
for supporting modes that require frequencies not provided
by the ICS90C64A.
VCLKE and MCLKE are the output enable signals for
VCLK and MCLK. When low, the respective output is
tri-stated.
MSELO-2 are the memory clock (MCLK) select lines. Table
1-2 shows how MCLK frequencies are selected. All signals
in this group have internal pull-up resistors.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table I-I.
VSEL2 and VSEL3 have internal pullups.

Outputs to VGA Controller
The outputs from the ICS90C64Ato the VGA controller are:
•
•

MCLK
VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

205

II

ICS90C64A
+ 5V

Power Considerations

C1

DVDD

11~F

The ICS90C64A product requires an AVDD supply free of
fast rise time transients. This requirement may be met in
several ways and is highly dependent on the characteristics
of the host system. A VG A adapter card is unique in that it
must function in an unknown environment. + 5 Volt power
quality is dependent not only on the quality of the power
supplyresident in the host system, but also on the other cards
plugged into the host's backplane. Power supply noise
ranges from fair to terrible. As the VGA adapter manufacturer has no control over this, he must assume the worst. The
best solution is to create a clean + 5 Volts by deriving it from
the + 12 Volt supply by using a zener diode and dropping
resistor. A 470 Ohm resistor and 5.1 Volt Zener diode are
the least costly way to accomplish this. A .047 to .1 microfarad bypass capacitor tied from A VDD to A V ss insures
good high-frequency decoupling of this point.

470

+ 12V

R1

D1

C2

AVDD

4.711~F

10

+ 5V

Laptop and notebook computers have entirely different
problems with power. Typically they have no + 12 Volt
supply; however, they are much quieter electrically. Because
the designer has complete control of the system architecture, he can place sensitive components and systems such as
the RAMDAC and Dual Video/Memory Clock away from
DRAM and other noise-generating components. Most systems provide power that is clean enough to allow for jitterfree Dual Video/Memory Clock performance ifthe + 5 Volt
supply is decoupled with a resistor and 22 microfarad Tantalum capacitor. Digital inputs that are desired to be held
at a static logical high level should not be tied to + 5 Volts
as this will result in excessive current drain through the ESD
protection diode. The internal pullup resistors will adequately keep these inputs high.

R1

C2

C3

AVDD

DVDD

122~F 11~F
VSS, AVSS

18
+ 5V
.1~F

1

AVDD

R1

DVDD

122~F 11~F
AVSS

206

(I

ICS90C64A
Table 1-1

VCLK SELECTION
VCLK Frequency (MHz)

3

2

1

0

ICS90C64A

ICS9OC64A -903

ICS90C64A-907

ICS90C64A-909

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

30.0
77.25
EXTCLK
80.0

30.0
77.25
EXTCLK
80.0

30.250
77.25
EXTCLK
80.0

30.0
77.25
EXTCLK
80.0

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

31.5
36.0
75.0
50.0

31.5
36.0
7.50
50.0

31.5
35.5
75.0
72.0

31.5
36.0
75.0
50.0

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

40.0
50.0
32.0
44.9

40.0
50.0
32.0
44.9

40.0
50.0
32.0
44.9

40.0
50.0
32.0
44.9

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

25.175
28.322
65.0
36.0

25.175
28.322
65.0
36.0

25.175
28.322
65.0
36.0

25.175
28.322
65.0
36.0

,

I

Table 1-2 MCLK SELECTION

R

1

0

ICS90C64A

ICS90C64A-903

ICS90C64A-907

ICS9OC64A-909

0
0

0
0
1
1

0
1
0
1

33.0
49.218
60.0
30.5

33.0
49.218
60.0
30.5

65.0
49.218
60.0
62.5

75.0
40.0
45.0
50.0

1
1
1
1

0
0
1
1

0
1
0
1

41.612
37.5
36.0
44.296

41.612
37.5
36.0
44.296

41.612
37.5
55.0
44.296

55.0
60.0
65.0
70.0

I

I

M<::LK Frequencies (MHz)

207

II

ICS90C64A

EXTCLK
CLKl
SELEN
VCAP

,--,
v

MUX

PLL
DIVIDER

---[:(

VCLK

I I

VSELO
VSELl
VSEL2
VSEL3
VCLKE

MCAP
MSELO
MSELl
MSEL2
MCLKE

FIGURE 2-2

I

PLL
DIVIDER
I

~

II

ICS90C64A FUNCTIONAL BLOCK DIAGRAM

208

MCLK

ICS90C64A
Pin Descriptions
The following table provides the pm descriptions for the 20-pin ICS90C64A packages.
PIN
NUMBER

PIN
SYMBOL

TYPE

DESCRIPTION

I

CLKI

IN

Reference input clock from system

2

MSEL2

IN

Select input for MCLK selectIOn

3

EXTCLK

IN

External clock input for an additional frequency

4

VSELI

IN

Control input for VCLK selection
Control input for VCLK selection

5

VSELO

IN

6

SELEN

IN

Strobe for latching VSEL(O,l) (Low enable)

7

VSEL2

IN

Control input for VCLK selection

8

VSEL3
MSELO

IN
IN

Control input for VCLK selection
Select input for MCLK selection

9
10

DGND

-

II

MSELI

IN

12

MCLK

OUT

13

-

14

N.C.
MCLKE

IN

Ground for Digital Circuit
Select input for MCLK selection
Memorv Clock Output
No connection
Enable input for MCLK output (hi/?h enables output)

IS

AVDD

-

16

AGND

-

Ground for analog circuit

17

N.C.

-

No connection
Enable input for VCLK output (hi/?h enables output)

18

VCLKE

IN

19

VCLK

OUT

20

DVDD

-

Power supply for analog circuit

Video Clock Output
Power supplv for Digital Circuit

Note:
CLKI, EXTCLK,VSELO, VSELl,VSEL2, VSEL3, SELEN, MSELO, MSELl, MSEL2, VCLKE, and MCLKE - input
pillS have internal pullup resistors.

209

ICS90C64A
Standard Test Conditions

Absolute Maximum Ratings
Ambient Temperature
under bias

The characteristics below apply for the following standard
test conditions, unless otherwise noted. All voltages are
referenced to Vss (OV Ground). Positive current flows into
the referenced pin.

o °c to 70°C

Storage temperature

-40 °c to 125°C

Voltage on all inputs
and outputs with
respect to Vss

0.5 to 7 Volts

Note: Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

Operating Temperature
range

o°c to 70°C

Power supply voltage

4.75 to 5.25 Volts

DC Characteristics
SYMBOL
VIL

PARAMETER
Input Low Voltage

VIH

Input High Voltage

IIH

MIN

TYP

MAX

UNITS

0.8

V

CONDITIONS

Vss
2.0

VDD

V

Input Leakage Current

-

10

-

0.4

VOH

Output Low Voltage
Output High Voltage

uA
V

-

VOH

Output High Voltage

VDD-.4
2.4

Vm = VDD
IOL = 8.0mA
IOH = 4.0mA

Ice

Supply Current

-

20

28

V
rnA

Ice

Supply Current

-

27

35

rnA

IOH = 8.0mA
No load
VCLK= 28MHz
MCLK= 40MHz
No load
VCLK= 80MHz
MCLK= 40MHz

Rup

Internal Pullup Resistors

50

-

Cm

Input Pin Capacitance

-

8

Kohms
pF

COUI

Output Pin Capacitance

-

12

pF

VOL

210

VDD - sv
Fe = 1 MHz
Fe= IMHz

(I

ICS90C64A

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:
I.REFCLK= l4.3ISMHz

2. Tc

=

IIFc

3. All units are in nanoseconds (ns), unless labeled otherwise.
4. Output pin loading = 15pF

SYMBOL

PARAMETER

MIN

TYP

MAX

NOTES

SELEN TIMING
Tpwen
Tsuen
Thden

Enable Pulse Width
Setup Time Data to Enable
Hold Time Data to Enable

Tr
Tf

Rise Time
Fall Time

Tr
Tf
Tr
Tf
ThIgh
ThIgh

Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Duty Cycle
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
Output Enable to Tri-State
(into and out of) time

20
20
10
Reference Input Clock

10
10

Phase-Jitter 1 ns max.
Duty Cycle 42.5% min.
to 57.5% max.

MCLK and VCLK TIMINGS

*

.9
.9
1.2
1.2
50%
45%

1.5
1.5
2.0
2.0
60%
55%
0.5
135
20
15

.SV-2.0V*
2.0V-.SV
.3 VDD-.7 VDD
.7 VDD-.3 VDD
l.4V Switch Point
VDD/2 Switch Point
%
MHz
ns
ns

WD90CII VIdeo Controller IS deSIgned with TTL level mput thresholds on the mputs dnven by the ICS90C64A VCLK and MCLK outputs.
The later controllers (WD90C20. WD9OC22. WD9OC26. WD9OC30. and WD90C31) are deSIgned WIth mput SWItch pomts ofVCC/2 (CMOS)

211

ICS90C64A

ENABLE TIMING
VSELO
VSEL 1

/

"-

v

"-

f'..-

/

SELEN
tpwen

I
I

thden

tsuen

CLOCK WAVEFORM
tc=1/fc
tr

tf

2JN

2.OV

O.8V

O.8V ' - - - - - - - - - - - - /

FIGURE 5-1

ICS90C64A TIMING

212

•

ICS90C65

Integrated
Circuit
Systems, Inc.

Dual Voltage Video/Memory Clock Generator

Introduction

Features

The Integrated Circuit Systems ICS90C65 is a dual clock
generator for VGA applications. It simultaneously generates two clocks. One clock is for the video memory, and the
other is the video dot clock.

•

The ICS90C65 has been specifically designed to serve the
portable PC market with operation at either 3.3V or 5V with
a comprehensive power-saving shut-down mode.
This data sheet supplies sales order information, a functional
overview, signal pin details, a block diagram, ACIDC characteristics, timing diagrams, and package mechanical information.

•
•
•

•

•

Description
The Integrated Circuit Systems Video Graphics Array
Clock Generator (lCS90C65) is capable of producing different output frequencies under firmware control. The
video output frequency is derived from a 14.318 MHz system
clock available in IBM PC/XT/AT and Personal Systeml2
computers. It is designed to work with Western Digital
Imaging Video Graphics Array and 8514/A devices to optimize video subsystem performance.
The video dot clock output may be one of 15 internallygenerated frequencies or one external input. The selection
of the video dot clock frequency is done through four inputs.
•
•
•
•

VSELO
VSELI
VSEL2
VSEL3

•
•

Specified for dual voltage operation (VDD= 3.3V or 5V),
but operates continuously from 3.0V to 5.25V
Designed to be powered down for extended battery life
Backward compatibility to the ICS90C64 and ICS90C63
Dual Clock generator for the IBM-compatible Western
Digital Imaging Video Graphics Array (VGA) LSI devices, and 85141 A chip sets
Integral loop filter components, reduce cost and phase
jitter
Generates fifteen video clock frequencies (including
25.175 and 28.322 MHz) derived from a 14.318 MHz
system clock reference freq uency
On-chip generation of eight memory clock frequencies
Video clock is selectable among the 15 internally generated clocks and one external clock
CMOS technology
Available in 20-pin PLCC, SO and DIP packages

y

':i

8~
VSEL1

4

VSELO

5

SELEN

6

VSEL2

7

VSEL3

B

§

~

~

--

elKI
MSEL2 ~
EXTCLK ~

en

~

w

en
~

The MCLK output is one of eight internally-generated frequencies as shown in Table 1-2. The various VCLK and
MCLK frequencies are derived from the 14.318 MHz Input
frequency.
The VCLKE and MCLKE input can tristate the VCLK and
MCLK outputs to facilitate board level testing.

213

VSELO
SELEN

17

NC

16

AVSS

15

AVDD

14

MCLKE

:"'

" I'
u
Y

~

~

~

DVDD

0

VCLK
VCLKE

NC

VSELl

The input and truth table have been designed to allow a
direct connection to one of the many Western Digital Imaging VGA controllers or 85l4/A chip sets.

VCLKE

ICS90C65V
::'

VSELO and VSELI are latched by the SELEN signal.
VSEL2 and VSEL3 are used as direct inputs to the VCLK
selection. Table I-I is the truth table for VCLK selection.

y

0

1'; Ii

ICS90C65M

AVDD
MCLKE

VSEL2
VSELJ
MSEL:J
DVSS

Note-ICS9OC65N (DIP) pInout

AVSS

PWRDN

MCU<
MSELI

IS

Identical to ICS9OC65M (SO) pInout.

Ordering Information
ICS9OC65V-XXX (PLCC Package)
ICS9OC65M-XXX (SO Package)
ICS9OC65N-XXX (DIP Package)
(XXX = Pattern number)

II

ICS90C65
ICS90C65 VGA Interface
The ICS90C65 has two system interfaces: System Bus and
VGA Controller, as well as other programmable inputs.
Figure I shows how the Integrated Circuit Systems' VGA
Clock ICS90C65 is connected to a VG A controller. Western
Digital Imaging VGA controllers normally have a status bit
that indicates to the VGA controller that it is working with
a clock chip. When working with a clock chip the VGA
controller changes two of its clock inputs to outputs. They
are the VCLKIIVCSLDIVCSEL and VCLK2IVCSELI
VCSELH outputs and they are used to select the required
video frequency.

Pullup at reset
and PR15(5)= 0

When the powerdown capabilities are used, the control
signal for PWRDN is normally held in one of a group of
latches. If the powerdown function is not to be used,
PWRDN must be tied to VDD, otherwise the internal pull
down will place the chip in the powerdown mode.

WD90C26

~

AMD(3)

LATCH
VCSlD I - - -

VCKIN

VCSEl I -

MClK

ICS90C65
---

SD2

VSElO

SD3

VSEl1
~

PWRDN

SElEN
14.318 MHz

VClK

-

MClK

-

VSEL2

ClKI

Figure 1

214

II

ICS90C65

System Bus Inputs

User-Definable Inputs

The system bus inputs are:

The user definable inputs are:

•
•
•

CLKI
VSELO
VSELI

The ICS90C65 uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used
as inputs to VSELO and VSEL I for video frequency selection.

Inputs from VGA Controller
SELEN

The ICS90C65 is programmed to generate different video
clock frequencies using the inputs of VSELO, VSEL I,
VSEL2, and VSEL3. The signals VSEL2 and VSEL3 may
be supplied by the VGA controller as is the case in Western
Digital Imaging VGA controllers. The inputs VSELO-I are
latched with the signal SELEN. The SELEN input should
be an active low pulse. This active low pulse is generated in
Western Digital Imaging VG A controllers during 110 writes
to internal register 3C2h.
Note: Only VSELO and VSELl are latched with signal
SELEN.

Outputs to VGA Controller
The outputs from the ICS90C65to the VGA controller are:
•
•

EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3
PWRDN

EXTCLK is an additional input that may be internaliyrouted
to the VCLK output. This additional input is useful for
supporting modes that require frequencies not provided by
the ICS90C65 or for use during board test.
VCLKE and MCLKE are the output enable signals for
VCLK and MCLK. When low the respective output is tristated.

The VGA controller input to the ICS90C65 is:
•

•
•
•
•
•

MCLK
VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

Analog Filters
The analog filters are integral to the ICS90C65 device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter is reduced as externally-generated noise cannot easily
influence the phase-locked loop filter.

215

MSELO-2 are the memory clock (MCLK) select lines. Table
1-2 shows how MCLK frequencies are selected. All signals
in this group have internal pull-up resistors.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table 1-1.
VSEL2 and VSEL3 have internal pullups.
PWRDN can place the ICS90C65 in a powerdown mode
which drops its supply current requirement below I microamp. When placed in this mode, the digital inputs may
be either high or low or floating without causing an increase
in the ICS90C65 supply current.
The PWRDN pin must be low (It has an internal pulldown.)
m order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high by the ICS90C65
when it is in its low power state.
If CLKI is being driven by an external source, it may be
driven low or high without a power penalty. If CLKI is at an
intermediate voltage (Vss+ 0.5 < VIN < VDD-O.S), there
will be a small increase in supply current. If CLKI is driven
at 14.318 MH z while the chip is in powerdown, the ICS90C65
supply current will increase to approximately 1.2 rnA.

The SELEN (pin 6) may be used to guard against inad vertent
frequency changes during powerdown/powerup sequences.
By holding the SELEN low during powerdown and powerup
sequences, the ICS90C65 will retain the most recent video
frequency selection.

ICS90C65
Power Considerations
+ 5V

The ICS9OC65 product requires an A VDD supply free of
fast rise time transients. This requirement may be met in
several ways and is highly dependent on the characteristics
ofthe host system. A VGA adapter card is unique in that it
must function in an unknown environment. + 5 Volt power
quality is dependent not only on the quality of the power
supplyresident in the host system, but also on the other cards
plugged into the host's backplane. Power supply noise
ranges from fair to terrible. As the VGA adapter manufacturer has no control over this, he must assume the worst. The
best solution is to create a clean + 5 Volts by deriving it from
the + 12 Volt supply by using a zener diode and dropping
resistor. A 470 Ohm resistor and 5.1 Volt Zener diode are
the least costly way to accomplish this. A .047 to .1 microfarad bypass capacitor tied from A VDD to A vss insures good
high- frequency decoupling of this point.
Laptop and notebook computers have entirely different
problems with power. Typically they have no + 12 Volt
supply; however, they are much quieter electrically. Because
the designer has complete control of the system architecture,
he can place sensitive components and systems such as the
RAMDAC and Dual Video/Memory Clock away from
DRAM and other noise-generating components. Most systems provide power that is clean enough to allow for jitterfree Dual VideolMemoryClock performance if the + 5 Volt
supply is decoupled with a resistor and 22 microfarad Tantalum capacitor. Digital inputs that are desired to be held at
a static logical high level should not be tied to + 5 Volts as
this may result in excessive current drain through the ESD
protection diode. The internal pullup resistors will adequately keep these inputs high.

C1
DVDD
11UF
470

+ 12V

R1

D1

C1

AVDD
VSS

4.7V I1UF

-=-

+

216

5V

"="

10
R1

C2

C3

AVDD

DVDD

!2UF lUF
VSS

AVSS

ICS90C65
Pin Descriptions
The following table provides the pin descriptions for the 20-pin ICS90C65 packages.
PIN
NUMBER

PIN
SYMBOL

TYPE

DESCRIPTION

1

CLKI

IN

2

MSEL2

IN

Select inp_ut for MCLK selection

3

EXTCLK

IN

External clock inQut for an additional frequency

VSELI

IN

Control input for VCLK selection

VSELO

IN

Control input for VCLK selection

SELEN

IN

Strobe for latching VSEL(O,l) (Low

7

VSEL2

IN

Control input for VCLK selection

8
9

VSEL3

IN

Control input for VCLK selection

MSELO

IN

10

DVSS

-

4
5
6

------

Reference input clock from system

enable~

Select input for MCLK selection
Ground for Digital Circuit

11

MSELI

IN

12

MCLK

OUT

13

PWRDN

IN

Power Down Control

14
15
16

MCLKE

IN

Enable input for MCLK output (hiJ!.h enables out/Jut)

AVDD
AVSS

-

Ground for analog circuit

17

N.C.

-

No connection

18
19

VCLKE

IN

VCLK

OUT

20

DVDD

-

Select input for MCLK selection
Memory Clock Output

Power supply for analog circuit

Enable input for VCLK output (hiJ!.h enables outvut)
Video Clock Output
Power supply for Digital Circuit

Note:
CLKI, EXTCLK,VSELO, VSELl,VSEL2, VSEL3, SELEN, MSELO, MSELl, MSEL2, VCLKE, and MCLKE - input pins
have internal pullup resistors. PWRDN has an internal pulldown resistor.

217

ICS90C65
Absolute Maximum Ratings
Ambient Temperature
under bias

o°c to 70°C

Storage temperature

_40°C to 125 °c

Standard Test Conditrons
The characteristics below apply for the following standard
test conditions, unless otherwise noted. All voltages are
referenced to Vss (OV Ground). Positive current flows into
the referenced pin.

0.3 to 7 Volts
Voltage on all inputs and
outputs with respect to V ss
Note: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Operating Temperature
range

o°c to 70°C

Power supply voltage

3.0 to 5.25 Volts

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:
l.REFCLK= 14.318MHz
2 .Te = liFe
3 All units are in nanoseconds (ns).
4.Maximum jitter is within a range of 30 ~s after triggering on a 400 MHz scope.
5.Rise and fall time is between 0.8 and 2.0 VDC unless otherwise stated.
6.0utput pin loading = 15pF
7.Duty cycle is measured at VDD/2 unless otherwise stated.
SYMBOL
Tpw
Tsu
Thd

PARAMETER

MIN
STROBE TIMING

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

20
20

-

-

-

-

@

S.OV
2
2
0.5
135
20

Duty Cycle 40% min. to
60% max.
%
MHz
ns

15

ns

-

3
3

-

110
30

Duty Cycle 40% min. to
60% max.
%
MHz
ns

20

ns

-

-

MCLK and VCLK TIMINGS
Tr
Tf

-

-

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
Output Enable to Tristate
(into and out of) time

-

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
Output Enable to Tri-State
(into and out of) time

@

3.3V

.5

218

NOTES

-

10

MCLK and VCLK TIMINGS
Tr
Tf

MAX

II

ICS90C65

DC Characteristics at 5 Volts Voo
SYMBOL

PARAMETER

MIN

MAX

UNITS

VDD

Operating Voltage Range

4.75

5.25

V

CONDITIONS

Input Low Voltage

Vss

0.8

V

VDD - 5V

Input High Voltage

2.0

VDD

V

VDD = 5V

lIH

Input Leakage Current

-

10

VOL

Output Low Voltage

-

0.4

J.LA
V

IOL = 8.0rnA

VOH

Output High Voltage

2.4

-

V

IOH = 8.0rnA

IDD
Rup

Supply Current

-

30

rnA

VDD = 5V

Internal Pullup Resistors

50

-

Kohrns

VIN = O.OV

Cm

Input Pin Capacitance

-

pF

Fe= IMHz

Output Pin Capacitance

pF

Fe= IMHz

Powerdown Supply Current

-

8
12
1.0

Internal Pulldown Equivalent

20

-

!lA
Kohrns

VIN= VDD= 5V

CONDITIONS

VIL
VIH

Cout

c__!rK
RDN

I

I

I

!

I

VIN = Vee

VDD= 3.3V

DC Characteristics at 3.3 Volts VOO
SYMBOL

PARAMETER

MIN

MAX

UNITS

VDD

Operating Voltage Range

3.0

3.6

V

VIL

Input Low Voltage

Vss

0.8

V

VDD = 3.3V

VIH

Input High Voltage

2.0

VDD

V

VDD = 3.3V

IIH

Input Leakage Current

-

10

!lA

Vm = VDD

VOL

Output Low Voltage

-

0.4

V

IOL = 3.0rnA

VOH

Output High Voltage

2.4

-

V

IOH = 3.0 rnA

IDD

Supply Current

-

20

Rup

Internal Pullup Resistors

100

-

rnA
I

!

VDD = 3.3V
I

Kohrns

VIN = O.OV

Cm

Input Pin Capacitance

pF

Fe= IMHz

Output Pin Capacitance

-

8

Cout

12

pF

Fe= IMHz

IPN

Powerdown Supply Current

-

1.0

RDN

Internal Pulldown Equivalent

50

-

!lA
Kohrns

VIN = VDD = 3.3V

219

VDD = 3.3V

ICS90C65

ENABLE TIMING
VSELO
VSEL 1

"-

/

"-

/

SELEN
tpwen

I

thden

r

tsuen

CLOCK WAVEFORM
te= 1Ife
tr

tf

2JN
O.8V

ICS90C65 TIMING

220

"/

ICS90C65
Table 1-1 VCLK SELECTION
VSEL
VCLKFREQUENCY(MHz)
3

2

1

0

Pattern 951

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

30.0
77.25

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

80.0
31.5
36.0
75.0
50.0

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

40.0
50.0
32.0
44.9

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

25.175
28.322
65.0
36.0

EXTCLK

Table 1-2 MCLK SELECTION
MSEL
MCLK FREQUENCIES (MHz)
2

1

0

Pattern 951

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

0
0
1
1

0
1
0
1

33.0
49.218
60.0
30.5
41.612
37.5
36.0
44.296

221

222

ICS9161

Integrated

_

Circuit

Systems, Inc.

Preliminary Information

Dual Programmable Graphics Frequency Generator
Features
•
•
•

•
•
•
•
•
•

Two fully user-programmable phase-locked loops are
offered in a single package. One PLL is designed to drive
the memory clock, while the second drives the video
clock. The outputs may be changed on-the-fly to any
desired frequency between 390 kHz and 120 MHz. The
ICS9161 is ideally suited for any design where multiple
or varying frequencies are required.

Pin for pin and function compatible with
ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying
frequencies are required
Increased frequency resolution from optional
pre-divide by 2 on the M counter
Output enable feature available for tri-stating
outputs
Independent clock outputs range from 390 kHz
to 120 MHz
Operation up to 140 MHz available
Power-down capabilities
Low power, high speed 0.8 !l CMOS technology
Glitch-free transitions
Available in 16 pin SOIC or PDIP package

This part is ideal for graphics applications. It generates
low jitter, high speed pixel clocks. It can be used to
replace multiple, expensive high speed crystal oscillators. The flexibility of the device allows it to generate
non-standard graphics clocks.
The ICS9161 is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The
low profile, 16 pin SOIC or PDIP package and low jitter
outputs are especially attractive in board space critical
disk drives.

General Description
The ICS9161 is a fully programmable graphics clock
generator. It can generate user specified clock frequencies using an externally generated input reference or a
single crystal. The output frequency is programmed by
entering a 24 bit digital word through the serial port.

Block Dia ram

[NIT1=;==========:~ ~

[NITO

~I

I

223

The leader in the area of multiple output clocks on a
single chip, ICS has been shipping graphics frequency
generators since October, 1990, and is constantly improving the phase locked loop. The ICS9161 incorporates a patented fourth generation PLL that offers the
best jitter performance available.

II

ICS9161
Pin Configuration
SELO-CLK

1

16

/PD

SELl-DATA

2

15

EXTSEL

VDD

3

14

INITl

13

VDD

12

INITO

......

n
(J)
\0
.....
0\
.....

OE

4

GND

5

Xl

6

11

EXTCLK

X2

7

10

/ERROUT

MCLK

8

9

VCLK

p
· f
In · o
eSCrlp'lon
Pin Name

Pin #

SELO-CLK

1

SELl-DATA

2

AVDD
OE
GND
Xl

3
4
5
6

X2

7
8
9

MCLK
VCLK
/ERROUT
EXTCLK
INITO
VDD
INITl
EXTSEL
/PD

10
11

12
13
14
15
16

Description
Clock input in serial programming mode
Clock select pin in operating mode
Data input in serial programming mode
Clock select pin in operating mode
Power
Tri-states outputs when low
Ground
Crystal input
Crystal output
Memory clock output
Video clock output
Output low signals an error in the serially programmed word
External clock input
Selects initial power-up conditions LSB
Power
Selects initial Dower-UD conditions MSB
Selects external clock input (EXTCLK) as VCLK output
Power-down pin, active low

224

II

ICS9161

Register Definitions

OE IPD

The register file consists of the following six registers:

0
1
1
1
1

Register Addressing
Address

Register

Definition

000
001
010
011
100

REGO
REGI
REG2
MREG
PWRDWN

110

CNTLREG

Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memory Register
Divisor for Power-down
mode
Control Register

1

1

x
0
1
1
1
1
1

VCLK Selection
EXTSEL
SELl SELO
x
x
x
x
0
1
x

x
x
0
0
1
1

1

x
x
0
1
0
x
1

VCLK
Tri-State
Forced High
REGO
REGI
EXTCLK
REG2
REG2

As seen in the table above, OE acts to tri-state the output.
The /PD pin forces the VCLK signal high while powering down the part. The EXTCLK pin will only be multiplexed in when EXTSEL and SELO are logic 0 and SEL 1 is
a logic 1.

The ICS9161 places the three video clock registers and the
memory clock register in a known state upon power-up.
The registers are initialized based on the state of the INITl
and INITO pins at application of power to the device. The
INIT pins must ramp up with VDD if a logical 1 on either
pin is required. These input pins are internally pulled
down and will default to a logical 0 if left unconnected.

The memory clock outputs are controlled by /PD and OE
as follows:
MCLK Selection
OE
IPD
MCLK
x
Tri-State
0
1
1
MREG
PWRDWN
1
0

The registers are initialized as follows:

Register Selection

The Clock Select pins SELO and SELl have two purposes.
In serial programming mode, these pins act as the clock
and data pins. New data bits come in on SELl and these
bits are clocked in by a signal on SELO. While these pins
are acquiring new information, the VCLK signal remains
unchanged. When SELO and SELl are acting as register
selects, a timeout interval is required to determine whether
the user is selecting a new register or wants to program
the part. During this initial timeout, the VCLK signal
remains at its previous frequency. At the end of this
timeout interval, a new register is selected. A second
timeout interval is required to allow the VCO to settle to
its new value. During this period of time, typically
5 msec, the input reference signal is multiplexed to the
VCLKsignai.

When the ICS9161 is operating, the video clock output is
controlled with a combination of the SELO, SELl, /PD,
and OE pins. The video clock is also multiplexed to an
external clock (EXTCLK) which can be selected with the
EXTSEL pin. The VCLK Selection Table shows how
VCLK is selected.

When MCLK or the active VCLK register is being reprogrammed, then the reference signal is multiplexed glitchfree to the output during the first timeout interval. A
second timeout interval is also required to allow the VCO
to settle. During this period, the reference signal is
multiplexed to the appropriate output signal.

.. rlzahon
R eglster I mha
INITl

INITO

MREG

REGO

REG1

REG2

0
0
1
1

0
1
0
1

32.500
40.000
50.350
56.644

25.175
25.175
40.000
40.000

28.322
28.322
28.322
50.350

28.322
28.322
28.322
50.350

225

ICS9161

Control Register Definitions
The control register allows the user to adjust various internal options The register is defined as follows·

Bit

Bit Name

Default Value

Description

9

C5

0

This bit determines which power-down mode the fPO pin
will implement. Power-down mode 1, C5 = 0, forces the
MCLK signal to be a function of the power-down register.
Power-down mode 2, C5 = 1, turns off the crystal and
disables all outputs.

8

C4

0

This bit determines which clock is multiplexed to VCLK
during frequency changes. C4 = 0 multiplexes the reference frequency to the VCLK output. C4 = 1 multiplexes
MCLK to the VCLK output for applications where the
graphics controller cannot run as slow as fREF-

7

C3

0

This bit determines the length of the timeout interval. The
timeout interval is derived from the MCLK VCo. If this
VCO is programmed to certain extremes, the timeout
interval maybe too short. C3 = 0, normal timeout. C3 = 1,
doubled timeout interval.

6

C2

0

Reserved, must be set to O.

5

CI

1

This bit adjusts the duty cycle. CI = 0 causes a Ins decrease in output high time. CI = 1 causes no adjustment.
If the load capacitance is high, the adjustment can bring
the duty cycle closer to 50%.

4

CO

0

Reserved, must be set to O.

3

NS2

0

Acts on register 2. NS2 = 0 prescales the N counter by 2.
NS2 = 1 prescales the P counter value to 4.

2

NSI

0

Acts on register 1. NSI = 0 prescales the N counter by 2.
NSI = 1 prescales the P counter value to 4.

1

NSO

0

Acts on register O. NSO = 0 prescales the P counter by 2.
NSO = 1 prescales the P counter value to 4.

226

ICS9161
Serial Programming Architecture
The pins SELO and SELl perform the dual functions of
selecting registers and serial programming. In serial
programming mode, SELO acts as a clock pin while SELl
acts as the data pin. The ICS9161-0l may not be serially
programmed when in power-down mode.
In order to program a particular register, an unlocking
sequence must occur. The unlocking sequence is detailed
in the following timing diagram:

SELl pins, and since any change in their state may affect
the output frequency, new data input on the selection bits
is only permitted to pass through the decode logic after
the watchdog timer has timed out. This delay of SELO or
SEL 1 data permits a serial program cycle to occur without
affecting the current register selection.

Serial Data Register
The serial data is clocked into the serial data register in the
order described in figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit
is sampled on the rising edge of CLK. The complement of
the data bit must be sampled on the previous falling edge
of CLK. The setup and hold time requirements must be
met on both CLK edges. For specifics on timing, see the
timing diagrams on pages 10, 11, and 12.

n
SELO-CLK
The unlock sequence consists of at least 5 low-to-high
transitions of CLK while data is high, followed immediately by a single low-to-high transition while data is low.
Following this unlock sequence, data can be loaded into
the serial data register.
Following any transition of CLK or DATA, the watchdog
timer is reset and begins counting. The watchdog timer
ensures that successive rising edges of CLK and DATA
do not violate the timeout specification of 2ms. If a
timeout occurs, the lock mechanism is reset and the data
in the serial data register is ignored.
Since the VCLK registers are selected by the SELO and

The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a
stop bit. A total of 24 bits must always be loaded into the
serial data register or an error is issued. Following the
entry of the last data bit, a stop bit or load command is
issued by bringing DATA high and toggling CLK highto-low and low-to-high. The unlocking mechanism then
resets itseIf following the load. Only after a timeout
period are the SELO and SELl pins allowed to return to a
register selection function.
The serial data register is exactly 24 bits long, enough to

Data Bits

Address Bits

LBS
STOP
BIT#

vco ProgWord

2

3

4

5

6

7

8

M'O M'1 M'2 M'3 M'4 M'5 M'6 RO

9

10

11

12

R1

R2

N'O

N'1 N'2

13

14

17

18

19

20

21

22

23

24

N'3 N'4 N'5 N'6

10

11

12 13

AO

A1

0

15

16

CNTL Reg

0

0

0

0

0

0

0

0

0

0

0

0 PSO PS1 PS2 CO

PWRDWN
Reg

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 1 - Serial Data Timing

227

C1
0

C2 C3

C4

C5

0

PO

P2

P3

0

P1

0

BIT#

VCO
ProgWord
CNTL Reg
PWRDWN
Reg

ICS9161
accept the data being sent. The stop bit acts as a load
command that passes the contents of the Serial Data
Register into the register indicated by the three address
bits. If a stop bit is not received after the serial register is
full, and more data is sent, all data in the register is
ignored and an error issued. If correct data is received,
then the unlocking mechanism rearms, all data in the
serial data register is ignored, and an error is issued.

The equations used to determined the oscillatorfrequency
are:
N=N' +3
M=M'+2
FyCO = Prescale· N/M· FCLK
where 35M 5129 and 4 5 N 5 130
and prescale = 2 or 4, as set in the control register
The value of FyCO must remain between 50 MHz and 120
MHz. As a result, for output frequencies below 50MHz,
FyCO must be brought into range. To achieve this, an
output divisor is selected by setting the values of the Mux
Field (R) as follows:

IERROUT Operation
Any error in programming the ICS9161 is signaled by
/ERROUT. When the pin goes low, an error has been
detected. It stays low until the next unlock sequence. The
signal is invoked for any of the following errors: incorrect
start bit, incorrect data encoding, incorrect length of data
word, and incorrect stop bit.

Output Divisor

Programming the ICS9161
The ICS9161 has a wide operating range, but it is recommended that it is operated within the following limits:
1 MHz < FREF < 60 MHz
200 KHz < FREF/M < 5 MHz
50 MHz < FyCO < 120 MHz
FCLK 5120 MHz

FREF = Input
Reference Frequency
M = Reference divide
3 to 129
Fvco = VCO output
frequency
FCLK = output
frequency

Index (I)
N counter value (N')
Mux(R)
M counter value (M')

Divisor
1
2
4
8
16
32
64
128

Unlike the ICD2061A, the ICS9161's VCO does not require tuning to place it in certain ranges. The ICS9161's
VCO will operate from 50 MHz to 120 MHz without
adjusting the VCO gain. However, to maintain
compatability, the I bits are programmed as in the
ICD2061A.
These bits are dummy bits except for the following two
cases:
Index Field (I)

The frequency of the programmable oscillator FyCO is
determined by the following fields:
Field

R
000
001
010
011
100
101
110
111

# of Bits

I

VCLKFvco

MCLK Fvco

4
7
3
7

1110
1111

Turn off VCLK
Mux MCLK to VLCK

50-120 MHz
50-120 MHz

Where the least significant bit is the last bit of M and the
most significant bit is the first bit of I.

When the index field is setto 1111, VCLKis turned off and
both channels run from the same MCLK VCO. This is
done in an effort to reduce jitter, which may increase
when VCOs run at 2n multiples of one another. If the two
outputs must be multiples of one another, it is best to mux
MCLK over to the output of the VCLK VCO, and to

228

ICS9161
power-down the VCLKVCO. The multiplexed frequency
will be divided down by the correct divisor (M) and
output on VCLK.

Power Management Issues

The power-down register divisor is determined according to the 4-bit word programmed into the PWRDWN
register (see table below).

Power-down mode 2

Power-down mode 1
The ICS9161 contains a mechanism to reduce the quiescent power when stand-by operation is desired. Powerdown mode 1 is invoked by pulling IPD low and having
the proper CNTL register bit set to zero. In this mode,
VCOs are shut down, the VCLK output is forced high,
and the MCLK output is set to a user-defined low frequency value to refresh dynamic RAM.
The power-down MCLK value is determined by the
following equation:
MCLKPD = FREF I (PWRDWN register divisor value)

When there is no need for any output during powerdown, an alternate mode is available which will completely shut down all outputs and the reference oscillator,
but still preserves all register contents. Power-down
mode 2 is invoked by first programming the power-down
bit in the CNTL register and then pulling the IPD pin low.

The/PO pin
The IPD pin has a standard internal pull-up resistor
during normal operation. When the chip goes into powerdown mode 1 or 2, the normal pull-up resistor is dynamically switched to a weak pull-up, which reduces power
consumption. If the IPD pin is allowed to float after it has
been pulled down, the weak pull-up will bring the signal
high and allow the device to resume operation.

Power Down Register Table
P3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

PWRDWNbits
P2
PI
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

PO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

PWRDWN
Register Value
0
1
2
3
4
5
6
7
8 (default)
9
A

B
C
D
E
F

229

MCLK

Power-down
Divisor

(fREF =14.31818)

n/a
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4

n/a
447.4 KHz
477.3 KHz
511.4 KHz
550.7 KHz
596.6 KHz
650.8 KHz
715.9 KHz
795.5 KHz
894.9 KHz
1.02 MHz
1.19 MHz
1.43 MHz
1.79 MHz
2.39 MHz
3.58 MHz

PD

ICS9161
Absolute Maximum Ratings
VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C

Storage temperature ................................ -40°C to + 150°C
Voltage on I/O pins referenced to GND ...... GND -0.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

Note. Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. ThIs is a stress rating only and
funchonal operation of the devices at these or any other conditions above those indicated In the operational sechons of thIS specification IS not
implied. Exposure to absolute maXImum conditions for extended perIods may affect devIce reliability.

Electrical Characteristics
(VDD = +5V ± 5%, O°C

~

TAMBIENT~ +70°C unless otherwise stated)

Device Specifications
Maximum Ratings
Name

Description

Min

Max

Units

VDD

Suvvlv volta2:e relative to GND
Input voltage with respect to GND

-0.5
-0.5

Operating temperature
Storage temperature

0
-65

Volts
Volts
°C

T~·TYW
T~()l

Max soldering temperature (10 sec)

T
Pmss

Junction temperature
Package power dissipation

7.0
VDD+0.5
+70
+150
+260
+125
350

VTl\
TOPf'R

DC Characteristics
Name
Description
Vnc

High level input voltage

Vn
Vore

L

Low level input voltage
High level CMOS ouput voltage
Low level output voltage
Input high current
Input low current
Output leakage current
Power suvvlv current
Power supply current (typical)
Analog power supply current
PmATPr-downJ'TTrrpnt (Moclp 1)

Ipn?

Power-down current (Mode 2)

VOT
InIn
107

Inn
Inn_TvP
kn

C'N

Min

Typ

Max

2.0
0.8
3.84
0.4
100
-250
10
65

15
35
6
25

Input capacitance

230

10
7.5
50
10

Units
V
V
V
V
Ila
Ila
Ila
rna
rna
rna
rna
Ila
pf

°C
°C
°C
mWatts

Conditions

Ioc = -4 rna
lOT = 4ma
VTH = 5.25 V
Vn =OV
(tri-state)
@60MHz

ICS9161
AC Characteristics

Symbol
fREF
tvcc
t1
t2
t3
t4
ts
t lrea1
tfreq2
tA
ttlmeout

tB

t6

t7

ts

t9
t 10
tn
tserclk

tsu
tHD
tldcmd

Name
Reference
frequency
Reference period
Input duty cycle
Output clock
I periods
Output duty
cycle
Rise times

Description
Reference oscillator value
(note 1)
l/fvcc
Duty cycle for the input oscillator
defined as t It
Output oscillator values

Duty cycle for the output
oscillators (note 2)
Rise time for the ouput oscillators
into a 25 of load
Fall times
Fall time for the output oscillator
into a 25 pf load
freql output
Old frequency output
freq20uput
New frequency output
Time clock output remains high whilE
fREF mux time
output muxes to reference frequency
Timeout internal Interval for serial programming and for VCO changes to
settle (note 3)
Time clock ouput remains high
tfreq2 muxtime
while output muxes to new
frequency value
Tri-state
Time for the ouput oscillators to go
into tri-state mode after OUTDIS signal assertion
CLKvalid
Time for the output oscillators to
recover from tri-state mode after
OUTDIS -signal goes high
Power-Down
Time for power-down mode of
operation to take effect
Power-Up
Time for recovery from power-down
mode of operation
MCLKOUT
Time for MCLK to go high
high
after PWRDWN is asserted high
MCLKOUT
Delay of MCLK prior to fMCLK
signal at output
delay
Llock perIod ot senal clock
Setup time
Hold time
Load command

Min

Typ

Max

Units

1

14.31818

60

Mhz

16.6

1000

ns

25%
8.33
(120 MHz)

75%
2564
(390 MHz)

ns

45%

55%

05 tREF

2
as tREF

5

ns

3

ns

1.5tREF

ns

10

ns

15tREF

ns

0

12

ns

0

12

ns

12

ns

12

ns

0

tpWRDWN

ns

05tMCLK

15 t MCLK

ns
msec
ns
ns
ns

tREF
20
10
0

1..

NOTES
1. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies w!ll ShIft proportionally.
2. Duty cycle IS measured at CMOS threshold levels. At 5 volts, VTH = 2.5 volts).
3. If the mterval,s too short, see the timeout interval section in the control register definition.

231

3

1.

t 1+30

ICS9161

t""IIIt--------tREF------~·
'-1"'__
'-- - - t 1 ·
......
,.

p

I

XTALIN
'REF

f-=

VCLK ___t4_
MCLK
-

10%

:r~~
t2

__

10%

Rise and Fall Times

aUTOIS·

VCLK
MCLK

tri-stated out ut

Tri-Stated Timing

232

I

j

}~----

ICS9161

SELO
SEL1

veo Settle time

Selection Recognition Time

1imeout

~I

VCLK

~
~req1

11meout

I·

New Frequency State

·1

\\J ~
I·

b.

Internal
TImeout

I
I
I

I
I

I

~
tA

tREF

·1· ; ·1- ·1
tB

tfreq2

Selection Timing

I
I
I

veo Settle time

Stop
Bit

New Frequency State

11meout
(Internal
Timeout)

----------+--:--7'
I

I

~~

VCLK
MCLK

I

H

I·

~req1

·1·; ·1 ~
tB

ltreq2

Or t MCLK if bit set
in Control Register

MCLK & Active VCLK Register Programming Timing

233

ICS9161

IPD------,
This IS when VCLK directly
muxes to VCLK PLL
: /(mayglltch)
I

19

~------------------~
forced high
VCLKM

~

IVCLK

i-

1VCLK 1

MCLK

fpWRDWN
(value from PWRDWN register)
1)lt takes 2-10 msec after soft
power-down to guarantee lock
of VCLK & MCLK PLLs

Soft Power-Down Timing (Mode 2)

Unlock Sequence

21~serclk31

Start Bit
I

41

CLK

DATA

Valid Data Sequence (24 bits)
CLK

DATA

Serial Programming Timing

234

I

Stop Bit I

ICS9161
Ordering Information
Part Number
ICS9161-xxCW16
ICS9161-xxCN16

Temperature Range
O°C to +70°C
O°C to +70°C

235

Package Type
16 lead Plastic SOIC
16 lead Plastic DIP

236

AV9194/AV90C64

Integrated
Circuit
Systems, Inc.

•

Dual Frequency Generator
Features

General Description

• Two independent clock outputs available
• On chip Phase Locked Loops with VCO and integrated loop filters for low jitter clock outputs
• Mask option for 16 + 4 frequencies, or 8 + 8
• Frequencies up to 130 MHz on each output clock
generated internally
• Low power CMOS technology
• 20 pin PDIP or SOIC package
• Minimum number of external components
• Tristate outputs
• Pin compatible with ICS2494 and ICS90C64
• Crystal oscillator circuitry with output clock
• 16 pin narrow SOIC (150 mil) or PDIP package
option available

The AV9194 is a dual output frequency generator that is
ideal for graphics applications. The device can replace
many crystal oscillators by containing all of the required
output frequencies on-chip. The A V9194 can use either a
crystal or TTL level clock for its input reference frequency. On notebooks and other motherboards, the
14.318MHz input can be generated by the AV9128/9 or
the AV9152/ 3 / 5. Utilizing ICS' proprietary analog CMOS
Phase Locked Loop (PLL) technology, this reference
frequency is used to generate two independently controlled output clocks, VCLK and MCLK. Up to 20 output
frequencies, ranging from 5 to 130 MHz, can be mask
programmed into the device at the time of manufacture.
The six Frequency Select pins are used to choose one of
16 (or 8) masked output frequencies on the video clock,
VCLK, and one of 4 (or 8) frequencies on the second
clock, designated MCLK. This second clock can be used
as a memory clock to time DRAMs and VRAMs, as
another video (or pixel) clock, or as a system clock
required by graphics processors like the 8514A and
34010/20. Standard versions of the AV9194 are available.

Applications
Graphics: Many video graphics systems now utilize multiple
clock oscillators to provide all of the frequencies required for
different monitors and modes of resolution. In addition, many
graphics processors require one separate fixed frequency for
the memory or system clock. By providing two independent
output clocks, the AV9194 saves power, board space, and cost
in eliminating these oscillators.

The AV9194 is one of the latest in ICS's frequency generator
family. ICS has devices that are designed for many computer
and computer peripheral applications, all manufactured in
analog CMOS technology.

Block Dia ram
~~~~ ]

VCLK

VFSO
VFSI
VFS2
VFS3
EN
ICLK/XI

~
~

--J..

X2~

VDD

I
I
I
.J

GND

--j

MFSI
MFSO

XTAL
OSC

~ XTALOUT
f + - - - - - - - . - - - - - - - - - - - -...I~

..

~

PHASE LOCK
LOOP
CONTROL LOGIC

~--~--------~~

I

~MCLK

_ _ _ .J

237

II

AV9194 / AV90C64
Pin Configurations
VDD

ICLK/Xl
X2
NC

VDD

ICLK

VCLK

NC

VCLK

XTALOUT

NC

OE

VFSO

GND

VFSI

VFSI

AGND

VFSO

ENorPD*

AVDD

EN

VFS2

NC

VFS2

VFS3

VDD

VFS3

>
-<

\0
0

n
0\

*"

NC
AGND
AVDD
NC
NC

MFSO

MCLK

MFSO

MCLK

GND

MFSI

GND

MFSI

"r

P"In 0 eSCrlp110n for AV9194 I AV90C64
Pin
Name
ICLK/Xl
X2

NC
VFSO
VFSI
EN
EN
PD*
VFS2
VFS3
MFSO
GND
MFSI
MCLK
VDD
NC
AVDD
AGND
GND
XTALOUT
OE
VCLK
VDD

Pin #
AV9194 AV90C64

1
2
3
4
5
6
-

6
7
8
9
10
11
12
13
14
15
16
17
18
-

19
20

1
-

3
5
4
-

6
-

7
8
9
10
11
12

Pin
type
Input
Output
-

Input
Input
Input
Input
Input
Input
Input
Input
-

Input
Out}Jut

-

-

14
15
16

-

-

-

-

Intput
Input
Output

18
19
20

-

-

Description
INPUT CLOCK. TTL clock signal or crystal input
CRYSTAL OUT. Connect when using crystal or ceramic resonator
NOT CONNECTED. No internal connection
VIDEO FREQUENCY SELECT 0 (LSB)
VIDEO FREQUENCY SELECT 1
ENABLE. Transparent high. A low latches the frequency select data
ENABLE. Latches VFSO-VFS3 and MFSO, MFSI upon rising edge
POWER DOWN. Turns off V+MCLK when low (AV9194-46 only)
VIDEO FREQUENCY SELECT 2
VIDEO FREQUENCY SELECT 3 (MSB)
MEMORY FREQUENCY SELECT 0 (LSB)
DIGITAL GROUND
MEMORY FREQUENCY SELECT 1 (MSB)
MEMORY CLOCK output
Digital power supply. Connect to +5V DC supply
NOT CONNECTED. No internal connection
Analog power supply. Connect to +5V DC supply
ANALOG GROUND
DIGITAL GROUND
CRYSTAL CLOCK OUTPUT
OUTPUT ENABLE. Tristates VCLK when low
VIDEO CLOCK output to drive pixel clock
Digital power supply. Connect to +5V DC supply

238

AV9194 / AV90C64
ABSOLUTE MAXIMUM RATINGS
AVDD, VDD referenced to GND ................................. 7V
Operating temperature under bias ............ O°C to +70°C
Storage temperature ................................ -40°C to +125°C
Voltage on flO pins referenced to GND ...... GND - O.5V
toVDD+O.5V

Power dissipation ................................................ 0.5 Watts
ESD rating as per MIL-STD-883D, Method 3015,
any pin.................................................................... 1800V

Note: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the devIce Tins IS a stress rating only and
functional operation of the deVices at these or any other conditIOns above those mdicated In the operational sections of this specification IS not
Implied. Exposure to absolute maXImum condItions for extended periods may affect deVIces reliability.

Electrical Characteristics

(VDD = +5V± 10%, TA
Symbol

= O°C to 70°C unless otherwise stated)

Parameter

Min

Typ

Max

Units

Conditions

DC "' ..
V,L
V,H
I'L(I)
IIH
VOL
VOH
VOH
VOH
100
IODSB

~P(l)
Fd
C,

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output High Voltage
Output High Voltage
Supply Current
Supply Current, Power Down
(AV9194-46 Only)
Internal Pullup Resistors
Output Frequency Change
over Supply and Temperature
Input Capacitance

-

0.8

-

2.0
-5
-

VDD-.4V
VDD-.8V
2.4

-

-50
5
0.4

-

20
30

50

500

V
V
IlA
IlA
V
V
V
V
mA
IlA

Voo=5V
Voo=5V
VIN=OV
VIN = VDD
10L = 8mA
10H= -lmA,VDD = 5.0V
10H= -4mA'VDD = 5.0V
10H= -8mA
No load. 28 and 40MHz
No load. 28 and 40MHz

KQ

0.005

%

8

pF

With respect to
typical frequency
Fc =1 MHz

NOTES: (1) Input pins VFSO-VFS3, MFSO, MFSl, EN, OE and PD* have internal pull-up resistors.
(2) Pins Xl and X2 have on-chip capacitors of 20pF to GND and are tied together by a IM!1
on-chip resistor.

AC Characteristics
tCLKR
tCLKF
tw
t
'u
t hd
t,
t,
tf
tf
d,
fIn
t,l'
t b

&:tax

Input Clock Rise Time
Input Clock Fall Time
Enable pulse width
Setup time data to enable
Hold time data to enable
Rise time, 0.8 to 2.0 Volts
Rise time, 20% to 80%
Fall time, 2.0 to 0.8 Volts
Fall time, 80% to 20%
Duty cycle, MCLK andVCLK
Input frequency, ICLK
Jitter, 1 sigma
Jitter, absolute
Maximum Output Frequency

20
20
20
20
10

-

5

239

-

1
2
2
4
1
2
2
4
48/52 40/60
14.318 20
±75
±325 ±500
130

ns
ns
ns
ns
ns
ns
ns
ns
ns
%
MHz
ps
ps
MHz

25 pf
25 pf
25 pf
25 pf
25 pf

load
load
load
load
load

II

AV9194 / AV90C64

AV9194 and AV90C64 Standard Versions
Mask

Number

AV9194-04

VGA
Controllers

Tseng Labs
ET4000

AV9194-07

53
S3
86C801,805,928 86C801,805,928

VCLK
ADDRESS
0
1
2
3
4
5
6
7
8
9
A

B
C
D
E
F

AV9194-12

AV9194-36

AV9194-37

53

Cirrus
Logic

Tseng Labs
ET4000

XTAL
65.028
EXTFREQ
36.00
25.175
28.322
24.00
40.00
44.90
50.35
16.257
32.514
56.644
20.00
41.539
80.00

50.350
56.644
65.00
72.00
80.00
89.80
63.00
75.00
25.175
28.322
31.50
36.00
40.00
44.90
50.00
65.00

55.00
60.00
70.00
65.00

55.00
75.00
70.00
80.00

86C911,924

VCLK OUTPUT (MHz)
25.175
28.322
32.514
36.00
40.00
44.90
50.35
65.00
50.35
56.664
65.028
72.00
80.00
89.80
75.00
108.00

25.175
28.322
40.0
0.00
50.00
77.00
36.00
44.90
130.00
120.00
80.00
31.50
110.00
65.00
75.00
94.50

MCLK
ADDRESS
0
1
2
3

AV9194-11

25.175
28.322
40.0
0.00
50.00
77.00
36.00
44.90
130.00
120.00
80.00
31.50
110.00
65.00
75.00
94.50

25.175
28.322
40.0
0.00
50.00
77.00
36.00
44.90
130.00
120.00
80.00
31.50
110.00
65.00
75.00
72.00

MCLK OUTPUT (MHz)
41.00
46.00
50.00
56.00

45.00
38.00
52.00
50.00

32.90
35.60
43.90
49.10

240

40.00
41.612
44.744
50.00

AV9194 / AV90C64

AV9194 and AV90C64 Standard Versions (continued)
Mask
Number

AV9194-42

AV9194-44

AV9194-46

AV9194-56

AV9194-60

AV90C64

VGA
Controllers

WD
WD90C30

CPU
Applications

NCR
77C22E

S3
86C911,86C924

Weitek
5X86

WD
(All)

50.35
56.644
33.25
52.00
80.00
63.00
0.00
75.00
25.175
28.322
31.50
36.00
40.00
44.90
50.00
65.00

30.00
77.25
0.00
80.00
31.50
36.00
75.00
50.00
40.00
50.00
32.00
44.90
25.175
28.322
65.00
36.00

40.00
33.333
45.00
50.00

41.61
37.50
49.22
44.30

VCLK
ADDRESS
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

VCLK OUTPUT (MHz)
30.00
77.250
EXTFREQ
80.00
31.50
36.00
75.00
50.00
40.00
50.00
32.00
44.90
25.175
28.322
65.00
36.00

20.00
24.00
32.00
40.00
50.00
66.667
80.00
100.00
54.00
70.00
90.00
110.00
25.00
33.333
40.00
50.00

MCLK
ADDRESS
0
1
2
3

25.175
28.322
36.00
65.00
44.90
50.00
80.00
75.00
56.644
63.00
72.00
130.00
90.00
100.00
110.00
120.00

25.175
28.322
40.0
0.00
50.00
77.00
36.00
44.90
130.00
120.00
80.00
31.50
110.00
65.00
75.00
72.00

MCLK OUTPUT (MHz)
36.00
44.347
37.50
44.773

16.00
24.00
50.00
66.667

50.00
60.00
65.00
75.00

55.00
75.00
70.00
80.00

Avasem is continually developing new standard versions of the AV9194.
Consult your local sales representative for the latest A vasem products.

241

II

AV9194 / AV90C64
A V9194 BOARD LAYOUT

c:::J
~ c:::J
~ c=J
~

o

,--,
L..---.J

~ c=J
c:::J
c:::J
c=J

~

To
System
VDD

OO-0.lI1F

resistor
if used
~ =connectionto

SYSTEM GROUND

W

ground plane

This is the recommended layout for the AV9194. Shown are the power connections
and the ground plane.
The most important feature is the isolated ground plane, connected at one point near
the 2.21LF and 0.1 ILF decoupling caps. The ferrite bead is optional, but will help with
EMI radiation from the power supply trace. In applications with an excessively noisy
power supply, a 10 n resistor in the power supply line (between the decoupling caps
and the ferrite bead, if used) is recommended to reduce induced clock jitter. The
traces to distribute power should be as wide as possible.
If a crystal or crystal oscillator is used, it should be surrounded by the isolated ground
plane. Clock output traces should be kept narrow, and distance over isolated ground
plane should be kept to a minimum to reduce coupling.

242

AV9194 / AV90C64
AV9194
Recommended External Circuit

I

+5V
loa
(see note #5)

(see note #4)

I

O.lIlF
Xl

14.318 MHz
crystal

X2

1
2

EXT

3

VFSO
VFSI

4
5
6
7
8
9
10

EN orPO*
VFS2
VFS3
MFSO
GND

>
-<

1.0
I-'
1.0
~

20
19
18
17
16
15
14
13

VDD
VCLK
XTALOUT
GND
AGNO
AVOO

-=

NC
VDD

12

MCLK

11

MFSI

-=
Notes:
1. Avasem recommends the use of an isolated ground plane for the A V9194.
All grounds shown on this drawing should be connected to this ground plane.
This ground plane should be connected to the system ground plane at a single point.
Please refer to AV9194 Board Layout diagram.
2. A single power supply connection for all VDO lines at the decoupling
capacitors is recommended to reduce interaction of analog and digital circuits.
The decoupling capacitors should be located as close to the VDD pins as possible.
4. The ferrite bead does not enhance the performance of the A V9194, but will
reduce EMI radiation from the VDO line.
5. The 10 a resistor is optional for noisy power supply applications. It is used to
reduce clock jitter which may be induced by excessive power supply noise.

243

AV9194 / AV90C64
Ordering Information
Part Number
A V9194-xxCN20
AV9194-xxCW20
AV90C64N
AV90C64M

Temperature Ran~e
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C

Packa~e Type
20 lead Plastic DIP
20 lead Plastic SOIC
20 lead Plastic DIP
20 lead Plastic SOIC

Note: The dash number following AV9194, (denoted by xx above) must be inCluded when ordering product since it
specifies the mask options being ordered. Please request an A V9194 customer order form when ordering custom
masks.

244

ICS
Video Timing Generator Applications

24S

246

•

Integrated
Circuit
Systems, Inc.

Application Note

Designing with ICS Video Dot Clock Generators
The ICS family of dot clock generators is a simple to use,
cost-effective solution to the generation of dot clock frequencies required by VGA and other graphics subsystems.
Application of these parts is fairly straightforward; however,
certain precautions should be taken to insure a low phase
jitter implementation when laying out circuit boards. The
ICS dot clock products are high-speed high-performance
mixed analog/digital IC products. As such they are capable
of generating very fast rise time signals « 1.5 nanoseconds).
Although ICS dot clock generators have digital inputs and
outputs, they are precision analog ICs. They are dependent
internally on stable, noise-free analog signals in the microvolt region for jitter-free operation.

I nternal Crystal Oscillator

I

5M
PIN

TO LOGIC

Grounding
The most common reason for poor performance of graphics
subsystems products is inadequate grounding. To achieve
maximum performance, a ground plane layer will be req uired for the area on which the dot clock generator is
placed. Typical graphics cards already have this layer as
many other parts of the subsystem such as the DRAM and
Ramdac require this as well. To prevent ground loops and
circulating currents associated with other parts of the subsystem from generating differential voltages across the circuitry used with the dot clock, a cut should be made in the
ground plane layer surrounding the dot clock circuitry so
that it connects with the main part of the groundplane at one
point. Preferably this will lead to a low noise area close to
the card edge connector. This insures that signals related to
logic, DRAM memory, and other circuitry will not be superimposed on VCO control inputs.

The Two-Layer VGA Board
Recently, competitive pressure in the VOA adapter market
has resulted in a high level ofinterest in designing a two-layer
VGA PC board. With some compromise in jitter performance, a successful two layer design may be achieved. The
success of a t\ro layer design is totally dependent on board
layout. Video RAM represents a highly capacitive load to
the VOA controller. Read/write operations result in high
currents in the order of amperes on the VGA board. If these
current pulses interact with the dot clock generator via
common ground paths, etc. the result will be highly unsatisfactory. If the ground paths to the VO A controller are not
robust, the relative ground bounce of the VGA controller,
dot clock generator, and Ramdac will create visuallyapparent problems. Component placement must be carefully
thought out with respect to ground currents if a two layer
design is to be successful. We strongly suggest that you
contact ICS applications engineering and submit a copy of
your layout and PCB artwork to us before you purchase
boards.

247

Crystal Oscillator & Crystal Selection
Most of the ICS family of dot clock generators have circuitry
onboard to implement a Pierce oscillator with the addition
of only one external component, a quartz crystal. Pierce
oscillators operate the crystal in anti- (also called parallel-)
resonant mode. See the AC Characteristics in the appropriate data sheet for the effective capacitive loading to specify
when ordering crystals.
So called series-resonant crystals may also be used with the
ICS dot clock generators. Be aware that the oscillation
frequency will be slightly higher than the frequency that is
stamped on the can (typically 0.005-0.01 % ).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
As it is necessary for this circuitry to be biased into the linear
region to implement the oscillator function these pins are
susceptible to noise pickup. Avoid routing digital signals or
the dot clock generator outputs underneath or near these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.

Reference Frequency
Alternatively, the bus clock signal at 14.31818 maybe used.
If this is done, an on-board buffer should be used to clean
up this signal, and prevent problems with noise, ringing, and
overshoot. If a bipolar buffer is used, the signal should be
capacitively coupled to XTALI as the internal oscillator is
internally biased to a Vnn/2 threshold. A .047 or .1 microfarad capacitor is recommended for this application.
HCMOS buffers may be directly connected to XTALI
through a 33 ohm series resistor. XT AL2 must be left
unconnected if an external clock is used.

Application Note

Bypassing

Soldering Considerations

High frequency bypassing of the ICS dot clock generator is
mandatory for proper operation. Short, low inductance connections are important between the analog and digital VDD
pins to the bypass capacitors and from the capacitor to
ground. When selecting capacitors to bypass this or any
other high-frequency device, the frequency of most concern
is not the operating frequency of the device, but the frequency equivalent to lIrisetime, in this case 500 MHz. Multiple bypass capacitors are preferable, with a small ceramic
disk placed as close as possible to the supply pin. The
capacitor, its leads, and the interconnect leads form a series
resonant circuit. This circuit should be resonant at a frequency well above the frequency of interest (500 MHz).
Therefore capacitor values of .047 microfarad or less will
provide more effective bypassing, forcing the bypassing to
operate on the capacitive side of resonance. A larger (1
microfarad or greater) tantalum bypass should parallel this
to reject lower frequency noise.

A problem that ICS applications engineering is beginning to
see quite often is related to the new water-based fluxes. Until
quite recently most fluxes used for PC board assembly were
of the activated rosin type. Wave soldering machines
sprayed flux directly on the solder side ofthe PCB, then the
board traveled through the solder wave. Boards were then
run through a vapor degreaser where trichlorethelyne
(TCE) or Freon were used to remove residual flux. Environmental considerations have all but eliminated the use of
these substances for flux removal.

"M icrophonics"
ICS applications engineering occasionally receives complaints about graphics subsystems being "microphonic." It
is claimed that our parts are subject to output jitter if they
are tapped on or vibrated. These problems invariably show
up on surface-mount board designs. When investigated, the
problem always turns out to be ceramic capacitors.
Small surface-mount ceramic capacitors are made with barium titanate dielectric material. Barium titanate is also used
to make microphones, ultrasonic transducers etc., as it is one
of the most efficient piezoelectric material. Soldering these
capacitors to aGIO glass epoxy PC board results in the
capacitor being placed in mechanical compression, as the
glass/epoxy material has a much higher coefficient of thermal expansion than does the barium titanate, a ceramic.
When the PCB cools after a soldering operation the capacitor is partially compressed and rigidly atached to the board.
Any vibration transmitted to the board results in flexure of
the capacitor which outputs a resultant voltage. Although
the same materials are used to make leaded components,
the wire leads decouple the mechanical stress and vibration
from the capacitor, and no problem results.
This phenomenon caused difficulties with graphics subsystems that used our first generation devices such as the
ICS1394, ICS1560, and ICS9OC63 which had external-loop
filter components. The ad vent of second generation dot
clock devices with integral loop filters has all but eliminated
this problem if double bypassing is used. The larger tantalum
capacitor is non-microphonic even in surface mount, and
readily absorbs mechanically generated voltage spikes from
the smaller (but more effective at high frequencies) ceramic
capacitor.

Rosin based fluxes are very stable non-conductive materials
at room temperatures and cause few problems even when
poorly cleaned. Water-based fluxes are hygroscopic, that is
they absorb water from the water vapor present in air. As
they are ionic compounds, they can cause a resistive film to
be left on boards that have been improperly cleaned. In
addition, the incresased usage of surface mount technology
has resulted in components being much closer to the PC
board surface, making it harder to adequately remove flux
from under these components. The smaller lead spacing and
higher density of these boards results in shorter leakage
paths, and a higher probability ofleakage related problems.
The problem typically manifests itself as a crystal oscillator
startup problem. A customer will call ICS and say that one
of our dot clock generator products refused to start. Replacing the device fixed the problem. As they have experienced
the problem several times they are requesting ICS Quality
Assurance to run a failure analysis. When we retest their
parts all appear to work normally.
When the customer replaced the part he inadvertently fixed
the problem. Board repair is invariably done with a soldering
iron and rosin core solder. Most often an aerosol can offlux
remover is used to clean up after a repair. Heating the solder
pads to remove and replace the suspected device will drive
any moisture from the PC board. The rosin flux has substances to entrap or neutralize ionic contaminants and, even
if not properly cleaned, leaves a waterproof coating. With
the offending conductive residue removed, the crystal oscillator circuitry is now capable of biasing itself back into the
linear re gion and will be able to start.
This source of problems could also cause jitter related
problems in first generation devices with external loop filter
components, as this circuitry exhibits very high impedances.
Straight digital circuitry is relatively immune to these problems; however, it may be causing similar problems with
Ramdac circuitry.
Make sure your PC board assembly operation is regularly
tested for ionic contamination and you will never see this
problem.

248

Application Note

Output Considerations

Power Supply Considerations

The output circUitry of the ICS family of dot clock generator
products exhibits a characteristic impedance of approximately 33 ohms. A series resistor of 33 ohms and an inexpensive ferrite bead in series with the output will greatly
reduce the radiated harmonics of the output signal without
otherwise impairing performance. This may be helpful in
meeting FCC requirements. The ICS dot clock generator
has consistently produced less interference than fixed frequencycrystal oscillators in this respect, as it is onlyproducing one frequency at a time and has nicely controlled rise
and fall times. See the comparative spectral plots ofthe rcs
dot clock generators and crystal oscillators and note the
relatively rapid rate that high frequency harmonics fall off
for the dot clock generator. In no case should a capacitor
be connected from the output signal to ground. At the
frequency equivalent to the risetime (500MHz) even a 6
picofarad oscilloscope probe is equivalent to a 50 ohm
reactance. The current, to charge and discharge this capacitor, has to be provided from VDD and ground. This capacitive loading defeats the purpose of our carefully controlled
bypassing circuitry, and is not required for meeting FCC
interference req uirements, if the series resistor and ferrite
bead are used.

ICS dot clock generators function as phase-locked loops. A
stable reference frequency is generated by the crystal oscillator. This frequency is divided down by a variable modulus
frequency divider and fed to the reference input of the phase
comparator. The feedback input of this phase comparator
is fed by a second variable modulus frequency divider; however, this divider chain is driven by a voltage-controlled
oscillator (VCO). The output of the phase comparator is a
tristate signal which produces a pulse which has a width
proportional to the phase difference between the reference
and feedback inputs. The polarity of these error pulses is
dependent on whether the feedback input leads or lags the
reference input. These correction pulses are integrated in
the loop filter and are applied to the VCO input in such a
polarity as to minimize the phase error. In a perfect system
this loop would settle with no remaining phase error and
remain there until a new frequency was required and different modulo divisors were selected. In practice, the loop can
correct for external disturbances as long as these disturbances occur more slowly than the loop natural frequency.
Changes in power supply voltage affect the gain of the VCO,
and the phase comparator. If they happen slowly enough,
the loop compensates and no error is introduced. Step
changes cannot be compensated for and must be elimmated.

XTALOSC

ICS Dot Clock Generator
MKR 26 MHz

fp

MKR 29 MHz

REF~~~-,~AT~T~EN~1.~OB~,-__, -__~__,-_-~B~7~.~O~B.m

fp

1121 dB/

REF~~~-,~A~TTTE~N~1~·rO~B-,,--,__- ,__- ,__-~B~~

1121 dB!

START 121 Hz
RES BW :3

MHz

Output Spectrum

249

Application Note

When a higher voltage supply is available, the simplest
approach is to regulate the analog supply voltage and eliminate the disturbance. In desktop PCs the + 12 volt supply
can be used either with a three terminal regulator or a zener
diode and dropping resistor.
Laptop and notebook computers pose a more difficult problem in that a higher voltage supply is not usually available.
The laptop/notebook electrical environment is more benign
than the desktop computer environment, as there is no
provision for using add-on boards that may inject unknown
quantities of noise into the system. ICS dot clock generators
are not particularly critical as to absolute supply voltage
level, only to step disturbances. A series resistor and bypass
tantalum electrolytic capacitor can be used to limit the rate
of change in supply voltage to a rate that can be handled by
the phase-locked loop. Two configurations are shown. Figure B is probably better where the va A controller presents
steady-state frequency-select information to the dot clock
generator. In applications where the va A controller presents frequency-select information on a bus and strobes the
dot clock generator when frequency-select data is valid.
Figure C is probably more appropriate because the bus
signals may overshoot and inject noise through the input
protection diodes.

Typical Power Supply Configurations
+5V~--------~~~====:;~

FIGURE A
OPTIMUM DESKTOP POWER CIRCUITRY

I

10

DVDD

Dot Clock
Generator
VSS.

Summary
ICS dot clock generators have revolutionized the personal
computer and workstation graphics function.The capability
to generate virtually any desired frequency at less cost than
a single crystal oscilator has expanded the versatility of
today's graphics systems for the PC beyond where high end
workstation performance was a few years ago. Size, PC
board real estate, and power requirements have shrunk to
the point where today's laptop and notebook computers
have graphics performance nearly as good as desktop machines. Systems design of a high-performance graphics system has been simplified so that with a few design precautions
outlined above high-performance graphics can be implemented in any system.

AVSS

FIGUREB
LAPTOP/NOTEBOOK COMPUTER POWER CIRCUITS

I

18

DVDD

Dot Clock
Generator
VSS.

1

AVSS

1

FIGUREC
LAPTOP/NOTEBOOK COMPUTER POWER CIRCUITS

250

II

Application Note

Common VGA Board Layout Mistakes

D.

E.

Suggestions tor a better layout:
A. Keep loop filter components (where required) close to dot clock generator and away from high speed DRAM circuitry.
B. Keep by-pass capacitor close to A VDD pin.

C. Move XT AL close to pins XT AL I and XT AL2. Keep fast logic signals away from this area.
D. Move oscillator can up between RAM and dot clock passive components.

E. Break ground plane level to create unipotential ground connection for dot clock circuitry.

251

252

•

Clock Generators

Integrated
Circuit
Systems, Inc.

Applications Brief

Understanding ICS Data Sheet Jitter Specifications
Introduction
ICS clock generator devices utilize frequency synthesis
based on phase locked loop (PLL) technology. Unless
carefully designed, PLL-based clock generators are subject
to excessive period variation, or 1itter." This applications
brief will help in the understanding of ICS jitter specifications.
In most processor and time keeping applications, an excess
of clock jitter does not affect operation. However, in other
applications such as video,data acquisition or data recovery,
clock jitter characteristics can be an important system design consideration. ICS is the most experienced manufacturer ofvideo and processor clock devices and has perfected
PLL based clock design. ICS produces clock devices exhibiting the lowest jitter and the least susceptibility to power
supply noise.

Understanding ICS Jitter
Specifications
Many ofthe ICS clock generator data sheets list output clock
jitter specifications in the AC Characteristics section. ICS
defines clock jitter as the difference in time of any given
clock period as compared to the mean clock period, which
is defined as I/frequency. This can be expressed as time
(psec) or as a percentage ofthe clock period.

Jitter, Absolute is the maximum deviation that would be
expected (plus or minus) from a mean clock period.
Jitter, 1 Sigm a is similar to an average deviation that would be
expected (plus or minus) from a mean clock period. This
specification assumes that, statistically, a sample of clock
cycle periods follow a normal probability function, which
indeed it typically does. Jitter, 1 Sign a is the jitter value at
one standard deviation (one sigma) of the jitter measurement population. This specification is useful in graphics
applications.

How ICS Clock Jitter is Measured
ICS characterizes output clock jitter using a Stanford Research SR620 Time Interval Analyzer. This instrument is set
up to take 2,000 clock period samples over a several second
period, therefore, random noncontiguous clock periods are
sampled. The measure data provided by the instrument is
the typical value listed in the data sheet (the SR620provides
both 1 Sigma and Absolute measurements). The maximwn
value listed is the worst case measurement expected over the
output frequency range, changes in operating conditions
such as supply voltage and temperature, and changes in the
semiconductor process.

253

254

•

~

ICS Clock Synthesizers

Integrated
Circuit
Systems, Inc.

Applications Note

Clock Output Frequency Accuracy
and Input Reference Topics
Clock Synthesizer Multiplication Ratio
Granularity

This application note addresses output frequency lICCUI'IICy
of ICS Clock Synthesizels. Output frequency lICCUI'IICy is
determined both by the programmable step size of the PIL
and input reference frequency IICCUI'IICJ. Input reference
circuits are also discussed, with emphasis on using a
discrete quartz crysts1 device.

ICS frequency generator ICs use the common PIL (phaseLocked-Loop) technique for clock generation. Figure 1
shows a simplified block diagram of a PIL based clock
generator which is applicable to all ICS clock generators.
This approach to clock generation uses an input reference
frequency that is multiplied by an integer ratio to obtsin the
desired output frequency. Once the PIL is "in lock"
(typically several milli-seconds after power up), the output
frequency of the chip is relsted to the reference frequency
ex4ctly by this programmed multiplication ratio.

Determining Your Frequency
Accuracy Needs
ICS clock synthesizer devices are used in a diversity of
applications all of which have different clock lICCUI'IICy
requirements. For example, in VGA graphics applications,
the pixel clock frequency can easily tolerate an inIICCUI'IICy
of 0.5" (5,000 ppm or part-per-million) or more since
CRT timing is uncritical. This is also true for the CPU and
other system clocks in mother board applications, as long as
maximum clock rates are not taken to literally. There are,
however, mother board applicstions that must have greater
IICCUI'IICJ. Floppy disk drive control chips typically require
a 24 MHz reference clock that is accurate to 0.1" (1,000
ppm). Modem and SCSI chips typically specify 0.0020.005" (20-50 ppm) lICCUI'IICy. Clocks used on the
motherboard for time keeping purposes will create a 1
minute-per-month inIICCUI'IICJ for every 0.0023" (23 ppm)
devistion from ideal frequency.
Musical instrument
synthesis demands higbly accurate clocks since even a small
error can produce audible beating with snother instrument.

fiN

IN'UT REfEIOfNCE FRECIlENCV)
(OUIPUT ClOCK FflEQUENCV)

four

~--------~tN~------~

Figure 1
Simplified Diagram of PLL-Based
Clock Generator Circuit
Referring to the PIL circuit in Figure I,

With improved clock frequency lICCUI'IICy comes increased
component cost and design complexity. System clock
lICCUI'IICy requirements should therefore be approached
realistically.

N snd M are limited to a range of integer values that are
predetermined in the clock synthesizer design. Considering
this limitation of discrete values, with a given liN, lOUT
can only be increased or decreased in finite step sizes.

255

II

ICS Clock Synthesizer App Note

Thus, a desired output frequency (the target frequency) may
not be hit exactly with a given reference frequency. The
size of the minimum frequency steps will be determined by
the devices N and M range. As an example, in the
AV9107, N can be assigned integer values from 2 to 128
and M from 2 to 32. Using a 14.31818 MHz reference, if
an output frequency of 50 MHz is desired, the closest
output frequencies achievable are 49.88 MHz (N/M =
108/31) or 50.11 MHz (N/M = 7/2). In general, the
AV9107 will have an approximate frequency error of
0.25 % due to the programming granularity.

error in the reference frequency will result in a +0.1 %
error in the output frequency (deviation from actual
frequency where applicable).
When choosing a reference frequency generator, precision
is associated with cost. The most accurate and costly
reference is a crystal oscillator module. The more common
and less expensive approach is to use a discrete extemaJ
quartz device (most ICS clock chips have built in crystal
oscillator circuitry).
Any stable and continuous clock signal (within the specified
frequency range) can be used as a reference clock for ICS
clock chips. Special circuit considerations are advised
when a clock signal, such a system clock or crystal
oscillator module output, is used to drive an ICS clock
generator that contains an integrated crystal oscillator
circuit. Please refer to the device data sheet or contact ICS
Applications Engineering.

Some of the ICS clock synthesizer data sheets list both
target and actual frequencies of the device. The target
frequency is the typical value required for the intended
application. For example, for processor clock devices,
target frequencies are typically round numbers such as 20,
25, 33.3 or 50 MHz relating to the rated CPU speed.
However, because the typical processor clock IC uses a
14.31818 MHz reference frequency, these exact target
frequencies cannot be obtained within practical limits of N
and M values. (The reference frequency of 14.31818 MHz
is chosen because it is a common system clock frequency
and quartz crystals at this frequency are readily available.)
Furthermore, there is no reason for a processor clock to be
extremely accurate (although it should be stable with little
jitter and maintain a good duty cycle).

Use of the Crystal Oscillator Module
A crystal oscillator module is a hybrid device that contains
a quartz crystal, an oscillator circuit and an output buffer
for the clock output. Since the internal circuit is trimmed
during manufacturing, very good frequency accuracy and
stability are achieved. These devices commonly yield
accuracy's of + \- 20 ppm and exhibit excellent stability
over time, temperature, and power supply voltage. The
device requires a power supply and typically outputs a
CMOS TIL-compatible output clock signal.

The actual frequency listed in the data sheet represents the
output frequency of the device as determined by multiplying
the ideal reference frequency of the device (exactly
14.31818 MHz) by the preprogrammed PLL ratio. Again,
the PLL ratio is programmed to obtain an actual frequency
as close to the target frequency as possible, within the
limitation of the device's Nand M integer ranges.

Use of the Discrete Quartz Crystal
Device
INPUT REFERENCE CLOCKS

Most ICS frequency generators contain an integral crystal
oscillator circuit. With such devices, an extemaJ quartz
crystal is connected between two specified device pins.
This forms a complete parallel-resonant crystal oscillator
circuit (also known as a Pierce oscillator). In most cases

Again by nature of the PLL technique, there will be a direct
correlation between the accuracy of the input reference
frequency and that of the output frequency. A +0.1 %.

256

II

ICS Clock Synthesizer App Note

the only external component required is the quartz crystsl,
since the required load capacitors and feedback resistor are
integrated onto the chip as well. The complete oscillstor
circuit is shown in Figure 2. With careful design, accuracy
to within +/- 100 ppm can be achieved.

This is also used when no internal load capacitors are
provided (refer to device data sheet).

ICS DEVICE

LOAD CAPACITANCE
TO CRYSTAL

AV91 07
AV9110
AV9128
AV9129
AV9154
AV9155
ICS1494
ICS1562
ICS1567
ICS1694
ICS2407
ICS2409
ICS2439
ICS2494
ICS2595
ICS2655
ICS5300
ICS9132

12pf
12 pf
12 pf
12 pf
12 pf
12 pf
15 pf
11 pf
15 pf
15pf
15 pf
15pf
15 pf
15 pf
15 pf
15 pf
12 pf
7.5pf

XTAL

Of---------,
PLL

REFERENCE
FREQUENCY

J
-

CR'ISTAL OSCILlATOR

CIRCU/IRV

J
-

CLOCK GENERATOR CHIP

Figure 2
ICS Clock Generator
Crystal Oscillator Circuit

Table 1
ICS Clock Generator
Capacitive Load to Crystal

Quartz crystal devices can be specified by the crystsl

manufacturer for either series or parallel resonant operstion.
All ICS clock generator devices use parallel resonant
operation, sometime referred to as "parallel mode" •
Parallel resonant crystals specify a load capacitance value
which must be observed to ensure an accurate oscillation
frequency.
Table 1 lists the load capacitance applied to the external
crystsl by various ICS clock generators. This is the total
measured load capacitance which accounts for stray
capacitance in the device package and printed circuit traces
(short lead length used).
The load capacitance on the crystsl can be increased by
applying external load capacitors as shown in Figure 3.
This is useful when the crystal's specified load capacitance
is above that provided the provided by the clock generator.

257

ICS Clock Synthesizer App Note

~~

XTAL

ell

I~~I

T

!L __________________________
Cp
II
Figure 4
Electrical Model of Quartz Crystal
CLOCK GENERATOR
CHIP

In a parallel resonant crystal oscillator circuit, such as used
in ICS clock synthesizer devices, an LC tank circuit is
created as illustrated in Figure S. CJlFF is the lump
capacitance consisting of CM' Cp, and external Cv

Figure 3
Connection of External
Load Capacitors
to Clock Generator Chip
The load presented to the crystal in Figure 3 is

The resonant frequency can then be calculated as:

CLl and CL2 should be equivalent values.

The resistance RS in the crystal has no effect on resonance
frequency. However, the active circuitry of the oscillator,
represented by the inverter in Figure 5, must have enough
"negative resistance" to overcome the loss imposed by RS.
This allows the LS tank voltage amplitude to increase and
maintain a full oscillation voltage swing. Most crystal
manufactures recommend a negative resistance magnitude of
at least five times the RS (or ESR) value to ensure oscillator
start up; ICS crystal oscillator circuits have a negative
resistance magnitude above 250 ohms.

Calculating Crystal Oscillation
Frequency Accuracy
When a quartz crystal is operated in a series resonant
oscillator, the crystal oscillates at it's series resonant
frequency determined by LM and CM (the crystal's
motional inductance and capacitance) as shown in Figure 4.

258

•

ICS Clock Synthesizer App Note

we assume that total CL variation can be +/- 3 pf, then
oscillation frequency error will be from -166.7 ppm to
+ 277.8 ppm. Even if assuming that external circuit
capacitance can be controlled, just considering the variation
of the AV9155's internal load capacitors, which vary -/10% or +/- 1 pf, would account for a oscillation frequency
error of -166 ppm to +75 ppm. Remember that oscillator
error due to CL deviation is in addition to other errors such
as the rated crystal frequency tolerance and the effects of
crystal temperature and aging (consult the crystal's data
sheet).

XTAL

C EFF

XTAL

osc
Crystal Power Dissipation

Figure 5
Electrical Model of Parallel Resonant
Quartz Crystal Oscillator Circuit

Crystal manufactures typically specify a suggested crystal
power dissipation range. This is the range within which the
crystal's temperature will not rise to the point of causing
excessive oscillation frequency drift. Maximum crystal
power dissipation is also typically listed. Well above the
suggested dissipation range, this is the limit above which
crystal damage can occur (it will stop working), over a
period of time.

The parallel resonant frequency of the crystal oscillator is
higher than the series resonant frequency of the crystal.
The fractional frequency "pulling" or the fractional amount
that the parallel resonant frequency will be above the series
resonate frequency can be calculated as

Most through-hole mount crystals specify a suggested
power dissipation of about 1 mW, well suited for ICS clock
generators. This is also true for the standard larger-sized
surface mount crystals.
Problems can arise with some smaller types of surface
mount crystals. A typical 14.318 MHz surface mount
crystal used with an ICS clock generator will dissipate
about 200 to 500 micro watts, depending on which clock
generator is used. Maximum crystal power ratings of only
100 micro watts or lower are not uncommon, however most
crystal manufactures will admit that this figure can be
exceeded by 5-10 times. For maximum power dissipation it
is best to consult directly with the crystal manufacturer.

If we know is, the series resonant frequency of the crystal,
we can then calculateip, the parallel resonant frequency as

fp =(1 +P)fs·
Let's take the example of a series 14.31818 MHz crystal
used with the AV9155. A typical value of CM is 20xl0- 15
farad (the crystal manufacturer can give you this
information). From Table I, we find that CL presented by
the AV9155 is 12 pf. In this case, P is calculated to be
0.0008333 andJP is calculated to be 14.33011 MHz which
is 833 ppm (parts per million) above the series resonant
frequency.

Calculating Crystal Power Dissipation
Power dissipation within the quartz crystal is caused by
oscillation current flowing through the crystal's effective
series resistance, shown as RS in Figure 4. This is
commonly listed as 'ESR' (Effective Series Resistance) in
the crystal data sheet. Power dissipation can be calculated
as

We can also use the above equations to determine
oscillation error caused by total CL error. In the example
of using the AV9155 where typical circuit CL is 12 pf, if

259

•

ICS Clock Synthesizer App Note

where ILC is the oscillation current in the LC tank circuit
shown in Figure 5. It is difficult to measure ILC during
oscillation, therefore we measure differential voltage across
the crystal and make the following substitution:

where/is the frequency of oscillation and VpK is the pesk
voltage across the crystal. Our final simplified equation is
now

Using the final equation it is easy to calculate approximate
power dissipation with readily obtainable values. VpK can
be measured with a high speed differential oscilloscope (low
capacitance probes must be used), or the curves of Figures
6 or 7 can be used for the following list of devices:
AV9107, AV9110, AV9128, AV9129, AV9154, AV9155.

Where VXTAL is the RMS voltage across the crystal.
ZXTAL consists of both the reactance of the inductor shown
in Figure 5 and resistance RS not shown. However, at
oscillation the inductive reactive is much larger than RS and
so the contribution of RS to ZXTAL can be ignored.
Therefore we can make the approximation that

As an example, lets say that we are operating an AV9155
with a VDD of 5 volts using a 14.318 MHz crystal with an
RS (or ESR) rating of 35 ohms. From Table 1 we find that
CL = 12 pf and from Figure 6 we find that VpK = 2.5
volts. Substituting values in the final equation above we
determine that crystal power dissipation is approximately
127 micro-watts.

Substituting in the earlier equation we get

By definition of a resonant circuit, the reactance's of the
crystal's inductance and the external load capacitance are
equal. This can be stated as

1

roLM = roC .
L

Again through substitution we now get

or

260

•
VpK

ICS Clock Synthesizer App Note

5

5

4

4
VPK

3

I

3
2

2

5

10

15

20

25

5

30

10

15

20

25

Frequency (MHz)

Frequency (MHz)

Figure 6
Peak Voltage Across Crystal
With vee = 5.0 Volts

Figure 7
Peak Voltage Across Crystal
With vee = 3.0 Volts

261

30

262

les
Video Timing Generator Product
Standard Frequency Patterns

263

264

ICS1494A
ICS1494 Pattern Request Form
ICS produces a selection of standard pattern ICS1494's pre-programmed for compatibility with many popular VGA
chipsets. Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will
apply. Contact ICS sales for details.

ICS Part
Number
Compatible
VGA
ChIDsets
Video Clock
Address
(HEXl
0
1
2
3
4
5
6

7
8
9
A

B
C
D
E
F
10
11
12
13
14
15
16
17

18
19
1A
IB
1C
1D
IE
IF

ICS1494·
523
Tseng Lab,
ET4000

ICS 1494·
527
Cirrus Logic

GD5320
GD6410

Frequency

Frequency

~MHz)

25175
28322
32.514
36000
40000
44900
65000
84.000
25175
28322
40.000
44.900
32514
28322
36.000
65.000
25175
28322
32.514
36000
40000
44900
56.000
65000
25.175
28322
32.514
40000
44.900
60000
80.000
84000

I
,

ICS1494530
NCR
77C22E

ICS1494535
AT!

Frequency

Frequency

(MHz)
42.950
48.770
92400
36000
50350
56.644
EXT
44.900
30240
32.000
110000
80.000
39910
44900
75.000
65000
42.950
48.770
92.400
36000
50.350
56.644
EXT
44900
30240
32000
110000
80000
39.910
44900
75.000
65000

(MHz)
XTAL
XTAL
16257
16257
EXTFREO
EXTFREO
32.514
32514
25175
25 175
28322
28322
24000
24000
40000
40.000
XTAL
25.175
16.257
28322
EXTFREO
36.000
36000
65.000
25.175
44.900
28.33~ r-- 50000
24000
56000
40.000
75.000
XTAL
25175
65028
28322
EXTFREQ
40000
36000
65000
25175
44.900
28.332
50000
24000
56000
40.000
75.000
44900
25175
50344
28322
16.257
EXTFREO
32.514
EXTFREO
56644
60000
20000
80.000
EXTFREQ
50000
EXTFREO
80.000
.(MH~

I

I

ICS 1494539
Tseng Labs
ET4000
' (2X Frea )

I

ICS1494540

ICS1494
543

RadIUs

Supermac

ICS1494
544
Selko-Epson

Frequency

Frequency

Frequency

Frequency

(MHz)
25175
28332
32.514
36000
40000
44900
50350
65000
33400
37.575
31480
41750
55 110
74160
77 250
80000
50.350
56664
65.028
72000
80000
89800
75000
108.000
70000
75000
85.000
90000
95.000
110.000
115.000
120.000

(MHz)
57283
12.273
14500
15667
112000
126000
30.240
91200
120000
48.000
50675
55.300
64.000
68.750
88500
51.270
100.000
95.200
55000
60.000
63.000
99.522
130000
80.000
25.175
28322
48000
76800
38400
43.200
61440
EXT

MHz)
14318
EXT
12273
15667
17734
25175
30.240
13.500
14.750
14187
55.000
57.283
64.000
80000
100.000
130.480
28.322
36.000
40000
40.900
44.900
50.000
62000
65.000
75000
89.211
99522
103.140
107350
111518
113.484
122320

(MHz)
28636
42105
47846
78431
XTAL
21053
50.350
25175
EXT
3.000
6.000
8.000
10000
12000
16000
20000
25.000
30.000
32000
33000
40.000
44.000
46.000
50000
60.000
66.000
70000
80000
90000
100.000
110.000
120.000

,

Standard frequency patterns are available and are included as an example.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
If the internal frequency to which the ICS 1494 remains locked when EXTFREQ is selected is critical, it should be specified.
Order info: ICSI494M-XXX or ICSI494N-XXX (M= SO pkg., N= DIP pkg., XXX = Pattern number)

265

II

Ie S2494/2494A
ICS2494 Standard Patterns

ICS produces a selection of standard pattern ICS2494's pre-programmed for compatibility with many popular VGA
chip sets. Custom patterns are also available, although a significant volume commitment and/or one-time mash charge will
apply. Contact ICS sales for details.

ICS Part
Number

CompatIble
VGA
Chlpsets
VIdeo Clock
Address
(HEX)
0
I

2
3
4
5
6
7
8
9
A
B

C
D
E
F
Memory
Clock
Address
(HEX)
0
I

2
3

ICS2494·
236
ICS2494A·
310*1
CIrrus LogIC
GD6410

ICS 9294·
237
ICS2494A·
304*2
Tseng Labs
ET4000
ET400·W32
Acer M3125

ICS2494·
240

ICS2494·
244
ICS2494A
317*3
MOlherboard
ApplIcatIOns
(CPU Clocks)

ICS2494·
245/307

Frequency

Frequency
(MHz)
50.350
56.644
65000
72000
80000
89.800
63000
75.000
25175
28.322
31500
36.000
40.000
44.900
50.000
65.000

Frequency

(MHz)
XTAL
65.028
EXTFREO
36.000
25.175
28.322
24.000
40.000
44.900
50350
16.257
32.514
56.644
20.000
41.539
80.000

Frequency
(MHz)
20000
24.000
32.000
40.000
50.000
66.667
80.000
100.000
54.000
70.000
90.000
110.000
25.000
33.333
40.000
50.000

Frequency

Frequency

(MHz)

(MHz)

Frequency
(MHz)

32.900
35.600
43.900
49.100

40.000
41.612
44.744
50.000

64000
40000
48.000
60.000

Texas. Instr
TMS34010
TMS34020

(MHz)
25.175
28.332
28.636
36.000
40.000
42.954
44.900
57272
60.000
63960
75.000
80.000
85000
99.000
102000
108.000

ICS2494·
247

ICS2494·
253

ICS2494·
256 .

Cirrus Logic

GD5320

NCR
77C22E

S3
86C911
86C924

Frequency

Frequency

Frequency

Frequency

(MHz)
50.350
56644
65000
72000
80.000
89.800
63.000
75.000
25.175
28.322
31.500
36.000
40.000
44.900
50.000
77.500

(MHz)
XTAL
16.257
EXTFREO
32.514
25.175
28322
24.000
40.000
XTAL
16.257
EXTFREO
36.000
25.175
28.322
24000
40.000

(MHz)
25.175
28.322
40.000
65000
44900
50.000
130.000
75.000
25175
28.322
EXTFREO
EXTFREO
60.000
80000
EXTFREO
EXTFREO

(MHz)
25.175
28.322
40.000
EXTFREO
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
72.000

Frequency

Frequency

Frequency

Frequency

(MHz)

(MHz)

(MHz)

(MHz)

Frequency
(MHz)

16.000
24.000
50.000
66667

40.000
41.612
44.744
50.000

31000
36.400
43.900
49.100

50.000
60.000
65.000
75.000

55.000
75.000
70.000
80000

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-3l8 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

266

II

I CS2494/2494A

ICS Part
Number

ICS2494260

ICS2494263

Compatible
VGA
Chlpsets

Weltek
W5086
W5186

NCR
77C22E

ICS2494318*4
CIrrUS Logic
GD5410

Video Clock
Address
(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

Frequency
(MHz)
50.350
56.644
33.250
52.000
80.000
63.000
EXTFREO
75000
25.175
28.322
31.500
36.000
40.000
44.900
50.000
65.000

Frequency
(MHz)
25.175
28.322
36.000
65.000
44.900
50.000
80.000
75000
25.175
28.322
EXTFREO
EXTFREO
60000
80.000
EXTFREO
EXTFREO

Frequency
(MHz)
30.250
65000
85000
36000
25.175
283.322
34.000
40000
44.900
50.350
31500
32.500
63.000
72.000
75.000
80.000

Frequency
(MHz)

Frequency
(MHz)

40.000
33333
45.000
50.000

50.000
40.000
65.000
75000

Memory
Clock
Address
(HEX)
0
1
2
3

ICS2494273

ICS2494275

ICS2494277

ICS2494280

ICS2494281

Headland
HT216
HT216-32

S3
86C801
86C805
86C928

NCR
77C22E+

S3
86C801
86C805

Tseng

Frequency
(MHz)
25.175
28322
EXT
44900
41.539
78.000
79.200
80.000
31.469
35.402
EXTFREO
56.125
51.924
91.000
87406
36.000

Frequency
(MHz)
25175
28322
40.000
32.500
50350
65.000
38000
44.900
31.500
36.000
80.000
63.000
50.000
100.00
76.000
110.000

Frequency
(MHz)
25175
28.322
40.000
EXTFREO
50.000
77000
36.000
44.889
130000
120000
80.000
31500
110.000
65.000
75.000
94.500

Frequency
(MHz)
25175
28.322
36.000
65.000
44.900
50.000
80.000
75.000
56.644
63000
72.000
130.000
90.000
100.000
110.000
120.000

Frequency
(MHz)
25.175
28.322
40.000
EXT
50.000
77000
36000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
50350
56.644
65.000
72.000
80.000
89.800
63.000
75.000
83078
93.463
100.000
104.000
108.000
120000
130.000
134.700

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

36.000
44000
49.000
40000

51.924
41539
44900
56125

70.000
63.830
60.000
81.000

45000
38.000
52000
50.000

50.000
60.000
65.000
75.000

55000
60.000
70000
65.000

50.000
55.000
60.000
65.000

ICS2494

266

ICS24942711321

* 1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

267

Ie S2494/2494A
ICS Par!
Number
Compatlble
VGA
ChIDse!s
Video Clock
Address
(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Clock
Address
(HEX)
0
1
2
3

ICS2494A305
S3
86C924

ICS2494306
CIrrus LOgIc
GD6410
GD6412

Frequency
(MHz)
25.175
28.322
40.000
EXTFREO
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
XTAL
65.000
EXTFREO
36.000
25.175
28322
24.000
40000
44.900
50350
16.257
32.514
56.644
20.000
41.539
80.000

Frequency
(MHz)
55.000
75.000
70.000
80.000

ICS2494314
Texas

ICS2494A319

ICS2494A320
AdvanceLogIc
ALG2101
ALG2201

ICS2494A322

ICS2494A324
Tseng Labs
ET4000
ET4000W32

Frequency
(MHz)
12.273
13.500
14.750
25.175
28322
36.000
40.000
44900
50.000
64.000
75.000
80.000
100.000
108.000
120.000
135.000

Frequency
(MHz)
25.175
28.322
40.000
72.000
50.000
77.500
36.000
44.900
63.000
100.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
50.350
56.644
89.800
72000
75000
65.000
63.000
80.000
57.272
85.000
94.000
96.000
100.000
108.000
110.000
77.000

Frequency
(MHz)
20.000
20.480
24.576
24.704
25.216
25.248
25.600
26.000
28.800
29.491
30.720
32.768
33.6000
44.736
9.600
20.500

Frequency
(MHz)
50.000
56.644
65.000
72.000
80000
89.800
63.000
75.000
83.078
93463
100.000
104.000
108.000
120.000
130.000
134.700

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

32.900
35.600
43.900
39.900

32.000
40.000
48.000
60.000

48.000
52.500
55000
50.000

76000
80.000
85.000
90.000

15.360
13.947
13.947
24.000

50.000
56.000
60.000
65.000

Instruments

* 1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

268

ICS2494/2494A
ICS Par!
Number
Compallble
VGA
ChIDse!s
VIdeo Clock
Address
!HEX)
0
I
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Clock
Address
(HEX)
0
I
2
3

ICS2494325
Maxtek

ICS2494326

ICS2494330

ICS2494334

ICS2494-

ICS2494

ICS2494-

Frequency
(MHz)
25175
28322
31500
36000
40.000
44.900
50.350
65.000
56.644
7200
75000
77000
80000
94500
120.000
108.000

Frequency
(MHz)
66000
62.000
61236
61.000
60.500
60000
59.300
59.000
58968
57200
56.200
55500
40.000
38200
32.500
30.500

Frequency
(MHz)
18.432
31.470
50000
EXTFREO
48000
54.000
59.200
75500
96.000
108778
73.410
50.490
110.439
100.000
125.000
135.000

Frequency
(MHz)
25175
28.322
31500
36.000
40000
44900
50.000
65000
75000
77500
80.000
90000
100000
110.000
126000
135000

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

45.000
50.000
65.000
70.000

48.000
50000
40.000
60000

47.720
45.000
40.000
50.000

60.000
50.000
55.000
50.000

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

269

II

ICS2492

ICS2492 Pattern Request Form
In addition to the pattern below, custom patterns are also available, although a significant volume commitment and/or
one-time mask charge will apply. Contact ICS sales for details.

ICS Part
Number

ICS2492-453

Address FS3-0
(Hex)

Frequency
(MHz)

Application

0
I
2
3
4
5
6
7
8
9
0
B
C
D

20

286-10
-12
386-16
-20
-25
-33
-40
-50
TURBO-27
-35
-45
-55
486-25
-33
-40
-50

24
32
40
50
66.6
80
100
54
70
90
110
25
33.3

F

40
50

AddressMSO
(Hex)

Frequency
(MHz)

Application

0
1

16
24

AT-BUS
FDC

E

ICS2492Custom
Pattern # I
Frequency
(MHz)

Frequency
(MHz)

Custom pattern # 1 reference frequency =
The standard frequency shown has been specified by and is supported by the respective VGA manufacturer.
The standard pattern shown above uses _ _ MHz as the input reference frequency.
Order info: ICS2492M-XXX or ICS2492N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

270

ICS2495
ICS2495 Pattern Request Form
Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will apply.
Contact ICS sales for details.

ICS Part
Number

ICS2495-

ICS2495-

Compatible
VGA
Chipsets

Custom
Pattern # 1

Custom
Pattern # 2

Video Clock
Address (HEX)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

0
1
2
3
4
5
6
7

8
9
A
B

C
D
E
F
Memory Clock
Address (HEX)

0
1
2
3

Custom pattern # 1 reference frequency =
Custom pattern # 2 reference frequency =
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
If the internal frequency to which the ICS2495 remains locked to is critical when EXTFREQ is selected, it should be
specified.
Order info: ICS2495M-XXX or ICS2495N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

271

ICS2496
ICS2496 Pattern Request Form
rcs produces a selection of standard pattern ICS2496's pre-programmed for compatibility with many popular VGA chipsets.
Custom patterns are also available although a significant volume commitment and/or one-time mask charge will apply. Contact
rcs Sales for details.
rcs Part
Number
Compatible
VGA
Chipsets
Video Clock
Mlress(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C

ICS2496452
Cirrus Logic
GD64lO

ICS2496454
Cirrus Logic
GD6412

Frequency
(MHz)
XTAL
65.000
EXTFREQ
36.000
25.175
28.322
24.000
40.000
44.900
50.350
16.257
32.514
56.644

Frequency
(MHz)
XTAL
65.000
EXTFREQ
36.000
25.175
28.322
24.000
40.000
44.900
50.350
16.257
32.514
56.444

rCS2496456
Motherboard
Applications
(CPUOocks)
Frequency
(MHz)
20.000
24.000
32.000
40.000
50.000
66.667
80.000
100.000
54.000
70.000
90.000
110.000
25.000

D
E
F

20.000
41.539
80.000

20.000
41.539
80.000

33.333
40.000
50.000

Memory
Clock
AI:klres<;(HEX)

Frequency
(MHz)

Frequency
(MHz)

FreqUen?
(MHz)

0
1
2
3

32.900
35.600
43.900
49.100

32.900
35.600
43.900
39.900

16.000
24.000
50.000
66.667

Standard frequencies shown have been specified by and are
supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the
input reference frequency.
Order info:

rCS2496M-XXX or rCS2496N-XXX
(M=SO package, N=DIP package,
XXX=Pattern number).

272

ICS

GENDACTM

Products

ICS GENDACs provide highly integrated mixed-signal solutions for advanced VGA controllers.
These products have been designed utilizing ICS's proven technology for exceptionally low-jitter
video clock synthesizers and high-accuracy video DACs. The definitions for these products were
written with the close cooperation of VGA controller manufacturers to ensure our customers
maximum design flexibility. Our 16-bit pixel path devices are leading edge components for video
systems and establish the industry standard with 70 hertz refresh requirements at resolutions of
1280 x 1024 pixels.

273

ICS GENDAC Products Selection Guide
Product
Applications

rcs
Device Type
rCS5300

rCS530l

Personal Computer and
Engineering Work
Station Computer Graphics

ICS5340

ICS5341

I

Features

Package Types

8-bit Pixel Port, Triple 8-bit Video
DACs, Operation to 135 MHz.
7 Selectable P-Clock Frequencies
(5 Programmable).

44 Pin PLCC

Tseng Compatibility, 8-bit Pixel Port,
Triple 8-bit Video DACs, Operation
to l35MHz. 7 Selectable P-Clock
Frequencies (5 Programmable).

44 Pin PLCC

l6-bit Pixel Port, Triple 8-bit Video
DACs, Operation to 135 MHz.
I 2:1 Pixel MUltiplexing. 7 Selectable
P-Clock Frequencies (5 Programmable).
.
2 Selectable and Programmable
M-CIock Frequencies.

68 Pin PLCC

Tseng Compatibility, l6-bit Pixel Port,
Triple 8-bit Video DACs,
Operation to 13SMHz.
2:1 Pixel Multiplexing. 7 Selectable
P-Clock Frequencies (5 Programmable).
2 Selectable and Programmable
M-Clock Frequencies.

68 Pin PLCC

ADV ANCE INFORMATION documents contam mformatIOn on new products
data and other specIficatIOns are subject to change WIthout notIce,

In

Page

275

303

331

363

the sampling or preproductIOn phase ofdeve]opment CharactenstIc

PRODUCT PREVIEW documents contam infOrmatIOn on products In the formatIve or de~lgn phase of development Characteflstlc data and other
'ipeclflcatlons are design goals IeS reserves the nght to change or dlscontmue these products \VIthout notIce.

274

•

ICS5300
GENDAC

Integrated
Circuit
Systems, Inc.

a-bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5300 GENDAC is a combination of dual programmable clock generators, a 256 x I8-bit RAM, and a triple
8-bit video DAC. The GENDAC supports 8-bit pseudo
color applications, as well as IS-bit, I6-bit and 24-bitTrue
Color bypass for high speed, direct access to the DACs.

• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)

The RAM makes it possible to display 256 colors selected
from a possible 262, 144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, 6 of
which are programmable by the user. The memory clock
has one programmable frequency location.
The three 8-bit DACs on the ICS5300 are capable of
driving singly or doubly-terminated 75Q loads to nominal 0 - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

• One programmable memory (controller) clock
frequency (CLKl)
•
•
•
•
•
•

DAC power down in blanking mode
Low power operation
Anti-sparkle circuitry
On-chip loop filters reduce external components
Standard CPU interface
Single external crystal (typically 14.318 MHz)

• Monitor Sense
• Internal voltage reference
• 135 MHz (-3),110 MHz (-2) & 80 MHz (-1)
versions
• Very low clock jitter

Block Diagram
SENSE'

f+-+-I.... RED

PO-P7

~~::GREEN
L~...k----~~¥EET
VREF

~PCLK

DO-D7

~--

~--------------------------------------------~CLKO

't---------------------------------------------~CLKI

275

I

ICS5300
GENDAC

•
*
Offio
,...,oE-<
&~zGiJlCJlvs~~5~
:S:uffiuuuuuu><><

Pin Configuration
RD*
DO
D1

D2
D3
D4
D5
D6
D7
RSO
RSI

'-Ol!")~r'lN""':;j:~~::;~

7
8
9
10
11
12
13
14
15
16
17~

GENDAC I

ICS5300

CJ',O""'Nr'l~l!")'-Ot>OO
~NNNNNNNNN

39
38
37
36
35
34
33
32
31
30
29

BLANK*
PCLK
P7
P6
P5
P4
P3
P2
PI
PO
DVDD

Pin Description (68 pin PLCC)
Pin #

Type

Description

CSI

1

Input

CS2

2

Input

CGND
SENSE*

3
4

Output

CVDD
WR*

5
6

Input

RD*

7

Input

8 -15

I/O

Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Ground for clock circuits. Connect to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
Clock Power Supply. Connect to DVDD
RAM/PLL Write Enable, active low. This signal controls the timing of the
write operation on the microprocessor interface inputs, DO-D7.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
System data bus I/ O. These bidirectional Data I/ 0 lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.

Symbol

DO- D7

-

-

276

ICS5300
GENDAC

•
Pin Description (continued)
Symbol

Pin #

Type

RSO
RS1
RS2
CGND
CVDD
RED
GREEN
BLUE

16
17
18
19
20
21
22
23

Input
Input
Input

Output
Output
Output

AVDD
RSET

24
25

Input

AGND
DGND
VREF

26
27
28

Input

DVDD
PO-P7

29
30 - 37

Input

PCLK

38

Input

BLANK*

39

Input

XIN
XOUT
CLKO

40
41
42

Input
Output
Output

CLK1
CSO

43
44

Output
Input

-

-

-

-

Description
Register Address Select o. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Ground for clock circuits. Connect to ground
Clock Power Supply. Connect to AVDD
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value. These
outputs are typically used to drive a CRT monitor.
Analog power supply. Connect to A VDD
Resistor Set. This pin is used to set the currentlevel in the analog outputs.
It is usually connected through a 140Q, 1% resistor to ground.
Analog Ground. Connect to ground
Digital Ground. Connect to ground
Internal Reference Voltage. Normally connects to a O.IIlF cap to
ground. To use an external Vref, connect a 1.235V reference to this pin.
Digital power supply.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be grounded if they are not used.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address Anding inputs. This clock also controls the progress of these
values through the three-stage pipeline of the Color Palette RAM,
DAC, and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be updated through DO-D7 during blanking.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
Memory clock output. Used to time the video memory.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.

277

ICS5300
GENDAC

Internal Registers
RS2 RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENDAC. This register
can be accessed through either register address 0,0,0 or register address
0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.
Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
color values to the color palette RAM.

1

Pixel Address
READ

Writing to this 8-bit register is performed prior to reading one or more
color values from the color palette RAM.

1

Color Value

° ° °
°
° °
1

The 18-bit Color Value register acts as a buffer between the microprocessor
interface and the color palette. Using a three bytes transfer sequence allows
a value to be read from or written to this register. When a byte is read, the
color value is contained in the least significant 6 bits, DO-D5 (the most
significant 2 bits are set to zero). When writing a byte, the same 6 bits are
used. When reading or writing, data is transferred in the same order - the
red byte first, then green, then blue. Each transfer between the Color Value
register and the color palette replaces the normal pixel mapping operations
of the GENDAC for a single pixel.
After writing three definitions to this register, its contents are written to the
location in the color palette RAM specified by the Pixel Address register,
and the Pixel Address register increments.
After reading three definitions from this register, the contents of the location
in the color palette RAM specified by the Pixel Address registers are copied
into the Color Value register, and the Pixel Address register increments.

°

1

°

Pixel Mask

The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
position in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask register
does not affect the Pixel Address generated by the microprocessor interface
when the palette RAM is being accessed.

278

ICS5300
GENDAC

II
Internal Registers (continued)
RS2

RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

1

0

0

PLLAddress
WRITE

Writing to this 8-bit register is performed prior to writing one or more
PLL programming values to the PLL Parameter register.

1

1

1

PLLAddress
READ

Writing to this 8-bit register is performed prior to reading one or more
PLL programming values from the PLL Parameter register.

1

1

0

Command

This8-bit register selects the color mode, for instance 8-bit Pseudo Color, HiColor, True Color, or XGA, and DAC power down. The registers are reset
to pseudo color mode on power up.

1

0

1

PLL
Parameter

There are sixteen parameter registers as indexed by PLL Address Write/
Readregisters. Parameter registers 00-00 and OF are two bytes long and OE
is one byte long. This register set contains one control register. The bits of this
register include clock select and enable functions, the rest contain PLL
frequency parameters. After writing the start index address in the PLL
address register, these registers can be accessed in successive two (or one)
bytes. The address register auto increments after one or two bytes to access
the entire register set.

279

I

ICS5300
GENDAC

Absolute Maximum Ratings
Power Supply Voltage .................................................. 7 V

DC Digital Output Current .................................... 25 rnA

Voltage on any other pin ...... GND- O.5V to VDD + O.5V

Analog Output Current ......................................... .45 rnA

Temperature under bias .......................... - 40° C to 85° C

Reference Current .................................................. -15 rnA

Storage Temperature ............................. - 65° C to 150° C

Power Dissipation ..................................................... 1.0 W

Note

Stresses above those hsted under Absolute Max1mum Ratmgs may cause permanent damage to the dev1ce. Th1s 1S a stress ratmg only and
functional operatIon of the device at these or any other condItIons above those mdIcated in the operational sectIons of this speclflcatlOn
15 not imphed. Exposure to absolute maX1mum rahng conditions for extended penods may affect dev1ce reliabihty.

Electrical Characteristics
Symbol

Parameter

Conditions

Min

Max

Units

5.25

1.35

V
V
V
rnA
V

VDD = max,
GND ~ VIN ~ VDD
VDD = max,
GND ~ VIN ~ VDD

±1O

IlA

±50

IlA

10= max,

250

rnA

50

rnA
V
V
ns

DC CHARACTERISTICS (note: J)
VDD
VIH

lIN

Positive supply voltage
Input logic "1" voltage
Input logic "0" voltage
Reference current
Reference voltage
Digital input current

Ioz

Off-state digital output current

IDD

Average power supply current

VIL
IREF
VREF

4.75
2.0
-0.5
-7.0
1.10

VDD + 0.5
0.8

-10

Digital outputs unloaded

IDACOFF
VOH
VOL
ICLK r
ICLKf
FD

DACs in power down mode
No palette access
Output logic ''1''
10 = -3.2mA, note K
Output logic "0"
10 = -3.2mA, note K
Input Clock Rise Time
TTL levels
Input Clock Fall Time
TTL levels
Frequency Change of CLKO and
With respect to
CLK1 over supply and temperature
typical frequency

280

2.4
0.4
15
15
0.05

ns
%

ICS5300
GENDAC

•
Electrical Characteristics (continued)
Symbol

Parameter

Conditions

Min

Max

Units

DAC CHARACTERISTICS (note: J)
VO (max) Maximum output voltage
Maximum output current
Full scale error
DAC to DAC correlation

10 (max)

Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*

10 SlOmA

Vo SlV
note A, B

1.5
21

V
rnA

±5

%
%
LSB
LSB
ns
ns
ns
pVsec

±2
±0.5

note B
note B
note B
note C
note C
note C
note C

±l

28
20
6
200

* Charactenzed values only

Symbol

Parameter

Conditions

Min

Max

Units

25
25

135
135
1.5
1.5
60/40
130 ps

MHz
MHz
ns
ns

PLL AC CHARACTERISTICS

it

Clock 0 operating range
Clock 1 operating range

tr
tr
dt

Output clocks rise time
Output clocks fall time
Duty Cycle

hs
jabs
fref

Jitter, one sigma
Jitter, absolute
Input reference frequency

fO

25 pf load, TTL levels
25 pf load, TTL levels
40/60

Typically 14.318 MHz

281

-300 ps
5

300 ps
25

%
ps
ps
MHz

It

II

ICS5300
GENDAC

AC Electrical Characteristics (note: J)

Symbol
tCHCH
LltCHCH
t CLCH
t CHCL

t pVCH
t CHPX
t BVCH
tCHBX
tCHAV
LltCHAV
tWLWH
tRLRH
tSVWL
tSVRL
tWLSX
t RLSX
t DvwH
tWHDX
tRLQX

Parameter
PCLKperiod
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC output
Differential output delay
WR* pulse width low
RD* pulse width low
Register select setup time
Register select setup time
Register select hold time
Register select hold time
WR* data setup time
WR* data hold time

tWHRL3

Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write interval
WR* followed by read interval
Successive read interval
RD* followed by write interval
WR* after color write
RD* after color write
RD* after color read
WR* after color read
RD* after read address write

tSOD

SENSE* output delay

tRLQV
tRHQX
tRHQZ
tWHWLl
tWHRLl
tRHRLl
t RHWLl
tWHWL2
tWHRL2
tRHRL2
tRHWL2

Condition

80 MHz
Min
Max

110 MHz
Min
Max

135 MHz
Min Max Units

12.5

9.09

7.4

ns

3
3

ns
ns
ns
ns
ns
ns

±2.5

note D

5
5
note E
note E
note E

3.6
3.6
3

3
3
3
3

note E
noteF
note G

+2.5

3

2

50
50
10

Write cycle
Read cycle
Write cycle
Read cycle

20
2
50
50
10
10

10
10
10

10
5
5

note I
note I
note I

8 (tCHcH
8 (tCHCH
8 (tCHCH

~ (tCHCH

~ (tCHCH

4 (tCHCH

20

20
4 (tCHCH

8 (tCHCH)
8 (tCHCH )
8 (tCHCH)

1

40
5

4 (tCHCH)
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )

~ (tCHCH
4 (tCHCH

282

5

5
20

.~ (t CHCH

10

40

1

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

10

5
40

20
2
50
50
10
10
10
10

10
10
10
10

10

noteH
note I
note I
note I
note I
note I
note I

2
1
2
1

2

20
2

%

ns
ns
ns

4 (tCHCH
4 (tCHCH
4 (tCHCH
4 (tCHCH
4 (tCHCH
8 (tCHCH
8 (tCHCH
8 (tCHCH

cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

1

Il s

ICS5300
GENDAC

•
General Operation

NOTES
A

Full scale error IS denved from desIgn equatIOn
{[(F S lOUT) R, - 21 (IREF) R,]/12 ](IRcr)R,lIIOO%

VBLACK LEVEL =OV F.5 lOUT = Actual full scale measured output
B

R= 37 5Q, 'REF = - 8 88mA

C

ZI = 37 5Q + 30 pF, '1m = - 8.88mA

o

ThIs parameter IS the allowed PIxel Clock frequency vanahon It
does not permIt the PIxel Clock penod to vary outsIde themlmmum
values for PIxel Clock (tCHCHl penod

E

It IS reqUIred that the color palette's pIxel address be a valId logIc
level wIth the appropnate setup and hold hmes at each nsmg edge
of P eLK (thIS reqUIrement Includes the blankIng penod)

F

The output delay 15 measured from the 50% pOInt of the nSIng edge
of CLOCK to the valId analog output A valId analog output IS
defmed when the analog sIgnal IS halfway between Its succeSSIve

values.

G.
H

ThIS applIes to dIfferent analog outputs on the same devIce
Measured at ± 200 m V from steady state output voltage
ThIS parameter allows synchromzatIon between operatIons on the
mIcroprocessor Interface and the pIxel stream being processed by
the color palette

].

The follOWIng speCIfIcatIOns apply for VDD = +5V± 0 5V, GND=O
OperatIng Temperature = O°C to 70 c C

K.

Except for SENSE pm.

AC Test Conditions
Input pulse levels ................................................. VDD to 3V
Input rise and fall times (10% to 90%) .......................... 3ns
Digital input timing reference level... ........................ 1.5V
Digital output timing reference level... ..... O.8V and 2.4V

Capacitance
C 1 Digital input.. ............................................................. 7pF
Co Digital output. ........................................................... 7pF
C OA Analogoutput... .................................................... 10pF
2000

1.4V

I/O~
50 pF (including scope and jig)

I
DIGITAL OUTPUT LOAD

The ICS5300 GENDAC is intended for use as the analog
output stage of raster scan video systems. It contains a
high-speed Random Access Memory of 256 x 18-bit words,
three 618-bit high-speed DACs,a microprocessor I graphic
controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 39 of the ICS5300. This signal acts on all three of the
analog outputs. The BLANK* signal is delayed internally
so that it appears with the correct relationship to the pixel
bit stream at the analog outputs.
A pixel word mask is included to allow the incoming
pixel address to be masked. This permits rapid changes to
the effective contents ofthe color palette RAM to facilitate
such operations as animation and flashing objects.
Operations on the contents of the mask register can also
be totally asynchronous to the pixel stream.
The ICS5300 also includes dual PLL frequency generators
providing a video clock (CLKO) and a memory clock
(CLKl), both generated from a single 14.318 MHz crystal.
There are eight selectable CLKO frequencies of which six
are programmable, and a single programmable CLKI
frequency. Default values (Table 1 and Table 2) are
loaded into the appropriate registers on power up.

Video Path
The GENDAC supports four different video modes and
is determined by bits 5-7 of the command register. The
default mode is the 6-bit Pseudo Color mode. The other
modes are the bypass IS-bit, 16-bit and 24 bit True Color.

Pseudo color
In this mode, Pixel Address and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding rising edges of the clock. The DAC outputs depends
on the data in the color palette RAM.

283

II

ICS5300
GENDAC

Bypass Modes
The GENDAC supports three different bypass modes; 15bit (5,5,5) mode, 16-bit (5,6,5) mode and the 24-bit True
Color 8-bit DAC mode. In these modes, the pixel address
pins PO-P7 represent the Color Data that is applied directly to the DAC. The internal RAM is bypassed. In the
15/16-bit mode two consecutive bytes contain the 15/16
bits of color data. Two consecutive rising edges of the
PCLK latch the data on the PO-P7 pins into registers and
the byte framing is internally synchronized with the
rising edge ofBLANK*. The internal pipe line delay from
the "first byte" to the DAC is four PCLK rising edges. In
the 24-bit True Color mode, three bytes contains the 24-bit
color data. Three consecutive rising edges of the PCLK
latch the data. The framing is the same as the 15/16-bit
mode. The internal pipe line delay from the "first byte" to
the DAC is five PCLK rising edges.

DAC Outputs
The outputs of the DACs are designed to be capable of
producing 0.7 volt peak white amplitude with an IREF of
8.88 rnA when driving a doubly terminated 75Q load.
This corresponds to an effective DAC output load
(REFFECTIVE) of 37.5Q.
The formula for calculating IREF with various peak white
voltage/output loading combinations is given below:
VpEAKWHlTE

2.1

X REFFECTIVE

Note that for all values of IREF and output loading:
V BLACK LEVEL = 0
The reference current IREF is determined by the reference
voltage V REF and the value of the resistor connected to
RsET pin. VREF can be the internal band gap reference
voltage or can be overridden by an external voltage. In
both cases IREF =VREF/RsET .

lOUT

lf1
1

~

REFF

_I
28
V REF
(EXT)

"sET

Figure 4 - DAC Set up
The BLANK* inputto the GENDAC acts on all three ofthe
DAC outputs. When the BLANK" input is low, the DACs
are powered down.
The connection between the DAC outputs of the ICS5300
and the RGB inputs of the monitor should be regarded as
a transmission line. Impedance changes along the transmission line will result in the reflection of part of the video
signal back along the transmission line. These reflections
may result in a degradation of the picture displayed by
the monitor.
RF techniques should be observed to ensure good fidel-

ity. The PCB trace connecting the GENDAC to the offboard connector should be sized to form a transmission
line of the correct impedance. Correctly matched RF
connectors should be used for connection from the PCB to
the coaxial cable leading to the monitor and from the
cable to the monitor.
There are two recommended methods of DAC termination: double termination and buffered signal. Each is
described below with its relative merits:
Double Termination (Figure 1)
For this termination scheme, a load resistor is placed at
both the DAC output and the monitor input. The resistor
values should be equal to the characteristic impedance of
the line. Double termination of the DAC output allows
both ends of the transmission line between the DAC
outputs and the monitor inputs to be correctly matched.
The result should be an ideal reflection free system. This
arrangement is relatively tolerant to variations in
transmission line impedance (e.g. a mismatched
connector) since no reflections occur from either end of
the line.

284

ICS5300
GENDAC

•
A doubly terminated DAC output will rise faster than any
singly terminated output because the rise time of the
DAC outputs is dependent on the RC time constant of the
load.

}-

ICS5300

MONITOR
R LOAD

R LOAD
GND

I

I

Buffered Signal (Figure 2)
If theGENDAC drives large capacitive loads (for instance
long cable runs), it may be necessary to buffer the DAC
?utputs. The buffer will have a relatively high input
Impedance. The connection between the DAC outputs
and the buffer inputs should also be considered as a
transmission line. The buffer output will have a relatively
low impedance. It should be matched to the transmission
line between it and the monitor with a series terminating
resistor. The transmission line should be terminated at
the monitor.

GND

J

v

Rs

R LOAD

"\--

The ICS5300 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK1)
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop filters, minimizing board component
count.

GND

Figure 1 - Double Termination

ICS5300

PLL Clock

There are eight possible video clock, CLKO, frequencies
(£0-£7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bit in the PLL
control register. Two of these frequencies (fO-£1) are fixed
and the other six (f2-£7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL parameter registers. The default frequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There is only a single programmable memory clock
frequency (CLKl ). On power up this frequency defaults
to the frequency given in table 2. The memory clock
transition between frequencies is smooth and glitch free
if the transition is kept between the limits 45-65 MHz.

fn

(MHz)

fO
£1

25.175
28.322

f2
f3
f4
f5

31.500
36.00
40.00
44.889

f6

65.00

f7

75.00

VLCK
Comments

MONITOR

RT
GND

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF =1.23 Volts. When
the voltage on any of these pins go higher than the
reference voltage to the comparators, the SENSE* pin is
driven low. This signalis used to detectthetype of (or lack
of) monitor connected to the system.

285

VGAO (VGA Color monitor) (fixed)
VGAl (VGA Monochrome monitor)
(fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768 @ 70 Hz,
True Color 640 x 480 (programmable)

Table 1- Video clock (CLKO) default frequency
register (with a 14.318 MHz input)

ICS5300
GENDAC

•
fn

Comments

MHz

fA

45.00 MHz Memory and CUI subsystem clock

Table 2 - Memory Clock (CLK!) default frequency
register

Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5300, and the register addresses through
which they can be accessed.

RS2

RSI

RSO

a
a
a
a

0

a

1

1
1

0

1
1
1
1
O/HF

1

a

0
0

0

1
1
1

a

1

1

a

Register Name
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
Command
PLL Address (read mode)
Command Register
accessed by (hidden) flag after
special sequence of events

Writing to the color palette RAM
To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.
Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.
Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the CENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

286

ICS5300
GENDAC

•
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is reset for Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5300 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5300. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. At the end of the second Read, the address
location is automatically incremented. The address register (OE) is incremented after the first byte Read.

Power Down Mode
When bit 0 in the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Power Supply
As a high speed CMOS device, the ICS5300 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 29.
To supply the transient currents required by the ICS5300,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended that the decoupling capacitance
between VDD and GND should be a 0.1 f1F high frequency
capacitor, in parallel with a large tantalum capacitor with

287

I

ICS5300
GENDAC

•
a value between 22~F and 47~F. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EM!.
The combination of series impedance in the ground supply
to the GENDAc. and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the
GENDAC behave like low impedance transmission lines
driven from a low impedance transmission source and
terminated with a high impedance. In accordance with
transmission line principles, signal transitions will be
reflected from the high impedance input to the device.
Similarly, signal transitions will be inverted and reflected
from the low impedance TTL output. Line termination is
recommended to reduce or eliminate the ringing, particularly the undershoot caused by reflections. The termination may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of

using fewer components. Series termination is accomplished by placing a resistor in series with the signal at the
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around 1000 will be
required. Since each design will result in a different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

288

ICS5300
GENDAC

II
Functional Description

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/stop control. The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Bit 0

This section describes the register address and bit definition for RAMDAC and the Frequency Synthesizer sections.

Color Palette
Command Register
= 011)

(RSO-RS2
(RSO-RS1

=01 with hidden flag)

By setting bits in the command register the ICSS300 can be
programmed for different color modes and can be powered down for low power operation.
7
6
S
Color Mode
2
1
0

3
2
1
Reserved
Should all =0

4

The four selectable color modes are described here.
Mode 0: 8-bit Pseudo Color (one clock per pixel). This
mode is the 8-bit per pixel Pseudo Color mode. In this
mode. inputs PO-P7 are the pixel address for the color
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is
selected by setting bits CR7-CRS to 000. There are three
clock cycles pipe line delays from input to DAC output.

0
Snooze

Table 3 - Command Registers
Bit 7-5

Color Modes

Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

8-bit Pseudo Color mode

Bit 4 - 1 (Reserved)

7

6

S

DATA BYTE
4
3
2

o

7

6

S

PIXEL ACCESS
4
3
2

o

CM2
(CR7)

CMl
(CR6)

CMO
(CR5)

0
0
0
0

0
0
1
1

0
1
0
1

6-Bit Pseudo Color with Palette (Default)
IS-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
16-Dit Direct Color with Bypass (XGA)

1
2
3
2

0

a

IS-Bit Direct Color with Bypass (Hi-Color)
IS-Bit Direct Color with Bypass (Hi-Color)
I6-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

2
2
2
3

1
1
1
1

a
1
1

1

a
1

Clock Cycles!
Pixel Bits

Color Mode

Table 4 - Color Mode Select

289

ICS5300
GENDAC

•
Mode 1: (IS-bit per color bypassHi-Color mode).
This mode is the IS-bit per pixel bypass mode. In this
mode, inputs PO-P7 are the color DATA and are input
directly to the DAC, bypassing the color palette. The two
bytes of data is latched in two successive PCLK rising
edges. ICS5300 supports only the two clock mode and
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the 15/
16 one clock modes are selected as two clock modes in this
chip. The low-byte, high byte synchronization is internally
done by the rising edge of BLANK*. Each color is 5-bit
wide and is packed into two bytes as shown below. The
mode is selected by setting bits CR7-CR5 to 001, 100 or
101.

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
BLANK*. In this mode, each of the colors are 8-bit wide
and the DAC is an 8-bit wide DAC. The first byte is blue
followed by green and red. This mode can be selected by
setting bits CR7-CR5 to 010 or 111. The DAC outputs
changes every three cycles and the pipeline delay from
the first byte to output is five cycles.
24-bit color mode
THIRD BYTE

SECOND BYTE

FIRST BYTE

pppppppp pppppppp pppppppp

IS-Bit Color Mode
3LSB = set to zero

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 65432 1 0
7 6 543 210 765 432 1 0 7 6 5 4 3 2 1 0
RED
GREEN
BLUE

SECOND BYTE

FIRST BYTE
PPPPPPPP
7 6 5 432 1 0 7 6 5 4 3 2 1 0

pppppppp

xl7 6 5 413 7 6 5 4 317 6 543
RED
GREEN
BLUE
Mode 2: (16-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POP7 inputs to go to the DAC directly, bypassing the color
palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 6 bits wide and green is 5
bits wide. The 2 bytes of data is packed as shown below.
The mode is selected by setting bits CR7-CR5 to 011 or
110.

Frequency Generators
The ICS5300 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values to
the PLL Parameter Register Bank (table 5).

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed by register select pins
RS2-RSO = 100 or 111.
7

6 5 4 3 2 1 0
PLL REGISTER ADDRESS
7 6 5 4 3 2 1 0

16-Bit color mode
2LSB = set to zero (green)
3LSB = set to zero (blue, red)
SECOND BYTE

FIRST BYTE

pppppppp pppppppp

7 6 5 432 1 0 7 6 5 4 3 2 1 0
7 6 5 43176 5 43 217 6 5 4 3
RED
GREEN
BLUE

PLL Parameter Register
There are sixteen registers in the PLL parameter register
(table 5). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLK1 programmable frequency and register OE is the PLL CLKO control register.

290

ICS5300
GENDAC

•
Index

R!W

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/R/R/R/W
R/-

CLKO £0 PLL Parameters
CLKO f1 PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO f4 PLL Parameters
CLKO f5 PLL Parameters
CLKO f6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLKlfAPLL
(Reserved) = 0
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

PLL Data Registers
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(1-byte)
(2-byte)

The CLKO and CLKI input frequency is deternimed by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.
M-Byte PLL Parameter Input
The M -byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
7
6
Reserved
=0
X

X

X

X

X

X

x

N-Byte PLL Parameter Input
The N-byte has two values. Nl sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2,4, or 8 post divide clock output.

Table 5 - PLL Parameter Registers

7
5
6
Reserved N2-Code
X X
=0

PLL Control Register
Bits in this register determine internal or external CLKO
select.
7

N2code
00
01
10
11

Enable Internal Clock Select ONCS) for CLKO.
When this bit is set to 1, the CLKO output
frequency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4 - 3 (Reserved).
Bit 2 - 0 Internal Clock Select for CLKO ONCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects £0.

4

X

3
2
1
0
Nl-Divider Value

X

X

X

X

N2 Post Divide Code

Bit 7 - 6 Reserved.
Bit 5

o

543
2
1
M-Divider Value

Divider
1
2
4
8

The block diagram of the PLL clock synthesizer is given
in following figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
(M+2) x Fref
Fout ~----=
(Nl+2) X2 N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the following page for programming example.

291

I!!
iii

ICS5300
GENDAC

•
3. 60 MHz.::; (M+2) fREF .::; 270 MHz
(N1+2)

Programming Example
Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower jitter
at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output
divides, which tends to improve the duty cycle.

From the table on page 17, we find N2 = 2
Substituting F,d = 14.318 and 2N2 = 4 into the equation on
page 17:

4. fClKO and fClK! .::; 135 MHz
This is the output frequency.

( 22.175).4= (M+2)
14.318
(N1 + 2)

These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

by trial and error:
A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition
N2* fClK .::; 270 MHz

( 25.175) 4 ~ 127
14.318
18
so

M + 2 = 127
Nl + 2 = 18

M=125
N1 = 16

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0
N=01010000b

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz

This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the crystal
inputs, so this is not a problem.
2. 600 kHz < fREF .::; 8 MHz
(N1+2)
This is the frequency input to the phase detector.

B. Calculate

(M2+)
(N1+2)

=

2N2f out
fref

C. Now (M+2) and (N1+2) must be found by trial and
error. With a 14.318 MHz reference frequency, there will
generally be a small output frequency error due to the
resolution limit of (M+2) and (N1+2). For a given frequency tolerance, several different (M+2) and (N1+2)
combinations can usually be found. Usually, a few
minutes trying out numbers with a calculator will produce a workable combination. Multiplying possible
values of (N1 +2) by the desiredratio will indicate approximately the value of M. This method is shown in the
example below. A program could be written to try all
possible combinations of (M+2) and (N1 +2) (3937 possible combinations), discard those outside error band
and select from those remaining by giving preference t~
ratios which use lower values of (M+2). Lower values of
(M+2) and (N1 +2) provide better noise rejection in the
phase locked loop.
Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

292

ICS5300
GENDAC

•
A. 66*8 = 528 > 250 veo speed too high
66*4 = 264 > 250 veo speed too high
66*2 = 132 < :!5~ veo speed OK, N2 = 2, N2 code =
01 from table on page 17 of the data sheet.

B.

132/14.31818 = 9.219
This is the desired frequency multiplication ratio.

C. Setting (Nl+2) = 3,4,. .. 12,13 and performing some
simple calculations yields the following table:
(Note that Nl cannot be 0)

(Nl+2)

(Nl +2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
g.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.

We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

I Fou~
r-

Figure 3 - PLL Clock Synthesizer Block Diagram

eS2
0
0
0
0
1
1
1
1

External Select
CSI
0
0
1
1
0
0
1
1

(Internal Select PLL Control Register)
eso
BIT 2
BIT 1
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
Video Clock Selection Table

293

BIT 0
0
1
0
1
0
1
0
1

eLK 0 Frequency
fO
f1
f2
f3
f4
f5
f6
f7

ICS5300
GENDAC

•
PLCK

PooP?

BLANK*

DUU\ \ 0 / / U U U U U U
)-- A~B~

RED

L-__________________~

GREEN

L-_________________~

)--A~

B

~

C

""""\

~B~NK--B~NK~

F~G~

r-F ____ G~

C~B~NK--B~NK...J

BLUE

System Timing - Pseudo Color, Mode 0

PLCK

Poop?

BLANK*

c

RED

C~BLANK---BLANK~

GREEN

BLUE

~BLANK---BLANKJ

-A~B

C

LBLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

294

ICS5300
GENDAC

•
PCLK

BLANK

PO-P7

~___ A____~~B-DAC-RD

DAC-GR
DAC-BL

~A~B_

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-J

___________________________________________

~A____~~B~-J

System Timing Bypass - 15 (5/5/5) and 16 (5/6/5) Modes 1, 2

25n5

100n5

DAC-BL ____________________________~/
DAC-GR

125n5

150n5

"'-______~r

-----------~----~--~~

DAC-RD ____________________________~/~----,A.----''------nB------'r-C-

System Timing Bypass True Color 24 (8,8,8) Mode 3

295

ICS5300
GENDAC

I--tWLWH--

WR*

RSO-RS1

DO-D7

t SVWL

I

I

I

I

Jt

WLSX

I

"I

I
t DVW:I

I

I

"I

ItWHDX

I

I

Basic Write Cycle Timing

RD*

RSO-RS1

DO-D7

Basic Read Cycle Timing

t WHWL1 f---~

WR*

RD*

RSO

RS1

0

0

Write to Pixel Mask Register Followed by Write

WR*

Write to Pixel Mask Register Followed by Read

-\~'"~rt=

t RHRL1 f----I

RD*

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

296

ICS5300
GENDAC

II
WR*

\~"

C

' ••• 0

RO*

RSO

RS1

RS2

00-07

\

7
7

\
\

/

\

/

V

\

V
~
~

C

ADDRESS 't--------\ADDRESS +1 ) } - - - - - - - - - - - - - -

\--1" "=tWHRL3

WR*

RO*

~----------------

/

RSO

\

/

RS1
RS2

00-07

~

ADDRESS ';-----\ ADDRESS } } - - - - - - - - - - - - - -

Write and Read Back Pixel Address Register (Write Mode)

WR*

RO*

RSO

RS1
RS2

~"

,. ""lAAFLJ----

/

L_~~~~L

/
\

\
\ c-=\ c-=\ /
c-=\ c-=\ c-=\ /

7 \'----_-----'
7 \~_---J

00-07

Read Color Value then Pixel Address Register (Read Mode)

297

__

ICS5300
GENDAC

II
WR*

-LJ-"
,_. LJ ,_. U ,_.

"~

'-1- ,~"' -L

RD*

RSO

~

/

RS1

~

RS2

~

7

\

7

\

7

\

~

L

\

L

\

L

x:::=xJ
x:::=xJ

/

L

\

L

\

L

x:::=xJ

\

ADDRESS

DO-D7

~

RED

GREEN

BLUE

Color Value Write followed by any Read

WR*~'

IWHWL1

U

.-

-.

IWHWL1

U' U

0-

-0

IWHWL1

.-

-0

:WHWL2

L

.-

RD*

RSO

~

L

/

\

/

\

7

'\

CJCJ

RS1

~

L

\

L

\

L

\

L

CJCJ

~

L

\

L

\

L

\

L

CJCJ

RS2

DO-D7

ADDRESS

RED

GREEN

Color Value Write followed by any Write

298

BLUE

ICS5300
GENDAC

•
WR*

y,

t RHRL1

t WHRL3

t AHRL2

t AHRL1

'U' 'U' 'U' 'L

RO*

RSO

V

\

7

\

7

\

7

\

RS1

V

\

~

/

~

L

~

/

~

L

~

L

\

L

\

L

RS2

00-07

ADDRESS

BLUE

GREEN

RED

x=::=o
x=::=o
x=::=o

Color Value Read followed by any Read

WR*

~,

t WHRL3

RO*

·U 'U' ·u·,-Jt RHRL1

t RHRL1

RSO

V

\

7

\

7

\

7

\

RS1

V

\

~

~

L

~

L

~

L
L

~

RS2

L
L

\

L

00-07

ADDRESS

\
RED

GREEN

Color Value Read followed by any Write

299

BLUE

x=::=o
x=::=o
x=::=o

ICS5300
GENDAC

II
WR*

RD*

RSO

\

/

RS1

/

RS2

v

DO-D7

- - - - \ ADDRESS!-----<. ADDRESS ) } - - - - - - - - - - - - - - - -

\,--_~7

Write and Read back PLL Address Register (Write Mode)

WR*

~-~.

RD*

t WHRL3

'L

V

\

7

\

RS2

V

\

7

\

DO-D7

- - - - \ ADDRESS !-----<. ADDRESS ) } - - - - - - - - - - - - - - - -

RSO

RS1

Write and Read back PLL Address Register (Read Mode)

300

ICS5300
GENDAC

•
WR*

I

RO*

RSO

RS1

RS2

u
u

\

\

u

00-07 _---{

PLL ADDRESS

Read Two bytes PLL Register then PLL Address Register

WR*

RO'

RSO

LJ \

/

~

~

RS1

LJ \
LJ \

\

~

~

/

~

----<.

~

RS2

00-07

ADDRESS

Read One Byte PLL Register then PLL Address Register

301

ICS5300
GENDAC

The ground plane is continuous, but the power plane is separated into analog and digital sections as shown. Power is
supplied to the analog power plane through the ferrite bead,
and bypassed at the power entry point by C3, a 10 J.1F tantalum
capacitor. These high current connections should have multiple vias to the ground and power planes, if possible. Power
connections should be connected to the analog or digital power
plane, as shown in the diagram. Power pins 5 and 29 should be
connected to digital power, power pins 20 and 24 to analog
power. Decoupling capacitors (indicated by Cl) should be
placed as close to the GENDAC as possible.

Monitor SENSE Signal
RED,
GREEN,
BLUE

/
335V

/
'soD

SENSE

'-

The analog and digital I/O lines are not shown. Analog signals
(DAC outputs, Vref, Rset) should only be routed above the
analog power plane. Digital signals should only be routed
above the digital power plane.

The high performance of which the ICS5300 GENDAC is
capable is dependent on careful PC board layout. The use of
a four layer board (internal power and ground planes, signals
on the two surface layers) is recommended. The layout below
shows a suggested configuration.

Recommended Layout

Cl

DIGITAL Power
Plane

Cl
+

Yl

100 mil Separation

40
41
42

c::::JoOCJ
Cl

0

+

0_

0+
C1
C2
C3

FBI
R1

Y1

Cl

43
44
1
2
3
4
5

ICS5300
Analog Power
Plane Island

6

VIA to ground plane
VIA to power plane
,01 uf chip capacitor
,1uf chip capacitor
10uf tantulum capacitor
Ferrite Bead
140 ohm 1% resistor
14.318 Mhz parallel resonant crysal cut for C L=12

302

C2

C3

ICS5301
GENDAC

Integrated
Circuit
Systems, Inc.

•

8-Bit Integrated Clock-LUT-DAC
General Description

Features

The rCS5301 GENDAC is a combination of dual programmable clock generators, a 256 x IS-bit RAM, and a triple
S-bit video DAC. The GENDAC supports S-bit pseudo
color applications, as well as IS-bit, 16-bit and 24-bit True
Color bypass for high speed, direct access to the DACs.

• Designed for compatibility with Tseng Labs VGA
controllers
• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)
• One programmable memory (controlled clock
frequency (CLKl)

The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains S frequencies, 6 of
which are programmable by the user. The memory clock
has one programmable frequency location.
The three S-bit DACs on the ICS5301 are capable of
driving singly or doubly-terminated 75Q loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
rcs is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

•
•
•
•
•
•

DAC power down in blanking mode
Low power operation
Anti-sparkle circuitry
On-chip loop filters reduce external components
Standard CPU interface
Single external crystal (typically 14.318 MHz)

• Monitor Sense
• Internal voltage reference
• 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1)
versions
• Very low clock jitter

Block Diagram

SENSE'

PO-P7
MUX

COLOR

PALETTE
256 X 18 BIT

RED
GREEN
BLUE

L....,-~---RESET

18

NORM

VREF

~PCLK
~~

00-07

~----------------------------------------~CLKO

~-----------------------------------------'CLKI

303

ICS5301
GENDAC

•
*
otJlo

,....,0[-<

~~(il~UlUl&5~~B~
UCflUUUUUU><><

Pin Configuration

\oL!")'1'<'lN,....,~~~:;;~

RD*
DO
D1
D2
D3
D4
D5
D6
D7
RSO
RSI

7
8
9
10
11
12
13
14
15
16
17~

GENDAC I

ICS5301

O\O~NC'1"J-.::t"L!)I..Ot--...OO
~NNNNNNNNN

39
38
37
36
35
34
33
32
31
30
29

BLANK*
PCLK
P7
P6
P5
P4
P3
P2
PI
PO
DVDD

Pin Description (68 pin PLCC)
Symbol

Pin #

Type

Description

CSI

1

Input

CS2

2

Input

CGND
SENSE'

3
4

Output

CVDD
WR*

5
6

Input

RD*

7

Input

8 -15

I/O

Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Ground for clock circuits. Connect to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
Clock Power Supply. Connect to DVDD
RAM/PLL Write Enable, active low. This signal controls the timing ofthe
write operation on the microprocessor interface inputs, DO-D7.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.

DO-D7

-

-

304

ICS5301
GENDAC

•
Pin Description (continued)
Symbol

Pin #

Type

RSO
RSI
RS2
CGND
CVDD
RED
GREEN
BLUE

16
17
18
19
20
21
22
23

Input
Input
Input

Output
Output
Output

AVDD
RSET

24
25

Input

AGND
DGND
VREF

26
27
28

Input

DVDD
PO-P7

29
30 - 37

Input

PCLK

38

Input

BLANK*

39

Input

XIN
XOUT
CLKO

40
41
42

Input
Output
Output

CLKI
CSO

43
44

Output
Input

-

-

-

Description
Register Address Select O. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Ground for clock circuits. Connect to ground.
Clock Power Supply. Connect to AVDD.
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value. These
outputs are typically used to drive a CRT monitor.
Analog power supply. Connect to AVDD.
Resistor Set. This pin is used to set the current level in the analog outputs.
It is usually connected throllKh a 140[.1, 1 % resistor to ground.
Analog Ground. Connect to ground.
Digital Ground. Connect to ground.
Internal Reference Voltage. Normally connects to a O.I~F cap to
ground. To use an external Vref, connect a 1.235V reference to this pin.
Digital power supply.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be grounded if they are not used.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK* inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC, and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette mav still be updated through DO-D7 during blanking.
Crystal irl!,ut. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
Memory clock output. Used to time the video memory.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.

305

ICS5301
GENDAC

Internal Registers
RS2 RSl

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENOAC. This register
can be accessed through either register address 0,0,0 or register address
0,1,1. A read from address 0,0,0 is identical to a read from address O,I,I.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.
0

0

0

Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
color values to the color palette RAM.

0

1

1

Pixel Address
READ

Writing to this 8-bit register is performed prior to reading one or more
color values from the color palette RAM.

0

0

1

Color Value

The 18-bit Color Value register acts as a buffer between the microprocessor
interface and the color palette. Using a three bytes transfer sequence allows
a value to be read from or written to this register. When a byte is read, the
color value is contained in the least significant 6 bits, DO-OS (the most
significant 2 bits are set to zero). When writing a byte, the same 6 bits are
used. When reading or writing, data is transferred in the same order - the
red byte first, then green, then blue. Each transfer between the Color Value
register and the color palette replaces the normal pixel mapping operations
of the GENOAC for a single pixel.
After writing three definitions to this register, its contents are written to the
location in the color palette RAM specified by the Pixel Address register,
and the Pixel Address register increments.
After reading three definitions from this register, the contents of the location
in the color palette RAM specified by the Pixel Address registers are copied
into the Color Value register, and the Pixel Address register increments.

0

1

0

Pixel Mask

The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
position in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask register
does not affect the Pixel Address generated by the microprocessor interface
when the palette RAM is being accessed.

306

ICS5301
GENDAC

•
Internal Registers (continued)
RS2

RSI

RSO

Register
Name

1

0

0

PLLAddress
WRITE

Writing to this 8-bit register is performed prior to writing one or more
PLL programming values to the PLL Parameter register.

1

1

1

PLLAddress
READ

Writing to this 8-bit register is performed prior to reading one or more
PLL programming values from the PLL Parameter register.

1

1

0

Command

This 8-bitregister selects the color mode, for instance 8-bit Pseudo Color, HiColor, True Color, or XGA, and DAC power down. The registers are reset
to pseudo color mode on power up.

1

0

1

PLL
Parameter

There are sixteen parameter registers as indexed by PLL Address Write/
Readregisters. Parameter registers 00-00 and OF are two bytes long and OE
is one byte long. This register set contains one control register. The bits of this
register include clock select and enable functions, the rest contain PLL
frequency parameters. After writing the start index address in the PLL
address register, these registers can be accessed in successive two (or one)
bytes. The address register auto increments after one or two bytes to access
the entire register set.

Description
(all registers can be written to and read from)

307

ICS5301
GENDAC

Absolute Maximum Ratings
Power Supply Voltage .................................................. 7 V

DC Digital Output Current .................................... 25 rnA

Voltage on any other pin ...... GND- O.5V to Voo + O.5V

Analog Output Current ......................................... .45 rnA

Temperature under bias .......................... - 40° C to 85° C

Reference Current .................................................. -15 rnA

Storage Temperature ............................. - 65° C to 150° C

Power Dissipation ..................................................... 1.0 W

Note:

Stresses above those hsted under Absolute Maximum Ratings may cause permanent damage to the deVice. Ths IS a stress ratmg only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
IS not 1ffiphed. Exposure to absolute maximum ratmg conditions for extended periods may affect device rehabihty.

Electrical Characteristics
Symbol

Parameter

Max

Units

5.25
Voo +0.5
0.8
-10
1.35
±1O

V
V
V
rnA
V

Voo = max,
GND::; VIN ::; Voo

±50

~

10 = max,

250

rnA

50
0.4
15
15

mA
V
V
ns
ns

0.05

%

Conditions

Min

DC CHARACTERISTICS (note: J)

lREF
VREF
lIN

Positive supply voltage
Input logic "1" voltage
Input logic "0" voltage
Reference current
Reference voltage
Digital input current

loz

Off-state digital output current

100

Average power supply current

Voo
VIH
VIL

4.75
2.0
-0.5
-7.0
1.10
Voo = max,
GND::;VIN::;Voo

~

Digital outputs unloaded

IOACOFF
VOH
VOL
ICLK.
ICLKf
FD

DACs in power down mode
No palette access
Output logic "1"
10 =-3.2mA, note K
Output logic "0"
10 =-3.2rnA, note K
Input Clock Rise Time
TTL levels
Input Clock Fall Time
TTL levels
Frequency Change of CLKO and
With respect to
CLKI over supply and temperature typical frequency

308

2.4

ICS5301
GENDAC

•
Electrical Characteristics (continued)
Symbol

Parameter

Conditions

Min

Max

Units

DAC CHARACTERISTICS (note: J)
Vo(max) Maximum output voltage
Maximum output current
Full scale error
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*

10 (max)

1.5
21

10 :s; lOrnA

Vo :S;lV
note A, B
note B
note B
note B
noteC
noteC
noteC
noteC

±5
±2

±0.5
±1

28
20
6
200

V
rnA
%
%
LSB
LSB
ns
ns
ns
pVsec

* Charactenzed values only

Symbol

Parameter

Conditions

Min

Max

Units

25
25

135
135
1.5
1.5
60/40
130 ps
300ps
25

MHz
MHz
ns
ns
%

PLL AC CHARACTERISTICS
fO

fJ
tr
tr
dt
hs
jabs
fref

Clock 0 operating range
Clock 1 operating range
Output clocks rise time
Output clocks fall time
Duty Cycle
Jitter, one sigma
Jitter, absolute
Input reference frequency

25 pf load, TTL levels
25 pf load, TTL levels
40/60

Typically 14.318 MHz

309

-300 ps
5

ps
ps
MHz

ICS5301
GENDAC

AC Electrical Characteristics (note: J)

Symbol
t CHCH
M CHCH
t CLCH
t CHCL
t pVCH
tCHPX
t BVCH
tCHBX
tCHAV
,MCHAV
t WLWH
tRLRH
tSVWL
tSVRL
tWLSX
tRLSX
t DvwH
tWHDX
tRLQX
tRLQV
tRHQX
tRHQZ
tWHWLl
tWHRLl
tRHRLl
tRHWLl
tWHWL2
tWHRL2
tRHRL2
tRHWL2
tWHRL3
tSOD

Parameter
PCLKperiod
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC output
Differential output delay
WR* pulse width low
RD* pulse width low
Register select setup time
Register select setup time
Register select hold time
Register select hold time
WR* data setup time
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write interval
WR* followed by read interval
Successive read interval
RD* followed by write interval
WR* after color write
RD* after color write
RD* after color read
WR* after color read
RD* after read address write

Condition

80 MHz
Min
Max

110 MHz
Min
Max

135 MHz
Min Max Units

12.5

9.09

7.4

±2.5

note D

note E
noteE
note E
note E
note F
noteG

+2.5

5
5

3.6
3.6

3

3

3

3
3

3

2
1
2
1

2
2

3

20
2

Write cycle
Read cycle
Write cycle
Read cycle

20
2

50
50
10
10
10
10

50
50
10
10

10

10

10

10

10

10

10

10

10
5

10

10

5

5

note I
note I
note I

5

14 (tCHCH)

14 (tCHCH )
14 (tCHCH )
14 (tCHCH )
14 (tCHCH )
4 (tCHCH )
8 (tCHCH)
8 (tCHCH )
8 (tCHCH)

1

310

ns
ns
ns
ns
ns
ns

5
40

20

SENSE* output delay

20
2
50
50
10

40
noteH
note I
note I
note, I
note I
note I
note I

3

40
5

20

ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

20

ns
ns
ns
ns

4 (tCHCH )
4 (tCHCH)
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )
4 (tCHCH)

4 (tCHCH)
4 (tCHCH)
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )

8 (tCHCH )
8 (tCHCH )
8 (tCHCH )

8 (tCHCH )
8 (tCHCH)
8 (tCHCH)

cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

1

I1s

1

ICS5301
GENDAC

•
General Operation

NOTES:

A.

Full scale error IS denved from desIgn equatIon
I[(F.S lOUT) RL - 2 1 (IREF) RLl/[21(1REF)RLlIlOO%
VBLACK LEVEL =OV F.5 lOUT = Actual full scale measured output

B.

R= 37.50, IREF = - 8 88mA

C.

Zr = 37.50 + 30 pF, IREF = - 8.88mA

D.

ThIs parameter 15 the allowed PIxel Clock frequency variatlOn It
does not permIt the PIxel Clock penod to vary outsIde the mInImUm
values for PIXel Clock (tCHCH ) penod

E

It 15 reqUlred that the color palette's pIxel address be a vahd logIc
level wIth the appropnate setup and hold llmes at each nSlng edge
of PeLK (thIS reqUlrement Includes the blanking penod)

F

The output delay 15 measured from the 50% point of the nSlng edge
of CLOCK to the vahd analog output A vahd analog output 15
defmed when the analog sIgnal 15 halfway between its successIve
values.

G.

ThIS applies to dIfferent analog outputs on the same devIce.

H.

Measured at ± 200 mV from steady state output voltage

I.

ThIS parameter allows synchrOniZatIOn between operatIons on the
mIcroprocessor interface and the pIxel stream being processed by
the color palette.

J.

The following spectiications apply for V 00= +5V± O.5V, GND=O
Operating Temperature = O°C to 70'C.

K.

Except for SENSE pin

AC Test Conditions
Input pulse levels ................................................. VDD to 3V
Input rise and fall times (10% to 90%) .......................... 3ns
Digital input timing reference level... ........................ 1.5V
Digital output timing reference level... ..... 0.8V and 2.4V

Capacitance
C 1 Digital input.. ............................................................. 7pF
Co Digital output... ......................................................... 7pF
C OA Analog output. ...................................................... l0pF
2000

The ICS5301 GENDAC is intended for use as the analog
output stage of raster scan video systems. It contains a
high-speed Random Access Memory of256 x 18-bitwords,
three6/8-bithigh-speed DACs, a microprocessor I graphic
controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 39 of the ICS5301. This signal acts on all three of the
analog outputs. The BLANK* signal is delayed internally
so that it appears with the correct relationship to the pixel
bit stream at the analog outputs.
A pixel word mask is included to allow the incoming
pixel address to be masked. This permits rapid changes to
the effective contents of the color palette RAM to facilitate
such operations as animation and flashing objects.
Operations on the contents of the mask register can also
be totally asynchronous to the pixel stream.
The ICS5301 also includes dual PLL frequency generators
providing a video clock (CLKO) and a memory clock
(CLKl), both generated from a single 14.318 MHz crystal.
There are eight selectable CLKO frequencies of which six
are programmable, and a single programmable CLKI
frequency. Default values (Table 1 and Table 2) are
loaded into the appropriate registers on power up.

Video Path
The GENDAC supports four different video modes and
is determined by bits 5-7 of the command register. The
default mode is the 6-bit Pseudo Color mode. The other
modes are the bypass IS-bit, 16-bit and 24 bit True Color.

Pseudo color

14V

1I0~
50 pF (including scope and jig)

I

In this mode, Pixel Address and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding rising edges of the clock. The DAC outputs depends
on the data in the color palette RAM.

DIGITAL OUTPUT LOAD

311

ICS5301
GENDAC

•
Bypass Modes
TheGENDAC supports three different bypass modes; 15bit (5,5,5) mode, 16-bit (5,6,5) mode and the 24-bit True
Color 8-bit DAC mode. In these modes, the pixel address
pins PO-P7 represent the Color Data that is applied directly to the DAC. The internal RAM is bypassed. In the
15/16-bit mode two consecutive bytes contain the 15/16
bits of color data. Two consecutive rising edges of the
PCLK latch the data on the PO-P7 pins into registers and
the byte framing is internally synchronized with the
rising edge of BLANK*. The internal pipe line delay from
the "first byte" to the DAC is four PCLK rising edges. In
the 24-bit True Color mode, three bytes contains the 24-bit
color data. Three consecutive rising edges of the PCLK
latch the data. The framing is the same as the 15/16-bit
mode. The internal pipe line delay from the "first byte" to
the DAC is five PCLK rising edges.

DAC Outputs
The outputs of the DACs are designed to be capable of
producing 0.7 volt peak white amplitude with an IREF of
8.88 mA when driving a doubly terminated 750 load.
This corresponds to an effective DAC output load
(REFFECTIVE) of 37.50.
The formula for calculating IREF with various peak white
voltage/output loading combinations is given below:
VpEAKWHITE
2.1

X

REFFECTIVE

Note that for all values of IREF and output loading:
VBLACK LEVEL = 0
The reference current IREF is determined by the reference
voltage VREF and the value of the resistor connected to
RsET pin. VREF can be the internal band gap reference
voltage or can be overridden by an external voltage. In
both cases IREF =VREF/RsET'

lOUT

I

qRm
~

~I
(EXT)

Figure 4 - DAC Set up

The BLANK*inputtotheGENDAC acts on all threeofthe
DAC outputs. When the BLANK* input is low, the DACs
are powered down.
The connection between the DAC outputs of the ICS5301
and the RGB inputs of the monitor should be regarded as
a transmission line. Impedance changes along the transmission line will result in the reflection of part of the video
signal back along the transmission line. These reflections
may result in a degradation of the picture displayed by
the monitor.
RF techniques should be observed to ensure good fidelity. The PCB trace connecting the GENDAC to the offboard connector should be sized to form a transmission
line of the correct impedance. Correctly matched RF
connectors should be used for connection from the PCB to
the coaxial cable leading to the monitor and from the
cable to the monitor.
There are two recommended methods of DAC termination: double termination and buffered signal. Each is
described below with its relative merits:
Double Termination (Figure 1)
For this termination scheme, a load resistor is placed at
both the DAC output and the monitor input. The resistor
values should be equal to the characteristic impedance of
the line. Double termination of the DAC output allows
both ends of the transmission line between the DAC
outputs and the monitor inputs to be correctly matched.
The result should be an ideal reflection free system. This
arrangement is relatively tolerant to variations in
transmission line impedance (e.g. a mismatched
connector) since no reflections occur from either end of
the line.

312

ICS5301
GENDAC

•
~doublyte~minatedDACoutputwilirisefasterthanany

smgly ternunated output because the rise time of the
DAC outputs is dependent on the RC time constant of the
load.

}-

ICSS300
GND

RLOAD

RWAD

1

MONITOR

[

GND

Figure 1 - Double Termination

Buffered Signal (Figure 2)
If the GENDAC drives large capacitive loads (for instance

long cable runs), it may be necessary to buffer the DAC
?utputs. The buffer will have a relatively high input
Impedance. The connection between the DAC outputs
and the buffer inputs should also be considered as a
tran~mission line. The buffer output will have a relatively
low Impedance. It should be matched to the transmission
lin~ between it and the monitor with a series terminating
resIstor. The transmission line should be terminated at
the monitor.

ICS5300
GND

1

rC>d
R LOAD

-

)-

PLL Clock
The ICS5301 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK1)
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop filters, minimizing board component
count.
There are eight possible video clock, CLKO, frequencies
(£O-f7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bit in the PLL
control register. Two of these frequencies (£0-£1) are fixed
and the other six (f2-f7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL pararneterregisters. The default frequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There is only a single programmable memory clock
frequency (CLK1 ). On power up this frequency defaults
to the frequency given in table 2. The memory clock
transition between frequencies is smooth and glitch free
if the transition is kept between the limits 45-65 MHz.

MONITOR

fn

(MHz)

£0
£1

50.350
56.644

f2
f3
f4
f5

31.500
36.00
40.00
44.889

f6

65.00

f7

75.00

RT
GND

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF =1.23 Volts. When
the voltage on any of these pins go higher than the
reference voltage to the comparators, the SENSE* pin is
driven low. This signalis used to detect the type of (or lack
of) monitor connected to the system.

313

VLCK
Comments

VGAO (VGA Color monitor) (fixed)
VGA1 (VGA Monochrome monitor)
(fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768 @ 70 Hz,
True Color 640 x 480 (programmable)

Table 1 - Video clock (CLKO) default frequency
register (with a 14.318 MHz input)

II

ICS5301
GENDAC

MCLK (fA)

Comments

45.00 MHz

Memory and GUI subsystem clock
Smooth transition between 45-65 MHz

Writing to the color palette RAM
To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.

Table 2 - Memory Clock (eLK1) Default Frequency
Register

Microprocessor Interface
Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.

Below are listed the six microprocessor interface registers
within the ICS5301, and the register addresses through
which they can be accessed.
RS2

RS1

RSO

0
0
0
0
1
1
1
1
O/HF

0
1
0
1
0
0
1
1
1

0
1
1

0
0
1
0
1
0

Register Name
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
Command
PLL Address (read mode)
Command Register
accessed by (hidden) flag after
special sequence of events

Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the GENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

314

ICS5301
GENDAC

•
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is reset for Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5301 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5301. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. At the end of the second Read, the address
location is automatically incremented. The address register (OE) is incremented after the first byte Read.

Power Down Mode
When bit 0 in the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Power Supply
As a high speed CMOS device, the ICS5301 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 29.
To supply the transient currents required by the ICS5301,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended thatthe decoupling capacitance
between VDD and GND should be a 0.1 JlF high frequency
capacitor, in parallel with a large tantalum capacitor with

315

I

ICS5301
GENDAC

•
a value between 221lF and 471lF. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EM!.
The combination of series impedance in the ground supply
to the GENDAC, and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the
GENDAC behave like low impedance transmission lines
driven from a low impedance transmission source and
terminated with a high impedance. In accordance with
transmission line principles, signal transitions will be
reflected from the high impedance input to the device.
Similarly, signal transitions will be inverted and reflected
from the low impedance TTL output. Line termination is
recommended to reduce or eliminate the ringing, particularly the undershoot caused by reflections. The termination may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of

using fewer components. Series termination is accomplished by placing a resistor in series with the signal at the
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around lOOn will be
required. Since each design will result in a different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

316

ICS5301
GENDAC

•
Functional Description

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/ stop control. The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Bit 0

This section describes the register address and bit definition for RAMDAC and the Frequency Synthesizer sections.

Color Palette
Command Register
(RSO-RS2 = 011)
(RSO-RS1 = 01 with hidden flag)

By setting bits in the command register the ICSS301 can be
programmed for different color modes and can be powered down for low power operation.
7
6
S
Color Mode
0
2
1

4

1
3
2
Reserved
Should all =0

0
Snooze

Table 3 - Command Registers
Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

Bit 7-5

Bit 4 - 1 (Reserved)

Color Modes
The four selectable color modes are described here.
Mode 0: 8-bit Pseudo Color (one clock per pixel). This
mode is the 8-bit per pixel Pseudo Color mode. In this
mode. inputs PO-P7 are the pixel address for the color
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is
selected by setting bits CR7-CRS to 000. There are three
clock cycles pipe line delays from input to DAC output.
8-bit Pseudo Color mode
DATA BYTE
7

6

S

7

6

S

2

1

o

PIXEL ACCESS
4
2
3

1

o

4

3

CM2
(CR7)

CMl
(CR6)

CMO
(CR5)

0
0
0
0

0
0
1
1

0
1
0
1

6-Bit Pseudo Color with Palette (Default)
1S-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
16-Bit Direct Color with Bypass (XGA)

1
2
3
2

1
1
1
1

0
0
1
1

0
1
0
1

IS-Bit Direct Color with Bypass (Hi-Color)
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

2
2
2
3

Clock Cycles!
Pixel Bits

Color Mode

Table 4 - Color Mode Select

317

ICS5301
GENDAC

•
Mode 1: (IS-bit per color bypassHi-Color mode).
This mode is the IS-bit per pixel bypass mode. In this
mode, inputs PO-P7 are the color DATA and are input
directly to the DAC, bypassing the color palette. The two
bytes of data is latched in two successive PCLK rising
edges. ICS5301 supports only the two clock mode and
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the 15/
16 one clock modes are selected as two clock modes in this
chip. The low-byte, high byte synchronization is internally
done by the rising edge of BLANK*. Each color is 5-bit
wide and is packed into two bytes as shown below. The
mode is selected by setting bits CR7-CR5 to 001, 100 or
101.
15-Bit Color Mode
3LSB = set to zero

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
BLANK*. In this mode, each of the colors are 8-bit wide
and the DAC is an 8-bit wide DAC. The first byte is blue
followed by green and red. This mode can be selected by
setting bits CR7-CR5 to 010 or 111. The DAC outputs
changes every three cycles and the pipeline delay from
the first byte to output is five cycles.
24-bit color mode
SECOND BYTE
THIRD BYTE
pppppppp pppppppp

7 6 543 2 1 a 7 6 5 4 3 2 1 a 765 432 1 a
76543 210 7 6 5 4 3 2 1 a 7 6 5 4 3 2 1 a
RED

FIRST BYTE
SECOND BYTE
pppppppp PPPPPPPP
7 6 5 4 3 2 1 a 7 6 5 4 3 2 1 a

xl7 6 5 413 76 5 4 317 6 5 4 3
RED

GREEN

BLUE

Mode 2: (16-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POP7 inputs to go to the DAC directly, bypassing the color
palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 6 bits wide and green is 5
bits wide. The 2 bytes of data is packed as shown below.
The mode is selected by setting bits CR7-CR5 to 011 or
110.

FIRST BYTE

PPPPPPPP

7 6 543 2 1 a 7 6 5 4 321 a
7 6 5 4 317 6 543 217 6 5 4 3
RED

GREEN

BLUE

GREEN

BLUE

Frequency Generators
The ICS5301 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values to
the PLL Parameter Register Bank (table 5).

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed by register select pins
RS2-RSO = 100 or 111.
6 5 4 3 2 1 0
PLL REGISTER ADDRESS
7 6 5 4 3 2 1 0
7

16-Bit color mode
2LSB = set to zero (green)
3LSB = set to zero (blue, red)
SECOND BYTE
pppppppp

FIRST BYTE

PPPPPPPP

PLL Parameter Register
There are sixteen registers in the PLL parameter register
(table 5). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLKI programmable frequency and register OE is the PLL CLKO control register.

318

ICS5301
GENDAC

•
Index

RIW

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/R/R/R/W
R/-

CLKO fO PLL Parameters
CLKO f1 PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO f4 PLL Parameters
CLKO f5 PLL Parameters
CLKO f6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLKlfAPLL
(Reserved) = 0
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

PLL Data Registers
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(1-byte)
(2-byte)

The CLKO and CLK1 input frequency is deternimed by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.
M-Byte PLL Parameter Input
TheM-byte has a 7-bitvalue (1-127) which is the feedback
divider of the PLL.
7
6
Reserved
=0
X

PLL Control Register
Bits in this register determine internal or external CLKO
select.

5

7
6
5
Reserved N2-Code
X
X
=0

o
X

Enable Internal Clock Select (INCS) for CLKO.
When this bit is set to 1, the CLKO output
frequency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4 - 3 (Reserved).
Bit 2 - 0 Internal Clock Select for CLKO (INCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects fO.

319

4

3
2
1
0
N1-Divider Value
X
X
X
X X

N2 Post Divide Code
N2code
00
01
10
11

Bit 7 - 6 Reserved.
Bit 5

4
2
3
M-Divider Value
X
X
X
X
X

N-Byte PLL Parameter Input
The N-byte has two values. N1 sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2, 4, or 8 post divide clock output.

Table 5 - PLL Parameter Registers

7

5

Divider
1

2
4
8

The block diagram of the PLL clock synthesizer is given
in following figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
(M+2) x Fref
Fout = - - - - (N1+2) X2 N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the following page for programming example.

ICS5301
GENDAC

II
Programming Example

3. 60 MHz

Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

~

(M+2) fREF
(Nl+2)

~

270 MHz

This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower jitter
at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output
divides, which tends to improve the duty cycle.

From the table on page 17, we find N2 = 2
Substituting F'el = 14.318 and 2N2 = 4 into the equation on
page 17:

4. fClKO and fClK! ~ 135 MHz
This is the output frequency.

( 25.175).4= (M + 2)
14.318
(N1 + 2)

These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

by trial and error:
( 25.175) 4 ~
14.318
so

A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition
N2* fCTK ~ 270 MHz

1R
18

M + 2 = 127
N1 + 2 = 18

M= 125
N1 = 16

B. Calculate

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & Nl = 0 & 1 0 & 1 0 0 0 0
N=01010000b

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz
This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the crystal
inputs, so this is not a problem.
2. 600 kHz < fREF ~ 8 MHz
(Nl+2)
This is the frequency input to the phase detector.

(M2+)
2N2f out
(N1 +2) =
fref

C. Now (M+2) and (Nl+2) must be found by trial and
error. With a 14.318 MHz reference frequency, there will
generally be a small output frequency error due to the
resolution limit of (M+2) and (Nl+2). For a given frequency tolerance, several different (M+2) and (Nl+2)
combinations can usually be found. Usually, a few
minutes trying out numbers with a calculator will produce a workable combination. Multiplying possible
values of (N1 +2) by the desiredratio will indicate approximately the value of M. This method is shown in the
example below. A program could be written to try all
possible combinations of (M+2) and (Nl +2) (3937 possible combinations), discard those outside error band,
and select from those remaining by giving preference to
ratios which use lower values of (M+2). Lower values of
(M +2) and (N1 +2) provide better noise rejection in the
phase locked loop.
Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

320

ICS5301
GENDAC

•

B. 132/14.31818 = 9.219
This is the desired frequency multiplication ratio.

A. 66*8 = 528 > 250 VCO speed too high
66*4 = 264 > 250 VCO speed too high
66*2 = 132 < 250 VCO speed OK, N2 = 2, N2 code =
01 from table on page 17 of the data sheet.

C. Setting (Nl+2) = 3,4, ... 12,13 and performing some

simple calculations yields the following table:
(Note that Nl cannot be 0)

(Nl+2)

(Nl+2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.

We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

I Fou~
r-

Figure 3 - PLL Clock Synthesizer Block Diagram

CS2
0
0
0
0
1
1
1
1

External Select
CSI
0
0
1
1

0
0
1

1

(Internal Select PLL Control Register)
CSO
0
1
0

BIT 2
BIT 1
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
1
Video Clock Selection Table

321

BIT 0
0
1
0
1

0
1
0
1

CLK 0 Frequency
fO
f1
f2
f3
f4
f5
f6
f7

ICS5301
GENDAC

PLCK

PooP?

BLANK'

UUU\ \ 0 / / U U U U U U
c

LA~B~\

RED

'-----_ _ _ _ _ _ _ _ _ _~I

GREEN

'---------------~I

BLUE

'---__________-'1

\

LBLANK-BLANK~

B

A~~
A

F~G~

IF~G~

C~BLANK-BLANKJ

~B~C~BLANK-BLANK~ F ~G----.r

System Timing - Pseudo Color, Mode 0

PLCK

PooP?

BLANK'

RED

GREEN

BLUE

C

~BLANK---BLANKJ

C~BLANK---BLANKJ
C

~BLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

322

ICS5301
GENDAC

•
PCLK

BLANK

PO-P7

A.-----I,rBDAC-RD

---+---------------------1--"

DAC-GR

_ ______________________________~~~A~B/

DAC-BL

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1~~A-----I,rB--

System Timing Bypass -15 (5/5/5) and 16 (5/615) Modes 1, 2

Ons

25ns

50ns

75ns

100ns

125ns

150ns

PLCK

PO-P7
DAC-BL _ _ _ _ _ _ _ _ _ _ _ _ _ ____1/

DAC~R---------------~-----~----~~
DAC-RD _ _ _ _ _ _ _ _ _ _ _ _ _ _---'/r---:AA----------;B,.---~~

System Timing Bypass True Color 24 (8,8,8) Mode 3

323

ICS5301
GENDAC

•
WR'

RSO-RS1

00-07

Basic Write Cycle Timing

RO'

RSO-RS1

00-07

Basic Read Cycle Timing

WR'

~

\

RO'

RSO

n

/

RS1

U

~

X

XJ

n

/ ... X

XJ

[]

.
..
~

L

XJ
XJ

Write to Pixel Mask Register Followed by Read

Write to Pixel Mask Register Followed by Write

WR'

'~ll

t RHAl1

\

1'---------RD'

'"-rt=

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

324

ICS5301
GENDAC

II
WR"

RO"

~·'~t=

RSO

RS1

V
V

\
\

7
7

RS2

~

/

\

00-07

WR"

-------\ ADDRESS '(-------
----<

ADDRESS

)1--------------

Write and Read back PLL Address Register (Write Mode)

WR*

~.

t WHAL3

RO*

'L

RSO

V

\

7

\-

RS1

V

\

7

\

V

\

7

\

RS2

00-07

---<

ADDRESS

'>----<

ADDRESS

)1--------------

Write and Read back PLL Address Register (Read Mode)

328

ICS5301
GENDAC

•
WR*

RO*

RSO

RS1

RS2

\~"

':tAAi1f----

o

u

\

\

u

00-07 _ _--{

PLL ADDRESS

Read Two bytes PLL Register then PLL Address Register

WR*

~"

'. .""tAfi--t--h-------+RHRL

_

RO*

RSO

LJ

RS1

LJ \ \ r==\ r==\
LJ ~ ~

RS2

00-07 -----\

~

ADDRESS

~

~

~~-----------

Read One Byte PLL Register then PLL Address Register

329

ICS5301
GENDAC

II
Monitor SENSE Signal
RED,
GREEN,
BLUE

335V

'-----.-1 'soD
SENSE:"---+----_

Recommended Layout
tiple vias to the ground and power planes, if possible. Power
connections should be connected to the analog or digital power
plane, as shown in the diagram. Power pins 5 and 29 should be
connected to digital power, power pins 20 and 24 to analog
power. Decoupling capacitors (indicated by Cl) should be
placed as close to the GENDAC as possible.

The high performance of which the ICS5301 GENDAC is
capable is dependent on careful PC board layout. The use of
a four layer board (internal power and ground planes, signals
on the two surface layers) is recommended. The layout below
shows a suggested configuration.
The ground plane is continuous, but the power plane is
separated into analog and digital sections as shown. Power is
supplied to the analog power plane through the ferrite bead,
and bypassed atthe power entry point by C3, a 10 IlF tantalum
capacitor. These high current connections should have mul-

The analog and digital I/O lines are not shown. Analog signals
(DAC outputs, Vref, Rset) should only be routed above the
analog power plane. Digital signals should only be routed
above the digital power plane.

Cl

DIGITAL Power
Plane

Cl

+

Yl

100 mil Separation

40

'---a 41

42
43

44

c:::JoC>C:)

Cl

Cl

1
2
3

ICS5301

..........--JO"'-_-O ~
6

+

o_
0+
C1
C2
C3
FBI
R1
Y1

VIA to ground plane
VIA to power plane
,01 uf clup capaCltor
,1uf clup capaCltor
10uf tantulum capaotor
Fernte Bead
140 ohm 1 % reSlstor
14.318 Mhz paralleJ resonant crysaJ cut for C L=12

330

C2

C3

II

ICS5340
GENDAC

Integrated
Circuit
Systems, Inc.

16-Bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5340 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a
triple 8-bit video DAC. The GENDAC supports 8-bit
pseudo color applications, as well as 15-bit, 16-bit and 24bit True Color bypass for high speed, direct access to the
DACs.

• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (ClKO)
• Two programmable memory (controller) clock
frequency (ClKl)
• DAC power down in blanking mode
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor Sense
• Internal voltage reference
• 135 MHz (-3),110 MHz (-2) & 80 MHz (-1) versions
• Very low clock jitter
• latched frequency control pin

The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, 6 of
which are programmable by the user. The memory clock
has two programmable frequency locations.
The three 8-bit DACs on the ICS5340 are capable of
driving singly or doubly-terminated 750 loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows
displayed colors to be changed in a single write cycle
rather than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

Block Diagram
PCLK------'t

18

NORM

DO-D7

PCLK

WR"-RD" _ _

~p

- INTERFACE

RSO·2~

~------------~------------------------~~CLKO

XOUT

'1-----------------------------------------.

331

eLK!

ICS5340
GENDAC

Pin Configuration
N/C
N/C
N/C

N/C
N/C

WR*
RS2
RSI
RSO

CVDD

GENDACII
ICS5340

XIN

XOUT
CGND

Pl2
Pll
PIO
P9
P8
P7
P6

DVDD
P5

CLKI

AGND

CGND
N/C
N'/C
N/C
N/C

P4
P3
P2

N/C
N/C

Rev 1.0

Pin Description (68 pin PLCC)
Symbol
D7-DO

Pin #
68,1 - 7

Type
I/O

RD*

8

Input

WR*

13

Input

RS2
RSI
RSO
CVDD
XIN
XOUT
CGND

14
15
16
17
18
19
20

Input
Input
Input

Input
Output

-

Description
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
RAM/PLL Write Enable, active low. This signal controls the timing of the
write operation on the microprocessor interface inputs, DO-D7.
Register Address Select O. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Crystal oscillator and CLKO power supply connect to AVDD.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
VSS for CLKO. Connect to ground.

332

ICS5340
GENDAC

•
Pin Description (continued)
Symbol

Pin #

Type

CLKI
CGND
CLKO

21
22
28

Output

CVDD
CSO

29
30

Input

CSI

31

Input

CS2

32

Input

VREF

33

I/O

RSET

34

Input

SENSE*

35

Output

AVDD
BLUE
GREEN
RED

37
36
38
39

Output
Output
Output

STROBE
PO - PIS

40
41- 42
46-48,50

Input
Input

49
51
65
52-58,
62-64

-

Input

BLANK*

66

Input

DGND

67

-

AGND
DVDD
PCLK

-

Output

-

-

-

Description
Memory clock out~ut. Used to time the video memory.
VSS for CLKl. Connect to ground.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
CLKI Power Supply. Connect to AVDD.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Internal Reference Voltage. Normally connects to a 0.1~ cap to ground.
To use an external Vref, connect a l.235V reference to this pin.
Resistor Set. This pin is used to set the current level in the analog outputs.
It is usually connected through a 140Q, 1% resistor to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
DAC power supply. Connect to AVDD.
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value.
These outputs are typically used to drive a CRT monitor.
Latches the input clock select signals CSO - CS2.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be 2:rounded if thev are not used.
DAC Ground. Connect to ground.
Digital power supply.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK* inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be updated through DO-D7 during blanking.
Digital Ground. Connect to ground.

333

ICS5340
GENDAC

•
Internal Registers
RS2 RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENDAC. This register
can be accessed through either register address 0,0,0 or register address
0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.

° ° °
° 1 1
° ° 1

Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
color values to the color palette RAM.

Pixel Address
READ

Writing to this 8-bit register is performed prior to reading one or more
color values from the color palette RAM.

Color Value

The 18-bit Color Value register acts as a buffer between the microprocessor
interface and the color palette. Using a three bytes transfer sequence allows
a value to be read from or written to this register. When a byte is read, the
color value is contained in the least significant 6 bits, DO-DS (the most
significant 2 bits are set to zero). When writing a byte, the same 6 bits are
used. When reading or writing, data is transferred in the same order - the
red byte first, then green, then blue. Each transfer between the Color Value
register and the color palette replaces the normal pixel mapping operations
of the GENDAC for a single pixel.
After writing three definitions to this register, its contents are written to the
location in the color palette RAM specified by the Pixel Address register,
and the Pixel Address register increments.
After reading three definitions from this register, the contents of the location
in the color palette RAM specified by the Pixel Address registers are copied
into the Color Value register, and the Pixel Address register increments.

°

1

°

Pixel Mask

The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
position in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask register
does not affect the Pixel Address generated by the microprocessor interface
when the palette RAM is being accessed.

334

ICS5340
GENDAC

•
Internal Registers (continued)
RS2

RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

1

0

0

PLL Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
PLL programming values to the PLL Parameter register.

1

1

1

PLL Address
READ

Writing to this 8-bit register is performed prior to reading one or more
PLL programming values from the PLL Parameter register.

1

1

0

Command

This 8-bit register selects the color mode, for instance 8-bit Pseudo Color, HiColor, True Color, or XGA, and DAC power down. The registers are reset
to pseudo color mode on power up.

1

0

1

PLL
Parameter

There are sixteen parameter registers as indexed by PLL Address Write!
Read registers. Parameter registers 00-00 and OF are two bytes long and OE*
is one byte long. This register set contains one control register. The bits of this
register include clock select and enable functions, the rest contain PLL
frequency parameters. After writing the start index address in the PLL
address register, these registers can be accessed in successive two (or one)
bytes. The address register auto increments after one or two bytes to access
the entire register set.

335

ICS5340
GENDAC

•
Absolute Maximum Ratings
Power Supply Voltage .................................................. 7 V

DC Digital Output Current .................................... 25 rnA

Voltage on any other pin ...... GND - 0.5V to VDD + O.5V

Analog Output Current ......................................... .45 rnA

Temperature under bias .......................... - 40° C to 85° C

Reference Current .................................................. -15 rnA

Storage Temperature ............................. - 65° C to 150° C

Power Dissipation ..................................................... 1.0 W

Note

Stresses above those listed under Absolute MaxlInum Ratmgs may cause permanent damage to the devIce. This is a stress rating only and
funchonal operahon of the device at these or any other conditions above those indIcated In the operational sections of this specification
IS not ImplIed. Exposure to absolute maximum rating conditIOns for extended periods may affect device reliabIlity.

Electrical Characteristics
Symbol

Parameter

Conditions

Min

Max

Units

V

DC CHARACTERISTICS (note: J)
VDD

Positive supply voltage

4.75

5.25

VIH

Input logic "1" voltage

2.0

VDD + 0.5

V

VIL

Input logic "0" voltage

IREF
VREF

Reference current

0.5
-7.0

0.8
-10

V
rnA

lIN

Digital input current

Reference voltage

1.10
VDD = max,

1.35

V

± 10

llA

±50

llA

250

rnA

50

rnA

GND~VIN~VDD

loz

Off-state digital output current

VDD = max,
GND~VIN~VDD

IDD

Average power supply current

10= max,
Digital outputs unloaded

DACs in power down mode

No palette access

IDACOFF
VOHS
VOLS

Sense logic "1"

10= .4mA

Sense logic "0"

10= .4mA

VOHC

Clock logic "1"

10 = TBD

VOLC
VOH

Clock logic "0"
logic "1"

10 = -3.2mA, note K

VOL
ICLKr *

logic "0"

10 = 3.2mA, note K

ICLKf*

Input Clock Fall Time

FD

Frequency Change of CLKO and
CLKI over supply and temperature

Input Clock Rise Time

2.4

V
0.4

Ia = TBD

V
V

2.4
0.4

V

TTL levels

0.4
15

V
ns

TTL levels

15

ns

With respect to
typical frequency

0.05

%

336

2.4

V

ICS5340
GENDAC

•
Electrical Characteristics (continued)
Symbol

Parameter

Conditions

Min

Max

Units

DAC CHARACTERISTICS (note: J)
Va (max) Maximum output voltage
Maximum output current
Full scale error
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*

10 (max)

1.5
21
±5
±2
±0.5

:0; 10 rnA
Va :0; IV
note A, B
note B
note B
note B
noteC
noteC
noteC
note C

10

±l

28
20
6
200

V
rnA
%
%
LSB
LSB
ns
ns
ns
pVsec

* Charactenzed values only

Symbol

Parameter

Conditions

Min

Max

Units

25
25

135
135
3
3
60/40
130 ps
300 ps
25

MHz
MHz
ns
ns
%

PLL AC CHARACTERISTICS
fa
f1
tr
tr
dt
hs
jabs
fref

Clock 0 operating range*
Clock 1 operating range*
Output clocks rise time*
Output clocks fall time*
DutyCycle*
Jitter, one sigma*
Jitter, absolute*
Input reference frequency*

25 pf load, TTL levels
25 pf load, TTL levels
40/60

Typically 14.318 MHz

337

-300 ps
5

ps
ps
MHz

II

ICS5340
GENDAC

AC Electrical Characteristics (note: J)

Symbol
tCHCH
Llt CHCH*
tCLCH
t CHCL
t pvcH
t CHPX
t BVCH

Parameter

tWHWL2
tWHRL2
tRHRL2
tRHwL2
tWHRL3

PCLKperiod
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC output
Differential output delay
WR* pulse width low
RD* pulse width low
Register select setup time
Register select setup time
Register select hold time
Register select hold time
WR* data setup time
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write interval
WR* followed by read interval
Successive read interval
RD* followed by write interval
WR* after color write
RD* after color write
RD* after color read
WR* after color read
RD* after read address write

tSOD

SENSE* output delay

tCHBX
tCHAV*
L'ltCHAV
t WLWH
tRLRH
tSVWL
tSVRL
t WLsX
t RLSX
t DvwH
tWHDX
tRLQX
tRLQV
tRHQX
tRHQZ
tWHWLl
tWHRLl
tRHRLl
t RHwLl

Condition

80 MHz
Max
Min

110 MHz
Min
Max

135 MHz
Min Max Units

12.5

9.09

7.4

±2.5

note D

%

5
5

3.6
3.6

3

3
3
3
3

3

2
1
2
1

(tCHCH)

4 (tcHCH )

4 (tCHCH)

4 (tcHCH )
4 (tcHCH )
~ (tCHCH )

4 (t cHCH)
4 (tcHCH)
4 (tCHCH )

4 (tCHCH )
4 (tCHCH )
4 (tCHCH)

8 (tCHCH)
8 (tcHCH)
8 (tCHCH)

8 (tCHCH )
8 (tcHCH )
8 (tCHCH )

8 (tCHCH)
8 (tCHCH )
8 (tCHCH)

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

1

I1s

noteE
noteE
noteE
noteE
noteF
noteG

3

2
20
2
50
50
10

10

10
10
10
10
10

10

10
5

10
5

50
50

10
10

10

40
5

40
5

20
~ (tcHCH )

1

40
5

20
4 (tcHCH )
4 (tCHCH )

~ (tCHCH)

338

20
2

50
50
10
10
10
10
10
5

~

3

2

20
2

Write cycle
Read cycle
Write cycle
Read cycle

noteH
note I
note I
note I
note I
note I
note I
note I
note I
note I

ns

+2.5

20
4 (tCHCH)
4 (tCHCH)

1

ICS5340
GENDAC

•
General Operation

NOTES
A.

Full scale error IS denved from des.gn equatton
{[(F.S loUT) 1\ - 2.1 (IREF) 1\1/[2 1(IREF)RLlIlOO%
VBLACK LEVEL=OV F.S lOUT = Actual full scale measured output

B.

R= 37.5(1, lREF = - 8.88mA

C

~=

D.

This parameter .s the allowed PlXel Clock frequency variallon. It
does not penmtthe P.xelClockpenod to vary outside the m.rumum
values for Pixel Clock (tCHCH) period

E.

It is required that the color palette's pixel address be a vahd log.c

37.5(1 + 30 pF, IREF = - 8 88mA

level with the appropnate setup and hold times at each rismg edge
of PCLK (thIS reqmrement includes the blankmg period).
F

The output delay.s measured from the 50% point ofthe nsmg edge
of CLOCK to the vahd analog output. A vahd analog output .s
defined when the analog s.gnal.s halfway between.ts success.ve
values.

G

This applies to different analog outputs on the same dev.ce.

H.

Measured at ± 200 m V from steady state output voltage

I.

This parameter allows synchroruzation between operations on the
microprocessor interface and the pixel stream bemg processed by
the color palette.

J.

The following specmcations apply for Vnn = +5V± O.5V, GND=O
Operating Temperature = O°C to 70°C.

K.

Except for SENSE pin.

AC Test Conditions
Input pulse levels ................................................. VDD to 3V
Input rise and fall times (10% to 90%) ......................... .3ns
Digital input timing reference leveL ........................ 1.5V
Digital output timing reference level... ..... 0.8V and 2.4V

An externally generated BLANK* signal can be applied to
pin 66 of the ICS5340. This signal acts on all three of the
analog outputs. The BLANK* signal is delayed internally
so that it appears with the correct relationship to the pixel
bit stream at the analog outputs.
A pixel word mask is included to allow the incoming
pixel address to be masked. This permits rapid changes to
the effective contents of the color palette RAM to facilitate
such operations as animation and flashing objects.
Operations on the contents of the mask register can also
be totally asynchronous to the pixel stream.
The ICS5340 also includes dual PLL frequency generators
providing a video clock (CLKO) and a memory clock
(CLK1), both generated from a single 14.318 MHz crystal.
There are eight selectable CLKO frequencies. Six are
programmable, and two are fixed. There are two selectable and programmable CLKI frequencies (fA, fB). Default values (Table 1 and Table 2) are loaded into the
appropriate registers on power up.

Video Path

Capacitance
C1 Digital input. .............................................................. 7pF
Co Digital output. ........................................................... 7pF
COA Analogoutput.. ..................................................... 10pF
20012

1.4V

I/O~

I

The ICS5340 GENDAC is intended for use as the analog
output stage of raster scan video systems. It contains a
high-speed Random Access Memory of256 x 18-bitwords,
three 6 / 8-bit high-speed DACs, a microprocessor / graphic
controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators.

50 pF

The GENDAC supports nine different video modes and
is determined by bits 4-7 of the command register. The
default mode is the 8-bit Pseudo Color mode. The other
modes are the bypass 15-bit, 16-bit and 24 bit True Color
modes in 8-bit and 16-bit interface, and the 16-bit Pseudo
Color (2:1) mode with 2X Clock.. The 16-bit True Color
has sparse and packed modes.

(including scope and jig)

DIGITAL OUTPUT LOAD

339

ICS5340
GENDAC

•
Pseudo Color
8-bit Interface
In this mode, Pixel Address, PO-P7 and BLANK" inputs
are sampled on the rising edge of the clock (PCLK) and
any change appears at the analog outputs after three
succeeding rising edges of the PCLK. The DAC outputs
depends on the data in the color palette RAM.

The reference current IREF is determined by the reference
voltage VREF and the value of the resistor connected to
RsET pin. VREF can be the internal band gap reference
voltage or can be overridden by an external voltage. In
both cases IREF =VREF/RsET'
I lOUT

Iif1R
I'"

16-bit Interface
In this mode, Pixel Address, PO-PI5 and BLANK" inputs
are sampled on the rising edge of the clock (PCLK) and
any change appears at the analog outputs after three
succeeding rising edges of the 2 x ICLK. The DAC outputs
depends on the data in the color palette RAM.

33
VREF
(Elm

34

1

EFF

J

RSET

Figure 4 - DAC Set up

The BLANK" inputto the GENDAC acts on all three ofthe
DAC outputs. When the BLANK" input is low, the DACs
are powered down.

Bypass Mode

The GENDAC supports seven different bypass modes:
three for byte transfers and four for word transfers. In The connection between the DAC outputs of the ICS5340
these modes, the address pins PO-PI5 represent Color and the RGB inputs of the monitor should be regarded as
Data that is applied directly to the DAC . The internal a transmission line. Impedance changes along the translook-up table RAM is ignored. During byte transfers, the mission line will result in the reflection of part of the video
P8-P15 inputs are Don't Care. Data is always latched on signal back along the transmission line. These reflections
the rising edge of PCLK. Byte or Word framing is inter- may result in a degradation of the picture displayed by
the monitor.
nally synchronized with the rising edge of BLANK".

Dac Outputs
The outputs of the DACs are designed to be capable of
producing 0.7 volt peak white amplitude with an IREF of
8.88 rnA when driving a doubly terminated 750 load.
This corresponds to an effective DAC output load
(REFFECfIVE ) of 37.50. The formula for calculating IREF
with various peak white voltage/output loading
combinations is given below:
IREF =

VPEAK WHITE
2.1

X ~FFECTIVE

Note that for all values of IREF and output loading:
V BLACK LEVEL = 0

RF techniques should be observed to ensure good fidelity. The PCB trace connecting the GENDAC to the offboard connector should be sized to form a transmission
line of the correct impedance. Correctly matched RF
connectors should be used for connection from the PCB to
the coaxial cable leading to the monitor and from the
cable to the monitor.
There are two recommended methods of DAC termination: double termination and buffered signal. Each is
described below with its relative merits:
Double Termination (Figure 1)
For this termination scheme, a load resistor is placed at
both the DAC output and the monitor input. The resistor
values should be equal to the characteristic impedance of
the line. Double termination of the DAC output allows
both ends of the transmission line between the DAC

340

ICS5340
GENDAC

II
outputs and the monitor inputs to be correctly matched.
The result should be an ideal reflection free system. This
arrangement is relatively tolerant to variations in
transmission line impedance (e.g. a mismatched
connector) since no reflections occur from either end of
the line.
A doubly terminated DAC output will rise faster than any
singly terminated output because the rise time of the
DAC outputs is dependent on the RC time constant of the
load.

)-

ICS5340

GND

MONITOR

GND

Figure 1 - Double Termination

Buffered Signal (Figure 2)
If the GENDAC drives large capacitive loads (for instance
long cable runs), it may be necessary to buffer the DAC

outputs. The buffer will have a relatively high input
impedance. The connection between the DAC outputs
and the buffer inputs should also be considered as a
transmission line. The buffer output will have a relatively
low impedance. It should be matched to the transmission
line between it and the monitor with a series terminating
resistor. The transmission line should be terminated at
the monitor.

ICS5340

rV

RS

) RLOAD
GND

PLL Clock
The ICS5340 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK1)
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop filters, minimizing board component
count.

RLOAD
RLOAD

I

reference voltage to the comparators, the SENSE* pin is
driven low. This signal is used to detect the type of (or lack
of) monitor connected to the system.

MONITOR
Rr

l

GND

There are eight possible video clock, CLKO, frequencies
(fO-£7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bitin the PLL
control register. Two of these frequencies (fO-£1) are fixed
and the other six (f2-£7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL parameter registers. The default frequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There are two programmable memory clock frequencies (fA, fB). On power up this frequency defaults to
the frequency given in table 2. The memory clock transition between frequencies is smooth and glitch free if the
transition is kept between the limits 45-65 MHz.

fA

(MHz)

to
f1
12
13
14
f5

25.175
28.322
31.500
36.00
40.00
44.889

16

65.00

17

75.00

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF = 1.23 Volts. When
the voltage on any of these pins go higher than the

341

VLCK
Comments
VGAO (VGA Graphics) (fixed)
VGA 1 (VGA Text) (fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768 @ 70 Hz,
True Color 640 x 480 (programmable)

Table 1- Video clock (CLKO) default frequency register
(with a 14.318 MHz input)

I

ICS5340
GENDAC

Writing to the color palette RAM
fn

MHz

Comments

fA

45.00 MHz Memory and GUI subsystem clock

f8

55.00 MHz Memory and GUI subsystem clock

Table 2 - Memory Clock (CLKl) default frequency
register

Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5340, and the register addresses through
which they can be accessed.
RS2

RSl

RSO

0
0
0
0
1
1
1
1
O/HF

0
1
0
1
0
0
1
1
1

0
1
1
0
0
1
0
1
0

Register Name
Pixel Address (write model
Pixel Address (read model
Color Value
Pixel Mask
PLL Address (write model
PLL Parameter
Command
PLL Address (read model
Command Register
accessed by (hiddenl flag after
special sequence of events

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the GENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.
Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.
Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.
The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

342

ICS5340
GENDAC

•
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is reset for Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5340 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. At the end of the second Read, the address
location is automatically incremented.The address register (OE) is incremented after the first byte Read.

Power Down Mode
When bit 0 in the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5340. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

343

Power Supply
As a high speed CMOS device, the ICS5340 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 27.
To supply the transient currents required by the ICS5340,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended thatthe decoupling capacitance
between VDD and GND should be a O.1~F high frequency
capacitor, in parallel with a large tantalum capacitor with

Ii

ICS5340
GENDAC

•
a value between 22/lF and 47/lF. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EM!.
The combination of series impedance in the ground supply
to the GENDAC, and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the GENDACbehave like low impedance transmission lines driven
from a low impedance transmission source and terminated with a high impedance. In accordance with transmission line principles, signal transitions will be reflected
from the high impedance input to the device. Similarly,
signal transitions will be inverted and reflected from the
low impedance TTL output. Line termination is recommended to reduce or eliminate the ringing, particularly
the undershoot caused by reflections. The termination
may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of

using fewer components. Series termination is accomplished by placing a resistor in series with the signal at the
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around lOOn will be
required. Since each design will result in a different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

344

ICS5340
GENDAC

(I
Bit 7-4

Functional Description
This section describes the register address and bit definition
for RAMDAC and the Frequency Synthesizer sections.

Bit 3 - 1 (Reserved)

Color Palette
Command Register
(RSO-RS2 = 011)
(RSO-RS1 = 01 with hidden flag)

Bit 0

By setting bits in the command register the ICSS340 can
be programmed for different color modes and can be
powered down for low power operation.
7
6
S
Color Mode
2
1
0

I

4

Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

2
3
1
Reserved = 0

0
Snooze

3

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/ stop controL The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Table 3 - Command Registers

8-BIT INTERFACE
Mode
CM3 CM2 CMl CMO
Number (CR4) (CR7) (CR6) (CR5)
0
1
3
2
1
1
2
3

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

16-BIT INTERFACE
Mode
CM3 CM2 CMl CMO
Number (CR4) (CR7) (CR6) (CR5)
4
S
6
7
8

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1

0
1

Clock Cycles!
Pixel Bits

Color Mode
8-Bit Pseudo Color with Palette (Default)
IS-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
16-Bit Direct Color with Bypass (XGA)
IS-Bit Direct Color with Bypass (Hi-Color)
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

1
2
3
2
2
2
2
3
Clock Cycles!
Pixel Bits

Color Mode
Muxed 16-Bit Pseudo Color with Palette
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit Direct Color with Bypass (True-Color)
24-Bit Packed Direct Color with Bypass (True-Color)
Reserved
Reserved
Reserved
Table 4 - Color Mode Select

345

1/2
1
1
2
3/2

ICS5340
GENDAC

•

Mode 2: (16-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POThe nine selectable color modes are described here. Modes P7 inputs to go to the DAC directly, bypassing the color
0- 3 are 8-bit interfaces with PO-P7 bits, P8-P15 are Don't palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
Care bits.
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 5 bits wide and green is 6
Mode 0: 8-bit Pseudo Color (one clock per pixel). This bits wide. The 2 bytes of data is packed as shown below.
mode is the 8-bit per pixel Pseudo Color mode. In this This mode can be selected by setting bits CR7-CR4 to 0110
mode, inputs PO-P7 are the pixel address for the color or 1100.
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is I6-Bit Color Mode 2 Pixel Description
selected by setting bits CR7-CR4 to 0000. There are three
2LSB = set to zero (green)
clock cycles pipe line delays from input to DAC output.
3LSB =set to zero (blue, red)

Color Modes

8-bit Pseudo Color Mode
7 6 543 2 1 076 5 4 3 2 1
PIXEL BYTE
PPPPPPPP

7654321
7 6 5 4 3 2 1

a

7 6 5 4 3
BLUE

a
a

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
BLANK*. In this mode, each of the colors are 8-bit wide
and the DAC is an 8-bit wide DAC. The first byte is blue
followed by green and red. This mode can be selected by
setting bits CR7-CR4 to 0100 or 1110. The DAC outputs
changes every three cycles and the pipeline delay from
the first byte to output is five cycles.

PIXEL ADDRESS

Mode 1: 05-bit per color bypassHi-Color mode).
This mode is the IS-bit per pixel bypass mode. In this
mode, inputs PO-P7 are the color DATA and are input
directly to the DAC, bypassing the color palette. The two
bytes of data is latched in two successive PCLK rising
edges. ICS5340 supports only the two clock mode and
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the 15/ 24-bit Color Mode 3 Pixel Description
16 one clock modes are selected as two clock modes in this
SECOND BYTE
FIRST BYTE
THIRD BYTE
chip. The low-byte, high byte synchronization is internally PPPPPPPP PPPPPPPP PPPPPPPP
done by the rising edge of BLANK*. Each color is S-bit 7 6 5 4 3 2 1 a 7 6 5 4 321 a 7 6 5 4 3 2 1 a
wide and is packed into two bytes as shown below. This
mode can be selected by setting bits CR7-CR4 to 0010, 7 6 543 2 1 076 5 4 3 2 1 a 7 6 5 4 3 2 1 a
GREEN
BLUE
RED
1000 or 1010.
I5-Bit Color Mode 1 Pixel Description
3LSB = set to zero
SECOND BYTE
FIRST BYTE
PPPPPPPP PPPPPPPP

7 6 543 2 1

a 765

4 321

a

xI76 5 4 317 6 5 4 317 6 5 4 3
RED

GREEN

BLUE

Modes 4 - 8 use the 16-bit pixel interface.
Mode4: (S-bitPseudoColortwopixelsperclock) Inthismode,
inputsPO-P15arelatchedontherisingedgeofeveryPCLK. PO7 and PS-P1S are used for successive addresses for the palette
RAM using an internal clock that runs at twice the PCLK
frequency. TheDACoutputschangetwiceforeveryPCLKand
the pipeline delay from the first word to output is one and a one
half cycles. This mode can be selected by setting bits CR7-CR4
to 0001.

346

ICS5340
GENDAC

II

Multiplexed 8-bit Pseudo Color Word Mode 4 Pixel
Mode 7: (16-bit pixel interface, 24-bit per color bypass
Description
TRUE color mode) In this mode inputs PO-PIS are the
color Data and are input directly to the DAC bypassing the
PIXEL WORD
color Palette. Two words are latched on two successive
PPPPPPPPPPPPPPPP
rising edge of PCLK to form the 24-bit DAC input. The
51413121110 9 8 7 6 5 4 3 2 1 0
first word and the lower byte of the second word form the
7 6 5 4 3 2 1 o7 6 5 4 3 2 2 0
24-bit pixel input to the DAC. The higher byte of the
2nd PIXEL
1st PIXEL
second word is ignored. The low and high word synchroADDRESS
ADDRESS
nization is internally done by the rising edge of the
BLANK*. The pipeline delay from latching of first word to
Mode 5: (16-bit pixel interface, IS-bit per color bypass Hi- DAC output is 4 cycles and each pixel is 2 pixel clocks
Color Mode) In this mode inputs PO-PIS are the color Data wide. In this mode, each of the colors are 8-bits wide and
and are input directly to the DAC, bypassing the color the DAC is 8-bit wide DAC. The first byte is Blue followed
palette. The Data is latched by the rising edge ofPCLK and by Green and Red. This mode is selected by setting bits
is pipelined to the DAC. The pipeline delay from input to CR7-CR4 to 0111.
DAC output is 3 PCLK cycles. Each color is S-bit wide as
shown below. This mode is selected by setting bits CR7- 24-Bit Direct Color Word Mode 7 Pixel Description
CR4 to 0011.
,-----:FI:::R:::S:::T:-:W':":O=R:::D-----,
PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0

IS-Bit Color Word Mode 5 Pixel Description
3LSB = set to zero

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
GREEN
1
BLUE

PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0

SECOND WORD
PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0

XI7 6 5 4 317 6 5 4 317 6 543
1 RED
1 GREEN 1 BLUE

Mode 6: (16-bit pixel interface, 16-bit per color bypass
XGA mode) In this mode input PO-PIS are the color Data
and arc input directly to the DAC bypassing the color
Palette. The Data is latched by the rising edge ofPCLKand
is pipelined to the DAC. The pipeline delay, from input to
DAC output, is 3 PCLK cycles. In this mode Blue and Red
colors are S bits wide, and Green is 6 bits wide. This mode
is selected by selecting bits CR7-CR4 to 0101.
I6-Bit Color Word Mode 6 Pixel Description
2LSB = set to zero (GREEN)
3LSB = set to zero (BLUE, RED)
PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0
7 6 5 4 317 6 5 4 3 217 6 5 4 3
RED
GREEN
1 BLUE

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
RED

1

L....._ _ _ _ _ _'--_....:..:.:::.::..._ _---'

Mode 8: (16-bit pixel interface packed 24-bit per color
bypass TRUE color mode) In this mode inputs PO-PIS are
the color Data and are input directly to the DAC bypassing
the color Palette. Three words are latched on three successive rising edge of PCLK to form two successive 24-bit
DAC inputs. The 16-bit first word and the lower byte of
the second word from the first 24-bit pixel input and the
second byte of the second word with the 16 bits ofthe third
word from the second 24-bit pixel input. This cycle repeats
every 3 cycles. The three word synchronization is internally done by the rismg edge of BLANK*. The pipeline
delay from latching of first word to DAC output is 3 1/2
cycles and each of the colors are 8-bits wide and DAC is 8bit wide DAC. The first byte is Blue followed by Green and
Red. Repeats. This mode is selected by setting bits CR7CR4 to 1001.

347

ICS5340
GENDAC

•
Packed 24-bit Word Mode 8 Pixel Description
IstDACCycle
SECOND WORD
FIRST WORD
pppppppp pppppppppppppppp
7 6 5 432 1 0 15 1413 12 1110 9 8 7 6 5 4 3 2 1 0

7 6 5 432 1 0 7 6 5 4 3 2 1 0\7 6 5 4 3 2 1 0
RED
GREEN
BLUE

2nd DAC Cycle
THIRD WORD
SECOND WORD
pppppppppppppppp pppppppp
151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RED
GREEN
BLUE

Index

R/W

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/W
R/R/R/W
R/-

CLKO £0 PLL Parameters
CLKO f1 PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO £4 PLL Parameters
CLKO f5 PLL Parameters
CLKO £6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLKI fAPLL
CLKI fB PLL
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(I-byte)
(2-byte)

Table 5 - PLL Parameter Registers

Frequency Generators

PLL CONTROL REGISTER
The ICS5340 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values
to the PLL Parameter Register Bank (table 5).

Bits in this register determine internal or external CLKO
select.
0
7
5
4
2
1
6
3
(RV) (RV) ENBL CLKI (RV) INTERNAL SELEC1
-0
-0 INCS SEL -0
X
X
X

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed by register select pins
RS2-RSO = 100 or 111.
6 5 4 3 2 1 0
PLL REGISTER ADDRESS
7 6 5 4 3 2 1 0

Bit 7,6, 3 Reserved.
Bit 5

Enable Internal Clock Select ONCS) for CLKO.
When this bit is set to 1, the CLKO output
freq uency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4

Clkl Select
When this bit is set to 0, fA is selected. When it
is set to 1, fB is selected. Default is 0, fA selected,
at power up.

7

PLL Parameters Registers
There are sixteen registers in the PLL parameter register
(table 5). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLKI programmable frequency and register OE is the PLL CLKO control register.

Bit 2 - 0 Internal Clock Select for CLKO (INCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects £0.

348

ICS5340
GENDAC

•
PLL Data Registers

Programming Example

The CLKO and CLK1 input frequency is determined by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.

Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

M-Byte PLL Parameter Input
The M-byte has a 7-bitvalue 0-127) which is the feedback
divider of the PLL.
7
6
Reserved
=0
X

5
X

4
3
2
1
M-Divider Value
X

X

X

X

a

( 25.175) 4= (M + 2)
14.318
(N1 + 2)

X

N-Byte PLL Parameter Input
The N-byte has two values. N1 sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2, 4, or 8 post divide clock output.
7
6
5
4
3
2
1 0
Reserved N2-Code
N1-Divider Value
X
X
X
X
X X
=0
X

by trial and error:
( 25.175) . 4 = 127
14.318
18
so
M + 2 = 127
N1 + 2 = 18

M= 125
N1 = 16

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = a & N2 code & Nl = 0 & 1 0 & 1 0 0 a
N=01010000b

e •

N2 Post Divide Code
If mode 4 is set in the command register, CR7-CR4 equal
0001, N2 code must be 10.

N2code
00
01
10
11

From the table in the previous section, we find N2 = 2
Substituting FREF = 14.318 and 2N2 = 4 into the equation on
page 17:

Divider
1
2
4
8

a

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:

The block diagram of the PLL clock synthesizer is shown
in figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
C'v1+2) x Fref
Fout = - - - - (N1+2) X2N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the next section for programming example.

349

The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz
This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the
crystal inputs, so this is not a problem.
2. 600 kHz < fREF :S 8 MHz
(N1+2)
This is the frequency input to the phase detector.

II
3. 60 MHz

ICS5340
GENDAC

s. (M+2) fref

S. 270 MHz

and (Nl +2) combinations can usually be found.
Usually, a few minutes trying out numbers with a
calculator will produce a workable combination.
Multiplying possible values of (Nl +2) by the desired
ratio will indicate approximately the value of M. This
method is shown in the example below. A program
could be written to try all possible combinations of
(M+2) and (Nl +2) (3937 possible combinations), discard those outside error band, and select from those
remaining by giving preference to ratios which use
lower values of (M+2). Lower values of (M+2) and
(Nl+2) provide better noise rejection in the phase
locked loop.

(Nl+2)
This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower
jitter at higher frequencies. Also, running the VCO at
multiples of the desired frequency allows the use of
output divides, which tends to improve the duty
cycle.
4. fCLKO and fCLK1

s. 135 MHz

This is the output frequency.
These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition N2* fCLK s. 270 MHz
B. Calculate

(M+2)
(Nl+2)

=

2N2fout
fref

C. Now (M+2) and (Nl+2) must be found by trial and
error. With a 14.318 MHz reference frequency, there
will generally be a small output frequency error due
to the resolution limit of (M+2) and (Nl +2). For a
given frequency tolerance, several different (M+2)

Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

A. 66*8 = 528 > 250
VCO speed too high
66*4 = 264 > 250
VCO speed too high
66*2 = 132 < 250
VCO speed OK, N2 = 2, N2 code
= 01 from table on page 17 of the data sheet.

B. 132/14.31818 = 9.219
This is the desired frequency multiplication ratio.
C. Setting (Nl +2) = 3,4, ... 12, 13 and performing some
simple calculations yields the following table:
(Note that Nl cannot be 0).

(Nl+2)

(Nl+2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

350

ICS5340
GENDAC

•
The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.
We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

I Fau!

r--

Figure 3 - PLL Clock Synthesizer Block Diagram

(Internal Select PLL Control Register)

External Select
CS2

CSI

CSO

BIT 2

BIT 1

BIT 0

CLK 0 Frequency

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

fO
f1
f2
f3
f4
f5
f6
f7

Video Clock Selection Table

351

ICS5340
GENDAC

PLCK

PO-P7

BLANK"

UUU\ \01' IUUOOUU
C

RED

}- A~B~ \

L--_ _ _ _ _ _ _ _ _ _---'

\...BLANK-BLANK~

B

GREEN

BLUE

}-A~ ~
'--------------'

F~G~

r--F~G~
C----------BLANK-BLANKJ

I'~.----------~~--~,/,VA~B~C\~BLANK-BLANK~ F~G-----.r
System Timing - Pseudo Color, Mode 0

PLCK

PO-P7

BLANK"

RED

GREEN

BLUE

C~BLANK---BLANKJ
C

~BLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

352

ICS5340
GENDAC

PCLK

BLANK

PO-P7

DAC-RD

DAC-GR
DAC-BL

---t----------------------.:..-/

~A~B_
----------------------+~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~A--~~B-

System Timing Bypass - 15 (5/5/5) and 16 (5/6/5) Modes 1, 2

Ons

2Sns

sans

7Sns

lOOns

12Sns

lS0ns

PLCK

BLANK*

PO-P7

DAC-BL

-----------------------~/

DAC-GR

-------------~--~~~~

DAC-RD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'r--A~~-

System Timing Bypass True Color 24 (8,8,8) Mode 3

353

ICS5340
GENDAC

•
PCLK
ICLK
PO-P7
P8-P15

BLANK*

RED

GREEN

)-A,--- BJC------- D,
~ K-L~--------~
~BLANK----~r-J

\r-AJB\..-

~--_--_~I

C'--D-BLANK----~r- J------'L-

BLUE

System Timing - Multiplexed 8-bit Pseudo Color, Mode 4

PCLK

PO-PI5

BLANK*

I

\J \ \ r \ / 7 "-J "-J "-J

RED

GREEN

__________________
L.

~V--A~B~'_~~~
______
/
\ BLANK

BLUE

A~B-~--'B::..::L::..:A=..;NK=-----System Timing -16-bit Color, Mode 5 (5,5,5) and 6 (5,6,5)

354

ICS5340
GENDAC

•
PCLK

PO-PIS

BLANK*

\J\\C\//\J\J\J

RED

GREEN

BLUE

System Timing - 16-bit Direct True Color, Mode 7

PCLK

PO-P15

BLANK'/

RED

V V \ \ C\ C\ / 7 V V V V \.-.

'---------------~>----A~B~BLANK~--BLANK---.I

GREEN '-----_ _ _ _ _ _ _ _ _ _ _

BLUE

----'>____A~_B---- llLANK---BLANK~

'---------------~r--A~B~BLANK---BLANK---.I
System Timing - 24-bit Packed Color, Mode 8

355

II

ICS5340
GENDAC

~IWLWH--

WR'

RSO-RS1

DO-D7

ISVWL

I

,I

F

J

I WLSX

I

'I
I DVWH

1

~

1

J

I

'I

I
IWHDX

'I

Basic Write Cycle Timing

RD'

RSO-RS1

DO-D7

Basic Read Cycle Timing

I WHWLl 1-------1

WR'

RD'

RSO

RS1

0

o

0

Write to Pixel Mask Register Followed by Write

WR'

I AHAL1

Write to Pixel Mask Register Followed by Read

1-------1

RD'

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

356

ICS5340
GENDAC

•
WR*

RO*

RSO

\'-----_____1

v

RS1

\

7

RS2

/

\

00-07

\~----------------------~
\~----------------------~
/

------\ ADDRESS '!------
f::..Olo\"4

000000
C1

0+
C1

cz

C3
FBt

Rt
R2

Yt

o

C2
37 o--c:::J
36 0
0
35 0
CJoOC:J
0
34 0
0
33 ~
0
C2
32 0
Analog Power
31 0
Plane Island
30 0
~

-------

0_

100 mil Separation

C2
VIA to ground plane
VIA to power plane
,00uf chip capacitor
,luf chip capadtor
lOuf tantulum capacitor
Ferrite Bead
140 ohm 1% resistor
100 ohm 5% resistor
parallel resonant crysal cut for C L = 12 pf

362

0
0
0
0
0
0
0

•

ICS5341
GENDAC

Integrated
Circuit
Systems, Inc.

Advance Information

16-Bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5341 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a triple
8-bit video DAC. The GENDAC supports 8-bit pseudo
color applications, as well as IS-bit, 16-bit and 24-bitTrue
Color bypass for high speed, direct access to the DACs.

• Designed for compatibility with Tseng Labs VGA
controllers
• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)
• Two programmable memory (controller) dock
frequency (CLKl)
• DAC power down in blanking mode
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor Sense
• Internal voltage reference
• 135 MHz (-3),110 MHz (-2) & 80 MHz (-1) versions

The RAM makes it possible to display 256 colors selected
from a possible 262, 144 colors. The dual clock generators
use Phase Locked Loop (PLLl technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, 6 of
which are programmable by the user. The memory clock
has two programmable frequency locations.
The three 8-bit DACs on the ICS5341 are capable of
driving singly or doubly-terminated 75Q loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

Block Diagram

• Very low clock jitter
• Latched frequency control pin

PCLK-------'}

RO'RSO

~p

-INTERFACE

-2.:;c..

--'====FF==1i
f--------'--------------.

CLKO

XOUT

' \ - - - - - - - - - - - - - - - - - - - - CLK1

363

ICS5341
GENDAC

•

Advance Information

Pin Configuration

N/C
N/C
N/C
WR'
RS2
RSl
RSO
CVDD
XIN
XOUT

GENDACII
ICS5341

CGND
CLKl
CGND
N/C
N/C
N/C
N/C

N/C
N/C
Pl2
Pll
PlO
P9
P8
P7

P6
DVDD
P5
AGND
P4
P3
P2
N/C
N/C

Rev 1.0

Pin #
68,1 - 7

Type
I/O

RD*

8

Input

WR*

13

Input

RS2
RS1
RSO
CVDD
XIN
XOUT
CGND

14
15
16
17
18
19
20

Input
Input
Input

Symbol
D7-DO

-

Input
Output
-

Description
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
RAM/PLL Write Enable, active low. This signal controls the timing ofthe
write operation on the microprocessor interface inputs, DO-D7.
Register Address Select o. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Crystal oscillator and CLKO power supply connect to AVDD.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
VSS for CLKO. Connect to ground.

364

ICS5341
GENDAC

•

Advance Information

Pin Description (continued)
Symbol

Pin #

Type

CLKI
CGND
CLKO

21
22
28

Output

CVDD
CSO

29
30

Input

CSI

31

Input

CS2

32

Input

VREF

33

I/O

RSET

34

Input

SENSE*

35

Output

AVDD
BLUE
GREEN
RED

37
36
38
39

Output
Output
Output

STROBE
PO- P15

40
41-42
46-48,50

Input
Input

49
51
65
52-58,
62-64

-

Input

BLANK*

66

Input

DGND

67

-

AGND
DVDD
PCLK

-

Output

-

-

Description
Memory clock output. Used to time the video memory.
VSS for CLKl. Connect to ground.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
CLKI Power Sunnlv. Connect to AVDD.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) outnut. Latched bv STB.
Internal Reference Voltage. Normally connects to a 0.111 cap to ground.
To use an external Vref connect a l.235V reference to this pin.
Resistor Set. This pin is used to set the current level in the analog outputs.
It is usuallv connected throul1Ch a 140Q 1% resistor to I1Cround.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor tvne.
DAC power supply. Connect to AVDD.
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value.
These outnuts are tvnicallv used to drive a CRT monitor.
Latches the input clock select signals CSO - CS2.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be
-' I if thev are not used.
DAC (;round. Connf'ct to I1Cround.
Digital power supplv.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK* inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be undated throUlzh 00-D7 durine: blankine:.
Digital Ground. Connect to ground.

365

366

ICS

Motherboard Timing Generator
Products

In this latest issue of the data book, ICS continues to lead the market by offering the industry's widest
selection of advanced motherboard and CPU clock generators found anywhere. New products
include designs to address a wide variety of uses, including disk drive, modem, and Pentium™ CPU
clocking applications. This is all in addition to the widest choice of advanced desktop and laptop
motherboard and CPU systems clock generators in the industry.
As a market oriented company, ICS designs products with and for you, our customers, and we welcome
inquiries concerning new product ideas for any of the above applications.

367

ICS liming Generator Selection Guide
Motherboard Clock Products
Product
Application

ICS
Device Type

Package
Types

Page

ICS2407
ICS2409
ICS2439

IMI407, IMI409 and IMI439
Compatible.

6
9
9

2
2
2

18PinDIP,SOIC
24PinDIP,SSOP
24PinDIP,SSOP

369

ICS2492

Buffered XTAL Out.
Tristate PLL Outputs.

3

2

WPin
DIP,SOIC

375

ICS2494-244
ICS2494A-317

Buffered XTAL Out. Note: See Video
Dot Clock Section for Data.

3

2

WPin
DIP,SOIC

161

ICS2694

9 Fixed, CPU -CPU fl Selectable Provides
CPU, Co-Processor, Hard and Floppy
Disk, Kbd, Ser. Port, Bus Clk. Function.

11

2

24 Pin
DIP,SOIC

381

AV9107

CPU Clock Generator.

2

1

8 or 14 Pin
DIP,SOIC

387

ICS9108

3 Volt CPU Clock Generator.

2

1

8 or 14 Pin
DIP,SOIC

395

AV912819

Motherboard Frequency Generator
Outputs Kbd Clock, Systems Clock, 110
Clock, Comm. Clock and CPU Clock.

8/11

4

160rWPin
DIP,SOIC

403

ICS9131

32 kHz Input Generates CPU Clocks.

3

2

16 Pin
DIP,PDIP

417

ICS9132

32 kHz Input Generates all Motherboard
Clocks.

6

4

WPin
DIP,SOIC

425

ICS9133

32 kHz Input Generates CPU Clock and
System Clock and Two Fixed Clocks.

6

3

WPin
SOIC,PDIP

435

AV9140

R4000 Processor Series Master
Clock Generator.

1

1

8 Pin
DIP,SOIC

441

AV9154

Low Cost 16 Pin Clock Generator.
Generates CPU Clock, Keyboard Clock,
System Clock and 110 Clock.

7

2

16 Pin
DIP,SOIC

445

Motherboard Clock Generator.
Produces CPU Clock, Keyboard Clock,
System Clock and 1/0 Clock

8

WPin
DIP,SOIC

461

ICS9158

Clock Generator with Integrated Buffers.

11

2

24 Pin
SOIC

473

ICS2496-456

3Volt Operation, Buffered XTAL Out.
Note: See Video Dot Clock Section for
Data.

3

2

WPin
DIP, sOle

173

Clock Generator Designed Specifically
for use with OPT! Chipset.

4

16 Pin
DIP,SOIC

455

Motherboard

AV9155

Laptopl
Notebook

Features

Number Number
of
of
Outputs PLL's

AV9154-06/60

2

2

ADVANCE INFORMATION documents contain information on newproducts in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.
PRODUCT PREVmW documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

368

ICS2407
ICS2409
ICS2439
Product Preview

Integrated
Orcuit
Systems, Inc.

•

Dual-PLL Motherboard Frequency Generator

Description

Features

This ICS family of motherboard frequency generators all
stem from the same basic design. Theyare dual-PLL (phaselocked loop) clock generators specifically designed for
motherboard applications. Metal layer and assembly options are used to generate the three separate device types in
order to optimize the functionality for specific applications.
All frequencies are synthesized from a single reference
clock which may be generated by the on-chip crystal oscillator or an external reference clock.

•

The CPU clock PLL is ROM-programmed to generate any
of seven customer specified frequencies through selection
of the address lines SCLKO-SCLK2. In the ICS2409 and
ICS2439 versions the SCLK3 input selects those frequencies
directly or divided by two forthe CPUX2 output. The CPUX2
output is then divided by two to generate the CPUCLK
output. A power-down mode may be selected with the
SCLK inputs to reduce standby current consumption to a
few microamperes.

•
•
•
•
•
•
•
•
•

Supports 286, 386, & 486 desktop and notebook motherboard designs
Advanced ICS monolithic phase-locked loop technology for low short -term and "cumulative" jitter
Completely integrated - no external loop filter capacitors required
Dual-modulus prescaler permits high-speed operation
with no sacrifice in accuracy
Power-down mode for low standby power consumption
Low-skew between CPUX2 and CPUCLK outputs
«Insec)
3-volt supply capability to 85 MHz (CPUX2 output)
Output enable (OE- ) pin for tri-state of device outputs
ICS2409 and ICS2439 offer 24-pin PDIP (0.3'') and
24-pin SSOP (5.3mm) package options
ICS2407 offers 18-pin PDIP (0.3'') and 18-pin SOIC
(0.3'') package options

The auxiliary (AUX) PLL generates the fixed frequencies
shown in Table I for other system uses. A buffered reference
frequency output is available on the REFOUT pin. Two
non-dedicated buffers are provided on the ICS2439 and
ICS2409 for additional drive capability without adding external buffers and their board space.
ICS2407 Simplified Block Diagram
XTAL1
XTAL2

>---------7

REFOUT1

>---------7

REFOUT2

h-.------"7 CPUX2
CPUClK

AUX PLL (as above)

~24MHZ

~16MHZ
SClKQ
SClK1
SClK2

369

ICS2407
ICS2409
ICS2439
ICS2409 Simplified Block Diagram
XTALl
XTAL2

I-+--,--~

7159MHZ
SCLK3

CPUCLK

/3

32MHZ

/4

~

24MHZ

SCLKl
SCLK2

/6

16MHZ

AUX PLL (as above)

SCLKO

BUN

-------------'[>>--------.:::.)

Bl_0UT

--------~[»-------~

B2_0UT

)

ICS2439 Simplified Block Diagram
XTALl
XTAL2

1-7---.--REFOUT

SCLK3

CPUX2

CPUCLK

4

24MHZ

/6

~

16MHZ

SCLKl
SCLK2

/8

12MHZ

AUX PLL (as above)

SCLKO

BUN

-------------1[>>----------4)

Bl_0UT

-----------1[>

B2_0UT

)

370

ICS2407
ICS2409
ICS2439
Circuit Function and Application

Pin Description

Fixed Frequencies

Input Pins

The ICS motherboard family supplies "fixed" frequencies
normally used to provide several system functions:
•
•
•
•
•

Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be
connected between XTALl (1) and XTAL2 (2). In IBM
compatible applications this will typically be a l4.31SlS
MHz crystal.

32 MHz - ISA Bus Clock
24 MH z - Floppy Drives
16 MHz - AT Bus Clock Output
12 MHz - Keyboard Clock
7.149 MHz - Keyboard Clock

Digital Inputs
SCLKO, SCLKl, SCLK2 and SCLK3 (ICS2409, ICS2439
are the TTL compatible frequency select inputs for the
bmary code corresponding to the desired frequency. All
select pms have mternal pull-up devices built in (See Table 2
fora complete list of available frequencies).

Selectable CPU Clock Frequencies

o~ly)

The ICS2407, ICS2409 and ICS2439 are designed to generate CPU clock options ranging from 24MHz, to SSMHz. For
added flexibility, the ICS2409 and ICS2439 allow the user to
select each of these frequencies divided by 2.

Buffer Inputs (ICS2409 & ICS2439)

Buffered Output Pins

B LIN a.nd B2_IN (3, 7) provide additional buffering needed
on a typical board design without the added cost of external
components.

In addition, the ICS2409 and ICS2439 provide 2 non-dedicated buffers for additional flexibility. This allows for extra
drive capability without sacrificing the extra board space
required for external buffers.

Output Enable
An output enable pin OE- allows the user to tri-state the
d~vice outputs. When this pin is high, all outputs are in
tn-stat~ mode. When low, all outputs are enabled. This pin
has an mternal pull-down to enable all outputs when the pin
is N/C.

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS~39 provide the bus clock for the rest of the system. This
ehmmates the need for an additional14.3lSlS MHz crystal
oscillator on the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer REFOUT when using it to provide the system clock. On the
ICS2407, there are two identical outputs, REFOUTl and
REFOUT2.

Ordering Information
ICSXXXXM (SO Package)
ICSXXXXN (DIP Package)
ICSXXXXF (SSOP Package)

Power-Down Mode
All three devices have been optimized for use in battery
operated portables. It can be placed in a powerdown mode
which drops its supply current requirement below lIlA(typical).
ICS2407 Pinout
REFoun
VDD

N/C

(XXX = Pattern num ber)

ICS2409 Pmout

ICS2439 Pinout

"

XTALl

REFOUT

24

XTALl

REFOUT

17

XTAC2

SCOUT

23

XTAL2

81_0UT

23

"

Bl_IN

VDD

"

BUN

VDD

"

24

REFOUT2

16MHZ

15

VSS

N/C

21

N/c

21

SCLKO

24MHZ

14

7159MHZ

16MHZ

20

12MHZ

16MHZ

20

VSS

13

SCLKO

24MHZ

SCLKO

24MHZ

CPUX2

12

B2_IN

"

"

SCLK2

11

OE-

10

SCLKl

CPUCLK

32MHZ

"

B2_0UT

17

VSS

"

VDD

18

B2_0UT

17

VSS

16

SCLKl

CPUX2

15

SGLK2

14

SCLK3

SGlK2

OE-

13

CPUCLK

"

CPUX2

SCLK3

371

RESERVED

15

SCLKl

CPUCLK

B2_IN

N/C

OE-

13

ICS2407
ICS2409
ICS2439
Absolute Maximum Ratings
Supply Voltage .............
Input Voltage ..............
Output Voltage ... '" .......
Clamp Diode Current .......
Output Current per Pin ......
Operating Temperature .....
Storage temperature ........
Power Dissipation ..........

VDD ............ -O.SV to + 7V
VIN. . ........... -O.SV to VDD + O.SV
VOUT ........... -O.5V to VDD + O.SV
VrK & 10K ....... ± 30mA
lOUT ............ ± SOmA
To .............. O°C to 70°
Ts .............. -8SoC to 150°
PD .............. sOOm W

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation it is recommended that Yin and
Vout be constrained to > = Vss and < = VDD.

DC Characteristics at 5 Volts VDD
PARAMETER

SYMBOL

Operating Voltage Range

VDD

Input Low Voltage

VrL

Input High Voltage

CONDITIONS

MIN

MAX

UNITS

4.5

5.S

V

VDD= SV

Vss

0.8

V

VIH

VDD= SV

2.0

VDD

V

Input Leakage Current

IIH

VIN= VDD

-

10

Output Low Voltage

VOL

IOL= 1.2OmA

-

0.4

IlA
V

Output High Voltage

VOH

IOH= 1.2OmA

2.4

0

V

Supply Current

IDD

VCLK= 40MHz

-

40

rnA

Supply Current

IDD

VCLK= 88MHz

-

SO

rnA

Internal Pullup Current

Rup

VIN= O.OV

30

100

Internal Pulldown Current

RDOWN

VIN= O.OV

30

100

Input Pin Capacitance

CrN

Fc= IMHz

-

8

IlA
IlA
pF

Output Pin Capacitance

COUT

Fc= IMHz

-

12

pF

Powerdown Supply Currrent

IPN

VDD= 3.3V

-

I

IlA

372

ICS2407
ICS2409
ICS2439

II
DC Characteristics at 3.3 Volts Voo
MIN

MAX

UNITS

3.0

3.6

V

Voo= 3.3V

Vss

0.8

V

VIH

Voo= 3.3V

2.0

Voo

V

Input Leakage Current

IIH

VIN= Voo

-

10

Output Low Voltage

VOL

IOL= 8.OmA

-

0.4

IlA
V

Output High Voltage

PARAMETER

SYMBOL

Operating Voltage Range

Voo

Input Low Voltage

VIL

Input High Voltage

CONDITIONS

VOH

IOH= 8.OmA

2.4

0

V

Supply Current

100

CPUX2= 40MHz

-

35

rnA

Supply Current

100

CPUX2= 88MHz

-

25

rnA

Internal Pullup Current

Rup

VIN= O.OV

20

70

IlA

Internal Pulldown Current

ROOWN

VIN= O.OV

20

70

Input Pin Capacitance

CIN

Fc= IMHz

-

8

IlA
pF

Output Pin Capacitance

COUT

Fc= IMHz

-

12

pF

Powerdown Supply Currrent

IPN

Voo= 3.3V

-

1

IlA

AC Timing Characteristics
The following notes apply to all ofthe parameters presented in this section.
1. REFCLK = 14.31818 MHz
2. to = life
3. All units are in nanoseconds (ns)
4. Rise and fall time between.8 and 2.0 VDX unless otherwise stated.
5. Output pin loading = 15pF
6. Duty cycle measured at Vool2 unless otherwise stated

SYMBOL

PARAMETER

MIN

MAX

NOTES

OUTPUT TIMING @5v
Tr

Rise Time

-

Tf

Fall Time

-

2

-

Frequency Error

-

0.5

%

Tak

Clock Skew (CPUCLK & CPUX2)

-

1.0

nSec

-

Duty Cycle

45

55

%

-

Output Enable to Tri-State
(into and out of) time

-

15

nSec

2

OUTPUT TIMING @3.3v
Rise Time

-

Tf

Fall Time

-

3

-

Frequency Error

-

0.5

%

Tak

Clock Skew (CPUCLK & CPUX2)

-

1.5

nSec

-

Duty Cycle

45

55

%

-

Output Enable to Tri-State
(into and out of) time

-

20

nSec

Tr

373

3

ICS2407
ICS2409
ICS2439

II
Table 1: Fixed Output Frequencies

ICS2439

ICS2409

ICS2407

24MHz

32MHz

24MHz

16MHz

24 MHz

16MHz

12MHz

16MHz
7.159 MHz

Table 2: CPU Clock Frequency Selection
ICS2439

ICS2409

ICS2407

SCLK3

SCLK2

SCLKI

SCLKO

Pattern 001

Pattern 001

Pattern 407

0

0

0

0

12MHz

12MHz

12MHz

0

0

0

1

16

16

16

0

0

1

0

20

20

20

0

0

1

1

25

25

25

0

1

0

0

33.33

33.33

33.33

0

1

0

1

40

40

40

0

1

1

0

30

44

44

0

1

1

1

PowerDown

PowerDown

PowerDown

1

0

0

0

24

24

1

0

0

1

32

32

1

0

1

0

40

40

1

0

1

1

50

50

1

1

0

0

66.66

66.66

1

1

0

1

80

80

1

1

1

0

60

88

1

1

1

1

TEST

TEST

PRODUCT PREVIEW documents contain informatIOn on products In the formative or
deSign phase of development Charactenstlc data and other speCifications are deSign
goals les reserves the nght to change or discontinue these products Without notice

374

I~; fuw~too
Circuit

ICS2492

Systems, Inc.

CPU Clock Generator
Features

•
•
•
•
•
•
•
•

Low cost - eliminates need for mUltiple crystal clock
oscillators in motherboard applications
Mask-programmable frequencies
Pre-programmed versions for a selection of CPU clocks
Glitch-free frequency transitions
Provision for external frequency input
Internal clock remains locked when the external frequency input is selected
Low power CMOS device technology

•
•
•

Buffered Xtal Out
Integral Loop Filter components
Fast acquisition of selected frequencies, strobed or nonstrobed

•

Guaranteed performance up to 135 MHz

•

Excellent power supply rejection

•
•

Advanced PLL for low phase-jitter

Small footprint - 20 pin DIP or SO

Description

Output Enable function for tristate control of the two
clock outputs.

Pin Configuration

The ICS2492 CPU Clock Generator is an integrated circuit
dual phase locked loop frequency synthesizer capable of
generating 16 CPU frequencies and two other clockfrequencies for use with high performance personal computer motherboards. Utilizing CMOS technology to implement all
linear, digital and memory functions, the ICS2492 provides
a low-power, small footprint, low-cost solution to the generation of CPU clocks. Provision is made via a single level
custom mask to implement customer-specific frequency
sets. Phase-locked loop circuitry permits rapid glitch-free
transitions between clock frequencies.

XTALl

The ICS2492 is fully pin and function compatible with ICS'
industry-standard ICS2494 dual clock generator except that
an output enable function has been added to pin 11. A
pre-programmed version with a full selection of CPU clocks
is available as part number ICS2492-4S3. The frequencies
in this pattern are essentially identical to those in the
ICS2494-244 standard pattern.

20

DVDD

XTAL2

2

19

CPUCLK

EXTFREQ

3

18

XTALOUT

FSO

4

17

VSS

FSI

5

16

VSS

STROBE

6

15

AVDD

FS2

7

14

VSS

FS3

8

13

DVDD

MSO

9

12

BCLK

VSS

10

11

OUTEN

Notes:
1. In apphcatlOns where the external frequency mput IS not specIfied,
EXTFREQ must be tIed to Vss.
2. ICS2492M(SO) pmout IS Identical to ICS2492N(DIP).

375

(I

ICS2492
Power Supply Conditioning

Circuit and Application Options
The ICS2492 will typically derive its frequency reference
from a series-resonant crystal connected between pins I and
2. Where a high quality reference signal is available, such as
in an application where the graphics subsystem is resident
on the motherboard, this reference may directly replace the
crystal. This signal should be coupled to pin 1. If the reference signal amplitude is less than 3.5 volts, a .047 microfarad
capacitor should be used to couple the reference signal into
XTALI. Pin 2 must be left open.
The ICS2492 is capable of multiplexing an externally generated frequency source of VCLK via a mask option, in addition to its internally-generated clock.
This is input via EX1FREQ (3). When an external source is
selected, the PLL remains locked to the value specified in
the selected address. This provision facilitates the ability [Q
rapidly change frequencies. When this option is not specified in the ROM pattern, pin 3 is internally tied to Vss and
should be connected to Vss on the PCB.

The ICS2492 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and
noise-free power supplyis available, no external components
are required. However, in most applications it is judicious to
decouple the power supply as shown in Figures I or 2. Figure
1 is the normal configuration for 5 Volt only applications.
Which of the two provides superior performance depends
on the noise content of the power supplies. In general, the
configuration of Figure 1 is satisfactory. Figure 2 is the more
conventional if a 12 Volt analog supply is available, although
the improved performance comes at a cost of an extra component; however, the cost of the discretes used in Figure 2 is
less than the cost of Figure l's discrete components.
The number and differentiation of the analog and digital
supply pins are intended for maximum performance products. In most applications, all VDDS may be tied together.
The function of the multiple pins is to allow the user to realize
the maximum performance from the silicon with a minimum
degradation due to the package and PCB. At the frequencies
of interest, the effects of the inductance of the bond wires
and package lead frame are non-trivial. Byusing the multiple
pins, ICS has minimized the effect of packaging and has
minimized the interaction of the digital and analog supply
currents.

22
A

~3~2

r-11P'

20
19
18

~

4

FSO '"
FS1
,....
STROBE
,....
FS2
FS3 '"
MSO

9

17
16
15
14
13
12

10

11

~

5

6
7
8

ICS2492

~

-

'--

Figure 1

376

¥2

'~

5.0V

.(') VCLK
-l"\ XTALO UT

..() MCLK
-() MS 1

II

ICS2492
different motherboard designs. As the quality of this signal
is typically outside of the control of the graphics adapter
card manufacturer, it is suggested that this signal be buffered on the graphics adapter board. XTAL2 (2) must be left
open in this configuration.

Applications
Layout Considerations
Utilizing the ICS2492 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions
in board layout if satisfactory jitter-free performance is to
be realized. Care should be exercised in ensuring that components not related to the ICS2492 do not share its ground.
In applications utilizing a multi-layer board, Vss should be
directly connected to the ground plane. Multiple pins are
utilized for all analog and digital Vss and Vdd connections
to permit extended frequency VCLK operation to 135 MH z.
However, in all cases, all Vss and VDD pins should be
connected.

Buffered XTALOUT
In motherboard applications it maybe desirable to have the
ICS2492 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
To do this, the XTALOUT (18) output should be buffered
with a CMOS driver.

Output Circuit Considerations
As the dot clock is usually the highest frequency present in
a video graphics system, consideration should be given to
EM!. To minimize problems with meeting FCC EMI requirements, the trace which connects VCLK (19) or MCLK
(12) and other components in the system should be kept as
short as possible. The ICS2492 outputs have been designed
to minimize overshoot. In addition, it may be helpful to place
a ferrite bead in these signal paths to limit the propagation
of high order harmonics of this signal. A suitable device
would be a Ferroxcube 56-590-65/4B or equivalent. This
device should be placed physically close to the ICS2492. A
33 to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary to reduce ringing and
reflection of the signal and may reduce phase-jitter as well
as EM!.

Figure 2
S.OV

~I

rllR

19

,.--2
FSO

17

FSl
STROBE
FS2
FS3

5

16

ICS2492

7
8

9

MSO

VCLK

18

4
6

1

~

~

XTALOU T

m

15
14

~
12

11

~2
1

£',

RI

12.DV

-=47V

MCLK
MS1

External Frequency Sources
-

Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal should be connected between XTALI (1) and XTAL2 (2).
In IBM-compatible applications this will typically be a
14.31818 MHz crystal, but fundamental mode crystals between IOMHz and 25MHz have been tested. Maintain short
lead lengths between the crystal and the ICS2492. In some
applications, it may be desirable to utilize the bus clock. If
the signal amplitude is equal to or greater than 3.5 volts, it
rna y be connected directly to XTALI (1). If the signal amp litude is less than 3.5 volts, connect the clock through a .047
microfarad capacitor to XTALI (1), and keep the lead length
of the capacitor to XTALI (1) to a minimum to reduce noise
susceptibility. This input is internally biased at VDDI 2. Since
TTL compatible clocks typically exhibit a VOH of 3.5V,
capacitivelycoupling the input restores noise immunity. The
ICS2492 is not sensitive to the duty cycle of the bus clock;
however, the quality of this signal varies considerably with

EXTFREQ (3) on versions so equipped by the programming, is an input to a digital multiplexer. When this input is
enabled, signals driving the input will appear at VCLK (19)
instead of the PLL output. Internally, the PLL will remain
in lock at the frequency selected by the ROM code.

Digital Inputs
FSO (4), FS1 (5), FS2 (7), and FS3 (8), are the TTL
compatible frequency select inputs for the binary code corresponding to the frequency desired. STROBE (6), when
high, allows new data into the frequency select latches; and
when low, prevents address changes per Figure 3. The internal power-on-clear signal will force an initial frequency code
corresponding to an all-zeros input state. MSO (9) and MSI
(ll)are the corresponding memory select inputs and are not
strobed.

377

ICS2492
Absolute Maximum Ratings
Supply Voltage
Input Voltage .
Output Voltage
Clamp Diode Current
Output Current per Pin
Operating Temperature
Storage Temperature.
Power Dissipation ...

.VDD
.VIN .
· Your
· VIK& 10K

. lour
· To
.Ts
.. PD

-O.5V to + 7V
-O.5V to VDD+ O.SV
-O.5V to VDD+ O.SV
+ / -30mA
+ / -SOmA
o DC to 70 DC
-8S DC to + ISO DC
SOOmW

Values beyond these ratings maydamage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and
Your be constrained to > = Vss and < = VDD

DC Characteristics (O DC to 70 DC)
SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNITS

VDD

Operating Voltage Range

4.0

S.S

V

Vss
2.0

0.8

V

VDD = SV

VDD

V

VDD = SV

uA
V

VIN= Vee
IOL= 4.0mA

VIL

InllUt Low Voltage

VIH

Input High Voltage

IIH

Input Leakage Current

-

10

VOL

Output Low Voltage

-

0.4

VOH

Output High Voltage

2.4

-

V

IOH = 4.0mA

IDD

Supply Current

-

27

rnA

VDD = SV, VCLK = 80
MHz
Vdd = SV, Vm = OV

Rup *
Cm

Internal Pullup Resistors

SO

200

Input Pin Capacitance

-

8

KOhm
pF

C~uJ

Output Pin Capacitance

-

12

pF

* The following inputs have pullups: FSO-3, MSO-l, STROBE.

378

Fe = IMHz
Fe = 1MHz

ICS2492
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
l.XtalFrequency= 14.31S18MHz
2. Te = liFe
3. All units are in nanoseconds (ns).
4. Rise and fall time is between O.S and 2.0 VDC.
5. Output pin loading = 25pF
6. Duty cycle is measured at I.4V.
7. Supply Voltage Range = 4.0 to 5.5 Volts
S. Temperature Range = 0 DC to 70 DC

SYMBOL

PARAMETER

MIN

MAX

NOTES

STROBE TIMING
Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency

20

-

10
10

MCLK AND VCLK TIMINGS
Tf
-

-

-

Tpw

STROBE

FSO- FS]

3
3
0.5
135
15

-

!

~

}
>:<
t-

Tsu

-i-

Figure 3

379

Thd

>:<
--t

Duty Cycle 40% min. to
60% max.
%
MHz
ns

380

I!;

Integra~
Circuit

ICS2694

Systems, Inc.

Motherboard Clock Generator
Features

Applications

•

•
•
•
•
•
•

•
•
•
•
•
•
•
•

Low cost - eliminates multiple oscillators and Count
Down Logic
Primary VCO has 16 Mask Programmable frequencies
(normally CPU clock)
Secondary VCO has I Mask Programmable frequency
(usually 96 MHz)
Pre-programmed Versions for typical PC applications
10 Outputs in addition to the Primary CPU clock
Capability to reconfigure counter stages to change the
frequencies of the outputs via mask options
Advanced PLL design
On chip PLL filters
Very Flexible Architecture

Description
The ICS2694 Motherboard Clock Generator is an in-tegrated
circuit using PLL and VCO technology to generate virtually
all the clock signals required in a PC. The use of the device can
be generalized to satisfy the timing needs of most digital
systems by reprogramming the VCO or reconfiguring the
counter stages which derive the output frequencies from the
VCO's.

CPU clock and Co-processor clock
Hard Disk and Floppy Disk clock
Keyboard clock
Serial Port clock
Bus clock
System counting or timing functions

Pin Configuration

OUT2

01

24

OUT3

OUTI

02

23

OUT4

OUTO

o3

22

OUTS

21

OUT6

20

oun (CPUCLKl2)

CPUCLK

o4
o5

VSS

06

19

OUT8

DVDD

07

18

AVDD

17

XTAL2

16

XTALI

OUT9

STROBE
CPUSELO

The primary VCO is customarily used to generate the CPU
clock and is so labeled on the ICS2694. Pre-programmed
frequency sets are listed on page 6. These choices were made
to match the major microprocessor families. CPUSEL (0-3)
allow the user to select the appropriate frequency for the
application.
Due to the filter in the phase-locked loop, the CPUCLK will
move in a linear fashion from one frequency to a newlyselected frequency without glitches. If a fixed CPUCLK value
is desired, CPUSEL (0-3) may be hard wired to the desired
address with STROBE tied high. (It has a pullup.) For board
test and debug, pulling OUTPUTE to Ground will tristate all
the outputs.

381

o8
o9

CPUSELI

0

10

15

AVSS

CPUSEL2

o II

14

OUTPUTE

CPUSEL3

0

12

13

CLKIN

Ordering Information

ICS2694N-XXX (DIP Package)
ICS2694M-XXX (SO Package)
(XXX - Pattern number)

ICS2694
Pin Description
PIN NUMBER
1
2
3
4
5

NAME
OUT2
OUTl
OUTO
OUT9
CPUCLK

6
7
8

VSS
DVDD
STROBE

9
10
11
12
13

CPUSELO
CPUSELl
CPUSEL2
CPUSEL3
CLKIN

14
15
16
17

OUTPUTE
AVSS
XTALl
XTAL2

18
19
20
21
22
23
24

AVDD
OUT8
OUT7
OUT6
OUTS
OUT4
OUB

DESCRIPTION
4mAOutput
4mAOutput
4mAOutput
4mAOutput
4mA Output driven by Voltage Controlled Oscillator 1 (VCOl). VCOI is controlled
bva 16 word ROM.
Ground for digital portion of chip
Plus supply for digital portion of chip
Input control for transparent latches associated with CPU (0-3) which select one of
16 values for CPUCLK. Holding STROBE high causes the latches to be transparent.
LSB CPUCLK address bit
CPUCLK address bit
CPUCLK address bit
MSB CPUCLK address bit
An alternative input for the reference clock. The crystal oscillator output and CLKIN
are gated together to generate the reference clock for the VCO's. If CLKIN is used,
XTAL 1 should be held high and XTAL2 left open. If the internal oscillator is used,
hold CLKIN high.
Pulling this line low tristates all outputs.
Ground for analog portion of chip
Input of internal crystal oscillator stage
Output of internal crystal oscillator stage. This pin should have nothing connected
to it but one of the quartz crystal terminals.
Positive supply for analog portion of chip.
4mAOutput
4mA Output (Usually assigned as CPUCLKl2 for co-processor use)
4mAOutput
4mAOutput
4mAOutput
4mAOutput
-~-

382

ICS2694
Frequency Reference

Power Supply Conditioning

The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTALI (I) and XTAL2 (2). In
IBM-compatible applications, this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the ICS2694. In order to optimize the
quality of the quartz crystal oscillator, the input switching
threshold of XTALI is VDD/2 rather than the conventional 1.4
V of TTL. Therefore, XTALI may not respond properly to a
legal TTL signal since TTL is not required to exceed VDDI2.
Therefore, another clock input CLKIN (pin 13) has been added
to the chip which is sized to have an input switching point of
1.4 V. Inside the chip, these two inputs are ANDED. Therefore,
when using the XTALI and XTAL2, CLKIN should be held
high. (It has a pullup.) When using CLKIN, XTALI should be
held high. (It does not have a pullup because a pullup would
interfere with the oscillator bias.)

The ICS2694 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in some applications it may be judicious to
decouple the power supply as shown in Figures I or 2. Figure
I is the normal configuration for 5 Volt only applications.
Which of the two provides superior performance depends on
the noise content of the power supplies. In general, the configuration of Figure I is satisfactory. Figure 2 is the more
conventional if a 12 Volt analog supply is available, although
the improved performance comes at a cost of an extra component; however, the cost of the discretes used in Figure 2 are less
than the cost of Figure I's discrete components.

It is anticipated that some applications will use both clock

inputs, properly gated, for either board test or unique system
functions. By generating all the system clocks from one reference input, the phase and delay relationships between the
various outputs will remain relatively fixed, thereby eliminating problems arising from totally unsynchronized clocks interacting in a system.

+5

C1

Since the ICS2694 outputs a large number of high-frequency
clocks, conservative design practices are recommended. Care
should be exercised in the board layout of supply and ground
traces, and adequate power supply decoupling capacitors consistent with the application should be used.

+50

C1

DVDD

lll!F

+5

33
R1

C2

C3

121!111lF

I11!F

AVDD
VSS, AVSS

+120

470
R1

Figure 2

Figure 1

383

DVDD

ICS2694
Absolute Maximum Ratings
Supply Voltage ................
Input Voltage ..................
Output Voltage ................
Clamp Diode Current ...........
Output Current per Pin ..........
Operating Temperature ..........
Storage Temperature ............
Power Dissipation ..............

VDD. . . . . . . . . . ..
VIN . . . . . . . . . . ..
VOUT. . . . . . . . ..
VIK & 10K. . . . . ..
lOUT ...........
To .............
Ts . . . . . . . . . . . ..
PD . . . . . . . . . . . ..

-O.SV to + 7V
-O.SV to VDD +O.5V
-O.SV to VDD +O.SV
+/-30mA
+/-SOmA
0 °c to + ISO °c
-8S °c to + ISO °c
SOOmW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be
constrained to > = Vss and < = VDD.

DC Characteristics (0 °C to 70°C)
SYMBOL
VDD
VIL
VIH
IIH
VOL
VOH
IDD
Rup *
Cin
COUI

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Supply Current
Internal Pullup Resistors
Input Pin Capacitance
Output Pin Capacitance

* The following inputs have pullups:

MIN
4.0

MAX

Vss
2.0

0.8
VDD
10
0.4

-

S.S

2.4

-

-

SS

SO

-

-

8
12

-

UNITS
V
V
V
uA
V
V
mA
KOhm
pF
pF

OUTPUTE, STROBE, CPUSEL (0-3), CLKIN.

384

CONDITIONS
II

VDD=5V
VDD=SV
VIN = Vee
IOL=4.0mA
IOH=4.0mA
VDD = SV, CPUCLK = 80 MHz
VDD = SY, Vm = OV
Fe = 1 MHz
Fc = 1 MHz

II

ICS2694

AC Timing Characteristics
The following notes apply to all parameters presented in this section:
1.
2.
3.
4.
5.
6.
7.

Xtal Frequency = 14.31818 MHz
All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = 15pF
Duty cycle is measured at l.4V.
Supply Voltage Range = 4.5 to 5.5 Volts
Temperature Range = 0 DC to 70 DC

SYMBOL

PARAMETER

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf
-

Rise Time
Fall Time
Frequency Error
Maximum Frequency

MIN
STROBE TIMING
20
10
10
FOUTTIMING
-

Note:
Pattern -004 has rising edges of CPUCLK and CPUCLKl2 matched to ± 2 ns.

385

MAX

NOTES

-

-

3
3
0.5
135

Duty Cycle 40% min. to 60% max.
at 80 MHz
%
MHz

ICS2694
ICS2694 Standard Patterns
32 MHz
1.846 MHz
24 MHz
6 MHz

D1

a
a
a

24

16 MHz

2

23

8 MHz

3

22

9.6 MHz

4

21

14.318 MHz

20

CPUCLKl2

CPUCLK
VSS
DVDD
STROBE
CPUSELO
CPUSELI
CPUSEL2
CPUSEL3

a
a
a
a
a
a
a

6

19

1.19 MHz

7

18

AVDD

8

17

XTAL2

9

16

XTALI

10

15

AVSS

11

14

OUTPUTE

12

13

CLKlN

Another alternative for CPU CLOCK generation is the
ICS2494-244 if the additional functions of the ICS2694 are
not needed in the application.

ICS Part Number

E
F

ICS2494244
Frequency
(MHz)
20
24
32
40
50
66.6
80
100
54
70
90
110
25
33.3
40
50

Address MS 1-0
(Hex)
0
1
2
3

Frequency
(MHz)
16
24
50
66.6

Address FS3-0
(Hex)
0
1
2
3
4
5
6
7
8
9
0

ICS2694-004

B

CPUSELO-3
(Hex)
0
1
2
3
4
5
6
7
8
9
10
11

12
13
14
15

C

CPUCLK OUTPUT (Pin 5)
(MHz)
2
10
20
24
25
32
33.33
40
48
50
54
66.67
68
80
100
16

D

Note:
Pattern -004 has rising edges of CPUCLK and CPUCLKl2
matched to ± 2 ns.

386

AV91 07

Integrated
Circuit
Systems, Inc.

•

CPU Frequency Generator
Features

Applications

• Patented on-chip Phase Locked Loop with VCO
for clock generation
• Provides reference clock and synthesized clock
• Generates frequencies from 2 to 120 MHz
• 2 to 32 MHz input reference frequency
• On chip loop filter
• Up to 16 frequencies stored internally
• Low power CMOS technology
• Single +3.3 or +5 volt power supply
• Runs up to 50 MHz at 3.3V
• 8 pin DIP or SOIC package or
14 pin DIP or SOIC package

Graphics: The AV9107 is the easiest to use, lowest cost,
and smallest footprint frequency generator for graphics
applications. It can generate up to 16 different frequencies, including all frequencies necessary for VGA standards. It should be used in place of the AV9105 / 6 when
the reference clock is also needed.
Computer: The AV9107 is the ideal solution forreplacing
high speed oscillators and for reducing clock speeds to
save power in computers. The device provides smooth,
glitch-free frequency transitions so that the CPU can
continue to operate during slow down or speed up. The
rate of frequency change makes the AV9107 compatible
with all 386DX, 386SX, 486DX, 486DX2, and 486SX devices. Standard versions include the AV9107-03, -04, -05
and -10.

General Description

Disk Drives: Smaller than a single crystal or an oscillator, the tiny sorc package can be used for any general
purpose frequency generation in disk drives. The most
popular application is for Constant Density Recording,
where its low jitter output clock provides the necessary
frequencies for reading and recording. Another popular
application is for slowing the disk drive CPU to save
power.

The AV9107 offers a tiny footprint solution for generating
two simultaneous clocks. One clock, the REFCLK, is a fixed
output frequency which is the same as the input reference
crystal (or clock). The other clock, CLK1, can vary between
2 and 120 MHz, with up to 16 selectable preprogrammed
frequencies stored in internal ROM.
The device has advanced features which include on-chip
loop filters, tri-state outputs, and power down capability.
A minimum of external components - two decoupling
capacitors and an optional ferrite bead - are all that are
required for jitter free operation. Standard versions for
computer motherboard applications are the AV9107-03,
AV9107-04, AV9107-05 and AV9107-1O. Custom masked
versions, with customized frequencies and features, are
available in 6-8 weeks for a small NRE.

High Speed Systems: The AV9107 can be used as a
proximity oscillator - using a low frequency (down to 2
MHz) input to generate a high frequency clock (up to 120
MHz) near the device requiring the high frequency. This
avoids the need to route high speed traces over a long
distance.

Block Dia ram
~~%~ ~-

- - - - - - - - - - - -- - - - - - - - - - - -I
elKlor

I
I

2XCPUCLK

-+__

L -_ _

FSO--+--~

FSl--t--+i
FS2--r--~

FS3--+--+!

FREQUENCY STOREI
PHASE LOCK LOOP
CONrROL LOGIC

, - - - - 1 - - OE

I
-+~~!I
t
I
XllICLK
~I~SCILLATORI-I---------~~Q
~~
i_
X2 4:
: .
~

ENABLE--t--~L-.-_ _ _ _ _ _ _ _ _J

________________________ J

387

OE

REFCLK
orCPUCLK

AV91 07

o
o

o

40 MHz
50 MHz
66.6 MHz
80 MHz

1

1

o

1

1

FS1
0
0
1
1

Decoding Table for AV91 07-03, 14.318 input
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

-

Decod'Ina lia bl e for AV910710" 14318'InDUt

FS1

FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

FSO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

FSO
0
1
0
1

CLK1
25 MHz
33.3 MHz
40 MHz
50 MHz

Pin Configurations

CLK1
16 MHz
40 MHz
50 MHz
80 MHz
66.66 MHz
100 MHz
8 MHz
4 MHz
8 MHz
20 MHz
25 MHz
40 MHz
33.33 MHz
50 MHz
4 MHz
2 MHz

FSO
REFCLK
VDD
CLK1
OE (CLK1)
OE(REFCLK)
X2

FS1
FS2
FS3
AGND
GND
PD*
X1/ICLK
AV9107-o3

FSO u 8
GND 2
7
XI/ICLK 3
6
X2 4
5

REFCLK
VDD
CLKI
PSI

A V9107-05/-10

Pin Descriction for AV91 [)7-03. AV91 07-05 and AV91 07-1 0
Pin Name
FSO
FS1
FS2
FS3
AGND
GND
PD*
X1/ICLK
X2

2
3
4

OE(REFCLK)
OE(CLKl)
CLK1
VDD
REFCLK

Pin Type Description

Pin #
-05/-10
1
5

6
7
8

-03
14
1
2
3
4
5
6
7
8
9
10
11
12
13

Input
Input
Input
Input

-

Input
Input
Output
Input
Input
Output

Output

FREQUENCY SELECT 0 for CLK1 (-03 has pull-up)
FREQUENCY SELECT 1 for CLK1 (-03 has pull-up)
FREQUENCY SELECT 2 for CLK1 (-03 has pull-up)
FREQUENCY SELECT 3 for CLK1 (-03 has pull-up)
Analog GROUND
Digital GROUND
POWER DOWN. Shuts off chip when low. Internal pull-up
CRYSTAL INPUT or INPUT CLOCK frequency. Typically
14.318MHz system clock
CRYSTAL OUTPUT (No Connect when clock used)
OUTPUT ENABLE. Tri-states REFCLK when low. Pull-up
OUTPUT ENABLE. Tri-states CLK1 when low. Pull-up
CLOCK1 Output (see decoding tables)
Digital power supply (+5V DC)
REFERENCE CLOCK output. Produces a buffered version
of the input clock or crystal frequency (typically 14.318 MHz)

388

II .~~~
AV91 07
The AV91 07-04
The AV9107-04 provides a 2X output and a IX output,
which are skew controlled to within Ins on the rising
edges. For the frequencies listed in the decoding tables,
the part assumes a 14.318 MHz input. The device is also
useful for providing integer multiples or divides based on
inputs in the range of 2 to 32 MHz.

Pin Confi uration
FSO

FSI
FS2
FS3

CPUCLK

VDD

AGND
GND

2XCPUCLK
OE (2XCPUCLK)
OE(CPUCLK)
X2

PD*
Xl/ICLK

AV9107-04
14 pin DIP, SOIC

Decoding Table for AV91 07-04
(using a 14.318 MHz input)
FS3 PS2 FSI PSO
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
0
1
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1

2XCPUCLK
80 MHz
66.66 MHz
50 MHz
40 MHz
100 MHz
33.33 MHz
32 MHz
25 MHz
64 MHz
2XINPUT
3XINPUT
8XINPUT
.5XINPUT
.25XINPUT
120 MHz
130 MHz

CPUCLK
40 MHz
33.33 MHz
25 MHz
20 MHz
50 MHz
16.67 MHz
16 MHz
12.5 MHz
32 MHz
INPUT
1.5X INPUT
4XINPUT
.25XINPUT
.125XINPUT
60 MHz
65 MHz

-

p.In DescrlDllon
· f for AV91 07 04
Pin
Name

Pin #

FSI
FS2
FS3
AGND
GND
PD*
Xl/ICLK

1
2
3
4
5
6
7

Input
Input
Input

X2
OE(CPUCLK)
OE(2XCPUCLK)

8
9
10
11
12
13
14

Output
Input
Input
Output

2XCPUCLK
VDD
CPUCLK
FSO

Pin Type Description

-

Input
Input

-

Output
Input

FREQUENCY SELECT 1 (see decoding table). Pull-up
FREQUENCY SELECT 2 (see decoding table). Pull-up
FREQUENCY SELECT 3 (see decoding table). Pull-up
Analog GROUND
Digital GROUND
POWER DOWN. Shuts off entire chip when low. Pull-up
CRYSTAL INPUT or INPUT CLOCK frequency. Typically
14.318MHz system clock
CRYSTAL OUTPUT (No Connect when clock used)
OUTPUT ENABLE. Tri-states CPUCLK when low. Pull-up
OUTPUT ENABLE. Tri-states 2XCPUCLK when low. Pull-up
2X CPU CLOCK Output (see decoding table, note t below)
Digital power supply (+5V DC)
CPU CLOCK Output (see decoding table, note t below)
FREQUENCY SELECT 0 (see decoding table). Pull-up

'The CPUCLK and 2XCPUCLK outputs are skew controlled to within 1.0 ns max

389

AV91 07
Frequency Accuracy and
Calculation

Allowable Input and Output
Frequencies

The accuracy of the frequencies produced by the AV9107
depends on the input frequency and the desired actual
output frequency. The formula for calculating the exact
output frequency is as follows:

The input frequency should be between 2 and 32 MHz
and the AlB ratio should not exceed 24. The output
should fall in the range of 2-120 MHz.

A
Output Frequency = Input Frequency x B
where A = 2, 3, 4... 128, and
B = 2, 3, 4... 32.
For example, to calculate the actual output frequency for
a video monitor expecting a 44.900 MHz clock and using
a 14.318 MHz input clock, the closest AlB ratio is 69/22,
which gives an output of 44.906 MHz (within 0.02% of
the target frequency). Generally, the AV9107 can produce frequencies within 0.1 % of the desired output.

Output Enable
The Output Enable feature tri-states the specified output
clock pins. This places the selected output pins in a high
impedance state to allow for system level diagnostic
testing.

Power Down
If equipped, the power down pin shuts off the specified

PLL or entire chip to save current. A few milliseconds are
required to reach full functioning speed from a power
downstate.

Frequency Transitions
A key A V9107 feature is the ability to provide glitch-free frequency transitions across its output frequency range. The
AV9107-03 provides smooth transitions between any of the two groups of eight frequencies (when FS3=0 or FS3=1),
so that the device will switch glitch-free between 4 - 100 MHz and 2 - 50 MHz.

390

•

AV91 07

ABSOLUTE MAXIMUM RATINGS
Voltage on I/O pins referenced to eND ...... eND -O.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

AVDD, VDD referenced to eND ................................. 7V
Operating temperature under bias ............. O°C to +70°C
Storage temperature ................................ -65°C to +150°C

Note: Stresses above those listed under Absolute Maximum RatIngs may cause permanent damage to the deVIce ThIs IS a stress ratIng only, and
functional operalIon of the devices at these or any other condIlIons above those indIcated In the operatIOnal seclIons of thIS specification is not
imphed. Exposure to absolute maXImum conditIOns for extended periods may affect the rehabIhty of the device.

ELECTRICAL CHARACTERISTICS AT 5V
(Operating V DD = +4.5V to +5.5V, TA = O°C to 70°C unless otherwise stated)
Parameter
Symbol
Min Typ Max Units Conditions
DC CHARACTERISTICS
VIL
VIH
IlL
I

~L

VOH

~D
d

C
C'L
IDDSTDBY

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current
Output Frequency Change
over Supply and Temperature
Input Capacitance
Load Capacitance
Standby Supply Current

-

-

0.8

2.0

-

-

-

2.4
-

-

-

10
0.002

-5
5
0.4
-

20
0.05
10

20
25

V
V
llA
llA
V
V
rnA
%
pF
pF
llA

VDD = 5V
VDD =5V
VIN=OV
VIN=~
I =8
IOL = -4mA
!-rate 1
With respect to
typical frequency
ExcelXt Xl, X2
Pins 1, X2
Note 2

ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
%
%
%
ms
ms
ns

25 pfload
25 pfload
25 pfload
25 pfload
151/ load
Al frequencies
All frequencies
From 50 to 4 MHz
From off to 100MHz
AV9107-04

AC CHARACTERISTICS
tw
t

t

U

t

rtLK
ICLK;
thd
t,
t
t;

JTt
IPS
Jabs

tft
t

t ek
U

Enable pulse width
Setup time data to enable
Output Frequency
Input Frequency
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V
Output Fall time, 2.0 to Ci':SV
Fall time, 80% to 20% VDD
Dutycyde
Jitter, 1 sigma
Jitter, absolute
Frequency Transition time
Power up time
Clock skew between CPUCLK
and 2XCPUCLK outputs

20
20
2
2
-

10

-

14.318
-

-

1
2
1

40

50/50
±0.5
±3

-

15
±0.5

-

120
32
20
20
-

2
4
2
4
60
±2
±5
20
30
±1.0

Note 1: AV9107-03 with no load, with 14.318 MHz crystal input, and CLK1 running at 40 MHz. Power supply
current varies with frequency. Consult A vasem for actual current at different frequencies.
Note 2: AV9107-03 with the power down pin low (active).
Note 3: To guarantee operation at 100 MHz or above, please indicate the highest speed used when ordering. For
example, if 120 MHz would be used on the AV9107-04CS14, order it as AV9107-04CS14-120.

391

II [~~~
V9107

Electrical Characteristics at 3.3V
(Operating VDD = +3.0V to +3.7V, TA

Symbol

= O°C to 70°C unless otherwise stated)

Parameter

Min

Typ

Max

Units Conditions

DC CHARACTERISTICS
VlL
VIH
IlL
I

~L
V

OH

~o
d

C
C'L
IODSIDBY

Input Low Voltage
- 0.15Voo
Input High Voltage
O· 7Voo
-5
Input Low Current
Input High Current
5
0.1
Output Low Voltage
Output High Voltage
Voo-·1V
Supply Current
8
15
0.002
0.01
Output Frequency Change
over Supply and Temperature
Input Capacitance
10
Load Capacitance
20
Supply Current, Standby
15

V
V
JlA

JlA

V
V
rnA
%
pF
pF

JlA

VIN=OV
VIN=~
I =8
IOL =-4mA
mte1
With respect to
typical frequency
Excext Xl, X2
Pins 1, X2
When powered down

AC CHARACTERISTICS
t
(
ItLK
ICLK;
thd
t,

j
r"
T'

Jabs

tft
t

t
(

U

Enable pulse width
Setup time data to enable
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Rise time
Fall time
Dutycyc1e
Jitter, 1 sigma
Jitter, absolute
Frequency Transition time
Power u£ time
Output requency
Input Frequency

20
20

-

-

-

10

-

20
20

-

4
4
60

-

-

-

40

-

-

SO/50
±0.5
±3

-

±2

±5
20

15
2
2

14.318

80
32

ns
ns
ns
ns
ns
ns
ns
%
%
%
ms
ms
MHz
MHz

15 pfload
15 pfload
15!Jf load
A frequencies
All frequencies
From 2 to 25 MHz
From off to 66.66 MHz

Note 1: AV9107-03 with no load, with 14.318 MHz crystal input, and CLK1 running at 40 MHz. Power supply
current varies with frequency. Consult ICS for actual current at different frequencies.
Note 2: To guarantee 3V operation, please specify the AV9107-xxCxxx-3V when ordering.

392

AV91 07

Actual Frequencies
Decoding Table for AV91 07-04,14.318 input

Decoding Table for AV91 07-05,14.318 input
FSI
0
0
1
1

FSO
0
1
0
1

FS3 FS2 FSI FSO
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1

CLKI
40.01 MHz
SO.l1 MHz
66.61 MHz
80m MHz

Decoding Table for AV91 07-03, 14.318 input
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

FSI
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

FSO
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1

CLKI
16.00 MHz
39.99 MHz
SO.l1 MHz
80m MHz
66.58 MHz
100.23 MHz
8.02 MHz
4.01 MHz
8.02 MHz
20.00 MHz
2S.06 MHz
40.01 MHz
33.29 MHz
S0.11 MHz
4.01 MHz
2.0SMHz

Decoding Table for AV91 07-10, 14.318 input
FSI
0
0
1
1

FSO
0
1
0
1

CLKI
2S.0S7MHz
33.289 MHz
40.006 MHz
SO.113 MHz

393

2XCPUCLK
80.D2 MHz
66.62 MHz
S0.11 MHz
40.01 MHz
100.23 MHz
33.31 MHz
32.01 MHz
2S.06MHz
64.02 MHz
2XINPUT
3XINPUT
8XINPUT
.SXINPUT
.2SXINPUT
120.00 MHz
129.96 MHz

CPUCLK
40.01 MHz
33.31 MHz
2S.06MHz
20.00 MHz
SO.11 MHz
16.66 MHz
16.00 MHz
12.47 MHz
32.01 MHz
IX INPUT
I.5X INPUT
4XINPUT
.2SXINPUT
.12SXINPUT
60.00 MHz
64.98 MHz

AV91 07
r erma Inorma
f
f Ion
Od
Part Number
AV9107-xxCNS
AV9107-xxCSS
AV9107-xxCN14
AV9107-xxCS14

Temperature Range
O°C
O°C
O°C
O°C

Package Type
S lead Plastic DIP (300 mils)
S lead SOlC (150 mils)
14 lead Plastic DIP (300 mils)
14 lead SOlC (150 mils)

to +70°C
to +70°C
to +70°C
to +70°C

394

ICS9108

Integrated
Circuit
Systems, Inc.

•

Advance Information

CPU Frequency Generator
Features

General Description

• 3V version of popular ICS9107
• Runs up to 66 MHz at 3.3V
• 50/50 typical duty cycle
• ±250 psec absolute jitter
• Generates frequencies from 2 to 140 MHz
• 2 to 32 MHz input reference frequency
• Up to 16 frequencies stored internally
• Patented on-chip Phase Locked Loop with VCO
for clock generation
• Provides reference clock and synthesized clock
• On chip loop filter
• Low power 0.8 11 CMOS technology
• 8 pin or 14 pin DIP or SOIC package

The ICS91 08 offers a tiny footprint solution for generating
two simultaneous clocks. One clock, the REFCLK, is a
fixed output frequency which is the same as the input
reference crystal (or clock). The other clock, CLK1, can
vary between 2 and 140 MHz, with up to 16 selectable
preprogrammed frequencies stored in internal ROM.
The ICS9108 is ideal for use in a 3.3V system. It can
generate a 66.66 MHz clock at 3.3V. In addition, the
ICS9108 provides a symmetrical wave form with a worst
case duty cycle of 45/55. The ICS9108-04 has very tight
edge control between the CPU clock and 2XCPU clock
outputs, with a worst case skew of 250 psec.
The device has advanced features which include on-chip
loop filters, tri-state outputs, and power down capability.
A minimum of external components - two decoupling
capacitors and an optional ferrite bead - are all that are
required for jitter free operation. Standard versions for
computer motherboard applications are the ICS9108-03,
ICS9108-04, ICS9108-05, and the ICS9108-1O. Custom
masked versions, with customized frequencies and
features, are available in 6-8 weeks for a small NRE fee.

Block Dia ram

r----------------------------POWER___
DOWN
~I

I
I

PHASE
DETECTOR

CHARGE
PUMP

LOOP
FILTER

OUTPUT

I
I

&~O

CLKlor
2XCPUCLK

IL-~------------I
Fso----i---i~

OE

FREQUENCY STORE!
PHASE LOCK LOOP
CONTROL LOGIC

FSl----ir---~~

FS2 ----il---~~
FS3 ---'r---i~
ENABLE

+

XlIICL~ -..-~:-~~.rI-O-S-CI-L-LL-A-T-oIRI

~

~ :i
EM ~~i:~1

L ____________________________

395

~

OE

>

REFCLK
orCPUCLK

II

ICS9108

-

Decod·Ina 11abl e for ICS91 08 05 14318·InDut
PSI
0
0
1
1

FSO
0
1
0
1

DecodingTablefor ICS91 08-03, 14.318 input
PS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

PSI
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

FSI
0
0
1

FSO
0
1
0

1

1

1

0
1
0
1
0
1

0
1
0
1
0
1
0
1

CLKI
25 MHz
33.3 MHz
40 MHz
50 MHz

Pin Configurations

CLKI
16 MHz
40 MHz
50 MHz
80 MHz
66.66 MHz
100 MHz
8 MHz
4 MHz
8 MHz
20 MHz
25 MHz
40 MHz
33.33 MHz
50 MHz
4 MHz
2 MHz

FSO
0

-

Decod·Ing 11able for ICS910810'-'- 14318·InJlU t

CLKI
40 MHz
50 MHz
66.6 MHz
80 MHz

FSO
REFCLK
VDD
CLKI
OE (CLKI)
OE (REFCLK)
X2

FSI
FS2
PS3
AGND
GND
PD*
Xl/ICLK
ICS9108-03

FSO u 8 REFCLK
GND 2
7 VDD
XI/ICLK 3
6 CLKI
X2 4
5 FSI
ICS9108-0S/-10

-

-

p.In 0 escru:tlon for ICS9108 03I. ICS9108 05 an d ICS9108-10
Pin Name

Pin #

PSO
FSI
FS2
FS3
AGND
GND
PD*
Xl/ICLK

1
5

X2

4

OE(REFCLK)
OE(CLKl)
CLKI
VDD
REFCLK

6
7
8

2
3

Pin Type Description

14
1
2
3
4
5
6
7

Input
Input
Input
Input

8
9
10
11
12
13

Output
Input
Input
Output

-

Input
Input

Output

FREQUENCY SELECT 0 for CLKI (-03 has pull-up)
FREQUENCY SELECT 1 for CLKI (-03 has pull-up)
FREQUENCY SELECT 2 for CLKI (-03 ha~ull-~
FREQUENCY SELECT 3 for CLKl (-03 has pull-up)
Analog GROUND
Digital GROUND
POWER DOWN. Shuts off chip when low. Internal pull-up
CRYSTAL INPUT or INPUT CLOCK frequency. Typically
14.318MHz system clock
CRYSTAL OUTPUT (No Connect when clock used)
OUTPUT ENABLE. Tri-states REFCLK when low. Pull-up
OUTPUT ENABLE. Tri-states CLKI when low. Pull-up
CLOCKI Output (see decoding tables)
Digital power supply (+3V DC)
REFERENCE CLOCK output. Produces a buffered version
of the input clock or crystal frequency (typically 14.318 MHz)

396

ICS9108
The ICS91 08-04
The ICS9108-04 provides a 2X output and a IX output,
which are skew controlled to within Ins on the rising
edges. For the frequencies listed in the decoding tables,
the part assumes a 14.318 MHz input. The device is also
useful for providing integer multiples or divides based on
inputs in the range of 2 to 32 MHz.

Pin Confi uration
FSO

FSI
FS2
FS3
AGND
GND

CPUCLK

VDD
2XCPUCLK
OE (2XCPUCLK)
OE (CPUCLK)

PD*
Xl/ICLK

X2
ICS9108-04

14 pin DIP, SOIC

·r

Decoding Table for ICS91 08-04
(using a 14.318 MHz input)
FS3 FS2 FS1 FSO
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
1
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1

2XCPUCLK
80 MHz
66.66 MHz
SO MHz
40 MHz
100 MHz
33.33 MHz
32 MHz
25 MHz
64 MHz
2XINPUT
3XINPUT
8XINPUT
.5XINPUT
.25XINPUT
120 MHz
130 MHz

CPUCLK
40 MHz
33.33 MHz
25 MHz
20 MHz
SO MHz
16.67 MHz
16 MHz
12.5 MHz
32 MHz
INPUT
1.SX INPUT
4XINPUT
.25XINPUT
.12SXINPUT
60 MHz
65 MHz

-

p.In Descrlpllon for ICS91 08 04
Pin
Name
FSI
FS2
FS3
AGND
GND
PD*
Xl/ICLK
X2

OE(CPUCLK)
OE(2XCPUCLK)
2XCPUCLK
VDD
CPUCLK
FSO

Pin #

Pin Type Description

1
2
3
4
5
6
7

Input
Input
Input

8
9
10
11
12
13
14

Output
Input
Input
Output

-

Input
Input

-

Output
Input

FREQUENCY SELECT 1 (see decoding table). Pull-up
FREQUENCY SELECT 2 (see decoding table). Pull-up
FREQUENCY SELECT 3 (see decoding table). Pull-up
Analog GROUND
Digital GROUND
POWER DOWN. Shuts off entire chip when low. Pull-up
CRYSTAL INPUT or INPUT CLOCK frequency. Typically
14.318MHz system clock
CRYSTAL OUTPUT (No Connect when clock used)
OUTPUT ENABLE. Tri-states CPUCLK when low. Pull-up
OUTPUT ENABLE. Tri-states 2XCPUCLK when low. Pull-up
2X CPU CLOCK Output (see decoding table, note t below)
Digital power supply (+3V DC)
CPU CLOCK Output (see decoding table, note t below)
FREQUENCY SELECT 0 (see decoding table). Pull-up

'The CPUCLK and 2XCPUCLK outputs are skew controlled to within 1.0 ns max

397

ICS9108
Power Down

Frequency Accuracy and
Calculation
The accuracy of the frequencies produced by the ICS91 OS
depends on the input frequency and the desired actual
output frequency. The formula for calculating the exact
output frequency is as follows:
Output Frequency = Input Frequency x

If equipped, the power down pin shuts off the specified
PLL or entire chip to save current. A few milliseconds are
required to reach full functioning speed from a power
down state.

Frequency Transitions

~

where A = 2, 3, 4... 12S, and
B = 2, 3, 4... 32.
For example, to calculate the actual output frequency for
a video monitor expecting a 44.900 MHz clock and using
a 14.31S MHz input clock, the closest A/B ratio is 69/22,
which gives an output of 44.906 MHz (within 0.02% of
the target frequency). Generally, the ICS910S can produce frequencies within 0.1 % of the desired output.

A key ICS910S feature is the ability to provide glitch-free
frequency transitions across its output frequency range.
The ICS910S-03 provides smooth transitions between
any of the two groups of eight frequencies (when FS3=0
or FS3=1), so that the device will switch glitch-free between 4 -100 MHz and 2 - 50 MHz.

Allowable Input and Output
Frequencies
The input frequency should be between 2 and 32 MHz
and the A/B ratio should not exceed 24. The output
should fall in the range of 2-120 MHz.

Output Enable
The Output Enable feature tri-states the specified output clock pins. This places the selected output pins in a
high impedance state to allow for system level diagnostic testing.

398

ICS9108
Absolute Maximum Ratings
Voltage on I/O pins referenced to eND ...... eND -O.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

AVDD, VDD referenced to eND ................................. 7V
Operating temperature under bias ............. O°C to +70°C
Storage temperature ................................ -65°C to +150°C

Note. Stresses above those lIsted under Absolute MaXImum Ratings may cause permanent damage to the devIce. This is a stress ratIng only, and
functlOnal operatlOn of the deVIces at these or any other condItIons above those mdicated m the operatIonal sectIons of thIS specificatlOn IS not
ImplIed. Exposure to absolute maXimum conditions for extended penods may affect the relIabIlity of the deVIce

Electrical Characteristics at 5V
(Operating VDD

Symbol

= +4.5V to +S.5V, TA = ODe to 70 e
0

Parameter

unless otherwise stated)

Min

Typ

Max

-

-

0.8

2.0

-

-

Units Conditions

DC Char"' ..• ....... istics
VIL
VIH
IlL
I

~L

VOH
?D
d

C
C'L
IDDSTDBY

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current
Output Frequency Change
over Supply and Temperature
Input Capacitance
Load CapaCitance
Standby Supply Current

-

-

2.4
-

-

-

15
0.002

-5
5
0.4
-

20
0.05
10

20
10

pF
pF
!LA

VDD = 5V
VDD = 5V
VIN = OV
VIN: VD5\
IOL - 8m
I = -4mA
mtel
With respect to
typical frequency
Exce~t Xl, X2
Pins 1, X2
Note 2

ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
%
%
ps
ps
ns
ps
ps
ns
ms
ms
ps

25 pfload
25 pfload
25 pfload
25 pfload
15 pfload
15 pfload
16-100MHz
8 -14.318 MHz
Below 8 MHz
16-100MHz
8 -14.318 MHz
Below 8 MHz
From 50 to 4 MHz
From off to 100MHz
AV9107-04

V
V
!LA
!LA
V
V
mA
%

AC Characteristics
tw
t

t"

r

ItLK
ICLK;
thd
t,
t
t;

Jd t
Tt

t"
t"
TJIS

TJ"b~

T
tfl
tpu

Jabs
Jabs

T~k

Enable pulse width
Setup time data to enable
Output Frequency
Input Frequency
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V
Output Fall time, 2.0 to B:sv
Fall time, 80% to 20% V~
Duty cycle (UfI to 66.6
z)
Duty cycle (A I other frequencies)
Jitter, 1 sigma
Jitter, 1 sigma
Jitter, 1 sigma
Jitter, absolute
Jitter, absolute
Jitter, absolute
Frequency Transition time
Power up time
Clock skew between CPUCLK
and 2XCPUCLK outputs

20
20
2
2
-

10

-

14.318
-

-

1
2
1

45
40

50
48/52
90
150

-

±150
±500
15

-

120
32
20
20
-

2
4
2
4
55
60
150
300
1.5
±250
±800
±3.5
20
30
±250

Note 1: AV9108-03 with no load, with 14.318 MHz crystal input, and CLKI running at 40 MHz. Power supply
current varies with frequency. Consult Avasem for actual current at different frequencies.
Note 2: A V9108-03 with the power down pin low (active).
Note 3: To guarantee operation at 100 MHz or above, please indicate the highest speed used when ordering. For
example, if 120 MHz would be used on the A V9107-04CSI4, order it as AV9108-04CS14-120.

399

ICS9108

Electrical Characteristics at 3.3V
(Operating V DD

Symbol

= +3.0V to +3.7V, T A = O°C to 70°C unless otherwise stated)
Parameter

Min

Typ

Max

Units Conditions

DC Characteristics
VIL
VIH
IlL
I

~L

VOH
?O
d
C
C'L
IODSTDBY

Input Low Voltage
Input High Voltage
O· 7Voo
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-·1V
10
Supply Current
0.002
Output Frequency Change
over Supply and Temperature
Input Capacitance
Load C acitance
20
Supply urrent, Standby
10

6

0.15Voo
-

-5
5
0.1
-

15
0.01
10

V
V
~A
~A

V
V
rnA
%
pF
pF
~A

VIN=OV
VIN ~ Vo]\
IOL - 8m

~=-4mA

ate 1
With respect to
typical frequency
Exce~t Xl, X2
Pins 1, X2
When powered down

AC Characteristics
tw
t
IL:LK
ICLK;
thd
t

~

T'

t'
T"
T"
Tab'
T,abs

tft
t

t
(

Jabs

U

Enable pulse width
Setup time data to enable
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Rise time
Fall time
Duty cycle
Jitter,l sigma
Jitter, 1 sigma
Jitter, 1 sigma
Jitter, absolute
Jitter, absolute
Jitter, absolute
Frequency Transition time
Power up; time
Output requency
Input Frequency

20
20

-

-

-

-

-

-

20
20

10
-

40

48/52
90
150
±150
±500

-

4
4
60
150
300
1.5
±250
±800
±3.5
20

15
2
2

14.318

67
32

ns
ns
ns
ns
ns
ns
ns
%
ps
ps
ns
ps
ps
ns
ms
ms
MHz
MHz

15 pfload
15 pfload
15 pf load
16 -100MHz
8 -14.318 MHz
Below 8 MHz
16 -100 MHz
8 -14.318 MHz
Below 8 MHz
From 2 to 25 MHz
From off to 66.66 MHz
AV9107-03, FS3 = 0

Note 1: AV9108-03 with no load, with 14.318 MHz crystal input, and CLK1 running at 40 MHz. Power supply
current varies with frequency. Consult ICS for actual current at different frequencies.
Note 2: To guarantee 3V operation, please specify the AV9108-xxCxxx-3V when ordering.

400

ICS9108

Actual Frequencies
Decoding Table for ICS91 08-05,14.318 input
FS1
0
0
1
1

FSO
0
1
0
1

Decoding Table for ICS91 08-04,14.318 input
FS3 FS2 FS1 FSO
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1

CLK1
40.01 MHz
SO.l1 MHz
66.61 MHz
SO.Ol MHz

DecodingTable for ICS91 08-03,14.318 input
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

FSO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

CLK1
16.00 MHz
39.99 MHz
SO.l1 MHz
SO.01 MHz
66.5SMHz
100.23 MHz
S.02MHz
4.01 MHz
S.02MHz
20.00 MHz
2S.06MHz
40.01 MHz
33.29 MHz
SO.l1 MHz
4.01 MHz
2.0SMHz

2XCPUCLK
SO.02MHz
66.62 MHz
SO.l1 MHz
40.01 MHz
100.23 MHz
33.31 MHz
32.01 MHz
2S.06MHz
64.02 MHz
2XINPUT
3XINPUT
SXINPUT
.SXINPUT
.2SXINPUT
120.00 MHz
129.96 MHz

CPUCLK
40.01 MHz
33.31 MHz
2S.06MHz
20.00 MHz
S0.11 MHz
16.66 MHz
16.00 MHz
12.47 MHz
32.01 MHz
IX INPUT
l.SX INPUT
4XINPUT
.2SXINPUT
.12SXINPUT
60.00 MHz
64.9SMHz

Decoding Table for AV9108-10, 14.318 input
FS1
0
0
1
1

FSO
0
1
0
1

CLKI
2S.0S7MHz
33.2S9 MHz
40.006 MHz
SO.113 MHz

ord erma Inf ormation
Part Number
ICS91OS-xxCNS
ICS9108-xxCSS
ICS910S-xxCN14
ICS9108-xxCS14

Temperature Range
O°C
O°C
O°C
O°C

Package Type
S lead Plastic DIP (300 mils)
S lead SOIC (1S0 mils)
14 lead Plastic DIP (300 mils)
14 lead SOIC (1S0 mils)

to +70°C
to +70°C
to +70°C
to +70°C

Note: The dash number following ICS910S (denoted by xx above) must be included when ordering product since it
specifies the frequency decoding table being ordered. Decoding options can be created by a simple metal mask
change. Please use the ICS910S order form when ordering custom masks.

401

402

AV9128/9

Integrated
Circuit
Systems, Inc.

•

Motherboard Frequency Generator
frequencies, depending on the task being performed.
The AV9128/9 further reduces the current consumption
by having the ability to completely shut down the individual clocks when not in use. Standard parts with
power down for portable computers include the
AV9129-08, AV9128-22, and AV9128-24.

Features
•
•
•
•
•
•
•
•
•
•
•
•
•

AV9129 - 28 pin direct replacement for AV9127
AV9128 - 20 pin version for space-critical applications
Four independent clock generators
Skew controlled outputs on A V9129
Smooth frequency transitions
Power down options
Tri-state outputs
Up to 11 output clocks
On-chip loop filter components
Can generate clocks up to 100 MHz
14.318 MHz oscillator circuitry
28 pin PDIP or SOIC package - A V9129
20 pin PDIP or SOIC package - A V9128

General Description
The AV9128/9 is designed to generate clocks for all 8088,
286, 386, 486, and RISC based motherboards, including
laptops and notebook computers. The only external
components required are an input crystal and decoupIing capacitors. High performance applications may
also require high speed clock termination components.
The chip includes four independent clock generators
plus the reference crystal oscillator clock to produce all
necessary frequencies, including master clock, CPU clock,
twice CPU clock frequency, keyboard clock, floppy disk
controller clock, serial communications clock and bus
clocks. Different frequencies from Clocks #1, #2 and #3
can be selected using the frequency select pins.

Applications
Desktop Computers/Workstations: The AV9128/9 can
provide all of the necessary clocks for the motherboard,
replacing crystals and oscillators, and can be a single
chip solution for all different speeds and types of processors used. The A V9129 has up to five synchronized
outputs that are skew controlled to within Ins (typical)
for the processor clock (Clock#2), making it ideal for
high speed 386, 486 and RISC systems. The AV9129-06
and A V9129-23 are standard parts available to all customers.

The frequencies and power down options in the A V9128 /
9 are mask programmable. Customer specific masks can
be made and prototypes delivered within 6-8 weeks
from receipt of order. ICS also offers standard versions
such as those described in this data sheet.
The chip has multiple output buffers on key clocks to
allow for improved EMI performance by isolating clocks
going to different parts of the board, and thereby reducing the possibility of reflections. The chip provides slower
clock edges compared to oscillators, further helping EMI.

Laptop/NotebookComputers: TheAV9128/9is the ideal
solution for generating clocks in portables. The user can
save power by running the processor clock at lower

Block Dia ram
14.318 MHz
crystal
14.318 MHz
14.318 MHz
eLK1
Frequency Select
Power Down

Power Down

. -_ _ _ Power Down

CLOCK
GENERATOR

CLK3
Frequency Select

. -_ _-f-_ _ Frequency Select

REFERENCE
CLOCK

2

2XCPU

CLK41

CLOCK
GENERATOR
3

4

OE

403

CLK42
Power Down

•

AV9128/9

Pin DescriDtion for AV9128-22 (when usina a 14.318MHz reference)
Pin #

Pin type

CLKI

1

X2
Xl /ICLK
VDD
GND
CLK3
CLK4

2
3
4
5
6
7
8
9

Output
Output

Pin Name

DC
AGND
OE
PDCLK3*
PDCLK4*

10
11
12

AVDD
REFCLK

13
14

GND
VDD
CPUCLK
PDCLKl*

15
16
17
18

SCLK21
SCLK20

19
20

Input
-

Output
Output
-

Input
Input
Input
-

Output
-

Output
Input
Input
Input

Description
CLOCKI. (1.84 MHz)
CRYSTAL connection for 14.318 MHz crystal
CRYSTAL connection for 14.318 MHz crystal or CLOCK INPUT
POWER SUPPLY (+5V)
GROUND
CLOCK3 output (24 MHz)
CLOCK4 output (16 MHz)
Don't Connect this pin
ANALOG GROUND
OUTPUT ENABLE. A low level tri-states all outputs. Note 1
POWER DOWN. Powers down CLOCK3 when low
POWER DOWN. Powers down CLOCK4 when low
ANALOG POWER SUPPLY (+5V)
REFERENCE CLOCK. Produces a 14.318 MHz clock
GROUND
POWER SUPPLY (+5V)
CPU CLOCK. (see table)
POWER DOWN. Powers down CLOCKI when low
CLOCK2 frequency SELECT 1
CLOCK2 frequency SELECT 0

Note 1: Has internal pull-up resistor on this pin

404

AV9128/9
Block Diagram for AV9128-22

14318 MHz
crystal

1 84MHz

SCLK20

X2

SCLK2l

14318 MHz

1 844 MHz
50,40,32 MHz or OFF
CLK1 Power Down

24 MHz

Xl

PDCLK1"

VDD

CPUCLK

GND

VDD

24MHz

GND

l6MHz

REFCLK

16 MHz
DC

CLI<3 Power Down

CLK4 Power Down

PDCLK4"

OE

PDCLK3"

Output Enable

Decoding Tables for AV9128-22
(using 14.318 MHz input. Actual frequencies shown, in MHz)
CLOCK#3

CLOCK#l

CLOCK#2
SCLK21
(Pin 19)
0
0
1
1

CLK1
(Pin 1)

CLK3
(Pin 6)

1,844

23.71

CLOCK#4
SCLK20
(Pin 20)
0
1
0
1

CPUCLK
(Pin 17)
OFF
32,21
40.00
50.11

CLK4
(Pin 7)
16,00

REFERENCE CLOCK
REFCLK
(Pin 14)
14.318
When all 4 clocks are powered down, the 14,318 MHz reference clock automatically powers down.

405

AVDD

AGND

I

•

AV9128/9

Pin Description for AV9128-24 and -25 (when using a 14.318MHz reference)
Pin Name
CLKI
X2

Xl/ICLK
VDD
GND
CLK3
CLK4
DC
AGND
OE
PDCLK3*
PDCLK4*
AVDD
REFCLK
GND
VDD
CPUCLK
PDCLKl*
SCLK21
SCLK20

Pin #

Pin type

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Output
Output
Input

-

Output
Output

-

Input
Input
Input

Output
-

Output
Input
Input
Input

Description
CLOCKI (1.84 MHz)
CRYSTAL connection for 14.318 MHz crystal. NC for clock input
CRYSTAL connection or INPUT CLOCK
POWER SUPPLY (+5V)
GROUND
CLOCK3 (12 MHz on AV9128-24, 24 MHz on AV9128-25)
CLOCK4 output (16 MHz)
Don't Connect this pin
ANALOG GROUND
OUTPUT ENABLE. A low level tri-states all outputs. Note 1
POWER DOWN. Powers down CLOCK3 when low
POWER DOWN. Powers down CLOCK4 when low
ANALOG POWER SUPPLY (+5V)
REFERENCE CLOCK. Produces a 14.318 MHz clock.
GROUND
POWER SUPPLY (+5V)
CPU CLOCK2 output (see table on following page)
POWER DOWN. Powers down CLOCKI when low
CLOCK2 frequency SELECT 1
CLOCK2 frequency SELECT 0

Note 1: Has internal pull-up resistor

406

•

AV9128/9

Block Diagram for AV9128-24, AV9128-25
!43!8MHz
crystal

REFERENCE
CLOCK

CLK!

20

SCLK20

X2

19

SCLK21

Frequency Select

14318MHz

X1/ICLK

VDD
184MHz

CLOCK
GENERATOR

Power Down

1

CLOCK
GENERATOR
2

6666,50,40
orOMHz (off)

GND

5

CLOCK
GENERATOR
3

Power Down

CLOCK
GENERATOR

CLK4

16 MHz

VDD

"' ...

GND

14

REFCLK

Output Enable

10

Decoding Tables for AV9128-24, AV9128-25
(using 14.318 MHz input. Actual frequencies shown, in MHz)
CLOCK#3
CLK3
(Pin 6)

CLOCK#l
CLK1
(Pin 1)

11.86 or 23.71

1.844

CLOCK#2
SCLK21
(Pin 19)
0
0
1
1

SCLK20
(Pin 20)
0
1
0
1

CLOCK#4
CLK4
(Pin 7)

CPUCLK
(Pin 17)
OFF
40.00
50.11
66.58

16.00

REFERENCE CLOCK
REFCLK
(Pin 14)
14.318

When all 4 clocks are powered down, the 14.318 MHz reference clock automatically powers down.

407

CPUCLK

15

AGND
OE

PDCLKl"

17
16

DC

Power Down

18

..........
"''''

"''''
""""
NN

CLK3
12 MHz (-24)
or
24 MHz (-25)

»
«

13

AVDD

12

PDCLK4'

11

PDCLK3'

II

•

AV9128/9

Pin Description for AV9129-06 (when usina a 14.318MHz reference)
Pin Name
SCLK31
SCLK30
CLK1
Xl
X2
REFCLKI
VDD
DGND
CLK3
CLK42
CLK41
AGND
OE
TEST
SCLK1
PD*
AVDD
REFCLK2
CLK21
CLK22
DGND
VDD
CLK23
CLK24
CLK25
SCLK22
SCLK21
SCLK20

Pin #

Pin type

1
2
3
4
5
6
7
8
9
10

Input
Input
Output
Input
Output
Output

11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Output
Output
Output

Input

Input
Input

Output
Output
Output

Output
Output
Output
Input
IIl£ut
Input

Description
CLOCK3 frequency SELECT 1
CLOCK3 frequency SELECT 0
CLOCKI output
CRYSTAL connection for 14.318 MHz crystal, or input clock
CRYSTAL connection for 14.318 MHz crystal
REFERENCE CLOCK output #1. Produces 14.318 MHz clock
DIGITAL POWER SUPPLY (+5V)
DIGITAL GROUND
CLOCK3 output
CLOCK4 output #2
CLOCK4 output #1
ANALOG GROUND
OUTPUT ENABLE. A low tri-states the output clocks. Note 1
TEST. Connect to VDD or can be left floating. Note 1
CLOCK 1 frequency SELECT. Note 1
POWER DOWN. A low shuts down all 4 clock generators. Note 1
ANALOG POWER SUPPLY (+5V DC)
REFERENCE CLOCK output #2. Produces 7.159 MHz clock
CLOCK2 output #1
CLOCK2 output #2
DIGITAL GROUND
DIGITAL POWER SUPPLY (+5V)
CLOCK2 output #3
CLOCK2 output #4
CLOCK2 output #5
CLOCK2 frequency SELECT 2
CLOCK2 frequency SELECT 1
CLOCK2 frequency SELECT 0

Note 1: These pins have internal pull-up resistors to maintain complete functionality when used in an AV9127 socket

408

•

AV9128/9

Block Dia ram for AV9129-06
14318MHz
crystal

14318 MHz
7159MHz
1844MHz
or 1841MHz

{

-

r

REFERENCE
CLOCK

CLOCK
GENERATOR
2

SELECT

02:-

SCLK31

SCLK20

SCLK30

SCLK21

elK1

SCLK22

Xl

4

CLOCK
GENERATOR
1
FREQUENCY ___

955, 16 00, 24
4009 MHz

FREQUENCY
l SELECT

CLOCK
GENERATOR
3

CLOCK

GENERATOR
4

6682,50 II, 4009,3341,

f-I-- 3201,2506,24 00, 20 05 MHz

r-

-r-

CLK25

X2

CLK24

REFCLKI

3341,2506,2005,1670,
16 AD, 1253, 1200, 10 02 MHz

CLK23

VDD

16MHz

12MHz

VOO

DGNO

DGNO

elK3

CLK22

CLK42

CLK21

CLK41

REFCLK2

AGND

FREQUENC
Y-P
SELECT

~;;I~~J -

~POWER

AVDD

OE

DOWN

PO"

TEST

SCLKI

Decoding Tables for AV9129-06
(using 14.318 MHz input. Actual frequencies shown, in MHz)
CLOCK#1
SCLKI
(Pin 15)
0
1

CLOCK#3
SCLK31
(Pin #1)
0
0
1
1

CLKI
(Pin 3)
18.44
1.844

CLOCK#2
SCLK22 SCLK21 SCLK20
CLK22-5
I (Pin 26) (Pin 27) (Pin 28) I (Pins 20 23-25)
0
0
66.63
0
0
0
1
50.11
0
1
40.09
0
::\'\.,2
0
1
1
1
0
31.98
0
1
0
1
25.06
1
1
23.98
0
1
1
1
20.05

CLK21
(Pin 19)
33.32
25.06
20.05
Ih.hh
15.99
12.53
11.99
10.02

SCLK30
(Pin #2)
0
1
0
1

CLOCK#4
CLK41
(Pin 11)
16.00
REFERENCE CLOCK
REFCLKI
(Pin 6)
14.32

409

CLK3
(Pin #9)
9.62
15.97
23.86
39.86
CLK42
(Pin 10)
12.00

REFCLK2
(Pin 18)
7.16

E1

AV9128/9
Pin DescriDtion for AV9129-08 (when usina a 14.318MHz reference)
Pin Name
PDCLK3*
PDCLK4*
CLKI
Xl
X2
REFCLKI
VDD
DGND
CLK3
CLK42
CLK41
AGND
OE
TEST
SCLKI
SCLK21
AVDD
REFCLK2
NC
CLK22
DGND
VDD
CLK23
NC
NC
PDCLKl*
PDCLK2*
SCLK20

Pin #

Pin type

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Input
Input
Output
Input
Output
Output
-

Output
Output
Output
-

Input
-

Input
Input
-

Output
-

Output
-

Output
-

Input
Input
Input

•

Description
POWER DOWN CLOCK#3. Shuts off CLK3 when low
POWER DOWN CLOCK#4. Shuts off CLK4 when low
CLOCKI output
CRYSTAL connection for 14.318 MHz crystal, or input clock
CRYSTAL connection for 14.318 MHz crystal
REFERENCE CLOCK output #1. Produces 14.318 MHz clock
DIGITAL POWER SUPPLY (+5V)
DIGITAL GROUND
CLOCK3 output
CLOCK4 output #2
CLOCK4 output #1
ANALOG GROUND
OUTPUT ENABLE. A low tri-states the output clocks. Note 1
TEST. Connect to VDD or can be left floating. Note 1
CLOCKI frequency SELECT. Note 1
CLOCK2 frequency SELECT 1. Note 1
ANALOG POWER SUPPLY (+5V DC)
REFERENCE CLOCK output #2. Produces 14.318 MHz clock
NO CONNECT
CLOCK2 output #2
DIGITAL GROUND
DIGITAL POWER SUPPLY (+5V)
CLOCK2 output #3
NO CONNECT
NO CONNECT
POWER DOWN CLOCK#1. Shuts off CLKI when low
POWER DOWN CLOCK#2. Shuts off CLK2 when low
CLOCK2 frequency SELECT 0

Note 1: These pins have internal pull-up resistors to maintain complete functionality when used in an AV9127 socket

410

AV9128/9
Block Dia ram for AV9129-08
14318MHz
crystal
14318MHz
14318MHz

1844MHZ
or 1844 MHz

{

--

REFERENCE
CLOCK

CLOCK
GENERATOR

CLOCK
GENERATOR

1

2

eLK1 Power Down,----0
Frequency Select

24 00 MHz

eLK3 Power Dow

r+

t-

----.

--

rr-

Frequency
Select

CLOCK
GENERATOR

3

4

n __

SCLK20

PDCLK4*

PDCLK2*

eLK1

PDCLKl*

Xl

NC

80,666,50 or 40 MHz
X2

NC

4 0,333,25 or 20 MHz
REFCLKl

1-'CLK2 Power Down
CLOCK
GENERATOR

PDCLK3*

r----- 16 QO MHz
r----- 3201 MHz
I-- CLK4 Power Down

CLK23

VDD

VDD

DGND

DGND

CLK3

CLK22

CLK42

NC

CLK41

REFCLK2

AGND

'---- Output

AVDD

OE

SCLK21

Enable
TEST

SCLKI

Decoding Tables for AV9129-08
(Using 14.318 MHz input. All frequencies in MHz)
REFCLK
PDCLK
(1-4)*
0
1

CLOCK#1
PDCLKl*
(Pin 26)
0
1
1

REFCLK
OUTPUT
OFF
ON

REFCLKI
(Pin 6)
LOW
14.318

CLOCK#4
PDCLK4*
(Pin 2)
0
1

REFCLK2
(Pin 18)
LOW
14.318

CLK4
OUTPUTS
OFF
ON

CLK41
(Pin 11)
LOW
32.00

CLK42
(Pin 10)
LOW
16.00

rTnrK,n
CLKI
OUTPUT
OFF
ON
ON

SCLKI
(Pin 15)

X
0
1

CLKI
(Pin 3)
LOW
18.44
1.844

PDCLK3*
(Pin 1)
0
1

CLK3
OUTPUT
OFF
ON

CLK3
(Pin 9)
LOW
24.08

CLOCK#2
PDCLK2*
(Pin 27)
0
1
1
1
1

SCLK21
(Pin 16)

SCLK20
(Pin 28)

X

X

0
0
1
1

0
1
0
1

CLK22,23
(Pin 20 23)
OFF
ON
ON
ON
ON

CLK23
(Pin 23)
LOW
80.05
66.63
50.11
40.00

CLK22
(Pin 20)
LOW
40.03
33.32
25.06
20.00

When PDCLKl*, POCLK2*, POCLK3*, and PDCLK4* all power down, the REFCLK automatically powers down.

411

iii

•

AV9128/9

Pin Description for AV9129-23 (when using a 14.318MHz reference)
Pin Name
PDCLK2*
SCLK31
CLK1
X2
Xl
NC
VDD
DGND
CLK3
CLK42
CLK41
AGND
SCLK30
NC
OE
SCLK22
AVDD
REFCLK2
REFCLK1
CLK22
DGND
VDD
CLK23
CLK24
CLK25
PDCLK4*
SCLK21
SCLK20

Pin #

Pin type

1
2

Input
Input

3
4
5
6
7

Output
Output

8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Input
-

Output
Output
Output
-

Input
-

Input
Input
-

Output
Output
Output
-

Output
Output
Output
Input
Input
Input

Description
POWER DOWN. Powers down CLOCK2 when low. Note 1
CLOCK3 frequency SELECTl. Note 1
CLOCK1 output (1.844 MHz)
CRYSTAL connection for 14.318 MHz crystal
CRYSTAL connection for 14.318 MHz crystal, or input clock
NO CONNECT
DIGITAL POWER SUPPLY (+5V)
DIGITAL GROUND
CLOCK3 output
CLOCK4 output #2 (23.71 MHz)
CLOCK4 output #1 (11.86 MHz)
ANALOG GROUND
CLOCK3 frequency SELECTO. Note 1
TEST. Connect to VDD or can be left floating
OUTPUT ENABLE. All outputs are tri-stated when low. Note 1
CLOCK2 frequency SELECT 2
ANALOG POWER SUPPLY (+5V DC)
REFERENCE CLOCK output #2. Produces 14.318 MHz clock
REFERENCE CLOCK output #1. Produces 14.318 MHz clock
CLOCK2 output #2
DIGITAL GROUND
DIGITAL POWER SUPPLY (+5V)
CLOCK2 output #3
CLOCK2 output #4
CLOCK2 output #5
POWER DOWN. Power down CLOCK4 when low. Note 1
CLOCK2 frequency SELECT 1
CLOCK2 frequency SELECT 0

Note 1: Has internal pull-up resistor on this pin

412

•

AV9128/9

Block Dia ram for AV9129-23
14318MHz
REFERENCE
CLOCK

crystal
14318MHz
14318 MHz

Frequency Select

~'-_ _ _----'

1844MHz

SCLK20

SCLK31

SCLK21

Power Down

100',80,66.6,SD,40,
32,16,8 MHz

CLOCK
GENERATOR
2

CLOCK
GENERATOR
1

elK1

CLOCK
GENERATOR

12 MHz

CLOCK
GENERATOR
4

Frequency Select 2

24 MHz

CLK25

Xl

CLK24

NC

CLK23

VDD

DCND

DCND

CLIG

CLK22

CLK42

REFCLKI

CLK41

REFCLK.2

AGND

AVDD

SCLK30

SCLK22

NC

Power Down

OE

PDCLK4>O

Xl

VDD

50',40,333,25,20,
16,8,4 MHz

32,30,24,16
MHz

PDCLK2·

OE

Decoding Tables for AV9129-23
(using 14.318 MHz input. Actual frequencies shown, in MHz)
CLOCK#3
SCLK31
(Pin 2)
0
0
1
1

,LOr'Kll

CLKI
(Pin 3)
1.844

CLOCK#2
SCLK22 SCLK21 SCLK20
(Pin 16) (Pin 27) (Pin 28
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

CLK22,23 CLK24,25
(Pins 20 23) (Pins 24 25)
7.50
3.75
15.51
7.75
32.22
16.11
40.09

20.04

50.11
66.54
80.18
100.23*

25.05
33.27
40.09
50.11*

SCLK30
(Pin 13)
0
1
0
1

CLOCK#4
CLK41
(Pin 11)
11.86
REFERENCE CLOCK
REFCLKI
(Pin 19)
14.32

CLK3
(Pin 9)
24.00
30.07
32.00
16.00
CLK42
(Pin 10)
23.71

REFCLK2
(Pin 18)
14.32

* The 1,1,1 selection does not guarantee a 100 MHz and 50 MHz output clock with the standard A V9129-23. If either
of these clocks is desired, order the device as an AV9129-23Cx 28-100. The 100 MHz operation will be specially
screened.

413

II

•

AV9128/9
Absolute Maximum Ratings

Storage temperature ................................ -40°C to +150°C
Voltage on flO pins referenced to GND ...... GND -0.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts
Note: Stresses above those listed under Absolute Maximum ratmgs may cause permanent damage to the device. This IS a stress rating only and
funchonal operation of the devices at these or any other conditions above those indicated m the operational sechons of this specification IS not

AVDD, VDD referenced to GND ................................. 7V
Operating temperature under bias ............. O°C to +70°C

implied. Exposure to absolute maximum conditions for extended periods may affect deVices reIJabiIJty

Electrical Characteristics
(VDD = +5V± 10%, TA

Symbol
D~

= ODC to 70 DC unless otherwise stated)
Parameter

Min

Typ Max Units

Conditions

Char' ·...•.......istics

VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
Icc
FD
Isc
Icc
ICCSTDBY
Rpu

Input Low Voltage
Input High Voltage
2.0
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-.4V
Output High Voltage
VDD-·SV
2.4
Output High Voltage
Supply Current
Output Frequency Change
over Supply and Temperature
Short circuit current
25
Supply Current
Standby Supply Current
Pull-up resistor value

AC Characteristics
tIC'
tIC'
t,
t,
tf
t,
dt
dt
til'
t

r
-t
t pu

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% VDO
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VOD
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power up time

-

43/57
40/60
5

-

45
0.005

O.S
-

-5*
5
0.4
-

0.05

40
30
50
6S0

V
V
~A
~A

V
V
V
V
rnA
%
rnA
rnA
~A

kQ

-

ns

-

TIS

20
20
1
2
2
4
1
2
2
4
4S/52 57/43
43/57 60/40
1
3
2
5
14.31S
32
1
1.5
5

Voo=5V
Voo = 5V
VIN=OV
VIN = Voo
IOL =4mA
IOH = -lmA,Voo=5.0V
IOH = -4mA,Voo=5.0V
lIoH = -SmA
No load, AV9129-06
With respect to
typical frequency
Eacl:l output clock
No load, AV9129-0S
All Clocks off
Pins 13-16 AV9129

ns
ns
ns
ns
%
%
%
%
MHz
ns

25 pfload
25 pfload
25 pf load
25 pfload
25 pf load
25 pf load
As compared with
clock period

ms

From off to SO MHz

* Crystal mput pm wIll be higher, typically

-lO~A

Notes:
1. All clocks on AV9129-06 running at highest possible frequencies. Power supply current can change substantially
with different mask configurations (see Application Note AAN02).

414

•

AV9128/9

Ordering Information
Part Number
A V9128-xxCN20
A V9128-xxCW20
AV9129-xxCN28
AV9129-xxCW28

Temperature Range
O°C
O°C
O°C
O°C

to+70°C
to+70°C
to +70°C
to +70°C

Package Type
20 lead Plastic DIP
20 lead SOIC
28 lead Plastic DIP (300 mils)
28 lead SOle

Note: The dash number following A V9128/9, (denoted by xx above) must be included when ordering product, since
it specifies the options being ordered. For 100 Mhz devices, add -100 MHz to part number.

415

416

ICS9131

Integrated
Circuit
Systems, Inc.

Advance Information

32 kHz Motherboard Frequency Generator
General Description

Features

The ICS9131 offers a tiny footprint solution for generating
a selectable CPU clock from a 32.768 kHz crystal. The
device allows a variety of microprocessors to be clocked by
changing the state of address lines FSO, FSI, and FS2. The
ICS9131 is the ideal solution for rep acing high speed oscillators and for reducing clock speeds to save power in computers. The device provides smooth, glitch-free frequency
transitions so that the CPU can continue to operate during
slowdown or speed up. The rate offrequencychange makes
the ICS9161 compatible with all 386DX, 386SX, 486DX,
486D XZ, 486SX and Pentium™ microprocessors.

•
•
•
•
•
•
•
•

The ICS9131 is driven from a single 32.768 kHz crystal. The
only external components required are the crystal, crystal
components, and decoupling capacitors. The device generates the 14.318 MHz system clock, eliminating the need for
a 14.318 MHz crystal. High- Performance applications may
require high speed clock termination components.

Single 32.768 kHz crystal generates system clock and
selectable CPU clock
Generates CPU clocks from 8 MHz to 100 MHz.
Operates from 3.3V or S.OV supply
Operates up to 66 MHz at 3.3V
Separate VDD for 32 kHz clock enables it to run from
battery
STOPCLK feature allows for a smooth turn-on and
turn-off of the CPU clock to static processors
Output enable tristates outputs
16-pin PDrp or sorc package

Applications
Notebook/Palmtop Computers: The ICS9131 works with
+ 3V and + SV and a single 32.768 kHz crystal, making it
the ideal solution for generating clocks in portables with
minimum board space. The user can save power by using
this single part instead of oscillators or other frequency
generators. The ICS9131 further reduces the current consumption by having the ability to completely shut-down the
individual clocks when not in used, while still maintaining
the separately powered 32.768 kHz clock.

VDD32 Supply
The ICS9131 has a separate power supply for the 32.768 kHz
oscillator circuitry. This allows the 32kHz clock to run from
a battery or other souce while the main power to the chip is
disconnected. The VDD32 supply is guaranteed to operate
down to + 2.0V, with the clock consuming less than 10IlA at
+ 3.3V with the main VDD at Ov.
The frequencies and power down options in the ICS9131 are
mask programmable. Customer specific masks can be made
and prototypes delivered within 6-8 weeks from receipt of
order. rcs also offers standard versions, such as those
described in this data sheet.

Block Diagram

STOPCLK
32.768 kHz

crystal
32.768 kHz

Reference
Clock
14.318 MHz

Pentium

IS

Clock
Generator
1
+---~

a trademark of Intel

417

Clock
Generator
2

CPUCLK

ICS9131
Pin Configuration

Decoding Table for CPU Clock

32KhZ
X2

n

Xl

-fI.l

VDD32
VCC
VSS
AGND

loCI

w

b

OE

FSO
FSI
CPUCLK.
VCC
VSS
STOPCLK·
REFCLK.
FS2

FS2

FSI

FSO

CPUCLK

ACTUALS

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

16

16.004
25.059
33.412
40.095
50.119
60.142
66.484
80.190

25
33.3
40
50
60
66.6
80

Ordering Infonnation
ICS9131-01CN (DIP)
ICS913l-0lCM (SOIC)

Pin Descriptions
PIN NUMBER
1

PIN NAME

TYPE

DESCRIPTION

32kHz

OUTPUT

32.768 kHz output

2

X2

OUTPUT

Connect 32 kHz crystal

3

Xl

INPUT

Connect 32 kHz crystal

4

VDD32

Power Supply for 32 kHz oscillator

5

VCC

Power Supply (+ 3.3V - 5.0V)

6

VSS

Ground

7

AGND

Analog Ground

8

OE

INPUT

OE tristates outputs when low

9

FS2

INPUT

CPU clock frequency select 2

10

REFCLK

11

STOPCLK*

OUTPUT
INPUT

14.318 MHz output
Stops CPU Clock when low

12

VSS

13

VCC

14

CPUCLK

15

FSI

INPUT

CPU clock frequency select 1

16

FSO

INPUT

CPU clock frequency select 0

Ground
Power supply (+ 3.3V-5.0V)
OUTPUT

CPU Clock output (see Decoding table)

418

II

ICS9131

Block Diagram for ICS9133-01

32.768 kHz

crystal

~--

LJ

32.768 kHz +-

I

Output
Buffer

~

I+-

Reference

k

Clock~
14.318 MHz
Clock
Generator

I

STOPCLK
3

J

~

Frequency Select

I
I

CPU Clock

i

f-:,

Output
Buffers

1- CPUCLK
OE

14.318 MHz

Recommended External Circuit

2
nr./1
3
'-0
4 ----------w-.-...
.-...
5
0
.-...
6
7
LJ 8
~

VDDX

VDD

I

9
i

16
15
14

p
1,

13

12
11
10
9

tOM

tJ
I

~

Notes:
1) The external components shown should be placed as close to the device as possible.
2) Pins 5 and 13 should be connected together externally. One decoupling capacitor may suffice for both pins.
3) May be part of system decoupling.
4) A Ion 3/lF low pass filter maybe required_

419

ICS9131
Absolute Maximum Ratings
VDD referenced to GND .....................
Operating temperature under bias .............
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . ..
Voltage on I/O pins referenced to GND .........
Power dissipation ............................

7V
O"C to + 70"C
-40"C to + 150"C
GND -0.5V to VDD+ 0.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

Electrical Characteristics
Voo = + 3.0 to 3.7V, TA= O"C to 70"C unless otherwise stated)

DC Characteristics
MIN

TYP

MAX

UNITS

Input Low Voltage

PARAMETER

SYMBOL
VIL

Voo= 3.3V

-

-

0.2Voo

V

Input High Voltage

VIH

Voo= 3.3V

0.7Voo

-

-

V

Input Low Current

hL

VIN= OV

-

-

-2*

ItA

Input High Current

IJH

VIN= Voo

-

2*

Output Low Voltage

VOL

IOL= 4mA

-

0.1

J.1A
V

Output High Voltage

VOH

IOH= -lmA, Voo= 3.3V

Voo-.IV

-

-

V

IOH= -4mA, Voo= 3.3V

-

-

-

V

Output High Voltage

VOH

Output High Voltage

VOH

TEST CONDITIONS

IOH= -SmA

2.4

-

-

V

-

.005

0.05

%

Output Frequency
Change over Supply and
Temperature

Fo

With respect to typical
frequency

Short circuit current

Isc

Each output clock

15

mA

Icc
Rpu

No load, 40 MHz

10

mA

620

ill

Supply Current
Pull-up resistor value

420

ICS9131
Electrical Characteristics
VDD

= + 3.0 to 3.7V, TA= OOC to 700C unless otherwise stated)
AC Cbaraeteristics
PARAMETER

SYMBOL

Input Clock Rise Time

tICr

Input Clock Fall Time

tICf

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

-

5

lis

-

5

-

1.5

2

lis
ns

Output Rise time, 0.8 to 2.0V

tr

15 pfload

Rise time, 20% to 80% VDD

tr

15 pfload

-

2.5

4

ns

Output Fall time, 2.0 to 0.8V

tf

15 pfload

-

1.5

2

ns

Fall time, 80% to 20% VDD

tf

15 pfload

-

2.5

4

ns

Duty cycle

dt

15 pfload

43/57

48/52

57/43

%

Duty cycle, reference clocks

dt

15 pfload (Note 1)

40/60

43/57

60/40

%

Jitter, one sigman

tJis

As compared with clock
period

-

1

3

%

Jitter, absolute

tjab

2

5

%

25

32.768

40

kHz

100

500

ps

Input Frequency

fi

Clock skew between any
Clock # 2 outputs

Tak

Power up time

tpu

From off to 40 MHz

Note 1: 32 kHz output duty cycle is dependent on crystal used.

421

10

ms

II

ICS9131
Electrical Characteristics
Voo = + 5V± 10%, T A= OOC to 700C unless otherwise stated)

DC Cbaraeteristks
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage

VIL

Voo= 3.3V

-

-

0.2Voo

V

Input High Voltage

VIH

Voo= 3.3V

0.7Voo

-

-

V

Input Low Current

lIL

VIN= OV

-

-

-2*

I1A

Input High Current

lIH

VIN= Vno

-

2*

JJA

Output Low Voltage

VOL

IOL= 4mA

-

-

0.1

V

Output High Voltage

VOH

10H= -lmA, Voo= 3.3V

Voo-.1V

-

-

V

Output High Voltage

VOH

IOH= -4mA, Voo= 3.3V

-

-

-

V

Output High Voltage

VOH

IOH= -SmA

2.4

-

-

V

-

.005

0.05

%

Output Frequency
Change over Supply and
Temperature

Fo

With respect to typical
frequency

Short circuit current

Isc

Each output clock

33

rnA

Icc
Rpu

No load, 40 MHz

17

rnA

380

ill

Supply Current
Pull-up resistor value

Electrical Characteristics
Voo = + 5VrelO%, TA= OOC to 700C unless otherwise stated)
AC CbaracterisUcs

PARAMETER

SYMBOL

TEST CONDITIONS

Input Clock Rise Time

tICr

Input Clock Fall Time
Output Rise time, O.S to 2.0V

tICf
tr

15 pfload

MIN

TYP

MAX

UNITS

-

-

5

I1S

-

5

-

1

1.5

I1s
ns
ns

Rise time, 20% to SO% Voo

tr

15 pfload

-

2

3

Output Fall time, 2.0 to O.SV

tf

15 pfload

-

1

1.5

ns

Fall time, SO% to 20% Voo

tf

15 pfload

-

2

3

ns

Duty cycle

dt

15 pfload

43/57

4S/52

57/43

%

Duty cycle, reference clocks

dt

15 pfload (Note 1)

40/60

43/57

60/40

%

Jitter, one sigman

tJIS

As compared with clock
period

-

1

3

%

Jitter, absolute

tjab

Input Frequency

25

fl

Clock skew between any
Clock # 2 outputs

Tak

Power up time

tpu

From off to SO MHz

Note 1: 32 kHz output duty cycle is dependent on crystal used.

422

2

5

%

32.76S

40

kHz

100

500

ps

10

ms

[I

ICS9131

Stop Clock Feature
The ICS9131 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock pin
goes low, the CPUCLK will go low after the next occuring
falling edge. When STOPCLK again goes high, CPUCLK
resumes on the next rising edge of the internal clock. This
feature enables fast, glitch-free starts and stops of the
CPUCLK and is useful in Energy Star motherboard applications.

L

32 kHz Supply Current
14

JlA

12

CL = 25pF

10

CL = 15pF

8

CL

=

OpF

6
4

2
0

t
0

I

I

I

I

I

I

1

2

3

4

5

6

Vdd

ADVANCE INFORMATION documents contain Information on new products

In

the samw

piing or preproduction phase of development Charactenstlc data and other specifications

are subject to change WIthout notice

423

424

•

ICS9132

Integrated
Circuit
Systems, Inc.

Advance Information
32 kHz Motherboard Frequency Generator
Features

Applications

• Single 32.768 kHz crystal generates all PC
motherboard clocks
• Four independent clock generators
• Generate CPU clock from 12.5 to 100 MHz
• Up to 6 output clocks
• Each clock can be individually powered down
• Separate VDD for 32 kHz clock
• Output enable tri-states outputs
• On-chip loop filter components
• Operates from +3.3V or 5.0V supply
• Skew controlled 2x and Ix CPU clocks
• 20 pin PDlP or SOIC package

Notebook/Palmtop Computers: The ICS9132-0l works
with +3V and +5V and a single 32.768 kHz crystal,
making it the ideal solution for generating clocks in
portables with minimum board space. The user can save
power by using this single part instead of oscillators or
other frequency generators. The ICS9132 further reduces
the current consumption by having the ability to
completely shut down the individual clocks when not in
use, while still maintaining the separately powered
32.768 kHz clock.
Desktop Computers: The ICS9132-03 works at 5V while
saving the cost and space of oscillators. Using a single
32.768 kHz crystal, the ICS9132-03 generates all CPU and
peripheral clocks found on a motherboard.

General Description

VDD32 SUPPLY
The ICS9132 has a separate power supply for the
32.768 kHz oscillator circuitry. This allows the 32 kHz
clock to run from a ba ttery or other source while the main
power to the chip is disconnected. The VDD32 supply is
guaranteed to operate down to +2.0V, with the clock
consuming less than lOJ.lA at +3.3V with the main VDD
atOV.

The ICS9132 is designed to generate clocks for all 286,
386,486, Pentium and RISC based motherboards, including laptops and notebook computers. The only external
components required are a 32.768 kHz crystal, crystal
components, and decoupling capacitors. The device
generates the 14.318 MHz system clock, eliminating the
need for a 14.318 MHz crystal. High performance applications may require high speed clock termination components. The chip includes four independent clock
generators plus the 32.768 kHz reference clock to prod uce all necessary frequencies, including real time clock/
DRAM refresh, master clock, CPU clock, twice CPU
clock frequency, keyboard clock, floppy disk controller
clock, serial communications clock and bus clocks.
Different frequencies from clocks #2, #3, and #4 can be
selected using the frequency select pins, however clock
#1 will be at 14.318 MHz for all standard versions.

Part

Description

ICS9132-01

Notebook version

ICS9132-03

DesktoD version

ICS9132-16

Pentium version with SCUZZY clock

ICS9132-18

Pentium version

Block Diagram
~

I
32768 kHz
crystal

:[

-

REFERENCE
CLOCK

-

--

CLOCK
GENERATOR

CLOCK
GENERATOR

1

2

CLOCK
GENERATOR

CLOCK
GENERATOR

3

4

425

f-----

-

ICS9132
ICS9132-01 Decoding Table for
CPU CLOCK

Pin Configuration
32kHz

SCLK20

X2

SCLK21

XI

SCLK22
CPU

VDD32
VDD

VDD

GND

GND
16004 MHz

24006 MHz

14319MHz

I 847 MHz

VDD

GND
PD24 + 184

SCLK22
Pin 18
0
0
0
0
1
1
1
1

~

SCLK21 SCLK20 CPU (MHz)
Pin 20
Pin 19
Pin 17
0
OFF
0
1
4.010 MHz
0
0
25.059
1
1
33.258
1
0
40.095
0
1
50.119
0
0
66.641*
1
1
80.060*
1
* Only at 5V supply voltage

_ _ _ _ _--...r- PD!4 + 16

-

p.In Descrlptlon for ICS913201
Pin Name
32kHz
X2
Xl
VDD32
VDD
GND
24.006 MHz
1.847 MHz
GND
PD24.006 & 1.847 MHz
PD14& 16 MHz
VDD
14.319 MHz
16.004 MHz
GND
VDD
CPU
SCLK22
SCLK21
SCLK20

Pin # Pin type Description
1
2
3
4
5
6
7
8
9

Output
Output
Input

10

Input
Input

11
12
13
14
15
16
17
18
19
20

-

Output
Output
-

-

Output
Output
-

Output
Input
Input
Input

32.768 kHz output
Connect 32 kHz crystal
Connect 32 kHz crystal
Power supply for 32 kHz oscillator only
Power supply (+3.3 - +5.OV)
GROUND
24.006 MHz clock output
1.847 MHz clock output
GROUND
POWER DOWN. Shuts off 24.006 & 1.847 MHz clocks when low
POWER DOWN. Shuts off 14.319 & 16.004 MHz clocks when low
Power Supply (+3.3 to +5.OV)
14.319 MHz clock output
16.004 MHz clock output
GROUND
Power Supply (+3.3 to +5.OV)
CPU clock output (see decoding table)
CPU clock frequency SELECT 2
CPU clock frequency SELECT 1
CPU clock frequency SELECT 0

426

ICS9132

Block Dia ram for ICS9132-01
32.768 kHz
crystal
0

REFERENCE
CLOCK

32.768 kHz

Frequency Select
14.318 MHz
Power Down

1.8 MHz

CLOCK
GENERATOR

CLOCK
GENERATOR
2

1

CLOCK
GENERATOR
3

CLOCK
GENERATOR
4

CPU

16 MHz
24 MHz

Power Down

Recommended External Circuit
20
19

2

18
4

VDOX

VDD

17

....

I"l

16

....'llw

15

VJ

(NO~:~~~

N

7

14
13
12

10

11

NOTES:
(1) The external components shown should be placed as close to the device as possible.
(2) Pins 5 and 16 should be connected together externally.
One decoupling capacitor may suffice for both pins.
(3) May be part of system decoupling.

427

ICS9132
Pin Configuration

ICS9132-03 Decoding Tables
CPU CLOCK

32KHz

SCLK20

X2

SCLK21

XI

SCLK22
2XCPU

VDD32
VDD

VDD

GND

GND

CLK3

CPU
14319

24007 MHz

SCLK22
Pin 18
0
0
0
0
1
1
1
1

SCLK21
Pin 19
0
0
1
1
0
0
1
1

SCLK20 2xCPU(MHz) CPU (MHz)
Pin 20
Pin 17
Pin 14
0
100.226
50.113
1
32.005
16.003
0
25.059
12.530
1
33.293
16.647
40.006
0
20.003
1
50.119
25.059
0
66.586
33.293
80.012*
1
40.006

VDD

GND

DE

SCLK3

KBDCLOCK
SCLK3
0
1

* Only at SV supply voltage

CLK3
8.002
12.082

Pin Description for ICS9132-03 (5V operation. 3V available upon request)
Pin
Name
32kHz
X2
Xl
VDD32
VDD
GND
CLK3
24.007 MHz
GND
SCLK3
OE
VDD
14.319MHz
CPU
GND
VDD
2xCPU
SCLK22
SCLK21
SCLK20

Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Pin
type
Output
Output
Input
-

Output
Output
-

Input
Input
-

Output
Output
-

Output
Input
Input
Input

Description
32.768 kHz output
Connect 32 kHz crystal
Connect 32 kHz crystal
Power supply for 32 kHz oscillator only
Power supply (+S.OV)
GROUND
Keyboard CLOCK 3 8 or 12 MHz output
24.007 MHz clock output
GROUND
Keyboard CLOCK 3 Frequency Select. Pull-up resistor connected
OUTPUT ENABLE. A low tri-states clock outputs. Pull-up resistor connected
Power Supply (+S.OV)
14.319 MHz clock output
CPU clock output (see decoding table)
GROUND
Power Supply (+S.OV)
Double frequency CPU clock output
CPU clock frequency SELECT 2. Pull-up resistor connected
CPU clock frequency SELECT 1. Pull-up resistor connected
CPU clock frequency SELECT o. Pull-up resistor connected

428

ICS9132
BI oc kO"laaram f or ICS91 32-03

32Zr~~t:~z : (
32.768kHz_

REFERENCE
CLOCK

f-3

1
14.318 MHz_

CLOCK
~
GENERATOR

CLOCK
GENERATOR
2

1

t
SCLK3 ___
CLK3_

f

Frequency Select

r---- 2xCPU
I---- CPU

t

CLOCK
GENERATOR

CLOCK
GENERATOR
_24MHz
4

3

t

t

Output Enable -

Recommended External Circuit
20
19
18
17

VODX

;:;
en
....""w

VDD

(NO~~~~~

16
15

N

14
13
12

o11!F

11

10

NOTES:
(1) The external components shown should be placed as close to the device as possible.
(2) Pins 5 and 16 should be connected together externally.
One decoupling capacitor may suffice for both pins.
(3) May be part of system decoupling.

429

ICS9132
ICS9132-16 Decoding Tables

Pin Configuration

CPU CLOCK
32kHz

SCLK20

X2

SCLK21

Xl

SCLK22
CPU (CLK 24)

VDD32
VDD

VOD

GND

GND

40095

20048

24 006 MHz

14319

SCLK22
Pin 18
0
0
0
0
1
1
1
1

SCLK21
Pin 19
0
0
1
1
0
0
1
1

SCLK20
Pin 20
0
1
0
1
0
1
0
1

CPU (MHz)
Pin 17
OFF
8.055
9.980
11.858
OFF
50.119
60.006
66.617

~mooth

/

transitions

~mooth

/

transitions

VDD(VCCA)

12003

GND _ _ _ _ _ _ _ _ _ _c- PD'

Pin Description for ICS9132-16 (5V operation. 3V available upon request)
Pin
Name
32kHz
X2
Xl
VDD32
VDD
GND
40.095 MHz
24.006 MHz
12.003 MHz
GND
PD*
VDD
14.319 MHz
20.048 MHz
GND
VDD
CPU
SCLK22
SCLK21
SCLK20

Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13

14
15
16
17
18
19
20

Pin
type
Output
Output
Input

Output
Output
Output

Input

Output
Output

Output
Input
Input
Input

Description
32.768 kHz output
Connect 32 kHz crystal
Connect 32 kHz crystal
Power supply for 32 kHz oscillator only
Power supply (+5.0V)
GROUND
40.095 MHz SCUZZY clock output
24.007 MHz clock output
12.003 MHz keyboard clock output
GROUND
POWER DOWN. Forces all outputs low except 32 kHz
Power Supply (+5.0V)
14.319 MHz clock output
20.048 MHz clock output
GROUND
Power Supply (+5.0V)
CPU clock output (see decoding table)
CPU clock frequency SELECT 2. Pull-up resistor connected
CPU clock frequency SELECT 1. Pull-up resistor connected
CPU clock frequency SELECT o. Pull-up resistor connected

430

ICS9132
Pin Configuration

ICS9132-18 Decoding Tables
CPU CLOCK
SCLK20

X2

SCLK2l

Xl

SCLK22
2XCPU

VDD32

VDD

VDD

GND

GND

CPU

8 002 MHz

14319 MHz

24 007 MHz

SCLK22
Pin 18
0
0
0
0
1
1
1
1

SCLK21
Pin 19
0
0
1
1
0
0
1
1

SCLK20 2xCPU(MHz) CPU (MHz)
Pin 20
Pin 17
Pin 14
59.999
0
29.999
1
16.002
8.001
0
25.056
12.528
1
33.255
16.627
39.992
0
19.996
1
49.896
24.948
66.610
0
33.305
1
80.012
40.006

VDD

GND

OE

PD"

Pin Description for ICS9132-18 (5V operation. 3V available upon request)
Pin
Name

Pin

32kHz

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

X2

Xl
VDD32
VDD
GND
8.002 MHz
24.007 MHz
GND
PD*
OE
VDD
14.319 MHz
CPU
GND
VDD
2xCPU
SCLK22
SCLK21
SCLK20

#

Pin
type
Output
Output
Input
-

Output
Output
-

Input
Input

Output
Output
-

Out}:mt
Input
Input
Input

Description
32.768 kHz output
Connect 32 kHz crystal
Connect 32 kHz crystal
Power supply for 32 kHz oscillator only
Power supply (+5.0V)
GROUND
8.002 MHz keyboard clock output
24.007 MHz clock output
GROUND
POWER DOWN. All outputs go low except 32 kHz
OUTPUT ENABLE. A low tri-states clock outputs. Pull-up resistor connected
Power Supply (+5.0V)
14.319 MHz clock output
CPU clock output (see decoding table)
GROUND
Power Supply (+5.0V)
Double frequency CPU clock output
CPU clock frequency SELECT 2. Pull-up resistor connected
CPU clock frequency SELECT 1. Pull-up resistor connected
CPU clock frequency SELECT O. Pull-up resistor connected

431

ICS9132
Absolute Maximum Ratings
Storage temperature................................ -40°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
toVDD+O.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. DoC to +70°C

Note: Stresses above those lISted under Absolute Maximum ratings may cause permanent damage to the device. Tins IS a stress rating only and
functional operation of the devices at these or any other conditions above those indicated m the operational sections of this specification IS not
Implied. Exposure to absolute maxunum condihons for extended periods may affect devices reliability.

Electrical Characteristics
(VDD = +3.0 to 3.7V, T A

Symbol

= DoC to 70°C unless otherwise stated)

Parameter

Min

Typ

Max

Units

-

0.2Voo

-

V
V

-

.005

0.05

V
V
V
V
%

Conditions

DC Char... · ·•.....istics
VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
Fo
Isc
Icc

~

Input Low Voltage
Input High Voltage
O·7VDO
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-·IV
Output High Voltage
Output High Voltage
2.4
Output Frequency Change
over Supply and Temperature
Short circuit current
Supply Current
Pull-up resistor value

-

-2*
2*
0.1

~
~

Voo = 3.3V
Voo = 3.3V
VIN=OV
VIN=Voo
IOL =4mA
IOH= -lrnA,Voo=3.3V
IOH= -4rnA,Voo =3.3V
1IOH= -8mA
With respect to
typical frequency
Eacn output clock
No load, 40 MHz

15
10
620

rnA
rnA
kQ

-

IlS
Ils
ns
ns
ns
ns
%
%
%
%
kHz
ps

15 pfload
15pfload
15 pfload
15pfload
15 pf load
15 pf load (Note 1)
As compared with
clock period

m,.

From off to 40 MH7.

~C Characteristics
tIC,
t ICf
t,
t,
tf

j

t

dt
t)I'

}ab
t'k
t

Input Clock Rise Time
Input Clock Fall,Time
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V00
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% V00
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
.Power UD time

-

43/57
40/60
25

5
5
1.5
2
4
2.5
1.5
2
2.5
4
48/52 57/43
43/57 60/40
1
3
2
5
32.768
40
100
500
-

10

Note 1: 32 kHz output duty cycle is dependent on crystal used.

432

ICS9132

Electrical Characterisitics
(VDD = +5V± 10%, TA

Symbol

= ooe to 70 e unless otherwise stated)
0

Parameter

Min

Typ

Max

Units

-

0.2VDD

.005

0.05

V
V
IlA
IlA
V
V
V
V
%

Conditions

DC Characteristics
VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
FD
Isc
Icc
Rpu

Input Low Voltage
Input High Voltage
O·7V DD
Input Low Current
Input High Current
Output Low Voltage
VDD-.1V
Output High Voltage
Output High Voltage
Output High Voltage
2.4
Output Frequency Change
over Supply and Temperature
Short circuit current
Supply Current
Pull-up resistor value

-

-2*
2*
0.1

-

33
17
3S0

rnA
rnA
kQ

VDD = 3.3V
VDD = 3.3V
VIN=OV
VIN = VDD
IOL =4mA
IoH = -lmA,VDD =3.3V
IOH = -4mA,VDD=3.3V
lIoH = -SmA
With respect to
typical frequency
Each output clock
No load, 40 MHz

AC Characteristics
tIC'
t ICI
t,
t,
tf
tf
dt
dt
tII>

?'b

·t
t pu

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% VDD
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VDD
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power up time

-

43/57
40/60
25

1
2
1
2
4S/52
43/57
1
2
32.76S
100
5

Note 1: 32 kHz output duty cycle is dependent on crystal used.

433

5
5
1.5
3
1.5
3
57/43
60/40
3
5
40
500

IlS
Ils
ns
ns
ns
ns
%
%
%
%
kHz
ps

25 pfload
25 pfload
25 pfload
25 pfload
25 pf load
25 pf load (Note 1)
As compared with
clock period

ms

From off to SO MHz

ICS9132
32 kHz Supply Current
14

I-tA

12

C L = 25pF

10

C L = 15pF

B
6

CL

= OpF

4

2

O+---~~--~----~----~----~--~

o

3

2

4

5

6

Vdd

Ordering Information
Part Number
ICS9132-xxCN20
ICS9132-xxCW20

Temperature Range

Package Type

O°C to +70°C
O°C to +70°C

20 lead Plastic DIP
20 lead SOIC

-xx

Application

-01

Notebook
Desktop

-03

Features
Contains power down
Tri-state outsputs, 2xCPU

434

ICS9133

Integrated
Circuit
Systems, Inc.

•

Advance Information

32 kHz Motherboard Frequency Generator
Different frequencies from clocks #2 and #3 can be
selected using the frequency select pins, but clock #1 will
be at 14.318 MHz for all standard versions.

Features
• Single 32.768 kHz crystal generates all PC
motherboard clocks
• Cost-reduced version of popular ICS9132
• 3 independent clock generators
• Generates CPU clocks from 12.5 to 100 MHz
• Up to 7 output clocks
• Separate VDD for 32 kHz clock
• Output enable tri-states outputs
• Power down options available
• Operates from 3.3V or 5.0V supply
• Operates up to 66 MHz at 3.3V
• Skew controlled 2x and Ix CPU clocks
• 20 pin PDIP or SOIC package

VDD32 Supply
The ICS9133 has a separate power supply for the
32.768 kHz oscillator circuitry. This allows the 32 kHz
clock to run from a battery or other source while the main
power to the chip is disconnected. The VDD32 supply is
guaranteed to operate down to +2.0V, with the clock
consuming less than lOJ.1A at +3.3V with the main VDD
atOV.
The frequencies and power down options in the ICS9133
are mask programmable. Customer specific masks can
be made and prototypes delivered within 6 - 8 weeks
from receipt of order. Integrated Circuit Systems also
offers standard versions, such as that described in this
data sheet.

General Description
The ICS9133 is designed to generate clocks for all 286,
386,486,PentiumandRISCbasedmotherboards,including laptops and notebook computers. The only external
components required are a 32.768 kHz crystal, crystal
components, and decoupling capacitors. The device
generates the 14.318 MHz system clock, eliminating the
need for a 14.318 MHz crystal. High performance applications may require high speed clock termination components. The chip includes three independent clock
generators plus the 32.768 kHz reference clock to produce all necessary frequencies, including real time clock/
DRAM refresh, master clock, CPU clock, twice CPU
clock frequency, keyboard clock, floppy disk controller
clock, serial communications clock and bus clocks.

Applications
Notebook I Palmtop Computers: The ICS9133 works
with +3V and +5V and a single 32.768 kHz crystal,
making it the ideal solution for generating clocks in
portables with minimum board space. The user can save
power by using this single part instead of oscillators or
other frequency generators. The ICS9133 further reduces
the current consumption by having the ability to
completely shut down the individual clocks when not in
use, while still maintaining the separately powered
32.768 kHz clock.

BI oc kD·lagram

I
32.768 kHz ..J:"""
crystal ~
32.768kHz _

REFERENCE
CLOCK

14.318 MHz

•

CPUCLK
_
CLOCK
GENERATOR
2
-2XCPUCLK

CLOCK
GENERATOR
1

I
~

43S

CLOCK
_
GENERATOR
3

PERIPHERAL
CLOCKS

I

ICS9133

Decoding Table for CPU Clock

Pin Configuration
32kHz

SCLKO

X2

SCLKl

Xl

SCLK2

SCLK21

SCLK20

2XCPU

CPU

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

8
16
32
40
50
66.6
80*
100*

4
8
16
20
25
33.3
40*
50*

CPU

VDD32

2XCPU

VDD

eND

VDD

l6MHz

eND

24MHz

14318MHz

12MHz

VDD(VCCA)

eND

SCLK22

~

_ _ _ _ _-.r-

* Only at 5V supply voltage

OE

P'In DeSCriDIIOn
r for ICS9133
Pin Name
32kHz
X2
Xl
VDD32
VDD
GND
16MHz
24MHz
12MHz
GND
OE
VDD
14.318MHz
GND
VDD
2XCPU
CPU
SCLK2
SCLK1
SCLKO

Pin # Pin type Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Output
Output
Input
-

32.768 kHz output
Connect 32 kHz crystal
Connect 32 kHz crystal
Power supply for 32 kHz oscillator only
Power supply (+3.3 - +5.DV)
GROUND

Output
Output

16 MHz clock output
24 MHz clock output

Output

12 MHz clock output
GROUND
OE tristate outputs when low
Power Supply (+3.3 to +5.0V)

-

Input
-

Output
-

Output
Output
Input
Input
Input

14.318 MHz clock output
GROUND
Power Supply (+3.3 to +5.0V)
2XCPU clock out£ut (see decoding table)
CPU clock output (see decoding table)
CPU clock frequency SELECT 2
CPU clock frequency SELECT 1
CPU clock frequency SELECT 0

436

ICS9133
Block Dia ram for ICS9133-01
32:~:~Z
32.768 kHz

0

REFERENCE
CLOCK

Frequency Select
OUTPUT
BUFFERS

14.318 MHz
CLOCK
GENERATOR

2XCPU
CPU CLOCK
CPU
OE

14.318 MHz
16 MHz
PERIPHERAL
CLOCKS

OUTPUT
BUFFERS

-12MHz
_ 2 4 MHz

Recommended External Circuit

NOTES:
(1) The external components shown should be placed as close to the device as possible.
(2) Pins 5 and 15 should be connected together externally.
One decoupling capacitor may suffice for both pins.
(3) May be part of system decoupling.

437

m

ICS9133
ABSOLUTE MAXIMUM RATINGS
Voltage on I/O pins referenced to GND ...... GND -O.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to GND ................................................ 7V
Operating temperature under bias............. O°C to +70°C
Storage temperature ................................ -40°C to +150°C

Note. Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification IS not
implied. Exposure to absolute maxnnum conditIOns for extended periods may affect devices reliability.

Electrical Characteristics
(VDD = +3.0 to 3.7V, T A

Symbol

DC Chal
VIL
VIH
III
IIH
VOL
VOH
VOH
VOH
Fo
Isc
Icc

~

= O°C to 70°C unless otherwise stated)

Parameter

Min

Typ

Max

Units

-

0. 2Voo

V
V
~
liA
V
V
V
V
%

Conditions

istics
Input Low Voltage
Input High Voltage
O· 7Voo
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-·IV
Output High Voltage
Output High Voltage
2.4
Output Frequency Change
over Supply and Temperature
Short circuit current
Supply Current
Pull-up resistor value

-

-

-2*
2*
0.1

-

-

-

.005

0.05

15
10
620

rnA
rnA
kQ

Voo= 3.3V
Voo = 3.3V
VIN=OV
VIN = Voo
IOL =4rnA
IoH = -lrnA,Voo=3.3V
IoH = -4rnA,Voo=3.3V
lIoH =-8rnA
With respect to
typical frequency
Each output clock
No load, 40 MHz

AC Characteristics
tIC,
t ICf
t,
t,
tf
tf
d,
d,
tjl'

(b

T,k
t pu

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V00
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% V00
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power up time

-

43/57
40/60
25

-

1.5
2.5
1.5
2.5
48/52
43/57
1
2
32.768
100
10

Note 1: 32 kHz output duty cycle is dependent on crystal used.

438

5
5
2
4
2
4
57/43
60/40
3
5
40
500

lis
lis
ns
ns
ns
ns
%
%
%
%
kHz
ps

15pfload
15pfload
15 pfload
15 pf load
15 pf load
15 pf load (Note 1)
As compared with
clock period

ms

From off to 40 MHz

ICS9133

Electrical Characteristics
(V DD = +5V± 10%, T A

Symbol

= O°C to 70°C unless otherwise stated)
Parameter

Min

Typ

Max

Units

-

0.2VDD

V
V

.005

0.05

Conditions

DC Characteristics
VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
FD
Isc
Icc
~u

Input Low Voltage
Input High Voltage
O·7VDD
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
VDD-·IV
Output High Voltage
Output High Voltage
2.4
Output Frequency Change
over Supply and Temperature
Short circuit current
Supply Current
Pull-up resistor value

-

-2*
2*
0.1
-

33
17
380

~A
~A

V
V
V
V
%
rnA
rnA
kQ

VDD = 3.3V
VDD = 3.3V
VIN=OV
VIN = VDD
IOL =4mA
IoH = -lmA,V DD =3.3V
IOH = -4mA,VDD=3.3V
IoH = -8mA
1 With respect to
typical frequency
Each output clock
No load, 40 MHz

AC Characteristics
tIC,
tIC!
t,
t

t;

tf
d,
d,
tjl,

}ab
T5k
t

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power up time

-

-

-

-

-

-

43/57
40/60
25

1
2
1
2
48/52
43/57
1
2
32.768
100
10

Note 1: 32 kHz output duty cycle is dependent on crystal used.

439

5
5
1.5
3
1.5
3
57/43
60/40
3
5
40
500

~s
~s

ns
ns
ns
ns
%
%
%
%
kHz
ps

15 pfload
15 pfload
15 pfload
15 pf load
15 pf load
15 pf load (Note 1)
As compared with
clock period

ms

From off to 80 MHz

ICS9133
32 kHz Su

Current
14

C L =25pF

12

10

IlA

CL = 15pF

B

CL = OpF

6
4

2
O+---~----~----+---~----~--~

o

2

3

4

5

6

Vdd

Ordering Information
Part Number
lCS9133-01CN20
ICS9133-01 CW20

Temperature Range

Package Type

WC to +70"C
O°C to +70°C

20 lead Plastic DIP
20 lead SOlC

440

II

AV9140

Integrated
Circuit
Systems, Inc.

R4000 Frequency Generator
Features
•
•
•
•
•
•
•
•
•

Pin Configuration

Ideally suited for R4000 family clock source
Meets high and low time specifications
Uses inexpensive 14.318 MHz reference crystal
Selectable 50, 75 or 100 MHz output frequency
Patented on-chip Phase Locked Loop with VCO
for clock generation
Power down frequency selection
8 pin DIP or SOIC package
Low power CMOS technology
+5 volt power supply

FSG u 8 REFOUT
GND
2
7 VDD
Xl
3
6
CLKOUT
X2
4
5
FSl
AV9140-01
8 pin DIP, SOIC

Decoding Table for AV9140-01

General Description
The AV9140 offers a small and inexpensive solution for
generating an R4000 processor series master clock. It
generates a selectable output frequency of 50, 75 or
100 MHz and generates an output waveform compatible
with R4000 series master clock specifications. Output
frequency is derived from a 14.318 MHz reference input
clock using PLL techniques. The 14.318 reference clock
can be either a discrete quartz crystal or a TTL clock
signal.

Output
Frequency

Input
Selection

The device includes an on-chip loop filter for the PLL
circuit. Required external components include two
decoupling capacitors and an optional ferrite bead for
power supply conditioning, and two external load
capacitors when a crystal reference is used. Custom
masked versions, with customized frequencies and
features, are available in 6-8 weeks for a small NRE.

FS1

FSO

Desired
CLKOUT
Frequency
(MHz)

Actual
CLKOUT
Frequency
(MHz)

0
0
1
1

0
1
0
1

OFF
50
75
100

OFF
50.113
74.959
100.227

Block Dia ram
FS1
FSO

FREQUENCY
LOOKUP TABLE
ANDPLL
--i--~ CONTROL LOGIC

CLKOUT

Xl
REFOUT
X2

441

AV9140
Pin Description
Pin
Name

Pin #

Pin Type

FSO
GND
Xl

1
2
3

Input
Input

X2
FS1
CLKOUT
VDD
REFOUT

4
5
6

Output
Input
Output

-

7

-

8

Output

Description
FREQUENCY SELECT for CLKOUT
GROUND
CRYSTAL INPUT or INPUT CLOCK frequency. Typically
14.318MHz system clock
CRYSTAL OUTPUT
FREQUENCY SELECT for CLKOUT
CLOCK OUTPUT
Power Supply (+5V DC)
REFERENCE CLOCK 14.318 MHz OUTPUT

Input Reference

Frequency Accuracy

The reference frequency of 14.31818 MHz was chosen
since this is a common system frequency. Quartz crystals cut to this frequency are readily available and
inexpensve. When using the AV9140 with a quartz
crystal, the crystal is connected between pins Xl and X2.
Appropriate load capacitors are also connected from Xl
to ground and from X2 to ground, depending on crystal
requirements. The AV9140 has an input capacitance of
approximately 2.5 pF to ground at both Xl and X2. Refer
to the quartz crystal data sheet for total load capacitance
requirements.

The AV9140 uses PLL (Phase-Lock-Loop) circuitry to
establish the output frequency which is based on a fixed
ratio of the input frequency. The actual frequencies
shown in the AV9140-01 decoding table are for when
14.31818 MHz is used as a reference frequency. Any
percent error of this reference frequency will result in the
same percent error in the output frequency.

When driving the AV9140 with an external clock, Xl is
used as the clock input and pin X2 is left unconnected.

Power Down
When "OFF" is selected by FS2 and FS3, the chip goes into
a power down mode.

442

•

AV9140

Absolute Maximum Ratings
Storage temperature ................................ -65°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
toVDD+O.5V
Power dissipation ................................................ 0.5 Watts

AVDD, VDD referenced to GND ................................. 7V
Operating temperature under bias............. O°C to +70°C

Note. Stresses above those listed under Absolute Maxnnum Ratmgs may cause permanent damage to the device. This is a stress ratmg only, and
functional operation of the devices at these or any other conditions above those indicated m the operahonal sechons of this specification IS not
nnplied. Exposure to absolute maximum condlhons for extended penods may affect the rehablhty of the device.

Electric Characteristics
(Operating V DD

Symbol

= +4.5V to +5.5V, T A = O°C to 70°C unless otherwise stated)
Parameter

Min

Typ

Max

-

-

0.8

Units Conditions

DC Characteristics

vlL

VIH
IlL
I

~L

VOH

~~

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current
Supply- Current
Input Ca~acitance
Standby upply Current

~~TDBY
AC Characteristics

~
rItLK
ICLK;
thd

~:

t,

j

t

tol

~:

t Jabs

t"pu

Enable pulse width
Setup hme data to enable
Output Frequency
Input Frequency
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V
Output Fall time, 2.0 to (J:SV
Fall time, 80% to 20% VDD
Output Duty cycle
Output Low time @ 75 MHz
Output High time @ 75 MHz
Jitter, 1 sigma
Jitter, absolute
Frequency Transition time
Power up time

-

V
V
IlA
V
V

10
15

-

-

-

20
30
10

25

-

20
20
8
2

-

-

2.0
-5
-5

-

.8VDD

-

10

-

-

14.318
-

5
5
.2VDD

100
30
20
20
-

1
1.5
1
1.5
48/52

2
3
2
3
60

-

-

-

60
±250

-

15

150
±450
20
30

-

-

40
3
3
-

-

!LA

VDD = 5V
VDD = 5V
VIN =OV
VIN=VDD

rnA
rnA

Note 1
Note 2

pF
IlA

Ex~tXl

ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ms
ms

"0

' selected

(Recommended)
(Recommended)
15 pfload
15 pfload
15 pfload
15 pfload
15 pf load, Note 3
15 pfload
15 rlload
Al frequencies
All fre~encies
From 5 to 100 MHz
From off to 100MHz

Notes
1. AV9140 with no load, with 14.318 MHz crystal input, and CLKI running at 75'MHz. Power supply current
varies with frequency. Consult Avasem for actual current at different frequencies.
2. AV9140 with 15 pF load on CLKOUT and REFOUT, CLKOUT = 100 MHz.
3. Output Duty Cycle measures using threshold voltage of 1.4 volts.

443

AV9140
Od
r ermg If
n ormation
Part Number

Part Marking

Temperature Range

Package Type

AV9140-0lCN8
AV9140-01CS8
AV9140-01CS8T&R

AV9140-01
AV40-1
AV40-1

O°C to +70°C
O°C to +70°C

8 lead Plastic DIP (300 mils)
8 lead SOIC (150 mils)
8 SOIC Tape and Reel (1000/reel)

----

444

AV9154

Integrated
Circuit
Systems,Inc.

•

Low Cost 16 Pin Frequency Generator
Features

General Description

• Compatible with 286, 386, and 486 CPUs
• Generates up to 6 output clocks for CPU plus
peripherals
• Up to 100 MHz
• All loop filter components internal
• Skew controlled 2X and IX CPU clocks
• 3V and 5V versions
• 16 pin PDIP or 150 mil wide SOIC
• Power down options

The AV9154 is a low cost frequency generator designed
for general purpose PC and disk drive applications. Its
CPU clocks provide all necessary frequencies for 286,
386 and 486 systems, including support for the latest
speeds of processors. The stancfard devices use a 14.318
MHz crystal to generate the CPU and peripheral clocks
for integrated cfesktop and notebook motherboards.
The CPU clock offers the unique feature of smooth,
glitch-free transitions from one frequency to the next,
making this the ideal device to use wnenever slowin~ the
CPU speed. The AV9154 makes a gradual transition
between frequencies, so that it obeys the Intel cycle to
cycle timing specification for 486 systems.

Applications
Computer Motherboards· The AV9154 replaces crystals
and oscillators, saving board space, component cost,
part count, and inventory costs. It produces a switchable
CPU clock, and up to four fixed clocks to drive floppy
disk, communications, super I/O, bus, and I or keyboard
devices. The small package and 3V operation is perfect
for handheld computers.
Disk Drjyes; The low profile, narrow SOIC package
makes this a popular cfevice for replacing expensive
surface mount oscillators in space-critical disk drives.

Block Dia ram for AV9154

VDD

GNP

The simultaneous 2X and IX CPU clocks offer controlled
skew to within 1.Ons (max) of each other.
lCS has been shipfing Motherboard Frequency
Generators since Apri 1990, and is the leader in the area
of multiple output clocks on a single chip. The AV9154
uses the same technology as lCS's highly successful
AV9107 and AV9155 products. lCS offers a broad family
of frequency generators for motherboards, graphics and
other applications, including cost effective versions with
oniyoneortwooutputciocKs. ConsultlCSforallofyour
clock generation needs.

AVDD

AGNP

,________ J ___ J _________ 1 ___ J __________ .,,
3-4

FSO-3

14.318 MHz

CPU
CLOCK

OUTPUT
BUFFERS

REFERENCE
CLOCK
PERIPHERAL
CLOCKS

2XCPU
:-CPU

KBCLK
BUSCLK
FDCLK
COMMCLK

OUTPUT
BUFFERS

----------------------------------f-----PD

Pentium'l1ol is a trademark of Intel Corporation

445

AV9154
Pin Configurations
FSl

FSO

FS2

1

FSO
FSl

15

2XCPUCLK

X2

2

14

CPUCLK

Xl

3

VDD

VDD

4

12

GND

GND

5

6

11

14.318MHz

16 or 32MHz

6

14.318MHz

8MHz

7

10

FS2

8MHz

7

FS3

AGND

8

9

PO"

AGND

8

PO"

X2

2

Xl

3

VDD

4

GND

5

24MHz

~
\D
......

~
I
~

15

SCLK21

14

2XCPUCLK

13

VDD

12

GND

24MHz

11

14.318MHz

12MHz

7

10

SCLK22

AGND

8

9

X2

~
\D

Xl

......

VDD

!Jl

""-

N

GND

1

X2

2

Xl

3

VDD

4

GND

5

~

\D

......
~
I
......

0

CPUCLK

...... ......
~
~
I
I
~ @

VDD
GND

SCLK20

1.84MHz

8MHz

~
~
\D
\D

'I

OE

FSO

FSO

15

FSl

X2

14

CPUCLK

Xl

13

VDD

VDD

12

GND

GND

FSl

~
\D

......
~
I
......

15

FS2

14

CPUCLK

13

VDD

12

GND

0\

16MHz

6

11

24MHz

24MHz

11

14.318MHz

1.84MHz

7

10

14.318MHz

12MHz

10

PDCPU

AGND

8

9

PDFCLK*

AGND

9

PDREF

* Active low

446

AV9154

- -

-

p.In 0 escrlptlon for AV915404 05" -10" -16" -25 27
~,

Pin
Name

Pin
Type Description

VDD
VDD
GND
GND

P
P
P
P

A(;ND

p

FSO
PSI
PS2
FS3
PDREF

I
I
I
I
I

PDCPU
PD*
PDFCLK*
Xl
X2
32MHz
24MHz
16MHz
12MHz
8MHz
1.84MHz
14.318MHz
CPUCLK

I
I
I
I

0
0
0
0
0
0
0
0
0

2XCPUCLK

0

Pin #

Digital Power (+3.3V or +5V)
Digital Power (+3.3V or +5V)
Digital GROUND
Digital GROUND
AN AT.oC (;ROlJND

FREQUENCY SELECT 0 for CPUCLK
FREQUENCY SELECT 1 for CPUCLK
FREQUENCY SELECT 2 for CPUCLK
FREQUENCY SELECT 3 for CPUCLK
POWER DOWN REFERENCE Clock
(14.318 MHz) (Active High)
POWER DOWN CPU Oock (Active Hil!h)
POWER DOWN All (Active Low)
POWER DOWN FIXED CLOCK (1.84 8 16 24)
CRYSTAL IN
CRYSTAL OUT
32 MHz clock outDut
24 MHz clock outDut
16 MHz clock outDut
12 MHz clock outDut
8 MHz clock output
1.84 MHz clock output
14.318 MHz reference clock output
CPU CLOCK output determined by status
lofFSO - FS3
2X CPU CLOCK output

*ActiveLow

447

-04

-05

-10

-16

-25

-27

4
13
5
12
8
1
16
10

4
13
5
12
8
16
15
1
10

4
13
5
12
8
16
15

4
13
5
12
8
1
16
15

-

4
13
5
12
8
16
15
1
10

4
13
5
12
8
16
15
10

-

9
10

-

-

9

-

-

9

-

-

9
-

-

-

-

9
3
2
6

3
2

3
2

3
2

-

6

6

11
6

7

7

3
2

-

6

-

-

11

-

11

1
7
10

14
15

14

14

-

-

-

-

7

-

-

-

-

-

3
2

-

6

7

7

-

11

11

1
11

14

14

-

-

-

14

II

AV9154

Clock Tables in MHz
I All Dc rts shown will oDerate at 3Vl
FS(3:0)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Floppy
Bus
Kybd
Comm
Refclk
3V

-04
2XCPU CPU
100-

50'
40'
33.325
20
16
12
8

so-

66.650
40
32
24
16

-

-

24

-05
CPUCLK

-10
CPUCLK

-16
CPUCLK

-25
CPUCLK

-27
CPUCLK

2
8
16
20
25
33.340504
16
32
40
50
66.6-

PDCPU
40
50
66.6-

16
20
25
33.3
40
50
66.6'

2
8
16
20
25
33.340504
16
32
40
50
66.6-

75
32
60
40
50
66.66
80
52

so-

100-

-

-

-

so-

-

so-

100'

-

-

24
24
24
32
16
12
8
8
12
1.84
1.84
14.318
14.3111
14.3111
14.3111
14.318
14.318
up to SO MHz up to SO MHz up to SO MHz up to SO MHz up to SO MHz up to 50 MHz

8
-

16
8

-

-

- These selections will only operate at 5V

448

-

Smooth
Transitions

Smooth
Transitions

91 .~~~
AV9154
Actual Output Frequencies
(using 14.318 MHz input. All frequencies in MHz)
-04

FS(3:0)

2XCPU CPU
0
1
2
3
4
5
6
7
8
9
A

B
C
D
E
F
Floppy

Bus
Kybd
Comm
Refclk

100.23*
SO.l8*
66.48*
50.11
40.09
32.22
24.23
15.75
-

50.11*
40.09*
33.24*
25.06
20.05
16.11
12.12
7.88

-

24.00

-

8.00
14.318

-

-05
CPUCLK

-10
CPUCLK

2.15
8.18
16.11
20.05
25.06
33.24*
40.09*
50.11*
4.30
16.11
32.22
40.09
50.11
66.48*
SO.18*
100.23*

PDCPU
40.09
50.11
66.48*
-

16.00
8.00
14.318

24.00
16.00
8.00
1.846
14.318

-

-

-16
CPUCLK

-25
CPUCLK

-27
2XCPUCLK

16.11
20.05
25.06
33.41
40.09
50.11
66.48*
80.18*
-

2.15
8.18
16.11
20.05
25.06
33.24*
40.09*
50.11*
4.30
16.11
32.22
40.09
50.11
66.48*
SO.18*
100.23*

75.17
31.94
60.136
40.09
50.11
66.48
SO.18
51.90

24.00

-

12.00

32.01
8.00

14.318

14.318

24
12
1.846
14.318

-

-

-

* These selections will only operate at 5V

449

-

-

Smooth
Transitions

Smooth
Transitions

II

AV9154
Absolute Maximum Ratings

Storage temperature ................................ -40°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
toVDD+0.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum conditions for extended periods may affect devices reliability.

Electrical Characterisitcs at 5V
(VDD- +5V+
- 10%, T'A - O°C to 70°C unless otherwise stated)

Symbol

DC

Char~

VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
100

Fo

~

<
I

Parameter

Min

Typ Maxi Units

Conditions

cteristics
Input Low Voltage
Input High Voltage
2.0
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-·4V
Output High Voltage
Vof8V
.4
Output High Voltage
Supply Current
Output Frequency Change
over Supply and Temperature
Short circuit current
25
Input Capacitance
Load Capacitance
Supply Current power down

0.8
-5
5
0.4

25
0.002

40
0.01

40
10
20
30

V
V
~

IlA
V
V
V
V
rnA
%
rnA
pF
pF
I.J.A

Voo=5V
Voo=5V
VIN=OV
VIN = Voo
IOL =4rnA
IOH= -lrnA,Voo=5.0V
IOH = -4rnA,Voo=5.0V
IOH= -SmA
lNoload
With respect to
typical frequency
Eacll output clock
Except Xl, X2
Pins Xl, X2

AC Characteristics
tiC,
tlCf
t
t'
t;
tf
d,
d,
tjlS
tjab

}ab
Tsk
th

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% V
Output Fall time, 2.0 to
Fall time, SO% to 20% V00
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Jitter, absolute
Input Frequency
Clock skew between CPU and
2XCPU outputs
Frequency Transition time

B:sv

40/60
40/60

14.318
0.5

1.0

ns
ns
ns
ns
ns
ns
%
%
%
%
ps
MHz
ns

15

20

ms

1

2
1
2
48/52
43/57
0.8
2

20
20
2
4
2
4
60/40
60/40
2.5
5
700

15pfload
15 pfload
15 pfload
15 pfload
15 pfload
15 pfload
As compared with
clock period
16-100 MHz clocks

From 8 to 100 MHz

AV9154-04

Notes:
1. All clocks on AV9154-05 running at highest possible frequencies. Power supply current can change substantially
with different mask configurations. Consult ICS.

450

AV9154

Electrical Characteristics at 3.3V
(Operating V DD = +2.7V to +3.7V, T A = O°C to 70°C unless otherwise stated)

Symbol

Parameter

Min

Typ

Max

Units Conditions

DC Characteristics
VIL
VIH
IlL
I

~L
V

OH
?o
d

C.

C'L
IOOSIDBY
I

Input Low Voltage
Input High Voltage
O· 7Voo
Input Low Current
-5
-5
Input High Current
Output Low Voltage
Output High Voltage
Voo-·IV
15
Supply Current
0.002
Output Frequency Change
over Supply and Temperature
Input Capacitance
20
LOad 06acitance
15
Supply urrent, Standby
Short Circuit Current
30

0.15Voo

V
V

5
5
0.1

~
V

-

-

V
rnA

0.01

%

10

pF
pF
~

VIN=OV

VIN=~

I

=8

f L=_4rnA
mtel
With respect to
typical frequency
Exce'Xt Xl, X2
Pins I, X2
When powered down

rnA

AC ChA .... ,....... '· ....
tw
t
ItLK
ICLK;
~
t

~

T~.

~:bs

tft

fur.

Enable pulse width
Setup time data to enable
Input Clock Rise time
Input Clock Fall time
Hold time data to enable
Rise time
Fall time
Duty cycle
Jitter, 1 sigma
Jitter, absolute
Frequency Transition time
Power uJ: time
Output requency
Input Frequencv

-

20
20

-

10

-

40

48/52
±D.5
±3

-

20
20
-

4
4
60
±2
±5
20

15
2
2

14.318

50
32

ns
ns
ns
ns
ns
ns
ns
%
%
%

ms
ms
MHz
MHz

15 pfload
15 pfload
15 ~f load
Al frequencies
All frequencies
From 2 to 25 MHz
From off to 50 MHz

Note 1: AV9154 with no load, with 14.318 MHz crystal input, and CLKI running at 40 MHz. Power supply
current varies with frequency. Consult ICS for actual current at different frequencies.

451

II

AV9154

AV9154
Recommended External Circuit
+5V

t

FB

l..CJte#4)

2.2~FI

14.318 MHz crystal

1

X2

'-------12
1....-_ _...:.X
.:.:1---j 3
~_.......;V~D~D:""-_ _--1 4

O.l~I

~G",-,ND=-_ _-l

AGND
r _ _- ;

5

6
7

8

16
15
14
VDD
1 3 1 - - - - - - -.....
GND
121------...;=-,
11

10
9

Notes:
1. Avasem recommends the use of an isolated ground plane for the AV9154.
All grounds shown on this drawing should be connected to this ground plane.
This ground plane should be connected to the system ground plane at a single point.
Please refer to AV9154 Board Layout diagram.

2. A single power supply connection for all VDD lines at the 2.2 ~ decoupling
capacitor is recommended to reduce interaction of analog and digital circuits. The
0.1 ~ decoupling capacitors should be located as close to each VDD pin as possible.
3. A 33 n series termination resistor should be used on any clock output which drives
more than one load or drives a long trace (more than about 2 inches), especially when
using high frequencies (>50 MHz). This termination resistor is put in series with the
clock output line close to the clock output. It helps improve jitter perfomance and reduce
EMI by damping standing waves caused by impedance mismatches in the output clock
circuit trace.
4. The ferrite bead does not enhance the performance of the AV9154,
but will reduce EMf radiation from the VDD line.

452

•

AV9154

AV9154 Recommended Board Layout
PIN 1

XTAL

--4-F.f-- FB

Gap in Ground Plane

A V9154 Ground

-EJ=

=-+

~ = connection to

W

- System Ground -

To
System
VDD

ground plane

This is the recommended layout for the AV9154 to maximize clock performance. Shown are
the power and ground connections, the ground plane, and the input/ output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high
frequency ground and system noise from propagating through the device. When compared
to using the system ground and power planes, this technique will minimize output clock jitter.
The isolated ground plane should be connected to the system ground plane at one point, near
the 2.2J.IF decoupling cap. For lowest jitter performance, this isolated ground plane should
be kept away from clock output pins and traces. Keeping the isolated ground plane area as
small as possible will minimize EMI radiation. Use a sufficient gap between the isolated
ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD
line optional, but will help reduce EML
The traces to distribute the output clocks should be over a system ground or power supply
plane. The trace width should be about two times the thickness of the PC board between the
trace and the underlying plane. These guidelines help minimize clock jitter and EM!
radiation. The traces to distribute power should be as wide as possible.

453

AV9154
Ordering Information
Part Number
AV9154-xxCNI6
AV9154-xxCSI6

Temperature Range
O'C to +70'C
O'C to +70'C

Package Type
16 lead Plastic DIP
16 lead 150 mil wide SOIC

Note: The dash number following AV9154, (denoted by xx above) must be included when ordering product, since
it specifies the options being ordered.

Part Marking
ICS
AV9154-xxCx16
Date code/Lot code

454

II

AV9154-06/60

Integrated
Circuit
Systems, Inc.

OPTi Notebook Frequency Generator
Features

General Description

•
•
•
•
•
•

The AV9154 is a low cost frequency generator designed
for general purpose PC and disk drive applications. Its
CPU clocks provide all necessary frequencies for 286,
386 and 486 systems, including support for the latest
speeds of processors. The standard devices use a 14.318
MHz crystal to generate the CPU and peripheral clocks
for integrated desktop and notebook motherboards.

Compatible with 286, 386, and 486 CPUs
Up to 66.6 MHz (-60) or 80 MHz (-06) CPU clocks
All loop filter components internal
3V and 5V operation
16 pin 150 mil wide SOIC
Power down control of CPU clock

The A V9154-06 and AV9154-60 are specifically designed
for use with OPTi core logic chip sets. The only noticeable
difference between the two parts is in their CPU clock
selection tables as shown on page 3.

Applications
Computer Motherboards: The A V9154 replaces crystals
and oscillators, saving board space, component cost,
part count, and inventory costs. It produces a switchable
CPU clock, and up to four fixed clocks to drive floppy
disk, communications, super I/O, bus, and/or keyboard devices. The small package and 3V operation is
perfect for handheld computers.

The AV9154-06 and AV9154-60 can operate at 5.0V±10%
or 3.3V±1O%, but the CPU frequencies are limited (see
the asterisks on the selection tables on page 3) during
3.3V operation. The parts have two power down pins.
One shuts off the CPU clock to a low state when the
power down pin is taken high, and the other turns off the
14.318 MHz output in the same manner.

Block Dia ram for AV9154-06/60

VlD

G-1'JD

~---------------.------ ------------.i.--------------------------------------------------------------------------.
FSO-2

CPU
CLOCK

PDCPUCLK

14.318 MHz
PD14

REFERENCE
CLOCK

~

OUTPUT
BUFFER

CPUCLK

OUTPUT 1----iH.... 24 MHz
BUFFER
PERIPHERAL
CLOCKS
OUTPUT
BUFFER

-----------------------------------------------------------------------------------------------------------------~

455

128kHz

I

•

AV9154-06/60

Pin Configurations
FSO

1

16

FS1

X2

2

15

FS2

Xl

3

14

CPUCLK

VDD

4

............

13

VDD

GND

5

""''''''

12

GND

24MHz

6

11

14.318MHz

128kHz

7

10

POCPUCLK

AGND

8

9

»
«
\0\0

(J] (J]
I

I

0\ 0
00\

PD14

-

p.In Descnptlon for AV9154 06/60
PIN
NAME
FSO
X2

Xl
VDD
GND
24MHz
128kHz
AGND
PD14
PDCPUCLK
14.318MHz
GND
VDD
CPUCLK
FS2
FS1

PIN
#

PIN
TYPE

1
2
3
4
5
6

I
0
I
P
P
0
0
P
I
I
0
P
P
0
I
I

7

8
9
10
11
12
13
14
15
16

DESCRIPTION
FREQUENCY SELECT 0 for CPUCLK
Crvstalout. Connect a 14.318 MHz crystal to this Din
Crystal in. Connect a 14.318 MHz crystal to this pin
Di!!:ital Power (+3.3V or +5V)
Di!!:ital GROUND
24 MHz clock output
128 kHz clock output
ANALOG GROUND
POWER DOWN 14.318 MHz outout (Active H~hl
POWER DOWN CPU CLOCK (Active Hi!!:h)
14.318 MHz reference clock ou~ut
Digital GROUND
Di!!:ital Power (+3.3V or +5V)
CPU CLOCKmlIDuUietennined ~status of FSO - FS2
FREOUENCY SELECT 2 for CPUCLK
FREQUENCY SELECT 1 for CPUCLK

456

•

AV9154-06/60

Clock Tables for AV9154-06/60
(in MHz)
FS(2:0)
0
1
2
3
4
5
6
7

-06

-60

CPUCLK
16
20
25
33.33
40
50
66.66
80*

CPUCLK

8
16
20
25
33.33
40*
50*
66.66*

Actual Output Frequencies
(in MHz)
FS(2:0)
0
1
2
3
4
5
6

7

-06

-60

CPUCLK

CPUCLK

16.11
20.05
25.06
33.24
40.09
50.11
66.48
80.18*

8.182
16.11
20.05
25.06
33.24
40.09*
50.11*
66.48*

* These selections will only operate at 5V

457

•

AV9154-06/60

Absolute Maximum Ratings
Storage temperature ................................ -40°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
toVDD+0.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C

Note. Stresses above those lIsted under Absolute Maximum ratings may cause permanent damage to the device. This IS a stress rating only and
funclional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification IS not
implied. Exposure to absolute maximum condllions for extended periods may affect devices reliability.

Electrical Characterisitcs at 5V
(VDD

= +5V± 10%, T A = O°C to 70°C unless otherwise stated)
Parameter

Symbol

Min

Typ Max I Units

Conditions

DC Characteristics
VIL
VIR
IlL
IIH
VOL
VOH
VOH
VOH
100

Fo
Isc
C

<

IOOSTBY

Input Low Voltage
Input High Voltage
2.0
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo -·4V
Output High Voltage
Von-·8V
2.4
Output High Voltage
Supply Current
Output Frequency Change
over Supply and Temperature
Short circuit current
25
Input Capacitance
Load Capacitance
Supply Current, lowest

25
0.002

0.8

V
V

-5
5
0.4

~A
~A

40
0.01

40
10
20
20

V
V
V
V
rnA
%
rnA
pF
pF
rnA

Voo = 5V
Voo = 5V
VIN = OV
VIN = Voo
IOL =4mA
IoH = -lmA
IOH=-4mA
IoH =-8mA
INo load
With respect to
typical frequency
Each output clock
Except Xl, X2
Pins Xl, X2
When powered down

AC Characteristics
tIC'

t ICf

t

l'
t;
tf
dt
dt
dt
T
'II'
I,b

~Iab
tft
t pu

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V
Output Fall time, 2.0 to 6'~v
Fall time, 80% to 20% V00
Duty cycle
Duty cycle, reference clock
Duty cycle, CPU clock -06
Jitter, one sigma
Jitter, absolute
Jitter, absolute
Input Frequency
Frequency Transition time
Power up time

-

40/60
40/60
40/60

1
2
1
2
48/52
43/57
42/58
±0.8
±2
14.318
15
15

20
20
2
4
2
4
60/40
60/40
60/40
±2.5
±5
700
20

Note 1. All clocks on A V9154-06 or -60 running at highest possible frequencies

458

ns
ns
ns
ns
ns
ns
%
%
%
%
%
ps
MHz
ms
ms

15 pfload
15 pfload
15 pf load
15 pf load
15 pfload
15 pfload
15 pf load
As compared with
clock period
16-80 MHz clocks
From 16 to 80 MHz
From off to 50 MHz

•

AV9154-06/60

Electrical Characteristics at 3.3V
(Operating VDD = +3.0V to +3.7V, T A = O°C to 70°C unless otherwise stated)

Symbol

Parameter

Min

Typ

Max

Units Conditions

DC Characteristics
VIL
VIH
IlL
I

~L
V

OH
?o
d

C
C'L
10m
Isc

Input Low Voltage
Input High Voltage
O· 7V oo
-5
Input Low Current
-5
Input High Current
Output Low Voltage
Output High Voltage
Voo-.IV
Supply Current
15
0.002
Output Frequency Change
over Supply and Temperature
Input Capacitance
20
Load C'6acitance
Supply urrent, Lowest
14
Short Circuit Current
30

0.15Voo

-

5
5
0.1
-

0.01
10

V
V
~A
~A

V
V
rnA
%

pF
pF
rnA
rnA

VIN = OV
VIN:: V0 5\.
IOL - 8m

~=-4mA

ote 1
With respect to
typical frequency
ExceS'ct Xl, X2
Pins 1, X2
When powered down

AC Characteristics

C

Input Clock Rise Time
Input Clock Fall Time
Rise time
Fall time
Duty cycle, fixed clocks
Duty cycle, CPU clock -06
Duty cycle, reference clock
Jitter, 1 sigma
Jitter, absolute
Frequency Transition time
Power u time
Output requency

f,

Input Frequency

tIC'
tlCf
t

~

d tt
dt
T
TIl'
Jabs

tft
t

A

-

-

40/60
40/60
40/60

48/52
42/58
43/57
±0.5
±3

20
20
4
4
60/40
60/40
60/40
±2
±5
20

15
2

33
14.318

ns
ns
ns
ns
%
%
%
%
%

ms
ms
MHz

15 pf load
15 pf load
15 pf load
15 pf load
15 pf load
All frequencies
All frequencies
From 8 to 33 MHz
From off to 50 MHz
Will operate up to 50MHz
for -06 version

MHz

Note 1: AV9154 with no load, with 14.318 MHz crystal input, and CPUCLK running at 33 MHz. Power supply
current varies with frequency. Consult ICS for actual current at different frequencies

459

•

AV9154-06/60

Ordering Information
Part Number

Temperature Range

A V9154-xxeS16

ooe to +70 e

Package Type
16 lead 150 mil wide sore

o

Note: The dash number following AV9154, (denoted by xx above) must be included when ordering product, since
it specifies the options being ordered.

460

AV9155

Integrated
Circuit
Systems,Inc.

•

Low Cost 20 Pin Frequency Generator
making this the ideal device to use whenever slowing the
CPU speed. The AV9155 makes a gradual transition
between frequencies, so that it obeys the Intel cycle to
cycle timing specification for 486 systems. The simultaneous 2X and IX CPU clocks offer controlled skew to
within 1.5ns (max) of each other.

Features
• Compatible with 286, 386, and 486 CPUs
• Supports Turbo modes
• Generates communications clock, keyboard clock,
floppy disk clock, system reference clock, bus clock
and CPU clock
• Output Enable tri-states outputs
• Up to 100 MHz
• 20 pin DIP or SOIC
• All loop filter components internal
• Skew controlled 2X and IX CPU clocks
• Power Down option

ICS offers several versions of the AV9155. The different
devices are shown below:

AV9155-02
AV9155-03

The AV9155 is a low cost frequency generator designed
specifically for desktop and notebook PC applications.
Its CPU clocks provide all necessary CPU frequencies for
286,386 and 486 systems, including support for the latest
speeds of processors. The device uses a 14.318 MHz
crystal to generate the CPU and all peripheral clocks for
integrated desktop motherboards.

AV9155-36

ICS has been shipping Motherboard Frequency Generators since April 1990, and is the leader in the area of
multiple output clocks on a single chip. The AV9155 is a
third generation device, and uses ICS's patented analog
CMOS Phase Locked Loop technology for low phase
jitter. ICS offers a broad family of frequency generators
for motherboards, graphics and other applications, including cost effective versions with only one or two
output clocks. Consult ICS for all of your clock generationneeds.

The CPU clock offers the unique feature of smooth,
glitch-free transitions from one frequency to the next,

Block Diagram for AV9155
-

-

-

-

-

-

-

~

_:
I

-

-

-

-

-

-

-

-

Includes Pentium™ freauencies
Features a special40MHz SCUZZY
clock

AV9155-23

The dual 14.318 MHz clock outputs allows one output
for the system and one to be the input to an ICS GraphiCS
Frequency Generator such as the AV9194.

SCLK2O-23

Motherboard clock generator with 16
MHz BUSCLK
Motherboard clock generator with 32
MHz BUSCLK
Special frequencies for both 386 and
486CPUs

AV9155-0l

General Description

r -

Descrintion

Part

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

--I
I

CPU
CLOCK

CPU

14.318 MHz
Crystal

14.318 MHz
14.318 MHz

CJ

I

REFERENCE
CLOCK

r-------------------~------~

GND

POWER DOWN

461

OE
KBCLK
BUSCLK
FDCLK
COMMCLK

PERIPHERAL
CLOCKS

VDD

2XCPU

AGND

•

AV9155

Pin Configuration
1.843MHz

SCLK20

1843MHz

SCLK20

X2

SCLK21

X2

SCLK21

Xl

CPU

Xl

CPU

VDD

2XCPU

VDD

GND

VDD

GND

VDD

16or32MHz

GND

32MHz

GND

24MHz

14.318MHz

24MHz

14.318MHz

12MHz

14.318MHz

12MHz

14.318MHz

AGND

PO"

AGND

PD'

OE

SCLK22

OE

2XCPU

SCLK22

- -

. f
p.In DescrlOllon
for AV915501 02
Pin Name
l.843MHz

Pin #

16MHz/32MHz
24MHz
12MHz
AGND
OE
SCLK22
AVDD
PO"'
14.318MHz
14.318MHz
GND
VDD
2XCPU

1
2
3
4
5
6
7
8
9
10
11
12
12
13
14
15
16
17

CPU
SCLK21
SCLK20

18
19
20

X2

Xl
VDD
GND

Pin type
Output
Output
Inout

Output
Output
Output

Input
Input

Input
Output
Outout

-

Oumut
Output
Input
Input

Description
1.84 MHz clock output
CRYSTAL connection
CRYSTAL connection
DIGITAL POWER SUPPLY (+5V)
Digital GROUND
16 MHz (AV9155-01) or 32MHz (AV9155-02) clock output
24 MHz floppy disk/combination I/O clock output
12 MHz kevboard clock outout
ANALOG GROUND (original version)
OUlPUT ENABLE. Tri-states all outputs when low
CPU CLOCK frequency SELECT #2
ANALOG POWER SUPPLY (+5V )
POWER DOWN. Shuts off entire chip when low (U version)
14.318 MHz reference clock output
14.318 MHz reference clock outout
Dil!i.tal GROUND
DIGITAL POWER SUPPLY (+5V)
2X CPU dock oumut
1X CPU clock output
CPU CLOCK frequency SELECT #1
CPU CLOCK frequency SELECT #0

462

II

AV9155

Decoding and Clock Tables AV9155-01
(using 14.318 MHz input. All frequencies in MHz)
CLOCK#2 CPU and 2XCPU
SCLK22 SCLK21 SCLK20
(Pin II) (Pin 19) (Pin 20)
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1

2XCPU
(Pin 17)
8
16
32
40
50
66.66
80
100

PERIPHERAL CLOCKS
COMMCLK BUSCLK
(Pin 1)
(Pin 6)
16
1.843

CPU
fPin 18)
4
8
16
20
25
33.33
40
50

REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FOCLK
(Pin 7)
24

KBCLK
(Pin 8)
12

REFCLK2
(Pin 14)
14.318

Decoding and Clock Tables AV9155-02
(using 14.318 MHz input. All frequencies in MHz)
CLOCK#2 CPU and 2XCPU
SCLK22 SCLK21 SCLK20
(Pin 11) (Pin 19) (Pin 20)
0
0
0
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1

2XCPU
(Pin 17)
8
16
32
40
50
66.66
80
100

PERIPHERAL CLOCKS
COMMCLK BUSCLK
(Pin 1)
(Pin 6)
1.843
32

CPU
(Pin 18)
4
8
16
20
25
33.33
40
50

REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FOCLK
(Pin 7)
24

KBCLK
(Pin 8)
12

REFCLK2
(Pin 14)
14.318

The "U" Version
ICS is producing enhanced versions of the AV9155-01 and AV9155-02 that are exactly compatible with the original
versions. These "u" versions offer improved performance and the addition of a power down pin that turns off the
entire chip.

Frequency Transitions
A key feature of the AV9155 is its ability to provide smooth, glitch-free frequency transitions on the CPU and 2XCPU
clocks when the frequency select pins are changed. These frequency transitions do not violate the Intel 486
specification of less than 0.1 % frequency change per clock period.

Using an Input Clock as Reference
The AV9155 is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is
possible to use a crystal oscillator or clock input. Please see application note AAN04 for details on driving the AV9155
with a clock.

463

II

AV9155

Pin Configurations
20

6MHz

SCLK20

X2

2

19

SCLK21

Xl

3

18

SCLK22

VDO

4

17

CPU

GNO

5

16

VDO

~.....


OE

-

p.In Descrlptlon for AV915503
Pin Name
6MHz
X2

Xl
VDD
GND
24MHz
16MHz
8MHz
AGND
OE
SCLK23
PD*
14.318MHz
14.318MHz

Pin #

Pin type

1
2

Output

3
4

Input

5
6
7
8
9
10
11
12

Ou~ut

Output
Output
Output
-

Input
Input

13
14

Input
Output
Output

GND
VDD
CPU
SCLK22

15
16

-

17
18

Output
Input

SCLK21
SCLK20

19
20

Input
Input

Description
6 MHz clock output (-03) or 1.843 MHz (-23) clock output
CRYSTAL connection
CRYSTAL connection
DIGITAL POWER SUPPLY (+5V)
Digital GROUND
24 MHz (-03) floppy disk or 16 MHz (-23) bus clock out
16 MHz (-03) bus clock output or 24 MHz (-23) fl<>pl'Y_ disk
8 MHz (-03) or 12 MHz (-23) keyboard clock output
ANALOG GROUND
OUTPUT ENABLE. Tri-states all outputs when low
CPU CLOCK frequency
POWER DOWN. Turns off entire chip when low
14.318 MHz reference clock output
14.318 MHz reference clock output
Digital GROUND
DIGITAL POWER SUPPLY (+5V)
CPU clock output / 2XCPU clock output
CPU CLOCK frequency SELECT #2 (-03) / CPU clock o~ut (-23)
CPU CLOCK frequency SELECT #1
CPU CLOCK frequency SELECT #0

464

•

AV9155

Decoding and Clock Tables for AV9155-03

(using 14.318 MHz input. All frequencies in MHz)
CLOCK #2 CPU
SCLK23 SCLK22
(Pin 11) (Pin 18)
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
1
1

1

1
1

1
1

SCLK21
(Pin 19)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

SCLK20
(Pin 20)
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1

CPU
(Pin 17)
16
40
50
80
66.66
100
8
4
8
20
25
40
33.3
50
4
2

~
~

386

486

Smooth, glitch-free frequency transitions are guaranteed if the state of SCLK23 (pin 11) is not changed (smooth
transitions are guaranteed in either the top or bottom half of the frequency decode table).

PERIPHERAL CLOCKS
COMMCLK BUSCLK
(Pin 1)
(Pin 7)
6 MHz
16 MHz

REFERENCE CLOCKS
REFCLK1
(Pin 13)
14.318

FOCLK
(Pin 6)
24 MHz

KBCLK
(Pin 8)
8 MHz

REFCLK2
(Pin 14)
14.318

46S

91 )~~
AV9155
Pin Configuration
1.843MHz

40MHz

20

SCLK20

X2

2

19

SCLK21

Xl

3

18

CPU

VDD

4

17

2XCPU

16

GND

5

15

15MHz

6

20

X2

2

19

Xl

3

18

VCC

4

17

:>
~
....

:>
....~

GND

5

16MHz

6

24MHz

7

14

14.318MHz

24MHz

7

14

14.318MHz

12MHz

8

13

14.318MHz

12MHz

8

13

14.318MHz

12

GND

9

12

PD"

11

OE

10

11

SCLK22

'"

'"
I

N

t.l

GND
OE

9
10

'"~
'"

16

VDD

15

GND

Pin Confiauration for A 119155-2 3, -36
Pin Name

Pin #

1.843/4OMHz

1
2
3
4
5
6
7
8
9
10
11
12
12
13
14
15
16
17
18
19
20

X2

Xl
VDD
GND
16MHz/15MHz
24MHz
12MHz
AGND
OE
SCLK22
AVDD
PO14.318MHz
14.318MHz
GND
VDD
2XCPU
CPU
SCLK21
SCLK20

Pin type

Description

Output
Output
Inout

1.843 MHz/4O MHz clock output
CRYSTAL connection
CRYSTAL connection
DIGITAL POWER SUPPLY (+5V)
Digital GROUND
16 MHz /15 MHz clock output
24 MHz floppy disk/combination I/O clock output
12 MHz kevboard clock output
ANALOG GROUND (original version)

Output
Output
Output

Input
Input

Input
Output
Outout

Ou~ut

Output
Input
Input

OUTPUT ENABLE. Tri-states all outputs when low
CPU CLOCK frequency SELECT #2
ANALOG POWER SUPPLY (+5V )
POWER DOWN. Shuts off entire chip when low (U version)
14.318 MHz reference clock output
14.318 MHz reference clock outout
Digital GROUND
DIGITAL POWER SUPPLY (+5V)
2X_CPU dock outnut
IX CPU clock output
CPU CLOCK frequency SELECT #1
CPU CLOCK frequency SELECT #0

466

II

AV9155

Decoding and ClockTables (using 14.318 MHz input. All frequencies in MHz)
AV9155-23

PERIPHERAL CLOCKS
COMMCLK BUSCLK
(Pin 1)
(Pin 6)
1.843
16
REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FDCLK
(Pin 7)
24

KBCLK
(Pin 8)
12

REFCLK2
(Pin 14)
14.318

AV9155-36

PERIPHERAL CLOCKS
SCUZZYCLK BUSCLK
(Pin 1)
(Pin 6)
40
15
REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FDCLK
(Pin 7)
24

KBCLK
(Pin 8)
12

REFCLK2
(Pin 14)
14.318

467

II

AV9155

Absolute Maximum Ratings
Storage temperature ................................ -40°C to +150°C
Voltage on flO pins referenced to GND ...... GND -D.5V
toVDD +O.5V
Power dissipation ................................................ 0.5 Watts

AVDD, VDD referenced to GND................................. 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum conditions for extended periods may affect devices reliability.

Electrical Characteristics
(V00 = +5V± 10%, TA = O°C to 70°C unless otherwise stated)

Symbol

Parameter

Min

Typ Max Units

Conditions

DC Chara(:teristics
VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
Icc
ICOSTBY
Fo
I

~u
C.

C:

Input Low Voltage
Input High Voltage
2.0
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-.4V
Output High Voltage
Vor8V
Output High Voltage
.4
Supply Current
Supply Current, Power Down
Output Frequency Change
over Supply and Temperature
Short circuit current
25
Pull-up resistor value
Input Capacitance
Load Canacitance

40
35
0.002

0.8

V
V

-5
5
0.4

JlA.
JlA.

70
0.01

40
680
10
20

V
V
V
V
mA

JlA.
%

mA
ill
pF
nF

Voo=5V
Voo=5V
VIN=OV
VIN = Voo
IOL = 4mA
IoH = -lmA,voo=5.0V
IOH = -4mA,Voo=5.0V
IoH = -8mA
INoload
No load
With respect to
typical frequency
Eadi output clock
Pin 10 (and 12,U only)
Except Xl, X2
Pins -X1 X2

AC Chal
t,
t,
tl
tl
d,
d,
tjls
tjab
}ab

tok
tft

Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V00
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% V00
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Jitter, absolute
Input Frequency
Clock skew between CPU and
2XCPU outputs
Frequency Transition time

40/60
40/60

1
2
1
2
48/52
43/57
0.8
2

2
4
2
4
60/40
60/40
2.5
5
700

14.318
1

1.5

ns
ns
ns
ns
%
%
%
%
ps
MHz
ns

15

20

ms

25 pfload
25 pfload
25 pfload
25 pfload
25 pf load
25 pf load
As compared with
clock period
16-100 MHz clocks

From 8 to 100MHz

(l.Ons max on U parts)

Notes:
1. All clocks on AV9155-01 running at highest possible frequencies. Power supply current can change substantially
with different mask configurations. Consult ICS.

468

AV9155
Actual Output Frequencies
(using 14.318 MHz input. All frequencies in MHz)
AV9155-23

AV9155-01 and AV9155-02
CPU CLOCK

CPU CLOCK

SCLK22 SCLK21 SCLK20
(Pin 11) (Pin 19) (Pin 20)
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1

2XCPU
(Pin 17)
7.50
15.51
32.22
40.09
50.11
66.82
80.18
100.23

PERIPHERAL CLOCKS
COMMCLK
BUSCLK
(Pin 1)
(Pin 6)
1.846
32.01 or 16.00

FDCLK
(Pin 7)
24.00

CPU
(Pin 18)
3.75
7.76
16.11
20.05
25.06
33.41
40.09
50.11

SCLK22 SCLK21 SCLK20
(Pin 11) (Pin 19) (Pin 20)
0
0
0
1
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
1
PERIPHERAL CLOCKS
COMMCLK
BUSCLK
(Pin 1)
(Pin 6)
1.843
16.00

KBCLK
(Pin 8)
12.00

AV9155-03

FDCLK
(Pin 7)
24.00

CPU
(Pin 18)
37.585
15.970
30.068
20.045
25.057
33.238
40.091
25.952
KBCLK
(Pin 8)
12.00

AV9155-36

CLOCK #2 CPU
SCLK23
(Pin 11)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

2XCPU
(Pin 17)
75.170
31.940
60.136
40.090
50.113
66.476
80.181
51.903

SCLK22
(Pin 18)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

CPU CLOCK
SCLK21
(Pin 19)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

PERIPHERAL CLOCKS
COMMCLK BUSCLK
(Pin 1)
(Pin 7)
6.00
16.00

SCLK20 CPU
(Pin 20) (Pin 17)
15.51
0
40.09
1
50.11
0
80.18
1
66.82
0
100.23
1
7.58
0
4.30
1
7.76
0
1
20.05
25.06
0
1
40.09
33.41
0
50.11
1
3.79
0
2.15
1

FDCLK
(Pin 6)
24.00

SCLK22 SCLK21 SCLK20
I (Pin 11) (Pin 19) (Pin 20)
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
PERIPHERAL CLOCKS
SCUZZYCLK BUSCLK
(Pin 1)
(Pin 7)
40.00
15.00

KBCLK
(Pin 8)
8.00

469

2XCPU
(Pin 12"1
8.054
16.002
59.875
39.886
50.113
66.476
80.181
100.226

FDCLK
(Pin 6)
24.00

CPU
. (Pin lID
4.027
8.001
29.936
19.943
25.057
33.238
40.091
50.113

KBCLK
(Pin 8)
12.00

AV9155

AV9155
Recommended External Circuit
+5V

kg

(see note #4)

2.2~I
1.843MHZ
X2
Xl

14.318 MHz crystal
VDD
GND

o.l~I

-

16/32MHz
24MHz
12MHz
AGND

-

OE

1

2
3
4
5
6
7
8

>
-<
\C
~

til
til

20
19
18
17
16

SCLK20
SCLK21
CPU
2XCPU
VDD
GND

15

14
13

9

12

10

11

14.318MHz
14.318MHz

-

IO.1~

PD*
SCLK22

Notes:
1. ICS recommends the use of an isolated ground plane for the AV9155.
All grounds shown on this drawing should be connected to this ground plane.
This ground plane should be connected to the system ground plane at a single point.
Please refer to AV9155 Board Layout diagram.
2. A single power supply connection for all VDD lines at the 2.2 ~ decoupling
capacitor is recommended to reduce interaction of analog and digital circuits. The
0.1 ~ decoupling capacitors should be located as close to each VDD pin as possible.
3. A 33 n series termination resistor should be used on any clock output which drives
more than one load or drives a long trace (more than about 2 inches), especially when
using high frequencies (>50 MHz). This termination resistor is put in series with the
clock output line close to the clock output. It helps improve jitter perfomance and reduce
EMI by damping standing waves caused by impedance mismatches in the output clock
circuit trace.
4. The ferrite bead does not enhance the performance of the AV9155,
but will reduce EMI radiation from the VDD line.

470

•

AV9155
AV9155 Recommended Board Layout
PIN 1

XTAL

mGap in Ground Plane

2.21iF

A V9155 Ground

.L;J.C =connection to
QO ground plane

- System Ground -

This is the recommended layout for the AV9155 to maximize clock performance. Shown are
the power and ground connections, the ground plane, and the input/ output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high
frequency ground and system noise from propagating through the device. When compared
to using the system ground and power planes, this technique will minimize output clock jitter.
The isolated ground plane should be connected to the system ground plane at one point, near
the 2.2~F decoupling cap. For lowest jitter performance, this isolated ground plane should
be kept away from clock output pins and traces. Keeping the isolated ground plane area as
small as possible will minimize EM! radiation. Use a sufficient gap between the isolated
ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD
line optional, but will help reduce EM!.
The traces to distribute the output clocks should be over a system ground or power supply
plane. The trace width should be about two times the thickness of the PC board between the
trace and the underlying plane. These guidelines help minimize clock jitter and EM!
radiation. The traces to distribute power should be as wide as possible.

471

AV9155
Ordering Information
Part Number
AV9155-xxCN20
AV9155-xxCW20

Temperature Range
O·C to +70·C
O·C to +70·C

Package Type
20 lead Plastic DIP
20 lead Plastic SOIC

Notes:
The dash number following AV9155, (denoted by xx above) must be included when ordering product, since it
specifies the version being ordered. Tape and reel packaging should be ordered with the suffix T&R. For instance,
if the -01 in SOIC and tape and reelis required, order the part as AV9155-01 CW20T &R. All versions currently shipping
are U versions, as of September 1992.

Part Marking
Original version (-01 and -02):

U version (-01 and -02):

ICS
AV9155-xxCx20
Date code/Lot code

ICS
AV9155-xxCx20
U Date code/Lot code

472

ICS9158

Integrated
Circuit
Systems, Inc.

•

Advance Information

Integrated Buffer and Motherboard Frequency Generator
Features

The CPU clocks provide all necessary frequencies for
286, 386, 486, and Pentium systems, including support
for the latest speeds of processors .

•
•
•
•
•
•
•
•
•

Eight skew free, high drive CPU clock outputs
Up to 100 MHz output at 5V, 66 MHz at 3.3V
± 250psec skew between CPU outputs
Outputs can drive up to 30pF load
25mA output drivers
Typical 50/50 duty cycle
Compatible with 486 and Pentium CPUs
Glitch-free start and stop clock feature
Optional power-down mode supports Energy Star
("green") PCs
• On chip loop filter components
• Low power, high speed 0.8 J.l CMOS technology
• 24 pin POIP or SOIC package

The CPU clock offers the unique feature of smooth,
glitch-free transitions from one frequency to the next,
making this the ideal device to use whenever slowing the
CPU speed. The ICS9158 makes a gradual transition
between frequencies, so that it meets the Intel cycle to
cycle timing specification for 486 systems.
ICS has been shipping Motherboard Frequency Generators since April 1990, and is the leader in the area of
multiple output clocks on a single chip. The ICS9158 is a
third generation device, and uses ICS' patented analog
CMOS Phase Locked Loop technology for low phase
jitter. ICS offers a broad family of frequency generators
for motherboards, graphics and other applications, including cost effective versions with only one or two
output clocks. Consult ICS for all of your clock generation needs.

General Description
The ICS9158 is a low cost frequency generator designed
specifically for desktop and notebook PC applications.
Eight high drive, skew controlled copies of the CPU
clock are available, eliminating the need for an external
buffer.

Clock Table (in MHz)

Each high drive (25 rnA) output is capable of driving a
30pFIoad and hasa typical duty cyc1e of 50/50. TheCPU
clock ouputs are skew controlled to within ±250psec.

Clock

AV9158-0l

BUSCLK
FDCLK
14.318

16
24
14.318

CPUCLK
2XCPUCLK

4,8,30,20,25,33.3,40, or 50
816604050 66.6 80 or 100

Block Diagram
so - 52

3

--t------+---~

REFERENCE
CLOCK

2XCPU
CPU
CLOCK

CPUl,2,3,4,5,6,7

,----------~---+__OE

14.318 MHz
BU5CLK

PERIPHERAL
CLOCKS

FDCLK

r-r

VDD GND

AGND

473

•

ICS9158

Pin Configuration
CPU2

so

Xl40UT

51

X14IN

CPU1

VDD

2XCPU

GND

VDD

16MHz

GND

24MHz

14318MHz

CPU3

CPU.

AGND

AVDD

OE

52

CPU5

CPU6

GND

CPU7

ICS915801
· f Ion
escrlp'
- PIn · O
Pin Name

Pin #

Pin Type Description

CPU2

1

Output

X140UT

2

-

CPU clock output

X14IN
VDD

3

-

4

-

Crystal connection
Crystal connection
Digital POWER 5UPPLY (+5V)

GND

5

-

Digital GROUND

16MHz

6

24MHz

7

CPU3

8

Output
Output
Output

16 MHz clock output
24 MHz floppy diskl combination 110 clock output

AGND

9

-

OE

10

Input

CPU5

11

Output

CPU clock output

GND
CPU7

12
13

-

Output

Digital GROUND
CPU clock output
CPU clock outnut

CPU clock output
ANALOG GROUND
OUTPUT ENABLE. Tri-states all outputs when low

CPU6

14

Output

52

15

Input

AVDD

-

CPU4

16
17

Output

CPU clock output

14.318MHz

18

Output

14.318 MHz clock output

GND

19

-

VDD

20

-

2XCPU
CPUI

21

Output

2X CPU clock output

22

Output

CPU clock output

51

23

Input

CPU clock frequency select #1

SO

24

Input

CPU clock frequency select #0

CPU clock frequency select 2
ANALOG power supply (+5V)

Digital GROUND
Digital POWER 5UPPLY (+5V)

474

ICS9158
Absolute Maximum Ratings
Storage temperature................................ -40°C to +150°C
Voltage on flO pins referenced to GND...... GND -O.5V
to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

AVDD, VDD referenced to GND ................................. 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification IS not
implied. Exposure to absolute maximum conditions for extended periods may affect devices reliability.

Electrical Characteristics
(V·DD- +5V+
- O°C to 70°C unless otherwise stated)
- 10%, T A-

Symbol

Parameter

Min

Typ Max Units

Conditions

DC Chan lcteristics
VIL
VIH
IlL
IIH
VOL
VOH
VOH
VOH
Icc
Fo
Isc
Rpu
C,
CL

Input Low Voltage
2.0
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Voo-·4V
Output High Voltage
Voo-·8V
Output High Voltage
2.4
Supply Current
Output Frequency Change
over Supply and Temperature
Short circuit current
25
Pull-up resistor value
Input Capacitance
Load Capacitance

0.8
- 40
+40
0.4

70
0.002

0.01

56
680
8
30

V
V
j.tA
j.tA
V
V
V
V
rnA
%
rnA
kQ
pF
pF

Voo = 5V
Voo = 5V
VIN = OV
VIN = Voo
IOL =4mA
IOH = -lmA,Voo=5.0V
IOH = -4mA,Voo=5.0V
IoH = -8mA
INoload
With respect to
typical frequency
Each output clock
Input pin
Except Xl, X2
Pins Xl, X2

AC Characteristics
tr
tr
tf
tf
dt
dt
til'
t b

t'"

r

·t
tft

Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V00
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDO
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Jitter, absolute
Input Frequency
Clock skew between CPU and
2XCPU outputs
Frequency Transition time

40/60
40/60

14.318
100

250

ns
ns
ns
ns
%
%
%
%
ps
MHz
ps

13

20

ms

1
2.5
0.5
1.5
48/52
43/57
0.5
2

2
3
1
2
60/40
60/40
2.0
5
500

30 pfload
30 pf load
30 pfload
30 pfload
30 pf load
30 pf load
As compared with
clock period
16-100 MHz clocks

From 3.79 to 50.1 MHz

Notes:
1. All clocks on ICS9158 running at highest possible frequencies. Power supply current can change substantially
with different mask configurations. Consult ICS.

475

II

ICS9158
ICS91S8-01 CPU Clock Decoding Table
(using 14.318 MHz input. All frequencies in MHz)
CLOCK#2 CPU and 2XCPU
51
52
SO
I(Pin 15) (Pin 23) (Pin 24)
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
1
1
1

2XCPU
(Pin 21)
7.580
15.511
59.875
40.090
50.113
66.476
79.772
100.226

PERIPHERAL CLOCKS
BUSCLK
FDCLK
(Pin 6)
(Pin 7)
16.002
24.003

CPU
3.790
7.756
29.938
20.045
25.057
33.238
39.886
50.113

REFERENCE CLOCK
REFCLKI
(Pin 18)
14.318

Frequency Transitions
A key feature of the ICS9158 is its ability to provide smooth, glitch-free frequency transitions on the CPU and 2XCPU
clocks when the frequency select pins are changed. The frequency transition rate does not violate the Intel 486
specification of less than 0.1 % frequency change per clock period.

USing an Input Clock as a Reference
The ICS9158 is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is
possible to use a crystal oscillator or other clock sources. Please see application note AAN04 for details on driving
the ICS9158 with a clock.

Stop Clock Feature
The ICS9158 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock
pin goes low, the CPUCLK will go low after the next occuring falling edge. When STOPCLK again goes high, CPUCLK
resumes on the next rising edge of the internal clock. This feature enables fast, glitch-free starts and stops of the
CPUCLK and is useful in Energy Star motherboard applications .

............- - - - - - - " " " ".......

476

•

ICS9158

Ordering Information
Part Number
ICS9158-xxCN24
ICS9158-xxCW24

Temperature Range
O·C to+70·C
O·C to+70·C

Package Type
24 lead Plastic DIP
24 lead Plastic SOIC

II

477

478

ICS
Special Purpose IC
Products

479

Special Purpose
Product
A pp lica tions

Ie Products Guide

ICS
Device Type

Features

Package Types

Page

ICS1694A

Single Crystal Generates Three
Low-Jitter Clocks.

8 Pin
DIP,SOIC

481

AV9110

User-Programmable "On-the-Fly";
Low-Jitter makes it Ideal for Disk
Drive or Video Applications.

14 Pin
DIP,SOIC

485

High Resolution Clock Generator;
One Channel has Accuracy to within
50 PPM and making it Ideal for
Modem, Ethernet and AD 1848
Applications.

16 or 20
Pin
DIP,SOIC

495

AV9170

Clock Synchronizer and
Multiplier.

8 Pin
DIP,SOIC

497

AV9172

Low Skew Output Buffer. Low Skew
and Jitter make it Ideal for Pentium™
Applications.

16 Pin
DIP,SOIC

51J

AV9173

Low Cost Video Genlock PLL.

8 Pin
DIP,SOIC

519

ICS9175

Low Skew Output Buffer Crystal
Generates Six Low Skew,
Low-Jitter Clocks.

16 Pin
DIP,SOIC

523

ICS9176

Input Clock Generates 10 Low Skew,
Low-Jitter Outputs. Ideal for Pentium
or PLI Applications.

28 Pin PLCC

ICS9123

Motherboard

535

ADVANCE INFORMATIO N documents contain information on new products in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.
PRODUCT PREVIEW documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

480

•

ICS1694A

Integrated
Circuit
Systems, Inc.

Product Preview

Mini-Motherboard Clock Generator
Features

Applications

•
•
•
•
•

Low Cost Motherboard Clock Generator
Small Footprint, space-saving package
Very Flexible Architecture
Advanced PLL design
Upgraded the ICS1694 to include Output Enable and
higher frequency capabilities

•

Any design requiring clocking signals or count down
chains derived from a clock signal

•

Many standard patterns available

•
•
•
•
•

Memory refresh
Keyboard
Serial port
Floppy Disk
Hard Disk

•
•

CPU
Coprocessor

Description
The ICSI694A Mini-Motherboard Clock Generator has
been developed to give designers a unique, efficient (cost,
size, and power) means of generating the various clocks
required in a digital system. The initial patterns being offered as standards are summarized in Table 1.

Pin Configuration

VDD
The low cost and small size of the ICS1694A allow the
designer to use mUltiple devices (different patterns) in a
system in order to generate the clock signals physically close
to the requirement, instead of having long PCB board traces
transmitting (and radiating) the signals.

AVDD/OE

The ICSl694Acontains all the passive components required
for a crystal oscillator or it may be driven by a clock signal.
In some applications, one of the outputs of one ICS1694A
will be used as the clock input of a second or third ICSI694A,
thus requiring only one quartz crystal for the system and, in
the process, synchronizing all the clock signals to the crystal
oscillator.
The ICSI694A contains a single PLL. Therefore all output
frequencies, other than the buffered crystal oscillator, must
be the result of an integer division of the PLL frequency.
For instance, if the PLL operates at 120 MHz, the outputs
could be a selection of three of any of the following: 120
MHz, 60 MHz, 40 MHz, 30 MHz, 24 MHz, 20 MHz, 15
MHz, 12MHz, lOMHz, 8MHz,6MHz,etc. More detail
concerning the options is given in the section titled
PATTERNS.

481

OUTl
2

7

OUT2

OSCI

3

6

OUT3

OSC2

4

5

VSS

Ordering Information
ICSI694AN-XXX (DIP Package)
ICS1694AM-XXX (SO Package)
(XXX= Pattern Number)

II

ICS1694A

Pin 2 may be bonded to serve as either AVDD (analog
positive supply) or OE (output enable). The outputs
(OUTl, OUT2,and OUT3) will be enabled whenOE is held
high. OE has internal pull-up so it maybe allowed to float.

For instance, pattern 010 programs the VCO to 120 MHz.
Then a divide by 3 yields 40 MHz; a divide by 4 yields 30
MHz; and a divide by 5 yields 24 MHz. Obviously, some of
the divide chains can and are combined. An output may also
be the crystal oscillator frequency or that frequency divided
by an integer.

If particularly stable outputs are required, the option with

It should also be considered that the input does not have to

pin 2 bonded as AVDD is recommended. AVDD should
be driven by the system's analog supply, if available. In some
applications where only a digital supply is available, AVDD
can be driven from the digital VDD supply through a simple
RC decoupling circuit. The voltage drop across the series
resistor should be held to less than 250 mv. It is difficult to
generalize across all applications, but in the majorityofcases
the performance of the ICS1694A is completely satisfactory
when used with power supplied only to pin 1 and pin 2
bonded as Output Enable .

be 14.318 MHz, but can be any fundamental mode crystal
up to 25 MHz. Table 1 lists the frequencies available from
the various patterns. For any of these patterns, the crystal
frequency (and thus the PLL-VCO frequency) may be
changed and the output frequencies will be scaled accordingly. For instance, if the crystal frequency used is one half
of that listed in Table 1, the actual output frequencies will
be one half those listed in the table. Also options are
available which will work with an overtone crystal.

Options

.Patterns
A number of standard patterns will be offered which will
satisfy most of the typical requirements of the PC market.
New patterns are continuously being added as new applications surface. ICS welcomes suggestions for new patterns
and will also fabricate custom patterns as described in the
following paragraph.
The ICS1694A contains one PLL-VCO which is mask programmable to any frequency up to 180 MHz. The chip
contains a number of counter stages which can be used to
count the VCO frequency down to the desired output frequencies. The output frequencies are derived by dividing
the VCO frequency by an integer.This is a limitation on the
frequencies which can be generated in the same chip since
each frequency must be derived from the same VCO frequency.

Absolute Maximum Ratings
Supply Voltage . . . . . . . . VDD . . . . . . .
Input Voltage . . . . . . . . . VIN . . . . .
Output Voltage . . . . . . . . VOUT .. .
. VIK & 10K .
Clamp Diode Current.
Output Current per Pin
. lOUT .
Operating Temperature
. To .
Storage Temperature..
. Ts .
Power Dissipation ...
. PD .

-O.5Vto + 7V
-0.5V to VDD+ 0.5V
-0.5V to VDD+ O.5V
+ 1-3OmA

+ 1-50mA

o°c to 70°C
_85°C to + 150 °c
300mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and
VOUT be constrained to > = Vss and < = VDD.

482

II

ICS1694A

DC Characteristics (OOC to 70OC)
SYMBOL

PARAMETER

MIN

VOD

Operating_Voltage Range

VIL
VIH

Input Low Voltage

ILH

Input Leakage Current

VOL
VOH

Output Low Voltage
Output High Voltage

204

IOD

Digital Supply Current

--

IAA
Cm

Analog Supply Current

Coot

Input High Voltage

Input Pin Capacitance
Output Pin Capacitance

MAX

S.OV± S%OPERATION
4.75
5.25
Vss
2.0

---

UNITS

CONDITIONS

V

0.8

V

VDD-

VDO
10

V

VDD = 5V

5V

--

IlA
V
V

VIN = Vee
IOL = 4.0mA
IOH = 4.0mA

30

rnA

Voo = 5V, VCO = 120MHz

8

rnA
pF
pF

VDD = 5V, VCO = 120MHz
Fe= IMHz
Fe = IMHz

004

---

8

12
3.3V+ lO%OPERATION

20
rnA
VDO= 3.3V, VCO = 120 MHz
Analog
Supply
Current
rnA
6
IAA
VDO= 3.3V, VCO = 120 MHz
Ifthe OE option is used, IDD will be the sum of both the digital and analog supply currents.
100

Digital Supply Current

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:
1. Xtal Frequency = 14.318 MHz, unless otherwise noted.

2.
3.
4.
5.
6.

All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC at 5.0V.
Output pin loading = 15pF
Duty cycle is measured at IAV at 5.0V.
Temperature Range = 0 °c to 70°C

S.OV ± S%OPERATION
SYMBOL

PARAMETER

MIN

MAX

NOTES

MCLK AND VCLK TIMING
Tr
Tf
Dc
Fm

---

Rise Time
Fall Time
Duty Cycle
Maximum Freguency

45

2
2
55
180

%

MHz

3.0V ± lO%OPERATION
SYMBOL

PARAMETER

MIN

MAX

NOTES

MCLK AND VCLK TIMING
Tr
Tf
Dc
Fm

--

Rise Time
Fall Time
Duty Cycle
Maximum Frequency

--

45

483

3
3
55
120

%
MHz

ICS1694A

Standard Frequency Patterns (M Hz)
Table 1
PINS

FUNCTION

PATTERNS
014

015

016

017

8

oun

24

25

12

6

24

24

XTAL

XTAL

7

OUT2

40

40

40

60

40

XTAL

16

12

6
5

OUT3
VSS

30

30

30

20

20

40

24

24

4

XTAL2

25

25

25

25

14.318

14.318

14.318

14.318

3
2

XTALl
AVDD/OE

1

VDD

PINS

FUNCTION

8

oun

7

OUT2

6

oun

5
4

XTAL2

010

011

012

013

PATTERNS

VSS

3

XTALl

2

AVDD/OE

1

VDD

484

•

~

AV9110

Integrated
Circuit
Systems, Inc.

Serially Programmable Frequency Generator
Features

Disk Drives: The A V9110 generates zone clocks for
constant density recording schemes. The low profile,
narrow 14 pin sorc package, and low jitter outputs are
especially attractive in board-space critical disk drives.

• Complete user programmability of output frequency
through serial input data port
• On chip Phase Locked Loop for clock generation
• Generates accurate frequencies up to 130 MHz
• Tri-state CMOS outputs
• 5 volt power supply
• Low power CMOS technology
• 14 pin DIP or 150 mil SOIC
• Very low jitter
• Wide operating range VCO.

General Description
The AV9110 generates user specified clock frequencies
using an externally generated input reference, such as a
14.318 MHz or 10.00 MHz crystal connected between
pins 1 and 2. Alternately, a TTL input reference clock
signal can be used. The output frequency is determined
by a 24 bit digital word entered through the serial port.
The serial port enables the user to change the output
frequency on-the-fly.

Applications
Graphics: The AV9110 generates low jitter, high speed
pixel (or dot) clocks. It can be used to replace multiple
expensive high speed crystal oscillators. The flexibility
of this device allows it to generate non-standard graphics clocks, allowing the user to program frequencies onthe-fly.

The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.

Block Dia ram
D17. Dl8

Xl

X2

VCO

OUTPUT
DNIDER
R~I.2,4 or 8

D22

CLK

OE

485

AV9110
Pin Configuration
Xl

14

X2

13

OE

12

CLK

11

VDD

10

GND

AVDD

2

AGND

3

VDD

4

GND

5

DATA

6

9

CLK/X

SCLK

7

8

CEo

>->«
1..0 1..0
............
...... ......

, ,

00
00

N ......

Clock Reference
Implementations:
AV9110-01 vs.AV9110-02
The AV9110 requires a stable reference clock (5 to 32
MHz) to generate a stable, low-jitter output clock. The
AV9110-01 is optimized to use an external quartz crystal
as a frequency reference, without the need of additional
external components. The AV911O-02 is optimized to
accept an TTL clock reference. Either device can be used
with an external crystal or accept a TTL clock reference,
although extra components may be required. The various
combinations implied are summarized in Figure 2 (see
page 7).

14 pin DIP, sOle

p.In Descrlotlon
Pin #

Pin type

Xl
AVDD
AGND
VDD
GND
DATA
SCLK
CEo

1
2
3
4
5

CLKjX
GND
VDD
CLK
OE
X2

9
10
11
12
13
14

Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Output
Input
Input

Pin Name

6
7
S

Description
Crystal input or TTL reference clock
ANALOG power supply. Connect to +5 V
ANALOG GROUND
Digital power supply. Connect to +5 V
Digital GROUND
Serial DATA pin
SERIAL CLOCK. Clocks shift register
CHIP ENABLE. Active low, controls data transfer
CMOS CLOCK divided by X output
Digital GROUND
Digital power supply. Connect to +5 V
CMOS CLOCK output
OUTPUT ENABLE. Tri-states both outputs when low
Crystal input or TTL reference clock

486

AV9110
Absolute Maximum Ratings
Storage temperature ................................ -65°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
toVDD+0.5V
Power dissipation ................................................ 0.8 Watts

AVDD, VDD referenced to GND................................. 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those listed under Absolute Maximum Ratings may cause permanen't damage to the device. This is a stress rating only, and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum conditions for extended periods may affect the rehability of the device.

Electrical Characteristics

(Vnn = +5V+
- 10%, T - oDe to 70 0e unless otherwise stated)
Symbol
Parameter
Min Typ

Max

Units

Conditions

DC Characteristics
v IL
VIH
IIL
I

~L

V
It'tK
ICLK;
100

AC Chal
fo
t

~

t

~F
~:TA

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output Hi~h Voltage
Input Cloc Rise Time
Input Clock Fall Time
Supply Current

-

2.0
-

2.4
-

-

-

0.8
-

-5
5
0.4

-

20
20

25

V
V
IlA
IlA
V
V
nS
nS
rnA

voo = 5V
Voo=5V
VIN = OV
VIN=~
I =8
IOL = 8mA
OH
No load

istics
Output frequency range
Rise time, 20-80%
Fall time, 80-20%
Dutycyc1e
Jitter,l sigma
Jitter, absolute
Input reference freq.; AV9110-0l
Input reference fre~t AV911O-02
Input DATA or SC K frequency

0.78
-

-

130
3
3
60

±40
±125
14.318
14.318

-

40
5
0.6

487

32
32
32

MHz
ns
ns
%
ps

25 pfload
25 pfload
25 pf load

ITHz
MHz
MHz

Crtstal input
T L input

AV9110
Serial Programming
The AV911 0 is programmed to generate clock frequencies by entering data through the shift register. Figure 1
displays the proper timing sequence. On the negative
going edge of CE*, the shift register is enabled and the
data at the DATA pin is loaded into the shift register on
the rising edge of the SCLK. Bit DO is loaded first,
followed by Dl, D2, etc. This data consists of the 24 bits
shown in the Shift Register Bit Assignment in Table 1,
and therefore takes 24 clock cycles to load. An internal
counter then disables the input and transfers the data to

internal latches on the rising edge of the 24th cycle of the
SCLK. Any data entered after the 24th cycle is ignored
until CE* is taken high and then low to start a new word.
CE* must remain low for a minimum of 24 SCLK clock
cycles. If CE* is taken high before 24 clock cycles have
elapsed, the data is ignore (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit
location for generating the output clock frequency and
the output divider circuitry, respectively.

Sh"1ft ReOlster Bit Assianment
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

Equation
Variable

Assignment

-

VCO frequency divider (LSB)
"

"
"
"
"

N

Integer

VCO frequency divider (MSB)
Reference frequency divider (LSB)

=

"
"
"
"
"

M
Integer

Reference frequency divider (MSB)
VCO pre-scale divide (O=divide by 1, l=divide by 8)
CLK/X output divide CODO (see table 2)
CLK/X output divide CODI (see table 2)
VCO output divide VODO (see table 2)
VCO output divide VODl (see table 2)
Output enable CLK (O=tri-state)
Output enable CLK/X (O=tri-state)
Reserved. Should be programmed low (0)
Reference clock select on CLK (1 = reference frequency)
Reserved. Should be programmed high (1)
Table 1

488

-

::J

]
]

V
X
R

De ault
-02

Bit

1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
1
1
1
1
0
1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

-01

1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
0
1

91

•

~~~

AV9110
Output Divider Truth Tables
CODI

CLKIX
Output divide

CODO

VODI

VODO

a
a

a

(R)

IY\

a
a
1
1

a

1
2
4
8

1

a
1

VCO
Output divide

1
1

1
2
4
8

1

a
1

Table 2

Table 3

Programming the PLL
The AV9110 has a wide operating range but it is recommended
that it is operated within the following limits:
2 MHz < fREF < 32 MHz
f
200KHz<~ <5MHz
M

fREF= Input reference frequency

50 MHz < fyeo < 250 MHz

fyeo = VCO output frequency

fCLK

~130MHz

M = Reference divide, 3 to 127

feLK = CLK or CLK/X output frequency

The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
f yeo = N·V·fREF
M

where N = VCO divide, 3 to 127
M = Reference divide, 3 to 127
V = Pre-scale, 1 or 8

The 2 output drivers then give the following frequencies:
fyeo
R

fyeo
fCLK/x = R.X

N·V·f
M.RREF or fREF (output muxable by bit 17)
Where R, X = output dividers, 1,2,4 or 8

Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or
greater. This will give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.

489

•

AV9110

cj'' - - - - - - - - +..

--tb,------'.I

tsul .....-...--

SCLK

~DON'TCARE

D2

Figure 1 - Serial programming

ACTiming
Parameter
tSUl
tsu2
thl

~

Jitter
Minimum time (ns)

For high performance applications, the AV9110 offers
extremely low jitter and excellent power supply rejection.
The one sigma jitter distribution is typically less than 40
ps and the maximum jitter is typically less than ±125 ps.
For optimum performance, the device should be
decoupled with both a 2.21lF and a O.lIlF capacitor. Refer
to Recommended Board Layout diagram on page 8.

10
10
10
10

Frequency Acquisition Time

Output Enable

Frequency acquisition (or "lock") time is the time that it
takes to change from one frequency to another, and is a
function of the difference between the old and new
frequencies. The AV9110 can typically lock to within 1%
of a new frequency in less than 200lls. This is also true
with power-on.

The AV9110 outputs can be disabled with either the OE
pin or through serial port programming. Setting the OE
pin low tristates CLK and CLK/X. Alternatively, setting
bits D19 and D20 low in the serial word will tri-state the
two outputs. Both the OE pin and D19 or D20 must be
high to enable an output.

Power-On Reset

Frequency Transition Glitches

Upon power-up the internal latches are pre-set to provide
the following output clock frequencies (14.318 MHz
reference assumed):
Device
CLKoutput
CLK/Xoutput
AV911 0-01
25.175 MHz
6.29 MHz
AV9110-02
25.175MHz
12.59 MHz

The AV9110 starts changing frequency on the rising edge
ofthe24thserialclock. If the programming of any output
divider is changed, the output clock may glitch before
locking to the new output frequency. However, if the
output dividers are unchanged, the VCO will change to
the new frequency in less than 200 Ilsec with no output
glitches (no partial clock cycles).

These preset default frequencies can be changed with
a custom metal mask, as can other attributes.

490

AV9110
AV9110 Quartz Crystal Selection
When an external quartz crystal will be used as a
frequency reference for the AV911O, attention needs to
be given to crystal selection if accurate reference frequency
and output frequency is desired. The A V9110 uses a
Pierce oscillator design which operates the quartz crystal
in parallel-resonant mode. It requires a quartz crystal cut
for parallel-resonant operation to ensure an accurate
frequency of oscillation (a less expensive series-resonant
crystal can be used with the device but it will oscillate
approximatelyO.1 % too fast). TheAV911O-0l has internal
crystal load capacitors which result in a total crystal load
capacitance of approximately 12 pH 10%. The AV911002 does not have internal load capacitors, but contributes
about 3 pf load capacitance to the crystal.

manufacturer to operate suitably with the AV91 xx-series
crystal oscillator design, having load capacitance
characteristics that are compatible with the AV911O-0l.
Toyocom
Part Number
TN4-30374
TN4-8037S
TN4-30376
TN4-30377
Epson
Part Number
MA-SOS or
MA-S06
CA-30l

Following is a list of recommended crystal devices for
the AV9110. They have been tested by the crystal

14.318 MHz surface mount crystal
20 MHz surface mount crystal
14.318 MHz through-hole crystal
20 MHz through-hole crystal

Surface mount crystal
Through-hole crystal

Figure 2
Clock Reference Combinations

~

X2

~ Xl

TTL
REFERENCE
SOURCE

AV911O-0l

.01

~F
1-r-_~X2

AV9110-0l
Xl

Using AV9110-01 with a crystal

Using AV911O-0l with an external clock

X2
AV91 I 0-02
~-----LX~I

TTL
REFERENCE
SOURCE

__________~

:::r::

Using AV9110-02 with a crystal

NC X2

AV9110-0l
Xl

Using A V911 0-02 with an external clock

491

II

AV9110
AV9110

Recommended Board Layout

-SYSTEM GROUND

~

W

=

connection to
ground plane

This is the recommended layout for the AV911 a to maximize clock performance. Shown are
the power and ground connections, the ground plane, and the input/ output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high
frequency ground and system noise from coupling to the AV911O. As when compared to using the
system ground and power planes, this technique will lessen output clock jitter. The isolated
ground plane should be connected to the system ground plane at one point, near the 2.2~F
decoupling cap. For lowest jitter performance, this isolated ground plane should be kept away
from clock output pins and traces. Keeping the isolated ground plane area as small as possible
will minimize EM! radiation. Use a sufficient gap between the isolated ground plane and system
ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but will help
reduceEMI.
The traces to distribute the output clocks should be over an unbroken system ground or power
supply plane. The trace width should be about two times the thickness of the PC board between
the trace and the underlying plane. These guidelines help minimize clock jitter and EM!
radiation. The traces to distribute power should be as wide as possible.

492

•

AV9110

AV9110 Typical Duty Cycle
VCO Output Divide, R = 1
Duty Cycle will improve if R > 1

6000
5600
5600
5400

----~

5200
III!

---------------------

5000
4600
4600
4400
4200
4000
0

20

40

60

60

100

120

MHz

AV9110Idd
CL =OpF, R=l

4000

3500

3000

2500
<[

E
2000

1500

1000

500

o

10

20

30

40

50

60

70

60

MHz

493

90

100

110

120 130

140 150

140

II

AV9110
Ordering Information
Part Number
AV9110-0lCNI4
AV9110-0lCSI4
AV9110-02CNI4
AV911 0-02CS 14

Temperature Range
O°C
O°C
O°C
O°C

to +70°C
to +70°C
to +70°C
to +70°C

Package Type
14 lead Plastic DIP
14 lead SOIC 150 mil wide
14 lead Plastic DIP
14 lead SOIC 150 mil wide

494

Integrated
Circuit
Systems, Inc.

•

ICS9123

Advance Information

High Resolution Frequency Generator
Features

General Description

• Cost effective solution for MODEM, ETHERNET
and AD1848 applications

The ICS9123 is a multiple output frequency generator
ultilizing PLL (Phase Lock Loop) frequency synthesis. It
contains three PLL frequency synthesizers and an internal
crystal oscillator reference circuit. Thus, with only an
external crystal and the necessary power supply
decoupling capacitors, four different output clock
frequencies can be provided.

• Three independent PLL's
• Four clock frequencies generated from one crystal
• One high resolution PLL provides ± 50 PPM
accuracy
• Eight ROM based frequency selections for the

PLLl of the device has the ability to provide high output
frequency resolution (±50 ppm). This makes it suitable
for providing clocks for system functions such as modems,
ethernet, and sound synthesis. PLL2 and PLL3 provide
output clocks for other system applications such as
microprocessors and DSP chips. For example, in modem
applications, the ICS9123 generates the high resolution
clock generator for the AID converter and two lower
resolution clocks for the microprocessor and DSP.

high resolution PLLl
• Four ROM based frequency selections each for
PLL2 and PLL3
• 3V or 5V power supply
• On chip loop filter components
• Low power CMOS technology
• 20 or 16 pin PDIP or SOIC package

Each of the PLL clock generators has a ROM based
frequency selection table which is addressed through
device input pins. PLLl has eight frequency select
locations; PLL2 and PLL3 each has four. The ROM based
tables are preprogrammed. However, they can be
customized for the user specific applications.

Block Diagram

r------------------------l
Xl

---L

I
I

I

T_ :

...

XTAL
OSC

PLL2

X2 I

XOUT "

FOUTI

-

i

:
I

PLU
(HIGH
~
RESOLUTION)

~

PLL3

I

I
I
I
I
IL _________________________ II

495

,

...

FOUT2

...

FOUT3

:
I
I
I
I
I
I
I

I
I
I
I

I
I
I

ICS9123
Decoding Table for Clock Frequency
(Using 14.31818 MHz Input Frequency)

Pin Configuration
XOUT

SCLKO

X2

SCLKI

Xl

SCLK2

VDD

Foun

VDD

VDD

GND

GND

FOUT3

FOUT2

GND

AVDD

SCLK2
2

SCLK21

SCLK20

FOUT1*
(MHZ)

FOUT2
(MHZ)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

8.06400
19.66080
29.49120
11.05920
13.82400
3.68640
14.74560
16.00031

19.7
29.5
8.06
14.6
19.7
29.5
8.06
14.6

* FOUTI frequencies shown are accurate to within 2 PPM

p.In DeSCnpl10n
. f
Pin Name
XOUT
X2
Xl
VDD
VDD
GND
FOUT3
GND
VDD
FOUT2
GND
VDD
FOUTI
SCLK2
SCLKI
SCLK20

Pin # Pin type Description
1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Output
Output
Input
-

Output
-

Output
-

Output
Input
Input
Input

Crystal buffered output
Connect crystal
Connect crystal
3V or 5V power supply
3V or 5V power supply
GROUND
Output frequency of one of 3 PLL's
GROUND
3V or 5V power supply
Output frequency of one of 3 PLL's
GROUND
3V or 5V power supply
Output frequency of the high resolution PLL
CPU clock frequency SELECT 2
CPU clock frequency SELECT 1
CPU clock frequency SELECT 0

496

FOUT3
(MHZ)
29.5
8.06
19.7
16.5
29.5
8.06
19.7
16.5

AV9170

Integrated
Circuit
Systems, Inc.

•

Clock Synchronizer and Multiplier
Features

Description

•
•
•
•
•
•
•
•
•
•
•

The AV9170 generates an output clock which is synchronized to a given continuous input clock with zero delay
(± Ins). Using ICS' proprietary phase locked loop (PLL)
analog CMOS technology, the AV9I70 is useful for regenerating clocks in high speed systems where skew is a
major concern. By the use of the two select pins, multiples or divisions of the input clock can be generated
with zero delay (see Tables 2 and 3). The standard
versions produce two outputs, where CLK2 is always a
divide by two version of CLKl.

On chip Phase Locked Loop for clock synchronization
Synchronizes frequencies up to 100 MHz (output)
±Ins skew (max) between input and output clocks
Can recover poor duty cycle clocks
CLKI and CLK2 skew controlled to within ± Ins
5 volt only power supply
Low power CMOS technology
Small 8 pin DIP or SOIC package
On chip loop filter
AV9170-0I, -04 for output clocks 20-100 MHz
AV9170-02, -05 for output clocks 5-25 MHz

The AV9I70 is also useful to recover poor duty cycle
clocks. A 50 MHz signal with a 20/80% duty cycle, for
example, can be regenerated to the 48/52% typical of the
part.

Pin Confiauration

FBIN u 8 CLK2
IN
2 7 VDD
GND
3 6 CLK1

FSO

4

5

The AV9I70 allows the user to control the PLL feedback,
making it possible, with an additional 74F240 octal buffer
(or other such device that offers controlled skew outputs), to synchronize up to 8 output clocks with zero
delay compared to the input (see Figure 1).

FS1

AV9170

Application notes for the AV9I70 are available. Please
consult ICS.

p.In DeSCrlpl10n
·f
Pin Name
FBIN
IN
GND

FSO
FSI
CLKI
VDD
CLK2

Pin #
1
2
3
4
5
6
7
8

Tvpe
Input
Input

Input
Input
Output

Output

Description
FEEDBACK INPUT
INPUT for reference clock
GROUND
FREOUENCY SELECT 0
FREQUENCY SELECT 1
CLOCK output 1 (See Tables 1, 2, 3, 6, 7 for values)
Power Supply (+5V)
CLOCK output 2 (See Tables 1, 2, 3, 6, 7 for values)

Block Dia ram
External Connection to CLKl or CLK2 (not both)

I--I~-~

FBIN
IN --t---~~~~

CLKl

h--lt--. CLK2

497

AV9170
Using the AV9170

Eliminate High Speed Clock
Routing Problems

The A V9170 has the following characteristics:
The AV9170 makes it possible to route lower speed
clocks over long distances on the PC board, and to place
an A V9170 next to the device requiring a higher speed
clock. The multiplied output can then be used to produce a phase locked, higher speed output clock.

1. Rising edges at IN and FBIN are lined up.

Falling edges are not synchronized.
2. The relationship between the frequencies at FBIN
and IN is shown in Table 1.
TABLE 1
FSI
0

a
1
1

FSO
0
1
0
1

fpBIN (-01, -02)

Compensate for Propagation Delays

fpBIN (-04, -05)

2·fIN
4·fIN
fIN
S·fIN

Including an AV9170 in a timing loop allows the use of
PALs, gate arrays, etc., with loose timing specifications.
The AV9170 compensates for the delay through the PAL
and synchronizes the output to the input reference clock.

3·fIN
5·fIN
6·fIN
10·fIN

3. The frequency of CLK2 is half the CLK1 frequency.

Operating Frequency Range

4. The CLK1 frequency ranges are:

The AV9170 is offered in versions optimized for operation in two frequency ranges. The -01 and -04 cover high
frequencies, 20 to 100 MHz. The -02 and -as operate from
5 to 25 MHz. The A V9170 can be supplied with custom
multiplication factors and operating ranges. Consult
ICS for details.

AV9170-Ol, -04
AV9170-02, -05

20 < fCLKl < 100MHz
5 < fCLKl < 25 MHz

The A V9170 will only operate correctly within these
frequency ranges.

A

lication of AV9170 for Multiple Out

REFERENCE

CLKl

CLOCK

AV9170

FBIN

CLK2

Figure 1

498

•

AV9170

Using CLK2 Feedback

Using CLK1 Feedback

Connecting CLK2 to FBIN as shown in Figure 2 will
cause all of the rising edges to be aligned (Fig. 4).

With CLKI connected to FBIN as shown in Figure 3, the
input and CLKI output will be aligned on the rising
edge, but CLK2 can be either rising or falling (Fig. 5).
Consult ICS if the CLKI frequency is desired to be higher
than 100 MHz.

1...

FBmL
IN

ICS9170-01

...

FBIN L

CLK2

IN
CLKI

CLK2

.

ICS9170-02
CLKI

Figure 2

Figure 3
For CLK1 frequencies 20 -100 MHz (-01)
For CLK1 frequencies 5 - 25 MHz (-02)

For CLK2 frequencies 10 - 50 MHz (-01)
For CLK2 frequencies 2.5 -12.5 MHz (-02)

FS1

FSO

CLK1 CLK2

FS1

FSO

0
0
1
1

0
1
0
1

INx4 INx2
INx8 INx4
INx2 IN
INx16INx8

0
0
1
1

0
1
0
1

CLK1 CLK2

INx2
INx4
IN
INx8

IN
INx2
IN+2
INx4

Table 3
Decoding Table for AV9170-01, 2 with CLKI Feedback

Table 2
Decoding Table for AV9170-01, 2 with CLK2 Feedback

IN

IN

CLK1

CLK2
CLK1
Figure 4
Input and Output Clock Waveforms with
CLK2 Connected to FBIN

Figure 5
Input and Output Clock Waveforms with
CLK1 Connected to FBIN

499

[I

AV9170

Using CLK2 Feedback

Using CLK1 Feedback

Connecting CLK2 to FBIN as shown in Figure 2 will
cause all of the rising edges to be aligned (Fig. 4).

With CLKI connected to FBIN as shown in Figure 3, the
input and CLKI output will be aligned on the rising
edge, but CLK2 can be either rising or falling (Fig. 5).
Consult ICS if the CLKI frequency is desired to be higher
than 100 MHz.

FBIN

L

IN
~

1

FBIN

CLK2

IN

ICS9170-04

L..

..
ICS9170-05

CLKl

CLKI

Figure 6
For CLK2 frequencies 10 - 50 MHz (-04)
For CLK2 frequencies 2.5 - 12.5 MHz (-05)

o
o
1
1

o
1

o
1

INx6
INxlO
INx12
INx20

CLK2

Figure 7
For CLK1 freq!Jencies 20 -100 MHz (-04)
For CLK1 frequencies 5 - 25 MHz (-05)

FSI
0
0
1
1

INx3
INx5
INx6
INxlO

FSO
0
1
0
1

CLKI
INx3
INx5
INx6
INxlO

CLK2
INxl.5
INx2.5
INx3
INx5

Table 6

Table 7

Decoding Table for AV9170-04, 5 with CLK2 Feedback

Decoding Table for AV9170-04, 5 with CLKI Feedback

IN~

\._ _ _ _~I

IN

~

\~_--.J/

\L-_ _

CLK2~~/~
CLK1~J\JV\JVV\J
Figure 8
Input and Output Clock Waveforms with
CLK2 Connected to FBIN

Figure 9
Input and Output Clock Waveforms with
CLK1 Connected to FBIN

500

II

AV9170

Absolute Maximum Ratings
Storage temperature ................................ -65°C to +150°C
Voltage on flO pins referenced to eND ...... eND -0.5V
toVDD+0.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to eND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those lIsted under Absolute MaXImum Ratings may cause permanent damage to the deVIce Th,s is a stress ratmg only, and
funchonal operahon of the deVIces at these or any other conditions above those mdIcated m the operahonal sechons of thIS specIftcatlOn IS not
ImplIed Exposure to absolute maXImum condIhons for extended penods may affect the relIabtlity of the deVIce.

Electrical Characteristics
(VDD= +5V± 5%, TA

Symbol

=

O°C to 70°C unless otherwise stated)

Parameter

Min

Tvp

-

-

Max Units

Conditions

DC Characteristics
V,L
VLH
ILL

I'H
VOL
VOH
VOH
VOH
100

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output High Voltage
Output High Voltage
Supply Current

Voo-.4V
Voo-·SV
2.4

-

-

-

20

50

V
V
IlA
IlA
V
V
V
V
rnA

-

-

-

-

ns
ns
ns
ns
ns
ns
%
%
ps
ps
%
MHz
MHz
MHz
ns

2.0
-5
-5
-

-

O.S

5
5
0.4

-

Voo=5V
Voo=5V
VIN =OV
V,N = Voo
IOL = SmA
IOH =-lmA,Voo =5.0V
IOH = -4mA,Voo=5.0V
IOH = -SmA
Unloaded, 100MHz

AC Characteristics
ICLK
ICLK;
t,
t,
tf

(kew1

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% V
Output Fall time, 2.0 to B~v
Fall time, SO% to 20% V
Output Duty cycle, A V9'f70-0l
Output Duty cycle, AV9170-02
Jitter, 1 sigma
Jitter, absolute
Jitter, absolute
Input Frequency
Output Frequency CLK1
Output Frequency CLK1
FBIN to IN skew

tskewl

FBIN to IN skew

-2

0.6

2

ns

tskew2

CLK1 to CLK2 skew

-1

0.4

1

ns

J

dt
Tt
TI ,

Tabs

f

abs

t

r

40
45
-500
-2%

1
2
1
2
4S/5
49/51
±120
±250

1
20
5
-1

0.4

10
10
2
4
2
4
60
55
300
500
2
67
100
25
1

15 pf load
15 pf load
15 pf load
15 pfload
15 pf load. Note 2, 3
15 pf load. Note 2, 3
For CLK1 > 10 MHz
For CLK1 < 10 MHz
Note 1
AV9170-01, -04
AV9170-02, -05
Note 2, 4. Input rise
time <5ns
Note 2, 4. Input rise
time -JVv,,-+-----I 2

7 i---t--'

AV9170
REFERENCE

CLOCK

33

3

6 t--+-'VV'v--~

4

5

Figure 10
AV9170 RECOMMENDED CIRCUIT CONFIGURATION
(arbitrary configuration of CLK1 feedback and pin 4, 5 logic states)

508

Application Note

AV9170

PIN 1

€&

=

connection to
ground plane
Figure 11
AV9170 Board Layout

5.0 Summary
The AV9170 is extremely flexible and provides utility in
a wide range of system clock and other applications, not
limited to those discussed in this application note. A
related product is the AV9173, which is designed for
video genlock (clock recovery) applications. Please refer
to the AV9173 data sheet. The AV9170 may have applications in similar circuits as well. If this application note
does not answer all of your A V9170 questions, please call
ICS's applications department.

509

Application Note

II

AV9170

to better decouple higher frequencies. The ferrite bead
shown in the VDD line does not enhance the AV9170
performance, but it will reduce EM! radiation from the
VDD line caused by AV9170 dynamic loading. External
feedback circuitry should have its own power supply
connection and decoupling capacitors.

be used in circuit design and layout to minimize noise
coupling. Using the guidelines given below will help
ensure stable, low-jitter clock performance.
For EM! sensitive applications, clock signals are one of
the biggest causes for FCC rejection. This is due to their
continuous, single-frequency character that is easily
picked up in the narrow band emitted frequency test.
Following the circuit and layout guidelines below will
help reduce EM!.

Except for very short clock output lines going to only one
load, itis good practice to use a 33 ohm series termination
resistor on the output clock line, as shown in Figure 10.
It should be placed close to the AV9170 output. This will
help reduce EM! and apparent clock jitter by damping
standing waves caused by wave reflection at the end of
the signal trace (which acts as a transmission line).

Figure 10 provides the AV9170 recommended external
circuit, not including any additional feedback circuitry.
A single power supply connection should be used to all
device pins. The 0.1 ~ decoupling capacitor should be
located as close to the VDD pin as possible. Above
50 MHz output frequencies, it may be helpful to replace
the 0.1 ~ capacitor with a lower value, such as 0.01 ~,

The recommended AV9170 PC board layout is shown in
Figure 11. The optional 33 ohm output termination
resistors or ferrite bead are not shown.

FERRITE
BEAD
+5V

I

O.1!1F

-=-

1------------

11

r~--_:~--_+~---AAA~--~OUTPUT
1
8
CLOCKS

')...IV\/'tr--+---------i 2

AV9170

REFERENCE
CLOCK

7 i--+-...J
33

3

61----+-'vv\t--~

4

5

Figure 10
AV9170 Recommended Circuit Configuration
(arbitrary configuration of CLK1 feedback and pin 4, 5 logic states)

510

AV9172

Integrated
Network
Systems, Inc.

•

Advance Information

Low Skew Output Buffer
Features
•
•
•
•
•
•
•
•
•
•
•

clock. The final outputs can be programmed to be
replicas of the 2x clocks or non-overlapping two phase
clocks at twice the reference frequency. The AV9172-01
operates with input clocks from 25 MHz to 50 MHz while
producing outputs from 25 MHz to 100 MHz.

AV9172-01 is pin compatible with Gazelle GA1210E
±250ps skew (max) between outputs
±500ps skew (max) between input & outputs
Input frequency range from 25 MHz to 50 MHz
Output frequency range from 25 MHz to 100 MHz
Special mode for two-phase clock generation
Inputs and outputs are fully TTL compatible
CMOS process results in low power supply current
High drive, 25mA outputs
Low cost
16 pin SOIC (300 mil) or 16 pin PDIP package

The use of a phase-locked loop (PLL) allows the output
clocks to run at multiples of the input clock. This permits
routing of a lower speed clock and local generation of a
required high speed clock. Synchronization of the phase
relationship between the input clock and the output
clocks is accomplished when one output clock is connected to the input pin FBIN. The PLL circuitry matches
rising edges of the input clock and output clocks.

General Description

The AV9172 is fabricated using CMOS technology which
results in much lower power consumption and cost
compared with the gallium arsenide based GA1210E.
The typical operating current for the AV9172 is SOmA
versus 120mA for the GA1210E.

The AV9172 is designed to generate low skew clocks for
clock distribution in high performance PCs and workstations. It uses phase-locked loop technology to align the
phase and frequency of the output clocks with an input
reference clock. Because the input to output skew is
guaranteed to ±500ps, the part acts as a "zero delay"
buffer.

rcs offers several versions of the AV9155.

The different

devices are shown below:

The AV9172 has six configurable outputs. The
AV9172-01 version has one output that runs at the same
phase and frequency as the reference clock. A second
output runs at the same frequency as the reference, but
can either be in phase or 1800 out of phase from the input
clock. Two outputs are provided that are at twice the
reference frequency and in phase with the reference

Block Dia ram

Part

Deseri tion

AV9172-01

Second source of GA1210

AV9172-03

Clock doubler and buffer

AV9172-07

Clock buffer

QO
QI
FBIN

Q2

CLKlN
DIVIDE
LOGIC

Q3

!NY'
EN2

Q4

Q5

L ______________________________

511

I

I

~

•

AV9172

Configuration Table for 9172·01
EN2 INVl*
0
0
1
1

0
1
0
1

Pin Configuration

QO

Ql

Q2

Q3

Q4

Q5

IX
IX
IX
IX

lX*
IX
lX*
IX

2X
2X
2X
2X

2X
2X
2X
2X

2X
2X
01
01

2X
2X
02
02

GND
GND

2

INVl*

3

Q5
~

Q4

4

-<
\D

Q3

5

~

Q2

eLKIN

6

0
'"-'

VDD

7

QO

VDD

8

GND

EN2
NOTES:
1. IX designates that the output is a replica of CLKIN
2. 2X designates that the output is twice the frequency of
CLKIN, and in phase
3. lX* means that the output is at the same frequency
andl80° out of phase (inverted) from CLKIN
4. 01 will produce a 1/4 duty cycle clock of CLKIN
5. 02 will produce a 1/4 duty cycle clock delayed 180
fromCLKIN

VDD

FBIN

'"-'

Ql

0

Pin Description for AV9172·01
PIN NAME
GND
GND
INVl*
EN
FBIN
CLKIN
VDD
VDD
GND
00
01
02
03
Q4
Q5
VDD

PIN #

PIN TYPE

1
2
3
4
5
6

-

7

8
9
10
11
12
13
14
15
16

Input
Input
Input
Input
-

Output
Output
Output
Output
Output
Output
-

DESCRIPTION
GROUND
GROUND
INVI * Inverts 01 when low
EN converts 04 and 05 to phase clocks when high
FEEDBACK INPUT from output QO
INPUT for reference clock
Power supplv (+5V)
Power sllJ2I)ly (+5V)
GROUND
QO phase and fr~uen~same as i~uti1X~ Feed back to.mn 5
01 is a Ix clock in phase or 180 0 out of phase with input
02 twice the frequency of 00 (2x)
03 twice the frequency of 00 (2x)
Q4 iseither a 2X clock or a two phase clock - see config. table
Q5 is either a 2X clock or a two phase clock - see config. table
Power supply (+5V)

512

II ~~~
AV917 2

Timing Diagrams for 9172-01
EN2 = 0 INVI = 0
FBIN=QO

INPUT
LOW
LOW

INPUT

INV!
EN2

eLKIN

Q5
Q4
Q3
Q2
Q!
QO
Q3
Q4

Q5~~
INPUT
QO

EN2 = 0 INVI = 1
FBIN = QO

HIGH
LOW

INV!
EN2

eLKIN

Q!~~

Q5
Q4
Q3
Q2
Q!
QO

Q2
Q3
Q4

Q5~~

INPUT
QO
LOW
HIGH

INVI
EN2

EN2 = 1 INVI = 0
FBIN = QO
INPUT

Q5
Q4
Q3
Q2
Q!
QO

Q!
Q2

Q3~~
Q4
Q5

INPUT
QO

EN2 = 1 INVI = 1
FBIN=QO

HIGH
HIGH

INPUT

INV!
EN2

eLKIN

Q5
Q4
Q3
Q2
Q!
QO

Q!
Q2

Q3~~
Q4
Q5

513

II

•

AV9172
Configuration Table for AV9172-03
(33 MHz Input)

EN2 INVl*
0
1
0
1

0
0
1
1

Pin Configuration

QO

Ql

Q2

Q3

Q4

Q5

GND

66
66
66
66

66
66
66
66

66
66
66
66

66
66
33
33

66
66
33
33

66
33
66
33

GND

2

INVl'

3

EN2

4

VDD
Q5

><:
\!J
.......

"-J
N

Q4
Q3

FBIN

5

eLKIN

6

VDD

7

QO

VDD

8

GND

I

Q2

0

Timing Diagram for AV9172-03

EN2

Q5

INVH

Q4

INPUT

Q3
Q2
Ql
33MHzIN QO
FBlN

QO-Q5

INPUT

33 MHz

Q3-Q5

~

(If 33 MHz modes selected)

514

w

Ql

AV9172

Configuration Table for 9172·07
(66 MHz Input)

EN2 INVl*

a
1

a
a

1

1
1

a

Pin Configuration

QO

Ql

Q2

Q3

Q4

Q5

GND

VDD

66
66
66
66

66
66
66
66

66
66
66
66

66
66
33
33

66
66
33
33

66
33
66
33

GND

Q5

INVl*

Q4

EN2

Q3

FBIN

Q2

eLKIN

Ql

VDD

QO

VDD

GND

Timing Diagrams for AV9172·07

EN2

INVl*
INPUT

Q5
Q4
Q3
Q2
Ql

66MHzIN QO
FBIN

INPUT
33 MHz

OO-Q5

Q3-Q5~
(If 33 MHz modes selected)

SIS

I

AV9172

Absolute Maximum Ratings
VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. DOC to +70°C
Storage temperature ................................ -65°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V

to VDD+O.5V
Power dissipation ................................................ 0.5 Watts

Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. and
functional operation of the devices at these or any other conditions above those Indicated In the operatIonal sections of thIS specIfication is not
Imphed. Exposure to absolute maXImum condItions for extended peflods may affect the reliabihty of the deVIce.

Electrical Characteristics
(VDD= +5V± 5%, TA = O°C to 70°C unless otherwise stated)

Symbol Parameter

Min

Typ

Max

Units
V
V
!lA
!lA
V
V
rnA

Conditions

DC Characteristics
VIL
VIH
IlL
IIH
VOL
VOH
1m

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current

-

-

O.S

2.0
-5
-5

-

-

-

-

0.5

5
5
O.S

2.4

-

-

-

35

60

-

-

10
10
1
2
1
2
55

VDD = 5V
VDD = 5V
VIN = OV
VIN = VDD
IOL = 25mA
IOH = -25mA
Unloaded, 50MHz

AC Characteristics
ICLK,
ICLKf
t,
t,
tf
tf
dt

tskewl

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% VDD
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VDD
Output Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input Frequency
Output Frequency
FBIN to IN skew

25
25
-500

tskewl

FBIN to IN skew
Skew between any 2 outputs
at same frequency
Skew between any 2 outputs
at different frequencies

T"
Tab,
f

(

tskew2

-300

50
100
500

ns
ns
ns
ns
ns
ns
%
ps
ps
MHz
MHz
ps

1000

-500

1000

ps

-250

±50

250

ps

Note 2, 4. Input rise
time <3ns
Note 2, 4. Input rise
time .t is a trademark of Intel Corporation

523

ICS9175

Configuration Table - ICS9175-04
(All units in MHz)

Pin Configuration
GND
GND

2

SCLKI

3

SCLKO

4

Xl

>-<

n
CfJ
\D
.....
~
(J]

5

I

0

*'"

16

VDD

15

Q5

14

Q4

13

Q3

12

Q2

11

Ql
QO

X2

6

VDD

7

10

VDD

8

9

SCLKI

SCLKO

QO

Ql

Q2

Q3

Q4

Q5

0
0
1
1

0
1
0
1

66
66
66
66

66
66
66
66

66
66
66
66

66
66
33
33

66
66
33
33

66
33
66
33

GND

-

P"In 0 escri"f
;llion for ICS917504
PIN NAME
GND
GND
SCLKI
SCLKO
Xl
X2
VDD
VDD
GND
00
01
02
03
Q4
Q5
VDD

PIN #

PIN TYPE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Invut
Input
Input
Input

Output
Outvut
Output
Outvut
Output
Output

-

DESCRIPTION
GROUND
GROUND
SCLKI selects number of 112 sveed clocks
SCLKO selects number of 1/2 speed clocks
Xl crystal output
X2 crystal output
Power suvvlv (+5V)
Power supply (+5V)
GROUND
00 is a 66 MHz clock
01 is a 66 MHz clock
02 is a 66 MHz clock
03 can be 66 MHz or 33 MHz clock
Q4 can be 66 MHz or 33 MHz clock
05 can be 66 MHz or 33 MHz clock
Power supply (+5V)

524

ICS9175

•

Configuration Table - ICS9175-05
(All units in MHz)

Pin Configuration
GND

1

16

VDD

GND

2

15

Q5

SCLKI

......

3

(')

14

Q4

[Jl

4

\0

......

13

Q3

Xl

5

'1
Ul
0
Ul

,

12

Q2

X2

6

11

Ql

VDD

7

10

QO

VDD

8

9

SCLKO

SCLK1

SCLKO

QO

Q1

Q2

Q3

Q4

Q5

0
0
1
1

0

60
60
60
60

60
60
60
60

60
60
60
60

60
60
30
30

60
60
30
30

60
30
60
30

1

0
1

GND

-

p.In Descri otlon for ICS917505
PIN NAME
GND
GND
SCLK1
SCLKO
Xl
X2
VDD
VDD
GND
00
01
Q2
03
Q4
05
VDD

PIN #

PIN TYPE

1
2
3
4
5
6
7
8
9
10

-

11

12
13
14
15
16

Input
Input
Input
Input

Output
Output
Output
Output
Output
Output

-

DESCRIPTION
GROUND
GROUND
SCLK1 selects number of 1/2 speed clocks
SCLKO selects number of 1/2 speed clocks
Xl crystal output
X2 crystal output
Power supply (+5V)
Power supply (+5V)
GROUND
00 is a 60 MHz clock
01 is a 60 MHz clock
Q2 is a 60 MHz clock
03 can be 60 MHz or 30 MHz clock
Q4 can be 60 MHz or 30 MHz clock
Q5 can be 60 MHz or 30 MHz clock
Power supply (+5V)

525

ICS9175

Configuration Table - ICS9175-06
(All units in MHz)

Pin Configuration
GND
GND
SCLKI
SCLKO
Xl

2

......

16

VDD

15

Q5

3

n
CJ)

14

Q4

4

\0

......

13

Q3

,

12

Q2

5

'1
U1

a

SCLKI

SCLKO

QO

Ql

Q2

Q3

Q4

Q5

0
0
1
1

0
1
0
1

52
52
52
52

52
52
52
52

52
52
52
52

52
52
26
26

52
52
26
26

52
26
52
26

0\

X2

6

11

Ql

VOD

7

10

QO

VDD

8

9

GND

-

P"In Descn"f
)1 Ion for ICS917506
PIN NAME
GND
GND
SCLKI
SCLKO
Xl
X2
VDD
VDD
GND
00
01
02
03
Q4
05
VDD

PIN #

PIN TYPE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Input
Input
Input
Input

-

Output
Output
Output
Output
Output
Output

-

DESCRIPTION
GROUND
GROUND
SCLKI selects number of 1/2 speed clocks
SCLKO selects number of 1/2 speed clocks
Xl crystal output
X2 crystal output
Power supply (+5V)
Power supply (+5V)
GROUND
00 is a 52 MHz clock
nl is a 52MHz _clock
~ is a 52 MHz clock
Q3 can be 52 MHz or 26 MHz clock
Q4 can be 52 MHz or 26 MHz clock
05 can be 52 MHz or 26 MHz clock
Power supply (+5V)

526

ICS9175

Absolute Maximum Ratings
Storage temperature ................................ -65°C to +150°C
Voltage on flO pins referenced to GND ...... GND -O.5V
to VDD+0.5V
Power dissipation ................................................ 0.5 Watts

VDD referenced to GND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C

Note: Stresses above those listed under Absolute MaXImum Ratings may cause permanent damage to the devIce. This IS a stress ratmg only, and
funchonal operation of the devices at these or any other condItions above those indicated In the operahonal sections of this specificatIOn is not
implied. Exposure to absolute maximum condItions for extended penods may affect the rehabihty of the devIce

Electrical Characteristics
(VDD= +5V± 5%, T A

Symbol

=

O°C to 70°C unless otherwise stated)

Parameter

Min

Typ

Max

Units

Conditions

-

-

O.S

2.0
-5
-5

-

0.5

V
V
IlA
IlA
V
V
rnA

Voo=5V
Voo=5V
VIN =OV
VIN = Voo
IOL =25mA
IOH = -25mA
Unloaded, SCLK = 00
15 pf load
15 pf load
15 pf load
15 pf load
15 pf load

100
250

ns
ns
ns
ns
%
ps
ps
MHz
MHz
ps

500

ps

Note 2, 4

DC Characteristics
VIL
VIH
IlL
IIH
VOL
VOH
100

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current

5
5
O.S

2.4

-

-

-

35

60

-

0.7
1.2
0.7
1.2
49/51
60
±200
14.31S

1
2
1
2
55

AC Characteristics
t,
t,
tf
tf
d,
T"
TabS

f

(
tskew2

Output Rise time, O.S to 2.0V
Rise time, 20% to SO% VDO
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VDO
Output Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input Frequency
Output Frequency
Skew between any 2 outputs
at same frequency
Skew between any 2 outputs
at different frequencies

45

-250

±50

Note 1
Note 2, 4

NOTES:
1. It may be possible to operate the ICS9175 outside of these ranges. Consult ICS for your specific application.
2. All skew specifications are measured with a 50n transmission line, load terminated with 50n to l.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at l.4V on rising edges. Loading must be equal on outputs.

527

•

ICS9175

Ordering Information
Part Number

Temperature Range

Package Type

ICS9175-xxCN16
ICS9175-xxCS16

O'C to +70'C
O°C to +70° C

16 lead PDIP
16 lead SOIC (300 mils)

528

ICS9176

Integrated
Circuit

l1~ml Systems,Inc.

Advance Information

Low Skew Output Buffer
Features
•
•
•
•
•
•
•
•
•
•

ICS9176-o1 is pin compatible with Triquint GAI086
±500 ps skew (max) between input and outputs
±250 ps skew (max) between outputs
10 symmetric, TTL-compatible outputs
28 pin J-Iead surface mount package
High drive, 40 rnA outputs
Power down option
Output frequency range 16 MHz to 130 MHz
Input frequency range 6 MHz to 80 MHz
Ideal for PCI bus applications

loop (PLl) acts either as a IX clock multiplier or a 1/2X
clock multiplier depending on the state of the input control pins TO and Tl. With metal mask options, any type of
ratio between the input clock and output clock can be
achieved, including 2X.
The Pll maintains the phase and frequency relationship
between the input clock and the outputs by externally
feeding back FBOUT to FBIN. Any change in the input
will be tracked by all 10 outputs. However, the change at
the outputs will happen smoothly so no glitches will be
present on any driven input. The PlL circuitry matches
rising edges of the input clock and the output clock. Since
the inputto FBIN skew is guaranteed to±500 psec, the part
acts as a "zero delay" buffer.

The ICS9176 has a total of eleven outputs. Of these,
FBOUT is dedicated as the feedback into the PLl and
another, Q/2, has an output frequency half that of the
The ICS9176 is designed specifically to support the tight remaining nine. These nine outputs can either be running
timing requirements of high-performance microproces- at the same speed as the input, or at half the frequency of
sors and chip sets. Because the jitter of the device is the input. The maximum rise and fall time of an output is
limited to ±250 psec, the ICS9176 is ideal for clocking 14 ns and each is TTL-compatible with a 40 rnA symmetric
Pentium™ systems. The 10 high drive (40 rnA), low- drive.
skew (± 250 psec) outputs make the ICS9176 a perfect fit
for PCI clocking requirements.
The ICS9176 is fabricated using CMOS technology which
results in much lower power consumption and cost comThe ICS9176 has 10 outputs synchronized in phase and pared with the gallium arsenide based 1086E. The typical
frequency to an input clock. The internal phase locked operating current for the ICS9176 is 60mA versus 115mA
for the GAI086E.

General Description

Block Diagram

Selection Table
Tl

To

Description

10

0

Power Down

0

1

Test Modejpll Off ClK = ou.m.ut~l

Q3

1

0

Normal(PllOn)

Q4

1

1

Divide by 2 Mode

FBOUT

Q2
CLK

DIVIDE
LOGIC
TO
11

Q5
Q6
Q7
Q8
~

Q/2

529

ICS9176

i

Pin Configuration

>::

"u ~
.J

~ ~

~

"

TO

VOD

VOD

Q9

Qf2

Q8

GND

GND

FBOUT

\ll

QI

Q6

VOD

VOD

p.In 0 escriptlon
Pin Name
GND
08
Q9

VDD
GND
NC
NC
VDD
CLK
T1
FBIN
TO
VDD
0/2
GND
FBOUT
Q1

VDD
GND

Q2
Q3
VDD
Q4
Q5
GND
VDD
Q6
Q7

"
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Pin type

Output
Output
-

Input
Input
Input
Input

Output

Output
Output

Output
Output

Output
Output
-

Output
Output

Description
GROUND
Output clock 8
OuIQut clock 9
Power supply (+5V)
GROUND
No connect
No connect
Power supply (+5V)
Input for reference clock
T1 selects normal operation, powerdown or test mode
FEEDBACK INPUT from output FBOUT
TO selects normal operation. powerdown or test mode
Power Supply (+5V)
Half-clock output
GROUND
FEEDBACK OUTPUT to Input FBIN
Output clock 1
Power Supply (+5V)
GROUND
Output clock 2
Output clock 3
Power supply (±5V)
Output clock 4
Output clock 5
GROUND
Power Supply (±5V)
Output clock 6
Output clock 7

530

ICS9176
Applications
FBOUT is normally connected to FBIN to facilitate input
to output skew control. However, there is no requirement that the external feedback connection be a direct
hard~ire from an output pin to the FBIN pin. As long as
the signal at FBIN is derived directly from the FBOUT
pin and maintains its frequency, additional delays can be
accommodated. The clock phase of the outputs (rising
edge) will be adjusted so that the phase of FBIN and the
input clock will be the same. See Figure 1 for an example.

The ICS9176 is also ideal for clocking multi-processor
systems. The 10 outputs can be used to synchronize the
oferation of CPU cache and memory banks operating at
different speeds. Figure 2 depicts a 2-CPU system in
~hich processors and associated peripherals are operatmg at 66 MHz. Each of the nine outputs operating at 66
MHz are fully utilized to drive the appropriate CPU,
cache and memory control logic. The 33 MHz output is
used to synchronize the operation of the slower memory
bank to the restart of the system.

FBIN

'--

~

FBIN
ICS9176

66MH

+2

SYSTEM ----+

33MH2

II

FBOUT

QI

CLOCK

Q2
Q3
Q4

Figure 1

Q5

MEMORY
CONTROL
LOGIC

Q6

In ~igu.re.1, t~e ~ropagation delay through the divide by
2 CircUit IS elimmated. The internal phase-locked loop
will adjust the output clock on the ICS9176 to ensure zero
phase delay between the FBIN and CLK signals, as a
result, the rising edge at the output of the divide by two
circuit will be aligned with the rising edge of the 66 MHz
input clock. This type of configuration can be used to
eliminate propagation delay as long as the signal at FBIN
is continuous and is not gated or conditional.

Q7

CPU2

GND----+

Q8

CACHE

VDD -------+-

Q9
Q/2
SLOW

MEMORY
CONTROL
LOCIC
(33MHZ)

Figure 2

531

ICS9176
Timing Diagrams

INPUT CLOCK
QI-Q9

Q/2

Timing in Divide by 1 Mode

INPUT CLOCK

L--_---II
----II

QI-Q9

Q/2

L - -_ _ _

Timing in Divide by 2 Mode

INPUT CLOCK

QI-Q9

Q/2

Timing in Eliminate by Test Mode

Note:

In test mode, the veos are bypassed. The test clock input is simply buffered, then output.
The part is transparent. Damage to the device may occur if an output is shorted or
forced to ground or VDD.

INPUT CLOCK _ _-,
QI-Q9
Q/2

Timing in Power Down Mode

532

II

ICS9176

Absolute Maximum Rating
VDD referenced to eND ................................................ 7V
Operating temperature under bias ............. O°C to +70°C
Storage temperature ................................ -65°C to +150°C

Voltage on I/O pins referenced to eND ...... eND -0.5V
to VDD +O.5V
Power dissipation ................................................ 0.5 Watts

Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the devIces at these or any other conditIOns above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maXImum conditions for extended pen ods may affect the reliabIlity of the devIce.

Electrical Characteristics
(VDD= +5V± 5%, TA = O°C to 70°C unless otherwise stated)

Symbol

Parameter

Min

Typ

Max

Units

V
V

Conditions

DC Characteristics
VIL
VIH
IlL
IIH
VOL
VOH
100

AC

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current
('L

ICLK
ICLK;
t,
t,
tf
tf
dt
Tlo
Tabs

f

(
tskewl

tskew2

... .....

Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% V00
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VDO
Output Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input Frequency
Output Frequency
FBIN to IN skew
Skew between any 2 outputs
at same frequency
Skew between any 2 outputs
at different frequencies

-

-

O.S

2.0
-5
-5

-

-

-

-

0.5

5
5
O.S

~

voo= 5V
Voo = 5V
VIN =OV
VIN = Voo
10L = 25mA
10H = -25mA
Unloaded, 66.66MHz

2.4

-

-

J..lA
V
V

-

55

110

rnA

-

-

10
10
1
2
1
2
55

-300

300
50
130
500

ns
ns
ns
ns
ns
ns
%
ps
ps
MHz
MHz
ps

±50

250

ps

Note 2, 4. Input rise
time <3ns
Note 2,4

500

ps

Note 2, 4

45
-300
25
16
-500
-250

0.7
1.2
0.7
1.2
49/51
60
±200

15 pf load
15 pfload
15 pfload
15 pf load
15 pf load

Note 1

NOTES:
1. It may be possible to operate the ICS9176 outside of these ranges. Consult ICS for your specific
application.
2. All skew specifications are measured with a son transmission line, load terminated with son to l.4V.
3. Duty cycle measured at l.4V.
4. Skew measured at l.4V on rising edges. Loading must be equal on outputs.

533

ICS9176
Od·
r erma If
normaf Ion
Part Number
AV9176-xx

Part Marking

Temperature Range

Package Type

O·Cto+70·C

28 lead PLCC

534

ICS
Special Purpose IC Applications

535

536

Pentium™ Applications

I\;fu~ated
Circuit

Applications Note

Systems, Inc.

Clocking Intel Pentium Based Systems
The Intel Pentium processor brings new levels of
performance to PC based desktop systems. Unfortunately
for the system designer, italso places higher demands on
the system clocking. Jitter, high and low time, and skew
are carefully specified. Oscillators may be expensive or
difficult to obtain for the frequencies needed. Oock
skew can be difficult to control.

24 MHz

14.318 MHz
xTAl

12 MHz

o

14.318 MHz

CPU

ICS offers a number of solutions for the Pentium system
designer, from our workhorse AV9155, proven in millions
of 386 and 486 systems, to the AV9175, with its 6 skew
controlled outputs. The AV9172 and AV9176 are pin and
function compatible CMOS alternatives to GA1210 and
GAI086 GaAs PLL clock drivers.
For low cost systems, where only the processor is clocked,
the simplest solution is to use the AV9155-23, shown in
Figure 1. This clock generator features fixed outputs of
1.84,16,24, 12, and two 14.318 MHz. The CPU output can
be selected with the three address pins to one of eight
frequencies, including 66.66, 60, and 52 MHz. A CPU /2
output is also provided, which is skew matched to
typically 200 ps.
The AV9154-27 shown in Figure 2 offers the most
commonly used system clocks of 1.84, 24, 12 and 14.318
MHz, as well as a single CPU output which can be set to
one of eight frequencies. The 16 pin package uses very
little board space.

1.843 MHz

AV9154-27

(:I2,40.so.52,6O,66,75,80 MH7)

Figure 2

High performance systems have more demanding clock
requirements. The processor, cache controller, local bus
accelerators, and PCI-EISA bridge require low skew, low
jitter clocks. The AV9172 is a phase-locked loop buffer
with 6 outputs - four at the CPU frequency and two at 1/
2 CPU frequency. Two of the CPU outputs can be
configured as non-overlapping clocks. The AV9172 has
guaranteed skew of 250 ps between outputs running at
the same frequency (50 ps typical) and 500 ps between Ix
and l/2x outputs. A typical configuration is shown in
Figure 3. The output frequency is exactly Ix or 2x the
input frequency with ±5oo ps skew between input and
output.

AV9172
t-=-~66MHz

AV9155-23
14.318 MHz
xTAl

1.843MBz
16 MHz
24 MHz

fo>"''--~66MHz

elK

1-"""-~66MHz

12MBz

o

P"=---~

}14.318MHz

CPU

FBIN

(32,40.';0.52,60,66,75,80 MHz)

66 MHz

1-'-/-'-""'" 33 MHz

L __~..>r.::..r~33MHz

CPU/2

Figure 1

Figure 3
Pentium'I1ll is a trademark of Intel Corporation

537

Pentium™ Applications

II
- --

Applications Note

An ideal source for the 1 /2x clock required by the AV9172
is the AV9155-23 mentioned earlier. This gives the system
designer all the fixed clocks that he requires, as well as
low jitter, skew matched copies of the CPU and 1/2 CPU
clocks (Figure 4). The AV9172 is a direct replacement for
the Gazelle GAl21O,but fabricated ina high speed CMOS
process rather than expensive gallium arsenide.

1-4318MHz
xTAL

---

The AV9175 is a single frequency clock generator which
synthesizes standard Pentium system frequencies from a
low cost 14.318 MHz crystal. Using the select pins, the
designer can allocate the six outputs to be either lxor 1/
2x outputs as shown in Figure5. The AV9175 may also be
driven directly from the 14.318 MHz output of the AV915523 as shown in Figure 6. This gives the system designer
all required fixed clocks, six skew matched CPU clocks
plus another CPU and 1/2 CPU output, which can be
independently varied in frequency.
The AV9176 is a direct replacement for the Gazelle GAI086,
which features ten skew matched outputs. Additional
information will be forthcoming.

1.843Mfu
16 MHz
24 MHz
12 MHz

AV9155-23

---

}14.318MHz
CPU

CJ

{32,40,so"s2,60,66,7S,WJMHz}

CPU/2

66 MHz

AV915S·23

66 MHz

24 MHz

14.318MH
x'fA

66 MHz

12 MHz

o

6. MHz

1.843 MHz
16 MHz

}t<.318 MHz
CPU A

33 MHz

(32AQ,50,52,.6(J,66,75,oo MHz)

CPUA/2

33 MHz

A V9175 (choose 52, 60, or 66 MHz versions)
ALL CPU ANDCPU/20UfPUrSSKEW CONTROLLED

}

CPUD OUTPUTS

xl

Figure 4
N

x2

CONFIGUREASCPUDOR
} CPU 8/2 OUTPUTS

51..50:

0
CPU A AND CPU D FREQUENCIES ARE INDEPENDENT

14.318MHzD

51

CPU

CPU

CPU

CPU

so

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPlJ/2 Cl'lJ/2

CPU

CPU

CPU/2 CPU/2

CPU

CPU/2 CPU

Figure 6

xTAL
CJ>U/2

VERSIONS AVAIlABLE FOR CPU = 52, 60, AND 66 MHz

Figure 5

538

ICS

High-Performance
Products

ICS continues to set new standards for High-Performance Frequency Synthesis, and this latest product
offering represents the highest frequency performance and widest choice of products in the industry.
ICS puts its unique mixed signal CMOS technology to work, offering high frequency video and CPU
timing solutions and features previously unavailable in the market. For example, the ICS1562 video
graphics clock is being utilized successfully in customer CPU and video applications to over 400 MHz.
New products in this issue of the ICS data book include a 180 MHz version of the very popular
ICS1562, (ICSI572), a 'line lock' clock for synchronizing with low frequency references (ICSI522),
and a dual PLL clock with both video and memory outputs. These new products also offer the
advantages available across the ICS High Performance line - features such as user programmability,
extremely low jitter, and multiple outputs.
ICS High-Performance Products are designed with and for you, our customers. Our customer dialog
is continuous, and we welcome the opportunity to discuss how we can put our High-Performance to
work for you.

539

n

iii

ICS High-Performance Product Selection Guide

I

Product
Applications

rcs
Device Type

Features

Package Types

ICSl522

User-Programmable Frequencies,
'Line Lock' Capability

24 Pin
SOlC

. -----,-_.-

ICS1561

-.- 2,4, 8 TTL Out. Integral Loop Filter.
FJQTREcOMMENDED FOR NEW DESIGN

I

---

ICSl56lA

-~.

,

ICSl562

-- --

1---~1

User-Programmable Frequencies.
RAMDACTM Reset Logic
(Brooktree compatible).

16 Pin
Narrow
SOIC

557

20 Pin
DIP, SOlC

575

32 Frequency ROM-based RAMDAC
Reset Logic (Brooktree compatible).

ICSI572

User-Programmable Frequencies.
RAMDAC Reset Logic
(Brooktree compatible).

ICS2572

~

549

20 Pin
DIP, SOlC

ICS1567

f-----

20Pm
DIP, SOlC

541
. .- . .

-.- 2, 4, 8 TTL Out. Integral Loop Filter.
Replaces ICSl561.
- - - - - - - _..

Workstation
Clock
Generators

I

---"-

Page

I

-

I

User-Programmable Dual PLL.
16V+ 4M Locations.
---..-L

20 Pin
SOlC

...

~

---I
!

585

I

20 Pin
DIP, SOIC

I

.L

603

Notes:
I. All products have internal loop filters except as noted.
2. All products operate at 5V typo except as noted.

ADVANCE INFORMATION documentscontam mformatIon on new products III the sampitngor preproductlOll phase of development CharactenstIc
data and other speCificatIOns are subject to change Without notice
PRODUCT PREVIEW documents contam mformatIOn on products In the formative or deSIgn phase of development. Charactensttc data and other
speCIficatIOns are deSign goals ICS reserves the nght to change or discontinue these products Without notice.

540

•

ICS1522

Integrated
Circuit
Systems, Inc.

Product Preview

User-Programmable Video Clock Generatorl
Line-Locked Clock Regenerator

Description

Features

The ICS1522 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing ICS'
advanced CMOS mixed-mode technology, the ICS1522
provides a low-cost solution for high-end video clock generation where synchronization to an external video source is
required.

•

•
•

The ICS1522 has differential video clock outputs (CLK+
and CLK-) that are compatible with industry standard video
DAC.

•
•
•

Operating frequencies are fully programmable with direct
control provided for reference divider, pre-scaler, feedback
divider and post -scaler.

•
•

Serial programming: Input and reference divisors,
VCO gain, phase comparator gain, delay, and test
modes
Supports high-resolution graphics - Differential CLK
outputs to 230 MHz
Eliminates need for multiple ECL output voltage controlled crystal oscillators and external components
Fully-programmable synthesizer capability - not just a
clock multiplier
Line-locked clock generation capability; 15 - 100 kHz
External feedback loop capability allows graphics system to be used as the feedback divisor
Small footprint 24-pin SOIC
Phase adjustment permits precise clocking in video
recovery application

Applications
•
•
•

Block Diagram

LCD Projector Systems
Multimedia video line locking
Genlock applications
v-veo

I-PUMP

PDEN

EXTVCO

PROGRAMMING
INTERFACE
----~IPROG

,--;;:;:;:-1-------

~'CLK+
L=""--_j----- ____ CLK-

~-r-r~~~--~

0

541

II

ICS1522
Overview

Output Post-Scaler

The ICS1522 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just
simple multiples of the reference frequency. The ICS1522
uses the latest generation offrequency synthesis techniques
developed by ICS and is completely suitable for the most
demanding video applications.

A programmable post-scaler may be inserted between the
YCO and the CLK+ and CLK- outputs of the ICS1522.
This is useful in generating oflower frequencies, as the YCO
has been optimized for high-frequency operation.
The post-scaler allows the selection of:

PLL Synthesizer Description Ratiometric Mode
The ICS1522 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference
frequency is generated byan on-chip crystal oscillator or the
reference frequency may be applied to the ICS1522 from an
external frequency source, typically horizontal sync from
another display system.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or YCO, to a frequency that will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:
F(

Address 101
Data Bits 6,7

Feedback +
Feedback +
Feedback+
Feedback+

1
2
4
8

11

01
10
00

01
10
00

11

Data Bits 0, 1,2

Address 110

The YCO gain is programmable, which permits the ICS1522
to be optimized for best performance at all operating frequencies.

Function

YCO frequency
YCO frequency'" 2
YCO frequency'" 4
YCO frequency.,. 8

The ICS1522 has an additional programmable divider (referred to in Figure 1 as the load counter) that is used to
generate the LOAD clock frequency for the video DAC.
The modulus of this divider may be set to 3,4,5,6, 8, or 10
under register control. The design of this divider permits
the output duty factor to be 50/50, even when odd modulus
is selected. The input frequency to this divider is the output
of the output post-scaler described above.

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).

The reference divider may be programmed for any modulus
from 1 to 1024 in steps of one.

Address 101
Data Bits 4,5

Load Clock Divider

. _ F(XTALl) . Feedback Divider
veo). Reference Divider

The feedback divider may be programmed for any modulus
from 1 to 2048 in steps of one followed by a divide by 1, 2, 4
or 8 feedback post-scaler.

Function

L(2)

L(1)

L(O)

Divide Ratio

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

3
4
4
5
6
8
8
10

Digital Inputs - ICS1522
The programming of the ICS1522 is performed serially by
using the SDATA, SCLK, and SELn pins to load the 7, 11 bit
internal memory locations.
Single bit changes are accomplished by addressing the appropriate memory location and writing only 11 bits of data,
not by writing all 77 data bits.
For proper programming of the ICS1522, it is important that
all transitions of the SELn input occur during the same state
ofthe SCLK input.

542

II

ICS1522

SDATA is shifted into a 15 bit serial register on the rising
edge of SCLK while SELn is low. The first bit loaded is
RIWn followed by a 3 bit address and II bit data (both
address & data are LSB first). When a rising edge ofSCLK
occurs while SELn is high (SDATAignored), the contents of
the serial register are loaded into the addressed II bit
memory location if RIWn is low. If RIWn is high upon the
above condition, the data from the addressed memory location is loaded into the serial shift register and SDATA is set
as an output. The RIWn bit, 3 bit address, and 11 bit data
will be serially shifted out of the ICS1522 on the SDATA pin
on the rising edge of SCLK while SELn is low.
An additional control pin on the ICS1522, PDEN can be
used to disable the phase-frequency detector in line-locked
applications. When disabled, the phase detector will ignore
any inputs and allow the VCO to coast. This feature is useful
in systems using composite sync.

Output Description
The differential output drivers, CLK+ and CLK-, are current-mode and are designed to drive resistive terminations
in a complementary fashion. The outputs are current-sinking only, with the amount of sink current programmable via
the IPRG pin. The sink current, which is steered to either
CLK+ or CLK-, is four times the current supplied to the
IPRG pin. For most applications, a resistor from VDDO to
IPRG will set the current to the necessary precision.

The loop phase is locked to the rising edges of the
XTALlIEXTREF input signal, if REF _POL is set to logic O.

RO

VAA

Rl'

-------".Rt
0.<-

Clock·

r-~~~w~---+~~CIock

Typical Output Circuitry Configuration
Line-Locked Operation
Some video applications require a clock to be generated that
is a multiple of horizontal sync. The ICS1522 supports this
mode of operation. The reference divider should be set to
divide by one and the desired polarity (rising or falling) of
lock edge should be selected. By using the phase detector
hardware disable mode (PDEN), the PLL can be made to
free-rum at the beginning of the vertical interval of the
external video, and can be reactivated at its completion.

Reference Oscillator and
Crystal Selection

External Feedback Operation

The ICS1522 has circuitry on-board to implement a Pierce
oscillator with the addition of a quartz crystal and two
external loading capacitors. Pierce oscillators operate the
crystal in anti- (also called parallel-) resonant mode.

The ICS1522 option also supports the inclusion of an external counter as the feedback divider ofthe PLL. This mode
is useful in graphic systems that must be "genlocked" to
external video sources.

Series-resonant crystals may also be used with the ICS1522.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically
0.025-0.05% ).

When the FBK_SEL bit is set to logic 0, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal
applied to the EXTFBK input ifFBK_POL is set to logic O.

As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
A void routing digital signals or the ICS1522 outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the ICS1522, it is important that it be jitter-free. The rising
and falling edges of that signal should be fast and free of
noise for best results.

543

II

ICS1522
Power-On Initialization

Power Supplies and Decoupling

The ICS1522 has an internal power-on reset circuit that sets
the multiplexer to pass the reference frequency to the
CLK+ and CLK- outputs.

The ICS1522 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH ofthese pins
should connect to the ground plane of the video board as
close to the package as is possible.

These functions should allow initialization of most graphics
systems that cannot immediately provide for register programming upon system power-up.
Because the power-on reset circuit is on the VDD supply.
and because that supply is filtered. care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD supply
reaches four volts.

Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1522 supports

The ICS1522 has a VDDOpin which is the supply of + 5 volt
power to all output drivers. This pin should be connected
to the power plane (or bus) using standard high-frequency
decoupling practice. That is, capacitors should have low
series inductance and be mounted close to the ICS1522.
The VDD pin is the power supplypin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application
circuitry). This will allow the PLL to "track" through power
supply fluctuations without visible effects.

this through a register programmable mode, AUXEN.
When this mode is set, AUXCLK will directly control the
logic levels of the CLK+ and CLK- pins while OMUXl,
OMUX2, OMUX3, and OMUX4 will control OUTl,
OUT2, OUT3 and OUT4, respectively.

Pin Descriptions
PIN NUMBER
If-------

I
2
3
4
5
6
7
8
9
10
11
12
13
14
IS
16
17
18
19
20
21
22
23
24

PIN NAME
IPUMP
SDATA
SCLK
SELn
AVDD
XTALI/EXTREF
XTAL2
Reserved
VSS
VSS
OUT4
OUT3
VDD
OUT2
OUT!
VSS
IPRG
CLKCLK+
VDDO
PDEN
EXTFBK
EXTVCO
VVCO

TYPE
OUT
IN/OUT
IN
IN
PWR
IN
OUT
NC
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
OUT
OUT
PWR
IN
IN
IN
IN

DESCRIPTION
Charge Pump Output (External loop fIlter apphcatlOns
Senal Data Input/Output
Senal Clock Input
Senal Port Enable
Analog + 5 Volt Supply
External Reference Input / Xtal OscIllator Input
Xtal OscIllator Output

~

Reserved for future applIcatIOn

Ground
Ground
Output 4
Output 3
DIgItal + 5 Volt Supply
Output 2
Output I
Ground
Output Dnver Current Programmmg Input
DIfferentIal CLK- Output
Differential CLK+ Output
Output Driver + 5 Volt Supply
Phase Detector Enable
External Feedback Input
External VCO Input
VCO Control Voltage Input (External loop filter apphcatIOns)

544

II

ICS1522

Absolute Maximum Ratings
VDD, VDDO (measured to Vss) ........ , .......
Digital Inputs ...............................
Digital Outputs ..............................
Ambient operating temp ......................
Storage temperature .........................
J unction temperature. . . . . . . . . . . . . . . . . . . . . . . ..
Soldering temperature ........................

7.0V
V ss -0.5 to VDD to 0.5V
VSS -0.5 to VDDO to + 0.5V
-55 to 125 0 C
-65 to 150 0 C
175 0 C
2600 C

Recommended Operating Conditions
VDD, VDDO (measured to Vss) ................ 4.75 to 5.25V
Operating Temperature (Ambient) ............. 0 to 700 C

DC Characteristics
TTL-Compatible Inputs
(PDEN, EXTFBK, SDATA, SClK, SELn)

PARAMETER

MIN

MAX

UNITS

Input High Voltage

SYMBOL
Vlh

CONDITIONS

2.0

VDD + 0.5

V

Input Low Voltage

VI!

Vss - 0.5

0.8

V

.20

.60

V

Input Hysteresis
Input High Current

Ilh

Vlh = VDD

-

10

uA

Input Low Current

II!

VI!= 0.0

-

200

uA

Input Capacitance

Cm

-

8

pF

XTAL1/EXTREF Input and EXTVCO

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Input High Voltage

Vxh

3.75

VDD + 0.5

V

Input Low Voltage

Vxl

Vss - 0.5

1.25

MIN

MAX

ClK+ , ClK- Outputs

PARAMETER

SYMBOL

CONDITIONS

lfferential Output Voltage

UNITS

V

0.6

OUT1, OUT2, OUT3, OUT4 Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

Output High Voltage
(Ioh= 4.0mA)

2.4

Output Low Voltage
(101= 8.0mA)

-

545

MAX

UNITS
V

0.4

V

ICS1522
AC Characteristics
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Fvco

VCO Frequency

14

230

MHz

Fxtal
Cpar

Crystal Freq uency

5

20

MHz

100

kHz

Crystal Oscillator Loading Capacitance

-----

20

pF

Horizontal Sync Rate

15

Txhl

XTALI High Time (when driven externally)

8

ns

Txlo

XTALI Low Time (when driven externally)

8

ns

FHSYNC

TnT

Phase Jiller (see Note I)

Tlock

PLL Acq uire Time (to within 1%)

1

500

ns
~s

Idd

VDD Supply Current

15

mA

lddo

VDDO Supply Current (excluding CLK+ /termination)

20

mA

ANALOG INPUTS
TFPH

Fine Phase Adjustment Range

0

10

ns

VFPH

Control Voltage for FPHADJ

0

5

VDC

FPHADJ Input Bias Current

20

nA

Capacitance ofFPHADJ Input

100

pF

1.5

kHz

Bandwidth ofFPHADJ Input (3dB)

0.5

DIGITAL INPUT
SELn, SDATA Setup Time

10

ns

SELn, SDATA Hold Time

10
20

ns

SCLK Pulse Width (Thi or Tlo)

ns

SCLK Frequency

20

MHz

Phase-frequency detector enable time

50

ns

Phase-frequency detector disable time

50

ns

DIGITAL OUTPUTS
TSKEW

Time Skew between CLK+ ,CLK-

500

pS

FCLK

CLK+ and CLK- Clock Rate

230

MHz

VCO

VCO Gain, VCO(0:2)

IS

100

MHzlV

PFD

Phase Detector Gain, PFD (0:2)

.05

12

~A/rad

GAINS

Note 1: TnT is the total uncertainty of the phase measured at the start of a video line on a 350 MHz oscilloscope under
these conditions: HSYNC pin driven with crystal oscillator at 48.363 kHz; Fvco = 65.000 MHz; M = 0
(divide by 1 on the output; and N = 1343 (1344 clocks per line).
Note 2: TDRIFT is the difference between the average phase at the start of the line and the average phase at the end of
the line as measured under the same conditions as in Note 1.

546

[I

ICS1522

Memory Definition
ICS1522 memory is loaded serially with the least significant bit clocked into the device first. After the R/Wn bit, the next
three bits of the programming word (15 bits) hold the memory location to be loaded. The least significant 11 bits are the
data to be loaded.

Default

Memory
Address

I Values

I
Data Bits

I

(Hex)

Name

Description

F(O:lO)

Fccdback Divider Modulus (Modulus

LO(0:7)

M Counter Lo Sync State

000

0-10

001

0-7

001

8-10

0

010

0-7

06

010

8-10

0

Oll

0-9

013

R(0:9)

011

10

0

REF_POL

External Reference Polarity (1

100

0-2

4

VCO(0:2)

VCO Gain (See Table)

100

3-5

3

PFD(0:2)

Phase Detector Gain (See Table)

100

6

1

PDEN

100

7

1

INLFLT

Internal Loop Filter (1

04F

I

03

I

=

Value + 1)

Don't Care
HI(0:7)

M Counter Hi Sync State
'Don't Care

=
= Invert)

Reference Divider Modulus (Modulus

Phase Detector Enable (1

=

=

Value + 1)

= Enable)
Internal)

100

8

1

INT_VCO

Internal VCO (l

100

9

0

CLK_SEL

Internal feedback input clock select (0 = VCO
Output)

100

10

0

Reserved

Reserved - Set to Zero

0

1

FBK_SEL

Feedback Select (1

101

1

0

FBK]OL

External Feedback Polarity (l

101

2

0

ADD

101

3

0

SWLW

101

4-5

0

PDA(O:l)

Output Post-Scaler

101

6-7

3

PDB(O:l)

Feedback Post-Scaler

101

._-

Internal)

= Internal)
= Invert)

Addition of 1 VCO Cycle (0 to 1 = Add)
Removal of 1 VCO Cycle (0 to 1 = Swallow)

Don't Care

101

8-10

0

110

0-2

7

L(0:2)

110

3

0

OMUX1

oun Select (0 =

110

4

0

OMUX2

OUT2 Select (0 = Int Fbk, 1 = Div By 4 90Deg)

110

5

0

OMUX3

OUT3 Select (0 = Sync Lo, 1 = DivBy4180Deg)

110

6

1

OMUX4

OUT4 Select (0 = Sync Hi, 1 = Div By 4 270Deg)

110

7

0

DACRST

Output Reset (CLK+

110

8

0

AUXEN

Output Test Mode (1

AUXCLK

Load Counter
Load Cntr, 1 = Div By 4 ODeg)

-

110

9

0

110

10

0

Output Clock When in Test Mode
Don't Care

547

= 1, CLK- = 0)
= Test, See Board Test Support)

ICS1522
Pixel-by-Pixel Adjustment of
Genlocking Phase
To understand the operation of the pixel-by-pixel phase
adjustment feature, imagine that the modulus of the on-chip
divider (that is, NI X N2) is equivalent to the graphics system
overall divide. Also, imagine that the overflow of the internal
N2 divider occurs at the same time as the overflow of the
graphics system line counter. We would be able to switch
carefully between both dividers with no effect on the loop.
Let us assume that we are now using the internal divider.
Now, imagine that the programmed value of the Nl divider
(really a pre-scaler) is increased by one for a single passthrough that pre-scaler (think of this as "swallowing" a feedback pulse). We will lose exactly one CLK period of phase
in the feedback path. The VCO will speed up momentarily
to compensate for that, and re-lock the loop.
In doing so, the graphics system will receive exactly one extra
CLK cycle, advancing the phase of the graphics system
HSYNC by one CLK period relative to the reference
HSYNC. In a similar fashion, we can decrease the programmed value of the prescaler ("adding" a pulse) to retard
the phase of the graphics system.
Initial synchronization can be performed (to within + /CLK) by a scheme where the internal counters are held in
reset until an HSYNC pulse is returned from the graphics
system.

Ordering Information
All ICS devices in SOIC packages carry an 'M" designation.
Example: ICS1522M

548

ICS1561

Integrated

Circuit
Systems, Inc.

•

Differential Output Video Dot Clock Generator
Features

Applications

•

High frequency operation for extended video modes -

•

Workstations

•

up to 180 MHz
Compatible with Brooktree high performance RAMDACSTM

•
•
•

High resolution MACH displays
EGA - VGA - Super VGA video ada
8514A - TMS 34010 - TMS 340

G

•
•
•

clock oscillators in video display subsystems
Strobed fTransparent frequency select options
Mask-programmable frequencies

•
•
•

non-strobed
Advanced PLL for low phase-jitter
Dynamic control of VCO sensitivity

•

rri=d wop ,.;no_en,IT, fr'4 00

"''0V
providi~

(tj

cl

~

k.~\

Ii
The IC 1
Dot
eneraf
abl

c
enerator is
up 032
0

'~~:I~.tn~for

e

cui
uencies

FSI

vid

ms. U tilizin
ec nolo
II II ear, digital and
ryfuncti
Ipro es a low power, small
t
generation of video dot
es e compatible with VGA, EGA,
,
as well as the higher frequencies
dvance applications in desktop publishing and
workstatio
aphics. Provision is made via a single level
custom mask to implement customer specific frequencysets.
Phase-locked loop circuitry permits rapid glitch-free transitions between clock frequencies. The ICS1561 provides
positive ECL outputs compatible with RAMDACTM clock
and clock* inputs. TTL compatible clocks at 1, 112, 114, and
1/8 the primary clock frequency facilitate the interfacing of
video DRAM to the system.

I

20 FS2

FSO 2
STROBE 3

19 FS3
18 FS4

VDD 4
XTALI 5
XTAL2 6

17 AVSS

FOUT 7

14 FDIV2

VSS 8
RESERVED

9

16 FDIV8
15 FDIV4
13

CLK

12 CLKN

AVDD ,-,10.=0_..=.1,,-,1 VDDO

Top View
Ordering Information
ICS1561NXXX (DIP Package)
ICS1561MXXX (SO Package)
(XXX ~ Pattern number)

549

550

•

ICS1561 A

Integrated
Circuit
Systems, Inc.

Product Preview

Differential Output Video Dot Clock Generator

Description

Features

The ICS1561A is a very high performance monolithic PLL
frequency synthesizer. Utilizing ICS' advanced CMOS
mixed mode technology, the ICS1561A provides a low cost
solution for high-end video clock generation.

•
•
•

The ICS1561A has differential video clock outputs (CLK
and CLK*) that are compatible with industry standard video
DACs & RAMDACSTM. Additional clock outputs, FDIV2,
FDIV4 and FDIV8, provide frequencies which are 112, 114
and 118 the main clock frequency.

•
•
•
•
•

Operating frequencies are selectable from a pre programmed (customer defined) table. An on-chip crystal oscillator for generating the reference frequency is provided
on the ICS1561A.

High Frequency operation for extended video modes up to 230MHz
Compatible with Brooktree high performance RAMDACs
Low Cost - Eliminates need for multiple ECL crystal
clock oscillators in video display subsystems
Advanced PLL for low phase-jitter
Dynamic control ofVCO sensitivity provides optimized
loop gain over entire frequency range
Strobedrrransparent frequency select options
Small footprint - 20 pin DIP or SO packages available
Fully backward compatible to ICS1561

Block Diagram
ICS1561A Simplified Block Diagram
XTAl1
XTAL2

ROM

ClK+
ClK-

ICS1561A Pinout
FSI

F52

FSO

FS3

19

STROBE

FSoI

18

veD

AVSS

17

XTALI

FDN8

I"

XTAL2

FOIV4

15

Four

FDM

1.

VSS
10

20

ClK

13

RESERVED

ClKN

12

AveD

veDO

11

Ordering Information
ICS1561ANXXX (DIP Package)
ICS1561AMXXX (SO Package)
(XXX = Pattern Number)

RAMDAC

551

IS

a trademark of Brooktree Corporation

ICS1561A
Pin Descriptions
PIN NUMBER

PIN NAME

1

FSI

2

FSO

3

STROBE

4

VDD

TYPE

DESCRIPTION
Frequency select input, TTL compatible
Frequency select input, TTL compatible (LSB)
Negative edge clock for select inputs, TTL compatible
5V power pin

5

XTALl

6

XTAL2

Crystal interface

7

FOUT

Clock output, TTL compatible

8

VSS

9

Phase out

Crystal interface/Ext. oscillator input

Digital ground
Phase comparator output

10

AVDD

Analog VDD input

11

VDDO

Output stage VDD supply pin

12

CLOCKN

13

CLOCK

14

FDIV2

Clock/2 output, TTL compatible

15

FDIV4

Clock/4 output, TTL compatible

16

FDIV8

Clock/8 output, TTL compatible

17

AVSS

18

FS4

Frequency select input, TTL compatible

19

FS3

Frequency select input, TTL compatible

20

FS2

Frequency select input, TTL compatible

Complementary clock output, positive ECL
Clock output, positive ECL

Analog ground

552

ICS1561A
Absolute Maximum Ratings
Supply voltage ..............
Ambient operating temp .....
Storage temperature ........
Input Voltage ..............
Output Voltage .............
Clamp Diode Current .......
Output Current per Pin ......
Power Dissipation ..........

VDD ............
To ..............
Ts ..............
VIN .............
VOUT ...........
VIK & 10K .......
lOUT ............
PD ..............

-O.SV to + 7V
O"C to 70"C
-8S"C to + ISO"C
-O.SV to VDD+ O.5V
-O.SV to VDD+ O.SV
± 30mA

± SOmA
SOOmW

Values beyond these ratings may damage the device. This deVice contains circuitry to protect the mputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that Yin and
Vout be constrained to > = Vss and < = VDD.

DC Characteristics
(Power Supply Voltage 4.75-5.25 Volts)
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

Input Low Voltage

VIL

VDD= SV

Vss

0.8

V

VDD= SV

2.0

VDD

V
IlA
V

Input High Voltage

VIH

TYP

Input Leakage Current

hH

VIN= VDD

-

10

Output Low Voltage

VOL

IOL= 8.OmA

-

0.4

Output High Voltage

VOH

IOH= 4.OmA

2.4

-

V

Supply Current

VDD= SV

-

30

rnA

Internal Pull-up Current

IDD
Rup

VDD= SV

25

100

Input Pin Capacitance

CIN

Fe= IMHz

-

8

IlA
pF

Output Pin Capacitance

COUT

Fe= IMHz

-

12

pF

553

II

ICS1561 A
Circuit Description

Frequency Synthesizer Description

Overview

The reference frequency is generated by an on-chip crystal
oscillator, or the reference frequency may be applied to the
ICS1561A from an external frequency source.

The ICS1561A is designed to provide the graphics system
clock signals required by industry standard RAMDACs.
One of 32 pre-programmed (user definable) frequencies
may be selected under digital control. Fully programmable
feedback and reference divider capability allow virtually any
frequency to be generated, not just simple multiples of the
reference frequency. The ICS1561A uses the latest generation offrequency synthesis techniques developed by ICS and
is completely suitable for the most demanding video applications.

The ICS1561Agenerates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed loop feedback system that drives the output frequency to be ratiometrically related to the reference frequencyprovided to the PLL. The phase-frequency detector
shown in the block diagram drives the VCO to a frequency
that will cause the two inputs to the phase frequencydetector
to be matched in frequency and phase. This occurs when:
F

Digital Inputs

Transparent Mode - When the STROBE pin is held HIGH,
the FSO through FS4 inputs are transparent; that is, they
directly access the ROM table. The synthesizer will output
the frequency programmed into the location addressed by
the FSO-FS4 pins.
Latched Mode - When the STROBE pin is held LOW, the
FSO-FS4 pins are ignored. The synthesizer will output the
frequency corresponding to the state of the FSO-FS4 pins
when the STROBE pin was last HIGH. In the event that the
ICS1561Ais powered up with the STROBE pin held LOW,
the synthesizer will output the frequency programmed into
address 0 (i.e., the one selected with FSO through FS4 at a
logic LOW level).

Divided Dot clock Outputs

_ F(XTALl)*Feedback Divider
Reference Divider

(VCO)-

The FSO-FS4 pins and the STROBE pin are used to select
the desired operating frequency from the 32 pre-programmed frequencies in the ROM table of the ICS1561A.
The FSO-FS4 and STROBE pins are each equipped with a
pull-up and will be at a logic HIGH level when not connected.

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).
The divider programming is one of the functions performed
by the ROM lookup table in the ICS1561A. The VCO gain
is also ROM programmable which permits the ICS1561A to
be optimized for best performance at each frequency in the
table.
The feedback divider makes use of a dual modulus prescaler
techniq ue that allows construction of a programmable
counter to operate at high speeds while still allowing the
feedback divider to be programmed in steps of I. This is an
improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or
larger) in this respect.
A post divider may be inserted between the VCO and the
CLK and CLK* outputs of the ICS1561A. This is useful in
generation oflower frequencies, as the VCO has been optimized for high frequency operation. Different post divider
settings may be used for each frequency in the table.

The ICS1561A has additional outputs which provide a 12, /4
and /8 of the main frequency.

Output Stage Description
The CLK and CLK* outputs are each connected to the
drains ofP-Channel MOSFET devices. The source of each
of these devices is connected to VD DO. Typical on resistance of each device is 15 Ohms. These outputs will drive
the clock and clock* of a RAMDAC device when a resistive
network is utilized.
The divided outputs are high current CMOS type drives.

554

II

ICS1561A
Bus Clock Interface

Application Information
Power Supplies
The ICS1561A has a VDDO pin which is the supply of + 5
volt power to all output stages. This pin should be connected
to the power plane (or bus) using standard high frequency
decoupling practice. This decoupling consists of a low series
inductance bypass capacitor, using the shortest leads possible, mounted close to the ICS1561A.
The AVDD pin is the power supply for the synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application
circuitry). This will allow the PLL to "track" through power
supply fluctuations without visible effects.

In some applications, it may be desirable to utilize the bus
clock. To do this, connect the clock through a .047uF capacitor to XTALI (5) and keep the lead length of the capacitor
to XTALI (5) to a minimum to reduce noise susceptibility.
This input is internally biased at VDD/2. Since TTL compatible clocks typically exhibit a VOH of 3.5V, capacitively
coupling the input restores noise immunity. The ICS1561A
is not sensitive to the duty cycle of the bus clock; however,
the quality of this signal varies considerably with different
motherboard designs. As the quality of the bus clock is
typically outside the control of the graphics adapter card
manufacturer, it is suggested that this signal be buffered on
the graphics adapter board. XTAL2 (6) must be left open
in this configuration.
ICS1561A Interface

Crystal Oscillator and Crystal Selection

The ICS1561A has circuitry onboard to implement a Pierce
oscillator with the addition of only one external component,
a quartz crystal. Pierce oscillators operate the crystal in anti
(also called parallel) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.

The ICS1561A should be located as close as possible to the
video DAC or RAMDAC. The differential output CLOCK
drivers are current sourcing only and are designed to drive
resistive terminations in a complementary fashion. CLK and
CLK* connections should follow good ECL interconnection
practice. Terminating resistors should be as close as possible
to the RAMDAC.

So-called series resonant crystals may also be used with the
ICS1561A. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically 0.0050.01 %).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
Avoid routing digital signals or the ICS 1561A outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.

555

ICS1561 A
ICS1561 A Standard Patterns
ICS produces standard frequency patterns for the ICS1561A. These patterns include the majority of frequencies most
customers require. Custom patterns are also available, although a significant volume commitment and/or one-time mask
charge will apply. Contact ICS sales for details.

r--

ICS Part
Number
Video Clock
Address
(HEX)

ICSI561
-706
Frequency
(MHz)

ICS1561707
Frequency
(MHz)

ICS1561Custom Pattern 1
Frequency
(MHz)

ICS1561Custom Pattern 2
Frequency
(MHz)

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
lA
IB
lC
1D
IE
IF
Reference
Frequency

12.273
14.500
15.667
25.175
28.000
30.240
31.500
38.400
43.200
50.400
50.675
51.270
55.000
57.283
63.000
64.000
68.750
75.000
88.500
99.422
99.522
100.000
112.000
126.000
140.000
160.000
180.000
200.000
217.000
60.000
250.000
7.875
14.31818
MHz

25.175
28.322
32.500
36.000
37.500
40.000
44.900
57.000
64.000
65.000
72.000
74.160
76.000
80.000
84.000
98.000
100.000
107.000
108.000
110.000
112.000
130.000
135.000
140.000
160.000
170.000
180.000
200.000
126.500
128.000
132.000
136.710
14.31818
MHz

MHz

MHz

Note: All frequencIes above 180MHz III the standard patterns shown above are expenmental and are not guaranteed.

Order info: ICSI561M-XXX or ICSI561N-XXX (M

=

SO pkg., N

556

=

DIP pkg., XXX

=

Pattern number)

ICS1562

Integrated
Circuit
Systems, Inc.

User Programmable Differential Output Graphics Clock Generator
Description

Features

The ICS1562 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing rcs'
advanced CMOS mixed-mode technology, the ICS1562
provides a low cost solution for high-end video clock generation.

•

The ICS1562 has differential video clock outputs (CLK+
and CLK-) that are compatible with industry standard video
DAC. Another clock output, LOAD, is provided whose
frequency is derived from the main clock bya programmable
divider. An additional clock output is available, LDIN2,
which is derived from the LOAD frequency and whose
modulus may also be programmed.

•

•

•

•
•

Operating frequencies are fully programmable with direct
control provided for reference divider, pre-scaler, feedback
divider and post-scaler.
Reset of the pipeline delay on Brooktree RAMDACsTM may
be performed under register control. Outputs may also be
set to desired states to facilitate circuit board testing.

•
•
•

Two programming options:
ICS1562-001 (Parallel Programming)
ICS1562-201 (Serial Programming)
Supports high-resolution graphics - CLK output to
230MHz
Eliminates need for multiple ECL output crystal oscillators
Fully programmable synthesizer capability - not just a
clock multiplier
Circuitry included for reset of Brooktree RAMDACTM
pipeline delay
VRAM shift clock generation capability
(-201 option only)
Line-locked clock generation capability
External feedback loop capability (-201 option only)
Compact - 16-pin 0.150" skinny sorc package

Simplified Block Diagram - ICS1562
ICS1562 - 001 Pinout
XTAL1
XTAl2

EXTFBK}
BLANK

(·201 only)

----7
FEEDBACK DIVIDER
PROGRAMMING
INTERFACE

CLK+
CLK-

LOAD

DRIVER

~

LD/N2

ADO

AD1

16

XTAL1

AD2

15

XTAl2

AD3

14

STROBE

VDD

13

vss
vss

VDDO

12

IPRG

11

LOAD

CLK+

10

LD/N2

CLK-

ICS1562 - 201 Pinout
EXTFBK

DATA

16

XTAL1

HOLD

15

XTAl2

BLANK

14

DATCLK

VDD

13

vss
vss

VDDO

12

IPRG

11

LOAD

CLK+

10

LD/N2

CLK-

Ordering Information
rCSI562M-XXX
(16 pin SOIC package)

Figure 1

(XXX= Pattern number)

557

II

ICS1562

Table I permits the derivator of "A" & 'M" converter programming directly from desired modulus.

Overview
The ICS1562 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just
simple multiples of the reference frequency. The ICS1562
uses the latest generation of frequency synthesis techniques
developed by ICS and is completely suitable for the most
demanding video applications.

PLL Post-Scaler
A programmable post-scaler may be inserted between the
YCO and the CLK+ and CLK- outputs of the ICS1562.
This is useful in generatingoflower frequencies, as the YCO
has been optimized for high-frequency operation.
The post-scaler allows the selection of:

PLL Synthesizer Description - Ratiometric Mode

•
•
•
•

The ICS1562 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequencyprovided to the PLL (see Figure I). The reference
frequency is generated by an on-chip crystal oscillator or the
reference frequency may be applied to the ICS1562 from an
external frequency source.

YCO frequency
YCO frequency divided by 2
YCO frequency divided by 4
Internal register bit (AUXCLK) value

Load Clock Divider

The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or YCO, to a frequency that will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:

The ICS1562 has an additional programmable divider (referred to in Figure I as the NI divider) that is used to
generate the LOAD clock frequency for the video DAC.
The modulus ofthis divider maybe set to 3, 4, 5, 6, 8, or 10
under register control. The design of this divider permits the
output duty factor to be 50/50, even when an odd modulus
is selected. The input frequency to this divider is the output
of the PLL post-scaler described above.

F(vco : = F(XTALl) . Feed~a~k Divider
)
Reference DIvider

Digital Inputs - ICS1562-001 Option

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).

The YCO gain is programmable, which permits the ICS1562
to be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from I to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 448 in steps of one. Anyeven modulus from
448 through 896 can also be achieved by setting the "double"
bit which doubles the feedback divider modulus. The feedback divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at
low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that
typically impose a factor-of-four penalty (or larger) in this
respect.

The ADO-AD3 pins and the STROBE pin are used to load
all control registers of the ICS1562 (-001 option). The ADOAD3 and STROBE pins are each equipped with a pull-up
and will be at a logic HIGH level when not connected. They
maybe driven with standard TTL or CMOS logic families.
The address ofthe register to be loaded is latched from the
ADO-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from the ADO-AD3 pins by
a positive edge on the STROBE pin. See Figure 2 for a
timing diagram. After power-up, the ICS1562-00l requires
32 register writes for new programming to become effective.
Since only 13 registers are used at present, the programming
system can perform 19 "dummy" writes to address 13 or 14
to complete the sequence.

558

ICS1562
An additional control pin on the ICS1562-201, BLANK can
perform either of two functions. It may be used to disable
the phase-frequency detector in line-locked applications.
Alternatively, the BLANK pin may be used as a synchronous
enable for VRAM shift clock generation. See sections on
Line-Locked Operations and VRAM shift clock generation
for details.

This allows the synthesizer to be completely programmed
for the desired frequency before it is made active. Once the
part has been "unlocked" by the 32 writes, programming
becomes effective immediately.
ALL registers identified in the data sheet (0-9, II, 12 & 15)
MU ST be written upon initial programming. The programming registers are not initialized upon power-up, but the
latched outputs of those registers are. The latch is made
transparent after 32 register writes. If any register has not
been written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist.
Register 10 does exist, but is reserved for future expansion.
To insure compatibility with possible future modifications to
the database, ICS recommends that all three unused locations be written with zero.

Output Description
The differential output drivers, CLK+ and CLK, are current-mode and are designed to drive resistive terminations
in a complementary fashion. The outputs are current-sinking only, with the amount of sink current programmable via
the IPRG pin. The sink current, which is steered to either
CLK+ or CLK-, is four times the current supplied to the
IPRG pin. For most applications, a resistor from VDDO to
IPRG will set the current to the necessary precision.

ICS1562-001 Register Loading

STROBE

ADO·AD3

~
~

1

=r:= =t5

ADDRESS VALID

~

'0

The LOAD output is a high-current CMOS type drive whose
frequency is controlled bya programmable divider that may
be selected for a modulus of 3,4, 5, 6, 8, or 10. It may also
be suppressed under register control.

3

DATA VALID

L

The LDIN2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programmable modulus may range from 1 to 512 in steps of one.

Figure 2
Digital Inputs - ICS1562-201 Option

Pipeline Delay Reset Function

The programming of the ICS1562-201 is performed serially
byusing the DATCLK, DATA, and HOLD- pins to load an
internal shift register.

The ICS1562 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACsTM. This
sequence can be generated by setting the appropriate register bit (DACRST) to a logic I and then resetting to logic O.

DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD- pin is latched
at the same time. When HOLD- is low, the shift register
may be loaded without disturbing the operation of the
ICS1562. When high, the shift register outputs are transferred to the control registers, and the new programming
information becomes active. Ordinarily, a high level should
be placed on the HOLD- pin when the last data bit is
presented. See Figure 3 for the programming sequence.

When changing frequencies, it is advisable to allow 500
microseconds after the new frequency is selected to activate
the reset function. The output frequency of the synthesizer
should be stable enough at that point for the video DAC to
correctly execute its reset sequence. See Figure 4 for a
diagram of the pipeline delay reset sequence.
Pipeline Delay Reset Timing

ICS1562-201 Register Loading

STROBE
or

DATCLK
CLK+

LOAD

Figure 4
559

I

II

ICS1562
Reference Oscillator and Crystal
Selection
The ICS1562 has circuitry on~board to implement a Pierce
oscillator with the addition of only one external component,
a quartz crystal. Pierce oscillators operate the crystal in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to specify
when ordering crystals.
Series-resonant crystals may also be used with the ICS1562.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically
0.025-0.05% ).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
Avoid routing digital signals or the ICS1562 outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.

ICS1562-OOl

The ICSl562-001 supports phase detector
disable via a special control mode. When the
PDRSTEN (phase detector reset enable)
bit is set and the last address latched is 15
(OFh), a high level on AD3 will disable PLL
locking.

ICS1562-201

The ICS1562-201 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disable PLL locking.

External Feedback Operation
The ICS1562-201 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This
mode is useful in graphic systems that must be "genlocked"
to external video sources.

If an external reference frequency source is to be used with

When the EXTFBEN bit is set to logic 1, the phase-frequency detector will use the EXTFBK pin as its feedback
input. The loop phase will be locked to the rising edges of
the signal applied to the EXTFBK input.

the ICSl562, it is important that it be jitter-free. The rising
and falling edges of that signal should be fast and free of
noise for best results.

VRAM Shift Clock Generation

The loop phase is locked to the falling edges of the XTAL 1
input signals.

Line-Locked Operation
The ICS1562 supports line-locked clock applications by
allowing the LOAD (N 1) and N2 divider chains to act as the
feedback divider for the PLL.
The Nl and N2 divider chains allow a much larger modulus
to be achieved than the PLVs own feedback divider. Additionally, the output of the N2 counter is accessible off-chip
for performing horizontal reset of the graphics system,
where necessary. This mode is set under register control
(ALTLOOP bit). The reference divider (R counter) will
ordinarily be set to divide by 1 in this mode, and the HSYNC
signal of the external video will be supplied to the XTALl
input. The output frequency of the synthesizer will then be:

The ICS1562-201 option supports VRAM shift clock generation and interruption. By programming the N2 counter
to divide by 1, the LDIN2 output becomes a duplicate of the
LOAD output. When the SCEN bit is set, the LDIN2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LDIN2 will be free-running and
in phase with LOAD. When BLANK is taken low, the
LDIN2 output is stopped at a low level. See Figure 5 for a
diagram of the sequence. Note that this use ofthe BLANK
pin precludes its use for phase comparator disable (see
Line-Locked Operation).

VRAM Shift Clock Control

BLANK

\\'\»\\\'t"\\\

~

/I/II/I!!I!!I/

~~
~

F(CLK) : = F (XTALl) . Nl . N2.

FigureS

By using the phase-detector hardware disable mode, the
PLL can be made to free-run at the beginning of the vertiCal
interval of the external video, and can be reactivated at its
completion.

560

;-

ICS1562
•

Power-On Initialization
The ICS1562 has an internal power-on reset circuit that
performs the following functions:
I)

Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.

2)

Selects the modulus ofthe NI divider (for the
LOAD clock) to be four.

Phase Detector Gain: For most graphics applications
and divider ranges, set P[I,O] = 10 and set P[2] = 1.
Under some circumstances, setting the P[2] bit "on" can
reduce jitter. During 1562 operation at exact multiples
of the crystal frequency, P[2] bit = 0 may provide the
best jitter performance.

Board Test Support

These functions should allow initialization of most graphics
systems that cannot immediately provide for register programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD supply
reaches 4 volts.

It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1562 supports this
through a register programmable mode, AUXEN. When
this mode is set, two register bits directly control the logic
levels of the CLK+ /CLK- pins and the LOAD pin. This
mode is activated when the S[O] and S[1] bits are both set to
logic 1. See Register Mapping for details.

Power Supplies and Oecoupling
Programming Notes
•

•

•

VCO Frequency Range: Use the post-divider to keep
the VCO frequency as high as possible within its operating range.
Divider Range: For best results in normal situations
(i.e, pixel clock generation for hi-res displays), keep the
reference divider modulus as short as possible (for a
frequency at the output of the reference divider in the
few hundred kHz to several MHz range). If you need
to go to a lower phase comparator reference frequency
(usually required for increased frequency accuracy),
that is acceptable, but jitter performance will suffer
somewhat.
VCO Gain Programming: Use the minimum gain
which can reliably achieve the VCO frequency desired,
as shown here:
VCO GAIN
4

5
6
7

MAX FREQUENCY
120 MHz
200 MHz
230 MHz

The ICS1562 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as
close to the package as is possible.
The ICS1562 has a VDDO pin which is the supply of + 5
volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have
low series inductance and be mounted close to the ICS1562.
The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We
recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to ''track'' through
power supply fluctuations without visible effects. See Figure 6 for typical external circuitry.
ICS1562
DIFFERENTIAL CLOCK QUTPU- SINK CURRENT

*
510

'SPECIAL APPLICATION. Contact factory for custom product above
230 MHz.

15
1O~1hc==~~~~~~~~4

;

.

__~~--~

1
15
2
2.5
Clr..+!CU<'- OJ-pur VOLTAGE (

Figure 6

561

~

15K

o~~~~----~

005

680

3.5
)

ICS1562
a)

ICS1562-001 Typicallnlerface

o 1/-tF
1

rD~
4
5

SELECT LOGIC

-=i=-

L-.f,----;;---1L

ADO
XTAL1
XTAL2
STROBE
VSS

VSS

AD1
AD2
AD3
VDD
VDDO
IPRG

LOAD
LD/N2

C~-

C~+

II

r--lt--

Tr

~
14
13
12
11

P=n

::L
~

+ 5V

22!lF

I
+ 5V
10

~01/-tF

9

I

J

~

}

+ 5V
510
01!lF

82

82

820

820

TO
RAMDAC

,-

-~

I

+

~

b)
ICS1562-201 Typicallnlerface

GRAPHICS
CONTROLLER

{

-

PROGRAMMING {
INTERFACE

-

1

EXTFBK

rD~~~~
4
5

DATCLK

VSS

-=i=- ~ VSS
LOAD

~ LD/N2

DATA

J

o 1!lF

lit

VDD
VDDO
IPRG

C~+

C~-

+ 5V

Tr

~~~Kr--it13
12
11

P=n

10

~01!lF

9

I
+ 5V

<

82

82

I

~

}

I
+ 5V
510

820

820

01!lF -~

I

~

Figure 7

562

-=i=-

-

TO
RAMDAC

ICS1562
Register Mapping - ICS1562-001 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562. PC SOFTWARE IS A V AILABLE FROM ICS TO AUTOMA TICALL Y GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY
FOR DETAILS.

REG#

BIT(S)

0
1

0-3
0-2

R[0] .. R[3]
R[4]..R[6]

Reference divider modulus control bits
Modulus = value + 1

2

0-3

A[0] .. A[3]

Controls A counter. When set to zero, modulus= 7. Otherwise,
modulus= 7 for "value"underflows of the prescaler, and modulus= 6
thereafter until M counter underflows.

3
4

0-3
0-1

M [O]..M [3]
M [4]..M [5]

M counter control bits
Modulus = value + 1

4

3

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 617 to 12114).

5

0-2

N1[0] .. N1[2]

Sets N1 modulus according to this table. These bits are set to implement a divide-by-four on power-up.

DESCRIPTION

BIT REF.

N1[2]
0
0
0
0
1
1
1
1
6
7

0-3
0-2

N2[0] .. N2[3]
N2[4] .. N2[7]

8

3

N2[8]

8

0-2

V[O] .. V[l]

N1[1]
0
0
1
1
0
0
1
1

N1[0]
0
1
0
1
0
1
0
1

RATIO
3
4
4
5
6
8
8
10

Sets the modulus of the N2 divider.
The input ofthe N2 divider is the output ofthe N1 divider in all clock
modes except AUXEN.

Sets the gain ofthe VCO.
V[2]

V[l]

V [0]

I
1
1
I

0
0
1
1

0
1
0
1

563

VCOGAIN
(MHz/VOLT)
30
45
60
80

ICS1562
REG#
9

BIT REF.
0-1

DESCRIPTION

P[O] .. P[1]

Sets the gain ofthe phase detector according to this table.
P[1]
0
0
1
1

prO]
0
1
0
1

GAIN (uA/radian)
0.05
0.15
0.5
1.5

9

3

[P21

Phase detector tuning bit. Normally should be set to one.

11

0-1

S[O] .. S[I]

PLL post -scaler/test mode select bits

-

S[1] S[O]
DESCRIPTION
0
0 Post-scaler= I. F(CLK)= F(PLL). The output ofthe Nl divider
r----- d!ives the LOAD outQut which, in turn, drives the N2 divider.
1 Post-scaler= 2. F(CLK)= F(PLL)I2. The output of the Nl
0
divider drives the LOAD output which, in turn, drives the N2
divider.
1
0 Post-scaler= 4. F(CLK)= F(PLL)/4. The output of the Nl
divider drives the LOAD output which, in turn, drives the N2
divider.
1
1 AUXEN CLOCK MODE. The AUXCLK bit drives the
differential outputs CLK+ and CLK- and the AUXNl bit drives
the LOAD output which, in turn, drives the N2 divider.

11

2

AUX_CLK

When in the AUXEN clock mode, this bit controls the differential
outputs.

11

3

AUX_Nl

When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).

12

0

RESERVED

Must be set to zero.

JAMPLL

Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.

12
12

2

DACRST

Set to zero for normal operation. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+ /- 1 CLK period).
To initiate a RAMDACTM reset sequence, simply write a one to
this register bit followed by a zero.

12

3

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

15

0

ALTLOOP

Controls substitution of N I and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N 1 and N2 dividers are used.

15

3

PDRSTEN

Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See LINE-LOCKED CLOCK GENERATION section for more
details on the operation ofthis function.

564

II

ICS1562

Register Mapping - ICS1562-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICSl562 PC SOFTWARE IS A V AILABLE FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS CONTACT FACTORY
FOR DETAILS

BIT REF.
1-3

N1[O]..N1[2]

DESCRIPTION
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
NI[2]

NI[I]

NI[O]

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

RATIO

3
4
4

5
6
8
8
10

4

RESERVED

Set to zero.

5

RESERVED

MUST be set to zero. If this bit is ever programmed for a logic one, device
operation will cease and further serial data load into the registers will be
inhibited until a power-offlpower-on sequence.

6

JAMPLL

Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.

7

DACRST

Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge ofthe LD output (+ /- 1 CLK period).
To initiate a RAMDACTM reset sequence, simply write a one to this register
bit followed by a zero.

8

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

9

ALTLOOP

Controls substitution ofNl and N2 dividers into feedback loop ofPLL.
When this bit is a logic 1, the N1 and N2 dividers are used.

10

SCEN

VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LDIN2 output.

11

EXTFBKEN

External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.

12

PDRSTEN

Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.

565

II

ICS1562
DESCRIPTION

BIT REF.
13-14

S[O] .. S[I]

PLL post-scaler/test mode select bits.
S[I] S[O]
DESCRIPTION
0
0 Post-scaler= 1. F(CLK)= F(PLL). The output of the NI divider
drives the LOAD output which, in turn drives the N2 divider.
1 Post -scaler= 2. F(CLK)= F(PLL)/2. The output of the NI
0
divider drives the LOAD output which, in turn, drives the N2
divider.
0 Post-scaler= 4. F(CLK)= F(PLL)/4. The output of the NI
1
divder drives the LOAD output which, in turn, drives the N2
divider.
1
1 AUXEN CLOCK MODE. The AUXCLK bit drives the
differential outputs CLK+ and CLK- and the AUXNl bit drives
the LOAD output which, in turn, drives the N2 divider.

15

When in the AUXEN clock mode, this bit controls the differential outputs.

16

When in the AUXEN clock mode, this bit controls the Nl output (and
consequently the N2 output according to its programming).

17-24
28

N2[O] ..N2[7]
N2[8]

25-27

V[O] .. V[2]

29-30

P[O] .. P[I]

}

Sets the modulus of the N2 divider. The input of the N2 divider is the
output ofthe Nl divider in all clock modes except AUXEN.
Sets the gain ofVCO.
V[2]

V[I]

V[O]

I
1
1
1

0
0
1

0
1
0
1

I

VCOGAIN
(MHz/VOLT)
30
45
60
80

Sets the gain of the phase detector according to this table.
P[I]
0
0
1
1

P[O]
0
1
0
1

GAIN (uA/radian)
0.05
0.15
0.5
1.5

31

RESERVED

Set to zero.

32

P[2]

Phase detector tuning bit. Should normally be set to one.

S66

II

ICS1562

BIT(S)

BIT REF.

33-38

M[0) .. M[5)

M counter control bits
Modulus = value + I

39

RESERVED

Set to zero.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 617 to 12114).

41-44

A[0) .. A[3)

Controls A counter. When set to zero, modulus= 7. Otherwise,
modulus= 7 for "value" underflows of the prescaler, and modulus= 6
thereafter until M counter underflows.

45-48

RESERVED

Set to zero.

49-55

R[0) .. R[6)

Reference divider modulus control bits
Modulus = value + I

56

RESERVED

Set to zero.

DESCRIPTION

567

ICS1562
Table 1 - ''A'' & 'M" Divider Programming
Feedback Divider Modulus Table
A[21 ..A[01M[51 ..M[OI

001

010

011

100

101

110

111

000

55
61
67
73
79
85
91
97
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193
199

7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
126
1"33
140
147
154
161
168
175
182
189
196
203
210
217
224

()()()()()()

000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111

13
19
25
31
37
43
49
55
61
67
73
79
85
91
97
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193

20
26
32
38
44
50
56
62
68
74
80
86
92
98
104
110
116
122
128
134
140
146
152
158
164
170
176
182
188
194

27
33
39
45
51
57
63
69
75
81
87
93
99
105
III

117
123
129
135
141
147
153
159
165
171
177
183
189
195

34
40
46
52
58
64
70
76
82
88
94
100
106
112
118
124
130
136
142
148
154
160
166
172
178
184
190
196

41
47
53
59
65
71
77
83
89
95
101
107
113
119
125
131
137
143
149
155
161
167
173
179
185
191
197

48
54
60
66
72
78
84
90
96
102
108
114
120
126
132
138
144
150
156
162
168
174
180
186
192
198

A[21-.A(01M[51 ..M[01
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
lllOOI

111010
111011
111100
111101
111110
111111

001

010

011

100

101

110

111

000

199
205
211
217
223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385

200

206
212
218
224
230
236
242
248
254
260
266
272
278
284
290
296
302
308
314
320
326
332
338
344
350
356
362
368
374
380
386

201
207
213
219
225
231
237
243
249
255
261
267
273
279
285
291
297
303
309
315
321
327
333
339
345
351
357
363
369
375
381
387

202
208
214
220
226
232
238

203
209
215
221
227
233
239
245
251
257
263
269
275
281
287
293
299
305
311
317
323
329
335
341
347
353
359
365
371
377
383
389

204
210
216
222
228
234
240
246
252
258
264
270
276
282
288
294
300
306
312
318
324
330
336
342
348
354
360
366
372
378
384
390

205
211
217
223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385
391

231
238
245
252
259
266
273
280
287
294
301
308
315
322
329
336
343
350
357
364
371
378
385
392
399

244

250
256
262
268
274
280
286
292
298
304
310
316
322
328
334
340
346
352
358
364
370
376
382
388

406

413
420
427
434
441
448

Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to fmd the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is:

N = [(M + I) ·6] + A

except when A= 0, then:

N= (M + 1)·7

Under all circumstances:

A '5. M

S68

ICS1562
Pin Descriptions - ICS1562-001
PIN#

NAME

10
9
7
2
3

CLK+
CLK-

16
IS
14
8
4
13
12
11
S,6

LOAD
XTALl
XTAL2
ADO
ADI
AD2
AD3
LD/N2
STROBE
VDD
VDDO
IPRG
VSS

DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by N 1.
Quartz crystal connection I/external reference frequency input
Quartz crystal connection 2
Address/Data Bit 0 (LSB)
Address/Data Bit I
Address/Data Bit 2
Address/Data Bit 3 (MSB)
Divided LOAD output. See text.
Control for address/data latch
PLL system power (+ SY. See application diagram.)
Output stage power (+ SV)
Output stage current set
Device ground. Both pins must be connected to the same ground potential.

Pin Descriptions - ICS1562-002
PIN#

NAME

10
9
7
2
3
4
16
IS
14
8

CLK+
CLK-

13
12
11
S,6

LOAD
XTALl
XTAL2
DATCLK
DATA
HOLDBLANK
LD/N2
EXTFBK
VDD
VDDO
IPRG
VSS

DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by N1.
Quartz crystal connection lIexternal reference freq uency input
Quartz crystal connection 2
Data Clock (Input)
Serial Register Data (Input)
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input). See text.
PLL system power (+ SY. See application diagram.)
Output stage power (+ SV)
Output stage current set
Device ground. Both pins must be connected.

569

(I

ICS1562
Absolute Maximum Ratings
VDD, VDDO (measured to Vss) ......................
Digital Inputs .......................................
DigitalOutputs .....................................
Ambient Operating Temperature ......................
Storage Temperature ................................
Junction Temperature ................................
Soldering Temperature ...............................

7.0 V
V ss-0.5 to VDD + 0.5 V
V ss-0.5 to VDDO + + 0.5 V
-55 to 125 :C
-65 to 150 C
175°C
260 °c

Recommended Operating Conditions
VDD, VDDO (measured to Vss) ...................... 4.75 to 5.25 V
Operating Temperature (Ambient) .................... 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
001 Option - (ADO-AD3, STRO~
201 Option - (DATCLK, DATA, HOLD, BLANK, EXTFBK)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance

SYMBOL
Vlh
VII
Iih
IIi
Cm

CONDITIONS

Vih= VDD
VIi= 0.0

MIN
2.0

MAX
VDD+ 0.5
0.8
10
200
8

UNITS
V
V
uA
uA
pF

MIN

MAX

3.75
Vss-0.5

VDD+ 0.5
1.25

UNITS
V

MIN
2.4
-

MAX

UNITS

-

V
V

Vss-0.5
-

XTAL11nput
PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL

CONDITIONS

Vxh
Vx\

CLK+ , CLK- Outputs
PARAMETER
DifferentialOut ut Voltage

CONDITIONS

LOAD, LD/N2 Outputs
PARAMETER
Output High Voltage (Ioh = 4.OmA)
Output Low Voltage (101 = 8.OmA)

SYMBOL

CONDITIONS

570

0.4

ICS1562
AC Characteristics
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Fvco

VCO Frequency (see Note I)

20

230

MHz

Fxtal
Cpar

Crystal Freq uency
Crystal Oscillator Loading Capacitance

5

20

MHz
pF

Fload

LOAD Frequency

80

MHz

Txhl

XTALl High Time (when driven externally)

8

ns

T xlo

XTAL I Low Time (when driven externally)

8

ns

Tlock

PLL Acquire Time (to within 1%)
VDD Supply Current

500
15

t.b.d.

I1s
rnA

VDDO Supply Current (excluding CLK+ ftermination)
DIGITAL INPUTS - ICSI562-001

20

t.b.d.

rnA

Idd
Iddo

20

I

Address Setup Time

2

Address Hold Time

10
10

ns
ns

3

Data Setup Time

10

ns

4

Data Hold Time

10

ns

5

STROBE Pulse Width (Thl or Tlo)
20
DIGITAL INPUTS - ICS1562-201

ns

6

DATAfHOLD- Setup Time

10

ns

7

DATAfHOLD- Hold Time

10

ns

8

DATCLK Pulse Width (Thl or Tlo)

20

ns

PIPELINE DELAY RESET
9

Reset Activation Time

10

Reset Duration

2*Tclk
4*Tload

11

Restart Delay

12

Restart Matching

13

CLK+ fCLK- Clock Rate

14

LOAD To LDfN2 Skew (Shift Clock Mode)

ns
ns

-I *Tclk

2*Tload

ns

+ 1.5*Tclk

ns

230

MHz

+ 2

ns

DIGITAL OUTPUTS
-2

0

Note I: Use of the post-divider is required for frequencies lower than 20MHz on CLK+ & CLK- outputs. Use of the
post-divider is recommended for output frequencies lower than 65MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and
eLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the domain) if anyCLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
IeS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification
in virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and
register programming.

571

II

II

ICS1562 Application Information

Output Circuit Considerations for the ICS1562
Output Circuitry
The dot clock signals CLK and CLK- are typically the
highest frequency signals present in the workstation. To
minimize problems with EMI, crosstalk, and capacitive
loading extra care should be taken in laying out this area of
the PC board. The ICS1562 is packaged in a 0.2"-wide 16-pin
SOIC package. This permits the clock generator, crystal,
and related components to be laid out in an area the size of
a postage stamp. The ICS1562 should be placed as close as
possible to the RAMDAC. The CLK and CLK- pins are
running at VHF frequencies; one should minimize the
length of PCB trace cOl;mecting them to the RAMDAC so
that they don't become radiators ofRF energy.

Strip line is the other form a PCB transmission line can take.
A buried trace between ground planes (or between a power
plane and a ground plane) is common in multi-layer boards.
Attempting to create a workstation design without the use
of multi-layer boards would be adventurous to say the least,
the issue would more likely be whether to place the interconnect on the surface or between layers. The between layer
approach would work better from an EMI standpoint, but
would be more difficult to layout. A strip line is shown
below:

At the frequencies that the ICS1562 is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting wires. These lines can take two forms: microstrip
and stripline. A microstrip line is shown below:

DimensIons in Inches

Strlpllne
Using 10z. copper (0.0015" thick) and 0.040"thickness G 10,
a 0.010" trace will exhibit a characteristic impedance of 750
in a strip line configuration.

87

Typically, RAMDACS require a V1h ofVAA-1.0 Volts as a
guaranteed logical "1" and a Vil ofVAA-1.6 as a guaranteed
logical "0". Worst case input capacitance is 10 pF.

(5.98h)

zo=Ver+1.41 In Q.8w+t

Dimensions in inches

Microstrip Line
Essentially, the microstrip is a copper trace on a PCB over
a ground plane. Typically, the dielectric is G 10 glass epoxy.
It differs from a standard PCB trace in that its width is
calculated to have a characteristic impedance. To calculate
the characteristic impedance of a microstrip line one must
know the width and thickness of the trace, and the thickness
and dielectric constant of the dielectric. For G 10 glass epoxy, the dielectric constant (er) is about 5. Propagation delay
is strictly a function of dielectric constant. For G 10 propagation, delay is calculated to be 1.77 ns/ft.

Output circuitry for the ICS1562 is shown in the following
diagram. It consists of a 4/1 current mirror, and two open
drain output FE Ts along with inverting buffers to alternately
enable each current-sinking driver. Both CLK and CLK~
outputs are connected to the respective CLOCK and
CLOCK* inputs of the RAMDAC with transmission lines
and terminated in their equivalent impedances by the
Thevenin equivalent impedances ofRI and R2 or Rl' and R2'.

572

ICS1562 Application Note

The ICSl562 is incapable of sourcing current, so VIh must
be set by the ratios of these resistors for each of these lines.
R 1 and R2 are electrically in parallel from an AC standpoint
because Vdd is bypassed to ground through bypass-capacitor network Cb. If we picked a target impedance of 750 for
our transmission line impedance, a value of9lO for Rl and
Rl' and a value of 4300 for R2 and R2' would yield a
Thevinin equivalent characteristic impedance of75.l Wand
a Vih value ofVAA-.873 Volts, a margin ofO.127Volts. This
maybe adequate; however, at higher frequencies one must
contend with the IOpF input capacitance of the RAMDAC.
Values of 820 for Rl and Rl' and 8200 for R2 and R2'
would give us a characteristic impedance of74.50 and a VIh
value of VAA-.45. With a .55 Volt margin on V.h, this voltage
level might be safer.
To set a value for VII, we must determine a value for Iprg that
will cause the output FET's to sink an appropriate current.
We desire VII to be VAA -l.6 or greater. VAA -2 would seem
to be a safe value. Setting up a sink current of 25 milliamperes would guarantee this through our 820 pull-up resistors. As this is controlled by a 4/1 current mirror, 7 mA into
Iprg should set this current properly. A 5100 resistor from
V dd to Iprg should work fine.
Resistors Rt and Rt' are shown as series terminating resistors at the ICS1562 end of the transmission lines. These are
not required for operation, but may be useful for meeting
EMI requirements. Their intent is to interact with the input
capacitance of the RAMDAC and the distributed capacitance of the transmission line to soften up rise and fall times
and consequently cut some of the high-order harmonic
content that is more likely to radiate RF energy. In actual
usage they would most likely be 10 to 200 resistors or
possibly ferrite beads.

573

Cb is shown as multiple capacitors. Typically, a 22 ~ tantalum should be used with separate.l ~ and 220pF capacitors
placed as close to the pins as possible. This provides low
series inductance capacitors right at the source of high
frequency energy. Rd is used to isolate the circuitry from
external sources of noise. Five to ten ohms should be adequate.

....

c.

-------'"

I

'I'

~

R1

.,.

"

..

v AA
ClockClock

...

RAMDAC

1CS1562

ICS1562 Output Circuitry
Great care must be used when evaluating high frequency
circuits to achieve meaningful results. The 10 pF input capacitance and long ground lead of an ordinary scope probe
will make any measurements made with it meaningless. A
low capacitance FET probe with a ground connection directly connected to the shield at the tip will be required. A
lGHz bandwidth scope will be barely adequate, try to find
a faster unit.

574

ICS1567

Integrated
Circuit
Systems, Inc.

Differential Output Video Dot Clock Generator
Features

Applications

•

•
•
•
•
•

•

•
•
•
•
•
•
•

High frequency operation for extended video modes up to 180MHz
Compatible with Brooktree high performance RAMDACSTM
a) Differential output clocks with ECL logic levels
b) Programmable divider modulus for load clock
c) Circuitry included for automatic reset of Brooktree
RAMDACTM pipeline delay
Low cost - eliminates need for multiple ECL crystal
clock oscillators in video display systems
Strobed/Transparent frequency select options
32-user selected mask-programmable frequencies
Fast acquisition of selected frequencies, strobed or
non-strobed
Advanced PLL for low phase-jitter
Dynamic control of VCO sensitivity providing optimized loop gain over entire frequency range
Small footprint - 16 pin wide body (300 mil) SOIC

Description

Workstations
High-resolution PC and MAC displays
8514A - TMS340XO systems
EGA - VGA - Super VGA video
Telecom reference clock generation - suitable for Sonet,
A TM and other data rates up to 155.52 Mb.

Pin Configuration

The ICS1567 is a very high performance monolithic PLL
frequency synthesizer. Utilizing ICS' advanced CMOS
mixed-mode technology, the ICS1567 provides a low cost
solution for high-end video clock generation, and for telecom system clock generation.
The ICS1567 has differential video clock outputs (CLK and
CLK*) that are compatible with industry standard video
DACs & RAMDACs. An additional clock output, LD*, is
provided, whose frequency is divided down from the main
clock by a programmable divider.
Operating frequencies are selectable from a pre-programmed (customer-defined) table. An on-chip crystal oscillator for generating the reference frequency is provided
on the ICS1567.
Programming of the ICS1567 is accomplished via frequency
select pins on the package. The ICS1567 has five lines plus
a STROBE pin which permits selection of 32 frequencies.
Reset of the pipeline delay on Brooktree RAMDACs is
automatically performed on a rising edge of the STROBE
line.

575

FSO
XTALl

16

FSI

2

15

FS2

XTAL2

3

14

FS3

STROBE

4

13

VDD

VSS

5

12

VDDO

VSS

6

II

VDDO

LD*

7

10

CLK

FS4

8

9

CLK*

Ordering Information
ICSI567MXXX (16 pin SOIC Package)
(XXX= Pattern number)

ICS1567
Block Diagram

Xl
X2

ClK+
ClK-

FSO
FSl
FS2
FS3

lOAD

FS4

STROBE

Figure 1

System Schematic

1

FSO
XTAL

r-1D~
4
5

STROBE

6

Vss

7
8

lOAD
FS4

ICS1567

16
15
14
13
12

FSl
FS2
FS3
A

10

VDD
v

r-1l10
9

-~-~+
- '-

Figure 2

576

VDDD

ClK
ClK"

[I

ICS1567

Typical Output Configuration
+5VoIIs

rD1

r-

110

ICSl567 47
CLK+ .AJ.t..A,

RAMDAC
Oock

160

47

CLK-

110

.AJ.t..A,

Oock.
-

---

Load

160

LD·

Notes:
CLK & CLK* outputs are pseudo-ECL. Logic low level is set by the ratio ofthe resistors stacked across the power supply VLO = (V supply. 160)/( 110 + 160) in the example shown above.
The above values are a good starting point for RAMDACTM or clock generator interface.

Figure 3
Pin Description
PIN NUMBER
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16

PIN SYMBOL
• FSO
XTALl
XTAL2
• STROBE
VSS
VSS
LD*
• FS4
CLK*
CLK
VDDO
VDDO
VDD
• FS3
• FS2
• FSI

TYPE

DESCRIPTION

IN
IN
OUT
IN

Frequency Select LSB
Crystal Interface/External Oscillator Input
Crystal Interface
Control For Frequency Select Latch, also performs automatic
RAMDAC reset
Device Ground (Both pins must be connected.)
Device Ground (Both pins must be connected.)
Load Output. This output is at CLK frequency divided by N 1.
Frequency Select MSB
Clock Output Inverted
Clock Output Non-Inverted
Output Stage Power (Both pins must be connected)

---

OUT
IN
OUT
OUT
--

--IN
IN
IN

Output Stage Power (Both pins must be connected)
PLL System Power
Frequency Select
Frequency Select
Frequency Select

• = inputs with internal pull-up resistor

577

ICS1567
Circuit Description

Frequency Synthesizer Description

Overview

Refer to Figure 1 for a block diagram of the ICS1567. The
reference frequency is generated by an on-chip crystal oscillator, or the reference frequency may be applied to the
ICS1567 from an external frequency source.

The ICS1567 is designed to provide the graphics system
clock signals required by industry standard RAMDACs.
One of 32 pre-programmed (user-definable) frequencies
may be selected under digital control. Fully programmable
feedback and reference divider capability allow virtually any
frequency to be generated, not just simple multiples of the
reference frequency. The ICS1567 uses the latest generation of frequency synthesis techniques developed by ICS and
is completely suitable for the most demanding video applications.

The ICS1567 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequencyprovided to the PLL. The phase-frequency detector
shown in the block diagram drives the VCO to a frequency
that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:

Digital Inputs
The FSO-FS4 pins and the STROBE pin are used to select
the desired operating frequency from the 32 pre-programmed frequencies in the ROM .tab~e of the IC.S15~7.
The STROBE pin also controls actIvatIOn of the plpelme
delay RESET function included in the ICS1567 (see PIPELINE DELAY RESET section for details). The FSO-FS4
and STROBE pins are each equipped with a pull-up and will
be at a logic HIGH level when not connected.
Transparent Mode - When the STROBE pin is held HIGH,
the FSO through FS4 inputs are transparent; that is, they
directly access the ROM table. The synthesizer will output
the frequency programmed into the location addressed by
the FSO-FS4 pins.
Latched Mode - When the STROBE pin is held LOW, the
FSO-FS4 pins are ignored. The synthesizer will output the
frequency corresponding to the state of the FSO-FS4 pins
when the STROBE pin was last HIGH. In the event that the
ICS1567 is powered-up with the STROBE pin held LOW,
the synthesizer will output the frequency programmed into
address 0 (i.e., the one selected with FSO through FS4 at a
logic LOW level).

F(vco) =

F(XTALl) • Feedback Divider
Reference Divider

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency p~o­
vided to the part (assuming correctly-programmed dlVlders). The divider programming is one of the functions
performed by the ROM look-up table in the ICS156~. The
VCO gain is also ROM programmable WhICh permIts the
ICS1567 to be optimized for best performance at each frequency in the table.
The feedback divider makes use ofa dual-modulus prescaler
technique that allows construction of a programmable
counter to operate at high speeds while still allowing the
feedback divider to be programmed in steps of 1. This is an
improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or
larger) in this respect.
A post-divider may be inserted between the VCO and the
CLK and CLK* outputs of the ICS1567. This is useful in
generation oflower frequencies, as the VCO has been ~pti­
mized for high-frequency operation. DIfferent post-dlVlder
settings may be used for each frequency in the table.

578

ICS1567
Load Clock Divider
The ICS1567 has an additional programmable divider that
is used to generate the LOAD frequency. The modulus of
this divider may be set to 3, 4, 5, 6, 8, or 10. The design of
this divider permits the output duty factor to be 50/50, even
when an odd modulus is selected.
The selection of the modulus is done by the ROM look-up
table. A different modulus may, therefore, be selected for
each frequency address.

Application Information
Power Supplies
The ICS1567 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH ofthese pins
should connect to the ground plane of the video board as
close to the package as is possible.
The ICS1567 has two VDDO pins which are the supply of

+ 5 volt power to all output stages. Again, both VDDO pins

Pipeline Delay Reset Function
The ICS1567 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This
sequence is automatically generated by the ICS1567 upon
any rising edge of the STROBE line.
When the frequency select inputs (FSO-FS4) are used in a
transparent mode, simply lower and raise the STROBE line
to activate the function. When the frequency select inputs
are latched, simply load the same frequency into the
ICS1567 twice.
When changing frequencies, it is advisable to allow 500uSec
after the new frequency is selected to activate the reset
function. The output frequency ofthe synthesizer should be
stable enough at that point for the RAMDAC to correctly
execute its reset sequence.
See Figure 4 for a diagram of the clock sequencing.

Output Stage Description
The CLK and CLK* outputs are each connected to the
drains of P-Channel MOSFET devices. The source of each
of these devices is connected to VDDO. Typical on resistance of each device is 15 Ohms. These outputs will drive
the clock and clock* of a RAMDAC device when a resistive
network equivalent to Figure 3 is utilized.
The LD* output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may
be selected for a modulus of 3,4,5,6,8, or 10. Under control
of the ROM, this output may also be suppressed (logic low
level) at any frequency select address, if desired.

connect to the same point on the die. BOTH of these pins
should be connected to the power plane (or bus) using
standard high-frequency decoupling practice. This decoupiing consists of a low series inductance bypass capacitor,
using the shortest leads possible, mounted close to the
ICS1567.
The VDD pin is the power supply for the synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided
for this pin (as shown in the recommended application
circuitry). This will allow the PLL to ''track'' through power
supply fluctuations without visible effects.

Crystal Oscillator and Crystal Selection
The ICS1567 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component,
a quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.
So-called series-resonant crystals may also be used with the
ICS1567. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically 0.005-0.01 %).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
Avoid routing digital signals or the ICS1567 outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.

579

II

ICS1567
Application Notes (continued)

ICS1567 Interface

Bus Clock Interface

The ICS1567 should be located as close as possible to the
video DAC or RAMDAC. Figure 3 illustrates interfacing the
ICS1567 to a RAMDAC. The differential output CLOCK
drivers are current sourcing only and are designed to drive
resistive terminations in a complementary fashion. CLK and
CLK* connections should follow good ECL interconnection
practice. Terminating resistors should be as close as possible
to the RAMDAC.

In some applications, it may be desirable to utilize the bus
clock. To do this, connect the clock through a .047uF capacitor to XTALI (2) and keep the lead length ofthe capacitor
to XTALl (2) to a minimum to reduce noise susceptibility.
This input is internally biased at VDD12. Since TTL compatible clocks typically exhibit a VOH of 3.5V, capacitively
coupling the input restores noise immunity. The ICSl567 is
not sensitive to the duty cycle ofthe bus clock; however, the
qualityofthis signal varies considerably with different motherboard designs. As the quality ofthe bus clock is typically
outside the control of the graphics adapter card manufacturer, it is suggested that this signal be buffered on the
graphics adapter board. XTAL2 (3) must be left open in this
configuration.

Absolute Maximum Ratings
Ambient Temeperature under bias. . ..
SupplyVoJtage ....................
Input Voltage ......................
Output Voltage ....................
Clamp Diode Current. ..............
Output Current per Pin . . . . . . . . . . . ..
Storage Temperature. . . . . . . . . . . . . ..
Power Dissipation. . . . . . . . . . . . . . . . ..

To .............
VDD ...........
VIN ............
VOUT ..........
VIK & 10K ......
lOUT ...........
Ts .............
PD .............

O°C to 70°C
-O.5V to + 7V
-O.5V to VDD + O.5V
-O.5V to VDD + O.5V
+ 1-3OmA
+ 1;5OmA
-85 C to + 150°C
500mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid
applications of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and
VOUT be constrained to > = Vss and < = VDD.

Standard Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are
referenced to VSS (OV Ground). Positive current flows into the referenced pin.
O°C to 70°C
4.75 to 5.25 Volts

580

ICS1567
DC Characteristics
SYMBOL

MIN

MAX

UNITS

Input High Voltage

VIH

2.0

VDD + 0.5

V

Input Low Voltage

VIL

Vss -0.5

0.8

V

Input High Current

IIH

10

uA

VIN= VDD

Input Low Current

IrL

-200

uA

VIN= Vss

V

IOH = -4.0 rnA

V

IOL = 6.0rnA

V

See Figure 4

I

PARAMETER

CONDITIONS

LOAD OUTPUT
Output High Voltage

VOH

Output Low Voltage

VOL

2.4
0.4
. CLOCK OUTPUTS

Differential Output Voltage
:(CLK-CLK*)

VOD

1.2

VDD + 0.5

XTALI INPUT
Input High Voltage

VXH

3.75

Input Low Voltage

VXL

VSS -0.5

1.25

V

Operating Current

IDD

50

rnA

Outputs Unloaded

Input Pin Capacitance

CIN

8

pF

Fc= IMHz

COUT

12

pF

Fc= IMHz

Output Pin Capacitance

581

V

ICS1567
AC Characteristics
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

60
0.5
2
2
180

%
%
ns
ns
MHz
uS

3,4,9

60
60
2
2

%
MHz
ns
ns

6

20

MHz
pF

CLK and CLK* TIMING
Duty Cycle
Frequency Error
Rise Time
Fall Time
VCO Frequency
PLL Acquire Time

THIGH
Tr
Tf
FyCO
TLOCK

40

20
500

5,9
5,9
1

LD*TIMING
Duty Cycle
Load Freguency
Rise Time
Fall Time
Crystal Frequency
Crystal 0 scillator
Loadinj( Capacitance
XTALl High Time
XTALI Low Time
Rise Time
Fall Time

40
THIGH
FLOAD
Tr
Tf
REFERENCE INPUT CLOCK
5
FXTAL
20
CPAR
TXHI
TXLO
Tr
Tf

8
8
10
10

7,8
7,8

ns
ns
ns
ns

2
2
2, 7
2, 7

ns
ns
ns

10

ns
ns
ns

10
10
10

DIGITAL INPUTS
Frequency Select Setup Time
Frequency Select Hold Time
Strobe Pulse Width

1
2
3

Reset Activation
Reset Duration
Restart Delay

4
5
6

10

10
20
PIPELINE DELAY RESET
2*TcLK
4*TcLK
-l*TcLK

+ 1.5*TcLK

10
10

Notes:
1. Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK* outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
2. Values for XTALI driven by an external clock
3. Duty Cycle for Differential Output (CLK- CLK*)
4. Duty cycle measured at VODI2 for Differential CLK Output
5. Rise and fall time between 20% and 80% ofVOD
6. Duty cycle measured at 1.4v for TTL 110
7. Rise and fall time between 0.8 and 2.0 VDC for TTL 110
8. Output pin loading = 15 pf
9. See Figure 3.
10. See Figure 4.

582

ICS1567
~3

LATCHED INPUTS,
STROBE
FSO-FS4

--_I

----7

\'--____

~1 ~2---7

----~X

~

PIPELINE DELAY RESET'

~3*3-7
~

/~~\--------------

STROBE
DIFFCLK
LD*

f- 4 - ) * ( - - - 5

-----7)

~~
-7

~

Tclk

6 -7

~

~
Figure 4

S83

ICS1567
ICS1567 Pattern Request Form
Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will apply.
Contact ICS Sales for details.
ICS Part
Number
Video Clock
Address (HEX)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

ICS1567742
Frequency
(MHz)

ICS1567Custom Pattern # 1
Frequency
(MHz)

112.000
148.000
OFF
135.000
31.500 .
105.500
78.000
86.000
108.000
120.000
128.000
93.000
112.000
148.000
135.000
89.210
105.500
112.000
25.000
45.000
64.000
75.000
78.000
86.000
103.000
108.000
120.000
127.000
128.000
135.000
112.000
148.000

Custom pattern # 1 reference frequency =
Standard parttern shown above uses 16.000 MHz as the input reference frequency.
Order info: ICSI567M-XXX or ICSI567N-XXX (M= SO pkg., N= DIP pkg., XXX= Pattern number)

584

•

ICS1572

Integrated
Circuit
Systems, Inc.

User Programmable Differential Output Graphics Clock Generator
Description

Features

The ICS1572 is a high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing rcs'
advanced CMOS mixed-mode technology, the ICS1572
provides a low cost solution for high-end video clock generation in workstations and high-end PC applications.

•

The ICS1572 has differential video clock outputs (CLK+
and CLK-) that are compatible with industry standard video
DACs. Another clock output, LOAD, is provided whose
frequency is derived from the main clock bya programmable
divider. An additional clock output is available, LD/N2,
which is derived from the LOAD frequency and whose
modulus may also be programmed.
Operating frequencies are fully programmable with direct
control provided for reference divider, pre-scaler, feedback
divider and post-scaler.
Reset of the pipeline delay on Brooktree RAMDACsTM may
be performed under register control. Outputs may also be
set to desired states to facilitate circuit board testing.

•
•
•
•
•

Supports high-resolution graphics - CLK output to 180
MHz
Eliminates need for multiple ECL output crystal oscillators
Fully programmable synthesizer capability - not just a
clock multiplier
Available in 20-pin 300 mil wide body sorc package
Available in both parallel (101) and serial (301)
programming versions
Circuit included for reset of Brooktree RAMDAC
pipeline delay

Applications
•

•
•

Workstations
AutoCad Accelerators
High-end PC graphics systems
ICSI572-101 Pinout
NC

NC

20

ADO

AD1

19

XTAL1

AD2

18

XTAL1

XTAL2

AD3

17

XTAL2

STROBE

VDD

16

VSS

VDDO

15

10

FEEDBACK DIVIDER

VSS

IPRG

14

LOAD

CLK+

13

LD/N2

CLK-

12

NC

NC

11

PROGRAMMING
INTERFACE

ICSI572-301 Pinout
CLK+

NC

NC

20

CLK-

EXTFBK

DATA

19

XTAL1

HOLD

18

XTAL2

BLANK

17

DATCLK

VOD

16

VSS

VODO

15

VSS

IPRG

14

LOAD

CLK+

13

LD/N2

CLK-

12

NC

NC

11

LOAD

LD/N2

10

Figure 1
RAMDAC IS a trademark of Brooktree Corporation

585

(I

ICS1572

Table I permits the derivation of "A" & 'M" counter programming directly from desired modulus.

Overview
The ICS1572 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just
simple multiples of the reference frequency. The ICS1572
uses the latest generation of frequency synthesis techniques
developed by ICS and is completely suitable for the most
demanding video applications.

PLL Post-Scaler
A programmable post-scaler may be inserted between the
VCO and the CLK+ and CLK- outputs of the ICS1572.
This is useful in generating oflower frequencies, as the VCO
has been optimized for high-frequency operation.
The post-scaler allows the selection of:

PLL Synthesizer DescriptionRatiometric Mode
The ICS1572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequencyprovided to the PLL (see Figure 1). The reference
frequency is generated by an on-chip crystal oscillator or the
reference frequency may be applied to the ICS1572 from an
external frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or VCO, to a frequencythat will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:
F(

veo):

=

F(XTALl) . Feedback Divider
Reference Divider

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).
The VCO gain is programmable, which permits the ICS1572
to be optimized for best performance at all operating frequencies.
The reference divider maybe programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 391 in steps of one. Any even modulus from
392 through 782 can also be achieved by setting the "double"
bit which doubles the feedback divider modulus. The feedback divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at
low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that
typically impose a factor-of-four penalty (or larger) in this
respect.

586

•
•
•
•

VCO frequency
VCO frequency divided by 2
VCO frequency divided by 4
Internal register bit (AUXCLK) value

Load Clock Divider
The ICSI572 has an additional programmable divider
(referred to in Figure I as the NI divider) that is used to
generate the LOAD clock frequency for the video DAC.
The modulus of this divider may be set to 3, 4, 5, 6, 8, or 10
under register control. The design of this divider permits the
output duty factor to be 50/50, even when an odd modulus
is selected. The input frequency to this divider is the output
of the PLL post-scaler described above.

Digital Inputs -ICS1572-101 Option
The ADO-AD3 pins and the STROBE pin are used to load
all control registers of the ICS1572 (-101 option). The ADOAD3 and STROBE pins are each equipped with a pull-up
and will be at a logic HIG H level when not connected. They
maybe driven with standard TTL or CMOS logic families.
The address ofthe register to be loaded is latched from the
ADO-AD3 pins bya negative edge on the STROBE pin. The
data for that register is latched from the ADO-AD3 pins by
a positive edge on the STROBE pin. See Figure 2 for a
timing diagram. After power-up, the ICS1572-101 requires
32 register writes for new programming to become effective.
Since only 13 registers are used at present, the programming
system can perform 19 "dummy" writes to address 13 or 14
to complete the sequence.

II

ICS1572

This allows the synthesizer to be completely programmed
for the desired frequency before it is made active. Once the
part has been ''unlocked'' by the 32 writes, programming
becomes effective immediately.
ALL registers identified in the data sheet (0-9, II, 12 & 15)
MU ST be written upon initial programming. The programming registers are not initialized upon power-up, but the
latched outputs of those registers are. The latch is made
transparent after 32 register writes. If any register has not
been written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist.
Register 10 does exist, but is reserved for future expansion.
To insure compatibility with possible future modifications to
the database, ICS recommends that all three unused locations be written with zero.
ICS1572-101 Register Loading

---r--

STROBE

~

5

~ 1 ~ k-3==1-4~

~

ADO·AD3

ADDRESS VALID

G

DATA VALID

An additional control pin on the ICS1572-301, BLANK can
perform either of two functions. It may be used to disable
the phase-frequency detector in line-locked applications.
Alternatively, the BLANK pin maybe used as a synchronous
enable for VRAM shift clock generation. See sections on
Line-Locked Operations and VRAM shift clock generation
for details.

Output Description
The differential output drivers, CLK+ and CLK, are current-mode and are designed to drive resistive terminations
in a complementary fashion. The outputs are current-sinking only, with the amount of sink current programmable via
the IPRG pin. The sink current, which is steered to either
CLK+ or CLK-, is approximately four times the current
supplied to the IPRG pin. For most applications, a resistor
from VDDO to IPRG will set the current to the necessary
precision. See Figure 6 for output characteristics.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled bya programmable divider that may
be selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also
be suppressed under register control.

'C

The LD/N2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programmable modulus may range from I to 512 in steps of one.

Figure 2
Digital Inputs - ICS1572-301 Option
The programming of the ICS1572-301 is performed serially
byusingtheDATCLK, DATA, and HOLD- pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD- pin is latched
at the same time. When HOLD- is low, the shift register
may be loaded without disturbing the operation of the
ICS1572. When high, the shift register outputs are transferred to the control registers, and the new programming
information becomes active. Ordinarily, a high level should
be placed on the HOLD- pin when the last data bit is
presented. See Figure 3 for the programming sequence.

Pipeline Delay Reset Function
The ICS1572 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This
sequence can be generated by setting the appropriate register bit (DACRST) to a logic 1 and then resetting to logic O.
When changing frequencies, it is advisable to allow 500
microseconds after the new frequency is selected to activate
the reset function. The output frequency of the synthesizer
should be stable enough at that point for the video DAC to
correctly execute its reset sequence. See Figure 4 for a
diagram ofthe pipeline delay reset sequence.
Pipeline Delay Reset Timing

ICS1572-301 Register Loading

~

8-

,

~ l~

DATCLI<
DATA

HOLD

=:\

6

7~

DATA_56

CI

r

J

STROBE
or
DATCLI<
CLK+

L

\~f0-~~AA
7
-i1

LOAD

Figure 3

~

TCLI<

,

Figure 4
587

12

-1

~

~«-~___

ICS1572
ICS1572-101

The ICS1572 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component,
a quartz crystal. Pierce oscillators operate the crystal in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to specify
when ordering crystals.

The ICS1572-101 supports phase detector
disable via a special control mode. When the
PDRSTEN (phase detector reset enable)
bit is set, a high level on AD3 will disable
PLL locking.

ICS1572-301

The ICS1572-301 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disable PLL locking.

Series-resonant crystals may also be used with the ICS1572.
Be aware that the oscillation frequency will be slightlyhigher
than the frequcncy that is stamped on the can (typically
0.025-0.05% ).

External Feedback Operation

Reference Oscillator and Crystal
Selection

The ICS1572-301 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This
mode is useful in graphic systems that must be "genlocked"
to external video sources.

As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
Avoid routing digital signals or the ICS1572 outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.

When the EXTFBEN bit is set to logic I, the phase-frequency detector will use the EXTFBK pin as its feedback
input. The loop phase will be locked to the rising edges of
the signal applied to the EXTFBK input.

If an external reference frequency source is to be used with
the ICS1572, it is important that it be jitter-free. The rising
and falling edges of that signal should be fast and free of
noise for best results.
The loop phase is locked to the falling edges of the XTALI
input signals.

Line-Locked Operation
The ICS1572 supports line-locked clock applications by
allowing the LOAD (NI) and N2divider chains to act as the
feedback divider for the PLL.

VRAM Shift Clock Generation
The ICS1572-301 option supports VRAM shift clock generation and interruption. By programming the N2 counter
to divide by I, the LD/N2 output becomes a duplicate ofthe
LOAD output. When the SCEN bit is set, the LDIN2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LD/N2 will be free-running and
in phase with LOAD. When BLANK is taken low, the
LDIN2 output is stopped at a low level. See Figure 5 for a
diagram of the sequence. Note that this use of the BLANK
pin precludes its use for phase comparator disable (see
Line-Locked Operation).

The NI and N2 divider chains allow a much larger modulus
to be achieved than the PLI..:s own feedback divider. Additionally, the output of the N2 counter is accessible off-chip
for performing horizontal reset of the graphics system,
where necessary. This mode is set under register control
(ALTLOOP bit). The reference divider (R counter) is set
to divide by 1 in this mode, and the HSYNC signal of the
external video will be supplied to the XTALI input. The
output frequency of the synthesizer will then be:

VRAM Shift Clock Control

B~~

~

!'lII;!/I//I/l

LO~~

LDiN2LJ-\

F(CLK) : = F (XTALl) . NI . N2.
By using the phase-detector hardware disable mode, the
PLL can be made to free-run at the beginning of the vertical
interval of the external video, and can be reactivated at its
completion.

;--

Figure 5

588

II

ICS1572
•

Power-On Initialization
The ICS1572 has an internal power-on reset circuit that
performs the following functions:
1)

Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.

2)

Selects the modulus ofthe N 1 divider (for the
LOAD clock) to be four.

Board Test Support

These functions should allow initialization of most graphics
systems that cannot immediately provide for register programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VD D supply
reaches 4 volts.

Programming Notes
•

•

•

VCO Frequency Range: Use the post-divider to keep
the VCO frequency as high as possible within its operating range.
Divider Range: For best results in normal situations
(i.e., pixel clock generation for hi-res displays), keep the
reference divider modulus as short as possible (for a
freq uency at the output of the reference divider in the
few hundred kHz to several MHz range). If you need
to go to a lower phase comparator reference frequency
(usually required for increased frequency accuracy),
that is acceptable, but jitter performance will suffer
somewhat.
VCO Gain Programming: Use the minimum gain
which can reliably achieve the VCO frequency desired,
as shown here:
VCOGAIN
4
5
6
7

Phase Detector Gain: For most graphics applications
and divider ranges, set P[I,O] = 10 and set P[2] = l.
Under some circumstances, setting the P[2] bit "on" can
reduce jitter. During 1572 operation at exact multiples
of the crystal frequency, P[2] bit = 0 may provide the
best jitter performance.

MAX FREQUENCY
120 MHz
200 MHz
230 MHz

It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1572 supports this

through a register programmable mode, AUXEN. When
this mode is set, two register bits directly control the logic
levels of the CLK+ ICLK- pins and the LOAD pin. This
mode is activated when the S[O] and S[I] bits are both set to
logic l. See Register Mapping for details.

Power Supplies and Decoupling
The ICS1572 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as
close to the package as is possible.
The ICS1572 has a VDDO pin which is the supply of + 5
volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have
low series inductance and be mounted close to the ICS1572.
The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We
recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to "track" through
power supply fluctuations without visible effects. See
Figure 7 for typical external circuitry.
DI,FERENTIAL

*

CLOC~

OUTPU- SINI\ CURRENT

:>10,
15--~L-----------------~

• SPECIAL APPLICATION Contact factory for custom product above
230 MHz.

10

Figure 6
589

~I

~

ICS1572
ICS1572 Typical Interface

,--10
SELECT LOGIC

L-=t= ~~
3

4
5
6

~~
-~
--J:[

XTALl
XTAL2

STROBE
VSS
VSS
LOAD
LD/N2
NC

~~

AD2
AD3
VDD
VDDO

~~

=!=-

LI+

16
15

Tr

1~

~

-i¥-17

+ 5V
j

120

120

C~-~
I"7
---1.!.-

NC

TO

I

RAMDAC

390

< 390

<

--

J:
Figure 3

S90

~

-

II

ICS1572

Register Mapping - ICS1572-1 01 (Parallel Programming Option)
NOTE' IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572 PC SOFTWARE IS A VAILABLE FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS CONTACT FACTORY
FOR DETAILS

REG#

BIT(S)

0
1

0-3
0-2

R[0] .. R[3]
R [4]..R [6]

Reference divider modulus control bits
Modulus = value + I

2

0-3

A[0] .. A[3]

Controls A counter. When set to zero, modulus= 7. Otherwise,
modulus= 7 for "value" underflows of the prescaler, and modulus= 6
thereafter until M counter underflows.

3
4

0-3
0-1

M[0] .. M[3]
M[4] .. M[5]

M counter control bits
Modulus = value + I

4

3

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6/7 to 121l4).

5

0-2

N I [O] .. N I [21

Sets NI modulus according to this table. These bits are set to implement a divide-by-four on power-up.

BIT REF.

6
7

0-3
0-3

N2[0] .. N2[3]
N2[4] .. N2[7]

8

3

N2[8]

8

0-2

V[O] .. V[1]

DESCRIPTION

NI[2]

NI[1]

Nl[O]

RATIO

0
0

0
0

0
I

3
4

0

I

0

4

0

I

1

5

1

0

0

6

I

1

1

0
1

0

8

1

I

1

10

8

--

I
-

Sets the modulus of the N2 divider. Modulus = value + 1
The input of the N2 divider is the output of the N I divider in all clock
modes except AUXEN.

Sets the gain of the VCO.
V[2]

V[1]

V [0]

1

0

0

30

1

0

1

45

1

1

1

1

0
1

60
80

591

VCO GAIN
(MHz/VOLT)

(I

ICS1572
REG#
9

BIT REF.
0-1

DESCRIPTION

P[O] .. P[1]

Sets the gain ofthe phase detector according to this table.
P[I]

prO]

GAIN (uA/radian)

0

0.05

0

0
1

1

0

0.5

1

I

1.5

0.15

9

3

[P2]

Phase detector tuning bit. Normally should be set to one.

11

0-1

S[O] .. S[1]

PLL post-scaler/test mode select bits
S[I] S[O]
0

0

0

I

I

0

I

1

DESCRIPTION
Post-scaler= 1. F(CLK)= F(PLL). The output ofthe NI divider
drives the LOAD output which, in turn, drives the N2 divider.
Post -scaler= 2. F(CLK)= F(PLL)I2. The output of the NI
divider drives the LOAD output which, in turn, drives the N2
divider.
Post-scaler= 4. F(CLK)= F(PLL)/4. The output of the NI
divider drives the LOAD output which, in turn, drives the N2
divider.
AUXEN CLOCK MODE. The AUXCLK bit drives the
differential outputs CLK+ and CLK- and the AUXNI bit drives
the LOAD output which, in turn, drives the N2 divider.
----

11

2

AUX_CLK

When in the AUXEN clock mode, this bit controls the differential
outputs.

II

3

AUX_NI

When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).

12

0

RESERVED

Must be set to zero.

JAMPLL

Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.

12
12

2

DACRST

Set to zero for normal operation. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+ /- I CLK period).
To initiate a RAMDACTM reset sequence, simply write a one to
this register bit followed by a zero.

12

3

SELXTAL

When set to logic I, passes the reference frequency to the post-scaler.

15

0

ALTLOOP

Controls substitution ofNl and N2 dividers into feedback loop ofPLL.
When this bit is a logic I, the NI and N2 dividers are used.

15

3

PDRSTEN

Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See LINE-LOCKED CLOCK GENERATION section for more
details on the operation of this function.

592

ICS1572
Register Mapping· ICS1572·301 (Serial Programming Option)
NOTE IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS I 572. PC SOFTWARE IS AVAILABLE FROM ICS TO AUTOMATICALL Y GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY
FOR DETAILS

BlT(S)

BIT REF.

1-3

NI[a] .. NI[2]

DESCRIPTION
Sets N 1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
NI[2]

NI[I]

NI[a]

a

a

a

3

a

1

4

a

a
I

a

4

a

1

1

I

0

a

5
6

1

a

I

8

1

1

a

8

1

1

1

10

RATIO

4

RESERVED

Set to zero.

5

RESERVED

MUST be set to zero. If this bit is ever programmed for a logic one, device
operation will cease and further serial data load into the registers will be
inhibited until a power-off/power-on sequence.

6

JAMPLL

Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.

7

DACRST

Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+ 1- 1 CLK period).
To initiate a RAMDACTM reset sequence, simply write a one to this register
bit followed by a zero.

8

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

9

ALTLOOP

Controls substitution ofNI and N2 dividers into feedback loop ofPLL.
When this bit is a logic I, the NI and N2 dividers are used.

10

SCEN

VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.

11

EXTFBKEN

External PLL feedback select. When logic I, the EXTFBK pin is used for
the phase-frequency detector feedback input.

12

PDRSTEN

Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.

593

ICS1572
BIT REF.
13-14

DESCRIPTION

S[O] .. S[1]

PLL post-scaler/test mode select bits.
S[1] S[O]
DESCRIPTION
0
0 Post-scaler= 1. F(CLK)= F(PLL). The output ofthe NI divider
drives the LOAD output which, in turn, drives the N2 divider.
0
1 Post-scaler= 2. F(CLK)= F(PLL)I2. The output of the Nl
divider drives the LOAD output which, in turn, drives the N2
divider.
0 Post -scaler= 4. F(CLK)= F(PLL)/4. The output of the NI
I
divider drives the LOAD output which, in turn, drives the N2
divider.
I
I AUXEN CLOCK MODE. The AUXCLK bit drives the
differential outputs CLK+ and CLK- and the AUXNI bit drives
the LOAD output which, in turn, drives the N2 divider.

15

When in the AUXEN clock mode, this bit controls the differential outputs.

16

When in the AUXEN clock mode, this bit controls the NI output (and
consequently the N2 output according to its programming).

17-24
28

N2[0]..N2[7]
N2[8]

25-27

V[0] .. V[2]

29-30

P[O] .. P[I]

}

Sets the modulus ofthe N2 divider. The input ofthe N2 divider is the
output of the NI divider in all clock modes except AUXEN.
Sets the gain ofVCO.
V[2]

V[1]

V[O]

I
I
1
I

0
0
1
I

0
1
0
1

VCO GAIN
(MHzlVOLT)
30
45
60
80

Sets the gain of the phase detector according to this table.
P[I]
0
0
1
I

prO]
0
I
0
I

GAIN (uA/radian)
0.05
0.15
0.5
1.5

31

RESERVED

Set to zero.

32

P[2]

Phase detector tuning bit. Should normally be set to one.

594

II

ICS1572

BIT(S)

BIT REF.

33-38

M[O] .. M[5]

M counter control bits
Modulus = value + 1

39

RESERVED

Set to zero.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 617 to 12114).

41-44

A [O]..A [3]

Controls A counter. When set to zero, modulus= 7. Otherwise,
modulus= 7 for "value" underflows of the prescaler, and modulus= 6
thereafter until M counter underflows.

45-48

RESERVED

Set to zero.

49-55

R [O]..R [6]

Reference divider modulus control bits
Modulus = value + 1

56

RESERVED

Set to zero.

DESCRIPTION

I

595

ICS1572
Table 1 - "A" & 'M" Divider Programming
Feedback Divider Modulus Table
A[2j ••A[Oj·

001

010

011

100

101

110

111

A[2j ..A[Oj-

000

M[5j .. M[Oj

001

010

011

100

101

110

111

000

M[5j .. M['Oj

000000

7

100000

199

200

201

202

203

204

205

231

14

100001

205

206

207

208

209

210

211

238

21

100010

211

212

213

214

215

216

217

245

28

100011

217

218

219

220

221

222

223

252

35

100100

223

224

225

226

227

228

229

259

42

100101

229

23'0

231

232

233

234

235

266

49

100110

235

236

237

238

239

240

241

273

56

100111

241

242

243

244

245

246

247

280

63

101000

247

248

249

250

251

252

253

287

67

70

101001

253

254

255

256

257

258

259

294

72

73

77

101010

259

260

261

262

263

264

265

301

77

78

79

84

101011

265

266

267

268

269

270

271

308

83

84

85

91

101100

271

272

273

274

275

276

277

315

000001

13

000010

19

20

000'011

25

26

27

00'010'0

31

32

33 i

34

00'0101

37

38

39

40

41

00011'0

43

44

45

46

47

48

000111

49

50

51

52

53

54

55

001000

55

56

57

58

59

60

61

'001001

61

62

63

64

65

66

'001010

67

68

69

7'0

71

001011

73

74

75

76

001100

79

80

81

82

001101

85

86

87

88

89

9'0

91

98

10110!

277

278

279

280

281

282

283

322

001110

91

92

93

94

95

96

97

105

101110

283

284

285

286

287

288

289

329

001111

97

98

99

100

101

102

103

112

101111

289

290

291

292

293

294

295

336

010000

103

104

105

106

107

108

109

119

110000

295

296

297

298

299

300

301

343

010001

109

110

112

113

114

115

126

110001

301

302

303

304

305

306

307

350

010010

115

116

118

119

120

121

133

110010

307

308

310

311

312

313

357

'010011

121

122

124

125

126

127

140

110011

313

314

309
315

316

317

318

319

364

010100

127

128

III
117
123
129

130

131

132

133

147

110100

319

320

321

322

323

324

325

371

010101

133

134

135

136

137

138

139

154

110101

325

326

327

328

329

330

331

378

010110

139

140

141

142

143

144

145

161

110110

331

332

333

334

335

336

337

385

'010111

145

146

147

148

149

150

151

168

110111

337

338

339

340

341

342

343

392

011000

151

152

153

154

155

156

157

175

111000

343

344

345

346

347

348

349

399

011001

157

158

159

160

161

162

163

182

111001

349

350

351

352

353

354

355

406

355

356

357

358

359

360

361

413

361

362

363

364

365

366

367

420

011010

163

164

165

166

167

168

169

189

011011

169

170

171

172

173

174

175

196

f--- 111010
111011

011100

175

176

177

178

179

180

181

203

111100

367

368

369

370

371

372

373

427

011101

181

182

183

184

185

186

187

210

111101

373

374

375

376

377

378

379

434

011110

187

188

191

192

193

217

111110

379

380

381

382

383

384

385

441

011111

193

194

~

190
196

197

198

199

224

111111

385

386

387

388

389

390

391

448

195

Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is:

N = [(M + 1) ·6] + A

except when A= 0, then:

N= (M + I) ·7

Under all circumstances:

A:S; M

5%

I

ICS1572
Pin Descriptions -ICS1572-101
PIN#
13

12
8
3
4
2
19
18
17

9
S
16
IS
14
6,7
1,10,11,20

DESCRIPTION

NAME
CLK+
CLKLOAD
XTALI
XTAL2
ADO
ADI
AD2
AD3
LD/N2
STROBE
VDD
VDDO
IPRG
VSS
NC

Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK freq uency divided by N I.
Quartz crystal connection lIexternal reference freq uency input
Quartz crystal connection 2
Address/Data Bit 0 (LSB)
Address/Data Bit I
AddresslData Bit 2
Address/Data Bit 3 (MSB)
Divided LOAD output. See text.
Control for address/data latch
PLL system power (+ SY. See application diagram.)
Output stage power (+ 5V)
Output stage current set
Device ground. Both pins must be connected to the same ground potential.
Not connected

Pin Descriptions - ICS1572-301
PIN#
13

12
8
3
4
S
19
18
17

9
2
16
IS
14
6,7
1,10,11,20

NAME
CLK+
CLKLOAD
XTALI
XTAL2
DATCLK
DATA
HOLDBLANK
LDIN2
EXTFBK
VDD
VDDO
IPRG
VSS
NC

DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by Nl.
Quartz crystal connection l!external reference freq uency input
Quartz crystal connection 2
Data Clock (Input)
Serial Register Data (Input)
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input). See text.
PLL system power (+ SY. See application diagram.)
Output stage power (+ SV)
Output stage current set
Device ground. Both pins must be connected.
Not connected

597

ICS1572
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) ......................
Digital Inputs .......................................
Digital Outputs ... , ........ " ..................... ,.
Ambient Operating Temperature ......................
Storage Temperature ................................
Junction Temperature ................................
Soldering Temperature ...............................

7.0V
Vss-0.5 to VDD + 0.5V
Vss-0.5 to VDDO + 0.5V
-55 to 125°C
-65 to 150°C
175°C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to VSS) ...................... 4.75 to 5.25V
Operating Temperature (Ambient) .................... 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
101 Option - (ADO-AD3, STRO~
301 Option - (DATClK, DATA, HOLD, BLANK, EXTFBK)

PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance

SYMBOL
Vlh
VII
Ilh
III
Cm

CONDITIONS

Vlh= VDD
Vll= 0.0

MIN
2.0
Vss-0.5

MAX
VDD+ 0.5
0.8

-

10

-

150
8

-

UNITS
V
V
uA
uA
pF

XTAl1 Input

PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL

CONDITIONS

Vxh
Vxl

MIN
3.75
Vss-0.5

MAX
VDD+ 0.5
1.25

UNITS
V

MIN
2.4

MAX

-

0.4

UNITS
V
V

ClK+ , ClK- Outputs

PARAMETER
DifferentialOut ut Voltage

CONDITIONS

lOAD, lDIN2 Outputs

PARAMETER
Output High Voltage (loh= 4.0mA)
Output Low Voltage (101= 8.OmA)

SYMBOL

CONDITIONS

598

-

ICS1572
SYMBOL
Fvco
Fxtal
C par
Fload
Txhl
Txlo
ThIgh
Jclk
Tlock
Idd
Iddo

1
2
3
4
5
6
7

8
9
10
11

12
13
14

PARAMETER
VCO Frequency (see Note 1)

MIN
20
5

Crystal Frequency
Crystal Oscillator Loading Capacitance
LOAD Frequency
XTALl High Time (when driven externally)
8
XTAL 1 Low TIme (when driven externally)
8
Differential Clock Output Duty Cycle
45
(see Note 2)
Differential Clock Output Cumulative
JitterJsee Note 3)
PLL Acquire Time (to within 1% )
VDD Supply Current
VDDO Supply Current (excluding CLK+ ftermination)
DIGITAL INPUTS - ICSI572-lOl
Address Setup Time
10
Address Hold Time
10
Data Setup Time
10
Data Hold Time
STROBE Pulse Width (Thl or TIo)

TYP

MAX
160

UNITS
MHz

20
80

MHz
pF
MHz
ns
ns

55

%

20

< 0.06
500
15
20

pixel
~s

t.b.d.
t.b.d.

ns
ns
ns
ns
ns

10
---~

20
DIGITAL OUTPUTS - ICSI572-301
DATAfHOLD- Setup Time
10
DATAfHOLD- Hold Time
10
DATCLK Pulse Width (Thl or TIo)
20
PIPELINE DELAY RESET
Reset Activation Time
Reset Duration
4*Tload
Restart Delay
Restart Matching
-!*Tclk
DIGITAL OUTPUTS
CLK+ fCLK- Clock Rate
LOAD To LDfN2 Skew (Shift Clock Mode)
-2

rnA
rnA

ns
ns
ns
2*Tclk
2*Tload
+ 1.5*Tclk
180
0

+2

ns
ns
ns
ns
MHz
ns

Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and
eLK-.

Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time,
compared with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification
in virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and
register programming.

599

ICS1572 Application Information

Output Circuit Considerations for the ICS1572
Output Circuitry
The dot clock signals CLK and CLK- are typically the
highest frequency signals present in the workstation. To
minimize problems with EMI, crosstalk, and capacitive
loading extra care should be taken in laying out this area of
the PC board. The ICS1572 is packaged in a 0.3 "-wide 20-pin
SOIC package. This permits the clock generator, crystal,
and related components to be laid out in an area the size of
a postage stamp. The ICS1572 should be placed as close as
possible to the RAMDAC. The CLK and CLK- pins are
running at VHF frequencies; one should minimize the
length of PCB trace connecting them to the RAMDAC so
that they don't become radiators ofRF energy.

Stripline is the other form a PCB transmission line can take.
A buried trace between ground planes (or between a power
plane and a ground plane) is common in multi-layer boards.
Attempting to create a workstation design without the use
of multi-layer boards would be adventurous to say the least,
the issue would more likely be whether to place the interconnect on the surface or between layers. The between layer
approach would work better from an EMI standpoint, but
would be more difficult to layout. A strip line is shown
below:

At the frequencies that the ICS1572 is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength ofthat frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting wires. These lines can take two forms: microstrip
and stripline. A microstrip line is shown below:

Strlpllne
Using loz. copper (0.0015" thick) and 0.040"thickness G 10,
a 0.010" trace will exhibit a characteristic impedance of750
in a strip line configuration.

zo=

87

ye r +1.41

Typically, RAMDACS require a VIh of V AA-1.0 Volts as a
guaranteed logical "1" and a VII of VAA-1.6 as a guaranteed
logical "0". Worst case input capacitance is 10 pF.

(5.98h)

In D.8w+!

Dimensions in inches

Microstrip Line
Essentially, the microstrip is a copper trace on a PCB over
a ground plane. Typically, the dielectric is G 10 glass epoxy.
It differs from a standard PCB trace in that its width is
calculated to have a characteristic impedance. To calculate
the characteristic impedance of a microstrip line one must
know the width and thickness ofthe trace, and the thickness
and dielectric constant of the dielectric. For G 10 glass epoxy, the dielectric constant (er) is about 5. Propagation delay
is strictly a function of dielectric constant. For G 10 propagation, delay is calculated to be 1.77 ns/ft.

Output circuitry for the ICS1572 is shown in the following
diagram. It consists of a 411 current mirror, and two open
drain output FE Ts along with inverting buffers to alternately
enable each current-sinking driver. Both CLK and CLKoutputs are connected to the respective CLOCK and
CLOCK* inputs of the RAMDAC with transmission lines
and terminated in their equivalent impedances by the
Thevenin equivalent impedances ofRI and R20r Rl' and R2'.

600

(I

ICS1572 Application Note

The ICS1572 is incapable of sourcing current, so Vlh must
be set by the ratios of these resistors for each of these lines.
R 1 and R2are electrically in parallel from an AC standpoint
because Vdd is bypassed to ground through bypass-capacitor network Cb. If we picked a target impedance of 750. for
our transmission line impedance, a value of910. for R I and
Rl' and a value of 4300. for R2 and R2' would yield a
Thevinin equivalent characteristic impedance of75.1 Wand
a Vih value ofVAA-.873 Volts, a margin ofO.l27Volts. This
maybe adequate; however, at higher frequencies one must
contend with the IOpF input capacitance ofthe RAMDAC.
Values of 820. for R 1 and R l' and 8200. for R2 and R2'
would give us a characteristic impedance of74.50. and a Vlh
value of V AA -.45. With a .55 Volt margin on Vlh, this voltage
level might be safer.

Cb is shown as multiple capacitors. Typically, a 22 J.lF tantalum should be used with separate .I J.lF and 220pF capacitors
placed as close to the pins as possible. This provides low
series inductance capacitors right at the source of high
frequency energy. Rd is used to isolate the circuitry from
external sources of noise. Five to ten ohms should be adequate.
Vdd

I 'd
Cb

' ' ' t, _______ ,

0~
eLK,

' J:

To set a value for V II, we must determine a value for Iprg that
will cause the output FE T's to sink an appropriate current.
We desire VII to be V AA-1.6 or greater. V AA-2 would seem
to be a safe value. Setting up a sink current of 25 milliamperes would guarantee this through our 820. pull-up resistors. As this is controlled by a 411 current mirror, 7 rnA into
Iprg should set this current properly. A 5100. resistor from
V dd to Iprg should work fine.
Resistors Rt and Rt' are shown as series terminating resistors at the ICS1572 end of the transmission lines. These are
not required for operation, but may be useful for meeting
EMI requirements. Their intent is to interact with the input
capacitance of the RAMDAC and the distributed capacitance of the transmission line to soften up rise and fall times
and consequently cut some of the high-order harmonic
content that is more likely to radiate RF energy. In actual
usage they would most likely be 10 to 200. resistors or
possibly ferrite beads.

±

~4
ICS1572

I
I
I
I
I

Rt'

-"

I
RI'

Clock-

,

~l

v AA
Clock

". !

RAMDAC

GND

ICS1572 Output Circuitry
Great care must be used when evaluating high frequency
circuits to achieve meaningful results. The 10 pF input capacitance and long ground lead of an ordinary scope probe
will make any measurements made with it meaningless. A
low capacitance FET probe with a ground connection directly connected to the shield at the tip will be required. A
IGHz bandwidth scope will be barely adequate, try to find
a faster unit.

601

602

•

ICS2572

Integrated
Circuit
Systems, Inc.

Advance Information

User-Programmable Dual High-Performance Clock Generator
Description

Features

The ICS2572 is a dual-PLL (phase-locked loop) clock generator with differential video outputs specifically designed
for high-resolution, high-refresh rate, video applications.
The video PLL generates any of 16 pre-programmed frequencies through selection of the address lines FSO-FS3.
Similarly, the auxiliary PLL can generate anyone of four
pre-programmed frequencies via the MSO & MSllines.

•

A unique feature of the ICS2572 is the ability to redefine
frequency selections after power-up. This permits complete
set-up ofthe frequency table upon system initialization.

•
•
•
•
•
•

Advanced ICS monolithic phase-locked loop
technology
Supports high-resolution graphics - differential CLK
output to 185 MHz
Divided dotclock output (WAD) available
Simplified device programming
Sixteen selectable VCLK frequencies (all user reprogrammable)
Four selectable MCLKfrequencies (all user reprogrammable)
Windows NT compatible

Applications
•
•

High end PCllow end workstation graphics designs
requiring differential output
X Terminal graphics

Block Diagram
XTALl
LOAD

XTAL2

CLK+
CLK-

MCLK PLL (as above)
STROBE
FSO
FSl
FS2
FS3
MSO
MSl

VCLK Set &
Program
Mode
Interface

MCLK

MCLKSet

--L_ _ _- '

603

II

ICS2572
Pin Configuration
XTALl

20

VDD

XTAL2

2

19

CLK+

EXTFREQ

3

18

CLK-

FSO

4

17

VSS

FSI

5

16

LOAD

STROBE

6

IS

VAA

FS2

7

14

VSS

FS3

8

13

VDD

MSO

9

12

MCLK

VSS

10

11

MSI

Pin Descriptions
PIN NUMBER
I
2
3
4

5
7
8
6
9
11
19
18
16
12
17
10,14
13,20
IS

PIN NAME
XTALl
XTAL2
EXTFREQ
FSO
FSI
FS2
FS3
STROBE
MSO
MSI
CLK+
CLKLOAD
MCLK
RESERVED
VSS
VDD
VAA

TYPE
A
A
I
I
I
I
I
I
I
I

,

0
0
0
0

P
P
P

DESCRIPTION
Quartz crystal connection lIReference Frequency Input.
Quartz crystal connection 2.
External Frequency Input
VCLK PLL Frequency Select LSB.
VCLK PLL Frequency Select Bit.
VCLK PLL Frequency Select Bit.
VCLK PLL Frequency Select MSB.
Control for Latch ofVCLK Select Bits (FSO-FS3).
MCLK PLL Frequency Select LSB.
MCLK PLL Frequency Select MSB.
Pixel Clock Output (not-inverted)
Pixel Clock Output {inverted)
Divided Dotc1ock (14,5, or 8)
MCLK Frequency Output
Must Be Connected to VSS.
Device Ground. All pins must be connected.
Output Stage V dd. All pins must be connected.
Synthesizer V dd.

604

ICS2572
Digital Inputs
The FSO-FS3 pins and the STROBE pin are used to select
the desired operating frequency of the VCLK output from
the 16 pre-programmed I user-programmed selections in
the ICS2S72. These pins are also used to load new frequency data into the registers.
Available configurations for the STROBE input include:
positive-edge triggered, negative-edge triggered, high-level
transparent, and low-level transparent (see Ordering Information).

VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the
appropriate data to the ICS2S72 FS inputs. Do not perform
any further writes to the device for 50 milliseconds (assumes
a 14.318 MHz reference). The synthesizer will output the
new frequency programmed into that location after a brief
delay (see timeout specifications).

MCLK Output Frequency Selection
The MSO-MSI pins are used to directly select the desired
operating frequency of the MCLK output from the four
pre-programmed/user-programmed selections in the
ICS2S72. These inputs are not latched, nor are they involved with memory programming operations.

Programming Mode Selection
A programming sequence is defined as a period of at least
50 milliseconds of no data writes to the ICS2572 (to clear
the shift register) followed by a series of data writes (as
shown here):

60S

FSO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

FSI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

FS2
START bit (must be ''0'')

"
RIW* control

"
LO (location LSB)
"
L1
"
L2
"
L3
"
IA (location MSB)
"
NO (feedback LSB)
"
Nl
"
N2
"
N3
"
N4
"
N5
"
N6
"
N7 (feedback MSB) .
"
EXTFREQ bit (selected if "1 '')
"
DO (post-divider LSB)
"
Dl (post-divider MSB)
"

STOPI bit (must be "1"
"
STOP2 bit (must be "1 '')
"

FS3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ICS2572
Observe that the internal shift register is "clocked" by a
transition of FS3 data from "0" to "1 ". If an extended sequence of register loading is to be performed (such as a
power-on initialization sequence). note that it is not necessary to implement the 50 millisecond delay between them.
Simply repeat the sequence above as many times as desired.
Writes to the FS port will not be treated as frequency select
data until up to 50 milliseconds have transpired since the last
write. Note that FSO and FSI inputs are "don't care."

D[1-0]
00
01
10
11

POST-DIVIDER
9
4
2
1

ReadlWrite* Control Bit

Data Description
Location Bits (LO-L4)

The first five bits after the start bit control the frequency
location to be re-programmed according to this table. The
rightmost bit (the LSB) of the five shown in each selection
of the table is the first one sent.

Table 1 - Location Bit Programming
Lr4-01
01100
01101
01110
01111
10010
10011

Table 2 - Post-Divider Programming

LOCATION
VCLK Address 12
VCLK Address 13
VCLK Address 14
VCLK Address 15
MCLK Address 2
MCLK Address 3

Feedback Set Bits (NO-N7)

These bits control the feedback divider setting for the location specified. The modulus of the feedback divider will be
equal to the value ofthese bits + 257. The least significant
bit (NO) is sent first.

When set to a "0", the ICS2572 shift register will transfer its
contents to the selected memory register at the completion
of the programming sequence outlined above.
When this bit is a "1 ", the selected memory location will be
transferred to the shift register to permit a subsequent
readback of data. No modification of device memory will be
performed.
To readback any location of memory, perform a "dummy"
write of data (complete with start and stop bits) to that
location but set the RIW* control bit (make it "1'). At the
end of the sequence (i.e. after the stop bits have been
"clocked"), "clocking" of the FS3 input 11 more times will
output the data bits only in the same seq uence as above on
the FSOpin.
EXTFREQ Input

The EXTFREQ input allows an externally generated frequency to be routed to the VCLK output pin under device
programming control. If the EXTFREQ bit is set (logic "1 ')
at the selected address location (VCLK addresses onl)') , the
frequency applied to the EXTFREQ input will be routed to
the VCLK output.

Post-Divider Set Bits (00-01)

These bits control the post-divider setting for the location
specified according to this table. The least significant bit
(DO) is sent first.

606

II

ICS2572

Frequency Synthesizer Description
Refer to Figure 1 for a block diagram of the ICS2572.
The ICS2572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is
a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequencyprovided to the PLL. The phase-frequency detector
shown in the block diagram drives the VCO to a frequency
that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs
when:

FVCO= FXTAL1*

~

The VCO will then need to be programmed to two times
45.723 MHz, or 91.446 MHz. To calculate the required
feedback divider modulus we divide the VCO frequency by
the reference frequency and multiply by the reference divider:

91.446 *43- 27462
14.31818
.
which we round off to 275. The exact output frequency will
be:

211 *14.31818*1

= 45.784 MHz

The value of the N programming bits may be calculated by
subtracting 257 from the desired feedback divider modulus.
Thus, the N value will be set to 18 (275-257) or 000100102.
The D bit programming is 102 (from Table 2).

where N is the effective modulus of the feedback divider
chain and R is the modulus ofthe reference divider chain.
The feedback divider on the ICS2572 may be set to any
integer value from 257 to 512. This is done by the setting of
the NO-N7 bits. The standard reference divider on the
ICS2572 is fixed to a value of43 (this maybe setto a different
value via ROM programming; contact factory). The
ICS2572 is equipped with a post-divider and multiplexer
that allows the output frequency range to be scaled down
from that ofthe VCO by a factor of 2,4, or 8.
Therefore, the YC.Q frequency range will be from 5.976 to
11.906 (257/43 to 512143) of the reference frequency. The
QlIlpJJ1 frequency range will be from 0.747 to 11.906 times
the reference frequency. Worst case accuracy for any desired frequency within that range will be 0.2%.
If a 14.31818 MHz reference is used, the output frequency
range would be from 10.697 MHz to l70.486 MHz.

Programming Example

LOAD Frequency Selection
The LOAD (or divided dotclock) output frequency will be
the CLK+ /CLK- frequency divided by 1, 4, 5, or 8. The
choice of modulus is a factory option, and is specified along
with the ROM frequencies in the VCLK and MCLK tables
by way of the two-digit suffix ofthe part number.

Reference Oscillator & Crystal
Selection
The ICS2572 has on-board circuitry to implement a Pierce
oscillator with the addition of only one external component,
a quartz crystal. Pierce oscillators operate the crystal in
parallel-resonant (also called anti-resonant mode. See the
AC Characteristics for the effective capacitive loading to
specify when ordering crystals.

Suppose that we want differential CLK output to be 45.723
MHz. We will assume the reference frequency to be
14.31818 MHz.
The VCO frequency range will be 85.565 MHz to 170.486
MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will need
to set the post-divider to two to get an output of 45.723 MHz.

607

Crystals characterized for their series-resonant frequency
may also be used with the ICS2572. Be aware that the
oscillation frequency in circuit will be slightly higher than
the frequency that is stamped on the can (typically 0.0250.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend that
the crystal be mounted as closely as possible to the package.
A void routing digital signals or the ICS2572 outputs underneath or near these traces. It is also desirable to ground the
crystal can to the ground plane, if possible.

II

ICS2572
External Reference Sources
An external frequency source may be used as the reference
for the VCLK and MCLK PLLs. To implement this. simply
connect the reference frequency source to the XTALI pin
of the ICS2572. For best results, insure that the clock edges
are as clean and fast as possible and that the input voltage
thresholds are not violated.

Power Supply
The ICS2572 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as
close to the package as is possible.
The ICS2572 has a VDD pin which is the supply of + 5 volt
power to all output stages. This pin should be connected to
the power plane (or bus) using standard high-frequency
decoupling practice. That is, use low-capacitors should
have low series inductance and be mounted close to the
ICS2572.
The VAApin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend
that RC decoupling or zener regulation be provided for this
pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects.

608

ICS2572
Absolute Maximum Ratings
Supply voltage ............................... -.5V to + 7V
Logic inputs ................................. -.5V to VDD + .5V
Ambient operating temp ...................... 0 to 70°C
Storage temperature ......................... -85 to + 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

DC Characteristics
PARAMETER
TTL-Compatible Inputs
(FSO-3, MSO-I, STROBE):
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
XTAL1:
Input High Voltage
Input Low Voltage
CLK+ /CLK- Output
Sink Current
High Voltage (Other
Outputs)
@Ioh= O.4mA
Low Voltage (Other
OutjJuts)
@Iol= 8.0mA

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Vlh
Vii
Ilh
II)
ClIl

2.0
VSS-0.5

VDD+ 0.5
0.8
10
200
8

V
V
uA
uA
pF

Vxh
Vx1
Isink

VDD*0.75
VSS-0.5

VDD+ 0.5
VDD*0.25

V
V
rnA

Voh

4

Vol

V

0.4

609

V

ICS2572
AC Characteristics
PARAMETER
Phase-Locked Loop:
VCLK, MCLK VCO
Frequency
PLL Acquire Time
Crystal Oscillator
Crystal Frequency
Range
Parallel Loading
Capacitance
XTALl Minimum
High Time
XTAL1 Minimum Low
Time
Power Supplies:
VDD SupplvCurrent
VAA Supply Current
Digital Outputs:
CLK+ ICLK- Recommended Termination
Other Outputs Rise
Time @ Cload= 20pf
Other Outputs Fall
Time @ Cload= 20pf

SYMBOL

TEST CONDITIONS

Fvco

MIN

TYP

100

Tlock

MAX

UNITS

235

MHz

500

Fxtal

5

uSec
25

20

MHz
pF

Txhi

8

nSec

Txlo

8

nSec

idd
Iaa
50
Tf
Tf

35
10

rnA
rnA

2

ohms

2

nSec
nSec

610

(I

ICS2572

Ordering Information:
ICS2572N-SXX (0.300" DIP Package)
ICS2572M-SXX (0.300" SOIC Package)
where:
"s" denotes strobe option:
"xx" denotes default frequencies:

PATTERN
Reference Divider
VCLKADDR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MCLKADDR
0
1
2
3

A - positive level transparent (i.e., 2494 interface compatible)
B - negative level transparent
C - positive edge triggered
D - negative edge triggered

ICS2572-01
43
FbkDiv/PostDiv - FVCLK(MHz)
300/1- 99.89
37811 - 125.87
27711 - 92.24
432/4 - 35.96
302/2 - 50.28
340/2 - 56.61
EXTFREQ270/2 - 44.95
40511 - 134.86
384/4 - 31.97
330/1 - 109.88
481/2 - 80.08
479/4 - 39.87
270/2 - 44.95
450/2 - 74.92
390/2 - 64.93
FbkDivlPostDiv- FMCT.K
481/4 - 40.04
270/2 - 44.95
39614 - 32.97
300/2 - 49.95

611

612

les
Power Management
Products

In 1991 ICS introduced first silicon on its QuickSaver™ Controller using voltage inflection termination and ReFLEX® charging to fast charge Nickel Cadmium batteries. Today ICS unveils the next
generation - QuickSaverTMJI Controller - for fast and quick charging of Nickel Cadmium and Nickel
Hydride batteries.
The QuickSaverTMJI Controller family uses more sophisticated mixed-signal building blocks to bring
cost-effectively the real value of inflection voltage termination and reverse pulse conditioning charge
to your designs.
ICS has also introduced a line of load management switches. These switches provide glitch-free
handling of the power management shut-down function in the PC environment.

ReFLEX

IS

a regIstered trademark ofChflstle Electnc CorporatIOn.

613

les Power Management Products
Selection Guide
Product
Application

ICS
Device Type
ICS1700

Ni-Cd Battery Charge
Processor

Maximum
Charge Rate

Package
Types

Page

4C

I NOTFORRECOMMENDED
I
NEW DESIGN

Integrated Battery
Charge Maintenance
Controller.

16 PinDIP
20 Pin
615
SOIC

Integrated Battery
Charge Maintenance
Controller.

4C

ICS1700A

16 PinDIP
20 Pin
617
SOIC

Enhanced Feature
Integrated Battery ChargeMaintenance Control.

4C

16 Pin DIP
20 Pin
SOIC

SmartBat™ In-the-Pack Data
Acquisition and Storage
IC for Charge Control and
Capacity Measurement.

N/A

Quad High-Side Switches

N/A

Ni-Cd Battery Charge Processor
NiMH Battery Charge Processor

ICS1702

Battery Charging and Capacity
Measurement IC

ICS1705

AV9304/9504
Notebook PCs and PDAs
Power Switching

Features

300mQ RDS On Slow
Turn-on for glitch-free
Operation.
AV9312/9512

Dual High-Side Switches
200mQ RDS On Slow
Turn-on for glitch-free
Operation.

N/A

8 Pin
SOIC

16 Pin DIP
16 Pin
SOIC
16 Pin DIP
16 Pin
SOIC

633

653

655

659

Note: C=Ampere/hour capacity of battery.
SmartBat is a trademark of Integrated Circuit Systems, Inc.

Integrated Circuit Systems, Inc. (ICS) shall be held harmless for any misapplication of this device such as: exceeding the rated
specifications of the battery manufacturer; charging batteries other than nickel-cadmium and/or nickel metal hydride type;
personal or product damage caused by the charging device, circuit, or system itself; unsafe use, application, and/or manufacture
of a charging system using this device.

ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data
and other specifications are subject to change without notice.

PRODUCT PREVIEW documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

614

ICS1700

Integrated
Grcuit
Systems, Inc.

Data Sheet

QuickSaver™ Controller For Nickel-Cadmium Batteries
Features

Applications

• A ReFLEX® charging system (I)
• Capable of full charge in 20 minutes*
• Pulsed maintenance mode charge - keeps batteries
primed at peak capacity
• Employs sophisticated multiple charge termination
methods - as recommended by battery producers
• Reduces internal cell heating
• Reduces internal cell pressure

• AC or DC powered NiCd Battery Chargers

•
•

•
•

r~~I.t.~lVt'il:iI!.8~SI device using

•
•
•

e
the intelligent
This device uses the
e
harging and time-derivaM;;_~~~~erccombination of these two
afe charging of nickel-cadmium
20 minutes. *
~~~rjltllIlollllllqJi

LED OUll'UTS
pins 3, 4, 5

f----

CHARGE
CONTROL
pin 1

DISCHARGE
CONTROL

pin 2

IT >------1
EXTERNAL
VOLTAGE
REFERENCE
pin 13

-----+

+---..,+

Short CircUit
Detect

"-------1+

HI Impedance
and Open
Circuit Detect

L-------1

Pm numbers shown are for DIP package

* A 20mmuf!j charge assumes a chargIng rate of4C. NOT ALL BATTERIES ARE CAPABLE OF ACCEPTING A 4C CHARGE RATE.
(I) ReFLEX IS the regIstered trademark of ChrISlie ElectrIc CorporatIOn.
REV2J25J93

615

616

ICS1700A

Integrated
Circuit
Systems, Inc.

•

Advance Information

QuickSaverll™ Controller for Nickel-Cadmium Batteries
General Description

Features

The ICS1700A QuickSaverII device is a CMOS monolithic
integrated circuit that supervises and controls the charge
and charge termination of rechargeable Nickel-cadmium
batteries. The ICS1700A is a pin-for-pin, functionally compatible replacement device for the original QuickSaver controller ICS1700. The ICS1700A employs voltage
termination of the fast charge cycle and reverse pulse charging for battery conditioning in all charge stages.

•
•
•
•
•

Applications
•
•
•
•
•
•

AC or DC powered NiCd Battery Chargers
Notebook and laptop personal computers
Portable co=unications equipment
Portable video and audio equipment
Portable point-of-sale equipment
Portable power tools

•
•
•
•
•
•
•
•

A QSIITMcharging system
Capable of full charge in 15 minutes!
Pulse maintenance mode charge - keeps batteries
primed at peak capacity
Accepts a thermal switch or thermistor input
Four stage charge
Soft start
Fast
Topping
Maintenance
Polling mode auto-reset
Employs several charge termination methods as reco=ended by battery producers
Reduces internal cell heating
Reduces internal cell pressure
LED drivers for charge status, over temperature and
some fault conditions
Multiple charge rate capability
Microprocessor-based with internal ROM
Internal safety timer protects against damaging over
overcharge

Block Diagram

Pin Configuration

RC INPUT-------l

~~g~-------------,
~~~-------------,

LED
OUTPUTS
CHARGE

CHG
OCHG
PFN
CMN
OTN
SO
VSS
AVSS

VOO
TEST
VIN
VREF
THERM
RC
MRN
Sl

DISCHARGE

Ordering Infonnation
TH~~~

ICS1700AN
(DIP 16 Pin Package)
ICS1700AM
(SOlC 20 Pin Package)

-------------1

lies maka. no claim about fl. capability of any battery to accept. fnt charge. ICS strongly recommends that the battery manufacturer be consulted before fast charging.

617

ICS1700A
Table 1: Pin Definitions
PIN
NUMBER
(DIP)

PIN
NUMBER
(SO)

PIN
NAME

TYPE

DEFINITION

1

1

CRG

OUT

Active high TTL compatible signal turns on external current source
providing current to charge battery.

2

2

DCRG

OUT

Active high TTL compatible signal turns on external current sink.

3

3

PFN

OUT

Auto polling and fault indicator. An active low turns on an external
indicator to show the device is either polling for a battery or has
detected a fault condition.

4

5

CMN

OUT

Charge Mode. An active low turns on external LED, indicating the
state of the charge cycle. Continuous low indicates charge in
progress, \\hile an alternating low/high indicates maintenance mode.

5

7

OTN

OUT

Over temperature indicator. An active low turns on an external
indicator to show the temperature of the battery is too hot to charge.

6

8

SO

IN

Select O. Used with S 1 signal to program the device for the desired
charge rate.

7

9

Logic ground.

10

Vss
LVss

PWR

8

PWR

Ground pin for output indicator (LED) drivers.

9

11

SI

IN

10

12

MRN

IN

Master RESET signal initiates the charge sequence.

11

13

RC

IN

Resistor/Capacitor pin sets the frequency of the internal clock.

12

14

TRERM

IN

Thermistor or thermal switch input. An internal resistor string
establishes the voltage thresholds for hot or cold temperature
sensing.

13

16

14

18

VREF
VIN

IN

Batteryvoltage normalized to one cell with external resistor divider.

15

19

TEST

IN

Active high on this pin activates factory test mode. Tie to V ss.

16

20

VDD

PWR

Select 1. U sed with the SO signal to program the device for the
desired charge rate.

No connect.

+ 5 volt supply.

Pins 4, 6,15, and 17 are ''No Connects" in the SO package.

618

ICS1700A
Pin Descriptions

The polling detect (PFN) indicator is on when the ICS1700A
polls for a battery or a battery fault occurs. The indicator is
a warning that charge pulses are appearing at the charging
system terminals at regular intervals. When a battery is
found, the indicator is deactivated.

The ICS1700A requires some external components to control the clock rate, sense temperature and provide an indicator display. The chip must be interfaced to an external
power source that will provide the constant current required
to charge a battery pack as well as a circuit that will sink a
negative current discharge pulse.

The over temperature (OTN) indicator is active whenever
the voltage at the temperature sense input falls into a range
that indicates to the ICS1700A that the attached battery may
be too hot to charge. The OTN indicator is also activated
with the MMN indicator if the battery is initialized in the
cold temperature charge region. The OTN indicator will
also activate if the battery becomes cold while a charge is in
progress.

The ICS1700A does not control the amount of current
flowing into the battery in any way other than turning it on
and off. The required current for the selected charge rate
must be provided by the user's power source. The external
charging circuitry must provide a constant current at the
selected charge rate. For example, to charge a 1.2 ampere
hour battery at a 30 minute (2C) rate, requires approximately 2.4 amperes of current.

Charge Rate Selection: SO, Sl Pins
The SO and SI signals must be progra=ed by the user to
inform the ICS1700A ofthe desired charge rate. Since the
signals have an internal l00KO pull-up, no connection to
VDD is required to program a high level. When a low level
is desired, the pin should be grounded. A high impedance
condition may be accomplished through a resistor divider.
The voltage ranges for logic low, high impedance and logic
high are detailed in Table 7 Logic Signals. To program the
SO and 81 signals, refer to the Charge Rate List in Table 2.

Output Logic Signals: CHG,DCHG Pins
The CRG and DCRG signals are active high, TTL compatible signals. In addition to being TTL compatible, the
CMOS outputs are capable of sourcing current which adds
flexibility when interfacing to other circuitry. A logic high on
the CRG signal indicates that the constant current supply
should be activated. A logic high on the DCRG signal
indicates that the discharger should be activated.
Care must be taken to control wiring resistance, and the load
resistor must be capable of handling this short-duration
high-amplitude pulse. If the deep discharge-to-charge mode
is selected, the power dissipation of the load resistor must
be properly selected to accept the extended length of the
discharge pulse.

II

Indicators: CMN, PFN, OTN Pins
Indicators can be connected to the device to display the
charge mode and any fault conditions. The device has four
outputs for driving external indicators. These pins are active
low. The four indicator outputs have open drains and are
designed to be used with LEDs. Each output can sink over
20 rnA which requires the use of an external current limiting
resistor. The four indicator signals denote fast charge
mode, maintenance mode, polling detect mode and out of
temperature range condition.
The charge mode (CMN) indicator is activated continuously
during the soft start and pulsed fast charge modes. When
the controller enters the dual phase maintenance mode, the
signal is turned off.

619

II

ICS1700A
Table 2: Charge Rate List
Topping
Charge P¥lse
Period

Maintenance Charge
Pulse Period2

Timer

SO

Sl

Charge
Rate

L

L

4C

15 min (114 hr)

40 sec

160 sec

lS.75 min

L

H

2C

30 min (lllhr)

20 sec

SO sec

37.0Smin

Charge Time

H

L

1C

60 min (1 hr)

10 sec

40 sec

7250 min

H

H

CIl

120 min (2hr)

5 sec

20 sec

141.60 min

lporiod meanl tho tim.. botween pulac ••

Master Reset: MRN Pin
The MRN pin is provided to re-program the chip for a new
mode or charging sequence. An internal debounce circuit
protects against spikes on the line lasting less than 100 ms.
This pin has an internal pull-up of 100Kn. A logic low on
the MRN pin must be present for more than 300 ms for a
reset to occur. A master reset is required to clear an over
temperature condition, clear the device self test or to change
charge rates or modes.

For NiCd and NiMH cells, charging should be prevented
below 10DC and above 45 DC. At 10DC, the resistance of the
specified thermistor is nominally 17.96 Kn. At 45OC, the
resistance drops to 4749 O. The ICS1700A has a voltage
threshold for the low temperature (IOOC) at 2.4 V, and a
voltage threshold for the high temperature (45OC) at 0.9S V
All voltages are referred to VDD = 5 V. Using a resistor
divider with 10 KO for the thermistor and a 24 KO fixed
resistance, the divider looks like Figure I at 25OC:

Clock Input: R C Pin
The RC pin is used to setthe frequency on the internal clock.
A 16 KO resistor is connected between this pin and VDD.
A 100 pF capacitor is connected between this pin and
ground. The frequency of the internal clock is I MHz.

VDD

Temperature Sensing: THERM Pin
The THERM pin requires some thought if a thermistor is
going to be used for hot and cold temperature termination.
The input impedance of the THERM pin is about 10M
typically. The example below works for a 10K @ 250C
thermistor such as the Semitec USA (Ishizuka Electronics
Corp.) part # ATl03-2. TheICS1700AhasalOOKOpull-up
internal to the pin.

10 K

Figure 1: Voltage divider atTHERM pin

620

ICS1700A
The voltage at the THERM pin should be about 1.67V at
2SOC. Thble 4 contains the voltage thresholds and the corresponding temperatures. A short circuit thermal switch
threshold of about O.ISV at the THERM pin is available
when either an open circuit thermal switch or no temperature sense device is used. If a voltage is below the short
circuit thermal switch threshold, the ICS1700A assumes the
thermal switch is closed to ground and the part is allowed to
operate. When the thermal switch opens at high temperature, the pull-up raises the voltage above the high temperature voltage threshold, and the part shuts down. If no
temperature sense device is used, the THERM pin must be
grounded. The short circuit voltage corresponds to a thermistor temperature of about IS0°C.

Voltage Input: VIN Pin
The normalized battery voltage is connected to the voltage
input (VIN) pin. The input impedance of the VIN pin is
about 1 MO typically. The battery voltage must be normalized through a resistor divider network to one cell. For
example, if the battery consists of six cells in a series, the
voltage at the VIN pin must be equal to the total battery
voltage divided by six. This can be accomplished with two
external resistors. To determine the correct resistor values,
count the number of cells to be charged in series. Then
choose either Rl or R2 and solve for the other resistor using:
Rl

= R2 x (# of cells-I) or R2 = RlI (# of cells -1)

VDD

VIN pin

# of cells ::-

normally closed thermal switch
opens at 45°C

Figure 2: Thermal swtch to
connection to ground at the
THERMpin

Table 4: Temperature Threshold List
Voltage

Thermistor
Temperature

Open Circuit Thermal
Switch Voltage

4.2

-2SOC

Cold Temperature
Thermistor Voltage
Hot Temperature
Thermistor Voltage
Short Circuit Thermal
Switch Voltage

2.4

100C

0.98

4SOC

0.IS0

IS0°C

Parameter

~
Figure 3: Resistor divider netvwrk at
the VlN pin
Power: VDD Pin
The device power supply is connected to the VDD pin. The
voltage should be + S VDC and maybe supplied to the part
through a regulator which can handle periodic current demands. See Table 6, DC Characteristics for more information.

Grounding: VSS,AVSS Pins
There are two ground pins. One pin is used to return the
current that the indicator drivers must sink and to handle
the internal digital logic. This pin is labeled VSS and should
have a direct connection to a solid ground point to avoid
inducing ground bounce in the AVSS ground. The AVSS
ground connects to the internal analog circuitry. The AVSS
pin should also have a direct connection to a solid ground
point. Care must be taken to maintain the same potential at
both the VSS and AVSS ground point connections.

621

II

ICS1700A
Data Tables
Table 5: Absolute Maximum Ratings
Supply Voltage
Logic Input Levels

65
-05 to VDD + O.S

V

Oto70
-SS to ISO

"C
"C

Ambient Operating Temperature
Storage Temperature

V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at the Absolute Maximum Ratings or other conditions not consistent with
the characteristics shown in this document is not reco=ended. Exposure to absolute maximum rating condition for
extended periods may affect product reliability.

Table 6: DC Characteristics
VDD=S.OV; Tamb=25°C
PARAMETER
Supply Voltage
Supply Current, Static
Supply Current, Dynamic

SYMBOL TEST CONDITIONS
VDD

MAX

45

s.o

55

UNITS
V
rnA

2.46

V

0

V

8192 clocks (13 bits)

300

IlV

IDDd
VBG= 1.23V

Lower AID Converter Range
AfD Resolution

TYP
S
10

IDDs

Upper AID Converter Range

MIN

rnA

High level Source Current, Pull-up

Ipu

VGs=SV

SO

IlA

Low Level Sink Current, Pulldown
High level Source Current,
ChargefDischarge Pins
Low Level Sink Current,
ChargefDischarge Pins

IpD

VGs=SV

SO

IlA

Low Level Sink Current,
Indicator Pins
Input Impedance, VIN pin

IHCD

VGs=SV, VT=0.9SV

43.3

rnA

ILCD

VGs=SV, VT=0.7V

91.0

rnA

ILL

VGS= SV, VT=0.7V

122

rnA

1.0

Mn

ZVIN

622

II

ICS1700A
Table 7: Logic Signals
PARAMETER

SYMBOL TEST CONDITIONS

MIN

High Level Input Voltage

VIR

35

Low Level Input Voltage

VIL

High Level Output Voltage

VOH

IOH= 2.0 rnA
Voo=MIN

0.8
2.4

Low Level Output Voltage

VOL

IOL= 2.0 rnA
Voo=MIN

Low Level Output Voltage.
Indica tor Pins

VLL

IOL= lOrnA

0.102

TYP

MAX

UNITS

0.84

0.89

V
V

0.4

V

0.109

0.115

V

TYP

MAX

UNITS

V

Table 8: Timing Characteristics
PARAMETER
Clock Frequency

SYMBOL TEST CONDITIONS
fCLK

ResetlThermal Switch Debounce

MIN

R= 16KW. C= 100pF

1.0

fCLK= 1.0 MHz

300

MHz
ms

Charge Pulse Width

tcpw

fCLK = 1.0 MHz

1048

IDS

Discharge Pulse Width

topw

fCLK= 1.0MHK

5

ms

fCLK= 1.0 MHz

4

ms

fCLK= 1.0 MHz

16.38

ms

Cycle Time

tAOC
tc)"!_

fCLK= 1.0 MHz

1077

ms

Capacitor Discharge Pulse Width

tcow

fCLK= 1.0 MHz

5

ms

Capacitor Discharge Pulse Period

fCLK= 1.0 MHz

100

ms

Polling Detect Pulse Width

tco
tpow

fCLK= 1.0 MHz

100

IDS

Polling Detect Pulse Period

tpo

fCLK= 1.0 MHz

524

ms

Topping Charge Length

tTc

fCLK= 1.0 MHz

2.096

hrs

fCLK= 1.0 MHz

4.19

s

fCLK= 1.0 MHz

4.19

s

Settling Time
ADC Acquisition Time

Maintenance Mode Sample Delay
Maintenance Mode Voltage
Sample Period

Table 9: Voltage Thresholds
PARAMETER
Maintenance Mode Removal
Voltage Drop

SYMBOL TEST CONDITIONS
V_
rm

MIN

TYP

MAX

UNITS

0.2

V
mV

Temperature Voltage Difference

THERM

15.9

Thermal Switch Open Circuit

THERM

4.2

V

Thermal Switch Short Circuit

THERM

0.15

V

Cold Thermistor

2.4

V

Hot Thermistor

0.98

V

0.2

V

Capacitor Discharge Short Circuit

Vsc

623

II

II

ICS1700A

Current
(not to scale)

tI

Soft Start

I

Stage 1

Rapid Charge

I

Topping Charge

Maintenance Charge

Stage 3

Stage 2

Stage 4

Figure 4: Graphical representation of current levels during
the four charging stages
Soft Start Charge

Operation
Charging Stages
The charging sequence consists offour stages. The application of current can be shown graphically in Figure 4. Soft
start charge gradually increases current levels up to the user
specified fast charge levels during the first few minutes of
charge.
The soft start is followed by a high current charge that
includes a deep, reverse polarity pulse of short duration,
which continues until termination. After termination, a two
hour CliO topping charge followed by a C/40 maintenance
charge is applied. Each ofthese four stages is described next
in more detail.

I:.

1<*
Discharge pulse width

lIoE<~_______ delay time -------.-.:*~- t cycle ----7J
-.J

Figure 6: Represen1a1ive 1iming diagram for 'lopping and maintenance charges

625

II

ICS1700A

The slope changes its profile sharply in response to small
perturbations in the cell voltage. The slope will reach a
maximum just before the actual peak in the cell voltage, as
shown in the figure. By calculating a relation between the
minimum slope and an empirically derived threshold, the
ICS1700A can predict the moment of full charge and accurately terminate the applied current before the battery begins to overcharge.

Maintenance Charge
The maintenance charge is intended to offset the natural
self-discharge ofNiCd batteries by keeping the cells primed
at peak charge. When the topping charge mode is completed, the ICS1700A begins the fourth charge stage by
extending the duty cycle of the applied current pulses again.
The current pulses are decreased to a C/40 rate which will
last for as long as a battery voltage is present at the voltage
input (VIN) pin, or, if the ten hour timer mode is enabled,
until the timer stops the controller. The maintenance mode
indicator MMN is the only indicator active during this mode.

Negative Voltage Slope Tennination (-dVldt)
Cells that are charged at low charge rates, or those cells
which are not thoroughly conditioned, or are possessing an
unusual cell construction may not have a normal voltage
profile. The ICS1700A also uses an alternate method of
charge termination based on a slight decrease in the voltage
slope to stop charge to cells whose voltage profile is very
shallow. The negative slope method looks for a flattening of
the voltage slope which may indicate a shallow peak in the
voltage profile, and enters the maintenance mode if the
slope is less than zero for three successive samples. The zero
slope point occurs slightly beyond the peak voltage and is
shown on the voltage curve graph.

Charge Termination Methods
Several charge termination schemes, including voltage inflection (dVldt) , negative voltage slope (-elVldt) , maximum
voltage (V max) ,maximum temperature (T max) and two overall charge timers are available for use during fast charge.
The voltage inflection and negative voltage slope methods
may be used with or without the temperature slope and the
maximum temperature method. Maximum temperature,
maximum voltage and the fast charge timer are always enabled as backup methods. Ifvoltage termination is used, an
initial voltage slope check is performed to detect fully
charged cells.

Maximum Voltage Tennination

Voltage Inflection Tennination (dVldt)
The most distinctive point on the voltage curve of a charging
battery in response to a constant current is the peak in the
voltage curve that occurs as the cell transitions from charge
to overcharge. The voltage peak is characterized by a relatively shallow voltage slope that becomes sharply steeper,
flattens out and drops sharply negative. By mathematically
calculating the first derivative (dVIdt) of the voltage, a second curve can be generated showing the change in voltage
with respect to time, as shown in Figure 7.

(VmaJJ
Through the use of an internal bandgap reference set at
1.23VDC, the ICS1700A uses two comparators in front of
the analog-to-digital converter to determine the presence of
a battery. Provided that the system designer has maintained
a 2.0V Icell terminal voltage, the chip will terminate the
charge when it detects an open circuit voltage above
2.0V Icell. (Maximum voltage should not be used as the only
charge term ination method, especially when fast charging any
batteryf)

626

II

ICS1700A
1.8

0.0020
Termination Point----~Ji-I-....

1.7

0.0015

Inflection Point _ _ _ _---',.,

t

1.6

:i"
0.0010

)-

!
::lj!
'"

i!

1.5

II

~

E"

0.0005

!.

..!!
UI

1.4
Slope Curve

0.0000
1.3

1.2

0

1000

2000

3000

4000

5000

-0.0005

TIme (seconds)

Figure 7: Voltage and slope curves vs. charge 'time
Maximum Temperature Tennination (TmaJJ
Maximum temperature can be sensed using either a thermistor or a thermal switch. The maximum temperature termination can also be bypassed ifdesired, although it is strongly
reco=ended that some form of temperature termination
be used. The hardware used to sense maximum temperature levels is always enabled, and can only be disabled by
shorting the temperature sense pin (THERM) to ground.
Maximum temperature termination cannot be disabled if
temperature slope termination is used.

Ifa thermistor is used, the ICS1700Ahas two voltage thresholds which sense whether the battery is too hot or too cold
to charge. The thresholds are designed for a typical 10 KO
@ 25°e NTe thermistor. These voltage levels are sensed
across the thermistor. As temperature increases, the voltage
across the thermistor will drop. At a temperature of 45°e,
the ICS1700Aassumes the battery has gotten hot and charge
is terminated. Refer to Table 4 for voltage indications at
several temperatures.

If a thermal switch is used, a 45°e open circuit switch is
reco=ended. If the switch is closed to ground (signifying
the battery is less than 45°C), the chip will operate since the
voltage at the THERM pin will be at ground. If the switch

opens at 45°C, an internal pull-up will engage and the
ICS1700A will fault to over temperature since the voltage
will be at VDD.

If a battery is determined to be hot, either through an open
thermal switch or a thermistor threshold, the over temperature (OTN) indicator will tum on. The device must be reset
once the over temperature condition has cleared to start the
charge sequence. The appropriate indicators for the particular charge mode will light when the temperature is normal and charging can begin.
The section Mode Selection, Cold Tempemture Charging has
information on the cold temperature region. See the section
under Tempemture Sensing for more information regarding
the use of a thermistor or a thermal switch at the temperature sense pin. Table 4 in that section lists voltages and
corresponding temperatures.

627

ICS1700A
Fast Charge Timer Termination 3
The ICS1700Aalso uses a timer to shut off the fast charge if
the device goes beyond a safe charging time limit. These
times are programmed into the chip, and are listed below in
Table 10. If the device is used at a charge rate other than the
ones allowed, care must be taken to avoid premature termination due to the timer cutoff. This deadman timer cannot
be disabled.
Initial Slope Check
The initial slope check is a test to detect fully charged
batteries before a long term high current charge is applied.
After that period oftime, the initial slope value is calculated
and is tested for a negative value. If the initial slope is
negative, the voltage must be decreasing over the sampling
period and the battery is assumed to be fully charged. The
ICS1700A will then enter the maintenance mode. If the
slope is positive, the ICS1700A stores the slope and continues charging.
This check is always active when voltage slope termination
is enabled.

Table 10: Fast Charge Timer List
Charge Time
(minutes)

Charge Rate

Timer Cutoff
(minutes)

15

4C

18.75

30

2C

37.08

45

1.3C

55.00

60

1C

72.50

90

C/1.5

107.5

120

CI2

141.6

150

CI2.5

209.89

180

CI3

241.90

240

C/4

273.14

Battery Detection and Removal
Polling Detect
The polling/fault detect (PFN) indicator is on when the
ICS1700A is polling for a battery or has shut down due to a
fault condition. When polling, the indicator is a warning that
the charger is still active and that charge pulses are occuring
at the charging system terminals consistent with the user
selected charge rate. The ICS1700A enters this mode by
applying a charge pulse for a 100 ms ('tpd) period. During
the pulse, the ICS1700A monitors the voltage of the input
pin to determine the voltage relative to the open circuit
voltage at the terminals. If a battery is present, its voltage
will be below the open circuit voltage while charge is applied, and a normal charging sequence will begin. If a
battery is not present, the voltage will be at or above the open
circuit voltage reference and the part will eventually shut off.
The 100 ms pulse will recur over a 524 ms ('tpd) period
incorporating 20 individual pulse samples (approximately
10 seconds). After this period, the part will shut down and
must be reset through the master reset (MRN) pin. The
fault indication will occur if a battery is present and a fault
occurs. In that case, the ICS1700A will stop the charging
sequence upon detection of the fault.

Out of Tempera1ure Range
The out of temperature range (OTN) indicator is active
whenever the voltage at the temperature sense input falls
into the range that indicates to the ICS1700A that the attached battery maybe too hotto charge. The OTN indicator
is active also if the battery is cold during the initialization of
charge or becomes cold while charging is in progress. This
condition, while indicated, does not terminate the charge
sequence and is not a fault condition, per se.

3 'II'\tIen the f.1t charge 'Iuner ,hutl off tle fa.t charge operation, the ICS1700A wll go Into mllnlllnance mode charge and 1he maln1anance mode indicator wll b. on at d'I.. 'me.

628

ICS1700A
Application Information
BENEFIT TO USER

FEATURE
Inflection Termination
Reverse Pulse
Auto Polling
Temperature Input
Four Stage Charge
Safety Timers

Reduces internal heat and pressure, and extends the batteries '\lurking" life.
Eliminates the need to discharge before charge; available in all charge modes.
Automatic search for battery presence at the terminals.
Thennistor or thermal smtch high temperature shut down.
Soft start and topping modes in addition to fast and maintenance mode charge.
A failsafe deadman timer.

The ICS1700A is a pin-for-pin compatible version of the
original QuickSaverTlol ICS1700. In this version, ICS has
modified the internal device building blocks to be more
robust. The ICS1700A features a 13 bit delta-sigma analogto-digital converter, (the same converter designed into the
ICS1700A), and a wider data path to improve the data
acquisition aspects of the device.

3) Auto polling at the battery terminals applies a charge
pulse then monitors the voltage input and compares this
to the open circuit voltage to determine if the battery is
present. If the battery has been temporarily removed
and is re-inserted or contact with the battery is broken
momentarily, the charging sequence will re-start automatically.

The ICS1700A includes three new features not found on the
ICSI700.
1) Battery temperature sensing for over temperature
charge termination through a thermistor or a thermal
switch. The present device only accepts a thermal switch
input.
2) Four stage charging that prevents early charge termination when the battery is completely discharged. A twohour ClIO topping mode to ease the battery into 100%
full charge.

629

ICS1700A

II

Application Information
Figure 8 shows a typical application using the ICS1700A. R1
and R2 are selected to scale the battery voltage to 1 cell. The
following table shows some typical values. Additional
information is available under Pin Descriptions- Voltage
Input: VIN Pin.
CELLS

R1

R2

1

Short

Open

2

2K
2K
3K

2K
lK
lK

12K
10K

3K
2K

3
4

5
6

7

12K

2K

8

9.1K

1.3K

It is very important that care be taken to minimize noise
coupling and ground bounce. In addition, wiring resistance
and connectors can add significant amounts of resistance to
the charge and discharge circuits. Be sure to connect the
ground side of the discharge transistor to the negative lead
of the battery as close to the battery as possible. This will
reduce ground bounce and coupled noise.

When designing a printed circuit board, make sure ground
and power traces are heavy and bypass capacitors are used
close to the chip. Use a separate ground system for the
discharge current to prevent high circulating currents from
disturbing normal operation.
A constant current source should be used to provide charging current to the battery. Resistors may be used if the
current does not vary more than 20 %•
Additional application information will be provided in the
final version of the data sheet, and as part of a series of
regular technical updates.

630

les 1700A
Notes: 1)

2)
3)

Negative battery terminal and DC return
should be connected at one point.

4)

A thermal switch or thermistor can be
used with the ICS1700A Refer to the
application note for the equivalent
circuit diagram when using a thermistor.

+V

CONSTANT
CURRENT
SOURCE

Value of resistor determined by
discharge current and capacity of
battery pack:.
Device must be logic level compatible.

CURRENTENMLE

Rl
R2

+IIV
+6V

16K

l00pF

~6'l6
lN4148

~

Figure 8:

Functional Diagram

631

I

632

(I

ICS1702

Integrated
Circuit
Systems, Inc.

Advance Information

QuickSaverll™ Controller for Fast Charge and
Conditioning of NiCd and NiMH Batteries
General Description

Features

The ICS1702 QuickSaver II device is a CMOS monolithic
integrated circuit that supervises and controls the charge
and charge termination of rechargeable Nickel-Cadmium,
and Nickel-Metal Hydride batteries. The ICS1702 employs
voltage and temperature termination methods and pulse
charging for battery conditioning.

•
•
•
•

Applications

•

•
•
•
•
•
•
•
•

AC or DC powered NiCd and/or NiMH battery chargers
Cellular telephone
Portable PC
Remote data acquisition
Two-way radio
Portable video equipment
Portable power tools
Portable audio equipment

•
•
•
•
•
•
•
•
•

Patent pending QS II charge algorithm
Voltage inflection termination
Temperature slope termination
Reverse pulse conditioning
in charge mode
in maintenance mode
in condition mode
Four stage charge
Soft start
Fast
Topping
Maintenance
Fast charging
15 minutes for NiCd 1
1 hour for NiMH 1
7 charge terminations
9 progra=able charge rates
Cold battery condition charge
Hot battery charge fault
Polling mode Auto-Reset
System test through QS II controller
Full condition cycle to 0.8V /cell
Adjustable open circuit reference

Block Diagram

Pin Configuration

RC I N P U T - - - - - j

CHG

~~~~~-------------------.

DCHG

s~~~~----------------------~

MMN

PFN
LED
OUTPUTS
CHARGE

VOLTAGE
SENSE

CMN

DISCHARGE

-+-+-----l

VIN
OPREF
THERM

OTN

AUX1

SO

AUXO

VSS
OPEN
CIRCUIT
REFERENCE

VDD
TEST

AVSS

51

DTSEL
RC
MRN

Ordering Information
ICSI702N (20 Pin DIP Package)
ICSI702M (20 Pin sorc Package)

TH~~~ft --4'----------------------1

Temp. Range = O"C to +70"C

1 1CS makea no claim about the capablhtyofanybattery{NiCd orNIMHI to accept a faatcharg •. ICS atronglyrecommendathatthe battery manufacturer be consulted before faatcharglng.

633

II

ICS1702
Table 1: Pin Definitions
PIN NUMBER

PIN NAME

TYPE

DEFINITION

1

CHG

OUT

2
3

DCHG
PFN

OUT
OUT

4

MMN

OUT

5

CMN

OUT

6

OTN

OUT

7

SO

IN

S
9

VSS
AVSS

PWR
PWR

Active high TTL compatible signal available to tum on an external
current source to provide current to charge the battery.
Active high TTL compatible signal available to tum on a discharge circuit.
Polling detect indicator. An active low turns on an external indicator
to show the device is in the polling detect mode and is polling for the
presence of the battery.
Maintenance mode indicator. An active low turns on an external
indicator showing the battery is in either a topping charge mode,
maintenance mode or a condition mode. This signal is also applied
with the over temperature indicator when the battery is in a cold
charge mode.
Charge mode indicator. An active low turns on an external indicator,
indicating the device is in either a soft start or a fast charge mode.
Out of temperature range indicator. An active low turns on an
external indicator showing the battery to be out of the normal fast
charge temperature range.
Tristate input used with the Sl pin to program the device for the
desired charge rate.
Logic and display indicator ground.
Analog ground.

10

Sl

IN

11
12

MRN
RC

IN

13
14

DTSEL
AUXO

IN
IN
IN

15

AUX1

IN

16

THERM

IN

17

OPREF

IN

18
19
20

VIN
TEST
VDD

IN
nlc
PWR

Tristate input used with the SO pin to program the device for the
desired charge rate.
Master reset signal. A low to high transition initiates a device reset.
A resistor and capacitor sets the frequency of the internal clock.
Selects temperature slope andlor voltage slope termination.
Tristate input used with the AUX1 pin to program the device for a
special charge mode or a device self-test mode.
Tristate input used with the AUXO pin to program the device for a
special charge mode or a device self-test mode.
Thermistor or thermal switch input. An internal resistor string
establishes voltage thresholds for hot or cold temperature sensing.
Open circuit reference. A resistor divider on this pin sets the open
circuit voltage reference used to detect the presence of the battery.
Battery terminal voltage normalized to one cell with a resistor divider.
No Connect (Engineering test mode input).
Device supply = + 5.0 VDC ± 05 Vdc.

634

II

ICS1702

Pin Descriptions
The ICS1702requires some external components to control
the clock rate, sense temperature and provide an indicator
display. The chip must be interfaced to an external power
source that will provide the constant current required to
charge a battery pack as well as a circuit that will sink a
negative current discharge pulse.
The ICS1702 does not control the amount of current flowing
into the battery in any way other than turning it on and off.
The required current for the selected charge rate must be
provided by the user's power source. The external charging
circuitry must provide a constant current at the selected
charge rate. For example, to charge a 1.2 ampere hour
battery at a 30 minute (2C) rate, requires approximately 2.4
amperes of current.

Output Logic Signals: CRG, DCRG Pins
The CHG and DCHG signals are active high, TTL compatible signals. In addition to being TTL compatible, the
CMOS outputs are capable of sourcing current which adds
flexibility when interfacing to other circuitry. A logic high on
the CHG signal indicates that the constant current supply
should be activated. A logic high on the DCHG signal
indicates that the discharger should be activated.
Care must be taken to control wiring resistance, and the load
resistor must be capable of handling this short-duration
high-amplitude pulse. If the deep discharge-to-charge mode
is selected, the power dissipation of the load resistor must
be properly selected to accept the extended length of the
discharge pulse.

Indicators: CMN, MMN, PFN, OTN Pins
Indicators can be connected to the device to display the
charge mode and any fault conditions. The device has four
outputs for driving external indicators. These pins are active
low. The four indicator outputs have open drains and are
designed to be used with LEDs. Each output can sink over
20 mA which requires the use of an external current limiting
resistor. The four indicator signals denote fast charge
mode, maintenance mode, polling detect mode and out of
temperature range condition.
The charge mode (CMN) indicator is activated continuously
during the soft start and pulsed fast charge modes. When
the controller enters the dual phase maintenance mode, the
signal is turned off.

635

The maintenance mode (MMN) indicator is on when the
ICS1702 is in either the topping charge, maintenance
charge, direct maintenance mode, or the condition mode.
The MMN indicator is also lit in conjunction with the OTN
indicator when cold temperature charging is in progress.
The maintenance mode indicator pulses at a 524 ms rate
when the ICS1702 is controlling the discharge portion ofthe
discharge-to-charge mode.
The polling detect (PFN) indicator is on when the ICS1702
polls for a battery. The indicator is a warning that charge
pulses are appearing at the charging system terminals at
regular intervals. When a battery is found, the indicator is
deactivated.
The over temperature (OTN) indicator is active whenever
the voltage at the temperature sense input falls into a range
that indicates to the ICS1702 that the attached battery may
be too hot to charge. The OTN indicator is also activated
with the MMN indicator if the battery is initialized in the
cold temperature charge region. The OTN indicator will
also activate if the battery becomes cold while a charge is in
progress.

Charge Rate Selection: SO, Sl Pins
The SO and SI signals must be programmed by the user to
inform the ICS1702 of the desired charge rate. Since the
signals have an internal 100KQ pull-up, no connection to
VDD is required to program a high level. When a low level
is desired, the pin should be grounded. A high impedance
condition may be accomplished through a resistor divider.
The voltage ranges for logic low, high impedance and logic
high are detailed in Table 8 Logic Signals. To program the
SO and SI signals, refer to the Charge Rate List in Table 2.

II

[I

ICS1702
Table 2: Charge Rate List
Topping
Charge Pulse
Period 2

Maintenance Charge
Pulse Period 2

Timer

15 min (114 hr)

40 sec

160 sec

18.75 min

SO

SI

Charge
Rate

L

L

4C

L

H

2C

30 min (112 hr)

20 sec

80 sec

37.08 min

L

Z

1.3C

45 min (3/4 hr)

13 sec

53 sec

55.00 min

H

L

IC

60 min (1 hr)

10 sec

40 sec

72.50 min

H

Z

C/1.5

90 Min (1112 hr)

7 sec

27 sec

107.50 min

H

H

CI2

120 min (2 hr)

5 sec

20 sec

141.60 min

Z

L

CI2.5

150 min (2 112 hr)

4 sec

16 sec

209.87 min

Z

Z

C/3

180 min (3 hr)

3 sec

13 sec

241.90 min

Z

H

C/4

240 (4 hr)

2 sec

10 sec

273.13 min

Charge Time

Mode Selection: A UXO, A UX1 Pins
The AUXO and AUXI signals must be programmed by the
user to inform the ICS1702 ofthe desired mode. Since the
signals have an internal pull-up of l00KQ no connection to
VDD is required to program a high level. When a low level
is desired, the pin should be grounded.

High impedance may be accomplished through a resistor
divider. The voltage ranges for logic low, high impedance
and logic high are detailed in Table 8, Logic Signals. To
program the AUXO and AUXI signals, refer to the Mode
Select List in Table 3.

Table 3: Mode Select List
AUXO

AUXI

Mode Selected

L

L

Direct Maintenance

L

Z

L

H

Data Output
Device Self-Test

Device self-test for embedded applications

Ten Hour Timer

Limits total charge including the maintenance charge to 10 hours

Z

Z

H

L

H

Z

Condition

H

H

Fast Charge

Mode Operation
Indefinite C/40 maintenance mode
Outputs data in a serial self-clocking format 3

Deep Discharge to Charge lC battery discharge followed by full charge

2 Penod means the time between pulses
3 Data output help disks will be available from the factory

In

Timed CliO topping charge followed by C/40 maintenance
charge
Normal operation

lstQtr 1994

636

ICS1702
Master Reset: MRN Pin
The MRN pin is provided to re-program the chip for a new
mode or charging sequence. An internal debounce circuit
protects against spikes on the line lasting less than 100 ms.
This pin has an internal pull-up of lOOKQ. A logic low on
the MRN pin must be present for more than 131 ms for a
reset to occur. A master reset is required to clear an over
temperature condition, clear the device self test or to change
charge rates or modes.

Clock Input: RC Pin
The RC pin is used to set the frequency on the internal clock.
A 16 KQ resistor is connected between this pin and VDD.
A 100 pF capacitor is connected between this pin and
ground. The frequency of the internal clock is I MHz.

The voltage at the THERM pin should be about 1.67V at
25°C. Table 4 contains the voltage thresholds and the corresponding temperatures. A short circuit thermal switch
threshold of about O.l5V at the THERM pin is available
when either an open circuit thermal switch or no temperature sense device is used. If a voltage is below the short
circuit thermal switch threshold, the ICS1702 assumes the
thermal switch is closed to ground and the part is allowed to
operate. When the thermal switch opens at high temperature, the pull-up raises the voltage above the high temperature voltage threshold, and the part shuts down. If no
temperature sense device is used, the TIlERM pin must be
grounded. The short circuit voltage corresponds to a thermistor temperature of about 150aC.

Temperature Sensing: THERM Pin
The THERM pin requires some thought if a thermistor is
going to be used for hot and cold temperature termination.
The input impedance of the THERM pin is about IQM
typically. The example below works for a 10K @ 25°C
thermistor such as the Semitec USA (Ishizuka Electronics
Corp.) part # ATl03-2. The ICS1702 has a lOOKQ pull-up
internal to the pin.

normally closed thermal switch
opens at 45Q C

Figure 2: Thermal switch to
connection to ground at the
THERM pin

For NiCd and NiMH cells, charging should be prevented
below IO°C and above 45OC. At IOOC, the resistance of the
specified thermistor is nominally 17.96 Kil. At 45OC, the
resistance drops to 4749 Q. The ICS1702 has a voltage
threshold for the low temperature (IO°C) at 2.4 V, and a
voltage threshold for the high temperature (45°C) at 0.98 V
All voltages are referred to VDD = 5 V. U sing a resistor
divider with 10 KQ for the thermistor and a 24 KQ fixed
resistance, the divider looks like Figure I at 25°C:
VDD

Figure 1: Voltage divider at THERM pin

637

ICS1702
Table 4: Temperature Threshold List
Voltage

Thermistor Temperature

Open Circuit Thermal Switch Voltage

4.2

-25 "C

Cold Temperature Thermistor Voltage

2.4

10 °C

Hot Temperature Thermistor Voltage

0.98

45°C

Short Circuit Thermal Switch Voltage

0.150

150 "C

Parameter

Termination Select: DTSEL Pin
The ICS1702 has the capability to support either temperature termination, voltage termination or both methods simultaneously. A pull-down at the DTSEL pad enables
voltage termination only and is the default condition. Tying
the pin to VDD enables both temperature (dTldt) and voltage (dVdt) termination methods. Temperature slope termination as the only method is enabled by tying the DTSEL
pin to the CMN indicator. A transition ofthe CMN indicator and the DTSEL pin tied to CMN will set the temperature
slope termination method only in the ICS1702. See Table 5
for the DTSEL logic conditions.

Table 5: Termination Select List
Tie DTSEL Pin to .

Condition

Result

No Connect (pull-down at pad)

Low (default) Voltage slope termination only (dVldt, -dVldt)

dV/dt, -dVdt)VDD

High

Voltage and temperature termination (dVldt, -dVldt, dTldt)

CMN

High to Low

Temperature slope termination only (dTldt)

Note: Maximum temperature, maXImum voltage (open CIfCllIt detection) and fast charge timer terminatIOn methods are always enabled. Refer to
specIfIc sectIOns for mformation on dlsabhng the max temperature and max voltage methods.

638

ICS1702
Open Circuit Reference: OPREF Pin

Power: VDD Pin

The open circuit reference (OPREF) pin requires a voltage
divider to establish the open circuit voltage reference. To be
effective, the open circuit reference should be 200 to 300 m V
higher than the maximum expected charging voltage. The
maximum voltage that can be read by the analog to digital
converter at the voltage input pin is about 2.4V, so the open
circuit reference voltage should be set below that point. The
maximum voltage allowed at the OPREF pin is VDD.

The device power supply is connected to the VD D pin. The
voltage should be + 5 VDC and may be supplied to the part
through a regulator which can handle periodic current demands. See Table 7, DC Chamcteristics for more information.

Voltage Input: VIN Pin
The normalized battery voltage is connected to the voltage
input (VIN) pin. The input impedance of the VIN pin is
about 1 Mil typically. The battery voltage must be normalized through a resistor divider network to one cell. For
example, if the battery consists of six cells in a series, the
voltage at the VIN pin must be equal to the total battery
voltage divided by six. This can be accomplished with two
external resistors. To determine the correct resistor values,
count the number of cells to be charged in series. Then
choose either R 1 or R2 and solve for the other resistor using:
Rl= R2x(# ofcells-l) or R2= Rl/(# of cells-I)

VIN pin

# of cells ::

J
Figure 3: Resistor divider network at
the VIN pin

639

Grounding: VSS, A VSS Pins
There are two ground pins. One pin is used to return the
current that the indicator drivers must sink and to handle
the internal digital logic. This pin is labeled VSS and should
have a direct connection to a solid ground point to avoid
inducing ground bounce in the AVSS ground. The AVSS
ground connects to the internal analog circuitry. The AVSS
pin should also have a direct connection to a solid ground
point. Care must be taken to maintain the same potential at
both the VSS and AVSS ground point connections.

II

ICS1702
Data Tables
Table 6: Absolute Maximum Ratings
Supply Voltage

V

6.5
-0,5 to VDD + 0,5

Logic Input Levels

Oto 70

V
DC

-55 to 150

DC

Ambient Operating Temperature
Storage Temperature

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device, This is a stress
rating only, Functional operation ofthe device at the Absolute Maximum Ratings or other conditions not consistent with
the characteristics shown in this document is not recommended, Exposure to absolute maximum rating condition for
extended periods may affect product reliability,

Table 7: DC Characteristics
VDD= 5,OV; Tamb= 25 DC
PARAMETER

SYMBOL TEST CONDITIONS

Supply Voltage

VDD

Supply Current, Static

IDDs

Supply Current, Dynamic

IDDd

Upper AID Converter Range

TYP

MAX

4,5

5,0

5.5

UNITS
V

5

rnA

10

rnA

2.46

V

0

V

8192 clocks (13 bits)

300

VBG= 1.23V

Lower AID Converter Range
AID Resolution

MIN

High level Source Current, Pull-up

Ipu

VGs= 5V

50

IlV
IlA

Low Level Sink Current, Pulldown
High level Source Current,
ChargelDischarge Pins

IPD

VGS= 5V

50

IlA

IHCD

VGs= 5V, VT= O,95V

43,3

rnA

Low Level Sink Current,
ChargelDischarge Pins

ILCD

VGs= 5V, VT= O,7V

91.0

rnA

Low Level Sink Current,
Indicator Pins

ILL

VGS= 5V, VT= O,7V

122

rnA

1.0

MO

Input Impedance, VIN pin

ZVIN

640

ICS1702
Table 8: Logic Signals
PARAMETER

SYMBOL TEST CONDITIONS

MIN

High Level Input Voltage

VIH

3.5

Low Level Input Voltage

VIL

0.8

High Level Output Voltage

VOH

IOH= 2.0 rnA
VDD= MIN

Low Level Output Voltage

VOL

IOL= 2.0 rnA
VDD= MIN

Low Level Output Voltage,
Indicator Pins

VLL

IOL= lOrnA

Low Level Tristate Input Voltage

VZL

High Impedance Level Tristate
Input Voltage
High Level Tristate Input Voltage

TYP

MAX

0.84

0.89

UNITS
V

2.4

V
V

0.4

V
V

0.102

0.109

0.115

SO, SI, AUXO, AUXI

0

0.4

0.82

V

Vzz

SO, SI, AUXO, AUXI

0.82

2.5

4.1

V

VZH

SO, SI, AUXO, AUXI

4.1

5

5

V

TYP

MAX

UNITS

Table 9: liming Characteristics
PARAMETER
Clock Frequency

SYMBOL TEST CONDITIONS
fCLK

Reset/Thermal Switch Debounce
Charge Pulse Width
Discharge Pulse Width

tcpw
tDPW

Settling Time

MIN

R= 16KW, C= l00pF

1.0

MHz

fCLK= 1.0 MHz

131

ms

fCLK= 1.0 MHz

1048

ms

fcLK= 1.0 MH K

5

ms

fCLK= 1.0 MHz

4

ms

tADC

fCLK= 1.0 MHz

16.38

ms

Cycle Time

tcycle

fCLK= 1.0 MHz

1077

ms

Capacitor Discharge Pulse Width

tCDW

fCLK= 1.0 MHz

5

ms

ADC Acquisition Time

Capacitor Discharge Pulse Period

tCD

fCLK= 1.0 MHz

100

ms

Polling Detect Pulse Width

tPDW

fcLK= 1.0 MHz

100

ms

Polling Detect Pulse Period

tpD

fCLK= 1.0MHz

524

ms

Topping Charge Length

tTC

fCLK= 1.0 MHz

2.096

hrs

Maintenance Mode Sample Delay

fCLK= 1.0 MHz

4.19

s

Maintenance Mode Voltage
Sample Period

fCLK= 1.0 MHz

4.19

s

Temperature Sample Period

fcLK= 1.0 MHz

33.54

ms

Deep Discharge MMN Indicator
Blink Rate

fCLK= 1.0 MHz

524

ms

fCLK= 1.0 MHz

250

ms

Deep Discharge Pulse Width

tDDC

641

II

II

ICS1702
Table 10: Voltage Thresholds
PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNITS

Deep Discharge Termination

VDDC

0.8

V

Maintenance Mode Removal
Voltage Drop

V rem

0.2

V

Temperature Voltage Difference

15.9

mV

Thermal Switch Open Circuit

4.2

V

Thermal Switch Short Circuit

0.15

V

Cold Thermistor

2.4

V

Hot Thermistor

0.98

V

Capacitor Discharge Short Circuit

0.2

V

Vsc

642

ICS1702

Current
(notto scale)

Soft Start

t
I
I

Stage 1

Rapid Charge

I

Topping Charge

Stage 2

Maintenance Charge

Stage 4

Stage 3

Figure 4: Graphical representation of current levels during the four
charging stages
Operation

Soft Start Charge

Charging Stages
The charging sequence consists offour stages. The application of current can be shown graphically in Figure 4. Soft
start charge gradually increases current levels up to the user
specified fast charge levels during the first few minutes of
charge.
The soft start is followed by a high current charge that
includes a deep, reverse polarity pulse of short duration,
which continues until termination. After termination, a two
hour CIlO topping charge followed by a C/40 maintenance
charge is applied. Each of these four stages is described next
in more detail.

7

Rechargeable cells can exhibit a high impedance condition
while accepting the initial charging current. This high impedance condition can cause a false voltage inflection point
at the beginning of the charge cycle which may be misinterpreted as a fully charged battery by the voltage inflection
termination method. In the first stage, the soft start routine
is intended to ease batteries into a fast charge mode by
gradually increasing the current to the fast charge rate. The
gradual increase in current alleviates the false inflection
point, improves charge efficiency and improves battery life.

Fast Charge
In the second stage, the ICS1702 employs a method of
applying the charge current in a series of charge and discharge pulses that is intended to increase the charging efficiency. The technique consists of a positive current
charging pulse followed by a high current, short duration
discharge pulse. The cycle, shown with charge, discharge,
rest and data acquisition periods in Figure 5, repeats until
the batteries are fully charged.
rest
time

/

< E ( : - - - - - - - - - Charge pulse width

1< >I<

tcpw -----~)

topw

Discharge pulse width

t2j7
so
o
+2.5

+-__+,S"-l VSS
+-__+,S"-l AVSS
o

a

S1

VDD 20
TEST 19

~

3.DC return of discharge FET
should be connected close to
negative battery terminal

+5

M

R4

VIN 1-'1"'8'--________-..__-+__---.

R3

OPREFI-'I~7------------r_--+---_+----------------~1V

rnERM~I~6~-----+~2~.5--~--------+_------_,
AUX11-'1",,5-<>--l>;--+

THERMISTOR OR
THERMAL SWITCH

DTSEL 1-"",-3-<>->9
RC 12

+5

MRN

Figure 9: Functional Diagram

652

•

ICS170S

Integrated
Circuit
Systems, Inc.

Product Preview

Battery Charging and Capacity Measurement IC

General Description

Features

The ICS1705 is a CMOS IC which resides in the battery
pack and operates in conjunction with a host processor or
controller. The host processor and the ICS1705 are configured as Master/Slave. The ICS1705 provides pack specific
battery information, and contains all the analog circuitry
necessary for accurate capacity, self-discharge and voltage
measurement.

•

The ICS1705 measures and stores battery voltage and monitors temperature through a sensor, providing all analog data
to allow the host processor to control the charging. The
ICS1705 also outputs one of 8 factory-programmable battery identification numbers, and accumulates temperature
dependent self-discharge information. To minimize interconnect, the ICS1705 supports a single wire bi-directional
asynchronous serial link to the host processor for data
read/write, voltage and temperature monitoring and is compatible with most microcontroller asynchronous serial I/O
ports.

•

•
•
•
•
•

Complete "in the pack" capacity and charge measurement system
Delta/sigma A/D for measurement of:
Battery voltage
Ambient and battery temperatures
Temperature dependent self-discharge monitor
Single wire asynch serial interface to host IlC
20llA (max) standby current
Eight bytes of RAM for capacity and history storage
Wide supply voltage operating range

Applications
•
•
•
•
•

Mobile communications
Consumer video
Notebook and laptop computers
Personal digital assistants
Portable instruments

Block Diagram

II

Vref

vee

AID
CONVERTER

1.25V REF

BTEMP
V(SENSE)

GND

X1

X2

SELFDISCHARGE
TIMERS
AND
RAM

BI-DIRECTIONAL
SERIAL
COMMUNICATIONS

653

SilO

654

•

IW

AV9304/9504

Integrated
Circuit
Systems, Inc.

Quad Power Management Switches
General Description

Features

The AV9304/AV9504 Power Management Integrated Switch
(PMIS) is designed for 3 and 5 Volt systems that need to
switch steady state currents of up to 500mA. The PMIS is a
self contained part requiring no external components. The
AV9304 and AV9504 contain four power switches. in either
the 16 pin PDIP or the 300 mil wide 16 pin SOIC package.

•
•
•
•
•
•
•
•
•

The N-Channel FET switches have a typical 0.3n on- resistance. with a maximum of 0.4n For switching currents
larger than 500mA. these transistors can be paralleled
together. The +2.7V to +3.7V input supply range. the low
quiescent current and the automatic power down features
make the AV9304 ideal for battery-powered switching and
control applications. such as notebook computers. portable
medical analyzers and test equipment.

AV9304: 3.0 or 3.3V operating supply voltage
AV9504: 5V operating supply voltage
Switches loads from 2.7V to S.5V
0.3n typical. O.4n max switch resistance
Steady state current of SOOmA per switch
Automatic Power Down
1 msce FET soft tum on
No external components required
Output Ready signal

Applications
•
•
•
•
•

The "soft tum-on" feature of the 9304/9504 ensures that
there will be no spikes on the switched power supply when
the power turns on to the load.

Notebook PC Power Switching
PCMCIA VCC Switching
PDA's
Palmtop Computers
Hand-Held Medical Instruments

The 9304 operates with a supply voltage of 2.7 to 3.6V while
the 9504 operates with a supply voltage of 4.5 to 5.5Y. Either
part can switch loads from 2.7V to 5.5Y.

Block Diagram
--·----AY;-30-4-I9-S-04---l

VOO

,..........---, t-l

IN1

Q11-?-_-1

~reH
IN2

I

1 01

I

to,...~,......._

rt
tFI

11

--+i

Sl

52

READY

IN1

I...--..L...,t-t<----4I
II
~-..J

01

Q3

~reH

IN2
GND

I
Q4 ....._--1
,I '----,;-'

655

S1
I 02

~t-l
I,'

II

II

AV9304/AV9504
Pin Configuration

voo

IN4

VDD

16

IN4

01

S4

01

2

15

84

51

D4

81

3

14

04

IN1

READY

IN1

4

13

READY

5

12

IN3

6

11

83

LOAD

1N3

LOAD

02

53

02

52

03

82

7

10

GNO

IN2

8

9

IN2

03
GND

16-Pln sOle (M16W)

16-Pin DIP (N16)

Pin Descriptions
PIN #
1
2
3
4
5

PIN NAME
VDD
Dl
SI
INI

6
7

D2
S2
IN2
GND
D3
S3
IN3
READY
D4
S4
IN4

8
9
10
11
12
13
14
15
16

TYPE

LOAD

Out
Out
In
In
Out
Out
In

Out
Out
In
Out
Out
Out
In

DESCRIPTION
Positive supply voltage for the IC
PET 1 Drain
PET 1 Source
Logic input to PET 1 driver
Transparent low latch. A logic "0" on this pin allows data to flow from IN to
the PET driver. A logic "1" latches the outputs in their present state.
PET 2 Drain
PET 2 Source
Logic input to PET 2 driver
Ground
PET 3 Drain
PET 3 Source
Logic input to PET 3 driver
Pulse indicating last input to change has its PET stable and fully turned on
PET 4 Drain
PET 4 Source
Logic input to PET 4 driver

Ordering Information:
Part Number

Temperature Range

AV9304CN16

O·Cto 70·C

16-lead plastic DIP (PI6)

AV9304CW16

O·Cto 70·C

16-lead Plastic SOIC (MI6W)

AV9504CN16

O·C t070·C

16-lead plastic DIP (PI6)

AV9504CW16

O·Cto 70·C

16-lead Plastic SOIC (M16W)

656

Package Type

II

AV9304/AV9504
Absolute Maximum Ratings

Operating Conditions

VDD referenced to GND................................................. 7V
Storage temperature .................................. -40·C to +12S·C
Voltage on I/O pins ............................ -.OSV to VDD +O.5V
Power dissipation .................................................. 0.5 Watts

Drain Voltage:
AV9304 ........................................................ 2.7V to S.SV
AV9S04 ........................................................ 2.7V to S.SV
Operating temperature under bias ................. O·C to +70·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
AV9304 (Operating Vnn=+2.7 to +3.7V, TA=O·C to 70·C unless otherwise stated)
AV9S04 (Operating Vnn=+4.5 to +S.SV, TA=O·C to 70·C unless otherwise stated)
PARAMETER
Chip supply
Chip supply

SYMBOL
Vnn
Vnn

CONDITIONS
DC Characteristics
AV9304
AV9S04

MIN

TYP

MAX

UNITS

2.7
4.S

3.3
S

3.7
S.S

V
V

S.S

V

Switch Drain Voltage

VnF(l)

2.7

Switch Source Voltage

VSF

V nF -O·2

VnF

V

Input Low Voltage

Vn..

Vss

O.2Vnn

V

Input High Voltage

Vm

0.7Vnn

Vnn

V

SOO

rnA

Supply Current

InF
InD2(2)

0
All switches active

100

200

Standby Current

InDSB

All switches off

2

4

Input Low Current

In..

VIN=OV

1m

V1N=Vnn

-

-2

Input High Current

ItA
J.lA
ItA
ItA

Switch on Resistance

RoN

Switch on Resistance

RoN

Switch Current

.3

All conditions
2S·C,Vn p=3.3V
AC Characteristics
SO

INx to LOAD Inactive Setup Time

tsu

20

LOAD inactive to INx Hold Time

tHn

10

Delay to Ready

.4

.2S

tw

LOAD Pulse Width

2

-

ns
ns
ns

6

tn

n
n

ms

Note 1: In addition to the power dissipated by the oscillator and 4 charge pumps, the drop across the switches also contributes to the on chip power. This power per switches is given by: InP(VnrV SF). The total on-chip power should be held below
O.SW.
Note 2: The current consumed by the IC is proportional to the number of switches on. If only 1 FET is on, Inn will be 114 of
specified value.

657

II

II

A V9304/AV9504
Device Description
Each of the channels consists of a transparent latch, charge
pump, and N-Channel PET. Logic inputs to the drivers are
latched when LOi\i5 goes high. The logic high signal from
the latch activates the charge pump and, a few milliseconds
later, the PET is fully turned on. On chip circuitry controls
the PET tum on, which typically takes 1ms (fig 2.), to avoid
the power supply current spikes (fig. 1) which would occur if
the switch turned on fast into a fully discharged load capacitance. The chip has a common oscillator that drives the 4
charge pumps and runs at approximately 500KHz.

"r====:
IE

IE

)1

lmS

OmS

)1

POWER

SYSTEM

SWITCH

POWER
SUPPLY

Figure 2. ICS9304/9504 controlled output rise-time
and READY signal timing
An edge detector monitors the 4 latch outputs and activates
the timer when any output goes high. The Ready signal,
which comes from the timer, goes low immediately and then
goes high again typically in 6ms, thus generating a negative
going pulse (see Figure 1). Ready returns to the high state
when output PET is stable and fully turned on.

sv 1------;

I

4~

READY L-_ _ _ _ _ _ _ _~--......I

------_._--

---_._----+-I

1(0)

The automatic power down feature works by monitoring the
latch outputs. When all the latch outputs are at a logical zero,
the output of the NOR gate is high and asserts the power
down to the oscillator.
The AV9304/9504 PETs do not contain source to drain
diodes, so when the part is used for switching inductive loads
an external diode should be connected across the PET.

!

k--1ms~

Figure 1. Power Supply glitch caused by fast TON

658

II
~

AV931219512

Integrated
Circuit
Systems, Inc.

Dual Power Management Switches
General Description

Features

The AV9312/9512 Power Management Integrated Switches
are designed for 3 and 5 Volt systems that need to switch
steady state currents of up to 500mA. These are self contained parts requiring no external components. The AV9312
and AV9512 contain two power switches, and are available in
either 14 pin PDIP or 150 mil wide 14 pin SOIC package.

•
•
•
•
•
•
•
•

The N-Channel FET switches have a typical 0.20 on- resistance, with a maximum of 0.3n. For switching currents
larger than 500mA, these transistors can be paralleled
together. The +2.7V to +3.7V input supply range, the low
quiescent current and the automatic power down features
make the AV9312 ideal for battery-powered switching and
control applications, such as notebook computers, portable
medical analyzers and test equipment.
The "soft tum-on" feature of the 9312/9512 ensures that
there will be no spikes on the switched power supply when
the power turns on to the load.

AV9312: 3.0 or 3.3V operating supply voltage
AV9512: 5V operating supply voltage
Switches loads from 2.7V to 5.5V
0.20 typical, 0.30 max switch resistance
Steady state current of 500mA per switch
Automatic Power Down
1 msec FET soft tum on
No external components required

Applications
•
•

Notebook PC Power Switching
PCMCIA VCC Switching

•
•
•

PDA's
Palmtop Computers
Hand-Held Medical Instruments

The 9312 operates with a supply voltage of 2.7 to 3.6V while
the 9512 operates with a supply voltage of 4.5 to 5.5V. Either
part can switch loads from 2.7V to 5.5Y.

Block Diagram
r'~'~'~""""""""""""""""""""""""""""""""""""""""""""" ........................ ·~·~ ..

·l

IN1

i LOAD

J

IN2

D2
D2.

~

GND

t................................................................................::::.................................................. J

659

AV93121AV9512
Pin Configuration
RESET

VDO

RESET

VDO

S2

I6AD
D2

S2

LOAD

S2

D2

S2

D2

S1

D2

S1

01

S1

01

IN1

01

IN1

01

S1

GNO

GNO

IN2

14-Pin DIP (N14)

IN2

14-Pln sOle (M14)

Pin Descriptions
PIN #
1
2
3
4
5
6
7

8
9

10
11
12
13
14

PIN NAME
RESET
S2
S2
Sl
SI
INI
GND
IN2
Dl
Dl
D2
D2

TYPE
In

LOAD
VDD

Out
Out
Out
Out
In

In
Out
Out
Out
Out
In

-

DESCRIPTION
Resets input latches and turns all PET switches off when low
FET 2 Source. Must be externally connected to Pin 3
FET 2 Source. Must be externally connected to Pin 2
FET 1 Source. Must be externally connected to Pin 5
FET 1 Source. Must be externally connected to Pin 4
Logic input to FET 1 driver
Ground
Logic input to FET 2 driver
FET 1 Source. Must be externally connected to Pin 10
FET 1 Source. Must be externally connected to Pin 9
FET 2 Source. Must be externally connected to Pin 12
FET 2 Source, Must be externally connected to Pin 11
Transparent low latch. A logic "0" on this pin allows data to flow from IN to
the FET driver. A logic" 1" latches the outputs in their present state.
Power Supply for the chip: 2.7 to 3.6Vfor AV9312 and 4.5 to 5.5Vfor AV9512

Ordering Information:
Part Number

Temperature Range

AV9312CN14

O'C to 70'C

14-lead Plastic DIP (N14)

AV9512CN14

o'e to70'e

14-lead Plastic DIP (N14)

AV9312CS14

o'e to 70'e

14-lead Plastic sOle (M14)

AV9512eS14

o'e to70'e

14-lead Plastic sOle (M14)

660

Package Type

II

AV93121AV9512
Absolute Maximum Ratings

Operating Conditions

VDD referenced to GND ................................................. 7V
Storage temperature .................................. -40·C to +125·C
Voltage on I/O pins ............................ -.05V to VDD +0.5V
Power dissipation .................................................. 0.5 Watts

Drain Voltage:
AV9312 ........................................................ 2.7V to 5.5V
AV9512 ........................................................ 2.7V to 5.5V
Operating temperature under bias ................. O·C to + 70·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
AV93 12 (Operating VDD=+2.7 to +3.7V, TA=O·C to 70·C unless otherwise stated)
AV9512 (Operating VDD=+4.5 to +5.5 V, TA=O·C to 70·C unless otherwise stated)
PARAMETER
Chip supply
Chip supply

SYMBOL
VDD
VDD

CONDITIONS
DC Characteristics
AV9312
AV9512

MIN

TYP

MAX

UNITS

2.7
4.5

3.3

3.7
5.5

V
V

5

Switch Drain Voltage

VDF(1)

2.7

5.5

V

Switch Source Voltage

V SF

VDF~·2

VDF

V

Input Low Voltage

Vn.

Vss

0.2VDD

V

Input High Voltage

VIH

0.7VDD

V DD

V

0

500

rnA

Supply Current

IDF
IDD2 (2)

All switches active

100

200

Standby Current

IDDSB

All switches off

2

4

JJA
JJA
JJA
JJA

Switch Current

Input Low Current

In.

VIN=OV

-

-2

Input High Current

IIH

VIN=VDD

-

2

RoN
RoN

All conditions

.2

.3

25·C,VD~3.3V

.15

n
n

-

ns

Switch on Resistance
Switch on Resistance

AC Characteristics
LOAD Pulse Width

tw

50

INx to LOAD Inactive Setup TIme

tsu

20

tHD

10

LOAD inactive to INx Hold TIme

ns
ns

Note 1: In addition to the power dissipated by the oscillator and 2 charge pumps, the drop across the switches also contributes to the on chip power. This power per switches is given by: IDF

4.0V

Figure 2. ICS931219512 controlled output rise-time
To insure the FET switches are off, the RESET pin should be
pulsed low.
An edge detector monitors the 4 latch outputs and activates
the timer when any output goes high. The Ready signal,
which comes from the timer, goes low immediately and then
goes high again typically in 6ms, thus generating a negative
going pulse (see Figure 1). Ready returns to the high state
when output FET is stable and fully turned on.

POWER

SYSTEM

1mS

I

_..........................-................._-;.............__._..........

The AV9312/9512 FETs do not contain source to drain
diodes, so when the part is used for switching inductive loads
an external diode should be connected across the FET.

I

~O)

!

k---1mS~

Figure 1. Power Supply glitch caused by fast TON
The automatic power down feature works by monitoring the
latch outputs. When all the latch outputs are at a logical zero,
the output of the NOR gate is high and powers down the
oscillator to conserve power.
The AV93 12/9512 FETs do not contain source to drain
diodes. If the part is used for switching inductive loads, an
external diode should be connected across the FET.
The source pins and drain pins should be connected together
externally for each output switch to obtain minimum switch
on resistance. So, DI (pin#9) should be connected to Dl (pin
#10) and likewise with D2, SI, and S2.

662

ICS

Power Management
Applications

II

663

664

•

AN1700A

Integrated
Circuit
Systems, Inc.

Application Note

QuickSaver™ Controller For Nickel-Cadmium Batteries
Development of Nickel-Cadmium Batteries
Alkaline nickel plate technology began with the 1899 invention of a vented nickel-cadmium battery by Waldmar
Jungner. Around the same time, Thomas Edison experimented with a rechargeable nickel-iron battery for use in
electric automobiles. Unfortunately, the materials for these
alkaline storage batteries were expensive in comparison with
other types of batteries, so their practical use was severely
limited.
Since then, several major refinements to Jungner's nickelcadmium battery have dramatically enhanced the characteristics of nickel-cadmium technology. An improvement in
1932 was a method to place the active materials inside a
porous nickel plate electrode, which was then packed inside
a metal tube container. By 1947, research had begun on the
development of a sealed nickel-cadmium battery that recombined the internal gases caused by the chemical reactions instead of venting them. The successful resolution of
that problem has led to a wide range of possible uses for
nickel-cadmium batteries.

The advantages of sealed nickel-cadmium batteries include
excellent efficiency, long discharge life, high-cycle lifetimes
and high-energy density in a small, lightweight, compact
design. Nickel-cadmium batteries are cost-effective, require
no maintenance and are very rugged. These attributes continue to make these batteries a popular choice for industrial
and consumer applications.

The parameter for describing current flow is known as the
C rate. The C rate is defined as the current flow rate that is
equal to the rated battery capacity. For example, applying a
2 ampere charge to a I ampere-hour battery is a 2C charge
rate. The same 2 ampere charge to a 500 mAh cell is a 4C
rate. The C rate scales with the battery capacity.
The voltage that a nickel-cadmium cell can supply is typically around 1.3 volts under no-load conditions. The internal
electrochemical reactions determine the no-load voltage
(Vo) of the cell. The voltage changes slightly with ambient
temperature, age, and condition of the cell. Vo also varies as
a function of the amount of capacity already removed from
the cell.
The effective internal impedance (ZI) is determined by two
factors: the resistance of the internal plates in the cell and
the degree of difficulty of the ionic flow through the separator and electrolyte. The resistance of the plates is constant;
however, the impedance due to the ionic flow varies dramatically during the application of charge to a cell.

Cell Electrochemistry
When a cell is charged or discharged, the nickel and cadmium plates undergo an oxidation-reduction (redox) reaction. This means oxygen, in an ionized form, is transferred
between the positive and negative plates.
The redox reaction between the plates occurs without
changing the physical condition of the plates. The reaction
is entirely self-contained and completely reversible, since
the charge or discharge process consumes none of the active
materials on the plates. While under charge, the positive
plate reduces from cadmium hydroxide to cadmium by releasing oxygen into the electrolyte and by accepting electrons from the charging circuitry:

Battery Parameters
Batteries are defined as consisting of one or more cells,
usually connected in series for higher output voltages. Cells
are the individual building blocks, containing a positive
cadmium plate, a negative nickel plate, an insulating separator and an alkaline electrolyte.
Cell capacity is specified as the rate of current a cell can
supply over time under discharge, usually measured in units
of ampere-hours. The quantity of reactive materials inside a
cell determines the charge a cell can contain; therefore, the
bigger the cell, the more capacity it has.

Cd (OH)2 + 2e

_

Charge

=

Cd + 20H

DIscharge

Equation 1: Reduction Reaction

QUickSaver IS a trademark of Integrated CircUit Systems, Inc

665

II

AN1700A
The nickel hydroxide in the negative plate accepts oxygen
from the electrolyte to create nickel oxyhydroxide:

The oxygen gases that are generated and recombined at the
positive and negative plates are exothermic reactions. This
means that heat is created during the reaction. The exothermic heating is a potential problem when charging nickelcadmium batteries.

Charge

2Ni(OH)2+ 20H

2Ni OOH + 2H20 + 2e
Discharge

Equation 2: Oxidation Reaction

Cell Charge Curve

The alkaline electrolyte in the cell does not undergo a chemical change. Its purpose is only to transfer hydroxide ions
from one set of plates to the other. The overall reaction of
the cell in the electrolyte is:

Nickel-cadmium cells have a typical voltage vs. time charging curve, as shown in Figure 1:

Charge

2Ni(OH)2 + Cd(OH)2

=

Cd + 2H20 + 2NiOOH

Discharge

Equation 3: Net Reaction

Temperature Termination

2.0

50

-tN Termination

160

Inflection Paint Termination

1.9
45
1.8

120
40

~

(I)

0

1.7

~

""
1')

o

2-

1.6

35

(f)

-2
2

C>-

80

(f)
(f)

C>-

1.5

1:'

E

Voltage

D-

([)

B

f-

30

A

1.4

40
25

Temperature

1.3
Pressure

1.2

20
0

1000

2000

3000

4000

5000

6000

Time (seconds)

Figure 1:

Voltage, Temperature and Pressure Curves

666

1:'
:J

(I)

(I)

01

.3
0
>

.'2'

1:'

0

AN1700A
The application of a steady charging current to a discharged
battery causes an immediate jump in the cell voltage, due to
the cell's internal impedance (point A). The cell voltage
continues to rise at a much slower rate as the battery begins
to accept a charge. In this region (point B) the oxygen gas
generated by the electrochemical reaction is being recombined at the same rate, so the internal cell temperature and
pressure remain low.

Generating and recombining oxygen in the electrolyte are
exothermic reactions. Overcharging a battery (point E) continues to generate oxygen gas, building temperatures and
pressures. Forcing a battery to vent causes a loss of electrolyte, reducing battery capacity and damaging the cell. If the
gas cannot vent quickly enough, the battery can explode.

Charging Concerns
Oxygen and hydrogen are the two gases generally present
during cell charging. Oxygen, which is present in much
greater amounts than hydrogen, causes pressure build-up
when more oxygen is created than can be absorbed. A
nominal pressure during charge of about I Ib.lsq .in. will
increase rapidly during overcharge to 100 Ib.lsq .in. or
higher, depending on the charge rate.
At some time during the charge, the cell voltage begins to
rise much more sharply (point C). This change in slope is
caused by an increase in the internal impedance and signals
that the battery is nearing its capacity to accept charge. The
increase in impedance is due to fewer and fewer sites remaining on the positive electrode that can generate oxygen.

Overcharge
Eventually the continued application of current is no longer
converted to stored energy in the cell. Instead, the oxygen
overpotential at the positive plates is surpassed. Oxygen gas
is produced due to the electrolysis of the electrolyte, and not
by the reduction of cadmium hydroxide to cadmium. The
electrolyte, composed of potassium hydroxide and water,
changes hydroxide ions into oxygen, water and free electrons.
40H
Equation 4: Anion Oxidation Reaction

The oxygen produced by electrolysis is quickly recombined
in the electrolyte at the negative plates. However, a marked
increase in cell temperature and pressure follows as the
current input shifts from raising the cell's state of charge to
generating oxygen gas.

Pressure
The gas buildup in nickel-cadmium cells is a problem when
contemplating methods to charge batteries. Gas bubbles
accumulate on the surface of plates, reducing the plate
surface area and increasing impedance. Overcharging produces gas which, if not recombined quickly enough, can
cause damaging pressures to build up inside a cell. Excess
pressure causes a sealed cell to vent, resulting in a loss of
electrolyte. As electrolyte escapes through repeated venting, the capacity decreases and impedance increases as it
becomes tougher to transfer ions between plates.

Temperature
Exothermic heating contributes to shortened battery life by
increasing the possibility of venting, the principle source of
low battery life. Nickel-cadmium batteries also have a negative temperature coefficient, meaning an increase in the
ambient temperature by a hot cell reduces the no-load
voltage ofthe surrounding cells.

Memory Effect
Under normal use (i.e., complete cell discharge) the crystal
size on the cell plates remains small. If the nickel oxyhydroxide is not completely converted back into nickel hydroxide
during a partial battery discharge, the nickel oxyhydroxide
crystals will clump together, forming larger crystal structures. This crystal size change is the cause of the memory
effect in nickel-cadmium batteries.

Cell Shorting
U sing low rate constant-current trickle charges, crystalline
fingers, or dendrites, can propagate through the plate separators and across the cell plates. In severe circumstances,
these crystal dendrites can partially or completely short-circuit a cell internally.

The switch from generating oxygen at the plates to generating oxygen in the electrolyte also causes a sharp drop in the
cell's impedance, since it is easier to strip oxygen from the
abundant hydroxide ions than from the scarcer cadmium
hydroxide. This drop in impedance causes a corresponding
drop in voltage, creating a peak in the cell voltage curve
(point D).

667

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II

AN1700A
Conventional Chargers
The majority of chargers try to avoid the problems associated with overcharging by applying a low current charge.
Nickel-cadmium cells have a natural charge decay rate of
about Cl30 to Cl50 if left undisturbed. A nickel-cadmium
cell can accept a low rate current of ClIO or less for extended
periods (18 to 22 hours) without excessive gassing or heating. A low rate constant-current charger can apply a low
trickle charge current for as long as the battery remains
connected to the charger. As the cell slowly charges, it can
radiate heat to lower temperature surrounding areas.
The problem with trickle chargers is that they are fairly slow.
For example, the capacity of the cell determines exactly how
slow: a one ampere/hour cell on a ClIO charge takes 10 hours
or more. Continued recharging with slow rate currents also
causes dendrite formations to occur. Most trickle chargers
even apply a charge without any feedback control to monitor
temperature or voltage in case of an emergency shutdown.

Voltage Termination
Chargers employing a feedback control mechanism are
much safer to operate. Some feedback systems monitor the
battery voltage, some watch the cell temperature, and others
are timer controlled.
The most distinctive parameter to monitor is the peak in the
cell voltage that occurs as the cell transitions from charge to
overcharge. Many chargers look for a negative change in
voltage (-A V) and terminate charge at that point. Others
look for a certain voltage threshold and stop charging at that
point.
Problems occur if batteries are composed of unmatched
cells since each cell has its own characteristics. The voltage
monitoring methods are inappropriate for unmatched cells,
since the voltages of different cells in a batterypack are often
inconsistent with each other. Battery voltages can vary 5%
with a 25°C variation in ambient temperature, and the
internal imbalances, impedances and levels of precharge
will vary from cell to cell.

Temperature Termination
Another way to recognize full charge involves sensing cell
temperature. Batteries typically reach about 45°C to 50 °c
at peak charge. Another method is to monitor the temperature gradient between the inside and outside of a battery
pack and terminate at some predetermined threshold.
In either case, though, the battery will be undercharged at
high ambient temperatures or damaged at low temperatures
due to the negative temperature coefficient of nickel-cadmium cells. Variations in unmatched cell charge acceptance
cannot be monitored with any accuracy since there is no way
to tell if a particular cell out of several cells has reached its
full charge. Also, the battery pack manufacturer must place
the thermal sensors in the appropriate position inside the
pack.
The goal of the ICS1700A QuickSaverII Controller is to
quickly and safely charge a nickel-cadmium cell without
stressing the cell. Solving some of the problems associated
with rapidly charging a nickel-cadmium cell requires a controlled application of the charging current to the cell, as well
as a careful monitoring of the cell's condition. These two
requirements are met by using a pulsed current to charge
the cell and a mathematically-derived first derivative of the
battery voltage to watch the cell's state of charge.

The QuickSaverll Charge Method
The ICS1700A QuickSaverII Controller employs a unique
method of charging batteries that solves some of the problems raised previously. This method, patent pending, consists of a positive current charging pulse followed by a
high-current, short duration discharge pulse. The cycle,
shown in Figure 2, is repeated until the batteries are
charged.

668

AN1700A
I

~

~~----------~, ~------------~

C~hrge

POSitIve
current pulse

2ms~

'
E

983 ms

-25 x charge pulse

1
Figure 2:

Reverse Pulse Charge Profile

The amplitude of the positive charging pulse is determined
by the current capability of the power supply, the desired
charge rate and the cell capacity. The ICS1700A is capable
of controlling four user-selectable rapid charge rates of 4C,
2C, IC and O.SC, where C is the rated battery capacity in
ampere-hours. These charge rates roughly translate into 20
minute, 45 minute, 1.5 hour and 3 hour charge times.
The discharge pulse has an amplitude set at -2.5 times the
charging current. Thus the negative charge energy
also varies as a function of cell capacity but remains a
fixed ratio to the positive charge rate.

'Burping"the Battery
The primary purpose of the discharge pulse is to prevent the
accumulation of gas bubbles on the cell plates. These gas
bubbles are created under charge by the normal recombination of nickel hydroxide into nickel oxyhydroxide and cadmium hydroxide into cadmium.
The generated oxygen gas accumulates as bubbles across the
cell plates, reducing the effective surface area and raising
the internal cell impedance. Since the plate area is diminished, the time needed to completely charge the batteries
increases.
The discharge pulse acts to "burp" a battery by stripping the
bubbles away from the plates and assisting in the recombination of oxygen at the negative plates. This depolarizing
process helps reduce the cell's internal pressure, temperature and impedance, turning the majority of the applied
charge into stored energy instead of gas and heat.

The charge/discharge pulse cycle helps to restore the crystal
structure of the cell plates by breaking down crystal formations, eliminating "memory" problems. The process also
helps restore the crystal structure of the cadmium anodes.
Reducing the effect of crystal size problems enhances the
charging efficiency, allowing quicker charges at higher currents.

Trough Voltage Sensing
A 10 millisecond delay immediately follows the discharge
pulse. No charge is applied during this delay, allowing the
cell chemistry to recover. The ICS1700A reads the no-load
battery voltage during this "quiet" window. The no-load
voltage that is measured here contains less noise and is a
more accurate representation of a battery's true charge
state. Since no charging current is flowing, the measured cell
voltage is not obscured by any internal or external IR drops
or distortions caused by excess plate surface charge.

Maintenance Mode
Once the QuickSaver II Controller has determined that the
cells under charge have reached a full charge state, it drops
into a maintenance mode. The purpose of this mode is to
keep the nickel-cadmium batteries primed at peak charge
for later use. Since the charge on a nickel-cadmium battery
naturally decays over time at a varying rate of C/30 to C/50,
the maintenance mode provides a C/30 charge for as long as
the cells are connected III the charger, and the charger is
"ON."
The applied C/30 charge consists of the same charge/discharge pulse used in QSII fast charging, except the duty
factor ofthe pulse sequence has been extended. For example, the same charge/discharge pulse that happens every
second at a 2C charge rate would now occur every 60
seconds for a maintenance rate of C/30.

669

II

II

AN1700A
CHARGE MODE
-;..

1

MAINTENANCE MODE

): E

sec

~

Charge Rate x 30 sec

Figure 3:

~

Charge Pulse

+-

Discharge Pulse

---

Charge and Maintenance Profile

The charge/discharge pulses in the maintenance mode prevent dendrite formations from propagating across the plates
and separators, and helps maintain the crystal structure of
the cell plates.

Slope Termination
By far the most distinctive pointto look for is the peak in the
cell voltage curve, indicating the transition from charge to
overcharge. The voltage peak is characterized by a steep
positive slope that flattens out, then turns sharply negative.
By taking the first derivative (dvldt) of the cell voltage, a
second curve can be drawn showing the change in voltage
with respect to time.

18

00020

17
00015

1.6

c:-

"

0.0010 0.
E

"
0

?0

2:-

Voltage Curve

0

Termination
POint

15

'"
"-.!'l
0

2:-

,g"'"

0.0005

0

>

Linear Regression

0.0000

Curve

13

12

"

Q.

0

Ui

1.4

o

-0 0005
1000

2000

3000

4000

5000

Time (seconds)

Figure 4:

Voltage and Slope Curves with Termination Point

670

II

AN1700A

The first derivative will change its slope sharply in response
to small perturbations in the cell voltage curve. This sensitivityto the cell voltage helps monitor changes in the voltages
of individual cells. The first derivative, shown in Figure 4,
will peak just before the actual peak in the cell voltage. The
QuickSaver II controller can then accurately terminate
charge before the battery begins overcharging.
To enhance the shape ofthe first derivative, a linear regression algorithm can find the best fit curve for any set of data
points. The ICSI700A uses a linear regression formula to
best fit the slope m in the equation for a line y = mx + b:
SLXY -

m=

SLX2 _

LXLY
(LX)2

Equation 5: Linear Regression Formula
where s is the number of samples used in calculating the
slope m, and x and y represent axis coordinates.

Chip Operation

QuickSaverll Termination Methods
The ICSI700A uses eight different techniques to determine
when to end the charge, employing voltage monitoring,
temperature sensing and timer cutoff methods.
1) The primary method monitors the linear regression

slope of the battery voltage as outlined on Page 9. The
charge is terminated and a maintenance mode begins
when the slope reaches a derived cutoff threshold,
shown on Figure 4. The derived threshold is continuously calculated from the start of the charge routine.
Several requirements must be met, however, before the
cutoff threshold can be correctly computed to avoid
premature termination caused by anomalies in the different cells. Due to the sensitivityofthe linear regression
slope to the voltage curve, small variations in the voltage
curve can cause large swings in the linear regression
slope. This sensitivity to the battery voltage is especially
useful in monitoring unmatched cells with different
charge peaks.
2) Several unmatched cells may cause a battery charge

The core of the ICSI700A is essentially a specialized reduced instruction set (RISC) microprocessor, optimized for
efficient numerical calculations since the mathematics
needed to derive the linear regression slope and to determine the correct termination point are fairly complex.
The controller uses a 10 bit successive approximation analog
to digital converter (ADC) to change the measured analog
voltages to digital voltage numbers. These voltage numbers
are then averaged with successive numbers to create an
average voltage number. The averaging process limits the
effect of voltage jumps caused by battery and ADC noise.
The number of successive voltage numbers used in the
average depends on the charge rate.
An infmite impulse response (IIR) filter weights the averaged voltage number to filter out any large aberrations in the
cell voltage curve. The filtered average is stored in a 12
sample first-in first-out (FIFO) queue. The twelve point
FIFO holds the voltage numbers used to generate the slope.

671

curve to never reach a voltage peak. This condition
occurs if some cells reach their individual peaks while
others are still charging. A second method of charge
termination watches for a few successive calculations of
a negative linear regression slope which would indicate
a diminishing voltage curve. The ICSI700A then discontinues charging and places these cells on maintenance.
3) If a charge is applied to a fully charged battery, the cell
voltage will rise very rapidly since any applied energy
becomes plate surface charge only and does not add any
appreciable energy to the stored charge in the battery.
The ICS1700Adetects this rapid increase in voltage and
quickly shuts off the charge routine to avoid overcharging. The cells are then placed on maintenance
charge.
4) Overcharged batteries which have a charge immediately

re-applied to them will show a sharp drop in cell voltage
as a result of the change in the cell impedance. The
voltage drop triggers a sharp decrease in the linear
regression slope and will cause the ICSI700A to quickly
drop into a low current maintenance mode.

II

AN1700A
5) After several months of disuse some nickel-cadmium
cells may exhibit a high impedance condition. This high
impedance condition may not be noticeable until the
battery is under full charge. Continued charging of these
cells will create high temperatures and pressures in a
battery that may have been weakened previously. The
ICS1700A watches for these high impedance batteries
and terminates the charge if the no-load voltage runs too
high. It is recommended that these cells be replaced.
The ICS1700A must be reset before charging another
battery.
6) A battery sometimes contains cells that may be shorted
internally due to dendrite growth or damaged separators. The ICS1700A attempts to detect these batteries
before a long term high current charge is applied. A
normal battery will jump to about 1.3 volts in response
to an applied current. A shorted battery will remain
below a preset threshold, indicating previously damaged
cells. These cells should be replaced. The controller
must be reset before another battery can be charged.
7) Failsafe termination utilizes the "deadman" timer which
terminates charge after a preset amount of time in the
unlikely event that the cell voltage curve never reaches
a peak voltage nor descends in slope. The timer will time
out after a certain period based on the selected charge
rate. The charger must be reset before charging can
continue.
8) The final method utilizes an end-user supplied thermal
switch which will open circuit if the battery becomes too
warm. Shutofftemperatures for nickel-cadmium batteries are about 45°C to 50 °c to avoid unnecessary venting.
It is strongly recommended that a thermal switch be used
when charging nickel-cadmium batteries at high rates.
Short circuit or open circuit charger contacts are detected before a full charge is applied to avoid harming
the charging circuitry. A high current pulse is applied to
the contacts with the resulting voltage compared to
preset thresholds. If the voltage never rises, or rises too
high, a contact fault is presumed. The ICS1700A assumes that a battery has been misplaced against the
contacts, and will reattempt to start a charge. At the end
ofthis period the controller will quit trying and will have
to be reset for further use.

Interfacing to External Circuitry
The ICS1700A requires some external components to control the clock rate and provide an indicator display (see
Figure 5). The chip must be interfaced to an external power
source that will provide the constant current required to
charge a battery pack as well as a circuit that will sink a
negative current discharge pulse.
The ICS1700A does not control the amount of current flowing into the battery in any way other than turning it on and
off. THE REQUIRED CURRENT FOR THE SELECTED CHARGE
RATE MUST BE PROVIDED BY THE USER'S POWER SOURCE. The
external charging circuitry must provide a constant current
at the charge rate that was previously selected. For example,
to charge a 1.2 ampere hour battery at a 2C rate, 2.4 amperes
of current would be needed.
The Charge and Discharge signals are active high, TTL
compatible signals. In addition to being TTL compatible,
the CMOS outputs are capable of sourcing current which
can add flexibility when interfacing to other circuitry. A
'high" on the "Charge" signal indicates that the constant
current supply should be activated. A 'high" on the 'Discharge" signal indicates that the discharger should be activated.
Care must be taken to control wiring resistance, and the load
resistor must be capable of handling this short-duration
high-amplitude pulse.
LED indicators can be connected to the device to display

the charge mode and any fault conditions. The device has
three outputs for driving external indicators. The three indicator outputs have open drains and are designed to be
used with LED indicators. Each output can sink over 20 mA
which requires the use of an external current limiting resistor. The three indicator signals denote battery fault, charge
mode and over temperature.
The battery fault indicator is activated whenever a battery
with low charge slope or a high impedance is detected.
Either one of these faults indicates a defective battery. The
low charge slope failure indicates that the battery is not
accepting charge normally. It is detected by a very slow rise
in battery voltage during the first twenty seconds of charge.
The high impedance failure is detected by very high charging
voltage during the first twenty seconds of charge.
The battery fault indicator is also activated when a poor
contact between the charger and the battery is detected. It
may also activate if the charge terminals are short circuited
or if a battery pack has several shorted cells. In the event that
a contact fault is detected, the controller will retest twice per
second for a good contact for a total of 10 seconds. If the
contact fault is not cleared during the initial ten seconds of

672

AN1700A
charging, the controller will enter a quit mode and can only
be restarted by momentarily opening the over temperature
switch or by momentarily grounding the reset pin.
The charge mode indicator is activated continuously during
charging. When the controller enters maintenance mode,
the signal is pulsed on and off at a one half second rate.
The over temperature indicator is activated whenever the
over temperature sWitch opens. This indicates that excessively high temperatures have occurred in the battery pack.
The over temperature signal also issues a reset command to
the microprocessor. If a fault condition occurs, it can be
cleared by opening the over temperature line connected to
the temperature switch contained within the battery pack.
The TS input connects to one side of the temperature sensor
(thermal) switch. The other side of this switch connects to
ground. The thermal switch should have a cutoff of 45°C.
The TS input has an internal pull-up resistor insuring a high
logic level when the switch is open. The controller will not
attempt to start a charge sequence unless this signal is low.
The SO and SI signals must be programmed by (he user to
inform the ICS1700A of the desired charge rate. Since the
signals have an internal pull-up, no connection to VDD is
required to program a high level. When a low level is
desired, the pin should be grounded. To program the SO and
SI signals, refer to the table shown below (Table I).

The reset pin is provided to restart the charge sequence. An
external I Ilf capacitor should be connected to this pin and
ground to provide a power-on master clear signal. In addition, a diode should be connected from this pin to the + 5V
supply to discharge the capacitor in the event of a momentarypower interruption. This pin has a Schmidt trigger input
which protects against slowly rising voltages. A reset is
required to clear a battery fault or contact fault condition or
to exit the maintenance mode.
An external reference voltage is not required for the

ICS1700A. An internal bandgap voltage reference (1.25V,
nominally) is provided for battery and contact fault detection. If a more precise reference is required, an external
voltage reference can be used on pin 13 and this reference
will override the internal bandgap reference.
There are two ground pins. One pin is used exclusively to
return the current that the LED drivers must sink. The pin
is labeled L VSS and should have a direct connection to a
ground point to avoid inducing ground bounce in the VSS
ground. The ground for the rest of the circuitry is labeled
VSS. Both ground points must have the same potential.
The '1CS1700A QuickSaverII Controller Evaluation Board
Application Note" contains some additional, valuable information regarding interfacing with external components.

References
I) Sealed Type Nickel-Cadmium Batteries Engineering

Handbook. Sanyo Corp., 1990.

Table 1

so

I

L

I
II

H

SI

RATE

I

TIMER

2) Sealed Rechargeable Batteries Application Manual.
Gates Energy Products, 1989.

PERIOD

I

I,

I MAINT PULSE

L

4C

18.75 min

160 sec

L

H

2C

37.08 min

80 sec

H

L

IC

72.3 min

40 sec

H

0.5C

141.6 min

20 sec

The normalized battery voltage is connected to the VIN pin.
The battery voltage must be normalized to one cell. For
example, if the battery consists of six cells in series, the VIN
voltage must be equal to the battery voltage divided by six.
This can be accomplished with two external resistors. The
input impedance of the VIN pin is quite high, about I MQ
typically.
The R C pin is used to set the frequency of the internal clock.
A 16KQ resistor is connected between this pin and VDD,
and a 100pF capacitor is connected between this pin and
ground. The frequency of the internal clock is I MHz.

3) Nickel Cadmium Technical Manual. Panasonic
Industrial Co., 1989.
4) Benjamin, Fred. The Reflex Principle of Charging
Nickel-Cadmium and Other Batteries.
Gardena: Christie Electric Corp., May 22, 1972, pp 3-11.
5) Benjamin, Fred, et al. 6-in-1 Battery Sleuth - CASP with
Reflex2000 - The Ultimate Answer to BatteryProblems.
Gardena: Christie Electric Corp.
6) Benjamin, Fred. "System for 20-Min Recharging of
Sealed Nickel-Cadmium Batteries." SMPTE Journal,
86 (April 1977) pp. 204-209.
7) Bailer, John, et al. Chemistry. 2nd ed. Orlando: Academic Press, 1984.

673

II

AN1700A
Notes:

I)

2)

Value of resIstor determined by
discharge current and capacIty of
battery pack.
DeVIce must be log!c level compatlb1e.

3)

Negat!ve battery termmal and DC return
should be connected at one pomt.

4)

A thermal switch or thermIstor can be
used with the ICS1700A Refer to the
applicatIOn note for the eqUIvalent
ClrcUlt dIagram when usmg a thermIstor.

+V

CURRENT ENABLE

(note 1) R3

+ 5V

H

(note 3)

CHG

16

VDD

Rl

01~F

DCHG

15

TEST

R2

lK
01W

/'/'

PFN

14

VIN

/'/'

CMN

13

VREF

/'/'

OTN

12

THERM

+ 5V

¢

ICS1700A

~

+ 5V
16K

lK

~

0/

SO

11

RC

VSS

10

MRN

LVSS

9

100pF
¢5%
1 O~F

Figure 5:

SI

~¢

Functional Diagram

674

lN4148

~

III

Integrated Circuit Systems. Inc.

SINCE 1976

REVERSE PULSE CHARGING - AN OVERVIEW OF CURRENT RESEARCH
PROGRAMS
by
Tom Gosse'
INTEGRATED CIRCUIT SYSTEMS, INC. eICS)
Valley Forge PA 19482

ABSTRACT
Recent research into the cycle life of rechargeable consumer cell NiCd batteries has
produced interesting results. While the evolution of battery technology has accounted for
increases in the total number of charge/discharge cycles, more dramatic results appear to
be available with improvements in battery charging methodology. A study that compared
inflection voltage termination in combination with reverse polarity charging pulses to
negative delta voltage in combination with a constant current charge, provides
preliminary data that suggests a 2X improvement in 'working' cycles.

INTRODUCTION
The market for mobile products powered by rechargeable consumer cell technology is
growing at a significantly greater rate than the rest of the technology products market. At
the same time formerly third order problems such as untethered operating time, battery
reliability, consumer safety, and environmental correctness are fast becoming second and
first order concerns of the product manager. Product designers are turning to intelligent
power control to answer some of these questions. Smart micro controllers with consumer
safety features built-in, offer a facile approach to fast charge, but the issues of overall run
time and battery reliability must be examined in greater depth.
Integrated Circuit Systems (lCS) performed fast charge and discharge cycle testing from
August of 1992 to March of 1993 using fast charge NiCd consumer cells. The testing
compared two different charge methods. The results of this testing encouraged ICS to
commission a study by THE STATE UNIVERSITY OF NEW JERSEY RUTGERS
entitled "Reverse Pulse Method of Charging Alkaline Batteries". The discussion that
follows covers background, philosophy, and method for both the ICS test and RUTGERS
study.

675

I

Definition of Terms
In order to minimize confusion a brief definition of terms is necessary. Gates Energy
Products defines various types of charging as a function of the Crate 1 . This is "the rate
in amperes or milliamperes numerically equal to the capacity rating of the cell given in
ampere-hours or milliampere-hours.,,2 The simplest type of charger trickles current into
the battery at a small fraction of the C rate, (e.g. C/20 full recharge in 36-48 hours).
More complex chargers allow current to virtually pour into the battery at some mUltiple
ofC, (e.g. 4C full recharge in 15-20 minutes).
Table 1 below defines three methods of charging batteries. Recharge time is only an
estimate based on battery temperatures <25°C and reasonable conversion efficiency from
the constant current source. Fast charge will be the focus of this presentation.

METHOD OF
CHARGING

"C" RATE

RECHARGE TIME
(HOURS)

STANDARD
QUICK
FAST

C/20 - ClIO
C/5 - C/2

36 - 16

IC - 4C

7 - 2
I - .3

Table 1 - Methods of Charge
Fast Charge

The life cycle testing performed at ICS was conducted at a 4C charge rate and a lC
discharge rate with a cool down period between discharge and charge. The average
temperature of the batteries at the start of each charge cycle was observed automatically
by the system. The charge cycle could not start until the battery pack measured 25°C
±0.25°. The charge period was approximately 17 minutes for the inflection voltage with
pulses and approximately 22 minutes for the -delta voltage, constant current method.
Discharge was performed into a known load and was approximately 1 hour each time.

Fast Charge Techniques
Fast charge techniques are comprised of two main elements: terminating the charge and
delivering the energy. A brief look at these elements and comparison of their features
will facilitate the discussion.

IGates Energy Products APPLICATION MANUAL for SEALED RECHARGEABLE BATTERIES;
Section 3.2; pp53-80.
20p cit p53.

676

Termination

When fast charging sealed consumer cell batteries two internal characteristics provide the
necessary information for charge termination - battery voltage and temperature. The
absolute value of both of these variables change when the battery is under charge. Cell
voltage and temperature can be measured externally to provide termination data. A
summary of several termination approaches for voltage and temperature is germane to
this primer. Figure 1 compares voltage and temperature termination to internal cell
temperature and pressure when fast charging. (Notice the rapid rise in the temperature
and pressure component after the voltage infection point.)"

Temperature Termination •••• .. ••••••••• .. ••••• .. ••• ..

.

2.0

-t,v Terminot,on ........ ••• .. •• ......
Inflection Point Termination ••••••••••••••

1.9

j

·1:

··1
"

160

50

45
120

1.8
40

~

.....

.....

e
35 .a
.,1:!
...E.,

....

;; 1.7

....~

u

.......
III

=g

~

.,

,g'"
~

1.6

.1'
Q.

SO ...GI
:>

.

III

Q.

1.5

e

n.

30

40

1.4
25
1.3
1.2

o

1000

2000

3000

4000

5000

6000

20

0

Time (seconds)

Figure 1
A comparison of various termination methods at 1C

•• Data for Figure 1 has been accumulated over the past 2 years by testing a large variety of rapid and
standard charge batteries from a number of manufacturers. The pressure and temperature data is actual and
was acquired using pressure transducers inserted in the battery and temperature sensors in the pack.

677

A comparison study of voltage based termination methods includes dVldt, -dV, and Vmax
so that a conclusive analysis can be performed. dVldt type charge termination is a
relatively complex mathematical calculation of the first derivative of voltage through the
use of a linear regression formula 3 • This terminates the charge at the voltage inflection
when the cell has reached -98% of full charge voltage. This point of inflection is prior to
a transition into cell overcharge.
-dV and Vmax are far simpler termination methods using either a comparison to cell
voltage at the start of charge or a maximum voltage threshold referenced to an external
open circuit voltage level.

Figure 2 below highlights the voltage inflection and the negative voltage and maximum
voltage points can be seen as well. In the study performed by IeS discussed in this paper
we compared only dVldt and -dV. The amount of negativity was set at -7 millivolts per
cell.

1.8

0.0020
Termination Point

1.7
0.0015

Inllecllon Point

eo 1.8

'7

:t

i

J

0.0010

t.5
0.0005

1.4Slope Curve

0.0000

1.3

0

1000

2000

300D

5000

-D.OOO5

11m. (IICOneII)

Figure 2.
A comparison of voltage termination methods.
3 To enhance the shape of the first derivative, a linear regression algorithm can find the best fit curve for
any set of data points. ICS uses y mx + b: m srxy - rx~y / s~ - (rx)', where s is the number of

=

=

samples used in calculating the slope m, and x and y represent axis coordinates.
678

i

Ii

Termination of charge using the temperature method is predicated upon the internal heat
generated by the cell as it approaches full charge. This method requires monitoring of
both the cell temperature and compensating for ambient temperature differences.
Similarly to voltage, several varieties of temperature methods can be employed to
terminate a fast charge, dT/dt, dT, and Tmax'
In a small measure dTldt can be likened to dVldt because of the requirement for constant
sampling of the temperature so that a representative curve can be obtained. It is quite
different though when comparing the volatility of the two variables. The cell temperature
will generally rise more rapidly than ambient as it approaches the charge/overcharge
transition point. However fast charging hot or cold batteries (as defined by the
manufacturer's specifications) can be quite a nasty experience and some method of
understanding the batteries pre-charge temperature should be included in any temperature
based scheme.
dT which terminates the charge upon detection of a crossover temperature point when
compared to a 'dummy' thermal mass in the battery and Tmax which essentially shuts off
the charge after the battery reaches a fixed temperature can definitely be affected by the
hot/cold battery problem. Figure 3 below shows some typical temperature slopes for
NiCd and NiMH battery types.
50

45

I

..... 40

E
!

i

35

Nickel-Uetal Hydride
Temperature

!.
~

... 30

Nickel-Cadmium
Temperature

25

20

,

o

I

1000

,

,

I

,

,

2000

,

I

,

,

3000

,

I

,

4000

TIme (seconds)

Figure 3.
dT/dt curves for NiCd and NiMH batteries.

679

,

!

5000

•

,

.
6000

Charge Current

Another component of fast charging sealed consumer cell NiCd batteries is to provide a
current source. In the first tests that ICS performed we compared constant current with
reverse polarity pulsing current. There is also positive pulsing current that can be used
to charge batteries. In Figure 4 the various components of each of these three
applications of current are presented.

IoE(~------Cha::pulse

width

\:PW

----~)

rest
tIme

1<*
Discharge pulse width

oE(~__________________ t~ ----------------~~

Figure 4.
The application of current during charge.
A constant cu"ent charge consists of a continuous application of current to the negative
electrode. Reverse polarity pulsing cu"ent consists of a forward bias and reverse bias
current pulse. While positive pulsing cu"ent is the application of forward bias current in
an on/off pattern.
ICS uses a specific reverse polarity pulsing cu"ent pattern that is represented from start
to finish in the one(l) second segment shown in Figure 4. This pattern is based primarily
on the Christie Electric reFLEX® principle put forth by Fred Benjamin in a paper
entitled "THE reFLEX PRINCIPLE OF CHARGING NICKEL-CADMIUM AND
OTHER BATTERIES"4 circa 1976. (lCS is the exclusive licensee of Christie patent
4,746,852 for incorporation into integrated circuit devices.) The pulse pattern is
composed of three main elements: a forward bias current, a high current reverse bias
discharge, and a rest period. This pattern is repeated throughout the charging sequence,
with battery voltage measurements taken once every second, within the rest period.
The discharge pulse is set at -2.5X the charge rate, e.g. a charge rate of 1C (1 hour) for a
1.2 ampere-hour battery would be discharged at -3A, so that the desired effect of the
pulse can be assured every time. Regularity is an important feature of this method and
allows for consistent voltage readings and good charge efficiency. The -2.5X discharge is
Excerpts from "THE reFLEX PRINCIPLE OF CHARGING NICKEL-CADMIUM AND OTHER
BATTERIES" F. Benjamin; pp.3-11. along with notes from the ICS data sheet for the ICS 1700
QuickSaver™ CONTROLLER for NiCd Batteries.

4

680

intended to momentarily reverse the gas bubbling effect of the charge process,
incrementally reducing internal heating and associated pressure effects. It is also believed
to promote charge efficiency by way of temporarily reducing the surface resistance to
charge of the positive nickel plate. s
Simple pulse current charging does not have the same effect on the battery because the
stress relief in the opposing direction is not present. In many instances in the past, on/off
pulses were misconstrued to mean the same thing as reverse polarity pulsing, but there
are significant differences that can actually be felt when charging the battery at high rates
15-30 minutes or less. 6 In fact, the average temperature of cells charged with this method
in ICS testing was less than 3°C above ambient compared to an average of 3X that for
cells charged with constant current.

Research Program
In 1991 ICS executed a license agreement with Christie Electric Company of Gardena
California that permitted ICS to incorporate the principle features of the Christie CASP
apparatus into a single mixed signal integrated circuit. Upon completion of the
development of this IC, and a test configuration that would provide substantive battery
charging data, ICS began to accumulate data on batteries at various high rate charges.
The initial data was taken over a relatively short number of consecutive cycles to
understand the actual temperature changes, final capacity at termination, and operational
mysteries of the Christie machine interpreted into an algorithm.
Subsequent testing saw the incorporation of the internal pressure measurement This
measurement became available when it was discovered that there was a small gap at the
bottom of most sealed cells that could be tapped and a pressure transducer inserted and
soldered into place. A GPIB data acquisition system that had heretofore been used only
for temperature and voltage information was fonnatted to accept and plot pressure data as
well. A summary of this data is shown in Figure 1.

Preliminary Life Cycle Testing
Further expansion of the GPIB system led to the development of a 'life cycle test plan'.
This plan took twelve new, rapid charge batteries, purchased through a battery distributor,
and subjected them consecutive charge and discharge cycles until they fell below 50% of
their specified minimum capacity. The batteries were made into two 6 cell battery packs,
with all cells connected in series. A thennal switch was inserted into each pack for safety
and a thennistor was also inserted to record pack temperature during charge and
discharge. Each pack was cycled ten times at a CII 0 rate for cell conditioning.

S F.
6 F.

Benjamin, op cit, p. S.
Benjamin, op cit, pp. S-6, and excerpts from

les lab notes on battery charge testing at high rates.
681

The charge rate was 4e and charge time averaged 17 minutes for the reverse polarity
pulse charge and 23 minutes for the constant current charge. The discharge rate into a
known load was 1e, based on the manufacturer's specification. There was a cool down
period of 15 minutes provided for each pack between charge and discharge such that
neither pack started the charge cycle at a temperature higher than ambient. Testing began
in August of 1992 and concluded in March of 1993.

Results
The results of this testing was that a significant improvement in the number of charge and
discharge cycles could be seen in one method over another. This was an important first
step because most of the published information from the battery manufacturers indicated
the opposite. In fact, most of the manufacturers purported to get 500 cycles using
conventional trickle charging. The results of the graph on the next page show that fast
charging gives you a higher target to shoot at and that critical components of the charging
methodology may improve that target as well.

Rutgers Plan
In order to further exercise this theory of charging techniques les has contracted Rutgers
University in New Jersey to perform more extensive testing on IRl'ger numbers of cells.
Their test proposal will include all of the elements discussed above along with a
destructive physical analysis of the cells at 10, 100, and 500 cycles. The purpose of this
analysis is to examine the actual effect of the charge and discharge process on the
electrodes, separators, and internal physics of the battery. Since this paper is being
written in August, some of the early results of this testing will be available at the PCIM
conference in October.
The goal of the test plan is to develop an inside the cell picture of the stress induced by
charging and discharging a battery. A detailed examination of both the nickel and
cadmium electrodes will be performed through a testing lab associated with Rutgers in an
attempt to determine if the constant application of current is detrimental to the electrodes
and separator and conversely if the application of current and a reverse pulse provides a
positive effect to electrodes and separator.

682

III fut~mred
~

AAN05

Circuit
Systems, Inc.

Simplifying Dual Voltage PCMCIA Power Switching
Most new notebook PC designs incorporate support for two
PCMCIA interface cards. The PCMCIA spec (release 2.01)
supports both 5V and 3.3V cards.
After card insertion is detected, the VCC pins (pins 51 and
17) go from their initial state of no power to 5Y. The card is
then interrogated to determine whether the card's operation
should be at 5V or 3.3V by reading the card's identification
ROM tuples.

SYSTEM
POWER

SUPPLY

SYON

3.3YON

Figure 2. PCMCIA VCC Switching

The 5V line may be called upon to supply significant (>lA
peak) power to run disk drives. LAN cards etc. 3.3V power
requirements are typically much lower. (300mA max.) since
the overwhelming majority of 3.3V only cards anticipated are
semiconductor memory cards.
In figure 3. discrete P-Channel power MOSFETs are chosen
for the 5V switching. since they provide low RnsON with 5V
enhancement. The AV9312 or AV9512 offer a compact and
economical solution for switching the 3.3V; with both channels being handled in a single SOIC package with no external
components. In addition. the AV9312 and 9512 have ImS
rise time. ensuring no glitching to the system supply when
the switch closes. The 5V MOSFET switches are slowed
down with external R and C to avoid high switching currents
when charging the external card's capacitance.
Figure 1. PCMCIA Power-up Sequence

If a 3.3V supply requirement is read from the card. the system is required to drop the card's power supply from 5V to
3.3V. This requires power switching on the VCC line.

The AV9512 is designed to work with VCC at 5Vand works
with CMOS input logic levels. If the PCMCIA controller
runs from a 3.3V supply. the AV9312 would be used and
level translation will be required for PMOS switches Ql and
Q2 (fig 4).

Therefore. two power switches are required per socket. one
switch for 5V and one for 3.3V as shown in figure 2.

683

II

II

AAN05

5V for 9512 or
3.3V for 9312

SLOT A POWER
SYSTEM RESET ~>-~~....;"..--+--t

Figure 3. Complete Schematic for Dual Slot 5.0V or 3.3V PCMCIA Vee support

Figure 4 shows translation from 3.3V signals to the SV
switches with slow rise time, assuming the command signal
is active low. If load capacitance is small, rise time control
may not be necessary and Dl, R2, and Cl can be eliminated.
Ql and Rl can be replaced by a non-inverting 3.3V to SV
buffer if available.

Figure 4. 3.3V Logic Level to PMOS Drive with
Rise-TIme Control

A simpler solution to the 3.3V translation problem uses a single 9304 for each PCMCIA card slot (Fig. 5). Three Channels of the switch are paralleled for the SV switching to
increase current handling capability to I.SA and reduce
ROSON to below 1000n

Figure 5. 3.3V Logic Level input PCMCIA Power
Switching - Minimal Component Usage

In all of these circuits, the control logic should never command both the SV and 3.3V switches to be on simultaneously. A simultaneous "on" command would cause
substantial current to flow from the SV to the 3.3V power
supplies and damage the power devices.

684

ICS

Communications
Products

In addition to the Caller ID product offering in this issue, ICS is applying its unique High Performance
mixed signal CMOS technology to a new market - Communications. Applying our extensive Frequency Synthesis capability to communications systems clock and timing applications will allow ICS
to offer this market a new level of system performance. These advanced products are in process now,
with data sheets available in the near future. Contact ICS for further information.

II

685

ADV ANCE INFORMA nON documentscontam mformatIon on new products m the samplmgor preproductIOn phase of development. Charactenstlc
data and other specIfIcatIOns are subject to change WIthout notIce.

PRODUCT PREVIEW documents contam mformatlOll on products III the formatIve or deSign phase of development. CharacterIstIC data and other
speCifICatIOns are deSIgn goals. res reserves the nght to change or dlscontmue these products WIthout notice.

686

I~; fure~um
~

ICS1660

Circuit
Systems, Inc.

Incoming Call Line Identification (ICLID) Receiver
with Ring Detection
Description

Features

The ICS1660 'lCLID" circuit is a monolithic CMOS VLSI
device that decodes and detects the Erequency ~hift .Keying
(FSK) signals used in caller identification telephone service.
The ICSl660, when used in conjunction with some external
components, amplifies, filters and demodulates the FSK
data transmitted from the central office to the telephone
subscriber.

•
•
•
•
•
•

The ICSl660 detects the first power ring signal and demodulates the 1200 baud FSK data transmitted during the
silent interval between the first and second power ring. The
FSK data is transmitted from the central office switch to the
subscriber line as part of the CLASS service of ~alling
Number !2.elivery (CND). This data is then demodulated,
amplified and filtered by the ICSl660 and digitally transmitted to the host controller/processor.

Ring Detection
Low Battery Detection
Internal 5V Regulator - can externally source 25mA
FSK Demodulation
Powerdown in Standby Mode
Direct Interface to Host Microprocessor or
Microcomputer

Applications

The ICSl660 is designed to be powered by any off-the-shelf
9.0 volt battery. The on-chip 5.0 voltage regulator powers
the host microprocessor and any external circuitry supported by the ICSl660. This portion of the circuit can be
overridden by connecting the VIN pin (18) to the VDD pin
(I) for a common power supply. A low battery detection
circuit is also provided on-chip and signals the microprocessor on the FSKIBAT pin (17) when the PWR pin (16)
input is pulled low.

•
•
•
•
•

Telephones
Facsimile Machines
Modems
Telephone Interface Equipment
Stand-alone ICLID products

ICLID Block Diagram
TO LINE

TO PHONE

MlcroRng Detect

FSK Demodulation
Signal Condltlomng
Low Battery Detect

Power Down
Standby
Voltage

Regulation

687

Controller

~KmAD

a
D

Extemal
Memory
(RAM/EPROM)

ICS1660
Block Diagram

022W

I

0221!F

VCOSET

LFILTER

PLL

3
VSS

POSTF
011!F

1000pF

I
PWR

FSKBAT

16

688

I

soak

II

ICS1660
Differential Front End

Function Description
Power Supply
The ICS1660 is designed to be powered by a standard 9.0
volt battery. The chip contains a voltage regulator that
powers external circuitry and provides the supply voltage for
all digital I/O on the circuit. This allows easy interface
between the ICS1660 and other standard logic working at
5.0V. This regulator has short circuit protection and requires an external filter/compensation capacitor with a minimum value of lOuf.
In the event that an external regulated 5.0V supply is available, the VIN and VDD pins can be shorted to permit the
entire system to work from a common supply.
A low battery detection circuit is provided. This circuit is
designed for a typical trip point of 6.0V with hysteresis of
about 200m V above the trip point. This signal is low active
and is multiplexed to the FSKBA T output pin when the PWR
input is low.
In an effort to keep power dissipation to a minimum and
extend battery life, most of the analog circuits are turned off
when the circuit is at rest waiting for a ring detect, (PWR pin
low). During this time only the regulator, low battery detect,
reference generator, and ring detect circuits are active.
When the PWR pin is high, all circuits are active.

Ring Detect
As shown in the attached block diagram, the LINEA and
LINEB inputs should be connected to the telephone line
through external 82KQ resistors and O.luf capacitors. This
provides DC isolation and sets up a voltage divider with
internal resistors that will detect 35.0V RMS typically. This
voltage is applied across the LINEA and LINEB inputs. The
design value of the internal resistors is 8.1 KQ ± 20% with
relative accuracy of 2%. The RING output is high active.

As shown in the attached block diagram, the LINEA and
LINEB inputs go into a differential amplifier which in turn
drives a filter. All resistors are internal to the chip while
capacitors are connected as shown in the block diagram.
After filtering, the signal is AC coupled into a high gain
amplifier that converts the signal to digital. This digital
signal in turn acts as the reference frequency for the phase
comparator section of the phase locked loop.

FSK Demodulation
After the signal from the telephone line has been filtered,
amplified and converted to digital, it acts as an input to a
phase locked loop. This PLL does FSK demodulation. The
summing amplifier shown in the block diagram provides a
signal to the VCO that should be about 0.5V for MARK
frequency (1200 HZ), and 2.0V for SPACE frequency (2200
HZ).
As shown in the block diagram, the LFIL TER (loop filter)
output has a post filter attached to it. This POSTF signal is
sent to a comparator. The other side of the comparator is
set to approximately 2.5V. This comparator has a small
amount (200 m V) ofbysteresis and its output is the demodulated FSK data. The FSK output is high for MARK frequency and low for SPACE frequency. FSK data is
multiplexed out of the FSKBAT pin when the PWR input is
high.
The VCO frequency is set with one external resistor with a
value in the range of300K for a center frequencyof1700 HZ.
The lock range will be 660 HZ to 2630 HZ typical. The
center frequency reproducibility will be ± 15%. The center
frequency can be adjusted in the system by connecting
AMPIN to VSS, PWR to VDD, and adjusting the external
resistor for 1700 HZ. This frequency can be observed at the
LFIL TER output or the FSKIBA T output.

689

ICS1660
Typical Application

100HM
TIP
RING

MOV

82k

82k

o 111F
250V

o 0111F

o 011lF

250V

250V

15

FILTERl

10

FILTER2
PWR

02211F

ICS1660
13

1000 pF

POSTF
VR1

18

120VA~11
AC/DC
ADAPTER

91V
100llF

-=-

9VDC

690

CAL JUMPER
0----

RING

B

r----------r---------17

MICRO
CONTROLLER

FILTER 11
OUT I--~r-------

VCOSET

AMP
IN

VIN

VDD

12

,-~--~--~
VOUT

o 111F
300

1

16

A

FSKIBAT
LFILTER

+ 5V

5V

+/- 10%

II

ICS1660

Pin Descriptions
PIN NUMBER
DIP SO

NAME

DESCRIPTION

VDD

Supply voltage pin to external circuits. Output of 5.0 volt regulator.

2

2

RING

Ring detect output signal to the host microprocessor.

3

3

POSTF

Post loop filter signal used by demodulator.

4

4

LFILTER

Loop filter for PLL.

5

5

LINEAFIL TER

Filter input from line "A."

6

6

VCOSET

Center frequency adjustment pin.

7

7

LINEA

'Tip" input from telephone line.

8

8

LINEB

'Ring" input from telephone line.

9

9

VSS

Ground.

10

11

FILTER2

Active filter pin.

11

12

FILTEROUT

Active filter pin.

12

13

AMPIN

Input from active filter.

13

14

FILTER3

Active filter pin.

14

15

LINEBFIL TER

Filter input from line 'B."

15

16

FILTER 1

Active filter pin.

16

17

PWR

Logic input signal to switch from low current standby mode.

17

18

FSKIBAT

Multiplexed output signal controlled by PWR pin. In standby mode, this is a
low battery (active low) signal. During FSK demodulation, this is the data line
to the IlP (mark = high).

18

19

VIN

Input power supply pin.

10

20

NC on
VDD
RING

sorc

18 -YIN

VDD- I

20 -NC

RING

2

19-YIN

POSTF

3

17

FSKIBAT

16

PWR

15

FILTERI

LINEAFILTER

14

LINEBFlLTER

VCOSET

6

13

FILTER3

LINEA

7

12

AMPlN

LINEA~7

LINEB

8

11

F1LTEROUT

10

F1LTER2

LINEB U 1 3 - AMPlN
VSS
9
12 - FILTEROUT

2

POSTF
LFILTER

VSS

4

18 PIN

18 -FSKIBAT

LFILTER ---i4

17-PWR

LINEAFILTER ---l 5

16iFILTERI
15 i-LINEBFILTER

VCOSET ---16

NC

DIP

14 :-FILTER3

10

11 -

20 PIN

SOIC

691

FILTER2

Ordering Information
ICSI660N (DIP Package)
ICSI660M (SOIC Package)

[I

ICS1660
Analog

Input/Output Specifications
Digital
RING and FSKBA T outputs are standard CMOS outputs
with voltage swings between Vss and VDD.
PWR is a logic input. A level converter circuit is on chip to
allow the logic signal that swing between V ss and VDD to be
internally converted to signals that swing between Vss and
VIN. It should be noted that to minimize power consumption
caused by through current in logic gates, the PWR input
should always swing to within 100 mV ofVss or VDD. The
PWR input signal is low when the ICS1660 is in lower power
mode waiting for an incoming call.
The LFILTER output is a standard CMOS output powered
from VD D. This output has an internal resistor with a
typical value of 30KQ. This is used in conjunction with the
external capacitor shown in the block diagram to form the
loop filter for the PLL.

The value of the ring detect is as previously discussed 35.0V
RMS typical. The actual value is set by the choice of the
external resistors that are connected to the LINEA and
LINEB inputs. The matching of these resistors to the internal 8.IKQ resistors is also a factor. The signal level at the
chip that will cause a ring is the bandgap voltage, (1.25V) or
below.
The chip is designed for an input signal level of -12.5dbm to
-28.5dbm into 900 ohms. This translates to a signal that is
between 100 m V and 636 m V peak to peak.
The filter section should be connected as shown in the block
diagram. U sing the external capacitors as shown, and assuming nominal values on the internal resistors, the corner frequencies are 900HZ and 3860HZ.
An external resistor with a value of approximately 330KQ is
connected between the LFIL TER and POSTF pads. This
resistor along with the external capacitor shown in the block
diagram form the post filter. This post filter is used in
conjunction with the comparator to do the FSK demodulation.

Absolute Maximum Ratings*
(Voltages referenced to V ss)
Supply Voltage . . . . . . . . VIN
Voltage at any Input . . . . . .
Operation Temperature Range
Storage Temperature Range

*

-0.5V to + lOY
-0.5V to VDD + 0.5V
_55°C to + 125 °c
_50°C to 150 °c

Absolute maximum ratings are those values beyond which the safety of this device cannot be guaranteed.
These values are NOT RECOMMENDED operating conditions.

692

II

ICS1660

DC Characteristics
VIN = 4.5V - 1O.OV; T A = O°C - 70°C, Recommended Operating Range
SYMBOL
lIN

PARAMETER
Standby Current

lIN

Active Current

Voo
100
VIN

Regulator Output Voltage
Regulator Output Current
Regulator Dropout
Low Battery Detect
Low Battery Detect
Hvsteresis

lOUT
lOUT

Ring Source Current
FSKBA T and Ring Sink
Current

MIN
-

TYP
20

MAX
30

UNITS
uA

-

-

10

mA

4.5

5.0

5.5
25.0
1.0

Volts
mA
Volts
Volts
mV

2.0
0.5
6.0
200

OUTPUT CURRENT SINKlSOURCE
-500
uA
500
uA
-

693

CONDITIONS
PWR LOW, VIN = 9.0V,
100= 21lA
PWR HIGH, VIN= 9.0V
VCOSET= 300K
Output Current

Low Battery Detect - Hysteresis

YOUTH = VDD - 0.5V
VOUTL= Vss+ O.4V

ICS1660
ICLID Process Flowchart
(for Microprocessor and ASIC (lCSl660) Interface)

MlCROCONlROUER
IN STANDBYiSl.EEP
MODE

MlCROCONlROLLER

MlCROCONlROUER

ASIC IPWlI AT END
OF RING

FROM ASIC IFSKI
DURING SILENT
PERIOD

~YE_S;"'_ _ _ _-ITURNlf~:~R TO ....-----I CH~~~tey:URE

YES

YES

MlCROCONlROLLfR
WIlKES UP
AND PROCESSES
KEYPAD INTERRUPT
NO

MlCROCONlROLLER
PROCESSES DATA
AND TURNS OFF

DISPLAYS
INFORMAnON
AND liMES OUT

IPIMII

NO

YES

DISPLAYS
ERROR MESSAGE
AND lHEN liMES OUT

694

DISPLAYS
INFORMAlION
AND STORES DATA
AND lHEN lIMES OUT

Integrated
Circuit
Systems, Inc.

DB1660

ICS1660 ICLID Demonstration Board
Features

Overview

• Fully functional system permits verification of results
obtained in a product application.
• Displays ICLID function without extensive design
effort.

The OBI660 ICLID demonstration board is intended to be
used to demonstrate the function of the ICSI660 Incoming
Call Line Identification Receiver IC.1t provides a full-function incoming call display unit to verify the proper function
of the ICS1660 ICLID device.
NOTE: The only device that Integrated Circuit Systems Inc.
is able to supply is the ICSI660. The other semiconductor
devices and the display used on this board are proprietary
designs and are not available from ICS.

Operation
To use the ICS1660 ICLID demo board. install a 9 volt
alkaline battery in the battery clip on the board, and attach
the battery connector. Facing the connector end of the
board with the board "battery side up ", the RJll connector
on the right should be connected to a standard modular
phone jack. The connector at the center of the board may
be connected to the telephone instrument removed from the
modular connector. Turn the board over so that the display
is facing up and the two push buttons are toward you.
Assuming that caller 10 is available in your area, when your
telephone begins ringing, the display will show the telephone
number of your caller. After 20 seconds the display will
return to its normal (blank) mode and the number will be
stored in memory as the most recent call. When someone
calls you from an area where the telephone company is not
offering caller 10 service or an area that is not yet providing
caller 10 information via the long distance network, the
display will say "OUT-OF-AREA." In some areas, the calling party may be able to block their number from appearing
on your call display. In this case, the display will say "PRI_
VATE." If the OBI660 receives garbled data, a "?" will
appear in every digit location that has unrecognized numbers. If all digits are garbled, the display will read 'ERROR"
but will not be stored in memory. In some areas, the local
phone company will send a long-distance indicator which
will show as an 'L" on the display either with or without the
incoming number.

Pushbutton Functions
Two push buttons exist on the OB1660 board. The button to
the left when facing the board, display up and buttons
toward you is the TIME button. The button to your right is
the REVIEW button. When the REVIEW button is pressed
the phone number of the most recent call will be displayed.
Each additional time the REVIEW button is pressed (within
20 seconds) the next most recent call is displayed. When the
last call stored in memory has been reviewed, the next press
of the REVIEW button will display 'END."

If REVIEW is pressed again within 20 seconds, it will bring
you back to the start of the memory list and the most recent
call will be displayed. Ifmore than 20 seconds have elapsed
before the REVIEW button is pressed, the display will blank
and the next time REVIEW is pressed the most recent call
will be displayed.
The time and date of an incoming call can be viewed by first
pressing the REVIEW button until the selected number is
displayed, and then pressing the TIME button. Ifthe TIME
button is pressed again within 20 seconds, the telephone
number will again be displayed. This allows the TIME button to be used as a toggle between the telephone number
and the date/time of the particular call.
NOTE: The REVIEW and TIME buttons are not operative
during the interval when a new incoming phone number is
being received.
When the ten call memory of the OB1660 is full, the oldest
call will automatically be erased to make room for the next
call that comes in. To manually remove all calls, press the
TIME button while the REVIEWbutton is pressed. This will
also cause all the segments ofthe LCD display to be visible
for as long as both ofthese buttons are pressed.

695

696

ICS
ASIC Capabilities

697

698

Mixed Analog/Digital Technology
ICS's capability in mixed analog/digital (mixed mode) technology is a direct outgrowth of 16 years experience
providing turn-key designs. We have found that few mixed-mode applications lend themselves to a high level of
integration with standard cells only. Customization is critical to bridge the gap between standard cells and the
application.
ICS's confidence and success in mixed-mode design is due to our custom cell approach and our focus on
understanding the systems in which the IC must perform. We firmly believe the development of any mixed-signal
IC can be completed quickly and accurately by our team of skilled, experienced analog designers.
At ICS we use a custom cell based design methodology for our analog designs. We have developed the tools and
expertise that allow us to customize analog cells reliably and inexpensively. This approach combines the ease of
design and low risk of standard cells with the flexibility of full custom.
Of course, developing a functioning analog circuit is not as easy as connecting a few cells. An analog designer must
view the circuit function as a whole to ensure correct and accurate performance. Below is a representative list of
analog functions which we have designed and produced.

Power Conversion/Regnlation

Op-Amps

Bandgap Voltage Reference
Linear Voltage Regulator
Charge-Pump Voltage Booster
Charge-Pump Voltage Inverter
Microprocessor Reset/Clock Supervisor
Low Battery Detect
Power Switching Circuits

Low-Quiescent Current (uA)
Wide Input/Output Common Mode
High Speed (SMHz)
High Output Current

AID Converters
Successive Approximation
Dual-Slope
Sample/Track & Hold
V/F Converters

Control/Actuator Drive
Stepper Motor Driver
Air-Core Meter Movement Driver
Pulse-Width Modulated Motor Driver
Solenoid Driver
SCR/Triac Drive/Phase Control
X-Y Sensor Grid Drive
4-2OmA 2-Wire Current Loop
L VDT Demodulator/Driver

D/A Converters
R-2R
Weighted

Signal Conditioning
Active Filters
Balanced Synchronous Demodulator
Digital Sine Wave Synthesis
Fixed & Variable Gain AC Amplification

Miscellaneous
LED/LCD Display Drive
Crystal & Ceramic Resonator Oscillators
Timers/Oscillators
Precision Matched Current Sources
High-Frequency VCO/PLL (230MHz)

III

699

ASICS At ICS
ICS has been a leader in providing state-of-the-art
mixed signal and complex digital ASIC designs since
1976. The company was founded by assembling an
unequaled engineering and design team to supply the
electronics industry with the best in technical solutions
and customer service in the ASIC marketplace. ICS
has developed over 400 circuits since its beginning, and
its success in standard products can be attributed to the
same attention to detail applied to ASIC contract designs. ASIC projects are an important part of our
business, and we can provide our customers with the
best, most cost-effective solution to their ASIC needs.

ICS has focused its resources on providing the very best
technical design expertise in both analog and digital
technology. The cornerstone of this expertise is a custom/cell based approach where ICS assumes responsibility for the design, simulation, layout and verification
of each circuit. We use standard cell libraries together
with custom cells/functions where needed, a fully integrated CAD system, and proven CMOS processes. In
addition, we develop the test hardware and programs
necessary for each device we design. Our goal is to
supply a high quality product. We remain committed
to every product through on-time delivery, inventory
management and ongoing product engineering.

•

A Technical Engineering Focus - - The ICS engineering design team assigned to your ASIC product is involved from concept through characterization. Test development is considered part
of this design task, thereby assuring that all critical parameters are adequately tested. Our engineers develop a full understanding of the engineering application for each ASIC device which
allows ICS to critically evaluate the planned approach.

•

Design Flexibility - - ICS advanced design technology makes changes and modifications affordable and fast at any stage of design or production.
Simple modifications can often be corrected in
one or two mask levels, saving time and money
when changes are needed.

•

Process Flexibility - - To bring the very best
technology to your application, our suppliers include many of the leading semiconductor foundries and packaging houses. This allows for
multi-sourcing, various packaging alternatives,
and optimal utilization of semiconductor process
technology. The large volume of standard product business we do with our suppliers assures us
of competitive pricing. This permits ICS to extend large-volume pricing advantages to our
ASIC customers.

•

Complete Production Support - - ICS's approach is to out source mask tooling, wafer fab
and assembly while maintaining in-house control
over production control, testing, QC and product
engineering.

Our business philosophy is to form a partnership with
any customer whose business and technical requirements fit our guidelines and capabilities. We provide
our ASIC customers with product management, development and production sourcing capabilities, by acting
as an extension of your own engineering force. Through
this partnership we are able to provide the most costeffective solution to meet your requirements. We have
developed unique relationships with software design
companies, silicon foundries, photomask houses, and
assembly operations, both domestic and international.
These relationships provide ICS with the flexibility to
select from many particular methodologies, processes
or techniques. Our high volume of standard product
business insures competitive pricing and service that's
second to none.

700

ICS Application Specific Standard Product
ICS has the capability to customize anyofthe standard
products we offer to better suit the needs of its customers. Customized Standard Products permit an OEM
customer to optimize his system design and minimize
the amount of "glue" logic (or "glue linear") required to
implement his end product. This can result in significant size, power, and cost savings in most OEM products.
Customization of ICS standard products can entail
various degrees of complexity. A simple example might
be to change the sense of logic levels input or output
from a standard product. Frequency Timing Generator products often require specific output frequencies,
power down capabilities, or control capabilities not
available from our standard product listings. A more
complex example would be the addition of latches to
input or output signals. Perhaps the addition of a microphone preamplifier to one of the inputs of the
ICS2101 audio mixer IC would simplify your design,
packaging, and manufacturing task.
Obviously the investment in many of these alterations
can be substantial in tooling and inventory costs. Therefore the projected volume must justify the investment.
In some cases ICS may be willing to share the cost if
other markets can be found for the new product.
The growth of laptop and notebook personal computers in the marketplace has placed a severe demand on
manufacturers in the area of packaging, power consumption, performance and cost. ASIC devices may be
the only practical way to satisfy these needs.
The standard for computers since the tirst integrated
circuits made their appearance in the marketplace has
been 5 volt logic levels. Power consumption, size (due
to the size of battery packs), and performance requirements are rapidly moving this standard towards 3 volt
logic levels. ICS ASIC capabilities permit many standard products to be redesigned to work at 3 volt levels.

701

Since ICS standard products are a logical outgrowth of
our ASIC experience they utilize the same wafer fabs,
semiconductor processes, standard cell libraries and
building blocks used in our ASIC designs. This allows
ICS to use most of our standard products as super cells
in ASIC designs. The inclusion of standard product
designs in your large-scale ASIC design permits fully
characterized building blocks to be incorporated into
your ASIC with minimum risk when compared to designed-from-scratch implementations of a complex
function. Design cost, risk, and time-to-market are also
improved as we do not have to reinvent the wheel each
time the function is needed.

Foundry Selection
The chart below shows the qualified CMOS processes used by ICS for ASIC and standard products. This chart is
constantly changing, as ICS is always negotiating for the latest proven manufacturing technology. This allows us
to offer the most competitive costs to our ASIC customers, while at the same time providing qualified, proven
manufacturing processes. Please contact your ICS representative for the latest list of available processes applicable
to your particular need.

ICS Technologies
SEMICONDUCTOR
TECHNOLOGY
CMOS 311 Single Metal

Principal Features

SPEED

DENSITY

LSI
CELLS

MULTI
SOURCE

STD
CELLS

GATE
ARRAY

VOLTS

ANALOG
FULL
CELLS CUSTOM

Medium
25 MHz

Medium

Some

YES

YES

NO

3-10

YES

YES
YES

Medium

Medium

NO

YES

YES

NO

10

SWitched
Cap.

High

OK Gates

Some

YES

YES

NO

5

YES

YES

CMOS Metal Gate

Low 10 MHz

Low

NO

YES

YES

NO

5-18

YES

YES

CMOS High Voltage

Low 10 MHz

Low

NO

NO

YES

NO

30

YES

YES

CMOS 1.011

High

High

Many

YES

YES

NO

5

YES

YES

CMOS 81l

HIQh

Very HIQh

Many

NO

YES

NO

5

YES

YES

CMOS.61l

HIQh

Very HIQh

Many

NO

YES

NO

5

YES

YES

CMOS 311 Double Poly
CMOS 1.511 Double Metal

702

ICS
Quality and Reliability Information

703

ICS: Reliability Through Design
Right from the start, we concentrate on the ultimate quality of the product. rcs product reliability is designed in
to meet the necessary controls that are imposed during production and testing. All rcs designs utilize a variety of
"design-process-rule checks" to insure that product performance is consistent with our quality and reliability goals.
Design simulations and wafer data base file verifications playa prominent role throughout the prototype and are
production stages of the design to eliminate test correlation problems after the design is completed.
rn a continuing effort to improve reliability as new devices are being developed, we review the data acquired from
previous device designs to determine if any changes are necessary to improve performance and/or enhance the
new device's operation. We evaluate all aspects of packaging technology, including leadframe vs. die-size
compatibility, packaging materials and methods. rcs develops test programs to isolate problems during wafer
probe and final testing to assure the quality of our products.
An extremely important phase of the product development cycle is the characterization of devices to insure their
functional performance and establish margins of performance relative to device specifications. Samples of
prototype units are initially measured to ascertain their performance characteristics and to verify that the transition
from design and simulation to production processes has not had any deleterious effects.

GENERAL PROCESS FLOW

Production Flow
The production flow for rcs products is shown
in the adjacent diagram, which provides some
detail of the basic controls that are exercised
through the various process stages. The processes of Wafer Fabrication, Assembly and Taping and Reeling are performed by outside
facilities, with a process control- and electricaldata review for each lot of material before being
routed for processing by these subcontractors.
Wafer and package testing are performed at
rcs.
A set of electrical characteristics data is provided for each wafer lot rcs receives. Every lot
gets a parametric evaluation to determine the
uniformity ofthe process and to serve as a quality control gate for wafer acceptance from
manufacturing. SPC controls are maintained
through the use of the accumulated profile parameters to serve as a source of electrical data
feedback in support of process control and improvement programs. This data is also monitored by rcs to assess wafer fab performance
and establish acceptance criteria for wafer fab
lots. Environmental test monitoring including,
HTOL, Temperature Cycling, Autoclave and
Temperature/Humidity tests are performed to
monitor the reliability of wafers produced.
The introduction of wafers into rcs from the
wafer fab source initiates the traceability recording that tracks every part shipped from rcs.
Wafer lot numbers assigned at the wafer fab
source are recorded and are tracked through all
stages of test, assembly, taping and ultimate
shipment. At the rcs facility, all wafers are
probed on a 100% basis before being shipped
for assembly.

~

WAFERFAB
(Sub-contractor)

MATERIAL
RECEIPT

•

SPC PROCESS MONITORING

•

WAFER PROBE PROCESS
CONTROLS

•

PROCESS RELIABILl1Y
MONITORING

•

INITIATE WAFER TRAVELER
AND TRACEABILl1Y RECORDING

•

MAINTAIN RECORDS OF EACH
LOT FROM RECEIPT THROUGH
PROBING, INSPECTION,
STOCKING AND SHIPMENT TO
ASSEMBLER

100%
WAFER PROBE

ISSUE TO

STOCKROOM

SHIP TO

ASSEMBLY
SOURCE

704

!

GENERAL PROCESS FLOW (continued)

Assembly suppliers are responsible to ICS for
the processing of probed wafers into finished
package configurations in accordance with
ICS-supplied assembly specifications and
bonding diagrams. Each assembly lot is supplied with a process traveler, which delineates
the results of each process step and process
monitor inspection. SPC data is maintained
and reviewed on a periodic basis to assess such
characteristics as: die shear, bond pull, solderability, marking permanence and process control elements pertinent to the assembly
operations.

•

•

APPROVED ASSEMBLY
SOURCES WITH MONITORS
OF PROCESS STEPS THROUGH
ESTABLISHED SPC TRACKING
AND PROCESS CONTROLS

•

CONTROLLED ENVIRONMENT
FOR TEMPERATURE/HUMIDITY/
ESD

TEST

•

l

AQL SAMPLING OF ASSEMBLED
PARTS AND REVIEW OF
ASSEMBLY PROCESS LOT
TRAVELERS

•

100% TEST OF ALL RECEIVED
MATERIAL

•

AQL SAMPLING FOR TEST AND
AND MECHANICAL CHARACTERISTICS

•

CONTROLLED STOCKROOM
PENDING SHIPMENT

ASSEMBLY
OPERATION
(Sub-contractor)

l
ASSEMBLY LOT
RECEIPT

,

Processing at ICS includes incoming inspection examination of finished packages. Then
we initiate test travelers to record test and
inspection results and to allow for control of
material into the stockroom. All parts are
tested on a 100% basis in established test programs, and are checked on an AQL sampling
basis for electrical and mechanical characteristics before acceptance to stock.

MATERIAL
CONTROL

,

Ifcustomer requirements call for parts to be on
tape & reel, the parts are packaged to ICS
control specs for the implementation of this
operation. The basic spec for this operation is
per EIA Standard RS-4SI.

ISSUE TO

STOCKROOM

III

~

IF REQUIRE D BY CUSTOMER

SHIP TO

TAPE/REEL
SUPPLIER

,

TAPE & REEL
ASSEMBLY
(Sub-contractor)

•

TAPE & REEL OPERATIONS
CONFORMING TO EIA
STANDARDS RS-481

•

INCOMING VISUAL EXAMINATION AND ISSUE STOCK FOR
SHIPMENT

•

FINAL PACKAGING AND
SHIPMENT

•

OUTGOING QUALITY AUDITS

~
MATERIAL
RECEIPT &
ISSUE TO
STOCK ROOM

~

,

STOCK ROOM

SHIPPING

705

'fraceability
At ICS, traceability of products is a critical attribute of the entire production process. Tracking is initiated at the
wafer fabrication process and is maintained through all successive processing steps through final shipment.
Records of traceability are retained to allow for tracking of product delivered to a specific customer so that its
source may be determined if the need arises. Records are also available for communicating with suppliers the
identification and isolation of any problems.

Electrostatic Protection
The phenomenon ofESD (Electrostatic Discharge) can be a source of damage to sensitive semiconductor devices.
In order to address this potential for damage a dual approach is initiated. It is first addressed in the design stage
where the design guidelines provide for electrostatic protection of the input/output stages of the device. ESD
susceptibility of each device is verified to ensure the design is robust enough to be handled in the customers'
environment using normal handling precautions. A minimum level of 2kV is the standard for design; however,
product currently under test is equal to or exceeds 4kV susceptibility levels. Tests are performed in accordance
with MIL STD 883 method 3015.7.
Second, we protect against damage throughout the inspection, test and subsequent handling of parts. All personnel
are aware ofthe effects ofESD and are trained in proper handling techniques. Work stations are ESD controlled
with ground straps, ESD dissipative table tops and floor mats and air ionizers. Work in process is transported in
conductive tubs and discharged before handling on the dissipative work tables. Parts are shipped in ESD protective
tubes or reels which are further protected by electrostatic protective bags.

Product Qualification and Monitoring
The Quality Assurance Department is responsible for the qualification and monitoring of all devices manufactured
by ICS. This activity is designed to evaluate all wafer processes and package configurations and to maintain a
proactive corrective program to prevent the shipment of unreliable product.

In the qualification process, we apply the following tests and stresses:

High Thmperature Operating Life
High temperature operating life (HTOL or HTOB) testing is performed to accelerate failure mechanisms which
are thermally activated through the application of extreme temperatures and the use of biased operating conditions.
The temperature and voltage conditions used in the stress will vary with the product being tested. However, the
typical stress ambient is 125 DC with the bias applied equal to or greater than the data sheet nominal value. All
devices used in the HTOL test are sampled directly after final electrical test with no prior burn-in or other
pre screening unless called out in the normal production flow. Testing can either be performed with dynamic signals
applied to the device or in static bias configuration for a typical test duration of 1000 hours.

Thmperature Humidity Bias
Temperature humidity bias (THB) is an environmental test performed at a temperature of 85 DC and a relative
humidity of 85%. The test is designed to measure the moisture resistance of plastic encapsulated circuits. A
nominal static bias is applied to the device to create the electrolytic cells necessary to accelerate corrosion of the
metalization. Most groups are tested to 1000 hours.

Autoclave
Autoclave is an environmental test which measures device resistance to moisture penetration and the resultant
effects of galvanic corrosion. Autoclave is a highly accelerated and destructive test. Conditions employed during
the test include 121 DC, 100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism.
Groups of parts are normally tested for a 96 hour duration.

706

High Temperature Storage
High temperature storage is performed to measure the stabihtyof semiconductor devices during storage at elevated
temperatures with no electrical stress applied. The devices are typically exposed to an ambient of 150°C. An
acceleration of charge loss from the storage cell or threshold changes are the expected results. All groups are
typically tested to 1000 hours.

Temperature Cycle
Temperature cycle testing accelerates the effects of thermal expansion mismatch among the different components
within a specific die and packaging system. This test is typically performed per MIL STD 883 or MIL STD 750
with the minimum and maximum temperatures being _65°C and + 150 DC. During temperature cycle testing.
devices are inserted into a cycling system and held at the cold dwell temperature for at least ten minutes. Following
this cold dwell, the devices are heated to the hot dwell where they remain for another ten minute minimum time
period. The system employs a circulating air environment to assure rapid stabilization at the specified temperature.
The dwell at each extreme, plus the two transition times of five minutes each (one up to the hot dwell temperature,
another down to the cold dwell temperature), constitute one cycle. Test duration for this test will vary with the
device and packaging system employed. A typical test consists of 300 cycles, however some tests are extended to
look for longer term effects.

Thermal Shock
The objective of thermal shock testing is the same as that for temperature cycle testing - to emphasize differences
in expansion coefficients for components of the packaging system. However, thermal shock provides the additional
stress of sudden temperature change. This sudden change is due to the shorter transfer time, 10 seconds maximum,
and the increased thermal conductivity of a liquid ambient. This test is typically performed per MIL STD 883 or
MIL STD 750 with minimum and maximum temperatures being _65°C to + 150 Dc. Devices are placed in a
fluorocarbon bath and cooled to minimum specified temperature. After being held in the cold chamber for five
minutes minimum, the devices are transferred to an adjacent chamber filled with fluorocarbon at the maximum
specified temperature for an equivalent time. Two five-minute dwells plus two ten-second transitions constitute
one cycle.

Reliability Data Analysis
Reliability is the probability that a semiconductor device will perform its specified function in a given environment
for a specified period of time. The most frequently used reliability measure is the device failure rate. The failure
rate is obtained by dividing the number of failures observed by the product of the number of total device on test
and the test time interval. This is normally expressed in failures per billion device hours (FITS), which is a point
estimate because it is obtained from observations on a portion, or sample, of the population of devices.
To project the failure rate of devices being tested to a total population, chi-square distribution statistics are applied
at established confidence intervals. These are nominally calculated at 60% and 90% confidence levels to express
a level of confidence that the sample failure rate approximates that of the entJre population. In addition, since the
failure rate of semiconductor devices is inherently low, the application of acceleratIOn factors is applied to the data.
Commonly used Arrhenius equations are applied which provide relationships between test stress levels and normal
use operation. In applying this assessment tool an activation energy (Ea) of 0.7 Ea is normally used to determine
the Acceleration factor. This Ea level is chosen in lieu of establishing individual Ea values for each of the failure
mechanisms applicable to the technology and circuit under evaluation, particularly since the failure mechanism
database is so limited.
To determine the failure rate ofICS products, the HTOL data for individual as well as families of devices is utilized.
HTOL testing provides an adequate thermal stress with the devices being biased at greater than nominal value and
operated in a dynamic mode in this environment. Utilization of these techniques will provide a realistic, conservative estimation of the product failure rate.

707

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