1994_Lattice_Data_Book 1994 Lattice Data Book

User Manual: 1994_Lattice_Data_Book

Open the PDF directly: View PDF PDF.
Page Count: 621

Download1994_Lattice_Data_Book 1994 Lattice Data Book
Open PDF In BrowserView PDF
marshall
San Francisco Branch
336 Los Coches
Milpitas, California 95035
Electronics Group
Claude Michael Group
FAX

(408) 942-4600
(408) 942-4700
(408) 262-1224

plSlandisplSIProductlndex
Pins

Density
(PLD
Gates)

Tpd(ns)

Fmax(MHz)

Icc
(mA)

pLSl1 ispLSI 1016

44

2000

10,12,15,20

110,90,80,60

150

64 Macroceil High-Density PLD

2-61

pLSl1 ispLSI 1024

68

4000

12,15,20

90,80,60

190

96 Macroceil High-Density PLD

2-81

84

6000

12,15,20

90,80,60

195

128 Macroceil High-Density PLD

2-97

pLSl1 ispLSI 1048

120

8000

15,18,24

80,70,50

235

192 Macroceil High-Density PLD

2-117

pLSl1 ispLSI 1048C

128

8000

18,24

70,50

235

192 Macroceil High-Density PLD

2-133

pLSl1 ispLSI 2032

44

1000

7.5,10,15

135,110,80

-

32 Macroceil High-Density PLD

2-151

pLSl1 ispLSI 3256

160

11000

15,17,23

80,70,50

-

256 Macroceil High-Density PLD

2-169

Description

Page

PART #

pLSl1 ispLSI 1032

Description

Page

GAL Product Index
Pins

Tpd (ns)

Fmax(MHz)

Icc
(rnA)

GAL16V8

20

5,7.5,10,15,25

166, 100, 62.5, 41.6

55,90,115

GAL 16V8Z!ZD

20

12.15

83.3,62.5

55

100

Zero-Power 20-Pin PLD

GAL16VP8

20

15,25

80,50

115

-

64mA High Output Drive 16V8

3-49

PART #

Isb
(~)

-

Universal 20-Pin PLD

3-5
3-29

GAL18Vl0

20

15,20

62.5

115

-

22Vl0 Subset

3-67

GAL20RA10

24

10,15,20,30

71.4,50,41.7,25

100

-

Asynchronous - 10 Prog. Clocks

3-79

GAL20V8

24

5,7.5,10,15,25

166,100,62.5,41.6

55,90,115

-

Universal 24-Pin PLD

3-97

GAL20V8Z1ZD

24

12,15

83.3,62.5

55

100

Zero-Power 24-Pin PLD

3-121

GAL20VP8

24

15,25

80,50

115

-

64mA High Output Drive 20V8

3-141

GAL20XV10

24

10,15,20

100, 83.3, 71.4

00

-

24-Pin XOR PLD

3-159

5,6,7.5, 10, 15,25

200,166,142.8,105,
83.3,38.5

55,90,130,140,
150

-

Universal 24-Pin PLD

3-173

GAL22Vl0

24

ispGAL22Vl0

28

7.5,10,15

111,105,83.3

140

-

In-System Programmable 22Vl0

3-193

GAL26CV12

28

7.5,10,15,20

142.8,105,83.3,62.5

130

-

22Vl0 Superset

3-213

GAL6001

24

30

27

150

-

FPLA Architecture

3-231

GAL6002

24

15,20

75,60

135

-

FPLA Architecture

3-249

In-System Programmable Generic Digital Switch Product Index
Pins

Tpd(ns)

Fmax(MHz)

Icc
(mA)

ispGDS14

20

7.5

50

40

7 x 7 Programmable Switch Matrix

4-5

ispGDS18

24

7.5

50

40

9 x 9 Programmable Switch Matrix

4-5

ispGDS22

28

7.5

50

40

11 x 11 Programmable Switch Matrix

4-5

PART #

Description

Page

Thank you for your interest in Lattice Semiconductor's programmable logic
products. Lattice offers the world's highest performance and broadest product
line of low density and high density CMOS PLDs.
This data book includes our industry standard GAL®product line and our new
High-Density PLDs, the pLSI® and ispLSFM 1000,2000, and 3000 families. The
pLSI and ispLSI families combine the performance and ease of use of PLDs
with the density and flexibility of FPGAs.
Lattice Semiconductor, the worldwide leader in E2CMOS PLDs, is committed
to supplying you with the optimal solution to all of your programmable logic
requirements.

Steven A. Laub
Vice President and General Manager

Lattice Semiconductor Corporation

1994 Data Book

••••••
......
••••••

••••••
••••••
••••••
Copyright © 1994 Lattice Semiconductor Corporation
E2CMOS, GAL, ispGAL, pDS, pLSI, Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor
Corporation. Generic Array Logic, ISP, ispCODE, ispDOWNLOAD, ispGDS, ispLSI, ispSTREAM, Latch-Lock, pDS+ and
RFT are trademarks of Lattice Semiconductor Corporation
All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
Lattice Semiconductor Corporation products are made under one or more of the following U.S. and international patents:

4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US,
5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US,
5,245,226 US, 5,251,169 US, 0194091 EP, 019677181 EP, 0196771 UK, 0196771 WG.
LATTICE SEMICONDUCTOR CORP.
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
TELEX 277338 LSC UR

iv

Table of
Contents
Section 1: Introduction
Introduction .......................................................................................... 1-1
Section 2: High-Density Programmable Logic
Introduction to pLSI and ispLSI Families .............................................. 2-1
1000 Family Architectural Description .................................................. 2-11
2000 Family Architectural Description .................................................. 2-25
3000 Family Architectural Description .................................................. 2-31
ispLSI Architecture and Programming .................................................. 2-39
pLSI and ispLSI 1000 Family Datasheets
Introduction to pLSI and ispLSI 1000 Family ........................................ 2-57
pLSI and ispLSI 1016 ........................................................................... 2-61
pLSI and ispLSI1024 ........................................................................... 2-81
pLSI and ispLSI 1032 ........................................................................... 2-97
pLSI and ispLSI 1048 ........................................................................... 2-117
pLSI and ispLSI 1048C ......................................................................... 2-133
pLSI and ispLSI 2000 Family Datasheets
Introduction to pLSI and ispLSI2000 Family ........................................ 2-149
pLSI and ispLSI2032 ........................................................................... 2-151
pLSI and ispLSI 3000 Family Datasheets
Introduction to pLSI and ispLSI3000 Family ........................................ 2-167
pLSI and ispLSI3256 ........................................................................... 2-169
Section 3: Low-Density Programmable Logic
Introduction to Generic Array Logic ...................................................... 3-1
Commercial/Industrial Product Datasheets
GAL16V8 .............................................................................................. 3-5
GAL 16V8Z1ZD ...................................................................................... 3-29
GAL 16VP8 ........................................................................................... 3-49
GAL 18V1 O............................................................................................ 3-67
GAL20RA 10 ......................................................................................... 3-79
GAL20V8 .............................................................................................. 3-97
GAL20V8Z1ZD ...................................................................................... 3-121
GAL20VP8 ........................................................................................... 3-141
GAL20XV10 ......................................................................................... 3-159
GAL22V10 ............................................................................................ 3-173
ispGAL22V10 ....................................................................................... 3-193
GAL26CV12 ......................................................................................... 3-213
GAL6001 .............................................................................................. 3-231
GAL6002 .............................................................................................. 3-249

v

Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Introduction to ispGDS ......................................................................... 4-1
ispGDS22/18/14 Datasheet .................................................................. 4-5

Section 5: Military Program
Military Program Overview ................................................................... 5-1
Military Ordering Information ................................................................ 5-3

Military Product Datasheets
GAL 16V8 .............................................................................................. 5-5
GAL20V8 .............................................................................................. 5-13
GAL22V10 ............................................................................................ 5-21
pLSI and ispLSI 1016 (See Commercial Datasheet)
pLSI and ispLSI 1024 (See Commercial Datasheet)
pLSI and ispLSI 1032 (See Commercial Datasheet)

Section 6: Development Tools
Lattice Design Tool Strategy ................................................................. 6-1
System Design Process ....................................................................... 6-3
pLSI and ispLSI Design Flow ................................................................ 6-5

Lattice Development Tool Datasheets
pDS Software ....................................................................................... 6-9
pDS+ ABEL Software ........................................................................... 6-15
pDS+ Viewlogic Software ..................................................................... 6-19
pDS+ LOG/iC Software ........................................................................ 6-25
isp Starter Kit ........................................................................................ 6-31
ispCODE .............................................................................................. 6-33
isp Engineering Kit - Model 100 ........................................................... 6-39
isp Engineering Kit - Model 200 ........................................................... 6-43
ispDOWNLOAD Cable ......................................................................... 6-49
pLSI and ispLSI Design Tool Selector Guide ........................................ 6-51
GAL Development Support ................................................................... 6-55
ispGDS Compiler Support .................................................................... 6-57

Section 7: Quality and Reliability
Quality Assurance Program .................................................................. 7-1
Qualification Program ........................................................................... 7-3
PCMOS Testability Improves Quality .................................................. 7-5
ISO 9000 Program ................................................................................ 7-7

Section 8: General Information
Copying PAL, EPLD & PEEL Patterns into GAL Devices ..................... 8-1
GAL Product Line Cross Reference ..................................................... 8-3
Package Thermal Resistance ............................................................... 8-5
Tape and Reel Specifications ............................................................... 8-6
Package Diagrams ............................................................................... 8-7
Sales Offices ........................................................................................ 8-21
vi

I

Section 1: Introduction
Introduction .......................................................................................... 1-1
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information

1-i

--

1-ii

Introduction
Inventory Reduction

Background
Lattice Semiconductor Corporation, founded in 1983
and based in Hillsboro, Oregon, has completed its tenth
year of supplying innovative solutions for the high performance system design needs of its customers. Through
its pioneering efforts at applying E2CMOS® technology
to programmable logic, Lattice has established the GAL®
family of products as the industry standard worldwide.
With the introduction of the hi!lh-density programmable
Large Scale Integration (pLSIIIII) devices and in-system
programmable Large Scale Integration (ispLSITM) devices,
Lattice has become the world's largest supplier of lowdensity CMOS PLDs and the fastest growing supplier of
high-density CMOS PLDs.
Lattice has recently introduced two new low-density insystem programmable devices: the ispGAL22V10 and
ispGDSTM. The ispGAL22V10 brings on-the-fly system
logic reconfigurability to the industry standard GAL22V1 o.
The ispGDS (in-system programmable Generic Digital
Switch) family further extends Lattice's programmable
technology beyond logic to board interconnect and signal
routing. ispGDS opens new possibilities for system
designers and is just the first of a number of application
specific programmable solutions which will be addressed
by Lattice in the future.

A single standard part type can be used in multiple,
diverse applications. Just 5 GAL architectures replace
virtually all bipolar PAL® architectures (see figure 1).

Products
The Lattice PLD product offering can be segmented into
two strategic product thrusts:

Low Density: GAL Family
- 100 - 1,000 Gates
- The Highest Performance PLDs from any Supplier
- Superior Replacements for Bipolar and CMOS PLD
Architectures
- E2CMOS Low-Power, Quality and Reliability
- Broadest Range of PLD Architectures Offering Features
not Available in other PLDs

High Density: pLSI and IspLSI Families
- 1,000 - 14,000 Gates (World's Largest)
- World's Fastest High-Density PLDs (HDPLDs)
- Superior HDPLD Architecture (Flexible, Predictable
Performance)
- Pioneering Non-volatile In-System Programmability (ISP)
- Range of Effective Development Tool Options

The Lattice Advantage
Time-to-Market
E2CMOS PLDs enable system designers to meet evershrinking time-to-market constraints while avoiding the
significant development costs, lead times and dedicated
inventories associated with traditional ASIC and bipolar
PLD solutions.

Figure 1_ Five GAL devices replace virtually all bipolar
PAL devices.
L/l1l/a gAL Ilulf1ll
16va
20va
2ORA10
2OXV10·
22Vl0

Flexibility
Programmable and reprogrammable devices enable fast
and easy modifications to system designs.

Product Differentiation
Programmable devices support end-product differentiation through proprietary feature enhancements. This
is particularly true when a system utilizes the non-volatile
ISpTM (In-System Programmable) technology pioneered
by Lattice.

1-1

------

10HB
10L8
10P6
12H6
12L8
12P6

14H4
14H8
14L4
14L8
14P4
14P8

1111111111[ i!1:S!lI[IIDIDII2IIL!!sIlg

16H2
16H8
16H8
16L2
16L8
16L8

16P2
16P6
16P8
lBR4
16RS
leAS

16RP4
leAP6
16RP6
16H4
18L4
18P4

• GAL2OXV10 replllCM 2Ol10, 2OX10, 2OX811'1d 20)(4

18P8
18U8
2OH2
2OH8
20L2
20L8

----2Ol10·
20P6
2OR4

2OR6
20RB
2ORP4

2ORP6
2ORP8
2ORA10
20X4·
20XS·
2OX10·
22\'10

Introduction
in-system programmable high-density PLD family ispLSI, as well as the ispGAL22V10 and ispGDS.

Lattice Product Features
There are three fundamental features which Lattice PLDs
share: E2CMOS technology, performance leadership
and innovation.

The ISP concept, and the ispLSI, ispGAL and ispGDS
families in particular, dramatically impact system development and manufacturing. Lattice ISP solutions deliver:

E2CMOS Technology
All GAL, pLSI and ispLSI devices are manufactured
using Lattice's proprietary high-speed UltraMOS®
E2CMOS technology. Lattice is unique among "fab-Iess"
companies in that the process technology development
is actually done by Lattice. UltraMOS technology
successfully combines the best features of CMOS and
NMOS process technology to yield PLDs with the following key features:
- Industry Leading Performance
- High Logic Densities
- Low Power Consumption
- Non-Volatile, In-System Programmability

Effortless Prototyping: Design iterations can be downloaded directly to the ISP device soldered onto the
prototype board.
Reconfigurable Systems: A single generic board can
be "personalized" to one of many system configurations
at final board level test.
Simplified Manufacturing: Eliminates all stand-alone
programming steps. Device programming can be done
as part of board-level testing. The result is no
misprogrammed devices, no inventory headaches keeping track of patterned devices, and no PLD rework costs.
No More Bent Leads: ISP technology also solves the
handling problems associated with high pin count, fine
pitch packages (PQFP, TQFP etc.). It eliminates bent
leads and unreliable solder joints by programming devices
in-system.

- Fast Erase and Reprogram Times
- 100% Full Parametric Testability
- 100% Programming and Functional Yields

Performance Leadership
Lattice continues its long track record of producing the
fastest CMOS PLDs in the market. These industryleading high-performance products are typically available
to the market months ahead of any other PLD supplier.
As a result, Lattice customers have always been able to
take full advantage of next generation microprocessor
speeds and bring out industry leading end products of
their own, thus fueling their own success.

Summary
Lattice, the leader in E2CMOS PLDs, is committed to
providing its customers with industry-leading programmable solutions. We realize that your system design
requirements and time-to-market pressures will only get
tougher in the future. Lattice is committed to supporting
you with state-of-the-art products with the performance,
architecture, quality and reliability to meet your needs.

While speed continues to be a top priority, Lattice has
also introduced PLD families which address other logic
design concerns such as low power ("Zero-Power"
GAL16/20V8Z and GAL16/20V8ZD), high output drive
(GAL 16/20VP8) and logic density (GAL26CV12).

Innovation
The third, and perhaps the most important attribute of
Lattice's products is technology and architectural
innovation. Lattice's most far-reaching innovation may
have been the decision in 1984 to combine E2CMOS
technology with the PLD architecture when all other PLD
suppliers were offering UV erasable EPROM technology.
This marriage yielded the GAL product family - the "1st
Revolution in PLD design."
Lattice innovation also started the "2nd Revolution in
PLD design" with the introduction of the first non-volatile

1-2

Section 1: Introduction
Section 2: High-Density Programmable Logic
Introduction to pLSI and ispLSI Families .............................................. 2-1
1000 Family Architectural Description .................................................. 2-11
2000 Family Architectural Description .................................................. 2-25
3000 Family Architectural Description .................................................. 2-31
ispLSI Architecture and Programming ................ '" ............................... 2-39
pLSI and ispLSI1 000 Family Datasheets
Introduction to pLSI and ispLSI 1000 Family ........................................ 2-57
pLSI and ispLSI1016 ........................................................................... 2-61
pLSI and ispLSI 1024 ........................................................................... 2-81
pLSI and ispLSI 1032 ........................................................................... 2-97
pLSI and ispLSI 1048 ......... '" ............................. '" ............................... 2-117
pLSI and ispLSI 1048C ......................................................................... 2-133
pLSI and ispLSI 2000 Family Datasheets
Introduction to pLSI and ispLSI2000 Family ........................................ 2-149
pLSI and ispLSI2032 ........................................................................... 2-151
pLSI and ispLSI 3000 Family Datasheets
Introduction to pLSI and ispLSI 3000 Family ........................................ 2-167
pLSI and ispLSI3256 ........................................................................... 2-169
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information

2-i

•

2-ii

Introduction to
pLSI@ and ispLSI™ Families
pLSI and ispLS11000: The Premier High
Density Family

The Lattice pLSI and ispLSI Families
The Lattice programmable Large Scale Integration (pLSI)
and in-system programmable Large Scale Integration
(ispLSI) families are the logical choice for your next
design project. They're the first programmable logic
devices to combine the performance and ease of use of
PLDs with the density and flexibility of FPGAs. And at 135
MHz system speed, and up to 14000 PLD gates, they're
the world's fastest and highest density programmable
logic devices!
There are three pLSI and ispLSI families to fit your
specific application needs. Lattice's premier pLSI and
ispLSI1 000 family implements high integration functions
such as controllers, LANs and encoders at high speeds.
The high performance pLSI and ispLSI 2000 family with
its large number of lIDs handles timers, counters as well
as timing critical interfaces to high speed RISe/elSe
microprocessors. The highest density pLSI and ispLSI
3000 family integrates complete system logic, DSP functions, and entire encryption or compression logic into a
single package, while delivering superior performance.

o 110 MHz system performance
010 ns pin-to-pin delay (maximum)
02000-8000 PLD gates

o 44-pin to 128-pin packages
pLSI and ispLSI 2000: Unparalleled System
Performance
0135 MHz system performance (world's fastest!)

o 7.5 ns pin-to-pin delay (maximum)
o

1000-4000 PLD gates

o 44-pin to 128-pin packages
o High I/O to Logic Ratio
pLSI and ispLSI 3000: Density with
Performance

The ispLSI 1000, 2000 and 3000 families pioneer nonvolatile, in-system programmability, a technology that
allows real-time programming, less expensive manufacturing and end-user system reconfiguration.

o

110 MHz system performance

010 ns pin-to-pin delay (maximum)
08000-14000 PLD gates (world's largest!)

All the development tools you need are available from
Lattice - tools ranging from Lattice's own entry level
software to higher level, third-party design environments.
With these tools, you'll be completing your circuit designs
in hours instead of weeks or months.

o 128-pin to 208-pin packages
o

Boundary scan for enhanced testability
(IEEE 1149.1)

Lattice's pLSI and ispLSI Families
Applications
• Address Decoders
• State Machines
• CountersITlmers
• GfueLogic

160

• Processor BusesJ
128

va Requirements
• Pentium System
Performance

Applications

• Address
Decoders
• State Machines

96

vas

Applications

• VLSIChlps
• Graphlcs/DSP

• COunters/Tlmers

• Glue Logic
Applications

64

• LAN Controllers

1000

• Memory/DMA Controllers
• Graphic SuiJ..functions
• Interrupt Controllers

32

2000 Gates

GAL
Product Line
0

32

Functions
• Cache Controllers
• EncrypllonlDocryp1lon
• Compression
Encoders
• Glue Logic

• Data Packet: Encoders
• GluaLogic

64

96

192

128
Donslly (Macrocells)

2-1

256

320

•

Introduction to pLSI and ispLSI
Family Overview
From registers to counters, from multiplexers to complex
state machines, these families of high-density programmable logic will address your high-performance system
logic needs.

Each device contains multiple Generic Logic Blocks
(GLBs), architectured to maximize system flexibility and
performance. And a generous supply of registers and
1/0 cells provides the optimum balance of internal logic
and external connections. A global interconnect scheme
ties everything together, enabling high logic utilization.

With PLD gate densities ranging from 1,000 to 14,000,
the pLSI and ispLSI devices provide the range of programmable logic solutions you need to meet design
requirements today and tomorrow.
Table 1. pLSI and ispLSI Family Attributes

pLSIandispLSI1000

Density
(PLD Gates)
Speed:
Fmax (MHz)
Speed:
Tpd (ns)
Macrocells
Registers
Inputs & I/Os
Pins/Package

112!30QO-2A

2-2

1994 Data Book

Introduction to pLSI and ispLSI
o Low power

pLSI and ispLSI Architecture
The pLSI and ispLSI architecture was constructed with
real system design requirements in mind. Figure 1
shows the representation of the pLSI 3256 architecture.
This architecture provides the designer with the following
advantages.

o High Speed

o Flexible architecture

o Easy to use
o Design portability across all the families
o Non-volatile in-system programmable (ispLSI)

o Advanced Global Clock Network
o Boundary Scan (3000 Family)

o Predictable performance

pLSIandispLSI2000

pLSIandispLSI3000

112/300o-3A

2-3

1994 Data Book

Introduction to pLSI and ispLSI
The Global Routing Pool

The Output Routing Pool (ORP)
The Output Routing Pool (ORP) is a unique pLSI and
ispLSI architectural feature which provides flexible connections between the GLB outputs and the output pins.
This flexibility allows for "last minute" logic design changes
to be implemented without changing the external pin-out.

Central to the pLSI and ispLSI architecture is the
Global Routing Pool (GRP), which connects all of the
internal logic and makes it available to the designer.
The GRP provides complete interconnectivity with
fixed and predictable delays. This unique interconnect
scheme consistently provides high performance and
allows effortless implementation of complex designs.

---- --- M

Figure 1. pLSI 3256 Functional Block Diagram
l1lil1li

n ut us

I output Routing Pool (ORP) I
~0~~

l1li

1 ~B

n ut us

I Output Routing Pool (ORP) I

r--~

G~-

I~ ~B

B -1
B 1
! I
B
V'-Bi I
"0

o

'"

:;::

"

::::J

~

GLB-

c

Generic
Logic
Block

:~ ,5

Ilj ~B

1 8~B
1 [8
A3

GRP-

~

Global
Routing
Pool

Global Routing Pool
(GRP)

Q.

B~~I

I~~B

B~'~I

1'1!B
I gB

E1

~ c

ORPOutput
Routing
Pool

CLKClock
Distribution
Network

B! 1

~

----",

@0~~~

III

Scan

~[§J@J~~

~~0~~

---- ----

0_
OT""C\llll:lII:

I output Routing Pool (ORP) I

I Outeut Routin~ Pool (ORP) I

dddSS

In ut us

In ut Bus

~
0849

Generic Logic Block (GLB)
The key element in the pLSI and ispLSI architecture is the
Generic Logic Block (GLB). This powerful logic block
provides a high input-to-output ratio for best logic efficiency. The GLB (figure 2) used in the pLSI and ispLSI
1000 and 2000 families feature 18 inputs which drive an
array of 20 Product Terms (PTs). These product terms
feed four outputs which effectively handle both wide and
narrow gating functions. The pLSI and ispLSI 3000 family

utilizes a Twin GLB which delivers wider logic functionality. The Twin GLB accepts 24 inputs and feeds two arrays
of 20 Product Terms that ultimately drive two sets of four
outputs.
The architectural flexibility of the pLSI and ispLSI GLB,
combined with its optimum input-to-output ratio, allows
the GLB to implement virtually all 4-bit and 8-bit MSI
functions.

2-4

1994 Data Book

Introduction to pLSI and ispLSI
An additional element of architectural flexibility is the
Product Term Sharing Array (PTSA). The PTSA allows
the 20 PTs from the AND array to be shared with any and
all of the four GLB outputs. This ability to share PTs
between all of the four GLB outputs provides a highly
efficient means to implement complex state machines by
eliminating duplicate product term groups.
Each of the four outputs from the PTSA feeds into a
flexible Output Logic Macrocell (OLMC). consisting of a
D-type flip-flop with an Exclusive-OR gate on the input.

The OLMC allows each GLB output to be configured as
either combinatorial or registered. Combinatorial mode is
available as AND-OR or Exclusive-OR. Registered mode
is available as D. Tor J-K.
The power of the GLB is further enhanced by a flexible
clock distribution network. This network provides a choice
of clock signals to each GLB: global synchronous clock
signals or internally generated asynchronous product
term clock signals.

Figure 2. pLSI and ispLSI1000 and 2000 Family GLB
4 Output Logic

20 Product
Terms

Macrocelis

I
2
Dedicated
Inputs

16

I

\

I
Logic
Array

Inputs
From GRP

~

,

\

Registered
or

V Combinatorial

OLMC
Product
Term
Sharing
Array

• Combinatorial

f-T

AND-OR-XOR/

Outputs

V

4

• Registered

Outputs
toGRP,
ORP or 1/0

D, T,J-K
SynchlAsynch
Clocking

Figure 3. pLSI and ispLSI 3000 Family "Twin GLB"
20 Product
Terms

II

f-1o

24
Inputs
FromGRP

4 Output Logic
Macrocells

\

Registered
or

~

OLMC
Product
Term
Sharing
Array

V Combinatorial
Outputs
/V

• Combinatorial
AND-OR-XOR

T

.Reg~~V~_K
Synch/Asynch
Clocking

4
outputs
toGRP,
ORP or 1/0

Logic
Array
OLMC

To

Product
Term
Sharing
Array

2-5

Outputs
toGRP,
ORP or 1/0

• Combinatorial
AND-QR-XOR

T

• Reglf,,¥eJ_ K
SYQclilAsynch
Clocking

4

1994 Data Book

•

Introduction to pLSI and ispLSI
Figure 4. GLB: Multi-Mode Configuration

-PIoducrTerrn

1000
and 2000
~~. Family
.""'
....
~ llil GLB
_OR

tI::>~~o.

-

. rfbJ lmI

~~OO

-

-

-- Control
Funclone

......
D~!Yl'::h

ProdUdTenn

3000
Famil y
GLB

e:..."':"'~R r - - 1mI

.0

tD-1JB~o,

rz. 3)

r:z0

..

'PT~

lp

fE)
d~~

7.''''''

-.

u~ ~O2~
I""

PodOUtput

~01=1n1J

f!~ 1m
U

~~oo

r---

-

AND Array

C onttol
Function.

Standard Configuration

Exclusive-XOR Configuration

o

GLB Outputs Comprised of 4,4, 5 and 7 Product
Terms

o

The PTSA can Combine up to 20 Product Terms
per GLB Output to Meet the Needs of Both Wide
and Narrow Logic Functions

o
o

For Speed-Critical Timing Paths

o

Utilizes Powerful Exclusive-XOR Architecture

o

Greatfor Counters, Comparators and ALU Functions

Single PT Configuration

o

High-Speed Bypass Configuration

o
o

....

Small Logic Functions at Fast Speed

Multi-Mode Configuration

Bypasses the PTSA and the Internal Exclusive·
OR gate of the OLMC

o

Individual Outputs
Configurable

Provides Four Product Terms per Output

o

PTSA Gives Flexibility in the Number and Selection of Product Terms per Output

Supports Design of Fast Address Decoders

2·6

are

Independently

1994 Data Book

Introduction to pLSI and ispLSI
Prototype Board Designs

Security Cell
A security cell is provided in the pLSI and ispLSI devices
to prevent unauthorized copying of the array patterns.
Once programmed, this cell prevents further read access
to the functional bits in the device. This cell can only be
erased by reprogramming the device, so the original
configuration can never be examined once this cell is
programmed.

Device Programming
pLSI and ispLSI devices can be programmed using a
Lattice-approved device programmer, available from a
number of third party manufacturers. Complete
programming of the device takes only a few seconds.
Erasing of the device is automatic and is completely
transparent to the user. In-system programming is also
available with ispLSI devices which allows programming
on the circuit board using Lattice programming algorithms
and standard 5V system power.

Latch-up Protection
pLSI and ispLSI devices are designed with an on-board
charge pump to negatively bias the substrate. The
negative bias is of sufficient magnitude to prevent input
undershoots from causing the internal circuitry to latchup. Additionally, outputs are designed with n-channel
pull-ups instead of the traditional p-channel pull-ups to
eliminate any possibility of SCR induced latching.

In-system programmability
Lattice's ispLSI devices (in-system programmable) are
the industry'S only high-density programmable logic family offering non-volatile, in-system reconfigurability.
ispLSI devices are available in all three families: 1000,
2000 and 3000. The ispLSI devices are 100 percent
functionally and parametrically compatible with their pLSI
counterparts, with the added capability for 5-volt insystem programmability and reprogrammability.
Complex logic functions can be implemented in multiple
ispLSI devices with complete on-board configurability.
In-system programming of a multiple ispLSI chip solution
is easily achieved through a proprietary in-system erase/
program/verify technique.

In-system programming allows you to program and modify
your logiC designs "in-system" without removing the
device(s) from the board. This accelerates the system
and board-level debug process and enables you to
define the board layout earlier in the design process.

Fine Pitch Package Handling
When programming traditional PLDs, manual handling is
required during both design/debugging and manufacturing stages. When using PQFPs or TQFPs, fragile leads
as thin as 0.5 mm can easily bend in the programmer
socket causing coplanarity damage. With ispLSI, you
can solder these packages onto your printed circuit
board and still program and reprogram the devices
during debugging and manufacturing - without ever
losing a single part due to bent leads.

Reconfigurable Systems
Your options become boundless when you have the
ability to change the functionality of devices already
soldered on a p.c. board. You can now implement multiple hardware configurations with the same circuit board
design. A variety of protocols or system interfaces can be
implemented on a generic board as the last step in the
manufacturing flow.

Easier Field Updates
With software reconfigurable systems, field updates are
as easy as loading a new configuration from a floppy or
downloading it through a modem.

Enhanced Manufacturing Flow with ispLSI
Perhaps the most exciting benefit of the ispLSI family is
its potential to streamline the manufacturing process by
eliminating the separate programming and labeling steps
usually associated with PLDs. Quality is enhanced when
product handling steps are reduced, in this case, those
associated with programming, labeling and reinventorying multiple device types. Eliminating socketing
further improves quality and reduces board cost. Figure
6 shows the enhanced manufacturing with the ispLSI
device.

In-system programmability can revolutionize the way you
design, manufacture and service systems.

2-7

1994 Data Book

•

I

Introduction to pLSI and ispLSI
Figure 5. In-System Programmable Graphics Board

•

ispLSI Devices

•

ISP Interface
0290D

Figure 6. Manufacturing Flow Comparison
Standard Flow
Using PLDslFPGAs

Enhanced Flow
Using ispLSI Devices

All necessary programming is achieved via five TTL-level
logic interface signals (see figure 7). These five signals
control the on-chip programming circuitry, which protects
against inadvertent reprogramming via on-chip state
machines. The ispLSI family can also be programmed
using popular third-party logic programmers.

Figure 7. In-System Programming Interface (MultiChip Solution)
501
SOD
MODE
SCLK
ispEN

Board Test
• Diagnostics Using ispLSI
• Final Programming
• Final Board Test

I

S-wlra ISP
Programming
Interface

ispLSI

2-8

1994 Data Book

Introduction to pLSI and ispLSI
General Description

Boundary Scan
An emerging trend in board-level testing is boundary
scan test, an attractive feature helping designers test
system boards efficiently while lowering test and manufacturing costs. The pLSI and ispLSI 3000 family offers
dedicated IEEE 1149.1 boundary scan support for all test
functions required by the standard. By using pLSI and
ispLSI devices you not only eliminate expensive "bed-ofnails" testers but also simplify testing of surface-mount
boards, multi-layer boards and boards using fine-pitch
packages. Boundary scan is ideal wherever tight board
layout limits access to logic signals.

All pLSI and ispLSI families are supported by Lattice's lowcost pDS software. It runs on IBM-compatible (386/486/
Pentium) PCs with Microsoft®Windows.
The graphical user interface employs an easy-to-use
mouse and pull-down menu driven approach. Combined
with Boolean logic data entry using an ABEL TM-like
syntax, pDS makes design entry with pLSI and ispLSI
quick and straightforward (see figure 8).
Figure 8. pDS Design Flow
• Boolean Equations
• Macros (>275)
• "ABEL"-Like Syntax

It only takes 4 pins to implement the boundary scan
interface. The ispLSI3000 devices share the four boundary scan signals with the in-system programming pins.
This enhances the testability of system designs allowing
logic to be reconfigured to improve controllability and
observability.

• Logic Minimization
• Checks for Signal Availability

Lattice Development Systems
• Automatic
• Optimized
• Fast

The Lattice pLSI/ispLSI Development System (pDS)
software is used to implement designs in pLSI and ispLSI
devices. Design alternatives can be quickly implemented
using Lattice's low cost pDS software or the pDS+ family
of Fitters that interface with third-party development
software packages. This section describes the pDS and
pDS+ Development Systems. Programmer support is
also discussed.

·Viewsim
• EDIF Compatible

• JEDEC File Generation
• Download to Programmer
or to Device (ispLSI)

pLSl/ispLSI Development System (pDS)
Features

0292A

o

High-Performance, Low-Cost Development
Environment

o
o
o

Supports pLSI and ispLSI Device Families
Boolean Logic and Text File Design Entry
Windows Based Graphical User Interface

The pDS software supports over 275 macros to assist the
deSign process. These macros cover most TTL functions, from gate primitives to 16-bit counters. The software
also supports user-definable macros which can be modifications of existing macros or custom creations.
The pDS software automatically verifies the deSign,
performs logic minimization and checks for signal availability.

DOver 275 Macros Available

o
o
o

Automatic Place and Route

o

JEDEC File Download Direct to Programmer or
ispLSI Device

The Lattice Place and Route software assigns pins and
critical speed paths while routing the design.

Static Timing Table
Logic Simulation with Viewlogic™ Viewsim TM

Quick compilation speeds the design, debug and rework
process dramatically. Incremental design techniques are
also supported.

2-9

1994 Data Book

Introduction to pLSI and ispLSI
Timing and functional simulation is available from Lattice,
using Viewsim simulation software.

pLSI and ispLSI devices. No proprietary, expensive, high
pin-count programmers are required.

The Windows graphical user interface makes
programming easy, using pull-down menus, intuitive
point-and-click commands and self explanatory
instructions. Without any up-front training, designs can
be completed within hours instead of days or weeks.

High pin-count socket adapters are available from Emulation Technology, Procon Technology, EDI Corporation
and Logical Systems Corporation.

pLSl/ispLSI Development System Plus (pOS+)
Features

o
o
o
o
o
o
o
o

Additionally, the ispLSI family can be programmed on the
board (in-system), which eliminates the need for a standalone programmer. For specific details refer to the
Lattice Programming Tools Guide available from your
local Sales Representative.

Table 2. Programming Support

Supports pLSI and ispLSI Device Families
Schematic Capture, State Machine, Design Entry
HDL, and Boolean Equations

Programmer Vendor

Model
Pilot-U84

Expanded Macro Library (>300)
Advin Systems

Automatic Logic Minimization and Partitioning

Pilot-U40
Pilot-GUGCE

Automatic Place and Route
Logic and Timing Simulation

BP Microsystems

PLD-1128

EDIF Compatible

CP-1128

JEDEC File Download Direct to Programmer or
ispLSI Device

2900
Data 110

General Description

3900
Unisite 40/48

For higher level design entry environments, Lattice offers
pDS+ development software packages, which expand on
the core capabilities of pDS. Schematic capture, state
machine, HDL and Boolean entry are supported, along
with an expanded macro library.

Allpro 40
Logical Devices
Allpro 88
SMS Micro Systems

System 3000

The pDS+ software utilizes industry standard third-party
design environments such as Viewlogic's Viewdraw™
and Data 1I0's ABEL.
Running on IBM compatible (386/486/Pentium) PCs or
workstation platforms, pDS+ software supports automatic
logic minimization and partitioning as well as place and
route, resulting in high logic utilization.
For logic and timing simulation, support is available from
Lattice through Viewlogic Viewsim simulation tools.

Third Party Programming Support
The pLSI and ispLSI families are supported by popular
third-party logic programmers including Data 110, Logical
Devices, BP-Microsystems, Stag, System General, SMS
Micro Systems and Advin. Table 2 describes each
vendor's specific programmer models that support the

Sprint Expert

Stag
ZL30/A
System General

TURPRO-1

isp Engineering Kit
The ispLSI family may also be programmed with Lattice's
isp Engineering Kit Model 100 for PCs and Model 200 for
Sun workstations. The kit is designed for engineering
purposes only and is not intended for production use. By
connecting an 8 wire cable to the parallel printer port of
a PC, JEDEC files can be easily downloaded into the
ispLSI device. Additionally, this cable can be connected
directly to the circuit board facilitating on-board in-system
programming.

2-10

1994 Data Book

1000 Family
Architectural Description
pLSI and ispLSI 1000 Family Introduction
The basic unit of logic for the pLSI and ispLSI families is
the Generic Logic Block (GLB). Figure 1 illustrates the
pLSI1032 with its 32 GLBs labelled AO, A1 .. D7. Each
GLB has 18 inputs, a programmable AND/ORIXOR array, and four outputs which can be configured to be either
combinatorial or registered. Inputs to the G LB come from
the Global Routing Pool (GRP) and dedicated inputs. All
of the GLB outputs are brought back into the GRP so that
they can be connected to the inputs of any other GLB on
the device.
As an example, the pLSI 1032 has 64 1/0 cells, each of
which is directly connected to an 1/0 pin. Each 1/0 cell
can be individually programmed to be a combinatorial
input, registered input, latched input, output or bi-directionall/O pin with 3-state control. Additionally, all outputs
are polarity selectable, active high or active low. The
signal levels are TTL compatible voltages and the output
drivers can source 4 rnA or sink 8 rnA.
The I/O cells are grouped into sets of 16 as shown in
figure 1. Each of these 1/0 groups is associated with a
Megablock through the use of the Output Routing Pool
(ORP).

Eight GLBs, 16 I/O cells, one ORP and two dedicated
inputs are connected togetherto make a Megablock. The
outputs of the eight GLBs are connected to a set of 16
universal 1/0 cells by theORP. Each Megablockshares
a common Output Enable (OE) signal. The pLSI 1032
device, shown in figure 1 contains four Megablocks.
The GRP has as its inputs the outputs from all ofthe GLBs
and all of the inputs from the bi-directional 1/0 cells. All
of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the devices are selected using the Clock
Distribution Network. The dedicated clock pins
(YO, Y1, Y2 and Y3) are brought into the distribution
network, and five outputs (CLK 0, CLK1 , CLK 2, 10CLK
oand 10CLK 1) are provided to route clocks to the GLBs
and 1/0 cells. The Clock Distribution Network can also be
driven from a special GLB (CO on the pLSI and ispLSI
1032 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.

Figure 1. pLSI1032 Functional Block Diagram

MTLofa~

.,.5

~:rl-------------'

I .,,,.,,,""""""
I .,,,"'".
I
I .,,,""
.....
,::~

;;:m:6
;;:m:9

co

~

f

Kl6

!

litHO

::: il~:'

J

;'~
.:-~

.:-:.

.,."

',':'

"".

.::.:

.:.;.

11013,·:·.·
VOl4 ::'-!<
110 IS
~~.

"H'
""
.,
,,~

':",

i

:Et:=:=~

INO
IN' :~ •• _~ ______ /

VOI,Q VOt.O
'61718111

IIOJ.QVOI,()
2O:i!1Z!T.l

I.Or'()KlI,o

242526'0

2-11

1994 Data Book

1000 Family Architectural Description
Generic Logic Block
The Generic logic Block (GlB) is the standard logic
block of the lattice high-density plSI and isplSI devices.
A GlB has 18 inputs, four outputs and the logic necessary to implement most standard logic functions. The
internal logic of the GlB is divided into four separate
sections: the AND Array, the Product Term Sharing Array
(PTSA), the Reconfigurable Registers, and the Control
Functions (see figure 2). The AND array consists of 20
product terms which can produce the logical sum of any
of the 18 GlB inputs. Sixteen of the inputs come from the
Global Routing Pool, and are either feedback signals
from any of the GlBs or inputs from the external flO cells.
The two remaining inputs come directly from two dedicated input pins. These signals are available to the
product terms in both the logical true and the complementedforms which makes boolean logic reduction more
efficient.
The PTSA takes the 20 product terms and routes them
to the four GlB outputs. There are four OR gates, with
four, four, five and seven product terms each (see figure

2). The output of any of these OR gates can be routed to
any of the four GlB outputs, and if more product terms
are needed, the PTSA can combine them as necessary.
In addition, the PTSA can share product terms similar to
an FPLA device. If the user's main concern is speed, the
PTSA can use a bypass circuit which provides four
product terms to each output, to increase the performance of the cell (see figure 3). This can be done to any
or all of the four outputs from the GlB.
The Reconfigurable Registers consist of four D-type flipflops with an XOR gate on the input. The XOR gate in the
GlB can be used either as a logic element orto reconfigure the D-type flip-flop to emulate a J-K or T-type flip-flop
(see figure 4). This greatly simplifies the design of
counters, comparators and AlU type functions. The
registers can be bypassed if the user needs a combinatorialoutput. Each register output is brought back into the
Global Routing Pool and is also brought to the I/O cells
via the Output Routing Pool. Reconfigurable registers
are not available when the four product term bypass is
used.

Figure 2. GLB: Product Term Sharing Array Example

--

Inputs From
Global Routing Pool

o

1

2

3

4

5

6

7

8

Dedicated
Inputs
Product Term
Sharing Array

9 10 11 12 13 14 15 18 17

Reconfigurable
Registera
D.J-K, andT

03

02

~~obaJ

Routing
Pool and
OuIpul
01 Routing

Pool

00

AND Array

Control
Functions

CLKO
CLK1

CLK2
PTCIock
PTOutput _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ To Output

Enable

2-12

Enable Mux

1994 Data Book

1000 Family Architectural Description
Figure 3. GLB: Four Product Term Bypass Example
Inputs From
Global AolJIng Pool

Dedicated
1"1'''''

--------------------------~~
o 1 2 3 .. 6 e 7 8 II 10 11 12 13 14 15 18 17
03

02

~~bal
Routing
Pool and
Output

12

Routing
01 Pool

17
18

00

19

ANDArrl1i'/

PT Re ..t
Global RESET
Control

Functions

CLKO
CLK1
CLK2

MUX

PT Clock

PT~~~~ __- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~~~~p~~
Figure 4. GLB: XOR Gate Example
Input. From
Global Ro..ing Pool

Dedicated
I""uts

------------~------------~
o 1 2 3 • 5 IS 7 8 V 1011 12 13 14 15 18 17

Product Term Sharing
Arrl1i'/(XOR
Configuration Shown)

03

02

~~obal
Routing
Pool and
Output

01 Routing
Pool

00

AND Array

Control
Functions

-----------------------------------+,~~~:~

2-13

1994 Data Book

•

1000 Family Architectural Description
Generic Logic Block (continued)
The PTSA is flexible enough to allow these features to be
used in virtually any combination that the user desires. In
the GlB shown in figure 5, Output Three (03) is configured
using the XOR gate while Output Two (02) is configured
using the four Product Term Bypass. Output One (01)
uses one of the inputs from the five Product Term OR
gate while Output Zero (00) combines the remaining four
product terms with all of the product terms from the seven
Product Term OR gate for a total of eleven (7+4).
Various signals which control the operation of the GlB
outputs are driven from the Control Functions (see figure
5). The clock for the registers can come from any ofthree
sources developed in the Clock Distribution Network
(see Clock Distribution Network section) orfrom a product
term within the GlB. The Reset Signal for the GlB can
come from the Global Reset pin (RESET) or from a

product term within the block. The global reset pin is
always connected and is logically ·ORed" with the PT
reset (if used). An active reset signal always sets the Q
of the registers to a logic 0 state. The Output Enable for
the 1/0 cells associated with the GlB comes from a
product term within the block. Use of a product term for
a control function makes that product term unavailable
for use as a logic term. Referto the ProductTerm Sharing
Matrix (table 1) to determine which logic functions are
affected.
There are many additional features in a GlB which allow
implementation of logic intensive functions. These
features are accessible using the Hard Macros from the
software and require no intervention on the part of the
user.

Figure 5. GlB: Mixed Mode Configuration Example
Inputs From
Global Routing Pool

Dedicated
Inputs

--------------~----------~
o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Product Term
Sharing Array
3
n

•4

~
7
A

A
1nl
111

12
1.

15
1S'
1A

19

o Registers

~!!ndXOR

~

.:

+4 (Shared)

,)

~

~~~

D

h " ' .....

~

~

I

a x
~~
D

03

To
02 Global
Routing
Pool and
Output
Routing
Pool

JE> i?s-l~~o'
7+ 4 (Shared) I
PT's

~,
~~ 00

AND Array

PTReset
Global RESET
Control
Functions

ClK 0 _

r--

ClK 1 -'- MUX
ClK2PTCIockPTOutput
Enable

"--

K

r-MUX

"-~

2-14

To Output
Enable Mux

1994 Data Book

1000 Family Architectural Description
Product Term Sharing Matrix
This matrix shows how each of the product terms are
used in the various modes. As an example, Product
Term 12 can be used as an inputto the five input OR gate
in the standard configuration. This OR gate under
standard configuration can be routed to any of the four
GLB outputs. Product Term 12 is not used in the four

product term bypass mode. When GLB output one is
used in the XOR mode Product Term 12 becomes one of
the inputs to the four input OR Gate. If Product Term 12
is not used in the logic, then it is available for use as either
the Asynchronous Clock signal or the GLB Reset signal.

Table 1. Product Term Sharing Matrix
Product Standard Configuration
Four Product Term
Single Product Term
Term #
Output Number
Output Number
Bypass Output Number

3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

2

1

0

3

•• ••
•• ••

••
••
••
••
••
•••
••
••
••
•

•••
•
••
••
••
••
•

•••
•

••
••

••
••

•• ••
••• •••
•• ••
•• ••
•• ••
••

••
••
•••

2

1

0

3

2

1

0

•

•

•••
•

•

••
••

3

3

••
••

•
••
••

XOR Function
Output Number

2

2

••
••

1

1

••
••
•

Alternate
Function

0

0

.ClK/Reset

••
•••
•
•

·OE/Reset

The Megablock
A Megablock consists of eight GLBs, an ORP, 16 liD
cells, two dedicated inputs and a common product term
DE. Each of these will be explained in detail in the
following sections. These elements are coupled together
as shown in figure 6. The various members of the pLSI
and ispLSI families combine from one to eight Megablocks
on a single device (see table 2).
Forthe 1000 Family, the eight GLBs within the Megablock
share two dedicated input pins. These dedicated input
pins are not available to GLBs in any other Megablock.
These pins are dedicated (non-registered) inputs only

and are automatically assigned by software. The product
term DE signal is generated within the Megablock and is
common to all 16 of the liD cells in the Megablock. The
DE signal can be generated using a product term (PT19)
in any of the eight GLBs within the Megablock (see the
section on the Output Enable Control for further details).
Because ofthe shared logic within the Megablock, signals
which share a common function (counters, busses, etc.)
should be grouped within a Megablock. This will allow the
user to obtain the best utilization of the logic within the
device and eliminate routing bottlenecks.

2-15

1994 Data Book

1000 Family Architectural Description
Table 2. Device Resources
pLSI and ispLSI Devices

Megablocks

GLBs

1016
1024
1032

2
3
4
6

16
24
32
48

1048/1048C

I/O Cells

32
48
64
96

Dedicated Inputs

4
6
8
10/12
Table2-001S8

Figure 6. The Megablock Block Diagram

Input Routing
Signal inputs are handled in two ways within the device.
First, each 1/0 cell within the device has its input routed
directly to the GRP. This gives every GLB within the
device access to each 1/0 cell input. Second, each
Megablock has two dedicated inputs which are directly
routed to the eight GLBs within the Megablock. Both
input paths are shown in figure 6.

The Output Routing Pool
The ORP routes signals from the GLB outputs to 1/0 cells
configured as outputs or bi-directional pins (see figure
7). The purpose of the ORP is to allow greater flexibility
when assigning 1/0 pins. It also simplifies the job for the
routing software which results in a higher degree of
utilization.

By examining the ORP in figure 7, it can be seen that a
GLB output can be connected to one of four 1/0 cells.
Further flexibility is provided by using the PTSA, (figures
2 through 5) which makes the GLB outputs completely
interchangeable. This allows the routing program to
freely interchange the outputs to achieve the best
routability. This is an automatic process and requires no
intervention on the part of the user.
The ORP bypass connections (see figure 8) further
increase the flexibility of the device. The ORP bypass
connects specific GLB outputs to specific 1/0 cells at a
faster speed. The bypass path tends to restrict the
routability of the device and should only be used for
critical signals.

2-16

1994 Data Book

1000 Family Architectural Description
Figure 7. Output Routing Pool
...-_--, ,--_--, ,--_~ ...-_--, ,..-_--, ,--_~ .--_~ ,..-_-, 1/0 Cell Inputs

toGRP

16

m-;---I:

ORPj-i-1--i---i-i ---m---I---i--i--i--~--i--i-.---1--i--m---I-

Figure 8. Output Routing Pool Showing Bypass
...-_--, ...-_--, ...-_--, r - - " ' " r - - " ' " ,-_ _--,

Inputs
...----, ...---, 1/0 Cell
to GRP

16

ORP--:,
____

________

____

___

____

_____________

,

__J

I/O Cell
The 1/0 cell (see figure 9) is used to route input, output
or bi-directional signals connected to the 1/0 pin. The two
logic inputs come from the ORP (see figure 9). One
comes from the ORP, and the other comes from the
faster ORP bypass. A pair of multiplexers select which
signal will be used, and its polarity. The Output Enable
of the I/O cell is controlled by the OE signal generated
within each Megablock.
As with the data path, a multiplexer selects the signal
polarity. The Output Enable can be set to a logic high
(enabled) when an output pin is desired, or logic low
(disabled) when an input pin is needed. The Global
Reset (RESET) signal is driven by the active low chip
reset pin. This reset is always connected to all GLB and
I/O registers. Each I/O cell can individually select one of

the two clock signals (IOCLK 0 or 10CLK 1). These clock
signals are generated by the Clock Distribution Network.
Using the multiplexers, the I/O cell can be configured as
an input, an output, a 3-stated output or a bi-directional
1/0. The D-type register can be configured as a level
sensitive transparent latch or an edge triggered flip-flop
to store the incoming data. Figure 10 illustrates some of
the various I/O cell configurations possible.
There is an active pull-up resistor on the I/O pins which
is automatically used when the pin is not connected. An
option exists to have active pull-up resistors connected to
all pins. This improves the noise immunity and reduces
Icc for the device.

2-17

1994 Data Book

•

1000 Family Architectural Description
Figure 9. 110 Cell Architecture

From OE MUX - - - - - - - - - - - - -..
Output
Enable

Active
Pull Up

From Output
Routing Pool
From Output
Routing Pool
Bypass

I/O Pin

To Global _ _ _ _ _ _ _ _-<
Routing Pool

10CLKO
10CLK 1

Note:
From Global

RESET-------------------------------~

o

Represents an E2CMOS Cell.

Figure 10. Examples of 110 Cell Configurations

~

~

Input Buffer

Output Buffer

Q
1I0Cell _ _- I
Clock
Inverting Output Buffer
Latch Input

1I0Cell _ _-I>
Clock

Bi-Directional
I/O Pin With
Registered Input

>---.-iC I/O Pin

Output Buffer with
3-State Enable

I/O Cell _ _ _ _--I>
Clock

Registered Input

Input Cells

Output Cells

2-18

Bi·Directional Cells

1994 Data Book

1000 Family Architectural Description
The Output Enable Control
One OE signal can be generated within each GLB using
the OE Product Term (PT19). One of the eight OE
signals within a Megablock is then routed to all of the 1/0
cells within that Megablock (see figure 11). This OE
signal can simultaneously control all of the 16 1/0 cells
which are used in 3-state mode. Individual 1/0 cells also
have independent control for permanently enabling or

disabling the output buffer (refer to the 1/0 cell section).
Only one OE signal is allowed per Megablock for 3-state
operation. The advantage to this approach is that the OE
signal can be generated in any GLB within the Megablock
which happens to have an unused OE product term. This
frees up the other OE product terms for use as logic.

Figure 11. Output Enable Control for a Megablock

) - - - - - . . 4 - - - - - . . - 1 - - - - - - - - - - - -.......----_-+----- ToOthe,
) - - - P + 4 - - - - _ + i - - - - - - - - - - -.......+-t----rl-+----- 1/0 Cells
ispLSI and pLSI

1048C Devices
Only

2-19

1994 Data Book

1000 Family Architectural Description
Global Routing Pool
The GRP is a lattice proprietary interconnect structure
which offers fast predictable speeds with complete connectivity. The GRP allows the outputs from the GlBs or
the I/O cell inputs to be connected to the inputs of the
GlBs. Any GlB output is available to the input of all other
GlBs, and similarly an input from an I/O pin is available

as an input to all of the GlBs. Because of the uniform
architecture of the plSI and isplSI devices, the delays
through the GRP are both consistent and predictable.
However, they are slightly affected by GlB loading as
shown in the example plSI1 032-80 GlB loading Delay
graph (see figure 12).

Figure 12. Example Graph of GRP Delay vs GLB loading
5.0
4.5

en 4.0
c::

>- 3.5
as

pLSI 1032-80

co
03.0

c..

II:
C!)

2.5
2.0
1.5 1

4
GLB Loads

Clock Distribution Network
The Clock Distribution Networks are shown in figure 13.
They generate five global clock signals ClK 0, ClK 1,
ClK 2 , 10ClK 0 and 10ClK 1. The first three, ClK 0,
ClK 1 and ClK 2 are used for clocking all the GlBs in the
device. Similarly, 10ClK 0 and 10ClK 1 signals are used
for clocking all of the 1/0 cells in the device. There are four
dedicated system clock pins (YO, Y1, Y2, Y3), three for
the plSI and isplSI1016 (YO, Y1, Y2), which can be
directed to any GlB or any 1/0 cell using the Clock
Distribution Network. The other inputs to the Clock Distribution Network are the four outputs of a dedicated
clock GlB ("CO" for the plSI 1032 is shown in figure 1).
These clock GlB outputs can be used to create a userdefined internal clocking scheme.

signal ClK o. The outputs of the clock GlB in turn can
generate a "divide by" signal of the ClK 0 which can be
connected to ClK 1, ClK 2, 10ClK 0 or 10ClK 1 global
clock lines.
All GlBs have the capability of generating their own
asynchronous clocks using the clock Product Term
(PT12). ClK 0, ClK 1 and ClK 2 feed to their corresponding clock MUX inputs on all the GlBs (see figure
2).
The two 1/0 clocks generated in the Clock Distribution
Network 10ClK 0 and 10ClK 1, are brought to all the II
cells and the user programs the 1/0 cell to use one of
the two.

o

For example, the clock GlB can be clocked using the
external main clock pin YO connected to global clock

2-20

1994 Data Book

1000 Family Architectural Description
Figure 13. Clock Distribution Networks

pL5 I and ispL511024,
1032 and 1048

Generic logic
Block "CO"
00 01 02 03

pl51 and ispl511016

Clock Distribution
Network

Generic logic
Block "BO"
0001 02 03

Clock Distribution
Network
ClKO
ClK 1
ClK2
10ClKO
IOClK1

YO Y1

ClKO
ClK 1
ClK2
10ClKO
10ClK 1

YO Y1* Y2
ClK!
Reset

Y2 Y3

Dedicated Clock
Input Pins

Dedicated Clock
Input Pins

'Note: Pin Y1 has the Ciack and
Reset Functions Multiplexed
on the plSI and IsplS11016,
Selection is controlled in
the software tools.

Timing Model
The task of determining the timing through the device is
simple and straightforward. A device timing model is
shown in figure 14. To determine the time that it takes for
data to propagate through the device, simply determine
the path the data is expected to follow, and add the
various delays together (figure 15). Critical timing paths

are shown in figure 14, using data sheet parameters.
Note that the Internal timing parameters are given for
reference only, and are not tested. (External timing
parameters are tested and guaranteed on every device).

Figure 14. pLSI and ispLSI Timing Modell
1/0 Cell

GRP

GLB

ORP

1/0 Cell

~------------------- ~~

'Note: Y1 and Y2 only forthe plSI and isplS11016.

2-21

1994 Data Book

•

,

1000 Family Architectural Description
Figure 15. pLSI and ispLSI Timing Model Examples1
Combinatorial Paths
tpd1
#1

tiobp
#20

+
+

tgrp4
#28

+
+

t4ptbp
#33

+
+

torpbp
#46

+
+

tOb
#47

tpd2
tiobp
#2
#20
Registered Paths

+
+

tgrp4
#28

+
+

txoradj
#36

+
+

torp
#45

+
+

tob
#47

tsu = Logic
+
th
= Clock(max) +
tco = Clock(max) +
Specific Examples:

Regsu
Regh
Regco

-

Clock(min)
Logic
Output
+

tgrp4
#28

+
+

t4ptbp)
#33)

+
+

tgsu
#38

-

tgyO(min)
#50

(tiobp
(#20

+
+

tgrp4
#28

+
+

t4ptbp)
#33)

General Form:

tsu1 =
#6

(tiobp
(#20

+
+

= tgyO(max) +
#50
+

tgh
#39

tc01 = tgyO(max) +
#7
#50
+

tgco
#40

+
+

(torpbp
(#46

+
+

tob)
#47)

tsu2 =
#9

tgrp4
#28

+

txoradj)
#36)

+
+

tgsu
#38

+ tgyO(min)
#50
+

(tiobp
(#20

+
+

tgrp4
#28

+
+

(torp
(#45

+
+

tob)
#47)

th1
#8

(tiobp
(#20

+
+

= tgyO(max) +
#50
=
+

tgh
#39

tco2 = tgyO(max) +
#10 =
#50
+

tgco
#40

th2
#11

+
+

txoradj)
#36)

1. The timing parameter reference numbers refer to the Internal Timing Parameters contained in the individual data sheets.

Circuit Timing Example
Figure

16. Timing Calculation Example

A design requires two logic levels (each uses the 20PTXOR path). The design then uses a GLB register before exiting
the device using the ORP bypass. Calculate tsu. th and teo.

~
~
~

Logic Level
#1
20PTXOR

I----I~

Logic Level
#2
I----I~ GLB Reg
20PTXOR

ORP
Bypass

YO

2-22

1994 Data Book

1000 Family Architectural Description
Figure 16. Timing Calculation Example (continued)
tsu

Logic +Reg su - Clock (min)

19.5 ns

(tiobp + tgrp4 + t20ptxor + tgbp + tgrp4 + t20ptxor) + tgsu - tgyO(min)
(#20 + #28 + #35 + #37 + #28 + #35) + #38 - #50
(2.0 + 2.0 + 8.0 + 1.0 + 2.0 + 8.0) + 1.0 - 4.5

th

Clock (max) + Reg h - Logic

-14.0 ns

tgyO(max) + tgh - (tiobp + tgrp4 + t20ptxor + tgbp + tgrp4 + t20ptxor)
#50 + #39 - (#20 + #28 + #35 + #37 + #28 + #35)
4.5 + 4.5 - (2.0 + 2.0 + 8.0 + 1.0 + 2.0 + 8.0)

tco

Clock (max) + Reg co + Output

10.0 ns

tgyO(max) + tgco + (torpbp + tob)
#50 + #40 + (#46 + #47)
4.5 + 2.0 + (0.5 + 3.0)

•

1 . The delay values used are for a pLSI 1032-80 device.

2-23

1994 Data Book

I

Notes

2-24

1994 Data Book

2000 Family
Architectural Description
pLSI and ispLSI 2000 Family Introduction
The basic unit of logic of the pLSI and ispLSI2000 family
is essentially the same as that of the pLSI and ispLSI
1000 family. However, there are some specific architectural differences: Global clock structure, I/O Cell and OE
structure, and ORP structure. A functional block diagram
of the 2032 device is shown in figure 1. These architectural differences are described in detail below.

Global Clock Structure
The clock GLB distribution network of the 1000 family has
been eliminated and replaced by three dedicated global

GLB clock input signals CLKO, CLK1 , and CLK2. These
three clocks are used for clocking all the GLBs configured
as registers in the device. They feed directly to the GLB
clock input via a clock multiplexer. CLKO is associated
with system clock pin YO, CLK1 corresponds to system
clock pin Y1, and finally CLK3 corresponds to system
clock pin Y2. This is illustrated in figure 2. The GLB
global clocks do not have inversion capability, but all
GLBs continue to have the capability of generating their
own asynchronous clocks using the clock product term
(PT12) with inversion capability. The GLB global clocks
and the GLB product term clock feed to their corresponding clock multiplexer shown in figure 3.

Figure 1. pLSI 2032 Functional Block Diagram

GOEO

Global Routing Pool
(GRP)

MODE.
ispEN

II
YO
Y1'
SClKIY2

*Nole: Y1 and RESET
are munlplexed
on the same pin
0139B(1)ispi2(XXl

2-25

1994 Data Book

•

2000 Family Architectural Description
Figure 2. Global Clock Structure
Clock Distribution
r----------------l~

ClK 0

r---------------l~ClK1
r---------~ClK2

0095A3isp/2000

Dedicated Clock
Input Pins
Figure 3. GLB with Clock Multiplexer Scheme

Inputs From
Global Routing Pool

Dedicated
Inputs

--------------~--------------- ~
o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Product Term
Sharing Array

D Registers
3 PT's and

0

~
,
4
5

~
7
8

~
11
12

l14
15

~
1tr
18
19
0133A/2000

AND Array

~~

~

~

h

IE>

4 PT Bypass

Single PT

~

-=
7 +4 PT's

~

~ ~O3
I

~O2

II
I
II~Ol
i
V ~OO

To
Global
Routing
Pool and
Output
Routing
Pool

PTReset
Global RESET

Control
Functions

PTCIOC~~CLKO
CLKl
CLK2

MUX

-

PTOutput
Enable

Output
•ToEnable
Mux
0133A/2000

2-26

1994 Data Book

2000 Family Architectural Description
VO Cell and OE Structure
The reconfigurable input register or latch has been removed to simplify the 1/0 cell architecture. Each 1/0 cell
can be individually programmed to be a combinatorial
input, combinatorial output, or a bi-directionall/O pin with
3-state control. With the simplified 1/0 cell architecture,
the 1/0 clocks have also been removed. This is illustrated
in figure 4. The product term output enable (PTOE)

I

signal is still generated within each GLB using product
term 19. The PTOE is generated in one of the eight
GLBs. In addition to the PTOE, there is a global output
enable (GOE) pin which can control any of the device's
3-state output buffers. The multiplexing between the
GOE and PTOE is illustrated in figure 5. The 2032 device
has one GOE, and the 2064 and 2096 devices each have
2 GOEs.

Figure 4. pLSI and ispLSI 2000 Family 110 Cell Architecture

GlobalOEO
Megablock OE

Programmable
Pull Up

MUXI---i

Vee

ORPMUX
ORP Bypass

To Global
Routing Pool

--------------<
0138A-712000

Note:

o

Represents an E2CMOS Cell.

Figure 5. pLSI and ispLSI 2000 Family Output Enable Controls

2-27

1994 Data Book

•

2000 Family Architectural Description
32 GLB outputs feed only 16 associated I/O cells. In this
device family, 32 GLB outputs of a megablock can feed
32 I/O cells. Output routability has doubled. This is
illustrated in figure 6. Each GLB output has an ORP
bypass capability so more designs can have critical
output signals. This is shown in figure 7.

Output Routing Pool (ORP)
Each megablock now contains two ORPs to increase
output routability. A set of four GLBs is associated with
one of the two ORPs within the megablock. The 16
outputs of the four GLBs within a megablock will feed to
any ofthe 16 associated I/O cells. In the 1000 family, the

Figure 6. pLSI and ispLSI 2000 Family Output Routing Pool
I/O Cell Inputs

10 :~ 3JI 0 :~ 31l 0 ~ 3J l0 :~ 3J
,- --

- --

-

,,,

--

-

-

-

--

-

--

-

-- -

-

-

-

-- -

- -

I

r

'" I~

I/O Cells---+

III "' ....

i«'

~

- -

.- --

,,, '''
,,, '''
,,, '''
,'

-

~

0

-~

,
ORP-,

,,
,,,

I

J

'.

toGRP
/'

:~ 311 0 : ; 311 0 :~ 311 0 :~ 31
- - - -- - - - -- - - - - -- - - - - -,,

-

,,
,,,

"

V~2

,

,,,
-

--

-

--

-

t!!

-

N

-

--

-

-

...

- - -- - - -

....

I

,

__ J

! ~~'"

0031E1:2000

Figure 7. pLSI and ispLSI 2000 Family Output Routing Pool Showing Bypass

I t~ 3 I
0

,,
,,,

0

:~ 3 II 0 1~ 3J l0 t~ 3J I0 t~ 311 0 ~~ 3 II 0 1A~ 311 0 t~ 31

- - - - -- - - - - -- - - - - - -- -

-

-

- - -- - - - - -- - - - - - -- -

- - ,,

,
,
,,,
- - - ------

I

"
"
"
"

11

t1

~'"

III

r

'"

- - -- - - - - - - -- -

"

- -

_I" 1_

-

11

11

"' ....

- - - -- - - - - -- - - - - -- - -

ta.C>

t

III

:!!'"

~

2-28

I
I

I

t1
N

....

III
I Jl

f/ ~2

,

"

-

;'

,,,
,,,
,,,

"
"
"
"

ORP--,,

I/O Cell Inputs
tO~RP

_ __ t

C>~

0034B12OO0

1994 Data Book

2000 Family Architectural Description
Timing Model
The task of determining the timing through the device is
simple and straightforward. A device timing model is
shown in figure 8. To determine the time that it takes for
data to propagate through the device, simply determine
the path the data is expected to follow, and add the
various delays together (figure 8). Critical timing paths

are shown in figure 8, using data sheet parameters. Note
that the Internal timing parameters are given for reference only, and are not tested. (External timing parameters
are tested and guaranteed on every device).

Figure 8. pLSI and ispLSI 2032 Timing Model
I/O Cell

GRP

GLB

ORP

I/O Cell

~~r------""-""-----,,-----A--..~
Feedback

Ded.ln

r----c#2=-S=----+-------,

I/O Pinr---I/o~D;;-e",-,-Y---o+----=;---I-l-'t--~:::--'--*~=--==":':""=---r+--'---:=-::"::::':----l~
#20
(Input)

R~m r--------------r--~-~

YO,1,2

>----------""'''-=-'-----------..1

GOEO

>-________

~~~6,~57~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ __J

Derivations of tsu, th and tco from the Product Term Clock1
tsu

2.2 ns
th

1.6 ns

Logic + Reg su - Clock (min)
(tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))
(#24 + #28 + #35) + (#38) - (#20 + #28 + #44)
(1.0 + 1.3 + 4.7) + (0.8) - (1.0 + 1.3 + 3.3)
Clock (max) + Reg h - Logic
(tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)
(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
(1.0 + 1.3 + 3.3) + (3.0) - (1.0 + 1.3 + 4.7)

Clock (max) + Reg co + Output
~ (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)
~ (#20 + #28 + #44) + (#40) + (#45 + #47)
8.8 ns = (1.0 + 1.3 + 3.3) + (0.7) + (1.3 + 1.2)

tco

1. Calculations are based upon timing specs for the pLSI and ispLSI 2032-135L

2-29

1994 Data Book

Notes

2-30

1994 Data Book

3000 Family
Architectural Description
pLSI and ispLSI 3000 Family Introduction
The basic unit of logic of the pLSI and ispLSI 3000 family
is closely related to that of the pLSI and ispLSI 1000
family. However, there are some notable architectural

differences: Boundary Scan, Megablock and GLB structure, Global clock structure, and lID cell structure. A
functional block diagram of the ispLSI 3256 device is
shown in figure 1. The architectural differences are
described in the following sections.

Figure 1. ispLSI 3256 Functional Block Diagram

~0~~~ ~~~~~

RESET

I Output Routing Pool (ORP) I

I Output Routing Pool (ORP) I

In utBus

In utBus

IIIII

-=='-===-===-==::::....-_-==-=='-===-===--_--'-=='---"

,,111::::....-_ _ _

0139AIsp/3256

2-31

1994 Data Book

•

!

3000 Family Architectural Description
Generic Logic Block
The Twin GlB is the standard logic block of the lattice
plSI and isplSI 3000 Family. This Twin GlB has 24
inputs, eight outputs and the logic necessary to implement most standard logic functions. The intemallogic of
the Twin GlB is divided into four separate sections: The
AND Array, the Product Term Sharing Array, the
Reconfigurable Registers, and the Control section.
The AND array consists of two 20 Product Term Sharing
Arrays which can produce the logical sum of any of the 24
Twin GlB inputs. These inputs all come from the GRP,
and are either feedback signals from any of the 32 Twin
GlBs or inputs from the external 110 Cells. All Twin GlB

input signals are available to the Product Terms in both
the logical true and complemented forms which makes
Boolean logic reduction easier.
The two Product Term Sharing Arrays (PTSA) take the 20
Product Terms each and allocate them to four Twin GlB
outputs. There are four OR gates, with four, four, five and
seven inputs respectively. The output of any of these
gates can be routed to any of the four Twin GlB outputs,
and if more Product Terms are needed, the PTSA can
combine them as necessary. If the user's main concern
is speed, the PTSA can use a bypass circuit with four
Product Terms to increase the performance of the cell.
This can be done to any or all of the eight outputs of the
Twin GlB.

Figure 2. Twin GlB: Product Term Sharing Array

sProcb:tTerm
__
01214

R........
D,J-K,endT

. 7 . "Oil 1211U 1111 17'11820"2221

tl~~
~O1

~

£>:

1-=

r:":I

~

~

rttr ~
~ ttt ~

-~iB=
......
gHU

PTOock

Twin

GLB

wx

Pod ...

~

x

02

x

01

..........

~

~

~
..........
_

.-/

l"~~
Ii~~
PTCiock

......

PTOU....

2-32

T.Output

I

tr~
ltt

GLB

_....

..,.

~

Q_~

~

eon...

PTOU\>U'

AND_

-

To
...-

lUI

~04
r:":I

~c. To

"'-

R_
=

""
~oe Pod

~

~~
X

GLB
aT

WX
I

_....

T.Output

1994 Data Book

3000 Family Architectural Description
Megablock Structure

ciated outputs. A total of 32 GLB outputs are fed to the

Four Twin GLBs make up a Megablock. Each GLB has a
maximum fan-in of 24 inputs, and no dedicated inputs
associated with any Megablock. A GLB has eight asso-

ORP. However, only 16 out of the 32 outputs feed to 16
I/O cells. The Megablock structure is shown in figure 3.

•

Figure 3. pLSI and ispLSI 3000 Family Megablock Block Diagram

I/O 1/0 1/0
Cell Cell Cell
o 1
2

1/0

1/0

Cell
3

Cell
15
0028A13256

Global Clock Structure
The global clock structure is made up of five global clock
input pins, YO, Y1, Y2, Y3, andY4. This is shown in figure
4. Three of the clock pins are dedicated for GLB clocks
and the remaining two clock pins are dedicated for 1/0
register clocks. The clock GLB generation network which

is designed into the 1000 device family has been removed so all input clock signals are fed directly to the
GLB clock input via a clock multiplexer. The GLB global
clocks do not have inversion capability, but the product
term clock does have inversion capability before it reaches
the clock multiplexer.

Figure 4. pLSI and ispLSI 3000 Family Global Clock Structure

C=>....----------- ClK 0
Y1 C=>
- CLK1
Y2 C=>
- CLK2
Y3 C=>
.. 10ClK 0
Y4 C=>
.. 10CLK 1
YO

0163Ai3256

2-33

1994 Data Book

3000 Family Architectural Description
I/O Cells
The VO cell structure architecture remains nearly the
same as the 1000 Family as illustrated in figure 5. Each
1/0 cell now contains Boundary Scan Registers as shown
in figure 8. An input pin has only one scan register as
shown in figure 9. A global test OE signal is hardwired to

all 1/0 cells and is useful to perform static testing of all the
3-state output buffers within the device. In a,ddition to the
test OE signal, two global OEs are connected to all 110
pins. The product term OE is shared between two
Megablocks resulting in twice the GLBs being able to use
a single OE signal. The Megablock OE signal and global
OE signals are fed to an OE multiplexer. The OE signals,
with the exception of the test OE, have inversion capability after going through the OE multiplexer as shown in
figure 6.

Figure 5. pLSI and ispLSI 3000 Family I/O Cell Architecture

TntOE---------------,
Global CEO
GiobalOE1
Megablock OEO

J-~---::-:-....,

FromORP

, -

Output
Enable

~-

Programmable
Pullup

----------,
See Boundary ,
Scan For Details :

From
ORPBypass

,_______ t-_-_-_-_1_~_If~~~_p~~n~j

To Global _ _ _C
Routing Pool

Q

0

IOCLKO
RfL

IOCLK 1

t"

Note:

0138A13256

Reprnents an E2cMOS Cell.

2-34

1994 Data Book

3000 Family Architectural Description
Figure 6. pLSI and ispLSI 3000 Family Output Enable Controls
;-------------------------------------t~------------------------------------

: ....
' --~ ,..----==:-, ,------, ,..-----,

:

>----,.+------rl------------M----~+_----

To Other

>-----jH-+----....-t-I-----------.......- H - - - - . - I - + - - - - - 1I0eelis

Boundary Scan
Boundary Scan (IEEE 1149.1 compatible) is a test feature incorporated within the device to provide on-chip test
capabilities during PCB testing. Five input signal pins,
BSCAN, TOI, TCLK, TMS, TRST, and one output signal
pin, TOO, are associated with the boundary scan logic
cells. These Signal pins occupy the same dedicated
signal pins used for ISP....2!Q9.!:amming. The signal BSCAN
is associated with the ispEN pin, TOI corresponds to the
SOl pin, TCLK corresponds to the SCLK pin, TMS corre-

sponds to the MODE pin, and TOO corresponds to the
SOO pin. When ispEN is asserted low, the MODE, SOl,
SOO, and SCLK options become active for ISP programming. Otherwise, BSCAN, TOI, TCLK, TMS, TOO, and
TRST options become active for boundary scan testing
of the device. The boundary scan block diagram is
shown in figure 7. TOI is the test data serial input, TCLK
is the boundary scan clock associated with the serial shift
register, TMS is the test mode select input, TOO is the
test data output, and finally TRST is the reset signal pin.

Figure 7. Boundary Scan Block Diagram

Test Data Output (TOO)

Test Data Input (TDI)
Test Mode Select (TMS)

To 1/0 Cell Boundary
Boundary Scan Enable (BSCAN)
Boundary Scan ClK (TClK)
Reset Signal (TRST)

•

Scan Registers

Boundary Scan

•
•
0846

2-35

1994 Data Book

3000 Family Architectural Description
The user interfaces to the boundary scan circuitry through
the Test Access Port (TAP). The TAP consists of a
control state machine, instruction decoder and instruction register.
The TAP is controlled using the test control lines: Test
Data IN (TOI), Test Data Out (TOO), Test Mode Select
(TMS), Test Reset (TRST) and Test Clock (TCK).
The TAP controls the operation of the Boundary Scan
Registers after decoding the instruction code sent to the
instruction register (see table 1).
The Boundary Scan Registers for the I/O cells are shown
in figure 8. As illustrated in the figure, each I/O cell
contains 3 registers, 2 latches and 5 multiplexers to

implement the ability to capture the state of the I/O cell or
set the state of the output path of the cell or function as
a conventional I/O cell.
The Boundary Scan Registers required for an input only
cell are shown in figure 9. An input only cell can only have
its state captured, which only requires one MUX and one
register.
A" of the input cells and I/O cells are serially connected
together in a long chain. The scan out of one cell is
connected to the scan in of the next cell. The cells are
connected in the following order: TOI to 1063 thru 1032
to Y4, Y3, Y2, Y1, Reset, TOE, GOE1, GOEO, YO, 1031
thru 100 to 1064 thru 10127 to TOO.

Figure 8. Boundary Scan Registers for I/O Cells

1-----10

01-.......- - 1 0

SCAN IN (from previous pad)

01----1

GLB
OE

1---+-10

01---.--+-10

01----1

GLB
Oulput
Shift DR

--+----1--'

1---+-10

Clock DR

0 1 - - - + - - SCANOUT (to next pad)

Update OR

110 IN _ - - - - - - - - - - - - - - - - - - - - - - - - - '

2-36

1994 Data Book

3000 Family Architectural Description
Figure 9. Boundary Scan Registers for an Input Only Cell

t-----ID
Scan In

Q I - - - - SCANOUT
(to next pad)

•

(from previous pad)
Shift DR

Clock DR

Table 1. Boundary Scan Instruction Codes
Description

Instruction Name

Code

SAMPLE! PRELOAD

10

Loads and shifts data into BScan registers

EXTEST

00

Drives external 1/0 with BScan registers

BYPASS

11

Bypasses registers of selected device(s)

Note: LSB shifts in 1St.

Table 11). oooe

Timing Model
The task of determining the timing through the device is
simple and straightforward. A device timing model is
shown in figure 10. To determine the time that ittakes for
data to propagate through the device, simply determine
the path the data is expected to follow, and add the

various delays together (figure 11). Critical timing paths
are shown in figure 10, using data sheet parameters.
Note that the Internal timing parameters are given for
reference only, and are not tested. (External timing
parameters are tested and guaranteed on every device).

Figure 10. pLSI and ispLSl3256 Timing Model

_____ ..---..r,..----...
110 Coli

GAP

GLB
Jo. . . .- - - - . . . . ,
..

ClAP
~,

110 CaO
to:

YO.1.2 ) -_ _ _ _ _ _ _...:.:::::60~_ _ _ _ _ _ _-.I

0.1)-----------_________--'
TOE

>--------------________
2-37

~

1994 Data Book

3000 Family Architectural Description
Figure 11. Timing Calculation Example
Derivations of tsu, th and tco from the Product Term Clock1
tsu

6.5 ns =
th

Logic + Reg su • Clock (min)
~tiCbP + tgip4 + t2optxo.) + (tgsu) - (tiobp + tgrp4 + tpick(min»
\#24+ #31+ #39) + (#42) - (#24+ #31+ #48)
(2+ 4 + 8.5) + (1.5) - (2 + 4 + 3.5 )

Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max») + (tgh) - (bobp + tgrp4 + t20ptxor)
(#24+ #31+ #48) + (#43) - (#24+ #31+ #39)
8 ns = (2 + 4 + 7.5) + (9) • (2 + 4 + 8.5)

teo

Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max») + (tgco) + (torp + tob)

= (#24 + #31 + #48) + (#44) + (#49 + #51)
20 ns = (2 + 4 + 7.5) + (1.5) + (2 + 3)

1. Calculations are based upon timing specs for the pLSI and ispLSI 3256-70L

2-38

1994 Data Book

ispLSI Architecture and
Programming
ispLSI Programming Information
The following general programming information on the
ispLSI (in-system programmable Large Scale Integration)
devices describes how the internal state machine is implemented for programming and how to use the five
programming interface signals to step through the state
machine. The device specific information, such as timing
and pin-outs, can be found in the individual data sheets.
The programming information given in this section applies
to all ispLSI devices.

Programming Overview
To distinguish between normal operation and programming, two modes are defined: normal mode and edit
mode. Once the device is in edit mode, the entire programming operation of the device is controlled by the internal
ISP state machine. The in-system programming enable
(ispEN) signal controls the device operation modes.

The programming is controlled by the on-chip state machine
via five programming interface signals. The ispEN signal
is used to enable and disable the four programming control
signals which include Serial Data In (SOl), Mode (MODE),
Serial Data Out (SDO) and Serial Clock (SCLK). When the
device is in normal mode, the four programming control
signal pins can be used as normal Dedicated Input Pins.
Rgure 1 illustrates one such possible configuration for
programming multiple ispLSI devices. With this scheme
the 1SPEfiI'signal for individual devices is enabled separately
and one device is placed in the edit mode at a time. Since
theotherdevices are in the normal mode, they can continue
to perform normal system functions. This simple scheme
requires connecting all four programming control signal
pins together and precludes their use as dedicated inputs
for normal system functions. ispEN isthe only programming
interface signal that is dedicated to a pin.

Figure 1. ispLSI Programming Interface

Serial Data In
Serial Data Out
ISP-Mode
ISP-Clock
ISP-Enable ~-

I~

L,--J
5-Pin ISP Interface

2-39

1994 Data Book

ispLSI Architecture and Programming
Normal Mode
In Normal Modethefourprogramming control pins become
Dedicated Input pins. By muHiplexing the programming
control pins, these programming control pins can have a
normal input function during Normal Mode. Figures 2
illustrates how to utilize the four programming control
signal pins for performing normal system functions. Intemal
to the device, the programming functions are completely
isolated from the normal operating functions when the
device is in Normal Mode. Keeping the ispEN signal high
puts the device in Normal Mode. For simplicity, the four
programming control pins can be left unused for normal
input functions. These pins can be reserved for ISP by
using the ISP switch in the development tools. By leaving
these pins unused, the programming interface is simplified
when the programming signals and the Normal Mode input
signals are not muHiplexed.

Edit Mode
Programming circuitry is enabled by driving the ispEN
signal low which puts the device in Edit Mode. In Edit
Mode, all the functional
pins and input pins that are not
used during programming are 3-stated. With the exception
of the SOO signal, the remainder of the programming
interface signals are input signals. When multiplexing the
programming interface signals, the input driving the SOO
pin must be 3-stated to make sure that there is no signal
contention. All programming is accomplished in the Edit
Mode by controlling the programming state machine with
the MODE and SOl signals. SCLK is used to clock
programming data in and out through SOl and SOO pins.
SOl has a dual role as one ofthe two control signals for the
state machine and as the serial data input. To avoid any
intemal register data contentions, Lattice recommends
that the device Reset pin be pulled to ground when the
device is in Edit Mode.

va

SOl performs two different functions. First, as the input to
the serial shift register and second, as one ofthetwo control
pins for the programming state machine. Because of this
dual role, SOl's function is controlled by the MODE signal.
When MODE is low SOl is the serial input to the shift
registers and when MODE is high SOl becomes the control
signal. Internal to the device, the SOl is muHiplexed to
address shift register, high order data shift register and low
order data shift register. The different shift instructions of
the state machine determine which of these shift registers
gets the input of the SOl.
The MODE signal combined with the SOl signal controls
the programming state machine. This signal connects in
parallel to all ispLSI devices.
SCLK is the serial shift register clock that is used to clock
the internal serial shift registers. A low-to-high (positive)
clock transition clocks the state machine. It also connects
in parallel to all ispLSI devices. Similar to SOl, the shift
instructions determine which of the shift registers are
clocked for the data input from SOl.
SOO is the output of the serial shift registers. The selection
of the shift register is determined by the state machine's
shift instruction. In the flow through instruction and when
MODE is driven high, SOO connects directly to SOl, and
bypasses the device's shift registers. Since this is the only
output pin for the Edit Mode, this signal will drive the
external devices that are connected to this pin.

Programming Interface
The five programming interface pins are ispEN, SOl,
MODE, Sooand SCLK. Once in Edit Mode, programming
is controlled by SOl, MODE, SOO and SCLK signals. In
Normal Mode, the programming control pins can be used
as dedicated inputs to the device.
ispEN is an active low, dedicated enable pin, which enables the four programming control pins when it is driven
low (VIU and disables the programming control pins when
it is driven high (VIH). All other
pins are 3-stated during
Edit Mode and pulled up by the internal active pull-up
resistors (equivalent to 1001<0 ).

va

2-40

1994 Data Book

ispLSI Architecture and Programming
Programming Details
Programming is completely controlled by the state machine,
once the device is in the Edit Mode. The state machine
consists of three states, in which all programming related
operations are performed. In order to run these programming operations, five bit instructions are defined (see table
2). Each instruction is then shifted into the device in one of
the three states and executed in another state. The initial
state of the state machine is used when the device is idle
during edit, or to shift out the eight bit device identification
code.
The following sections describe the general information
about the critical timing parameters, state machine, state
machine instructions, and device layoutthat apply to all the
ispLSI devices. Any device specific information like the
size of the shift registers and the device specific timing
information can be found in the individual device data
sheets.

There are various ways of programming the ispLSI devices.
The easiest is to dedicate the ISP programming pins only
for the programming functions. With dedicated ISP pins,
one can either program the devices in a serial daisy chain
configuration (figure 1) or in a parallel programming
configuration where the programming signals are
multiplexed. The parallel multiplexed programming method
gives the user another advantage of being able to use the
programming pins for system functions. Figure 2 illustrates
a multiplexing scheme which allows the user to control the
ISP programming through multiple ispEN signals. The
multiple ispEN signals not only control the ispEN inputs of
the ispLSI devices, but also is the control signal for
multiplexing the functional signals and the ISP programming
signals. The ISP programming Signals MODE, SOl and
SCLK function as inputs for normal functional mode as well
as the ISP programming mode. SDO, however, functions
as an input in normal functional mode and as an output in
ISP programming mode. Figure 2 also shows the difference
in controlling these different programming signals.

Figure 2. The Scan and Multiplex Programming Mode

SOO MOOE

SOl

SCLK

SOl

ispLSI

SCLK

SOO

ispLSI

2-41

1994 Data Book

ispLSI Architecture and Programming
Isu -

Critical Timing Parameters
When programming ispLSI devices, there are several
critical timing parameters that must be met to ensure
proper programming. The two most critical parameters are
the programming pulse width (tpwp) and the bulk erase
pulse width (tbew)' These pulse widths determine the
programming and erasing of the E2 cells. Figure 4 shows
these critical program and erase timing specifications.
Along with the two programming and erasing specification,
the following timing specifications must also be met.
Specifies the time it takes to get into the ISP mode
after ispEN signal is activated or the time it takes
to come out from the ISP mode after the ispEN
becomes inactive.

Set up time of the control signals before the SCLK
or the set up time of input Signals against other
control signals where applicable.
Hold time of the control signal after the SCLK. It
also applies to the same input signals from the set
uptime.

!elkl, !elkh

Minimum clock pulse width.

tpwv-

Verify or read pulse width. The minimum time
requirement from the rising clock edge of verifyl
load instruction execution to the next rising clock
edge (see figure 4).

trs! -

Power on reset timing requirement. trs! must
elapse after power up before any operations are
performed on the device.

All the programming timing parameters are summarized in
the timing diagram (see figure 5).
Figure 4. Program, Verify & Bulk Erase Timing
Execute State (Program, Verify or Bulk Erase Instruction)
MODE

tpwp, Thew. or tpwv
SOl

th----~'----~-----------/

J+.-+I--tclkh

SClK _ _".,/

~
"

tsu

"'---

/

j.;::: tclkl ~

Figure 5. ISP Programming Timing Requirements

Unused
~:ZZ#Q~f--!~=------------~~K2Z
Output 4.

MODE

SCLK

---t--"

--:--t-~

SDO

~

Don'tCare

~ Transitional State

•
2-42

1994 Data Book

ispLSI Architecture and Programming
Figure 6. Programming State Machine
Load
ID

Shift
ID

Execute
Command

Load
Command

•

Note:
Control signals: MODE, SDI

Table 1. ispLSI Device ID Codes

State Machine Operation
The state machine has three states to control programming
and uses the MODE and SDI signals as inputs for each
state. Based on these input signals, the state machine
makes decisions to either stay in the same state or to
branch to another state. The three states are Idle/ID State,
Command Shift State and Execute State. The programming
state machine diagram in figure 6 shows the three states
and the logic levels of the control signals needed to force
each transition state.

Device

MSB

LSB

ispLSI1016

00000001

ispLSI1024

00000010

ispLSI1032

00000011

ispLSI1048

00000100

ispLSI 1048C

00000101

ispLSI2032

00010101

ispLSI3256

00100010

IdleJID State
The Idle/ID state is the first state which is active when the
device gets into the Edit Mode. The state machine is in the
Idie/lD state when the device is idle, in the Edit Mode, or
when the user needs to read the device identification. The
eight bit device identification is loaded into the shift register
by driving MODE high, SDI low and clocking the state
machine with SCLK. Once the ID is loaded, it is read out
serially by driving MODE low. Notice that when reading the
device ID serially, SDI can either be high or low (don't care)
and the state machine needs only seven clocks to read out
eight bits of ID. The default state for the control signals is
MODE high and SDI low. State transition to Command
Shift State occurs when both MODE and SDI are high while
state machine gets a clock transition. Table 1 lists the eight
bit device ID's for all the ispLSI devices. As with most shift
registers the Least Significant Bit (LSB) of the ID gets
shifted out from the SDO first.

Command Shift State
This state is strictly used for shifting in the command
instructions into the state machine. The entire five-bit
instruction set is listed in the next section. When MODE is
low and SDI is don't care in the Command Shift State,

SCLK shifts the instruction into the state machine. Once
the instruction is shifted into the state machine, the state
machine must transition to the Execute State to execute
the instruction. Driving both MODE and SDI high and
applying the clock will transfer the state machine from the
Command Shift State to Execute State. If needed, the state
machine can move from Command Shift State to Idie/lD
State by driving MODE high and SDllow.

Execute State
In the Execute State, the state machine executes instructions that are loaded into the device in the Command Shift
State. For some instructions, the state machine requires
more than one clock to execute the command. An example
of this multiple clock requirement is the address or data
shift instruction. The number of clock pulses required for
these instructions depends on the device shift register
sizes (refer to the ISP programming section of the data
sheet). When executing instructions such as Program,
Verify or Bulk Erase, the necessary timing requirements
must be followed to make sure that the commands are
executed properly. For specific timing information refer to
the individual data sheets.

2-43

1994 Data Book

!

ispLSI Architecture and Programming
To execute a command, the MODE is driven low and SOl
is "don't care." For multiple clock instructions the control
signals must remain in the same state throughout the
duration of the execution. MODE high and SOl high will
take the state machine back to the Command Shift State
and MODE high and SOl low will take the state machine to
the IdiellD State.

device identification is done during the IdlellD State and
does not require an instruction.

Instructions

When a device is secured by programming the security cell
(PRGMSC), the on-chip verify and load circuitry is disabled. Securing of the device should be done as the last
procedure after all the device verifications have been
completed. The only way to erase the security cell is to
perform a bulk erase on the device.

Table 2 lists the instructions that can be loaded into the
state machine in the Command Shift State and then
executed in the Execute State. Notice that reading the

While it is possible to erase the individual arrays of the
device, it is recommended that the entire device be erased
(UBE) and programmed in one operation. This Bulk Erase
operation should precede every programming cycle as an
initialization.

Table 2. State Machine Instruction Set
Instruction

Operation

00000
00001

NOP
ADDSHFT

00010
00011
00100
00101
00110

DATASHFT
UBE
GRPBE
GLBBE
ARCHBE

00111

PRGMH

01000

PRGML

01001
01010

PRGMSC
VERILDH

01011

VERILDL

01100

GLBPRLD

01101

10PRLD

01110

FLOWTHRU

10010

VEILDH

10011

VEILDL

Description
No operation performed
Address Register Shift: Shifts address into the address shift register from
SDIN.
Data Register Shift: Shifts data into or out of the data serial shift register.
User Bulk Erase: Erase the entire device.
Global Routing Pool Bulk Erase: Bulk erases the GRP array only.
Generic Logic Block Bulk Erase: Bulk erases all the GLB array only.
Architecture Bulk Erase: Bulk erases the architecture array and VO
configuration only.
Program High Order Bits: The data in the data shift register is programmed into the addressed rows high order bits.
Program Low Order Bits: The data in the data shift register is programmed into the addressed rows low order bits.
Program Security Cell: Programs the security cell of the device.
VerifylLoad High Order Bits: Load the data from the selected rows high
order bits into the data shift register for verification.
VerifylLoad Low Order Bits: Load the data from the selected rows low
order bits into the data shift register for verification.
Generic Lgtc Block Preload: Preloads the registers in the GLB with the
data from S IN. All registers in the GLB form a serial shift register. Refer
to device layout section for details.
VO Preload: Preloads the 1/0 registers with the data from SDIN. All
registers in the VO cell form a serial shift register (the same order as GLB
registers).
Flow Through: Bypasses all the internal shift registers and SDOUT becomes the same as SDIN.
Verify EraselLoad High Order Bits: Load the data from the selected row's
high order bits into the data shift register for erased verification.
Verify EraselLoad Low Order Bits: Load the data from the selected rows
low order bits into the data shift register for erased verification. .

2-44

1994 Data Book

ispLSI Architecture and Programming
Fuse Map to Device Conversion

Device Layout
The purpose of knowing the device layout is to be able to
translate the JEDEC format programming file into the serial
data stream format for programming ispLSI devices. Two
main factors determine how the translation is implemented:
the length of the address shift register and the length of the
data shift register. The length of the address shift register
indicates how many rows of data are to be programmed
into the device. The length of the data shift register
indicates how many bits are to be programmed in each row.
Both registers operate on the First In First Out (FIFO) basis
where the Least Significant Bit (LSB) of the data or address
is shifted in first and the Most Significant Bit (MSB) of the
data or address is shifted in last. For the data shift register,
the low order bits and the high order bits are separately
shifted.
Each ispLSI device has a predefined number of address
rows and data bits needed to access its E2CMOS® cells
during programming. The data bits span the columns of the
E2 array. From this information the number of programming cells (or fuses) are determined. Table 3 highlights the
address and data shift register (SR) sizes for a" ispLSI
devices. The JEDEC file for these ispLSI devices will
reflect the number of cells (fuses) seen in table 3. The total
number of cells becomes critical if the programming patterns are to be stored in an on-board memory storage of
limited capacity such as EPROM or PROM.
The L field in the JEDEC programming file indicates the first
cell number of each row. The JEDEC standard requires
that there is at least the beginning cell number LOOOOO.
L fields of the subsequent lines are optional. From this
reference cell location all other cell locations can be determined. Zero in the cell location indicates that the E2 cell in
that particular location is programmed (or has a logic
connection equivalent to a metal fuse being intact). A one
(1) in the cell location indicates that the cell is erased
(equivalentto a blown fuse). The fusemap operation in the
Lattice software generates this JEDEC standard
programming file.

One of the major elements needed to program an ispLSI
device is the JEDEC fuse map in which the specific logic
implementation is stored. While the ispCODE software
takes care of these details, it is important to understand
how this JEDEC fuse map is mapped onto the physical
ispLSI device during programming. The physical layout of
the fuse pattern begins with Address Row 0 and ends with
the maximum Address Row N and is determined by the
length of the Address SR as described in table 3. Spanning
the Address Rows are the outputs of the High-Order Data
SR and Low-Order Data SR, as described in table 4.
Programming fuses on a given row are enabled by a "1"
within the Address Shift Register for the appropriate row
and the use of state machine instructions that selectively
operate on the High-Order Data SR or the Low-Order Data
SA. For example, the PRGMH instruction programs the
High-Order data bits within the device for the selected
Address Rowand the PRGML instruction programs the
Low-Order data bits (table 2 lists the ISP state machine
instructions). Referring to figure 7, the starting cell (LOOOOO)
ofthe JEDEC fuse map shifts into the device atthe physical
location corresponding to Address Row 0, High-Order
DataSR bitO. nand m in the figure refer to the Address SR
length and the Data SR length, respectively, of the device
(refer to table 3). A series of sequential shifts eventually
results in the last cell location (Total # of Cells - 1) of the
JEDEC fuse map shifting into Address Row (n-1), LowOrder Data SR bit (m-1) on the actual device.
The ispCODE Software routines make use of a bit packed
data format, called ispSTREAMTM, to transfer data between the JEDEC fuse map and the physical device
locations. The JEDEC fuse map can be translated into
ispSTREAM using the iSP-.iedtoisp function and the
ispSTREAM format can be translated into a JEDEC fuse
map using the isp_isptojed function.

Command Stream
The first step of programming the ispLSI devices is to
determine the type of device to be programmed. This can
be done by reading the eight-bit device ID of a" the devices.

Table 3. ispLSI Address and Data Shift Register and Total Cell Summary
ispLSI1016
Address SR Length
Data SR Length/Address
Total Number of Cells

ispLSI1024

ispLSI1032

ispLSI1048

ispLSI2032

ispLSI3256

96

102

108

120

102

180

160
15,360

240

320
34,560

480

80

676

57,600

8,160

121,680

24,480

2-45

1994 Data Book

•

I
I

ispLSI Architecture and Programming
Table 4. Summary of Data Shift Register Bits

ispLSI1016

DataSR Bits

ispLSI1024

ispLSI1032

IspLSI1048

High Order Data SR LSB

0

0

0

0

High Order Data SR MSB

79

119

159

239

Low Order Data SR LSB

80

120

160

240

Low Order Data SR MSB

159

239

319

479

Data SR Size (Bits)

160

240

320

480

Figure 7. ispLSI Device to Fuse Map Translation
DATA

DATA

~
Data In
(SDIN)

[(m/2)-1J ... High Order Shift Register ... 0

(m-1) ... Low Order Shift Register ... (m/2)

SDOUT

Row Addr. In (SDIN)
,--------------------....,
(n-1)

E2 CMOS Cell Array

Low-Order SR
Fuse# (m-1) _

High-Order SR

Fuse# (ml2)1 Fuse# [(m/2)-1J- Fuse# 0

SDOUT

246

1994 Data Book

ispLSI Architecture and Programming
By keeping the SDI to a known level (either high or low), the
ID shift can be terminated when a sequence of eight ones
or eight zeros is read. From the device ID the serial bit
stream for programming can be arranged. A typical
programming sequence is as follows:
1) ADDSHFT command shift
2) Execute ADDSHFT command

preload all ofthe registers: GLBPRLD and 10PRLD. These
two commands enable two different shift registers and
enable data to be loaded into the device. The process of
loading data into the device is:
1. Enter the ISP programming mode by driving ispEN pin
to ViI.

Shift address

2. Load command GLBPRLD and execute command (wait
onetclk).

4)

DATASHFT command shift

3. Clock in the GLB preload data.

5)

Execute DATASHFT command

3)

4. Load the command 10PRLD and execute the command
(wait one tClk).

6) Shift high order data
7)

PRGMH command shift

8)

Execute PRGMH

9)

DATASHFT command shift

5. Clock in the I/O preload data.
6. Return to the normal mode by driving the ispEN pin to
Vih.

10) Execute DATASHFTcommand
11) Shift low order data

7. Execute the vectors.

12) PRGML command shift

When preloading a device it is important to keep the
dedicated input pins (RESET, YO, Y1, Y2 and Y3) in the
same state as the previous vector. If the state of these pins
is switched during the preload sequence the register may
not load correctly and the results cannot be guaranteed.

13) Execute PRGML
14) Repeat from 1) until all rows are programmed.

Diagnostic Register Preload
This section explains how to preload all of the buried
registers and I/O registers to a known state to test the logic
function of a device. The process of loading the register will
reduce the time necessary to test a function that is deeply
embedded in the logic of an ispLSI device.
To preload a device the ISP state machine is used with the
same five pins that are used for programming ispEN, SDI,
MODE, SDO and SCLK. Two state machine commands

The preload feature is not recommended on designs which
use product term resets. The asynchronous nature of
these resets can cause registers to be reset unexpectedly,
therefore the results cannot be guaranteed.
There are two shift registers used to preload an ispLSI
device, the GLB shift register and the I/O shift register (see
table 6). The data formattor both devices is shown in figure
9. The GLB registers are listed with their outputs (Le. (A7
00) indicating output 0, of GLB A7).

Table 6. Preload Shift Registers
Device

GLB Shift Reg. Length

I/O Shift Reg. Length

ispLSI1016

64 bits

32 bits

ispLSI1024

96 bits

48 bits

ispLSI1032

128 bits

64 bits

ispLSI1048

192 bits

96 bits

ispLSI2032

32 bits

N/A

ispLSI3256

256 bits

128 bits

•
2-47

1994 Data Book

ispLSI Architecture and Programming
Figure 9. GLB Shift Register and I/O Shift Register Format
GLB Shift Register Format
Oataln
(SOl)

(BO 00) (BO 01 )... (B7 02) (B7 03)

OataOut
(SOO)

Oata In
(SOl)

(B4 00) ... (B7 03) (CO 00) ... (C7 03)

OataOut
(SOO)

Oataln
(SOl)

(CO 00) ... (C7 03) (00 00) ... (07 03)

OataOut
(SOO)

Oata In
(SOl)

(A7 OO) ... (AO 03) (continued)

(continued) (00 00) ... (07 03) (EO 00) ... (E7 03) (FO OO) ... (F7 03)

Oataln
(SOl)

Oata Out
(SOO)

OataOut
(SOO)

Oataln
(SOl)

(continued) (EO OO) ... (E7 03) (FO OO) ... (F7 03) (GO OO) ... (G7 03) (HO OO) ... (H7 03)

OataOut
(SOO)

I/O Shift Register Format
Oata In
(SOl)

OataOut
(SOO)

Oata In

(501)

OataOut
(SOO)

Oataln
(SOl)

OataOut
(SOO)

Oataln
(SOl)

OataOut
(SOO)

Oataln
(SOl)

OataOut
(SOO)

2-48

1994 Data Book

ispLSI Architecture and Programming
ISP Programming Support
To assist users in implementing the ISP programming,
Lattice provides the isp Engineering Kit hardware and
ispCOOE C language software routines which implement
the basic ISP functions for programming. The Lattice ISP
programming support uses the PC parallel port to program
the devices.

isp Engineering Kit Hardware Definition
Lattice provides both a PC-based (Model 100) and a Sun
Workstation-based (Model 200) isp Engineering Kit. PCbased, parallel 1/0 port programming interface
implementation is explained in this section. For details on
the Model 200 refer to the Model 200 isp Engineering Kit
datasheet. The main function of this ispLSI programming
interface is to provide four properly timed programming
signals and the ispEN signal to the device. The PC parallel
port is used in the isp Engineering Kit to provide these
programming signals. The signals driven by the parallel
port can be used either by the Lattice isp Programming
Module (part of isp Engineering Kit Model 100) or on the

system board if the circuit board is built with provisions to
connect the ISP programming signals to the appropriate
traces.
In the case of users using the PC serial port as the 1/0 port
for programming, the serial data must be converted by
additional circuitry into the appropriate programming signals. There must also be timing circuitry that translates the
serial instructions into timed ISP programming signals.
This section only discuss the parallel port interface. Lattice's
isp Engineering Kit Model 200 supports serial port programming.
In order to use the PC parallel port, the parallel port
operation must be defined properly. After defining the port,
it is just a matter of developing the programming software
to read and write from the parallel port. To guarantee the
signal integrity and drive capability, a 74HC367 buffer
should be directly connected at the parallel port's 0825
connector. Figure 11 defines the parallel port 0825 pins
and the associated ISP programming signals. The global
RESET signal is also provided to ensure a proper register
reset after programming.

Figure 10. Configuring an ispLSI Device from a Remote System

End-Product P.C. Board

Parallel Port
Connection

2-49

1994 Data Book

.I

ispLSI Architecture and Programming
The buffer then drives the cable that connects the output of
the buffer to the ISP pins of the device. It is important to
keep the cable length to a minimum to reduce the loading
on the signal drivers. Since ispEN, SOl, SCLK and MOOE
are inputs to the ispLSI device, they are being driven by the
buffer connected to the parallel port. SOO, on the other
hand, is an output signal which the ispLSI device has to
drive. Ifthe load on the SOO signal is more than a minimum
length cable and the parallel port input, it is recommended
that the user provide a buffer on the circuit board to ensure
signal integrity.

Based on the programming pulse width requirement, the
total programming time can be estimated. Since the
shifting the address and data is relatively small compared
to the programming time, the total programming time can
be estimated by the following formula.
Total Programming Time = Address SR Length X 2 X tpwp

Assuming that the programming pulse width (tpwp) is
100ms, the total programming time for the ispLSI1048 is
approximately 24 seconds.

Forthe parallel port interface, the software must access the
proper parallel port address. Once the port is defined, the
data transfer is accomplished by simply reading from the
port and writing to the port. The software must also
guarantee proper timing between the ISP programming
signals. When the programming software is executed,
most of the shorter hardware timing requirements are
automatically met due to the relatively long instruction
execution times. The programming pulse width (tpwp) and
bulk erase pulse width (tbew), which are in the 40ms to
200ms range, are the hardware timings that typically
require wait states in the software. The example functions
in the ispCOOE illustrates reading of the computer's timer
chip to generate these wait states.

Microprocessor-Based Programming
Similar to PC-based I/O port controlled programming, a
processor or a microprocessor can be used to directly
supply the ISP programming signals with minimum decoding logic and an optional storage device (see figure 12).
The discussion in this section pertains to the implementation of ISP programming on a circuit board with a
microprocessor. The discussion is based on the assumption that the patterns and the code are stored in EPROMs.
Since an efficient use of storage is desirable, the bit packed
ispSTREAM format will use the least amount of storage.
The basic requirement here, again, is to supply properly
timed ISP programming signals.

Figure 11. PC Parallel Port Buffer & RJ45 Connector Definition
DB25 Parallel Port
Connector Pins

f-i4HC367,

,

DIS

Pin 10 _ _ _ _+'_<

DOO

Pin 2 - - - - f - + - - l

DOl

Pin 3 ----f-~-l

D02

Pin 4

D03

Pin 5 -

isp Interface
1--..-_ _ _ _ SDOUT

SDIN

)--i---.o-v'

-.,..,....-+-"';""-1

SCLK

MODE

10K

......--4-+--1 )--;'-Ho-v'

4 - NO CONNECT

5- ispEN
6-SOI
7-SDO

10K

D04

Pin 6 -

.....- - - i - - l

D06
DI5

Pin a ----,
Pin 12

DI3
GND

Pin 15 - Vee Sense
Pin 20 - GND

)--!---.o-v'

RESET

a-vce

I-- Port Sense

2-50

1994 Data Book

ispLSI Architecture and Programming
Hardware Configuration
There are several ways to define the ISP programming
hardware depending on the type of storage device and how
the ispLSI devices are to be programmed. The hardware
configuration shown infigure 13 uses an 8-bitwide EPROM
to store the fuse maps and code. The patterns are then
read from the EPROM by the microprocessor and converted into serial stream format. The ISP signals are driven
from the decoder and I/O port which decodes the proper
ISP read/write address space similar to the I/O port definition of the previous setup. Similarly, fuse map memory
addresses must also be defined to be properly read from
the EPROM.

Software support for this case is very similar to the previous. Within the software, however, address spaces for the
ISP read/write locations and the EPROM read locations
must be defined. The storage space requirement for the
code must also be determined if the code is going to reside
in the storage device. Based on the ispCODE functions,
the object code which is capable of executing basic ISP
functions typically does not exceed 8K byte of memory.
This memory requirement is directly proportional to the
amount of ISP and user interface functions.

ISP Software Interface

Programming pattern storage requirements are directly
dependent upon the ispLSI device type and which ISP
functions must be executed by the microprocessor. Assuming the bit packed ispSTREAM formatforthe fuse map,
the number of bytes required for each ispLSI device is
simply the total number of cells divided by eight. In the case
of ispLSl1048, 7.2K bytes is required to store the JEDEC
fuse map.

In addition to the hardware interface, the ispCODE C
language routines take care of the ispLSI programming
software interface. The software interface must implement
routines to read and write from the parallel port, to translate
the JEDEC fusemap to and from the stream file format, and
to toggle the ISP hardware signals connected at the output
port. Predefined routines for these functions such as
isp_program, isp_read, isp_verify, etc. are provided with
the ispCODE. The ispLSI user only needs to integrate
these routines into their overall system software.

Similar to the parallel port interface, most hardware timing
requirements can be satisfied by the software instruction
execution time. Only the program, verify and bulk erase
times requires the software to have wait cycles. Many
microprocessor boards will not have a timer chip to time the
wait states. However, the instruction execution times
typically can be accurately estimated. Therefore, timing
loops must be inserted into the instructions control critical
hardware timing.

The ispCODE routines makes use of the ispSTREAM bit
packed data format to transfer data between the JEDEC
fuse map and the physical device location. The JEDEC
fuse map can be translated into ispSTREAM using the
ispjedtoisp function and the ispSTREAM format can be
translated into a JEDEC fuse map using the isp_isptojed
function. In addition to the fuse map translation routines,
the ispCODE provides functions to check the device ID, to
read and write the User Electronic Signature (UES), and to

Figure 12. Configuring an ispLSI Device from an On-Board Microprocessor

2-51

1994 Data Book

II
!

ispLSI Architecture and Programming
keep track of the program cycle counter. Refer to the
ispCOOE User Manual for more details.

ispLSI Device Special Features
In addition to transfering the fuse pattem into the ispLSI
device with proper ISP timing, there are a few administrative
functions that can make device programming more efficientwhen implemented in the ISP programming algorithm.
All ispLSI devices have hardwired device identification
codes. These 10 codes should be used to identify proper
device and fuse map compatibility. The 10 check should be
run as the very first procedure before any device programming procedures. The ispCOOE routines provided by
Lattice include the isp_geUd function to facilitate this
process.
The ispLSI devices also provide several programmable
locations forthe UES and program cycle counter. The UES
can be used to identify which pattem is programmed into

the device. This is a very useful way of electronically
identifying the devices and their programs, especially
when the devices are secured. A 16-bit program cycle
counter can be implemented within the reserved loacation,
similar to the UES, to keep track of the number of program
cycles which the device experiences to avoid exceeding
the maximum programming cycle limit. UES and program
cycle counter routines are provided as part of Lattice's
ispCOOE software.
One of the diagnostic features of the ispLSI devices is
register preload. GLB and 1/0 registers become serial shift
registers during the register preload command execution.
Data can either be shifted into or out of these shift registers
for system diagnostic functions. Special attention must be
paid to the GLB and 1/0 clocks in order to use the register
preload features properly. One must drive all GLB or all
1/0 clocks high throughout the execution of the GLB or 1/0
preload commands. This means that when defining the
test pattem that uses the preload commands all GLB or all
1/0 clock polarities must be the same.

Figure 13. Microprocessor Board Configuration

Addr

Address
Decode

AS

f'JW

VOPor!
Register
L.._ _ _ _-+\ (Bidirectional)

MODE
SCLK

00·D7.-j_ _ _ _ _-+j

SOl
SDO

iiiDEl'/"

IlpLSI Device

Decoder

Control Signals (RIW,AS,etc..)

&

DATA

I/O Port
Logic

...Mll

L..

14 IUU

Microprocessor

+S001
SDI2

~ IspLSI Device

1.-+

4-

PROM
or
EPROM

~
.~002
8013

ADDRESS

4

lopLSl DevIce

~
SD03
~

2-52

1994 Data Book

ispLSI Architecture and Programming
Boundary Scan
The Lattice 3000 family of devices supports the IEEE
1149.1 Boundary Scan specifications. The following
sections explain in detail how to interface to the devices
through the Test Access Port (TAP), how the boundary
scan registers are implemented within the devices, and the
boundary scan instructions that are supported by the pLSI
and ispLSI 3000 family
Test Access Port (TAP)

The test access port of the boundary scan is accessed
through six interface signals. These interface signals have
dual functions in the case of ispLSI 3000 family and are
used for Boundary Scan interface and in-system
programming interface signals. For the pLSI 3000 family
the six interface signals are only used for the boundary
scan TAP interface. Table 7 describes the interface signals.
The above mentioned six signals are dedicated for Boundary
Scan use for the pLSI family of devices. Since ISP
programming is accomplished through the same pins, five
of the six signals have both Boundary Scan interface and
ISP functions on the ispLSI devices. The TRST is the only
signal that does not have a dual function. It is only used to
reset the TAP controller state machine. The sequencing of
test routines are governed by the TAP controller state
machine. The state machine uses the TMS and TCK
signals as its inputs to sequence the states. Figure 14A is
the IEEE1149.1 specified state machine where the condition
forthe state transtion is the state of the TMS input condition
before TCK within a given state. The timing specification
is also shown on figure 14B.

The main features of the TAP controller state machine
consists of Test-Logic-Reset state to reset the controller
and the Run-Test states. Two main components of the
Run-Test states are Data Register (DR) control states and
Instruction Register (IR) control states. Both of these
register control states are organized in a similar manner
where one can capture the registers, shift the register
string, or update the registers. Capturing the DRs simply
loads the DR with the data from the corresponding functional
input, output, or I/O pins. The IR capture, on the other hand,
loads the IRs with the previously executed instruction bits.
Shift register states serially shifts the DR and IR. In the
case of DR shift, the data is shifted according to the order
of the inputs, outputs, and I/Os defined in the Boundary
Scan section of each device data sheet. The IRs are shifted
out from the least significant bit first. During update
registers states, the DRs update the latches to drive the
external pins and IRs update the instruction bits with the
instruction that is to be executed.
Boundary Scan Registers

In order to support Boundary Scan, two types of data
registers are defined for the ispLSl/pLSI devices -- I/O cell
registers and input cell registers. The main purpose of
these registers is to capture test data from the appropriate
signals and shift data to either drive the test pins or examine
captured test data.
Figure 15 describes the registerforthe liD cell. The liD cell,
by definition, must have three components. One register
component captures the output enable (DE) signal, the
second component captures the output data and the third

Table 7. Boundary Scan Interface Signals
pLSI3000
Family
BSCAN

ispLSI3000
Family

--

BSCAN/ispEN

Pin Function Description
Active high signal on this pin selects the Boundary Scan function while active low signal
selects the ISP function on the ispLSI devices. Internal pullup on this pin drives the
signal high when the external pin is not driven.

TCK

TCKlSCLK

Test Clock function for Boundary Scan and serial clock for the ISP function.

TMS

TMS/MODE

Test Mode Select for Boundary Scan and MODE control for ISP function.

TOI

TOI/SDI

Test Data Input for Boundary Scan and Serial Data Input for ISP pin functions as serial
data input pin for both interfaces.

TRST

TRST

Test Reset Input is an asynchronous signal to initialize the TAP controller to
Test-Logic-Reset state.

TOO

TOO/SO~

Test Data Output for Boundary Scan and Serial Data Output for ISP pin functions as
serial data output pin for both interfaces.

2-53

1994 Data Book

..
II

ispLSI AlChitecture and Programming

..-=---:------:=-=-~---, 1
h---t~ Select-OR-Scan I - - - - - + i

r--~-~

0

L -_ _~~--~

Figure 14A. TAP Controller State Machine

TCK
TMSor
TOI
TOO

tsu = 0.1 J.lS (min.)

th = 0.1 J.lS (min.)

teo = 0.1 J.lS (min.)

Figure 148. TAP Controller Timing Diagram

2-54

1994 Data Book

ispLSI Architecture and Programming

GLB
OE

-r;-

SCAN IN
(from
previous
cell)

,t

D

U

Q

- >

D

r--

U

a
X

Q

>

-'M

GLB
OUTPUT

Lr;U

'1-

-"M

D

to-

Q

>

D

~

U

ST

I'

"'10

r\. PirY!

!-

Q

>

Update DR

~r"M
D

U

Q

SCAN OUT (to next cell)

~+
0-

Shift DR

>

Clock DR

Figure 15. Boundary Scan 1/0 Cell

captures the input data. These components make up the
three registers that are part of the shift register string for
each of the 1/0 pins. Only parts of the 1/0 cell registers will
have valid data when 1/0 pins are configured as input only
or output only and the test routines must be able to monitor
the appropriate register bits. The update registers are used
mainly to store data that is to be driven onto the 1/0 pins.
The multiplexer controls are driven by the signal from the
TAP controller at appropriate states.
The function of an input cell register is much simpler than
that of an 1/0 cell. Figure 16 illustrates the single input
register cell. The purpose of the 1/0 cell is to capture the
input test data and shift the data out of the shift register
string.

1----10

Q

SCANOUT
(to next cell)

(from previous

cell)
Shift DR

Clock DR

Figure 16. Boundary Scan Input Cell

2-55

1994 Data Book

•

ispLSI Architecture and Programming
Boundary Scan Instructions

Lattice pLSI and ispLSI devices support the three mandatory
instructions defined by the Boundary Scan definition. The
following paragraphs describe each of the instructions and
its instruction code. A two bit long shift register is defined
within the devices to implement the instruction shift register.
The SAMPLE/PRELOAD (Instruction Code -01) instruction
is used to sample the pins that are to be tested. During
Capture-DR state, while executing this instruction, the DRs
are loaded with the state of the pins which can then be
examined after shifting the data through TOO. The
PRELOAD part of this instruction is simply loading the DRs
during Shift-DR state with the desired condition for each of
the pins.

The EXTEST (Instruction Code - 00) instruction drives the
external pins with the previously updated values from the
DR during Update-DR state.
The BYPASS (Instruction Code -11) instruction is used to
bypass any device that is not accessed during any part of
the test. The definition of BYPASS instruction allows the
TDI not to be driven during Shift-IR state. In order to shift
in the correct instruction code the TDI pin has an internal
pull-up to drive a logic high. A bypassed boundary scan
device has a single bypass register as shown in figure 17
below.

Figure 17. Bypass Register
FromTDI
Shift DR

o

Q

ToTDO

Clock DR

2-56

1994 Data Book

Introduction to
pLS/~ and ispLS/TM 1000 Family
pLSI and ispLSI Product 1000 Family

Introduction to pLSllispLSI 1000 Family

0

110 MHz System Performance

0

10 ns Pin-to-Pin Delay

0

Deterministic Performance

0

High Density (2,000-8,000 PLD Gates)

0

44 Pin to 128 Pin Package Options

The Lattice pLSI and ispLSI 1000 Families combine the
performance and ease of use of PLDs with the density
and flexibility of FPGAs.

0

Flexible Architecture

0

Easy-to-Use

The pLSI and ispLSI1 000 Families are ideal for designs
requiring high speeds with highly integrated logic.

0

In-System Programmable (ispLSI)

Lattice Semiconductor's pLSI (programmable Large Scale
Integration) and ispLSI (in-system programmable Large
Scale Integration) are high-density and high-performance
E2CMOS® programmable logic devices. They provide
design engineers with a superior system solution for
integrating high-speed logic on a single chip.

The ispLSI devices have also pioneered non-volatile, insystem programmability, a technology that allows real-time
programming, less expensive manufacturing and enduser feature reconfiguration.

pLSlandispLSITechnology

Lattice's E2CMOS technology features reprogrammability, the ability to program the device again and again to
easily incorporate any design modifications. This same
capability allows full parametric testability during manufacturing, which guarantees 100 percent programming
and functional yield.
All necessary development tools are available from Lattice and third-party vendors. Development tools offered
range from Lattice's low cost pDS® software, featuring
Boolean entry in a graphical WindowsTM based environment, to the pDS+TM family of Fitters that interface with
third party development software packages. Design
systems interfacing with pDS+ Fitters feature schematic
capture, state machine and HDL design entry. Designs
can now be completed in hours as opposed to days or
weeks.

o

UltraMOS E2CMOS Choice

o

Electrically Erasable/Programmable/
Reprogrammable

o

100% Tested During Manufacture

o

100% Programming Yield

o

Fast Programming

the PLD Technology of

pLSI and ispLSI Development Tools

2-57

o

Low Cost, Fully Integrated pDS Design System
for the PC

o

pDS+ Support for Industry-Standard ThirdParty Design Environments and Platforms

o

HDL, VHDL Boolean Equation, State Machine
and Schematic Capture Entry

o
o

Timing and Functional Simulation
PC and Workstation Platforms

1994 Data Book

•

Introduction to pLSI and ispLSI 1000 Family
1000 Family Overview
The pLSI and ispLSI1 000 family of high-density devices
address high-performance system logic needs, ranging
from registers, to counters, to muHiplexers, to complex
state machines.

Each device contains mUHiple Generic Logic Blocks
(GLBs), which are designed to maximize system flexibility
and performance. A balanced ratio of registers and VO
cells provides the optimum combination of intemallogic
and external connections. A global interconnect scheme
ties everything together, enabling utilization of up to 80%
of available logic. Table 1 describes the family attributes.

With PLD densities ranging from 2,000 to 8,000 gates,
the pLSI and ispLSI1 000 Families provide a wide range
of programmable logic solutions which meet tomorrows
design requirements today.
Table 1. pLSI and ispLSI1000 Family Attributes
Family Member

1016

1024

1032

104811048C

Density (PLD Gates)

2,000

4,000

6,000

8,000

Speed: fmax (MHz)

110

90

90

80

Speed: tpd (ns)

10

12

12

15

GLBs

16

24

32

48

Registers

96

144

192

288

Inputs + I/O

36

54

72

1061110·

Pin/Package

44-pin PLCC

68-pin PLCC

84-pin PLCC

120-pin PQFP

44-pin TQFP

68-pin JLCC

1OO-pin TQFP

128-pin PQFp·

44-pin JLCC

84-pin CPGA
TabieHlOO3A

• pLSVispLSI1048C Only

2-58

1994 Data Book

Introduction to pLSI and ispLSI 1000 Family

Figure 1. 1000 Family Packages

0

pLSl1016
&
ispLSl1016

44-Pin PLCC

pLSl1032
&
ispLSl1032

pLS11024
&
ispLSl1024

68-Pin PLCC

84-Pin PLCC

pLSl1032
&
ispLSl1032

pLSl1016
&
ispLSl1016

0

0
44-PinTQFP

pLSI
10161883
&
ispLSI10161883

1 Oo-Pin TQFP

pLS110241883
&
ispLS110241883

•

pLS11048
&
ispLSl1048

12o-Pin PQFP

0

pLSI1048C
&
ispLS11048C

128-Pin PQFP

pLSI 10321883
&
ispLSI 10321883

•

lD
D
0
44-PinJLCC

68-PinJLCC

84-Pin CPGA

2-59

0288C

1994 Data Book

"

Notes

2-60

1994 Data Book

~~~Lattice
••••••

pLS/® and ispLSr 1016
M

••••••
••••••

High-Density Programmable Logic

Features

Functional Block Diagram

• PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE
HIGH DENSITY LOGIC
- High-Speed Global Interconnect
- 2000 PLD Gates
- 32 I/O Pins, Four Dedicated Inputs
- 96 Registers
- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Security Cell Prevents Unauthorized Copying

r-El , , , , , ,
El GLB ,
El , ,
L-El ,
Logic

Array

• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- fmax 110 MHz Maximum Operating Frequency
- fmax = 60 MHz for Industrial and Milltary/SS3 Devices
- tpd 10 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile E2CMOS Technology
-100% Tested

=
=

Global Routing Pool (GRP)

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
-In-System Programmable S-Volt Only
- Change Logic and Interconnects "On-the-Fly" in
Seconds
- Reprogram Soldered Device for Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global
Interconnectivity
• pLSUispLSI DEVELOPMENT SYSTEM (pDS,")
pDS Software
- Easy to Use PC Windows™ Interface
- Boolean Logic Compiler
- Manual Partitioning
- Automatic Place and Route
- Static Timing Table
pDS+™ Software
- Industry Standard, Third Party Design
Environments
- Schematic Capture, State Machine, HDL
- Automatic Partitioning
- Automatic Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workstation Platforms

III
Description
The Lattice pLSI and ispLSI 1016 are High-Density
Programmable Logic Devices containing 96 Registers,
32 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all ofthese elements. The ispLSI1 016 features
5-Volt in-system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1016 device, but multiplexes four input pins to control insystem programming.
The basic unit of logic on the pLSI and ispLSI 1016
devices is the Generic Logic Block (GLB). The GLBs are
labeled AO, A 1 .. B7 (see figure 1). There are a total of 16
GLBs in the pLSI and ispLSI 1016 devices. Each GLB
has 18 inputs, a programmable AND/ORIXOR array, and
four outputs which can be configured to be either
combinatorial or registered. Inputs to the GLB come from
the GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and imonnation herein are
subject to change without notice.

LATIICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATIICE; FAX (503) 681-3037

2-61

1994 Data Book

~HLattice
......
••••••

SpecificationspLSI and ispLSI1016

••••••

Functional Block Diagram
Figure 1. pLSI and ispLSI1 016 Functional Block Diagram

Generic

Logic Blocks
(GLBs)
IN3
MODE'IIN2

1/00
1/01
1102
V03
1/04
V05
1106
1/07
I/OB
I/O.
11010
V011

!I

il
:

I
I
I
I

0:cr:
Q.
0

I~

.5

"8a..
C>

:s"

Global
Routing

Pool
(GRP)

~

:;

~

0
11012
11013
11014
1/015

il

"ScI/INO

'SDOIIN 1

11028

11027
11026
11025
V024
11023
1/022
1/021

11020
I/O ,.
1I01B
11017
16

va

CLKO
CLK1
CLK2
loeLKO
IOCLK1

---------rMegablock

*lspENINC

11031
V030
1102.

•

YO
Y1~·

'SCLKlY2

, ISP Control Functions for ispLSI 1016 Only

·"Note: Y1 and RESET
are muHiplexed
on the same pin
0139B(1a)-ISIl.eps

The devices also have 32 1/0 cells, each of which is
directly connected to an 1/0 pin, Each 1/0 cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
1/0 pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 1/0 cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal 1/0 cells by the ORP. The pLSI and
ispLSI 1016 devices contain two of these Megablocks.

The GRP has as its inputs the outputs from all ofthe GLBs
and all of the inputs from the bi-directionall/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the pLSI and ispLSI1 016 devices are selected
using the Clock Distribution Network. Three dedicated
clock pins (YO, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK
2, 10CLK 0 and 10CLK 1) are provided to route clocks to
the GLBs and 1/0 cells. The Clock Distribution Network
can also be driven from a special clock GLB (BO on the
pLSI and ispLSI 1016 devices). The logic of this GLB
allows the user to create an internal clock from a combination of internal signals within the device.

2-62

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

Absolute Maximum Ratings

1

Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ...............-2.5 to Vee +1.0V
Off-State Output Voltage Applied ......-2.5 to Vee + 1.0V
Storage Temperature .................. -65 to 150°C
Case Temp. with Power Applied ........ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings· may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions
SYMBOL

PARAMETER

Supply Voltage

VCC

Commercial

TA = O°C to +70·C

Industrial

TA = -40°C to +85°C

Military/883

Tc = -55°C to +125°C

MIN.

MAX.

4.75

5.25

4.5

5.5

4.5

5.5

VIL

Input Low Voltage

0

0.8

VIH

Input High Voltage

2.0

Vcc + 1

UNITS

V

V
V
Table 2· OOOSAisp wlmil.eps

Capacitance (T A=25°C, f=1.0 MHz)
SYMBOL

C1
CZ

MAXIMUM1

UNITS

TEST CONDITIONS

Commercial/Industrial

8

pf

Vcc=5.0V, V'N=2.0V

Military

10

pf

Vcc=5.0V, V'N=2.0V

10

pf

V cc=5.0V, V,/O, Vy =2.0V

PARAMETER
Dedicated Input Capacitance
1/0 and Clock CapaCitance

Table 2-0006

1. Guaranteed but not 100% tested.

Data Retention Specifications
PARAMETER

MINIMUM

MAXIMUM

UNITS

Data Retention

20

-

YEARS

1000

ispLSI Erase/Reprogram Cycles

100

pLSI Erase/Reprogram Cycles

CYCLES
CYCLES
Table 2-OOOBA-I'P

2-63

1994 Data Book

•

i

!

~~~lattice

Specifications pLSI and ispLSI 1016

••••••
••••••

••••••
Switching Test Conditions
Input Pulse Levels

Figure 2. Test Load

GNDto 3.0V
~

Input Rise and Fall Time

3ns 10% to 90%

Input Timing Reference Levels

+SV

1.SV

Output Timing Reference Levels

l.SV

Output Load

Device
Test
Output ------.-----4~--~ Point

See figure 2

3-state levels are measured O.SV from steady-state
active level.

-=
Output Load Conditions (see figure 2)
Test Condition

R1

R2

CL

4700

3900

3SpF

Active High

00

3900

3SpF

Active Low

4700

3900

3SpF

00

3900

SpF

4700

3900

SpF

A
B

C

Active High to Z
at V OH - O.SV
Active Low to Z

-=

*CL includes Test Fixture and Probe Capacitance.

at VOL +O.SV
rable 2- 0004A

DC Electrical Characteristics
Over Recommended Operating Conditions
CONDITION

MIN.

TYP.3

MAX.

UNITS

VOL

Output Low Voltage

10L =8 mA

-

0.4

V

VOH

Output High Voltage

10H =-4 mA

2.4

-

V

IlL

Input or I/O Low Leakage Current

OV ~ VIN ~ VIL (MAX.)

IIH

Input or 1/0 High Leakage Current

3.SV ~ VIN ~ Vee

IIL-isp

isp Input Low Leakage Current

OV ~ VIN ~ VIL (MAX.)

IIL-PU

1/0 Active Pull-Up Current

OV~VIN ~ V IL

1081

Output Short Circuit Current

Vee = SV, VOIIf = O.SV

-

lee2

Operating Power Supply Current

SYMBOL

PARAMETER

-

-

VIL = O.SV, VIH = 3.0V I Commercial
fTOGGLE = 1 MHz

Ilndustrial/Military

-so
-

-10

IJA

10

IlA

-1S0

IlA

-1S0

IlA

-200

mA

100

1S0

mA

100

170

mA

1. One output at a time for a maximum duration of one second. Voot = O.SV was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2. Measured using four 1S-bit counters.
3. Typical values are at Vco = SV and T A = 2Soc.
Table 2-0007A-16 w/mll

2-64

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

External Timing Parameters
Over Recommended Operating Conditions

PARAMETER TESTs
CONDo

-110

DESCRIPTION!

-90

UNITS

MIN. MAX. MIN. MAX

tpd1

A

1

Data Propagation Delay, 4PT bypass, ORP bypass

-

10

A

2

Data Propagation Delay, Worst Case Path

-

14.5

-

12

tpd2

17

ns

fmax

A

3

Clock Frequency with Internal Feedback 3

111

-

90.9

-

MHz
MHz

ns

fmax (Ext.)

-

4

Clock Frequency with External Feedback (isU2 : tcol)

70.1

5

Clock Frequency, Max Toggle 4

125

125

-

tsu1

-

-

58.8

fmax (Tog.)

6

GLB Reg. Setup Time before Clock, 4PT bypass

4.5

-

6

-

ns

tc01

A

7

GLB Reg. Clock to Output Delay, ORP bypass

-

7

-

8

ns

MHz

0

-

0

-

ns

7.5

-

9

-

ns

10 GLB Reg. Clock to Output Delay

-

8.5

-

10

ns

-

11 GLB Reg. Hold Time after Clock

0

-

0

-

ns

th1

-

8

GLB Reg. Hold Time after Clock, 4 PT bypass

tsu2

-

9

GLB Reg. Setup Time before Clock

tc02

-

th2
tr1

A

12 Ext. Reset Pin to Output Delay

-

14

-

15

ns

trw1

-

13 Ext. Reset Pulse Duration

10

-

10

-

ns

ten

B

14 Input to Output Enable

-

15

-

15

ns

tdis

C

15 Input to Output Disable

-

15

-

15

ns

twh

-

16 Ext. Sync. Clock Pulse Duration, High

4

-

4

4

-

4

18 1/0 Reg. Setup Time before Ext. Sync. Clock (Y1, Y2)

2

-

2

-

ns

17 Ext. Sync. Clock Pulse Duration, Low

5.5

-

6.5

-

ns

twl
tsu5
th5
1.
2.
3.
4.
5.

if

19 1/0 Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)

Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit loadable counter using GRP feedback.
fmax (Toggle) may be less than !/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions Section.

2-65

ns
ns

Table 2-0030-161110,90C

1994 Data Book

~~~Lattice
......
••••••

SpecificationspLSI and ispLSI1016

••••••

External Timing Parameters
Over Recommended Operating Conditions

PARAMETER TEST 5 #2
CONDo

-80

DESCRIPTIONI

-60

UNITS

MIN. MAX. MIN. MAX.
1

Data Propagation Delay, 4PT bypass, ORP bypass

-

15

-

20

2

Data Propagation Delay, Worst Case Path

-

20

-

25

ns

3

Clock Frequency with Internal Feedback3

80

-

60

MHz

4

Clock Frequency with External Feedback (iSU2 ~ tcOV

50

Clock Frequency, Max Toggle4

100

-

38

5

tsu1

-

6

GLB Reg. Setup Time before Clock, 4PT bypass

7

-

9

-

tc01

A

7

GLB Reg. Clock to Output Delay, ORP bypass

-

10

-

13

ns

th1

8

GLB Reg. Hold Time after Clock, 4 PT bypass

0

-

0

-

ns

tsu2

-

9

GLB Reg. Setup Time before Clock

10

-

13

-

ns

tc02

-

10 GLB Reg. Clock to Output Delay

-

12

-

16

ns

th2

-

11 GLB Reg. Hold Time after Clock

0

-

0

-

ns

tr1

A

12 Ext. Reset Pin to Output Delay

-

17

-

22.5

ns

tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)

A
A
A

83

ns

MHz
MHz
ns

trw1

-

13 Ext. Reset Pulse Duration

10

-

13

-

ns

ten

B

14 Input to Output Enable

-

18

-

24

ns

tdis

C

15 Input to Output Disable

-

18

-

24

ns

twh

16 Ext. Sync. Clock Pulse Duration, High

5

-

6

-

ns

tsu5

-

th5

-

19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)

twl

17 Ext. Sync. Clock Pulse Duration, Low

5

-

6

2

-

2.5

-

ns

18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2)

6.5

-

8.5

-

ns

ns

Table 2-003(H6I80,60C

1.
2.
3.
4.
5.

Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit loadable counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions Section.

2-66

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1016

Internal Timing Parameters 1

PARAMETER

#2

-110

DESCRIPTION

-90

UNITS

MIN. MAX. MIN. MAX.
Inputs

-

0.8
1.7

-

1/0 Register Setup Time before Clock

4.1

-

4.5

1.8

-

2.0

1.7

tiobp

20

I/O Register Bypass

tiolat

21

1/0 Latch Delay

tiosu

22

tioh

23

1/0 Register Hold Time after Clock

tioco

24

1/0 Register Clock to Out Delay

tior

25

1/0 Register Reset to Out Delay

tdin

26

Dedicated Input Delay

-

tgrp1

27

GRP Delay, 1 GLB Load

-

0.6

tgrp4

28

GRP Delay, 4 GLB Loads

-

0.8

2.1
1.7

1.0

ns

2.0

ns

-

ns

-

2.0

ns

2.5

ns

2.0

ns

0.7

ns

1.0

ns

1.8

ns

ns

GRP
tgrp8

29

GRP Delay, 8 GLB Loads

-

1.5

-

tgrp12

30

GRP Delay, 12 GLB Loads

-

2.1

-

2.6

ns

tgrp16

31

GRP Delay, 16 GLB Loads

-

2.8

-

3.4

ns

t4ptbp

33

4 Product Term Bypass Path Delay

-

5.3

ns

34

1 Product TermlXOR Path Delay

6.1

-

6.5

t1ptxor

7.0

ns
ns

GLB
t20ptxor

35

20 Product TermIXOR Path Delay

-

6.6

-

8.0

txoradj

36

XOR Adjacent Path DelayS

-

8.2

9.5

ns

tgbp

37

GLB Register Bypass Delay

-

0.5

-

0.5

ns

tgsu

38

GLB Register Setup Time before Clock

0.3

-

1.0

-

ns

tgh

39

GLB Register Hold Time after Clock

2.9

-

3.5

-

ns

tgco

40

GLB Register Clock to Output Delay

1.6

ns

41

GLB Register Reset to Output Delay

2.1

-

1.5

tgr

-

2.5

ns

tptre

42

GLB Product Term Reset to Register Delay

-

8.2

ns

43

GLB Product Term Output Enable to 1/0 Cell Delay

-

9.0

-

10.0

tptoe

9.0

ns

tptck

44

GLB Product Term Clock Delay

2.8

6.2

3.5

7.5

ns

ORP
torp

45

ORPDelay

-

2.0

I-

2.5

ns

torpbp

46

ORP Bypass Delay

-

0.4

-

0.5

ns

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

2-67

1994 Data Book

~~~Lattice
......

••••••
••••••

Specifications pLSI and ispLSI 1016

Internal Timing Parameters 1

PARAMETER

#2

·110

DESCRIPTION

-90

UNITS

MIN. MAX. MIN. MAX.
Outputs

-

-

2.5

ns

3.3

4.0

ns

3.3

-

4.0

ns

2.9

2.9

3.5

3.5

ns

2.1

3.8

2.5

4.5

ns

4.2

1.0

5.0

ns

3.8

2.5

4.5

ns

4.2

1.0

5.0

ns

7.9

-

7.5

ns

tob

47

Output Buffer Delay

toen

48

I/O Cell OE to Output Enabled

todis

49

I/O Cell OE to Output Disabled

tgyO

50

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

tgy1/2

51

Clock Delay, Y1 or Y2 to Global GLB Clock Line

tgcp

52

Clock Delay, Clock GLB to Global GLB Clock Line

0.8

tioy1/2

53

Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line

2.1

tiocp

54

Clock Delay, Clock GLB to I/O Cell Global Clock Line

0.8

-

2.1

Clocks

Global Reset
tgr

55

Global Reset to GLB and I/O Registers

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

2·68

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1016

Internal Timing Parameters 1

PARAMETER

~

-80

DESCRIPTION

-60

UNITS

MIN. MAX. MIN. MAX.

Inputs

-

2.7

ns

4.0

ns

-

7.3

-

ns

1.3

-

ns

3.0

-

4.0

ns

2.5

-

3.3

ns

4.0

-

5.3

ns

1.5

2.0

ns

2.7

ns

4.0

ns

5.0

ns

6.0

ns

tiobp

20

1/0 Register Bypass

-

2.0

tiolat

21

I/O Latch Delay

-

3.0

tiosu

22

1/0 Register Setup Time before Clock

5.5

tioh

23

1/0 Register Hold Time after Clock

1.0

tioco

24

1/0 Register Clock to Out Delay

tior

25

1/0 Register Reset to Out Delay

tdin

26

Dedicated Input Delay

-

GRP

tgrp8

29

GRP Delay, 8 GLB Loads

30

GRP Delay, 12 GLB Loads

-

3.0

tgrp12
tgrp16

31

GRP Delay, 16 GLB Loads

-

4.5

-

t4ptbp

33

4 Product Term Bypass Path Delay

-

8.6

ns

34

1 Product TermIXOR Path Delay

-

6.5

t1ptxor

7.0

9.3

ns

t20ptxor

35

20 Product TermlXOR Path Delay

-

10.6

ns

txoradj

36

XOR Adjacent Path Delay3

tgbp

37

GLB Register Bypass Delay

tgrp1

27

GRP Delay, 1 GLB Load

tgrp4

28

GRP Delay, 4 GLB Loads

-

2.0
3.8

GLB

-

8.0
9.5
1.0

-

12.7

ns

1.3

ns
ns

tgsu

38

GLB Register Setup Time before Clock

1.0

-

1.3

-

tgh

39

GLB Register Hold Time after Clock

4.5

-

6.0

-

ns

tgco

40

GLB Register Clock to Output Delay

-

2.0

-

2.7

ns

3.3

ns

-

10.0

tgr

41

GLB Register Reset to Output Delay

tptre

42

GLB Product Term Reset to Register Delay

tptoe

43

GLB Product Term Output Enable to I/O Cell Delay

tptck

44

GLB Product Term Clock Delay

torp

45

ORP Delay

torpbp

46

ORP Bypass Delay

2.5

13.3

ns

9.0

-

12.0

ns

3.5

7.5

4.6

9.9

ns

-

2.5

-

3.3

ns

0.5

0.7

ns

ORP

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

2-69

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1016

Internal Timing Parameters 1

PARAMETER

~

-60

-80

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

Outputs
tob

47

Output Buffer Delay

ns

I/O Cell OE to Output Enabled

5.0

-

4.0

48

-

3.0

toen

6.7

ns

todis

49

I/O Cell OE to Output Disabled

-

5.0

-

6.7

ns

Clocks
tgyO

50

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

4.5

4.5

6.0

6.0

ns

tgy1/2

51

Clock Delay, Y1 or Y2 to Global GLB Clock Line

3.5

5.5

4.6

7.3

ns

tgcp

52

Clock Delay, Clock GLB to Global GLB Clock Line

1.0

5.0

1.3

6.6

ns

tioy1/2

53

Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line

3.5

5.5

4.6

7.3

ns

tiocp

54

Clock Delay, Clock GLB to I/O Cell Global Clock Line

1.0

5.0

1.3

6.6

ns

-

9.0

-

12.0

ns

Global Reset
tgr

55

Global Reset to GLB and I/O Registers

1. Internal Timin9 Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

2-70

1994 Data Book

H~Lattice
••••••

Specifications pLSI and ispLSI 1016

••••••
••••••

pLSI and ispLSI 1016 Timing Model

-------110 Cell

GRP

~

GLB

ORP

1/0 Cell

------------ ~-"---Feedback

Derivations of tsu, th and tco from the Product Term Clock1
tsu

5.5 ns

=

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
(#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
(1.0 + 1.0 + 8.0) + (1.0) - (1.0 + 1.0 + 3.5)

th

Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
3.0 ns= (1.0 + 1.0 + 7.5) + (3.5) - (1.0 + 1.0 + 8.0)

teo

Clock (max) + Reg co + Output
+ tptck(max)) + (tgco) + (torp + tab)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
16.0 ns (1.0+ 1.0 +7.5) + (1.5) + (2.5 + 2.5)

= (tiobp + tgrp4
=

Derivations of tsu, th and tco from the Clock GLB 1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgyO(min) + tgco + tgcp(min))
(#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.0 ns = (1.0 + 1.0 + 8.0) + (1.0) - (3.5 + 1.5 + 1.0)

th

Clock (max) + Reg h - Logic
(tgyO(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
3.5 ns= (3.5 + 1.5 + 5.0) + (3.5) - (1.0 + 1.0 + 8.0)

tco

Clock (max) + Reg co + Output
= (tgyO(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
16.5 ns = (3.5 + 1.5 + 5.0) + (1.5) + (2.5 + 2.5)

1. Calculations are based upon timing specs for the ispLSI 1016-90.

2-71

1994 Data Book

~~~Lattice

SpecificationspLSI and ispLSI1016

••••••
••••••
••••••

Figure 3. Typical Device Power Consumption vs fmax
150

<'

S100

u

JJ
50

o

10

20

30

40

50

60

70

80

90

100 110

fmax (MHz)
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 2S'C

ICC can be estimated for the pLSI and ispLSI1016 using the following equation:
ICC =31 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.009) where:
# of PTs =Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq

=Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC =5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127A-16-80-isp.eps

Figure 4. Maximum GRP Delay vs GLB loads

pLSI and ispLSI 1016-60

6
~

III

c::

>.
al

5

pLSI and ispLSI 1016-80

4
pLSI and ispLSI 1016-90,

Q)

o
a.. 3
a:
C!l

pLSlandispLSl1016-110

2

O~

____

~

4

______

~

______

8

~

______

12

~

16

GLB Loads
0126A-BO-16-isp.eps

2-72

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions of the Lattice High-Density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip. programming
can be accomplished by simply shifting data into the
device. Once the function is programmed. the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TTL level
logic interface signals. These five signals are fed into the
on-chip programming circuitry where a state machine
controls the programming. The interface signals are isp
Enable (ispEN). Serial Data In (SOl). Serial Data Out
(SDO). Serial Clock (SCLK) and Mode (MODE) control.
Figure 5 illustrates the block diagram of one possible
scheme for programming the ispLSI devices. For details
on the operation of the internal state machine and programming of the device please refer to the in-system
programming section in this Data Book.

Figure 5. ISP Programming Interface

SOO
SOl
MODE
SCLK
ispEN

}

5-wire ISP
Programming
Interface

'--'---

ispLSI
~

--

'--

f--+

ispGAL

'--

ill

' - - ispGOS

f----

f--

ispLSI

'l
02946

2-73

1994 Data Book

!

--

~HLattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

ISP Programming Voltage/Timing Specifications 1
SYMBOL

CONDITION

PARAMETER

VCCP

Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

VILP

Input Voltage Low

ispEN = Low

liP

Input Current

VOHP

Output Voltage High

IOH= -3.2 rnA

VOlP

Output Voltage Low

100.=5 rnA

tr tf

Input Rise and Fall

tispen

ispEN to Output 3-State Enabled

tispdis

ispEN to Output 3-State Disabled

tsu

Setup Time

tco

MIN.

TYP.

MAX.

UNITS

4.75

5

5.25

V

-

50

100

rnA

2.0

-

Veep

V

0

-

0.8

V

-

100

200

JLA

Veep

V

2.4
0

-

0.5

V

0.1

jLS

2

10

jLS

2

10

jLS

0.1

0.5

-

jLS

Clock to Output

0.1

0.5

th

Hold Time

0.1

0.5

tclkh, tclkl

Clock Pulse Width, High and low

0.5

1

tpwv

Verify Pulse Width

20

30

tpwp

Programming Pulse Width

40

tbew

Bulk Erase Pulse Width

200

Reset Time From Valid Veep
trst
1. ISP Programming is guaranteed !orTA • O'C to 70'C Operation only.

45

-\

-

2-74

-

100

-

jLS
jLS
jLS
jLS

ms
ms
jLS

1994 Data Book

H~Lattice
••••••

Specifications pLSI and ispLSI 1016

••••••
••••••

Figure 6. Timing Waveforms for In-System Programming (ispLSI1016)
VCC

/I

---'-I trst

Unused ~~~~~~~~77~~~~7/~77~~7?~7/~77~~~

Input

Unused

'-'~".../I'~)C)1~~"~~"~~".£..I.~""""""~~w~CLYI'
:~~~~~~~~~

•

________________________________________________________________________________~~~

Output "'"

MODE _______________--+_

SCLK _______________--+_______

OtBtB

~

Don'tCare

~

Undefined State

Figure 7. Program, Verify & Bulk Erase Waveforms (ispLSI1016)
Execute State (Program, Verify or Bulk Erase Instruction)
MODE
tpwp, tbew, or tpwv

501

~------th-------~'----+-------------'

"

1+--+r~:..!!:tc~lk!!.:h~
SCLK

tsu

,,__----J/

FtC'k'~/.

2-75

"'--1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1016

••••••

Figure 8 illustrates the address and data shift register bits
for the ispLSI 1016. For a detailed explanation refer to

the Device Layout discussion in the pLSI and ispLSI
Architectural Description section of this Data Book.

Figure 8. ispLSI1016 Shift Register Layout
D
A
T
A

D
A
T
A

High Order Shift Register
Low Order Shift Register

SOO
SOl

95

E2CMOS Cell Array

6
SDO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic "0" disables it.

2-76

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

• •••••
••••••
••••••

Pin Description

Name

TQFP
PLCC
JLCC
Pin Numbers Pin Numbers Pin Numbers

1/00-1/03
9, 10,
13, 14,
1/04-1/07
1/08-1/011
19, 20,
1/012 -1/015 23, 24,
1/016 -1/019 31, 32,
110 20 - 110 23 35, 36,
110 24 - 110 27 41, 42,
110 28 - 110 31 1, 2,

11,
15,
21,
25,
33,
37,
43,
3,

12,
16,
22,
26,
34,
38,
44,
4

15,
19,
25,
29,
37,
41,
3,
7,

16,
20,
26,
30,
38,
42,
4,
8,

17,
21,
27,
31,
39,
43,
5,
9,

18,
22,
28,
32,
40,
44,
6,
10

15,
19,
25,
29,
37,
41,
3,
7,

16,
20,
26,
30,
38,
42,
4,
8,

17,
21,
27,
31,
39,
43,
5,
9,

Description

18, Input/Output Pins - These are the general purpose 110
22, pins used by the logic array.
28,
32,
40,
44,
6,
10

40

2

2

Dedicated input pins to the device.

7

13

13

SDI"/IN 0

8

14

14

MODE"/IN2

30

36

36

SDO"/IN 1

18

24

24

SCLK"!Y2

27

33

33

Input - Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input - This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load
programming data into the device. SDI/IN 0 also is
used as one of the two control pins for the isp state
machine.
Input - This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as a pin to control the
operation of the isp state machine.
Input/Output - This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input - This pin performs two functions. It is a
dedicated clock input when ispEN is logic high. This
clock input is brought into the Clock Distribution
Network, and can optionally be routed to any GLB
andlor 110 cell on the device. When ispEN is logic low,
itfunctions as a clock pin forthe Serial Shift Register.

YO

5

11

11

Y1/RESET

29

35

35

GND
VCC

6,

IN3

17, 39
28

1, 23
12, 34

Dedicated Clock input. This clock input is connected
to one of the clock inputs of all of the GLBs on the
device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can
optionally be routed to any GLB andlor 110
cell on the device.
- Active Low (0) Reset pin which resets all of the
GLB and 110 registers in the device.

1,

23
12, 34

Ground (GND)

Vee
Table 2 - 0002G-16-isp

• For ispLSI 1016 Only

2-77

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI1016 44-Pin PLCC Pinout Diagram

1/028
1/029

1/018
1/017
1/016

1/030
1/031
YO
VCC
'ispEN/NC
'SOI/INO

IN 21MOOE'

pLSI1016
and
ispLSI1016

Yl/RESET
VCC
Y2ISCLK'

1/015

1/014

1/00
1/01

1/013
1/012

1/02

'Pins have dual function capability for ispLSll016 only (except pin 13, which is ispEN only).
0123A-lsp1016

pLSI and ispLSI1 016 44-Pin JLCC Pinout Diagram

1/028
1/029
1/030

VCC
'ispENlNC
'SOI/IN

a

1/018

38

1/017
1/016

37

1/031
YO

39

pLSI 1016/883
and
ispLSI 1016/883

1/00
1/01
1/02

36

IN 21MOOE'
Yl/RESET

vcc
Y2ISCLK'
32
31

1/015
1/014
1/013
1/012

, Pins have dual function capability for ispLSll016 only (except pin 13, which is ispEN only).
0123-16-1splJLCC

2-78

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1016

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI1016 44-Pin TQFP Pinout Diagram

11028

11018

11029

11017

11030

11016

11031

YO
VCC
"ispENfNC
"SDIIIN 0

pLSI1016
and
ispLSI1016

IN2IMODE"
YllRESET
VCC
Y2ISCLK"
11015

1100

11014

1101

11013

1102

11012

" Pins have dual function capability for ispLSll016 only (except pin 7, which is ispEN only).
0851-161TQf

2-79

1994 Data Book

~~~Lattice

SpecificationspLSI and ispLSI1016

••••••
••••••

••••••
Part Number Description

5

XXXX (XX) 1016 - XXX

DeviceFamily
pLSI
ispLSI

X

L
X

X

Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
Package
J= PLCC
T=TQFP
H =JLCC
' - - - - - - - - Power
L= Low

Device Number
Speed - - - - - - - - - - - - '
110 = 110 MHz fmax
90 = 90 MHz fmax
80 = 80 MHz fmax
60 = 60 MHz fmax

00212-80B-isp1016

pLSI and ispLSI 1016 Ordering Information
COMMERCIAL
Family

pLSI

fmax(MHz)

tpd (ns)

Ordering Number

Package

110

10

pLS1101S-110LJ

44-PinPLCC

110

10

pLS11016-110LT

44-PinTOFP

90

12

pLSI 1016-90LJ

44-Pin PLCC

90

12

pLSI 1016-90LT

44-PlnTOFP

80

15

pLS1101S-80LJ

44-Pin PLCC

80

15

pLSI 1016-80LT

44-PinTOFP

60

20

pLSI 101S-60LJ

44-Pin PLCC

SO

20

pLSI101S-S0LT

44-PinTOFP

110

10

ispLS11016-110LJ

44-Pin PLCC

110

10

ispLS1101S-110LT

44-PinTOFP

90

12

ispLSI 1016-90LJ

44-Pin PLCC

90

12

ispLSI 1016-90LT

44-Pin TOFP

80

15

ispLSI 101S-80LJ

44-Pin PLCC

80

15

ispLSI 101S-80LT

44-PinTOFP

SO

20

ispLSI 1016-60LJ

44-Pin PLCC

SO

20

ispLSI 101S-60LT

44-Pin TOFP

Family

fmax(MHz)

tpd (ns)

Ordering Number

Package

pLSI

SO

20

pLSI 101S-60LJI

44-Pin PLCC

lapLSI

SO

20

ispLSI 101S-S0LJI

44-Pin PLCC

Family

fmax(MHz)

tpd (ns)

Ordering Number

Package

pLSI

60

20

pLSI101S-60LH/883

44-PinJLCC

lapLSI

80

20

ispLSI 1016-60LHl883

44-PinJLCC

ispLSI

INDUSTRIAL

MILITARY1883

Table2-0041-16-\sp1016

2-80

1994 Data Book

~~~Lattice

pLS/® and ispLSf 1024
M

High-Density Programmable Logic

••••••
••••••
••••••

Features

Functional Block Diagram

• PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE
HIGH DENSITY LOGIC
- High-Speed Global Interconnect
- 4000 PLD G_a
- 48 110 Pine, Six Dadlcated Inputa
-144 Regl_ra
- Wide Input Gating for Faat Countera, State
Machlnea, Addre.. Decodera, atc.
- Small Logic Block Size for Faat Random Logic
- Security Cell Preventa Uneuthorlzed Copying
• HIGH PERFORMANCE E2cMOse TECHNOLOGY
- fmax = 90 MHz Maximum Operating Frequency
- fmax = 60 MHz for Induatrlal and Mllitary1883 Devicea
-tpd = 12 na Propagation Delay
- TTL Compatible Inputa and OUtputa
- Electrically Era..ble and Reprogrammable
- Non-Volatile EICMOS Technology
-100% Teated
• iapLSI OFFERS THE FOLLOWING ADDED FEATURES
-In-Syatem Programmable 5-Von Only
- Changa Logic and Interconnecta ·On-the-Fly" in
Seconda
- Reprogram Soldered Device for Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDa WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue
Logic and Structured Dealgna
- Four Dadlcated Clock Input Pina
- Synchronoua and Aaynchronoua Clocka
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global
Interconnectivlty
• pLSllispLSI DEVELOPMENT SYSTEM (pDS~
pDS Software
- Easy to Use PC Windows™ Interface
- Boolean Logic Compiler
- Manual Partnioning
- Automatic Place and Route
- Static Timing Table
pDS+ TM Software
- Industry Standard, Third Party Design
Envlronmenta
- Schematic Capture, State Machine, HDL
- Automatic Partitioning and Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workatatlon Platforma

I

,@Z]r-I

Ir-~

1u."IB "'" i~~
@±I ~ 19

uHf
19.9 ;g

Array

1 ~~
1". 6~
IA7I
~1B1

.......

I

R GLB
U,'

B,/

[§]a:13

[§] ~ EI

'@!]81"

Global Routing Pool (GRP) ICQl
L.:::!:!.I .......".,

~

li.J.l

~~~~~~~~ I"'-CL-K~Output Routing Pool
I ......~­
III BlEIl m.mm D.IlEI BlEIl rlei
I

III

0139-A-itp

Description
The Lattice pLSI and ispLSI 1024 are High-Density
Programmable Logic Devices containing 144 Registers,
48 Universal VO pins, six Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI1 024 features
5-VoH in-system programmability and in-system diagnostic capabilities. It is the first device which offers
non-volatile ·on-the-fly" reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems. It is architecturally and parametrically compatible to the pLSI 1024 device, but multiplexes four of the
dedicated input pins to control in-system programming.
The basic unit of logic on the pLSI and ispLSI 1024
devices is the Generic Logic Block (GLB). The GLBs are
labeled AO, A1 .. C7 (see figure 1). There are a total of
24 GLBs in the pLSI and ispLSI1 024 devices. Each GLB
has 18 inputs, a programmable AND/ORIXOR array, and
four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.

Copyright 0 1994 Lattice SemiDonductor Corp. AI brand or product names are trademarks or registered trademarks of their respective hokters. The Specifications and information herein are
subject to change wtlhoul notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503)681.0118; 1-800·LATTICE; FAX (503) 681-3037

2-81

1994 Data Book

~HLattice
......
••••••

Specifications pLSI and ispLSI 1024

••••••

Functional Block Diagram
Figure 1.pLSI and ispLSI1024 Functional Block Diagram

Generic
Logic Blocks
(GLBs)

:1
:1

1/047
1/046
1/045

1100 :
1/01
1/02 :
1/03 :

1104

1/05 :
1/06 :
1/07 :
,

11044
1/043
1/042
1/041
1/040

~

11039
11038
11037
1/036

In

1/08:1

1109 :
1/010 :

~

-

1/01' :

1/035
1/034
1/033
1/032

CLKO

elK 1
CLK2
IOCLKO
IOCLK1

*ispENlNC

lit
00000000

00000000

00000000

00000000

16 17 18 19

20 21 22 23

24252627

2829 30 31

'ISP Control Functions for isp1024 Only

01390(1a)-lsp.eps

The devices also have 48 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 rnA or sink 8 rnA.
Eight GlBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GlBs are connected
to a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The plSI and isplSI 1024 devices
contain three of these Megablocks.

The GRP has as its inputs the outputs from all ofthe GlBs
and all of the inputs from the bi-directionall/O cells. All of
these signals are made available to the inputs of the
GlBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the plSI and isplSI 1024 devices are selected
using the Clock Distribution Network. Four dedicated
clock pins (YO, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (ClK 0, ClK
1, ClK 2, 10ClK 0 and 10ClK 1) are provided to route
clocks to the GlBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GlB (B4
on the plSI and isplSI1024 devices). The logic of this
GlB allows the user to create an internal clock from a
combination of internal signals within the device.

2-82

1994 Data Book

~~~Latlice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

Absolute Maximum Ratings 1
Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ...............-2.5 to Vee + 1.0V
Off-State Output Voltage Applied ......-2.5 to Vee +1.0V
Storage Temperature ..................-65 to 150°C
Case Temp. with Power Applied ........-55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings· may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming. follow the programming specifications).

DC Recommended Operating Conditions
SYMBOL

PARAMETER

Supply Voltage

VCC

MIN.

MAX.

UNITS

Commercial

TA = O·C to +70·C

4.75

5.25

Industrial

TA = -40·C to +85·C

4.5

5.5

Military/883

Tc = -55·C to +125·C

4.5

5.5
0.8

V

Vcc+ 1

V

VIL

Input Low Voltage

0

VIH

Input High Voltage

2.0

V

Table 2- OOOSAJep whnll.epI

Capacitance (T A=25°C, f=1.0 MHz)
SYMBOL

C1
CZ

MAXIMUM1

UNITS

TEST CONDITIONS

CommerciaVlndustrial

8

pf

Vcc=5.0V. V'N=2.0V

Military

10

pf

Vcc=5.0V. V,~2.0V

10

pf

Vcc=5.0V. VIIO ' Vv=2.0V

PARAMETER
Dedicated Input Capacitance
I/O and Clock Capacitance

T. . . 2-0008

1. Guaranteed but not 100% tested.

Data Retention Specifications
PARAMETER
Data Retention

MINIMUM

MAXIMUM

UNITS

20

-

CYCLES

ispLSI Erase/Reprogram Cycles

1000

pLSI Erase/Reprogram Cycles

100

2-83

-

YEARS
CYCLES

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

Switching Test Conditions
Figure 2. Test Load

GNDto 3.0V

Input Pulse Levels

~3ns

Input Rise and Fall Time

10% to 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

+5V

See figure 2

Output Load

Device
Test
Output - - - - -......- -....-----i~ Point

3-state levels are measured 0.5V from steady-state
active level.

Output Load Conditions (see figure 2)
Test Condition
A
B

Active High
Active Low

C

Active High to Z
atVOH -0.5V
Active Low to Z

R1

R2

CL

470n

390n

35pF

00

390n

35pF

470n

390n

35pF

00

390n

5pF

470n

390n

5pF

*CL includes Test Fixture and Probe Capacitance.

at VOL + 0.5V
Table 2· OOO4A

DC Electrical Characteristics
Over Recommended Operating Conditions
MIN.

TYP.3

VOL

Output Low Voltage

IOl=8 mA

-

VOH

Output High Voltage

IOH =-4 mA

2.4

IlL

Input or VO Low Leakage Current

OV s Y'N S V,l (MAX.)

-

IIH

Input or VO High Leakage Current

3.5V s Y'N S Vee

-

IIL-isp

Isp Input Low Leakage Current

OV S Y'N S V,l (MAX.)

IIL-PU

VO Active Pull-Up Current

OVs Y'N SV,l

105 1

Output Short Circuit Current

Vee = 5V, VOUT = 0.5V

-

Icc2

Operating Power Supply Current

V,l = 0.5V, V,H = 3.0V I Commercial

SYMBOL

PARAMETER

CONDITION

f TOGGLE = 1 MHz

-

-60
IlndustriaVMilitary

-

MAX.

UNITS

0.4

V

-

V

-10

-150

ItA
ItA
ItA
ItA

-200

mA

130

190

mA

135

220

mA

10
-150

1. One output at a time for a maximum duration of one second. V... = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at Vcc = 5V and TA = 25°C.

2-84

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TESTs
CONDo

.2

-90

DESCRIPTIONl

-80

-60

UNITS

MIN. MAX. MIN. MAX. MIN. MAX

-

15

17

-

20

80
50

-

-

25

ns

60

-

MHz

38

MHz

tpd2

A

2

Data Propagation Delay, Worst Case Path

-

Tmax

A

3

Clock Frequency with Internal Feedbaci(3

90.9

-

4

Clock Frequency with External Feedback(iou2 ~IC01)

58.8

-

5

Clock Frequency, Max Toggle 4

125

-

100

tsul

-

6

GLB Reg. Setup Time before Clock, 4PT bypass

6

-

7

-

9

-

tcol

A

7

GLB Reg. Clock to Output Delay, ORP bypass

-

8

-

10

-

13

ns

thl

-

8

GLB Reg. Hold Time after Clock, 4 PT bypass

0

-

0

0

ns

9

GLB Reg. Setup Time before Clock

tpdl

Tmax (Ext.)
Tmax (Tog.)

A

1

Data Propagation Delay, 4PT bypass, ORP bypass

12

20

83

ns

MHz
ns

9

-

10

-

13

-

tc02

-

10 GLB Reg. Clock to Output Delay

-

10

-

12

-

16

ns

th2

-

11 GLB Reg. Hold Time after Clock

0

-

0

-

0

-

ns
ns

Isu2

-

ns

trl

A

12 Ext. Reset Pin to Output Delay

-

15

-

17

-

22.5

trwl

-

13 Ext. Reset Pulse Duration

10

-

10

-

13

-

ns

ten

B

14 Input to Output Enable

-

15

18

-

24

ns

C

15 Input to Output Disable

-

15

-

18

-

24

ns

16 Ext. Sync. Clock Pulse Duration, High

4

5

-

ns

4

6

-

ns

18 VO Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

2

2

2.5

-

ns

6.5

-

6.5

-

6

17 Ext. Sync. Clock Pulse Duration, Low

-

8.5

-

ns

tdis
twh
lwl
tsu5
th5

-

19 1/0 Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

5

Table 2-()()3().2419O,80,6OC

1.
2.
3.
4.
5.

Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock.
Refer to Timing Model in this data sheet for further details.
Standard l6-Bit loadable counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twll. This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions Section.

2-85

1994 Data Book

•

"

~HLattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1024

Internal Timing Parameters 1

PARAMETER

#2

-90

DESCRIPTION

-80

-60

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.
Inputs

-

5.5

-

1.0

-

2.4

-

2.8

-

-

4.8

-

2.1

-

-

Dedicated Input Delay

-

3.2

20

I/O Register Bypass

tiolat

21

I/O Latch Delay

tiosu

22

I/O Register Setup Time before Clock

tioh

23

I/O Register Hold Time after Clock

tioco

24

I/O Register Clock to Out Delay

tior

25

I/O Register Reset to Out Delay

tdin

26

-

3.0

2.4

tiobp

1.6

2.0

2.7

ns

4.0

ns

7.3

-

ns

1.3

-

ns

3.0

-

4.0

ns

2.5

-

3.3

ns

4.0

-

5.3

ns

GRP
tgrpl

27

GRP Delay, 1 GLB Load

-

1.2

tgrp4

28

GRP Delay, 4 GLB Loads

-

1.6

1.5

-

2.0

ns

2.0

-

2.7

ns

2.4

-

tgrp8

29

GRP Delay, 8 GLB Loads

-

tgrp12

30

GRP Delay, 12 GLB Loads

4.0

ns

-

3.0

-

3.8

5.0

ns

3.6

6.0

ns

5.0

-

4.5

GRP Delay, 24 GLB Loads

-

-

tgrp16

31

GRP Delay, 16 GLB Loads

tgrp24

32

6.3

-

8.3

ns

t4ptbp

33

4 Product Term Bypass Path Delay

-

5.2

-

6.5

-

8.6

ns

t1ptxor

34

1 Product TermIXOR Path Delay

-

5.7

-

7.0

9.3

ns

t20ptxor

35

20 Product TermIXOR Path Delay

-

7.0

8.0

txoradj

36

XOR Adjacent Path Delay3

8.2

tgbp

37

GLB Register Bypass Delay

-

-

-

tgsu

38

GLB Register Setup Time before Clock

1.2

1.0

tgh

39

GLB Register Hold Time after Clock

3.6

-

tgco

40

GLB Register Clock to Output Delay

1.6

tgr

41

GLB Register Reset to Output Delay

-

2.0

tptre

42

GLB Product Term Reset to Register Delay

8.0

tptoe

43

GLB Product Term Output Enable to I/O Cell Delay

tptck

44

GLB Product Term Clock Delay

torp

45

torpbp

46

3.0

GLB

0.8

10.6

ns

12.7

ns

1.0

-

1.3

ns

-

1.3

-

ns

4.5

-

6.0

-

ns

-

2.0

-

2.7

ns

-

2.5

-

3.3

ns

10.0

-

13.3

ns

9.0

-

12.0

ns

7.5

4.6

9.9

ns

9.5

-

7.8

-

2.8

6.0

3.5

ORP Delay

-

2.4

-

2.5

-

3.3

ns

ORP Bypass Delay

-

0.4

-

0.5

-

0.7

ns

ORP
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

2-86

1994 Data Book

H~Lattice

••••••
••••••

......

Specifications pLSI and ispLSI 1024

Internal Timing Parameters 1

PARAMETER

t?-

-90

DESCRIPTION

-80

-60

MIN. MAX. MIN. MAX. MIN. MAX.

UNITS

Outputs
tob

47

Output Buffer Delay

toen

48

VO Cell OE to Output Enabled

todis

49

I/O Cell OE to Output Disabled

-

2.4

-

3.0

4.0

-

5.0

-

4.0

-

5.0

-

4.0

ns

6.7

ns

6.7

ns

Clocks
tgyO

50

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

3.6

3.6

4.5

4.5

6.0

6.0

ns

tgy1/2

51

Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.8

4.4

3.5

5.5

4.6

7.3

ns

tgcp

52- Clock Delay, Clock GLB to Global GLB Clock Line

0.8

4.0

1.0

5.0

1.3

6.6

ns

tioy213

53

Clock Delay, Y2 or Y3 to 1/0 Cell Global Clock Line

2.8

4.4

3.5

5.5

4.6

7.3

ns

tiocp

54

Clock Delay, Clock GLB to 110 Cell Global Clock Line

0.8

4.0

1.0

5.0

1.3

6.6

ns

-

8.2

-

9.0

-

12.0

ns

Global Reset
tgr

55

Global Reset to GLB and VO Registers

1. Intamal Timing Parametars are not tastad and are for reference only.
2. Refer to Timing Model In thls data sheet for further details.

2-87

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1024

••••••

pLSI and ispLSI 1024 Timing Model
1/0 Cell

GRP

GLB

ORP

1/0 Cell

----~-----------------~
Feedback

Derivations of tsu, th and tco from the Product Term Clock1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)
(#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)

th

Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0 ns= (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)

tco

Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max) + (tgco) + (torp + tab)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)

Derivations of tsu, th and tco from the Clock GLB1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgyO(min) + tgco + tgcp(min)
(#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)

th

Clock (max) + Reg h - Logic
(tgyO(max) + tgco + tgcp(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns= (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)

tco

Clock (max) + Reg co + Output
= (tgyO(max) + tgco + tgcp(max) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)

1. Calculations are based upon timing specs for the pLSI and ispLSI 1024-80.

2-88

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

Figure 3. Typical Device Power Consumption vs fmax
200

150

l

~ 100

50

o

10

20

30

40

50

60

70

80

fmax (MHz)
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V. 25'C

ICC can be estimated for the pLSI and ispLSI 1024 using the following equation:

=

ICC 42 + (# of PTs ·0.45) + (# of nets· Max, freq • 0.008) where:
# of PTs Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device

=

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127A-24-80-iap

Figure 4. Maximum GRP Delay vs GLB Loads
pLSI and ispLS11024-60

6

>QS

pLSI and ispLS11024-80

4

pLSI and ispLSI 1024-90

Q)

C
0..

3

"

2

a:

O~

__

~

______

~

______

8
GLB Loads

~

______

12

~

16
0126A-80-24-isp.eps

2-89

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions ofthe Lattice High-Density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip, programming
can be accomplished by simply shifting data into the
device. Once the function is programmed, the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TIL level
logic interface Signals. These five signals are fed into the
on-Chip programming circuitry where a state machine
controls the programming. The interface signals are isp
Enable (ispEN), Serial Data In (SOl), Serial Data Out
(SOO), Serial Clock (SCLK) and Mode (MODE) control.
Figure 5 illustrates the block diagram of one possible
scheme for programming the ispLSI devices. For details
on the operation of the internal state machine and programming of the device please refer to the in-system
programming section in this Data Book.

Figure 5. ISP Programming Interface

SOO
SOl
MODE
SCLK
ispEN

-

}

5-wire ISP
Programming
Interface

-

--+

ispLSI

-----.

ispGAL

'-~

----.

2-90

ill
ispGOS

f----+

ispLSI

I

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

ISP Programming Voltageffiming Specifications 1
SYMBOL

PARAMETER

VCCP

Programming Voltage

Iccp

Programming Supply Current

CONDITION

MIN.

TYP.
5

MAX.

4.75

5.25

UNITS
V

-

50

100

rnA

VIHP

Input Voltage High

2.0

-

Veep

V

VllP

Input Voltage low

0

-

0.8

V

liP

Input Current

-

100

200

itA

VOHP

Output Voltage High

2.4

Veep

V

VOlP

Output Voltage low

0

-

0.5

V

tr, tf

Input Rise and Fall

-

-

0.1

I!S

tispen

ispEN to Output 3-State Enabled

-

2

10

its

ispEN = low

IOH= -3.2 mA
10l=5mA

tispdis

ispEN to Output 3-State Disabled

2

10

its

tsu

Setup Time

0.1

0.5

-

its

tco

Clock to Output

0.1

0.5

-

Hold Time

0.1

0.5

tclkh, tclkl

Clock Pulse Width, High and low

0.5

1

-

its

th

tpwv

Verify Pulse Width

20

30

-

tpwp

Programming Pulse Width

40

-

100

tbew

Bulk Erase Pulse Width

200

trst

Reset Time From Valid Veep

45

1. ISP Programming is guaranteed for TA = O'C to 70·C Operation only.

2-91

-

-

its
its
its

ms
ms
its
Table 2- 00291sp-C

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 1024

••••••
••••••

Figure 6. Timing Waveforms for In-System Programming (ispLSl1 024)

Unu~ ~~~~~~*-1!~

Output ~

____________________________

~~~

MODE ______--+_

SCLK _ _ _-+__

0181e

2LZ

Don't Care

~

Undefined State

Figure 7. Program, Verify & Bulk Erase Waveforms (ispLSI1024)

Execute State (Program, Verify or Bulk Erase Instruction)

MODE
tpwp, tbew, or tpwv
SOl

14--- til --~

"

1+-~=..!tc~lkh:!!;~
SCLK

------""

.

'---+-------'

,----/ ''---

tsu

Ftclkl~/.

2·92

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1024

••••••

••••••
••••••

FigureBillustratestheaddressanddatashiftregisterbits
for the ispLSI 1024. For a detailed explanation refer to

the Device Layout discussion in the pLSI and ispLSI
Architectural Description section of this Data Book.

Figure 8. IspLSI 1024 Shift Register Layout

Oata In
(SOl)

o

o

A
T

A
T

A

A

Hi h Order Shift Re ister

SOO
SOl
101

E2CMOS Cell Array

6

soo

Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic ·0' disables it.

2-93

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1024

••••••

Pin Description

Name

PLCC and JLCC
Pin Numbers

1/00-1103
1/04-1/07
1/08-1/011
I/O 12 -I/O 15
I/O 16 -I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 -1/047

22,
26,
30,
37,
41,
45,
56,
60,
64,
3,
7,
11,

23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
8,
12,

IN 4-IN 5

2,

15

--

24,
28,
32,
39,
43,
47,
58,
62,
66,
5,
9,
13,

25,
29,
33,
40,
44,
48,
59,
63,
67,
6,
10,
14

Description
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.

Dedicated input pins to the device.

ispEN'/NC

19

Input - Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.

SDI'/IN 0

21

MODE'/IN 3

55

Input - This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input - This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.

SDO'/IN 1

34

SCLK'/IN 2

49

RESET

20

Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.

YO

16

Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.

Y1

54

Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.

Y2

51

Y3

50

Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.

GND
VCC

1,
17,

Input/Output - This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input - This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, itfunctions as a clock pin
for the Serial Shift Register.

18,
36,

35,
53,

52
68

Ground (GND)
Vee

'For ispLSI 1024 Only
Table 2- 0002B-24-isp

2-94

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1024

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI1024 68-Pln PLCC Pinout Diagram
~;~~.~.~c8~~~~"g~
ggggggg~~>ggggggg

1,045

1.048
1.047
INS

vo
vee
GND

"iiiim'NC

ReSET

•

11028
11027
11028
11025
11024

1.043
1.0 ..

INa.t.Iooe"

v,

pLSI1024
and
ispLSI1024

vee
GND
Y2

va
IN2ISeLK"

11023
Iltll
1.02

1/022

1102'
1/020

110'9

~~~~~Or_DO~~·~~~m

ggggggg~~gggggggg

!il
.. Pins have dual1unclion capabilily for iapLS11020f only (exceptpin

1e. which is IspEN only).

pLSI and ispLSI1024 68-Pin JLCC Pinout Diagram

11043
11044
11045
11046
11047
INS
YO

vcc
GNO
"ispENi1'jC

REsE'i'

11028
11027
11026
110 25
11024

pLSI 10241883

and
ispLSI10241883

"SOVINO
1100
1101
1102
1103
1104

IN3IMOOE"
VI

vcc
GNO
V2
V3
IN2ISCLK"
11023
11022
11021
11020
110 19

~~~~QO--CON~.~~~m

ggggggg~~gggggggg

£Il
"Pins hay. dualluncHoo capability for iIIpLSl 1024 only (except pin 19, which ill ispEN only).
Ot2H4-llp(R.CC

2-95

1994 Data Book

I

~~~Lattice
••••••

Specifications pLSI and ispLSI 1024

••••••
••••••

, Part Number Description

(is)pLSI

1024 - XX

L

x x

Device Famlly----II

J...J

Device Number _ _ _ _ _

Speed - - - - - - - - - - - - - '
90 90 MHz 'max

=

'max

80 =80 MHz
60 = 60 MHz fmax

X

Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process

Package
J=PLCC
H=JLCC
' - - - - - - Power
L=Low

00212-80B-1sp102.

pLSI and ispLSI 1024 Ordering Information
COMMERCIAL
Family

pLSI

ispLSI

fmax(MHz)

tpd (ns)

Ordering Number

Package

90

12

pLSI 1024-90LJ

68-Pin PLCC

80

15

pLSI 1024-80LJ

68-Pin PLCC

60

20

pLS11024-60LJ

68-Pin PLCC

90

12

ispLSI 1024-90LJ

68-Pin PLCC

80

15

ispLS11024-80LJ

68-Pin PLCC

60

20

ispLSI 1024-60LJ

68-Pin PLCC

INDUSTRIAL
Family

fmax (MHz)

tpd (ns)

Ordering Number

Package

pLSI

60

20

pLS11024-60LJI

68-Pin PLCC

ispLSI

60

20

ispLS11024-60LJI

68-Pin PLCC

MILITARY1883
Family

fmax (MHz)

tpd (ns)

Ordering Number

Package

pLSI

60

20

pLSI 1024-60LHl883

68-Pin JLCC

IspLSI

60

20

ispLSI 1024-60LHl883

68-Pin JLCC
Table 2-004 1A-24-1sp

2-96

1994 Data Book

~~~Lattice

pLS/® and ispLSf 1032
M

High-Density Programmable Logic

••••••
••••••
••••••

. -----llill

Features

Functional Block Diagram

• PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE
HIGH DENSITY LOGIC
- High Speed Global Interconnect
- 6000 PLD Gates
- 64 VO Pins, Eight Dedicated Inputs
- 192 Registers
- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Fast Random Logic
- Security Cell Prevents Unauthorized Copying

I

§1§]~~§]§]§]§]

~
I o@:l

=
=

pDS Software
- Easy to Use PC WlndowsTM Interface
- Boolean Logic Compiler
- Manual Partitioning
- Automatic Place and Route
- Static Timing Table
pDS+™ Software
- Industry Standard, Third Party DeSign
Environments
- Schematic Capture, State Machine, HDL
- Automatic Partitioning and Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workstation Platforms

LogiC
Array

EI
EI

I

@]o
,@] ~

I
g: I~ I

'
GlB,

@] ~

_E1 //

@DBI

~ Global Routing Pool (GRP) ~o

~~~§]~~~~

. ----I

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
- In-System Programable S-Volt Only
- Change Logic and Interconnects "On-the-Fly" in
Seconds
- Reprogram Soldered Device for Debugging

• pLSVispLSI DEVELOPMENT SYSTEM (pD~

-E1

I ~~ II::A21I
I ~IA51
I BIABI

• HIGH PERFORMANCE E2CMOS'" TECHNOLOGY
- fmax 90 MHz Maximum Operating Frequency
- fmax 60 MHz for Industrial and Military/883 Devices
- tpd = 12 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile E2CMOS Technology
- 100% Tested

• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
- Four Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global
Interconnectivity

I

Output Routing Pool

I

Output Routing Pool

I

elK

Description

The Lattice pLSI and ispLSI 1032 are High-Density
Programmable LogiC Devices containing 192 Registers,
64 Universal 1/0 pins, eight Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSl1 032 features
5-Volt in-system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032 device, but multiplexes four of the dedicated input
pins to control in-system programming.
The basic unit of logic on the pLSI and ispLSI 1032
devices is the Generic Logic Block (GLB). The GLBs are
labeled AO, A 1 .. D7 (see figure 1). There are a total of
32 GLBs in the pLSI and ispLSl1 032 devices. Each GLB
has 18 inputs, a programmable AND/OR/XOR array, and
four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.

Copyright © 1994 lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

2-97

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Functional Block Diagram
Figure 1. pLSI and ispLSI 1032 Functional Block Diagram
~~~~

~~~~

~~~~

~~~~

~~~ro

~~~~

~M~~

~~~~

Generic

Logic Blocks
(GLBs)
IN5
IN4

I

1100
~1

1102
~3

110.
~5
~6

1107
1108
I/O_
110 10
~11

110 12

!I

il
:

l
:

~I

Global
Routing
Pool
(GRP)

0

~

~I

..s

I

~13

110 ,.
~16

'SCLK/lN 3

I/O 110 110 110
16 17 18 19

~

110 I/O I/O
20 21 22 23

VO 110 110
24 25 26 27

~

11047
I/O~

1/045
11044

1/043
11042
1/041

11040
11039
1/038
V037
1/036

V035
V034
V033
V032

I/O VO 110 ~
28 29 30 31
0139(1)-32-i@

"ISP Control Functions for ispLSI 1032 Only

The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
1/0 pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 rnA.
Eight GlBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GlBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The plSI and isplSI 1032 devices
contain four of these Megablocks.

The GRP has as its inputs the outputs from all ofthe GLBs
and all of the inputs from the bi-directionall/O cells. All of
these signals are made available to the inputs of the
GlBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the plSI and ispLSI 1032 devices are selected
using the Clock Distribution Network. Four dedicated
clock pins (YO, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (ClK 0, ClK
1, ClK 2, 10ClK 0 and 10ClK 1) are provided to route
clocks to the GlBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GlB (CO
on the plSI and isplSI1032 devices). The logic of this
GlB allows the user to create an internal clock from a
combination of internal signals within the device.

2-98

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Absolute Maximum Ratings 1
Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ............... -2.5 to Vee +1.0V

,

Off-State Output Voltage Applied ......-2.5 to Vee + 1.0V
Storage Temperature ..................-65 to 150°C
Case Temp. with Power Applied ........-55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions
SYMBOL

PARAMETER

Supply Voltage

VCC

MIN.

MAX.

Commercial

T.= o·C to +70·C

4.75

5.25

Industrial

TA = -40·C to +85·C

4.5

5.5

Military/883

Te = -55·C to +125·C

4.5

5.5

VIL

Input Low Voltage

0

0.8

VIH

Input High Voltage

2.0

Vcc+ 1

UNITS

V

V
V
Table 2· OOO5Alap wlmll.ep&

Capacitance (T A=25°C, f=1.0 MHz)
SYMBOL

C1
Ca

PARAMETER
Dedicated Input Capacitance

II Commerciallindustrial
Military

1/0 and Clock Capacitance

MAXIMUMl

UNITS

TEST CONDITIONS

8

pI

Vee=5.0V, V'N=2.0V

10

pI

Vee=5.0V, V'N=2.0V

10

pI

Vce=5.0V, V,to' Vy =2.0V
Table 2· 0006

1. Guaranteed but not 100% tested.

Data Retention Specifications
PARAMETER

MINIMUM

MAXIMUM

UNITS

Data Retention

20

-

YEARS

1000
100

-

CYCLES

ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles

CYCLES
Table 2.()O()8A-isp

2-99

1994 Data Book

--

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Switching Test Conditions
Input Pulse Levels

Figure 2. Test Load

GNDt03.OV

Input Rise and Fall Time

S 3ns 10% to 90%

Input Timing Reference Levels

1.SV

Output Timing Reference Levels

1.SV

+5V

See figure 2

Output Load

Device
Test
Output - - - - -.......- -.....- - - - 1.. Point

3-state levels are measured O.SV from steady-state
active level.

Output Load Conditions (s.. figure 2)
*CL includes Test Fixture and Probe Capacitance.
Teat Condition

R1

R2

CL

4700

3900

3SpF

Active High

00

3900

3SpF

Active Low

4700

3900

3SpF

00

3900

SpF

4700

3900

SpF

A

B

C

Active High to Z
atVOH-O.SV
Active Low to Z
at VOl. + O.SV

DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL

MIN.

TYP.3

MAX.

1000=BmA

-

0.4

V

Output High Voltage

IOH =-4 mA

2.4

-

-

V

-10
-lS0

IlA
IlA
IlA

-lS0

IIA

-200

mA

130

190

mA

13S

220

mA

PARAMETER

VOL

Output Low Voltage

VOH

CONDITION

ilL

Input or VO Low Leakage Current

OV S Y'N S V'L (MAX.)

-

IIH

Input or 1/0 High Leakage Current

3.SV S Y'N S Vee

-

IIL-Isp

isp Input Low Leakage Current
VO Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current

OV S Y'N S V'L (MAX.)

-

IIL-PU
10Sl
Icc2

-

OV SV,N S V'L
Vee = SV, VOUT= O.SV
V'L = O.SV, V,H = 3.OV
fTOGGLE = 1 MHz

I Commercial
I

Industrial

-60

-

-

10

UNITS

1. One output at a time for a maximum duration of one second.
2. Measured using eight 16-bit counters.
3. Typical values are at Vee = SV and TA = 2Soc.
TabJ. 2· 0007A-32-isp

2-100

1994 Data Book

H~Lattice
••••••

Specifications pLSI and ispLSI 1032

••••••
••••••

External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 5 fi
CONDo

-80

-

-

A

1 Data Propagation Delay, 4PT bypass, ORP bypass

tpd2

A

2

Data Propagation Delay, Worst Case Path

-

fmax

A

3

Clock Frequency with Intemal Feedback3

90.9

Clock Frequency with External Feedback(i.uZ~tcoJ

58.8

5

Clock Frequency, Max Toggle4

125

tsu1

-

4
6

GLB Reg. Setup Time before Clock, 4PT bypass

6

tc01

A

7

GLB Reg. Clock to Output Delay, ORP bypass

th1

-

-

8

GLB Reg. Hold Time after Clock, 4 PT bypass

0

-

9

GLB Reg. Setup Time before Clock

9

-

10

-

10

-

fmax (Tog.)

10 GLB Reg. Clock to Output Delay

th2

-

11 GLB Reg. Hold Time after Clock

0

tr1

A

12 Ext. Reset Pin to Output Delay

trw1

-

-

13 Ext. Reset Pulse Duration

10

tsu2
tco2

-60

MIN. MAX. MIN. MAX. MIN. MAX

tpd1

fmax (Ext.)

-

12

17

-

80
50
100

8

15

-

7

0

0

-

15
20

10

-

12

-

MHz
ns

-

13

ns

0

-

ns

13

-

ns

16

ns

-

ns

0

24

ns

24

ns

-

18

-

18

16 Ext. Sync. Clock Pulse Duration, High

4

-

5

-

17 Ext. Sync. Clock Pulse Duration, Low

4
2

9

MHz

ns

15

6.5

-

83

ns

15

18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

MHz

-

-

19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

-

13

14 Input to Output Enable

tsu5

60
38

-

15 Input to Output Disable

th5

ns

10

B

-

ns

25

22.5

C

twl

20

-

-

tdis

-

-

UNITS

17

ten
twh

1.
2.
3.
4.
5.

-90

DESCRIPTION1

5
2
6.5

-

-

6
6
2.5
8.5

-

ns
ns
ns
ns

Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and YO clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit counter using GRP feedback.
!max (Toggle) may be less than l/(lwh + lwl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions Section.

2-101

1994 Data Book

~~~lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1032

Internal Timing Parameters 1

PARAMETER

#2

-90

DESCRIPTION

~o

-80

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

Inputs

-

tiobp

20

1/0 Register Bypass

tiolat

21

1/0 Latch Delay

tosu

22

1/0 Register Setup Time before Clock

4.8

tioh

23

1/0 Register Hold Time after Clock

tioco

24

tior
tdin

1.6
2.4

-

2.0
3.0

-

2.7

ns

4.0

ns

7.3

-

ns

1.3

-

ns
ns

5.5

2.1

-

1.0

-

1/0 Register Clock to Out Delay

-

2.4

-

3.0

-

4.0

25

1/0 Register Reset to Out Delay

-

2.8

-

2.5

-

3.3

ns

26

Dedicated Input Delay

-

3.2

-

4.0

-

5.3

ns

27

GRP Delay, 1 GLB Load

-

1.2

-

1.5

ns

tgrp4

28

2.7

ns

29

GRP Delay, 8 GLB Loads

2.4

-

2.0

tgrp8

3.0

4.0

ns

tgrp12

30

GRP Delay, 12 GLB Loads

-

1.6
3.0

-

3.8

5.0

ns

tgrp16

31

GRP Delay, 16 GLB Loads

-

3.6

-

4.5

6.0

ns

tgrp32

32

GRP Delay, 32 GLB Loads

-

6.4

-

8.0

-

2.0

GRP Delay, 4 GLB Loads

10.6

ns

t4ptbp

33

4 Product Term Bypass Path Delay

-

5.2

-

6.5

-

8.6

ns

t1ptxor

34

1 Product TermIXOR Path Delay

5.7

-

7.0

-

9.3

ns

t20ptxor

35

20 Product TermIXOR Path Delay

-

7.0

-

8.0

10.6

ns

txoradj

36

XOR Adjacent Path DelayS

-

8.2

-

-

9.5

-

12.7

ns

tgbp

37

GLB Register Bypass Delay

-

0.8

-

1.0

-

1.3

ns

tgsu

38

GLB Register Setup Time before Clock

1.2

-

1.0

-

1.3

-

ns

tgh

39

GLB Register Hold Time after Clock

3.6

-

4.5

-

6.0

-

ns

tgco

40

GLB Register Clock to Output Delay

-

1.6

-

2.0

2.7

ns

tgr

41

GLB Register Reset to Output Delay

2.0

3.3

ns

42

GLB Product Term Reset to Register Delay

8.0

-

2.5

tptre

10.0

13.3

ns

tptoe

43

GLB Product Term Output Enable to 1/0 Cell Delay

-

7.8

-

9.0

-

12.0

ns

tptck

44

GLB Product Term Clock Delay

2.8

6.0

3.5

7.5

4.6

9.9

ns

torp

45

ORP Delay

-

2.5

ns

ORP Bypass Delay

0.4

-

0.5

-

3.3

46

-

2.4

torpbp

0.7

ns

GRP
tgrp1

GLB

ORP
1. Intemal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

2-102

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1032

Internal Timing Parameters 1

PARAMETER

#2

-90

DESCRIPTION

-60

-80

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob

47

Output Buffer Delay

toen

48

1/0 Cell OE to Output Enabled

todis

49

1/0 Cell OE to Output Disabled

-

2.4

-

3.0

-

4.0

ns

4.0

-

5.0

-

6.7

ns

4.0

-

5.0

-

6.7

ns

ns

Clocks
tgyO

50

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

3.6

3.6

4.5

4.5

6.0

6.0

tgy1/2

51

Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.8

4.4

3.5

5.5

4.6

7.3

ns

tgcp

52

Clock Delay, Clock GLB to Global GLB Clock Line

0.8

4.0

1.0

5.0

1.3

6.6

ns

tioy2/3

53

Clock Delay, Y2 or Y3 to 1/0 Cell Global Clock Line

2.8

4.4

3.5

5.5

4.6

7.3

ns

tiocp

54

Clock Delay, Clock GLB to 1/0 Cell Global Clock Line

0.8

4.0

1.0

5.0

1.3

6.6

ns

-

8.2

-

9.0

-

12.0

ns

Global Reset
tgr

55

Global Reset to GLB and 1/0 Registers

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

2-103

1994 Data Book

.I

H;Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

pLSI and ispLSI 1032 Timing Model
VO Cell

GRP

GLB

ORP

I/O Cell

-----~ -------------------~
Feedback

Derivations of tsu, th and tco from the Product Term Clock1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)
(#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)

th

Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0ns= (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)

tco

Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max) + (tgco) + (tarp + tab)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)

Derivations of tsu, th and tco from the Clock GLB1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgyO(min) + tgco + tgcp(min)
(#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)

th

Clock (max) + Reg h - Logic
(tgyO(max) + tgco + tgcp(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns= (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)

tco

Clock (max) + Reg co + Output
= (tgyO(max) + tgco + tgcp(max) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)

1. Calculations are based upon timing specs for the pLSI and ispLSI 1032-80.

2-104

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Figure 3. Typical Device Power Consumption vs fmax

250

;;(

S
~

200
150
100
50

o

10

20

30

40

50

60

70

80

fmax (MHz)
Notes: Configuration of eight 16-bit Counters
Typical Current at SV, 2S'C

ICC can be estimated for the pLSI and ispLSI 1032 using the following equation:
ICC =52 + (# of PTs • 0.30) + (# of nets' Max. freq • 0.009) where:
# of PTs =Number of Product Terms used in design
# of nets =Number of Signals used in device
Max. freq

=Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127A-32-SD-isp

Figure 4. Maximum GRP Delay vs GLB Loads

pLSI and ispLSI 1032-60

6

pLSI and ispLSI 1032-80
pLSlandispLSl1032-90

O~

__

~

______

4

~

______

8
GLB Loads

~

12

____

~

16
0126A-B0-32-isp

2-105

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1032

••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions of the Lattice High-Density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip, programming
can be accomplished by simply shifting data into the
device. Once the function is programmed, the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TTL level
logic interface signals. These five signals are fed into the
on-chip programming circuitry where a state machine
controls the programming. The interface signals are isp
Enable (ispEN), Serial Data In (SOl), Serial Data Out
(SDO), Serial Clock (SCLK) and Mode (MODE) control.
Figure 5 illustrates the block diagram of one possible
scheme for programming the ispLSI devices. For details
on the operation of the internal state machine and programming of the device please refer to the in-system
programming section in this Data Book.

Figure 5. ISP Programming Interface
SOO
SOl
MODE
SCLK
ispEN

-

}

5-wire ISP

Programming
Interface

~

ispLSI
~

-

-

~

ispGAL

-

'---

r---

~

ill
ispGDS

~

ispLSI

il

0294B

2-106

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 1032

••••••
••••••

ISP Programming Voltage/Timing Specifications1
SYMBOL

PARAMETER

VCCP

Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

VllP

Input Voltage low

liP

Input Current

VOHP

Output Voltage High

CONDITION

ispEN= low

IOH = -3.2 rnA

MIN.

TYP.

MAX.

4.75

5

5.25

V

-

50

100

mA

Veep

V

0.8

V

200

~A

Vccp

V

0

-

-

100

2.0

2.4

-

UNITS

VOlP

Output Voltage low

tr. tf

Input Rise and Fall

tispen

ispEN to Output 3-State Enabled

-

2

10

~

tispdis

ispEN to Output 3-State Disabled

-

2

10

~

tsu

Setup Time

0.1

0.5

tco

Clock to Output

0.1

0.5

-

th

Hold Time

0.1

0.5

-

~

tclkh. tclkl

Clock Pulse Width. High and low

0.5

1

-

~

30

-

IOl=5mA

0

tpwv

Verify Pulse Width

20

tpwp

Programming Pulse Width

40

tbew

Bulk Erase Pulse Width

trst

Reset Time From Valid Veep

200
45

1. ISP Programming is guaranteed forTA = O'C to 70'C Operation only,

2-107

-

0.5

V

0.1

~

100

-

~s

~s

~

ms
ms
~s
Table 2- 0029 tep·c

1994 Data Book

•

~~~Lattice
••••••

Specifications pLSI and ispLSI 1032

••••••
••••••

Rgure 6. Timing Waveforms for In-Systam Programming (lspLSI1032)

Output ,~~~~~~t-~~----------------------------+8~~~~
Unu~

MODE _ _ _-+--'

SCLK _ _ _-+-_-'

0181B

z:z
~

Don't Care
Undefined State

Figure 7. Program, Verify & Bulk Erase Waveforms (ispLSI1032)

,-------.1

Execute State (Program, Verify or Bulk Erase Instruction)

MODE

tpwp,
SOl

14--- til --~,,-__+------'"

"

~~~tc~lkh~~
SCLK

thew. or tpwv

_ _--J

tsu

' . . . _--J/

Ftclkl~
/

2-108

,~--

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Figure 8 illustrates the address and data shift register bits
for the ispLSI 1032. For a detailed explanation refer to

the Device Layout discussion in the pLSI and ispLSI
Architectural Description section of this Data Book.

Figure 8. ispLSI1032 Shift Register Layout
D

D
A
T
A

A
T

A

High Order Shift Register
Low Order Shift Register

SOO
SOl
107

E2CMOS Cell Array

6

soo

Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic "0" disables it.

2-109

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 1032

••••••
••••••

Pin Description

Name

PLCC Pin Numbers

1/00-1/03
1/04-1/07
1/08-1/011
1/012 -1/015
1/016 -1/019
110 20 - 110 23
110 24 - 110 27
110 28 - 110 31
110 32 - 110 35
110 36 - 110 39
110 40 - 110 43
110 44 - 1/047
110 48 - 1/051
110 52 - 110 55
110 56 - 110 59
110 60 - 110 63

26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,

27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,

28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,

IN4-IN7

67,

84,

2,

ispEN*/NC

23

°

25

SDI'/IN

29,

33,

Description
Input/Output Pins - These are the general purpose 110 pins used by the
logic array.

37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
19

Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input - This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN also is used as
one of the two control pins for the isp state machine.
Input- This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output - This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.

°

MODE'/IN 1

42

SDO'/IN 2

44

SCLK'/IN 3

61

Input - This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.

RESET

24

YO

20

Active Low (0) Reset pin which resets all of the GLB and 110 registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.

Yl

66

Y2

63

Y3

62

GND

1,
21,

Vce

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB andlor
any 110 cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any 110 cell on the
device.
22,
65

43,

64

Ground (GND)
Vee

, For ispLSI 1032 Only

Table 2-0002A-32-isp

2-110

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Pin Description
Name

Description

TQFP Pin Numbers

1/00-1/03
1/04-1/07
1/08-1/011
1/012 -1/015
1/016-1/019
1/020 -1/0 23
1/024 -I/O 27
1/028 - 1/0 31
1/0 32 - 1/0 35
1/0 36 - 1/0 39
1/0 40 - 1/0 43
1/044-1/047
1/0 48 - 1/0 51
I/O 52 -1/0 55
1/0 56 - 1/0 59
1/0 60 - 1/0 63
IN4-IN 7

17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,

18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,

19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,

20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9

InpuVOutput Pins - These are the general purpose 1/0 pins used by the
logic array.

66,

87,

89,

10

Dedicated input pins to the device.

ispEN'/NC

14

SDI'/IN 0

16

MODE'/IN 1

37

SDO'/IN 2

39

SCLK'/IN 3

60

NC

Input - Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SOl,
SDO and SCLK options become active.
Input- This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input - This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
InpuVOutJ;1ut - This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.

1,

2,

24,

25,

26,
51,
76,

27,
52,
77,

49,
74,
99,

50,
75
100

RESET

15

YO

11

Y1

65

Y2

62

Y3

61

GND
VCC

13,
12,

Input - This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
These pins are not used.

Active Low (0) Reset pin which resets all of the GLB and 1/0 registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB andlor
any 1/0 cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any 1/0 cell on the
device.
38,
64

63,

88

Ground (GND)

Vee
Table 2- 0002B-32-isp

, For ispLSI 1032 Only

2-111

1994 Data Book

H~Lattice
......
••••••

Specifications pLSI and ispLSI 1032

••••••

Pin Description

Name

CPGA Pin Numbers
F1,
K1,

H1,'
J2,

K3,
L4,

J5,

1/00-1103
1104-1/07
1108-1/011
11012 -11015
11016-11019
11020-11023
I/O 24 -11027
11028-11031
I/O 32 -11035
I/O 36-11039
11040-11043
1/044-11047
1/048-110,51
1/052 -110 55
1/056-11059
1/060-11063

L11,
J11,
E9,
B11,
B9,
AB,
AS,
84,
A1,
C1,

IN4-IN7

E10, C7,

IspEN"/NC

G3

SOI"/INO

G2

MODE"/IN 1

K6

SDO"IIN2

J7

SCLK"IIN3

G10

RESET

G1

YO

E1

Y1

E11

Y2

G9

Y3

G11

NC

G3

GND

C6,
F2,

Vee

L7,

KB,

L2,
K7,
LS,
K10,
H10,
011,
C10,
A10,

88,
B5,
A3,
B2,
02,

H2,
L1,
L3,
K5,

J1,

K2,

Input/Output Pins - These are the general purpose 110 pins used by the
logic array.

K4,
L5,

LB,

LB,

L10,
J10,
H11,
010,
A11,
A9,
B7,
C5,
A2,
C2,
01,

KS,
K11,
F10,
C11,
B10,

M,

Description

88,
A7,

M,
B3,
B1,
E3

E2

Dedicated input pins to the deVice.
Input - Dedicated In-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SOl,
SDO and SCLK options become active.
~ This pin performs two functions. It Isa dedicated Input pin when
sp
Is logic high. When ~ is logic low, It functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
InpE~- This pin performs two functions. It Is a dedicated input pin when
sp
Is logic high. When ~ is logic low, It functions as a pin to
control the operation of the Isp state machine.
Inpul/Outp!:!!="This pin performs two functions. It is a dedicated input
pin when IspEN Is logic high. When IspEN Is logic low, it functions as
en output pin to read serial shift register data.
~- This pin performs two functions. It is a dedicated input when
isp N is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and 1/0 registers
in the deVice.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock Input. This clock input is brought into the clock
distribution networK, end can optionally be routed to any GLB on the
deVice.
Dedicated Clock input. This clock input is brought into the clock
distribution networK, and can optionally be routed to any GLB and/or
any I/O calion the device.
Dedicated Clock Input. This clock Input is brought into the clock
distribution networK, and can optionally be routed to any 110 cell on the
device.
This pin should be left floating or tied to Vee
This pin should never be tied to GND,
'

F3,
F11

F9,

J6

Ground (GND)

Vee
Table2.()()02-321883

2-112

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI 1032 84-Pin PLCC Pinout Diagram

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

1/057

74

1/038

1/058
1/059

73
72

1/037
1/036

1/060

71

1/035

1/061

70

1/034

1/062

69

1/033

1/063

68

1/032

IN7

67

IN4

66

Y1

65

vcc

YO
VCC
GND
"ispEN/NC

pLSI1032
and
ispLSI1032

64

GND

63

Y2
Y3

RESET

62

"SDI/IN 0

61

IN 3/SCLK"

1/00
1/01

60
59

1/031
1/030

1/02

58

1/029

1/03

57

1/028

1/04

56

1/027

1/05

55

1/06

54

1/026
1/025

"Pins have dual function capability for ispLSI 1032 only (except pin 23, which is ispEN only).
0123-32-isp

2-113

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Pin Configuration
pLSI and ispLS11032100-pin TQFP Pinout Diagram

NC
NC
1/057
1/058
1/059
1/060
1/061
1/062
1/063

IN7
YO
VCC
GNO
*ispEN/NC
RESET
*SOI/IN 0
1/00
1/01
1/02
1/03
1/04
1/05
1/06

NC
NC

8~~~~~~~~m~~~~~~~~~oo~~~~~
1~

2
3
4
5

~

~

NC
NC
1/038
1/037

6

n
n
ro

7

W

8
9

~
~

1/035
1/034
1/033
1/032

~~

Y1

64
63

VCC
GNO

~~

Y2

~~
12
13

~~

pLSI1 032
and
ispLSI1 032

16
17
18

60
59
58

19

57

~

~

21

55

~
~
~
~

~
~
~
~

re~rereg~~~~~~~~~~~~~~~~~~~g

I/O 36

IN4

Y3

IN 3/SCLK*
1/031
1/030
1/029
1/028
1/027
1/026
1/025

NC
NC

*Pins have dual function capability for ispLSI1032 only (except pin 14, which is ispEN only).
0766A·32·isp

2-114

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1032

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI 1032/883 84-Pin CPGA Pinout Diagram
11

10

9

8

7

6

5

4

8 8 8 8 8 88 8
8 888888 8
88
Ge8
88
888
888
8 ~8
pLSI 10321883

and

ispLS110321883
BOTTOM VIEW

IN3

3

2

PINA1

1

888
888
.88
88
888
888
@ @S
INC

IN2

IN1

B

c
0

E

F

G

INO

88
@ 88
88
88
88888 @ 88888
88888888888
8 8

A

H

J

K

L

'Pins have dual function capability for ispLSI 1032/883 only (except pin 63, which is ispEN only).

2-115

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 1032

••••••
••••••

Part Number Description
(is)plSI
Device Family--=-----'

T

1032 - XX

x

X

X

L

Device Number - - - - - - - - '

Speed - - - - - - - - - - - - - '
90 90 MHz fmax
80 80 MHz fmax
60 60 MHz fmax

=
=
=

=

Blank Commercial
I Industrial
Grade
/883 - 883 Military Process

=

Package
J=PLCC
T=TQFP
G=CPGA

~-----Pow.

L=Low

00212-8OB-iep1032

pLSI and ispLSI 1032 Ordering Information
COMMERCIAL
Family

pLSI

IspLSI

fmax(MHz) tpd (ns)

Ordering Number

Package

90

12

pLSI1032-90W

84-PIn PLCC

90

12

pLSI1032-90LT

1OO-Pin TQFP

80

15

pLSI1032-80W

84-PinPLCC

pLSI 1032-80lT

100-Pln TQFP

80

15

60

20

pLSI1032-80W

84-Pin PLCC

60

20

pLSI 1032-8OlT

1OO-Pin TQFP

90

12

ispLSI1032-00w

84-Pin PLCC

90

12

ispLSll 032-9OlT

1OO-Pin TQFP

80

15

ispLSI 1032-SOW

84-Pin PLCC

80

15

ispLSI1032-80LT

100-Pin TQFP

80

20

ispLSI1032-80W

84-PinPLCC

80

20

ispLSI1032-80LT

100-Pin TQFP

INDUSTRIAL
Family

fmax(MHz) tpd (ns)

Ordering Number

Package

pLSI

60

20

pLSI1032-80WI

84-PinPLCC

IspLSI

60

20

ispLSI1032-80LJI

84-Pin PLCC

MIUTARY1883
Family

fmax(MHz) tpd (n8)

Ordering Number

SMDNumber

Package

pLSI

60

20

pLSI 1032-6OlGl863

5962-9466801MXC

84-PInCPGA

IspLSI

60

20

ispLSI 1032-80LG/863

5962-9308501 MXC

84-PinCPGA

2-116

1994 Data Book

~~~Lattice

pLSI® and ispLSf 1048
M

••••••
••••••
••••••

Features
• PROGRAMMABLE AND IN-SYSTEM PROGRAMMABLE
HIGH DENSITY LOGIC
- High-Speed Global Interconnects
- 8000 PLD Gates
- 96 110 Pins, Ten Dedicated Inputs
- 288 Registers
- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- fmax = 80 MHz Maximum Operating Frequency
- fmax = 50 MHz for Industrial Devices
- tpd = 15 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Eraseable and Reprogrammable
- Non-Volatile E2CMOS Technology
- 100% Tested
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
- In-System Programmable 5-Volt Only
- Change Logic and Interconnects "On-the-Fly" in
Seconds
- Reprogram Soldered Device for Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
- Four Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global
Interconnectivity
• pLSl/ispLSI DEVELOPMENT SYSTEM (pDS"')
pDS Software
- Easy to Use PC Windows™ Interface
- Boolean Logic Compiler
- Manual Partitioning
- Automatic Place and Route
- Static Timing Table
pDS+TM Software
- Industry Standard, Third Party Design
Environments
- Schematic Capture, State Machine, HDL
- Automatic Partitioning and Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workstation Platforms

High-Density Programmable Logic
Functional Block Diagram
1IlIIIIIIIII1IlIIIIIIIII1IlIIIIIIIII1IlIIIIIIIII.IIlIIIIIIIIIIIlIIIIIIIIIIIlIIIIIIIIIIIlIIIIIIIIIB

Ill!

I ~
Ilg.IiiJ
~
I ,,~
1M]
~

g.~

§]§1~
FsliF2liFlliFoi

Er '" -Logic

Global Routing Pool (GRP)

Id~

III IiiJ ~~~~~~o~~

Ill!

I Outeut Routina Pool I
~~~~§]~~~

Array

III

I
"
@§]
~I
~.
EI
~"
EI ' fOOi
I
./~g.
EI ,/ @TIdl
~

~

GLB

~~u~~~~o~~ ~
eLK

BIIlIIIIIIIIIIIlIIIIIIIIIIIlIIIIIIIIIIIlIIIIIIIII.1IlIIIIIIIII1IlIIIIIIIII1IlIIIIIIIII1IlIIIIIIIII

Description
The Lattice pLSI and ispLSI 1048 are High-Density
Programmable Logic Devices which contain 288 Registers, 96 Universal 110 pins, ten Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI1 048 features
5-Volt in-system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1048 device, but multiplexes four of the dedicated input
pins to control in-system programming.
The basic unit of logiC on the pLSI and ispLSI 1048
devices is the Generic LogiC Block (GLB). The GLBs are
labeled AO, A1 .. F7 (see figure 1). There are a total of 48
GLBs in the pLSI and ispLSI 1048 devices. Each GLB
has 18 inputs, a programmable AND/ORIXOR array, and
four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.

CopyrIght © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The speCifications and infonnation herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

2-117

1994 Data Book

I

~~~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

Functional Block Diagram
Figure 1. pLSI and IspLSI1048 Functional Block Diagram

oo~oooo

00000000

00000000

00000000

00000000

~~~~

~M~~

g~M~

~~~~

~~n.

00000000

RNn.

00000000
"ro~~

oo~oooo
.~~M

IN7
IN6

00'
005
00.

1/07
008

I/O.

il ~
,

,,

0012
0013

:1

~15

'SOl/INO
"MOD(;JIN1

-"

~I

I
In utBus

•. . .NINC

~I

Global
Routing
Pool
(GRP)

:I~

,,

0010
0011

~14

I

:1

000
001
00'
003

If06S

0062

"'''

If080

0059
0056

0057
0056

00 ..
0054
1/063
0052
1/051

0050
0049

11048

In utBus

III

.....---~=~=~~=:::-':::~,,-::~:-::OO~,/O::-:OO=-OO=I/O,,-::OO:--~,N=SC~LK"~/OO~,:::'/O':::OO,,-::~:--::,/O::":,/O~I/O=-~:::-':::I/O"-::"':-::VO~oo::-:OO=-OO=I/O,,-::,/O:----::-::-::-::-----I
242526V

28293031

4

IN5

32333435

36373839

40414243

44454647

0139F(1)·48-lsp

"ISP Control Functions for ispLSI 1048 Only

The devices also have 96 1/0 cells, each of which is
directly connected to an 1/0 pin. Each 1/0 cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mAo
Eight GLBs, 16 1/0 cells, two dedicated inputs (one
dedicated input in Megablock B and E) and one ORP are
connected together to make a Megablock (see figure 1).
The outputs of the eight GLBs are connected to a set of
16 universal 1/0 cells by the ORP. The pLSI and ispLSI
1048 devices contain six of these Megablocks.

The GRP has as its inputs the outputs from all ofthe GLBs
and all of the inputs from the bi-directionall/O cells. All of
these Signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the pLSI and ispLSI1 048 devices are selected
using the Clock Distribution Network. Four dedicated
clockpins (YO, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (CLK 0, CLK
1, CLK 2, 10CLK 0 and 10CLK 1) are provided to route
clocks to the GLBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GLB (DO
on the pLSI and ispLSI 1048 devices). The logic of this
GLB allows the user to create an internal clock from a
combination of internal signals within the device.

2-118

1994 Data Book

~HLattice
......
......
......
Absolute Maximum Ratings

Specifications pLSI and ispLSI 1048
1

Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ............... -2.5 to Vee +1.0V
Off-State Output Voltage Applied ......-2.5 to Vee +1.0V
Storage Temperature .................. -65 to 150°C
Case Temp. with Power Applied ........-55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN.

MAX.

Commercial

TA= O°C to +70°C

4.75

5.25

Industrial

TA = -40°C to +85°C

4.5

5.5

UNITS
V

VIL

Input Low Voltage

0

0.8

V

VIH

Input High Voltage

2.0

Vcc + 1

V

Capacitance (T A=25°C, f=1.0 MHz)
MAXIMUMl

UNITS

TEST CONDITIONS

Dedicated Input Capacitance

8

pf

Vcc=5.0V, V'N=2.0V

I/O and Clock Capacitance

10

pf

Vcc=5.0V, V,to, Vy=2.0V

SYMBOL

PARAMETER

C1
C.

1. Guaranteed but not 100% tested.

Data Retention Specifications
PARAMETER
Data Retention
ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles

MINIMUM

MAXIMUM

UNITS

20

-

YEARS

1000

-

CYCLES

100

-

CYCLES
Table 2·0008A-isp.eps

2-119

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1048

••••••

Switching Test Conditions
Input Pulse Levels

Figure 2. Test Load

GNDt03.0V
:!: 3ns 10% to 90%

Input Rise and Fall Time
Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

+5V

See figure 2

Output Load

Device _ _ _ _ _...._ _~._--~ Test
Output
Point

3-state levels are measured 0.5V from steady-state
active level.
TQle2- 0003

Output Load Conditions (see figure 2)
Test Condition

Rt

C

CL

470n

390n

35pF

Active High

00

390n

35pF

Active Low

470n

390n

35pF

00

390n

5pF

470n

390n

5pF

A

B

R2

Active High to Z
at VOH - 0.5V
Active Low to Z
at VOl. + 0.5V

*CL Includes Test Fixture and Probe Capacitance.

DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL

PARAMETER

CONDITION

MIN.

TYP.3

MAX.

-

-

0.4

V

-

V

-10

IJ.A

10

IJ.A

-150

IJ.A

-

-150
-200

IJ.A
mA

165

235

rnA

165

260

rnA

VOL

Output Low Voltage

IOL=8 rnA

VOH

Output High Voltage

IOH =-4 mA
OV:!: Y'N :!: V,L (MAX.)
3.5V:!: V,N :!: Vee

2.4

-

-60

ilL

Input or VO Low Leakage Current

IIH

Input or 1/0 High Leakage Current

IIL-isp

isp Input Low Leakage Current

IIL-PU

VO Active Pull-Up Current

OV :!: Y'N :!: V,L (MAX.)
OV:!: V,N :!: V,L

los1

Output Short Circuit Current

Vee = 5V, VOUT= 0.5V

Icc2

Operating Power Supply Current

-

V,L = 0.5V, V,H = 3.0V

I Commercial

fTOGGLE = 1 MHz

I Industrial

-

-

-

UNITS

1. One output at a time for a maximum duration of one second. V... = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at Vee = 5V and T.. = 25°C.
Table 2· 0007A-48-lop

2-120

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

External Timing Parameters
Over Recommended Operating Conditions

PARAMETER TESTs #2
CONDo

-70

-50

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

tpd1

A

1

Data Propagation Delay, 4PT bypass, ORP bypass

-

15

tpd2

A

2

Data Propagation Delay, Worst Case Path

-

20

fmax

A

3

Clock Frequency with Internal Feedback3

80

fmax (Ext.)

4

Clock Frequency with External FeedbaCk(tsu2: tco~

50

5

Clock Frequency, Max Toggle4

100

tsu1

-

6

GLB Reg. Setup Time before Clock, 4PT bypass

tc01

A

7

th1
tsu2

-

tc02

-

10 GLB Reg. Clock to Output Delay

th2

-

11 GLB Reg. Hold Time after Clock

fmax (Tog.)

-

23

-

71.4

-

53.6

41.7

7

-

9

-

GLB Reg. Clock to Output Delay, ORP bypass

-

10

-

8

GLB Reg. Hold Time after Clock, 4 PT bypass

0

-

0

9

GLB Reg. Setup Time before Clock

10

-

-

12

0

-

18

24

ns

30.7

ns
MHz

31.3

-

71.4

-

MHz

12

-

ns

12

-

16

ns

0
16

-

ns

12

-

-

14

-

18.7

ns

0

-

0

-

ns
ns

83

MHz

ns

tr1

A

12 Ext. Reset Pin to Output Delay

-

17

-

17

-

22.7

trw1

-

13 Ext. Reset Pulse Duration

10

-

10

-

13

-

ns

ten

B

14 Input to Output Enable

-

18

20

ns

C

15 Input to Output Disable

-

18

20

-

26.7

tdis

-

26.7

ns

twh

-

16 Ext. Sync. Clock Pulse Duration, High

5

-

6

-

7

ns

17 Ext. Sync. Clock Pulse Duration, Low

5

6

2

-

7

18 1/0 Reg. Setup Time before Ext. Sync. Clock (V2, V3)

-

-

2.7

-

ns

8.7

-

ns

twl
tsu5
th5
1.
2.
3.
4.
5.

-80

DESCRIPTION1

19 1/0 Reg. Hold Time after Ext. Sync. Clock (V2, V3)

6.5

2
6.5

ns

Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock.
Refer to Timing Model in this data sheet for further details.
Standard 16·Bitloadable counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions Section.
Table 2· 0030A·481BO,70,50

2-121

1994 Data Book

~~~Lattice

••••••
••••••

Specifications pLSI and ispLSI 1048

••••••
Internal Timing Parameters 1

PARAMETER

#2

-80

DESCRIPTION

-70

-50

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.
Inputs

-

2.5

-

3.0

-

4.0

-

3.3

-

4.0

-

5.3

ns

1/0 Register Setup Time before Clock

5.3

-

6.0

-

8.1

-

ns

1/0 Register Hold Time after Clock

1.5

-

0.5

-

0.9

-

ns

3.0

3.9

ns

4.6

ns

6.0

-

8.0

ns

tiobp

20

tiolat

21

110 Register Bypass
110 Latch Delay

tiosu

22

tioh

23

ns

tioco

24

1/0 Register Clock to Out Delay

-

2.5

tior

25

1/0 Register Reset to Out Delay

-

2.9

-

tdin

26

Dedicated Input Delay

-

5.0

-

27

GRP Delay, 1 GLB Load

-

2.1

-

2.5

-

3.3

ns

2.5

-

3.0

-

4.0

ns

-

5.3

ns

6.7

ns

3.5

GRP
tgrpl
tgrp4

28

GRP Delay, 4 GLB Loads

-

tgrp8

29

GRP Delay, 8 GLB Loads

-

3.3

-

4.0

tgrp12

30

GRP Delay, 12 GLB Loads

-

4.2

5.0

5.0

-

ns

-

16.0

-

8.0

13.3

21.3

ns

tgrp16

31

GRP Delay, 16 GLB Loads

tgrp48

32

GRP Delay, 48 GLB Loads

33

4 Product Term Bypass Path Delay

6.0

GLB
t4ptbp

-

5.4

-

6.5

-

8.6

ns

6.5

-

7.0

-

9.3

ns

-

7.6

-

7.5

-

10.0

ns

8.4

-

9.5

-

12.7

ns

tl ptxor

34

1 Product TermIXOR Path Delay

t20ptxor

35

20 Product Term/XOR Path Delay

txoradj

36

XOR Adjacent Path Delay3

tgbp

37

GLB Register Bypass Delay

0.8

-

1.0

-

1.3

ns

tgsu

38

GLB Register Setup Time before Clock

0.8

-

1.5

-

2.0

-

ns

tgh

39

GLB Register Hold Time after Clock

5.0

-

6.0

-

8.0

-

ns

tgco

40

GLB Register Clock to Output Delay

2.1

-

2.5

ns

41

GLB Register Reset to Output Delay

2.1

-

2.5

-

3.3

tgr

-

3.3

ns

tptre

42

GLB Product Term Reset to Register Delay

-

8.3

10.0

-

13.3

ns

tptoe

43

GLB Product Term Output Enable to 1/0 Cell Delay

tptck

44

GLB Product Term Clock Delay

torp

45

torpbp

46

-

8.8

-

9.0

-

11.9

ns

2.9

6.3

3.5

7.5

4.6

9.9

ns

ORP Delay

-

3.2

-

3.5

-

4.7

ns

ORP Bypass Delay

-

1.3

-

1.5

-

2.0

ns

ORP

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
Table 2· 0036A-4B/BO.70.50.eps

2-122

1994 Data Book

H~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1048

Internal Timing Parameters 1

PARAMETER

#2

-80

DESCRIPTION

-70

-50

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob

47

Output Buffer Delay

-

2.5

-

4.0

ns

48

1/0 Cell OE to Output Enabled

-

4.2

-

3.0

toen

5.0

-

6.7

ns

todis

49

1/0 Cell OE to Output Disabled

-

4.2

-

5.0

-

6.7

ns

tgyO

50

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

4.2

4.2

5.0

5.0

6.7

6.7

ns

tgy1/2

51

Clock Delay, Y1 or Y2 to Global GLB Clock Line

3.3

5.0

4.0

6.0

5.3

8.0

ns

tgcp

52

Clock Delay, Clock GLB to Global GLB Clock Line

0.8

4.2

1.0

5.0

1.3

6.6

ns

tioy2l3

53

Clock Delay, Y2 or Y3 to 1/0 Cell Global Clock Line

3.3

5.0

4.0

6.0

5.3

8.0

ns

tiocp

54

Clock Delay, Clock GLB to 1/0 Cell Global Clock Line

0.8

4.2

1.0

5.0

1.3

6.6

ns

-

9.2

-

8.0

-

10.6

ns

Clocks

Global Reset
tgr

55

Global Reset to GLB and 1/0 Registers

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

2-123

1994 Data Book

H~Lattice
.....•
••••••

Specifications pLSI and ispLSI 1048

••••••

pLSI and ispLSI 1048 Timing Model
110 Cell

GRP

GLB

ORP

110 Cell

-.-----~------------,~~

Derivations of tsu, th and tco from the Product Term Clock1
tsu

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)
(#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5)

th

6.0 ns =
tco

Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
(3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5)
Clock (max) + Reg co + Output

= (tiobp + tgrp4 + tptck(max) + (tgco) + (torp + lob)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0)
Derivations of tsu, th and tco from the Clock GLB 1
tsu

6.5 ns =

Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgyO(min) + tgco + tgcp(min)
(#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
(3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0)

th

Clock (max) + Reg h - Logic
(tgyO(max) + tgco + tgcp(max) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#50+#40+#52)+(#39) - (#20+#28+#35)
5.0 ns= (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)

teo

Clock (max) + Reg co + Output
+ tgcp(max) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)

= (tgyO(max) + tgco

1. Calculations are based upon timing specs for the pLSI and ispLSI 1048-70.

2-124

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

Figure 3. Typical Device Power Consumption vs fmax
250
~ 200
c(

.s 150
()

SJ

100
50

o
fmax (MHz)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at SV, 2S'C

ICC can be estimated for the pLSI and ispLSI 1048 using the following equation:

=

ICC 73 + (# of PTs' 0.23) + (# of nets' Max. freq • 0.010) where:
# of PTs =Number of Product Terms used in design
# of nets =Number of Signals used in device
Max. freq =Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127A-4S··S(Hsp

Figure 4. Maximum GRP Delay vs GLB Loads

8

pLSI and ispLS11048-50

7
6
til

C

pLSI and ispLSI 1048-70

5

pLSI and ispLSI 1048-80

>as 4
Cll

Cl
Q.

CC
(!J

3
2

o~

__

~

______

4

~

______

8

~

____

12

~

16

GLB Loads
0126A·48·80-isp

2-125

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1048

••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions ofthe Lattice High-Density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip, programming
can be accomplished by simply shifting data into the
device. Once the function is programmed, the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TTL level
logic interface signals. These five signals are fed into the
on-chip programming circuitry where a state machine
controls the programming. The interface signals are isp
Enable (ispEN), Serial Data In (SOl), Serial Data Out
(SDO), Serial Clock (SCLK) and Mode (MODE) control.
Figure 5 illustrates the block diagram of one possible
scheme for programming the ispLSI devices. For details
on the operation of the internal state machine and programming of the device please refer to the in-system
programming section in this Data Book.

Figure 5. ISP Programming Interface

SOD
SOl
MODE
SCLK
ispEN

-----+

}

5-wlre ISP
Programming
Interface

ispLSI

-:----

ispGAL

ill

- '-' - - ispGDS

ispLSI

~
02948

2-126

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

SYMBOL

PARAMETER

VCCP

Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

CONDITION

ispEN = low

MIN.

TYP.

MAX.

4.75

5

5.25

V

-

50

100

rnA

2.0

-

Veep

V

-

0.8

V

100

200

I1A

Veep

V

VllP

Input Voltage low

0

liP

Input Current

-

VOHP

Output Voltage High

VOlP

Output Voltage low

tr tf

Input Rise and Fall

IOH= -3.2 rnA
10l=5 rnA

2.4
0

-

UNITS

0.5

V

-

-

0.1

I1S

tispen

ispEN to Output 3-State Enabled

-

2

10

ispEN to Output 3-State Disabled

-

I1 s

tispdis

2

10

I1 s

tsu

Setup Time

0.1

0.5

-

I1 s

tco

Clock to Output

0.1

0.5

-

Hold Time

0.1

0.5

tclkh. tclkl

Clock Pulse Width. High and low

0.5

1

tpwv

Verify Pulse Width

20

30

-

I1 S

th

tpwp

Programming Pulse Width

40

tbew

Bulk Erase Pulse Width

200

-

trst

Reset Time From Valid Veep

45

-

1. ISP Programming IS guaranteed for TA - O'C to 70'C Operation only.

2-127

I1 s
I1 S
I1 S

100

ms

-

ms

I1 S
Table 2- 0029 iSl>C

1994 Data Book

•

~~~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

Figure 6. Timing Waveforms tor In-system Programming (ispLSI1048)

VCC

I'

/I
--'-I trst

Un~
Input "~~22~~~~~22~~22~~22~22~~22~~~+8~~
Un~
Output "~~22~~~t-~~----------------------------18~~~~

MODE _____--+_

SCLK _ _ _-+_--'

~ Don'tCare
~ Undefined State

Figure 7. Program, Verify & Bulk Erase Waveforms (lspLSI1048)
Execute State (Program, Verify or Bulk Erase Instruction)
MODE

tpwp, thew. or tpwv
SOl

1 + - - til ---~"-.....f----_--J

1+-i~::.Jtc~lkh~~
SCLK

----'

"

tsu

Ftclkl~/.

' _......

2-128

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048

••••••
••••••
••••••

Figure 8 illustrates the address and data shift register bits
for the ispLSI 1048. For a detailed explanation refer to

the Device Layout discussion in the pLSI and ispLSI
Architectural Description section of this Data Book.

Figure 8. ispLSI1048 Shift Register Layout
D

D

A
T

A

A

A

T

Oataln~r2_3_9_
...______
H~i9~h_O~r_d_e_r~S_h_ift__
R~eg~i_st_e_r________~
(SOl)

479...

SOO

Low Order Shift Register

~----------------------~~----------~

SOl
119

E2CMOS Cell Array

SOO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic "0" disables it.

2-129

1994 Data Book

H~lattice
......

Specifications pLSI and ispLSI 1048

••••••
••••••

Pin Description
Name
1/00-1/05
1/06-1/011
1/012 - 1/0 17
1/018 -1/0 23
110 24 - 1/0 29
1/0 30 - 1/0 35
1/036 -1/0 41
1/042 - 1/047
1/0 48 - 1/0 53
1/0 54 - 1/0 59
1/0 60 - 1/0 65
1/0 66 - 1/0 71
1/0 72 - 1/0 77
1/0 78 - 1/0 83
1/0 84 - 1/0 89
1/0 90 - 1/0 95
IN4
IN6-IN 11

PQFP Pin Numbers
20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43,
49, 50, 51, 52, 53, 54,
55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66,
67, 68, 69, 70, 71, 72,
80, 81, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91,
92, 93, 94, 95, 96, 97,
98, 99,100,101,102,103,
109,110,111,112,113,114,
115,116,117,118,119,120,

1,

2,

3,

7,

8,

9, 10, 11, 12

48,
79,104,105, -

ispEN'/NC

17

SDI'/IN 0

19

MODE-liN 1

44

SDO-/IN 3

47

SCLK-/IN 5

73

RESET

18

YO

14

Y1

78

Y2

75

Y3

74

GND
VCC

4

5,

Description
InpuVOutput Pins -These are the general purpose 1/0 pins used by the
logic array.

6,
Dedicated input pins to the device. (IN 2 and IN 9 not available)

108, 13

46, 76,106, 16
15, 45, 77, 107

Input - Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input- This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input - This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
InpuVOutput - This pin performs two functions. It is a dedicated input
pin when IspEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input - This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and 1/0 registers
in the device.
Dedicated Clock input This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB andlor
any 1/0 cell on the device.
Dedicated clock input This clock input is brought into the clock
distribution network, and can optionally be routed to any 1/0 cell on the
device.
Ground (GND)

Vee

'For ispLSI 1048 Only

Table 2- 0002C-48-isp

2-130

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1048

Pin Configuration
pLSI and ispLS11048120-Pin PQFP Pinout Diagram

1/084
1/085
1/086
1/087
1/088
1/089
1/090
1/091
1/092
1/093
1/094
1/095
IN 11
YO

vee
_GNO

'iSP:~~~~

1/058
1/057
1/056
1/055
1/054
11053
1/052
1/051
11050
1/049
1/048
IN6

pLSI1048
and
ispLSI1048

'SOI/INO

1/00
1101
1/02
1/03
1104
1/05
1/06
1/07
1/08
1/09
1/010

Y1

vee
GNO
Y2
Y3

IN 5/SeLK'
1/047
1/046
11045
1/044
11043
11042
1/041
11040
1/039
1/038
11037
1/036

• Pins have dual function capability for ispLSll048 only (except pin 17, which is ispEN only).
0124-4B-ISp

2-131

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 1048

••••••

••••••
••••••

Part Number Description

(is)pLSI
Device Famlly----II

T 1
1048 - XX

X

X

X

T

Device Number - - - - - - - - '
Speed - - - - - - - - - - - - - '
80 = 80 MHz fmax
70 = 70 MHz fmax
50 = 50 MHz fmax

G,.~
Blank = Commercial

I = Industrial
Package
Q=PQFP
' - - - - - - - Power
L=Low

0212-80B-ispl048

pLSI and ispLSI 1048 Ordering Information

COMMERCIAL
fmax(MHz)

tpd (ns)

Ordering Number

Package

80

15

pLS11048-8OLQ

120-Pin PQFP

70

18

pLSI 1048-70LQ

120-Pin PQFP

50

24

pLSI1048-50LQ

120-Pin PQFP

80

15

pLSI 1048-8OLQ

120-Pin PQFP

70

18

ispLSI1048-70LQ

120-Pin PQFP

50

24

ispLSI1048-50LQ

120-Pin PQFP

Family

fmax(MHz)

tpd (ns)

Ordering Number

Package

pLSI

50

24

pLS11048-50LQI

120-Pin PQFP

IspLSI

50

24

ispLSI1048-50LQI

120-Pin PQFP

Family

pLSI

IspLSI

INDUSTRIAL

Table2-0041A-48-iap

2-132

1994 Data Book

~~~Lattice

pLS/@ and ispLSf 1048C
M

High-Density Programmable Logic

••••••
••••••
••••••

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC
- High-Speed Global Interconnects
- 961/0 Pins, 12 Dedicated Inputs, 2 Global Output
Enables
- 288 Registers
- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS· TECHNOLOGY
- fmax 70 MHz Maximum Operating Frequency
- fmax 50 MHz for Industrial Devices
- tpd = 18 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Eraseable and Reprogrammable
- Non-Volatile E2CMOSTechnoiogy
-100% Tested at Time of Manufacture

=
=

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
- In-System Programmable 5-Volt Only
- Change Logic and Interconnects "On-the-Fly" In
Seconds
- Reprogram Soldered Device for Debugging
• COMBINES EASE OF USE AND THE FAST ~vjiPl',,:ia""
SPEED OF PLDs WITH THE DENSITY AM,nClo.c'iII..
IBILITY OF FIELD PROGRAMMABLE
- Complete Programmable
Logic and Structured
- Four Dedicated Clock
- Synchronous and As'vm!tir,[fl
- Flexible Pin
NlVi[ies Global
-Optimized

- Automatic Place and Route
- Static Timing Table
pDS+TM Software
- Industry Standard, Third Party DeSign
Environments
- Schematic Capture, State Machine, HDL
- Automatic Partitioning and Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workstation PlaHorms

ispLSI 1048C are High-Density
Devices containing 288 Registers,
12 Dedicated Input pins, two global
(GOE), four Dedicated Clock Input pins and
Routing Pool (GRP). The GRP provides comD~Hf intF!rr.lln~IAr.tivi'tv between all of these elements. The
11 048C features S-Volt in-system programming and
in-system diagnostic capabilities. It is the first device which
offers non-volatile "on-the-fly" reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems. It is architecturally and parametrically compatible to the pLSI1 048C device, but multiplexes
four of the dedicated input pins to control in-system programming. Compared to the pLSI and ispLSI 1048, the
pLSI and ispLSI 1048C offers two additional dedicated
inputs and two new global output enable pins.

d'll'OIllr~:nnla1i~....o'glc
Ln\iv~s~.trO pins,

The basic unit of logic on the pLSI and ispLSI 1048C
devices is the Generic Logic Block (GLB). The GLBs are
labeled AO, A 1 .. F7 (see figure 1). There are a total of 48
GLBs in the pLSI and ispLSI 1048C devices. Each GLB
has 18 inputs, a programmable AND/OR/XOR array, and
four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

2-133

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048C

••••••
••••••
••••••

Functional Block Diagram
Figure 1. pLSI and ispLSI1 048C Functional Block Diagram

RESET
GOEO

GCE1

00000000

rororooo

ooooooro

roooooro

~~~~

~~~M

~~MM

~~MOO

00000000

nnnn

00000000

00000000

nN~n

"m~M

00000000
MOOMM

II
II
II
IN7
IN6

,
1/00
1/01
roo
ro,
ro4
ro,
roe
007

il

1/000
11059

I~-

,,
,,,

0012
ro13
ro14
ro15

:1

1/058
1/057
1/056

Global
Routing
Pool
(GRP)

jim

roe
roo
ro1O
ro11

'SDIIINO
"MODEIIN1

0063
11062
I/OM

1/055
1/054
1/053
1/052
ro61
ro50
ro48
0048

,

0139F(2)-188-isp

A"'"",,:ril'\o~""'ombinatorial

input,
or bi-directional
dditionally, all outputs are
activ igh or active low. The signal
'ble voltages and the output drivers
sink 8 rnA.
"nl,...T· ·..nutput

Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The pLSI and
ispLSI1 048C devices contains six of these Megablocks.

The GRP has as its inputs the outputs from all ofthe GLBs
and all of the inputs from the bi-directionall/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the pLSI and ispLSI1 048C devices are selected
using the Clock Distribution Network. Four dedicated
clock pins (YO, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (CLK 0, CLK
1, ClK 2, 10ClK 0 and 10CLK 1) are provided to route
clocks to the GLBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GLB (DO
on the pLSI and isplSI1 048C devices). The logic of this
GLB allows the user to create an internal clock from a
combination of internal signals within the device.

2-134

1994 Data Book

~HLattice
••••••

Specifications pLSI and ispLSI 104BC

••••••
••••••

Absolute Maximum Ratings

1

Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ...............-2.5 to Vee +1.0V
Off-State Output Voltage Applied ......-2.5 to Vee + 1.0V
Storage Temperature ..................-65 to 150°C
Case Temp. with Power Applied ........ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage toJIfIti:levice. Functional
operation of the device at these or at any other conditions above those indicated in the operational
this specification
is not implied (while programming. follow the programming specifications).

PARAMETER

UNITS

Vee

Supply Voltage

v

VIL

Input Low Voltage

v

VIH

Input High Voltage

V

SYMBOL

2-135

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 104BC

••••••
••••••
••••••

Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time

S 3ns 10% to 90%

Input Timing Reference Levels

1.SV

Output Timing Reference Levels

1.SV

Output Load

Figure 2. Test Load

GNDt03.OV

+SV

See figure 2

3-state levels are measured O.SV from steady-state
active level.

Device
Output

Test

-----+---.....- -.... Point

Output Load Conditions (see figure 2)

1. One output at a time for a maximum duration of one second. V.... = O.SV was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2. Measured using twelve 16-blt counters.
Tablo 2- 0007A-4S-isp
3. Typical values are at Vcc = SV and TA = 25"C.

2-136

1994 Data Book

H~Lattice
••••••

Specifications pLSI and ispLSI 1048C

••••••
••••••

External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TESTs #2
CONDo

-70

DESCRIPTION1

-50

UNITS

MIN. MAX. MIN. MAX.

tpd1

A

Data Propagation Delay, 4PT bypass, ORP bypass

18.0

24.0

tpd2

A

2

Data Propagation Delay

20.5

27.0

A

3

Clock Frequency with Internal Feedback3

max (Ext.)

4

Clock Frequency with External Feedback 10.2: leo

MHz

max (Tog.)

5

Clock Frequency, Max Toggle 4

MHz

6

GLB Reg. Setup Time before Clock, 4PT bypass

7

GLB Reg. Clock to Output Delay, ORP bypass

fmax

tsu1
tco1

A

ns
ns
MHz

54.1

ns
14.5

ns

th1

8

GLB Reg. Hold Time after Clock, 4 PT bypass

ns

tsu2

9

GLB Reg. Setup Time before Clock

ns

tco2

10 GLB Reg. Clock to Output Delay

th2

11 GLB Reg. Hold Time after Clock

tr1

A

12 Ext. Reset Pin to Output Delay

15.0

13 Ext. Reset Pulse Duration

trw1

15.5

10.0

ns
ns

0
20.0

ns

ns

ns

13.0

14 Input to Output Enable

20.0

26.5

C

15

20.0

26.5

ns

tgoeen

B

16

15.0

20.0

ns

tgoedis

C

17

15.0

20.0

ns

tptoeen

B

tptoedis

twh

20

6.0

8.0

ns

twl

21

6.0

8.0

ns

tsu3
th3

re Ext. Sync. Clock (Y2, Y3)
ter Ext. Sync. Clock (Y2, Y3)

2.0

2.5

ns

6.5

8.5

ns

GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock.
for further details.
9 GRP feedback.
(twh + twl). This is to allow for a clock duty cycle of other than 50%.
itions Section.
Table 2· 003D-4BBI70, 50

2-137

1994 Data Book

..
I

~~~Lattice

Specifications pLSI and ispLSI 1048C

••••••
••••••
••••••

Internal Timing Parameters 1

PARAMETER

#2

-70

DESCRIPTION

-50

UNITS

MIN. MAX. MIN. MAX.

Inputs
tiobp

24

I/O Register Bypass

-

3.1

tiolat

25

I/O Latch Delay

-

4.0

8.5

tiosu

26

I/O Register Setup Time before Clock

6.5

-

tioh

27

I/O Register Hold Time after Clock

0.1

-

tioco

28

I/O Register Clock to Out Delay

tior

29

I/O Register Reset to Out Delay

tdin

30

Dedicated Input Delay

-

GRP
GRP Delay, 1 GLB Load

32

GRP Delay, 4 GLB Loads

tgrp8

33

GRP Delay, 8 GLB Loads

tgrp12

34

tgrp16

35

GRP Delay, 16 GLB Loads

GRPD"'Y'12GlB~~~

tgrp48

36

GRP Delay, 48 GLB Loads

t4ptbp

37

4 Product Term Bypass Pat

t1 ptxor

38

1 Product Term/XOR Path

t20ptxor

39

20 Product Term/

txoradj

40

XORAdjacen

~
~ _~

~V

GLB

-

42

GLB

tgh

43

tgco

4

tgr
tptoe
tptck

Path

before Clock
Ime after Clock
. tar Reset to Output Delay

GLB Koduct Term Reset to Register Delay

~ ~B Product Term Output Enable to I/O Cell Delay
4~ GLB Product Term Clock Delay

ns
ns
ns

6.0

ns

6.5

ns

5.8

-

7.7

ns

6.7

-

8.9

ns

-

16.5

7.6

-

5.0

-

5.8

10.1

ns

22.0

ns

6.7

ns

7.8

ns

6.5

-

8.7

ns

8.0

-

10.7

ns

-

0.9

-

1.2

ns

1.4

-

1.9

-

ns

7.1

-

ns

1.5

-

1.8

ns

5.3

k to Output Delay

B
L

tptre

a

ns

-

4.9

.~

41

ns

w

~-

31

tgrp4

tgsu

-

·4

:.:!)

~

GLB Reg

ns
ns

~41
~~;::

tgrp1

tgbp

l.4

1

4.1
5.3

-

2.1

-

2.8

ns

8.6

11.5

ns

7.0

-

9.2

ns

3.0

6.5

4.0

8.7

ns

-

2.5

-

3.0

ns

1.7

ns

ORP
torp

49

ORP Delay

torpbp

50

ORP Bypass Delay

1.5

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
Table 2- 0036-488170. 50

2-138

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 104BC

Internal Timing Parameters 1

PARAMETER

DESCRIPTION

Outputs
tob

51

Output Buffer Delay

3.5

ns

toen

52

1/0 Cell OE to Output Enabled

6.7

ns

todis

53

1/0 Cell OE to Output Disabled

6.7

ns

tgyO

54

Clock Delay, YO to Global GLB Clock Line (Ref. clock)

ns

tgy1/2

55

Clock Delay, Y1 or Y2 to Global GLB Clock Line

ns

Clocks

tgcp

56

Clock Delay, Clock GLB to Global GLB Clock Line

ns

tioy2/3

57

Clock Delay, Y2 or Y3 to 1/0 Cell Global Clock Line

ns

tiocp

58

Clock Delay, Clock GLB to 1/0 Cell Global Clock Line

ns

Global Reset to GLB and 1/0 Registers

ns

Global Reset
tgr

59

1. Internal Timing Parameters are not tested and are for reference only
2. Refer to Timing Model in this data sheet for further details.
Table 2- 0037-48CI70, 50

2-139

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048C

••••••
••••••
••••••

pLSI and ispLSI 1048C Timing Model
I/O Cell

GRP

~-------

GLB

ORP

VO Cell

----------""------'------Feedback

Oed. In > - - - # " " 3 0 - - + - - - - - - - - .

Yl.2.3

)--------+1

YO

GOEO. 1~-----------------___::A~~~~~

Logic + Reg su - Cia
(tiobp + tgrp4 +
(#24 + #32 + 9
5.5 ns= (3.0 + 3.0 + 7.5)

tsu

th

- (tiobp + tgrp4 + tptck(min))
+ #32 + #48)
+ 3.0 + 3.5)

gic
R (max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
+ (#43) - (#24 + #32 + #39)
+ (6.0) - (3.0 + 3.0 + 7.5)

6.5 ns=
th

Clock (max) + Reg h - Logic
(tgyO(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#54 + #44 + #56) + (#43) - (#24 + #32 + #39)
5.0 ns= (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)

Clock (max) + Reg co + Output
= (tgyO(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #44 + #56) + (#44) + (#49 + #51)
21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)

tco

1. Calculations are based upon timing specs for the pLSl/ispLSI1048C-70.

2-140

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 104BC

••••••
••••••
••••••

Figure 3. Typical Device Power Consumption vs fmax
250
~

«
.s
u

200
150

~ 100

50

o

10

20

30

40

50

60

70

80

fmax (MHz)
Notes: Configuration of Twelve 16·bit Counters
Typical Current at 5V, 25'C

ICC can be estimated for the pLSI and ispLSI1048C using the following equatio :

pLSlandispLSl1048C-50

pLSI and ispLS11048C-70

(!)

3
2
4

8
GLB Loads

12

16
0126A-4BB-80-isp

2-141

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1048C

••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions ofthe Lattice High-Density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip. programming
can be accomplished by simply shifting data into the
device. Once the function is programmed. the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TIL level
logic interface signals. These five signals are fed into the
on-Chip programming circuitry where a state machine
controls the programming. The interface Signals are isp
Enable (ispEN). Serial Data In (SOl). Serial Data Out
(SDO). Serial Clock (SCLK) and Mode (MODE) control.
Figure 5 illustrates the block diagram of one possible
scheme for programming the ispLSI devices. For details
on the operation of the internal state machine and programming of the device please ref
the in-system
programming section in this Data

Figure 5. ISP Programming Interface

SOO
SOl

}

MODE

SCLK
ispEN

5-wire ISP
Programming
Interface

ispLSI

02948

2-142

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 1048C

••••••
••••••
••••••

ISP Programming Voltage/Timing Specifications1
SYMBOL

PARAMETER

CONDITION

VCCP

Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

ispEN

=low

MIN.

TYP.

MAX.

4.75

5

5.25

V

-

50

100

rnA

2.0

-

Veep

V

0.8

V

100

200

itA

VILP

Input Voltage low

0

liP

Input Current

-

VOHP

Output Voltage High

10H=

VOlP

Output Voltage low

tr, tf

Input Rise and Fall

tispen

ispEN to Output 3-State Enabled

tispdis

ispEN to Output 3-State Disabled

tsu

Setup Time

tco

Clock to Output

th

Hold Time

tclkh, tclkl

Clock Pulse Width, High and low

tpwv

Verify Pulse Width

10L=

0

5 mA

-L: ?veep

~ i\ 0.5

-..&:. ~

-

~\
~,

L::"

Programming Pulse Width

tbew

Bulk Erase Pulse Width

\;?"

"'Pv
.v

Reset Time From Valid V~ '\..
0

70'C'I\,

.'\h

tC

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 1048C

••••••
••••••

Figure 6. Timing Waveforms for In-System Programming

ispLSI Pins are 3·Stated During Programming

~{2Z~~--!~!:....------------------t
Unused
Output .to

MODE _ _ _--j-_ _

SDI

------r----~----~--------~r_~~~_,~~~~~-

SCLK ___~+~

__-'
Valid

MODE

SOl

SCLK

2-144

1994 Data Book

~~~latlice

Specifications pLSI and ispLSI 104BC

••••••
••••••
••••••

Figure 8 illustrates the address and data shift register bits
for the ispLSI1048C. For a detailed explanation refer to

the Device Layout discussion in the pLSI and ispLSI
Architectiural Description section of this Data Book.

Figure 8. ispLS11048C Shift Register Layout

Data In
(SOl)

o

o

A

A

T

T

A

A

Hi h Order Shift Re isler
Low Order Shift Re ister

o
SOO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic "0" disables it.

2-145

1994 Oata Book

~~~Lattice

Specifications pLSI and ispLSI 104BC

••••••
••••••
••••••

Pin Description
Name
1/00-1/05
1/06-1/011
1/012 - 1/0 17
1/018 -1/0 23
110 24 - 1/0 29
1/0 30 - 1/0 35
1/036 -1/0 41
1/042 - 1/047
1/0 48 - 1/0 53
1/0 54 - 1/0 59
1/0 60 - 1/0 65
1/0 66 - 1/0 71
1/072-l/on
1/0 78 - 1/0 83
1/0 84 - 1/0 89
1/0 90 - 1/0 95

PQFP Pin Numbers
21, 22, 23, 24, 25, 26
27, 28, 29, 30, 31, 32
34, 35, 36, 37, 38, 39
40, 41, 42, 43, 44, 45
52, 53, 54, 55, 56, 57
58, 59, 60, 61, 62, 63
66, 67, 68, 69, 70, 71
72, 73, 74, 75, 76, 77
85, 86, 87, 88, 89, 90
91, 92, 93, 94, 95, 96,
98, 99,100,101,102,103,
104,105,106,107,108,109,
117,118,119,120,121,122
123,124,125,126,127,128,

2,

3,

6,

7

8,

9, 10, 11, 12,

4,

5,

13

GOEO, GOE1

64, 114

IN2,IN4
IN 6 -IN 11

47, 51
84,110,111, 115,116, 14
18

SDI"/IN 0

20

MODE"/IN 1

46

SDO"/IN 3

SCLK"/IN 5

Description
InpuVOutput Pins - These are the general purpose 1/0 pins used by the
logic array.

programming enable input pin. This pin
programming mode. The MODE, SOl,
become active.
rms two functions. It is a dedicated input pin when
gh. When ispEN is logic low, it functions as an input
ramming data into the device. SDI/IN 0 also is used as
o control pins for the isp state machine.
This pin performs two functions. It is a dedicated input pin when
is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
InpuVOutput - This pin performs two functions. It is a dedicated input
pin when iSpEI\I is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input - This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, itfunctions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and 1/0 registers
in the device.

YO
Y1

83

Y2

80

Y3

79

GND

Vee

1, 17, 33, 49, 65,81,
97, 112
16, 48, 82,113

Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB andlor
any 1/0 cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any 1/0 cell on the
device.
Ground (GNO)

Table 2· 0002C-48C

'For ispLSI 1048C Only

2-146

1994 Data Book

~HLattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 1048C

Pin Configuration
pLSI and ispLSI 1048C 128-Pin PQFP Pinout Diagram

GND

1/084
1/085
1/086
1/087
1/088
1/089
1/090
1/091
1/092
1/093
1/094
1/095
INll
VO
VCC
__
GND
" ispEN/NC
RESET
"SDI/INO
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
1/011

52
1/051
1/050
1/049

1/048

pLSI1048C
and
ispLSI

IN 6
VI
VCC
GND

V2
V3
IN 51SCLK"
1/047
1/046
1/045
1/044
1/043

1/042
1/041
1/040

1/039
1/038
1/037
1/036
GND

"Pins have dual function capability for ispLSll048C only (except pin 18, which is ispEN only).
0124-48C

2-147

1994 Data Book

~~~Lattice
......
••••••

Specifications pLSI and ispLSI 1048C

••••••

Part Number Description

T 1

(is)pLSI 1048C - XX
Device Famlly-----II

X

X

X

T

Device Number - - - - - - - - '

G_

Blank = Commercial
I = Industrial

Package
Q=PQFP

Speed - - - - - - - - - - - - - '
70 = 70 MHz fmax
50 = 50 MHz fmax

Family

fmax (MHz)

Package

pLSI

70

128-Pin PQFP
128-Pin PQFP

IspLSI

128-Pin PQFP
128-Pin PQFP

INDUSTRIAL

50

Ordering Number

Package

24

pLSI 1048C-50LQI

128-Pin PQFP

24

ispLSI 1048C-SOLQI

128-Pin PQFP
Table 2- 0041A-48C-iep

2-148

1994 Data Book

Introduction to
pLSI@ and ispLS/TM 2000 Family
Introduction to pLSI and ispLSI 2000 Family

pLSI and ispLSI Product 2000 Family

Lattice Semiconductor's pLSI (programmable Large Scale
Integration) and ispLSI (in-system programmable Large
Scale Integration) are high-density and high-performance
E2CMOS® programmable logic devices. They provide
design engineers with a superior system solution for
integrating high-speed logic on a single chip.
The Lattice pLSI and ispLSI 2000 Families are I/O intensive, programmable logic devices that combine high
performance and ease of use of PLDs with the density
and flexibility of FPGAs.
The pLSI and ispLSI 2000 families are ideal for designs
needing high performance in conjunction with high I/O
requirements.
The ispLSI devices have also pioneered non-volatile, insystem programmability, a technology that allows real-time
programming, less expensive manufacturing and enduser feature reconfiguration.

135 MHz System Performance

0

7.5 ns Pin-to-Pin Delay

0

Deterministic Performance

0

High Density (1,000-4,000 PLD Gates)

0

44 Pin to 128 Pin Package Options

0

Flexible Architecture

0

Easy-to-Use

0

In-System Programmable (ispLSI)

0

Ideal for I/O Intensive Designs

pLSlandispLSITechnology

Lattice's E2CMOS technology features reprogrammability, the ability to program the device again and again to
easily incorporate any design modifications. This same
capability allows full parametric testability during manufacturing, which guarantees 100 percent programming
and functional yield.
All necessary development tools are available from Lattice and third-party vendors. Development tools offered
range from Lattice's low cost pDS® software, featuring
Boolean entry in a graphical WindowsTM based environment, to the pDS+TM family of fitters that interfaces with
third party development software packages. Design
systems interfacing with pDS+ Fitters feature schematic
capture, state machine and HDL design entry. Designs
can now be completed in hours as opposed to days or
weeks.

0

o

UltraMOS E2CMOS Choice

o

Electrically Erasable/Programmable/
Reprogrammable

o

100% Tested During Manufacture

o

100% Programming Yield

o

Fast Programming

the PLD Technology of

pLSI and ispLSI Development Tools

2-149

o

Low Cost, Fully Integrated pDS Design System
for the PC

o
o

Boolean Equations and Macro Input

o

pDS+ Support for Industry-Standard ThirdParty Design Environments and Platforms

o
o

Timing and Functional Simulation

HDL and Schematic Capture Entry

PC and Workstation Platforms

1994 Data Book

Introduction to pLSI and ispLSI 2000 Family
2000 Family Overview
The pLSI and ispLSI 2000 families of high-density devices address high-performance system logic needs,
implementing logic functions ranging from registers, to
counters, to multiplexers, to complex state machines.

Each device contains multiple Generic Logic Blocks
(GLBs), which are designed to maximize system flexibility
and performance. A balanced ratio of registers and 1/0
celis provides the optimum combination of internal logic
and external connections. A global interconnect scheme
ties everything together, enabling utilization of up to 80%
of available logic. Table 1 describes the family attributes.

With PLD density ranging from 1,000 to 4,000 gates, the
pLSI and ispLSI 2000 Families provide a wide range of
programmable logic solutions which meet tomorrow's
design requirements today.
Table 1. pLSI and IspLSI 2000 Family Attributes
Family Member

2032

2064

2096

Density (PLD Gates)

1,000

2,000

4,000

Speed: fmax (MHz)

135

135

110

Speed: tpd (ns)

7.5

7.5

10

Macrocelis

32

64

96

Registers

32

64

96

Inputs + I/O

34

68

102

44-pin PLCC

84-pin PLCC

128-pin PQFP

44-pin TQFP

100-pin TQFP

Pin/Package

Tab 1-DOO3A4000

Figure 1. 2000 Family Packages

o
pLSI2064
&
ispLSI2064

pLSI2096
&
ispLSl2096

44-Pin PLCC

84-Pin PLCC

128-Pin PQFP

pLSI2032

pLS12064
&
ispLSI2064

pLSI2032
&
ispLSI2032

&

o

ispLSI2032

44-Pin TQFP

o

100-Pin TQFP

2-150

0288·2000

1994 Data Book

pLSI® and ispLSI™ 2032
••••••
••••••
••••••

High Density Programmable Logic
Functional Block Diagram

Features
• HIGH DENSITY PROGRAMMABLE LOGIC
High Speed Global Interconnect
1000 PLD Gates
32 1/0 Pins, Two Dedicated Inputs
32 Registers
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic

•

-

Global Routing Pool
(GAP)

• HIGH PERFORMANCE E'CMOS" TECHNOLOGY

=

- fmax 135 MHz Maximum Operating Frequency
- tpd = 7.5 ns Propagation Delay
- TIL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
-100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
-In-System Programmable 5-Volt Only
- Change Logic and Interconnects "On-the-Fly" in
Seconds
- Reprogram Soldered Devices for Debugging
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND
OF FIELD PROGRAMMABLE GATE
- Complete Programmable Device Can
Logic and Structured Designs
- Three Dedicated Clock Input
- Synchronous and A.. vn.ohr'nn
- Flexible Pin Plalcelmelnt
- Optimized Global
Interconnectivity
• pLSllispLSI
pDS Snlftw:A ....

-

Standard, Third Party Design
Environments
Schematic Capture, State Machine, HDL
Automatic Partitioning and Place and Route
Comprehensive Logic and Timing Simulation
PC and Workstation Platforms

and ispLSI 2032 are High Density
Logic Devices. The devices contain 32
32 Universal I/O pins, two Dedicated Input
Dedicated Clock Input Pins, one dedicated
OE input pin and a Global Aouting Pool (GAP).
The GAP provides complete interconnectivity between
all of these elements. The ispLSI2032 features 5-Volt insystem programmability and in-system diagnostic
capabilities. The ispLSI 2032 offers non-volatile "on-thefly" reprogrammability of the logic, as well as the
interconnects to provide truly reconfigurable systems. It
is architecturally and parametrically compatible to the
pLSI 2032 device, but multiplexes four input pins to
control in-system programming.
The basic unit of logic on the pLSI and ispLSI 2032
devices is the Generic Logic Block (GLB). The GLBs are
labeled AO, A1 .. A7 (see figure 1). There are a total of
eight GLBs in the pLSI and ispLSI 2032 devices. Each
GLB is made up of four macrocells. Each GLB has 18
inputs, a programmable AND/OR/Exclusive OA array,
and four outputs which can be configured to be either
combinatorial or registered. Inputs to the GLB come from
the GAP. All ofthe GLB outputs are brought back into the
GAP so that they can be connected to the inputs of any
GLB on the device.

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800·LATTICE; FAX (503) 681-3037

2-151

1994 Data Book

~HLattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 2032

Functional Block Diagram
Figure 1" pLSI and ispLSI2032 Functional Block Diagram

GOEO

Global Routing Pool
(GRP)

MODE"

•

ispEN"

•

, each of which is
directly connec
'"'J,r""'''''Each I/O cell can be
individually. _ •. _"...... _,.....
a combinatorial input,
in with 3-state control. The
output 0
L c patible voltages and the output
signal Ie
drivers can
4 mA or sink 8 mAo
Eight GLBs,
I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 32 universal I/O cells by the ORP. Each pLSI and
ispLSI 2032 devices contain one Megablock.

YO
Yl"

**Note: Y1 and RESET

SCLK"1Y2

on the same pin

are multiplexed

The GRP has as its inputs, the outputs from all of the
GLBs and all ofthe inputs from the bi-directionall/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the pLSI and ispLSI 2032 devices are selected
using the dedicated clock pins. Three dedicated clock
pins (YO, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.

2-152

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 2032

Absolute Maximum Ratings 1
Supply Voltage Vee .................... -0.5 to +7.0V
Input Voltage Applied ......•........-2.5 to Vee + 1.0V
Off-State Output Voltage Applied ......-2.5 to Vee +1.0V
Storage Temperature ..................-65 to 125°C
Ambient Temp. with Power Applied ........-55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings· may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections
specification
is not implied (while programming, follow the programming specifications).

0.8

Vcc+ 1

2-153

v

1994 Dala Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load

Figure 2. Test Load

GNDt03.0V
~

+5V

3ns 10% to 90%
1.5V
1.5V

Device _ _ _ _ _...._ _..._ _ _.. Test
Output
Point

See figure 2

3-state levels are measured 0.5V from steady-state
active level.

1. One output at a time for a maximum duration of one second. V...
degradation. Guaranteed but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at Vcc = 5V and T.. = 25°C.

2-154

=0.5V was selected to avoid test problems by tester ground
Tabl. 2· 000710p.'2032

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

• •••••
••••••
••••••

Over Recommended Operating Conditions
PARAMETER TEST5,2
CONO.

·135
-80
·110
1---,.--+--,---1---.---1 UNITS

DESCRIPTION1

MIN. MAX. MIN. MAX. MIN. MAX.

tpdl

A

1 Data Propagation Delay, 4PT bypass, ORP bypass

7.5

-

10.0

15.0

tpd2

A

2

Data Propagation Delay

10.0

-

13.3

20.0

fmax

A

3

Clock Frequency with Internal Feedback"

-

110.7

-

fmax (Ext.)

4 Clock Frequency with External Feedback{..

fmax (Tog.)

5

Clock Frequency, Max Toggle 4

137

u2: tcoJ

79.2

50

MHz

167

125

100

MHz

6

GLB Reg. Setup Time before Clock, 4PT bypass

4

-

5.3

GLB Reg. Clock to Output Delay, ORP bypass

-

4.5

-

8

GLB Reg. Hold Time aiter Clock, 4 PT bypass

o

tsu2

9

GLB Reg. Setup Time before Clock

tc02

10 GLB Reg. Clock to Output Delay

-

th2

11 GLB Reg. Hold Time aiter Clock

o

tcol

A

thl

trl

A

5.5

-

LI -

5y~' 10.0

tptoeen

B

14 Input to Output Enable

tptoedls

C

15 Input to Output Disable

tgoeen

B

16 Global OE to Output Enable

tgoedis

C

17 Global OE to Output Disable

ns
ns
ns

-

~

1"1-

1i'~/-

5.5"~""!J'
~

0 ~""J>

12.0

ns
ns
ns

0

12 Ext. Reset Pin to Output Delay

ns

~ 'YI~

13 Ext. Reset Pulse Duration

trwl

ns
MHz

100

7

tsul

80

ns

-

10.0

18.0

ns

-

18.0

ns

14.5

L\'
,"-. ' -

~

- rr..O

,\y -

-

14.5

ns

6.0

6.7

9.5

ns

6.0

6.7

9.5

ns

twh

18 External Synchronous C!~

~¥9h

3.0

4.0

5.0

ns

twl

19 External Synchrono~ck~&£~n, Low

3.0

4.0

5.0

ns

1.
2.
3.
4.
5.

Unless noted otherwise, aU parameters use 20
R th a
Refer to Timing Model in this data sheet f
rther de ils.
Standard 16·Bit loadable counter usln
feedba
frnax (Toggle) may be less than 1/(
I This i
for a clock duty cycle of other than 50%.
Reference Switching Test Condi .
t
Table 2 - OO3OAI2032-135

2·155

1994 Data Book

•

~~~lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Internal Timing Parameters 1
Over Recommended Operating Conditions
PARAMETER

.2

-110

-135

DESCRIPTION

-80

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

Inputs
tiobp

20

1/0 Register Bypass

1.0

1.3

26

Dedicated Input Delay

-

-

tdin

-

2.6

-

3.5

28

GRP Delay

-

1.3

-

1.7

-

3.2

-

2.0

ns

4.0

ns

A

2.0

ns

6.5

ns

~

ns

8.0

ns

1""'-

9.5

ns

-

1.0

ns

1.0

-

ns

GRP
tgrp

A" ~ Ttl

GLB
t4ptbp

33

4 Product Term Bypass Path Delay

t1ptxor

34

1 Product TermlXOR Path Delay

t20ptxor

35

20 Product TermlXOR Path Delay

txoradj

36

XOR Adjacent Path Delay3

tgbp

37

GLB Register Bypass Delay

tgsu

38

GLB Register Setup Time before Clock

tgh

39

GLB Register Hold Time after Clock

tgco

40

....,.7

tgr

41

tptre

42

/{'\.,
GLB Register Reset to Output Delay AVF'\. '\.
~
GLB Product Term Reset to Register~a~ "\. ':J -

tptoe

43

GLB Product Term Output En~(\~I1~

-

tptck

44

GLB Product Term Cloc~ ~\

45

ORP Delay

torpbp

/(

tob

47

O~

toen

48 ~~ O~~t Enabled

~

CIOCky"("\ ]

, I~ ~JI'vutput

IUS

4.7

~

~~
,~

"\.

I:;

-,

- LA:-- ~...... '

A

r'\3}

~~

-, ,~

"'
V

~

-

~,.

4.5

4.5

0.2

ns
2.0

ns

2.5

ns

5.9

-

10.0

ns

7.2

-

9.0

ns

4.4

4.4

3.5

3.5

ns

1.3

-

1.7

-

2.5

-

0.4

-

ns

0.3

0.5

ns

1.2

3.0

ns

4.3

5.0
5.0

ns

2.2

-

2.3

2.3

3.1

3.1

4.5

4.5

ns

-

6.4

-

8.5

-

9.0

ns

6.5

-

3.3

3.3

-

'\.~

-

Disabled

1.1
4.4

2.2

1.5

1.6

-

4.3

ns

,,~-

tgyO/~ ~ C~ Delay, YO to Global GLB Clock Line (Ref. clock)
Global R\.s~
tgr

~

-

Bypas~'- ""- ))¥
/(~,.., .& " \ . ';I'

ORP

todis

V

"'"",,'Y"V\":?'''''

46

Outputs

.L

GLB Register Clock to Output Delay

ORP
torp

A

~

4.0

Global Reset to GLB

1. Intemal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

2-156

Table 2- 0036A-1611351110

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

pLSI and ispLSI 2032 Timing Model

..--..--....-------..,..,-----"'"------. ...--""""--. ...- .....' - 110 Cel

GRP

GLB

ORP

VO Cell

Feedback

Oed.ln)-----,t2""s=---+--------,
110 Delay
~Pin~-~.~w~--+r_--~-~~~~~~~._~~~~~t_~~~-+H

(Input)

R"«>-------------r_-~~~~I

YO,1,2

>-________....;15:.:.0=---_ _ _ _ _ _ _ _

~

OOEO>-_ _ _ _ _ _ _ _~I5~S,~57~_ _ _ _ _ _ _~~~~~~~~

-Note: Y1 .,d Y2 ooly for plSI and iapl8l1018

CI

in)
or) + (tgsu) - (tiobp + tgrp + tptck(min)
+ (#38) - (#20 + #28 +#44}
) + (0.8) • (1.0 + 1.3 + 3.3)
~!p~l!lll!Jj() + Reg h • Logic
v4!!!'~fi.,'M':+ tgrp + tptck(max) + (tgh) - (tiobp + tgrp + t2optxor)
0+ #28 + #44) + (#39) - (#20 + #28 + #35)
"""'''''''4:111''' (1.0 + 1.3 + 3.3) + (3.0) • (1.0 + 1.3 + 4.7)

Clock (max) + Reg co + Output

= (tiobp + tgrp + tptck(max) + (tgco) + (torp + tob)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
8.8 ns

= (1.0 + 1.3 + 3.3) + (0.7) + (1.3 + 1.2)

Note: Calculations are based upon timing specifications for the pLSI and ispLS12032·135L.

2-157

1994 Data Book

•

i

~HLattice
......
••••••

Specifications pLSI and ispLSI 2032

••••••

Power Consumption
Power Consumption in the pLSI and ispLSI 2032 device
depends on two primary factors: the speed at which the
device is operating and the number of Product Terms

used. Figure 3 shows the relationship between power
and operating speed.

Figure 3. Typical Device Power Consumption vs fmax

90

<'
S
u

pLSI and ispLSI 2032

80
70

~ 60

50
40

0

ICC can be estimated for the pLSI and ispLSI 2032 using the follo~l\O·~101~
ICC =23 + (# of PTs * 0.33) + (# of nets * Max freq * 0.011)
# of PTs =Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device
m temperature) and an assumption of 2 GLB loads on
e value of ICC is sensitive to operating conditions and the
0127A-16-SD-ispl2000

2-158

1994 Data Book

~HLattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions of the Lattice high density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip, programming
can be accomplished by simply shifting data into the
device. Once the function is programmed, the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TTL level
logic interface signals. These five signals are fed into the
on-chip programming circuitry where a state machine
controls the programming. The simple signals for interface include isp Enable (ispEN), Serial Data In (SOl),
Serial Data Out (SDO), Serial Clock (SCLK) and Mode
(MODE) control. Figure 4 illustrates the block diagram of
one possible scheme of the programming interface for
the ispLSI devices. For details on the operation of the
internal state machine and programming of the device
please refer to the in-system program . section in this
Data Book.

Figure 4. ISP Programming Interface

SOO
}
SOl
MODE
SCLK
ispEN

5-wire ISP
Programming
Interface

ispLSI

ispLSI

02948

2-159

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 2032

ISP Programming Voltage/Timing Specifications 1

VCCP

PARAMETER
Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

VllP

Input Voltage low

SYMBOL

CONDITION

liP

Output Voltage High

IOH= -3.2 mA

VOlP

Output Voltage low

101. = 5 rnA

tr. tf

Input Rise and Fall
ispEN to Output 3-State Enabled

tispdis
tsu

Setup Time

teo

Clock to Output

th

Hold Time

tclkh. !elkl

Clock Pulse Width. High and low

tpwv

Verify Pulse Width

tpwp

Programming Pulse Width
Bulk Erase Pulse Width

trst

Reset Time From Valid Vccp

MAX.
5.25

UNITS

50

100

mA

-

Veep

v

0.8

v

100
2.4

o

-

v

200

Veep

~'.5

v
V
I1s
I1s

A

,.,SP_""._",r,.,.c·wv
tbew

TYP.
5

o

VOHP

iSP'EN to Output 3-State Disabled

2.0

ispEN= Low

Input Current

tispen

MIN.
4.75

2-160

'"

-:)

30
20
40
200

100

ms

ms

45
Table 2- 00291sp-C

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 2032

Figure 5. Timing Waveform for In-System Programming

MODE _ _ _-+-'"

SCLK

----+-01818

MODE

SCLK

~

Don'tCare

~

Undefined State

-.....,..r;;.

'--_/

_ _ _J

2-161

' _.....

1994 Data Book

~HLattice
......
••••••

Specifications pLSI and ispLSI 2032

••••••

Figure 7. ispLSI 2032 Shift Register Layout
D
A
T
A

D
A
T
A

Data In~f-:'3:c:9c:.::
••,,---._ _----':-'H"-"ig""h'--:O~r:...::d=-=e-=--r=-S:=-=,h,"=-ift=-::R==-e=.. g, :,is-=-t::..::ce,,---r_ _ _---::-::-I
(SOl)
79...
Low Order Shift Register
~----------~~-----~

6

Note:

soo

A logic "1" in the address shift register enables the row for programming or verification.
A logic "0" disables it.

2-162

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Pin Description
Name

PLCC Pin Numbers

Description
Input/Output Pins - These are the general purpose 1/0 pins used by the
logic array.

1/00-1/03
1/04-1/07
1/08-11011
1/0 12 -1/0 15
1/0 16 - 1/0 19
1/0 20 - 1/0 23
1/024-1/027
1/0 28 - 1/0 31

15,
19,
25,
29,
37,
41,
3,
7,

GOEO

2

Global Output Enable input pin.

YO

11

Y1/RESET

35

Dedicated Clock input. This clock inp
clock inputs of all the GLBs in the d
This pin performs two functions:

16,
20,
26,
30,
38,
42,
4,
8,

17,
21,
27,
31,
39,
43,
5,
9,

18,
22,
28,
32,
40,

44,
6,
10

of the

1. Dedicated Clock input. Thi c
clock inputs of all the
Bs
2. Active Low (0) Res
ispEN'/NC

13

MODE'/NC
SDI'/INO

36
14

SDO'/IN1

24

SCLK'IY2

33

GND
VCC

amming enable pin. this pin is
ming mode. When low, the MODE,
me active.
e, controls operation of ISP state-machine.
ions:
pin when not in ISP mode.
put when in ISP mode.
rforms two functions:
ted input pin when not in ISP mode.
rial data output when in isp mode.
his pin performs two functions:
1. Dedicated Clock input. This clock input is connected to one of the
clock inputs of all the GLBs in the device.
2. Input - When in ISP mode, functions as a clock pin for the Serial
Shift Register.
Ground (GND)
Vee

Table 2· 0002A·08isp/2000

2-163

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Pin Description

Name

Description

TQFP Pin Numbers
9,
13,
19,
23,
31,
35,
41,
1,

GOEO

40

Global Output Enable Input Pin.

ispEN*/NC

7

Input - Dedicated in-system progr
is brought low to enable the
ram
SDO and SCLK options beco

SDI'/IN 0

8

MODE'/NC

30

SDO'IIN 1

18

SCLK'1Y2

27

10,
14,
20,
24,
32,
36,
42,
2,

12,
16,
22,
26,

34,
38,
44,
4

edicated input pin when
w, it functions as an input
ice. SDIIIN 0 also is used as
state machine.
rms two functions. It is a dedicated input
Igh. When ispEN is logic low, it functions as
serial shift register data.
erforms two functions. It is a dedicated clock input
logic high. This clock input is brought into the Clock
etwork, and can optionally be routed to any GLB andlor
n the device. When ispEN is logic low, it functions as a clock
the Serial Shift Register.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
This pin performs two functions:

YO

- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB
and/or 1/0 cell on the device.
- Active Low (0) Reset pin which resets all of the GLB and 1/0
registers in the device.

Y1/RESET

GND
VCC

11,
15,
21,
25,
33,
37,
43,
3,

Input/Output Pins - These are the general purpose 1/0 pins used by the
logic array.

1/00-1/03
1/04-1/07
1/08-1/011
1/012 -1/0 15
1/016 ·1/0 19
1/0 20 - 1/0 23
1/0 24 - 1/0 27
1/028 - 1/0 31

Ground (GND)
6,

28

Vee

• For ispLSI 2032 Only

Table 2 • 00028-2032

2-164

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Pin Configuration
pLSI and ispLSI 2032 44-pin PLCC

.-

1/028
1/029

I

1/030
1/031

YO
VCC
*ispEN/NC

pLSI2032
and
ispLSI2032

*SDI/IN 0

1/00
1/01
1/02

1/018
1/017
1/016

pLSI2032
and
ispLSI2032

NC/MODE*
Yl/RESET
VCC
Y2ISCLK*

1/015
1/014

1/013
1/012

• ispLSI 2032 Only

2-165

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 2032

••••••
••••••
••••••

Part Number Description

_

Fam;"

(IS)r LSI 2 j - XXX X

x

XX

1

X

T

Device Number

-.

Blank = Commercial
Pin Count
44=44 Pins

SpHd------------------~

=

135 135 MHz fmax
110 = 110 MHz fmax
80 80 MHz fmax

=

Package

Device Family

44-Pin PLCC
44-PinTQFP
44-Pin PLCC
pLSI

44-PinTQFP
pLSI 2032-80LJ44

44-Pin PLCC

2032-80LT 44

44-PinTQFP

15
7.5

ispLS12032-135LJ44

44-Pin PLCC

135

7.5

ispLS12032-135LT44

44-Pin TQFP

110

10

ispLS12032-110LJ44

44-Pin PLCC

110

10

ispLSI 2032-11 OLT44

44-PinTQFP

80

15

ispLSI 2032-80LJ44

44-Pin PLCC

80

15

ispLSI 2032-80LT 44

44-PinTQFP
Table 2- 0041A-08isp/2000

2-166

1994 Data Book

Introduction to
pLSI@ and ispLS/TM 3000 Family
Introduction to pLSI and ispLSI 3000 Family

pLSI and ispLSI Product 3000 Family

Lattice Semiconductor's pLSI (programmable Large Scale
Integration) and ispLSI (in-system programmable Large
Scale Integration) are high-density and high-performance
E2CMOS® programmable logic devices. They provide
design engineers with a superior system solution for
integrating high-speed logic on a single chip.

0

10 ns Pin-to-Pin Delay

0

Deterministic Performance

0

High Density (8000 - 14,000 PLD Gates)

0

Flexible Easy-to-Use Architecture

0

In-System Programmable (ispLSI)

0

Boundary Scan (IEEE 1149.1)

pLSI and ispLSI Technology

The ispLSI devices have also pioneered non-volatile, insystem programmability, a technology that allows real-time
programming, less expensive manufacturing and enduser feature reconfiguration.
Lattice's E2CMOS technology features reprogrammability, the ability to program the device again and again to
easily incorporate any design modifications. This same
capability allows full parametric testability during manufacturing, which guarantees 100 percent programming
and functional yield.

110 MHz System Performance

.I

The Lattice pLSI and ispLSI 3000 Families are the third
generation to combine the performance and ease of use
of PLDs with the density and flexibility of FPGAs.
The pLSI and ispLSI 3000 Family is ideal for high density
deSigns, where integration of complete logic sUb-systems into a single device is necessary.

0

o

UltraMOS E2CMOS Choice

o

Electrically Erasable/Programmable/
Reprogrammable

o

100% Tested During Manufacture

o

100% Programming Yield

o

Fast Programming

the PLD Technology of

pLSI and ispLSI Development Tools

All necessary development tools are available from Lattice and third-party vendors. Development tools offered
range from Lattice's low cost pDS® software, featuring
Boolean entry in a graphical Windows™ based environment, to the pDS+™ family of Fitters that interface with
third party development software packages. pDS+ systems support schematic capture, state machine, Boolean,
and HDL Design entry. Designs can now be completed
in hours as opposed to days or weeks.

2-167

o

Low Cost, Fully Integrated pDS Design System
for the PC

o

HDL Boolean Equation and Schematic Capture
Entry

o

pDS+ Support for Industry-Standard ThirdParty Design Environments and Platforms

o
o

Timing and Functional Simulation
PC and Workstation Platforms

1994 Data Book

Introduction to pLSI and ispLSI 3000 Family
3000 Family Overview
The plSI and isplSI 3000 family of high-density devices
address high-performance system logic designs implementing logic functions, ranging from registers, to
counters, to multiplexers, to complex state machines.

Each device contains muHiple Generic logic Blocks
(GlBs), which are designed to maximize system flexibility
and performance. A balanced ratio of registers and I/O
cells provides the optimum combination of intemallogic
and external connections. A global interconnect scheme
ties everything together, enabling utilization of up to 80%
of available logic. Table 1 describes the family attributes.

With up to 14,000 PlD gates density, the plSI and isplSI
3000 Family provides a wide range of programmable
logic solutions which meet tomorrow's design requirements today.
Table 1. plSI and IsplSI3000 Family Attributes
Family Member

3192

3256

3320

Density (PLD Gates)

8,000

11,000

14,000

Speed: fmax (MHz)

110

80

80

Speed: tpd (ns)

10

15

15

Macrocells

192

256

320

Registers

288

384

480

96

128

160

128-pin POFP

160-pln MOFP
167-pin CPGA

208-pln MOFP
207-pin CPGA

Inputs +

va

PinIPackage

Table ,. 0003A-3000

Figure 1. 3000 Family Packages

•

o
pLSl3192

pLSI3256

"

"

lepLSl3192

IspLSI3256

128-Pln PQFP

1~lnMQFP

pLSl3320

"

IspLS13320

208-Pln MQFP

pLSI3256

pLSl3320

"

lepLSI3320

"

IspLSl3256

~ lD
•

187-Pln CPGA

207-PlnCPGA

2-168

1994 Data Book

pLSI® and ispLSI™ 3256
••••••
••••••
••••••

High Density Programmable Logic

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC
- High Speed Global Interconnect
-128110 Pins
- 11000 PLD Gates
- 384 Registers
- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
• HIGH PERFORMANCE

E2CMOS~

mEl

___ _

JllII

I Output Routing Pool I

i

~

@][BgJ§][BQJ

TECHNOLOGY

=

- fmax 80 MHz Maximum Operating Frequency
- tpd = 15 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
-100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
- In-System Programmable 5-Volt Only
- Change Logic and Interconnects "On-the-Fly" in
Seconds
- Reprogram Soldered Devices for Delbu!3gilng..~
• 100% IEEE 1149.1 BOUNDARY SCAN

~n,UIlIMIRfI

• OFFERS THE EASE OF USE AND CAc~'J!I"i~C'TClli
SPEED OF PLDs WITH THE ncl.... ,IT1IIII....
OF FIELD PROGRAMMABLE l.2~po..jN:lt~ y
- Complete Prclor:ammabl..
Logic and "'Trur","non
- Five Dedicated
- Synchronous
-Flexible

• pLSllispLSI
SYSTEM (pDS")
pDS Software
- Easy to
PC WlndowsTM Interface
- Boolean Logic Compiler
- Manual Partitioning
- Automatic Place and Route
- Static Timing Table
pDS+TM Software
- Industry Standard, Third Party Design
Environments
- Schematic Capture, State Machine, HDL
- Automatic Partitioning and Place and Route
- Comprehensive Logic and Timing Simulation
- PC and Workstation Platforms

Lattice pLSI and ispLSI 3256 are High Density
Programmable Logic Devices which contain 384 Registers, 128 Universal lID pins, five Dedicated Clock Input
Pins, eight Output Routing Pools (ORP), and a Global
Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3256
features 5-Volt in-system programmability and in-system
diagnostic capabilities. The ispLSI 3256 offers nonvolatile "on-the-fly" reprogrammability of the logic, as
well as the interconnects to provide truly reconfigurable
systems. It is architecturally and parametrically compatible to the pLSI 3256 devices, but multiplexes four input
pins to control in-system programming.
The basic unit of logic on the pLSI and ispLSI 3256
devices is the Twin Generic Logic Block (Twin GLB)
labelled AO, A 1... H3. There are a total of 32 ofthese Twin
GLBs in the pLSI and ispLSI 3256 devices. Each Twin
GLB has 24 inputs, a programmable AND array and two
OR/Exclusive-OR Arrays, and eight outputs which can
be configured to be either combinatorial or registered. All
Twin GLB inputs come from the GRP.

Copyright@ 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800·LATTICE; FAX (503) 681·3037

2-169

1994 Data Book

H~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 3256

Functional Block Diagram
Figure 1" pLSI and ispLSI 3256 Functional Block Diagram

Ii "g
...J

0

w

0

(!J

~

w

0

~
gj ~

0

(!J

W

0

0
::;

in

::;
I-

111111
TOE

1/00
1/01
1/02
1/03
V04
1/05
1/06
1/07
1/08
1/09
1/010
VOll
V012
1/013
1/014
1/015

III

I Output Routing Pool (ORP) I

I Output Routing Pool (ORP) I

~~~~

~~~~

TDVSDI"
TRST

TOO/SOO"

I B
"8

V095
V094
V093
V092

Ii:'

c::
Q.

B
I! 5B
I B
I~

1/091
1/090
V089
VOBB

c..

OJ

c:

S

V087
V086
V086
1/084

~

1/083
V082
V081
V080

(t
0

B~

I
Gi ~ I
8"55
~.E
I
[j§ I

V016
V017
VOla
1/019
1/020
V021
V022
V023

OJ III

1/024
1/025
1/026
1/027

E1

;j

1/028
V029
1/030
1/031

• ispLSI 3256 Only

1/079
1/078
1/077
1/076
1/075
1/074
1/073
1/072
V071
V070
V069
V068
V067
V086
1/065
1/064

0139isp13256

2-170

1994 Data Book

~HLattice

••••••
••••••

Specifications pLSI and ispLSI 3256

••••••

Description (continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 128 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mAo
The 128 I/O Cells are grouped into eight sets of 16 bits.
Each of these I/O groups is associated with a logic
Megablock through the use ofthe ORP. These groups of
161/0 cells share one ProductTerm Output Enable and
two Global Output Enable signals.

Clocks in the pLSI and ispLSI 3256 devices are provided
through five dedicated clock pins. The five pins provide
three clocks to the Twin GLBs and two clocks to the I/O
cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the pLSI and
Boundary Scan capability, which i.n~IPoised
connected between the on·-cni~iU'Sjmrf1\
device's input and output
ated boundary scan r"'niC!t~_\.,ifln j
boundary scan registers

Four Twin GLBs, 16 I/O Cells and one ORP are connected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The pLSI and ispLSI 3256
Device contains eight of these Megablocks.
The G RP has as its inputs the outputs from all of
GLBs and all of the inputs from the hirllirAIr.tirInA,K1C
All of these signals are made available
Twin GLBs. Delays through the GRP
ized to minimize timing skew and

32
Registers

384

I/O Pins

128

GlobalOE

2

Test OE
Table 1· 0003Aisp/3256

2-171

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Absolute Maximum Ratings

1

Supply VoHage Vee.................... -0.5 to +7.0V
Input VoHage Applied ...............-2.5 to Vee +1.0V
Off-State Output VoHage Applied ......-2.5 to Vee +1.0V
Storage Temperature ..................-65 to 125°C
Ambient Temp. with Power Applied ........-55 to 125°C
1. Stresses above those listed under the "Absolute Maximum Ratings' may cause permanent damageJP'llflA'cevlCe.
operation of the device at these or at any other conditions above those indicated in the operational ~tml~tf
is not implied (while programming, follow the programming specifications).

2-172

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Switching Test Conditions
Input Pulse Levels

Figure 2. Test Load

GNDt03.0V

Input Rise and Fall Time

:s; 3ns 10% to 90%
1.5V

Input Timing Reference Levels

1.5V

Output Timing Reference Levels
Output Load

See figure 2

3-state levels are measured 0.5V from steady-state
active level.
Tebte 2- 0003

Device
Test
Output - - - - -......- -....----I~ Point

fTOGGLE =1 MHz
1. One output at a time for a maximum duration of one second. V... = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2. Measured using sixteen 16-bit counters.
3. Typical values are at Vee 5Vand TA 25°C.
T..,..2-ooo71_

=

=

2-173

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

External Switching Characteristics 1 . 2. 3
Over Recommended Operating Conditions

PARAMETER tEST 5
CONDo

,2

_806

UNITS
MIN. MAX. MIN. MAX MIN. MAX.

tpd1

A

1 Data Propagation Delay, 4PT bypass, ORP bypass

tpd2

A

2 Data Propagation Delay

-

fmax

A

3 Clock Frequency with Intemal Feedbacl(3

80

tsu1

-

4 Clock Frequency with External Feedback (.OU2 : tcO'J

tc01

A

7 GLB Reg. Clock to Output Delay, ORP bypass

'max (Ext.)
fmax (Tog.)

-

th1
tsu2
!co2

/('"

trw1

-

13 Ext. Reset Pulse Duration

tptoeen

B

14 Input to Output Enable

tptoedis

C

15 Input to Output Disa~' ~\

tgoeen

B

16 Global OE output~",

Igoedis

C

17 Global OE ~t Disa~, ~""

-

18 Test OE ~~ablel"'>"?'
19 Tes.l#~ut~s1lbJf"

boedis

20 ~~l.

twh

~ l~

tsu3
th3
1.
2.
3.
4.
5.
6.

A ........."'

'\~

\\.. '\.. ",?V

~\'\..~¥

V

\~-

se Duration, High

1foI'.oI••I·~J'I'9tup Time before Ext. Sync. Clock (Y3,Y4)

~) I~ ~. Hold Time after Ext. Sync. Clock (Y3, Y4)
d~"'ise, ¥.'arameters use 20 P1XOR path and ORP.

",,-

-

'U.
1""'"

r""'-'
~-

-

"'-'

."
IP": v'
~~

-

-

-

- - - -

-

-

-

-

-

-

-

-

ns
ns

- ~ )~~ ~ ~ hq' ~ ~ v-

Unless
Refer to Ti
g odel in this data sheet for further details.
Standard 16er using GRP feedback.
fmax (Toggle)
be less than lI(lwh + lwl). This is to allow for a clock duty cycle of other than 50"10.
Reference SWitching Test Conditions Section.
Contact factory for additional information.

2-174

23

:A1 ~IO

.... ""'\

-

A

-

~-

-

- ~ 1iX) S~~Pulse Duration, Low

twl

\'

~~

;-

12 Ext. Reset Pin to Output Delay

boeen

-,.

9 GLB Reg. Setup Time before Clock

A

70

17

'-'

8 GLB Reg. Hold Time after Clock, 4 PT bypass

tr1

-

6 GLB Reg. Setup Time before Clock, 4PT bypass

10 GLB Reg. Clock to Output Delay

-

15

5 Clock Frequency, Max Toggle4

11 GLB Reg. Hold Time after Clock

th2

-50

-70

DESCRIPTION1

MHz
MHz
MHz
ns
ns
ns
ns
ns
ns

-

ns

-

ns
ns
ns

-

ns

-

ns

-

ns

ns

ns

-

-

-

ns
ns
ns

Table 12 -G03OAIS256

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Internal Timing Parameters 1
Over Recommended Operating Conditions

PARAMETER

#2

-804

DESCRIPTION

-70

-50

t---,---t---,--+---.----1UNITS
MIN. MAX. MIN. MAX. MIN. MAX~

Inputs
tiobp

24

I/O Register Bypass

tiolat

25

110 Latch Delay

tiosu

26

I/O Register Setup Time before Clock

-

tioh

27

I/O Register Hold Time after Clock

-

tioco

28

I/O Register Clock to Out Delay

2
~

9

2.7

ns

j

4.1

ns

-

ns

-1~~

ns

~~. ~

l./t'")-1

r\.

-

/'

~ ~

2.7

ns
ns

ns
A~

"'I ~

-

6.5

-

8.8

ns

-

-

7

-

9.5

ns

-

-

8.5

-

11.5

ns

-

-

10

-

13.5

ns

-

1.5

1
-

2

1.4
-

ns
ns

t4ptbp

37

4 Product Term Bypass Path Delay

tl ptxor

38

1 Product TermlXOR Path Delay

t20ptxor

39

20 ProductTerm/XOR Path Del~\\" ~V

txoradj

40

XOR Adjacent Path Delay3

tgbp
tgsu

41
42

GLB Register Bypass De~\.~~
GLB Register Setu~e bef

tgh

43

GLB Register ~m"after

9

-

12.2

-

ns

tgco

44

GLB Regi~to'Qu

elay

-

-

1.5

-

2

ns

tgr

45

GLB R~~ \\..~ut Delay

-

-

2.5

-

3.4

ns

tptre

46

G~(illucf't{e~et to Register Delay

-

-

10

-

13.5

ns

tptoe

47 ~Lll

12.2

ns

10.1

ns

2

2.7

ns

0.5

0.7

ns

tptck

"{""~ _~~

AT ~ '\~

-

7'----------+---+-~~-+--~~T-~r_~

-

~------------~r-~r-~r-~--~r-~r-~r-~

"" Output Enable to I/O Cell Delay

9

~ ,~-~ erm Clock Delay

3.5

7.5

4.7

ORP
torp
torpbp
1.
2.
3.
4.

J -

I~ ~PDelay

5~ ORP Bypass Delay

Internal Timing Parameters are not tested and are for reference only.
Refer to Timing Model in this data sheet for further details.
The XOR Adjacent path can only be used by Lattice Hard Macros.
Contact factory for additional information.

2-175

Table 2- 0036A13256

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Internal Timing Parameters 1
Over Recommended Operating Conditions

PARAMETER

DESCRIPTION

Outputs
tob

51

Output Buffer Delay

ns

toen

52

I/O Cell OE to Output Enabled

ns

todis

53

I/O Cell OE to Output Disabled

ns

54

Clock Delay, YO or Y1 or Y2 to Global GLB Clock Line

ns

Clocks
tgyO/1/2

(Ref. clock)
tioy3/4

56

Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line

ns

Global Reset to GLB and I/O Registers

ns

Global Reset
tgr

57

1. Internal Timing Parameters are not tested and are for reference onl
2. Refer to Timing Model in this data sheet for further details.
3. Contact factory for additional information.

2-176

Table 2· 0037Ai3256

1994 Data Book

~HLattice

Specifications pLSI and ispLSI 3256

••••••
••••••

••••••
pLSI and ispLSI 3256 Timing Model
110 C4III

GRP

GlB

ORP

VO Cell

'_--"---"'-'- -..- -....'r....- - - - -.. . . .- - - - - - , , , - - -..- -...,,,_-""*-_.
Feedback

GRP

YO,1,2 )------------=.:*50::.:....---------7*'_.,;:s~
GOEO,1 ) - - - - - - - - - - - - - - - - - - - . . , . " , ' - - ' I ! , - - - " " i l t - - - - - - '
TOE >-----------------~~~~It-~~---~

I
(min)
Optxor) + (tgsu) - (tiobp + tgrp4 + tptck(min»
+ (#42) - (#24+ #31 + #48)
+ (1.5) - (2 + 4 + 3.5 )
+

-..~,.._\max)

+ Reg h - Logic
+ tgrp4 + tptck(max» + (tgh) - (tiobp + tgrp4 + t2Optxor)
#24+ #31 + #48) + (#43) - (#24+ #31 + #39)
~ (2+4+7.5)+(9)-(2+4+8.5)
20 ns=

Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max» + (tgco) + (torp + tab)
(#24 + #31 + #48) + (#44) + (#49 + #51)
(2 +4 + 7.5) + (1.5) + (2 + 3)

Note: Calculations are based on timing specs for the ispLSI 3256-70L.

2-177

1994 Data Book

~HLattice
......
••••••
......

Specifications pLSI and ispLSI 3256

Power Consumption
Power Consumption in the pLSI and ispLSI 3256 device
depends on two primary factors: the speed at which the
device is operating and the number of product terms

used. Figure 3 shows the relationship between power
and operating speed.

Figure 3. Typical Device Power Consumption vs fmax
250
~
.s200
()

g

150

o

10

20

30

40

ICC can be estimated for the pLSI and ispLSI 3
ICC =44 + (# of PTs * 0.18) + (# of nets *
# of PTs = Number of Product Terms u
# of nets = Number of Signals used
Max. freq = Highest Clock Frequ
The ICC estimate is based
average exists. These
program in the de

(Vee =5.0V, room temperature) and an assumption of 2 GLB loads on
tes only. Since the value of ICC is sensitive to operating conditions and the
uld be verified.
0127A-16-80-isp/3000

2-178

1994 Data Book

~~~Lattice
••••••

Specifications pLSI and ispLSI 3256

••••••
••••••

In-System Programmability
The ispLSI devices are the in-system programmable
versions of the Lattice high density programmable Large
Scale Integration (pLSI) devices. By integrating all the
high voltage programming circuitry on-chip, programming
can be accomplished by simply shifting data into the
device. Once the function is programmed, the nonvolatile E2CMOS cells will not lose the pattern even when
the power is turned off.

All necessary programming is done via five TTL level
logic interface signals. These five signals are fed into the
on-Chip programming circuitry where a state machine
controls the programming. The simple signals for interface include isp Enable (ispEN), Serial Data In (SOl),
Serial Data Out (SDO), Serial Clock (SCLK) and Mode
(MODE) control. Figure 4 illustrates the block diagram of
one possible scheme of the programm'
interface for
the ispLSI devices. For details on t
eration of the
internal state machine and progr
please refer to the in-system prQfjt:m1Mninc}os,
Data Book.

Figure 4. ISP Programming Interface

SDO
SOl
MODE
SCLK
ispEN

}

5-wire ISP
Programming

Interface

ispLSI

02948

2-179

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

ISP Programming VoltagefTiming Specifications
SYMBOL

CONDITION

Programming Voltage

Iccp

Programming Supply Current

VIHP

Input Voltage High

VllP

Input Voltage low

MIN.
4.75

TYP.

MAX.

5

5.25

V

50

100

mA

Vccp

V

0

-

0.8

V

-

100

2.0

ispEN = low

liP

Input Current

VOHP

Output Voltage High

IOH = -3.2 mA
IOL= 5 rnA

VOlP

Output Voltage Low

trtf

Input Rise and Fall

tispen

ispEN to Output 3-State Enabled

tispdis

ispEN to Output 3-State Disabled

tsu

Setup Time

tco

Clock to Output

th

Hold Time

tclkh, tclkl

Clock Pulse Width, High and low

tpwv

Verify Pulse Width

tpwp

Programming Pulse Width

tbew

Bulk Erase Pulse Width

trst
I.

PARAMETER

VCCP

2.4

A~ l\Vccp

o "" ~ r\{l·5

"rr ~l.-

I " "~

A

N"
\ ' I>b.-'\ I~

. - -~
h~

'\.~

h~'~

(~, ,~¥

L '-\\'\. ~V

A~~

Reset Time From Valid V~i\.'

~\V
)';>'

l.pp"'~m".""""''''T'W''

2-180

1')200

~ .... k~
;{~~

'\j~

0.5
0.5

0.1

0.5

0.5

1

20

30

80

-

UNITS

~A

V
V

r">~

~

10

~s

10

~

-

~s
~s

~

-

~
~s

160

ms
ms

200

-

-

45

-

-

~s

TabI. 2· 0029 i'P·3258

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Figure 5. Timing Waveform for ISP Operation

Unus~
~22~~~~~~~~----------------------------f8~~
Outputio

MODE

--------t-

SCLK _ _ _ _-+__

zz

Don'tCare

~

Execute State (Program. Verify or Bulk Erase Instruction)
MODE _--"" I ~I

tpwp. tbew. or tpwv
SOl

~--th---~'----+-------------'

~~~k~lk~h~

..,,7

SCLK _ _

'\

hu

,----/

/

Fklkl~

2-181

' _.....

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Figure 7. ispLSI3256 Shift Register Layout
D
A
T
A

D

A
T
A

High Order Shift Register
Low Order Shift Register

6

soo

0182Ai3256

Note:

A logic "1" in the address shift register enables the row for programming or verification.
A logic "0" disables it.

2-182

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 3256

Boundary Scan
Lattice offers support for the IEEE 1149.1 Boundary
Scan specification on the 3000 Family of devices.
The user interfaces to the boundary scan circuitry through
the Test Access Port (TAP). The TAP consists of a
control state machine, instruction decoder and instruction register.

The TAP is controlled using the test control lines: Test
Data IN (TOI), Test Data Out (TOO), Test Mode Select
(TMS), Test Reset ('FRST) and Test Clock (TCK).
The timing specifications for Boundary Scan are listed
below. The waveforms are shown in figure 9.

Figure 8. Boundary Scan Waveforms

VCC

BSCAN

.....:...~-'-''-'J..

0181A.eps

2-183

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Pin Description

Name
1/00-1/04
1/05-1/09
1/010 -1/014
1/015 -1/019
1/0 20 - 1/0 24
1/0 25 - 1/0 29
1/0 30 - 1/0 34
1/035 - VO 39
1/0 40 - 1/0 44
1/0 45 - 1/0 49
1/0 50 - 1/0 54
1/0 55 - 1/0 59
1/0 60 - 1/0 64
1/0 65 - 1/0 69
1/070 -1/0 74
1/0 75 - 1/0 79
1/0 80 - 1/0 84
1/0 85 - 1/0 89
1/0 90 - 1/0 94
1/0 95 - 1/0 99
1/0100 -1/0 104
1/0105 -1/0 109
1/0110 -1/0114
1/0115 -1/0 119
1/0120 - 1/0 124
1/0125 - 1/0 127

CPGA Pin Numbers
G1,
F3,
D3,
B1,
C6,
A6,
C9,
B11,
A14,
B15,
A17,
E16,
G16,
M17,
N16,
S16,
S14,
T14,
T11,
T9,
T6,
T3,
R4,
P2,
M3,
L1,

G2,
C1,
B2,

B4,

A4,
A7,
A9,
A12,
A15,
C14,
D16,
F15,
G17,
N17,
S17,
R15,
R13,
S12,
R10,
T8,
R7,
T2,
S2,
N3,
P1,
K3,

GOEO and GOE1
TOE

J17 and J15
J16

RESET

J3

YO, Y1 andY2

K1,

Y3 and Y4

K16,

G3,
E2,
C3,
C5,
B6,
C8,
A10,
C11,
A16,
B16,
E15,
D17,
H15,
M16,
N15,
R14,
T15,
T13,
S10,
S8,
T5,
R5,
R3,
S1,
N1,
K2

E1,
E3,

C4,
A3,
AS,
B8,
B10,
A13,
C13,
C15,
B17,
E17,
H16,
P17,
P16,
S15,
S13,
R11,
S9,
T7,
S6,
S4,
P3,
R1,
M1,

Description

F2,
Input/Output Pins - These are the general purpose 1/0 pins used by the
D2,
logic array.
B3,
B5,
C7,
B9,
A11,
B12,
B14,
D15,
C17,
F17,
L16,
R17,
P15,
T17,
R12,
T12,
R9,
S7,
T4,
S3,
T1,
N2,

l2,

epin.
) Reset pin which resets all of the GLB and 1/0 registers
ice.
ted Clock inputs. These clock inputs are connected to one of
clock inputs of all the GLBs on the device.
Dedicated Clock inputs. These clock inputs are connected to one of
the clock inputs of all the 1/0 cells in the device.
e

J2,

Boundary Scan Enable. Input - Dedicated in-system programming
enable input pin. This pin is brought low to enable the programming
mode. The MODE, SDI, SDO and SCLK options become active.
Input - This pin performs two functions. It is the Test Data input pin
when ispEN is logic high. When ispEN is logic low, it functions as an
input pin to load programming data into the device. SDI is also used
as one of the two control pins for the isp state machine.
Input - This pin performs two functions. It is the Test Clock input pin
when ispEN is logic high. When ispEN is logic low, it functions as a
clock pin for the Serial Shift Register.

BSCANlispEN"
TOI/SDI"

TCL

H3

TRST

H17

TOO/SDO"

L17

GND

VCC

F1,
B13,
T16,
M2
D1,
T10,

Input - This pin performs two functions. It is the Test Mode Select input
pin when rspEIiI is logic high. When ispEN is logic low, it functions as
pin to control the operation of the isp state machine.
Input - Test Reset, active low to reset the Boundary Scan State
Machine.
Output - This pin performs two functions. When ispEN is logic low, it
functions as the pin to read the isp data. When ispEN is high itfunctions
as Test Data Out.
A2,
C2,
C16, F16,
S11, S5,
A8,
L3,

B7,
L15,
R8,

G15, C12,
R6

C10, Ground (GND)
R16,
R2,
M15, Vee
Table 2- 0002isp/3256

• ispLSI 3256 Only

2-184

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Pin Description

Name
1/00-1/04
1/05-1/09
1/010 -1/0 14
1/015 -1/0 19
1/020 -11024
1/025 -110 29
1/0 30 - 1/0 34
1/0 35 - 1/0 39
1/0 40 - 1/0 44
1/0 45 - 1/0 49
1/0 50 - 1/0 54
1/0 55 - 1/0 59
1/0 60 - 1/0 64
1/0 65 - 1/0 69
1/0 70 - 1/0 74
1/0 75 - 1/0 79
1/0 80 - 1/0 84
1/0 85 - 1/0 89
1/0 90 - 1/0 94
1/0 95 - 1/0 99
1/0100 -1/0104
1/0105 -1/0 109
1/0110 -1/0 114
1/0115-1/0119
1/0 120 - 1/0 124
1/0125 -1/0 127
GOEO and GOE1
TOE

MQUAD Pin Numbers
25,
32,
37,
42,
48,
54,
59,
65,
70,
76,
82,
87,
93,
106,
113,
118,
123,
129,
135,
140,
146,
152,
157,
3,
8,
15,

26,
33,
38,
43,
49,
55,
60,
66,
72,
77,
83,
88,
94,
108,
114,
119,
124,
130,
136,
141,
147,
153,
158,
4,
9,
16,

28,
34,
39,
44,
50,
56,
61,
67,
73,
78,
84,
89,
95,
109,
115,
120,
126,
132,
137,
142,
148,
154,
159,
5,
11,
17,

29,
35,
40,
46,
52,
57,
62,
68,
74,
79,
85,
90,
96,
110,
116,
121,
127,
133,
138,
144,
149,
155,
160,
6,
13,

30,
36,
41,
47,
53,
58,
64,
69,
75,
80
86,
92,
105,
112,
117,
122,
128,
134,
139,
145,
150,
156,
2,
7,
14,

RESET

20
18, 19

Ie pin.
(0) Reset pin which resets all of the GLB and 1/0 registers
vice.
Icated Clock inputs. These clock inputs are connected to one of
e clock inputs of all the GLBs on the device.
Dedicated Clock inputs. These clock inputs are connected to one of
the clock inputs of all the 1/0 cells in the device.

Y2, Y3 and Y4

Boundary Scan Enable. Input - Dedicated in-system programming
enable in~ut pin. This pin is brought low to enable the programming
mode. T e MODE, SDI, SDO and SCLK options become active.
Input - This pin performs two functions. It is the Test Data input pin
when ispEN is logic high. When ispEN is logic low, it functions as an
input pin to load programming data into the device. SDI is also used
as one of the two control pins for the isp state machine.
Input - This pin performs two functions. It is the Test Clock input pin
when ispEN is logic high. When ispEN is logic low, it functions as a
clock pin for the Serial Shift Register.
Input- This pin performs two functions. It is the Test Mode Select input
pin when Isj5E1iI is logic high. When ispEN is logic low, it functions as
pin to control the operation of the isp state machine.
Input - Test Reset, active low to reset the Boundary Scan State
Machine.
Output- This pin performs two functions. When ispEN is logic low, it
functions as the pin to read the isp data. When ispEN is high itfunctions
as Test Data Oul.

BSCANlispEN"
TOI/SDI"

TMS/MODE"

24

TRST

97

TOO/SDO"

104

VCC

Input/Output Pins - These are the general purpose 1/0 pins used by the
logic array.

100 and 99
98

YO and Y1

GND

Description

1,
81,
12,
111,

10,
107,
31,
131,

27,
125,
51,
151

45,
143
71,

63,

Ground (GND)

91,

Vee

• ispLSI 3256 Only

Table 2- 0OO2Bisp/3256

2-185

1994 Data Book

H~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••
••••••

Pin Configuration
pLSI and ispLS13256167-pin CPGA Pinout Diagram

17

16

15

14

13

12

11

10

9

• ispLSI 3256 Only

8

7

6

5

4

3

2

1

0123Blsp

2-186

1994 Data Book

~~~Lattice

••••••
••••••
••••••

Specifications pLSI and ispLSI 3256

Pin Configuration
pLSI and ispLSI 3256 16D-Pln MQUAD Pinout Diagram

*ispLSI 3256 Only

2-187

1994 Data Book

~~~Lattice

Specifications pLSI and ispLSI 3256

••••••
••••••

••••••
Part Number Description

XXXX(XX) 3256 - XX

X

Device Family _ _----JI

1

X XXX X

T

pLSI
ispLSI

GMa

Blank = Commercial

Pin Count

Device Number - - - - - - - - - '

167 =
160

Speed - - - - - - - - - - - - '
80 = 80 MHz fmax
70 = 70 MHz fmax
50 = 50 MHz fmax

Family

Package
160-Pin MQUAD
167-Pin CPGA
pLS13256-70LM160

160-Pin MQUAD

pLS13256-70LG167

167-Pin CPGA

23

pLS13256-50LM160

160-Pin MQUAD

23

pLS13256-50LG160

167-Pin CPGA

80

15

ispLS13256-80LM160

160-Pin MQUAD

80

15

ispLSI 3256-80LG167

167-Pin CPGA

70

17

ispLS13256-70LM160

160-Pin MQUAD

70

17

ispLS13256-70LG167

167-Pin CPGA

50

23

ispLS13256-50LM160

160-Pin MQUAD

50

23

ispLSI 3256-50LG167

167-Pin CPGA

ispLSI

Table 2- 0041 A-08isp/3256

2-188

1994 Data Book

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Introduction to Generic Array Logic ...................................................... 3-1
Commercial/Industrial Product Datasheets
GAL 1SV8 .............................................................................................. 3-5
GAL 1SV8ZJZD ...................................................................................... 3-29
GAL 1SVP8 ........................................................................................... 3-49
GAL18V10 ............................................................................................ 3-S7
GAL20RA10 ......................................................................................... 3-79
GAL20V8 .............................................................................................. 3-97
GAL20V8ZJZD ...................................................................................... 3-121
GAL20VP8 ........................................................................................... 3-141
GAL20XV10 ......................................................................................... 3-159
GAL22V10 ............................................................................................ 3-173
ispGAL22V10 ....................................................................................... 3-193
GAL2SCV12 ......................................................................................... 3-213
GALS001 .............................................................................................. 3-231
GALS002 .............................................................................................. 3-249
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information

3-i

•

3-ii

Introduction to
Generic Array Logic
Overview

The GAL 16V8 and GAL20V8

Lattice, the inventor of the Generic Array Logic (GAL®)
family of low density, E2CMOS PLDs is the leading
supplier of low density CMOS PLDs in the world. Features
such as industry leading performance, low power
E2CMOS technology, 100% testability and 100%
programming yields make the GAL family the preferred
choice among system designers.
The GAL family contains 14 product architectures with a
variety of performance levels specified across commercial,
industrial and military (MIL-STD-883) operating ranges
to meet the demands of any system logic design.

• Performance ranges from the industry's fastest, at
Sns Tpd to popular 2Sns versions
• Low power consumption with Low Power versions
rated at 7SmA typical and Quarter Power versions
at 4SmA typical
• 8 Powerful Output Logic Macrocells (OLMCs) with
8 Product Terms each
• Standard 20-pin (DIP and PLCC) and 24/28-pin
(DIP/PLCC) packages

The GAL22V10
These GAL products can be segmented into two broad
categories:
Base Products - Aimed at providing a superior design
alternative to the bipolar PLD, these five architectures
replace over 98% of all bipolar PAL devices. The GAL 16V8
and GAL20V8 replace 42 different PAL devices. The
GAL22V10, GAL20RA 10 and GAL20XV1 0 round out the
Base products. These GAL devices meet, and in most
cases beat bipolar PAL performance specifications while
consuming significantly lower power and offering higher
quality and reliability via Lattice's electrically
reprogram mabie E2CMOS technology.
Extension Products - These products build upon the
Base GAL product features to provide enhanced
functionality including innovative architectures
(GAL18V10, GAL26CV12, GAL6001/6002), 64mA high
output drive (GAL 16VP8 & GAL20VP8), "Zero power"
operation (GAL 16V8Z1ZD & GAL20V8Z1ZD) and insystem programmability (ispGAL22V10).

• Available in industry leading Sns/200MHz versions
through 2Sns versions
• Low power consumption with Low Power versions
at 90mA and Quarter Power versions at 4SmA
typical
• 10 OLMCS with variable Product Terms per OLMC
ranging from 8 to 16 for increased logic capability
• Standard 24-pin DIP and 28-pin PLCC packages

The GAL 18V1 0
10 Outputs in a 20-pin Package
• 20-pin space-saving subset of the popular
GAL22V10
• 8-10 Product Terms per OLMC
• Ideal for p.c. board area constrained designs
• Only 10 output, 20-pin PLD in the market

A PRODUCT FOR ANY SYSTEM DESIGN NEED
Lattice GAL products have the performance, architectural features, low power, and high quality to meet the
needs of the most demanding system designs.

The GAL26CV12
Expanded Logic Density in a 28-pin DIP/PLCC
Package
• 28-pin superset of the popular GAL22V1 0
• World's fastest 28-pin PLD at 7.Sns
• 26 inputs, 12 outputs
• Flexible 22V10 OLMC
• Fully utilized 28-pin PLCC package give added
functionality over the 22V1 0 at no space premium!

3-1

•

Introduction to Generic Array Logic
The GAL20RA 10

The GAL 16V8Z1ZD and GAL20V8Z1ZD

High Performance Asynchronous Logic

Zero Stand-by Power

0100LMCs

o

SOIlA Icc typical stand-by power (1001lA MAX)

o

10 Independently programmable clocks

o

12ns Tpd performance

o

Each macrocell has an independent product term
clock

o

Two power-down modes

o

- Input transition detection (Z)

Fast 10ns Tpd performance

- Dedicated power-down pin (ZD)

o

Faster and lower power than bipolar PAL

o

Available in 24/2S-pin DIP/PLCC packages

o

The GAL20XV10

Available in 20-pin DIP/PLCC/SOIC and 24/2S-pin
DIP/PLCC packages

The GAL6001 and GAL6002

Perfect for Fast Counters, Decoders or Comparators

The Logic Density of an FPLA Architecture

o

Utilizes powerful XOR function for efficient
implementation of arithmetic functions

o

Unprecedented logic density in a 24/2S-pin
DIP/PLCC

o

Replaces: PAL20L10, 20X10, 20XS and 20X4,
12L10

o

Functional equivalent of 2 GAL22V1 Os

o

3S Macrocells

01 Onsl1 OOMHz performance significantly outperforms
bipolar PALs
o

o

Perfect for video, multimedia and graphics
applications
Available in 24/2S-pin DIP/PLCC packages

o

High output drive versions of the GAL16VS and
GAL20VS
10L =64mA vs standard 24mA
Combines GAL architecture with high drive of
74XX244 buffer families

o

Fast 1SnslSOMHz performance

o

Available in 20-pin DIP/PLCC
DIP/PLCC packages

10 Output Macrocells

o

10 I/O Macrocells

o

S Buried Logic Macrocells

o

1Snsl7SMHz performance

o

Ideal for register-intensive applications

Offers In-System Programmability

Ideal for Bus Interface or Memory Control Logic

o

10 Input Macrocells

o

The ispGAL22V10

The GAL 16VP8 and GAL20VP8

o

o

and 24/2S-pin

3-2

o

Popular 22V10 architecture

o

In-system programmable

o

Same 2S-pin PLCC as GAL22V10

o

Fast 7.Snsl111 MHz performance

o

Unprecedented design and manufacturing flexibility

Introduction to Generic Array Logic
Commercial/Industrial/Military Grades Available
The Lattice GAL family is available in a wide range of
commercial, industrial and military Grade versions. In
the military arena, Lattice offers a MIL-STD-883 family as
well as a family of Standard Military Drawing (SMD)
devices.
The following table summarizes the Lattice GAL product
offering.

Table 1. Lattice GAL Product Offering
Speed Options by Grade (Tpd in ns)
Commercial

Industrial

8831 Military

5,7.5,10,15,25

7.5,10,15,25

10,15,20,30

GAL16V8 Quarter Power

15,25

20,25

GAL16V8Z1ZD Zero Power

12, 15

-

-

GAL16VP8

15,25

-

-

GAL18V10

15,20

-

-

10,15,20,30

20

-

5,7.5, 10, 15,25

10,15,25

GAL20V8 Quarter Power

15,25

20,25

-

GAL20V8ZlZD Zero Power

12,15

-

GAL20VP8

15,25

-

-

GAL20XV10

10,15,20

-

-

GAL16V8 Low Power

GAL20RA10
GAL20V8 Low Power

GAL22V10 Low Power

-

10,15,20

15,20,25,30

5,6,7.5,10,15,25

10,15,20,25

15,25

-

-

ispGAL22V10

7.5,10,15

-

-

GAL26CV12

7.5,10,15,20

GAL22V10 Quarter Power

10,15,20

-

GAL6001

30

-

-

GAL6002

15,20

-

-

Vcc
Temperature
Packaging

5V±5%

5V±10%

5V±10%

Oto 75°C

-40 to 85°C

-55 to 125°C

Plastic DIP, PLCC
&SOIC

Plastic DIP & PLCC

CERDIP&LCC

3-3

•

Notes

3-4

GAL16V8
High Performance E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- 5 ns Maximum Propagation Delay
- Fmax 166 MHz
- 4 ns Maximum from Clock Input to Data Output
- UltraMOS· Advanced CMOS Technology

I/CLK

=

--1>-----------.,.---,

1/0/0

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc on Low Power Device
- 45mA Typ Icc on Quarter Power Device

1/0/0

• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

vOla

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 20-pin PAL· Devices with Full FunctionlFuse Map/Parametric Compatibility

vOla

1/0/0

vOla

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability

vOla

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

vOla
1/0E

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION

PIN CONFIGURATION

The GAL16V8C, at 5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed
perfonnance available in the PLD market. High speed erase times
«100ms) allow the devices to be reprogrammed quickly and efficiently.

DIP
PLCC

I/CLK

Vee
IIOIQ

~

I

~K~

I(!l!p

,.

20

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL 16V8 are the PAL architectures
listed in the table of the macrocell description section. GAL 16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.

I[ •
I[

,.

GAL16V8

I[ •

Top View

IIOIQ
IIOIQ

VO/Q
IIOIQ

IIOIQ
IIOIQ

I[

I[ 8 9

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL· products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

IIOIQ
IIOIQ

I

GND

"

11

13

IIOE IJOIQ

IfOIQ

VOIQ

IIOIQ

VO/Q

IIOIQ

GND

vOe

Copyright C 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and Information herein are
subject to change without notice.

LATIICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-5

1994 Data Book

~

Specifications GAL 16V8

••••••
••••••
••••••
GAL 16V8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

5

3

4

115

7.5

7

5

10

15

25

10

7

12

10

15

12

Ordering #

Package

GAL16VSC-5LP

20-Pin Plastic DIP

115

GAL 16VSC-5W

20-Lead PLCC

115

GAL16VSB-7LP

20-Pin Plastic DIP

115

GAL16VSB-7W

20-Lead PLCC

115

GAL16VSB-10LP

20-Pin Plastic DIP

115

GAL 16VSB-1 OW

20-Lead PLCC

55

GAL16VSB-15QP

20-Pin Plastic DIP

55

GAL16VSB-15QJ

20-Lead PLCC

00

GAL16VSB-15LP

20-Pin Plastic DIP

00

GAL 16VSB-15LJ

20-Lead PLCC

55

GAL16VSB-25QP

20-Pin Plastic DIP

55

GAL16VSB-25QJ

20-Lead PLCC

00

GAL16VSB-25LP

20-Pin Plastic DIP

00

GAL16VSB-25W

2Q-Lead PLCC

Industrial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

7.5

7

5

130

GAL16VSC-7LPI

20-Pin Plastic DIP

130

GAL16VSC-7WI

20-Lead PLCC

10

10

7

130

GAL16VSB-1 OLPI

20-Pin Plastic DIP

130

GAL16VSB-1 OWl

20-Lead PLCC

130

GAL16VSB-15LPI

20-Pin Plastic DIP

130

GAL 16VSB-15WI

2Q-Lead PLCC

65

GAL16VSB-20QPI

20-Pin Plastic DIP

65

GAL16VSB-20QJI

20-Lead PLCC

65

GAL16VSB-25QPI

20-Pin Plastic DIP

65

GAL16VSB-25QJI

20-Lead PLCC

130

GAL16VSB-25LPI

20-Pin Plastic DIP

130

GAL16VSB-25WI

20-Lead PLCC

15

aJ

25

12

13

15

10

11

12

Ordering #

Package

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL16VSC
GAL16VSB

X

~-~
Speed (ns)

L = Low Power
Q = Quarter Power

Power - - - - - - - - - '

3-6

X X

L

Grade

Blank = Commercial
I = Industrial

' - - - - - - Package P = Plastic DIP
J=PLCC

1994 Data Book

Specifications GAL 16V8

·......
.....
••••••
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development softwarelhardware and is completely
transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes are illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL16V8 . The information given on these architecture bits is
only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.

PAL Architectures
Emulated by GALl6V8

GAl16V8
Global OlMC Mode

l6R8
l6R6
l6R4
16RP8
l6RP6
l6RP4

Registered
Registered
Registered
Registered
Registered
Registered

l6l8
l6H8
l6P8

Complex
Complex
Complex

1018
l2l6
l4l4
l6l2
10H8
l2H6
l4H4
l6H2
10P8
l2P6
l4P4
l6P2

Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple

COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table
can be used to override the automatic device selection by the
software. For further details, refer to the compiler software
manuals.

In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.

ABEL
CUPL
LOG/IC
OrCAD-PLD
PLDesigner
TANGO-PLD

Registered

Complex

Simple

Auto Mode Select

P16V8R
G16V8MS
GAL16V8 R
"Registered'"
P16V8R2
G16V8R

P16V8C
G16V8MA
GAL16V8 C7
"Complex'"
P16V8C2
G16V8C

P16V8AS
G16V8AS
GAL16V8 C8
"Simple'"
P16V8C2
G16V8AS3

P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8

1) Used wi1h Configuration keyword.
2) Priorto Version 2.0 support.
3) Supported on Version 1.20 or later.

3-7

1994 Data Book

•

~~~Latticem

Specifications GAL 16V8

••••••

••••••
••••••
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as 1/0 functions.

mode. Dedicated input or output functions can be implemented
as subsets of the 1/0 function.

Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, 1/0 and register placement.

Registered outputs have eight product terms per output. 110's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
1/0. Up to eight registers or up to eight 1I0's are possible in this

elK

Registered Configuration for Registered Mode

·SYN=O.
• ACO=1.
• XOR=O defines Active low Output.
• XOR=1 defines Active High Output.
• AC1 =0 defines this output configuration.
• Pin 1 controls common ClK for the registered outputs.
• Pin 11 controls common OE for the registered outputs.
• Pin 1 & Pin 11 are permanently configured as ClK &
OE.

OE

Combinatorial Configuration for Registered Mode

·SYN=O.
• ACO=1.
• XOR=O defines Active low Output.
• XOR=1 defines Active High Output.
• AC1 =1 defines this output configuration.
• Pin 1 & Pin 11 are permanently configured as ClK &
OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3·8

1994 Data Book

Specifications GAL 16V8

·......
.....
••••••
REGISTERED MODE LOGIC DIAGRAM

DIP & PLCC Package Pinouts

-I'::
0

• ,

12

16

20

24

2B

0000

0224

J

PTO

§:
~

OLMC 19

0-

~

OLMC 18

~

OLMC 17

=-

~

OLMC 16

g:

OLMC 15

XOR-2048
ACl-2120

D
0256

0480

XOR-2049
ACl-2121

Lr0512

0736

XOR-2050
ACl-2122

:r

19
i

~=

18

~D

17

lj

16

~
I

0768

0992

XOR·2051
AC1·2123

r>102.

8=

1248

XOR·2052
AC1·2124

D
1280

~

OLMC 14

t}-

1504

XOR·2053
AC1·2125

D
1536

§:

g:

1760

OLMC 13
XOR·2054
AC1·2126

D
1792
-D-

~

2016

OLMC 12

~

0

XOR-2055
AC1·2127

:r
~=
:r
:r

15

14

13

12

d

2191

OE-CJ 11

64-USER ELECTRONIC SIGNATURE FUSES

2056,2067, ....
8\'1978\'196 ..

.... 2118, 2119
.... 8\'191 8\'190

SYN·2192
ACO·2193

M L
S

S

8

8

3-9

1994 Data Book

~HLatticem
••••••

Specifications GAL 16V8

••••••
••••••

COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.

pability. Designs requiring eight 1I0's can be implemented in the
Registered mode.

Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.

Up to six 1I0's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the 1/0 function. The
two outer most macrocells (pins 12 & 19) do not have input ca-

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial 110 Configuration for Complex Mode

- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Fin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Pin 12 and Pin 19 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-10

1994 Data Book

~~~Lattice~

Specifications GAL 16V8

••••••
••••••
••••••

COMPLEX MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1D---1>
0

•

8

12

16

20

24

28

D~

PTO

0000

~~

022'

D

l

OLUe 19

0256

§::::::: OLUe 18

13=

0480

D

D

~~

OLUe 17

~~

OLMe 16

D102'

B=
13=

1248

D
1280

B=
13=

1504

D
1536

B=
~

1760
~

1792

=-

~~

2016
~

r

n
v

n
v

XOR-2050
AC1-2122

0768

0992

v

XOR-2049
AC1-2121

0512

0736

n

XOR-2048
AC1-2120

XOR-2051
AC1-2123

OLMe 15
XOR-2052
AC1-2124

OLUe 14
XOR-2053
AC1-2125

OLue 13
XOR-2054
AC1-2126

OLue 12

-D
J

18

17

J

n J-D
v

n J-D
v

n J-D
v

eLI<=>
h

19

or--"

16

15

14

13

12

XOR-2055
AC1-2127

CJ 11

l

2191

64-USER ELECTRONIC SIGNATURE FUSES

12056, 2057, ....
Byte 71 Byte 6 ....
M L
S S

.... 2118, 21191
.... Byte '1 Byte 0

SYN-2192
ACO-2193

B B

3-11

1994 Data Book

Specifications GAL 16V8

••••••
••••••
••••••
SIMPLE MODE

Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to
the common 1Ol8 and 12P6 devices with many permutations of
generic output polarity or input choices.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has programmable polarity.

Combinatorial Output with Feedback Configuration
for Simple Mode

Vee

o

-SYN=1.
-ACO=O.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode
Vee

o

- SYN=1.
-ACO=O.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode
-SYN=1.
-ACO=O.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-12

1994 Data Book

~~~Latticem

Specifications GAL 16V8

••••••
••••••
••••••

SIMPLE MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts

D

"v
4

0

8

12

0000

D

" '" " '" ~J:

"'"

~

"'"

:B==

OLMC 19
XOR-2048
AC1-2120

n
v

-D 19

..
,

0480

OLMC 18

~

XOR-2049
AC1-2121

~

OLMC 17

~

OLMC 16

~

OLMC 15

11
v

~
~

18

D0512

0736

D
0768

0992

'024
1248

D
1200

:8=
D

'504
'538

D1792

~

XOR-2052
AC1-2124

OLMC 14
XOR-2053
AC1-2125

OLMC 13

-6-

OLMC 12

£=

"'''

XOR-2051
AC1-2123

~

=--

'760

XOR-2050
AC1-2122

XOR-2054
AC1-2126

XOR-2055
AC1-2127

r

n
v

II
v

-D 17

~
~

16

n

15

II

-D 14

n

13

II

-D 12

v

v

11

2191

64-USER ELECTRONIC SIGNATURE FUSES
1

2056,2057, ""
Byt&7iByte6 ""

M

... _2118, 2119
.... ByI91iByt&O

1

SYN-2192
ACO-2193

L

S S
B B

3-13

1994 Data Book

~~~Latticem

Specifications GAL 16VBC

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

AmbientTemperature (TA) ............................... 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:
Ambient Temperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

Vss-O.5

-

0.8

V

VIL

Input Low Voltage

VIH

Input High Voltage

2.0

-

Vcc+1

V

IIL1

Input or I/O Low Leakage Current

OV';;; VIN ,;;; VIL (MAX.)

-

IiH

Input or I/O High Leakage Current

3.5V ,;;; VIN ,;;; Vee

-

-

-100
10

!LA
!LA

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

10H = MAX. Yin = VIL or VIH

2.4

-

-

10L

Low Level Output Current

-

-

16

rnA

10H

High Level Output Current

-

-

-3.2

rnA

los2

Output Short Circuit Current

-30

-

-150

mA

Vee=5V

VouT=0.5V

TA=25°C

V

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

INDUSTRIAL
Operating Power

VIL = 0.5V

VIH = 3.0V

Supply Current

ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull·up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25°C

3-14

1994 Data Book

......
••••••

Specifications GAL 16V8C

••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

TEST
COND'.

COM

INO

-5

·7

DESCRIPTION

MIN. MAX. MIN. MAX.

UNITS

tpd

A

Input or 1/0 to Combinational Output

1

5

1

7.5

ns

tco

A

Clock to Output Delay

1

4

1

5

ns

tet·

-

Clock to Feedback Delay

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

A

-

3

-

3

ns

3

-

7

ns

0

142.8

-

-

83.3

-

MHz

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

166

-

100

-

MHz

A

Maximum Clock Frequency with
No Feedback

166

-

100

-

MHz

Clock Pulse Duration, High

3

-

5

-

ns

twl

-

Clock Pulse Duration, Low

3

-

5

-

ns

ten

B

Input or 1/0 to Output Enabled

1

6

1

9

ns

B

OE to Output Enabled

1

6

1

6

ns

C

Input or VO to Output Disabled

1

5

1

9

ns

C

OE to Output Disabled

1

5

1

6

ns

tsu
th

fmax'

twh

tdis

Setup Time, Input or Feedback before Clock"!'
Hold Time, Input or Feedback after Clock"!'

0

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these
parameters.

CAPACITANCE (TA

=25

C, f

=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

CI

Input Capacitance

8

pF

ClIO

1/0 Capacitance

8

pF

TEST CONDITIONS

=5.0V, VI =2.0V
=5.0V, VIIO =2.0V

VCG
VCG

"Guaranteed but not 100% tested.

3·15

1994 Data Book

I

.-

......
......
......

Specifications GAL 16V8B
RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(1)

Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Industrial Devices:
Ambient Temperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

MIN.

CONDITION

VIL

Input Low Voltage

VIH

Input High Voltage

IlL'

Input or I/O Low Leakage Current

OV ~ VIN

IIH

Input or I/O High Leakage Current

3.5V

VOL

Output Low Voltage

VOH

Output High Voltage

TVP.'

MAX.

UNITS

Vss-O.5

-

0.8

V

2.0

V

-

-

Vcc+1

VIL (MAX.)

-100

IlA

~

-

-

10

IlA

10L = MAX. Yin = VIL or VIH

-

-

0.5

V

10H = MAX. Yin = VIL or VIH

~

~

VIN

Vee

2.4

-

-

10L

Low Level Output Current

-

-

24

mA

10H

High Level Output Current

-

-

-3.2

mA

los2

Output Short Circuit Current

-

-150

mA

Vee = 5V

VauT=0.5V

T A=25°C

-30

V

COMMERCIAL
Icc

Operating Power

VIL= 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

-

75

115

mA

L -15/-25

75

90

mA

Q -15/-25

-

45

55

mA

L -7/-10

VIH= 3.0V

INDUSTRIAL
Operating Power

VIL = 0.5V

VIH = 3.0V

Supply Current

ftogglo = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but nat 100% tested.
3) Typical values are at Vee = 5V and TA = 25°C

3-16

1994 Data Book

Specifications GAL 16V8B

• •••••
......
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAM.

TEST
CONO'.

A

tpd

COM

COMIINO

COMIINO

INO

COM/INO

-7

-10

-15

-20

-25

DESCRIPTION

UNITS
MIN.

Input or I/O to

18 outputs switching

3

Comb. Output

11 output switching

-

MAX. MIN.

MAX. MIN.

MAX. MIN.

MAX. MIN.

MAX.

3

10

3

15

3

20

3

25

ns

7

-

-

-

-

-

-

-

-

ns

7.5

tco

A

Clock to Output Delay

2

5

2

7

2

10

2

11

2

12

ns

tcf2

-

Clock to Feedback Delay

-

3

-

6

-

8

-

9

-

10

ns

tsu

-

Setup Time, Input or Fdbk before Clki

7

-

10

-

12

-

13

-

15

-

ns

th

-

Hold Time, Input or Fdbk after Clki

0

-

0

-

0

-

0

-

0

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

83.3

-

58.8

-

45.5

-

41.6

-

37

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

100

-

62.5

-

50

-

45.4

-

40

-

MHz

A

Maximum Clock Frequency with
No Feedback

100

-

62.5

-

62.5

-

50

-

41.6

-

MHz

twh

-

Clock Pulse Duration, High

5

8

-

8

-

10

-

12

-

ns

twl

-

Clock Pulse Duration, Low

5

-

8

-

8

-

10

-

12

-

ns

ten

B

Input or I/O to Output Enabled

3

9

3

10

-

15

ns

OE to Output Enabled

2

6

2

10

-

15

-

25

B

-

20

20

ns

2

9

2

10

-

15

ns

1.5

10

-

15

-

25

6

-

20

1.5

20

ns

fmax 3

tdis

C

Input or I/O to Output Disabled

C

OE to Output Disabled

..

18

18

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

C,

Input Capacitance

8

pF

CI/O

I/O Capacitance

8

pF

TEST CONDITIONS
Vee = 5.0V, V,
Vee

= 2.0V
= 5.0V, VI/O =2.0V

"Guaranteed but not 100% tested.

3-17

II
I

1) Refer to SWItching Test CondItIons section .
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (TA

I

1994 Data Book

H~Latticem

Specifications GAL 16V8

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or
I/O FEEDBACK

CLK
REGISTERED
OUTPUT

Combinatorial Output

INPUT or
I/O FEEDBACK

Registered Output

----r-=r--~

OE

_---1~td~]~
ten~

COMBINATIONAL
OUTPUT

_

~

REGISTERED
OUTPUT

Input or VO to Output Enable/Disable

ax

=wm

--{Ok] l,,"~

OE to Output EnableJDisable

1:1-

~IOIII-I----ltfmaxfbI ~
(w/o

Clock Width
fmax with Feedback

3-18

1994 Data Book

~~~Latticem

Specifications GAL 16VB

••••••
••••••
••••••

fmax DESCRIPTIONS
ClK

··.... ----------------------_ ......---- ------------....
lOGIC

ClK

REGISTER

ARRAY

I

·... _-_ .... _-_ ... _-_..... --_._----_. __ .. _-_ ..............
lOll

.1411

tBU

..
I

tco~

fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feecllack is calculated from measured
tsu and tco.

r

· - - - t c l - - - - - - + l .1

1II·.t------tpd-----~.1

ClJ(

r-~,----------:----I

fmax with Internal Feedback lI(tsu+tcf)
Note: tet is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tet 1lfmax - tsu). The
value of tet is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tet + tpd.

=

~·t~;·t~·=:.:::;j···--···----·------.:
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twI). This
is to allow for a clock duty cycle of other than 50%.

SWITCHING TEST CONDITIONS
+5V

GNDto 3.0V

Input Pulse Levels
Input Rise and
Fall Times

I GAL16V8B
I GAL16V8C

2-3ns 10%-90%
1.5ns 10%-90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

TEST POINT

See Figure

c'l

R2

3-state levels are measured 0.5V from steady-state active
level.

=
'ClINCLUDES TEST FIXTURE AND PROBE CAPACITANCE

GAL 16V8B Output Load Conditions (see figure)
Test Condition
A
B

C

Rz

CL

..
..

390(1
390(1
390(1
390(1
390(1

50pF
50pF
50pF
5pF
5pF

200(1
Active High
Active Low
Active High
Active Low

GAL16V8C Output Load Conditions (see figure)

Rl

200(1
200(1

Test Condition
A

B
C

3-19

Rl

R2

CL

..
..

200(1
200(1
200(1
200(1
200(1

50pF
50pF
50pF
5pF
5pF

200(1
Active High
Active Low
Active High
Active Low

200(1
200(1

1994 Data Book

Specifications GAL 16V8

......
......
......
ELECTRONIC SIGNATURE

OUTPUT REGISTER PRELOAD

An electronic signature is provided in every GAL 16V8 device. It
contains 64 bits of reprogram mabie memory that can contain user
defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.

NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum.

SECURITY CELL

GAL 16V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.

A security cell is provided in the GAL 16V8 devices to prevent unauthorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device,
so the original configuration can never be examined once this cell
is programmed. The Electronic Signature is always available to
the user, regardless of the state of this control cell.

INPUT BUFFERS
GAL 16V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar
TTL devices.

LATCH-UP PROTECTION
GAL 16V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.

The GAL16V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logical "1 "). Lattice recommends that all unused inputs and tri-stated
I/O pins be connected to another active input, Vee, or Ground.
Doing this will tend to improve noise immunity and reduce Icc for
the device.

DEVICE PROGRAMMING

Typical Input Pull-up Characteristic
------

GAL devices are programmed using a Lattice-approved LogiC
Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.

~

~

~

=

-20

-------

--~---

~--+_--~~~--~--~--_4

r----r",~~~~-----r----r-----­

-40 ___
~--+----+---~--~--~
.60 "---_ _+-__-+___1--_ _+-__-1

o

1.0

2.0

3.0

4.0

5.0

Input Voltage (Volts)

3-20

1994 Data Book

~HLattice~

Specifications GAL 16V8

••••••
••••••
••••••

POWER-UP RESET
Vee

elK

INTERNAL
REGISTER
OUTPUTQ

Device Pin
~
Reset to Logic "1"

conditions must be met to guarantee a valid power-up reset of the
device. First, the Vcc rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

Circuitry within the GAL 16V8 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1115 MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN

PIN
Feedback 4 - - - - - - '

Vee
Active Pull-up
Circuit

Active PUll-Up
Circuit

..•.....

,

Tri-State
Control

PIN

Vee

_. *

Vref:

Data
Output

Typ. Vref = 3.2V

Typ. Vref

PIN

=3.2V

Feedback
(To Input Buffer)
Typical Output

Typical Input

3-21

1994 Data Book

~~~Latticem
••••••

Specifications GAL 16VB

••••••
••••••

GAL 16V8C-5: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee

~

r-....... i"---

I

-

E

0.8
4.50

5.00

4.75

--

II-PTL->H

~ 0.9

~

1.1

~

I

.~

"iii

o

0.8

--

1.1

~

I

"iii

---PTH->~f

...........

~

--PTL->H

E

~ 0.0

0.8
4.SO

4.75

5.00

0.8
4.SO

5.SO

5.25

4.75

--..... ~
5.SO

6.25

5.00

Supply Voltage (V)

Supply Voltage (V)

Normalized Tpd va Temp

Normalized Teo va Temp

Normalized Tau va Temp

1.3

I..-'"

PTL->H I

I-

"""

ioo"'"
~

1.4

81.2 ~---RISE

~

- - - PTH->L

1

E 0.9

Z

---.

.!

Supply Voltage (V)

I-- 1.1

"5l

I-FALL

~

1.3

"8. 1.2

I---RSE.~

~ 0.9

5.SO

5.25

1.2

1.2

11- - - PTH->L

~,.,

Normalized Tau va Vee

Normalized Teo va Vee

1.2

"5l

1.1

~

1

~

I-"""

L,..,.oo !o"

E 0.9

~

-

~

--FALL

~

~

~

~

~

~;

Temperature (deg_ C)

~

~

~

-0.25

~

-0.5

I- ~

--

jolt'"

-0.75

j..IIo p.-.

.....

.

~8

"8.
S

--PTL->Hl

IL

L

L

IL

V

0 .0

~

0.7

~

~

~
~
~
~
Temperature (deg_ C)

'"
N

~

-0.5

~~

,ll!

2l

-0.75

.. ;. V'"

- - - RISEl
--FALL

-I

Number 01 OUtputs SWitching

Number 01 OUtputs SWitching

Delta Tpd va Output Loading

Delta Teo va Output Loading

~- -

- RISE I

--FALL
4

I

~.

2
0

I

.. . ' ~

-0.25

--FALL

l-

~

"iii

=

~

E

-I

.s

1.1

l

Delta Teo va # of Outputs
Switching

---RISE.~

S

~

~

- - - PTH->L

Temperature (deg. C)
Delta Tpd va # of Outputs
SWitching

E

1.2

Z 0.8

0.7

~;

{!!.

8

o

Z 0.8

0.7

1.3

:::J

V

./

.
- :-:-:
~

---

~8

8

100

150

200

250

RISE

~
'"
~

-FALL

..

4

I-

..

,ll!

2

C

0
-2

50

i---

Output Loading (pF)

-'"

~.

~
o

300

-- -

SO

100

150

200

250

300

OUtput Loading (pF)

3-22

1994 Data Book

Specifications GAL 16V8

••••••
......
......

I
I
I

GAL 16V8C-5: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

I·

Voh va loh

Voh valoh

Vol va 101

4.25

1.5

./

0.5

/'

V

~

~

3

...........

.s::.

~ 2

20.00

40.00

60.00

0.00

80.00

10.00

20.00

3.5

+---+--+---7I1""---i

--g
t---+-""""':lI,I(iC---+----1

~ 0.90 +--~:...---+---+-----l

r-....... .....

1.00

1.2

'i

1.1

o

Z

.....

.........

0.9

·55

·25

"'"

0

25

50

75

-

0.00 0.50 1.00 1.SO 2.00 2.50 3.00 3.SO 4.00

J!

1.30

~

1.20

'iii

1.10

E
o 1.00

r-.

100

125

Z

0.90

./
~

/

./
./

0.80
25

50

75

100

Frequency (MHz)

Input Clamp (Vik)

~

15

/'

~

30

/

~ 20
-25

......

...... ........

0.8

10

~

~

1

Delta Icc va Vin (1 input)

I

4.00

3.00

Normalized Icc vs Freq.

Temperature (deg. C)

,...

2.00

loh(mA)

i'

.!::!

~

r--.

1.SO

Supply Voltage (V)

Vin (V)

SO.OO

.........

1.40

J!

0.80 ~---I---+----I-----l
4.SO
5.00
5.25
5.50
4.75

/

40.00

3.25
0.00

1.3

1.20 . , - - - , . - - , - - - , . - - - ,

~

r..........

Normalized Icc va Temp

Normalized Icc va Vee

1.00

30.00

~

loh(mA)

101 (mA)

.!::!

...........

3.75

~

o

0.00

1.10

.s::.

~

V

J!

~

r........

35

I
I

I

40
45
·2.00

·l.SO

·1.00

·O.SO

0.00

Vik (V)

3-23

1994 Data Book

~H Latti ce'"
......
......

Specifications GAL 16VB

••••••

GAL 16V8B-7/1 0: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee
1.2
"0
~1.1

-g
.~

1

iii

E

~

~

.

1- - I

~~

Normalized Teo

PTH->L

~

PTL->H

1.1

Supply Voltage (V)

5."
Supply Voltage (V)

Normalized Tpd vs Temp

Normalized Teo vs Temp

5.00

5.50

5.25

- - - PTH~>L

1

EO .•

o
Z

0,8

-

..,. ,.,

~

8

...; ~

--PTL->HI

1.2

1-'-"
~.

.~

1

iii

EO'.
o

z

0.•
4.SO

- - - RISE

~--FALL

.....
~~

--

"
{!!.
"0

~

..,

1--

.l!l

~

- - - PTH->L

1.2

--PTL->H

~

1.:

§

0 .•

z

0 .•

... t,.iiP""

/
..
--

..

o
o

- - - RISE

.
N

Temperature (deg. C)

Delta Teo vs # of Outputs
Switching

~

V

!..t'-

o

:;;. ;..::;- iI""'"
--.,..

-1.5

/

/

",

Temperature (deg. C)

Delta Tpd vs # of Outputs
Switching

-1

1.3

~

Temperature (deg. C)

.-

5.50

Normalized Tsu vs Temp

0.7

~

~-O.S

5.25

5.00

1.4

0.7

~

4.75

Supply Voltage (V)

0 .•

0.7

1

PT L->H

~ 0,9

5.60

5.00

4.75

•.SO

r-:.:.:. =-=-

E

1.3

L
1.1

i

.- -. -

E

1.3

.~

"

{!!.

FALL

~ 0.9

4.50

~

1-I -- Rlse.~

... -.

1

iii

.-~

0 .•

"-

Normalized Tsu vs Vec

Vee
1.2

1.1

~

.~

~ 0.9

"0 1.2

VB

1.2

/

~

,., :,;.. ~
..., ~.--

.....

---RISE~

--FALL

FALL
-2

-2

Number of Outputs Switching

Number of Outputs Switching

Delta Teo vs Output Loading

Delta Tpd vs Output Loading
10

10

~-

- - RISE

I
,,~-

."

./

~---RISEI

/"

--FALL I

FALL

~-

~

...

-2

-2
50

100

150

200

I

250

.--

~
50

300

...

~

V

-

...-:.

~

100

1 so

200

250

300

Output Loading (pF)

Output Loading (pF)

3-24

1994 Data Book

Specifications GAL 16V8

......
••••••
••••••

GAL 16V8B-7/10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh valoh

Voh vsloh

Vol va 101

4.5

/

0.75

:::" 0.5

g

0.25

~

........ ........

V

:;-

V

-

20.00

40.00

eo.OO

BO.OO

0.00

100.00

E

~ 0.90

"-

3.S
0.00

10.00 20.00 30.00 40.00 50.00 eo.OO

~

-----

..,."..

il

".,

1.1

"5l

1

r-....

1

~ 0.9

5.00

5.25

-55

5.50

-25

Della Icc va Vln (1 Input)

«'

.s

\

Jll 2
iii

J\

,

I

~

......

"-

"""

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

4.00

"

........

0

1.20

"5l

1.10

~

§ 1.00

........

o

.........

25

il

50

75

Z

........

100

125

0.90

/

-,,"

~

V

0.80
25

50

75

100

Frequency (MHz)

Input Clamp (Vile)

«"

il

3.00

Normalized Icc va Freq.

Temperature (deg. C)

Supply Voltage (V)

.s3

2.00

r--

1.30

.......

0.8
4.75

1.00

--

loh(mA)

1.2

0.80
4.50

0

g

Normalized Icc va Temp

1.20

iii

.r:.

loh(mA)

Normalized Icc va Vee

.~ 1.00

~

r---

3.75

lol(mA)

al

....... r-.

l/~

0.00

~ 1.10

4.2S

10
20
30
40
50
80
70
80
90
100

,
,I

,
I

I

I

-2.00

·1.50

·1.00

-0.50

0.00

Vik(V)

3-25

1994 Data Book

~~~Latticern

Specifications GAL 16V8

••••••
••••••
••••••

GAL 16V8B-15/25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd V8 Vee
1.2

1.2

1.2

11- - - PTH->L

r--- ""'-

:-::-:

II-PTL->H

-

0.8

4.SO

4.76

0.8
4.60

6.60

6.26

6.00

~

- ---

4.76

6.00

1
~

~

o

0.8

-

81.2 ~---

. .,;;.-

I"-

11 1.1

:.... ~

'Ii

.

1

EU
o

~

RISE
FALL

;,;

.,.

......
~

..

".

~

·25

so 75 100
Temperature (deg. C)
0

26

~

Z

-26

0

26

50

76

100

Delta TpcI V8 II of Outputs
Switching

E

-0.5

~

-1

~ -1.6

6.25

5.50

-PTL->H,

l.,..oo"

1

--'

~

0.9
0.8

".

",
066

126

-26

RISE.~

---

0

26

60

76

100

126

Temperature (deg. C)

Dalta Teo vs II of Outputs
Switching

- - ,.._. ,.. -1/.. -'"

", ~

,Il!

- - - PTH->ll

1.2

Temperature (deg. C)

~-

~-

0.7

·66

125

6.00

1.3

jl.l

1iI

0.7
-65

~

Normalized Tau va Tamp

~

Z 0.8

0.7

4.76

PTL-.H

1.4

1.3

PTL-.H

~

Supply Voltags (V)

Normalized Teo V8 Temp

I- 1.1

- .. - PTH-.L

0.8
4.60

6.60

6.26

Normalized TpcI va Temp

---PTH-.L

EO."

"-

I-FAll.

Supply Voltage (V)

1.3

Z

I---R~~

Supply Voltage (V)

XU

~

Normalized Tau va Vee

Normalized Teo V8 Vee

-FALL

- - -" ,..-- -- ,..

:[.0.6
~

-1

~

-1.5

,

..".

./

V

L

~

- - - RISE.
FALL

-2

2

6

Number of Outputs Swilching

Number of Outputs Switching

Dalta TpcI vs Output Loading

Delta Teo va Output Loading
12

12

.

10

:[
X
I- •

--FALL,

,Il!
~

2
-2

10

r--RISEI

~

L

--

./

--'

...

~
.!I

. / ...

;!I

150

200

260

300

OUtput Loading (pF)

3-26

,

RISE I

--FALL

I

8

2
-2

100

t--

~

o

."
60

:[.

'"'"

o

60

""-"

100

".

...

V... ... ...

160

200

260

..

300

Output Loading (pF)

1994 Data Book

~~~Latticem

Specifications GAL 16VB

••••••
••••••
••••••

GAL 16V8B-15/25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh valoh

Vohvaloh

Vol va 101

4.25

1.5

I; ~
I".;

0.5

~

"

......

~i""'"

20.00

40.00

eo.DO

BO.oo

0.00

100.00

10.00 20.00 30.00 40.00 SO.OO eo.OO

..""

0.80
4.50

~

V

J!

1.1

i=

1

~

.......

i8

5.25

5.50

\

-55

....... ....... ....

IJ

Z

0.00 o.so 1.00 1.50 2.00 2.50 3.00 3.50 4.00

VlnM

1.00
0.90

~

./

..""

l/""""

-25

a

25

so

75

100

125

25

so

75

100

Frequency (MHz)

Input Clamp (Vile)

~

r""'- .......

~

01

8

Temperature (
3.25

IOI(mA)

~~

....... ........

I--" ~

0.00

J!
~

~
-8
3.75

i""'-- ....

0
10
20
30
40

~

1
I

I

SO

80
70
80
90
100
-2.00

I
I

L

L
-1.50

-1.00

-0.50

0.00

Vlk (V)

3-27

1994 Data Book

~~~Lattice'M
.....•
......
......

Notes

3-28

1994 Data Book

GAL16V8Z
GAL 16V8ZD

••••••
••••••

••••••

Zero Power E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM

FEATURES

• ZERO POWER E"CMOS TECHNOLOGY
-100~ Standby Current
- Input Transition Detection on GAL16V8Z
- Dedicated Power-down Pin on GAL16V8ZD
- Input and Output Latching During Power Down

VCLK

1/010

• HIGH PERFORMANCE E"CMOS TECHNOLOGY
-12 ns Maximum Propagation Delay
- Fmax = 83.3 MHz
- 8 ns Maximum from Clock Input to Data Output
- TTL Compatible 16 mA Output Drive
- UltraMOse Advanced CMOS Technology

1/010

1/010
IIDPP

• E" CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogramrnable Cells
-100% Tested/Guaranteed 1oo'Y. Vields
- High Speed Electrical Erasure «100ms)
- 20 Vear Data Retention

1/010

1/010

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Architecturally Similar to Standard GAL 16V8

1/010

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100'Y. Functional Testability

1/010

• APPLICATIONS INCLUDE:
- Battery Powered Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing

1/010
ItOE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION

The GAL16Vaz and GAL16V8ZD, at 100 J.lA standby current and
12ns propagation delay provides the highest speed and lowest
power cormination PLD available in the market. The GAL 16V8ZJ
ZD is manufactured using Lallice's advanced zero power PCMOS
process, which combines CMOS with Electrically Erasable (E2)
floating gate technology.

PIN CONFIGURATION

DIPISOIC

Chip Carrier
Vee

The GAL16V8Z uses Input Transition Detection (lTD) to put the
device in standby mode and is capable of emulating the full functionality of the standard GAL 16V8. The GAL 16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby
mode. It has 15 inputs available to the AND array.

.....
3

1

19

IroPP 14

GAL16V8Z

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

6

I/O/a

18p 1/010

I/DPP

I/O/a

P1/010
16 P1/010

GAL16V8ZD
Top View

I/O/a
I/O/a

p I/O/Q
8

- - -9

11

I/O/a

1314 P1/010

............
--"':':"""_ _...:...:.J_

1/OE

Copyright C 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to chango without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-29

1994 Data Book

I

~

Specifications GAL 16VBZ
GAL 16VBZD

••••••
••••••
••••••
GAL 16VSZlZD ORDERING INFORMATION
GAL16V8Z: Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

Isb (J.1A)

12

10

8

!Xi

100

GAL16V8Z-12QP

20-Pin Plastic DIP

!Xi

100

GAL 16V8Z-12QJ

20-Lead PLCC

!Xi

100

GAL 16V8Z-12QS

2Cl-LeadSOIC

!Xi

100

GAL 16VSZ-15QP

20-Pin Plastic DIP

!Xi

100

GAL16V8Z-15QJ

2Cl-Lead PLCC

!Xi

100

GAL16V8Z-15QS

2Cl-LeadSOIC

15

15

10

Ordering #

Package

GAL 16V8ZD: Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

Isb (J.1A)

12

10

8

!Xi

100

GAL16V8ZD-12QP

Ordering #

20-Pin Plastic DIP

Package

!Xi

100

GAL16V8ZD-12QJ

20-Lead PLCC

15

15

10

!Xi

100

GAL16V8ZD-15QP

20-Pin Plastic DIP

!Xi

100

GAL16V8ZD-15QJ

20-Lead PLCC

PART NUMBER DESCRIPTION
XXXXXXXX -

~ce_~

xx

X

X X

II

GAL 16V8Z (Zero Power lTD)
GAL 16V8ZD (Zero Power DPP)

Speed (ns) _ _ _ _ _ _-1
Active Power _ _ _ _ _ _ _ _----1
Q = Quarter Power

3-30

G~:k ~m~m;.,
=

Package
P = Plastic DIP
J = PLCC
S =SOIC

1994 Data Book

Specifications GAL 16V8Z
GAL 16V8ZD

......
......
••••••
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.

XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the inpuVoutput configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL16V8ZJZD. The information given on these architecture bits
is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The

COMPILER SUPPORT FOR OLMC
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.

Software compilers support the three different global OLMC
modes as different device types. Most compilers also have the
ability to automatically select the device type, generally based on
the register usage and output enable (OE) usage. Register usage
on the device forces the software to choose the registered mode.
All combinatorial outputs with OE controlled by the product term
will force the software to choose the complex mode. The software
will choose the simple mode only when all outputs are dedicated
combinatorial without OE control. For further details, refer to the
compiler software manuals.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In dOing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using the standard GAL 16V8 JEDEC fuse pattern generated by the logic compilers for the GAL16V8ZD, special attention
must be given to pin 4 (DPP) to make sure that it is not used as
one of the functional inputs.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.

3-31

1994 Data Book

H~Latticem

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Registered outputs have eight product terms per output. I/O's
have seven product terms per output.

Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.

Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.

eLK

Registered Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- Pin 1 controls common ClK for the registered outputs.
- Pin 11 controls common DE for the registered outputL
- Pin 1 & Pin 11 are permanently configured as ClK & DE.

OE

Combinatorial Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as ClK & DE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-32

1994 Data Book

~~~Lattice'M
......

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••

REGISTERED MODE LOGIC DIAGRAM
DIP, SOIC & PLCC Package Pinouts

-P
0

4

8

12

16

20

24

0000

28

rj2~

• :r

PTO

OLMC 1

0224

19

XOR-2048
ACl-2120

0256

~

8=

0480

D-

OLMC 2

0736

~

• 4 D-

OLMC 3

~

0882

5 D--

OLMC 4

1248

OLMC 5

1280

~

1504

7 D-

OLMC 6
XOR-2053
ACl-2125

1536

OLMC 7

§=

1760

8D

XOR-2054
ACl-2126

1792

~
lli~

2016

I-~

OLMC 8
XOR-2055
ACl-2127

18

17

1

16

1

15

~=

]D

XOR-2052
ACl-2124

6 D-

".......,

~~

XOR-2051
ACl-2123

1024
-[")-

1

XOR-2050
ACl-2122

0768

".......,

~~

XOR-2049
ACl-2121

0512

~

1

1
~
1
~
1
~-

2191

14

13

12

,('lO~ 11

SYN-2192
ACO-2193
• Note: Input not available on GAL16V8ZD

MSB

3-33

1994 Data Book

~~~LatticeT"

Specifications GAL 16VBZ

••••••
••••••
••••••

GAL 16VBZD

COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.

Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.

Pin 4 is used as dedicated power-down pin on GAL 16V8ZD. It
cannot be used as functional input.

Up to six 110's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the 1/0 function. The
two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight 1I0's can be implemented in the
Registered mode.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial 110 Configuration for Complex Mode

-SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

-SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 12 and Pin 19 are configured to this
function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-34

1994 Data Book

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••
COMPLEX MODE LOGIC DIAGRAM

DIP, SOIC & PLCC Package Pinouts

D-

-j)
0

4

8

12

16

20

0224

2

24

28

PTO
J8

l.te

0000

~

~

OLMC 1

~

OLMC 2

~

0256

0480

3 D-

XOR-2049
ACI-2121

0512

§:==

E====

0736

•

4

t:l

-0 19

XOR-2048
ACI-2120

OLMC 3
XOR-2050
ACI-2122

Gll'
n-o

LJ

18

17

0768

~

0992

5 D-

OLMC 4
XOR-2051
ACI-2123

1024

~

1248

D

OLMC 5
XOR-2052
ACI-2124

1280

R:=

~

1504

.---..

OLMC 6
XOR-2053
ACI-2125

~

1536

~

1760

~

8

OLMC 7

Cl-

tl

8=

9D

~
~

OLMC 8

16

15

14

~-o 13

XOR-2054
ACI-2126

1792

2016

Q fa

v

~v

J

-D 12

XOR-2055
ACI-2127

CJ 11

2191

SYN-2192
ACO-2193
• Note: Input not available on GAL 16V8ZD

MSB

3-35

1994 Data Book

~~~Lattice~
••••••

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••

SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
in the input configuration.

Architecture configurations available in this mode are similar to
the common 10L8 and 12P6 devices with many permutations of
generic output polarity or input choices.

Pin 4 is used as dedicated power-down pin on GAL 16V8Z0. It
cannot be used as functional input.

All outputs in the simple mode have a maximum of eight porduct
terms that can control the logic. In addition, each output has programmable polarity.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

Vee

o

-SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode
Vee

- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.

a

Dedicated Input Configuration for Simple Mode
- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-36

1994 Data Book

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••
SIMPLE MODE LOGIC DIAGRAM

DIP, SOIC & PLCC Package Pinouts
1

D------I>
0

,

a

12

la

20

24

2a

B

?TO a

0000

022'

~
~

OLMC 1

~

OLMC 2

~

OLMC 3

~

OLMC 4

~

OLMC 5

~

OLMC 6

~

OLMC 7

XOR-2048
AC1-2120

~

-D 19

~

-D 18

v

D0256

O4ao

00512

~

0736

XOR-2049
AC1-2121

XOR-2050
AC1-2122

=l f-a

17

* 4 00768

~

0992

XOR-2051
AC1-2123

~

-D 16

=l

-D 15

n

-D 14

5 D102'

1248

6D
1280

1504

7

~

XOR-2052
AC1-2124

XOR-2053
AC1-2125

v

~

1536

~

1760

XOR-2054
AC1-2126

~Lo

13

D-1792

2016

0-

f-

~~

OLMC 8
XOR-2055
AC1-2127

n
v

or-<>
~

12

CJ 11

Ir
2191

SYN-2192
ACO-2193
MSB

* Note: Input not available on GAL16V8ZD

3-37

1994 Data Book

~~~Latticem

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo

Supply voltage Vee ......................................... -.5 to + 7V

Commercial Devices:

Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP}

MAX.

UNITS

0.8

V

Vcc+1

V

-10

~

10

~

IlL

Input or I/O Low Leakage Current

OV S VIN S VIL (MAX.)

-

IIH

Input or I/O High Leakage Current

3.5V S VIN S Vee

-

-

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

10H = MAX. Yin = VIL orVIH

2.4

-

-

V

-

V

-

-

16

rnA

-

-3.2

rnA

-30

-

-150

rnA

Z-12/-15
ZO-12/-15

-

50

100

~

Z-12/-15
ZO-12/-15

-

-

55

rnA

VIL

Input Low Voltage

Vss-O.5

VIH

Input High Voltage

2.0

10H = -100
10L

~

Yin = VIL orVIH

Low Level Output Current

10H

High Level Output Current

los'

Output Short Circuit Current

Vee = 5V

VouT=0.5V

TA=25°C

Vcc-1

COMMERCIAL
ISB

Stand-by Power
Supply Current

Icc

Operating Power
Supply Current

VIL=GNO

VIH = Vcc Outputs Open

VIL=0.5V VIH= 3.0V
= 15 MHz Outputs Open

Itoggle

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA

=25 cC, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

Cvo

I/O Capacitance

10

pF

Vee = 5.0V, VI/O = 2.0V

'Guaranteed but not 100% tested.

3-38

1994 Data Book

~~~Lattice~
......

Specifications GAL 16V8Z

••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM

COM
PARAMETER

TEST
COND'.

-12

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

tpd

A

Input or I/O to Combinational Output

3

12

3

15

ns

tco

A

Clock to Output Delay

2

8

2

10

ns

tcf2

-

Clock to Feedback Delay

-

6

-

7

ns

tsu

-

Setup Time, Input or Feedback before Clock!

10

-

15

-

ns

th

-

Hold Time, Input or Feedback after Clock!

0

-

0

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

55

-

40

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

62.5

-

45.5

-

MHz

A

Maximum Clock Frequency with
No Feedback

83.3

-

62.5

-

MHz

twh

-

Clock Pulse Duration, High

6

-

8

-

ns

twl

-

Clock Pulse Duration, Low

6

-

8

-

ns

ten

B

Input or I/O to Output Enabled

-

12

-

15

ns

B

OE to Output Enabled

-

12

-

15

ns

fmax 3

C

Input or I/O to Output Disabled

-

15

ns

OE to Output Disabled

-

15

C

12

-

15

ns

tas

-

Last Active Input to Standby

60

140

50

150

ns

tsa4

-

Standby to Active Output

6

13

5

15

ns

tdis

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.

STANDBY POWER TIMING WAVEFORMS
POWER
INPUT 0'
1/0 FEEDBACK

OE

* Note: Rising clock edges
are allowed during tsa but
outputs are not guaranteed.

ClK

OUTPUT

3-39

1994 Data Book

~~~LatticeTM

Specifications GAL 16V8ZD

••••••
••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

TEST
COND'.

COM

COM

-12

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION

A

Input or I/O to Combinational Output

3

12

tco

A

Clock to Output Delay

2

tcf2

Clock to Feedback Delay

tsu

-

Setup Time, Input or Feedback before Clockt

th

-

Hold Time, Input or Feedback after Clockt

0

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

A

UNITS

3

15

ns

8

2

10

ns

-

6

-

7

ns

10

15

ns

0

-

55

-

40

-

MHz

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)

62.5

-

45.5

-

MHz

A

Maximum Clock Frequency with
No Feedback

83.3

-

62.5

-

MHz

Clock Pulse Duration, High

6

-

8

-

ns

twl

-

Clock Pulse Duration, Low

6

-

8

-

ns

ten

B

Input or I/O to Output Enabled

-

12

15

ns

B

OE to Output Enabled

-

12

-

15

ns

-

15

ns

15

ns

tpd

fmax3

twh

tdis

C

Input or I/O to Output Disabled

C

OE to Output Disabled

15
12

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

3-40

1994 Data Book

Specifications GAL 16V8ZD

••••••
......
••••••

DEDICATED POWER-DOWN PIN SPECIFICATIONS
Over Recommended Operating Conditions
COM
PARAMETER

TEST
COND'.

COM

-12

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

twhd

-

DPP Pulse Duration High

12

-

15

-

ns

twld

-

DPP Pulse Duration Low

25

-

30

-

ns

ACTIVE TO STANDBY
tivdh

-

Valid Input before DPP High

5

-

ns

-

Valid OE before DPP High

0

-

8

tgvdh

0

ns

tcvdh

-

Valid Clock Before DPP High

0

-

0

-

ns

tdhix

-

Input Don't Care after DPP High

-

2

-

5

ns

tdhgx

-

OE Don't Care after DPP High

-

6

-

9

ns

tdhcx

-

Clock Don't Care after DPP High

-

8

-

11

ns

STANDBY TO ACTIVE
tdliv

-

DPP Low to Valid Input

12

-

15

-

ns

tdlgv

-

DPP Low to Valid OE

16

-

20

-

ns

tdlcv

-

DPP Low to Valid Clock

18

-

20

-

ns

tdlov

A

DPP Low to Valid Output

5

24

5

30

ns

1) Refer to Switching Test Conditions section.

DEDICATED POWER-DOWN PIN (DPP) TIMING WAVEFORMS
DPP

INPUT or

I/O FEEDBACK
OE

ClK

OUTPUT

3-41

1994 Data Book

~~~Lattice~

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

SWITCHING WAVEFORMS

\\\\\\\\\r

INPUT or
I/O FEEDBACK

\\\\\\

INPUT or
I/O FEEDBACK
VALID INPUT

'~tpd~1

elK

\\~==

COMBINATIONAL
OUTPUT

REGISTERED
OUTPUT

Combinatorial Output

INPUT or
I/O FEEDBACK

-!~--T-~--­

tenl=

Registered Output

~_~tdiS~J~

COMBINATIONAL
OUTPUT

. _

OE

Input or 110 to Output Enable/Dlsable

REGISTERED
OUTPUT

--{~J L0l=

OE to Output Enable/Disable

=

r"'t:~
~f04-f---1Ifmax ~
(w/ofb)

Clock Width

fmax with Feedback

3-42

1994 Data Book

Specifications GAL 16VBZ
GAL 16VBZD

••••••
••••••
••••••
fmax SPECIFICATIONS
ClK

lOGIC
ARRAY

REGISTER

CLK

._---- . --_ .. _----------_ .. _..... _......... __ .. __ ...............
lioIII.,..I----tsu ---1.*,1""1--- tco~
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.

ttII~----tcf-----'.~1

1oI~1------tpd-----~~1
CLK

f··········--··-----··········--·· -.. ------ .. --:

fmax with Internal Feedback 1/(tsu+tcf)
Note: tef is a calculated value, derived by subtracting tsu from
the period of fmax wlinternal feedback (tel = l/fmax - tsu). The
value of tel is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tel + tpd.

LOGIC

ARRAY

!...-- tsu+ th ~
fmax with No Feedback
Note: fmax with no feedback may be less than l/(twh + twi). This
is to allow for a clock duty cycle of other than SO%.

SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels

+5V

GNDto 3.0V
3ns10%-90%
1.SV
1.SV
See Figure

Output Load

3-state levels are measured O.SV from steady-state active
level.

FROM OUTPUT (010)
UNDER TEST

---+--_--

TEST POINT

Output Load Conditions (see figure)
Test Condition
A
Active High
B
Active Low
C
Active High
Active Low

R1

R2

300n

390n
390n
390n
390n
390n

-

-

300n
300n

CL
50pF
SOpF
SOpF
SpF
SpF

C l-

R2

=
·ClINCLUDES TEST FIXTURE AND PROBE CAPACITANCE

3-43

1994 Data Book

H~ Latti ce'"

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

ELECTRONIC SIGNATURE

OUTPUT REGISTER PRELOAD

An electronic signature word is provided in every GAL16V8Z1ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
secu rity cell.

When testing state machine deSigns, all possible states and state
transitions must be verified in the deSign, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(I.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.

NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum.

The GAL16V8Z1ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.

SECURITY CELL
A security cell is provided in the GAL 16V8Z1ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The electronic signature
data is always available to the user, regardless of the state of this
security cell.

INPUT BUFFERS
GAL 16V8Z1ZD devices are designed with TTL level compatible
input buffers. These buffers, with their characteristically high impedance, load driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic.

DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
Development Tools Section of the Data Book). Complete programming of the device takes only a few seconds. Erasing of the
device is transparent to the user, and is done automatically as part
of the programming cycle

GAL 16V8Z1ZD input buffers have latches within the buffers. As
a result, when the device goes into standby mode the inputs will
be latched to its values prior to standby. In order to overcome the
input latches, they will have to be driven by an external source.
Lattice recommends that all unused inputs and tri-stated 110 pins
for both devices be connected to another active input, Vcc' or
GND. Doing this will tend to improve noise immunity and reduce
Icc for the device.

INPUT TRANSITION DETECTION lTD
The GAL16V8Z relies on its intemal input detection circuitry to put
the device in power down mode. If there is no input transition for
the specified period of time, the device will go into the power down
state. Any valid input transition will put the device back into the
active state. The first riSing clock transition from power-down state
only acts as a wake up signal to the device and will not clock the
data input through to the output (refer to standby power timing
waveform for more detail). Any input pulse widths greater than
Sns at input voltage level of 1.SV will be detected as input transition. The device will not detect any input pulse widths less than
1ns measured at input voltage level of 1.SV as an input transition.

Typical Input Characteristic
40
30

~

20

c

10

..

a.
I!!
~

0

/

/

::J

U

'5
Q.
.5

DEDICATED POWER-DOWN PIN (DPP)

-10

/

"\
\
\

,

I
J

-20

\

-30

.-""

-40

The GAL16V8ZD uses pin 4 as the dedicated power-down signal
to put the device in to the power-down state. DPP is an active high
signal where a logic high driven on this signal puts the device into
power-down state. Input pin 4 cannot be used as a functional input
on this device.

o

2

3

4

5

Input Voltage (Volts)

3-44

1994 Data Book

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••
POWER-UP RESET
Vee

4.0V

----'

ClK

INTERNAL """'..,.....,.-.,..-........,........"....,,~~, I
REGISTER
OUTPUT 0

Device Pin
~
Reset to Logic '1"

asynchronous nature of system power-up, some conditions must
be met to guarantee a valid power-up reset of the GAL16V8Z1ZD.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.

Circuitry within the GAL 16V8Z1ZD provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1/lS MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN~

PIN

Vee

Tri-State
Control

Vee

Data
Output

PIN

PIN

Feedback
(To Input Buffer)
Typical Output
Typical Input

3-45

1994 Data Book

~~~Latticem

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

TYPICAL AC AND DC CHARACTERISTICS
Normalized Tpd ". Vee
1.2

~1.1

~

1

~

0.0

iii

......

...........

~

0.8
4.60

5.00

4.75

r---...-

0.8
4.50

I- 1.1

--PTL->HI

-g

.t:!

1

E 0.0
o

Z

0.8

E

~

".

0.7

:l!

~

...-

~
~~

V8

~

1.2

..

~---RISE

1.1

-FALL

~

.!:!
iii

~

",.

Temp

-

""'"

~

"

- --

-1

~

l1!

........
5.50

5.25

1.2

- - - PTH->LI

1.1

Z 0.8
0.7

~~

~

1

0.0

",

-PTL->HI

~

~

."

:; ?1

0

=

~

Ie

Temperature (deg. Cj

Delta Teo ". # of OUtputs
SWitching

~

- - -

~ -1.5

l.o·5
~
l1!

R1SE.~

-1

~

~

......

~

-FALL

~ :.JI"

~

---R1SE~

~ -1.6

-FALL

-2

-2

Number of Outputs Switching

Number of Outputs Switching
Delta Tpd

V8

Output Loading

Delta Teo V8 Output loading

10

10

~---R1SEI
-FALL I

.

./

LA(.
-2

{!!
~
.!:!
iii

5

Delta Tpd ". , of OUtpUtl
SWitching

~

~ 1.3

Temperature (deg. C)

. .

5.00

4.75

Normalized Tau va Temp

...

:;

Temperature (H

1.4

8

~

=

1

o

1.3

- - - PTH->L

~

1.1

5.60

5.25

Normalized Tco

1.3

R 1.2
iii

i

Supply Voltage (V)

Temp

V8

5.00

'II.

-g'

- .........

4.75

Supply Voltage (V)

Normalized Tpd

Vee

- - - PTH->L

1.3

I- 12

Z

5.60

5.25

I---~E.~

iii

· l -FALL

r-::... "'-

II-PTL->H

V8

1.4

1.2

11- - - PHt->L
.......

Nonnallzed Tlu

Normalized Teo va Vee

.... ~

....

oS

8

~

4

~

o

50

100

150

200

250

300

Output Loading (pF)

-FALL

~

2

o

V

V

~---R1SEI

"OJ"

.."..

-2

I

V

.. ...

V

v. .

~
60

100

150

200

250

300

Output Loading (pF)

3-46

1994 Data Book

H~LatticeTM

Specifications GAL 16V8Z
GAL 16V8ZD

••••••
••••••
••••••

TYPICAL AC AND DC CHARACTERISTICS
Vohvaloh

Voh valoh

Vol va 101
1.5

/

1.25

V'

0.5

- r-. - -

"

~

~

(5 0.75

>

""""-

.JI I"

0.25

4.5
4

~ 3.5\

........

"

./
0.00

0.00

80.00

40.00

20.00

Normalized Icc va Temp

..,

1.30

1.20
1.10
1.00

E 0.90
o

Z

0.80

~

./

0.70
4.SO

./

1.2

~ 1.1

al

/'

.!::!

"- ,

1

~

-~

~ 1.20

al

1.10

~

1.00

~

0.90

.!::!

0.8

4.75

5.00

5.25

0

,

10

S3

~

30

I

I ' .....

o

~

40

""

=

I ' .....

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.SO 4.00

Vin (V)

75

100

o

125

80
70

--

80 I
00
-1.00

I

50

75

~

~

•..

/

al •.•
~ 0.'
~ 0.'

I

-0.40

Vik (V)

3-47

-0.20

0.00

I

7

.!::!

-0.80

100

Normalized Icc va Freq. (ITO)

I

-0.80

25

Frequency (MHz)

I

~50

2

50

Input Clamp (Vik)

20

 10MHz)
1.30

~~ 0.9

Supply Voltage (V)

1ll
c;;

10h(mA)

loh(mA)

Normalized Icc va Vee

~

2.5 -I--~---+---I---l
3.00
4.00
2.00
0.00
1.00

10.00 20.00 30.00 40.00 SO.OO eo.OO

101 (mA)

~
-g

-1\---4--+--1---1

~ .j...1\~--1-_--1-_-I----1

iJ
./
10

100

,.00

10000

Frequency (KHz)

1994 Data Book

•

I

~~~Latticem

Notes

••••••
••••••
••••••

3-48

1994 Data Book

GAL 16VPB
High-Speed E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

• HIGH DRIVE E'CMOS® GAL®DEVICE
- TTL Compatible 64 mA Output Drive
- 15 ns Maximum Propagation Delay
- Fmax = 80 MHz
- 10 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology

1/0/0

• ENHANCED INPUT AND OUTPUT FEATURES
- Schmitt Trigger Inputs
- Programmable Open-Drain or Totem-Pole Outputs
- Active Pull-Ups on All Inputs and 110 pins

1/0/0

• E' CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «lOOms)
- 20 Year Data Retention

1/0/0

1/0/0

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Architecturally Compatible with Standard GAL 16V8

1/0/0

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability

1/0/0

• APPLICATIONS INCLUDE:
- Ideal for Bus Control & Bus Arbitration Logic
- Bus Address Decode Logic
- Memory Address, Data and Control Circuits
- DMA Control

1/0/0

1/0/0

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/OE

DESCRIPTION

The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control applications. The GAL 16VP8 is manufactured using Lattice's advanced FCMOS process which combines CMOS with Electrically
Erasable (F) floating gate technology. High speed erase times
«lOOms) allow the devices to be reprogrammed quickly and efficiently.

PIN CONFIGURATION

DIP
PLCC

IiCLK

vOla

System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL 16VP8
combines the familiar GAL 16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design
flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The 64mA output drive eliminates the need
for additional devices to provide bus driving capability.
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

[

.

I

IICLK

•

I
20

10p

[

[6

GAL16VP8
Top View

[

[ a •
I

11

vOla

IIOJQ

P

16P
p
13 1·P

"O/Q

vOla

UO/Q

vola

Vee

UO/Q

GND

GND

vOla

UD/Q

vOla

IIOE IIOJQ IJOIQ IIOIQ

vOla

116E

vOla

Copyright © 1994 Lattice Semiconductor Corp_ All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.SA
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-49

1994 Data Book

..
I

~HLatticem

Specifications GAL 16VPB

••••••
••••••
••••••

GAL 16VP8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

15

B

10

115

GAL16VPBB-15LP

20-Pin Plastic DIP

115

GAL16VPBB-15W

20-Lead PLCC

25

10

15

115

GAL16VPBB-25LP

20-Pin Plastic DIP

115

GAL16VPBB-25W

20-Lead PLCC

Ordering #

Package

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL16VP8B

DemeName~

x

L--_ _ _

Speed (ns)
L =Low Power

X X

Power - - - - - - - - - '

3-50

L--_ _ _ _

Grade

Blank = Commercial

Package P =Plastic DIP
J= PLCC

1994 Data Book

~~~Lattice~
••••••
••••••
......

Specifications GAL 16VPB

OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.

any of the three modes, while the AC1 and AC2 bit of each of the
macrocells controls the input/output and totem-pole/open-drain
configuration. These two global and 24 individual architecture bits
define a/l possible configurations in a GAL16VP8. The information
given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these
architecture bits from the pin definitions, so the user should not
need to directly manipulate these architecture bits .

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in

..
I

COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. Most compilers also have the
ability to automatically select the device type, generally based
on the register usage and output enable (OE) usage. Register
usage on the device forces the software to choose the registered
mode. All combinatorial outputs with OE controlled by the product
term will force the software to choose the complex mode. The
software will choose the simple mode only when all outputs are
dedicated combinatorial without OE control. For further details,
refer to the compiler software manuals.

In complex mode pin 1 and pin 10 become dedicated inputs and
use the feedback paths of pin19 and pin 11 respectively. Because of this feedback path usage, pin19 and pin 11 do not have
the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
14 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or opendrain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
In registered mode pin 1 and pin 10 are permanently configured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.

3-51

1994 Data Book

~~~Latticem

Specifications GAL 16VPB

••••••
••••••
••••••

REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as 1/0 functions.

Registered outputs have eight product terms per output. 110's
have seven product terms per output.

All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered
or 1/0. Up to eight registers or up to eight 110's are possible in
this mode. Dedicated input or output functions can be implemented as subsets of the 1/0 function.

The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

Registered Configuration for Registered Mode

elK

- SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 controls common ClK for the registered outputs.
- Pin 10 controls common OE for the registered outputL
- Pin 1 & Pin 10 are permanently configured as ClK & OE.

OE

Combinatorial Configuration for Registered Mode
-SYN=O.
- ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 & Pin 10 are permanently configured as ClK & OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-52

1994 Data Book

Specifications GAL 16VPB

••••••
••••••
••••••
REGISTERED MODE LOGIC DIAGRAM

DIP and PLCC Package Pinouts
~
~

0

•

2128

8

12

16

20

2.

28

PTD

-a 20
OLMC 1

0000

:§:

-=-

022.

XOR-2048
AC1-2120
AC2-2194

OLMC 2

0256

~

0480

2 D-

XOR-2049
AC1-2121
AC2-2195

OLMC 3

0512

§:

=§:

0736

3D

OLMC 4

0768

:8=
:8=

0992

40

XOR-2051
AC1-2123
AC2-2197

OLMC 5

1024

:8=
:8=

1248

6D
1280

-='l3=

1504

70
1536

-=:§:
~

1760

8

XOR-20SO
AC1-2122
AC2-2196

~

1792

XOR-2052
AC1-2124
AC2-2198

OLMC 6
XOR-2053
AC1-2125
AC2-2199

OLMC 7
XOR-2054
AC1-2126
AC2-2200

l!i.~

2016

90 -

ff"
2191

8

XOR-2055
AC1-2127
AC2-2201

or-"

[J~

on
on
Cf'

[l.

OLMC 8

:§:

Ct
b=
0=

[J

19

18

17

16

14

13

12

~
~

11

~

/1 OE
~

10

SYN-2192
ACO-2193

MSB

3-53

1994 Data Book

~~~Latticem
••••••
••••••
......

Specifications GAL 16VPB

COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
10 are always available as data inputs into the AND array.

Up to six 110's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the 1/0 function. The
two outer most macrocells (pins 11 & 19) do not have input capability. Designs requiring eight 110's can be implemented in the
Registered mode.

The JEDEC fuse numbers including the UES fuses and PTD
fuses are shown on the logic diagram on the following page.

Combinatorial 1/0 Configuration for Complex Mode
- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=O defines open-drain output.
- Pin 12 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode
- SYN=1.
- ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=O defines open-drain output.
- Pin 11 and Pin 19 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-54

1994 Data Book

~~~Latticem

Specifications GAL 16VPB

••••••
••••••
••••••

COMPLEX MODE LOGIC DIAGRAM
DIP and PLCC Package Pinouts

D

'"v

2128

0

4

8

12

16

20

24

28

PrO

CJ 20
0000

J.::

§=

§=

0224

l
0256

~

0480

2

~

0512

A:::=

B

B=

0736

3 D0788

§:::::::
t::l=

0992

4D
1024

1248

6D
1280

1504

7

~

XOR·2049
AC1·2121
AC2·2195

OLMC 3
XOR·2050
AC1·2122
AC2·2196

OLMC 4
XOR·2051
AC1·2123
AC2·2197

OLMC 5

~

OLMC 6

~
=.

~
~

1792

9D

OLMC 2

XOR·2052
AC1·2124
AC2·2198

XOR·2053
AC1·2125
AC2·2199

OLMC 7

1760

2016

XOR-2048
AC1·2120
AC2·2194

~

1536

8

OLMC 1

XOR·2054
AC1·2126
AC2·2200

8
§= OLMC
XOR·2055

§==

frl

~v

~v

G

19

JG

18

~ 17
~-

=:J

~C>
~v

~

~v

J-D
J-D
-D

16

14

13

12

J
-l
v

-a 11

AC1·2127
AC2·2201

CJ 10

2191

SYN-2192
ACO-2193

MSB

3-55

1994 Data Book

~~~Latticem

Specifications GAL 16VPB

••••••
••••••
••••••

SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Pins 1 and 10 are always available as data inputs into the AND
array. The center two macrocells (pins 14 & 16) cannot be used
in the input configuration.

All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has
programmable polarity.

The JEDEC fuse numbers including the UES fuses and PTD
fuses are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode
- SYN=1.
- ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 14 & 16 can be configured to
this function.
Combinatorial Output Configuration for Simple Mode
Vee

o

- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pins 14 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode
- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 14 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-56

1994 Data Book

~~~Lattice~
••••••
......
••••••

Specifications GAL 16VPB

SIMPLE MODE LOGIC DIAGRAM
DIP and PLCC Package Pinouts

D--f>--

2128

0

4

8

12

16

20

24

28

PTDI

J.

0000·

~

0224

~

0480

...,.

OLMC1
XOR-2048
AC1-2120
AC2-2194

OLMC2

0256

2

---a 20

XOR-2049
AC1-2121
AC2-2195

11

-D 19

11

-D 18

11
...-

-D 17

r1

-D 16

...-

...-

•

--

OLMC3

0512

~

0736

3 D-

XOR-2050
AC1-2122
AC2-2196

OLMC4

0768

~

0992

XOR-2051
AC1-2123
AC2-2197

...-

4 D-

OLMC5

1024

~

1248

6 D--

XOR-2052
AC1-2124
AC2-2198

OLMC6

1280

~

1504

7 r>--

XOR-2053
AC1-2125
AC2-2199

OLMC7

1536

B==

§=

1760

XOR-2054
AC1-2126
AC2-2200

11

-

14

r1 -

13

...-

or--..

"....,

v

r1
...-

-D 12

r1

-D 11

8 D-1792

B==

:8:=

2016

9 D-

l-

t

OLMC8
XOR-2055
AC1-2127
AC2-2201

...-

e

10

2191

SYN-2192
ACO-2193

MSB

LSB

3-57

1994 Data Book

~~~Lattice~

Specifications GAL 16VPB

••••••
••••••
••••••

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS!')

Commercial Devices:
Ambient Temperature (TAl ............................... 0 to 75°C
Supply voltage (Veel
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vee ......................................... -.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.OV
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ............................................ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP.'

MAX.

UNITS

VIL

Input Low Voltage

vss-o.s

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

VI'

Input Clamp Voltage

Vcc=Min.

-1.2

V

ilL"

Input or 1/0 Low Leakage Current

OV :s; VIN :s; VIL (MAX.)

-

-

-100

I!A

IIH

Input or 1/0 High Leakage Current

3.5V :s; VIN :s; Vee

Output Low Voltage

10L = MAX. yin = VIL or VIH

-

I!A

VOL

-

10
0.5

V

VOH

Output High Voltage

IOH = MAX. Yin =VIL orVIH

-

IIN=-32mA

2.4

-

-

10L

Low Level Output Current

-

-

64

rnA

10H

High Level Output Current

-

-

-32

rnA

los'

Output Short Circuit Current

-

-400

rnA

Vee=5V

Vour= 0.5V

TA=25°C

-60

V

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) Guaranteed but not 100% tested.
2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
4) Typical values are at Vcc = 5V and TA = 25°C

3-58

1994 Data Book

~~~Latticlf

Specifications GAL 16VPB

••••••
••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

TEST
COND'.

COM

COM

-15

-25

DESCRIPTION
MIN.

MAX. MIN.

MAX.

UNITS

tpd

A

Input or I/O to Combinational Output

3

15

3

25

ns

tco

A

Clock to Output Delay

2

10

2

15

ns

tcf'

-

Clock to Feedback Delay

-

4.5

-

10

ns

tsu

-

Setup Time, Input or Feedback before Clockt

8

10

ns

40

-

MHz

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

55.5

-

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

80

-

50

-

MHz

A

Maximum Clock Frequency with
No Feedback

80

-

50

-

MHz

twh

-

Clock Pulse Duration, High

6

-

10

-

ns

twl

-

Clock Pulse Duration, Low

6

-

10

-

ns

th

fmax3

ten

tdis

Hold Time, Input or Feedback after Clockt

0

0

ns

B

Input or I/O to Output Enabled

-

15

-

20

ns

B

OE to Output Enabled

-

12

-

15

ns

C

Input or I/O to Output Disabled

15

ns

OE to Output Disabled

-

20

C

-

15

ns

12

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

CAPACITANCE (TA

=25

C, f

=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM·

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

C'IO

I/O Capacitance

15

pF

=5.0V, V, =2.0V
Vee =5.0V, VIIO =2.0V
Vee

'Guaranteed but not 100% tested.

3-59

1994 Data Book

~~~Latticem

Specifications GAL 16VPB

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or
1/0 FEEDBACK

INPUT or
1/0 FEEDBACK

COMBINATORIAL
OUTPUT

\\t\\\lli:f::;~

ClK

\\\\\\\\\\\\\\U==

REGISTERED
OUTPUT

Combinatorial Output

Registered Output

INPUT or
I/O FEEDBACK

J
::G'~'R'D~

OUTPUT

~

OUTPUT

OE to Output EnablelDisable

Input or I/O to Output Enable/Disable

ox

r=t'"T~

~fooiI-I---1/fmax~
(w/ofdbk)

fmax with Feedback

Clock Width

3-60

1994 Data Book

~HLattice~

Specifications GAL 16VPB

••••••
••••••
••••••

fmax DESCRIPTIONS
CLK

..

elK

I

1<111
..1 - - - - Is u-

--1..
~I.....- - -

Ico~

I

fmax with External Feedback 1/(tsu+tco)
Note: fmax with extemal feedback is calculated
from measured tsu and tco.

r:---

tcf - - - - . .I

iB a resuk, the
state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of
the output pins. This feature can greatly simplify state machine
design by providing a known state on power-up. The timing diagram for power-up is shown above. Because of the asynchro-

INPUT/OUTPUT EQUIVALENT SCHEMATICS

~PIN
Feedback ....
~~----'
Vce

Active PUll-UP

Active Pull-up
Circuit

Circuit

-.:~ ....

............

i vref:
Programmable

: ESO
: Protection
: Circuit

:::n_0fb:rain
Output

PIN
: ESO
: Protection
: Circuit
~

PIN

Tri-State
Control

..... -- -- - --- -- - -:

Feedback

(To Input Buffer)
Vref = 3.1V

Vref= 3.1V

Typical Input

Typical Output

3-63

1994 Data Book

•

~~~Latticem

Specifications GAL 16VPB

••••••
••••••
••••••

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vee

-g
.t:f

1

~

~ 1.1

-g

--:-

~ 0.9

I---RIS"~

o

II--PTL->H

~ -.

1.2

1.2

11- - - PTH->L

"C
~1.1

.t:f

1

~

5.00

4.75

5.25

5.50

1

l/

"

-g.

Z 0.8

"iii

J ' 10"'"

8
~

1.2

4.75

5.25

5.00

E

~---RISE

4.50

5.50

1

o

Z

0.8

-55

-25

25

50

75

100

~~

JIll'"

~ 1.3

- - -

--PTL->H

~

1.1

~

1

E

o

Z
25

-25

50

75

100

Delta Tpd vs # of Outputs
Switching

. /I-":

"". . .

"C

{::

.l!l
a;

-

~

-:-:

-55

-25

25

50

75

100

125

Temperature (deg. C)

.s
8

-~

-0.5

IFALL

-0.5

'CJ
ii5

.........

.

--

m -0.75
-1

.............. ~

.

---RISE~
--FALL

-1.25

Number of Outputs Switching

Number of Outputs Switching

Delta Teo vs Output Loading

Delta Tpd vs Output Loading

~---RISEI
--FALL I

"C

{::2

-2

125

en -0.25

CJ -0.'

~ a

V

/

0.8 i-"

~

- - - RISET

:!ll

.,."

V

./

Delta Teo vs # of Outputs
Switching

-0.3

0'
.s

PTH->L

0.9

Temperature (deg. C)

en -0.1

5.50

0.7
-55

125

5.25

5.00

I- 1.2
"C

/"'"

~

Temperature (deg. C)

.s -0.2

4.75

Normalized Tsu vs Temp

0.7

0.7

-............. .............

Supply Voltage (V)

~

FALL

1.1

E 0.9

~

--PTL->H

1.4

OJ

.t:f
"iii

~

~ 0.9

1.3

PTH->L

a.
1-11 --PTL->H

o

1

Normalized Teo vs Temp

1.3

E 0.9

-g
.t:f

Supply Voltage (V)

Normalized Tpd vs Temp

- - -

........

0.8

4.50

Supply Voltage (V)

"iii

--

F---- r--

FALL

- - - PTH->L

~

:::J
~ 1.1

0.8

4.50

.t:f

I

~ 0.9

0.8

"0 12

Normalized Tsu vs Vee

Normalized Teo vs Vee

1.2

l/

f'"

V

V

"

0'
.s

,/

50

-2
100

150

200

250

300

~---RISEI
--FALL I

V

l/
50

f'"

100

V
150

1/

"
200

250

300

Output Loading (pF)

Output Loading (pF)

3-64

1994 Data Book

H~Latticem
......

Specifications GAL 16VPB

••••••
••••••

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs 101

Vohvs loh

Vohvs loh

0.5

4.5

r---

0.4

..,../

~ 0.3

:g

..,../

0.2

./

0.1

"

0.00

./
40.00

60.00

80.00

0.00

40.00

..,.
V

./

l..--V

~ 1.1

al

1

~

0.9

i'...

...........

J;l

i"'.

......

............

«
I

Ji\..
I

5

........

.......

-

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin(V)

/'

1.00

100

125

/"

V

25

/"
50

75

100

Frequency (MHz)

Input Clamp (Vik)

10

1

75

Temperature (deg. C)

2.5

til

o

Z

0.90
25

Delta Icc vs Vin (1 input)

1.5

1.30

-g 1.20
.!::!
OJ
E 1.10

0.7
5.50

«
52

4.00

Normalized Icc vs Freq.

~

.!::!

5.25

3.00

2.00

1.40

o 0.8

5.00

1.00

10h(mA)

Z

4.75

"-

0.00

50.00 60.00

Normalized Icc vs Temp

Supply Voltage (V)

0.5

30.00

1.2

4.50

~
Cl

20.00

10h(mA)

0.80

~

10.00

101 (mA)

al

E

g
3.5

20.00

1.10

~ 0.90

.c

3.75

Normalized Icc vs Vee

~ 1.00
til

~

V

1.20

~

4.25

-

~

20

I

30

40

:E50

/

60

/

/

.L"

70
80

/

"""

-2.00

-1.50

-1.00

-0.50

0.00

Vik(V)

3-65

1994 Data Book

•

~~~Lattice~

Notes

••••••
••••••
••••••

3-66

1994 Data Book

GAL1BV10
••••••
••••••
••••••

High Performance E2CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAM

FEATURES

• HIGH PERFORMANCE E2CMOS· TECHNOLOGY
-15 ns Maximum Propagation Delay
- Fmax = 62.5 MHz
- 10ns Maximum from Clock Input to Data Output
- TTL Compatible 16 mA Outputs
- UltraMOse Advanced CMOS Technology

IICLK
I/OIQ

.-

I/OIQ

• LOW POWER CMOS
- 75 mA Typical Icc

I

I/OIQ

• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

I/OIQ

I/OIQ

• TEN OUTPUT LOGIC MACROCELLS
- Uses Standard 22V10 Macrocell Architecture
- Maximum Flexibility for Complex Logic Designs

I/OIQ

I/OIQ

• PRELOAD AND POWER-ON RESET OF REGISTERS
-100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

I/OIQ

I/OIQ

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/OIQ

DESCRIPTION

The GAL18V1 0, at 15 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL 18V1 0 to consume much
less power when compared to its bipolar counterparts. The E2
technology offers high speed «1 OOms) erase times, providing the
ability to reprogram or reconfigure the device quickly and efficiently.

PACKAGE DIAGRAMS

DIP
PLCC

IICLK

Vee
I/OIQ

I

VCLK Vee

I/OIQ

I/OIQ

20

By building on the popular 22V1 0 architecture, the GAL 18V1 0
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V1 0 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V1 0 devices.

I/OIQ

IIOJO
VOIQ

GAL18V10
Top View

VOIQ
I/OJQ

VOIQ
I/OJQ

11
I/OJQ GND

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL@ products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

VOIQ

IIOJO IIOJO IIOJO
I/OIQ

VOIQ

GND

VO/Q

Copyright I.e 1994 lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and Information herein are
subject to change without notice.

LATIICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-67

1994 Data Book

~~~Latticem

Specifications GAL 1BV1 0

••••••
••••••
••••••

GAL18V10 ORDERING INFORMATION

Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

15

10

10

115

GAL18V10-15LP

20-Pin Plastic DIP

Package

115

GAL18V10-15LJ

20-Lead PLCC

::D

12

12

115

GAL18V1 0-20LP

20-Pin Plastic DIP

115

GAL18V10-20LJ

20-Lead PLCC

Ordering #

PART NUMBER DESCRIPTION

XXXXXXXX - XX

GAL18V10

DeYI"" Name

~

x

X X

' - - - - - Grade

Speed (ns)
L = Low Power Power - - - - - - - - - - '

3-68

Blank = Commercial

' - - - - - - Package

P = Plastic DIP
J = PLCC

1994 Data Book

H~Latticem

Specifications GAL 18V1 0

••••••
••••••
••••••

OUTPUT LOGIC MACROCELL (OLMC)
The GAL18V1 0 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
ten product terms (pins 14 and 15), and the other eight OLMCs
have eight product terms each. In addition to the product terms
available for logic, each OLMC has an additional product-term
dedicated to output enable control.

The GAL18V1 0 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this
dedicated product term is asserted. The Synchronous Preset sets
all registers to a logic one on the riSing edge of the next clock pulse
after this product term is asserted.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.

•
•
•
•

NOTE: The AR and SP product terms will force the 0 output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

AR

o
4 TO 1

Q

MUX

SP
2 TO 1 1 - - - - - - - - - - - - - '

MUX

GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS
NOTE: In registered mode, the feedback is from the /0 output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.

Each of the Macrocells of the GAL18V1 0 has two primary functional modes: registered, and combinatorialI/O. The modes and
the output polarity are set by two bits (SO and Sl), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the the following page.

COMBINATORIAL 110
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.

REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the 0 output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /0 output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.

3-69

1994 Data Book

. '
r"

H~Latticem
••••••

Specifications GAL 18V1 0

••••••
••••••

REGISTERED MODE

AR

AR

•

•
o

o

Q

SP

Q

SP

ACTIVE LOW

ACTIVE HIGH

So=O
S, =0

So=1
S,=O

COMBINATORIAL MODE

•

ACTIVE LOW

ACTIVE HIGH

So=O
S, =1

So=1
S, = 1

3-70

1994 Data Book

Specifications GAL 1BV1 0

• •••••
......
••••••
GAL 18V1 0 LOGIC DIAGRAM I JEDEC FUSE MAP

0

,

8

12

16

20

24

28

32

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

0000
0036

~
~

032'

Wf[J

~

19

3457

0360

:§3..

8

~

0848

2

OlMC 18

1

ttw

18

3459

0684

~ ~l

0972

tiU----=J

-b--'

3

17

3461

1008

~ ~J

1296

W-=J

4
1332

-0

~
1692

~

1728

::l::j

5

~

16

1

15

1

14

1

13

J

12

J

11

1

9

!U

~

~','L

=

~

2088

~

~u

348'

6

'---2124

~~

3:E:i

2412

~

~u

3469

7

'------2448

:ft:::h
~

2736

~

~

~u
81

3471

8

'------2n2

~-!L
'i::l=='

3080

~

~
3473

3098

~

§::f

3384

8

-fOLMc9l

~
3475

3420

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

..,.'.'.'.3.'.,.0
, ,
3476,3477 ...

ElectronIc Signature

... 3538, 3539

, ,,

3-71

1994 Data Book

..,

~~~Lattice~

Specifications GAL 18V1 0

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vcc ........................................ -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

Ambient Temperature (TA) ............................ 0 to + 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

ilL'

Input or 1/0 Low Leakage Current

OV S Y,N S V,L (MAX.)

-

-100

!lA

Input or 1/0 High Leakage Current

3.5V S Y,N S Vee

-

10

!lA

VOL

Output Low Voltage

IOL = MAX. Yin = V,L or V,H

-

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = V,L orV,H

2.4

-

-

V

IIH

10L

Low Level Output Current

-

10H

High Level Output Current

-

los2

Output Short Circuit Current

Vee=5V

VOUT = 0.5V TA = 25°C

-50

16

mA

-3.2

mA

-135

mA

COMMERCIAL
Operating Power

V,L = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

V,H = 3.0V

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

3-72

1994 Data Book

Specifications GAL 18V1 0

••••••
......
••••••
AC SWITCHING CHARACTERISTICS

over Recommend edO perar109 CondT
lions
PARAMETER

TEST
COND.'

COM

COM

·15

·20

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

tpd

A

Input or I/O to Combinatorial Output

-

15

-

20

ns

tco

A

Clock to Output Delay

-

10

-

12

ns

tcf2

-

Clock to Feedback Delay

-

7

-

10

ns

tsu

-

Setup Time, Input or Feedback before Clocki

10

-

12

-

ns

Hold Time, Input or Feedback after Clocki

0

-

0

-

ns

A

Maximum Clock Frequency with

50

-

41.6

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tct)

58.8

-

45.4

-

MHz

A

Maximum Clock Frequency with

62.5

-

62.5

-

MHz

th

External Feedback, 1/(tsu +tco)
fmax 3

No Feedback
twh

-

Clock Pulse Duration, High

8

-

8

-

ns

twl

-

Clock Pulse Duration, Low

8

-

8

-

ns

ten

B

Input or I/O to Output Enabled

-

15

-

20

ns

tdis

C

Input or I/O to Output Disabled

-

15

-

20

ns

tar

A

Input or I/O to Asynchronous Reset of Register

-

20

-

20

ns

tarw

-

Asynchronous Reset Pulse Duration

10

-

15

-

ns

tarr

-

Asynchronous Reset to Clock Recovery Time

15

-

15

-

ns

Synchronous Preset to Clock Recovery Time

10

-

12

-

ns

tspr

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (T A

=25 c C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM-

UNITS

TEST CONDITIONS

C,

Input Capacitance

8

pF

C vo

I/O CapaCitance

10

pF

=5.0V, V, =2.0V
Vee =5.0V, VI/a =2.0V
Vee

"Guaranteed but not 100% tested.

3·73

1994 Data Book

Specifications GAL 18V1 0

••••••
••••••
••••••
SWITCHING WAVEFORMS

INPUT or
I/O FEEDBACK

~~~~I'~--~-/I~~~

ClK

REGISTERED
OUTPUT

Combinatorial Output

Registered Output
INPUT or
I/O FEEDBACK

OUTPUT
ClK

1/fmax (in1ernal fdbk

Input or VO to Output Enable/Disable
REGISTERED_ ______t_ctr_ts_u_______
FEEDBACK

fmax with Feedback

ClK

~~=t:r-:
14---1/fmax

(w/ofdbk)

Clock Width

INPUT or
I/O FEEDBACK
DRIVING SP
ClK

REGISTERED
OUTPUT

INPUT or
I/O FEEDBACK
DRIVING AR

~-tsu

tco£
\\\\\\\\\\\\\\

.-tarw-.

elK

REGISTERED
OUTPUT

Synchronous Preset

Asynchronous Reset

3-74

1994 Data Book

~~~Lattice~

Specifications GAL 18V1 0

••••••
••••••
••••••

fmax DESCRIPTIONS
ClK

....
--.. ------------_ ........ ----,,
,,,

-.-------_ .. _,,,

ClK

,,,

lOGIC I--~ REGISTER
ARRAY

,

,-------------_ .. __ .. _---_._-------.- .... __ .-----_.,

r..

,
,
,------.... ---------------_ .. ---------------_._._ ..

IlOIIIoIfIf--- tsu ---1.~ll401f1f---- tco~

----tcl---I.~I

f------tpd----~.1

fmax with External Feedback 1/(1:su+tco)

1.
O I I.
I·

Note: fmax with external feedback is calculated from measured tsu and tco.

fmax with Internal Feedback 1/(1:su+tcf)

eLK

Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf 1lfmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.

r........................ ·...... ·· .......... ·..1

i

~~:y

=

i

REGISTER

~·t~·t~·==+i· .. ··· .. ······· .. ·..i
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than SO%.

SWITCHING TEST CONDITIONS
GNDt03.0V

Input Pulse Levels
Input Rise and Fall Times

+5V

3ns 10% - 90%

Input Timing Reference Levels

1.SV
1.SV

Output TIming Reference Levels

See Figure

Output Load

3-state levels are measured O.SV from steady-state active
level.

FROM OUTPUT (0/0)

TEST POINT

UNDER TEST

Output Load Conditions (see figure)
Test Condition

C

R2

CL

3000

3900

SOpF

Active High

~

3900

50pF

Active Low

3000

SOpF

A
B

R.

Rl

Active High

..

3900
3900

SpF

Active Low

3000

3900

SpF

C·
L

·C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

3-75

1994 Data Book

•

H~Latticem

Specifications GAL 1BV1 0

••••••
••••••
••••••

ELECTRONIC SIGNATURE

OUTPUT REGISTER PRELOAD

An electronic signature is provided in everY GAL18V1 0 device.
It contains 64 bits of reprogram mabie memory that can contain
user-defined data. Some uses include user 10 codes, revision
numbers, or inventory control. The signature data is always
available to the user independent of the state of the security cell.

When testing state machine deSigns, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.

SECURITY CELL
A security cell is provided in every GAL 18V1 0 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.

The GAL 18V1 0 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.

INPUT BUFFERS
LATCH-UP PROTECTION
GAL 18V1 0 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.

GAL18V1 0 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull ups
instead of the traditional p-channel pullups to eliminate any
possibility of SCR induced latching.

The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, lattice recommends that all unused inputs and tri-stated I/O pins be
connected to an adjacent active input, Vcc, or ground. Doing so
will tend to improve noise immunity and reduce Icc for the device.

DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.

Typical Input Current

C

.e
c
~

/'
./

-20

./

"
<>
'; ·40
co.

.:

~

:/

·60
1.0

2.0

3.0

4.0

5.0

Inpul Voltage (Volls)

3-76

1994 Data Book

H~Latticem
......
••••••

Specifications GAL 1BV1 0

••••••

POWER-UP RESET
Vcc

4.0V

_ _- - J

ClK

INTERNAL REGISTER
OUTPUTQ

ACTIVE lOW ~'ff(
OUTPUT REGISTER

Device Pin

~

~~

Device Pin

; -

ACTIVE HIGH
OUTPUT REGISTER

Reset to Logic "1-

Reset to La!!,c (1'

conditions must be met to guarantee a valid power-up reset of the
device. First, the Vee rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

Circuitry within the GAL18V1 0 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1!1S MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN~
Feedback ..

Vcc

Active Pull·up
Circuit

(Vral Typical"" 3.2V)

Tri-State
Control

r---·_·_-----_·_-,

:
: ESO

Vcc:
:

: Protection

PIN

Vcc

...L ...

(Vref Typical = 3.2V)

~ V~f ~

i: !:

:

!.~:~~:~.... ..l

Data
Output

:
:

:

.........:

PIN

Feedback
(TO Input Buffer)

Typical Input

Typical Output

3-77

1994 Data Book

~HLatticeTM

Specifications GAL 18V1 0
Typical Characteristics

••••••
••••••
••••••

Normalized Tpd vs Vee

1,3

1,2

'8,1.1
l'D

~

1

~

~

~

~

0 0.9

~
~

Z
0.8

PT H->L
PTL->H

I·····

r-

12+-____-1______~------~----~

12+-______~----_+------~----~

1,1

!o-.::::---_+------+-----j------..,

5

-+___1-__+ __--1

0,9+--_ _

4,5

Supply VoHage (V)

4,75

Normalized Tpd VS. Temperature

/

L

~

. /V

L

1

1...
z

0,8

V

~

0,8t---+----t---t----l
0,7l-_ _-I-_ _--4_ _ _-I-_ _-I
4.5

0

25

50

75

100

/'

V

- ---

~1.1

V

~

-55

125

-25

0

J

0,•

25

50

75

100

V'

./

/
Max. --4

Max.

",

IOLVS. VOL

250

V'

v

./

./

V

-25

0

25

50

75

100

/"

12

.§

V

1.1

I

o 0.9

Z

....- ... ~

~

/'

0,8

/'

0,7

100

200

300

400

4.75

4,5

5

5.25

5.5

Supply Voltage (V)

.150 ,.-____- .___IOH
___
VS,,_V_o_H__--._____,

Normalized Icc vs. Temperature

1.3 .,-__. -__.,-__.,-__--,__--,__. . ,__--,
locvtl.Temperature

200

1'50
...
,2100
50

/

V

/'

~

~

125

Normalized Icc VS. Vee

1,3

Output Loading Capacitance (pf)

# of Outputs

5.5

Ambient Temperature (OC)

./

·2
Max. - 8

V

0,7
-55

125

Delta Tpd vs, Output Loading

10

5.25

V

1

0,8

-2

..

5

1,2

Ambient Temperature (0C)

.....-

V V

4.75

Normalized Teo VS. Temperature

0,7
-25

~----_+------~----~

1.3

V

Delta Tpd VS, # of Outputs Switching

~

~

Supply VoHage (V)

./

Ambient Temperature (0C)

·1

~ If=~~~r_----_+------_F~~~

~ 0,9+-______

5,5

5,25

1.1

If!.

il

,,/

0,7
-50

o

5

1.2

1,2

V

'D

Normalized Tsu vs. Temperature

1,3

./

8 1,1 +-------~----_+------~----~

l-

Supply VoHage (V)

1.3

0,8

-~
.......
..........

•••••••••••••••••••

o.7L_--l__-L.::==+==::::J

5,5

5.25

1

0,8+---+---+r==-;;:PT;-:L~'>:;;H~l~
I·····PTH.>L I

0.7
4.75

Nonnalized Teo VS, Vee
1.3,-_ _- ._ _ _.--_ _- ._ _---.

-- -

~~

4,5

Normalized Tsu vs. Vee
1,3,---,----.-------r---.

1.'

·100 .p...,----1------~-----jI_----..,

.50+-------1----~d_----I_I_----..,

~

1.1

Z

0.9

l'

I

r",t---T--"t·:':·'::··:";I~'b~W~'T~~~pe~~I~"~:Jr-F......=+
•• '~
•• ~.•••+-,--+---+-f--+--I

'. ,

+--.J----II----+--+,-.::
..'h~*""~
........
............

2

VOL (V)

2

VOH(V)

3-78

·25

0

25

50

75

100

Ambient Temperature (OC)

1994 Data Book

GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

PL 0 - - - - - - - - - - - - - - ,

• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- 10 ns Maximum Propagation Delay
- Fmax 71.4 MHz
- 11 ns Maximum from Clock Input to Data Output
- TTL Compatible 8 mA Outputs
- UltraMOS" Advanced CMOS Technology

=

IIOJQ

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc

11010

• ACTIVE PULL·UPS ON ALL PINS

Il0l0

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100 ms)
- 20 Year Data Retention

..
I

IIOJQ

IIOJQ

• TEN OUTPUT LOGIC MACROCELLS
-Independent Programmable Clocks
- Independent Asynchronous Reset and Preset
- Registered or Combinatorial with Polarity
- Full Function and Parametric Compatibility with
PAL20RA10

VO/O

VOIQ

• PRELOAD AND POWER·ON RESET OF ALL REGISTERS
-100% Functional Testability

Il0l0

• APPLICATIONS INCLUDE:
- State Machine Control
- Standard Logic Consolidation
- Multiple Clock Logic Designs

IIOJQ

IIOJQ

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
OE

DESCRIPTION
PIN CONFIGURATION

The GAl20RA10 combines a high periormance CMOS process
with electrically erasable (F) floating gate technology to provide
the highest speed periormance available in the PLD market.
Lattice's FCMOS circuitry achieves power levels as low as 75mA
typical Icc which represents a substantial savings in power when
compared to bipolar counterparts. E2 technology offers high
speed «lOOms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.

DIP
PLCC

Vee

UOIO
I/OIQ

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA 10 is a direct parametric compatible
CMOS replacement for the PAl20RA 10 device.

1

1

NC
1

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacturing. Therefore,
LATTICE guarantees 100% field programmability and functionality
of all GAL products. LATTICE also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.

28

•

28

1/0/0

2•
2.

7

GAL20RA10
21
9 Top View

111

12

,. ,.

,.

19

I/OIQ

I/OIQ

I/OIQ

I/OIQ

I/OIQ

I/O/Q

NC
I/OIQ

110/0

I/OIQ

1/010

I/OIQ

IIOIQ

I/O/Q

DE

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-79

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
••••••
GAL20RA10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (rnA)

10

4

11

100

GAL20RA lOB· 1OLP

100

GAL20RA lOB· 1OLJ

28·Lead PLCC

15

7

15

100

GAL20RA10·15LP

24·Pin Plastic DIP

100

GAL20RA10·15LJ

28·Lead PLCC

20

10

20

100

GAL20RA10·20LP

24·Pin Plastic DIP

100

GAL20RA10·20LJ

28·Lead PLCC

100

GAL20RA10·30LP

24·Pin Plastic DIP

100

GAL20RA10·30LJ

28·Lead PLCC

3J

20

3J

Ordering #

Package
24·Pin Plastic DIP

Industrial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (rnA)

20

10

20

120

GAL20RA 10·20LPI

24·Pin Plastic DIP

120

GAL20RA 10·20LJI

28·Lead PLCC

Ordering #

Package

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL20RA10B Devl", Name
GAL20RA10

~

x

L -_ _ _ _

Speed (ns)
L = Low Power

X X

Grade

Blank = Commercial
I Industrial

=

Power - - - - - - - - - - '

3-80

Package P = Plastic DIP
J = PLCC

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
......

ASYNCHRONOUS RESET AND PRESET

OUTPUT LOGIC MACROCELL (OLMC)
The GAL20RA 10 OLMC consists of 10 D flip-flops with individual asynchronous programmable reset, preset and clock
product terms. The sum of four product terms and an ExclusiveOR provide a programmable polarity D-input to each flip-flop. An
output enable term combined with the dedicated output enable
pin provides tri-state control of each output. Each OLMC has a
flip-flop bypass, allowing any combination of registered or combinatorial outputs.

Each GAL20RA 10 macrocell has an independent asynchronous
reset and preset control product term. The reset and preset
product terms are level sensitive, and will hold the flip-flop in the
reset or preset state while the product term is active independent of the clock or D-inputs. It should be noted that the reset and
preset term alter the state of the flip-flop whose output is inverted
by the output buffer. A reset of the flip-flop will result in the output
pin becoming a logic high and a preset will result in a logic low.

The GAL20RA 10 has 10 dedicated input pins and 10 programmable 1/0 pins, which can be either inputs, outputs, or dynamic
1/0. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange 1/0 pin assignments without restriction.

FUNCTION
RESET PRESET
Registered function of data product term
0
0
Reset register to "0" (device pin = "1 ")
1
0
1
Preset register to "1" (device pin = "0")
0
Register-bypass (combinatorial output)
1
1

INDEPENDENT PROGRAMMABLE CLOCKS

COMBINATORIAL CONTROL

An independent clock control product term is provided for each
GAL20RA 10 macrocell. Data is clocked into the flip-flop on the
active edge 01 the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These
clocks can be derived Irom any pin or combination of pins and!
or feedback from other flip-flops. Multiple clock sources allow a
number of asynchronous register functions to be combined into
a single GAL20RA 10. This allows the designer to combine discrete logic functions into a single device.

The register in each GAL20RA 10 macrocell may be bypassed
by asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell
as a combinatorial output, or to fix the macrocell as combinatorial
only by forcing both reset and preset product terms active. Some
logic compilers will configure macrocells as registered or combinatorial based on the logic equations, others require the designer to force the reset and preset product terms active for combinatorial macrocells.

PROGRAMMABLE POLARITY
The polarity 61 the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flipflop. While anyone of the four logic function product terms are
active the D-input to the flip-flop will be low if the Exclusive-OR
bit is set to zero(O) and high if the Exclusive-OR bit is set to one(l).
It should be noted that the programmable polarity only affects the
data latched into the flip-flop on the active edge of the clock product
term. The reset, preset and preload will alter the state of the flipflop independent of the state of programmable polarity bit. The
ability to program the active polarity of the D-inputs can be used
to reduce the total number of product terms used, by allowing the
DeMorganization of the logic functions. This logic reduction is
accomplished by the logic compiler, and does not require the
designer to define the polarity.

PARALLEL FLIP-FLOP PRELOAD
The flip-flops of a GAL20RA 10 can be reset or preset from the
1/0 pins by applying a logic low to the preload pin (1) and applying
the desired logic level to each 1/0 pin. The 1/0 pins must remain
valid for the preload setup and hold time. All 10 flip-flops are reset
or preset during preload, independent of all other OLMC inputs.
A logic low on an 1/0 pin during preload will preset the flip-flop,
a logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin (13) will disable all 10 outputs
of the GAL20RA 10 when held high.

OUTPUT ENABLE
The output of each GAL20RA 10 macrocell is controlled by the
"AND'ing" of an independent output enable product term and a
common active low output enable pin(13). The output is enabled
while the output enable product term is active and the output
enable pin(13) is low. This output control structure allows several
output enable alternatives.

3-81

1994 Data Book

..
i

~~~Lattice~

Specifications GAL20RA 10

••••••
••••••
••••••

OUTPUT LOGIC MACROCELL DIAGRAM

OUTPUT LOGIC MACROCELL CONFIGURATION (REGISTERED with POLARITY)

AR
P L P Dt----+_t

OUTPUT LOGIC MACROCELL CONFIGURATION (COMBINATORIAL with POLARITY)

XOR (n)

3-82

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
••••••
GAL20RA 10 LOGIC DIAGRAM

DIP (PLCC) Package Pinouts
1 (2)

2 (3)

D
Pi
D

.......
-v

0

4

8

12

16

20

24

28

32

0

..... 280

600

D
640

POLMC - 23

I

POLMC - 22

=8=

~

920

4 (5)

i

:8

:§

6 (7)

XOR ·3201

OLMC - 21
XOR • 3202

~

960

5 (6)

XOR • 3200

"0----

320

3 (4)

36

=t3

1240

D1280

-Ll

1560

l3
-.....

~

OLMC - 19
XOR • 3204

XOR· 3205

D1920

OLMC - 17
2200
XOR· 3206

8 (10) D2240

OLMC - 16
2520

9 (11)

D

XOR ·3207
2560

OLMC - 15
2840

10 (12)

XOR· 3208

D-

I.J..

........

22 (26)

I.J..

........

21 (25)

W-

W-

20 (24)

~-a 19 (23)
~-a 18 (21)

~-a

17 (20)

~-a

16 (19)

b

OLMC - 14 --;J.

3160

15 (18)

D

--0-

A.

"'"
64·USER ELECTRONIC SIGNATURE FUSES

3210,3211, .".
Byte 7 Byte 6 ""

M

L

S

S

B

B

........

~XOR • 3209

a

14 (17)

13 (16)

OE

"" 3272, 3273
"" Byte 1 Byte 0

3-83

..

I

....,

2880

11 (13)

23 (27)

........
~XOR· 3203

OLMC - 18
7 (9)

........

OLMC - 20 --;J.

1600

1880

I.J..

W-

1994 Data Book

~~~Latticem

Specifications GAL20RA 108

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to V cc + 1.0V
Off-state output voltage applied .......... -2.5 to Vee +1 .OV
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

AmbientTemperature (TA) ............................ 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:
Ambient Temperature (TA) ......................... -40 to +85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may eause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

IIL'

Input or I/O Low Leakage Current

OV :s; VIN :s; VIL (MAX.)

-

-

-100

IIH

Input or I/O High Leakage Current

3.5V :s; VIN s Vee

-

10

!lA
!lA

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = VIL or VIH

-

2.4

-

10L

Low Level Output Current

-

10H

High Level Output Current

-

los2

Output Short Circuit Current

-50

Vee=5V

VOUT = 0.5V TA = 25°C

V

-

8

rnA

-3.2

rnA

-

-135

mA

100

mA

COMMERCIAL
Icc

Operating Power

VIL=0.5V

L-10

Supply Current

f'oggle = 15MHz Outputs Open

VIH =3.0V

-

75

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are atVcc = 5V and TA = 25°C

3-84

1994 Data Book

Specifications GAL20RA 10B

·......
.....
......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions
COM
PARAMETER

-10

TEST

DESCRIPTION

COND.'

MIN. MAX.

UNITS

tpd

A

Input or 1/0 to Combinatorial Output

2

10

ns

teo

A

Clock to Output Delay

2

11

ns

tsu

-

Setup Time, Input or Feedback before Clock!

4

-

ns

th

-

Hold Time, Input or Feedback after Clock!

3

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

66.7

-

MHz

Maximum Clock Frequency without

71.4

-

MHz

fmax'
A

Feedback
twh

-

Clock Pulse Duration, High

7

-

ns

twl

-

Clock Pulse Duration, Low

7

-

ns

Input or 1/0 to Output Enabled I Disabled

-

10

ns

ten I tdis

B,C

-

ten I tdis

B,C

OE to Output Enabled I Disabled

-

9

ns

tar I tap

A

Input or 1/0 to Asynchronous Reset I Preset

-

11

ns

tarw Itapw

-

Asynchronous Reset I Preset Pulse Duration

10

-

ns

tarr I tapr

-

Asynchronous Reset I Preset Recovery Time

7

-

ns

twp

-

Preload Pulse Duration

10

-

ns

tsp

-

Preload Setup Time

7

-

ns

thp

-

Preload Hold Time

7

-

ns

..
1) Refer to SWitching Test Conditions section .
2) Refer to fmax Descriptions section.

CAPACITANCE (TA

=25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

C,
CliO

TEST CONDITIONS

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

I/O Capacitance

10

pF

Vee = 5.0V, VIIO = 2.0V

'Guaranteed but not 100% tested.

3-85

1994 Data Book

~~~Lattice~

Specifications GAL20RA 10

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vcc ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vcc + 1.0V
Off-state output voltage applied .......... -2.5 to Vcc +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Ambient Temperature (TA) ............................ 0 to +75°C
Supply voltage (Vcc)
with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:
AmbientTemperature (TA) ••••••••••••••••••••••••• -40 to +85°C
Supply voltage (Vcc)
with Respect to Ground ..................... +4.50 to +5.50V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

V

2.0

Vcc+1

V

OV ~ VIN ~ VIL (MAX.)

-

-

-100

~

3.5V ~ VIN

-

-

10

~

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

IOH = MAX. Yin = VIL or VIH

2.4

-

-

-

-

8

mA

-3.2

mA

-135

mA

Vss-O.5

VIH

Input High Voltage

IlL'

Input or I/O Low Leakage Current

IIH

Input or I/O High Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

10H

High Level Output Current

los2

Output Short Circuit Current

UNITS

0.8

Input Low Voltage

Low Level Output Current

MAX.

-

VIL

10L

TYP."

~

Vcc=5V

Vcc

VOUT = 0.5V T A = 25°C

-50

V

COMMERCIAL
Icc

Operating Power

VIL=0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH =3.0V

L -15/-20/-30

-

75

100

mA

L-20

-

75

120

mA

INDUSTRIAL
Icc

Operating Power

VIL=0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH= 3.0V

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

3-86

1994 Data Book

Specifications GAL20RA 10

......
•••••••
•••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

tpd

TEST
COND.'

COM

COM fiND

COM

-15

-20

-30

DESCRIPTION
MIN. MAX. MIN. MAX. MIN. MAX.

A

Input or 110 to Combinatorial Output

-

15

-

20

UNITS

-

30

ns

tco

A

Clock to Output Delay

-

15

-

20

-

30

ns

tsu

-

Setup Time, Input or Feedback before Clocki

7

-

10

-

20

-

ns

th

-

Hold Time, Input or Feedback after Clocki

3

-

10

-

ns

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

45.0

-

3

A

33.3

-

20.0

-

MHz

A

Maximum Clock Frequency without

50.0

-

41.7

-

25.0

-

MHz

10

-

12

-

20

-

ns

fmax2
Feedback
twh

-

Clock Pulse Duration, High

-

Clock Pulse Duration, Low

10

-

12

-

20

-

ns

ten I tdis

B,C

Input or 110 to Output Enabled I Disabled

-

15

-

20

-

30

ns

ten I tdis

B,C

DE to Output Enabled I Disabled

-

12

15

-

20

ns

twl

A

Input or 110 to Asynchronous Reset I Preset

-

15

-

tarw/tapw

-

Asynchronous Reset I Preset Pulse Duration

15

-

20

tarr Itapr

-

Asynchronous Reset I Preset Recovery Time

10

-

12

twp

-

Preload Pulse Duration

15

-

tsp

-

Preload Setup Time

10

-

thp

-

Preload Hold Time

10

-

tar/tap

20

-

30

ns

20

-

ns

20
30

-

ns

20

-

15

-

25

-

ns

15

-

25

-

ns

ns

..
1) Refer to SWltchmg Test Conditions section .
2) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25

v

C, f

=1.0 MHz)
MAXIMUM"

UNITS

TEST CONDITIONS

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

110 Capacitance

10

pF

Vee = 5.0V, V,/O = 2.0V

SYMBOL

PARAMETER

C,

C VD

"Guaranteed but not 100% tested.

3-87

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
••••••
SWITCHING WAVEFORMS
INPUT or
110 FEEDBACK

INPUT or
110 FEEDBACK

COMBINATORIAL
OUTPUT

ClK
REGISTERED
OUTPUT

Combinatorial Output

INPUT or
110 FEEDBACK

Registered Output

INPUT or
110 FEEDBACK

OUTPUT

Q-OUTPUT OF
REGISTER

Input or VO to Output EnableJDisable

REGISTERED
OUTPUT PIN

twl

ClK
Q-OUTPUT OF
REGISTER

Clock Width

REGISTERED
OUTPUT PIN

PL

Asynchronous Reset and Preset
ALL 110
PINS

INPUT or

110 FEEDBACK
DRIVING AP or AR

Parallel Preload

ClK

t_a_pr_~_rr~

________________

OE

Asynchronous Reset and Preset Recovery

OUTPUT

OE to Enable I Disable

3-88

1994 Data Book

Specifications GAL20RA 10

• •••••
••••••
••••••
fmax DESCRIPTIONS

ClK

liLtI.

,.-----------------------_.----.-- -----------

lOGIC
ARRAY

f---'

f--------------------------------- ____ MOO_MOO_Oj
lOGIC

REGISTER

ARRAY

~-

--- ---- --- -- ---- -- ----- ---- ----- ---- ---- ---- --'
fmax with No Feedback

Note: fmax w~h no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.

fmax with External Feedback lI(1:su+tco)
Note: fmax with extemal feedback is calculated from measured tsu and tco.

SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels

+5V

GNDto 3.0V
3ns 10%-90%
1.5V
1.SV

Output Load

See Figure

3-state levels are measured O.SV from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
A

B

C

Active
Active
Active
Active

High
Low
High
Low

Rl

R2

CL

4700

3900
3900
3900
3900
3900

SOpF
SOpF
SOpF
SpF
SpF

~

4700
~

4700

FROM OUTPUT (OIQ)
UNDER TEST

TEST POINT

R2

C·
L

·C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

3-89

1994 Data Book

•

~~~Latticem
••••••

Specifications GAL20RA 10

••••••
••••••

ELECTRONIC SIGNATURE

DEVICE PROGRAMMING

An electronic signature word is provided in every GAL20RA10
device. It contains 64 bits of reprogram mabie memory that contains user defined data. Some uses include user 10 codes, revision numbers, pattern identification or inventory control codes.
The signature data is always available to the user independent
of the state of the security cell.

GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL DevelopmentTools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.

NOTE: The electronic signature bits if programmed to any value
other then zero(O) will alter the checksum of the device.

INPUT BUFFERS
GAL20RA10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
bipolar devices.

SECURITY CELL
A security cell is provided in every GAL20RA 10 devices as a
deterrent to unauthorized copying of the device pattern. Once
programmed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogramming the device. The original pattem can never be examined once
this cell is programmed. The Electronic Signature is always
available regardless of the security cell state.

GAL20RA10 input buffers have active pull-ups within their input
structure. As a result, unused inputs and I/O's will float to a TTL
"high" (logical "1 "). Lattice recommends that all unused inputs
and tri-stated I/O pins be connected to another active input, Vee,
or GND. Doing this will tend to improve noise immunity and reduce lee for the device.

LATCH-UP PROTECTION

Typical Input Pull-Up Characteristic

GAL20RA10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are deSigned with n-channel pull ups
instead of the traditional p-channel pull ups to eliminate any possibility of SCR induced latching.

C

.:.
c
~

·20

./

"
<>
;

"-

=

-40

~

./
./

V

·60

1.0

2.0

3.0

4.0

5.0

Input Voltage (Volts)

3-90

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
••••••
POWER-UP RESET
Circuitry within the GAl20RA10 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 11J.S MAX). As a result,
the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous
nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL20RA 10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The registers will reset within a maximum of 11J.S. As in normal system operation, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the minimum pulse width requirements.

Vcc

---'

eLK
INTERNAL
REGISTER
OUTPUTQ

VVVVVVVVVVVV\J

QFEEDBACK AND
R~~~;~~~~ !':£::L:0'/:''/:''/::,'/:''/:,'!:::'lY:-,J

Device P;n

Rese'

'0 Log~ .,.

\

__

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN~
Feedback ~
Active Pull-up
Circuit

Vee

~.

PIN

t

=:

Vee

, •.

l. ....

I~I

+---",'.+'-'-1<.
......

(VrefTypical"" 3.2V)

PIN

Feedback
(To Input Buffer)

Typical Input

Typical Output

3-91

1994 Data Book

Specifications GAL20RA 10

••••••
••••••
••••••

GAL20RA10B:TVPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd V8 Vee

"t=

1.1

al

j

1

1.2

~

r--.. """-

0.8
4.50

5.25

5.00

4.75

1.1

j

---. r--..

~ 0.9

1

"li!

E

~ 0.9

---- ---

0.8
•.50

5.50

4.75

Supply Voltage (V)

R 1.2
1

EO."

o

al

=i

~

,

8

l..-'"

l...,.o' I"

E

i

..,. ,
EO." ,..

1.1
._ 1

""

",. io"""

"li!

~

~

~

~ 1 .•

",.

al

1.2

.!::!
"li!

1

~

0.8

E

0.8

!

~

~

~

~

,;

~

~

.... ~

,; ",.

~

!

~0.5

~

·1

~ ·1.5

·4

~~~~~

Temperature (deg. C)

i-o'" ~

io"""

""

7

9

io"""

2

3

•

5

6

7

8

9

10

2

3

4

5

8

8

Number of OUtputs SWitching

Dells Tpd va Output Loading

Dells Tco va Output Loading

-~

~- -

~-

~-.-

,/

~-

10

/
~----

--?

io"'"

50

~E

-FALL!.

/

~

o

1

Number of OUtputs SWitching

~---nSE
-FALL I

0
·2

"'"

·2
1

~
o

~~

~

8

""

. / io"'"

..,. ~ ~

:ll!

~1.5

!2

5.50

Dells Teo va t of Outpuls
SWitching

,;

...

,/

~

Temperature (deg. C)

Delta Tpd V8 t of Outpuls
Switching

.s.

./

0.6

Temperature (deg. C)

,;

5.25

5.00

4.75

Normalized Tau va Temp

0.7

~

.........

0.6
4.50

o

0.7

I'

Supply Voltage (V)

1.2

Z

~

1.6

l-

~
~

1

~ 0.8

1.3

I- 1.1

r--..........

1.2

Normalized Teo V8 Temp

Normalized Tpd V8 Temp

Z 0.8

~

6.50

525

5.00

1.4

Supply Voltage (V)

1.3

~

Normalized T8u va Vee

Normalized Teo V8 Vee

1.2

100

150

Output Loading (pF)

3-92

"'"

50

100

150

Output Loading (pF)

1994 Data Book

~~~LatticeTM

Specifications GAL20RA 10

......
••••••
••••••

GAL20RA10B:TVPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs 101

Vohva loh

/

0.8

./

~ 0.6

:g

/'

0.4
0.2

"

V

20

.s::

.g

1.1

~

2

40

30

10

3.75

r--.... ......

20

30

.g

r-...

40

3.25

60

70

0.00

80

1.00

2.00

3.00

Normalized Icc va Temp

Normalized Icc vs Freq.

U

1.2

"

1.1

~

'-

-....... r---

r--....

.......

r-.....

~

5.00

5.25

I'

a:I

E
1.00
o

...... ......

0.8

-25

Supply Voltage (V)

Z

25

,

.§
2

0,

~

100

125

o

25

50

75

Frequency (MHz)

i;o"'"

30

~

40
50

~

I

= 60

0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70

Vin (V)

~

~

......... .......

......V

/

20

A

0.90

...-

1,...00'

Input Clamp (Vlk)
10

~3

75

Temperature (deg. C)

Delta Icc va Vin (1 input)

~4

".
".

0.80

-55

5.50

1.30

1.10

70

80
90
·2.00

I

I

f

,/
-1.50

-1.00

-0.50

0.00

Vik(V)

3-93

.I

"

:;; 1.20
CD

0.7
4.75

4.00

1.40

o

~a:I 1
E
0.9
o
Z

--

i'-

50

Normalized Icc va Vee

0.8
4.50

r-- r-10h(mA)

..............

1

3.5

10h(mA)

~ 0.9

a:I

.r:.

1.3

§

'ill

~

I\.. .....

101 (mA)

1.2

"'C
CD

"- ......

~3

/'
10

.§

Vohva loh

1994 Dala Book

~~~lattice~
••••••

Specifications GAL20RA 10

••••••
••••••

GAL20RA10:TVPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee
1.2

J- --

~1.1

~

~

--- .... ---

~ 0.9

0.8
4.50

4.75

5.00

0.8
4.60

5.50

6.25

0.7

5.00

~

1

E

~ 0.9

0.8
4.50

5.50

5.25

-- --

4.75

5.00

5.50

5.25

Normalized Teo va Temp

Normalized Tau va Temp
1.4

1.3

,

-

~

..--

~

Normalized Tpd va Temp

-PTl->H

o

4.75

1.1

Supply Voltege (V)

I- 1.1

Z 0.8

---

~

Supply Voltage (V)

- - - PTH->L

1

I-FALL

-----

1.3

EO.•

1- -- R,sel

Supply Voltage (V)

R 1.2

~

1.2

PTH->L

I-PTL->H

1

Normalized Tau va Vee

Normalized Teo va Vee
1.2

~

81.2

~~

l-

i

o

Z

.

~

-

~

z

~

Temperatura (OOg. C)

:l1!

~ -1.5

-;..-

-

i""""

. ;..-

E

RISE.~
FALL

~

-1

:l1!

2

3

..

e

5

7

8

9

Delta Tpd

V8

10

.s
~
S

~

FALL
2

3

4

5

e

7

B

9

10

Delta Teo

V8

Output Loading

12

~

j---RISE 1
-FALL

2

.. "

~

I

"

_.

".

~

..;
0

---RISE.~

Number of Outputs SWitching

Output Loading

12
8

-" "

~

-2

Number of Outputs Switching

10

-,-""

-..;

~- ~

~ -1.5 L."..oo

-2

-.;-

Temperatura (deg. C)

-0.5

---

..
.,

Delta Teo va' of Outputa
SWitching

-".
I"'"

~
~

...,.~

~

",

0.8

~

~

-1

-

1.1

10:

Delta Tpd va , of Outputa
Switching

-0.5

~

1.2

~

0.7

Temperatura (deg. C)

E

1.3

~

0.7

.,

~

0.8

I,..,0Il

...

~

./

1

E 0.9

~

-FAlL

1.1

~

~

~---RISE

....

.-

10
-.;-

.s

8

~4

:l1!
~

2
0

.
-2

-2

50

100

150

200

250

300

..;

~~--RISEI
-FALL I

,.,

~

50

..;~

" ..
100

.... ....
..;

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-94

1994 Data Book

~HLattice'"

Specifications GAL20RA 10

••••••
••••••
••••••

GAL20RA10:TVPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Yoh vsloh

Vah valoh

Vol va 101

4.5

,

2.5

~
C5

..,

1.5

>

I'

.~

2

1

0.5

"". i""""

0.00

20.00

~

........ r-....

~

.." ~
40.00

~~

1.00

~
0.00

r---

60.00

0.00

80.00

10.00 20.00 30,00 40.00 50.00 60.00

5.00

1.00

I

1.1

5.25

3.00

2.00

4.00

Normalized Icc va Freq.
1.40

1.2

~

-r--

loh(mA)

~

8
:0
~

........ i"oo...

"" ~ .....

1

~ 0.9

~

0.8
4.75

0.00

Normalized Icc va Temp

0.80
4.50

3.75

10h(mA)

---

-

"'- r--.-

0

3.5

Normalized Icc va Vee
1.20

al
.!:::!

-

~

~

.r:.

>

o
101 (mA)

~ 1.10

4.25

~o

Z

1.30

./

1.20
1.10

1.00

0.00

~

./"

"V"

0.80

o

5.50

Temperature (deg, C)

Supply Voltage C'J)

Delta Icc va Vln (1 Input)

16

30

45

Frequency (MHz)

Input Clamp (Vlk)
~

I('

;;(4

.5.

3

11\

~

J!!

2

G;

0,

J

If

I

"

10

I.......

~

...

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.SO 4.00

Vin C'J)

12

I

/

I

14
-2.00

-1.00

0.00

Vik(V)

3-95

1994 Data Book

Notes

••••••
••••••
••••••

3·96

1994 Data Book

GAL20V8
High Performance E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES
• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- 5 ns Maximum Propagation Delay
- Fmax 166 MHz
- 4 ns Maximum from Clock Input to Data Output
- UltraMOS" Advanced CMOS Technology

=

-1/0/0

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc on Low Power Device
- 45mA Typ Icc on Quarter Power Device

11010

• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

1/0/0

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 24-pin PAL'" Devices with Full FunctionlFuse Map/Parametric Compatibility

1/0/0

.I

1/010

1/0/0

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability

1/0/0

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

1/0/0

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION

PIN CONFIGURATION

The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (EO) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
«100ms) allow the devices to be reprogrammed quickly and efficiently.

DIP
PLCC
24

"....g uz

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures
listed in the table olthe macrocell description section. GAL20V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.

I

•

I

7

g

>

-

28

~

VO/O

GAL
20V8

26

2.

UOJQ

23

UOJQ

UOJQ

GAL20V8

NC

I

9

Top View

VO/O
VOIO
18

NC

21

VOIO

UOJQ

111

12

,.

16

c
z

!;! Ig -

"

19
18

~

VO/O
VO/O

UOJQ

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL'" products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

Vee

VO/Q

UOJQ

VO/O

GND

12

13

VOE

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-97

1994 Data Book

Specifications GAL20VB

••••••
••••••
••••••
GAL20V8 ORDERING INFORMATION
Commercial Grade Specifications
Ordering #

Tpd (ns)

Tsu (ns)

Teo (ns)

Icc (mA)

5

3

4

115

GAL20V8C-5W

28-Lead PLCC

7.5

7

5

10

10

15

12

15

25

7

10

12

Package

115

GAL20V8B-7LP

24-Pin Plastic DIP

115

GAL20V8B-7W

28-Lead PLCC

115

GAL20V8B-10LP

24-Pin Plastic DIP

115

GAL20V8B-10W

28-Lead PLCC

55

GAL20V8B-150P

24-Pin Plastic DIP

55

GAL20V8B-15QJ

28-Lead PLCC

00

GAL20V8B-15LP

24-Pin Plastic DIP

00

GAL20V8B-15W

28-Lead PLCC

55

GAL20V8B-250P

24-Pin Plastic DIP

55

GAL20V8B-250J

28-Lead PLCC

00

GAL20V8B-25LP

24-Pin Plastic DIP

00

GAL20V8B-25W

28-Lead PLCC

Industrial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

10

10

7

130

GAL20V8B-10LPI

24-Pin Plastic DIP

130

GAL20V8B-10WI

28-Lead PLCC

130

GAL20V8B-15LPI

24-Pin Plastic DIP

130

GAL20V8B-15WI

28-Lea'cl PLCC

ffi

GAL20V8B-200PI

24-Pin Plastic DIP

ffi

GAL20V8B-20QJI

28-Lead PLCC

ffi

GAL20V8B-250PI

24-Pin Plastic DIP

ffi

GAL20V8B-25QJI

28-Lead PLCC

130

GAL20V8B-25LPI

24-Pin Plastic DIP

130

GAL20V8B-25WI

28-Lead PLCC

15

12

13

2l

15

25

10

11

12

Ordering #

Package

PART NUMBER DESCRIPTION

xxxxxxxx - xx

GAL20V8C
GAL20V8B

Devke~"~

Q

L =Low Power
=Quarter Power

=

Blank Commercial
I Industrial

Speed (ns)

=

Power - - - - - - - - - - '

Package

P

J

3-98

=Plastic DIP

=PLCC

1994 Data Book

~~~Lattice'M

Specifications GAL20VB

••••••
••••••
••••••

OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development softwarelhardware and is completely
transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the inpuVoutput configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL20V8 . The information given on these architecture bits is
only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL20V8
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.

PAL Architectures
Emulated by GAL20V8

GAL20V8
Global OLMC Mode

20R8
20R6
20R4
20RP8
20RP6
20RP4

Registered
Registered
Registered
Registered
Registered
Registered

20L8
20H8
20P8

Complex
Complex
Complex

14L8
16L6
18L4
20L2
14H8
16H6
18H4
20H2
14P8
16P6
18P4
20P2

Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple

COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table
can be used to override the automatic device selection by the
software. For further details, refer to the compiler software
manuals.

In registered mode pin 1 and pin 13 (DIP pinout) are permanently
configured as clock and output enable, respectively. These pins
cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively. Because
of this feedback path usage, pin 22 and pin 15 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18 and 19) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.

ABEL
CUPL
LOGliC
OrCAD-PLD
PLDesigner
TANGO-PLD

Registered

Complex

Simple

Auto Mode Select

P20V8R
G20V8MS
GAL20V8 R
"Registered'"
P20V8R2
G20V8R

P20V8C
G20V8MA
GAL20V8 C7
"Complex'"
P20V8C2
G20V8C

P20V8AS
G20V8AS
GAL20V8 C8
"Simple'"
P20V8C2
G20V8AS3

P20V8
G20V8
GAL20V8
GAL20V8A
P20V8A
G20V8

1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.

3-99

1994 Data Book

~~~Latticern

Specifications GAL20V8

••••••
••••••
••••••

REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as 1/0 functions.

mode. Dedicated input or output functions can be implemented
as subsets of the 1/0 function.

Architecture configurations available in this mode are similar to
the common 20R8 and 20RP4 devices with various permutations
of polarity, 1/0 and register placement.

Registered outputs have eight product terms per output. 110's
have seven product terms per output.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
1/0. Up to eight registers or up to eight 110's are possible in this

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

elK

Registered Configuration for Registered Mode

-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- Pin 1 controls common ClK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as ClK &
OE.
OE

Combinatorial Configuration for Registered Mode

-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as ClK &
OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-100

1994 Data Book

Specifications GAL20VB

••••••
••••••
••••••
REGISTERED MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts
1(2) L)

V

"40
0

2(3)

4

12

8

"

20

24

28

32

36

PTO

0

-023(27)

~

0000

:s=

~

0200

3(4) L )
0320

-D-

:g

0"",

4(5)

D
0640

::P§:

0920

5(6)

'"""'
~

0960

:i=r

~

1240

6(7)

n
1280

~

1580

7(9)

"i.J-

n
1800

:s=

g

1880

8(10)
1920

if

D
2240

:i=r

~

2520

10(12)
11(13)

XOR-2560
AC1-2632

OLMC 21
XOR-2561
AC1-2633

OLMC 20
XOR-2562
AC1-2634

OLMC 19
XOR-2563
AC1-2635

OLMC 18
XOR·2564
AC1-2636

OLMC 17
XOR-2565
AC1-2637

OLMC 16
XOR-2566
AC1-2638

2200

9(11)

OLMC 22

D

~

OLMC 15
XOR-2567
AC1-2639

tr~

o11

~

~2

1(25)

1~2
0-

0(24)

CLIO

9(23)

0='

~J'

11

0~

_V""'O

8(21)

7(20)

16(19)

n
U-

k"l-

~

22(26)

15(18)

-

.c;.

~

""
"'"
1240

6(7)

D

"'"
7(9)

n

1800

8(10)

n

OLMC 19

:8:::::::1

OLMC 18

~
-=

"'"
1920

1"'>

~

:t=l=:=l

221)0

9(11)

XOR-2562
AC1·2634

~
~

"'"

OLMC 20

XOR-2563
AC1·2635

XOR-2564
AC1-2636

OLMC 17
XOR-2565
AC1·2637

OLMC 16

XOR-2566
AC1.2638

h
I

v

h

I

v

h
I

v

h

J

v

h

I

v

20(24)

~

--D 19(23)

~

18(21)

~

-10 17(20)

~

16(19)

D

"40

:§=:j OLMC 15
f3=::j

2520

10(12)

XOR-2567
AC1.2639

I&J"l

I

v

-Ir'iI 15(18)
~

CJ 14(17)

~

11(13) I>

h. j

CJ 13(16)

2703

64-USER ELECTRONIC SIGNATURE FUSES

12568, 2669. ....

I

Byte 7 Byte 6 ....
M
L

S
B

.. .. 2630. 26311
.. .. Byte 1 Byte 0

I

SYN·2704
ACO·2705

S
B

3-105

1994 Data Book

•

",

~HLatticem

Specifications GAL20V8C

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vcc + 1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Ambient Temperature (TA) ••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

VIL

Input Low Voltage

VIH

Input High Voltage

IlL'

Input or I/O Low Leakage Current

OV :<> VIN :<> VIL (MAX.)

hH

Input or I/O High Leakage Current

3.5V :<> VIN :<> Vee

MIN.

TYP."

MAX.

UNITS

Vss-O.5

-

0.8

V

Vcc+l

V

-100

J.lA

10

J.lA

0.5

V

-

V

2.0

-

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

VOH

Output High Voltage

10H = MAX. Yin = VIL or VIH

2.4

10L

-

Low Level Output Current

10H

High Level Output Current

los2

Output Short Circuit Current

Vee=5V

VOUT=0.5V

T A=25°C

-30

16

mA

-3.2

mA

-150

mA

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
.
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

3-106

1994 Data Book

Specifications GAL20V8C

••••••
......
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions
COM
PARAMETER

TEST
COND'.

-5

DESCRIPTION

MIN.

MAX

UNITS

tpd

A

Input or I/O to Combinational Output

1

5

ns

tco

A

Clock to Output Delay

1

4

ns

tct"

-

Clock to Feedback Delay

-

3

ns

tsu

-

Setup Time, Input or Feedback before Clock!

3

-

Hold Time, Input or Feedback after Clock!

0

-

ns

th

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

A

Maximum Clock Frequency with
No Feedback

twl

-

ten

B
B

fmax 3

twh

tdis

ns

142.8 -

MHz

166

-

MHz

166

-

MHz

Clock Pulse Duration, High

3

-

ns

Clock Pulse Duration, Low

3

-

ns

Input or I/O to Output Enabled

1

6

ns

OE to Output Enabled

1

6

ns

C

Input or I/O to Output Disabled

1

5

ns

C

OE to Output Disabled

1

5

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

8

pF

Vee =5.0V, V, =2.0V

CliO

I/O Capacitance

8

pF

Vee

=5.0V, VIIO =2.0V

"Guaranteed but not 100% tested.

3-107

1994 Data Book

Specifications GAL20VBB

••••••
••••••
••••••

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(1)

Commercial Devices:

Supply voltage V cc ....................................... -0.5 to + 7V
Input voltage applied .......................... -2.5 to V cc + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. --65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:
Ambient Temperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

0.8

V

Vcc+1

V

-

-

-100

~A

-

-

10

~

10L = MAX. Yin = VIL or VIH

-

0.5

V

10H = MAX. Yin = VIL or VIH

2.4

-

-

V

VIL

Input Low Voltage

Vss-O.S

VIH

Input High Voltage

2.0

IlL'

Input or I/O Low Leakage Current

OV s; VIN S; VIL (MAX.)

IIH

Input or I/O High Leakage Current

3.5V S; VIN S; Vee

VOL

Output Low Voltage

VOH

Output High Voltage

10L

Low Level Output Current

-

10H

High Level Output Current

-

los2

Output Short Circuit Current

Vec=5V

VOUT= 0.5V

TA=25°C

-30

24

mA

-3.2

mA

-150

mA

COMMERCIAL

Icc

Operating Power

VIL=0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH= 3.0V

L -7/-10

-

75

115

mA

L -15/-25

-

75

90

mA

Q -15/-25

-

45

55

mA

INDUSTRIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) The leakage current is due to the internal pull-up re&istor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25°C

3-108

1994 Data Book

Specifications GAL20V88

• •••••
......
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

TEST

PARAM. CONO'.

A

tpd

COM

COMIINO

COM/INO

INO

COM/INO

-7

-10

-15

-20

-25

DESCRIPTION
MIN.

MAX. MIN.

MAX. MIN.

MAX. MIN.

MAX. MIN.

MAX.

UNITS

Input or 1/0 to

18 outputs switching

3

7.5

3

10

3

15

3

20

3

25

ns

Comb. Output

11 output switching

-

7

-

-

-

-

-

-

-

-

ns

tco

A

Clock to Output Delay

2

5

2

7

2

10

2

11

2

12

ns

tcl"

Clock to Feedback Delay

-

3

-

6

-

8

-

9

-

10

ns

tsu

-

Setup Time, Input or Fdbk before Clk!

7

-

10

-

12

-

13

-

15

-

ns

th

-

Hold Time, Input or Fdbk after Clk!

0

0

-

0

-

0

-

ns

Maximum Clock Frequency with
External Feedback, l/(tsu + tco)

83.3

58.8

-

45.5

-

0

A

-

41.6

-

37

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, l/(tsu + tcf)

100

-

62.5

-

50

-

45.4

-

40

-

MHz

A

Maximum Clock Frequency with
No Feedback

100

-

62.5

-

62.5

-

50

-

41.7

-

MHz

twh

-

Clock Pulse Duration, High

5

-

8

-

8

-

10

-

12

-

ns

twl

-

Clock Pulse Duration, Low

5

-

8

-

8

-

10

-

12

-

ns

-

15

-

20

-

25

ns

15

-

18

-

20

ns

15

-

20

-

25

ns

18

-

20

ns

fmax3

ten

tdis

B

Input or I/O to Output Enabled

3

9

3

10

B

OE to Output Enabled

2

6

2

10

C

Input or I/O to Output Disabled

2

9

2

10

C

OE to Output Disabled

1.5

6

1.5

10

..

-

15

1) Refer to SWitching Test Conditions section .
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (TA

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

TEST CONDITIONS

C,

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

C'IO

I/O Capacitance

8

pF

Vcc = 5.0V, V'IO = 2.0V

"Guaranteed but not 100% tested.

3-109

1994 Data Book

II
I

~~~LatticeN

Specifications GAL20VB

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or

1/0 FEEDBACK

ClK

REGISTERED
OUTPUT

Combinatorial Output

INPUT or

1/0 FEEDBACK

r

----y
---' ~

I

CO."'NATIONAC"'-'

J

OUTPUT

Registered Output

OE

~

"'1~

~

REGISTERED
OUTPUT

Input or 110 to Output Enable/Disable

C~

--{~n

OE to Output Enable/Disable

t:}~Il

-c

~1.1

~OJ

1

i"'..... ~

0.8
4.50

4.75

~

-r--

II-PTL->H

.£E 0.9

5.25

5.00

6.00

4.75

1.1

"i
.~

1

.£~ 0.9
0.8
4.50

5.50

6.25

............

~

4.75

-PTL->H

............

5.00

~
5.50

5.'5

Supply Voltage (V)

Nonnalized Tpd vs Temp

Normalized Teo vs Temp

Normalized Tsu vs Temp

1.3

J- 1.1

PTL->H

1

EO.•

--

- - - PTH->L

~

Supply Voltage (V)

- - - PTH->L

o

,,--FALL

---.

0.8
4.50

1.3

Z 0.8

J---R1SE

1.1

~ 1
~ 0.9
.£

6.50

1.2

Supply Voltage (V)

R 1.'

~

Normalized Tsu vs Vee

Normalized Teo vs Vee

1..

o

~

1.2

~11

"i.

~~

~

" . i"""

1

EO.•

o

i"""

r--

1.'
::::J 1.3

RISE
FALL

~
".

~

~

~

~1.1

""

OJ

II""'

Z 0.8
0.7

0.7

1.'
1

~

0.9

Z

0.8

/'

"""""

0.7

on

on

Temperature (deg. C)

~ ~.5
,ll!

~ ~.75

-

...:-:

-

~

-r'

~

""""

---RISE.~
-FALL

-025

~ ~.5

;;

,ll!

~ ~.75

.

".'"

j---RISEI
-FALL I

4

l-

c

•

,/

0
-2

~~

---RISE.~
-FALL

Delta Teo vs Output Loading
8

S
a;

... / ....

Number of OUtputs SWitching

Delta Tpd va Output Loading

R

on

N

-1

Number of Outputs SWitching

~8

.

Temperature (deg. C)

E

-1

.5-

'"

Delta Teo vs # of Outputs
Switching

Delta Tpd va # of Outputs
Switching

1.o·25

""

l/

on

"I

N

Temperature (deg. C)

./

- - - PTH->L
--PTL->H

~

..--~

~- -

.....

- RISE
-FALL

~

-. V

V
50

100

150

200

250

300

..

-

_.
.--"",:" .
...

/
50

100

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-114

1994 Data Book

......
••••••
......

Specifications GAL20VB

GAL 20V8C-5: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

1.5

V

V

./

0.5

Voh veloh

Voh veloh

Vol va 101

~

3

gs::.

2

,

4.25

...........

~
~

r--...

...........

/'"
0.00

20.00

40.00

60.00

0.00

80.00

10.00

20.00

.!::!

1.10 t---+--+--~""----i

E

:£

(,) 1.2

.£
~ 1.1

1.00

0.90

+---+-----.rIfC---+---i

.!::!

+--2I'F'---+---+---i

o

Z 0.0

.f'----+--+---+----l

0.8

0.80
4.50

4.75

5.00

5.25

~

1

i'" "
-55

5.50

Q;

0

~

~

I
J

,

~

-"

==

.......
........

l/

~

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

15
20
25
30
35

r--..

"-

2.00

1.00

r-4.00

3.00

10h(mA)

Normalized Icc vs Freq_

1.40

o

........

-25

..........

25

.2

1.30

alN

1.20

/'
~

V

~ 1.10

r--.... .........

50

75

g

Z

i""--

100

125

/"

1.00

0.00

..,/

0.80
25

50

75

100

Frequency (MHz)

/

10

I

~ 2

...............

Input Clamp (Vik)

.

.s3
g

3.25
0.00

50.00

Temperature (deg. C)

Delta Icc vs Vin (1 input)

«

..........

1.50

Supply Voltage (V)

~4

40.00

~

3.5

1.3

1.20 , - - - , - - - , - - - , - - - - ,

(ij

..........

Normalized Icc va Temp

Normalized Icc vs Vee

al

3.75

10h(mA)

101 (mA)

1;1

30.00

g

40

,, ,
"

45
-2.00

1/

-1.50

-1.00

-0.50

0.00

Vik (V)

3-115

1994 Data Book

Specifications GAL20VB

·......
.....
••••••

GAL 20V8B-7/10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd
1.2
"01-0- 1.1

~~

VB

Vee

Normalized Teo

I-T-,-;:::====1
~

11--PTl.>H

1.2

1.1

~

f~~~·~-~-+~~~~~

(ij

~ 0.9

+---If---+--+----l

~ 0.9

--.

E 0.9
o

Z

.- --.

~

~~

4.75

5.00

5.25

4.50

5.50

.-~

~~

4.75

Normalized Tco

VB

;..--

I""'"

- - - RISE

~
"C

1.1

--FAll

.~

1

E 0.9

Temp

~ :-::""

"
{2.
~

~~

..-

0.8

1.3

1

~

09

Z

0.8

-

'"

"7
N

Temperature (deg. C)

~

·1

~

t3

--""""

~

p

~

- - - RISE

-1.5

~

--FALL

l'()5
~

-1

~

-1.5

.s

o

o

.... :;.. ...... ~ , --",'"

"'

,/

~

- - - RISE

~

FALL

·2

·2

Number of Outputs Switching

Number of Outputs Switching

Della Teo va Output Loading

Delta Tpd vs Output Loading
10

10

~---RISEI
FALL

t.,...t'
·2

o

"'

Temperature (deg. C)

Delta Tco vs # of Outputs
Switching

Delta Tpd vs # of Outputs
Switching

:;.
.. ....,.. "". --

--

I'"

'"

g.o.5

/

l/- -'"

!;'

0.7

Temperature (deg. C)

./

--PTL.>HI

1.1

(ij

/

---PTH.>ll

1.2

0.7

0.7

5.50

Normalized Tsu vs Temp

o

Z

0.8

5.25

1.4

o 1.2

(ij

5.00

Supply Voltage (V)

1.3

-~

~

0.9

Supply Voltage (V)

- - - PTH·>l
PTl·>H

r=-:.::.

1

--PTL·>H

0.8

4.50

1.3

1

1.1

"0

0.8

Normalized Tpd vs Temp

.~

- - - PTH·>l

~

FAll

E

Supply Voltage (V)

(ij

1-I -- RISE.~

--. .-

1

0.8 +----4---+---+-----1
4.50
4.75
5.00
5.25
5.50

"0 1.2
C.
..... 1.1
"0

Normalized Tsu vs Vee

Vee

1.2

11- - - PTH·>l
k---l---H

1

E

VB

./
I
~,1'=-

.

~---RISEI

"OJ'
.s

8

~

4

Jg

2

o

r3

~

·2
50

100

150

200

250

--FALL

.--

/'

...L r-l...,.ot'
50

300

I

100

150

-

V.

200

250

300

Output Loading (pF)

Output Loading (pF)

3-116

1994 Data Book

~~~Latticem

Specifications GAL20V8

••••••
••••••
••••••

GAL 20V8B-7i10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol

VB

Voh

101

VB

Voh

loh

VB

loh

4.5

/

0.75

>
~

0.5

,/
~

0.25

o

l/

0.00

........

~

~

3

s::.

~ 2

40.00

80.00

80.00

~ 1.10
.~ 1.00

~
0.90

--

4.75

VB

10,00 20.00 30.00 40.00 50.00 80.00

Vcc

Normalized Icc

.!!

V
~

'i
.t:!

~~

5.25

5.50

......

1.1
1

0.9

·55

VB

·25

Vln (1 Input)

o

.s<-

1\
I

J

" ..... ....
......

0.00 O.SO 1.00 I.SO 2.00 2.SO '.00 '.SO 4.00

Vin (V)

2.00

3.00

4.00

VB

Normalized Icc

Temp

VB

Freq.

V

,g

"

'i

i'"

0

'" ...... '"

so

25

./

1.10

~

.!l!

75

100

125

~
o

Z

1.00

.",-

0.90
0.80
25

so

75

100

Frequency (MHz)

Input Clamp (Vlk)

~.

.s.

1.00

loh(mA)

Temperature (deg. C)

<

,

0.00

o 1.20

r-....

Supply Voltage (V)

Delta Icc

r--

1.30

o.e
5.00

-

I--..

loh(mA)

O.BO

•. SO

""-

3 .•

0.00

100.00

1.2

-g

2

~

o

20,00

Normalized Icc

'ai
0

r-.

3.75

1.20

.!!.,

4.25

~

io"'"
101 (rnA)

~~

-r--

r--. '-

~

,

10
20
30
40

so
eo
70

eo

~

I

L

,

I
I

90
100
·2.00

·1.SO

·1.00

-C.SO

0.00

Vik (V)

3-117

1994 Data Book

..
I
I

H~Lattice~

Specifications GAL20V8

••••••
••••••
••••••

GAL 20V8B-15/25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee

~

I---PTH->L

-- ......

1

I-PTL->H

-

"'- ... ...

~ 0.9

~

1.1

~

1

4.75

4.50

E

~ 0.8

~
til
Z

O,B

1

,

- - - PTH->L
--PTL->H

.............

E

t---+--+---;---;

~ 0.8

0.•
•.SO

4.75

~

5.25

5.00

6.60

Normalized Tpd va Temp

Normalized Teo va Temp

Normalized Tau va Temp

PTL->H

.,. .. V

~

8

1.2

~11

~

~- -

~
~

"

'iii

!..",ooo ~

E 0.9

Ir""

- RSE
FALL

o

Z 0.•

~

....

:::J

P

l...- ~

·25

26

50

76

100

12

~

1.1

'iii

1

0

26

60

75

100

!

- - _. - 10""--1/
,
,;'"

-1

~

~ -1.5

,

~

j

~

2S

125

60

75

100

126

Temperature (deg. C)

- .. .. ,;'"- -" .".

E.o·5

;'

~

---RISE~

~ -1.5

--FALL

",

~

-1

~

,

~

- - - RISE.
FALL

~

-2

1

1

5

Number of Outputs Switching

Number of Outputs Switching

Delta Tpd va Output Loading

Delta Teo vs Output Loading
10

10

~---RISE

~

-FALL:

l/

..

"

I

Delta Teo va # of Outputs
Switching

-2

-2

,.

0 .•

Temperature (deg. C)
Delta Tpd va # of Outputa
Switching

-0.5

--PTL->H

So.•

z

·26

Temperature (deg. C)

g

- - - PTH->L,

0.7

·65

126

1.3

{!!.

0.7

0.7

..
. ,..

1.'

1.3

- - - PTH->L

·65

~

Supply Vollage (V)

1

EO.•

~
'iii

~

Supply Vollage (V)

1.1

o

1.1

Supply Vollage (V)

1.3

t-

L-~~

~

0.• -1---1----1---1---1
4.75
5.00
5.25
6.50
• .50

S.SO

5.25

5.00

ioc::---+--H

'iii

0 .•

"C 1.2
0-

1.2

1.2,-,--r;;====:::;'1

~,.,

~

Normalized Tau va Vee

Normalized Teo va Vee

1.2

~>

~~

~---RISE
--FALL

8 •

:/

~

l-

S
~

.1'

.
0

-2

.y

~

.... .
,,~

..

........:
..

o

SO

100

150

200

260

300

50

100

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-118

1994 Data Book

Specifications GAL20V8

......
......

GAL 20V8B-15/25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh vs loh

Voh vs loh

Vol vs 101

4.25

1.5

l.,; ~

I..'

0.5

~

.....

~io""

..... i-" i-"
0.00

--

i'-"",

20.00

40.00

60.00

~ 1.10

0.90

10.00 20.00 30.00 40.00

so.oo

0.00

60.00

~

......-

~

1.1

~

1

til

........

5.00

~ .......

-- ....... r-.. -

0.9

5.50

5.25

-55

-25

Supply Voltage (V)

/

J i"'---

1
t"-

-

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

VineY)

3.00

4.00

50

75

100

125

~

1.30
1.20

. /I '

~ 1.10
til

E
1.00
o
Z

0.90

/'

./

~

0.80
25

50

75

100

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

\

25

Temperature (deg. C)

A

2.00

Normalized Icc vs Freq.

g

0.8
4.75

1.00

-

1.40

E

:£

--..

loh(mA)

Normalized Icc vs Temp

0.80
4.50

j"'-....

3.5

1.2

......",.V

I"

loh(mA)

Normalized Icc vs Vee

-g

3.75

>
3.25

0.00

100.00

80.00

1.20

~~

-8

r-. ~

o
lol(mA)

.t::! 1.00

~

~

~

10
20
30
40

I
I
I

50
80

70
80
90
100
-2.00

I

,

I

I
-1.50

-1.00

-0.50

0.00

Vik(V)

3-119

1994 Data Book

~~~Latticem

Notes

••••••
••••••
••••••

3-120

1994 Data Book

GAL20VBZ
GAL20V8ZD

••••••
••••••
••••••

Zero Power E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM

FEATURES

• ZERO POWER E"CMOS TECHNOLOGY
- 100~ Standby Current
- Input Transition Detection on GAL20V8Z
- Dedicated Power-down Pin on GAL20V8ZD
- Input and Output Latching During Power Down

VOIQ

• HIGH PERFORMANCE E"CMOS TECHNOLOGY
-12 ns Maximum Propagation Delay
- Fmax = 83.3 MHz
- 8 ns Maximum from Clock Input to Data Output
- TIL Compatible 16 mA Output Drive
- UltraMOS- Advanced CMOS Technology

VOIQ

IIDPP
1/010

• E" CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
-100% TeatedlGuaranteed 100% Yields
- High Speed Electrical Erasure «lOOms)
- 20 Year Data Retention

VOIQ

VOIQ

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmeble Output Polarity
- Architecturally Similar to Standard GAL20V8

VOIQ

• PRELOAD AND POWER-QN RESET OF ALL REGISTERS
- 100% Functional Testability

VOIQ

• APPLICATIONS INCLUDE:
- Battery Powered Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing

VOIQ

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

liCE

DESCRIPTION

The GAL20vaz and GAL20V8ZD. at 100 IIA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z1ZD is manufactured using Lattice's advanced zero
power PCMOS process, which combines CMOS with Electrically
Erasable (P) floating gate technology.
The GAL20V8Z uses Input Transition Detection (lTD) to put the
device in standby mode and is capable of emulating the full functionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby
mode. It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
LATIICE is able to guarantee 100% field programmability and
functionality of all GAL products. LATIICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

PIN CONFIGURATION

DIP
Vee

Chip Carrier

:s!.l

0

z

8

>

-

28

IIDPP

1

~

5

7

MC
1 •

1/0/0

28

1/0/0

2S

GAL20V8Z
GAL20V8ZD
Top View

2'

IIOIQ

1/0/0

"OIQ

1/0/0

HC

1/0/0

21

UOIQ

18 19

UO/Q

1/0/0

UOIQ

I

1'12

14

18

- - ~ li Iii!

~

GND

1/0E

Copyright 0 1994 lattice Semiconductor Corp. An brand or product names are trademarks or registered trademarks of their respective holders, The specifications and information herein are
oubjecl to chango wiIhout notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct, Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 68HI118; 1-800-FASTGAL; FAX (503) 681-3037

3-121

1994 Data

Book

..

~~~Lattice~

Specifications GAL20V8Z
GAL20VBZD

••••••
••••••
••••••

GAL 20V8Z/ZD ORDERING INFORMATION
GAL20V8Z: Commercial Grade Specifications
Tpd (ns)

Tsu(ns)

Tco(ns)

12

10

8

15

15

Icc (mA)

10

Ordering #

ISB (!lA)

Package

55

100

GAL20V8Z-12QP

24-Pin Plastic DIP

55

100

GAL20V8Z-12QJ

28-Lead PLCC

55

100

GAL20V8Z-15QP

24-Pin Plastic DIP

55

100

GAL20V8Z-15QJ

28-Lead PLCC

Ordering #

Package

GAL20V8ZD: Commercial Grade SpeCifications
Tpd (ns)

Tsu (ns)

Tco(ns)

12

10

8

15

15

Icc (mA)

10

ISB (!lA)

55

100

GAL20V8ZD-12QP

24-Pin Plastic DIP

55

100

GAL20V8ZD-12QJ

28-Lead PLCC

55

100

GAL20V8ZD-15QP

24-Pin Plastic DIP

55

100

GAL20V8ZD-15OJ

28-Lead PLCC

PART NUMBER DESCRIPTION
XXXXXXXX - XX

DevIce Na...
GAL20V8Z (Zero Power ITO)
GAL20V8ZD (Zero Power DPP)

~

Blank =Commercial

Speed (ns) _ _ _ _ _ _--1

Package
P = Plastic DIP
J= PLCC

Active Power - - - - - - - - - '
Q =Quarter Power

3-122

1994 Data Book

Specifications GAL20V8Z
GAL20V8ZD

••••••
••••••
••••••
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The

XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the ACl bit of each of the macrocells
controls the inpuVoutput configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL20V8Z1ZD. The information given on these architecture bits
is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.

COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. Most compilers also have the
ability to automatically select the device type, generally based on
the register usage and output enable (OE) usage. Register usage
on the device forces the software to choose the registered mode.
All combinatorial outputs with OE controlled by the product term
will force the software to choose the complex mode. The software
will choose the simple mode only when all outputs are dedicated
combinatorial without OE control. For further details, refer to the
compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.

In complex mode pin 1(2) and pin 13(16) become dedicated inputs and use the feedback paths of pin 22(26) and pin 15(18) respectively. Because of this feedback path usage, pin 22(26) and
pin 15(18) do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18(21) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.
When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20V8ZD, special attention
must be given to pin 4(5) (DPP) to make sure that it is not used
as one of the functional inputs.

In registered mode pin 1(2) and pin 13(16) are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode.

3-123

1994 Data Book

Specifications GAL20V8Z

......
......
.....•

GAL20V8ZD

REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Registered outputs have eight product terms per output. I/O's
have seven product terms per output.

Architecture configurations available in this mode are similar to
the common 20R8 and 20RP4 devices with various permutations
of polarity, I/O and register placement.

Pin 4(5) is used as dedicated power-down pin on GAl20V8ZD.
It cannot be used as functional input.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

elK

Registered Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- Pin 1 (2) controls common ClK for the registered
outputs.
- Pin 13(16) controls common OE for the registered
outputs.
- Pin 1 (2~in 13(16) are permanently configured as
ClK& OE.

OE

Combinatorial Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1(2) & Pin 13(16) are permanently configured as
ClK & OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-124

1994 Data Book

H~LatticeM
••••••
......
......

Specifications GAL20V8Z
GAL20V8ZD

REGISTERED MODE LOGIC DIAGRAM
1(2)

DIP (PLCC) Package Pinouts

D---l>----

2040
0

2(3)

4

8

12

16

20

24

28

36

PTO

D-

O
k.

0000

~

0280

3(4)

32

D0320

~

H=

0600

•

4(5)

D0640

:!:t=

=t3=

0920

5(6)

D0960

§:
:!:t=

1240

6(7)

D--1280

B=
-tC

1580

7(9)

D1600

1880

8(10)

D--1920

2200

9(11)

OLMC 3
XOR-2562
ACl-2634

OLMC 4
XOR-2563
ACl-2635

OLMC 5
XOR-2564
ACl-2636

OLMC 7

1.J-

XOR-2565
ACl-2637

XOR-2566
ACl-2638

OLMC 8
XOR-2567
ACl-2639

2520

D

XOR-2561
ACl-2633

:R-

§'

11(13)

OLMC 2

~

2240

D

XOR-2560
ACl-2632

OLMC 6

D

10(12)

OLMC 1

rr"

rr
~r'
rr

22(26)

21(25)

20(24)

rJO

0°

rr

r1[J~

or-..

A

A

2700

23(27)

19(23)

18(21)

17(20)

16(19)

15(18)

<:J 14(17)
OEO 13(16)

SYN-2704
ACO-2705
MSB

• Note: Input not available on GAL20V8ZD

3-125

1994 Data Book

~~~Latticem

Specifications GAL20V8Z
GAL20V8ZD

••••••
••••••
••••••

COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2)
and 13(16) are always available as data inputs into the AND array.

Architecture configurations available in this mode are similar to
the common 20L8 and 20P8 devices with programmable polarity
in each macrocell.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD.
It cannot be used as functional input.

Up to six 1I0's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the 1/0 function. The
two outer most macrocells (pins 15(18) & 22(26)) do not have input
capability. Designs requiring eight 1I0's can be implemented in
the Registered mode.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial 1/0 Configuration for Complex Mode
- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 16(19) through Pin 21 (25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode
- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 15(18) and Pin 22(26) are configured to this
function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-126

1994 Data Book

Specifications GAL20V8Z
GAL20V8ZD

......
••••••
••••••

COMPLEX MODE LOGIC DIAGRAM
1(2)

0

2(3)

DIP (PLCC) Package Pinouts

D----1>-------D-

4

6

12

16

20

24

32

36

2640
PTO

--

~--

""
~

0000

0260

3(4)

26

~

D-

l

OLMC 1

•

4(5)

D
0640

5(6)

D

OLMC 6

~

OLMC 7

D1920

2200

D
2240

r>-

XOR·2563
AC1·2635

~~

{:j--

1880

11(13)

OLMC 4

OLMC 5

{:j--

1600

10(12)

XOR·2562
AC1·2634

:13=:=

D

........

XOR·2561
AC1·2633

.0-

1560

9(11)

OLMC 3

~

1260

8(10)

~

~

1240

7(9)

OLMC 2

D
0960

6(7)

~
:8==

0920

n-

:13=:=
{:j--

2520

l

~

~

22(26)

II

XOR-2560
AC1·2632

0320

0600

~

--cJ.23(27)

XOR·2564
AC1·2636

2-J
C]--------------2640
0

2(3)

4

8

12

16

2

XOR·2566
AC1·2638

-L1I 16(19)

D

~

2240

:t=l==I
10(12)

OLMC 4

OLMC5

~

9(11)

h

I

n
1800

8(10)

XOR·2562
AC1·2634

~

1560

7(9)

XOR·2561
AC1·2633

D
0980

6(7)

.c,.

~

0920

5(6)

~

OLMC 2

,.....,.

2520

OLMC 8
XOR·2567
AC1·2639

l

~

15(18)

CJ 14(17)

~

11(13)

t::l
I
L..r"li

CJ 13(16)

2703

SYN-2704
ACO-2705
MSB

* Note: Input not available on GAL20V8ZD

3-129

1994 Data Book

~~~Latticem
••••••

Specifications GAL20V8Z

GAL20V8ZD

••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:
AmbientTemperature (TA) ............................... 0 to 75°C
Supply voltage (Vcc)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vcc ......................................... -.5 to +7V
Input voltage applied .......................... -2.5 to Vcc + 1.0V
Off-state output voltage applied .......... -2.5 to Vcc + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

VIL

Input Low Voltage

Vss-D.S

VIH

Input High Voltage

2.0

Input or I/O High Leakage Current

3.5V ~ Y,N ~ Vcc

-

VOL

Output Low Voltage

10L = MAX. Yin = V,L or V,H

-

VOH

Output High Voltage

2.4

IlL
hH

Input or I/O Low Leakage Current

OV ~ Y,N ~ V,L (MAX.)

IOH = MAX. Yin = V,L or V,H
10H = -100 I1A Yin = V,L or V,H

10L

Low Level Output Current

10H

High Level Output Current

los'

Output Short Circuit Current

TA=25°C

-

MAX.

UNITS

0.8

V

Vcc+1

V

-10

I1A

10

I1A

-

0.5

V

-

-

V

-

V

16

mA

-3.2

mA

-30

-

-150

mA

Vcc-1

Vcc=5V VOUT=0.5V

TYP."

COMMERCIAL
ISB

Stand-by Power
Supply Current

V,L=GND V,H = Vee Outputs Open

Z-121-15
ZD-121-15

-

50

100

I1A

Icc

Operating Power
Supply Current

V,L= 0.5V V,H=3.0V
ftoggle = 15 MHz Outputs Open

Z-121-15
ZD-121-15

-

-

55

mA

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA = 25'C, f = 1.0 MHz)
SYMBOL

PARAMETER

MAXIMUM"

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

C'IO

I/O Capacitance

10

pF

Vee = 5.0V, Vvo = 2.0V

'Guaranteed but not 100% tested.

3-130

1994 Data Book

Specifications GAL20V8Z

••••••
••••••
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAMETER

TEST
COND'.

COM

COM

-12

-15

DESCRIPTION
MIN.

MAX.

MIN.

MAX.

UNITS

A

Input or I/O to Combinational Output

3

12

3

15

ns

tco

A

Clock to Output Delay

2

8

2

10

ns

tcf2

-

Clock to Feedback Delay

-

6

-

7

ns

tsu

-

Setup Time, Input or Feedback before Clocki

10

15

-

ns

Hold Time, Input or Feedback after Clocki

0

0

-

ns

A

Maximum Clock Frequency with
Extemal Feedback, 1/(tsu + tco)

55

-

40

-

MHz

A

Maximum Clock Frequency with
Intemal Feedback, 1/(tsu + tcf)

62.5

-

45.5

-

MHz

A

Maximum Clock Frequency with
No Feedback

83.3

-

62.5

-

MHz

Clock Pulse Duration, High

6

-

8

Clock Pulse Duration, Low

6

-

8

-

ns

twl

-

ten

B

Input or I/O to Output Enabled

-

12

-

15

ns

B

OE to Output Enabled

-

12

-

15

ns

C

Input or I/O to Output Disabled

-

15

ns

OE to Output Disabled

-

15

C

12

-

15

ns

tas

-

Last Active Input to Standby

60

140

50

150

ns

tsa4

-

Standby to Active Output

6

13

5

15

ns

tpd

th

fmax 3

twh

tdis

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.

STANDBY POWER TIMING WAVEFORMS
Icc-------,

POWER
INPUT or
I/O FEEDBACK

OE

* Note: Rising clock edges
are allowed during tsa but
outputs are not guaranteed.

ClK

OUTPUT

3-131

1994 Data Book

I

iii
I
I
I

~~~LatticeT"
••••••
......
••••••

Specifications GAL20V8ZD

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

tpd

TEST
COND'.

COM

COM

-12

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION

A

Input or 110 to Combinational Output

3

12

3

15

UNITS
ns

tco

A

Clock to Output Delay

2

8

2

10

ns

tcl"

-

Clock to Feedback Delay

-

6

-

7

ns

tsu

-

Setup Time, Input or Feedback before Clocki

10

15

-

Hold Time, Input or Feedback after Clocki

0

-

ns

th

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

55

-

40

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

62.5

-

45.5

-

MHz

A

Maximum Clock Frequency with
No Feedback

83.3

-

62.5

-

MHz

twh

-

Clock Pulse Duration, High

6

-

8

-

ns

twl

-

Clock Pulse Duration, Low

6

-

8

-

ns

ten

B

Input or I/O to Output Enabled

-

15

ns

B

OE to Output Enabled

-

12
12

15

ns

C

Input or I/O to Output Disabled

-

15

15

ns

C

OE to Output Disabled

-

12

-

15

ns

fmax 3

tdis

0

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

3-132

1994 Data Book

H~Lattice'"

Specifications GAL20V8ZD

••••••
••••••
••••••

DEDICATED POWER-DOWN PIN SPECIFICATIONS
Over Recommended Operating Conditions

PARAMETER

twhd
twld

TEST
COND'.

-

COM

COM

-12

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

DPP Pulse Duration High

12

-

15

-

ns

DPP Pulse Duration Low

25

-

30

-

ns

Valid Input before DPP High

5

-

8

ns

ACTIVE TO STANDBY

-

Valid OE before DPP High

0

-

0

Valid Clock Before DPP High

0

-

0

-

Input Don't Care after DPP High

-

2

-

5

ns

OE Don't Care after DPP High

-

6

ns

8

-

9

Clock Don't Care after DPP High

11

ns

DPP Low to Valid Input

12

-

15

-

ns

DPP Low to Valid OE

16

-

20

-

ns

tdlcv

-

DPP Low to Valid Clock

18

-

20

-

ns

tdlov

A

DPP Low to Valid Output

5

24

5

30

ns

tivdh
tgvdh
tcvdh
tdhix
tdhgx
tdhcx

ns
ns

STANDBY TO ACTIVE
tdliv
tdlgv

1) Refer to Switching Test Conditions section.

DEDICATED POWER-DOWN PIN (DPP) TIMING WAVEFORMS
DPP

INPUT or
110 FEEDBACK

OE

ClK

OUTPUT

3-133

1994 Data Book

Specifications GAL20V8Z
GAL20V8ZD

••••••
••••••
••••••
SWITCHING WAVEFORMS

INPUT or
1/0 FEEDBACK

ClK
REGISTERED
OUTPUT

Combinatorial Output

Registered Output

OE

Input or VO to Output Enable/Disable

REGISTERED
OUTPUT

-~[~]~

OE to Output EnableIDisable

elK

r'"'
t
~1~1l

1- -- RISE.~

iii

II-PTL->H

I-FAlL

1-12

-.......;;.

~ 0.9

0.8
4.50

4.76

0.8
4.50

5.50

6.25

6.00

..:.:. --

-.............

SUpply Voltage (V)

- - - PTH->L

I- 1.1

--PTL->H

1

8

0.9

Z

O.B

0.8
4.50

..".

~

.A

8

1.2

!;:;

1.1

.Il!
Gi

1

~

0.8

...

~

,,-

~~ -

- RLSE
--FALL

" . i-""'"

-

~

~

......

1.3

- - - PTH->Lr

1.2

-PTL->Hr

jl.l

iii

1

O.B

~

;
Temperature (deg. C)

~

-1

- - --

o

~

~ -1.5

-

goO.5
~

---RISE~

Jl!

~

~

8

Temperature (deg. C)

Delta Teo va. of Outputs
Switching

Delta TpcI v•• of Outputs
Switching

.
." .

"

0.7

Temperatura (deg_ C)

goO.6

ii'"

~~

8 0." ."

Z

~

I........

ill

~

6.50

Normalized Tau va Temp

0.7

0.7

""'"

1.4

E 0.9

~

5.26

5.00

4.75

SUpply Voltage (V)

1.3

X 1.2
iii

0.9

6.50

5.25

"'- ............

1

o

Normalized Teo va Temp

Normalized TpcI va Tamp

"i

E

Supply Voltage (V)

1.3

.Il!

6.00

~

1.1

Z

PTH->~t

- - -PTL->H

".

i"i'

- -"'-

4.75

1.3

-1

Jl!

~

~

~ -1.6

-FALL

~~

......

......

---RISE}
-FALL

-2

-2

2

Number of Outputs SWitching
Delta TpcI va Output Loading
10

~---RISEI

I

.... ~

~---RISEI

..

~

,

FALL

./ ,

~

LA"

50

,

100

7

Delta Teo v. Output Loading

10

FALL

6

Number of Outputs Switching

~
150

200

250

300

OUtput Loading (pF)

-2

I

~

V.

V

,

V

.

b?'
50

100

150

200

260

300

Output Loading (pF)

3-138

1994 Data Book

Specifications GAL20V8Z

GAL20V8ZD

••••••
••••••
••••••
TYPICAL AC AND DC CHARACTERISTICS

Voh vsloh

Voh vsloh

Volvslol
1.5

~

1.25

>
~ 0.75
>

-r-- r--Ioo. -r--

If"

?;

V

g

~

0.5

~

0.25

lL

0.00

3

..c:

2

'"
40.00

20.00

1.2

1.30

~

1.20
1.10

E 0.90
o

Z

lL"

1.00

0.80

./

V

./

5.00

5.25

-25

r- I--

al

1 ,.

00

I

J

"' .......

""

1'00...

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin(V)

0

25

50

75

100

o

125

30

60
70

80

25

50

75

100

Frequency (MHz)

Normalized Icc vs Freq. (ITO)

F
II

...g :~
=

-'"

~

10

2

-;/

~ 0.90

Input Clamp (Vik)

~

.- ~

1.10

.!:!!

Temperature (deg. C)

20

0,

1.30
~ 1.20

0.80
-55

5.50

Delta Icc vs Vln (1 input)

.l!l

Normalized Icc vs Freq. (DPP
& ITO> 10MHz)

0.8

4.75

Supply Voltage (V)

a;

2.5 ~--4---I---I----l
1.00
2.00
3.00
4.00
0.00

loh(mA)

" '" ~

0.70

4.50

\

Normalized Icc vs Temp

Normalized Icc vs Vee

~

~3.5

loh(mA)

101 (mA)

~
al

4

10.00 20.00 30.00 40.00 50.00 80.00

0.00

80.00

4.5 ~---+--+--I----l

~ ~1\~--I-_-+-_4-----l

I

U

I

al •.•
-!:!

I

'iii

E·"
~ •.2

I

I

90
-1.00

0.8

.!:!

-0.80

-0.60

-0.40

Vik (V)

3-139

-0.20

0.00

~

,.

'00

J

7
7

...

,

10000

Frequency (KHz)

1994 Data Book

~~~Latticem

Notes

••••••
••••••

••••••

3-140

1994 Data Book

GAL20VPB
High-Speed E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES
• HIGH DRIVE E2CMOS'" GAL'" DEVICE
- TTL Compatible 64 mA Output Drive
-15 ns Maximum Propagation Delay
- Fmax = 80 MHz
- 10 ns Maximum from Clock Input to Data Output
- UltraMOS'" Advanced CMOS Technology

I/CLK - t>

1/0/0

• ENHANCED INPUT AND OUTPUT FEATURES
- Schmitt Trigger Inputs
- Programmable Open-Drain or Totem-Pole Outputs
- Active Pull-Ups on All Inputs and I/O pins

1/0/0

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «lOOms)
- 20 Year Data Retention

1/0/0

1/0/0

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Architecturally Compatible with Standard GAL20V8

1/0/0

1/0/0

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Ideal for Bus Control & Bus Arbitration Logic
- Bus Address Decode Logic
- Memory Address, Data and Control Circuits
- DMA Control

1/0/0

1/010

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
IIOE

DESCRIPTION
The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control
applications. The GAL20VP8 is manufactured using Lattice's
advanced E2CMOS process which combines CMOS with Electrically Erasable (P) floating gate technology. High speed erase
times «lOOms) allow the devices to be reprogrammed quickly and
efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design
flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The 64mA output drive eliminates the need
for additional devices to provide bus-driving capability.
Unique test circuitry and reprogram mabie cells allow complete AC,
DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

PIN CONFIGURATION
PLCC

~

~

g CJz

28
I

Vee

DIP

2.

5

I/O/Q

2S

I/O/Q

1/0/a

VO/Q

7

GAL20VP8

23

1/0/0

•

Top View

21

GND

GND

,.

110/0

I/O/Q

NC

I

110/0

I/O/Q

NC

111

12

,.
Ig

16
CJ

z

18

1/0/0

I/O/Q

- g
" ~

I/O/Q
VO/Q

VOE

Copyright © 1994 Lattice Semiconductor Corp. AU brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP.• 5555 N.E. Moore Ct.. Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-141

1994 Data Book

•

......
......

Specifications GAL20VPB

••••••

GAL20VP8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

15

8

10

115

GAL20VP8B-15LP

Ordering #

Package

115

GAL20VP8B-15LJ

28-Lead PLCC

25

10

15

115

GAL20VP8B-25LP

24-Pin Plastic DIP

115

GAL20VP8B-25LJ

28-Lead PLCC

24-Pin Plastic DIP

PART NUMBER DESCRIPTION

xxxxxxxx - xx x x

GAL20VP8B Dovloe Nom.

~

Speed (ns)
L

=Low Power

Power - - - - - - - - - '

X

LG".'

Blank

' - - - - - - Package

P

=Commercial

=Plastic DIP

J = PLCC

3-142

1994 Data Book

Specifications GAL20VPB

......
••••••
••••••

OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any

of the three modes, while the AC1 and AC2 bit of each of the
macrocells controls the input/output and totem-pole/open-drain
configuration. These two global and 24 individual architecture bits
define all possible configurations in a GAL20VP8. The information
given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these
architecture bits from the pin definitions, so the user should not
need to directly manipulate these architecture bits.

COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. Most compilers also have the
ability to automatically select the device type, generally based on
the register usage and output enable (OE) usage. Register usage
on the device forces the software to choose the registered mode.
All combinatorial outputs with OE controlled by the product term
will force the software to choose the complex mode. The software
will choose the simple mode only when all outputs are dedicated
combinatorial without OE control. For further details, refer to the
compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
In registered mode pin 1(2) and pin 12(14) are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode.

In complex mode pin 1(2) and pin 12(14) become dedicated inputs and use the feedback paths of pin 22(26) and pin 14(17) respectively. Because of this feedback path usage, pin 22(26) and
pin 14(17) do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins (pins
17(20) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.
In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or opendrain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.

3-143

1994 Data Book

Specifications GAL20VPB

••••••
••••••
......
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Registered outputs have eight product terms per output. I/O's
have seven product terms per output.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

elK

Registered Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) controls common ClK for the registered
outputs.
- Pin 12(14) controls common OE for the registered
outputs.
- Pin 1(2) & Pin 12(14) are permanently configured as
ClK&OE.

OE

Combinatorial Configuration for Registered Mode
-SYN=O.
-ACO=1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) & Pin 12(14) are permanently configured as
ClK&OE.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-144

1994 Data Book

Specifications GAL20VPB

••••••
••••••
••••••
REGISTERED MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts
1(2) D

"v

~o

4

8

12

16

20

24

28

32

36

V640

PTD

Z

0000

~
~

0280

2(3) D
0320

~
~

0800

3(4) D

~

0920

4(5) D

~

1240

5(6) D
1280

-6-

=§:
1560

XOR·2561
AC1·2633
AC2·2707

XOR·2562
AC1-2634
AC2·270B

'"'"'

XOR·2563
AC1·2635
AC2·2709

OLMC 5
XOR·2564
AC1·2636
AC2·2710

~

1600

-6-

~

1860

B(10) '"'"'
~

1920

~
2200

1...1-

0

OLMC 6
XOR·2565
AC1·2637
AC2·2711

OLMC 7
XOR·2566
AC1·2638
AC2·2712

OLMC 8

2240

XOR·2567
AC1·2639
AC2·2713

2520

10(12) I>
11(13)

OLMC 2

OLMC 4

0960

9(11)

XOR·2560
AC1-2632
AC2·2706

OLMC 3

0640

7(9)

OLMC 1

2703

24{2B)

a

23(27)

D

VJ-

22(26)

~~

21 (25)

D~

20(24)

DO
tr

D°
tr~
o~
0-

....

D

a

A

"

19(23)

17(20)

16(19)

15(18)

14(17)

-

13(16)

-

12(14)

OEn

SYN·2704
ACO-2705

MSB

3-145

1994 Data Book

Specifications GAL20VPB

••••••
••••••
••••••
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or I/O functions.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 14(17) & 22(26)) do not have input
capability. Designs requiring eight I/O's can be implemented in
the Registered mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2)
and 12(14) are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial 110 Configuration for Complex Mode
- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=O defines open-drain output.
- Pin 15(18) through Pin 21 (25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode
- SYN=1.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=O defines open-drain output.
- Pin 14(17) and Pin 22(26) are configured to this
function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-146

1994 Data Book

~~~Latticern
......

Specifications GAL20VPB

••••••
••••••

COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1(2)

"v

D

~o

4

8

12

,.

-a 24(28)
20

24

28

32

PTD

2840

Z

0000

0280

2(3)

3.

D-0320

0600

/

~

OLMC 1

~

OLMC 2

-0-

OLMC 3

3(4) l...)--

0840

~

0920

4(5)

D0960

~

1240

5(6)

D1280

~

7(9)

1600

~
1880

8(10)

-<-J-

~
~

1920

=§=
B=

2200

9(11)

0
2240

XOR-2560
AC1-2632
AC2-2706

10(12)

D

1

11(13)

D

~

n

--a 22(26)

v

U-

IT

20(24)

XOR-2562
AC1-2634
AC2-2708

OLMC 4
XOR-2563
AC1-2635
AC2-2709

XOR-2564
AC1-2636
AC2-2710

OLMC 6
XOR-2565
AC1-2637
AC2-2711

OLMC 7
XOR-2566
AC1-2638
AC2-2712

§:= OLMC 8

2520

r---cJ 23(27)

D~ 21(25)

XOR-2561
AC1-2633
AC2-2707

OLMC 5

-D1580

I

XOR-2567
AC1-2639
AC2-2713

Q. j

n
n

J".,.

J

P-j
~

19(23)

17(20)

16(19)

15(18)

--D 14(17)

CJ 13(16)
CJ 12(14)

2703

SYN-2704
ACO-2705
MSB

3-147

1994 Data Book

H~Lattice~

Specifications GAL20VP8

••••••
••••••
••••••

SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has programmable polarity.

Vee

Pins 1(2) and 12(14) are always available as data inputs into the
AND array. The center two macrocells (pins 17(20) & 19(23)) cannot be used in the input configuration.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

o

- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 17(20) & 19(23) can be
configured to this function.
Combinatorial Output Configuration for Simple Mode

Vee

-SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pins 17(20) & 19(23) are permanently configured to
this function.

o

Dedicated Input Configuration for Simple Mode
-SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 17(20) & 19(23) can be
configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-148

1994 Data Book

Specifications GAL20VPB

••••••
......
......
SIMPLE MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts
1(2) D - - - t > > - - - - - - - - - - - -

~o

-~~

• •

12

I.

20

2•

2.

32

36

--,....,

~

0280

0

l
0320

3(4) .-..
~

-

CZ

0000

2(3)

j640

PTD

0600

~
=B=

OLMC 3

=B=
=B=

OLMC 4

=B=
=B=

OLMC 5

0640

~

0920

4(5) 0
0960

-0-

1240

5(6)

D---------I:6==
1280

1560

-0-

~

7(9) ~

lBOO

~

1880

8(10) 0
1920

~

2200

9(11)

D
2240 -

10(12)
11(13)

.-..

=B=
=B=

2520

XOR-2560
AC1-2632
AC2-2706

OLMC 2

~

r-Cl:23(27)

---

OLMC 1

XOR-2561
AC1-2633
AC2-2707

XOR-2562
AC1-2634
AC2-2708

XOR-2563
AC1-2635
AC2-2709

XOR-2564
AC1-2636
AC2-2710

OLMC 6
XOR-2565
AC1-2637
AC2-2711

OLMC 7
XOR-2566
AC1-2638
AC2-2712

OLMC 8
XOR-2567
AC1-2639
AC2-2713

l

- - 0 24(28)

v

:=J ra

n
C1
v

21(25)

1 - 20(24)

f-O 19(23)

n
v

--D 17(20)

n
v

--D 16(19)

n
v

--D 15(18)

l

v

--0 14(17)

I

CJ 13(16)

~

D-

•

~ 22(26)

CJ 12(14)

2703

SYN-2704
ACO-2705
MSB

3-149

1994 Data Book

Specifications GAL20VPB

••••••
••••••
••••••
ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:
AmbientTemperature (TA) ••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vcc)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vcc ......................................... -.5 to +7V
Input voltage applied .......................... -2.5 to Vcc + 1.0V
Off-state output voltage applied .......... -2.5 to Vcc + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

VIL

Input Low Voltage

Vss-O.5

VIH

Input High Voltage

2.0

VI'

Input Clamp Voltage

Vcc= Min.

IIL2

Input or I/O Low Leakage Current

OV ~ VIN ~ Vil (MAX.)

IIH

Input or 1/0 High Leakage Current

VOL
VOH

TYP.'

-

MAX.

UNITS

0.8

V

Vcc+l

V

-1.2

V

-

-100

ILA

3.5V ~ VIN ~ Vcc

-

-

10

ILA

Output Low Voltage

10l = MAX. Yin = Vil or VIH

-

-

0.5

V

Output High Voltage

10H = MAX. Yin = Vil or VIH

2.4

-

10L

Low Level Output Current

10H

High Level Output Current

los'

Output Short Circuit Current

IIN=-32mA

Vcc=5V

VouT=0.5V

TA=25°C

-60

-

V

64

mA

-32

mA

-400

mA

COMMERCIAL
Operating Power

Vil = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) Guaranteed but not 100% tested.
2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
4) Typical values are at Vcc = 5V and TA = 25°C

3-150

1994 Data Book

Specifications GAL20VPB

••••••
......
......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAMETER

tpd

TEST
COND'.

COM

COM

-15

-25

MIN. MAX.

MIN. MAX.

DESCRIPTION

A

Input or 110 to Combinational Output

3

15

3

25

UNITS
ns

tco

A

Clock to Output Delay

2

10

2

15

ns

tcf2

-

Clock to Feedback Delay

-

4.5

-

10

ns

tsu

-

Setup Time, Input or Feedback before Clock i

8

10

-

ns

th

-

Hold Time, Input or Feedback after Clock i

0

-

0

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

55.5

-

40

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

80

-

50

-

MHz

A

Maximum Clock Frequency with
No Feedback

80

-

50

-

MHz

twh

-

Clock Pulse Duration, High

6

-

10

ns

twl

-

Clock Pulse Duration, Low

6

-

10

-

ten

B

Input or I/O to Output Enabled

-

15

-

20

ns

B

OE to Output Enabled

12

-

15

ns

15

-

20

ns

12

15

ns

fmax 3

tdis

C

Input or I/O to Output Disabled

-

C

OE to Output Disabled

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

CAPACITANCE (TA

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM·

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

CliO

I/O Capacitance

15

pF

Vee = 5.0V, VIIO = 2.0V

·Guaranteed but not 100% tested.

3-151

1994 Data Book

~HLaHiceru
......

Specifications GAL20VPB

••••••
••••••

SWITCHING WAVEFORMS

INPUT or
I/O FEEDBACK

ClK

REGISTERED
OUTPUT

Combinatorial Output

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

Registered Output

----r------l-_

~

OE

-------1~td~iS j~ten=t
. _

REGISTERED
OUTPUT

Input or VO to Output Enable/Disable

OE to Output Enable/Disable

:1-

r 1 ===:;]
~I

1-40 ~

SCHMITT TRIGGER INPUTS
One of the enhancements of the GAL20VP8 for bus interface logic
implementation is input hysteresis. The threshold of the positive
going edge is 1.5V, while the threshold of the negative going edge
is 1.3V. This provides a typical hysteresis of 200mV between
positive and negative transitions of the inputs.

HIGH DRIVE OUTPUTS
All eight outputs of the GAL20VP8 are capable of driving 64 mA
loads when driving low and 32 mA loads when driving high. Near
symmetrical high and low output drive capability provides small
skews between high-to-Iow and low-to-high output transitions.

/

/

/'
1/

·60

o

1.0

2.0

3.0

4.0

5.0

Input Voltage (Volts)

PROGRAMMABLE OPEN-DRAIN OUTPUTS
In addition to the standard GAL20V8 type configuration, the
outputs of the GAL20VP8 are individually programmable either
as a standard totem pole output or an open-drain output. The
totempole output drives the specified VCYrl and VOL levels whereas
the open-drain output drives only the specified VOL' The VOH level
on the open-drain ouput depends on the external loading and pullup. This output configuration is controlled by the AC2 fuse. When
AC2 cell is erased (JEDEC "1 ") the output is configured as a
totempole output and when AC2 cell is programmed (JEDEC "0")
the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totempole configuration. The AC2 fuses associated with each of the outputs is
included in all of the logic diagrams.

3-154

1994 Data Book

Specifications GAL20VPB

......
• •••••
••••••

POWER-UP RESET
Vcc

4.0 V

ClK

INTERNAL
REGISTER
OUTPUTQ

aFEEDBACK
AND XXXXXXXXXXXYY
REGISTERED
OUTPUT PIN L..JI.'-lL..JL...><....lL"",-,"-"'-"-.lL...l<..j.J

Circuitry within the GAL20VP8 provides a reset signal to all registers during power-up. All intemal registers will have their Q outputs set low after a specified time (tpr, 11lS MAX). As a result, the
state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of
the output pins. This feature can greatly simplify state machine
design by providing a known state on power-up. The timing diagram for power-up is shown above. Because of the asynchro-

DevIce Pin

RosellOLogic'l'

\

L-

nous nature of system power-up, some conditions must be met
to guarantee a valid power-up reset of the GAL20VP8. First, the
Vcc rise must be monotonic. Second, the clock input must be at
static TTL level as shown in the diagram during power up. The
registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet
the minimum pulse width requirements.

INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN

PIN
Feedback .-------'

Vec

Active Pull-up
Circuit

Active Pull-up
Circuit
roo - - -- _.... - _.. _.... --.

:
Vee:
: ESD
:
:
: Protection
:, Circuit
,,
,,
,
,
1 __ .. __ .... __ .... -

___ I

Vee

. __ L __
,
,,
,,
,,
,,
,,
,,
,

...y....
. Vref:

Programmable
Open-Drain
Data
Output

PIN

PIN

Tri-State
Control·-=+--+--11

Feedback
(To Input Buffer)
Vref=3.1V

Vref=3.1V
Typical Input

Typical Output

3-155

1994 Data Book

Specifications GAL20VPB

• •••••
••••••
••••••
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized TpcI V8 Vee
1.2

'iii

~

......

II

5.00

4.75

5.25

0.8
4.50

5.50

1.3

",

PTL->H

1/

8

J'

(jj

o

5.26

~

~

1.1

.~

1

(jj

I"'"

1.2

E 0.9

~

o

Z

0.8

t-J

1.1

~

1

-55

-25

25

50

75

100

0.8
4.50

l-

S

4.76

, .. ..

""

~

i

1.3

- - - PTH->l

1.2

-PTL->H

1.1

'iii

1

E

~

I"'"

/

/

V

/'

.".

0.8
60

75

100

125

·66

·26

25

SO

75

100

125

Temperature (deg. C)

~.(I.25

8
l-

---RISE~

.(1.3

5.50

6.25

Delta Teo vs # of Outputs
SWitching

.
~

2i -0.4

r--.-

Normalized T8u V8 Temp

~ 0.9

25

"""'- ~ =--

l...,..oo"

6.00

I

Supply Voltage (V)

~

l / io"'"

Delta TpcI V8 # of Outputs
Switching

.s
R .(1.2

...........
..............

Temperature (deg. C)

-0.1

PTL->H

~ 0.9

J

-26

Temperature (deg. C)

0"

PTH->~

- - -

0.7
·55

125

........

I

0.7

0.7

~

1.4

RISE
-FALL

~

{!!.

6.60

Normalized Teo V8 Temp

1

E 0.9

5.00

4.75

Normalized Tpd V8 Temp

I- 1.1

Z 0.8

--- - -

Supply Voltage (V)

- - - PTH->l

~

I-FALL

Supply Voltage (V)

1.3

i.~

~

---

E

~ 0.9

0.8
4.50

1---Rlse~

PTL->H

1

R 1.2

1.2

1.2

11- - - PTH->L

~,.,

iN

Normalized T8u va Vee

Normalized Teo V8 Vee

FALL

S

.(1.75

-1

-0.5

,. '

..-- ~

.(1.5

2i

i--"'" ..-r

,

--

RISE~

- - -

-FALL

-1.25

1

Number of Outputs Switching

Number of Outputs Switching

Delta TpcI vs Output Loading

Delta Teo V8 Output Loading

~---RISEI

..,4

.s

--FALL

~ 2 t--+--t::~f--+--t--\
~

~

0

t-7F-t-+--+-t---1
-2

50

100

150

200

250

300

V
o

l/
50

,

100

I

l.,..ooo"

,."

160

~

200

250

300

Output Loading (pF)

Output loading (pF)

3-156

1994 Data Book

Specifications GAL20VPB

••••••
......
......
TYPICAL AC AND DC CHAR,ACTERISTIC DIAGRAMS
Voh valoh

Vol va lot

Voh valoh
4.5

0.5

........

0.4

~ 0.3

~

~

0.2

-

-

~
~

0.1

o

"

~

i,.;'

0.00

"

40.00

80.00

0.00

80.00

10.00 20.00 30.00 40.00 50.00 60.00

Normalized Icc va Temp

11

1.10

1.00

~

.,,-

./

~

1.1

~

al 1
~E 0.9
o

Z

5.00

5.25

I""'" "'-......

0.8

........

,

g

.....

Vin (V)

1.20
1.10
1.00

100

125

/'

V

25

/'
50

V

75

100

Frequency (MHz)

/

I

40

I
./

60

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

o

Z

1.30

,

~50

....... 100..

4.00

Input Clamp (Vlk)

<,30

J\

75

Temperature (deg. C)

10

I

alN
~

0.90

20

1.5

0.5

11
1'0....

25

2.5

1

.......

5.SO

~>

3.00

Nonnallzed Icc va Freq.

0.7

4.75

-

2.00

1.40

Delta lee va Vin (1 Input)

:!1!
~

-

1.00

loh(mA)

1.2

Supply Voltage (V)

11

0.00

loh(mA)

Nonnallzed Icc va Vee

0.80
4.SO

:,

3.5

20.00

1.20

0.90

£

>
3.75

lo/(mA)

11
~
~~

4.25

~

70
80

".
.."

-2.00

-1.50

-1.00

-0,50

0.00

Vik(V)

3-157

1994 Data Book

~HLatticem
••••••

Notes

••••••
••••••

3-158

1994 Data Book

GAL20XV10
High-Speed E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

~LKLr--~===========---~----,

• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- 10 ns Maximum Propagation Delay
- Fmax 100 MHz
- 7 ns Maximum from Clock Input to Data Output
- TTL Compatible 16 mA Outputs
- UltraMOS" Advanced CMOS Technology

=

vOla

vola

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 90mA Max Icc
- 75mA Typ Icc

•

I/OIQ

• ACTIVE PULL-UPS ON ALL PINS
vOla

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100 ms)
- 20 Year Data Retention

VOIO

VOIO

• TEN OUTPUT LOGIC MACROCELLS
- XOR Gate Capability on all Outputs
- Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
- Registered or Combinatorial with Polarity

VOIO

VOIO

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
- High Speed Counters
- Graphics Processing
- Comparators

VOIO

vO/o

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

liOEo---------------------.4-----'

DESCRIPTION

The GAl20XV1 0 combines a high performance CMOS process
with electrically erasable (F) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counterparts. FCMOS technology offers high speed «100ms) erase
times providing the ability to reprogram, reconfigure or test the
devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20XV1 0 are the PAL" architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacturing. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL® products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

PACKAGE DIAGRAMS

DIP
PLCC
IICLK

I

I

5

7

NC

I

•

111

110/0

:5 u 8
g :z
>

~ ~

28

28

1/0/0
25

23

Top View

21

12

"

CJ

~

1/0/0

1I0IO

110/0
1/0/0

NC

,. ,. ,.,.
:z

1I0IO

1I0IO

GAL20XV10

•

Vee

1I0IO

110/0

1I0IO

1/0/0

1I0IO

1/0/0

Ig ~ ~

110/0
110/0

GND

IIOE

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifIcations and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-159

1994 Data Book

I

~HLattice~

Specifications GAL20XV10

••••••
••••••
••••••

GAL20XV10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

10

6

7

00

15

al

8

10

8

10

00

00

Ordering #

Package

GAL20XV1 OB-1 OLP

24-Pin Plastic DIP

GAL20XV10B-10LJ

28-Laad PLCC

GAL20XV10B-15LP

24-Pin Plastic DIP

GAL20XV10B-15W

28-Lead PLCC

GAL20XV10B-20LP

24-Pin Plastic DIP

GAL20XV10B-20LJ

28-Lead PLCC

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL20XV10B

.,.....N.me

I
Blank = Commercial

Speed (ns)
L = Low Power Power - - - - - - - -....

3-160

L-_ _ _ _ _

Package P = Plastic DIP
J = PLCC

1994 Data Book

......
••••••
......

Specifications GAL20XV10

OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the Output logic
Macrocell. It should be noted that actual implementation is
accomplished by development softwarelhardware and is completely transparent to the user.
The GAL20XV10 has two global architecture configurations that
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/ClK and IIOE pins used
as inputs. The Feedback mode emulates registered PAL d~ices
with the I/ClK pin used as the register clock and the IIOE pin
as an output enable for all registers. The following is a list of
PAL architectures that the GAl20XV10 can emulate. It also
shows the global architecture mode used to emulate the PAL
architecture.
PAL Architectures Emulated by
GAl20XV10
PAl12l10
PAl20l10
PAl20X10
PAl20X8
PAl20X4

GAL20XV10 Global
OLMCMode
Input Mode
Input Mode
Feedback Mode
Feedback Mode
Feedback Mode

Exclusive-OR macrocells. In Feedback mode, the state of the
register is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path
on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array.
REGISTERED CONFIGURATION
The Macrocell is set to Registered configuration when ACO = 1
and AC1 = O. Three of the four product terms are used as sumof-product terms for the D input olthe register. The inverting output buffer is enabled by the fourth product term. The output is
enabled while this product term is true. The XOR bit controls the
polarity of the output. The register is clocked by the low-to-high
transition of the I/ClK. In Feedback mode, the state of the register is available to the AND array via an internal feedback path
on all macrocells. In Input mode, the state of the register is
available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array.
XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configuration when ACO 0 and AC1 1. The four product terms are
segmented into two OR-sums of two product terms each, which
are then combined by an Exclusive-OR gate and fed to an output
buffer. The inverting output buffer is enabled by the 1/eJi:
pin, which is an active low output enable that is common to all
XOR macrocells. In Feedback mode, the state of the 1/0 pin
is available to the AND array via an internal feedback path
on all macrocells. In Input mode, the state of the 1/0 pin is available to the AND array via an input buffer path on macrocells
2 through 9 only, macrocells 1 and 10 have no input into the AND
array.

=

INPUT MODE
The Input mode architecture is defined when the global
architecture bit SYN = 1. In this mode, the I/ClK pin becomes
an input to the AND a[@y and also provides the clock source
for all registers. The IIOE pin becomes an input into the AND
array and provides the output enable control for any macrocell
configured as an Exclusive-OR function. Feedback into the AND
array is provided from macrocells 2 through 9 only. In this mode,
macrocells 1 and 10 have no feedback into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global architecture bit SYN O. In this mode the I/ClK pin becomes
a dedicated clock source for all registers. The IIOE pin is a dedicated output enable control for any macrocell configured as an
Exclusive-OR function. The I/ClK and IIOE pins are not available
to the AND array in this mode. Feedback into the AND array
is provided on all macrocells 1 through 10.

=

FEATURES
Each Output logic Macrocell has four possible logic function
configurations controlled by architecture control bits ACO and
AC1. Four product terms are fed into each macrocell.

=

COMBINATORIAL CONFIGURATION
The Macrocell is set to Combinatorial mode when ACO 1 and
AC1 1. Three of the four product terms are used as sumof-product terms for the combinatorial output. The XOR bit controls the polarity of the output. The inverting output buffer is
enabled by the fourth product term. The output is enabled while
this product term is true. In Feedback mode, the state of the
1/0 pin is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the 1/0 pin
is available to the AND array via an input buffer path on macrocells 2 through 9 only, macrocells 1 and 10 have no input into
the AND array.

=

=

XOR REGISTERED CONFIGURATION
The Macrocell is set to the Exclusive-OR Registered configuration when ACO 0 and AC1 O. The four product terms are
segmented into two OR-sums of two product terms each, which
are then combined by an Exclusive-OR gate and fed into aD-type
register. The register is clocked by the low-to-high transition of
the I/ClK pin. The inverting output buffer is enabled by the
IIOE pin, which is an active low output enable common to all

=

=

3-161

1994 Data Book

II
I

Specifications GAL20XV10

••••••
••••••
••••••
INPUT MODE
OE

!...........................................!
XOR Registered Configuration
- SYN =1.
-ACO=O.
-AC1 =0.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- Pin 13(16) can be OE and/or Input.

·

.

elK:············································

··.--_ ........... _-_ ... ....... .................
_

_

Registered Configuration
- SYN =1.
-ACO = 1.
-AC1 =0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- OE controlled by product term.

elK:···········································
OE

................................... .

XOR Combinatorial Configuration
-SYN =1.
-ACO = O.
-AC1 = 1.
- OLMC 1 and OLMC1 0 do not have the
feedback path.
- Pin 13(16) can be OE and/or Input.
'..

................................... .

. -----------_ ..... --.... -... --... _._--.

~~D [L-~
~'"'

U

'._-_._._._--_._--_._-_._------.. -- .. -.'

3-162

Combinatorial Configuration
- SYN = 1.
-ACO = 1.
-AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- OE controlled by product term.

1994 Data Book

Specifications GAL20XV10

·......
.....
INPUT MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinout
1(2)

-j)

D-

0

4

8

12

16

20

24

28

32

36

OLMC - 1

0

-

120

2(3)

XOR ·1600
ACO - 1610
AC1 ·1620

D---i:6==

--

OLMC - 2

160

XOR ·1601
ACO -1611
AC1 -1621

280

3(4)

D-

OLMC - 3

320

XOR·1602
ACO - 1612
AC1 - 1622

440

4(5)

D-

OLMC - 4

480

XOR - 1603
ACO -1613
AC1 - 1623

600

5(6)

---

D-

OLMC - 5

640

XOR - 1604
ACO ·1614
AC1 ·1624

760

6(7)

D

OLMC - 6

BOO

XOR·1605
ACO - 1615
AC1 - 1625

920

7(9)

D-

OLMC - 7

960

XOR - 1606
ACO - 1616
AC1 ·1626

1080

8( 1 0)

D-------t6

OLMC - 8

1120

XOR 1607
ACO • 1617
ACI -1627

1240

9( 11)

D----

OLMC - 9

1280
-{

1400

10(12)

D

XOR - 1608
ACO·1618
AC1 - 1628

L-6-

D-~

1440
1560

11(13)

~ f-D 23(27)

L

1-------rl4t
f----------~-~-~---

o

4

8

. . ----.
16
20

12

24

28

32

36

OLMC • 1

•

XOR·1600

120

2(3)

0

ACO·1610
AC1 ·1620

"

"0---

OLMC ·2

16.

XOR·1601
ACO ·1611
AC1 ·1621

280

3(4)

D-

OLMC ·3

320

XOR·1602
ACO·1612
AC1 ·1622

44.

4(5)

D-

OLMC ·4

48.

XOR·1603
ACO ·1613
ACt ·1623

6••

5(6)

D-

OLMC ·5

64.

XOR· t604
ACO ·1814
ACt ·1624

76.

6(7)

D-Q-'

800

7(9)

D-

".

::8=

XOR·1606
ACO·1618
AC1 ·1628

0

OLMC • B

1120

XOR·1607
ACO· t617
ACt·1627

1240

9(11 )

D-

OLMC • 9

1280

XOR·1608
ACO·1618
AC1 • 1628

1400

10(12)

D-

OLMC·10

1440
1560

11(13)

XOR· t605
ACO ·1615
AC1 ·1625

OLMC • 7

9..
1080

8(10)

OLMC ·6

p:i-

D-

~

XOR·1609
ACO" 1619
AC1 ·1629

b

23(27)

IrJ.

".....

22(26)

IrJ.

".....

21 (25)

U-

0-

~-o
Irl.

~-D

Irl.
~

20(24)

19(23)

18(21 )

b-o
b-o
b
b
<::J

17(20)

16(19)

15(18)

14(17)

13(16)

40·USER ELECTRONIC SIGNATURE FUSES
SYN -1630

3-165

1994 Data Book

......
••••••
......

Specifications GAL20XV10

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo

Supply voltage Vcc ....................................... -0.5 to+7V

Commercial Devices:

Input voltage applied .......................... -2.5 to Vee +1.0V
Off-state output voltage applied ......... -2.5 to Vee + 1.0V
Storage Temperature ................................ -65 to 150°C
Ambient Temperature with
Power Applied .......................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while programming, follow the programming specifications).

Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

Vss-O.5

-

0.8

V

VIL

Input Low Voltage

VIH

Input High Voltage

2.0

-

Vee+1

V

IlL'

Input or 1/0 Low Leakage Current

OV $ VIN $ VIL (MAX.)

-

-

-100

J.lA

hH

Input or 1/0 High Leakage Current

3.5V $ VIN $ Vee

-

-

10

J.lA

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = VIL or VIH

2.4

-

-

V

-

-

16

mA

-

-

-3.2

mA

-50

-

-150

mA

10L

Low Level Output Current

10H

High Level Output Current

los2

Output Short Circuit Current

Vee=5V

VOUT = 0.5V TA= 25°C

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) The leakage current is due to the internal pull-up on all input and 1/0 pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25°C

3-166

1994 Data Book

......
••••••
.....•

Specifications GAL20XV10

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

PARAMETER

TEST
COND.'

COM

COM

COM
-10

-15

-20

MIN. MAX.

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

tpd

A

Input or I/O to Combinatorial Output

3

10

3

15

3

20

ns

tco

A

Clock to Output Delay

2

7

2

8

2

10

ns

tcf2

-

Clock to Feedback Delay

-

4

-

4

-

4

ns

tsu

-

Setup Time, Input or Feedback before Clocki'

-

8

-

10

-

ns

th

A

6
0

-

0

-

0

-

ns

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

76.9

-

62.5

-

50

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

100

-

83.3

-

71.4

-

MHz

A

Maximum Clock Frequency with
No Feedback

100

-

83.3

-

71.4

-

MHz

twh

-

Clock Pulse Duration, High

4

6

-

7

-

Clock Pulse Duration, Low

4

6

-

7

-

ns

twl

-

B

Input or 1/0 to Output Enabled

3

10

3

15

3

20

ns

B

OE to Output Enabled

2

9

2

10

2

15

ns

3

9

3

15

3

20

ns

2

9

2

10

2

15

ns

fmax 3

ten

tdis

Hold Time, Input or Feedback after Clocki'

C

Input or 1/0 to Output Disabled

C

OE to Output Disabled

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL

PARAMETER

MAXIMUM"

UNITS

TEST CONDITIONS

CI

Input CapaCitance

8

pF

CliO

110 Capacitance

8

pF

=5.0V, VI =2.0V
Vcc =5.0V, VIIO =2.0V
Vcc

"Guaranteed but not 100% tested.

3-167

1994 Data Book

~~~Latticem

Specifications GAL20XV10

••••••
••••••
••••••

SWITCHING WAVEFORMS
INPUT or
1/0 FEEDBACK

INPUT or
1/0 FEEDBACK

CLK
COMBINATORIAL
OUTPUT

REGISTERED
OUTPUT
11 fmax(external fdbk)

Combinatorial Output

Registered Output
INPUT or
1/0 FEEDBACK

OE

OUTPUT

OUTPUT

Input or YO Feedback to Enable/Disable

OE to Output Enable/Disable

CLK

tw I
CLK

REGISTERED
FEEDBACK

Clock Width

fmax with Feedback

INPUT/OUTPUT EQUIVALENT SCHEMATICS

~PIN

PIN~

Feedbacl<~
Vee
Tn-State
Control

~

PIN

t

(VrefTypical '" 3.2V)

Vee

PIN

t----+--K.

Feedback

(To Input Buffer)

Typical Input

Typical Output

3-168

1994 Data Book

......
......

Specifications GAL20XV10

••••••

fmax DESCRIPTIONS
ClK

LOGIC
ARRAY

loll

REGISTER

~14

tsu

elK

..

tco~

fmax with External Feedback 1/(tsu+tco)

!

Note: fmax with external feedback is calculated from measured
tsu and tco.
elK

~.-----tcf-----i.~1

14114f------tpd------.!~1

fmax with Internal Feedback lI(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tef 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tef + tpd.

=

14----- tsu+ th ----.I
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.

SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels

+5V

GNDto 3.0V
3ns 10%-90%
1.SV
1.SV

Output Load

See Figure

3-state levels are measured O.SV from steady-state active
level.

FROM OUTPUT (0/0)
UNDER TEST

TEST POINT

Output Load Conditions (see figure)
Test Condition
A
B
C

Active
Active
Active
Active

High
Low
High
Low

R1

R2

CL

300n

390n
390n
390n
390n
390n

SOpF
SOpF
SOpF
SpF
SpF

00

300n
00

300n

,

C'

'C, INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

3-169

1994 Data Book

......
••••••

Specifications GAL20XV10

••••••

ELECTRONIC SIGNATURE

INPUT BUFFERS

An electronic signature word is provided in every GAL20XV10
device. It contains 40 bits of reprogrammable memory that contains user defined data. Some uses include user 10 codes, revision numbers, pattern identification or inventory control codes.
The signature data is always available to the user independent
of the state of the security cell.
NOTE: The electronic signature bits, if programmed to any value
other then zero(O) will alter the checksum of the device.

SECURITY CELL

GAL20XV10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar
TTL devices.
GAL20XV10 input buffers have active pull-ups within their input
structure. This pull-up will cause any un-terminated input or
I/O to float to a TTL high (logical 1). Lattice recommends that all
unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
Typical Input Pull-up Characteristic
,-----

A security cell is provided in every GAL20XV1 0 device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always
available regardless of the security cell state.

LATCH-UP PROTECTION
GAL20XV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any
possibility of SCR induced latching.

,--------

~ -20~----~--~-.~~~--~-----+-----1

<.>

~-40~

.,/'

.:

DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers. Complete programming of the device takes less than a second. Erasing
of the device is transparent to the user, and is done automatically
as part of the programming cycle.

----_._--

...
.:.

-60 '--------+-----+----1------1--------'
1.0
2.0
3.0
4.0
5.0
Input Voltage (Volts)

POWER-UP RESET
Circuitry within the GAL20XV1 0 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1!IS MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to guarantee a valid power-up reset of the GAL20XV1 O.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.

Vee ____4_.0..JV

ClK

INTERNAL
REGISTER
OUTPUTQ

3-170

1994 Data Book

Specifications GAL20XV10

••••••
......
••••••

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee

Normalized Teo

1.2

~,.,

-g
~

e

1

1.2

1.2

11- - - PTH->L

r--....... ...........

0.8
4.50

4.76

~

II--PTL-.>H

1

0.8
4.SO

Normalized Tpd vs Temp

- - - PTH·>L

-

1-11 --PTL.>HI

Z

0.8
0.7

5.26

.~

1,

.".

- - - PTH->L

~

1.1

~

1iI

e

PTL·>H

~

~ 0.9

0.8
4.SO

6.50

4.75

6.00

~

6.26

..
5.50

Supply Voltage (V)

Supply Voltage (V)

Normalized Teo vs Temp

Normalized Tsu vs Temp

1.3

1.3

.,
eo."
o

6.00

4.76

Supply Voltage (V)

~

-.

~

~ 0.9

6.SO

5.26

5.00

1---RI9E~
I"
FALL

-.. -.-

1.1

~
e

--.. r--.

~ 0.8

"'C 1.2
Q.

Normalized Tsu vs Vee

Vee

YS

..".

i-"""

......

25

~

8

1.2

~---RISE

!;;

1.1

FALL

.~

1

1iI

-

......

eo o.a

Z

0.8

~

-I--

i"'""

75

100

1

·1

_ _ III

." 10-""

0

25

50

75

E

.Q.5

~

---RISE~

."

2

3

4

100

126

26

·25

-55

60

75

100

125

Temperature (deg. C)

~ ·1.5

-_. -~ ~
r'" ...

~

".

."

10-"" ~

RISE.~

- - -FALL

·2

e

5

·1

~

-FALL

·2
7

B

9

10

2

Number of Outputs Switching

3

4

5

e

7

8

9

10

Number of Outputs Switching

Delta Tpd vs Output loading

Dalta Teo vs Output loading
12

12
10

~

0.8

Dalta Teo vs # of Outputs
Switching

-

"".

·1.5

~"

~

0.9

." ~

-

,y.

I
l.,.;'

Temperature (deg. C)

. ...

-0.5

.1'l

~

1.1

g

Delta Tpd vs # of Outputs
Switching

~

~

Z

·25

Temperature (deg. C)

!

--PTL·>H

0.7

..ss

125

---PTH.>L,

1.2

'iii

~

0.7

50

1.3

./

~- -

- RISE,
--FALL

./

J

""

~

~.

V

... ...

...

10

.

.5..
8

8

8

200

250

300

....

~

...

fI" ...

~ 2

150

~

~~

.!l!

·2
100

~

I
--FALL I
- RISE

I-

~
50

~- -

.y

~

50

100

150

200

250

300

Output loading (pF)

Output loading (pF)

3-171

1994 Data Book

Specifications GAL20XV10

••••••
••••••
••••••

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol wlol

Vohvs 100

Voh wloh
4.5

2.5

~'.5

g

t..;.

1

0.5

.-.

0.00

, ~"

~

20.00

40.00

80.00

t..;.

4.25

~

2

"

80.00

100.00

0.00

3.5
0.00

10.00 20.00 30.00 40.00 SO.OO 80.00

, Normalized Icc Vs VCC

1.10

-"

~ 0.90

l/

V

Normalized Icc va Temp

,

,/

11

i

1.1

....

5.00

5.25

j'o..

"i

.......
1"""-0 .......

-55

Supply Voltage (V)

-25

0

25

II

l/

,

\

0.00 O.SO 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

~

.....

75

, -'

§ 1.10

.......
100

125

o

Z

1.00
0.90
0.80
0.70

.,../
o

~

"

/

25

50

75

100

Frequency (MHz)

Input Clamp (Vik)
~

20

II

1.30

~ 1.20

Temperature (deg. C)

Delta Icc vs Vin (1 input)

A

50

4.00

./

,;-

11 :::

1

5.50

~

3.00

Normalized Icc va Freq.

0.8
4.75

2.00

1.70
1.80

~ 0.9

0.80

4.50

1.00

loh(mA)

1.2

1.00

"- -- r--...
~

3.75

loh(mA)

1.20

i

~

i""'-o- .......

IOI(mA)

11

~

...... ........

,/

40

~

60

5

80

100

I

-

./

120
-2.00

-1.50

-1.00

-0.50

0.00

Vik (V)

3-172

1994 Data Book

~~~Lattice~
••••••

GAL22V10
High Performance E2CMOS PLD
Generic Array Logic™

••••••
••••••

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE E2CMOS'" TECHNOLOGY
- 5 ns Maximum Propagation Delay
- Fmax 200 MHz
- 4 ns Maximum from Clock Input to Data Output
- UltraMOS'" Advanced CMOS Technology

UCLK

=

I/O/Q

• ACTIVE PULL-UPS ON ALL PINS

UOIQ

• COMPATIBLE WITH STANDARD 22V10 DEVICES
- Fully FunctionlFuse-MapiParametric Compatible
with Bipolar and UVCMOS 22V10 Devices

IIO/Q

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
- 90mA Typ Icc on Low Power Device
- 45mA Typ Icc on Quarter Power Device

UO/Q

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

UO/Q

UO/Q

UOIQ

• TEN OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
- 100% Functional Testability

UO/Q

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

UOIQ

UO/Q

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION

PACKAGE DIAGRAMS

The GAL22V1 OC, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (P) floating gate technology to provide the highest performance available of any 22V1 0 device on the market. CMOS circuitry allows the GAL22V1 0 to consume much less power when
compared to bipolar 22V1 0 devices. P technology offers high
speed «1 OOms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V1 0 devices.

DIP
PLCC
l<

-'

g
I

I

~

28

26

5

I/O/a
uOla
25

7

23

GAL22V10

NC

I

Vee

q

g
z > g

0

9

tIOIQ

uOla

tIOIQ

IIO/a

UO/Q

IIOla

NC

21

Top View

1I0/a

tIOIQ

IIO/a

tIO/Q

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL" products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

111
12

14
Q

z

"

16
0

z

19
18

1I0/a

tIOIQ

1I0/a

~ ~

1I0/a
GND

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 661-0116 or 1-600-FASTGAL; FAX (503) 661-3037

3-173

1994 Data Book

•

I
I

Specifications GAL22V10

••••••
••••••
••••••
GAL22V10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (n8)

T8U (n8)

Tco (ns)

5

3

4

150

GAL22Vl0C-5W

6

4

4

140

GAL22Vl0C-6W

28-Lead PLCC

715

415

415

140

GAL22Vl0C-7W

28-Lead PLCC

5

415

140

GAL22Vl0C-7LP

24-Pin Plastic DIP

615

5

140

GAL22Vl0B-7LP

24-Pin Plastic DIP

140

GAL22Vl0B-7W

28-Lead PLCC

130

GAL22Vl0B-l0LP

24-Pin Plastic DIP

130

GAL22Vl OB-l OW

28-Lead PLCC

55

GAL22Vl0B-15QP

24-Pin Plastic DIP

55

GAL22Vl0B-15QJ

28-Lead PLCC

130

GAL22Vl0B-15LP

24-Pin Plastic DIP

130

GAL22Vl0B-15W

28-Lead PLCC

55

GAL22Vl0B-25QP

24-Pin Plastic DIP

55

GAL22V10B-25QJ

28-Lead PLCC

00

GAL22V10B-25LP

24-Pin Plastic DIP

00

GAL22Vl0B-25W

28-Lead PLCC

10

15

25

Icc (mA)

7

7

10

8

15

15

Ordering #

Package
28-Lead PLCC

Industrial Grade Specifications
Package

Ordering #

Tpd (n8)

T8U (n8)

Tco (n8)

Icc (mA)

10

7

7

160

GAL22Vl0C-10LPI

24-Pin Plastic DIP

160

GAL22V1 OC-1 OWl

28-Lead PLCC

15

10

8

150

GAL22V10B-15LPI

24-Pin Plastic DIP

150

GAL22V10B-15WI

28-Lead PLCC

150

GAL22V10B-20LPI

24-Pin Plastic DIP

150

GAL22V10B-20WI

28-Lead PLCC

150

GAL22V10B-25LPI

24-Pin Plastic DIP

150

GAL22Vl0B-25WI

28-Lead PLCC

2J

25

14

10

15

15

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL22V10C Devl.. Nome
GAL22V10B

~
Blank = Commercial
I = Industrial

Speed (ns)
L = Low Power Power _ _ _ _ _ _ _ _---l
Q = Quarter Power

3-174

L -_ _ _ _

Package P = Plastic DIP
J = PLCC

1994 Data Book

Specifications GAL22V10

......
••••••
......
OUTPUT LOGIC MACROCELL (OLMC)
The GAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 14 and 23), two have ten product terms
(pins 15 and 22), two have twelve product terms (pins 16 and 21),
two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.

The GAL22V1 0 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.

NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

AR

•
•
•

D

•

4 TO 1

Q

elK

MUX

Q

SP
2 TO 1

MUX

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL22V1 0 has two primary functional modes: registered, and combinatorialI/O. The modes and
the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED

In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OlMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O

In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.

3-175

1994 Data Book

II
I

~HLatticeT"

Specifications GAL22V10

••••••
••••••
••••••

REGISTERED MODE

AR

•
•

D

AR
Q

Q

D

elK
SP

SP

ACTIVE LOW

ACTIVE HIGH

So=O
S,=O

So= 1
S,=O

COMBINATORIAL MODE

ACTIVE HIGH

ACTIVE LOW
So=O

So= 1

S, =1

S, =1

3-176

1994 Data Book

Specifications GAL22V10

......
......
......
GAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP

DIP (PLCC) Package Pinouts
1 (2)

,

.

,

'00'

"

"

'"

"

"

"

"""

"

.,
ASYNCHRONOUS RESET
(TO ALL REGISTERS)

l'B-

"'''

2(3)

23

1
It-bm
~

''''

t-

''''

~
so

58"

,,<3
"

~

""

L
~

2112

4 (5)

p------

~
so
5814

"

5815

~
so

''''

"

5617

,,'"
5 (6)

p------

~
so

""
"

5819

"'"
6 (7)

I-

"'"
4312

t-

.,,'

-

1

20 (24)

1

19 (23)

1

18 (21)

1

17 (20)

J

16(19)

U
U
U

U

~
so

"'"
"
""

U

~

e--OLMC 16
so
s,

""
''''

U

ru
iP-CfrtJ
~

It-

5324

9 (11)

""

11 (13)

21 (25)

~

"'"

10(12)

1

~

29'"

8 (10)

22 (26)

~

"58

7 (9)

23 (27)

5811

"'''

3 (4)

-fo'MC1 1

~
"'"

0396

~,
~NCHRONOUS

"'"
""

PRESET
(TO ALL REGISTERS)

15 (18)

14 (17)

13 (16)

.'.'.'.-.'.'.'.'
,, ,,
5826,5829 ...

Electronic Signature

... 5890,5891

"

3-177

1994 Data Book

•

Specifications GAL22V1 DC

••••••
••••••
••••••

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(1)

Commercial Devices:
Ambient Temperature (TA) •••••••••••••••••••••••••••• 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Industrial Devices:
AmbientTemperature (TA) ••••••••••••••••••••••••••• -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

MIN.

CONDITION

TYP."

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

ilL'

Input or I/O Low Leakage Current

-

-

-100

IlA

OV:5 VIN :5 VIL (MAX.)

Input or I/O High Leakage Current

3.SV :5 VIN :5 Vec

-

-

10

!lA

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

-

O.S

V

VOH

Output High Voltage

10H = MAX. Yin = VIL or VIH

2.4

-

-

V

IIH

10L

Low Level Output Current

-

-

16

mA

10H

High Level Output Current

-

-

-3.2

mA

los2

Output Short Circuit Current

-30

-

-130

mA

Vee=SV

VOUT = O.SV TA = 2Soc

COMMERCIAL

I

Icc

I Operating Power Supply Current

VIL = O.SV

VIH = 3.0V

ftoggle = 1SMHz Outputs Open

If--L_-S_-+_ _-+1_90--j1_1_S_0_+-lm_A--j1

I

L-6!-7

I

90

I

140

I

mA

I

INDUSTRIAL
Operating Power Supply Current

VIL = O.SV

VIH = 3.0V

ftoggle = 1SMHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = SV and TA = 2S °C

3-178

1994 Data Book

Specifications GAL22V10C

......
••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

COM

COM

TEST
PARAM CONO.'

DESCRIPTION

-5 (PLCC)

COM

-6 (PLO#» -7 (PLCC)

MIN. MAX. MIN.

I~.

~~

A

Input or VO to Combinatorial Output

1

tco

A

Clock to Output Delay

1

4

-

3

- It

-

tsu

-

Clock to Feedback Delay
Setup Time, Input or Fdbk before Clk'!'

3

4

b-

th

-

Hold Time, Input or Fdbk after Clk'!'

0

0

~t-

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

142.8

-

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tef)

166

-

A

Maximum Clock Frequency with
No Feedback

200

-

tef'

fmax 3

-

Clock Pulse Duration, High

2.5

Clock Pulse Duration, Low

2.5

-

ten

B

Input or I/O to Output Enabled

1

6

tdis

C

Input or I/O to Output Disabled

1

6

tar

A

Input or I/O to Asynch. Reset of Reg.

1

5.5

tarw

-

Asynch. Reset Pulse Duration

5.5

tarr
tspr

-10

1

7.5

1

7.5

1

1

4.5

1

4.5

3

-

3

4.5

-

5

0

0

111

-

105

-

142.~ ~-

133

-

125

16~ ~-

166

-

3

3

Ii

1

i

~~

125

UNITS

10

ns

1

7

ns

-

2.5

ns

7

ns

71.4

-

MHz

-

105

-

MHz

142.8

-

105

-

MHz

-

3.5

-

4
4

-

ns

3.5

1

7.5

1

7.5

1

10

ns

0

ns

~Ir>

twl

twh

1

INO

MIN. MAX. MIN. MAX. MIN. MAX

tpd

5

COM
-7 (PDIP)

Asynch. Reset to Clk'!' Recovery Time

4

-

Synch. Preset to Clk'!' Recovery Time

4

-

t

#t
i3 :i!:: -

W6
Y1 6

~
Q

~

5

ns

1

7.5

1

7.5

1

9

ns

7.5

1

9

1

9

1

13

ns

-

7

-

7

8

-

5

5

-

5

-

ns

5

-

8
10

ns
ns

1) Refer to Switching Te8t Condition8 section.
2) Calculated from fmax with internal feedback. Refer to fmax De8cription section.
3) Refer to fmax De8cription section. Characterized initially and after any design or process changes that may affect these
parameters.

CAPACITANCE (TA = 25 C, f = 1.0 MHz)

.

SYMBOL

PARAMETER

MAXIMUM·

UNITS

TEST CONDITIONS

C1

Input Capacitance

8

pF

Coo

I/O Capacitance

8

pF

=5.0V, V, =2.0V
Vee =5.0V, VI/o =2.0V
Vcc

Guaranteed but not 100% tested .

3-179

1994 Data Book

•

~~~Latticeru
......

Specifications GAL22V10B

••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:
Ambient Temperature (TA) ............................ 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Industrial Devices:
Ambient Temperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

MAX.

UNITS

-

0.8

V

TYP."

VIL

Input Low Voltage

VIH

Input High Voltage

2.0

-

Vcc+1

V

IlL'

Input or I/O Low Leakage Current

OV ::; VIN ::; VIL (MAX.)

-

-

-100

itA

IIH

Input or I/O High Leakage Current

3.5V ::; VIN ::; Vee

-

-

10

itA

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = VIL or VIH

Vss-O.5

2.4

-

-

10L

Low Level Output Current

-

-

16

mA

10H

High Level Output Current

-

-

-3.2

mA

los2

Output Short Circuit Current

-30

-

-130

mA

Vec=5V

VOUT = 0.5V T A = 25°C

V

COMMERCIAL
Icc

-

90

140

mA

90

130

mA

75

90

mA

0-15/-25

-

45

55

mA

L-15/-20/-25

-

90

150

mA

L-7

Operating Power

VIL= 0.5V

Supply Current

ftogglo = 15MHz Outputs Open

VIH =3.0V

L-10/-15
L-25

INDUSTRIAL
Icc

Operating Power

VIL=0.5V

Supply Current

ftogglo = 15MHz Outputs Open

VIH= 3.0V

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

3-180

1994 Data Book

Specifications GAL22V10S

••••••
••••••

......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAM.

TEST

COND.'

COM

COM

COM/IND

IND

COM liND

-7

-10

-15

-20

-25

DESCRIPTION

MIN. MAX MIN. MAX MIN. MAX MIN. MAX MIN. MAX.

UNITS

tpd

A

Input or I/O to Comb. Output

3

7.5

3

10

3

15

3

20

3

25

ns

tco

A

Clock to Output Delay

2

5

2

7

2

8

2

10

2

15

ns

tcf2

-

Clock to Feedback Delay

-

2.5

-

2.5

-

8

-

13

ns

tsu,

-

Setup Time, Input or Fdbk before Clk'!' 6.5

-

7

-

10

-

14

-

15

-

ns

tsu 2

-

Setup Time, SP before Clock'!'

10

-

10

-

10

-

14

-

15

ns

th

-

Hold Time, Input or Fdbk after Clk'!'

0

-

0

-

0

-

0

-

0

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

87

-

71.4

-

55.5

-

41.6

-

33.3

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

111

-

105

-

80

-

45.4

-

35.7

-

MHz

A

Maximum Clock Frequency with
No Feedback

111

-

105

-

83.3

-

50

-

38.5

-

MHz

twh

-

Clock Pulse Duration, High

4

-

4

-

6

-

10

-

13

-

ns

fmax 3

2.5

-

ns

twl

-

Clock Pulse Duration, Low

4

-

4

-

6

-

10

-

13

-

ns

ten

B

Input or I/O to Output Enabled

3

8

3

10

3

15

3

20

3

25

ns

tdis

C

Input or I/O to Output Disabled

3

8

3

9

3

15

3

20

3

25

ns

tar

A

Input or I/O to Asynch. Reset of Reg.

3

13

3

13

3

20

3

25

3

25

ns
ns

tarw

-

Asynch. Reset Pulse Duration

8

-

8

-

15

-

20

-

25

-

tarr

-

Asynch. Reset to Clk'!' Recovery Time

8

-

8

-

10

-

20

-

25

-

ns

tspr

-

Synch. Preset to Clk'!' Recovery Time

10

-

10

-

10

-

14

-

15

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (TA

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

C,

Input Capacitance

8

pF

CliO

I/O Capacitance

8

pF

TEST CONDITIONS
Vee =5.0V, V,

=2.0V
Vee =5.0V, VI/C =2.0V

"Guaranteed but not 100% tested.

3-181

1994 Data Book

~~~Latticem

Specifications GAL22V10

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or
I/O FEEDBACK

\ \\ \ \ \\ \ \ r!AUD INPUT

COMBINATORIAL
OUTPUT

t"TT"'f\\\\"TTT'"\\\I"'"TTT\
\\

INPUT or
I/O FEEDBACK

'~tpd~,

CLK

,\""I"TT'1\\\Ur--,---- _

REGISTERED
OUTPUT

Combinatorial Output

Registered Output
INPUT or
I/O FEEDBACK

OUTPUT
CLK

Input or VO to Output EnableJDisable
REGISTERED
FEEDBACK

frnax with Feedback

C~

~"T~~

~IOIIII-t---l/fmax~
(W/ofdbk)

Clock Width

INPUT or
110 FEEDBACK
DRIVING AR

INPUT or
VO FEEDBACK
DRIVINGSP
CLK

CLK

REGISTERED
OUTPUT

REGISTERED
OUTPUT

Synchronous Preset

Asynchronous Reset

3-182

1994 Data Book

Specifications GAL22V10

......
••••••

......
fmax DESCRIPTIONS

eLK

I..

.1..

Isu -

r. .---

Ico----.

fmax with External Feedback 1/(tsu+tco)

tct - -..... I
IL.M.lL..>L~~->J.--,,--,,I\,--,---,,R=ese=tto:..;:cLo=gic::....:·0:.L·
1_ _

up, some conditions must be met to guarantee a valid power-up
reset of the device. First, the Vee rise must be monotonic. Second, the clock input must be at static TIL level as shown in the
diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking
the device until all input and feedback path setup times have been
met. The clock must also meet the minimum pulse width requirements.

Circuitry within the GAL22V1 0 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1~ MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly
simplify state machine design by providing a known state on
power-up. Because of the asynchronous nature of system power-

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Feedback oil

Vee
(VrefTypical = 3.2V)

Active Pull-up

Active PUll-up
Circuit

Circuit

1 _._.

Vcc
c_
T n - S t a t e i : Vref i:

(Vref Typical = 3.2V)

Control

~t~l+---Kj

PIN

PIN

Feedback
(To Input Buffer)

Typical Input

Typical Output

3-185

1994 Data Book

~HLatticem

Specifications GAL22V10

••••••
••••••
••••••

GAL22V10C-6/-?: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd va Vee
1.2

~1.1

"5l
.~

1U

E

1.2

1- --

I---RISE~
I-FALl

PTH->L

I-PTL->H

1

~ 0.•

~ ~ --....
r-4.15

5.25

5.00

o

0.8 .j....--+---I--~---I
5.50
4.15
5.00
5.25
4.50

Supply Voltage (V)

Normalized Teo va Temp

Nonnallzed Tau va Temp
1.4

1.3

r-

~

~

8
il-

10'

~-

1.2

- - RISE
-FALL

1.1

.~

",. ~

1

iii

8

-~

0 .•

.....

iil

.- ."""

---

........ ~

1.3

iii

1

~

0 .•

Z

0

25

50

75

100

·25

0

25

SO

75

Delta Tpd va • of Outputa
Switching

- ...,
,

-0.25

fII

..s

-0.5

~

·1

C

-1.25

-

...

~--

~ .a.75

".

~

---RISE~
--FALL

!

.a.25

~

.a.5

100

125

-55

-25

~ .a.75
·1

3

..

5

8

7

8

0

25

SO

75

100

125

Temperature (deg. C)

9

..

10

...... .,...
1

2

1...,-

tI"" ---R1SE~

.,... ,

3

,I

-'" ...

...

~

·1.5
2

.J'

Delta Teo va • of Outputs
Switching

tI""

~

1

~

0.8

.- "..

Temperature (deg. C)

Temperature (deg. C)

_

~

~

0.7

·55

125

PTH->L

-PTL->H

]1.1

0.7
-25

- - -

I- 1.2

Z 0.8

0.7
-55

-l:---+--41

~ 1+---+-=~~=--4-~

5.50

5.25

Nonnallzed Tpd va Temp

1

Z 0.8

5.00

Supply Voltage (V)

1U

EO.•

4.75

4.50

SUpply Voltage (V)

-PTL->H

r-T--,;::==:::::r==:::::;,

1.1

E

5.50

- - - PTH->L

1.2

~ 0.• +---+--.J.---4-~

1.3

~

~

0.8

0.8
4.50

'B. 1.2
I- 1.1

Nonnallzed Tau va Vee

Normalized Teo va Vee

..

-FALL
5

8

7

8

9

10

Number of Outputs Switching

Number of Outputs Switching

Delta Tpd va Output loading

Delta Teo va Output loading
12

~---R1SEI
-FALL

l/

I

I.t'

V

V
o

8

8 •

c!l

100

150

200

250

V
o

300

~

I...t'

2

-2

~

I.ot""

~

V
50

~---R1SEI
--FALL I

I-

~
·2

10

.E.

V
50

100

150

200

250

300

Output Loading (pF)

OUtput Loading (pF)

3-186

1994 Data Book

~~~Lattice'"

Specifications GAL22V10

••••••
••••••
••••••

GAL22V10C-6/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

2.5

~

15

>

,

1.5

,

1
0.5

J'

0.00

20.00

3.76

'-

r--..... ......
........

i-o"
~

40.00

80.00

BO.OO

100.00

0,00

.,----,---r---,.--"""2/11

"'" ~ .........

E

~ 0.90 ~--I'--1I--~-~

0.00

SO.OO 80.00

1.00

-55

-25

0

/

<" 30
g
~ 40

-

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.S0 4.00

4.00

Normalized Icc v. Freq.

25

50

75

1l

1.20

~

1.10

~

1.00

Z

'"

100

125

0.90

/

./

~
o

~

l/

25

50

75

100

Frequency (MHz)

~

10

20

I

3.00

Input Clamp (Vlk)

Delta Icc va Vln (1 Input)

...... ......

"'- .......

Temperature (deg. C)

It

2.00

r-......

10h(mA)

O.B

Supply Voltage (V)

Vin(V)

i"-o...

~

~ 1.00 ~--r--3~-~-~

0.90 ~--+--I---+----l
5.25
5.50
4.50
4.75
5.00

~

1.30

i

1/

...........

3.25

Normalized Icc va Temp
1.2

1.10 +---+---t--~:"'---1

If ......

~

loh(mA)

Normalized Icc va Vcc

1l

.........

10.00 20.00 30.00 40.00

101 (mA)

1.20

Vohv.loh

Vohvsloh

Vol v.lol

so
BO

1/

/'
/
1/

70
-2.50

-2.00

-1.SO

-1.00

.a,50

0.00

Vik(V)

3-187

1994 Data Book

~~~LatticeTM

Specifications GAL22V10

......
••••••
••••••

GAL22V10B-7/-10/-1S/-2SL: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized TpcI VB Vr:c
1.2

~1.1

i
o

Z

1.2

.........

II--PTL->H

...

.

1

.....

r- ......

0.8
4.50

0.8
4.75

5.50

5.25

5.00

4.50

4.75

Supply Voltage (V)

5.25

5.00

5.50

- - - PTH->L

1

.

o

~~

o

.. "~

-

t>

~. -

1.2

{!.

~

~

0.9
0.8

o

,

-

- RSE

--FALL

1

Z

I.,..000o ~

1.3

- - - PTH->L

{!!.

1.2

11

--PTL->H

1. 1

::J

... ~

ii

~

~

~

~

;!!

0.9

Z

0.8

~

~

~

~ -1.5

,.

~

~

..

k 1-"

i'~

~

RISE.~

- - -FALL

~

-1

~

2

3

4

5

8

7

8

o

'"

o

o

..

~

.... ~ ~

".

~

- - - RISE
FALL

9

10

1

2

3

4

5

8

7

8

9

10

Number of Outputs Switching

Delta Teo V8 Output Loading
12

12

./

~---RISEI
--FALL

8

l-

S
~ 2
-2

~

~~

~ -1.5

Delta Tpd VB Output Loading

X

~
~

Temperatura (deg. C)

-0.5

Number of Outputs Switching

.s

,,-

.

-2
1

10

~

il}

E

-2

"ii"

5.50

Delta Teo V8 # of Outputs
Switching

Delta Tpd V8 # of Outputs
SWitching

-1

,..,.

Temperatura (deg. C)

E~'S

5.25

0.7
~

il}

Temperatura (deg. C)

~

1

~

0.7

0.7

-

... ...

1.4

"C 1.1

0.8

il}

... ...

Normalized TBu VB Temp

Normalized Teo VB Temp

1.3

iEO.•

PTL->H

5.00

I

PT~>~

•• -

Supply Voltage (V)

1.3

-PTL->H

4.75

Supply Voltage (V)

Normalized Tpd VB Temp

I- 1.1

1

.
~ -:...

~ 0.9

4.50

"C 1.2
C.

1.1

j
~

.......

0.9

0.8

Z

~

I-FAll

... ...

..

1.2

1- -- RISE~

II---PTH->L

..........
~

Normalized TBU VB Vr:c

Normalized Teo VB Vr:c

V

~

~

I

""'..."
/:: ...

"

. ..

10

"ii"

.s
8

100

150

200

~

8

~

~

250

~

f'

I-

2

-2
50

~---RISEI
-FALL I

./

"

..

~
50

300

"r..

.....

100

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-188

1994 Data Book

Specifications GAL22V10

••••••

GAL22V108-7/-10/-1S/-2SL: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh valoh

Voh valoh

Vol va 101

4.5
2.5

~

"6

1 .5

>

1

,

0.5

io""
0.00

'"

20.00

1I
...
;'
,.

/

...........

.....

4.25

.........

40.00

60.00

80.00

0.00

100.00

10.00 2000

i""""-o

3.75

30.00 40.00

SO.OO 60.00

0.00

~ 1.10

",.

~ 0.90

.",.,

./

~

1.1

1

".

~

........

~

.......

~ 0.9

5.00

5.25

5.50

·55

·25

Supply Voltage (V)

~

0

;;(

.s

1\
I

~

""" r-.... ......

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

50

4.00

.......

75

.",.,

./

",.

.... ,,/

~090

.......

100

125

0.80
25

50

75

100

Frequency (MHz)

Input Clamp (Vlk)

,,

10
20

J \

25

1

Temperature (deg. C)

Delta Icc va Vln (1 Input)

~

3.00

2.00

1.10

'00

0.8
4.75

-

Normalized Icc va Freq.

1l

1

0.80
4.50

1.00

1.20

1.2

1.00

r-- r-loh(mA)

Normalized Icc va Temp

Normalized Icc va Vcc

~

0

loh(mA)

1.20

.~

s::.

>
3.5

lol(mA)

a:

\.. ......

~

r--..

30
40

,

50
60
70
80
90
100

,

-2.00

I

I
I

-1.50

-1.00

-0.50

0.00

Vik(V)

3-189

1994 Data Book

~HLattice~
......

Specifications GAL22V10

••••••
••••••

GAL22V108-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized TpcI vs Vee

-4.50

-

to--

4.75

]

1

r--

1.2

1.2

1.1~
iii

~

1.1

]

1

iii

E

E 0.9

o

0.90

Z

Z

0.8
5.50

5.25

5.00

--- -

0.8
4.50

4.75

Normalized TpcI vs Temp

./

o

0.8

~

8

1.2

i

1.1

'iii

" . io-""'"

E

0.8
4.50

E 0.9

~

o

Z

O.B

0.7

~

iii

"i""

g

~

~

Temperature (deg. C)

~

:[ .o.s

""

~

" . io-""

·1

".

",..,,-

I-""

:!l!

~ ·1.5
·2

1

2

3

4

5

8

7

8

9

10

1

2

3

4

5

8

7

B

9

10

Number of Outputs SWitching

Number of Outputs SWitching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

l'

12

~

---RISE
--FALL:

R•

I-

:!l!

,

~

'f'

10'-

12

.. ..

010

~

'"

50

100

~

.!!!

~
200

250

300

./

,- ..

.J

4
2

./

.... . .
.JIll'

--FALL I

8

·2
160

~---RISEI

.s

~

2
·2

~

Delta Tco vs # of Outputs
Switching

.,. .., ~ "
".

'"

~

Temperature (deg. C)

·1

~

./

1

0.8

0.7

~ -0.75

E

./

Z 0.•

Delta Tpd vs # of Outputs
Switching

10

~

1.2

~

Temperature (deg. C)

.0.5

1.3

]1.1

1/

i\l

: [ ..0.25

5.50

5.25

Normalized Tsu vs Temp

..,
~

5.00

1.4

0.7

~
:!l!

4.75

r--

Supply Voltage (V)

~

1

-

~

~ 0.9

5.SO

5.25

l-

./

1

1

iii

Normalized Teo vs Temp

~

I- 1.1

Z

]

1.3

R 1.2

E 0.9

5.00

--..

1.1

Supply Voltage (V)

1.3

]

~

~

Supply Voltage (V)

iii

Normalized Tsu va Vee

Normalized Teo vs Vee
1.2

",

I:?'"
o

50

100

150

200

260

300

Output Loading (pF)

Output Loading (pF)

3-190

1994 Data Book

Specifications GAL22V10

••••••
••••••
••••••

GAL22V108-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Voh valoh

Vol va 101

Voh valoh

0.8

/

~ 06

~

0.2

:E.c

./

0.4

l/

~ 2

./

0.00

"- .......

3

3.75

1.10

0.90
0.80

---

4.50

~

~

g

1.2

i1.1

~

1

E
0.9
o
Z

5.00

-

5.25

- r- r-

0.8

25

,

10
20

-

0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70

Vin (V)

75

100

125

~

1.60

~ 1.40

./

'o" 1.20
E

/'

./'

1.00

~
o

25

so

75

100

Frequency (MHz)

Input Clamp (Vlk)

Delta Icc va Vln (1 Input)

I' ......
r-

4.00

/

1.80

0.80
-25

Temperature (deg. C)

A

i

Z

-55

5.50

3.00

Normalized Icc va Freq.

g

r- 1-0...

Supply Voltage (V)

./

2.00

2.00

0.7

4.75

1.00

loh(mA)

Normalized Icc va Temp
1.3

~

3.25

..... .....
0.00

Normalized Icc va Vcc

1.00

r-....

--- -.......

loh(mA)

1.20

~
~~

.....

3.5

>

40.00

20.00

lol(mA)

.§

~

15

~

~.......

~

30

~

40

~

SO

f
f

'"

:= 60
70

80
90

-2.00

1...0'"

,f

f

f
-1.50

-1.00

-O.SO

0.00

Vik (V)

3-191

1994 Data Book

H~Lattice~
......
......
......

Notes

3-192

1994 Data Book

ispGAL22V1 0
In-System Programmable E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••
FEATURES

FUNCTIONAL BLOCK DIAGRAM

• IN-SYSTEM PROGRAMMABLE (S-V ONLY)
- 4-Wire Serial Programming Interface
- Minimum 10,000 Program/Erase Cycles

~lK

1/0/0

• HIGH PERFORMANCE E2CMOS-TECHNOLOGY
- 7.5 ns Maximum Propagation Delay
- Fmax = 111 MHz
- 5 ns Maximum from Clock Input to Data Output
- UltraMOS" Advanced CMOS Technology

1/0/0

110/0

• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
- Fully Function/Fuse-MaplPararnetric Compatible
with Bipolar and CMOS 22V10 Devices

110/0

1/0/0

• P CELL TECHNOLOGY
- In-System Programmable Logic
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

11010

110/0

• TEN OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs

110/0

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Software-Driven Hardware Configuration

I/O/Q

1/0/0

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
SIlO

SIll
MODE
SCLK

DESCRIPTION
The ispGAL22V1 0, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (P) floating gate technology to provide the industry's
first in-system programmable 22V1 0 device. P technology offers high speed «1 OOrns) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

PACKAGE DIAGRAMS

PLCC

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAl22V1 0 is fully functionlfuse map/parametric
compatible with standard bipolar and CMOS 22V1 0 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V1 0 PLCC package with No-Connect pins being
used for ISP interface signals.

28

I

5

I

7

I

9

I

1112

26

25

I/OJQ

23

1/010

0010

ispGAL22V10

MODE

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all products. LATTICE also guarantees 10,000
erase/rewrite cycles and data retention in excess of 20 years.

SOO

Top View
21

I/OJQ

18 19

I/OJQ

I/OJQ

'-'

14
........

'-'

16
........

L...I

..............

~ ~ - ~ ~

Copyright C 1994 Lattice Semioonductor Corp. AU brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LAITICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-193

1994 Data Book

I

II
I

~~~Lattice~
••••••

Specifications ispGAL22V10

••••••
••••••

ispGAL22V10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

7.5

6.5

5

140

ispGAL22V10B-7W

Ordering #

Package
28-Lead PLCC

10

7

7

140

ispGAL22V1OB-1OW

28-Lead PLCC

15

10

8

140

ispGAL22V10B-15W

28-Lead PLCC

PART NUMBER DESCRIPTION

xxxxxxxx - xx x

ispGAL22V10B

om.. Name

X X

~

L...-_ _ _

Speed (n5)
L = Low Power Power - - - - - - - - - - '

3-194

Grade

Blank =Commercial

Package J = PLCC

1994 Data Book

~~~Lattice~
••••••
......
......

Specifications isp GAL22V1 0

OUTPUT LOGIC MACROCELL (OLMC)
The ispGAL22V1 0 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (OLMC 1 and 10), two have ten product terms
(OLMC 2 and 9), two have twelve product terms (OLMC 3 and
8), two have fourteen product terms (OLMC 4 and 7), and two
OLMCs have sixteen product terms (OLMC 5 and 6). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.

The ispGAL22V10 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.

NOTE: The AR and SP product terms will force the output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

a

AR

•
•
•

D
4 TO 1

Q

MUX

elK
SP
2 TO 1

MUX

ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the ispGAL22V1 0 has two primary functional modes: registered, and combinatorial 110. The modes and
the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED

In registered mode the output pin associated with an individual
OLMC is driven by the a output of that OLMC's D-type flip-flop.
Logic polarity of the output Signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Outputtri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's 10 output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the 10 output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
1/0, as can the combinatorial pins.
COMBINATORIAL 110

In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic 1/0). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.

3-195

1994 Data Book

.I

~Hlatticem
......
......
......

Specifications isp GAL22V1 0

REGISTERED MODE

AR

•
•
•
•

AR
Q

0

elK

Q

0

Q

Q

SP

SP

ACTIVE HIGH

ACTIVE LOW
So = 1
S,=O

So=O
S,=O

COMBINATORIAL MODE

ACTIVE LOW

ACTIVE HIGH

So=O

So=1

S, =1

S,

3-196

=1

1994 Data Book

Specifications isp GAL22V1 0

......
••••••
••••••

ispGAL22V10 LOGIC DIAGRAM I JEDEC FUSE MAP
PLCC Package Pinouts
2
0

4

,

12

"

20

24

28

32

"

"

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

0000
0014

~ ~LMC 2'[ 1

~

03"

5808
S1
5809

0440

§=l 10

[OLMc22l

4

~

rm:MC21
so

""

'--,---OLMC 20
SO
581.
S1
5815

14
2112

5

25

J

24

J

23

1

21

J

20

J

19

~

'--2156

r--

OLMC 19

so

16

~

581.
S1
5817

2860

6

'---

'''''

bLMc1a

p-!S-

50
5818
51
5819

~

3808

7

'---

""
14

'oLMC17
so

5820
51
5821

"'"

U

'--4312

10

J

~

5812
S1
5813

""

9

26

5811

3

""

J

tt!D

B=l

08B0

27

Ii 12
c8=J

""

~-

OLMC 16

so

5822
51
5823

'---

4884

~~

5324

11
5368

U

m
t!LJ
5824
51
5825

J

~ml

~.

5720

18

17

51
5827

12

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

5764

13

3-197

16

1994 Data Book

~~~Lattice'M
......
......
......

Specifications isp GAL22V1 0

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:

Supply voltage Vee ........................................ -0.5 to +7V

Ambient Temperature (TA) ............................ 0 to + 75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Input voltage applied ........................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

MIN.

CONDITION

TYP.3

MAX.

UNITS

-

0.8

V

VIL

Input Low Voltage

VIH

Input High Voltage

2.0

-

Vcc+1

V

IlL'

Input or 1/0 Low Leakage Current

OV ,,; VIN ,,; VIL (MAX.)

-

-

-100

fLA

IIH

Input or I/O High Leakage Current

3.5V ,,; VIN ,,; Vec

-

-

10

fLA

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = VIL or VIH

2.4

-

-

V

-

-

16

mA

-

-

-3.2

mA

-30

-

-130

mA

10L

Vss-O.5

Low Level Output Current

10H

High Level Output Current

los2

Output Short Circuit Current

Vee=5V

VouT=0.5V

T A =25°C

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

flogglo = 15MHz Outputs Open

VIH = 3.0V

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (T A

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

C vo

I/O Capacitance

8

pF

Vee = 5.0V, V vo = 2.0V

'Guaranteed but not 100% tested.

3-198

1994 Data Book

Specifications isp GAL22V1 0

......
......
......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions
COM

COM
PARAMETER

tpd

TEST
COND.'

-7

-10

-15

MIN. MAX.

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

A

Input or 1/0 to Combinatorial Output

-

7.5

-

10

-

7
2.5

tco

A

Clock to Output Delay

-

5

-

tcf2

-

Clock to Feedback Delay

-

2.5

-

tsu

-

Setup Time, Input or Feedback before Clock1'

6.5

-

7

10

10

tsu 2

-

Setup Time, SP before Clock1'

th

-

Hold Time, Input or Feedback after Clock1'

0

-

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

87

-

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

111

A

Maximum Clock Frequency with
No Feedback

twh

-

twl

-

fmax 3

COM

15

ns

-

8

ns

-

2.5

ns

10

-

ns

10

0

-

0

-

ns

71.4

-

55.5

-

MHz

-

105

-

80

-

MHz

111

-

105

-

83.3

-

MHz

Clock Pulse Duration, High

4

-

4

6

4

-

4

-

ns

Clock Pulse Duration, Low

-

6

ns

ns

ten

B

Input or 1/0 to Output Enabled

-

15

ns

Input or 1/0 to Output Disabled

8

-

10

C

-

8

tdis

10

-

15

ns

tar

A

Input or 1/0 to Asynchronous Reset of Register

-

13

-

13

-

20

ns

tarw

-

Asynchronous Reset Pulse Duration

8

-

8

Asynchronous Reset to Clock Recovery Time

8

-

8

10

-

ns

-

-

15

tarr
tspr

-

Synchronous Preset to Clock Recovery Time

10

-

10

-

10

-

ns

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

3-199

1994 Data Book

II
I

~HLatticem

Specifications isp GAL22V1 0

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or
VOFEEDBACK

COMBINATORIAL
OUTPUT

\\\\\\\\\t;~

INPUT or
VOFEEDBACK

\\\\\\\\\\\\\\\!'----~--

ClK
REGISTERED
OUTPUT

Combinatorial Output

Registered Output
INPUT or
VOFEEDBACK

OUTPUT

ClK

Input or 110 to Output EnableIDlsable

ox

REGISTERED
FEEDBACK

rt'"T~1r-

t_cf_~__t_su_______

_______

fmax with Feedback

~1II-I---lIfmaX~
(wfofdbk)

Clock Width

INPUT or
I/O FEEDBACK
DRIVINGSP

~--tau

REGISTERED

DRIVINGAR

..-tarw-.

ClK

kO£

CLK

OUTPUT

INPUT or
I/O FEEDBACK

REGISTERED

\\\\\\\\\\\\\\

OUTPUT

Asynchronous Reaet

Synchronous Preset

3-200

1994 Data Book

~~~Lattice~
••••••
......

Specifications isp GAL22V1 0

fmax DESCRIPTIONS
ClK

elK

lOGIC
ARRAY

IOII~I----

1--" REGISTER

tsu ----j~~IIOIII~I---- tco~

:------------------------------------------------:

r
JIIII·~I------tpd-----*I~1

~---tcf------.!~I

fmax with External Feedback 1/{tau+tco)
Note: fmax with extemal feedback is calculated from measured tsu and tco.

fmax with Internal Feedback 1/{tsu+tcf)

ClK

~.-

...............-... -........... ··-··········i

Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf 1lfmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.

=

LOGIC
ARRAY

REGISTER

~·t~;·t~·==+i······-··-··········:
fmax with No Feedback
Note: fmax with no feedback may be less
than 1ltwh + twI. This is to allow for a clock
duty cycle of other than 50%.

SWITCHING TEST CONDITIONS
Input Pulse Levels

+5V

GNDto 3.0V

Input Rise and Fall Times

3ns 10%-90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure
FROM OUTPUT (010)
UNDER TEST

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (aee figure)
Test Condition
A
B

Active High
Active Low

C

Active High
Active Low

R1

TEST POINT

R2

R2

C'
L

CL

3000

3900

50pF

~

3900

50pF

3000

3900

50pF

~

3900

5pF

3000

3900

5pF

'C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

3-201

1994 Data Book

Specifications isp GAL22V1 0

••••••
••••••
••••••
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every ispGAL22V1 0
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user 10 codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V1 0 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice 22V1 0 device type when compiling a set of logic
equations. In addition, many device programmers have two separate selections for the device, typically an ispGAL22V10 and a
ispGAL22V10-UES (UES = User Electronic Signature) or
ispGAL22V1 O-ES. This allows users to maintain compatibility with
existing 22V1 0 designs, while still having the option to use the GAL
device's extra feature.
The JEDEC map for the ispGAL22V1 0 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the ispGAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device programmer.

SECURITY CELL
A security cell is provided in every ispGAL22V1 0 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.

OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(Le., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
The ispGAL22V1 0 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.

INPUT BUFFERS
ispGAL22V10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
The input and 1/0 pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However,
Lattice recommends that all unused inputs and tri-stated 110 pins
be connected to an adjacent active input, Vcc, or ground. Doing
so will tend to improve noise immunity and reduce Icc for the
device. (See equivalent input and 1/0 schematics on the following
page.)

Typical Input Current
----

~--

C

LATCH-UP PROTECTION
ispGAL22V10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the
circuitry to latch. Additionally, outputs are designed with n-channel
pull ups instead of the traditional p-channel pullups to eliminate
any possibility of SCR induced latching.

.:.
;;
~

/'
·20

"

u

;

-40

=

·60

t>.

-

./

./

/'
1.0

2.0

3.0

4.0

5.0

Inpul Voltage (Volts)

DEVICE PROGRAMMING
The ispGAL22V10 device uses a standard 22V10 JEDEC
fusemap file to describe the device programming information. Any
third party logic compiler can produce the JEDEC file for this
device.
The JEDEC file can be used to program the device using a standard PLD programmer or the in-system programming methods
described later in this data sheet.

3-202

1994 Data Book

~~~LatticeM
......
......
......

Specifications isp GAL22V1 0

POWER-UP RESET
Circuitry within the ispGAL22V10 provides a reset signal to all reg.
isters during power·up. All intemal registers will have their Q out·
puts set low after a specified time (tpr, 1118 MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power·up. The
timing diagram for power·up is shown below. Because of the
asynchronous nature of system power·up, some conditions must
be met to guarantee a valid power·up reset of the ispGAL22V1 O.
First, the Vee rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all in·
put and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

Vee

CLK
,

INTERNAL
REGISTER
a· OUTPUT

ACTIVE LOW
OUTPUT REGISTER

VVVVVVVVVVVV\ /

I\AMM/\MMI\Y

ACTIVE HIGH ~
OUTPUT REGISTER

Device Pin
\
Reset to Logic ·t" " - -

Device Pin

. ;

Reset to Logic ·0·

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN~

PIN

Vee
Active Pull·up
Circuit
Tri·State
Control

Vee

,..l. ....

i Vref 1
· .
,

0

•o

•0

•

0
00
0

•
o

o
o
o

o

Data
OUtput

PIN

0

0
0

:o

:

~

.... ... .J

o

(VrefTyplcal = 32V)

0
0

PIN

Feedback
(To Input Buffer)
Output

Input

3-203

1994 Data Book

~

~~~Latticern
......
......
......

Specifications isp GAL22V1 0

IN-SYSTEM PROGRAMMING OVERVIEW
The ispGAL22V10 device can be programmed in a number of
ways. Two options are to build a custom cable to program
devices on your board directly from the parallel port of a PC, or
to build the programming capability right into your system. To
support the software side of either of these solutions, Lattice
provides the ispGAL Download library of programming routines.
These routines are written in ANSI-standard C language, which
can be used either to serve as detailed examples or to be
integrated directly into your system. These routines include
such common operations as Program, Read, and Verify. The
routines are structured so that any hardware-dependent code is
contained in a few well-documented functions, which can be
easily modified for virtually any system. Example programs are
included which use the parallel printer port of an IBM PC or
compatible.

debug of programming circuitry you build into your own system.
Many of the best applications for the ispGAL device use their
ability to reconfigure a system in the field. In any system that
uses a microprocessor, the microprocessor can often be used
to program the ispGAL devices right in the system. The Lattice
ispGAL Download software routines can be used to easily
integrate ispGAL programming capability into your system
software, or allow you to quickly create a custom program for
configuring the system. A typical system is shown below in
Figure 1. Note that the pattern information is normally stored in
the Lattice ispSTREAMTM format, which is a bit-packed format
providing device pattern storage in less than 1/8 that of a
standard JEDEC file. The pattern information may reside either
on-board in an EPROM or EEPROM, or be loaded from an
external source such as a disk or across a network.

In addition, popular third-party programmers provide the ability
to program the devices in a socket, just like conventionally
programmed devices. This is especially useful for engineering

Figure 1. In-System Programming Using ispGAL Download Routines

3-204

1994 Data Book

Specifications ispGAL22V1 0

••••••
......
......
IN-SYSTEM PROGRAMMING OVERVIEW
Another possibility is to use an external system, such as a
portable PC, to change the configuration of a board by reprogramming an on-board ispGAL device (see figure 2 below). This
can be useful for field service personnel to re-configure a board
for testing or to enable optional features. The same method can
be used during the deSign, test or manufacturing phase, before
the board is put into a working system capable of reprogramming
the devices.

When programming multiple ispGAL devices, the ISP serial
interface allows the user to cascade multiple ISP devices in a
serial daisy chain (see figure 3). This serial daisy chain interface
provides the flexibility to program all daisy chained devices at
once or one at a time through a 4-wire interface. To program the
serial devices one at a time, the Lattice ISP FLOWTHRU
instruction is provided to bypass the serial devices that are not
to be programmed.

Lattice provides a stand-alone utility program that uses the PC
parallel port to program ispGAL devices through a cable. Also,
the ispGAL software library can be used to easily create custom
programs for programming the ispGAL devices through your
own interface. Example programs using the PC parallel port are
included in the ispGAL Download software.

If you have any questions about programming the ispGAL
devices, please contact Lattice Application Engineering at 800327-8425 or 503-693-0201.

End-Product P.C. Board

Parallel Port
Connection

Figure 2. Configuring the ispGAL Device from a Remote System

Serial Data Path

I

SOO

Signals from
Programming
Controller
(System Processor)

SOl

SOl

MOJ)E

MOOE

SCLK

SCLK

I

SOO

ispGAL
Device

ispGAL
Device

ispGAL
Device

r

..-----

SOl

SOO

SOl

-

MOOE
SCLK

I

SOO

I--

MOOE
SCLK

4

II

Parallel Control Path
Figure 3. ISP Serial Daisy Chain

3-205

1994 Data Book

."::

H~Latticeru

Specifications isp GAL22V1 0

••••••
••••••
••••••

The ispGAL uses a similar programming algorithm and programming parameters to other Lattice ISP devices. The devices
generate their own intemal supervoltage for programming, and
only require standard TIL signals to program. Programming the
ispGAL device is centered around a 3-state state machine, with
its state transitions controlled by two control signals. One of the
states is the normal operation state, with the other two states
controlling the programming process. The ISP programming
state machine is controlled by four dedicated programming pins
on each device, which are described below. During normal
device operation the 501, MODE and SCLK pins should be tied
low.

the internal serial shift registers and to clock the state machine
between states. State changes and shifting data in is done on
a low-to-high transition. When shifting data out, the data is
available on 500 only after asubsequent high-to-Iowtransition.
When MODE is high, SCLK controls the programming state
machine, and when MODE is low, SCLK acts as a shift register
clock to shift data in or out or to start an operation.

SERIAL PROGRAMMING INTERFACE
The ispGAL devices are programmed using the four dedicated
programming interface pins: 501, MODE, 500 and SCLK.

PROGRAMMING STATE MACHINE OPERATION
The programming state machine controls which mode the device
is in, and provides the means to read and write data to the device
(see figure 4). The four dedicated control pins are used to load
and unload data, and to control the state machine. The state
machine is a 2 bit state machine, with three defined states: iDLE
(00), SHIFT (01) and EXECUTE (10). Instruction codes are
shifted into the device in the SHIFT state, and control which
instruction is to be executed in the EXECUTE state. In the SHI FT
and EXECUTE states all the 1/0 pins are tri-stated. To transition
between states MODE is held high, 501 is set to the appropriate
level, and SCLK is clocked.

Serial Data In (501) performs two differentfunctions. First asthe
input to the serial shift register, and second as one of the two
control pinsforthe programming state machine. Because ofthis
dual role, the function of 501 is controlled by the MODE pin.
When MODE is low, 501 is the serial input to the shift registers
and when MODE is high, 501 becomes a control signal. Internal
to the device, the 501 is multiplexed to various shift registers in
the device. The different shift instructions of the state machine
determine which of these shift registers gets the input from 501.
The MODE signal, combined with the 501 signal, controls the
programming state machine, as described in this section.
Serial Clock (SCLK) isthe serial shift register clock used to clock

Load

Shift

10

10

Serial Data Out (500) is the output of the serial shift registers.
The selection of shift register is again determined by the state
machine's shift instruction. When MODE is driven high, 500
connects directly to the 501, bypassing the device's shift registers.

The IDLE state is the default state of the state machine. In this
state the device is in normal operation, and programming
operations are disabled. Each device contains a hardwired eight
bit 10 code, which can be read from this state. The IDLE state
may be reached from any other state by setting MODE high, 501
low, and clocking SCLK.

Load
Command

Note:
Control signals: MODE, SOl

Figure 4. Programming State Machine

3-206

1994 Data Book

Specifications ispGAL22V10

••••••
••••••
••••••
The SHIFT state provides the means to load an instruction into
the state machine. A five bit instruction is loaded into the state
machine by holding MODE low and clocking in the instruction,
via SDI. The entire Instruction Set is shown below in Table 1.
Once an instruction is loaded into the state machine, it may be
executed in the EXECUTE state. The SHIFT state is reached
from either of the other two states by setting MODE and SDI
high, and clocking SCLK.
The EXECUTE state is where the instruction that was shifted in
during the SHIFT state is actually executed. An individual
instruction execution is started by taking MODE low and clocking
SCLK.

Instruction Operation

The Device ID shift register is only accessible in the IDLE state.
It is eight bits long, and is only used to shift outthe device ID. For
ispGAL22Vl0, the ID is defined to be 08 (hex). The Instruction
shift register is only accessible in the SHIFT state. It is five bits
long, and is only used to shift the Instruction Codes into the
device. The Data and Instruction shift registers expect the LSB
shifted in first. The Data shift register is 138 bits long, and is used
to shift all addresses and data into or out of the device. The Data
shift register is only accessible in the EXECUTE state when
executing a SHIFT_DATA instruction. The architecture shift
register is 20 bits long and the OLMC 1's Sl architecture bit is
shifted in first and OLMC 1O's SO architecture bit is shifted in last.
The architecture shift register is accessed during EXECUTE
state when ARCH_SHIFT instruction is executed.

Description

00000

Nap

No operation performed.

00010

SHIFT_DATA

Clocks data into, or out of,
the Data Shift Register.

00011

BULK_ERASE

Erases the entire device.

00101

ERASE_ARRAY

Erases everything except
the Architecture rows.

00110

ERASE_ARCH

Erases the Architecture
rows only

00111

PROGRAM

Programs the Serial Shift
Register data into the
addressed row

01010

VERIFY

Load data from the
selected row into the
Serial Shift Register.

01101

10PRLD

Preload the 1/0 register
with given data.

01110

FLOWTHRU

Disables the Shift Register
(SDI=SDO).

10100

ARCH SHIFT

Enables the Architecture
shift register for shifting
data into or out of the
register.

Table 1. Instruction Codes
SHIFT REGISTERS
The ispGAL device has four shift registers, the Device ID shift
register, the Instruction shift register, the Data shift register, and
the Architecture shift register. All shift registers operate on a
First In First Out (FI Fa) basis, and are chosen by which state the
programming state machine is in.

To program an ispGAL device, data is read from a serial bit
stream and shifted into the shift registers. The data is read 138
bits at a time, shifted into the device, and then a programming
operation is performed. The exact sequence, and the methods
for converting a JEDEC map into a serial bit stream is explained
in the Device Architecture section.

TIMING
Programming the ispGAL devices properly requires that a number
of timing specifications be met. Most critical are the specifications
relating to programming and erasing the PCMOS cells. In
addition to a minimum pulse width, there is also a maximum
specification for these parameters. Table 2 lists the programming
mode specifications for the ispGAL device. Diagrams for the
programming mode specifications are shown in Figures 5, 6,
and 7 on the following page.
INTERNAL ARCHITECTURE
This section explains the internal architecture of the device as it
relates to programming. This section is not strictly necessary to
the programming of the device if you are using the Lattice
software tools provided.
The key to easy programming of the ispGAL device is the use of
a bit-stream of all the data that needs to be shifted into a device
to program it. Lattice calls this bit-stream format an ispSTREAMTM
format. The ispSTREAM format uses one bit to represent the
state of each olthe programmable cells, instead olthe byte value
used in a JEDEC file. Considering the additional characters in a
JEDEC file, this means a space savings of more than a factor of
eight. In addition, the ispSTREAM does not require any parsing.
The bits are simply read from the file and shifted into the device.
Since 804 bytes are required to store the pattern for an ispGAL
device, multiple patterns can be stored in a small space.
This section mainly concerns the details of constructing the
ispSTREAM format. If you are using the supplied software tools,
a conversion utility (complete with source code) is included to
convert an industry-standard JEDEC file to an ispSTREAM
format. All of the Lattice software routines read from and write to
this ispSTREAM format.

3-207

1994 Data Book

~~~Latticem
......
......
......

Specifications isp GAL22V1 0

The ispGAL device have three basic sections to their programming architecture (see figure 8). There are 44, 132-bit wide rows
of AND array section, one 64-bit wide row of User Electronic
Signature (UES) section and one 20-bit wide row of architecture
information.

address bits must also be shifted into the shift register along with
the AND array data. Executing a PROGRAM command following
the combination of data and row address shift programs the row
that is specified by the shift instruction. The UES row is unique
from the AND array data rows in that it is only 64 bits long. When
the row address bits are added to the row the total shift register
length required to fully specify the UES row is 70 bits long. In
other words only 70 bits out of 132 bit shift register is used for
UES. The 20-bit long architecture shift register is selected when
ARCH_SHIFT instruction is executed. The OLMC 0, S1: OLMC
0, SO; OLMC 1, S1: OLMC1, SO: etc. are shifted in order with the
last bit of the shift register being OLMC 10, SO.

The AND array section of the physical layout is organized so that
each column of JEDEC fuse numbers shown in the logic
diagram of ispGAL22V10 corresponds to one row of shift
register for the device layout. This translates to each physical
row being 132 bits long. With each row of AND array data, there
is a 6-bit row address associated with it. Including the row
address bits makes the shift registers 138 bits long. These row
Paramo

Description

trst

Time from power-up of device to any progamming operation.

Min.
1

Max.
-

Ils

tisp

Time from leaving IDLE state to I/O pins tri-state, or entering IDLE state to I/O pins active.

-

10

tsu
th

Setup time, from either MODE or SOl to rising edge of SCLK.

100

-

J.lS
ns

Hold time, from rising edge of SCLK to MODE or SOl changing level.

100

tco

Time from falling edge of SCLK to data out on SDO.

tclkh

Clock pulse width of SCLK while high.

0.5

tclkl

Clock pulse width of SCLK while low.

0.5

tpwp

Time for a programming operation.

40

tpwe
tpwv

Time for an erase operation.

200

ms

Time for a verifv operation.

5

us

Unit

ns
150

ns
Ils

100

J.lS
ms

Table 2. Programming Mode Timing Specifications

Vee

MODE

-{~h

MODE
SOl

SOl

I~su~~I~
_____~______
~_ICOJk~______~~~

SCLK _____

SCLK
liSP~

I/O pins

HI-Z

IISP~

_____

SOO
(

VALID

Figure 5. Programming Mode Timing

Figure 6. Shift Register Timing

1 - - - - Enter EXECUTE state (PROGRAM, VERIFY, or ERASE instruction)

MODE
Ipwp, IPW9,
or Ipwv

SOl
Isu 1/--____,

SCLK
Figure 7. Program, Verify, & Erase Timing

3-208

1994 Data Book

Specifications ispGAL22V1 0

• •••••
......
..•...
ispStream Format
To convert the information in a standard JEDEC file into the
ispSTREAM format, all of the addressing information is added,
as well as the place-holding bits to fill to the next byte boundary.
The objective is to have every bit that is shifted into the device
for programming included in the ispSTREAM format. For the
AND array rows, this means simply adding six bits to the end of
each row. For the UES row, there are 2 bits to add. And for the
architecture row 4 bits are added. These additional bits must be
properly handled when data is shifted into the shift register. The
proper number of bits must be incremented to forward the
ispSTREAM bits to point to the next correct address bit.

The ispSTREAM uses one bit for each programmable cell. This
means that each AND array row will take 138 bits. Similarly, 64
bits for the UES and 20 bits for the architecture. One extra byte
is used at the front of the file to store the device ID code. This ID
code is the same as the one hardwired into the device. The
purpose of including this ID code is to be sure the ispSTREAM
type matches that of the device to be programmed. All
ispSTREAM formats, regardless of which Lattice In-System
Programmable device they are for, will contain this ID code as
the first byte. By reading this ID code, you can tell which device
the ispSTREAM is for. If the ispSTREAMs are stored in EPROM
for instance, they will be stacked end to end, and the ID code will
help to determine not only which device type it belongs with, but
how long it is, and thus where the next pattern starts.

..
I

8-bit 10 Shift Register
SOl

SOl

---+I B7 B6...

--+I

... B1 BO

~ SOO

~SOO

138-bit Address/Data Shift Register

Row Addr: 0

000000

1

000001

•

JEDEC Fuse #: 5764,5720,5676 ...
JEDEC Fuse #: 5765,5721,5677 ...

... 0088,0044,0000
... 0089,0045,0001

~

e

....
....

4--6 bits - - . ~---- -- - --- - -132 bits --- ------- -1- ................ ~
AND Array (5808 bits) :

42
43
44

101010
101011
101100

.

~EDEC Fuse #: 5806 5762 5718 ...
... 0130,0086,0042
JEDEC Fuse #: 5807,5763,5719 ...
... 0131,0087,0043
~EDEC Fuse #: 5891,5890 ...
UES (64 bits)
... 58295828

Architecture Shift Register
SOl

EDEC Fuse #: 5826,5827,5824 ...

... 5811,5808,5809

---.

SOO

Figure 8. ispGAL Device ShiH Register Layout

3-209

1994 Data Book

~~~Latticem

Specifications isp GAL22V1 0

••••••
••••••
••••••

ISP PROGRAMMING TOOLS SUPPORT
To assist users in implementing ISP programming, Lattice
provides ispGAL C language routines included with the ispGAL
Download software which implement the basic ISP functions for
programming through the PC parallel port. This section provides
the details of the PC parallel port definition needed to program
the ispGAL.

9 below defines the parallel port DB25 pins and the associated
programming signals. This hardware definition is identical to the
Lattice ispLSI programming hardware with the exception of the
ispEN and RESET signals which are defined only for the ispLSI
devices.
The buffer at the parallel port drives the cable that connects the
output ofthe buffer to the ISP programming signals of the device.
It is important to keep the cable length to a minimum to reduce
the loading on the signal drivers. The SOl, SCLK and MODE
inputs to the ispGAL are driven by the buffer connected at the
parallel port. The SDO output signal from the ispGAL is driven
from the device back to the parallel port. If the load on the SOO
signal is more than a minimum cable length and the parallel port
input, it is recommended that the user provide a buffer on the
circuit board to ensure good signal integrity.

PC PARALLEL PORT DEFINITION
The PC parallel port must be properly defined in order to use the
ispGAL software to program the devices. After defining the port,
ispGAL Download software controls the read and write of data
through the parallel port. To guarantee the signal integrity and
drive capability, a 74HC367 (or equivalent) buffer should be
directly connected at the parallel port's DB25 connector. Figure

OB25 Parallel Port
Connector Pins

r---------,
74HC367 :

,

isp Interface

016

Pin 10 _ _ _ _+-_-<..

000

Pin 2

501

001

Pin 3

SCLK

002

Pin 4

MOOE

003

Pin 5

NC

004

Pin 6

006
015

Pin 8 - - - - ,
Pin 12

013
GNO

Pin 15 - Vee Sense
Pin 20 - GNO

1-...' - - - - -

500

NC

4 - NO CONNECT
5 - NO CONNECT
6-501
7-500
V
8- ce

t--- Port Sense
Figure 9. PC Parallel Port Buffer & RJ45 Connector Definition

3-210

1994 Data Book

Specifications isp GAL22V1 0

......
......
......

ispGAL22V1 OB: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vee
1.2 , - - - - - - , - - - , - - - , - - - - ,

o

~1.1+---t--+--+----i

.~
 ,

i/

0.5

~
0.00

.....

,

.;'

E

~

V

40.00

60.00

80.00

100.00

0.00

--r---

10.00 20.00 30.00 40.00 50.00 60.00

0.00

1.00

2.00

3.00

101 (mA)

10h(mA)

10h(mA)

Normalized Icc vs Vee

Normalized Icc vs Temp

Normalized Icc vs Freq.

I--"""

--

o

"..,.---

"C 1,1

~

.........

1

L.9
o

Z

....... .......

......... ~

5.25

5.50

I

I

\

<'
~

l"- t--

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin(V)

..,......,.
V

a

-25

25

50

75

100

125

25

50

75

'DO

Frequency (MHz)

Input Clamp (Vik)

.§.

.....

1.00

~ 0.90

Temperature (deg. C)

Delta Icc vs Vee

1\

)

",........
."..,,-

O.BO

-55

Supply Voltage (V)

1\

1.10

E

......... "

0.8

.§
as

0.7
5.00

4.75

4.00

1.20

1.2

.2

0.8
4.50

.....
3.75

1.3

1

~

0

>
3.5

20.00

l;!,.,

~ 0.9

.c:

~

"C

'"as

~

r-.... ~

V'

'.2

~

4.25

I 'i"'-o..

'0
20
30
40
50
60
70
80
90
'DO
-2.00

,
,
,,

/
,,

-1.50

-1.00

-0.50

0.00

Vik(V)

3-212

1994 Data Book

GAL26CV12
High Performance E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

I/ClK

• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
- 7.5 ns Maximum Propagation Delay
- Fmax = 142.8 MHz
- 4.5ns Maximum from Clock Input to Data Output
- TTL Compatible 16 mA Outputs
- UltraMOS" Advanced CMOS Technology

INPUT
1/0/0

1/0/0

• ACTIVE PULL-UPS ON ALL PINS

1/0/0

• LOW POWER CMOS
- 90 mA Typical Icc

1/0/0

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «lOOms)
- 20 Year Data Retention

..
I

1/0/0

1/0/0

110/0

• TWELVE OUTPUT LOGIC MACROCELLS
- Uses Standard 22Vl0 Macrocells
- Maximum Flexibility for Complex Logic Designs

1/0/0

• PRELOAD AND POWER-ON RESET OF REGISTERS
-100% Functional Testability

1/0/0

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

1/0/0

1/0/0

1/0/0

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION

The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E2 technology
offers high speed «lOOms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V1 0 architecture, the
GAL26CV12 eliminates the learning curve typically associated
with using a new device architecture. The generic architecture
provides maximum design flexibility by allowing the Output Logic
Macrocell (OLMC) to be configured by the user. The GAL26CV12
OLMC is fully compatible with the OLMC in standard bipolar and
CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GALli> products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.

PACKAGE DIAGRAMS

DIP
UClK

PLCC

Il0l0
VO/O
IIOIQ

VOIO
28
I

26

5

25

vee

7

GAL26CV12

2'

IIOIQ
110/0

9

Top View

21

GND

I

I
I

1/0/0

110/0

Il0l0

110/0

I

1 12

14

16

1819

GND

IIOIQ

110/0

Il0l0

1/0/0

Il0l0

---0000

Il0l0

~~~~

Il0l0
Il0l0

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.SA
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

3-213

1994 Data Book

~~~Lattice~

Specifications GAL26CV12

••••••
••••••
••••••

GAL26CV12 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Tsu (ns)

Tco(ns)

Icc (mA)

7.5

6

4.5

130

GAL26CV12C-7LP

28-Pin Plastic DIP

130

GAL26CV12C-7W

26-Lead PLCC

10

7

7

130

GAL26CV12B-l0LP

28-Pin Plastic DIP

130

GAL26CV12B-l0W

26-Lead PLCC

130

GAL26CV12B-15LP

28-Pin Plastic DIP

130

GAL26CV12B-15W

28-Lead PLCC

130

GAL26CV12B-20LP

28-Pin Plastic DIP

130

GAL26CV12B-20W

28-Lead PLCC

15

10

8

2)

12

12

Ordering #

Package

Industrial Grade Specifications
Tpd(ns)

Tsu (ns)

Tco (ns)

Icc (mA)

10

7

7

150

GAL26CV12C-l0LPI

28-Pin Plastic DIP

150

GAL26CV12C-l0WI

28-Lead PLCC

15

10

8

150

GAL26CV12B-15LPI

28-Pin Plastic DIP

150

GAL26CV12B-15WI

28-Lead PLCC

150

GAL26CV12B-20LPI

28-Pin Plastic DIP

150

GAL26CV12B-20WI

28-Lead PLCC

2)

12

12

Ordering #

Package

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL26CV12C
GAL26CV12B

DevIce Name

~

x

X X

' - - - - - - Grade

Speed (ns)
L = Low Power Power - - - - - - - - - - '

3-214

Blank = Commercial
I Industrial

=

Package P = Plastic DIP
J = PLCC

1994 Data Book

~~~LatticeM
••••••
......
......

Specifications GAL26CV12

OUTPUT LOGIC MACROCELL (OLMC)
The GAL26CV12 has a variable number of product terms per
OLMC. Of the twelve available OLMCs, two OLMCs have access
to twelve product terms (pins 20 and 22), two have access to ten
product terms (pins 19 and 23), and the other eight OLMCs have
eight product terms each. In addition to the product terms available
for logic, each OLMC has an additional product term dedicated
to output enable control.

The GAL26CV12 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this
dedicated product term is asserted. The Synchronous Preset sets
all registers to a logic one on the rising edge of the next clock
pulse after this product term is asserted.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.

NOTE: The AR and SP product terms will force the 0 output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.

AR

o
4 TO 1

Q

MUX

Q

SP
2 TO 1 f - - - - - - - - - - - - - - '

MUX
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)

OUTPUT LOGIC MACROCELL CONFIGURATIONS
NOTE: In registered mode, the feedback is from the /0 output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.

Each of the Macrocells of the GAL26CV12 has two primary
functional modes: registered, and combinatorial I/O. The modes
and the output polarity are set by two bits (SO and S1), which are
normally controlled by the logic compiler. Each of these two
primary modes, and the bit settings required to enable them, are
described below and on the the following page.

REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the 0 output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an
individual product term for each OLMC, and can therefore be
defined by a logic equation. The D flip-flop's /0 output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.

COMBINATORIAL VO
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. LogiC polarity of the
output Signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "product
term driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.

3-215

1994 Data Book

.,,"

Specifications GAL26CV12

• •••••
••••••
••••••
REGISTERED MODE

COMBINATORIAL MODE

•

ACTIVE LOW

ACTIVE HIGH

s. = 1

S. =0
S, 1

=

S,

3-216

=1

1994 Data Book

Specifications GAL26CV12

••••••
......
......
GAL26CV12 LOGIC DIAGRAM / JEDEC FUSE MAP

0,

l:,

.... _.

"

16

20

"

28

32

"

<0

"

.
28

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

:=:

0052

2

,

~ ,

"'"'
0520:

~

~

09~ ~
3

J

27

---fOLMc26l

1

26

~
eo,,,
5'

~-

09"'.~.=
,,,,-'"

~

=ltl-=J

~

~

4

1
UTt
~
""

1456. ~

~

'612 -

~r~"t
J
~

~

24

5'

5

""

~

1924 ::

.':'

OLMC23

10

6

~

2496.=

.~

':'

3120

8

J

23

1

22

J

20

~

~

,..4=

CiLMc22

~U
5'

6355

'-----3172

r

=
:=':'

3700 ::

9

~

~"'U
""
5'

~

F tm
t!LJJ

""'.=-'"
.~

4368=

10
"20~

11

25

5'

~ lfr[J

636'
~

'''' -

""'

~

.:=
''''':=

12

""~

~

If+- W:flJ
5'
~
"'"

sm==
13

~ ,

S624.~
,,<0

III

4

m

6262

IIII

-falMc1sl

J

liP

19

18

17

16

15

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

•" '.'.'.'.'.'.'.0
6368,6369 ...

Electronic Signature

..• 6430,6431

3-217

1994 Data Book

.-

~~~Latticem

Specifications GAL26CV12C

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Commercial Devices:
Ambient Temperature (TA) .............•..•........... 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................... -55 to 125°C

Industrial Devices:
AmbientTemperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ......................... +4.5 to +5.5V

1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

V

2.0

-

Vcc+1

V

-

-100

IJA

-

10

IJA

IOL = MAX. Yin = VIL or VIH

-

V

2.4

-

0.5

IOH = MAX. Yin = VIL or VIH

-

V

-

-

16

mA

-

-3.2

mA

-30

-

-130

mA

150

mA

Input High Voltage

ilL'

Input or 1/0 Low Leakage Current

OV ~ VIN ~ VIL (MAX.)

IIH

Input or 1/0 High Leakage Current

3.5V ~ VIN ~ Vee

VOL

Output Low Voltage

VOH

Output High Voltage
Low Level Output Current
High Level Output Current
Output Short Circuit Current

UNITS

0.8

VIH

10H

MAX.

-

Input Low Voltage

los2

TYP."

Vss-O.5

VIL

10L

MIN.

CONDITION

Vcc=5V

VOUT = 0.5V T A = 25°C

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

Outputs Open

VIH = 3.0V flO9gl8 = 15MHz

INDUSTRIAL
Icc

Operating Power

VIL=0.5V

Supply Current

Outputs Open

VIH = 3.0V flogglO = 15MHz

L-10

-

90

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C.

3-218

1994 Data Book

~HLatticeTM

Specifications GAL26CV12C

••••••
••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM
PARAMETER

TEST
COND.'

IND

-7

-10

MIN. MAX.

MIN. MAX.

DESCRIPTION

UNITS

A

Input or 110 to Combinatorial Output

1

tco

A

Clock to Output Delay

1

4.5

tcf2

-

Clock to Feedback Delay

-

2.5

tsu

-

Setup Time, Input or Feedback before Clock i

6

-

th

-

Hold Time, Input or Feedback after Clock

0

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

95.2

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

A

Maximum Clock Frequency with
No Feedback

twh

-

tpd

fmax3

7.5

1

ns

7

ns

2.5

ns

7

-

ns

-

0

-

71.4

-

MHz

117.6

-

105

-

MHz

142.8

-

105

-

MHz

Clock Pulse Duration, High

3.5

-

4

-

ns

i

1

10

-

ns

twl

-

Clock Pulse Duration, Low

3.5

-

4

-

ns

ten

B

Input or 110 to Output Enabled

1

7.5

1

10

ns

tdis

C

Input or 110 to Output Disabled

1

7.5

1

9

ns

tar

A

Input or 110 to Asynchronous Reset of Register

1

9

1

13

ns

tarw

-

Asynchronous Reset Pulse Duration

7

-

8

-

ns

tarr

-

Asynchronous Reset to Clock i Recovery Time

5

-

8

-

ns

tspr

-

Synchronous Preset to Clock i Recovery Time

5

-

10

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

CAPACITANCE (T A

=25

n

C, f

=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

C,

Input Capacitance

8

pF

C'IO

I/O Capacitance

8

pF

TEST CONDITIONS
Vee =5.0V, V,
Vcc

=2.0V
=5.0V. V'IO =2.0V

"Guaranteed but not 100% tested.

3-219

1994 Data Book

Specifications GAL26CV12B

••••••
••••••
••••••
ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................... -55 to 125°C

Commercial Devices:

1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

Ambient Temperature (TA) ........................... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ......................... +4.5 to +5.5V

Ambient Temperature (TA) ............................ 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

MIN.

CONDITION

TYP."

MAX.

UNITS

0.8

V

2.0

-

Vcc+1

V

OV ~ VIN ~ VIL (MAX.)

-

-

-100

IlA

3.5V ~ VIN

-

-

10

itA

-

-

0.5

V

-

V

VIL

Input Low Voltage

Vss-O.5

VIH

Input High Voltage

IlL'

Input or I/O Low Leakage Current

IIH

Input or I/O High Leakage Current

VOL

Output Low Voltage

10L

= MAX. Yin =

VOH

Output High Voltage

10H

= MAX. Yin = VIL or VIH

~ Vee
VIL

or VIH

2.4

10L

Low Level Output Current

-

10H

High Level Output Current

-

los2

Output Short Circuit Current

Vee

= 5V

VOUT

= 0.5V TA = 25°C

-30

16

mA

-3.2

mA

-130

mA

150

mA

COMMERCIAL
Operating Power

VIL

Supply Current

Outputs Open

= 0.5V

VIH

= 3.0V f,oggle = 15MHz

INDUSTRIAL
Icc

= 0.5V

Operating Power

VIL

Supply Current

Outputs Open

VIH

= 3.0V f,oggle = 15MHz

L-15/-20

-

90

I

I

I

I

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C.

=

3-220

1994 Data Book

Specifications GAL26CV12B

••••••
••••••
......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAMETER

TEST
COND.'

COM

COMIINC

-10

-15

-20

MIN. MAX.

MIN. MAX.

MIN. MAX.

DESCRIPTION

COM/INC

UNITS

tpd

A

Input or I/O to Combinatorial Output

3

10

3

15

3

20

ns

tco

A

Clock to Output Delay

2

7

2

8

2

12

ns

tcf'

-

Clock to Feedback Delay

-

2.5

-

2.5

-

10

ns

tsu,

-

Setup Time, Input or Feedback before Clock

tsu,

-

Setup Time, SP before Clock

th

-

Hold Time, Input or Feedback after Clock

A

Maximum Clock Frequency with
External Feedback, l/(tsu + tco)

A

Maximum Clock Frequency with
Internal Feedback, l/(tsu + tcf)

A

Maximum Clock Frequency with
No Feedback

twh

-

Clock Pulse Duration, High

fmax3

l'

l'
l'

7

-

10

-

12

-

ns

10

-

10

-

12

-

ns

0

-

0

-

55.5

-

0

71.4

41.6

-

MHz

105

-

80

-

45.4

-

MHz

105

-

83.3

-

62.5

-

MHz

4

-

6

-

8

-

ns

ns

twl

-

Clock Pulse Duration, Low

4

-

6

-

8

-

ns

ten

B

Input or I/O to Output Enabled

3

10

3

15

3

20

ns

tdis

C

Input or I/O to Output Disabled

3

10

3

15

3

20

ns

tar

A

Input or I/O to Asynchronous Reset of Register

3

13

3

20

3

20

ns

tarw

-

Asynchronous Reset Pulse Duration

8

-

10

-

15

-

ns

tarr

-

Asynchronous Reset to Clock Recovery Time

8

-

10

-

15

-

ns

tspr

-

Synchronous Preset to Clock Recovery Time

10

-

10

-

12

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

CAPACITANCE (T A = 25°C, f = 1.0 MHz)
SYMBOL

PARAMETER

MAXIMUM'

UNITS

CI

Input CapaCitance

8

pF

CliO

I/O Capacitance

8

pF

TEST CONDITIONS
Vee =5.0V, VI

=2.0V
Vee =5.0V, VI/O =2.0V

'Guaranteed but not 100% tested.

3-221

1994 Data Book

~H Latti ce'M

Specifications GAL26CV12

••••••
••••••
••••••

SWITCHING WAVEFORMS

INPUT or
VOFEEDBACK

\\\\i\i\it:;~UT

INPUT or

VO FEEDBACK

COMBI NATORIAl
OUTPUT

\TTT"1\\\\l==

ClK

\\"TTT"\\\\""\\

1""T""'rT\\

REGISTERED
OUTPUT

Combinatorial Output

Registered Output
INPUT or
VOFEEDBACK

OUTPUT
ClK

Input or VO to Output EnablelDisable
REGISTERED
FEEDBACK

fmax with Feedback

ox

~t"T~~

~1r....:Jl....l/...MAM..>L>L..lLJl...c.L6N\-"-,,,--,-_R...:.es,-,e_tt.:..o_Log..:::i..:..c_"oJ."1___

Circuitry within the GAL26CV12 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 11lS MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some

conditions must be met to guarantee a valid power-up reset of the
device. First, the Vce rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Feedback ..

Vee

Active Pull·up
Circuit
Vee

~

t

=:

, ••

l....,

(Vref Typical = 3.2V)

I'~i

+-----,-,"+-1("
".'

PIN

Feedback
(To Input Buffer)

Typical Output

Typical Input

3-225

1994 Data Book

Specifications GAL26CV12

••••••
••••••
••••••

GAL26CV12C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vee
1.2

~1.1

~

~

1

12r---~----'---~~--~

~

r--...... -...

---

~ 0.9

4.60

4.75

1

EO.•

o

z

0.'

-

., V

-g

.!:::!

./

~

Normalized Teo

,.,.

o

0.'

.~

-

1

"iii

./

-I""""

E 0.9
o

Z 0.'

~

"

75

100

Normalized Tsu vs Temp

1.3

"

{!!.

1.2

"i

l'

o.g

o

Z 0.'
26

·25

60

76

.Q.25

~ -0.5

til~

)~

.(l.75

/

~

....

-

~

"

"

.,"
./

100

-66

125

·25

0

26

60

76

100

126

Temperature (deg. C)

Delta Teo vs # of Outputs
Switching

Delta Tpd vs # of Outputs
Switching

"C

~

Temperature (deg. C)

Temperature (deg. C)

~

-

1.1

0.7

·66

126

5.50

1.4

0.7
50

6.26

5.00

Supply Voltage (V)

~

-g'

0.7
25

4.76

4.60

-

1.2

<>

1-"

-

~

Temp

V8

1.3

............

~ 0.9

Supply Voltage (V)

Normalized Tpd vs Temp

a.

j"--..

1

0.9 l-----+---4----I-----I
4.50
4.75
6.00
6.26
5.60

5.60

1.3
"0 1.2

11

~~ 0.9 t----t---;----i---\

Supply Voltage (V)

.... 1.1

1.1

"C

i--

~ 'F=~r_--~~~~

r---

5,25

5.00

~

+----4----+----1f---I

1.1

-g

0.8

"iii

Normalized Tsu vs Vee

Normalized Teo V1I Vee

1-- ....

i

~

-0.25

I

o

~

-0.5

~

til

.(l.75

-- - I--

I

·1

-1

1

2

3

4

5

6

7

8

9

1

10 11 12

2

3

4

5

8

7

8

9 10 11 12

Number of Outputs Switching

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

12
10

~

R

8

~-

- - RISE

--FALLl

8

I-

.l!!

Qj

Cl

2

-2

./

~

"

-,
.....

,

~
50

-2

100

150

200

250

-

~---RISEI
--FALL I

300

1/

L

50

Output Loading (pF)

~

, -V

100

150

200

250

300

OUtput Loading (PF)

3-226

1994 Data Book

~HLatticem

Specifications GAL26CV12

••••••
••••••
••••••

GAL26CV12C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

2.5

~

~

"0 1.5

>

v

1

~

,~

0.00

20.00

3.75

~
.s::

g

~

0.5

3

"-

t'....

2

~

eo.oo

",0.00

60.00

100.00

1

E 0.9

o

Z 0.8

.......

o
o

~

.......

1

i'...

E
0.9
o

.2

-

........

-25

0

25

50

75

100

Delta Icc vs Vin (1 input)

Input Clamp (Vik)

I

I

l/

"'"

r---.. ...... r-

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

20
30

~

40

o

Z

1.00

0.90

./

,.... /

125

o

25

50

75

100

Frequency (MHz)

",.

10
~

./

~ 1.10

roo-

L

./

.~ 1.20

Temperature (deg. C)

.s«

V

1.30

'0

Supply Voltage (V)

~

1.40

0.80
-55

5.50

4.00

3.00

Normalized Icc vs Freq.

0.7

5.25

2.00

1.00

loh(mA)

o

Z 0.8

5.00

-

""""-

0.00

1.50

1.1

V

/
4.75

"'i'--- .....

r---...

1.2

:c i'-.

/'
./

I,

3.25

1.3

./

0.7

4.50

.........

3.5

Normalized Icc vs Temp

1.3

1.2
1.1

.......

g

loh(mA)

Normalized Icc vs Vee

.!::!
"iii

~

.s::

10.00 20.00 30.00 40.00 50.00 80.00

0.00

101 (mA)

~
-g

Voh vsloh

Voh vsloh

Vol va 101

50

V

/

V

/

'/

80
-2.00

-1.50

-1.00

-0.50

0.00

Vik(V)

3-227

1994 Data Book

~~~Lattice~

Specifications GAL26CV12

••••••
••••••
••••••

GAL26CV12B: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc

1 ----o

Z

r-.....

1

0.9

~

4.50

~

:---

E

5.00

4.76

:---

1

:li!E 0.9
0.8
4.50

5.50

5.25

-- -5.00

4.75

r-6.50

5.25

Normalized Tpd vs Temp

Normalized Teo va Temp

Normalized Tsu va Temp

.,..

1

",

E 0.9

1.4

1.3

V

8

1.2

~

1.1

.~

'/

1.2

~

1.1

g

./

0.8

{!!.
'iii

V"

o

1.3

"

,/'r'

E 0.9

Z

./

",

1

"iii

'/

Z

·25

25

50

75

100

25

·25

50

75

1!!

ioo-" ~

,--- .,.......

: [ -0.5

~

~

.,.

~
£!

-1

3

4

5

6

7

B

9

10 11 12

Delta Tpd vs Output Loading

~- - - RISE I
--FALL

,

I
~

1!!
2

-2

75

100

125

~

"""

1

3

~

.,. ~---

.,.

~

2

..

5

8

7

8

9

10 11 12

Delta Teo vs Output Loading
12

t-

o

SO

Number of Outputs Switching

12

'iii

25

Temperature (deg. C)

-2
2

Number of Outputs Switching

X6

-26

~ -1.5

1

.s

·66

126

-0.5

-2

10

100

E

-1.5

'iii'

./

Delta Tco vs it of Outputs
Switching

Delta Tpd vs it of Outputs
Switching

-1

~

Temperature (deg. C)

Temperature (OOg. C)

~

./

1
0.9

0.7

·55

125

../
."

0.8

0.7

0.7

·55

:---

"iii

Supply Voltage (V)

l- 1.1

0.8

0.8
4.50

-- --

1.1

Supply Voltage (V)

R 1.2

o

1

~

'.!:!5l

Supply Voltage (V)

1.3

Z

r--

~ 0.9

5.50

5.25

5.00

4.75

1.1

"iii

0.8

~"iii

1.2

1.2

~1.1

alN

Normalized Tau va Vee

Normalized Tco va Vee

1.2

~

v:. ,,-

./
-"

...

,,'"

--FALL

8

150

250

~

2

300

L.,ooI"

~
50

Output Loading (pF)

""" ...

~

V'" ......

£!

~

200

I

8

-2
100

-"

t--RISEI

t-

~
50

10

l

100

150

200

250

300

Output Loading (PF)

3-228

1994 Data Book

~HLatticem
.•....
••••••

Specifications GAL26CV12

......

GAL26CV12B: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol va 101

Voh va loh

Voh va loh
4.5

2.5

~

2

15

1.5

>

1

~

..... 1--'
'" '"

'-

IL

I......... ~

4.25

........

0.00

20.00

40.00

80.00

80.00

100.00

0.00

3.5
0.00

~ 1.1
1

---

V

~

!,..--

:g8
~

os

Z

r--....

1.1

5.25

5.50

1

to-....

.........

0.8

-25

~

"

~

,

j

1/

~

t--

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin(V)

V"

0

25

50

75

100

125

25

50

75

100

Frequency (MHz)

Input Clamp (Vlk)

[
..... ~

1.00

..".., V'

~ 0.80

["."""

Temperature (deg. C)

Delta Icc vs Vin (1 input)

1\

4.00

0.80
-55

Supply Voltage (V)

1\

3.00

.."..,

~ 1.10
~

0.7
5.00

4.75

2.00

~

1.20

1.2

E
o.g
o

0.8

4.50

'.00

~

Normalized Icc vs Freq.

1.3

-g

---

loh(mA)

Normalized Icc vs Temp

1.2

o.g

3.75

loh(mA)

Normalized Icc vs Vee

~
~

r""'--

~

10.00 20.00 30.00 40.00 50.00 80.00

101 (mA)

.~

t-.....

~

0.5

~ -...

~

10
20
30
40
50
80
70
80
90
100

,
f
If
f
f
f
IJ'

-2.00

-1.SO

-1.00

~.SO

0.00

Vik (V)

3-229

1994 Data Book

~
I
I

H~Latticem

Notes

••••••
••••••
••••••

3-230

1994 Data Book

GAL 600 1
High Performance E2CMOS FPLA
Generic Array Logic™

••••••
••••••
••••••
FEATURES

FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 30ns Maximum Propagation Delay
- 27M Hz Maximum Frequency
- 12ns Max. Clock to Output Delay
- TTL Compatible 16mA Outputs
- UltraMOS® Advanced CMOS Technology

lN~'tr

• LOW POWER CMOS
- 90mA Typical Icc
• E2
-

CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/Guaranteed 100% Yields
High Speed Electrical Erasure «lOOms)
20 Year Data Retention

• UNPRECEDENTED FUNCTIONAL DENSITY
- 78 x 64 x 36 FPLA Architecture
-10 Output Logic Macrocells
- 8 Buried Logic Macrocells
- 20 Input and VO Logic Macrocells

MACROCELL NAMES
ILMC

• HIGH-LEVEL DESIGN FLEXIBILITY
- Asynchronous or Synchronous Clocking
- Separate State Register and Input Clock Pins
- Functional Superset of Existing 24-pin PAL®
and FPLA Devices

INPUT LOGIC MACROCELL

10LMC 1/0 LOGIC MACROCELL

• APPLICATIONS INCLUDE:
- Sequencers
- State Machine Control
- Multiple PLD Device Integration

BLMC

BURIED LOGIC MACROCELL

OLMC

OUTPUT LOGIC MACROCELL

PIN NAMES

DESCRIPTION
Using a high performance FCMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24pin, 300-mil package.

10 - 1'0

INPUT

I/O/Q

ICLK

INPUT CLOCK

Vee

BIDIRECTIONAL
POWER (+5)

OCLK

OUTPUT CLOCK

GND

GROUND

PIN CONFIGURATION
DIP

PLCC
I/ICLK

The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC).
In addition, there are 10 Input Logic Macrocells (ILMC) and 10
110 Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.

~
s !i!
•

Advanced features that simplify programming and reduce test
time, coupled with FCMOS reprogrammable cells, enable 100%
AC, DC, programmability, and functionality testing of each
GAL6001 during manufacture. This allows Lattice to guarantee
100% performance to specifications. In addition, data retention
of 20 years and a minimum of 100 eraselwrite cycles are
guaranteed.

7

GAL6001

Ne
I

Top View

9

.11

12

24

Vee
I/O/Q

.s 2•

I/O/Q

2.

I/OIQ

I/OIQ

I

6

,. ,. ,.,.
!i! g ~ ~
"

6001

IIOIQ

18

NC

21

I/OIQ

GAL

I/OIQ
I/OIQ

I

'-'

~ ~ ~
28

•

1

I/OIQ

I/OIQ

VOIQ

I/OIQ

VOIQ
I/O/Q

0

z

I/O/Q

I/OIQ

GND

12

13

OCLK

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681·3037

3-231

1994 Data Book

Specifications GAL6001

••••••
••••••
••••••
GAL6001 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Fclk(MHz)

Icc (mA)

30

27

150

GAL6001 B-30LP

24-Pin Plastic DIP

150

GAL6001 B-30LJ

28-Lead PLCC

Ordering #

Package

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL6001B

Devlce_e~

x

' - - - - - Grade

Speed (ns)
L = Low Power

X X

Power - - - - - - - - - - '

3-232

Blank = Commercial

' - - - - - - Package P = Plastic DIP
J", PLCC

1994 Data Book

Specifications GAL6001

• •••••
......
••••••

INPUT LOGIC MACROCELL (ILMC) AND 1/0 LOGIC MACROCELL (IOLMC)
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
10LMC to the 1/0 pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as
a clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility. With

the GAL6001 , external registers and latches are not necessary.
Both the ILMC and the 10LMC are block configurable. However,
the ILMC can be configured independently of the 10LMC. The
three valid macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.

OUTPUT LOGIC MACROCELL (OLMC) AND BURIED LOGIC MACROCELL (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are
called the Buried Logic Macrocells (BLMC), and are useful for
building state machines. The second group of macrocells consists of 10 cells whose outputs, in addition to feeding back into
the AND array, are available at the device pins. Cells in this group
are known as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or DIE-type register.
Output macrocells always have 1/0 capability, with directional control provided by the 10 output enable (OE) product terms. Additionally, the polarity of each OLMC output is selected through the
"0" XOR. Polarity selection is available for BLMCs, since both
the true and complemented forms of their outputs are available
in the AND array. Polarity of all "E" sum terms is selected through
the"E" XOR.
When the macrocell is configured as a DIE type register, it is
clocked from the common OCLK and the register clock enable
input is controlled by the associated "E" sum term. This configuration is useful for building counters and state-machines with state
hold functions.

When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its "E" sum term
is routed directly to the clock input. This permits asynchronous
programmable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are
reset to a logic zero. If connected to an output pin, a logic one
will occur because of the inverting output buffer.
There are two possible feedback paths from each OLMC. The
first path is directly from the OLMC (this feedback is before the
output buffer and always present). When the OLMC is used as
an output, the second feedback path is through the 10LMC. With
this dual feedback arrangement, the OLMC can be permanently
buried (the associated OLMC pin is an input), or dynamically
buried with the use of the output enable product term.
The DIE registers used in this device offer the designer the ultimate in flexibility and utility. The DIE register architecture can
emulate RS-, JK-, and Hype registers with the same efficiency
as a dedicated RS-, JK-, or T-register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.

3-233

1994 Data Book

•

~~~Latticem

Specifications GAL6001

••••••
••••••
••••••

ILMC AND IOLMC CONFIGURATIONS
ICLK

E
Q

MUX
D
INVALID
REG.
INPUT

Q

or 110

0

0

0

1

1

0

1

1

AND
ARRAY

D

LATCH

ISYN

ILMC/IOLMC
Generic Logic Block Diagram

ILMC (Input Logic Macroce")
JEDEC Fuse Numbers

10LMC (110 Logic Macroce")
JEDEC Fuse Numbers

ISYN

LATCH

ISYN

LATCH

8218

8219

8220

8221

3-234

1994 Data Book

~~~Latlice'M

Specifications GAL6001

••••••
••••••
••••••

ILMC AND IOLMC CONFIGURATIONS

1-

,

i

NC

INPUT
PINS 2-11_+'_ _ _ _ _ _-+10_ _ _ _ _

~

VOPINS
14-23

IClK

JI1ClK
---------------i

-r-f-I'Q::-

,

1

~~
TO
AND

INPUT
PINS 2-11 , 10
OR ......;.~f-----I D
If0 PINS
14-23

ARRAY

1-

Asynchronous Input
ISYN

10
TO
AND
ARRAY

_______________

_

Latched Input

LA~CH I

ISYN

LATCH

o

o

IClK

Q

INPUT
PINS 2-11
10
REGISTER
OR
--r---f---j D
If0 PINS
14-23

1-----+--+-"1
10
TO
AND
ARRAY

Registered Input
ISYN

o

I

LA~CH

3-235

I

1994 Data Book

H~Lattice~
••••••

Specifications GAL6001

••••••
••••••

OLMC AND BLMC CONFIGURATIONS
,

OE

,PRODUCT
: TERM

AND'

ARRAY

RESET

MUX

OLMCONLY

i iXORD(i)
D

~~,

L

,

1

9~

R

0

Q-----"
-'

9D-~

C~S(i)

0

OS~i)

-E

XORE(i)

1

D

MUX
Vcc-

E

IOLMC

,"----

OLMCONLY

1
MUX

'-----

0

-

1

OCLK

OLMC/BLMC
Generic Logic Block Diagram

OLMC (Output Logic Macrocell)

BLMC (Buried Logic Macrocell)

JEDEC Fuse Numbers

JEDEC Fuse Numbers

OLMC

OCLK

OSYN

XORE

XORD

BLMC

OCLK

OSYN

XORE

0

8178

8179

8180

8181

7

8175

8176

8177

1

8182

8183

8184

8185

6

8172

8173

8174

2

8186

8187

8188

8189

5

8169

8170

8171

3

8190

8191

8192

8193

4

8166

8167

8168

4

8194

8195

8196

8197

3

8163

8164

8165

5

8198

8199

8200

8201

2

8160

8161

8162

6

8202

8203

8204

8205

1

8157

8158

8159

7

8206

8207

8208

8209

0

8154

8155

8156

8

8210

8211

8212

8213

9

8214

8215

8216

8217

3-236

1994 Data Book

Specifications GAL6001

• •••••
......
••••••
OLMC AND BLMC CONFIGURATIONS

~~::~ ~~ ...................... ~
RESET

RESET

_fi J, ~ _
, 0.

,
\
\
\

Ne

~

FROM
OR

.

XOR

ARRAYE~

~

,,

I/O ~
I
,
I OLMCONLY \

FROM
OR
ARRAY

i

IOLMC

i
E-.I

NC

Ne
OCLK

OCLK

DIE Type Registered
OSYN(i)

Combinatorial
OSYN(i)

OCKS(i)

OCKS(i)

o

o

RESET

I,
I: XOR

,

I,

D_

OLIIIC ~
ONLY;;

_

1 ..... __ .... __ ........... ,,1

FROM
OR
ARRAY

y"

.DR

I

i

NC

L ______

1_ - - - - - - - - - -

j

oeLK

D Type Register
with Sum Term
Asynchronous Clock
OCKS(i)

o

3-237

1994 Data Book

•

Specifications GAL6001

• •••••
••••••
••••••
GAL6001 LOGIC DIAGRAM

~~I
I

D>

(0

"UX
t-.

'"

Ill..,

~n n~

'"

...

J

_

0

nn

~ o~

q
0

n

~ ~
H
0 0 o
el
0

0

t=
t=
f=
f=
~

•
l

:Jg
'-----

"UX

I

nn U i i

~~l

QQQQQQQ~Q(l

g~:!.!!?.~t::.e~::~~

3-238

1994 Data Book

~

........
........
I •••••••

23(27)

"""
..."""r~

22(26)

n

o=0(1)--1
_. :iE :::r
:::l~;::;:<1>

21(25)

Q.rog.:::l

_. =(I)

g.

_.
=
cq

:::l _. C

3

(I)~=o"

g.
~ ~. ~
...... 0 ...... 0

20(24)

lllo.<1>(l)Co.o

iSle=+:

<1> col III CD'
::"""3<»
Q 3 III 3-

19(23)

en x -.
1ll:iE -.~
2';::;:3-0

1

=OC ....

c.l

N
~

<1>~38..
x :::l 0 C
"2. 10 - 0

Ill» ............

1

~:g~coI

18(21)

17(20)

g5'::D3
?g;.~(I)

0<1> ......

:::l ....

(I)

......

:::r

16(19)

1ll

<1>

g.

CJ)

"C
CD

(1)03"
III

9<1>'<

III

1

C')

15(18)

~

C')

Q)
~

111111111111111111111111l1li111111111111111111111111111111111111
~

~

RESET

~t:L

14(17)

o

:::J

(J)

13(16)

OCLK

~
.....

S
.....

~
~
o

"

II

Specifications GAL6001

••••••
••••••
••••••
ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Commercial Devices:
Ambient Temperature (TA) ••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP."

MAX.

UNITS

Vss-O.5

-

0.8

V

2.0

-

Vcc+1

V

IJA

VIL

I nput Low Voltage

VIH

Input High Voltage

ilL'

Input or I/O Low Leakage Current

OV::o:; VIN ::0:; VIL (MAX.)

-

IIH

Input or I/O High Leakage Current

3.5VIH ::0:; VIN ::0:; Vec

-

-100

-

10

IJA

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

10H = MAX. Yin = VIL or VIH

2.4

-

-

V

10L

Low Level Output Current

-

-

16

rnA

10H

High Level Output Current

-

rnA

Output Short Circuit Current

-

-3.2

los2

-130

rnA

Vce=5V

VouT=0.5V

-30

COMMERCIAL
Operating Power

VIL = 0.5V

Supply Current

ftoggle = 15MHz Outputs Open

VIH = 3.0V

1) The leakage current is due to the internal pull-up on all pins.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA

=25

2

C, f

=1.0 MHz)
MAXIMUM"

UNITS

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

I/O Capacitance

10

pF

Vee = S.OV, V'IO = 2.0V

SYMBOL

PARAMETER

C,
C'IO

TEST CONDITIONS

"Guaranteed but not 100% tested.

3-240

1994 Data Book

......
••••••

Specifications GAL6001

••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM
PARAMETER

TEST
COND'.

-30

DESCRIPTION

MIN. MAX.

UNITS

tpdl

A

Combinatorial Input to Combinatorial Output

-

30

ns

tpd2

A

Feedback or I/O to Combinatorial Output

-

30

ns

tpd3

A

Transparent latch Input to Combinatorial Output

-

35

ns

tcol

A

Input latch IClK to Combinatorial Output Delay

-

35

ns

tc02

A

Input Reg. IClK to Combinatorial Output Delay

-

35

ns

tc03

A

Output DIE Reg. OClK to Output Delay

-

12

ns

~
I

tc04

A

Outout 0 Rea. Sum Term ClK to Outout Delav

-

35

ns

tsul

-

Setup Time, Input before Input latch IClK

2.5

-

ns

tsu2

-

Setup Time, Input before Input Reg. IClK

2.5

ns

tsu3

-

Setup Time, Input or Feedback before DIE Reg_. OClK

25

tsu4

-

Setup Time, Input or Feedback before 0 Reg. Sum Term ClK

7.5

tsu5

-

Setup Time, Input Reg. IClK before DIE Reg. OClK

30

tsu6

-

Setup Time, Input Reg. IClK before 0 Reg. Sum Term ClK

15

-

thl

-

Hold Time, Input after Input latch IClK

5

-

ns

th2

-

Hold Time, Input after Input Reg. IClK

5

-

ns

th3

-

Hold Time, Input or Feedback after DIE Reg. OClK

0

-

ns

th4

-

Hold Time, Injlut or Feedback after 0 Reg. Sum Term ClK

10

-

ns

fmax

-

Maximum Clock Frequency, OClK

27

-

MHz

twhl

-

IClK or OClK Pulse Duration, High

10

-

ns

twh2

-

Sum Term ClK Pulse Duration, High

15

-

ns

twll

-

IClK or OClK Pulse Duration, low

10

ns

twl2

-

Sum Term ClK Pulse Duration, low

15

tarw

-

Reset Pulse Duration

15

-

ten

B

Input or I/O to Output Enabled

-

25

ns

tdis

C

Input or I/O to Output Disabled

-

25

ns

ns
ns
ns
ns

ns
ns

A

Input or I/O to Asynchronous Reg. Reset

-

35

ns

tarrl

-

Asynchronous Reset to OClK Recovery Time

20

ns

tarr2

-

Asynchronous Reset to Sum Term ClK Recovery Time

10

-

tar

ns

1) Refer to Switching Test Conditions section.

3-241

1994 Data Book

~~~Latticem

Specifications GAL6001

••••••
••••••
••••••

SWITCHING WAVEFORMS
INPUT or
1/0 FEEDBACK

COMBINATORIAL
OUTPUT

\\\\\\\r

INPUT or
1/0 FEEDBACK

VALID INPUT

l~tpd1.~,-"'"'\\\,\""\\\\"'\\\TTT\\\~
"\

~\\ fVALIDINPUT!\\\\ \\ \ \

\\\

l~tsu2

2~U

,--------

IClK (REGISTER)

Combinatorial Output

COMBINATORIAL
OUTPUT

INPUT or
1/0 FEEDBACK

OClK

IClK (lATCH)

Sum Term ClK

~11=

COMBINATORIAL
OUTPUT

-:i___
Registered Input

------

latched Input

.~

INPUT or
1/0 FEEDBACK

VALID INPU-,.----y \ \ \ \ \ \

_~ ~_b_U_4~_~_~~_'
__

Sum Term ClK

INPUT or
1/0 FEEDBACK

OClK

_ __

\\\\\\\\\\\\\\\\~'-----

==

tc03~

1/fmax----'
REGISTERED
OUTPUT

REGISTERED
OUTPUT

Registered Output (Sum Term ClK)

illill\\\\\\\\\~V\
Registered Output (OClK)

INPUT or
1/0 FEEDBACK
INPUT or
1/0 FEEDBACK
DRIVINGAR

OUTPUT

REGISTERED
OUTPUT

Input or I/O to Output EnableJDlsable

SumTermClK

IClKor
OClK

ytWh2

OClK

Sum Term ClK

~tarr1

Asynchronous Reset

Clock Width

3-242

1994 Data Book

Specifications GAL 600 1

••••••
••••••
......
fmax DESCRIPTIONS
elK

eLK

1<111<111--- Isu ----Jl~.,.IL

-

II--PTL->H

~

1.1

al
.~

1

~

~ 0.9

I---RISE~
I - - FALL

--- -. -.

4.50

4.75

5.00

5.25

1.3

- - - PTH->L

a.
1-11 --PTL->H

al·

1

4.75

Z

0.8

5.00

1

OJ

E

5.25

--FALL

1

-

~~

:J

..... ~

10--"'"

EO.•
o

Z

{!!.

-25

25

50

75

100

~

-1

ll!

~ -1.5

Z

-55

25

-25

~

",

V
i-""""

I..--"

0.8

50

75

100

125

·25

-55

Temperature (deg. C)

~
.IfI' ~

,
v.: ~1'"

I..--' k'

25

50

75

100

125

Temperature (deg. C)

Delta Teo vs # of Outputs
Switching

I("'

-

---RIS~~
--FALL

~

-0.5

~

-1

ll!

~ ·1.5

-

, ~ ~ .....
, -~ ~
,
j..""
---RISE~
1/

-

--FALL

-2
6

9

7

10

3

1

Number of Outputs Switching

4

6

7

Delta Teo vs Output Loading
12

12

10

~

~---RISEI

8

--FALL

~

6

ll!
CD

2

I

./
./

/

V_ ,
./

./

-- -

10

~

8

8

6

150

200

250

300

- - RISE I

--FALL

,/

I

,/

.L

ll!

V

2

-2
100

~-

l-

~

~-

50

10

9

Number of Outputs Switching

Delta Tpd vs Output Loading

-2

PTH->L

1

~ O.

-2

o

--PTL->H

OJ

Delta Tpd vs # of Outputs
Switching

-0.5

5.50

0.7

Temperature (deg. C)

~

- - -

1.2

.~ 1.1

0.8

125

1.3

"0

0.7
-55

5.25

Normalized Tsu vs Temp

CD

1="-

5.00

1.4

~

0.7

4.75

4.50

5.50

Normalized Teo vs Temp

"0 1.1
.~

- r--

I""--

Supply Voltage (V)

~---RISE

OJ

--

- - - PTH->L
--PTL->H

Supply Voltage (V)

1.2

o

1..",00 ~

OJ
o

~ io"'"

al
.!:::!

1.3

-

~

1.1

0.8

0.8
4.50

5.50

Normalized Tpd vs Temp

EO.•

...

{!!.

~ 0.9

Supply Voltage (V)

.~

:J

~ 0 .•

0.8

"0 1.2

Normalized Tau va Vee

Normalized Teo va Vee

,

",-"

L

-

,

1/-"- ./
o

50

100

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-246

1994 Data Book

Specifications GAL6001

••••••
••••••
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vohvs loh

Vol vs 101
2.5

4.5

J

~ 1.5

g

1

... V

0.5

./

"

V

4.25

.......... .........

40.00

60.00

0.00

80.00

10.00

Normalized Icc vs Vee

(,J

1.10

E

0.90

~

~

---

~

1.1

~

ijl

20.00

30.00

40.00

50.00

5.00

i'-.

........

1

~

~

0.9

Z

5.25

5.50

-55

~

~

......

·25

25

1

II

0.5

~

<'
$

~

"- ........ ......

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

2.00

3.00

4.00

75

"

100

1.00

V
~

,..-

~

~ 0.90
0.80
125

25

50

75

100

Frequency (MHz)

Input Clamp (Vik)

,

10
20

~

1.10

E

Temperature (deg. C)

2.5

I~
I I'..

1.00

Normalized Icc vs Freq.

..§

0.8

Delta Icc vs Vin (1 input)

1.5

0.00

ijl

(;

Supply Voltage (V)

<'
$2

60.00

10h(mA)

0.7
4.75

4.50

'-

3.75

..........

1.20

.t:!

0.80

Cl

..........

Normalized Icc vs Temp
1.2

ijl

..§
~

............

I

30
40

I

,
,
,

50
60
70
80
90
100
-2.00

1/

-1.50

-1.00

-0.50

0.00

Vik(V)

3-247

.I

"- -r-r----

0

10h(mA)

1.20

~ 1.00
lIS

\.

.s::

>
3.5

20.00

101 (rnA)

~

~

. /V

0.00

..§

Voh vs loh

1994 Data Book

Notes

••••••
••••••
......

3-248

1994 Data Book

GAL 6002
High Performance E2CMOS FPLA
Generic Array Logic™

••••••
••••••
••••••
FEATURES

FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 15ns Maximum Propagation Delay
- 75MHz Maximum Frequency
- 6.5ns Max. Clock to Output Delay
- TTL Compatible 16mA Outputs
- UltraMOS" Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS

•

• LOW POWER CMOS
- 90mA Typical Icc
• E2
-

CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/Guaranteed 100% Yields
High Speed Electrical Erasure «100ms)
20 Year Data Retention

• UNPRECEDENTED FUNCTIONAL DENSITY
- 78 x 64 x 36 FPLA Architecture
- 10 Output Logic Macrocells
- 8 Buried Logic Macrocells
- 20 Input and VO Logic Macrocells

MACROCELL NAMES
ILMC

INPUT LOGIC MACROCELL

10LMC 110 LOGIC MACROCELL

• HIGH-LEVEL DESIGN FLEXIBILITY
- Asynchronous or Synchronous Clocking
- Separate State Register and Input Clock Pins
- Functional Superset of EXisting 24-pin PAL®
and FPLA Devices

BLMC

BURIED LOGIC MACROCELL

OLMC

OUTPUT LOGIC MACROCELL

PIN NAMES

• APPLICATIONS INCLUDE:
- Sequencers
- State Machine Control
- Multiple PLD Device Integration

10 - 110

DESCRIPTION
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 3OQ-mil package. FCMOS technology offers
high speed «100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC).
In addition, there are 10 Input Logic Macrocells (ILMC) and 10
110 Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacturing. As a result,
Lattice is able to guarantee 100% field programmability and
functionality of all GAL products. Lattice also guarantees 100
eraselrewrite cycles and data retention in excess of 20 years.

INPUT

ICLK

INPUT CLOCK

OCLK

OUTPUT CLOCK

110/0

BIDIRECTIONAL

Vee
GND

POWER (+5V)
GROUND

PIN CONFIGURATION

DIP

PLCC
1

IItCLK

~

s
I

u

z

28

•

2.

I/OIQ

2.

I/OIQ
I/OIQ

I

7

GAL6002

NC

1

•

111

12

Top View

I.
c

z

"

Vee

~ ~ ~

23

1

NC

21

,. ,."
~ ~ ~ ~

I/OIQ

•

I/OIQ

GAL
6002

I/OIQ
IIOIQ
I/OIQ
I/OIQ

VOIQ
I/OIQ

IfOIQ

I/OIQ

IfOIQ

UO/Q
I/OIQ
GND

12

OCLK

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1·800·FASTGAL; FAX (503) 681-3037

3-249

1994 Data Book

I
!

~~~Latticem

Specifications GAL6002

••••••
••••••
••••••

GAL6002 COMMERCIAL DEVICE ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)

Fclk(MHz)

Icc (rnA)

15

75

135

GAL6002B-15LP

24-Pin Plastic DIP

135

GAL6002B-15LJ

28-Lead PLCC

135

GAL6002B-20LP

24-Pin Plastic DIP

135

GAL6002B-20LJ

28-Lead PLCC

20

60

Package

Ordering #

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL6002B Devloe Name

~
Blank = Commercial

Speed (ns)
L = Low Power

Power - - - - - - - - - - '

3-250

' - - - - - - Package P = Plastic DIP
J = PLCC

1994 Data Book

Specifications GAL6002

......
••••••
••••••

INPUT LOGIC MACROCELL (ILMC) AND 1/0 LOGIC MACROCELL (IOLMC)
The GAL6002 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
10LMC to the 1/0 pins (14-23). Each input section is individually
configurable as asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as
a clock input for registered macrocells. Individually configurable
inputs provide system designers with unparalleled design flexibility.
With the GAL6002, external input registers and latches are not
necessary.

Both the ILMC and the 10LMC are individually configurable and
the ILMC can be configured independently of the 10LMC. The
three valid macrocell configurations and its associated fuse
numbers are shown in the diagrams on the following pages. Note
that these programmable cells are configured by the logic compiler
software. The user does not need to manually manipulate these
architecture bits.

OUTPUT LOGIC MACROCELL (OLMC) AND BURIED LOGIC MACROCELL (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are
called the Buried Logic Macrocells (BLMC), and are useful for
building state machines. The second group of macrocells consists
of 10 cells whose outputs, in addition to feeding back into the AND
array, are available at the device pins. Cells in this group are
known as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinational, D-type
register with sum term (asynchronous) clock, or DIE-type register.
Output macrocells always have 1/0 capability, with directional
control provided by the 10 output enable (OE) product terms.
Additionally, the polarity of each OLMC output is selected through
the programmable polarity control cell called XORD. Polarity
selection for BLMCs is selected through the true and complement
forms of their feedbacks to the AND array. Polarity of all E (Enable)
sum terms is selected through the XORE programmable cells.
When the output or buried logic macrocell is configured as a
DIE type register, the register is clocked from the common OCLK
and the register clock enable input is controlled by the associated
"E" sum term. This configuration is useful for building counters
and state-machines with count hold and state hold functions.

sum term is routed directly to the clock input. This permits
asynchronous programmable clocking, selected on a register-byregister basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. All registers reset
to logic zero. With the inverting output buffers, the output pins will
reset to logic one.
There are two possible feedback paths from each OLMC. The
first path is directly from the OLMC (this feedback is before the
output buffer). When the OLMC is used as an output, the second
feedback path is through the 10LMC. With this dual feedback
arrangement, the OLMC can be permanently buried without losing
the use of the associated OLMC pin as an input, or dynamically
buried with the use of the output enable product term.
The DIE registers used in this device offer the designer the
ultimate in flexibility and utility. The DIE register architecture can
emulate RS, JK, and T registers with the same efficiency as a
dedicated RS, JK, or T registers.
The three macrocell configurations are shown in the diagrams on
the following pages. These programmable cells are also
configured by the logic compiler software. The user does not need
to manually manipulate these architecture bits.

When the macrocell is configured as a 0 type register with a sum
term clock, the register is always enabled and the associated "En

3-251

1994 Data Book

Specifications GAL6002

••••••
••••••
••••••
ILMC AND IOLMC CONFIGURATIONS
lelK

-------,-----

LATCH

E

MUX
INVALID

REG.
INPUT

or 110

----+----

QI-------I

0

0

0

1

1

0

1

1

AND
ARRAY

+----10

LATCH(i) ISYN(i)

ILMCIIOLMC
Generic Logic Block Diagram

Input Macrocell JEDEC Fuse Numbers

110 Macrocell JEDEC Fuse Numbers

INSYNC

INLATCH

ILMC

IOSYNC

IOLATCH

8218

8219

0

8238

8239

9

8220

8221

1

8240

8241

8

8222

8223

2

8242

8243

7

8245

6

IOLMC

8224

8225

3

8244

8226

8227

4

8246

8247

5

8228

8229

5

8248

8249

4
3

8230

8231

6

8250

8251

8232

8233

7

8252

8253

2

8234

8235

8

8254

8255

1

8236

8237

9

8256

8257

0

3-252

1994 Data Book

Specifications GAL6002

••••••
••••••
••••••
OLMC AND BLMC CONFIGURATIONS

OE
: PRODUCT
AND: TERM
ARRAY

IOLMC

RESET

.1.

..

MUX

OLMCONLY

: :XORD(i)

i

1

;

.•

D-+-~D-c-----~4---j
MUX

0

Vee

o

Q

I
I

E

XORE(i)

E~

~

1

1
OCLK

OLMC/BLMC
Generic Logic Block Diagram

OLMC JEDEC Fuse Numbers

BLMC JEDEC Fuse Numbers

OLMC

CKS

OUTSYNC

XORE

XORD

BLMC

CKS

OUTSYNC

XORE

0

8178

8179

8180

8181

7

8175

8176

8177

1

8182

8183

8184

8185

6

8172

8173

8174

2

8186

8187

8188

8189

5

8169

8170

8171

3

8190

8191

8192

8193

4

8166

8167

8168

4

8194

8195

8196

8197

3

8163

8164

8165

5

8198

8199

8200

8201

2

8160

8161

8162

6

8202

8203

8204

8205

1

8157

8158

8159

7

8206

8207

8208

8209

0

8154

8155

8156

8

8210

8211

8212

8213

9

8214

8215

8216

8217

3-253

1994 Data Book

........
••••••••
••••••••
...
••• r-

lelK

···AJ

2(3) u3(4)

_.
=

1111111111

1(2), /

11111111 111111111111111111111111111111111111111111111111

_---r."",,-,-

n

-

4(5)

--

CD.

5(6)
6(7)
7(9)
8(10) '---,

9(11)
11(13)

,BLMC2 ~
OLMC3

,BLMC5 ~

~
"""C7

w
N

....

C1I

-

en

--

~
~

~
~

~

co

e.g

CI

s
8'

'"

0-

---

W(

0?iWiffi(

¢WlffiWlffi

~
~

~
~
~

-~~

'"0
CD

()

~

()

~

o

::J

en

~
....

g
2

~
I". :W,a ..,..
BLMC7

~ __'-lc
~

rl~- "-"ao- 'R- 'JiU
,

f5G -~

BLMC6J"L

.:-/1.
~

'

h'
ORO

BLMC5J"L
XCRE ........

~
'

ORO

,

U-_4--lL
E

o

BL~

XORE

,

o

ORO

c.u
N

8l

BLMC3

~
'-'-_=t-->-L']"'XORE

EO~

'V
ORO,

'

,

++-_g'--£L

CD
CD

~

o

~

OJ

8><"

III

II II

II

I

~LMC~9
~ Jt1tttttf-H1lo--------I--L-D~
I
- ...,
II

-

III

~~LMC8,~~
XaR'

0'R'a

XORE

22(26)

~

0

-

",

-

.""

XORE

"

~LMC6
XOAD

r-

III

XOR'

0

21(25)

:

_.
=
n
CD.

af--l2Jm'tHrtt~----JL---.1_'

20(24)

R'l1'l

~

~LMC5mrtttfl>------;!-----A-Y
0

f!11

C»

-u

~~:2~~I~+WJ---- J

XOR'

I

'1

~LMC7~±R~'ffir~~---~~
~

...

23(27)

"

0

19(23)

0

R'

' :.:~~,,~r--=cr±;==:::::::r.=l'l~Nrt-ttt-H-jI>+~-_-_-_-_-1_Lr
Jt
"

H--bf¥r=t-l"':~
~~,.;;;~
B~LMCO

......

I

........
••••••••
........
...
r...

XORE

:'

-LMC4

18(21)

0

XORO

,0

-

" ,

0

:: :::.
~

17(20)

_I

m1tli>-----l----4----l7

~LMC2~~R~'lffirli+------~
XCAD

0

XCR'

,E

~

0

~C1

XORO

0

XORE

1

a

0

m'tjtI--------I!-----.1--"?

_

I

CD

(")

~

(")

"f'l1'l
0

16(19)

(J)
"'C

aH.QJ

--K.....d

15(18)

•

I

0

~

,
_ .'
'1'"
=i1ffim=~III~ffiit~lfW'~ltHl'w~~OLMCO
~J~~'m=ct1rt---'~ff
iqi======================================~~~~~~~~~~~~~~~~~:XO:RE~~~'~E~~=
OCLK

OJ
.-+
::::::I

14(17)

_

I

13(16)

_

I

-u

(J)

....0)~
()

2

Specifications GAL6002

••••••
......
••••••
ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo

Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C

Commercial Devices:
Ambient Temperature (TA) ••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V

1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP.'

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

IlL'

Input or I/O Low Leakage Current

OV :<;; Y,N :<;; V,L (MAX.)

-

-

-100

~

IIH

Input or I/O High Leakage Current

3.5V :<;; V,N:<;; Vec

-

10

I1A

VOL

Output Low Voltage

IOL = MAX. Yin = V,L or V,H

-

0.5

V

VOH

Output High Voltage

IOH = MAX. Yin = V,L or V,H

2.4

-

-

V

10L

Low Level Output Current

-

-

16

rnA

10H

High Level Output Current

-

-

-3.2

rnA

los2

Output Short Circuit Current

-30

-

-130

rnA

Vce=5V

VOUT = 0.5V TA = 25°C

COMMERCIAL
Operating Power

V,L = 0.5V

V,H = 3.0V

Supply Current

ftoggl. = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL

PARAMETER

MAXIMUM"

UNITS

TEST CONDITIONS

C,

Input Capacitance

8

pF

Vee = 5.0V, V, = 2.0V

CliO

I/O Capacitance

8

pF

Vcc = 5.0V, V,tO = 2.0V

"Guaranteed but not 100% tested.

3-256

1994 Data Book

Specifications GAL6002

••••••
••••••
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAM.

TEST

COND'.

COM

COM

·15

·20

DESCRIPTION

UNITS

MIN. MAX MIN. MAX

tpdl

A

Combinatorial Input to Combinatorial Output

-

15

-

20

ns

tpd2

A

Feedback or I/O to Combinational Output

-

15

-

20

ns

tpd3

A

Transparent latch Input to Combinatorial Output

-

18

-

23

ns

tcol

A

Input Latch IClK to Combinatorial Output Delay

-

20

-

25

ns

tc02

A

Input Reg. IClK to Combinatorial Output Delay

-

20

-

25

ns

tc03

A

Output DIE Reg. OClK to Output Delay

-

6.5

-

8

ns

tc04

A

Output D Rea. Sum Term ClK to Output Delav

-

18

-

20

ns

tcf12

-

Output DIE Reg. OClK to Buried Feedback Delay

-

3.6

-

7

ns

tcf22

-

Output DReg. STClK to Buried Feedback Delay

-

10.1

-

13

ns

tsul

Setup Time, Input before Input latch IClK

1.5

-

2

-

ns

tsu2

-

Setup Time, Input before Input Reg. IClK

1.5

-

2

-

ns

tsu3

-

Setup Time, Input or Fdbk before DIE Reg. OClK

11.5

-

ns

Setup Time, Input or Fdbk before D Reg. Sum Term ClK

5

-

13

tsu4

7

-

ns

tsu5

-

Setup Time, Input Reg. IClK before DIE Reg. OClK

15

-

20

-

ns

tsu6

-

Setup Time, Input Reg. IClK before D Reg. Sum Term ClK

7

-

ns

Hold Time, Input after Input latch IClK

3

4

-

ns

th2

-

Hold Time, Input after Input Reg. IClK

3

-

9

thl

4

-

ns

th3

-

Hold Time, Input or Feedback after DIE Reg. OClK

0

-

0

-

ns

6

-

ns

47.6

-

MHz

37

-

MHz

50

-

MHz

th4

-

Hold Time, Input or Feedback after D Reg. Sum Term ClK

4

fmaxP

-

Max. Clock Frequency w/External Feedback, 1/(tsu3+tc03)

55.5

fmax2 3

-

Max. Clock Frequency w/External Feedback, 1/(tsu4+tc04)

43.4

fmax3 3

-

Max. Clock Frequency w/lnternal Feedback, 1/(tsu3+tcfl)

66

-

fmax4 3

-

Max. Clock Frequency w/lnternal Feedback, 1/(tsu4+tcf2)

66

-

50

-

MHz

Max. Clock Frequency wINo Feedback, OClK

75

-

60

-

MHz

fmax5 3

-

Max. Clock Frequency wINo Feedback, STClK

70

-

60

-

MHz

IClK Pulse Duration, High

6

-

7

-

ns

twh2

-

OClK Pulse Duration, High

6

-

7

-

ns

twh3

-

STClK Pulse Duration, High

7

-

8

-

ns

fmax6
twhl

3

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Desciption section.
3) Refer to fmax Desciption section.

3·257

1994 Data Book

~~~Latticem

Specifications GAL6002

••••••
••••••
••••••

AC SWITCHING CHARACTERISTICS (CONT.)
Over Recommended Operating Conditions

PARAMETER

TEST
COND'.

COM

COM

-15

-20

DESCRIPTION

MIN. MAX. MIN. MAX
IClK Pulse Duration, low

6

-

7

-

ns

OClK Pulse Duration, low

6

-

ns

7

8

-

ns

Reset Pulse Duration

12

-

7

STClK Pulse Duration, low

15

-

ns

-

15

-

20

ns

-

20

ns

20

ns

14

-

ns

tarw

-

ten

B

Input or I/O to Output Enabled

tdis

C

Input or I/O to Output Disabled

-

15

tar

A

Input or I/O to Asynchronous Reg. Reset

-

16

-

Asynchronous Reset to OClK Recovery Time

11

Asynchronous Reset to Sum Term ClK Recovery Time

4

-

twl1
twl2
twl3

tarr1
tarr2

UNITS

6

ns

1) Refer to SWitching Test Conditions section.

3-258

1994 Data Book

Specifications GAL6002

••••••
••••••
......
SWITCHING WAVEFORMS

\'\\\\\\1

INPUT or
I/O FEEDBACK

INPUT or
I/O FEEDBACK

VALID INPUT

'~tPd1 '~,-----""\\\\""%\C"TTT\\\""\
\\~

COMBINATORIAL
OUTPUT

\\\\\\ r

Y\\\\\\\

VALID INPUT

l~tsu2

2~U

,-----------I

IClK (REGISTER)

I

.-

COMBINATORIAL
OUTPUT

Combinatorial Output

OClK

INPUT or
1/0 FEEDBACK

Sum Term ClK

IClK (lATCH)

~__________tc__o1~

COMBINATORIAL
OUTPUT

Registered Input

latched Input
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
OClK

tco3~

Sum Term ClK

REGISTERED
OUTPUT

REGISTERED
OUTPUT

\\\\\\\\\\\~\~\\\G==
Registered Output (OClK)

Registered Output (Sum Term ClK)
INPUT or
I/O FEEDBACK

m

_

u

1=----=*'~

-----------INPUT or
I/O FEEDBACK
DRIVINGAR

-~~Id"]~~"'1=

OUTPUT

REGISTERED
OUTPUT

-----Input or 110 to Output Enable/Disable

SumTermCLK

IClKor
OClK

Sum Term ClK

JM3

OCLK

. - tarr1

Asynchronous Reset

Clock Width

3-259

1994 Data Book

~HLatti ce
••••••

T

Specifications GAL6002

•

••••••
••••••

fmax DESCRIPTIONS
elK

elK

1H

Q)

.!::::!

PTH->L

1.1

"0
1

1.2

1.2

"0

{?:

1.1

.!:::!

~o

Z

0.8

1

4.75

5.00

5.25

5.50

4.75

4.50

--PTL-:>H

. ..,..i-"""'"

1

Iii

E 0.9
o

Z

5.25

5.00

E
o 0.9

0.8
4.50

5.50

1.3

o

r~

~

"/ io"

1---

1.2

R1SE
--FALL

1.1

Q)

.!:::!
Iii

1

""... i""'"

E 0.0
o

Z

0.8

-55

-25

25

50

75

100

~

-1

--

::J

~

~

~ -1.5

-25

25

50

75

.........~

(.:-

~

l.".oo' k'

.

~
::[ ·0.5

---RISE~
--FALL

~

E

~

·1

~

~ -1.5

12

6

.$
c;;

2

t--RISEl

Z

./

[....-"

0.8

100

125

-25

-55

25

50

75

100

125

Temperature (deg. C)

... ~ ;..;::.

. . .. ~ I-'
,/

~

---RISE~

V

--FALL

o

I

~

./

~.

12

./

/

Cl

~---RISEI
--FALL I

8

150

200

250

2

V"

.

.

.

l.?" •
./
50

300

/

~

~

~

./

6

t-

-2

1 00

./

10

:[ 8

L
50

10

Number of Outputs Switching

Delta Tco vs Output Loading

..
.
v. .

--FALL

t-

-2

V'

10

Delta Tpd vs Output Loading

"&.

1

o 0.9

"",10'
/

-2

o

8

--PTL->H

Delta Teo vs # of Outputs
Switching

Number of Outputs Switching

l

- - - PTH->L

1.2

"C
~ 1.1

~

-2

10

1.3

Temperature (deg. C)

. /~

5.50

Normalized Tsu vs Temp

""...

Delta Tpd vs # of Outputs
Switching

·0.5

5.25

0.7

-55

125

5.00

1.4

0.8

Temperature (deg. C)

~

4.75

Supply Voltage (V)

0.7

0.7

--PTL-:>H

r--

Normalized Tco vs Temp

.

PTH-:>L

--- - --

1

Z

Normalized Tpd vs Temp

.!::::!

.!:::!
Iii

Supply Voltage (V)

1.3

-g

al

-- ---

0.9

Supply Voltage (V)

- - -

- - - PTH-:>L

::J
~ 1.1

0.8

4.50

~,.,

I---RISE~
I
FALL

--- --

-g

~

~ 0.9

"C 1.2

Normalized Tsu vs Vce

Normalized Tco vs Vcc

1.2

100

150

200

250

300

Output Loading (pF)

Output Loading (pF)

3-263

1994 Data Book

Specifications GAL6002

••••••
••••••
••••••
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vohva loh

Vol va 101
2.5

g

4.5

I

)1

~ 1.5
1
0.5

a ",.
0.00

,. ,,/

~

/'

1.10

al

~ 1.00

E

~ 0.90

4.25

.......... r-....

20.00

40.00

60.00

80.00

0.00

~

Cl

1
0.5

- --......

"-

3.75

........

10.00 20.00

30.00 40.00

50.00 60.00

0.00

1.00

2.00

--

3.00

10h(mA)

10h(mA)

Normalized Icc va Vee

Normalized Icc va Temp

Normalized Icc vs Freq.

-----~

4.75

5.00

5.25

al

1

~

0.9

........

(;
0.8
0.7

-55

5.50

-25

I

V

~

,~

0.00 O.SO 1.00 1.50 2.00 2.50 3.00 3.50 4.00

VineY)

"

.......

~os

~

~

1.00

V"

~

~

~

0.90

0.80

75

100

125

25

50

75

100

Frequency (MHz)

Input Clamp (Vik)

~

~

1.10

"0

Temperature (deg. C)

«
g

I~

.l;l

25

10
20

I

~

.t:!

Z

4.00

1.20

i'.
.l;l'.'

2.5

1.5

r---......

101 (mA)

Delta Icc va Vln (1 input)

Jj

...........

3.5

Supply Voltage (V)

2

r\.

f;

1.2

0.80
4.50

«
g

~

.s:::

a

1.20

.l;l

Voh va loh

30
40
50
60
70
80
90
100

L
I
I

IL
f
f
f

-2.00

-1.50

-1.00

-0.50

0.00

Vik(V)

3-264

1994 Data Book

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Introduction to ispGOS ......................................................................... 4-1
ispG OS22/18/14 Oatasheet .................................................................. 4-5
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information

4-i

4-ii

Introduction to ispGDSTM
Lattice, the pioneer of non-volatile in-system
programmable (ISPTM) logic has now expanded the
application of ISP to include programmable system
interconnect. The new ispGDS (Generic Digital SWitch)
family combines the in-system programmability, high
performance and low power of Lattice's GAL
programmable logic technology with a switch matrix
architecture, resulting in an innovative programmable
signal router. The ispGDS is a configurable switch matrix
which provides the ability to quickly implement and change
p.c. board connections without changing mechanical
switches or other system hardware. ISP allows the
connections to be reprogrammed without removal from
the p. c. board via a simple SV, 4 wire serial interface.
This capability allows the system designer to define
hardware which can be reconfigured in-system to meet a
variety of applications. The ispGDS also conserves
board real estate, providing up to 22 II0s in about a
quarter square inch of board space.

AO

With today's demand for user-friendly systems, there is
an increasing need for hardware which is easily
reconfigured under software control without manual
intervention. The Lattice ispGDS family is an ideal
solution for end-system feature reconfiguration and signal
routing applications. The fast 7.Sns propagation delay
through the devices supports high-performance signal
routing applications. Easiersystem upgrades, userfeature
selection and system manufacturing are the results.
The ispGDS also provides higher quality and reliability
than other switch solutions due to the nature of E2CMOS
technology. E2CMOS technology supports 100%
testability which guarantees you 100% in-system
programmability and functionality.
There are three members of the ispGDS family: the
ispGDS22, ispGDS18, and ispGDS14. Each of the
devices operate identically with the only difference being
the number of 1/0 cells available .

. . - - - - - ' - - - - SCLK

Programming
Circuitry

A1
A2

SOl

MODE

L-_ _ _ _~-,-SDO

A3

«
i

A4

~

PROGRAMMABLE -+--+---1
SWITCH MATRIX

AS

III AS
A7

Figure 1.
Diagram

AB

ispGDS22 Functional Block

A9

Each I/O macrocell can be configured as an
input, an inverting or non-inverting output, or
a fixed TTL high or low output. Any 1/0 pin
can be driven by any other 1/0 pin in the
opposite bank. A single input can also drive
one or more outputs in the opposite bank,
allowing a signal (such as a clock) to be
distributed to multiple designations on the
board under software control.

A10

~

m

~~'-1D---~ ___ ~ [b

~

~ [Q ~
BankB

(fOCel!
Closed only when CO=1 and C1=O

Vee

4:1 MUX
01

Swilch

Matrix

4-1

•

i

Introduction to ispGDS
ispGDS Applications
With the ispGDS, designs can be reconfigured without
mechanical devices or user intervention. Provision for
easier system upgrades and feature selection can now

be included in the system's original design. A few
examplesofactualispGDSapplicationsdemonstratethe
possibilities.

PC add-on cards can be configured for
plug-and-play applications with an
ispGDS device.

Port Interface
and 110 Bus
Arbitration

The ispGDS supports reconfiguration of COM
port characteristics and interrupt levels via
software updates through the PC bus
interface. The ispGDS provides the flexibility
so one generic PC card can be reconfigured
by software for multiple applications.

Port

One board design can support two
different microprocessor speeds with the
ispGDS.
System
Logic

System J.lP
Executes
ispGDS

Based on the motherboard processor
configuration, the software directs the ispGDS
to set the clock speed and the hardware for
the correct configuration. The ispGDS
eliminates the need to manually reconfigure
the hardware to support manufacturing
motherboards with different processors.

SIW
Clock Generator

Create a cross point switch with the
ispGDS

J.lP
~

o

E
 <'>

o33

«««
««

o44
It)

oSS

<0'<1"

o66

«

««

o77
00 <0 '1'-1t)

o99

«««
«««
o

~

10

00 <0

«««

0
"'01),,"

1

"'.,.'"

",coo ",coo
~~'"

II II II
0_'"

2
~"'OI)

~~'"

"''''0

o~",

o~",

II II II

~~'"

II II II

3

4

0"''''
",coo
~~'"

II II

II

o~",

000 000 000 000

0

:::::::
ispGDS22:
ispGDS18:
ispGDS14:

810
88
86

0

:::::::

~

B9
B7
85

B8
B6
B4

0

5

O)~'"

co °
--'" 0_'"
II II II
000 000
01)"'0

II

II II

"'0'"
01)
~~'"

o~",

0

0

:::::::

:::::::

:::::::

B7
85

B6

B5

6
""O)~

--'"

01),,"0

II II II

o~",

7
~~g
~-'"
II II II

o~",

8
01),,"0)
01),,"0)

9

10

.,."'''' "''''''"
01),,"0)

01),,"0)

Ii
Ii Ii "iilili'
0_'"

u"Ii

o~",

o~",

000 000 000 000 000

~
B4
84

~
B3
B3
B3

0

:::::::
B2
82
82

0

:::::::
Bl
81
81

0

:::::::
BO
80
BO

User Electronic Signature

Figure 9. ispGDS JEDEC Fuse Map

4-19

1994 Data 800k

H~Lattice~
••••••

Specifications ispGDS

••••••
••••••

To simplify the algorithms, all operations use an ispStream
format as the data structure from which to read from and write
to. The ispStream contains all the address information, and
simplifies all the operations considerably. Working from the
ispStream, the device appears as an array of 16 rows by 24 bits
long.

Program Algorithm
Before programming a device, it must first be erased. Cells can
be programmed (set to a JEDEC zero) using the programming
command, but only an Erase procedure erase a cell (set a cell
back to a JEDEC one). In this algorithm, the entire device is
erased (Bulk Erased), and then the entire device is programmed.
To program a device:
- Call procedure: GeUD ( to check device type)
- Call procedure: Change_State (from IDLE to SHIFT state)

Load Algorithm
The load algorithm below Is the same for all ispGDS devices.
Firstthe 13 rows of array data (11 rows for the array matrix, and
2 for the UES) is read, and then the 3 rows of Architecture
information is read. After each row is read, it is stored in an
ispStream format.
In order to load each row's data into the shift register, it is
necessary to load the address of the row into the appropriate
area of the shift register. Because of the unique way the different
areas of the device are addressed, the simplest way to get the
addresses into the device in the proper order is to use an existing
ispStream to supply those addresses. In other words, the full
data for each row is loaded from the ispStream into the device.
When a VERI FY command is executed, the device's data for that
same row is then loaded into the shift register to be shifted out.
This method will be used in this algorithm.

- Call procedure: Wait (Erase_Time)

When using an existing ispStream to supply the addresses, the
data should not be the same as the expected data, or a failure
to verify may not be detected. To cover this possibility, a pattern
that contains all ones for data can be used (and is supplied with
the software tools provided by Lattice). This ispStream still has
the addresses intact, but all programmable cell data is set to a
one (erased state).

- Call procedure: Change_State ( to SHIFT state)

To load a device:

(Erase entire device)
- Call procedure: Shift_Command, with command: ERASE
- Call procedure: Change_State (to EXECUTE State)
- Call procedure: Execute_Command (starts operation)

- Set row_count =0

- Call procedure: GeUD (to check device)

- Loop until row_count = 15

- Call procedure: Change_State ( from IDLE to SHIFT state)

(Program one row on each loop)

- Set row_count =0

- Call procedure: Shift_Command, with command:
SHIFT_DATA

- Loop until row_count

=15

- Call procedure: Shift_Command, with command:
SHIFT_DATA

- Call procedure: Change_State (to EXECUTE State)
- Call procedure: Shift_Data_ln, with data location in
ispStream at (row_count x 24)

- Call procedure: Change_State (to EXECUTE State)
- Call procedure: Shift_Data_ln, with data location in

- Call procedure: Change_State ( to SHIFT state)

Source ispStream at (row_count x 24)

- Call procedure: Shift_Command, with command:
PROGRAM

- Call procedure: Change_State ( to SHIFT state)

- Call procedure: Change_State (to EXECUTE State)

- Call procedure: Shift_Command, with command: VERIFY

- Call procedure: Execute_Command (starts operation)

- Call procedure: Change_State (to EXECUTE State)

- Call procedure: Wait (Program_Time)

- Call procedure: Execute_Command (starts operation)

- Call procedure: Change_State ( to SHIFT state)

- Call procedure: Wait (Verify-Time)
- Call procedure: Change_State ( to SHIFT state)

- End Loop

- Call procedure: Shift_Command, with command:
SHIFT_DATA
- Call procedure: Change_State (to EXECUTE State)
- Call procedure: Shift_Data_Out, with data location in
Target ispStream at (row_count x 24)
- Call procedure: Change_State ( to SHIFT state)
- End Loop

4-20

1994 Data Book

......
......
......

Specifications ispGDS

Verify Algorithm

Goto_IDLE Procedure

A row by row verification procedure is used to verify the ispGDS
device, and is basically the same as the verify algorithm, except
that each row is compared with (instead of stored in) an
ispStream as the data is shifted out of the device. Note that the
special pattern used for verifying is used to load the addresses,
the same as in the Load algorithm. The

The Goto_IDLE procedure resets the programming state machine to the IDLE state, regardless of which state it is in.

To load a device:

bring SCLK pin High

Procedure Steps:
set MODE pin High, and SDI pin Low
waitTsu

- Call procedure: GeUD (to check device type)

wait Tclkh

- Call procedure: Change_State (from IDLE to SHIFT state)

bring SCLK pin Low

- Set row_count =0

(END Procedure)

- Loop until row30unt = 15

GeCID Procedure

- Call procedure: Shift_Command, with command:
SHIFT_DATA

-Call procedure: Shift_Command, with command: VERIFY

The 8 bit device ID code provides the means to identify the three
different ispGDS devices. The ID is read in the IDLE state by first
loading the ID into the shift register and then clocking the data
out. The ID is loaded by holding MODE high and SDI low and
clocking the device. The ID is clocked out of the device by
holding MODE low and clocking DCLK. Only seven clock cycles
are required, since the first bit is available at SDO after the ID is
loaded.

- Call procedure: Change_State (to EXECUTE State)

8 bit ID codes:

- Call procedure: Execute_Command (starts operation)

Device

Pins

Device ID

- Call procedure: Wait (Verify_Time)

ispGDS22

28

0111 0010 (72 hex)

- Call procedure: Change_State (to SHIFT state)

ispGDS18

24

0111 0001 (71 hex)

- Call procedure: Shift_Command, with command:
SHIFT_DATA

ispGDS14

20

0111 0000 (70 hex)

- Call procedure: Change_State (to EXECUTE State)
- Call procedure: Shift_Data_ln, with data location in
Source ispStream at (row_count x 24)
- Call procedure: Change_State ( to SHIFT state)

- Call procedure: Change_State (to EXECUTE State)

Procedure Steps:

- Call procedure: Shift_Data_Out, with data location a 24
bit temporary buffer

set MODE pin High, and SDI pin Low
waitTsu

- Compare temp row buffer with data location in ispStream
to be verified against, at (row_count x 24)

Set SCLK pin High
wait Tclkh

- Verify Error if the 24 bits don't match

Set SCLK pin Low

- Call procedure: Change_State (to SHIFT state)

set count =0

- End Loop

get value from SDO and store in temp_buffer[Oj

PROCEDURES

set count = 1

This section describes the procedures that make up the program, verify and load algorithms for the ispGDS family of
devices. The procedures are written so each algorithm may be
written in a high-level modular format, calling one olthe following
procedures to actually change pin levels and handle timing.

loop until count == 7
bring SCLK pin High
waitTwh
bring SCLK pin Low

Important: Notice that most of the procedures are written so the
state machine is left in the Shift State ready to perform the next
operation. This point is important in keeping all the routines
compatible.

waitTwl
get value from SDO and store in temp_buffer[countj
End loop
( Device ID code is now stored in the temp_buffer array)
(END procedure)

4-21

1994 Data Book

4 ',

~~~Latticem

Specifications ispGDS

••••••
••••••
••••••

wait Tclkh

Change_State Procedure
The Change_State procedure changes the programming state
machine to the next state, according to the state diagram.

End loop

bring SCLK pin Low

Procedure Steps:

(END Procedure)

set MODE pin High, and SDI pin High

ShifC Data_Out Procedure

waitTsu

The ShifLData_ln procedure explains the steps to clock a row
of data out of the device and store it in an ispStream. This
procedure shifts out 22 bits of data, and is used for all 16 rows.

bring SCLK pin High
wait Th
set MODE pin Low, and SDI pin Low

Procedure Steps:

wait Tclkh

set MODE pin Low

bring SCLK pin Low

waitTsu

(END Procedure)

set count =0
loop until count == 23

ShifC Command Procedure
The Shift_Command procedure shifts a five bit command into
the device's shift register. The various commands should be
coded so the procedure can use a mnemonic (such as
PROGRAM), and the controlling software will use the appropriate
five bit sequence for that command.
Procedure Steps:

bring SCLK pin High
wait Tclkh
bring SCLK pin Low
get value of SDO pin and store as next bit in ispStream ( bit
number count x row_number)

=

End loop

set MODE pin Low

(END Procedure)

set count =0

Execute_Command Procedure

loop until count == 4
get next bit of command code (count

=bit number)

set SDI pin to bit value

The Execute_Command procedure causes many of the
commands to begin executing after the state machine is in the
EXECUTE state.

waitTsu

Procedure Steps:

bring SCLK pin High

set MODE pin Low, and SDI pin Low

wait Tclkh

waitTsu

bring SCLK pin Low
count

bring SCLK pin High

=count +1

waitTwh

End loop

bring SCLK pin Low

(END Procedure)

(END Procedure)

ShifC Data_'n Procedure

Wait Procedure

The Shift_Data_ln procedure explains the steps to clock a row
of data into the device, reading the data from an ispStream. This
procedure shifts in 22 bits of data, and is used for all 16 rows.
Procedure Steps:
set MODE pin Low
set count =0
loop until count

== 23

get next bit from ispStream ( bit number
row_number)

= count x

The Wait procedure simply waits the indicated time period, to
make sure various timing parameters are met. This procedure is
most likely to be used when executing the PROGRAM and
ERASE procedures, which need a long delay (tens of
milliseconds). The other timing parameters may be able to be
guaranteed by the system timing, although the wait procedure
can also be used. The various timing parameters should be
coded so that a mnemonic (such as PROGRAM_TIME) may be
passed to the procedure. This procedure will be system
(hardware) specific.

set SDI pin to bit value

Procedure Steps:

waitTsu

wait the indicated time

bring SCLK pin High

(END Procedure)

4-22

1994 Data Book

Specifications ispGDS

......
......
••••••

ISP PROGRAMMING TOOLS SUPPORT
To assist users in implementing the ISP programming, Lattice
provides ispGDS Download softwareC language routines which
implement the basic ISP functions for programming through the
PC parallel port. This section provides the details ofthe ispGDS
C code and the PC parallel port definition needed to program the
ispGDS.

device. It is important to keep the cable length to a minimum to
reduce the loading on the signal drivers. The SDI, SCLK and
MODE inputs to the ispGDS are driven by the buffer connected
at the parallel port. SDO output signal from the ispGDS is driven
from the device back to the parallel port. If the load on the SDO
signal is more than a minimum cable length and the parallel port
input, it is recommended that the user provide a buffer on the
circuit board to ensure signal integrity.

PC PARALLEL PORT DEFINITION
The PC parallel port must be properly defined in order to use the
ispGDS software to program the devices. After defining the port,
it is just a matter of using the ispGDS software to read and write
from the parallel port. To guarantee the signal integrity and drive
capability, a 74HC367 (or equivalent) buffer should be directly
connected at the parallel port's DB25 connector. Figure 10
below defines the parallel port DB25 pins and the associated
programming signals. This hardware definition is identical to the
Lattice ispLSI programming hardware with the exception of the
ispEN and RESET signals which are defined only for the ispLSI
devices.

ISP SOFTWARE INTERFACE
In addition to the hardware interface, the ispGDS Download C
language routines take care ofthe ispGDS programming software
interface. The software interface must implement routines to
read and write from the parallel port, to translate JEDEC fusemap
to and from the stream file format, and to toggle the ISP hardware
signals connected at the output port. Predefined routines for
these functions such as gds_program, gds_read, gds3erify,
etc. are provided with the ispGDS download software which is
available on the Lattice BBS at (503) 693-0215 under the file
name GDSPKG.ZIP.

The buffer at the parallel port drives the cable that connects the
output of the buffer to the ISP programming signals of the

D825 Parallel Port
Connector Pins

r-74HC367-1,

Also available within the GDSPKG.ZIP file is a compiler that
supports all the ispGDS devices. These utilities can also be
obtained from your local Lattice sales representative.

isp Interface

016

Pin 10 _ _ _ _+-_<

000

Pin 2

SOl

001

Pin3

SCLK

002

Pin 4

MODE

003

Pin 5

004

Pin 6

006
015

Pin 8
Pin 12 _ _ _

013
GND

Pin 15 - Vee Sense
Pin 20 - GND

1-...,.'----- SDO

NC

87654321

4 - NO CONNECT
5 - NO CONNECT
6-S01
7-S00

8-Vcc

....Jf- Port Sense

Figure 10. PC Parallel Port Buffer & RJ45 Connector Definition

4-23

1994 Data Book

~~~Latticem

Specifications ispGDS

••••••
••••••
••••••

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Delta Tpd vs It of Outputa
SWitching

Normalized Tpd vs Vee

'.3

1- - -

X '.2

....
~

~

o

Z

~~

1.1

I-PTL.>H

!

';~:

....

1
0.75
0.5
0.25

i---

.

"-

0.9

~
~

5.SO

5.25

5.00

4.75

1

2

3

•

5

'.3
- - - PTH·>l.

,.,
~ ,

....

E 0.9
o

0 .•

.

-PTL·>H

.J

~

~

·55

.. fo;..
~

12

8

7

8

~,o
~ 8

~P'

"B.
....

~

~---RISE

0

75

'00

.
2

~

~

"

0"~~

50

100

ISO

200

2SO

V'

~

3

~

.c

~ 2

80.00

80.00

0.00

~
........

al

~

0.80
•. SO

---

./

l'

0.00

6.26

Supply Voltage (V)

6.50

1.00

2.00

3.00

10h(mA)

Normalized Icc va Temp

Normalized Icc va Freq.

'.00

1.30

r--

Z 0.9

6.00

'-

10h(mA)

-

--

~

1.20

.,V

i

r- r-

:l:!

~

1.10

~ 1.00

........-

./

."

0.90

0.•
4.15

-... r-....

3.25

10.00 20.00 30.00 40.00 SO.DO 80.00

~ 1.1

i

"-

3.5

~

1.2

1.20

~

~~-4~

Voh valoh

~ 3.75

r-.....

Normalized Icc va Vee

~ 1.'0

__

Vin (V)

........ 1'0..

/
00.00

~~

'.25

~~
20.00

__

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

300

Output Loading (pF)

101 (mA)

~ 0.90

.

",

'25

"""

0.00

~

V'
/

.a.SO

Delta Icc vs Vln (1 Input)

Voh vsloh

2.5
2

·1.00

...

~

Vol va 101

0.00

"

I

Vik(V)

; ...
50

I

·,.SO

.A

25

~
(5,.5
> ,

I

80
00
".00

10 11

...

-FALL

8

Temperature (deg. C)

1.00

~60

:!flO

Delta Tpd va Output Loading

"

·25

I

'0

Number of Outputs Switching

0.7

0.5

~

70

,.

X '.2

I

_30

.. ...... ....

......

Nonnallzed Tpd va Temp

~

...

...

~

Supply Voltage (V)

Z

R'SE

20

o ..... 1"'"

0.8
'.SO

,

'0

--FAlL

"B. 1.25

'" ~

,

2.25
2

PTH->l.

Input Clamp (Vile)

-56

·25

25

50

75

100

Temperature (deg. C)

4-24

125

25

50

75

100

Frequency (MHz)

1994 Data Book

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Military Program Overview ................................................................... 5-1
Military Ordering Information ................................................................ 5-3

Military Product Datasheets
GAL16V8 ..... ............... .. ............. ........... ... ...... ............... ....... ... .... .......... 5-5
GAL20V8 .............................................................................................. 5-13
GAL22V1 0 ............................................................................................ 5-21
pLSI and ispLSI 1016 (See Commercial Datasheet)
pLSI and ispLSI 1024 (See Commercial Datasheet)
pLSI and ispLSI 1032 (See Commercial Datasheet)

Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information

5-i

•

5-ii

Military Program
OvelView
CORPORATE PHILOSOPHY
Lattice Semiconductor is committed to leadership in device
performance and quality. Our family of Military GAL
devices is a reflection of this philosophy. Lattice
manufactures all devices under strict Quality Assurance
guidelines. All grades, Commercial through Military 883,
are monitored under a quality program conformant to
MIL-I-38535 Appendix C with inspections conformant to
MIL-I-45208.

MIL-STD-883 COMPLIANCE
MIL-STD-883 defines a uniform and precise method for
environmental, mechanical and electrical testing which
ensures the suitability of microelectronic devices for use
in military and aerospace systems. Table I summarizes
the MIL-STD-883, Class B flow. Table II summarizes the
conformance testing required by MIL-STD-883, Method
5005, for quality conformance testing of Lattice military
microcircuits.

Complete reviews of Lattice's procedures, documentation
and technical data are welcomed and can be arranged at
the Company's facility near Portland, Oregon.

MIL-I-38535
MIL-I-38535 Appendix A and C, when used in conjunction
with MIL-STD-883, define deSign, packaging, material,
marking, sampling, qualification and quality system
requirements for Lattice military devices.

QUALITY AND TESTABILITY
Lattice Semiconductor processes its devices to strict
conformance with MIL-STD-883 Class B. In conjunction
with the military flow, the inherent testability of E2CMOS
technology allows Lattice to achieve a quality level superior
to other PLD technologies.
All devices are patterned and tested dozens of times
throughoutthe manufacturing flow. Every device is tested
under worst case configurations to assure customers
achieve 100% yields. Tests are performed using the
same E2 cell array that will be used for the final patterning
of the devices. This 100% "actual test" philosophy does
away with the correlated and simulated testing that is
necessary with bipolar and UV (EPROM) based PLD
devices.
RELIABILITY
Lattice Semiconductor performs extensive reliability testing
priorto product release. This testing continues in the form
of Reliability Monitors that are run on an ongoing basis to
assure continued process integrity. A formal, written
report ofthese test results is updated regularly and can be
obtained from your local Lattice Sales Representative.
The reliability testing performed includes extensive analysis
of fundamental design and process integrity. The
reprogrammable nature of Lattice devices allows for an
inherently more thorough reliability evaluation than other
programmable alternatives.

5-1

GROUP DATA
Group A and B data is taken on every inspection lot per
MIL-STD-883, Class B requirements. This data, along
with Generic Group C and D data can be supplied, upon
written request, with your device shipment. Your Lattice
sales representative can advise you of charges and
leadtime necessary for providing this data.
STANDARD MILITARY DRAWINGS
Lattice actively supports the DESC Standard Military
Drawing (SMD) Program. The SMD Program offers a cost
effective alternative to source control drawings and
provides standardized MIL-STD-883 product
specifications to simplify military procurement.
A list of currently available SMD qualified devices is
provided (see Military Ordering Information).

•

!

Military Program Overview
MILITARY QUALITY CONFORMANCE
INSPECTIONS (TABLE II)

MILITARY SCREENING FLOW
(TABLE I)
Screen

Method

Requirement

Internal Visual
Temp. Cycling
Constant Acceleration
Hermeticity
Fine
Gross
Endurance Test
Retention Test

2010 Condo B
1010Cond. C
2001 Condo E
1014
Condo AorB
Condo C
1033
Unbiased Bake
24 HRS.
TA= 180°C
Applicable Device
Specification
Tc= 25°C
1015 Condo D
Applicable Device
Specification
Tc= 25°C
PDA=5%
Applicable Device
Specification
Tc= 125'C
Applicable Device
Specification
Tc=-55'C
Applicable Device
Specification
Tc= 25°C
2009
MIL-M-38535,
Appendix A
Sec. 4.5 and
MIL-STD-883
Sec. 1.2

100%
100%
100%
100%

Pre Burn-In Electrical

Dynamic Burn-In
Post Burn-I n Electrical

Final Electrical Test

Final Electrical Test

Final Electrical Test

External Visual
QCI Sample Selection

Subgroup
I Method
GROUP A: Electrical Tests
Subgroups 1, 7, 9
Applicable Device Spec.
Electrical Test
Subgroups 2, 8A, 10
Electrical Test
Subgroups S, 88, 11
Electrical Test

100%
100%

25°C
Applicable Device Spec.
Max. Operating Temp.
Applicable Device Spec.

100%

Bond Strength

100%
100%

Sample
LTPD=2
LTPD=2
LTPD=2

Min. Operating Temp.

GROUP B: Mechanical Tests
Subgroup 2
Solvent Resistance
SubgroupS
Solderability
Subgroup 5

I

4(0)

2015
LTPD = 10
2003
LTPD = 15
2011

GROUP C: Chip Integrity Tests
Subgroup 1
Dynamic Life Test
End Point Electrical
Subgroup 2
Unbiased Retention
End Point Electrical

100%

1005, 1,000 HRS. 125°C
Applicable Device Spec.

LTPD=5

1,000 HRS. 150°C
Applicable Device Spec.

LTPD=5

GROUP D: Environmentallntearitv

100%

Subgroup 1
PhYSical Dimensions
Subgroup 2
Lead Integrity
Hermeticity
SubgroupS
Thermal Shock
Temp. Cycle
Moisture Resistance
Hermeticity
Visual Examination
Endpoint Electrical
Subgroup 4
Mechanical Shock
Vibration
Constant Acceleration
Hermeticity
Visual Examination
Endpoint Electrical
Subgroup 5
Salt Atmosphere
Hermeticity
Visual Examination
Subgroup 6
Internal Water Vapor
Subgroup 7
Lead Finish Adhesion
SubgroupS
Lid Torque

100%

100%
Sample

5-2

LTPD = 15
2016
LTPD=5
2004, Condo B
1014
LTPD = 15
1011, Condo B, 15 Cycles
1010, Condo C, 100 Cycles
1004
1014
1004,1010
Applicable Device Spec.
LTPD = 15
2002, Condo B
2007, Condo A
2001, Condo E
1014
1010,1011
Applicable Device Spec.
LTPD= 15
1009, Condo A
1014
1009
3(0)
1018 < 5,000 PPM, 100°C
LTPD = 15
2025
5(0)
2024

Military Ordering
Information
Lattice offers the most comprehensive line of military
PCMOS Programmable Logic Devices. Lattice
recognizes the trend in military device procurementtowards
using SMD compliant devices and encouragescustomers

to use the SMD number where it exists, when ordering
parts. Listed below are Lattice's military qualified devices
and their corresponding SMD numbers. Please contact
your local Lattice representative for the latest product
listing.

Military Products Selector Guide
Family

ParU

SMD,

T~

Fmax
(MHz)

Icc

~l)

Package

pLSll016-60LHl883

Contact Factory

20

60

100

Max
(mA)
170

plSI

pLSI l024-60LHl883
pLSll032·60LG1883
ispLSll016-60LHI883

Contact Factory
S962·9466801MXC
Contact Factory

20
20
20

60
60
60

130
135
100

215
220
170

68-PinJLCC
84-Pin CPGA
44-PinJLCC

lapLSI

ispLSI 1024-60LHl883
ispLSI 1032-60LGl883

Contact Factory
5962·9308501 MXC

20
20

60
60

130
135

215
220

68-PinJLCC
84-Pin CPGA

GAL16V8B·l OLDl883
GAL16V8B·l0LRl883
GAL 16V8B·l 5LDl883

5962·8983904RA
5962·89839042A
5962·8983903RA

10
10
15

62.5
62.5
50

75
75
75

130
130
130

2O-Pin CERDIP
2O-Pin LCC
2O-Pin CERDIP

GAL 16V88·15LRl883
GAL16VSA·20LDl883

5962·89839032A
5962·8983902RA

15
20

50
41.6

75
75

130
130

2O-Pin LCC
2O-Pin CERDIP

GAL16VSA·20LRl883
GAL16VSA·30LDl883
GAL20V8B·10LDl883

5962·89839022A
5962·8983901 RA
5962·8984004LA

20
30
10

41.6
33.3
62.5

75
75
75

130
130
130

2O-Pin LCC
2O-Pin CERDIP
24-Pin CERDIP

GAL20V8B·l0LRl883
GAL20V8B·15LDl883

S962·89840043A
5962·8984003LA

10
15

62.5
50

75
75

130
130

28-Pin LCC
24-Pin CERDIP

GAL20VSA·15LRl883
GAL20V8B·20LDl883
GAL20VSA·20LRl883

5962·89840033A
5962·8984002LA
5962·89840023A

15
20
20

50
41.6
41.6

75
75
75

130
130
130

28-Pin LCC
24-Pin CERDIP
28-Pin LCC

GAL22Vl0B·15LDl883

5962·8984103LA

15

62.5

90

150

24-Pin CERDIP

GAL22Vl0B·15LRl883
GAL22Vl0B·20LDl883

5962·89841033A
5962·8984102LA

15
20

62.5
33

90
90

150
150

28-Pin LCC
24·Pin CERDIP

GAL22Vl0B·20LRl883
GAL22Vl0B·25LDl883

5962·89841023A
5962·8984104LA

20

33

28-Pin LCC

33

90
90

150

25

150

24·Pin CERDIP

GAL22Vl0B·30LDl883

5962·8984101 LA

30

25

90

150

24·Pin CERDIP

GAL16V8

GAL20V8

GAL22Vl0

5·3

44·PinJLCC

•

Military Ordering Information
DESC Standard Military Drawing Listing
SMO.

SMO.

LATTICE PART.

LATTICE PART.

5962-8983901 HA

GAL16V8A-30LD/883

5962-89840043A

GAl20V8B-10LRl883

5962-89839022A

GAL16V8A-20LRl883

5962-8984004LA

GAl20V8B-10LD/883

5962-8983902RA

GAL16V8A-20LD/883

5962-8984101 LA

GAl22V10B-30LD/883

5962-89839032A

GAL16V8B-15LRl883

5962-89841023A

GAl22V10B-20LRl883

5962-8983903RA

GAL16V8B-15LD/883

5962-8984102LA

GAl22V10B-20LD/883

5962-89839042A

GAL16V8B-10LRl883

5962-89841033A

GAl22V10B-15LRl883

5962-8983904RA

GAL16V8B-1 OLD/883

5962-8984103LA

GAl22V10B-15LD/883

5962-89840023A

GAl20V8A-20LRl883

5962-8984104LA

GAl22V10B-25LD/883

5962-8984002LA

GAl20V8A-20LD/883

5962-9308501 MXC

ispLSI 1032-60LG/883

5962-89840033A

GAl20V8A-15LRl883

5962-9466801 MXC

pLSI 1032-60LGl883

5962-8984003LA

GAl20V8A-15LD/883

Standard Military Drawing Number Description
5962-XXXXX

xx

X
Lead Finish
A
C

=Solder dipped
=Gold plated

Package Type
R = 20-lead
L
2
3

CERDIP

=24-lead CERDIP
=20-pin LCC
=28-pin LCC

Device Class
X

=85-terminal CPGA

Device Type
Drawing Number

5-4

GAL16V81883
High Performance E2CMOS PLD
Generic Array Logic™

••••••
••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES
• HIGH PERFORMANCE E2CMOS" TECHNOLOGY
-10 ns Maximum Propagation Delay
- Fmax = 62.5 MHz
- 7 ns Maximum from Clock Input to Data Output
- TTL Compatible 12 mA Outputs
- UltraMOS" Advanced CMOS Technology

VCLK

~I>-~~~~~~~~~~-,----~--,

1/0/0

• 50% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc

1/0/0

• ACTIVE PULL-UPS ON ALL PINS (GAL16V8B-10)
1/0/0

• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention

1/0/0

1/0/0

• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 20-pin PAL" Devices with Full Function/Fuse Map/Parametric Compatibility

1/0/0

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability

1/0/0

• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade

vOla
1/0E

• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION

PIN CONFIGURATION

The GAL16V8/883 is a high performance FCMOS programmable logic device processed in full compliance to MIL-STD883. This military grade device combines a high performance
CMOS process with Electrically Erasable (F) floating gate
technology to provide the highest speed/power performance
available in the 883 qualified PLD market. The GAL16V8B/883,
at 10ns maximum propagation delay time, is the world's fastest
military qualified CMOS PLD.

CERDIP
LCC

IICLK

Vee

110/0
I

IfCLK Vee

20
I

The generic GAL architecture provides maximum design flexibility
by allowing the Output Logic Macrocell (OLMC) to be configured
by the user. The GAL 16V8/883 is capable of emulating all
standard 20-pin PAL" devices with full function/fuse map/parametric compatibility.

I

4

,.

18

GAL16V8

•

,.

Top View

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice guarantees 100% field programmability and functionality
of all GAL products. Lattice also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.

I

8

11
I

GND

IIOE IIOIQ

110/0

IJOIQ

11010

IJOIQ

UO/Q

1/010

IJOIQ

110/0

IJOIQ

,. ,.

11010

IJOIQ

1/010

IJOIQ

1/0/0

GND

liCE

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

5-5

1994 Data Book

.~

~HLatticem

Specifications GAL 16VBBIBB3

••••••
••••••
••••••

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
Case Temperature (Te) .............................. -55 to 125°C

Supply voltage Vee ....................................... -0.5 to + 7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

CONDITION

PARAMETER

MIN.

TYP.'

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

Vcc+1

V

IlL'

Input or I/O Low Leakage Current

-

-100
-10

J.lA
J.lA

-

10

J.lA

0.5

V

OV ~ VIN ::; VIL (MAX.)

L-10
L-15

-

Input or I/O High Leakage Current

3.5V ~ VIN ::; Vee

-

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

VOH

Output High Voltage

IOH = MAX. Yin = VIL or VIH

2.4

-

-

-

12

mA

-2

mA

-30

-

-150

mA

-

75

130

mA

IIH

10L

Low Level Output Current

10H

High Level Output Current

los2

Output Short Circuit Current

Icc

Operating Power
Supply Current

IVIL = 0.5V

Vee=5V

VOUT = 0.5V TA= 25°C

I L-10/-15

VIH = 3.0V

V

ftogglo = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

5-6

1994 Data Book

~~~Latticem

Specifications GAL 16V8BI883

••••••
••••••
••••••

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER

tpd

TEST
COND'.
A

-10

-15

MIN. MAX.

MIN. MAX.

DESCRIPTION
Input or I/O to Combinational Output

2

10

1

UNITS

3

15

ns

tco

A

Clock to Output Delay

7

2

12

ns

tct"

-

Clock to Feedback Delay

-

7

-

12

ns

tsu

-

Setup Time, Input or Feedback before Clock!

10

-

12

-

ns

th

-

Hold Time, Input or Feedback after Clock!

0

-

0

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

58.8

-

41.6

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

58.8

-

41.6

-

MHz

A

Maximum Clock Frequency with
No Feedback

62.5

-

50

-

MHz

twh

-

Clock Pulse Duration, High

8

10

-

Clock Pulse Duration, Low

8

-

ns

twl

-

B

Input or I/O to Output Enabled

-

10

15

ns

B

OE to Output Enabled

-

10

-

15

ns

fmax 3

ten

tdis

10

ns

C

Input or I/O to Output Disabled

-

10

-

15

ns

C

OE to Output Disabled

-

10

-

15

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM-

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

Cva

I/O Capacitance

10

pF

Vee = 5.0V, V'IO = 2.0V

'Guaranteed but not 100% tested.

5-7

1994 Data Book

•

Specifications GAL 16VBAlBB3

••••••
......
......
ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING CONDo
CaseTemperature (Te) ............................... -55 to 125°C

Supply voltage Vee'" .................................... -0.5 to + 7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TVP!

VIL

Input Low Voltage

Vss-O.5

-

VIH

Input High Voltage

2.0

MAX.

UNITS

0.8

V

-

Vcc+1

V

IlL

Input or I/O Low Leakage Current

OV ::; VIN ::; VIL (MAX.)

-

-

-10

IlA

hH

Input or I/O High Leakage Current

VIH::; VIN ::; Vce

-

-

10

IlA

VOL

Output Low Voltage

10L = MAX. Yin = VIL or VIH

-

V

Output High Voltage

10H = MAX. Yin = VIL or VIH

2.4

-

0.5

VOH

-

V

12

mA

10L

-

Low Level Output Current

-

-2.0

mA

-30

-

-150

mA

-

75

130

mA

-

10H

High Level Output Current

los'

Output Short Circuit Current

Icc

Operating Power

VIL=0.5V

Supply Current

ftog910 = 25MHz Outputs Open

Vcc=5V

VOUT= 0.5V T A =25°C
L -20/-30

VIH= 3.0V

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25°C

5-8

1994 Data Book

Specifications GAL 16V8A1883

• •••••
••••••
••••••
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions
PARAMETER

TEST

~OND'.

·30

·20

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX.

tpd

A

Input or 1/0 to Combinational Output

3

20

3

30

ns

tco

A

Clock to Output Delay

2

15

2

20

ns

tcf2

-

Clock to Feedback Delay

-

15

-

20

ns

tsu

Setup Time, Input or Feedback before Clocki

15

-

25

-

ns

th

-

Hold Time, Input or Feedback after Clocki

0

-

0

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

33.3

-

22.2

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

33.3

-

22.2

-

MHz

A

Maximum Clock Frequency with
No Feedback

41.6

-

33.3

-

MHz

twh

-

Clock Pulse Duration, High

12

-

15

-

ns

twl

-

Clock Pulse Duration, Low

12

-

15

-

ns

ten

B

Input or 1/0 to Output Enabled

ns

18

-

30

OE to Output Enabled

-

20

B

25

ns

C

Input or 1/0 to Output Disabled

-

20

-

30

ns

C

OE to Output Disabled

-

18

-

25

ns

fmax3

tdis

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25

n C,

f

=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

CliO

1/0 Capacitance

10

pF

Vee = 5.0V, VIIO = 2.0V

'Guaranteed but not 100% tested.

5·9

1994 Data Book

•

I

~~~Lattice~

Specifications GAL 16V81883

••••••
••••••
••••••

SWITCHING WAVEFORMS
INPUT or
I/O FEEDBACK

ClK
REGISTERED
OUTPUT

Combinatorial Output

INPUT or
I/O FEEDBACK

---y

r

---f

I

~

COMBINA~ONAL

""-,

J

OUTPUT

Registered Output

~

""}~-

~

Input or I/O to Output Enable/Disable

c"

::-

OE to Output EnablelDisable

j::r

~1ooII-1----1Ifmax ~
(w/olb)

Clock Width

fmax with Feedback

5-10

1994 Data Book

Specifications GAL 16V81883

••••••
......
......
fmax DESCRIPTIONS
ClK

ClK

1OIII1.1----t8u -----'••1l0III.1---- tco-------'
fmax with External Feedback 1/(1:su+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
ClK

~I"---tcf-----.J.I

,...I------tp d-----~.I

fmax with Internal Feedback 1/(1:su+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax wlinternal feedback (tel 1lfmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

=

~tsu+t~·~I··
fmax with No Feedback
Note: fmax with no feedback may be less than l/(twh + twl). This
is to allow for a clock duty cycle of other than SO%.

SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels

+5V

GNDto 3.0V
3ns 10%-90%
1.SV
1.SV

Output Load

See Figure

3-state levels are measured O.SV from steady-state active level.

FROM OUTPUT (0/0)
UNDER TEST

TEST POINT

Output Load Conditions (see figure)
Test Condition
A
B
C

Active
Active
Active
Active

High
Low
High
Low

R1

R2

CL

390Q
=
390Q
=
390Q

7S0Q
7S0Q
7S0Q
7S0Q
7S0Q

SOpF
SOpF
SOpF
SpF
SpF

R2

c'L

'C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

S-11

1994 Data Book

.~
I

~~~Lattic~
••••••
......
••••••

Specifications GAL 16VBIBB3

GAL 16V8 ORDERING INFORMATION (MIL-STD-883 and SMD)
Ordering #
Tpc:I
(ns)

Tsu
(ns)

Teo
(ns)

Icc
(rnA)

10

10

7

130

20-Pin CERDIP

GAL16V8B-1 OLD/883

5962-8983904RA

130

20-Pin LCC

GAL16V8B-1 OLR/883

5962-89839042A

130

20-Pin CERDIP

GAL16V8B-15LD/883

5962-8983903RA

130

20-Pin LCC

GAL16V8B-15LRl883

5962-89839032A

130

20-Pin CERDIP

GAL16V8A-20LD/883

5962-8983902RA

130

20-Pin LCC

GAL16V8A-20LRl883

5962-89839022A

130

20-Pin CERDIP

GAL16V8A-30LD/883

5962-8983901 RA

15

12

ro

15

:Il

25

12

15

ro

MIL-STD-883

Package

SMD#

Note: Lattice recognizes the trend in military device procurement towards using SMD
compliant devices, as such, ordering by this number where it exists is recommended.

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL16V8B
GAL16V8A

~~me~

x X X

L

Speed (ns) - - - - - - - '

L

=Low Power

Power - - - - - - - - - - - - '

L-._ _ _ _

MIL Process /883

Package

=883 Process

D = CERDIP
R=LCC

5-12

1994 Data Book

GAL20VBIBB3
High Performance E2CMOS PLD
Generic Array Logic™

••••••

••••••
••••••

FUNCTIONAL BLOCK DIAGRAM

FEATURES

° HIGH PERFORMANCE E2CMOS" TECHNOLOGY
-10 ns Maximum Propagation Delay
- Fmax = 62.5 MHz
- 7 ns Maximum from Clock Input to Data Output
- TIL Compatible 12 mA Outputs
- UltraMOS'" Advanced CMOS Technology

1/0/0

° 50% REDUCTION IN POWER FROM BIPOLAR
-

f--l:l-r-lr- 1/0/0

75mA Typ Icc on Low Power Device

° E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «lOOms)
- 20 Year Data Retention

f--I>-, --I-r 1/0/0

f--h--f-- 1/0/0

° EIGHT OUTPUT LOGIC MACROCELLS
-

Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Also Emulates 24-pin PAL" Devices with Full Function/Fuse Map/Parametric Compatibility

10LIAC f---t>--r--- 1/0/0

10liAC f---t>.,L- 1/0/0

° PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-

100% Functional Testability

° APPLICATIONS INCLUDE:
-

KlllAC f---t>.,-L- 1/0/0

DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade

° ELECTRONIC SIGNATURE FOR IDENTIFICATION
L.__r----'---- 110E

DESCRIPTION

PIN CONFIGURATION

The GAL20V8/883 is a high performance FCMOS programmable logic devices processed in full compliance to MIL-STD883. This military grade device combines a high performance
CMOS process with Electrically Erasable (F) floating gate
technology to provide the highest speed/power performance
available in the 883 qualified PLD market.

CERDIP
LCC
24

~

The generic GAL architecture provides maximum design flexibility
by allowing the Output Logic Macrocell (OLMC) to be configured
by the user. The GAL20V8/883 is capable of emulating all
standard 24-pin PAL" devices with full function/fuse map/parametric compatibility.

,•

4

,

7

2

~ ~ -

0

28

GAL20V8

2.
2.
2.

Ne

,•

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice guarantees 100% field programmability and functionality
of all GAL products. Lattice also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.

'" 12

vOla
VO/Q
1fO/Q

GAL

1fO/Q

20V8

1/0/0
1/0/0

Ne

Top View

,.

I.
c

z

"

~

Vee

~

21

VO/O

IfOlQ

18

1/010

VO/Q

I.

18

VOIO

'IOIQ

VOIO

Ig - ~

VOIO

GND

12

13

I/OE

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders, The specifications and infonnation herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037

5-13

1994 Data Book

H~Lattice'M
••••••

Specifications GAL20V8BI883

••••••
••••••

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(1)

CaseTemperature (Tc) ............................... -55 to 125°C
Supply voltage (Vcc)
with Respect to Ground ..................... +4.50 to +5.50V

Supply voltage Vcc ....................................... -0.5 to +7V
Input voltage applied .......................... -2.5 to Vcc + 1.0V
Off-state output voltage applied .......... -2.5 to Vcc + 1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

VIL

Input Low Voltage

VIH

Input High Voltage

CONDITION

MIN.

TYP."

MAX.

UNITS

Vss-O.5

-

0.8

V

2.0

Vcc+1

V

-100

IlL

Input or I/O Low Leakage Current

OV s; VIN s; VIL (MAX.)

-

-

IIH

Input or I/O High Leakage Current

3.5VIH s; VIN S; Vcc

-

-

10

ItA
ItA

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

V

Output High Voltage

IOH = MAX. Yin = VIL or VIH

2.4

-

V

-

-

0.5

VOH

12

mA

-2.0

mA

-30

-

-150

mA

130

mA

10L

Low Level Output Current

10H

High Level Output Current

los'

Output Short Circuit Current

Icc

Operating Power

VIL=0.5V

Supply Current

ftoggle = 15MHz Outputs Open

Vcc=5V

VOUT= 0.5V T A=25°C
L-10

VIH= 3.0V

-

75

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 °C

5-14

1994 Data Book

......
••••••

Specifications GAL20V8BI883

......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions
PARAMETER TEST
COND'.

-10

DESCRIPTION

MIN. MAX.

UNITS

tpd

A

Input or I/O to Combinational Output

2

10

ns

tco

A

Clock to Output Delay

1

7

ns

tcf2

-

Clock to Feedback Delay

-

7

ns

tsu

-

Setup Time, Input or Feedback before Clocki

10

-

ns

th

-

Hold Time, Input or Feedback after Clocki

0

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

58.8

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)

58.8

-

MHz

A

Maximum Clock Frequency with
No Feedback

62.5

-

MHz

twh

-

Clock Pulse Duration, High

8

-

ns

twl

-

Clock Pulse Duration, Low

8

-

ns

ten

B

Input or I/O to Output Enabled

-

10

ns

B

DE to Output Enabled

-

10

ns

C

Input or I/O to Output Disabled

-

10

ns

C

DE to Output Disabled

-

10

ns

fmax 3

tdis

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

CliO

I/O Capacitance

10

pF

Vee = 5.0V, V,/O = 2.0V

'Guaranteed but not 100% tested.

5-15

1994 Data Book

•

......
••••••

Specifications GAL20V8A1883

••••••

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(1)

CaseTemperature (Te) ............................... -55 to 125°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

Supply voltage Vee ....................................... -0.5 to + 7V
Input voltage applied .......................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

PARAMETER

CONDITION

MIN.

TYP.'

MAX.

UNITS

VIL

Input Low Voltage

Vss-O.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

-

-

-10

I!A

ilL

Input or 1/0 Low Leakage Current

OV ~ VIN ~ VIL (MAX.)

Input or I/O High Leakage Current

VIH

-

10

I!A

VOL

Output Low Voltage

IOL = MAX. Yin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

10H = MAX. yin = VIL or VIH

2.4

-

-

V

Low Level Output Current

-

-

12

mA

-

-

-2.0

mA

-

-150

mA

130

mA

IIH

10L

~

VIN

~

Vcc

10H

High Level Output Current

los'

Output Short Circuit Current

Icc

Operating Power

VIL=0.5V

Supply Current

f'o99lo = 25MHz Outputs Open

Vee=5V

VouT=0.5V T A=25°C

VIH= 3.0V

L -15/-20

-30

-

75

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25°C

5-16

1994 Data Book

......
......
••••••

Specifications GAL20V8A1883

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER

TEST

~OND'.

-15

DESCRIPTION

-20
UNITS

MIN. MAX MIN. MAX.

tpd

A

Input or 1/0 to Combinational Output

3

15

3

20

ns

12

2

15

ns

tco

A

Clock to Output Delay

2

tcf2

-

Clock to Feedback Delay

-

12

-

15

ns

tsu

-

Setup Time, Input or Feedback before Clock

12

-

15

ns

th

-

Hold Time, Input or Feedback after Clock

0

-

0

-

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

41.6

-

33.3

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

41.6

-

33.3

-

MHz

A

Maximum Clock Frequency with
No Feedback

50

-

41.6

-

MHz

twh

-

Clock Pulse Duration, High

10

-

12

-

ns

twl

-

Clock Pulse Duration, Low

10

-

12

-

ns

ten

B

Input or 1/0 to Output Enabled

-

15

-

20

ns

B

OE to Output Enabled

-

15

-

18

ns

C

Input or 1/0 to Output Disabled

-

15

-

20

ns

OE to Output Disabled

-

15

-

18

ns

fmax3

tdis

C

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.

CAPACITANCE (T A

=25°C, f =1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM"

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

Vee = 5.0V, V, = 2.0V

CliO

1/0 Capacitance

10

pF

Vee = 5.0V, Vito = 2.0V

'Guaranteed but not 100% tested.

5-17

1994 Data Book

•

Specifications GAL20VBIBB3

••••••
••••••
••••••
SWITCHING WAVEFORMS

INPUT or
1/0 FEEDBACK

ClK

REGISTERED
OUTPUT

Registered Output

Combinatorial Output

INPUT or
1/0 FEEDBACK

-----l~---r

. ---- .-

~--------1~tdiSJ J~en~

COMBINATIONAL
OUTPUT

. _

Input or 1/0 to Output Enable/Disable

C~

OE to Output Enable/Disable

~t:1-

~1 '"

26

I/OIQ

2.

I/O/Q

I/OIQ

UO/Q

1

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V1 0 devices.

7

1

9

111

Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL® products.

Top View
12

16

-

I/OIQ

2.

UO/Q

Ne

I/OIQ

21

I/O/Q

I/OIQ

GAL22V10

Ne

Vee

,.

18

I/OIQ

I/OIQ

I/O/Q

I/OIQ

"cz "z ~ ~
"

I/OIQ
I/OIQ

GND
Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and infonnation herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800·FASTGAL; FAX (503) 681·3037

5-21

1994 Data Book

•

Specifications GAL22V10B/883

......
.....•

RECOMMENDED OPERATING CONDo

ABSOLUTE MAXIMUM RATINGS(l)

Case Temperature (Te) .............................. -55 to 125°C

Supply voltage Vee ........................................ -0.5 to + 7V
Input voltage applied ........................... -2.5 to Vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................ -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

Supply Voltage (Vee)
with Respect to Ground ..................... +4.50 to +5.50V

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL

CONDITION

PARAMETER

MIN.

TYP.'

MAX.

UNITS

VIL

Input Low Voltage

Vss - 0.5

-

0.8

V

VIH

Input High Voltage

2.0

-

Vcc+1

V

IIL'

Input or I/O Low Leakage Current

OV ~ VIN ~ VIL (MAX.)

-

-

-100

IlA

Input or I/O High Leakage Current

3.5V ~ VIN

-

-

10

Il A

VOL

Output Low Voltage

IOL= MAX. Vin = VIL or VIH

-

-

0.5

V

VOH

Output High Voltage

IOH= MAX. Vin = VIL or VIH

2.4

-

-

V

IIH

~

Vee

10L

Low Level Output Current

-

-

12

mA

10H

High Level Output Current

-

-

-2.0

mA

los2

Output Short Circuit Current

-

-135

mA

Icc

Operating Power

150

mA

Supply Current

I VIL = 0.5V

Vee=5V

VOUT = 0.5V TA = 25°C

IL -15/-20/-25/-30

VIH = 3.0V

-50

-

90

f,ogglo = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C

5-22

1994 Data Book

Specifications GAL22V10BI883

......
......
AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

PARAMETER

TEST
CON D.'

tpd

-15

DESCRIPTION

-20

-25

-30

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

A

Input or I/O to Combinatorial Output

-

UNITS

15

-

20

-

25

-

30

ns

teo

A

Clock to Output Delay

-

8

-

15

-

20

-

20

ns

tcF

-

Clock to Feedback Delay

-

8

-

15

-

20

-

20

ns

tsu

-

Setup Time, Input or Feedback before Clock!

12

-

17

-

20

-

25

-

ns

th

-

Hold Time, Input or Feedback after Clock!

0

-

0

-

0

-

0

-

ns

A

Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)

50

-

31.2

-

25

-

22

-

MHz

A

Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)

50

-

31.2

-

25

-

22

-

MHz

A

Maximum Clock Frequency with
No Feedback

62.5

-

33

-

33

-

25

-

MHz

twh

-

Clock Pulse Duration, High

8

-

15

-

15

-

20

-

ns

twl

-

Clock Pulse Duration, Low

8

-

15

-

15

-

20

-

ns

B

Input or I/O to Output Enabled

-

15

-

20

-

25

-

25

fmax 3

ten

..

-~

...

-

""-

---

ns
, - -

tdis

C

Input or I/O to Output Disabled

-

15

-

20

-

25

-

25

ns

tar

A

Input or I/O to Asynchronous Reset of Register

-

20

-

25

-

30

-

30

ns

tarw

-

Asynchronous Reset Pulse Duration

15

-

20

-

25

-

30

-

ns

tarr

-

Asynchronous Reset to Clock Recovery Time

15

-

20

-

25

-

30

-

ns

tspr

-

Synchronous Preset to Clock Recovery Time

12

-

17

-

20

--

25

-

ns

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL

PARAMETER

MAXIMUM'

UNITS

TEST CONDITIONS

C,

Input Capacitance

10

pF

CliO

I/O Capacitance

10

pF

= 5.0V, V, = 2.0V
Vee = 5.0V, Vila =2.0V
Vee

'Guaranteed but not 100% tested.

5-23

1994 Data Book

Specifications GAL22V101883

••••••
••••••
••••••
SWITCHING WAVEFORMS
INPUT or

VO FEEDBACK

COMBINATORIAL
OUTPUT

\\\\\\\\\l::;:UT

INPUT or
I/O FEEDBACK

\\\\\\\\\\\\\\\1==

ClK
REGISTERED
OUTPUT

Combinatorial Output

Registered Output
INPUT or
VO FEEDBACK

OUTPUT
ClK

Input or VO to Output EnablelDisable
REGISTERED
FEEDBACK

ax

t_cf~_ts_u_ _ __

____

fmax with Feedback

r'whT':ir---{-"'-I---1/fmax~
(w/o !cIlk)

Clock Width

INPUT or
110 FEEDBACK
DRIVINGAR

INPUT or
110 FEEDBACK
DRIVINGSP
ClK

ClK

REGISTERED
OUTPUT

REGISTERED
OUTPUT

Synchronous Preset

Asynchronous Reset

5-24

1994 Data Book

~HLatticem
......

Specifications GAL22V101883

••••••
••••••

fmax DESCRIPTIONS
ClK

foII
. .I - - - -

ClK

tsu ----1.~I....I - - - - tco----'
"'~~~tcf~~~~1
r
I - - - - - - I p d -----~~I

fmax with External Feedback 1/ctsu+tco)

foII
..

Note: fmax with external feedback is calculated from measured tsu and tco.

fmax with Internal Feedback 1/ctsu+tcf)

ClK

Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.

~i~u+i;'=-'I
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.

SWITCHING TEST CONDITIONS
Input Pulse Levels

+5V

GNDt03.0V

Input Rise and Fall Times

3ns 10%-90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure
FROM OUTPUT (O/Q)
UNDER TEST

3-state levels are measured 0.5V from steady-state active
level.

C'
L

Output Load Conditions (see figure)
Test Condition
A
B

C

Rl

TEST POINT

R2

CL

3900

7500

50pF

Active High

00

7500

50pF

Active Low

3900

7500

50pF

Active High

00

7500

5pF

Active Low

3900

7500

5pF

'C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

5-25

1994 Data Book

•

~~~Latticem
••••••
......
••••••

Specifications GAL22V101883

GAL22V10 ORDERING INFORMATION (MIL-STD-883 and SMD)
Ordering #
Tpd
(ns)

Tsu
(ns)

Tco
(ns)

15

12

8

20

17

15

Icc
(mA)

Package

MIL-STD-883

SMD#

150

24-Pin CERDIP

GAL22V1 OB-15LD/883

5962-8984103LA

150

28-Pin LCC

GAL22V1 OB-15LRl883

5962-89841033A

150

24-Pin CERDIP

GAL22V10B-20LD/883

5962-8984102LA

150

28-PinLCC

GAL22V10B-20LRl883

5962-89841023A

25

20

20

150

24-Pin CERDIP

GAL22V10B-25LD/883

5962-8984104LA

:D

25

20

150

24-Pin CERDIP

GAL22V10B-30LD/883

5962-8984101 LA

Note: Lattice recognizes the trend in military device procurement towards using SMD
compliant devices, as such, ordering by this number where it exists is recommended.

PART NUMBER DESCRIPTION
XXXXXXXX - XX

GAL22V10B Devloe Nome

~

x

XX

L

Speed (ns) - - - - - - - '

L = Low Power Power - - - - - - - - - - '

5-26

MIL Process /883 = 883 Process

' - - - - - - - Package

D = CERDIP
R=LCC

1994 Data Book

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Lattice Design Tool Strategy ................................................................. 6-1
System Design Process ....................................................................... 6-3
pLSI and ispLSI Design Flow .. .............................................................. 6-5
Lattice Development Tool Datasheets
pDS Software ....................................................................................... 6-9
pDS+ ABEL Software ........................................................................... 6-15
pDS+ Viewlogic Software ..................................................................... 6-19
pDS+ LOG/iC Software ........................................................................ 6-25
isp Starter Kit ........................................................................................ 6-31
ispCODE .............................................................................................. 6-33
isp Engineering Kit - Model 100 ........................................................... 6-39
isp Engineering Kit - Model 200 ........................................................... 6-43
ispDOWNLOAD Cable ......................................................................... 6-49

pLSI and ispLSI Design Tool Selector Guide ........................................ 6-51
GAL Development Support ................................................................... 6-55
ispGDS Compiler Support .................................................................... 6-57
Section 7: Quality and Reliability
Section 8: General Information

6-i

•

I

6-ii

Lattice Design Tool
Strategy
Introduction
The Lattice design tool strategy for the pLSI and ispLSI
families is to support a wide range of design environments.
Lattice provides both a proprietary PC-based solution
(pDS®) as well as third-party compatible CAE tools (pDS+TM
Fitters) that run on PC and Sun workstation platforms.
The Lattice pDS (pLSI and ispLSI Development System)
software provides a comprehensive, high-performance,
low-cost package for logic development. Developed and
supported by Lattice, pDS provides an easy-to-use Windows-based graphical interface using a mouse and
pull-down menus. Design entry includes Boolean equationsand macros. Forsimulation, timing tables are included
as a standard offering. Additionally, pDS interfaces with
Viewlogic's Viewsim simulation package for full functional
and timing simulation. pDS software generates industry
standard JEDEC programming files and supports direct
download into ispLSI devices.

Lattice's pDS+ (pDS Plus) solution supports multiple thirdparty CAE tools, providing designers with the capability to
design in familiar CAE environments. These third-party
CAE tools offer schematic capture, hardware description
language (such as VHDL), state machine language, Boolean
equation, and macro design entry as well as functional and
timing simulators for design verification.
Lattice's pDS and pDS+ solutions give designers powerful,
easy to use, cost-effective design tools to meet their
development needs. Each third-party vendor must adhere
to strict quality and certification requirements before becoming qualified, thus ensuring superior support. Additional
support for popular third-party CAE tools is scheduled.
Contact your local Lattice Sales Representative for
availability.

•

Figure 1. pDS and pDS+ Design Flows

I

Design Idea

pDS

I

Third-Party
Environments

pDS
Design [
Entry

I

Boolean

~

I

Viewlogic
Workview

I
"

Device
Fitting

II

Logic Partitioning
Auto Place & Route

1

Design [
Verification

I

~

pDS+

Viewlogic

ISDATA
LOGIiC

Data 1/0
ABEL

I II

1

pDS+

ABEL

II

pDS+

LOGIiC

I

I

IIIParty
Other Third
Vendors

pDS+

I

Other

,

1

Viewlogic Viewsim
Functional and Timing Simulator

6-1

Other Third
Party Simulator

I

Lattice Design Tool Strategy
Lattice Design Flow
There are three steps in the Lattice pLSI and ispLSI design
flow: design entry, device fitting (logic partitioning, place
and route), and design verification. (See the pDS and
pDS+ Design Flow). This section outlines the design flow
of the pDS and pDS+ solutions.

Lattice pDS
Lattice's pDS solution is a comprehensive, self-contained
design solution which operates on a PC under Microsoft
Windows. pDS uses familiar ABEL-like Boolean equation
and macro design entry, and provides manual partitioning,
high speed automatic place and route, and simulation
timing tables for design verification. Viewlogic's Viewsim
simulation package is compatible with pDS for functional
and timing simulation.
After the development work has been completed, the
design is ready to be programmed into a device. For thirdparty programming support, the pDS package generates a
JEDEC fusemap. Alternatively, the ispLSI devices can be
programmed directly from the PC or Sun workstation with
the Lattice isp Engineering Kit.
The pDS development systems are ideal fordesigners who
desire a cost-effective, user friendly approach to pLSI and
ispLSI deSign.

Lattice pDS+
The pDS+ solution combines third-party CAE tools for
design entry and verification with the Lattice pDS+ Fitter for
device fitting to offer a powerful and complete development
solution. Initial Fitter products include the pDS+ ABEL
Fitter, pDS+ Viewlogic Fitter, and pDS+ LOG/iC Fitter
which interface with their respective third party design
tools.
The design entry step is typically performed with schematic
capture, Boolean equations, state machines, truth tables
or a Hardware Description Language (HDL). Once design
entry is complete, the design is ready to be implemented
into a Lattice pLSI or ispLSI device.
The Lattice pDS+ Fitter uses architecture-specific algorithms to synthesize a logic description into a pLSI or
ispLSI device. Steps in the device fitting process include
logic optimization and minimization, automatic logic partitioning, and automatic place and route.
pDS+ also supports design verification. Design verification
options include both functional and timing simulation.
Various combinations of graphical and text-based functional and timing simulators are supported by third-party
CAE vendors.
Following design verification, the Lattice pDS+ Fitter generates a JEDEC fusemap for device programming. The
design can be programmed into a pLSI device using thirdparty programmers. In addition, the ispLSI devices can be
programmed directly from the PC or Sun workstation
system using Lattice's isp Engineering Kit, or from dedicated
logic designed into the end-system.

6-2

System Design
Process
Introduction

Partitioning

Conceptually, system definition is the first step in the
design process. This involves visualizing the PLD's interaction with the rest of the electronic system and defining a
general flow diagram to determine the design's basic
sequential behavior. This organizational flow, used to
integrate an entire subsystem into high density devices, is
described in the following topics and shown in figure 1.

Figure 1. System Design Flow

After completing the conceptual design, the designer
partitions the system into modules or functional blocks.
These blocks can be a few components or multiple circuit
boards with numerous components. The designer organizes these functional blocks to match the capabilities of
the devices being targeted, for example, the number of I/O
pins, flip-flops and gates needed. The user should also
consider the frequency at which the targeted device must
operate, the number of clocks required, and the timing
relationships of signals (AC specifications).

Define System

Partition into Functional Blocks

Specify Components

Design Logic into Targeted Device

Test and Debug Device

PCB Layout

Specifying Components
After the partitioning is defined, the designer chooses the
components which will be used to implement the desired
functions. The design should meetthe system specifications
using the least number of components in order to keep the
system cost as low as possible while keeping the system
reliability as high as possible.
System specifications calling for low weight, low power and
reduced size also drive designers to higher levels of logic
integration. These added requirements can adversely affect
the design schedule and project completion. The pLSI and
ispLSI high-density devices can meet such design
requirements while delivering excellent performance. The
pLSI and ispLSI family of high-speed, high-density PLDs
supported by easy-to-use effective software for fast design
implementation and verification.

Design Entry and Optimization

Test and Debug System

Deliver System

After the functional partitioning and component specifications are completed, the logic necessary to implement the
functions is defined block by block. The logiC may include
standard TTL functions, CMOS logic functions, orfunctions
from a library, such as the Lattice Macro Library. The
implementation of logic into a high density device is optimized
for the targeted device by the deSign software. The
partitioning also affects the optimization. Optimization can
be for speed, utilization or a combination of both.
Logic entry for a Lattice high density device is done with the
pLSI/ispLSI Development System or with any of Lattice's
pDS+ Fitter products (pDS+ Viewlogic, pDS+ ABEL,
pDS+ LOG/iC, etc.). The pDS software utilizes the Graphical User Interface (GUI) of Microsoft's Windows™ to
provide a complete design flow from logic entry to program-

6-3

•

I

System Design Process
ming pLSllispLSI devices within hours. The pDS+ ABEL
software supports textual design entry using a Hardware
Description Language (HDL). Standard CAE schematic
design entry is supported by the pDS+ Viewlogic software.
pDS+ LOGliC supports Boolean, truth table and state
machine entry.

To assist system testability, the ispLSI devices offer preload
and verification features. These features allow register
contents to be verified without using logic analyzers or
other debugging tools.

Printed Circuit Board Layout
Once the logic has been verified, the Printed Circuit Board
(PCB) is laid out and manufactured. Since the logic may be
changed during design, this phase of the system design is
usually executed after the logic has been validated. It is
recommended that board design and layout be done after
verifying designs using pLSI and ispLSI parts.

Test and Debug
When designing a system, or a portion of a system, it is
easier to test and debug pieces or modules rather than the
entire system. In this manner, the designer can confirm
module designs, or functional blocks, and find problems
earlier in the design cycle.

System Test and Debug

Logic can be verified by either timing simulation or actual
testing of the programmed device. Simulation can be
accomplished using the Viewlogic Viewsim logic simulator
(available from Lattice). Design errors detected by software simulation can be corrected by the designer before
the printed circuit board is laid out and manufactured,
which saves time and reduces cost. Board and system
level simulation can be accomplished through behavioral
simulation using Logic Modeling Corporation's models.

System test and debug is the final stage of the design
process. The logic and the PCB are tested as a system and
minor enhancements or bug fixes are implemented. Because of the flexibility of the pLSI and ispLSI devices, minor
changes can be made without affecting the layout of the
PCB or the pinout of the device.

Reprogrammable devices allow the designerto test, debug,
and modify logic right on the p.c. board. pLSI and ispLSI
devices can be reprogrammed multiple times. This
reprogrammability further assists the designers by allowing them to temporarily program the devices with diagnostic
and design verification logic.
The designer should always attempt to design logic with
testability in mind. Testability means different things to
different designers. Key guidelines to be aware of are:

o

Large counters should be segmented for quick and
easy testing.

o

Logic should be designed for controllability and
observability.

o

There should be no floating nets.

o

All nets should be at a known state or are able to be set
or reset.

6-4

pLSI and ispLSI

Design Flow
Introduction
Once the system design has been organized into functional components, and the logic functions which need to
be incorporated in the selected components defined, the
logic design phase begins. The general design flow is
shown in figure 1. A pLSI or ispLSI design may be
implemented from a number of design environments:
including pLSI/ispLSI Development System (pDS),
pDS+ ABEL, pDS+ Viewlogic and pDS+ LOG/iC

Figure 1. General Design Flow

design implementations. ABEL also accepts VHDL aas a
high level language input. The Lattice-ABEL interface
allows many existing PLD designs to be easily integrated
and converted into a pLSI or ispLSI devices.
For standard CAE schematic designs, the pDS+Viewlogic
software provides support for graphical and hierarchical
logic implementations using the Lattice library of primitives
and macros. The Viewlogic interface also allows easy
integration of system or user-created functions into a
hierarchical schematic using a top-down or bottom-up
design methodology. Additonally, Viewsynthesis offers
VHDL capability to round out the design entry process.

Design Verification
Verification using the pDS software is accomplished in two
steps after logic has been placed. First, each cell may be
individually verified to ensure that the minimized logic will
fit into the GLB architecture. After all GLB and I/O cells are
incrementally checked, the entire design is then verified to
ensure that all nets have proper sources and destinations .

Simulation

These design environments offer various levels of design
implementation from logic entry through programming the
device. They support a variety of user interfaces and entry
methods including: MS WindowsGUI, Data I/O ABEL HDL
or VHDL, Viewlogic ViewdrawNiewsynthesis and the
ISDATA LOG/iC Design System. The design flows using
these development software systems are shown in figures
2, 2a, 2b and 2c.

Design Entry
The pDS software allows the user to manually partition the
logic to control design fit and performance. Using the MS
Windows environment, logic functions are placed into
Generic Logic Blocks (GLBs) and I/O Cells. This can be
done by using the Edit, Cut, Copy, and Paste functions to
enter Boolean equations and/or pre-defined functions from
the Lattice Macro or user libraries.
In addition to Boolean design entry, the pDS+ABEL HDL
format allows high-level descriptions of counters, adders,
comparators, etc. The ABEL language also supports state
machines, truth tables and case constructs for behavioral

Because the advanced pDS+ tools perform automatic
partitioning, design verification is done at a higher-level
(pre-partitioned). In the ABEL environment, the Compile
(ahdI2pla) function performs the syntax and design rule
checks. After the Compile phase, the Optimize (plaopt)
function (optionally) minimizes the design.
In the pDS+Viewlogic environment, pre-partitioned design
verification is performed by the Design Analyzer which
ensures the logic conforms to the Lattice design rules.

Partitioning
Partitioning using the pDS software is done by the user as
part ofthe design entry process. The advanced pDS+ABEL,
pDS+ Viewlogic and pDS+ LOG/iC tools incorporate
Lattice's automatic partitioner which accepts converted
data from designs entered in ABEL, Viewlogic and LOGJiC
respectively. Lattice specific attributes for design entry are
available to guide the partitioner in order to optimize usage
of device features and performance.

Place and Route
All Lattice design tools offer automatic place and route.
This entails placement of GLB and 10C logic and then
routing (or interconnecting) the source signals to their

6-5

•

I

pLSI and ispLSI Design Flow
destinations. In the pLSI and ispLSI devices, the Global
Routing Pool (GRP) provides fast interconnects from
external inputs and GLB feedbacks to the GLB inputs. The
Output Routing Pool (ORP) provides flexible interconnects
from GLB outputs to external pins. To take advantage of
the architectu ral features, Lattice offers two different routers,
Fast and Strong. The Fast router utilizes quick algorithms
to route most designs. The more comprehensive Strong
router is used to route more complex designs.

Figure 2. pDS Design Flow
Design Entry

+

Cell Verify

+

Design Verify

Post-route Simulation

Place & Route

I

After place and route, a netlist for full timing and function
simulation may be passed to the Viewsim simulator.
Viewsim supports simulation using both textual and
graphical input and interfaces. Board and system level
simulation models are also available from Logic Modeling
Corporation.

Viewsim Simulation

Fusemap Generation

Download to ispLSI
or
Download to Programmer
for pLSI and ispLSI

Documentation
Report files, containing partitioned equations and pin-out
information, may be generated for routed or un-routed
designs. The pDS software can also generate reports with
post-route maximum timing delays. In addition, the design
can be exported in an Electronic Design Interchange
Format (EDIF). This supports design interfaces to standard
third-party CAE tools.

Figure 2a. pDS+ ABEL Design Flow
Design Entry

I

+

Compile to PLA

Device Programming
Programming information is generated on a routed design
by the FuseMap Generator for a specific pLSI and ispLSI
device. It is an ASCII file written in the JEDEC format.
Using the pDS+ ABEL software, the user may optionally
append test vectors onto the JEDEC file. This allows postprogramming functional test on the actual device.
Two programming methods are used to program the pLSI
and ispLSI devices. The first method uses the Device
Programming Mode for both types of devices.
This
method facilitates device programming support from thirdparty vendors. The second method uses the Lattice
In-System Programming Mode and applies to the ispLSI
family of devices.
Both methods of device programming allow the user to
program and read back the fuesmap from the programmed
device for verification (if the security cell has not been set).

6-6

ABEL Simulation

I

Viewsim Simulation

I

Partitioning
Place and Route

I

I
Fusemap Generation

+

Download to ispLSI
or
Download to Programmer
for pLSI and ispLSI

+

Functional Test

I

pLSI and ispLSI Design Flow
Figure 2b. pDS+ Viewlogic Design Flow
Design Entry

+

Design Analysis

+

Partitioning
Place and Route

I

Viewsim Simulation

I

Fusemap Generation

+

Download to ispLSI
or
Download to Programmer
for pLSI and ispLSI

Figure 2c. pDS+ LOG/iC Design Flow

•
Viewsim Simulation

Download to ispLSI
or
Download to Programmer
for pLSI and ispLSI

Functional Test

6-7

Notes

6-8

pD~

••••••
••••••

••••••

Features

Introduction

• pLSI@ and ispLSI ,. Development System
- Supports pLSI and ispLSI1 000,2000 and 3000
Families
• Design Entry with Easy-to-Use WindowsTM
Environment
-

ABEL-Like Boolean Equation Entry
Logic Macro Entry with over 275 "TTL-Like"
Macros
Manual Device Partitioning Ensures Tight
Control of Performance and Utilization

-

Efficient Design Optimization &
Minimization
"Hands Free" Automatic Place and Route
Fast Route Option for Quick Turnaround
Strong Route Option for Comprehensive and
Optimized Routing
Predictable Performance

• Complete DeSign Verification
-

Functional and Timing Simulation Option
Using Viewsim

• Industry Standard JEDEC Programming File
Generation
- Standard JEDEC Device Fusemap
• Optional isp Engineering Kit (Model 100)*
-

The pDS software is a comprehensive design package
for the Lattice pLSI and ispLSI device families giving full
design entry and device implementation capabilities underthe Windows deSign environment. The pDS software
provides the best solution for high performance designs
which require direct control of the logic implementation.
It offers designers complete control over the performance and utilization of the device. The pDS software
allows designers to quickly move from concept to a
programmed logic device.
The pDS software also offers a simulation option for full
functional and timing simulation of designs using
Viewlogic's Viewsim software.

• Fast Design Compilation
-

Software

PC Compatible Programmer for Engineering
Use
Supports Entire ispLSI Device Family
Download to Programmer Circuit Board

pDS Software
Using the pDS software, designs can be defined completely using simple Boolean equations and "TTL-like"
logic macros. Automated design capabilities shorten
design cycles allowing designers to explore several design solutions before deciding on the one that provides
the best solution.
Designs can be entered in two ways: either through the
integrated edit windows within the pDS software, or by
using a standard ASCII text editor to create a design file
that can be importe~ into the pDS environment. The
Lattice Place and Route software automatically places
the logic and routes the interconnections. The Fusemap
program generates a fuse file which can then be downloaded into a device programmer or directly to a Lattice
ispLSI device (see figure 1).
Figure 1. pDS Design Flow

• Runs on 386/486/Pentium IBM-Compatible PC
Under Windows™ Environment

Simulation

'Not intended for production programming
Device Programming
Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681·0118; 1·800·LATTICE; FAX (503) 681-3037

6-9

1994 Data Book

•

I

~~~Lattice

pDS Software

••••••
••••••
••••••

Design Entry
pDS software offers an easy to use interface as shown in
figure 2. Designers can quickly enter the design into

GLBs and 1/0 cells through this interface. An example of
an edit window is shown in figure 3. Tables 1, 2 and 3
provide a condensed list of the different operations which
are supported in the pDS software.

Figure 2. User Interface
=PlSI Oeuelopment System
File Design Cell Macro Library

D

Message

Zoom

CD

I I I I I I I I I I I I I I I I I

-AD

I D? I D61 D51 D41 D31 D21 DI I DO I
C?

I--

Al

C6

'c5
r--

A2

:--

C4

A3

:-A4
!--

I-C3
r-C2
I--

'A7

reo

'--

A5

BCD

r-

I-

CI

AS

~

r!.

B

r-

,---

~

aa

!::!elp

~

I BO I HI I B2 I B3 I B4 I B5 I Bb I H? I~
I I I I I I I I I I I I I I I I I o::::r::IJ
LJ

+

L+

L·J_&

Messages
Edit !;Iear
r+ielcome To pLSI Development System!

"'1

..
+

Figure 3. Sample Edit Window Illustrating Boolean
Equations and Macros

Table 1. Keywords

SIGTYPE CO_P OUT;
SIGTYPE Cl

The following summarizes the pDS software keywords,
operators and dot extensions used.

Keyword

REG OUT;

Description

CONSTANT

Assigns a value to a signal

SET

Assigns a label to a group of signals

SIGTYPE

Assigns specific attributes to a GLB
output

CO;

CRIT

Used for the 4 product term bypass

Cl.CLK = SYSCLK;

XPIN

Identifies external signal in the 1/0
cell

LOCK

Locks an 1/0 cell to a pin

XOR4 (par, Dl, D2, D3, D4)
EQUATIONS
CO_P

CO_O & CO_l # CO_2;

Cl

Cl$$

END;

EQUATIONS Beginning of the Boolean description
of the logic in a GLB

/I

6-10

The text that follows is a comment

1994 Data Book

~HLattice
••••••
......
••••••

pDS Software
Logic Optimization

Table 2. Operators
Operator

Description

=

Assignment

!

Inversion

$$

Hardware exclusive OR

&

AND

#

OR

$

Exclusive OR

!$

Exclusive NOR

The pDS software provides extensive design rule checking during the optimization and fitting process. After the
design has been checked, the software initiates logic
minimization to reduce the number of product terms
needed.

Automatic Place and Route
The pDS software provides an automatic place and route
routine which eliminates the need for manual routing and
provides a quicker design cycle time. The router automatically generates pinouts based on an optimal design
implementation or it can use a user defined pinout. There
are two routing options:

Table 3. Dot Extensions
Extension

Description

.D

Identifies the signal as the D input

.Q

Identifies the signal as the Q output

.RE

Identifies the product term reset
signal for the GlB

.ClK

Identifies the system clock for the
GlB

.PTClK

Identifies the product term clock for
the GlB

.OE

Identifies the output enable signal
for the 1/0 cells within the
megablock

-

The Fast Route option performs quick place and route to
reach the debugging stage sooner. The Strong Route
option performs a comprehensive routing search to maximize device resource utilization and ensures efficient
design implementation. With the Strong Route option,
small deSign changes can generally be performed without expensive PC board rework.
Incremental place-and-route capability allows last-minute
logic updates to be implemented without design pin-out
changes.

The pDS software offers an extensive selection (over
275) of TTL-like macros. These macros enable the
design engineer to use familiar pre-defined functions to
build a design. Table 4 shows a summary of the available
macros in the pDS software.
Table 4. Macro Summary
Macro Type
AND/NAND
ORINOR
XORlXNOR

II0s
Flip-Flops
Arithmetic
Counters
Shift Registers
MUX/DEMUX
Miscellaneous

Quantity

29
24
11
31
25
28
66

15
34
25

Fast Route
Strong Route

Post Route Simulation
Complete post route design verification can be peformed
using the optional Viewsim timing simulator.

Fusemap Generation
The lattice Fusemap generation module outputs the file
containing the fuse pattern used to implement the logic in
the device. A security feature offers protection of proprietary deSigns from unauthorized duplication.

Device Programming
The pDS software supports two ways of programming
devices. The designer can program the parts themselves through the In-System Programming option or
download the file to a third-party device programmer
(shown in table 5).

6-11

1994 Data Book

•

~~~Lattice

pDS Software

••••••
••••••
••••••

In-System Programming allows the devices to be programmed without removing them from the system board.
A download cable is used to transfer the bit stream and
programming instructions (called ispSTREAM) from the
pDS software to the target system.
Table 5. Programming Support
Programmer Vendor

-

Kit Contains Programming Module (Base Unit),
Download Cable, AlC Adapter, Socket Adapters
and
- One ispLSI Device Sample Included per Adapter
For more information on specific devices, please refer to
the isp Engineering Kit data sheet.

Model
Pilot-U84

Advin Systems

isp Engineering Kit Ordering Information

Pilot-U40

Product Code

Description

pDS4102-PM

Model 100 Universal Programming
Module

Pilot-GUGCE
BP Microsystems

Technical Support Assistance

PLD-1128
CP-1128
2900

Data 1/0

Lattice Hotline:

1-408-428-6414 (International)

email:

1-408-980-9814
applications@lattice.com

Warranty/Update Service

Allpro 40
Logical Devices
Allpro 88

• 90 Day Warranty on Disk Media

Sprint Expert

• One year of Maintenance Support Included

System 3000

• Annual Maintenance Agreement Available

ZL30/A

• 90 Day Warranty on isp Engineering Kit

Stag
System General

1-800-LATTICE (Domestic)

Lattice BBS:

3900
Unisite 40148

SMS Micro Systems

Lattice Hotline:

TURPRO-1

High pin-count socket adapters are available from Emulation Technology, EDI Corporation and PROCON.

System Requirements
-

386/486/Pentium IBM Compatible PC

-

MS DOS Version 3.3 or Later
MS Windows Version 3.1 or Later
4 MB RAM and 10MB Hard Disk Space
Parallel Printer Port for Software Key
VGA or Higher Resolution Display
Mouse (Windows Compatible)

6-12

1994 Data Book

H~Lattice
••••••

pDS Software

••••••
••••••

pDS Ordering Information
Product Code

Description

pDS1101-STD/PC1

pLSI and ispLSI Development System supports 1000 and 2000 Family devices

pDS1101-3UP/PC1

pLSI and ispLSI Development System Upgrade to add support fo 3000 Family devices

pDS11 01-ULT/PC1

pLSI and ispLSI Development System supports 1000, 2000 and 3000 Family devices

pDS1101 M-STD/PC1

pDS11 01-STD/PC1 Annual Maintenance Renewal

pDS1101M-ULT/PC1

pDS1101-ULT/PC1 Annual Maintenance Renewal

pDS3302-PC1

Viewlogic Viewsim Timing & Functional Simulator

pDS1102-PC1

Viewlogic Viewsim Simulation Libraries and Interface Files

•

6-13

1994 Data Book

~~~Lattice

Notes

••••••
••••••
••••••

6-14

1994 Data Book

~~~Lattice~
••••••

pDS+™ABEL
Software

••••••
••••••

Features

Introduction

• pLSl18 and ispLS"" Development System
-Supports All pLSI and ispLSI 1000, 2000 and
3000 Families

The pDS+ ABEL software from Lattice Semiconductor
offers a powerful solution to fit high-density logic designs
into Lattice's pLSI and ispLSI devices.

• Design Entry Using ABEL and VHDL-DirectTM
- Design Verification Using ABEL Functional
Simulation
- Lattice Fitter for Design Synthesis
- Optional Timing Simulation Using Viewlogic
Viewsim

Design entry is made simple by using ABEL software from
Data I/O together with the pDS+ ABEL Fitter for design
implementation. The Lattice pDS+ ABEL software offers
high-level, device independent design entry with efficient
logic compilation, delivering unprecedented performance
for the most complex designs.

• Supports Viewlogic ViewPLD
• Integrated Development Environment for MixedMode Design Entry
- ABEL Hardware Description Language (AHDL)
or VHDL Syntax Including Boolean Equations,
Truth Tables and State Machines
- Graphical Menu Driven User Interface
• Lattice pDS+ ABEL Fitter
- Automatic Device Fitter Ensures High
Utilization and Performance
- Efficient Design Optimization & Minimization
- Automatic Partitioning with High Utilization
- "Hands Free" Automatic Place and Route
- Fast Route Option for Quick Turnaround
- Strong Route Option for Comprehensive and
Optimized Routing
- Predictable Performance
• Industry Standard Programming File Generation
- Standard JEDEC Device Fusemap
- Standard JEDEC Device Test Vectors
• Optional isp Engineering Kit*
- Programmer for Engineering Use
- Model 100 for PC
- Model 200 for Sun Workstation
- Supports All ispLSI Device Families
- Download to Programmer or Circuit Board

Data 1/0 ABEL
The easy-to-use, menu-driven ABEL software packages
provide a complete pre-fit design environment. Using the
ABEL Hardware Description Language (AHDL) from DATA
I/O Corporation or the IEEE standard VHDL, complex
designs can be quickly and efficiently described using a
combination of Boolean Equations, Truth Tables, State
Machine syntax or other HDL descriptions. The HDL
syntax allows design creation without regard to any specific device dependencies. The built-in functional simulator
allows designs to be fully verified before device fitting. The
menu driven environment makes design implementation
as easy as clicking a mouse button. Synario will support
schematic entry and additional features.

pDS+ ABEL Software
The Lattice pDS+ ABEL Fitter for pLSI and ispLSI devices
is completely integrated within the ABEL Software environment. The Lattice Fitter provides hands-off design
implementation through intelligent design optimization,
logic partitioning, automatic place & route and fusemap
generation with optional test vectors, in standard JEDEC
format. Extensive top level design control is provided to
optimize design implementation for speed and/or high
device resource utilization. The pDS+ ABEL Fitter performs the following functions during design synthesis:

• PC and Sun Workstation Design Platforms
- PC - 386/486/Pentium IBM Compatible PC
- Sun Workstation - Sun SPARC 4

-

Design Optimization and Logic Minimization

-

Automatic Partitioning

- Automatic Place and Route

'Not intended for production programming

-

Design Parameter Control

-

Fusemap Generation

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-15

1994 Data Book

•

H~Lattice
......

pDS+ ABEL Software

••••••
••••••

Figure 3. pDS+ ABEL Fully Integrated Design Environment
ABEL

VHDL Direct ™

pDS+ ABEL Fitter
Design Process Manager (DPM)

L-____________________________________~~~
Report File

Design Optimization and Logic Minimization
The pDS+ ABEL Fitter uses proprietary algorithms targeted for device specific features. The Fitter optimizes
the design thoroughly, compressing multiple level logic
into two level logic, and utilizing logic minimization,
product term sharing and XOR functions wherever necessary.ln addition, the pDS+ ABEL Fittersupports multiple
fitting strategies to obtain the best device utilization and
performance.

Automatic Partitioning
The pDS+ ABEL Fitter incorporates a powerful Automatic Partitionerfor hands-free synthesis of a design into
Generic Logic Blocks (GLBs). The partitioner takes full
advantage of the device's powerful features such as the
hard XOR function and product term sharing. The internal XOR can be utilized for Arithmetic functions, T-Type
flip-flops, and on & off set optimization functions. The
partitioner also makes extensive use of product term
sharing. Product term sharing allows the fitter to efficiently use device resources by sharing product terms
across multiple logic functions. These features combine
to maximize device resource utilization and increase
design performance.

Automatic Place and Route
Automatic place and route eliminates the need for manual
editing and accelerates the design cycle. The Router
automatically generates pinouts based on the optimal
design implementation or uses user assigned pinouts. It
offers two routing options:
-

Fast Route
Strong Route

The Fast Route option allows quick place and route for
fast debugging of designs. The Strong Route option
performs a comprehensive route to maximize device
resource utilization and ensure efficient design implementation. The result is small design changes don't
result in expensive PC Board rework.

Design Parameter Control
Extensive design parameter control at the design entry
level is possible with the pDS+ ABEL Fitter giving the
user the option to optimize the design for maximum
utilization and speed. Controls are specified using "Property" statements in the ABEL design file. These controls
fall into two categories:
-

6-16

Performance and Utilization Control
Design Implementation Control

1994 Data Book

~HLattice
• •••••
......
••••••

pDS+ ABEL Software
ISP_EXCEPT_ Y2

Performance and Utilization Control
Special properties can be passed to the pDS+ ABEL
Fitter providing complete control over critical design
considerations. Fitter control over design partitioning and
routing optimizes the design for speed and/or device
utilization. Here are a few of the powerful features:
Specifies maximum level of (GLB's) delay
PRESERVE

Maintains a net as GLB output

SCP/ECP

Defines critical paths to reduce delays

EFFORT

Runs four optimization strategies and
uses the best to implement the design

CRIT

Instructs router to use the faster Output
Routing Pool Bypass

SNP/ENP

Defines logic paths for no logic minimization

SAP/EAP

Defines asynchronous paths to prevent
signal duplication

LXOR2

Defines nets to use the internal hard
XOR for speed (Macro library element)

Design Implementation Control
pDS+ ABEL Design implementation controls are used for
changing such design parameters as security, clocking,
etc. Some of the implementation controls are:

Reserves all ISP pins except Y2
Uses Y1 clock pin on ispLSI 1016/
pLSI 1016 as a global reset pin

LOCK

Lets you lock I/O signals to specific
device pins.

Parameter File
The pDS+ ABEL Fitter provides a parameter file feature
which helps designers eliminate guesswork and optimizes the design for the right device. It allows the user
to try a number of design implementation options using
the design implementation controls in batch mode. The
parameter file instructs the partitioner and the router on
how to maximize both device utilization and performance.
The pDS+ ABEL Fitter also provides post-route equations
showing exactly how the design is implemented in the
selected device.

Fusemap Generation
The pDS+ ABEL Fitter generates a device fusemap in
standard JEDEC format. A security feature gives protection of proprietary designs from unauthorized duplication.
The fitter also appends any design test vectors in JEDEC
format to the device fusemap thus facilitating a quick,
easy functional verification of a programmed device.

Design Verification
MAX_GLB_IN Controls maximum number of inputs to a
GLB
AVG_GLB_IN

Specifies average number of inputs to a
GLB

FASTCLK

Lets you assign a product term clock to
use the Fast Clock Distribution network
to clock all or desired sets of registers

REGTYPE

Specifies register placement either in an
I/O Cell or GLB

PULLUP

Specifies internal pull-up resistors on all
or unused I/Os

SECURITY

Sets the device security cell to prevent
unauthorized fusemap read back

ISP

Instructs Router to reserve in-system
programming pins

The pDS+ ABEL software provides functional simulation
of all pLSI and ispLSI designs using the built-in ABEL
functional simulator. The simulation test vectors can be
combined into the JEDEC file for device testing in a
programmer.
Complete post route design verification can also be
performed using the optional Viewsim timing simulator.
The pDS+ ABEL software generates the "sim" file required for Viewsim simulation. Simulation libraries are
available from Lattice for both PC and Sun platforms.
The Viewlogic Viewsim simulation is available from Lattice for the PC platform.

6-17

1994 Data Book

•

~HLattice
••••••
......
••••••

pDS+ ABEL Software
currently supported by programmers from the following
vendors:

System Requirements (PC Platform)
- 386/486/Pentium IBM Compatible PC
- MSDOS Version 3.3 or Later
- 16 MB RAM with 10MB Hard Disk Space
- ABEL 4.1 or Later
- Parallel Printer Port for Software Key

Programmer Vendor

Advin Systems

System Requirements (Sun Platform)

Pilot-U40
Pilot-GUGCE

-Sun Sparc4
- Sun OS Version 4.x
- Open Windows 3.0
- ABEL 4.1 or Later
- 16 MG RAM with 100 MB Hard Disk Space
- 3 Button Mouse

BP Microsystems

PLD-1128
CP-1128
2900

Data 1/0

3900
Unisite 40/48

Technical Support Assistance

Allpro40

Lattice Hotline:

1-800-LATTICE (Domestic)

Lattice Hotline:

1-408-428-6414 (International)

Lattice BBS:

Model
Pilot-U84

Logical Devices
Allpro 88
SMS Micro Systems

1-408-980-9814

Sprint Expert
System 3000

email:

applications@lattice.com

Stag
ZL30/A

pDS+ ABEL Ordering Information

System General

TURPRO-1

Product Code

Description

pDS2102-PC1

pDS+ ABEL Fitter for PC

High Pin-count socket adapters are available from Emulation Technology, EDI Corporation and PROCON.

pDS21 02-SN 1

pDS+ ABEL Fitter for Sun
Workstation

isp Engineering Kit Ordering Information

pDS2102M-PC1

pDS+ ABEL Fitter Maintenance

pDS2102M-SN1

pDS+ ABEL Fitter Maintenance

pDS3302-PC1

Viewlogic Viewsim Timing and
Functional Simulator
Viewlogic Viewsim Timing and
Functional Simulation Libraries and
Interface Files (For customers who
already own Viewlogic Viewsim)

pDS1102-PC1

Note: Contact Lattice for availability of pDS+ ABEL
support for Synario and pLSI & ispLSI 2000 and
3000 Families.

Kit Contains Programming Module (Base Unit),
Download Cable, AlC Adapter, Socket Adapters
and
One ispLSI Device Sample Included per Adapter

Product Code

Description

pDS4102-PM

Model 100 Universal Programming
Module (for PC)

pDS4102-WS

Model 200 Universal Programming
Module (for Sun)

Warranty/Update Service

Programmer Support

• 90 Day Warranty on Disk Media

All devices in the Lattice ispLSI device families can be
programmed while installed on the target circuit board. Insystem programming can be performed either via the isp
Engineering Kit or by an on-board microprocessor.
All Lattice ispLSI and pLSI devices can be programmed
using third-party PLD programmers. These devices are

• One year Maintenance Support Included with Purchase
• Annual Maintenance Agreement Available
• 90 Day Warranty on isp Engineering Kit

6-18

1994 Data Book

~~~Lattice
••••••

pDS+™Viewlogic
Software

••••••
••••••

Features

Introduction
The pDS+ Viewlogic Software from Lattice Semiconductor now offers a powerful solution to fit high density logic
designs into Lattice's pLSI and ispLSI devices.

• pLSl1ib and ispLSr" Development System
-

Supports All pLSI and ispLSI 1000 Devices

-

Support for 2000 and 3000 Families Under
Development

• Integrated Workview 4.x, Pro Series, Workview
Plus or Powerview Development Environment for
Design Entry
-

Schematic Entry
Over 300 "TTL-like" Macros
Viewsynthesis VHDL Language Entry
Graphical Menu Driven User Interface
Command Line Driven User Interface

Design entry and implementation is made simple using
the software environments from Viewlogic Corporation.
Viewlogic has a number of software products of various
names. The new Pro Series of products will be supported
by Lattice in 1994. For simplicity the tools are referred to
as Viewdraw, Viewsim and Viewsynthesis. The Lattice
pDS+ Viewlogic software supports high level, device
independent design entry together with efficient logic
compilation, delivering the most complex designs in the
shortest time possible.

• Lattice pDS+ Viewlogic Fitter
-

Automatic Device Fitter Ensures
High Utilization and Performance
Efficient Design Optimization & Minimization
Automatic Partitioning
"Hands Free" Automatic Place and Route
Fast Route Option for Quick Turnaround
Strong Route Options for Comprehensive and
Optimized Routing
Predictable Performance

• Complete Design Verification
-

Using Viewsim Timing Simulator

• Industry Standard Programming File Generation
-

Standard JEDEC Device Fusemap

• Optional isp Engineering Kit*
-

Programmer for Engineering Use
Model 100 for PC
Model 200 for Sun Workstation
Supports All ispLSI Device Families
Download to Programmer or Circuit Board

• PC and Sun Workstation Design Platforms
-

Viewlogic's Software
Viewlogic supports schematic entry using Viewdraw.
Viewdraw lets you create designs without regard to any
specific device dependencies. Viewdraw offers advanced
features such as cut and paste, unlimited zoom and pan
functions, automatic symbol generation as well as many
other features to streamline and speed-up the design and
verification process. Viewsynthesis supports VHDL language entry as well. The integrated design environment
supports an optional timing simulator (Viewsim) so designs can be fully simulated before device programming.
The Menu-driven environment makes design implementations as easy as a single click of the mouse button. The
pDS+ Viewlogic design environment also offers the user
multi-window operation, allowing schematic, simulator
and waveform (Viewwave) windows to be opened concurrently. Results can also be dynamically back annotated
to the schematic for design verification.
The Viewwave software is a graphical editor for creating
simulation input stimulus as well as analyzing waveforms. This graphical editor/analyzer also increases
designer productivity through its speed and ease-of-use.

PC - 386/486/Pentium IBM Compatible PC
Sun Workstation - Sun Sparc 4

'Not intended for production programming

pDS+ Viewlogic Software
The Lattice pDS+ Viewlogic Fitter for pLSI and ispLSI
devices is completely integrated within the Viewlogic

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-19

1994 Data Book

•

I

pDS+ Viewlogic Software
environment. The Lattice pDS+ Viewlogic Fitter provides
hands-off design implementation through intelligent design optimization, logic partitioning, automatic place and
route and fusemap generation. The pDS+ Viewlogic
software comes complete with a library of over 300 TTLlike macros to simplify design entry. Extensive top level
design control is provided for design implementation
optimized for speed andlor high device resource utilization. The pDS+ Viewlogic Fitter performs the following
functions during design synthesis:
-

Design Optimization and LogiC Minimization

-

Automatic Partitioning

-

Automatic Place and Route

-

Design Parameter Control

-

Fusemap Generation

pDS+ Viewlogic Macro Library
The pDS+ View logic software offers an extensive selection (over 300) of TTL-like macros. These macros enable
the design engineer to use familiar predefined functions
to build a design. Table 1 shows a summary of the
available macros in the pDS+ software.
Table 1. Macro Summary
Macro Type

AND/NAND
OR/NOR
XORlXNOR
II0s
Flip-Flops
Latches
Arithmetic
Counters
Shift Registers
Miscellaneous

Quantity

29
24
12
89
39
30
22
65
15
45

Figure 1. pDS+ Viewlogic PC Design Interface

0478E

6-20

1994 Data Book

pDS+ Viewlogic Software

••••••
••••••
••••••
Figure 2. pDS+ Viewlogic Integrated Design Environment

pDS+ Vlawloglc FIlla,
Design Process Manager (OPM)

~----~~
L---------t-l~
RaponFila
0817...

Figure 3. pDS+ Viewlogic Multi-Window PC Design Environment
NAN3 .1(SCH)B-17··X11··O: 10

DRAW: X=973

6-21

Y=518

DX=2

DY=9

1994 Data Book

•

pDS+ Viewlogic Software
Design Optimization and Logic Minimization
The pDS+ Viewlogic Fitter uses proprietary logic synthesis algorithms targeted for device-specific features. The
fitter performs a thorough design optimization, compressing multiple level logic into two level logic, and
utilizing logic minimization, product term sharing and
XOR functions wherever necessary. In addition, the
pDS+ Viewlogic Fitter supports multiple fitting strategies
to obtain the best device utilization and performance.

Automatic Partitioning
The pDS+ Viewlogic Fitter incorporates a powerful Automatic Partitioner for hands-free synthesis of a design into
Generic Logic Blocks (GLBs). The partitioner takes full
advantage of the device's powerful features such as the
hard XOR and product term sharing. The internal XOR
can be utilized for Arithmetic functions, T-Type flip-flops,
and on & off set optimization functions. The partitioner
also makes extensive use of product term sharing. Product term sharing allows the Fitter to efficiently use device
resources by sharing product terms across multiple logic
functions. These features combine to maximize device
resource utilization and increase design performance.

Automatic Place and Route
Automatic place and route eliminates the need for manual
editing and accelerates the design cycle. The Router
automatically generates pinouts based on optimal design implementation or uses user-assigned pinouts. It
offers two routing options:
-

Fast Route
Strong Route

The Fast Route option allows quick place and route for
fast debugging of designs. The Strong Route option
performs comprehensive routing to maximize device
resource utilization and ensures efficient design implementation. The result is small design changes do not
result in expensive PCB rework.

Viewdraw design file. These controls fall into two categories:
Performance and Utilization Control
Design Implementation Control

Performance and Utilization Control
Special attributes can be passed to the pDS+ Viewlogic
Fitter providing complete control over critical design
considerations. Fitter control over design partitioning and
routing optimizes the design for speed and/or device
utilization. Here are a few of the powerful features:
MAX_DELAY Specifies maximum levels of (GLBs)
delay
PRESERVE

Maintains a net as GLB output

SCP/ECP

Defines critical paths to reduce delays

EFFORT

Runs four optimization strategies and uses
the best to implement the design.

CRIT

Instructs router to use the faster Output
Routing Pool Bypass

SNP/ENP

Defines logic paths for no logic minimization

SAP/EAP

Defines asynchronous paths to prevent
signal duplication

LXOR2

Defines nets to use the internal hard XOR
for speed (This is a macro library element)

Design Implementation Control
pDS+ Viewlogic Design implementation controls are
used for changing such design parameters as security,
clocking and pin locking. Some of the powerful implementation controls are:
Controls maximum number of inputs
to a GLB
Specifies average number of inputs to
aGLB
FASTCLK

Assigns a clock to the Fast Clock
Distribution network to clock all or desired sets of registers

REGTYPE

Specifies register placement either in
an I/O Cell or GLB

PULLUP

Specifies internal pull-up resistors on
all or unused I/Os

SECURITY

Sets the device security cell to prevent
unauthorized fusemap read back

Design Parameter Control
The pDS+ Viewlogic Fitter offers extensive design parameter control at the design entry level, letting the user
optimize the design for maximum utilization and/or speed.
All of the controls are specified using "Attributes" in the

6-22

1994 Data Book

pDS+ Viewlogic Software

·......
.....
••••••
ISP

Instructs Router to reserve device insystem programming pins

System Requirements (Sun Platform)

ISP _EXCEPT _ Y2 Reserves all ISP pins except Y2

as

Y1_AS_RESET

Uses Y1 clock pin on ispLSI and pLSI
1016 as a global reset pin

LOCK

Lets you lock 1/0 signals to specific
device pins

-

Technical Support Assistance

Parameter File
The pDS+ View logic Fitter provides a parameter file
feature which helps designers eliminate the guesswork
and optimizes the design for the right device. It allows the
user to try a number of design implementation options
using all of the design implementation controls in a batch
mode. The parameter file instructs the partitioner and
the router to maximize both device utilization and performance.
The pDS+ Viewlogic Fitter also provides a post route
design file for optional timing simulation.

Design Verification

Lattice Hotline 1-800-LATTICE (Domestic)
Lattice Hotline 1-408-428-6414 (International)
Lattice BBS
1-408-980-9814

Programmer Support
All devices in the Lattice ispLSI device family can be
programmed while installed on the target circuit board.
In-system programming can be performed either via the
isp Engineering Kit or by an on-board microprocessor.
All Lattice ispLSI and pLSI devices can be programmed
using third-party programmers. These devices are currently supported by programmers from the following
vendors:

The pDS+ Viewlogic software offers complete post route
design verification using the optional Viewsim timing
simulator. The pDS+ Viewlogic Fitter generates the
"wire" file required for Viewsim simulations, and generates a "sim" file which can be used in the Viewsim
simulator, or other design platforms. The Viewlogic
simulation libraries and the Viewsim simulator are available from Lattice.

Programmer Vendor

Advin Systems

Pilot-U40
Pilot-GUGCE

BP Microsystems

PLD-1128
CP-1128

The pDS+ Viewlogic software generates a device fusemap
in standard JEDEC format. A security feature offers
protection of proprietary designs from unauthorized duplication. The Fitter also appends any design test vectors
in JEDEC format to the device fusemap thus facilitating
a quick, easy functional verification of a programmed
device.

2900
Data 1/0

3900
Unisite 40/48
Allpro 40

Logical Devices
Allpro 88
SMS Micro Systems

System Requirements (PC Platform)
386/486/Pentium IBM Compatible PC
MS DOS Version 3.3 or Later
16 MB RAM with 40 MB Hard Disk Space
Workview 4.1 or Later
Serial Port for Mouse
3 Button Mouse (Mouse Systems Compatible)
Parallel Printer Port for Software Key

Model

Pilot-U84

Fusemap Generation

-

Sun Sparc 4
Sun
Version 4.x
Open Windows 3.0
Workview 4.1 or Powerview 5.0 or Later
16 MB RAM with 100 MB Hard Disk Space
3 Button Mouse

Sprint Expert
System 3000

Stag
ZL30/A
System General

TURPRO-1

High pin-count socket adapters are available from Emulation Technology, EDI Corporation and PROCON.

6-23

1994 Data Book

•

,

pDS+ Viewlogic Software
pDS+ Viewlogic Ordering Information
Software Products
pDS1102-PC1
pDS 11 02-SN 1
pDS1103-PC1
pDS1104-PC1
pDS1301-PC1
pDS2101-PC1
pDS2101-SN1
pDS3302A-PC1
pDS3302-PC1

Viewlogic Viewsim and Viewdraw Libraries and Interface Files (Direct Viewlogic Customers on the PC)
Viewlogic Viewsim and Viewdraw Libraries and Interface Files (Direct Viewlogic Customers on the Sun)
Viewlogic Viewsim and Viewdraw Libraries and Interface Files (Customers of Actel or Other FPGA
Suppliers on the PC)
Viewlogic Viewsim and Viewdraw Libraries and Interface Files (Xilinx Customers on the PC)
Viewlogic Viewdraw Schematic Editor
pDS+ Viewlogic Fitter for (PC)
pDS+ Viewlogic Fitter for (Sun)
pDS+ Viewlogic Viewsim Functional and Timing Simulator (PC) for Current Viewlogic Users
pDS+ Viewlogic Viewsim Functional and Timing Simulator (PC) for New Viewlogic Users

Maintenance Agreements
pDS1102M-PC1
pDS1102M-SN1
pDS1301 M-PC1
pDS21 01 M-PC1
pDS21 01 M-SN1
pDS3302M-PC1

Viewlogic Viewsim and Viewdraw Libraries and Interface Files (Lattice Viewsim Library Products)
(pDS11 02-PC1)
Viewlogic Viewsim and Viewdraw Libraries and Interface files (pDS1102-SN1)
Viewlogic Viewdraw Schematic Editor (pDS1301-PC1)
pDS+ Viewlogic Fitter (pDS2101-PC1)
pDS+ Viewlogic Fitter (pDS2101-SN1)
pDS+ Viewlogic Viewsim Functional and Timing Simulator (For all Lattice Viewsim Simulation Products)
(pDS3302-PC1 )

isp Engineering Kit
pDS4102-PM

pDS4102-WS

Model 100 Universal Programming Module for the PC:
Universal Programming Module,(2) 8 wire Download cables, AC/DC Power Supply Converter, 25-Pin
Parallel Port Adapter
Model 200 Universal Programming Module for the Sun

Warranty / Update Service
• 90 Day Warranty on Disk Media
• One year of Maintenance Support Included with Purchase
• Annual Maintenance Agreement Available
• 90 Day Warranty on isp Engineering Kit

6-24

1994 Data Book

~~~Lattice~
••••••

pDS+™LOGliC
Software

••••••
••••••

Introduction

Features

The pDS+ LOG/iC software from Lattice Semiconductor
offers a powerful solution to fit high density logic designs
into Lattice's pLSI and ispLSI devices.

• pLSl1i> and ispLSI'M Development System Support
- pLSI 1016, 1024, 1032
-ispLSI1016,1024,1032
- Support for 2000 Family Under Development

Design entry is made simple by using LOG/iC software
from ISDATA GmbH together with the pDS+ LOG/iC
Fitter for design implementation. The Lattice pDS+
LOG/iC software offers high-level, device independent
design entry with efficient logic compilation, delivering
unprecedented performance for the most complex designs.

• Design Entry Using ISDATA LOG/iC PLUS or
PERFECT and LOG/iC ODC
- Design Verification Using LOG/iC Functional
Simulation
- Lattice Fitter for Design Synthesis
- Optional Timing Simulator

ISDATA LOG/iC

• Integrated Development Environment for MixedMode Design Entry
ISDATA LOG/iC Syntax Including Boolean
Equations, Truth Tables and State Machines,
Optional VHDL, Schematics or Graphical State
Machine Entry
- Graphical Menu Driven User Interface
-

• Lattice pDS+ LOG/iC Fitter
- Automatic Device Fitter Ensures High
Utilization and Performance
- Efficient Design Optimization & Minimization
- Automatic Partitioning with High Utilization
- "Hands Free" Automatic Place and Route
- Fast Route Option for Quick Turnaround
- Strong Route Option for Comprehensive and
Optimized Routing
- Predictable Performance
• Industry Standard Programming File Generation
- Standard JEDEC Device Fusemap
• Optional isp Engineering Kit*
-

Programmer for Engineering Use
Supports ispLS11016, 1024, & 1032
Model 100 for PC
Download to Programmer or Circuit Board

The easy to use, menu driven ISDATA LOG/iC software
package provides a complete design environment. Using
the LOG/iC program package, complex designs can be
quickly and efficiently described using a combination of
Boolean Equations, Truth Tables, State Machine syntax
or other LOG/iC design. The LOG/iC syntax creates
designs without regard to any specific device dependencies. The built-in functional simulator allows designs to
be fully verified before device fitting. The menu driven
environment makes design implementation simple to
use.

pDS+ LOG/iC Software
The Lattice pDS+ LOG/iC Fitter for pLSI and ispLSI
devices is completely integrated within the LOG/iC software environment. The Lattice Fitter provides hands-off
design implementation through intelligent design optimization, logic partitioning, automatic place & route and
fusemap generation with optional test vectors in standard
JEDEC format. Extensive top level design control is
provided to optimize design implementation for speed
and/or high device resource utilization. The pDS+
LOG/iC Fitter performs the following functions during
design synthesis:
- Design Optimization and Logic Minimization
- Automatic Partitioning

• Runs on 386/486/Pentium IBM Compatible PC
-Not intended for production programming

-

Automatic Place and Route

-

Design Parameter Control

-

Fusemap Generation

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-25

1994 Data Book

•

I

~HLattice

pDS+ LOGliC Software

••••••
••••••
••••••

Figure 1. pDS+ LOG/iC Design Interface

~

110/06/93 111:40

!SDAT.4

LOG/iC

LOG / i C
PLD

Co....ands:

l'Iodules for:

1 Gates/FPGA 1 pprogra..

Gates

..-

-

VERIFY

GatesPro

DIR

PLDSEL

SYSTEI'I

START

J:;DIT

PRIttT

EXIT

UTIL

LOGDPI'I

COI'II'I

HELP

Copyright (C) 1985,1991 by ISDATA G..bH, Karlsruhe, Ger.. any ..VOlt are running LOG/iC release 3.4

Select ..odule or co ....and. Press  to execute

Figure 2. pDS+ LOGIiC Fully Integrated Design Environment

pDS+LDGIIC Filler
Design Process Manager (DPM)

L-------------------------------------~_i~~

0599E

6-26

1994 Data Book

~~~Lattice
......
......
......

pDS+ LOGliC Software
-

Design Optimization and Logic Minimization
The pDS+ LOG/iC Fitter uses proprietary algorithms
targeted for device specific features. The Fitter optimizes
the design thoroughly, compressing multiple level logic
into two level logic, and utilizing logic minimization,
product term sharing and XOR functions wherever necessary. In addition, the pDS+ LOG/iC Fitter supports
multiple fitting strategies to obtain the best device utilization and performance.

Automatic Partitioning
The pDS+ LOG/iC Fitter incorporates a powerful Automatic Partitioner for hands-free synthesis of a design into
Generic Logic Blocks (GLBs). The partitioner takes full
advantage of the device's powerful features, such as the
hard XOR function and product term sharing. The internal XOR can be utilized for Arithmetic functions, T-Type
flip-flops, and on & off set optimization functions. Common sUb-expressions are extracted, and unused registers
are eliminated. These features combine to maximize
device resource utilization and increase design performance.

Automatic Place and Route
Automatic place and route eliminates the need for manual
editing and accelerates the design cycle. The Router
automatically generates pinouts based on the optimal
design implementation or uses user assigned pinouts. It
offers two routing options:
-

Fast Route
Strong Route

Fitter Statements
Option Statements
Net Statements
Path Statements
Sym Statements

Fitter Statements
Special properties can be passed to the pDS+ LOG/iC
Fitter providing complete control over critical design
considerations. Fitter control over design partitioning and
routing optimizes the design for speed and/or device
utilization. Here are a few of the powerful features:
PART

Determines device type to be used

EFFORTITRY Runs four optimization strategies and
uses the best to implement the design.
TRY uses only one of the four strategies,
and overrides EFFORT if both are specified
LOCK

Lets you lock I/O signals to specific
device pins

MAX_DELAY

Specifies maximum level of (GLBs) delay

AVG_GLB_IN

Specifies average number of inputs to a
GLB. Default is 16

MAX_GLB_IN Controls maximum numberof inputs to a
GLB. Default is 16
FAST/STRONG Method of routing. Default is STRONG
ROUTE Fixed

Option Statements

The Fast Route option allows quick place and route for
fast debugging of designs. The Strong Route option
performs a comprehensive route to maximize device
resource utilization and ensure efficient design implementation. The result is small design changes don't
result in expensive p.c. board rework.

pDS+ LOG/iC Design implementation controls are used
for changing such design parameters as security, pullups etc. Some of the implementation controls are:
ISP

Instructs Router to reserve in-system
programming pins

ISP_EXCEPT_Y2 Reserves alilSP pins except Y2 (ispLSI
and pLSI 1016 only)

Design Parameter Control
Extensive design parameter control at the design entry
level is possible with the pDS+ LOG/iC Fitter giving the
user the option to optimize the design for maximum
utilization and speed. Controls are specified using "Property" statements in the Lattice Property file (.IPR). These
controls fall into five categories:

Y1_AS_RESETUses Y1 clock pin on ispLSI and pLSI
1016 as a global reset pin
SECURITY

Sets the device security cell to prevent
unauthorized fusemap read back

PULLUP

Specifies internal pull-up resistors on all
(ON) or unused I/Os

6-27

1994 Data Book

•

~~~Lattice
......
......
......

pDS+ LOGliC Software

Net Statements
These properties control how the design is mapped into
the specified features of the target device:
CLK 0 - 2

Assigns GLB clock signals

10CLK 0-1

Assigns I/O cell clock signals

FASTCLK

Assigns a product term clock to use any
one of the dedicated clock inputs to
clock all or desired sets of registers

SLOWCLK

Designate clock to use a product term
clock within a GLB

Fusemap Generation

PRESERVE

Prevents logic minimization on specified
nodes

CRIT

Specifies Output Routing Pool Bypass
Modes for selected duplication

Path Statements
The following properties specify paths in the design that
have special fitting requirements:
SAP/EAP

The pDS+ LOG/iC Fitter also provides post route equations showing exactly how the design is implemented in
the selected device. An optional timing simulator is also
available for detailed post route timing simulation of
designs using the VERIFY section of the menu.

The pDS+ LOG/iC Fitter generates a device fuse map in
standard JEDEC format. The fusemap is automatically
produced and inserted in the JEDEC file after a successful route. A security feature gives protection of proprietary
designs from unauthorized duplication.

Design Verification
The pDS+ LOG/iC software provides functional simulation of pLSI and ispLSI designs using the optional
LOG/iC Functional Design Verifier (FDV). The simulation
test program file (.DTP) can be created for device simulation in the VERIFY menu, but the FDV can also be
stimulated interactively on the screen.
Full timing simulation is also available using Viewlogic's
Viewsim Simulation (available from Lattice).

System Requirements

Defines asynchronous paths to prevent
signal duplication

SCP/ECP

Defines critical paths to reduce delays

SNP/ENP

Defines logic paths for no logic minimization

386/486/Pentium IBM Compatible PC
- MSDOS Version 3.3 or Later
- 16 MB RAM with 40MB Hard Disk Space
- 31/2" Floppy Disk Drive
-ISDATA's LOG/iC PLUS or PERFECT and
LOG/iC ODC SOFTWARE
- Parallel Printer Port for Software Key
- EGA Graphics Monitor or higher

Sym Statements
These allow you to choose to place a register in a specific
GLB or an I/O cell:
SYMIOC

Register in the I/O cell

SYM GLB

Register in the GLB

Technical Support Assistance

Parameter File
The pDS+ LOG/iC Fitter uses a parameter file (.IPR file)
feature to help designers optimize the design for the right
device. It allows the user to try a number of design
implementation options using the design implementation
controls in batch mode. The parameter file instructs the
partitioner and the router on how to maximize both device
utilization and performance.

6-28

Lattice Hotline:

1-800-LATTICE (Domestic)

Lattice Hotline:

1-408-428-6414 (International)

Lattice BBS:

1-408-980-9814

email:

applications@lattice.com

ISDATA Inc.

1-51 0-531-8553
1-800-777-1202

ISDATA GmbH: 49-721-751087

1994 Data Book

H~Lattice
••••••

pDS+ LOG/iC Software

••••••
••••••

Programmer Support

pDS+ LOG/iC Ordering Information

All devices in the Lattice ispLSI device family can be
programmed while installed on the target circuit board.
In-system programming can be performed either via the
isp Engineering Kit or by an on-board microprocessor.
All Lattice ispLSI and pLSI devices can be programmed
using third-party PLD programmers. These devices are
currently supported by programmers from the following
vendors:
Programmer Vendor

Product Code

Description

pDS2103-PC1
pDS2103M-PC1

pDS+LOG/iC Fitter for PC
pDS+LOG/iC Fitter Maintenance

pDS3302-PC1

Viewlogic Viewsim Simulator

pDS3302M - PC1

VI'ewsl'm Mal'ntenance

pDS1102-PC1

Viewsim Library

Model

isp Engineering Kit Ordering Information

Pilot-U84
Advin Systems

Pilot-GUGCE
BP Microsystems

-

Kit Contains Programming Module (Base Unit),
Download Cable and AlC Adapter

-

One ispLSI Device Sample Included per Adapter

Pilot-U40

PLD-1128
CP-1128

Product Code

Description

pDS4102-PM

Model 100 Universal Programming
Module

2900
Data 1/0

Warranty/Update Service

3900
Unisite 40148

• 90 Day Warranty on Disk Media

Allpro 40

• One year Maintenance Support Included with Purchase

Logical Devices
Allpro 88
SMS Micro Systems

Sprint Expert

• Annual Maintenance Agreement Available

System 3000

• 90 Day Warranty on isp Engineering Kit

Stag
ZL30/A
System General

TURPRO-1

High Pin-count socket adapters are available from Emulation Technology, EDI Corporation and PROCON.

6-29

1994 Data Book

•

~~~Latlice

Notes

••••••
••••••
••••••

6-30

1994 Data Book

ispTM Starter Kit
••••••
••••••
••••••

Starter Set of Software, Hardware, Datasheets and
Samples for Lattice ISP Products

Includes

Introduction

• Software
- pDS1016-PC1 Design Development System for
ispLSI 1016 Device
- ispGAL Download Software
- ispGDS'" (Generic Digital Switch) Compiler
and Download Software
- ispCODE'· ANSI C Compiled and Source
Programming Software
• Datasheets
- ispLSI 1016 Device Datasheet
- ispGAL22V10 Device Datasheet
- ispGDS22118/14 Device Datasheet
• Samples
- ispLS11016-60LJ Device in 44 pin PLCC
Package
- ispGAL22V10B-15LJ Device in 28 pin PLCC
Package
- ispGDS14-7J Device in 20 pin PLCC Package
• Hardware
- ispDOWNLOAD'" Cable

Features
• Easy to Use Kit Contains Everything Needed for
In-System Programmable Device Design-in
• Supports Lattice's ispLSI 1016 Device - the
Industry's Fastest High Density Programmable
Device at 110 MHz
• Supports Industry Standard 22V10 Architecture
Coupled with Lattice's Innovative In-System
Programmable Design Capability
• Supports Lattice's New isp Generic Digital Switch
for Applications such as Software Driven Hardware
Configuration and Multiple DIP Switch Replacement
•

E2CMOS

Technology

The isp Starter Kit is designed to make Lattice's innovative
in-system programmable device technology available in
a single, complete package. The isp Starter Kit contains
all the software, hardware, device samples, and
information you need to begin designing with Lattice's
ISP products. The ispLSI devices are the fastest High
Density Programmable Logic devices in the industry, at
110 MHz, as certified by PREpTM Benchmarks. Lattice's
new 7.5ns ispGAL22V10 device has all the advantages
of In-System Programmability and maintains the familiar
22V1 0 architecture and 28-pin PLCC pinout. The ispGDS
is Lattice's latest in-system programmable innovation.
This new family of devices offers the ability to configure
its programmable switch matrix to connect signals
arbitrarily between two banks of 1/0 pins or to force pins
to fixed high or low logic states.

In-System Programmability (ISP)
ISP is a Lattice innovation that supports device function
programming and reprogramming on the printed circuit
board at 5 volts. There are several advantages to
in-system programmability: First, it accelerates the system
and board level debug process and enables you to define
your board layout earlier in the design process. Second,
ISP eliminates bent leads caused by extra handling and
socket insertions made during the device programming
process. Third, systems incorporating ISP are
reconfigurable with the devices already soldered to the
p.c. board, minimizing board rework time and expense.
With this capability your system options are boundless
and easier field updates are made possible by
downloading a new configuration file via a floppy disk or
modem.

ispLSI 1016 and pDS 1016 Software
The ispLSI 1016 device is a fast, high density
programmable logic device containing 64 logic registers,
32 Universal 1/0 pins with input registers, four dedicated
input pins, three dedicated clock input pins, and a
programmable Global Routing Pool (GRP). The basic
logic element of the device is the Generic Logic Block
(GLB) which has 18 inputs, a programmable ANDIORI
XOR array, and four outputs that may be configured as

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-31

1994 Data Book

•

isp Starter Kit

••••••
••••••
••••••
either combinatorial or registered. Lattice's pDS1016
Design Software is a high performance development
environment that runs on IBM compatible 386/486/
Pentium PCs. The software has a friendly, efficient,
Microsoft Windows Interface which supports familiar
Boolean equation entry. pDS1016 features automatic
logic Place and Route for quick design implementation.
To make designing even easier there is a library of over
200 Logic Macros for fast design entry.

ispGAL22V10 and Download Software
The ispGAL22V10 is the industry's first in-system
programmable 22V10 device and offers a fast 7.5ns
maximum propagation delay time. The generic
architecture provides maximum flexibility by allowing the
Output Logic Macrocell (OLMC) to be configured by the
user. The logic functionality, fusemap, and AC and DC
parameters of the ispGAL22V1 0 are fully compatible with
standard bipolar and CMOS 22V1 0 devices. The 28-pin
PLCC package provides the same functional pinout as
the standard 22V1 0 by using thefour "No Connect" pins
on the 28 pin PLCC for the ISP interface signals.

ispGDS and CompilerlDownload Software
The Lattice ispGDS family is an ideal solution for
reconfiguring system signal routing and replacing DIP
switches used for feature selection. Each I/O cell can be
configured as an input, an inverting or non inverting
output, or a fixed TTL high or low output. Any I/O pin in
the one bank can be driven by any I/O pin in the opposite
bank. A single input can also drive one or more outputs
in the opposite bank, allowing a Signal, such as a clock,
to be distributed to multiple destinations on the board.
The ispGDS Compiler and Download Software is a
simple text entry and compilation design tool that produces
a standard JEDEC file for device programming.

Ordering Information
Part Number

Description

isp-SK

Lattice isp Starter Kit

Designs for the ispGAL22V10 can be compiled by any
logic compiler supporting the 22V10 architecture. The
ispGAL Download Software takes any 22V1 0 JEDEC file
as input and programs the device in-system, quickly and
easily.

6-32

1994 Data Book

ispCODE™
••••••
••••••
••••••

Source Code for In-System Programming
of the Lattice ispLSr Family
M

Features
• C-LANGUAGE SOURCE CODE FOR IN-SYSTEM
PROGRAMMING OFTHE ispLSI FAMILY
- Simplifies In-System Programming
- Pre-Defined Routines for Common
Programming Functions
- Extensively Commented Code Provides
Complete Reference
- Easy Modification Saves Valuable Time
- Supports Programming of Multiple ispLSI
Devices on Individual Boards
• ACCEPTS PROGRAMMING FILES FROM THE
pLSI AND ispLSI DEVELOPMENT SYSTEM (pDS@)
- Supports pDS and pDS+TM Software
- Supports ispLS11000, 2000, and 3000 Families
• PORTABLE TO ANY HARDWARE PLATFORM
- Adaptable to Any Hardware Interface
- UNIX Systems, PCs, Testers, Embedded
Systems
- ANSI-Standard C for Portability
• GENERATES ispSTREAMTM FORMAT FOR
GREATER EFFICIENCY
- Bit-packed File Format for Storing JEDEC
Fusemap
- Requires Less Than 1/8 the Storage Space of a
Standard JEDEC File
- Ideal for Use in Embedded Systems, PROMs
and EPROMs
- Includes Checksum To Assure Data Integrity
• USER ELECTRONIC SIGNATURE (UES)
SUPPORTED
- Provides Data Storage Area In Device
- Facilitates User Identification of Program for
Secured Devices
- Automatic Counter Records Number of
Programming Cycles
• EXTENSIVE EXAMPLE FILES
- Fast Learning Curve
-100% of Library Functions Demonstrated

Introduction
The ispCODE software from Lattice is designed to facilitate in-system programming of ispLSI devices on
customer-specific hardware platforms. The ispCODE
works with Lattice's pLSI and ispLSI Development System software to give users a powerful, fully integrated tool
kit for developing logic designs and programming ispLSI
devices "on-the-fly."
After completion of the logic design and creation of a
JEDEC file by the pDS or pDS+ software (see figure 1),
in-system programming can be accomplished on customer-specific hardware: UNIX systems, PCs, testers,
embedded systems (see figure 2). The ispCODE software package supplies specific routines, with extensively
commented code, for incorporation into user application
programs. These routines provide users with flexible,
easy-to-use program modules which support the programming of a single device or multiple devices on a
board.

ispCODE Software
The ispCODE software consists of source files containing subroutines for performing all the functions needed to
control the programming of Lattice in-system programmable devices (see Table 1). These routines are provided
as fully-commented source code for easy inclusion with
any software written in the industry-standard C language.
This source code library was designed from the ground
up to be easily portable to any system that has an ANSIstandard C compiler. The majority of the code is completely
independent of the hardware platform and rarely requires
modification. All hardware dependent portions of the
code are in a separate file, and are easily modified for any
hardware system. The code supports the programming
of multiple ispLSI devices by controlling the ispEN pins of
each device separately, or in a daisy chain configuration.
Example programs are provided to demonstrate the use
of each routine. These example programs are designed
to enhance readability and understanding. In addition,
they provide a practical method of immediately programming devices. By making small changes to the
hardware-specific source files and re-compiling the example programs, a complete set of command-line oriented

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-33

1994 Data Book

•

I

~HLattice~

ispCODE

••••••
••••••
••••••

utilities are created that program, verify, read, and secure
devices.
All of the example programs and the hardware-specific
code are written to run on IBM PC or compatible microcomputers. The programs use the standard PC parallel printer
port to provide the interface to the Lattice device's insystem programming pins (see figure 3). The pinout is
compatible with the Lattice isp Engineering Kit Model 100.

There are ispCODE routines for converting JEDEC files to
ispSTREAM files, and for converting back to JEDEC files.
In addition, ispCODE software includes stand-alone programs called "jedtoisp" and "isptojed" which can be used
for converting files. When using the ispCODE routines and
the example programs, the JEDEC files are first converted
to ispSTREAM format. The ispSTREAM files are then
used to do the programming.

User Electronic Signature

Fusemap Storage
All of the ispCODE routines use a bit-packed file format for
storing the device pattem information. This bit stream is
called an ispSTREAM, and consists of one bit for each of
the programmable cells in the devices, plus one byte at the
front of the file for a device ID code, and four bytes at the
end of the file for a 32-bit checksum. This format provides
the most compact means possible for storing the pattern
information, requiring less than 1/8 the storage space of a
standard JEDEC file. This format is ideal for use in embedded systems, and the storage of ispLSI pattem information
in PROMs orEPROMs. Also, using the ispSTREAM format
simplifies the programming code, thus reducing the possibilityof errors. The following are the ispSTREAM storage
requirements for ispLS11000 family devices:

DIllia
ispLSI1016
ispLSI1024
ispLSI1032
ispLSl1048

The ispCODE library provides routines for accessing the
UES (User Electronic Signature), which is a user-accessible data storage area present in all Lattice in-system
programmable devices. This area can be used to store
information relating to the current configuration of the
device or system, and is always readable, even when the
functional portions of the devices are secured.
The ispLSI 1000 family devices have the following UES
areas available:
~

ispLSI1016
ispLSI1024
ispLSI1032
ispLSI1048

UESArea
8 bytes
13 bytes
18 bytes
28 bytes

Storage ReQuirement

1933 bytes
3078 bytes
4343 bytes
7233 bytes

Figure 1. Using the ispCODE SOftware

--

.....

.......

Programming

Signal.

6-34

1994 Data Book

ispCODE

• •••••
......
Figure 2. Configuring an ispLSI Device from an On-board Microprocessor

5-Pin Programming
Interface

5

•

Figure 3. Configuring an ispLSI Device from a Remote System
End-Product P.C. Board

Parallel Port
Connection

6-35

1994 Data Book

~HLatticem
......
••••••

ispCODE

••••••

Automatic Program Count
Another useful feature of ispCODE is the implementation
of a program counter. A section of the same area in which
the UES is stored is reserved for a 16-bit count of
programming cycles. When the ispCODE routines are
used exclusively for programming the device, an accurate count of programming cycles will be available to the
user. The programming routine automatically increments
the count after each programming cycle. There is also a
routine which reads the count value from the device.

Routine

Purpose
program the entire device

isp_read()

read the entire device

isp_verify()

verify the entire device

isp_secure()

secure the device

isp.Jedtoisp()

convert JEDEC file to ispSTREAM format

ispJsptojed()

convert ispSTREAM format to JEDEC file

isp_newO

initialize device data structure, including
pattern data and address

isp_delete()

delete device data structure

isp_read_ues()

read the User Electronic Signature (UES)
from the device

isp_ues_to_string()

convert an array of UES bits to a standard
Cstring

isp_string_to_ues()

convert a standard C string to an array of
UES bits

isp_compare_ues()

compare two arrays of UES bits

isp_geccount()

get the programming count

isp_geUd()

get the device ID from a device

isp_add_checksum()

calculate and add/update an ispSTREAM
checksum

isp_check_stream()

verify the checksum of an ispSTREAM

isp_calc_checksum()

calculate the checksum of an ispSTREAM

Devices Supported
The ispCODE library of routines will support all Lattice insystem programmable devices. As new devices are
developed and released, the ispCODE library will be
updated to include them.

Table 1. High Level Routines
isp"'program()

Multiple isp_STRUCT structures may be allocated at
once, since all the routines take a pointer to a Single
isp_STRUCT, and don't depend on any global variables.
Each structure created holds a pointerto an ispSTREAM,
as well as the 1/0 port address, for the device (and other
device-specific data). Different devices could be located
at different addresses and easily programmed by sequential calls to the isp_programO routine with a different
isp_STRUCT pointer each time.

Hardware Requirements
The ispCODE routines are designed to be portable to any
hardware platform with an ANSI C compiler available.
The code is written such that accessing the pins of the
Lattice device is done by writing to a memory or 110 port
address.
In addition to driving the pins, a method of controlling
timing in the millisecond range is required. The best
approach for this is a hardware-based method, such as
a timer chip that can be read. Most micro controllers have
a timer built in, and most other systems have some way
of keeping time that may be used. The ispCODE source
files include an example of reading the timer chip on a PC
to accurately time the programming pulses.

ispCODE Ordering Information
Part Number

Description

pDS4103

ispCode Software - ANSI C Compiled
and Source Files

Lattice includes a copy of the ispCODE with pDS and
pDS+ software purchases.

Technical Support Assistance

Using the Routines
All the user-accessible routines use a data structure
(isp_STRUCT) to hold all the data needed to do any ISP
operation on a given device. This structure is defined in
a header file, which must be included in any program that
calls the Lattice routines. There are two routines, isp_newO
and isp_deleteO, which handle the memory allocation
and freeing, as well as the data initialization for
isp_STRUCT items.

Lattice Hotline: 1-800-LATTICE (Domestic)
Lattice Hotline: 1-408-428-6414 (International)

6-36

Lattice SSS: 1-408-980-9814
email: applications@lattice.com

1994 Data Book

ispCODE

••••••
••••••
......
ispCODE Example Program
Below is a sample program using the Lattice routines to
program, verify, and secure a device from an ispSTREAM
file. The usual error checking has been omitted for clarity,
with the ispCODE specific sections in boldface type. This
file would be compiled and linked with the ispCODE
routines to produce the executable program.
#include
#include
II include



"isplsi.h"

void main(int argc, char *argv[])
(

isp_STRUCT *device;
unsigned inport, outport;
FILE *source_file;
int verified = FALSE;
int

i, dev_nuID;

/* Program device #1 */
dev_num = 1;

/* use LPT1 parallel port on PC */
inport = PORT1_IN;
outport = PORT1_0UT;

II

/* Initialize isp device structure, allocate memory for the
ispSTREAM, and set device type and I/O ports */
device = isp_new(ispLSl1032, TRUE, FALSE, inport+1, outport, dev_num);

I

/* read file into ispSTREAM buffer allocated by isp_new()*/
source_file = fopen (argv[l],' rb") ;
for( i=O; istreamLbits; i++)
device->stream[i] = getc(source_file);
/* print status and program the device */
printf( "Programming .... Please wait. \n");
isp-program(device, FALSE);
/* print status and verify the device */
print f ( "Verifying. . .. Please wai t. \n");
verified = isp_verify(device, TRUE);
i f ( verified)
(

printf('Device programmed and verified! \n");
/* secure device if verified properly */
isp_secure(device);
else
printf('ERROR: Device did not verify \n");
/* free the memory allocated for the isp_STRUCT */
isp_delete(device);
/*main() * /

6-37

1994 Data Book

Notes

••••••
••••••
......

6-38

1994 Data Book

~~~Lattice

ispTM Engineering Kit
Mode/100

••••••
••••••
••••••

Features
• Supports All ispLSI 1000, 2000 and 3000 Family
Members
• Stand-alone Device Programmer
• Download Directly to an ISpTM Device on System Board
- Only 5 Control/Data Pins Needed
• Quick Device Programming
• Inexpensive, Small and Compact
- Eliminates Need For Expensive, Remote
Programmer
• Excellent for Prototyping New Designs
- Not Intended For Production Programming
• Easy to Use
• Connects Directly to Parallel Printer Port of Host PC

Description
The isp Engineering Kit Model 100 provides designers a
quick and inexpensive means of evaluating and
prototyping new designs using Lattice in-system programmable Large Scale Integration (ispLSITM) devices.
This Kit is designed for engineering purposes only and is
not intended for production use. The Kit programs
devices from the parallel printer port of a host PC using
the Lattice pLSl/ispLSI Development System (pDS®j or
pLSl/ispLSI Development System Plus (pDS+TM) PCbased designs tools. By connecting a system cable
(included) from the host PC to the isp Engineering Kit, or
connecting from the host PC to the target device on the
system board, a JEDEC file can be easily downloaded
into the ispLSI device(s).

isp Engineering Kit - Model 100

UPM Description
The Model 100 Universal Programming Module (UPM) is
designed to support all package types available from
Lattice. It consists of the following components:
-

Universal Programming Module Base Unit

-

Power Supply Converter (11 OVAC/9VDC @
200mA)

-

Components

-

The isp Engineering Kit Model 100 consists of two primary components, each sold separately:
Universal Programming Module (UPM)
Socket Adapters
The adapters plug into the UPM base. The adapter
provides the appropriate PLCC, PQFP, TQFP, or
QFP socket for a particular ispLSI device package.

- Included for North America and Asia Only
25-Pin Parallel Port Adapter
6' Universal Programming Module Download Cable
with Modular Phone connectors (RJ45) on both
ends
6' System Download Cable with a Modular Phone
connector on one end and a AMP 1-87499-3 connector on other end

The connection between the host PC and the UPM base
unit is shown in figure 1.

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-39

1994 Data Book

•

~~~Lattice

isp Engineering Kit Mode/100

••••••
••••••
••••••

Electrical Characteristics

Download Cables
Download Cable with RJ-45 Phone Connectors on
Both Ends

Power Supply
AC Input Voltage:

110 VAC

DC Output Voltage:

9VDC @ 200mA

UPM Physical Characteristics

Length:

6.0 feet (192.8 cm)

Connectors:

RJ-45 with eight positions

System Download Cable with RJ-45 Phone and
AMP 1-87499-3 Connectors

Length:

3.75 inches

Width:

2.625 inches

Length:

6.0 feet (192.8 cm)

Depth:

1.375 inchs

Connectors:

RJ-45 with eight positions
AMP single in-line 0.100 "
center spacing 8 positions

Figure 1. Universal Programming Module Description

RJ-45connector

7~

:_____________ jl-~-'g-ht-pos--'-9-·Otns===::::;L-LJ~~':=..-

Vee.

Soo.

~i

IspEN •

Place

behind security
key

plug.

• 25-pin Parallel Port Adaplar

MODE •
GND •
SCLl< •

• 6' Universal Programming Module Cable
• 6' System Download cable with
Modular AMP ConnllClDr

adapter
i
on paraHeI
port i
RJ-45

pinout

SOl.

Programming Module
• Power SUpply Converter (9VDC)

It
_.
lUll

Front View
AMP Connector

--1

T

.01¢

capacitor

--Note: capacitor recommended
on system board

connector
positions

RJ-45

eight positions

:
9--1========::;,qLJI---r---.JI-n-n---n---.
--=--="
:-m--m---m-mmnnlr----'
connector

eight

-c:=

Universal Programming
Module
Base Unit

DC Power Plug

1-----l~I-~----~~--------------------.
~L-rS-u-~-~-co-n~~
~I
L -____________~
~

110VACI9VDC@200mA
PooHive or Negative..,.

2.1mm

J.---I
5.5mm

6-40

1994 Data Book

H~Lattice

••••••
••••••
••••••

isp Engineering Kit Mode/1DD

Ordering Information
Order Code

Product Description

pDS4102-PM

isp Engineering Kit Model 100 for the PC:
UPM programming module, (2) 8 wire Download cables, AC/DC Power Supply Converter,
25-Pin Parallel Port Adapter

pDS4102-J44

44-pin PLCC socket adapter, (1) ispLSI1016 Engineering Sample

pDS4102-T44

44-pin TOFP socket adapter, (1) ispLSI1016 Engineering Sample

pDS4102-J68

68-pin PLCC socket adapter, (1) ispLSI1024 Engineering Sample

pDS4102-J84

84-pin PLCC socket adapter, (1) ispLSI1032 Engineering Sample

pDS4102-T100

100-pin TOFP socket adapter, (1) ispLSI1032 Engineering Sample

pDS41 02-0120

120-pin POFP socket adapter, (1) ispLSI1048 Engineering Sample

pDS41 02-0128

128-pin POFP socket adapter, (1) ispLS11048C Engineering Sample

pDS4102-M160

160-pin MOFP socket adapter, (1) ispLSI 3256 Engineering Sample

pDS4102-G167

167-pin CPGA socket adapter, (1) ispLSI3256 Engineering Sample

•

6-41

1994 Data Book

~~~Lattice
......
••••••

Notes

••••••

6-42

1994 Data Book

~~~Lattice

ispTM Engineering Kit
Model 200

••••••
••••••
••••••

Features
• Supports All ispLS11000, 2000, and 3000 Family
Members
• Stand-alone Device Programmer
• Download Directly to an ISpTM Device on System Board
- Only 5 ControVData Pins Needed
• Quick Device Programming
• Inexpensive, Small and Compact
- Eliminates Need For Expensive, Remote
Programmer
• All External isp Signals Optically Isolated from
Workstation
- Prevents Ground Loop Problems
• Excellent for Prototyping New Designs
- Not Intended for Production Programming
• Easy to Use
• Connects Directly to Serial Port of Host
Workstation

isp Engineering Kit - Model 200

Description
The isp Engineering Kit Model 200 provides designers a
quick and inexpensive means of evaluating and
prototyping new designs using Lattice in-systems programmable Large Scale Integration devices (ispLSI'M).
This Kit is designed for engineering purposes only and is
not intended for production use. The Kit programs
devices from the RS-232 serial port of a host workstation
using the Lattice pLSl/ispLSI Development System Plus
(pDS+ TM) workstation based design tools by connecting
a system download cable (included) from the host workstation to the isp Engineering Kit.

Model 200 Description
The Model 200 Universal Programming Module (UPM) is
designed to support all package types available from
Lattice. It consists of the following components:
-

Power Supply Converter (110VAC/9VDC at
500mA)
- Included for North America and Asia Only
RS-232C (DB25P) Serial Port Adapter and cable

Components
The isp Engineering Kit Model 200 consists of two primary components, each sold separately:
-

-

Universal Programming Module (UPM)
Socket Adapters
The adapters plug into the UPM base. The adapter
provides the appropriate PLCC, PQFP, TQFP or
QFP socket.

Universal Programming Module Base Unit

6' Universal Programming Module Download Cable
with Modular Phone connectors (RJ45) on both
ends
6' System Download Cable with a Modular Phone
connector on one end and a AMP 1-87499-3 connector on other end

A drawing showing the connection between the workstation host and the UPM is shown in figure 1.

Copyright © 1994 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are
subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037

6-43

1994 Data Book

~~~Lattice
......
••••••

isp Engineering Kit Model 200

••••••

Left Panel

Detailed Functional Description

Top Panel

Power Input Jack

This jack is coaxial and accepts
the power plug from the Power
Supply Converter.

RS-232 RJ-11 Jack

This jack connects the RS-232C
flat cable to the workstation's
serial port.

BAUD

An eight position DIP switch that
sets the serial port communications parameters. This switch is
set at the factory for optimum
performance.

The top panel has three status indicator lights:
Power Indicator Light:

Green illuminates when the
power is turned ON and the correct input voltage is applied to
the programming module.

System Indicator Light: Green or Red. When data is
transmitted to or read from an
isp device on the socket adapter
board, the light becomes green.
When any type of error is detected during programming, the
light blinks red.
isp Indicator Light:

Green illuminates when data is
transmitted to or read from an
isp device that is connected to
the isp download cable. If the
programming module detects
the presence of a supply voltage on the isp download cable,
it becomes active and programming to the socket adapter board
is bypassed, regardless of the
presence of a device on the
socket adapter board.

Right Panel
ON/OFF Switch

This switch controls the input
power supplied to the programming module.

RJ-45 Jack

If download is to be performed
while an isp device is on board,
the isp download cable is
plugged into the RJ-45 jack.

Figure 2. isp Engineering Kit Model 200
Qulck-ReIeaaeL.evers

Quick-Connect Interface for Socket Adapter Boards
USE BOTH HANDLES

Located at rear of the top panel
are slots for the dual set of quick
release contacts and the
handles used to activate them.
The inner or outer pair of contacts is chosen depending on
type of socket adapter board
used. The handles are flipped
up when a socket adapter board
is inserted in the proper contact
slots. Push both handles down
to lock the socket adapter board
in place.

II~II

o} 0I 0J

isp Engineeri~ ~

Status IndIcatarUghts

Left Side Panel

...............

9VDC@500mA

lIP.,.

•

•

Power

BAUD

II

Rs=c

•

DIP Switch for Serial Pori Seb.lp

Right Side Panel

OFF_ON
•

6-44

Power Swftch

•

1994 Data Book

~HLattice

isp Engineering Kit Model 200

••••••
••••••
••••••

Figure 1. isp Engineering Kit Model 200
lop EnglMering Kit Contents
1. Model 200 Programming Module
2. Power Supply Converter

Connect Adapter

110VACI9VDC @5OOmA
3. Serial Port Coble (Adapler " Cable)
4. Isp Download Coble

to Workstation

5. User Documentation

Socket Adapter Board
(purchased separately)
• Sample Device

R5-232C Serial PorI

AMP connector
.100" center"'PBClng
Isp
(eight positions)
IspEn_KIt
Model 200
Programming Module

DB25P Male Connector
Pln# 2 Receive Data· to Model 200
Pln# 3 Send Data • from _1200
Pln# 7 Ground

RJ-45 connector

(elghtposHlons)

".j

~!-----[J=...l

Power SUpply Convertar

110VACl9VDC @ 500 mA

~Co-axlal Port Plug

IA

5.5mm

DownliJ
~

P

-

L -_ _ _ __

c - - - - - - ( N o t Used)
r-,---,-- Baud Rate

TT

D

QI2.1mm
Center polarity + or •

Front VIew
AMP
Connector

:

",:

500.

Vee"" •

~u~u~~u~
12345678

SDI.
IspEN.
plug •

ParHy OdcllEverI/IIIone

7-EIIt/&oBH - 1 Stop BIII2 Stop Bits - - - - DIP SwiII:h settings for Serial Port Set Up'

MODE •
GND •

1
.J

0.01

~f

capscRDr

SCLK.

*Note: These are factory settfngs
*Note: User's system must supply 5VDC @30mA

6·45

1994 Data Book

•

~HLattice

isp Engineering Kit Model 200

••••••
••••••

••••••

DIP Switch Settings

Electrical Characteristics

DIP switch settings for Model 200 are shown in Tables 1
to 4.

Power Supply

Note: SWl is not used and asterisk following parameters
are default factory settings

AC Input Voltage:

110 VAC

DC Output Voltage:

9 VDC @ 500mA

UPM Physical Characteristics
Table 1. RS-232C Baud Rate Selection
Baud Rate

Length:

6.50 inches

SW4

Width:

4.125 inches

DOWN

UP

Depth:

1.50 inches

DOWN

DOWN

SW2

SW3

38400·

UP

19200

UP

9600

DOWN

UP

UP

2400

DOWN

UP

DOWN

1200

DOWN

DOWN

UP

300

DOWN

DOWN

DOWN

Download Cables
Serial Port Cable with RJ-11 Phone Connectors on
Both Ends

Table 2. Parity Selection

Length:

6.0 feet (192.8 cm)

Connectors:

RJ-ll with 6 positions

System Download Cable with RJ-45 Phone and
AMP 1-87499-3 Connectors

Parity

SW5

SW6

None·

DOWN

DOWN

Length:

6.0 feet (192.8 cm)

Odd

UP

DOWN

Connectors:

Even

UP

UP

RJ-45 with 8 positions
AMP Single in-line 0.100"
center spacing 8 positions

Table 3. Word Length Selection
Word Length

7 Data Bits
8 Data Bits·

SW7
DOWN
UP

Table 4. Stop Bit Selection
Number of Stop Bits
1·

DOWN

SW8

2

UP

6-46

1994 Data Book

~HLattice
......
......
......

isp Engineering Kit Model 200

Ordering Information
Order Code

Product Description

pDS4102-WS

isp Engineering Kit Model 200 for the Workstation:
M200PM programming module, (1) 8 wire Download cable, (1) 6 wire Download cable, ACIDC
Power Supply Converter

pDS4102-J44

44-pin PLCC socket adapter, (1) ispLSI1016 Engineering Sample

pDS4102-T44

44-pin TQFP socket adapter, (1) ispLSI1016 Engineering Sample

pDS4102-J68

68-pin PLCC socket adapter, (1) ispLSI 1024 Engineering Sample

pDS4102-J84

84-pin PLCC socket adapter, (1) ispLSI1032 Engineering Sample

pDS41 02-T1 00

100-pin TQFP socket adapter, (1) ispLSI 1032 Engineering Sample

pDS4102-0120

120-pin POFP socket adapter, (1) ispLSI1048 Engineering Sample

pDS41 02-0128

128-pin PQFP socket adapter, (1) ispLSI 1048C Engineering Sample

pDS4102-M160

160-pin MOFP socket adapter, (1) ispLSI3256 Engineering Sample

pDS4102-G167

167-pin CPGA socket adapter, (1) ispLSI3256 Engineering Sample

6-47

1994 Data Book

~~~Lattice

Notes

••••••
••••••
••••••

6-48

1994 Data Book

ispDOWNLOAD Cable
TM

Download Cable for In-System Programming
of the Lattice ISP"" Family of Devices

••••••
••••••
••••••

Introduction

Features
• CABLE AND PARALLEL PORT ADAPTER FACILITATE
IN-SYSTEM PROGRAMMING OF ISP FAMILY OF
DEVICES
- Simplifies In-System Programming
- Ideal for Design Prototyping and Debugging

• SUPPORTS ALL ISpTM FAMILIES
- ispLSI'- Families (1000, 2000 and 3000)
-lspGAL· Family
- ispGDS- Family
• EASY-TO-USE CONNECTORS
- 25-Pin Adapter Connects to PC Parallel Printer
Port
- TWo 6' Cables Offer P.C. Board Interface
Options:
• RJ-45 Connector
• AMP Connector (8 Position, .100 Inch
Center Spacing)

The ispDOWNLOAD Cable product is designed to facilitate
in-system programming of all Lattice ISP devices on a
printed circuit board directly from the parallel port of a PC.
With In-System Programming, hardware functions can
be programmed and modified in real-time on the system
board to give additional productfeatures, shorten system
design and debug cycle time, enhance product
manufacturability and simplify field upgrades. After
completion of the logic design and creation of a JEDEC
file by a logic compiler such as the pDS®, pDS+™ Fitter
or ispGDS Compiler software, Lattice's ispDOWNLOAD
Software programs devices on the end-product p.c. board
by generating programming signals directly from the
parallel port of a PC which then pass through the
ispDOWNLOAD Cable to the device. With this cable and
a connector on the p.c. board, no additional components
are required to program a device. The ispDOWNLOAD
Software automatically generates the appropriate ISP
command, programming address and data from the
JEDEC fusemap information. ispDOWNLOAD Software
is included with all Lattice pDS and pDS+ Fitter products.
For the ispGDS, the ispDOWNLOAD Software can be
obtained directly from the Lattice Literature Department.

Figure 1. ispDOWNLOAD Cable Offers Two Types of In-System Programming Interfaces
Front View
of AMP Connector
Pinout

To . - -

PC

25-pln
Parallel
Port
Adapter

AMP Connector
.100· Center-Spacing
Eight Poeinons ,,"

---

RJ-45 COMector
Eight Poottlons

_ me

-- --'
,,

0 ----

It.

II

.011Jt

.... Capacitor

6'

------

•

Vee

.SOO
• SCI

To

•

IspEN

•

NoConnect

~ System

Board

.
•

MODE

•

GNO
SCLK

Note: Cepadtor Recommended on System Board

Front View

To . - -

PC

25-pln
ParaHel
Port
Adapter

RJ-45 Connector
Eight Poottlone

RJ~45

Connedor
Eight Posilions

II
II

01 RJ-45 Sockel
Pin Configuration

I~,~~

---+

1 - - - - 6' - - - - I

To
System

Board

'--Vee
Copyright 0 1994 Lattice Semiconductor Corp. AI brand or PfOduct names are trademarks or registered trademarks of their respective holders, The specifications and information herein are
subjecl to change without notloe.

LATIlCE SEMICONDUCTOR CORP., 5655 Northeast Mool9 Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; HIOO-LATTICE; FAX (503) 681-3037

6-49

1994 Data Book

ispDOWNLOAD Cable

••••••
••••••
••••••
Figure 2. PC Parallel Port Connector
0825 Parallel Port
Connector Pins

r--------,

74HC367 :

isp Interface

-+_<

DI6

Pin 10 _ _ _

DOO

Pin 2

>---i---VV--. SDIN

D01

Pin 3

SCLK

D02

Pin 4

D03

Pin 5

D04

Pin 6

D06
015

Pin 8
Pin 12

013
GND

Pin 15 - Vee Sense
Pin20-GND

>-~_..yV'-

MODE

>-~_..yV'- RESET

==:=J--

Port Sense

Figure 3. Configuring In-System Programming from a Remote System
End-Product P.C. Board

ispDownload
Cable (6')

Ordering Information
Part Number
pDS4102-DL

Description
ispDOWNLOAD Cable (For PC Only)
Contains: Two 6' Cables with RJ45 and AMP Connectors
Parallel Port Adapter
Documentation

6-50

1994 Data Book

pLSI and ispLSI Design Tool Selector Guide
DESIRED
DESIGN
ENVIRONMENT
LATTICE
pLSlandispLSI
Development System
(pDS)

DESIRED
CAPABILITIES
Entry and Fitting

Entry, Fitting,
and Simulation

pLSI and ispLSI
DESIRED FAMILY
SUPPORT
EXISTING
1000 2000 3000 TOOLS
x

DESIGN TOOL
SOLUTION

PC
ORDERING
INFORMATION

SUN
ORDERING
INFORMATION

None

pDS-STD (Standard)

pDStl0t-STD/PCt

N/A

x

pDSll0l

pDS 3000 Family Upgrade

pDSttOt-3UP/PCl

N/A

x

None

pDS-Ultra

pDStt Ot-ULT/PCl

N/A

x

x

x

x

x

None

pDS-STD (Standard)
Viewlogic ViewSim Simulator

pDStl0l-STD/PCl
pDS3302-PCl

N/A
N/A

x

x

ViewSim purchased
from Viewlogic

pDS-STD (Standard)
Viewlogic Interface/Library

pDStl0t-STD/PCl
pDS1102-PCl

N/A
N/A

x

x

ViewSim purchased
from ActellTllOther

pDS-STD (Standard)
Viewlogic Interface/Library Upgrade

pDStl0l-STD/PCl
pDStl03-PCl

N/A
N/A

x

x

ViewSim purchased
from Xilinx

pDS-STD (Standard)
Viewlogic Interface/Library Upgrade

pDStt Ot-STD/PCl
pDStt 04-PCl

N/A
N/A

x

x

x

None

pDS-Ultra
Viewlogic ViewSim Simulator

pDStl0t-ULT/PCl
pDS3302-PCl

N/A
N/A

x

x

x

ViewSim purchased
from Viewlogic

pDS-Ultra
Viewlogic Interface/Library

pDS110t-ULT/PCt
pDS1102-PCl

N/A
N/A

x

x

x

ViewSim purchased
from ActellTllOther

pDS-Ultra
Viewlogic Interface/Library Upgrade

pDStl0l-ULT/PCl
pDStl03-PCl

N/A
N/A

x

x

x

ViewSim purchased
from Xilinx

pDS-Ultra
Viewlogic Interface/Library Upgrade

pDStl 01-ULT/PCl
pDS1104-PCl

N/A
N/A

None

Lattice pDS Software to Support
pLSI10t6 and ispLS11016, ispGDS,
ispGAL22VtO, Device Samples,
Datasheets, and ispDownload Cable

isp-SK

N/A

0>

~

LATTICE
isp-Starter Kit
In System Programmable
isp-Starter Kit

x
an;nspGAL22Vt 0
and ispGDS

•

pLSI and ispLSI Design Tool Selector Guide (Cont.)

DESIRED
DESIGN
ENVIRONMENT
DATA I/O
ABEL

DESIRED
CAPABILITIES

pLSI and ispLSI
DESIRED FAMILY
SUPPORT
EXISTING
1000 2000 3000 TOOLS

DESIGN TOOL
SOLUTION

PC
ORDERING
INFORMATION

SUN
ORDERING
INFORMATION

None

ABEL 4.3 or Later
Lattice pDS+ ABEL Fitter

From Data I/O
pDS2102-PCl

From Data I/O
pDS2102-SNl

ABEL 4.3 or Later

Lattice pDS+ ABEL Fitter

pDS2102-PCl

pDS2102-SNl

None

ABEL 4.3 or Later
Lattice pDS+ ABEL Fitter
Viewlogic ViewSim Simulator
Viewlogic Interface/Library

From Data I/O
pDS2102-PCl
pDS3302-PCl
Included w/pDS3302

From Data I/O
pDS2102-SNl
From Viewlogic
pDSll02-SNl

x

ABEL 4.3 or Later

Lattice pDS+ ABEL Fitter
Viewlogic ViewSim Simulator
Viewlogic Interface/Library

pDS2102-PCl
pDS3302-PCl
Included w/pDS3302

pDS2102-SNl
From Viewlogic
pDSll02-SNl

x

ViewSim purchased
from Viewlogic

ABEL 4.3 or Later
Lattice pDS+ ABEL Fitter
Viewlogic Interface/Library

From Data I/O
pDS2102-PCl
pDSll02-PCl

From Data I/O
pDS2102-SNl
pDSll02-SNl

x

ViewSim purchased
from ActellTl/Other
(PC Only)

ABEL 4.3 or Later
Lattice pDS+ ABEL Fitter
Viewlogic Interface/Library Upgrade

From Data I/O
pDS2102-PCl
pDSll03-PCl

N/A
N/A
N/A

x

ViewSim purchased
from Xilinx
(PC Only)

ABEL 4.3 or Later
Lattice pDS+ ABEL Fitter
Viewlogic Interface/Library Upgrade

From Data I/O
pDS2102-PCl
pDSll04-PCl

N/A
N/A
N/A

None

Viewlogic View Draw Capture
Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library

pDSI301-PCl
pDS2101-PCl
Included w/pDS1301

From Viewlogic
pDS2101-SNl
pDSll02-SNl

x

ViewDraw purchased
from Viewlogic

Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library

pDS2101-PCl
pDS1102-PCl

pDS2101-SN1
pDS1102-SNl

x

ViewDraw purchased
from ActellTl/Other
(PC Only)

Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library

pDS2101-PCl
pDS1103-PCl

N/A
N/A

x

ViewDraw purchased

Lattice pDS+ Viewlogic Fitter

pDS2101-PC1

N/A

Entry and Fitting

x
x
Entry, Fitting,
and Simulation

x

Ol

cJ,

I\)

VIEWLOGIC
Workview, PRO Series,
Workview +, and
Powerview

---

Capture and Fitting

x

I
i

pLSI and ispLSI Design Tool Selector Guide (Cont.)
DESIRED
DESIGN
ENVIRONMENT
VIEWLOGIC
Workview, PRO Series,
Workview Plus, and
Powerview

DESIRED
CAPABILITIES

pLSI and ispLSI
DESIRED FAMILY
SUPPORT
EXISTING
1000 2000 3000 TOOLS

DESIGN TOOL
SOLUTION

PC
ORDERING
INFORMATION

SUN
ORDERING
INFORMATION

None

Viewlogic ViewDraw Capture
Viewlogic ViewSim Simulator
Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library

pDS1301-PC1
pDS3302-PC1
pDS2101-PC1
Included w/pDS1301

From Viewlogic
From Viewlogic
pDS2101-SN1
pDS1102-SN1

x

ViewDrawNiewSim
from Viewlogic

Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library

pDS2101-PC1
pDS1102-PC1

pDS2101-SN1
pDS1102-SN1

x

ViewDrawNiewSim
from ActelfTI/Other
(PC Only)

Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library Upgrade

pDS2101-PC1
pDS1103-PC1

N/A
N/A

x

ViewDrawlViewSim
fromXilinx
(PC Only)

Lattice pDS+ Viewlogic Fitter
Viewlogic Interface/Library Upgrade

pDS2101-PC1
pDS1104-PC1

N/A
N/A

x

ViewSynthesis
purchased from
Viewlogic

Lattice Viewlogic Synthesis Library

pDS110S-PC1

pDS110S-SN1

None

LOG/iC
Lattice pDS+ LOG/iC Fitter

From ISDATA
pDS2103-PC1

N/A
N/A

LOG/iC

Lattice pDS+ LOG/iC Fitter

pDS2103-PC1

N/A

None

LOG/iC
Viewlogic ViewSim Simulator
Lattice pDS+ LOG/iC Fitter

From ISDATA
pDS3302-PC1
pDS2103-PC1

N/A
N/A
N/A

x

ViewDrawlViewSim
from Viewlogic

Lattice pDS+ LOG/iC Fitter
Viewlogic Interface/Library

pDS2103-PC1
pDS 11 02-PC1

N/A
N/A

x

ViewDrawNiewSim
from ActelfTI/Other
(PC Only)

Lattice pDS+ LOG/iC Fitter
Viewlogic Interface/Library Upgrade

pDS2103-PC1
pDS1103-PC1

N/A
N/A

x

ViewDrawNiewSim
from Xilinx (PC Only)

Lattice pDS+ LOG/iC Fitter
Viewlogic Interface/Library Upgrade

pDS2103-PC1
pDS1104-PC1

N/A
N/A

Capture, Fitting,
and Simulation
x

O'l

0.

U)

Synthesis Option
(VHDL Entry)

ISDATA
LOG/iC

Entry and Fitting
x
x
Entry, Fitting,
and Simulation
x

I

pLSI and ispLSI Design Tool Selector Guide (Cont.)

DESIRED
DESIGN
ENVIRONMENT
LOGIC MODELING

0>

&.
-I>-

DESIRED
CAPABILITIES
Board and System
Level Simulation

pLSI and ispLSI
DESIRED FAMILY
SUPPORT
EXISTING
1000 2000 3000 TOOLS
x

DESIGN TOOL
SOLUTION

PC
ORDERING
INFORMATION

SUN
ORDERING
INFORMATION

None

SmartModel Library Subscription

Purchase from LMC

Purchase from LMC

Logic Modeling
Library Subscription

Routine SmartModel Library
Maintenance

Purchase from LMC

Purchase from LMC

pDS or pDS+
Software

ANSI C Source and Compiled
In System Programming Routines

pDS4103

pDS4103

pDS4102-PM

LATTICE ispCODE'
Programming
• Included with pDS and
pDS+ Fitter Software

x

LATTICE isp Engineering Programming
Kit and Socket Adapters

x

x

x

ispEngineering Kit Modell 00

x

x

x

ispEngineering Kit Model 200

x
x
x
x
x
x

x
x

x
x

44 Pin PLCC Socket Adapter
44 Pin TQFP Socket Adapter
68 Pin PLCC Socket Adapter
84 Pin PLCC Socket Adapter
100 Pin TQFP Socket Adapter
120 Pin PQFP Socket Adapter
128 Pin PQFP Socket Adapter
160 Pin MQUAD Socket Adapter
167 Pin PGA Socket Adapter

Socket Adapter
Socket Adapter
Socket Adapter
Socket Adapter
Socket Adapter
Socket Adapter
Socket Adapte r
Socket Adapter
Socket Adapter

x
x
x

pDS4102-WS
pDS4102-J44
pDS4102-T44
pDS4102-J68
pDS4102-J84
pDS4102-Tl00
pDS4102-Q120
pDS4102-Q128
pDS4102-Q160
pDS4102-G167

pDS4102-J44
pDS4102-T44
pDS4102-J68
pDS4102-J84
pDS4102-Tl00
pDS4102-Q120
pDS4102-Q128
pDS4102-Q160
pDS4102-G167

GAL Development
Support
Lattice Semiconductor recommends the use of qualified
programming equipment when programming Lattice devices. Lattice works with several programming
manufacturers to insure that there is cost effective equipment available. We have approved programmers in each
of the following catagories:
•
•
•
•

Low Cost GAL Only Programmers
Mid Range 28-pin Programmers
Full Universal Programmers
Production Programming Equipment

Lattice conducts a very stringent qualification procedure,
which includes a complete evaluation of the programming,
verification and load algorithms; verification of critical
pulse widths and voltage levels, along with a complete
yield analysis. The result is the best programming yields
in the industry and a guarantee of 100% programming
yields to customers using qualified programming
equipment. Below are the third-party programmers which
are qualified to program Lattice devices.
For a current listing of Lattice qualified programmers,
please call Lattice's Literature Distribution Department
(Tel: 503-693-0287; FAX: 503-681-3037).

LOGIC COMPILER SUPPORT

QUALIFED PROGRAMMERS
Vendor

Programmer

Vendor

Autosite

AccelTech.

Logic Compiler
Tango PLD
PIC Designer Composer

Unisite
Cadence
3900

PIC Designer Concept

Data VO
2900

DataVO

ABEL

29B

ISDATA

LOG/iC

60AlH

Logical Devices

CUPL

Allpro88

Mentor Graphics

PLSynthesis II

Allpro40

Minc

PLDesigner-XL

Logical Devices
OrCAD

OrCADPLD

ZL30B & ZL30A

Omation

Schema-PLD

Quasar-U84 & Quasar-U40

Viewlogic

ViewPLD

System 3000
Stag

TURPRO-1 & TURPRO-1/FX
System General
SGUP-85A
Sprint Expert
SMS Microcomputer
Sprint Plus
BP-1200
BP-Microsystems

PLD-1128 & CP-1128
PLD-1100
Pilot-U84 & Pilot-U40

Advin
Pilot-GL & Pilot-GCE

6-55

•

GAL Development Support
PROGRAMMER/COMPILER VENDORS
Accel Technologies
6825 Flanders Dr.
San Diego, CA 92121
Tel: (619) 554-1000
FAX: (619) 554-1019
Advin Systems
1050-L Duane Ave
Sunnyvale, CA 94086
Tel: (408) 243-7000
FAX: (408) 736-2503
BP Microsystems
1000 N Post Oak Road
Houston, TX 77055-7237
Tel: (713) 688-4600
1-800-225-2102
FAX: (713) 688-0902
BBS: (713) 688-9283
Cadence Design Systems
555 River Oaks Parkway
San Jose, CA 95134
Tel: (408) 943-1234
FAX: (408) 943-0513
Data VO Corp.
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
Tel: (206) 881-6444
Tel: 1-800-247-5700
FAX: (206) 882-1043
In Europe contact:
Data 1/0 Corp.
Tel: +31 (0) 20-6622866
In Japan contact:
Data 1/0 Corp.
Tel: (03) 432-6991

ISDATAGmbH
Haid-und-Neu-StraBe 7
7500 Karlsruhe 1
Germany
Tel: 0721-693092
FAX: 0721-174263
In the U.S. contact
ISDATAlnc.
Tel: (408) 373-7359
FAX: (408) 373-3622

Omatlon
801 Presidential
Richardson, TX 75081
Tel: (214) 231-5167
FAX: (214) 783-9072
OrCAD Systems Corp.
3175 N.W. Aloclek Dr.
Hillsboro, OR 97124
Tel: (503) 690-9881
FAX: (503) 690-9891

Logical Devices
692 South Military Trail
Deerfield Beach, FL 33442
Tel: (305) 428-6868
FAX: (305) 428-1181
Mentor Graphics
8005 SW. Boeckman Rd.
Wilsonville, OR 97070
Tel: (503) 685-7000
FAX: (503) 685-1204
Minc Incorporated
6755 Earl Dr.
Colorado Springs, CO 80918
Tel: (719) 590-1155
FAX: (719) 590-7330

SMS Micro Systems
1M Grund 15
0-7988 Wangen
Germany
Tel: (49) 7522-5018
FAX: (49) 7522-8929
In the U.S. contact:
SMS North America, Inc.
16522 N.E. 135th PI.
Redmond, WA 98052
Tel: (206) 883-8447
FAX: (206) 883-8601
Stag Microsystems
Martinfield
Welwyn Garden City
HertsAL71JT
United Kingdom
Tel: 011-44-707-332148
FAX: 011-44-707-371503
In the U.S. contact:
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
Tel: (408) 988-1118
FAX: (408) 988-1232

6-56

System General
3F1., No.1, Alley 8, Lane 45
Bao Shing Rd.
Shin Dian
Taipei, Taiwan R.O.C.
Tel: 886-2-9173005
FAX: 886-2-9111283
In the U.S. contact:
System General
510 S. Park Victoria Dr.
Milpitas, CA 95035
Tel: (408) 263-6667
FAX: (408) 262-9220
Viewlogic Systems
293 Boston Post Rd. West
Marlboro, MA 01752
Tel: (508) 480-0881
FAX: (508) 480-0882

ispGDS
Compiler Support
Introduction
To simplify the development of ispGDS devices, Lattice
offers an ispGDS assembler which processes the input
ASCII files to generate the JEDEC compatible fusemap
files required for the ispGDS devices. Free ispGDS
assembler software is available from the Lattice BBS at
503-693-0215 under GDSPKG.ZIP file. This software is
also available on diskette by calling the Lattice Hotline at
1-800-327-8425 (FASTGAL) For design engineers who
are familiar with standard third party compiler software
packages, ABEL from Data I/O and CUPL from Logical
Devices also support all ispGDS devices.

Using the GDS Compiler
The compiler will accept an ASCII text file containing the
GDS programming instructions, and will create JEDEC
and .DOC files. Once a JEDEC file has been created, the
ispGDS device can be programmed by either downloading
the JEDEC file to a programmer, or by using the ispGDS
Download utility to program the device using the parallel
port of an IBM compatible PC.

Compiler Syntax
The basic compiler syntax supports inserting comments,
title, device type, pin aSSignments and input/output
assignments. The ispGDS compiler source file comment
lines are denoted with quote marks atthe beginning ofthe
comment lines. The title is defined with the key word "title
=". Any text following the "title =" key word that are within
single quotes are defined to be the title of the design.
Similarly, the device type is defined by the key word
"device =" followed by the three valid device types -ispgds22, ispgds18, ispgds14. The compiler syntax also
allow the user to assign pin names by typing in a 10
character pin name followed by at least a single space,
the "pin" keyword and the pin number. This pin assignment
is optional since the compiler syntax allows the user to
use the "pin" key word and the pin number directly in the
input/output aSSignments.
The output pins are assigned on the left side of the
equation and the input pins are assigned on the right side
of the equation. To assign an output pin to either high or
low, simply assign "H" or "L· respectively on the right side
of the equation. If you need to assign an input pin to
multiple output pins, use one line for each assignment, as

shown in the following example. In the example below,
pin 28 is an input that is routed to three outputs - pin 1,
pin 2 and pin 3. Further, each output's polarity can be
individually defined. The example shows pin 3 as an
active low polarity whereas pin 1 and pin 2 are defined to
be active high polarity. An example source file is appended
at the end of this document.

=

pin 1 pin 28
pin 2 = pin 28
!pin 3 = pin 28

Assembling a File
To use the assembler, create an ASCII GDS source file,
then invoke the assembler from the DOS command line.
For example: gasm 
where test.gds is the name of the GDS source file. GDS
will create a JEDEC file with the same base name, and a
.JED extension, like "test.jed,· and a doc file with a .DOC
extension, like "test.doc."

Submitting a New Problem Report
If you find problems with the assembler, please ZIP the
following files together, and upload to the Lattice BBS at
(503)693-0215:
1. the GDS source file
2. the JEDEC file
3. a description of the error
Afterthe files are uploaded, please call the Lattice Hotline
at (800) 327-8425 and inform them that the files have
been uploaded.

Programming the ispGDS
You can either program the GDS using a JEDEC file
output from the GDS assembler, or by using the
GDS_PROG routines included in the GDSPKG software
package. To program the GDS using a programmer,
follow these steps:
1. Create an ASCII GDS source file
2. Assemble the GDS file using the GDS assembler
(GASM ).
3. Download the JEDEC file created by the assembler
to the programmer and program the device. The

6-57

ispGDS Compiler Support
JEDEC file will have the same name as your GDS
source file, but will have a .JED extension
(for example, "test.jed").

To program using the parallel port of the PC, follow these
steps:
1. Create an ASCII GDS source file

Alternatively, you may want to program the ispGDS
devices either through the parallel port of an IBM
compatible PC, or through some custom hardware
configuration. The routines included in the ispGDS
compiler software package are configured to use the PC
parallel port for programming. If you want to use a custom
hardware configuration, read through the comments in
GDS_PROG for information on which routines need to be
modified. If you are programming using the PC, you will
need an ispDOWNLOAD Cable and ISP programming
interface signals on the circuit board which will plug into
the printer port on your PC.

2. Assemble the GDS file using the GDS assembler
(GASM)
3. Convert the JEDEC file to ISP stream format by
running JEDTOISP. See the documentation on
JEDTOISP for further information.
4. Run GDS _PROG to program the device using the
parallel port.

GDS Source Format
The following text is an example of a GDS source file.
"This is a cormnent (line begins with quote mark)
title = 'DIP SWITCH REPLACEMENT CONFIGURATION'
" the ispgds device type (ispgds22. ispgdsl8. ispgdsl4)
device = ispgds22
" pin names are defined as follows
pin_name

pin 28

" pin 1 is an output connected to pin 28
pin_ name
pin 1
pin 2
pin 27
" pin 3 is another output connected to pin 28
pin 3

pin 28

" pin 5 is always high
pin 5
h
"pin 6 is always low
pin 6 = 1
pin 8 = pin 22
"! defines the inverted output for pin 9
!pin 9
pin 20
pin
pin
pin
pin

10
12
13
14

pin
pin
pin
pin

19
17
16
15

Notes
If you get an error regarding "pin 0", you may have duplicated an output pin assignment ( by assigning different input Signals to
the same output pin). Refer to the line number in the assembler error message to locate the source of the problem.

6-58

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Quality Assurance Program .................................................................. 7-1
Qualification Program ........................................................................... 7-3
PCMOS Testability Improves Quality .................................................. 7-5
ISO 9000 Program ................................................................................ 7-7

Section 8: General Information

7-i

7-ii

Quality Assurance
Program
Introduction
Lattice views quality assurance as a corporate responsibility and an integral part of all operational activities. Lattice's
Quality Assurance organization is independentfrom Manufacturing and has direct access to top management, assuring
sufficient authority is afforded to quality issues.
Lattice's quality program is in full compliance to the quality
assurance requirements of MIL-M-3851 0 Appendix A and
all inspection system requirements of MIL-I-45208. Lattice
is also fully certified to the ISO 9001 standard.

Reliability
All new products, processes and vendors must pass predefined evaluations before receiving initial qualification
release. Major changes to products, processes or vendors
require additional qualificaton before implementation. To
assure continuing conformance to reliability goals, an
ongoing monitor program is maintained on all products.

In-Process Control
Qualified product must be manufactured under strict quality controls that start with regulated procurement and
documented inspection plans for all incoming materials.
Sample testing and in-line monitoring as well as statistical
process control charts provide constant feedback at each
critical step of the manufacturing process.

commensurate to that of Lattice. These suppliers are
audited at least once a year to monitor their compliance to
Lattice's quality initiatives and goals. Incoming inspection
is performed to provide feedback and continuous improvement of subcontractor performance with the main objective
being to control quality atthe source. Communications and
in-line data are continuously exchanged to allow real-time
monitoring of subcontractor manufacturing operations.

Document Control
Every product and process must have adequate written
documentation released and available at the point of use
before production begins. All information related to the
definition, manufacturing, testing and support of Lattice
products or services shall be maintained and controlled.
Initial release as well as subsequent changes must be
properly reviewed and approved before implemented.

Nonconforming Material
Material found to be nonconforming to specified requirements is identified, segregated, analyzed and dispositioned
per documented procedures. Records are maintained
denoting the nature of the discrepancy as well as the final
disposition. All dispositions involve the applicable engineering section and Quality Assurance. Where applicable,
the root cause of the discrepancy will be identified and a
corrective action implemented using the CAR (Corrective
Action Request) form.

Failure analysis

Calibration
All equipment involved in determining product conformance to specifications through inspection, measurement or
testing must be of the required accuracy. Equipment is
calibrated and maintained on a defined interval against a
nationally recognized standard. In addition, equipment
must exhibit a suitable indicator showing calibration status
as well as safeguards to disallow unauthorized adjustments.

Training
Key manufacturing personnel must complete a formal
training program and obtain certification for each operation
before they are allowed to perform activities affecting
quality. Methods and records identifying the type and
extent of training are maintained and recertification required on a yearly basis.

Subcontractor Control
All subcontracted manufacturing operations must be performed by sources exhibiting a quality program

7-1

Failure modes discovered during qualification testing, inspections, customer returns or in-process screening are
processed through Lattice's Failure Analysis group to
determine the cause or relevancy of the failure. Verified
failure modes are documented and corrective action initiated as required to eliminate the root cause.

Corrective action
All operational functions utilize a documented corrective
action system coordinated, recorded and monitored by
Quality Assurance. The system is designed to provide for
proactive problem identification and resolution in a timely
manner. Inputs include vendor, internal and customer
related problems. Emphasis is placed on effective elimination of the root cause to prevent recurrence of the problem.
Management is responsible for ensuring that employees
have sufficiently well defined responsibilities, authority and
organizational freedom to identify potential quality related
problems as well as initiate and implement solutions.

Quality Assurance Program
Self Audit
Internal self audits of the entire quality and delivery system
are performed per written procedures and to a predefined
schedule. The functional audits evaluate actual method to
written procedure. The results of these audits are documented on a checklist and any discrepancies are brought
to the attention of personnel responsible for the audited
area. Deficiencies require corrective actions must be
initiated and subsequently verified as to deployment and
effectiveness. A periodic review of these functional audit
results and corrective actions is performed by Quality
Assurance.

Procurement
All direct materials and services affecting quality or reliability of end product must be purchased from qualified sources.
Selection of these critical suppliers is based upon one of
more of the following: quality system audits, product qualification testing, correlation studies, incoming inspection
and demonstrated ability. A qualified supplier list is maintained by Quality Assurance and used by Purchasing to
control procurement. Each purchase order must specify
the applicable controlling requirements for all such direct
materials or services.

7-2

Qualification
Program
Introduction
Lattice has an intensive qualification program for examining and testing new products, processes, and vendors in
order to insure the highest levels of quality. Lattice's
Quality and Reliability Group is responsible for defining and
implementing this qualification program.

The following table outlines the steps which must be
performed before a new product, package or process is
released. The requirements listed below are general
guidelines. Detailed information on Lattice's qualification
process is available to customers upon request.

Qualification Requirements
#of
Test

Duration

Samples

New Product

New Wafer Process

1250 C Operating Lifetest
(5.25V)

300

1,000 Hours

2,000 Hours

2,000 Hours 1

1500 C Biased Retention
Bake (5.25V)

450

1,000 Hours

2,000 Hours

2,000 Hours 1

Endurance Cycling

75

10,000 Cycles

10,000 Cycles

N/A

ESD (COM, HBM, MM)

216

End otTest

End of Test

N/A

Latch-Up Immunity

27

End otTest

End otTest

N/A

Temperature Cycling
(-65 to 1500 C)

150

1,000 Cycles

1 ,000 Cycles

1,000 Cycles

Biased 85/85 (5V)

225

NlA

1,000 Hours

1,000 Hours

Autoclave (121 0 C, 15psig)

150

N/A

336 Hours

336 Hours

Lead Integrity (DIP only)

9

N/A

N/A

End of Test

Solderability

9

N/A

N/A

End of Test

Physical Dimensions

6

N/A

N/A

End otTest

1. Required for new assembly technologies only.

7-3

New Package

II
I

Qualification Program
Reliability Monitor Program
The Reliability Monitor Program is designed to monitor all
fab and assembly facilities as well as each process technology in production. A summary of the program test and
sampling plan is shown below.

The Reliability Monitor Program provides for a periodic
reliability monitor of Lattice products. The program assures that all Lattice products comply on a continuing basis
with established reliability and quality levels.

Short Term Process Monitor (Bi-Weekly)
Test

#ofSamples

Duration

1250 C Operating Lifetest (6.50V)

70

160 Hours

1500 C Biased Retention Bake (5.25V)

70

160 Hours

Autoclave (121 0 C, 15psig)

35

160 Hours

# of Samples

Duration

1250 C Operating Lifetest (6.00V)

100

2000 Hours

1500 C Biased Retention Bake (5.25V)

150

2000 Hours

#ofSamples

Duration

Temperature Cycling (-65 to 1500 C)

50

1000 Cycles

85 0 C/85% RH

75

2000 Hours

Long Term Process Monitor (Monthly)
Test

Ongoing Package Monitor (Monthly)
Test

7-4

E2CMOS Testability
Improves Quality
Introduction
The inherent testability of Lattice's E2CMOS PLDs significantly improves their quality and reliability. By using
electrically erasable EEPROM technology to produce GAL,
pLSI and ispLSI devices, Lattice is able to perform 100%
AC/DC, functional, and parametric testing of every single
device. In order to achieve the highest quality levels,
Lattice programs and tests each device repeatedly throughout the manufacturing process.

Actual Test vs_ Simulated Test
Why is "actual tesf' so significant? PLDs, unlike most other
semiconductor devices, have a programmable element
that determines the final device functionality and AC/DC
performance. These programmable elements can be
fabricated from metal link fuses, programmable diodes or
transistors, volatile static RAM cells, UV EPROM cells or
electrically erasable EEPROM cells. Each of these technologies carries a different variability of programming
success and a variance in the impact of the programming
success on the performance and reliability of the device.
The most common programmable elements are the metal
fuse, EPROM cell and EEPROM cell. Of these element
types, only the EEPROM cell can be thoroughly tested by
the manufacturer prior to shipment to an end user OEM.

EEPROM Allows Actual Test
Each of the technologies identified above can be
programmed. In this manner they are all the same. The
differences become apparent when the erase times are
analyzed. Metal link and One-Time Programmable (OTP)
devices cannot be erased. UV EPROM devices can be
erased, however the time required is 20-30 minutes (in an
expensive windowed package). EEPROM devices, on the
other hand, offer instant erasability on the order of 50 ms
(thousandth's of a second). The advantage of this instant
erase for manufacturing test is significant. Instant erase
allows instant re-patterning for additional testing.

the test flexibility. Since the normal "user" programmable
elements cannot be programmed during manufacture (all
elements must be available for end-user programming) the
manufacturers of one-time programmable PLDs resort to
using simulated and correlated performance of test rows,
test columns and phantom or dummy-test arrays. At best,
this is a statistical measure ofthe actual device performance.
One need only look at the "normal" programming yield
fallout of 0.5 to 3% or the "acceptable" post-programming
test vector and board yield fallout of 0.5 to 2% to know that
this correlation is weak. The quality systems of today are
measuring defects in parts per million (PPM). A six sigma
program requires less than 3.4 PPM, four orders of
magnitude less than that achievable with non-testable
PLDs.

Actual Matrix Patterning
The unique capability of E2CMOS devices to be instantly
electrically erased allows these devices to be patterned
multiple times during Lattice's manufacturing test. Normal
array cells in the programmable matrix are patterned,
erased and tested again and again. The test rows or
columns, phantom arrays, etc., that are used with other
technologies are not necessary with E2CMOS devices.
Programmability of every cell is checked dozens of times.
Historically, the checking of a successful programming
operation consisted of no more than a pass/fail verification
step. This digital, go/no go check is not adequate to assure
that the cell is programmed properly with sufficient margin
to guarantee long-term reliable performance of the device.
Lattice E2CMOS devices are processed through a
proprietary cell verification step that consists of an analog
measure (to millivolt accuracy) of the actual cell threshold.
This capability is used for extensive reliability and quality
measurements and testing.

Worst Case AC/DC Testing

Other Methods Are Imprecise

A PLD does not have a defined function until the engineer
patterns the device with his custom pattern. The manufacturer, when considering the testing of a PLD, must consider
the hundreds of different architecture and functional variations that can be created by the end user. Each configuration
of architecture brings on a different set of worst case
pattern and stimulus conditions. Quick application of a
series of worst case patterns that cover all of the permutations of input combinations, array load and switching, and
output configuration is required.

All PLD devices must be tested to some degree to validate
functionality and performance. Technologies that are not
erasable or require lengthy erase times severely constrain

E2CMOS devices offer instant erasability to address this
reconfiguration and test problem. Testing each additional

EEPROM technology has been used for PLD manufacturing by Lattice for more than a decade. Lattice refers to their
high performance EEPROM technology as E2CMOS
technology. Extensive reliability studies of the technology
have been performed with industry-wide acceptance, including the military.

7-5

•

fE2CMOS Testability Improves Quality
worst case configuration takes fractions of a second,
allowing multiple patterns to be checked to assure performance to rated speeds. The final result is a device with
defects reduced from PP.!::! (parts per hundred) to PPM
(parts per million).

7-6

ISO 9000
Program
Introduction
Lattice is the first major PLD manufacturer to complete ISO
9000 registration. Lattice Quality Systems have been
certified, and the company is registered to the ISO 9000
standard. Lattice certification is for ISO 9001, the most
comprehensive of the various ISO 9000 levels, covering
the design, manufacturing, sales, and service functions.

ISO 9000 Certification
Certification to the ISO 9000 standard provides a recognized
and standardized basis for the continued development of
the quality and reliability of Lattice products. This certification
assures Lattice's customers that its Quality Systems are
well organized and embody a "Quality Firsf' philosophy. It
also reaffirms Lattice's promise to provide its customers
with the highest quality and most reliable products in the
industry.

What is ISO 9000?
The ISO 9000 series is an international version of British
Standard BS 5750, intended to define the quality
management systems for a wide range of an organization's

activities. The standard was initiated by the British Standards
Institution, which over the last 80 years has certified over
9,000 Quality Systems. Today, both the CEN (European
Committee for Standardization), which is commissioned to
coordinate quality standards in Europe and remove potential
trade restrictions within and outside the European
Community, and the USA Standard ANSI/ASQC have
adopted the ISO 9000 series.
Four quality standards make up the ISO 9000 series: ISO
9004, ISO 9003, ISO 9002, and ISO 9001. ISO 9004 is an
informational document containing guidelines for Quality
Management and Quality Systems. ISO 9003 guarantees
quality in a product's final testing and inspection. ISO 9002
confirms quality in the production and installation of a
product. ISO 9001 assures quality in a product's design,
development, production, and installation. ISO 9001 is
composed of 20 system sections, including the ISO 9002
and ISO 9003 subsets. Lattice is certified to the most
comprehensive quality standard of the series, ISO 9001,
and registered with the American Society for Quality
Control's Registration Accreditation Board.

Lattice Semiconductor: First PLD Supplier to Achieve ISO 9000 Certification

7-7

Notes

7-8

Section 1: Introduction
Section 2: High-Density Programmable Logic
Section 3: Low-Density Programmable Logic
Section 4: In-System Programmable Generic Digital Switch (ispGDS) Devices
Section 5: Military Program
Section 6: Development Tools
Section 7: Quality and Reliability
Section 8: General Information
Copying PAL, EPLD & PEEL Patterns into GAL Devices ..................... 8-1
GAL Product Line Cross Reference ..................................................... 8-3
Package Thermal Resistance ............................................................... 8-5
Tape and Reel Specifications ............................................................... 8-6
Package Diagrams ............................................................................... 8-7
Sales Offices ........................................................................................ 8-21

•
8-i

!

8-ii

Copying PAL, EPLD &PEEL
Patterns Into GAL Devices
INTRODUCTION
The generic/universal architectures of Lattice GAL devices
are able to emulate a wide variety of PAL, EPLD and
PEEL devices. GAL devices are direct functional and
parametric replacements for most PLD device
architectures. To use GAL devices in place of other PLD
types, some conversion of the original device pattern may
be needed. This conversion is not difficuh, and can be
accomplished at eitherthe design or manufacturing level.
The following sections describe several techniques
available to convert PAL, EPLD and PEEL device patterns
to Lattice GAL device patterns.

A GAL device may also be programmed from a master
PAL device by reading the pattem ofthe master PAL into
the programmer memory, then selecting the appropriate
RAL device or PAL type to cross-program from. The GAL
device can then be programmed from the programmer
memory.

CROSS PROGRAMMING: GAL16V8 AND GAL20V8
The GAL 16V8 and GAL20V8 devices replace most
standard 20-pin and 24-pin PAL devices. To simplify the
conversion process, Lattice has worked with programmer
hardware manufacturers to provide the ability to program
GAL devices directly from existing PAL JEDEC files, or
master PAL devices. Lattice qualified programmers can
automatically configure the architecture of a GAL device
to emulate the source PAL device.
To provide a conceptual framework for the conversion
from PAL devices to GAL devices, a mythical device
known as a RAL device was created. A RAL device is
simply a GAL device configured to emulate a PAL. There
is a one-to-one correspondence between the name of a
PAL device and that of a RAL device. For example, a
RAL16L8 is simply a GAL16V8 configured as a PAL 16L8.
Some programmers list the RAL device types as choices
for cross-programming, while others specifically state
that a cross-programming operation is to be performed
using a PAL device type as the architecture type. Other
programmers list devices such as a Lattice 16L8. Even
though Lattice does not make a 16L8 device, choosing
this selection allows the programmer to accept a 16L8
JEDEC file, and will program a GAL16V8 device to
emulate a PAL 16L8.
To program a GAL16V8 or GAL20V8 device from an
existing PAL JEDEC file, simply select the appropriate
device code (either RAL type, or PAL type to crossprogram from), then download the PAL JEDEC file to the
programmer. Insert the appropriate GAL device that can
directly emulate the PAL device (according to the chart in
the GAL 16V8 orGAL20V8 data sheets). Theprogrammer
will automatically configure the GAL device to emulate the
PAL device during programming. The resulting GAL
device is 100% compatible with the original PAL device.

8-1

CROSS PROGRAMMING: GAL22V10/GAL20RA10
The GAL22V1 0 and GAL20RA10 are direct replacements
for bipolar PAL devices, and are JEDEC fuse map
compatible with these industry standard devices. To
program a GAL22V10 or GAL20RA10 device from an
existing PAL JEDEC file, simply select the appropriate
GAL device code, then download the PAL JEDEC file to
the programmer. The resulting GAL device is 100%
compatible with the original PAL.
GAL devices also may be programmed from Master PAL
devices by reading the pattern of the Master PAL into the
programmer memory, then selecting the appropriate GAL
device code. The GAL device can then be programmed
from the programmer memory.
The GAL22V10 and GAL20RA10 also can store a User
Electronic Signature (seethe data sheets on these devices
for more information). To use this feature, the JEDEC file
must contain this information. To add the signature data
to the JEDEC map, use the PALtoGAL conversion utility
(see next section) or recompile the source equations for
a Lattice GAL device instead of a generic 22V10 type.
Many programmers list two device types to differentiate
between the two types of JEDEC files, and list both a
GAL22V10 and a name such as GAL22V10-UES or
GAL22V10-ES. Other programmers allow both types of
J EDEC files to be accepted, and simply don't program the
Signature fuses if they are not present in the file.
CROSS PROGRAMMING: GAL20XV10
The GAL20XV1 Ocan be configured asadirect replacement
for bipolar PAL20X10. 20X8. 20X4. and 20L10 devices.
Many programmers provide cross-programming support
similartothatprovidedfortheGAL 16V8IGAL20V8devices.
This allows the use of existing PAL device files to program
the GAL20XV10 to emulate the PAL devices. The
PALtoGAL conversion software (described below) also
supports conversion of the PAL JEDEC files to a
functionally equivalent GAL device file.
PALTOGAL CONVERSION UTILITY SOFTWARE
Lattice has created a software utility that will convert an
existing PAL device JEDEC file to the appropriate GAL

II
!

Copying PAL Patterns
Into GAL Devices
device JEDEC format. Called PALtoGAL, this software
utility can be used to convert PAL device files to GAL
device files, add/or change the User Electronic Signature
without changing device functionality, and reformat existing
GAL JEDEC files for readability.

contacting the GAL Applications Hotline at 1-800FASTGAL (327-8425) or (503) 693-0201. The software
also may be downloaded from Lattice's Electronic Bulletin
Board at (503) 693-0215; the file name is
"PALTOGAL.EXE".

Since a few programmable logic devices have features
that a GAL device cannot exactly emulate, the PALtoGAL
utility will clearly describe the incompatibility but will not
create an output file. GAL devices programmed using
files converted by PALtoGAL will be 100% compatible
with the original logic device. PALtoGAL is just another
method of cross-programming, and should produce the
same